diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml
index 4c3fd9a247..fb8209dbd3 100644
--- a/.github/workflows/nightly.yml
+++ b/.github/workflows/nightly.yml
@@ -33,11 +33,16 @@ jobs:
     env:
       CC: ${{ matrix.cc }}
       SSL: ${{ matrix.ssl }}
-      TFLAGS: ${{ matrix.select }} -DMQTT_LOCALHOST
+      TFLAGS: ${{ matrix.select }} -DMQTT_LOCALHOST -DNO_ABORT
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && test/setup_mqtt_server.sh && make -C test ${{ matrix.target }}
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} > log
+    - run: test/health.awk < log > json
+    - run: scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/linux_${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
   mip:
     runs-on: ubuntu-latest
     strategy:
@@ -54,11 +59,17 @@ jobs:
     env:
       CC: ${{ matrix.cc }}
       SSL: ${{ matrix.ssl }}
-      TFLAGS: -DMQTT_LOCALHOST
+      TFLAGS: -DMQTT_LOCALHOST -DNO_ABORT
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: if [ "${{ matrix.target }}" == "mip_tap_test" ]; then ./test/setup_ga_network.sh ; fi && sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && make -C test ${{ matrix.target }} IPV6=0
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: if [ "${{ matrix.target }}" == "mip_tap_test" ]; then ./test/setup_ga_network.sh ; fi && sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && make -C test ${{ matrix.target }} IPV6=0 > log
+    - run: test/health.awk < log > json
+    - run: scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_$(date +"%Y%m%d").json"
+
   mip89:
     runs-on: ubuntu-latest
     strategy:
@@ -151,9 +162,15 @@ jobs:
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: brew install mbedtls wolfssl mosquitto # jq openssl already pre-installed
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: brew install mbedtls wolfssl mosquitto gawk # jq openssl already pre-installed
     - run: /opt/homebrew/opt/mosquitto/sbin/mosquitto -c /Users/runner/work/mongoose/mongoose/test/mosquitto.conf.macos &
-    - run: make -C test test ASAN_OPTIONS= MBEDTLS=$(echo $(brew --cellar)/mbedtls*/*) OPENSSL=$(echo $(brew --cellar)/openssl*/*) WOLFSSL=$(echo $(brew --cellar)/wolfssl*/*)
+    - run: make -C test test ASAN_OPTIONS= MBEDTLS=$(echo $(brew --cellar)/mbedtls*/*) OPENSSL=$(echo $(brew --cellar)/openssl*/*) WOLFSSL=$(echo $(brew --cellar)/wolfssl*/*) > log
+    - run: test/health.awk < log > json
+    - run: scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/macos_test_cc_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
+
   windows:
     runs-on: ubuntu-latest
     strategy:
@@ -173,7 +190,13 @@ jobs:
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: ./test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} 
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: ./test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} > log
+    - run: test/health.awk < log > json
+    - run: scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/windows_${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
+ 
   arm:
     runs-on: ubuntu-latest
     strategy:
@@ -204,9 +227,15 @@ jobs:
     name: tutorials ${{ matrix.ssl }}
     steps:
     - uses: actions/checkout@v4
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
     - run: sudo apt -y install libpcap-dev
-    - run: make -C test tutorials CFLAGS_EXTRA="${{ matrix.ssl }}"
+    - run: make -C test tutorials CFLAGS_EXTRA="${{ matrix.ssl }}" > log
+    - run: test/health.awk < log > json
+    - run: scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/tutorials_${{ matrix.ssl }}_$(date +"%Y%m%d").json"
     - run: make -C test clean_tutorials
+
   tutorials_win:
     runs-on: windows-latest
     strategy:
@@ -466,9 +495,9 @@ jobs:
     - run: make -C tutorials/stm32/nucleo-f746zg-make-freertos-tcp test VCON_API_KEY=${{secrets.VCON_API_KEY}}
     - name: Cube
       run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
-    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
+    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
 
   test_f4:
     runs-on: ubuntu-latest
@@ -481,9 +510,9 @@ jobs:
     - run: make -C tutorials/stm32/nucleo-f429zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
     - name: Cube
       run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
-    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
 
   test_h743:
     runs-on: ubuntu-latest
@@ -496,8 +525,8 @@ jobs:
     - run: make -C tutorials/stm32/nucleo-h743zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #    - name: Cube
 #      run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
 
   test_h723:
     runs-on: ubuntu-latest
diff --git a/mongoose.c b/mongoose.c
index 7b616508e7..26ac7a2c35 100644
--- a/mongoose.c
+++ b/mongoose.c
@@ -2608,6 +2608,7 @@ int mg_iobuf_resize(struct mg_iobuf *io, size_t new_size) {
       mg_free(io->buf);
       io->buf = (unsigned char *) p;
       io->size = new_size;
+      io->len = len;
     } else {
       ok = 0;
       MG_ERROR(("%lld->%lld", (uint64_t) io->size, (uint64_t) new_size));
@@ -4157,6 +4158,7 @@ void mg_mgr_init(struct mg_mgr *mgr) {
 #endif
 
 
+
 #if MG_ENABLE_TCPIP
 #define MG_EPHEMERAL_PORT_BASE 32768
 #define PDIFF(a, b) ((size_t) (((char *) (b)) - ((char *) (a))))
@@ -4205,7 +4207,7 @@ struct eth {
 struct ip {
   uint8_t ver;    // Version
   uint8_t tos;    // Unused
-  uint16_t len;   // Length
+  uint16_t len;   // Datagram length
   uint16_t id;    // Unused
   uint16_t frag;  // Fragmentation
 #define IP_FRAG_OFFSET_MSK 0x1fff
@@ -4218,13 +4220,13 @@ struct ip {
 };
 
 struct ip6 {
-  uint8_t ver;      // Version
-  uint8_t opts[3];  // Options
-  uint16_t len;     // Length
-  uint8_t proto;    // Upper level protocol
-  uint8_t ttl;      // Time to live
-  uint8_t src[16];  // Source IP
-  uint8_t dst[16];  // Destination IP
+  uint8_t ver;       // Version
+  uint8_t label[3];  // Flow label
+  uint16_t plen;     // Payload length
+  uint8_t next;      // Upper level protocol
+  uint8_t hops;      // Hop limit
+  uint8_t src[16];   // Source IP
+  uint8_t dst[16];   // Destination IP
 };
 
 struct icmp {
@@ -4233,6 +4235,12 @@ struct icmp {
   uint16_t csum;
 };
 
+struct icmp6 {
+  uint8_t type;
+  uint8_t code;
+  uint16_t csum;
+};
+
 struct arp {
   uint16_t fmt;    // Format of hardware address
   uint16_t pro;    // Format of protocol address
@@ -4282,6 +4290,14 @@ struct dhcp {
   uint8_t options[30 + sizeof(((struct mg_tcpip_if *) 0)->dhcp_name)];
 };
 
+struct dhcp6 {
+  union {
+    uint8_t type;
+    uint32_t xid;
+  };
+  uint8_t options[30 + sizeof(((struct mg_tcpip_if *) 0)->dhcp_name)];
+};
+
 #pragma pack(pop)
 
 struct pkt {
@@ -4293,12 +4309,33 @@ struct pkt {
   struct ip *ip;
   struct ip6 *ip6;
   struct icmp *icmp;
+  struct icmp6 *icmp6;
   struct tcp *tcp;
   struct udp *udp;
   struct dhcp *dhcp;
+  struct dhcp6 *dhcp6;
 };
 
 static void mg_tcpip_call(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+#if MG_ENABLE_PROFILE
+  const char *names[] = {
+  "TCPIP_EV_ST_CHG",
+  "TCPIP_EV_DHCP_DNS",
+  "TCPIP_EV_DHCP_SNTP",
+  "TCPIP_EV_ARP",
+  "TCPIP_EV_TIMER_1S",
+  "TCPIP_EV_WIFI_SCAN_RESULT",
+  "TCPIP_EV_WIFI_SCAN_END",
+  "TCPIP_EV_WIFI_CONNECT_ERR",
+  "TCPIP_EV_DRIVER",
+  "TCPIP_EV_USER" 
+  };
+  if (ev != MG_TCPIP_EV_POLL && ev < (int) (sizeof(names) / sizeof(names[0]))) {
+    MG_PROF_ADD(c, names[ev]);
+  }
+#endif
+  // Fire protocol handler first, user handler second. See #2559
+  if (ifp->pfn != NULL) ifp->pfn(ifp, ev, ev_data);
   if (ifp->fn != NULL) ifp->fn(ifp, ev, ev_data);
 }
 
@@ -4306,7 +4343,7 @@ static void send_syn(struct mg_connection *c);
 
 static void mkpay(struct pkt *pkt, void *p) {
   pkt->pay =
-      mg_str_n((char *) p, (size_t) (&pkt->raw.buf[pkt->raw.len] - (char *) p));
+      mg_str_n((char *) p, (size_t) (&pkt->pay.buf[pkt->pay.len] - (char *) p));
 }
 
 static uint32_t csumup(uint32_t sum, const void *buf, size_t len) {
@@ -4569,7 +4606,7 @@ static void rx_dhcp_client(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   uint8_t msgtype = 0, state = ifp->state;
   // perform size check first, then access fields
   uint8_t *p = pkt->dhcp->options,
-          *end = (uint8_t *) &pkt->raw.buf[pkt->raw.len];
+          *end = (uint8_t *) &pkt->pay.buf[pkt->pay.len];
   if (end < (uint8_t *) (pkt->dhcp + 1)) return;
   if (memcmp(&pkt->dhcp->xid, ifp->mac + 2, sizeof(pkt->dhcp->xid))) return;
   while (p + 1 < end && p[0] != 255) {  // Parse options RFC-1533 #9
@@ -4629,7 +4666,7 @@ static void rx_dhcp_client(struct mg_tcpip_if *ifp, struct pkt *pkt) {
 // Simple DHCP server that assigns a next IP address: ifp->ip + 1
 static void rx_dhcp_server(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   uint8_t op = 0, *p = pkt->dhcp->options,
-          *end = (uint8_t *) &pkt->raw.buf[pkt->raw.len];
+          *end = (uint8_t *) &pkt->pay.buf[pkt->pay.len];
   // struct dhcp *req = pkt->dhcp;
   struct dhcp res = {2, 1, 6, 0, 0, 0, 0, 0, 0, 0, 0, {0}, 0, {0}};
   if (end < (uint8_t *) (pkt->dhcp + 1)) return;
@@ -4666,26 +4703,25 @@ static void rx_dhcp_server(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   }
 }
 
-static void rx_udp(struct mg_tcpip_if *ifp, struct pkt *pkt) {
+static bool rx_udp(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   struct mg_connection *c = getpeer(ifp->mgr, pkt, true);
-  if (c == NULL) {
-    // No UDP listener on this port. Should send ICMP, but keep silent.
+  struct connstate *s;
+  if (c == NULL) return false;  // No UDP listener on this port
+  s = (struct connstate *) (c + 1);
+  c->rem.port = pkt->udp->sport;
+  memcpy(c->rem.ip, &pkt->ip->src, sizeof(uint32_t));
+  memcpy(s->mac, pkt->eth->src, sizeof(s->mac));
+  if (c->recv.len >= MG_MAX_RECV_SIZE) {
+    mg_error(c, "max_recv_buf_size reached");
+  } else if (c->recv.size - c->recv.len < pkt->pay.len &&
+             !mg_iobuf_resize(&c->recv, c->recv.len + pkt->pay.len)) {
+    mg_error(c, "oom");
   } else {
-    struct connstate *s = (struct connstate *) (c + 1);
-    c->rem.port = pkt->udp->sport;
-    memcpy(c->rem.ip, &pkt->ip->src, sizeof(uint32_t));
-    memcpy(s->mac, pkt->eth->src, sizeof(s->mac));
-    if (c->recv.len >= MG_MAX_RECV_SIZE) {
-      mg_error(c, "max_recv_buf_size reached");
-    } else if (c->recv.size - c->recv.len < pkt->pay.len &&
-               !mg_iobuf_resize(&c->recv, c->recv.len + pkt->pay.len)) {
-      mg_error(c, "oom");
-    } else {
-      memcpy(&c->recv.buf[c->recv.len], pkt->pay.buf, pkt->pay.len);
-      c->recv.len += pkt->pay.len;
-      mg_call(c, MG_EV_READ, &pkt->pay.len);
-    }
+    memcpy(&c->recv.buf[c->recv.len], pkt->pay.buf, pkt->pay.len);
+    c->recv.len += pkt->pay.len;
+    mg_call(c, MG_EV_READ, &pkt->pay.len);
   }
+  return true;
 }
 
 static size_t tx_tcp(struct mg_tcpip_if *ifp, uint8_t *dst_mac, uint32_t dst_ip,
@@ -4725,17 +4761,20 @@ static size_t tx_tcp(struct mg_tcpip_if *ifp, uint8_t *dst_mac, uint32_t dst_ip,
   MG_VERBOSE(("TCP %M:%hu -> %M:%hu fl %x len %u", mg_print_ip4, &ip->src,
               mg_ntohs(tcp->sport), mg_print_ip4, &ip->dst,
               mg_ntohs(tcp->dport), tcp->flags, len));
-  // mg_hexdump(ifp->tx.buf, PDIFF(ifp->tx.buf, tcp + 1) + len);
   return ether_output(ifp, PDIFF(ifp->tx.buf, tcp + 1) + len);
 }
 
-static size_t tx_tcp_pkt(struct mg_tcpip_if *ifp, struct pkt *pkt,
-                         uint8_t flags, uint32_t seq, const void *buf,
-                         size_t len) {
-  uint32_t delta = (pkt->tcp->flags & (TH_SYN | TH_FIN)) ? 1 : 0;
+static size_t tx_tcp_ctrlresp(struct mg_tcpip_if *ifp, struct pkt *pkt,
+                              uint8_t flags, uint32_t seqno) {
+  uint32_t ackno = mg_htonl(mg_ntohl(pkt->tcp->seq) + (uint32_t) pkt->pay.len +
+                            ((pkt->tcp->flags & (TH_SYN | TH_FIN)) ? 1 : 0));
   return tx_tcp(ifp, pkt->eth->src, pkt->ip->src, flags, pkt->tcp->dport,
-                pkt->tcp->sport, seq, mg_htonl(mg_ntohl(pkt->tcp->seq) + delta),
-                buf, len);
+                pkt->tcp->sport, seqno, ackno, NULL, 0);
+}
+
+static size_t tx_tcp_rst(struct mg_tcpip_if *ifp, struct pkt *pkt, bool toack) {
+  return tx_tcp_ctrlresp(ifp, pkt, toack ? TH_RST : (TH_RST | TH_ACK),
+                         toack ? pkt->tcp->ack : 0);
 }
 
 static struct mg_connection *accept_conn(struct mg_connection *lsn,
@@ -4799,7 +4838,7 @@ static size_t trim_len(struct mg_connection *c, size_t len) {
 long mg_io_send(struct mg_connection *c, const void *buf, size_t len) {
   struct mg_tcpip_if *ifp = c->mgr->ifp;
   struct connstate *s = (struct connstate *) (c + 1);
-  uint32_t dst_ip = *(uint32_t *) c->rem.ip;
+  uint32_t dst_ip = c->rem.ip4;
   len = trim_len(c, len);
   if (c->is_udp) {
     if (!tx_udp(ifp, s->mac, ifp->ip, c->loc.port, dst_ip, c->rem.port, buf,
@@ -4846,8 +4885,7 @@ static void read_conn(struct mg_connection *c, struct pkt *pkt) {
   struct connstate *s = (struct connstate *) (c + 1);
   struct mg_iobuf *io = c->is_tls ? &c->rtls : &c->recv;
   uint32_t seq = mg_ntohl(pkt->tcp->seq);
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   if (pkt->tcp->flags & TH_FIN) {
     uint8_t flags = TH_ACK;
     if (mg_ntohl(pkt->tcp->seq) != s->ack) {
@@ -4934,10 +4972,9 @@ static void read_conn(struct mg_connection *c, struct pkt *pkt) {
   }
 }
 
-
 // TCP backlog
 struct mg_backlog {
-  uint16_t port, mss; // use port=0 for available entries
+  uint16_t port, mss;  // use port=0 for available entries
   uint8_t age;
 };
 
@@ -4947,7 +4984,7 @@ static int backlog_insert(struct mg_connection *c, uint16_t port,
   size_t i;
   for (i = 0; i < sizeof(c->data) / sizeof(*p); i++) {
     if (p[i].port != 0) continue;
-    p[i].age = 2; // remove after two calls, average 1.5 call rate
+    p[i].age = 2;  // remove after two calls, average 1.5 call rate
     p[i].port = port, p[i].mss = mss;
     return (int) i;
   }
@@ -4970,7 +5007,7 @@ static void backlog_remove(struct mg_connection *c, uint16_t key) {
 
 static void backlog_maintain(struct mg_connection *c) {
   struct mg_backlog *p = (struct mg_backlog *) c->data;
-  size_t i; // dec age and remove those where it reaches 0
+  size_t i;  // dec age and remove those where it reaches 0
   for (i = 0; i < sizeof(c->data) / sizeof(*p); i++) {
     if (p[i].port == 0) continue;
     if (p[i].age != 0) --p[i].age;
@@ -5007,88 +5044,108 @@ static void handle_opt(struct connstate *s, struct tcp *tcp) {
 static void rx_tcp(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   struct mg_connection *c = getpeer(ifp->mgr, pkt, false);
   struct connstate *s = c == NULL ? NULL : (struct connstate *) (c + 1);
-#if 0
-  MG_INFO(("%lu %hhu %d", c ? c->id : 0, pkt->tcp->flags, (int) pkt->pay.len));
-#endif
+  // Order is VERY important; RFC-9293 3.5.2
+  // - check clients (Group 1) and established connections (Group 3)
   if (c != NULL && c->is_connecting && pkt->tcp->flags == (TH_SYN | TH_ACK)) {
+    // client got a server connection accept
     handle_opt(s, pkt->tcp);  // process options (MSS)
     s->seq = mg_ntohl(pkt->tcp->ack), s->ack = mg_ntohl(pkt->tcp->seq) + 1;
-    tx_tcp_pkt(ifp, pkt, TH_ACK, pkt->tcp->ack, NULL, 0);
+    tx_tcp_ctrlresp(ifp, pkt, TH_ACK, pkt->tcp->ack);
     c->is_connecting = 0;  // Client connected
     settmout(c, MIP_TTYPE_KEEPALIVE);
     mg_call(c, MG_EV_CONNECT, NULL);  // Let user know
     if (c->is_tls_hs) mg_tls_handshake(c);
     if (!c->is_tls_hs) c->is_tls = 0;  // user did not call mg_tls_init()
   } else if (c != NULL && c->is_connecting && pkt->tcp->flags != TH_ACK) {
-    // mg_hexdump(pkt->raw.buf, pkt->raw.len);
-    tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
+    mg_error(c, "connection refused");
   } else if (c != NULL && pkt->tcp->flags & TH_RST) {
+    // TODO(): validate RST is within window (and optional with proper ACK)
     mg_error(c, "peer RST");  // RFC-1122 4.2.2.13
   } else if (c != NULL) {
-#if 0
-    MG_DEBUG(("%lu %d %M:%hu -> %M:%hu", c->id, (int) pkt->raw.len,
-              mg_print_ip4, &pkt->ip->src, mg_ntohs(pkt->tcp->sport),
-              mg_print_ip4, &pkt->ip->dst, mg_ntohs(pkt->tcp->dport)));
-    mg_hexdump(pkt->pay.buf, pkt->pay.len);
-#endif
+    // process segment
     s->tmiss = 0;                         // Reset missed keep-alive counter
     if (s->ttype == MIP_TTYPE_KEEPALIVE)  // Advance keep-alive timer
       settmout(c,
                MIP_TTYPE_KEEPALIVE);  // unless a former ACK timeout is pending
     read_conn(c, pkt);  // Override timer with ACK timeout if needed
-  } else if ((c = getpeer(ifp->mgr, pkt, true)) == NULL) {
-    tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
-  } else if (pkt->tcp->flags & TH_RST) {
-    if (c->is_accepted) mg_error(c, "peer RST");  // RFC-1122 4.2.2.13
-    // ignore RST if not connected
-  } else if (pkt->tcp->flags & TH_SYN) {
-    struct connstate cs;  // At this point, s = NULL, there is no connection
-    int key;
-    uint32_t isn;
-    if (pkt->tcp->sport != 0) {
-      handle_opt(&cs, pkt->tcp);                          // process options (MSS)
-      key = backlog_insert(c, pkt->tcp->sport, cs.dmss);  // backlog options (MSS)
-      if (key < 0) return;  // no room in backlog, discard SYN, client retries
-      // Use peer's src port and bl key as ISN, to later identify the handshake
-      isn = (mg_htonl(((uint32_t)key << 16) | mg_ntohs(pkt->tcp->sport)));
-      tx_tcp_pkt(ifp, pkt, TH_SYN | TH_ACK, isn, NULL, 0);
-    } // what should we do when port=0 ? Linux takes port 0 as any other port
-  } else if (pkt->tcp->flags & TH_FIN) {
-    tx_tcp_pkt(ifp, pkt, TH_FIN | TH_ACK, pkt->tcp->ack, NULL, 0);
-  } else if ((uint16_t) (mg_htonl(pkt->tcp->ack) - 1) ==
-             mg_htons(pkt->tcp->sport)) {
-    uint16_t key = (uint16_t) ((mg_htonl(pkt->tcp->ack) - 1) >> 16);
-    struct mg_backlog *b = backlog_retrieve(c, key, pkt->tcp->sport);
-    if (b != NULL) {
-      accept_conn(c, pkt, b->mss);  // pass options
-      backlog_remove(c, key);
-    } else if (!c->is_accepted) {         // not an actual match, reset
-      tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
-      // TODO(scaprile): revisit this and below, weird scenarios
-    }
-  } else if (!c->is_accepted) {  // no peer
-    tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
-  } else {
-    // MG_VERBOSE(("dropped silently.."));
-  }
+  } else
+    // - we don't listen on that port; RFC-9293 3.5.2 Group 1
+    // - check listening connections; RFC-9293 3.5.2 Group 2
+    if ((c = getpeer(ifp->mgr, pkt, true)) == NULL) {
+      // not listening on that port
+      if (!(pkt->tcp->flags & TH_RST)) {
+        tx_tcp_rst(ifp, pkt, pkt->tcp->flags & TH_ACK);
+      }  // else silently discard
+    } else if (pkt->tcp->flags == TH_SYN) {
+      // listener receives a connection request
+      struct connstate cs;  // At this point, s = NULL, there is no connection
+      int key;
+      uint32_t isn;
+      if (pkt->tcp->sport != 0) {
+        handle_opt(&cs, pkt->tcp);  // process options (MSS)
+        key = backlog_insert(c, pkt->tcp->sport,
+                             cs.dmss);  // backlog options (MSS)
+        if (key < 0) return;  // no room in backlog, discard SYN, client retries
+        // Use peer's src port and bl key as ISN, to later identify the
+        // handshake
+        isn = (mg_htonl(((uint32_t) key << 16) | mg_ntohs(pkt->tcp->sport)));
+        tx_tcp_ctrlresp(ifp, pkt, TH_SYN | TH_ACK, isn);
+      }  // what should we do when port=0 ? Linux takes port 0 as any other
+         // port
+    } else if (pkt->tcp->flags == TH_ACK) {
+      // listener receives an ACK
+      struct mg_backlog *b = NULL;
+      if ((uint16_t) (mg_htonl(pkt->tcp->ack) - 1) ==
+          mg_htons(pkt->tcp->sport)) {
+        uint16_t key = (uint16_t) ((mg_htonl(pkt->tcp->ack) - 1) >> 16);
+        b = backlog_retrieve(c, key, pkt->tcp->sport);
+        if (b != NULL) {                // ACK is a response to a SYN+ACK
+          accept_conn(c, pkt, b->mss);  // pass options
+          backlog_remove(c, key);
+        }  // else not an actual match, reset
+      }
+      if (b == NULL) tx_tcp_rst(ifp, pkt, true);
+    } else if (pkt->tcp->flags & TH_RST) {
+      // silently discard
+    } else if (pkt->tcp->flags & TH_ACK) {  // ACK + something else != RST
+      tx_tcp_rst(ifp, pkt, true);
+    } else if (pkt->tcp->flags & TH_SYN) {  // SYN + something else != ACK
+      tx_tcp_rst(ifp, pkt, false);
+    }  // else  silently discard
 }
 
 static void rx_ip(struct mg_tcpip_if *ifp, struct pkt *pkt) {
-  uint16_t frag = mg_ntohs(pkt->ip->frag);
+  uint8_t ihl;
+  uint16_t frag, len;
+  if (pkt->pay.len < sizeof(*pkt->ip)) return;  // Truncated
+  if ((pkt->ip->ver >> 4) != 4) return;         // Not IP
+  ihl = pkt->ip->ver & 0x0F;
+  if (ihl < 5) return;                     // bad IHL
+  if (pkt->pay.len < (ihl * 4)) return;    // Truncated / malformed
+  // There can be link padding, take length from IP header
+  len = mg_ntohs(pkt->ip->len); // IP datagram length
+  if (len < (ihl * 4) || len > pkt->pay.len) return; // malformed
+  pkt->pay.len = len; // strip padding
+  mkpay(pkt, (uint32_t *) pkt->ip + ihl);  // account for opts
+  frag = mg_ntohs(pkt->ip->frag);
   if (frag & IP_MORE_FRAGS_MSK || frag & IP_FRAG_OFFSET_MSK) {
     struct mg_connection *c;
-    if (pkt->ip->proto == 17) pkt->udp = (struct udp *) (pkt->ip + 1);
-    if (pkt->ip->proto == 6) pkt->tcp = (struct tcp *) (pkt->ip + 1);
+    if (pkt->ip->proto == 17) pkt->udp = (struct udp *) (pkt->pay.buf);
+    if (pkt->ip->proto == 6) pkt->tcp = (struct tcp *) (pkt->pay.buf);
     c = getpeer(ifp->mgr, pkt, false);
     if (c) mg_error(c, "Received fragmented packet");
   } else if (pkt->ip->proto == 1) {
-    pkt->icmp = (struct icmp *) (pkt->ip + 1);
+    pkt->icmp = (struct icmp *) (pkt->pay.buf);
     if (pkt->pay.len < sizeof(*pkt->icmp)) return;
     mkpay(pkt, pkt->icmp + 1);
     rx_icmp(ifp, pkt);
   } else if (pkt->ip->proto == 17) {
-    pkt->udp = (struct udp *) (pkt->ip + 1);
-    if (pkt->pay.len < sizeof(*pkt->udp)) return;
+    pkt->udp = (struct udp *) (pkt->pay.buf);
+    if (pkt->pay.len < sizeof(*pkt->udp)) return; // truncated
+    // Take length from UDP header
+    len = mg_ntohs(pkt->udp->len); // UDP datagram length
+    if (len < sizeof(*pkt->udp) || len > pkt->pay.len) return; // malformed
+    pkt->pay.len = len; // strip excess data
     mkpay(pkt, pkt->udp + 1);
     MG_VERBOSE(("UDP %M:%hu -> %M:%hu len %u", mg_print_ip4, &pkt->ip->src,
                 mg_ntohs(pkt->udp->sport), mg_print_ip4, &pkt->ip->dst,
@@ -5101,47 +5158,115 @@ static void rx_ip(struct mg_tcpip_if *ifp, struct pkt *pkt) {
       pkt->dhcp = (struct dhcp *) (pkt->udp + 1);
       mkpay(pkt, pkt->dhcp + 1);
       rx_dhcp_server(ifp, pkt);
-    } else {
-      rx_udp(ifp, pkt);
+    } else if (!rx_udp(ifp, pkt)) {
+      // Should send ICMP Destination Unreachable for unicasts, but keep silent
     }
   } else if (pkt->ip->proto == 6) {
-    uint16_t iplen, off;
-    pkt->tcp = (struct tcp *) (pkt->ip + 1);
+    uint8_t off;
+    pkt->tcp = (struct tcp *) (pkt->pay.buf);
     if (pkt->pay.len < sizeof(*pkt->tcp)) return;
-    mkpay(pkt, pkt->tcp + 1);
-    iplen = mg_ntohs(pkt->ip->len);
-    off = (uint16_t) (sizeof(*pkt->ip) + ((pkt->tcp->off >> 4) * 4U));
-    if (iplen >= off) pkt->pay.len = (size_t) (iplen - off);
+    off = pkt->tcp->off >> 4;  // account for opts
+    if (pkt->pay.len < (4 * off)) return;
+    mkpay(pkt, (uint32_t *) pkt->tcp + off);
     MG_VERBOSE(("TCP %M:%hu -> %M:%hu len %u", mg_print_ip4, &pkt->ip->src,
                 mg_ntohs(pkt->tcp->sport), mg_print_ip4, &pkt->ip->dst,
                 mg_ntohs(pkt->tcp->dport), (int) pkt->pay.len));
     rx_tcp(ifp, pkt);
+  } else {
+    MG_DEBUG(("Unknown IP proto %x", (int) pkt->ip->proto));
+    if (mg_log_level >= MG_LL_VERBOSE)
+      mg_hexdump(pkt->ip, pkt->pay.len >= 32 ? 32 : pkt->pay.len);
   }
 }
 
 static void rx_ip6(struct mg_tcpip_if *ifp, struct pkt *pkt) {
-  // MG_DEBUG(("IP %d", (int) len));
-  if (pkt->ip6->proto == 1 || pkt->ip6->proto == 58) {
-    pkt->icmp = (struct icmp *) (pkt->ip6 + 1);
-    if (pkt->pay.len < sizeof(*pkt->icmp)) return;
-    mkpay(pkt, pkt->icmp + 1);
-    rx_icmp(ifp, pkt);
-  } else if (pkt->ip6->proto == 17) {
-    pkt->udp = (struct udp *) (pkt->ip6 + 1);
+  uint16_t len = 0;
+  uint8_t next, *nhdr;
+  bool loop = true;
+  if (pkt->pay.len < sizeof(*pkt->ip6)) return;  // Truncated
+  if ((pkt->ip6->ver >> 4) != 0x6) return;       // Not IPv6
+  next = pkt->ip6->next;
+  nhdr = (uint8_t *) (pkt->ip6 + 1);
+  while (loop) {
+    switch (next) {
+      case 0:   // Hop-by-Hop 4.3
+      case 43:  // Routing 4.4
+      case 60:  // Destination Options 4.6
+      case 51:  // Authentication RFC-4302
+        MG_INFO(("IPv6 extension header %d", (int) next));
+        next = nhdr[0];
+        len += (uint16_t)(8 * (nhdr[1] + 1));
+        nhdr += 8 * (nhdr[1] + 1);
+        break;
+      case 44:  // Fragment 4.5
+      {
+        struct mg_connection *c;
+        if (nhdr[0] == 17) pkt->udp = (struct udp *) (pkt->pay.buf);
+        if (nhdr[0] == 6) pkt->tcp = (struct tcp *) (pkt->pay.buf);
+        c = getpeer(ifp->mgr, pkt, false);
+        if (c) mg_error(c, "Received fragmented packet");
+      }
+        return;
+      case 59:  // No Next Header 4.7
+        return;
+      case 50:  // IPsec ESP RFC-4303, unsupported
+      default:
+        loop = false;
+        break;
+    }
+  }
+  // There can be link padding, take payload length from IPv6 header - options
+  pkt->pay.buf = (char *) nhdr;
+  pkt->pay.len = mg_ntohs(pkt->ip6->plen) - len;
+  if (next == 58) {
+    pkt->icmp6 = (struct icmp6 *) (pkt->pay.buf);
+    if (pkt->pay.len < sizeof(*pkt->icmp6)) return;
+    mkpay(pkt, pkt->icmp6 + 1);
+    MG_DEBUG(("ICMPv6 %M -> %M len %u", mg_print_ip6, &pkt->ip6->src,
+              mg_print_ip6, &pkt->ip6->dst, (int) pkt->pay.len));
+    // rx_icmp6(ifp, pkt);
+  } else if (next == 17) {
+    pkt->udp = (struct udp *) (pkt->pay.buf);
     if (pkt->pay.len < sizeof(*pkt->udp)) return;
-    // MG_DEBUG(("  UDP %u %u -> %u", len, mg_htons(udp->sport),
-    // mg_htons(udp->dport)));
     mkpay(pkt, pkt->udp + 1);
+    MG_DEBUG(("UDP %M:%hu -> %M:%hu len %u", mg_print_ip6, &pkt->ip6->src,
+              mg_ntohs(pkt->udp->sport), mg_print_ip6, &pkt->ip6->dst,
+              mg_ntohs(pkt->udp->dport), (int) pkt->pay.len));
+    if (ifp->enable_dhcp_client && pkt->udp->dport == mg_htons(546)) {
+      pkt->dhcp6 = (struct dhcp6 *) (pkt->udp + 1);
+      mkpay(pkt, pkt->dhcp6 + 1);
+      // rx_dhcp6_client(ifp, pkt);
+    } else if (ifp->enable_dhcp_server && pkt->udp->dport == mg_htons(547)) {
+      pkt->dhcp6 = (struct dhcp6 *) (pkt->udp + 1);
+      mkpay(pkt, pkt->dhcp6 + 1);
+      // rx_dhcp6_server(ifp, pkt);
+    } else if (!rx_udp(ifp, pkt)) {
+      // Should send ICMPv6 Destination Unreachable for unicasts, keep silent
+    }
+  } else if (next == 6) {
+    uint8_t off;
+    pkt->tcp = (struct tcp *) (pkt->pay.buf);
+    if (pkt->pay.len < sizeof(*pkt->tcp)) return;
+    off = pkt->tcp->off >> 4;  // account for opts
+    if (pkt->pay.len < sizeof(*pkt->tcp) + 4 * off) return;
+    mkpay(pkt, (uint32_t *) pkt->tcp + off);
+    MG_DEBUG(("TCP %M:%hu -> %M:%hu len %u", mg_print_ip6, &pkt->ip6->src,
+              mg_ntohs(pkt->tcp->sport), mg_print_ip6, &pkt->ip6->dst,
+              mg_ntohs(pkt->tcp->dport), (int) pkt->pay.len));
+    rx_tcp(ifp, pkt);
+  } else {
+    MG_DEBUG(("Unknown IPv6 next hdr %x", (int) next));
+    if (mg_log_level >= MG_LL_VERBOSE)
+      mg_hexdump(pkt->ip6, pkt->pay.len >= 32 ? 32 : pkt->pay.len);
   }
 }
 
 static void mg_tcpip_rx(struct mg_tcpip_if *ifp, void *buf, size_t len) {
   struct pkt pkt;
   memset(&pkt, 0, sizeof(pkt));
-  pkt.raw.buf = (char *) buf;
-  pkt.raw.len = len;
-  pkt.eth = (struct eth *) buf;
-  // mg_hexdump(buf, len > 16 ? 16: len);
+  pkt.pay.buf = pkt.raw.buf = (char *) buf;
+  pkt.pay.len = pkt.raw.len = len; // payload = raw
+  pkt.eth = (struct eth *) buf;   // Ethernet = raw
   if (pkt.raw.len < sizeof(*pkt.eth)) return;  // Truncated - runt?
   if (ifp->enable_mac_check &&
       memcmp(pkt.eth->dst, ifp->mac, sizeof(pkt.eth->dst)) != 0 &&
@@ -5152,28 +5277,19 @@ static void mg_tcpip_rx(struct mg_tcpip_if *ifp, void *buf, size_t len) {
     len -= 4;  // TODO(scaprile): check on bigendian
     crc = mg_crc32(0, (const char *) buf, len);
     if (memcmp((void *) ((size_t) buf + len), &crc, sizeof(crc))) return;
+    pkt.pay.len = len;
   }
+  mkpay(&pkt, pkt.eth + 1);
   if (pkt.eth->type == mg_htons(0x806)) {
-    pkt.arp = (struct arp *) (pkt.eth + 1);
-    if (sizeof(*pkt.eth) + sizeof(*pkt.arp) > pkt.raw.len) return;  // Truncated
+    pkt.arp = (struct arp *) (pkt.pay.buf);
+    if (pkt.pay.len < sizeof(*pkt.arp)) return; // Truncated
     mg_tcpip_call(ifp, MG_TCPIP_EV_ARP, &pkt.raw);
     rx_arp(ifp, &pkt);
   } else if (pkt.eth->type == mg_htons(0x86dd)) {
-    pkt.ip6 = (struct ip6 *) (pkt.eth + 1);
-    if (pkt.raw.len < sizeof(*pkt.eth) + sizeof(*pkt.ip6)) return;  // Truncated
-    if ((pkt.ip6->ver >> 4) != 0x6) return;                         // Not IP
-    mkpay(&pkt, pkt.ip6 + 1);
+    pkt.ip6 = (struct ip6 *) (pkt.pay.buf);
     rx_ip6(ifp, &pkt);
   } else if (pkt.eth->type == mg_htons(0x800)) {
-    pkt.ip = (struct ip *) (pkt.eth + 1);
-    if (pkt.raw.len < sizeof(*pkt.eth) + sizeof(*pkt.ip)) return;  // Truncated
-    // Truncate frame to what IP header tells us
-    if ((size_t) mg_ntohs(pkt.ip->len) + sizeof(struct eth) < pkt.raw.len) {
-      pkt.raw.len = (size_t) mg_ntohs(pkt.ip->len) + sizeof(struct eth);
-    }
-    if (pkt.raw.len < sizeof(*pkt.eth) + sizeof(*pkt.ip)) return;  // Truncated
-    if ((pkt.ip->ver >> 4) != 4) return;                           // Not IP
-    mkpay(&pkt, pkt.ip + 1);
+    pkt.ip = (struct ip *) (pkt.pay.buf);
     rx_ip(ifp, &pkt);
   } else {
     MG_DEBUG(("Unknown eth type %x", mg_htons(pkt.eth->type)));
@@ -5264,7 +5380,7 @@ static void mg_tcpip_poll(struct mg_tcpip_if *ifp, uint64_t now) {
     uint32_t rem_ip;
     if ((c->is_udp && !c->is_arplooking) || c->is_listening || c->is_resolving)
       continue;
-    memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+    rem_ip = c->rem.ip4;
     if (ifp->now > s->timer) {
       if (s->ttype == MIP_TTYPE_ARP) {
         mg_error(c, "ARP timeout");
@@ -5355,8 +5471,7 @@ void mg_tcpip_free(struct mg_tcpip_if *ifp) {
 static void send_syn(struct mg_connection *c) {
   struct connstate *s = (struct connstate *) (c + 1);
   uint32_t isn = mg_htonl((uint32_t) mg_ntohs(c->loc.port));
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   tx_tcp(c->mgr->ifp, s->mac, rem_ip, TH_SYN, c->loc.port, c->rem.port, isn, 0,
          NULL, 0);
 }
@@ -5380,11 +5495,10 @@ static void ip4_mcastmac(uint8_t *mac, uint32_t *ip) {
 
 void mg_connect_resolved(struct mg_connection *c) {
   struct mg_tcpip_if *ifp = c->mgr->ifp;
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   c->is_resolving = 0;
   if (ifp->eport < MG_EPHEMERAL_PORT_BASE) ifp->eport = MG_EPHEMERAL_PORT_BASE;
-  memcpy(c->loc.ip, &ifp->ip, sizeof(uint32_t));
+  c->loc.ip4 = ifp->ip;
   c->loc.port = mg_htons(ifp->eport++);
   MG_DEBUG(("%lu %M -> %M", c->id, mg_print_ip_port, &c->loc, mg_print_ip_port,
             &c->rem));
@@ -5436,8 +5550,7 @@ static void init_closure(struct mg_connection *c) {
   struct connstate *s = (struct connstate *) (c + 1);
   if (c->is_udp == false && c->is_listening == false &&
       c->is_connecting == false) {  // For TCP conns,
-    uint32_t rem_ip;
-    memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
     tx_tcp(c->mgr->ifp, s->mac, rem_ip, TH_FIN | TH_ACK, c->loc.port,
            c->rem.port, mg_htonl(s->seq), mg_htonl(s->ack), NULL, 0);
     settmout(c, MIP_TTYPE_FIN);
@@ -5491,8 +5604,7 @@ void mg_mgr_poll(struct mg_mgr *mgr, int ms) {
 bool mg_send(struct mg_connection *c, const void *buf, size_t len) {
   struct mg_tcpip_if *ifp = c->mgr->ifp;
   bool res = false;
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   if (ifp->ip == 0 || ifp->state != MG_TCPIP_STATE_READY) {
     mg_error(c, "net down");
   } else if (c->is_udp && (c->is_arplooking || c->is_resolving)) {
@@ -7700,7 +7812,9 @@ bool mg_ota_end(void) {
 
 
 size_t mg_queue_vprintf(struct mg_queue *q, const char *fmt, va_list *ap) {
-  size_t len = mg_snprintf(NULL, 0, fmt, ap);
+  va_list ap_copy;
+  va_copy(ap_copy, *ap);
+  size_t len = mg_vsnprintf(NULL, 0, fmt, &ap_copy);
   char *buf;
   if (len == 0 || mg_queue_book(q, &buf, len + 1) < len + 1) {
     len = 0;  // Nah. Not enough space
@@ -8904,7 +9018,7 @@ static void mg_set_non_blocking_mode(MG_SOCKET_TYPE fd) {
 void mg_multicast_add(struct mg_connection *c, char *ip);
 void mg_multicast_add(struct mg_connection *c, char *ip) {
 #if MG_ENABLE_RL
-#error UNSUPPORTED
+  MG_ERROR(("unsupported"));
 #elif MG_ENABLE_FREERTOS_TCP
   // TODO(): prvAllowIPPacketIPv4()
 #else
@@ -11000,6 +11114,8 @@ enum mg_tls_hs_state {
 
   // Server state machine:
   MG_TLS_STATE_SERVER_START,       // Wait for ClientHello
+  MG_TLS_STATE_SERVER_WAIT_CERT,   // Wait for Certificate
+  MG_TLS_STATE_SERVER_WAIT_CV,     // Wait for CertificateVerify
   MG_TLS_STATE_SERVER_NEGOTIATED,  // Wait for Finish
   MG_TLS_STATE_SERVER_CONNECTED    // Done
 };
@@ -11035,14 +11151,15 @@ struct tls_data {
   uint8_t x25519_cli[32];  // client X25519 key between the handshake states
   uint8_t x25519_sec[32];  // x25519 secret between the handshake states
 
-  int skip_verification;   // perform checks on server certificate?
-  int cert_requested;      // client received a CertificateRequest?
+  bool skip_verification;  // do not perform checks on server certificate
+  bool cert_requested;     // client received a CertificateRequest
+  bool is_twoway;          // server is configured to authenticate clients
   struct mg_str cert_der;  // certificate in DER format
   struct mg_str ca_der;    // CA certificate
   uint8_t ec_key[32];      // EC private key
-  char hostname[254];      // server hostname (client extension)
+  char hostname[254];      // matching hostname
 
-  int is_ec_pubkey;          // EC or RSA?
+  bool is_ec_pubkey;         // EC or RSA
   uint8_t pubkey[512 + 16];  // server EC (64) or RSA (512+exp) public key to
                              // verify cert
   size_t pubkeysz;           // size of the server public key
@@ -11488,18 +11605,18 @@ static int mg_tls_recv_record(struct mg_connection *c) {
 }
 
 static void mg_tls_calc_cert_verify_hash(struct mg_connection *c,
-                                         uint8_t hash[32], int is_client) {
+                                         uint8_t hash[32], bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
-  uint8_t server_context[34] = "TLS 1.3, server CertificateVerify";
-  uint8_t client_context[34] = "TLS 1.3, client CertificateVerify";
   uint8_t sig_content[130];
   mg_sha256_ctx sha256;
 
   memset(sig_content, 0x20, 64);
   if (is_client) {
-    memmove(sig_content + 64, client_context, sizeof(client_context));
+    uint8_t client_context[34] = "TLS 1.3, client CertificateVerify";
+    memcpy(sig_content + 64, client_context, sizeof(client_context));
   } else {
-    memmove(sig_content + 64, server_context, sizeof(server_context));
+    uint8_t server_context[34] = "TLS 1.3, server CertificateVerify";
+    memcpy(sig_content + 64, server_context, sizeof(server_context));
   }
 
   memmove(&sha256, &tls->sha256, sizeof(mg_sha256_ctx));
@@ -11641,17 +11758,46 @@ static void mg_tls_server_send_ext(struct mg_connection *c) {
   mg_tls_encrypt(c, ext, sizeof(ext), MG_TLS_HANDSHAKE);
 }
 
-static void mg_tls_server_send_cert(struct mg_connection *c) {
+// signature algorithms we actually support:
+// rsa_pkcs1_sha256, rsa_pss_rsae_sha256 and ecdsa_secp256r1_sha256
+static const uint8_t secp256r1_sig_algs[12] = {
+    0x00, 0x0d, 0x00, 0x08, 0x00, 0x06, 0x04, 0x03, 0x08, 0x04, 0x04, 0x01,
+};
+
+static void mg_tls_server_send_cert_request(struct mg_connection *c) {
+  struct tls_data *tls = (struct tls_data *) c->tls;
+  size_t n = sizeof(secp256r1_sig_algs) + 6;
+  uint8_t *req = (uint8_t *) mg_calloc(1, 13 + n);
+  if (req == NULL) {
+    mg_error(c, "tls cert req oom");
+    return;
+  }
+  req[0] = MG_TLS_CERTIFICATE_REQUEST;  // handshake header
+  MG_STORE_BE24(req + 1, n + 9);
+  req[4] = 0;                  // context length
+  MG_STORE_BE16(req + 5, n);   // extensions length
+  MG_STORE_BE16(req + 7, 13);  // "signature algorithms"
+  MG_STORE_BE16(req + 9, sizeof(secp256r1_sig_algs) + 2);  // length
+  MG_STORE_BE16(
+      req + 11,
+      sizeof(secp256r1_sig_algs));  // signature hash algorithms length
+  memcpy(req + 13, (uint8_t *) secp256r1_sig_algs, sizeof(secp256r1_sig_algs));
+  mg_sha256_update(&tls->sha256, req, 13 + n);
+  mg_tls_encrypt(c, req, 13 + n, MG_TLS_HANDSHAKE);
+  mg_free(req);
+}
+
+static void mg_tls_send_cert(struct mg_connection *c, bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
-  int send_ca = !c->is_client && tls->ca_der.len > 0;
-  // server DER certificate + CA (optional)
+  int send_ca = !is_client && tls->ca_der.len > 0;
+  // DER certificate + CA (server optional)
   size_t n = tls->cert_der.len + (send_ca ? tls->ca_der.len + 5 : 0);
   uint8_t *cert = (uint8_t *) mg_calloc(1, 13 + n);
   if (cert == NULL) {
     mg_error(c, "tls cert oom");
     return;
   }
-  cert[0] = 0x0b;  // handshake header
+  cert[0] = MG_TLS_CERTIFICATE;  // handshake header
   MG_STORE_BE24(cert + 1, n + 9);
   cert[4] = 0;                                 // request context
   MG_STORE_BE24(cert + 5, n + 5);              // 3 bytes: cert (s) length
@@ -11694,7 +11840,7 @@ static void finish_SHA256(const MG_UECC_HashContext *base,
   mg_sha256_final(hash_result, &c->ctx);
 }
 
-static void mg_tls_send_cert_verify(struct mg_connection *c, int is_client) {
+static void mg_tls_send_cert_verify(struct mg_connection *c, bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   // server certificate verify packet
   uint8_t verify[82] = {0x0f, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00};
@@ -11771,12 +11917,9 @@ static void mg_tls_client_send_hello(struct mg_connection *c) {
 
   uint8_t x25519_pub[X25519_BYTES];
 
-  // signature algorithms we actually support:
-  // rsa_pkcs1_sha256, rsa_pss_rsae_sha256 and ecdsa_secp256r1_sha256
-  uint8_t secp256r1_sig_algs[12] = {
-      0x00, 0x0d, 0x00, 0x08, 0x00, 0x06, 0x04, 0x03, 0x08, 0x04, 0x04, 0x01,
-  };
-  // all popular signature algorithms (if we don't care about verification)
+  // - "signature algorithms we actually support", see above
+  //   uint8_t secp256r1_sig_algs[]
+  // - all popular signature algorithms (if we don't care about verification)
   uint8_t all_sig_algs[34] = {
       0x00, 0x0d, 0x00, 0x1e, 0x00, 0x1c, 0x04, 0x03, 0x05, 0x03, 0x06, 0x03,
       0x08, 0x07, 0x08, 0x08, 0x08, 0x09, 0x08, 0x0a, 0x08, 0x0b, 0x08, 0x04,
@@ -11820,7 +11963,8 @@ static void mg_tls_client_send_hello(struct mg_connection *c) {
   const char *hostname = tls->hostname;
   size_t hostnamesz = strlen(tls->hostname);
   size_t hostname_extsz = hostnamesz ? hostnamesz + 9 : 0;
-  uint8_t *sig_alg = tls->skip_verification ? all_sig_algs : secp256r1_sig_algs;
+  uint8_t *sig_alg =
+      tls->skip_verification ? all_sig_algs : (uint8_t *) secp256r1_sig_algs;
   size_t sig_alg_sz = tls->skip_verification ? sizeof(all_sig_algs)
                                              : sizeof(secp256r1_sig_algs);
 
@@ -12195,7 +12339,7 @@ static int mg_tls_verify_cert_cn(struct mg_der_tlv *subj, const char *host) {
   return matched;
 }
 
-static int mg_tls_client_recv_cert(struct mg_connection *c) {
+static int mg_tls_recv_cert(struct mg_connection *c, bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   unsigned char *recv_buf;
 
@@ -12213,7 +12357,8 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
   }
 
   if (recv_buf[0] != MG_TLS_CERTIFICATE) {
-    mg_error(c, "expected server certificate but got msg 0x%02x", recv_buf[0]);
+    mg_error(c, "expected %s certificate but got msg 0x%02x",
+             is_client ? "server" : "client", recv_buf[0]);
     return -1;
   }
 
@@ -12223,7 +12368,7 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
   }
 
   {
-    // Normally, there are 2-3 certs in a chain
+    // Normally, there are 2-3 certs in a chain (when is_client)
     struct mg_tls_cert certs[8];
     int certnum = 0;
     uint32_t full_cert_chain_len = MG_LOAD_BE24(recv_buf + 1);
@@ -12268,9 +12413,10 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
       }
 
       if (ci == certs) {
-        // First certificate in the chain is peer cert, check SAN and store
-        // public key for further CertVerify step
-        if (mg_tls_verify_cert_san(cert, certsz, tls->hostname) <= 0 &&
+        // First certificate in the chain is peer cert, check SAN if requested,
+        // and store public key for further CertVerify step
+        if (tls->hostname != NULL && *tls->hostname != '\0' &&
+            mg_tls_verify_cert_san(cert, certsz, tls->hostname) <= 0 &&
             mg_tls_verify_cert_cn(&ci->subj, tls->hostname) <= 0) {
           mg_error(c, "failed to verify hostname");
           return -1;
@@ -12301,7 +12447,7 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
           !mg_tls_verify_cert_signature(&certs[certnum - 1], &ca)) {
         mg_error(c, "failed to verify CA");
         return -1;
-      } else {
+      } else if (is_client) {
         MG_VERBOSE(
             ("CA was not in the chain, but verification with builtin CA "
              "passed"));
@@ -12309,11 +12455,11 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
     }
   }
   mg_tls_drop_message(c);
-  mg_tls_calc_cert_verify_hash(c, tls->sighash, 0);
+  mg_tls_calc_cert_verify_hash(c, tls->sighash, !is_client);
   return 0;
 }
 
-static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
+static int mg_tls_recv_cert_verify(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   unsigned char *recv_buf;
   if (mg_tls_recv_record(c) < 0) {
@@ -12321,8 +12467,8 @@ static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
   }
   recv_buf = &c->rtls.buf[tls->recv_offset];
   if (recv_buf[0] != MG_TLS_CERTIFICATE_VERIFY) {
-    mg_error(c, "expected server certificate verify but got msg 0x%02x",
-             recv_buf[0]);
+    mg_error(c, "expected %s certificate verify but got msg 0x%02x",
+             c->is_client ? "server" : "client", recv_buf[0]);
     return -1;
   }
   if (tls->recv_len < 8) {
@@ -12331,7 +12477,7 @@ static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
     return -1;
   }
 
-  // Ignore CertificateVerify is strict checks are not required
+  // Ignore CertificateVerify if strict checks are not required
   if (tls->skip_verification) {
     mg_tls_drop_message(c);
     return 0;
@@ -12462,13 +12608,13 @@ static void mg_tls_client_handshake(struct mg_connection *c) {
       tls->state = MG_TLS_STATE_CLIENT_WAIT_CERT;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_CERT:
-      if (mg_tls_client_recv_cert(c) < 0) {
+      if (mg_tls_recv_cert(c, true) < 0) {
         break;
       }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_CV;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_CV:
-      if (mg_tls_client_recv_cert_verify(c) < 0) {
+      if (mg_tls_recv_cert_verify(c) < 0) {
         break;
       }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_FINISH;
@@ -12477,28 +12623,19 @@ static void mg_tls_client_handshake(struct mg_connection *c) {
       if (mg_tls_client_recv_finish(c) < 0) {
         break;
       }
-      if (tls->cert_requested) {
-        /* for mTLS we should generate application keys at this point
-         * but then restore handshake keys and continue with
-         * the rest of the handshake */
-        struct tls_enc app_keys;
-        struct tls_enc hs_keys = tls->enc;
-        mg_tls_generate_application_keys(c);
-        app_keys = tls->enc;
-        tls->enc = hs_keys;
-        mg_tls_server_send_cert(c);
-        mg_tls_send_cert_verify(c, 1);
-        mg_tls_client_send_finish(c);
-        tls->enc = app_keys;
-      } else {
-        mg_tls_client_send_finish(c);
-        mg_tls_generate_application_keys(c);
+      if (tls->cert_requested && tls->cert_der.len > 0) {  // two-way auth
+        mg_tls_send_cert(c, true);
+        mg_tls_send_cert_verify(c, true);
       }
+      mg_tls_client_send_finish(c);
+      mg_tls_generate_application_keys(c);
       tls->state = MG_TLS_STATE_CLIENT_CONNECTED;
       c->is_tls_hs = 0;
       mg_call(c, MG_EV_TLS_HS, NULL);
       break;
-    default: mg_error(c, "unexpected client state: %d", tls->state); break;
+    default:
+      mg_error(c, "unexpected client state: %d", tls->state);
+      break;
   }
 }
 
@@ -12512,9 +12649,14 @@ static void mg_tls_server_handshake(struct mg_connection *c) {
       mg_tls_server_send_hello(c);
       mg_tls_generate_handshake_keys(c);
       mg_tls_server_send_ext(c);
-      mg_tls_server_send_cert(c);
-      mg_tls_send_cert_verify(c, 0);
+      if (tls->is_twoway) mg_tls_server_send_cert_request(c);
+      mg_tls_send_cert(c, false);
+      mg_tls_send_cert_verify(c, false);
       mg_tls_server_send_finish(c);
+      if (tls->is_twoway) {
+        tls->state = MG_TLS_STATE_SERVER_WAIT_CERT;
+        break;
+      }
       tls->state = MG_TLS_STATE_SERVER_NEGOTIATED;
       // fallthrough
     case MG_TLS_STATE_SERVER_NEGOTIATED:
@@ -12525,7 +12667,17 @@ static void mg_tls_server_handshake(struct mg_connection *c) {
       tls->state = MG_TLS_STATE_SERVER_CONNECTED;
       c->is_tls_hs = 0;
       return;
-    default: mg_error(c, "unexpected server state: %d", tls->state); break;
+    case MG_TLS_STATE_SERVER_WAIT_CERT:
+      if (mg_tls_recv_cert(c, false) < 0) break;
+      tls->state = MG_TLS_STATE_SERVER_WAIT_CV;
+      // Fallthrough
+    case MG_TLS_STATE_SERVER_WAIT_CV:
+      if (mg_tls_recv_cert_verify(c) < 0) break;
+      tls->state = MG_TLS_STATE_SERVER_NEGOTIATED;
+      break;
+    default:
+      mg_error(c, "unexpected server state: %d", tls->state);
+      break;
   }
 }
 
@@ -12612,6 +12764,7 @@ void mg_tls_init(struct mg_connection *c, const struct mg_tls_opts *opts) {
       MG_ERROR(("Failed to load certificate"));
       return;
     }
+    if (!c->is_client) tls->is_twoway = true;  // server + CA: two-way auth
   }
 
   if (opts->cert.buf == NULL) {
@@ -14184,6 +14337,10 @@ void mg_tls_free(struct mg_connection *c) {
     mbedtls_ssl_config_free(&tls->conf);
 #ifdef MBEDTLS_SSL_SESSION_TICKETS
     mbedtls_ssl_ticket_free(&tls->ticket);
+#endif
+#if defined(MBEDTLS_VERSION_NUMBER) && MBEDTLS_VERSION_NUMBER >= 0x03000000 && \
+    defined(MBEDTLS_PSA_CRYPTO_C)
+    mbedtls_psa_crypto_free(); // https://github.com/Mbed-TLS/mbedtls/issues/9223#issuecomment-2144898336
 #endif
     mg_free(tls);
     c->tls = NULL;
@@ -20085,7 +20242,8 @@ void mg_free(void *ptr) {
 
 #if (!defined(MG_ENABLE_DRIVER_PICO_W) || !MG_ENABLE_DRIVER_PICO_W) && \
     (!defined(MG_ENABLE_DRIVER_CYW) || !MG_ENABLE_DRIVER_CYW) && \
-    (!defined(MG_ENABLE_DRIVER_CYW_SDIO) || !MG_ENABLE_DRIVER_CYW_SDIO)
+    (!defined(MG_ENABLE_DRIVER_CYW_SDIO) || !MG_ENABLE_DRIVER_CYW_SDIO) && \
+    (!defined(MG_ENABLE_DRIVER_NXP_WIFI) || !MG_ENABLE_DRIVER_NXP_WIFI)
 
 
 bool mg_wifi_scan(void) {
@@ -20093,9 +20251,8 @@ bool mg_wifi_scan(void) {
   return false;
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
-  (void) ssid;
-  (void) pass;
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  (void) wifi;
   return mg_wifi_scan();
 }
 
@@ -20103,10 +20260,8 @@ bool mg_wifi_disconnect(void) {
   return mg_wifi_scan();
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
-  (void) ssid;
-  (void) pass;
-  (void) channel;
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  (void) wifi;
   return mg_wifi_scan();
 }
 
@@ -20567,28 +20722,42 @@ static size_t cmsis_rx(void *buf, size_t buflen, struct mg_tcpip_if *ifp) {
 #endif
 
 static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
 static bool s_link, s_auth, s_join;
 
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
+
 static bool cyw_init(uint8_t *mac);
 static void cyw_poll(void);
 
 static bool mg_tcpip_driver_cyw_init(struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
+  struct mg_wifi_data *wifi = &d->wifi;
   if (MG_BIG_ENDIAN) {
     MG_ERROR(("Big-endian host"));
     return false;
   }
   s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
   s_link = s_auth = s_join = false;
+  ifp->pfn = wifi_cb;
   if (!cyw_init(ifp->mac)) return false;
 
-  if (d->apmode) {
-    MG_DEBUG(("Starting AP '%s' (%u)", d->apssid, d->apchannel));
-    return mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
-  } else if (d->ssid != NULL && d->pass != NULL) {
-    MG_DEBUG(("Connecting to '%s'", d->ssid));
-    return mg_wifi_connect(d->ssid, d->pass);
+  if (wifi->apmode) {
+    return mg_wifi_ap_start(wifi);
+  } else if (wifi->ssid != NULL && wifi->pass != NULL) {
+    return mg_wifi_connect(wifi);
   }
   return true;
 }
@@ -20598,7 +20767,7 @@ size_t mg_tcpip_driver_cyw_output(const void *buf, size_t len,
                                   struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-  return mg_cyw_tx(d->apmode ? 1 : 0, (void *) buf, len) >= len ? len : 0;
+  return mg_cyw_tx(d->wifi.apmode ? 1 : 0, (void *) buf, len) >= len ? len : 0;
 }
 
 static bool mg_tcpip_driver_cyw_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -20606,7 +20775,7 @@ static bool mg_tcpip_driver_cyw_poll(struct mg_tcpip_if *ifp, bool s1) {
   if (!s1) return false;
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-  return d->apmode ? s_link : s_link && s_auth && s_join;
+  return d->wifi.apmode ? s_link : s_link && s_auth && s_join;
 }
 
 struct mg_tcpip_driver mg_tcpip_driver_cyw = {mg_tcpip_driver_cyw_init,
@@ -21589,7 +21758,7 @@ static size_t cyw_spi_poll(uint8_t *response) {
     cyw_spi_write(CYW_SPID_FUNC_BUS, CYW_BUS_SPI_INT, &val, sizeof(val));
     return 0;
   }
-  cyw_spi_read(CYW_SPID_FUNC_WLAN, 0,  response, len);
+  cyw_spi_read(CYW_SPID_FUNC_WLAN, 0,  response, (uint16_t)len);
   return len;
 }
 
@@ -21652,7 +21821,7 @@ static bool cyw_spi_init() {
   cyw_set_backplane_window(CYW_CHIP_CHIPCOMMON); // set backplane window to start of CHIPCOMMON area
   cyw_spi_read(CYW_SPID_FUNC_CHIP, (CYW_CHIP_CHIPCOMMON + 0x00) & CYW_CHIP_BCKPLN_ADDRMSK, &val, 2);
   if (val == 43430) val = 4343;
-  MG_INFO(("WLAN chip is CYW%u%c", val), val == 4343 ? 'W' : ' '));
+  MG_INFO(("WLAN chip is CYW%u%c", val, val == 4343 ? 'W' : ' '));
 
   // Load firmware (code and NVRAM)
   if (!cyw_load_firmware(d->fw)) return false;
@@ -21930,16 +22099,22 @@ bool mg_wifi_scan(void) {
   return cyw_wifi_scan();
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
-  return cyw_wifi_connect(ssid, pass);
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
+  MG_DEBUG(("Connecting to '%s'", wifi->ssid));
+  return cyw_wifi_connect(wifi->ssid, wifi->pass);
 }
 
 bool mg_wifi_disconnect(void) {
   return cyw_wifi_disconnect();
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
-  return cyw_wifi_ap_start(ssid, pass, channel);
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  MG_DEBUG(("Starting AP '%s' (%u)", wifi->apssid, wifi->apchannel));
+  return cyw_wifi_ap_start(wifi->apssid, wifi->appass, wifi->apchannel);
 }
 
 bool mg_wifi_ap_stop(void) {
@@ -22169,6 +22344,101 @@ struct mg_tcpip_driver mg_tcpip_driver_imxrt = {mg_tcpip_driver_imxrt_init,
 
 #endif
 
+#ifdef MG_ENABLE_LINES
+#line 1 "src/drivers/nxp_wifi.c"
+#endif
+#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_NXP_WIFI) && \
+    MG_ENABLE_DRIVER_NXP_WIFI
+
+
+
+bool __attribute__((weak)) netif_init(struct mg_tcpip_if *ifp) {
+  (void) ifp;
+  MG_ERROR(("Please link wifi/port/net contents"));
+  return false;
+}
+size_t __attribute__((weak))
+netif_tx(const void *bfr, size_t len, struct mg_tcpip_if *ifp) {
+  (void) bfr;
+  (void) len;
+  netif_init(ifp);
+  return 0;
+}
+bool __attribute__((weak)) netif_connect(struct mg_wifi_data *wifi) {
+  (void) wifi;
+  return netif_init(NULL);
+}
+bool __attribute__((weak))
+netif_poll(struct mg_tcpip_if *ifp, bool s1, mg_tcpip_event_handler_t evcb) {
+  (void) ifp;
+  (void) s1;
+  (void) evcb;
+  return false;
+}
+
+static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
+
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG &&
+      *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
+
+static bool nxp_wifi_init(struct mg_tcpip_if *ifp) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+  s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
+  ifp->pfn = wifi_cb;
+  if (!netif_init(ifp)) return false;
+  if (wifi->apmode) {
+    return mg_wifi_ap_start(wifi);
+  } else if (wifi->ssid != NULL && wifi->pass != NULL) {
+    return mg_wifi_connect(wifi);
+  }
+  return true;
+}
+
+bool nxp_wifi_poll(struct mg_tcpip_if *ifp, bool s1) {
+  return netif_poll(ifp, s1, mg_tcpip_call);
+}
+
+struct mg_tcpip_driver mg_tcpip_driver_nxp_wifi = {nxp_wifi_init, netif_tx,
+                                                   NULL, nxp_wifi_poll};
+
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
+  return netif_connect(wifi);
+}
+
+bool __attribute__((weak)) mg_wifi_scan(void) {
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_disconnect(void) {
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  (void) wifi;
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_ap_stop(void) {
+  return netif_init(NULL);
+}
+
+#endif
+
 #ifdef MG_ENABLE_LINES
 #line 1 "src/drivers/phy.c"
 #endif
@@ -22335,23 +22605,41 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
 
 
 static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
+static bool s_aplink = false, s_scanning = false;
+static bool s_stalink = false, s_connecting = false;
+
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_pico_w_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG &&
+      *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
 
 static bool mg_tcpip_driver_pico_w_init(struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
+  struct mg_wifi_data *wifi = &d->wifi;
   s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
+  ifp->pfn = wifi_cb;
   if (cyw43_arch_init() != 0)
     return false;  // initialize async_context and WiFi chip
-  if (d->apmode && d->apssid != NULL) {
-    MG_DEBUG(("Starting AP '%s' (%u)", d->apssid, d->apchannel));
-    if (!mg_wifi_ap_start(d->apssid, d->appass, d->apchannel)) return false;
+  if (wifi->apmode && wifi->apssid != NULL) {
+    if (!mg_wifi_ap_start(wifi)) return false;
     cyw43_wifi_get_mac(&cyw43_state, CYW43_ITF_STA, ifp->mac);  // same MAC
   } else {
     cyw43_arch_enable_sta_mode();
     cyw43_wifi_get_mac(&cyw43_state, CYW43_ITF_STA, ifp->mac);
-    if (d->ssid != NULL) {
-      MG_DEBUG(("Connecting to '%s'", d->ssid));
-      return mg_wifi_connect(d->ssid, d->pass);
+    if (wifi->ssid != NULL) {
+      return mg_wifi_connect(wifi);
     } else {
       cyw43_arch_disable_sta_mode();
     }
@@ -22364,35 +22652,33 @@ static size_t mg_tcpip_driver_pico_w_tx(const void *buf, size_t len,
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
   return cyw43_send_ethernet(&cyw43_state,
-                             d->apmode ? CYW43_ITF_AP : CYW43_ITF_STA, len, buf,
-                             false) == 0
+                             d->wifi.apmode ? CYW43_ITF_AP : CYW43_ITF_STA, len,
+                             buf, false) == 0
              ? len
              : 0;
 }
 
-static bool s_aplink = false, s_scanning = false;
-static bool s_stalink = false, s_connecting = false;
-
 static bool mg_tcpip_driver_pico_w_poll(struct mg_tcpip_if *ifp, bool s1) {
   cyw43_arch_poll();  // not necessary, except when IRQs are disabled (OTA)
   if (s_scanning && !cyw43_wifi_scan_active(&cyw43_state)) {
     MG_VERBOSE(("scan complete"));
     s_scanning = 0;
-    mg_tcpip_call(s_ifp, MG_TCPIP_EV_WIFI_SCAN_END, NULL);
+    mg_tcpip_call(ifp, MG_TCPIP_EV_WIFI_SCAN_END, NULL);
   }
   if (ifp->update_mac_hash_table) {
     // first call to _poll() is after _init(), so this is safe
-    cyw43_wifi_update_multicast_filter(&cyw43_state, (uint8_t *)mcast_addr, true);
+    cyw43_wifi_update_multicast_filter(&cyw43_state, (uint8_t *) mcast_addr,
+                                       true);
     ifp->update_mac_hash_table = false;
   }
   if (!s1) return false;
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
-  if (d->apmode) return s_aplink;
+  if (d->wifi.apmode) return s_aplink;
   int sdkstate = cyw43_wifi_link_status(&cyw43_state, CYW43_ITF_STA);
   MG_VERBOSE(("conn: %c state: %d", s_connecting ? '1' : '0', sdkstate));
   if (sdkstate < 0 && s_connecting) {
-    mg_tcpip_call(s_ifp, MG_TCPIP_EV_WIFI_CONNECT_ERR, &sdkstate);
+    mg_tcpip_call(ifp, MG_TCPIP_EV_WIFI_CONNECT_ERR, &sdkstate);
     s_connecting = false;
   }
   return s_stalink;
@@ -22423,7 +22709,7 @@ void cyw43_cb_tcpip_set_link_up(cyw43_t *self, int itf) {
 }
 void cyw43_cb_tcpip_set_link_down(cyw43_t *self, int itf) {
   if (itf == CYW43_ITF_AP) {
-     s_aplink = false;
+    s_aplink = false;
   } else {
     s_stalink = false;
     // SDK calls this before we check status, don't clear s_connecting here
@@ -22463,9 +22749,15 @@ bool mg_wifi_scan(void) {
   return res;
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
   cyw43_arch_enable_sta_mode();
-  int res = cyw43_arch_wifi_connect_async(ssid, pass, CYW43_AUTH_WPA2_AES_PSK);
+  MG_DEBUG(("Connecting to '%s'", wifi->ssid));
+  int res = cyw43_arch_wifi_connect_async(wifi->ssid, wifi->pass,
+                                          CYW43_AUTH_WPA2_AES_PSK);
   MG_VERBOSE(("res: %d", res));
   if (res == 0) s_connecting = true;
   return (res == 0);
@@ -22477,9 +22769,11 @@ bool mg_wifi_disconnect(void) {
   return true;
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
-  cyw43_wifi_ap_set_channel(&cyw43_state, channel);
-  cyw43_arch_enable_ap_mode(ssid, pass, CYW43_AUTH_WPA2_AES_PSK);
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  MG_DEBUG(("Starting AP '%s' (%u)", wifi->apssid, wifi->apchannel));
+  cyw43_wifi_ap_set_channel(&cyw43_state, wifi->apchannel);
+  cyw43_arch_enable_ap_mode(wifi->apssid, wifi->appass,
+                            CYW43_AUTH_WPA2_AES_PSK);
   return true;
 }
 
diff --git a/mongoose.h b/mongoose.h
index 6148b9e465..52a032a385 100644
--- a/mongoose.h
+++ b/mongoose.h
@@ -285,6 +285,7 @@ extern "C" {
 #define mode_t size_t
 #include <alloca.h>
 #include <time.h>
+#define strdup(s) ((char *) mg_strdup(mg_str(s)).buf)
 #elif defined(__CCRH__)
 #else
 #include <sys/stat.h>
@@ -1060,6 +1061,10 @@ struct timeval {
 #define MG_SET_MAC_ADDRESS(mac)
 #endif
 
+#ifndef MG_TCPIP_DHCPNAME_SIZE
+#define MG_TCPIP_DHCPNAME_SIZE 18  // struct mg_tcpip_if :: dhcp_name size
+#endif
+
 #ifndef MG_SET_WIFI_CONFIG
 #define MG_SET_WIFI_CONFIG(data)
 #endif
@@ -1604,7 +1609,11 @@ struct mg_dns {
 };
 
 struct mg_addr {
-  uint8_t ip[16];    // Holds IPv4 or IPv6 address, in network byte order
+  union {    // Holds IPv4 or IPv6 address, in network byte order
+    uint8_t ip[16];
+    uint32_t ip4;
+    uint64_t ip6[2];
+  };
   uint16_t port;     // TCP or UDP port in network byte order
   uint8_t scope_id;  // IPv6 scope ID
   bool is_ip6;       // True when address is IPv6 address
@@ -3023,28 +3032,37 @@ bool mg_ota_flash_end(struct mg_flash *flash);
 
 
 
+struct mg_wifi_data {
+  char *ssid, *pass;      // STA mode, SSID to connect to
+  char *apssid, *appass;  // AP mode, our SSID
+  uint32_t apip, apmask;  // AP mode, our IP address and mask
+  uint8_t security;       // STA mode, TBD
+  uint8_t apsecurity;     // AP mode, TBD
+  uint8_t apchannel;      // AP mode, channel to use
+  bool apmode;  // start in AP mode; 'false' -> connect to 'ssid' != NULL
+};
+
 struct mg_wifi_scan_bss_data {
-    struct mg_str SSID;
-    char *BSSID;
-    int16_t RSSI;
-    uint8_t security;
+  struct mg_str SSID;
+  char *BSSID;
+  int16_t RSSI;
+  uint8_t security;
 #define MG_WIFI_SECURITY_OPEN 0
-#define MG_WIFI_SECURITY_WEP  MG_BIT(0)
-#define MG_WIFI_SECURITY_WPA  MG_BIT(1)
+#define MG_WIFI_SECURITY_WEP MG_BIT(0)
+#define MG_WIFI_SECURITY_WPA MG_BIT(1)
 #define MG_WIFI_SECURITY_WPA2 MG_BIT(2)
 #define MG_WIFI_SECURITY_WPA3 MG_BIT(3)
-    uint8_t channel;
-    unsigned band :2;
+  uint8_t channel;
+  unsigned band : 2;
 #define MG_WIFI_BAND_2G 0
 #define MG_WIFI_BAND_5G 1
-    unsigned has_n :1;
+  unsigned has_n : 1;
 };
 
-
 bool mg_wifi_scan(void);
-bool mg_wifi_connect(char *ssid, char *pass);
+bool mg_wifi_connect(struct mg_wifi_data *);
 bool mg_wifi_disconnect(void);
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel);
+bool mg_wifi_ap_start(struct mg_wifi_data *);
 bool mg_wifi_ap_stop(void);
 
 
@@ -3068,19 +3086,20 @@ typedef void (*mg_tcpip_event_handler_t)(struct mg_tcpip_if *ifp, int ev,
                                          void *ev_data);
 
 enum {
-  MG_TCPIP_EV_ST_CHG,           // state change                   uint8_t * (&ifp->state)
-  MG_TCPIP_EV_DHCP_DNS,         // DHCP DNS assignment            uint32_t *ipaddr
-  MG_TCPIP_EV_DHCP_SNTP,        // DHCP SNTP assignment           uint32_t *ipaddr
-  MG_TCPIP_EV_ARP,              // Got ARP packet                 struct mg_str *
-  MG_TCPIP_EV_TIMER_1S,         // 1 second timer                 NULL
-  MG_TCPIP_EV_WIFI_SCAN_RESULT, // Wi-Fi scan results             struct mg_wifi_scan_bss_data *
-  MG_TCPIP_EV_WIFI_SCAN_END,    // Wi-Fi scan has finished        NULL
-  MG_TCPIP_EV_WIFI_CONNECT_ERR, // Wi-Fi connect has failed       driver and chip specific
-  MG_TCPIP_EV_DRIVER,           // Driver event                   driver specific
-  MG_TCPIP_EV_USER              // Starting ID for user events
+  MG_TCPIP_EV_ST_CHG,  // state change                   uint8_t * (&ifp->state)
+  MG_TCPIP_EV_DHCP_DNS,   // DHCP DNS assignment            uint32_t *ipaddr
+  MG_TCPIP_EV_DHCP_SNTP,  // DHCP SNTP assignment           uint32_t *ipaddr
+  MG_TCPIP_EV_ARP,        // Got ARP packet                 struct mg_str *
+  MG_TCPIP_EV_TIMER_1S,   // 1 second timer                 NULL
+  MG_TCPIP_EV_WIFI_SCAN_RESULT,  // Wi-Fi scan results             struct
+                                 // mg_wifi_scan_bss_data *
+  MG_TCPIP_EV_WIFI_SCAN_END,     // Wi-Fi scan has finished        NULL
+  MG_TCPIP_EV_WIFI_CONNECT_ERR,  // Wi-Fi connect has failed       driver and
+                                 // chip specific
+  MG_TCPIP_EV_DRIVER,  // Driver event                   driver specific
+  MG_TCPIP_EV_USER     // Starting ID for user events
 };
 
-
 // Network interface
 struct mg_tcpip_if {
   uint8_t mac[6];                  // MAC address. Must be set to a valid MAC
@@ -3096,11 +3115,12 @@ struct mg_tcpip_if {
   bool update_mac_hash_table;      // Signal drivers to update MAC controller
   struct mg_tcpip_driver *driver;  // Low level driver
   void *driver_data;               // Driver-specific data
+  mg_tcpip_event_handler_t pfn;    // Driver-specific event handler function
   mg_tcpip_event_handler_t fn;     // User-specified event handler function
   struct mg_mgr *mgr;              // Mongoose event manager
   struct mg_queue recv_queue;      // Receive queue
-  char dhcp_name[12];              // Name reported to DHCP, "mip" if unset
-  uint16_t mtu;                    // Interface MTU
+  char dhcp_name[MG_TCPIP_DHCPNAME_SIZE];  // Name for DHCP, "mip" if unset
+  uint16_t mtu;                            // Interface MTU
 #define MG_TCPIP_MTU_DEFAULT 1500
 
   // Internal state, user can use it but should not change it
@@ -3143,6 +3163,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_ppp;
 extern struct mg_tcpip_driver mg_tcpip_driver_pico_w;
 extern struct mg_tcpip_driver mg_tcpip_driver_rw612;
 extern struct mg_tcpip_driver mg_tcpip_driver_cyw;
+extern struct mg_tcpip_driver mg_tcpip_driver_nxp_wifi;
 
 // Drivers that require SPI, can use this SPI abstraction
 struct mg_tcpip_spi {
@@ -3152,7 +3173,6 @@ struct mg_tcpip_spi {
   uint8_t (*txn)(void *, uint8_t);  // SPI transaction: write 1 byte, read reply
 };
 
-
 #endif
 
 
@@ -3186,16 +3206,9 @@ struct mg_tcpip_driver_cyw_firmware {
 };
 
 struct mg_tcpip_driver_cyw_data {
+  struct mg_wifi_data wifi;
   void *bus;
   struct mg_tcpip_driver_cyw_firmware *fw;
-  char *ssid;
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
   bool hs;          // use chip "high-speed" mode; otherwise SPI CPOL0 CPHA0 (DS 4.2.3 Table 6)
 };
 
@@ -3268,6 +3281,34 @@ struct mg_tcpip_driver_imxrt_data {
 #endif
 
 
+#if MG_ENABLE_TCPIP  && \
+    defined(MG_ENABLE_DRIVER_NXP_WIFI) && MG_ENABLE_DRIVER_NXP_WIFI
+
+
+struct mg_tcpip_driver_nxp_wifi_data {
+  struct mg_wifi_data wifi;
+};
+
+
+#define MG_TCPIP_DRIVER_INIT(mgr)                                   \
+  do {                                                              \
+    static struct mg_tcpip_driver_nxp_wifi_data driver_data_;       \
+    static struct mg_tcpip_if mif_;                                 \
+    MG_SET_WIFI_CONFIG(&driver_data_);                              \
+    mif_.ip = MG_TCPIP_IP;                                          \
+    mif_.mask = MG_TCPIP_MASK;                                      \
+    mif_.gw = MG_TCPIP_GW;                                          \
+    mif_.driver = &mg_tcpip_driver_nxp_wifi;                        \
+    mif_.driver_data = &driver_data_;                               \
+    mif_.recv_queue.size = 8192;                                    \
+    mif_.mac[0] = 2; /* MAC read from OTP at driver init */         \
+    mg_tcpip_init(mgr, &mif_);                                      \
+    MG_INFO(("Driver: nxp wifi, MAC: %M", mg_print_mac, mif_.mac)); \
+  } while (0)
+
+#endif
+
+
 
 
 struct mg_phy {
@@ -3298,14 +3339,7 @@ bool mg_phy_up(struct mg_phy *, uint8_t addr, bool *full_duplex,
 #include "pico/unique_id.h"     // keep this include
 
 struct mg_tcpip_driver_pico_w_data {
-  char *ssid;
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
+  struct mg_wifi_data wifi;
 };
 
 #define MG_TCPIP_DRIVER_INIT(mgr)                                 \
diff --git a/src/arch_freertos.h b/src/arch_freertos.h
index 2dc23b637a..dd54ad40a6 100644
--- a/src/arch_freertos.h
+++ b/src/arch_freertos.h
@@ -17,6 +17,7 @@
 #define mode_t size_t
 #include <alloca.h>
 #include <time.h>
+#define strdup(s) ((char *) mg_strdup(mg_str(s)).buf)
 #elif defined(__CCRH__)
 #else
 #include <sys/stat.h>
diff --git a/src/config.h b/src/config.h
index 23be298202..0a8dea4d92 100644
--- a/src/config.h
+++ b/src/config.h
@@ -179,6 +179,10 @@
 #define MG_SET_MAC_ADDRESS(mac)
 #endif
 
+#ifndef MG_TCPIP_DHCPNAME_SIZE
+#define MG_TCPIP_DHCPNAME_SIZE 18  // struct mg_tcpip_if :: dhcp_name size
+#endif
+
 #ifndef MG_SET_WIFI_CONFIG
 #define MG_SET_WIFI_CONFIG(data)
 #endif
diff --git a/src/drivers/cyw.c b/src/drivers/cyw.c
index e493bc87d8..e4620e19d7 100644
--- a/src/drivers/cyw.c
+++ b/src/drivers/cyw.c
@@ -13,28 +13,42 @@
 #endif
 
 static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
 static bool s_link, s_auth, s_join;
 
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
+
 static bool cyw_init(uint8_t *mac);
 static void cyw_poll(void);
 
 static bool mg_tcpip_driver_cyw_init(struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
+  struct mg_wifi_data *wifi = &d->wifi;
   if (MG_BIG_ENDIAN) {
     MG_ERROR(("Big-endian host"));
     return false;
   }
   s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
   s_link = s_auth = s_join = false;
+  ifp->pfn = wifi_cb;
   if (!cyw_init(ifp->mac)) return false;
 
-  if (d->apmode) {
-    MG_DEBUG(("Starting AP '%s' (%u)", d->apssid, d->apchannel));
-    return mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
-  } else if (d->ssid != NULL && d->pass != NULL) {
-    MG_DEBUG(("Connecting to '%s'", d->ssid));
-    return mg_wifi_connect(d->ssid, d->pass);
+  if (wifi->apmode) {
+    return mg_wifi_ap_start(wifi);
+  } else if (wifi->ssid != NULL && wifi->pass != NULL) {
+    return mg_wifi_connect(wifi);
   }
   return true;
 }
@@ -44,7 +58,7 @@ size_t mg_tcpip_driver_cyw_output(const void *buf, size_t len,
                                   struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-  return mg_cyw_tx(d->apmode ? 1 : 0, (void *) buf, len) >= len ? len : 0;
+  return mg_cyw_tx(d->wifi.apmode ? 1 : 0, (void *) buf, len) >= len ? len : 0;
 }
 
 static bool mg_tcpip_driver_cyw_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -52,7 +66,7 @@ static bool mg_tcpip_driver_cyw_poll(struct mg_tcpip_if *ifp, bool s1) {
   if (!s1) return false;
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-  return d->apmode ? s_link : s_link && s_auth && s_join;
+  return d->wifi.apmode ? s_link : s_link && s_auth && s_join;
 }
 
 struct mg_tcpip_driver mg_tcpip_driver_cyw = {mg_tcpip_driver_cyw_init,
@@ -1035,7 +1049,7 @@ static size_t cyw_spi_poll(uint8_t *response) {
     cyw_spi_write(CYW_SPID_FUNC_BUS, CYW_BUS_SPI_INT, &val, sizeof(val));
     return 0;
   }
-  cyw_spi_read(CYW_SPID_FUNC_WLAN, 0,  response, len);
+  cyw_spi_read(CYW_SPID_FUNC_WLAN, 0,  response, (uint16_t)len);
   return len;
 }
 
@@ -1098,7 +1112,7 @@ static bool cyw_spi_init() {
   cyw_set_backplane_window(CYW_CHIP_CHIPCOMMON); // set backplane window to start of CHIPCOMMON area
   cyw_spi_read(CYW_SPID_FUNC_CHIP, (CYW_CHIP_CHIPCOMMON + 0x00) & CYW_CHIP_BCKPLN_ADDRMSK, &val, 2);
   if (val == 43430) val = 4343;
-  MG_INFO(("WLAN chip is CYW%u%c", val), val == 4343 ? 'W' : ' '));
+  MG_INFO(("WLAN chip is CYW%u%c", val, val == 4343 ? 'W' : ' '));
 
   // Load firmware (code and NVRAM)
   if (!cyw_load_firmware(d->fw)) return false;
@@ -1376,16 +1390,22 @@ bool mg_wifi_scan(void) {
   return cyw_wifi_scan();
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
-  return cyw_wifi_connect(ssid, pass);
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
+  MG_DEBUG(("Connecting to '%s'", wifi->ssid));
+  return cyw_wifi_connect(wifi->ssid, wifi->pass);
 }
 
 bool mg_wifi_disconnect(void) {
   return cyw_wifi_disconnect();
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
-  return cyw_wifi_ap_start(ssid, pass, channel);
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  MG_DEBUG(("Starting AP '%s' (%u)", wifi->apssid, wifi->apchannel));
+  return cyw_wifi_ap_start(wifi->apssid, wifi->appass, wifi->apchannel);
 }
 
 bool mg_wifi_ap_stop(void) {
diff --git a/src/drivers/cyw.h b/src/drivers/cyw.h
index e2160997f2..e7cfb5a1c9 100644
--- a/src/drivers/cyw.h
+++ b/src/drivers/cyw.h
@@ -22,16 +22,9 @@ struct mg_tcpip_driver_cyw_firmware {
 };
 
 struct mg_tcpip_driver_cyw_data {
+  struct mg_wifi_data wifi;
   void *bus;
   struct mg_tcpip_driver_cyw_firmware *fw;
-  char *ssid;
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
   bool hs;          // use chip "high-speed" mode; otherwise SPI CPOL0 CPHA0 (DS 4.2.3 Table 6)
 };
 
diff --git a/src/drivers/nxp_wifi.c b/src/drivers/nxp_wifi.c
new file mode 100644
index 0000000000..36179c5f74
--- /dev/null
+++ b/src/drivers/nxp_wifi.c
@@ -0,0 +1,91 @@
+#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_NXP_WIFI) && \
+    MG_ENABLE_DRIVER_NXP_WIFI
+
+#include "drivers/nxp_wifi.h"
+
+bool __attribute__((weak)) netif_init(struct mg_tcpip_if *ifp) {
+  (void) ifp;
+  MG_ERROR(("Please link wifi/port/net contents"));
+  return false;
+}
+size_t __attribute__((weak))
+netif_tx(const void *bfr, size_t len, struct mg_tcpip_if *ifp) {
+  (void) bfr;
+  (void) len;
+  netif_init(ifp);
+  return 0;
+}
+bool __attribute__((weak)) netif_connect(struct mg_wifi_data *wifi) {
+  (void) wifi;
+  return netif_init(NULL);
+}
+bool __attribute__((weak))
+netif_poll(struct mg_tcpip_if *ifp, bool s1, mg_tcpip_event_handler_t evcb) {
+  (void) ifp;
+  (void) s1;
+  (void) evcb;
+  return false;
+}
+
+static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
+
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG &&
+      *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
+
+static bool nxp_wifi_init(struct mg_tcpip_if *ifp) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+  s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
+  ifp->pfn = wifi_cb;
+  if (!netif_init(ifp)) return false;
+  if (wifi->apmode) {
+    return mg_wifi_ap_start(wifi);
+  } else if (wifi->ssid != NULL && wifi->pass != NULL) {
+    return mg_wifi_connect(wifi);
+  }
+  return true;
+}
+
+bool nxp_wifi_poll(struct mg_tcpip_if *ifp, bool s1) {
+  return netif_poll(ifp, s1, mg_tcpip_call);
+}
+
+struct mg_tcpip_driver mg_tcpip_driver_nxp_wifi = {nxp_wifi_init, netif_tx,
+                                                   NULL, nxp_wifi_poll};
+
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
+  return netif_connect(wifi);
+}
+
+bool __attribute__((weak)) mg_wifi_scan(void) {
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_disconnect(void) {
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  (void) wifi;
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_ap_stop(void) {
+  return netif_init(NULL);
+}
+
+#endif
diff --git a/src/drivers/nxp_wifi.h b/src/drivers/nxp_wifi.h
new file mode 100644
index 0000000000..9c7c491201
--- /dev/null
+++ b/src/drivers/nxp_wifi.h
@@ -0,0 +1,28 @@
+#pragma once
+
+#if MG_ENABLE_TCPIP  && \
+    defined(MG_ENABLE_DRIVER_NXP_WIFI) && MG_ENABLE_DRIVER_NXP_WIFI
+
+
+struct mg_tcpip_driver_nxp_wifi_data {
+  struct mg_wifi_data wifi;
+};
+
+
+#define MG_TCPIP_DRIVER_INIT(mgr)                                   \
+  do {                                                              \
+    static struct mg_tcpip_driver_nxp_wifi_data driver_data_;       \
+    static struct mg_tcpip_if mif_;                                 \
+    MG_SET_WIFI_CONFIG(&driver_data_);                              \
+    mif_.ip = MG_TCPIP_IP;                                          \
+    mif_.mask = MG_TCPIP_MASK;                                      \
+    mif_.gw = MG_TCPIP_GW;                                          \
+    mif_.driver = &mg_tcpip_driver_nxp_wifi;                        \
+    mif_.driver_data = &driver_data_;                               \
+    mif_.recv_queue.size = 8192;                                    \
+    mif_.mac[0] = 2; /* MAC read from OTP at driver init */         \
+    mg_tcpip_init(mgr, &mif_);                                      \
+    MG_INFO(("Driver: nxp wifi, MAC: %M", mg_print_mac, mif_.mac)); \
+  } while (0)
+
+#endif
diff --git a/src/drivers/pico-w.c b/src/drivers/pico-w.c
index f54d801077..398875ae69 100644
--- a/src/drivers/pico-w.c
+++ b/src/drivers/pico-w.c
@@ -6,23 +6,41 @@
 #include "pico/stdlib.h"
 
 static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
+static bool s_aplink = false, s_scanning = false;
+static bool s_stalink = false, s_connecting = false;
+
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_pico_w_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG &&
+      *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
 
 static bool mg_tcpip_driver_pico_w_init(struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
+  struct mg_wifi_data *wifi = &d->wifi;
   s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
+  ifp->pfn = wifi_cb;
   if (cyw43_arch_init() != 0)
     return false;  // initialize async_context and WiFi chip
-  if (d->apmode && d->apssid != NULL) {
-    MG_DEBUG(("Starting AP '%s' (%u)", d->apssid, d->apchannel));
-    if (!mg_wifi_ap_start(d->apssid, d->appass, d->apchannel)) return false;
+  if (wifi->apmode && wifi->apssid != NULL) {
+    if (!mg_wifi_ap_start(wifi)) return false;
     cyw43_wifi_get_mac(&cyw43_state, CYW43_ITF_STA, ifp->mac);  // same MAC
   } else {
     cyw43_arch_enable_sta_mode();
     cyw43_wifi_get_mac(&cyw43_state, CYW43_ITF_STA, ifp->mac);
-    if (d->ssid != NULL) {
-      MG_DEBUG(("Connecting to '%s'", d->ssid));
-      return mg_wifi_connect(d->ssid, d->pass);
+    if (wifi->ssid != NULL) {
+      return mg_wifi_connect(wifi);
     } else {
       cyw43_arch_disable_sta_mode();
     }
@@ -35,35 +53,33 @@ static size_t mg_tcpip_driver_pico_w_tx(const void *buf, size_t len,
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
   return cyw43_send_ethernet(&cyw43_state,
-                             d->apmode ? CYW43_ITF_AP : CYW43_ITF_STA, len, buf,
-                             false) == 0
+                             d->wifi.apmode ? CYW43_ITF_AP : CYW43_ITF_STA, len,
+                             buf, false) == 0
              ? len
              : 0;
 }
 
-static bool s_aplink = false, s_scanning = false;
-static bool s_stalink = false, s_connecting = false;
-
 static bool mg_tcpip_driver_pico_w_poll(struct mg_tcpip_if *ifp, bool s1) {
   cyw43_arch_poll();  // not necessary, except when IRQs are disabled (OTA)
   if (s_scanning && !cyw43_wifi_scan_active(&cyw43_state)) {
     MG_VERBOSE(("scan complete"));
     s_scanning = 0;
-    mg_tcpip_call(s_ifp, MG_TCPIP_EV_WIFI_SCAN_END, NULL);
+    mg_tcpip_call(ifp, MG_TCPIP_EV_WIFI_SCAN_END, NULL);
   }
   if (ifp->update_mac_hash_table) {
     // first call to _poll() is after _init(), so this is safe
-    cyw43_wifi_update_multicast_filter(&cyw43_state, (uint8_t *)mcast_addr, true);
+    cyw43_wifi_update_multicast_filter(&cyw43_state, (uint8_t *) mcast_addr,
+                                       true);
     ifp->update_mac_hash_table = false;
   }
   if (!s1) return false;
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
-  if (d->apmode) return s_aplink;
+  if (d->wifi.apmode) return s_aplink;
   int sdkstate = cyw43_wifi_link_status(&cyw43_state, CYW43_ITF_STA);
   MG_VERBOSE(("conn: %c state: %d", s_connecting ? '1' : '0', sdkstate));
   if (sdkstate < 0 && s_connecting) {
-    mg_tcpip_call(s_ifp, MG_TCPIP_EV_WIFI_CONNECT_ERR, &sdkstate);
+    mg_tcpip_call(ifp, MG_TCPIP_EV_WIFI_CONNECT_ERR, &sdkstate);
     s_connecting = false;
   }
   return s_stalink;
@@ -94,7 +110,7 @@ void cyw43_cb_tcpip_set_link_up(cyw43_t *self, int itf) {
 }
 void cyw43_cb_tcpip_set_link_down(cyw43_t *self, int itf) {
   if (itf == CYW43_ITF_AP) {
-     s_aplink = false;
+    s_aplink = false;
   } else {
     s_stalink = false;
     // SDK calls this before we check status, don't clear s_connecting here
@@ -134,9 +150,15 @@ bool mg_wifi_scan(void) {
   return res;
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
   cyw43_arch_enable_sta_mode();
-  int res = cyw43_arch_wifi_connect_async(ssid, pass, CYW43_AUTH_WPA2_AES_PSK);
+  MG_DEBUG(("Connecting to '%s'", wifi->ssid));
+  int res = cyw43_arch_wifi_connect_async(wifi->ssid, wifi->pass,
+                                          CYW43_AUTH_WPA2_AES_PSK);
   MG_VERBOSE(("res: %d", res));
   if (res == 0) s_connecting = true;
   return (res == 0);
@@ -148,9 +170,11 @@ bool mg_wifi_disconnect(void) {
   return true;
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
-  cyw43_wifi_ap_set_channel(&cyw43_state, channel);
-  cyw43_arch_enable_ap_mode(ssid, pass, CYW43_AUTH_WPA2_AES_PSK);
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  MG_DEBUG(("Starting AP '%s' (%u)", wifi->apssid, wifi->apchannel));
+  cyw43_wifi_ap_set_channel(&cyw43_state, wifi->apchannel);
+  cyw43_arch_enable_ap_mode(wifi->apssid, wifi->appass,
+                            CYW43_AUTH_WPA2_AES_PSK);
   return true;
 }
 
diff --git a/src/drivers/pico-w.h b/src/drivers/pico-w.h
index fd0b504612..65ddb8bef0 100644
--- a/src/drivers/pico-w.h
+++ b/src/drivers/pico-w.h
@@ -8,14 +8,7 @@
 #include "pico/unique_id.h"     // keep this include
 
 struct mg_tcpip_driver_pico_w_data {
-  char *ssid;
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
+  struct mg_wifi_data wifi;
 };
 
 #define MG_TCPIP_DRIVER_INIT(mgr)                                 \
diff --git a/src/iobuf.c b/src/iobuf.c
index 390e9ce2a1..4d83f4cd12 100644
--- a/src/iobuf.c
+++ b/src/iobuf.c
@@ -25,6 +25,7 @@ int mg_iobuf_resize(struct mg_iobuf *io, size_t new_size) {
       mg_free(io->buf);
       io->buf = (unsigned char *) p;
       io->size = new_size;
+      io->len = len;
     } else {
       ok = 0;
       MG_ERROR(("%lld->%lld", (uint64_t) io->size, (uint64_t) new_size));
diff --git a/src/net.h b/src/net.h
index 73fe20d931..e608820465 100644
--- a/src/net.h
+++ b/src/net.h
@@ -14,7 +14,11 @@ struct mg_dns {
 };
 
 struct mg_addr {
-  uint8_t ip[16];    // Holds IPv4 or IPv6 address, in network byte order
+  union {    // Holds IPv4 or IPv6 address, in network byte order
+    uint8_t ip[16];
+    uint32_t ip4;
+    uint64_t ip6[2];
+  };
   uint16_t port;     // TCP or UDP port in network byte order
   uint8_t scope_id;  // IPv6 scope ID
   bool is_ip6;       // True when address is IPv6 address
diff --git a/src/net_builtin.c b/src/net_builtin.c
index e2d6a9fd7c..f086133afe 100644
--- a/src/net_builtin.c
+++ b/src/net_builtin.c
@@ -1,4 +1,5 @@
 #include "net_builtin.h"
+#include "profile.h"
 
 #if MG_ENABLE_TCPIP
 #define MG_EPHEMERAL_PORT_BASE 32768
@@ -48,7 +49,7 @@ struct eth {
 struct ip {
   uint8_t ver;    // Version
   uint8_t tos;    // Unused
-  uint16_t len;   // Length
+  uint16_t len;   // Datagram length
   uint16_t id;    // Unused
   uint16_t frag;  // Fragmentation
 #define IP_FRAG_OFFSET_MSK 0x1fff
@@ -61,13 +62,13 @@ struct ip {
 };
 
 struct ip6 {
-  uint8_t ver;      // Version
-  uint8_t opts[3];  // Options
-  uint16_t len;     // Length
-  uint8_t proto;    // Upper level protocol
-  uint8_t ttl;      // Time to live
-  uint8_t src[16];  // Source IP
-  uint8_t dst[16];  // Destination IP
+  uint8_t ver;       // Version
+  uint8_t label[3];  // Flow label
+  uint16_t plen;     // Payload length
+  uint8_t next;      // Upper level protocol
+  uint8_t hops;      // Hop limit
+  uint8_t src[16];   // Source IP
+  uint8_t dst[16];   // Destination IP
 };
 
 struct icmp {
@@ -76,6 +77,12 @@ struct icmp {
   uint16_t csum;
 };
 
+struct icmp6 {
+  uint8_t type;
+  uint8_t code;
+  uint16_t csum;
+};
+
 struct arp {
   uint16_t fmt;    // Format of hardware address
   uint16_t pro;    // Format of protocol address
@@ -125,6 +132,14 @@ struct dhcp {
   uint8_t options[30 + sizeof(((struct mg_tcpip_if *) 0)->dhcp_name)];
 };
 
+struct dhcp6 {
+  union {
+    uint8_t type;
+    uint32_t xid;
+  };
+  uint8_t options[30 + sizeof(((struct mg_tcpip_if *) 0)->dhcp_name)];
+};
+
 #pragma pack(pop)
 
 struct pkt {
@@ -136,12 +151,33 @@ struct pkt {
   struct ip *ip;
   struct ip6 *ip6;
   struct icmp *icmp;
+  struct icmp6 *icmp6;
   struct tcp *tcp;
   struct udp *udp;
   struct dhcp *dhcp;
+  struct dhcp6 *dhcp6;
 };
 
 static void mg_tcpip_call(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+#if MG_ENABLE_PROFILE
+  const char *names[] = {
+  "TCPIP_EV_ST_CHG",
+  "TCPIP_EV_DHCP_DNS",
+  "TCPIP_EV_DHCP_SNTP",
+  "TCPIP_EV_ARP",
+  "TCPIP_EV_TIMER_1S",
+  "TCPIP_EV_WIFI_SCAN_RESULT",
+  "TCPIP_EV_WIFI_SCAN_END",
+  "TCPIP_EV_WIFI_CONNECT_ERR",
+  "TCPIP_EV_DRIVER",
+  "TCPIP_EV_USER" 
+  };
+  if (ev != MG_TCPIP_EV_POLL && ev < (int) (sizeof(names) / sizeof(names[0]))) {
+    MG_PROF_ADD(c, names[ev]);
+  }
+#endif
+  // Fire protocol handler first, user handler second. See #2559
+  if (ifp->pfn != NULL) ifp->pfn(ifp, ev, ev_data);
   if (ifp->fn != NULL) ifp->fn(ifp, ev, ev_data);
 }
 
@@ -149,7 +185,7 @@ static void send_syn(struct mg_connection *c);
 
 static void mkpay(struct pkt *pkt, void *p) {
   pkt->pay =
-      mg_str_n((char *) p, (size_t) (&pkt->raw.buf[pkt->raw.len] - (char *) p));
+      mg_str_n((char *) p, (size_t) (&pkt->pay.buf[pkt->pay.len] - (char *) p));
 }
 
 static uint32_t csumup(uint32_t sum, const void *buf, size_t len) {
@@ -412,7 +448,7 @@ static void rx_dhcp_client(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   uint8_t msgtype = 0, state = ifp->state;
   // perform size check first, then access fields
   uint8_t *p = pkt->dhcp->options,
-          *end = (uint8_t *) &pkt->raw.buf[pkt->raw.len];
+          *end = (uint8_t *) &pkt->pay.buf[pkt->pay.len];
   if (end < (uint8_t *) (pkt->dhcp + 1)) return;
   if (memcmp(&pkt->dhcp->xid, ifp->mac + 2, sizeof(pkt->dhcp->xid))) return;
   while (p + 1 < end && p[0] != 255) {  // Parse options RFC-1533 #9
@@ -472,7 +508,7 @@ static void rx_dhcp_client(struct mg_tcpip_if *ifp, struct pkt *pkt) {
 // Simple DHCP server that assigns a next IP address: ifp->ip + 1
 static void rx_dhcp_server(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   uint8_t op = 0, *p = pkt->dhcp->options,
-          *end = (uint8_t *) &pkt->raw.buf[pkt->raw.len];
+          *end = (uint8_t *) &pkt->pay.buf[pkt->pay.len];
   // struct dhcp *req = pkt->dhcp;
   struct dhcp res = {2, 1, 6, 0, 0, 0, 0, 0, 0, 0, 0, {0}, 0, {0}};
   if (end < (uint8_t *) (pkt->dhcp + 1)) return;
@@ -509,26 +545,25 @@ static void rx_dhcp_server(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   }
 }
 
-static void rx_udp(struct mg_tcpip_if *ifp, struct pkt *pkt) {
+static bool rx_udp(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   struct mg_connection *c = getpeer(ifp->mgr, pkt, true);
-  if (c == NULL) {
-    // No UDP listener on this port. Should send ICMP, but keep silent.
+  struct connstate *s;
+  if (c == NULL) return false;  // No UDP listener on this port
+  s = (struct connstate *) (c + 1);
+  c->rem.port = pkt->udp->sport;
+  memcpy(c->rem.ip, &pkt->ip->src, sizeof(uint32_t));
+  memcpy(s->mac, pkt->eth->src, sizeof(s->mac));
+  if (c->recv.len >= MG_MAX_RECV_SIZE) {
+    mg_error(c, "max_recv_buf_size reached");
+  } else if (c->recv.size - c->recv.len < pkt->pay.len &&
+             !mg_iobuf_resize(&c->recv, c->recv.len + pkt->pay.len)) {
+    mg_error(c, "oom");
   } else {
-    struct connstate *s = (struct connstate *) (c + 1);
-    c->rem.port = pkt->udp->sport;
-    memcpy(c->rem.ip, &pkt->ip->src, sizeof(uint32_t));
-    memcpy(s->mac, pkt->eth->src, sizeof(s->mac));
-    if (c->recv.len >= MG_MAX_RECV_SIZE) {
-      mg_error(c, "max_recv_buf_size reached");
-    } else if (c->recv.size - c->recv.len < pkt->pay.len &&
-               !mg_iobuf_resize(&c->recv, c->recv.len + pkt->pay.len)) {
-      mg_error(c, "oom");
-    } else {
-      memcpy(&c->recv.buf[c->recv.len], pkt->pay.buf, pkt->pay.len);
-      c->recv.len += pkt->pay.len;
-      mg_call(c, MG_EV_READ, &pkt->pay.len);
-    }
+    memcpy(&c->recv.buf[c->recv.len], pkt->pay.buf, pkt->pay.len);
+    c->recv.len += pkt->pay.len;
+    mg_call(c, MG_EV_READ, &pkt->pay.len);
   }
+  return true;
 }
 
 static size_t tx_tcp(struct mg_tcpip_if *ifp, uint8_t *dst_mac, uint32_t dst_ip,
@@ -568,17 +603,20 @@ static size_t tx_tcp(struct mg_tcpip_if *ifp, uint8_t *dst_mac, uint32_t dst_ip,
   MG_VERBOSE(("TCP %M:%hu -> %M:%hu fl %x len %u", mg_print_ip4, &ip->src,
               mg_ntohs(tcp->sport), mg_print_ip4, &ip->dst,
               mg_ntohs(tcp->dport), tcp->flags, len));
-  // mg_hexdump(ifp->tx.buf, PDIFF(ifp->tx.buf, tcp + 1) + len);
   return ether_output(ifp, PDIFF(ifp->tx.buf, tcp + 1) + len);
 }
 
-static size_t tx_tcp_pkt(struct mg_tcpip_if *ifp, struct pkt *pkt,
-                         uint8_t flags, uint32_t seq, const void *buf,
-                         size_t len) {
-  uint32_t delta = (pkt->tcp->flags & (TH_SYN | TH_FIN)) ? 1 : 0;
+static size_t tx_tcp_ctrlresp(struct mg_tcpip_if *ifp, struct pkt *pkt,
+                              uint8_t flags, uint32_t seqno) {
+  uint32_t ackno = mg_htonl(mg_ntohl(pkt->tcp->seq) + (uint32_t) pkt->pay.len +
+                            ((pkt->tcp->flags & (TH_SYN | TH_FIN)) ? 1 : 0));
   return tx_tcp(ifp, pkt->eth->src, pkt->ip->src, flags, pkt->tcp->dport,
-                pkt->tcp->sport, seq, mg_htonl(mg_ntohl(pkt->tcp->seq) + delta),
-                buf, len);
+                pkt->tcp->sport, seqno, ackno, NULL, 0);
+}
+
+static size_t tx_tcp_rst(struct mg_tcpip_if *ifp, struct pkt *pkt, bool toack) {
+  return tx_tcp_ctrlresp(ifp, pkt, toack ? TH_RST : (TH_RST | TH_ACK),
+                         toack ? pkt->tcp->ack : 0);
 }
 
 static struct mg_connection *accept_conn(struct mg_connection *lsn,
@@ -642,7 +680,7 @@ static size_t trim_len(struct mg_connection *c, size_t len) {
 long mg_io_send(struct mg_connection *c, const void *buf, size_t len) {
   struct mg_tcpip_if *ifp = c->mgr->ifp;
   struct connstate *s = (struct connstate *) (c + 1);
-  uint32_t dst_ip = *(uint32_t *) c->rem.ip;
+  uint32_t dst_ip = c->rem.ip4;
   len = trim_len(c, len);
   if (c->is_udp) {
     if (!tx_udp(ifp, s->mac, ifp->ip, c->loc.port, dst_ip, c->rem.port, buf,
@@ -689,8 +727,7 @@ static void read_conn(struct mg_connection *c, struct pkt *pkt) {
   struct connstate *s = (struct connstate *) (c + 1);
   struct mg_iobuf *io = c->is_tls ? &c->rtls : &c->recv;
   uint32_t seq = mg_ntohl(pkt->tcp->seq);
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   if (pkt->tcp->flags & TH_FIN) {
     uint8_t flags = TH_ACK;
     if (mg_ntohl(pkt->tcp->seq) != s->ack) {
@@ -777,10 +814,9 @@ static void read_conn(struct mg_connection *c, struct pkt *pkt) {
   }
 }
 
-
 // TCP backlog
 struct mg_backlog {
-  uint16_t port, mss; // use port=0 for available entries
+  uint16_t port, mss;  // use port=0 for available entries
   uint8_t age;
 };
 
@@ -790,7 +826,7 @@ static int backlog_insert(struct mg_connection *c, uint16_t port,
   size_t i;
   for (i = 0; i < sizeof(c->data) / sizeof(*p); i++) {
     if (p[i].port != 0) continue;
-    p[i].age = 2; // remove after two calls, average 1.5 call rate
+    p[i].age = 2;  // remove after two calls, average 1.5 call rate
     p[i].port = port, p[i].mss = mss;
     return (int) i;
   }
@@ -813,7 +849,7 @@ static void backlog_remove(struct mg_connection *c, uint16_t key) {
 
 static void backlog_maintain(struct mg_connection *c) {
   struct mg_backlog *p = (struct mg_backlog *) c->data;
-  size_t i; // dec age and remove those where it reaches 0
+  size_t i;  // dec age and remove those where it reaches 0
   for (i = 0; i < sizeof(c->data) / sizeof(*p); i++) {
     if (p[i].port == 0) continue;
     if (p[i].age != 0) --p[i].age;
@@ -850,88 +886,108 @@ static void handle_opt(struct connstate *s, struct tcp *tcp) {
 static void rx_tcp(struct mg_tcpip_if *ifp, struct pkt *pkt) {
   struct mg_connection *c = getpeer(ifp->mgr, pkt, false);
   struct connstate *s = c == NULL ? NULL : (struct connstate *) (c + 1);
-#if 0
-  MG_INFO(("%lu %hhu %d", c ? c->id : 0, pkt->tcp->flags, (int) pkt->pay.len));
-#endif
+  // Order is VERY important; RFC-9293 3.5.2
+  // - check clients (Group 1) and established connections (Group 3)
   if (c != NULL && c->is_connecting && pkt->tcp->flags == (TH_SYN | TH_ACK)) {
+    // client got a server connection accept
     handle_opt(s, pkt->tcp);  // process options (MSS)
     s->seq = mg_ntohl(pkt->tcp->ack), s->ack = mg_ntohl(pkt->tcp->seq) + 1;
-    tx_tcp_pkt(ifp, pkt, TH_ACK, pkt->tcp->ack, NULL, 0);
+    tx_tcp_ctrlresp(ifp, pkt, TH_ACK, pkt->tcp->ack);
     c->is_connecting = 0;  // Client connected
     settmout(c, MIP_TTYPE_KEEPALIVE);
     mg_call(c, MG_EV_CONNECT, NULL);  // Let user know
     if (c->is_tls_hs) mg_tls_handshake(c);
     if (!c->is_tls_hs) c->is_tls = 0;  // user did not call mg_tls_init()
   } else if (c != NULL && c->is_connecting && pkt->tcp->flags != TH_ACK) {
-    // mg_hexdump(pkt->raw.buf, pkt->raw.len);
-    tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
+    mg_error(c, "connection refused");
   } else if (c != NULL && pkt->tcp->flags & TH_RST) {
+    // TODO(): validate RST is within window (and optional with proper ACK)
     mg_error(c, "peer RST");  // RFC-1122 4.2.2.13
   } else if (c != NULL) {
-#if 0
-    MG_DEBUG(("%lu %d %M:%hu -> %M:%hu", c->id, (int) pkt->raw.len,
-              mg_print_ip4, &pkt->ip->src, mg_ntohs(pkt->tcp->sport),
-              mg_print_ip4, &pkt->ip->dst, mg_ntohs(pkt->tcp->dport)));
-    mg_hexdump(pkt->pay.buf, pkt->pay.len);
-#endif
+    // process segment
     s->tmiss = 0;                         // Reset missed keep-alive counter
     if (s->ttype == MIP_TTYPE_KEEPALIVE)  // Advance keep-alive timer
       settmout(c,
                MIP_TTYPE_KEEPALIVE);  // unless a former ACK timeout is pending
     read_conn(c, pkt);  // Override timer with ACK timeout if needed
-  } else if ((c = getpeer(ifp->mgr, pkt, true)) == NULL) {
-    tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
-  } else if (pkt->tcp->flags & TH_RST) {
-    if (c->is_accepted) mg_error(c, "peer RST");  // RFC-1122 4.2.2.13
-    // ignore RST if not connected
-  } else if (pkt->tcp->flags & TH_SYN) {
-    struct connstate cs;  // At this point, s = NULL, there is no connection
-    int key;
-    uint32_t isn;
-    if (pkt->tcp->sport != 0) {
-      handle_opt(&cs, pkt->tcp);                          // process options (MSS)
-      key = backlog_insert(c, pkt->tcp->sport, cs.dmss);  // backlog options (MSS)
-      if (key < 0) return;  // no room in backlog, discard SYN, client retries
-      // Use peer's src port and bl key as ISN, to later identify the handshake
-      isn = (mg_htonl(((uint32_t)key << 16) | mg_ntohs(pkt->tcp->sport)));
-      tx_tcp_pkt(ifp, pkt, TH_SYN | TH_ACK, isn, NULL, 0);
-    } // what should we do when port=0 ? Linux takes port 0 as any other port
-  } else if (pkt->tcp->flags & TH_FIN) {
-    tx_tcp_pkt(ifp, pkt, TH_FIN | TH_ACK, pkt->tcp->ack, NULL, 0);
-  } else if ((uint16_t) (mg_htonl(pkt->tcp->ack) - 1) ==
-             mg_htons(pkt->tcp->sport)) {
-    uint16_t key = (uint16_t) ((mg_htonl(pkt->tcp->ack) - 1) >> 16);
-    struct mg_backlog *b = backlog_retrieve(c, key, pkt->tcp->sport);
-    if (b != NULL) {
-      accept_conn(c, pkt, b->mss);  // pass options
-      backlog_remove(c, key);
-    } else if (!c->is_accepted) {         // not an actual match, reset
-      tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
-      // TODO(scaprile): revisit this and below, weird scenarios
-    }
-  } else if (!c->is_accepted) {  // no peer
-    tx_tcp_pkt(ifp, pkt, TH_RST | TH_ACK, pkt->tcp->ack, NULL, 0);
-  } else {
-    // MG_VERBOSE(("dropped silently.."));
-  }
+  } else
+    // - we don't listen on that port; RFC-9293 3.5.2 Group 1
+    // - check listening connections; RFC-9293 3.5.2 Group 2
+    if ((c = getpeer(ifp->mgr, pkt, true)) == NULL) {
+      // not listening on that port
+      if (!(pkt->tcp->flags & TH_RST)) {
+        tx_tcp_rst(ifp, pkt, pkt->tcp->flags & TH_ACK);
+      }  // else silently discard
+    } else if (pkt->tcp->flags == TH_SYN) {
+      // listener receives a connection request
+      struct connstate cs;  // At this point, s = NULL, there is no connection
+      int key;
+      uint32_t isn;
+      if (pkt->tcp->sport != 0) {
+        handle_opt(&cs, pkt->tcp);  // process options (MSS)
+        key = backlog_insert(c, pkt->tcp->sport,
+                             cs.dmss);  // backlog options (MSS)
+        if (key < 0) return;  // no room in backlog, discard SYN, client retries
+        // Use peer's src port and bl key as ISN, to later identify the
+        // handshake
+        isn = (mg_htonl(((uint32_t) key << 16) | mg_ntohs(pkt->tcp->sport)));
+        tx_tcp_ctrlresp(ifp, pkt, TH_SYN | TH_ACK, isn);
+      }  // what should we do when port=0 ? Linux takes port 0 as any other
+         // port
+    } else if (pkt->tcp->flags == TH_ACK) {
+      // listener receives an ACK
+      struct mg_backlog *b = NULL;
+      if ((uint16_t) (mg_htonl(pkt->tcp->ack) - 1) ==
+          mg_htons(pkt->tcp->sport)) {
+        uint16_t key = (uint16_t) ((mg_htonl(pkt->tcp->ack) - 1) >> 16);
+        b = backlog_retrieve(c, key, pkt->tcp->sport);
+        if (b != NULL) {                // ACK is a response to a SYN+ACK
+          accept_conn(c, pkt, b->mss);  // pass options
+          backlog_remove(c, key);
+        }  // else not an actual match, reset
+      }
+      if (b == NULL) tx_tcp_rst(ifp, pkt, true);
+    } else if (pkt->tcp->flags & TH_RST) {
+      // silently discard
+    } else if (pkt->tcp->flags & TH_ACK) {  // ACK + something else != RST
+      tx_tcp_rst(ifp, pkt, true);
+    } else if (pkt->tcp->flags & TH_SYN) {  // SYN + something else != ACK
+      tx_tcp_rst(ifp, pkt, false);
+    }  // else  silently discard
 }
 
 static void rx_ip(struct mg_tcpip_if *ifp, struct pkt *pkt) {
-  uint16_t frag = mg_ntohs(pkt->ip->frag);
+  uint8_t ihl;
+  uint16_t frag, len;
+  if (pkt->pay.len < sizeof(*pkt->ip)) return;  // Truncated
+  if ((pkt->ip->ver >> 4) != 4) return;         // Not IP
+  ihl = pkt->ip->ver & 0x0F;
+  if (ihl < 5) return;                     // bad IHL
+  if (pkt->pay.len < (ihl * 4)) return;    // Truncated / malformed
+  // There can be link padding, take length from IP header
+  len = mg_ntohs(pkt->ip->len); // IP datagram length
+  if (len < (ihl * 4) || len > pkt->pay.len) return; // malformed
+  pkt->pay.len = len; // strip padding
+  mkpay(pkt, (uint32_t *) pkt->ip + ihl);  // account for opts
+  frag = mg_ntohs(pkt->ip->frag);
   if (frag & IP_MORE_FRAGS_MSK || frag & IP_FRAG_OFFSET_MSK) {
     struct mg_connection *c;
-    if (pkt->ip->proto == 17) pkt->udp = (struct udp *) (pkt->ip + 1);
-    if (pkt->ip->proto == 6) pkt->tcp = (struct tcp *) (pkt->ip + 1);
+    if (pkt->ip->proto == 17) pkt->udp = (struct udp *) (pkt->pay.buf);
+    if (pkt->ip->proto == 6) pkt->tcp = (struct tcp *) (pkt->pay.buf);
     c = getpeer(ifp->mgr, pkt, false);
     if (c) mg_error(c, "Received fragmented packet");
   } else if (pkt->ip->proto == 1) {
-    pkt->icmp = (struct icmp *) (pkt->ip + 1);
+    pkt->icmp = (struct icmp *) (pkt->pay.buf);
     if (pkt->pay.len < sizeof(*pkt->icmp)) return;
     mkpay(pkt, pkt->icmp + 1);
     rx_icmp(ifp, pkt);
   } else if (pkt->ip->proto == 17) {
-    pkt->udp = (struct udp *) (pkt->ip + 1);
-    if (pkt->pay.len < sizeof(*pkt->udp)) return;
+    pkt->udp = (struct udp *) (pkt->pay.buf);
+    if (pkt->pay.len < sizeof(*pkt->udp)) return; // truncated
+    // Take length from UDP header
+    len = mg_ntohs(pkt->udp->len); // UDP datagram length
+    if (len < sizeof(*pkt->udp) || len > pkt->pay.len) return; // malformed
+    pkt->pay.len = len; // strip excess data
     mkpay(pkt, pkt->udp + 1);
     MG_VERBOSE(("UDP %M:%hu -> %M:%hu len %u", mg_print_ip4, &pkt->ip->src,
                 mg_ntohs(pkt->udp->sport), mg_print_ip4, &pkt->ip->dst,
@@ -944,47 +1000,115 @@ static void rx_ip(struct mg_tcpip_if *ifp, struct pkt *pkt) {
       pkt->dhcp = (struct dhcp *) (pkt->udp + 1);
       mkpay(pkt, pkt->dhcp + 1);
       rx_dhcp_server(ifp, pkt);
-    } else {
-      rx_udp(ifp, pkt);
+    } else if (!rx_udp(ifp, pkt)) {
+      // Should send ICMP Destination Unreachable for unicasts, but keep silent
     }
   } else if (pkt->ip->proto == 6) {
-    uint16_t iplen, off;
-    pkt->tcp = (struct tcp *) (pkt->ip + 1);
+    uint8_t off;
+    pkt->tcp = (struct tcp *) (pkt->pay.buf);
     if (pkt->pay.len < sizeof(*pkt->tcp)) return;
-    mkpay(pkt, pkt->tcp + 1);
-    iplen = mg_ntohs(pkt->ip->len);
-    off = (uint16_t) (sizeof(*pkt->ip) + ((pkt->tcp->off >> 4) * 4U));
-    if (iplen >= off) pkt->pay.len = (size_t) (iplen - off);
+    off = pkt->tcp->off >> 4;  // account for opts
+    if (pkt->pay.len < (4 * off)) return;
+    mkpay(pkt, (uint32_t *) pkt->tcp + off);
     MG_VERBOSE(("TCP %M:%hu -> %M:%hu len %u", mg_print_ip4, &pkt->ip->src,
                 mg_ntohs(pkt->tcp->sport), mg_print_ip4, &pkt->ip->dst,
                 mg_ntohs(pkt->tcp->dport), (int) pkt->pay.len));
     rx_tcp(ifp, pkt);
+  } else {
+    MG_DEBUG(("Unknown IP proto %x", (int) pkt->ip->proto));
+    if (mg_log_level >= MG_LL_VERBOSE)
+      mg_hexdump(pkt->ip, pkt->pay.len >= 32 ? 32 : pkt->pay.len);
   }
 }
 
 static void rx_ip6(struct mg_tcpip_if *ifp, struct pkt *pkt) {
-  // MG_DEBUG(("IP %d", (int) len));
-  if (pkt->ip6->proto == 1 || pkt->ip6->proto == 58) {
-    pkt->icmp = (struct icmp *) (pkt->ip6 + 1);
-    if (pkt->pay.len < sizeof(*pkt->icmp)) return;
-    mkpay(pkt, pkt->icmp + 1);
-    rx_icmp(ifp, pkt);
-  } else if (pkt->ip6->proto == 17) {
-    pkt->udp = (struct udp *) (pkt->ip6 + 1);
+  uint16_t len = 0;
+  uint8_t next, *nhdr;
+  bool loop = true;
+  if (pkt->pay.len < sizeof(*pkt->ip6)) return;  // Truncated
+  if ((pkt->ip6->ver >> 4) != 0x6) return;       // Not IPv6
+  next = pkt->ip6->next;
+  nhdr = (uint8_t *) (pkt->ip6 + 1);
+  while (loop) {
+    switch (next) {
+      case 0:   // Hop-by-Hop 4.3
+      case 43:  // Routing 4.4
+      case 60:  // Destination Options 4.6
+      case 51:  // Authentication RFC-4302
+        MG_INFO(("IPv6 extension header %d", (int) next));
+        next = nhdr[0];
+        len += (uint16_t)(8 * (nhdr[1] + 1));
+        nhdr += 8 * (nhdr[1] + 1);
+        break;
+      case 44:  // Fragment 4.5
+      {
+        struct mg_connection *c;
+        if (nhdr[0] == 17) pkt->udp = (struct udp *) (pkt->pay.buf);
+        if (nhdr[0] == 6) pkt->tcp = (struct tcp *) (pkt->pay.buf);
+        c = getpeer(ifp->mgr, pkt, false);
+        if (c) mg_error(c, "Received fragmented packet");
+      }
+        return;
+      case 59:  // No Next Header 4.7
+        return;
+      case 50:  // IPsec ESP RFC-4303, unsupported
+      default:
+        loop = false;
+        break;
+    }
+  }
+  // There can be link padding, take payload length from IPv6 header - options
+  pkt->pay.buf = (char *) nhdr;
+  pkt->pay.len = mg_ntohs(pkt->ip6->plen) - len;
+  if (next == 58) {
+    pkt->icmp6 = (struct icmp6 *) (pkt->pay.buf);
+    if (pkt->pay.len < sizeof(*pkt->icmp6)) return;
+    mkpay(pkt, pkt->icmp6 + 1);
+    MG_DEBUG(("ICMPv6 %M -> %M len %u", mg_print_ip6, &pkt->ip6->src,
+              mg_print_ip6, &pkt->ip6->dst, (int) pkt->pay.len));
+    // rx_icmp6(ifp, pkt);
+  } else if (next == 17) {
+    pkt->udp = (struct udp *) (pkt->pay.buf);
     if (pkt->pay.len < sizeof(*pkt->udp)) return;
-    // MG_DEBUG(("  UDP %u %u -> %u", len, mg_htons(udp->sport),
-    // mg_htons(udp->dport)));
     mkpay(pkt, pkt->udp + 1);
+    MG_DEBUG(("UDP %M:%hu -> %M:%hu len %u", mg_print_ip6, &pkt->ip6->src,
+              mg_ntohs(pkt->udp->sport), mg_print_ip6, &pkt->ip6->dst,
+              mg_ntohs(pkt->udp->dport), (int) pkt->pay.len));
+    if (ifp->enable_dhcp_client && pkt->udp->dport == mg_htons(546)) {
+      pkt->dhcp6 = (struct dhcp6 *) (pkt->udp + 1);
+      mkpay(pkt, pkt->dhcp6 + 1);
+      // rx_dhcp6_client(ifp, pkt);
+    } else if (ifp->enable_dhcp_server && pkt->udp->dport == mg_htons(547)) {
+      pkt->dhcp6 = (struct dhcp6 *) (pkt->udp + 1);
+      mkpay(pkt, pkt->dhcp6 + 1);
+      // rx_dhcp6_server(ifp, pkt);
+    } else if (!rx_udp(ifp, pkt)) {
+      // Should send ICMPv6 Destination Unreachable for unicasts, keep silent
+    }
+  } else if (next == 6) {
+    uint8_t off;
+    pkt->tcp = (struct tcp *) (pkt->pay.buf);
+    if (pkt->pay.len < sizeof(*pkt->tcp)) return;
+    off = pkt->tcp->off >> 4;  // account for opts
+    if (pkt->pay.len < sizeof(*pkt->tcp) + 4 * off) return;
+    mkpay(pkt, (uint32_t *) pkt->tcp + off);
+    MG_DEBUG(("TCP %M:%hu -> %M:%hu len %u", mg_print_ip6, &pkt->ip6->src,
+              mg_ntohs(pkt->tcp->sport), mg_print_ip6, &pkt->ip6->dst,
+              mg_ntohs(pkt->tcp->dport), (int) pkt->pay.len));
+    rx_tcp(ifp, pkt);
+  } else {
+    MG_DEBUG(("Unknown IPv6 next hdr %x", (int) next));
+    if (mg_log_level >= MG_LL_VERBOSE)
+      mg_hexdump(pkt->ip6, pkt->pay.len >= 32 ? 32 : pkt->pay.len);
   }
 }
 
 static void mg_tcpip_rx(struct mg_tcpip_if *ifp, void *buf, size_t len) {
   struct pkt pkt;
   memset(&pkt, 0, sizeof(pkt));
-  pkt.raw.buf = (char *) buf;
-  pkt.raw.len = len;
-  pkt.eth = (struct eth *) buf;
-  // mg_hexdump(buf, len > 16 ? 16: len);
+  pkt.pay.buf = pkt.raw.buf = (char *) buf;
+  pkt.pay.len = pkt.raw.len = len; // payload = raw
+  pkt.eth = (struct eth *) buf;   // Ethernet = raw
   if (pkt.raw.len < sizeof(*pkt.eth)) return;  // Truncated - runt?
   if (ifp->enable_mac_check &&
       memcmp(pkt.eth->dst, ifp->mac, sizeof(pkt.eth->dst)) != 0 &&
@@ -995,28 +1119,19 @@ static void mg_tcpip_rx(struct mg_tcpip_if *ifp, void *buf, size_t len) {
     len -= 4;  // TODO(scaprile): check on bigendian
     crc = mg_crc32(0, (const char *) buf, len);
     if (memcmp((void *) ((size_t) buf + len), &crc, sizeof(crc))) return;
+    pkt.pay.len = len;
   }
+  mkpay(&pkt, pkt.eth + 1);
   if (pkt.eth->type == mg_htons(0x806)) {
-    pkt.arp = (struct arp *) (pkt.eth + 1);
-    if (sizeof(*pkt.eth) + sizeof(*pkt.arp) > pkt.raw.len) return;  // Truncated
+    pkt.arp = (struct arp *) (pkt.pay.buf);
+    if (pkt.pay.len < sizeof(*pkt.arp)) return; // Truncated
     mg_tcpip_call(ifp, MG_TCPIP_EV_ARP, &pkt.raw);
     rx_arp(ifp, &pkt);
   } else if (pkt.eth->type == mg_htons(0x86dd)) {
-    pkt.ip6 = (struct ip6 *) (pkt.eth + 1);
-    if (pkt.raw.len < sizeof(*pkt.eth) + sizeof(*pkt.ip6)) return;  // Truncated
-    if ((pkt.ip6->ver >> 4) != 0x6) return;                         // Not IP
-    mkpay(&pkt, pkt.ip6 + 1);
+    pkt.ip6 = (struct ip6 *) (pkt.pay.buf);
     rx_ip6(ifp, &pkt);
   } else if (pkt.eth->type == mg_htons(0x800)) {
-    pkt.ip = (struct ip *) (pkt.eth + 1);
-    if (pkt.raw.len < sizeof(*pkt.eth) + sizeof(*pkt.ip)) return;  // Truncated
-    // Truncate frame to what IP header tells us
-    if ((size_t) mg_ntohs(pkt.ip->len) + sizeof(struct eth) < pkt.raw.len) {
-      pkt.raw.len = (size_t) mg_ntohs(pkt.ip->len) + sizeof(struct eth);
-    }
-    if (pkt.raw.len < sizeof(*pkt.eth) + sizeof(*pkt.ip)) return;  // Truncated
-    if ((pkt.ip->ver >> 4) != 4) return;                           // Not IP
-    mkpay(&pkt, pkt.ip + 1);
+    pkt.ip = (struct ip *) (pkt.pay.buf);
     rx_ip(ifp, &pkt);
   } else {
     MG_DEBUG(("Unknown eth type %x", mg_htons(pkt.eth->type)));
@@ -1107,7 +1222,7 @@ static void mg_tcpip_poll(struct mg_tcpip_if *ifp, uint64_t now) {
     uint32_t rem_ip;
     if ((c->is_udp && !c->is_arplooking) || c->is_listening || c->is_resolving)
       continue;
-    memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+    rem_ip = c->rem.ip4;
     if (ifp->now > s->timer) {
       if (s->ttype == MIP_TTYPE_ARP) {
         mg_error(c, "ARP timeout");
@@ -1198,8 +1313,7 @@ void mg_tcpip_free(struct mg_tcpip_if *ifp) {
 static void send_syn(struct mg_connection *c) {
   struct connstate *s = (struct connstate *) (c + 1);
   uint32_t isn = mg_htonl((uint32_t) mg_ntohs(c->loc.port));
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   tx_tcp(c->mgr->ifp, s->mac, rem_ip, TH_SYN, c->loc.port, c->rem.port, isn, 0,
          NULL, 0);
 }
@@ -1223,11 +1337,10 @@ static void ip4_mcastmac(uint8_t *mac, uint32_t *ip) {
 
 void mg_connect_resolved(struct mg_connection *c) {
   struct mg_tcpip_if *ifp = c->mgr->ifp;
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   c->is_resolving = 0;
   if (ifp->eport < MG_EPHEMERAL_PORT_BASE) ifp->eport = MG_EPHEMERAL_PORT_BASE;
-  memcpy(c->loc.ip, &ifp->ip, sizeof(uint32_t));
+  c->loc.ip4 = ifp->ip;
   c->loc.port = mg_htons(ifp->eport++);
   MG_DEBUG(("%lu %M -> %M", c->id, mg_print_ip_port, &c->loc, mg_print_ip_port,
             &c->rem));
@@ -1279,8 +1392,7 @@ static void init_closure(struct mg_connection *c) {
   struct connstate *s = (struct connstate *) (c + 1);
   if (c->is_udp == false && c->is_listening == false &&
       c->is_connecting == false) {  // For TCP conns,
-    uint32_t rem_ip;
-    memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
     tx_tcp(c->mgr->ifp, s->mac, rem_ip, TH_FIN | TH_ACK, c->loc.port,
            c->rem.port, mg_htonl(s->seq), mg_htonl(s->ack), NULL, 0);
     settmout(c, MIP_TTYPE_FIN);
@@ -1334,8 +1446,7 @@ void mg_mgr_poll(struct mg_mgr *mgr, int ms) {
 bool mg_send(struct mg_connection *c, const void *buf, size_t len) {
   struct mg_tcpip_if *ifp = c->mgr->ifp;
   bool res = false;
-  uint32_t rem_ip;
-  memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
+  uint32_t rem_ip = c->rem.ip4;
   if (ifp->ip == 0 || ifp->state != MG_TCPIP_STATE_READY) {
     mg_error(c, "net down");
   } else if (c->is_udp && (c->is_arplooking || c->is_resolving)) {
diff --git a/src/net_builtin.h b/src/net_builtin.h
index c4316d21ca..b3c1494c32 100644
--- a/src/net_builtin.h
+++ b/src/net_builtin.h
@@ -20,19 +20,20 @@ typedef void (*mg_tcpip_event_handler_t)(struct mg_tcpip_if *ifp, int ev,
                                          void *ev_data);
 
 enum {
-  MG_TCPIP_EV_ST_CHG,           // state change                   uint8_t * (&ifp->state)
-  MG_TCPIP_EV_DHCP_DNS,         // DHCP DNS assignment            uint32_t *ipaddr
-  MG_TCPIP_EV_DHCP_SNTP,        // DHCP SNTP assignment           uint32_t *ipaddr
-  MG_TCPIP_EV_ARP,              // Got ARP packet                 struct mg_str *
-  MG_TCPIP_EV_TIMER_1S,         // 1 second timer                 NULL
-  MG_TCPIP_EV_WIFI_SCAN_RESULT, // Wi-Fi scan results             struct mg_wifi_scan_bss_data *
-  MG_TCPIP_EV_WIFI_SCAN_END,    // Wi-Fi scan has finished        NULL
-  MG_TCPIP_EV_WIFI_CONNECT_ERR, // Wi-Fi connect has failed       driver and chip specific
-  MG_TCPIP_EV_DRIVER,           // Driver event                   driver specific
-  MG_TCPIP_EV_USER              // Starting ID for user events
+  MG_TCPIP_EV_ST_CHG,  // state change                   uint8_t * (&ifp->state)
+  MG_TCPIP_EV_DHCP_DNS,   // DHCP DNS assignment            uint32_t *ipaddr
+  MG_TCPIP_EV_DHCP_SNTP,  // DHCP SNTP assignment           uint32_t *ipaddr
+  MG_TCPIP_EV_ARP,        // Got ARP packet                 struct mg_str *
+  MG_TCPIP_EV_TIMER_1S,   // 1 second timer                 NULL
+  MG_TCPIP_EV_WIFI_SCAN_RESULT,  // Wi-Fi scan results             struct
+                                 // mg_wifi_scan_bss_data *
+  MG_TCPIP_EV_WIFI_SCAN_END,     // Wi-Fi scan has finished        NULL
+  MG_TCPIP_EV_WIFI_CONNECT_ERR,  // Wi-Fi connect has failed       driver and
+                                 // chip specific
+  MG_TCPIP_EV_DRIVER,  // Driver event                   driver specific
+  MG_TCPIP_EV_USER     // Starting ID for user events
 };
 
-
 // Network interface
 struct mg_tcpip_if {
   uint8_t mac[6];                  // MAC address. Must be set to a valid MAC
@@ -48,11 +49,12 @@ struct mg_tcpip_if {
   bool update_mac_hash_table;      // Signal drivers to update MAC controller
   struct mg_tcpip_driver *driver;  // Low level driver
   void *driver_data;               // Driver-specific data
+  mg_tcpip_event_handler_t pfn;    // Driver-specific event handler function
   mg_tcpip_event_handler_t fn;     // User-specified event handler function
   struct mg_mgr *mgr;              // Mongoose event manager
   struct mg_queue recv_queue;      // Receive queue
-  char dhcp_name[12];              // Name reported to DHCP, "mip" if unset
-  uint16_t mtu;                    // Interface MTU
+  char dhcp_name[MG_TCPIP_DHCPNAME_SIZE];  // Name for DHCP, "mip" if unset
+  uint16_t mtu;                            // Interface MTU
 #define MG_TCPIP_MTU_DEFAULT 1500
 
   // Internal state, user can use it but should not change it
@@ -95,6 +97,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_ppp;
 extern struct mg_tcpip_driver mg_tcpip_driver_pico_w;
 extern struct mg_tcpip_driver mg_tcpip_driver_rw612;
 extern struct mg_tcpip_driver mg_tcpip_driver_cyw;
+extern struct mg_tcpip_driver mg_tcpip_driver_nxp_wifi;
 
 // Drivers that require SPI, can use this SPI abstraction
 struct mg_tcpip_spi {
@@ -104,5 +107,4 @@ struct mg_tcpip_spi {
   uint8_t (*txn)(void *, uint8_t);  // SPI transaction: write 1 byte, read reply
 };
 
-
 #endif
diff --git a/src/printf.c b/src/printf.c
index d9998ccfb2..1b6107acf8 100644
--- a/src/printf.c
+++ b/src/printf.c
@@ -3,7 +3,9 @@
 #include "util.h"
 
 size_t mg_queue_vprintf(struct mg_queue *q, const char *fmt, va_list *ap) {
-  size_t len = mg_snprintf(NULL, 0, fmt, ap);
+  va_list ap_copy;
+  va_copy(ap_copy, *ap);
+  size_t len = mg_vsnprintf(NULL, 0, fmt, &ap_copy);
   char *buf;
   if (len == 0 || mg_queue_book(q, &buf, len + 1) < len + 1) {
     len = 0;  // Nah. Not enough space
diff --git a/src/sock.c b/src/sock.c
index 84694896d1..ac9fcd4ea2 100644
--- a/src/sock.c
+++ b/src/sock.c
@@ -181,7 +181,7 @@ static void mg_set_non_blocking_mode(MG_SOCKET_TYPE fd) {
 void mg_multicast_add(struct mg_connection *c, char *ip);
 void mg_multicast_add(struct mg_connection *c, char *ip) {
 #if MG_ENABLE_RL
-#error UNSUPPORTED
+  MG_ERROR(("unsupported"));
 #elif MG_ENABLE_FREERTOS_TCP
   // TODO(): prvAllowIPPacketIPv4()
 #else
diff --git a/src/tls_builtin.c b/src/tls_builtin.c
index 25a7ccfff6..864e10a0ef 100644
--- a/src/tls_builtin.c
+++ b/src/tls_builtin.c
@@ -42,6 +42,8 @@ enum mg_tls_hs_state {
 
   // Server state machine:
   MG_TLS_STATE_SERVER_START,       // Wait for ClientHello
+  MG_TLS_STATE_SERVER_WAIT_CERT,   // Wait for Certificate
+  MG_TLS_STATE_SERVER_WAIT_CV,     // Wait for CertificateVerify
   MG_TLS_STATE_SERVER_NEGOTIATED,  // Wait for Finish
   MG_TLS_STATE_SERVER_CONNECTED    // Done
 };
@@ -77,14 +79,15 @@ struct tls_data {
   uint8_t x25519_cli[32];  // client X25519 key between the handshake states
   uint8_t x25519_sec[32];  // x25519 secret between the handshake states
 
-  int skip_verification;   // perform checks on server certificate?
-  int cert_requested;      // client received a CertificateRequest?
+  bool skip_verification;  // do not perform checks on server certificate
+  bool cert_requested;     // client received a CertificateRequest
+  bool is_twoway;          // server is configured to authenticate clients
   struct mg_str cert_der;  // certificate in DER format
   struct mg_str ca_der;    // CA certificate
   uint8_t ec_key[32];      // EC private key
-  char hostname[254];      // server hostname (client extension)
+  char hostname[254];      // matching hostname
 
-  int is_ec_pubkey;          // EC or RSA?
+  bool is_ec_pubkey;         // EC or RSA
   uint8_t pubkey[512 + 16];  // server EC (64) or RSA (512+exp) public key to
                              // verify cert
   size_t pubkeysz;           // size of the server public key
@@ -530,18 +533,18 @@ static int mg_tls_recv_record(struct mg_connection *c) {
 }
 
 static void mg_tls_calc_cert_verify_hash(struct mg_connection *c,
-                                         uint8_t hash[32], int is_client) {
+                                         uint8_t hash[32], bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
-  uint8_t server_context[34] = "TLS 1.3, server CertificateVerify";
-  uint8_t client_context[34] = "TLS 1.3, client CertificateVerify";
   uint8_t sig_content[130];
   mg_sha256_ctx sha256;
 
   memset(sig_content, 0x20, 64);
   if (is_client) {
-    memmove(sig_content + 64, client_context, sizeof(client_context));
+    uint8_t client_context[34] = "TLS 1.3, client CertificateVerify";
+    memcpy(sig_content + 64, client_context, sizeof(client_context));
   } else {
-    memmove(sig_content + 64, server_context, sizeof(server_context));
+    uint8_t server_context[34] = "TLS 1.3, server CertificateVerify";
+    memcpy(sig_content + 64, server_context, sizeof(server_context));
   }
 
   memmove(&sha256, &tls->sha256, sizeof(mg_sha256_ctx));
@@ -683,17 +686,46 @@ static void mg_tls_server_send_ext(struct mg_connection *c) {
   mg_tls_encrypt(c, ext, sizeof(ext), MG_TLS_HANDSHAKE);
 }
 
-static void mg_tls_server_send_cert(struct mg_connection *c) {
+// signature algorithms we actually support:
+// rsa_pkcs1_sha256, rsa_pss_rsae_sha256 and ecdsa_secp256r1_sha256
+static const uint8_t secp256r1_sig_algs[12] = {
+    0x00, 0x0d, 0x00, 0x08, 0x00, 0x06, 0x04, 0x03, 0x08, 0x04, 0x04, 0x01,
+};
+
+static void mg_tls_server_send_cert_request(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
-  int send_ca = !c->is_client && tls->ca_der.len > 0;
-  // server DER certificate + CA (optional)
+  size_t n = sizeof(secp256r1_sig_algs) + 6;
+  uint8_t *req = (uint8_t *) mg_calloc(1, 13 + n);
+  if (req == NULL) {
+    mg_error(c, "tls cert req oom");
+    return;
+  }
+  req[0] = MG_TLS_CERTIFICATE_REQUEST;  // handshake header
+  MG_STORE_BE24(req + 1, n + 9);
+  req[4] = 0;                  // context length
+  MG_STORE_BE16(req + 5, n);   // extensions length
+  MG_STORE_BE16(req + 7, 13);  // "signature algorithms"
+  MG_STORE_BE16(req + 9, sizeof(secp256r1_sig_algs) + 2);  // length
+  MG_STORE_BE16(
+      req + 11,
+      sizeof(secp256r1_sig_algs));  // signature hash algorithms length
+  memcpy(req + 13, (uint8_t *) secp256r1_sig_algs, sizeof(secp256r1_sig_algs));
+  mg_sha256_update(&tls->sha256, req, 13 + n);
+  mg_tls_encrypt(c, req, 13 + n, MG_TLS_HANDSHAKE);
+  mg_free(req);
+}
+
+static void mg_tls_send_cert(struct mg_connection *c, bool is_client) {
+  struct tls_data *tls = (struct tls_data *) c->tls;
+  int send_ca = !is_client && tls->ca_der.len > 0;
+  // DER certificate + CA (server optional)
   size_t n = tls->cert_der.len + (send_ca ? tls->ca_der.len + 5 : 0);
   uint8_t *cert = (uint8_t *) mg_calloc(1, 13 + n);
   if (cert == NULL) {
     mg_error(c, "tls cert oom");
     return;
   }
-  cert[0] = 0x0b;  // handshake header
+  cert[0] = MG_TLS_CERTIFICATE;  // handshake header
   MG_STORE_BE24(cert + 1, n + 9);
   cert[4] = 0;                                 // request context
   MG_STORE_BE24(cert + 5, n + 5);              // 3 bytes: cert (s) length
@@ -736,7 +768,7 @@ static void finish_SHA256(const MG_UECC_HashContext *base,
   mg_sha256_final(hash_result, &c->ctx);
 }
 
-static void mg_tls_send_cert_verify(struct mg_connection *c, int is_client) {
+static void mg_tls_send_cert_verify(struct mg_connection *c, bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   // server certificate verify packet
   uint8_t verify[82] = {0x0f, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00};
@@ -813,12 +845,9 @@ static void mg_tls_client_send_hello(struct mg_connection *c) {
 
   uint8_t x25519_pub[X25519_BYTES];
 
-  // signature algorithms we actually support:
-  // rsa_pkcs1_sha256, rsa_pss_rsae_sha256 and ecdsa_secp256r1_sha256
-  uint8_t secp256r1_sig_algs[12] = {
-      0x00, 0x0d, 0x00, 0x08, 0x00, 0x06, 0x04, 0x03, 0x08, 0x04, 0x04, 0x01,
-  };
-  // all popular signature algorithms (if we don't care about verification)
+  // - "signature algorithms we actually support", see above
+  //   uint8_t secp256r1_sig_algs[]
+  // - all popular signature algorithms (if we don't care about verification)
   uint8_t all_sig_algs[34] = {
       0x00, 0x0d, 0x00, 0x1e, 0x00, 0x1c, 0x04, 0x03, 0x05, 0x03, 0x06, 0x03,
       0x08, 0x07, 0x08, 0x08, 0x08, 0x09, 0x08, 0x0a, 0x08, 0x0b, 0x08, 0x04,
@@ -862,7 +891,8 @@ static void mg_tls_client_send_hello(struct mg_connection *c) {
   const char *hostname = tls->hostname;
   size_t hostnamesz = strlen(tls->hostname);
   size_t hostname_extsz = hostnamesz ? hostnamesz + 9 : 0;
-  uint8_t *sig_alg = tls->skip_verification ? all_sig_algs : secp256r1_sig_algs;
+  uint8_t *sig_alg =
+      tls->skip_verification ? all_sig_algs : (uint8_t *) secp256r1_sig_algs;
   size_t sig_alg_sz = tls->skip_verification ? sizeof(all_sig_algs)
                                              : sizeof(secp256r1_sig_algs);
 
@@ -1237,7 +1267,7 @@ static int mg_tls_verify_cert_cn(struct mg_der_tlv *subj, const char *host) {
   return matched;
 }
 
-static int mg_tls_client_recv_cert(struct mg_connection *c) {
+static int mg_tls_recv_cert(struct mg_connection *c, bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   unsigned char *recv_buf;
 
@@ -1255,7 +1285,8 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
   }
 
   if (recv_buf[0] != MG_TLS_CERTIFICATE) {
-    mg_error(c, "expected server certificate but got msg 0x%02x", recv_buf[0]);
+    mg_error(c, "expected %s certificate but got msg 0x%02x",
+             is_client ? "server" : "client", recv_buf[0]);
     return -1;
   }
 
@@ -1265,7 +1296,7 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
   }
 
   {
-    // Normally, there are 2-3 certs in a chain
+    // Normally, there are 2-3 certs in a chain (when is_client)
     struct mg_tls_cert certs[8];
     int certnum = 0;
     uint32_t full_cert_chain_len = MG_LOAD_BE24(recv_buf + 1);
@@ -1310,9 +1341,10 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
       }
 
       if (ci == certs) {
-        // First certificate in the chain is peer cert, check SAN and store
-        // public key for further CertVerify step
-        if (mg_tls_verify_cert_san(cert, certsz, tls->hostname) <= 0 &&
+        // First certificate in the chain is peer cert, check SAN if requested,
+        // and store public key for further CertVerify step
+        if (tls->hostname != NULL && *tls->hostname != '\0' &&
+            mg_tls_verify_cert_san(cert, certsz, tls->hostname) <= 0 &&
             mg_tls_verify_cert_cn(&ci->subj, tls->hostname) <= 0) {
           mg_error(c, "failed to verify hostname");
           return -1;
@@ -1343,7 +1375,7 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
           !mg_tls_verify_cert_signature(&certs[certnum - 1], &ca)) {
         mg_error(c, "failed to verify CA");
         return -1;
-      } else {
+      } else if (is_client) {
         MG_VERBOSE(
             ("CA was not in the chain, but verification with builtin CA "
              "passed"));
@@ -1351,11 +1383,11 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
     }
   }
   mg_tls_drop_message(c);
-  mg_tls_calc_cert_verify_hash(c, tls->sighash, 0);
+  mg_tls_calc_cert_verify_hash(c, tls->sighash, !is_client);
   return 0;
 }
 
-static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
+static int mg_tls_recv_cert_verify(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   unsigned char *recv_buf;
   if (mg_tls_recv_record(c) < 0) {
@@ -1363,8 +1395,8 @@ static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
   }
   recv_buf = &c->rtls.buf[tls->recv_offset];
   if (recv_buf[0] != MG_TLS_CERTIFICATE_VERIFY) {
-    mg_error(c, "expected server certificate verify but got msg 0x%02x",
-             recv_buf[0]);
+    mg_error(c, "expected %s certificate verify but got msg 0x%02x",
+             c->is_client ? "server" : "client", recv_buf[0]);
     return -1;
   }
   if (tls->recv_len < 8) {
@@ -1373,7 +1405,7 @@ static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
     return -1;
   }
 
-  // Ignore CertificateVerify is strict checks are not required
+  // Ignore CertificateVerify if strict checks are not required
   if (tls->skip_verification) {
     mg_tls_drop_message(c);
     return 0;
@@ -1504,13 +1536,13 @@ static void mg_tls_client_handshake(struct mg_connection *c) {
       tls->state = MG_TLS_STATE_CLIENT_WAIT_CERT;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_CERT:
-      if (mg_tls_client_recv_cert(c) < 0) {
+      if (mg_tls_recv_cert(c, true) < 0) {
         break;
       }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_CV;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_CV:
-      if (mg_tls_client_recv_cert_verify(c) < 0) {
+      if (mg_tls_recv_cert_verify(c) < 0) {
         break;
       }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_FINISH;
@@ -1519,28 +1551,19 @@ static void mg_tls_client_handshake(struct mg_connection *c) {
       if (mg_tls_client_recv_finish(c) < 0) {
         break;
       }
-      if (tls->cert_requested) {
-        /* for mTLS we should generate application keys at this point
-         * but then restore handshake keys and continue with
-         * the rest of the handshake */
-        struct tls_enc app_keys;
-        struct tls_enc hs_keys = tls->enc;
-        mg_tls_generate_application_keys(c);
-        app_keys = tls->enc;
-        tls->enc = hs_keys;
-        mg_tls_server_send_cert(c);
-        mg_tls_send_cert_verify(c, 1);
-        mg_tls_client_send_finish(c);
-        tls->enc = app_keys;
-      } else {
-        mg_tls_client_send_finish(c);
-        mg_tls_generate_application_keys(c);
+      if (tls->cert_requested && tls->cert_der.len > 0) {  // two-way auth
+        mg_tls_send_cert(c, true);
+        mg_tls_send_cert_verify(c, true);
       }
+      mg_tls_client_send_finish(c);
+      mg_tls_generate_application_keys(c);
       tls->state = MG_TLS_STATE_CLIENT_CONNECTED;
       c->is_tls_hs = 0;
       mg_call(c, MG_EV_TLS_HS, NULL);
       break;
-    default: mg_error(c, "unexpected client state: %d", tls->state); break;
+    default:
+      mg_error(c, "unexpected client state: %d", tls->state);
+      break;
   }
 }
 
@@ -1554,9 +1577,14 @@ static void mg_tls_server_handshake(struct mg_connection *c) {
       mg_tls_server_send_hello(c);
       mg_tls_generate_handshake_keys(c);
       mg_tls_server_send_ext(c);
-      mg_tls_server_send_cert(c);
-      mg_tls_send_cert_verify(c, 0);
+      if (tls->is_twoway) mg_tls_server_send_cert_request(c);
+      mg_tls_send_cert(c, false);
+      mg_tls_send_cert_verify(c, false);
       mg_tls_server_send_finish(c);
+      if (tls->is_twoway) {
+        tls->state = MG_TLS_STATE_SERVER_WAIT_CERT;
+        break;
+      }
       tls->state = MG_TLS_STATE_SERVER_NEGOTIATED;
       // fallthrough
     case MG_TLS_STATE_SERVER_NEGOTIATED:
@@ -1567,7 +1595,17 @@ static void mg_tls_server_handshake(struct mg_connection *c) {
       tls->state = MG_TLS_STATE_SERVER_CONNECTED;
       c->is_tls_hs = 0;
       return;
-    default: mg_error(c, "unexpected server state: %d", tls->state); break;
+    case MG_TLS_STATE_SERVER_WAIT_CERT:
+      if (mg_tls_recv_cert(c, false) < 0) break;
+      tls->state = MG_TLS_STATE_SERVER_WAIT_CV;
+      // Fallthrough
+    case MG_TLS_STATE_SERVER_WAIT_CV:
+      if (mg_tls_recv_cert_verify(c) < 0) break;
+      tls->state = MG_TLS_STATE_SERVER_NEGOTIATED;
+      break;
+    default:
+      mg_error(c, "unexpected server state: %d", tls->state);
+      break;
   }
 }
 
@@ -1654,6 +1692,7 @@ void mg_tls_init(struct mg_connection *c, const struct mg_tls_opts *opts) {
       MG_ERROR(("Failed to load certificate"));
       return;
     }
+    if (!c->is_client) tls->is_twoway = true;  // server + CA: two-way auth
   }
 
   if (opts->cert.buf == NULL) {
diff --git a/src/tls_mbed.c b/src/tls_mbed.c
index 0c466ef2df..ac7321e243 100644
--- a/src/tls_mbed.c
+++ b/src/tls_mbed.c
@@ -58,6 +58,10 @@ void mg_tls_free(struct mg_connection *c) {
     mbedtls_ssl_config_free(&tls->conf);
 #ifdef MBEDTLS_SSL_SESSION_TICKETS
     mbedtls_ssl_ticket_free(&tls->ticket);
+#endif
+#if defined(MBEDTLS_VERSION_NUMBER) && MBEDTLS_VERSION_NUMBER >= 0x03000000 && \
+    defined(MBEDTLS_PSA_CRYPTO_C)
+    mbedtls_psa_crypto_free(); // https://github.com/Mbed-TLS/mbedtls/issues/9223#issuecomment-2144898336
 #endif
     mg_free(tls);
     c->tls = NULL;
diff --git a/src/wifi.h b/src/wifi.h
index c63da15256..e8dabd6cdd 100644
--- a/src/wifi.h
+++ b/src/wifi.h
@@ -4,26 +4,35 @@
 #include "log.h"
 #include "str.h"
 
+struct mg_wifi_data {
+  char *ssid, *pass;      // STA mode, SSID to connect to
+  char *apssid, *appass;  // AP mode, our SSID
+  uint32_t apip, apmask;  // AP mode, our IP address and mask
+  uint8_t security;       // STA mode, TBD
+  uint8_t apsecurity;     // AP mode, TBD
+  uint8_t apchannel;      // AP mode, channel to use
+  bool apmode;  // start in AP mode; 'false' -> connect to 'ssid' != NULL
+};
+
 struct mg_wifi_scan_bss_data {
-    struct mg_str SSID;
-    char *BSSID;
-    int16_t RSSI;
-    uint8_t security;
+  struct mg_str SSID;
+  char *BSSID;
+  int16_t RSSI;
+  uint8_t security;
 #define MG_WIFI_SECURITY_OPEN 0
-#define MG_WIFI_SECURITY_WEP  MG_BIT(0)
-#define MG_WIFI_SECURITY_WPA  MG_BIT(1)
+#define MG_WIFI_SECURITY_WEP MG_BIT(0)
+#define MG_WIFI_SECURITY_WPA MG_BIT(1)
 #define MG_WIFI_SECURITY_WPA2 MG_BIT(2)
 #define MG_WIFI_SECURITY_WPA3 MG_BIT(3)
-    uint8_t channel;
-    unsigned band :2;
+  uint8_t channel;
+  unsigned band : 2;
 #define MG_WIFI_BAND_2G 0
 #define MG_WIFI_BAND_5G 1
-    unsigned has_n :1;
+  unsigned has_n : 1;
 };
 
-
 bool mg_wifi_scan(void);
-bool mg_wifi_connect(char *ssid, char *pass);
+bool mg_wifi_connect(struct mg_wifi_data *);
 bool mg_wifi_disconnect(void);
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel);
+bool mg_wifi_ap_start(struct mg_wifi_data *);
 bool mg_wifi_ap_stop(void);
diff --git a/src/wifi_dummy.c b/src/wifi_dummy.c
index 84886509c8..b1c737968a 100644
--- a/src/wifi_dummy.c
+++ b/src/wifi_dummy.c
@@ -2,7 +2,8 @@
 
 #if (!defined(MG_ENABLE_DRIVER_PICO_W) || !MG_ENABLE_DRIVER_PICO_W) && \
     (!defined(MG_ENABLE_DRIVER_CYW) || !MG_ENABLE_DRIVER_CYW) && \
-    (!defined(MG_ENABLE_DRIVER_CYW_SDIO) || !MG_ENABLE_DRIVER_CYW_SDIO)
+    (!defined(MG_ENABLE_DRIVER_CYW_SDIO) || !MG_ENABLE_DRIVER_CYW_SDIO) && \
+    (!defined(MG_ENABLE_DRIVER_NXP_WIFI) || !MG_ENABLE_DRIVER_NXP_WIFI)
 
 
 bool mg_wifi_scan(void) {
@@ -10,9 +11,8 @@ bool mg_wifi_scan(void) {
   return false;
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
-  (void) ssid;
-  (void) pass;
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  (void) wifi;
   return mg_wifi_scan();
 }
 
@@ -20,10 +20,8 @@ bool mg_wifi_disconnect(void) {
   return mg_wifi_scan();
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
-  (void) ssid;
-  (void) pass;
-  (void) channel;
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  (void) wifi;
   return mg_wifi_scan();
 }
 
diff --git a/test/health.awk b/test/health.awk
new file mode 100755
index 0000000000..299f3c36e3
--- /dev/null
+++ b/test/health.awk
@@ -0,0 +1,11 @@
+#!/usr/bin/env -S gawk -f
+# gawk used to avoid "towc" errors seen on MacOS. env used to circumvent brew installing it wherever they like
+
+BEGIN {
+	FS="\t"
+	print "{"
+}
+/HEALTH_DASHBOARD/ { print $2 }
+END {
+	print "}"
+}
diff --git a/test/health.sh b/test/health.sh
new file mode 100755
index 0000000000..7232e397a2
--- /dev/null
+++ b/test/health.sh
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+cd /data/downloads/health
+find . -mtime +28 -not -name 'index*.json' -delete
+find . -name "*.json" -not -name 'index*.json' | jq -R . | jq -s . > index.json
diff --git a/test/mip_tap_test.c b/test/mip_tap_test.c
index f4cffd245c..a3211b16f5 100644
--- a/test/mip_tap_test.c
+++ b/test/mip_tap_test.c
@@ -82,7 +82,12 @@ static const char *s_ca_cert =
 static char *host_ip;
 
 static int s_num_tests = 0;
+static bool s_error = false;
 
+#ifdef NO_ABORT
+static int s_abort = 0;
+#define ABORT() ++s_abort, s_error = true
+#else
 #ifdef NO_SLEEP_ABORT
 #define ABORT() abort()
 #else
@@ -90,6 +95,7 @@ static int s_num_tests = 0;
   sleep(2); /* 2s, GH print reason */ \
   abort();
 #endif
+#endif
 
 #define ASSERT(expr)                                            \
   do {                                                          \
@@ -101,6 +107,7 @@ static int s_num_tests = 0;
     }                                                           \
   } while (0)
 
+
 static struct mg_http_message gethm(const char *buf) {
   struct mg_http_message hm;
   memset(&hm, 0, sizeof(hm));
@@ -246,7 +253,7 @@ static int fetch(struct mg_mgr *mgr, char *buf, const char *url,
 static void test_http_client(struct mg_mgr *mgr) {
   char buf[FETCH_BUF_SIZE];
   int rc = 0;
-  const bool ipv6 = 0;
+  const bool ipv6 = MG_ENABLE_IPV6;
 #if MG_TLS
   if (ipv6) {
     rc = fetch(mgr, buf, "https://ipv6.google.com",
@@ -260,11 +267,12 @@ static void test_http_client(struct mg_mgr *mgr) {
   if (ipv6) {
     rc = fetch(mgr, buf, "http://ipv6.google.com",
                "GET / HTTP/1.0\r\nHost: ipv6.google.com\r\n\r\n");
+    ASSERT(rc == 200);  // OK
   } else {
     rc = fetch(mgr, buf, "http://cesanta.com",
                "GET /robots.txt HTTP/1.0\r\nHost: cesanta.com\r\n\r\n");
+    ASSERT(rc == 301);  // OK: Permanently moved (HTTP->HTTPS redirect)
   }
-  ASSERT(rc == 301);  // OK: Permanently moved (HTTP->HTTPS redirect)
 
 #endif
 }
@@ -531,22 +539,41 @@ int main(void) {
     usleep(10000);  // 10 ms
   }
 
+#define DASHBOARD(x)  printf("HEALTH_DASHBOARD\t\"%s\": %s,\n", x, s_error ? "false":"true");
+
   // RUN TESTS
   usleep(500000);  // 500 ms
+  s_error = false;
   test_http_client(&mgr);
+  DASHBOARD("http_client");
+
   usleep(500000);  // 500 ms
+  s_error = false;
   test_http_server(&mgr);
+  DASHBOARD("http_server");
+
   usleep(500000);  // 500 ms
+  s_error = false;
   test_tls(&mgr);
+  DASHBOARD("tls");
+
   usleep(500000);  // 500 ms
+  s_error = false;
   test_mqtt_connsubpub(&mgr);
-  usleep(500000);  // 500 ms
-
-  printf("SUCCESS. Total tests: %d\n", s_num_tests);
+  DASHBOARD("mqtt");
 
   // Clear
+  s_error = false;
   mg_mgr_free(&mgr);
   ASSERT(mgr.conns == NULL);  // Deconstruction OK
   close(fd);
-  return 0;
+  printf("HEALTH_DASHBOARD\t\"cleanup\": %s\n", s_error ? "false":"true");
+ // last entry with no comma
+
+#ifdef NO_ABORT
+  if (s_abort != 0) return EXIT_FAILURE;
+#endif
+
+  printf("SUCCESS. Total tests: %d\n", s_num_tests);
+  return EXIT_SUCCESS;
 }
diff --git a/test/mip_test.c b/test/mip_test.c
index 51b2242f42..d24d8692bf 100644
--- a/test/mip_test.c
+++ b/test/mip_test.c
@@ -6,9 +6,14 @@
 #include "driver_mock.c"
 
 static int s_num_tests = 0;
+static bool s_error = false;
 static int s_sent_fragment = 0;
 static int s_seg_sent = 0;
 
+#ifdef NO_ABORT
+static int s_abort = 0;
+#define ABORT() ++s_abort, s_error = true
+#else
 #ifdef NO_SLEEP_ABORT
 #define ABORT() abort()
 #else
@@ -16,6 +21,7 @@ static int s_seg_sent = 0;
   sleep(2); /* 2s, GH print reason */ \
   abort();
 #endif
+#endif
 
 #define ASSERT(expr)                                            \
   do {                                                          \
@@ -27,6 +33,7 @@ static int s_seg_sent = 0;
     }                                                           \
   } while (0)
 
+
 static void test_csum(void) {
   uint8_t ip[20] = {0x45, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x28, 0x11,
                     0x94, 0xcf, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01};
@@ -34,15 +41,26 @@ static void test_csum(void) {
   // UDP and TCP checksum calc funcions use the same basic calls as ipcsum()
 }
 
+static bool executed = false;
+
+static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  if (ev == MG_TCPIP_EV_ST_CHG) {
+    ASSERT(*(uint8_t *) ev_data == MG_TCPIP_STATE_READY);
+    executed = true;
+  }
+  (void) ifp;
+}
+
 static void test_statechange(void) {
-  char tx[1540];
   struct mg_tcpip_if iface;
   memset(&iface, 0, sizeof(iface));
   iface.ip = mg_htonl(0x01020304);
   iface.state = MG_TCPIP_STATE_READY;
-  iface.tx.buf = tx, iface.tx.len = sizeof(tx);
   iface.driver = &mg_tcpip_driver_mock;
+  iface.fn = mif_fn;
   onstatechange(&iface);
+  ASSERT(executed == true);
+  executed = false;
 }
 
 static void ph(struct mg_connection *c, int ev, void *ev_data) {
@@ -54,6 +72,17 @@ static void fn(struct mg_connection *c, int ev, void *ev_data) {
   (void) c, (void) ev, (void) ev_data;
 }
 
+static void tcpclosure_fn(struct mg_connection *c, int ev, void *ev_data) {
+  if (ev == MG_EV_ACCEPT) c->is_draining = 1;
+  (void) c, (void) ev_data;
+}
+
+static void client_fn(struct mg_connection *c, int ev, void *ev_data) {
+  if (ev == MG_EV_ERROR || ev == MG_EV_CONNECT)
+    (*(int *) c->fn_data) = ev;
+  (void) c, (void) ev_data;
+}
+
 static void frag_recv_fn(struct mg_connection *c, int ev, void *ev_data) {
   if (ev == MG_EV_ERROR) {
     if (s_sent_fragment > 0) {
@@ -83,6 +112,7 @@ static void frag_send_fn(struct mg_connection *c, int ev, void *ev_data) {
   (void) c, (void) ev_data;
 }
 
+
 static void test_poll(void) {
   int count = 0, i;
   struct mg_tcpip_if mif;
@@ -145,15 +175,16 @@ static void create_tcp_seg(struct eth *e, struct ip *ip, uint32_t seq,
   t.ack = mg_htonl(ack);
   t.sport = mg_htons(sport);
   t.dport = mg_htons(dport);
-  t.off = (uint8_t) (sizeof(t) / 4 << 4) + (uint8_t) (opts_len / 4 << 4);
+  t.off = (uint8_t) ((sizeof(t) / 4) << 4) + (uint8_t) ((opts_len / 4) << 4);
   memcpy(s_driver_data.buf, e, sizeof(*e));
   ip->len =
-      mg_htons((uint16_t) (sizeof(*ip) + sizeof(struct tcp) + payload_len));
+      mg_htons((uint16_t) (sizeof(*ip) + 4 * (t.off >> 4) + payload_len));
   memcpy(s_driver_data.buf + sizeof(*e), ip, sizeof(*ip));
   memcpy(s_driver_data.buf + sizeof(*e) + sizeof(*ip), &t, sizeof(t));
   if (opts != NULL && opts_len)
     memcpy(s_driver_data.buf + sizeof(*e) + sizeof(*ip) + sizeof(t), opts, opts_len);
   s_driver_data.len = sizeof(*e) + sizeof(*ip) + sizeof(t) + payload_len + opts_len;
+  if (s_driver_data.len < 64) s_driver_data.len = 64; // add padding when needed
 }
 
 static void create_tcp_simpleseg(struct eth *e, struct ip *ip, uint32_t seq,
@@ -163,9 +194,9 @@ static void create_tcp_simpleseg(struct eth *e, struct ip *ip, uint32_t seq,
   create_tcp_seg(e, ip, seq, ack, flags, 1, 80, payload_len, NULL, 0);
 }
 
-static void init_tcp_tests(struct mg_mgr *mgr, struct eth *e, struct ip *ip,
+static void init_tests(struct mg_mgr *mgr, struct eth *e, struct ip *ip,
                            struct mg_tcpip_driver *driver,
-                           struct mg_tcpip_if *mif, mg_event_handler_t f) {
+                           struct mg_tcpip_if *mif, uint8_t proto) {
   mg_mgr_init(mgr);
   memset(mif, 0, sizeof(*mif));
   memset(&s_driver_data, 0, sizeof(struct driver_data));
@@ -174,9 +205,6 @@ static void init_tcp_tests(struct mg_mgr *mgr, struct eth *e, struct ip *ip,
   mif->driver = driver;
   mif->driver_data = &s_driver_data;
   mg_tcpip_init(mgr, mif);
-  mg_http_listen(mgr, "http://0.0.0.0:80", f, NULL);
-  mgr->conns->pfn = NULL;  // HTTP handler not needed
-  mg_mgr_poll(mgr, 0);
 
   // setting the Ethernet header
   memset(e, 0, sizeof(*e));
@@ -185,8 +213,18 @@ static void init_tcp_tests(struct mg_mgr *mgr, struct eth *e, struct ip *ip,
 
   // setting the IP header
   memset(ip, 0, sizeof(*ip));
-  ip->ver = 4 << 4 | 5;
-  ip->proto = 6;
+  ip->ver = (4 << 4) | 5;
+  ip->proto = proto;
+}
+
+static void init_tcp_tests(struct mg_mgr *mgr, struct eth *e, struct ip *ip,
+                           struct mg_tcpip_driver *driver,
+                           struct mg_tcpip_if *mif, mg_event_handler_t f) {
+
+  init_tests(mgr, e, ip, driver, mif, 6); // 6 -> TCP                            
+  mg_http_listen(mgr, "http://0.0.0.0:80", f, NULL);
+  mgr->conns->pfn = NULL;  // HTTP handler not needed
+  mg_mgr_poll(mgr, 0);
 }
 
 static void init_tcp_handshake(struct eth *e, struct ip *ip,
@@ -194,47 +232,118 @@ static void init_tcp_handshake(struct eth *e, struct ip *ip,
   struct tcp *t = (struct tcp *)(s_driver_data.buf + sizeof(*e) + sizeof(*ip));
 
   // SYN
-  create_tcp_simpleseg(e, ip, 1000, 0, TH_SYN | TH_ACK, 0);
+  create_tcp_simpleseg(e, ip, 1000, 0, TH_SYN, 0);
+  MG_VERBOSE(("SYN     -->"));
   mg_mgr_poll(mgr, 0); // make sure we clean former stuff in buffer
 
   // SYN-ACK
   while (!received_response(&s_driver_data)) mg_mgr_poll(mgr, 0);
   ASSERT((t->flags == (TH_SYN | TH_ACK)));
   ASSERT((t->ack == mg_htonl(1001)));
+  MG_VERBOSE(("SYN+ACK <--"));
 
   // ACK
   create_tcp_simpleseg(e, ip, 1001, 2, TH_ACK, 0);
-  mg_mgr_poll(mgr, 0);
+  MG_VERBOSE(("ACK     -->"));
+  mg_mgr_poll(mgr, 0);  // this may have data on return !
 }
 
-
+// DHCP discovery works as a 1 second timeout, we take advantage of it
+// (something is received within 1s) and we mask it when doing longer waits
+// (verify received data is TCP by checking IP's protocol field)
 static void test_tcp_basics(void) {
   struct mg_mgr mgr;
   struct eth e;
   struct ip ip;
   struct tcp *t = (struct tcp *) (s_driver_data.buf + sizeof(e) + sizeof(ip));
-  // uint64_t start, now;
-  // bool response_recv = true;
+  struct ip *i = (struct ip *) (s_driver_data.buf + sizeof(e));
+  uint64_t start, now;
   struct mg_tcpip_driver driver;
   struct mg_tcpip_if mif;
 
   init_tcp_tests(&mgr, &e, &ip, &driver, &mif, fn);
 
-  // send SYN to a non-used port, expect RST + ACK
-  create_tcp_seg(&e, &ip, 1234, 1, TH_SYN, 0, 69, 0, NULL, 0);
+// https://datatracker.ietf.org/doc/html/rfc9293#section-3.5.2	Reset Generation
+  // non-used port. Group 1 in RFC
+  // send SYN, expect RST + ACK
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_SYN, 1, 69, 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == (TH_RST | TH_ACK));
+  ASSERT(t->seq == mg_htonl(0));
+  ASSERT(t->ack == mg_htonl(1235));
+
+  // send SYN+ACK, expect RST
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_SYN | TH_ACK, 1, 69, 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == TH_RST);
+  ASSERT(t->seq == mg_htonl(4321));
+  // send data, expect RST + ACK
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_PUSH, 1, 69, 2, NULL, 0);
+  mg_mgr_poll(&mgr, 0);
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == (TH_RST | TH_ACK));
+  ASSERT(t->seq == mg_htonl(0));
+  ASSERT(t->ack == mg_htonl(1236));
+
+  // send ACK, expect RST
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_ACK, 1, 69, 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0);
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == TH_RST);
+  ASSERT(t->seq == mg_htonl(4321));
+
+  // send FIN, expect RST + ACK
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_FIN, 1, 69, 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == (TH_RST | TH_ACK)); // Linux answers RST only
+  ASSERT(t->seq == mg_htonl(0));
+  ASSERT(t->ack == mg_htonl(1235));
+
+  // send FIN+ACK, expect RST
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_FIN | TH_ACK, 1, 69, 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == TH_RST);
+  ASSERT(t->seq == mg_htonl(4321));
+
+  // listening, non-connected port. Group 2 in RFC
+  // send data, expect no response
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_PUSH, 1, 80, 2, NULL, 0);
+  mg_mgr_poll(&mgr, 0);
+  ASSERT(!received_response(&s_driver_data));
+
+  // send ACK, expect RST
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_ACK, 1, 80, 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0);
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == TH_RST);
+  ASSERT(t->seq == mg_htonl(4321));
+
+  // send SYN+ACK, expect RST
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_SYN | TH_ACK, 1, 80, 0, NULL, 0);
   mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
   while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
-  ASSERT((t->flags == (TH_RST | TH_ACK)));
-  ASSERT((t->ack == mg_htonl(1235)));
+  ASSERT(t->flags == TH_RST);
+  ASSERT(t->seq == mg_htonl(4321));
 
-  // send data to a non-used port, expect a RST + ACK
-  create_tcp_seg(&e, &ip, 1234, 1, TH_PUSH, 0, 69, 0, NULL, 0);
+  // send FIN, expect no response
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_FIN, 1, 80, 0, NULL, 0);
   mg_mgr_poll(&mgr, 0);
+  ASSERT(!received_response(&s_driver_data));
+
+  // send FIN+ACK, expect RST
+  create_tcp_seg(&e, &ip, 1234, 4321, TH_FIN | TH_ACK, 1, 80, 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
   while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
-  ASSERT((t->flags == (TH_RST | TH_ACK)));
-  ASSERT((t->ack == mg_htonl(1234)));
+  ASSERT(t->flags == TH_RST);
+  ASSERT(t->seq == mg_htonl(4321));
+
+
+  // we currently don't validate checksum, no silently discarded segment test
 
-  
 
   init_tcp_handshake(&e, &ip, &mgr);   // starts with seq_no=1000, ackno=2
 
@@ -255,7 +364,234 @@ static void test_tcp_basics(void) {
   ASSERT((t->flags == TH_ACK));
   ASSERT((t->ack == mg_htonl(1001)));  // expecting 1001, dude
 
-  // we currently don't validate checksum, no silently discarded segment test
+  // Initiate closure, send FIN (test client-initiated closure)
+  // https://datatracker.ietf.org/doc/html/rfc9293#section-3.6 
+  // We are case 1, Mongoose is case 2
+  create_tcp_simpleseg(&e, &ip, 1001, 2, TH_FIN, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  // Mongoose does a fast reduced ("3-way instead of 4-way" closure)
+  ASSERT((t->flags == (TH_FIN | TH_ACK))); // Mongoose ACKs our FIN, sends FIN
+  ASSERT((t->seq == mg_htonl(2)));
+  ASSERT((t->ack == mg_htonl(1002)));
+  // make sure it is still open
+  ASSERT(mgr.conns->next != NULL);  // more than one connection: the listener + us
+  create_tcp_simpleseg(&e, &ip, 1002, 3, TH_ACK, 0); // ACK Mongoose FIN
+  mg_mgr_poll(&mgr, 0);
+  ASSERT(!received_response(&s_driver_data));
+  // make sure it is closed
+  ASSERT(mgr.conns->next == NULL);  // only one connection: the listener
+
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+
+  // Test client-initiated closure timeout, do not ACK
+  init_tcp_tests(&mgr, &e, &ip, &driver, &mif, fn);
+  init_tcp_handshake(&e, &ip, &mgr);   // starts with seq_no=1000, ackno=2
+  create_tcp_simpleseg(&e, &ip, 1001, 2, TH_FIN, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  // Mongoose does a fast reduced ("3-way instead of 4-way" closure)
+  ASSERT((t->flags == (TH_FIN | TH_ACK))); // Mongoose ACKs our FIN, sends FIN
+  ASSERT((t->seq == mg_htonl(2)));
+  ASSERT((t->ack == mg_htonl(1002)));
+  // make sure it is still open
+  ASSERT(mgr.conns->next != NULL);  // more than one connection: the listener + us
+  s_driver_data.len = 0; // avoid Mongoose "receiving itself"
+  start = mg_millis();
+  now = 0;
+  do {
+    mg_mgr_poll(&mgr, 0);
+    if (received_response(&s_driver_data) && i->proto == 6) break; // check first
+    now = mg_millis() - start;
+  } while (now < (12 * MIP_TCP_FIN_MS)/10);
+  ASSERT(now > MIP_TCP_FIN_MS);
+  // make sure it is closed
+  ASSERT(mgr.conns->next == NULL);  // only one connection: the listener
+
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+
+  // Test server-initiated closure, abbreviated 3-way: respond FIN+ACK
+  // https://datatracker.ietf.org/doc/html/rfc9293#section-3.6
+  // We are case 2, Mongoose is case 1
+  init_tcp_tests(&mgr, &e, &ip, &driver, &mif, tcpclosure_fn);
+  init_tcp_handshake(&e, &ip, &mgr);   // starts with seq_no=1000, ackno=2
+  // we should have already received the FIN due to the call above
+  start = mg_millis();
+  while (!received_response(&s_driver_data)) {
+    mg_mgr_poll(&mgr, 0);
+    now = mg_millis() - start;
+    if (now > 2 * MIP_TCP_ACK_MS)
+      ASSERT(0);  // response should have been received by now
+  }
+  ASSERT((t->seq == mg_htonl(2)));
+  ASSERT((t->ack == mg_htonl(1001)));
+  ASSERT(t->flags == (TH_FIN | TH_ACK)); // Mongoose ACKs last data, sends FIN
+  // send FIN + ACK
+  create_tcp_simpleseg(&e, &ip, 1001, 3, TH_FIN | TH_ACK, 0); // ACK FIN, send FIN
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT((t->flags == TH_ACK)); // Mongoose ACKs our FIN
+  ASSERT((t->seq == mg_htonl(3)));
+  ASSERT((t->ack == mg_htonl(1002)));
+  // make sure it is closed
+  ASSERT(mgr.conns->next == NULL);  // only one connection: the listener
+
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+
+  // Test server-initiated closure, long 4-way closure: respond ACK
+  init_tcp_tests(&mgr, &e, &ip, &driver, &mif, tcpclosure_fn);
+  init_tcp_handshake(&e, &ip, &mgr);   // starts with seq_no=1000, ackno=2
+  // we should have already received the FIN, tested in above tst
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT((t->seq == mg_htonl(2)));
+  ASSERT((t->ack == mg_htonl(1001)));
+  ASSERT(t->flags == (TH_FIN | TH_ACK)); // Mongoose ACKs last data, sends FIN
+  // ACK Mongoose FIN, do *not* send FIN yet
+  create_tcp_simpleseg(&e, &ip, 1001, 3, TH_ACK, 0); // ACK FIN
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  start = mg_millis();
+  now = 0;
+  do {
+    if (received_response(&s_driver_data)) break; // check first
+    mg_mgr_poll(&mgr, 0);
+    now = mg_millis() - start;
+  } while (now < 2 * MIP_TCP_ACK_MS); // keep timeout below 1s (DHCP discover)
+  ASSERT(now >= 2 * MIP_TCP_ACK_MS);
+  // make sure it is still open
+  ASSERT(mgr.conns->next != NULL);  // more than one connection: the listener + us
+  create_tcp_simpleseg(&e, &ip, 1001, 3, TH_FIN, 0); // send FIN
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT((t->flags == TH_ACK)); // Mongoose ACKs our FIN
+  ASSERT((t->seq == mg_htonl(3)));
+  ASSERT((t->ack == mg_htonl(1002)));
+  // make sure it is closed
+  ASSERT(mgr.conns->next == NULL);  // only one connection: the listener
+
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+
+  // Test server-initiated closure, FIN retransmission: do not ACK FIN
+  // Actual data retransmission is tested on another unit test
+  init_tcp_tests(&mgr, &e, &ip, &driver, &mif, tcpclosure_fn);
+  init_tcp_handshake(&e, &ip, &mgr);   // starts with seq_no=1000, ackno=2
+  // we should have already received the FIN, tested in some tst above
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT((t->seq == mg_htonl(2)));
+  ASSERT((t->ack == mg_htonl(1001)));
+  ASSERT(t->flags == (TH_FIN | TH_ACK)); // Mongoose ACKs last data, sends FIN
+  s_driver_data.len = 0; // avoid Mongoose "receiving itself"
+  start = mg_millis();
+  now = 0;
+  do {
+    if (received_response(&s_driver_data)) break; // check first
+    mg_mgr_poll(&mgr, 0);
+    now = mg_millis() - start;
+  } while (now < 2 * MIP_TCP_ACK_MS); // keep timeout below 1s (DHCP discover)
+//  ASSERT(now < 2 * MIP_TCP_ACK_MS); ******** WE FAIL THIS, Mongoose does not retransmit, FIN is not an additional element in the stream
+//  ASSERT((t->seq == mg_htonl(2)));
+//  ASSERT((t->ack == mg_htonl(1001)));
+//  ASSERT(t->flags == (TH_FIN | TH_ACK)); // Mongoose retransmits FIN
+  // send FIN + ACK
+  create_tcp_simpleseg(&e, &ip, 1001, 3, TH_FIN | TH_ACK, 0); // ACK FIN, send FIN
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT((t->flags == TH_ACK)); // Mongoose ACKs our FIN
+  ASSERT((t->seq == mg_htonl(3)));
+  ASSERT((t->ack == mg_htonl(1002)));
+  // make sure it is closed
+  ASSERT(mgr.conns->next == NULL);  // only one connection: the listener
+
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+
+  // Test simultaneous closure
+  // https://datatracker.ietf.org/doc/html/rfc9293#section-3.6 case 3
+  init_tcp_tests(&mgr, &e, &ip, &driver, &mif, tcpclosure_fn);
+  init_tcp_handshake(&e, &ip, &mgr);   // starts with seq_no=1000, ackno=2
+  // we should have already received the FIN due to the call above
+  start = mg_millis();
+  while (!received_response(&s_driver_data)) {
+    mg_mgr_poll(&mgr, 0);
+    now = mg_millis() - start;
+    if (now > 2 * MIP_TCP_ACK_MS)
+      ASSERT(0);  // response should have been received by now
+  }
+  ASSERT((t->seq == mg_htonl(2)));
+  ASSERT((t->ack == mg_htonl(1001)));
+  ASSERT(t->flags == (TH_FIN | TH_ACK)); // Mongoose ACKs last data, sends FIN
+  // Also initiate closure, send FIN, do *not* ACK Mongoose FIN
+  create_tcp_simpleseg(&e, &ip, 1001, 2, TH_FIN, 0); 
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT((t->flags == TH_ACK)); // Mongoose ACKs our FIN
+  ASSERT((t->seq == mg_htonl(3)));
+  ASSERT((t->ack == mg_htonl(1002)));
+  // make sure it is still open   ******** WE FAIL THIS, Mongoose closes immediately, does not wait to retransmit its ACK nor to get the other end ACK
+//  ASSERT(mgr.conns->next != NULL);  // more than one connection: the listener + us
+//  create_tcp_simpleseg(&e, &ip, 1002, 3, TH_ACK, 0); // ACK FIN
+//  mg_mgr_poll(&mgr, 0);
+  // make sure it is closed
+  ASSERT(mgr.conns->next == NULL);  // only one connection: the listener
+
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+
+  // Test responses to a connecting client
+  // https://datatracker.ietf.org/doc/html/rfc9293#section-3.5 
+  // NOTE: Mongoose ignores any data until connection is actually established
+  // NOTE: Mongoose does not support the concept of "simultaneous open", Mongoose is either client or server
+  {
+  struct mg_connection *c;
+  int event = 255;
+  uint32_t ackno;
+  // this creates a listener we won't use
+  init_tcp_tests(&mgr, &e, &ip, &driver, &mif, tcpclosure_fn);
+
+  c = mg_connect(&mgr, "tcp://1.2.3.4:1234/", client_fn, &event);
+  ASSERT(c!=NULL);
+  ASSERT(received_response(&s_driver_data));
+  ASSERT((t->flags == TH_SYN));
+  ASSERT(event == 255);
+  // invalid SYN + ACK to connecting client (after SYN...), send ACK out of seq
+  ackno = mg_ntohl(t->seq) + 1000;
+//  create_tcp_seg(&e, &ip, 4321, ackno, TH_SYN | TH_ACK, 1234, mg_ntohs(c->loc.port), 0, NULL, 0);
+//  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+//  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+//  ASSERT((t->flags == (TH_RST | TH_ACK)));  // ***************** WHAT DOES LINUX DO HERE ????
+// ******** WE FAIL THIS, Mongoose does not validate the ACK number
+//  ASSERT((t->seq == mg_htonl(ackno)));
+//  ASSERT((t->ack == mg_htonl(4322)));
+
+  // connect
+  ackno = mg_ntohl(t->seq) + 1;
+  create_tcp_seg(&e, &ip, 4321, ackno, TH_SYN | TH_ACK, 1234, mg_ntohs(c->loc.port), 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
+  while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
+  ASSERT(t->flags == TH_ACK);
+  ASSERT(t->seq == mg_htonl(ackno));
+  ASSERT((t->ack == mg_htonl(4322)));
+  ASSERT(event == MG_EV_CONNECT);
+
+  event = 255;
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+
+  // test connection failure, send RST+ACK
+  // this creates a listener we won't use
+  init_tcp_tests(&mgr, &e, &ip, &driver, &mif, tcpclosure_fn);
+  c = mg_connect(&mgr, "tcp://1.2.3.4:1234/", client_fn, &event);
+  received_response(&s_driver_data); // get the SYN
+  ackno = mg_ntohl(t->seq) + 1;
+  create_tcp_seg(&e, &ip, 4321, ackno, TH_RST + TH_ACK, 1234, mg_ntohs(c->loc.port), 0, NULL, 0);
+  mg_mgr_poll(&mgr, 0);
+  MG_DEBUG(("event: %d", event));
+  ASSERT(event == MG_EV_ERROR);
+  ASSERT(!received_response(&s_driver_data));
+  }
 
   s_driver_data.len = 0;
   mg_mgr_free(&mgr);
@@ -405,7 +741,6 @@ static void test_tcp_backlog(void) {
   struct tcp *t = (struct tcp *) (s_driver_data.buf + sizeof(e) + sizeof(ip));
   struct ip *i = (struct ip *) (s_driver_data.buf + sizeof(e));
   uint64_t start, now;
-  //bool response_recv = true;
   struct mg_tcpip_driver driver;
   struct mg_tcpip_if mif;
   uint16_t opts[4 / 2];                            // Send MSS, RFC-9293 3.7.1
@@ -421,18 +756,22 @@ static void test_tcp_backlog(void) {
   mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
   while (!received_response(&s_driver_data)) mg_mgr_poll(&mgr, 0);
   ASSERT(t->flags == (TH_SYN | TH_ACK));
-  // delay ACK so it is removed from the backlog
+  // delay ACK so conn attempt is removed from the backlog
+  s_driver_data.len = 0; // avoid Mongoose "receiving itself"
   start = mg_millis();
   do {
     mg_mgr_poll(&mgr, 0);
     now = mg_millis() - start;
   } while (now < 2100);
-  // Mongoose may have retransmitted SYN + ACK, so
-  create_tcp_simpleseg(&e, &ip, 1235, 2, TH_ACK, 0);
-  mg_mgr_poll(&mgr, 0); // make sure we clean former stuff in buffer
-  while (!received_response(&s_driver_data) || i->proto != 6) mg_mgr_poll(&mgr, 0);
-  ASSERT(t->flags == (TH_RST | TH_ACK));
-
+  // check backlog is empty
+  c = mgr.conns;
+  ASSERT(c->next == NULL);
+  for (j = 0; j < LOGSZ; j++) {
+    struct mg_backlog *b = (struct mg_backlog *)(c->data) + j;
+    ASSERT(b->port == 0);
+  }
+  // Mongoose may have retransmitted SYN + ACK, and DHCP sent discover
+  received_response(&s_driver_data);  // make sure we clean buffer
 
   opts[0] = mg_htons(0x0204); // RFC-9293 3.2
   // fill the backlog
@@ -494,12 +833,102 @@ static void test_tcp(void) {
   test_tcp_retransmit();
 }
 
+
+static void udp_fn(struct mg_connection *c, int ev, void *ev_data) {
+  if (ev == MG_EV_READ && c->recv.len == 2 && c->recv.buf[0] == 'p')
+    mg_send(c, "P90", 3);
+  (void) ev_data;
+}
+
+static void create_udp_dat(struct eth *e, struct ip *ip, uint16_t sport, uint16_t dport, size_t payload_len) {
+  struct udp u;
+  memset(&u, 0, sizeof(struct udp));
+  u.sport = mg_htons(sport);
+  u.dport = mg_htons(dport);
+  u.len = mg_htons((uint16_t) (sizeof(u) + payload_len));
+  memcpy(s_driver_data.buf, e, sizeof(*e));
+  ip->len = mg_htons((uint16_t) (sizeof(*ip) + sizeof(u) + payload_len));
+  memcpy(s_driver_data.buf + sizeof(*e), ip, sizeof(*ip));
+  memcpy(s_driver_data.buf + sizeof(*e) + sizeof(*ip), &u, sizeof(u));
+  *(s_driver_data.buf + sizeof(*e) + sizeof(*ip) + sizeof(u)) = 'p';
+  s_driver_data.len = sizeof(*e) + sizeof(*ip) + sizeof(u) + payload_len;
+  if (s_driver_data.len < 64) s_driver_data.len = 64; // add padding when needed
+}
+
+static void init_udp_tests(struct mg_mgr *mgr, struct eth *e, struct ip *ip,
+                           struct mg_tcpip_driver *driver,
+                           struct mg_tcpip_if *mif, mg_event_handler_t f) {
+
+  init_tests(mgr, e, ip, driver, mif, 17); // 17 -> UDP
+  mif->ip = 1;
+  mif->state = MG_TCPIP_STATE_READY; // so mg_send() works and DHCP stops
+  mg_listen(mgr, "udp://0.0.0.0:888", f, NULL);
+  mg_mgr_poll(mgr, 0);
+}
+
+static void test_udp(void) {
+  struct mg_mgr mgr;
+  struct eth e;
+  struct ip ip;
+  struct udp *u = (struct udp *) (s_driver_data.buf + sizeof(e) + sizeof(ip));
+  // struct ip *i = (struct ip *) (s_driver_data.buf + sizeof(e));
+  struct mg_tcpip_driver driver;
+  struct mg_tcpip_if mif;
+
+  init_udp_tests(&mgr, &e, &ip, &driver, &mif, udp_fn);
+  received_response(&s_driver_data);
+  s_driver_data.len = 0;
+
+  // send data to a non-open port, expect no response (we don't send Destination Unreachable)
+  create_udp_dat(&e, &ip, 1, 800, 2);
+  mg_mgr_poll(&mgr, 0);
+  ASSERT(!received_response(&s_driver_data));
+
+  // send data to an open port, expect response
+  create_udp_dat(&e, &ip, 1, 888, 2);
+  mg_mgr_poll(&mgr, 0);
+  ASSERT(received_response(&s_driver_data));
+  ASSERT(u->sport == mg_htons(888));
+  ASSERT(u->len == mg_htons(sizeof(u) + 3));
+  ASSERT(*((char *)(u + 1)) == 'P');
+
+  s_driver_data.len = 0;
+  mg_mgr_free(&mgr);
+}
+
+
+#define DASHBOARD(x)  printf("HEALTH_DASHBOARD\t\"%s\": %s,\n", x, s_error ? "false":"true");
+
 int main(void) {
+  s_error = false;
   test_csum();
+  DASHBOARD("checksum");
+
+  s_error = false;
   test_statechange();
+  DASHBOARD("statechange");
+
+  s_error = false;
   test_poll();
+  DASHBOARD("poll");
+
+  s_error = false;
   test_tcp();
+  DASHBOARD("tcp");
+
+  s_error = false;
+  test_udp();
+  DASHBOARD("udp");
+
+  s_error = false;
   test_fragmentation();
+  printf("HEALTH_DASHBOARD\t\"ipfrag\": %s\n", s_error ? "false":"true");
+ // last entry with no comma
+
+#ifdef NO_ABORT
+  if (s_abort != 0) return EXIT_FAILURE;
+#endif
+
   printf("SUCCESS. Total tests: %d\n", s_num_tests);
-  return 0;
+  return EXIT_SUCCESS;
 }
diff --git a/test/unit_test.c b/test/unit_test.c
index 54b276b509..579bd95829 100644
--- a/test/unit_test.c
+++ b/test/unit_test.c
@@ -4,7 +4,12 @@
 #include "math.h"
 
 static int s_num_tests = 0;
+static bool s_error = false;
 
+#ifdef NO_ABORT
+static int s_abort = 0;
+#define ABORT() ++s_abort, s_error = true
+#else
 #ifdef NO_SLEEP_ABORT
 #define ABORT() abort()
 #else
@@ -12,6 +17,7 @@ static int s_num_tests = 0;
   sleep(2); /* 2s, GH print reason */ \
   abort();
 #endif
+#endif
 
 #define ASSERT(expr)                                            \
   do {                                                          \
@@ -316,6 +322,8 @@ static void test_iobuf(void) {
   mg_iobuf_add(&io, io.len, "a", 1);
   ASSERT(io.buf != NULL && io.size == 20 && io.len == 11);
   ASSERT(memcmp(io.buf, "xhi!123456a", io.len) == 0);
+  mg_iobuf_resize(&io, 1);
+  ASSERT(io.buf != NULL && io.size == 10 && io.len == 10);
   mg_iobuf_free(&io);
 }
 
@@ -867,8 +875,10 @@ static int fetch(struct mg_mgr *mgr, char *buf, const char *url,
     if (strstr(url, "localhost") != NULL) {
       // Local connection, use self-signed certificates
       opts.ca = mg_unpacked("/certs/ca.crt");
-      // opts.cert = mg_str(s_tls_cert);
-      // opts.key = mg_str(s_tls_key);
+      if (strstr(url, "23456") != NULL) { // hinted from caller
+        opts.cert = mg_unpacked("/certs/client.crt");
+        opts.key = mg_unpacked("/certs/client.key");
+      }
     }
     mg_tls_init(c, &opts);
   }
@@ -1414,7 +1424,6 @@ static void test_tls(void) {
   struct mg_str bd;
   ASSERT(data.buf != NULL && data.len > 0);
   memset(&opts, 0, sizeof(opts));
-  // opts.ca = mg_str(s_tls_ca);
   opts.cert = mg_unpacked("/certs/server.crt");
   opts.key = mg_unpacked("/certs/server.key");
   mg_mgr_init(&mgr);
@@ -1463,6 +1472,20 @@ static void test_tls(void) {
       "is 1.3 only; re-enable when other stacks can be easily configured for "
       "1.3\n");
 #endif
+
+  // Repeat the simplest test with two-way authentication
+  opts.ca = mg_unpacked("/certs/ca.crt"); // configure the server for two-way
+  // make it fail: the client will not use 2-way
+  ASSERT(fetch(&mgr, buf, url, "GET /a.txt HTTP/1.0\n\n") != 200);
+  // make it work
+  mg_mgr_free(&mgr);
+  ASSERT(mgr.conns == NULL);
+  mg_mgr_init(&mgr);
+  url = "https://localhost:23456"; // port # hints the client to use two-way
+  c = mg_http_listen(&mgr, url, eh1, &opts);
+  ASSERT(c != NULL);
+  ASSERT(fetch(&mgr, buf, url, "GET /a.txt HTTP/1.0\n\n") == 200);
+  ASSERT(cmpbody(buf, "hello\n") == 0);
   mg_mgr_free(&mgr);
   ASSERT(mgr.conns == NULL);
 #endif
@@ -1525,7 +1548,7 @@ static void test_http_client(void) {
   ASSERT(ok == 200);
   mg_mgr_poll(&mgr, 1);
 
-  // Make host validationfail
+  // Make host validation fail
   c = mg_http_connect(&mgr, url, f3, &ok);
   ASSERT(c != NULL);
   opts.name = mg_str("dummy");  // Set some invalid hostname value
@@ -1535,6 +1558,16 @@ static void test_http_client(void) {
   MG_INFO(("OK: %d", ok));
   ASSERT(ok == 777);
   mg_mgr_poll(&mgr, 1);
+  // Skip host validation
+  c = mg_http_connect(&mgr, url, f3, &ok);
+  ASSERT(c != NULL);
+  opts.name = mg_str("");
+  mg_tls_init(c, &opts);
+  ok = 0;
+  for (i = 0; i < 500 && ok <= 0; i++) mg_mgr_poll(&mgr, 10);
+  MG_INFO(("OK: %d", ok));
+  ASSERT(ok == 200);
+  mg_mgr_poll(&mgr, 1);
   opts.name = mg_url_host(url);
 #if MG_TLS == MG_TLS_BUILTIN
   mg_free((void *) opts.ca.buf);
@@ -3176,7 +3209,7 @@ static void test_udp(void) {
 }
 
 static void test_check_ip_acl(void) {
-  struct mg_addr ip = {{1, 2, 3, 4}, 0, 0, false};  // 1.2.3.4
+  struct mg_addr ip = {{{1, 2, 3, 4}}, 0, 0, false};  // 1.2.3.4
   ASSERT(mg_check_ip_acl(mg_str(NULL), &ip) == 1);
   ASSERT(mg_check_ip_acl(mg_str(""), &ip) == 1);
   ASSERT(mg_check_ip_acl(mg_str("invalid"), &ip) == -1);
@@ -3953,54 +3986,124 @@ static void test_crypto(void) {
   test_rsa();
 }
 
+
+#define DASHBOARD(x)  printf("HEALTH_DASHBOARD\t\"%s\": %s,\n", x, s_error ? "false":"true");
+
 int main(void) {
   const char *debug_level = getenv("V");
   if (debug_level == NULL) debug_level = "3";
   mg_log_set(atoi(debug_level));
 
+  s_error = false;
   test_crypto();
+  DASHBOARD("crypto");
+
+  s_error = false;
   test_split();
+  test_util();
+  test_str();
+  test_match();
+  test_crc32();
+  DASHBOARD("misc");
+
+  s_error = false;
   test_json();
+  DASHBOARD("json");
+
+  s_error = false;
   test_queue();
+  DASHBOARD("queue");
+
+  s_error = false;
   test_rpc();
-  test_str();
-  test_match();
+  DASHBOARD("rpc");
+
+  s_error = false;
+  test_check_ip_acl();
+  DASHBOARD("ip_acl");
+
+  s_error = false;
+  test_udp();
+  DASHBOARD("udp");
+
+  s_error = false;
   test_get_header_var();
+  test_http_get_var();
   test_http_parse();
   test_rewrites();
-  test_check_ip_acl();
-  test_udp();
-  test_packed();
-  test_crc32();
   test_multipart();
   test_invalid_listen_addr();
   test_http_chunked();
-  test_http_upload();
-  test_http_stream_buffer();
-  test_util();
+  DASHBOARD("http_support");
+
+  s_error = false;
+  test_packed();
+  DASHBOARD("packed_fs");
+
+  s_error = false;
   test_dns();
+  DASHBOARD("dns");
+
+  s_error = false;
   test_timer();
+  DASHBOARD("timers");
+
+  s_error = false;
   test_url();
+  DASHBOARD("url");
+
+  s_error = false;
   test_iobuf();
+  DASHBOARD("iobuf");
+
+  s_error = false;
   test_base64();
-  test_http_get_var();
+  DASHBOARD("base64");
+
+  s_error = false;
   test_tls();
+  DASHBOARD("tls");
+
+  s_error = false;
   test_ws();
   test_ws_fragmentation();
+  DASHBOARD("ws");
+
+  s_error = false;
+  test_http_upload();
+  test_http_stream_buffer();
   test_http_server();
   test_http_404();
   test_http_no_content_length();
   test_http_pipeline();
   test_http_range();
+  DASHBOARD("http_server");
+
 #ifndef LOCALHOST_ONLY
+  s_error = false;
   test_sntp();
+  DASHBOARD("sntp");
+
+  s_error = false;
   test_mqtt();  // sorry, MQTT_LOCALHOST is also skipped 
+  DASHBOARD("mqtt");
+
+  s_error = false;
   test_http_client();
+  DASHBOARD("http_client");
+
 #else
   (void) test_sntp, (void) test_mqtt, (void) test_http_client;
 #endif
+  s_error = false;
   test_poll();
-  printf("SUCCESS. Total tests: %d\n", s_num_tests);
+  printf("HEALTH_DASHBOARD\t\"poll\": %s\n", s_error ? "false":"true");
+ // last entry with no comma
+
+#ifdef NO_ABORT
+  if (s_abort != 0) return EXIT_FAILURE;
+#endif
 
+  printf("SUCCESS. Total tests: %d\n", s_num_tests);
   return EXIT_SUCCESS;
 }
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.cproject b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.cproject
new file mode 100644
index 0000000000..2992312c13
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.cproject
@@ -0,0 +1,897 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.crt.advproject.config.exe.debug.252552941">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.252552941" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.252552941" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; # arm-none-eabi-objcopy -v -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
+					<folderInfo id="com.crt.advproject.config.exe.debug.252552941." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.exe.debug.1082653760" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1289303214" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+							<builder buildPath="${workspace_loc:/frdmrw612_wifi_webconfig}/Debug" id="com.crt.advproject.builder.exe.debug.1379385878" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+							<tool id="com.crt.advproject.cpp.exe.debug.20078202" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
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+								<option id="com.crt.advproject.link.cpp.lto.optmization.level.839027142" name="Link-time optimization level" superClass="com.crt.advproject.link.cpp.lto.optmization.level"/>
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+								<option id="com.crt.advproject.link.cpp.crpenable.502166984" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.cpp.crpenable"/>
+								<option id="com.crt.advproject.link.cpp.flashconfigenable.1653194340" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.cpp.flashconfigenable" value="true" valueType="boolean"/>
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+								<option id="com.crt.advproject.link.cpp.config.1179816857" name="Obsolete (Config)" superClass="com.crt.advproject.link.cpp.config"/>
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+								<option id="com.crt.advproject.link.thumb.1282025773" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
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+								<option id="com.crt.advproject.link.gcc.lto.298108731" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.link.gcc.lto"/>
+								<option id="com.crt.advproject.link.gcc.lto.optmization.level.39481577" name="Link-time optimization level" superClass="com.crt.advproject.link.gcc.lto.optmization.level"/>
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+								<option id="com.crt.advproject.link.toram.1856728509" name="Link application to RAM" superClass="com.crt.advproject.link.toram"/>
+								<option id="com.crt.advproject.link.stackOffset.1459930769" name="Stack offset" superClass="com.crt.advproject.link.stackOffset"/>
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+								<option id="com.crt.advproject.link.config.1922487468" name="Obsolete (Config)" superClass="com.crt.advproject.link.config"/>
+								<option id="com.crt.advproject.link.store.908213121" name="Obsolete (Store)" superClass="com.crt.advproject.link.store"/>
+								<option id="com.crt.advproject.link.securestate.1237011711" name="TrustZone Project Type" superClass="com.crt.advproject.link.securestate"/>
+								<option id="com.crt.advproject.link.sgstubs.placement.1953785846" name="Secure Gateway Placement" superClass="com.crt.advproject.link.sgstubs.placement"/>
+								<option id="com.crt.advproject.link.sgstubenable.1364235338" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable"/>
+								<option id="com.crt.advproject.link.nonsecureobject.38053095" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject"/>
+								<option id="com.crt.advproject.link.inimplib.1183785230" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib"/>
+								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.2025198933" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
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+							</tool>
+							<tool id="com.crt.advproject.tool.debug.release.1082520937" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.release">
+								<option id="com.crt.advproject.miscellaneous.end_of_heap.1818360975" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap"/>
+								<option id="com.crt.advproject.miscellaneous.pvHeapStart.2144777792" name="First address of the heap" superClass="com.crt.advproject.miscellaneous.pvHeapStart"/>
+								<option id="com.crt.advproject.miscellaneous.pvHeapLimit.1762095255" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit"/>
+								<option id="com.crt.advproject.debugger.security.nonsecureimageenable.1515614492" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable"/>
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+								<option id="com.crt.advproject.linkserver.debug.prevent.release.59864048" name="Prevent Debugging" superClass="com.crt.advproject.linkserver.debug.prevent.release"/>
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+					<sourceEntries>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="CMSIS"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="board"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="component"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="flash"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="linkscripts"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="wifi"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="frdmrw612_wifi_webconfig.null.470491832" name="frdmrw612_wifi_webconfig" projectType="com.crt.advproject.projecttype.exe"/>
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+	<storageModule moduleId="scannerConfiguration">
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+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
+		<sdkName>SDK_2.x_FRDM-RW612</sdkName>
+		<sdkExample>frdmrw612_wifi_webconfig</sdkExample>
+		<sdkVersion>2.16.100</sdkVersion>
+		<sdkComponents>middleware.wifi.imu.RW612;middleware.wifi.wifidriver.RW612;platform.drivers.flexcomm_usart_freertos.RW612;component.osa_free_rtos.RW612;driver.conn_fwloader.RW612;component.mflash.frdmrw612.RW612;component.mflash_file.RW612;component.wireless_imu_adapter.RW612;utility.debug_console.RW612;platform.utilities.assert.RW612;middleware.lwip.apps.httpsrv.RW612;platform.drivers.clock.RW612;middleware.freertos-kernel.heap_3.RW612;middleware.wifi.RW612;middleware.lwip.RW612;middleware.edgefast_wifi_nxp.RW612;middleware.freertos-kernel.cm33_non_trustzone.RW612;platform.drivers.flash_config.frdmrw612.RW612;device.RW612_CMSIS.RW612;device.RW612_startup.RW612;platform.drivers.reset.RW612;platform.drivers.flexspi.RW612;platform.drivers.cache_cache64.RW612;platform.drivers.cns_io_mux.RW612;platform.drivers.lpc_gpio.RW612;platform.drivers.power.RW612;platform.drivers.ocotp.RW612;component.els_pkc.platform.rw61x_standalone_clib_gdet_sensor.RW612;platform.utilities.misc_utilities.RW612;middleware.wifi.common_files.RW612;platform.drivers.imu.RW612;middleware.wifi.osa.RW612;middleware.wifi.osa_free_rtos.RW612;platform.drivers.common.RW612;middleware.wifi.template.RW612;middleware.wifi.net.RW612;component.wifi_bt_module.tx_pwr_limits.RW612;middleware.wifi.net_free_rtos.RW612;middleware.lwip.apps.lwiperf.RW612;middleware.freertos-kernel.RW612;middleware.freertos-kernel.template.RW612;middleware.freertos-kernel.extension.RW612;platform.drivers.flexcomm.RW612;platform.drivers.flexcomm_usart.RW612;component.lists.RW612;component.osa_interface.RW612;component.mflash.common.RW612;platform.drivers.gdma.RW612;component.serial_manager.RW612;utility.str.RW612;component.serial_manager_uart.RW612;component.usart_adapter.RW612;middleware.lwip.template.RW612;middleware.lwip.sys_arch_dynamic.RW612;CMSIS_Include_core_cm.RW612;device.RW612_system.RW612;component.els_pkc.els_header_only.RW612;component.els_pkc.els_common.RW612;component.els_pkc.memory.RW612;component.els_pkc.standalone_gdet.RW612;component.els_pkc.platform.rw61x_inf_header_only.RW612;component.els_pkc.buffer.RW612;component.els_pkc.core.RW612;component.els_pkc.param_integrity.RW612;component.els_pkc.flow_protection.RW612;component.els_pkc.secure_counter.RW612;component.els_pkc.pre_processor.RW612;component.els_pkc.toolchain.RW612;component.els_pkc.data_integrity.RW612;frdmrw612_wifi_webconfig;</sdkComponents>
+		<boardId>frdmrw612</boardId>
+		<package>RW612ETA2I</package>
+		<core>cm33_nodsp</core>
+		<coreId>cm33_RW612</coreId>
+	</storageModule>
+	<storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;
+&lt;TargetConfig&gt;
+&lt;Properties property_3="NXP" property_4="RW612" property_count="5" version="100300"/&gt;
+&lt;infoList vendor="NXP"&gt;
+&lt;info chip="RW612" name="RW612"&gt;
+&lt;chip&gt;
+&lt;name&gt;RW612&lt;/name&gt;
+&lt;family&gt;RW61X&lt;/family&gt;
+&lt;vendor&gt;NXP&lt;/vendor&gt;
+&lt;memory can_program="true" id="Flash" is_ro="true" size="0" type="Flash"/&gt;
+&lt;memory id="RAM" size="1216" type="RAM"/&gt;
+&lt;memoryInstance derived_from="Flash" driver="RW61X_FlexSPI_A_SFDP_QSPI.cfx" edited="true" id="QSPI_FLASH" location="0x8000000" size="0x800000"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="SRAM" location="0x20000000" size="0x130000"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="MBOX1" location="0x41380000" size="0x488"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="TXQ1" location="0x41380488" size="0x1000"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="MBOX2" location="0x443c0000" size="0x488"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="TXQ23" location="0x443c0488" size="0x1080"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="TXQ32" location="0x443c1508" size="0x1080"/&gt;
+&lt;/chip&gt;
+&lt;processor&gt;
+&lt;name gcc_name="cortex-m33-nodsp"&gt;Cortex-M33 (No DSP)&lt;/name&gt;
+&lt;family&gt;Cortex-M&lt;/family&gt;
+&lt;/processor&gt;
+&lt;/info&gt;
+&lt;/infoList&gt;
+&lt;/TargetConfig&gt;</projectStorage>
+	</storageModule>
+	<storageModule moduleId="openCmsis"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Debug"/>
+		<configuration configurationName="Release">
+			<resource resourceType="PROJECT" workspacePath="/frdm-rw612-xpresso-freertos-lwip"/>
+		</configuration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.default_mex b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.default_mex
new file mode 100644
index 0000000000..e8abfa2460
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.default_mex
@@ -0,0 +1 @@
+frdm-rw612-xpresso-freertos-builtin.mex
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.project b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.project
new file mode 100644
index 0000000000..2c73623d9f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>frdm-rw612-xpresso-freertos-builtin</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
+	</natures>
+</projectDescription>
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/language.settings.xml b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/language.settings.xml
new file mode 100644
index 0000000000..d64fc9bae9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.crt.advproject.config.exe.debug.252552941" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
+			<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="452102550212881743" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+		</extension>
+	</configuration>
+	<configuration id="com.crt.advproject.config.exe.release.438620977" name="Release">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+			<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="470729173164118281" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+		</extension>
+	</configuration>
+</project>
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/org.eclipse.core.resources.prefs b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000000..99f26c0203
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_compiler.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_compiler.h
new file mode 100644
index 0000000000..21a2c7110d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_gcc.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_gcc.h
new file mode 100644
index 0000000000..045aaf19de
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_gcc.h
@@ -0,0 +1,2211 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.4.1
+ * @date     27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+  \brief   Initializes data and bss sections
+  \details This default implementations initialized all data and additional bss
+           sections relying on .copy.table and .zero.table specified properly
+           in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+  extern void _start(void) __NO_RETURN;
+
+  typedef struct {
+    uint32_t const* src;
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __copy_table_t;
+
+  typedef struct {
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __zero_table_t;
+
+  extern const __copy_table_t __copy_table_start__;
+  extern const __copy_table_t __copy_table_end__;
+  extern const __zero_table_t __zero_table_start__;
+  extern const __zero_table_t __zero_table_end__;
+
+  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = pTable->src[i];
+    }
+  }
+
+  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = 0u;
+    }
+  }
+
+  _start();
+}
+
+#define __PROGRAM_START           __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              __StackSeal
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi":::"memory")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe":::"memory")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+  uint32_t result;
+  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+    __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+  } else {
+    result = __SXTB16(__ROR(op1, rotate)) ;
+  }
+  return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
+{
+  uint32_t result;
+  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+    __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
+  } else {
+    result = __SXTAB16(op1, __ROR(op2, rotate));
+  }
+  return result;
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_version.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_version.h
new file mode 100644
index 0000000000..6addcbb7b7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.5
+ * @date     02. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/core_cm33.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/core_cm33.h
new file mode 100644
index 0000000000..05d27f2cec
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/core_cm33.h
@@ -0,0 +1,3277 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.2.3
+ * @date     13. October 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include                        /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header                   /* treat file as system include file */
+#elif defined ( __GNUC__ )
+  #pragma GCC diagnostic ignored "-Wpedantic"   /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_FP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT             1U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED7[21U];
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup CMSIS_DCB       Debug Control Block
+  \brief    Type definitions for the Debug Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DIB       Debug Identification Block
+  \brief    Type definitions for the Debug Identification Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */
+  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */
+  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */
+  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */
+  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \deprecated Core Debug Base Address */
+  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */
+  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \deprecated Core Debug configuration struct */
+  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */
+  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \deprecated Core Debug Base Address           (non-secure address space) */
+  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */
+  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct   (non-secure address space) */
+  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */
+  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
+  \brief      Register alias definitions for backwards compatibility.
+  @{
+ */
+#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */
+/*@} */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    Debug Control function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+  \brief    Functions that access the Debug Control Block.
+  @{
+ */
+
+
+/**
+  \brief   Set Debug Authentication Control Register
+  \details writes to Debug Authentication Control register.
+  \param [in]  value  value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+    __DSB();
+    __ISB();
+    DCB->DAUTHCTRL = value;
+    __DSB();
+    __ISB();
+}
+
+
+/**
+  \brief   Get Debug Authentication Control Register
+  \details Reads Debug Authentication Control register.
+  \return             Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+    return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Debug Authentication Control Register (non-secure)
+  \details writes to non-secure Debug Authentication Control register when in secure state.
+  \param [in]  value  value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+    __DSB();
+    __ISB();
+    DCB_NS->DAUTHCTRL = value;
+    __DSB();
+    __ISB();
+}
+
+
+/**
+  \brief   Get Debug Authentication Control Register (non-secure)
+  \details Reads non-secure Debug Authentication Control register when in secure state.
+  \return             Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+    return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ##################################    Debug Identification function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+  \brief    Functions that access the Debug Identification Block.
+  @{
+ */
+
+
+/**
+  \brief   Get Debug Authentication Status Register
+  \details Reads Debug Authentication Status register.
+  \return             Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+    return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Debug Authentication Status Register (non-secure)
+  \details Reads non-secure Debug Authentication Status register when in secure state.
+  \return             Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+    return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/mpu_armv8.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/mpu_armv8.h
new file mode 100644
index 0000000000..b6ff9a9b48
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/mpu_armv8.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.3
+ * @date     03. February 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/tz_context.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/tz_context.h
new file mode 100644
index 0000000000..d4c1474f9c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug.ld b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug.ld
new file mode 100644
index 0000000000..88da825d4c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug.ld
@@ -0,0 +1,453 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Generated linker script file for RW612
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v24.12 [Build 148] [2025-01-10] on Sep 10, 2025, 4:53:33 PM
+ */
+
+INCLUDE "frdm-rw612-xpresso-freertos-builtin_Debug_library.ld"
+INCLUDE "frdm-rw612-xpresso-freertos-builtin_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+     /* Offset .text by 0x1000 bytes, which whill be added by the image tool*/
+    .boot_hdr : ALIGN(4)
+    {
+        FILL(0xFF)
+        . = 0x400;
+        __FLASH_BASE = .;
+        KEEP(*(.flash_conf))
+        . = 0x1000;
+    } > QSPI_FLASH
+
+    /* MAIN TEXT SECTION */
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        __vectors_start__ = ABSOLUTE(.) ;
+        KEEP(*(.isr_vector))
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data));
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2));
+        LONG(  SIZEOF(.data_RAM2));
+        LONG(LOADADDR(.data_RAM3));
+        LONG(    ADDR(.data_RAM3));
+        LONG(  SIZEOF(.data_RAM3));
+        LONG(LOADADDR(.data_RAM4));
+        LONG(    ADDR(.data_RAM4));
+        LONG(  SIZEOF(.data_RAM4));
+        LONG(LOADADDR(.data_RAM5));
+        LONG(    ADDR(.data_RAM5));
+        LONG(  SIZEOF(.data_RAM5));
+        LONG(LOADADDR(.data_RAM6));
+        LONG(    ADDR(.data_RAM6));
+        LONG(  SIZEOF(.data_RAM6));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        LONG(    ADDR(.bss_RAM3));
+        LONG(  SIZEOF(.bss_RAM3));
+        LONG(    ADDR(.bss_RAM4));
+        LONG(  SIZEOF(.bss_RAM4));
+        LONG(    ADDR(.bss_RAM5));
+        LONG(  SIZEOF(.bss_RAM5));
+        LONG(    ADDR(.bss_RAM6));
+        LONG(  SIZEOF(.bss_RAM6));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+
+        *(.after_vectors*)
+
+        *(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)       KEEP(*freertos*/tasks.o(.rodata*)) /* FreeRTOS Debug Config */
+       *(.rodata)
+       *(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o).rodata.*)
+       *(.constdata .constdata.*)
+       . = ALIGN(4);
+
+    } > QSPI_FLASH
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > QSPI_FLASH
+
+    .ARM.exidx : ALIGN(4)
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > QSPI_FLASH
+ 
+    _etext = .;
+        
+    /* DATA section for MBOX1 */
+
+    .data_RAM2 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM2 = .) ;
+        PROVIDE(__start_data_MBOX1 = .) ;
+        *(.ramfunc.$RAM2)
+        *(.ramfunc.$MBOX1)
+        *(.data.$RAM2)
+        *(.data.$MBOX1)
+        *(.data.$RAM2.*)
+        *(.data.$MBOX1.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM2 = .) ;
+        PROVIDE(__end_data_MBOX1 = .) ;
+     } > MBOX1 AT>QSPI_FLASH
+
+    /* DATA section for TXQ1 */
+
+    .data_RAM3 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM3 = .) ;
+        PROVIDE(__start_data_TXQ1 = .) ;
+        *(.ramfunc.$RAM3)
+        *(.ramfunc.$TXQ1)
+        *(.data.$RAM3)
+        *(.data.$TXQ1)
+        *(.data.$RAM3.*)
+        *(.data.$TXQ1.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM3 = .) ;
+        PROVIDE(__end_data_TXQ1 = .) ;
+     } > TXQ1 AT>QSPI_FLASH
+
+    /* DATA section for MBOX2 */
+
+    .data_RAM4 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM4 = .) ;
+        PROVIDE(__start_data_MBOX2 = .) ;
+        *(.ramfunc.$RAM4)
+        *(.ramfunc.$MBOX2)
+        *(.data.$RAM4)
+        *(.data.$MBOX2)
+        *(.data.$RAM4.*)
+        *(.data.$MBOX2.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM4 = .) ;
+        PROVIDE(__end_data_MBOX2 = .) ;
+     } > MBOX2 AT>QSPI_FLASH
+
+    /* DATA section for TXQ23 */
+
+    .data_RAM5 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM5 = .) ;
+        PROVIDE(__start_data_TXQ23 = .) ;
+        *(.ramfunc.$RAM5)
+        *(.ramfunc.$TXQ23)
+        *(.data.$RAM5)
+        *(.data.$TXQ23)
+        *(.data.$RAM5.*)
+        *(.data.$TXQ23.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM5 = .) ;
+        PROVIDE(__end_data_TXQ23 = .) ;
+     } > TXQ23 AT>QSPI_FLASH
+
+    /* DATA section for TXQ32 */
+
+    .data_RAM6 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM6 = .) ;
+        PROVIDE(__start_data_TXQ32 = .) ;
+        *(.ramfunc.$RAM6)
+        *(.ramfunc.$TXQ32)
+        *(.data.$RAM6)
+        *(.data.$TXQ32)
+        *(.data.$RAM6.*)
+        *(.data.$TXQ32.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM6 = .) ;
+        PROVIDE(__end_data_TXQ32 = .) ;
+     } > TXQ32 AT>QSPI_FLASH
+
+    /* MAIN DATA SECTION */
+    .uninit_RESERVED (NOLOAD) : ALIGN(4)
+    {
+        _start_uninit_RESERVED = .;
+        KEEP(*(.bss.$RESERVED*))
+       . = ALIGN(4) ;
+        _end_uninit_RESERVED = .;
+    } > SRAM AT> SRAM
+
+    /* Main DATA section (SRAM) */
+    .data : ALIGN(4)
+    {
+       FILL(0xff)
+       _data = . ;
+       PROVIDE(__start_data_RAM = .) ;
+       PROVIDE(__start_data_SRAM = .) ;
+       *(vtable)
+       *(.ramfunc*)
+       KEEP(*(CodeQuickAccess))
+       KEEP(*(DataQuickAccess))
+       *(RamFunction)
+       *mflash_drv.o(.text .text* .rodata .rodata*)
+       *fsl_flexspi.o(.text .text* .rodata .rodata*)
+       *(.data*)
+       . = ALIGN(4) ;
+       _edata = . ;
+       PROVIDE(__end_data_RAM = .) ;
+       PROVIDE(__end_data_SRAM = .) ;
+    } > SRAM AT>QSPI_FLASH
+
+    /* BSS section for MBOX1 */
+    .bss_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM2 = .) ;
+       PROVIDE(__start_bss_MBOX1 = .) ;
+       *(.bss.$RAM2)
+       *(.bss.$MBOX1)
+       *(.bss.$RAM2.*)
+       *(.bss.$MBOX1.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM2 = .) ;
+       PROVIDE(__end_bss_MBOX1 = .) ;
+    } > MBOX1 AT> MBOX1
+
+    /* BSS section for TXQ1 */
+    .bss_RAM3 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM3 = .) ;
+       PROVIDE(__start_bss_TXQ1 = .) ;
+       *(.bss.$RAM3)
+       *(.bss.$TXQ1)
+       *(.bss.$RAM3.*)
+       *(.bss.$TXQ1.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM3 = .) ;
+       PROVIDE(__end_bss_TXQ1 = .) ;
+    } > TXQ1 AT> TXQ1
+
+    /* BSS section for MBOX2 */
+    .bss_RAM4 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM4 = .) ;
+       PROVIDE(__start_bss_MBOX2 = .) ;
+       *(.bss.$RAM4)
+       *(.bss.$MBOX2)
+       *(.bss.$RAM4.*)
+       *(.bss.$MBOX2.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM4 = .) ;
+       PROVIDE(__end_bss_MBOX2 = .) ;
+    } > MBOX2 AT> MBOX2
+
+    /* BSS section for TXQ23 */
+    .bss_RAM5 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM5 = .) ;
+       PROVIDE(__start_bss_TXQ23 = .) ;
+       *(.bss.$RAM5)
+       *(.bss.$TXQ23)
+       *(.bss.$RAM5.*)
+       *(.bss.$TXQ23.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM5 = .) ;
+       PROVIDE(__end_bss_TXQ23 = .) ;
+    } > TXQ23 AT> TXQ23
+
+    /* BSS section for TXQ32 */
+    .bss_RAM6 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM6 = .) ;
+       PROVIDE(__start_bss_TXQ32 = .) ;
+       *(.bss.$RAM6)
+       *(.bss.$TXQ32)
+       *(.bss.$RAM6.*)
+       *(.bss.$TXQ32.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM6 = .) ;
+       PROVIDE(__end_bss_TXQ32 = .) ;
+    } > TXQ32 AT> TXQ32
+
+    /* MAIN BSS SECTION */
+    .bss (NOLOAD) : ALIGN(4)
+    {
+        _bss = .;
+        PROVIDE(__start_bss_RAM = .) ;
+        PROVIDE(__start_bss_SRAM = .) ;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(__end_bss_RAM = .) ;
+        PROVIDE(__end_bss_SRAM = .) ;
+        PROVIDE(end = .);
+    } > SRAM AT> SRAM
+
+    /* NOINIT section for MBOX1 */
+    .noinit_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM2 = .) ;
+       PROVIDE(__start_noinit_MBOX1 = .) ;
+       *(.noinit.$RAM2)
+       *(.noinit.$MBOX1)
+       *(.noinit.$RAM2.*)
+       *(.noinit.$MBOX1.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM2 = .) ;
+       PROVIDE(__end_noinit_MBOX1 = .) ;
+    } > MBOX1 AT> MBOX1
+
+    /* NOINIT section for TXQ1 */
+    .noinit_RAM3 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM3 = .) ;
+       PROVIDE(__start_noinit_TXQ1 = .) ;
+       *(.noinit.$RAM3)
+       *(.noinit.$TXQ1)
+       *(.noinit.$RAM3.*)
+       *(.noinit.$TXQ1.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM3 = .) ;
+       PROVIDE(__end_noinit_TXQ1 = .) ;
+    } > TXQ1 AT> TXQ1
+
+    /* NOINIT section for MBOX2 */
+    .noinit_RAM4 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM4 = .) ;
+       PROVIDE(__start_noinit_MBOX2 = .) ;
+       *(.noinit.$RAM4)
+       *(.noinit.$MBOX2)
+       *(.noinit.$RAM4.*)
+       *(.noinit.$MBOX2.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM4 = .) ;
+       PROVIDE(__end_noinit_MBOX2 = .) ;
+    } > MBOX2 AT> MBOX2
+
+    /* NOINIT section for TXQ23 */
+    .noinit_RAM5 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM5 = .) ;
+       PROVIDE(__start_noinit_TXQ23 = .) ;
+       *(.noinit.$RAM5)
+       *(.noinit.$TXQ23)
+       *(.noinit.$RAM5.*)
+       *(.noinit.$TXQ23.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM5 = .) ;
+       PROVIDE(__end_noinit_TXQ23 = .) ;
+    } > TXQ23 AT> TXQ23
+
+    /* NOINIT section for TXQ32 */
+    .noinit_RAM6 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM6 = .) ;
+       PROVIDE(__start_noinit_TXQ32 = .) ;
+       *(.noinit.$RAM6)
+       *(.noinit.$TXQ32)
+       *(.noinit.$RAM6.*)
+       *(.noinit.$TXQ32.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM6 = .) ;
+       PROVIDE(__end_noinit_TXQ32 = .) ;
+    } > TXQ32 AT> TXQ32
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        PROVIDE(__start_noinit_RAM = .) ;
+        PROVIDE(__start_noinit_SRAM = .) ;
+        *(.noinit*)
+        . = ALIGN(4) ;
+        _end_noinit = .;
+        PROVIDE(__end_noinit_RAM = .) ;
+        PROVIDE(__end_noinit_SRAM = .) ;
+    } > SRAM AT> SRAM
+
+    .smu_cpu13_mbox (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu13_mbox)
+        KEEP (*(.smu_cpu13_mbox))
+        . = ALIGN(4);
+    } > MBOX1 AT> MBOX1
+
+    .smu_cpu31_txq (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu31_txq)
+        KEEP (*(.smu_cpu31_txq))
+        . = ALIGN(4);
+    } > TXQ1 AT> TXQ1
+
+    .smu_cpu23_mbox (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu23_mbox)
+        KEEP (*(.smu_cpu23_mbox))
+        . = ALIGN(4);
+    } > MBOX2 AT> MBOX2
+
+    .smu_cpu32_txq (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu32_txq)
+        KEEP (*(.smu_cpu32_txq))
+        . = ALIGN(4);
+    } > TXQ32 AT> TXQ32
+
+    /* Reserve and place Heap within memory map */
+    _HeapSize = 0x20000;
+    .heap (NOLOAD) :  ALIGN(4)
+    {
+        _pvHeapStart = .;
+        . += _HeapSize;
+        . = ALIGN(4);
+        _pvHeapLimit = .;
+    } > SRAM
+
+     _StackSize = 0x800;
+     /* Reserve space in memory for Stack */
+    .heap2stackfill (NOLOAD) :
+    {
+        . += _StackSize;
+    } > SRAM
+    /* Locate actual Stack in memory map */
+    .stack ORIGIN(SRAM) + LENGTH(SRAM) - _StackSize - 0 (NOLOAD) :  ALIGN(4)
+    {
+        _vStackBase = .;
+        . = ALIGN(4);
+        _vStackTop = . + _StackSize;
+    } > SRAM
+
+    /* Provide basic symbols giving location and size of main text
+     * block, including initial values of RW data sections. Note that
+     * these will need extending to give a complete picture with
+     * complex images (e.g multiple Flash banks).
+     */
+    _image_start = LOADADDR(.text);
+    _image_end = LOADADDR(.data) + SIZEOF(.data);
+    _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_library.ld b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_library.ld
new file mode 100644
index 0000000000..b598306535
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_library.ld
@@ -0,0 +1,17 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Generated linker script file for RW612
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v24.12 [Build 148] [2025-01-10] on Sep 10, 2025, 4:53:33 PM
+ */
+
+GROUP (
+  "libgcc.a"
+  "libc_nano.a"
+  "libm.a"
+  "libcr_newlib_nohost.a"
+)
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_memory.ld b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_memory.ld
new file mode 100644
index 0000000000..8196a3e461
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_memory.ld
@@ -0,0 +1,52 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Generated linker script file for RW612
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v24.12 [Build 148] [2025-01-10] on Sep 10, 2025, 4:53:33 PM
+ */
+
+MEMORY
+{
+  /* Define each memory region */
+  QSPI_FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 0x800000 /* 8M bytes (alias Flash) */  
+  SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x130000 /* 1216K bytes (alias RAM) */  
+  MBOX1 (rwx) : ORIGIN = 0x41380000, LENGTH = 0x488 /* 1160 bytes (alias RAM2) */  
+  TXQ1 (rwx) : ORIGIN = 0x41380488, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */  
+  MBOX2 (rwx) : ORIGIN = 0x443c0000, LENGTH = 0x488 /* 1160 bytes (alias RAM4) */  
+  TXQ23 (rwx) : ORIGIN = 0x443c0488, LENGTH = 0x1080 /* 4224 bytes (alias RAM5) */  
+  TXQ32 (rwx) : ORIGIN = 0x443c1508, LENGTH = 0x1080 /* 4224 bytes (alias RAM6) */  
+}
+
+  /* Define a symbol for the top of each memory region */
+  __base_QSPI_FLASH = 0x8000000  ; /* QSPI_FLASH */  
+  __base_Flash = 0x8000000 ; /* Flash */  
+  __top_QSPI_FLASH = 0x8000000 + 0x800000 ; /* 8M bytes */  
+  __top_Flash = 0x8000000 + 0x800000 ; /* 8M bytes */  
+  __base_SRAM = 0x20000000  ; /* SRAM */  
+  __base_RAM = 0x20000000 ; /* RAM */  
+  __top_SRAM = 0x20000000 + 0x130000 ; /* 1216K bytes */  
+  __top_RAM = 0x20000000 + 0x130000 ; /* 1216K bytes */  
+  __base_MBOX1 = 0x41380000  ; /* MBOX1 */  
+  __base_RAM2 = 0x41380000 ; /* RAM2 */  
+  __top_MBOX1 = 0x41380000 + 0x488 ; /* 1160 bytes */  
+  __top_RAM2 = 0x41380000 + 0x488 ; /* 1160 bytes */  
+  __base_TXQ1 = 0x41380488  ; /* TXQ1 */  
+  __base_RAM3 = 0x41380488 ; /* RAM3 */  
+  __top_TXQ1 = 0x41380488 + 0x1000 ; /* 4K bytes */  
+  __top_RAM3 = 0x41380488 + 0x1000 ; /* 4K bytes */  
+  __base_MBOX2 = 0x443c0000  ; /* MBOX2 */  
+  __base_RAM4 = 0x443c0000 ; /* RAM4 */  
+  __top_MBOX2 = 0x443c0000 + 0x488 ; /* 1160 bytes */  
+  __top_RAM4 = 0x443c0000 + 0x488 ; /* 1160 bytes */  
+  __base_TXQ23 = 0x443c0488  ; /* TXQ23 */  
+  __base_RAM5 = 0x443c0488 ; /* RAM5 */  
+  __top_TXQ23 = 0x443c0488 + 0x1080 ; /* 4224 bytes */  
+  __top_RAM5 = 0x443c0488 + 0x1080 ; /* 4224 bytes */  
+  __base_TXQ32 = 0x443c1508  ; /* TXQ32 */  
+  __base_RAM6 = 0x443c1508 ; /* RAM6 */  
+  __top_TXQ32 = 0x443c1508 + 0x1080 ; /* 4224 bytes */  
+  __top_RAM6 = 0x443c1508 + 0x1080 ; /* 4224 bytes */  
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/README.md b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/README.md
new file mode 100644
index 0000000000..9167836af9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/README.md
@@ -0,0 +1,4 @@
+This example assumes your FRDM-RW612 board already has the Wi-Fi submodule firmware already burned to flash. This seems to be the case for new boards.
+
+In case this is not so, please follow indications in NXP's "frdmrw612_wifi_webconfig" example, components/conn_fwloader/readme.txt
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.c
new file mode 100644
index 0000000000..a4abac5693
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.c
@@ -0,0 +1,437 @@
+/*
+ * Copyright 2021-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_clock.h"
+#include "board.h"
+#include "fsl_flexspi.h"
+#include "fsl_cache.h"
+#include "fsl_io_mux.h"
+#include "fsl_power.h"
+#include "fsl_ocotp.h"
+#include "mcuxClEls.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    uint32_t uartClkSrcFreq = 0;
+
+    /* attach FRG0 clock to FLEXCOMM3 (debug console) */
+    CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+static status_t flexspi_hyper_ram_run_seq(FLEXSPI_Type *base, uint32_t seqIndex)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+
+    /* Write data */
+    flashXfer.deviceAddress = 0U;
+    flashXfer.port          = kFLEXSPI_PortB1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = seqIndex;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    return status;
+}
+
+/* Initialize psram. */
+status_t BOARD_InitPsRam(void)
+{
+    flexspi_device_config_t psramConfig = {
+        .flexspiRootClk       = 106666667, /* 106MHZ SPI serial clock */
+        .isSck2Enabled        = false,
+        .flashSize            = 0x2000,    /* 64Mb/KByte */
+        .addressShift         = false,
+        .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
+        .CSInterval           = 0,
+        .CSHoldTime           = 3,
+        .CSSetupTime          = 3,
+        .dataValidTime        = 1,
+        .columnspace          = 0,
+        .enableWordAddress    = false,
+        .AWRSeqIndex          = 12,
+        .AWRSeqNumber         = 1,
+        .ARDSeqIndex          = 11,
+        .ARDSeqNumber         = 1,
+        .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+        .AHBWriteWaitInterval = 0,
+        .enableWriteMask      = true,
+    };
+
+    uint32_t psramLUT[16] = {
+        /* Read Data */
+        [0] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24),
+        [1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 6, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD,
+                              0x04),
+
+        /* Write Data */
+        [4] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24),
+        [5] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+        /* Reset Enable */
+        [8] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x66, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+        /* Reset */
+        [12] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x99, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+    };
+
+    flexspi_config_t config;
+#if BOARD_ENABLE_PSRAM_CACHE
+    cache64_config_t cacheCfg;
+#endif
+    status_t status         = kStatus_Success;
+
+    if (!BOARD_IS_XIP()) /* FlexSPI not initialized */
+    {
+        CLOCK_EnableClock(kCLOCK_Flexspi);
+        RESET_ClearPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+        BOARD_SetFlexspiClock(FLEXSPI, 5U, 3U); /* 320M / 3 */
+
+        /* Get FLEXSPI default settings and configure the flexspi. */
+        FLEXSPI_GetDefaultConfig(&config);
+
+        /* Init FLEXSPI. */
+        config.rxSampleClock      = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
+        config.rxSampleClockPortB = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
+        config.rxSampleClockDiff  = false;
+        /*Set AHB buffer size for reading data through AHB bus. */
+        config.ahbConfig.enableAHBPrefetch    = true;
+        config.ahbConfig.enableAHBBufferable  = true;
+        config.ahbConfig.enableAHBCachable    = true;
+        config.ahbConfig.enableReadAddressOpt = true;
+        for (uint8_t i = 1; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
+        {
+            config.ahbConfig.buffer[i].bufferSize = 0;
+        }
+        /* FlexSPI has total 1KB RX buffer.
+         * Set DMA0 master to use AHB Rx Buffer0.
+         */
+        config.ahbConfig.buffer[0].masterIndex    = 10;  /* GDMA */
+        config.ahbConfig.buffer[0].bufferSize     = 512; /* Allocate 512B bytes for DMA0 */
+        config.ahbConfig.buffer[0].enablePrefetch = true;
+        config.ahbConfig.buffer[0].priority       = 0;
+        /* All other masters use last buffer with 512B bytes. */
+        config.ahbConfig.buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1].bufferSize = 512;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+        config.enableCombination = false;
+#endif
+        FLEXSPI_Init(BOARD_FLEXSPI_PSRAM, &config);
+    }
+
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(BOARD_FLEXSPI_PSRAM, &psramConfig, kFLEXSPI_PortB1);
+
+    /* Update bottom LUT table (44-59). */
+    FLEXSPI_UpdateLUT(BOARD_FLEXSPI_PSRAM, 44U, psramLUT, ARRAY_SIZE(psramLUT));
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(BOARD_FLEXSPI_PSRAM);
+
+    do
+    {
+        /* Reset PSRAM */
+        status = flexspi_hyper_ram_run_seq(BOARD_FLEXSPI_PSRAM, 13U);
+        if (status == kStatus_Success)
+        {
+            status = flexspi_hyper_ram_run_seq(BOARD_FLEXSPI_PSRAM, 14U);
+        }
+        if (status != kStatus_Success)
+        {
+            status = kStatus_Fail;
+            break;
+        }
+
+#if BOARD_ENABLE_PSRAM_CACHE
+        CACHE64_GetDefaultConfig(&cacheCfg);
+        /* Suppose:
+           Flash on PC bus starting from 0x08000000, controlled by cache 0.
+           PSRAM on PS bus starting from 0x28000000, controlled by cache 1.
+         */
+        CACHE64_Init(CACHE64_POLSEL1, &cacheCfg);
+        CACHE64_EnableWriteBuffer(CACHE64_CTRL1, true);
+        CACHE64_EnableCache(CACHE64_CTRL1);
+#endif
+    } while (false);
+
+    return status;
+}
+
+void BOARD_InitSleepPinConfig(void)
+{
+    int32_t i;
+
+    /* Set all non-AON pins output low level in sleep mode. */
+    for (i = 0; i < 22; i++)
+    {
+        IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+    }
+    for (i = 28; i < 64; i++)
+    {
+        IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+    }
+
+    /* Set RF_CNTL 0-3 output low level in sleep mode. */
+    for (i = 0; i < 4; i++)
+    {
+        IO_MUX_SetRfPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+    }
+}
+
+void BOARD_DeinitFlash(FLEXSPI_Type *base)
+{
+    /* Enable FLEXSPI clock again */
+    CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK;
+
+    /* Enable FLEXSPI module */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    /* Wait until FLEXSPI is not busy */
+    while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
+    {
+    }
+    /* Disable module during the reset procedure */
+    base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+}
+
+void BOARD_InitFlash(FLEXSPI_Type *base)
+{
+    uint32_t status;
+    uint32_t lastStatus;
+    uint32_t retry;
+
+    /* Loopback from DQS pad can maximize RD board flash speed. */
+    if ((base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) != FLEXSPI_MCR0_RXCLKSRC(1))
+    {
+        base->MCR0 = (base->MCR0 & ~FLEXSPI_MCR0_RXCLKSRC_MASK) | FLEXSPI_MCR0_RXCLKSRC(1);
+    }
+    /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is
+     * recommended. */
+    base->DLLCR[0] = 0x1U;
+
+    /* Enable FLEXSPI module */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+    while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
+    {
+    }
+
+    /* Need to wait DLL locked if DLL enabled */
+    if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
+    {
+        lastStatus = base->STS2;
+        retry      = BOARD_FLEXSPI_DLL_LOCK_RETRY;
+        /* Wait slave delay line locked and slave reference delay line locked. */
+        do
+        {
+            status = base->STS2;
+            if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
+                (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK))
+            {
+                /* Locked */
+                retry = 100;
+                break;
+            }
+            else if (status == lastStatus)
+            {
+                /* Same delay cell number in calibration */
+                retry--;
+            }
+            else
+            {
+                retry      = BOARD_FLEXSPI_DLL_LOCK_RETRY;
+                lastStatus = status;
+            }
+        } while (retry > 0);
+        /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+        for (; retry > 0U; retry--)
+        {
+            __NOP();
+        }
+    }
+}
+
+/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
+void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
+{
+    if ((CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src)) ||
+        ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) != (divider - 1)))
+    {
+        /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the
+         FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock
+         frequency. */
+        BOARD_DeinitFlash(base);
+
+        /* Disable clock before changing clock source */
+        CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK;
+        /* Update flexspi clock. */
+        CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
+        CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
+        CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
+        while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
+        {
+        }
+        /* Enable FLEXSPI clock again */
+        CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK;
+
+        BOARD_InitFlash(base);
+    }
+}
+
+static bool LoadGdetCfg(power_gdet_data_t *data)
+{
+    bool retval = true;
+
+    /* If T3 256M clock is disabled, GDET cannot work. */
+    if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_MASK) != 0U)
+    {
+        retval = false;
+    }
+    else
+    {
+        /* GDET clock has been characterzed to 64MHz */
+        CLKCTL0->ELS_GDET_CLK_SEL = CLKCTL0_ELS_GDET_CLK_SEL_SEL(2);
+    }
+
+    if (retval)
+    {
+        /* LOAD command */
+        MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GlitchDetector_LoadConfig_Async((uint8_t *)data));
+        if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GlitchDetector_LoadConfig_Async) != token) ||
+            (MCUXCLELS_STATUS_OK_WAIT != result))
+        {
+            retval = false;
+        }
+        MCUX_CSSL_FP_FUNCTION_CALL_END();
+    }
+
+    if (retval)
+    {
+        /* Wait for the mcuxClEls_GlitchDetector_LoadConfig_Async operation to complete. */
+        MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR));
+        if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
+        {
+            retval = false;
+        }
+        MCUX_CSSL_FP_FUNCTION_CALL_END();
+    }
+
+    return retval;
+}
+
+static void ConfigSvcSensor(void)
+{
+    uint64_t svc;
+    uint32_t pack;
+    status_t status;
+    power_gdet_data_t gdetData = {0U};
+    uint32_t rev = SOCCTRL->CHIP_INFO & SOCCIU_CHIP_INFO_REV_NUM_MASK;
+
+    status = OCOTP_ReadSVC(&svc);
+    if (status == kStatus_Success)
+    { /* CES */
+        status = OCOTP_ReadPackage(&pack);
+        if (status == kStatus_Success)
+        {
+            /*
+               A2 CES: Use SVC voltage.
+               A1 CES: Keep boot voltage 1.11V.
+             */
+            POWER_InitVoltage((rev == 2U) ? ((uint32_t)svc >> 16) : 0U, pack);
+        }
+
+        /* SVC GDET config */
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(149, &gdetData.CFG[0]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(150, &gdetData.CFG[1]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(151, &gdetData.CFG[2]) : status;
+        /* A2 CES load fuse 155 for trim calculation. A1 CES directly use the default trim value in fuse 152. */
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead((rev == 2U) ? 155 : 152, &gdetData.CFG[3]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(153, &gdetData.CFG[4]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(154, &gdetData.CFG[5]) : status;
+        assert(status == kStatus_Success);
+
+        /* Must configure GDET load function for POWER_EnableGDetVSensors(). */
+        Power_InitLoadGdetCfg(LoadGdetCfg, &gdetData, pack);
+    }
+    else
+    {
+        /* A1/A2 non-CES */
+        SystemCoreClockUpdate();
+
+        /* LPBG trim */
+        BUCK11->BUCK_CTRL_EIGHTEEN_REG = 0x6U;
+        /* Change buck level */
+        PMU->PMIP_BUCK_LVL = PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL(0x60U) |  /* 1.8V */
+                             PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL(0x22U) |  /* 0.8V */
+                             PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL(0x60U) | /* 1.8V */
+                             PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL(0x54U);  /* 1.05V */
+        /* Delay 600us */
+        SDK_DelayAtLeastUs(600, SystemCoreClock);
+    }
+}
+
+/* This function is used to configure static voltage compansation and sensors, and in XIP case, change FlexSPI clock
+   to a stable source before clock tree(Such as PLL and Main clock) update */
+void BOARD_ClockPreConfig(void)
+{
+    OCOTP_OtpInit();
+    ConfigSvcSensor();
+    OCOTP_OtpDeinit();
+
+    if (BOARD_IS_XIP())
+    {
+        /* Move FLEXSPI clock source to T3 256m / 4 to avoid instruction/data fetch issue in XIP when
+         * updating PLL and main clock.
+         */
+        BOARD_SetFlexspiClock(FLEXSPI, 6U, 4U);
+    }
+    else
+    {
+        RESET_ClearPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+        BOARD_DeinitFlash(FLEXSPI);
+        CLOCK_AttachClk(kNONE_to_FLEXSPI_CLK);
+        CLOCK_DisableClock(kCLOCK_Flexspi);
+        RESET_SetPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+    }
+}
+
+/* Update FlexSPI clock source and set flash to full speed */
+void BOARD_ClockPostConfig(void)
+{
+    if (BOARD_IS_XIP())
+    {
+        /* Call function BOARD_SetFlexspiClock() to set clock source to aux0_pll_clk. */
+        BOARD_SetFlexspiClock(FLEXSPI, 2U, 2U);
+    }
+    else
+    {
+    }
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.h
new file mode 100644
index 0000000000..42df55954d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2021-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "FRDM-RW612"
+
+/*! @brief Macro to judge XIP */
+#define BOARD_IS_XIP()                                                                                          \
+    ((((uint32_t)BOARD_InitDebugConsole >= 0x08000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x10000000U)) || \
+     (((uint32_t)BOARD_InitDebugConsole >= 0x18000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U)))
+
+/*! @brief The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE     kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) FLEXCOMM3
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART          USART3
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFlexCommClkFreq(3)
+#define BOARD_DEBUG_UART_FRG_CLK \
+    (&(const clock_frg_clk_config_t){3, kCLOCK_FrgPllDiv, 255, 0}) /*!< Select FRG3 mux as frg_pll */
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRG_to_FLEXCOMM3
+#define BOARD_DEBUG_UART_RST        kFC3_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm3
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM3_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM3_IRQn
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_FLEXSPI_PSRAM FLEXSPI
+#ifndef BOARD_ENABLE_PSRAM_CACHE
+#define BOARD_ENABLE_PSRAM_CACHE 1
+#endif
+
+/* Board I2C for codec */
+#define BOARD_CODEC_I2C_BASEADDR   I2C2
+#define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetFlexCommClkFreq(2U)
+#define BOARD_CODEC_I2C_INSTANCE   2
+#define BOARD_CODEC_I2C_SDA_PORT   0
+#define BOARD_CODEC_I2C_SCL_PORT   0
+#define BOARD_CODEC_I2C_SDA_PIN    16
+#define BOARD_CODEC_I2C_SCL_PIN    17
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  0U
+#define LOGIC_LED_OFF 1U
+
+/* A fake led on GPIO header */
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 0U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 0U
+#endif
+
+#define LED_BLUE_INIT(output)                                                            \
+    GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
+
+/* Board SW PIN */
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#define BOARD_SW2_GPIO_PORT 0U
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 11U
+#endif
+
+#define BOARD_ENET0_PHY_ADDRESS (0x02U)
+
+/*! @brief The USIM SMARTCARD PHY configuration. */
+#define BOARD_SMARTCARD_MODULE                (USIM)      /*!< SMARTCARD communicational module instance */
+#define BOARD_SMARTCARD_MODULE_IRQ            (USIM_IRQn) /*!< SMARTCARD communicational module IRQ handler */
+#define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ (CLOCK_GetUsimClkFreq())
+#define BOARD_SMARTCARD_CLOCK_VALUE           (4000000U)  /*!< SMARTCARD clock frequency (4Mhz) */
+#define BOARD_SMARTCARD_IRQ_PORT              (0)
+#define BOARD_SMARTCARD_IRQ_PIN               (19)
+#define BOARD_SMARTCARD_TS_TIMER_IRQ          (CTIMER0_IRQn)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+status_t BOARD_InitPsRam(void);
+void BOARD_InitSleepPinConfig(void);
+void BOARD_ClockPreConfig(void);
+void BOARD_ClockPostConfig(void);
+AT_QUICKACCESS_SECTION_CODE(void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider));
+AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitFlash(FLEXSPI_Type *base));
+AT_QUICKACCESS_SECTION_CODE(void BOARD_InitFlash(FLEXSPI_Type *base));
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.c
new file mode 100644
index 0000000000..dba6e1dcdd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up all selectors to provide selected clocks.
+ *
+ * 3. Set up all dividers.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v14.0
+processor: RW612
+package_id: RW612ETA2I
+mcu_data: ksdk2_0
+processor_version: 0.16.9
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: audio_pll_clk.outFreq, value: 4246732800/345600007 MHz}
+- {id: aux0_pll_clk.outFreq, value: 260 MHz}
+- {id: avpll_ch1_clkout.outFreq, value: 4246732800/345600007 MHz}
+- {id: avpll_ch2_clkout.outFreq, value: 1415577600/22118401 MHz}
+- {id: cau_slp_clk.outFreq, value: 4 MHz}
+- {id: clk_32k.outFreq, value: 32 kHz}
+- {id: clk_pmu_sys.outFreq, value: 52 MHz}
+- {id: els_128m_clk.outFreq, value: 128 MHz}
+- {id: els_256m_clk.outFreq, value: 256 MHz}
+- {id: els_64m_clk.outFreq, value: 64 MHz}
+- {id: ffro_clk_div4.outFreq, value: 640/53 MHz}
+- {id: hclk.outFreq, value: 260 MHz}
+- {id: lposc_clk_i.outFreq, value: 1 MHz}
+- {id: main_clk.outFreq, value: 260 MHz}
+- {id: main_pll_clk.outFreq, value: 260 MHz}
+- {id: otp_fuse_32m_clk.outFreq, value: 32 MHz}
+- {id: refclk_phy.outFreq, value: 40 MHz}
+- {id: sfro_clk_i.outFreq, value: 16 MHz}
+- {id: systick_fclk.outFreq, value: 260 MHz}
+- {id: t3pll_mci_256m.outFreq, value: 256 MHz}
+- {id: t3pll_mci_48_60m_irc.outFreq, value: 2560/53 MHz}
+- {id: tcpu_mci_clk.outFreq, value: 260 MHz}
+- {id: tddr_mci_flexspi_clk.outFreq, value: 320 MHz}
+settings:
+- {id: CLKCTL0.MAINCLKSELB.sel, value: CLKCTL0.MAINPLLCLKDIV}
+- {id: CLKCTL0.MAINPLLCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL0.PMUFCLKDIV.scale, value: '5', locked: true}
+- {id: CLKCTL0.SYSCPUAHBCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL0.SYSTICKFCLKSEL.sel, value: CLKCTL0.SYSTICKFCLKDIV}
+- {id: CLKCTL0.WDT0FCLKSEL.sel, value: NO_CLOCK}
+- {id: CLKCTL1.FRGPLLCLKDIV.scale, value: '13', locked: true}
+- {id: CLKCTL1.OSEVENTFCLKSEL.sel, value: NO_CLOCK}
+- {id: REFCLK_SYS_Config, value: Disabled}
+- {id: SYSCTL2.CH1_M.scale, value: '2621440', locked: true}
+- {id: SYSCTL2.CH1_OFFSET_DIV.scale, value: '345600007', locked: true}
+- {id: SYSCTL2.CH2_M.scale, value: '2621440', locked: true}
+- {id: SYSCTL2.CH2_OFFSET_DIV.scale, value: '66355203', locked: true}
+- {id: SYSCTL2.T3_FBDIV.scale, value: '64', locked: true}
+- {id: SYSCTL2.T3_REFDIV.scale, value: '1', locked: true}
+- {id: T3PLL_MCI_213P3M_Config, value: Disabled}
+- {id: T3PLL_MCI_FLEXSPI_Config, value: Disabled}
+- {id: TCPU_MCI_FLEXSPI_CLK_Config, value: Disabled}
+- {id: TDDR_MCI_ENET_CLK_Config, value: Disabled}
+sources:
+- {id: CAU.XTAL_OSC.outFreq, value: 40 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN =
+    {
+        .ch1Freq = kCLOCK_AvPllChFreq12p288m,     /* AVPLL channel frequency 12.288 MHz */
+        .ch2Freq = kCLOCK_AvPllChFreq64m,         /* AVPLL channel frequency 64 MHz */
+        .enableCali = true,                       /* AVPLL calibration is enabled */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Disable GDET and VSensors */
+    POWER_DisableGDetVSensors();
+    /* Enable CAU sleep clock for PMU */
+    if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U)
+    {
+        /* Enable the CAU sleep clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkCauSlp);
+    }
+    if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U)
+    {
+        /* Enable the REFCLK_SYS clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkSys);
+    }
+    /* Initialize T3 PLL and enable outputs that are not clock gated. */
+    CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m);
+    /* Enable FFRO - T3 PLL 48/60 MHz IRC clock output */
+    CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk);
+    /* Enable T3 PLL 256 MHz clock output */
+    CLOCK_EnableClock(kCLOCK_T3PllMci256mClk);
+    BOARD_ClockPreConfig();
+    /* Set core clock to safe system oscillator clock for initialization of other sources. */
+    CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK);
+    CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1);
+    /* Initialize TCPU PLL and enable outputs that are not clock gated. */
+    CLOCK_InitTcpuRefClk(3120000000UL, kCLOCK_TcpuFlexspiDiv10);
+    /* Enable TCPU PLL MCI clock output */
+    CLOCK_EnableClock(kCLOCK_TcpuMciClk);
+    /* Initialize TDDR PLL and enable outputs that are not clock gated. */
+    CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10);
+    /* Enable TDDR PLL FlexSPI clock output */
+    CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk);
+    /* Initialize AVPLL and enable both channels. */
+    CLOCK_InitAvPll(&avpllConfig_BOARD_BootClockRUN);
+    /* Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kRC32K_to_CLK32K);                 /* Switch CLK32K to RC32K */
+    /*!< Please note SYSTICK_CLK source is used only if the SysTick SYST_CSR register CLKSOURCE bit is set to 0. */
+    CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK);                 /* Switch SYSTICK_CLK to SYSTICK_DIV */
+    /* Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U);         /* Set .AUDIOPLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U);         /* Set .FRGPLLCLKDIV divider to value 13 */
+    CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U);         /* Set .MAINPLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U);         /* Set .AUX0PLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U);         /* Set .SYSTICKFCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U);         /* Set .PMUFCLKDIV divider to value 5 */
+    /* Select the main clock source for the main system clock (MAINCLKSELA and MAINCLKSELB). */
+    CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK);
+    BOARD_ClockPostConfig();
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_HCLK;
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockLPR
+outputs:
+- {id: aux0_pll_clk.outFreq, value: 260 MHz}
+- {id: clk_32k.outFreq, value: 32 kHz}
+- {id: clk_pmu_sys.outFreq, value: 52 MHz}
+- {id: els_128m_clk.outFreq, value: 128 MHz}
+- {id: els_256m_clk.outFreq, value: 256 MHz}
+- {id: els_64m_clk.outFreq, value: 64 MHz}
+- {id: hclk.outFreq, value: 260 MHz}
+- {id: main_clk.outFreq, value: 260 MHz}
+- {id: main_pll_clk.outFreq, value: 260 MHz}
+- {id: otp_fuse_32m_clk.outFreq, value: 32 MHz}
+- {id: refclk_phy.outFreq, value: 40 MHz}
+- {id: refclk_sys.outFreq, value: 40 MHz}
+- {id: sfro_clk_i.outFreq, value: 16 MHz}
+- {id: systick_fclk.outFreq, value: 260 MHz}
+- {id: t3pll_mci_256m.outFreq, value: 256 MHz}
+- {id: tcpu_mci_clk.outFreq, value: 260 MHz}
+settings:
+- {id: AVPLL_Init_Config, value: Disabled}
+- {id: CAU_SLP_CLK_Config, value: Disabled}
+- {id: CLKCTL0.MAINCLKSELB.sel, value: CLKCTL0.MAINPLLCLKDIV}
+- {id: CLKCTL0.MAINPLLCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL0.SYSOSCBYPASS_SEL.sel, value: NO_CLOCK}
+- {id: CLKCTL0.SYSTICKFCLKSEL.sel, value: CLKCTL0.SYSTICKFCLKDIV}
+- {id: CLKCTL1.CLKOUTSEL1.sel, value: CLKCTL1.CLKOUTSEL0}
+- {id: CLKCTL1.CLKOUTSEL2.sel, value: CLKCTL1.CLKOUTSEL1}
+- {id: CLKCTL1.FRGPLLCLKDIV.scale, value: '13', locked: true}
+- {id: SYSCTL2.T3_FBDIV.scale, value: '64'}
+- {id: SYSCTL2.TCPU_FBDIV.scale, value: '78', locked: true}
+- {id: SYSCTL2.TCPU_MCI_FLEXSPI_CLK_DIV.scale, value: '10', locked: true}
+- {id: SYSCTL2.TCPU_REFDIV.scale, value: '1', locked: true}
+- {id: T3PLL_MCI_213P3M_Config, value: Disabled}
+- {id: T3PLL_MCI_48_60M_IRC_Config, value: Disabled}
+- {id: T3PLL_MCI_FLEXSPI_Config, value: Disabled}
+- {id: TCPU_MCI_FLEXSPI_CLK_Config, value: Disabled}
+- {id: TDDR_MCI_ENET_CLK_Config, value: Disabled}
+- {id: TDDR_MCI_FLEXSPI_CLK_Config, value: Disabled}
+- {id: TDDR_PLL_Init_Config, value: Disabled}
+sources:
+- {id: CAU.XTAL_OSC.outFreq, value: 40 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockLPR(void)
+{
+    /* Disable GDET and VSensors */
+    POWER_DisableGDetVSensors();
+    /* Enable CAU sleep clock for PMU */
+    if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U)
+    {
+        /* Enable the CAU sleep clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkCauSlp);
+    }
+    if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U)
+    {
+        /* Enable the REFCLK_SYS clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkSys);
+    }
+    /* Initialize T3 PLL and enable outputs that are not clock gated. */
+    CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m);
+    /* Enable T3 PLL 256 MHz clock output */
+    CLOCK_EnableClock(kCLOCK_T3PllMci256mClk);
+    BOARD_ClockPreConfig();
+    /* Set core clock to safe system oscillator clock for initialization of other sources. */
+    CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK);
+    CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1);
+    /* Initialize TCPU PLL and enable outputs that are not clock gated. */
+    CLOCK_InitTcpuRefClk(3120000000UL, kCLOCK_TcpuFlexspiDiv10);
+    /* Enable TCPU PLL MCI clock output */
+    CLOCK_EnableClock(kCLOCK_TcpuMciClk);
+    /* Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kRC32K_to_CLK32K);                 /* Switch CLK32K to RC32K */
+    /*!< Please note SYSTICK_CLK source is used only if the SysTick SYST_CSR register CLKSOURCE bit is set to 0. */
+    CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK);                 /* Switch SYSTICK_CLK to SYSTICK_DIV */
+    /* Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U);         /* Set .FRGPLLCLKDIV divider to value 13 */
+    CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U);         /* Set .MAINPLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U);         /* Set .AUX0PLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U);         /* Set .SYSTICKFCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U);         /* Set .PMUFCLKDIV divider to value 5 */
+    /* Select the main clock source for the main system clock (MAINCLKSELA and MAINCLKSELB). */
+    CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK);
+    /* Deinitialization of the AVPLL. */
+    CLOCK_DeinitAvPll();
+    /* Deinitialize TDDR PLL. */
+    CLOCK_DeinitTddrRefClk();
+    BOARD_ClockPostConfig();
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKLPR_HCLK;
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.h
new file mode 100644
index 0000000000..f4a5c313c4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AUDIO_PLL_CLK              12287999UL     /* Clock consumers of audio_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_AUX0_PLL_CLK               260000000UL    /* Clock consumers of aux0_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_AUX1_PLL_CLK               0UL            /* Clock consumers of aux1_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_AVPLL_CH1_CLKOUT           12287999UL     /* Clock consumers of avpll_ch1_clkout output : N/A */
+#define BOARD_BOOTCLOCKRUN_AVPLL_CH2_CLKOUT           63999997UL     /* Clock consumers of avpll_ch2_clkout output : N/A */
+#define BOARD_BOOTCLOCKRUN_CAU_SLP_CLK                4000000UL      /* Clock consumers of cau_slp_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_32K                    32000UL        /* Clock consumers of clk_32k output : RTC */
+#define BOARD_BOOTCLOCKRUN_CLK_OUT                    0UL            /* Clock consumers of clk_out output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_PMU_SYS                52000000UL     /* Clock consumers of clk_pmu_sys output : PMU */
+#define BOARD_BOOTCLOCKRUN_CTIMER0_FCLK               0UL            /* Clock consumers of ctimer0_fclk output : CTIMER0 */
+#define BOARD_BOOTCLOCKRUN_CTIMER1_FCLK               0UL            /* Clock consumers of ctimer1_fclk output : CTIMER1 */
+#define BOARD_BOOTCLOCKRUN_CTIMER2_FCLK               0UL            /* Clock consumers of ctimer2_fclk output : CTIMER2 */
+#define BOARD_BOOTCLOCKRUN_CTIMER3_FCLK               0UL            /* Clock consumers of ctimer3_fclk output : CTIMER3 */
+#define BOARD_BOOTCLOCKRUN_DMIC_FCLK                  0UL            /* Clock consumers of dmic_fclk output : DMIC0 */
+#define BOARD_BOOTCLOCKRUN_ELS_128M_CLK               128000000UL    /* Clock consumers of els_128m_clk output : ELS */
+#define BOARD_BOOTCLOCKRUN_ELS_256M_CLK               256000000UL    /* Clock consumers of els_256m_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_ELS_64M_CLK                64000000UL     /* Clock consumers of els_64m_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_ELS_FCLK                   0UL            /* Clock consumers of els_fclk output : ELS */
+#define BOARD_BOOTCLOCKRUN_FFRO_CLK_DIV4              12075471UL     /* Clock consumers of ffro_clk_div4 output : N/A */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM0_FCLK             0UL            /* Clock consumers of flexcomm0_fclk output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM14_FCLK            0UL            /* Clock consumers of flexcomm14_fclk output : FLEXCOMM14 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM1_FCLK             0UL            /* Clock consumers of flexcomm1_fclk output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM2_FCLK             0UL            /* Clock consumers of flexcomm2_fclk output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM3_FCLK             0UL            /* Clock consumers of flexcomm3_fclk output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_FCLK               0UL            /* Clock consumers of flexspi_fclk output : FLEXSPI */
+#define BOARD_BOOTCLOCKRUN_GAU_FCLK                   0UL            /* Clock consumers of gau_fclk output : GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1 */
+#define BOARD_BOOTCLOCKRUN_HCLK                       260000000UL    /* Clock consumers of hclk output : AHB_SECURE_CTRL, APU0, APU1, BLEAPU, BLECTRL, BUCK11, BUCK18, CACHE64_CTRL0, CACHE64_CTRL1, CACHE64_POLSEL0, CACHE64_POLSEL1, CAU, CDOG, CLKCTL0, CLKCTL1, CRC, CTIMER0, CTIMER1, CTIMER2, CTIMER3, DMA0, DMA1, DMIC0, ELS, ENET, FLEXCOMM0, FLEXCOMM1, FLEXCOMM14, FLEXCOMM2, FLEXCOMM3, FLEXSPI, FREQME, GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1, GDMA, GPIO, INPUTMUX, ITRC, LCDIC, MCI_IO_MUX, MRT0, MRT1, OCOTP, OSTIMER, PINT, PKC, PMU, POWERQUAD, PUF, ROMCP, RSTCTL0, RSTCTL1, RTC, SCT0, SDU_FBR_CARD, SDU_FN0_CARD, SDU_FN_CARD, SECGPIO, SENSOR_CTRL, SOCCTRL, SOC_OTP_CTRL, SYSCTL0, SYSCTL1, SYSCTL2, SysTick, TRNG, USBOTG, USIM, UTICK, WLAPU, WLCTRL, WWDT0 */
+#define BOARD_BOOTCLOCKRUN_LCD_FCLK                   0UL            /* Clock consumers of lcd_fclk output : LCDIC */
+#define BOARD_BOOTCLOCKRUN_LPOSC_CLK_I                1000000UL      /* Clock consumers of lposc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKRUN_MAIN_CLK                   260000000UL    /* Clock consumers of main_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_MAIN_PLL_CLK               260000000UL    /* Clock consumers of main_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_MCLK_OUT                   0UL            /* Clock consumers of mclk_out output : N/A */
+#define BOARD_BOOTCLOCKRUN_OSEVENT_FCLK               0UL            /* Clock consumers of osevent_fclk output : OSTIMER */
+#define BOARD_BOOTCLOCKRUN_OTP_FUSE_32M_CLK           32000000UL     /* Clock consumers of otp_fuse_32m_clk output : OCOTP */
+#define BOARD_BOOTCLOCKRUN_REFCLK_PHY                 40000000UL     /* Clock consumers of refclk_phy output : USBOTG */
+#define BOARD_BOOTCLOCKRUN_REFCLK_SYS                 0UL            /* Clock consumers of refclk_sys output : N/A */
+#define BOARD_BOOTCLOCKRUN_SCT_FCLK                   0UL            /* Clock consumers of sct_fclk output : SCT0 */
+#define BOARD_BOOTCLOCKRUN_SFRO_CLK_I                 16000000UL     /* Clock consumers of sfro_clk_i output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYSOSC_CLK_I               0UL            /* Clock consumers of sysosc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYSTICK_FCLK               260000000UL    /* Clock consumers of systick_fclk output : SysTick */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_213P3M           0UL            /* Clock consumers of t3pll_mci_213p3m output : N/A */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_256M             256000000UL    /* Clock consumers of t3pll_mci_256m output : N/A */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_48_60M_IRC       48301886UL     /* Clock consumers of t3pll_mci_48_60m_irc output : N/A */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_FLEXSPI_CLK      0UL            /* Clock consumers of t3pll_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_TCPU_MCI_CLK               260000000UL    /* Clock consumers of tcpu_mci_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_TCPU_MCI_FLEXSPI_CLK       0UL            /* Clock consumers of tcpu_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_TDDR_MCI_ENET_CLK          0UL            /* Clock consumers of tddr_mci_enet_clk output : ENET */
+#define BOARD_BOOTCLOCKRUN_TDDR_MCI_FLEXSPI_CLK       320000000UL    /* Clock consumers of tddr_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_USIM_FCLK                  0UL            /* Clock consumers of usim_fclk output : USIM */
+#define BOARD_BOOTCLOCKRUN_UTICK_FCLK                 0UL            /* Clock consumers of utick_fclk output : UTICK */
+#define BOARD_BOOTCLOCKRUN_WDT0_FCLK                  0UL            /* Clock consumers of wdt0_fclk output : WWDT0 */
+
+/*! @brief AVPLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN;
+/*! @brief Clock pre-initialization function.
+ */
+extern void BOARD_ClockPreConfig(void);
+/*! @brief Clock post-initialization function.
+ */
+extern void BOARD_ClockPostConfig(void);
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKLPR_AUDIO_PLL_CLK              0UL            /* Clock consumers of audio_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_AUX0_PLL_CLK               260000000UL    /* Clock consumers of aux0_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_AUX1_PLL_CLK               0UL            /* Clock consumers of aux1_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_AVPLL_CH1_CLKOUT           0UL            /* Clock consumers of avpll_ch1_clkout output : N/A */
+#define BOARD_BOOTCLOCKLPR_AVPLL_CH2_CLKOUT           0UL            /* Clock consumers of avpll_ch2_clkout output : N/A */
+#define BOARD_BOOTCLOCKLPR_CAU_SLP_CLK                0UL            /* Clock consumers of cau_slp_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_CLK_32K                    32000UL        /* Clock consumers of clk_32k output : RTC */
+#define BOARD_BOOTCLOCKLPR_CLK_OUT                    0UL            /* Clock consumers of clk_out output : N/A */
+#define BOARD_BOOTCLOCKLPR_CLK_PMU_SYS                52000000UL     /* Clock consumers of clk_pmu_sys output : PMU */
+#define BOARD_BOOTCLOCKLPR_CTIMER0_FCLK               0UL            /* Clock consumers of ctimer0_fclk output : CTIMER0 */
+#define BOARD_BOOTCLOCKLPR_CTIMER1_FCLK               0UL            /* Clock consumers of ctimer1_fclk output : CTIMER1 */
+#define BOARD_BOOTCLOCKLPR_CTIMER2_FCLK               0UL            /* Clock consumers of ctimer2_fclk output : CTIMER2 */
+#define BOARD_BOOTCLOCKLPR_CTIMER3_FCLK               0UL            /* Clock consumers of ctimer3_fclk output : CTIMER3 */
+#define BOARD_BOOTCLOCKLPR_DMIC_FCLK                  0UL            /* Clock consumers of dmic_fclk output : DMIC0 */
+#define BOARD_BOOTCLOCKLPR_ELS_128M_CLK               128000000UL    /* Clock consumers of els_128m_clk output : ELS */
+#define BOARD_BOOTCLOCKLPR_ELS_256M_CLK               256000000UL    /* Clock consumers of els_256m_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_ELS_64M_CLK                64000000UL     /* Clock consumers of els_64m_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_ELS_FCLK                   0UL            /* Clock consumers of els_fclk output : ELS */
+#define BOARD_BOOTCLOCKLPR_FFRO_CLK_DIV4              0UL            /* Clock consumers of ffro_clk_div4 output : N/A */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM0_FCLK             0UL            /* Clock consumers of flexcomm0_fclk output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM14_FCLK            0UL            /* Clock consumers of flexcomm14_fclk output : FLEXCOMM14 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM1_FCLK             0UL            /* Clock consumers of flexcomm1_fclk output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM2_FCLK             0UL            /* Clock consumers of flexcomm2_fclk output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM3_FCLK             0UL            /* Clock consumers of flexcomm3_fclk output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKLPR_FLEXSPI_FCLK               0UL            /* Clock consumers of flexspi_fclk output : FLEXSPI */
+#define BOARD_BOOTCLOCKLPR_GAU_FCLK                   0UL            /* Clock consumers of gau_fclk output : GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1 */
+#define BOARD_BOOTCLOCKLPR_HCLK                       260000000UL    /* Clock consumers of hclk output : AHB_SECURE_CTRL, APU0, APU1, BLEAPU, BLECTRL, BUCK11, BUCK18, CACHE64_CTRL0, CACHE64_CTRL1, CACHE64_POLSEL0, CACHE64_POLSEL1, CAU, CDOG, CLKCTL0, CLKCTL1, CRC, CTIMER0, CTIMER1, CTIMER2, CTIMER3, DMA0, DMA1, DMIC0, ELS, ENET, FLEXCOMM0, FLEXCOMM1, FLEXCOMM14, FLEXCOMM2, FLEXCOMM3, FLEXSPI, FREQME, GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1, GDMA, GPIO, INPUTMUX, ITRC, LCDIC, MCI_IO_MUX, MRT0, MRT1, OCOTP, OSTIMER, PINT, PKC, PMU, POWERQUAD, PUF, ROMCP, RSTCTL0, RSTCTL1, RTC, SCT0, SDU_FBR_CARD, SDU_FN0_CARD, SDU_FN_CARD, SECGPIO, SENSOR_CTRL, SOCCTRL, SOC_OTP_CTRL, SYSCTL0, SYSCTL1, SYSCTL2, SysTick, TRNG, USBOTG, USIM, UTICK, WLAPU, WLCTRL, WWDT0 */
+#define BOARD_BOOTCLOCKLPR_LCD_FCLK                   0UL            /* Clock consumers of lcd_fclk output : LCDIC */
+#define BOARD_BOOTCLOCKLPR_LPOSC_CLK_I                0UL            /* Clock consumers of lposc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKLPR_MAIN_CLK                   260000000UL    /* Clock consumers of main_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_MAIN_PLL_CLK               260000000UL    /* Clock consumers of main_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_MCLK_OUT                   0UL            /* Clock consumers of mclk_out output : N/A */
+#define BOARD_BOOTCLOCKLPR_OSEVENT_FCLK               0UL            /* Clock consumers of osevent_fclk output : OSTIMER */
+#define BOARD_BOOTCLOCKLPR_OTP_FUSE_32M_CLK           32000000UL     /* Clock consumers of otp_fuse_32m_clk output : OCOTP */
+#define BOARD_BOOTCLOCKLPR_REFCLK_PHY                 40000000UL     /* Clock consumers of refclk_phy output : USBOTG */
+#define BOARD_BOOTCLOCKLPR_REFCLK_SYS                 40000000UL     /* Clock consumers of refclk_sys output : N/A */
+#define BOARD_BOOTCLOCKLPR_SCT_FCLK                   0UL            /* Clock consumers of sct_fclk output : SCT0 */
+#define BOARD_BOOTCLOCKLPR_SFRO_CLK_I                 16000000UL     /* Clock consumers of sfro_clk_i output : N/A */
+#define BOARD_BOOTCLOCKLPR_SYSOSC_CLK_I               0UL            /* Clock consumers of sysosc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKLPR_SYSTICK_FCLK               260000000UL    /* Clock consumers of systick_fclk output : SysTick */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_213P3M           0UL            /* Clock consumers of t3pll_mci_213p3m output : N/A */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_256M             256000000UL    /* Clock consumers of t3pll_mci_256m output : N/A */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_48_60M_IRC       0UL            /* Clock consumers of t3pll_mci_48_60m_irc output : N/A */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_FLEXSPI_CLK      0UL            /* Clock consumers of t3pll_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_TCPU_MCI_CLK               260000000UL    /* Clock consumers of tcpu_mci_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_TCPU_MCI_FLEXSPI_CLK       0UL            /* Clock consumers of tcpu_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_TDDR_MCI_ENET_CLK          0UL            /* Clock consumers of tddr_mci_enet_clk output : ENET */
+#define BOARD_BOOTCLOCKLPR_TDDR_MCI_FLEXSPI_CLK       0UL            /* Clock consumers of tddr_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_USIM_FCLK                  0UL            /* Clock consumers of usim_fclk output : USIM */
+#define BOARD_BOOTCLOCKLPR_UTICK_FCLK                 0UL            /* Clock consumers of utick_fclk output : UTICK */
+#define BOARD_BOOTCLOCKLPR_WDT0_FCLK                  0UL            /* Clock consumers of wdt0_fclk output : WWDT0 */
+
+/*******************************************************************************
+ * API for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.c
new file mode 100644
index 0000000000..ba7ee59853
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2021 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "pin_mux.h"
+#include "fsl_io_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {                                /*!< Function assigned for the core: Cortex-M33[cm33] */
+    IO_MUX_SetPinMux(IO_MUX_FC3_USART_DATA);
+    IO_MUX_SetPinMux(IO_MUX_GPIO11);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.h
new file mode 100644
index 0000000000..377cfda427
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2021 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);                                 /*!< Function assigned for the core: Cortex-M4[cm4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/fsl_loader.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/fsl_loader.c
new file mode 100644
index 0000000000..a416edabba
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/fsl_loader.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2020-2021,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef TFM_PARTITION_LOADER_SERVICE
+#include "fsl_loader_utils.h"
+
+//! @addtogroup sbloader
+//! @{
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+////////////////////////////////////////////////////////////////////////////
+//! @brief fw download
+////////////////////////////////////////////////////////////////////////////
+status_t sb3_fw_download(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr)
+{
+    return sb3_fw_download_impl(loadTarget,flag,sourceAddr);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief fw reset
+////////////////////////////////////////////////////////////////////////////
+status_t sb3_fw_reset(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr)
+{
+    return sb3_fw_reset_impl(loadTarget, flag, sourceAddr);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief power on device
+////////////////////////////////////////////////////////////////////////////
+void power_on_device(LOAD_Target_Type loadTarget)
+{
+    power_on_device_impl(loadTarget);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief power off device
+////////////////////////////////////////////////////////////////////////////
+void power_off_device(LOAD_Target_Type loadTarget)
+{
+    power_off_device_impl(loadTarget);
+}
+//! @}
+////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////
+#endif /* TFM_PARTITION_LOADER_SERVICE */
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/fsl_loader_utils.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/fsl_loader_utils.c
new file mode 100644
index 0000000000..1d6101e4d0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/fsl_loader_utils.c
@@ -0,0 +1,1614 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include "fsl_loader_utils.h"
+#include "api_tree_root.h"
+#include "fsl_power.h"
+#ifndef __ZEPHYR__
+#include "board.h"
+#include "fsl_debug_console.h"
+#else
+#include "fsl_clock.h"
+#endif
+
+#ifdef MCUBOOT_APPLICATION
+#include "mcuboot_app_support.h"
+#endif
+
+#include "mflash_drv.h"
+
+#if defined(MBEDTLS_THREADING_C) && defined(MBEDTLS_THREADING_ALT)
+#if defined(PSA_CRYPTO_DRIVER_THREAD_EN)
+#include "mcux_psa_els_pkc_common_init.h"
+#else
+#include "els_pkc_mbedtls.h"
+#endif /* defined(PSA_CRYPTO_DRIVER_THREAD_EN) */
+#endif /* defined(MBEDTLS_THREADING_C) && defined(MBEDTLS_THREADING_ALT) */
+
+//! @addtogroup sbloader
+//! @{
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if 0
+#define SBLOADER_PRINTF(...)     \
+    do                           \
+    {                            \
+        PLOG_DEBUG(__VA_ARGS__); \
+    } while (0)
+#else
+#define SBLOADER_PRINTF(...)
+#endif
+
+/*!
+ * @brief load cpu1/cpu2 firmware.
+ */
+#define CIU_RST_SW2                (0x41240184U)
+#define CIU_RST_SW2_CPU1_RST_MASK  (0x40000000U)
+#define CIU2_RST_SW3               (0x4424011cU)
+#define CIU2_RST_SW3_CPU2_RST_MASK (0x00000010U)
+
+#define IMU_SYNC_MAGIC_PATTERN  (0xABCDEF89U)
+#define CPU1_MAGIC_PATTERN_ADDR (0x41380000U)
+#define CPU2_MAGIC_PATTERN_ADDR (0x443c0000U)
+
+#define SOCCTRL_CHIP_INFO_REV_NUM_MASK (0xFU)
+
+
+#define CLKCTL0_PSCCTL1_OTP_MASK  (0x20000U)
+#define RSTCTL0_PRSTCTL1_OTP_MASK (0x20000U)
+
+#define STAGING_BUF_SZ 256u
+typedef struct sb3_desc {
+    uint32_t fmt;
+    uint32_t sub_fmt;
+    uint32_t dst_addr;
+    uint32_t area_sz;
+} sb3_load_desc_t;
+
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+static status_t ldr_DoHeader_v3(fsl_api_core_context_t *ctx);
+static status_t ldr_DoDataRead(fsl_api_core_context_t *ctx);
+static status_t ldr_DoBlock(fsl_api_core_context_t *ctx);
+static status_t ldr_DoLoadCmd(fsl_api_core_context_t *ctx);
+static status_t ldr_DoExecuteCmd(fsl_api_core_context_t *ctx);
+static status_t ldr_ReadFromFlash(uint8_t * buf, uint32_t src_flash_offset, size_t read_sz);
+
+static status_t load_service_monolithic(LOAD_Target_Type loadTarget, uint32_t sourceAddr);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief nboot library context. */
+static fsl_api_core_context_t s_fsl_api_core_context = {0};
+static fsl_ldr_Context_v3_t s_sbloader_context;
+static uint8_t packetBuf[512]  = {0};
+static fsl_nboot_context_t g_nbootCtx = {0};
+#ifdef CONFIG_FW_VDLLV2
+static uint32_t vdll_image_base = 0;
+#endif
+
+static bootloader_tree_v0_t *g_bootloaderTree_v0;
+static bootloader_tree_v1_t *g_bootloaderTree_v1;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+__attribute__((__noinline__))
+static void sb3_Delay(uint32_t loop)
+{
+    if (loop > 0U)
+    {
+        __ASM volatile(
+            "1:                             \n"
+            "    SUBS   %0, %0, #1          \n"
+            "    CMP    %0, #0              \n"
+            "    BNE    1b                  \n"
+            :
+            : "r"(loop));
+    }
+}
+
+static void sb3_DelayUs(uint32_t us)
+{
+    uint32_t instNum;
+
+    instNum = ((SystemCoreClock + 999999UL) / 1000000UL) * us;
+    sb3_Delay((instNum + 2U) / 3U);
+}
+
+static uint32_t _ActiveApplicationRemapOffset(void)
+{
+    return (MFLASH_FLEXSPI->HADDROFFSET);
+}
+////////////////////////////////////////////////////////////////////////////
+//! @brief power on device implementation
+////////////////////////////////////////////////////////////////////////////
+void power_on_device_impl(LOAD_Target_Type loadTarget)
+{
+    uint8_t target_type = ((uint8_t)loadTarget & ~0x80);
+
+    if (LOAD_WIFI_FIRMWARE == target_type)
+    {
+        POWER_PowerOnWlan();
+    }
+    else if ((LOAD_BLE_FIRMWARE == target_type) || (LOAD_15D4_FIRMWARE == target_type))
+    {
+        POWER_PowerOnBle();
+    }
+    else
+    {
+        ; /* none to do */
+    }
+    // There's 2.6us gap from device Power-On till device sub-system power up.
+    // Do a time delay which >2.6us for device sub-system here.
+    sb3_DelayUs(5U);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief power off device implementation
+////////////////////////////////////////////////////////////////////////////
+void power_off_device_impl(LOAD_Target_Type loadTarget)
+{
+    uint8_t target_type = ((uint8_t)loadTarget & ~0x80);
+
+    if (LOAD_WIFI_FIRMWARE == target_type)
+    {
+        POWER_PowerOffWlan();
+    }
+    else if ((LOAD_BLE_FIRMWARE == target_type) || (LOAD_15D4_FIRMWARE == target_type))
+    {
+        POWER_PowerOffBle();
+    }
+    else
+    {
+        ; /* none to do */
+    }
+    sb3_DelayUs(5U);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief reset device
+////////////////////////////////////////////////////////////////////////////
+void reset_device(LOAD_Target_Type loadTarget)
+{
+    uint8_t target_type = ((uint8_t)loadTarget & ~0x80);
+    if (LOAD_WIFI_FIRMWARE == target_type)
+    {
+        *((uint32_t *)CIU_RST_SW2) = *((uint32_t *)CIU_RST_SW2) | CIU_RST_SW2_CPU1_RST_MASK;
+    }
+    else if ((LOAD_BLE_FIRMWARE == target_type) || (LOAD_15D4_FIRMWARE == target_type))
+    {
+        *((uint32_t *)CIU2_RST_SW3) = *((uint32_t *)CIU2_RST_SW3) | CIU2_RST_SW3_CPU2_RST_MASK;
+    }
+    else
+    {
+        ; /* none to do */
+    }
+}
+
+static fsl_ldr_Context_v3_t *get_sbloader_v3_context(fsl_api_core_context_t *ctx)
+{
+    return ctx->sbloaderCtx;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief get firmware version from otp
+////////////////////////////////////////////////////////////////////////////
+static fsl_nboot_status_t nboot_hal_get_secure_firmware_version(uint32_t *fwVer, LOAD_Target_Type loadTarget)
+{
+    if (fwVer == NULL)
+    {
+        return kStatus_NBOOT_InvalidArgument;
+    }
+
+    uint32_t tmpVersion               = 0u;
+    uint32_t trustedFwVersionFuses[4] = {0};
+    uint32_t fuseIdxStart;
+
+    uint8_t target_type = (uint8_t)loadTarget & ~0x80;
+     if (LOAD_WIFI_FIRMWARE == target_type)
+    {
+        fuseIdxStart = OTP_WIFI_FW_VER0_FUSE_IDX;
+    }
+    else if (LOAD_BLE_FIRMWARE == target_type)
+    {
+        fuseIdxStart = OTP_BLE_FW_VER0_FUSE_IDX;
+    }
+    else if (LOAD_15D4_FIRMWARE == target_type)
+    {
+        fuseIdxStart = OTP_15_4_FW_VER0_FUSE_IDX;
+    }
+    else
+    {
+        return kStatus_NBOOT_InvalidArgument;
+    }
+
+    for (uint32_t i = 0u; i < ARRAY_SIZE(trustedFwVersionFuses); i++)
+    {
+        status_t status = OCOTP_OtpFuseRead(fuseIdxStart, &trustedFwVersionFuses[i]);
+        if (status != kStatus_Success)
+        {
+            return kStatus_NBOOT_Fail;
+        }
+        ++fuseIdxStart;
+    }
+
+    for (uint32_t i = 0u; i < ARRAY_SIZE(trustedFwVersionFuses); i++)
+    {
+        // Only the low-half 16-bit is used for counter calculation
+        for (uint8_t j = 0U; j < 16U; j++)
+        {
+            if ((trustedFwVersionFuses[i] & (uint32_t)((uint32_t)(1U) << j)) != 0U)
+            {
+                ++tmpVersion;
+            }
+        }
+    }
+
+    *fwVer = tmpVersion;
+
+    return kStatus_NBOOT_Success;
+}
+////////////////////////////////////////////////////////////////////////////
+//! @brief fw download implementation
+////////////////////////////////////////////////////////////////////////////
+status_t sb3_fw_download_impl(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr)
+{
+    volatile uint32_t *magic_pattern_addr = NULL;
+    status_t status                       = kStatus_Fail;
+    int wait_count                        = 200;
+    uint8_t target_type                   = ((uint8_t)loadTarget & ~0x80);
+
+    if ((g_bootloaderTree_v1 == NULL) && ((get_chip_revision() == 1U) || (get_chip_revision() == 2U)))
+    {
+        g_bootloaderTree_v1 = ((bootloader_tree_v1_t *)0x13030000);
+    }
+    else if (g_bootloaderTree_v0 == NULL)
+    {
+        g_bootloaderTree_v0 = ((bootloader_tree_v0_t *)0x13024100);
+    }
+	else
+    {
+        ; /* none to do */
+    }
+
+    if (LOAD_WIFI_FIRMWARE == target_type)
+    {
+        magic_pattern_addr = (volatile uint32_t *)CPU1_MAGIC_PATTERN_ADDR;
+    }
+    else if ((LOAD_BLE_FIRMWARE == target_type) || (LOAD_15D4_FIRMWARE == target_type))
+    {
+        magic_pattern_addr = (volatile uint32_t *)CPU2_MAGIC_PATTERN_ADDR;
+    }
+#ifdef CONFIG_FW_VDLLV2
+    else if (LOAD_WIFI_VDLL_FIRMWARE == loadTarget)
+    {
+        status = load_service(loadTarget, sourceAddr);
+        return status;
+    }
+#endif
+    else
+    {
+        return status;
+    }
+
+    // Check if fw already active, if active skip download fw
+    if (IMU_SYNC_MAGIC_PATTERN == *((volatile uint32_t *)magic_pattern_addr))
+    {
+        status = kStatus_Success;
+        return status;
+    }
+
+    if (loadTarget & 0x80)
+    {
+        status = load_service_monolithic(loadTarget, sourceAddr);
+    }
+    else
+    {
+        status = load_service(loadTarget, sourceAddr);
+    }
+
+    // Wait for fw activation for 1s. Return fail if wait_count is used up.
+    while (wait_count != 0)
+    {
+        if (IMU_SYNC_MAGIC_PATTERN != *((volatile uint32_t *)magic_pattern_addr))
+        {
+            /* 5 ms delay */
+            sb3_DelayUs(1000 * 5);
+            wait_count--;
+            if (wait_count == 0)
+            {
+                status = kStatus_Fail;
+            }
+        }
+        else
+        {
+            status = kStatus_Success;
+            break;
+        }
+    }
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief fw reset implementation
+////////////////////////////////////////////////////////////////////////////
+status_t sb3_fw_reset_impl(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr)
+{
+    status_t status = kStatus_Fail;
+
+    power_off_device_impl(loadTarget);
+
+    status = sb3_fw_download_impl(loadTarget, flag, sourceAddr);
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief load command processing
+////////////////////////////////////////////////////////////////////////////
+static status_t ldr_DoLoadCmd(fsl_api_core_context_t *ctx)
+{
+    status_t status = kStatus_Fail;
+
+    fsl_ldr_Context_v3_t *context = get_sbloader_v3_context(ctx);
+
+    // check current data_block_position
+    if (context->data_block_position == context->block_data_size)
+    {
+        // we reached end of data section, need to get the next block
+        status = kStatus_Success;
+    }
+    else if (context->data_block_position + context->data_range_header.length <= context->block_data_size)
+    {
+        // the load data enough in data section (buffer)
+        (void)memcpy((uint8_t *)context->data_range_header.startAddress,
+                     (uint8_t *)&context->data_block[context->data_block_position], context->data_range_header.length);
+        // this load command completed.
+        // this data range section process finiskStatus_FLASH_Successhed.
+        context->in_data_range      = false;
+        context->data_range_handled = 0;
+        context->data_block_position += context->data_range_header.length + context->data_range_gap;
+        context->data_section_handled += context->data_range_header.length + context->data_range_gap;
+        status = kStatus_Success;
+    }
+    else
+    {
+        // we have partial data to load
+        (void)memcpy((uint8_t *)context->data_range_header.startAddress,
+                     (uint8_t *)&context->data_block[context->data_block_position],
+                     context->block_data_size - context->data_block_position);
+        context->data_range_handled = context->block_data_size - context->data_block_position;
+        context->data_range_header.startAddress += context->data_range_handled;
+        context->data_range_header.length -= context->data_range_handled;
+        context->data_block_position += context->data_range_handled;
+        context->data_section_handled += context->data_range_handled;
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief Execute command processing
+////////////////////////////////////////////////////////////////////////////
+static status_t ldr_DoExecuteCmd(fsl_api_core_context_t *ctx)
+{
+    fsl_ldr_Context_v3_t *context = get_sbloader_v3_context(ctx);
+    // this data range section process finished.
+    context->in_data_range      = false;
+    context->data_range_handled = 0;
+
+    // Actual jump is implemented in fsl_sbloader_finalize().
+    return (status_t)kStatusRomLdrPendingJumpCommand;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief data block processing
+////////////////////////////////////////////////////////////////////////////
+static status_t ldr_DoBlock(fsl_api_core_context_t *ctx)
+{
+    fsl_ldr_Context_v3_t *context = get_sbloader_v3_context(ctx);
+
+    status_t status = kStatus_Fail;
+    // new data range with new data block
+    fsl_sb3_data_range_header_t *data_range_header;
+    fsl_sb3_section_header_t *data_section_header;
+
+    while (context->in_data_block)
+    {
+        // check if we are in a data section
+        if (context->in_data_section)
+        {
+            // in process of a data section
+            data_section_header = &context->data_section_header;
+        }
+        else
+        {
+            // new data section started
+            data_section_header = (fsl_sb3_section_header_t *)(void *)&context->data_block[context->data_block_position];
+
+            // save data range section header
+            (void)memcpy(&context->data_section_header, data_section_header, sizeof(fsl_sb3_section_header_t));
+
+            // branch to section types (only data range is currently supported)
+            switch (data_section_header->sectionType)
+            {
+                case ((uint32_t)kSectionNone):
+                    status = kStatus_Success;
+                    break;
+                case ((uint32_t)kSectionDataRange):
+                    context->in_data_section      = true;
+                    context->data_section_handled = 0;
+                    context->in_data_range        = false;
+                    context->data_range_handled   = 0;
+                    context->data_block_position += sizeof(fsl_sb3_section_header_t);
+                    break;
+                case ((uint32_t)kSectionDiffUpdate):
+                case ((uint32_t)kSectionDDRConfig):
+                case ((uint32_t)kSectionRegister):
+                default:
+                    // non-supported section type
+                    SBLOADER_PRINTF("Bootloader: %s, invalid section type = %x", __func__,
+                                    data_section_header->sectionType);
+                    status = kStatus_Fail;
+                    break;
+            }
+            if (data_section_header->sectionType != (uint32_t)kSectionDataRange)
+            {
+                return status;
+            }
+        }
+
+        switch (data_section_header->sectionType)
+        {
+            case ((uint32_t)kSectionDataRange):
+            {
+                // check if we are in a data range
+                if (context->in_data_range)
+                {
+                    // continue current data range process
+                    data_range_header = &context->data_range_header;
+                }
+                else
+                {
+                    // started a new data range
+                    data_range_header =
+                        (fsl_sb3_data_range_header_t *)(void *)&context->data_block[context->data_block_position];
+
+                    // check command tag
+                    if (data_range_header->tag != SB3_DATA_RANGE_HEADER_TAG)
+                    {
+                        // bad data range section
+                        status = kStatus_Fail;
+                        SBLOADER_PRINTF("Bootloader: %s, invalid data range header tag = %x", __func__,
+                                        data_range_header->tag);
+                        return status;
+                    }
+
+                    // save data range section header
+                    (void)memcpy(&context->data_range_header, data_range_header, sizeof(fsl_sb3_data_range_header_t));
+                    context->in_data_range            = true;
+                    context->has_data_range_expansion = false;
+                    context->data_range_handled       = sizeof(fsl_sb3_data_range_header_t); // used anywhere?
+                    context->data_block_position += sizeof(fsl_sb3_data_range_header_t);
+                    context->data_section_handled += sizeof(fsl_sb3_data_range_header_t);
+
+                    // 16 bytes alignmnent check and handling
+                    context->data_range_gap = 0;
+
+                    switch ((fsl_sb3_cmd_t)data_range_header->cmd)
+                    {
+                        case kSB3_CmdLoad:
+                            context->data_range_gap =
+                                (SB3_DATA_ALIGNMENT_SIZE_IN_BYTE - (data_range_header->length & 0xFU)) & 0xFU;
+                            break;
+                        default:
+                            // Do nothing for the commands.
+                            break;
+                    }
+                }
+
+                switch (data_range_header->cmd)
+                {
+                    case ((uint32_t)kSB3_CmdLoad):
+                        if (!context->has_data_range_expansion)
+                        {
+                            SBLOADER_PRINTF("Bootloader: %s, Copy data range expansion", __func__);
+                            // check current data_block_position
+                            if (context->data_block_position == context->block_data_size)
+                            {
+                                // we reached end of data section, need to get the next block
+                                return kStatus_Success;
+                            }
+                            else if ((context->data_block_position + sizeof(fsl_sb3_data_range_expansion_t)) <=
+                                     context->block_data_size)
+                            {
+                                // save data range section header expansion.
+                                (void)memcpy(&context->data_range_expansion,
+                                             (fsl_sb3_data_range_expansion_t *)&context
+                                                 ->data_block[context->data_block_position],
+                                             sizeof(fsl_sb3_data_range_expansion_t));
+                                context->has_data_range_expansion = true;
+                                context->data_block_position += sizeof(fsl_sb3_data_range_expansion_t);
+                                context->data_section_handled += sizeof(fsl_sb3_data_range_expansion_t);
+                            }
+                            else
+                            {
+                                // Unaligned data range.
+                                return kStatus_Fail;
+                            }
+                        }
+                        else
+                        {
+                            SBLOADER_PRINTF("Bootloader: %s, Has data range expansion", __func__);
+                        }
+                        break;
+                    default:
+                        // Do nothing for the commands without header expansion.
+                        break;
+                }
+
+                // branch to range commands
+                switch (data_range_header->cmd)
+                {
+                    case ((uint32_t)kSB3_CmdLoad):
+                        status = ldr_DoLoadCmd(ctx);
+                        if (status != kStatus_Success)
+                        {
+                            return status;
+                        }
+                        break;
+                    case ((uint32_t)kSB3_CmdExecute):
+                        status = ldr_DoExecuteCmd(ctx);
+                        break;
+                    default:
+                        // this data range section process finished.
+                        context->in_data_range      = false;
+                        context->data_range_handled = 0;
+                        break;
+                }
+                if (data_range_header->cmd == (uint32_t)kSB3_CmdExecute)
+                {
+                    return status;
+                }
+
+                // check if we reach the end of this data section
+                if (context->data_section_handled == context->data_section_header.length)
+                {
+                    // this data section completed
+                    context->in_data_section = false;
+                }
+                else if (context->data_section_handled > context->data_section_header.length)
+                {
+                    // bad data section
+                    // return error
+                    SBLOADER_PRINTF("Bootloader: %s, bad data section.", __func__);
+                    status = kStatus_Fail;
+                    return status;
+                }
+                else
+                {
+                    ; /* none to do */
+                }
+
+                // check if we reach the end of this data block
+                if (context->data_block_position == context->block_data_size)
+                {
+                    // This data block process finished.
+                    context->block_buffer_position = 0;
+                    context->in_data_block         = false;
+                    context->data_block_position   = 0;
+                    context->Action                = (fsl_pLdrFnc_v3_t)ldr_DoDataRead;
+                    SBLOADER_PRINTF("Bootloader: %s, data blobck process done.", __func__);
+                    status = kStatus_Success;
+                }
+                else if (context->data_block_position > context->block_data_size)
+                {
+                    // bad block position
+                    // bad pointer
+                    SBLOADER_PRINTF("Bootloader: %s, bad block position.", __func__);
+                    status = kStatus_Fail;
+                    return status;
+                }
+                else if (context->data_block_position + SB3_DATA_ALIGNMENT_SIZE_IN_BYTE > context->block_data_size)
+                {
+                    // data is not 16 bytes aligned.
+                    // return error
+                    status = kStatus_Fail;
+                    SBLOADER_PRINTF("Bootloader: %s, data not aligned.", __func__);
+                    return status;
+                }
+                else
+                {
+                    ; /* none to do */
+                }
+            }
+            break;
+            case ((uint32_t)kSectionDiffUpdate):
+            case ((uint32_t)kSectionDDRConfig):
+            case ((uint32_t)kSectionRegister):
+            default:
+                // non-supported section type
+                SBLOADER_PRINTF("Bootloader: %s, non-supported section type = %x", __func__,
+                                data_section_header->sectionType);
+                status                 = kStatus_Fail;
+                context->in_data_block = false;
+                break;
+        }
+    }
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief data block decryption and handling
+////////////////////////////////////////////////////////////////////////////
+static status_t ldr_DoDataRead(fsl_api_core_context_t *ctx)
+{
+    status_t status                = kStatus_Fail;
+    fsl_nboot_status_t nbootResult = kStatus_NBOOT_Fail;
+
+    fsl_ldr_Context_v3_t *context = get_sbloader_v3_context(ctx);
+
+    // check block integrity
+    if (context->processedBlocks < ctx->nbootCtx->totalBlocks)
+    {
+        // call nboot lib to decrypt the data block
+        if ((get_chip_revision() == 1U) || (get_chip_revision() == 2U))
+        {
+            nbootResult = (fsl_nboot_status_t)g_bootloaderTree_v1->nbootDriver->nboot_sb3_load_block(
+                ctx->nbootCtx, (uint32_t *)&context->block_buffer[0]);
+        }
+        else
+        {
+            nbootResult = (fsl_nboot_status_t)g_bootloaderTree_v0->nbootDriver->nboot_sb3_load_block(
+                ctx->nbootCtx, (uint32_t *)&context->block_buffer[0]);
+        }
+        if (nbootResult == kStatus_NBOOT_Success)
+        {
+            context->block_buffer_position = 0;
+#if defined(NBOOT_IGNORE_SB3_COMMANDS)
+            if (g_nboot_ctx.processData != NBOOT_IGNORE_SB3_COMMANDS)
+#endif
+            {
+                context->in_data_block       = true;
+                context->data_block          = &context->block_buffer[context->data_block_offset];
+                context->data_block_position = 0;
+                context->processedBlocks++;
+                status = ldr_DoBlock(ctx);
+            }
+#if defined(NBOOT_IGNORE_SB3_COMMANDS)
+            else
+            {
+                status = kStatus_Success;
+            }
+#endif
+        }
+        else
+        {
+            SBLOADER_PRINTF("ROM API: %s, nboot_sb3_load_block is failed, status = %x", __func__, nbootResult);
+            status = kStatus_Fail;
+        }
+    }
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief header block handling
+////////////////////////////////////////////////////////////////////////////
+static status_t ldr_DoHeader_v3(fsl_api_core_context_t *ctx)
+{
+    status_t status = kStatus_Success;
+    fsl_nboot_sb3_load_manifest_parms_t manifestParms;
+
+    fsl_ldr_Context_v3_t *context = get_sbloader_v3_context(ctx);
+
+    do
+    {
+        fsl_nboot_sb3_header_t *header = (fsl_nboot_sb3_header_t *)(void *)&context->block_buffer[0];
+        if (context->block_buffer_size == sizeof(fsl_nboot_sb3_header_t))
+        {
+            // Update the buffer size to the size of Block 0.
+            context->block_buffer_size = header->imageTotalLength;
+            SBLOADER_PRINTF("ROM API: %s, manifest size = %x, but buffer size =%x", __func__,
+                            context->block_buffer_size, sizeof(context->block_buffer));
+            if (context->block_buffer_size > sizeof(context->block_buffer))
+            {
+                status = kStatus_Fail;
+                break;
+            }
+            // Resume the cleared buffer position.
+            context->block_buffer_position = sizeof(fsl_nboot_sb3_header_t);
+
+            status = kStatus_Success;
+            break;
+        }
+
+        if (context->block_buffer_size != header->imageTotalLength)
+        {
+            status = kStatus_Fail;
+            break;
+        }
+
+        (void)memset(&manifestParms, 0, sizeof(fsl_nboot_sb3_load_manifest_parms_t));
+
+        fsl_nboot_status_t nbootResult = nboot_hal_get_sb3_manifest_params(ctx->nbootCtx, &manifestParms);
+        if (nbootResult != kStatus_NBOOT_Success)
+        {
+            SBLOADER_PRINTF("ROM API: %s, nboot_hal_get_sb3_manifest_params is failed, status = %x", __func__,
+                            nbootResult);
+            status = kStatus_Fail;
+            break;
+        }
+
+        // call nboot lib to verify the block header
+        if ((get_chip_revision() == 1U) || (get_chip_revision() == 2U))
+        {
+            nbootResult = (fsl_nboot_status_t)g_bootloaderTree_v1->nbootDriver->nboot_sb3_load_manifest(
+                ctx->nbootCtx, (uint32_t *)(void *)header, &manifestParms);
+        }
+        else
+        {
+            nbootResult = (fsl_nboot_status_t)g_bootloaderTree_v0->nbootDriver->nboot_sb3_load_manifest(
+                ctx->nbootCtx, (uint32_t *)(void *)header, &manifestParms);
+        }
+        if (nbootResult == kStatus_NBOOT_Success)
+        {
+            context->data_block_offset = (uint8_t)(sizeof(uint32_t) /* blockNumber*/ + header->certificateBlockOffset -
+                                                   sizeof(fsl_nboot_sb3_header_t));
+            context->block_buffer_size = (uint32_t)context->data_block_offset + NBOOT_SB3_CHUNK_SIZE_IN_BYTES;
+            context->block_buffer_position = 0;
+            context->block_size            = header->blockSize;
+            context->block_data_size       = NBOOT_SB3_CHUNK_SIZE_IN_BYTES;
+            context->block_data_total      = context->block_size * ctx->nbootCtx->totalBlocks;
+            context->in_data_section       = false;
+            context->data_section_handled  = 0;
+            context->processedBlocks       = 0;
+            context->Action                = (fsl_pLdrFnc_v3_t)ldr_DoDataRead;
+            status                         = kStatus_Success;
+        }
+        else
+        {
+            SBLOADER_PRINTF("ROM API: %s, nboot_sb3_load_manifest is failed, status = %x", __func__, nbootResult);
+            status = kStatus_Fail;
+        }
+    } while (false);
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief Initialize the loader state machine.
+////////////////////////////////////////////////////////////////////////////
+status_t fsl_sbloader_init(fsl_api_core_context_t *ctx)
+{
+    status_t status = kStatus_InvalidArgument;
+
+    do
+    {
+        if (ctx == NULL)
+        {
+            break;
+        }
+
+        fsl_ldr_Context_v3_t *context = ctx->sbloaderCtx;
+
+        // Initialize the context
+        (void)memset(context, 0, sizeof(fsl_ldr_Context_v3_t));
+        context->block_buffer_size = sizeof(fsl_nboot_sb3_header_t);
+
+        // Process the first chunk of the image header
+        context->Action = (fsl_pLdrFnc_v3_t)ldr_DoHeader_v3;
+
+        // Initialize the allowed command set
+        context->commandSet = SBLOADER_V3_CMD_SET_ALL;
+
+        status = kStatus_Success;
+
+    } while (false);
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief Finalize the loader operations
+////////////////////////////////////////////////////////////////////////////
+status_t fsl_sbloader_finalize(fsl_api_core_context_t *ctx)
+{
+    status_t status = kStatus_Fail;
+
+    fsl_ldr_Context_v3_t *context = get_sbloader_v3_context(ctx);
+
+    if (context->data_range_header.cmd == (uint32_t)kSB3_CmdExecute)
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief Pump the loader state machine.///////////////////////////////////
+static status_t fsl_sbloader_pump(fsl_api_core_context_t *ctx, uint8_t *data, uint32_t length)
+{
+    status_t status = kStatus_InvalidArgument;
+    do
+    {
+        fsl_ldr_Context_v3_t *context = ctx->sbloaderCtx;
+        uint32_t required             = 0U;
+        uint32_t available            = 0U;
+        uint32_t readPosition         = 0U;
+
+        while (readPosition < length)
+        {
+            required  = context->block_buffer_size - context->block_buffer_position;
+            available = length - readPosition;
+
+            // copy what we need to complete a full chunk into the chunk buffer
+            if ((required > 0U) && (available > 0U))
+            {
+                uint32_t toCopy = required > available ? available : required;
+                if ((context->block_buffer_position < context->block_buffer_size) &&
+                    (context->block_buffer_position + toCopy <= context->block_buffer_size) &&
+                    (readPosition + toCopy <= length))
+                {
+                    if ((context->block_buffer_position + toCopy) >= sizeof(context->block_buffer))
+                    {
+                        // block buffer over-flow.
+                        SBLOADER_PRINTF("ROM API: %s, block buffer is overflown", __func__);
+                        status = kStatus_Fail;
+                        break;
+                    }
+                    (void)memcpy(&context->block_buffer[context->block_buffer_position], &data[readPosition], toCopy);
+                    required -= toCopy;
+                    available -= toCopy;
+                    readPosition += toCopy;
+                    context->block_buffer_position += toCopy;
+                    status = kStatus_Success;
+                }
+                else
+                {
+                    status = kStatus_Fail;
+                    break;
+                }
+            }
+
+            if (required == 0U)
+            {
+                // a full chunk was filled to process it
+                context->block_buffer_position = 0U;
+                status                         = (context->Action)(ctx);
+
+                if (status != kStatus_Success)
+                {
+                    if (status != (status_t)kStatusRomLdrPendingJumpCommand)
+                    {
+                        SBLOADER_PRINTF("sbloader Action failed: 0x%08x", status);
+                    }
+                    break;
+                }
+            }
+            else if (available == 0U)
+            {
+                // otherwise we are just going to wait for more data
+                status = (status_t)kStatusRomLdrDataUnderrun;
+                break;
+            }
+            else
+            {
+                ; /* None to do */
+            }
+        }
+    } while (false);
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief Read flash area loading to RAM buffer.
+// Direct read from flash is not allowed when remapping is active.
+// buf             : pointer to RAM buffer, its size must be sufficient to receive
+//                   the required number of bytes.
+// src_flash_offset: 'virtual' address in flash relative to start of flash storage.
+//                   Actual 'physical' address results from the addition of the remap offset.
+// read_sz         : Number of bytes to be read.
+////////////////////////////////////////////////////////////////////////////
+static status_t ldr_ReadFromFlash(uint8_t * buf, uint32_t src_flash_offset, size_t read_sz)
+{
+    status_t st;
+    static const uint32_t mflash_base = (1u << 27);
+    uint32_t remap_offset = _ActiveApplicationRemapOffset();
+    if (remap_offset == 0U)
+    {
+        memcpy(buf, (void*)src_flash_offset, read_sz);
+        st = kStatus_Success;
+    }
+    else
+    {
+        // similar to mflash_drv_log2phys
+        uint32_t phys_offset = (src_flash_offset + remap_offset) & ~mflash_base;
+        st = mflash_drv_read(phys_offset, (uint32_t *)buf, read_sz);
+    }
+    return st;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief Read SB3 area descriptor.
+// Direct read from flash is not allowed when remapping is active.
+// hdr       : pointer to RAM fsl_nboot_sb3_header_t structure.
+// sourceAddr: 'virtual' address where SB3 header is expected.
+////////////////////////////////////////////////////////////////////////////
+status_t read_nboot_sb3_header(fsl_nboot_sb3_header_t * hdr, uint32_t sourceAddr)
+{
+   return ldr_ReadFromFlash((uint8_t*)hdr, sourceAddr, sizeof(fsl_nboot_sb3_header_t));
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief load service with format of sb3
+// readOffset: image offset in flash
+////////////////////////////////////////////////////////////////////////////
+status_t loader_process_sb_file(uint32_t readOffset)
+{
+    status_t status                    = kStatus_Fail;
+    uint32_t packetLength              = sizeof(packetBuf);
+    s_fsl_api_core_context.sbloaderCtx = &s_sbloader_context;
+    s_fsl_api_core_context.nbootCtx    = &g_nbootCtx;
+    bool elsFlag                       = false;
+    uint32_t CSS_CTRL_context          = 0;
+#ifdef CONFIG_FW_VDLLV2
+    uint32_t counter;
+#endif
+
+    do
+    {
+        (void)POWER_EnableGDetVSensors();
+        if (((CLKCTL0->PSCCTL0 & CLKCTL0_PSCCTL0_ELS_MASK) == 0U) ||
+            ((CLKCTL0->PSCCTL1 & CLKCTL0_PSCCTL1_ELS_APB_MASK) == 0U) ||
+            ((RSTCTL0->PRSTCTL0 & RSTCTL0_PRSTCTL0_ELS_MASK) != 0U))
+        {
+            elsFlag = true;
+            CLOCK_EnableClock(kCLOCK_Els);
+            CLOCK_EnableClock(kCLOCK_ElsApb);
+            RESET_PeripheralReset(kELS_RST_SHIFT_RSTn);
+        }
+
+#if defined(MBEDTLS_THREADING_C) && defined(MBEDTLS_THREADING_ALT)
+        (void)mcux_els_mutex_lock();
+#endif
+
+        if ((get_chip_revision() == 1U) || (get_chip_revision() == 2U))
+        {
+            status = (int32_t)g_bootloaderTree_v1->nbootDriver->nboot_context_init(s_fsl_api_core_context.nbootCtx);
+        }
+        else
+        {
+            status = (int32_t)g_bootloaderTree_v0->nbootDriver->nboot_context_init(s_fsl_api_core_context.nbootCtx);
+        }
+        if (status != (status_t)kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        status = fsl_sbloader_init(&s_fsl_api_core_context);
+        if (status != kStatus_Success)
+        {
+            break;
+        }
+
+        // Pump the sbloader content and do sbloader handling until ROM see the jump command and jump to the image
+        while (true)
+        {
+            memcpy(packetBuf, (void*)readOffset, packetLength);
+
+            if ((get_chip_revision() == 1U) || (get_chip_revision() == 2U))
+            {
+                status = fsl_sbloader_pump(&s_fsl_api_core_context, packetBuf, packetLength);
+            }
+            else
+            {
+                status = g_bootloaderTree_v0->iapApiDriver->fsl_sbloader_pump(&s_fsl_api_core_context, packetBuf,
+                                                                              packetLength);
+            }
+
+            // kStatusRomLdrDataUnderrun means need more data
+            // kStatusRomLdrSectionOverrun means we reached the end of the sb file processing
+            // either of these are OK
+            if ((status == (status_t)kStatusRomLdrDataUnderrun) || (status == (status_t)kStatusRomLdrSectionOverrun))
+            {
+                status = kStatus_Success;
+            }
+            else if (status == (status_t)kStatusRomLdrPendingJumpCommand)
+            {
+                status = fsl_sbloader_finalize(&s_fsl_api_core_context);
+#ifdef CONFIG_FW_VDLLV2
+                assert((readOffset & 0x3U) == 0U);
+                for (counter = 0; counter < (packetLength + 7U) >> 2U; counter++)
+                {
+                    if (*(uint32_t *)readOffset == TAG_SB_V3)
+                    {
+                        vdll_image_base = readOffset;
+                        break;
+                    }
+                    else
+                    {
+                        readOffset += 4U;
+                    }
+                }
+#endif
+                break;
+            }
+            else
+            {
+                ; /* No necessary actions. */
+            }
+
+            if (status != kStatus_Success)
+            {
+                break;
+            }
+
+            readOffset += packetLength;
+        }
+    } while (false);
+
+    if (get_chip_revision() == 0U)
+    {
+        CSS_CTRL_context = ELS->ELS_CTRL;
+    }
+
+    if ((get_chip_revision() == 1U) || (get_chip_revision() == 2U))
+    {
+        (void)g_bootloaderTree_v1->nbootDriver->nboot_context_deinit(s_fsl_api_core_context.nbootCtx);
+    }
+    else
+    {
+        (void)g_bootloaderTree_v0->nbootDriver->nboot_context_deinit(s_fsl_api_core_context.nbootCtx);
+    }
+
+    if (get_chip_revision() == 0U)
+    {
+        ELS->ELS_CTRL = (CSS_CTRL_context & 0xFFU);
+    }
+
+#if defined(MBEDTLS_THREADING_C) && defined(MBEDTLS_THREADING_ALT)
+    (void)mcux_els_mutex_unlock();
+#endif
+
+    if (elsFlag == true)
+    {
+        RESET_SetPeripheralReset(kELS_RST_SHIFT_RSTn);
+        CLOCK_DisableClock(kCLOCK_ElsApb);
+        CLOCK_DisableClock(kCLOCK_Els);
+    }
+    POWER_DisableGDetVSensors();
+
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief load service with format of raw binary image
+// readOffset: image offset in flash
+////////////////////////////////////////////////////////////////////////////
+static status_t loader_process_raw_file(uint32_t readOffset)
+{
+    status_t status = kStatus_Fail;
+    uint32_t *src_addr;
+    uint32_t *dst_addr;
+    uint32_t code_size;
+    uint32_t *data_ptr      = (uint32_t *)readOffset;
+    uint32_t total_raw_size = 0;
+
+#ifdef CONFIG_FW_VDLLV2
+    if ((*data_ptr == LOADER_RAW_BINARY_FORMAT) && (*(data_ptr + 1) == LOADER_VDLL_RAW_BINARY_FORMAT))
+    {
+        src_addr  = data_ptr + 4;
+        dst_addr  = (uint32_t *)*(data_ptr + 2);
+        code_size = *(data_ptr + 3);
+        (void)memcpy(dst_addr, src_addr, code_size);
+        status = kStatus_Success;
+    }
+    else
+#endif
+    {
+        do
+        {
+            if (*data_ptr != LOADER_RAW_BINARY_FORMAT)
+            {
+                break;
+            }
+
+            src_addr  = data_ptr + 4;
+            dst_addr  = (uint32_t *)*(data_ptr + 2);
+            code_size = *(data_ptr + 3);
+            // Check for raw ending segment
+            if (((uint32_t)src_addr == 0xffffffffU) || ((uint32_t)dst_addr == 0xffffffffU))
+            {
+                if (code_size == total_raw_size)
+                {
+                    status = kStatus_Success;
+#ifdef CONFIG_FW_VDLLV2
+                    vdll_image_base = (uint32_t)(data_ptr + 4);
+#endif
+                }
+                break;
+            }
+
+            (void)memcpy(dst_addr, src_addr, code_size);
+            data_ptr += 4U + (code_size >> 2U);
+            total_raw_size += code_size;
+        } while (true);
+    }
+
+    return status;
+}
+
+static status_t loader_process_raw_file_monolithic(uint32_t readOffset)
+{
+    status_t status = kStatus_Fail;
+    uint32_t *dst_addr;
+    uint32_t code_size;
+    uint32_t sz;
+
+
+    uint32_t total_raw_size = 0U;
+    uint8_t staging_buf[STAGING_BUF_SZ] = { 0u };
+
+    do {
+        sb3_load_desc_t *p_desc = (sb3_load_desc_t*)&staging_buf[0];
+        status_t flash_st;
+        /* Firs read the SB3 area descriptor */
+        flash_st = ldr_ReadFromFlash(&staging_buf[0], readOffset, sizeof(sb3_load_desc_t));
+        if (flash_st != kStatus_Success)
+        {
+            break;
+        }
+        readOffset += sizeof(sb3_load_desc_t);
+
+        if (p_desc->fmt != LOADER_RAW_BINARY_FORMAT)
+        {
+            break;
+        }
+
+        dst_addr  = (uint32_t*)p_desc->dst_addr;
+        code_size = p_desc->area_sz;
+
+        // Check for raw ending segment
+        if (p_desc->dst_addr == 0xffffffffU)
+        {
+            if (code_size == total_raw_size)
+            {
+                status = kStatus_Success;
+#ifdef CONFIG_FW_VDLLV2
+                vdll_image_base = readOffset;
+#endif
+            }
+            break;
+        }
+
+        /* start of indirect memcpy to destination */
+        sz = code_size;
+        while (sz >= STAGING_BUF_SZ)
+        {
+            flash_st = ldr_ReadFromFlash(&staging_buf[0], readOffset, STAGING_BUF_SZ);
+            if (flash_st != kStatus_Success)
+            {
+                break;
+            }
+            (void)memcpy(dst_addr, &staging_buf[0], STAGING_BUF_SZ);
+            readOffset += STAGING_BUF_SZ;
+            dst_addr += STAGING_BUF_SZ/4;
+            sz -= STAGING_BUF_SZ;
+        }
+        if (flash_st != kStatus_Success)
+        {
+            break;
+        }
+        /* last chunk smaller than staging buffer */
+        if (sz > 0U)
+        {
+            flash_st = ldr_ReadFromFlash(&staging_buf[0], readOffset, sz);
+            if (flash_st != kStatus_Success)
+            {
+                break;
+            }
+            (void)memcpy(dst_addr, &staging_buf[0], sz);
+            readOffset += sz;
+            dst_addr += (sz+3U)/4U;
+        }
+        /* at this point are is fully consumed and copied to destination : */
+#ifdef CONFIG_FW_VDLLV2
+        if ((p_desc->sub_fmt == LOADER_VDLL_RAW_BINARY_FORMAT))
+        {
+            status = kStatus_Success;
+            break;
+        }
+#endif
+        total_raw_size += code_size;
+
+    } while (true);
+
+    return status;
+}
+
+#ifndef __ZEPHYR__
+static bool __FlexSpiFlashInit(void)
+{
+    bool ret = false;
+    if (((CLKCTL0->PSCCTL0 & CLKCTL0_PSCCTL0_FLEXSPI0_MASK) == 0U) ||
+        ((RSTCTL0->PRSTCTL0 & RSTCTL0_PRSTCTL0_FLEXSPI0_MASK) != 0U))
+    {
+        CLOCK_EnableClock(kCLOCK_Flexspi);
+        RESET_PeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+        BOARD_SetFlexspiClock(FLEXSPI, 2U, 2U);
+        BOARD_InitFlash(FLEXSPI);
+        ret = true;
+    }
+    return ret;
+}
+
+static void __FlexSpiFlashDeInit(void)
+{
+    RESET_ClearPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+    BOARD_DeinitFlash(FLEXSPI);
+    CLOCK_AttachClk(kNONE_to_FLEXSPI_CLK);
+    CLOCK_DisableClock(kCLOCK_Flexspi);
+    RESET_SetPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+}
+
+#endif
+
+static int __OtpInit(void)
+{
+    int ret = 0; /* will stay 0 if nothing to do */
+    if (((CLKCTL0->PSCCTL1 & CLKCTL0_PSCCTL1_OTP_MASK) == 0U) ||
+        ((RSTCTL0->PRSTCTL1 & RSTCTL0_PRSTCTL1_OTP_MASK) != 0U))
+    {
+        status_t st;
+#ifdef USE_OCOTP_DRIVER_IN_LOAD_SERVICE
+        st = OCOTP_OtpInit();
+#else
+        if ((get_chip_revision() == 1U) || (get_chip_revision() == 2U))
+        {
+            st = g_bootloaderTree_v1->otpDriver->init(0U);
+        }
+        else
+        {
+            RESET_PeripheralReset(kOTP_RST_SHIFT_RSTn);
+            st = g_bootloaderTree_v0->otpDriver->init(0U);
+        }
+#endif
+        if (st != kStatus_Success)
+        {
+            ret = -1;
+        }
+        else
+        {
+            ret = 1;
+        }
+    }
+    return ret;
+}
+
+static int __OtpDeInit(void)
+{
+    int ret = -1;
+#ifdef USE_OCOTP_DRIVER_IN_LOAD_SERVICE
+        if (OCOTP_OtpDeinit() == kStatus_Success)
+        {
+            ret = 0;
+        }
+#else
+        if ((get_chip_revision() == 1U) || (get_chip_revision() == 2U))
+        {
+            if (g_bootloaderTree_v1->otpDriver->deinit() == kStatus_Success)
+            {
+                ret = 0;
+            }
+        }
+        else
+        {
+            if (g_bootloaderTree_v0->otpDriver->deinit() == kStatus_Success)
+            {
+                ret = 0;
+            }
+        }
+#endif
+    return ret;
+}
+
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief load service
+// loadTarget: LOAD_WIFI_FIRMWARE / LOAD_BLE_FIRMWARE / LOAD_15D4_FIRMWARE
+// sourceAddr: load firmware source address, if 0 load default address
+////////////////////////////////////////////////////////////////////////////
+status_t load_service(LOAD_Target_Type loadTarget, uint32_t sourceAddr)
+{
+    status_t status = kStatus_Fail;
+    fsl_nboot_sb3_header_t *pt_a_ptr;
+    fsl_nboot_sb3_header_t *pt_b_ptr;
+    fsl_nboot_sb3_header_t *active_pt_ptr;
+    uint32_t firmwareVersion = 0xFFFFFFFFU;
+    int otp_status           = 0;
+#ifndef __ZEPHYR__
+    bool flexspiFlag         = __FlexSpiFlashInit();
+#endif
+
+    if (LOAD_WIFI_FIRMWARE == loadTarget)
+    {
+        if (sourceAddr == 0U)
+        {
+            pt_a_ptr = (fsl_nboot_sb3_header_t *)WIFI_IMAGE_A_OFFSET;
+            pt_b_ptr = (fsl_nboot_sb3_header_t *)WIFI_IMAGE_B_OFFSET;
+        }
+        else
+        {
+            pt_a_ptr = (fsl_nboot_sb3_header_t *)sourceAddr;
+            pt_b_ptr = (fsl_nboot_sb3_header_t *)(sourceAddr + WIFI_IMAGE_SIZE_MAX);
+        }
+    }
+    else if (LOAD_BLE_FIRMWARE == loadTarget)
+    {
+        if (sourceAddr == 0U)
+        {
+            pt_a_ptr = (fsl_nboot_sb3_header_t *)BLE_IMAGE_A_OFFSET;
+            pt_b_ptr = (fsl_nboot_sb3_header_t *)BLE_IMAGE_B_OFFSET;
+        }
+        else
+        {
+            pt_a_ptr = (fsl_nboot_sb3_header_t *)sourceAddr;
+            pt_b_ptr = (fsl_nboot_sb3_header_t *)(sourceAddr + BLE_IMAGE_SIZE_MAX);
+        }
+    }
+    else if (LOAD_15D4_FIRMWARE == loadTarget)
+    {
+        if (sourceAddr == 0U)
+        {
+            pt_a_ptr = (fsl_nboot_sb3_header_t *)Z154_IMAGE_A_OFFSET;
+            pt_b_ptr = (fsl_nboot_sb3_header_t *)Z154_IMAGE_B_OFFSET;
+        }
+        else
+        {
+            pt_a_ptr = (fsl_nboot_sb3_header_t *)sourceAddr;
+            pt_b_ptr = (fsl_nboot_sb3_header_t *)(sourceAddr + Z154_IMAGE_SIZE_MAX);
+        }
+    }
+#ifdef CONFIG_FW_VDLLV2
+    else if (LOAD_WIFI_VDLL_FIRMWARE == loadTarget)
+    {
+        assert(vdll_image_base != 0U);
+        pt_a_ptr = (fsl_nboot_sb3_header_t *)(vdll_image_base + sourceAddr);
+        pt_b_ptr = NULL;
+    }
+#endif
+    else
+    {
+        return kStatus_Fail;
+    }
+
+#ifdef MCUBOOT_APPLICATION
+    {
+        /* Skip MCUBoot header if present */
+
+        struct image_header *header;
+
+        header = (void *)pt_a_ptr;
+        if (header->ih_magic == IMAGE_MAGIC)
+        {
+            pt_a_ptr = (void *)(((uint8_t *)pt_a_ptr) + header->ih_hdr_size);
+        }
+
+        header = (void *)pt_b_ptr;
+        if (header->ih_magic == IMAGE_MAGIC)
+        {
+            pt_b_ptr = (void *)(((uint8_t *)pt_b_ptr) + header->ih_hdr_size);
+        }
+    }
+#endif
+
+    otp_status = __OtpInit();
+    if (otp_status < 0)
+    {
+        return kStatus_Fail;
+    }
+
+#ifdef CONFIG_FW_VDLLV2
+    if (LOAD_WIFI_VDLL_FIRMWARE != loadTarget)
+#endif
+    {
+        if (nboot_hal_get_secure_firmware_version(&firmwareVersion, loadTarget) != kStatus_NBOOT_Success)
+        {
+            return kStatus_Fail;
+        }
+
+        // imu init may be called before or after load_service(), not sure user will do in which sequence.
+        // If imu init is before load_service(), it is not appropriate do Power-Off here, then comment out Power-Off.
+        // power_off_device_impl(); // temporarily comment out for PDM Non-UPF version
+
+        power_on_device_impl(loadTarget);
+    }
+
+    /* Check partition TAG and select active partition */
+    if ((pt_a_ptr->magic != TAG_SB_V3) && (pt_b_ptr->magic != TAG_SB_V3))
+    {
+        active_pt_ptr = pt_a_ptr;
+        status        = loader_process_raw_file((uint32_t)active_pt_ptr);
+    }
+    else if ((pt_a_ptr->magic == TAG_SB_V3) && (pt_b_ptr->magic != TAG_SB_V3))
+    {
+        active_pt_ptr = pt_a_ptr;
+#ifdef CONFIG_FW_VDLLV2
+        if (LOAD_WIFI_VDLL_FIRMWARE != loadTarget)
+        {
+#endif
+            if (active_pt_ptr->firmwareVersion < firmwareVersion)
+            {
+                return kStatus_Fail;
+            }
+#ifdef CONFIG_FW_VDLLV2
+        }
+#endif
+        status = loader_process_sb_file((uint32_t)active_pt_ptr);
+    }
+    else if ((pt_a_ptr->magic != TAG_SB_V3) && (pt_b_ptr->magic == TAG_SB_V3))
+    {
+        active_pt_ptr = pt_b_ptr;
+        if (active_pt_ptr->firmwareVersion < firmwareVersion)
+        {
+            return kStatus_Fail;
+        }
+        status = loader_process_sb_file((uint32_t)active_pt_ptr);
+    }
+    else
+    {
+        if (pt_a_ptr->firmwareVersion >= pt_b_ptr->firmwareVersion)
+        {
+            active_pt_ptr = pt_a_ptr;
+        }
+        else
+        {
+            active_pt_ptr = pt_b_ptr;
+        }
+
+        if (active_pt_ptr->firmwareVersion < firmwareVersion)
+        {
+            return kStatus_Fail;
+        }
+        status = loader_process_sb_file((uint32_t)active_pt_ptr);
+    }
+
+    if (otp_status != 0)
+    {
+        /* OTP init was done here */
+        (void)__OtpDeInit();
+    }
+
+    if (status == kStatus_Success)
+    {
+        reset_device(loadTarget);
+    }
+
+#ifndef __ZEPHYR__
+    if (flexspiFlag)
+    {
+        __FlexSpiFlashDeInit();
+    }
+#endif
+    return status;
+}
+
+
+static status_t load_service_monolithic(LOAD_Target_Type loadTarget, uint32_t sourceAddr)
+{
+    status_t status = kStatus_Fail;
+    uint32_t hdr_a = 0UL;
+    fsl_nboot_sb3_header_t boot_hdr;
+    fsl_nboot_sb3_header_t *pt_a_ptr = &boot_hdr;
+    uint32_t firmwareVersion = 0xFFFFFFFFU;
+    uint32_t sel_fw_ver;
+    int otp_status           = 0;
+
+    memset(&boot_hdr, 0xff, sizeof(fsl_nboot_sb3_header_t));
+
+#ifndef __ZEPHYR__
+    bool flexspiFlag         = __FlexSpiFlashInit();
+#endif
+    (void)mflash_drv_init();
+    do {
+        status_t ret = kStatus_Fail;
+        if ((LOAD_WIFI_FW_MONOLITHIC != loadTarget) && (LOAD_BLE_FW_MONOLITHIC != loadTarget) && (LOAD_15D4_FW_MONOLITHIC != loadTarget))
+        {
+            break;
+        }
+        if (sourceAddr == 0UL)
+        {
+            break;
+        }
+        hdr_a = sourceAddr;
+
+        otp_status = __OtpInit();
+        if (otp_status < 0)
+        {
+            break;
+        }
+
+        if (nboot_hal_get_secure_firmware_version(&firmwareVersion, loadTarget) != kStatus_NBOOT_Success)
+        {
+           break;
+        }
+
+        // imu init may be called before or after load_service(), not sure user will do in which sequence.
+        // If imu init is before load_service(), it is not appropriate do Power-Off here, then comment out Power-Off.
+        // power_off_device_impl(); // temporarily comment out for PDM Non-UPF version
+
+        power_on_device_impl(loadTarget);
+
+        ret = ldr_ReadFromFlash((uint8_t*)pt_a_ptr, hdr_a, sizeof(fsl_nboot_sb3_header_t ));
+        if (ret != kStatus_Success)
+        {
+            break;
+        }
+        /* Check partition TAG and select active partition */
+        if (pt_a_ptr->magic == TAG_SB_V3)
+        {
+            sel_fw_ver = pt_a_ptr->firmwareVersion;
+
+            if (sel_fw_ver < firmwareVersion)
+            {
+                break;
+            }
+            status = loader_process_sb_file(hdr_a);
+        }
+        else
+        {
+            status = loader_process_raw_file_monolithic(hdr_a);
+        }
+
+    } while (false);
+
+    if (otp_status != 0)
+    {
+        /* OTP init was done here so undo it here */
+        (void)__OtpDeInit();
+    }
+
+    if (status == kStatus_Success)
+    {
+        reset_device(loadTarget);
+    }
+#ifndef __ZEPHYR__
+    if (flexspiFlag)
+    {
+        __FlexSpiFlashDeInit();
+    }
+#endif
+    return status;
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief get chip revision
+////////////////////////////////////////////////////////////////////////////
+uint8_t get_chip_revision(void)
+{
+    return (uint8_t)(SOCCTRL->CHIP_INFO & SOCCTRL_CHIP_INFO_REV_NUM_MASK);
+}
+
+//! @}
+////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/api_tree_root.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/api_tree_root.h
new file mode 100644
index 0000000000..27d44c054b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/api_tree_root.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2016-2019, 2021,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef __API_TREE_ROOT_H__
+#define __API_TREE_ROOT_H__
+
+#include "fsl_loader_utils.h"
+#include "nboot_rom_api_table.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+// Load and set user appplication boot options stored in specific register
+#define LOAD_USER_APP_BOOT_OPTIONS()        (SYSCON_USER_APP_BOOT_OPTIONS)
+#define CLEAR_USER_APP_BOOT_OPTIONS()       (SYSCON_USER_APP_BOOT_OPTIONS = 0u)
+#define SET_USER_APP_BOOT_OPTIONS(value)    (SYSCON_USER_APP_BOOT_OPTIONS = value)
+
+//! @brief Boot parameters of the user application
+//!  WORD    OFFSET      FIELD                              DESCRIPTION
+//!          [31:24]     TAG                                Must be '0xEB'
+//!          [23:20]     Boot mode                          0:Master boot mode; 1: ISP boot
+//!          [19:16]     Boot interface                     0:USART 1:I2C 2:SPI 3:USB HID 4:QSPI 5:USB DFU
+//!          [15:12]     Boot instance(Channel)             0 or 1; For SD or MMC,this is to select the instance
+//!                                                         For FLEXSPI boot, this select the Channel A or Channel B
+//!          [11:08]     Redundant boot image index         Redundant boot image index for FlexSPI NOR flash
+//!          [07:00]     Reserved
+//!
+//!  TAG[31:24]	    BOOT MODE[23:20]    INTERFACE[19:16]    INSTANCE[15:12]     RBII    Reserved[07:00]     COMBINATION     BOOT ACTION
+//!  0xEB  	        0                   0	                X	                X       X	                0xEB00XXXX	    MASTR BOOT: USART
+//!	                0	                1	                X	                X       X	                0xEB01XXXX	    MASTR BOOT: I2C
+//!	                0	                2	                X	                X       X	                0xEB02XXXX	    MASTR BOOT: SPI
+//!	                0	                3	                X	                X       X	                0xEB03XXXX	    MASTR BOOT: USB HID
+//!	                0	                4	                X	                0       X	                0xEB0400XX	    MASTR BOOT: FlexSPI Channel A:boot image index 0
+//!	                0	                4	                X	                1       X	                0xEB0401XX	    MASTR BOOT: FlexSPI Channel A:boot image index 1
+//!	                0                   4	                X	                0       X	                0xEB0410XX	    MASTR BOOT: FlexSPI Channel B:boot image index 0
+//!	                0	                4	                X	                1       X	                0xEB0411XX	    MASTR BOOT: FlexSPI Channel B:boot image index 1
+//!	                0	                5	                X	                X       X	                0xEB05XXXX	    MASTR BOOT: USB DFU
+//!	                1	                0	                X	                X       X	                0xEB10XXXX	    ISP BOOT: USART
+//!	                1	                1	                X	                X       X	                0xEB11XXXX	    ISP BOOT: I2C
+//!	                1	                2	                X	                X       X	                0xEB12XXXX	    ISP BOOT: SPI
+//!
+
+typedef struct _fsl_user_app_boot_invoke_option
+{
+    union
+    {
+        struct
+        {
+            uint32_t reserved           : 8;
+            uint32_t boot_image_index   : 4;
+            uint32_t instance           : 4;
+            uint32_t boot_interface     : 4;
+            uint32_t mode               : 4;
+            uint32_t tag                : 8;
+        } B;
+        uint32_t U;
+    } option;
+} fsl_user_app_boot_invoke_option_t;
+
+//! @brief Boot interface can be selected by user application
+//! @note  For USB-HID QSPI USB-DFU SD MMC, these interfaces are invalid for ISP boot
+enum
+{
+    kUserAppBootPeripheral_UART     = 0u,
+    kUserAppBootPeripheral_I2C      = 1u,
+    kUserAppBootPeripheral_SPI      = 2u,
+    kUserAppBootPeripheral_USB_HID  = 3u,
+    kUserAppBootPeripheral_FLEXSPI  = 4u,
+    kUserAppBootPeripheral_DFU      = 5u
+};
+
+//! @brief Boot mode can be selected by user application
+//! @note  For master boot, valid boot insterfaces for user application are USART I2C SPI USB-HID USB-DFU SD MMC
+//!        For ISP boot, valid boot interfaces for user application are USART I2C SPI
+enum
+{
+    kUserAppBootMode_MasterBoot = 0,
+    kUserAppBootMode_IspBoot    = 1,
+};
+
+
+//!@brief OTP driver API Interface for A0
+typedef struct
+{
+    uint32_t version;
+    status_t (*init)(uint32_t src_clk_freq);
+    status_t (*deinit)(void);
+    status_t (*fuse_read)(uint32_t addr, uint32_t *data);
+    status_t (*fuse_program)(uint32_t addr, uint32_t data, bool lock);
+    status_t (*reload)(void);
+    status_t (*crc_check)(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
+    status_t (*crc_calc)(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
+    status_t (*crc_check_sw)(uint32_t *src, uint32_t numberOfWords, uint32_t crc_fuse_idx);
+} ocotp_driver_v0_t;
+
+//!@brief OTP driver API Interface for A1/A2
+typedef struct
+{
+    uint32_t version;
+    status_t (*init)(uint32_t src_clk_freq);
+    status_t (*deinit)(void);
+    status_t (*fuse_read)(uint32_t addr, uint32_t *data, uint32_t argChk);
+    status_t (*fuse_program)(uint32_t addr, uint32_t data, bool lock);
+    status_t (*reload)(void);
+    status_t (*crc_check)(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
+    status_t (*crc_calc)(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
+    status_t (*crc_check_sw)(uint32_t *src, uint32_t numberOfWords, uint32_t crc_fuse_idx);
+} ocotp_driver_v1_t;
+
+//! @brief Root of the bootloader API tree for A0.
+//!
+//! An instance of this struct resides in read-only memory in the bootloader. It
+//! provides a user application access to APIs exported by the bootloader.
+//!
+//! @note The order of existing fields must not be changed.
+//!
+//! @ingroup context
+typedef struct BootloaderTree_v0
+{
+    void (*runBootloader)(void *arg);                               //!< Function to start the bootloader executing.
+    fsl_standard_version_t                      version;                //!< Bootloader version number.
+    const char                              *copyright;             //!< Copyright string.
+    const uint32_t                          reservedBootloader2;
+    const nboot_interface_v0_t              *nbootDriver;           //!< Image authentication API.
+    const uint32_t                          reservedBootloader3;
+    const ocotp_driver_v0_t                 *otpDriver;             //!< OTP driver API.
+    const fsl_iap_api_interface_t               *iapApiDriver;
+} bootloader_tree_v0_t;
+
+//! @brief Root of the bootloader API tree for A1/A2.
+//!
+//! An instance of this struct resides in read-only memory in the bootloader. It
+//! provides a user application access to APIs exported by the bootloader.
+//!
+//! @note The order of existing fields must not be changed.
+//!
+//! @ingroup context
+typedef struct BootloaderTree_v1
+{
+    void (*runBootloader)(void *arg);                               //!< Function to start the bootloader executing.
+    fsl_standard_version_t                      version;                //!< Bootloader version number.
+    const char                              *copyright;             //!< Copyright string.
+    const uint32_t                          reservedBootloader2;
+    const nboot_interface_v1_t              *nbootDriver;           //!< Image authentication API.
+    const uint32_t                          reservedBootloader3;
+    const ocotp_driver_v1_t                 *otpDriver;             //!< OTP driver API.
+    const fsl_iap_api_interface_t               *iapApiDriver;
+} bootloader_tree_v1_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // __API_TREE_ROOT_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader.h
new file mode 100644
index 0000000000..e595a2c2e4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2016, 2022,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_LOADER_H__
+#define __FSL_LOADER_H__
+
+#include <stdint.h>
+#include "fsl_common.h"
+
+typedef enum
+{
+    LOAD_WIFI_FIRMWARE = 1,
+    LOAD_BLE_FIRMWARE,
+    LOAD_15D4_FIRMWARE,
+#ifdef CONFIG_FW_VDLLV2
+    LOAD_WIFI_VDLL_FIRMWARE,
+#endif
+    LOAD_WIFI_FW_MONOLITHIC = 0x81,
+    LOAD_BLE_FW_MONOLITHIC  = 0x82,
+    LOAD_15D4_FW_MONOLITHIC = 0x83,
+    LOAD_TYPE_MAX,
+} LOAD_Target_Type;
+
+void power_on_device(LOAD_Target_Type loadTarget);
+void power_off_device(LOAD_Target_Type loadTarget);
+
+status_t sb3_fw_download(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+status_t sb3_fw_reset(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+
+//! @}
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader_utils.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader_utils.h
new file mode 100644
index 0000000000..f9bd6041aa
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader_utils.h
@@ -0,0 +1,670 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_LOADER_UTILS_H__
+#define __FSL_LOADER_UTILS_H__
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_loader.h"
+#include "fusemap.h"
+#include "fsl_ocotp.h"
+#include "fsl_os_abstraction.h"
+
+//! @addtogroup sbloader
+//! @{
+/*! @brief Status group numbers. */
+#define kStatusGroup_SBLoader                  (101U)
+#define NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES  (48u)
+#define NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES (48u)
+#define NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES  (48u)
+#define NBOOT_EC_COORDINATE_MAX_SIZE           NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES
+#define NBOOT_ROOT_CERT_COUNT                  (4u)
+#define NBOOT_SB3_CHUNK_SIZE_IN_BYTES          (256u)
+#define NBOOT_KEYINFO_WORDLEN                  (23u)
+#define NXPCLHASH_WA_SIZE_MAX                  (128u + 64u)
+#define NBOOT_CONTEXT_BYTELEN                  (192u + NXPCLHASH_WA_SIZE_MAX)
+#define NBOOT_CONTEXT_WORDLEN                  (NBOOT_CONTEXT_BYTELEN / sizeof(uint32_t))
+#define NXPCLCSS_HASH_RTF_OUTPUT_SIZE          ((size_t)32U)
+
+#define SECURE_TERM_PART_LOCK        (0x6ac3c36au)
+#define SECURE_TERM_PART_OPEN        (0xc36ac36au)
+#define SECURE_TERM_SECURE_PART_OPEN (0xc36a6ac3u)
+#define SECURE_TERM_FA_PART_OPEN     (0xc3c36a6au)
+#define SECURE_OEM_FA_PART_OPEN      (0xc3c3a6a6u)
+
+#define LOADER_RAW_BINARY_FORMAT      (0x72617762U)
+#ifdef CONFIG_FW_VDLLV2
+#define LOADER_VDLL_RAW_BINARY_FORMAT (0x76646c6cU)
+#endif
+
+/*! @brief partition table constants. */
+#define WIFI_IMAGE_SIZE_MAX (0xa0000U)
+#define BLE_IMAGE_SIZE_MAX  (0x50000U)
+#define Z154_IMAGE_SIZE_MAX (0x50000U)
+#ifndef WIFI_IMAGE_A_OFFSET
+#define WIFI_IMAGE_A_OFFSET (0x08400000U)
+#endif
+#define WIFI_IMAGE_B_OFFSET (WIFI_IMAGE_A_OFFSET + WIFI_IMAGE_SIZE_MAX) // 0x4a0000
+#define BLE_IMAGE_A_OFFSET  (WIFI_IMAGE_B_OFFSET + WIFI_IMAGE_SIZE_MAX) // 0x540000
+#define BLE_IMAGE_B_OFFSET  (BLE_IMAGE_A_OFFSET + BLE_IMAGE_SIZE_MAX)   // 0x590000
+#define Z154_IMAGE_A_OFFSET (BLE_IMAGE_B_OFFSET + BLE_IMAGE_SIZE_MAX)   // 0x5e0000
+#define Z154_IMAGE_B_OFFSET (Z154_IMAGE_A_OFFSET + Z154_IMAGE_SIZE_MAX) // 0x630000
+
+/** Type for nboot status codes */
+typedef uint32_t fsl_nboot_status_t;
+
+/**
+ * \defgroup nbootStatusValues  This type defines status return values used by NBOOT functions that are not easily
+ * disturbed by Fault Attacks
+ * @{
+ */
+#define kStatus_NBOOT_Success                ((fsl_nboot_status_t)0x5A5A5A5Au) /*!< Operation completed successfully. */
+#define kStatus_NBOOT_Fail                   ((fsl_nboot_status_t)0x5A5AA5A5u) /*!< Operation failed. */
+#define kStatus_NBOOT_InvalidArgument        ((fsl_nboot_status_t)0x5A5AA5F0u) /*!< Invalid argument passed to the function. */
+#define kStatus_NBOOT_RequestTimeout         ((fsl_nboot_status_t)0x5A5AA5E1u) /*!< Operation timed out. */
+#define kStatus_NBOOT_KeyNotLoaded           ((fsl_nboot_status_t)0x5A5AA5E2u) /*!< The requested key is not loaded. */
+#define kStatus_NBOOT_AuthFail               ((fsl_nboot_status_t)0x5A5AA5E4u) /*!< Authentication failed. */
+#define kStatus_NBOOT_OperationNotAvaialable ((fsl_nboot_status_t)0x5A5AA5E5u) /*!< Operation not available on this HW. */
+#define kStatus_NBOOT_KeyNotAvailable        ((fsl_nboot_status_t)0x5A5AA5E6u) /*!< Key is not avaialble. */
+#define kStatus_NBOOT_IvCounterOverflow      ((fsl_nboot_status_t)0x5A5AA5E7u) /*!< Overflow of IV counter (PRINCE/IPED). */
+#define kStatus_NBOOT_SelftestFail           ((fsl_nboot_status_t)0x5A5AA5E8u) /*!< FIPS self-test failure. */
+#define kStatus_NBOOT_InvalidDataFormat      ((fsl_nboot_status_t)0x5A5AA5E9u) /*!< Invalid data format for example antipole */
+#define kStatus_NBOOT_IskCertUserDataTooBig \
+    ((fsl_nboot_status_t)0x5A5AA5EAu) /*!< Size of User data in ISK certificate is greater than 96 bytes */
+#define kStatus_NBOOT_IskCertSignatureOffsetTooSmall \
+    ((fsl_nboot_status_t)0x5A5AA5EBu) /*!< Signature offset in ISK certificate is smaller than expected */
+#define kStatus_NBOOT_MemcpyFail ((fsl_nboot_status_t)0x5A5A845A) /*!< Unexpected error detected during nboot_memcpy() */
+
+/*! @brief sb3.1 maigc number. */
+#define TAG_SB_V3 (0x33766273U) // "sbv3"
+
+/*!
+ * @brief NBOOT type for the root key revocation
+ *
+ * This type defines the NBOOT root key revocation
+ *
+ */
+#define kNBOOT_RootKey_Enabled (0xAAu)
+#define kNBOOT_RootKey_Revoked (0xBBu)
+
+/*! @brief The size of the root of trust key table hash. */
+#define NBOOT_ROOT_ROTKH_SIZE_IN_WORD (12U)
+#define NBOOT_ROOT_ROTKH_SIZE_IN_BYTE (NBOOT_ROOT_ROTKH_SIZE_IN_WORD * 4U)
+
+/*! @brief The size of PKC Blob. */
+#define NBOOT_PCK_BLOB_SIZE_IN_WORD (12U)
+#define NBOOT_PCK_BLOB_SIZE_IN_BYTE (NBOOT_PCK_BLOB_SIZE_IN_WORD * 4U)
+
+/*!
+ * @brief NBOOT type specifying the elliptic curve to be used
+ *
+ * This type defines the elliptic curve type and length
+ *
+ */
+#define kNBOOT_RootKey_Ecdsa_P256 (0x0000FE01u)
+#define kNBOOT_RootKey_Ecdsa_P384 (0x0000FD02u)
+
+/*!
+ * @brief NBOOT type for the root key usage
+ *
+ * This type defines the NBOOT root key usage
+ *
+ */
+#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA_ImageKey_FwKey (0x0u)
+#define kNBOOT_RootKeyUsage_Unused                              (0x7u)
+
+//! @brief SB loader status codes.
+enum _sbloader_status
+{
+    kStatusRomLdrSectionOverrun  = MAKE_STATUS(kStatusGroup_SBLoader, 0),
+    kStatusRomLdrSignature       = MAKE_STATUS(kStatusGroup_SBLoader, 1),
+    kStatusRomLdrSectionLength   = MAKE_STATUS(kStatusGroup_SBLoader, 2),
+    kStatusRomLdrUnencryptedOnly = MAKE_STATUS(kStatusGroup_SBLoader, 3),
+    kStatusRomLdrEOFReached      = MAKE_STATUS(kStatusGroup_SBLoader, 4),
+    kStatusRomLdrChecksum        = MAKE_STATUS(kStatusGroup_SBLoader, 5),
+    kStatusRomLdrCrc32Error      = MAKE_STATUS(kStatusGroup_SBLoader, 6),
+    kStatusRomLdrUnknownCommand  = MAKE_STATUS(kStatusGroup_SBLoader, 7),
+    kStatusRomLdrIdNotFound      = MAKE_STATUS(kStatusGroup_SBLoader, 8),
+    kStatusRomLdrDataUnderrun    = MAKE_STATUS(kStatusGroup_SBLoader, 9),
+    kStatusRomLdrJumpReturned    = MAKE_STATUS(kStatusGroup_SBLoader, 10),
+    kStatusRomLdrCallFailed      = MAKE_STATUS(kStatusGroup_SBLoader, 11),
+    kStatusRomLdrKeyNotFound     = MAKE_STATUS(kStatusGroup_SBLoader, 12),
+    kStatusRomLdrSecureOnly      = MAKE_STATUS(kStatusGroup_SBLoader, 13),
+    kStatusRomLdrResetReturned   = MAKE_STATUS(kStatusGroup_SBLoader, 14),
+
+    kStatusRomLdrRollbackBlocked        = MAKE_STATUS(kStatusGroup_SBLoader, 15),
+    kStatusRomLdrInvalidSectionMacCount = MAKE_STATUS(kStatusGroup_SBLoader, 16),
+    kStatusRomLdrUnexpectedCommand      = MAKE_STATUS(kStatusGroup_SBLoader, 17),
+    kStatusRomLdrBadSBKEK               = MAKE_STATUS(kStatusGroup_SBLoader, 18),
+    kStatusRomLdrPendingJumpCommand     = MAKE_STATUS(kStatusGroup_SBLoader, 19),
+};
+
+/*!
+ * @brief Boolean type for the NBOOT functions
+ *
+ * This type defines boolean values used by NBOOT functions that are not easily disturbed by Fault Attacks
+ *
+ */
+typedef enum _fsl_nboot_bool
+{
+    kNBOOT_TRUE                = 0x3C5AC33Cu, /*!< Value for TRUE.  */
+    kNBOOT_TRUE256             = 0x3C5AC35Au, /*!< Value for TRUE when P256 was used to sign the image.  */
+    kNBOOT_TRUE384             = 0x3C5AC3A5u, /*!< Value for TRUE when P384 was used to sign the image.  */
+    kNBOOT_FALSE               = 0x5AA55AA5u, /*!< Value for FALSE. */
+    kNBOOT_OperationAllowed    = 0x3c5a33ccU,
+    kNBOOT_OperationDisallowed = 0x5aa5cc33U,
+} fsl_nboot_bool_t;
+
+/** Type for nboot protected status codes */
+typedef uint64_t fsl_nboot_status_protected_t;
+
+/*!
+ * @brief NBOOT type for a timestamp
+ *
+ * This type defines the NBOOT timestamp
+ *
+ */
+typedef uint32_t fsl_nboot_timestamp_t[2];
+typedef uint32_t fsl_nboot_root_key_revocation_t;
+typedef uint32_t fsl_nboot_root_key_usage_t;
+typedef uint32_t fsl_nboot_root_key_type_and_length_t;
+typedef uint32_t fsl_nboot_soc_lifecycle_t;
+
+/*!
+ * @brief NBOOT type for the root of trust parameters
+ *
+ * This type defines the NBOOT root of trust parameters
+ *
+ */
+#define kNBOOT_SocRkh_Size_Words_P384 (12u)
+#define kNBOOT_SocRkh_Size_Words_P256 (8u)
+typedef struct _fsl_nboot_rot_auth_parms
+{
+    /* trusted information originated from CFPA */
+    fsl_nboot_root_key_revocation_t soc_rootKeyRevocation[NBOOT_ROOT_CERT_COUNT]; /*!< Provided by caller based on NVM
+                                                                                 information in CFPA: ROTKH_REVOKE */
+    uint32_t soc_imageKeyRevocation; /*!< Provided by caller based on NVM information in CFPA: IMAGE_KEY_REVOKE */
+
+    /* trusted information originated from CMPA */
+    uint32_t soc_rkh[kNBOOT_SocRkh_Size_Words_P384]; /*!< Provided by caller based on NVM information in CMPA: ROTKH
+                                                        (hash of hashes) */
+    /*!< In case of kNBOOT_RootKey_Ecdsa_P384, sock_rkh[0..11] are used */
+    /*!< In case of kNBOOT_RootKey_Ecdsa_P256, sock_rkh[0..7] are used */
+
+    uint32_t soc_numberOfRootKeys; /* unsigned int, between minimum = 1 and maximum = 4; */
+    fsl_nboot_root_key_usage_t soc_rootKeyUsage[NBOOT_ROOT_CERT_COUNT]; /* CMPA */
+    fsl_nboot_root_key_type_and_length_t
+        soc_rootKeyTypeAndLength; /* static selection between ECDSA P-256 or ECDSA P-384 based root keys */
+
+    /* trusted information originated from OTP fuses */
+    fsl_nboot_soc_lifecycle_t soc_lifecycle;
+} fsl_nboot_rot_auth_parms_t;
+
+/*!
+ * @brief NBOOT SB3.1 header type
+ *
+ * This type defines the header used in the SB3.1 manifest
+ *
+ */
+typedef struct _fsl_nboot_sb3_header
+{
+    uint32_t magic;         /*! offset 0x00: Fixed 4-byte string of 'sbv3' without the trailing NULL */
+    uint32_t formatVersion; /*! offset 0x04: (major = 3, minor = 1); The format version determines the manifest (block0)
+                               size. */
+    uint32_t flags;         /*! offset 0x08: not defined yet, keep zero for future compatibility */
+    uint32_t blockCount;    /*! offset 0x0C: Number of blocks not including the manifest (block0). */
+    uint32_t blockSize; /*! offset 0x10: Size in bytes of data block (repeated blockCount times for SB3 data stream). */
+    fsl_nboot_timestamp_t timeStamp;     /*! offset 0x14: 64-bit value used as key derivation data. */
+    uint32_t firmwareVersion;        /*! offset 0x1c: Version number of the included firmware */
+    uint32_t imageTotalLength;       /*! offset 0x20: Total manifest length in bytes, including signatures etc. */
+    uint32_t imageType;              /*! offset 0x24: image type and flags */
+    uint32_t certificateBlockOffset; /*! offset 0x28: Offset from start of header block to the certificate block. */
+    uint8_t description[16];         /*! offset 0x32: This field provides description of the file. It is an arbitrary
+                                                      string injected by the signing tool, which helps to identify the file. */
+} fsl_nboot_sb3_header_t;
+
+/*!
+ * @brief  manifest loading parameters
+ *
+ * This type defines the NBOOT SB3.1 manifest loading parameters
+ *
+ */
+typedef struct _fsl_nboot_sb3_load_manifest_parms
+{
+    fsl_nboot_rot_auth_parms_t soc_RoTNVM;   /*! trusted information originated from CFPA and NMPA */
+    uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */
+    uint8_t pckBlob[48];                 /*! CSSv2 protected blob with Part Common Key (PCK) */
+} fsl_nboot_sb3_load_manifest_parms_t;
+
+/*! @brief Data structure holding input arguments to POR secure boot (authentication) algorithm. Shall be read from SoC
+ * trusted NVM or SoC fuses. */
+typedef struct _fsl_nboot_img_auth_ecdsa_parms
+{
+    /* trusted information originated from CFPA and NMPA */
+    fsl_nboot_rot_auth_parms_t soc_RoTNVM;
+
+    uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */
+} fsl_nboot_img_auth_ecdsa_parms_t;
+
+/*! @brief The size of the blob with Key Blob. */
+#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_256 (32)
+#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_384 (48)
+#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX (NBOOT_KEY_BLOB_SIZE_IN_BYTE_384)
+
+#define NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES (808)
+#define NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES    (308)
+
+// Provides forward reference to the loader context definition.
+typedef struct _fsl_ldr_Context_v3 fsl_ldr_Context_v3_t;
+
+//! sb3 section definitions
+
+//! section type
+typedef enum _fsl_sectionType
+{
+    kSectionNone       = 0, // end or invalid
+    kSectionDataRange  = 1,
+    kSectionDiffUpdate = 2,
+    kSectionDDRConfig  = 3,
+    kSectionRegister   = 4,
+} fsl_section_type_t;
+
+#define SB3_DATA_RANGE_HEADER_FLAGS_ERASE_MASK (0x1u) // bit 0
+#define SB3_DATA_RANGE_HEADER_FLAGS_LOAD_MASK  (0x2u) // bit 1
+
+#define SB3_DATA_RANGE_HEADER_TAG       (0x55aaaa55U)
+#define SB3_DATA_ALIGNMENT_SIZE_IN_BYTE (16u)
+
+//! section data range structure
+typedef struct fsl_range_header
+{
+    uint32_t tag;
+    uint32_t startAddress;
+    uint32_t length;
+    uint32_t cmd;
+} fsl_sb3_data_range_header_t;
+
+typedef struct fsl_range_header_expansion
+{
+    uint32_t memoryId;
+    uint32_t pad0;
+    uint32_t pad1;
+    uint32_t pad2;
+} fsl_sb3_data_range_expansion_t;
+
+//! sb3 DATA section header format
+typedef struct fsl_section_header
+{
+    uint32_t sectionUid;
+    uint32_t sectionType;
+    uint32_t length;
+    uint32_t _pad;
+} fsl_sb3_section_header_t;
+
+// loader command enum
+
+typedef enum _fsl_loader_command_sb3
+{
+    kSB3_CmdInvalid = 0,
+    kSB3_CmdLoad    = 2,
+    kSB3_CmdExecute = 3,
+} fsl_sb3_cmd_t;
+
+//! The all of the allowed command
+#define SBLOADER_V3_CMD_SET_ALL ((1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute))
+
+#define SB3_DATA_BUFFER_SIZE_IN_BYTE (MAX(128, NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX))
+
+/*! @brief Data structure holding secure counter value used by nboot library */
+typedef struct _fsl_nboot_secure_counter
+{
+    uint32_t sc;
+    uint32_t scAp;
+} fsl_nboot_secure_counter_t;
+
+/*!
+ * @brief NBOOT context type
+ *
+ * This type defines the NBOOT context
+ *
+ */
+typedef struct _fsl_nboot_context
+{
+    uint32_t totalBlocks; /*!< holds number of SB3 blocks. Initialized by nboot_sb3_load_header(). */
+    uint32_t processData; /*!< flag, initialized by nboot_sb3_load_header().
+                             SB3 related flag set by NBOOT in case the nboot_sb3_load_block()
+                             provides plain data to output buffer (for processing by ROM SB3 loader */
+    uint32_t timeout;     /*!< timeout value for css operation. In case it is 0, infinite wait is performed */
+    uint32_t keyinfo[NBOOT_KEYINFO_WORDLEN]; /*!< data for NBOOT key management. */
+    uint32_t context[NBOOT_CONTEXT_WORDLEN]; /*!< work area for NBOOT lib. */
+    uint32_t uuid[4];                        /*!< holds UUID value from NMPA */
+    uint32_t prngReadyFlag;     /*!< flag, used by nboot_rng_generate_lq_random() to determine whether CSS is ready to
+                                   generate rnd number */
+    uint32_t multipartMacBuffer[1024 / sizeof(uint32_t)];
+    uint32_t oemShareValidFlag; /*!< flag, used during TP to determine whether valid oemShare was set by
+                                   nboot_tp_isp_gen_oem_master_share() */
+    uint32_t oemShare[4]; /*!< buffer to store OEM_SHARE computed by nxpCLTrustProv_nboot_isp_gen_oem_master_share() */
+    fsl_nboot_secure_counter_t secureCounter; /*!< Secure counter used by nboot */
+    uint32_t rtf[NXPCLCSS_HASH_RTF_OUTPUT_SIZE / sizeof(uint32_t)];
+    uint32_t imageHash[48 / sizeof(uint32_t)];
+    uint32_t authStatus;
+    fsl_nboot_bool_t disableProvisioningFirmwareNXP; /*!< Flag to disable execution of NXP signed provisioning Firmwares */
+} fsl_nboot_context_t;
+
+//! @brief Structure of version property.
+//!
+//! @ingroup bl_core
+typedef union fsl_StandardVersion
+{
+    struct
+    {
+        uint8_t bugfix; //!< bugfix version [7:0]
+        uint8_t minor;  //!< minor version [15:8]
+        uint8_t major;  //!< major version [23:16]
+        char name;      //!< name [31:24]
+    };
+    uint32_t version;   //!< combined version numbers
+
+#if defined(__cplusplus)
+    StandardVersion() : version(0)
+    {
+    }
+    StandardVersion(uint32_t version) : version(version)
+    {
+    }
+#endif
+} fsl_standard_version_t;
+
+//!@brief Memory region information table
+typedef struct fsl_mem_region
+{
+    uint32_t start;
+    uint32_t end;
+} fsl_mem_region_t;
+
+//! @brief Memory Attribute Structure
+typedef struct _fsl_mem_attribute
+{
+    uint32_t memId;
+    uint32_t regionCount;
+    fsl_mem_region_t *memRegions;
+    void *context;
+} fsl_mem_attribute_t;
+
+typedef struct _fsl_arena_context
+{
+    uint32_t start;
+    uint32_t end;
+    uint32_t nextAddr;
+} fsl_arena_context_t;
+
+//!@brief Memory region interface structure
+typedef struct fsl_api_memory_region_interface
+{
+    status_t (*init)(fsl_mem_attribute_t *attr);
+#if defined(ROM_API_HAS_FEATURE_MEM_READ)
+#if ROM_API_HAS_FEATURE_MEM_READ
+    status_t (*read)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf);
+#endif
+#endif
+
+    status_t (*write)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf);
+    status_t (*fill)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t len, uint32_t pattern);
+    status_t (*flush)(fsl_mem_attribute_t *attr);
+    status_t (*erase)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t len);
+    status_t (*config)(fsl_mem_attribute_t *attr, uint32_t *buf);
+    status_t (*erase_all)(fsl_mem_attribute_t *attr);
+    status_t (*alloc_ctx)(fsl_arena_context_t *ctx, fsl_mem_attribute_t *attr, void *miscParams);
+} fsl_api_memory_region_interface_t;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+//! @brief Contiguous RAM region count
+#define RAM_REGION_COUNT (2U)
+
+//! @brief Contiguous FLEXSPINOR meomry count
+#define FLEXSPINOR_REGION_COUNT (1U)
+
+//! @brief Memory Interface count
+#define MEM_INTERFACE_COUNT (2U)
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _fsl_lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} fsl_flexspi_lut_seq_t;
+
+//!@brief FlexSPI Pad Configuration Override
+typedef struct
+{
+    uint8_t pu_pd_override_en;
+    uint8_t pu_pd_value;
+    uint8_t sr_config_override_en;
+    uint8_t sr_config_value;
+} fsl_flexspi_pad_config_override_t;
+
+typedef struct
+{
+    uint8_t time_100ps;  // Data valid time, in terms of 100ps
+    uint8_t delay_cells; // Data valid time, in terms of delay cells
+} fsl_flexspi_dll_time_t;
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _fsl_FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    fsl_flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    fsl_flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 (unused/not applicable on RW610)
+    uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 (unused/not applicable on RW610)
+    fsl_flexspi_pad_config_override_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    fsl_flexspi_pad_config_override_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    fsl_flexspi_pad_config_override_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    fsl_flexspi_pad_config_override_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;                                 //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;                             //!< [0x074-0x077] CS deselect interval between two commands
+    fsl_flexspi_dll_time_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B
+    uint16_t busyOffset;                 //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    fsl_flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t dll0CrVal;                 //!> [0x1b0-0x1b3] Customizable DLL0CR setting
+    uint32_t dll1CrVal;                 //!> [0x1b4-0x1b7] Customizable DLL1CR setting
+    uint32_t reserved4[2];              //!< [0x1b8-0x1bf] Reserved for future use
+} fsl_flexspi_mem_config_t;
+
+typedef struct fsl_soc_memory_map_struct
+{
+    struct
+    {
+        uint32_t start;
+        uint32_t end;
+    } ramRegions[RAM_REGION_COUNT];
+    struct
+    {
+        uint32_t start;
+        uint32_t end;
+    } flexspiNorRegions[FLEXSPINOR_REGION_COUNT];
+} fsl_soc_mem_regions_t;
+
+//!@brief Memory entry data structure
+typedef struct fsl_memory_map_entry
+{
+    fsl_mem_attribute_t *memoryAttribute;
+    const fsl_api_memory_region_interface_t *memoryInterface;
+} fsl_api_memory_map_entry_t;
+
+//!@brief API initialization data structure
+typedef struct fsl_kb_api_parameter_struct
+{
+    uint32_t allocStart;
+    uint32_t allocSize;
+} fsl_kp_api_init_param_t;
+
+//!@brief Memory context structure
+typedef struct fsl_memory_context_struct
+{
+    status_t (*flush)(fsl_mem_attribute_t *attr);
+    fsl_mem_attribute_t *attr;
+} fsl_mem_context_t;
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _fsl_flexspi_nor_config
+{
+    fsl_flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t isDataOrderSwapped;     //!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2)
+    uint8_t reserved0[1];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t flashStateCtx;         //!< Flash State Context
+    uint32_t reserve2[10];          //!< Reserved for future use
+} fsl_flexspi_nor_config_t;
+
+//!@brief The API context structure
+typedef struct fsl_api_core_context
+{
+    fsl_soc_mem_regions_t memRegions;
+    fsl_arena_context_t arenaCtx;
+    fsl_flexspi_nor_config_t flexspinorCfg;
+    fsl_mem_context_t memCtx;
+    fsl_ldr_Context_v3_t *sbloaderCtx;
+    fsl_nboot_context_t *nbootCtx;
+    uint8_t *sharedBuf;
+    fsl_api_memory_map_entry_t memEntries[MEM_INTERFACE_COUNT];
+} fsl_api_core_context_t;
+
+//!@brief IAP API Interface structure
+typedef struct fsl_iap_api_interface_struct
+{
+    fsl_standard_version_t version; //!< IAP API version number.
+    status_t (*api_init)(fsl_api_core_context_t *coreCtx, const fsl_kp_api_init_param_t *param);
+    status_t (*api_deinit)(fsl_api_core_context_t *coreCtx);
+    status_t (*mem_init)(fsl_api_core_context_t *ctx);
+    status_t (*mem_read)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, uint8_t *buf, uint32_t memoryId);
+    status_t (*mem_write)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, const uint8_t *buf, uint32_t memoryId);
+    status_t (*mem_fill)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t pattern, uint32_t memoryId);
+    status_t (*mem_flush)(fsl_api_core_context_t *ctx);
+    status_t (*mem_erase)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t memoryId);
+    status_t (*mem_config)(fsl_api_core_context_t *ctx, uint32_t *buf, uint32_t memoryId);
+    status_t (*mem_erase_all)(fsl_api_core_context_t *ctx, uint32_t memoryId);
+    status_t (*fsl_sbloader_init)(fsl_api_core_context_t *ctx);
+    status_t (*fsl_sbloader_pump)(fsl_api_core_context_t *ctx, uint8_t *data, uint32_t length);
+    status_t (*fsl_sbloader_finalize)(fsl_api_core_context_t *ctx);
+} fsl_iap_api_interface_t;
+
+//! Function pointer definition for all loader action functions.
+// typedef status_t (*fsl_pLdrFnc_v3_t)(ldr_Context_v3_t *);
+typedef status_t (*fsl_pLdrFnc_v3_t)(fsl_api_core_context_t *n);
+
+//! Loader context definition.
+struct _fsl_ldr_Context_v3
+{
+    fsl_pLdrFnc_v3_t Action;        //!< pointer to loader action function
+    uint32_t block_size;        //!< size of each block in bytes
+    uint32_t block_data_size;   //!< data size in bytes (NBOOT_SB3_CHUNK_SIZE_IN_BYTES)
+    uint32_t block_data_total;  //!< data max size in bytes (block_size * data_size
+    uint32_t block_buffer_size; //!< block0 and block size
+    uint32_t block_buffer_position;
+    uint8_t block_buffer[MAX(NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES,
+                             NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES)]; //! will be used for both block0 and blockx
+    uint32_t processedBlocks;
+
+    uint8_t data_block_offset; //! data block offset in a block.
+    bool in_data_block;        //!< in progress of handling a data block within a block
+    uint8_t *data_block;
+    uint32_t data_block_position;
+
+    bool in_data_section; //!< in progress of handling a data section within a data block
+    uint32_t data_section_handled;
+    fsl_sb3_section_header_t data_section_header;
+
+    bool in_data_range; //!< in progress of handling a data range within a data section
+    uint32_t data_range_handled;
+    uint32_t data_range_gap;
+    fsl_sb3_data_range_header_t data_range_header;
+    bool has_data_range_expansion;
+    fsl_sb3_data_range_expansion_t data_range_expansion;
+
+    uint32_t commandSet; //!< support command set during sb file handling
+
+    uint32_t data_position;
+    uint8_t data_buffer[SB3_DATA_BUFFER_SIZE_IN_BYTE]; //!< temporary data buffer
+
+    uint32_t fuse_cmd_position;
+    uint8_t fuse_cmd_buffer[32 * 4]; //!< used for fuse command
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+#define BIT0 (1UL << 0U)
+
+void power_on_device_impl(LOAD_Target_Type loadTarget);
+void power_off_device_impl(LOAD_Target_Type loadTarget);
+void reset_device(LOAD_Target_Type loadTarget);
+status_t load_service(LOAD_Target_Type loadTarget, uint32_t sourceAddr);
+status_t sb3_fw_download_impl(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+status_t sb3_fw_reset_impl(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+fsl_nboot_status_t nboot_hal_get_sb3_manifest_params(fsl_nboot_context_t *context, fsl_nboot_sb3_load_manifest_parms_t *parms);
+status_t loader_process_sb_file(uint32_t readOffset);
+status_t fsl_sbloader_init(fsl_api_core_context_t *ctx);
+status_t fsl_sbloader_finalize(fsl_api_core_context_t *ctx);
+uint8_t get_chip_revision(void);
+
+//! @}
+
+#endif /* __FSL_LOADER_UTILS_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fusemap.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fusemap.h
new file mode 100644
index 0000000000..4da982437e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fusemap.h
@@ -0,0 +1,2586 @@
+
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef __FUSEMAP_H__
+#define __FUSEMAP_H__
+
+#include "fsl_device_registers.h"
+
+/* Fuse Word LOCK_CFG0 Index 0 */
+#define OTP_LOCK_CFG0_FUSE_IDX (0u)
+
+#define OTP_LOCK_CFG0_FUSE_VALUE()   (OCOTP->OTP_SHADOW[OTP_LOCK_CFG0_FUSE_IDX])
+#define OTP_BOOT_CFG_LOCK_FUSE_IDX   (0u)
+#define OTP_BOOT_CFG_LOCK_FUSE_SHIFT (0u)
+#define OTP_BOOT_CFG_LOCK_FUSE_MASK  (0x7u)
+#define OTP_BOOT_CFG_LOCK_FUSE_WIDTH (3u)
+#define OTP_BOOT_CFG_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_BOOT_CFG_LOCK_FUSE_IDX] & OTP_BOOT_CFG_LOCK_FUSE_MASK) >> OTP_BOOT_CFG_LOCK_FUSE_SHIFT)
+
+#define OTP_SEC_BOOT_CFG_LOCK_FUSE_IDX   (0u)
+#define OTP_SEC_BOOT_CFG_LOCK_FUSE_SHIFT (3u)
+#define OTP_SEC_BOOT_CFG_LOCK_FUSE_MASK  (0x38u)
+#define OTP_SEC_BOOT_CFG_LOCK_FUSE_WIDTH (3u)
+#define OTP_SEC_BOOT_CFG_LOCK_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG_LOCK_FUSE_IDX] & OTP_SEC_BOOT_CFG_LOCK_FUSE_MASK) >> \
+     OTP_SEC_BOOT_CFG_LOCK_FUSE_SHIFT)
+
+#define OTP_DCFG_CC_SOCU_LOCK_FUSE_IDX   (0u)
+#define OTP_DCFG_CC_SOCU_LOCK_FUSE_SHIFT (6u)
+#define OTP_DCFG_CC_SOCU_LOCK_FUSE_MASK  (0x1C0u)
+#define OTP_DCFG_CC_SOCU_LOCK_FUSE_WIDTH (3u)
+#define OTP_DCFG_CC_SOCU_LOCK_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DCFG_CC_SOCU_LOCK_FUSE_IDX] & OTP_DCFG_CC_SOCU_LOCK_FUSE_MASK) >> \
+     OTP_DCFG_CC_SOCU_LOCK_FUSE_SHIFT)
+
+#define OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_IDX   (0u)
+#define OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_SHIFT (9u)
+#define OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_MASK  (0xE00u)
+#define OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_WIDTH (3u)
+#define OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_IDX] & OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_MASK) >> \
+     OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_SHIFT)
+
+#define OTP_LOCK_CFG_LOCK_FUSE_IDX   (0u)
+#define OTP_LOCK_CFG_LOCK_FUSE_SHIFT (12u)
+#define OTP_LOCK_CFG_LOCK_FUSE_MASK  (0x7000u)
+#define OTP_LOCK_CFG_LOCK_FUSE_WIDTH (3u)
+#define OTP_LOCK_CFG_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_LOCK_CFG_LOCK_FUSE_IDX] & OTP_LOCK_CFG_LOCK_FUSE_MASK) >> OTP_LOCK_CFG_LOCK_FUSE_SHIFT)
+
+/* Fuse Word LOCK_CFG1 Index 1 */
+#define OTP_LOCK_CFG1_FUSE_IDX (1u)
+
+#define OTP_LOCK_CFG1_FUSE_VALUE()   (OCOTP->OTP_SHADOW[OTP_LOCK_CFG1_FUSE_IDX])
+#define OTP_CUST_KEY_LOCK_FUSE_IDX   (1u)
+#define OTP_CUST_KEY_LOCK_FUSE_SHIFT (0u)
+#define OTP_CUST_KEY_LOCK_FUSE_MASK  (0x7u)
+#define OTP_CUST_KEY_LOCK_FUSE_WIDTH (3u)
+#define OTP_CUST_KEY_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_CUST_KEY_LOCK_FUSE_IDX] & OTP_CUST_KEY_LOCK_FUSE_MASK) >> OTP_CUST_KEY_LOCK_FUSE_SHIFT)
+
+#define OTP_PRINCE_CFG_FUSE_IDX   (1u)
+#define OTP_PRINCE_CFG_FUSE_SHIFT (3u)
+#define OTP_PRINCE_CFG_FUSE_MASK  (0x38u)
+#define OTP_PRINCE_CFG_FUSE_WIDTH (3u)
+#define OTP_PRINCE_CFG_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PRINCE_CFG_FUSE_IDX] & OTP_PRINCE_CFG_FUSE_MASK) >> OTP_PRINCE_CFG_FUSE_SHIFT)
+
+#define OTP_KEYSTORE_CFG_LOCK_FUSE_IDX   (1u)
+#define OTP_KEYSTORE_CFG_LOCK_FUSE_SHIFT (6u)
+#define OTP_KEYSTORE_CFG_LOCK_FUSE_MASK  (0x1C0u)
+#define OTP_KEYSTORE_CFG_LOCK_FUSE_WIDTH (3u)
+#define OTP_KEYSTORE_CFG_LOCK_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_KEYSTORE_CFG_LOCK_FUSE_IDX] & OTP_KEYSTORE_CFG_LOCK_FUSE_MASK) >> \
+     OTP_KEYSTORE_CFG_LOCK_FUSE_SHIFT)
+
+#define OTP_LIFECYCLE_LOCK_FUSE_IDX   (1u)
+#define OTP_LIFECYCLE_LOCK_FUSE_SHIFT (9u)
+#define OTP_LIFECYCLE_LOCK_FUSE_MASK  (0xE00u)
+#define OTP_LIFECYCLE_LOCK_FUSE_WIDTH (3u)
+#define OTP_LIFECYCLE_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_LIFECYCLE_LOCK_FUSE_IDX] & OTP_LIFECYCLE_LOCK_FUSE_MASK) >> OTP_LIFECYCLE_LOCK_FUSE_SHIFT)
+
+#define OTP_CRC_HI_LOCK_FUSE_IDX   (1u)
+#define OTP_CRC_HI_LOCK_FUSE_SHIFT (12u)
+#define OTP_CRC_HI_LOCK_FUSE_MASK  (0x7000u)
+#define OTP_CRC_HI_LOCK_FUSE_WIDTH (3u)
+#define OTP_CRC_HI_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_CRC_HI_LOCK_FUSE_IDX] & OTP_CRC_HI_LOCK_FUSE_MASK) >> OTP_CRC_HI_LOCK_FUSE_SHIFT)
+
+/* Fuse Word LOCK_CFG2 Index 2 */
+#define OTP_LOCK_CFG2_FUSE_IDX (2u)
+
+#define OTP_LOCK_CFG2_FUSE_VALUE()    (OCOTP->OTP_SHADOW[OTP_LOCK_CFG2_FUSE_IDX])
+#define OTP_OTP_SHARE_LOCK_FUSE_IDX   (2u)
+#define OTP_OTP_SHARE_LOCK_FUSE_SHIFT (0u)
+#define OTP_OTP_SHARE_LOCK_FUSE_MASK  (0x7u)
+#define OTP_OTP_SHARE_LOCK_FUSE_WIDTH (3u)
+#define OTP_OTP_SHARE_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_OTP_SHARE_LOCK_FUSE_IDX] & OTP_OTP_SHARE_LOCK_FUSE_MASK) >> OTP_OTP_SHARE_LOCK_FUSE_SHIFT)
+
+#define OTP_ROM_PATCH_LOCK_FUSE_IDX   (2u)
+#define OTP_ROM_PATCH_LOCK_FUSE_SHIFT (3u)
+#define OTP_ROM_PATCH_LOCK_FUSE_MASK  (0x38u)
+#define OTP_ROM_PATCH_LOCK_FUSE_WIDTH (3u)
+#define OTP_ROM_PATCH_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ROM_PATCH_LOCK_FUSE_IDX] & OTP_ROM_PATCH_LOCK_FUSE_MASK) >> OTP_ROM_PATCH_LOCK_FUSE_SHIFT)
+
+#define OTP_NXP_KEY_LOCK_FUSE_IDX   (2u)
+#define OTP_NXP_KEY_LOCK_FUSE_SHIFT (6u)
+#define OTP_NXP_KEY_LOCK_FUSE_MASK  (0x1C0u)
+#define OTP_NXP_KEY_LOCK_FUSE_WIDTH (3u)
+#define OTP_NXP_KEY_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_NXP_KEY_LOCK_FUSE_IDX] & OTP_NXP_KEY_LOCK_FUSE_MASK) >> OTP_NXP_KEY_LOCK_FUSE_SHIFT)
+
+#define OTP_CRC_LO_LOCK_FUSE_IDX   (2u)
+#define OTP_CRC_LO_LOCK_FUSE_SHIFT (9u)
+#define OTP_CRC_LO_LOCK_FUSE_MASK  (0xE00u)
+#define OTP_CRC_LO_LOCK_FUSE_WIDTH (3u)
+#define OTP_CRC_LO_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_CRC_LO_LOCK_FUSE_IDX] & OTP_CRC_LO_LOCK_FUSE_MASK) >> OTP_CRC_LO_LOCK_FUSE_SHIFT)
+
+#define OTP_COMMON_LOCK_FUSE_IDX   (2u)
+#define OTP_COMMON_LOCK_FUSE_SHIFT (12u)
+#define OTP_COMMON_LOCK_FUSE_MASK  (0x7000u)
+#define OTP_COMMON_LOCK_FUSE_WIDTH (3u)
+#define OTP_COMMON_LOCK_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_COMMON_LOCK_FUSE_IDX] & OTP_COMMON_LOCK_FUSE_MASK) >> OTP_COMMON_LOCK_FUSE_SHIFT)
+
+/* Fuse Word TRIM_CFG0 Index 3 */
+#define OTP_TRIM_CFG0_FUSE_IDX (3u)
+
+#define OTP_TSENS_CAU_MIN_FUSE_IDX   (3u)
+#define OTP_TSENS_CAU_MIN_FUSE_SHIFT (0u)
+#define OTP_TSENS_CAU_MIN_FUSE_MASK  (0x3FFu)
+#define OTP_TSENS_CAU_MIN_FUSE_WIDTH (10u)
+
+#define OTP_TSENS_CAU_MAX_FUSE_IDX   (3u)
+#define OTP_TSENS_CAU_MAX_FUSE_SHIFT (10u)
+#define OTP_TSENS_CAU_MAX_FUSE_MASK  (0xFFC00u)
+#define OTP_TSENS_CAU_MAX_FUSE_WIDTH (10u)
+
+#define OTP_V11_SENS_MIN_FUSE_IDX   (3u)
+#define OTP_V11_SENS_MIN_FUSE_SHIFT (20u)
+#define OTP_V11_SENS_MIN_FUSE_MASK  (0x3FF00000u)
+#define OTP_V11_SENS_MIN_FUSE_WIDTH (10u)
+
+/* Fuse Word TRIM_CFG1 Index 4 */
+#define OTP_TRIM_CFG1_FUSE_IDX (4u)
+
+#define OTP_V11_SENS_MAX_FUSE_IDX   (4u)
+#define OTP_V11_SENS_MAX_FUSE_SHIFT (0u)
+#define OTP_V11_SENS_MAX_FUSE_MASK  (0x3FFu)
+#define OTP_V11_SENS_MAX_FUSE_WIDTH (10u)
+
+#define OTP_V18_SENS_MIN_FUSE_IDX   (4u)
+#define OTP_V18_SENS_MIN_FUSE_SHIFT (10u)
+#define OTP_V18_SENS_MIN_FUSE_MASK  (0xFFC00u)
+#define OTP_V18_SENS_MIN_FUSE_WIDTH (10u)
+
+#define OTP_V18_SENS_MAX_FUSE_IDX   (4u)
+#define OTP_V18_SENS_MAX_FUSE_SHIFT (20u)
+#define OTP_V18_SENS_MAX_FUSE_MASK  (0x3FF00000u)
+#define OTP_V18_SENS_MAX_FUSE_WIDTH (10u)
+
+/* Fuse Word CFG_STATE Index 5 */
+#define OTP_CFG_STATE_FUSE_IDX (5u)
+
+#define OTP_GDET_VALID_FUSE_IDX   (5u)
+#define OTP_GDET_VALID_FUSE_SHIFT (0u)
+#define OTP_GDET_VALID_FUSE_MASK  (0x1u)
+#define OTP_GDET_VALID_FUSE_WIDTH (1u)
+
+#define OTP_GDET_RESET_DIS_FUSE_IDX   (5u)
+#define OTP_GDET_RESET_DIS_FUSE_SHIFT (1u)
+#define OTP_GDET_RESET_DIS_FUSE_MASK  (0xEu)
+#define OTP_GDET_RESET_DIS_FUSE_WIDTH (3u)
+
+#define OTP_DTRNG_VALID_FUSE_IDX   (5u)
+#define OTP_DTRNG_VALID_FUSE_SHIFT (4u)
+#define OTP_DTRNG_VALID_FUSE_MASK  (0x10u)
+#define OTP_DTRNG_VALID_FUSE_WIDTH (1u)
+
+#define OTP_DIS_ROM_HIDING_FUSE_IDX   (5u)
+#define OTP_DIS_ROM_HIDING_FUSE_SHIFT (5u)
+#define OTP_DIS_ROM_HIDING_FUSE_MASK  (0x1E0u)
+#define OTP_DIS_ROM_HIDING_FUSE_WIDTH (4u)
+
+#define OTP_TSENS_CAU_VALID_FUSE_IDX   (5u)
+#define OTP_TSENS_CAU_VALID_FUSE_SHIFT (9u)
+#define OTP_TSENS_CAU_VALID_FUSE_MASK  (0x200u)
+#define OTP_TSENS_CAU_VALID_FUSE_WIDTH (1u)
+
+#define OTP_V11_SENS_VALID_FUSE_IDX   (5u)
+#define OTP_V11_SENS_VALID_FUSE_SHIFT (10u)
+#define OTP_V11_SENS_VALID_FUSE_MASK  (0x400u)
+#define OTP_V11_SENS_VALID_FUSE_WIDTH (1u)
+
+#define OTP_V18_SENS_VALID_FUSE_IDX   (5u)
+#define OTP_V18_SENS_VALID_FUSE_SHIFT (11u)
+#define OTP_V18_SENS_VALID_FUSE_MASK  (0x800u)
+#define OTP_V18_SENS_VALID_FUSE_WIDTH (1u)
+
+#define OTP_RCAL_VALUE_FUSE_IDX   (5u)
+#define OTP_RCAL_VALUE_FUSE_SHIFT (12u)
+#define OTP_RCAL_VALUE_FUSE_MASK  (0x7F000u)
+#define OTP_RCAL_VALUE_FUSE_WIDTH (7u)
+
+#define OTP_RCAL_VALID_FUSE_IDX   (5u)
+#define OTP_RCAL_VALID_FUSE_SHIFT (19u)
+#define OTP_RCAL_VALID_FUSE_MASK  (0x80000u)
+#define OTP_RCAL_VALID_FUSE_WIDTH (1u)
+
+#define OTP_DISABLE_15_4_FUSE_IDX   (5u)
+#define OTP_DISABLE_15_4_FUSE_SHIFT (20u)
+#define OTP_DISABLE_15_4_FUSE_MASK  (0x100000u)
+#define OTP_DISABLE_15_4_FUSE_WIDTH (1u)
+
+/* Fuse Word ITRC_CHIP_RESET_SEL0 Index 6 */
+#define OTP_ITRC_CHIP_RESET_SEL0_FUSE_IDX (6u)
+
+/* Fuse Word ITRC_CHIP_RESET_SEL1 Index 7 */
+#define OTP_ITRC_CHIP_RESET_SEL1_FUSE_IDX (7u)
+
+/* Fuse Word SYSCTL0_PRODUCT_ID Index 9 */
+#define OTP_SYSCTL0_PRODUCT_ID_FUSE_IDX (9u)
+
+#define OTP_SYSCTL0_PRODUCT_ID_FUSE_IDX   (9u)
+#define OTP_SYSCTL0_PRODUCT_ID_FUSE_SHIFT (0u)
+#define OTP_SYSCTL0_PRODUCT_ID_FUSE_MASK  (0xFFFFu)
+#define OTP_SYSCTL0_PRODUCT_ID_FUSE_WIDTH (16u)
+
+/* Fuse Word SYSOSC_ST Index 10 */
+#define OTP_SYSOSC_ST_FUSE_IDX (10u)
+
+#define OTP_SYSOSC_ST_31_0_FUSE_IDX   (10u)
+#define OTP_SYSOSC_ST_31_0_FUSE_SHIFT (0u)
+#define OTP_SYSOSC_ST_31_0_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_SYSOSC_ST_31_0_FUSE_WIDTH (32u)
+
+/* Fuse Word SYSCTL0_AUTOCLKGATEOVERRIDE0 Index 11 */
+#define OTP_SYSCTL0_AUTOCLKGATEOVERRIDE0_FUSE_IDX (11u)
+
+/* Fuse Word SYSCTL0_AUTOCLKGATEOVERRIDE1 Index 12 */
+#define OTP_SYSCTL0_AUTOCLKGATEOVERRIDE1_FUSE_IDX (12u)
+
+#define OTP_SYSCTL0_AUTOCLKGATEOVERRIDE1_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_SYSCTL0_AUTOCLKGATEOVERRIDE1_FUSE_IDX])
+/* Fuse Word BOOT_CFG0 Index 15 */
+#define OTP_BOOT_CFG0_FUSE_IDX (15u)
+
+#define OTP_BOOT_CFG0_FUSE_VALUE()         (OCOTP->OTP_SHADOW[OTP_BOOT_CFG0_FUSE_IDX])
+#define OTP_PRIMARY_BOOT_SOURCE_FUSE_IDX   (15u)
+#define OTP_PRIMARY_BOOT_SOURCE_FUSE_SHIFT (0u)
+#define OTP_PRIMARY_BOOT_SOURCE_FUSE_MASK  (0xFu)
+#define OTP_PRIMARY_BOOT_SOURCE_FUSE_WIDTH (4u)
+#define OTP_PRIMARY_BOOT_SOURCE_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PRIMARY_BOOT_SOURCE_FUSE_IDX] & OTP_PRIMARY_BOOT_SOURCE_FUSE_MASK) >> \
+     OTP_PRIMARY_BOOT_SOURCE_FUSE_SHIFT)
+
+#define OTP_DEFAULT_ISP_MODE_FUSE_IDX   (15u)
+#define OTP_DEFAULT_ISP_MODE_FUSE_SHIFT (4u)
+#define OTP_DEFAULT_ISP_MODE_FUSE_MASK  (0x70u)
+#define OTP_DEFAULT_ISP_MODE_FUSE_WIDTH (3u)
+#define OTP_DEFAULT_ISP_MODE_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_DEFAULT_ISP_MODE_FUSE_IDX] & OTP_DEFAULT_ISP_MODE_FUSE_MASK) >> \
+     OTP_DEFAULT_ISP_MODE_FUSE_SHIFT)
+
+#define OTP_BOOT_CLK_SPEED_FUSE_IDX   (15u)
+#define OTP_BOOT_CLK_SPEED_FUSE_SHIFT (7u)
+#define OTP_BOOT_CLK_SPEED_FUSE_MASK  (0x80u)
+#define OTP_BOOT_CLK_SPEED_FUSE_WIDTH (1u)
+#define OTP_BOOT_CLK_SPEED_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_BOOT_CLK_SPEED_FUSE_IDX] & OTP_BOOT_CLK_SPEED_FUSE_MASK) >> OTP_BOOT_CLK_SPEED_FUSE_SHIFT)
+
+#define OTP_STOP_ON_FAILURE_FUSE_IDX   (15u)
+#define OTP_STOP_ON_FAILURE_FUSE_SHIFT (10u)
+#define OTP_STOP_ON_FAILURE_FUSE_MASK  (0x400u)
+#define OTP_STOP_ON_FAILURE_FUSE_WIDTH (1u)
+#define OTP_STOP_ON_FAILURE_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_STOP_ON_FAILURE_FUSE_IDX] & OTP_STOP_ON_FAILURE_FUSE_MASK) >> \
+     OTP_STOP_ON_FAILURE_FUSE_SHIFT)
+
+#define OTP_22_PRINCE_GCM_ROUNDS_FUSE_IDX   (15u)
+#define OTP_22_PRINCE_GCM_ROUNDS_FUSE_SHIFT (11u)
+#define OTP_22_PRINCE_GCM_ROUNDS_FUSE_MASK  (0x800u)
+#define OTP_22_PRINCE_GCM_ROUNDS_FUSE_WIDTH (1u)
+#define OTP_22_PRINCE_GCM_ROUNDS_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_22_PRINCE_GCM_ROUNDS_FUSE_IDX] & OTP_22_PRINCE_GCM_ROUNDS_FUSE_MASK) >> \
+     OTP_22_PRINCE_GCM_ROUNDS_FUSE_SHIFT)
+
+#define OTP_TZM_IMAGE_TYPE_FUSE_IDX   (15u)
+#define OTP_TZM_IMAGE_TYPE_FUSE_SHIFT (12u)
+#define OTP_TZM_IMAGE_TYPE_FUSE_MASK  (0x3000u)
+#define OTP_TZM_IMAGE_TYPE_FUSE_WIDTH (2u)
+#define OTP_TZM_IMAGE_TYPE_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_TZM_IMAGE_TYPE_FUSE_IDX] & OTP_TZM_IMAGE_TYPE_FUSE_MASK) >> OTP_TZM_IMAGE_TYPE_FUSE_SHIFT)
+
+#define OTP_PSA_BSTATE_SKIP_FUSE_IDX   (15u)
+#define OTP_PSA_BSTATE_SKIP_FUSE_SHIFT (14u)
+#define OTP_PSA_BSTATE_SKIP_FUSE_MASK  (0x4000u)
+#define OTP_PSA_BSTATE_SKIP_FUSE_WIDTH (1u)
+#define OTP_PSA_BSTATE_SKIP_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PSA_BSTATE_SKIP_FUSE_IDX] & OTP_PSA_BSTATE_SKIP_FUSE_MASK) >> \
+     OTP_PSA_BSTATE_SKIP_FUSE_SHIFT)
+
+#define OTP_PSA_BSTATE_INC_KEYS_FUSE_IDX   (15u)
+#define OTP_PSA_BSTATE_INC_KEYS_FUSE_SHIFT (15u)
+#define OTP_PSA_BSTATE_INC_KEYS_FUSE_MASK  (0x8000u)
+#define OTP_PSA_BSTATE_INC_KEYS_FUSE_WIDTH (1u)
+#define OTP_PSA_BSTATE_INC_KEYS_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PSA_BSTATE_INC_KEYS_FUSE_IDX] & OTP_PSA_BSTATE_INC_KEYS_FUSE_MASK) >> \
+     OTP_PSA_BSTATE_INC_KEYS_FUSE_SHIFT)
+
+#define OTP_REDUNDANT_SPI_PORT_FUSE_IDX   (15u)
+#define OTP_REDUNDANT_SPI_PORT_FUSE_SHIFT (16u)
+#define OTP_REDUNDANT_SPI_PORT_FUSE_MASK  (0x70000u)
+#define OTP_REDUNDANT_SPI_PORT_FUSE_WIDTH (3u)
+#define OTP_REDUNDANT_SPI_PORT_FUSE_VALUE()                                                     \
+    ((OCOTP->OTP_SHADOW[OTP_REDUNDANT_SPI_PORT_FUSE_IDX] & OTP_REDUNDANT_SPI_PORT_FUSE_MASK) >> \
+     OTP_REDUNDANT_SPI_PORT_FUSE_SHIFT)
+
+#define OTP_SECURE_BOOT_EN_FUSE_IDX   (15u)
+#define OTP_SECURE_BOOT_EN_FUSE_SHIFT (19u)
+#define OTP_SECURE_BOOT_EN_FUSE_MASK  (0x180000u)
+#define OTP_SECURE_BOOT_EN_FUSE_WIDTH (2u)
+#define OTP_SECURE_BOOT_EN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_SECURE_BOOT_EN_FUSE_IDX] & OTP_SECURE_BOOT_EN_FUSE_MASK) >> OTP_SECURE_BOOT_EN_FUSE_SHIFT)
+
+#define OTP_DICE_INC_OTP_FUSE_IDX   (15u)
+#define OTP_DICE_INC_OTP_FUSE_SHIFT (22u)
+#define OTP_DICE_INC_OTP_FUSE_MASK  (0x400000u)
+#define OTP_DICE_INC_OTP_FUSE_WIDTH (1u)
+#define OTP_DICE_INC_OTP_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DICE_INC_OTP_FUSE_IDX] & OTP_DICE_INC_OTP_FUSE_MASK) >> OTP_DICE_INC_OTP_FUSE_SHIFT)
+
+#define OTP_DICE_SKIP_FUSE_IDX   (15u)
+#define OTP_DICE_SKIP_FUSE_SHIFT (23u)
+#define OTP_DICE_SKIP_FUSE_MASK  (0x800000u)
+#define OTP_DICE_SKIP_FUSE_WIDTH (1u)
+#define OTP_DICE_SKIP_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DICE_SKIP_FUSE_IDX] & OTP_DICE_SKIP_FUSE_MASK) >> OTP_DICE_SKIP_FUSE_SHIFT)
+
+#define OTP_BOOT_FAIL_PORT_FUSE_IDX   (15u)
+#define OTP_BOOT_FAIL_PORT_FUSE_SHIFT (24u)
+#define OTP_BOOT_FAIL_PORT_FUSE_MASK  (0x7000000u)
+#define OTP_BOOT_FAIL_PORT_FUSE_WIDTH (3u)
+#define OTP_BOOT_FAIL_PORT_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_BOOT_FAIL_PORT_FUSE_IDX] & OTP_BOOT_FAIL_PORT_FUSE_MASK) >> OTP_BOOT_FAIL_PORT_FUSE_SHIFT)
+
+#define OTP_BOOT_FAIL_PIN_FUSE_IDX   (15u)
+#define OTP_BOOT_FAIL_PIN_FUSE_SHIFT (27u)
+#define OTP_BOOT_FAIL_PIN_FUSE_MASK  (0xF8000000u)
+#define OTP_BOOT_FAIL_PIN_FUSE_WIDTH (5u)
+#define OTP_BOOT_FAIL_PIN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_BOOT_FAIL_PIN_FUSE_IDX] & OTP_BOOT_FAIL_PIN_FUSE_MASK) >> OTP_BOOT_FAIL_PIN_FUSE_SHIFT)
+
+/* Fuse Word BOOT_CFG1 Index 16 */
+#define OTP_BOOT_CFG1_FUSE_IDX (16u)
+
+#define OTP_BOOT_CFG1_FUSE_VALUE()        (OCOTP->OTP_SHADOW[OTP_BOOT_CFG1_FUSE_IDX])
+#define OTP_QSPI_AUTO_PROBE_EN_FUSE_IDX   (16u)
+#define OTP_QSPI_AUTO_PROBE_EN_FUSE_SHIFT (0u)
+#define OTP_QSPI_AUTO_PROBE_EN_FUSE_MASK  (0x1u)
+#define OTP_QSPI_AUTO_PROBE_EN_FUSE_WIDTH (1u)
+#define OTP_QSPI_AUTO_PROBE_EN_FUSE_VALUE()                                                     \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_AUTO_PROBE_EN_FUSE_IDX] & OTP_QSPI_AUTO_PROBE_EN_FUSE_MASK) >> \
+     OTP_QSPI_AUTO_PROBE_EN_FUSE_SHIFT)
+
+#define OTP_QSPI_PROBE_TYPE_FUSE_IDX   (16u)
+#define OTP_QSPI_PROBE_TYPE_FUSE_SHIFT (1u)
+#define OTP_QSPI_PROBE_TYPE_FUSE_MASK  (0xEu)
+#define OTP_QSPI_PROBE_TYPE_FUSE_WIDTH (3u)
+#define OTP_QSPI_PROBE_TYPE_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_PROBE_TYPE_FUSE_IDX] & OTP_QSPI_PROBE_TYPE_FUSE_MASK) >> \
+     OTP_QSPI_PROBE_TYPE_FUSE_SHIFT)
+
+#define OTP_QSPI_FLASH_TYPE_FUSE_IDX   (16u)
+#define OTP_QSPI_FLASH_TYPE_FUSE_SHIFT (4u)
+#define OTP_QSPI_FLASH_TYPE_FUSE_MASK  (0x70u)
+#define OTP_QSPI_FLASH_TYPE_FUSE_WIDTH (3u)
+#define OTP_QSPI_FLASH_TYPE_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_FLASH_TYPE_FUSE_IDX] & OTP_QSPI_FLASH_TYPE_FUSE_MASK) >> \
+     OTP_QSPI_FLASH_TYPE_FUSE_SHIFT)
+
+#define OTP_QSPI_DUMMY_CYCLES_FUSE_IDX   (16u)
+#define OTP_QSPI_DUMMY_CYCLES_FUSE_SHIFT (7u)
+#define OTP_QSPI_DUMMY_CYCLES_FUSE_MASK  (0x780u)
+#define OTP_QSPI_DUMMY_CYCLES_FUSE_WIDTH (4u)
+#define OTP_QSPI_DUMMY_CYCLES_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_DUMMY_CYCLES_FUSE_IDX] & OTP_QSPI_DUMMY_CYCLES_FUSE_MASK) >> \
+     OTP_QSPI_DUMMY_CYCLES_FUSE_SHIFT)
+
+#define OTP_QSPI_FREQUENCY_FUSE_IDX   (16u)
+#define OTP_QSPI_FREQUENCY_FUSE_SHIFT (11u)
+#define OTP_QSPI_FREQUENCY_FUSE_MASK  (0x3800u)
+#define OTP_QSPI_FREQUENCY_FUSE_WIDTH (3u)
+#define OTP_QSPI_FREQUENCY_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_FREQUENCY_FUSE_IDX] & OTP_QSPI_FREQUENCY_FUSE_MASK) >> OTP_QSPI_FREQUENCY_FUSE_SHIFT)
+
+#define OTP_QSPI_RESET_PIN_ENABLE_FUSE_IDX   (16u)
+#define OTP_QSPI_RESET_PIN_ENABLE_FUSE_SHIFT (14u)
+#define OTP_QSPI_RESET_PIN_ENABLE_FUSE_MASK  (0x4000u)
+#define OTP_QSPI_RESET_PIN_ENABLE_FUSE_WIDTH (1u)
+#define OTP_QSPI_RESET_PIN_ENABLE_FUSE_VALUE()                                                        \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_RESET_PIN_ENABLE_FUSE_IDX] & OTP_QSPI_RESET_PIN_ENABLE_FUSE_MASK) >> \
+     OTP_QSPI_RESET_PIN_ENABLE_FUSE_SHIFT)
+
+#define OTP_QSPI_RESET_PIN_FUSE_IDX   (16u)
+#define OTP_QSPI_RESET_PIN_FUSE_SHIFT (15u)
+#define OTP_QSPI_RESET_PIN_FUSE_MASK  (0x7F8000u)
+#define OTP_QSPI_RESET_PIN_FUSE_WIDTH (8u)
+#define OTP_QSPI_RESET_PIN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_RESET_PIN_FUSE_IDX] & OTP_QSPI_RESET_PIN_FUSE_MASK) >> OTP_QSPI_RESET_PIN_FUSE_SHIFT)
+
+#define OTP_QSPI_HOLD_TIME_FUSE_IDX   (16u)
+#define OTP_QSPI_HOLD_TIME_FUSE_SHIFT (23u)
+#define OTP_QSPI_HOLD_TIME_FUSE_MASK  (0x1800000u)
+#define OTP_QSPI_HOLD_TIME_FUSE_WIDTH (2u)
+#define OTP_QSPI_HOLD_TIME_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_HOLD_TIME_FUSE_IDX] & OTP_QSPI_HOLD_TIME_FUSE_MASK) >> OTP_QSPI_HOLD_TIME_FUSE_SHIFT)
+
+#define OTP_QSPI_PWR_HOLD_TIME_FUSE_IDX   (16u)
+#define OTP_QSPI_PWR_HOLD_TIME_FUSE_SHIFT (25u)
+#define OTP_QSPI_PWR_HOLD_TIME_FUSE_MASK  (0x1E000000u)
+#define OTP_QSPI_PWR_HOLD_TIME_FUSE_WIDTH (4u)
+#define OTP_QSPI_PWR_HOLD_TIME_FUSE_VALUE()                                                     \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_PWR_HOLD_TIME_FUSE_IDX] & OTP_QSPI_PWR_HOLD_TIME_FUSE_MASK) >> \
+     OTP_QSPI_PWR_HOLD_TIME_FUSE_SHIFT)
+
+/* Fuse Word BOOT_CFG2 Index 17 */
+#define OTP_BOOT_CFG2_FUSE_IDX (17u)
+
+#define OTP_BOOT_CFG2_FUSE_VALUE()     (OCOTP->OTP_SHADOW[OTP_BOOT_CFG2_FUSE_IDX])
+#define OTP_QSPI_IMAGE_SIZE_FUSE_IDX   (17u)
+#define OTP_QSPI_IMAGE_SIZE_FUSE_SHIFT (0u)
+#define OTP_QSPI_IMAGE_SIZE_FUSE_MASK  (0xFu)
+#define OTP_QSPI_IMAGE_SIZE_FUSE_WIDTH (4u)
+#define OTP_QSPI_IMAGE_SIZE_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_IMAGE_SIZE_FUSE_IDX] & OTP_QSPI_IMAGE_SIZE_FUSE_MASK) >> \
+     OTP_QSPI_IMAGE_SIZE_FUSE_SHIFT)
+
+#define OTP_QSPI_DELAY_CELL_NUM_FUSE_IDX   (17u)
+#define OTP_QSPI_DELAY_CELL_NUM_FUSE_SHIFT (4u)
+#define OTP_QSPI_DELAY_CELL_NUM_FUSE_MASK  (0x7F0u)
+#define OTP_QSPI_DELAY_CELL_NUM_FUSE_WIDTH (7u)
+#define OTP_QSPI_DELAY_CELL_NUM_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_DELAY_CELL_NUM_FUSE_IDX] & OTP_QSPI_DELAY_CELL_NUM_FUSE_MASK) >> \
+     OTP_QSPI_DELAY_CELL_NUM_FUSE_SHIFT)
+
+#define OTP_QSPI_IMAGE_OFFSET_FUSE_IDX   (17u)
+#define OTP_QSPI_IMAGE_OFFSET_FUSE_SHIFT (11u)
+#define OTP_QSPI_IMAGE_OFFSET_FUSE_MASK  (0x1FF800u)
+#define OTP_QSPI_IMAGE_OFFSET_FUSE_WIDTH (10u)
+#define OTP_QSPI_IMAGE_OFFSET_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_QSPI_IMAGE_OFFSET_FUSE_IDX] & OTP_QSPI_IMAGE_OFFSET_FUSE_MASK) >> \
+     OTP_QSPI_IMAGE_OFFSET_FUSE_SHIFT)
+
+/* Fuse Word BOOT_CFG3 Index 18 */
+#define OTP_BOOT_CFG3_FUSE_IDX (18u)
+
+#define OTP_BOOT_CFG3_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_BOOT_CFG3_FUSE_IDX])
+#define OTP_ROTK0_USAGE_FUSE_IDX   (18u)
+#define OTP_ROTK0_USAGE_FUSE_SHIFT (0u)
+#define OTP_ROTK0_USAGE_FUSE_MASK  (0x7u)
+#define OTP_ROTK0_USAGE_FUSE_WIDTH (3u)
+#define OTP_ROTK0_USAGE_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ROTK0_USAGE_FUSE_IDX] & OTP_ROTK0_USAGE_FUSE_MASK) >> OTP_ROTK0_USAGE_FUSE_SHIFT)
+
+#define OTP_ROTK1_USAGE_FUSE_IDX   (18u)
+#define OTP_ROTK1_USAGE_FUSE_SHIFT (3u)
+#define OTP_ROTK1_USAGE_FUSE_MASK  (0x38u)
+#define OTP_ROTK1_USAGE_FUSE_WIDTH (3u)
+#define OTP_ROTK1_USAGE_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ROTK1_USAGE_FUSE_IDX] & OTP_ROTK1_USAGE_FUSE_MASK) >> OTP_ROTK1_USAGE_FUSE_SHIFT)
+
+#define OTP_ROTK2_USAGE_FUSE_IDX   (18u)
+#define OTP_ROTK2_USAGE_FUSE_SHIFT (6u)
+#define OTP_ROTK2_USAGE_FUSE_MASK  (0x1C0u)
+#define OTP_ROTK2_USAGE_FUSE_WIDTH (3u)
+#define OTP_ROTK2_USAGE_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ROTK2_USAGE_FUSE_IDX] & OTP_ROTK2_USAGE_FUSE_MASK) >> OTP_ROTK2_USAGE_FUSE_SHIFT)
+
+#define OTP_ROTK3_USAGE_FUSE_IDX   (18u)
+#define OTP_ROTK3_USAGE_FUSE_SHIFT (9u)
+#define OTP_ROTK3_USAGE_FUSE_MASK  (0xE00u)
+#define OTP_ROTK3_USAGE_FUSE_WIDTH (3u)
+#define OTP_ROTK3_USAGE_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ROTK3_USAGE_FUSE_IDX] & OTP_ROTK3_USAGE_FUSE_MASK) >> OTP_ROTK3_USAGE_FUSE_SHIFT)
+
+#define OTP_ITRC_ZEROIZE_FUSE_IDX   (18u)
+#define OTP_ITRC_ZEROIZE_FUSE_SHIFT (12u)
+#define OTP_ITRC_ZEROIZE_FUSE_MASK  (0x3000u)
+#define OTP_ITRC_ZEROIZE_FUSE_WIDTH (2u)
+#define OTP_ITRC_ZEROIZE_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ITRC_ZEROIZE_FUSE_IDX] & OTP_ITRC_ZEROIZE_FUSE_MASK) >> OTP_ITRC_ZEROIZE_FUSE_SHIFT)
+
+#define OTP_PRINCE_ENABLE_FUSE_IDX   (18u)
+#define OTP_PRINCE_ENABLE_FUSE_SHIFT (14u)
+#define OTP_PRINCE_ENABLE_FUSE_MASK  (0x4000u)
+#define OTP_PRINCE_ENABLE_FUSE_WIDTH (1u)
+#define OTP_PRINCE_ENABLE_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PRINCE_ENABLE_FUSE_IDX] & OTP_PRINCE_ENABLE_FUSE_MASK) >> OTP_PRINCE_ENABLE_FUSE_SHIFT)
+
+#define OTP_ENF_CNSA_FUSE_IDX   (18u)
+#define OTP_ENF_CNSA_FUSE_SHIFT (15u)
+#define OTP_ENF_CNSA_FUSE_MASK  (0x18000u)
+#define OTP_ENF_CNSA_FUSE_WIDTH (2u)
+#define OTP_ENF_CNSA_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ENF_CNSA_FUSE_IDX] & OTP_ENF_CNSA_FUSE_MASK) >> OTP_ENF_CNSA_FUSE_SHIFT)
+
+#define OTP_ENABLE_CRC_CHECK_FUSE_IDX   (18u)
+#define OTP_ENABLE_CRC_CHECK_FUSE_SHIFT (17u)
+#define OTP_ENABLE_CRC_CHECK_FUSE_MASK  (0x60000u)
+#define OTP_ENABLE_CRC_CHECK_FUSE_WIDTH (2u)
+#define OTP_ENABLE_CRC_CHECK_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_ENABLE_CRC_CHECK_FUSE_IDX] & OTP_ENABLE_CRC_CHECK_FUSE_MASK) >> \
+     OTP_ENABLE_CRC_CHECK_FUSE_SHIFT)
+
+#define OTP_USE_PUF_FUSE_IDX   (18u)
+#define OTP_USE_PUF_FUSE_SHIFT (19u)
+#define OTP_USE_PUF_FUSE_MASK  (0x80000u)
+#define OTP_USE_PUF_FUSE_WIDTH (1u)
+#define OTP_USE_PUF_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_USE_PUF_FUSE_IDX] & OTP_USE_PUF_FUSE_MASK) >> OTP_USE_PUF_FUSE_SHIFT)
+
+#define OTP_PUF_BLOCK_ENROLL_FUSE_IDX   (18u)
+#define OTP_PUF_BLOCK_ENROLL_FUSE_SHIFT (20u)
+#define OTP_PUF_BLOCK_ENROLL_FUSE_MASK  (0x100000u)
+#define OTP_PUF_BLOCK_ENROLL_FUSE_WIDTH (1u)
+#define OTP_PUF_BLOCK_ENROLL_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_PUF_BLOCK_ENROLL_FUSE_IDX] & OTP_PUF_BLOCK_ENROLL_FUSE_MASK) >> \
+     OTP_PUF_BLOCK_ENROLL_FUSE_SHIFT)
+
+#define OTP_PUF_BLOCK_SET_KEY_FUSE_IDX   (18u)
+#define OTP_PUF_BLOCK_SET_KEY_FUSE_SHIFT (21u)
+#define OTP_PUF_BLOCK_SET_KEY_FUSE_MASK  (0x200000u)
+#define OTP_PUF_BLOCK_SET_KEY_FUSE_WIDTH (1u)
+#define OTP_PUF_BLOCK_SET_KEY_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_PUF_BLOCK_SET_KEY_FUSE_IDX] & OTP_PUF_BLOCK_SET_KEY_FUSE_MASK) >> \
+     OTP_PUF_BLOCK_SET_KEY_FUSE_SHIFT)
+
+#define OTP_FIPS_KDF_STEN_FUSE_IDX   (18u)
+#define OTP_FIPS_KDF_STEN_FUSE_SHIFT (22u)
+#define OTP_FIPS_KDF_STEN_FUSE_MASK  (0x400000u)
+#define OTP_FIPS_KDF_STEN_FUSE_WIDTH (1u)
+#define OTP_FIPS_KDF_STEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_FIPS_KDF_STEN_FUSE_IDX] & OTP_FIPS_KDF_STEN_FUSE_MASK) >> OTP_FIPS_KDF_STEN_FUSE_SHIFT)
+
+#define OTP_FIPS_CMAC_STEN_FUSE_IDX   (18u)
+#define OTP_FIPS_CMAC_STEN_FUSE_SHIFT (23u)
+#define OTP_FIPS_CMAC_STEN_FUSE_MASK  (0x800000u)
+#define OTP_FIPS_CMAC_STEN_FUSE_WIDTH (1u)
+#define OTP_FIPS_CMAC_STEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_FIPS_CMAC_STEN_FUSE_IDX] & OTP_FIPS_CMAC_STEN_FUSE_MASK) >> OTP_FIPS_CMAC_STEN_FUSE_SHIFT)
+
+#define OTP_FIPS_DRBG_STEN_FUSE_IDX   (18u)
+#define OTP_FIPS_DRBG_STEN_FUSE_SHIFT (24u)
+#define OTP_FIPS_DRBG_STEN_FUSE_MASK  (0x1000000u)
+#define OTP_FIPS_DRBG_STEN_FUSE_WIDTH (1u)
+#define OTP_FIPS_DRBG_STEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_FIPS_DRBG_STEN_FUSE_IDX] & OTP_FIPS_DRBG_STEN_FUSE_MASK) >> OTP_FIPS_DRBG_STEN_FUSE_SHIFT)
+
+#define OTP_FIPS_ECDSA_STEN_FUSE_IDX   (18u)
+#define OTP_FIPS_ECDSA_STEN_FUSE_SHIFT (25u)
+#define OTP_FIPS_ECDSA_STEN_FUSE_MASK  (0x2000000u)
+#define OTP_FIPS_ECDSA_STEN_FUSE_WIDTH (1u)
+#define OTP_FIPS_ECDSA_STEN_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_FIPS_ECDSA_STEN_FUSE_IDX] & OTP_FIPS_ECDSA_STEN_FUSE_MASK) >> \
+     OTP_FIPS_ECDSA_STEN_FUSE_SHIFT)
+
+#define OTP_FIPS_AES_STEN_FUSE_IDX   (18u)
+#define OTP_FIPS_AES_STEN_FUSE_SHIFT (26u)
+#define OTP_FIPS_AES_STEN_FUSE_MASK  (0x4000000u)
+#define OTP_FIPS_AES_STEN_FUSE_WIDTH (1u)
+#define OTP_FIPS_AES_STEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_FIPS_AES_STEN_FUSE_IDX] & OTP_FIPS_AES_STEN_FUSE_MASK) >> OTP_FIPS_AES_STEN_FUSE_SHIFT)
+
+#define OTP_FIPS_SHA_STEN_FUSE_IDX   (18u)
+#define OTP_FIPS_SHA_STEN_FUSE_SHIFT (27u)
+#define OTP_FIPS_SHA_STEN_FUSE_MASK  (0x8000000u)
+#define OTP_FIPS_SHA_STEN_FUSE_WIDTH (1u)
+#define OTP_FIPS_SHA_STEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_FIPS_SHA_STEN_FUSE_IDX] & OTP_FIPS_SHA_STEN_FUSE_MASK) >> OTP_FIPS_SHA_STEN_FUSE_SHIFT)
+
+#define OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_IDX   (18u)
+#define OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_SHIFT (28u)
+#define OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_MASK  (0x30000000u)
+#define OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_WIDTH (2u)
+#define OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_VALUE()                                                           \
+    ((OCOTP->OTP_SHADOW[OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_IDX] & OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_MASK) >> \
+     OTP_SKIP_PM_SIGN_VERIFCATION_FUSE_SHIFT)
+
+/* Fuse Word BOOT_CFG4 Index 19 */
+#define OTP_BOOT_CFG4_FUSE_IDX (19u)
+
+#define OTP_BOOT_CFG4_FUSE_VALUE()     (OCOTP->OTP_SHADOW[OTP_BOOT_CFG4_FUSE_IDX])
+#define OTP_RECOVERY_OFFSET_FUSE_IDX   (19u)
+#define OTP_RECOVERY_OFFSET_FUSE_SHIFT (0u)
+#define OTP_RECOVERY_OFFSET_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_RECOVERY_OFFSET_FUSE_WIDTH (32u)
+#define OTP_RECOVERY_OFFSET_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_RECOVERY_OFFSET_FUSE_IDX] & OTP_RECOVERY_OFFSET_FUSE_MASK) >> \
+     OTP_RECOVERY_OFFSET_FUSE_SHIFT)
+
+/* Fuse Word BOOT_CFG5 Index 20 */
+#define OTP_BOOT_CFG5_FUSE_IDX (20u)
+
+#define OTP_BOOT_CFG5_FUSE_VALUE()          (OCOTP->OTP_SHADOW[OTP_BOOT_CFG5_FUSE_IDX])
+#define OTP_KEY_STORE_START_ADDR_FUSE_IDX   (20u)
+#define OTP_KEY_STORE_START_ADDR_FUSE_SHIFT (0u)
+#define OTP_KEY_STORE_START_ADDR_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_KEY_STORE_START_ADDR_FUSE_WIDTH (32u)
+#define OTP_KEY_STORE_START_ADDR_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_KEY_STORE_START_ADDR_FUSE_IDX] & OTP_KEY_STORE_START_ADDR_FUSE_MASK) >> \
+     OTP_KEY_STORE_START_ADDR_FUSE_SHIFT)
+
+/* Fuse Word BOOT_CFG6 Index 21 */
+#define OTP_BOOT_CFG6_FUSE_IDX (21u)
+
+#define OTP_BOOT_CFG6_FUSE_VALUE()        (OCOTP->OTP_SHADOW[OTP_BOOT_CFG6_FUSE_IDX])
+#define OTP_KEY_STORE_END_ADDR_FUSE_IDX   (21u)
+#define OTP_KEY_STORE_END_ADDR_FUSE_SHIFT (0u)
+#define OTP_KEY_STORE_END_ADDR_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_KEY_STORE_END_ADDR_FUSE_WIDTH (32u)
+#define OTP_KEY_STORE_END_ADDR_FUSE_VALUE()                                                     \
+    ((OCOTP->OTP_SHADOW[OTP_KEY_STORE_END_ADDR_FUSE_IDX] & OTP_KEY_STORE_END_ADDR_FUSE_MASK) >> \
+     OTP_KEY_STORE_END_ADDR_FUSE_SHIFT)
+
+/* Fuse Word SEC_BOOT_CFG0 Index 22 */
+#define OTP_SEC_BOOT_CFG0_FUSE_IDX (22u)
+
+#define OTP_SEC_BOOT_CFG0_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG0_FUSE_IDX])
+#define OTP_REVOKE_ROOTKEY_FUSE_IDX    (22u)
+#define OTP_REVOKE_ROOTKEY_FUSE_SHIFT  (0u)
+#define OTP_REVOKE_ROOTKEY_FUSE_MASK   (0xFu)
+#define OTP_REVOKE_ROOTKEY_FUSE_WIDTH  (4u)
+#define OTP_REVOKE_ROOTKEY_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_REVOKE_ROOTKEY_FUSE_IDX] & OTP_REVOKE_ROOTKEY_FUSE_MASK) >> OTP_REVOKE_ROOTKEY_FUSE_SHIFT)
+
+#define OTP_FA_MODE_EN_FUSE_IDX   (22u)
+#define OTP_FA_MODE_EN_FUSE_SHIFT (4u)
+#define OTP_FA_MODE_EN_FUSE_MASK  (0x10u)
+#define OTP_FA_MODE_EN_FUSE_WIDTH (1u)
+#define OTP_FA_MODE_EN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_FA_MODE_EN_FUSE_IDX] & OTP_FA_MODE_EN_FUSE_MASK) >> OTP_FA_MODE_EN_FUSE_SHIFT)
+
+#define OTP_DICE_SKIP_CSR_FUSE_IDX   (22u)
+#define OTP_DICE_SKIP_CSR_FUSE_SHIFT (4u)
+#define OTP_DICE_SKIP_CSR_FUSE_MASK  (0x10u)
+#define OTP_DICE_SKIP_CSR_FUSE_WIDTH (1u)
+#define OTP_DICE_SKIP_CSR_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DICE_SKIP_CSR_FUSE_IDX] & OTP_DICE_SKIP_CSR_FUSE_MASK) >> OTP_DICE_SKIP_CSR_FUSE_SHIFT)
+
+/* Fuse Word SEC_BOOT_CFG1 Index 23 */
+#define OTP_SEC_BOOT_CFG1_FUSE_IDX (23u)
+
+#define OTP_SEC_BOOT_CFG1_FUSE_VALUE()  (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG1_FUSE_IDX])
+#define OTP_DAP_VENDOR_USAGE_FUSE_IDX   (23u)
+#define OTP_DAP_VENDOR_USAGE_FUSE_SHIFT (0u)
+#define OTP_DAP_VENDOR_USAGE_FUSE_MASK  (0xFFFFu)
+#define OTP_DAP_VENDOR_USAGE_FUSE_WIDTH (16u)
+#define OTP_DAP_VENDOR_USAGE_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_DAP_VENDOR_USAGE_FUSE_IDX] & OTP_DAP_VENDOR_USAGE_FUSE_MASK) >> \
+     OTP_DAP_VENDOR_USAGE_FUSE_SHIFT)
+
+/* Fuse Word SEC_BOOT_CFG2 Index 24 */
+#define OTP_SEC_BOOT_CFG2_FUSE_IDX (24u)
+
+#define OTP_SEC_BOOT_CFG2_FUSE_VALUE()     (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG2_FUSE_IDX])
+#define OTP_REVOKE_IMG_KEY_15_0_FUSE_IDX   (24u)
+#define OTP_REVOKE_IMG_KEY_15_0_FUSE_SHIFT (0u)
+#define OTP_REVOKE_IMG_KEY_15_0_FUSE_MASK  (0xFFFFu)
+#define OTP_REVOKE_IMG_KEY_15_0_FUSE_WIDTH (16u)
+#define OTP_REVOKE_IMG_KEY_15_0_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_REVOKE_IMG_KEY_15_0_FUSE_IDX] & OTP_REVOKE_IMG_KEY_15_0_FUSE_MASK) >> \
+     OTP_REVOKE_IMG_KEY_15_0_FUSE_SHIFT)
+
+/* Fuse Word SEC_BOOT_CFG3 Index 25 */
+#define OTP_SEC_BOOT_CFG3_FUSE_IDX (25u)
+
+#define OTP_SEC_BOOT_CFG3_FUSE_VALUE()      (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG3_FUSE_IDX])
+#define OTP_REVOKE_IMG_KEY_31_16_FUSE_IDX   (25u)
+#define OTP_REVOKE_IMG_KEY_31_16_FUSE_SHIFT (0u)
+#define OTP_REVOKE_IMG_KEY_31_16_FUSE_MASK  (0xFFFFu)
+#define OTP_REVOKE_IMG_KEY_31_16_FUSE_WIDTH (16u)
+#define OTP_REVOKE_IMG_KEY_31_16_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_REVOKE_IMG_KEY_31_16_FUSE_IDX] & OTP_REVOKE_IMG_KEY_31_16_FUSE_MASK) >> \
+     OTP_REVOKE_IMG_KEY_31_16_FUSE_SHIFT)
+
+/* Fuse Word SEC_BOOT_CFG4 Index 26 */
+#define OTP_SEC_BOOT_CFG4_FUSE_IDX (26u)
+
+#define OTP_SEC_BOOT_CFG4_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG4_FUSE_IDX])
+/* Fuse Word SEC_BOOT_CFG5 Index 27 */
+#define OTP_SEC_BOOT_CFG5_FUSE_IDX (27u)
+
+#define OTP_SEC_BOOT_CFG5_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG5_FUSE_IDX])
+/* Fuse Word SEC_BOOT_CFG6 Index 28 */
+#define OTP_SEC_BOOT_CFG6_FUSE_IDX (28u)
+
+#define OTP_SEC_BOOT_CFG6_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG6_FUSE_IDX])
+/* Fuse Word SEC_BOOT_CFG7 Index 29 */
+#define OTP_SEC_BOOT_CFG7_FUSE_IDX (29u)
+
+#define OTP_SEC_BOOT_CFG7_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG7_FUSE_IDX])
+/* Fuse Word SEC_BOOT_CFG8 Index 30 */
+#define OTP_SEC_BOOT_CFG8_FUSE_IDX (30u)
+
+#define OTP_SEC_BOOT_CFG8_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_SEC_BOOT_CFG8_FUSE_IDX])
+/* Fuse Word DCFG_CC_SOCU_NS Index 31 */
+#define OTP_DCFG_CC_SOCU_NS_FUSE_IDX (31u)
+
+#define OTP_DCFG_CC_SOCU_NS_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_DCFG_CC_SOCU_NS_FUSE_IDX])
+#define OTP_CRC8_NS_FUSE_IDX             (31u)
+#define OTP_CRC8_NS_FUSE_SHIFT           (0u)
+#define OTP_CRC8_NS_FUSE_MASK            (0xFFu)
+#define OTP_CRC8_NS_FUSE_WIDTH           (8u)
+#define OTP_CRC8_NS_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_CRC8_NS_FUSE_IDX] & OTP_CRC8_NS_FUSE_MASK) >> OTP_CRC8_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_NIDEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_NIDEN_NS_FUSE_SHIFT (8u)
+#define OTP_DFLT_NIDEN_NS_FUSE_MASK  (0x100u)
+#define OTP_DFLT_NIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_NIDEN_NS_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_NIDEN_NS_FUSE_IDX] & OTP_DFLT_NIDEN_NS_FUSE_MASK) >> OTP_DFLT_NIDEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_DBGEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_DBGEN_NS_FUSE_SHIFT (9u)
+#define OTP_DFLT_DBGEN_NS_FUSE_MASK  (0x200u)
+#define OTP_DFLT_DBGEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_DBGEN_NS_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_DBGEN_NS_FUSE_IDX] & OTP_DFLT_DBGEN_NS_FUSE_MASK) >> OTP_DFLT_DBGEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_SPNIDEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_SPNIDEN_NS_FUSE_SHIFT (10u)
+#define OTP_DFLT_SPNIDEN_NS_FUSE_MASK  (0x400u)
+#define OTP_DFLT_SPNIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_SPNIDEN_NS_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_SPNIDEN_NS_FUSE_IDX] & OTP_DFLT_SPNIDEN_NS_FUSE_MASK) >> \
+     OTP_DFLT_SPNIDEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_SPIDEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_SPIDEN_NS_FUSE_SHIFT (11u)
+#define OTP_DFLT_SPIDEN_NS_FUSE_MASK  (0x800u)
+#define OTP_DFLT_SPIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_SPIDEN_NS_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_SPIDEN_NS_FUSE_IDX] & OTP_DFLT_SPIDEN_NS_FUSE_MASK) >> OTP_DFLT_SPIDEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_TAPEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_TAPEN_NS_FUSE_SHIFT (12u)
+#define OTP_DFLT_TAPEN_NS_FUSE_MASK  (0x1000u)
+#define OTP_DFLT_TAPEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_TAPEN_NS_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_TAPEN_NS_FUSE_IDX] & OTP_DFLT_TAPEN_NS_FUSE_MASK) >> OTP_DFLT_TAPEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU1NIDEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_CPU1NIDEN_NS_FUSE_SHIFT (13u)
+#define OTP_DFLT_CPU1NIDEN_NS_FUSE_MASK  (0x2000u)
+#define OTP_DFLT_CPU1NIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU1NIDEN_NS_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU1NIDEN_NS_FUSE_IDX] & OTP_DFLT_CPU1NIDEN_NS_FUSE_MASK) >> \
+     OTP_DFLT_CPU1NIDEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU1DBGEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_CPU1DBGEN_NS_FUSE_SHIFT (14u)
+#define OTP_DFLT_CPU1DBGEN_NS_FUSE_MASK  (0x4000u)
+#define OTP_DFLT_CPU1DBGEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU1DBGEN_NS_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU1DBGEN_NS_FUSE_IDX] & OTP_DFLT_CPU1DBGEN_NS_FUSE_MASK) >> \
+     OTP_DFLT_CPU1DBGEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU2NIDEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_CPU2NIDEN_NS_FUSE_SHIFT (15u)
+#define OTP_DFLT_CPU2NIDEN_NS_FUSE_MASK  (0x8000u)
+#define OTP_DFLT_CPU2NIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU2NIDEN_NS_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU2NIDEN_NS_FUSE_IDX] & OTP_DFLT_CPU2NIDEN_NS_FUSE_MASK) >> \
+     OTP_DFLT_CPU2NIDEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU2DBGEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_CPU2DBGEN_NS_FUSE_SHIFT (16u)
+#define OTP_DFLT_CPU2DBGEN_NS_FUSE_MASK  (0x10000u)
+#define OTP_DFLT_CPU2DBGEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU2DBGEN_NS_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU2DBGEN_NS_FUSE_IDX] & OTP_DFLT_CPU2DBGEN_NS_FUSE_MASK) >> \
+     OTP_DFLT_CPU2DBGEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_ISPCMDEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_ISPCMDEN_NS_FUSE_SHIFT (17u)
+#define OTP_DFLT_ISPCMDEN_NS_FUSE_MASK  (0x20000u)
+#define OTP_DFLT_ISPCMDEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_ISPCMDEN_NS_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_ISPCMDEN_NS_FUSE_IDX] & OTP_DFLT_ISPCMDEN_NS_FUSE_MASK) >> \
+     OTP_DFLT_ISPCMDEN_NS_FUSE_SHIFT)
+
+#define OTP_DFLT_FACMDEN_NS_FUSE_IDX   (31u)
+#define OTP_DFLT_FACMDEN_NS_FUSE_SHIFT (18u)
+#define OTP_DFLT_FACMDEN_NS_FUSE_MASK  (0x40000u)
+#define OTP_DFLT_FACMDEN_NS_FUSE_WIDTH (1u)
+#define OTP_DFLT_FACMDEN_NS_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_FACMDEN_NS_FUSE_IDX] & OTP_DFLT_FACMDEN_NS_FUSE_MASK) >> \
+     OTP_DFLT_FACMDEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_NIDEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_NIDEN_NS_FUSE_SHIFT (19u)
+#define OTP_PINNED_NIDEN_NS_FUSE_MASK  (0x80000u)
+#define OTP_PINNED_NIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_NIDEN_NS_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_NIDEN_NS_FUSE_IDX] & OTP_PINNED_NIDEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_NIDEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_DBGEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_DBGEN_NS_FUSE_SHIFT (20u)
+#define OTP_PINNED_DBGEN_NS_FUSE_MASK  (0x100000u)
+#define OTP_PINNED_DBGEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_DBGEN_NS_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_DBGEN_NS_FUSE_IDX] & OTP_PINNED_DBGEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_DBGEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_SPNIDEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_SPNIDEN_NS_FUSE_SHIFT (21u)
+#define OTP_PINNED_SPNIDEN_NS_FUSE_MASK  (0x200000u)
+#define OTP_PINNED_SPNIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_SPNIDEN_NS_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_SPNIDEN_NS_FUSE_IDX] & OTP_PINNED_SPNIDEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_SPNIDEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_SPIDEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_SPIDEN_NS_FUSE_SHIFT (22u)
+#define OTP_PINNED_SPIDEN_NS_FUSE_MASK  (0x400000u)
+#define OTP_PINNED_SPIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_SPIDEN_NS_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_SPIDEN_NS_FUSE_IDX] & OTP_PINNED_SPIDEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_SPIDEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_TAPEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_TAPEN_NS_FUSE_SHIFT (23u)
+#define OTP_PINNED_TAPEN_NS_FUSE_MASK  (0x800000u)
+#define OTP_PINNED_TAPEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_TAPEN_NS_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_TAPEN_NS_FUSE_IDX] & OTP_PINNED_TAPEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_TAPEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU1NIDEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_CPU1NIDEN_NS_FUSE_SHIFT (24u)
+#define OTP_PINNED_CPU1NIDEN_NS_FUSE_MASK  (0x1000000u)
+#define OTP_PINNED_CPU1NIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU1NIDEN_NS_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU1NIDEN_NS_FUSE_IDX] & OTP_PINNED_CPU1NIDEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_CPU1NIDEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU1DBGEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_CPU1DBGEN_NS_FUSE_SHIFT (25u)
+#define OTP_PINNED_CPU1DBGEN_NS_FUSE_MASK  (0x2000000u)
+#define OTP_PINNED_CPU1DBGEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU1DBGEN_NS_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU1DBGEN_NS_FUSE_IDX] & OTP_PINNED_CPU1DBGEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_CPU1DBGEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU2NIDEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_CPU2NIDEN_NS_FUSE_SHIFT (26u)
+#define OTP_PINNED_CPU2NIDEN_NS_FUSE_MASK  (0x4000000u)
+#define OTP_PINNED_CPU2NIDEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU2NIDEN_NS_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU2NIDEN_NS_FUSE_IDX] & OTP_PINNED_CPU2NIDEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_CPU2NIDEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU2DBGEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_CPU2DBGEN_NS_FUSE_SHIFT (27u)
+#define OTP_PINNED_CPU2DBGEN_NS_FUSE_MASK  (0x8000000u)
+#define OTP_PINNED_CPU2DBGEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU2DBGEN_NS_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU2DBGEN_NS_FUSE_IDX] & OTP_PINNED_CPU2DBGEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_CPU2DBGEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_ISPCMDEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_ISPCMDEN_NS_FUSE_SHIFT (28u)
+#define OTP_PINNED_ISPCMDEN_NS_FUSE_MASK  (0x10000000u)
+#define OTP_PINNED_ISPCMDEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_ISPCMDEN_NS_FUSE_VALUE()                                                     \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_ISPCMDEN_NS_FUSE_IDX] & OTP_PINNED_ISPCMDEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_ISPCMDEN_NS_FUSE_SHIFT)
+
+#define OTP_PINNED_FACMDEN_NS_FUSE_IDX   (31u)
+#define OTP_PINNED_FACMDEN_NS_FUSE_SHIFT (29u)
+#define OTP_PINNED_FACMDEN_NS_FUSE_MASK  (0x20000000u)
+#define OTP_PINNED_FACMDEN_NS_FUSE_WIDTH (1u)
+#define OTP_PINNED_FACMDEN_NS_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_FACMDEN_NS_FUSE_IDX] & OTP_PINNED_FACMDEN_NS_FUSE_MASK) >> \
+     OTP_PINNED_FACMDEN_NS_FUSE_SHIFT)
+
+#define OTP_FORCE_UUID_MATCH_NS_FUSE_IDX   (31u)
+#define OTP_FORCE_UUID_MATCH_NS_FUSE_SHIFT (30u)
+#define OTP_FORCE_UUID_MATCH_NS_FUSE_MASK  (0x40000000u)
+#define OTP_FORCE_UUID_MATCH_NS_FUSE_WIDTH (1u)
+#define OTP_FORCE_UUID_MATCH_NS_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_FORCE_UUID_MATCH_NS_FUSE_IDX] & OTP_FORCE_UUID_MATCH_NS_FUSE_MASK) >> \
+     OTP_FORCE_UUID_MATCH_NS_FUSE_SHIFT)
+
+/* Fuse Word USB_ID Index 32 */
+#define OTP_USB_ID_FUSE_IDX (32u)
+
+#define OTP_USB_VID_FUSE_IDX   (32u)
+#define OTP_USB_VID_FUSE_SHIFT (0u)
+#define OTP_USB_VID_FUSE_MASK  (0xFFFFu)
+#define OTP_USB_VID_FUSE_WIDTH (16u)
+
+#define OTP_USB_PID_FUSE_IDX   (32u)
+#define OTP_USB_PID_FUSE_SHIFT (16u)
+#define OTP_USB_PID_FUSE_MASK  (0xFFFF0000u)
+#define OTP_USB_PID_FUSE_WIDTH (16u)
+
+/* Fuse Word DCFG_CC_SOCU Index 33 */
+#define OTP_DCFG_CC_SOCU_FUSE_IDX (33u)
+
+#define OTP_DCFG_CC_SOCU_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_DCFG_CC_SOCU_FUSE_IDX])
+#define OTP_CRC8_FUSE_IDX             (33u)
+#define OTP_CRC8_FUSE_SHIFT           (0u)
+#define OTP_CRC8_FUSE_MASK            (0xFFu)
+#define OTP_CRC8_FUSE_WIDTH           (8u)
+#define OTP_CRC8_FUSE_VALUE()         ((OCOTP->OTP_SHADOW[OTP_CRC8_FUSE_IDX] & OTP_CRC8_FUSE_MASK) >> OTP_CRC8_FUSE_SHIFT)
+
+#define OTP_DFLT_NIDEN_FUSE_IDX   (33u)
+#define OTP_DFLT_NIDEN_FUSE_SHIFT (8u)
+#define OTP_DFLT_NIDEN_FUSE_MASK  (0x100u)
+#define OTP_DFLT_NIDEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_NIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_NIDEN_FUSE_IDX] & OTP_DFLT_NIDEN_FUSE_MASK) >> OTP_DFLT_NIDEN_FUSE_SHIFT)
+
+#define OTP_DFLT_DBGEN_FUSE_IDX   (33u)
+#define OTP_DFLT_DBGEN_FUSE_SHIFT (9u)
+#define OTP_DFLT_DBGEN_FUSE_MASK  (0x200u)
+#define OTP_DFLT_DBGEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_DBGEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_DBGEN_FUSE_IDX] & OTP_DFLT_DBGEN_FUSE_MASK) >> OTP_DFLT_DBGEN_FUSE_SHIFT)
+
+#define OTP_DFLT_SPNIDEN_FUSE_IDX   (33u)
+#define OTP_DFLT_SPNIDEN_FUSE_SHIFT (10u)
+#define OTP_DFLT_SPNIDEN_FUSE_MASK  (0x400u)
+#define OTP_DFLT_SPNIDEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_SPNIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_SPNIDEN_FUSE_IDX] & OTP_DFLT_SPNIDEN_FUSE_MASK) >> OTP_DFLT_SPNIDEN_FUSE_SHIFT)
+
+#define OTP_DFLT_SPIDEN_FUSE_IDX   (33u)
+#define OTP_DFLT_SPIDEN_FUSE_SHIFT (11u)
+#define OTP_DFLT_SPIDEN_FUSE_MASK  (0x800u)
+#define OTP_DFLT_SPIDEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_SPIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_SPIDEN_FUSE_IDX] & OTP_DFLT_SPIDEN_FUSE_MASK) >> OTP_DFLT_SPIDEN_FUSE_SHIFT)
+
+#define OTP_DFLT_TAPEN_FUSE_IDX   (33u)
+#define OTP_DFLT_TAPEN_FUSE_SHIFT (12u)
+#define OTP_DFLT_TAPEN_FUSE_MASK  (0x1000u)
+#define OTP_DFLT_TAPEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_TAPEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_TAPEN_FUSE_IDX] & OTP_DFLT_TAPEN_FUSE_MASK) >> OTP_DFLT_TAPEN_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU1NIDEN_FUSE_IDX   (33u)
+#define OTP_DFLT_CPU1NIDEN_FUSE_SHIFT (13u)
+#define OTP_DFLT_CPU1NIDEN_FUSE_MASK  (0x2000u)
+#define OTP_DFLT_CPU1NIDEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU1NIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU1NIDEN_FUSE_IDX] & OTP_DFLT_CPU1NIDEN_FUSE_MASK) >> OTP_DFLT_CPU1NIDEN_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU1DBGEN_FUSE_IDX   (33u)
+#define OTP_DFLT_CPU1DBGEN_FUSE_SHIFT (14u)
+#define OTP_DFLT_CPU1DBGEN_FUSE_MASK  (0x4000u)
+#define OTP_DFLT_CPU1DBGEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU1DBGEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU1DBGEN_FUSE_IDX] & OTP_DFLT_CPU1DBGEN_FUSE_MASK) >> OTP_DFLT_CPU1DBGEN_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU2NIDEN_FUSE_IDX   (33u)
+#define OTP_DFLT_CPU2NIDEN_FUSE_SHIFT (15u)
+#define OTP_DFLT_CPU2NIDEN_FUSE_MASK  (0x8000u)
+#define OTP_DFLT_CPU2NIDEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU2NIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU2NIDEN_FUSE_IDX] & OTP_DFLT_CPU2NIDEN_FUSE_MASK) >> OTP_DFLT_CPU2NIDEN_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU2DBGEN_FUSE_IDX   (33u)
+#define OTP_DFLT_CPU2DBGEN_FUSE_SHIFT (16u)
+#define OTP_DFLT_CPU2DBGEN_FUSE_MASK  (0x10000u)
+#define OTP_DFLT_CPU2DBGEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU2DBGEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU2DBGEN_FUSE_IDX] & OTP_DFLT_CPU2DBGEN_FUSE_MASK) >> OTP_DFLT_CPU2DBGEN_FUSE_SHIFT)
+
+#define OTP_DFLT_ISPCMDEN_FUSE_IDX   (33u)
+#define OTP_DFLT_ISPCMDEN_FUSE_SHIFT (17u)
+#define OTP_DFLT_ISPCMDEN_FUSE_MASK  (0x20000u)
+#define OTP_DFLT_ISPCMDEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_ISPCMDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_ISPCMDEN_FUSE_IDX] & OTP_DFLT_ISPCMDEN_FUSE_MASK) >> OTP_DFLT_ISPCMDEN_FUSE_SHIFT)
+
+#define OTP_DFLT_FACMDEN_FUSE_IDX   (33u)
+#define OTP_DFLT_FACMDEN_FUSE_SHIFT (18u)
+#define OTP_DFLT_FACMDEN_FUSE_MASK  (0x40000u)
+#define OTP_DFLT_FACMDEN_FUSE_WIDTH (1u)
+#define OTP_DFLT_FACMDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_FACMDEN_FUSE_IDX] & OTP_DFLT_FACMDEN_FUSE_MASK) >> OTP_DFLT_FACMDEN_FUSE_SHIFT)
+
+#define OTP_PINNED_NIDEN_FUSE_IDX   (33u)
+#define OTP_PINNED_NIDEN_FUSE_SHIFT (19u)
+#define OTP_PINNED_NIDEN_FUSE_MASK  (0x80000u)
+#define OTP_PINNED_NIDEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_NIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_NIDEN_FUSE_IDX] & OTP_PINNED_NIDEN_FUSE_MASK) >> OTP_PINNED_NIDEN_FUSE_SHIFT)
+
+#define OTP_PINNED_DBGEN_FUSE_IDX   (33u)
+#define OTP_PINNED_DBGEN_FUSE_SHIFT (20u)
+#define OTP_PINNED_DBGEN_FUSE_MASK  (0x100000u)
+#define OTP_PINNED_DBGEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_DBGEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_DBGEN_FUSE_IDX] & OTP_PINNED_DBGEN_FUSE_MASK) >> OTP_PINNED_DBGEN_FUSE_SHIFT)
+
+#define OTP_PINNED_SPNIDEN_FUSE_IDX   (33u)
+#define OTP_PINNED_SPNIDEN_FUSE_SHIFT (21u)
+#define OTP_PINNED_SPNIDEN_FUSE_MASK  (0x200000u)
+#define OTP_PINNED_SPNIDEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_SPNIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_SPNIDEN_FUSE_IDX] & OTP_PINNED_SPNIDEN_FUSE_MASK) >> OTP_PINNED_SPNIDEN_FUSE_SHIFT)
+
+#define OTP_PINNED_SPIDEN_FUSE_IDX   (33u)
+#define OTP_PINNED_SPIDEN_FUSE_SHIFT (22u)
+#define OTP_PINNED_SPIDEN_FUSE_MASK  (0x400000u)
+#define OTP_PINNED_SPIDEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_SPIDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_SPIDEN_FUSE_IDX] & OTP_PINNED_SPIDEN_FUSE_MASK) >> OTP_PINNED_SPIDEN_FUSE_SHIFT)
+
+#define OTP_PINNED_TAPEN_FUSE_IDX   (33u)
+#define OTP_PINNED_TAPEN_FUSE_SHIFT (23u)
+#define OTP_PINNED_TAPEN_FUSE_MASK  (0x800000u)
+#define OTP_PINNED_TAPEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_TAPEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_TAPEN_FUSE_IDX] & OTP_PINNED_TAPEN_FUSE_MASK) >> OTP_PINNED_TAPEN_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU1NIDEN_FUSE_IDX   (33u)
+#define OTP_PINNED_CPU1NIDEN_FUSE_SHIFT (24u)
+#define OTP_PINNED_CPU1NIDEN_FUSE_MASK  (0x1000000u)
+#define OTP_PINNED_CPU1NIDEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU1NIDEN_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU1NIDEN_FUSE_IDX] & OTP_PINNED_CPU1NIDEN_FUSE_MASK) >> \
+     OTP_PINNED_CPU1NIDEN_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU1DBGEN_FUSE_IDX   (33u)
+#define OTP_PINNED_CPU1DBGEN_FUSE_SHIFT (25u)
+#define OTP_PINNED_CPU1DBGEN_FUSE_MASK  (0x2000000u)
+#define OTP_PINNED_CPU1DBGEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU1DBGEN_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU1DBGEN_FUSE_IDX] & OTP_PINNED_CPU1DBGEN_FUSE_MASK) >> \
+     OTP_PINNED_CPU1DBGEN_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU2NIDEN_FUSE_IDX   (33u)
+#define OTP_PINNED_CPU2NIDEN_FUSE_SHIFT (26u)
+#define OTP_PINNED_CPU2NIDEN_FUSE_MASK  (0x4000000u)
+#define OTP_PINNED_CPU2NIDEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU2NIDEN_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU2NIDEN_FUSE_IDX] & OTP_PINNED_CPU2NIDEN_FUSE_MASK) >> \
+     OTP_PINNED_CPU2NIDEN_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU2DBGEN_FUSE_IDX   (33u)
+#define OTP_PINNED_CPU2DBGEN_FUSE_SHIFT (27u)
+#define OTP_PINNED_CPU2DBGEN_FUSE_MASK  (0x8000000u)
+#define OTP_PINNED_CPU2DBGEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU2DBGEN_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU2DBGEN_FUSE_IDX] & OTP_PINNED_CPU2DBGEN_FUSE_MASK) >> \
+     OTP_PINNED_CPU2DBGEN_FUSE_SHIFT)
+
+#define OTP_PINNED_ISPCMDEN_FUSE_IDX   (33u)
+#define OTP_PINNED_ISPCMDEN_FUSE_SHIFT (28u)
+#define OTP_PINNED_ISPCMDEN_FUSE_MASK  (0x10000000u)
+#define OTP_PINNED_ISPCMDEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_ISPCMDEN_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_ISPCMDEN_FUSE_IDX] & OTP_PINNED_ISPCMDEN_FUSE_MASK) >> \
+     OTP_PINNED_ISPCMDEN_FUSE_SHIFT)
+
+#define OTP_PINNED_FACMDEN_FUSE_IDX   (33u)
+#define OTP_PINNED_FACMDEN_FUSE_SHIFT (29u)
+#define OTP_PINNED_FACMDEN_FUSE_MASK  (0x20000000u)
+#define OTP_PINNED_FACMDEN_FUSE_WIDTH (1u)
+#define OTP_PINNED_FACMDEN_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_FACMDEN_FUSE_IDX] & OTP_PINNED_FACMDEN_FUSE_MASK) >> OTP_PINNED_FACMDEN_FUSE_SHIFT)
+
+#define OTP_FORCE_UUID_MATCH_FUSE_IDX   (33u)
+#define OTP_FORCE_UUID_MATCH_FUSE_SHIFT (30u)
+#define OTP_FORCE_UUID_MATCH_FUSE_MASK  (0x40000000u)
+#define OTP_FORCE_UUID_MATCH_FUSE_WIDTH (1u)
+#define OTP_FORCE_UUID_MATCH_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_FORCE_UUID_MATCH_FUSE_IDX] & OTP_FORCE_UUID_MATCH_FUSE_MASK) >> \
+     OTP_FORCE_UUID_MATCH_FUSE_SHIFT)
+
+/* Fuse Word DCFG_CC_SOCU_AP Index 34 */
+#define OTP_DCFG_CC_SOCU_AP_FUSE_IDX (34u)
+
+#define OTP_DCFG_CC_SOCU_AP_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_DCFG_CC_SOCU_AP_FUSE_IDX])
+#define OTP_CRC8_AP_FUSE_IDX             (34u)
+#define OTP_CRC8_AP_FUSE_SHIFT           (0u)
+#define OTP_CRC8_AP_FUSE_MASK            (0xFFu)
+#define OTP_CRC8_AP_FUSE_WIDTH           (8u)
+#define OTP_CRC8_AP_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_CRC8_AP_FUSE_IDX] & OTP_CRC8_AP_FUSE_MASK) >> OTP_CRC8_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_NIDEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_NIDEN_AP_FUSE_SHIFT (8u)
+#define OTP_DFLT_NIDEN_AP_FUSE_MASK  (0x100u)
+#define OTP_DFLT_NIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_NIDEN_AP_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_NIDEN_AP_FUSE_IDX] & OTP_DFLT_NIDEN_AP_FUSE_MASK) >> OTP_DFLT_NIDEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_DBGEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_DBGEN_AP_FUSE_SHIFT (9u)
+#define OTP_DFLT_DBGEN_AP_FUSE_MASK  (0x200u)
+#define OTP_DFLT_DBGEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_DBGEN_AP_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_DBGEN_AP_FUSE_IDX] & OTP_DFLT_DBGEN_AP_FUSE_MASK) >> OTP_DFLT_DBGEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_SPNIDEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_SPNIDEN_AP_FUSE_SHIFT (10u)
+#define OTP_DFLT_SPNIDEN_AP_FUSE_MASK  (0x400u)
+#define OTP_DFLT_SPNIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_SPNIDEN_AP_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_SPNIDEN_AP_FUSE_IDX] & OTP_DFLT_SPNIDEN_AP_FUSE_MASK) >> \
+     OTP_DFLT_SPNIDEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_SPIDEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_SPIDEN_AP_FUSE_SHIFT (11u)
+#define OTP_DFLT_SPIDEN_AP_FUSE_MASK  (0x800u)
+#define OTP_DFLT_SPIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_SPIDEN_AP_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_SPIDEN_AP_FUSE_IDX] & OTP_DFLT_SPIDEN_AP_FUSE_MASK) >> OTP_DFLT_SPIDEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_TAPEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_TAPEN_AP_FUSE_SHIFT (12u)
+#define OTP_DFLT_TAPEN_AP_FUSE_MASK  (0x1000u)
+#define OTP_DFLT_TAPEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_TAPEN_AP_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_TAPEN_AP_FUSE_IDX] & OTP_DFLT_TAPEN_AP_FUSE_MASK) >> OTP_DFLT_TAPEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU1NIDEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_CPU1NIDEN_AP_FUSE_SHIFT (13u)
+#define OTP_DFLT_CPU1NIDEN_AP_FUSE_MASK  (0x2000u)
+#define OTP_DFLT_CPU1NIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU1NIDEN_AP_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU1NIDEN_AP_FUSE_IDX] & OTP_DFLT_CPU1NIDEN_AP_FUSE_MASK) >> \
+     OTP_DFLT_CPU1NIDEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU1DBGEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_CPU1DBGEN_AP_FUSE_SHIFT (14u)
+#define OTP_DFLT_CPU1DBGEN_AP_FUSE_MASK  (0x4000u)
+#define OTP_DFLT_CPU1DBGEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU1DBGEN_AP_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU1DBGEN_AP_FUSE_IDX] & OTP_DFLT_CPU1DBGEN_AP_FUSE_MASK) >> \
+     OTP_DFLT_CPU1DBGEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU2NIDEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_CPU2NIDEN_AP_FUSE_SHIFT (15u)
+#define OTP_DFLT_CPU2NIDEN_AP_FUSE_MASK  (0x8000u)
+#define OTP_DFLT_CPU2NIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU2NIDEN_AP_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU2NIDEN_AP_FUSE_IDX] & OTP_DFLT_CPU2NIDEN_AP_FUSE_MASK) >> \
+     OTP_DFLT_CPU2NIDEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_CPU2DBGEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_CPU2DBGEN_AP_FUSE_SHIFT (16u)
+#define OTP_DFLT_CPU2DBGEN_AP_FUSE_MASK  (0x10000u)
+#define OTP_DFLT_CPU2DBGEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_CPU2DBGEN_AP_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_CPU2DBGEN_AP_FUSE_IDX] & OTP_DFLT_CPU2DBGEN_AP_FUSE_MASK) >> \
+     OTP_DFLT_CPU2DBGEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_ISPCMDEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_ISPCMDEN_AP_FUSE_SHIFT (17u)
+#define OTP_DFLT_ISPCMDEN_AP_FUSE_MASK  (0x20000u)
+#define OTP_DFLT_ISPCMDEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_ISPCMDEN_AP_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_ISPCMDEN_AP_FUSE_IDX] & OTP_DFLT_ISPCMDEN_AP_FUSE_MASK) >> \
+     OTP_DFLT_ISPCMDEN_AP_FUSE_SHIFT)
+
+#define OTP_DFLT_FACMDEN_AP_FUSE_IDX   (34u)
+#define OTP_DFLT_FACMDEN_AP_FUSE_SHIFT (18u)
+#define OTP_DFLT_FACMDEN_AP_FUSE_MASK  (0x40000u)
+#define OTP_DFLT_FACMDEN_AP_FUSE_WIDTH (1u)
+#define OTP_DFLT_FACMDEN_AP_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_DFLT_FACMDEN_AP_FUSE_IDX] & OTP_DFLT_FACMDEN_AP_FUSE_MASK) >> \
+     OTP_DFLT_FACMDEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_NIDEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_NIDEN_AP_FUSE_SHIFT (19u)
+#define OTP_PINNED_NIDEN_AP_FUSE_MASK  (0x80000u)
+#define OTP_PINNED_NIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_NIDEN_AP_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_NIDEN_AP_FUSE_IDX] & OTP_PINNED_NIDEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_NIDEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_DBGEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_DBGEN_AP_FUSE_SHIFT (20u)
+#define OTP_PINNED_DBGEN_AP_FUSE_MASK  (0x100000u)
+#define OTP_PINNED_DBGEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_DBGEN_AP_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_DBGEN_AP_FUSE_IDX] & OTP_PINNED_DBGEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_DBGEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_SPNIDEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_SPNIDEN_AP_FUSE_SHIFT (21u)
+#define OTP_PINNED_SPNIDEN_AP_FUSE_MASK  (0x200000u)
+#define OTP_PINNED_SPNIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_SPNIDEN_AP_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_SPNIDEN_AP_FUSE_IDX] & OTP_PINNED_SPNIDEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_SPNIDEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_SPIDEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_SPIDEN_AP_FUSE_SHIFT (22u)
+#define OTP_PINNED_SPIDEN_AP_FUSE_MASK  (0x400000u)
+#define OTP_PINNED_SPIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_SPIDEN_AP_FUSE_VALUE()                                                   \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_SPIDEN_AP_FUSE_IDX] & OTP_PINNED_SPIDEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_SPIDEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_TAPEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_TAPEN_AP_FUSE_SHIFT (23u)
+#define OTP_PINNED_TAPEN_AP_FUSE_MASK  (0x800000u)
+#define OTP_PINNED_TAPEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_TAPEN_AP_FUSE_VALUE()                                                  \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_TAPEN_AP_FUSE_IDX] & OTP_PINNED_TAPEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_TAPEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU1NIDEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_CPU1NIDEN_AP_FUSE_SHIFT (24u)
+#define OTP_PINNED_CPU1NIDEN_AP_FUSE_MASK  (0x1000000u)
+#define OTP_PINNED_CPU1NIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU1NIDEN_AP_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU1NIDEN_AP_FUSE_IDX] & OTP_PINNED_CPU1NIDEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_CPU1NIDEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU1DBGEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_CPU1DBGEN_AP_FUSE_SHIFT (25u)
+#define OTP_PINNED_CPU1DBGEN_AP_FUSE_MASK  (0x2000000u)
+#define OTP_PINNED_CPU1DBGEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU1DBGEN_AP_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU1DBGEN_AP_FUSE_IDX] & OTP_PINNED_CPU1DBGEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_CPU1DBGEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU2NIDEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_CPU2NIDEN_AP_FUSE_SHIFT (26u)
+#define OTP_PINNED_CPU2NIDEN_AP_FUSE_MASK  (0x4000000u)
+#define OTP_PINNED_CPU2NIDEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU2NIDEN_AP_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU2NIDEN_AP_FUSE_IDX] & OTP_PINNED_CPU2NIDEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_CPU2NIDEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_CPU2DBGEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_CPU2DBGEN_AP_FUSE_SHIFT (27u)
+#define OTP_PINNED_CPU2DBGEN_AP_FUSE_MASK  (0x8000000u)
+#define OTP_PINNED_CPU2DBGEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_CPU2DBGEN_AP_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_CPU2DBGEN_AP_FUSE_IDX] & OTP_PINNED_CPU2DBGEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_CPU2DBGEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_ISPCMDEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_ISPCMDEN_AP_FUSE_SHIFT (28u)
+#define OTP_PINNED_ISPCMDEN_AP_FUSE_MASK  (0x10000000u)
+#define OTP_PINNED_ISPCMDEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_ISPCMDEN_AP_FUSE_VALUE()                                                     \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_ISPCMDEN_AP_FUSE_IDX] & OTP_PINNED_ISPCMDEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_ISPCMDEN_AP_FUSE_SHIFT)
+
+#define OTP_PINNED_FACMDEN_AP_FUSE_IDX   (34u)
+#define OTP_PINNED_FACMDEN_AP_FUSE_SHIFT (29u)
+#define OTP_PINNED_FACMDEN_AP_FUSE_MASK  (0x20000000u)
+#define OTP_PINNED_FACMDEN_AP_FUSE_WIDTH (1u)
+#define OTP_PINNED_FACMDEN_AP_FUSE_VALUE()                                                    \
+    ((OCOTP->OTP_SHADOW[OTP_PINNED_FACMDEN_AP_FUSE_IDX] & OTP_PINNED_FACMDEN_AP_FUSE_MASK) >> \
+     OTP_PINNED_FACMDEN_AP_FUSE_SHIFT)
+
+#define OTP_FORCE_UUID_MATCH_AP_FUSE_IDX   (34u)
+#define OTP_FORCE_UUID_MATCH_AP_FUSE_SHIFT (30u)
+#define OTP_FORCE_UUID_MATCH_AP_FUSE_MASK  (0x40000000u)
+#define OTP_FORCE_UUID_MATCH_AP_FUSE_WIDTH (1u)
+#define OTP_FORCE_UUID_MATCH_AP_FUSE_VALUE()                                                      \
+    ((OCOTP->OTP_SHADOW[OTP_FORCE_UUID_MATCH_AP_FUSE_IDX] & OTP_FORCE_UUID_MATCH_AP_FUSE_MASK) >> \
+     OTP_FORCE_UUID_MATCH_AP_FUSE_SHIFT)
+
+/* Fuse Word PRINCE_GCM_IV_STORE_START_ADDR Index 35 */
+#define OTP_PRINCE_GCM_IV_STORE_START_ADDR_FUSE_IDX (35u)
+
+#define OTP_PRINCE_GCM_IV_STORE_START_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_IV_STORE_START_ADDR_FUSE_IDX])
+/* Fuse Word PRINCE_GCM_IV_STORE_END_ADDR Index 36 */
+#define OTP_PRINCE_GCM_IV_STORE_END_ADDR_FUSE_IDX (36u)
+
+#define OTP_PRINCE_GCM_IV_STORE_END_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_IV_STORE_END_ADDR_FUSE_IDX])
+/* Fuse Word PRINCE_GCM_REG0_START_ADDR Index 37 */
+#define OTP_PRINCE_GCM_REG0_START_ADDR_FUSE_IDX (37u)
+
+#define OTP_PRINCE_GCM_REG0_START_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG0_START_ADDR_FUSE_IDX])
+#define OTP_IPED_REG0_START_ADDR_FUSE_IDX           (37u)
+#define OTP_IPED_REG0_START_ADDR_FUSE_SHIFT         (0u)
+#define OTP_IPED_REG0_START_ADDR_FUSE_MASK          (0xFFFFFFu)
+#define OTP_IPED_REG0_START_ADDR_FUSE_WIDTH         (24u)
+#define OTP_IPED_REG0_START_ADDR_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_IPED_REG0_START_ADDR_FUSE_IDX] & OTP_IPED_REG0_START_ADDR_FUSE_MASK) >> \
+     OTP_IPED_REG0_START_ADDR_FUSE_SHIFT)
+
+#define OTP_ENABLE_REG0_FUSE_IDX   (37u)
+#define OTP_ENABLE_REG0_FUSE_SHIFT (30u)
+#define OTP_ENABLE_REG0_FUSE_MASK  (0xC0000000u)
+#define OTP_ENABLE_REG0_FUSE_WIDTH (2u)
+#define OTP_ENABLE_REG0_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ENABLE_REG0_FUSE_IDX] & OTP_ENABLE_REG0_FUSE_MASK) >> OTP_ENABLE_REG0_FUSE_SHIFT)
+
+/* Fuse Word PRINCE_GCM_REG0_END_ADDR Index 38 */
+#define OTP_PRINCE_GCM_REG0_END_ADDR_FUSE_IDX (38u)
+
+#define OTP_PRINCE_GCM_REG0_END_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG0_END_ADDR_FUSE_IDX])
+
+/* Fuse Word PRINCE_GCM_REG1_START_ADDR Index 39 */
+#define OTP_PRINCE_GCM_REG1_START_ADDR_FUSE_IDX (39u)
+
+#define OTP_PRINCE_GCM_REG1_START_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG1_START_ADDR_FUSE_IDX])
+#define OTP_IPED_REG1_START_ADDR_FUSE_IDX           (39u)
+#define OTP_IPED_REG1_START_ADDR_FUSE_SHIFT         (0u)
+#define OTP_IPED_REG1_START_ADDR_FUSE_MASK          (0xFFFFFFu)
+#define OTP_IPED_REG1_START_ADDR_FUSE_WIDTH         (24u)
+#define OTP_IPED_REG1_START_ADDR_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_IPED_REG1_START_ADDR_FUSE_IDX] & OTP_IPED_REG1_START_ADDR_FUSE_MASK) >> \
+     OTP_IPED_REG1_START_ADDR_FUSE_SHIFT)
+
+#define OTP_ENABLE_REG1_FUSE_IDX   (39u)
+#define OTP_ENABLE_REG1_FUSE_SHIFT (30u)
+#define OTP_ENABLE_REG1_FUSE_MASK  (0xC0000000u)
+#define OTP_ENABLE_REG1_FUSE_WIDTH (2u)
+#define OTP_ENABLE_REG1_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ENABLE_REG1_FUSE_IDX] & OTP_ENABLE_REG1_FUSE_MASK) >> OTP_ENABLE_REG1_FUSE_SHIFT)
+
+/* Fuse Word PRINCE_GCM_REG1_END_ADDR Index 40 */
+#define OTP_PRINCE_GCM_REG1_END_ADDR_FUSE_IDX (40u)
+
+#define OTP_PRINCE_GCM_REG1_END_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG1_END_ADDR_FUSE_IDX])
+
+/* Fuse Word PRINCE_GCM_REG2_START_ADDR Index 41 */
+#define OTP_PRINCE_GCM_REG2_START_ADDR_FUSE_IDX (41u)
+
+#define OTP_PRINCE_GCM_REG2_START_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG2_START_ADDR_FUSE_IDX])
+#define OTP_IPED_REG2_START_ADDR_FUSE_IDX           (41u)
+#define OTP_IPED_REG2_START_ADDR_FUSE_SHIFT         (0u)
+#define OTP_IPED_REG2_START_ADDR_FUSE_MASK          (0xFFFFFFu)
+#define OTP_IPED_REG2_START_ADDR_FUSE_WIDTH         (24u)
+#define OTP_IPED_REG2_START_ADDR_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_IPED_REG2_START_ADDR_FUSE_IDX] & OTP_IPED_REG2_START_ADDR_FUSE_MASK) >> \
+     OTP_IPED_REG2_START_ADDR_FUSE_SHIFT)
+
+#define OTP_ENABLE_REG2_FUSE_IDX   (41u)
+#define OTP_ENABLE_REG2_FUSE_SHIFT (30u)
+#define OTP_ENABLE_REG2_FUSE_MASK  (0xC0000000u)
+#define OTP_ENABLE_REG2_FUSE_WIDTH (2u)
+#define OTP_ENABLE_REG2_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ENABLE_REG2_FUSE_IDX] & OTP_ENABLE_REG2_FUSE_MASK) >> OTP_ENABLE_REG2_FUSE_SHIFT)
+
+/* Fuse Word PRINCE_GCM_REG2_END_ADDR Index 42 */
+#define OTP_PRINCE_GCM_REG2_END_ADDR_FUSE_IDX (42u)
+
+#define OTP_PRINCE_GCM_REG2_END_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG2_END_ADDR_FUSE_IDX])
+
+/* Fuse Word PRINCE_GCM_REG3_START_ADDR Index 43 */
+#define OTP_PRINCE_GCM_REG3_START_ADDR_FUSE_IDX (43u)
+
+#define OTP_PRINCE_GCM_REG3_START_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG3_START_ADDR_FUSE_IDX])
+#define OTP_IPED_REG3_START_ADDR_FUSE_IDX           (43u)
+#define OTP_IPED_REG3_START_ADDR_FUSE_SHIFT         (0u)
+#define OTP_IPED_REG3_START_ADDR_FUSE_MASK          (0xFFFFFFu)
+#define OTP_IPED_REG3_START_ADDR_FUSE_WIDTH         (24u)
+#define OTP_IPED_REG3_START_ADDR_FUSE_VALUE()                                                       \
+    ((OCOTP->OTP_SHADOW[OTP_IPED_REG3_START_ADDR_FUSE_IDX] & OTP_IPED_REG3_START_ADDR_FUSE_MASK) >> \
+     OTP_IPED_REG3_START_ADDR_FUSE_SHIFT)
+
+#define OTP_ENABLE_REG3_FUSE_IDX   (43u)
+#define OTP_ENABLE_REG3_FUSE_SHIFT (30u)
+#define OTP_ENABLE_REG3_FUSE_MASK  (0xC0000000u)
+#define OTP_ENABLE_REG3_FUSE_WIDTH (2u)
+#define OTP_ENABLE_REG3_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_ENABLE_REG3_FUSE_IDX] & OTP_ENABLE_REG3_FUSE_MASK) >> OTP_ENABLE_REG3_FUSE_SHIFT)
+
+/* Fuse Word PRINCE_GCM_REG3_END_ADDR Index 44 */
+#define OTP_PRINCE_GCM_REG3_END_ADDR_FUSE_IDX (44u)
+
+#define OTP_PRINCE_GCM_REG3_END_ADDR_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_PRINCE_GCM_REG3_END_ADDR_FUSE_IDX])
+
+/* Fuse Word LIFE_CYCLE_STATE Index 45 */
+#define OTP_LIFE_CYCLE_STATE_FUSE_IDX (45u)
+
+#define OTP_LIFE_CYCLE_STATE_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_LIFE_CYCLE_STATE_FUSE_IDX])
+#define OTP_LCS_FUSE_IDX                  (45u)
+#define OTP_LCS_FUSE_SHIFT                (0u)
+#define OTP_LCS_FUSE_MASK                 (0xFFu)
+#define OTP_LCS_FUSE_WIDTH                (8u)
+#define OTP_LCS_FUSE_VALUE()              ((OCOTP->OTP_SHADOW[OTP_LCS_FUSE_IDX] & OTP_LCS_FUSE_MASK) >> OTP_LCS_FUSE_SHIFT)
+
+#define OTP_LCS_REDUNDANT_FUSE_IDX   (45u)
+#define OTP_LCS_REDUNDANT_FUSE_SHIFT (8u)
+#define OTP_LCS_REDUNDANT_FUSE_MASK  (0xFF00u)
+#define OTP_LCS_REDUNDANT_FUSE_WIDTH (8u)
+#define OTP_LCS_REDUNDANT_FUSE_VALUE() \
+    ((OCOTP->OTP_SHADOW[OTP_LCS_REDUNDANT_FUSE_IDX] & OTP_LCS_REDUNDANT_FUSE_MASK) >> OTP_LCS_REDUNDANT_FUSE_SHIFT)
+
+/* Fuse Word UUID[31:0] Index 46 */
+#define OTP_UUID_31_0_FUSE_IDX (46u)
+
+/* Fuse Word UUID[63:32] Index 47 */
+#define OTP_UUID_63_32_FUSE_IDX (47u)
+
+/* Fuse Word UUID[95:64] Index 48 */
+#define OTP_UUID_95_64_FUSE_IDX (48u)
+
+/* Fuse Word UUID[127:96] Index 49 */
+#define OTP_UUID_127_96_FUSE_IDX (49u)
+
+/* Fuse Word RO_PUF[31:0] Index 50 */
+#define OTP_RO_PUF_31_0_FUSE_IDX (50u)
+
+/* Fuse Word RO_PUF[63:32] Index 51 */
+#define OTP_RO_PUF_63_32_FUSE_IDX (51u)
+
+/* Fuse Word RO_PUF[95:64] Index 52 */
+#define OTP_RO_PUF_95_64_FUSE_IDX (52u)
+
+/* Fuse Word RO_PUF[127:96] Index 53 */
+#define OTP_RO_PUF_127_96_FUSE_IDX (53u)
+
+/* Fuse Word RO_PUF[159:128] Index 54 */
+#define OTP_RO_PUF_159_128_FUSE_IDX (54u)
+
+/* Fuse Word RO_PUF[191:160] Index 55 */
+#define OTP_RO_PUF_191_160_FUSE_IDX (55u)
+
+/* Fuse Word RO_PUF[223:192] Index 56 */
+#define OTP_RO_PUF_223_192_FUSE_IDX (56u)
+
+/* Fuse Word RO_PUF[255:224] Index 57 */
+#define OTP_RO_PUF_255_224_FUSE_IDX (57u)
+
+/* Fuse Word RO_PUF[287:256] Index 58 */
+#define OTP_RO_PUF_287_256_FUSE_IDX (58u)
+
+/* Fuse Word RO_PUF[319:288] Index 59 */
+#define OTP_RO_PUF_319_288_FUSE_IDX (59u)
+
+/* Fuse Word RO_PUF[351:320] Index 60 */
+#define OTP_RO_PUF_351_320_FUSE_IDX (60u)
+
+/* Fuse Word RO_PUF[383:352] Index 61 */
+#define OTP_RO_PUF_383_352_FUSE_IDX (61u)
+
+/* Fuse Word RO_PUF[415:384] Index 62 */
+#define OTP_RO_PUF_415_384_FUSE_IDX (62u)
+
+/* Fuse Word RO_PUF[447:416] Index 63 */
+#define OTP_RO_PUF_447_416_FUSE_IDX (63u)
+
+/* Fuse Word RO_PUF[479:448] Index 64 */
+#define OTP_RO_PUF_479_448_FUSE_IDX (64u)
+
+/* Fuse Word RO_PUF[511:480] Index 65 */
+#define OTP_RO_PUF_511_480_FUSE_IDX (65u)
+
+/* Fuse Word RO_PUF[543:512] Index 66 */
+#define OTP_RO_PUF_543_512_FUSE_IDX (66u)
+
+/* Fuse Word RO_PUF[575:544] Index 67 */
+#define OTP_RO_PUF_575_544_FUSE_IDX (67u)
+
+/* Fuse Word RO_PUF[607:576] Index 68 */
+#define OTP_RO_PUF_607_576_FUSE_IDX (68u)
+
+/* Fuse Word RO_PUF[639:608] Index 69 */
+#define OTP_RO_PUF_639_608_FUSE_IDX (69u)
+
+/* Fuse Word RO_PUF[671:640] Index 70 */
+#define OTP_RO_PUF_671_640_FUSE_IDX (70u)
+
+/* Fuse Word RO_PUF[703:672] Index 71 */
+#define OTP_RO_PUF_703_672_FUSE_IDX (71u)
+
+/* Fuse Word RO_PUF[735:704] Index 72 */
+#define OTP_RO_PUF_735_704_FUSE_IDX (72u)
+
+/* Fuse Word RO_PUF[767:736] Index 73 */
+#define OTP_RO_PUF_767_736_FUSE_IDX (73u)
+
+/* Fuse Word RO_PUF[799:768] Index 74 */
+#define OTP_RO_PUF_799_768_FUSE_IDX (74u)
+
+/* Fuse Word RO_PUF[831:800] Index 75 */
+#define OTP_RO_PUF_831_800_FUSE_IDX (75u)
+
+/* Fuse Word OTP_SHARE1[31:0] Index 76 */
+#define OTP_OTP_SHARE1_31_0_FUSE_IDX (76u)
+
+#define OTP_OTP_SHARE1_31_0_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_31_0_FUSE_IDX])
+/* Fuse Word OTP_SHARE1[63:32] Index 77 */
+#define OTP_OTP_SHARE1_63_32_FUSE_IDX (77u)
+
+#define OTP_OTP_SHARE1_63_32_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_63_32_FUSE_IDX])
+/* Fuse Word OTP_SHARE1[95:64] Index 78 */
+#define OTP_OTP_SHARE1_95_64_FUSE_IDX (78u)
+
+#define OTP_OTP_SHARE1_95_64_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_95_64_FUSE_IDX])
+/* Fuse Word OTP_SHARE1[127:96] Index 79 */
+#define OTP_OTP_SHARE1_127_96_FUSE_IDX (79u)
+
+#define OTP_OTP_SHARE1_127_96_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_127_96_FUSE_IDX])
+/* Fuse Word OTP_SHARE1[159:128] Index 80 */
+#define OTP_OTP_SHARE1_159_128_FUSE_IDX (80u)
+
+#define OTP_OTP_SHARE1_159_128_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_159_128_FUSE_IDX])
+/* Fuse Word OTP_SHARE1[191:160] Index 81 */
+#define OTP_OTP_SHARE1_191_160_FUSE_IDX (81u)
+
+#define OTP_OTP_SHARE1_191_160_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_191_160_FUSE_IDX])
+/* Fuse Word OTP_SHARE1[223:192] Index 82 */
+#define OTP_OTP_SHARE1_223_192_FUSE_IDX (82u)
+
+#define OTP_OTP_SHARE1_223_192_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_223_192_FUSE_IDX])
+/* Fuse Word OTP_SHARE1[255:224] Index 83 */
+#define OTP_OTP_SHARE1_255_224_FUSE_IDX (83u)
+
+#define OTP_OTP_SHARE1_255_224_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE1_255_224_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[31:0] Index 84 */
+#define OTP_OTP_SHARE2_31_0_FUSE_IDX (84u)
+
+#define OTP_OTP_SHARE2_31_0_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_31_0_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[63:32] Index 85 */
+#define OTP_OTP_SHARE2_63_32_FUSE_IDX (85u)
+
+#define OTP_OTP_SHARE2_63_32_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_63_32_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[95:64] Index 86 */
+#define OTP_OTP_SHARE2_95_64_FUSE_IDX (86u)
+
+#define OTP_OTP_SHARE2_95_64_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_95_64_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[127:96] Index 87 */
+#define OTP_OTP_SHARE2_127_96_FUSE_IDX (87u)
+
+#define OTP_OTP_SHARE2_127_96_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_127_96_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[159:128] Index 88 */
+#define OTP_OTP_SHARE2_159_128_FUSE_IDX (88u)
+
+#define OTP_OTP_SHARE2_159_128_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_159_128_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[191:160] Index 89 */
+#define OTP_OTP_SHARE2_191_160_FUSE_IDX (89u)
+
+#define OTP_OTP_SHARE2_191_160_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_191_160_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[223:192] Index 90 */
+#define OTP_OTP_SHARE2_223_192_FUSE_IDX (90u)
+
+#define OTP_OTP_SHARE2_223_192_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_223_192_FUSE_IDX])
+/* Fuse Word OTP_SHARE2[255:224] Index 91 */
+#define OTP_OTP_SHARE2_255_224_FUSE_IDX (91u)
+
+#define OTP_OTP_SHARE2_255_224_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_OTP_SHARE2_255_224_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[31:0] Index 92 */
+#define OTP_CUST_SK_MK_31_0_FUSE_IDX (92u)
+
+#define OTP_CUST_SK_MK_31_0_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_31_0_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[63:32] Index 93 */
+#define OTP_CUST_SK_MK_63_32_FUSE_IDX (93u)
+
+#define OTP_CUST_SK_MK_63_32_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_63_32_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[95:64] Index 94 */
+#define OTP_CUST_SK_MK_95_64_FUSE_IDX (94u)
+
+#define OTP_CUST_SK_MK_95_64_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_95_64_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[127:96] Index 95 */
+#define OTP_CUST_SK_MK_127_96_FUSE_IDX (95u)
+
+#define OTP_CUST_SK_MK_127_96_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_127_96_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[159:128] Index 96 */
+#define OTP_CUST_SK_MK_159_128_FUSE_IDX (96u)
+
+#define OTP_CUST_SK_MK_159_128_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_159_128_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[191:160] Index 97 */
+#define OTP_CUST_SK_MK_191_160_FUSE_IDX (97u)
+
+#define OTP_CUST_SK_MK_191_160_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_191_160_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[223:192] Index 98 */
+#define OTP_CUST_SK_MK_223_192_FUSE_IDX (98u)
+
+#define OTP_CUST_SK_MK_223_192_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_223_192_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[255:224] Index 99 */
+#define OTP_CUST_SK_MK_255_224_FUSE_IDX (99u)
+
+#define OTP_CUST_SK_MK_255_224_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_255_224_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[287:256] Index 100 */
+#define OTP_CUST_SK_MK_287_256_FUSE_IDX (100u)
+
+#define OTP_CUST_SK_MK_287_256_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_287_256_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[319:288] Index 101 */
+#define OTP_CUST_SK_MK_319_288_FUSE_IDX (101u)
+
+#define OTP_CUST_SK_MK_319_288_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_319_288_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[351:320] Index 102 */
+#define OTP_CUST_SK_MK_351_320_FUSE_IDX (102u)
+
+#define OTP_CUST_SK_MK_351_320_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_351_320_FUSE_IDX])
+/* Fuse Word CUST_SK_MK[383:352] Index 103 */
+#define OTP_CUST_SK_MK_383_352_FUSE_IDX (103u)
+
+#define OTP_CUST_SK_MK_383_352_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_CUST_SK_MK_383_352_FUSE_IDX])
+/* Fuse Word RKTH[383:352] Index 104 */
+#define OTP_RKTH_383_352_FUSE_IDX (104u)
+
+#define OTP_RKTH_383_352_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_383_352_FUSE_IDX])
+/* Fuse Word RKTH[351:320] Index 105 */
+#define OTP_RKTH_351_320_FUSE_IDX (105u)
+
+#define OTP_RKTH_351_320_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_351_320_FUSE_IDX])
+/* Fuse Word RKTH[319:288] Index 106 */
+#define OTP_RKTH_319_288_FUSE_IDX (106u)
+
+#define OTP_RKTH_319_288_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_319_288_FUSE_IDX])
+/* Fuse Word RKTH[287:256] Index 107 */
+#define OTP_RKTH_287_256_FUSE_IDX (107u)
+
+#define OTP_RKTH_287_256_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_287_256_FUSE_IDX])
+/* Fuse Word RKTH[255:224] Index 108 */
+#define OTP_RKTH_255_224_FUSE_IDX (108u)
+
+#define OTP_RKTH_255_224_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_255_224_FUSE_IDX])
+/* Fuse Word RKTH[223:192] Index 109 */
+#define OTP_RKTH_223_192_FUSE_IDX (109u)
+
+#define OTP_RKTH_223_192_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_223_192_FUSE_IDX])
+/* Fuse Word RKTH[191:160] Index 110 */
+#define OTP_RKTH_191_160_FUSE_IDX (110u)
+
+#define OTP_RKTH_191_160_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_191_160_FUSE_IDX])
+/* Fuse Word RKTH[159:128] Index 111 */
+#define OTP_RKTH_159_128_FUSE_IDX (111u)
+
+#define OTP_RKTH_159_128_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_159_128_FUSE_IDX])
+/* Fuse Word RKTH[127:96] Index 112 */
+#define OTP_RKTH_127_96_FUSE_IDX (112u)
+
+#define OTP_RKTH_127_96_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_127_96_FUSE_IDX])
+/* Fuse Word RKTH[95:64] Index 113 */
+#define OTP_RKTH_95_64_FUSE_IDX (113u)
+
+#define OTP_RKTH_95_64_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_95_64_FUSE_IDX])
+/* Fuse Word RKTH[63:32] Index 114 */
+#define OTP_RKTH_63_32_FUSE_IDX (114u)
+
+#define OTP_RKTH_63_32_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_63_32_FUSE_IDX])
+/* Fuse Word RKTH[31:0] Index 115 */
+#define OTP_RKTH_31_0_FUSE_IDX (115u)
+
+#define OTP_RKTH_31_0_FUSE_VALUE() (OCOTP->OTP_SHADOW[OTP_RKTH_31_0_FUSE_IDX])
+/* Fuse Word NXP_WIFI_SK_MK[31:0] Index 116 */
+#define OTP_NXP_WIFI_SK_MK_31_0_FUSE_IDX (116u)
+
+/* Fuse Word NXP_WIFI_SK_MK[63:32] Index 117 */
+#define OTP_NXP_WIFI_SK_MK_63_32_FUSE_IDX (117u)
+
+/* Fuse Word NXP_WIFI_SK_MK[95:64] Index 118 */
+#define OTP_NXP_WIFI_SK_MK_95_64_FUSE_IDX (118u)
+
+/* Fuse Word NXP_WIFI_SK_MK[127:96] Index 119 */
+#define OTP_NXP_WIFI_SK_MK_127_96_FUSE_IDX (119u)
+
+/* Fuse Word NXP_WIFI_SK_MK[159:128] Index 120 */
+#define OTP_NXP_WIFI_SK_MK_159_128_FUSE_IDX (120u)
+
+/* Fuse Word NXP_WIFI_SK_MK[191:160] Index 121 */
+#define OTP_NXP_WIFI_SK_MK_191_160_FUSE_IDX (121u)
+
+/* Fuse Word NXP_WIFI_SK_MK[223:192] Index 122 */
+#define OTP_NXP_WIFI_SK_MK_223_192_FUSE_IDX (122u)
+
+/* Fuse Word NXP_WIFI_SK_MK[255:224] Index 123 */
+#define OTP_NXP_WIFI_SK_MK_255_224_FUSE_IDX (123u)
+
+/* Fuse Word NXP_WIFI_SK_MK[287:256] Index 124 */
+#define OTP_NXP_WIFI_SK_MK_287_256_FUSE_IDX (124u)
+
+/* Fuse Word NXP_WIFI_SK_MK[319:288] Index 125 */
+#define OTP_NXP_WIFI_SK_MK_319_288_FUSE_IDX (125u)
+
+/* Fuse Word NXP_WIFI_SK_MK[351:320] Index 126 */
+#define OTP_NXP_WIFI_SK_MK_351_320_FUSE_IDX (126u)
+
+/* Fuse Word NXP_WIFI_SK_MK[383:352] Index 127 */
+#define OTP_NXP_WIFI_SK_MK_383_352_FUSE_IDX (127u)
+
+/* Fuse Word DTRNG_CFG[31:0] Index 128 */
+#define OTP_DTRNG_CFG_31_0_FUSE_IDX (128u)
+
+/* Fuse Word DTRNG_CFG[63:32] Index 129 */
+#define OTP_DTRNG_CFG_63_32_FUSE_IDX (129u)
+
+/* Fuse Word DTRNG_CFG[95:64] Index 130 */
+#define OTP_DTRNG_CFG_95_64_FUSE_IDX (130u)
+
+/* Fuse Word DTRNG_CFG[127:96] Index 131 */
+#define OTP_DTRNG_CFG_127_96_FUSE_IDX (131u)
+
+/* Fuse Word DTRNG_CFG[159:128] Index 132 */
+#define OTP_DTRNG_CFG_159_128_FUSE_IDX (132u)
+
+/* Fuse Word DTRNG_CFG[191:160] Index 133 */
+#define OTP_DTRNG_CFG_191_160_FUSE_IDX (133u)
+
+/* Fuse Word DTRNG_CFG[223:192] Index 134 */
+#define OTP_DTRNG_CFG_223_192_FUSE_IDX (134u)
+
+/* Fuse Word DTRNG_CFG[255:224] Index 135 */
+#define OTP_DTRNG_CFG_255_224_FUSE_IDX (135u)
+
+/* Fuse Word DTRNG_CFG[287:256] Index 136 */
+#define OTP_DTRNG_CFG_287_256_FUSE_IDX (136u)
+
+/* Fuse Word DTRNG_CFG[319:288] Index 137 */
+#define OTP_DTRNG_CFG_319_288_FUSE_IDX (137u)
+
+/* Fuse Word DTRNG_CFG[351:320] Index 138 */
+#define OTP_DTRNG_CFG_351_320_FUSE_IDX (138u)
+
+/* Fuse Word DTRNG_CFG[383:352] Index 139 */
+#define OTP_DTRNG_CFG_383_352_FUSE_IDX (139u)
+
+/* Fuse Word DTRNG_CFG[415:384] Index 140 */
+#define OTP_DTRNG_CFG_415_384_FUSE_IDX (140u)
+
+/* Fuse Word DTRNG_CFG[447:416] Index 141 */
+#define OTP_DTRNG_CFG_447_416_FUSE_IDX (141u)
+
+/* Fuse Word DTRNG_CFG[479:448] Index 142 */
+#define OTP_DTRNG_CFG_479_448_FUSE_IDX (142u)
+
+/* Fuse Word DTRNG_CFG[511:480] Index 143 */
+#define OTP_DTRNG_CFG_511_480_FUSE_IDX (143u)
+
+/* Fuse Word DTRNG_CFG[543:512] Index 144 */
+#define OTP_DTRNG_CFG_543_512_FUSE_IDX (144u)
+
+/* Fuse Word DTRNG_CFG[575:544] Index 145 */
+#define OTP_DTRNG_CFG_575_544_FUSE_IDX (145u)
+
+/* Fuse Word DTRNG_CFG[607:576] Index 146 */
+#define OTP_DTRNG_CFG_607_576_FUSE_IDX (146u)
+
+/* Fuse Word DTRNG_CFG[639:608] Index 147 */
+#define OTP_DTRNG_CFG_639_608_FUSE_IDX (147u)
+
+/* Fuse Word DTRNG_CFG[671:640] Index 148 */
+#define OTP_DTRNG_CFG_671_640_FUSE_IDX (148u)
+
+/* Fuse Word GDET_CFG[31:0] Index 149 */
+#define OTP_GDET_CFG_31_0_FUSE_IDX (149u)
+
+/* Fuse Word GDET_CFG[63:32] Index 150 */
+#define OTP_GDET_CFG_63_32_FUSE_IDX (150u)
+
+/* Fuse Word GDET_CFG[95:64] Index 151 */
+#define OTP_GDET_CFG_95_64_FUSE_IDX (151u)
+
+/* Fuse Word GDET_CFG[127:96] Index 152 */
+#define OTP_GDET_CFG_127_96_FUSE_IDX (152u)
+
+/* Fuse Word GDET_CFG[159:128] Index 153 */
+#define OTP_GDET_CFG_159_128_FUSE_IDX (153u)
+
+/* Fuse Word GDET_CFG[191:160] Index 154 */
+#define OTP_GDET_CFG_191_160_FUSE_IDX (154u)
+
+/* Fuse Word GDET_TRIM0 Index 155 */
+#define OTP_GDET_TRIM0_FUSE_IDX (155u)
+
+#define OTP_GDET_TRIM0_31_0_FUSE_IDX   (155u)
+#define OTP_GDET_TRIM0_31_0_FUSE_SHIFT (0u)
+#define OTP_GDET_TRIM0_31_0_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_GDET_TRIM0_31_0_FUSE_WIDTH (32u)
+
+/* Fuse Word USER_ECC_0 Index 156 */
+#define OTP_USER_ECC_0_FUSE_IDX (156u)
+
+/* Fuse Word USER_ECC_1 Index 157 */
+#define OTP_USER_ECC_1_FUSE_IDX (157u)
+
+/* Fuse Word USER_ECC_2 Index 158 */
+#define OTP_USER_ECC_2_FUSE_IDX (158u)
+
+/* Fuse Word USER_ECC_3 Index 159 */
+#define OTP_USER_ECC_3_FUSE_IDX (159u)
+
+/* Fuse Word USER_ECC_4 Index 160 */
+#define OTP_USER_ECC_4_FUSE_IDX (160u)
+
+/* Fuse Word USER_ECC_5 Index 161 */
+#define OTP_USER_ECC_5_FUSE_IDX (161u)
+
+/* Fuse Word USER_ECC_6 Index 162 */
+#define OTP_USER_ECC_6_FUSE_IDX (162u)
+
+/* Fuse Word USER_ECC_7 Index 163 */
+#define OTP_USER_ECC_7_FUSE_IDX (163u)
+
+/* Fuse Word ROM_PATCH_DATA0 Index 164 */
+#define OTP_ROM_PATCH_DATA0_FUSE_IDX (164u)
+
+/* Fuse Word ROM_PATCH_DATA1 Index 165 */
+#define OTP_ROM_PATCH_DATA1_FUSE_IDX (165u)
+
+/* Fuse Word ROM_PATCH_DATA2 Index 166 */
+#define OTP_ROM_PATCH_DATA2_FUSE_IDX (166u)
+
+/* Fuse Word ROM_PATCH_DATA3 Index 167 */
+#define OTP_ROM_PATCH_DATA3_FUSE_IDX (167u)
+
+/* Fuse Word ROM_PATCH_DATA4 Index 168 */
+#define OTP_ROM_PATCH_DATA4_FUSE_IDX (168u)
+
+/* Fuse Word ROM_PATCH_DATA5 Index 169 */
+#define OTP_ROM_PATCH_DATA5_FUSE_IDX (169u)
+
+/* Fuse Word ROM_PATCH_DATA6 Index 170 */
+#define OTP_ROM_PATCH_DATA6_FUSE_IDX (170u)
+
+/* Fuse Word ROM_PATCH_DATA7 Index 171 */
+#define OTP_ROM_PATCH_DATA7_FUSE_IDX (171u)
+
+/* Fuse Word ROM_PATCH_DATA8 Index 172 */
+#define OTP_ROM_PATCH_DATA8_FUSE_IDX (172u)
+
+/* Fuse Word ROM_PATCH_DATA9 Index 173 */
+#define OTP_ROM_PATCH_DATA9_FUSE_IDX (173u)
+
+/* Fuse Word ROM_PATCH_DATA10 Index 174 */
+#define OTP_ROM_PATCH_DATA10_FUSE_IDX (174u)
+
+/* Fuse Word ROM_PATCH_DATA11 Index 175 */
+#define OTP_ROM_PATCH_DATA11_FUSE_IDX (175u)
+
+/* Fuse Word ROM_PATCH_DATA12 Index 176 */
+#define OTP_ROM_PATCH_DATA12_FUSE_IDX (176u)
+
+/* Fuse Word ROM_PATCH_DATA13 Index 177 */
+#define OTP_ROM_PATCH_DATA13_FUSE_IDX (177u)
+
+/* Fuse Word ROM_PATCH_DATA14 Index 178 */
+#define OTP_ROM_PATCH_DATA14_FUSE_IDX (178u)
+
+/* Fuse Word ROM_PATCH_DATA15 Index 179 */
+#define OTP_ROM_PATCH_DATA15_FUSE_IDX (179u)
+
+/* Fuse Word ROM_PATCH_DATA16 Index 180 */
+#define OTP_ROM_PATCH_DATA16_FUSE_IDX (180u)
+
+/* Fuse Word ROM_PATCH_DATA17 Index 181 */
+#define OTP_ROM_PATCH_DATA17_FUSE_IDX (181u)
+
+/* Fuse Word ROM_PATCH_DATA18 Index 182 */
+#define OTP_ROM_PATCH_DATA18_FUSE_IDX (182u)
+
+/* Fuse Word ROM_PATCH_DATA19 Index 183 */
+#define OTP_ROM_PATCH_DATA19_FUSE_IDX (183u)
+
+/* Fuse Word ROM_PATCH_DATA20 Index 184 */
+#define OTP_ROM_PATCH_DATA20_FUSE_IDX (184u)
+
+/* Fuse Word ROM_PATCH_DATA21 Index 185 */
+#define OTP_ROM_PATCH_DATA21_FUSE_IDX (185u)
+
+/* Fuse Word ROM_PATCH_DATA22 Index 186 */
+#define OTP_ROM_PATCH_DATA22_FUSE_IDX (186u)
+
+/* Fuse Word ROM_PATCH_DATA23 Index 187 */
+#define OTP_ROM_PATCH_DATA23_FUSE_IDX (187u)
+
+/* Fuse Word ROM_PATCH_DATA24 Index 188 */
+#define OTP_ROM_PATCH_DATA24_FUSE_IDX (188u)
+
+/* Fuse Word ROM_PATCH_DATA25 Index 189 */
+#define OTP_ROM_PATCH_DATA25_FUSE_IDX (189u)
+
+/* Fuse Word ROM_PATCH_DATA26 Index 190 */
+#define OTP_ROM_PATCH_DATA26_FUSE_IDX (190u)
+
+/* Fuse Word ROM_PATCH_DATA27 Index 191 */
+#define OTP_ROM_PATCH_DATA27_FUSE_IDX (191u)
+
+/* Fuse Word ROM_PATCH_DATA28 Index 192 */
+#define OTP_ROM_PATCH_DATA28_FUSE_IDX (192u)
+
+/* Fuse Word ROM_PATCH_DATA29 Index 193 */
+#define OTP_ROM_PATCH_DATA29_FUSE_IDX (193u)
+
+/* Fuse Word ROM_PATCH_DATA30 Index 194 */
+#define OTP_ROM_PATCH_DATA30_FUSE_IDX (194u)
+
+/* Fuse Word ROM_PATCH_DATA31 Index 195 */
+#define OTP_ROM_PATCH_DATA31_FUSE_IDX (195u)
+
+/* Fuse Word ROM_PATCH_DATA32 Index 196 */
+#define OTP_ROM_PATCH_DATA32_FUSE_IDX (196u)
+
+/* Fuse Word ROM_PATCH_DATA33 Index 197 */
+#define OTP_ROM_PATCH_DATA33_FUSE_IDX (197u)
+
+/* Fuse Word ROM_PATCH_DATA34 Index 198 */
+#define OTP_ROM_PATCH_DATA34_FUSE_IDX (198u)
+
+/* Fuse Word ROM_PATCH_DATA35 Index 199 */
+#define OTP_ROM_PATCH_DATA35_FUSE_IDX (199u)
+
+/* Fuse Word ROM_PATCH_DATA36 Index 200 */
+#define OTP_ROM_PATCH_DATA36_FUSE_IDX (200u)
+
+/* Fuse Word ROM_PATCH_DATA37 Index 201 */
+#define OTP_ROM_PATCH_DATA37_FUSE_IDX (201u)
+
+/* Fuse Word ROM_PATCH_DATA38 Index 202 */
+#define OTP_ROM_PATCH_DATA38_FUSE_IDX (202u)
+
+/* Fuse Word ROM_PATCH_DATA39 Index 203 */
+#define OTP_ROM_PATCH_DATA39_FUSE_IDX (203u)
+
+/* Fuse Word ROM_PATCH_DATA40 Index 204 */
+#define OTP_ROM_PATCH_DATA40_FUSE_IDX (204u)
+
+/* Fuse Word ROM_PATCH_DATA41 Index 205 */
+#define OTP_ROM_PATCH_DATA41_FUSE_IDX (205u)
+
+/* Fuse Word ROM_PATCH_DATA42 Index 206 */
+#define OTP_ROM_PATCH_DATA42_FUSE_IDX (206u)
+
+/* Fuse Word ROM_PATCH_DATA43 Index 207 */
+#define OTP_ROM_PATCH_DATA43_FUSE_IDX (207u)
+
+/* Fuse Word ROM_PATCH_DATA44 Index 208 */
+#define OTP_ROM_PATCH_DATA44_FUSE_IDX (208u)
+
+/* Fuse Word ROM_PATCH_DATA45 Index 209 */
+#define OTP_ROM_PATCH_DATA45_FUSE_IDX (209u)
+
+/* Fuse Word ROM_PATCH_DATA46 Index 210 */
+#define OTP_ROM_PATCH_DATA46_FUSE_IDX (210u)
+
+/* Fuse Word ROM_PATCH_DATA47 Index 211 */
+#define OTP_ROM_PATCH_DATA47_FUSE_IDX (211u)
+
+/* Fuse Word ROM_PATCH_DATA48 Index 212 */
+#define OTP_ROM_PATCH_DATA48_FUSE_IDX (212u)
+
+/* Fuse Word ROM_PATCH_DATA49 Index 213 */
+#define OTP_ROM_PATCH_DATA49_FUSE_IDX (213u)
+
+/* Fuse Word ROM_PATCH_DATA50 Index 214 */
+#define OTP_ROM_PATCH_DATA50_FUSE_IDX (214u)
+
+/* Fuse Word ROM_PATCH_DATA51 Index 215 */
+#define OTP_ROM_PATCH_DATA51_FUSE_IDX (215u)
+
+/* Fuse Word ROM_PATCH_DATA52 Index 216 */
+#define OTP_ROM_PATCH_DATA52_FUSE_IDX (216u)
+
+/* Fuse Word ROM_PATCH_DATA53 Index 217 */
+#define OTP_ROM_PATCH_DATA53_FUSE_IDX (217u)
+
+/* Fuse Word ROM_PATCH_DATA54 Index 218 */
+#define OTP_ROM_PATCH_DATA54_FUSE_IDX (218u)
+
+/* Fuse Word ROM_PATCH_DATA55 Index 219 */
+#define OTP_ROM_PATCH_DATA55_FUSE_IDX (219u)
+
+/* Fuse Word ROM_PATCH_DATA56 Index 220 */
+#define OTP_ROM_PATCH_DATA56_FUSE_IDX (220u)
+
+/* Fuse Word ROM_PATCH_DATA57 Index 221 */
+#define OTP_ROM_PATCH_DATA57_FUSE_IDX (221u)
+
+/* Fuse Word ROM_PATCH_DATA58 Index 222 */
+#define OTP_ROM_PATCH_DATA58_FUSE_IDX (222u)
+
+/* Fuse Word ROM_PATCH_DATA59 Index 223 */
+#define OTP_ROM_PATCH_DATA59_FUSE_IDX (223u)
+
+/* Fuse Word ROM_PATCH_DATA60 Index 224 */
+#define OTP_ROM_PATCH_DATA60_FUSE_IDX (224u)
+
+/* Fuse Word ROM_PATCH_DATA61 Index 225 */
+#define OTP_ROM_PATCH_DATA61_FUSE_IDX (225u)
+
+/* Fuse Word ROM_PATCH_DATA62 Index 226 */
+#define OTP_ROM_PATCH_DATA62_FUSE_IDX (226u)
+
+/* Fuse Word ROM_PATCH_DATA63 Index 227 */
+#define OTP_ROM_PATCH_DATA63_FUSE_IDX (227u)
+
+/* Fuse Word ROM_PATCH_DATA64 Index 228 */
+#define OTP_ROM_PATCH_DATA64_FUSE_IDX (228u)
+
+/* Fuse Word ROM_PATCH_DATA65 Index 229 */
+#define OTP_ROM_PATCH_DATA65_FUSE_IDX (229u)
+
+/* Fuse Word ROM_PATCH_DATA66 Index 230 */
+#define OTP_ROM_PATCH_DATA66_FUSE_IDX (230u)
+
+/* Fuse Word ROM_PATCH_DATA67 Index 231 */
+#define OTP_ROM_PATCH_DATA67_FUSE_IDX (231u)
+
+/* Fuse Word ROM_PATCH_DATA68 Index 232 */
+#define OTP_ROM_PATCH_DATA68_FUSE_IDX (232u)
+
+/* Fuse Word ROM_PATCH_DATA69 Index 233 */
+#define OTP_ROM_PATCH_DATA69_FUSE_IDX (233u)
+
+/* Fuse Word ROM_PATCH_DATA70 Index 234 */
+#define OTP_ROM_PATCH_DATA70_FUSE_IDX (234u)
+
+/* Fuse Word ROM_PATCH_DATA71 Index 235 */
+#define OTP_ROM_PATCH_DATA71_FUSE_IDX (235u)
+
+/* Fuse Word ROM_PATCH_DATA72 Index 236 */
+#define OTP_ROM_PATCH_DATA72_FUSE_IDX (236u)
+
+/* Fuse Word ROM_PATCH_DATA73 Index 237 */
+#define OTP_ROM_PATCH_DATA73_FUSE_IDX (237u)
+
+/* Fuse Word ROM_PATCH_DATA74 Index 238 */
+#define OTP_ROM_PATCH_DATA74_FUSE_IDX (238u)
+
+/* Fuse Word ROM_PATCH_DATA75 Index 239 */
+#define OTP_ROM_PATCH_DATA75_FUSE_IDX (239u)
+
+/* Fuse Word ROM_PATCH_DATA76 Index 240 */
+#define OTP_ROM_PATCH_DATA76_FUSE_IDX (240u)
+
+/* Fuse Word ROM_PATCH_DATA77 Index 241 */
+#define OTP_ROM_PATCH_DATA77_FUSE_IDX (241u)
+
+/* Fuse Word ROM_PATCH_DATA78 Index 242 */
+#define OTP_ROM_PATCH_DATA78_FUSE_IDX (242u)
+
+/* Fuse Word ROM_PATCH_DATA79 Index 243 */
+#define OTP_ROM_PATCH_DATA79_FUSE_IDX (243u)
+
+/* Fuse Word ROM_PATCH_DATA80 Index 244 */
+#define OTP_ROM_PATCH_DATA80_FUSE_IDX (244u)
+
+/* Fuse Word ROM_PATCH_DATA81 Index 245 */
+#define OTP_ROM_PATCH_DATA81_FUSE_IDX (245u)
+
+/* Fuse Word ROM_PATCH_DATA82 Index 246 */
+#define OTP_ROM_PATCH_DATA82_FUSE_IDX (246u)
+
+/* Fuse Word ROM_PATCH_DATA83 Index 247 */
+#define OTP_ROM_PATCH_DATA83_FUSE_IDX (247u)
+
+/* Fuse Word ROM_PATCH_DATA84 Index 248 */
+#define OTP_ROM_PATCH_DATA84_FUSE_IDX (248u)
+
+/* Fuse Word ROM_PATCH_DATA85 Index 249 */
+#define OTP_ROM_PATCH_DATA85_FUSE_IDX (249u)
+
+/* Fuse Word ROM_PATCH_DATA86 Index 250 */
+#define OTP_ROM_PATCH_DATA86_FUSE_IDX (250u)
+
+/* Fuse Word ROM_PATCH_DATA87 Index 251 */
+#define OTP_ROM_PATCH_DATA87_FUSE_IDX (251u)
+
+/* Fuse Word ROM_PATCH_DATA88 Index 252 */
+#define OTP_ROM_PATCH_DATA88_FUSE_IDX (252u)
+
+/* Fuse Word ROM_PATCH_DATA89 Index 253 */
+#define OTP_ROM_PATCH_DATA89_FUSE_IDX (253u)
+
+/* Fuse Word ROM_PATCH_DATA90 Index 254 */
+#define OTP_ROM_PATCH_DATA90_FUSE_IDX (254u)
+
+/* Fuse Word ROM_PATCH_DATA91 Index 255 */
+#define OTP_ROM_PATCH_DATA91_FUSE_IDX (255u)
+
+/* Fuse Word ROM_PATCH_DATA92 Index 256 */
+#define OTP_ROM_PATCH_DATA92_FUSE_IDX (256u)
+
+/* Fuse Word ROM_PATCH_DATA93 Index 257 */
+#define OTP_ROM_PATCH_DATA93_FUSE_IDX (257u)
+
+/* Fuse Word ROM_PATCH_DATA94 Index 258 */
+#define OTP_ROM_PATCH_DATA94_FUSE_IDX (258u)
+
+/* Fuse Word ROM_PATCH_DATA95 Index 259 */
+#define OTP_ROM_PATCH_DATA95_FUSE_IDX (259u)
+
+/* Fuse Word ROM_PATCH_DATA96 Index 260 */
+#define OTP_ROM_PATCH_DATA96_FUSE_IDX (260u)
+
+/* Fuse Word ROM_PATCH_DATA97 Index 261 */
+#define OTP_ROM_PATCH_DATA97_FUSE_IDX (261u)
+
+/* Fuse Word ROM_PATCH_DATA98 Index 262 */
+#define OTP_ROM_PATCH_DATA98_FUSE_IDX (262u)
+
+/* Fuse Word ROM_PATCH_DATA99 Index 263 */
+#define OTP_ROM_PATCH_DATA99_FUSE_IDX (263u)
+
+/* Fuse Word ROM_PATCH_DATA100 Index 264 */
+#define OTP_ROM_PATCH_DATA100_FUSE_IDX (264u)
+
+/* Fuse Word ROM_PATCH_DATA101 Index 265 */
+#define OTP_ROM_PATCH_DATA101_FUSE_IDX (265u)
+
+/* Fuse Word ROM_PATCH_DATA102 Index 266 */
+#define OTP_ROM_PATCH_DATA102_FUSE_IDX (266u)
+
+/* Fuse Word ROM_PATCH_DATA103 Index 267 */
+#define OTP_ROM_PATCH_DATA103_FUSE_IDX (267u)
+
+/* Fuse Word ROM_PATCH_DATA104 Index 268 */
+#define OTP_ROM_PATCH_DATA104_FUSE_IDX (268u)
+
+/* Fuse Word ROM_PATCH_DATA105 Index 269 */
+#define OTP_ROM_PATCH_DATA105_FUSE_IDX (269u)
+
+/* Fuse Word ROM_PATCH_DATA106 Index 270 */
+#define OTP_ROM_PATCH_DATA106_FUSE_IDX (270u)
+
+/* Fuse Word ROM_PATCH_DATA107 Index 271 */
+#define OTP_ROM_PATCH_DATA107_FUSE_IDX (271u)
+
+/* Fuse Word ROM_PATCH_DATA108 Index 272 */
+#define OTP_ROM_PATCH_DATA108_FUSE_IDX (272u)
+
+/* Fuse Word ROM_PATCH_DATA109 Index 273 */
+#define OTP_ROM_PATCH_DATA109_FUSE_IDX (273u)
+
+/* Fuse Word ROM_PATCH_DATA110 Index 274 */
+#define OTP_ROM_PATCH_DATA110_FUSE_IDX (274u)
+
+/* Fuse Word ROM_PATCH_DATA111 Index 275 */
+#define OTP_ROM_PATCH_DATA111_FUSE_IDX (275u)
+
+/* Fuse Word ROM_PATCH_DATA112 Index 276 */
+#define OTP_ROM_PATCH_DATA112_FUSE_IDX (276u)
+
+/* Fuse Word ROM_PATCH_DATA113 Index 277 */
+#define OTP_ROM_PATCH_DATA113_FUSE_IDX (277u)
+
+/* Fuse Word ROM_PATCH_DATA114 Index 278 */
+#define OTP_ROM_PATCH_DATA114_FUSE_IDX (278u)
+
+/* Fuse Word ROM_PATCH_DATA115 Index 279 */
+#define OTP_ROM_PATCH_DATA115_FUSE_IDX (279u)
+
+/* Fuse Word ROM_PATCH_DATA116 Index 280 */
+#define OTP_ROM_PATCH_DATA116_FUSE_IDX (280u)
+
+/* Fuse Word ROM_PATCH_DATA117 Index 281 */
+#define OTP_ROM_PATCH_DATA117_FUSE_IDX (281u)
+
+/* Fuse Word ROM_PATCH_DATA118 Index 282 */
+#define OTP_ROM_PATCH_DATA118_FUSE_IDX (282u)
+
+/* Fuse Word ROM_PATCH_DATA119 Index 283 */
+#define OTP_ROM_PATCH_DATA119_FUSE_IDX (283u)
+
+/* Fuse Word ROM_PATCH_DATA120 Index 284 */
+#define OTP_ROM_PATCH_DATA120_FUSE_IDX (284u)
+
+/* Fuse Word ROM_PATCH_DATA121 Index 285 */
+#define OTP_ROM_PATCH_DATA121_FUSE_IDX (285u)
+
+/* Fuse Word ROM_PATCH_DATA122 Index 286 */
+#define OTP_ROM_PATCH_DATA122_FUSE_IDX (286u)
+
+/* Fuse Word ROM_PATCH_DATA123 Index 287 */
+#define OTP_ROM_PATCH_DATA123_FUSE_IDX (287u)
+
+/* Fuse Word ROM_PATCH_DATA124 Index 288 */
+#define OTP_ROM_PATCH_DATA124_FUSE_IDX (288u)
+
+/* Fuse Word ROM_PATCH_DATA125 Index 289 */
+#define OTP_ROM_PATCH_DATA125_FUSE_IDX (289u)
+
+/* Fuse Word ROM_PATCH_DATA126 Index 290 */
+#define OTP_ROM_PATCH_DATA126_FUSE_IDX (290u)
+
+/* Fuse Word ROM_PATCH_DATA127 Index 291 */
+#define OTP_ROM_PATCH_DATA127_FUSE_IDX (291u)
+
+/* Fuse Word CERTIFICATE0[31:0] Index 292 */
+#define OTP_CERTIFICATE0_31_0_FUSE_IDX (292u)
+
+/* Fuse Word CERTIFICATE0[63:32] Index 293 */
+#define OTP_CERTIFICATE0_63_32_FUSE_IDX (293u)
+
+/* Fuse Word CERTIFICATE0[95:64] Index 294 */
+#define OTP_CERTIFICATE0_95_64_FUSE_IDX (294u)
+
+/* Fuse Word CERTIFICATE0[127:96] Index 295 */
+#define OTP_CERTIFICATE0_127_96_FUSE_IDX (295u)
+
+/* Fuse Word CERTIFICATE0[159:128] Index 296 */
+#define OTP_CERTIFICATE0_159_128_FUSE_IDX (296u)
+
+/* Fuse Word CERTIFICATE0[191:160] Index 297 */
+#define OTP_CERTIFICATE0_191_160_FUSE_IDX (297u)
+
+/* Fuse Word CERTIFICATE0[223:192] Index 298 */
+#define OTP_CERTIFICATE0_223_192_FUSE_IDX (298u)
+
+/* Fuse Word CERTIFICATE0[255:224] Index 299 */
+#define OTP_CERTIFICATE0_255_224_FUSE_IDX (299u)
+
+/* Fuse Word CERTIFICATE0[287:256] Index 300 */
+#define OTP_CERTIFICATE0_287_256_FUSE_IDX (300u)
+
+/* Fuse Word CERTIFICATE0[319:288] Index 301 */
+#define OTP_CERTIFICATE0_319_288_FUSE_IDX (301u)
+
+/* Fuse Word CERTIFICATE0[351:320] Index 302 */
+#define OTP_CERTIFICATE0_351_320_FUSE_IDX (302u)
+
+/* Fuse Word CERTIFICATE0[383:352] Index 303 */
+#define OTP_CERTIFICATE0_383_352_FUSE_IDX (303u)
+
+/* Fuse Word CERTIFICATE0[415:384] Index 304 */
+#define OTP_CERTIFICATE0_415_384_FUSE_IDX (304u)
+
+/* Fuse Word CERTIFICATE0[447:416] Index 305 */
+#define OTP_CERTIFICATE0_447_416_FUSE_IDX (305u)
+
+/* Fuse Word CERTIFICATE0[479:448] Index 306 */
+#define OTP_CERTIFICATE0_479_448_FUSE_IDX (306u)
+
+/* Fuse Word CERTIFICATE0[511:480] Index 307 */
+#define OTP_CERTIFICATE0_511_480_FUSE_IDX (307u)
+
+/* Fuse Word CERTIFICATE0[543:512] Index 308 */
+#define OTP_CERTIFICATE0_543_512_FUSE_IDX (308u)
+
+/* Fuse Word CERTIFICATE0[575:544] Index 309 */
+#define OTP_CERTIFICATE0_575_544_FUSE_IDX (309u)
+
+/* Fuse Word CERTIFICATE0[607:576] Index 310 */
+#define OTP_CERTIFICATE0_607_576_FUSE_IDX (310u)
+
+/* Fuse Word CERTIFICATE0[639:608] Index 311 */
+#define OTP_CERTIFICATE0_639_608_FUSE_IDX (311u)
+
+/* Fuse Word CERTIFICATE0[671:640] Index 312 */
+#define OTP_CERTIFICATE0_671_640_FUSE_IDX (312u)
+
+/* Fuse Word CERTIFICATE0[703:672] Index 313 */
+#define OTP_CERTIFICATE0_703_672_FUSE_IDX (313u)
+
+/* Fuse Word CERTIFICATE0[735:704] Index 314 */
+#define OTP_CERTIFICATE0_735_704_FUSE_IDX (314u)
+
+/* Fuse Word CRC0 Index 360 */
+#define OTP_CRC0_FUSE_IDX (360u)
+
+/* Fuse Word CRC1 Index 361 */
+#define OTP_CRC1_FUSE_IDX (361u)
+
+/* Fuse Word CRC2 Index 362 */
+#define OTP_CRC2_FUSE_IDX (362u)
+
+/* Fuse Word CRC3 Index 363 */
+#define OTP_CRC3_FUSE_IDX (363u)
+
+/* Fuse Word CRC4 Index 364 */
+#define OTP_CRC4_FUSE_IDX (364u)
+
+/* Fuse Word CRC5 Index 365 */
+#define OTP_CRC5_FUSE_IDX (365u)
+
+/* Fuse Word CRC6 Index 366 */
+#define OTP_CRC6_FUSE_IDX (366u)
+
+/* Fuse Word CRC7 Index 367 */
+#define OTP_CRC7_FUSE_IDX (367u)
+
+/* Fuse Word NT_FW_VER0 Index 368 */
+#define OTP_NT_FW_VER0_FUSE_IDX (368u)
+
+#define OTP_NT_FW_VER_15_0_FUSE_IDX   (368u)
+#define OTP_NT_FW_VER_15_0_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_15_0_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_15_0_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER1 Index 369 */
+#define OTP_NT_FW_VER1_FUSE_IDX (369u)
+
+#define OTP_NT_FW_VER_31_16_FUSE_IDX   (369u)
+#define OTP_NT_FW_VER_31_16_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_31_16_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_31_16_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER2 Index 370 */
+#define OTP_NT_FW_VER2_FUSE_IDX (370u)
+
+#define OTP_NT_FW_VER_47_32_FUSE_IDX   (370u)
+#define OTP_NT_FW_VER_47_32_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_47_32_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_47_32_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER3 Index 371 */
+#define OTP_NT_FW_VER3_FUSE_IDX (371u)
+
+#define OTP_NT_FW_VER_63_48_FUSE_IDX   (371u)
+#define OTP_NT_FW_VER_63_48_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_63_48_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_63_48_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER4 Index 372 */
+#define OTP_NT_FW_VER4_FUSE_IDX (372u)
+
+#define OTP_NT_FW_VER_79_64_FUSE_IDX   (372u)
+#define OTP_NT_FW_VER_79_64_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_79_64_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_79_64_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER5 Index 373 */
+#define OTP_NT_FW_VER5_FUSE_IDX (373u)
+
+#define OTP_NT_FW_VER_95_80_FUSE_IDX   (373u)
+#define OTP_NT_FW_VER_95_80_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_95_80_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_95_80_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER6 Index 374 */
+#define OTP_NT_FW_VER6_FUSE_IDX (374u)
+
+#define OTP_NT_FW_VER_111_96_FUSE_IDX   (374u)
+#define OTP_NT_FW_VER_111_96_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_111_96_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_111_96_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER7 Index 375 */
+#define OTP_NT_FW_VER7_FUSE_IDX (375u)
+
+#define OTP_NT_FW_VER_127_112_FUSE_IDX   (375u)
+#define OTP_NT_FW_VER_127_112_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_127_112_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_127_112_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER8 Index 376 */
+#define OTP_NT_FW_VER8_FUSE_IDX (376u)
+
+#define OTP_NT_FW_VER_143_128_FUSE_IDX   (376u)
+#define OTP_NT_FW_VER_143_128_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_143_128_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_143_128_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER9 Index 377 */
+#define OTP_NT_FW_VER9_FUSE_IDX (377u)
+
+#define OTP_NT_FW_VER_159_144_FUSE_IDX   (377u)
+#define OTP_NT_FW_VER_159_144_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_159_144_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_159_144_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER10 Index 378 */
+#define OTP_NT_FW_VER10_FUSE_IDX (378u)
+
+#define OTP_NT_FW_VER_175_160_FUSE_IDX   (378u)
+#define OTP_NT_FW_VER_175_160_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_175_160_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_175_160_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER11 Index 379 */
+#define OTP_NT_FW_VER11_FUSE_IDX (379u)
+
+#define OTP_NT_FW_VER_191_176_FUSE_IDX   (379u)
+#define OTP_NT_FW_VER_191_176_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_191_176_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_191_176_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER12 Index 380 */
+#define OTP_NT_FW_VER12_FUSE_IDX (380u)
+
+#define OTP_NT_FW_VER_207_192_FUSE_IDX   (380u)
+#define OTP_NT_FW_VER_207_192_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_207_192_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_207_192_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER13 Index 381 */
+#define OTP_NT_FW_VER13_FUSE_IDX (381u)
+
+#define OTP_NT_FW_VER_223_208_FUSE_IDX   (381u)
+#define OTP_NT_FW_VER_223_208_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_223_208_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_223_208_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER14 Index 382 */
+#define OTP_NT_FW_VER14_FUSE_IDX (382u)
+
+#define OTP_NT_FW_VER_239_224_FUSE_IDX   (382u)
+#define OTP_NT_FW_VER_239_224_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_239_224_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_239_224_FUSE_WIDTH (16u)
+
+/* Fuse Word NT_FW_VER15 Index 383 */
+#define OTP_NT_FW_VER15_FUSE_IDX (383u)
+
+#define OTP_NT_FW_VER_255_240_FUSE_IDX   (383u)
+#define OTP_NT_FW_VER_255_240_FUSE_SHIFT (0u)
+#define OTP_NT_FW_VER_255_240_FUSE_MASK  (0xFFFFu)
+#define OTP_NT_FW_VER_255_240_FUSE_WIDTH (16u)
+
+/* Fuse Word TZ_FW_VER0 Index 384 */
+#define OTP_TZ_FW_VER0_FUSE_IDX (384u)
+
+#define OTP_TZ_FW_VER_15_0_FUSE_IDX   (384u)
+#define OTP_TZ_FW_VER_15_0_FUSE_SHIFT (0u)
+#define OTP_TZ_FW_VER_15_0_FUSE_MASK  (0xFFFFu)
+#define OTP_TZ_FW_VER_15_0_FUSE_WIDTH (16u)
+
+/* Fuse Word TZ_FW_VER1 Index 385 */
+#define OTP_TZ_FW_VER1_FUSE_IDX (385u)
+
+#define OTP_TZ_FW_VER_31_16_FUSE_IDX   (385u)
+#define OTP_TZ_FW_VER_31_16_FUSE_SHIFT (0u)
+#define OTP_TZ_FW_VER_31_16_FUSE_MASK  (0xFFFFu)
+#define OTP_TZ_FW_VER_31_16_FUSE_WIDTH (16u)
+
+/* Fuse Word TZ_FW_VER2 Index 386 */
+#define OTP_TZ_FW_VER2_FUSE_IDX (386u)
+
+#define OTP_TZ_FW_VER_47_32_FUSE_IDX   (386u)
+#define OTP_TZ_FW_VER_47_32_FUSE_SHIFT (0u)
+#define OTP_TZ_FW_VER_47_32_FUSE_MASK  (0xFFFFu)
+#define OTP_TZ_FW_VER_47_32_FUSE_WIDTH (16u)
+
+/* Fuse Word TZ_FW_VER3 Index 387 */
+#define OTP_TZ_FW_VER3_FUSE_IDX (387u)
+
+#define OTP_TZ_FW_VER_63_48_FUSE_IDX   (387u)
+#define OTP_TZ_FW_VER_63_48_FUSE_SHIFT (0u)
+#define OTP_TZ_FW_VER_63_48_FUSE_MASK  (0xFFFFu)
+#define OTP_TZ_FW_VER_63_48_FUSE_WIDTH (16u)
+
+/* Fuse Word WIFI_FW_VER0 Index 388 */
+#define OTP_WIFI_FW_VER0_FUSE_IDX (388u)
+
+#define OTP_WIFI_FW_VER_15_0_FUSE_IDX   (388u)
+#define OTP_WIFI_FW_VER_15_0_FUSE_SHIFT (0u)
+#define OTP_WIFI_FW_VER_15_0_FUSE_MASK  (0xFFFFu)
+#define OTP_WIFI_FW_VER_15_0_FUSE_WIDTH (16u)
+
+/* Fuse Word WIFI_FW_VER1 Index 389 */
+#define OTP_WIFI_FW_VER1_FUSE_IDX (389u)
+
+#define OTP_WIFI_FW_VER_31_16_FUSE_IDX   (389u)
+#define OTP_WIFI_FW_VER_31_16_FUSE_SHIFT (0u)
+#define OTP_WIFI_FW_VER_31_16_FUSE_MASK  (0xFFFFu)
+#define OTP_WIFI_FW_VER_31_16_FUSE_WIDTH (16u)
+
+/* Fuse Word WIFI_FW_VER2 Index 390 */
+#define OTP_WIFI_FW_VER2_FUSE_IDX (390u)
+
+#define OTP_WIFI_FW_VER_47_32_FUSE_IDX   (390u)
+#define OTP_WIFI_FW_VER_47_32_FUSE_SHIFT (0u)
+#define OTP_WIFI_FW_VER_47_32_FUSE_MASK  (0xFFFFu)
+#define OTP_WIFI_FW_VER_47_32_FUSE_WIDTH (16u)
+
+/* Fuse Word WIFI_FW_VER3 Index 391 */
+#define OTP_WIFI_FW_VER3_FUSE_IDX (391u)
+
+#define OTP_WIFI_FW_VER_63_48_FUSE_IDX   (391u)
+#define OTP_WIFI_FW_VER_63_48_FUSE_SHIFT (0u)
+#define OTP_WIFI_FW_VER_63_48_FUSE_MASK  (0xFFFFu)
+#define OTP_WIFI_FW_VER_63_48_FUSE_WIDTH (16u)
+
+/* Fuse Word BLE_FW_VER0 Index 392 */
+#define OTP_BLE_FW_VER0_FUSE_IDX (392u)
+
+#define OTP_BLE_FW_VER_15_0_FUSE_IDX   (392u)
+#define OTP_BLE_FW_VER_15_0_FUSE_SHIFT (0u)
+#define OTP_BLE_FW_VER_15_0_FUSE_MASK  (0xFFFFu)
+#define OTP_BLE_FW_VER_15_0_FUSE_WIDTH (16u)
+
+/* Fuse Word BLE_FW_VER1 Index 393 */
+#define OTP_BLE_FW_VER1_FUSE_IDX (393u)
+
+#define OTP_BLE_FW_VER_31_16_FUSE_IDX   (393u)
+#define OTP_BLE_FW_VER_31_16_FUSE_SHIFT (0u)
+#define OTP_BLE_FW_VER_31_16_FUSE_MASK  (0xFFFFu)
+#define OTP_BLE_FW_VER_31_16_FUSE_WIDTH (16u)
+
+/* Fuse Word BLE_FW_VER2 Index 394 */
+#define OTP_BLE_FW_VER2_FUSE_IDX (394u)
+
+#define OTP_BLE_FW_VER_47_32_FUSE_IDX   (394u)
+#define OTP_BLE_FW_VER_47_32_FUSE_SHIFT (0u)
+#define OTP_BLE_FW_VER_47_32_FUSE_MASK  (0xFFFFu)
+#define OTP_BLE_FW_VER_47_32_FUSE_WIDTH (16u)
+
+/* Fuse Word BLE_FW_VER3 Index 395 */
+#define OTP_BLE_FW_VER3_FUSE_IDX (395u)
+
+#define OTP_BLE_FW_VER_63_48_FUSE_IDX   (395u)
+#define OTP_BLE_FW_VER_63_48_FUSE_SHIFT (0u)
+#define OTP_BLE_FW_VER_63_48_FUSE_MASK  (0xFFFFu)
+#define OTP_BLE_FW_VER_63_48_FUSE_WIDTH (16u)
+
+/* Fuse Word 15_4_FW_VER0 Index 396 */
+#define OTP_15_4_FW_VER0_FUSE_IDX (396u)
+
+#define OTP_15_4_FW_VER_15_0_FUSE_IDX   (396u)
+#define OTP_15_4_FW_VER_15_0_FUSE_SHIFT (0u)
+#define OTP_15_4_FW_VER_15_0_FUSE_MASK  (0xFFFFu)
+#define OTP_15_4_FW_VER_15_0_FUSE_WIDTH (16u)
+
+/* Fuse Word 15_4_FW_VER1 Index 397 */
+#define OTP_15_4_FW_VER1_FUSE_IDX (397u)
+
+#define OTP_15_4_FW_VER_31_16_FUSE_IDX   (397u)
+#define OTP_15_4_FW_VER_31_16_FUSE_SHIFT (0u)
+#define OTP_15_4_FW_VER_31_16_FUSE_MASK  (0xFFFFu)
+#define OTP_15_4_FW_VER_31_16_FUSE_WIDTH (16u)
+
+/* Fuse Word 15_4_FW_VER2 Index 398 */
+#define OTP_15_4_FW_VER2_FUSE_IDX (398u)
+
+#define OTP_15_4_FW_VER_47_32_FUSE_IDX   (398u)
+#define OTP_15_4_FW_VER_47_32_FUSE_SHIFT (0u)
+#define OTP_15_4_FW_VER_47_32_FUSE_MASK  (0xFFFFu)
+#define OTP_15_4_FW_VER_47_32_FUSE_WIDTH (16u)
+
+/* Fuse Word 15_4_FW_VER3 Index 399 */
+#define OTP_15_4_FW_VER3_FUSE_IDX (399u)
+
+#define OTP_15_4_FW_VER_63_48_FUSE_IDX   (399u)
+#define OTP_15_4_FW_VER_63_48_FUSE_SHIFT (0u)
+#define OTP_15_4_FW_VER_63_48_FUSE_MASK  (0xFFFFu)
+#define OTP_15_4_FW_VER_63_48_FUSE_WIDTH (16u)
+
+/* Fuse Word USER_RED_0 Index 400 */
+#define OTP_USER_RED_0_FUSE_IDX (400u)
+
+/* Fuse Word USER_RED_1 Index 401 */
+#define OTP_USER_RED_1_FUSE_IDX (401u)
+
+/* Fuse Word USER_RED_2 Index 402 */
+#define OTP_USER_RED_2_FUSE_IDX (402u)
+
+/* Fuse Word USER_RED_3 Index 403 */
+#define OTP_USER_RED_3_FUSE_IDX (403u)
+
+/* Fuse Word ROLLBACK_COUNTER_0 Index 404 */
+#define OTP_ROLLBACK_COUNTER_0_FUSE_IDX (404u)
+
+#define OTP_ROLLBACK_COUNTER_FUSE_IDX   (404u)
+#define OTP_ROLLBACK_COUNTER_FUSE_SHIFT (0u)
+#define OTP_ROLLBACK_COUNTER_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_ROLLBACK_COUNTER_FUSE_WIDTH (32u)
+
+/* Fuse Word ROLLBACK_COUNTER_1 Index 405 */
+#define OTP_ROLLBACK_COUNTER_1_FUSE_IDX (405u)
+
+#define OTP_ROLLBACK_COUNTER_FUSE_IDX_1 (405u)
+#define OTP_ROLLBACK_COUNTER_FUSE_SHIFT (0u)
+#define OTP_ROLLBACK_COUNTER_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_ROLLBACK_COUNTER_FUSE_WIDTH (32u)
+
+/* Fuse Word ROLLBACK_COUNTER_2 Index 406 */
+#define OTP_ROLLBACK_COUNTER_2_FUSE_IDX (406u)
+
+#define OTP_ROLLBACK_COUNTER_FUSE_IDX_2 (406u)
+#define OTP_ROLLBACK_COUNTER_FUSE_SHIFT (0u)
+#define OTP_ROLLBACK_COUNTER_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_ROLLBACK_COUNTER_FUSE_WIDTH (32u)
+
+/* Fuse Word ROLLBACK_COUNTER_3 Index 407 */
+#define OTP_ROLLBACK_COUNTER_3_FUSE_IDX (407u)
+
+#define OTP_ROLLBACK_COUNTER_FUSE_IDX_3 (407u)
+#define OTP_ROLLBACK_COUNTER_FUSE_SHIFT (0u)
+#define OTP_ROLLBACK_COUNTER_FUSE_MASK  (0xFFFFFFFFu)
+#define OTP_ROLLBACK_COUNTER_FUSE_WIDTH (32u)
+
+#define OTP_FUSEMAP_SIZE (420u)
+
+#endif // __FUSEMAP_H__
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/life_cycle.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/life_cycle.h
new file mode 100644
index 0000000000..dfd48bed69
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/life_cycle.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2020-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __LIFE_CYCLE_H__
+#define __LIFE_CYCLE_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Life cycle definitions. */
+#define LIFECYCLE_NXP_BLANK (0x0u)
+
+#define LIFECYCLE_NXP_DEV_NON_SEC (0xFDu)
+#define LIFECYCLE_NXP_DEV_SEC     (0xFEu)
+
+#define LIFECYCLE_NXP_PROVISIONED  (0x1u)
+#define LIFECYCLE_OEM_OPEN         (0x3u)
+#define LIFECYCLE_OEM_SECURE       (0x7u)
+#define LIFECYCLE_OEM_CLOSED       (0xFu)
+#define LIFECYCLE_OEM_FIELD_RETURN (0x1Fu)
+#define LIFECYCLE_NXP_FIELD_RETURN (0x3Fu)
+
+#define LIFECYCLE_OEM_LOCKED (0xCFu)
+#define LIFECYCLE_SHREDDED   (0xFFu)
+
+#define DIS_ROM_HIDIND_MASK  (0xF00000u)
+#define DIS_ROM_HIDIND_SHIFT (20u)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+uint32_t get_lifecycle_state(void);
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/nboot_rom_api_table.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/nboot_rom_api_table.h
new file mode 100644
index 0000000000..cc98d9978f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/nboot_rom_api_table.h
@@ -0,0 +1,40 @@
+/*
+ *     Copyright 2020-2021 NXP
+ *     All rights reserved.
+ *
+ *     SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __NBOOT_ROM_API_TABLE_H__
+#define __NBOOT_ROM_API_TABLE_H__
+
+typedef int romapi_status_t;
+
+typedef struct
+{
+    romapi_status_t (*nboot_rsvd0)(void);
+    fsl_nboot_status_t (*nboot_context_init)(fsl_nboot_context_t *context);
+    fsl_nboot_status_t (*nboot_context_deinit)(fsl_nboot_context_t *context);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_manifest)(fsl_nboot_context_t *context,
+                                                        uint32_t *manifest,
+                                                        fsl_nboot_sb3_load_manifest_parms_t *parms);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_block)(fsl_nboot_context_t *context, uint32_t *block);
+    fsl_nboot_status_protected_t (*nboot_rsvd1)(void);
+    fsl_nboot_status_protected_t (*nboot_rsvd2)(void);
+} nboot_interface_v0_t;
+
+typedef struct
+{
+    romapi_status_t (*romapi_rng_generate_random)(uint8_t *output, size_t outputByteLen);
+    fsl_nboot_status_t (*nboot_context_init)(fsl_nboot_context_t *context);
+    fsl_nboot_status_t (*nboot_context_deinit)(fsl_nboot_context_t *context);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_manifest)(fsl_nboot_context_t *context,
+                                                        uint32_t *manifest,
+                                                        fsl_nboot_sb3_load_manifest_parms_t *parms);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_block)(fsl_nboot_context_t *context, uint32_t *block);
+    fsl_nboot_status_protected_t (*nboot_img_authenticate_ecdsa)(fsl_nboot_context_t *context,
+                                                             uint8_t imageStartAddress[],
+                                                             fsl_nboot_bool_t *isSignatureVerified,
+                                                             fsl_nboot_img_auth_ecdsa_parms_t *parms);
+} nboot_interface_v1_t;
+
+#endif /* _NBOOT_ROM_API_TABLE_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/life_cycle.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/life_cycle.c
new file mode 100644
index 0000000000..ed05a0ae44
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/life_cycle.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 - 2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "life_cycle.h"
+#include "fusemap.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+uint32_t get_lifecycle_state(void)
+{
+    uint32_t lifeCycleStateOtpShadow          = OTP_LCS_FUSE_VALUE();
+    uint32_t lifeCycleStateRedundantOtpShadow = OTP_LCS_REDUNDANT_FUSE_VALUE();
+    if (lifeCycleStateOtpShadow != lifeCycleStateRedundantOtpShadow)
+    {
+        while (true)
+        {
+            ; /* No necessary actions. */
+        }
+    }
+
+    return ((lifeCycleStateOtpShadow & OTP_LCS_FUSE_MASK) >> OTP_LCS_FUSE_SHIFT);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/nboot_hal.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/nboot_hal.c
new file mode 100644
index 0000000000..078ccdeff9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/nboot_hal.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright 2020 - 2021,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <limits.h>
+#include "fusemap.h"
+#include "fsl_loader_utils.h"
+#include "life_cycle.h"
+#include "fsl_ocotp.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define NBOOT_HAL_PRINTF(...)
+
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+/*!
+ * @brief Get the root security parameters.
+ *
+ * Read the root security configurations from OTP.
+ *
+ * @param context   NBOOT context.
+ * @param parms     Root security parameters.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_InvalidArgument Invalid values of the parms
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static fsl_nboot_status_t nboot_hal_get_root_auth_parms(fsl_nboot_context_t *context, fsl_nboot_rot_auth_parms_t *parms);
+
+/*!
+ * @brief Get the ROTK revoke settings.
+ *
+ * Read the OTP_ROTK_REVOKE.
+ *
+ * @param rotkRevoke ROTK revoke state.
+ * @param rotkCnt ROTK count.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static inline fsl_nboot_status_t nboot_hal_get_rotk_revoke(fsl_nboot_root_key_revocation_t *rotkRevoke, uint32_t rotkCnt);
+
+/*!
+ * @brief Get the ROTKH.
+ *
+ * Read the IFR_ROTKH.
+ *
+ * @param rotkh ROTKH value.
+ * @param rotkhSize ROTKH size in bytes.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static fsl_nboot_status_t nboot_hal_get_rotkh(uint32_t *rotkh, uint32_t rotkhSize);
+
+/*!
+ * @brief Get the type of the root keys.
+ *
+ * Get the root key type
+ *
+ * @param rootKeyType Type of the root keys.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static inline fsl_nboot_status_t nboot_hal_get_root_key_type(fsl_nboot_root_key_type_and_length_t *rootKeyType);
+
+/*!
+ * @brief Get the Part Common Key(PCK).
+ *
+ * Read the IFR_PCK_BLOB.
+ *
+ * @param pckBlob PCK blob.
+ * @param pckBlobSize PCK blob size in byte.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static inline fsl_nboot_status_t nboot_hal_get_pck_blob(uint8_t *pckBlob, uint32_t pckBlobSize);
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static inline uint32_t set_antipole(uint32_t value)
+{
+    return (value & 0xFFFFu) | (~(value & 0xFFFFu) << 16);
+}
+
+static fsl_nboot_status_t nboot_hal_get_root_auth_parms(fsl_nboot_context_t *context, fsl_nboot_rot_auth_parms_t *parms)
+{
+    if ((NULL == context) || (NULL == parms))
+    {
+        return kStatus_NBOOT_InvalidArgument;
+    }
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Fail;
+    do
+    {
+        status =
+            nboot_hal_get_rotk_revoke(&parms->soc_rootKeyRevocation[0],
+                                      sizeof(parms->soc_rootKeyRevocation) / sizeof(parms->soc_rootKeyRevocation[0]));
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        status = nboot_hal_get_rotkh(&parms->soc_rkh[0], sizeof(parms->soc_rkh));
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        parms->soc_numberOfRootKeys = 0u;
+        parms->soc_rootKeyUsage[1]  = kNBOOT_RootKeyUsage_Unused;
+        parms->soc_rootKeyUsage[2]  = kNBOOT_RootKeyUsage_Unused;
+        parms->soc_rootKeyUsage[3]  = kNBOOT_RootKeyUsage_Unused;
+        for (size_t i = 0; i < (sizeof(parms->soc_rootKeyUsage) / sizeof(parms->soc_rootKeyUsage[0])); i++)
+        {
+            if ((parms->soc_rootKeyUsage[i] & OTP_ROTK0_USAGE_FUSE_MASK) != kNBOOT_RootKeyUsage_Unused)
+            {
+                parms->soc_numberOfRootKeys++;
+            }
+        }
+
+        status = nboot_hal_get_root_key_type(&parms->soc_rootKeyTypeAndLength);
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        parms->soc_lifecycle = (fsl_nboot_soc_lifecycle_t)set_antipole(get_lifecycle_state());
+        status               = kStatus_NBOOT_Success;
+    } while (false);
+	
+	if (status != kStatus_NBOOT_Success)
+	{
+	    (void)memset(parms, 0, sizeof(*parms));
+	}
+
+    return status;
+}
+
+static inline fsl_nboot_status_t nboot_hal_get_rotk_revoke(fsl_nboot_root_key_revocation_t *rotkRevoke, uint32_t rotkCnt)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(rotkRevoke);
+    assert(rotkCnt == NBOOT_ROOT_CERT_COUNT);
+
+    /* Set all root key to 'revoked' state */
+    for (uint32_t i = 0u; i < rotkCnt; i++)
+    {
+        rotkRevoke[i] = kNBOOT_RootKey_Enabled;
+    }
+
+    return kStatus_NBOOT_Success;
+}
+
+static fsl_nboot_status_t nboot_hal_get_rotkh(uint32_t *rotkh, uint32_t rotkhSize)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(rotkh);
+    assert(rotkhSize == (uint32_t)NBOOT_ROOT_ROTKH_SIZE_IN_BYTE);
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Success;
+
+    /* root key hash fixed in Flash memory */
+#ifdef USE_ENG_CERTIFICATE
+    rotkh[0]  = 0xd0cfb419U;
+    rotkh[1]  = 0x4037ee3cU;
+    rotkh[2]  = 0xde74393eU;
+    rotkh[3]  = 0x0156d0a3U;
+    rotkh[4]  = 0x373b8677U;
+    rotkh[5]  = 0x6b6aee3dU;
+    rotkh[6]  = 0x619b459eU;
+    rotkh[7]  = 0xfa33f31dU;
+    rotkh[8]  = 0x00000000U;
+    rotkh[9]  = 0x00000000U;
+    rotkh[10] = 0x00000000U;
+    rotkh[11] = 0x00000000U;
+#else
+    if ((get_chip_revision() == 0U))
+    {
+        rotkh[0]  = 0x60DFBEE6U;
+        rotkh[1]  = 0x8799305FU;
+        rotkh[2]  = 0xBA9E4AE6U;
+        rotkh[3]  = 0x1908394FU;
+        rotkh[4]  = 0x7AC4F934U;
+        rotkh[5]  = 0xEF76BF41U;
+        rotkh[6]  = 0x2E27796EU;
+        rotkh[7]  = 0x94DB19A0U;
+        rotkh[8]  = 0x00000000U;
+        rotkh[9]  = 0x00000000U;
+        rotkh[10] = 0x00000000U;
+        rotkh[11] = 0x00000000U;
+    }
+    else if ((get_chip_revision() == 1U))
+    {
+        rotkh[0]  = 0x9C758C58U;
+        rotkh[1]  = 0x0A5CCEAAU;
+        rotkh[2]  = 0x850DAD41U;
+        rotkh[3]  = 0x1371EEBAU;
+        rotkh[4]  = 0xB7874851U;
+        rotkh[5]  = 0x53C5BA44U;
+        rotkh[6]  = 0xF236F964U;
+        rotkh[7]  = 0x3320ECDFU;
+        rotkh[8]  = 0x00000000U;
+        rotkh[9]  = 0x00000000U;
+        rotkh[10] = 0x00000000U;
+        rotkh[11] = 0x00000000U;
+    }
+    else if ((get_chip_revision() == 2U))
+    {
+        rotkh[0]  = 0xE7C7E9BBU;
+        rotkh[1]  = 0x12C8C535U;
+        rotkh[2]  = 0x37E61148U;
+        rotkh[3]  = 0x2BE7F18CU;
+        rotkh[4]  = 0x8F0E3094U;
+        rotkh[5]  = 0xB2BA7F32U;
+        rotkh[6]  = 0xEC9B4ECBU;
+        rotkh[7]  = 0xAD9FC941U;
+        rotkh[8]  = 0x00000000U;
+        rotkh[9]  = 0x00000000U;
+        rotkh[10] = 0x00000000U;
+        rotkh[11] = 0x00000000U;
+    }
+	else
+	{
+	    ; /* none to do */
+	}
+#endif
+    return status;
+}
+
+static inline fsl_nboot_status_t nboot_hal_get_root_key_type(fsl_nboot_root_key_type_and_length_t *rootKeyType)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(rootKeyType);
+
+    *rootKeyType = kNBOOT_RootKey_Ecdsa_P256;
+
+    return kStatus_NBOOT_Success;
+}
+
+static inline fsl_nboot_status_t nboot_hal_get_pck_blob(uint8_t *pckBlob, uint32_t pckBlobSize)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(pckBlob);
+    assert(pckBlobSize == (uint32_t)NBOOT_PCK_BLOB_SIZE_IN_BYTE);
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Fail;
+    status_t otpStatus    = kStatus_Fail;
+
+    do
+    {
+        uint32_t fuseIdxStart = OTP_NXP_WIFI_SK_MK_31_0_FUSE_IDX;
+        for (int i = 0; i < (NBOOT_PCK_BLOB_SIZE_IN_BYTE / 4); i++)
+        {
+            otpStatus = OCOTP_OtpFuseRead(fuseIdxStart, (uint32_t *)(&pckBlob[4 * i]));
+            if (otpStatus != kStatus_Success)
+            {
+                return kStatus_NBOOT_Fail;
+            }
+            ++fuseIdxStart;
+        }
+        status = kStatus_NBOOT_Success;
+    } while (false);
+
+    return status;
+}
+
+fsl_nboot_status_t nboot_hal_get_sb3_manifest_params(fsl_nboot_context_t *context, fsl_nboot_sb3_load_manifest_parms_t *parms)
+{
+    if ((NULL == context) || (NULL == parms))
+    {
+        return kStatus_NBOOT_InvalidArgument;
+    }
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Fail;
+    do
+    {
+        status = nboot_hal_get_root_auth_parms(context, &parms->soc_RoTNVM);
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        status = nboot_hal_get_pck_blob(&parms->pckBlob[0], sizeof(parms->pckBlob));
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        status = kStatus_NBOOT_Success;
+    } while (false);
+
+    if (status != kStatus_NBOOT_Success)
+    {
+        (void)memset(parms, 0, sizeof(*parms));
+    }
+
+    return status;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/readme.txt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/readme.txt
new file mode 100644
index 0000000000..ebdfe35ba9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/readme.txt
@@ -0,0 +1,38 @@
+1.Examples that support monolithic image download do not need the steps 2-6 to load fw:
+    Wi-Fi examples: wifi_cli, wifi_wpa_supplicant, wifi_cli_static, wifi_cert, wifi_cli_fw_dump, wifi_cli_prov, wifi_test_mode
+	ncp examples: ncp_device
+	coex examples: coex_cli, coex_supplicant_cli
+
+	These examples can load cpu1/2 fw automatically, don't need to load them seperatly.
+
+2. FW image names:
+	Production FW, for users:
+		rw61x_sb_wifi_a2.bin, for CPU1_wifi of redfinch a2 board
+		rw61x_sb_ble_a2.bin, for CPU2_ble of redfinch a2 board
+		rw61x_sb_ble_15d4_combo_a2.bin, for CPU2_ble_15.4_combo of redfinch a2 board
+
+3. where to get FW image(Production and mfg_FW):
+	In the directory:  /components/conn_fwloader/fw_bin
+
+4. How to load FW(Production and mfg_FW):
+	Need to write the FW image to flash first, then the loadservice will download FW when power on.
+	For example, the CMD to write CPU1 image to flash in J-link window:
+		loadbin C:\xxx\rw61x_sb_wifi_xx.bin,0x08400000
+
+	The CMD to write CPU2_ble image to flash in J-link window:
+		loadbin C:\xxx\rw61x_sb_ble_xx.bin,0x08540000
+
+	The CMD to write CPU2_15.4 image to flash in J-link window:
+		loadbin C:\xxx\rw61x_sb_ble_15d4_combo_xx.bin,0x085e0000
+
+5. How to generate the C files to be compiled in the monolithic binary:
+	In a shell go to directory /components/conn_fwloader. Enter the following command:
+	 'python script/fw_bin2c_conv.py -t sb fw_bin'
+	or 'python script/fw_bin2c_conv.py -t raw fw_bin':
+	This results in generating the C files under fw_bin/A1 and fw_bin/A2 subdirectories.
+
+6. Remap mechanism support
+	Whenever the remap feature is active, the flash should not be accessed in direct mode.
+	As a consequence, no structure cast should be done on flash direct addresses. Likewise memcpy operations
+	should be avoided. Instead all flash accesses must be done via staging buffers in RAM, that 
+	get loaded using the mflash driver.
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/compiler/mcuxClToolchain.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/compiler/mcuxClToolchain.h
new file mode 100644
index 0000000000..06d67ade78
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/compiler/mcuxClToolchain.h
@@ -0,0 +1,144 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#ifndef COMPILER_TOOLCHAIN_H_
+#define COMPILER_TOOLCHAIN_H_
+
+/* for armclang */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    #define CSS_IDATA_SEGMENT __attribute__((section("CSS_IDATA_SEGMENT")))
+    #define CSS_CONST_SEGMENT __attribute__((section("CSS_CONST_SEGMENT_SECTION")))
+    #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) __attribute__((section("MCUX_OBFUSCATED_FUP_SEGMENT")))
+    #define UNUSED_PARAM __attribute__((unused))
+    /*  
+        Use of UNALIGNED on ARMCLANG
+
+        The __unaligned keyword is a type qualifier that tells the compiler to treat the pointer or variable as an unaligned pointer or variable.
+        www.keil.com/support/man/docs/armclang_ref/armclang_ref_pfl1493130433688.htm
+
+        The use of __attribute__((packed)) is incorrect on ARMCLANG
+
+        The packed type attribute specifies that a type must have the smallest possible alignment. This attribute only applies to struct and union types.
+        www.keil.com/support/man/docs/armclang_ref/armclang_ref_chr1393328521340.htm
+
+        -munaligned-access is the default for architectures that support unaligned accesses to data. This default applies to all architectures supported by Arm Compiler for Embedded 6, except Armv6-M, and Armv8-M without the Main Extension.
+    */
+    #define UNALIGNED __unaligned
+    #define MCUX_CSSL_UNUSED(p) ((void) (p))
+    /* Macro for alligning buffers to cpu word */
+    #define ALIGNED __attribute__((aligned(4))) 
+
+/* using the gcc toolchain file for both gcc and armgcc */
+#elif defined ( __GNUC__ )
+    #define CSS_IDATA_SEGMENT
+    #define CSS_CONST_SEGMENT
+    #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4)))
+    #define UNUSED_PARAM __attribute__((unused))
+    #define UNALIGNED
+    /* Macro for alligning buffers to cpu word */
+    #define ALIGNED __attribute__((aligned(4))) 
+
+/* for armcc compiler */
+#elif defined ( __CC_ARM )
+    #define CSS_IDATA_SEGMENT __attribute__((section("CSS_IDATA_SEGMENT")))
+    #define CSS_CONST_SEGMENT __attribute__((section("CSS_CONST_SEGMENT")))
+    #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) __attribute__((section("MCUX_OBFUSCATED_FUP_SEGMENT")))
+    #define UNUSED_PARAM __attribute__((unused))
+    #define UNALIGNED __packed
+    /* Macro for alligning buffers to cpu word */
+    #define ALIGNED __attribute__((aligned(4))) 
+
+/* for ghs compiler */
+#elif defined ( __ghs__ )
+    #define CSS_IDATA_SEGMENT
+    #define CSS_CONST_SEGMENT
+    #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4)))
+    #define UNUSED_PARAM __attribute__((unused))
+    #define UNALIGNED
+    /* Macro for alligning buffers to cpu word */
+    #define ALIGNED __attribute__((aligned(4))) 
+
+/* for iar compiler */
+#elif defined ( __ICCARM__ )
+    #define CSS_IDATA_SEGMENT __attribute__((section("CSS_IDATA_SEGMENT")))
+    #define CSS_CONST_SEGMENT __attribute__((section("CSS_CONST_SEGMENT")))
+    #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) __attribute__((section(".mcux_obfuscated_fup_segment")))
+    #define UNUSED_PARAM __attribute__((unused))
+    #define UNALIGNED __packed
+    /* Macro for alligning buffers to cpu word */
+    #define ALIGNED __attribute__((aligned(4))) 
+
+/* for llvm */
+#elif defined ( __clang__ )
+    #define CSS_IDATA_SEGMENT
+    #define CSS_CONST_SEGMENT
+    #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4)))
+    #define UNUSED_PARAM __attribute__((unused))
+    #define UNALIGNED
+    /* Macro for alligning buffers to cpu word */
+    #define ALIGNED __attribute__((aligned(4))) 
+    
+
+#endif
+
+
+#if defined(__ghs__) || defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__)
+    #define GHS_ICCARM_ARMCC_GT_10_5_GNUC
+#endif
+
+#if defined(__ghs__) || defined(__gcc__) || defined(__ICCARM__) || defined(__GNUC__)
+    #define GHS_GCC_ICCARM_GNUC
+#endif
+
+#if defined(__ghs__) || defined(__gcc__) || defined(__ICCARM__)
+    #define GHS_GCC_ICCARM
+#endif
+
+#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || defined(__CC_ARM) || defined(__GNUC__)
+    #define ICCARM_ARMCC_GNUC
+#endif
+
+#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+    #define ICCARM_ARMCLANG_GNUC
+#endif
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+    #define ARMCC_LT_10_5 //6.01 build 0050
+#endif
+
+
+#if defined ( __CC_ARM )
+/* Arm Compiler 4/5 */
+#define MCUX_CL_COMPILER_ARMCC
+#define MCUX_CL_COMPILER_ARM_COMPILER
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+/* Arm Compiler 6.6 LTM (armclang) */
+#define MCUX_CL_COMPILER_ARMCLANG_LTM
+#define MCUX_CL_COMPILER_ARM_COMPILER
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+/* Arm Compiler above 6.10.1 (armclang) */
+#define MCUX_CL_COMPILER_ARMCLANG
+#define MCUX_CL_COMPILER_ARM_COMPILER
+
+#elif defined (_clang_)
+#define MCUX_CL_COMPILER_ARM_COMPILER /* i.e. Version 6.01 build 0019  */
+#endif
+
+
+#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && !defined(inline) && !defined(__cplusplus)
+    #define ARMCC_MSC_VER_NOT_INLINE_NOT_CPP
+#endif
+
+#endif /* COMPILER_TOOLCHAIN_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/internal/mcuxClBuffer_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/internal/mcuxClBuffer_Internal.h
new file mode 100644
index 0000000000..e30a9f6ac1
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/internal/mcuxClBuffer_Internal.h
@@ -0,0 +1,46 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** 
+ * \file  mcuxClBuffer_Internal.h
+ * \brief Internal functions of the mcuxClBuffer component
+ */
+
+#ifndef MCUXCLBUFFER_INTERNAL_H_
+#define MCUXCLBUFFER_INTERNAL_H_
+
+#include <mcuxClCore_Platform.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Include the configuration for the buffer types. */
+#include <mcuxClBuffer_Cfg.h>
+
+/* Include the selected implementation of the buffer types. */
+#if defined(MCUXCLBUFFER_USE_OBJECT) && (1 == MCUXCLBUFFER_USE_OBJECT)
+#  include <internal/mcuxClBuffer_Internal_Object.h>
+#elif defined(MCUXCLBUFFER_USE_POINTER) && (1 == MCUXCLBUFFER_USE_POINTER)
+#  include <internal/mcuxClBuffer_Internal_Pointer.h>
+#else
+#  error "No buffer type implementation found/configured."
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLBUFFER_INTERNAL_H_ */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/internal/mcuxClBuffer_Internal_Pointer.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/internal/mcuxClBuffer_Internal_Pointer.h
new file mode 100644
index 0000000000..d8cd0413ce
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/internal/mcuxClBuffer_Internal_Pointer.h
@@ -0,0 +1,310 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxClBuffer_Internal_Pointer.h
+ * \brief Provides the internal API & implementation for the plain C pointer buffer types.
+ */
+
+#ifndef MCUXCLBUFFER_INTERNAL_POINTER_H_
+#define MCUXCLBUFFER_INTERNAL_POINTER_H_
+
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Platform.h>
+
+#include <mcuxClBuffer.h>
+#include <mcuxClBuffer_Pointer.h>
+
+#include <mcuxCsslDataIntegrity.h>
+
+
+#include <mcuxClMemory_Copy.h>
+#include <internal/mcuxClMemory_Copy_Internal.h>
+#include <internal/mcuxClMemory_CopyWords_Internal.h>
+#include <mcuxClMemory_Copy_Reversed.h>
+#include <internal/mcuxClMemory_CopySecure_Internal.h>
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \defgroup clBufferUsage Buffer read/write functionality
+ * \brief Buffer read/write functionality.
+ * \ingroup mcuxClBuffer
+ */
+
+/* TODO CLNS-10260: finalize the implementation and especially update all the memory functions that are called from here, once CLNS-9401 is finished.
+ * Appropriate memory functions should be called, to properly handle the security and the different cases of length/alignment (e.g. length being a multiple of 4 or power of 2).
+ */
+
+/**
+ * \brief Writes the pointer of \p bufSrc plus the \p offset in \p ppDest.
+ * 
+ * \param bufSrc      Input buffer
+ * \param offset      Offset of the input buffer
+ * \param bufCpuWa    Not used
+ * \param ppDest      Pointer to the address where the result is written to
+ * \param byteLength  Not used
+ * 
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_inputBufferToCPU)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_inputBufferToCPU(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *bufCpuWa UNUSED_PARAM, const uint8_t **ppDest, uint32_t byteLength UNUSED_PARAM)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_inputBufferToCPU);
+  *ppDest = (const uint8_t *)bufSrc + offset;
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_inputBufferToCPU, MCUXCLBUFFER_STATUS_OK);
+
+}
+
+
+/**
+ * \brief Perform a read from the buffer
+ *
+ * \param bufSrc     Input buffer from which the data shall be read.
+ * \param offset     Offset into the buffer at which the read operation shall start.
+ * \param pDst       Pointer to the memory location where the data will be stored.
+ * \param byteLength Amount of bytes that will be read.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_read)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_read(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *pDst, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_read);
+
+  MCUX_CSSL_DI_EXPUNGE(memCpyParams, ((uint32_t) pDst) + ((uint32_t) bufSrc) + byteLength + offset);
+  MCUX_CSSL_FP_FUNCTION_CALL(copy_status ,mcuxClMemory_copy_int(pDst, &bufSrc[offset], byteLength));
+  if(MCUXCLMEMORY_STATUS_OK != copy_status)
+  {
+      MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_read, MCUXCLBUFFER_STATUS_FAULT);
+  }
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_read, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_int)
+      );
+}
+
+/**
+ * \brief Perform a word-wise read from the buffer
+ *
+ * \param bufSrc     Input buffer from which the data shall be read.
+ * \param offset     Offset into the buffer at which the read operation shall start.
+ * \param pDst       Pointer to the memory location where the data will be stored.
+ * \param byteLength Amount of bytes that will be read.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_read_word)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_read_word(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *pDst, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_read_word);
+
+  MCUX_CSSL_DI_EXPUNGE(memCpyParams, ((uint32_t) pDst) + ((uint32_t) bufSrc) + byteLength + offset);
+  MCUX_CSSL_FP_FUNCTION_CALL(copy_status, mcuxClMemory_copy_words_int(pDst, &bufSrc[offset], byteLength));
+  if(MCUXCLMEMORY_STATUS_OK != copy_status)
+  {
+      MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_read_word, MCUXCLBUFFER_STATUS_FAULT);
+  }
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_read_word, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_words_int)
+      );
+}
+
+/**
+ * \brief Perform an read with endianess reversal from the buffer
+ *
+ * \param bufSrc     Input buffer from which the data shall be read.
+ * \param offset     Offset into the buffer at which the read operation shall start.
+ * \param pDst       Pointer to the memory location where the data will be stored.
+ * \param byteLength Amount of bytes that will be read.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_read_reverse)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_read_reverse(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *pDst, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_read_reverse);
+
+  MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pDst, &bufSrc[offset], byteLength);
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_read_reverse, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed));
+}
+
+/**
+ * \brief Perform a secure read from the buffer
+ *
+ * \param bufSrc     Input buffer from which the data shall be read.
+ * \param offset     Offset into the buffer at which the read operation shall start.
+ * \param pDst       Pointer to the memory location where the data will be stored.
+ * \param byteLength Amount of bytes that will be read.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_read_secure)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_read_secure(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *pDst, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_read_secure);
+
+  MCUXCLMEMORY_FP_MEMORY_COPY(pDst, &bufSrc[offset], byteLength);
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_read_secure, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy));
+}
+
+/**
+ * \brief Perform a secure read with endianess reversal from the buffer
+ *
+ * \param bufSrc     Input buffer from which the data shall be read.
+ * \param offset     Offset into the buffer at which the read operation shall start.
+ * \param pDst       Pointer to the memory location where the data will be stored.
+ * \param byteLength Amount of bytes that will be read.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_read_secure_reverse)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_read_secure_reverse(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *pDst, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_read_secure_reverse);
+
+  MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pDst, &bufSrc[offset], byteLength);
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_read_secure_reverse, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed));
+}
+
+
+/**
+ * \brief Perform a write to the buffer
+ *
+ * \param bufDst     Output buffer to which the data shall be written.
+ * \param offset     Offset into the buffer at which the write operation shall start.
+ * \param pSrc       Pointer to the memory location from where the data will be read.
+ * \param byteLength Amount of bytes that will be written.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_write)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_write(mcuxCl_Buffer_t bufDst, uint32_t offset, const uint8_t *pSrc, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_write);
+
+  MCUX_CSSL_DI_EXPUNGE(memCpyParams, ((uint32_t) pSrc) + ((uint32_t) bufDst) + byteLength + offset);
+  MCUX_CSSL_FP_FUNCTION_CALL(copy_status ,mcuxClMemory_copy_int(&bufDst[offset], pSrc, byteLength));
+  if(MCUXCLMEMORY_STATUS_OK != copy_status)
+  {
+      MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write, MCUXCLBUFFER_STATUS_FAULT);
+  }
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_int)
+      );
+}
+
+/**
+ * \brief Perform a word-wise write to the buffer
+ *
+ * \param bufDst     Output buffer to which the data shall be written.
+ * \param offset     Offset into the buffer at which the write operation shall start.
+ * \param pSrc       Pointer to the memory location from where the data will be read.
+ * \param byteLength Amount of bytes that will be written.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_write_word)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_write_word(mcuxCl_Buffer_t bufDst, uint32_t offset, const uint8_t *pSrc, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_write_word);
+
+  MCUX_CSSL_DI_EXPUNGE(memCpyParams, ((uint32_t) pSrc) + ((uint32_t) bufDst) + byteLength + offset);
+  MCUX_CSSL_FP_FUNCTION_CALL(copy_status, mcuxClMemory_copy_words_int(&bufDst[offset], pSrc, byteLength));
+  if(MCUXCLMEMORY_STATUS_OK != copy_status)
+  {
+      MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write_word, MCUXCLBUFFER_STATUS_FAULT);
+  }
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write_word, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_words_int)
+      );
+}
+
+
+/**
+ * \brief Perform a write with endianess reversal to the buffer
+ *
+ * \param bufDst     Output buffer to which the data shall be written.
+ * \param offset     Offset into the buffer at which the write operation shall start.
+ * \param pSrc       Pointer to the memory location from where the data will be read.
+ * \param byteLength Amount of bytes that will be written.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_write_reverse)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_write_reverse(mcuxCl_Buffer_t bufDst, uint32_t offset, const uint8_t *pSrc, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_write_reverse);
+
+  MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(&bufDst[offset], pSrc, byteLength);
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write_reverse, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed));
+}
+
+/**
+ * \brief Perform a secure write to the buffer
+ *
+ * \param bufDst     Output buffer to which the data shall be written.
+ * \param offset     Offset into the buffer at which the write operation shall start.
+ * \param pSrc       Pointer to the memory location from where the data will be read.
+ * \param byteLength Amount of bytes that will be written.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_write_secure)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_write_secure(mcuxCl_Buffer_t bufDst, uint32_t offset, const uint8_t *pSrc, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_write_secure);
+
+  MCUX_CSSL_DI_EXPUNGE(memCpyParams, ((uint32_t) pSrc) + ((uint32_t) bufDst) + byteLength + offset);
+  MCUX_CSSL_FP_FUNCTION_CALL(copy_status, mcuxClMemory_copy_secure_int(&bufDst[offset], pSrc, byteLength));
+
+  if(MCUXCLMEMORY_STATUS_OK != copy_status)
+  {
+      MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write_secure, MCUXCLBUFFER_STATUS_FAULT);
+  }
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write_secure, MCUXCLBUFFER_STATUS_OK,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_secure_int));
+}
+
+/**
+ * \brief Perform a secure write with endianess reversal to the buffer
+ *
+ * \param bufDst     Output buffer to which the data shall be written.
+ * \param offset     Offset into the buffer at which the write operation shall start.
+ * \param pSrc       Pointer to the memory location from where the data will be read.
+ * \param byteLength Amount of bytes that will be written.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_write_secure_reverse)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_write_secure_reverse(mcuxCl_Buffer_t bufDst, uint32_t offset, const uint8_t *pSrc, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_write_secure_reverse);
+
+  MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(&bufDst[offset], pSrc, byteLength);
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_write_secure_reverse, MCUXCLBUFFER_STATUS_OK, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed));
+}
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLBUFFER_INTERNAL_POINTER_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer.h
new file mode 100644
index 0000000000..4e9c55580d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer.h
@@ -0,0 +1,266 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2024 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxClBuffer.h
+ * \brief Provides the API for the CL buffer types.
+ */
+
+#ifndef MCUXCLBUFFER_H_
+#define MCUXCLBUFFER_H_
+
+#include <mcuxClCore_Platform.h>
+
+#include <mcuxClBuffer_Constants.h>
+
+/* Include the actual implementation of the flow protection mechanism. */
+#include <mcuxClBuffer_Impl.h>
+
+
+/**
+ * \addtogroup mcuxClAPI MCUX CL -- API
+ *
+ * \defgroup mcuxClBuffer Buffer API
+ * \brief CL Buffer types.
+ * \ingroup mcuxClAPI
+ */
+
+/**
+ * \defgroup clBufInit Buffer initialization functionality
+ * \brief Buffer initialization functionality.
+ * \ingroup mcuxClBuffer
+ *
+ * Two sets of default buffer initializations are provided, each with
+ * read-only (RO, for mcuxCl_InputBuffer_t) and read-write (RW, for mcuxCl_Buffer_t)
+ * variants:
+ *  - Plain: basic CPU copy operations (aligned when possible)
+ *  - DMA: utilizing DMA peripherals
+ *
+ * \note The DMA variants will be mapped to plain for buffer implementations
+ * that do not support DMA operations.
+ *
+ * Additionally a custom initializer is provided as well as some aliases
+ * that can be used as shorthand notation.
+ */
+
+/**
+ * \def MCUXCLBUFFER_INIT
+ * \brief Initialize an input/output buffer (mcuxCl_Buffer_t).
+ * \api
+ * \ingroup clBufInit
+ *
+ * This macro is an alias for \p MCUXCLBUFFER_INIT_RW.
+ *
+ * \see MCUXCLBUFFER_INIT_RW
+ *
+ * \param name the name to be used for the buffer variable
+ * \param info pointer to a data structure that holds relevant information for the handler
+ * \param ptr  pointer to the memory location of the buffer
+ * \param size size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_INIT(name, info, ptr, size) \
+  MCUXCLBUFFER_INIT_RW(name, info, ptr, size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_RO
+ * \brief Initialize an input buffer (mcuxCl_InputBuffer_t) with plain CPU handling.
+ * \api
+ * \ingroup clBufInit
+ *
+ * This macro can be used to initialize an input buffer that will be handled
+ * using plain CPU operations.
+ *
+ * \param name the name to be used for the buffer variable
+ * \param info pointer to a data structure that holds relevant information for the handler
+ * \param ptr  pointer to the memory location of the buffer
+ * \param size size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_INIT_RO(name, info, ptr, size) \
+  MCUXCLBUFFER_INIT_PLAIN_RO_IMPL(name, info, ptr, size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_RW
+ * \brief Initialize an input/output buffer (mcuxCl_Buffer_t) with plain CPU handling.
+ * \api
+ * \ingroup clBufInit
+ *
+ * This macro can be used to initialize an input/output buffer that will be
+ * handled using plain CPU operations.
+ *
+ * \param name the name to be used for the buffer variable
+ * \param info pointer to a data structure that holds relevant information for the handler
+ * \param ptr  pointer to the memory location of the buffer
+ * \param size size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_INIT_RW(name, info, ptr, size) \
+  MCUXCLBUFFER_INIT_PLAIN_RW_IMPL(name, info, ptr, size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_DMA_RO
+ * \brief Initialize an input buffer (mcuxCl_InputBuffer_t) with DMA handling.
+ * \api
+ * \ingroup clBufInit
+ *
+ * This macro can be used to initialize an input buffer that will be handled
+ * using DMA operations.
+ *
+ * \note DMA operations are only supported for object-oriented buffer implementations.
+ *
+ * \param name the name to be used for the buffer variable
+ * \param info pointer to a data structure that holds relevant information for the handler
+ * \param ptr  pointer to the memory location of the buffer
+ * \param size size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_INIT_DMA_RO(name, info, ptr, size) \
+  MCUXCLBUFFER_INIT_DMA_RO_IMPL(name, info, ptr, size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_DMA_RW
+ * \brief Initialize an input/output buffer (mcuxCl_Buffer_t) with DMA handling.
+ * \api
+ * \ingroup clBufInit
+ *
+ * This macro can be used to initialize an input/output buffer that will be
+ * handled using DMA operations.
+ *
+ * \note DMA operations are only supported for object-oriented buffer implementations.
+ *
+ * \param name the name to be used for the buffer variable
+ * \param info pointer to a data structure that holds relevant information for the handler
+ * \param ptr  pointer to the memory location of the buffer
+ * \param size size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_INIT_DMA_RW(name, info, ptr, size) \
+  MCUXCLBUFFER_INIT_DMA_RW_IMPL(name, info, ptr, size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_DMA
+ * \brief Initialize an input/output buffer (mcuxCl_Buffer_t) with DMA handling.
+ * \api
+ * \ingroup clBufInit
+ * 
+ * This macro is an alias for \p MCUXCLBUFFER_INIT_RW.
+ * 
+ * \see MCUXCLBUFFER_INIT_RW
+ *
+ * \param name the name to be used for the buffer variable
+ * \param info pointer to a data structure that holds relevant information for the handler
+ * \param ptr  pointer to the memory location of the buffer
+ * \param size size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_INIT_DMA(name, info, ptr, size) \
+  MCUXCLBUFFER_INIT_DMA_RW(name, info, ptr, size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_CUSTOM
+ * \brief Initialize an input/output buffer with custom handler
+ * \api
+ * \ingroup clBufInit
+ *
+ * This macro can be used to initialize an input/output buffer with a custom
+ * handler.
+ *
+ * \note Custom handlers are only supported for object-oriented buffer
+ * implementations.
+ *
+ * \param name    the name to be used for the buffer variable
+ * \param handler the callback function that will handle the buffer operations
+ * \param info    pointer to a data structure that holds relevant information for the handler
+ * \param spec    specification of the buffer properties
+ * \param ptr     pointer to the memory location of the buffer
+ * \param size    size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_INIT_CUSTOM(name, handler, info, spec, ptr, size) \
+  MCUXCLBUFFER_INIT_CUSTOM_IMPL(name, handler, info, spec, ptr, size)
+
+/**
+ * \defgroup clBufUpdate Buffer manipulation functionality
+ * \brief Input/output buffer manipulation functionality.
+ * \ingroup mcuxClBuffer
+ */
+
+/**
+ * \def MCUXCLBUFFER_UPDATE
+ * \brief Update the buffer pointer with the given offset.
+ * \api
+ * \ingroup clBufUpdate
+ *
+ * \param name   the name of the buffer variable to update.
+ * \param offset the amount of bytes that the buffer pointer should be moved.
+ */
+#define MCUXCLBUFFER_UPDATE(name, offset) \
+  MCUXCLBUFFER_UPDATE_IMPL(name, offset)
+
+/**
+ * \def MCUXCLBUFFER_DERIVE_RO
+ * \brief Derive a new input buffer object from an existing one (updated with the given offset).
+ * \api
+ * \ingroup clBufUpdate
+ *
+ * \param name     the name of the buffer variable to create.
+ * \param original the name of the buffer variable that will be cloned.
+ * \param offset   the amount of bytes that the buffer pointer should be moved.
+ */
+#define MCUXCLBUFFER_DERIVE_RO(name, original, offset) \
+  MCUXCLBUFFER_DERIVE_RO_IMPL(name, original, offset)
+
+/**
+ * \def MCUXCLBUFFER_DERIVE_RW
+ * \brief Derive a new input/output buffer object from an existing one (updated with the given offset).
+ * \api
+ * \ingroup clBufUpdate
+ *
+ * \param name     the name of the buffer variable to create.
+ * \param original the name of the buffer variable that will be cloned.
+ * \param offset   the amount of bytes that the buffer pointer should be moved.
+ */
+#define MCUXCLBUFFER_DERIVE_RW(name, original, offset) \
+  MCUXCLBUFFER_DERIVE_RW_IMPL(name, original, offset)
+
+/**
+ * \def MCUXCLBUFFER_SET
+ * \brief Update the buffer pointer the a new memory location.
+ * \api
+ * \ingroup clBufUpdate
+ *
+ * \param name the name of the buffer variable to update
+ * \param ptr  pointer to the memory location of the buffer
+ * \param size size of the buffer - RFU
+ */
+#define MCUXCLBUFFER_SET(name, ptr, size) \
+  MCUXCLBUFFER_SET_IMPL(name, ptr, size)
+
+/**
+ * \def MCUXCLBUFFER_GET
+ * \brief Get the pointer of the buffer
+ * \api
+ * \ingroup clBufUpdate
+ *
+ * \param name the name of the buffer variable
+ */
+#define MCUXCLBUFFER_GET(name) \
+  MCUXCLBUFFER_GET_IMPL(name)
+
+/**
+ * \def MCUXCLBUFFER_IS_NULL
+ * \brief Check the buffer and its pointer against NULL
+ * \api
+ * \ingroup clBufUpdate
+ *
+ * \param name the name of the buffer variable
+ */
+#define MCUXCLBUFFER_IS_NULL(name) \
+  MCUXCLBUFFER_IS_NULL_IMPL(name)
+
+
+#endif /* MCUXCLBUFFER_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Cfg.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Cfg.h
new file mode 100644
index 0000000000..9603792554
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Cfg.h
@@ -0,0 +1,48 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxClBuffer_Cfg.h
+ * \brief Configuration of the implementation for the buffer types.
+ */
+
+#ifndef MCUXCLBUFFER_CFG_H_
+#define MCUXCLBUFFER_CFG_H_
+
+#include <mcuxClCore_Platform.h>
+
+/**
+ * \addtogroup mcuxClCFG MCUX CL -- Configurations
+ *
+ * \defgroup mcuxClBuffer_CFG Buffer Configuration
+ * \brief Configuration options for the buffer types.
+ * \ingroup mcuxClCFG
+ */
+
+/**
+ * \def MCUXCLBUFFER_USE_OBJECT
+ * \brief If set to 1, use the object oriented buffer implementation.
+ * \ingroup mcuxClBuffer_CFG
+ */
+    #define MCUXCLBUFFER_USE_OBJECT 0
+
+/**
+ * \def MCUXCLBUFFER_USE_POINTER
+ * \brief If set to 1, use the plain C pointer buffer implementation.
+ * \ingroup mcuxClBuffer_CFG
+ */
+    #define MCUXCLBUFFER_USE_POINTER 1
+
+/* Basic configuration sanity check */
+
+#endif /* MCUXCLBUFFER_CFG_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Constants.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Constants.h
new file mode 100644
index 0000000000..ec4d321a3f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Constants.h
@@ -0,0 +1,41 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** \file  mcuxClBuffer_Constants.h
+ *  \brief Constants for use with the mcuxClBuffer component */
+
+#ifndef MCUXCLBUFFER_CONSTANTS_H_
+#define MCUXCLBUFFER_CONSTANTS_H_
+
+#include <mcuxClCore_Platform.h>
+
+/**
+ * \defgroup clBufferConstants Buffer constants
+ * \brief Buffer constants
+ * \ingroup mcuxClBuffer
+ */
+
+/**
+ * \brief Buffer status code
+ *
+ * This type provides information about the status of the Buffer operation that
+ * has been performed.
+ */
+typedef uint32_t mcuxClBuffer_Status_t;
+
+/* Error codes */
+#define MCUXCLBUFFER_STATUS_ERROR                        ((mcuxClBuffer_Status_t) 0x01235330u)
+#define MCUXCLBUFFER_STATUS_OK                           ((mcuxClBuffer_Status_t) 0x01232E03u)
+#define MCUXCLBUFFER_STATUS_FAULT                        ((mcuxClBuffer_Status_t) 0x0123F0F0u)
+
+#endif /* MCUXCLBUFFER_CONSTANTS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Impl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Impl.h
new file mode 100644
index 0000000000..7909b5b9e5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Impl.h
@@ -0,0 +1,36 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxClBuffer_Impl.h
+ * \brief Selection of the implementation for the buffer types.
+ */
+
+#ifndef MCUXCLBUFFER_IMPL_H_
+#define MCUXCLBUFFER_IMPL_H_
+
+#include <mcuxClCore_Platform.h>
+
+/* Include the configuration for the buffer types. */
+#include <mcuxClBuffer_Cfg.h>
+
+/* Include the selected implementation of the buffer types. */
+#if defined(MCUXCLBUFFER_USE_OBJECT) && (1 == MCUXCLBUFFER_USE_OBJECT)
+#  include <mcuxClBuffer_Object.h>
+#elif defined(MCUXCLBUFFER_USE_POINTER) && (1 == MCUXCLBUFFER_USE_POINTER)
+#  include <mcuxClBuffer_Pointer.h>
+#else
+#  error "No buffer type implementation found/configured."
+#endif
+
+#endif /* MCUXCLBUFFER_IMPL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Pointer.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Pointer.h
new file mode 100644
index 0000000000..0a8230ab91
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/inc/mcuxClBuffer_Pointer.h
@@ -0,0 +1,231 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2024 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxClBuffer_Pointer.h
+ * \brief Provides the implementation for the basic C pointer buffer types.
+ */
+
+#ifndef MCUXCLBUFFER_POINTER_H_
+#define MCUXCLBUFFER_POINTER_H_
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxCsslFlowProtection.h>
+
+/**
+ * \addtogroup mcuxClAPI MCUX CL -- API
+ *
+ * \addtogroup mcuxClBuffer Buffer API
+ * \brief Essential types and functionality.
+ * \ingroup mcuxClAPI
+ */
+
+/**
+ * \defgroup clBufferTypes Buffer type definitions
+ * \brief Types used by the buffer operations.
+ * \ingroup mcuxClBuffer
+ */
+
+/**
+ * \brief Input buffer type
+ * \ingroup clBufferTypes
+ *
+ * This type provides a pointer to the memory location that should be used to
+ * read input data from.
+ */
+typedef const uint8_t * mcuxCl_InputBuffer_t;
+
+/**
+ * \brief Input/output buffer type
+ * \ingroup clBufferTypes
+ *
+ * This type provides a pointer to the memory location that can be used for
+ * both reading input data and writing output data.
+ */
+typedef uint8_t * mcuxCl_Buffer_t;
+
+/**
+ * \brief Perform a read from the buffer
+ *
+ * \param bufSrc     Input buffer from which the data shall be read.
+ * \param offset     Offset into the buffer at which the read operation shall start.
+ * \param pDst       Pointer to the memory location where the data will be stored.
+ * \param byteLength Amount of bytes that will be read.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClBuffer_import)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_import(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *pDst, uint32_t byteLength);
+
+/**
+ * \brief Perform a write to the buffer
+ *
+ * \param bufDst     Output buffer to which the data shall be written.
+ * \param offset     Offset into the buffer at which the write operation shall start.
+ * \param pSrc       Pointer to the memory location from where the data will be read.
+ * \param byteLength Amount of bytes that will be written.
+ * \return Status of the operation.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClBuffer_export)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_export(mcuxCl_Buffer_t bufDst, uint32_t offset, const uint8_t *pSrc, uint32_t byteLength);
+
+/**
+ * \def MCUXCLBUFFER_INIT_PLAIN_RO_IMPL
+ * \brief Initialize an input buffer with plain CPU handling.
+ * \ingroup clBufInit
+ *
+ * This macro can be used to initialize an input buffer that will be handled
+ * using plain CPU operations.
+ *
+ * \param _name the name to be used for the buffer variable
+ * \param _info unused for the current implementation
+ * \param _ptr  pointer to the memory location of the buffer
+ * \param _size unused for the current implementation
+ */
+#define MCUXCLBUFFER_INIT_PLAIN_RO_IMPL(_name, _info, _ptr, _size) \
+  mcuxCl_InputBuffer_t (_name) = (mcuxCl_InputBuffer_t)(_ptr)
+
+/**
+ * \def MCUXCLBUFFER_INIT_PLAIN_RW_IMPL
+ * \brief Initialize an input/output buffer with plain CPU handling.
+ * \ingroup clBufInit
+ *
+ * This macro can be used to initialize an input/output buffer that will be
+ * handled using plain CPU operations.
+ *
+ * \param _name the name to be used for the buffer variable
+ * \param _info unused for the current implementation
+ * \param _ptr  pointer to the memory location of the buffer
+ * \param _size unused for the current implementation
+ */
+#define MCUXCLBUFFER_INIT_PLAIN_RW_IMPL(_name, _info, _ptr, _size) \
+  mcuxCl_Buffer_t (_name) = (mcuxCl_Buffer_t)(_ptr)
+
+/**
+ * \def MCUXCLBUFFER_INIT_DMA_RO_IMPL
+ * \brief DMA handling is not supported. Initialize an input buffer with plain CPU handling.
+ * \ingroup clBufInit
+ *
+ * This buffer implementation does not support DMA handling, so CPU handling is used as a fallback.
+ * This macro is an alias for \p MCUXCLBUFFER_INIT_PLAIN_RO_IMPL.
+ *
+ * \param _name the name to be used for the buffer variable
+ * \param _info unused for the current implementation
+ * \param _ptr  pointer to the memory location of the buffer
+ * \param _size unused for the current implementation
+ */
+#define MCUXCLBUFFER_INIT_DMA_RO_IMPL(_name, _info, _ptr, _size) \
+  MCUXCLBUFFER_INIT_PLAIN_RO_IMPL(_name, _info, _ptr, _size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_DMA_RW_IMPL
+ * \brief DMA handling is not supported. Initialize an input/output buffer with plain CPU handling.
+ * \ingroup clBufInit
+ *
+ * This buffer implementation does not support DMA handling, so CPU handling is used as a fallback.
+ * This macro is an alias for \p MCUXCLBUFFER_INIT_PLAIN_RW_IMPL.
+ *
+ * \param _name the name to be used for the buffer variable
+ * \param _info unused for the current implementation
+ * \param _ptr  pointer to the memory location of the buffer
+ * \param _size unused for the current implementation
+ */
+#define MCUXCLBUFFER_INIT_DMA_RW_IMPL(_name, _info, _ptr, _size) \
+  MCUXCLBUFFER_INIT_PLAIN_RW_IMPL(_name, _info, _ptr, _size)
+
+/**
+ * \def MCUXCLBUFFER_INIT_CUSTOM_IMPL
+ * \brief Usage of custom handler is not supported. Initialize an input/output buffer with plain CPU handling.
+ * \ingroup clBufInit
+ *
+ * This macro is an alias for \p MCUXCLBUFFER_INIT_PLAIN_RW_IMPL.
+ *
+ * \param _name    the name to be used for the buffer variable
+ * \param _handler unused for the current implementation
+ * \param _info    unused for the current implementation
+ * \param _spec    unused for the current implementation
+ * \param _ptr     pointer to the memory location of the buffer
+ * \param _size    unused for the current implementation
+ */
+#define MCUXCLBUFFER_INIT_CUSTOM_IMPL(_name, _handler, _info, _spec, _ptr, _size) \
+    MCUXCLBUFFER_INIT_PLAIN_RW_IMPL(_name, _info, _ptr, _size)
+
+
+/**
+ * \def MCUXCLBUFFER_UPDATE_IMPL
+ * \brief Update the buffer pointer with the given offset.
+ * \ingroup clBufUpdate
+ *
+ * \param _name   the name of the buffer variable to update
+ * \param _offset the amount of bytes that the buffer pointer should be moved.
+ */
+#define MCUXCLBUFFER_UPDATE_IMPL(_name, _offset) \
+  do { (_name) += (_offset); } while(false)
+
+/**
+ * \def MCUXCLBUFFER_DERIVE_RO_IMPL
+ * \brief Derive a new input buffer object from an existing one (updated with the given offset).
+ * \ingroup clBufUpdate
+ *
+ * \param _name     the name of the buffer variable to create.
+ * \param _original the name of the buffer variable that will be cloned.
+ * \param _offset   the amount of bytes that the buffer pointer should be moved.
+ */
+#define MCUXCLBUFFER_DERIVE_RO_IMPL(_name, _original, _offset) \
+  mcuxCl_InputBuffer_t (_name) = (mcuxCl_InputBuffer_t) &(_original)[_offset]
+
+/**
+ * \def MCUXCLBUFFER_DERIVE_RW_IMPL
+ * \brief Derive a new input/output buffer object from an existing one (updated with the given offset).
+ * \ingroup clBufUpdate
+ *
+ * \param _name     the name of the buffer variable to create.
+ * \param _original the name of the buffer variable that will be cloned.
+ * \param _offset   the amount of bytes that the buffer pointer should be moved.
+ */
+#define MCUXCLBUFFER_DERIVE_RW_IMPL(_name, _original, _offset) \
+  mcuxCl_Buffer_t (_name) = (mcuxCl_Buffer_t) &(_original)[_offset]
+
+/**
+ * \def MCUXCLBUFFER_SET_IMPL
+ * \brief Update the buffer pointer the a new memory location.
+ * \ingroup clBufUpdate
+ *
+ * \param _name the name of the buffer variable to update
+ * \param _ptr  pointer to the memory location of the buffer
+ * \param _size unused for the current implementation
+ */
+#define MCUXCLBUFFER_SET_IMPL(_name, _ptr, _size) \
+  do { (_name) = (_ptr); } while(false)
+
+/**
+ * \def MCUXCLBUFFER_GET_IMPL
+ * \brief Get the pointer of the buffer
+ * \ingroup clBufUpdate
+ *
+ * \param _name the name of the buffer variable
+ */
+#define MCUXCLBUFFER_GET_IMPL(_name) \
+  (_name)
+
+/**
+ * \def MCUXCLBUFFER_IS_NULL_IMPL
+ * \brief Check the buffer pointer against NULL
+ * \ingroup clBufUpdate
+ *
+ * \param _name the name of the buffer variable
+ */
+#define MCUXCLBUFFER_IS_NULL_IMPL(_name) \
+  (NULL == MCUXCLBUFFER_GET_IMPL(_name))
+
+
+#endif /* MCUXCLBUFFER_POINTER_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/src/mcuxClBuffer.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/src/mcuxClBuffer.c
new file mode 100644
index 0000000000..60eee3fd26
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClBuffer/src/mcuxClBuffer.c
@@ -0,0 +1,47 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxClBuffer.c
+ * \brief Provides the internal implementation for the plain C pointer buffer types.
+ */
+
+
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Platform.h>
+
+#include <mcuxClBuffer.h>
+#include <mcuxCsslDataIntegrity.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <internal/mcuxClBuffer_Internal.h>
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_export)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_export(mcuxCl_Buffer_t bufDst, uint32_t offset, const uint8_t *pSrc, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_export);
+
+  MCUX_CSSL_FP_FUNCTION_CALL(status, mcuxClBuffer_write(bufDst, offset, pSrc, byteLength));
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_export, status, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClBuffer_write));
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClBuffer_import)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClBuffer_Status_t) mcuxClBuffer_import(mcuxCl_InputBuffer_t bufSrc, uint32_t offset, uint8_t *pDst, uint32_t byteLength)
+{
+  MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClBuffer_import);
+
+  MCUX_CSSL_FP_FUNCTION_CALL(status, mcuxClBuffer_read(bufSrc, offset, pDst, byteLength));
+
+  MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClBuffer_import, status, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClBuffer_read));
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Examples.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Examples.h
new file mode 100644
index 0000000000..dedc579b99
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Examples.h
@@ -0,0 +1,89 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#ifndef MCUXCLCORE_EXAMPLES_H_
+#define MCUXCLCORE_EXAMPLES_H_
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_Macros.h>
+#include <mcuxCsslFlowProtection.h>
+
+
+/**
+ * \def MCUXCLEXAMPLE_FUNCTION
+ * \brief Macro to indicate that the symbol is an example function.
+ */
+// TODO CLNS-3599: #define MCUXCLEXAMPLE_FUNCTION(_name) uint32_t _name(void)
+#define MCUXCLEXAMPLE_FUNCTION(_name) \
+MCUX_CSSL_ANALYSIS_START_PATTERN_EXAMPLE_FUNCTION() \
+bool _name(void) \
+MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXAMPLE_FUNCTION()
+
+/**
+ * \def MCUXCLEXAMPLE_STATUS_OK
+ * \brief Example execution completed successfully.
+ */
+#define MCUXCLEXAMPLE_STATUS_OK      true // TODO CLNS-3599: 0xC001C0DEu
+
+/**
+ * \def MCUXCLEXAMPLE_OK
+ * \brief Example execution completed successfully.
+ * \deprecated{Replaced by MCUXCLEXAMPLE_STATUS_OK}
+ */
+#define MCUXCLEXAMPLE_OK      MCUXCLEXAMPLE_STATUS_OK
+
+/**
+ * \def MCUXCLEXAMPLE_STATUS_ERROR
+ * \brief Example execution resulted in an unexpected error.
+ */
+#define MCUXCLEXAMPLE_STATUS_ERROR   false // TODO CLNS-3599: 0xEEEEEEEEu
+
+/**
+ * \def MCUXCLEXAMPLE_ERROR
+ * \brief Example execution resulted in an unexpected error.
+ * \deprecated{Replaced by MCUXCLEXAMPLE_STATUS_ERROR}
+ */
+#define MCUXCLEXAMPLE_ERROR   MCUXCLEXAMPLE_STATUS_ERROR
+
+
+/**
+ * \def MCUXCLEXAMPLE_STATUS_FAILURE
+ * \brief Example execution resulted in an expected failure.
+ */
+#define MCUXCLEXAMPLE_STATUS_FAILURE  false // TODO CLNS-3599: 0xFFFFFFFFu
+
+/**
+ * \def MCUXCLEXAMPLE_FAILURE
+ * \brief Example execution resulted in an expected failure.
+ * \deprecated{Replaced by MCUXCLEXAMPLE_STATUS_FAILURE}
+ */
+#define MCUXCLEXAMPLE_FAILURE  MCUXCLEXAMPLE_STATUS_FAILURE
+
+/**
+ * \brief Assert whether two buffers are equal.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCore_assertEqual)
+static inline bool mcuxClCore_assertEqual(const uint8_t * const x, const uint8_t * const y, uint32_t length)
+{
+  for (uint32_t i = 0; i < length; ++i)
+  {
+    if (x[i] != y[i])
+    {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+#endif /* MCUXCLCORE_EXAMPLES_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_FunctionIdentifiers.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_FunctionIdentifiers.h
new file mode 100644
index 0000000000..36ca796e68
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_FunctionIdentifiers.h
@@ -0,0 +1,5997 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2024 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClCore_FunctionIdentifiers.h
+ * @brief Definition of function identifiers for the flow protection mechanism.
+ *
+ * @note This file might be post-processed to update the identifier values to
+ * proper/secure values.
+ */
+
+#ifndef MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
+#define MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+#include <mcuxCsslAnalysis.h>
+
+MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER()
+
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwVersion                                        (0x6366u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwConfig                                         (0x4C37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwState                                          (0x7907u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Enable_Async                                        (0x44DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Reset_Async                                         (0x5457u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Disable                                             (0x466Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntEnableFlags                                   (0x0DB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetIntEnableFlags                                   (0x4E2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetIntFlags                                       (0x0FB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntFlags                                         (0x55CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_WaitForOperation                                    (0x34B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_LimitedWaitForOperation                             (0x6CE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetErrorFlags                                     (0x710Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorCode                                        (0x7456u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorLevel                                       (0x59D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_Async                                          (0x59D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Enable                                    (0x496Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Disable                                   (0x23CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_ShaDirect                                      (0x7C29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cipher_Async                                        (0x13D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyGen_Async                                     (0x2E95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchange_Async                                (0x5762u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchangeInt_Async                             (0x555Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccSign_Async                                       (0x3C36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerify_Async                                     (0x5B0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerifyInt_Async                                  (0x62ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp                                          (0x5578u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp_SqrMultAws                               (0x067Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Init_Async                                     (0x607Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_PartialInit_Async                              (0x035Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateAad_Async                                (0x0F59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateData_Async                               (0x2E9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Finalize_Async                                 (0x2DA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cmac_Async                                          (0x1793u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_LoadConfig_Async                     (0x693Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_Trim_Async                           (0x09BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hmac_Async                                          (0x4BE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Rfc5869_Async                                  (0x5B92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp800108_Async                                 (0x27A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async          (0x3F84u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async           (0x7545u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyDelete_Async                                     (0x58F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvision_Async                                  (0x5ED0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvisionRom_Async                               (0x64B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImport_Async                                     (0x1397u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImportPuk_Async                                  (0x2CAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyExport_Async                                     (0x258Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_handleKeyExportError                                (0x46B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequest_Async                               (0x4D9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequestRaw_Async                            (0x62D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoad_Async                          (0x2756u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async                       (0x42F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async                      (0x62E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed             (0x37D0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_Reseed                     (0x5939u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_Init_Async                                     (0x3BC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandomWord                                  (0x3AC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandom                                      (0x49D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetKeyProperties                                    (0x7E14u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_compute                                            (0x2DAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_compare                                            (0x42DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_verify                                             (0x3D45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_init                                               (0x416Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_process                                            (0x5873u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_finish                                             (0x17D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_selftest                                           (0x68F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_export_state                                       (0x7871u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_import_state                                       (0x79C4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Md5                                 (0x25CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Md5                                 (0x29F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Md5                                  (0x396Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha1                                (0x61B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha1                                (0x7196u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha1                                 (0x52D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha224                              (0x7958u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha224                              (0x6B19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha224                               (0x1A76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha256                              (0x5AC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha256                              (0x4F1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha256                               (0x39C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha384                              (0x4E5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha384                              (0x115Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha384                               (0x512Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha512                              (0x28E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha512                              (0x15E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha512                               (0x54CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3_shake                          (0x4D1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3_shake                          (0x1B8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3_shake                           (0x1EC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3                                (0x7326u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3                                (0x3B94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3                                 (0x2F49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_finishAbsorb                          (0x25F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_squeeze                               (0x2D4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_createShakeAlgorithm                          (0x5B23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_Sha2                              (0x784Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_Sha2                               (0x076Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_Sha2                              (0x23B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_MiyaguchiPreneel                  (0x45F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_MiyaguchiPreneel                  (0x5C1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_MiyaguchiPreneel                   (0x166Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_Sha2_DmaBlocking                   (0x40DFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_Sha2_DmaBlocking                  (0x5336u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_process_Sha2                              (0x36C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_finish_Sha2                               (0x73B0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2                              (0x4E33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2_Truncated                    (0x28F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2_FullBlocks                   (0x6C8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2_Padding                      (0x71CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_Sha2_Prepare_Truncated                    (0x12BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_process_Sha2_FullBlocks                   (0x5966u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_finish_Sha2_Padding                       (0x15ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_dmaProtectionAddressReadback              (0x5C71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha256                        (0x718Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha384                        (0x3B0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2                                 (0x195Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2_direct                          (0x4EACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_md5                                    (0x2CE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha1                                   (0x70B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha256                                 (0x72C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha512                                 (0x7B82u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_keccak                                 (0x54DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha3_Keccak                           (0x3627u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha1                                  (0x33C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha256                                (0x3A0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha512                                (0x3E16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha                                (0x6F12u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha                                (0x459Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha                                 (0x33ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha3                               (0x0FE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha3                               (0x2AF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha3                                (0x4771u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ltc_oneShot_Sha3_core                         (0x2973u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneshot_SecSha_init                           (0x435Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_compute                                             (0x41AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_init                                                (0x6A72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_process                                             (0x5396u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_generate                                            (0x1A6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_finish                                              (0x6B0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_generate_shake                               (0x271Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_init_sha3_shake                                (0x22EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_process_sha3_shake                             (0x2A37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_oneshot_sha3_shake                             (0x0E7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_finish_shake                                   (0x3572u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadCopro                                           (0x2579u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadMemory                                          (0x7962u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_flush                                               (0x26ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_setKeyproperties                                    (0x3879u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_LoadFuncPtr_t                                       (0x55C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_FlushFuncPtr_t                                      (0x476Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_init                                                (0x3635u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_setProtection                                       (0x6C3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement                                           (0x7A19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect                                             (0x33A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_compute                                             (0x22F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_compare                                             (0x7686u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_init                                                (0x16EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_process                                             (0x5CB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_finish                                              (0x4D59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_verify                                              (0x29F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compute                                        (0x36ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compare                                        (0x316Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_init                                           (0x6B1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_process                                        (0x29CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_finish                                         (0x70DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_verify                                         (0x3077u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_createGmacMode                                 (0x7CB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Oneshot                            (0x6783u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Init                               (0x528Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Update                             (0x475Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Finalize                           (0x7295u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Oneshot                          (0x2C9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Init                             (0x5F41u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Update                           (0x5786u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Finalize                         (0x6734u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Sw                                  (0x17D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Sw                                     (0x1D4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Sw                                   (0x47C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Sw                                 (0x323Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Els                                 (0x2B6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Els                                    (0x34D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Els                                  (0x66A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Els                                (0x4D2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_compute                                            (0x453Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_init                                               (0x43BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_process                                            (0x4BA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_finish                                             (0x7623u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_prepareHMACKey                                     (0x46E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_createHmacMode                                     (0x634Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_InitLocalUptrt                                     (0x6762u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_LeadingZeros                                       (0x0DE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ShiftModulus                                       (0x63E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_NDash                                              (0x236Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_QDash                                              (0x60BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_QSquared                                           (0x197Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModInv                                             (0x48DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModExp_SqrMultL2R                                  (0x791Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestInstantiate_Async                       (0x5C27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestExtract_Async                           (0x2E9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesEcb_Async                            (0x0B97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesCtr_Async                            (0x743Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_clear                                            (0x6BC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy                                             (0x126Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_set                                              (0x6AA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Initialize                                          (0x7319u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Deinitialize                                        (0x7315u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_GenerateUPTRT                                       (0x1C5Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Calc                                                (0x152Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcConst                                           (0x6693u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcFup                                             (0x2B71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForFinish                                       (0x255Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForReady                                        (0x05AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_init                                            (0x58B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRtf                                          (0x057Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_cleanup                                         (0x2CD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_destroy                                         (0x6A4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setSecurityOptions                              (0x0F63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRandom                                       (0x78B4u)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_sha512                                        (0x6E2Cu)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_aead                                          (0x4D4Du)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p256                                    (0x1769u)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p384                                    (0x7526u)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_hmac                                          (0x7067u)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_eckxh                                         (0x2D36u)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_extract                                  (0x61ABu)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ctr                                      (0x3E64u)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ecb                                      (0x415Fu)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ckdf                                          (0x3E83u)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_hkdf                                          (0x4E2Du)
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest                                               (0x4F58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Extract_Async                         (0x1F23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Expand_Async                          (0x7427u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Sp80056c_Async                                 (0x307Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_keyProv                                       (0x59AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_get_oem_cust_cert_dice_puk          (0x436Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_eck_sign                        (0x1F89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_enc_blk                         (0x7C43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_key_gen                         (0x653Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_sb_store_key                            (0x75E0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_rts_get_id_clns                 (0x5935u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_gen_oem_master_share                (0x5D83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_set_oem_master_share                (0x7D50u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_store_key                       (0x1AADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_rfc3394_wrap_manual                           (0x6B70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_ssf_insert_cert                 (0x15E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify_P384                                         (0x155Du)
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_cmac                                  (0x3E34u)
+#define MCUX_CSSL_FP_FUNCID_nboot_key_delete                                             (0x29DAu)
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_export_key                                   (0x6A4Eu)
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_is_loaded                                    (0x7744u)
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_init                                         (0x32BCu)
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_generate_rom_key                             (0x259Du)
+#define MCUX_CSSL_FP_FUNCID_nboot_cmac_authenticate_romapi                               (0x4CB5u)
+#define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_manifest                                      (0x76C4u)
+#define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_block                                         (0x36E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockVerify                                         (0x1BA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDecrypt_Start                                  (0x238Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockEncrypt_Start                                  (0x785Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockCrypt_Finish                                   (0x478Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDeriveKey                                      (0x54EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestImportPck                                   (0x437Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestDeriveKdk                                   (0x732Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_DeletePck                                           (0x5A5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Cleanup                                             (0x4ED8u)
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa                                 (0x6E62u)
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_romapi                          (0x2D99u)
+#define MCUX_CSSL_FP_FUNCID_nboot_sb3_img_authenticate_ecdsa                             (0x5AC6u)
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_internal                        (0x4E65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_none                                    (0x5A4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_ckdf                                    (0x588Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveTwoScalars                                (0x28DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble_NIST                              (0x4EB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult_NIST                                  (0x3672u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR_NIST                             (0x05E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd_NIST                                   (0x629Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SwitchEndianness_P384                               (0x7C8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_rts_insert_cert                         (0x0EBAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetRandomStartDelay                                 (0x134Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetRandomStartDelay                                 (0x51C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLock                                             (0x4AE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ReleaseLock                                         (0x61D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_IsLocked                                            (0x646Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetMasterUnlock                                     (0x30B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ConfigureCommandCRC                                 (0x4CF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetCommandCRC                                       (0x0B9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_VerifyVsRefCRC                                      (0x5C17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_RespGen_Async                                       (0x7256u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportBigEndianToPkc                                (0x5F30u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportBigEndianFromPkc                              (0x3D1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify                                              (0x5CA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SwitchEndianness                                    (0x36A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR                                  (0x65ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble                                   (0x7986u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd                                        (0x10FEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult                                       (0x59B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_RandomizeUPTRT                                      (0x1D87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ReRandomizeUPTRT                                    (0x5E54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SecurePointMult                                     (0x03BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwVersion                                      (0x0CCFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwState                                        (0x0B57u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntEnableFlags                                 (0x176Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntEnableFlags                                 (0x346Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ResetIntFlags                                     (0x3E29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntFlags                                       (0x5D2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Configuration                                     (0x4EE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Lock                                              (0x1177u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ConfigEval                                        (0x28EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Enroll                                            (0x31B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reconstruct                                       (0x3C9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_KeyGeneration                                     (0x3EC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntFlags                                       (0x6AD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_img_authenticate_ecdsa                              (0x788Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_dev_set_wrap_data                   (0x5369u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge              (0x4A6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_mcux          (0x48D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_oem          (0x12FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_TrailingZeros                                      (0x037Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ReduceModEven                                      (0x235Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_KeyGen                                              (0x6726u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportBigEndianFromPkc                        (0x19E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_BlindedSecretKeyGen_RandomWithExtraBits    (0x5C87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_ResetEventCounter                    (0x14EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_GetEventCounter                      (0x2D72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportBigEndianToPkc                          (0x271Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Sign                                                (0x59A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointMult                                           (0x5AD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_public                                              (0x7469u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privatePlain                                        (0x0E7Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_verify                                              (0x2D78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Verify_NoEMSA                                       (0x689Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_sign                                 (0x50DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Verify                                      (0x270Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivideOdd                                     (0x509Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssVerify                                           (0x69B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_mgf1                                                (0x7878u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privateCRT                                          (0x69D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_sign                                                (0x1C7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Sign_NoEMSA                                         (0x758Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssEncode                                           (0x3C66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SetupEnvironment                                    (0x318Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_SetupEnvironment                             (0x6A39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_SecureScalarMult_XZMontLadder                  (0x4D55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_X                                            (0x147Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeScalar                                 (0x5197u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeCoordinate                             (0x44F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_GenerateMultiplicativeBlinding                      (0x03BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLastDmaAddress                                   (0x3E51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_CompareDmaFinalOutputAddress                        (0x6A3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_KeyAgreement                                 (0x6933u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_KeyAgreement_Core                            (0x5E86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_GenerateKeyPair                              (0x097Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_GenerateKeyPair_Core                         (0x1EE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivide                                        (0x3CE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_init                                             (0x456Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_reseed                                           (0x4CE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_generate                                         (0x7D28u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_uninit                                           (0x41FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_selftest                                         (0x51E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_checkSecurityStrength                            (0x3B13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncPatch                                          (0x17D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncInit                                           (0x4E8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncGenerate                                       (0x20DFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_generate_internal                                (0x32E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPQDistance                                      (0x345Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ModInv                                              (0x178Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_MillerRabinTest                                     (0x5F42u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ComputeD                                            (0x6A36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_VerifyE                                             (0x53F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_GenerateProbablePrime                               (0x1ACEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Crt                                   (0x5F12u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_UpdateRefCRC                                        (0x05BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPrimeCandidate                                  (0x10EFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Plain                                 (0x58B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportLittleEndianToPkc                             (0x275Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportLittleEndianFromPkc                           (0x0BDAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportLittleEndianToPkc                       (0x64F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportLittleEndianFromPkc                     (0x16E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Weier_SetupEnvironment                              (0x54B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes                                 (0x05B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_crypt                                            (0x1BB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init                                             (0x7683u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_process                                          (0x61E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_finish                                           (0x60EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_None                                 (0x529Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Random                               (0x1B9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Decrypt                              (0x368Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method1                    (0x33C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method2                    (0x15BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_PKCS7                                (0x3974u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_None                              (0x5AA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Default                           (0x075Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method1                 (0x61B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method2                 (0x6D1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_PKCS7                             (0x7923u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Stream                            (0x3C6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesGcm                                (0x6731u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_crypt                                              (0x68BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init                                               (0x6EA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_process                                            (0x3E89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_process_adata                                      (0x19D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_finish                                             (0x21BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_verify                                             (0x6D0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesCcm                                (0x5633u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesCcmEls                               (0x25A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesGcmEls                               (0x3BA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_encrypt                                            (0x5C65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_decrypt                                            (0x137Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_encrypt                                       (0x3B89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_decrypt                                       (0x2F0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_Init                                               (0x73D0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_getEntropyInput                                    (0x34E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_checkConfig                                        (0x471Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_generate                            (0x246Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_init                                (0x5A1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_reseed                              (0x41E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_selftest                            (0x14DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_reseedAlgorithm                     (0x517Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateAlgorithm                   (0x42FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_generatePrHandler                (0x447Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_selftestAlgorithm                (0x54BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PTG3_selftestAlgorithm                      (0x435Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateOutput                      (0x6D8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_UpdateState                         (0x35A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_bcc                                 (0x5B54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_df                                  (0x13E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_updateEntropyInput                          (0x525Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_initFunction                       (0x70DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_reseedFunction                     (0x5CCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createTestFromNormalMode                    (0x72C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_initFunction                     (0x327Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_reseedFunction                   (0x3C33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_DRBG_AES_Internal_blockcipher               (0x5E98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PrDisabled      (0x541Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_selftestFunction                 (0x4755u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_instantiateAlgorithm                (0x22F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PTG3            (0x72A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_initFunction                      (0x6E2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_reseedFunction                    (0x20FEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_generateFunction                  (0x72A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_selftestFunction                  (0x6939u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createPatchMode                             (0x642Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_incV                                (0x09AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_selftestFunction                   (0x4BB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_HmacDrbg_instantiateAlgorithm               (0x370Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_HmacDrbg_UpdateState                        (0x5AB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_HmacDrbg_generateAlgorithm                  (0x11FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_HmacDrbg_generateOutput                     (0x185Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createCustomHmacDrbgMode                    (0x52B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_selftest_VerifyArrays                       (0x5D13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reset                                             (0x334Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_EngineEls                                   (0x3B46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair                               (0x2D6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature                             (0x43F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature                               (0x15DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_encrypt                              (0x3B70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Decode_decrypt                              (0x56CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_SetupEnvironment                              (0x31CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateCustomKeyType                      (0x4D6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateDomainParams                       (0x321Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_MAC_ISO9797_1_Method2                (0x5857u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepEncode                                          (0x6A27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepDecode                                          (0x2DC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPrng_init                                               (0x7346u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClPrng_generate                                           (0x44F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RecodeAndReorderScalar                              (0x39E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_FixScalarMult                                  (0x08EFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainFixScalarMult25519                        (0x612Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainFixScalarMult448                          (0x28BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectComb                             (0x0EAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PointDoubleEd25519                             (0x3E43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PointDoubleEd448                               (0x632Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_MixedPointAddEd25519                           (0x13EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_MixedPointAddEd448                             (0x70ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectML                               (0x4D99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_VarScalarMult                                  (0x05BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainVarScalarMult                             (0x7C54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PrecPointImportAndValidate                     (0x7323u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Ckdf                                                (0x19E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_verify                                        (0x72B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_crypt                                         (0x0F78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_finish                                        (0x0E8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process                                       (0x1375u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_init                                          (0x2A5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process_adata                                 (0x18D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateKeyPair                            (0x19D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_generate_keypair                                    (0x5BC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_GenerateKeyPair                       (0x47A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_Public                                      (0x195Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_UtilsAsym_ModularExponentiation             (0x47F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcInitialize                                 (0x294Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcDeinitialize                               (0x69C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_BlindedScalarMult                                   (0x2AD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_BlindedScalarMult                             (0x76A8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PointDecFct_SEC                            (0x3674u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_S5xyStub                      (0x0F96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_S5xyStub                    (0x05F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_selftest                                      (0x05F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_sign                                          (0x08FEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_verify                                        (0x46DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_init                                          (0x169Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_finish                                        (0x61DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_selftest                                         (0x3571u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_SetupEnvironment                           (0x132Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetVersionAndConfig                              (0x694Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetStatus                                        (0x346Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SyncReset                                        (0x3DC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntEnable                                     (0x0F2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetIntEnable                                     (0x683Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ClearIntStatus                                   (0x6D94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntStatus                                     (0x15E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_Lock                                             (0x68B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsLocked                                         (0x5653u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsIndexLocked                                    (0x3B19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_StartEnable                                      (0x725Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ContinueEnable                                   (0x0B5Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_LockIndex                                        (0x30BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ResetIndex                                       (0x1F19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_EndOperation                                     (0x17C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_CalcHashModN                                  (0x1A79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed25519                           (0x6CA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed448                             (0x4D56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_InitPrivKeyInputMode                          (0x536Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setResource                                     (0x3785u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_configure_job                                   (0x761Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_request                                         (0x559Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_release                                         (0x48EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_triggerUserCallback                             (0x1D36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_init                                           (0x7968u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_handle_interrupt                               (0x7634u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_request                                        (0x23D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_release                                        (0x78CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_linkKeyPair                                         (0x50F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithmeticOperation                                 (0x61A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointAdd                                    (0x0797u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_RemoveBlinding                                      (0x6CE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_ScalarMult                                  (0x599Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement_selftest                                  (0x5939u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDH_KeyAgreement                                   (0x10F7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_encrypt                                          (0x6279u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_decrypt                                          (0x1F1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_encrypt                                     (0x5659u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_decrypt                                     (0x119Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi                                 (0x6C3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi                                 (0x1DB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_encrypt_Sgi                            (0x4DD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_decrypt_Sgi                            (0x5EE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi                                 (0x3374u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finish_Sgi                                  (0x51ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveScalar                                    (0x1FA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PrivateKeyValidation                       (0x0DEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PublicKeyValidation                        (0x2F32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateHashPrefix                            (0x4957u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateProtocolDescriptor                    (0x19CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignatureModeDescriptor               (0x5BC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_PreHashMessage                                (0x396Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair_Core                          (0x436Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_Core                        (0x47E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_Core                          (0x57A1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_GenerateSignature                             (0x3CCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_VerifySignature                               (0x5574u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointSub                                    (0x395Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivation                                          (0x3B2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_108           (0x784Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_108                     (0x3D38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ISOIEC_18033_2           (0x1A3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ISOIEC_18033_2                     (0x15CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_56C           (0x45E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_OneStep             (0x7E84u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_TwoStep             (0x4CDAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ANSI_X9_63               (0x6AAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ANSI_X9_63                         (0x19ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_HKDF                     (0x7B84u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_HKDF                               (0x53ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_PBKDF2                   (0x3B25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_PBKDF2                             (0x2D33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivation_pbkdf2_computeHmac                       (0x74C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_IKEv2                    (0x3A66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_IKEv2                              (0x5D86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_Randombytes                                    (0x2D1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_XOF_Hash                                       (0x78D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Init_And_Absorb                       (0x2CCBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Absorb                                (0x64F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Squeeze                               (0x6C1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Keypair                                       (0x307Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Keypair_Core                                  (0x529Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Sign                                          (0x6DE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Verify                                        (0x24EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_checkInputs                                   (0x65D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_computeMu                                     (0x1573u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_performPolynomialArithmetic                   (0x58DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_Verify_checkInputs                   (0x2F1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_computeMu                            (0x136Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_performPolynomialArithmetic          (0x2C6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_reversed                                    (0x7B41u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcInitialize                                       (0x3DA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcDeinitialize                                     (0x1CB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_backup                                         (0x23E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_restore                                        (0x652Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_Sc_Backup                                      (0x2CC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_Sc_Restore                                     (0x507Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_resume                                          (0x3AB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_selftest                                            (0x42AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_selftest                                           (0x24AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Aes_encryptBlock                         (0x425Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Aes_decryptBlock                         (0x4B39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Aes_scheduleKey                          (0x2C7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Aes_handleIv                             (0x325Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Des_encryptBlock                         (0x4EE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Des_decryptBlock                         (0x706Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Des_scheduleKey                          (0x15D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Des_handleIv                             (0x05DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cbc_encrypt                              (0x2CE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cbc_decrypt                              (0x1B99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cbc_initEncrypt                          (0x2CB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cbc_initDecrypt                          (0x4753u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cbc_process                              (0x0E6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cbc_finish                               (0x52DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cfb_encrypt                              (0x2F70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cfb_decrypt                              (0x1877u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cfb_initEncrypt                          (0x5CAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cfb_initDecrypt                          (0x325Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cfb_process                              (0x11AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Cfb_finish                               (0x63B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ctr_encrypt                              (0x256Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ctr_decrypt                              (0x4EE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ctr_initEncrypt                          (0x5599u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ctr_initDecrypt                          (0x4C6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ctr_process                              (0x78C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ctr_finish                               (0x1D53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Df4_encrypt                              (0x474Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Df4_decrypt                              (0x4BC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Df4_initEncrypt                          (0x2CD5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Df4_initDecrypt                          (0x18F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Df4_process                              (0x7790u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Df4_finish                               (0x1A6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ecb_encrypt                              (0x75C1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ecb_decrypt                              (0x1697u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ecb_initEncrypt                          (0x135Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ecb_initDecrypt                          (0x4FA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ecb_process                              (0x243Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ecb_finish                               (0x1F16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ofb_encrypt                              (0x683Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ofb_decrypt                              (0x6E31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ofb_initEncrypt                          (0x623Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ofb_initDecrypt                          (0x47E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ofb_process                              (0x53C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Ofb_finish                               (0x6535u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Xts_encrypt                              (0x2697u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Xts_decrypt                              (0x07E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Xts_initEncrypt                          (0x599Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Xts_initDecrypt                          (0x2B93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Xts_process                              (0x4AF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_Sw_Xts_finish                               (0x2C5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC16                                        (0x518Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC32                                        (0x738Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_verifyContextCrc                                 (0x49E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_computeContextCrc                                (0x43BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC32                                (0x296Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC16                                (0x54F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKem_encapsulate                                         (0x2B36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKem_decapsulate                                         (0x58C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi_nonBlocking                     (0x5726u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi_nonBlocking                     (0x03B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi_nonBlocking                     (0x4AE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_completeAutoMode_Multipart                  (0x4BD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_completeAutoMode_Oneshot                    (0x7945u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_write_secure                                     (0x5917u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_write_secure_reverse                             (0x4F0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_read                                             (0x27ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_read_word                                        (0x1CBCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_read_reverse                                     (0x2FA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_read_secure                                      (0x4BC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_read_secure_reverse                              (0x4D27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_write                                            (0x5BA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_write_word                                       (0x6B92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_write_reverse                                    (0x2B47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_import                                           (0x59B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_export                                           (0x7784u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Montgomery_Reduce                             (0x356Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_NTT                                      (0x46ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_InvNTT_To_Mont                           (0x319Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Pointwise_Montgomery                     (0x5B2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Eta_Pack                                 (0x1BCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Eta_Unpack                               (0x33A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_T1_Pack                                  (0x2B59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_t1_Unpack                                (0x6E07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_T0_Pack                                  (0x529Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_T0_Unpack                                (0x1B95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Z_Pack                                   (0x78CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Z_Unpack_17                              (0x21F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Z_Unpack_19                              (0x549Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Z_Unpack                                 (0x0BF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_W1_Pack                                  (0x6CA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_W1_Unpack                                (0x4575u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_W_Pack                                   (0x06FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_W_Unpack                                 (0x1B33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_C_Pack                                   (0x4CB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_C_Unpack                                 (0x3D70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_H_Unpack                                 (0x2B78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Unpack_SK                                     (0x2C4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Reduce32                                      (0x51B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Reduce                                   (0x2E36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Caddq                                         (0x704Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Uniform_Gamma1                           (0x35A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Make_Hint                                     (0x4C67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Challenge                                (0x72C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Indcpa_Generate_Keys                              (0x7711u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Verify                                            (0x4AD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Encrypt                                           (0x5B34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Decrypt                                           (0x749Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_KeyGen                                            (0x38DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Encaps                                            (0x0E9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Decaps                                            (0x7632u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Montgomery_Reduce                                 (0x6633u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Barrett_Reduce                                    (0x5E0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_NTT                                               (0x253Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Basemul                                           (0x1D39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_InvNTT_To_Mont                               (0x06CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Rej_Uniform                                       (0x3A4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Mul_Streamed_Matrix                          (0x7C0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Mul_Streamed_Skpk                            (0x7172u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Csubq                                        (0x2B56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Compress                                     (0x24DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Decompress                                   (0x46F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_To_Bytes                                          (0x3C9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_From_Msg                                          (0x731Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_To_Msg                                            (0x5A2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Cbd2                                              (0x117Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Cbd3                                              (0x6785u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Get_Noise_Eta1                               (0x53E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Get_Noise_Eta2                               (0x3596u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_NTT                                          (0x03BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_To_Mont                                      (0x3CE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Reduce                                       (0x54D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Add                                          (0x362Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Sub                                          (0x530Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Compress_Gen                                 (0x7A32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Decompress_Gen                               (0x3475u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Compress_Eta1                                (0x61CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Poly_Decompress_Eta1                              (0x668Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Shake128_Absorb                                   (0x5876u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Shake128_Squeeze                                  (0x549Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Stream128_Absorb                                  (0x721Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Stream128_Squeeze                                 (0x3578u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Shake256_PRF                                      (0x2A3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_PRF                                               (0x63C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_KDF                                               (0x4ED4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_Cmov                                              (0x2ABCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Caddq                                    (0x231Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Add                                      (0x1EE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Sub                                      (0x0E73u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Shiftl                                   (0x29DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Power2Round                                   (0x5A2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Power2Round                              (0x48FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Decompose                                     (0x35AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Decompose                                (0x2D74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Use_Hint                                      (0x3B8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Use_Hint                                 (0x0577u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_CHK_Norm                                 (0x6D58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Rej_Uniform                                   (0x7929u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Mul_Streamed_Matrix_Accumulate           (0x6E0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Mul_Streamed_Matrix                      (0x47D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Rej_Eta                                       (0x4E4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Poly_Uniform_Eta                              (0x6F0Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSgi_Backup                                              (0x4F15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSgi_Restore                                             (0x7D60u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_SignAllocateCpuWa                             (0x32C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_SignPrepare                                   (0x685Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_SignComputeHintsForW1                         (0x1ED4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_SignCheckCS2                                  (0x4EA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_SignComputeZ                                  (0x27B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_int                                         (0x1C9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_words_int                                   (0x45CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_reversed_int                                (0x38CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_secure_int                                  (0x3A55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_secure_pow2_int                             (0x5536u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_secure_reversed_int                         (0x5E29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_compare_int                                      (0x427Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_compare_secure_int                               (0x5D52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_compare_dpasecure_int                            (0x272Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_clear_int                                        (0x05EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_clear_secure_int                                 (0x2D8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_set_int                                          (0x3F28u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_set_secure_int                                   (0x32F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDma_requestInputAndOutput                               (0x0D37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDma_releaseInputAndOutput                               (0x362Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDma_release                                             (0x3663u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDma_request                                             (0x266Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_cpu_direct                                       (0x1EB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_cpu_read                                         (0x395Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_cpu_write                                        (0x6A96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_cpu_reverse                                      (0x08FBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_commonHandlerToken                               (0x0CDEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_publicExp                                           (0x6A56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_keyExpansion                                        (0x4A6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_encryptBlock                                        (0x7856u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_decryptBlock                                        (0x7DA0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClBuffer_inputBufferToCPU                                 (0x2D95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Weier_DomainParamsCheck                             (0x1EC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify_P384_CheckRS1                                (0x25DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify_P384_CheckRS2                                (0x371Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_getMillerRabinTestIterations                        (0x037Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_DeterministicECDSA_GenerateProtocolDescriptor       (0x6C2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_entry                                           (0x07ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_addRoundKey                                         (0x36AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_invSubBytesShiftRows                                (0x0ADBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_memCpy                                              (0x173Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_invMixColumns                                       (0x3999u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_mixColumns                                          (0x5A95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_rotWord                                             (0x4B2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_subBytesShiftRows                                   (0x46D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_subWord                                             (0x519Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_calcNrOfRounds                                      (0x646Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_xorWithRcon                                         (0x0F1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAes_xor                                                 (0x0ABBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_keyExpansion                                        (0x571Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_encryptBlock                                        (0x59C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_decryptBlock                                        (0x334Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_rot28Left                                           (0x7827u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_permutateData                                       (0x29B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_selectEbit                                          (0x2CCDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_splitData                                           (0x37C2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_sFunction                                           (0x0DBCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_fFunction                                           (0x7435u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_genRoundKeys                                        (0x66E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_pack64                                              (0x49F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_unpack64                                            (0x7926u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_encrypt                                             (0x5C96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClDes_decrypt                                             (0x45AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Verify_Compare_NoEMSA                               (0x38CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Encrypt_NoEME                                       (0x619Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Decrypt_NoEME                                       (0x3927u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Util_encrypt                                        (0x6F09u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Util_decrypt                                        (0x58AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_xor                                              (0x38D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Public_KeyType_ModeConstructor                      (0x67C8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PrivatePlain_KeyType_ModeConstructor                (0x5E1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PrivateCRT_KeyType_ModeConstructor                  (0x73A4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PrivateCRT_DFA_KeyType_ModeConstructor              (0x71F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModSquareRoot                                      (0x651Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModSquareRoot_TonelliShanks                        (0x7B24u)
+#define MCUX_CSSL_FP_FUNCID_LegendreSymbol                                               (0x625Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ltc_oneShot_Sha3                              (0x53AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ltc_oneShot_Sha3_Shake                        (0x11D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_Ltc_process_Sha3                                   (0x5789u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_Ltc_finish_Sha3_core                               (0x3E62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_Ltc_finish_Sha3                                    (0x623Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_Ltc_finish_Sha3_Shake                              (0x7895u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_Ltc_generate_shake                             (0x7370u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes_Init                            (0x2D71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes_Process                         (0x1C2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes_Finish                          (0x5D1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_computeContextCrc                                  (0x5F22u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_verifyContextCrc                                   (0x46F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_ProcessBlocks                      (0x1CD5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_DeterministicECDSA_BlindedSecretKeyGen              (0x4CADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_456                                             (0x558Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_457                                             (0x153Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_458                                             (0x26E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_459                                             (0x1DC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_460                                             (0x307Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_461                                             (0x2537u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_462                                             (0x3AA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_463                                             (0x6D86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_464                                             (0x67A2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_465                                             (0x52F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_466                                             (0x09F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_467                                             (0x6DC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_468                                             (0x5E1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_469                                             (0x7A86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_470                                             (0x2D47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_471                                             (0x09EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_472                                             (0x1D27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_473                                             (0x68EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_474                                             (0x29D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_475                                             (0x66B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_476                                             (0x1537u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_477                                             (0x6F05u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_478                                             (0x4CF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_479                                             (0x1D3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_480                                             (0x15D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_481                                             (0x6173u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_482                                             (0x04BFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_483                                             (0x4B47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_484                                             (0x07B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_485                                             (0x3AD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_486                                             (0x638Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_487                                             (0x3953u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_488                                             (0x7135u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_489                                             (0x585Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_490                                             (0x43CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_491                                             (0x2B74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_492                                             (0x6569u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_493                                             (0x4C6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_494                                             (0x0737u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_495                                             (0x7916u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_496                                             (0x28BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_497                                             (0x2557u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_498                                             (0x609Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_499                                             (0x691Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_500                                             (0x31E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_501                                             (0x3A53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_502                                             (0x7658u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_503                                             (0x5C59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_504                                             (0x6725u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_505                                             (0x7A38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_506                                             (0x3356u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_507                                             (0x6696u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_508                                             (0x52ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_509                                             (0x4F49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_510                                             (0x2799u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_511                                             (0x2E17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_512                                             (0x2AD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_513                                             (0x524Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_514                                             (0x7561u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_515                                             (0x4D8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_516                                             (0x0CF6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_517                                             (0x39B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_518                                             (0x45BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_519                                             (0x5665u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_520                                             (0x70E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_521                                             (0x2EB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_522                                             (0x06D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_523                                             (0x5E45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_524                                             (0x72D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_525                                             (0x129Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_526                                             (0x21BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_527                                             (0x0D5Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_528                                             (0x0F3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_529                                             (0x131Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_530                                             (0x539Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_531                                             (0x7D06u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_532                                             (0x47D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_533                                             (0x25D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_534                                             (0x13F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_535                                             (0x14F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_536                                             (0x2759u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_537                                             (0x7994u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_538                                             (0x45B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_539                                             (0x38C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_540                                             (0x52DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_541                                             (0x29ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_542                                             (0x6B29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_543                                             (0x5476u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_544                                             (0x467Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_545                                             (0x49BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_546                                             (0x40EFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_547                                             (0x6B8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_548                                             (0x28EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_549                                             (0x11F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_550                                             (0x5C1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_551                                             (0x7998u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_552                                             (0x7887u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_553                                             (0x30BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_554                                             (0x0DF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_555                                             (0x3257u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_556                                             (0x6D2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_557                                             (0x670Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_558                                             (0x04FEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_559                                             (0x6E25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_560                                             (0x52B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_561                                             (0x1F34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_562                                             (0x1AB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_563                                             (0x4E56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_564                                             (0x53D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_565                                             (0x70ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_566                                             (0x3B4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_567                                             (0x5176u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_568                                             (0x4DF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_569                                             (0x29AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_570                                             (0x3955u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_571                                             (0x7A1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_572                                             (0x1C6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_573                                             (0x053Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_574                                             (0x499Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_575                                             (0x23B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_576                                             (0x6A35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_577                                             (0x4F16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_578                                             (0x0BC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_579                                             (0x13ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_580                                             (0x5437u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_581                                             (0x51DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_582                                             (0x27E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_583                                             (0x3D29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_584                                             (0x6137u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_585                                             (0x64CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_586                                             (0x4C8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_587                                             (0x45F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_588                                             (0x07D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_589                                             (0x551Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_590                                             (0x3AD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_591                                             (0x5EC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_592                                             (0x63B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_593                                             (0x4B2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_594                                             (0x1E1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_595                                             (0x53A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_596                                             (0x34DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_597                                             (0x11FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_598                                             (0x3A95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_599                                             (0x6D51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_600                                             (0x56C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_601                                             (0x64D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_602                                             (0x633Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_603                                             (0x2B1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_604                                             (0x255Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_605                                             (0x764Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_606                                             (0x0B6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_607                                             (0x63ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_608                                             (0x7F02u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_609                                             (0x0F35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_610                                             (0x1B2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_611                                             (0x0ABEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_612                                             (0x4CCBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_613                                             (0x7554u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_614                                             (0x5639u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_615                                             (0x6758u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_616                                             (0x30F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_617                                             (0x0FB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_618                                             (0x30EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_619                                             (0x4C5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_620                                             (0x61D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_621                                             (0x5C9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_622                                             (0x7D11u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_623                                             (0x6F81u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_624                                             (0x3A59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_625                                             (0x383Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_626                                             (0x3B4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_627                                             (0x3AB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_628                                             (0x1CE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_629                                             (0x372Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_630                                             (0x3745u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_631                                             (0x7938u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_632                                             (0x55D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_633                                             (0x21F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_634                                             (0x1B65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_635                                             (0x4D6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_636                                             (0x54B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_637                                             (0x7136u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_638                                             (0x5DA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_639                                             (0x52BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_640                                             (0x3D92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_641                                             (0x20FDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_642                                             (0x43CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_643                                             (0x4C75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_644                                             (0x2B33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_645                                             (0x0EADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_646                                             (0x1ED1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_647                                             (0x34BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_648                                             (0x4DE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_649                                             (0x13F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_650                                             (0x6D43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_651                                             (0x60F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_652                                             (0x519Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_653                                             (0x0DBAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_654                                             (0x43DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_655                                             (0x03AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_656                                             (0x6E61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_657                                             (0x64B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_658                                             (0x2A9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_659                                             (0x3659u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_660                                             (0x6CD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_661                                             (0x17B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_662                                             (0x0E2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_663                                             (0x6179u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_664                                             (0x14FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_665                                             (0x1D5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_666                                             (0x5CC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_667                                             (0x4EA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_668                                             (0x097Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_669                                             (0x33E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_670                                             (0x68F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_671                                             (0x5B25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_672                                             (0x6473u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_673                                             (0x5479u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_674                                             (0x2771u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_675                                             (0x0A7Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_676                                             (0x61AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_677                                             (0x3D4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_678                                             (0x13CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_679                                             (0x0C5Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_680                                             (0x35E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_681                                             (0x19F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_682                                             (0x7A54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_683                                             (0x760Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_684                                             (0x1FA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_685                                             (0x1F64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_686                                             (0x36B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_687                                             (0x0A9Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_688                                             (0x54E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_689                                             (0x6CC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_690                                             (0x3792u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_691                                             (0x4766u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_692                                             (0x69B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_693                                             (0x48B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_694                                             (0x3719u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_695                                             (0x3F06u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_696                                             (0x715Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_697                                             (0x12DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_698                                             (0x721Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_699                                             (0x1D65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_700                                             (0x2736u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_701                                             (0x29D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_702                                             (0x1CDCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_703                                             (0x1D1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_704                                             (0x29D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_705                                             (0x5D64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_706                                             (0x30FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_707                                             (0x63B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_708                                             (0x2FC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_709                                             (0x1F29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_710                                             (0x4D65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_711                                             (0x7AC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_712                                             (0x0DDAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_713                                             (0x38ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_714                                             (0x56A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_715                                             (0x1CE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_716                                             (0x0DE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_717                                             (0x5553u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_718                                             (0x7E24u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_719                                             (0x3B32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_720                                             (0x7C62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_721                                             (0x61C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_722                                             (0x3D8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_723                                             (0x4FC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_724                                             (0x61EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_725                                             (0x3B86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_726                                             (0x19BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_727                                             (0x43B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_728                                             (0x1D8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_729                                             (0x4E35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_730                                             (0x7C23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_731                                             (0x734Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_732                                             (0x3327u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_733                                             (0x6716u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_734                                             (0x707Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_735                                             (0x3897u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_736                                             (0x4F43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_737                                             (0x3723u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_738                                             (0x5A36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_739                                             (0x333Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_740                                             (0x6C99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_741                                             (0x15ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_742                                             (0x1DCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_743                                             (0x538Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_744                                             (0x6C5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_745                                             (0x53D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_746                                             (0x5E46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_747                                             (0x5E0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_748                                             (0x233Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_749                                             (0x686Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_750                                             (0x1B3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_751                                             (0x691Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_752                                             (0x50BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_753                                             (0x46D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_754                                             (0x2DB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_755                                             (0x154Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_756                                             (0x6BC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_757                                             (0x0FB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_758                                             (0x3DC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_759                                             (0x44D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_760                                             (0x3DE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_761                                             (0x7463u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_762                                             (0x39CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_763                                             (0x643Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_764                                             (0x4AB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_765                                             (0x495Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_766                                             (0x5CD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_767                                             (0x6C65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_768                                             (0x34B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_769                                             (0x781Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_770                                             (0x67C2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_771                                             (0x7259u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_772                                             (0x5C93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_773                                             (0x1AB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_774                                             (0x2DD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_775                                             (0x076Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_776                                             (0x19E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_777                                             (0x47D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_778                                             (0x5672u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_779                                             (0x476Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_780                                             (0x15B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_781                                             (0x1B69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_782                                             (0x53B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_783                                             (0x29E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_784                                             (0x5B62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_785                                             (0x316Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_786                                             (0x5897u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_787                                             (0x6ACAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_788                                             (0x235Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_789                                             (0x1F0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_790                                             (0x618Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_791                                             (0x0DADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_792                                             (0x7A94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_793                                             (0x78D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_794                                             (0x7949u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_795                                             (0x5B51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_796                                             (0x1B2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_797                                             (0x116Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_798                                             (0x386Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_799                                             (0x5BE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_800                                             (0x4EC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_801                                             (0x505Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_802                                             (0x4675u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_803                                             (0x305Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_804                                             (0x7E90u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_805                                             (0x5969u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_806                                             (0x7AA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_807                                             (0x4BC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_808                                             (0x2379u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_809                                             (0x23B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_810                                             (0x7CC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_811                                             (0x715Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_812                                             (0x2B53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_813                                             (0x1579u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_814                                             (0x4657u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_815                                             (0x6AC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_816                                             (0x4E1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_817                                             (0x7724u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_818                                             (0x52CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_819                                             (0x495Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_820                                             (0x1B5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_821                                             (0x682Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_822                                             (0x32DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_823                                             (0x133Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_824                                             (0x0EF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_825                                             (0x5B89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_826                                             (0x0FA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_827                                             (0x4CD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_828                                             (0x479Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_829                                             (0x6363u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_830                                             (0x4D74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_831                                             (0x18EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_832                                             (0x748Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_833                                             (0x3A3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_834                                             (0x5D49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_835                                             (0x198Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_836                                             (0x762Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_837                                             (0x0BD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_838                                             (0x2F34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_839                                             (0x75D0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_840                                             (0x1D78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_841                                             (0x62A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_842                                             (0x4F68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_843                                             (0x5791u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_844                                             (0x39D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_845                                             (0x285Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_846                                             (0x6E86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_847                                             (0x05EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_848                                             (0x59C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_849                                             (0x5BC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_850                                             (0x740Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_851                                             (0x0E76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_852                                             (0x157Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_853                                             (0x6B0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_854                                             (0x6A47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_855                                             (0x0E3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_856                                             (0x7638u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_857                                             (0x24E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_858                                             (0x0D6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_859                                             (0x5517u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_860                                             (0x30D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_861                                             (0x1D59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_862                                             (0x57E0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_863                                             (0x745Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_864                                             (0x43D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_865                                             (0x3B58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_866                                             (0x730Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_867                                             (0x75C8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_868                                             (0x278Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_869                                             (0x54ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_870                                             (0x0AEDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_871                                             (0x46CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_872                                             (0x56D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_873                                             (0x5CB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_874                                             (0x317Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_875                                             (0x73C8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_876                                             (0x2BB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_877                                             (0x079Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_878                                             (0x31CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_879                                             (0x47CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_880                                             (0x2AB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_881                                             (0x52E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_882                                             (0x5CA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_883                                             (0x16F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_884                                             (0x5713u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_885                                             (0x6B86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_886                                             (0x5A93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_887                                             (0x66E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_888                                             (0x5257u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_889                                             (0x3B34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_890                                             (0x0CB7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_891                                             (0x6335u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_892                                             (0x1D93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_893                                             (0x38B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_894                                             (0x4F8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_895                                             (0x2E2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_896                                             (0x7A51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_897                                             (0x56AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_898                                             (0x1BD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_899                                             (0x1AF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_900                                             (0x1975u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_901                                             (0x2CB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_902                                             (0x11BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_903                                             (0x681Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_904                                             (0x5E23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_905                                             (0x7AB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_906                                             (0x7534u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_907                                             (0x3DC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_908                                             (0x655Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_909                                             (0x4B1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_910                                             (0x70CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_911                                             (0x1E66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_912                                             (0x556Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_913                                             (0x5B07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_914                                             (0x390Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_915                                             (0x4DCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_916                                             (0x596Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_917                                             (0x1AECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_918                                             (0x41DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_919                                             (0x5617u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_920                                             (0x5C4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_921                                             (0x4F23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_922                                             (0x662Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_923                                             (0x24FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_924                                             (0x0E4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_925                                             (0x62F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_926                                             (0x35CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_927                                             (0x68E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_928                                             (0x7D81u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_929                                             (0x58E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_930                                             (0x1C97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_931                                             (0x25B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_932                                             (0x0AD7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_933                                             (0x39C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_934                                             (0x3C27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_935                                             (0x28F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_936                                             (0x175Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_937                                             (0x39A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_938                                             (0x2375u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_939                                             (0x3699u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_940                                             (0x3D43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_941                                             (0x70B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_942                                             (0x34E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_943                                             (0x4FC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_944                                             (0x03FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_945                                             (0x5AACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_946                                             (0x46EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_947                                             (0x065Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_948                                             (0x49CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_949                                             (0x64C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_950                                             (0x6393u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_951                                             (0x392Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_952                                             (0x16DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_953                                             (0x0BB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_954                                             (0x591Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_955                                             (0x4C6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_956                                             (0x4C7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_957                                             (0x1E99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_958                                             (0x14E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_959                                             (0x3479u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_960                                             (0x5CB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_961                                             (0x0ECBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_962                                             (0x748Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_963                                             (0x23F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_964                                             (0x5B68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_965                                             (0x6CD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_966                                             (0x4B93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_967                                             (0x712Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_968                                             (0x19DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_969                                             (0x4C76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_970                                             (0x6356u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_971                                             (0x41F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_972                                             (0x30FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_973                                             (0x6B4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_974                                             (0x55D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_975                                             (0x2C2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_976                                             (0x5A9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_977                                             (0x5CD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_978                                             (0x23E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_979                                             (0x6C17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_980                                             (0x5C8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_981                                             (0x7934u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_982                                             (0x526Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_983                                             (0x1B59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_984                                             (0x694Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_985                                             (0x1E55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_986                                             (0x163Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_987                                             (0x6F41u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_988                                             (0x06DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_989                                             (0x5D94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_990                                             (0x2A9Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_991                                             (0x6636u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_992                                             (0x5C6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_993                                             (0x4AB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_994                                             (0x0DCBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_995                                             (0x7A25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_996                                             (0x3E52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_997                                             (0x7361u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_998                                             (0x4576u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_999                                             (0x25E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1000                                            (0x60CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1001                                            (0x5B31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1002                                            (0x16AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1003                                            (0x1AC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1004                                            (0x3AA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1005                                            (0x6C95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1006                                            (0x7159u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1007                                            (0x7C4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1008                                            (0x4733u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1009                                            (0x4567u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1010                                            (0x38B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1011                                            (0x24F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1012                                            (0x724Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1013                                            (0x6AB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1014                                            (0x5A69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1015                                            (0x72AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1016                                            (0x7643u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1017                                            (0x2C6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1018                                            (0x25C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1019                                            (0x3A87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1020                                            (0x225Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1021                                            (0x6D16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1022                                            (0x35ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1023                                            (0x3E91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1024                                            (0x789Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1025                                            (0x7B0Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1026                                            (0x12F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1027                                            (0x34F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1028                                            (0x7C86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1029                                            (0x56E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1030                                            (0x569Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1031                                            (0x3AC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1032                                            (0x3339u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1033                                            (0x1957u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1034                                            (0x5563u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1035                                            (0x6A71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1036                                            (0x55B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1037                                            (0x1DD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1038                                            (0x499Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1039                                            (0x3359u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1040                                            (0x2AD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1041                                            (0x592Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1042                                            (0x5E4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1043                                            (0x0F8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1044                                            (0x6D49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1045                                            (0x6B58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1046                                            (0x34D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1047                                            (0x16F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1048                                            (0x2D6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1049                                            (0x239Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1050                                            (0x16D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1051                                            (0x58BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1052                                            (0x44FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1053                                            (0x359Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1054                                            (0x6D91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1055                                            (0x4D2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1056                                            (0x1E4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1057                                            (0x33B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1058                                            (0x1CBAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1059                                            (0x7278u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1060                                            (0x3B29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1061                                            (0x7447u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1062                                            (0x4E99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1063                                            (0x78E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1064                                            (0x58F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1065                                            (0x750Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1066                                            (0x7E09u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1067                                            (0x14CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1068                                            (0x1DB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1069                                            (0x615Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1070                                            (0x3B8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1071                                            (0x58F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1072                                            (0x2AB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1073                                            (0x6B25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1074                                            (0x0C77u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1075                                            (0x5972u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1076                                            (0x13AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1077                                            (0x12F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1078                                            (0x38ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1079                                            (0x5CD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1080                                            (0x26CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1081                                            (0x2ECAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1082                                            (0x37C8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1083                                            (0x5A3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1084                                            (0x38E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1085                                            (0x4F19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1086                                            (0x2795u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1087                                            (0x768Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1088                                            (0x393Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1089                                            (0x417Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1090                                            (0x5A66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1091                                            (0x35B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1092                                            (0x65D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1093                                            (0x6956u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1094                                            (0x2F45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1095                                            (0x4ED2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1096                                            (0x586Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1097                                            (0x6371u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1098                                            (0x52A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1099                                            (0x27D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1100                                            (0x5D16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1101                                            (0x36B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1102                                            (0x5A17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1103                                            (0x295Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1104                                            (0x13ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1105                                            (0x0ED3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1106                                            (0x5B26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1107                                            (0x61DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1108                                            (0x3C56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1109                                            (0x660Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1110                                            (0x6365u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1111                                            (0x5A0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1112                                            (0x3743u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1113                                            (0x06F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1114                                            (0x4CAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1115                                            (0x5974u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1116                                            (0x17E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1117                                            (0x1A67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1118                                            (0x7C49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1119                                            (0x14D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1120                                            (0x2B17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1121                                            (0x741Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1122                                            (0x5745u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1123                                            (0x7C1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1124                                            (0x2B2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1125                                            (0x6C1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1126                                            (0x35CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1127                                            (0x05F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1128                                            (0x2C9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1129                                            (0x71A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1130                                            (0x123Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1131                                            (0x069Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1132                                            (0x136Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1133                                            (0x6857u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1134                                            (0x4E0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1135                                            (0x193Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1136                                            (0x15F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1137                                            (0x127Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1138                                            (0x668Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1139                                            (0x34ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1140                                            (0x7AA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1141                                            (0x3E25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1142                                            (0x3365u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1143                                            (0x4C5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1144                                            (0x2E1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1145                                            (0x2B55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1146                                            (0x64EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1147                                            (0x36D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1148                                            (0x70E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1149                                            (0x3794u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1150                                            (0x5167u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1151                                            (0x1A6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1152                                            (0x6A66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1153                                            (0x311Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1154                                            (0x62F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1155                                            (0x6A6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1156                                            (0x13BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1157                                            (0x274Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1158                                            (0x6AA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1159                                            (0x22F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1160                                            (0x2755u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1161                                            (0x5E26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1162                                            (0x726Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1163                                            (0x5AC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1164                                            (0x51D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1165                                            (0x04DFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1166                                            (0x4DA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1167                                            (0x49DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1168                                            (0x7439u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1169                                            (0x645Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1170                                            (0x6C96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1171                                            (0x236Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1172                                            (0x2AADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1173                                            (0x5BA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1174                                            (0x2673u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1175                                            (0x41EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1176                                            (0x18E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1177                                            (0x705Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1178                                            (0x1C3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1179                                            (0x7607u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1180                                            (0x0E97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1181                                            (0x4A9Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1182                                            (0x1759u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1183                                            (0x3A47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1184                                            (0x5A27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1185                                            (0x4A6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1186                                            (0x6267u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1187                                            (0x4B59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1188                                            (0x2ACBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1189                                            (0x16CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1190                                            (0x6CF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1191                                            (0x7D42u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1192                                            (0x432Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1193                                            (0x25F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1194                                            (0x546Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1195                                            (0x69E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1196                                            (0x7C91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1197                                            (0x232Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1198                                            (0x2337u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1199                                            (0x6E1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1200                                            (0x5E85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1201                                            (0x1A73u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1202                                            (0x29F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1203                                            (0x5738u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1204                                            (0x1DCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1205                                            (0x21EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1206                                            (0x3B0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1207                                            (0x25EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1208                                            (0x0DB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1209                                            (0x7543u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1210                                            (0x4735u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1211                                            (0x11EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1212                                            (0x458Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1213                                            (0x6C2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1214                                            (0x15B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1215                                            (0x3C3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1216                                            (0x5C5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1217                                            (0x53A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1218                                            (0x635Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1219                                            (0x638Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1220                                            (0x70AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1221                                            (0x1DD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1222                                            (0x34BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1223                                            (0x491Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1224                                            (0x0DD5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1225                                            (0x2BC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1226                                            (0x6536u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1227                                            (0x63D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1228                                            (0x75A1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1229                                            (0x1357u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1230                                            (0x4F98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1231                                            (0x2FC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1232                                            (0x139Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1233                                            (0x64ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1234                                            (0x13CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1235                                            (0x332Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1236                                            (0x6663u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1237                                            (0x4FC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1238                                            (0x65A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1239                                            (0x67C4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1240                                            (0x487Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1241                                            (0x6B0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1242                                            (0x516Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1243                                            (0x0FC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1244                                            (0x3E46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1245                                            (0x627Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1246                                            (0x4A5Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1247                                            (0x2DD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1248                                            (0x6A65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1249                                            (0x7760u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1250                                            (0x7750u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1251                                            (0x5879u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1252                                            (0x3D64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1253                                            (0x06F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1254                                            (0x4787u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1255                                            (0x1CF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1256                                            (0x70E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1257                                            (0x41B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1258                                            (0x12BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1259                                            (0x146Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1260                                            (0x5497u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1261                                            (0x633Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1262                                            (0x48F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1263                                            (0x1BC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1264                                            (0x545Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1265                                            (0x616Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1266                                            (0x51BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1267                                            (0x728Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1268                                            (0x3965u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1269                                            (0x47A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1270                                            (0x74CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1271                                            (0x0CBEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1272                                            (0x3C6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1273                                            (0x50EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1274                                            (0x45F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1275                                            (0x30DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1276                                            (0x6DA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1277                                            (0x68ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1278                                            (0x0CFCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1279                                            (0x273Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1280                                            (0x51B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1281                                            (0x1B4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1282                                            (0x35F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1283                                            (0x0D57u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1284                                            (0x02EFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1285                                            (0x4A67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1286                                            (0x457Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1287                                            (0x54E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1288                                            (0x2AF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1289                                            (0x746Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1290                                            (0x6A74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1291                                            (0x099Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1292                                            (0x654Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1293                                            (0x3C5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1294                                            (0x18BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1295                                            (0x617Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1296                                            (0x2E5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1297                                            (0x6E68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1298                                            (0x713Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1299                                            (0x26F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1300                                            (0x6257u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1301                                            (0x786Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1302                                            (0x16D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1303                                            (0x1C67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1304                                            (0x64CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1305                                            (0x62B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1306                                            (0x47C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1307                                            (0x78A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1308                                            (0x2ED8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1309                                            (0x3B07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1310                                            (0x5B1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1311                                            (0x1E47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1312                                            (0x39B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1313                                            (0x30E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1314                                            (0x41EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1315                                            (0x5547u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1316                                            (0x4B4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1317                                            (0x2E1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1318                                            (0x5A3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1319                                            (0x7558u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1320                                            (0x32F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1321                                            (0x4727u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1322                                            (0x3ACCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1323                                            (0x3655u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1324                                            (0x1F49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1325                                            (0x3B1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1326                                            (0x6077u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1327                                            (0x4EB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1328                                            (0x056Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1329                                            (0x7C58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1330                                            (0x45D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1331                                            (0x3FA0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1332                                            (0x63D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1333                                            (0x76C8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1334                                            (0x4D95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1335                                            (0x370Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1336                                            (0x1F8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1337                                            (0x4CDCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1338                                            (0x3539u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1339                                            (0x24CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1340                                            (0x1D99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1341                                            (0x451Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1342                                            (0x15B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1343                                            (0x5CC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1344                                            (0x3CC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1345                                            (0x6C56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1346                                            (0x04F7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1347                                            (0x7D84u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1348                                            (0x25BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1349                                            (0x2CD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1350                                            (0x391Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1351                                            (0x075Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1352                                            (0x67A4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1353                                            (0x195Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1354                                            (0x478Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1355                                            (0x47E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1356                                            (0x52C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1357                                            (0x18BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1358                                            (0x3473u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1359                                            (0x798Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1360                                            (0x3378u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1361                                            (0x72D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1362                                            (0x7163u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1363                                            (0x18DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1364                                            (0x22FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1365                                            (0x2BCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1366                                            (0x0E6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1367                                            (0x2CF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1368                                            (0x5D4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1369                                            (0x3527u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1370                                            (0x3353u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1371                                            (0x1CCEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1372                                            (0x4BD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1373                                            (0x1E8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1374                                            (0x7D24u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1375                                            (0x4E47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1376                                            (0x5955u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1377                                            (0x72A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1378                                            (0x1E33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1379                                            (0x5AD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1380                                            (0x247Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1381                                            (0x67E0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1382                                            (0x4BA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1383                                            (0x594Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1384                                            (0x454Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1385                                            (0x58EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1386                                            (0x4DD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1387                                            (0x7364u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1388                                            (0x0B3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1389                                            (0x1E53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1390                                            (0x5EC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1391                                            (0x31F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1392                                            (0x7495u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1393                                            (0x439Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1394                                            (0x344Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1395                                            (0x5A1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1396                                            (0x3963u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1397                                            (0x46ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1398                                            (0x1DAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1399                                            (0x326Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1400                                            (0x522Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1401                                            (0x73C2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1402                                            (0x1DB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1403                                            (0x14F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1404                                            (0x26F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1405                                            (0x32D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1406                                            (0x6B15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1407                                            (0x19AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1408                                            (0x0D5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1409                                            (0x7899u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1410                                            (0x5587u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1411                                            (0x674Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1412                                            (0x2C73u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1413                                            (0x2B1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1414                                            (0x12AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1415                                            (0x78B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1416                                            (0x3731u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1417                                            (0x4D35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1418                                            (0x23D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1419                                            (0x4B65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1420                                            (0x29F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1421                                            (0x7394u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1422                                            (0x65D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1423                                            (0x386Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1424                                            (0x6C0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1425                                            (0x6C4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1426                                            (0x2BA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1427                                            (0x2F46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1428                                            (0x3D26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1429                                            (0x7A15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1430                                            (0x7398u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1431                                            (0x73C4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1432                                            (0x32DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1433                                            (0x21F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1434                                            (0x162Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1435                                            (0x1E2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1436                                            (0x22DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1437                                            (0x593Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1438                                            (0x173Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1439                                            (0x66D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1440                                            (0x217Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1441                                            (0x44EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1442                                            (0x3617u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1443                                            (0x09DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1444                                            (0x51CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1445                                            (0x591Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1446                                            (0x45ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1447                                            (0x19ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1448                                            (0x7649u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1449                                            (0x3653u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1450                                            (0x6574u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1451                                            (0x7C16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1452                                            (0x7932u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1453                                            (0x364Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1454                                            (0x790Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1455                                            (0x323Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1456                                            (0x586Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1457                                            (0x1B35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1458                                            (0x78E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1459                                            (0x6F06u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1460                                            (0x0BF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1461                                            (0x14DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1462                                            (0x5959u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1463                                            (0x3CAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1464                                            (0x5734u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1465                                            (0x46E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1466                                            (0x2ABAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1467                                            (0x0AEBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1468                                            (0x46CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1469                                            (0x6273u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1470                                            (0x32AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1471                                            (0x4E93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1472                                            (0x369Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1473                                            (0x4DB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1474                                            (0x23F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1475                                            (0x3AB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1476                                            (0x744Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1477                                            (0x26D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1478                                            (0x5953u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1479                                            (0x558Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1480                                            (0x5D45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1481                                            (0x2B35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1482                                            (0x32D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1483                                            (0x7943u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1484                                            (0x0AAFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1485                                            (0x2F91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1486                                            (0x68F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1487                                            (0x3D54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1488                                            (0x1BF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1489                                            (0x2AABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1490                                            (0x1C4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1491                                            (0x0D67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1492                                            (0x159Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1493                                            (0x1E59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1494                                            (0x6A2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1495                                            (0x18FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1496                                            (0x39C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1497                                            (0x6F28u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1498                                            (0x219Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1499                                            (0x1976u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1500                                            (0x24DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1501                                            (0x51ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1502                                            (0x7217u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1503                                            (0x5137u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1504                                            (0x2F43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1505                                            (0x14BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1506                                            (0x5297u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1507                                            (0x40FEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1508                                            (0x2A79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1509                                            (0x117Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1510                                            (0x269Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1511                                            (0x66C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1512                                            (0x42EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1513                                            (0x153Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1514                                            (0x55A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1515                                            (0x7615u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1516                                            (0x43F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1517                                            (0x1BE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1518                                            (0x3C1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1519                                            (0x33D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1520                                            (0x607Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1521                                            (0x6475u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1522                                            (0x3C8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1523                                            (0x1799u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1524                                            (0x5EA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1525                                            (0x7459u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1526                                            (0x2735u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1527                                            (0x6476u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1528                                            (0x6C27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1529                                            (0x2B1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1530                                            (0x61BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1531                                            (0x3B16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1532                                            (0x2AB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1533                                            (0x644Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1534                                            (0x2ED1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1535                                            (0x1F68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1536                                            (0x1557u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1537                                            (0x3D07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1538                                            (0x1A5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1539                                            (0x55E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1540                                            (0x3995u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1541                                            (0x5E70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1542                                            (0x71D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1543                                            (0x3E0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1544                                            (0x2F07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1545                                            (0x163Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1546                                            (0x4B33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1547                                            (0x3D85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1548                                            (0x297Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1549                                            (0x0EDCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1550                                            (0x4A2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1551                                            (0x5E43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1552                                            (0x4F32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1553                                            (0x1AB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1554                                            (0x64B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1555                                            (0x4EC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1556                                            (0x6E19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1557                                            (0x42BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1558                                            (0x3B92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1559                                            (0x5A56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1560                                            (0x6587u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1561                                            (0x66A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1562                                            (0x19B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1563                                            (0x21D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1564                                            (0x4376u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1565                                            (0x32A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1566                                            (0x7951u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1567                                            (0x1B2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1568                                            (0x5754u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1569                                            (0x0D8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1570                                            (0x1D3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1571                                            (0x3E86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1572                                            (0x43CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1573                                            (0x1739u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1574                                            (0x7985u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1575                                            (0x7472u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1576                                            (0x196Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1577                                            (0x2DE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1578                                            (0x6A78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1579                                            (0x38BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1580                                            (0x1F51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1581                                            (0x0F6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1582                                            (0x70B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1583                                            (0x34D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1584                                            (0x64E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1585                                            (0x352Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1586                                            (0x6764u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1587                                            (0x3555u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1588                                            (0x378Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1589                                            (0x1D35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1590                                            (0x515Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1591                                            (0x292Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1592                                            (0x4C3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1593                                            (0x1733u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1594                                            (0x5BA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1595                                            (0x59E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1596                                            (0x7313u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1597                                            (0x48BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1598                                            (0x7075u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1599                                            (0x11BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1600                                            (0x5D43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1601                                            (0x3876u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1602                                            (0x1B6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1603                                            (0x1BCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1604                                            (0x18F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1605                                            (0x559Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1606                                            (0x19BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1607                                            (0x382Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1608                                            (0x3751u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1609                                            (0x5768u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1610                                            (0x1BC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1611                                            (0x7E60u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1612                                            (0x27C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1613                                            (0x33C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1614                                            (0x2B87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1615                                            (0x2E74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1616                                            (0x7B05u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1617                                            (0x59B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1618                                            (0x465Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1619                                            (0x3D15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1620                                            (0x0F8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1621                                            (0x38D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1622                                            (0x659Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1623                                            (0x295Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1624                                            (0x265Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1625                                            (0x7626u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1626                                            (0x27B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1627                                            (0x55B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1628                                            (0x64E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1629                                            (0x315Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1630                                            (0x299Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1631                                            (0x6C59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1632                                            (0x169Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1633                                            (0x3639u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1634                                            (0x0F6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1635                                            (0x4ACDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1636                                            (0x3D1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1637                                            (0x2397u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1638                                            (0x664Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1639                                            (0x5731u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1640                                            (0x2E66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1641                                            (0x1BE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1642                                            (0x5B2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1643                                            (0x27B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1644                                            (0x4BC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1645                                            (0x433Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1646                                            (0x2F83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1647                                            (0x1657u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1648                                            (0x2B65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1649                                            (0x2BD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1650                                            (0x561Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1651                                            (0x4375u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1652                                            (0x1AAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1653                                            (0x39F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1654                                            (0x668Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1655                                            (0x4C9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1656                                            (0x6EA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1657                                            (0x1667u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1658                                            (0x0AEEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1659                                            (0x075Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1660                                            (0x2A2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1661                                            (0x643Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1662                                            (0x564Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1663                                            (0x33CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1664                                            (0x63A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1665                                            (0x56B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1666                                            (0x53CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1667                                            (0x7299u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1668                                            (0x0DE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1669                                            (0x47A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1670                                            (0x632Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1671                                            (0x7307u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1672                                            (0x3917u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1673                                            (0x719Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1674                                            (0x3B31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1675                                            (0x658Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1676                                            (0x3C59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1677                                            (0x744Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1678                                            (0x63CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1679                                            (0x0677u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1680                                            (0x74CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1681                                            (0x1B39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1682                                            (0x4BCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1683                                            (0x45D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1684                                            (0x2CABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1685                                            (0x456Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1686                                            (0x0F9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1687                                            (0x1CB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1688                                            (0x327Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1689                                            (0x0E6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1690                                            (0x23DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1691                                            (0x55E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1692                                            (0x69D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1693                                            (0x5B16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1694                                            (0x78B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1695                                            (0x69CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1696                                            (0x385Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1697                                            (0x4937u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1698                                            (0x6CA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1699                                            (0x263Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1700                                            (0x709Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1701                                            (0x513Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1702                                            (0x496Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1703                                            (0x6E0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1704                                            (0x57C4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1705                                            (0x3F41u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1706                                            (0x2B3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1707                                            (0x7A0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1708                                            (0x7931u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1709                                            (0x63C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1710                                            (0x783Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1711                                            (0x5B70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1712                                            (0x65B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1713                                            (0x49B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1714                                            (0x65A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1715                                            (0x6996u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1716                                            (0x2F86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1717                                            (0x574Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1718                                            (0x423Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1719                                            (0x564Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1720                                            (0x3636u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1721                                            (0x0D1Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1722                                            (0x782Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1723                                            (0x2AA7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1724                                            (0x5D91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1725                                            (0x1277u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1726                                            (0x265Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1727                                            (0x0F1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1728                                            (0x606Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1729                                            (0x5C9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1730                                            (0x5353u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1731                                            (0x191Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1732                                            (0x330Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1733                                            (0x5E25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1734                                            (0x08FDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1735                                            (0x5175u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1736                                            (0x6CAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1737                                            (0x5333u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1738                                            (0x1ACBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1739                                            (0x6672u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1740                                            (0x39D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1741                                            (0x3BB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1742                                            (0x7A52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1743                                            (0x5794u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1744                                            (0x5D23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1745                                            (0x6D1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1746                                            (0x72E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1747                                            (0x5F82u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1748                                            (0x650Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1749                                            (0x0D9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1750                                            (0x1B3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1751                                            (0x36D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1752                                            (0x0B75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1753                                            (0x583Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1754                                            (0x2EE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1755                                            (0x41DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1756                                            (0x159Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1757                                            (0x6F44u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1758                                            (0x7B30u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1759                                            (0x46BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1760                                            (0x0B6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1761                                            (0x3CD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1762                                            (0x06DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1763                                            (0x69B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1764                                            (0x216Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1765                                            (0x3F90u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1766                                            (0x166Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1767                                            (0x1D96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1768                                            (0x32E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1769                                            (0x32D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1770                                            (0x17A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1771                                            (0x5A8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1772                                            (0x2373u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1773                                            (0x2DC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1774                                            (0x51F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1775                                            (0x6E91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1776                                            (0x4F92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1777                                            (0x7325u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1778                                            (0x31B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1779                                            (0x495Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1780                                            (0x1ABAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1781                                            (0x75B0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1782                                            (0x56C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1783                                            (0x26DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1784                                            (0x5387u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1785                                            (0x64E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1786                                            (0x11DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1787                                            (0x591Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1788                                            (0x23CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1789                                            (0x7358u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1790                                            (0x6317u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1791                                            (0x4F34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1792                                            (0x49B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1793                                            (0x27E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1794                                            (0x6593u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1795                                            (0x44EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1796                                            (0x6C1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1797                                            (0x26BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1798                                            (0x30EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1799                                            (0x276Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1800                                            (0x47C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1801                                            (0x5173u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1802                                            (0x07D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1803                                            (0x714Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1804                                            (0x3D8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1805                                            (0x0D4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1806                                            (0x6533u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1807                                            (0x2778u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1808                                            (0x1ECCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1809                                            (0x7A23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1810                                            (0x49F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1811                                            (0x3F0Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1812                                            (0x1B1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1813                                            (0x0D76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1814                                            (0x24BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1815                                            (0x07CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1816                                            (0x2DCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1817                                            (0x7952u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1818                                            (0x5D0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1819                                            (0x55E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1820                                            (0x672Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1821                                            (0x549Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1822                                            (0x1B53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1823                                            (0x0DC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1824                                            (0x1E5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1825                                            (0x6B64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1826                                            (0x0DA7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1827                                            (0x289Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1828                                            (0x7B42u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1829                                            (0x59E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1830                                            (0x07F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1831                                            (0x3CA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1832                                            (0x1F4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1833                                            (0x2DACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1834                                            (0x39D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1835                                            (0x0B3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1836                                            (0x751Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1837                                            (0x1C9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1838                                            (0x55A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1839                                            (0x7568u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1840                                            (0x46AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1841                                            (0x70D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1842                                            (0x5AA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1843                                            (0x3D68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1844                                            (0x570Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1845                                            (0x0BB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1846                                            (0x641Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1847                                            (0x3E58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1848                                            (0x62C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1849                                            (0x6B46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1850                                            (0x57D0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1851                                            (0x7E30u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1852                                            (0x6789u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1853                                            (0x12F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1854                                            (0x12BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1855                                            (0x7654u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1856                                            (0x15A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1857                                            (0x2AECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1858                                            (0x6CACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1859                                            (0x236Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1860                                            (0x5F48u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1861                                            (0x269Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1862                                            (0x6B26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1863                                            (0x578Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1864                                            (0x532Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1865                                            (0x18CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1866                                            (0x5B38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1867                                            (0x2AE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1868                                            (0x0977u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1869                                            (0x6A8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1870                                            (0x3A56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1871                                            (0x6947u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1872                                            (0x1A2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1873                                            (0x655Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1874                                            (0x3D52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1875                                            (0x2B4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1876                                            (0x26F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1877                                            (0x2E71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1878                                            (0x35D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1879                                            (0x1EB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1880                                            (0x1CB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1881                                            (0x171Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1882                                            (0x5DC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1883                                            (0x4D1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1884                                            (0x3A5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1885                                            (0x6D89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1886                                            (0x36D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1887                                            (0x3D89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1888                                            (0x0EBCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1889                                            (0x4759u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1890                                            (0x7AC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1891                                            (0x4F29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1892                                            (0x2D2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1893                                            (0x2F31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1894                                            (0x3E13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1895                                            (0x62CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1896                                            (0x3E26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1897                                            (0x06BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1898                                            (0x662Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1899                                            (0x0EDAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1900                                            (0x54CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1901                                            (0x0BDCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1902                                            (0x11EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1903                                            (0x54D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1904                                            (0x51D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1905                                            (0x1F2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1906                                            (0x0BD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1907                                            (0x324Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1908                                            (0x4D53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1909                                            (0x4DE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1910                                            (0x3EC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1911                                            (0x34B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1912                                            (0x7564u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1913                                            (0x03F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1914                                            (0x155Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1915                                            (0x0D7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1916                                            (0x6547u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1917                                            (0x3D31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1918                                            (0x3C65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1919                                            (0x3395u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1920                                            (0x16ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1921                                            (0x66A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1922                                            (0x33B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1923                                            (0x7C92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1924                                            (0x4E17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1925                                            (0x745Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1926                                            (0x2BC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1927                                            (0x26B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1928                                            (0x5EA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1929                                            (0x3396u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1930                                            (0x0F27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1931                                            (0x4B53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1932                                            (0x3C2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1933                                            (0x349Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1934                                            (0x5378u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1935                                            (0x722Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1936                                            (0x2B6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1937                                            (0x6EB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1938                                            (0x6D64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1939                                            (0x2E72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1940                                            (0x4DE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1941                                            (0x3738u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1942                                            (0x4BAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1943                                            (0x7271u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1944                                            (0x3497u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1945                                            (0x4DC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1946                                            (0x2EB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1947                                            (0x7A2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1948                                            (0x0FCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1949                                            (0x3734u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1950                                            (0x748Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1951                                            (0x690Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1952                                            (0x6E83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1953                                            (0x7F08u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1954                                            (0x5276u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1955                                            (0x41BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1956                                            (0x43ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1957                                            (0x34D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1958                                            (0x7097u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1959                                            (0x237Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1960                                            (0x6745u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1961                                            (0x3B54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1962                                            (0x4E1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1963                                            (0x3D34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1964                                            (0x0E5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1965                                            (0x3AF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1966                                            (0x723Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1967                                            (0x671Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1968                                            (0x30F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1969                                            (0x5723u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1970                                            (0x6F18u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1971                                            (0x3E4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1972                                            (0x55A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1973                                            (0x08DFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1974                                            (0x26CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1975                                            (0x1D5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1976                                            (0x2C97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1977                                            (0x3BA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1978                                            (0x7A46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1979                                            (0x44EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1980                                            (0x1DC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1981                                            (0x41FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1982                                            (0x5E94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1983                                            (0x76A1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1984                                            (0x295Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1985                                            (0x629Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1986                                            (0x3E0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1987                                            (0x464Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1988                                            (0x2F51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1989                                            (0x6761u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1990                                            (0x0ACFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1991                                            (0x3D58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1992                                            (0x257Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1993                                            (0x44F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1994                                            (0x62EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1995                                            (0x4CB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1996                                            (0x659Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1997                                            (0x7A07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1998                                            (0x5C33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1999                                            (0x2BA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2000                                            (0x703Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2001                                            (0x5D58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2002                                            (0x7139u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2003                                            (0x3656u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2004                                            (0x4EB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2005                                            (0x7E81u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2006                                            (0x33E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2007                                            (0x2CADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2008                                            (0x59CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2009                                            (0x1EB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2010                                            (0x3764u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2011                                            (0x23D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2012                                            (0x4537u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2013                                            (0x7651u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2014                                            (0x7591u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2015                                            (0x4E6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2016                                            (0x1679u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2017                                            (0x259Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2018                                            (0x389Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2019                                            (0x1FB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2020                                            (0x3F09u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2021                                            (0x227Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2022                                            (0x74C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2023                                            (0x70F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2024                                            (0x14DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2025                                            (0x61B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2026                                            (0x336Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2027                                            (0x619Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2028                                            (0x266Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2029                                            (0x4C2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2030                                            (0x6F22u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2031                                            (0x58E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2032                                            (0x26EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2033                                            (0x3E8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2034                                            (0x28DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2035                                            (0x72D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2036                                            (0x1F54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2037                                            (0x07ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2038                                            (0x0BCBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2039                                            (0x7709u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2040                                            (0x4A5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2041                                            (0x3CD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2042                                            (0x0F17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2043                                            (0x24EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2044                                            (0x3C4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2045                                            (0x0ED9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2046                                            (0x7865u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2047                                            (0x4477u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2048                                            (0x6738u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2049                                            (0x2E96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2050                                            (0x6A63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2051                                            (0x7D48u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2052                                            (0x419Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2053                                            (0x58D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2054                                            (0x6EC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2055                                            (0x427Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2056                                            (0x52D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2057                                            (0x13D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2058                                            (0x5C78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2059                                            (0x63A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2060                                            (0x3E1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2061                                            (0x6B8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2062                                            (0x31DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2063                                            (0x6B32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2064                                            (0x74D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2065                                            (0x374Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2066                                            (0x6666u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2067                                            (0x4C97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2068                                            (0x269Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2069                                            (0x41CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2070                                            (0x1A9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2071                                            (0x4DB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2072                                            (0x31EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2073                                            (0x1E74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2074                                            (0x762Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2075                                            (0x70D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2076                                            (0x0B4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2077                                            (0x653Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2078                                            (0x7C31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2079                                            (0x4ED1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2080                                            (0x30F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2081                                            (0x11B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2082                                            (0x48DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2083                                            (0x0767u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2084                                            (0x125Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2085                                            (0x3CB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2086                                            (0x7586u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2087                                            (0x0FE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2088                                            (0x62AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2089                                            (0x3536u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2090                                            (0x7117u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2091                                            (0x6D15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2092                                            (0x0FD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2093                                            (0x3A1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2094                                            (0x5D1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2095                                            (0x0A7Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2096                                            (0x0A5Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2097                                            (0x4CCDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2098                                            (0x314Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2099                                            (0x3A9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2100                                            (0x670Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2101                                            (0x523Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2102                                            (0x58BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2103                                            (0x3157u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2104                                            (0x3770u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2105                                            (0x3972u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2106                                            (0x2ACDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2107                                            (0x71C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2108                                            (0x4F51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2109                                            (0x1A97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2110                                            (0x34CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2111                                            (0x622Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2112                                            (0x514Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2113                                            (0x1736u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2114                                            (0x23CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2115                                            (0x72B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2116                                            (0x7552u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2117                                            (0x1B1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2118                                            (0x6175u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2119                                            (0x3AE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2120                                            (0x32EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2121                                            (0x2727u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2122                                            (0x66C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2123                                            (0x4EC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2124                                            (0x16BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2125                                            (0x4717u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2126                                            (0x558Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2127                                            (0x7C98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2128                                            (0x734Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2129                                            (0x2EA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2130                                            (0x358Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2131                                            (0x54D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2132                                            (0x12EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2133                                            (0x7E50u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2134                                            (0x523Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2135                                            (0x6BA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2136                                            (0x0CF3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2137                                            (0x78A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2138                                            (0x5716u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2139                                            (0x351Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2140                                            (0x157Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2141                                            (0x2997u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2142                                            (0x718Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2143                                            (0x7992u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2144                                            (0x5A9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2145                                            (0x2BB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2146                                            (0x455Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2147                                            (0x569Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2148                                            (0x3CA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2149                                            (0x2B2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2150                                            (0x6837u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2151                                            (0x58D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2152                                            (0x2E87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2153                                            (0x1FD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2154                                            (0x58ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2155                                            (0x786Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2156                                            (0x5F18u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2157                                            (0x5A8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2158                                            (0x4D9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2159                                            (0x453Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2160                                            (0x2F2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2161                                            (0x11CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2162                                            (0x0F4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2163                                            (0x48EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2164                                            (0x2EC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2165                                            (0x2B27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2166                                            (0x31DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2167                                            (0x66D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2168                                            (0x1E6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2169                                            (0x7CC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2170                                            (0x0AF6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2171                                            (0x52AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2172                                            (0x48FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2173                                            (0x2AC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2174                                            (0x69E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2175                                            (0x1C37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2176                                            (0x3ACAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2177                                            (0x174Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2178                                            (0x68B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2179                                            (0x17F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2180                                            (0x1C3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2181                                            (0x59A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2182                                            (0x2C57u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2183                                            (0x5F14u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2184                                            (0x3EA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2185                                            (0x43E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2186                                            (0x4D39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2187                                            (0x32CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2188                                            (0x2597u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2189                                            (0x4F8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2190                                            (0x11F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2191                                            (0x15D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2192                                            (0x351Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2193                                            (0x4AB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2194                                            (0x7073u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2195                                            (0x331Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2196                                            (0x3A8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2197                                            (0x39B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2198                                            (0x341Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2199                                            (0x62F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2200                                            (0x43B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2201                                            (0x4DA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2202                                            (0x4ADAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2203                                            (0x546Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2204                                            (0x4FA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2205                                            (0x6647u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2206                                            (0x654Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2207                                            (0x17D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2208                                            (0x05FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2209                                            (0x4AAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2210                                            (0x7239u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2211                                            (0x0F74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2212                                            (0x02BFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2213                                            (0x4E63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2214                                            (0x7076u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2215                                            (0x0EABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2216                                            (0x6C71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2217                                            (0x21B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2218                                            (0x49C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2219                                            (0x754Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2220                                            (0x58E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2221                                            (0x6867u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2222                                            (0x5E61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2223                                            (0x398Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2224                                            (0x7685u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2225                                            (0x366Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2226                                            (0x6A5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2227                                            (0x03EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2228                                            (0x5C4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2229                                            (0x171Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2230                                            (0x45D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2231                                            (0x649Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2232                                            (0x261Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2233                                            (0x137Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2234                                            (0x596Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2235                                            (0x3C72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2236                                            (0x4AD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2237                                            (0x2B9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2238                                            (0x56F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2239                                            (0x2DCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2240                                            (0x578Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2241                                            (0x3467u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2242                                            (0x36B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2243                                            (0x22DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2244                                            (0x339Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2245                                            (0x07DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2246                                            (0x07B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2247                                            (0x1597u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2248                                            (0x47B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2249                                            (0x6D19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2250                                            (0x2667u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2251                                            (0x6D25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2252                                            (0x09DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2253                                            (0x33A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2254                                            (0x1D9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2255                                            (0x6CD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2256                                            (0x1CA7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2257                                            (0x43F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2258                                            (0x2F68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2259                                            (0x227Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2260                                            (0x4F46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2261                                            (0x3E92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2262                                            (0x698Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2263                                            (0x359Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2264                                            (0x6A9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2265                                            (0x7714u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2266                                            (0x6347u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2267                                            (0x16B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2268                                            (0x3DD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2269                                            (0x66F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2270                                            (0x6873u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2271                                            (0x589Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2272                                            (0x621Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2273                                            (0x61BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2274                                            (0x23ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2275                                            (0x1F32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2276                                            (0x6E0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2277                                            (0x78A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2278                                            (0x6E32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2279                                            (0x6AD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2280                                            (0x0DECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2281                                            (0x51B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2282                                            (0x2ED4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2283                                            (0x3837u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2284                                            (0x0FB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2285                                            (0x22BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2286                                            (0x2FD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2287                                            (0x695Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2288                                            (0x4E36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2289                                            (0x2E8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2290                                            (0x553Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2291                                            (0x4975u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2292                                            (0x25CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2293                                            (0x43D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2294                                            (0x6359u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2295                                            (0x6751u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2296                                            (0x0B6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2297                                            (0x729Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2298                                            (0x217Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2299                                            (0x598Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2300                                            (0x4E4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2301                                            (0x49ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2302                                            (0x746Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2303                                            (0x3D0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2304                                            (0x25B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2305                                            (0x1A9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2306                                            (0x21EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2307                                            (0x5E68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2308                                            (0x7A43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2309                                            (0x1A3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2310                                            (0x5D0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2311                                            (0x4795u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2312                                            (0x0F8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2313                                            (0x5C5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2314                                            (0x7523u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2315                                            (0x251Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2316                                            (0x7915u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2317                                            (0x493Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2318                                            (0x2ADAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2319                                            (0x3C4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2320                                            (0x7E11u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2321                                            (0x1D2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2322                                            (0x3A63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2323                                            (0x0F5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2324                                            (0x5C99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2325                                            (0x5AE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2326                                            (0x17A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2327                                            (0x0BB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2328                                            (0x07B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2329                                            (0x1F0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2330                                            (0x6E70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2331                                            (0x389Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2332                                            (0x631Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2333                                            (0x45CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2334                                            (0x4B9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2335                                            (0x2877u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2336                                            (0x32ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2337                                            (0x5C56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2338                                            (0x3E8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2339                                            (0x6DD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2340                                            (0x6927u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2341                                            (0x5C3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2342                                            (0x6BC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2343                                            (0x5D46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2344                                            (0x6E51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2345                                            (0x742Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2346                                            (0x536Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2347                                            (0x543Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2348                                            (0x3987u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2349                                            (0x2AF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2350                                            (0x3A17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2351                                            (0x62D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2352                                            (0x2B4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2353                                            (0x60AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2354                                            (0x19CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2355                                            (0x4CE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2356                                            (0x5467u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2357                                            (0x52CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2358                                            (0x5C6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2359                                            (0x561Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2360                                            (0x06FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2361                                            (0x616Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2362                                            (0x68D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2363                                            (0x3E45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2364                                            (0x274Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2365                                            (0x1E39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2366                                            (0x60FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2367                                            (0x728Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2368                                            (0x76C1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2369                                            (0x3EA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2370                                            (0x178Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2371                                            (0x7964u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2372                                            (0x6DA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2373                                            (0x61D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2374                                            (0x14BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2375                                            (0x613Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2376                                            (0x58E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2377                                            (0x3AA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2378                                            (0x712Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2379                                            (0x44CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2380                                            (0x7171u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2381                                            (0x783Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2382                                            (0x6E85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2383                                            (0x44BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2384                                            (0x5DC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2385                                            (0x76A4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2386                                            (0x6969u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2387                                            (0x328Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2388                                            (0x3372u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2389                                            (0x1E5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2390                                            (0x68E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2391                                            (0x615Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2392                                            (0x6CB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2393                                            (0x1BB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2394                                            (0x13C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2395                                            (0x2F52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2396                                            (0x24DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2397                                            (0x7A83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2398                                            (0x7CA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2399                                            (0x2A8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2400                                            (0x79A4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2401                                            (0x0F53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2402                                            (0x58B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2403                                            (0x3C69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2404                                            (0x03DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2405                                            (0x648Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2406                                            (0x49B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2407                                            (0x4A3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2408                                            (0x7B60u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2409                                            (0x67A8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2410                                            (0x25BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2411                                            (0x34CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2412                                            (0x192Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2413                                            (0x7C2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2414                                            (0x07CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2415                                            (0x4AEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2416                                            (0x78C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2417                                            (0x7853u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2418                                            (0x19B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2419                                            (0x686Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2420                                            (0x34E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2421                                            (0x1CADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2422                                            (0x7913u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2423                                            (0x2DB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2424                                            (0x32D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2425                                            (0x6AA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2426                                            (0x554Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2427                                            (0x74A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2428                                            (0x355Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2429                                            (0x5BC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2430                                            (0x199Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2431                                            (0x7147u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2432                                            (0x672Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2433                                            (0x4F52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2434                                            (0x5356u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2435                                            (0x7E44u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2436                                            (0x2567u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2437                                            (0x447Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2438                                            (0x13A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2439                                            (0x744Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2440                                            (0x057Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2441                                            (0x2357u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2442                                            (0x5393u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2443                                            (0x614Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2444                                            (0x055Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2445                                            (0x7227u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2446                                            (0x57C2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2447                                            (0x7961u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2448                                            (0x3A33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2449                                            (0x18AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2450                                            (0x658Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2451                                            (0x1F91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2452                                            (0x3BD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2453                                            (0x3F44u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2454                                            (0x4D72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2455                                            (0x54D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2456                                            (0x2DE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2457                                            (0x4772u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2458                                            (0x26B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2459                                            (0x36C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2460                                            (0x1FC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2461                                            (0x05DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2462                                            (0x0BE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2463                                            (0x4AF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2464                                            (0x2B2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2465                                            (0x07E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2466                                            (0x245Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2467                                            (0x3D25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2468                                            (0x5EC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2469                                            (0x69D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2470                                            (0x174Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2471                                            (0x3563u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2472                                            (0x07EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2473                                            (0x32ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2474                                            (0x25D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2475                                            (0x35D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2476                                            (0x3275u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2477                                            (0x3647u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2478                                            (0x6E4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2479                                            (0x27D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2480                                            (0x6D70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2481                                            (0x6752u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2482                                            (0x7C52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2483                                            (0x343Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2484                                            (0x272Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2485                                            (0x7AE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2486                                            (0x1BA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2487                                            (0x51D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2488                                            (0x2EAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2489                                            (0x20FBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2490                                            (0x2E65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2491                                            (0x4CC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2492                                            (0x2CF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2493                                            (0x66E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2494                                            (0x353Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2495                                            (0x2F15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2496                                            (0x3A96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2497                                            (0x24F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2498                                            (0x2A7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2499                                            (0x4277u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2500                                            (0x58D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2501                                            (0x1DC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2502                                            (0x4ACEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2503                                            (0x0377u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2504                                            (0x358Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2505                                            (0x4B8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2506                                            (0x6E15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2507                                            (0x0ECDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2508                                            (0x7C8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2509                                            (0x4CD5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2510                                            (0x6699u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2511                                            (0x64F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2512                                            (0x75C4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2513                                            (0x665Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2514                                            (0x5A47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2515                                            (0x51DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2516                                            (0x7A45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2517                                            (0x6B07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2518                                            (0x312Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2519                                            (0x338Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2520                                            (0x17C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2521                                            (0x7A68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2522                                            (0x44FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2523                                            (0x532Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2524                                            (0x30DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2525                                            (0x5798u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2526                                            (0x31CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2527                                            (0x3A72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2528                                            (0x5DC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2529                                            (0x5CC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2530                                            (0x5770u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2531                                            (0x2765u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2532                                            (0x5D8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2533                                            (0x1AE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2534                                            (0x1B56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2535                                            (0x5339u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2536                                            (0x7925u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2537                                            (0x5947u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2538                                            (0x6AC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2539                                            (0x4679u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2540                                            (0x570Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2541                                            (0x66D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2542                                            (0x18F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2543                                            (0x652Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2544                                            (0x5758u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2545                                            (0x568Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2546                                            (0x692Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2547                                            (0x479Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2548                                            (0x1CE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2549                                            (0x2ADCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2550                                            (0x7748u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2551                                            (0x346Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2552                                            (0x754Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2553                                            (0x720Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2554                                            (0x1AE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2555                                            (0x14F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2556                                            (0x5A2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2557                                            (0x56A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2558                                            (0x2F0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2559                                            (0x2D1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2560                                            (0x0EE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2561                                            (0x11F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2562                                            (0x28F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2563                                            (0x22FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2564                                            (0x3F48u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2565                                            (0x0E79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2566                                            (0x6DC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2567                                            (0x64D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2568                                            (0x7236u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2569                                            (0x4B3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2570                                            (0x7316u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2571                                            (0x36CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2572                                            (0x61F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2573                                            (0x439Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2574                                            (0x7991u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2575                                            (0x14EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2576                                            (0x65D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2577                                            (0x2A5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2578                                            (0x19DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2579                                            (0x55C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2580                                            (0x1BD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2581                                            (0x69C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2582                                            (0x6974u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2583                                            (0x6E89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2584                                            (0x561Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2585                                            (0x69F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2586                                            (0x43ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2587                                            (0x3D83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2588                                            (0x366Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2589                                            (0x47B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2590                                            (0x68CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2591                                            (0x7538u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2592                                            (0x6AB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2593                                            (0x3335u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2594                                            (0x56A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2595                                            (0x58D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2596                                            (0x74D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2597                                            (0x0FCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2598                                            (0x3C1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2599                                            (0x0B9Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2600                                            (0x6E34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2601                                            (0x4CA7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2602                                            (0x1B87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2603                                            (0x34F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2604                                            (0x1C3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2605                                            (0x60BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2606                                            (0x38D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2607                                            (0x4B66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2608                                            (0x345Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2609                                            (0x1771u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2610                                            (0x688Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2611                                            (0x3CCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2612                                            (0x6E54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2613                                            (0x6A99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2614                                            (0x58A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2615                                            (0x0F47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2616                                            (0x2CEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2617                                            (0x24BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2618                                            (0x2F58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2619                                            (0x1B36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2620                                            (0x66B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2621                                            (0x50E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2622                                            (0x0D97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2623                                            (0x5655u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2624                                            (0x1F4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2625                                            (0x1373u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2626                                            (0x590Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2627                                            (0x71A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2628                                            (0x2B63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2629                                            (0x784Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2630                                            (0x46D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2631                                            (0x39E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2632                                            (0x2D65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2633                                            (0x6A17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2634                                            (0x33E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2635                                            (0x342Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2636                                            (0x0A6Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2637                                            (0x2A76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2638                                            (0x4673u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2639                                            (0x5E34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2640                                            (0x5372u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2641                                            (0x2C3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2642                                            (0x0EEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2643                                            (0x5D70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2644                                            (0x4F4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2645                                            (0x361Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2646                                            (0x33AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2647                                            (0x3EB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2648                                            (0x0DCDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2649                                            (0x4E8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2650                                            (0x2F2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2651                                            (0x365Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2652                                            (0x5A4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2653                                            (0x5A74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2654                                            (0x61ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2655                                            (0x1D72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2656                                            (0x7A26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2657                                            (0x53B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2658                                            (0x78F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2659                                            (0x23E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2660                                            (0x56D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2661                                            (0x2CDAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2662                                            (0x3A1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2663                                            (0x159Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2664                                            (0x18FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2665                                            (0x7C94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2666                                            (0x25E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2667                                            (0x1BB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2668                                            (0x25F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2669                                            (0x3C17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2670                                            (0x2FB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2671                                            (0x65A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2672                                            (0x634Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2673                                            (0x0CEDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2674                                            (0x05D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2675                                            (0x6D62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2676                                            (0x65C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2677                                            (0x55E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2678                                            (0x199Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2679                                            (0x65C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2680                                            (0x6E8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2681                                            (0x42FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2682                                            (0x1DE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2683                                            (0x4C4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2684                                            (0x40F7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2685                                            (0x7EC0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2686                                            (0x0B7Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2687                                            (0x7A91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2688                                            (0x6D52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2689                                            (0x4E8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2690                                            (0x492Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2691                                            (0x3A93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2692                                            (0x35C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2693                                            (0x6CE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2694                                            (0x33D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2695                                            (0x0CF5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2696                                            (0x66CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2697                                            (0x716Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2698                                            (0x16E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2699                                            (0x42F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2700                                            (0x593Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2701                                            (0x3F18u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2702                                            (0x264Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2703                                            (0x1755u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2704                                            (0x6E64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2705                                            (0x55F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2706                                            (0x5B43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2707                                            (0x4AE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2708                                            (0x74E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2709                                            (0x4763u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2710                                            (0x59A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2711                                            (0x252Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2712                                            (0x6AACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2713                                            (0x4D96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2714                                            (0x2C7Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2715                                            (0x4B2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2716                                            (0x21AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2717                                            (0x4E9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2718                                            (0x1D95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2719                                            (0x391Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2720                                            (0x7782u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2721                                            (0x2BC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2722                                            (0x23EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2723                                            (0x69A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2724                                            (0x354Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2725                                            (0x2EB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2726                                            (0x1D55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2727                                            (0x2DC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2728                                            (0x652Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2729                                            (0x5C4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2730                                            (0x6C55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2731                                            (0x167Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2732                                            (0x2BE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2733                                            (0x15AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2734                                            (0x6E52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2735                                            (0x7193u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2736                                            (0x25ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2737                                            (0x4D33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2738                                            (0x215Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2739                                            (0x613Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2740                                            (0x22DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2741                                            (0x6665u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2742                                            (0x7195u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2743                                            (0x7A0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2744                                            (0x7362u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2745                                            (0x6EA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2746                                            (0x0DCEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2747                                            (0x7661u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2748                                            (0x63D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2749                                            (0x4979u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2750                                            (0x25CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2751                                            (0x5F28u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2752                                            (0x5327u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2753                                            (0x0F72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2754                                            (0x0A3Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2755                                            (0x0CD7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2756                                            (0x48E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2757                                            (0x63CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2758                                            (0x2E99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2759                                            (0x117Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2760                                            (0x2A6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2761                                            (0x4CEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2762                                            (0x4BB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2763                                            (0x1ED2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2764                                            (0x2EC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2765                                            (0x385Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2766                                            (0x16B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2767                                            (0x32F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2768                                            (0x69CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2769                                            (0x433Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2770                                            (0x35B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2771                                            (0x1E87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2772                                            (0x6E45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2773                                            (0x61F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2774                                            (0x7525u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2775                                            (0x547Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2776                                            (0x63AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2777                                            (0x1717u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2778                                            (0x1C76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2779                                            (0x7F40u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2780                                            (0x3A69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2781                                            (0x4C3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2782                                            (0x497Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2783                                            (0x6F30u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2784                                            (0x29D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2785                                            (0x55D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2786                                            (0x5473u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2787                                            (0x70F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2788                                            (0x2C76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2789                                            (0x02F7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2790                                            (0x3A71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2791                                            (0x0E3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2792                                            (0x03F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2793                                            (0x33B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2794                                            (0x542Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2795                                            (0x6E29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2796                                            (0x515Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2797                                            (0x11EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2798                                            (0x7255u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2799                                            (0x663Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2800                                            (0x0EE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2801                                            (0x7718u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2802                                            (0x50F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2803                                            (0x1B93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2804                                            (0x729Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2805                                            (0x5AB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2806                                            (0x319Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2807                                            (0x6C36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2808                                            (0x48BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2809                                            (0x3693u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2810                                            (0x2A57u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2811                                            (0x5D0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2812                                            (0x1B55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2813                                            (0x790Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2814                                            (0x42BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2815                                            (0x13B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2816                                            (0x2CCEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2817                                            (0x23F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2818                                            (0x7B90u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2819                                            (0x1937u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2820                                            (0x543Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2821                                            (0x5D92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2822                                            (0x256Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2823                                            (0x6F88u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2824                                            (0x139Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2825                                            (0x5F0Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2826                                            (0x7343u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2827                                            (0x096Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2828                                            (0x4F64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2829                                            (0x7235u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2830                                            (0x68D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2831                                            (0x7DC0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2832                                            (0x38E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2833                                            (0x3C93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2834                                            (0x385Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2835                                            (0x38E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2836                                            (0x19EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2837                                            (0x2C75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2838                                            (0x6CA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2839                                            (0x7338u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2840                                            (0x2CBCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2841                                            (0x3935u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2842                                            (0x506Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2843                                            (0x5D85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2844                                            (0x15ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2845                                            (0x53B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2846                                            (0x731Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2847                                            (0x3559u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2848                                            (0x24F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2849                                            (0x68E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2850                                            (0x3B38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2851                                            (0x4BE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2852                                            (0x299Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2853                                            (0x59E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2854                                            (0x3B83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2855                                            (0x2AE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2856                                            (0x07D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2857                                            (0x52B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2858                                            (0x6635u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2859                                            (0x1F25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2860                                            (0x7391u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2861                                            (0x37C1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2862                                            (0x06F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2863                                            (0x19F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2864                                            (0x4EB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2865                                            (0x1E72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2866                                            (0x4B4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2867                                            (0x31F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2868                                            (0x3978u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2869                                            (0x6A55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2870                                            (0x0EECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2871                                            (0x5E92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2872                                            (0x685Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2873                                            (0x2DA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2874                                            (0x3DA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2875                                            (0x439Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2876                                            (0x7570u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2877                                            (0x48CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2878                                            (0x595Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2879                                            (0x513Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2880                                            (0x0BABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2881                                            (0x61CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2882                                            (0x60F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2883                                            (0x50B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2884                                            (0x1B47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2885                                            (0x1B74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2886                                            (0x5BB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2887                                            (0x31F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2888                                            (0x13B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2889                                            (0x6F0Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2890                                            (0x3167u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2891                                            (0x60FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2892                                            (0x7989u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2893                                            (0x3695u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2894                                            (0x4B3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2895                                            (0x7A4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2896                                            (0x5B52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2897                                            (0x4AD5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2898                                            (0x68DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2899                                            (0x15E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2900                                            (0x572Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2901                                            (0x730Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2902                                            (0x369Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2903                                            (0x5A39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2904                                            (0x4ECAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2905                                            (0x5DE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2906                                            (0x7728u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2907                                            (0x6F48u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2908                                            (0x077Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2909                                            (0x69E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2910                                            (0x2739u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2911                                            (0x19B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2912                                            (0x6497u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2913                                            (0x2C8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2914                                            (0x1637u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2915                                            (0x316Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2916                                            (0x3F24u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2917                                            (0x0B67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2918                                            (0x3AACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2919                                            (0x227Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2920                                            (0x15CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2921                                            (0x658Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2922                                            (0x3D16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2923                                            (0x6E92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2924                                            (0x2E0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2925                                            (0x494Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2926                                            (0x2B66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2927                                            (0x2C67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2928                                            (0x7896u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2929                                            (0x31E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2930                                            (0x4579u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2931                                            (0x1B8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2932                                            (0x2576u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2933                                            (0x3437u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2934                                            (0x3AE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2935                                            (0x73A8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2936                                            (0x74AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2937                                            (0x5C35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2938                                            (0x0CE7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2939                                            (0x7619u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2940                                            (0x79B0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2941                                            (0x1EA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2942                                            (0x623Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2943                                            (0x547Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2944                                            (0x12CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2945                                            (0x4CBCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2946                                            (0x2AD5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2947                                            (0x2CD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2948                                            (0x1DA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2949                                            (0x691Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2950                                            (0x7A85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2951                                            (0x4796u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2952                                            (0x66C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2953                                            (0x4D8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2954                                            (0x535Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2955                                            (0x3D4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2956                                            (0x23BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2957                                            (0x6E8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2958                                            (0x48BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2959                                            (0x5867u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2960                                            (0x41F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2961                                            (0x5CE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2962                                            (0x1CE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2963                                            (0x5CD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2964                                            (0x3A39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2965                                            (0x3678u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2966                                            (0x35D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2967                                            (0x5956u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2968                                            (0x7E82u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2969                                            (0x0FAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2970                                            (0x2ECCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2971                                            (0x63D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2972                                            (0x5B85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2973                                            (0x617Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2974                                            (0x7562u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2975                                            (0x2A67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2976                                            (0x368Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2977                                            (0x79E0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2978                                            (0x4F45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2979                                            (0x3197u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2980                                            (0x5C53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2981                                            (0x0CBDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2982                                            (0x2E59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2983                                            (0x527Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2984                                            (0x770Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2985                                            (0x2A5Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2986                                            (0x2BD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2987                                            (0x2E5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2988                                            (0x42BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2989                                            (0x76C2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2990                                            (0x6BD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2991                                            (0x3E54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2992                                            (0x6F14u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2993                                            (0x6966u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2994                                            (0x2CE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2995                                            (0x664Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2996                                            (0x62DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2997                                            (0x31A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2998                                            (0x2F19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2999                                            (0x6A33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3000                                            (0x2BCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3001                                            (0x4EC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3002                                            (0x6AE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3003                                            (0x2F0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3004                                            (0x2F38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3005                                            (0x493Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3006                                            (0x15D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3007                                            (0x1A7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3008                                            (0x3DA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3009                                            (0x5EC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3010                                            (0x12E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3011                                            (0x7629u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3012                                            (0x62B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3013                                            (0x6669u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3014                                            (0x7D0Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3015                                            (0x187Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3016                                            (0x4BE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3017                                            (0x3399u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3018                                            (0x332Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3019                                            (0x0B9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3020                                            (0x68F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3021                                            (0x70CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3022                                            (0x69A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3023                                            (0x4AD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3024                                            (0x2CE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3025                                            (0x4367u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3026                                            (0x28F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3027                                            (0x3AE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3028                                            (0x19C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3029                                            (0x0DD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3030                                            (0x1787u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3031                                            (0x3BC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3032                                            (0x1DE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3033                                            (0x6599u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3034                                            (0x7079u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3035                                            (0x4DAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3036                                            (0x5317u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3037                                            (0x4F2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3038                                            (0x7D09u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3039                                            (0x18F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3040                                            (0x17A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3041                                            (0x706Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3042                                            (0x02DFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3043                                            (0x3666u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3044                                            (0x64DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3045                                            (0x5635u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3046                                            (0x03DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3047                                            (0x1DE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3048                                            (0x7CC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3049                                            (0x48DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3050                                            (0x6CB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3051                                            (0x68CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3052                                            (0x2979u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3053                                            (0x52F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3054                                            (0x26C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3055                                            (0x2BD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3056                                            (0x5347u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3057                                            (0x372Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3058                                            (0x41EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3059                                            (0x0E9Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3060                                            (0x0B5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3061                                            (0x07E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3062                                            (0x1B96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3063                                            (0x5A78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3064                                            (0x09EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3065                                            (0x45ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3066                                            (0x37A2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3067                                            (0x0FD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3068                                            (0x45BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3069                                            (0x15F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3070                                            (0x515Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3071                                            (0x7272u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3072                                            (0x388Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3073                                            (0x1F2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3074                                            (0x287Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3075                                            (0x7A0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3076                                            (0x72CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3077                                            (0x1E2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3078                                            (0x25D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3079                                            (0x2D56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3080                                            (0x478Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3081                                            (0x1BAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3082                                            (0x79C8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3083                                            (0x6A0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3084                                            (0x6A8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3085                                            (0x0BCEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3086                                            (0x67B0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3087                                            (0x2D17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3088                                            (0x394Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3089                                            (0x70ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3090                                            (0x26ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3091                                            (0x1BACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3092                                            (0x49D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3093                                            (0x4CCEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3094                                            (0x5875u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3095                                            (0x7037u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3096                                            (0x543Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3097                                            (0x714Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3098                                            (0x7293u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3099                                            (0x6B34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3100                                            (0x7781u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3101                                            (0x4BB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3102                                            (0x4D47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3103                                            (0x71C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3104                                            (0x1C79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3105                                            (0x1477u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3106                                            (0x661Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3107                                            (0x26AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3108                                            (0x0ED6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3109                                            (0x68B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3110                                            (0x374Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3111                                            (0x5267u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3112                                            (0x636Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3113                                            (0x69C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3114                                            (0x7668u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3115                                            (0x417Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3116                                            (0x4E96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3117                                            (0x147Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3118                                            (0x378Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3119                                            (0x14BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3120                                            (0x17E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3121                                            (0x483Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3122                                            (0x63E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3123                                            (0x78D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3124                                            (0x7133u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3125                                            (0x0B8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3126                                            (0x7D41u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3127                                            (0x1D69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3128                                            (0x6AE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3129                                            (0x4676u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3130                                            (0x698Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3131                                            (0x790Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3132                                            (0x7169u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3133                                            (0x4573u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3134                                            (0x6457u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3135                                            (0x27B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3136                                            (0x09BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3137                                            (0x3A78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3138                                            (0x1D17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3139                                            (0x15C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3140                                            (0x1CECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3141                                            (0x6CCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3142                                            (0x656Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3143                                            (0x5E51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3144                                            (0x2D4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3145                                            (0x3457u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3146                                            (0x2975u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3147                                            (0x05FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3148                                            (0x5D26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3149                                            (0x7385u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3150                                            (0x51E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3151                                            (0x2679u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3152                                            (0x2E3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3153                                            (0x35B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3154                                            (0x3F0Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3155                                            (0x095Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3156                                            (0x587Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3157                                            (0x7C70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3158                                            (0x463Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3159                                            (0x696Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3160                                            (0x3A74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3161                                            (0x03EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3162                                            (0x47A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3163                                            (0x61D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3164                                            (0x267Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3165                                            (0x791Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3166                                            (0x79A8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3167                                            (0x7664u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3168                                            (0x6369u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3169                                            (0x36D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3170                                            (0x6955u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3171                                            (0x7705u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3172                                            (0x36CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3173                                            (0x07B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3174                                            (0x711Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3175                                            (0x5F09u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3176                                            (0x565Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3177                                            (0x71E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3178                                            (0x07BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3179                                            (0x6F03u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3180                                            (0x741Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3181                                            (0x5A55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3182                                            (0x16D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3183                                            (0x326Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3184                                            (0x7AA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3185                                            (0x1CD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3186                                            (0x453Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3187                                            (0x05CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3188                                            (0x097Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3189                                            (0x6639u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3190                                            (0x4A8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3191                                            (0x2D55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3192                                            (0x511Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3193                                            (0x175Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3194                                            (0x5EA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3195                                            (0x1F45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3196                                            (0x436Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3197                                            (0x66D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3198                                            (0x563Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3199                                            (0x0DD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3200                                            (0x4D93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3201                                            (0x5719u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3202                                            (0x3AE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3203                                            (0x1E3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3204                                            (0x335Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3205                                            (0x2BC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3206                                            (0x3E70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3207                                            (0x0F66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3208                                            (0x55CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3209                                            (0x70BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3210                                            (0x45DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3211                                            (0x2DB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3212                                            (0x338Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3213                                            (0x34A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3214                                            (0x06EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3215                                            (0x6D32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3216                                            (0x7C13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3217                                            (0x634Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3218                                            (0x0BE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3219                                            (0x4D5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3220                                            (0x4F94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3221                                            (0x716Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3222                                            (0x3971u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3223                                            (0x705Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3224                                            (0x5D61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3225                                            (0x7872u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3226                                            (0x723Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3227                                            (0x394Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3228                                            (0x3363u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3229                                            (0x6396u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3230                                            (0x34EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3231                                            (0x0D75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3232                                            (0x6723u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3233                                            (0x325Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3234                                            (0x58ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3235                                            (0x5D89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3236                                            (0x296Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3237                                            (0x0DDCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3238                                            (0x1F58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3239                                            (0x7B06u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3240                                            (0x74C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3241                                            (0x0A77u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3242                                            (0x7B22u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3243                                            (0x352Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3244                                            (0x3A4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3245                                            (0x1EB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3246                                            (0x6C66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3247                                            (0x545Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3248                                            (0x54F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3249                                            (0x585Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3250                                            (0x5C2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3251                                            (0x2CECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3252                                            (0x7847u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3253                                            (0x036Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3254                                            (0x7698u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3255                                            (0x72C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3256                                            (0x1FC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3257                                            (0x4A73u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3258                                            (0x7499u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3259                                            (0x78C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3260                                            (0x03EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3261                                            (0x4C1Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3262                                            (0x31C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3263                                            (0x5A63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3264                                            (0x5C3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3265                                            (0x63E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3266                                            (0x7389u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3267                                            (0x5695u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3268                                            (0x6AF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3269                                            (0x23C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3270                                            (0x607Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3271                                            (0x66CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3272                                            (0x631Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3273                                            (0x057Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3274                                            (0x568Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3275                                            (0x2E33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3276                                            (0x3179u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3277                                            (0x5A99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3278                                            (0x7592u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3279                                            (0x6372u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3280                                            (0x794Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3281                                            (0x0F69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3282                                            (0x5C72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3283                                            (0x4A3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3284                                            (0x49F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3285                                            (0x7253u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3286                                            (0x507Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3287                                            (0x615Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3288                                            (0x4CABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3289                                            (0x5D98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3290                                            (0x1756u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3291                                            (0x53CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3292                                            (0x4EAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3293                                            (0x7383u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3294                                            (0x0D9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3295                                            (0x139Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3296                                            (0x5E07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3297                                            (0x0F56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3298                                            (0x34F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3299                                            (0x7B11u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3300                                            (0x3875u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3301                                            (0x0DE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3302                                            (0x04FDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3303                                            (0x43B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3304                                            (0x3857u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3305                                            (0x1ECAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3306                                            (0x18DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3307                                            (0x1A1Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3308                                            (0x13DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3309                                            (0x4FB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3310                                            (0x6B43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3311                                            (0x54B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3312                                            (0x5AB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3313                                            (0x3783u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3314                                            (0x4E3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3315                                            (0x3959u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3316                                            (0x0AF9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3317                                            (0x463Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3318                                            (0x7546u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3319                                            (0x4E27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3320                                            (0x730Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3321                                            (0x4B1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3322                                            (0x1753u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3323                                            (0x1F26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3324                                            (0x343Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3325                                            (0x7B21u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3326                                            (0x43ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3327                                            (0x4EA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3328                                            (0x38F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3329                                            (0x1F70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3330                                            (0x0757u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3331                                            (0x4D3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3332                                            (0x279Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3333                                            (0x74B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3334                                            (0x1F98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3335                                            (0x1673u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3336                                            (0x313Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3337                                            (0x2D53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3338                                            (0x0BBAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3339                                            (0x0B7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3340                                            (0x59D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3341                                            (0x69D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3342                                            (0x02FDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3343                                            (0x5663u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3344                                            (0x0B76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3345                                            (0x165Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3346                                            (0x7F20u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3347                                            (0x647Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3348                                            (0x4756u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3349                                            (0x71B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3350                                            (0x7A8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3351                                            (0x2763u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3352                                            (0x2FA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3353                                            (0x353Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3354                                            (0x4BCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3355                                            (0x17E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3356                                            (0x3669u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3357                                            (0x067Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3358                                            (0x27CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3359                                            (0x651Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3360                                            (0x0EF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3361                                            (0x0BADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3362                                            (0x38A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3363                                            (0x7A2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3364                                            (0x6D4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3365                                            (0x49BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3366                                            (0x7334u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3367                                            (0x64ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3368                                            (0x709Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3369                                            (0x59C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3370                                            (0x768Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3371                                            (0x645Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3372                                            (0x31BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3373                                            (0x4778u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3374                                            (0x1AF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3375                                            (0x14AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3376                                            (0x4BF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3377                                            (0x3671u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3378                                            (0x0D3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3379                                            (0x3B2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3380                                            (0x7EA0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3381                                            (0x5978u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3382                                            (0x7E88u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3383                                            (0x3C2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3384                                            (0x2DD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3385                                            (0x361Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3386                                            (0x18BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3387                                            (0x429Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3388                                            (0x3C35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3389                                            (0x239Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3390                                            (0x6D8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3391                                            (0x1EA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3392                                            (0x23F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3393                                            (0x1F38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3394                                            (0x5C69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3395                                            (0x28FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3396                                            (0x4F07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3397                                            (0x7A16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3398                                            (0x535Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3399                                            (0x0FA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3400                                            (0x45DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3401                                            (0x5B29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3402                                            (0x0C7Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3403                                            (0x4F31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3404                                            (0x4736u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3405                                            (0x1EC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3406                                            (0x6B4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3407                                            (0x68A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3408                                            (0x798Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3409                                            (0x319Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3410                                            (0x25E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3411                                            (0x62B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3412                                            (0x237Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3413                                            (0x19A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3414                                            (0x13E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3415                                            (0x2EA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3416                                            (0x2F54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3417                                            (0x329Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3418                                            (0x69A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3419                                            (0x26F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3420                                            (0x443Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3421                                            (0x5569u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3422                                            (0x4C79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3423                                            (0x2E3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3424                                            (0x46BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3425                                            (0x263Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3426                                            (0x6527u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3427                                            (0x6B61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3428                                            (0x3297u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3429                                            (0x62D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3430                                            (0x3996u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3431                                            (0x138Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3432                                            (0x0D73u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3433                                            (0x794Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3434                                            (0x69A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3435                                            (0x39AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3436                                            (0x2D96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3437                                            (0x4337u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3438                                            (0x78C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3439                                            (0x5D54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3440                                            (0x459Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3441                                            (0x2D27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3442                                            (0x5E0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3443                                            (0x1C57u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3444                                            (0x6C4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3445                                            (0x32B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3446                                            (0x2676u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3447                                            (0x6999u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3448                                            (0x348Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3449                                            (0x5A71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3450                                            (0x516Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3451                                            (0x6395u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3452                                            (0x293Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3453                                            (0x26ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3454                                            (0x7A92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3455                                            (0x259Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3456                                            (0x1675u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3457                                            (0x7516u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3458                                            (0x229Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3459                                            (0x4EE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3460                                            (0x332Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3461                                            (0x3371u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3462                                            (0x5F03u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3463                                            (0x4A7Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3464                                            (0x0CEBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3465                                            (0x4CF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3466                                            (0x788Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3467                                            (0x44AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3468                                            (0x03DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3469                                            (0x5D19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3470                                            (0x3939u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3471                                            (0x551Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3472                                            (0x41DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3473                                            (0x493Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3474                                            (0x7839u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3475                                            (0x5F88u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3476                                            (0x56ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3477                                            (0x2F4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3478                                            (0x3A5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3479                                            (0x649Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3480                                            (0x6B49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3481                                            (0x5A96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3482                                            (0x1D1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3483                                            (0x3CB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3484                                            (0x4AC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3485                                            (0x46F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3486                                            (0x4F70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3487                                            (0x30F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3488                                            (0x11DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3489                                            (0x692Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3490                                            (0x147Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3491                                            (0x2E6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3492                                            (0x3CC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3493                                            (0x56B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3494                                            (0x34AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3495                                            (0x4DD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3496                                            (0x33F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3497                                            (0x3E23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3498                                            (0x3F42u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3499                                            (0x6791u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3500                                            (0x2DE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3501                                            (0x663Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3502                                            (0x54ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3503                                            (0x3CACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3504                                            (0x3716u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3505                                            (0x2E1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3506                                            (0x7C45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3507                                            (0x707Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3508                                            (0x71A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3509                                            (0x57A8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3510                                            (0x073Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3511                                            (0x705Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3512                                            (0x6D0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3513                                            (0x65E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3514                                            (0x74D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3515                                            (0x6D07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3516                                            (0x661Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3517                                            (0x74B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3518                                            (0x0EB6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3519                                            (0x16F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3520                                            (0x5E58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3521                                            (0x3732u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3522                                            (0x5A35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3523                                            (0x2477u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3524                                            (0x30CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3525                                            (0x3EC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3526                                            (0x0DF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3527                                            (0x71D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3528                                            (0x178Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3529                                            (0x22B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3530                                            (0x35D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3531                                            (0x37A1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3532                                            (0x5707u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3533                                            (0x702Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3534                                            (0x6B45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3535                                            (0x4B6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3536                                            (0x17C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3537                                            (0x2B96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3538                                            (0x6743u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3539                                            (0x6D98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3540                                            (0x7C83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3541                                            (0x71D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3542                                            (0x15DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3543                                            (0x3633u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3544                                            (0x64BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3545                                            (0x55A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3546                                            (0x1B0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3547                                            (0x4E95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3548                                            (0x368Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3549                                            (0x5355u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3550                                            (0x5C95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3551                                            (0x0ED5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3552                                            (0x472Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3553                                            (0x6D4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3554                                            (0x6653u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3555                                            (0x32B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3556                                            (0x467Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3557                                            (0x2F26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3558                                            (0x3A9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3559                                            (0x470Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3560                                            (0x554Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3561                                            (0x6D0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3562                                            (0x0BEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3563                                            (0x64AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3564                                            (0x4ACBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3565                                            (0x1676u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3566                                            (0x6993u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3567                                            (0x2CF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3568                                            (0x170Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3569                                            (0x72CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3570                                            (0x595Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3571                                            (0x4B17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3572                                            (0x2BAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3573                                            (0x2D5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3574                                            (0x785Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3575                                            (0x13DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3576                                            (0x3D0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3577                                            (0x6CC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3578                                            (0x66AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3579                                            (0x4CECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3580                                            (0x16D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3581                                            (0x6467u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3582                                            (0x15CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3583                                            (0x5A65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3584                                            (0x43AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3585                                            (0x3798u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3586                                            (0x60F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3587                                            (0x455Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3588                                            (0x4F38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3589                                            (0x64A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3590                                            (0x7616u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3591                                            (0x2F89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3592                                            (0x4E4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3593                                            (0x15F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3594                                            (0x36C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3595                                            (0x6355u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3596                                            (0x544Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3597                                            (0x7D22u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3598                                            (0x39A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3599                                            (0x5A8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3600                                            (0x2D87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3601                                            (0x465Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3602                                            (0x761Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3603                                            (0x65F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3604                                            (0x093Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3605                                            (0x50DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3606                                            (0x2F29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3607                                            (0x05BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3608                                            (0x7722u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3609                                            (0x709Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3610                                            (0x4E59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3611                                            (0x2B8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3612                                            (0x1F15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3613                                            (0x5DB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3614                                            (0x6770u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3615                                            (0x2F92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3616                                            (0x44BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3617                                            (0x6B31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3618                                            (0x1967u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3619                                            (0x626Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3620                                            (0x3E49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3621                                            (0x62DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3622                                            (0x76B0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3623                                            (0x40BFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3624                                            (0x625Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3625                                            (0x63E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3626                                            (0x6FA0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3627                                            (0x1973u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3628                                            (0x6875u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3629                                            (0x56C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3630                                            (0x3DA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3631                                            (0x51E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3632                                            (0x5AC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3633                                            (0x4373u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3634                                            (0x12DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3635                                            (0x721Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3636                                            (0x067Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3637                                            (0x166Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3638                                            (0x41F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3639                                            (0x247Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3640                                            (0x0AB7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3641                                            (0x4E6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3642                                            (0x2573u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3643                                            (0x3393u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3644                                            (0x07AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3645                                            (0x6595u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3646                                            (0x5565u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3647                                            (0x1EE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3648                                            (0x3DC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3649                                            (0x74A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3650                                            (0x3CB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3651                                            (0x6978u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3652                                            (0x07CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3653                                            (0x47B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3654                                            (0x3D61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3655                                            (0x1F0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3656                                            (0x626Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3657                                            (0x54A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3658                                            (0x685Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3659                                            (0x572Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3660                                            (0x358Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3661                                            (0x4BD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3662                                            (0x31D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3663                                            (0x56E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3664                                            (0x6EC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3665                                            (0x38F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3666                                            (0x7C34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3667                                            (0x664Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3668                                            (0x1CABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3669                                            (0x6565u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3670                                            (0x0A7Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3671                                            (0x7199u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3672                                            (0x19B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3673                                            (0x48EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3674                                            (0x07DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3675                                            (0x08F7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3676                                            (0x6B98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3677                                            (0x329Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3678                                            (0x74D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3679                                            (0x71E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3680                                            (0x0F65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3681                                            (0x5E83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3682                                            (0x2D35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3683                                            (0x3336u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3684                                            (0x38DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3685                                            (0x58DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3686                                            (0x7B0Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3687                                            (0x4CB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3688                                            (0x61B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3689                                            (0x4E2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3690                                            (0x26BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3691                                            (0x55B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3692                                            (0x3867u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3693                                            (0x47CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3694                                            (0x7C0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3695                                            (0x61ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3696                                            (0x163Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3697                                            (0x0D5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3698                                            (0x16E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3699                                            (0x10DFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3700                                            (0x5F90u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3701                                            (0x58CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3702                                            (0x35C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3703                                            (0x072Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3704                                            (0x687Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3705                                            (0x1CB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3706                                            (0x4E66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3707                                            (0x19F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3708                                            (0x4AB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3709                                            (0x55C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3710                                            (0x589Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3711                                            (0x5363u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3712                                            (0x4D3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3713                                            (0x169Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3714                                            (0x197Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3715                                            (0x6C39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3716                                            (0x6F11u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3717                                            (0x1BD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3718                                            (0x2B0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3719                                            (0x1F92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3720                                            (0x44DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3721                                            (0x7692u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3722                                            (0x7E48u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3723                                            (0x4B63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3724                                            (0x52F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3725                                            (0x6D68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3726                                            (0x2FE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3727                                            (0x2657u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3728                                            (0x5A6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3729                                            (0x71C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3730                                            (0x4B1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3731                                            (0x27A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3732                                            (0x6AE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3733                                            (0x51ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3734                                            (0x21DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3735                                            (0x1E9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3736                                            (0x7417u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3737                                            (0x35A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3738                                            (0x2ACEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3739                                            (0x3F05u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3740                                            (0x6C47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3741                                            (0x2E2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3742                                            (0x12DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3743                                            (0x1765u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3744                                            (0x2B99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3745                                            (0x24F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3746                                            (0x1AF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3747                                            (0x4A9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3748                                            (0x0F4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3749                                            (0x562Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3750                                            (0x7E05u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3751                                            (0x6713u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3752                                            (0x1B17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3753                                            (0x32B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3754                                            (0x6695u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3755                                            (0x59CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3756                                            (0x7127u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3757                                            (0x0CFAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3758                                            (0x7513u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3759                                            (0x71E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3760                                            (0x78ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3761                                            (0x5475u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3762                                            (0x59C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3763                                            (0x585Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3764                                            (0x32BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3765                                            (0x75C2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3766                                            (0x167Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3767                                            (0x5E32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3768                                            (0x5993u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3769                                            (0x233Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3770                                            (0x4BACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3771                                            (0x3C63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3772                                            (0x4877u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3773                                            (0x3B23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3774                                            (0x1A8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3775                                            (0x213Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3776                                            (0x7589u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3777                                            (0x5B32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3778                                            (0x1BC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3779                                            (0x6AC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3780                                            (0x438Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3781                                            (0x61E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3782                                            (0x70EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3783                                            (0x30EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3784                                            (0x5AD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3785                                            (0x0ECEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3786                                            (0x5FC0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3787                                            (0x273Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3788                                            (0x1E27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3789                                            (0x5CACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3790                                            (0x3ED0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3791                                            (0x6C72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3792                                            (0x7F04u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3793                                            (0x70BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3794                                            (0x19F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3795                                            (0x6D31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3796                                            (0x7156u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3797                                            (0x7712u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3798                                            (0x12B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3799                                            (0x598Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3800                                            (0x689Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3801                                            (0x5DA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3802                                            (0x5556u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3803                                            (0x172Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3804                                            (0x7352u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3805                                            (0x71B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3806                                            (0x26E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3807                                            (0x17A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3808                                            (0x0CBBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3809                                            (0x669Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3810                                            (0x5F50u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3811                                            (0x687Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3812                                            (0x2A73u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3813                                            (0x3C53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3814                                            (0x360Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3815                                            (0x594Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3816                                            (0x7392u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3817                                            (0x4B8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3818                                            (0x38CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3819                                            (0x7835u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3820                                            (0x33C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3821                                            (0x598Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3822                                            (0x2D69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3823                                            (0x2DD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3824                                            (0x7E21u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3825                                            (0x71B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3826                                            (0x4739u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3827                                            (0x3C39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3828                                            (0x5593u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3829                                            (0x42F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3830                                            (0x4E3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3831                                            (0x0F39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3832                                            (0x7742u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3833                                            (0x3E98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3834                                            (0x0F3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3835                                            (0x384Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3836                                            (0x5D29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3837                                            (0x4CE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3838                                            (0x6C8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3839                                            (0x6387u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3840                                            (0x674Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3841                                            (0x586Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3842                                            (0x693Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3843                                            (0x63C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3844                                            (0x54ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3845                                            (0x1AABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3846                                            (0x333Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3847                                            (0x7BA0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3848                                            (0x41BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3849                                            (0x4B35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3850                                            (0x09F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3851                                            (0x50AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3852                                            (0x329Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3853                                            (0x2A7Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3854                                            (0x7E0Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3855                                            (0x05DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3856                                            (0x59F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3857                                            (0x72ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3858                                            (0x3B85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3859                                            (0x2B5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3860                                            (0x4FD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3861                                            (0x249Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3862                                            (0x13E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3863                                            (0x68E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3864                                            (0x62E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3865                                            (0x2774u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3866                                            (0x28FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3867                                            (0x5D51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3868                                            (0x60DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3869                                            (0x1DA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3870                                            (0x6553u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3871                                            (0x5A59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3872                                            (0x71D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3873                                            (0x6ACCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3874                                            (0x40FDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3875                                            (0x59E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3876                                            (0x50CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3877                                            (0x770Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3878                                            (0x4F61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3879                                            (0x4B69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3880                                            (0x534Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3881                                            (0x0EF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3882                                            (0x45CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3883                                            (0x2733u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3884                                            (0x5157u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3885                                            (0x29C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3886                                            (0x09B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3887                                            (0x6B68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3888                                            (0x45E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3889                                            (0x2DC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3890                                            (0x6A6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3891                                            (0x23D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3892                                            (0x4177u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3893                                            (0x54AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3894                                            (0x56D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3895                                            (0x73A2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3896                                            (0x27CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3897                                            (0x5B91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3898                                            (0x2F1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3899                                            (0x3F12u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3900                                            (0x0E5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3901                                            (0x271Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3902                                            (0x671Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3903                                            (0x4BE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3904                                            (0x4976u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3905                                            (0x5A1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3906                                            (0x3F30u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3907                                            (0x725Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3908                                            (0x12D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3909                                            (0x29E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3910                                            (0x3749u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3911                                            (0x49D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3912                                            (0x466Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3913                                            (0x254Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3914                                            (0x2A1Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3915                                            (0x3786u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3916                                            (0x7A62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3917                                            (0x79A1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3918                                            (0x7A1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3919                                            (0x7D12u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3920                                            (0x3E61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3921                                            (0x4F2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3922                                            (0x2E63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3923                                            (0x3C87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3924                                            (0x09CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3925                                            (0x68C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3926                                            (0x5715u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3927                                            (0x67A1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3928                                            (0x2EACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3929                                            (0x79C1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3930                                            (0x3267u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3931                                            (0x4B36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3932                                            (0x5571u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3933                                            (0x16B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3934                                            (0x077Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3935                                            (0x14FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3936                                            (0x1D1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3937                                            (0x5179u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3938                                            (0x5AAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3939                                            (0x4B99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3940                                            (0x1ABCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3941                                            (0x0E5Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3942                                            (0x64D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3943                                            (0x28B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3944                                            (0x5C8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3945                                            (0x4F0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3946                                            (0x7266u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3947                                            (0x5527u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3948                                            (0x1E65u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3949                                            (0x626Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3950                                            (0x1CCDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3951                                            (0x51BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3952                                            (0x11DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3953                                            (0x6176u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3954                                            (0x35A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3955                                            (0x5DD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3956                                            (0x2747u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3957                                            (0x7583u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3958                                            (0x3746u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3959                                            (0x2575u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3960                                            (0x33E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3961                                            (0x1E36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3962                                            (0x2F8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3963                                            (0x3CE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3964                                            (0x22EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3965                                            (0x2E35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3966                                            (0x4AABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3967                                            (0x4D2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3968                                            (0x07BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3969                                            (0x758Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3970                                            (0x631Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3971                                            (0x3599u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3972                                            (0x7551u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3973                                            (0x6768u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3974                                            (0x4BB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3975                                            (0x7B09u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3976                                            (0x74ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3977                                            (0x26B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3978                                            (0x72B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3979                                            (0x7B81u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3980                                            (0x56B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3981                                            (0x2E56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3982                                            (0x474Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3983                                            (0x445Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3984                                            (0x43DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3985                                            (0x7519u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3986                                            (0x1D63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3987                                            (0x2BE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3988                                            (0x265Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3989                                            (0x4CF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3990                                            (0x5D07u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3991                                            (0x0FC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3992                                            (0x5999u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3993                                            (0x27F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3994                                            (0x6C69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3995                                            (0x1A37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3996                                            (0x627Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3997                                            (0x6687u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3998                                            (0x24BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3999                                            (0x5D38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4000                                            (0x0FACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4001                                            (0x3754u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4002                                            (0x7351u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4003                                            (0x0BD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4004                                            (0x7919u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4005                                            (0x28BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4006                                            (0x3B15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4007                                            (0x34B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4008                                            (0x3B62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4009                                            (0x2EA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4010                                            (0x7694u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4011                                            (0x54E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4012                                            (0x6D61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4013                                            (0x5399u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4014                                            (0x718Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4015                                            (0x3B64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4016                                            (0x6333u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4017                                            (0x1D47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4018                                            (0x31D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4019                                            (0x5539u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4020                                            (0x68ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4021                                            (0x4E5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4022                                            (0x3BC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4023                                            (0x0EC7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4024                                            (0x74E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4025                                            (0x193Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4026                                            (0x7332u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4027                                            (0x287Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4028                                            (0x13D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4029                                            (0x43D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4030                                            (0x38EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4031                                            (0x3F22u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4032                                            (0x6EC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4033                                            (0x45A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4034                                            (0x7B18u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4035                                            (0x5E31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4036                                            (0x73C1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4037                                            (0x74E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4038                                            (0x6C9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4039                                            (0x6ED0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4040                                            (0x1CAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4041                                            (0x389Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4042                                            (0x5751u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4043                                            (0x36C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4044                                            (0x45C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4045                                            (0x36A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4046                                            (0x1575u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4047                                            (0x7836u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4048                                            (0x42F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4049                                            (0x3A6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4050                                            (0x3347u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4051                                            (0x2B4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4052                                            (0x27C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4053                                            (0x15EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4054                                            (0x48F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4055                                            (0x6A95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4056                                            (0x3B1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4057                                            (0x4B6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4058                                            (0x29A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4059                                            (0x0EE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4060                                            (0x4B56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4061                                            (0x5E15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4062                                            (0x22EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4063                                            (0x43C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4064                                            (0x1F1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4065                                            (0x71E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4066                                            (0x28EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4067                                            (0x36E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4068                                            (0x247Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4069                                            (0x4F26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4070                                            (0x7D82u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4071                                            (0x6674u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4072                                            (0x04FBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4073                                            (0x531Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4074                                            (0x5761u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4075                                            (0x49D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4076                                            (0x7B50u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4077                                            (0x5732u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4078                                            (0x2675u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4079                                            (0x7478u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4080                                            (0x3CA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4081                                            (0x4B5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4082                                            (0x4C57u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4083                                            (0x6BE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4084                                            (0x2C79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4085                                            (0x1B66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4086                                            (0x74B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4087                                            (0x6E23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4088                                            (0x6C2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4089                                            (0x03D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4090                                            (0x5A33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4091                                            (0x3EC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4092                                            (0x55D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4093                                            (0x719Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4094                                            (0x639Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4095                                            (0x7349u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4096                                            (0x4B27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4097                                            (0x1CD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4098                                            (0x584Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4099                                            (0x33D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4100                                            (0x2FC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4101                                            (0x545Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4102                                            (0x7CA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4103                                            (0x3D2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4104                                            (0x1CEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4105                                            (0x4DA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4106                                            (0x65CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4107                                            (0x4ECCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4108                                            (0x4B95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4109                                            (0x7817u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4110                                            (0x6D83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4111                                            (0x6A1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4112                                            (0x29B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4113                                            (0x6DB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4114                                            (0x135Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4115                                            (0x3791u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4116                                            (0x16ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4117                                            (0x1DD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4118                                            (0x5792u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4119                                            (0x4F91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4120                                            (0x4FC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4121                                            (0x471Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4122                                            (0x1763u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4123                                            (0x6C78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4124                                            (0x6B94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4125                                            (0x133Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4126                                            (0x581Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4127                                            (0x5F60u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4128                                            (0x7E42u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4129                                            (0x6F84u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4130                                            (0x1BA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4131                                            (0x62BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4132                                            (0x26D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4133                                            (0x751Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4134                                            (0x34ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4135                                            (0x0776u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4136                                            (0x2B95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4137                                            (0x7855u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4138                                            (0x60D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4139                                            (0x13E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4140                                            (0x5971u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4141                                            (0x45E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4142                                            (0x447Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4143                                            (0x4A57u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4144                                            (0x23ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4145                                            (0x3B68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4146                                            (0x3595u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4147                                            (0x06AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4148                                            (0x65C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4149                                            (0x31ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4150                                            (0x1F46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4151                                            (0x750Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4152                                            (0x323Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4153                                            (0x62ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4154                                            (0x6378u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4155                                            (0x5F21u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4156                                            (0x24EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4157                                            (0x26B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4158                                            (0x2CDCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4159                                            (0x7A34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4160                                            (0x355Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4161                                            (0x1ADAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4162                                            (0x5666u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4163                                            (0x5CE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4164                                            (0x21DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4165                                            (0x3D98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4166                                            (0x19D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4167                                            (0x64E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4168                                            (0x6A53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4169                                            (0x145Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4170                                            (0x23A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4171                                            (0x3725u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4172                                            (0x782Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4173                                            (0x6539u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4174                                            (0x2B72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4175                                            (0x54F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4176                                            (0x462Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4177                                            (0x63A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4178                                            (0x6617u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4179                                            (0x16E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4180                                            (0x6B23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4181                                            (0x3933u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4182                                            (0x52B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4183                                            (0x3A3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4184                                            (0x5B4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4185                                            (0x636Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4186                                            (0x706Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4187                                            (0x0F1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4188                                            (0x0EB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4189                                            (0x46B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4190                                            (0x5837u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4191                                            (0x0AE7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4192                                            (0x7689u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4193                                            (0x3993u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4194                                            (0x68B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4195                                            (0x4A4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4196                                            (0x3789u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4197                                            (0x2E55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4198                                            (0x5678u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4199                                            (0x7532u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4200                                            (0x4F85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4201                                            (0x6BA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4202                                            (0x61F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4203                                            (0x0ADEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4204                                            (0x678Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4205                                            (0x2F25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4206                                            (0x13F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4207                                            (0x4D78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4208                                            (0x67C1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4209                                            (0x1AD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4210                                            (0x647Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4211                                            (0x3B52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4212                                            (0x43B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4213                                            (0x4D36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4214                                            (0x611Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4215                                            (0x6D34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4216                                            (0x7296u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4217                                            (0x1A5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4218                                            (0x7C51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4219                                            (0x3F82u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4220                                            (0x0DF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4221                                            (0x760Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4222                                            (0x07D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4223                                            (0x1F85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4224                                            (0x568Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4225                                            (0x6197u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4226                                            (0x499Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4227                                            (0x6B51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4228                                            (0x2637u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4229                                            (0x12FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4230                                            (0x49AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4231                                            (0x1D0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4232                                            (0x3AA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4233                                            (0x0FC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4234                                            (0x2D93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4235                                            (0x5E13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4236                                            (0x331Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4237                                            (0x73A1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4238                                            (0x3E2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4239                                            (0x5A53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4240                                            (0x6746u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4241                                            (0x371Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4242                                            (0x70D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4243                                            (0x51F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4244                                            (0x4774u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4245                                            (0x4C9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4246                                            (0x3665u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4247                                            (0x531Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4248                                            (0x473Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4249                                            (0x1C6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4250                                            (0x16A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4251                                            (0x44DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4252                                            (0x1E6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4253                                            (0x3175u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4254                                            (0x5743u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4255                                            (0x6B1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4256                                            (0x55C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4257                                            (0x2A3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4258                                            (0x5729u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4259                                            (0x336Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4260                                            (0x4E87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4261                                            (0x4CBAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4262                                            (0x1D66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4263                                            (0x33A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4264                                            (0x17B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4265                                            (0x6B91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4266                                            (0x43EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4267                                            (0x61F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4268                                            (0x0ABDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4269                                            (0x5647u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4270                                            (0x4B78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4271                                            (0x02FBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4272                                            (0x53C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4273                                            (0x68D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4274                                            (0x742Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4275                                            (0x7AC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4276                                            (0x3768u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4277                                            (0x1E8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4278                                            (0x7263u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4279                                            (0x0B1Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4280                                            (0x2D9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4281                                            (0x7CA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4282                                            (0x46B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4283                                            (0x526Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4284                                            (0x7869u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4285                                            (0x7E0Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4286                                            (0x268Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4287                                            (0x57A2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4288                                            (0x6276u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4289                                            (0x0DD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4290                                            (0x16C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4291                                            (0x35C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4292                                            (0x7433u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4293                                            (0x2B3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4294                                            (0x5963u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4295                                            (0x30AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4296                                            (0x0F93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4297                                            (0x1E35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4298                                            (0x5237u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4299                                            (0x6297u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4300                                            (0x34F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4301                                            (0x399Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4302                                            (0x6374u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4303                                            (0x2EC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4304                                            (0x3E31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4305                                            (0x27C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4306                                            (0x565Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4307                                            (0x27A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4308                                            (0x475Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4309                                            (0x738Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4310                                            (0x53B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4311                                            (0x7057u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4312                                            (0x66ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4313                                            (0x7D18u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4314                                            (0x38F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4315                                            (0x3CC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4316                                            (0x6754u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4317                                            (0x26CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4318                                            (0x7C1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4319                                            (0x42CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4320                                            (0x562Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4321                                            (0x6A93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4322                                            (0x54E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4323                                            (0x2B8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4324                                            (0x6D92u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4325                                            (0x5B94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4326                                            (0x7703u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4327                                            (0x552Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4328                                            (0x6A9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4329                                            (0x5B46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4330                                            (0x1A3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4331                                            (0x53E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4332                                            (0x136Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4333                                            (0x7645u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4334                                            (0x0BAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4335                                            (0x72B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4336                                            (0x3355u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4337                                            (0x7155u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4338                                            (0x64BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4339                                            (0x683Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4340                                            (0x7B12u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4341                                            (0x526Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4342                                            (0x3E1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4343                                            (0x2717u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4344                                            (0x2F13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4345                                            (0x05F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4346                                            (0x656Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4347                                            (0x624Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4348                                            (0x1FA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4349                                            (0x507Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4350                                            (0x3C1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4351                                            (0x742Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4352                                            (0x1DC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4353                                            (0x6E94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4354                                            (0x53E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4355                                            (0x1F52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4356                                            (0x073Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4357                                            (0x4F4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4358                                            (0x7C25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4359                                            (0x38AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4360                                            (0x13B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4361                                            (0x0EB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4362                                            (0x3C5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4363                                            (0x127Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4364                                            (0x6555u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4365                                            (0x158Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4366                                            (0x3D19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4367                                            (0x1997u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4368                                            (0x2D8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4369                                            (0x0C7Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4370                                            (0x3BC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4371                                            (0x7386u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4372                                            (0x7A4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4373                                            (0x5AD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4374                                            (0x0BCDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4375                                            (0x2F98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4376                                            (0x06B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4377                                            (0x7368u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4378                                            (0x1D33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4379                                            (0x33D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4380                                            (0x363Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4381                                            (0x3AB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4382                                            (0x7507u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4383                                            (0x7721u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4384                                            (0x2E27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4385                                            (0x4C3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4386                                            (0x5DC2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4387                                            (0x5B13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4388                                            (0x69B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4389                                            (0x3A1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4390                                            (0x452Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4391                                            (0x2A6Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4392                                            (0x5371u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4393                                            (0x4D87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4394                                            (0x7C15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4395                                            (0x6E4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4396                                            (0x58CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4397                                            (0x276Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4398                                            (0x70D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4399                                            (0x68BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4400                                            (0x4769u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4401                                            (0x2AEAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4402                                            (0x527Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4403                                            (0x2E6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4404                                            (0x781Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4405                                            (0x5AA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4406                                            (0x2D3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4407                                            (0x764Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4408                                            (0x592Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4409                                            (0x7C61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4410                                            (0x2B9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4411                                            (0x463Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4412                                            (0x3726u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4413                                            (0x62CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4414                                            (0x665Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4415                                            (0x4F13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4416                                            (0x20EFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4417                                            (0x1979u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4418                                            (0x0FD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4419                                            (0x29CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4420                                            (0x1B27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4421                                            (0x666Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4422                                            (0x70F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4423                                            (0x6C6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4424                                            (0x193Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4425                                            (0x3A36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4426                                            (0x43F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4427                                            (0x37E0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4428                                            (0x06EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4429                                            (0x1C8Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4430                                            (0x74F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4431                                            (0x4765u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4432                                            (0x6E43u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4433                                            (0x29E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4434                                            (0x5D32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4435                                            (0x1ACDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4436                                            (0x0CAFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4437                                            (0x2772u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4438                                            (0x5E89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4439                                            (0x6C53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4440                                            (0x1E78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4441                                            (0x5B49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4442                                            (0x552Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4443                                            (0x0CDBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4444                                            (0x2AE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4445                                            (0x654Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4446                                            (0x0F2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4447                                            (0x6B13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4448                                            (0x299Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4449                                            (0x65E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4450                                            (0x4FE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4451                                            (0x0D3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4452                                            (0x44BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4453                                            (0x287Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4454                                            (0x75A8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4455                                            (0x639Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4456                                            (0x1E1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4457                                            (0x1B1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4458                                            (0x3533u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4459                                            (0x1E17u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4460                                            (0x465Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4461                                            (0x2EE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4462                                            (0x335Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4463                                            (0x54DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4464                                            (0x497Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4465                                            (0x4597u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4466                                            (0x6CC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4467                                            (0x34C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4468                                            (0x538Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4469                                            (0x3476u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4470                                            (0x5D8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4471                                            (0x15B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4472                                            (0x2DF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4473                                            (0x3AC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4474                                            (0x274Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4475                                            (0x5B0Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4476                                            (0x43E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4477                                            (0x3AD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4478                                            (0x6897u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4479                                            (0x37A4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4480                                            (0x69AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4481                                            (0x6DA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4482                                            (0x5AE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4483                                            (0x1E9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4484                                            (0x1E93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4485                                            (0x6D2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4486                                            (0x5CB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4487                                            (0x4DACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4488                                            (0x0DB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4489                                            (0x17CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4490                                            (0x7C46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4491                                            (0x194Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4492                                            (0x0F71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4493                                            (0x4799u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4494                                            (0x6559u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4495                                            (0x4E1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4496                                            (0x23E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4497                                            (0x28DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4498                                            (0x7C19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4499                                            (0x6AE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4500                                            (0x6959u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4501                                            (0x6556u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4502                                            (0x52E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4503                                            (0x43D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4504                                            (0x7866u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4505                                            (0x2769u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4506                                            (0x30DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4507                                            (0x1FC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4508                                            (0x45E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4509                                            (0x6792u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4510                                            (0x5F11u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4511                                            (0x073Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4512                                            (0x309Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4513                                            (0x24FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4514                                            (0x4637u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4515                                            (0x29EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4516                                            (0x22BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4517                                            (0x2B39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4518                                            (0x469Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4519                                            (0x3B51u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4520                                            (0x1AD5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4521                                            (0x58ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4522                                            (0x649Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4523                                            (0x31BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4524                                            (0x25B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4525                                            (0x2D1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4526                                            (0x7174u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4527                                            (0x4E78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4528                                            (0x0F33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4529                                            (0x5693u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4530                                            (0x27D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4531                                            (0x6BC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4532                                            (0x5936u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4533                                            (0x09F5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4534                                            (0x64B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4535                                            (0x29E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4536                                            (0x3EE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4537                                            (0x5CCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4538                                            (0x0BECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4539                                            (0x7153u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4540                                            (0x4B4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4541                                            (0x6C4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4542                                            (0x165Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4543                                            (0x3758u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4544                                            (0x2BA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4545                                            (0x3CA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4546                                            (0x1E2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4547                                            (0x49F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4548                                            (0x262Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4549                                            (0x44B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4550                                            (0x33CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4551                                            (0x13BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4552                                            (0x172Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4553                                            (0x4ADCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4554                                            (0x7646u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4555                                            (0x09EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4556                                            (0x326Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4557                                            (0x0DABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4558                                            (0x7CA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4559                                            (0x4EF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4560                                            (0x51E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4561                                            (0x5CE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4562                                            (0x6571u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4563                                            (0x2EF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4564                                            (0x74A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4565                                            (0x1F61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4566                                            (0x25AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4567                                            (0x5E52u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4568                                            (0x461Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4569                                            (0x61E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4570                                            (0x605Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4571                                            (0x3E15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4572                                            (0x571Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4573                                            (0x27A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4574                                            (0x2EA5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4575                                            (0x283Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4576                                            (0x392Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4577                                            (0x49E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4578                                            (0x5B8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4579                                            (0x3C8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4580                                            (0x383Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4581                                            (0x6E98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4582                                            (0x47C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4583                                            (0x45ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4584                                            (0x678Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4585                                            (0x18B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4586                                            (0x1376u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4587                                            (0x1337u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4588                                            (0x62B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4589                                            (0x39D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4590                                            (0x037Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4591                                            (0x296Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4592                                            (0x31D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4593                                            (0x3936u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4594                                            (0x076Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4595                                            (0x3D86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4596                                            (0x29CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4597                                            (0x78E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4598                                            (0x5366u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4599                                            (0x49EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4600                                            (0x760Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4601                                            (0x2B8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4602                                            (0x4CD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4603                                            (0x7B88u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4604                                            (0x4DC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4605                                            (0x3956u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4606                                            (0x51A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4607                                            (0x293Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4608                                            (0x267Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4609                                            (0x0E37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4610                                            (0x2E39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4611                                            (0x7B48u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4612                                            (0x7178u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4613                                            (0x6C5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4614                                            (0x51EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4615                                            (0x7970u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4616                                            (0x2A3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4617                                            (0x2C5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4618                                            (0x6729u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4619                                            (0x3707u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4620                                            (0x4DCAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4621                                            (0x2957u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4622                                            (0x266Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4623                                            (0x4ABCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4624                                            (0x4967u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4625                                            (0x199Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4626                                            (0x5725u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4627                                            (0x0F99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4628                                            (0x42E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4629                                            (0x5365u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4630                                            (0x2376u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4631                                            (0x275Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4632                                            (0x3C47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4633                                            (0x22E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4634                                            (0x4F86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4635                                            (0x0FE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4636                                            (0x5D25u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4637                                            (0x6D46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4638                                            (0x555Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4639                                            (0x18EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4640                                            (0x5D4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4641                                            (0x487Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4642                                            (0x71ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4643                                            (0x354Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4644                                            (0x4F0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4645                                            (0x0DF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4646                                            (0x3C74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4647                                            (0x0AF5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4648                                            (0x32CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4649                                            (0x298Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4650                                            (0x42DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4651                                            (0x186Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4652                                            (0x3C2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4653                                            (0x72A5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4654                                            (0x1B4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4655                                            (0x1E4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4656                                            (0x7863u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4657                                            (0x7C2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4658                                            (0x646Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4659                                            (0x4B5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4660                                            (0x583Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4661                                            (0x3387u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4662                                            (0x1BA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4663                                            (0x53C6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4664                                            (0x2FA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4665                                            (0x16BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4666                                            (0x7893u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4667                                            (0x31E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4668                                            (0x3276u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4669                                            (0x45D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4670                                            (0x25B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4671                                            (0x468Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4672                                            (0x1E96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4673                                            (0x079Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4674                                            (0x45EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4675                                            (0x361Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4676                                            (0x54BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4677                                            (0x3566u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4678                                            (0x0AF3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4679                                            (0x7CC8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4680                                            (0x5B61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4681                                            (0x6A8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4682                                            (0x398Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4683                                            (0x789Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4684                                            (0x50BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4685                                            (0x1EA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4686                                            (0x3715u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4687                                            (0x5783u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4688                                            (0x750Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4689                                            (0x75A2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4690                                            (0x059Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4691                                            (0x1EAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4692                                            (0x0CEEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4693                                            (0x6719u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4694                                            (0x3E32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4695                                            (0x2B69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4696                                            (0x156Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4697                                            (0x57C8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4698                                            (0x60BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4699                                            (0x5C1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4700                                            (0x5C39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4701                                            (0x19CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4702                                            (0x7D90u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4703                                            (0x315Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4704                                            (0x272Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4705                                            (0x66B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4706                                            (0x6E1Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4707                                            (0x6C6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4708                                            (0x4A3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4709                                            (0x23B6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4710                                            (0x560Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4711                                            (0x6FC0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4712                                            (0x3C4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4713                                            (0x1AD9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4714                                            (0x5DA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4715                                            (0x5E38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4716                                            (0x26E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4717                                            (0x517Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4718                                            (0x2C3Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4719                                            (0x3273u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4720                                            (0x6953u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4721                                            (0x50EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4722                                            (0x5275u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4723                                            (0x3AD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4724                                            (0x592Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4725                                            (0x51AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4726                                            (0x6A59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4727                                            (0x5699u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4728                                            (0x31F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4729                                            (0x3C8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4730                                            (0x7487u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4731                                            (0x427Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4732                                            (0x1F86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4733                                            (0x5E49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4734                                            (0x5F05u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4735                                            (0x1D56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4736                                            (0x1CF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4737                                            (0x3752u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4738                                            (0x35B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4739                                            (0x670Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4740                                            (0x64D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4741                                            (0x2F4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4742                                            (0x5D34u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4743                                            (0x0DB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4744                                            (0x6F90u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4745                                            (0x306Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4746                                            (0x466Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4747                                            (0x6C9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4748                                            (0x1367u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4749                                            (0x69ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4750                                            (0x513Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4751                                            (0x3D62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4752                                            (0x313Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4753                                            (0x2D8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4754                                            (0x3B98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4755                                            (0x53E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4756                                            (0x3569u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4757                                            (0x6353u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4758                                            (0x1F31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4759                                            (0x1D6Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4760                                            (0x5687u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4761                                            (0x7515u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4762                                            (0x5BD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4763                                            (0x1772u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4764                                            (0x43E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4765                                            (0x36E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4766                                            (0x5B0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4767                                            (0x72E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4768                                            (0x349Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4769                                            (0x06BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4770                                            (0x5669u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4771                                            (0x5B8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4772                                            (0x498Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4773                                            (0x3535u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4774                                            (0x1D2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4775                                            (0x6B85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4776                                            (0x703Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4777                                            (0x7269u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4778                                            (0x50D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4779                                            (0x68CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4780                                            (0x69E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4781                                            (0x72E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4782                                            (0x752Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4783                                            (0x5749u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4784                                            (0x364Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4785                                            (0x1B9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4786                                            (0x5B86u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4787                                            (0x7C0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4788                                            (0x3F21u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4789                                            (0x694Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4790                                            (0x5C2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4791                                            (0x6A3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4792                                            (0x2E2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4793                                            (0x38B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4794                                            (0x4ABAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4795                                            (0x52ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4796                                            (0x53D2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4797                                            (0x47ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4798                                            (0x187Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4799                                            (0x449Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4800                                            (0x25E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4801                                            (0x7354u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4802                                            (0x60B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4803                                            (0x1CDAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4804                                            (0x5395u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4805                                            (0x257Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4806                                            (0x471Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4807                                            (0x62E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4808                                            (0x331Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4809                                            (0x46C7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4810                                            (0x7D88u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4811                                            (0x3AC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4812                                            (0x2367u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4813                                            (0x7598u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4814                                            (0x47B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4815                                            (0x7613u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4816                                            (0x58F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4817                                            (0x6C63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4818                                            (0x6A4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4819                                            (0x6F24u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4820                                            (0x5987u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4821                                            (0x234Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4822                                            (0x42DBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4823                                            (0x638Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4824                                            (0x4A37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4825                                            (0x2FC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4826                                            (0x7A49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4827                                            (0x417Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4828                                            (0x7C89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4829                                            (0x68ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4830                                            (0x51D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4831                                            (0x253Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4832                                            (0x6B83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4833                                            (0x1BB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4834                                            (0x1778u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4835                                            (0x3237u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4836                                            (0x74E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4837                                            (0x63C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4838                                            (0x1C6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4839                                            (0x31AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4840                                            (0x1ADCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4841                                            (0x5636u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4842                                            (0x2AF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4843                                            (0x64CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4844                                            (0x55ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4845                                            (0x1B72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4846                                            (0x6AD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4847                                            (0x40FBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4848                                            (0x52CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4849                                            (0x343Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4850                                            (0x6935u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4851                                            (0x6578u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4852                                            (0x7466u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4853                                            (0x6BA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4854                                            (0x5AE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4855                                            (0x5596u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4856                                            (0x7529u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4857                                            (0x566Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4858                                            (0x4B9Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4859                                            (0x6A1Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4860                                            (0x174Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4861                                            (0x0AFCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4862                                            (0x1A7Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4863                                            (0x394Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4864                                            (0x7A29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4865                                            (0x2E69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4866                                            (0x7C38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4867                                            (0x3BA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4868                                            (0x32ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4869                                            (0x5E64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4870                                            (0x179Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4871                                            (0x26DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4872                                            (0x32E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4873                                            (0x315Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4874                                            (0x7730u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4875                                            (0x2793u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4876                                            (0x24D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4877                                            (0x5F06u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4878                                            (0x3D2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4879                                            (0x5B45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4880                                            (0x4FA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4881                                            (0x3173u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4882                                            (0x628Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4883                                            (0x4BA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4884                                            (0x6AA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4885                                            (0x4D4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4886                                            (0x5752u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4887                                            (0x62F8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4888                                            (0x50EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4889                                            (0x63A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4890                                            (0x6566u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4891                                            (0x55B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4892                                            (0x62E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4893                                            (0x666Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4894                                            (0x5359u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4895                                            (0x5B15u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4896                                            (0x5B98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4897                                            (0x35C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4898                                            (0x1A75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4899                                            (0x28D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4900                                            (0x4397u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4901                                            (0x3D32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4902                                            (0x426Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4903                                            (0x5374u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4904                                            (0x13D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4905                                            (0x749Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4906                                            (0x196Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4907                                            (0x2753u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4908                                            (0x64ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4909                                            (0x6A2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4910                                            (0x6336u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4911                                            (0x39E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4912                                            (0x1EA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4913                                            (0x7A70u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4914                                            (0x2177u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4915                                            (0x5559u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4916                                            (0x223Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4917                                            (0x5FA0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4918                                            (0x4697u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4919                                            (0x1DE8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4920                                            (0x50F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4921                                            (0x2ED2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4922                                            (0x3C71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4923                                            (0x3317u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4924                                            (0x0E75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4925                                            (0x2DA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4926                                            (0x534Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4927                                            (0x09D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4928                                            (0x703Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4929                                            (0x6BA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4930                                            (0x31D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4931                                            (0x6EE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4932                                            (0x46CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4933                                            (0x1B78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4934                                            (0x6879u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4935                                            (0x5C8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4936                                            (0x5C66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4937                                            (0x50F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4938                                            (0x25ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4939                                            (0x6563u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4940                                            (0x726Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4941                                            (0x135Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4942                                            (0x7D03u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4943                                            (0x25ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4944                                            (0x3D91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4945                                            (0x26D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4946                                            (0x2D66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4947                                            (0x587Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4948                                            (0x4357u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4949                                            (0x09DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4950                                            (0x51F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4951                                            (0x5A72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4952                                            (0x7453u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4953                                            (0x171Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4954                                            (0x351Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4955                                            (0x1AE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4956                                            (0x699Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4957                                            (0x0FA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4958                                            (0x3729u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4959                                            (0x21EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4960                                            (0x6B16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4961                                            (0x3F60u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4962                                            (0x539Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4963                                            (0x3E68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4964                                            (0x1D74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4965                                            (0x732Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4966                                            (0x10FBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4967                                            (0x1AE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4968                                            (0x538Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4969                                            (0x0B79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4970                                            (0x1CD3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4971                                            (0x42EDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4972                                            (0x5555u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4973                                            (0x2D59u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4974                                            (0x594Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4975                                            (0x34E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4976                                            (0x60DEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4977                                            (0x533Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4978                                            (0x71A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4979                                            (0x516Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4980                                            (0x07F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4981                                            (0x6971u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4982                                            (0x546Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4983                                            (0x551Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4984                                            (0x2796u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4985                                            (0x0F55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4986                                            (0x72F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4987                                            (0x1DD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4988                                            (0x15F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4989                                            (0x5E19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4990                                            (0x39A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4991                                            (0x3574u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4992                                            (0x73E0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4993                                            (0x6D23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4994                                            (0x4DD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4995                                            (0x564Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4996                                            (0x46ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4997                                            (0x36F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4998                                            (0x2E53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4999                                            (0x523Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5000                                            (0x566Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5001                                            (0x0B37u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5002                                            (0x49ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5003                                            (0x52E6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5004                                            (0x7AC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5005                                            (0x5DA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5006                                            (0x1B63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5007                                            (0x5E2Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5008                                            (0x23ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5009                                            (0x350Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5010                                            (0x6DA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5011                                            (0x07ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5012                                            (0x76E0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5013                                            (0x27E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5014                                            (0x6AB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5015                                            (0x53A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5016                                            (0x62CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5017                                            (0x11F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5018                                            (0x41BEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5019                                            (0x7187u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5020                                            (0x4379u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5021                                            (0x7631u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5022                                            (0x32F1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5023                                            (0x356Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5024                                            (0x1C7Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5025                                            (0x2F85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5026                                            (0x49CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5027                                            (0x27C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5028                                            (0x52D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5029                                            (0x13CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5030                                            (0x1DACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5031                                            (0x78E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5032                                            (0x3C96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5033                                            (0x3C3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5034                                            (0x5ACCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5035                                            (0x1E69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5036                                            (0x7331u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5037                                            (0x3CB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5038                                            (0x56A3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5039                                            (0x345Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5040                                            (0x6D38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5041                                            (0x149Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5042                                            (0x23AEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5043                                            (0x32B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5044                                            (0x66E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5045                                            (0x3D46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5046                                            (0x630Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5047                                            (0x38E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5048                                            (0x07A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5049                                            (0x6339u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5050                                            (0x6CD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5051                                            (0x3C95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5052                                            (0x6F50u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5053                                            (0x1D4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5054                                            (0x56B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5055                                            (0x7A8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5056                                            (0x45B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5057                                            (0x1B5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5058                                            (0x2976u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5059                                            (0x6678u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5060                                            (0x6972u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5061                                            (0x2BE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5062                                            (0x066Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5063                                            (0x7455u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5064                                            (0x2D39u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5065                                            (0x32E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5066                                            (0x7D14u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5067                                            (0x21E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5068                                            (0x29B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5069                                            (0x46B5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5070                                            (0x3547u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5071                                            (0x534Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5072                                            (0x7A13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5073                                            (0x19E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5074                                            (0x32CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5075                                            (0x1CCBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5076                                            (0x349Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5077                                            (0x2D9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5078                                            (0x7C4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5079                                            (0x5EA8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5080                                            (0x5C2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5081                                            (0x1795u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5082                                            (0x434Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5083                                            (0x3556u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5084                                            (0x473Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5085                                            (0x6A69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5086                                            (0x5B4Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5087                                            (0x7662u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5088                                            (0x1727u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5089                                            (0x2F61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5090                                            (0x2DB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5091                                            (0x49A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5092                                            (0x46E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5093                                            (0x6479u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5094                                            (0x792Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5095                                            (0x34ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5096                                            (0x0EA7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5097                                            (0x6627u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5098                                            (0x3696u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5099                                            (0x3593u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5100                                            (0x02FEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5101                                            (0x47AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5102                                            (0x57A4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5103                                            (0x686Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5104                                            (0x256Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5105                                            (0x6917u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5106                                            (0x5C47u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5107                                            (0x5CC6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5108                                            (0x5E4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5109                                            (0x17ACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5110                                            (0x2F23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5111                                            (0x6936u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5112                                            (0x2AB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5113                                            (0x2CB3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5114                                            (0x5C74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5115                                            (0x286Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5116                                            (0x06DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5117                                            (0x6C74u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5118                                            (0x3587u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5119                                            (0x3EA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5120                                            (0x2D4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5121                                            (0x2EE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5122                                            (0x6572u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5123                                            (0x4D1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5124                                            (0x44E7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5125                                            (0x74A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5126                                            (0x4AADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5127                                            (0x0BE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5128                                            (0x4F62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5129                                            (0x35E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5130                                            (0x4E69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5131                                            (0x4F54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5132                                            (0x4667u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5133                                            (0x49E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5134                                            (0x7287u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5135                                            (0x1F62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5136                                            (0x7233u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5137                                            (0x71CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5138                                            (0x3369u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5139                                            (0x46E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5140                                            (0x2E4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5141                                            (0x3D23u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5142                                            (0x334Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5143                                            (0x56E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5144                                            (0x71AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5145                                            (0x38B9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5146                                            (0x3B45u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5147                                            (0x0BF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5148                                            (0x365Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5149                                            (0x1567u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5150                                            (0x635Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5151                                            (0x23DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5152                                            (0x2766u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5153                                            (0x6CE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5154                                            (0x1CF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5155                                            (0x1379u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5156                                            (0x4D69u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5157                                            (0x0D79u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5158                                            (0x22F6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5159                                            (0x7F10u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5160                                            (0x50FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5161                                            (0x4E9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5162                                            (0x347Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5163                                            (0x399Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5164                                            (0x39B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5165                                            (0x6C33u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5166                                            (0x6E26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5167                                            (0x5CE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5168                                            (0x4AE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5169                                            (0x548Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5170                                            (0x33B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5171                                            (0x226Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5172                                            (0x3969u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5173                                            (0x56D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5174                                            (0x692Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5175                                            (0x7531u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5176                                            (0x2F94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5177                                            (0x1DA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5178                                            (0x1EE1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5179                                            (0x165Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5180                                            (0x46D5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5181                                            (0x55AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5182                                            (0x38BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5183                                            (0x6CC9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5184                                            (0x36E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5185                                            (0x156Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5186                                            (0x68D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5187                                            (0x26D6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5188                                            (0x1C9Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5189                                            (0x7329u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5190                                            (0x752Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5191                                            (0x28AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5192                                            (0x1F13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5193                                            (0x7954u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5194                                            (0x79D0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5195                                            (0x21FCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5196                                            (0x54F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5197                                            (0x7C32u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5198                                            (0x6C87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5199                                            (0x5279u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5200                                            (0x4D5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5201                                            (0x5AA6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5202                                            (0x4A75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5203                                            (0x669Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5204                                            (0x3A35u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5205                                            (0x552Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5206                                            (0x4DE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5207                                            (0x41D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5208                                            (0x455Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5209                                            (0x0BB5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5210                                            (0x1CF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5211                                            (0x6157u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5212                                            (0x1B6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5213                                            (0x2C6Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5214                                            (0x4DB2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5215                                            (0x22CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5216                                            (0x2F8Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5217                                            (0x6656u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5218                                            (0x7A58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5219                                            (0x3A8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5220                                            (0x5533u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5221                                            (0x1DA9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5222                                            (0x7A98u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5223                                            (0x27D1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5224                                            (0x1DB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5225                                            (0x0F5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5226                                            (0x6E13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5227                                            (0x65B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5228                                            (0x3D49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5229                                            (0x36B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5230                                            (0x3B0Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5231                                            (0x0C9Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5232                                            (0x143Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5233                                            (0x17AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5234                                            (0x5995u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5235                                            (0x5785u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5236                                            (0x176Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5237                                            (0x51B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5238                                            (0x386Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5239                                            (0x7652u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5240                                            (0x7E41u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5241                                            (0x37A8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5242                                            (0x619Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5243                                            (0x6AD2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5244                                            (0x3E4Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5245                                            (0x7471u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5246                                            (0x503Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5247                                            (0x66B2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5248                                            (0x4DC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5249                                            (0x2CF2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5250                                            (0x6B54u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5251                                            (0x65B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5252                                            (0x7874u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5253                                            (0x42B7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5254                                            (0x1F94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5255                                            (0x1D4Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5256                                            (0x5F84u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5257                                            (0x6987u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5258                                            (0x31B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5259                                            (0x347Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5260                                            (0x16CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5261                                            (0x4A9Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5262                                            (0x0D6Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5263                                            (0x3F50u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5264                                            (0x2F64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5265                                            (0x3687u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5266                                            (0x0ADDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5267                                            (0x0BF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5268                                            (0x3C99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5269                                            (0x1C5Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5270                                            (0x20F7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5271                                            (0x09FAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5272                                            (0x3CF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5273                                            (0x456Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5274                                            (0x18EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5275                                            (0x782Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5276                                            (0x0FD8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5277                                            (0x69C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5278                                            (0x2E4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5279                                            (0x7A64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5280                                            (0x1AF1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5281                                            (0x1AB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5282                                            (0x48F3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5283                                            (0x1FA4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5284                                            (0x12F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5285                                            (0x485Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5286                                            (0x7B44u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5287                                            (0x645Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5288                                            (0x5746u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5289                                            (0x7C85u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5290                                            (0x0773u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5291                                            (0x4997u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5292                                            (0x5F0Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5293                                            (0x2A4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5294                                            (0x317Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5295                                            (0x722Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5296                                            (0x7C64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5297                                            (0x459Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5298                                            (0x525Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5299                                            (0x7493u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5300                                            (0x708Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5301                                            (0x15BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5302                                            (0x7AD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5303                                            (0x3B49u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5304                                            (0x6EC4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5305                                            (0x3E2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5306                                            (0x278Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5307                                            (0x3D13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5308                                            (0x70CDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5309                                            (0x4A1Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5310                                            (0x3CE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5311                                            (0x17B4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5312                                            (0x17E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5313                                            (0x49ADu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5314                                            (0x6AC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5315                                            (0x6D29u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5316                                            (0x0EB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5317                                            (0x6D13u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5318                                            (0x172Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5319                                            (0x77A0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5320                                            (0x10FDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5321                                            (0x0BA7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5322                                            (0x3966u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5323                                            (0x38F4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5324                                            (0x20BFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5325                                            (0x31ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5326                                            (0x1E3Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5327                                            (0x5ACAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5328                                            (0x5D68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5329                                            (0x322Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5330                                            (0x2FA1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5331                                            (0x079Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5332                                            (0x6965u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5333                                            (0x4A76u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5334                                            (0x712Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5335                                            (0x7D30u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5336                                            (0x5B19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5337                                            (0x0EE6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5338                                            (0x0F95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5339                                            (0x68DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5340                                            (0x2BF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5341                                            (0x2EE4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5342                                            (0x632Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5343                                            (0x3C78u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5344                                            (0x7CD0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5345                                            (0x74B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5346                                            (0x189Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5347                                            (0x08BFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5348                                            (0x0BE9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5349                                            (0x0CDDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5350                                            (0x60EBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5351                                            (0x550Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5352                                            (0x17B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5353                                            (0x4DB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5354                                            (0x76A2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5355                                            (0x1D71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5356                                            (0x2DA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5357                                            (0x17CCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5358                                            (0x3F88u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5359                                            (0x65E8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5360                                            (0x788Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5361                                            (0x7706u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5362                                            (0x7983u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5363                                            (0x3A6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5364                                            (0x5996u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5365                                            (0x1735u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5366                                            (0x25D9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5367                                            (0x37B0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5368                                            (0x2BB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5369                                            (0x5E91u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5370                                            (0x5D31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5371                                            (0x4D63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5372                                            (0x7E12u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5373                                            (0x5A4Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5374                                            (0x7465u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5375                                            (0x39C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5376                                            (0x6237u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5377                                            (0x7A61u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5378                                            (0x2A75u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5379                                            (0x2967u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5380                                            (0x6749u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5381                                            (0x1ED8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5382                                            (0x3CC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5383                                            (0x34CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5384                                            (0x4B0Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5385                                            (0x6CB8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5386                                            (0x54CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5387                                            (0x253Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5388                                            (0x313Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5389                                            (0x4AF4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5390                                            (0x2B5Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5391                                            (0x5B64u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5392                                            (0x570Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5393                                            (0x5F81u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5394                                            (0x6327u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5395                                            (0x556Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5396                                            (0x3A4Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5397                                            (0x6659u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5398                                            (0x3A99u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5399                                            (0x62ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5400                                            (0x0C7Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5401                                            (0x625Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5402                                            (0x487Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5403                                            (0x2E8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5404                                            (0x66A9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5405                                            (0x486Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5406                                            (0x05EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5407                                            (0x1E1Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5408                                            (0x6596u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5409                                            (0x59D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5410                                            (0x2CB9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5411                                            (0x74C9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5412                                            (0x291Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5413                                            (0x472Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5414                                            (0x279Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5415                                            (0x113Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5416                                            (0x474Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5417                                            (0x5965u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5418                                            (0x0EF8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5419                                            (0x35E2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5420                                            (0x0F9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5421                                            (0x5535u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5422                                            (0x352Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5423                                            (0x6DC1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5424                                            (0x6C8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5425                                            (0x29ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5426                                            (0x22BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5427                                            (0x6963u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5428                                            (0x363Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5429                                            (0x3CD1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5430                                            (0x196Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5431                                            (0x64DAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5432                                            (0x5696u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5433                                            (0x1E71u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5434                                            (0x6B89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5435                                            (0x3176u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5436                                            (0x6275u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5437                                            (0x39CAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5438                                            (0x4B96u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5439                                            (0x76D0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5440                                            (0x13ECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5441                                            (0x698Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5442                                            (0x3E19u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5443                                            (0x65B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5444                                            (0x741Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5445                                            (0x4FA2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5446                                            (0x7A31u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5447                                            (0x695Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5448                                            (0x2D2Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5449                                            (0x4D8Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5450                                            (0x4747u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5451                                            (0x26E5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5452                                            (0x4CD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5453                                            (0x71C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5454                                            (0x4E53u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5455                                            (0x2AAEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5456                                            (0x3517u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5457                                            (0x1D6Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5458                                            (0x10BFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5459                                            (0x531Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5460                                            (0x0E67u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5461                                            (0x62D3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5462                                            (0x3553u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5463                                            (0x4BA3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5464                                            (0x613Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5465                                            (0x7166u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5466                                            (0x3137u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5467                                            (0x2D5Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5468                                            (0x0AFAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5469                                            (0x446Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5470                                            (0x0BBCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5471                                            (0x6CB4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5472                                            (0x699Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5473                                            (0x1C73u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5474                                            (0x28CFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5475                                            (0x3A27u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5476                                            (0x7D05u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5477                                            (0x6995u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5478                                            (0x1AD6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5479                                            (0x1A5Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5480                                            (0x1F8Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5481                                            (0x79A2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5482                                            (0x70E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5483                                            (0x5F44u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5484                                            (0x6B62u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5485                                            (0x3AAAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5486                                            (0x5AB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5487                                            (0x6CCCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5488                                            (0x47E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5489                                            (0x0E3Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5490                                            (0x6D26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5491                                            (0x2BE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5492                                            (0x47D8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5493                                            (0x66C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5494                                            (0x437Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5495                                            (0x06BBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5496                                            (0x4B8Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5497                                            (0x4B72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5498                                            (0x1E95u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5499                                            (0x1A4Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5500                                            (0x16CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5501                                            (0x7788u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5502                                            (0x6BB0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5503                                            (0x71B8u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5504                                            (0x4E55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5505                                            (0x7C68u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5506                                            (0x42EEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5507                                            (0x6C93u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5508                                            (0x2DE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5509                                            (0x338Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5510                                            (0x1EC3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5511                                            (0x64F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5512                                            (0x56C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5513                                            (0x1EF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5514                                            (0x52BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5515                                            (0x72D4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5516                                            (0x4C9Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5517                                            (0x6B38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5518                                            (0x3E0Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5519                                            (0x391Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5520                                            (0x56E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5521                                            (0x7625u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5522                                            (0x4AECu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5523                                            (0x074Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5524                                            (0x0CF9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5525                                            (0x263Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5526                                            (0x3E38u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5527                                            (0x7946u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5528                                            (0x1BC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5529                                            (0x2D2Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5530                                            (0x38ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5531                                            (0x370Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5532                                            (0x3A2Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5533                                            (0x3279u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5534                                            (0x711Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5535                                            (0x72E1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5536                                            (0x57B0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5537                                            (0x65E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5538                                            (0x643Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5539                                            (0x49E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5540                                            (0x387Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5541                                            (0x7B03u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5542                                            (0x4CE5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5543                                            (0x582Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5544                                            (0x6A1Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5545                                            (0x0779u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5546                                            (0x1E56u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5547                                            (0x58CBu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5548                                            (0x713Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5549                                            (0x4F89u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5550                                            (0x7436u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5551                                            (0x7594u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5552                                            (0x1A9Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5553                                            (0x6E16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5554                                            (0x48AFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5555                                            (0x49B3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5556                                            (0x2D3Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5557                                            (0x7165u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5558                                            (0x0775u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5559                                            (0x4E72u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5560                                            (0x65A6u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5561                                            (0x04EFu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5562                                            (0x616Bu)
+
+MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER()
+
+#endif /* MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Macros.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Macros.h
new file mode 100644
index 0000000000..78e86fb69b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Macros.h
@@ -0,0 +1,57 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClCore_Macros.h
+ * @brief Definition of macros.
+ *
+ */
+
+#ifndef MCUXCLCORE_MACROS_H_
+#define MCUXCLCORE_MACROS_H_
+
+/* Macro to calculate the rounded down number of words that fit into the specified size */
+#define MCUXCLCORE_NUM_OF_WORDS_FLOOR(wordsize, size)  \
+  ((size) / (wordsize))
+
+/* Macro to calculate the rounded up number of words needed to fit an object of the specified size */
+#define MCUXCLCORE_NUM_OF_WORDS_CEIL(wordsize, size)  \
+  (((size) + (wordsize) - 1u) / (wordsize))
+
+/* Macro to calculate the rounded down number of CPU words that fit into the specified size */
+#define MCUXCLCORE_NUM_OF_CPUWORDS_FLOOR(size)  \
+  MCUXCLCORE_NUM_OF_WORDS_FLOOR(sizeof(uint32_t), size)
+
+/* Macro to calculate the rounded up number of CPU words needed to fit an object of the specified size */
+#define MCUXCLCORE_NUM_OF_CPUWORDS_CEIL(size)  \
+  MCUXCLCORE_NUM_OF_WORDS_CEIL(sizeof(uint32_t), size)
+
+/* Macro to round up a given size to the nearest multiple of a specified word size */
+#define MCUXCLCORE_ALIGN_TO_WORDSIZE(wordsize, size)  \
+  (MCUXCLCORE_NUM_OF_WORDS_CEIL(wordsize, size) * (wordsize))
+
+/* Macro to round up a given size to the nearest multiple of the CPU word size */
+#define MCUXCLCORE_ALIGN_TO_CPU_WORDSIZE(size)  \
+  MCUXCLCORE_ALIGN_TO_WORDSIZE(sizeof(uint32_t), size)
+
+/* Macro to calculate the maximum of two values */
+#define MCUXCLCORE_MAX(a, b)  \
+MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT("Fixed values are allowed as macro inputs") \
+  (((a) > (b)) ? (a) : (b)) \
+MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT()
+
+/* Macro to calculate the minimum of two values */
+#define MCUXCLCORE_MIN(a, b)  \
+  (((a) < (b)) ? (a) : (b))
+
+#endif /* MCUXCLCORE_MACROS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Platform.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Platform.h
new file mode 100644
index 0000000000..804f7c6e13
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Platform.h
@@ -0,0 +1,23 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#ifndef MCUXCLCORE_PLATFORM_H_
+#define MCUXCLCORE_PLATFORM_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+#endif /* MCUXCLCORE_PLATFORM_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Toolchain.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Toolchain.h
new file mode 100644
index 0000000000..735b064149
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Toolchain.h
@@ -0,0 +1,33 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#ifndef MCUXCLCORE_TOOLCHAIN_H_
+#define MCUXCLCORE_TOOLCHAIN_H_
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxCsslFlowProtection.h>
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCl_Core_Swap64)
+static inline uint64_t mcuxCl_Core_Swap64(uint64_t value)
+{
+    return __builtin_bswap64(value);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCl_Core_Swap32)
+static inline uint32_t mcuxCl_Core_Swap32(uint32_t value)
+{
+    return __builtin_bswap32(value);
+}
+
+
+#endif /* MCUXCLCORE_TOOLCHAIN_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal.h
new file mode 100644
index 0000000000..7ae2f8a543
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal.h
@@ -0,0 +1,364 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClEls_Internal.h
+ *  @brief Provide macros for mcuxClEls internal use.
+ * This header declares internal macros to deduplicate code and support for internal use only. */
+
+#ifndef MCUXCLELS_INTERNAL_H_
+#define MCUXCLELS_INTERNAL_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <platform_specific_headers.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <mcuxCsslFlowProtection.h>
+
+#include <internal/mcuxClEls_Internal_mapping.h>
+#include <internal/mcuxClEls_SfrAccess.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxClEls_Common.h>
+#include <mcuxClEls_Types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****                                ****/
+/**** ELS Hardware Abstraction Layer ****/
+/****                                ****/
+
+
+/** Asserts the correctness of the supplied parameters*/
+#define MCUXCLELS_INPUT_PARAM_CHECK(x_) if((x_)) { return MCUXCLELS_STATUS_SW_INVALID_PARAM; }
+#define MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(funcid, x_)                         \
+do                                                                              \
+{                                                                               \
+    if ((x_))                                                                    \
+    {                                                                           \
+        MCUX_CSSL_FP_FUNCTION_EXIT(funcid, MCUXCLELS_STATUS_SW_INVALID_PARAM);    \
+    }                                                                           \
+MCUX_CSSL_ANALYSIS_START_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION()      \
+} while (false)                                                                 \
+MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION()
+
+#define ELS_CMD_BIG_ENDIAN ((uint8_t) 0x01U)    ///< ELS command option specifying big-endian byte order
+#define ELS_CMD_LITTLE_ENDIAN ((uint8_t) 0x00U) ///< ELS command option specifying little-endian byte order
+
+// Utility code of mcuxClEls implementation
+
+/** Sets the variable-size input buffer from which the input 0 of the ELS operation will be transferred via DMA. */
+static inline void mcuxClEls_setInput0(const uint8_t *pInput, uint32_t inputSize)
+{
+    MCUXCLELS_SFR_WRITE(ELS_DMA_SRC0,     (uint32_t) pInput);
+    MCUXCLELS_SFR_WRITE(ELS_DMA_SRC0_LEN, inputSize);
+}
+
+/** Sets the fixed-size input buffer from which the input 0 of the ELS operation will be transferred via DMA. */
+static inline void mcuxClEls_setInput0_fixedSize(const uint8_t *pInput)
+{
+    MCUXCLELS_SFR_WRITE(ELS_DMA_SRC0, (uint32_t) pInput);
+}
+
+/** Sets the fixed-size input buffer from which the input 1 of the ELS operation will be transferred via DMA. */
+static inline void mcuxClEls_setInput1_fixedSize(const uint8_t *pInput)
+{
+    MCUXCLELS_SFR_WRITE(ELS_DMA_SRC1, (uint32_t) pInput);
+}
+
+/** Sets the variable-size input buffer from which the input 2 of the ELS operation will be transferred via DMA. */
+static inline void mcuxClEls_setInput2(const uint8_t *pInput, uint32_t inputSize)
+{
+    MCUXCLELS_SFR_WRITE(ELS_DMA_SRC2,     (uint32_t) pInput);
+    MCUXCLELS_SFR_WRITE(ELS_DMA_SRC2_LEN, inputSize);
+}
+
+/** Sets the fixed-size input buffer from which the input 2 of the ELS operation will be transferred via DMA. */
+static inline void mcuxClEls_setInput2_fixedSize(const uint8_t * pInput)
+{
+    MCUXCLELS_SFR_WRITE(ELS_DMA_SRC2, (uint32_t) pInput);
+}
+
+/** Sets the variable-size output buffer to which the result of the ELS operation will be transferred via DMA. */
+static inline void mcuxClEls_setOutput(uint8_t *pOutput, uint32_t outputSize)
+{
+    MCUXCLELS_SFR_WRITE(ELS_DMA_RES0,     (uint32_t) pOutput);
+    MCUXCLELS_SFR_WRITE(ELS_DMA_RES0_LEN, outputSize);
+}
+
+/** Sets the output buffer to which the result of the ELS operation will be transferred via DMA. */
+static inline void mcuxClEls_setOutput_fixedSize(uint8_t *pOutput)
+{
+    MCUXCLELS_SFR_WRITE(ELS_DMA_RES0, (uint32_t) pOutput);
+}
+
+/** Sets the ELS keystore index 0, for commands that access a single key. */
+static inline void mcuxClEls_setKeystoreIndex0(uint32_t index)
+{
+    MCUXCLELS_SFR_WRITE(ELS_KIDX0, index);
+}
+
+
+/** Sets the ELS keystore index 1, for commands that access 2 keys. */
+static inline void mcuxClEls_setKeystoreIndex1(uint32_t index)
+{
+    MCUXCLELS_SFR_WRITE(ELS_KIDX1, index);
+}
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+/** Sets the ELS keystore index 2, for commands that access 3 keys. */
+static inline void mcuxClEls_setKeystoreIndex2(uint32_t index)
+{
+    MCUXCLELS_SFR_WRITE(ELS_KIDX2, index);
+}
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/** Sets the ELS requested key properties, for commands that create a key. */
+static inline void mcuxClEls_setRequestedKeyProperties(uint32_t properties)
+{
+    MCUXCLELS_SFR_WRITE(ELS_KPROPIN, properties);
+}
+
+/** Starts an ELS command. */
+static inline void mcuxClEls_startCommand(uint32_t command, uint32_t cmdcfg0, uint32_t byteOrder)
+{
+    uint32_t ctrl = MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_CMD, command)
+                    | MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_START, 1u)
+                    | MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_EN, 1u)
+                    | MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, BYTE_ORDER, byteOrder);
+
+    MCUXCLELS_SFR_WRITE(ELS_CMDCFG0, cmdcfg0);
+    MCUXCLELS_SFR_WRITE(ELS_CTRL,    ctrl);
+}
+
+
+/** Gets a specific field in the given SFR value, according to the given mask and shift value.
+ *  @retval @c value of the requested field in the given ELS SFR value */
+static inline uint32_t mcuxClEls_getSfrField(uint32_t sfrValue, uint32_t mask, uint32_t shift)
+{
+    return ((uint32_t)(sfrValue & mask) >> shift);
+}
+
+/** Set a specific field in the given SFR value, according to the given mask and shift value.
+  * The unrelated fields/bits will not be changed */
+static inline void mcuxClEls_setSfrField(volatile uint32_t *pSfr, uint32_t value, uint32_t mask, uint32_t shift)
+{
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS("Sfr offset from address")
+	/* get the current value of the SFR and clear the bits that will be set */
+  uint32_t sfrValue = *pSfr & (~mask);
+	/* set the bits and re-write the full value to the SFR */
+  *pSfr = sfrValue | (((uint32_t)(value << shift)) & mask);
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS()
+}
+
+/** Tests if the ELS is in BUSY state.
+ *  @retval @c true if the ELS is in BUSY state */
+static inline bool mcuxClEls_isBusy(void)
+{
+    return (0u != MCUXCLELS_SFR_BITREAD(ELS_STATUS, ELS_BUSY) );
+}
+
+
+/** Macros to access the bit fields for the ELS_STATUS SFR */
+#define MCUXCLELS_SFR_STATUS_ELS_BUSY            ELS_BUSY
+#define MCUXCLELS_SFR_STATUS_ELS_IRQ             ELS_IRQ
+#define MCUXCLELS_SFR_STATUS_ELS_ERR             ELS_ERR
+#define MCUXCLELS_SFR_STATUS_PRNG_RDY            PRNG_RDY
+#define MCUXCLELS_SFR_STATUS_ECDSA_VFY_STATUS    ECDSA_VFY_STATUS
+#define MCUXCLELS_SFR_STATUS_PPROT               PPROT
+#define MCUXCLELS_SFR_STATUS_DRBG_ENT_LVL        DRBG_ENT_LVL
+#define MCUXCLELS_SFR_STATUS_DTRNG_BUSY          DTRNG_BUSY
+#define MCUXCLELS_SFR_STATUS_ELS_LOCKED          ELS_LOCKED
+
+/** Gets a specific field in the ELS_STATUS SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_STATUS_* */
+#define MCUXCLELS_GET_STATUS_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_STATUS), MCUXCLELS_SFR_FIELD_MASK(ELS_STATUS, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_STATUS, field))
+
+
+/** Macros to access the bit fields for the ELS_CTRL SFR */
+#define MCUXCLELS_SFR_CTRL_ELS_EN                ELS_EN
+#define MCUXCLELS_SFR_CTRL_START                 ELS_START
+#define MCUXCLELS_SFR_CTRL_RESET                 ELS_RESET
+#define MCUXCLELS_SFR_CTRL_CMD                   ELS_CMD
+#define MCUXCLELS_SFR_CTRL_BYTE_ORDER            BYTE_ORDER
+
+/** Gets a specific field in the ELS_CTRL SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_CTRL_* */
+#define MCUXCLELS_GET_CTRL_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_CTRL), MCUXCLELS_SFR_FIELD_MASK(ELS_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CTRL, field))
+
+/** Sets a specific field in the ELS_CTRL SFR. The unrelated fields/bits will not be changed
+ *  @param field: Any field name in MCUXCLELS_SFR_CTRL_*
+ *  @param value: The value to set the requested SFR field to */
+#define MCUXCLELS_SET_CTRL_FIELD(field, value) \
+  mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_CTRL), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CTRL, field))
+
+
+/** Macros to access the bit fields for the ELS_CFG SFR */
+#define MCUXCLELS_SFR_CFG_ADCTRL                 ADCTRL
+#define MCUXCLELS_SFR_CFG_SHA2_DIRECT            SHA2_DIRECT
+
+/** Gets a specific field in the ELS_CFG SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_CFG_* */
+#define MCUXCLELS_GET_CFG_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_CFG), MCUXCLELS_SFR_FIELD_MASK(ELS_CFG, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CFG, field))
+
+/** Sets a specific field in the ELS_CFG SFR. The unrelated fields/bits will not be changed
+ *  @param field: Any field name in MCUXCLELS_SFR_CFG_*
+ *  @param value: The value to set the requested SFR field to */
+#define MCUXCLELS_SET_CFG_FIELD(field, value) \
+  mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_CFG), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_CFG, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CFG, field))
+
+
+/** Macros to access the bit fields for the ELS_ERR_STATUS SFR */
+#define MCUXCLELS_SFR_ERR_STATUS_BUS_ERR         BUS_ERR
+#define MCUXCLELS_SFR_ERR_STATUS_OPN_ERR         OPN_ERR
+#define MCUXCLELS_SFR_ERR_STATUS_ALG_ERR         ALG_ERR
+#define MCUXCLELS_SFR_ERR_STATUS_ITG_ERR         ITG_ERR
+#define MCUXCLELS_SFR_ERR_STATUS_FLT_ERR         FLT_ERR
+#define MCUXCLELS_SFR_ERR_STATUS_PRNG_ERR        PRNG_ERR
+#define MCUXCLELS_SFR_ERR_STATUS_ERR_LVL         ERR_LVL
+#define MCUXCLELS_SFR_ERR_STATUS_DTRNG_ERR       DTRNG_ERR
+
+/** Gets a specific field in the ELS_ERR_STATUS SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_ERR_STATUS_* */
+#define MCUXCLELS_GET_ERROR_STATUS_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_ERR_STATUS), MCUXCLELS_SFR_FIELD_MASK(ELS_ERR_STATUS, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_ERR_STATUS, field))
+
+/** Checks if a specific error bit in the ELS_ERR_STATUS SFR is set.
+ *  @retval @c true if the requested ELS error status bit is set */
+#define MCUXCLELS_IS_ERROR_BIT_SET(field) \
+    (1u == MCUXCLELS_GET_ERROR_STATUS_FIELD(field))
+
+
+/** Macros to access the bit fields for the ELS_CMDCRC_CTRL SFR */
+#define MCUXCLELS_SFR_CMDCRC_CTRL_CMDCRC_RST     CMDCRC_RST
+#define MCUXCLELS_SFR_CMDCRC_CTRL_CMDCRC_EN      CMDCRC_EN
+
+/** Sets a specific field in the ELS_CMDCRC_CTRL SFR. The unrelated fields/bits will not be changed
+ *  @param field: Any field name in MCUXCLELS_SFR_CMDCRC_CTRL_*
+ *  @param value: The value to set the requested SFR field to */
+#define MCUXCLELS_SET_CMDCRC_CTRL_FIELD(field, value) \
+  mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_CMDCRC_CTRL), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_CMDCRC_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CMDCRC_CTRL, field))
+
+/** Macros to access the bit fields for the ELS_SHA2_CTRL SFR */
+#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_START       SHA2_START
+#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_RST         SHA2_RST
+#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_INIT        SHA2_INIT
+#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_LOAD        SHA2_LOAD
+#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_MODE        SHA2_MODE
+#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_BYTE_ORDER  SHA2_BYTE_ORDER
+
+/** Gets a specific field in the ELS_SHA2_CTRL SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_SHA2_CTRL_* */
+#define MCUXCLELS_GET_SHA2_CTRL_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_SHA2_CTRL), MCUXCLELS_SFR_FIELD_MASK(ELS_SHA2_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_SHA2_CTRL, field))
+
+/** Sets a specific field in the ELS_SHA2_CTRL SFR. The unrelated fields/bits will not be changed
+ *  @param field: Any field name in MCUXCLELS_SFR_SHA2_CTRL_*
+ *  @param value: The value to set the requested SFR field to */
+#define MCUXCLELS_SET_SHA2_CTRL_FIELD(field, value) \
+  mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_SHA2_CTRL), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_SHA2_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_SHA2_CTRL, field))
+
+
+/** Macro to access the bit fields for the ELS_SHA2_STATUS SFR */
+#define MCUXCLELS_SFR_SHA2_STATUS_SHA2_BUSY      SHA2_BUSY
+
+/** Gets a specific field in the ELS_SHA2_STATUS SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_SHA2_STATUS_* */
+#define MCUXCLELS_GET_SHA2_STATUS_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_SHA2_STATUS), MCUXCLELS_SFR_FIELD_MASK(ELS_SHA2_STATUS, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_SHA2_STATUS, field))
+
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+/**
+ * Macros to access the bit fields for the ELS_GDET_EVTCNT SFR
+ * */
+#define MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT            GDET_EVTCNT
+#define MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE   GDET_EVTCNT_CLR_DONE
+
+/** Gets a specific field in ELS_GDET_EVTCNT SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_GDET_EVTCNT_* */
+#define MCUXCLELS_GET_GDET_EVTCNT_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_GDET_EVTCNT), MCUXCLELS_SFR_FIELD_MASK(ELS_GDET_EVTCNT, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_GDET_EVTCNT, field))
+
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+
+/** Macros to access the bit fields for the ELS_INT_ENABLE SFR */
+#define MCUXCLELS_SFR_INT_ENABLE_INT_EN           INT_EN
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+#define MCUXCLELS_SFR_INT_ENABLE_GDET_INT_EN      GDET_INT_EN
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+
+/** Gets a specific field in the ELS_INT_ENABLE SFR.
+ *  @param field: Any field name in MCUXCLELS_SFR_INT_ENABLE_* */
+#define MCUXCLELS_GET_INT_ENABLE_FIELD(field) \
+  mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_INT_ENABLE), MCUXCLELS_SFR_FIELD_MASK(ELS_INT_ENABLE, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_INT_ENABLE, field))
+
+
+/* Total buffer size in output, which is used for cache maintenance */
+#define MCUXCLELS_HASH_BUFFER_SIZE(options)  MCUXCLELS_HASH_BUFFER_SIZE_DIGEST(options) +  MCUXCLELS_HASH_BUFFER_SIZE_RTF(options)
+#define MCUXCLELS_HASH_BUFFER_SIZE_RTF(options) ( (MCUXCLELS_HASH_RTF_OUTPUT_ENABLE == options.bits.rtfoe) ? MCUXCLELS_HASH_RTF_OUTPUT_SIZE : 0u )
+#define MCUXCLELS_HASH_BUFFER_SIZE_DIGEST(options) ( (1u < options.bits.hashmd) ? MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512 : MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 )
+
+#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING
+extern uint32_t mcuxClEls_rng_drbg_block_counter;
+
+#define MCUXCLELS_RNG_DRBG_ITERATIVE_SEEDING_ITERATIONS  8u
+#define MCUXCLELS_RNG_DRBG_BLOCK_COUNTER_THRESHOLD       4096u
+#define MCUXCLELS_RNG_DRBG_ECCKEYGEN_INCREASE            10u
+#define MCUXCLELS_RNG_DRBG_ECCSIGN_INCREASE              14u
+#define MCUXCLELS_RNG_DRBG_ECCVERIFY_INCREASE            5u
+#define MCUXCLELS_RNG_DRBG_KEYDELETE128_INCREASE         4u
+#define MCUXCLELS_RNG_DRBG_KEYDELETE256_INCREASE         6u
+#define MCUXCLELS_RNG_DRBG_DRBGREQUEST_INCREASE(outputLength) ((outputLength + 15u) / 16u)
+
+/**
+ * @brief This function resets the internal ELS DRBG block counter and reseeds the ELS DRBG
+ *        using the iterative reseeding procedure
+ *
+ * @retval #MCUXCLELS_STATUS_SW_FAULT            if a failure occurred
+ * @retval #MCUXCLELS_STATUS_OK                  on successful operation
+ */
+MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER()
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Dtrng_IterativeReseeding_Reseed)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Dtrng_IterativeReseeding_Reseed(const uint8_t *pDtrngConfig);
+MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER()
+#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */
+
+
+/**
+ * @brief This function provides error handling for mcuxClEls_KeyExport_Async function
+ *
+ * @param[in]   pOutput              The memory address of the exported key which will be cleared
+ * @param[in]   keyLength            The key length which will be cleared
+ * @param[in]   interrupt_state_old  The interrupts state which will be restored
+ *
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_handleKeyExportError)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_handleKeyExportError(uint8_t *pOutput, size_t keyLength, mcuxClEls_InterruptOptionEn_t interrupt_state_old);
+
+/* Functional macro to check for ELS Level 1 errors */
+#define MCUXCLELS_LEVEL1_ERROR(returnCode) (MCUXCLELS_STATUS_HW_OPERATIONAL == (returnCode)) || (MCUXCLELS_STATUS_HW_ALGORITHM == (returnCode)) || (MCUXCLELS_STATUS_HW_BUS == (returnCode))
+
+/** read from ELS PRNG SFR. */
+static inline uint32_t mcuxClEls_readPrngOut(void)
+{
+    return MCUXCLELS_SFR_READ(ELS_PRNG_DATOUT); 
+}
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_INTERNAL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_Common.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_Common.h
new file mode 100644
index 0000000000..620c1c424e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_Common.h
@@ -0,0 +1,67 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Internal_Common.h
+ * @brief ELS header for common internal functionality.
+ */
+
+#ifndef MCUXCLELS_INTERNAL_COMMON_H_
+#define MCUXCLELS_INTERNAL_COMMON_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common types
+#include <platform_specific_headers.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+
+/**
+ * @def MCUXCLELS_HW_VERSION
+ * @ingroup mcuxClEls_Common
+ * @brief Compatible ELS hardware IP version for the CLNS release that this header is part of.
+ */
+#ifndef MCUXCL_FEATURE_ELS_GET_FW_VERSION
+#define MCUXCLELS_HW_VERSION ((mcuxClEls_HwVersion_t) { \
+        .bits = { \
+            .revision = (uint32_t) ELS_HW_VERSION_REVISION, \
+            .minor = (uint32_t) ELS_HW_VERSION_MINOR, \
+            .major = (uint32_t) ELS_HW_VERSION_MAJOR, \
+            .level = (uint32_t) ELS_HW_VERSION_LEVEL \
+        } \
+    })
+#else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
+#define MCUXCLELS_HW_VERSION ((mcuxClEls_HwVersion_t) { \
+        .bits = { \
+            .revision = (uint32_t) ELS_HW_VERSION_REVISION, \
+            .minor = (uint32_t) ELS_HW_VERSION_MINOR, \
+            .major = (uint32_t) ELS_HW_VERSION_MAJOR, \
+            .fw_revision = (uint32_t) ELS_HW_VERSION_FW_REVISION, \
+            .fw_minor = (uint32_t) ELS_HW_VERSION_FW_MINOR, \
+            .fw_major = (uint32_t) ELS_HW_VERSION_FW_MAJOR \
+        } \
+    })
+#endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_INTERNAL_COMMON_H_ */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_mapping.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_mapping.h
new file mode 100644
index 0000000000..39497a7263
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_mapping.h
@@ -0,0 +1,105 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Internal_mapping.h
+ * @brief Header providing mapping for legacy definitions (with CSS)
+ */
+
+#ifndef MCUXCLELS_INTERNAL_MAPPING_H_
+#define MCUXCLELS_INTERNAL_MAPPING_H_
+
+#if !defined(ELS_KS_CNT)
+#define ELS_KS_CNT  CSS_KS_CNT
+#endif
+
+#if !defined(ID_CFG_ELS_CMD_AUTH_CIPHER)
+#define ID_CFG_ELS_CMD_AUTH_CIPHER  ID_CFG_CSS_CMD_AUTH_CIPHER
+#endif
+#if !defined(ID_CFG_ELS_CMD_CHAL_RESP_GEN)
+#define ID_CFG_ELS_CMD_CHAL_RESP_GEN  ID_CFG_CSS_CMD_CHAL_RESP_GEN
+#endif
+#if !defined(ID_CFG_ELS_CMD_CIPHER)
+#define ID_CFG_ELS_CMD_CIPHER  ID_CFG_CSS_CMD_CIPHER
+#endif
+#if !defined(ID_CFG_ELS_CMD_CKDF)
+#define ID_CFG_ELS_CMD_CKDF  ID_CFG_CSS_CMD_CKDF
+#endif
+#if !defined(ID_CFG_ELS_CMD_CMAC)
+#define ID_CFG_ELS_CMD_CMAC  ID_CFG_CSS_CMD_CMAC
+#endif
+#if !defined(ID_CFG_ELS_CMD_DRBG_TEST)
+#define ID_CFG_ELS_CMD_DRBG_TEST  ID_CFG_CSS_CMD_DRBG_TEST
+#endif
+#if !defined(ID_CFG_ELS_CMD_DTRNG_CFG_LOAD)
+#define ID_CFG_ELS_CMD_DTRNG_CFG_LOAD  ID_CFG_CSS_CMD_DTRNG_CFG_LOAD
+#endif
+#if !defined(ID_CFG_ELS_CMD_DTRNG_EVAL)
+#define ID_CFG_ELS_CMD_DTRNG_EVAL  ID_CFG_CSS_CMD_DTRNG_EVAL
+#endif
+#if !defined(ID_CFG_ELS_CMD_DTRNG_PRVL_CFG_LOAD)
+#define ID_CFG_ELS_CMD_DTRNG_PRVL_CFG_LOAD  ID_CFG_CSS_CMD_DTRNG_PRVL_CFG_LOAD
+#endif
+#if !defined(ID_CFG_ELS_CMD_ECKXH)
+#define ID_CFG_ELS_CMD_ECKXH  ID_CFG_CSS_CMD_ECKXH
+#endif
+#if !defined(ID_CFG_ELS_CMD_ECSIGN)
+#define ID_CFG_ELS_CMD_ECSIGN  ID_CFG_CSS_CMD_ECSIGN
+#endif
+#if !defined(ID_CFG_ELS_CMD_ECVFY)
+#define ID_CFG_ELS_CMD_ECVFY  ID_CFG_CSS_CMD_ECVFY
+#endif
+#if !defined(ID_CFG_ELS_CMD_GDET_CFG_LOAD)
+#define ID_CFG_ELS_CMD_GDET_CFG_LOAD  ID_CFG_CSS_CMD_GDET_CFG_LOAD
+#endif
+#if !defined(ID_CFG_ELS_CMD_GDET_TRIM)
+#define ID_CFG_ELS_CMD_GDET_TRIM  ID_CFG_CSS_CMD_GDET_TRIM
+#endif
+#if !defined(ID_CFG_ELS_CMD_HASH)
+#define ID_CFG_ELS_CMD_HASH  ID_CFG_CSS_CMD_HASH
+#endif
+#if !defined(ID_CFG_ELS_CMD_HKDF)
+#define ID_CFG_ELS_CMD_HKDF  ID_CFG_CSS_CMD_HKDF
+#endif
+#if !defined(ID_CFG_ELS_CMD_HMAC)
+#define ID_CFG_ELS_CMD_HMAC  ID_CFG_CSS_CMD_HMAC
+#endif
+#if !defined(ID_CFG_ELS_CMD_KDELETE)
+#define ID_CFG_ELS_CMD_KDELETE  ID_CFG_CSS_CMD_KDELETE
+#endif
+#if !defined(ID_CFG_ELS_CMD_KEYGEN)
+#define ID_CFG_ELS_CMD_KEYGEN  ID_CFG_CSS_CMD_KEYGEN
+#endif
+#if !defined(ID_CFG_ELS_CMD_KEYIN)
+#define ID_CFG_ELS_CMD_KEYIN  ID_CFG_CSS_CMD_KEYIN
+#endif
+#if !defined(ID_CFG_ELS_CMD_KEYOUT)
+#define ID_CFG_ELS_CMD_KEYOUT  ID_CFG_CSS_CMD_KEYOUT
+#endif
+#if !defined(ID_CFG_ELS_CMD_KEYPROV)
+#define ID_CFG_ELS_CMD_KEYPROV  ID_CFG_CSS_CMD_KEYPROV
+#endif
+#if !defined(ID_CFG_ELS_CMD_TLS)
+#define ID_CFG_ELS_CMD_TLS  ID_CFG_CSS_CMD_TLS
+#endif
+
+#if (!defined(ID_CFG_ELS_CMD_RND_REQ)) && defined(ID_CFG_CSS_CMD_RND_REQ)
+#define ID_CFG_ELS_CMD_RND_REQ  ID_CFG_CSS_CMD_RND_REQ
+#endif
+
+#if (!defined(ID_CFG_ELS_CMD_DRBG_REQ)) && defined(ID_CFG_CSS_CMD_DRBG_REQ)
+#define ID_CFG_ELS_CMD_DRBG_REQ  ID_CFG_CSS_CMD_DRBG_REQ
+#endif
+
+
+#endif /* MCUXCLELS_INTERNAL_MAPPING_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_SfrAccess.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_SfrAccess.h
new file mode 100644
index 0000000000..fdad73bfc1
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_SfrAccess.h
@@ -0,0 +1,92 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClEls_SfrAccess.h
+ *  @brief Provide macros for mcuxClEls internal use.
+ * This header declares internal macros to deduplicate code and support for internal use only. */
+
+#ifndef MCUXCLELS_SFRACCESS_H_
+#define MCUXCLELS_SFRACCESS_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <platform_specific_headers.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <internal/mcuxClEls_Internal_mapping.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****                                ****/
+/**** ELS Hardware Abstraction Layer ****/
+/****                                ****/
+
+/**
+ * Definitions for accessing ELS SFRs via, e.g., IP_ELS->STATUS.
+ */
+
+/** Helper macros for constructing SFR field name constants */
+#define MCUXCLELS_PASTE(a,b)  a ## b
+#define MCUXCLELS_CONCAT(a,b) MCUXCLELS_PASTE(a,b)
+#define MCUXCLELS_SFR_FIELD(prefix,sfr,field)        MCUXCLELS_CONCAT(prefix, sfr ## _ ## field)
+
+/** Helper macros to get the mask and shift values for a specific ELS SFR field */
+#define MCUXCLELS_SFR_FIELD_MASK(sfr, field)         MCUXCLELS_CONCAT(MCUXCLELS_SFR_FIELD(ELS_SFR_PREFIX,sfr,field), _MASK)
+#define MCUXCLELS_SFR_FIELD_SHIFT(sfr, field)        MCUXCLELS_CONCAT(MCUXCLELS_SFR_FIELD(ELS_SFR_PREFIX,sfr,field), _SHIFT)
+#define MCUXCLELS_SFR_FIELD_FORMAT(sfr, field, val)  (MCUXCLELS_SFR_FIELD(ELS_SFR_PREFIX,sfr,field) (val))
+
+/**********************************************************/
+/* Helper macros for ELS SFR access                       */
+/**********************************************************/
+
+/** Read from ELS SFR */
+#define MCUXCLELS_SFR_READ(sfr)  (ELS_SFR_BASE->ELS_SFR_NAME(sfr))
+
+/** Write to ELS SFR */
+#define MCUXCLELS_SFR_WRITE(sfr, value)                                                  \
+    do{                                                                                 \
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS("Sfr offset from address")    \
+        ELS_SFR_BASE->ELS_SFR_NAME(sfr) = (value);                                      \
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS()                              \
+    } while(false)
+
+/** Read from ELS SFR bit field */
+#define MCUXCLELS_SFR_BITREAD(sfr, bit)  \
+    ((ELS_SFR_BASE->ELS_SFR_NAME(sfr) & MCUXCLELS_SFR_FIELD_MASK(sfr, bit)) >> MCUXCLELS_SFR_FIELD_SHIFT(sfr, bit))
+
+/** Set bit field of ELS SFR (read-modify-write) */
+#define MCUXCLELS_SFR_BITSET(sfr, bit)  \
+    do{ ELS_SFR_BASE->ELS_SFR_NAME(sfr) |= MCUXCLELS_SFR_FIELD_MASK(sfr, bit); } while(false)
+
+/** Clear bit field of ELS SFR (read-modify-write) */
+#define MCUXCLELS_SFR_BITCLEAR(sfr, bit)  \
+    do{ ELS_SFR_BASE->ELS_SFR_NAME(sfr) &= (~ (uint32_t) MCUXCLELS_SFR_FIELD_MASK(sfr, bit)); } while(false)
+
+/** Set value of multi-bit field of ELS SFR (read-modify-write) */
+#define MCUXCLELS_SFR_BITVALSET(sfr, bit, val)  \
+    do{                                                                                                                             \
+        uint32_t temp = ELS_SFR_BASE->ELS_SFR_NAME(sfr) & (~ (uint32_t) MCUXCLELS_SFR_FIELD_MASK(sfr, bit));                         \
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS("Sfr offset from address")                                                \
+        ELS_SFR_BASE->ELS_SFR_NAME(sfr) = temp | ((val) << MCUXCLELS_SFR_FIELD_SHIFT(sfr, bit)) & MCUXCLELS_SFR_FIELD_MASK(sfr, bit); \
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS()                                                                          \
+    } while(false)
+
+/**** ------------------------------ ****/
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_SFRACCESS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls.h
new file mode 100644
index 0000000000..be55ed0368
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls.h
@@ -0,0 +1,256 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020, 2022 NXP                                                 */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls.h
+ * @brief Top-level include file for the ELS driver
+ *
+ * This includes headers for all of the functionality provided by the ELS IP.
+ *
+ * @defgroup mcuxClEls mcuxClEls
+ * @brief ELS driver
+ *
+ * This component abstracts the hardware access to the ELS IP.
+ * The library exposes the following hardware functionality:
+ * <ol>
+ *      <li> COMMON
+ *          <ul>
+ *              <li> Determine information of the underlying ELS hardware IP
+ *                  <ul> <li> #mcuxClEls_GetHwVersion </ul>
+ *                  @if MCUXCL_FEATURE_ELS_HWCONFIG
+ *                  <ul> <li> #mcuxClEls_GetHwConfig </ul>
+ *                  @endif
+ *                  <ul> <li> #mcuxClEls_GetHwState </ul>
+ *              <li> ELS enabling, disabling, and software reset
+ *                  <ul> <li> #mcuxClEls_Enable_Async </ul>
+ *                  <ul> <li> #mcuxClEls_Reset_Async </ul>
+ *                  <ul> <li> #mcuxClEls_Disable </ul>
+ *              <li> Interrupt management
+ *                  <ul> <li> #mcuxClEls_SetIntEnableFlags </ul>
+ *                  <ul> <li> #mcuxClEls_GetIntEnableFlags </ul>
+ *                  <ul> <li> #mcuxClEls_ResetIntFlags </ul>
+ *                  <ul> <li> #mcuxClEls_SetIntFlags </ul>
+ *              <li> Wait for completion of an ELS operation
+ *                  <ul> <li> #mcuxClEls_WaitForOperation </ul>
+ *                  <ul> <li> #mcuxClEls_LimitedWaitForOperation </ul>
+ *              <li> Error handling
+ *                  <ul> <li> #mcuxClEls_ResetErrorFlags </ul>
+ *                  <ul> <li> #mcuxClEls_GetErrorCode </ul>
+ *                  <ul> <li> #mcuxClEls_GetErrorLevel </ul>
+ *              <li> Random delay feature for AES based operations
+ *                  <ul> <li> #mcuxClEls_SetRandomStartDelay </ul>
+ *                  <ul> <li> #mcuxClEls_GetRandomStartDelay </ul>
+ *              @if MCUXCL_FEATURE_ELS_LOCKING
+ *              <li> ELS Locking
+ *                  <ul> <li> #mcuxClEls_GetLock </ul>
+ *                  <ul> <li> #mcuxClEls_ReleaseLock </ul>
+ *                  <ul> <li> #mcuxClEls_IsLocked </ul>
+ *                  <ul> <li> #mcuxClEls_SetMasterUnlock </ul>
+ *              @endif
+ *              @if MCUXCL_FEATURE_ELS_RESP_GEN
+ *              <li> Calculate response to a hardware generated challenge
+ *                  <ul> <li> #mcuxClEls_RespGen_Async </ul>
+ *              @endif
+ *              @if MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK
+ *              <li> Final Address Readback (security feature)
+ *                  <ul> <li> #mcuxClEls_GetLastDmaAddress </ul>
+ *              @endif
+ *              @if MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
+ *              <li> Final Address Compare (security feature)
+ *                  <ul> <li> #mcuxClEls_CompareDmaFinalOutputAddress </ul>
+ *              @endif
+ *          </ul>
+ *      <li> CRC
+ *          <ul>
+ *              <li> Command CRC checks
+ *                  <ul> <li> #mcuxClEls_ConfigureCommandCRC </ul>
+ *                  <ul> <li> #mcuxClEls_GetCommandCRC </ul>
+ *                  <ul> <li> #mcuxClEls_VerifyVsRefCRC </ul>
+ *                  <ul> <li> #mcuxClEls_UpdateRefCRC </ul>
+ *          </ul>
+ *      <li> HASH
+ *          <ul>
+ *              <li> SHA-2 hashing
+ *                  <ul> <li> #mcuxClEls_Hash_Async </ul>
+ *          @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ *              <li> SHA-2 hashing in direct mode
+ *                  <ul> <li> #mcuxClEls_ShaDirect_Enable </ul>
+ *                  <ul> <li> #mcuxClEls_ShaDirect_Disable </ul>
+ *                  <ul> <li> #mcuxClEls_Hash_ShaDirect </ul>
+ *          @endif
+ *          </ul>
+ *      @if MCUXCL_FEATURE_ELS_HMAC
+ *      <li> HMAC (Keyed-Hash Message Authentication Code)
+ *          <ul>
+ *              <li> HMAC
+ *                  <ul> <li> #mcuxClEls_Hmac_Async </ul>
+ *          </ul>
+ *      @endif
+ *      @if MCUXCL_FEATURE_ELS_CMAC
+ *      <li> CMAC (Cipher-Based Message Authentication Code)
+ *          <ul>
+ *              <li> CMAC
+ *                  <ul> <li> #mcuxClEls_Cmac_Async </ul>
+ *          </ul>
+ *      @endif
+ *      <li> CIPHER (Symmetric Encryption)
+ *          <ul>
+ *              <li> AES
+ *                  <ul> <li> #mcuxClEls_Cipher_Async </ul>
+ *          </ul>
+ *      @if MCUXCL_FEATURE_ELS_AEAD
+ *      <li> AEAD (Authenticated Encryption with Associated Data)
+ *          <ul>
+ *              <li> Authenticated Encryption with Associated Data
+ *                  <ul>
+ *                      <li> #mcuxClEls_Aead_Init_Async
+ *                      <li> #mcuxClEls_Aead_UpdateAad_Async
+ *                      <li> #mcuxClEls_Aead_UpdateData_Async
+ *                      <li> #mcuxClEls_Aead_Finalize_Async
+ *                  </ul>
+ *          </ul>
+ *      @endif
+ *      <li> KEY MANAGEMENT
+ *          <ul>
+ *          @if MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE
+ *              <li> Key deletion
+ *                  <ul> <li> #mcuxClEls_KeyDelete_Async </ul>
+ *          @endif
+ *          @if MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV
+ *              <li> Key provisioning
+ *                  <ul> <li> #mcuxClEls_KeyProvision_Async </ul>
+ *          @endif
+ *          @if MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM
+ *              <li> Key provisioning (ROM)
+ *                  <ul> <li> #mcuxClEls_KeyProvisionRom_Async </ul>
+ *          @endif
+ *              <li> Key import
+ *                  <ul> <li> #mcuxClEls_KeyImport_Async </ul>
+ *          @if MCUXCL_FEATURE_ELS_PUK_INTERNAL
+ *              <li> Public key import
+ *                  <ul> <li> #mcuxClEls_KeyImportPuk_Async </ul>
+ *          @endif
+ *          @if MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT
+ *              <li> Key export
+ *                  <ul> <li> #mcuxClEls_KeyExport_Async </ul>
+ *          @endif
+ *              <li> Key properties
+ *                  <ul> <li> #mcuxClEls_GetKeyProperties </ul>
+ *          </ul>
+ *      @if MCUXCL_FEATURE_ELS_RNG
+ *      <li> RNG
+ *          <ul>
+ *              <li> Random data generation using DRBG
+ *                  <ul> <li> #mcuxClEls_Rng_DrbgRequest_Async </ul>
+ *              @if MCUXCL_FEATURE_ELS_RND_RAW
+ *              <li> Get raw (unprocessed) random data from the DTRNG
+ *                  <ul> <li> #mcuxClEls_Rng_DrbgRequestRaw_Async </ul>
+ *              @endif
+ *              <li> FIPS CAVP test mode
+ *                  <ul> <li> #mcuxClEls_Rng_DrbgTestInstantiate_Async </ul>
+ *                  <ul> <li> #mcuxClEls_Rng_DrbgTestExtract_Async </ul>
+ *                  <ul> <li> #mcuxClEls_Rng_DrbgTestAesEcb_Async </ul>
+ *                  <ul> <li> #mcuxClEls_Rng_DrbgTestAesCtr_Async </ul>
+ *              <li> Configuration of the DTRNG
+ *                  <ul> <li> #mcuxClEls_Rng_Dtrng_ConfigLoad_Async </ul>
+ *                  <ul> <li> #mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async </ul>
+ *              <li> PRNG
+ *              @if MCUXCL_FEATURE_ELS_PRND_INIT
+ *                  <ul> <li> #mcuxClEls_Prng_Init_Async </ul>
+ *              @endif
+ *                  <ul> <li> #mcuxClEls_Prng_GetRandomWord </ul>
+ *                  <ul> <li> #mcuxClEls_Prng_GetRandom </ul>
+ *          </ul>
+ *      @endif
+ *      <li> ECC (Elliptic Curve Cryptography)
+ *          <ul>
+ *              <li> ECC Key generation
+ *                  <ul> <li> #mcuxClEls_EccKeyGen_Async </ul>
+ *              @if MCUXCL_FEATURE_ELS_ECC_KEY_EXCHANGE
+ *              <li> ECC key exchange
+ *                  <ul> <li> #mcuxClEls_EccKeyExchange_Async </ul>
+ *                  @if MCUXCL_FEATURE_ELS_PUK_INTERNAL
+ *                  <ul> <li> #mcuxClEls_EccKeyExchangeInt_Async </ul>
+ *                  @endif
+ *              @endif
+ *              <li> ECC signature generation
+ *                  <ul> <li> #mcuxClEls_EccSign_Async </ul>
+ *              <li> ECC signature verification
+ *                  <ul> <li> #mcuxClEls_EccVerify_Async </ul>
+ *              @if MCUXCL_FEATURE_ELS_PUK_INTERNAL
+ *                  <ul> <li> #mcuxClEls_EccVerifyInt_Async </ul>
+ *              @endif
+ *          </ul>
+ *      <li> KEY DERIVATION
+ *          <ul>
+ *              <li> Key derivation
+ *                  <ul>
+ *                      @if MCUXCL_FEATURE_ELS_CKDF
+ *                      <li> #mcuxClEls_Ckdf_Sp800108_Async
+ *                      @if  MCUXCL_FEATURE_ELS_CKDF_SP80056C
+ *                      <li> #mcuxClEls_Ckdf_Sp80056c_Extract_Async
+ *                      <li> #mcuxClEls_Ckdf_Sp80056c_Expand_Async
+ *                      @endif
+ *                      @endif
+ *                      @if MCUXCL_FEATURE_ELS_HKDF
+ *                      <li> #mcuxClEls_Hkdf_Rfc5869_Async
+ *                      <li> #mcuxClEls_Hkdf_Sp80056c_Async
+ *                      @endif
+ *                  </ul>
+ *              @if MCUXCL_FEATURE_ELS_TLS
+ *              <li> Master Key and Session Key derivation
+ *                  <ul>
+ *                      <li> #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async
+ *                      <li> #mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async
+ *                  </ul>
+ *              @endif
+ *          </ul>
+ *      @if MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+ *      <li> ELS Glitch Detector control
+ *          <ul>
+ *              <li> #mcuxClEls_GlitchDetector_LoadConfig_Async
+ *              <li> #mcuxClEls_GlitchDetector_Trim_Async
+ *              <li> #mcuxClEls_GlitchDetector_GetEventCounter
+ *              <li> #mcuxClEls_GlitchDetector_ResetEventCounter
+ *          </ul>
+ *      @endif
+ *  </ol>
+ *
+ *  After each call to a function ending in <tt>_Async</tt>, one of the waiting functions #mcuxClEls_WaitForOperation or #mcuxClEls_LimitedWaitForOperation must be called to ensure completion.
+ *  The waiting functions may fail, e.g., when the ELS enters an error state.
+ */
+
+#ifndef MCUXCLELS_H_
+#define MCUXCLELS_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+#include <mcuxClEls_Types.h>
+#include <mcuxClEls_Common.h>
+#ifdef MCUXCL_FEATURE_ELS_CMD_CRC
+#include <mcuxClEls_Crc.h>
+#endif /* MCUXCL_FEATURE_ELS_CMD_CRC */
+#include <mcuxClEls_Hash.h>
+#include <mcuxClEls_Hmac.h>
+#include <mcuxClEls_Cmac.h>
+#include <mcuxClEls_Cipher.h>
+#include <mcuxClEls_Aead.h>
+#include <mcuxClEls_KeyManagement.h>
+#include <mcuxClEls_Rng.h>
+#include <mcuxClEls_Ecc.h>
+#include <mcuxClEls_Kdf.h>
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+#include <mcuxClEls_GlitchDetector.h>
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+
+#endif /* MCUXCLELS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Aead.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Aead.h
new file mode 100644
index 0000000000..c0486bec8a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Aead.h
@@ -0,0 +1,457 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Aead.h
+ * @brief ELS header for Authenticated Encryption with Associated Data (AEAD).
+ * 
+ * This header exposes functions that enable using the ELS for Authenticated Encryption with Associated Data (AEAD).
+ * The AEAD algorithm supported by ELS is AES in Galois/Counter Mode (GCM), as described in NIST Special Publication
+ * 800-38D.
+ */
+
+ /**
+ * @defgroup mcuxClEls_Aead mcuxClEls_Aead
+ * @brief This part of the @ref mcuxClEls driver supports Authenticated Encryption with Associated Data (AEAD).
+ * @ingroup mcuxClEls
+ * @{
+ */
+#ifndef MCUXCLELS_AEAD_H_
+#define MCUXCLELS_AEAD_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Aead_Macros mcuxClEls_Aead_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Aead
+ * @ingroup mcuxClEls_Aead
+ * @{
+ */
+/**
+ * @defgroup MCUXCLELS_AEAD_ MCUXCLELS_AEAD_
+ * @brief Defines macros used to initialize #mcuxClEls_AeadOption_t
+ * @ingroup mcuxClEls_Aead_Macros
+ * @{
+ */
+#define MCUXCLELS_AEAD_ENCRYPT ((uint8_t)0x00U) ///< Set #mcuxClEls_AeadOption_t.dcrpt to this value to encrypt data
+#define MCUXCLELS_AEAD_DECRYPT ((uint8_t)0x01U) ///< Set #mcuxClEls_AeadOption_t.dcrpt to this value to decrypt data
+
+#define MCUXCLELS_AEAD_STATE_IN_DISABLE ((uint8_t)0x00U) ///< Set #mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from ELS
+#define MCUXCLELS_AEAD_STATE_IN_ENABLE  ((uint8_t)0x01U) ///< Set #mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from the context
+
+#define MCUXCLELS_AEAD_LASTINIT_TRUE  ((uint8_t)0x01U)  ///< Set #mcuxClEls_AeadOption_t.lastinit to this value if this is the last call to init
+#define MCUXCLELS_AEAD_LASTINIT_FALSE ((uint8_t)0x00U)  ///< Set #mcuxClEls_AeadOption_t.lastinit to this value if this is not the last call to init
+
+#define MCUXCLELS_AEAD_EXTERN_KEY ((uint8_t)0x01U)  ///< Set #mcuxClEls_AeadOption_t.extkey to this value to use an external key
+#define MCUXCLELS_AEAD_INTERN_KEY ((uint8_t)0x00U)  ///< Set #mcuxClEls_AeadOption_t.extkey to this value to use a key from the ELS keystore
+
+#define MCUXCLELS_AEAD_ACPMOD_INIT    ((uint8_t)0x00U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Init mode. For internal use
+#define MCUXCLELS_AEAD_ACPMOD_AADPROC ((uint8_t)0x01U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Process Additional Authenticated Data mode. For internal use
+#define MCUXCLELS_AEAD_ACPMOD_MSGPROC ((uint8_t)0x02U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Process Message mode. For internal use
+#define MCUXCLELS_AEAD_ACPMOD_FINAL   ((uint8_t)0x03U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Finalize mode. For internal use
+
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+#define MCUXCLELS_AEAD_STATE_OUT_ENABLE  ((uint8_t)0x01U) ///< Set #mcuxClEls_AeadOption_t.acpsoe to this value to save the state to the context. For internal use
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+/**
+ * @}
+ */
+
+#define MCUXCLELS_AEAD_IV_BLOCK_SIZE  16U  ///< AES-GCM IV Granularity:  128 bit (16 bytes)
+#define MCUXCLELS_AEAD_AAD_BLOCK_SIZE 16U  ///< AES-GCM AAD Granularity: 128 bit (16 bytes)
+#define MCUXCLELS_AEAD_TAG_SIZE       16U  ///< tag size: Tag generation supports only a 128 bit wide tag (16 bytes)
+#define MCUXCLELS_AEAD_CONTEXT_SIZE   80U  ///< context size: 512 bit (64 bytes) + 16 bytes for finalize
+/**
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Aead_Types mcuxClEls_Aead_Types
+ * @brief Defines all types of @ref mcuxClEls_Aead
+ * @ingroup mcuxClEls_Aead
+ * @{
+ */
+/**
+ * @brief Command option bit field for #mcuxClEls_Aead_Init_Async, #mcuxClEls_Aead_UpdateAad_Async, #mcuxClEls_Aead_UpdateData_Async and #mcuxClEls_Aead_Finalize_Async.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_AeadOption_t word-wise
+    struct
+    {
+        uint32_t :1;          ///< RFU
+        uint32_t dcrpt :1;    ///< Defines if encryption or decryption shall be performed
+        uint32_t acpmod :2;   ///< This field is managed internally
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+        uint32_t acpsoe :1;   ///< This field is managed internally
+#else
+        uint32_t :1;          ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+        uint32_t acpsie :1;   ///< This field is managed internally
+        uint32_t msgendw :4;  ///< The size of the last data block (plain/cipher text) in bytes, without padding
+        uint32_t lastinit :1; ///< Defines whether this is the last call to init
+        uint32_t :2;          ///< RFU
+        uint32_t extkey :1;   ///< Defines whether an external key shall be used
+        uint32_t :18;         ///< RFU
+    } bits;                   ///< Access #mcuxClEls_AeadOption_t bit-wise
+} mcuxClEls_AeadOption_t;
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Aead_Functions mcuxClEls_Aead_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Aead
+ * @ingroup mcuxClEls_Aead
+ * @{
+ */
+
+/**
+ * @brief AES-GCM initialization
+ *
+ * This is the first stage of AEAD encryption/decryption. This generates the initial context out of the IV @p pIV and the key (@p pKey or @p keyIdx).
+ *
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]      options   The AEAD command options. For more information, see #mcuxClEls_AeadOption_t.
+ * @param[in]      keyIdx    Index of the key inside the ELS keystore
+ * @param[in]      pKey      Pointer to the key
+ * @param[in]      keyLength Size of @p pKey in bytes
+ * @param[in]      pIV       Pointer to memory area that contains the IV
+ * @param[in]      ivLength  Size of @p pIV in bytes, with padding
+ * @param    [out] pAeadCtx  Pointer to the memory area that receives the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+ *
+ * The properties of some parameters change with respect to selected options.
+ *
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY</dt>
+ *          <dd>@p keyIdx is ignored.
+ *
+ *          @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY</dt>
+ *          <dd>@p keyIdx must be a valid key index with the correct usage rights.
+ *
+ *          @p pKey and @p keyLength are ignored.</dd>
+ *  </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_Init_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Init_Async(
+    mcuxClEls_AeadOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pKey,
+    size_t keyLength,
+    uint8_t const * pIV,
+    size_t ivLength,
+    uint8_t * pAeadCtx
+    );
+
+/**
+ * @brief AES-GCM partial initialization
+ * 
+ * This is the first stage of AEAD encryption/decryption. This generates the initial context out of the IV @p pIV and the key (@p pKey or @p keyIdx).
+ * 
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]      options   The AEAD command options. For more information, see #mcuxClEls_AeadOption_t.
+ * @param[in]      keyIdx    Index of the key inside the ELS keystore
+ * @param[in]      pKey      Pointer to the key
+ * @param[in]      keyLength Size of @p pKey in bytes
+ * @param[in]      pIV       Pointer to memory area that contains the IV
+ * @param[in]      ivLength  Size of @p pIV in bytes, with padding
+ * @param    [out] pAeadCtx  Pointer to the memory area that receives the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+ * 
+ * The properties of some parameters change with respect to selected options.
+ * 
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY</dt>
+ *          <dd>@p keyIdx is ignored.
+ *
+ *          @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY</dt>
+ *          <dd>@p keyIdx must be a valid key index with the correct usage rights.
+ *
+ *          @p pKey and @p keyLength are ignored.</dd>
+ *
+ *      <dt>@p options.msgendw</dt>
+ *          <dd>This field is ignored</dd>
+ *  </dl></dd>
+ * </dl>
+ * 
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_PartialInit_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_PartialInit_Async(
+    mcuxClEls_AeadOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pKey,
+    size_t keyLength,
+    uint8_t const * pIV,
+    size_t ivLength,
+    uint8_t * pAeadCtx
+    );
+
+/**
+ * @brief AES-GCM update of the Additional Authenticated Data (AAD)
+ * 
+ * This is the second stage of AEAD encryption/decryption. This updates the internal authentication tag with the AAD.
+ * 
+ * #mcuxClEls_Aead_Init_Async must have been called before calling this function.
+ * 
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]      options   The AEAD command options. For more information, see #mcuxClEls_AeadOption_t.
+ * @param[in]      keyIdx    Index of the key inside the ELS keystore
+ * @param[in]      pKey      Pointer to the key
+ * @param[in]      keyLength Size of @p pKey in bytes
+ * @param[in]      pAad      Memory area that contains the AAD
+ * @param[in]      aadLength Length of the @p pAad in bytes with padding
+ * @param[in, out] pAeadCtx  Pointer to the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+ * 
+ * The properties of some parameters change with respect to selected options.
+ * 
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY</dt>
+ *          <dd>@p keyIdx is ignored.
+ *
+ *          @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY</dt>
+ *          <dd>@p keyIdx must be a valid key index with the correct usage rights.
+ *
+ *          @p pKey and @p keyLength are ignored.</dd>
+ *
+ *      <dt>@p options.msgendw</dt>
+ *          <dd>This field is ignored</dd>
+ *  </dl></dd>
+ * </dl>
+ * 
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_UpdateAad_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateAad_Async(
+    mcuxClEls_AeadOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pKey,
+    size_t keyLength,
+    uint8_t const * pAad,
+    size_t aadLength,
+    uint8_t * pAeadCtx
+    );
+
+/**
+ * @brief AES-GCM update of the encrypted data
+ * 
+ * This is the third stage of AEAD encryption/decryption. This processes the given plaintext (in case of encryption)
+ * or ciphertext (in case of decryption) and outputs the ciphertext (in case of encryption) or plaintext (in case of decryption).
+ * 
+ * #mcuxClEls_Aead_Init_Async, #mcuxClEls_Aead_UpdateAad_Async must have been called before calling this function.
+ *
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]      options     The AEAD command options. For more information, see #mcuxClEls_AeadOption_t.
+ * @param[in]      keyIdx      Index of the key inside the ELS keystore
+ * @param[in]      pKey        Pointer to the key
+ * @param[in]      keyLength   Size of @p pKey in bytes
+ * @param[in]      pInput      Pointer to the memory location of the data to be processed
+ * @param[in]      inputLength Size of @p pInput in bytes with padding
+ * @param    [out] pOutput     Pointer to the processed data memory location
+ * @param[in, out] pAeadCtx    Pointer to the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+ * 
+ * The properties of some parameters change with respect to selected options.
+ * 
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY</dt>
+ *          <dd>@p keyIdx is ignored.
+ *
+ *          @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY</dt>
+ *          <dd>@p keyIdx must be a valid key index with the correct usage rights.
+ *
+ *          @p pKey and @p keyLength are ignored.</dd>
+ *
+ *      <dt>@p options.msgendw</dt>
+ *          <dd>This field has to be set to the size of the last data block (plain/cipher text) in bytes, without padding.
+ *              In case the last block is a full block, this field has to be set to 0.</dd>
+ *  </dl></dd>
+ * </dl>
+ * 
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_UpdateData_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateData_Async(
+    mcuxClEls_AeadOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pKey,
+    size_t keyLength,
+    uint8_t const * pInput,
+    size_t inputLength,
+    uint8_t * pOutput,
+    uint8_t * pAeadCtx
+    );
+
+/**
+ * @brief AES-GCM final encryption/decryption
+ * 
+ * This is the fourth stage of AEAD encryption/decryption. This updates the authentication tag with the final data
+ * length block and outputs the tag at the desired location.
+ * 
+ * #mcuxClEls_Aead_Init_Async, #mcuxClEls_Aead_UpdateAad_Async and #mcuxClEls_Aead_UpdateData_Async must have been called
+ * before calling this function.
+ *
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]      options    The AEAD command options. For more information, see #mcuxClEls_AeadOption_t.
+ * @param[in]      keyIdx     Index of the key inside the ELS keystore
+ * @param[in]      pKey       Pointer to the key
+ * @param[in]      keyLength  Size of @p pKey in bytes
+ * @param[in]      aadLength  Length of the complete Additional Authenticated Data (AAD) in bytes, without padding.
+ * @param[in]      dataLength Length of the complete plaintext/ciphertext in bytes, without padding.
+ * @param    [out] pTag       Pointer where the resulting tag will be stored
+ * @param[in]      pAeadCtx   Pointer to the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+ * 
+ * The properties of some parameters change with respect to selected options.
+ * 
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY</dt>
+ *          <dd>@p keyIdx is ignored.
+ *
+ *          @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY</dt>
+ *          <dd>@p keyIdx must be a valid key index with the correct usage rights.
+ *
+ *          @p pKey and @p keyLength are ignored.</dd>
+ *
+ *      <dt>@p options.msgendw</dt>
+ *          <dd>This field is ignored</dd>
+ *  </dl></dd>
+ * </dl>
+ * 
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_Finalize_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Finalize_Async(
+    mcuxClEls_AeadOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pKey,
+    size_t keyLength,
+    size_t aadLength,
+    size_t dataLength,
+    uint8_t * pTag,
+    uint8_t * pAeadCtx
+    );
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_AEAD_H_ */
+
+/**
+ * @}
+ * 
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cipher.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cipher.h
new file mode 100644
index 0000000000..a0f3590971
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cipher.h
@@ -0,0 +1,239 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Cipher.h
+ * @brief ELS header for symmetric ciphers.
+ *
+ * This header exposes functions that enable using the ELS for symmetric encryption/decryption.
+ * The cipher algorithm supported by ELS is AES in the following modes:
+ * - Electronic Code Book (ECB) mode, 
+ * - Cipher Block Chaining (CBC) mode, and 
+ * - Counter (CTR) mode.
+ * Supported key sizes are 128, 192, and 256 bits.
+ */
+
+/**
+ * @defgroup mcuxClEls_Cipher mcuxClEls_Cipher
+ * @brief This part of the @ref mcuxClEls driver supports functionality for symmetric ciphers
+ * @ingroup mcuxClEls
+ * @{
+ */
+
+#ifndef MCUXCLELS_CIPHER_H_
+#define MCUXCLELS_CIPHER_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Cipher_Macros mcuxClEls_Cipher_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Cipher
+ * @ingroup mcuxClEls_Cipher
+ * @{
+ */
+
+/**
+ * @defgroup MCUXCLELS_CIPHER_ MCUXCLELS_CIPHER_
+ * @brief Defines valid options to be used by #mcuxClEls_CipherOption_t
+ * @ingroup mcuxClEls_Cipher_Macros
+ *
+ * Valid AES key sizes in bytes
+ * @{
+ */
+
+#define MCUXCLELS_CIPHER_ENCRYPT 0U                      ///< Set this option at #mcuxClEls_CipherOption_t.dcrpt to perform an encryption
+#define MCUXCLELS_CIPHER_DECRYPT 1U                      ///< Set this option at #mcuxClEls_CipherOption_t.dcrpt to perform a decryption
+
+#define MCUXCLELS_CIPHER_STATE_OUT_ENABLE  1U            ///< Set this option at #mcuxClEls_CipherOption_t.cphsoe to export the internal ELS state to @p pIV
+#define MCUXCLELS_CIPHER_STATE_OUT_DISABLE 0U            ///< Set this option at #mcuxClEls_CipherOption_t.cphsoe to not export the internal ELS state
+
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+#define MCUXCLELS_CIPHER_STATE_IN_ENABLE  1U             ///< Set this option at #mcuxClEls_CipherOption_t.cphsie to import an external ELS state from @p pIV
+#define MCUXCLELS_CIPHER_STATE_IN_DISABLE 0U             ///< Set this option at #mcuxClEls_CipherOption_t.cphsie to not import an external ELS state
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+
+#define MCUXCLELS_CIPHER_EXTERNAL_KEY 1U                 ///< Set this option at #mcuxClEls_CipherOption_t.extkey to use a key located in CPU memory provided by @p pKey
+#define MCUXCLELS_CIPHER_INTERNAL_KEY 0U                 ///< Set this option at #mcuxClEls_CipherOption_t.extkey to use a key located in ELS keystore privded by @p keyIdx
+
+#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB 0x00U    ///< Set this option at #mcuxClEls_CipherOption_t.cphmde to use AES engine in Electornic Code Book (ECB) mode
+#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC 0x01U    ///< Set this option at #mcuxClEls_CipherOption_t.cphmde to use AES engine in Cipher Block Chaining (CBC) mode
+#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR 0x02U    ///< Set this option at #mcuxClEls_CipherOption_t.cphmde to use AES engine in Counter (CTR) mode
+/**
+ * @}
+ */
+
+
+/**
+ * @ingroup mcuxClEls_Cipher_Macros
+ */
+#define MCUXCLELS_CIPHER_BLOCK_SIZE_AES   ((size_t) 16U) ///< Size of an AES input block: 128 bit (16 bytes)
+
+/**
+ * @defgroup MCUXCLELS_CIPHER_KEY_SIZE_AES_ MCUXCLELS_CIPHER_KEY_SIZE_AES_
+ * @brief Defines valid AES key sizes in bytes
+ * @ingroup mcuxClEls_Cipher_Macros
+ * @{
+ */
+
+#define MCUXCLELS_CIPHER_KEY_SIZE_AES_128 ((size_t) 16U) ///< Size of an AES128 key: 128 bit (16 bytes)
+#define MCUXCLELS_CIPHER_KEY_SIZE_AES_192 ((size_t) 24U) ///< Size of an AES192 key: 192 bit (24 bytes)
+#define MCUXCLELS_CIPHER_KEY_SIZE_AES_256 ((size_t) 32U) ///< Size of an AES192 key: 256 bit (32 bytes)
+/**
+ * @}
+ *
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Cipher_Types mcuxClEls_Cipher_Types
+ * @brief Defines all types of @ref mcuxClEls_Cipher
+ * @ingroup mcuxClEls_Cipher
+ * @{
+ */
+
+/**
+ * @brief Command option bit field for #mcuxClEls_Cipher_Async
+ *
+ * Bit field to configure #mcuxClEls_Cipher_Async. See @ref MCUXCLELS_CIPHER_ for possible options.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value;     ///< Accesses the bit field as a full word
+    } word;                 ///< Access #mcuxClEls_CipherOption_t word-wise
+    struct
+    {
+        uint32_t :1;        ///< RFU
+        uint32_t dcrpt :1;  ///< Define operation mode
+        uint32_t cphmde :2; ///< Define cipher mode
+        uint32_t cphsoe :1; ///< Define whether the ELS internal cipher state should be extracted to external memory or kept internally
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+        uint32_t cphsie :1; ///< Define whether an external provided cipher state should be imported from external memory
+        uint32_t :7;        ///< RFU
+#else
+        uint32_t :8;        ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+        uint32_t extkey :1; ///< Define whether an external key from memory or ELS internal key should be used
+        uint32_t :18;       ///< RFU
+    } bits;                 ///< Access #mcuxClEls_CipherOption_t bit-wise
+} mcuxClEls_CipherOption_t;
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Cipher_Functions mcuxClEls_Cipher_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Cipher
+ * @ingroup mcuxClEls_Cipher
+ * @{
+ */
+
+ /**
+ * @brief Performs AES encryption/decryption.
+ * 
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ *
+ * Performs an AES encryption/decryption. Call #mcuxClEls_WaitForOperation to complete the operation.
+ * @param[in]       options     Encryption/decryption command options. For detailed information, see #mcuxClEls_CipherOption_t.
+ * @param[in]       keyIdx      Index of the key inside the ELS keystore. See parameter properties section in function description.
+ * @param[in]       pKey        Memory area that contains the key. See parameter properties section in function description.
+ * @param[in]       keyLength   Size of @p pKey in bytes. Must be a valid key size of @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_. See parameter properties section in function description.
+ * @param[in]       pInput      Pointer to the input data to be encrypted/decrypted. Padding must be already applied.
+ * @param[in]       inputLength Size of @p pInput in bytes, must be a multiple of the block size.
+ * @param[in, out]  pIV         A pointer to the memory location which contains/receives the IV/state of cipher. See parameter properties section in function description.
+ * @param[out]      pOutput     Pointer to the output buffer to store encrypted/decrypted data.
+ *
+ * The properties of some parameters change with respect to selected options.
+ *
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.cphmde == #MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB</dt>
+ *          <dd>@p pIV is ignored.
+ *
+ *      <dt>@p options.cphmde == #MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC</dt>
+ *          <dd>@p pIV must be set to the IV (when encrypting the first block) or to the last block of the ciphertext of the previous operation.
+ *          ELS will always read and write to this location.
+ *
+ * @ifnot ELS_NO_INTERNAL_STATE_FLAGS
+ *          @p options.cphsie is ignored.
+ * @endif
+ *
+ *          @p options.cphsoe is ignored.</dd>
+ *
+ *      <dt>@p options.cphmde == #MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR</dt>
+ *          <dd>@p pIV must be set to the IV (when encrypting the first block) or to the state output of the previous
+ *          encryption/decryption operation. ELS will write to this location if @p options.cphsoe == #MCUXCLELS_CIPHER_STATE_OUT_ENABLE.</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_CIPHER_EXTERNAL_KEY</dt>
+ *          <dd>@p keyIdx is ignored.</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_CIPHER_INTERNAL_KEY</dt>
+ *          <dd>@p pKey is ignored.
+ *
+ *          @p keyLength is ignored.</dd>
+ *
+ *  </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Cipher_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cipher_Async(
+    mcuxClEls_CipherOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pKey,
+    size_t keyLength,
+    uint8_t const * pInput,
+    size_t inputLength,
+    uint8_t * pIV,
+    uint8_t * pOutput
+    );
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_CIPHER_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cmac.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cmac.h
new file mode 100644
index 0000000000..7bb8b94885
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cmac.h
@@ -0,0 +1,191 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Cmac.h
+ * @brief ELS header for CMAC support.
+ * This header exposes functions that enable using the ELS for the generation of cipher-based message authentication
+ * codes (CMAC).
+ * The supported cipher algorithm is AES-128 and AES-256.
+ */
+
+/**
+ * @defgroup mcuxClEls_Cmac mcuxClEls_Cmac
+ * @brief This part of the @ref mcuxClEls driver supports functionality for cipher-based message authentication codes (CMAC).
+ * @ingroup mcuxClEls
+ * @{
+ */
+
+#ifndef MCUXCLELS_CMAC_H_
+#define MCUXCLELS_CMAC_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * MACROS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Cmac_Macros mcuxClEls_Cmac_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Cmac
+ * @ingroup mcuxClEls_Cmac
+ * @{
+ */
+
+/**
+ * @defgroup MCUXCLELS_CMAC_KEY_SIZE_ MCUXCLELS_CMAC_KEY_SIZE_
+ * @brief Valid CMAC key sizes in bytes
+ * @ingroup mcuxClEls_Cmac_Macros
+ * @{ */
+#define MCUXCLELS_CMAC_KEY_SIZE_128 ((size_t) 16U) ///< Size of 128 bit CMAC key (16 bytes)
+#define MCUXCLELS_CMAC_KEY_SIZE_256 ((size_t) 32U) ///< Size of 256 bit CMAC key (32 bytes)
+/** @} */
+
+/**
+ * @defgroup MCUXCLELS_CMAC_ MCUXCLELS_CMAC_
+ * @brief Option values for #mcuxClEls_CmacOption_t
+ * @ingroup mcuxClEls_Cmac_Macros
+ * @{ */
+#define MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE  1U ///< Set #mcuxClEls_CmacOption_t.extkey to this value to use an external key
+#define MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE 0U ///< Set #mcuxClEls_CmacOption_t.extkey to this value to use a key from the ELS keystore
+#define MCUXCLELS_CMAC_INITIALIZE_DISABLE   0U ///< Set #mcuxClEls_CmacOption_t.initialize to this value if the message chunk does not include the first block of the message
+#define MCUXCLELS_CMAC_INITIALIZE_ENABLE    1U ///< Set #mcuxClEls_CmacOption_t.initialize to this value if the message chunk includes the first block of the message
+#define MCUXCLELS_CMAC_FINALIZE_DISABLE     0U ///< Set #mcuxClEls_CmacOption_t.finalize to this value if the message chunk does not include the last block of the message
+#define MCUXCLELS_CMAC_FINALIZE_ENABLE      1U ///< Set #mcuxClEls_CmacOption_t.finalize to this value if the message chunk includes the last block of the message
+/**
+ * @}
+ */
+
+#define MCUXCLELS_CMAC_OUT_SIZE ((size_t) 16U) ///< Size of CMAC output: 128 bit (16 bytes)
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Cmac_Types mcuxClEls_Cmac_Types
+ * @brief Defines all types of @ref mcuxClEls_Cmac
+ * @ingroup mcuxClEls_Cmac
+ * @{
+ */
+/**
+ * @brief Command option bit field for #mcuxClEls_Cmac_Async.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_CmacOption_t word-wise
+    struct
+    {
+        uint32_t initialize : 1; ///< Request initial processing for the first block of the message
+        uint32_t finalize : 1;   ///< Request final processing for the last block of the message
+        uint32_t soe : 1;        ///< This field is managed internally
+        uint32_t sie : 1;        ///< This field is managed internally
+        uint32_t :9;             ///< RFU
+        uint32_t extkey :1;      ///< An external key should be used
+        uint32_t :18;            ///< RFU
+    } bits;                      ///< Access #mcuxClEls_CmacOption_t bit-wise
+} mcuxClEls_CmacOption_t;
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Cmac_Functions mcuxClEls_Cmac_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Cmac
+ * @ingroup mcuxClEls_Cmac
+ * @{
+ */
+/**
+ * @brief Performs CMAC with AES-128 or AES-256
+ * 
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]      options     The command options. For more information, see #mcuxClEls_CmacOption_t.
+ * @param[in]      keyIdx      The CMAC key index
+ * @param[in]      pKey        Pointer to the padded CMAC key
+ * @param[in]      keyLength   Size of @p pKey in bytes. Must be a @ref MCUXCLELS_CMAC_KEY_SIZE_ "valid CMAC key size". See the parameter properties section in the function description.
+ * @param[in]      pInput      Pointer to a memory location which contains the data, padded via SP 800-38b standard, to be authenticated
+ * @param[in]      inputLength Size of @p pInput in bytes before padding
+ * @param[in, out] pMac        Pointer to the CMAC command state input/output. See the parameter properties section in the function description.
+ * 
+ * The properties of some parameters change with respect to selected options.
+ *
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.extkey == #MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE</dt>
+ *          <dd>@p keyIdx is ignored.</dd>
+ *
+ *      <dt>@p options.extkey == #MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE</dt>
+ *          <dd>@p pKey is ignored.
+ *
+ *          @p keyLength is ignored.</dd>
+ * 
+ *      <dt>(@p options.finalize == #MCUXCLELS_CMAC_FINALIZE_DISABLE)</dt>
+ *          <dd>The intermediate state is written to @p pMac. </dd>
+ * 
+ *      <dt>@p options.finalize == #MCUXCLELS_CMAC_FINALIZE_ENABLE</dt>
+ *          <dd>The resulting MAC is written to @p pMac.
+ * 
+ *          @p options.soe is ignored.</dd>
+ *  </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if an invalid parameter was specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Cmac_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cmac_Async(
+    mcuxClEls_CmacOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pKey,
+    size_t keyLength,
+    uint8_t const * pInput,
+    size_t inputLength, 
+    uint8_t * pMac
+    );
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_CMAC_H_ */
+
+/**
+ * @}
+ * 
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Common.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Common.h
new file mode 100644
index 0000000000..61c0244eb0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Common.h
@@ -0,0 +1,848 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Common.h
+ * @brief ELS header for common functionality.
+ *
+ * This header exposes functions that support hardware state management for other ELS commands.
+ */
+
+/**
+ * @defgroup mcuxClEls_Common mcuxClEls_Common
+ * @brief This part of the @ref mcuxClEls driver supports common functionality
+ * @ingroup mcuxClEls
+ * @{
+ */
+#ifndef MCUXCLELS_COMMON_H_
+#define MCUXCLELS_COMMON_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Types.h> // Common types
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup mcuxClEls_Common_Macros mcuxClEls_Common_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Common
+ * @ingroup mcuxClEls_Common
+ * @{
+ */
+
+#define MCUXCLELS_API    ///< Marks a function as a public API function of the mcuxClEls component
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+
+#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
+  #define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_CompareDmaFinalOutputAddress)
+#else
+  #define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN (0u)
+#endif
+
+
+/**
+ * @defgroup mcuxClEls_InterruptOptionEn_t_Macros mcuxClEls_InterruptOptionEn_t
+ * @brief Defines interrupt enable option values
+ * @ingroup mcuxClEls_Common_Macros
+ * @{
+ */
+#define MCUXCLELS_ELS_INTERRUPT_ENABLE              (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.elsint to allow ELS to trigger an interrupt
+#define MCUXCLELS_ELS_INTERRUPT_DISABLE             (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.elsint to prevent ELS from triggering an interrupt
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+#define MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_ENABLE  ((uint32_t) 1U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.gdetint to allow the Glitch Detector to trigger an interrupt
+#define MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_DISABLE ((uint32_t) 0U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.gdetint to prevent the Glitch Detector from triggering an interrupt
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+/**@}*/
+
+/**
+ * @defgroup mcuxClEls_InterruptOptionRst_t_Macros mcuxClEls_InterruptOptionRst_t
+ * @brief Defines interrupt reset option values
+ * @ingroup mcuxClEls_Common_Macros
+ * @{
+ */
+#define MCUXCLELS_ELS_RESET_CLEAR             (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.elsint to reset the ELS interrupt flag
+#define MCUXCLELS_ELS_RESET_KEEP              (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.elsint to keep the ELS interrupt flag
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+#define MCUXCLELS_GLITCH_DETECTOR_RESET_CLEAR ((uint32_t) 1U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.gdetint to reset the Glitch Detector interrupt flag
+#define MCUXCLELS_GLITCH_DETECTOR_RESET_KEEP  ((uint32_t) 0U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.gdetint to keep the Glitch Detector interrupt flag
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+/**@}*/
+
+/**
+ * @defgroup mcuxClEls_InterruptOptionSet_t_Macros mcuxClEls_InterruptOptionSet_t
+ * @brief Defines interrupt set option values
+ * @ingroup mcuxClEls_Common_Macros
+ * @{
+ */
+#define MCUXCLELS_ELS_INTERRUPT_SET          (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.elsint to set the ELS interrupt flag
+#define MCUXCLELS_ELS_INTERRUPT_KEEP         (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.elsint to leave the ELS interrupt flag unchanged
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+#define MCUXCLELS_GLITCH_DETECTOR_NEG_SET    (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_neg to set the negative Glitch Detector interrupt flag
+#define MCUXCLELS_GLITCH_DETECTOR_NEG_KEEP   (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_neg to leave the negative Glitch Detector interrupt flag unchanged
+#define MCUXCLELS_GLITCH_DETECTOR_POS_SET    (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_pos to set the positive Glitch Detector interrupt flag
+#define MCUXCLELS_GLITCH_DETECTOR_POS_KEEP   (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_pos to leave the positive Glitch Detector interrupt flag unchanged
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+/**@}*/
+
+/**
+ * @defgroup MCUXCLELS_ERROR_FLAGS_ MCUXCLELS_ERROR_FLAGS_
+ * @brief Options for error flag clearing
+ * @ingroup mcuxClEls_Common_Macros
+ * @{
+ */
+#define MCUXCLELS_ERROR_FLAGS_KEEP  ((mcuxClEls_ErrorHandling_t) 0x0u) ///< Set this option at #mcuxClEls_ErrorHandling_t to not clear any error flags
+#define MCUXCLELS_ERROR_FLAGS_CLEAR ((mcuxClEls_ErrorHandling_t) 0x1u) ///< Set this option at #mcuxClEls_ErrorHandling_t to clear all ELS error flags
+/**@}*/
+
+/**
+ * @defgroup MCUXCLELS_RESET_ MCUXCLELS_RESET_
+ * @brief Options for reset handling
+ * @ingroup mcuxClEls_Common_Macros
+ * @{
+ */
+#define MCUXCLELS_RESET_DO_NOT_CANCEL ((mcuxClEls_ResetOption_t) 0x0u) ///< Set this option at #mcuxClEls_ResetOption_t to abort the requested command if another ELS operation is still running
+#define MCUXCLELS_RESET_CANCEL        ((mcuxClEls_ResetOption_t) 0x1u) ///< Set this option at #mcuxClEls_ResetOption_t to execute the requested command even if another ELS operation is still running
+/**@}*/
+
+/**
+ * @defgroup MCUXCLELS_STATUS_PPROT_ MCUXCLELS_STATUS_PPROT_
+ * @brief Values for the privilege/security level of ELS commands
+ *
+ * Note that some keys and memory areas may only be accessible when ELS is on a certain privilege/security level.
+ *
+ * The default value, before any command has been executed, is #MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE.
+ *
+ * @ingroup mcuxClEls_Common_Macros
+ * @{
+ */
+#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE    ((uint32_t) 0x0u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged secure mode
+#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE      ((uint32_t) 0x1u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged secure mode
+#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE ((uint32_t) 0x2u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged non-secure mode
+#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE   ((uint32_t) 0x3u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged non-secure mode
+/**@}*/
+
+/**
+ * @defgroup MCUXCLELS_STATUS_ECDSAVFY_ MCUXCLELS_STATUS_ECDSAVFY_
+ * @brief ECDSA verify check values
+ * @ingroup mcuxClEls_Common_Macros
+ * @{
+ */
+#define MCUXCLELS_STATUS_ECDSAVFY_NORUN  ((uint32_t) 0x0u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that no ECDSA verify operation has been executed
+#define MCUXCLELS_STATUS_ECDSAVFY_FAIL   ((uint32_t) 0x1u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification failed
+#define MCUXCLELS_STATUS_ECDSAVFY_OK     ((uint32_t) 0x2u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification passed
+#define MCUXCLELS_STATUS_ECDSAVFY_ERROR  ((uint32_t) 0x3u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that an error has occurred
+/**@}*/
+
+/**
+ * @defgroup MCUXCLELS_STATUS_DRBGENTLVL_ MCUXCLELS_STATUS_DRBGENTLVL_
+ * @brief Constants for Entropy quality of the current DRBG instance
+ * @ingroup mcuxClEls_Common_Macros
+ * @{ */
+#define MCUXCLELS_STATUS_DRBGENTLVL_NONE ((uint32_t) 0x0u) ///< This value of #mcuxClEls_HwState_t.drbgentlvl means that the DRBG is not running
+#define MCUXCLELS_STATUS_DRBGENTLVL_LOW  ((uint32_t) 0x1u) ///< This value of #mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with a low security strength (sufficient for commands with a low DRBG security strength requirement, see the function description to check which level is required)
+#define MCUXCLELS_STATUS_DRBGENTLVL_HIGH ((uint32_t) 0x2u) ///< This value of #mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with 128 bits of security strength (sufficient for commands with a high DRBG security strength requirement, see the function description to check which level is required)
+/** @} */
+
+#ifdef MCUXCL_FEATURE_ELS_LOCKING
+/**
+ * @defgroup MCUXCLELS_LOCKING_ MCUXCLELS_LOCKING_
+ * @brief Constants for ELS locking feature
+ * @ingroup mcuxClEls_Common_Macros
+ * @{ */
+#define MCUXCLELS_MASTER_UNLOCK_ANY         ((uint32_t) 0x1Fu) ///< Any bus master ID can override ELS lock
+/** @} */
+#endif /* MCUXCL_FEATURE_ELS_LOCKING */
+
+
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+
+/**
+ * @defgroup mcuxClEls_Common_Types mcuxClEls_Common_Types
+ * @brief Defines all types of @ref mcuxClEls_Common
+ * @ingroup mcuxClEls_Common
+ * @{
+ */
+
+/**
+ * @brief Result type of #mcuxClEls_GetHwVersion
+ *
+ * Contains the ELS version value.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_HwVersion_t word-wise
+    struct
+    {
+        uint32_t revision :4; ///< Revision number
+        uint32_t minor :8;    ///< Minor version
+        uint32_t major :4;    ///< Major version
+#ifndef MCUXCL_FEATURE_ELS_GET_FW_VERSION
+        uint32_t level :4;    ///< Release level version
+        uint32_t :12;         ///< RFU
+#else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
+        uint32_t fw_revision :4; ///< Firmware Revision number
+        uint32_t fw_minor :8;    ///< Firmware Minor version
+        uint32_t fw_major :4;    ///< Firmware Major version
+#endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
+    } bits;                   ///< Access #mcuxClEls_HwVersion_t bit-wise
+} mcuxClEls_HwVersion_t;
+
+/**
+ * @brief Result type of #mcuxClEls_GetHwState
+ *
+ * Contains ELS status information.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_HwState_t word-wise
+    struct
+    {
+        uint32_t busy :1;       ///< ELS is busy
+        uint32_t irq :1;        ///< ELS interrupt activated
+        uint32_t err :1;        ///< ELS is in error state
+        uint32_t prngready :1;  ///< ELS PRNG is seeded and ready to use
+        uint32_t ecdsavfy :2;   ///< ECDSA verify operation state (For possible values of this field, see @ref MCUXCLELS_STATUS_ECDSAVFY_)
+        uint32_t pprot :2;      ///< The privilege/security level of the most recently started ELS command (For possible values of this field, see @ref MCUXCLELS_STATUS_PPROT_)
+        uint32_t drbgentlvl :2; ///< Entropy quality of the current DRBG instance (For possible values of this field, see @ref MCUXCLELS_STATUS_DRBGENTLVL_)
+        uint32_t dtrng_busy: 1; ///< Indicates the DTRNG is gathering entropy
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+        uint32_t gdet_pos :1;   ///< Glitch detector interrupt activated (positive)
+        uint32_t gdet_neg :1;   ///< Glitch detector interrupt activated (negative)
+#else
+        uint32_t :2;            ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+        uint32_t :3;            ///< RFU
+#ifdef MCUXCL_FEATURE_ELS_LOCKING
+        uint32_t els_locked :1; ///< ELS is locked
+#else
+        uint32_t :1;            ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_LOCKING */
+        uint32_t :15;           ///< RFU
+    } bits;                     ///< Access #mcuxClEls_HwState_t bit-wise
+} mcuxClEls_HwState_t;
+
+/**
+ * @brief Type to handle ELS error clearing options
+ *
+ * For possible values, see @ref MCUXCLELS_ERROR_FLAGS_.
+ */
+typedef uint32_t mcuxClEls_ErrorHandling_t;
+
+/**
+ * @brief Type to handle ELS reset options
+ *
+ * For possible values, see @ref MCUXCLELS_RESET_.
+ */
+typedef uint32_t mcuxClEls_ResetOption_t;
+
+/**
+ * @brief Command option type for #mcuxClEls_SetIntEnableFlags and #mcuxClEls_GetIntEnableFlags
+ *
+ * Used to get/set ELS interrupt enable options.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_InterruptOptionEn_t word-wise
+    struct
+    {
+        uint32_t elsint :1;  ///< Whether ELS interrupt should be used. (For possible values of this field, see @ref mcuxClEls_InterruptOptionEn_t_Macros)
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+        uint32_t gdetint :1; ///< Whether Glitch detector interrupt should be used. (For possible values of this field, see @ref mcuxClEls_InterruptOptionEn_t_Macros)
+#else
+        uint32_t :1;         ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+        uint32_t :30;        ///< RFU
+    } bits;                  ///< Access #mcuxClEls_InterruptOptionEn_t bit-wise
+} mcuxClEls_InterruptOptionEn_t;
+
+/**
+ * @brief Type to control which ELS interrupts should be reset when calling #mcuxClEls_ResetIntFlags
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_InterruptOptionRst_t word-wise
+    struct
+    {
+        uint32_t elsint :1;  ///< Whether ELS interrupt should be reset. (For possible values of this field, see @ref mcuxClEls_InterruptOptionRst_t_Macros)
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+        uint32_t gdetint :1; ///< Whether Glitch detector interrupt should be reset. (For possible values of this field, see @ref mcuxClEls_InterruptOptionRst_t_Macros)
+#else
+        uint32_t :1;         ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+        uint32_t :30;        ///< RFU
+    } bits;                  ///< Access #mcuxClEls_InterruptOptionRst_t bit-wise
+} mcuxClEls_InterruptOptionRst_t;
+
+/**
+ * @brief Type to control which ELS interrupts should be set when calling #mcuxClEls_SetIntFlags
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_InterruptOptionSet_t word-wise
+    struct
+    {
+        uint32_t elsint :1;     ///< Whether ELS interrupt should be set. (For possible values of this field, see @ref mcuxClEls_InterruptOptionSet_t_Macros)
+#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+        uint32_t gdetint_neg :1;///< Whether Glitch detector neg interrupt should be set. (For possible values of this field, see @ref mcuxClEls_InterruptOptionSet_t_Macros)
+        uint32_t gdetint_pos :1;///< Whether Glitch detector pos interrupt should be set. (For possible values of this field, see @ref mcuxClEls_InterruptOptionSet_t_Macros)
+#else
+        uint32_t :2;            ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
+        uint32_t :29;           ///< RFU
+    } bits;                     ///< Access #mcuxClEls_InterruptOptionSet_t bit-wise
+} mcuxClEls_InterruptOptionSet_t;
+
+/**
+ * @brief Result type of #mcuxClEls_GetHwConfig
+ *
+ * Contains ELS configuration values.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_InterruptOptionSet_t word-wise
+    struct
+    {
+        uint32_t ciphersup :1;       ///< Indicates whether the cipher command is supported
+        uint32_t authciphersup :1;   ///< Indicates whether the auth_cipher command is supported
+        uint32_t ecsignsup :1;       ///< Indicates whether the ecsign command is supported
+        uint32_t ecvfysup :1;        ///< Indicates whether the ecvfy command is supported
+        uint32_t eckxchsup :1;       ///< Indicates whether the dhkey_xch command is supported
+        uint32_t keygensup :1;       ///< Indicates whether the keygen command is supported
+        uint32_t keyinsup :1;        ///< Indicates whether the keyin command is supported
+        uint32_t keyoutsup :1;       ///< Indicates whether the keyout command  is supported
+        uint32_t kdeletesup :1;      ///< Indicates whether the kdelete command is supported
+        uint32_t keyprovsup :1;      ///< Indicates whether the keyprov command is supported
+        uint32_t ckdfsup :1;         ///< Indicates whether the ckdf command is supported
+        uint32_t hkdfsup :1;         ///< Indicates whether the hkdf command is supported
+        uint32_t tlsinitsup :1;      ///< Indicates whether the tls_init command is supported
+        uint32_t hashsup :1;         ///< Indicates whether the hash command is supported
+        uint32_t hmacsup :1;         ///< Indicates whether the hmac command is supported
+        uint32_t cmacsup :1;         ///< Indicates whether the cmac command is supported
+        uint32_t drbgreqsup :1;      ///< Indicates whether the drbg_req command is supported
+        uint32_t drbgtestsup :1;     ///< Indicates whether the drbg_test command is supported
+        uint32_t dtrgncfgloadsup :1; ///< Indicates whether the dtrng_cfg_load command is is supported
+        uint32_t dtrngevalsup :1;    ///< Indicates whether the dtrng_eval command is supported
+        uint32_t gdetcfgloadsup :1;  ///< Indicates whether the gdet_cfg_load command is supported
+        uint32_t gdettrimsup :1;     ///< Indicates whether the gdet_trim command is supported
+        uint32_t :10;                ///< RFU
+    } bits;                          ///< Access #mcuxClEls_InterruptOptionSet_t bit-wise
+} mcuxClEls_HwConfig_t;
+
+#define drbgreqsub drbgreqsup ///< Deprecated name for #mcuxClEls_HwConfig_t.drbgreqsup
+
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Common_Functions mcuxClEls_Common_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Common
+ * @ingroup mcuxClEls_Common
+ * @{
+ */
+/**
+ * @brief Determines the version of the underlying ELS hardware IP.
+ *
+ * @attention This header was delivered as part of a CLNS release which is compatible with a specific ELS hardware IP version.
+ *
+ * @param[out] result Pointer which will be filled with the ELS hardware version
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwVersion)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwVersion(
+    mcuxClEls_HwVersion_t * result
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_HWCONFIG
+/**
+ * @brief Determines the hardware configuration of the underlying ELS hardware IP.
+ *
+ * @param[out] result Pointer which will be filled with the ELS hardware configuration
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwConfig)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwConfig(
+    mcuxClEls_HwConfig_t * result
+    );
+#endif /* MCUXCL_FEATURE_ELS_HWCONFIG */
+
+/**
+ * @brief Determines the current state of the ELS.
+ *
+ * @param[out] result Pointer which will be filled with the ELS status information
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwState)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwState(
+    mcuxClEls_HwState_t * result
+    );
+
+/**
+ * @brief Enables the ELS.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK_WAIT
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK_WAIT
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Enable_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Enable_Async(
+    void
+    );
+
+/**
+ * @brief Perform a synchronous reset of the ELS.
+ *
+ * This means that:
+ * - any running ELS command will be stopped,
+ * - all errors will be cleared,
+ * - all keys will be deleted,
+ * - any RNG entropy will be discarded,
+ * - the glitch detector will be reset and
+ * - the run-time fingerprint will be restored to its default value.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in] options A value indicating whether any running ELS operations shall be canceled
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ *
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the reset
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Reset_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Reset_Async(
+    mcuxClEls_ResetOption_t options
+    );
+
+/**
+ * @brief Disable the ELS.
+ *
+ * This is useful as a power saving mechanism.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Disable)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Disable(
+    void
+);
+
+/**
+ * @brief Set interrupt enable flags.
+ *
+ * @param[in] options The command options, determining which interrupts should be enabled or disabled. For more information, see #mcuxClEls_InterruptOptionEn_t.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetIntEnableFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntEnableFlags(
+    mcuxClEls_InterruptOptionEn_t options
+    );
+
+/**
+ * @brief Get interrupt enable flags.
+ *
+ * @param[out] result Pointer which is filled with the configuration of the interrupts enable register.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetIntEnableFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetIntEnableFlags(
+    mcuxClEls_InterruptOptionEn_t * result
+    );
+
+/**
+ * @brief Clear the interrupt status register.
+ *
+ * @param[in] options The command options, determining which interrupt status bits should be cleared. For more information, see #mcuxClEls_InterruptOptionRst_t.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ResetIntFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetIntFlags(
+    mcuxClEls_InterruptOptionRst_t options
+    );
+
+/**
+ * @brief Set the interrupt status register, for debug and testing purposes.
+ *
+ * @param[in] options The command options, determining which interrupt status bits should be set. For more information, see #mcuxClEls_InterruptOptionSet_t.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetIntFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntFlags(
+    mcuxClEls_InterruptOptionSet_t options
+    );
+
+/**
+ * @brief Wait for an ELS operation and optionally clear the error status.
+ *
+ * If an ELS operation is active, this function waits for completion of that operation. For this, the
+ * busy flag of ELS is polled. Additionally, this function checks and returns any applicable error indication.
+ * If no operation is active, the function returns immediately.
+ *
+ * @param[in] errorHandling Define if error flags shall be cleared.
+ *
+ * @retval #MCUXCLELS_STATUS_OK if the last operation was successful, or no operation was active
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_WaitForOperation)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_WaitForOperation(
+    mcuxClEls_ErrorHandling_t errorHandling
+    );
+
+/**
+ * @brief Await the completion of an ELS operation for a limited amount of time and optionally clear the error status.
+ *
+ * If an ELS operation is active, this function waits for completion of that operation until a counter expires.
+ * For this, the busy flag of ELS is polled. The counting mechanism behaves like a simple for-loop from
+ * @p counterLimit to one. This counter does not have a well-defined relationship to real-world time.
+ * Additionally, this function checks and returns any applicable error indication.
+ * If no operation is active, the function returns immediately.
+ *
+ * @param[in] counterLimit The limit of the wait counter.
+ * @param[in] errorHandling Define if error flags shall be cleared.
+ *
+ * @retval #MCUXCLELS_STATUS_OK if the last operation was successful, or no operation was active
+ * @retval #MCUXCLELS_STATUS_SW_COUNTER_EXPIRED if the counter expired while waiting for the operation to complete
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_LimitedWaitForOperation)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_LimitedWaitForOperation(
+    uint32_t counterLimit,
+    mcuxClEls_ErrorHandling_t errorHandling
+    );
+
+/**
+ * @brief Resets all error flags that have been set by a previous operation.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ResetErrorFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetErrorFlags(
+    void);
+
+/**
+ * @brief Get the last ELS error code and optionally clear the error status.
+ *
+ * @param[in] errorHandling Define if error flags shall be cleared.
+ *
+ * @retval #MCUXCLELS_STATUS_OK 	if the last operation was successful or no operation was active
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetErrorCode)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorCode(
+    mcuxClEls_ErrorHandling_t errorHandling
+    );
+
+/**
+ * @brief Get the last ELS error code and level and optionally clear the error status.
+ *
+ * @param[in]  errorHandling    Define if error flags shall be cleared.
+ * @param[out] errorLevel       Pointer to the location that will receive the value of the error level.
+ *
+ * @retval #MCUXCLELS_STATUS_OK  if the last operation was successful or no operation was active
+ * @retval #MCUXCLELS_STATUS_    if the last operation resulted in an error
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetErrorLevel)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorLevel(
+    mcuxClEls_ErrorHandling_t errorHandling,
+    uint32_t *errorLevel
+    );
+
+/**
+ * @brief Set the random start delay for AES based operations. This impacts mcuxClEls_Aead_*, mcuxClEls_Cipher_*, mcuxClEls_Cmac_*, ncpClEls_Ckdf_*, mcuxClEls_KeyImport_Async, mcuxClEls_KeyExport_Async
+ *
+ * @param[in] startDelay Define the max random start delay. Acceptable values are a power of 2 minus one, starting from 0 to 1023 (0, 1, 3, 7, ..., 1023).
+ *
+ * @retval #MCUXCLELS_STATUS_OK if the operation was successful
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetRandomStartDelay)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetRandomStartDelay(
+    uint32_t startDelay
+    );
+
+/**
+ * @brief Get the random start delay for AES based operations.
+ *
+ * @param[out] startDelay Pointer to store random start delay configuration.
+ *
+ * @retval #MCUXCLELS_STATUS_OK if the operation was successful
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetRandomStartDelay)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetRandomStartDelay(
+    uint32_t * startDelay
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_LOCKING
+/**
+ * @brief Lock ELS to a session
+ *
+ * This operation locks the ELS, when the lock is obtained a nonzero value will be stored in @p sessionId, and the PPROT and bus Master ID
+ * of the locking command will be recorded. Subsequent unlocking can only be done by one of the following:
+ *      1.  ELS reset
+ *      2.  Normal unlock: calling #mcuxClEls_ReleaseLock with the correct @p sessionId, from the same bus Master ID and using the same PPROT settings.
+ *      3.  Privileged unlock: calling #mcuxClEls_ReleaseLock with any value of @p sessionId, from the bus Master ID set with the #mcuxClEls_SetMasterUnlock
+ *          command and PPROT settings 'secure privileged'.
+ * While ELS is locked read access is only permitted to ELS_STATUS and ELS_SESSION_ID and writes are only permitted to ELS_RESET, except for accesses that
+ * have the same bus Master ID and PPROT settings.
+ *
+ * @param[out] pSessionId  The session identifier assigned to the lock, it is required to unlock the session, it will be zero when a lock could not be obtained.
+ *
+ * @retval #MCUXCLELS_STATUS_OK                  if the operation was successful
+ * @retval #MCUXCLELS_STATUS_SW_LOCKING_FAILED   if the operation was not successful
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetLock)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLock(
+    uint32_t * pSessionId
+    );
+
+/**
+ * @brief Release ELS lock for the session
+ *
+ * This operation unlocks the ELS when following conditions are met:
+ *      1.  Normal unlock: providing the correct @p sessionId, from the same bus Master ID and using the same PPROT settings.
+ *      2.  Privileged unlock: providing any value of @p sessionId, from the bus Master ID set with the #mcuxClEls_SetMasterUnlock command
+ *          and PPROT settings 'secure privileged'.
+ * Invalid attempts to unlock ELS will result in a bus error.
+ *
+ * @param[in] sessionId  The session identifier obtained while locking ELS
+ *
+ * @retval #MCUXCLELS_STATUS_OK   if the operation was successful
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ReleaseLock)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ReleaseLock(
+    uint32_t sessionId
+    );
+
+/**
+ * @brief Check if ELS is locked
+ *
+ * This operation returns the locking status of ELS.
+ *
+ * @retval #MCUXCLELS_STATUS_OK                  if the operation was successful and ELS is not locked
+ * @retval #MCUXCLELS_STATUS_SW_STATUS_LOCKED    if the operation was successful and ELS is locked
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_IsLocked)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_IsLocked(void);
+
+/**
+ * @brief Set the bus master ID that can unlock ELS
+ *
+ * This operation sets the bus master ID of the master that can override ELS lock. This command can only be executed once after reset.
+ * Invalid attempts to set the bus master ID will result in a bus error.
+ *
+ * @param[in] masterId  The bus master identifier that can override the ELS lock. Special value #MCUXCLELS_MASTER_UNLOCK_ANY allows any bus master identifier to override the ELS lock.
+ *
+ * @retval #MCUXCLELS_STATUS_OK                   if the operation was successful
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetMasterUnlock)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetMasterUnlock(
+    uint32_t masterId
+    );
+
+#endif /* MCUXCL_FEATURE_ELS_LOCKING */
+
+
+#ifdef MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK
+/**
+ * @brief Reads back the last address processed by the ELS DMA (security feature)
+ *
+ * @param[out] pLastAddress	Pointer to the last address read/written by the ELS DMA
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetLastDmaAddress)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLastDmaAddress(
+    uint32_t* pLastAddress
+    );
+#endif /* MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK */
+
+#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
+/**
+ * @brief Compares the last address processed by the ELS DMA with the expected final address of the output buffer given to the last ELS command (security feature).
+ *        The given address @p outputStartAddress and expected length @p expectedLength determine the expected final address.
+ *        This function can be used to verify that the final DMA transfer of an ELS command has completed as expected.
+ *
+ * @param[in] outputStartAddress Pointer to the output buffer of the last ELS operation
+ * @param[in] expectedLength     Expected length of the output buffer of the last ELS operation
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ *
+ * @retval #MCUXCLELS_STATUS_SW_COMPARISON_FAILED if the comparison between the expected final address and the actual final address processed by ELS fails
+ * @retval #MCUXCLELS_STATUS_OK_WAIT              if the comparison was successful
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_CompareDmaFinalOutputAddress)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_CompareDmaFinalOutputAddress(
+        uint8_t *outputStartAddress,
+        size_t expectedLength
+        );
+#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK  */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_COMMON_H_ */
+
+/**
+ * @}
+ *
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Crc.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Crc.h
new file mode 100644
index 0000000000..5b7199704c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Crc.h
@@ -0,0 +1,637 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Crc.h
+ * @brief ELS header for Command CRC functionality.
+ *
+ * This header exposes functions that support the usage of the Command CRC feature for ELS.
+ */
+/**
+ * @defgroup mcuxClEls_Crc mcuxClEls_Crc
+ * @brief This part of the @ref mcuxClEls driver defines the Command CRC functionality
+ * @ingroup mcuxClEls
+ * @{
+ */
+#ifndef MCUXCLELS_CRC_H_
+#define MCUXCLELS_CRC_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Types.h> // Common types
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Crc_Macros mcuxClEls_Crc_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Crc
+ * @ingroup mcuxClEls_Crc
+ * @{
+ */
+
+/**
+ * @defgroup MCUXCLELS_CMD_CRC_ MCUXCLELS_CMD_CRC_
+ * @brief Constants for ELS Command CRC
+ * @ingroup mcuxClEls_Crc_Macros
+ * @{ */
+#define MCUXCLELS_CMD_CRC_VALUE_RESET    ((uint32_t) 0x1u) ///< Reset the Command CRC to initial value
+#define MCUXCLELS_CMD_CRC_VALUE_ENABLE   ((uint32_t) 0x2u) ///< Enable update of Command CRC value by executing commands
+#define MCUXCLELS_CMD_CRC_VALUE_DISABLE  ((uint32_t) 0x0u) ///< Disable update of Command CRC value by executing commands
+
+#define MCUXCLELS_CMD_CRC_RESET          ((uint32_t) 0x1u) ///< Reset the Command CRC to initial value
+#define MCUXCLELS_CMD_CRC_ENABLE         ((uint32_t) 0x1u) ///< Enable update of Command CRC value by executing commands
+#define MCUXCLELS_CMD_CRC_DISABLE        ((uint32_t) 0x0u) ///< Disable update of Command CRC value by executing commands
+
+#define MCUXCLELS_CMD_CRC_POLYNOMIAL     ((uint32_t) 0x04C11DB7u) ///< CRC polynomial for the Command CRC
+#define MCUXCLELS_CMD_CRC_INITIAL_VALUE  ((uint32_t) 0xA5A5A5A5u) ///< Initial value for the Command CRC
+/** @} */
+
+/**
+ * @defgroup MCUXCLELS_CMD_CRC_REFERENCE_ MCUXCLELS_CMD_CRC_REFERENCE_
+ * @brief Macros for reference ELS Command CRC
+ * @ingroup mcuxClEls_Crc_Macros
+ * @{
+ */
+
+/**
+ * @brief Initializes a reference CRC variable with the command CRC initial value.
+ *        The new variable has the given name.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_INIT(crc)  \
+    uint32_t (crc) = MCUXCLELS_CMD_CRC_INITIAL_VALUE
+
+/**
+ * @brief Resets the given reference CRC variable to the command CRC initial value.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_RESET(crc)  \
+    (crc) = MCUXCLELS_CMD_CRC_INITIAL_VALUE
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_Init_Async.
+ */
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options)                \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT;                           \
+    (options).bits.lastinit = MCUXCLELS_AEAD_LASTINIT_TRUE;                       \
+    (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_DISABLE;                      \
+    (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE;                      \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+	(retVal);                                                                    \
+  })
+#else
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options)                \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT;                           \
+    (options).bits.lastinit = MCUXCLELS_AEAD_LASTINIT_TRUE;                       \
+    (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_DISABLE;                      \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_PartialInit_Async.
+ */
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options)         \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT;                           \
+    (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE;                      \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#else
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options)         \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT;                           \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_UpdateAad_Async.
+ */
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options)           \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_AADPROC                         \
+    (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE;                       \
+    (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE;                      \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#else
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options)           \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_AADPROC;                        \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_UpdateData_Async.
+ */
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options)          \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_MSGPROC                         \
+    (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE;                       \
+    (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE;                      \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#else
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options)          \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_MSGPROC;                        \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_Finalize_Async.
+ */
+#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options)            \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_FINAL                           \
+    (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE;                       \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#else
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options)            \
+  ({                                                                             \
+    (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_FINAL;                          \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Cipher_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER(crc, options)                   \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CIPHER, (options).word.value, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Cmac_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC(crc, options)                     \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CMAC, (options).word.value, &(crc))
+
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_EccKeyGen_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN(crc, options)                \
+  ({                                                                             \
+    (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                      \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_EccKeyExchange_Async.
+ */
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc)                                 \
+    ({                                                                                        \
+        mcuxClEls_EccKeyExchOption_t options = {0u};                                           \
+        options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                                 \
+        options.bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL;                                   \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc));     \
+        (retVal);                                                                             \
+    })
+#else
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc)                                 \
+    ({                                                                                        \
+        mcuxClEls_EccKeyExchOption_t options = {0u};                                           \
+        options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                                 \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc));     \
+        (retVal);                                                                             \
+    })
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_EccKeyExchangeInt_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT(crc)                              \
+    ({                                                                                        \
+        mcuxClEls_EccKeyExchOption_t options = {0u};                                           \
+        options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                                 \
+        options.bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL;                                   \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc));     \
+        (retVal);                                                                             \
+    })
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_EccSign_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN(crc, options)                             \
+  ({                                                                                        \
+    (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                                 \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN, (options).word.value, &(crc)); \
+    (retVal);                                                                               \
+  })
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_EccVerify_Async.
+ */
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options)                          \
+  ({                                                                                        \
+    (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                                 \
+    (options).bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL;                                   \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \
+    (retVal);                                                                               \
+  })
+#else
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options)                          \
+  ({                                                                                        \
+    (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                                 \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \
+    (retVal);                                                                               \
+  })
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_EccVerifyInt_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT(crc, options)            \
+  ({                                                                             \
+    (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE;                      \
+    (options).bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL;                        \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \
+    (retVal);                                                                    \
+  })
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_GlitchDetector_LoadConfig_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG(crc)         \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD, 0u, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_GlitchDetector_Trim_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM(crc)               \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM, 0u, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Hash_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH(crc, options)                     \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HASH, (options).word.value, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Hmac_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC(crc, options)                     \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HMAC, (options).word.value, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Ckdf_Sp800108_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108(crc)                                 \
+    ({                                                                                       \
+        mcuxClEls_CkdfOption_t options = {0u};                                                \
+        options.bits.ckdf_algo = MCUXCLELS_CKDF_ALGO_SP800108;                                \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CKDF, options.word.value, &(crc));     \
+        (retVal);                                                                            \
+    })
+
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Hkdf_Rfc5869_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869(crc, options)                                               \
+  ({                                                                                                               \
+    (options).bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_RFC5869;                                                         \
+    mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HKDF, (options).word.value, &(crc));    \
+    (retVal);                                                                                                      \
+  })
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Hkdf_Sp80056c_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C(crc)                                     \
+    ({                                                                                           \
+        mcuxClEls_HkdfOption_t options = {0u};                                                    \
+        options.bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_SP80056C;                                    \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HKDF, options.word.value, &(crc));     \
+        (retVal);                                                                                \
+    })
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY(crc)              \
+    ({                                                                                           \
+        mcuxClEls_TlsOption_t options = {0u};                                                     \
+        options.bits.mode = MCUXCLELS_TLS_INIT;                                                   \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_TLS, options.word.value, &(crc));          \
+        (retVal);                                                                                \
+    })
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY(crc)               \
+    ({                                                                                           \
+        mcuxClEls_TlsOption_t options = {0u};                                                     \
+        options.bits.mode = MCUXCLELS_TLS_FINALIZE;                                               \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_TLS, options.word.value, &(crc));          \
+        (retVal);                                                                                \
+    })
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyDelete_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc)                         \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KDELETE, 0u, &(crc))
+
+
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyImport_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, options)                \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYIN, (options).word.value, &(crc))
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyImportPuk_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK(crc)                                  \
+    ({                                                                                       \
+        mcuxClEls_KeyImportOption_t options = {0u};                                           \
+        options.bits.revf = MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE;                          \
+        options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_PBK;                                     \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYIN, options.word.value, &(crc));    \
+        (retVal);                                                                            \
+    })
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyExport_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT(crc)                                                              \
+    ({                                                                                                                \
+        mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT, 0u, &(crc));                 \
+        mcuxClEls_KeyImportOption_t import_options = {0u};                                                             \
+        import_options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_RFC3394;                                                   \
+        retVal = MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc);                                                    \
+        retVal = MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, import_options);                         \
+        (retVal);                                                                                                     \
+    })
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgRequest_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST(crc)                  \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, 0u, &(crc))
+
+#ifdef MCUXCL_FEATURE_ELS_RND_RAW
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgRequestRaw_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW(crc)               \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, MCUXCLELS_RNG_RND_REQ_RND_RAW, &(crc))
+#endif /* MCUXCL_FEATURE_ELS_RND_RAW */
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestInstantiate_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE(crc)                        \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestExtract_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT(crc)                             \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestAesEcb_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB(crc)                             \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestAesCtr_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR(crc)                             \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_Dtrng_ConfigLoad_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD(crc)             \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD, 0u, &(crc))
+
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE(crc)         \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL, 0u, &(crc))
+
+#ifdef MCUXCL_FEATURE_ELS_PRND_INIT
+/**
+ * @brief Updates given reference command CRC with command @ref mcuxClEls_Prng_Init_Async.
+ */
+#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT(crc)                               \
+    mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, MCUXCLELS_RNG_RND_REQ_PRND_INIT, &(crc))
+#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_CMD_CRC_CMD_ID_ MCUXCLELS_CMD_CRC_CMD_ID_
+ * @brief Constants for ELS Command IDs
+ * @ingroup mcuxClEls_Crc_Macros
+ * @{
+ */
+#define MCUXCLELS_CMD_CRC_CMD_ID_CIPHER          0 ///< ELS Command ID for CIPHER command
+#define MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER     1 ///< ELS Command ID for AUTH_CIPHER command
+#define MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN   3 ///< ELS Command ID for CHAL_RESP_GEN command
+#define MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN          4 ///< ELS Command ID for ECSIGN command
+#define MCUXCLELS_CMD_CRC_CMD_ID_ECVFY           5 ///< ELS Command ID for ECVFY command
+#define MCUXCLELS_CMD_CRC_CMD_ID_ECKXH           6 ///< ELS Command ID for ECKXH command
+#define MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN          8 ///< ELS Command ID for KEYGEN command
+#define MCUXCLELS_CMD_CRC_CMD_ID_KEYIN           9 ///< ELS Command ID for KEYIN command
+#define MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT         10 ///< ELS Command ID for KEYOUT command
+#define MCUXCLELS_CMD_CRC_CMD_ID_KDELETE        11 ///< ELS Command ID for KDELETE command
+#define MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV        12 ///< ELS Command ID for KEYPROV command
+#define MCUXCLELS_CMD_CRC_CMD_ID_CKDF           16 ///< ELS Command ID for CKDF command
+#define MCUXCLELS_CMD_CRC_CMD_ID_HKDF           17 ///< ELS Command ID for HKDF command
+#define MCUXCLELS_CMD_CRC_CMD_ID_TLS            18 ///< ELS Command ID for TLS command
+#define MCUXCLELS_CMD_CRC_CMD_ID_HASH           20 ///< ELS Command ID for HASH command
+#define MCUXCLELS_CMD_CRC_CMD_ID_HMAC           21 ///< ELS Command ID for HMAC command
+#define MCUXCLELS_CMD_CRC_CMD_ID_CMAC           22 ///< ELS Command ID for CMAC command
+#define MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ        24 ///< ELS Command ID for RND_REQ command
+#define MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST      25 ///< ELS Command ID for DRBG_TEST command
+#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD 28 ///< ELS Command ID for DTRNG_CFG_LOAD command
+#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL     29 ///< ELS Command ID for DTRNG_EVAL command
+#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD  30 ///< ELS Command ID for GDET_CFG_LOAD command
+#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM      31 ///< ELS Command ID for GDET_TRIM command
+/**
+ * @}
+ *
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Crc_Types mcuxClEls_Crc_Types
+ * @brief Defines all types of @ref mcuxClEls_Crc
+ * @ingroup mcuxClEls_Crc
+ * @{
+ */
+
+/**
+ * @brief Type to control ELS Command CRC
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Accesses the bit field as a full word
+    } word;
+    struct
+    {
+        uint32_t reset :1;      ///< Reset the Command CRC to initial value, set by #MCUXCLELS_CMD_CRC_RESET
+        uint32_t enable :1;     ///< Enable/Disable update of Command CRC value by executing commands, set with #MCUXCLELS_CMD_CRC_ENABLE / #MCUXCLELS_CMD_CRC_DISABLE
+        uint32_t : 30;          ///< RFU
+    } bits;                     ///< Access #mcuxClEls_CommandCrcConfig_t bit-wise
+} mcuxClEls_CommandCrcConfig_t;
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Crc_Functions mcuxClEls_Crc_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Crc
+ * @ingroup mcuxClEls_Crc
+ * @{
+ */
+
+/**
+ * @brief Set command CRC flags.
+ *
+ * @param[in] options    The command CRC options. For more information, see #mcuxClEls_CommandCrcConfig_t.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK
+ * @else
+ *  @return An error code that is always #MCUXCLELS_STATUS_OK
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ConfigureCommandCRC)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ConfigureCommandCRC(
+    mcuxClEls_CommandCrcConfig_t options
+    );
+
+/**
+ * @brief Get the current command CRC value.
+ *
+ * @param[out] commandCrc    The command CRC value.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection).
+ *  @retval MCUXCLELS_STATUS_OK                Operation successful
+ *  @retval MCUXCLELS_STATUS_SW_INVALID_PARAM  Parameter commandCRC points to NULL
+ * @else
+ *  @return An error code
+ *  @retval MCUXCLELS_STATUS_OK                Operation successful
+ *  @retval MCUXCLELS_STATUS_SW_INVALID_PARAM  Parameter commandCRC points to NULL
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetCommandCRC)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetCommandCRC(
+    uint32_t* commandCrc
+    );
+
+/**
+ * @brief Verifies a reference CRC against the computed ELS command CRC.
+ *
+ * @param[in] refCrc The reference CRC value.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_VerifyVsRefCRC)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_VerifyVsRefCRC(
+    uint32_t refCrc
+    );
+
+/**
+ * @brief Updates a reference CRC with the parameters of an ELS command.
+ *        This can be used to verify against the ELS command CRC.
+ *
+ * @param[in]     command  The ELS command ID.
+ * @param[in]     options  The command options for the given ELS command.
+ * @param[in,out] refCrc   The current reference CRC value to update.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection).
+ *  @retval MCUXCLELS_STATUS_OK                Operation successful
+ *  @retval MCUXCLELS_STATUS_SW_INVALID_PARAM  Parameter crc points to NULL
+ * @else
+ *  @return An error code
+ *  @retval MCUXCLELS_STATUS_OK                Operation successful
+ *  @retval MCUXCLELS_STATUS_SW_INVALID_PARAM  Parameter crc points to NULL
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_UpdateRefCRC)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_UpdateRefCRC(
+    uint8_t   command,
+    uint32_t  options,
+    uint32_t* refCrc
+    );
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_CRC_H_ */
+
+/**
+ * @}
+ *
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Ecc.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Ecc.h
new file mode 100644
index 0000000000..222a6c390c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Ecc.h
@@ -0,0 +1,593 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file mcuxClEls_Ecc.h
+ * @brief ELS header for elliptic curve cryptography
+ * This header exposes functions that enable using the ELS for elliptic curve cryptography.
+ * All functions operate on the NIST P-256 curve.
+ * The ECC operations supported are:
+ * - ECC key generation
+ * - ECC Diffie-Hellman key exchange
+ * - ECDSA signature generation/verification
+ */
+
+
+#ifndef MCUXCLELS_ECC_H_
+#define MCUXCLELS_ECC_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common types & functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup mcuxClEls_Ecc mcuxClEls_Ecc
+ * @brief This part of the @ref mcuxClEls driver supports functionality for elliptic curve cryptography
+ * @ingroup mcuxClEls
+ * @{
+ */
+
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Ecc_Macros mcuxClEls_Ecc_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Ecc
+ * @ingroup mcuxClEls_Ecc
+ * @{
+ */
+
+/**
+ * @defgroup MCUXCLELS_ECC_VALUE_ MCUXCLELS_ECC (Sign and Verify) option word values
+ * @brief Constants for #mcuxClEls_EccSignOption_t and #mcuxClEls_EccVerifyOption_t
+ * @ingroup mcuxClEls_Ecc_Macros
+ * @{
+ */
+#define MCUXCLELS_ECC_VALUE_HASHED              ((uint32_t) 0u<< 0u) ///< Set this option at #mcuxClEls_EccSignOption_t.value or #mcuxClEls_EccVerifyOption_t.value to specify input is the hash of the message
+#define MCUXCLELS_ECC_VALUE_NOT_HASHED          ((uint32_t) 1u<< 0u) ///< Set this option at #mcuxClEls_EccSignOption_t.value or #mcuxClEls_EccVerifyOption_t.value to specify input is the plain message
+#define MCUXCLELS_ECC_VALUE_RTF                 ((uint32_t) 1u<< 1u) ///< Set this option at #mcuxClEls_EccSignOption_t.value to include the RTF in the signature, only for #mcuxClEls_EccSignOption_t
+#define MCUXCLELS_ECC_VALUE_NO_RTF              ((uint32_t) 0u<< 1u) ///< Set this option at #mcuxClEls_EccSignOption_t.value to not include the RTF in the signature, only for #mcuxClEls_EccSignOption_t
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_KEYGEN_VALUE_ MCUXCLELS_KEYGEN option word values
+ * @brief Constants for #mcuxClEls_EccKeyGenOption_t
+ * @ingroup mcuxClEls_Ecc_Macros
+ * @{
+ */
+#define MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY   ((uint32_t) 1u<< 0u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to sign the public key
+#define MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN        ((uint32_t) 0u<< 1u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key will be a signing key usable by #mcuxClEls_EccSign_Async
+#define MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE ((uint32_t) 1u<< 1u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key will be a Diffie Helman key usable by #mcuxClEls_EccKeyExchange_Async
+#define MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC    ((uint32_t) 0u<< 2u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key is deterministic
+#define MCUXCLELS_KEYGEN_VALUE_RANDOM           ((uint32_t) 1u<< 2u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key is random
+#define MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY      ((uint32_t) 0u<< 3u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to generate a public key
+#define MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY       ((uint32_t) 1u<< 3u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to not generate a public key
+#define MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA   ((uint32_t) 0u<< 5u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to not use random data for signing the public key
+#define MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA  ((uint32_t) 1u<< 5u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to use random data for signing the public key
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_ECC_VALUE_BITS MCUXCLELS_ECC (Sign and Verify) option bit field values
+ * @brief Bit field constants for #mcuxClEls_EccSignOption_t and #mcuxClEls_EccVerifyOption_t
+ * @ingroup mcuxClEls_Ecc_Macros
+ * @{
+ */
+#define MCUXCLELS_ECC_HASHED                     ((uint32_t) 0U) ///< Set this option at #mcuxClEls_EccSignOption_t.echashchl or #mcuxClEls_EccVerifyOption_t.echashchl to specify input is the hash of the message
+#define MCUXCLELS_ECC_NOT_HASHED                 ((uint32_t) 1U) ///< Set this option at #mcuxClEls_EccSignOption_t.echashchl or #mcuxClEls_EccVerifyOption_t.echashchl to specify input is the plain message
+
+#define MCUXCLELS_ECC_RTF                        ((uint32_t) 1U) ///< Set this option at #mcuxClEls_EccSignOption_t.signrtf to include the RTF in the signature
+#define MCUXCLELS_ECC_NO_RTF                     ((uint32_t) 0U) ///< Set this option at #mcuxClEls_EccSignOption_t.signrtf to not include the RTF in the signature
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_KEYGEN_VALUE_BITS MCUXCLELS_KEYGEN option bit field values
+ * @brief Bit field constants for #mcuxClEls_EccKeyGenOption_t
+ * @ingroup mcuxClEls_Ecc_Macros
+ * @{
+ */
+#define MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE      (1U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign to sign the public key (signature will be concatenated to the output public key)
+#define MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE     (0U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign to not sign the public key
+
+#define MCUXCLELS_ECC_OUTPUTKEY_SIGN             (0U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a signing key usable by #mcuxClEls_EccSign_Async
+#define MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE      (1U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a Diffie Helman key usable by #mcuxClEls_EccKeyExchange_Async
+
+#define MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC    (0U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is deterministic
+#define MCUXCLELS_ECC_OUTPUTKEY_RANDOM           (1U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is random
+
+#define MCUXCLELS_ECC_GEN_PUBLIC_KEY             (0U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.skip_pbk to generate a public key
+#define MCUXCLELS_ECC_SKIP_PUBLIC_KEY            (1U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.skip_pbk to not generate a public key.
+                                                   ///< If #MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE set, this option will be ignored and a public key will be generated.
+
+#define MCUXCLELS_ECC_NO_RANDOM_DATA             (0U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign_rnd to not include user provided random data for the signature
+#define MCUXCLELS_ECC_INCLUDE_RANDOM_DATA        (1U) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign_rnd to include user provided random data for the signature.
+                                                   ///< #MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE must be set in this case.
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_INTERNAL_VALUE_BITS Option bit field values that are needed for internal use only
+ * @brief Internal bit field constants for several option types.
+ * @ingroup mcuxClEls_Ecc_Macros
+ * @{
+ */
+#define MCUXCLELS_ECC_REVERSEFETCH_ENABLE        (0x01U) ///< Reverse Fetch enabled. For internal use
+#define MCUXCLELS_ECC_REVERSEFETCH_DISABLE       (0x00U) ///< Reverse Fetch disabled. For internal use
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
+#define MCUXCLELS_ECC_EXTKEY_EXTERNAL        (0x01U) ///< Public key is taken from system memory. For internal use
+#define MCUXCLELS_ECC_EXTKEY_INTERNAL        (0x00U) ///< Public key is taken from internal keystore. For internal use
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_ECC_SIZE MCUXCLELS_ECC_SIZE
+ * @brief Defines size of public key and signature in bytes
+ * @ingroup mcuxClEls_Ecc_Macros
+ * @{
+ */
+#define MCUXCLELS_ECC_PUBLICKEY_SIZE     ((size_t) 64U) ///< Size of the public key
+#define MCUXCLELS_ECC_SIGNATURE_SIZE     ((size_t) 64U) ///< Size of the signature
+#define MCUXCLELS_ECC_SIGNATURE_R_SIZE   ((size_t) 32U) ///< Size of the signature part r
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */ /* mcuxClEls_Ecc_Macros */
+
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Ecc_Types mcuxClEls_Ecc_Types
+ * @brief Defines all types of @ref mcuxClEls_Ecc
+ * @ingroup mcuxClEls_Ecc
+ * @{
+ */
+
+/**
+ * @brief Data type for ECC parameters in ELS format
+ * @deprecated All ELS ECC functions now operate on uint8_t. This type will be removed soon.
+ */
+typedef uint8_t mcuxClEls_EccByte_t;
+
+/**
+ * @brief Command option bit field for #mcuxClEls_EccSign_Async
+ * Bit field to configure #mcuxClEls_EccSign_Async. See @ref MCUXCLELS_ECC_VALUE_BITS for possible options.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Access the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_ECC_VALUE_
+    } word;                     ///< Access #mcuxClEls_EccSignOption_t word-wise
+    struct
+    {
+        uint32_t echashchl :1;  ///< Define type of input, plain message or hash of message
+        uint32_t signrtf :1;    ///< Define if signing the Run-Time Fingerprint
+        uint32_t :2;            ///< RFU
+        uint32_t revf :1;       ///< This field is managed internally
+        uint32_t :27;           ///< RFU
+    } bits;                     ///< Access #mcuxClEls_EccSignOption_t bit-wise
+} mcuxClEls_EccSignOption_t;
+
+/**
+ * @brief Command option bit field for #mcuxClEls_EccVerify_Async
+ * Bit field to configure #mcuxClEls_EccVerifyOption_t. See @ref MCUXCLELS_ECC_VALUE_BITS for possible options.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Access the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_ECC_VALUE_
+    } word;                     ///< Access #mcuxClEls_EccVerifyOption_t word-wise
+    struct
+    {
+        uint32_t echashchl :1;  ///< Define type of input, plain message or hash of message
+        uint32_t :3;            ///< RFU
+        uint32_t revf :1;       ///< This field is managed internally
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
+        uint32_t :8;            ///< RFU
+        uint32_t extkey :1;     ///< This field is managed internally
+        uint32_t :18;           ///< RFU
+#else
+        uint32_t :27;           ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
+    } bits;                     ///< Access #mcuxClEls_EccVerifyOption_t bit-wise
+} mcuxClEls_EccVerifyOption_t;
+
+/**
+ * @brief Command option bit field for #mcuxClEls_EccKeyGen_Async
+ * Bit field to configure #mcuxClEls_EccKeyGenOption_t. See @ref MCUXCLELS_KEYGEN_VALUE_BITS for possible options.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_KEYGEN_VALUE_
+    } word;                     ///< Access #mcuxClEls_EccKeyGenOption_t word-wise
+    struct
+    {
+        uint32_t kgsign :1;     ///< Define if signing the output public key
+        uint32_t kgtypedh :1;   ///< Define the usage of the output key
+        uint32_t kgsrc :1;      ///< Define if the output key is deterministic or random
+        uint32_t skip_pbk :1;   ///< Define if generating a public key
+        uint32_t revf :1;       ///< This field is managed internally
+        uint32_t kgsign_rnd :1; ///< Define if using user provided random data for the signature.
+        uint32_t :26;           ///< RFU
+    } bits;                     ///< Access #mcuxClEls_EccKeyGenOption_t bit-wise
+} mcuxClEls_EccKeyGenOption_t;
+
+/**
+ * @brief Command option bit field for #mcuxClEls_EccKeyExchange_Async, for internal use only.
+ * Bit field to configure #mcuxClEls_EccKeyExchOption_t.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Accesses the bit field as a full word
+    } word;                     ///< Access #mcuxClEls_EccKeyExchOption_t word-wise
+    struct
+    {
+        uint32_t :4;            ///< RFU
+        uint32_t revf :1;       ///< This field is managed internally
+        uint32_t :8;            ///< RFU
+        uint32_t extkey :1;     ///< This field is managed internally
+        uint32_t :18;           ///< RFU
+    } bits;                     ///< Access #mcuxClEls_EccKeyExchOption_t bit-wise
+} mcuxClEls_EccKeyExchOption_t;
+
+/**
+ * @}
+ */ /* mcuxClEls_Ecc_Types */
+
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Ecc_Functions mcuxClEls_Ecc_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Ecc
+ * @ingroup mcuxClEls_Ecc
+ * @{
+ */
+
+/**
+ * @brief Generates an ECC key pair on the NIST P-256 curve.
+ * 
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * The public key will be stored in the standard ANSI X9.62 byte order (big-endian).
+ *
+ * @param[in]  options                The command options. For more information, see #mcuxClEls_EccKeyGenOption_t.
+ * @param[in]  signingKeyIdx          The index of the key to sign the generated public key.
+ * @param[in]  privateKeyIdx          Output key index.
+ * @param[in]  generatedKeyProperties The desired key properties of the generated key.
+ * @param[in]  pRandomData            Random data provided by the user.
+ * @param[out] pPublicKey             Pointer to the memory area which receives the public key and optionally the key signature.
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p options.kgsign == #MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE</dt>
+ *       <dd>@p signingKeyIdx is ignored.</dd>
+ *     <dt>@p options.kgsrc == #MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC</dt>
+ *       <dd>@p privateKeyIdx also defines the key index of the source key material.
+ *           The source key material will be overwritten by the output public key.</dd>
+ *     <dt>@p options.kgsign_rnd == #MCUXCLELS_ECC_NO_RANDOM_DATA</dt>
+ *       <dd>@p pRandomData is ignored.</dd>
+ *     <dt>@p pPublicKey must be aligned on a 4-byte boundary.</dt>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyGen_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyGen_Async(
+    mcuxClEls_EccKeyGenOption_t options,
+    mcuxClEls_KeyIndex_t signingKeyIdx,
+    mcuxClEls_KeyIndex_t privateKeyIdx,
+    mcuxClEls_KeyProp_t generatedKeyProperties,
+    uint8_t const * pRandomData,
+    uint8_t * pPublicKey
+    );
+
+/**
+ * @brief Performs a Diffie-Hellman key exchange with an internal ECC private key and an external ECC public key.
+ * 
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * The public key must be stored in the standard ANSI X9.62 byte order (big-endian).
+ *
+ * @param[in] privateKeyIdx          The private key index.
+ * @param[in] pPublicKey             Pointer to the public key of a third party.
+ * @param[in] sharedSecretIdx        The index in the ELS keystore that receives the shared secret that is generated by the ECDH operation.
+ * @param[in] sharedSecretProperties The desired key properties of the shared secret.
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p pPublicKey </dt>
+ *       <dd>The public key consists of the 256-bit X coordinate and the 256-bit Y coordinate.
+ *           The point must lie on the NIST P-256 curve, be encoded in X9.62 format and aligned on a 4-byte boundary.</dd>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyExchange_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchange_Async(
+    mcuxClEls_KeyIndex_t privateKeyIdx,
+    uint8_t const * pPublicKey,
+    mcuxClEls_KeyIndex_t sharedSecretIdx,
+    mcuxClEls_KeyProp_t sharedSecretProperties
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+/**
+ * @brief Performs a Diffie-Hellman key exchange with an internal ECC private key and an internal ECC public key.
+ * 
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in] privateKeyIdx          The private key index.
+ * @param[in] publicKeyIdx           The public key index.
+ * @param[in] sharedSecretIdx        The index in the ELS keystore that receives the shared secret that is generated by the ECDH operation.
+ * @param[in] sharedSecretProperties The desired key properties of the shared secret.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyExchangeInt_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchangeInt_Async(
+    mcuxClEls_KeyIndex_t privateKeyIdx,
+    mcuxClEls_KeyIndex_t publicKeyIdx,
+    mcuxClEls_KeyIndex_t sharedSecretIdx,
+    mcuxClEls_KeyProp_t sharedSecretProperties
+    );
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/**
+ * @brief Generates an ECDSA signature of a given message.
+ *
+ * The curve is NIST P-256.
+ * The message hash, must be stored in the standard ANSI X9.62 format.
+ * If the message is provided in plain, no prior conversion is necessary.
+ * The signature will be stored in the standard ANSI X9.62 byte order (big-endian).
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * No matter the value of @p options.echashchl, it must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * 
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]  options            The command options. For more information, see #mcuxClEls_EccSignOption_t.
+ * @param[in]  keyIdx             The private key index.
+ * @param[in]  pInputHash         The hash of the message to sign in X9.62 format.
+ * @param[in]  pInputMessage      The message to sign.
+ * @param[in]  inputMessageLength Size of @p pInputMessage in bytes.
+ * @param[out] pOutput            Pointer to the memory area which receives the generated signature in X9.62 format. (64 bytes)
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p options.echashchl == #MCUXCLELS_ECC_HASHED</dt>
+ *       <dd>@p pInputHash is used, and it must be aligned on a 4-byte boundary.
+ *           @p pInputMessage is ignored.</dd>
+ *     <dt>@p options.echashchl == #MCUXCLELS_ECC_NOT_HASHED</dt>
+ *       <dd>@p pInputHash is ignored.
+ *           @p pInputMessage and @p inputMessageLength are used.</dd>
+ *     <dt>@p pOptput must be aligned on a 4-byte boundary.</dt>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccSign_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccSign_Async(
+    mcuxClEls_EccSignOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pInputHash,
+    uint8_t const * pInputMessage,
+    size_t inputMessageLength,
+    uint8_t * pOutput
+    );
+
+/**
+ * @brief Verifies an ECDSA signature of a given message.
+ *
+ * The curve is NIST P-256.
+ * The message hash, must be stored in the standard ANSI X9.62 format.
+ * If the message is provided in plain, no prior conversion is necessary.
+ * The signature and public key must be stored in the standard ANSI X9.62 byte order (big-endian).
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * No matter the value of @p options.echashchl, it must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * 
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]  options             The command options. For more information, see #mcuxClEls_EccVerifyOption_t.
+ * @param[in]  pInputHash          The hash of the signed message in X9.62 format.
+ * @param[in]  pInputMessage       The message to sign.
+ * @param[in]  inputMessageLength  Size of @p pInputMessage in bytes.
+ * @param[in]  pSignatureAndPubKey Pointer to the memory area which contains the concatenation of the signature and the public key.
+ * @param[out] pOutput             Pointer to the memory area which will receive the recalculated value of the R component in case of a successful
+ *                                 signature verification.
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p options.echashchl == #MCUXCLELS_ECC_HASHED</dt>
+ *       <dd>@p pInputHash is used, and it must be aligned on a 4-byte boundary.
+ *           @p pInputMessage is ignored.</dd>
+ *     <dt>@p options.echashchl == #MCUXCLELS_ECC_NOT_HASHED</dt>
+ *       <dd>@p pInputHash is ignored.
+ *           @p pInputMessage and @p inputMessageLength are used.</dd>
+ *     <dt>@p pSignatureAndPubKey </dt>
+ *       <dd>It must be aligned on a 4-byte boundary.
+ *           The signature to be verified consists of the 256-bit R component and the 256-bit S component.
+ *           The public key is the one for verification. (Uncompressed, X and Y components)
+ *           The signature and the public key are in X9.62 format.</dd>
+ *     <dt>@p pOutput </dt>
+ *       <dd>It must be aligned on a 4-byte boundary.
+ *           The output shall be compared to the first 32 bytes stored at @p pSignatureAndPublicKey.</dd>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccVerify_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerify_Async(
+    mcuxClEls_EccVerifyOption_t options,
+    uint8_t const * pInputHash,
+    uint8_t const * pInputMessage,
+    size_t inputMessageLength,
+    uint8_t const * pSignatureAndPubKey,
+    uint8_t * pOutput
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+/**
+ * @brief Verifies an ECDSA signature of a given message.
+ *
+ * The curve is NIST P-256.
+ * The message hash, must be stored in the standard ANSI X9.62 format.
+ * If the message is provided in plain, no prior conversion is necessary.
+ * The signature must be stored in the standard ANSI X9.62 byte order (big-endian).
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * No matter the value of @p options.echashchl, it must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * 
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]  options             The command options. For more information, see #mcuxClEls_EccVerifyOption_t.
+ * @param[in]  publicKeyIdx        The public key index.
+ * @param[in]  pInputHash          The hash of the signed message in X9.62 format.
+ * @param[in]  pInputMessage       The message to sign.
+ * @param[in]  inputMessageLength  Size of @p pInputMessage in bytes.
+ * @param[in]  pSignature          Pointer to the memory area which contains the concatenation of the signature and the public key.
+ * @param[out] pOutput             Pointer to the memory area which will receive the recalculated value of the R component in case of a successful
+ *                                 signature verification.
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p options.echashchl == #MCUXCLELS_ECC_HASHED</dt>
+ *       <dd>@p pInputHash is used, and it must be aligned on a 4-byte boundary.
+ *           @p pInputMessage is ignored.</dd>
+ *     <dt>@p options.echashchl == #MCUXCLELS_ECC_NOT_HASHED</dt>
+ *       <dd>@p pInputHash is ignored.
+ *           @p pInputMessage and @p inputMessageLength are used.</dd>
+ *     <dt>@p pSignature</dt>
+ *       <dd>It must be aligned on a 4-byte boundary.
+ *           The signature to be verified consists of the 256-bit R component and the 256-bit S component.
+ *           The signature is in X9.62 format.</dd>
+ *     <dt>@p pOutput </dt>
+ *       <dd>It must be aligned on a 4-byte boundary.
+ *           The output shall be compared to the first 32 bytes stored at @p pSignatureAndPublicKey.</dd>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccVerifyInt_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerifyInt_Async(
+    mcuxClEls_EccVerifyOption_t options,
+    mcuxClEls_KeyIndex_t publicKeyIdx,
+    uint8_t const * pInputHash,
+    uint8_t const * pInputMessage,
+    size_t inputMessageLength,
+    uint8_t const * pSignature,
+    uint8_t * pOutput
+    );
+
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/**
+ * @}
+ */ /* mcuxClEls_Ecc_Functions */
+
+/**
+ * @}
+ */ /* mcuxClEls_Ecc */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_ECC_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_GlitchDetector.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_GlitchDetector.h
new file mode 100644
index 0000000000..84ce4da234
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_GlitchDetector.h
@@ -0,0 +1,157 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2022 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClEls_GlitchDetector.h
+ *  @brief ELS header for controlling the glitch detector.
+ *
+ * This header exposes functions that configure the ELS glitch detector. 
+ */
+ 
+#ifndef MCUXCLELS_GLITCHDETECTOR_H_
+#define MCUXCLELS_GLITCHDETECTOR_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common types & functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup mcuxClEls_GlitchDetector mcuxClEls_GlitchDetector
+ * @brief This part of the @ref mcuxClEls driver supports glitch detector functionality
+ * @ingroup mcuxClEls
+ * @{
+ */
+ 
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_GlitchDetector_Macros mcuxClEls_GlitchDetector_Macros
+ * @brief Defines all macros of @ref mcuxClEls_GlitchDetector
+ * @ingroup mcuxClEls_GlitchDetector
+ * @{
+ */
+
+#define MCUXCLELS_GLITCHDETECTOR_CFG_SIZE  ((size_t) 0x18u) ///< Glitch detector configuration size
+
+#define MCUXCLELS_GLITCHDETECTOR_TRIM_SIZE  ((size_t) 0x04u) ///< Glitch detector trim value size
+
+/**
+ * @}
+ */ /* mcuxClEls_GlitchDetector_Macros */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_GlitchDetector_Functions mcuxClEls_GlitchDetector_Functions
+ * @brief Defines all functions of @ref mcuxClEls_GlitchDetector
+ * @ingroup mcuxClEls_GlitchDetector
+ * @{
+ */
+
+/**
+ * @brief Loads a glitch detector configuration.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]   Pointer to the memory area which contains the glitch detector configuration. The size is fixed at #MCUXCLELS_GLITCHDETECTOR_CFG_SIZE bytes.
+ *
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request 
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_LoadConfig_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_LoadConfig_Async(
+    uint8_t const * pInput
+    );
+
+/** 
+ * @brief Calculates optimal ELS glitch detector configuration and writes it to system memory.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[out]  Pointer to the memory area which receives the glitch detector trim value. The size is fixed at #MCUXCLELS_GLITCHDETECTOR_TRIM_SIZE bytes.
+ *
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request 
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ *
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_Trim_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_Trim_Async(
+    uint8_t * pOutput 
+    );
+
+/** 
+ * @brief Reads the glitch detector's event counter
+ * 
+ * This function converts the event counter from Gray code to an unsigned number.
+ *
+ * @param[in]   Pointer to the word where the counter value will be stored.
+ *
+ * @retval #MCUXCLELS_STATUS_OK                  on successful request 
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_GetEventCounter)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_GetEventCounter(
+    uint8_t * pCount 
+    );
+
+/** 
+ * @brief Resets the glitch detector's event counter
+ *
+ * @retval #MCUXCLELS_STATUS_OK                  on successful request
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_ResetEventCounter)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_ResetEventCounter( void
+    );
+ 
+/**
+ * @}
+ */ /* mcuxClEls_GlitchDetector_Functions */
+ 
+/**
+ * @}
+ */ /* mcuxClEls_GlitchDetector */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_GLITCHDETECTOR_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hash.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hash.h
new file mode 100644
index 0000000000..808b99b413
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hash.h
@@ -0,0 +1,351 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Hash.h
+ * @brief ELS header for hashing.
+ *
+ * This header exposes functions that enable using the ELS for hashing.
+ * There are two modes to hash a message: The asynchronous way as an ELS command, and the SHA-Direct mode which feeds
+ * data to the internal registers of the ELS and is synchronous (blocking).
+ * The SHA-Direct mode is meant to be used when another command should be executed in parallel on the ELS while the
+ * hash operation is still ongoing. For this, use the DMA callback option in #mcuxClEls_Hash_ShaDirect.
+ */
+
+/**
+ * @defgroup mcuxClEls_Hash mcuxClEls_Hash
+ * @brief This part of the @ref mcuxClEls driver supports hashing
+ * @ingroup mcuxClEls
+ * @{
+ */
+
+#ifndef MCUXCLELS_HASH_H_
+#define MCUXCLELS_HASH_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+
+/**
+ * @defgroup mcuxClEls_Hash_Macros mcuxClEls_Hash_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Hash
+ * @ingroup mcuxClEls_Hash
+ * @{
+ */
+
+/**
+ * @defgroup MCUXCLELS_HASH_ MCUXCLELS_HASH_
+ * @brief Defines valid options to be used by #mcuxClEls_HashOption_t
+ * @ingroup mcuxClEls_Hash_Macros
+ * @{
+ */
+
+#define MCUXCLELS_HASH_INIT_ENABLE  1U ///< Set this option at #mcuxClEls_HashOption_t.hashini to initialize the hash
+#define MCUXCLELS_HASH_INIT_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.hashini to continue the hash
+
+#define MCUXCLELS_HASH_LOAD_ENABLE  1U ///< Set this option at #mcuxClEls_HashOption_t.hashld to load the hash state from @p pDigest
+#define MCUXCLELS_HASH_LOAD_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.hashld to not load the hash state
+
+#define MCUXCLELS_HASH_OUTPUT_ENABLE  1U ///< Set this option at #mcuxClEls_HashOption_t.hashoe to output the hash to @p pDigest
+#define MCUXCLELS_HASH_OUTPUT_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.hashoe to not output the hash
+
+#define MCUXCLELS_HASH_RTF_UPDATE_ENABLE  1U ///< Set this option at #mcuxClEls_HashOption_t.rtfupd to update the run-time fingerprint (only supported by #mcuxClEls_Hash_Async)
+#define MCUXCLELS_HASH_RTF_UPDATE_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.rtfupd to not update the run-time fingerprint
+
+#define MCUXCLELS_HASH_RTF_OUTPUT_ENABLE  1U ///< Set this option at #mcuxClEls_HashOption_t.rtfoe to output the run-time fingerprint (only supported by #mcuxClEls_Hash_Async)
+#define MCUXCLELS_HASH_RTF_OUTPUT_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.rtfoe to not output the run-time fingerprint
+
+#define MCUXCLELS_HASH_MODE_SHA_224        1U  ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-224
+#define MCUXCLELS_HASH_MODE_SHA_256        0U  ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-256
+#define MCUXCLELS_HASH_MODE_SHA_384        2U   ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-384
+#define MCUXCLELS_HASH_MODE_SHA_512        3U   ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-512
+
+
+#define MCUXCLELS_HASH_VALUE_MODE_SHA_224  ((uint32_t) MCUXCLELS_HASH_MODE_SHA_224 << 4)  ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-224
+#define MCUXCLELS_HASH_VALUE_MODE_SHA_256  ((uint32_t) MCUXCLELS_HASH_MODE_SHA_256 << 4)  ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-256
+#define MCUXCLELS_HASH_VALUE_MODE_SHA_384  ((uint32_t) MCUXCLELS_HASH_MODE_SHA_384 << 4)  ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-384
+#define MCUXCLELS_HASH_VALUE_MODE_SHA_512  ((uint32_t) MCUXCLELS_HASH_MODE_SHA_512 << 4)  ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-512
+
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_HASH_BLOCK_SIZE_ MCUXCLELS_HASH_BLOCK_SIZE_
+ * @brief Defines block sizes used by the supported hash algorithms
+ * @ingroup mcuxClEls_Hash_Macros
+ * @{
+ */
+#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_224  64U ///< SHA-224 output size: 512 bit (64 bytes)
+#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_256  64U ///< SHA-256 output size: 512 bit (64 bytes)
+#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_384  128U ///< SHA-384 output size: 1024 bit (128 bytes)
+#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_512  128U ///< SHA-512 output size: 1024 bit (128 bytes)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_HASH_STATE_SIZE_ MCUXCLELS_HASH_STATE_SIZE_
+ * @brief Defines the intermediate state sizes of the supported hash algorithms
+ * @ingroup mcuxClEls_Hash_Macros
+ * @{
+ */
+#define MCUXCLELS_HASH_STATE_SIZE_SHA_224  32U ///< SHA-224 state size: 256 bit (32 bytes)
+#define MCUXCLELS_HASH_STATE_SIZE_SHA_256  32U ///< SHA-256 state size: 256 bit (32 bytes)
+#define MCUXCLELS_HASH_STATE_SIZE_SHA_384  64U  ///< SHA-384 state size: 512 bit (64 bytes)
+#define MCUXCLELS_HASH_STATE_SIZE_SHA_512  64U  ///< SHA-512 state size: 512 bit (64 bytes)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_HASH_OUTPUT_SIZE_ MCUXCLELS_HASH_OUTPUT_SIZE_
+ * @brief Defines the output sizes of the supported hash algorithms (do not use for allocation)
+ * @ingroup mcuxClEls_Hash_Macros
+ * @{
+ */
+#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224 28U ///< SHA-224 output size: 224 bit (28 bytes)
+#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 32U ///< SHA-256 output size: 256 bit (32 bytes)
+#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384 48U ///< SHA-384 output size: 384 bit (48 bytes)
+#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512 64U ///< SHA-512 output size: 512 bit (64 bytes)
+/**
+ * @}
+ */
+
+/**
+ * @ingroup mcuxClEls_Hash_Macros
+ * @{
+ */
+#define MCUXCLELS_HASH_RTF_OUTPUT_SIZE ((size_t)32U) ///< Size of run-time fingerprint appended to the hash in @p pDigest in bytes, if #MCUXCLELS_HASH_RTF_OUTPUT_ENABLE was specified
+/**
+ * @}
+ *
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+
+/**
+ * @defgroup mcuxClEls_Hash_Types mcuxClEls_Hash_Types
+ * @brief Defines all types of @ref mcuxClEls_Hash
+ * @ingroup mcuxClEls_Hash
+ * @{
+ */
+
+/**
+ * @brief Command option bit field for #mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect.
+ *
+ * Bit field to configure #mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect. See @ref MCUXCLELS_HASH_ for possible options.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_HashOption_t word-wise
+    struct
+    {
+        uint32_t :2;         ///< RFU
+        uint32_t hashini :1; ///< Defines if the hash engine shall be initialized
+        uint32_t hashld :1;  ///< Defines if the hash engine shall be initialized with an externally provided digest
+        uint32_t hashmd :2;  ///< Defines which hash algorithm shall be used
+        uint32_t hashoe :1;  ///< Defines if the hash digest shall be moved to the output buffer
+        uint32_t rtfupd :1;  ///< RTF (Runtime Fingerprint) Update
+        uint32_t rtfoe :1;   ///< RTF (Runtime Fingerprint) Output Enabled
+        uint32_t :23;        ///< RFU
+    } bits;                  ///< Access #mcuxClEls_HashOption_t bit-wise
+} mcuxClEls_HashOption_t;
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * @defgroup mcuxClEls_Hash_Functions mcuxClEls_Hash_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Hash
+ * @ingroup mcuxClEls_Hash
+ * @{
+ */
+
+/**
+ * @brief Computes the hash of a message.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ *
+ * @param[in]       options     The command options. For more information, see #mcuxClEls_HashOption_t.
+ * @param[in]       pInput      Padded input data to be hashed
+ * @param[in]       inputLength Size of @p pInput in bytes. Since the input is padded, the length must be a multiple of the block size, see @ref MCUXCLELS_HASH_BLOCK_SIZE_.
+ * @param[in, out]  pDigest     Pointer to the memory area that contains/receives the (intermediate) hash digest, allocated by the caller, see @ref MCUXCLELS_HASH_STATE_SIZE_.
+ *
+ * The properties of some parameters change with respect to selected options.
+ *
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.hashini == #MCUXCLELS_HASH_INIT_ENABLE</dt>
+ *          <dd>@p options.hashld has no effect and shall be #MCUXCLELS_HASH_LOAD_DISABLE. No data is read from @p pDigest.</dd>
+ *
+ *      <dt>@p options.hashld == #MCUXCLELS_HASH_LOAD_DISABLE</dt>
+ *          <dd>@p pDigest is not expected to contain an initial state. No data is read from @p pDigest.</dd>
+ *
+ *      <dt>@p options.rtfoe == #MCUXCLELS_HASH_RTF_UPDATE_ENABLE</dt>
+ *          <dd>When this option is used the current runtime fingerprint (RTF) value will be appended to the output @p pDigest; an additional #MCUXCLELS_HASH_RTF_OUTPUT_SIZE bytes has to be allocated for @p pDigest.</dd>
+ *
+ *      <dt>@p options.hashoe == #MCUXCLELS_HASH_OUTPUT_ENABLE</dt>
+ *          <dd>The hash state is written to @p pDigest. The size varies depending on the choice of @p options.hashmd, for more information see @ref MCUXCLELS_HASH_STATE_SIZE_ . In cases where the state size and output size differ - see @ref MCUXCLELS_HASH_OUTPUT_SIZE_ -, the state must be truncated by the caller to obtain the final hash value.</dd>
+ *
+ *  </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hash_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hash_Async(
+    mcuxClEls_HashOption_t options,
+    uint8_t const * pInput,
+    size_t inputLength,
+    uint8_t * pDigest
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_SHA_DIRECT
+/**
+ * @brief Enables SHA-direct mode.
+ *
+ * If this mode is enabled, it allows the application processor to access the ELS hash
+ * engine, but at the same time it stops ELS operations from using the hash engine.
+ *
+ * Therefore, in SHA-direct mode, hashing can only be done with #mcuxClEls_Hash_ShaDirect.
+ * When SHA-direct mode is active, ELS operations which internally use the ELS hash engine
+ * will result in an operational error (see #MCUXCLELS_STATUS_HW_OPERATIONAL). To use those
+ * operations, disable SHA-direct mode. Please consult function descriptions to check
+ * whether and under which circumstances they internally use the ELS hash engine.
+ *
+ * ELS operations which do not internally use the ELS hash engine can be performed in
+ * parallel with a SHA-direct hash operation.
+ *
+ * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection)
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK                  on success
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ShaDirect_Enable)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ShaDirect_Enable(
+    void);
+
+/**
+ * @brief Disables SHA-direct mode.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK                  on success
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ShaDirect_Disable)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ShaDirect_Disable(
+    void);
+
+/**
+ * @brief Calculates the hash of a message using SHA-Direct mode.
+ *
+ * SHA-Direct mode must be enabled before calling this function. For more information, see #mcuxClEls_ShaDirect_Enable.
+ *
+ * In order to perform a hash calculation in SHA-Direct mode, the CPU must feed the input data to a register in ELS's SHA core, or configure a DMA to copy the input data to that register. A DMA can be used because feeding input data to the SHA core while the SHA core is busy results in an AHB bus stall, and there is no need to check any further flags before copying further data.
+ * If a DMA shall be used to perform this copy, a callback function must be provided by the caller that will configure and start the DMA.
+ * If no callback function is specified, this function will resort to using the CPU.
+ *
+ * @param[in]       options     The command options. For more information, see #mcuxClEls_HashOption_t.
+ * @param[in]       pInput      Padded input data to be hashed.
+ * @param[in]       inputLength Size of @p pInput in bytes. Since the input is padded, the length must be a multiple of the block size, see @ref MCUXCLELS_HASH_BLOCK_SIZE_.
+ * @param[in, out]  pDigest     Pointer to the memory area that contains/receives the (intermediate) hash digest, allocated by the caller, see @ref MCUXCLELS_HASH_STATE_SIZE_.
+ * @param[in]       pCallback   Callback function to load data into Sha core.
+ * @param[in, out]  pCallerData Pointer forwarded by the operation to the callback function.
+ *
+ * The properties of some parameters change with respect to selected options.
+ *
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.hashini == #MCUXCLELS_HASH_INIT_ENABLE</dt>
+ *          <dd>@p options.hashld has no effect and shall be #MCUXCLELS_HASH_LOAD_DISABLE. No data is read from @p pDigest. </dd>
+ *
+ *      <dt>@p options.hashld == #MCUXCLELS_HASH_LOAD_DISABLE</dt>
+ *          <dd>@p pDigest is not expected to contain an initial state. No data is read from @p pDigest. </dd>
+ *
+ *      <dt>@p options.hashoe == #MCUXCLELS_HASH_OUTPUT_ENABLE</dt>
+ *          <dd>The hash state is written to @p pDigest. The size varies depending on the choice of @p options.hashmd, for more information see @ref MCUXCLELS_HASH_STATE_SIZE_ . In cases where the state size and output size differ - see @ref MCUXCLELS_HASH_OUTPUT_SIZE_ -, the state must be truncated by the caller to obtain the final hash value.</dd>
+ *
+ *      <dt>@p pCallback != @c NULL </dt>
+ *          <dd>The callback function referenced by @p pCallback is called. Otherwise, the function uses a default implementation for the copy.</dd>
+ *  </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_SW_FAULT            if the callback returned an error
+ * @retval #MCUXCLELS_STATUS_OK                  on success
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hash_ShaDirect)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hash_ShaDirect(
+    mcuxClEls_HashOption_t options,
+    uint8_t const * pInput,
+    size_t inputLength,
+    uint8_t * pDigest,
+    mcuxClEls_TransferToRegisterFunction_t pCallback,
+    void * pCallerData
+    );
+#endif /* MCUXCL_FEATURE_ELS_SHA_DIRECT */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_HASH_H_ */
+
+/**
+ * @}
+ *
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hmac.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hmac.h
new file mode 100644
index 0000000000..7438ce30d6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hmac.h
@@ -0,0 +1,170 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Hmac.h
+ * @brief ELS header for HMAC support.
+ * 
+ * This header exposes functions that enable using the ELS for the generation of hashed-key message authentication
+ * codes (HMAC).
+ * The supported hash algorithm is SHA2-256.
+ */
+
+/**
+ * @defgroup mcuxClEls_Hmac mcuxClEls_Hmac
+ * @brief This part of the @ref mcuxClEls driver supports functionality for hashed-key message authentication codes.
+ * @ingroup mcuxClEls
+ * @{
+ */
+#ifndef MCUXCLELS_HMAC_H_
+#define MCUXCLELS_HMAC_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * MACROS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Hmac_Macros mcuxClEls_Hmac_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Hmac
+ * @ingroup mcuxClEls_Hmac
+ * @{
+ */
+/**
+ * @defgroup MCUXCLELS_HMAC_EXTERNAL_KEY_ MCUXCLELS_HMAC_EXTERNAL_KEY_
+ * @brief Defines valid options to be used by #mcuxClEls_HmacOption_t
+ * @ingroup mcuxClEls_Hmac_Macros
+ * @{
+ */
+#define MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE  1U ///< Set #mcuxClEls_HmacOption_t.extkey to this value to use an external key
+#define MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE 0U ///< Set #mcuxClEls_HmacOption_t.extkey to this value to use a key from the ELS keystore
+/**
+ * @}
+ */
+
+#define MCUXCLELS_HMAC_PADDED_KEY_SIZE ((size_t) 64U) ///< HMAC Key size: 64 bytes
+#define MCUXCLELS_HMAC_OUTPUT_SIZE ((size_t) 32U)     ///< HMAC Output size: 32 bytes
+/**
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Hmac_Types mcuxClEls_Hmac_Types
+ * @brief Defines all types of @ref mcuxClEls_Hmac
+ * @ingroup mcuxClEls_Hmac
+ * @{
+ */
+/**
+ * @brief Command option bit field for #mcuxClEls_Hmac_Async.
+ * 
+ * Valid option values can be found under @ref MCUXCLELS_HMAC_EXTERNAL_KEY_.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value; ///< Accesses the bit field as a full word
+    } word;             ///< Access #mcuxClEls_CipherOption_t word-wise
+    struct
+    {
+        uint32_t :13;       ///< RFU
+        uint32_t extkey :1; ///< Whether an external key should be used
+        uint32_t :18;       ///< RFU
+    } bits;                 ///< Access #mcuxClEls_CipherOption_t word-wise
+} mcuxClEls_HmacOption_t;
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Hmac_Functions mcuxClEls_Hmac_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Hmac
+ * @ingroup mcuxClEls_Hmac
+ * @{
+ */
+/**
+ * @brief Performs HMAC with SHA-256.
+ * 
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]      options     The command options. For more information, see #mcuxClEls_HmacOption_t.
+ * @param[in]      keyIdx      The HMAC key index, if an internal key shall be used
+ * @param[in]      pPaddedKey  Pointer to a memory location containing the padded HMAC key
+ * @param[in]      pInput      Pointer to a memory location which contains the data to be authenticated
+ * @param[in]      inputLength Size of @p pInput in bytes
+ * @param    [out] pOutput     The output message authentication code
+ * 
+ * The properties of some parameters change with respect to selected options.
+ *
+ * <dl>
+ *  <dt>Parameter properties</dt>
+ *
+ *  <dd><dl>
+ *      <dt>@p options.extkey == #MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE</dt>
+ *          <dd>@p keyIdx is ignored.
+ * 
+ *          @p pPaddedKey must contain the padded HMAC key, which can mean one of two things depending on the length of the original HMAC key, L<sub>kHMAC</sub>:
+ *          <ul><li>If L<sub>kHMAC</sub> &le; #MCUXCLELS_HMAC_PADDED_KEY_SIZE, @p pPaddedKey must be the HMAC key padded with zero-bytes to fill the required length of #MCUXCLELS_HMAC_PADDED_KEY_SIZE bytes.</li>
+ * 
+ *          <li>If L<sub>kHMAC</sub> &gt; #MCUXCLELS_HMAC_PADDED_KEY_SIZE, @p pPaddedKey must contain the SHA-256 hash of the HMAC key, padded with zero-bytes to fill the required length of #MCUXCLELS_HMAC_PADDED_KEY_SIZE bytes.</li></ul></dd>
+ * 
+ *      <dt>@p options.extkey == #MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE</dt>
+ *          <dd>@p keyIdx must be a valid key index with the correct usage rights for HMAC.
+ * 
+ *          @p pPaddedKey is ignored.</dd>
+ *
+ *  </dl></dd>
+ * </dl>
+ * 
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hmac_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hmac_Async(
+    mcuxClEls_HmacOption_t options,
+    mcuxClEls_KeyIndex_t keyIdx,
+    uint8_t const * pPaddedKey,
+    uint8_t const * pInput,
+    size_t inputLength,
+    uint8_t * pOutput
+    );
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_HMAC_H_ */
+/**
+ * @}
+ * 
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Kdf.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Kdf.h
new file mode 100644
index 0000000000..dcfe6fd6bd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Kdf.h
@@ -0,0 +1,338 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Kdf.h
+ * @brief ELS header for key derivation.
+ *
+ * This header exposes functions that enable using the ELS for various key derivation commands.
+ * The supported key derivation algorithms are CKDF, HKDF, TLS
+ */
+
+
+/**
+ * @defgroup mcuxClEls_Kdf mcuxClEls_Kdf
+ * @brief This part of the @ref mcuxClEls driver supports functionality for key derivation
+ * @ingroup mcuxClEls
+ * @{
+ */
+
+/**
+ * @defgroup mcuxClEls_Kdf_Macros mcuxClEls_Kdf_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Kdf
+ * @ingroup mcuxClEls_Kdf
+ * @{
+ */
+
+#ifndef MCUXCLELS_KDF_H_
+#define MCUXCLELS_KDF_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+
+
+
+
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+
+/**
+ * @defgroup mcuxClEls_Kdf_Define mcuxClEls_Kdf_Define
+ * @brief  constants
+ * @ingroup mcuxClEls_Kdf_Macros
+ * @{
+ */
+
+
+#define MCUXCLELS_CKDF_DERIVATIONDATA_SIZE               12u ///< Size of CKDF SP800-108 derivation data
+#define MCUXCLELS_CKDF_ALGO_SP800108                     0x0u ///< Use SP800-108 algorithm
+
+
+
+
+#define MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE 32u ///< Size of HKDF derivation data
+#define MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE     32u ///< Size of HKDF SP800-56C derived key
+
+#define MCUXCLELS_HKDF_VALUE_RTF_DERIV             ((uint32_t) 1u<< 0u) ///< Use RTF as derivation input
+#define MCUXCLELS_HKDF_VALUE_MEMORY_DERIV          ((uint32_t) 0u<< 0u) ///< Use derivation input from system memory
+
+#define MCUXCLELS_HKDF_ALGO_RFC5869                0x0u ///< Use RFC5869 algorithm
+#define MCUXCLELS_HKDF_ALGO_SP80056C               0x1u ///< Use SP800-56C algorithm
+
+#define MCUXCLELS_HKDF_RTF_DERIV                   1U ///< Use RTF as derivation input
+#define MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV         0U ///< Use derivation input from system memory
+
+#define MCUXCLELS_TLS_DERIVATIONDATA_SIZE          ((size_t) 80u) ///< Size of TLS derivation data
+#define MCUXCLELS_TLS_RANDOM_SIZE                  ((size_t) 32u) ///< Size of random bytes for TLS
+
+#define MCUXCLELS_TLS_INIT                         0u ///< Perform master key generation
+#define MCUXCLELS_TLS_FINALIZE                     1u ///< Perform session key generation
+
+/**
+ * @}
+ */ /* mcuxClEls_Kdf_Define */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+
+/**
+ * @defgroup mcuxClEls_Kdf_Types mcuxClEls_Kdf_Types
+ * @brief Defines all types of @ref mcuxClEls_Kdf
+ * @ingroup mcuxClEls_Kdf
+ * @{
+ */
+
+/** Internal command option bit field for CKDF functions. */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_HKDF_VALUE_
+    } word;
+    struct
+    {
+        uint32_t :12;
+        uint32_t ckdf_algo :2;  ///< Defines which algorithm and mode shall be used. This option is set internally and will be ignored:
+                                ///< #MCUXCLELS_CKDF_ALGO_SP800108  = Use SP800-108 algorithm
+        uint32_t :18;
+    } bits;
+} mcuxClEls_CkdfOption_t;
+
+/** Command option bit field for #mcuxClEls_Hkdf_Rfc5869_Async. */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_HKDF_VALUE_
+    } word;
+    struct
+    {
+        uint32_t rtfdrvdat :1;  ///< #MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV=use derivation input from system memory, #MCUXCLELS_HKDF_RTF_DERIV=use RTF (runtime fingerprint) as derivation input
+        uint32_t hkdf_algo :1;  ///< Defines which algorithm shall be used. This option is set internally and will be ignored:
+                                ///< #MCUXCLELS_HKDF_ALGO_RFC5869 = Use RFC5869 algorithm
+                                ///< #MCUXCLELS_HKDF_ALGO_SP80056C = Use SP800-56C algorithm
+        uint32_t :30;
+    } bits;
+} mcuxClEls_HkdfOption_t;
+
+/** Internal command option bit field for #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, and #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. */
+typedef union
+{
+    struct
+    {
+        uint32_t value;         ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_HKDF_VALUE_
+    } word;
+    struct
+    {
+        uint32_t :10;
+        uint32_t mode :1;       ///< Defines which phase of the key generation is performed. This option is set internally and will be ignored:
+                                ///< #MCUXCLELS_TLS_INIT  = Calculate master key from premaster key
+                                ///< #MCUXCLELS_TLS_FINALIZE = Calculate session keys from master key
+        uint32_t :21;
+    } bits;
+} mcuxClEls_TlsOption_t;
+
+/**
+ * @}
+ */ /* mcuxClEls_Kdf_Types */
+
+/**
+ * @}
+ */ /* mcuxClEls_Kdf_Macros */
+
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Kdf_Functions mcuxClEls_Kdf_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Kdf
+ * @ingroup mcuxClEls_Kdf
+ * @{
+ */
+
+
+/**
+ * @brief Derives a key using the HKDF (HMAC-based key derivation function) according to RFC5869.
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * @param[in] options The command options. For more information, see #mcuxClEls_HkdfOption_t.
+ * @param[in] derivationKeyIdx Key index used for derivation. Must be a 256-bit key with HKDF property bit set to 1.
+ * @param[in] targetKeyIdx Key bank number of the derived key. Will be a 256-bit key, the user must ensure there is enough space in the keystore to hold the derived key.
+ * @param[in] targetKeyProperties Requested properties for the derived key. The ksize field will be ignored.
+ * @param[in] pDerivationData The algorithm-specific derivation data, the length is #MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE bytes
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ *
+ *
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hkdf_Rfc5869_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Rfc5869_Async(
+    mcuxClEls_HkdfOption_t options,
+    mcuxClEls_KeyIndex_t derivationKeyIdx,
+    mcuxClEls_KeyIndex_t targetKeyIdx,
+    mcuxClEls_KeyProp_t targetKeyProperties,
+    uint8_t const * pDerivationData
+    );
+
+/** Derives a key using the HKDF (HMAC-based key derivation function) according to SP800-56C one-step approach with Sha2-256.
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in] derivationKeyIdx  Key index used for derivation. Must be a 256-bit key with HKDF property bit set to 1.
+ * @param[out] pTagetKey Memory area to store the derived key. Will be a 256-bit key, the user must ensure there is enough space in the keystore to hold the derived key.
+ * @param[in] pDerivationData The algorithm-specific derivation data
+ * @param[in] derivationDataLength Length of the derivation data
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hkdf_Sp80056c_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Sp80056c_Async(
+    mcuxClEls_KeyIndex_t derivationKeyIdx,
+    uint8_t * pTagetKey,
+    uint8_t const * pDerivationData,
+    size_t derivationDataLength
+    );
+
+
+/** Derives a key using the NIST SP 800-108 CMAC-based Extract-and-Expand Key Derivation Function.
+ * 
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ *   @param[in] derivationKeyIdx Key index used for derivation
+ *   @param[in] targetKeyIdx Key bank number of the derived key
+ *   @param[in] targetKeyProperties Requested properties for the derived key. Only set usage bits.
+ *   @param[in] pDerivationData The algorithm-specific derivation data, the length is #MCUXCLELS_CKDF_DERIVATIONDATA_SIZE bytes
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Ckdf_Sp800108_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Ckdf_Sp800108_Async(
+    mcuxClEls_KeyIndex_t derivationKeyIdx,
+    mcuxClEls_KeyIndex_t targetKeyIdx,
+    mcuxClEls_KeyProp_t targetKeyProperties,
+    uint8_t const * pDerivationData
+    );
+
+
+
+/** Generates a TLS master key based on a pre-master key and derivation data, according to the TLS 1.2 specification.
+ * The pre-master key is overwritten in this operation.
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in] pDerivationData The TLS derivation data, consisting of Label, Client Random and Server Random from the TLS 1.2 specification.
+ *                            Note: The order is different from #mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async.
+ * @param[in] keyProperties Desired key properties. Only #mcuxClEls_KeyProp_t::upprot_priv and #mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored.
+ * @param[in] keyIdx The index of the TLS pre-master key, which is overwritten with the master key
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async(
+    uint8_t const * pDerivationData,
+    mcuxClEls_KeyProp_t keyProperties,
+    mcuxClEls_KeyIndex_t keyIdx
+    );
+
+/** Generates TLS session keys based on a master key and derivation data, according to the TLS 1.2 specification.
+ * The master key and the following five key indices are overwritten in this operation.
+ * The keys are written in the following order:
+ * <ol>
+ *     <li> Client Encryption Key
+ *     <li> Client Message Authentication Key
+ *     <li> Server Encryption Key
+ *     <li> Server Message Authentication Key
+ * </ol>
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in] pDerivationData The TLS derivation data, consisting of Label, Server Random and Client Random from the TLS 1.2 specification.
+ *                            Note: The order is different from #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async.
+ * @param[in] keyProperties Desired key properties. Only #mcuxClEls_KeyProp_t::upprot_priv and #mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored.
+ * @param[in]  keyIdx  The index of the TLS master key, which is overwritten with one of the session keys.
+ *                     There must be three further consecutive unoccupied key indices following this index.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async(
+    uint8_t const * pDerivationData,
+    mcuxClEls_KeyProp_t keyProperties,
+    mcuxClEls_KeyIndex_t keyIdx
+    );
+
+/**
+ * @}
+ */ /* mcuxClEls_Kdf_Functions */
+
+/**
+ * @}
+ */ /* mcuxClEls_Kdf */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_KDF_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_KeyManagement.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_KeyManagement.h
new file mode 100644
index 0000000000..c0898a6bb3
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_KeyManagement.h
@@ -0,0 +1,332 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_KeyManagement.h
+ * @brief ELS header for key management.
+ *
+ * This header exposes functions that can be used to manage the keystore of ELS.
+ * This includes:
+ * - Importing keys
+ * @if MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT
+ * - Exporting keys
+ * @endif
+ * @if MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE
+ * - Deleting keys
+ * @endif
+ */
+
+/**
+ * @defgroup mcuxClEls_KeyManagement mcuxClEls_KeyManagement
+ * @brief This part of the @ref mcuxClEls driver supports functionality for keys management
+ * @ingroup mcuxClEls
+ * @{
+ */
+
+#ifndef MCUXCLELS_KEYMANAGEMENT_H_
+#define MCUXCLELS_KEYMANAGEMENT_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_KeyManagement_Macros mcuxClEls_KeyManagement_Macros
+ * @brief Defines all macros of @ref mcuxClEls_KeyManagement
+ * @ingroup mcuxClEls_KeyManagement
+ * @{
+ */
+
+/**
+ * @defgroup MCUXCLELS_KEYIMPORT_VALUE_KFMT_ MCUXCLELS_KEYIMPORT_VALUE_KFMT_
+ * @brief Defines valid options (word value) to be used by #mcuxClEls_KeyImport_Async
+ * @ingroup mcuxClEls_KeyManagement_Macros
+ *
+ * @{
+ */
+
+#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF      ((uint32_t) 0u<< 6u) ///< Key format UDF with shares in RTL or memory
+#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394  ((uint32_t) 1u<< 6u) ///< Key format RFC3394 with shares in memory
+#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF      ((uint32_t) 2u<< 6u) ///< Key from PUF
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PBK      ((uint32_t) 3u<< 6u) ///< Key from Public Key Certificate
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_KEYIMPORT_KFMT_ MCUXCLELS_KEYIMPORT_KFMT_
+ * @brief Defines valid options (bit values) to be used by #mcuxClEls_KeyImport_Async
+ * @ingroup mcuxClEls_KeyManagement_Macros
+ *
+ * @{
+ */
+#define MCUXCLELS_KEYIMPORT_KFMT_UDF             (0x00u) ///< Key format UDF with shares in RTL or memory
+#define MCUXCLELS_KEYIMPORT_KFMT_RFC3394         (0x01u) ///< Key format RFC3394 with shares in memory
+#define MCUXCLELS_KEYIMPORT_KFMT_PUF             (0x02u) ///< Key from PUF
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_KEYIMPORT_KFMT_PBK             (0x03u) ///< Key from Public Key Certificate
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE  (0x01U) ///< Reverse fetch enabled. For internal use
+#define MCUXCLELS_KEYIMPORT_REVERSEFETCH_DISABLE (0x00U) ///< Reverse fetch disabled. For internal use
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+#define MCUXCLELS_RFC3394_OVERHEAD               ((size_t) 16u)     ///< Overhead between RFC3394 blob and key size
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_RFC3394_ MCUXCLELS_RFC3394_
+ * @brief Defines specifying the length of RFC3394 containers
+ * @ingroup mcuxClEls_KeyManagement_Macros
+ *
+ * @{
+ */
+#define MCUXCLELS_RFC3394_CONTAINER_SIZE_128     ((size_t) 256u/8u) ///< Size of RFC3394 container for 128 bit key
+#define MCUXCLELS_RFC3394_CONTAINER_SIZE_256     ((size_t) 384u/8u) ///< Size of RFC3394 container for 256 bit key
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_RFC3394_CONTAINER_SIZE_P256    ((size_t) 640u/8u) ///< Size of RFC3394 container for P256 bit public key
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_KeyManagement_Types mcuxClEls_KeyManagement_Types
+ * @brief Defines all types of @ref mcuxClEls_KeyManagement
+ * @ingroup mcuxClEls_KeyManagement
+ * @{
+ */
+
+/**
+ * @brief Command option bit field for #mcuxClEls_KeyImport_Async
+ *
+ * Bit field to configure #mcuxClEls_KeyImport_Async. 
+ * See @ref MCUXCLELS_KEYIMPORT_KFMT_ for possible options in case the struct is accessed bit-wise.
+ * See @ref MCUXCLELS_KEYIMPORT_VALUE_KFMT_ for possible options in case the struct is accessed word-wise.
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t value;     ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_KEYIMPORT_VALUE_KFMT_
+    } word;                 ///< Access #mcuxClEls_KeyImportOption_t word-wise
+    struct
+    {
+        uint32_t :4;        ///< RFU
+        uint32_t revf :1;   ///< This field is managed internally
+        uint32_t :1;        ///< RFU
+        uint32_t kfmt :2;   ///< Defines the key import format, one of @ref MCUXCLELS_KEYIMPORT_KFMT_
+        uint32_t :24;       ///< RFU
+    } bits;                 ///< Access #mcuxClEls_KeyImportOption_t bit-wise
+} mcuxClEls_KeyImportOption_t;
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_KeyManagement_Functions mcuxClEls_KeyManagement_Functions
+ * @brief Defines all functions of @ref mcuxClEls_KeyManagement
+ * @ingroup mcuxClEls_KeyManagement
+ * @{
+ */
+
+/** 
+ * @brief Deletes a key from keystore at the given index.
+ * 
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]    keyIdx  The index of the key to be deleted
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_SW_FAULT            if a failure occurred
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyDelete_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyDelete_Async(
+        mcuxClEls_KeyIndex_t keyIdx
+);
+
+
+
+/** @brief Imports a key from external storage to an internal key register.
+ * 
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]    options          One of @ref MCUXCLELS_KEYIMPORT_KFMT_
+ * @param[in]    pImportKey       Pointer to the RFC3394 container of the key to be imported
+ * @param[in]    importKeyLength  Length of the RFC3394 container of the key to be imported
+ * @param[in]    wrappingKeyIdx   Index of the key wrapping key, if importing RFC3394 format
+ * @param[in]    targetKeyIdx     The desired key index of the imported key
+ *
+ *  <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p options.kfmt != #MCUXCLELS_KEYIMPORT_KFMT_RFC3394</dt><dd>
+ *       <ul style="list-style: none;">
+ *         <li>@p pImportKey is ignored.</li>
+ *         <li>@p importKeyLength is ignored.</li>
+ *         <li>@p wrappingKeyIdx is ignored.</li>
+ *         <li>@p targetKeyIdx is ignored. The unpacked key is automatically stored in key slots 0, 1.</li>
+ *       </ul></dd>
+ *     </dt>
+ *   </dl></dd>
+ *  </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyImport_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImport_Async(
+    mcuxClEls_KeyImportOption_t options,
+    uint8_t const * pImportKey,
+    size_t importKeyLength,
+    mcuxClEls_KeyIndex_t wrappingKeyIdx,
+    mcuxClEls_KeyIndex_t targetKeyIdx
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+/** @brief Imports a public key to an internal key register if the signature verification of the provided public key against
+ *         the provided signature is correct.
+ * 
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]    pCertificate       Pointer to the Certificate structure
+ * @param[in]    certificateLength  Length of the Certificate structure
+ * @param[in]    publicKeyOffset    Offset of the Public key to be imported within @p pCertificate
+ * @param[in]    pSignature         Signed challenge used to authenticate the imported key. Must be word aligned
+ * @param[in]    verifyingKeyIdx    The key index of the verifying public key
+ * @param[in]    keyProperties      The desired key properties of the imported key
+ * @param[in]    targetKeyIdx       The desired key index of the imported key
+ * @param[out]   pOutput            Pointer to the memory area which will receive the recalculated value of the R component in case of a successful
+ *                                  certificate verification. Must be word aligned
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyImportPuk_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImportPuk_Async(
+    uint8_t const * pCertificate,
+    size_t certificateLength,
+    size_t publicKeyOffset,
+    uint8_t const * pSignature,
+    mcuxClEls_KeyIndex_t verifyingKeyIdx,
+    mcuxClEls_KeyProp_t keyProperties,
+    mcuxClEls_KeyIndex_t targetKeyIdx,
+    uint8_t * pOutput	
+    );
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+
+/** @brief Exports a key from an internal key register to external storage, using a wrapping key.
+ * 
+ * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ * @endif
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]    wrappingKeyIdx     The key used for key wrapping
+ * @param[in]    exportKeyIdx       The key to export
+ * @param[out]   pOutput            The memory address of the exported key
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM    if invalid parameters were specified
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyExport_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyExport_Async(
+    mcuxClEls_KeyIndex_t wrappingKeyIdx, ///< [in]  The key used for key wrapping
+    mcuxClEls_KeyIndex_t exportKeyIdx,   ///< [in]  The key to export
+    uint8_t * pOutput                   ///< [out] The memory address of the exported key
+    );
+
+/** @brief Exports the properties of the keys stored in the ELS internal keystore
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[in]    keyIdx     Request key properties of the index defined here
+ * @param[out]   pKeyProp   Key properties of the index provided
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK                  on successful request */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetKeyProperties)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetKeyProperties(
+    mcuxClEls_KeyIndex_t keyIdx,
+    mcuxClEls_KeyProp_t * pKeyProp
+    );
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_KEYMANAGEMENT_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Rng.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Rng.h
new file mode 100644
index 0000000000..8bd1dc6907
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Rng.h
@@ -0,0 +1,435 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file mcuxClEls_Rng.h
+ * @brief ELS header for random number generation.
+ * This header exposes functions to configure the ELS RNGs (DRBG and DTRNG) and to generate random data.
+ */
+
+#ifndef MCUXCLELS_RNG_H_
+#define MCUXCLELS_RNG_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxClEls_Common.h> // Common functionality
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup mcuxClEls_Rng mcuxClEls_Rng
+ * @brief This part of the @ref mcuxClEls driver supports functionality for random number generation
+ * @ingroup mcuxClEls
+ * @{
+ */
+
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Rng_Macros mcuxClEls_Rng_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Rng
+ * @ingroup mcuxClEls_Rng
+ * @{
+ */
+#define MCUXCLELS_RNG_DTRNG_CONFIG_SIZE       ((uint8_t) 84)   ///< Size of DTRNG configuration
+#define MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE  ((uint8_t) 52)   ///< Size of DTRNG characterization data
+#define MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE  ((uint8_t) 188)  ///< Size of DTRNG characterization result
+
+#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE  4U                      ///< Minimum output size of #mcuxClEls_Rng_DrbgTestExtract_Async
+#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE  ((uint32_t) 1U << 16U)  ///< Maximum output size of #mcuxClEls_Rng_DrbgTestExtract_Async
+
+#define MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE ((uint32_t) 0U) ///< Command options value for DRBG Test Instantiate command. For internal use
+#define MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT     ((uint32_t) 1U) ///< Command options value for DRBG Test Extract command. For internal use
+#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB     ((uint32_t) 3U) ///< Command options value for DRBG Test AES-ECB command. For internal use
+#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR     ((uint32_t) 2U) ///< Command options value for DRBG Test AES-CTR command. For internal use
+
+#ifdef MCUXCL_FEATURE_ELS_RND_RAW
+#define MCUXCLELS_RNG_RND_REQ_RND_RAW            ((uint32_t) 1U << 1) ///< Command options value for RND_REQ command. For internal use
+#define MCUXCLELS_RNG_RAW_ENTROPY_SIZE           ((uint32_t) 32U)     ///< Fixed size of raw entropy when using the DTRNG
+#endif /* MCUXCL_FEATURE_ELS_RND_RAW */
+#ifdef MCUXCL_FEATURE_ELS_PRND_INIT
+#define MCUXCLELS_RNG_RND_REQ_PRND_INIT          ((uint32_t) 1U << 0) ///< Command options value for PRND_INIT command. For internal use
+#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */
+/**
+ * @}
+ */
+
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Rng_Functions mcuxClEls_Rng_Functions
+ * @brief Defines all functions of @ref mcuxClEls_Rng
+ * @ingroup mcuxClEls_Rng
+ * @{
+ */
+
+/**
+ * @brief Writes random data from the ELS DRBG to the given buffer.
+ *
+ * This function fills a buffer with random values from the DRBG. The DRBG provides 128 bits of security strength.
+ *
+ * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.
+ *
+ * If the random values from the DRBG are later used as a cryptographic key, the security strength of the cryptographic operation using the generated key should not exceed that of the DRBG.
+ *
+ * To name a few examples, this means (as per NIST SP 800-57 Part 1 Rev. 5):
+ * - AES-192 or AES-256 keys generated with this function will provide only 128 bits of security strength
+ * - RSA keys longer than 3072 bits will provide only 128 bits of security strength
+ * - ECC keys longer than 383 bits will provide only 128 bits of security strength
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[out] pOutput       Pointer to the beginning of the memory area to fill with random data
+ * @param[in]  outputLength  Number of requested random bytes
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p outputLength </dt>
+ *       <dd>supported values are #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE bytes up to
+ *           #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE bytes. The size must be a multiple of 4.</dd>
+ *   </dl></dd>
+ * </dl>
+ * 
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_SW_FAULT            in case of an internal error
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgRequest_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequest_Async(
+    uint8_t * pOutput,
+    size_t outputLength
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_RND_RAW
+/**
+ * @brief Writes 32 bytes of raw random data from the ELS TRNG to the given buffer.
+ *
+ * This function fills a buffer with raw (unprocessed) random values from the TRNG. 
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @param[out] pOutput       Pointer to the beginning of the memory area to fill with random data
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgRequestRaw_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequestRaw_Async(
+    uint8_t * pOutput
+    );
+#endif /* MCUXCL_FEATURE_ELS_RND_RAW */
+
+/**
+ * @brief Instantiates the DRBG in test mode.
+ *
+ * This function is a support function for FIPS CAVP testing. This function turns the ELS internal DRBG in test mode by loading known entropy from system memory.
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode.
+ * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.
+ *
+ * @param[in] pEntropy  Pointer to the input entropy data
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestInstantiate_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestInstantiate_Async(
+    uint8_t const * pEntropy
+    );
+
+/**
+ * @brief Performs a DRBG extraction.
+ *
+ * This function is a support function for FIPS CAVP testing. This function mimics the behavior of #mcuxClEls_Rng_DrbgRequest_Async and fills a buffer with random data when DRBG is in test mode.
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode.
+ * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.
+ *
+ * @attention #mcuxClEls_Rng_DrbgTestInstantiate_Async must be called prior to this function.
+ *
+ * @param[out] pOutput       Pointer to the output random number
+ * @param[in]  outputLength  Length of the random number
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p outputLength </dt>
+ *       <dd>supported values are #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE bytes up to
+ *           #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE bytes. The size must be a multiple of 4.</dd>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref MCUXCLELS_STATUS_ and @ref mcuxCsslFlowProtection)
+ * @else
+ *  @return An error code (see @ref MCUXCLELS_STATUS_)
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestExtract_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestExtract_Async(
+    uint8_t * pOutput,
+    size_t outputLength
+    );
+
+/**
+ * @brief Encrypts data using the AES-ECB engine of the DRBG.
+ *
+ * This function is a support function for FIPS CAVP testing. This function performs an AES-ECB encryption on system data to evaluate the encryption engine of the DRBG.
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode.
+ * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.
+ *
+ * @param[in]  pDataKey  Pointer to the data and key
+ * @param[out] pOutput   Pointer to the encrypted output
+ *
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestAesEcb_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesEcb_Async(
+    uint8_t const * pDataKey,
+    uint8_t * pOutput
+    );
+
+/**
+ * @brief Encrypts data using the AES-CTR engine of the DRBG.
+ *
+
+ * This function is a support function for FIPS CAVP testing. This function performs an AES-CTR encryption on system data to evaluate the encryption engine of the DRBG in test mode.
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode.
+ * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.
+ *
+ * @param[in]  pData       Pointer to the data to be encrypted
+ * @param[in]  dataLength  Length of the data to be encrypted
+ * @param[in]  pIvKey      Pointer to the IV and key
+ * @param[out] pOutput     Pointer to the encrypted output
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestAesCtr_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesCtr_Async(
+    uint8_t const * pData,
+    size_t dataLength,
+    uint8_t const * pIvKey,
+    uint8_t * pOutput
+    );
+
+/**
+ * @brief Loads a configuration of the ELS DTRNG.
+ *
+ * This function overwrites the default DTRNG configuration in order to optimize or fine tune the DTRNG entropy gathering process.
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ * Note that the TRNG configuration set by this function is non-persistent and any reset of the ELS (e.g. a power-cycle or calling #mcuxClEls_Reset_Async) will resets the DTRNG configuration to its default value.
+ *
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT
+ * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable).
+ * @endif
+ *
+ * @param[in] pInput  The pointer to DTRNG initialization data
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p pInput </dt>
+ *       <dd>The size is #MCUXCLELS_RNG_DTRNG_CONFIG_SIZE bytes.</dd>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_Dtrng_ConfigLoad_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigLoad_Async(
+    uint8_t const * pInput
+    );
+
+
+/**
+ * @brief Performs characterization of the ELS DTRNG.
+ *
+ * This function evaluates a DTRNG configuration for device specific characterization. The configuration used for characterization has to be placed in system memory.
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @attention If this function is called once, all other ELS commands except #mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async are blocked until any reset of the ELS (e.g. a power-cycle or calling #mcuxClEls_Reset_Async) is triggered.
+ *
+ * @param[in]  pInput  The pointer to DTRNG initialization data
+ * @param[out] pOutput The pointer to the evaluation result
+ *
+ * <dl>
+ *   <dt>Parameter properties</dt>
+ *   <dd><dl>
+ *     <dt>@p pInput </dt>
+ *       <dd>The size is #MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE bytes.</dd>
+ *     <dt>@p pOutput </dt>
+ *       <dd>The size is #MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE bytes.</dd>
+ *   </dl></dd>
+ * </dl>
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async(
+    uint8_t const * pInput,
+    uint8_t * pOutput
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_PRND_INIT
+/**
+ * @brief Initializes the ELS PRNG.
+ *
+ * This function initializes the PRNG. After this operation #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with lower security strength at the time of the call.
+ *
+ * Call #mcuxClEls_WaitForOperation to complete the operation.
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request
+ * @retval #MCUXCLELS_STATUS_OK_WAIT             on successful request
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_Init_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_Init_Async(void);
+#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */
+
+/**
+ * @brief Returns one random word from the ELS PRNG.
+ *
+ * This function returns one low-quality random CPU word gathered from the PRNG.
+ *
+ * @attention PRNG has to be initialized prior to the first time calling this function.
+ *
+ * @param[out] pWord  The pointer to the random word
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_OK  on successful request
+ * @retval #MCUXCLELS_STATUS_HW_PRNG in case of insufficient entropy
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_GetRandomWord)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandomWord(
+    uint32_t * pWord
+    );
+
+/**
+ * @brief Writes random data from the ELS PRNG to the given buffer.
+ *
+ * This function fills a buffer with low-quality random values gathered from the PRNG.
+ *
+ * @attention PRNG has to be initialized prior to the first time calling this function.
+ *
+ * @param[out] pOutput       Pointer to the beginning of the memory area to fill with random data from PRNG
+ * @param[in]  outputLength  Size of @p pOutput in bytes
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_OK  on successful request
+ * @retval #MCUXCLELS_STATUS_HW_PRNG in case of insufficient entropy
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_GetRandom)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandom(
+    uint8_t * pOutput,
+    size_t outputLength
+    );
+
+#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING
+/**
+ * @brief This function checks if a DRBG reseeding is needed and if so reseeds the ELS DRBG.
+ *
+ * This function checks if the ELS DRBG needs to be reseeded by the DTRNG, and if so, executes the iterative seeding process.
+ * The function internally disables ELS interrupts before (potentially) running the iterative seeding process and restores
+ * the original ELS interrupt enable flags afterwards, before returning to the caller. This allows to properly use the function
+ * in an ELS interrupt handler to reseed the ELS DRBG when needed.
+ * 
+ * @param[in]  pDtrngConfig  Pointer to the beginning of the memory area which contains the ELS DTRNG config
+ *
+ * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL)
+ *  @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @else
+ *  @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ * @endif
+ * @retval #MCUXCLELS_STATUS_OK  on successful request
+ * @retval #MCUXCLELS_STATUS_SW_FAULT in case the iterative seeding failed
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed(const uint8_t *pDtrngConfig);
+#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */
+
+/**
+ * @}
+ */ /* mcuxClEls_Rng_Functions */
+
+
+/**
+ * @}
+ */ /* mcuxClEls_Rng */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_RNG_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Types.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Types.h
new file mode 100644
index 0000000000..ddf80e82b6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Types.h
@@ -0,0 +1,306 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_Types.h
+ * @brief ELS type header.
+ *
+ * This header defines types that are used by other mcuxClEls headers.
+ */
+/**
+ * @defgroup mcuxClEls_Types mcuxClEls_Types
+ * @brief This part of the @ref mcuxClEls driver defines common types
+ * @ingroup mcuxClEls
+ * @{
+ */
+#ifndef MCUXCLELS_TYPES_H_
+#define MCUXCLELS_TYPES_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxCsslFlowProtection.h>
+
+#include <mcuxClEls_mapping.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * MACROS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Types_Macros mcuxClEls_Types_Macros
+ * @brief Defines all macros of @ref mcuxClEls_Types
+ * @ingroup mcuxClEls_Types
+ * @{
+ */
+
+#define MCUXCLELS_KEY_SLOTS (20U) ///< Number of key slots in the ELS key store.
+
+/** @defgroup MCUXCLELS_KEYPROPERTY_VALUE_ MCUXCLELS_KEYPROPERTY_VALUE_
+ * @brief Constants for initalizing #mcuxClEls_KeyProp_t.word
+ * @ingroup mcuxClEls_Types_Macros
+ * @{
+ */
+#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128         ((uint32_t) 0u<< 0u) ///< 128-bit key
+#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256         ((uint32_t) 1u<< 0u) ///< 256-bit key
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_512         ((uint32_t) 3u<< 0u) ///< 512-bit key
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+#define MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE               ((uint32_t) 1u<< 5u) ///< Key is active (loaded)
+#define MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT            ((uint32_t) 1u<< 6u) ///< First part of multi-slot key
+#define MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT ((uint32_t) 1u<< 7u) ///< General purpose key slot
+#define MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT       ((uint32_t) 1u<< 8u) ///< Retention key slot
+#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT          ((uint32_t) 1u<< 9u) ///< Hardware output key slot
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_KEYPROPERTY_VALUE_PUK                  ((uint32_t) 1u<<11u) ///< Trusted Public Key
+#define MCUXCLELS_KEYPROPERTY_VALUE_TECDH                ((uint32_t) 1u<<12u) ///< Private key that can only be used in ECDH with Trusted Public Key
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+#define MCUXCLELS_KEYPROPERTY_VALUE_CMAC                 ((uint32_t) 1u<<13u) ///< CMAC key
+#define MCUXCLELS_KEYPROPERTY_VALUE_KSK                  ((uint32_t) 1u<<14u) ///< Key signing key
+#define MCUXCLELS_KEYPROPERTY_VALUE_RTF                  ((uint32_t) 1u<<15u) ///< RTF signing key
+#define MCUXCLELS_KEYPROPERTY_VALUE_CKDF                 ((uint32_t) 1u<<16u) ///< CKDF signing key
+#define MCUXCLELS_KEYPROPERTY_VALUE_HKDF                 ((uint32_t) 1u<<17u) ///< HKDF signing key
+#define MCUXCLELS_KEYPROPERTY_VALUE_ECSGN                ((uint32_t) 1u<<18u) ///< ECC signing key
+#define MCUXCLELS_KEYPROPERTY_VALUE_ECDH                 ((uint32_t) 1u<<19u) ///< ECC Diffie Hellman private key
+#define MCUXCLELS_KEYPROPERTY_VALUE_AES                  ((uint32_t) 1u<<20u) ///< AES key
+#define MCUXCLELS_KEYPROPERTY_VALUE_HMAC                 ((uint32_t) 1u<<21u) ///< HMAC key
+#define MCUXCLELS_KEYPROPERTY_VALUE_KWK                  ((uint32_t) 1u<<22u) ///< Key Wrapping Key
+#define MCUXCLELS_KEYPROPERTY_VALUE_KUOK                 ((uint32_t) 1u<<23u) ///< Key Unwrapping Only Key
+#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET ((uint32_t) 1u<<24u) ///< TLS Premaster Secret
+#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET    ((uint32_t) 1u<<25u) ///< TLS Master Secret
+#define MCUXCLELS_KEYPROPERTY_VALUE_KGSRC                ((uint32_t) 1u<<26u) ///< Can provide key material input for ECC key generation
+#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT               ((uint32_t) 1u<<27u) ///< A key to be used in a hardware out key slot
+#define MCUXCLELS_KEYPROPERTY_VALUE_WRPOK                ((uint32_t) 1u<<28u) ///< The key can be wrapped
+#define MCUXCLELS_KEYPROPERTY_VALUE_DUK                  ((uint32_t) 1u<<29u) ///< Device Unique Key
+#define MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED           ((uint32_t) 1u<<30u) ///< Caller must be in privileged mode to use the key
+#define MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED        ((uint32_t) 0u<<30u) ///< Caller does not have to be in privileged mode to use the key
+#define MCUXCLELS_KEYPROPERTY_VALUE_SECURE               ((uint32_t) 0u<<31u) ///< Caller must be in secure mode to use the key
+#define MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE            ((uint32_t) 1u<<31u) ///< Caller does not have to be in secure mode to use the key
+/**
+ * @}
+ */
+
+/** @defgroup MCUXCLELS_KEYPROPERTY_ MCUXCLELS_KEYPROPERTY_
+ * @brief Constants for initalizing #mcuxClEls_KeyProp_t.bits
+ * @ingroup mcuxClEls_Types_Macros
+ * @{
+ */
+#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_128               (0U) ///< This value of #mcuxClEls_KeyProp_t.ksize indicates a 128 bit key
+#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_256               (1U) ///< This value of #mcuxClEls_KeyProp_t.ksize indicates a 256 bit key
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_512               (3U) ///< This value of #mcuxClEls_KeyProp_t.ksize indicates a 512 bit key
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+#define MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE                (1U) ///< This value of #mcuxClEls_KeyProp_t.kactv indicates that the slot contains an active key
+#define MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE               (0U) ///< This value of #mcuxClEls_KeyProp_t.kactv indicates that the slot does not contain active key
+#define MCUXCLELS_KEYPROPERTY_BASE_SLOT                  (1U) ///< This value of #mcuxClEls_KeyProp_t.kbase indicates that the slot is the base slot of a 2-slot key
+#define MCUXCLELS_KEYPROPERTY_SECOND_SLOT                (0U) ///< This value of #mcuxClEls_KeyProp_t.kbase indicates that the slot is the second slot of a 2-slot key
+#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE  (1U) ///< This value of #mcuxClEls_KeyProp_t.fgp indicates that the slot is a retention key slot or a hardware out key slot
+#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE (0U) ///< This value of #mcuxClEls_KeyProp_t.fgp indicates that the slot is a neither retention key slot nor hardware out key slot
+#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE        (1U) ///< This value of #mcuxClEls_KeyProp_t.frtn indicates that the slot is a retention key slot
+#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE       (0U) ///< This value of #mcuxClEls_KeyProp_t.frtn indicates that the slot is not a retention key slot
+#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE           (1U) ///< This value of #mcuxClEls_KeyProp_t.fhwo indicates that the slot is a hardware out key slot
+#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE          (0U) ///< This value of #mcuxClEls_KeyProp_t.fhwo indicates that the slot is not a hardware out key slot
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+#define MCUXCLELS_KEYPROPERTY_PUK_TRUE                   (1U) ///< This value of #mcuxClEls_KeyProp_t.upuk indicates that the slot is a Trusted Public Key
+#define MCUXCLELS_KEYPROPERTY_PUK_FALSE                  (0U) ///< This value of #mcuxClEls_KeyProp_t.upuk indicates that the slot is not a Trusted Public Key
+#define MCUXCLELS_KEYPROPERTY_TECDH_TRUE                 (1U) ///< This value of #mcuxClEls_KeyProp_t.utecdh indicates that the slot is a Private key that can only be used in ECDH with Trusted Public Key
+#define MCUXCLELS_KEYPROPERTY_TECDH_FALSE                (0U) ///< This value of #mcuxClEls_KeyProp_t.utecdh indicates that the slot is not a Private key that can only be used in ECDH with Trusted Public Key
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+#define MCUXCLELS_KEYPROPERTY_CMAC_TRUE                  (1U) ///< This value of #mcuxClEls_KeyProp_t.ucmac indicates that the key can be used for CMAC
+#define MCUXCLELS_KEYPROPERTY_CMAC_FALSE                 (0U) ///< This value of #mcuxClEls_KeyProp_t.ucmac indicates that the key cannot be used for CMAC
+#define MCUXCLELS_KEYPROPERTY_KSK_TRUE                   (1U) ///< This value of #mcuxClEls_KeyProp_t.uksk indicates that the key can be used for key signing
+#define MCUXCLELS_KEYPROPERTY_KSK_FALSE                  (0U) ///< This value of #mcuxClEls_KeyProp_t.uksk indicates that the key cannot be used for key signing
+#define MCUXCLELS_KEYPROPERTY_RTF_TRUE                   (1U) ///< This value of #mcuxClEls_KeyProp_t.urtf indicates that the key can be used for RTF signing
+#define MCUXCLELS_KEYPROPERTY_RTF_FALSE                  (0U) ///< This value of #mcuxClEls_KeyProp_t.urtf indicates that the key cannot be used for RTF signing
+#define MCUXCLELS_KEYPROPERTY_CKDF_TRUE                  (1U) ///< This value of #mcuxClEls_KeyProp_t.uckdf indicates that the key can be used for CKDF
+#define MCUXCLELS_KEYPROPERTY_CKDF_FALSE                 (0U) ///< This value of #mcuxClEls_KeyProp_t.uckdf indicates that the key cannot be used for CKDF
+#define MCUXCLELS_KEYPROPERTY_HKDF_TRUE                  (1U) ///< This value of #mcuxClEls_KeyProp_t.uhkdf indicates that the key can be used for HKDF
+#define MCUXCLELS_KEYPROPERTY_HKDF_FALSE                 (0U) ///< This value of #mcuxClEls_KeyProp_t.uhkdf indicates that the key cannot be used for HKDF
+#define MCUXCLELS_KEYPROPERTY_ECC_TRUE                   (1U) ///< This value of #mcuxClEls_KeyProp_t.uecsg indicates that the key can be used for ECC signing
+#define MCUXCLELS_KEYPROPERTY_ECC_FALSE                  (0U) ///< This value of #mcuxClEls_KeyProp_t.uecsg indicates that the key cannot be used for ECC signing
+#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE        (1U) ///< This value of #mcuxClEls_KeyProp_t.uecdh indicates that the key is a ECC Diffie Hellman private key
+#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE       (0U) ///< This value of #mcuxClEls_KeyProp_t.uecdh indicates that the key is not an ECC Diffie Hellman private key
+#define MCUXCLELS_KEYPROPERTY_AES_TRUE                   (1U) ///< This value of #mcuxClEls_KeyProp_t.uaes indicates that the key is an AES key
+#define MCUXCLELS_KEYPROPERTY_AES_FALSE                  (0U) ///< This value of #mcuxClEls_KeyProp_t.uaes indicates that the key is not an AES key
+#define MCUXCLELS_KEYPROPERTY_HMAC_TRUE                  (1U) ///< This value of #mcuxClEls_KeyProp_t.uhmac indicates that the key is an HMAC key
+#define MCUXCLELS_KEYPROPERTY_HMAC_FALSE                 (0U) ///< This value of #mcuxClEls_KeyProp_t.uhmac indicates that the key is not an HMAC key
+#define MCUXCLELS_KEYPROPERTY_KWK_TRUE                   (1U) ///< This value of #mcuxClEls_KeyProp_t.ukwk indicates that the key is a Key Wrapping Key
+#define MCUXCLELS_KEYPROPERTY_KWK_FALSE                  (0U) ///< This value of #mcuxClEls_KeyProp_t.ukwk indicates that the key is not a Key Wrapping Key
+#define MCUXCLELS_KEYPROPERTY_KUOK_TRUE                  (1U) ///< This value of #mcuxClEls_KeyProp_t.ukuok indicates that the key is a Key Unwrapping Only Key
+#define MCUXCLELS_KEYPROPERTY_KUOK_FALSE                 (0U) ///< This value of #mcuxClEls_KeyProp_t.ukuok indicates that the key is not a Key Unwrapping Only Key
+#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE  (1U) ///< This value of #mcuxClEls_KeyProp_t.utlspms indicates that the key is a TLS Premaster Secret
+#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE (0U) ///< This value of #mcuxClEls_KeyProp_t.utlspms indicates that the key is not a TLS Premaster Secret
+#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE     (1U) ///< This value of #mcuxClEls_KeyProp_t.utlsms indicates that the key is a TLS Master Secret
+#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE    (0U) ///< This value of #mcuxClEls_KeyProp_t.utlsms indicates that the key is not a TLS Master Secret
+#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE         (1U) ///< This value of #mcuxClEls_KeyProp_t.ukgsrc indicates that the key can be used as key material input for ECC key generation
+#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE        (0U) ///< This value of #mcuxClEls_KeyProp_t.ukgsrc indicates that the key cannot be used as key material input for ECC key generation
+#define MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE                (1U) ///< This value of #mcuxClEls_KeyProp_t.uhwo indicates that the key can be used in a hardware out key slot
+#define MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE               (0U) ///< This value of #mcuxClEls_KeyProp_t.uhwo indicates that the key cannot be used in a hardware out key slot
+#define MCUXCLELS_KEYPROPERTY_WRAP_TRUE                  (1U) ///< This value of #mcuxClEls_KeyProp_t.wrpok indicates that the key can be wrapped
+#define MCUXCLELS_KEYPROPERTY_WRAP_FALSE                 (0U) ///< This value of #mcuxClEls_KeyProp_t.wrpok indicates that the key cannot be wrapped
+#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE         (1U) ///< This value of #mcuxClEls_KeyProp_t.duk indicates that the key is a Device Unique Key
+#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE        (0U) ///< This value of #mcuxClEls_KeyProp_t.duk indicates that the key is not a Device Unique Key
+#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE            (1U) ///< This value of #mcuxClEls_KeyProp_t.upprot_priv indicates that the caller must be in privileged mode to use the key
+#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE           (0U) ///< This value of #mcuxClEls_KeyProp_t.upprot_priv indicates that the caller does not need to be in privileged mode to use the key
+#define MCUXCLELS_KEYPROPERTY_SECURE_TRUE                (0U) ///< This value of #mcuxClEls_KeyProp_t.upprot_sec indicates that the caller must be in secure mode to use the key
+#define MCUXCLELS_KEYPROPERTY_SECURE_FALSE               (1U) ///< This value of #mcuxClEls_KeyProp_t.upprot_sec indicates that the caller does not need to be in secure mode to use the key
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MCUXCLELS_STATUS_ MCUXCLELS_STATUS_
+ * @brief Return code definitions
+ * @ingroup mcuxClEls_Types_Macros
+ * @{
+ */
+#define MCUXCLELS_STATUS_OK                   ((mcuxClEls_Status_t) 0x05552E03u) ///< No error occurred
+#define MCUXCLELS_STATUS_OK_WAIT              ((mcuxClEls_Status_t) 0x05552E07u) ///< An <tt>_Async</tt> function successfully started an ELS command. Call #mcuxClEls_WaitForOperation to complete it
+#define MCUXCLELS_STATUS_HW_FAULT             ((mcuxClEls_Status_t) 0x05555330u) ///< ELS hardware detected a fault
+#define MCUXCLELS_STATUS_HW_ALGORITHM         ((mcuxClEls_Status_t) 0x05555334u) ///< An algorithm failed in hardware
+#define MCUXCLELS_STATUS_HW_OPERATIONAL       ((mcuxClEls_Status_t) 0x05555338u) ///< ELS was operated incorrectly
+#define MCUXCLELS_STATUS_HW_BUS               ((mcuxClEls_Status_t) 0x0555533Cu) ///< A bus access failed
+#define MCUXCLELS_STATUS_HW_INTEGRITY         ((mcuxClEls_Status_t) 0x05555370u) ///< An integrity check failed in hardware
+#define MCUXCLELS_STATUS_HW_PRNG              ((mcuxClEls_Status_t) 0x05555374u) ///< Read access to PRNG output while PRNG is not in ready state
+#define MCUXCLELS_STATUS_HW_DTRNG             ((mcuxClEls_Status_t) 0x05555378u) ///< Unable to get entropy from dTRNG with current configuration
+#define MCUXCLELS_STATUS_SW_FAULT             ((mcuxClEls_Status_t) 0x0555F0F0u) ///< Software detected a fault
+#define MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT  ((mcuxClEls_Status_t) 0x055553B0u) ///< an ELS command was started while the ELS was still busy, or a SHA-Direct command was started while the SHA kernel was still busy
+#define MCUXCLELS_STATUS_SW_INVALID_PARAM     ((mcuxClEls_Status_t) 0x055553F8u) ///< Incorrect parameters were supplied
+#define MCUXCLELS_STATUS_SW_INVALID_STATE     ((mcuxClEls_Status_t) 0x055553B8u) ///< This can happen when ELS is in a wrong state for the requested ELS command
+#define MCUXCLELS_STATUS_SW_COUNTER_EXPIRED   ((mcuxClEls_Status_t) 0x055553BCu) ///< A software counter expired while waiting for an ELS operation to finish
+#define MCUXCLELS_STATUS_SW_COMPARISON_FAILED ((mcuxClEls_Status_t) 0x05558930u) ///< A comparison between an ELS flag and its expected value failed
+#ifdef MCUXCL_FEATURE_ELS_LOCKING
+#define MCUXCLELS_STATUS_SW_LOCKING_FAILED    ((mcuxClEls_Status_t) 0x055553F4u) ///< Unable to obtain ELS lock
+#define MCUXCLELS_STATUS_SW_STATUS_LOCKED     ((mcuxClEls_Status_t) 0x05552E0Bu) ///< ELS status is locked
+#endif /* MCUXCL_FEATURE_ELS_LOCKING */
+/** @} */
+
+#define MCUXCLELS_STATUS_IS_HW_ERROR(x_) ((((mcuxClEls_Status_t) (x_)) & 0x0000FF00U) == 0x0000E100U) ///< Checks whether an error code is a hardware error. Indicates that an error was reported by ELS hardware.
+
+#define MCUXCLELS_STATUS_IS_SW_ERROR(x_) ((((mcuxClEls_Status_t) (x_)) & 0x0000FF00U) == 0x0000F000U) ///< Checks whether an error code is a software error. Indicates that the error was detected by the driver software and not by ELS hardware.
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @defgroup mcuxClEls_Types_Types mcuxClEls_Types_Types
+ * @brief Defines all types of @ref mcuxClEls_Types
+ * @ingroup mcuxClEls_Types
+ * @{
+ */
+/**
+ * @brief Type for ELS driver status codes
+ */
+typedef uint32_t mcuxClEls_Status_t;
+
+/**
+ * @brief Deprecated type for ELS driver protected status codes
+ */
+typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Status_Protected_t;
+
+/**
+ * @brief Type for ELS keystore indices
+ */
+typedef uint32_t mcuxClEls_KeyIndex_t;
+
+/** Type for ELS key store key properties */
+typedef union
+{
+    struct
+    {
+        uint32_t value;          ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_KEYPROPERTY_VALUE_
+    } word;                      ///< Access #mcuxClEls_KeyProp_t word-wise
+    struct
+    {
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+        uint32_t ksize :2;       ///< Key size
+        uint32_t :3;             ///< RFU
+#else
+        uint32_t ksize :1;       ///< Key size
+        uint32_t :4;             ///< RFU
+#endif
+        uint32_t kactv :1;       ///< Status flag to indicate whether the key slot contains an active key or not
+        uint32_t kbase :1;       ///< Status flag to indicate whether the key slot is a base slot or the second slot of a 256-bit key
+        uint32_t fgp :1;         ///< Hardware feature flag: General purpose key slot
+        uint32_t frtn :1;        ///< Hardware feature flag: Retention key slot
+        uint32_t fhwo :1;        ///< Hardware feature flag: Hardware-out key slot
+#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
+        uint32_t :1;             ///< RFU
+        uint32_t upuk :1;        ///< Usage permission for Trusted Public Key
+        uint32_t utecdh :1;      ///< Usage permission for Private key that can only be used in ECDH with Trusted Public Key
+#else
+        uint32_t :3;             ///< RFU
+#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
+        uint32_t ucmac :1;       ///< Usage permission for CMAC
+        uint32_t uksk :1;        ///< Usage permission for key signing
+        uint32_t urtf :1;        ///< Usage permission for RTF signing
+        uint32_t uckdf :1;       ///< Usage permission for CKDF
+        uint32_t uhkdf :1;       ///< Usage permission for HKDF
+        uint32_t uecsg :1;       ///< Usage permission for ECDSA signing
+        uint32_t uecdh :1;       ///< Usage permission for Elliptic Curve Diffie-Hellman
+        uint32_t uaes :1;        ///< Usage permission for AES
+        uint32_t uhmac :1;       ///< Usage permission for HMAC
+        uint32_t ukwk :1;        ///< Usage permission for key wrapping
+        uint32_t ukuok :1;       ///< Usage permission for key unwrapping, but not for key wrapping
+        uint32_t utlspms :1;     ///< Usage permission as a TLS premaster secret
+        uint32_t utlsms :1;      ///< Usage permission as a TLS master secret
+        uint32_t ukgsrc :1;      ///< Usage permission as input for ECC key generation
+        uint32_t uhwo :1;        ///< Usage permission in a hardware-out key slot
+        uint32_t wrpok :1;       ///< Usage permission to wrap
+        uint32_t duk :1;         ///< Device-unique key flag
+        uint32_t upprot_priv :1; ///< Access restriction to privileged mode
+        uint32_t upprot_sec :1;  ///< Access restriction to TrustZone secure mode
+    } bits;                      ///< Access #mcuxClEls_KeyProp_t bit-wise
+} mcuxClEls_KeyProp_t;
+
+
+#define utlpsms utlspms ///< Deprecated name for #mcuxClEls_KeyProp_t.utlspms
+
+/**
+ * @brief Function type for transfer of data to a memory-mapped register
+ *
+ * This function type is used as a callback for handling data transfer from memory to a memory-mapped register.
+ * Such a function shall read data from the @c uint8_t array source, and write data via a sequence of writes to @p destRegister.
+ * Further specification of this function's behavior can be found in the documentation of the function that accepts this function as a callback parameter.
+ * 
+ * @param [out] pDestRegister  Memory-mapped register that the output data shall be written to
+ * @param [in]  pSource        Array containing the input data
+ * @param [in]  sourceLength   Size of @p source in bytes
+ * @param [in, out] pCallerData   Custom pointer that is provided by the caller and forwarded to the callback function by the operation
+ * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information
+ */
+typedef mcuxClEls_Status_t (*mcuxClEls_TransferToRegisterFunction_t)(
+    uint32_t volatile * pDestRegister,
+    uint8_t const * pSource,
+    size_t sourceLength,
+    void * pCallerData);
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLELS_TYPES_H_ */
+
+/**
+ * @}
+ *
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_mapping.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_mapping.h
new file mode 100644
index 0000000000..069564d408
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_mapping.h
@@ -0,0 +1,549 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClEls_mapping.h
+ * @brief Header providing mapping for legacy function/definition names (with CSS)
+ */
+
+
+#ifndef MCUXCLELS_MAPPING_H_
+#define MCUXCLELS_MAPPING_H_
+
+/* Public definitions */
+/**
+ * MCUXCLCSS_CSS_((?:INTERRUPT_DISABLE|INTERRUPT_ENABLE|INTERRUPT_KEEP|INTERRUPT_SET|RESET_CLEAR|RESET_KEEP))(?!\w)
+ * -->
+ * MCUXCLELS_ELS_\1
+ *
+ * MCUXCLCSS_((?:API|AEAD_AAD_BLOCK_SIZE|AEAD_ACPMOD_AADPROC|AEAD_ACPMOD_FINAL|AEAD_ACPMOD_INIT|AEAD_ACPMOD_MSGPROC|AEAD_CONTEXT_SIZE|AEAD_DECRYPT|AEAD_ENCRYPT|AEAD_EXTERN_KEY|AEAD_INTERN_KEY|AEAD_IV_BLOCK_SIZE|AEAD_LASTINIT_FALSE|AEAD_LASTINIT_TRUE|AEAD_STATE_IN_DISABLE|AEAD_STATE_IN_ENABLE|AEAD_STATE_OUT_ENABLE|AEAD_TAG_SIZE|CIPHERPARAM_ALGORITHM_AES_CBC|CIPHERPARAM_ALGORITHM_AES_CTR|CIPHERPARAM_ALGORITHM_AES_ECB|CIPHER_BLOCK_SIZE_AES|CIPHER_DECRYPT|CIPHER_ENCRYPT|CIPHER_EXTERNAL_KEY|CIPHER_INTERNAL_KEY|CIPHER_KEY_SIZE_AES_128|CIPHER_KEY_SIZE_AES_192|CIPHER_KEY_SIZE_AES_256|CIPHER_STATE_IN_DISABLE|CIPHER_STATE_IN_ENABLE|CIPHER_STATE_OUT_DISABLE|CIPHER_STATE_OUT_ENABLE|CKDF_ALGO_SP800108|CKDF_ALGO_SP80056C_EXPAND|CKDF_ALGO_SP80056C_EXTRACT|CKDF_DERIVATIONDATA_SIZE|CKDF_RTF_DERIV|CKDF_SP80056C_DERIVATIONDATA_SIZE_16|CKDF_SP80056C_DERIVATIONDATA_SIZE_32|CKDF_SYSTEM_MEMORY_DERIV|CMAC_EXTERNAL_KEY_DISABLE|CMAC_EXTERNAL_KEY_ENABLE|CMAC_FINALIZE_DISABLE|CMAC_FINALIZE_ENABLE|CMAC_INITIALIZE_DISABLE|CMAC_INITIALIZE_ENABLE|CMAC_KEY_SIZE_128|CMAC_KEY_SIZE_256|CMAC_OUT_SIZE))(?!\w)
+ * MCUXCLCSS_((?:CMD_CRC_CMD_ID_AUTH_CIPHER|CMD_CRC_CMD_ID_CHAL_RESP_GEN|CMD_CRC_CMD_ID_CIPHER|CMD_CRC_CMD_ID_CKDF|CMD_CRC_CMD_ID_CMAC|CMD_CRC_CMD_ID_DRBG_TEST|CMD_CRC_CMD_ID_DTRNG_CFG_LOAD|CMD_CRC_CMD_ID_DTRNG_EVAL|CMD_CRC_CMD_ID_ECKXH|CMD_CRC_CMD_ID_ECSIGN|CMD_CRC_CMD_ID_ECVFY|CMD_CRC_CMD_ID_GDET_CFG_LOAD|CMD_CRC_CMD_ID_GDET_TRIM|CMD_CRC_CMD_ID_HASH|CMD_CRC_CMD_ID_HKDF|CMD_CRC_CMD_ID_HMAC|CMD_CRC_CMD_ID_KDELETE|CMD_CRC_CMD_ID_KEYGEN|CMD_CRC_CMD_ID_KEYIN|CMD_CRC_CMD_ID_KEYOUT|CMD_CRC_CMD_ID_KEYPROV|CMD_CRC_CMD_ID_RND_REQ|CMD_CRC_CMD_ID_TLS|CMD_CRC_DISABLE|CMD_CRC_ENABLE|CMD_CRC_INITIAL_VALUE|CMD_CRC_POLYNOMIAL|CMD_CRC_REFERENCE_INIT|CMD_CRC_REFERENCE_RESET|CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE|CMD_CRC_REFERENCE_UPDATE_AEAD_INIT|CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT|CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD|CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA|CMD_CRC_REFERENCE_UPDATE_CIPHER|CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108|CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND|CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT|CMD_CRC_REFERENCE_UPDATE_CMAC))(?!\w)
+ * MCUXCLCSS_((?:CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE|CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT|CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN|CMD_CRC_REFERENCE_UPDATE_ECCSIGN|CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY|CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT|CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG|CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM|CMD_CRC_REFERENCE_UPDATE_HASH|CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869|CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C|CMD_CRC_REFERENCE_UPDATE_HMAC|CMD_CRC_REFERENCE_UPDATE_KEYDELETE|CMD_CRC_REFERENCE_UPDATE_KEYEXPORT|CMD_CRC_REFERENCE_UPDATE_KEYIMPORT|CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK|CMD_CRC_REFERENCE_UPDATE_KEYPROVISION|CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM|CMD_CRC_REFERENCE_UPDATE_PRNG_INIT|CMD_CRC_REFERENCE_UPDATE_RESPGEN|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE|CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE))(?!\w)
+ * MCUXCLCSS_((?:CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD|CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY|CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY|CMD_CRC_RESET|CMD_CRC_VALUE_DISABLE|CMD_CRC_VALUE_ENABLE|CMD_CRC_VALUE_RESET|DMA_READBACK_PROTECTION_TOKEN|ECC_EXTKEY_EXTERNAL|ECC_EXTKEY_INTERNAL|ECC_GEN_PUBLIC_KEY|ECC_HASHED|ECC_INCLUDE_RANDOM_DATA|ECC_NOT_HASHED|ECC_NO_RANDOM_DATA|ECC_NO_RTF|ECC_OUTPUTKEY_DETERMINISTIC|ECC_OUTPUTKEY_KEYEXCHANGE|ECC_OUTPUTKEY_RANDOM|ECC_OUTPUTKEY_SIGN|ECC_PUBLICKEY_SIGN_DISABLE|ECC_PUBLICKEY_SIGN_ENABLE|ECC_PUBLICKEY_SIZE|ECC_REVERSEFETCH_DISABLE|ECC_REVERSEFETCH_ENABLE|ECC_RTF|ECC_SIGNATURE_R_SIZE|ECC_SIGNATURE_SIZE|ECC_SKIP_PUBLIC_KEY|ECC_VALUE_HASHED|ECC_VALUE_NOT_HASHED|ECC_VALUE_NO_RTF|ECC_VALUE_RTF|ERROR_FLAGS_CLEAR|ERROR_FLAGS_KEEP|GLITCHDETECTOR_CFG_SIZE|GLITCHDETECTOR_TRIM_SIZE|GLITCH_DETECTOR_INTERRUPT_DISABLE|GLITCH_DETECTOR_INTERRUPT_ENABLE|GLITCH_DETECTOR_NEG_KEEP))(?!\w)
+ * MCUXCLCSS_((?:GLITCH_DETECTOR_NEG_SET|GLITCH_DETECTOR_POS_KEEP|GLITCH_DETECTOR_POS_SET|GLITCH_DETECTOR_RESET_CLEAR|GLITCH_DETECTOR_RESET_KEEP|HASH_BLOCK_SIZE_SHA_224|HASH_BLOCK_SIZE_SHA_256|HASH_BLOCK_SIZE_SHA_384|HASH_BLOCK_SIZE_SHA_512|HASH_INIT_DISABLE|HASH_INIT_ENABLE|HASH_LOAD_DISABLE|HASH_LOAD_ENABLE|HASH_MODE_SHA_224|HASH_MODE_SHA_256|HASH_MODE_SHA_384|HASH_MODE_SHA_512|HASH_OUTPUT_DISABLE|HASH_OUTPUT_ENABLE|HASH_OUTPUT_SIZE_SHA_224|HASH_OUTPUT_SIZE_SHA_256|HASH_OUTPUT_SIZE_SHA_384|HASH_OUTPUT_SIZE_SHA_512|HASH_RTF_OUTPUT_DISABLE|HASH_RTF_OUTPUT_ENABLE|HASH_RTF_OUTPUT_SIZE|HASH_RTF_UPDATE_DISABLE|HASH_RTF_UPDATE_ENABLE|HASH_STATE_SIZE_SHA_224|HASH_STATE_SIZE_SHA_256|HASH_STATE_SIZE_SHA_384|HASH_STATE_SIZE_SHA_512|HASH_VALUE_MODE_SHA_224|HASH_VALUE_MODE_SHA_256|HASH_VALUE_MODE_SHA_384|HASH_VALUE_MODE_SHA_512|HKDF_ALGO_RFC5869|HKDF_ALGO_SP80056C|HKDF_RFC5869_DERIVATIONDATA_SIZE|HKDF_SP80056C_TARGETKEY_SIZE|HKDF_VALUE_MEMORY_DERIV|HKDF_VALUE_RTF_DERIV|HMAC_EXTERNAL_KEY_DISABLE|HMAC_EXTERNAL_KEY_ENABLE|HMAC_OUTPUT_SIZE|HMAC_PADDED_KEY_SIZE|HW_VERSION))(?!\w)
+ * MCUXCLCSS_((?:KEYGEN_VALUE_DETERMINISTIC|KEYGEN_VALUE_GEN_PUB_KEY|KEYGEN_VALUE_NO_PUB_KEY|KEYGEN_VALUE_NO_RANDOM_DATA|KEYGEN_VALUE_RANDOM|KEYGEN_VALUE_SIGN_PUBLICKEY|KEYGEN_VALUE_TYPE_KEYEXCHANGE|KEYGEN_VALUE_TYPE_SIGN|KEYGEN_VALUE_USE_RANDOM_DATA|KEYIMPORT_KFMT_PBK|KEYIMPORT_KFMT_PUF|KEYIMPORT_KFMT_RFC3394|KEYIMPORT_KFMT_UDF|KEYIMPORT_REVERSEFETCH_DISABLE|KEYIMPORT_REVERSEFETCH_ENABLE|KEYIMPORT_VALUE_KFMT_PBK|KEYIMPORT_VALUE_KFMT_PUF|KEYIMPORT_VALUE_KFMT_RFC3394|KEYIMPORT_VALUE_KFMT_UDF|KEYPROPERTY_ACTIVE_FALSE|KEYPROPERTY_ACTIVE_TRUE|KEYPROPERTY_AES_FALSE|KEYPROPERTY_AES_TRUE|KEYPROPERTY_BASE_SLOT|KEYPROPERTY_CKDF_FALSE|KEYPROPERTY_CKDF_TRUE|KEYPROPERTY_CMAC_FALSE|KEYPROPERTY_CMAC_TRUE|KEYPROPERTY_DEVICE_UNIQUE_FALSE|KEYPROPERTY_DEVICE_UNIQUE_TRUE|KEYPROPERTY_ECC_DH_PRIVATE_FALSE|KEYPROPERTY_ECC_DH_PRIVATE_TRUE|KEYPROPERTY_ECC_FALSE|KEYPROPERTY_ECC_TRUE|KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE|KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE|KEYPROPERTY_HKDF_FALSE|KEYPROPERTY_HKDF_TRUE|KEYPROPERTY_HMAC_FALSE|KEYPROPERTY_HMAC_TRUE|KEYPROPERTY_HW_OUT_FALSE|KEYPROPERTY_HW_OUT_SLOT_FALSE))(?!\w)
+ * MCUXCLCSS_((?:KEYPROPERTY_HW_OUT_SLOT_TRUE|KEYPROPERTY_HW_OUT_TRUE|KEYPROPERTY_INPUT_FOR_ECC_FALSE|KEYPROPERTY_INPUT_FOR_ECC_TRUE|KEYPROPERTY_KEY_SIZE_128|KEYPROPERTY_KEY_SIZE_256|KEYPROPERTY_KEY_SIZE_512|KEYPROPERTY_KSK_FALSE|KEYPROPERTY_KSK_TRUE|KEYPROPERTY_KUOK_FALSE|KEYPROPERTY_KUOK_TRUE|KEYPROPERTY_KWK_FALSE|KEYPROPERTY_KWK_TRUE|KEYPROPERTY_PRIVILEGED_FALSE|KEYPROPERTY_PRIVILEGED_TRUE|KEYPROPERTY_PUK_FALSE|KEYPROPERTY_PUK_TRUE|KEYPROPERTY_RETENTION_SLOT_FALSE|KEYPROPERTY_RETENTION_SLOT_TRUE|KEYPROPERTY_RTF_FALSE|KEYPROPERTY_RTF_TRUE|KEYPROPERTY_SECOND_SLOT|KEYPROPERTY_SECURE_FALSE|KEYPROPERTY_SECURE_TRUE|KEYPROPERTY_TECDH_FALSE|KEYPROPERTY_TECDH_TRUE|KEYPROPERTY_TLS_MASTER_SECRET_FALSE|KEYPROPERTY_TLS_MASTER_SECRET_TRUE|KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE|KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE|KEYPROPERTY_VALUE_ACTIVE|KEYPROPERTY_VALUE_AES|KEYPROPERTY_VALUE_BASE_SLOT|KEYPROPERTY_VALUE_CKDF|KEYPROPERTY_VALUE_CMAC|KEYPROPERTY_VALUE_DUK|KEYPROPERTY_VALUE_ECDH|KEYPROPERTY_VALUE_ECSGN|KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT|KEYPROPERTY_VALUE_HKDF|KEYPROPERTY_VALUE_HMAC))(?!\w)
+ * MCUXCLCSS_((?:KEYPROPERTY_VALUE_HW_OUT|KEYPROPERTY_VALUE_HW_OUT_SLOT|KEYPROPERTY_VALUE_KEY_SIZE_128|KEYPROPERTY_VALUE_KEY_SIZE_256|KEYPROPERTY_VALUE_KEY_SIZE_512|KEYPROPERTY_VALUE_KGSRC|KEYPROPERTY_VALUE_KSK|KEYPROPERTY_VALUE_KUOK|KEYPROPERTY_VALUE_KWK|KEYPROPERTY_VALUE_NOTPRIVILEGED|KEYPROPERTY_VALUE_NOTSECURE|KEYPROPERTY_VALUE_PRIVILEGED|KEYPROPERTY_VALUE_PUK|KEYPROPERTY_VALUE_RETENTION_SLOT|KEYPROPERTY_VALUE_RTF|KEYPROPERTY_VALUE_SECURE|KEYPROPERTY_VALUE_TECDH|KEYPROPERTY_VALUE_TLS_MASTER_SECRET|KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET|KEYPROPERTY_VALUE_WRPOK|KEYPROPERTY_WRAP_FALSE|KEYPROPERTY_WRAP_TRUE|KEYPROV_DUK_UPDATE_DISABLE|KEYPROV_DUK_UPDATE_ENABLE|KEYPROV_KEYSHARE_TABLE_SIZE|KEYPROV_KEY_PART_1_SIZE|KEYPROV_NOIC_DISABLE|KEYPROV_NOIC_ENABLE|KEYPROV_TESTERSHARE_SIZE|KEYPROV_VALUE_NOIC|KEY_SLOTS|MASTER_UNLOCK_ANY|RESET_CANCEL|RESET_DO_NOT_CANCEL|RESP_GEN_AVAILABLE_SLOT_0|RESP_GEN_AVAILABLE_SLOT_1|RESP_GEN_AVAILABLE_SLOT_2|RESP_GEN_SLOTS|RFC3394_CONTAINER_SIZE_128|RFC3394_CONTAINER_SIZE_256|RFC3394_CONTAINER_SIZE_P256|RFC3394_OVERHEAD|RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE))(?!\w)
+ * MCUXCLCSS_((?:RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE|RNG_DRBG_TEST_MODE_AES_CTR|RNG_DRBG_TEST_MODE_AES_ECB|RNG_DRBG_TEST_MODE_EXTRACT|RNG_DRBG_TEST_MODE_INSTANTIATE|RNG_DTRNG_CONFIG_SIZE|RNG_DTRNG_EVAL_CONFIG_SIZE|RNG_DTRNG_EVAL_RESULT_SIZE|RNG_RAW_ENTROPY_SIZE|RNG_RND_REQ_PRND_INIT|RNG_RND_REQ_RND_RAW|STATUS_DRBGENTLVL_HIGH|STATUS_DRBGENTLVL_LOW|STATUS_DRBGENTLVL_NONE|STATUS_ECDSAVFY_ERROR|STATUS_ECDSAVFY_FAIL|STATUS_ECDSAVFY_NORUN|STATUS_ECDSAVFY_OK|STATUS_HW_ALGORITHM|STATUS_HW_BUS|STATUS_HW_DTRNG|STATUS_HW_FAULT|STATUS_HW_INTEGRITY|STATUS_HW_OPERATIONAL|STATUS_HW_PRNG|STATUS_IS_HW_ERROR|STATUS_IS_SW_ERROR|STATUS_OK|STATUS_OK_WAIT|STATUS_PPROT_PRIVILEGED_NONSECURE|STATUS_PPROT_PRIVILEGED_SECURE|STATUS_PPROT_UNPRIVILEGED_NONSECURE|STATUS_PPROT_UNPRIVILEGED_SECURE|STATUS_SW_CANNOT_INTERRUPT|STATUS_SW_COMPARISON_FAILED|STATUS_SW_COUNTER_EXPIRED|STATUS_SW_FAULT|STATUS_SW_INVALID_PARAM|STATUS_SW_INVALID_STATE|STATUS_SW_LOCKING_FAILED|STATUS_SW_STATUS_LOCKED|TLS_DERIVATIONDATA_SIZE|TLS_FINALIZE|TLS_INIT|TLS_RANDOM_SIZE))(?!\w)
+ * -->
+ * MCUXCLELS_\1
+ */
+#define MCUXCLCSS_API  MCUXCLELS_API
+#define MCUXCLCSS_AEAD_AAD_BLOCK_SIZE  MCUXCLELS_AEAD_AAD_BLOCK_SIZE
+#define MCUXCLCSS_AEAD_ACPMOD_AADPROC  MCUXCLELS_AEAD_ACPMOD_AADPROC
+#define MCUXCLCSS_AEAD_ACPMOD_FINAL  MCUXCLELS_AEAD_ACPMOD_FINAL
+#define MCUXCLCSS_AEAD_ACPMOD_INIT  MCUXCLELS_AEAD_ACPMOD_INIT
+#define MCUXCLCSS_AEAD_ACPMOD_MSGPROC  MCUXCLELS_AEAD_ACPMOD_MSGPROC
+#define MCUXCLCSS_AEAD_CONTEXT_SIZE  MCUXCLELS_AEAD_CONTEXT_SIZE
+#define MCUXCLCSS_AEAD_DECRYPT  MCUXCLELS_AEAD_DECRYPT
+#define MCUXCLCSS_AEAD_ENCRYPT  MCUXCLELS_AEAD_ENCRYPT
+#define MCUXCLCSS_AEAD_EXTERN_KEY  MCUXCLELS_AEAD_EXTERN_KEY
+#define MCUXCLCSS_AEAD_INTERN_KEY  MCUXCLELS_AEAD_INTERN_KEY
+#define MCUXCLCSS_AEAD_IV_BLOCK_SIZE  MCUXCLELS_AEAD_IV_BLOCK_SIZE
+#define MCUXCLCSS_AEAD_LASTINIT_FALSE  MCUXCLELS_AEAD_LASTINIT_FALSE
+#define MCUXCLCSS_AEAD_LASTINIT_TRUE  MCUXCLELS_AEAD_LASTINIT_TRUE
+#define MCUXCLCSS_AEAD_STATE_IN_DISABLE  MCUXCLELS_AEAD_STATE_IN_DISABLE
+#define MCUXCLCSS_AEAD_STATE_IN_ENABLE  MCUXCLELS_AEAD_STATE_IN_ENABLE
+#define MCUXCLCSS_AEAD_STATE_OUT_ENABLE  MCUXCLELS_AEAD_STATE_OUT_ENABLE
+#define MCUXCLCSS_AEAD_TAG_SIZE  MCUXCLELS_AEAD_TAG_SIZE
+#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CBC  MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC
+#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CTR  MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR
+#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB  MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
+#define MCUXCLCSS_CIPHER_BLOCK_SIZE_AES  MCUXCLELS_CIPHER_BLOCK_SIZE_AES
+#define MCUXCLCSS_CIPHER_DECRYPT  MCUXCLELS_CIPHER_DECRYPT
+#define MCUXCLCSS_CIPHER_ENCRYPT  MCUXCLELS_CIPHER_ENCRYPT
+#define MCUXCLCSS_CIPHER_EXTERNAL_KEY  MCUXCLELS_CIPHER_EXTERNAL_KEY
+#define MCUXCLCSS_CIPHER_INTERNAL_KEY  MCUXCLELS_CIPHER_INTERNAL_KEY
+#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_128  MCUXCLELS_CIPHER_KEY_SIZE_AES_128
+#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_192  MCUXCLELS_CIPHER_KEY_SIZE_AES_192
+#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_256  MCUXCLELS_CIPHER_KEY_SIZE_AES_256
+#define MCUXCLCSS_CIPHER_STATE_IN_DISABLE  MCUXCLELS_CIPHER_STATE_IN_DISABLE
+#define MCUXCLCSS_CIPHER_STATE_IN_ENABLE  MCUXCLELS_CIPHER_STATE_IN_ENABLE
+#define MCUXCLCSS_CIPHER_STATE_OUT_DISABLE  MCUXCLELS_CIPHER_STATE_OUT_DISABLE
+#define MCUXCLCSS_CIPHER_STATE_OUT_ENABLE  MCUXCLELS_CIPHER_STATE_OUT_ENABLE
+#define MCUXCLCSS_CKDF_ALGO_SP800108  MCUXCLELS_CKDF_ALGO_SP800108
+#define MCUXCLCSS_CKDF_ALGO_SP80056C_EXPAND  MCUXCLELS_CKDF_ALGO_SP80056C_EXPAND
+#define MCUXCLCSS_CKDF_ALGO_SP80056C_EXTRACT  MCUXCLELS_CKDF_ALGO_SP80056C_EXTRACT
+#define MCUXCLCSS_CKDF_DERIVATIONDATA_SIZE  MCUXCLELS_CKDF_DERIVATIONDATA_SIZE
+#define MCUXCLCSS_HKDF_RTF_DERIV  MCUXCLELS_HKDF_RTF_DERIV
+#define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16  MCUXCLELS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16
+#define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32  MCUXCLELS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32
+#define MCUXCLCSS_HKDF_SYSTEM_MEMORY_DERIV  MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV
+#define MCUXCLCSS_CMAC_EXTERNAL_KEY_DISABLE  MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE
+#define MCUXCLCSS_CMAC_EXTERNAL_KEY_ENABLE  MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE
+#define MCUXCLCSS_CMAC_FINALIZE_DISABLE  MCUXCLELS_CMAC_FINALIZE_DISABLE
+#define MCUXCLCSS_CMAC_FINALIZE_ENABLE  MCUXCLELS_CMAC_FINALIZE_ENABLE
+#define MCUXCLCSS_CMAC_INITIALIZE_DISABLE  MCUXCLELS_CMAC_INITIALIZE_DISABLE
+#define MCUXCLCSS_CMAC_INITIALIZE_ENABLE  MCUXCLELS_CMAC_INITIALIZE_ENABLE
+#define MCUXCLCSS_CMAC_KEY_SIZE_128  MCUXCLELS_CMAC_KEY_SIZE_128
+#define MCUXCLCSS_CMAC_KEY_SIZE_256  MCUXCLELS_CMAC_KEY_SIZE_256
+#define MCUXCLCSS_CMAC_OUT_SIZE  MCUXCLELS_CMAC_OUT_SIZE
+#define MCUXCLCSS_CMD_CRC_CMD_ID_AUTH_CIPHER  MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CHAL_RESP_GEN  MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CIPHER  MCUXCLELS_CMD_CRC_CMD_ID_CIPHER
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CKDF  MCUXCLELS_CMD_CRC_CMD_ID_CKDF
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CMAC  MCUXCLELS_CMD_CRC_CMD_ID_CMAC
+#define MCUXCLCSS_CMD_CRC_CMD_ID_DRBG_TEST  MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST
+#define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD  MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD
+#define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_EVAL  MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL
+#define MCUXCLCSS_CMD_CRC_CMD_ID_ECKXH  MCUXCLELS_CMD_CRC_CMD_ID_ECKXH
+#define MCUXCLCSS_CMD_CRC_CMD_ID_ECSIGN  MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN
+#define MCUXCLCSS_CMD_CRC_CMD_ID_ECVFY  MCUXCLELS_CMD_CRC_CMD_ID_ECVFY
+#define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_CFG_LOAD  MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD
+#define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_TRIM  MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM
+#define MCUXCLCSS_CMD_CRC_CMD_ID_HASH  MCUXCLELS_CMD_CRC_CMD_ID_HASH
+#define MCUXCLCSS_CMD_CRC_CMD_ID_HKDF  MCUXCLELS_CMD_CRC_CMD_ID_HKDF
+#define MCUXCLCSS_CMD_CRC_CMD_ID_HMAC  MCUXCLELS_CMD_CRC_CMD_ID_HMAC
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KDELETE  MCUXCLELS_CMD_CRC_CMD_ID_KDELETE
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYGEN  MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYIN  MCUXCLELS_CMD_CRC_CMD_ID_KEYIN
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYOUT  MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYPROV  MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV
+#define MCUXCLCSS_CMD_CRC_CMD_ID_RND_REQ  MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ
+#define MCUXCLCSS_CMD_CRC_CMD_ID_TLS  MCUXCLELS_CMD_CRC_CMD_ID_TLS
+#define MCUXCLCSS_CMD_CRC_DISABLE  MCUXCLELS_CMD_CRC_DISABLE
+#define MCUXCLCSS_CMD_CRC_ENABLE  MCUXCLELS_CMD_CRC_ENABLE
+#define MCUXCLCSS_CMD_CRC_INITIAL_VALUE  MCUXCLELS_CMD_CRC_INITIAL_VALUE
+#define MCUXCLCSS_CMD_CRC_POLYNOMIAL  MCUXCLELS_CMD_CRC_POLYNOMIAL
+#define MCUXCLCSS_CMD_CRC_REFERENCE_INIT  MCUXCLELS_CMD_CRC_REFERENCE_INIT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_RESET  MCUXCLELS_CMD_CRC_REFERENCE_RESET
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CIPHER  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CMAC  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HASH  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HMAC  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RESPGEN  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RESPGEN
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY  MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY
+#define MCUXCLCSS_CMD_CRC_RESET  MCUXCLELS_CMD_CRC_RESET
+#define MCUXCLCSS_CMD_CRC_VALUE_DISABLE  MCUXCLELS_CMD_CRC_VALUE_DISABLE
+#define MCUXCLCSS_CMD_CRC_VALUE_ENABLE  MCUXCLELS_CMD_CRC_VALUE_ENABLE
+#define MCUXCLCSS_CMD_CRC_VALUE_RESET  MCUXCLELS_CMD_CRC_VALUE_RESET
+#define MCUXCLCSS_CSS_INTERRUPT_DISABLE  MCUXCLELS_ELS_INTERRUPT_DISABLE
+#define MCUXCLCSS_CSS_INTERRUPT_ENABLE  MCUXCLELS_ELS_INTERRUPT_ENABLE
+#define MCUXCLCSS_CSS_INTERRUPT_KEEP  MCUXCLELS_ELS_INTERRUPT_KEEP
+#define MCUXCLCSS_CSS_INTERRUPT_SET  MCUXCLELS_ELS_INTERRUPT_SET
+#define MCUXCLCSS_CSS_RESET_CLEAR  MCUXCLELS_ELS_RESET_CLEAR
+#define MCUXCLCSS_CSS_RESET_KEEP  MCUXCLELS_ELS_RESET_KEEP
+#define MCUXCLCSS_DMA_READBACK_PROTECTION_TOKEN  MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN
+#define MCUXCLCSS_ECC_EXTKEY_EXTERNAL  MCUXCLELS_ECC_EXTKEY_EXTERNAL
+#define MCUXCLCSS_ECC_EXTKEY_INTERNAL  MCUXCLELS_ECC_EXTKEY_INTERNAL
+#define MCUXCLCSS_ECC_GEN_PUBLIC_KEY  MCUXCLELS_ECC_GEN_PUBLIC_KEY
+#define MCUXCLCSS_ECC_HASHED  MCUXCLELS_ECC_HASHED
+#define MCUXCLCSS_ECC_INCLUDE_RANDOM_DATA  MCUXCLELS_ECC_INCLUDE_RANDOM_DATA
+#define MCUXCLCSS_ECC_NOT_HASHED  MCUXCLELS_ECC_NOT_HASHED
+#define MCUXCLCSS_ECC_NO_RANDOM_DATA  MCUXCLELS_ECC_NO_RANDOM_DATA
+#define MCUXCLCSS_ECC_NO_RTF  MCUXCLELS_ECC_NO_RTF
+#define MCUXCLCSS_ECC_OUTPUTKEY_DETERMINISTIC  MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC
+#define MCUXCLCSS_ECC_OUTPUTKEY_KEYEXCHANGE  MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE
+#define MCUXCLCSS_ECC_OUTPUTKEY_RANDOM  MCUXCLELS_ECC_OUTPUTKEY_RANDOM
+#define MCUXCLCSS_ECC_OUTPUTKEY_SIGN  MCUXCLELS_ECC_OUTPUTKEY_SIGN
+#define MCUXCLCSS_ECC_PUBLICKEY_SIGN_DISABLE  MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE
+#define MCUXCLCSS_ECC_PUBLICKEY_SIGN_ENABLE  MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE
+#define MCUXCLCSS_ECC_PUBLICKEY_SIZE  MCUXCLELS_ECC_PUBLICKEY_SIZE
+#define MCUXCLCSS_ECC_REVERSEFETCH_DISABLE  MCUXCLELS_ECC_REVERSEFETCH_DISABLE
+#define MCUXCLCSS_ECC_REVERSEFETCH_ENABLE  MCUXCLELS_ECC_REVERSEFETCH_ENABLE
+#define MCUXCLCSS_ECC_RTF  MCUXCLELS_ECC_RTF
+#define MCUXCLCSS_ECC_SIGNATURE_R_SIZE  MCUXCLELS_ECC_SIGNATURE_R_SIZE
+#define MCUXCLCSS_ECC_SIGNATURE_SIZE  MCUXCLELS_ECC_SIGNATURE_SIZE
+#define MCUXCLCSS_ECC_SKIP_PUBLIC_KEY  MCUXCLELS_ECC_SKIP_PUBLIC_KEY
+#define MCUXCLCSS_ECC_VALUE_HASHED  MCUXCLELS_ECC_VALUE_HASHED
+#define MCUXCLCSS_ECC_VALUE_NOT_HASHED  MCUXCLELS_ECC_VALUE_NOT_HASHED
+#define MCUXCLCSS_ECC_VALUE_NO_RTF  MCUXCLELS_ECC_VALUE_NO_RTF
+#define MCUXCLCSS_ECC_VALUE_RTF  MCUXCLELS_ECC_VALUE_RTF
+#define MCUXCLCSS_ERROR_FLAGS_CLEAR  MCUXCLELS_ERROR_FLAGS_CLEAR
+#define MCUXCLCSS_ERROR_FLAGS_KEEP  MCUXCLELS_ERROR_FLAGS_KEEP
+#define MCUXCLCSS_GLITCHDETECTOR_CFG_SIZE  MCUXCLELS_GLITCHDETECTOR_CFG_SIZE
+#define MCUXCLCSS_GLITCHDETECTOR_TRIM_SIZE  MCUXCLELS_GLITCHDETECTOR_TRIM_SIZE
+#define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_DISABLE  MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_DISABLE
+#define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_ENABLE  MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_ENABLE
+#define MCUXCLCSS_GLITCH_DETECTOR_NEG_KEEP  MCUXCLELS_GLITCH_DETECTOR_NEG_KEEP
+#define MCUXCLCSS_GLITCH_DETECTOR_NEG_SET  MCUXCLELS_GLITCH_DETECTOR_NEG_SET
+#define MCUXCLCSS_GLITCH_DETECTOR_POS_KEEP  MCUXCLELS_GLITCH_DETECTOR_POS_KEEP
+#define MCUXCLCSS_GLITCH_DETECTOR_POS_SET  MCUXCLELS_GLITCH_DETECTOR_POS_SET
+#define MCUXCLCSS_GLITCH_DETECTOR_RESET_CLEAR  MCUXCLELS_GLITCH_DETECTOR_RESET_CLEAR
+#define MCUXCLCSS_GLITCH_DETECTOR_RESET_KEEP  MCUXCLELS_GLITCH_DETECTOR_RESET_KEEP
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_224  MCUXCLELS_HASH_BLOCK_SIZE_SHA_224
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_256  MCUXCLELS_HASH_BLOCK_SIZE_SHA_256
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_384  MCUXCLELS_HASH_BLOCK_SIZE_SHA_384
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_512  MCUXCLELS_HASH_BLOCK_SIZE_SHA_512
+#define MCUXCLCSS_HASH_INIT_DISABLE  MCUXCLELS_HASH_INIT_DISABLE
+#define MCUXCLCSS_HASH_INIT_ENABLE  MCUXCLELS_HASH_INIT_ENABLE
+#define MCUXCLCSS_HASH_LOAD_DISABLE  MCUXCLELS_HASH_LOAD_DISABLE
+#define MCUXCLCSS_HASH_LOAD_ENABLE  MCUXCLELS_HASH_LOAD_ENABLE
+#define MCUXCLCSS_HASH_MODE_SHA_224  MCUXCLELS_HASH_MODE_SHA_224
+#define MCUXCLCSS_HASH_MODE_SHA_256  MCUXCLELS_HASH_MODE_SHA_256
+#define MCUXCLCSS_HASH_MODE_SHA_384  MCUXCLELS_HASH_MODE_SHA_384
+#define MCUXCLCSS_HASH_MODE_SHA_512  MCUXCLELS_HASH_MODE_SHA_512
+#define MCUXCLCSS_HASH_OUTPUT_DISABLE  MCUXCLELS_HASH_OUTPUT_DISABLE
+#define MCUXCLCSS_HASH_OUTPUT_ENABLE  MCUXCLELS_HASH_OUTPUT_ENABLE
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_224  MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_256  MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_384  MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_512  MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512
+#define MCUXCLCSS_HASH_RTF_OUTPUT_DISABLE  MCUXCLELS_HASH_RTF_OUTPUT_DISABLE
+#define MCUXCLCSS_HASH_RTF_OUTPUT_ENABLE  MCUXCLELS_HASH_RTF_OUTPUT_ENABLE
+#define MCUXCLCSS_HASH_RTF_OUTPUT_SIZE  MCUXCLELS_HASH_RTF_OUTPUT_SIZE
+#define MCUXCLCSS_HASH_RTF_UPDATE_DISABLE  MCUXCLELS_HASH_RTF_UPDATE_DISABLE
+#define MCUXCLCSS_HASH_RTF_UPDATE_ENABLE  MCUXCLELS_HASH_RTF_UPDATE_ENABLE
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_224  MCUXCLELS_HASH_STATE_SIZE_SHA_224
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_256  MCUXCLELS_HASH_STATE_SIZE_SHA_256
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_384  MCUXCLELS_HASH_STATE_SIZE_SHA_384
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_512  MCUXCLELS_HASH_STATE_SIZE_SHA_512
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_224  MCUXCLELS_HASH_VALUE_MODE_SHA_224
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_256  MCUXCLELS_HASH_VALUE_MODE_SHA_256
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_384  MCUXCLELS_HASH_VALUE_MODE_SHA_384
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_512  MCUXCLELS_HASH_VALUE_MODE_SHA_512
+#define MCUXCLCSS_HKDF_ALGO_RFC5869  MCUXCLELS_HKDF_ALGO_RFC5869
+#define MCUXCLCSS_HKDF_ALGO_SP80056C  MCUXCLELS_HKDF_ALGO_SP80056C
+#define MCUXCLCSS_HKDF_RFC5869_DERIVATIONDATA_SIZE  MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE
+#define MCUXCLCSS_HKDF_SP80056C_TARGETKEY_SIZE  MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE
+#define MCUXCLCSS_HKDF_VALUE_MEMORY_DERIV  MCUXCLELS_HKDF_VALUE_MEMORY_DERIV
+#define MCUXCLCSS_HKDF_VALUE_RTF_DERIV  MCUXCLELS_HKDF_VALUE_RTF_DERIV
+#define MCUXCLCSS_HMAC_EXTERNAL_KEY_DISABLE  MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE
+#define MCUXCLCSS_HMAC_EXTERNAL_KEY_ENABLE  MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE
+#define MCUXCLCSS_HMAC_OUTPUT_SIZE  MCUXCLELS_HMAC_OUTPUT_SIZE
+#define MCUXCLCSS_HMAC_PADDED_KEY_SIZE  MCUXCLELS_HMAC_PADDED_KEY_SIZE
+#define MCUXCLCSS_HW_VERSION  MCUXCLELS_HW_VERSION
+#define MCUXCLCSS_KEYGEN_VALUE_DETERMINISTIC  MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC
+#define MCUXCLCSS_KEYGEN_VALUE_GEN_PUB_KEY  MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY
+#define MCUXCLCSS_KEYGEN_VALUE_NO_PUB_KEY  MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY
+#define MCUXCLCSS_KEYGEN_VALUE_NO_RANDOM_DATA  MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA
+#define MCUXCLCSS_KEYGEN_VALUE_RANDOM  MCUXCLELS_KEYGEN_VALUE_RANDOM
+#define MCUXCLCSS_KEYGEN_VALUE_SIGN_PUBLICKEY  MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY
+#define MCUXCLCSS_KEYGEN_VALUE_TYPE_KEYEXCHANGE  MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE
+#define MCUXCLCSS_KEYGEN_VALUE_TYPE_SIGN  MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN
+#define MCUXCLCSS_KEYGEN_VALUE_USE_RANDOM_DATA  MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA
+#define MCUXCLCSS_KEYIMPORT_KFMT_PBK  MCUXCLELS_KEYIMPORT_KFMT_PBK
+#define MCUXCLCSS_KEYIMPORT_KFMT_PUF  MCUXCLELS_KEYIMPORT_KFMT_PUF
+#define MCUXCLCSS_KEYIMPORT_KFMT_RFC3394  MCUXCLELS_KEYIMPORT_KFMT_RFC3394
+#define MCUXCLCSS_KEYIMPORT_KFMT_UDF  MCUXCLELS_KEYIMPORT_KFMT_UDF
+#define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_DISABLE  MCUXCLELS_KEYIMPORT_REVERSEFETCH_DISABLE
+#define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_ENABLE  MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PBK  MCUXCLELS_KEYIMPORT_VALUE_KFMT_PBK
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PUF  MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_RFC3394  MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_UDF  MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF
+#define MCUXCLCSS_KEYPROPERTY_ACTIVE_FALSE  MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE
+#define MCUXCLCSS_KEYPROPERTY_ACTIVE_TRUE  MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE
+#define MCUXCLCSS_KEYPROPERTY_AES_FALSE  MCUXCLELS_KEYPROPERTY_AES_FALSE
+#define MCUXCLCSS_KEYPROPERTY_AES_TRUE  MCUXCLELS_KEYPROPERTY_AES_TRUE
+#define MCUXCLCSS_KEYPROPERTY_BASE_SLOT  MCUXCLELS_KEYPROPERTY_BASE_SLOT
+#define MCUXCLCSS_KEYPROPERTY_CKDF_FALSE  MCUXCLELS_KEYPROPERTY_CKDF_FALSE
+#define MCUXCLCSS_KEYPROPERTY_CKDF_TRUE  MCUXCLELS_KEYPROPERTY_CKDF_TRUE
+#define MCUXCLCSS_KEYPROPERTY_CMAC_FALSE  MCUXCLELS_KEYPROPERTY_CMAC_FALSE
+#define MCUXCLCSS_KEYPROPERTY_CMAC_TRUE  MCUXCLELS_KEYPROPERTY_CMAC_TRUE
+#define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_FALSE  MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE
+#define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_TRUE  MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE
+#define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE  MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE
+#define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE  MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE
+#define MCUXCLCSS_KEYPROPERTY_ECC_FALSE  MCUXCLELS_KEYPROPERTY_ECC_FALSE
+#define MCUXCLCSS_KEYPROPERTY_ECC_TRUE  MCUXCLELS_KEYPROPERTY_ECC_TRUE
+#define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE  MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE
+#define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE  MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE
+#define MCUXCLCSS_KEYPROPERTY_HKDF_FALSE  MCUXCLELS_KEYPROPERTY_HKDF_FALSE
+#define MCUXCLCSS_KEYPROPERTY_HKDF_TRUE  MCUXCLELS_KEYPROPERTY_HKDF_TRUE
+#define MCUXCLCSS_KEYPROPERTY_HMAC_FALSE  MCUXCLELS_KEYPROPERTY_HMAC_FALSE
+#define MCUXCLCSS_KEYPROPERTY_HMAC_TRUE  MCUXCLELS_KEYPROPERTY_HMAC_TRUE
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_FALSE  MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_FALSE  MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_TRUE  MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_TRUE  MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE
+#define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_FALSE  MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE
+#define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_TRUE  MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE
+#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_128  MCUXCLELS_KEYPROPERTY_KEY_SIZE_128
+#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_256  MCUXCLELS_KEYPROPERTY_KEY_SIZE_256
+#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_512  MCUXCLELS_KEYPROPERTY_KEY_SIZE_512
+#define MCUXCLCSS_KEYPROPERTY_KSK_FALSE  MCUXCLELS_KEYPROPERTY_KSK_FALSE
+#define MCUXCLCSS_KEYPROPERTY_KSK_TRUE  MCUXCLELS_KEYPROPERTY_KSK_TRUE
+#define MCUXCLCSS_KEYPROPERTY_KUOK_FALSE  MCUXCLELS_KEYPROPERTY_KUOK_FALSE
+#define MCUXCLCSS_KEYPROPERTY_KUOK_TRUE  MCUXCLELS_KEYPROPERTY_KUOK_TRUE
+#define MCUXCLCSS_KEYPROPERTY_KWK_FALSE  MCUXCLELS_KEYPROPERTY_KWK_FALSE
+#define MCUXCLCSS_KEYPROPERTY_KWK_TRUE  MCUXCLELS_KEYPROPERTY_KWK_TRUE
+#define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_FALSE  MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE
+#define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_TRUE  MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE
+#define MCUXCLCSS_KEYPROPERTY_PUK_FALSE  MCUXCLELS_KEYPROPERTY_PUK_FALSE
+#define MCUXCLCSS_KEYPROPERTY_PUK_TRUE  MCUXCLELS_KEYPROPERTY_PUK_TRUE
+#define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_FALSE  MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE
+#define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_TRUE  MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE
+#define MCUXCLCSS_KEYPROPERTY_RTF_FALSE  MCUXCLELS_KEYPROPERTY_RTF_FALSE
+#define MCUXCLCSS_KEYPROPERTY_RTF_TRUE  MCUXCLELS_KEYPROPERTY_RTF_TRUE
+#define MCUXCLCSS_KEYPROPERTY_SECOND_SLOT  MCUXCLELS_KEYPROPERTY_SECOND_SLOT
+#define MCUXCLCSS_KEYPROPERTY_SECURE_FALSE  MCUXCLELS_KEYPROPERTY_SECURE_FALSE
+#define MCUXCLCSS_KEYPROPERTY_SECURE_TRUE  MCUXCLELS_KEYPROPERTY_SECURE_TRUE
+#define MCUXCLCSS_KEYPROPERTY_TECDH_FALSE  MCUXCLELS_KEYPROPERTY_TECDH_FALSE
+#define MCUXCLCSS_KEYPROPERTY_TECDH_TRUE  MCUXCLELS_KEYPROPERTY_TECDH_TRUE
+#define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE  MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE
+#define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE  MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE
+#define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE  MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE
+#define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE  MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE
+#define MCUXCLCSS_KEYPROPERTY_VALUE_ACTIVE  MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE
+#define MCUXCLCSS_KEYPROPERTY_VALUE_AES  MCUXCLELS_KEYPROPERTY_VALUE_AES
+#define MCUXCLCSS_KEYPROPERTY_VALUE_BASE_SLOT  MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT
+#define MCUXCLCSS_KEYPROPERTY_VALUE_CKDF  MCUXCLELS_KEYPROPERTY_VALUE_CKDF
+#define MCUXCLCSS_KEYPROPERTY_VALUE_CMAC  MCUXCLELS_KEYPROPERTY_VALUE_CMAC
+#define MCUXCLCSS_KEYPROPERTY_VALUE_DUK  MCUXCLELS_KEYPROPERTY_VALUE_DUK
+#define MCUXCLCSS_KEYPROPERTY_VALUE_ECDH  MCUXCLELS_KEYPROPERTY_VALUE_ECDH
+#define MCUXCLCSS_KEYPROPERTY_VALUE_ECSGN  MCUXCLELS_KEYPROPERTY_VALUE_ECSGN
+#define MCUXCLCSS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT  MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HKDF  MCUXCLELS_KEYPROPERTY_VALUE_HKDF
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HMAC  MCUXCLELS_KEYPROPERTY_VALUE_HMAC
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT  MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT_SLOT  MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_128  MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_256  MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_512  MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_512
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KGSRC  MCUXCLELS_KEYPROPERTY_VALUE_KGSRC
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KSK  MCUXCLELS_KEYPROPERTY_VALUE_KSK
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KUOK  MCUXCLELS_KEYPROPERTY_VALUE_KUOK
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KWK  MCUXCLELS_KEYPROPERTY_VALUE_KWK
+#define MCUXCLCSS_KEYPROPERTY_VALUE_NOTPRIVILEGED  MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED
+#define MCUXCLCSS_KEYPROPERTY_VALUE_NOTSECURE  MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE
+#define MCUXCLCSS_KEYPROPERTY_VALUE_PRIVILEGED  MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED
+#define MCUXCLCSS_KEYPROPERTY_VALUE_PUK  MCUXCLELS_KEYPROPERTY_VALUE_PUK
+#define MCUXCLCSS_KEYPROPERTY_VALUE_RETENTION_SLOT  MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT
+#define MCUXCLCSS_KEYPROPERTY_VALUE_RTF  MCUXCLELS_KEYPROPERTY_VALUE_RTF
+#define MCUXCLCSS_KEYPROPERTY_VALUE_SECURE  MCUXCLELS_KEYPROPERTY_VALUE_SECURE
+#define MCUXCLCSS_KEYPROPERTY_VALUE_TECDH  MCUXCLELS_KEYPROPERTY_VALUE_TECDH
+#define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET  MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET
+#define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET  MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET
+#define MCUXCLCSS_KEYPROPERTY_VALUE_WRPOK  MCUXCLELS_KEYPROPERTY_VALUE_WRPOK
+#define MCUXCLCSS_KEYPROPERTY_WRAP_FALSE  MCUXCLELS_KEYPROPERTY_WRAP_FALSE
+#define MCUXCLCSS_KEYPROPERTY_WRAP_TRUE  MCUXCLELS_KEYPROPERTY_WRAP_TRUE
+#define MCUXCLCSS_KEYPROV_DUK_UPDATE_DISABLE  MCUXCLELS_KEYPROV_DUK_UPDATE_DISABLE
+#define MCUXCLCSS_KEYPROV_DUK_UPDATE_ENABLE  MCUXCLELS_KEYPROV_DUK_UPDATE_ENABLE
+#define MCUXCLCSS_KEYPROV_KEYSHARE_TABLE_SIZE  MCUXCLELS_KEYPROV_KEYSHARE_TABLE_SIZE
+#define MCUXCLCSS_KEYPROV_KEY_PART_1_SIZE  MCUXCLELS_KEYPROV_KEY_PART_1_SIZE
+#define MCUXCLCSS_KEYPROV_NOIC_DISABLE  MCUXCLELS_KEYPROV_NOIC_DISABLE
+#define MCUXCLCSS_KEYPROV_NOIC_ENABLE  MCUXCLELS_KEYPROV_NOIC_ENABLE
+#define MCUXCLCSS_KEYPROV_TESTERSHARE_SIZE  MCUXCLELS_KEYPROV_TESTERSHARE_SIZE
+#define MCUXCLCSS_KEYPROV_VALUE_NOIC  MCUXCLELS_KEYPROV_VALUE_NOIC
+#define MCUXCLCSS_KEY_SLOTS  MCUXCLELS_KEY_SLOTS
+#define MCUXCLCSS_MASTER_UNLOCK_ANY  MCUXCLELS_MASTER_UNLOCK_ANY
+#define MCUXCLCSS_RESET_CANCEL  MCUXCLELS_RESET_CANCEL
+#define MCUXCLCSS_RESET_DO_NOT_CANCEL  MCUXCLELS_RESET_DO_NOT_CANCEL
+#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_0  MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_0
+#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_1  MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_1
+#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_2  MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_2
+#define MCUXCLCSS_RESP_GEN_SLOTS  MCUXCLELS_RESP_GEN_SLOTS
+#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_128  MCUXCLELS_RFC3394_CONTAINER_SIZE_128
+#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_256  MCUXCLELS_RFC3394_CONTAINER_SIZE_256
+#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_P256  MCUXCLELS_RFC3394_CONTAINER_SIZE_P256
+#define MCUXCLCSS_RFC3394_OVERHEAD  MCUXCLELS_RFC3394_OVERHEAD
+#define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE  MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE
+#define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE  MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_CTR  MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_ECB  MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_EXTRACT  MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_INSTANTIATE  MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE
+#define MCUXCLCSS_RNG_DTRNG_CONFIG_SIZE  MCUXCLELS_RNG_DTRNG_CONFIG_SIZE
+#define MCUXCLCSS_RNG_DTRNG_EVAL_CONFIG_SIZE  MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE
+#define MCUXCLCSS_RNG_DTRNG_EVAL_RESULT_SIZE  MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE
+#define MCUXCLCSS_RNG_RAW_ENTROPY_SIZE  MCUXCLELS_RNG_RAW_ENTROPY_SIZE
+#define MCUXCLCSS_RNG_RND_REQ_PRND_INIT  MCUXCLELS_RNG_RND_REQ_PRND_INIT
+#define MCUXCLCSS_RNG_RND_REQ_RND_RAW  MCUXCLELS_RNG_RND_REQ_RND_RAW
+#define MCUXCLCSS_STATUS_DRBGENTLVL_HIGH  MCUXCLELS_STATUS_DRBGENTLVL_HIGH
+#define MCUXCLCSS_STATUS_DRBGENTLVL_LOW  MCUXCLELS_STATUS_DRBGENTLVL_LOW
+#define MCUXCLCSS_STATUS_DRBGENTLVL_NONE  MCUXCLELS_STATUS_DRBGENTLVL_NONE
+#define MCUXCLCSS_STATUS_ECDSAVFY_ERROR  MCUXCLELS_STATUS_ECDSAVFY_ERROR
+#define MCUXCLCSS_STATUS_ECDSAVFY_FAIL  MCUXCLELS_STATUS_ECDSAVFY_FAIL
+#define MCUXCLCSS_STATUS_ECDSAVFY_NORUN  MCUXCLELS_STATUS_ECDSAVFY_NORUN
+#define MCUXCLCSS_STATUS_ECDSAVFY_OK  MCUXCLELS_STATUS_ECDSAVFY_OK
+#define MCUXCLCSS_STATUS_HW_ALGORITHM  MCUXCLELS_STATUS_HW_ALGORITHM
+#define MCUXCLCSS_STATUS_HW_BUS  MCUXCLELS_STATUS_HW_BUS
+#define MCUXCLCSS_STATUS_HW_DTRNG  MCUXCLELS_STATUS_HW_DTRNG
+#define MCUXCLCSS_STATUS_HW_FAULT  MCUXCLELS_STATUS_HW_FAULT
+#define MCUXCLCSS_STATUS_HW_INTEGRITY  MCUXCLELS_STATUS_HW_INTEGRITY
+#define MCUXCLCSS_STATUS_HW_OPERATIONAL  MCUXCLELS_STATUS_HW_OPERATIONAL
+#define MCUXCLCSS_STATUS_HW_PRNG  MCUXCLELS_STATUS_HW_PRNG
+#define MCUXCLCSS_STATUS_IS_HW_ERROR  MCUXCLELS_STATUS_IS_HW_ERROR
+#define MCUXCLCSS_STATUS_IS_SW_ERROR  MCUXCLELS_STATUS_IS_SW_ERROR
+#define MCUXCLCSS_STATUS_OK  MCUXCLELS_STATUS_OK
+#define MCUXCLCSS_STATUS_OK_WAIT  MCUXCLELS_STATUS_OK_WAIT
+#define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_NONSECURE  MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE
+#define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_SECURE  MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE
+#define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_NONSECURE  MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE
+#define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_SECURE  MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE
+#define MCUXCLCSS_STATUS_SW_CANNOT_INTERRUPT  MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT
+#define MCUXCLCSS_STATUS_SW_COMPARISON_FAILED  MCUXCLELS_STATUS_SW_COMPARISON_FAILED
+#define MCUXCLCSS_STATUS_SW_COUNTER_EXPIRED  MCUXCLELS_STATUS_SW_COUNTER_EXPIRED
+#define MCUXCLCSS_STATUS_SW_FAULT  MCUXCLELS_STATUS_SW_FAULT
+#define MCUXCLCSS_STATUS_SW_INVALID_PARAM  MCUXCLELS_STATUS_SW_INVALID_PARAM
+#define MCUXCLCSS_STATUS_SW_INVALID_STATE  MCUXCLELS_STATUS_SW_INVALID_STATE
+#define MCUXCLCSS_STATUS_SW_LOCKING_FAILED  MCUXCLELS_STATUS_SW_LOCKING_FAILED
+#define MCUXCLCSS_STATUS_SW_STATUS_LOCKED  MCUXCLELS_STATUS_SW_STATUS_LOCKED
+#define MCUXCLCSS_TLS_DERIVATIONDATA_SIZE  MCUXCLELS_TLS_DERIVATIONDATA_SIZE
+#define MCUXCLCSS_TLS_FINALIZE  MCUXCLELS_TLS_FINALIZE
+#define MCUXCLCSS_TLS_INIT  MCUXCLELS_TLS_INIT
+#define MCUXCLCSS_TLS_RANDOM_SIZE  MCUXCLELS_TLS_RANDOM_SIZE
+
+
+/* Public types */
+/**
+ * mcuxClCss_((?:AeadOption_t|CipherOption_t|CkdfOption_t|CmacOption_t|CommandCrcConfig_t|EccByte_t|EccKeyExchOption_t|EccKeyGenOption_t|EccSignOption_t|EccVerifyOption_t|ErrorHandling_t|HashOption_t|HkdfOption_t|HmacOption_t|HwConfig_t|HwState_t|HwVersion_t|InterruptOptionEn_t|InterruptOptionRst_t|InterruptOptionSet_t|KeyImportOption_t|KeyIndex_t|KeyProp_t|KeyProvisionOption_t|ResetOption_t|Status_Protected_t|Status_t|TlsOption_t|TransferToRegisterFunction_t))(?!\w)
+ * -->
+ * mcuxClEls_\1
+ */
+#define mcuxClCss_AeadOption_t  mcuxClEls_AeadOption_t
+#define mcuxClCss_CipherOption_t  mcuxClEls_CipherOption_t
+#define mcuxClCss_CkdfOption_t  mcuxClEls_CkdfOption_t
+#define mcuxClCss_CmacOption_t  mcuxClEls_CmacOption_t
+#define mcuxClCss_CommandCrcConfig_t  mcuxClEls_CommandCrcConfig_t
+#define mcuxClCss_EccByte_t  mcuxClEls_EccByte_t
+#define mcuxClCss_EccKeyExchOption_t  mcuxClEls_EccKeyExchOption_t
+#define mcuxClCss_EccKeyGenOption_t  mcuxClEls_EccKeyGenOption_t
+#define mcuxClCss_EccSignOption_t  mcuxClEls_EccSignOption_t
+#define mcuxClCss_EccVerifyOption_t  mcuxClEls_EccVerifyOption_t
+#define mcuxClCss_ErrorHandling_t  mcuxClEls_ErrorHandling_t
+#define mcuxClCss_HashOption_t  mcuxClEls_HashOption_t
+#define mcuxClCss_HkdfOption_t  mcuxClEls_HkdfOption_t
+#define mcuxClCss_HmacOption_t  mcuxClEls_HmacOption_t
+#define mcuxClCss_HwConfig_t  mcuxClEls_HwConfig_t
+#define mcuxClCss_HwState_t  mcuxClEls_HwState_t
+#define mcuxClCss_HwVersion_t  mcuxClEls_HwVersion_t
+#define mcuxClCss_InterruptOptionEn_t  mcuxClEls_InterruptOptionEn_t
+#define mcuxClCss_InterruptOptionRst_t  mcuxClEls_InterruptOptionRst_t
+#define mcuxClCss_InterruptOptionSet_t  mcuxClEls_InterruptOptionSet_t
+#define mcuxClCss_KeyImportOption_t  mcuxClEls_KeyImportOption_t
+#define mcuxClCss_KeyIndex_t  mcuxClEls_KeyIndex_t
+#define mcuxClCss_KeyProp_t  mcuxClEls_KeyProp_t
+#define mcuxClCss_KeyProvisionOption_t  mcuxClEls_KeyProvisionOption_t
+#define mcuxClCss_ResetOption_t  mcuxClEls_ResetOption_t
+#define mcuxClCss_Status_Protected_t  mcuxClEls_Status_Protected_t
+#define mcuxClCss_Status_t  mcuxClEls_Status_t
+#define mcuxClCss_TlsOption_t  mcuxClEls_TlsOption_t
+#define mcuxClCss_TransferToRegisterFunction_t  mcuxClEls_TransferToRegisterFunction_t
+
+
+/* Public functions */
+/**
+ * mcuxClCss_((?:Aead_Finalize_Async|Aead_Init_Async|Aead_PartialInit_Async|Aead_UpdateAad_Async|Aead_UpdateData_Async|Cipher_Async|Ckdf_Sp800108_Async|Ckdf_Sp80056c_Expand_Async|Ckdf_Sp80056c_Extract_Async|Cmac_Async|CompareDmaFinalOutputAddress|ConfigureCommandCRC|Disable|EccKeyExchangeInt_Async|EccKeyExchange_Async|EccKeyGen_Async|EccSign_Async|EccVerifyInt_Async|EccVerify_Async|Enable_Async|GetCommandCRC|GetErrorCode|GetErrorLevel|GetHwConfig|GetHwState|GetHwVersion|GetIntEnableFlags|GetKeyProperties|GetLastDmaAddress|GetLock|GetRandomStartDelay|GlitchDetector_GetEventCounter|GlitchDetector_LoadConfig_Async|GlitchDetector_ResetEventCounter|GlitchDetector_Trim_Async|Hash_Async|Hash_ShaDirect|Hkdf_Rfc5869_Async|Hkdf_Sp80056c_Async|Hmac_Async|IsLocked|KeyDelete_Async|KeyExport_Async|KeyImportPuk_Async|KeyImport_Async|KeyProvisionRom_Async|KeyProvision_Async|LimitedWaitForOperation|Prng_GetRandom|Prng_GetRandomWord|Prng_Init_Async|ReleaseLock|ResetErrorFlags|ResetIntFlags|Reset_Async|RespGen_Async|Rng_DrbgRequestRaw_Async|Rng_DrbgRequest_Async|Rng_DrbgTestAesCtr_Async|Rng_DrbgTestAesEcb_Async|Rng_DrbgTestExtract_Async|Rng_DrbgTestInstantiate_Async|Rng_Dtrng_ConfigEvaluate_Async|Rng_Dtrng_ConfigLoadPrv_Async|Rng_Dtrng_ConfigLoad_Async|SetIntEnableFlags|SetIntFlags|SetMasterUnlock|SetRandomStartDelay|ShaDirect_Disable|ShaDirect_Enable|TlsGenerateMasterKeyFromPreMasterKey_Async|TlsGenerateSessionKeysFromMasterKey_Async|UpdateRefCRC|VerifyVsRefCRC|WaitForOperation))(?!\w)
+ * -->
+ * mcuxClEls_\1
+ */
+#define mcuxClCss_Aead_Finalize_Async  mcuxClEls_Aead_Finalize_Async
+#define mcuxClCss_Aead_Init_Async  mcuxClEls_Aead_Init_Async
+#define mcuxClCss_Aead_PartialInit_Async  mcuxClEls_Aead_PartialInit_Async
+#define mcuxClCss_Aead_UpdateAad_Async  mcuxClEls_Aead_UpdateAad_Async
+#define mcuxClCss_Aead_UpdateData_Async  mcuxClEls_Aead_UpdateData_Async
+#define mcuxClCss_Cipher_Async  mcuxClEls_Cipher_Async
+#define mcuxClCss_Ckdf_Sp800108_Async  mcuxClEls_Ckdf_Sp800108_Async
+#define mcuxClCss_Ckdf_Sp80056c_Expand_Async  mcuxClEls_Ckdf_Sp80056c_Expand_Async
+#define mcuxClCss_Ckdf_Sp80056c_Extract_Async  mcuxClEls_Ckdf_Sp80056c_Extract_Async
+#define mcuxClCss_Cmac_Async  mcuxClEls_Cmac_Async
+#define mcuxClCss_CompareDmaFinalOutputAddress  mcuxClEls_CompareDmaFinalOutputAddress
+#define mcuxClCss_ConfigureCommandCRC  mcuxClEls_ConfigureCommandCRC
+#define mcuxClCss_Disable  mcuxClEls_Disable
+#define mcuxClCss_EccKeyExchangeInt_Async  mcuxClEls_EccKeyExchangeInt_Async
+#define mcuxClCss_EccKeyExchange_Async  mcuxClEls_EccKeyExchange_Async
+#define mcuxClCss_EccKeyGen_Async  mcuxClEls_EccKeyGen_Async
+#define mcuxClCss_EccSign_Async  mcuxClEls_EccSign_Async
+#define mcuxClCss_EccVerifyInt_Async  mcuxClEls_EccVerifyInt_Async
+#define mcuxClCss_EccVerify_Async  mcuxClEls_EccVerify_Async
+#define mcuxClCss_Enable_Async  mcuxClEls_Enable_Async
+#define mcuxClCss_GetCommandCRC  mcuxClEls_GetCommandCRC
+#define mcuxClCss_GetErrorCode  mcuxClEls_GetErrorCode
+#define mcuxClCss_GetErrorLevel  mcuxClEls_GetErrorLevel
+#define mcuxClCss_GetHwConfig  mcuxClEls_GetHwConfig
+#define mcuxClCss_GetHwState  mcuxClEls_GetHwState
+#define mcuxClCss_GetHwVersion  mcuxClEls_GetHwVersion
+#define mcuxClCss_GetIntEnableFlags  mcuxClEls_GetIntEnableFlags
+#define mcuxClCss_GetKeyProperties  mcuxClEls_GetKeyProperties
+#define mcuxClCss_GetLastDmaAddress  mcuxClEls_GetLastDmaAddress
+#define mcuxClCss_GetLock  mcuxClEls_GetLock
+#define mcuxClCss_GetRandomStartDelay  mcuxClEls_GetRandomStartDelay
+#define mcuxClCss_GlitchDetector_GetEventCounter  mcuxClEls_GlitchDetector_GetEventCounter
+#define mcuxClCss_GlitchDetector_LoadConfig_Async  mcuxClEls_GlitchDetector_LoadConfig_Async
+#define mcuxClCss_GlitchDetector_ResetEventCounter  mcuxClEls_GlitchDetector_ResetEventCounter
+#define mcuxClCss_GlitchDetector_Trim_Async  mcuxClEls_GlitchDetector_Trim_Async
+#define mcuxClCss_Hash_Async  mcuxClEls_Hash_Async
+#define mcuxClCss_Hash_ShaDirect  mcuxClEls_Hash_ShaDirect
+#define mcuxClCss_Hkdf_Rfc5869_Async  mcuxClEls_Hkdf_Rfc5869_Async
+#define mcuxClCss_Hkdf_Sp80056c_Async  mcuxClEls_Hkdf_Sp80056c_Async
+#define mcuxClCss_Hmac_Async  mcuxClEls_Hmac_Async
+#define mcuxClCss_IsLocked  mcuxClEls_IsLocked
+#define mcuxClCss_KeyDelete_Async  mcuxClEls_KeyDelete_Async
+#define mcuxClCss_KeyExport_Async  mcuxClEls_KeyExport_Async
+#define mcuxClCss_KeyImportPuk_Async  mcuxClEls_KeyImportPuk_Async
+#define mcuxClCss_KeyImport_Async  mcuxClEls_KeyImport_Async
+#define mcuxClCss_KeyProvisionRom_Async  mcuxClEls_KeyProvisionRom_Async
+#define mcuxClCss_KeyProvision_Async  mcuxClEls_KeyProvision_Async
+#define mcuxClCss_LimitedWaitForOperation  mcuxClEls_LimitedWaitForOperation
+#define mcuxClCss_Prng_GetRandom  mcuxClEls_Prng_GetRandom
+#define mcuxClCss_Prng_GetRandomWord  mcuxClEls_Prng_GetRandomWord
+#define mcuxClCss_Prng_Init_Async  mcuxClEls_Prng_Init_Async
+#define mcuxClCss_ReleaseLock  mcuxClEls_ReleaseLock
+#define mcuxClCss_ResetErrorFlags  mcuxClEls_ResetErrorFlags
+#define mcuxClCss_ResetIntFlags  mcuxClEls_ResetIntFlags
+#define mcuxClCss_Reset_Async  mcuxClEls_Reset_Async
+#define mcuxClCss_RespGen_Async  mcuxClEls_RespGen_Async
+#define mcuxClCss_Rng_DrbgRequestRaw_Async  mcuxClEls_Rng_DrbgRequestRaw_Async
+#define mcuxClCss_Rng_DrbgRequest_Async  mcuxClEls_Rng_DrbgRequest_Async
+#define mcuxClCss_Rng_DrbgTestAesCtr_Async  mcuxClEls_Rng_DrbgTestAesCtr_Async
+#define mcuxClCss_Rng_DrbgTestAesEcb_Async  mcuxClEls_Rng_DrbgTestAesEcb_Async
+#define mcuxClCss_Rng_DrbgTestExtract_Async  mcuxClEls_Rng_DrbgTestExtract_Async
+#define mcuxClCss_Rng_DrbgTestInstantiate_Async  mcuxClEls_Rng_DrbgTestInstantiate_Async
+#define mcuxClCss_Rng_Dtrng_ConfigEvaluate_Async  mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async
+#define mcuxClCss_Rng_Dtrng_ConfigLoadPrv_Async  mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async
+#define mcuxClCss_Rng_Dtrng_ConfigLoad_Async  mcuxClEls_Rng_Dtrng_ConfigLoad_Async
+#define mcuxClCss_SetIntEnableFlags  mcuxClEls_SetIntEnableFlags
+#define mcuxClCss_SetIntFlags  mcuxClEls_SetIntFlags
+#define mcuxClCss_SetMasterUnlock  mcuxClEls_SetMasterUnlock
+#define mcuxClCss_SetRandomStartDelay  mcuxClEls_SetRandomStartDelay
+#define mcuxClCss_ShaDirect_Disable  mcuxClEls_ShaDirect_Disable
+#define mcuxClCss_ShaDirect_Enable  mcuxClEls_ShaDirect_Enable
+#define mcuxClCss_TlsGenerateMasterKeyFromPreMasterKey_Async  mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async
+#define mcuxClCss_TlsGenerateSessionKeysFromMasterKey_Async  mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async
+#define mcuxClCss_UpdateRefCRC  mcuxClEls_UpdateRefCRC
+#define mcuxClCss_VerifyVsRefCRC  mcuxClEls_VerifyVsRefCRC
+#define mcuxClCss_WaitForOperation  mcuxClEls_WaitForOperation
+
+/**
+ * There are also corresponding changes in other components:
+ * mcuxClMac_Mode_HMAC_SHA2_256_CSS  ->  mcuxClMac_Mode_HMAC_SHA2_256_ELS
+ * mcuxClRandomModes_Mode_CSS_Drbg   ->  mcuxClRandomModes_Mode_ELS_Drbg
+ */
+
+#endif /* MCUXCLELS_MAPPING_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Common.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Common.c
new file mode 100644
index 0000000000..0b04ab9a49
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Common.c
@@ -0,0 +1,383 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClEls_Common.c
+ *  @brief ELS implementation for common functionality.
+ *  This file implements the functions declared in mcuxClEls_Common.h and adds helper functions used by other implementation headers. */
+
+#include <stdbool.h>
+#include <platform_specific_headers.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClEls.h>
+#include <internal/mcuxClEls_Internal.h>
+#include <internal/mcuxClEls_Internal_Common.h>
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetHwVersion)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwVersion(
+    mcuxClEls_HwVersion_t * result)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetHwVersion);
+    result->word.value = MCUXCLELS_SFR_READ(ELS_VERSION);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetHwVersion, MCUXCLELS_STATUS_OK);
+}
+
+#ifdef MCUXCL_FEATURE_ELS_HWCONFIG
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetHwConfig)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwConfig(
+    mcuxClEls_HwConfig_t * result)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetHwConfig);
+    result->word.value = MCUXCLELS_SFR_READ(ELS_CONFIG);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetHwConfig, MCUXCLELS_STATUS_OK);
+}
+#endif /* MCUXCL_FEATURE_ELS_HWCONFIG */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetHwState)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwState(
+    mcuxClEls_HwState_t * result)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetHwState);
+    result->word.value = MCUXCLELS_SFR_READ(ELS_STATUS);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetHwState, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Enable_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Enable_Async(
+    void)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Enable_Async);
+    const uint32_t sfrVal =  MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_EN, 1u);
+    MCUXCLELS_SFR_WRITE(ELS_CTRL, sfrVal);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Enable_Async, MCUXCLELS_STATUS_OK_WAIT);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Disable)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Disable(
+    void)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Disable);
+    MCUXCLELS_SET_CTRL_FIELD(MCUXCLELS_SFR_CTRL_ELS_EN, 0u);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Disable, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetErrorCode)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorCode(
+    mcuxClEls_ErrorHandling_t errorHandling)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetErrorCode);
+
+    mcuxClEls_Status_t result = MCUXCLELS_STATUS_SW_FAULT;
+    if (1U == MCUXCLELS_GET_STATUS_FIELD(MCUXCLELS_SFR_STATUS_ELS_ERR))
+    {
+        if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_FLT_ERR))
+        {
+            result = MCUXCLELS_STATUS_HW_FAULT;
+        }
+        else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_ITG_ERR))
+        {
+            result = MCUXCLELS_STATUS_HW_INTEGRITY;
+        }
+        else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_OPN_ERR))
+        {
+            result = MCUXCLELS_STATUS_HW_OPERATIONAL;
+        }
+        else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_ALG_ERR))
+        {
+            result = MCUXCLELS_STATUS_HW_ALGORITHM;
+        }
+        else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_BUS_ERR))
+        {
+            result = MCUXCLELS_STATUS_HW_BUS;
+        }
+        else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_PRNG_ERR))
+        {
+            result = MCUXCLELS_STATUS_HW_PRNG;
+        }
+        else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_DTRNG_ERR))
+        {
+            result = MCUXCLELS_STATUS_HW_DTRNG;
+        }
+        else
+        {
+            result = MCUXCLELS_STATUS_SW_FAULT;
+        }
+    }
+    else
+    {
+        result = MCUXCLELS_STATUS_OK;
+    }
+
+    if (MCUXCLELS_ERROR_FLAGS_CLEAR == errorHandling){
+        MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_ResetErrorFlags()); /* always returns MCUXCLELS_STATUS_OK. */
+
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetErrorCode, result,
+            MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_ResetErrorFlags));
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetErrorCode, result);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetErrorLevel)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorLevel(
+    mcuxClEls_ErrorHandling_t errorHandling,
+    uint32_t *errorLevel)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetErrorLevel);
+
+    *errorLevel = MCUXCLELS_GET_ERROR_STATUS_FIELD(MCUXCLELS_SFR_ERR_STATUS_ERR_LVL);
+
+    MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_GetErrorCode(errorHandling));
+
+    /* Exit function with expectation: mcuxClEls_GetErrorCode was called unconditionally */
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetErrorLevel, result,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetErrorCode));
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_WaitForOperation)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_WaitForOperation(
+    mcuxClEls_ErrorHandling_t errorHandling)
+{
+    /* Enter flow-protected function with expectation: mcuxClEls_GetErrorCode will be called (unconditionally) */
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_WaitForOperation,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetErrorCode));
+
+    while (mcuxClEls_isBusy())
+    {
+        // Do nothing
+    }
+
+    MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_GetErrorCode(errorHandling));
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_WaitForOperation, result);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_LimitedWaitForOperation)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_LimitedWaitForOperation(
+    uint32_t counterLimit,
+    mcuxClEls_ErrorHandling_t errorHandling)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_LimitedWaitForOperation);
+
+    bool counterExpired = true;
+    while (0U != counterLimit)
+    {
+        if (!mcuxClEls_isBusy())
+        {
+            counterExpired = false;
+            break;
+        }
+        counterLimit--;
+    }
+
+    if (true == counterExpired)
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_LimitedWaitForOperation, MCUXCLELS_STATUS_SW_COUNTER_EXPIRED);
+    }
+
+    MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_GetErrorCode(errorHandling));
+
+    /* Exit function with expectation: mcuxClEls_GetErrorCode was called */
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_LimitedWaitForOperation, result,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetErrorCode));
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_ResetErrorFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetErrorFlags(
+    void)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_ResetErrorFlags);
+    const uint32_t sfrVal = MCUXCLELS_SFR_FIELD_FORMAT(ELS_ERR_STATUS, CLR_ERR_CLR, MCUXCLELS_ERROR_FLAGS_CLEAR);
+    MCUXCLELS_SFR_WRITE(ELS_ERR_STATUS_CLR, sfrVal);
+    // Poll error bit to be sure that error bits has been cleared. Required by HW spec.
+    while(0u != MCUXCLELS_GET_STATUS_FIELD(MCUXCLELS_SFR_STATUS_ELS_ERR))
+    {
+        // Do nothing
+    }
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_ResetErrorFlags, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Reset_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Reset_Async(
+    mcuxClEls_ResetOption_t options)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Reset_Async);
+
+    if (mcuxClEls_isBusy() && (MCUXCLELS_RESET_DO_NOT_CANCEL == options))
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Reset_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT);
+    }
+
+#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING
+    /* Set the drbg_block_counter to a value triggering a reseed after the upcoming RESET operation via interrupt */
+    mcuxClEls_rng_drbg_block_counter = MCUXCLELS_RNG_DRBG_BLOCK_COUNTER_THRESHOLD;
+#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */
+
+    MCUXCLELS_SET_CTRL_FIELD(MCUXCLELS_SFR_CTRL_RESET, 1u);
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Reset_Async, MCUXCLELS_STATUS_OK_WAIT);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetIntEnableFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntEnableFlags(
+    mcuxClEls_InterruptOptionEn_t options)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetIntEnableFlags);
+    MCUXCLELS_SFR_WRITE(ELS_INT_ENABLE, options.word.value);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetIntEnableFlags, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetIntEnableFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetIntEnableFlags(
+    mcuxClEls_InterruptOptionEn_t * result)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetIntEnableFlags);
+    result->word.value = MCUXCLELS_SFR_READ(ELS_INT_ENABLE);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetIntEnableFlags, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_ResetIntFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetIntFlags(
+    mcuxClEls_InterruptOptionRst_t options)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_ResetIntFlags);
+    MCUXCLELS_SFR_WRITE(ELS_INT_STATUS_CLR, options.word.value);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_ResetIntFlags, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetIntFlags)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntFlags(
+    mcuxClEls_InterruptOptionSet_t options)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetIntFlags);
+    MCUXCLELS_SFR_WRITE(ELS_INT_STATUS_SET, options.word.value);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetIntFlags, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetRandomStartDelay)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetRandomStartDelay(
+    uint32_t startDelay)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetRandomStartDelay);
+    MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_SetRandomStartDelay, 1024u < startDelay);
+
+    if (mcuxClEls_isBusy())
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetRandomStartDelay, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT);
+    }
+
+    MCUXCLELS_SET_CFG_FIELD(MCUXCLELS_SFR_CFG_ADCTRL, startDelay);
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetRandomStartDelay, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetRandomStartDelay)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetRandomStartDelay(
+    uint32_t *startDelay)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetRandomStartDelay);
+
+    *startDelay = MCUXCLELS_GET_CFG_FIELD(MCUXCLELS_SFR_CFG_ADCTRL);
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetRandomStartDelay, MCUXCLELS_STATUS_OK);
+}
+
+#ifdef MCUXCL_FEATURE_ELS_LOCKING
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetLock)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLock(
+    uint32_t * pSessionId)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetLock);
+
+    *pSessionId = MCUXCLELS_SFR_READ(ELS_SESSION_ID);
+    if(0u == *pSessionId)
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetLock, MCUXCLELS_STATUS_SW_LOCKING_FAILED);
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetLock, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_ReleaseLock)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ReleaseLock(
+    uint32_t sessionId)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_ReleaseLock);
+    MCUXCLELS_SFR_WRITE(ELS_SESSION_ID, sessionId);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_ReleaseLock, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_IsLocked)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_IsLocked(
+    void)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_IsLocked);
+
+    if(1u == MCUXCLELS_GET_STATUS_FIELD(MCUXCLELS_SFR_STATUS_ELS_LOCKED))
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_IsLocked, MCUXCLELS_STATUS_SW_STATUS_LOCKED);
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_IsLocked, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetMasterUnlock)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetMasterUnlock(
+    uint32_t masterId)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetMasterUnlock);
+    MCUXCLELS_SFR_WRITE(ELS_MASTER_ID, masterId);
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetMasterUnlock, MCUXCLELS_STATUS_OK);
+}
+#endif /* MCUXCL_FEATURE_ELS_LOCKING */
+
+
+#ifdef MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetLastDmaAddress)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLastDmaAddress(uint32_t* pLastAddress)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetLastDmaAddress);
+
+    *pLastAddress = MCUXCLELS_SFR_READ(ELS_DMA_FIN_ADDR);
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetLastDmaAddress, MCUXCLELS_STATUS_OK);
+
+}
+#endif /* MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK */
+
+#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_CompareDmaFinalOutputAddress)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_CompareDmaFinalOutputAddress(
+        uint8_t *outputStartAddress,
+        size_t expectedLength)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_CompareDmaFinalOutputAddress,
+                               MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetLastDmaAddress));
+
+    /* Calculate the expected final address from the input */
+    uint32_t expectedFinalAddress = (uint32_t)outputStartAddress + expectedLength;
+
+    /* Get the actual final address from ELS - no result check as function always returns OK */
+    uint32_t finalAddress;
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_GetLastDmaAddress(&finalAddress));
+
+    /* Compare the expected address to the actual one */
+    if(finalAddress != expectedFinalAddress)
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_CompareDmaFinalOutputAddress, MCUXCLELS_STATUS_SW_COMPARISON_FAILED);
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_CompareDmaFinalOutputAddress, MCUXCLELS_STATUS_OK);
+
+}
+#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_GlitchDetector.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_GlitchDetector.c
new file mode 100644
index 0000000000..f5a806cda5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_GlitchDetector.c
@@ -0,0 +1,98 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2022 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClEls_GlitchDetector.c
+ *  @brief ELS implementation for key management.
+ * This file implements the functions declared in mcuxClEls_GlitchDetector.h. */
+
+#include <mcuxClEls_GlitchDetector.h>
+#include <stdbool.h>
+#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <internal/mcuxClEls_Internal.h>
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_LoadConfig_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_LoadConfig_Async(
+    uint8_t const * pInput)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_LoadConfig_Async);
+    
+    /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */
+    if (mcuxClEls_isBusy())
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_LoadConfig_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT);
+    }
+    
+    mcuxClEls_setInput0_fixedSize(pInput);
+    mcuxClEls_startCommand(ID_CFG_ELS_CMD_GDET_CFG_LOAD, 0U, ELS_CMD_BIG_ENDIAN);
+    
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_LoadConfig_Async, MCUXCLELS_STATUS_OK_WAIT);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_Trim_Async)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_Trim_Async(
+    uint8_t * pOutput)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_Trim_Async);
+    
+    /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */
+    if (mcuxClEls_isBusy())
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_Trim_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT);
+    }
+    
+    mcuxClEls_setOutput_fixedSize(pOutput);
+    mcuxClEls_startCommand(ID_CFG_ELS_CMD_GDET_TRIM, 0U, ELS_CMD_BIG_ENDIAN);
+
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_Trim_Async, MCUXCLELS_STATUS_OK_WAIT);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_GetEventCounter)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_GetEventCounter(
+    uint8_t * pCount)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_GetEventCounter);
+
+    // Decode from Gray coding
+    uint8_t count8 = (uint8_t) MCUXCLELS_GET_GDET_EVTCNT_FIELD(MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT);
+    count8 ^= count8 >> 4u;
+    count8 ^= count8 >> 2u;
+    count8 ^= count8 >> 1u;
+    
+    // Assign to the result variable
+    *pCount = count8;
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_GetEventCounter, MCUXCLELS_STATUS_OK);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_ResetEventCounter)
+MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_ResetEventCounter(
+    void)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_ResetEventCounter);
+
+    // Start GDET Event Counter reset
+    MCUXCLELS_SFR_WRITE(ELS_GDET_EVTCNT_CLR, 1u);
+
+    // The actual reset occurs in a different clock domain from the ELS core clock, so we have to wait for synchroni-
+    // zation. The spec states that this takes on the order of 2 cycles of the ELS core clock plus 2 cycles of the
+    // Glitch Detector reference clock.
+    while(1u != MCUXCLELS_GET_GDET_EVTCNT_FIELD(MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE))
+    {
+        // Do nothing
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_ResetEventCounter, MCUXCLELS_STATUS_OK);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_ClearSecure_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_ClearSecure_Internal.h
new file mode 100644
index 0000000000..12f75667a6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_ClearSecure_Internal.h
@@ -0,0 +1,85 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_ClearSecure_Internal.h
+ *  @brief Memory header for secure clear function.
+ * This header exposes functions that enable secure memory clear function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Clear_Secure_Internal mcuxClMemory_Clear_Secure_Internal
+ * @brief This function clears all bytes in a memory region to null in a secure way 
+ * when a secure clear is available.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_CLEARSECURE_INTERNAL_H_
+#define MCUXCLMEMORY_CLEARSECURE_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxCsslFlowProtection.h>
+#include <internal/mcuxClMemory_SetSecure_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Sets all bytes of a memory buffer to a specified value.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pSrc + pDst + length)
+ *  
+ * @param[out]  pDst       pointer to the buffer to be set.
+ * @param[in]   length     size (in bytes) to be set.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes cleared at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_clear_secure_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_clear_secure_int
+(
+    uint8_t * pDst,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_clear_secure_int);
+
+        MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxClMemory_set_secure_int(pDst, 0u, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_clear_secure_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set_secure_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_CLEARSECURE_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Clear_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Clear_Internal.h
new file mode 100644
index 0000000000..cecd396dc0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Clear_Internal.h
@@ -0,0 +1,94 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Clear_Internal.h
+ *  @brief Memory header for clear function.
+ * This header exposes functions that enable using memory clear function.
+ */
+
+
+/**
+ * @defgroup mcuxClMemory_Clear_Internal mcuxClMemory_Clear_Internal
+ * @brief This function clears a memory region.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+
+#ifndef MCUXCLMEMORY_CLEAR_INTERNAL_H_
+#define MCUXCLMEMORY_CLEAR_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslDataIntegrity.h>
+#include <mcuxCsslMemory.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Sets all bytes of a memory buffer to a specified value.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pDst + length)
+ *  
+ * @param[out]  pDst       pointer to the buffer to be set.
+ * @param[in]   length     size (in bytes) to be set.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes cleared at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_clear_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_clear_int
+(
+    uint8_t * pDst,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_clear_int);
+
+        mcuxClMemory_Status_t retval = MCUXCLMEMORY_STATUS_FAULT;
+        MCUX_CSSL_FP_FUNCTION_CALL(csslRetval, mcuxCsslMemory_Clear(
+            mcuxCsslParamIntegrity_Protect(3u, pDst, length, length),
+            pDst,
+            length,
+            length));
+        retval = (mcuxClMemory_Status_t) csslRetval ^ (MCUXCSSLMEMORY_COMPONENT_MASK ^ MCUXCLMEMORY_COMPONENT_MASK);
+        MCUX_CSSL_DI_RECORD(identifier /* Not used */, (uint32_t) pDst + length);  // Unbalance the SC
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_clear_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Clear));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_CLEAR_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CompareDPASecure_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CompareDPASecure_Internal.h
new file mode 100644
index 0000000000..c817998859
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CompareDPASecure_Internal.h
@@ -0,0 +1,89 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_CompareDPASecure_Internal.h
+ *  @brief Memory header for dpa secure compare function.
+ * This header exposes functions that enable dpa secure memory compare function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Compare_DPASecure_Internal mcuxClMemory_Compare_DPASecure_Internal
+ * @brief This function compares two memory region @p lhs and @p rhs.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COMPARE_DPA_SECURE_INTERNAL_H_
+#define MCUXCLMEMORY_COMPARE_DPA_SECURE_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClSession_Types.h>
+#include <internal/mcuxClMemory_CompareSecure_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Compares two memory buffers with security against fault and DPA.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pLhs + pRhs + length)
+ *  
+ * @param[in]  session     Handle for the current CL session.
+ * @param[in]  pLhs        pointer to the left buffer to be compared.
+ * @param[in]  pRhs        pointer to the right buffer to be compared.
+ * @param[in]  length      size (in bytes) to be compared.
+ * 
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_EQUAL                 If length bytes of Lhs and Rhs are equal.
+ * @retval #MCUXCLMEMORY_STATUS_NOT_EQUAL             If at least one bytes differ between the two.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_compare_dpasecure_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_compare_dpasecure_int
+(
+    mcuxClSession_Handle_t session,
+    const uint8_t * pLhs,
+    const uint8_t * pRhs,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_compare_dpasecure_int);
+
+        (void)session;
+        MCUX_CSSL_FP_FUNCTION_CALL(retClCompare, mcuxClMemory_compare_secure_int(pLhs, pRhs, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_compare_dpasecure_int, retClCompare, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_compare_secure_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COMPARE_DPA_SECURE_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CompareSecure_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CompareSecure_Internal.h
new file mode 100644
index 0000000000..7d24f0d772
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CompareSecure_Internal.h
@@ -0,0 +1,85 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_CompareSecure_Internal.h
+ *  @brief Memory header for compare function.
+ * This header exposes functions that enable secure memory compare function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Compare_Internal mcuxClMemory_Compare_Secure_Internal
+ * @brief This function compares two memory region @p lhs and @p rhs.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COMPARE_SECURE_INTERNAL_H_
+#define MCUXCLMEMORY_COMPARE_SECURE_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslFlowProtection.h>
+#include <internal/mcuxClMemory_Compare_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Compares two memory buffers with security against fault and SPA.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pLhs + pRhs + length)
+ *  
+ * @param[in]  pLhs        pointer to the left buffer to be compared.
+ * @param[in]  pRhs        pointer to the right buffer to be compared.
+ * @param[in]  length      size (in bytes) to be compared.
+ * 
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_EQUAL                 If length bytes of Lhs and Rhs are equal.
+ * @retval #MCUXCLMEMORY_STATUS_NOT_EQUAL             If at least one bytes differ between the two.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_compare_secure_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_compare_secure_int
+(
+    const uint8_t * pLhs,
+    const uint8_t * pRhs,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_compare_secure_int);
+
+        MCUX_CSSL_FP_FUNCTION_CALL(retClCompare, mcuxClMemory_compare_int(pLhs, pRhs, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_compare_secure_int, retClCompare, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_compare_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COMPARE_SECURE_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Compare_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Compare_Internal.h
new file mode 100644
index 0000000000..03474affd6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Compare_Internal.h
@@ -0,0 +1,91 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Compare_Internal.h
+ *  @brief Memory header for internal compare function.
+ * This header exposes functions that enable memory compare function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Compare_Internal mcuxClMemory_Compare_Internal
+ * @brief This function compares two memory region @p lhs and @p rhs.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COMPARE_INTERNAL_H_
+#define MCUXCLMEMORY_COMPARE_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslMemory.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslDataIntegrity.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Compares two memory buffer with security agains faults.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pLhs + pRhs + length)
+ *  
+ * @param[in]  pLhs        pointer to the left buffer to be compared.
+ * @param[in]  pRhs        pointer to the right buffer to be compared.
+ * @param[in]  length      size (in bytes) to be compared.
+ * 
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_EQUAL                 If length bytes of Lhs and Rhs are equal.
+ * @retval #MCUXCLMEMORY_STATUS_NOT_EQUAL             If at least one bytes differ between the two.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_compare_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_compare_int
+(
+    const uint8_t * pLhs,
+    const uint8_t * pRhs,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_compare_int);
+
+    mcuxClMemory_Status_t retval = MCUXCLMEMORY_STATUS_FAULT;
+
+        MCUX_CSSL_FP_FUNCTION_CALL(csslRetval, 
+            mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u,  pLhs, pRhs, length),
+            pLhs, pRhs, length));
+        retval = (mcuxClMemory_Status_t) csslRetval ^ (MCUXCSSLMEMORY_COMPONENT_MASK ^ MCUXCLMEMORY_COMPONENT_MASK);  // May return invalid parameters too.
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_compare_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COMPARE_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecurePow2_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecurePow2_Internal.h
new file mode 100644
index 0000000000..2994b3d338
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecurePow2_Internal.h
@@ -0,0 +1,85 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_CopySecurePow2_Internal.h
+ *  @brief Memory header for copy functions.
+ * This header exposes functions that enable secure memory copy function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_CopySecurePow2_Internal mcuxClMemory_CopySecurePow2_Internal
+ * @brief This function securely copies a memory region from @p src to @p dst when a secure copy is available.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPYSECURE_ALIGNED_INTERNAL_H_
+#define MCUXCLMEMORY_COPYSECURE_ALIGNED_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslFlowProtection.h>
+#include <internal/mcuxClMemory_CopySecure_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location with security against fault and SPA.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pSrc + pDst + length)
+ *  
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_secure_pow2_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_copy_secure_pow2_int
+(
+    uint8_t * pDst,
+    uint8_t const * pSrc,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_secure_pow2_int);
+
+        MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxClMemory_copy_secure_int(pDst, pSrc, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_copy_secure_pow2_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_secure_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COPYSECURE_ALIGNED_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecure_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecure_Internal.h
new file mode 100644
index 0000000000..8acfdeaaa4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecure_Internal.h
@@ -0,0 +1,85 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_CopySecure_Internal.h
+ *  @brief Memory header for copy functions.
+ * This header exposes functions that enable secure memory copy function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Copy_Secure_Internal mcuxClMemory_Copy_Secure_Internal
+ * @brief This function securely copies a memory region from @p src to @p dst when a secure copy is available.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPYSECURE_INTERNAL_H_
+#define MCUXCLMEMORY_COPYSECURE_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslFlowProtection.h>
+#include <internal/mcuxClMemory_Copy_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location with security against fault and SPA.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pSrc + pDst + length)
+ *  
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_secure_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_copy_secure_int
+(
+    uint8_t * pDst,
+    uint8_t const * pSrc,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_secure_int);
+
+        MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxClMemory_copy_int(pDst, pSrc, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_copy_secure_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COPYSECURE_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecure_Reversed_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecure_Reversed_Internal.h
new file mode 100644
index 0000000000..470879edf1
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopySecure_Reversed_Internal.h
@@ -0,0 +1,85 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_CopySecure_Reversed_Internal.h
+ *  @brief Memory header for copy functions.
+ * This header exposes functions that enable secure memory copy function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Copy_Secure_Reversed_Internal mcuxClMemory_Copy_Secure_Reversed_Internal
+ * @brief This function securely copies a memory region from @p src to @p dst when a secure copy is available.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPYSECURE_REVERSED_INTERNAL_H_
+#define MCUXCLMEMORY_COPYSECURE_REVERSED_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslFlowProtection.h>
+#include <internal/mcuxClMemory_Copy_Reversed_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location with security against fault and SPA.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pSrc + pDst + length)
+ *  
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_secure_reversed_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_copy_secure_reversed_int
+(
+    uint8_t * pDst,
+    uint8_t const * pSrc,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_secure_reversed_int);
+    
+        MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxClMemory_copy_reversed_int(pDst, pSrc, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_copy_secure_reversed_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COPYSECURE_REVERSED_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopyWords_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopyWords_Internal.h
new file mode 100644
index 0000000000..83fb72f5f7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_CopyWords_Internal.h
@@ -0,0 +1,88 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_CopyWords_Internal.h
+ *  @brief Memory header for copy functions.
+ * This header exposes functions that enable memory copy word function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Copy_Words_Internal mcuxClMemory_Copy_Words_Internal
+ * @brief This function copies a memory region from @p src to @p dst in a robust way
+ * when a  copy is available.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPYWORDS_INTERNAL_H_
+#define MCUXCLMEMORY_COPYWORDS_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClMemory_Copy.h>
+#include <internal/mcuxClMemory_Copy_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location with security against fault only.
+ *
+ * The two buffers must not overlap and with length being a multiple of 4.
+ * 
+ * * Data Integrity: Record(pSrc + pDst + length)
+ *  
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_words_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_copy_words_int
+(
+    uint8_t * pDst,
+    uint8_t const * pSrc,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_words_int);
+
+        MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxClMemory_copy_int(pDst, pSrc, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_copy_words_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COPYWORDS_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Internal.h
new file mode 100644
index 0000000000..d9b816babd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Internal.h
@@ -0,0 +1,89 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Copy_Internal.h
+ *  @brief Internal memory header for copy functions.
+ * This header exposes functions that enable using memory copy function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Copy_Internal mcuxClMemory_Copy_Internal
+ * @brief This function copies a memory region from @p src to @p dst.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPY_INTERNAL_H_
+#define MCUXCLMEMORY_COPY_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslDataIntegrity.h>
+#include <mcuxClMemory_Copy.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location with security against fault.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pSrc + pDst + length)
+ *  
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_copy_int
+(
+    uint8_t * pDst,
+    uint8_t const * pSrc,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_int);
+    mcuxClMemory_Status_t retval = MCUXCLMEMORY_STATUS_FAULT;
+
+        MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy(pDst, pSrc, length, length));
+        MCUX_CSSL_DI_RECORD(identifier /* Not used */, (uint32_t) pSrc + (uint32_t) pDst + length);  // Balance the SC
+        retval = MCUXCLMEMORY_STATUS_OK;
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_copy_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy));   
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COPY_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Reversed_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Reversed_Internal.h
new file mode 100644
index 0000000000..a85c353046
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Reversed_Internal.h
@@ -0,0 +1,88 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Copy_Reversed_Internal.h
+ *  @brief Memory header for copy functions.
+ * This header exposes functions that enable secure memory copy function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Copy_Reversed_Internal mcuxClMemory_Copy_Reversed_Internal
+ * @brief This function securely copies a memory region from @p src to @p dst when a secure copy is available.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPY_REVERSED_INTERNAL_H_
+#define MCUXCLMEMORY_COPY_REVERSED_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslDataIntegrity.h>
+#include <mcuxClMemory_Copy_Reversed.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location with security against fault.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pSrc + pDst + length)
+ *  
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_reversed_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_copy_reversed_int
+(
+    uint8_t * pDst,
+    uint8_t const * pSrc,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_int);
+    mcuxClMemory_Status_t retval = MCUXCLMEMORY_STATUS_FAULT;
+
+        MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy_reversed(pDst, pSrc, length, length));
+        MCUX_CSSL_DI_RECORD(identifier /* Not used */, (uint32_t) pSrc + (uint32_t) pDst + length);  // Balance the SC
+        retval = MCUXCLMEMORY_STATUS_OK;
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_copy_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed));
+}
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif  /* MCUXCLMEMORY_COPY_REVERSED_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Internal.h
new file mode 100644
index 0000000000..7610021978
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Internal.h
@@ -0,0 +1,43 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClMemory_Internal.h
+ * @brief Top-level include file for the internal memory operations.
+ */
+
+#ifndef MCUXCLMEMORY_INTERNAL_H
+#define MCUXCLMEMORY_INTERNAL_H
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+
+#include <internal/mcuxClMemory_Clear_Internal.h>
+#include <internal/mcuxClMemory_Compare_Internal.h>
+#include <internal/mcuxClMemory_Copy_Internal.h>
+#include <internal/mcuxClMemory_Set_Internal.h>
+#include <internal/mcuxClMemory_Copy_Reversed_Internal.h>
+#include <internal/mcuxClMemory_CopyWords_Internal.h>
+
+#include <internal/mcuxClMemory_ClearSecure_Internal.h>
+#include <internal/mcuxClMemory_CompareDPASecure_Internal.h>
+#include <internal/mcuxClMemory_CompareSecure_Internal.h>
+#include <internal/mcuxClMemory_CopySecure_Internal.h>
+#include <internal/mcuxClMemory_SetSecure_Internal.h>
+#include <internal/mcuxClMemory_CopySecure_Reversed_Internal.h>
+#include <internal/mcuxClMemory_CopySecurePow2_Internal.h>
+
+#endif /* MCUXCLMEMORY_INTERNAL_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_SetSecure_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_SetSecure_Internal.h
new file mode 100644
index 0000000000..cbf0e4e822
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_SetSecure_Internal.h
@@ -0,0 +1,87 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_SetSecure_Internal.h
+ *  @brief Memory header for set functions.
+ * This header exposes functions that enable secure memory set function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Set_Secure_Internal mcuxClMemory_Set_Secure_Internal
+ * @brief This function sets all bytes in a memory region to a specified value in a secure way 
+ * when a secure set is available.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_SETSECURE_INTERNAL_H_
+#define MCUXCLMEMORY_SETSECURE_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxCsslFlowProtection.h>
+#include <internal/mcuxClMemory_Set_Internal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Sets all bytes of a memory buffer to a specified value.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pDst + length)
+ *  
+ * @param[out]  pDst       pointer to the buffer to be set.
+ * @param[in]   val        byte value to be set.
+ * @param[in]   length     size (in bytes) to be set.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_set_secure_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_set_secure_int
+(
+    uint8_t * pDst,
+    uint8_t val,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_set_secure_int);
+
+        MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxClMemory_set_int(pDst, val, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_set_secure_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set_int));
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_SETSECURE_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Set_Internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Set_Internal.h
new file mode 100644
index 0000000000..68119dc0ea
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Set_Internal.h
@@ -0,0 +1,94 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Set_Internal.h
+ *  @brief Memory header for set function.
+ * This header exposes functions that enable using memory set functions.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Set_Internal mcuxClMemory_Set_Internal
+ * @brief This function sets all bytes in a memory region to a specified value.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_SET_INTERNAL_H_
+#define MCUXCLMEMORY_SET_INTERNAL_H_
+
+#include <mcuxClConfig.h>  // Exported features flags header
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslDataIntegrity.h>
+#include <mcuxCsslMemory.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Sets all bytes of a memory buffer to a specified value.
+ *
+ * The two buffers must not overlap.
+ * 
+ * * Data Integrity: Record(pDst + length)
+ *  
+ * @param[out]  pDst       pointer to the buffer to be set.
+ * @param[in]   val        byte value to be set.
+ * @param[in]   length     size (in bytes) to be set.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCLMEMORY_STATUS_OK                 If @p length bytes copied at @p pDst.
+ * @retval #MCUXCLMEMORY_STATUS_FAULT
+ */
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_set_int)
+static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_set_int
+(
+    uint8_t * pDst,
+    uint8_t val,
+    uint32_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_set_int);
+    mcuxClMemory_Status_t retval = MCUXCLMEMORY_STATUS_FAULT;
+
+        MCUX_CSSL_FP_FUNCTION_CALL(csslRetval, mcuxCsslMemory_Set(
+            mcuxCsslParamIntegrity_Protect(4u, pDst, val, length, length),
+            pDst, val, length, length
+            ));
+        retval = (mcuxClMemory_Status_t) csslRetval ^ (MCUXCSSLMEMORY_COMPONENT_MASK ^ MCUXCLMEMORY_COMPONENT_MASK);
+        MCUX_CSSL_DI_RECORD(identifier /* Not used */, (uint32_t) pDst + length);  // Unbalance the SC
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMemory_set_int, retval, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Set));
+    
+}
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_SET_INTERNAL_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory.h
new file mode 100644
index 0000000000..2ee1703d4c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory.h
@@ -0,0 +1,44 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxClMemory.h
+ * @brief Top-level include file for the memory operations.
+ *
+ * @defgroup mcuxClMemory mcuxClMemory
+ * @brief Basic memory operations
+ *
+ * This component provides memory functions similar to the ones found in the C standard library.
+ *
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_H
+#define MCUXCLMEMORY_H
+
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClMemory_Constants.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClMemory_Endianness.h>
+#include <mcuxClMemory_Clear.h>
+#include <mcuxClMemory_Copy.h>
+#include <mcuxClMemory_Copy_Reversed.h>
+#include <mcuxClMemory_Set.h>
+#include <mcuxClMemory_Xor.h>
+
+/**
+ * @}
+ */
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Clear.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Clear.h
new file mode 100644
index 0000000000..1b0733b60e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Clear.h
@@ -0,0 +1,80 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Clear.h
+ *  @brief Memory header for clear functions.
+ * This header exposes functions that enable using memory clear function.
+ */
+
+
+/**
+ * @defgroup mcuxClMemory_Clear mcuxClMemory_Clear
+ * @brief This function clears a memory region.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+
+#ifndef MCUXCLMEMORY_CLEAR_H_
+#define MCUXCLMEMORY_CLEAR_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Overwrites a memory buffer with null bytes. 
+ * 
+ * If the destination buffer is too small, i.e. if bufLength < length, 
+ * (length-bufLength) is added to the Flow Protection token (see @ref mcuxCsslFlowProtection).
+ * 
+ * @param[out]  pDst        Pointer to the buffer to be cleared.
+ * @param[in]   length      size (in bytes) to be cleared.
+ * @param[in]   bufLength   buffer size (if bufLength < length, only bufLength bytes are cleared).
+ *
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_clear)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_clear (uint8_t *pDst, size_t length, size_t bufLength);
+
+
+/**********************************************
+ * MACROS
+ **********************************************/
+
+/** Helper macro to call #mcuxClMemory_clear with flow protection. */
+#define MCUXCLMEMORY_FP_MEMORY_CLEAR(pTarget, byteLen)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear((uint8_t *) (pTarget), byteLen, byteLen))
+
+/** Helper macro to call #mcuxClMemory_clear with flow protection with buffer. */
+#define MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF(pTarget, byteLen, buffLen)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear((uint8_t *) (pTarget), byteLen, buffLen))
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_CLEAR_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Constants.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Constants.h
new file mode 100644
index 0000000000..a2d0dfa238
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Constants.h
@@ -0,0 +1,57 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Constants.h
+ *  @brief Memory constant header.
+ * This header exposes constants used by the @ref mcuxClMemory functions. */
+
+/**
+ * @defgroup mcuxClMemory_Constants mcuxClMemory_Constants
+ * @brief Defines all constants used by the @ref mcuxClMemory functions.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_CONSTANTS_H
+#define MCUXCLMEMORY_CONSTANTS_H
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+
+#define MCUXCLMEMORY_COMPONENT_MASK              0x09990000u ///< Component mask value
+
+/**
+ * @defgroup MCUXCLMEMORY_STATUS_ MCUXCLMEMORY_STATUS_
+ * @brief Defines valid mcuxClMemory function return codes
+ * @ingroup mcuxClMemory_Types_Macros
+ * @{
+ */
+#define MCUXCLMEMORY_STATUS_OK                   ((mcuxClMemory_Status_t) 0x09992E03u) ///< Memory operation successful
+#define MCUXCLMEMORY_STATUS_EQUAL                ((mcuxClMemory_Status_t) 0x09992E47u) ///< The two contents of the Memory Compare are equal
+#define MCUXCLMEMORY_STATUS_NOT_EQUAL            ((mcuxClMemory_Status_t) 0x099989B8u) ///< The two contents of the Memory Compare are not equal
+#define MCUXCLMEMORY_STATUS_INVALID_PARAMETER    ((mcuxClMemory_Status_t) 0x0999533Cu) ///< A parameter was invalid
+#define MCUXCLMEMORY_STATUS_FAULT                ((mcuxClMemory_Status_t) 0x0999F0F0u) ///< A fault occurred in the execution
+
+/**
+ * @}
+ */
+
+#define MCUXCLMEMORY_ERRORCODE_OK MCUXCLMEMORY_STATUS_OK ///< Memory operation successful
+                                                       ///< @deprecated Please use #MCUXCLMEMORY_STATUS_OK instead
+
+#endif  /* MCUXCLMEMORY_CONSTANTS_H */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy.h
new file mode 100644
index 0000000000..e65fc74daf
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy.h
@@ -0,0 +1,82 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Copy.h
+ *  @brief Memory header for copy functions.
+ * This header exposes functions that enable using memory copy function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Copy mcuxClMemory_Copy
+ * @brief This function copies a memory region from @p src to @p dst.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPY_H_
+#define MCUXCLMEMORY_COPY_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location.
+ *
+ * The two buffers must not overlap.
+ * 
+ * If the destination buffer is too small, i.e. if bufLength < length, 
+ * (length-bufLength) is added to the Flow Protection token (see @ref mcuxCsslFlowProtection).
+ *  
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ * @param[in]  bufLength   buffer size (if bufLength < length, only bufLength bytes are copied).
+ *
+ */
+
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_copy)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength);
+
+
+/**********************************************
+ * MACROS
+ **********************************************/
+
+/** Helper macro to call #mcuxClMemory_copy with flow protection. */
+#define MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, byteLen)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, byteLen))
+
+/** Helper macro to call #mcuxClMemory_copy with flow protection with buffer. */
+#define MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pTarget, pSource, byteLen, buffLen)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, buffLen))
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COPY_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy_Reversed.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy_Reversed.h
new file mode 100644
index 0000000000..bb922b156c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy_Reversed.h
@@ -0,0 +1,74 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Copy_Reversed.h
+ *  @brief Memory header for reversed copy functions.
+ * This header exposes functions that enable using memory reversed copy function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Copy_Reversed mcuxClMemory_Copy_Reversed
+ * @brief This function copies a memory region from @p src to @p dst reversely.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_COPY_REVERSED_H_
+#define MCUXCLMEMORY_COPY_REVERSED_H_
+
+#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Copies a memory buffer to another location reversely.
+ *
+ * If the destination buffer is too small, i.e. if bufLength < length,
+ * then only bufLength bytes are copied reversely.
+ *
+ * @param[out] pDst        pointer to the buffer to be copied to.
+ * @param[in]  pSrc        pointer to the buffer to copy.
+ * @param[in]  length      size (in bytes) to be copied.
+ * @param[in]  bufLength   buffer size (if bufLength < length, only bufLength bytes are copied reversely).
+ *
+ */
+
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_copy_reversed)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy_reversed (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength);
+
+
+/**********************************************
+ * MACROS
+ **********************************************/
+
+/** Helper macro to call #mcuxClMemory_copy_reversed with flow protection. */
+#define MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pTarget, pSource, byteLen)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy_reversed((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, byteLen))
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_COPY_REVERSED_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Endianness.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Endianness.h
new file mode 100644
index 0000000000..b19145d9e0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Endianness.h
@@ -0,0 +1,118 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Endianness.h
+ *  @brief Memory header for endianness support functions.
+ * This header exposes macros that enable using endianness support functions.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Endianness mcuxClMemory_Endianness
+ * @brief These macros implement endianess management on integers
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_ENDIANNESS_H_
+#define MCUXCLMEMORY_ENDIANNESS_H_
+
+#include <mcuxClMemory_Types.h>
+#include <mcuxClConfig.h> // Exported features flags header
+
+
+/**********************************************
+ * MACROS
+ **********************************************/
+
+/**
+ * @brief Converts a 32-bit unsigned integer to a little-endian order @c uint8_t array .
+ *
+ * @note Implementation is platform independent.
+ *
+ * @param[out]      destination     pointer to a 4 byte buffer were 32-bit integer in little-endian will be encoded.
+ * @param[in]       value           pointer to the 32-bit integer to be encoded.
+ *
+ */
+#define mcuxClMemory_StoreLittleEndian32( destination, value )                       \
+do                                                                                  \
+{                                                                                   \
+    uint32_t local_value = (uint32_t)(value);                                       \
+    ((uint8_t*)(destination))[0] = (uint8_t) (((local_value) & 0x000000FFU) >>  0u);\
+    ((uint8_t*)(destination))[1] = (uint8_t) (((local_value) & 0x0000FF00U) >>  8u);\
+    ((uint8_t*)(destination))[2] = (uint8_t) (((local_value) & 0x00FF0000U) >> 16u);\
+    ((uint8_t*)(destination))[3] = (uint8_t) (((local_value) & 0xFF000000U) >> 24u);\
+} while (false)
+
+/**
+ * @brief Converts a 32-bit unsigned integer to a big-endian order @c uint8_t array.
+ *
+ * @note Implementation is platform independent.
+ *
+ * @param[in]       source          pointer to a 4 byte big-endian order @c uint8_t buffer that will be converted to an unsigned integer
+ *
+ */
+#define mcuxClMemory_StoreBigEndian32( destination, value )                          \
+do                                                                                  \
+{                                                                                   \
+    uint32_t local_value = (uint32_t)(value);                                       \
+    ((uint8_t*)(destination))[0] = (uint8_t) (((local_value) & 0xFF000000U) >> 24u);\
+    ((uint8_t*)(destination))[1] = (uint8_t) (((local_value) & 0x00FF0000U) >> 16u);\
+    ((uint8_t*)(destination))[2] = (uint8_t) (((local_value) & 0x0000FF00U) >>  8u);\
+    ((uint8_t*)(destination))[3] = (uint8_t) (((local_value) & 0x000000FFU) >>  0u);\
+} while (false)
+
+/**
+ * @brief Converts a little-endian order @c uint8_t array to a 32-bit unsigned integer.
+ *
+ * @note Implementation is platform independent.
+ *
+ * @param[in]       source          pointer to a 4 byte little-endian order @c uint8_t buffer that will be converted to an unsigned integer
+ *
+ */
+#define mcuxClMemory_LoadLittleEndian32( source )        \
+    ( (((uint32_t) ((const uint8_t*)(source))[0]) <<  0u) |   \
+      (((uint32_t) ((const uint8_t*)(source))[1]) <<  8u) |   \
+      (((uint32_t) ((const uint8_t*)(source))[2]) << 16u) |   \
+      (((uint32_t) ((const uint8_t*)(source))[3]) << 24u) )
+
+
+/**
+ * @brief Converts a big-endian order @c uint8_t array to a 32-bit unsigned integer.
+ *
+ * @param[in]       destination     pointer to a 4 byte buffer were 32-bit integer in big-endian will be decoded.
+ *
+ * @return a 32-bit unsigned integer
+ */
+#define mcuxClMemory_LoadBigEndian32( source )           \
+    ( (((uint32_t) ((const uint8_t*)(source))[0]) << 24u) |   \
+      (((uint32_t) ((const uint8_t*)(source))[1]) << 16u) |   \
+      (((uint32_t) ((const uint8_t*)(source))[2]) <<  8u) |   \
+      (((uint32_t) ((const uint8_t*)(source))[3]) <<  0u) )
+
+/**
+ * @brief MACRO that switches byte endianness of given CPU word.
+ *
+ * @param[in]       input           a 32-bit unsigned integer whose endianness will be reversed.
+ *
+ */
+
+#ifdef __REV
+#define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input)  __REV(input)
+#else
+#define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input)  ((((input) & 0xffu) << 24u) | (((input) & 0xff00u) << 8u) | (((input) & 0xff0000u) >> 8u) | (((input) & 0xff000000u) >> 24u))
+#endif
+
+#endif /* MCUXCLMEMORY_ENDIANNESS_H_ */
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Set.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Set.h
new file mode 100644
index 0000000000..f165c5df17
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Set.h
@@ -0,0 +1,77 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Set.h
+ *  @brief Memory header for set function.
+ * This header exposes functions that enable using memory set functions.
+ */
+
+/**
+ * @defgroup mcuxClMemory_Set mcuxClMemory_Set
+ * @brief This function sets all bytes in a memory region to a specified value.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_SET_H_
+#define MCUXCLMEMORY_SET_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+/**
+ * Sets all bytes of a memory buffer to a specified value.
+ * 
+ * If the destination buffer is too small, i.e. if bufLength < length, 
+ * (length-bufLength) is added to the Flow Protection token (see @ref mcuxCsslFlowProtection).
+ *  
+ * @param[out]  pDst       pointer to the buffer to be set.
+ * @param[in]   val        byte value to be set.
+ * @param[in]   length     size (in bytes) to be set.
+ * @param[in]   bufLength  buffer size (if bufLength < length, only bufLength bytes are set).
+ *
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_set)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_set (uint8_t *pDst, uint8_t val, size_t length, size_t bufLength);
+
+/**********************************************
+ * MACROS
+ **********************************************/
+
+/** Helper macro to call #mcuxClMemory_set with flow protection. */
+#define MCUXCLMEMORY_FP_MEMORY_SET(pTarget, val, byteLen)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set((uint8_t *) (pTarget), val, byteLen, byteLen))
+
+/** Helper macro to call #mcuxClMemory_set with flow protection with buffer. */
+#define MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pTarget, val, byteLen, buffLen)  \
+        MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set((uint8_t *) (pTarget), val, byteLen, buffLen))
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_SET_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Types.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Types.h
new file mode 100644
index 0000000000..69c0a3ec68
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Types.h
@@ -0,0 +1,68 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Types.h
+ *  @brief Memory type header.
+ * This header exposes types used by the @ref mcuxClMemory functions. */
+
+/**
+ * @defgroup mcuxClMemory_Types mcuxClMemory_Types
+ * @brief Defines all types used by the @ref mcuxClMemory functions.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_TYPES_H
+#define MCUXCLMEMORY_TYPES_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mcuxClConfig.h> // Exported features flags header
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+/**********************************************
+ * MACROS
+ **********************************************/
+/**
+ * @defgroup mcuxClMemory_Types_Macros mcuxClMemory_Types_Macros
+ * @brief Defines all macros of @ref mcuxClMemory_Types
+ * @ingroup mcuxClMemory_Types
+ * @{
+ */
+#define MCUXCLMEMORY_API extern  ///< Marks a function as a public API function of the mcuxClMemory component
+
+/**
+ * @}
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+/**
+ * @brief Type for error codes of mcuxClMemory component functions.
+ * 
+ * Type returned by mcuxClMemory functions. See @ref MCUXCLMEMORY_STATUS_ for possible options.
+ */
+typedef uint32_t mcuxClMemory_Status_t;
+
+/**
+ * @brief Deprecated type for error codes used by code-flow protected mcuxClMemory component functions.
+ */
+typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_Status_Protected_t;
+
+#endif /* #MCUXCLMEMORY_TYPES_H */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Xor.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Xor.h
new file mode 100644
index 0000000000..7a6218383a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Xor.h
@@ -0,0 +1,81 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023-2024 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  mcuxClMemory_Xor.h
+ *  @brief Memory header for xor functions.
+ * This header exposes functions that enable using memory xor function.
+ */
+
+/**
+ * @defgroup mcuxClMemory_xor mcuxClMemory_xor
+ * @brief This function performs xor between @p src1 and @p src2, and saves result to @p dst.
+ * @ingroup mcuxClMemory
+ * @{
+ */
+
+#ifndef MCUXCLMEMORY_XOR_H_
+#define MCUXCLMEMORY_XOR_H_
+
+#include <mcuxClConfig.h> // Exported features flags header
+
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**********************************************
+ * FUNCTIONS
+ **********************************************/
+
+/**
+ * Perform xor for 2 memory buffers.
+ *
+ * Operation in place is allowed - one of the input buffer can also be the output buffer.
+ *
+ *
+ * @param[out] pDst        pointer to the destination buffer.
+ * @param[in]  pSrc1       pointer to the first source buffer.
+ * @param[in]  pSrc2       pointer to the second source buffer.
+ * @param[in]  length      size (in bytes) to be operated
+ * @param[in]  bufLength   buffer size (if bufLength < length, only bufLength bytes are operated).
+ *
+ */
+
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_xor)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_xor(uint8_t *pDst, const uint8_t *pSrc1, const uint8_t *pSrc2, uint32_t length, size_t bufLength);
+
+
+/**********************************************
+ * MACROS
+ **********************************************/
+
+/** Helper macro to call #mcuxClMemory_xor with flow protection. */
+#define MCUXCLMEMORY_FP_MEMORY_XOR(pDst, pSrc1, pSrc2, length)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_xor(pDst, pSrc1, pSrc2, length, length))
+
+/** Helper macro to call #mcuxClMemory_xor with flow protection with buffer. */
+#define MCUXCLMEMORY_FP_MEMORY_XOR_WITH_BUFF(pDst, pSrc1, pSrc2, length, bufLen)  \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_xor(pDst, pSrc1, pSrc2, length, bufLen))
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* MCUXCLMEMORY_XOR_H_ */
+
+/**
+ * @}
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/src/mcuxClMemory.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/src/mcuxClMemory.c
new file mode 100644
index 0000000000..f09cf37254
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxClMemory/src/mcuxClMemory.c
@@ -0,0 +1,452 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021, 2023-2024 NXP                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#include <mcuxClMemory.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClToolchain.h>
+#include <mcuxCsslAnalysis.h>
+
+
+#define WORDSIZE  (sizeof(uint32_t))
+
+
+/**
+ * [DESIGN]
+ *
+ * This function considers the following cases of alignment of source and
+ * destination addresses and length:
+ *
+ *  Src Addr. | Des Addr. | Length    |
+ *  ----------+-----------+-----------+-------------------------------
+ *  aligned   | aligned   | aligned   | Case A: read word, write word
+ *  ----------+-----------+-----------+-------------------------------
+ *  aligned   | unaligned | aligned   | Case B: read word, write byte
+ *  ----------+-----------+-----------+-------------------------------
+ *  unaligned | aligned   | aligned   | Case C: read byte, write word
+ *  ----------+-----------+-----------+-------------------------------
+ *  unaligned | unaligned | aligned   | Case D: read byte,
+ *  any       | any       | unaligned |         write byte-word-byte
+ *
+ * Since SFR address and length shall be aligned,
+ * Cases A and B cover the usecases of SFR reading; and
+ * Cases A and C cover the useceses of SFR writing.
+ *
+ * If length > bufLength, and bufLength is not aligned, in cases A and B,
+ * the word containing last byte(s) is read in word, and last byte(s) is written byte-wisely.
+ * Ps, since length is aligned, last word in source shall be in valid address range.
+ *
+ * Case C is a special case of Case D, because the byte-wisely writing will be ignored.
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
+{
+    /* This function assumes caller providing valid addresses and length. */
+
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy);
+    MCUX_CSSL_FP_LOOP_DECL(mcuxClMemory_copy_loop);
+
+    uint8_t *pDstX = pDst;
+    const uint8_t *pSrcX = pSrc;
+    uint32_t copiedLength = 0u;
+
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("casting pointer to integer to check alignment.");
+    const uint32_t srcAddress = (uint32_t) pSrc;
+    const uint32_t dstAddress = (uint32_t) pDst;
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER();
+
+    const uint32_t srcAddrOrLength = srcAddress | length;
+    if (0u == (srcAddrOrLength % WORDSIZE))  /* source address and length are both aligned. */
+    {
+        uint32_t temp = 0u;
+
+        if (0u == (dstAddress % WORDSIZE))   /* destination address is aligned. */
+        {
+            /* Case A: copy word-wisely. */
+            while (((copiedLength + WORDSIZE) <= length) && ((copiedLength + WORDSIZE) <= bufLength))
+            {
+                MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+                MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller shall provide valid buffer pSrc[] of length.")
+                MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("source pointer is aligned in Case A.")
+                temp = *(const uint32_t *) pSrcX;
+                MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING()
+                pSrcX += WORDSIZE;
+                MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+
+                MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+                copiedLength += WORDSIZE;
+
+                MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+                MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller shall provide valid buffer pDst[] of bufLength.")
+                MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("destination pointer is aligned in Case A.")
+                *(uint32_t *) pDstX = temp;
+                MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING()
+                pDstX += WORDSIZE;
+                MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+
+                MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+            }
+        }
+
+        /* Case A: remaining byte(s) when (length < bufLength). */
+        /* Case B: read word-wisely, write byte-wisely. */
+        while ((copiedLength < length) && (copiedLength < bufLength))
+        {
+            if (0u == (copiedLength % WORDSIZE))
+            {
+                MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller shall provide valid buffer pSrc[] of length.")
+                MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("source pointer is aligned in Cases A and B.")
+                temp = *(const uint32_t *) pSrcX;
+                MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING()
+                pSrcX += WORDSIZE;
+                MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+            }
+            else
+            {
+                temp >>= 8u;
+            }
+
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+            MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller shall provide valid buffer pDst[] of bufLength.")
+            *pDstX = (uint8_t) (temp & 0xFFu);
+            pDstX++;
+            MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+
+            copiedLength++;
+        }
+
+    }
+    else
+    {
+        /* Cases C & D: read byte-wisely, write (byte-word-byte)-wisely. */
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("modular arithmetic, mod 4")
+        const uint32_t unalignedBytes = (0u - dstAddress) % WORDSIZE;
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+
+        // Loop on unaligned bytes if any.
+        // Loop on words
+        // Start at first aligned address, increment by 4 bytes. To understand the loop condition, consider without loss of generality a
+        // byte array b_i of length=4 and bufLength=4.
+        //
+        // |0                             3|4     4|
+        // +-------+-------+-------+-------+-------+
+        // |  b_0  |  b_1  |  b_2  |  b_3  |       |
+        // +-------+-------+-------+-------+-------+
+        //
+        // In order to determine whether a full word can be copied, check with regard to the copying position i:
+        // * Starting from i=0, a full word can be copied. i+4 is the first position that is outside of the valid range,
+        //   and it is equal to length.
+        // Therefore, checking that i+4 <= length and i+4 <= bufLength is a valid condition to check whether a full word can be
+        // copied.
+        // Loop on remaining bytes.
+
+        //copy unaligned bytes first, if any
+        for (; (copiedLength < length) && (copiedLength < bufLength) && (copiedLength < unalignedBytes); copiedLength++)
+        {
+            MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller shall provide valid buffers pSrc[] of length and pDst[] of bufLength.")
+            *pDstX = *pSrcX;
+            pDstX++;
+            pSrcX++;
+            MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+        }
+
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("The pointer is CPU word aligned after the byte-loop above.");
+        uint32_t* p32Dst = (uint32_t *) pDstX;
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING();
+
+        //loop on words
+        for (; ((copiedLength + WORDSIZE) <= length) && ((copiedLength + WORDSIZE) <= bufLength); copiedLength += WORDSIZE)
+        {
+            /* Volatile keyword is added to avoid any chance of optimization (i.e. full word read) */
+            /* The idea is to read byte-wise from SRC to avoid unaligned word reads, but write aligned and word-wise to DST */
+            MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller shall provide valid buffers pSrc[] of length and pDst[] of bufLength.")
+            uint32_t crtWordVal = (uint32_t)*(volatile const uint8_t *)pSrcX;
+            pSrcX++;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+            crtWordVal |= (uint32_t)*(volatile const uint8_t *)pSrcX << 8u;
+            pSrcX++;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+            crtWordVal |= (uint32_t)*(volatile const uint8_t *)pSrcX << 16u;
+            pSrcX++;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+            crtWordVal |= (uint32_t)*(volatile const uint8_t *)pSrcX << 24u;
+            pSrcX++;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+            MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_INCOMPATIBLE("The pointer is CPU word aligned after the byte-loop above.");
+            *p32Dst = crtWordVal;
+            p32Dst++;
+            MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_INCOMPATIBLE();
+            MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+        }
+
+        pDstX = (uint8_t *) p32Dst;
+        //loop on remaining bytes
+        for (; (copiedLength < length) && (copiedLength < bufLength); copiedLength++)
+        {
+            MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller shall provide valid buffers pSrc[] of length and pDst[] of bufLength.")
+            *pDstX = *pSrcX;
+            pDstX++;
+            pSrcX++;
+            MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop);
+        }
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_copy,
+        ((length <= bufLength) ? length : bufLength) - copiedLength,
+        MCUX_CSSL_FP_LOOP_ITERATIONS(mcuxClMemory_copy_loop,
+                                    ((length <= bufLength) ? length : bufLength)) );
+}
+
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_reversed)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy_reversed (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_reversed);
+    uint32_t len = length;
+    uint32_t diff;
+
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("diff is non-negative distance between pSrc and pDst, caculated according to platform architecture.")
+    if (pDst > pSrc)
+    {
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Casting pSrc and pDst to unsigned integer to calculate difference");
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_MODIFY_STRING_LITERALS("False positive: The constant string literal pSrc is not being modified");
+        diff = (uint32_t)pDst - (uint32_t)pSrc;
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MODIFY_STRING_LITERALS();
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER();
+    }
+    else
+    {
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Casting pSrc and pDst to unsigned integer to calculate difference");
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_MODIFY_STRING_LITERALS("False positive: The constant string literal pSrc is not being modified");
+        diff = (uint32_t)pSrc - (uint32_t)pDst;
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MODIFY_STRING_LITERALS();
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER();
+    }
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+
+    if (bufLength < length)
+    {
+        length = bufLength;
+        len = bufLength;
+    }
+
+    MCUX_CSSL_FP_LOOP_DECL(mcuxClMemory_copy_reversed_loop);
+
+    //non-overlap case
+    if (diff >= length)
+    {
+        diff = length;
+    }
+
+    uint8_t *pDstBt;
+    const uint8_t *pSrcBt;
+    if (pSrc > pDst)
+    {
+        // first copy the non-overlop part
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt will be in the valid range pDst[0 ~ bufLength] and pSrc will be in the valid range pSrc[0 ~ length].")
+        pSrcBt = pSrc + len - 1U;
+        pDstBt = (uint8_t *)pDst;
+
+        while (len > length - diff)
+        {
+            *pDstBt = *pSrcBt;
+            pDstBt++;
+            pSrcBt--;
+            len--;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop);
+        }
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+        //then swap the overlap part
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt2 will be in the valid range pDst[0 ~ bufLength].")
+        uint8_t *pDstBt2 = pDstBt + len - 1u;
+        while (len > 1U)
+        {
+            uint8_t tempByte = *pDstBt2;
+            *pDstBt2 = *pDstBt;
+            pDstBt2--;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop);
+            *pDstBt = tempByte;
+            pDstBt++;
+            len -= 2U;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop);
+        }
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+    }
+    else
+    {
+        // first copy the non-overlop part
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt will be in the valid range pDst[0 ~ bufLength].")
+        pDstBt = (uint8_t *)pDst + len - 1U;
+        pSrcBt = pSrc;
+
+        while (len > length - diff)
+        {
+            *pDstBt = *pSrcBt;
+            pDstBt--;
+            pSrcBt++;
+            len--;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop);
+        }
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+        //then swap the overlap part
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt2 will be in the valid range pDst[0 ~ bufLength], pDstBt will be in the valid range pDst[0 ~ bufLength].")
+        uint8_t *pDstBt2 = pDstBt - len + 1u;
+        while (len > 1U)
+        {
+            uint8_t tempByte = *pDstBt2;
+            *pDstBt2 = *pDstBt;
+            pDstBt2++;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop);
+            *pDstBt = tempByte;
+            pDstBt--;
+            len -= 2U;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop);
+        }
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+    }
+
+    /* update SC and return */
+    MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_copy_reversed,
+                              MCUX_CSSL_FP_LOOP_ITERATIONS(mcuxClMemory_copy_reversed_loop, (length - len)));
+}
+
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_set)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_set (uint8_t *pDst, uint8_t val, size_t length, size_t bufLength)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_set);
+
+    MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "modular arithmetic, mod 4")
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("casting to unsigned integer to calculate unaligned bytes");
+    uint32_t unalignedBytes = (0u - (uint32_t)pDst) % (sizeof(uint32_t));
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER();
+    MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    MCUX_CSSL_FP_LOOP_DECL(mcuxClMemory_set_loop);
+    uint32_t wordVal = ((uint32_t)val << 24) | ((uint32_t)val << 16) | ((uint32_t)val << 8) | (uint32_t)val;
+
+    //clear unaligned bytes first, if any
+    size_t i = 0u;
+    for(i = 0u; (i < length) && (i < bufLength) && (i < unalignedBytes); i++)
+    {
+        MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ bufLength].")
+        *pDst = val;
+        pDst++;
+        MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop);
+        MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    }
+
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("The pointer is CPU word aligned. So, it's safe to cast it to uint32_t*");
+    uint32_t* p32Dst = (uint32_t *) pDst;
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING();
+
+    //loop on words. See mcuxClMemory_copy for an explanation of the condition
+    while(((i + sizeof(uint32_t)) <= length) && ((i + sizeof(uint32_t)) <= bufLength))
+    {
+        MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p32Dst will be in the valid range pDst[0 ~ bufLength] and pSrc will be in the valid range pSrc[0 ~ length].")
+        MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop);
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_INCOMPATIBLE("This assignment never overflows because the pointer p32Dst points to pDst[i] where i <= length - 4");
+        *p32Dst = wordVal;
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_INCOMPATIBLE();
+        MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop);
+        p32Dst++;
+        MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop);
+        i += sizeof(uint32_t);
+        MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop);
+        MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    }
+
+    pDst = (uint8_t *) p32Dst;
+    //loop on remaining bytes
+    for(; (i < length) && (i < bufLength); i++)
+    {
+        MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ bufLength].")
+        *pDst = val;
+        pDst++;
+        MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop);
+        MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_set,
+                              ((length <= bufLength) ? length : bufLength) - i,
+                              MCUX_CSSL_FP_LOOP_ITERATIONS(mcuxClMemory_set_loop,
+                                                          ((length <= bufLength) ? length : bufLength)));
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_clear)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_clear (uint8_t *pDst, size_t length, size_t bufLength)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_clear, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set));
+
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set(pDst, 0U, length, bufLength));
+
+    MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_clear);
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_xor)
+MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_xor(uint8_t *pDst, const uint8_t *pSrc1, const uint8_t *pSrc2, uint32_t length, size_t bufLength)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_xor);
+    uint32_t remainingLen = length;
+
+    if (bufLength < remainingLen)
+    {
+        remainingLen = bufLength;
+    }
+
+    MCUX_CSSL_FP_LOOP_DECL(mcuxClMemory_xor_loop);
+
+    /* xor by word if aligned */
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_TO_VOIDPTR("Typecasting  pointer to integer is intentional")
+    if ((remainingLen >= WORDSIZE) && (0u == ((uint32_t)pDst & (WORDSIZE - 1u)))
+                && (0u == ((uint32_t)pSrc1 & (WORDSIZE - 1u)))
+                && (0u == ((uint32_t)pSrc2 & (WORDSIZE - 1u))))
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_TO_VOIDPTR()
+    {
+        do
+        {
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_xor_loop);
+            MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("pSrc1, pSrc2 and pDst are word aligned.")
+            const uint32_t temp1 = *(const uint32_t *)pSrc1;
+            const uint32_t temp2 = *(const uint32_t *)pSrc2;
+            *(uint32_t *)pDst = temp1 ^ temp2;
+            MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY()
+
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_xor_loop);
+            pSrc1 += WORDSIZE;
+            pSrc2 += WORDSIZE;
+            pDst += WORDSIZE;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_xor_loop);
+            remainingLen -= WORDSIZE;
+            MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_xor_loop);
+        } while (remainingLen >= WORDSIZE);
+    }
+
+    /* xor the remaining bytes */
+    while (remainingLen > 0u)
+    {
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Caller should set length and bufLength properly to make sure not to overflow.")
+        const uint8_t temp1 = *pSrc1++;
+        const uint8_t temp2 = *pSrc2++;
+        *pDst++ = temp1 ^ temp2;
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+        remainingLen--;
+        MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_xor_loop);
+    }
+
+    MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_xor,
+                              MCUX_CSSL_FP_LOOP_ITERATIONS(mcuxClMemory_xor_loop,
+                                                          ((length <= bufLength) ? length : bufLength)));
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslAnalysis.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslAnalysis.h
new file mode 100644
index 0000000000..f2b5a11b32
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslAnalysis.h
@@ -0,0 +1,694 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2024 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#ifndef MCUX_CSSL_ANALYSIS_H_
+#define MCUX_CSSL_ANALYSIS_H_
+
+#define MCUX_CSSL_ANALYSIS_STR(a) #a
+#define MCUX_CSSL_ANALYSIS_EMPTY()
+#define MCUX_CSSL_ANALYSIS_DEFER(id) id MCUX_CSSL_ANALYSIS_EMPTY()
+#define MCUX_CSSL_ANALYSIS_EXPAND(...) __VA_ARGS__
+
+#define MCUX_CSSL_ANALYSIS_PRAGMA(x) _Pragma(#x)
+
+/* Compiler defines TODO: decide proper placement for those */
+#if defined ( __CC_ARM )
+/* Arm Compiler 4/5 */
+#define MCUX_CSSL_COMPILER_ARMCC
+#define MCUX_CSSL_COMPILER_ARM_COMPILER
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+/* Arm Compiler 6.6 LTM (armclang) */
+#define MCUX_CSSL_COMPILER_ARMCLANG_LTM
+#define MCUX_CSSL_COMPILER_ARM_COMPILER
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+/* Arm Compiler above 6.10.1 (armclang) */
+#define MCUX_CSSL_COMPILER_ARMCLANG
+#define MCUX_CSSL_COMPILER_ARM_COMPILER
+
+#elif defined (_clang_)
+#define MCUX_CSSL_COMPILER_ARM_COMPILER /* i.e. Version 6.01 build 0019  */
+#endif // defined ( __CC_ARM )
+
+/* Example of common patterns, with either just predefined rationale, or a combination of discards. */
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_READ() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE("Read from a HW peripheral")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_HW_READ() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_WRITE() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE("Write to a HW peripheral")
+  /*MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_TO_OBJECT("Write to a HW peripheral")*/
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_HW_WRITE() \
+  /*MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_TO_OBJECT()*/ \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE()
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONVERSION_BETWEEN_ENUM_AND_INTEGER_TYPES(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_5, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONVERSION_BETWEEN_ENUM_AND_INTEGER_TYPES() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_5)
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_API_DECLARATIONS() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user, it is declared but never referenced. ")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_API_DECLARATIONS() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_AMBIGUOUS_IDENTIFIER("Identifiers longer than 31 characters are allowed for more descriptive naming")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_AMBIGUOUS_IDENTIFIER()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("explicit pointer casts reinterpreting opaque types of workarea-like buffer objects are allowed.")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY()
+/* Rule 11.3: applies to casts between ctx structs
+* e.g. cast from Aead_Context_t to more specific type AeadModes_Context_t
+*/
+#define MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Cast to a more specific type is allowed")
+#define MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_HEADER() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_C11_EXTENSION("External header outside our control") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNDEFINED_VALUE("External header outside our control") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_MACRO_IDENTIFIER("External header outside our control") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY("External header outside our control")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_HEADER() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_MACRO_IDENTIFIER() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNDEFINED_VALUE() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_C11_EXTENSION()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_MACRO() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT("External macro outside our control, operation is safe on target platform given correct arguments according to an API are provided") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_OPERATIONS_ON_INAPPROPRIATE_TYPE("External macro outside our control, operation is safe on target platform given correct arguments according to an API are provided") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONVERSIONS_WITH_INAPPROPRIATE_TYPE("External macro outside our control, operation is safe on target platform given correct arguments according to an API are provided") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_EXPLICIT_PARANTHESIS("External macro outside our control, operation is safe on target platform given correct arguments according to an API are provided") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_INVALID_WIDTH_IN_SHIFT_OPERATIONS("External macro outside our control, operation is safe on target platform given correct arguments according to an API are provided")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_MACRO() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_OPERATIONS_ON_INAPPROPRIATE_TYPE() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONVERSIONS_WITH_INAPPROPRIATE_TYPE() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_EXPLICIT_PARANTHESIS() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INVALID_WIDTH_IN_SHIFT_OPERATIONS()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_OBJ_SIZES() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNUSED_VARIABLE("Variables used to determine object sizes") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION("Variables used to determine object sizes")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_OBJ_SIZES() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNUSED_VARIABLE()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_FUP() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION("External declarations are generated by the FUP processing tool") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_5_8, "The FUP processing tool generates a second declaration")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_FUP() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_5_8) \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_FUP_PROGRAM() \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_LINKAGE_FUP() \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_DEFINITION_IN_TEMP_FILE_FUP()
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_FUP_PROGRAM() \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_DEFINITION_IN_TEMP_FILE_FUP() \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_LINKAGE_FUP()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_LINKAGE_FUP() \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_5_8, "The FUP processing tool generates a second external declaration")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_LINKAGE_FUP() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_5_8) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() 
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_DEFINITION_IN_TEMP_FILE_FUP() \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_8_6, "The FUP processing tool generates definitions in temporary build files")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DEFINITION_IN_TEMP_FILE_FUP() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_8_6)
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Integer overflows are allowed/expected for security counter variables per design")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_SWITCH_STATEMENT_RETURN_TERMINATION() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED("Return instead of break statement as terminator is allowed")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SWITCH_STATEMENT_RETURN_TERMINATION() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_INVARIANT_EXPRESSION_WORKAREA_CALCULATIONS() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT("Invariant expression is allowed in workarea calculation macros")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_INVARIANT_EXPRESSION_WORKAREA_CALCULATIONS() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_ESCAPING_LOCAL_ADDRESS("Address in SFR is for internal use only and does not escape")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ESCAPING_LOCAL_ADDRESS()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_DI_INTEGER_OVERFLOW() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Integer overflows are allowed/expected for DI variables per design")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DI_INTEGER_OVERFLOW() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_DI_CAST_POINTERS() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Typecast pointer to integer for DI record/expunge")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DI_CAST_POINTERS() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_SC_CAST_POINTERS() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Typecast pointer (void *) to integer for SC add/sub")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_CAST_POINTERS() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_EXAMPLE_FUNCTION() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_FUNCTION_DECLARATION("Declaration is not needed for release package. Cant be static as it is declared and used by testing framweork.") \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER()
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXAMPLE_FUNCTION() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_FUNCTION_DECLARATION() \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER()
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_VOID() \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_5, "Typecast pointer (void *) for correct representation to use pointer")
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_VOID() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_5)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_EXPLICIT_PARANTHESIS(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_12_1, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_EXPLICIT_PARANTHESIS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_12_1)
+
+#ifdef MCUX_CSSL_COMPILER_ARM_COMPILER
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_SIGNED_TRUNCATION() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_MAY_RESULT_IN_MISINTERPRETED_DATA("Truncated upper bits are not needed. Operation is implementation defined and documented in arm compiler user guide. If a value of integral type is truncated to a shorter signed integral type, the result is obtained by discarding an appropriate number of most significant bits. If the original number is too large, positive or negative, for the new type, there is no guarantee that the sign of the result is going to be the same as the original. On target ARM architecture two's complement representation is used and a sign will be derived from most significant bit of data remaining after truncation. This operation allows efficient implementation of signed numbers modular arithmetic.")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SIGNED_TRUNCATION() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_MAY_RESULT_IN_MISINTERPRETED_DATA()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_SIGNED_SHIFT() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_OPERATIONS_ON_INAPPROPRIATE_TYPE("Shift operation on signed numbers is implementation defined and documented in arm compiler user guide. Right shifts on signed quantities are arithmetic (sign extension is performed). Left shifs are logical. This operation allows sign extensions and efficient implementation of signed numbers arithmetic.") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_SIGNED_SHIFT_AMOUNT("Shift operation on signed numbers is implementation defined and documented in arm compiler user guide. Right shifts on signed quantities are arithmetic (sign extension is performed). Left shifs are logical. This operation allows sign extensions and efficient implementation of signed numbers arithmetic.")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SIGNED_SHIFT() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_OPERATIONS_ON_INAPPROPRIATE_TYPE() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SIGNED_SHIFT_AMOUNT()
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_TWOS_COMPLEMENT_REPRESENTATION() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_MAY_RESULT_IN_MISINTERPRETED_DATA("Algoritihm works correctly assuming two's complement representation of signed numbers. This is true for target ARM platform.")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_TWOS_COMPLEMENT_REPRESENTATION() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_MAY_RESULT_IN_MISINTERPRETED_DATA()
+
+#else //defined(MCUX_CSSL_COMPILER_ARM_COMPILER)
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_SIGNED_TRUNCATION() \
+  /* Intentionally empty */
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SIGNED_TRUNCATION() \
+  /* Intentionally empty */
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_SIGNED_SHIFT() \
+  /* Intentionally empty */
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SIGNED_SHIFT() \
+  /* Intentionally empty */
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_TWOS_COMPLEMENT_REPRESENTATION() \
+  /* Intentionally empty */
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_TWOS_COMPLEMENT_REPRESENTATION() \
+  /* Intentionally empty */
+#endif
+
+#define MCUX_CSSL_ANALYSIS_ASSERT_PARAMETER(value, min_value, max_value, return_code) \
+  MCUX_CSSL_ANALYSIS_COVERITY_ASSERT(value, min_value, max_value, return_code)
+
+#define MCUX_CSSL_ANALYSIS_ASSERT_PARAMETER_WITH_DATA_TYPE(value,data_type, min_value, max_value, return_code) \
+  MCUX_CSSL_ANALYSIS_COVERITY_ASSERT_WITH_DATA_TYPE(value, data_type, min_value, max_value, return_code)
+
+/* Example of basic violation suppression */
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DEAD_CODE(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_1, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DEAD_CODE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_1)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNUSED_MACRO(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNUSED_MACRO() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_3_1, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_3_1)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP36_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP36_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_MAY_RESULT_IN_MISINTERPRETED_DATA(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT02_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT31_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT00_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_MAY_RESULT_IN_MISINTERPRETED_DATA() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT02_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT31_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT00_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wcast-qual, rationale) \
+  MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(1836, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8) \
+  MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(1836) \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wcast-qual)
+
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_REGISTER_INDEXING() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_OUT_OF_BOUNDS_ACCESS("Apply an index to the base address of a HW peripheral to access the correct SFR-word. The caller is responsible for ensuring that the index is valid.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(ARRAY_VS_SINGLETON, "Apply an index to the base address of a HW peripheral to access the correct SFR-word. The caller is responsible for ensuring that the index is valid.")
+#define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_REGISTER_INDEXING_WITH_OFFSETOF() \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_OUT_OF_BOUNDS_ACCESS("Apply an index to the base address of a HW peripheral, where index was computed with 'offsetof' macro to ensure a correct offset.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(ARRAY_VS_SINGLETON, "Apply an index to the base address of a HW peripheral, where index was computed with 'offsetof' macro to ensure a correct offset.")
+#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_HW_REGISTER_INDEXING() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(ARRAY_VS_SINGLETON) \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_OUT_OF_BOUNDS_ACCESS()
+
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_OUT_OF_BOUNDS_ACCESS(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_18_1, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_OUT_OF_BOUNDS_ACCESS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_18_1) \
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST(rationale) \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER(rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER()
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wcast-qual, rationale) \
+  MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(1836, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP05_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP05_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8) \
+  MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(1836) \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wcast-qual)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_9, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_9)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_ARRAY_OUT_OF_BOUNDS(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_ARR30_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ARRAY_OUT_OF_BOUNDS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_ARR30_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_4, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_6, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT36_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_MSC15_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_MSC15_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT36_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_6) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_4)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER(rationale) \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER(rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER()
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_AMBIGUOUS_IDENTIFIER(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_5_1, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_5_4, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_5_5, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_AMBIGUOUS_IDENTIFIER() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_5_5) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_5_4) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_5_1)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_STRUCT(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_1, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_STRUCT() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_1)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_DEFINED(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_8_6, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_DEFINED() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_8_6)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DEFINED_MORE_THAN_ONCE(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_8_5, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DEFINED_MORE_THAN_ONCE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_8_5)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_2, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_2)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(INTEGER_OVERFLOW, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT30_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT32_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT08_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_12_4, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_12_4) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT08_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT32_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT30_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(INTEGER_OVERFLOW)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_WRAP(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT30_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT08_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_WRAP() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT08_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT30_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_INCOMPATIBLE(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_INCOMPATIBLE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DEREFERENCE_NULL_POINTER(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP34_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(FORWARD_NULL, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DEREFERENCE_NULL_POINTER() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(FORWARD_NULL) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP34_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_1, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_3, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_6, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_1) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_3) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_6)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_ESCAPING_LOCAL_ADDRESS(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_18_6, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ESCAPING_LOCAL_ADDRESS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_18_6)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4, "Conditional expression does have a boolean type.")
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_C11_EXTENSION(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wc11-extensions, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_C11_EXTENSION() \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wc11-extensions)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNDEFINED_VALUE(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wundef, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNDEFINED_VALUE() \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wundef)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_IDENTIFIER(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wreserved-identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_IDENTIFIER() \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wreserved-identifier)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_MACRO_IDENTIFIER(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wreserved-macro-identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_MACRO_IDENTIFIER() \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wreserved-macro-identifier)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_FUNCTION_DECLARATION(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_8_4, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_FUNCTION_DECLARATION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_8_4)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wmissing-variable-declarations, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_8_4, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_8_4) \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wmissing-variable-declarations)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_OF_COMPOSITE_EXPRESSION(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_8, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_OF_COMPOSITE_EXPRESSION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_8)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNUSED_VARIABLE(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wunused-variable, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNUSED_VARIABLE() \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wunused-variable)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY(rationale) \
+  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wpadded, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY() \
+  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wpadded)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS(rationale) \
+  MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(-Warray-bounds, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS() \
+  MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(-Warray-bounds)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TAINTED_EXPRESSION(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Directive_4_14, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(TAINTED_SCALAR, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TAINTED_EXPRESSION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Directive_4_14) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(TAINTED_SCALAR)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_INVALID_WIDTH_IN_SHIFT_OPERATIONS(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Directive_12_2, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INVALID_WIDTH_IN_SHIFT_OPERATIONS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Directive_12_2)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONVERSIONS_WITH_INAPPROPRIATE_TYPE(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_4, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONVERSIONS_WITH_INAPPROPRIATE_TYPE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_4)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_OPERATIONS_ON_INAPPROPRIATE_TYPE(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_1, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_OPERATIONS_ON_INAPPROPRIATE_TYPE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_1)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_FLEXIBLE_ARRAY(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_18_7, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_FLEXIBLE_ARRAY() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_18_7)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_ASSIGNING_COMPOSITE_EXPRESSION(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_6, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ASSIGNING_COMPOSITE_EXPRESSION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_6)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_STDARG_USAGE(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_17_1, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_STDARG_USAGE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_17_1)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_VA_ARGS_USAGE(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_1, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_4, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_20_7, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_VA_ARGS_USAGE() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_20_7) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_4) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_1)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_VOIDPTR_TO_FUNCTION(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_5, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_VOIDPTR_TO_FUNCTION() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_5)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONCATENATION_PREPROCESSOR(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_20_10, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONCATENATION_PREPROCESSOR() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_20_10)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_SIGNED_SHIFT_AMOUNT(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT13_C, rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT14_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SIGNED_SHIFT_AMOUNT() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT14_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT13_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_MODIFY_STRING_LITERALS(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_STR30_C, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MODIFY_STRING_LITERALS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_STR30_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_RETURN_CODE_NOT_CHECKED(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Directive_4_7, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RETURN_CODE_NOT_CHECKED() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Directive_4_7)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_TO_VOIDPTR(rationale) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_6, rationale)
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_TO_VOIDPTR() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_6)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_FUNCTIONS_CONSUMED_BY_CUSTOMER() \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_DCL15_C, "can not make function static as it is consumed by customers.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_DCL19_C, "can not make function static as it is consumed by customers.")
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_FUNCTIONS_CONSUMED_BY_CUSTOMER() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_DCL19_C) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_DCL15_C)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPE_NAME_DOESNT_NEED_TO_BE_WRAPPED_BY_PARANTHESIS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_20_7, " Not wrapping a macro parameter in parentheses is allowed, if the parameter represents a type name")
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPE_NAME_DOESNT_NEED_TO_BE_WRAPPED_BY_PARANTHESIS() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_20_7)
+
+#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_IMPLICIT_CAST_FROM_CHAR() \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_3, "Implicit cast between char and uint8_t in examples is allowed for readability purposes")
+#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_IMPLICIT_CAST_FROM_CHAR() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_3)
+
+/* Tool specific handling: Coverity checkers */
+#if defined(__COVERITY__)
+
+#define MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(checker_identifier, rationale) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance block deviate checker_identifier rationale))
+#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(checker_identifier) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance end_block checker_identifier))
+
+#define MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(checker_identifier, rationale) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance block fp checker_identifier rationale))
+#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(checker_identifier) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance end_block checker_identifier))
+
+#define MCUX_CSSL_ANALYSIS_COVERITY_ASSERT(value, min_value, max_value, return_code) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(NO_EFFECT, "The minimum or the maximum value may have no effect for the condition.") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT("The minimum or the maximum value may have no effect for the condition.") \
+  if(((min_value) <= (value)) && ((value) <= (max_value))) \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(NO_EFFECT) \
+  {\
+    /* Do Nothing*/ \
+  }\
+  else \
+  {\
+    MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_17_4, "For void return, don't need to return a value at the end of function")\
+    return return_code;\
+    MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_17_4)\
+  }
+
+#define MCUX_CSSL_ANALYSIS_COVERITY_ASSERT_WITH_DATA_TYPE(value, data_type, min_value, max_value, return_code) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT36_C, "The minimum or the maximum value may have no effect for the condition.") \
+  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT("This is for the case where value is unsigned and min_value is unsigned zero.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_4, "The minimum or the maximum value may have no effect for the condition.") \
+  if((((data_type)(min_value)) <= ((data_type)(value))) && (((data_type)(value)) <= ((data_type)(max_value)))) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_4) \
+  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT() \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT36_C) \
+  {\
+    /* Do Nothing*/ \
+  }\
+  else \
+  {\
+    return return_code;\
+  }
+
+
+#else
+#define MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(checker_identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(checker_identifier)
+
+#define MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(checker_identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(checker_identifier)
+
+#define MCUX_CSSL_ANALYSIS_COVERITY_ASSERT(value, min_value, max_value, return_code)
+#define MCUX_CSSL_ANALYSIS_COVERITY_ASSERT_WITH_DATA_TYPE(value, data_type, min_value, max_value, return_code)
+#endif
+
+/* Tool specific handling: Clang warnings */
+#if defined(__clang__)
+#define MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(warning_identifier, rationale) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic push)) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
+#define MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(warning_identifier) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic pop))
+#else
+#define MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(warning_identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(warning_identifier)
+#endif
+
+/* Tool specific handling: GHS warnings */
+#if defined(__ghs__)
+#define MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(warning_identifier, rationale) \
+  MCUX_CSSL_ANALYSIS_PRAGMA(ghs nowarning warning_identifier)
+#define MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(warning_identifier) \
+  MCUX_CSSL_ANALYSIS_PRAGMA(ghs endnowarning warning_identifier)
+#else
+#define MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(warning_identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(warning_identifier)
+#endif
+
+/* Tool specific handling: GCC warnings */
+#if defined(__GNUC__)
+#define MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(warning_identifier, rationale)  \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic push)) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
+#define MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(warning_identifier)  \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic pop))
+#else
+#define MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(warning_identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(warning_identifier)
+#endif
+
+/* Arm Compiler 4/5 */
+#if defined(MCUX_CSSL_COMPILER_ARMCC)
+#define MCUX_CSSL_ANALYSIS_ARMCC_START_SUPPRESS_WARNING(warning_identifier, rationale)  \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(push)) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(diag_suppress MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
+#define MCUX_CSSL_ANALYSIS_ARMCC_STOP_SUPPRESS_WARNING(warning_identifier)  \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(pop))
+#else
+#define MCUX_CSSL_ANALYSIS_ARMCC_START_SUPPRESS_WARNING(warning_identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_ARMCC_STOP_SUPPRESS_WARNING(warning_identifier)
+#endif
+
+/* Arm Compiler 6 / Arm Compiler for Embedded 6 */
+#if defined(MCUX_CSSL_COMPILER_ARMCLANG) || defined(MCUX_CSSL_COMPILER_ARMCLANG_LTM)
+#define MCUX_CSSL_ANALYSIS_ARMCLANG_START_SUPPRESS_WARNING(warning_identifier, rationale)  \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic push)) \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
+#define MCUX_CSSL_ANALYSIS_ARMCLANG_STOP_SUPPRESS_WARNING(warning_identifier)  \
+  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic pop))
+#else
+#define MCUX_CSSL_ANALYSIS_ARMCLANG_START_SUPPRESS_WARNING(warning_identifier, rationale)
+#define MCUX_CSSL_ANALYSIS_ARMCLANG_STOP_SUPPRESS_WARNING(warning_identifier)
+#endif
+
+#endif /* MCUX_CSSL_ANALYSIS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslCPreProcessor.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslCPreProcessor.h
new file mode 100644
index 0000000000..f79bc21515
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslCPreProcessor.h
@@ -0,0 +1,216 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2019-2020, 2023 NXP                                            */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#ifndef MCUX_CSSL_C_PRE_PROCESSOR_H_
+#define MCUX_CSSL_C_PRE_PROCESSOR_H_
+
+/**
+ * @file  mcuxCsslCPreProcessor.h
+ * @brief The default implementation is based on standard C preprocessor
+ * functionality
+ */
+
+#define MCUX_CSSL_CPP_STR(a) #a
+
+#define MCUX_CSSL_CPP_ADD(a) + (a)
+
+#define MCUX_CSSL_CPP_CAT_IMPL(a, b) a##b
+
+#define MCUX_CSSL_CPP_CAT(a, b) \
+  MCUX_CSSL_CPP_CAT_IMPL(a, b)
+
+#define MCUX_CSSL_CPP_CAT3(a, b, c) \
+  MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_CAT(a, b), c)
+
+#define MCUX_CSSL_CPP_CAT4(a, b, c, d) \
+  MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_CAT(a, b), MCUX_CSSL_CPP_CAT(c, d))
+
+#define MCUX_CSSL_CPP_CAT6(a, b, c, d, e, f) \
+  MCUX_CSSL_CPP_CAT3( \
+    MCUX_CSSL_CPP_CAT(a, b), \
+    MCUX_CSSL_CPP_CAT(c, d), \
+    MCUX_CSSL_CPP_CAT(e, f))
+
+#define MCUX_CSSL_CPP_SEQUENCE_32TO0() \
+  32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, \
+  16, 15, 14, 13, 12, 11, 10,  9,  8,  7,  6,  5,  4,  3,  2,  1, 0
+
+#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_5TO0() \
+  n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \
+  n, n, n, n, n, n, n, n, n, n, n, 5, 4, 3, 2, 1, 0
+
+#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_4TO0() \
+  n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \
+  n, n, n, n, n, n, n, n, n, n, n, n, 4, 3, 2, 1, 0
+
+#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0() \
+  n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \
+  n, n, n, n, n, n, n, n, n, n, n, n, n, 3, 2, 1, 0
+
+#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0() \
+  n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \
+  n, n, n, n, n, n, n, n, n, n, n, n, n, n, 2, 1, 0
+
+#define MCUX_CSSL_CPP_ARG_N( \
+  _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, \
+  _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, \
+  N, ...) \
+    N
+
+#define MCUX_CSSL_CPP_ARGCOUNT_IMPL(...) \
+  MCUX_CSSL_CPP_ARG_N(__VA_ARGS__)
+
+#define MCUX_CSSL_CPP_ARGCOUNT(...) \
+  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_32TO0())
+
+#define MCUX_CSSL_CPP_ARGCOUNT_2N(...) \
+  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0())
+
+#define MCUX_CSSL_CPP_ARGCOUNT_3N(...) \
+  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0())
+
+#define MCUX_CSSL_CPP_ARGCOUNT_4N(...) \
+  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_4TO0())
+
+#define MCUX_CSSL_CPP_ARGCOUNT_5N(...) \
+  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_5TO0())
+
+#define MCUX_CSSL_CPP_OVERLOADED_IMPL(name, n) MCUX_CSSL_CPP_CAT_IMPL(name, n)
+
+#define MCUX_CSSL_CPP_OVERLOADED(name, ...) \
+  MCUX_CSSL_CPP_DEFER2(MCUX_CSSL_CPP_OVERLOADED_IMPL)()(name, MCUX_CSSL_CPP_ARGCOUNT(__VA_ARGS__))
+
+#define MCUX_CSSL_CPP_OVERLOADED1(name, ...) \
+  MCUX_CSSL_CPP_IF_ELSE(MCUX_CSSL_CPP_HAS_ONE_ARG(__VA_ARGS__))( \
+    /* If only one arg, use the 1 version */ \
+    MCUX_CSSL_CPP_CAT(name,1)(MCUX_CSSL_CPP_FIRST(__VA_ARGS__, /* ensure extra argument: */ 0)) \
+  )( \
+    /* Otherwise the n version */ \
+    MCUX_CSSL_CPP_CAT(name,n)(__VA_ARGS__) \
+  )
+
+#define MCUX_CSSL_CPP_OVERLOADED2(name, ...) \
+  MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_2N(__VA_ARGS__))(__VA_ARGS__)
+
+#define MCUX_CSSL_CPP_OVERLOADED3(name, ...) \
+  MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_3N(__VA_ARGS__))(__VA_ARGS__)
+
+#define MCUX_CSSL_CPP_OVERLOADED4(name, ...) \
+  MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_4N(__VA_ARGS__))(__VA_ARGS__)
+
+#define MCUX_CSSL_CPP_OVERLOADED5(name, ...) \
+  MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_5N(__VA_ARGS__))(__VA_ARGS__)
+
+/*****************************************************************************
+ * Helper macros                                                             *
+ *****************************************************************************/
+
+/* Apply a macro to all arguments */
+#define MCUX_CSSL_CPP_MAP(__macro, ...) \
+  MCUX_CSSL_CPP_EVAL(MCUX_CSSL_CPP_MAP_IMPL(__macro, __VA_ARGS__))
+
+/* Evaluate a complex macro (which needs multiple expansions to be processed) */
+#define MCUX_CSSL_CPP_EVAL(...)     MCUX_CSSL_CPP_EVAL1024(__VA_ARGS__)
+#define MCUX_CSSL_CPP_EVAL1024(...) MCUX_CSSL_CPP_EVAL512(MCUX_CSSL_CPP_EVAL512(__VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL512(...)  MCUX_CSSL_CPP_EVAL256(MCUX_CSSL_CPP_EVAL256(__VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL256(...)  MCUX_CSSL_CPP_EVAL128(MCUX_CSSL_CPP_EVAL128(__VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL128(...)  MCUX_CSSL_CPP_EVAL64( MCUX_CSSL_CPP_EVAL64( __VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL64(...)   MCUX_CSSL_CPP_EVAL32( MCUX_CSSL_CPP_EVAL32( __VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL32(...)   MCUX_CSSL_CPP_EVAL16( MCUX_CSSL_CPP_EVAL16( __VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL16(...)   MCUX_CSSL_CPP_EVAL8(  MCUX_CSSL_CPP_EVAL8(  __VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL8(...)    MCUX_CSSL_CPP_EVAL4(  MCUX_CSSL_CPP_EVAL4(  __VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL4(...)    MCUX_CSSL_CPP_EVAL2(  MCUX_CSSL_CPP_EVAL2(  __VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL2(...)    MCUX_CSSL_CPP_EVAL1(  MCUX_CSSL_CPP_EVAL1(  __VA_ARGS__))
+#define MCUX_CSSL_CPP_EVAL1(...)    __VA_ARGS__
+
+/* Recursive definition of map macro, assumes at least one argument */
+#define MCUX_CSSL_CPP_MAP_IMPL(__macro, ...) \
+  /* Apply the macro to the first argument from the list */\
+  __macro(MCUX_CSSL_CPP_FIRST(__VA_ARGS__, /* ensure second argument: */ 0)) \
+  /* Only proceed if there are additional arguments */\
+  MCUX_CSSL_CPP_IF(MCUX_CSSL_CPP_HAS_MORE_ARGS(__VA_ARGS__))( \
+    /* Recursive call for remaining arguments */\
+    MCUX_CSSL_CPP_DEFER2(MCUX_CSSL_CPP_MAP_IMPL_)()(__macro, \
+      MCUX_CSSL_CPP_NEXT(__VA_ARGS__)) \
+  )
+#define MCUX_CSSL_CPP_MAP_IMPL_() MCUX_CSSL_CPP_MAP_IMPL
+
+/* Extract first argument (requires at least two arguments to be present) */
+#define MCUX_CSSL_CPP_FIRST(a, ...) a
+/* Extract second argument (requires at least three arguments to be present) */
+#define MCUX_CSSL_CPP_SECOND(a, b, ...) b
+/* Extract third argument (requires at least four arguments to be present) */
+#define MCUX_CSSL_CPP_THIRD(a, b, c, ...) c
+/* Extract fourth argument (requires at least five arguments to be present) */
+#define MCUX_CSSL_CPP_FOURTH(a, b, c, d, ...) d
+/* Remove the first argument from the list (requires at least two arguments to be present) */
+#define MCUX_CSSL_CPP_NEXT(...) MCUX_CSSL_CPP_NEXT_()(__VA_ARGS__)
+#define MCUX_CSSL_CPP_NEXT_() MCUX_CSSL_CPP_NEXT__
+#define MCUX_CSSL_CPP_NEXT__(x, ...) __VA_ARGS__
+
+/* Check whether there is more then one argument */
+#define MCUX_CSSL_CPP_HAS_MORE_ARGS(...) \
+  MCUX_CSSL_CPP_NOT(MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_SECOND(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER())))
+
+#define MCUX_CSSL_CPP_HAS_ONE_ARG(...) \
+  MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_SECOND(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER()))
+
+#define MCUX_CSSL_CPP_HAS_TWO_ARGS(...) \
+  MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_THIRD(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER()))
+
+#define MCUX_CSSL_CPP_HAS_THREE_ARGS(...) \
+  MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_FOURTH(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER()))
+
+
+/* Check whether the argument is MCUX_CSSL_CPP_MARKER(), return 1 if it is */
+#define MCUX_CSSL_CPP_IS_MARKER(...) \
+  MCUX_CSSL_CPP_SECOND(__VA_ARGS__, 0, 0)
+#define MCUX_CSSL_CPP_MARKER() \
+  ~, 1
+
+/* Convert any argument into a bool (either 0 or 1), by double negation */
+#define MCUX_CSSL_CPP_BOOL(x) MCUX_CSSL_CPP_NOT(MCUX_CSSL_CPP_NOT(x))
+
+/* Boolean negation (map value 0 to the marker, and check if we have the marker) */
+#define MCUX_CSSL_CPP_NOT(x) MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_NOT_BOOL_, x))
+#define MCUX_CSSL_CPP_NOT_BOOL_0 MCUX_CSSL_CPP_MARKER()
+
+/* Convert condition to bool */
+#define MCUX_CSSL_CPP_IF(condition) MCUX_CSSL_CPP_IF_(MCUX_CSSL_CPP_BOOL(condition))
+/* Convert bool to decision defines */
+#define MCUX_CSSL_CPP_IF_(condition) MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_IF_BOOL_, condition)
+/* If 0, do nothing*/
+#define MCUX_CSSL_CPP_IF_BOOL_0(...)
+/* If 1, perform action */
+#define MCUX_CSSL_CPP_IF_BOOL_1(...) __VA_ARGS__
+
+/* Convert condition to bool */
+#define MCUX_CSSL_CPP_IF_ELSE(condition) MCUX_CSSL_CPP_IF_ELSE_IMPL(MCUX_CSSL_CPP_BOOL(condition))
+/* Convert bool to decision defines */
+#define MCUX_CSSL_CPP_IF_ELSE_IMPL(condition) MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_IFE_BOOL_, condition)
+/* If 0, ignore action */
+#define MCUX_CSSL_CPP_IFE_BOOL_0(...)             MCUX_CSSL_CPP_IFE_BOOL_0_ELSE
+/* Else 0, perform action */
+#define MCUX_CSSL_CPP_IFE_BOOL_0_ELSE(...) __VA_ARGS__
+/* If 1, perform action */
+#define MCUX_CSSL_CPP_IFE_BOOL_1(...) __VA_ARGS__ MCUX_CSSL_CPP_IFE_BOOL_1_ELSE
+/* Else 1, ignore action */
+
+#define MCUX_CSSL_CPP_IFE_BOOL_1_ELSE(...)
+
+/* Defer macro expansion */
+#define MCUX_CSSL_CPP_EMPTY()
+#define MCUX_CSSL_CPP_DEFER1(macro) macro MCUX_CSSL_CPP_EMPTY()
+#define MCUX_CSSL_CPP_DEFER2(macro) macro MCUX_CSSL_CPP_EMPTY MCUX_CSSL_CPP_EMPTY()()
+
+#endif /* MCUX_CSSL_C_PRE_PROCESSOR_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity.h
new file mode 100644
index 0000000000..1a77d54233
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity.h
@@ -0,0 +1,151 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslDataIntegrity.h
+ * @brief Provides the API for the CSSL data integrity mechanism.
+ */
+
+#ifndef MCUXCSSLDATAINTEGRITY_H_
+#define MCUXCSSLDATAINTEGRITY_H_
+
+/* Include the Secure Counter definitions */
+#include <mcuxCsslSecureCounter.h>
+
+/* Include the actual implementation of the data integrity mechanism. */
+#include <mcuxCsslDataIntegrity_Impl.h>
+
+/**
+ * @addtogroup mcuxCsslAPI MCUX CSSL -- API
+ *
+ * @defgroup mcuxCsslDataIntegrity Data Integrity API
+ * @brief Data integrity mechanism.
+ * @ingroup mcuxCsslAPI
+ */
+
+
+/**
+ * @defgroup diCore Data integrity core functionality
+ * @brief Data integrity handling core functionality.
+ * @ingroup mcuxCsslDataIntegrity
+ */
+
+/****************************************************************************/
+/* Constants                                                                */
+/****************************************************************************/
+
+/**
+ * @def MCUX_CSSL_DI_CHECK_PASSED
+ * @brief Positive comparison result value.
+ * @api
+ * @ingroup diCore
+ */
+#define MCUX_CSSL_DI_CHECK_PASSED \
+  MCUX_CSSL_DI_CHECK_PASSED_IMPL
+
+/**
+ * @def MCUX_CSSL_DI_CHECK_FAILED
+ * @brief Negative comparison result value.
+ * @api
+ * @ingroup diCore
+ */
+#define MCUX_CSSL_DI_CHECK_FAILED \
+  MCUX_CSSL_DI_CHECK_FAILED_IMPL
+
+/****************************************************************************/
+/* Initialization                                                           */
+/****************************************************************************/
+
+/**
+ * @def MCUX_CSSL_DI_INIT
+ * @brief Backup of the current data integrity value, that will be checked later
+ *        on with MCUX_CSSL_SC_CHECK.
+ *        Note that in case the Security Counter back-end requires allocation, it
+ *        is expected that this will be handled by the Flow Protection mechanism
+ *        before the initialization of the Data Integrity.
+ * @api
+ * @ingroup diCore
+ *
+ * @param backupValue Fresh variable name to store the current DI value.
+ */
+#define MCUX_CSSL_DI_INIT(backupValue) \
+  MCUX_CSSL_DI_INIT_IMPL(backupValue)
+
+/****************************************************************************/
+/* Check                                                                    */
+/****************************************************************************/
+
+/**
+ * @def MCUX_CSSL_DI_CHECK
+ * @brief Comparison operation for the data integrity.
+ * @api
+ * @ingroup diCore
+ *
+ * @param reference Reference value to compare the data integrity value against.
+ * @return          Either #MCUX_CSSL_DI_CHECK_PASSED, if the value matches, or
+ *                  #MCUX_CSSL_DI_CHECK_FAILED if the value is different.
+ */
+#define MCUX_CSSL_DI_CHECK(reference) \
+  MCUX_CSSL_DI_CHECK_IMPL(reference)
+
+/**
+ * @def MCUX_CSSL_DI_CHECK_EXIT
+ * @brief Comparison operation for the data integrity.
+ *        It compares the data integrity value to reference value, and exits
+ *        with the given fault status code if the comparison fails.
+ *        If the comparison succeeds, the normal execution will continue.
+ * @api
+ * @ingroup diCore
+ *
+ * @param id        Identifier of the function from which we will exit.
+ * @param reference Reference value to compare the data integrity value against.
+ * @param fail      Result that should be returned if the data integrity check failed.
+ */
+#define MCUX_CSSL_DI_CHECK_EXIT(id, reference, fail) \
+  MCUX_CSSL_DI_CHECK_EXIT_IMPL(id, reference, fail)
+
+/****************************************************************************/
+/* Updates                                                                  */
+/****************************************************************************/
+
+/**
+ * @defgroup diUpdate Data integrity record
+ * @brief Support for recording a value in the data integrity register
+ * @ingroup mcuxCsslDataIntegrity
+ */
+
+/**
+ * @def MCUX_CSSL_DI_RECORD
+ * @brief Record the @p value for data integrity checking.
+ * @api
+ * @ingroup diUpdate
+ *
+ * @param identifier Identifier for the @p value that will be recorded.
+ * @param value Value which needs to be recorded for the given @p identifier.
+ */
+#define MCUX_CSSL_DI_RECORD(identifier, value) \
+  MCUX_CSSL_DI_RECORD_IMPL(identifier, value)
+
+/**
+ * @def MCUX_CSSL_DI_EXPUNGE
+ * @brief Expunge the record for @p value.
+ * @api
+ * @ingroup diUpdate
+ *
+ * @param identifier Identifier for the @p value that will be expunged.
+ * @param value Expected value that was recorded for the given @p identifier.
+ */
+#define MCUX_CSSL_DI_EXPUNGE(identifier, value) \
+  MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value)
+
+#endif /* MCUXCSSLDATAINTEGRITY_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Cfg.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Cfg.h
new file mode 100644
index 0000000000..ba8cc78bd2
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Cfg.h
@@ -0,0 +1,47 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslDataIntegrity_Cfg.h
+ * \brief Configuration of the implementation for the data integrity mechanism.
+ */
+
+#ifndef MCUXCSSLDATAINTEGRITY_CFG_H_
+#define MCUXCSSLDATAINTEGRITY_CFG_H_
+
+/**
+ * \addtogroup mcuxCsslCFG MCUX CSSL -- Configurations
+ *
+ * \defgroup mcuxCsslDataIntegrity_CFG Data Integrity Configuration
+ * \brief Configuration options for the data integrity mechanism.
+ * \ingroup mcuxCsslCFG
+ */
+
+/**
+ * \def MCUX_CSSL_DI_USE_SECURE_COUNTER
+ * \brief If set to 1, use the data integrity mechanism implementation based on
+ *        the CSSL secure counter mechanism.
+ * \ingroup mcuxCsslDataIntegrity_CFG
+ */
+    #define MCUX_CSSL_DI_USE_SECURE_COUNTER      0
+
+/**
+ * \def MCUX_CSSL_DI_USE_NONE
+ * \brief If set to 1, do not use the data integrity mechanism.
+ * \ingroup mcuxCsslDataIntegrity_CFG
+ */
+    #define MCUX_CSSL_DI_USE_NONE    1
+
+/* Basic configuration sanity check */
+
+#endif /* MCUXCSSLDATAINTEGRITY_CFG_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Impl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Impl.h
new file mode 100644
index 0000000000..48015e93e5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Impl.h
@@ -0,0 +1,34 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslDataIntegrity_Impl.h
+ * \brief Selection of the implementation for the data integrity mechanism.
+ */
+
+#ifndef MCUXCSSLDATAINTEGRITY_IMPL_H_
+#define MCUXCSSLDATAINTEGRITY_IMPL_H_
+
+/* Include the configuration for the data integrity mechanism. */
+#include <mcuxCsslDataIntegrity_Cfg.h>
+
+/* Include the selected implementation of the data integrity mechanism. */
+#if defined(MCUX_CSSL_DI_USE_SECURE_COUNTER) && (1 == MCUX_CSSL_DI_USE_SECURE_COUNTER)
+#  include <mcuxCsslDataIntegrity_SecureCounter.h>
+#elif defined(MCUX_CSSL_DI_USE_NONE) && (1 == MCUX_CSSL_DI_USE_NONE)
+#  include <mcuxCsslDataIntegrity_None.h>
+#else
+  #error "No data integrity implementation found/configured."
+#endif
+
+#endif /* MCUXCSSLDATAINTEGRITY_IMPL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_None.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_None.h
new file mode 100644
index 0000000000..e06cc7363f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_None.h
@@ -0,0 +1,130 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslDataIntegrity_None.h
+ * \brief Implementation that disables the CSSL data integrity mechanism.
+ */
+
+#ifndef MCUXCSSLDATAINTEGRITY_NONE_H_
+#define MCUXCSSLDATAINTEGRITY_NONE_H_
+
+/**
+ * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations
+ *
+ * \defgroup mcuxCsslDataIntegrity_None Data Integrity: Disabled
+ * \brief Disable the data integrity mechanism.
+ * \ingroup mcuxCsslIMPL
+ */
+
+
+/**
+ * \defgroup diNoneCore Data integrity core functionality
+ * \brief Data integrity handling core functionality, when data integrity is disabled.
+ * \ingroup mcuxCsslDataIntegrity_None
+ */
+
+/****************************************************************************/
+/* Constants                                                                */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_DI_CHECK_PASSED_IMPL
+ * \brief Positive comparison result value.
+ * \ingroup diNoneCore
+ */
+#define MCUX_CSSL_DI_CHECK_PASSED_IMPL (MCUX_CSSL_SC_CHECK_PASSED)
+
+/**
+ * \def MCUX_CSSL_DI_CHECK_FAILED_IMPL
+ * \brief Negative comparison result value.
+ * \ingroup diNoneCore
+ */
+#define MCUX_CSSL_DI_CHECK_FAILED_IMPL (MCUX_CSSL_SC_CHECK_FAILED)
+
+/****************************************************************************/
+/* Initialization                                                           */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_DI_INIT_IMPL
+ * \brief Initialize the backup of the data integrity value to zero.
+ * \ingroup diNoneCore
+ *
+ * @param backupValue Fresh variable name to store the current DI value.
+ */
+#define MCUX_CSSL_DI_INIT_IMPL(backupValue) \
+  uint32_t backupValue = 0u
+
+/****************************************************************************/
+/* Check                                                                    */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_DI_CHECK_IMPL
+ * \brief Comparison operation implementation for the data integrity.
+ * \ingroup diNoneCore
+ *
+ * \param reference Reference value to compare the data integrity value against.
+ * \return          Always #MCUX_CSSL_DI_CHECK_PASSED.
+ */
+#define MCUX_CSSL_DI_CHECK_IMPL(reference) \
+  (MCUX_CSSL_DI_CHECK_PASSED_IMPL)
+
+/**
+ * \def MCUX_CSSL_DI_CHECK_EXIT_IMPL
+ * \brief Comparison operation implementation for the data integrity.
+ *        It has no impact on the normal execution of the calling function.
+ * \ingroup diNoneCore
+ *
+ * \param id        Identifier of the function from which we will exit (ignored).
+ * \param reference Reference value to compare the data integrity value against.
+ * \param fail      Result that should be returned if the data integrity check failed (ignored).
+ */
+#define MCUX_CSSL_DI_CHECK_EXIT_IMPL(id, reference, fail) \
+  (void)(reference)
+
+/****************************************************************************/
+/* Updates                                                                  */
+/****************************************************************************/
+
+/**
+ * \defgroup diNoneUpdate Data integrity record
+ * \brief Support for recording a value in the data integrity register, when data integrity is disabled.
+ * \ingroup mcuxCsslDataIntegrity_None
+ */
+
+/**
+ * \def MCUX_CSSL_DI_RECORD_IMPL
+ * \brief Implementation: Record the value for data integrity checking.
+ * \ingroup diNoneUpdate
+ *
+ * \param identifier Identifier for the value that will be recorded.
+ * \param value      Value which needs to be recorded for the given identifier.
+ */
+#define MCUX_CSSL_DI_RECORD_IMPL(identifier, value) \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_DI_EXPUNGE_IMPL
+ * \brief Implementation: Expunge the record for value.
+ * \ingroup diNoneUpdate
+ *
+ * \param identifier Identifier for the value that will be expunged.
+ * \param value      Expected value that was recorded for the given identifier.
+ */
+#define MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value) \
+  /* intentionally empty */
+
+
+#endif /* MCUXCSSLDATAINTEGRITY_NONE_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection.h
new file mode 100644
index 0000000000..8e8772b9e5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection.h
@@ -0,0 +1,1439 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslFlowProtection.h
+ * @brief Provides the API for the CSSL flow protection mechanism.
+ */
+
+#ifndef MCUX_CSSL_FLOW_PROTECTION_H_
+#define MCUX_CSSL_FLOW_PROTECTION_H_
+
+#include <mcuxCsslAnalysis.h>
+
+/* Include the actual implementation of the flow protection mechanism. */
+#include <mcuxCsslFlowProtection_Impl.h>
+
+/**
+ * @addtogroup mcuxCsslAPI MCUX CSSL -- API
+ *
+ * @defgroup mcuxCsslFlowProtection Flow Protection API
+ * @brief Flow protection mechanism.
+ * @ingroup mcuxCsslAPI
+ */
+
+
+/**
+ * @defgroup csslFpCore Flow protection core functionality
+ * @brief Flow protection handling core functionality.
+ * @ingroup mcuxCsslFlowProtection
+ *
+ * @todo Extend this description of the core functionality which relies
+ *       basically on the function calling flow protection.
+ *
+ * @declaration{MCUX_CSSL_FP_FUNCTION_DECL}
+ * @event{MCUX_CSSL_FP_FUNCTION_CALL}
+ * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED}
+ */
+
+/**
+ * @defgroup csslFpFunction Function calling flow protection
+ * @brief Support for flow protected functions.
+ * @ingroup mcuxCsslFlowProtection
+ *
+ * @declaration{MCUX_CSSL_FP_FUNCTION_DECL}
+ * @event{MCUX_CSSL_FP_FUNCTION_CALL}
+ * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED}
+ */
+
+
+MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Comments outline example sequences. For more readability, additional inner comments might be added.")
+/**
+ * @def MCUX_CSSL_FP_PROTECTED_TYPE
+ * @brief Based on a given base type, builds a return type with flow
+ *        protection.
+ * @ingroup csslFpFunction
+ *
+ * This macro must be used to wrap the function return type. For example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DECL(someFunction)
+ * MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) someFunction(void);
+ * @endcode
+ *
+ * Note that depending on the selected flow protection mechanism, the width of
+ * the result type may be limited to 32 bits or less to allow encoding a
+ * protection token in the other half of a 64-bit return value.
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DEF
+ *
+ * @param resultType The type to be converted into a protected type.
+ */
+#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType) \
+  MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType)
+
+/**
+ * @def MCUX_CSSL_FP_COUNTER_STMT
+ * @brief A statement which is only evaluated if a secure counter is used.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This macro can be used to create counting variables that are only present if
+ * the active configuration uses a secure counter, to avoid warnings about
+ * unused variables.
+ *
+ * @param statement The statement to be conditionally included.
+ */
+#define MCUX_CSSL_FP_COUNTER_STMT(statement) \
+  MCUX_CSSL_FP_COUNTER_STMT_IMPL(statement)
+
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_DECL
+ * @brief Declaration of a flow protected function.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This declaration must be placed just in front of the actual function
+ * declaration. For example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DECL(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void);
+ * @endcode
+ *
+ * @event{MCUX_CSSL_FP_FUNCTION_CALL}
+ * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DEF
+ * @see MCUX_CSSL_FP_FUNCTION_POINTER
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ *
+ * @param id Identifier for the function that is flow protected.
+ * @param ptrType Optional, pointer type matching this function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_DECL(...) \
+  MCUX_CSSL_FP_FUNCTION_DECL_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_DEF
+ * @brief Definition of a flow protected function.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This definition macro must be placed just in front of the actual function
+ * definition, that has been previously declared as flow protected using
+ * #MCUX_CSSL_FP_FUNCTION_DECL. For example:
+ * @code
+ * // someHeader.h
+ * MCUX_CSSL_FP_FUNCTION_DECL(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void);
+ *
+ * // someFile.c
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   // some function body
+ * }
+ * @endcode
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DECL
+ * @see MCUX_CSSL_FP_FUNCTION_POINTER
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ *
+ * @param id Identifier for the function that is flow protected.
+ * @param ptrType Optional, pointer type matching this function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_DEF(...) \
+  MCUX_CSSL_FP_FUNCTION_DEF_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_POINTER
+ * @brief Definition of a flow protected function pointer.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This definition macro must be placed around a function pointer
+ * definition. For example:
+ * @code
+ * // someHeader.h
+ * MCUX_CSSL_FP_FUNCTION_POINTER(ptrType,
+ * typedef void (*ptrType)(void));
+ *
+ * MCUX_CSSL_FP_FUNCTION_DECL(someFunction, ptrType) // Note: no semicolon here
+ * uint32_t someFunction(void);
+ *
+ * // someFile.c
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction, ptrType) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   // some function body
+ * }
+ * @endcode
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DECL
+ * @see MCUX_CSSL_FP_FUNCTION_DEF
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ *
+ * @param type Identifier for the function pointer type that is flow protected.
+ * @param definition Actual type definition of the function pointer type.
+ */
+#define MCUX_CSSL_FP_FUNCTION_POINTER(type, definition) \
+  MCUX_CSSL_FP_FUNCTION_POINTER_IMPL(type, definition)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @brief Flow protection handler for the function entry point.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This entry macro should be placed at the start of the function body that
+ * needs to be protected. The function must have been declared before as flow
+ * protected using #MCUX_CSSL_FP_FUNCTION_DECL. For example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // remainder of the function body
+ * }
+ * @endcode
+ *
+ * The only statements that should be placed before this one, are declarations
+ * for flow protected operations that are already used as expectations in this
+ * macro. For example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(uint32_t count)
+ * {
+ *   MCUX_CSSL_FP_LOOP_DECL(someLoop);
+ *   MCUX_CSSL_FP_LOOP_DECL(otherLoop);
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction,
+ *     MCUX_CSSL_FP_LOOP_ITERATIONS(someLoop, count),
+ *     MCUX_CSSL_FP_LOOP_ITERATIONS(otherLoop, 2u * count)
+ *   );
+ *   // Remainder of the function body, where someLoop makes count iterations,
+ *   // and otherLoop 2*count iterations.
+ * }
+ * @endcode
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DECL
+ * @see MCUX_CSSL_FP_FUNCTION_DEF
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:     Identifier of the function that has just been entered. <br>
+ *        - expect: Zero or more (comma separated) declarations of expected code
+ *               flow behavior.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ENTRY(...) \
+  MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_EXIT
+ * @brief Flow protection handler for the function exit point.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This exit macro must replace the regular \c return statements of a protected
+ * function. Given the following unprotected example:
+ * @code
+ * uint32_t someFunction(void)
+ * {
+ *   // some function body
+ *   return 0;
+ * }
+ * @endcode
+ * The protected version would become:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // remainder of the function body
+ *   MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0);
+ * }
+ * @endcode
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DECL
+ * @see MCUX_CSSL_FP_FUNCTION_DEF
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:     Identifier of the function from which we will exit.
+ *        - result: Result that should be encoded in the return value.
+ *        - expect: Zero or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * @return       A value in which both \p result and a flow protection token
+ *               are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT(...) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @brief Flow protection handler for the function exit point which includes
+ *        an actual check of the code flow.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This exit macro must replace the regular \c return statements of a protected
+ * function. In addition to #MCUX_CSSL_FP_FUNCTION_EXIT it also checks the flow
+ * protection, and selects the return value accordingly. For example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // remainder of the function body
+ *   MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(someFunction, 0, 0xFAu);
+ * }
+ * @endcode
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DECL
+ * @see MCUX_CSSL_FP_FUNCTION_DEF
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:      Identifier of the function from which we will exit.
+ *        - pass:    Result that should be encoded in the return value if the flow
+ *                   protection check passed.
+ *        - fail:    Result that should be encoded in the return value if the flow
+ *                   protection check failed.
+ *        - expect:  Zero or more (comma separated) declarations of expected code
+ *                  flow behavior.
+ * @return       A value in which both the result (either \p pass or \p fail)
+ *               and a flow protection token are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(...) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_EXIT_VOID
+ * @brief Flow protection handler for the exit point of functions with the
+ *        return type \c void.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This exit macro must replace the regular \c return statements of a protected
+ * void function. Given the following unprotected example:
+ * @code
+ * void someFunction(void)
+ * {
+ *   // some function body
+ *   return 0;
+ * }
+ * @endcode
+ * The protected version would become:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * void someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // remainder of the function body
+ *   MCUX_CSSL_FP_FUNCTION_EXIT_VOID(someFunction);
+ * }
+ * @endcode
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_DECL
+ * @see MCUX_CSSL_FP_FUNCTION_DEF
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ *
+ * @param ...       The following parameters need to be passed (comma separated):
+ *        - id:     Identifier of the function from which we will exit.
+ *        - expect: Zero or more (comma separated) declarations of expected code
+ *                  flow behavior.
+ * @return       A protected return value of type void.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID(...) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_RESULT
+ * @brief Extract the result value from a protected \p return value.
+ * @ingroup csslFpFunction
+ *
+ * This macro should mainly be used internally to extract the original return value
+ * from a protected value, e.g., in MCUX_CSSL_FP_FUNCTION_CALL_IMPL.
+ *
+ * @param ...       The following parameters need to be passed (comma seperated):
+ *        - type:   Optional, type of the result (default: uint32_t).
+ *        - return: The protected return value which contains the result.
+ */
+#define MCUX_CSSL_FP_RESULT(...) \
+  MCUX_CSSL_FP_RESULT_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_PROTECTION_TOKEN
+ * @brief Extract the protection token value from a protected \p return value.
+ * @ingroup csslFpFunction
+ *
+ * Note that this macro is only used with a local security counter,
+ * e.g. for configuration CSSL_SC_USE_SW_LOCAL
+ *
+ * @param return The protected return value which contains the protection token.
+ */
+#define MCUX_CSSL_FP_PROTECTION_TOKEN(return) \
+  MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL
+ * @brief Call a flow protected function.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This function call macro encapsulates the flow protection handling needed
+ * for calling a function. In particular it takes care of extracting the flow
+ * protection token from the return value (which has been inserted by
+ * #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK) and
+ * incorporating that in the flow protection of the current function. For
+ * example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction());
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *     MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
+ *   );
+ * }
+ * @endcode
+ *
+ * For functions returning void, the macro #MCUX_CSSL_FP_FUNCTION_CALL_VOID
+ * exists.
+ *
+ * @declaration{MCUX_CSSL_FP_FUNCTION_DECL}
+ * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED}
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - result: Fresh variable name to store the result of \p call.
+ *        - call:   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID
+ * @brief Call a flow protected void function.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This function call macro encapsulates the flow protection handling needed
+ * for calling a void function. In particular it takes care of extracting the
+ * flow protection token from the return value (which has been inserted by
+ * #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK) and
+ * incorporating that in the flow protection of the current function. For
+ * example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_VOID(otherFunction());
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *     MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
+ *   );
+ * }
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_FUNCTION_DECL}
+ * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED}
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - call:   The (protected) void function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED
+ * @brief Call a flow protected function from unprotected code.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This function call macro encapsulates the flow protection handling needed
+ * for calling a function from within a function which does not have local
+ * flow protection, or which uses a different flow protection mechanism than
+ * the one provided by CSSL. In particular it takes care of extracting the
+ * protection token and result from the return value (which has been inserted
+ * by #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK).
+ * For example:
+ * @code
+ * uint32_t someUnprotectedFunction(void)
+ * {
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(
+ *     result,
+ *     token,
+ *     otherFunction());
+ *   // Check the protection token
+ *   if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
+ *   {
+ *     return FAULT;
+ *   }
+ *   // ... The following code may use result as a variable ...
+ * }
+ * @endcode
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - result: Fresh variable name to store the result of \p call.
+ *        - token:  Fresh variable name to store the protection token of \p call.
+ *        - call:   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(__VA_ARGS__)
+
+  /**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED
+ * @brief Call a flow protected void function from unprotected code.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This function call macro encapsulates the flow protection handling needed
+ * for calling a void function from within a function which does not have flow
+ * protection, or which uses a different flow protection mechanism than the one
+ * provided by CSSL. In particular it takes care of extracting the protection
+ * token and result from the return value (which has been inserted by
+ * #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK).
+ * For example:
+ * @code
+ * uint32_t someUnprotectedFunction(void)
+ * {
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(
+ *     token,
+ *     protectedVoidFunction());
+ *   // Check the protection token
+ *   if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
+ *   {
+ *     return FAULT;
+ *   }
+ *   // ...
+ * }
+ * @endcode
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - token:  Fresh variable name to store the protection token of \p call.
+ *        - call:   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL_BEGIN
+ * @brief Call a flow protected function and check the protection token.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This function call macro encapsulates the flow protection handling needed
+ * for calling a function from within a function which does not have local
+ * flow protection, or which uses a different flow protection mechanism than
+ * the one provided by CSSL. In particular it takes care of extracting the
+ * protection token and result from the return value (which has been inserted
+ * by #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK).
+ * For example:
+ * @code
+ * uint32_t someUnprotectedFunction(void)
+ * {
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(
+ *     result,
+ *     token,
+ *     otherFunction());
+ *   // Check the protection token
+ *   if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
+ *   {
+ *     return FAULT;
+ *   }
+ *   // ... The following code may use result as a variable ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_END();
+ *   // ... result is invalid here ...
+ * }
+ * @endcode
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - result: Fresh variable name to store the result of \p call.
+ *        - token:  Fresh variable name to store the protection token of \p call.
+ *        - call:   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL_END
+ * @brief End a function call section started by
+ * #MCUX_CSSL_FP_FUNCTION_CALL_BEGIN.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * Example:
+ * @code
+ * uint32_t someUnprotectedFunction(void)
+ * {
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(
+ *     result,
+ *     token,
+ *     otherFunction());
+ *   // Check the protection token
+ *   if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
+ *   {
+ *     return FAULT;
+ *   }
+ *   // ... The following code may use result as a variable ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_END();
+ *   // ... result is invalid here ...
+ * }
+ * @endcode
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - result: Fresh variable name to store the result of \p call.
+ *        - token:  Fresh variable name to store the protection token of \p call.
+ *        - call:   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_END(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN
+ * @brief Call a flow protected void function and check the protection token.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This function call macro encapsulates the flow protection handling needed
+ * for calling a void function from within a function which does not have local
+ * flow protection, or which uses a different flow protection mechanism than
+ * the one provided by CSSL. In particular it takes care of extracting the
+ * protection token from the return value (which has been inserted
+ * by #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK).
+ * For example:
+ * @code
+ * uint32_t someUnprotectedFunction(void)
+ * {
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(
+ *     token,
+ *     otherFunction());
+ *   // Check the protection token
+ *   if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
+ *   {
+ *     return FAULT;
+ *   }
+ *   MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
+ * }
+ * @endcode
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - token:  Fresh variable name to store the protection token of \p call.
+ *        - call:   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID_END
+ * @brief End a void function call section started by
+ * #MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * Example:
+ * @code
+ * uint32_t someUnprotectedFunction(void)
+ * {
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(
+ *     token,
+ *     otherFunction());
+ *   // Check the protection token
+ *   if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
+ *   {
+ *     return FAULT;
+ *   }
+ *   MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
+ * }
+ * @endcode
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - token:  Fresh variable name to store the protection token of \p call.
+ *        - call:   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(...) \
+  MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_CALLED
+ * @brief Expectation of a called function.
+ * @api
+ * @ingroup csslFpFunction
+ *
+ * This expectation macro indicates to the flow protection mechanism that a
+ * function call is expected to happen (if placed before the actual call), for
+ * example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction,
+ *     MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
+ *   );
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction());
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0);
+ * }
+ * @endcode
+ * Or that a function call has happened (if placed after the actual call), for
+ * example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction());
+ *   // ...
+ *   MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *     MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
+ *   );
+ * }
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_FUNCTION_DECL}
+ * @event{MCUX_CSSL_FP_FUNCTION_CALL}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        -id: Identifier of the function that is expected to be called.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALLED(...) \
+  MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(__VA_ARGS__)
+
+
+/**
+ * @def MCUX_CSSL_FP_FUNCTION_ENTERED
+ * @brief Expectation implementation of an entered (but not exited) function.
+ * @ingroup csslFpFunction
+ *
+ * This expectation macro indicates to the flow protection mechanism that a
+ * function entry has happened, for example:
+ * @code
+ * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
+ * uint32_t someFunction(void)
+ * {
+ *   MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
+ *   // ...
+ *   MCUX_CSSL_FP_ASSERT(MCUX_CSSL_FP_FUNCTION_ENTERED(someFunction);
+ *   // ...
+ * }
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_FUNCTION_DECL}
+ * @event{MCUX_CSSL_FP_FUNCTION_CALL}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ * @see MCUX_CSSL_FP_FUNCTION_CALLED
+ * @see MCUX_CSSL_FP_ASSERT
+ *
+ * @param id Identifier of the function that is expected to be entered.
+ * @return   Counter value for the given function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ENTERED(id) \
+  MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id)
+
+
+/**
+ * @defgroup csslFpLoop Looping flow protection
+ * @brief Support for flow protected loops.
+ * @ingroup mcuxCsslFlowProtection
+ *
+ * @declaration{MCUX_CSSL_FP_LOOP_DECL}
+ * @event{MCUX_CSSL_FP_LOOP_ITERATION}
+ * @expectation{MCUX_CSSL_FP_LOOP_ITERATIONS}
+ */
+
+/**
+ * @def MCUX_CSSL_FP_LOOP_DECL
+ * @brief Declaration of a flow protected loop.
+ * @api
+ * @ingroup csslFpLoop
+ *
+ * To inform the flow protection mechanism about a loop that needs to be
+ * protected, a loop identifier needs to be declared. This identifier can then
+ * be used in the event and expectation macros. For example:
+ * @code
+ * MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier);
+ * for (uint32_t i = 0; i < 8; ++i)
+ * {
+ *   MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier);
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *   MCUX_CSSL_FP_LOOP_ITERATIONS(someLoopIdentifier, 8)
+ * );
+ * @endcode
+ *
+ * @event{MCUX_CSSL_FP_LOOP_ITERATION}
+ * @expectation{MCUX_CSSL_FP_LOOP_ITERATIONS}
+ *
+ * @param id Identifier for the loop that is flow protected.
+ */
+#define MCUX_CSSL_FP_LOOP_DECL(id) \
+  MCUX_CSSL_FP_LOOP_DECL_IMPL(id)
+
+/**
+ * @def MCUX_CSSL_FP_LOOP_ITERATION
+ * @brief Perform a loop iteration.
+ * @api
+ * @ingroup csslFpLoop
+ *
+ * This loop iteration macro informs the flow mechanism that an iteration event
+ * is performed for the loop declared by #MCUX_CSSL_FP_LOOP_DECL with the given
+ * \p id. For example:
+ * @code
+ * MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier);
+ * for (uint32_t i = 0; i < 8; ++i)
+ * {
+ *   MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier);
+ * }
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_LOOP_DECL}
+ * @expectation{MCUX_CSSL_FP_LOOP_ITERATIONS}
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:      Identifier for the loop that is flow protected.
+ *        - expect:  Zero or more (comma separated) declarations of expected code
+ *                   flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_LOOP_ITERATION(...) \
+  MCUX_CSSL_FP_LOOP_ITERATION_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_LOOP_ITERATIONS
+ * @brief Expected number of loop iterations.
+ * @api
+ * @ingroup csslFpLoop
+ *
+ * This expectation macro indicates to the flow protection mechanism that the
+ * loop declared by #MCUX_CSSL_FP_LOOP_DECL with the given \p id has made
+ * \p count iterations. For example:
+ * @code
+ * MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier);
+ * for (uint32_t i = 0; i < 8; ++i)
+ * {
+ *   MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier);
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *   MCUX_CSSL_FP_LOOP_ITERATIONS(someLoopIdentifier, 8)
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_LOOP_DECL}
+ * @event{MCUX_CSSL_FP_LOOP_ITERATION}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ *
+ * @param id    Identifier of the flow protected loop.
+ * @param count Number of expected iterations.
+ */
+#define MCUX_CSSL_FP_LOOP_ITERATIONS(id, count) \
+  MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count)
+
+
+
+/**
+ * @defgroup csslFpBranch Branching flow protection
+ * @brief Support for flow protected branches.
+ * @ingroup mcuxCsslFlowProtection
+ *
+ * @declaration{MCUX_CSSL_FP_BRANCH_DECL}
+ * @event{MCUX_CSSL_FP_BRANCH_POSITIVE,MCUX_CSSL_FP_BRANCH_NEGATIVE}
+ * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE}
+ */
+
+/**
+ * @def MCUX_CSSL_FP_BRANCH_DECL
+ * @brief Declaration of a flow protected branch.
+ * @api
+ * @ingroup csslFpBranch
+ *
+ * To inform the flow protection mechanism about a branch that needs to be
+ * protected, a branch identifier needs to be declared. This identifier can
+ * then be used in the events and expectation macros. For example:
+ * @code
+ * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
+ * if (condition)
+ * {
+ *   MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
+ * }
+ * else
+ * {
+ *   MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *   MCUX_CSSL_FP_BRANCH_TAKEN(someBranchIdentifier,
+ *     MCUX_CSSL_FP_BRANCH_POSITIVE_SCENARIO, condition)
+ * );
+ * @endcode
+ *
+ * @event{MCUX_CSSL_FP_BRANCH_POSITIVE,MCUX_CSSL_FP_BRANCH_NEGATIVE}
+ * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE}
+ *
+ * @param id Identifier for the branch that is flow protected.
+ */
+#define MCUX_CSSL_FP_BRANCH_DECL(id) \
+  MCUX_CSSL_FP_BRANCH_DECL_IMPL(id)
+
+/**
+ * @def MCUX_CSSL_FP_BRANCH_POSITIVE
+ * @brief Positive scenario for a branch is executed.
+ * @api
+ * @ingroup csslFpBranch
+ *
+ * This branch event macro informs the flow mechanism that the positive scenario
+ * of the branch is executed for the branch declared by
+ * #MCUX_CSSL_FP_BRANCH_DECL with the given \p id. For example:
+ * @code
+ * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
+ * if (condition)
+ * {
+ *   MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
+ * }
+ * else
+ * {
+ *   MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *   MCUX_CSSL_FP_CONDITIONAL_IMPL(!condition,
+ *     MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(someBranchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_BRANCH_DECL}
+ * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE}
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:     Identifier for the branch for which the positive scenario is
+ *                  executed.
+ *        - expect: Zero or more (comma separated) declarations of expected code
+ *                  flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_BRANCH_POSITIVE(...) \
+  MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_BRANCH_NEGATIVE
+ * @brief Negative scenario of a branch is executed.
+ * @api
+ * @ingroup csslFpBranch
+ *
+ * This branch event macro informs the flow mechanism that the positive scenario
+ * of the branch is executed for the branch declared by
+ * #MCUX_CSSL_FP_BRANCH_DECL with the given \p id. For example:
+ * @code
+ * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
+ * if (condition)
+ * {
+ *   MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
+ * }
+ * else
+ * {
+ *   MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *   MCUX_CSSL_FP_CONDITIONAL_IMPL(!condition,
+ *     MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(someBranchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_BRANCH_DECL}
+ * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE}
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:     Identifier for the branch for which the negative scenario is
+ *                  executed.
+ *        - expect: Zero or more (comma separated) declarations of expected code
+ *                  flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_BRANCH_NEGATIVE(...) \
+  MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE
+ * @brief Expectation that positive branch has been taken.
+ * @api
+ * @ingroup csslFpBranch
+ *
+ * This expectation macro indicates to the flow protection mechanism that the
+ * branch declared by #MCUX_CSSL_FP_BRANCH_DECL with the given \p id has
+ * executed the positive scenario (under the given \p condition). For example:
+ * @code
+ * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
+ * if (condition)
+ * {
+ *   MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
+ * }
+ * else
+ * {
+ *   MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *   // Providing the condition as part of the branch expectation.
+ *   // Alternatively, the expectation can be placed in a conditional block.
+ *   MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(someBranchIdentifier, condition)
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_BRANCH_DECL}
+ * @event{MCUX_CSSL_FP_BRANCH_POSITIVE}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ * @see MCUX_CSSL_FP_CONDITIONAL
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:        Identifier of the flow protected branch.
+ *        - condition: Optional, condition under which this branch is taken.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(...) \
+  MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE
+ * @brief Expectation that negative branch has been taken.
+ * @api
+ * @ingroup csslFpBranch
+ *
+ * This expectation macro indicates to the flow protection mechanism that the
+ * branch declared by #MCUX_CSSL_FP_BRANCH_DECL with the given \p id has
+ * executed the negative scenario (under the given \p condition). For example:
+ * @code
+ * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
+ * if (condition)
+ * {
+ *   MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
+ * }
+ * else
+ * {
+ *   MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
+ *   // Providing the branch expectation as part of a conditional block.
+ *   // Alternatively, the condition can be provided in the branch expectation.
+ *   MCUX_CSSL_FP_CONDITIONAL(!condition,
+ *     MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(someBranchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_BRANCH_DECL}
+ * @event{MCUX_CSSL_FP_BRANCH_NEGATIVE}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ * @see MCUX_CSSL_FP_CONDITIONAL
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:        Identifier of the flow protected branch.
+ *        - condition: Optional, condition under which this branch is taken.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(...) \
+  MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(__VA_ARGS__)
+
+
+
+/**
+ * @defgroup csslFpSwitch Switching flow protection
+ * @brief Support for flow protected switches.
+ * @ingroup mcuxCsslFlowProtection
+ *
+ * @declaration{MCUX_CSSL_FP_SWITCH_DECL}
+ * @event{MCUX_CSSL_FP_SWITCH_CASE,MCUX_CSSL_FP_SWITCH_DEFAULT}
+ * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN,MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT}
+ */
+
+/**
+ * @def MCUX_CSSL_FP_SWITCH_DECL
+ * @brief Declaration of a flow protected switch.
+ * @api
+ * @ingroup csslFpSwitch
+ *
+ * To inform the flow protection mechanism about a switch that needs to be
+ * protected, a switch identifier needs to be declared. This identifier can
+ * then be used in the events and expectation macros. For example:
+ * @code
+ * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
+ * switch (arg)
+ * {
+ *   case 0xC0DEu:
+ *   {
+ *     result = 0xC0DEu;
+ *     MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
+ *     break;
+ *   }
+ *   default:
+ *   {
+ *     result = 0;
+ *     MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
+ *     break;
+ *   }
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
+ *   // Option 1: provide the condition as part of the switch expectation.
+ *   MCUX_CSSL_FP_SWITCH_TAKEN(someSwitchIdentifier, 0xC0DEu, 0xC0DEu == arg),
+ *   // Option 2: place the switch expectation in a conditional block.
+ *   MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
+ *     MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @event{MCUX_CSSL_FP_SWITCH_CASE,MCUX_CSSL_FP_SWITCH_DEFAULT}
+ * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN,MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT}
+ *
+ * @param id Identifier for the switch that is flow protected.
+ */
+#define MCUX_CSSL_FP_SWITCH_DECL(id) \
+  MCUX_CSSL_FP_SWITCH_DECL_IMPL(id)
+
+/**
+ * @def MCUX_CSSL_FP_SWITCH_CASE
+ * @brief Case that is being handled from a switch.
+ * @api
+ * @ingroup csslFpSwitch
+ *
+ * This switch event macro informs the flow mechanism that the given \p case of
+ * the switch is executed for the switch declared by #MCUX_CSSL_FP_SWITCH_DECL
+ * with the given \p id. For example:
+ * @code
+ * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
+ * switch (arg)
+ * {
+ *   case 0xC0DEu:
+ *   {
+ *     result = 0xC0DEu;
+ *     MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
+ *     break;
+ *   }
+ *   default:
+ *   {
+ *     result = 0;
+ *     MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
+ *     break;
+ *   }
+ * }
+ * // ...
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
+ *   // Option 1: provide the condition as part of the switch expectation.
+ *   MCUX_CSSL_FP_SWITCH_TAKEN(someSwitchIdentifier, 0xC0DEu, 0xC0DEu == arg),
+ *   // Option 2: place the switch expectation in a conditional block.
+ *   MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
+ *     MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_SWITCH_DECL}
+ * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN}
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:     Identifier of the flow protected switch.
+ *        - case:   Case value that is chosen in the switch.
+ *        - expect: Zero or more (comma separated) declarations of expected code
+ *                  flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_SWITCH_CASE(...) \
+  MCUX_CSSL_FP_SWITCH_CASE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_SWITCH_DEFAULT
+ * @brief Case that is being handled from a switch.
+ * @api
+ * @ingroup csslFpSwitch
+ *
+ * This switch event macro informs the flow mechanism that the default case of
+ * the switch is executed for the switch declared by #MCUX_CSSL_FP_SWITCH_DECL
+ * with the given \p id. For example:
+ * @code
+ * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
+ * switch (arg)
+ * {
+ *   case 0xC0DEu:
+ *   {
+ *     result = 0xC0DEu;
+ *     MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
+ *     break;
+ *   }
+ *   default:
+ *   {
+ *     result = 0;
+ *     MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
+ *     break;
+ *   }
+ * }
+ *
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
+ *   // Option 1: provide the condition as part of the switch expectation.
+ *   MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg),
+ *   // Option 2: place the switch expectation in a conditional block.
+ *   MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
+ *     MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_SWITCH_DECL}
+ * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT}
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:     Identifier of the flow protected switch.
+ *        - expect: Zero or more (comma separated) declarations of expected code
+ *                  flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_SWITCH_DEFAULT(...) \
+  MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_SWITCH_TAKEN
+ * @brief Expected that a specific case is handled from a switch.
+ * @api
+ * @ingroup csslFpSwitch
+ *
+ * This expectation macro indicates to the flow protection mechanism that the
+ * switch declared by #MCUX_CSSL_FP_SWITCH_DECL with the given \p id has
+ * executed the \p case (under the given \p condition). For example:
+ * @code
+ * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
+ * switch (arg)
+ * {
+ *   case 0xC0DEu:
+ *   {
+ *     result = 0xC0DEu;
+ *     MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
+ *     break;
+ *   }
+ *   default:
+ *   {
+ *     result = 0;
+ *     MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
+ *     break;
+ *   }
+ * }
+ *
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
+ *   // Option 1: provide the condition as part of the switch expectation.
+ *   MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg),
+ *   // Option 2: place the switch expectation in a conditional block.
+ *   MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
+ *     MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_SWITCH_DECL}
+ * @event{MCUX_CSSL_FP_SWITCH_CASE}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:        Identifier of the flow protected switch.
+ *        - case:      Value of the case that is expected to be chosen in the
+ *                     switch.
+ *        - condition: Optional, condition under which the \p case is taken.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN(...) \
+  MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(__VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT
+ * @brief Expected that default case is handled from a switch.
+ * @api
+ * @ingroup csslFpSwitch
+ *
+ * This expectation macro indicates to the flow protection mechanism that the
+ * switch declared by #MCUX_CSSL_FP_SWITCH_DECL with the given \p id has
+ * executed the default case (under the given \p condition). For example:
+ * @code
+ * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
+ * switch (arg)
+ * {
+ *   case 0xC0DEu:
+ *   {
+ *     result = 0xC0DEu;
+ *     MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
+ *     break;
+ *   }
+ *   default:
+ *   {
+ *     result = 0;
+ *     MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
+ *     break;
+ *   }
+ * }
+ *
+ * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
+ *   // Option 1: provide the condition as part of the switch expectation.
+ *   MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg),
+ *   // Option 2: place the switch expectation in a conditional block.
+ *   MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
+ *     MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
+ *   )
+ * );
+ * @endcode
+ *
+ * @declaration{MCUX_CSSL_FP_SWITCH_DECL}
+ * @event{MCUX_CSSL_FP_SWITCH_DEFAULT}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - id:        Identifier of the flow protected switch.
+ *        - condition: Optional, condition under which the default case is taken.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(...) \
+  MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(__VA_ARGS__)
+
+
+
+/**
+ * @defgroup csslFpExpect Expectation handling
+ * @brief Expectation handling support functionality.
+ *
+ * @ingroup mcuxCsslFlowProtection
+ */
+
+/**
+ * @def MCUX_CSSL_FP_EXPECT
+ * @brief Declaration(s) of expected code flow behavior.
+ * @api
+ * @ingroup csslFpExpect
+ *
+ * This macro can be used to indicate expectations in the function body at
+ * another location than the function entry or exit.
+ *
+ * @note In general the use of this macro is discouraged, to avoid a potential
+ * security and/or code-size impact. However, it may be usefull for complex
+ * code, where an intermediate update can actually save code, since conditions
+ * for expectations can than be locallized.
+ *
+ * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED,MCUX_CSSL_FP_LOOP_ITERATIONS,MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE,MCUX_CSSL_FP_SWITCH_TAKEN}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_CONDITIONAL
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - expect: One or more (comma separated) declarations of expected code
+ *                  flow behavior.
+ */
+#define MCUX_CSSL_FP_EXPECT(...) \
+  MCUX_CSSL_FP_EXPECT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+/**
+ * @def MCUX_CSSL_FP_CONDITIONAL
+ * @brief Handling of conditionally expected code flow behavior.
+ * @api
+ * @ingroup csslFpExpect
+ *
+ * This macro can be used to indicate expectations that are only true under a
+ * given \p condition.
+ *
+ * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED,MCUX_CSSL_FP_LOOP_ITERATIONS,MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE,MCUX_CSSL_FP_SWITCH_TAKEN}
+ *
+ * @see MCUX_CSSL_FP_FUNCTION_ENTRY
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT
+ * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+ * @see MCUX_CSSL_FP_EXPECT
+ *
+ * @param condition Condition under which the given expectations apply.
+ * @param ...    One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ */
+#define MCUX_CSSL_FP_CONDITIONAL(condition, ...) \
+  MCUX_CSSL_FP_CONDITIONAL_IMPL((condition), __VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
+
+MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS()
+
+/**
+ * @def MCUX_CSSL_FP_ASSERT
+ * @brief Assert an expected state of the code flow.
+ * @api
+ * @ingroup csslFpExpect
+ *
+ * This macro can be used to check whether the code flow up to this point
+ * matches the expected state. Unlike the #MCUX_CSSL_FP_EXPECT macro, it will
+ * not update the expectations, but merely perform a check on the recorded
+ * events against the already recorded expectations plus the ones provided as
+ * parameters.
+ *
+ * If the check fails, the code defined in #MCUX_CSSL_FP_ASSERT_CALLBACK() will
+ * be executed.
+ *
+ * @note #MCUX_CSSL_FP_ASSERT_CALLBACK() must be defined before including the
+ * CSSL flow protection headers, otherwise a default implementation could be
+ * used.
+ *
+ * @see MCUX_CSSL_FP_EXPECT
+ *
+ * @param ...    The following parameters need to be passed (comma separated):
+ *        - expect: One or more (comma separated) declarations of expected code
+ *                  flow behavior.
+ */
+#define MCUX_CSSL_FP_ASSERT(...) \
+  MCUX_CSSL_FP_ASSERT_IMPL(__VA_ARGS__)
+
+#endif /* MCUX_CSSL_FLOW_PROTECTION_H_ */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Cfg.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Cfg.h
new file mode 100644
index 0000000000..ede3079fd6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Cfg.h
@@ -0,0 +1,55 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslFlowProtection_Cfg.h
+ * \brief Configuration of the implementation for the flow protection mechanism.
+ */
+
+#ifndef MCUX_CSSL_FLOW_PROTECTION_CFG_H_
+#define MCUX_CSSL_FLOW_PROTECTION_CFG_H_
+
+/**
+ * \addtogroup mcuxCsslCFG MCUX CSSL -- Configurations
+ *
+ * \defgroup mcuxCsslFlowProtection_CFG Flow Protection Configuration
+ * \brief Configuration options for the flow protection mechanism.
+ * \ingroup mcuxCsslCFG
+ */
+
+/**
+ * \def MCUX_CSSL_FP_USE_CODE_SIGNATURE
+ * \brief If set to 1, use the flow protection mechanism implementation based on
+ *        the Zen-V code signature HW mechanism.
+ * \ingroup mcuxCsslFlowProtection_CFG
+ */
+    #define MCUX_CSSL_FP_USE_CODE_SIGNATURE      0
+
+/**
+ * \def MCUX_CSSL_FP_USE_SECURE_COUNTER
+ * \brief If set to 1, use the flow protection mechanism implementation based on
+ *        the CSSL secure counter mechanism.
+ * \ingroup mcuxCsslFlowProtection_CFG
+ */
+    #define MCUX_CSSL_FP_USE_SECURE_COUNTER      1
+
+/**
+ * \def MCUX_CSSL_FP_USE_NONE
+ * \brief If set to 1, do not use the flow protection mechanism.
+ * \ingroup mcuxCsslFlowProtection_CFG
+ */
+    #define MCUX_CSSL_FP_USE_NONE      0
+
+/* Basic configuration sanity check */
+
+#endif /* MCUX_CSSL_FLOW_PROTECTION_CFG_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_FunctionIdentifiers.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_FunctionIdentifiers.h
new file mode 100644
index 0000000000..9d307f05a7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_FunctionIdentifiers.h
@@ -0,0 +1,129 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslFlowProtection_FunctionIdentifiers.h
+ * @brief Definition of function identifiers for the flow protection mechanism.
+ *
+ * @note This file might be post-processed to update the identifier values to
+ * proper/secure values.
+ */
+
+#ifndef MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
+#define MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
+
+/* Flow Protection example values: */
+#define MCUX_CSSL_FP_FUNCID_functionOnly0                     (0x50DDu)
+#define MCUX_CSSL_FP_FUNCID_functionOnly1                     (0x5595u)
+#define MCUX_CSSL_FP_FUNCID_functionOnly2                     (0x6B52u)
+#define MCUX_CSSL_FP_FUNCID_functionCall                      (0x50BBu)
+#define MCUX_CSSL_FP_FUNCID_functionCalls                     (0x4E71u)
+#define MCUX_CSSL_FP_FUNCID_functionLoop                      (0x4AF2u)
+#define MCUX_CSSL_FP_FUNCID_functionBranch                    (0x0D3Bu)
+#define MCUX_CSSL_FP_FUNCID_functionSwitch                    (0x22AFu)
+#define MCUX_CSSL_FP_FUNCID_functionComplex                   (0x781Bu)
+#define MCUX_CSSL_FP_FUNCID_data_invariant_memory_compare     (0x562Bu)
+#define MCUX_CSSL_FP_FUNCID_data_invariant_memory_copy        (0x4AA7u)
+#define MCUX_CSSL_FP_FUNCID_functionAssert                    (0x21DEu)
+/* Values for production use: */
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslParamIntegrity_Validate    (0x1AA7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Compare             (0x696Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Copy                (0x7D21u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Clear               (0x42D7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Set                 (0x44F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureClear         (0x29BCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCopy          (0x27AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureSet           (0x5B58u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCompare       (0x79C2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_DPASecureCompare    (0x5AF0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_DPASecComp      (0x629Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_CopyPow2        (0x53C3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_CopyWords       (0x3761u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecCopyPow2     (0x4A5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecComp         (0x187Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecClear        (0x2C3Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecSet          (0x6655u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXOR           (0x3366u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXORWithConst  (0x4A97u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_14                 (0x17C5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_15                 (0x1E8Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_16                 (0x26A7u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_17                 (0x14F9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_18                 (0x43E9u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_19                 (0x533Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_20                 (0x2EC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_21                 (0x7D44u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_22                 (0x2AE3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_23                 (0x7274u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_24                 (0x7CE0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_25                 (0x4DC5u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_26                 (0x3E94u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_27                 (0x75A4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_28                 (0x35E4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_29                 (0x63F0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_30                 (0x62BAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_31                 (0x7549u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_32                 (0x77C0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_33                 (0x662Eu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_34                 (0x521Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_35                 (0x6671u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_36                 (0x711Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_37                 (0x684Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_38                 (0x52EAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_39                 (0x1EACu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_40                 (0x4D66u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_41                 (0x4557u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_42                 (0x25F2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_43                 (0x278Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_44                 (0x3C55u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_45                 (0x1796u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_46                 (0x6732u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_47                 (0x67D0u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_48                 (0x5627u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_49                 (0x6AB1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_50                 (0x5927u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_51                 (0x51CEu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_52                 (0x7585u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_53                 (0x78B1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_54                 (0x0B5Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_55                 (0x6A87u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_56                 (0x19ABu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_57                 (0x57C1u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_58                 (0x589Du)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_59                 (0x61E3u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_60                 (0x0D2Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_61                 (0x5B1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_62                 (0x3CD4u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_63                 (0x0C6Fu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_64                 (0x21BDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_65                 (0x1D9Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_66                 (0x5674u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_67                 (0x60DDu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_68                 (0x78AAu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_69                 (0x0F36u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_70                 (0x6B2Au)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_71                 (0x2D63u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_72                 (0x2F16u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_73                 (0x4F1Cu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_74                 (0x5B83u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_75                 (0x7833u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_76                 (0x3B26u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_77                 (0x34DCu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_78                 (0x6E46u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_79                 (0x6F21u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_80                 (0x2937u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_81                 (0x1BE2u)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_82                 (0x2A9Bu)
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_83                 (0x78A3u)
+
+#endif /* MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Impl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Impl.h
new file mode 100644
index 0000000000..898c42c732
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Impl.h
@@ -0,0 +1,43 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2022 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslFlowProtection_Impl.h
+ * \brief Selection of the implementation for the flow protection mechanism.
+ */
+
+#ifndef MCUX_CSSL_FLOW_PROTECTION_IMPL_H_
+#define MCUX_CSSL_FLOW_PROTECTION_IMPL_H_
+
+/* Include the configuration for the flow protection mechanism. */
+#include <mcuxCsslFlowProtection_Cfg.h>
+
+/* Include the selected implementation of the flow protection mechanism. */
+#if defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && (1 == MCUX_CSSL_FP_USE_CODE_SIGNATURE)
+#  include <mcuxCsslFlowProtection_CodeSignature.h>
+#elif defined(MCUX_CSSL_FP_USE_SECURE_COUNTER) \
+      && (1 == MCUX_CSSL_FP_USE_SECURE_COUNTER)
+#  include <mcuxCsslSecureCounter_Cfg.h>
+#  include <mcuxCsslFlowProtection_SecureCounter_Common.h>
+#  if defined(MCUX_CSSL_SC_USE_SW_LOCAL) && (1 == MCUX_CSSL_SC_USE_SW_LOCAL)
+#    include <mcuxCsslFlowProtection_SecureCounter_Local.h>
+#  else
+#    include <mcuxCsslFlowProtection_SecureCounter_Global.h>
+#  endif
+#elif defined(MCUX_CSSL_FP_USE_NONE) && (1 == MCUX_CSSL_FP_USE_NONE)
+#  include <mcuxCsslFlowProtection_None.h>
+#else
+  #error "No flow protection implementation found/configured."
+#endif
+
+#endif /* MCUX_CSSL_FLOW_PROTECTION_IMPL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Common.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Common.h
new file mode 100644
index 0000000000..5b34950337
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Common.h
@@ -0,0 +1,1091 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslFlowProtection_SecureCounter_Common.h
+ * \brief Counter based implementation for the flow protection mechanism, for a local security counter.
+ */
+
+#ifndef MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_
+#define MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_
+
+/* Include the CSSL C pre-processor support functionality. */
+#include <mcuxCsslCPreProcessor.h>
+#include <mcuxCsslAnalysis.h>
+
+/* Include the CSSL secure counter mechanism as basic building block. */
+#include <mcuxCsslSecureCounter.h>
+
+/* Include the C99 standard integer types. */
+#include <stdint.h>
+
+/**
+ * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations
+ *
+ * \defgroup mcuxCsslFlowProtection_SecureCounter Flow Protection: Secure Counter
+ * \brief Secure counter based implementation for the flow protection mechanism.
+ * \ingroup mcuxCsslIMPL
+ */
+
+
+/**
+ * \defgroup csslFpCntCore Flow protection core functionality
+ * \brief Flow protection handling core functionality.
+ * \ingroup mcuxCsslFlowProtection_SecureCounter
+ *
+ * \todo Extend this description of the core functionality which relies
+ *       basically on the function calling flow protection.
+ *
+ * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL}
+ * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL}
+ * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL}
+ */
+
+/**
+ * \def MCUX_CSSL_FP_DECL_NAME
+ * \brief Construct a name based on type and id.
+ * \ingroup csslFpCntCore
+ *
+ * \param type Indicator for the type of declaration.
+ * \param id   Identifier for the flow protected entity.
+ * \return     CSSL flow protection entity name for given \p type and \p id.
+ */
+#define MCUX_CSSL_FP_DECL_NAME(type, id) \
+  MCUX_CSSL_CPP_CAT4(mcuxCsslFlowProtection_, type, _, id)
+
+/**
+ * \def MCUX_CSSL_FP_DECL_IMPL
+ * \brief Generic flow protected entity declaration implementation.
+ * \ingroup csslFpCntCore
+ *
+ * \param type Indicator for the type of declaration.
+ * \param id   Identifier for the flow protected entity.
+ * \return     CSSL flow protection entity declaration.
+ */
+#define MCUX_CSSL_FP_DECL_IMPL(type, id) \
+  MCUX_CSSL_SC_VALUE_TYPE MCUX_CSSL_FP_DECL_NAME(type, id) = \
+    MCUX_CSSL_CPP_CAT3(MCUX_CSSL_FP_, type, _ID)(id)
+
+/**
+ * \def MCUX_CSSL_FP_ID_IMPL
+ * \brief Generic identifier generator based on current line number.
+ * \ingroup csslFpCntCore
+ *
+ * \return Counter value based on the current line number.
+ */
+#define MCUX_CSSL_FP_ID_IMPL() \
+  MCUX_CSSL_CPP_CAT(__LINE__, u)
+
+
+
+/**
+ * \defgroup csslFpCntExpect Expectation handling
+ * \brief Expectation handling support functionality.
+ * \ingroup mcuxCsslFlowProtection_SecureCounter
+ */
+
+/**
+ * \def MCUX_CSSL_FP_EXPECTATIONS
+ * \brief Expectation aggregation.
+ * \ingroup csslFpCntExpect
+ *
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * \return       Aggregated counter value for the given expectations.
+ */
+#define MCUX_CSSL_FP_EXPECTATIONS(...) \
+  ((uint32_t) 0u + (MCUX_CSSL_CPP_MAP(MCUX_CSSL_CPP_ADD, __VA_ARGS__)))
+
+/**
+ * @def MCUX_CSSL_FP_COUNTER_STMT
+ * @brief A statement which is only evaluated if a secure counter is used.
+ * @api
+ * @ingroup csslFpCntCore
+ *
+ * This macro can be used to create counting variables that are only present if
+ * the active configuration uses a secure counter, to avoid warnings about
+ * unused variables.
+ *
+ * @param statement The statement to be conditionally included.
+ */
+#define MCUX_CSSL_FP_COUNTER_STMT_IMPL(statement) \
+  statement
+
+/**
+ * \def MCUX_CSSL_FP_CONDITIONAL_IMPL
+ * \brief Conditional expectation aggregation.
+ * \ingroup csslFpCntCore
+ *
+ * \param condition Condition under which the given expectations apply
+ * \param expect    One or more (comma separated) declarations of expected code
+ *                  code flow behavior.
+ * \return          Aggregated counter value for the given expectations, if
+ *                  condition is satisfied. Otherwise 0.
+ */
+#define MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, ...) \
+  (MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) & ((condition) ? ((uint32_t) UINT32_MAX) : ((uint32_t) 0)))
+
+/**
+ * @def MCUX_CSSL_FP_VOID_EXPECTATION_IMPL
+ * @brief Implementation of expectation of nothing
+ * @api
+ * @ingroup csslFpCntExpect
+ *
+ * This expectation macro indicates to the flow protection mechanism that nothing
+ * is expected to happen. This is mainly intended for internal use (to ensure at
+ * least one expectation is passed).
+ */
+#define MCUX_CSSL_FP_VOID_EXPECTATION_IMPL() \
+  (0u)
+
+/**
+ * \def MCUX_CSSL_FP_EXPECT_IMPL
+ * \brief Declaration(s) of expected code flow behavior.
+ * \ingroup csslFpCntExpect
+ *
+ * This macro can be used to indicate expectations in the function body at
+ * another location than the function entry or exit.
+ *
+ * \see MCUX_CSSL_FP_EXPECTATIONS
+ *
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ */
+#define MCUX_CSSL_FP_EXPECT_IMPL(...) \
+  MCUX_CSSL_SC_SUB( \
+    MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
+  )
+
+
+
+/**
+ * \defgroup csslFpCntFunction Function calling flow protection
+ * \brief Support for flow protected functions.
+ * \ingroup mcuxCsslFlowProtection_SecureCounter
+ *
+ * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL}
+ * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL}
+ * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL}
+ */
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ID
+ * \brief Generator for function identifiers.
+ * \ingroup csslFpCntFunction
+ *
+ * \param id Identifier for the flow protected function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ID(id) \
+  MCUX_CSSL_CPP_CAT(MCUX_CSSL_FP_FUNCID_, id)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK
+ * \brief Mask to be used to derive entry part from a function identifier
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK \
+  (0x5A5A5A5Au)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART
+ * \brief Part of the function identifier to be used at function entry.
+ * \ingroup csslFpCntFunction
+ *
+ * \param id Identifier for the flow protected function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id) \
+  (MCUX_CSSL_FP_FUNCTION_VALUE(id) & MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART
+ * \brief Part of the function identifier to be used at function exit.
+ * \ingroup csslFpCntFunction
+ *
+ * \param id Identifier for the flow protected function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \
+  (MCUX_CSSL_FP_FUNCTION_VALUE(id) - MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id))
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_DECL_IMPL
+ * \brief Declaration implementation of a flow protected function.
+ * \ingroup csslFpCntFunction
+ *
+ * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL}
+ * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL}
+ *
+ * @param id Identifier for the function that is flow protected.
+ * @param ptrType Optional, pointer type matching this function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_DECL_IMPL(...) \
+  /* Intentionally empty */
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_VALUE
+ * \brief Macro to get the value for a given function.
+ * \ingroup csslFpCntFunction
+ *
+ * \param id Identifier for the function that is flow protected.
+ * \return   The counter value for the given function \p id.
+ */
+#define MCUX_CSSL_FP_FUNCTION_VALUE(id) \
+  ((uint32_t) MCUX_CSSL_FP_FUNCTION_ID(id))
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_DEF_IMPL
+ * \brief Definition implementation of a flow protected function.
+ * \ingroup csslFpCntFunction
+ *
+ * Not used in the current implementation.
+ *
+ * @param id Identifier for the function that is flow protected.
+ * @param ptrType Optional, pointer type matching this function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_DEF_IMPL(...) \
+  /* Intentionally empty. */
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_POINTER_IMPL
+ * \brief Definition implementation of a flow protected function pointer.
+ * \ingroup csslFpNoneFunction
+ *
+ * @param type Identifier for the function pointer type that is flow protected.
+ * @param definition Actual type definition of the function pointer type.
+ */
+#define MCUX_CSSL_FP_FUNCTION_POINTER_IMPL(type, definition) \
+  definition
+
+/**
+ * \def MCUX_CSSL_FP_RESULT_OFFSET
+ * \brief Offset of the result in the return value.
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_RESULT_OFFSET \
+  (0u)
+
+/**
+ * \def MCUX_CSSL_FP_RESULT_MASK
+ * \brief Bitmask of the result in the return value.
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_RESULT_MASK \
+  (0xFFFFFFFFuLL)
+
+/**
+ * \def MCUX_CSSL_FP_RESULT_VALUE
+ * \brief Encode a result value for a protected return value.
+ * \ingroup csslFpCntFunction
+ *
+ * \param result The result that needs to be encoded.
+ */
+#define MCUX_CSSL_FP_RESULT_VALUE(result) \
+  (((uint64_t)(result) & MCUX_CSSL_FP_RESULT_MASK) << MCUX_CSSL_FP_RESULT_OFFSET)
+
+/**
+ * \def MCUX_CSSL_FP_RESULT_IMPL2
+ * \brief Extract the result value from a protected \p return value.
+ * \ingroup csslFpCntFunction
+ *
+ * \param type   Type of the result.
+ * \param return The protected return value which contains the result.
+ */
+#define MCUX_CSSL_FP_RESULT_IMPL2(type, return) \
+  ((type)(((return) >> MCUX_CSSL_FP_RESULT_OFFSET) & MCUX_CSSL_FP_RESULT_MASK))
+
+/**
+ * \def MCUX_CSSL_FP_RESULT_IMPL1
+ * \brief Extract the result value from a protected \p return value.
+ * \ingroup csslFpCntFunction
+ *
+ * \param return The protected return value which contains the result.
+ */
+#define MCUX_CSSL_FP_RESULT_IMPL1(return) \
+  MCUX_CSSL_FP_RESULT_IMPL2(uint32_t,return)
+
+/**
+ * \def MCUX_CSSL_FP_RESULT_IMPL
+ * \brief Extract the result value from a protected \p return value.
+ * \ingroup csslFpCntFunction
+ *
+ * \param type   Optional, type of the result.
+ * \param return The protected return value which contains the result.
+ */
+#define MCUX_CSSL_FP_RESULT_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_RESULT_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_PROTECTION_OFFSET
+ * \brief Offset of the protection token in the return value.
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_PROTECTION_OFFSET \
+  (32u)
+
+/**
+ * \def MCUX_CSSL_FP_PROTECTION_MASK
+ * \brief Bitmask of the protection token in the return value.
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_PROTECTION_MASK \
+  ((uint64_t) 0xFFFFFFFFuLL)
+
+/**
+ * \def MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE
+ * \brief Encode a protection token for a protected return value.
+ * \ingroup csslFpCntFunction
+ *
+ * Note that this macro is only used with a local security counter,
+ * e.g. for configuration CSSL_SC_USE_SW_LOCAL
+ *
+ * \param token The protection token that needs to be encoded.
+ */
+#define MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(token) \
+  ((((uint64_t)(token) & MCUX_CSSL_FP_PROTECTION_MASK)) << MCUX_CSSL_FP_PROTECTION_OFFSET)
+
+/**
+ * \def MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL
+ * \brief Extract the protection token value from a protected \p return value.
+ * \ingroup csslFpCntFunction
+ *
+ * Note that this macro is only used with a local security counter,
+ * e.g. for configuration CSSL_SC_USE_SW_LOCAL
+ *
+ * \param return The protected return value which contains the protection token.
+ */
+#define MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return) \
+  (uint32_t)(((return) >> MCUX_CSSL_FP_PROTECTION_OFFSET) & MCUX_CSSL_FP_PROTECTION_MASK)
+
+/**
+ * \def MCUX_CSSL_FP_COUNTER_COMPRESSED
+ * \brief Compressed version of the secure counter that can be used as a
+ *        protection token.
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_COUNTER_COMPRESSED() \
+  MCUX_CSSL_SC_VALUE()
+
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALLED_IMPL
+ * \brief Expectation implementation of a called function.
+ * \ingroup csslFpCntFunction
+ *
+ * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL}
+ * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL}
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_VALUE
+ *
+ * \param id Identifier of the function that is expected to be called.
+ * \return   Counter value for the given function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(id) \
+  MCUX_CSSL_FP_FUNCTION_VALUE(id)
+
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL
+ * \brief Expectation implementation of an entered (but not exited) function.
+ * \ingroup csslFpCntFunction
+ *
+ * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL}
+ * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL}
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_VALUE
+ *
+ * \param id Identifier of the function that is expected to be entered.
+ * \return   Counter value for the given function.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id) \
+  MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id)
+
+
+/**
+ * \defgroup csslFpCntLoop Looping flow protection
+ * \brief Support for flow protected loops.
+ * \ingroup mcuxCsslFlowProtection_SecureCounter
+ *
+ * \declaration{MCUX_CSSL_FP_LOOP_DECL_IMPL}
+ * \event{MCUX_CSSL_FP_LOOP_ITERATION_IMPL}
+ * \expectation{MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL}
+ */
+
+/**
+ * \def MCUX_CSSL_FP_LOOP_ID
+ * \brief Generator for loop identifiers.
+ * \ingroup csslFpCntLoop
+ *
+ * \param id Identifier for the flow protected loop.
+ * \return   Counter value for the given loop.
+ */
+#define MCUX_CSSL_FP_LOOP_ID(id) \
+  MCUX_CSSL_FP_ID_IMPL()
+
+/**
+ * \def MCUX_CSSL_FP_LOOP_DECL_IMPL
+ * \brief Declaration implementation of a flow protected loop.
+ * \ingroup csslFpCntLoop
+ *
+ * \param id Identifier for the loop that is flow protected.
+ */
+#define MCUX_CSSL_FP_LOOP_DECL_IMPL(id) \
+  MCUX_CSSL_FP_DECL_IMPL(LOOP, id)
+
+/**
+ * \def MCUX_CSSL_FP_LOOP_VALUE
+ * \brief Macro to get the value for a given loop.
+ * \ingroup csslFpCntLoop
+ *
+ * \param id Identifier for the loop that is flow protected.
+ * \return   The counter value for the given loop \p id.
+ */
+#define MCUX_CSSL_FP_LOOP_VALUE(id) \
+  MCUX_CSSL_FP_DECL_NAME(LOOP, id)
+
+/**
+ * \def MCUX_CSSL_FP_LOOP_ITERATION_IMPLn
+ * \brief Event implementation of a loop iteration (with expectations).
+ * \ingroup csslFpCntLoop
+ *
+ * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPL
+ *
+ * \param id     Identifier for the loop that is flow protected.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, ...) \
+  MCUX_CSSL_SC_ADD( \
+    MCUX_CSSL_FP_LOOP_VALUE(id) \
+    - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
+  )
+
+/**
+ * \def MCUX_CSSL_FP_LOOP_ITERATION_IMPL1
+ * \brief Event implementation of a loop iteration (without expectations).
+ * \ingroup csslFpCntLoop
+ *
+ * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPL
+ * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPLn
+ *
+ * \param id Identifier for the loop that is flow protected.
+ */
+#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL1(id) \
+  MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_LOOP_ITERATION_IMPL
+ * \brief Event implementation of a loop iteration.
+ * \ingroup csslFpCntLoop
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPL1
+ * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPLn
+ *
+ * \param id     Identifier for the loop that is flow protected.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_LOOP_ITERATION_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL
+ * \brief Expectation implementation of a number of loop iterations.
+ * \ingroup csslFpCntLoop
+ *
+ * \param id    Identifier of the flow protected loop.
+ * \param count Number of expected iterations.
+ */
+#define MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  ((count) * MCUX_CSSL_FP_LOOP_VALUE(id)) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+
+
+/**
+ * \defgroup csslFpCntBranch Branching flow protection
+ * \brief Support for flow protected branches.
+ * \ingroup mcuxCsslFlowProtection_SecureCounter
+ *
+ * \declaration{MCUX_CSSL_FP_BRANCH_DECL_IMPL}
+ * \event{MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL,MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL}
+ * \expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL}
+ */
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_ID
+ * \brief Generator for branch identifiers.
+ * \ingroup csslFpCntBranch
+ *
+ * \param id Identifier for the flow protected branch.
+ * \return   Counter value for the given branch.
+ */
+#define MCUX_CSSL_FP_BRANCH_ID(id) \
+  MCUX_CSSL_FP_ID_IMPL()
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_DECL_IMPL
+ * \brief Declaration implementation of a flow protected branch.
+ * \ingroup csslFpCntBranch
+ *
+ * \param id Identifier for the branch that is flow protected.
+ */
+#define MCUX_CSSL_FP_BRANCH_DECL_IMPL(id) \
+  MCUX_CSSL_FP_DECL_IMPL(BRANCH, id)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_VALUE
+ * \brief Macro to get the value for a given branch.
+ * \ingroup csslFpCntBranch
+ *
+ * \param id Identifier for the branch that is flow protected.
+ * \return   The counter value for the given branch \p id.
+ */
+#define MCUX_CSSL_FP_BRANCH_VALUE(id) \
+  MCUX_CSSL_FP_DECL_NAME(BRANCH, id)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE
+ * \brief Value to use for the positive scenario.
+ * \ingroup csslFpCntBranch
+ */
+#define MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE 0x5u
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE
+ * \brief Value to use for the negative scenario.
+ * \ingroup csslFpCntBranch
+ */
+#define MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE 0xAu
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL
+ * \brief Event implementation for the execution of a specified branch scenario.
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+ *
+ * \param id       Identifier for the branch for which the given \p scenario is
+ *                 executed.
+ * \param scenario The scenario for a branch is either positive or negative.
+ * \param expect   One or more (comma separated) declarations of expected code
+ *                 flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, scenario, ...) \
+  MCUX_CSSL_SC_ADD( \
+    (MCUX_CSSL_FP_BRANCH_VALUE(id) * (scenario)) \
+    - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
+  )
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn
+ * \brief Event implementation for the execution of a positive branch scenario
+ *        (with expectations).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1
+ *
+ * \param id     Identifier for the branch for which the positive scenario is
+ *               executed.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn(id, ...) \
+  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, \
+    __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1
+ * \brief Event implementation for the execution of a positive branch scenario
+ *        (without expectations).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn
+ *
+ * \param id Identifier for the branch for which the positive scenario is
+ *           executed.
+ */
+#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1(id) \
+  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+ * \brief Event implementation for the execution of a positive branch scenario.
+ * \ingroup csslFpCntBranch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1
+ * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn
+ *
+ * \param id     Identifier for the branch for which the positive scenario is
+ *               executed.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn
+ * \brief Event implementation for the execution of a negative branch scenario
+ *        (with expectations).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1
+ *
+ * \param id     Identifier for the branch for which the negative scenario is
+ *               executed.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn(id, ...) \
+  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, \
+    __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1
+ * \brief Event implementation for the execution of a negative branch scenario
+ *        (without expectations).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn
+ *
+ * \param id Identifier for the branch for which the negative scenario is
+ *           executed.
+ */
+#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1(id) \
+  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+ * \brief Event implementation for the execution of a negative branch scenario.
+ * \ingroup csslFpCntBranch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1
+ * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn
+ *
+ * \param id     Identifier for the branch for which the negative scenario is
+ *               executed.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_TAKEN_IMPL
+ * \brief Expectation implementation of an executed specified branch scenario.
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+ *
+ * \param id        Identifier of the flow protected branch.
+ * \param scenario The scenario for a branch is either positive or negative.
+ * \param condition Condition under which this branch is taken.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, scenario, condition) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, \
+    MCUX_CSSL_FP_BRANCH_VALUE(id) * (scenario)) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2
+ * \brief Expectation implementation of an executed positive branch (with
+ *        condition).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1
+ *
+ * \param id        Identifier of the flow protected branch.
+ * \param condition Condition under which this branch is taken.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2(id, condition) \
+  MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, condition)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1
+ * \brief Expectation implementation of an executed positive branch (without
+ *        condition).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2
+ *
+ * \param id Identifier of the flow protected branch.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1(id) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1, "True is of boolean type.") \
+    MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, true) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+ * \brief Expectation implementation of an executed positive branch.
+ * \ingroup csslFpCntBranch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2
+ *
+ * \param id        Identifier of the flow protected branch.
+ * \param condition Optional, condition under which this branch is taken.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2
+ * \brief Expectation implementation of an executed negative branch (with
+ *        condition).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1
+ *
+ * \param id        Identifier of the flow protected branch.
+ * \param condition Condition under which this branch is taken.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2(id, condition) \
+  MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, condition)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1
+ * \brief Expectation implementation of an executed negative branch (without
+ *        condition).
+ * \ingroup csslFpCntBranch
+ *
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2
+ *
+ * \param id Identifier of the flow protected branch.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1(id) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1, "True is of boolean type.") \
+    MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, true) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
+
+/**
+ * \def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+ * \brief Expectation implementation of an executed negative branch.
+ * \ingroup csslFpCntBranch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1
+ * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2
+ *
+ * \param id        Identifier of the flow protected branch.
+ * \param condition Optional, condition under which this branch is taken.
+ */
+#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL, __VA_ARGS__)
+
+
+
+/**
+ * \defgroup csslFpCntSwitch Switching flow protection
+ * \brief Support for flow protected switches.
+ * \ingroup mcuxCsslFlowProtection_SecureCounter
+ *
+ * \declaration{MCUX_CSSL_FP_SWITCH_DECL_IMPL}
+ * \event{MCUX_CSSL_FP_SWITCH_CASE_IMPL,MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL}
+ * \expectation{MCUX_CSSL_FP_SWITCH_TAKEN_IMPL,MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL}
+ */
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_ID
+ * \brief Generator for switch identifiers.
+ * \ingroup csslFpCntSwitch
+ *
+ * \param id Identifier for the flow protected switch.
+ * \return   Counter value for the given loop.
+ */
+#define MCUX_CSSL_FP_SWITCH_ID(id) \
+  MCUX_CSSL_FP_ID_IMPL()
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_DECL_IMPL
+ * \brief Declaration implementation of a flow protected switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \param id Identifier for the switch that is flow protected.
+ */
+#define MCUX_CSSL_FP_SWITCH_DECL_IMPL(id) \
+    MCUX_CSSL_FP_DECL_IMPL(SWITCH, id)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_VALUE
+ * \brief Macro to get the value for a given switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \param id Identifier for the switch that is flow protected.
+ * \return   The counter value for the given switch \p id.
+ */
+#define MCUX_CSSL_FP_SWITCH_VALUE(id) \
+  MCUX_CSSL_FP_DECL_NAME(SWITCH, id)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_CASE_IMPLn
+ * \brief Case that is being handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL2
+ *
+ * \param id     Identifier of the flow protected switch.
+ * \param case   Case value that is chosen in the switch.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, ...) \
+  MCUX_CSSL_SC_ADD( \
+    (MCUX_CSSL_FP_SWITCH_VALUE(id) * (case)) \
+    - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
+  )
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_CASE_IMPL2
+ * \brief Case that is being handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_CASE_IMPLn
+ *
+ * \param id   Identifier of the flow protected switch.
+ * \param case Case value that is chosen in the switch.
+ */
+#define MCUX_CSSL_FP_SWITCH_CASE_IMPL2(id, case) \
+  MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_CASE_IMPL
+ * \brief Case that is being handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL2
+ * \see MCUX_CSSL_FP_SWITCH_CASE_IMPLn
+ *
+ * \param id     Identifier of the flow protected switch.
+ * \param case   Case value that is chosen in the switch.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_SWITCH_CASE_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_SWITCH_CASE_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE
+ * \brief Value to use for default case.
+ * \ingroup csslFpCntSwitch
+ */
+#define MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE \
+  (0xDEFAu)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn
+ * \brief Case that is being handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1
+ *
+ * \param id     Identifier of the flow protected switch.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, ...) \
+  MCUX_CSSL_FP_SWITCH_CASE_IMPLn( \
+    id, MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1
+ * \brief Case that is being handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn
+ *
+ * \param id Identifier of the flow protected switch.
+ */
+#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1(id) \
+  MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, 0u) \
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL
+ * \brief Case that is being handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1
+ * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn
+ *
+ * \param id     Identifier of the flow protected switch.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior related to this event.
+ */
+#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3
+ * \brief Expected that a specific case is handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2
+ *
+ * \param id        Identifier of the flow protected switch.
+ * \param case      Value of the case that is expected to be chosen in the
+ *                  switch.
+ * \param condition Optional, condition under which the \p case is taken.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, condition) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, \
+    MCUX_CSSL_FP_SWITCH_VALUE(id) * (case)) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2
+ * \brief Expected that a specific case is handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3
+ *
+ * \param id   Identifier of the flow protected switch.
+ * \param case Value of the case that is expected to be chosen in the switch.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2(id, case) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1, "True is of boolean type.") \
+    MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, true) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_TAKEN_IMPL
+ * \brief Expected that a specific case is handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3
+ *
+ * \param id        Identifier of the flow protected switch.
+ * \param case      Value of the case that is expected to be chosen in the
+ *                  switch.
+ * \param condition Optional, condition under which the \p case is taken.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED3(MCUX_CSSL_FP_SWITCH_TAKEN_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2
+ * \brief Expected that default case is handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1
+ *
+ * \param id        Identifier of the flow protected switch.
+ * \param condition Condition under which the default case is taken.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, condition) \
+  MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE, condition)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1
+ * \brief Expected that default case is handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2
+ *
+ * \param id        Identifier of the flow protected switch.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1(id) \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
+  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1, "True is of boolean type.") \
+    MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, true) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_1) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
+  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
+
+/**
+ * \def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL
+ * \brief Expected that default case is handled from a switch.
+ * \ingroup csslFpCntSwitch
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1
+ * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2
+ *
+ * \param id        Identifier of the flow protected switch.
+ * \param condition Optional, condition under which the default case is taken.
+ */
+#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL, __VA_ARGS__)
+
+/**
+ * @def MCUX_CSSL_FP_ASSERT_CALLBACK
+ * @brief Fallback assert callback implementation.
+ * @api
+ * @ingroup csslFpCntExpect
+ *
+ * This macro will be executed if an #MCUX_CSSL_FP_ASSERT fails. In general this
+ * behavior should be defined by the user. This implementation is only in place
+ * to ensure that an implementation is always available.
+ *
+ * This is implemented a division by 0, which should trigger a compiler warning
+ * when used, to inform the user that the default implementation is used.
+ * Additionally, when still used at run-time it should trigger some system
+ * exception.
+ *
+ * \see MCUX_CSSL_FP_ASSERT
+ */
+#ifndef MCUX_CSSL_FP_ASSERT_CALLBACK
+  #define MCUX_CSSL_FP_ASSERT_CALLBACK() \
+    return 1/0 /* Fallback ASSERT callback is used, please provide your own. */
+#endif
+
+#endif /* MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Local.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Local.h
new file mode 100644
index 0000000000..a8a51531e8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Local.h
@@ -0,0 +1,497 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslFlowProtection_SecureCounter_Local.h
+ * \brief Counter based implementation for the flow protection mechanism, for a local security counter.
+ */
+
+#ifndef MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_
+#define MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_
+
+/* Include the CSSL C pre-processor support functionality. */
+#include <mcuxCsslCPreProcessor.h>
+
+/* Include the CSSL secure counter mechanism as basic building block. */
+#include <mcuxCsslSecureCounter.h>
+
+/* Include the C99 standard integer types. */
+#include <stdint.h>
+
+/* Include standard boolean types */
+#include <stdbool.h>
+
+
+/**
+ * \def MCUX_CSSL_FP_PROTECTED_TYPE_IMPL
+ * \brief Based on a given base type, builds a return type with flow
+ *        protection.
+ * \ingroup csslFpCntFunction
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_DEF_IMPL
+ *
+ * \param resultType The type to be converted into a protected type.
+ */
+#define MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType) \
+  uint64_t
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn
+ * \brief Flow protection handler implementation for the function entry point.
+ * \ingroup csslFpCntFunction
+ *
+ * Initialize the counter with the entry part of the function identifier, and
+ * include expectations in the initialization value.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL
+ *
+ * \param id     Identifier of the function that has just been entered.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, ...) \
+  MCUX_CSSL_SC_INIT( \
+    MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(function) \
+    - (MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__)) \
+  )
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1
+ * \brief Flow protection handler implementation for the function entry point.
+ * \ingroup csslFpCntFunction
+ *
+ * Initialize the counter with the entry part of the function identifier,
+ * without any potential expectations.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL
+ *
+ * \param id Identifier of the function that has just been entered.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1(function) \
+  MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL
+ * \brief Flow protection handler implementation for the function entry point.
+ * \ingroup csslFpCntFunction
+ *
+ * Initialize the counter with entry part of the function identifier, and
+ * include potential expectations in the initialization value.
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1
+ * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn
+ *
+ * \param id     Identifier of the function that has just been entered.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior.
+ */
+#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL, __VA_ARGS__)
+
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn
+ * \brief Flow protection handler implementation for the function exit point.
+ * \ingroup csslFpCntFunction
+ *
+ * Adjust the counter with the exit part of the function identifier, and
+ * include potential expectations in the adjustment value. Return the counter
+ * value together with the \p result via the function return value.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param result Result that should be encoded in the return value.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * \return       A value in which both \p result and a flow protection token
+ *               are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, ...) \
+  MCUX_CSSL_SC_ADD( \
+    MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \
+    - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
+  ); \
+  return (MCUX_CSSL_FP_RESULT_VALUE(result) \
+    | MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(MCUX_CSSL_FP_COUNTER_COMPRESSED()))
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1
+ * \brief Flow protection handler implementation for the function exit point.
+ * \ingroup csslFpCntFunction
+ *
+ * Adjust the counter with the exit part of the function identifier, without
+ * any potential expectations in the adjustment value. Return the counter value
+ * via the function return value.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL
+ *
+ * \param id Identifier of the function from which we will exit.
+ * \return   A value in which a flow protection token is encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1(id) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, 0u, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2
+ * \brief Flow protection handler implementation for the function exit point.
+ * \ingroup csslFpCntFunction
+ *
+ * Adjust the counter with the exit part of the function identifier, without
+ * any potential expectations in the adjustment value. Return the counter value
+ * together with the \p result via the function return value.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param result Result that should be encoded in the return value.
+ * \return       A value in which both \p result and a flow protection token
+ *               are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2(id, result) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPL
+ * \brief Flow protection handler implementation for the function exit point.
+ * \ingroup csslFpCntFunction
+ *
+ * Adjust the counter with the exit part of the function identifier, and
+ * include potential expectations in the adjustment value. Return the counter
+ * value together with the \p result via the function return value.
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param result Result that should be encoded in the return value.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * \return       A value in which both \p result and a flow protection token
+ *               are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_FUNCTION_EXIT_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn
+ * \brief Flow protection handler implementation for the function exit point
+ *        which includes an actual check of the code flow.
+ * \ingroup csslFpCntFunction
+ *
+ * Adjust the counter with the exit part of the function identifier, and
+ * include potential expectations in the adjustment value. Check whether the
+ * counter matches the expected value, and choose the result from \p pass and
+ * \p fail and return it together with the counter value via the function
+ * return value.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param pass   Result that should be encoded in the return value if the flow
+ *               protection check passed.
+ * \param fail   Result that should be encoded in the return value if the flow
+ *               protection check failed.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * \return       A value in which both the result (either \p pass or \p fail)
+ *               and a flow protection token are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, ...) \
+  MCUX_CSSL_SC_ADD( \
+    MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \
+    - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
+  ); \
+  return (MCUX_CSSL_FP_RESULT_VALUE( \
+    (MCUX_CSSL_SC_CHECK_PASSED == \
+        MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_FUNCTION_VALUE(id))) \
+    ? pass : fail) \
+    | MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(MCUX_CSSL_FP_COUNTER_COMPRESSED()))
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3
+ * \brief Flow protection handler implementation for the function exit point
+ *        which includes an actual check of the code flow.
+ * \ingroup csslFpCntFunction
+ *
+ * Adjust the counter with the exit part of the function identifier. Check
+ * whether the counter matches the expected value, and choose the result from
+ * \p pass and \p fail and return it together with the counter value via the
+ * function return value.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param pass   Result that should be encoded in the return value if the flow
+ *               protection check passed.
+ * \param fail   Result that should be encoded in the return value if the flow
+ *               protection check failed.
+ * \return       A value in which both the result (either \p pass or \p fail)
+ *               and a flow protection token are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3(id, pass, fail) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, 0u)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL
+ * \brief Flow protection handler implementation for the function exit point
+ *        which includes an actual check of the code flow.
+ * \ingroup csslFpCntFunction
+ *
+ * Adjust the counter with the exit part of the function identifier, and
+ * include potential expectations in the adjustment value. Check whether the
+ * counter matches the expected value, and choose the result from \p pass and
+ * \p fail and return it together with the counter value via the function
+ * return value.
+ *
+ * Implemented as an overloaded macro to simplify the use of the API.
+ *
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3
+ * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param pass   Result that should be encoded in the return value if the flow
+ *               protection check passed.
+ * \param fail   Result that should be encoded in the return value if the flow
+ *               protection check failed.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * \return       A value in which both the result (either \p pass or \p fail)
+ *               and a flow protection token are encoded.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED3(MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1
+ * \brief Flow protection handler for the exit point of functions with the
+ *        return type \c void.
+ * \ingroup csslFpCntFunction
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \return       A protected return value of type void.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1(id) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(id, 0U)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL2
+ * \brief Flow protection handler for the exit point of functions with the
+ *        return type \c void.
+ * \ingroup csslFpCntFunction
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * \return       A protected return value of type void.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPLn(id, ...) \
+  MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(id, 0U, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL
+ * \brief Flow protection handler for the exit point of functions with the
+ *        return type \c void.
+ * \ingroup csslFpCntFunction
+ *
+ * \param id     Identifier of the function from which we will exit.
+ * \param expect Zero or more (comma separated) declarations of expected code
+ *               flow behavior.
+ * \return       A protected return value of type void.
+ */
+#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_IMPL3
+ * \brief Event implementation of a flow protected function call.
+ * \ingroup csslFpCntFunction
+ *
+ * \param type   Type of the \p result variable.
+ * \param result Fresh variable name to store the result of \p call.
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_IMPL3(type, result, call) \
+  const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \
+  MCUX_CSSL_SC_ADD_ON_CALL( \
+    MCUX_CSSL_FP_PROTECTION_TOKEN(MCUX_CSSL_CPP_CAT(result, _protected))); \
+  type const result = MCUX_CSSL_FP_RESULT(type, \
+    MCUX_CSSL_CPP_CAT(result, _protected))
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_IMPL2
+ * \brief Event implementation of a flow protected function call.
+ * \ingroup csslFpCntFunction
+ *
+ * \param result Fresh variable name to store the result of \p call.
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_IMPL2(result, call) \
+  MCUX_CSSL_FP_FUNCTION_CALL_IMPL3(uint32_t, result, call)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_IMPL
+ * \brief Event implementation of a flow protected function call.
+ * \ingroup csslFpCntFunction
+ *
+ * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL}
+ * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL}
+ *
+ * \param type   Optional, type of the \p result variable.
+ * \param result Fresh variable name to store the result of \p call.
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_IMPL(...) \
+  MCUX_CSSL_CPP_OVERLOADED3(MCUX_CSSL_FP_FUNCTION_CALL_IMPL, __VA_ARGS__)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL
+ * \brief Event implementation of a flow protected void function call.
+ * \ingroup csslFpCntFunction
+ *
+ * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL}
+ * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL}
+ *
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL(call) \
+  { \
+  const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \
+  MCUX_CSSL_SC_ADD_ON_CALL( \
+    MCUX_CSSL_FP_PROTECTION_TOKEN(MCUX_CSSL_CPP_CAT(result, _protected))); \
+  }
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL
+ * \brief Implementation of a flow protected function call meant to be used
+ *        from within an unprotected function
+ * \ingroup csslFpCntFunction
+ *
+ *
+ * \param result Fresh variable name to store the result of \p call.
+ * \param token  Fresh variable name to store the protection token of \p call.
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call) \
+  const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \
+  const uint32_t token = MCUX_CSSL_FP_PROTECTION_TOKEN( \
+    MCUX_CSSL_CPP_CAT(result, _protected)); \
+  const uint32_t result = MCUX_CSSL_FP_RESULT( \
+    MCUX_CSSL_CPP_CAT(result, _protected))
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL
+ * \brief Implementation of a flow protected void function call meant to be
+ *        used from within an unprotected function
+ * \ingroup csslFpCntFunction
+ *
+ *
+ * \param token  Fresh variable name to store the protection token of \p call.
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call) \
+  const uint64_t MCUX_CSSL_CPP_CAT(token, _protected) = (call); \
+  const uint32_t token = MCUX_CSSL_FP_PROTECTION_TOKEN( \
+    MCUX_CSSL_CPP_CAT(token, _protected));
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL
+ * \brief Implementation of a flow protected function call meant to be used
+ *        from within an unprotected function, that must be terminated by
+ *        #MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL.
+ * \ingroup csslFpCntFunction
+ *
+ *
+ * \param result Fresh variable name to store the result of \p call.
+ * \param token  Fresh variable name to store the protection token of \p call.
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(result, token, call)   \
+do                                                                  \
+{                                                                   \
+    MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL
+ * \brief Implementation of the end of a section started by
+ * #MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL.
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL() \
+} while (false)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL
+ * \brief Implementation of a flow protected void function call meant to be used
+ *        from within an unprotected function, that must be terminated by
+ *        #MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL.
+ * \ingroup csslFpCntFunction
+ *
+ *
+ * \param token  Fresh variable name to store the protection token of \p call.
+ * \param call   The (protected) function call that must be performed.
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(token, call)   \
+do                                                                  \
+{                                                                   \
+    MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call)
+
+/**
+ * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL
+ * \brief Implementation of the end of a section started by
+ * #MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL.
+ * \ingroup csslFpCntFunction
+ */
+#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL() \
+} while (false)
+
+/**
+ * @def MCUX_CSSL_FP_ASSERT_IMPL
+ * @brief Assert an expected state of the code flow.
+ * @api
+ * @ingroup csslFpCntExpect
+ *
+ * This macro can be used to check whether the code flow up to this point
+ * matches the expected state. Unlike the #MCUX_CSSL_FP_EXPECT macro, it will
+ * not update the expectations, but merely perform a check on the recorded
+ * events against the already recorded expectations plus the ones provided as
+ * parameters.
+ *
+ * If the check fails, the code defined in MCUX_CSSL_FP_ASSERT_CALLBACK will be
+ * executed.
+ *
+ * \see MCUX_CSSL_FP_EXPECTATIONS
+ *
+ * \param expect One or more (comma separated) declarations of expected code
+ *               flow behavior.
+ */
+#define MCUX_CSSL_FP_ASSERT_IMPL(...) \
+  if (MCUX_CSSL_SC_CHECK_PASSED != \
+        MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__))) \
+  { \
+    MCUX_CSSL_FP_ASSERT_CALLBACK(); \
+  } \
+  else if (MCUX_CSSL_SC_CHECK_PASSED != \
+        MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__))) \
+  { \
+    MCUX_CSSL_FP_ASSERT_CALLBACK(); \
+  } \
+  else {/*empty*/}
+
+#endif /* MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Compare_asm.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Compare_asm.h
new file mode 100644
index 0000000000..cfafa1559a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Compare_asm.h
@@ -0,0 +1,171 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2022 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Internal_Compare_asm.h
+ * @brief Internal header of mcuxCsslMemory_Compare inline-asm macro
+ */
+
+
+#ifndef MCUXCSSLMEMORY_INTERNAL_COMPARE_ASM_H_
+#define MCUXCSSLMEMORY_INTERNAL_COMPARE_ASM_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+#if defined(__ghs__) || defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__)
+
+
+#define MCUXCSSLMEMORY_COMPARE_ASM_COMPARISON(retval_, cur_lhs_, cur_rhs_, nwords_, cnt_, notValid_, result_) \
+do{  \
+    uint32_t dat_lhs, dat_rhs;  \
+    __asm volatile (  \
+        "EOR    %[_retval], %[_result], %[_notValid]\n" /* retval should now be 0xFFFFFFFF */\
+        "LSRS   %[_nwords], %[_cnt], #2\n"                \
+        "CMP    %[_nwords], #0\n"                         \
+        "BGT    mcuxCsslMemory_Compare_word_loop\n"        \
+        "BEQ    mcuxCsslMemory_Compare_word_loop_end\n"    \
+        "B      mcuxCsslMemory_Compare_fault\n"            \
+        "mcuxCsslMemory_Compare_word_loop:\n"              \
+        "LDR    %[_dat_lhs], [%[_cur_lhs]], #+4\n"        \
+        "LDR    %[_dat_rhs], [%[_cur_rhs]], #+4\n"        \
+        "SUBS   %[_cnt], %[_cnt], #+4\n"                  \
+        "EORS   %[_dat_lhs], %[_dat_lhs], %[_dat_rhs]\n"  \
+        "BICS   %[_retval], %[_retval], %[_dat_lhs]\n"    \
+        "SUBS   %[_nwords], %[_nwords], #+1\n"            \
+        "MVN    %[_dat_rhs], %[_dat_lhs]\n"               \
+        "AND    %[_retval], %[_retval], %[_dat_rhs]\n"    \
+        "BNE     mcuxCsslMemory_Compare_word_loop\n"       \
+        "mcuxCsslMemory_Compare_word_loop_end:\n"          \
+        "MOVS   %[_dat_lhs], #0\n"                        \
+        "MOVS   %[_dat_rhs], #0\n"                        \
+        "CMP    %[_cnt], #0\n"                            \
+        "BGT    mcuxCsslMemory_Compare_byte_loop\n"        \
+        "BEQ    mcuxCsslMemory_Compare_fault\n"            \
+        "mcuxCsslMemory_Compare_byte_loop:\n"              \
+        "LDRB   %[_dat_lhs], [%[_cur_lhs]], #+1\n"        \
+        "LDRB   %[_dat_rhs], [%[_cur_rhs]], #+1\n"        \
+        "EORS   %[_dat_lhs], %[_dat_lhs], %[_dat_rhs]\n"  \
+        "BICS   %[_retval], %[_retval], %[_dat_lhs]\n"    \
+        "SUBS   %[_cnt], %[_cnt], #+1\n"                  \
+        "MVN    %[_dat_rhs], %[_dat_lhs]\n"               \
+        "AND    %[_retval], %[_retval], %[_dat_rhs]\n"    \
+        "BNE    mcuxCsslMemory_Compare_byte_loop\n"        \
+        "mcuxCsslMemory_Compare_fault:\n"                  \
+        : [_retval] "=r" (retval_),    \
+          [_cur_lhs] "+r" (cur_lhs_),  \
+          [_cur_rhs] "+r" (cur_rhs_),  \
+          [_cnt] "+r" (cnt_),          \
+          [_nwords] "+r" (nwords_),    \
+          [_dat_lhs] "=r" (dat_lhs),   \
+          [_dat_rhs] "=r" (dat_rhs)    \
+        : [_notValid] "r" (notValid_), \
+          [_result] "r" (result_)      \
+    );  \
+    (void)dat_lhs;  \
+    (void)dat_rhs;  \
+    (void)cnt_;     \
+    (void)notValid_;  \
+}while(false)
+
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+#define MCUXCSSLMEMORY_COMPARE_ASM_COMPARISON(retval_, cur_lhs_, cur_rhs_, nwords_, cnt_, notValid_, result_) \
+do{  \
+    uint32_t dat_lhs, dat_rhs;  \
+    __asm {  \
+        EOR    retval_, result_, notValid_;  \
+        LSRS   nwords_, cnt_, 2;  \
+        CMP    nwords_, 0;  \
+        BGT    mcuxCsslMemory_Compare_word_loop;  \
+        BEQ    mcuxCsslMemory_Compare_word_loop_end;  \
+        B      mcuxCsslMemory_Compare_fault;  \
+mcuxCsslMemory_Compare_word_loop:  \
+        LDR    dat_lhs, [cur_lhs_], +4;  \
+        LDR    dat_rhs, [cur_rhs_], +4;  \
+        SUBS   cnt_, cnt_, 4;  \
+        EORS   dat_lhs, dat_lhs, dat_rhs;  \
+        BICS   retval_, retval_, dat_lhs;  \
+        SUBS   nwords_, nwords_, 1;  \
+        MVN    dat_rhs, dat_lhs;  \
+        AND    retval_, retval_, dat_rhs;  \
+        BNE    mcuxCsslMemory_Compare_word_loop;  \
+mcuxCsslMemory_Compare_word_loop_end:  \
+        MOVS   dat_lhs, 0;  \
+        MOVS   dat_rhs, 0;  \
+        CMP    cnt_, 0;  \
+        BGT    mcuxCsslMemory_Compare_byte_loop;  \
+        BEQ    mcuxCsslMemory_Compare_fault;  \
+mcuxCsslMemory_Compare_byte_loop:  \
+        LDRB   dat_lhs, [cur_lhs_], +1;  \
+        LDRB   dat_rhs, [cur_rhs_], +1;  \
+        EORS   dat_lhs, dat_lhs, dat_rhs;  \
+        BICS   retval_, retval_, dat_lhs;  \
+        SUBS   cnt_, cnt_, 1;  \
+        MVN    dat_rhs, dat_lhs;  \
+        AND    retval_, retval_, dat_rhs;  \
+        BNE    mcuxCsslMemory_Compare_byte_loop;  \
+mcuxCsslMemory_Compare_fault:  \
+    }  \
+    (void)dat_lhs;  \
+    (void)dat_rhs;  \
+    (void)cnt_;  \
+    (void)notValid_;  \
+}while(false)
+
+#else
+    #error Unsupported compiler. The above section must be manually adapted to support your compiler inline assembly syntax.
+#endif
+
+
+/* If the binary representation of retval contains a zero,
+ * this sequence of instructions will turn retval to zero completely.
+ * If retval is 0xFFFFFFFF, it will remain untouched.
+ */
+#if defined(__ghs__) || defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__)
+#define MCUXCSSLMEMORY_COMPARE_ASM_CALC_RETVAL(retval_, errCode_)  \
+do{  \
+    __asm volatile (  \
+        "and %[_retval], %[_retval], %[_retval], ror  #1\n"  \
+        "and %[_retval], %[_retval], %[_retval], ror  #2\n"  \
+        "and %[_retval], %[_retval], %[_retval], ror  #4\n"  \
+        "and %[_retval], %[_retval], %[_retval], ror  #8\n"  \
+        "and %[_retval], %[_retval], %[_retval], ror #16\n"  \
+        "eor %[_retval], %[_retval], %[_errCode]\n"  \
+        : [_retval] "+r" (retval_)  \
+        : [_errCode] "r" (errCode_)  \
+    );  \
+    (void)errCode_;  \
+}while(false)
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+#define MCUXCSSLMEMORY_COMPARE_ASM_CALC_RETVAL(retval_, errCode_)  \
+do{  \
+    __asm {  \
+        AND retval_, retval_, retval_, ror 1;  \
+        AND retval_, retval_, retval_, ror 2;  \
+        AND retval_, retval_, retval_, ror 4;  \
+        AND retval_, retval_, retval_, ror 8;  \
+        AND retval_, retval_, retval_, ror 16;  \
+        EOR retval_, retval_, errCode_;  \
+    }  \
+    (void)errCode_;  \
+}while(false)
+
+#else
+    #error Unsupported compiler. The above section must be manually adapted to support your compiler inline assembly syntax.
+#endif
+
+
+#endif /* MCUXCSSLMEMORY_INTERNAL_COMPARE_ASM_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Copy_asm.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Copy_asm.h
new file mode 100644
index 0000000000..6f7c681ce7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Copy_asm.h
@@ -0,0 +1,300 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Internal_Copy_asm.h
+ * @brief Internal header of mcuxCsslMemory_Copy inline-asm macro
+ */
+
+
+#ifndef MCUXCSSLMEMORY_INTERNAL_COPY_ASM_H_ 
+#define MCUXCSSLMEMORY_INTERNAL_COPY_ASM_H_ 
+
+
+#if defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success)  \
+do{  \
+    __asm (  \
+        "MOV    %[_word], #0\n"  \
+        "MOV    %[_datareg], #0\n"  \
+        "MOV    %[_xorword], #0\n"  \
+        "CMP    %[_word], %[_nwords]\n"  \
+        "BLT    mcuxCsslMemory_Copy_word_loop\n"  \
+        "BGE    mcuxCsslMemory_Copy_word_loop_end\n"  \
+        "B      mcuxCsslMemory_Copy_fault\n"  \
+        "mcuxCsslMemory_Copy_word_loop:\n"  \
+        "LDR    %[_datareg], [%[_src], %[_word], LSL #2]\n"  \
+        "EORS   %[_cha], %[_cha], %[_datareg]\n"  \
+        "STR    %[_datareg], [%[_dst], %[_word], LSL #2]\n"  \
+        "EORS   %[_chb], %[_chb], %[_datareg]\n"  \
+        "ADDS   %[_word], %[_word], #+1\n"  \
+        "EORS   %[_xorword], %[_xorword], %[_word]\n"  \
+        "CMP    %[_word], %[_nwords]\n"  \
+        "BLT    mcuxCsslMemory_Copy_word_loop\n"  \
+        "mcuxCsslMemory_Copy_word_loop_end:\n"  \
+        "LSLS   %[_byte], %[_word], #2\n"  \
+        "MOV    %[_datareg], #0\n"  \
+        "CMP    %[_byte], %[_nbytes]\n"  \
+        "BLT    mcuxCsslMemory_Copy_byte_loop\n"  \
+        "BGE    mcuxCsslMemory_Copy_byte_loop_end\n"  \
+        "B      mcuxCsslMemory_Copy_fault\n"  \
+        "mcuxCsslMemory_Copy_byte_loop:\n"  \
+        "LDRB   %[_datareg], [%[_src], %[_byte]]\n"  \
+        "EORS   %[_cha], %[_cha], %[_datareg]\n"  \
+        "STRB   %[_datareg], [%[_dst], %[_byte]]\n"  \
+        "EORS   %[_chb], %[_chb], %[_datareg]\n"  \
+        "ADDS   %[_byte], %[_byte], #+1\n"  \
+        "CMP    %[_byte], %[_nbytes]\n"  \
+        "BLT    mcuxCsslMemory_Copy_byte_loop\n"  \
+        "mcuxCsslMemory_Copy_byte_loop_end:\n"  \
+        "MOV    %[_datareg], #0\n"  \
+        "EORS   %[_retval], %[_retval], %[_success]\n"  \
+        "mcuxCsslMemory_Copy_fault:\n"  \
+        : [_word] "+&r" (word)  \
+        , [_byte] "+&r" (byte)  \
+        , [_cha] "+&r" (cha)  \
+        , [_chb] "+&r" (chb)  \
+        , [_xorword] "+&r" (xorword)  \
+        , [_retval] "+r" (retval)  \
+        , [_datareg] "+&r" (datareg)  \
+        : [_src] "r" (src)  \
+        , [_dst] "r" (dst)  \
+        , [_nwords] "r" (nwords)  \
+        , [_nbytes] "r" (cnt)  \
+        , [_success] "r" (success)  \
+        : "cc", "memory"  \
+    );  \
+    (void)datareg;  \
+    (void)success;  \
+}while(false)
+
+#elif defined (__ghs__)
+#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success)  \
+do{  \
+    /* GHS compiler can only handle 10 registers for the usecase of this inline asm block. */  \
+    /* Store retval and success in registers of word and datareg. */  \
+    (word) = (retval);  \
+    (datareg) = (success);    \
+    __asm (  \
+        /* store retval and success on stack. */  \
+        "SUB    sp, #8\n"  \
+        "STR    %[_word], [sp, #0]\n"  \
+        "STR    %[_datareg], [sp, #4]\n"  \
+        /* original asm macro. */  \
+        "MOV    %[_word], #0\n"  \
+        "MOV    %[_datareg], #0\n"  \
+        "MOV    %[_xorword], #0\n"  \
+        "CMP    %[_word], %[_nwords]\n"  \
+        "BLT    mcuxCsslMemory_Copy_word_loop\n"  \
+        "BGE    mcuxCsslMemory_Copy_word_loop_end\n"  \
+        "B      mcuxCsslMemory_Copy_fault\n"  \
+        "mcuxCsslMemory_Copy_word_loop:\n"  \
+        "LDR    %[_datareg], [%[_src], %[_word], LSL #2]\n"  \
+        "EORS   %[_cha], %[_cha], %[_datareg]\n"  \
+        "STR    %[_datareg], [%[_dst], %[_word], LSL #2]\n"  \
+        "EORS   %[_chb], %[_chb], %[_datareg]\n"  \
+        "ADDS   %[_word], %[_word], #+1\n"  \
+        "EORS   %[_xorword], %[_xorword], %[_word]\n"  \
+        "CMP    %[_word], %[_nwords]\n"  \
+        "BLT    mcuxCsslMemory_Copy_word_loop\n"  \
+        "mcuxCsslMemory_Copy_word_loop_end:\n"  \
+        "LSLS   %[_byte], %[_word], #2\n"  \
+        "MOV    %[_datareg], #0\n"  \
+        "CMP    %[_byte], %[_nbytes]\n"  \
+        "BLT    mcuxCsslMemory_Copy_byte_loop\n"  \
+        "BGE    mcuxCsslMemory_Copy_byte_loop_end\n"  \
+        "B      mcuxCsslMemory_Copy_fault\n"  \
+        "mcuxCsslMemory_Copy_byte_loop:\n"  \
+        "LDRB   %[_datareg], [%[_src], %[_byte]]\n"  \
+        "EORS   %[_cha], %[_cha], %[_datareg]\n"  \
+        "STRB   %[_datareg], [%[_dst], %[_byte]]\n"  \
+        "EORS   %[_chb], %[_chb], %[_datareg]\n"  \
+        "ADDS   %[_byte], %[_byte], #+1\n"  \
+        "CMP    %[_byte], %[_nbytes]\n"  \
+        "BLT    mcuxCsslMemory_Copy_byte_loop\n"  \
+        "mcuxCsslMemory_Copy_byte_loop_end:\n"  \
+        /* load retval and success from stack. */  \
+        "LDR    %[_datareg], [sp, #0]\n"  \
+        /* use byte as temp. */  \
+        "STR    %[_byte], [sp, #0]\n"  \
+        "LDR    %[_byte], [sp, #4]\n"  \
+        /* set datareg = retval ^ success, instead of datareg = 0 in the original design. */  \
+        "EORS   %[_datareg], %[_datareg], %[_byte]\n"  \
+        "LDR    %[_byte], [sp, #0]\n"  \
+        "mcuxCsslMemory_Copy_fault:\n"  \
+        "ADD    sp, #8\n"  \
+        : [_word] "+&r" (word)  \
+        , [_byte] "+&r" (byte)  \
+        , [_cha] "+&r" (cha)  \
+        , [_chb] "+&r" (chb)  \
+        , [_xorword] "+&r" (xorword)  \
+        , [_datareg] "+&r" (datareg)  \
+        : [_src] "r" (src)  \
+        , [_dst] "r" (dst)  \
+        , [_nwords] "r" (nwords)  \
+        , [_nbytes] "r" (cnt)  \
+        : "cc", "memory"  \
+    );  \
+    (retval) = (datareg);  \
+}while(false)
+
+#elif defined (__GNUC__)
+#define MCUXCSSLMEMORY_COPY_SUCCESS_IMPL ((uint32_t)MCUXCSSLMEMORY_STATUS_OK ^ (uint32_t)MCUXCSSLMEMORY_STATUS_FAULT)
+#define MCUXCSSLMEMORY_COPY_DST_STACK_OFFSET (0)
+#define MCUXCSSLMEMORY_COPY_SRC_STACK_OFFSET (4)
+#define MCUXCSSLMEMORY_COPY_RETVAL_STACK_OFFSET (8)
+#define MCUXCSSLMEMORY_COPY_CNT_STACK_OFFSET (12)
+#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success)  \
+do{  \
+    /* [DESIGN]
+     * GNU compiler can only handle 7 registers for the usecase of this inline asm block, when building with optimization level 0.
+     * Thus, 5 registers need to be saved compared to the original asm macro.
+     * success is a constant, so it is defined as an immediatte instead of an input register.
+     * 4 registers can be used as temporary registers to push data to the stack: store retval, cnt, src, dst in registers of word, datareg, xorword, byte. */  \
+    uint32_t nwords_cnt = (nwords);  \
+    (word) = (retval);  \
+    (datareg) = (cnt);    \
+MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Typecast needed for specialized assembly routine") \
+    (xorword) = (uint32_t)(src);  \
+    (byte) = (uint32_t)(dst);    \
+MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER() \
+    __asm (  \
+        /* [DESIGN] store retval, success, src, dst on stack. */  \
+        "SUB    sp, #16\n"  \
+        "STR    %[_word], [sp, %[_RETVAL_OFFSET]]\n"  \
+        "STR    %[_datareg], [sp, %[_CNT_OFFSET]]\n"  \
+        "STR    %[_byte], [sp, %[_DST_OFFSET]]\n"  \
+        "STR    %[_xorword], [sp, %[_SRC_OFFSET]]\n" \
+        /* [DESIGN] original asm macro. */  \
+        "MOV    %[_word], #0\n"  \
+        "MOV    %[_datareg], #0\n"  \
+        "MOV    %[_xorword], #0\n"  \
+        "CMP    %[_word], %[_nwords_cnt]\n"  \
+        "BLT    mcuxCsslMemory_Copy_word_loop\n"  \
+        "BGE    mcuxCsslMemory_Copy_word_loop_end\n"  \
+        "B      mcuxCsslMemory_Copy_fault\n"  \
+        "mcuxCsslMemory_Copy_word_loop:\n"  \
+        /* [DESIGN] get src from the stack, _datareg is used as a temporary register */ \
+        "LDR    %[_datareg], [sp, %[_SRC_OFFSET]]\n"  \
+        "LDR    %[_datareg], [%[_datareg], %[_word], LSL #2]\n"  \
+        "EORS   %[_cha], %[_cha], %[_datareg]\n"  \
+        /* [DESIGN] _byte already contains the value of dst */ \
+        "STR    %[_datareg], [%[_byte], %[_word], LSL #2]\n"  \
+        "EORS   %[_chb], %[_chb], %[_datareg]\n"  \
+        "ADDS   %[_word], %[_word], #+1\n"  \
+        "EORS   %[_xorword], %[_xorword], %[_word]\n"  \
+        "CMP    %[_word], %[_nwords_cnt]\n"  \
+        "BLT    mcuxCsslMemory_Copy_word_loop\n"  \
+        "mcuxCsslMemory_Copy_word_loop_end:\n"  \
+        "LSLS   %[_byte], %[_word], #2\n"  \
+        "MOV    %[_datareg], #0\n"  \
+        "LDR    %[_nwords_cnt], [sp, %[_CNT_OFFSET]]\n"  \
+        /* [DESIGN] store word to the stack, at the offset of cnt which is not needed on stack anymore */  \
+        "STR    %[_word], [sp, %[_CNT_OFFSET]]\n"  \
+        /* [DESIGN] get dst from the stack, _word is used as a temporary register */ \
+        "LDR    %[_word], [sp, %[_DST_OFFSET]]\n"  \
+        "CMP    %[_byte], %[_nwords_cnt]\n"  \
+        "BLT    mcuxCsslMemory_Copy_byte_loop\n"  \
+        "BGE    mcuxCsslMemory_Copy_byte_loop_end\n"  \
+        "B      mcuxCsslMemory_Copy_fault\n"  \
+        "mcuxCsslMemory_Copy_byte_loop:\n"  \
+        /* [DESIGN] get src from the stack, _datareg is used as a temporary register */ \
+        "LDR    %[_datareg], [sp, %[_SRC_OFFSET]]\n"  \
+        "LDRB   %[_datareg], [%[_datareg], %[_byte]]\n"  \
+        "EORS   %[_cha], %[_cha], %[_datareg]\n"  \
+        /* [DESIGN] _word already contains the value of dst */ \
+        "STRB   %[_datareg], [%[_word], %[_byte]]\n"  \
+        "EORS   %[_chb], %[_chb], %[_datareg]\n"  \
+        "ADDS   %[_byte], %[_byte], #+1\n"  \
+        "CMP    %[_byte], %[_nwords_cnt]\n"  \
+        "BLT    mcuxCsslMemory_Copy_byte_loop\n"  \
+        "mcuxCsslMemory_Copy_byte_loop_end:\n"  \
+        /* [DESIGN] load retval from stack. */  \
+        "LDR    %[_datareg], [sp, %[_RETVAL_OFFSET]]\n"  \
+        /* [DESIGN] use _byte as temp. */  \
+        "STR    %[_byte], [sp, %[_RETVAL_OFFSET]]\n"  \
+        "LDR    %[_byte], =%[_SUCCESS]\n"  \
+        /* [DESIGN] set datareg = retval ^ success, instead of datareg = 0 in the original design. */  \
+        "EORS   %[_datareg], %[_datareg], %[_byte]\n"  \
+        "LDR    %[_byte], [sp, %[_RETVAL_OFFSET]]\n"  \
+        "LDR    %[_word], [sp, %[_CNT_OFFSET]]\n"  \
+        "mcuxCsslMemory_Copy_fault:\n"  \
+        "ADD    sp, #16\n"  \
+        : [_word] "+&r" (word)  \
+        , [_byte] "+&r" (byte)  \
+        , [_cha] "+&r" (cha)  \
+        , [_chb] "+&r" (chb)  \
+        , [_xorword] "+&r" (xorword)  \
+        , [_datareg] "+&r" (datareg)  \
+        , [_nwords_cnt] "+&r" (nwords_cnt)  \
+        : [_SUCCESS] "i" MCUXCSSLMEMORY_COPY_SUCCESS_IMPL \
+        , [_DST_OFFSET] "i" MCUXCSSLMEMORY_COPY_DST_STACK_OFFSET \
+        , [_SRC_OFFSET] "i" MCUXCSSLMEMORY_COPY_SRC_STACK_OFFSET \
+        , [_RETVAL_OFFSET] "i" MCUXCSSLMEMORY_COPY_RETVAL_STACK_OFFSET \
+        , [_CNT_OFFSET] "i" MCUXCSSLMEMORY_COPY_CNT_STACK_OFFSET \
+        : "cc", "memory"  \
+    );  \
+    (retval) = (datareg);  \
+    (void) success; \
+}while(false)
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success)  \
+do{  \
+    __asm {  \
+        MOV    word, 0;  \
+        MOV    datareg, 0;  \
+        MOV    xorword, 0;  \
+        CMP    word, nwords;  \
+        BLT    mcuxCsslMemory_Copy_word_loop;  \
+        BGE    mcuxCsslMemory_Copy_word_loop_end;  \
+        B      mcuxCsslMemory_Copy_fault;  \
+mcuxCsslMemory_Copy_word_loop:  \
+        LDR    datareg, [src, word, LSL 2];  \
+        EORS   cha, cha, datareg;  \
+        STR    datareg, [dst, word, LSL 2];  \
+        EORS   chb, chb, datareg;  \
+        ADDS   word, word, +1;  \
+        EORS   xorword, xorword, word;  \
+        CMP    word, nwords;  \
+        BLT    mcuxCsslMemory_Copy_word_loop;  \
+mcuxCsslMemory_Copy_word_loop_end:  \
+        LSLS   byte, word, 2;  \
+        MOV    datareg, 0;  \
+        CMP    byte, cnt;  \
+        BLT    mcuxCsslMemory_Copy_byte_loop;  \
+        BGE    mcuxCsslMemory_Copy_byte_loop_end;  \
+        B      mcuxCsslMemory_Copy_fault;  \
+mcuxCsslMemory_Copy_byte_loop:  \
+        LDRB   datareg, [src, byte];  \
+        EORS   cha, cha, datareg;  \
+        STRB   datareg, [dst, byte];  \
+        EORS   chb, chb, datareg;  \
+        ADDS   byte, byte, +1;  \
+        CMP    byte, cnt;  \
+        BLT    mcuxCsslMemory_Copy_byte_loop;  \
+mcuxCsslMemory_Copy_byte_loop_end:  \
+        MOV    datareg, 0;  \
+        EORS   retval, retval, success;  \
+mcuxCsslMemory_Copy_fault:  \
+    }  \
+    (void)datareg;  \
+    (void)success;  \
+}while(false)
+
+#else
+    #error Unsupported compiler. The above section must be manually adapted to support your compiler inline assembly syntax.
+#endif /* Compiler selection */
+
+
+#endif /* MCUXCSSLMEMORY_INTERNAL_COPY_ASM_H_  */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_SecureCompare.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_SecureCompare.h
new file mode 100644
index 0000000000..6363304dd6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_SecureCompare.h
@@ -0,0 +1,55 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023-2024 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Internal_SecureCompare.h
+ * @brief Internal header of mcuxCsslMemory_SecureCompare
+ */
+
+
+#ifndef MCUXCSSLMEMORY_INTERNAL_SECURECOMPARE_H_
+#define MCUXCSSLMEMORY_INTERNAL_SECURECOMPARE_H_
+
+#include <stdint.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+
+/**
+ * @brief Securely compares the two memory regions @p lhs and @p rhs - internal use only
+ *
+ * The implementation is secure in the following aspects:
+ *
+ * * Constant execution time: The execution sequence of the code is always identical for equal @p length parameters,
+ *     i.e. no branches are performed based on the data in @p pLhs or @p pRhs.
+ * * Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation.
+ * * Random order memory access: an attacker shall not be able to distinguish the position of the difference between the two compared buffers.
+ * * Blinded word compare: SPA protection.
+ * * Integrity of the result is ensured. The accumulator of differences is checked twice when generating the return status (EQUAL or NOT_EQUAL).
+ * * Data Integrity: Expunge(pLhs + pRhs + length)
+ *
+ * @param pLhs   The left-hand side data to compare. Must not be NULL.
+ * @param pRhs   The right-hand side data to compare. Must not be NULL.
+ * @param length The number of bytes to compare.
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCSSLMEMORY_STATUS_EQUAL If the contents of @p lhs and @p rhs are equal.
+ * @retval #MCUXCSSLMEMORY_STATUS_NOT_EQUAL If the contents of @p lhs and @p rhs are not equal.
+ * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Int_SecComp)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Int_SecComp(
+    const uint8_t * pLhs,
+    const uint8_t * pRhs,
+    uint32_t length
+);
+
+#endif  /* MCUXCSSLMEMORY_INTERNAL_SECURECOMPARE_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory.h
new file mode 100644
index 0000000000..7f77495590
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory.h
@@ -0,0 +1,41 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory.h
+ * @brief Top-level include file for the CSSL memory functions
+ */
+
+#ifndef MCUXCSSLMEMORY_H
+#define MCUXCSSLMEMORY_H
+
+/**
+ * @defgroup mcuxCsslMemory mcuxCssl Memory API
+ * @brief Control Flow Protected Memory Functions
+ *
+ * @ingroup mcuxCsslAPI
+ */
+#include <mcuxCsslMemory_Constants.h>
+#include <mcuxCsslMemory_Types.h>
+
+
+#include <mcuxCsslMemory_Compare.h>
+
+#include <mcuxCsslMemory_Clear.h>
+
+#include <mcuxCsslMemory_Copy.h>
+
+#include <mcuxCsslMemory_Set.h>
+
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Clear.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Clear.h
new file mode 100644
index 0000000000..8594031979
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Clear.h
@@ -0,0 +1,80 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Clear.h
+ * @brief header file of memory clear function
+ */
+
+
+#ifndef MCUXCSSLMEMORY_CLEAR_H_
+#define MCUXCSSLMEMORY_CLEAR_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslParamIntegrity.h>
+
+/**
+ * @defgroup mcuxCsslMemory_Clear mcuxCssl Memory Clear
+ * @brief Control Flow Protected Memory Clear Function
+ *
+ * @ingroup mcuxCsslMemory
+ * @{
+ */
+
+/**
+ * @defgroup mcuxCsslMemory_Clear_Functions mcuxCsslMemory_Clear Function Definitions
+ * @brief mcuxCsslMemory_Clear Function Definitions
+ *
+ * @ingroup mcuxCsslMemory_Clear
+ * @{
+ */
+
+/**
+ * @brief Clear @p length bytes of data at @p pDst
+ *
+ * The implementation is secure in the following aspects:
+ * Parameter integrity protection: the function returns immediately in case of an incorrect parameter checksum.
+ * Code flow protection: the function call is protected.
+ * Buffer overflow protection: no data is written to @p pDst beyond @p dstLength bytes.
+ *
+ * @param[in]  chk       The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect.
+ * @param[in]  pDst      The destination pointer to buffer to be cleared. Must not be NULL.
+ * @param[in]  dstLength The size of the destination data buffer in bytes.
+ * @param[in]  length    The number of bytes to clear.
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCSSLMEMORY_STATUS_OK                If the contents in buffer at @p pDst is cleared.
+ * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER If one of the parameters is invalid.
+ * @retval #MCUXCSSLMEMORY_STATUS_FAULT             If a fault was detected, included invalid checksum @p chk.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Clear)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Clear
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void * pDst,
+    size_t dstLength,
+    size_t length
+);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* MCUXCSSLMEMORY_CLEAR_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Compare.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Compare.h
new file mode 100644
index 0000000000..bfc5424f46
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Compare.h
@@ -0,0 +1,80 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Compare.h
+ * @brief Include file for constant time memory compare function
+ */
+
+#ifndef MCUXCSSLMEMORY_COMPARE_H
+#define MCUXCSSLMEMORY_COMPARE_H
+
+#include <stdint.h>
+#include <mcuxCsslParamIntegrity.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+
+/**
+ * @defgroup mcuxCsslMemory_Compare mcuxCssl Memory Compare
+ * @brief Control Flow Protected Memory Compare Function
+ *
+ * @ingroup mcuxCsslMemory
+ * @{
+ */
+
+/**
+ * @defgroup mcuxCsslMemory_Compare_Functions mcuxCsslMemory_Compare Function Definitions
+ * @brief mcuxCsslMemory_Compare Function Definitions
+ *
+ * @ingroup mcuxCsslMemory_Compare
+ * @{
+ */
+
+/**
+ * @brief Compares the two memory regions @p lhs and @p rhs
+ *
+ * The implementation is secure in the following aspects:
+ * 
+ * * Constant execution time: The execution sequence of the code is always identical for equal @p length parameters,
+ *     i.e. no branches are performed based on the data in @p pLhs or @p pRhs.
+ * * Parameter integrity protection: An incorrect parameter checksum makes the function return immediately.
+ * * Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation.
+ * 
+ * @param chk    The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect.
+ * @param pLhs   The left-hand side data to compare. Must not be NULL.
+ * @param pRhs   The right-hand side data to compare. Must not be NULL.
+ * @param length The number of bytes to compare.
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCSSLMEMORY_STATUS_EQUAL If the contents of @p lhs and @p rhs are equal.
+ * @retval #MCUXCSSLMEMORY_STATUS_NOT_EQUAL If the contents of @p lhs and @p rhs are not equal.
+ * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER If one of the parameters was invalid (i.e. @p lhs or @p rhs was NULL or @p length was zero).
+ * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Compare)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Compare
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void const * pLhs,
+    void const * pRhs,
+    size_t length
+);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Constants.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Constants.h
new file mode 100644
index 0000000000..28fed941bf
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Constants.h
@@ -0,0 +1,52 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Constants.h
+ * @brief Constants definitions for the mcuxCsslMemory component
+ */
+
+#ifndef MCUXCSSLMEMORY_CONSTANTS_H
+#define MCUXCSSLMEMORY_CONSTANTS_H
+
+#include <stdint.h>
+#include <mcuxCsslMemory_Types.h>
+
+/**********************************************
+ * CONSTANTS
+ **********************************************/
+
+/**
+ * @brief CSSL Memory Component mask value.
+ */
+#define MCUXCSSLMEMORY_COMPONENT_MASK              0x04240000u ///< Component mask value
+
+/**
+ * @defgroup MCUXCSSLMEMORY_STATUS_ MCUXCSSLMEMORY_STATUS_
+ * @brief Defines valid mcuxCsslMemory function return codes
+ * @ingroup mcuxCsslMemory_Constants
+ * @{
+ */
+#define MCUXCSSLMEMORY_STATUS_OK                 ((mcuxCsslMemory_Status_t) 0x04242E03u) ///< The operation was successful
+#define MCUXCSSLMEMORY_STATUS_EQUAL              ((mcuxCsslMemory_Status_t) 0x04242E47u) ///< The two contents of the Memory Compare are equal
+#define MCUXCSSLMEMORY_STATUS_NOT_EQUAL          ((mcuxCsslMemory_Status_t) 0x042489B8u) ///< The two contents of the Memory Compare are not equal
+#define MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER  ((mcuxCsslMemory_Status_t) 0x0424533Cu) ///< A parameter was invalid
+#define MCUXCSSLMEMORY_STATUS_FAULT              ((mcuxCsslMemory_Status_t) 0x0424F0F0u) ///< A fault occurred in the execution
+
+#define MCUXCSSLMEMORY_KEEP_ORDER     ((uint32_t) 0x042439A5u)  ///< Data storing in destination buffer in original order.
+#define MCUXCSSLMEMORY_REVERSE_ORDER  ((uint32_t) 0x0424395Au)  ///< Data storing in destination buffer with reversed order.
+/**
+ * @}
+ */
+
+#endif /* MCUXCSSLMEMORY_CONSTANTS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h
new file mode 100644
index 0000000000..9f5ffaa959
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h
@@ -0,0 +1,77 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021, 2023 NXP                                                 */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Copy.h
+ * @brief Include file for memory copy function
+ */
+
+#ifndef MCUXCSSLMEMORY_COPY_H_
+#define MCUXCSSLMEMORY_COPY_H_
+
+/**
+ * @defgroup mcuxCsslMemory_Copy mcuxCssl Memory Copy
+ * @brief Control Flow Protected Memory Copy Function
+ *
+ * @ingroup mcuxCsslMemory
+ * @{
+ */
+
+/**
+ * @defgroup mcuxCsslMemory_Copy_Functions mcuxCsslMemory_Copy Function Definitions
+ * @brief mcuxCsslMemory_Copy Function Definitions
+ *
+ * @ingroup mcuxCsslMemory_Copy
+ * @{
+ */
+
+/**
+ * @brief Copies @p length bytes of data from @p pSrc to @p pDst
+ *
+ * The implementation is secure in the following aspects:
+ *
+ * * Constant execution time: If @p pSrc and @p pDst have the same offset to the nearest 16-byte boundary, and if @p length
+ *     is the same, the execution sequence of the code is always identical.
+ * * Parameter integrity protection: An incorrect parameter checksum makes the function return immediately.
+ * * Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation.
+ * * Buffer overflow protection: No data is written to @p pDst beyond @p dstLength bytes.
+ *
+ * @param[in]     chk        The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect.
+ * @param[in]     pSrc       The data to be copied. Must not be NULL. Must not overlap with @p pDst.
+ * @param[out]    pDst       The destination pointer. Must not be NULL. Must not overlap with @p pSrc.
+ * @param[in]     dstLength  The size of the destination data buffer in bytes.
+ * @param[in]     length     The number of bytes to copy.
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCSSLMEMORY_STATUS_OK If the operation was successful.
+ * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER If one of the parameters was invalid (i.e. @p pSrc or @p pDst was NULL or @p length was zero).
+ * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Copy)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Copy
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void const * pSrc,
+    void * pDst,
+    size_t dstLength,
+    size_t length
+);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* MCUXCSSLMEMORY_COPY_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Set.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Set.h
new file mode 100644
index 0000000000..2a77ba1b8e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Set.h
@@ -0,0 +1,82 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021, 2023 NXP                                                 */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Set.h
+ * @brief header file of memory set function
+ */
+
+
+#ifndef MCUXCSSLMEMORY_SET_H_
+#define MCUXCSSLMEMORY_SET_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslParamIntegrity.h>
+
+/**
+ * @defgroup mcuxCsslMemory_Set mcuxCssl Memory Set
+ * @brief Control Flow Protected Memory Set Function
+ *
+ * @ingroup mcuxCsslMemory
+ * @{
+ */
+
+/**
+ * @defgroup mcuxCsslMemory_Set_Functions mcuxCsslMemory_Set Function Definitions
+ * @brief mcuxCsslMemory_Set Function Definitions
+ *
+ * @ingroup mcuxCsslMemory_Set
+ * @{
+ */
+
+/**
+ * @brief Set @p length bytes of data at @p pDst
+ *
+ * The implementation is secure in the following aspects:
+ * Parameter integrity protection: the function returns immediately in case of an incorrect parameter checksum.
+ * Code flow protection: the function call is protected.
+ * Buffer overflow protection: no data is written to @p pDst beyond @p bufLength bytes.
+ *
+ * @param[in]  chk          The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect.
+ * @param[in]  pDst         The destination pointer to buffer to be set. Must not be NULL.
+ * @param[in]  val          The byte value to be set. 
+ * @param[in]  length       The size in bytes to set.
+ * @param[in]  bufLength    The buffer size (if bufLength < length, only bufLength bytes are set).
+ *
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCSSLMEMORY_STATUS_OK                 If @p val set @p length times at @p pDst.
+ * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER  If one of the parameters is invalid.
+ * @retval #MCUXCSSLMEMORY_STATUS_FAULT              If a fault was detected, included invalid checksum @p chk.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Set)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Set
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void * pDst,
+    uint8_t val,
+    size_t length,
+    size_t bufLength
+);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* MCUXCSSLMEMORY_SET_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Types.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Types.h
new file mode 100644
index 0000000000..7daab12e15
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Types.h
@@ -0,0 +1,52 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Types.h
+ * @brief Type definitions for the mcuxCsslMemory component
+ */
+
+#ifndef MCUXCSSLMEMORY_TYPES_H
+#define MCUXCSSLMEMORY_TYPES_H
+
+#include <stdint.h>
+
+/**
+ * @defgroup mcuxCsslMemory_Types mcuxCsslMemory_Types
+ * @brief Defines common macros and types of @ref mcuxCsslMemory
+ * @ingroup mcuxCsslMemory
+ * @{
+ */
+
+/**********************************************
+ * TYPEDEFS
+ **********************************************/
+
+/**
+ * @defgroup mcuxCsslMemory_Types_Types mcuxCsslMemory_Types_Types
+ * @brief Defines all types of @ref mcuxCsslMemory_Types
+ * @ingroup mcuxCsslMemory_Types
+ * @{
+ */
+
+/**
+ * @brief Type for CSSL Memory status codes.
+ */
+typedef uint32_t mcuxCsslMemory_Status_t;
+/**
+ * @}
+ *
+ * @}
+ */
+
+#endif /* MCUXCSSLMEMORY_TYPES_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c
new file mode 100644
index 0000000000..dcb761d33f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c
@@ -0,0 +1,54 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Clear.c
+ * @brief mcuxCsslMemory: implementation of secure memory clear function
+ */
+
+
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslSecureCounter.h>
+#include <mcuxCsslParamIntegrity.h>
+#include <mcuxCsslMemory.h>
+#include <mcuxCsslMemory_Clear.h>
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Clear)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Clear
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void * pDst,
+    size_t dstLength,
+    size_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Clear,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate) );
+
+    MCUX_CSSL_FP_FUNCTION_CALL(retCode_paramIntegrityValidate, mcuxCsslParamIntegrity_Validate(chk, 3u, pDst, dstLength, length));
+    if ((retCode_paramIntegrityValidate != MCUXCSSLPARAMINTEGRITY_CHECK_VALID))
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Clear, MCUXCSSLMEMORY_STATUS_FAULT);
+    }
+
+    if (length > dstLength)
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Clear, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER);
+    }
+
+    MCUX_CSSL_FP_FUNCTION_CALL(retCode_memSet, mcuxCsslMemory_Set(mcuxCsslParamIntegrity_Protect(4u, pDst, 0u, length, dstLength), pDst, 0u, length, dstLength) );
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Clear, retCode_memSet,
+      MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Set ));
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c
new file mode 100644
index 0000000000..164c23ce0d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c
@@ -0,0 +1,78 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#include <mcuxCsslMemory.h>
+#include <mcuxCsslSecureCounter.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslAnalysis.h>
+#include <internal/mcuxCsslMemory_Internal_Compare_asm.h>
+
+#define CLS_NORMAL      0x2E00u
+#define CLS_MISMATCH    0x8900u
+#define LSB_NOT_EQUAL   0xB8u
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Compare)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Compare
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void const * pLhs,
+    void const * pRhs,
+    size_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Compare,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate)
+    );
+
+    MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxCsslParamIntegrity_Validate(chk, 3u, pLhs, pRhs, length));
+
+    if( (result != MCUXCSSLPARAMINTEGRITY_CHECK_VALID)) {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, MCUXCSSLMEMORY_STATUS_FAULT);
+    }
+
+   if((NULL == pLhs) || (NULL == pRhs)) {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER);
+    }
+
+    uint32_t nwords = 0u;
+    uint32_t retval = 0u;
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_VOID()
+    uint8_t const * cur_lhs = (uint8_t const *)pLhs;
+    uint8_t const * cur_rhs = (uint8_t const *)pRhs;
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_VOID()
+    uint32_t const notValid = ~(MCUXCSSLPARAMINTEGRITY_CHECK_VALID);
+    uint32_t const errCode = (uint32_t)MCUXCSSLMEMORY_STATUS_NOT_EQUAL;
+
+    /* Pre-calculate end pointers */
+    uint8_t const * end_lhs = &cur_lhs[length];
+    uint8_t const * end_rhs = &cur_rhs[length];
+
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("Exception 9: re-interpreting the memory for word access")
+    MCUXCSSLMEMORY_COMPARE_ASM_COMPARISON(retval, cur_lhs, cur_rhs, nwords, length, notValid, result);
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES()
+
+    MCUXCSSLMEMORY_COMPARE_ASM_CALC_RETVAL(retval, errCode);
+    retval &= 0x000000FFu;  /* Isolate the byte value that we are interested in */
+    retval |= MCUXCSSLMEMORY_COMPONENT_MASK | CLS_MISMATCH;  /* Defines the value to what is expected */
+    retval ^= (CLS_MISMATCH ^ CLS_NORMAL) & ((retval ^ LSB_NOT_EQUAL) << 8);  /* If equal, then change the class to match the equal case */
+
+    /* Check that the pointers reached the end */
+    if((end_lhs != cur_lhs) || (end_rhs != cur_rhs)) {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, MCUXCSSLMEMORY_STATUS_FAULT);
+    }
+
+    MCUX_CSSL_SC_ADD(nwords); // -> should be 0
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, retval);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c
new file mode 100644
index 0000000000..2a7a4d2d5a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c
@@ -0,0 +1,77 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#include <mcuxCsslMemory.h>
+#include <mcuxCsslSecureCounter.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslAnalysis.h>
+#include <internal/mcuxCsslMemory_Internal_Copy_asm.h>
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Copy)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Copy
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void const * pSrc,
+    void * pDst,
+    size_t dstLength,
+    size_t length
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Copy,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate)
+    );
+
+    MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxCsslParamIntegrity_Validate(chk, 4u, pSrc, pDst, dstLength, length));
+
+    if(result != MCUXCSSLPARAMINTEGRITY_CHECK_VALID) {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Copy, MCUXCSSLMEMORY_STATUS_FAULT);
+    }
+
+    if((NULL == pSrc) || (NULL == pDst) || (length > dstLength)) {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Copy, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER);
+    }
+
+    uint32_t retval = (uint32_t) MCUXCSSLMEMORY_STATUS_FAULT;
+
+    const uint32_t nwords = length / 4U;
+    const uint32_t success = (uint32_t)MCUXCSSLMEMORY_STATUS_OK ^ (uint32_t)MCUXCSSLMEMORY_STATUS_FAULT;
+    uint32_t word = 0U;
+    uint32_t xorword = 0U;
+    uint32_t byte = 0U;
+    uint32_t cha = nwords;
+    uint32_t chb = 0xFFFFFFFFU;
+    uint32_t datareg = 0U;
+
+    MCUX_CSSL_SC_ADD(word); // -> should be 0
+    MCUX_CSSL_SC_ADD(xorword); // -> should be 0
+    MCUX_CSSL_SC_SUB(2U * nwords); // -> corresponds to `~(cha ^ chb) + word` after the below assembly has executed
+    // The following value is essentially a precalculation of the function xorchain(n) = 1 ^ 2 ^ 3 ^ 4 ^ 5 ^ ... ^ n (a chain of XOR operations), where n is substituted by nwords.
+    // If n % 4 == 0, then xorchain(n) == n.
+    // If n % 4 == 1, then xorchain(n) == 1.
+    // If n % 4 == 2, then xorchain(n) == n + 1.
+    // If n % 4 == 3, then xorchain(n) == 0.
+    // The following is just a branchless way to do the case distinction.
+    // In the loop afterwards, this value is calculated by actually cumulatively XORing the value of the variable "word" in each loop iteration, which starts at 0 and increments up to nwords.
+    MCUX_CSSL_SC_SUB(nwords - (nwords % 2U) * nwords + ((nwords % 2U) ^ ((nwords % 4U) >> 1U))); // -> precalculation of xorword
+    MCUX_CSSL_SC_SUB(length); // -> corresponds to `byte` after the below assembly has executed
+
+    MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, pSrc, pDst, nwords, length, success);
+
+    MCUX_CSSL_SC_ADD(~(cha ^ chb));
+    MCUX_CSSL_SC_ADD(xorword);
+    MCUX_CSSL_SC_ADD(word);
+    MCUX_CSSL_SC_ADD(byte);
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Copy, retval);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c
new file mode 100644
index 0000000000..b97359f395
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c
@@ -0,0 +1,67 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Internal_SecureCompare_Stub.c
+ * @brief C file that contains the stub implementation of the secure compare in C
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslMemory_Constants.h>
+#include <mcuxCsslMemory_Types.h>
+#ifdef CSSL_MEMORY_ENABLE_COMPARE
+#include <mcuxCsslMemory_Compare.h>
+#include <mcuxCsslParamIntegrity.h>
+#endif /* CSSL_MEMORY_ENABLE_COMPARE */
+#include <internal/mcuxCsslMemory_Internal_SecureCompare.h>
+
+
+/**
+ * @brief Stub comparison of the two memory regions @p lhs and @p rhs - internal use only
+ *
+ * The implementation calls mcuxCsslMemory_Compare when possible (function defined and pointers aligned)
+ * else a code that contains no security countermeasure inside is called.
+ *
+ */
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Int_SecComp)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Int_SecComp
+(
+    const uint8_t * pLhs,
+    const uint8_t * pRhs,
+    uint32_t length
+)
+{
+#ifdef CSSL_MEMORY_ENABLE_COMPARE
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Int_SecComp,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare)
+    );
+
+    const uint32_t cpuWordSize = sizeof(uint32_t);
+    if ((0u == ((uint32_t) pLhs & (cpuWordSize - 1u))) && (0u == ((uint32_t) pRhs & (cpuWordSize - 1u)))) {
+        MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pLhs, pRhs, length), pLhs, pRhs, length));
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Int_SecComp, retval);
+    }
+#endif  /* CSSL_MEMORY_ENABLE_COMPARE */
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Int_SecComp);
+
+    mcuxCsslMemory_Status_t retval = MCUXCSSLMEMORY_STATUS_EQUAL;
+    for (uint32_t i = 0u; i < length; ++i) {
+        if (pLhs[i] != pRhs[i]) {
+            retval = MCUXCSSLMEMORY_STATUS_NOT_EQUAL;
+        }
+    }
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Int_SecComp, retval);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c
new file mode 100644
index 0000000000..1cb7242432
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c
@@ -0,0 +1,131 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2021-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslMemory_Set.c
+ * @brief mcuxCsslMemory: implementation of memory set function
+ */
+
+
+#include <stddef.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslSecureCounter.h>
+#include <mcuxCsslParamIntegrity.h>
+#include <mcuxCsslMemory.h>
+#include <mcuxCsslAnalysis.h>
+
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Set)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Set
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    void * pDst,
+    uint8_t val,
+    size_t length,
+    size_t bufLength
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Set,
+        MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate));
+
+    MCUX_CSSL_FP_FUNCTION_CALL(retCode_paramIntegrityValidate, mcuxCsslParamIntegrity_Validate(chk, 4u, pDst, val, length, bufLength));
+
+    if (MCUXCSSLPARAMINTEGRITY_CHECK_VALID != retCode_paramIntegrityValidate)
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Set, MCUXCSSLMEMORY_STATUS_FAULT);
+    }
+
+    if (NULL == pDst)
+    {
+        MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Set, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER);
+    }
+
+    size_t copyLen = bufLength < length ? bufLength : length;
+    uint32_t remainLength = (uint32_t) copyLen;
+    uint32_t wordVal = ((uint32_t)val << 24) | ((uint32_t)val << 16) | ((uint32_t)val << 8) | (uint32_t)val;
+    const uint32_t cpuWordSize = sizeof(uint32_t);
+
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_VOID()
+    volatile uint8_t *p8Dst = (volatile uint8_t *) pDst; // needs to be aligned
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_VOID()
+
+
+    MCUX_CSSL_ANALYSIS_START_PATTERN_SC_CAST_POINTERS()
+    MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ copyLen].")
+    MCUX_CSSL_SC_ADD((uint32_t) pDst + copyLen);
+    MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_CAST_POINTERS()
+
+    MCUX_CSSL_FP_LOOP_DECL(FirstByteLoop);
+    MCUX_CSSL_FP_LOOP_DECL(SecondByteLoop);
+    MCUX_CSSL_FP_LOOP_DECL(WordLoop);
+
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Typecast pointer to integer to check address for alignment")
+    while ((0u != ((uint32_t) p8Dst & (cpuWordSize - 1u))) && (0u != remainLength))
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER()
+    {
+        MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p8Dst will be in the valid range pDst[0 ~ copyLen].")
+        MCUX_CSSL_FP_LOOP_ITERATION(FirstByteLoop);
+        *p8Dst = val;
+        p8Dst++;
+        remainLength--;
+        MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    }
+
+
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("p8Dst is CPU word-aligned after the previous loop")
+    volatile uint32_t *p32Dst = (volatile uint32_t *) p8Dst;  /* p8Dst is CPU word-aligned after the previous loop. */
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING()
+    while (cpuWordSize <= remainLength)
+    {
+        MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p32Dst will be in the valid range pDst[0 ~ copyLen].")
+        MCUX_CSSL_FP_LOOP_ITERATION(WordLoop);
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("p8Dst is CPU word-aligned after the previous loop")
+        *p32Dst = wordVal;
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING()
+        p32Dst++;
+        remainLength -= cpuWordSize;
+        MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    }
+
+    p8Dst = (volatile uint8_t *) p32Dst;
+    while (0u != remainLength)
+    {
+        MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p8Dst will be in the valid range pDst[0 ~ copyLen].")
+        MCUX_CSSL_FP_LOOP_ITERATION(SecondByteLoop);
+        *p8Dst = val;
+        p8Dst++;
+        remainLength--;
+        MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    }
+
+    MCUX_CSSL_SC_SUB((uint32_t) p8Dst);
+    MCUX_CSSL_ANALYSIS_START_PATTERN_SC_CAST_POINTERS()
+    MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "modular arithmetic, mod 4")
+    MCUX_CSSL_FP_COUNTER_STMT(uint32_t noOfBytesToAlignment = ((0u - ((uint32_t) pDst)) % cpuWordSize));
+    MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW)
+    MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_CAST_POINTERS()
+
+    MCUX_CSSL_FP_COUNTER_STMT(uint32_t firstByteIteration = (copyLen > noOfBytesToAlignment)
+                             ? noOfBytesToAlignment
+                             : copyLen);
+    MCUX_CSSL_FP_COUNTER_STMT(uint32_t wordIteration = (copyLen > firstByteIteration)
+                             ? ((copyLen - firstByteIteration) / cpuWordSize)
+                             : 0u);
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Set, MCUXCSSLMEMORY_STATUS_OK,
+        MCUX_CSSL_FP_LOOP_ITERATIONS(FirstByteLoop, firstByteIteration),
+        MCUX_CSSL_FP_LOOP_ITERATIONS(WordLoop, wordIteration),
+        MCUX_CSSL_FP_LOOP_ITERATIONS(SecondByteLoop, copyLen - (wordIteration * cpuWordSize) - firstByteIteration));
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslParamIntegrity/inc/mcuxCsslParamIntegrity.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslParamIntegrity/inc/mcuxCsslParamIntegrity.h
new file mode 100644
index 0000000000..6bcd11f15a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslParamIntegrity/inc/mcuxCsslParamIntegrity.h
@@ -0,0 +1,116 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2021 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/// @file  mcuxCsslParamIntegrity.h
+/// @brief Top-level include file for the parameter integrity protection mechanism
+///
+/// The library exposes the following functions:
+/// <ol>
+///     <li> Generation of parameter checksums: #mcuxCsslParamIntegrity_Protect
+///     <li> Validation of parameter checksums: #mcuxCsslParamIntegrity_Validate
+/// </ol>
+
+#ifndef MCUXCSSLPARAMINTEGRITY_H
+#define MCUXCSSLPARAMINTEGRITY_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+
+/**
+ * @defgroup mcuxCsslParamIntegrity Parameter Integrity API
+ * @brief Functionality to ensure parameter integrity during function calls
+ *
+ * @ingroup mcuxCsslAPI
+ * @{
+ */
+
+/**
+ * @defgroup mcuxCsslParamIntegrity_Macros mcuxCsslParamIntegrity Macro Definitions
+ * @brief Macros of mcuxCsslParamIntegrity component
+ * @ingroup mcuxCsslParamIntegrity
+ * @{
+ */
+
+#define MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM ((mcuxCsslParamIntegrity_Checksum_t)0xb7151628u) ///< First eight hex digits of Eulers number
+
+#define MCUXCSSLPARAMINTEGRITY_CHECK_VALID ((mcuxCsslParamIntegrity_Checksum_t)0x6969u) ///< Return value of #mcuxCsslParamIntegrity_Validate if the parameter checksum was correct
+
+#define MCUXCSSLPARAMINTEGRITY_CHECK_INVALID ((mcuxCsslParamIntegrity_Checksum_t)0x9696u) ///< Return value of #mcuxCsslParamIntegrity_Validate if the parameter checksum was incorrect
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup mcuxCsslParamIntegrity_Types mcuxCsslParamIntegrity Type Definitions
+ * @brief Types of mcuxCsslParamIntegrity component
+ * @ingroup mcuxCsslParamIntegrity
+ * @{
+ */
+
+/**
+* @brief Build time assertion to ensure CPU word size of 32 bit
+*/
+typedef void * mcuxCsslParamIntegrity_AssertionCpuWordSize_t[(4u == sizeof(size_t)) ? (+1) : (-1)];
+
+/**
+* @brief  Type of a parameter checksum.
+*/
+typedef uint32_t mcuxCsslParamIntegrity_Checksum_t;
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup mcuxCsslParamIntegrity_Functions mcuxCsslParamIntegrity Function Definitions
+ * @brief Functions of mcuxCsslParamIntegrity component
+ * @ingroup mcuxCsslParamIntegrity
+ * @{
+ */
+
+/**
+ * @brief Calculates a parameter checksum.
+ * 
+ * @param nargs The number of parameters to be protected.
+ * @param ... The parameters that should be protected. Note that parameters bigger than a single machine word are not supported.
+ * @return checksum over the input parameters to be protected
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslParamIntegrity_Protect)
+mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect(size_t nargs, ...);
+
+/**
+ * @brief Verifies the correctness of a parameter checksum.
+ * 
+ * @param chk The parameter checksum.
+ * @param nargs The number of parameters to be protected.
+ * @param ... The parameters that were used to calculate the parameter checksum. Note that parameters bigger than a single machine word are not supported.
+ * @return A status code encapsulated in a flow-protection type.
+ * @retval #MCUXCSSLPARAMINTEGRITY_CHECK_VALID The parameter checksum was correct.
+ * @retval #MCUXCSSLPARAMINTEGRITY_CHECK_INVALID The parameter checksum was incorrect.
+ */
+MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslParamIntegrity_Validate)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslParamIntegrity_Checksum_t) mcuxCsslParamIntegrity_Validate(mcuxCsslParamIntegrity_Checksum_t chk, size_t nargs, ...);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c
new file mode 100644
index 0000000000..aba4a31d4b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c
@@ -0,0 +1,83 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#include <mcuxCsslParamIntegrity.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslAnalysis.h>
+#include <stdarg.h>
+#include <stddef.h>
+
+MCUX_CSSL_ANALYSIS_START_SUPPRESS_STDARG_USAGE("Usage of stdarg.h feature has been analyzed and approved, compiler error has been added for exceptions (when CPU word size > 32 bit)")
+
+MCUX_CSSL_FP_FUNCTION_DEF(rotate_right)
+static uint32_t rotate_right(uint32_t val, uint32_t shift_amt) {
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("shift_amt will be always less than 32.")
+    return ((val) >> (shift_amt) % 32u) | ((val) << (32u - (shift_amt)) % 32u);
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslParamIntegrity_InternalProtect)
+static mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_InternalProtect(size_t nargs, va_list args) {
+    mcuxCsslParamIntegrity_Checksum_t result = MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM;
+    for(size_t i = 0; i < nargs; i++) {
+        MCUX_CSSL_ANALYSIS_START_SUPPRESS_VA_ARGS_USAGE("This is third party code. va_arg macro from stdarg.h contains two violations to MISRA rule 10.1, two violations to MISRA rule 10.4 and a violation to MISRA rule 20.7")
+        MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW()
+        result += rotate_right(va_arg(args, uint32_t), i);
+        MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+        MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_VA_ARGS_USAGE()
+    }
+    return result;
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslParamIntegrity_Protect)
+mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect
+(
+    size_t nargs,
+    ...
+)
+{
+    va_list args;
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_VA_ARGS_USAGE("This is third party code. va_start macro from stdarg.h contains a violation to MISRA rule 20.7")
+    va_start(args, nargs);
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_VA_ARGS_USAGE()
+
+    mcuxCsslParamIntegrity_Checksum_t result = mcuxCsslParamIntegrity_InternalProtect(nargs, args);
+    va_end(args);
+    return result;
+}
+
+MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslParamIntegrity_Validate)
+MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslParamIntegrity_Checksum_t) mcuxCsslParamIntegrity_Validate
+(
+    mcuxCsslParamIntegrity_Checksum_t chk,
+    size_t nargs,
+    ...
+)
+{
+    MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslParamIntegrity_Validate);
+
+    va_list args;
+    MCUX_CSSL_ANALYSIS_START_SUPPRESS_VA_ARGS_USAGE("This is third party code. va_start macro from stdarg.h contains a violation to MISRA rule 20.7")
+    va_start(args, nargs);
+    MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_VA_ARGS_USAGE()
+
+    mcuxCsslParamIntegrity_Checksum_t recalculatedChecksum = mcuxCsslParamIntegrity_InternalProtect(nargs, args);
+    va_end(args);
+
+    MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslParamIntegrity_Validate,
+        (recalculatedChecksum == chk) ? MCUXCSSLPARAMINTEGRITY_CHECK_VALID : MCUXCSSLPARAMINTEGRITY_CHECK_INVALID
+    );
+}
+
+MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_STDARG_USAGE()
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter.h
new file mode 100644
index 0000000000..376f005dcd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter.h
@@ -0,0 +1,304 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * @file  mcuxCsslSecureCounter.h
+ * @brief Provides the API for the CSSL secure counter mechanism.
+ */
+
+#ifndef MCUXCSSLSECURECOUNTER_H_
+#define MCUXCSSLSECURECOUNTER_H_
+
+/* Include the actual implementation of the secure counter mechanism. */
+#include <mcuxCsslSecureCounter_Impl.h>
+
+/**
+ * @addtogroup mcuxCsslAPI MCUX CSSL -- API
+ *
+ * @defgroup mcuxCsslSecureCounter Secure Counter API
+ * @brief Secure counter mechanism.
+ * @ingroup mcuxCsslAPI
+ */
+
+
+/**
+ * @defgroup scCore Secure counter core functionality
+ * @brief Secure counter handling core functionality.
+ * @ingroup mcuxCsslSecureCounter
+ *
+ * @todo Extend this description of the core functionality.
+ */
+
+/****************************************************************************/
+/* Constants                                                                */
+/****************************************************************************/
+
+/**
+ * @def MCUX_CSSL_SC_CHECK_PASSED
+ * @brief Positive comparison result value.
+ * @api
+ * @ingroup scCore
+ */
+#define MCUX_CSSL_SC_CHECK_PASSED \
+  MCUX_CSSL_SC_CHECK_PASSED_IMPL
+
+/**
+ * @def MCUX_CSSL_SC_CHECK_FAILED
+ * @brief Negative comparison result value.
+ * @api
+ * @ingroup scCore
+ */
+#define MCUX_CSSL_SC_CHECK_FAILED \
+  MCUX_CSSL_SC_CHECK_FAILED_IMPL
+
+/**
+ * @def MCUX_CSSL_SC_VALUE_TYPE
+ * @brief Data type used for the secure counter values.
+ * @api
+ * @ingroup scCore
+ */
+#define MCUX_CSSL_SC_VALUE_TYPE \
+  MCUX_CSSL_SC_VALUE_TYPE_IMPL
+
+/****************************************************************************/
+/* Initialization                                                           */
+/****************************************************************************/
+
+/**
+ * @def MCUX_CSSL_SC_ALLOC
+ * @brief Allocation operation for the secure counter.
+ * @api
+ * @ingroup scCore
+ */
+#define MCUX_CSSL_SC_ALLOC() \
+  MCUX_CSSL_SC_ALLOC_IMPL()
+
+/**
+ * @def MCUX_CSSL_SC_INIT
+ * @brief Initialization operation for the secure counter.
+ * @api
+ * @ingroup scCore
+ *
+ * @param value Value with which the secure counter must be initialized.
+ */
+#define MCUX_CSSL_SC_INIT(value) \
+  MCUX_CSSL_SC_INIT_IMPL(value)
+
+/****************************************************************************/
+/* Check                                                                    */
+/****************************************************************************/
+
+/**
+ * @def MCUX_CSSL_SC_CHECK
+ * @brief Comparison operation for the secure counter.
+ * @api
+ * @ingroup scCore
+ *
+ * @param reference Reference value to compare the secure counter value against.
+ * @return          Either #MCUX_CSSL_SC_CHECK_PASSED, if the value matches, or
+ *                  #MCUX_CSSL_SC_CHECK_FAILED if the value is different.
+ */
+#define MCUX_CSSL_SC_CHECK(reference) \
+  MCUX_CSSL_SC_CHECK_IMPL(reference)
+
+/****************************************************************************/
+/* Counter increment                                                        */
+/****************************************************************************/
+/**
+ * @defgroup scInc Secure counter increment
+ * @brief Support for incrementing the secure counter.
+ * @ingroup mcuxCsslSecureCounter
+ */
+
+/**
+ * @def MCUX_CSSL_SC_ADD
+ * @brief Increment the secure counter with @p value.
+ * @api
+ * @ingroup scInc
+ *
+ * @see MCUX_CSSL_SC_ADD_0x1
+ * @see MCUX_CSSL_SC_ADD_0x10
+ * @see MCUX_CSSL_SC_ADD_0x100
+ * @see MCUX_CSSL_SC_SUB
+ *
+ * @param value Value with which the secure counter must be incremented.
+ */
+#define MCUX_CSSL_SC_ADD(value) \
+  MCUX_CSSL_SC_ADD_IMPL(value)
+
+/**
+ * @def MCUX_CSSL_SC_ADD_ON_CALL
+ * @brief Increment the secure counter with @p value in case of function call.
+ * @api
+ * @ingroup scInc
+ *
+ * @see MCUX_CSSL_SC_ADD
+ *
+ * @param value Value with which the secure counter must be incremented.
+ */
+#define MCUX_CSSL_SC_ADD_ON_CALL(value) \
+  MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value)
+
+/**
+ * @def MCUX_CSSL_SC_ADD_0x1
+ * @brief Increment the secure counter with 0x1.
+ * @api
+ * @ingroup scInc
+ *
+ * @see MCUX_CSSL_SC_ADD
+ * @see MCUX_CSSL_SC_ADD_0x10
+ * @see MCUX_CSSL_SC_ADD_0x100
+ * @see MCUX_CSSL_SC_SUB_0x1
+ */
+#define MCUX_CSSL_SC_ADD_0x1() \
+  MCUX_CSSL_SC_ADD_0x1_IMPL()
+
+/**
+ * @def MCUX_CSSL_SC_ADD_0x10
+ * @brief Increment the secure counter with 0x10.
+ * @api
+ * @ingroup scInc
+ *
+ * @see MCUX_CSSL_SC_ADD
+ * @see MCUX_CSSL_SC_ADD_0x1
+ * @see MCUX_CSSL_SC_ADD_0x100
+ * @see MCUX_CSSL_SC_SUB_0x10
+ */
+#define MCUX_CSSL_SC_ADD_0x10() \
+  MCUX_CSSL_SC_ADD_0x10_IMPL()
+
+/**
+ * @def MCUX_CSSL_SC_ADD_0x100
+ * @brief Increment the secure counter with 0x100.
+ * @api
+ * @ingroup scInc
+ *
+ * @see MCUX_CSSL_SC_ADD
+ * @see MCUX_CSSL_SC_ADD_0x1
+ * @see MCUX_CSSL_SC_ADD_0x10
+ * @see MCUX_CSSL_SC_SUB_0x100
+ */
+#define MCUX_CSSL_SC_ADD_0x100() \
+  MCUX_CSSL_SC_ADD_0x100_IMPL()
+
+/****************************************************************************/
+/* Counter decrement                                                        */
+/****************************************************************************/
+/**
+ * @defgroup scDec Secure counter decrement
+ * @brief Support for decrementing the secure counter.
+ * @ingroup mcuxCsslSecureCounter
+ */
+
+/**
+ * @def MCUX_CSSL_SC_SUB
+ * @brief Decrement the secure counter with @p value.
+ * @api
+ * @ingroup scDec
+ *
+ * @see MCUX_CSSL_SC_SUB_0x1
+ * @see MCUX_CSSL_SC_SUB_0x10
+ * @see MCUX_CSSL_SC_SUB_0x100
+ * @see MCUX_CSSL_SC_ADD
+ *
+ * @param value Value with which the secure counter must be decremented.
+ */
+#define MCUX_CSSL_SC_SUB(value) \
+  MCUX_CSSL_SC_SUB_IMPL(value)
+
+/**
+ * @def MCUX_CSSL_SC_SUB_0x1
+ * @brief Decrement the secure counter with 0x1.
+ * @api
+ * @ingroup scDec
+ *
+ * @see MCUX_CSSL_SC_SUB
+ * @see MCUX_CSSL_SC_SUB_0x10
+ * @see MCUX_CSSL_SC_SUB_0x100
+ * @see MCUX_CSSL_SC_ADD_0x1
+ */
+#define MCUX_CSSL_SC_SUB_0x1() \
+  MCUX_CSSL_SC_SUB_0x1_IMPL()
+
+/**
+ * @def MCUX_CSSL_SC_SUB_0x10
+ * @brief Decrement the secure counter with 0x10.
+ * @api
+ * @ingroup scDec
+ *
+ * @see MCUX_CSSL_SC_SUB
+ * @see MCUX_CSSL_SC_SUB_0x1
+ * @see MCUX_CSSL_SC_SUB_0x100
+ * @see MCUX_CSSL_SC_ADD_0x10
+ */
+#define MCUX_CSSL_SC_SUB_0x10() \
+  MCUX_CSSL_SC_SUB_0x10_IMPL()
+
+/**
+ * @def MCUX_CSSL_SC_SUB_0x100
+ * @brief Decrement the secure counter with 0x100.
+ * @api
+ * @ingroup scDec
+ *
+ * @see MCUX_CSSL_SC_SUB
+ * @see MCUX_CSSL_SC_SUB_0x1
+ * @see MCUX_CSSL_SC_SUB_0x10
+ * @see MCUX_CSSL_SC_ADD_0x100
+ */
+#define MCUX_CSSL_SC_SUB_0x100() \
+  MCUX_CSSL_SC_SUB_0x100_IMPL()
+
+/****************************************************************************/
+/* Direct access (optional)                                                 */
+/****************************************************************************/
+/**
+ * @defgroup scDirect Secure counter direct access
+ * @brief Support for directly accessing the secure counter.
+ * @ingroup mcuxCsslSecureCounter
+ *
+ * @warning Access to the secure counter is generally restricted, and generic
+ * access might not be allowed.
+ */
+
+/**
+ * @def MCUX_CSSL_SC_VALUE
+ * @brief Access operation for the current secure counter value.
+ * @api
+ * @ingroup scDirect
+ *
+ * @warning Access to the secure counter is generally restricted, and generic
+ * access might not be allowed. For portable code it is best to only rely on
+ * the check operation to verify the secure counter value.
+ *
+ * @return The current value of the secure counter.
+ */
+#define MCUX_CSSL_SC_VALUE() \
+  MCUX_CSSL_SC_VALUE_IMPL()
+
+/**
+ * @def MCUX_CSSL_SC_ASSIGN
+ * @brief Assignment operation for the secure counter.
+ * @api
+ * @ingroup scDirect
+ *
+ * @warning Access to the secure counter is generally restricted, and generic
+ * assignment might not be allowed. For portable code it is best to only rely
+ * on the initialization, increment and decrement operations to change the
+ * secure counter value.
+ *
+ * @param value Value that needs to be assigned to the secure counter.
+ */
+#define MCUX_CSSL_SC_ASSIGN(value) \
+  MCUX_CSSL_SC_ASSIGN_IMPL(value)
+
+#endif /* MCUXCSSLSECURECOUNTER_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Cfg.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Cfg.h
new file mode 100644
index 0000000000..8e71486676
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Cfg.h
@@ -0,0 +1,103 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslSecureCounter_Cfg.h
+ * \brief Configuration of the implementation for the secure counter mechanism.
+ */
+
+#ifndef MCUXCSSLSECURECOUNTER_CFG_H_
+#define MCUXCSSLSECURECOUNTER_CFG_H_
+
+/**
+ * \addtogroup mcuxCsslCFG MCUX CSSL -- Configurations
+ *
+ * \defgroup mcuxCsslSecureCounter_CFG Secure Counter Configuration
+ * \brief Configuration options for the secure counter mechanism.
+ * \ingroup mcuxCsslCFG
+ */
+
+/**
+ * \def MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG
+ * \brief If set to 1, use the hybrid secure counter mechanism implementation based on
+ *        a SW counter stored in a local variable and the code watchdog (CDOG) HW IP block.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG      0
+
+/**
+ * \def MCUX_CSSL_SC_USE_HW_CDOG
+ * \brief If set to 1, use the secure counter mechanism implementation based on
+ *        the code watchdog (CDOG) HW IP block.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_HW_CDOG      0
+
+/**
+ * \def MCUX_CSSL_SC_USE_HW_SCM
+ * \brief If set to 1, use the secure counter mechanism implementation based on
+ *        the subsystem control module (SCM) HW IP block.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_HW_SCM      0
+
+/**
+ * \def MCUX_CSSL_SC_USE_HW_S3SCM
+ * \brief If set to 1, use the secure counter mechanism implementation based on
+ *        the subsystem control module (S3SCM) HW IP block.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_HW_S3SCM      0
+
+/**
+ * \def MCUX_CSSL_SC_USE_SW_LOCAL
+ * \brief If set to 1, use the secure counter mechanism implementation based on
+ *        a SW counter stored in a local variable.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_SW_LOCAL    1
+
+/**
+ * \def MCUX_CSSL_SC_USE_SW_CONTEXT
+ * \brief If set to 1, use the secure counter mechanism implementation based on
+ *        a SW counter stored in a context structure.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_SW_CONTEXT    0
+
+/**
+ * \def MCUX_CSSL_SC_USE_SW_CALLBACK
+ * \brief If set to 1, use the secure counter mechanism implementation based on
+ *        a SW counter pointed to through a callback function.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_SW_CALLBACK    0
+
+/**
+ * \def MCUX_CSSL_SC_USE_SW_GLOBAL
+ * \brief If set to 1, use the secure counter mechanism implementation based on
+ *        a SW counter stored in a global variable.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_SW_GLOBAL    0
+
+/**
+ * \def MCUX_CSSL_SC_USE_NONE
+ * \brief If set to 1, do not use the secure counter mechanism.
+ * \ingroup mcuxCsslSecureCounter_CFG
+ */
+    #define MCUX_CSSL_SC_USE_NONE    0
+
+/* Basic configuration sanity check */
+
+#endif /* MCUXCSSLSECURECOUNTER_CFG_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Impl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Impl.h
new file mode 100644
index 0000000000..f263a98a83
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Impl.h
@@ -0,0 +1,52 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslSecureCounter_Impl.h
+ * \brief Selection of the implementation for the secure counter mechanism.
+ */
+
+#ifndef MCUXCSSLSECURECOUNTER_IMPL_H_
+#define MCUXCSSLSECURECOUNTER_IMPL_H_
+
+/* Include the configuration for the secure counter mechanism. */
+#include <mcuxCsslSecureCounter_Cfg.h>
+
+/* Include the selected implementation of the secure counter mechanism. */
+#if defined(MCUX_CSSL_SC_USE_HW_CDOG) && (1 == MCUX_CSSL_SC_USE_HW_CDOG)
+  #include <mcuxCsslSecureCounter_HardwareAddresses.h>
+  #include <mcuxCsslSecureCounter_HW_CDOG.h>
+#elif defined(MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG) && (1 == MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG)
+  #include <mcuxCsslSecureCounter_HardwareAddresses.h>
+  #include <mcuxCsslSecureCounter_Hybrid_LocalCDOG.h>
+#elif defined(MCUX_CSSL_SC_USE_HW_S3SCM) && (1 == MCUX_CSSL_SC_USE_HW_S3SCM)
+  #include <mcuxCsslSecureCounter_HardwareAddresses.h>
+  #include <mcuxCsslSecureCounter_HW_S3SCM.h>
+#elif defined(MCUX_CSSL_SC_USE_HW_SCM) && (1 == MCUX_CSSL_SC_USE_HW_SCM)
+  #include <mcuxCsslSecureCounter_HardwareAddresses.h>
+  #include <mcuxCsslSecureCounter_HW_SCM.h>
+#elif defined(MCUX_CSSL_SC_USE_SW_LOCAL) && (1 == MCUX_CSSL_SC_USE_SW_LOCAL)
+  #include <mcuxCsslSecureCounter_SW_Local.h>
+#elif defined(MCUX_CSSL_SC_USE_SW_CONTEXT) && (1 == MCUX_CSSL_SC_USE_SW_CONTEXT)
+  #include <mcuxCsslSecureCounter_SW_Context.h>
+#elif defined(MCUX_CSSL_SC_USE_SW_CALLBACK) && (1 == MCUX_CSSL_SC_USE_SW_CALLBACK)
+  #include <mcuxCsslSecureCounter_SW_Callback.h>
+#elif defined(MCUX_CSSL_SC_USE_SW_GLOBAL) && (1 == MCUX_CSSL_SC_USE_SW_GLOBAL)
+  #include <mcuxCsslSecureCounter_SW_Global.h>
+#elif defined(MCUX_CSSL_SC_USE_NONE) && (1 == MCUX_CSSL_SC_USE_NONE)
+  #include <mcuxCsslSecureCounter_None.h>
+#else
+  #error "No secure counter implementation found/configured."
+#endif
+
+#endif /* MCUXCSSLSECURECOUNTER_IMPL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_None.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_None.h
new file mode 100644
index 0000000000..16148f967c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_None.h
@@ -0,0 +1,274 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslSecureCounter_None.h
+ * \brief Implementation that disables the CSSL secure counter mechanism.
+ */
+
+#ifndef MCUXCSSLSECURECOUNTER_NONE_H_
+#define MCUXCSSLSECURECOUNTER_NONE_H_
+
+/**
+ * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations
+ *
+ * \defgroup mcuxCsslSecureCounter_None Secure Counter: Disabled
+ * \brief Disable the secure counter mechanism.
+ * \ingroup mcuxCsslIMPL
+ */
+
+
+/**
+ * \defgroup scNoneCore Secure counter core functionality
+ * \brief Secure counter handling core functionality.
+ * \ingroup mcuxCsslSecureCounter_None
+ *
+ * \todo Extend this description of the core functionality.
+ */
+
+/****************************************************************************/
+/* Constants                                                                */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_SC_CHECK_PASSED_IMPL
+ * \brief Positive comparison result value.
+ * \ingroup scNoneCore
+ */
+#define MCUX_CSSL_SC_CHECK_PASSED_IMPL (0xA5A5A5A5u)
+
+/**
+ * \def MCUX_CSSL_SC_CHECK_FAILED_IMPL
+ * \brief Negative comparison result value.
+ * \ingroup scNoneCore
+ */
+#define MCUX_CSSL_SC_CHECK_FAILED_IMPL (~ MCUX_CSSL_SC_CHECK_PASSED_IMPL)
+
+/**
+ * \def MCUX_CSSL_SC_COUNTER_TYPE_IMPL
+ * \brief Data type used for the secure counter.
+ * \ingroup scNoneCore
+ */
+#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL \
+  uint32_t
+
+/**
+ * \def MCUX_CSSL_SC_VALUE_TYPE_IMPL
+ * \brief Data type used for the secure counter values.
+ * \ingroup scNoneCore
+ */
+#define MCUX_CSSL_SC_VALUE_TYPE_IMPL \
+  static const uint32_t
+
+/**
+ * \def MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
+ * \brief Data type used for properly casting the secure counter balancing values.
+ * \ingroup scNoneCore
+ */
+#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL \
+  uint32_t
+
+/****************************************************************************/
+/* Initialization                                                           */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_SC_ALLOC_IMPL
+ * \brief Allocation operation implementation for the secure counter.
+ * \ingroup scNoneCore
+ */
+#define MCUX_CSSL_SC_ALLOC_IMPL() \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_INIT_IMPL
+ * \brief Initialization operation implementation for the secure counter.
+ * \ingroup scNoneCore
+ *
+ * \param value Value with which the secure counter must be initialized.
+ */
+#define MCUX_CSSL_SC_INIT_IMPL(value) \
+  /* intentionally empty */
+
+/****************************************************************************/
+/* Check                                                                    */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_SC_CHECK_IMPL
+ * \brief Comparison operation implementation for the secure counter.
+ * \ingroup scNoneCore
+ *
+ * \param reference Reference value to compare the secure counter value against.
+ * \return          Always #MCUX_CSSL_SC_CHECK_PASSED.
+ */
+#define MCUX_CSSL_SC_CHECK_IMPL(value) \
+  (MCUX_CSSL_SC_CHECK_PASSED_IMPL)
+
+/****************************************************************************/
+/* Counter increment                                                        */
+/****************************************************************************/
+/**
+ * \defgroup scNoneInc Secure counter increment
+ * \brief Support for incrementing the secure counter.
+ * \ingroup mcuxCsslSecureCounter_None
+ */
+
+/**
+ * \def MCUX_CSSL_SC_ADD_IMPL
+ * \brief Increment the secure counter with \p value.
+ * \ingroup scNoneInc
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ *
+ * \param value Value with which the secure counter must be incremented.
+ */
+#define MCUX_CSSL_SC_ADD_IMPL(value) \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_ADD_ON_CALL_IMPL
+ * \brief Increment the secure counter with \p value in case of function call.
+ * \ingroup scNoneInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ *
+ * \param value Value with which the secure counter must be incremented.
+ */
+#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value) \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_ADD_0X1_IMPL
+ * \brief Increment the secure counter with 0x1.
+ * \ingroup scNoneInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ */
+#define MCUX_CSSL_SC_ADD_0X1_IMPL() \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_ADD_0X10_IMPL
+ * \brief Increment the secure counter with 0x10.
+ * \ingroup scNoneInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ */
+#define MCUX_CSSL_SC_ADD_0X10_IMPL() \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_ADD_0X100_IMPL
+ * \brief Increment the secure counter with 0x100.
+ * \ingroup scNoneInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ */
+#define MCUX_CSSL_SC_ADD_0X100_IMPL() \
+  /* intentionally empty */
+
+/****************************************************************************/
+/* Counter decrement                                                        */
+/****************************************************************************/
+/**
+ * \defgroup scNoneDec Secure counter decrement
+ * \brief Support for decrementing the secure counter.
+ * \ingroup mcuxCsslSecureCounter_None
+ */
+
+/**
+ * \def MCUX_CSSL_SC_SUB_IMPL
+ * \brief Decrement the secure counter with \p value.
+ * \ingroup scNoneDec
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ *
+ * \param value Value with which the secure counter must be decremented.
+ */
+#define MCUX_CSSL_SC_SUB_IMPL(value) \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_SUB_0X1_IMPL
+ * \brief Decrement the secure counter with 0x1.
+ * \ingroup scNoneDec
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ */
+#define MCUX_CSSL_SC_SUB_0X1_IMPL() \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_SUB_0X10_IMPL
+ * \brief Decrement the secure counter with 0x10.
+ * \ingroup scNoneDec
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ */
+#define MCUX_CSSL_SC_SUB_0X10_IMPL() \
+  /* intentionally empty */
+
+/**
+ * \def MCUX_CSSL_SC_SUB_0X100_IMPL
+ * \brief Decrement the secure counter with 0x100.
+ * \ingroup scNoneDec
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ */
+#define MCUX_CSSL_SC_SUB_0X100_IMPL() \
+  /* intentionally empty */
+
+/****************************************************************************/
+/* Direct access (optional)                                                 */
+/****************************************************************************/
+/**
+ * \defgroup scNoneDirect Secure counter direct access
+ * \brief Support for directly accessing the secure counter.
+ * \ingroup mcuxCsslSecureCounter_None
+ *
+ * \warning Access to the secure counter is generally restricted, and generic
+ * access might not be allowed.
+ */
+
+/**
+ * \def MCUX_CSSL_SC_VALUE_IMPL
+ * \brief Access operation for the current secure counter value.
+ * \ingroup scNoneDirect
+ *
+ * \warning Access to the secure counter is generally restricted, and generic
+ * access might not be allowed. For portable code it is best to only rely on
+ * the check operation to verify the secure counter value.
+ *
+ * \return The current value of the secure counter.
+ */
+#define MCUX_CSSL_SC_VALUE_IMPL() \
+  1/0 /* not supported */
+
+/**
+ * \def MCUX_CSSL_SC_ASSIGN_IMPL
+ * \brief Assignment operation for the secure counter.
+ * \ingroup scNoneDirect
+ *
+ * \warning Access to the secure counter is generally restricted, and generic
+ * assignment might not be allowed. For portable code it is best to only rely
+ * on the initialization, increment and decrement operations to change the
+ * secure counter value.
+ *
+ * \param value Value that needs to be assigned to the secure counter.
+ */
+#define MCUX_CSSL_SC_ASSIGN_IMPL(value) \
+  /* intentionally empty */
+
+
+#endif /* MCUXCSSLSECURECOUNTER_NONE_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_SW_Local.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_SW_Local.h
new file mode 100644
index 0000000000..ed3a3bfd85
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_SW_Local.h
@@ -0,0 +1,293 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2020-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/**
+ * \file  mcuxCsslSecureCounter_SW_Local.h
+ * \brief SW implementation of the CSSL secure counter mechanism (using a local
+ *        variable).
+ */
+
+#ifndef MCUXCSSLSECURECOUNTER_SW_LOCAL_H_
+#define MCUXCSSLSECURECOUNTER_SW_LOCAL_H_
+
+/**
+ * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations
+ *
+ * \defgroup mcuxCsslSecureCounter_SwLocal Secure Counter: SW Local
+ * \brief Secure counter mechanism implementation using a local variable.
+ * \ingroup mcuxCsslIMPL
+ */
+
+
+/**
+ * \defgroup scSwlCore Secure counter core functionality
+ * \brief Secure counter handling core functionality.
+ * \ingroup mcuxCsslSecureCounter_SwLocal
+ *
+ * \todo Extend this description of the core functionality.
+ */
+
+/**
+ * \def MCUX_CSSL_SC_COUNTER_NAME
+ * \brief Variable name to use for storing the secure counter value.
+ * \ingroup scSwlCore
+ */
+#define MCUX_CSSL_SC_COUNTER_NAME \
+  mcuxCsslSecureCounter
+
+/****************************************************************************/
+/* Constants                                                                */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_SC_CHECK_PASSED_IMPL
+ * \brief Positive comparison result value.
+ * \ingroup scSwlCore
+ */
+#define MCUX_CSSL_SC_CHECK_PASSED_IMPL (0xA5A5A5A5u)
+
+/**
+ * \def MCUX_CSSL_SC_CHECK_FAILED_IMPL
+ * \brief Negative comparison result value.
+ * \ingroup scSwlCore
+ */
+#define MCUX_CSSL_SC_CHECK_FAILED_IMPL (~ MCUX_CSSL_SC_CHECK_PASSED_IMPL)
+
+/**
+ * \def MCUX_CSSL_SC_COUNTER_TYPE_IMPL
+ * \brief Data type used for the secure counter.
+ * \ingroup scSwlCore
+ */
+#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL \
+  uint32_t
+
+/**
+ * \def MCUX_CSSL_SC_VALUE_TYPE_IMPL
+ * \brief Data type used for the secure counter values.
+ * \ingroup scSwlCore
+ */
+#define MCUX_CSSL_SC_VALUE_TYPE_IMPL \
+  static const uint32_t
+
+/**
+ * \def MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
+ * \brief Data type used for properly casting the secure counter balancing values.
+ * \ingroup scSwlCore
+ */
+#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL \
+  uint32_t
+
+/****************************************************************************/
+/* Initialization                                                           */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_SC_ALLOC_IMPL
+ * \brief Allocation operation implementation for the secure counter.
+ * \ingroup scSwlCore
+ */
+#define MCUX_CSSL_SC_ALLOC_IMPL() \
+  MCUX_CSSL_SC_COUNTER_TYPE_IMPL MCUX_CSSL_SC_COUNTER_NAME
+
+/**
+ * \def MCUX_CSSL_SC_INIT_IMPL
+ * \brief Initialization operation implementation for the secure counter.
+ * \ingroup scSwlCore
+ *
+ * \param value Value with which the secure counter must be initialized.
+ */
+#define MCUX_CSSL_SC_INIT_IMPL(value) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_SC_ALLOC_IMPL() = ((MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value)) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+/****************************************************************************/
+/* Check                                                                    */
+/****************************************************************************/
+
+/**
+ * \def MCUX_CSSL_SC_CHECK_IMPL
+ * \brief Comparison operation implementation for the secure counter.
+ * \ingroup scSwlCore
+ *
+ * \param value     Reference value to compare the secure counter value against.
+ * \return          Either #MCUX_CSSL_SC_CHECK_PASSED, if the value matches, or
+ *                  #MCUX_CSSL_SC_CHECK_FAILED if the value is different.
+ */
+#define MCUX_CSSL_SC_CHECK_IMPL(value) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  (MCUX_CSSL_SC_CHECK_FAILED_IMPL ^ (MCUX_CSSL_SC_COUNTER_NAME - (((MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value)) + 1u))) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+/****************************************************************************/
+/* Counter increment                                                        */
+/****************************************************************************/
+/**
+ * \defgroup scSwlInc Secure counter increment
+ * \brief Support for incrementing the secure counter.
+ * \ingroup mcuxCsslSecureCounter_SwLocal
+ */
+
+/**
+ * \def MCUX_CSSL_SC_ADD_IMPL
+ * \brief Increment the secure counter with \p value.
+ * \ingroup scSwlInc
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ *
+ * \param value Value with which the secure counter must be incremented.
+ */
+#define MCUX_CSSL_SC_ADD_IMPL(value) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_SC_COUNTER_NAME += (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+/**
+ * \def MCUX_CSSL_SC_ADD_ON_CALL_IMPL
+ * \brief Increment the secure counter with \p value in case of function call.
+ * \ingroup scSwlInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ *
+ * \param value Value with which the secure counter must be incremented.
+ */
+#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value) \
+  MCUX_CSSL_SC_ADD_IMPL(value)
+
+/**
+ * \def MCUX_CSSL_SC_ADD_0X1_IMPL
+ * \brief Increment the secure counter with 0x1.
+ * \ingroup scSwlInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ */
+#define MCUX_CSSL_SC_ADD_0X1_IMPL() \
+  MCUX_CSSL_SC_ADD_IMPL(0x1u)
+
+/**
+ * \def MCUX_CSSL_SC_ADD_0X10_IMPL
+ * \brief Increment the secure counter with 0x10.
+ * \ingroup scSwlInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ */
+#define MCUX_CSSL_SC_ADD_0X10_IMPL() \
+  MCUX_CSSL_SC_ADD_IMPL(0x10u)
+
+/**
+ * \def MCUX_CSSL_SC_ADD_0X100_IMPL
+ * \brief Increment the secure counter with 0x100.
+ * \ingroup scSwlInc
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ */
+#define MCUX_CSSL_SC_ADD_0X100_IMPL() \
+  MCUX_CSSL_SC_ADD_IMPL(0x100u)
+
+/****************************************************************************/
+/* Counter decrement                                                        */
+/****************************************************************************/
+/**
+ * \defgroup scSwlDec Secure counter decrement
+ * \brief Support for decrementing the secure counter.
+ * \ingroup mcuxCsslSecureCounter_SwLocal
+ */
+
+/**
+ * \def MCUX_CSSL_SC_SUB_IMPL
+ * \brief Decrement the secure counter with \p value.
+ * \ingroup scSwlDec
+ *
+ * \see MCUX_CSSL_SC_ADD_IMPL
+ *
+ * \param value Value with which the secure counter must be decremented.
+ */
+#define MCUX_CSSL_SC_SUB_IMPL(value) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_SC_COUNTER_NAME -= (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+/**
+ * \def MCUX_CSSL_SC_SUB_0X1_IMPL
+ * \brief Decrement the secure counter with 0x1.
+ * \ingroup scSwlDec
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ */
+#define MCUX_CSSL_SC_SUB_0X1_IMPL() \
+  MCUX_CSSL_SC_SUB_IMPL(0x1u)
+
+/**
+ * \def MCUX_CSSL_SC_SUB_0X10_IMPL
+ * \brief Decrement the secure counter with 0x10.
+ * \ingroup scSwlDec
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ */
+#define MCUX_CSSL_SC_SUB_0X10_IMPL() \
+  MCUX_CSSL_SC_SUB_IMPL(0x10u)
+
+/**
+ * \def MCUX_CSSL_SC_SUB_0X100_IMPL
+ * \brief Decrement the secure counter with 0x100.
+ * \ingroup scSwlDec
+ *
+ * \see MCUX_CSSL_SC_SUB_IMPL
+ */
+#define MCUX_CSSL_SC_SUB_0X100_IMPL() \
+  MCUX_CSSL_SC_SUB_IMPL(0x100u)
+
+/****************************************************************************/
+/* Direct access (optional)                                                 */
+/****************************************************************************/
+/**
+ * \defgroup scSwlDirect Secure counter direct access
+ * \brief Support for directly accessing the secure counter.
+ * \ingroup mcuxCsslSecureCounter_SwLocal
+ *
+ * \warning Access to the secure counter is generally restricted, and generic
+ * access might not be allowed.
+ */
+
+/**
+ * \def MCUX_CSSL_SC_VALUE_IMPL
+ * \brief Access operation for the current secure counter value.
+ * \ingroup scSwlDirect
+ *
+ * \warning Access to the secure counter is generally restricted, and generic
+ * access might not be allowed. For portable code it is best to only rely on
+ * the check operation to verify the secure counter value.
+ *
+ * \return The current value of the secure counter.
+ */
+#define MCUX_CSSL_SC_VALUE_IMPL() \
+  MCUX_CSSL_SC_COUNTER_NAME
+
+/**
+ * \def MCUX_CSSL_SC_ASSIGN_IMPL
+ * \brief Assignment operation for the secure counter.
+ * \ingroup scSwlDirect
+ *
+ * \warning Access to the secure counter is generally restricted, and generic
+ * assignment might not be allowed. For portable code it is best to only rely
+ * on the initialization, increment and decrement operations to change the
+ * secure counter value.
+ *
+ * \param value Value that needs to be assigned to the secure counter.
+ */
+#define MCUX_CSSL_SC_ASSIGN_IMPL(value) \
+  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
+  MCUX_CSSL_SC_COUNTER_NAME = (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \
+  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
+
+#endif /* MCUXCSSLSECURECOUNTER_SW_LOCAL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_css_constants.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_css_constants.h
new file mode 100644
index 0000000000..989c88a5ec
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_css_constants.h
@@ -0,0 +1,53 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2018 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/********************************************************************************************************
+ * @file     ip_css_constants.h
+ *
+ * @brief    Additional register count constants for ip_css.
+ *
+ * @version  $Revision: $
+ * @date     8. October 2020
+ *
+ * @note     Generated with csv2a_create_cmsis_cheader V1.41
+ *
+ * @note     This File is NOT CMSIS compliant.
+ *******************************************************************************************************/
+
+
+
+#ifndef ip_css_CONSTANTS_H
+#define ip_css_CONSTANTS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ================================================================================ */
+/* ================        'ip_css' register names counting        ================ */
+/* ================================================================================ */
+
+#define CSS_DMA_SRC_CNT               3UL
+#define CSS_KIDX_CNT                  2UL
+#define CSS_KS_CNT                    20UL
+#define CSS_SHA2_DOUT_CNT             16UL
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* ip_css_CONSTANTS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_css_design_configuration.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_css_design_configuration.h
new file mode 100644
index 0000000000..3f1f19d427
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_css_design_configuration.h
@@ -0,0 +1,110 @@
+// CSS COMMAND LIST
+// **** --> processing include file 'config_css_commands.txt'
+// 
+// 
+// List of commands available in CSS
+// 
+#define ID_CFG_CSS_CMD_CIPHER 0
+#define ID_CFG_CSS_CMD_AUTH_CIPHER 1
+#define ID_CFG_CSS_CMD_RFU_0 2
+#define ID_CFG_CSS_CMD_RFU_1 3
+#define ID_CFG_CSS_CMD_ECSIGN 4
+#define ID_CFG_CSS_CMD_ECVFY 5
+#define ID_CFG_CSS_CMD_ECKXH 6
+#define ID_CFG_CSS_CMD_RFU_2 7
+#define ID_CFG_CSS_CMD_KEYGEN 8
+#define ID_CFG_CSS_CMD_KEYIN 9
+#define ID_CFG_CSS_CMD_KEYOUT 10
+#define ID_CFG_CSS_CMD_KDELETE 11
+#define ID_CFG_CSS_CMD_KEYPROV 12
+#define ID_CFG_CSS_CMD_RFU_4 13
+#define ID_CFG_CSS_CMD_RFU_5 14
+#define ID_CFG_CSS_CMD_RFU_6 15
+#define ID_CFG_CSS_CMD_CKDF 16
+#define ID_CFG_CSS_CMD_HKDF 17
+#define ID_CFG_CSS_CMD_TLS 18
+#define ID_CFG_CSS_CMD_RFU_7 19
+#define ID_CFG_CSS_CMD_HASH 20
+#define ID_CFG_CSS_CMD_HMAC 21
+#define ID_CFG_CSS_CMD_CMAC 22
+#define ID_CFG_CSS_CMD_RFU_9 23
+#define ID_CFG_CSS_CMD_DRBG_REQ 24
+#define ID_CFG_CSS_CMD_DRBG_TEST 25
+#define ID_CFG_CSS_CMD_RFU_11 26
+#define ID_CFG_CSS_CMD_RFU_12 27
+#define ID_CFG_CSS_CMD_DTRNG_CFG_LOAD 28
+#define ID_CFG_CSS_CMD_DTRNG_EVAL 29
+#define ID_CFG_CSS_CMD_GDET_CFG_LOAD 30
+#define ID_CFG_CSS_CMD_GDET_TRIM 31
+// Command Configurations
+// ID_CFG_CSS_CMD_CIPHER
+#define ID_CFG_CSS_CMD_CIPHER_DCRYPT 1
+#define ID_CFG_CSS_CMD_CIPHER_CPHMDE0 2
+#define ID_CFG_CSS_CMD_CIPHER_CPHMDE1 3
+#define ID_CFG_CSS_CMD_CIPHER_CPHSOE 4
+#define ID_CFG_CSS_CMD_CIPHER_CPHSIE 5
+#define ID_CFG_CSS_CMD_CIPHER_EXTKEY 13
+// ID_CFG_CSS_CMD_AUTH_CIPHER
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_DCRYPT 1
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_ACPMOD0 2
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_ACPMOD1 3
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_CPHSOE 4
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_CPHSIE 5
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW0 6
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW1 7
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW2 8
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW3 9
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_LASTINIT 10
+#define ID_CFG_CSS_CMD_AUTH_CIPHER_EXTKEY 13
+// ID_CFG_CSS_CMD_ECSIGN
+#define ID_CFG_CSS_CMD_ECSIGN_CFG_ECHASHCHL 0
+#define ID_CFG_CSS_CMD_ECSIGN_CFG_SIGNRTF 1
+#define ID_CFG_CSS_CMD_ECSIGN_CFG_REVF 4
+// ID_CFG_CSS_CMD_ECVFY
+#define ID_CFG_CSS_CMD_ECVFY_CFG_ECHASHCHL 0
+#define ID_CFG_CSS_CMD_ECVFY_CFG_REVF 4
+// ID_CFG_CSS_CMD_ECKXH
+#define ID_CFG_CSS_CMD_ECKXH_REVF 4
+// ID_CFG_CSS_CMD_KEYGEN
+#define ID_CFG_CSS_CMD_KEYGEN_KGSIGN 0
+#define ID_CFG_CSS_CMD_KEYGEN_KGTYPEDH 1
+#define ID_CFG_CSS_CMD_KEYGEN_KGSRC 2
+#define ID_CFG_CSS_CMD_KEYGEN_SKIP_PBK 3
+#define ID_CFG_CSS_CMD_KEYGEN_REVF 4
+#define ID_CFG_CSS_CMD_KEYGEN_KGSIGN_RND 5
+// ID_CFG_CSS_CMD_KEYIN
+#define ID_CFG_CSS_CMD_KEYIN_KFMT0 6
+#define ID_CFG_CSS_CMD_KEYIN_KFMT1 7
+// ID_CFG_CSS_CMD_KEYPROV
+#define ID_CFG_CSS_CMD_KEYPROV_ICEN 0
+// ID_CFG_CSS_CMD_CKDF
+#define ID_CFG_CSS_CMD_CKDF_CKDF_ALGO0 12
+#define ID_CFG_CSS_CMD_CKDF_CKDF_ALGO1 13
+// ID_CFG_CSS_CMD_HKDF
+#define ID_CFG_CSS_CMD_HKDF_RTFDRVDAT 0
+#define ID_CFG_CSS_CMD_HKDF_HKDF_ALGO 1
+#define ID_CFG_CSS_CMD_HKDF_SINGLE_STEP 2
+// ID_CFG_CSS_CMD_TLS
+#define ID_CFG_CSS_CMD_TLS_FINALIZE 10
+// ID_CFG_CSS_CMD_HASH
+#define ID_CFG_CSS_CMD_HASH_HASHINI 2
+#define ID_CFG_CSS_CMD_HASH_HASHLD 3
+// ID_CFG_CSS_CMD_HASH_HASHMD0
+#define ID_CFG_CSS_CMD_HASH_HASHMD0 4
+// ID_CFG_CSS_CMD_HASH_HASHMD1
+#define ID_CFG_CSS_CMD_HASH_HASHMD1 5
+#define ID_CFG_CSS_CMD_HASH_HASHOE 6
+#define ID_CFG_CSS_CMD_HASH_RTFUPD 7
+#define ID_CFG_CSS_CMD_HASH_RTFOE 8
+// ID_CFG_CSS_CMD_HMAC
+#define ID_CFG_CSS_CMD_HMAC_EXTKEY 13
+// ID_CFG_CSS_CMD_CMAC
+#define ID_CFG_CSS_CMD_CMAC_INIT 0
+#define ID_CFG_CSS_CMD_CMAC_FINALIZE 1
+#define ID_CFG_CSS_CMD_CMAC_SOE 2
+#define ID_CFG_CSS_CMD_CMAC_SIE 3
+#define ID_CFG_CSS_CMD_CMAC_EXTKEY 13
+// ID_CFG_CSS_CMD_DRBG_TEST
+#define ID_CFG_CSS_CMD_DRBG_TEST_MODE0 0
+#define ID_CFG_CSS_CMD_DRBG_TEST_MODE1 1
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_platform.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_platform.h
new file mode 100644
index 0000000000..01c5affbda
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/inc/ip_platform.h
@@ -0,0 +1,83 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2022-2023 NXP                                                  */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+/** @file  ip_platform.h
+ *  @brief Include file for the IP.
+ *
+ * This file defines base addresses and types for all IP blocks used by CLNS. */
+
+#ifndef IP_PLATFORM_H
+#define IP_PLATFORM_H
+
+#include "fsl_device_registers.h"
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+// Define base address of PUF
+#define PUF_SFR_BASE            PUF      ///< base of PUF SFRs
+#define PUF_SFR_NAME(sfr)       sfr      ///< full name of SFR
+#define PUF_SFR_PREFIX          PUF_     ///< sfr field name prefix
+#define PUF_SFR_SUFFIX_MSK     _MASK       ///< sfr field name suffix for mask
+#define PUF_SFR_SUFFIX_POS     _SHIFT      ///< sfr field name suffix for bit position
+
+
+// Define base address of CSS
+#define ELS_SFR_BASE            ELS         ///< base of CSS SFRs
+#define ELS_SFR_NAME(sfr)       sfr         ///< full name of SFR
+#define ELS_SFR_PREFIX          ELS_        ///< sfr field name prefix
+
+// Define base address of PKC
+#define PKC_SFR_BASE            PKC         ///< base of PKC SFRs
+#define PKC_SFR_NAME(sfr)       PKC_ ## sfr ///< full name of SFR
+#define PKC_SFR_PREFIX          PKC_PKC_    ///< sfr field name prefix
+#define PKC_SFR_SUFFIX_MSK      _MASK       ///< sfr field name suffix for mask
+#define PKC_SFR_SUFFIX_POS      _SHIFT      ///< sfr field name suffix for bit position
+
+// PKC_RAM base address is not defined in any header file
+#define PKC_RAM_ADDR ((uint32_t) 0x5015A000)
+#define PKC_RAM_SIZE  ((uint32_t)0x2000u)
+#define PKC_WORD_SIZE  8u
+
+// Define base address of TRNG
+#define TRNG_SFR_BASE           TRNG         ///< base of TRNG SFRs
+#define TRNG_SFR_NAME(sfr)      sfr          ///< full name of SFR
+#define TRNG_SFR_PREFIX         TRNG_        ///< sfr field name prefix
+#define TRNG_SFR_SUFFIX_MSK     _MASK        ///< sfr field name suffix for mask
+#define TRNG_SFR_SUFFIX_POS     _SHIFT       ///< sfr field name suffix for bit position
+
+// ELS version
+#define ELS_HW_VERSION_REVISION            1
+#define ELS_HW_VERSION_MINOR               22
+#define ELS_HW_VERSION_MAJOR               2
+#define ELS_HW_VERSION_FW_REVISION         1
+#define ELS_HW_VERSION_FW_MINOR            2
+#define ELS_HW_VERSION_FW_MAJOR            1
+
+// Interrupt definitions
+#define CSS_INTERRUPT_BUSY_NUMBER          ELS_IRQn
+#define CSS_INTERRUPT_ERR_NUMBER           ELS_IRQn
+#define CSS_INTERRUPT_IRQ_NUMBER           ELS_IRQn
+#define GDET_INTERRUPT_IRQ_NUMBER          ELS_GDET_IRQ_IRQn
+#define GDET_INTERRUPT_ERR_NUMBER          ELS_GDET_ERR_IRQn
+
+
+/* If we are supposed to determine the CSSv2 base address at link time, do not use the definitions from ip_css.h
+ * Redefine CSS as an extern pointer.
+ */
+#undef CSS_BASE
+extern void * ip_css_base;
+#define CSS_BASE                     ip_css_base
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/mcuxClConfig.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/mcuxClConfig.h
new file mode 100644
index 0000000000..dfad6abb6e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/mcuxClConfig.h
@@ -0,0 +1,857 @@
+/*--------------------------------------------------------------------------*/
+/* Copyright 2023 NXP                                                       */
+/*                                                                          */
+/* NXP Confidential. This software is owned or controlled by NXP and may    */
+/* only be used strictly in accordance with the applicable license terms.   */
+/* By expressly accepting such terms or by downloading, installing,         */
+/* activating and/or otherwise using the software, you are agreeing that    */
+/* you have read, and that you agree to comply with and are bound by, such  */
+/* license terms. If you do not agree to be bound by the applicable license */
+/* terms, then you may not retain, install, activate or otherwise use the   */
+/* software.                                                                */
+/*--------------------------------------------------------------------------*/
+
+#ifndef MCUXCL_CONFIG_H_
+#define MCUXCL_CONFIG_H_
+
+//commented defines for all available features 
+//#define    MCUXCL_FEATURE_EXPORTED_FEATURE_HEADER
+//#define    MCUXCL_FEATURE_EXPORTED_PLATFORM_HEADERS
+//#define    MCUXCL_FEATURE_PLATFORM_RW61X
+//#define    MCUXCL_FEATURE_PLATFORM_MCXN
+//#define    MCUXCL_FEATURE_PLATFORM_LPC
+//#define    MCUXCL_FEATURE_PROJECT_VOLTA_ON_NIRVANA
+//#define    MCUXCL_FEATURE_PLATFORM_MIMXRT
+//#define    MCUXCL_FEATURE_PROJECT_BLACKBIRD
+//#define    MCUXCL_FEATURE_PROJECT_CSSL
+//#define    MCUXCL_FEATURE_PROJECT_NCCL
+//#define    MCUXCL_FEATURE_PROJECT_QUANTUM
+//#define    MCUXCL_FEATURE_PROJECT_SHARK
+//#define    MCUXCL_FEATURE_HW_ELS
+//#define    MCUXCL_FEATURE_HW_GDET
+//#define    MCUXCL_FEATURE_HW_GLIKEY
+//#define    MCUXCL_FEATURE_HW_PKC
+//#define    MCUXCL_FEATURE_HW_ROPUF
+//#define    MCUXCL_FEATURE_HW_SAFO_SM3
+//#define    MCUXCL_FEATURE_HW_SAFO_SM4
+//#define    MCUXCL_FEATURE_HW_SGI
+//#define    MCUXCL_FEATURE_HW_TRNG
+//#define    MCUXCL_FEATURE_HW_RISCV_ZBB
+//#define    MCUXCL_FEATURE_HW_RISCV_CSW
+//#define    MCUXCL_FEATURE_HW_CACHE_ENABLED
+//#define    MCUXCL_FEATURE_ELS
+//#define    MCUXCL_FEATURE_ELS_AEAD
+//#define    MCUXCL_FEATURE_ELS_API_INPUT_PARAM_CHECKS
+//#define    MCUXCL_FEATURE_ELS_CKDF
+//#define    MCUXCL_FEATURE_ELS_CKDF_SP80056C
+//#define    MCUXCL_FEATURE_ELS_CMAC
+//#define    MCUXCL_FEATURE_ELS_ECC_KEY_EXCHANGE
+//#define    MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD_EVEN
+//#define    MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD
+//#define    MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+//#define    MCUXCL_FEATURE_ELS_HKDF
+//#define    MCUXCL_FEATURE_ELS_HMAC
+//#define    MCUXCL_FEATURE_ELS_HWCONFIG
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT
+//#define    MCUXCL_FEATURE_ELS_KEY_EXPORT_SW_DFA_PROTECTION
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_TEST
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM_TEST
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE_TEST
+//#define    MCUXCL_FEATURE_ELS_RNG
+//#define    MCUXCL_FEATURE_ELS_SHA_224
+//#define    MCUXCL_FEATURE_ELS_SHA_256
+//#define    MCUXCL_FEATURE_ELS_SHA_384
+//#define    MCUXCL_FEATURE_ELS_SHA_512
+//#define    MCUXCL_FEATURE_ELS_SHA_512_224
+//#define    MCUXCL_FEATURE_ELS_SHA_512_256
+//#define    MCUXCL_FEATURE_ELS_SHA_DIRECT
+//#define    MCUXCL_FEATURE_ELS_SHA_DIRECT_MODE_FLAG
+//#define    MCUXCL_FEATURE_ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+//#define    MCUXCL_FEATURE_ELS_TLS
+//#define    MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+//#define    MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS_CMAC
+//#define    MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
+//#define    MCUXCL_FEATURE_ELS_PUK_INTERNAL
+//#define    MCUXCL_FEATURE_ELS_RND_RAW
+//#define    MCUXCL_FEATURE_ELS_PRND_INIT
+//#define    MCUXCL_FEATURE_ELS_DTRNG_PRV_CONFIG_LOAD
+//#define    MCUXCL_FEATURE_ELS_LOCKING
+//#define    MCUXCL_FEATURE_ELS_CMD_CRC
+//#define    MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK
+//#define    MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
+//#define    MCUXCL_FEATURE_ELS_RANDOMIZE_RFC3394_OUT
+//#define    MCUXCL_FEATURE_ELS_RESP_GEN
+//#define    MCUXCL_FEATURE_ELS_GET_FW_VERSION
+//#define    MCUXCL_FEATURE_ELS_CACHE_MAINTENANCE
+//#define    MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND
+//#define    MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND_M2
+//#define    MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING
+//#define    MCUXCL_FEATURE_ELS_HW_OUT_SLOTS
+//#define    MCUXCL_FEATURE_ELS_LINK_BASE_ADDRESS
+//#define    MCUXCL_FEATURE_ELS_ENTROPY_TEST
+//#define    MCUXCL_FEATURE_GLIKEY
+//#define    MCUXCL_FEATURE_GLIKEY_STEPS_4
+//#define    MCUXCL_FEATURE_GLIKEY_STEPS_8
+//#define    MCUXCL_FEATURE_GLIKEY_GETVERSION
+//#define    MCUXCL_FEATURE_DMA
+//#define    MCUXCL_FEATURE_DMA_SGI_HANDSHAKE
+//#define    MCUXCL_FEATURE_SGI
+//#define    MCUXCL_FEATURE_SGI_AUTOMODE
+//#define    MCUXCL_FEATURE_SGI_AUTOMODE_WORKAROUND_READ_FULL_DATOUT
+//#define    MCUXCL_FEATURE_SGI_HAS_EXTERNAL_KEYBANKS
+//#define    MCUXCL_FEATURE_SAFO
+//#define    MCUXCL_FEATURE_AEAD_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_AEAD_CRYPT
+//#define    MCUXCL_FEATURE_AEAD_ENCRYPT_DECRYPT
+//#define    MCUXCL_FEATURE_AEAD_ONESHOT
+//#define    MCUXCL_FEATURE_AEAD_MULTIPART
+//#define    MCUXCL_FEATURE_AEAD_SELFTEST
+//#define    MCUXCL_FEATURE_AEADMODES_SW
+//#define    MCUXCL_FEATURE_AEADMODES_GCM
+//#define    MCUXCL_FEATURE_AEADMODES_CCM
+//#define    MCUXCL_FEATURE_AEADMODES_CCMSTAR
+//#define    MCUXCL_FEATURE_AEADMODES_EAX
+//#define    MCUXCL_FEATURE_AES128
+//#define    MCUXCL_FEATURE_AES192
+//#define    MCUXCL_FEATURE_AES256
+//#define    MCUXCL_FEATURE_AES_SW
+//#define    MCUXCL_FEATURE_1KDES
+//#define    MCUXCL_FEATURE_2K3DES
+//#define    MCUXCL_FEATURE_3K3DES
+//#define    MCUXCL_FEATURE_DES_SW
+//#define    MCUXCL_FEATURE_BUFFER_USE_OBJECT
+//#define    MCUXCL_FEATURE_BUFFER_USE_POINTER
+//#define    MCUXCL_FEATURE_BUFFER_SCATTER_GATHER
+//#define    MCUXCL_FEATURE_CIPHER_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_CIPHER_CRYPT
+//#define    MCUXCL_FEATURE_CIPHER_ENCRYPT_DECRYPT
+//#define    MCUXCL_FEATURE_CIPHER_ONESHOT
+//#define    MCUXCL_FEATURE_CIPHER_MULTIPART
+//#define    MCUXCL_FEATURE_CIPHER_RSA_ENCRYPT
+//#define    MCUXCL_FEATURE_CIPHER_RSA_DECRYPT
+//#define    MCUXCL_FEATURE_CIPHER_SELFTEST
+//#define    MCUXCL_FEATURE_CIPHERMODES_ECB
+//#define    MCUXCL_FEATURE_CIPHERMODES_CBC
+//#define    MCUXCL_FEATURE_CIPHERMODES_CTR
+//#define    MCUXCL_FEATURE_CIPHERMODES_CFB
+//#define    MCUXCL_FEATURE_CIPHERMODES_OFB
+//#define    MCUXCL_FEATURE_CIPHERMODES_XTS
+//#define    MCUXCL_FEATURE_CIPHERMODES_DMA_BLOCKING
+//#define    MCUXCL_FEATURE_CIPHERMODES_DMA_NONBLOCKING
+//#define    MCUXCL_FEATURE_CIPHERMODES_SW
+//#define    MCUXCL_FEATURE_CRC_HW
+//#define    MCUXCL_FEATURE_CRC_SW
+//#define    MCUXCL_FEATURE_CRC_CRC32
+//#define    MCUXCL_FEATURE_ECC
+//#define    MCUXCL_FEATURE_ECC_STRENGTH_CHECK
+//#define    MCUXCL_FEATURE_ECC_INTERNAL
+//#define    MCUXCL_FEATURE_ECC_EXTERNAL
+//#define    MCUXCL_FEATURE_ECC_WEIERSTRASS
+//#define    MCUXCL_FEATURE_ECC_TWISTEDEDWARDS
+//#define    MCUXCL_FEATURE_ECC_MONTGOMERY
+//#define    MCUXCL_FEATURE_ECC_VERIFY_P384
+//#define    MCUXCL_FEATURE_ECC_MONTDH
+//#define    MCUXCL_FEATURE_ECC_CURVE25519
+//#define    MCUXCL_FEATURE_ECC_CURVE448
+//#define    MCUXCL_FEATURE_ECC_EDDSA
+//#define    MCUXCL_FEATURE_ECC_ECDSA_DETERMINISTIC
+//#define    MCUXCL_FEATURE_ECC_ED25519
+//#define    MCUXCL_FEATURE_ECC_ED448
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_GENERATECUSTOMDOMAINPARAMS
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_DECODEPOINT
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_KEYGENERATION
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_KEYVALIDATION
+//#define    MCUXCL_FEATURE_ECC_ECDSA
+//#define    MCUXCL_FEATURE_ECC_ECDH
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTADD
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTSUB
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SCALARMULT
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SECURESCALARMULT
+//#define    MCUXCL_FEATURE_ECC_SECPK1_CURVES
+//#define    MCUXCL_FEATURE_ECC_SECPR1_CURVES
+//#define    MCUXCL_FEATURE_ECC_NISTPR1_CURVES
+//#define    MCUXCL_FEATURE_ECC_ANSIX9P_CURVES
+//#define    MCUXCL_FEATURE_ECC_BRAINPOOLR1_CURVES
+//#define    MCUXCL_FEATURE_ECC_BRAINPOOLT1_CURVES
+//#define    MCUXCL_FEATURE_EXAMPLE_PKC_ENABLED
+//#define    MCUXCL_FEATURE_HASH
+//#define    MCUXCL_FEATURE_HASH_MULTIPART
+//#define    MCUXCL_FEATURE_HASH_ONESHOT
+//#define    MCUXCL_FEATURE_HASH_COMPARE
+//#define    MCUXCL_FEATURE_HASH_COMPUTE
+//#define    MCUXCL_FEATURE_HASH_IMPORT_EXPORT_STATE
+//#define    MCUXCL_FEATURE_HASH_SELFTEST
+//#define    MCUXCL_FEATURE_HASHMODES
+//#define    MCUXCL_FEATURE_HASH_C_MD5
+//#define    MCUXCL_FEATURE_HASH_C_SHA_1
+//#define    MCUXCL_FEATURE_HASH_C_SHA_224
+//#define    MCUXCL_FEATURE_HASH_C_SHA_256
+//#define    MCUXCL_FEATURE_HASH_C_SHA_384
+//#define    MCUXCL_FEATURE_HASH_C_SHA_512
+//#define    MCUXCL_FEATURE_HASH_C_SHA_512_224
+//#define    MCUXCL_FEATURE_HASH_C_SHA_512_256
+//#define    MCUXCL_FEATURE_HASH_C_SHA3_SHAKE
+//#define    MCUXCL_FEATURE_HASH_C_SHA3
+//#define    MCUXCL_FEATURE_HASH_ELS
+//#define    MCUXCL_FEATURE_HASH_SGI
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_224
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_256
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_384
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_512
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_512_224
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_512_256
+//#define    MCUXCL_FEATURE_HASH_SGI_MIYAGUCHI_PRENEEL
+//#define    MCUXCL_FEATURE_HASH_LTC
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_224
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_256
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_384
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_512
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_128
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_256
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_128
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_256
+//#define    MCUXCL_FEATURE_HASH_RANGER5_LIB
+//#define    MCUXCL_FEATURE_HASH_DMA_BLOCKING
+//#define    MCUXCL_FEATURE_HASH_DMA_NONBLOCKING
+//#define    MCUXCL_FEATURE_HASH_SECSHA
+//#define    MCUXCL_FEATURE_HASH_SECSHA_1
+//#define    MCUXCL_FEATURE_HASH_SECSHA_224
+//#define    MCUXCL_FEATURE_HASH_SECSHA_256
+//#define    MCUXCL_FEATURE_HASH_SECSHA_384
+//#define    MCUXCL_FEATURE_HASH_SECSHA_512
+//#define    MCUXCL_FEATURE_HASH_SECSHA_512_224
+//#define    MCUXCL_FEATURE_HASH_SECSHA_512_256
+//#define    MCUXCL_FEATURE_HASH_SECSHA3
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_224
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_256
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_384
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_512
+//#define    MCUXCL_FEATURE_HASH_SGI_COUNT_WORKAROUND
+//#define    MCUXCL_FEATURE_KEY_DERIVATION
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_108
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_56C
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_ISOIEC_18033_2
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_ANSI_X9_63
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_RFC5246_PRF
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_HKDF
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_PBKDF2
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_IKEV2
+//#define    MCUXCL_FEATURE_KEY_GENERATION
+//#define    MCUXCL_FEATURE_KEY_GENERATION_RSA
+//#define    MCUXCL_FEATURE_KEY_AGREEMENT
+//#define    MCUXCL_FEATURE_KEY_PROTECT
+//#define    MCUXCL_FEATURE_KEY_SELFTEST
+//#define    MCUXCL_FEATURE_KEY_VALIDATION
+//#define    MCUXCL_FEATURE_KEM_KYBER_ENCAPS
+//#define    MCUXCL_FEATURE_KEM_KYBER_DECAPS
+//#define    MCUXCL_FEATURE_KYBER
+//#define    MCUXCL_FEATURE_LTC
+//#define    MCUXCL_FEATURE_MAC
+//#define    MCUXCL_FEATURE_MAC_COMPARE
+//#define    MCUXCL_FEATURE_MAC_COMPUTE
+//#define    MCUXCL_FEATURE_MAC_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_MAC_MULTIPART
+//#define    MCUXCL_FEATURE_MAC_ONESHOT
+//#define    MCUXCL_FEATURE_MAC_SELFTEST
+//#define    MCUXCL_FEATURE_MACMODES_CBCMAC
+//#define    MCUXCL_FEATURE_MACMODES_CMAC
+//#define    MCUXCL_FEATURE_MACMODES_SGI_CMAC_SUB_KEYS
+//#define    MCUXCL_FEATURE_MACMODES_GMAC
+//#define    MCUXCL_FEATURE_MACMODES_KMAC
+//#define    MCUXCL_FEATURE_MACMODES_XCBCMAC
+//#define    MCUXCL_FEATURE_MACMODES_DMA_BLOCKING
+//#define    MCUXCL_FEATURE_MACMODES_DMA_NONBLOCKING
+//#define    MCUXCL_FEATURE_MAC_SIPHASH
+//#define    MCUXCL_FEATURE_HMAC_ELS
+//#define    MCUXCL_FEATURE_HMAC_SW
+//#define    MCUXCL_FEATURE_MATH_SECMODEXP_RISCV_SFRMASKING
+//#define    MCUXCL_FEATURE_MATH_MOD_SQUAREROOT
+//#define    MCUXCL_FEATURE_PADDING_ISO9797_1_M1
+//#define    MCUXCL_FEATURE_PADDING_ISO9797_1_M2
+//#define    MCUXCL_FEATURE_PADDING_PKCS7
+//#define    MCUXCL_FEATURE_PADDING_REMOVAL
+//#define    MCUXCL_FEATURE_PKC_CRR_HEADER
+//#define    MCUXCL_FEATURE_PKC_RAM_4KB
+//#define    MCUXCL_FEATURE_PKC_RAM_8KB
+//#define    MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS
+//#define    MCUXCL_FEATURE_PKC_PKCRAM_EXPLICIT_INIT_WORKAROUND
+//#define    MCUXCL_FEATURE_PKC_BLOCK_CPU_WORKAROUND
+//#define    MCUXCL_FEATURE_PKC_CPUPKC_ARBITRATION_WORKAROUND
+//#define    MCUXCL_FEATURE_PKC_FLEX_MC
+//#define    MCUXCL_FEATURE_PKC_PW_READY
+//#define    MCUXCL_FEATURE_PKC_SFR_MASK
+//#define    MCUXCL_FEATURE_PRNG
+//#define    MCUXCL_FEATURE_PRNG_ELS
+//#define    MCUXCL_FEATURE_PRNG_SCM
+//#define    MCUXCL_FEATURE_PRNG_NONE
+//#define    MCUXCL_FEATURE_RANDOM
+//#define    MCUXCL_FEATURE_RANDOMMODES_ELSMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_NORMALMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_PATCHMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_TESTMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG
+//#define    MCUXCL_FEATURE_RANDOMMODES_HMACDRBG
+//#define    MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED
+//#define    MCUXCL_FEATURE_RANDOMMODES_PTG3
+//#define    MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_128
+//#define    MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_192
+//#define    MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256
+//#define    MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION
+//#define    MCUXCL_FEATURE_RANDOMMODES_NO_DERIVATION_FUNCTION
+//#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_ELS
+//#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_SGI
+//#define    MCUXCL_FEATURE_RSA_SIGN
+//#define    MCUXCL_FEATURE_RSA_VERIFY
+//#define    MCUXCL_FEATURE_RSA_KEYGENERATION
+//#define    MCUXCL_FEATURE_RSA_NOHWACC_2K
+//#define    MCUXCL_FEATURE_RSA_NOHWACC_3K
+//#define    MCUXCL_FEATURE_RSA_VERIFY_SWONLY
+//#define    MCUXCL_FEATURE_RSA_STRENGTH_CHECK
+//#define    MCUXCL_FEATURE_RSA_RSASSA_PSS
+//#define    MCUXCL_FEATURE_RSA_RSASSA_PKCS1v15
+//#define    MCUXCL_FEATURE_RSA_RSAES_OAEP
+//#define    MCUXCL_FEATURE_RSA_RSAES_PKCS1v15
+//#define    MCUXCL_FEATURE_RSA_NOEMSA
+//#define    MCUXCL_FEATURE_RSA_8K_KEYS
+//#define    MCUXCL_FEATURE_RSA_NOEME
+//#define    MCUXCL_FEATURE_RSA_COMPARE_NOEMSA
+//#define    MCUXCL_FEATURE_SESSION_HAS_RANDOM
+//#define    MCUXCL_FEATURE_SESSION_HAS_RTF
+//#define    MCUXCL_FEATURE_SESSION_PKCWA_CHECK
+//#define    MCUXCL_FEATURE_SESSION_JOBS
+//#define    MCUXCL_FEATURE_SESSION_ENTRYEXIT_REGULARRETURN
+//#define    MCUXCL_FEATURE_SESSION_ENTRYEXIT_EARLYEXIT
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_DUMMYCYCLES
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_ADDITIONAL_SWCOMP
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_DOUBLE_VERIFICATION_SIGNATURE
+//#define    MCUXCL_FEATURE_SIGNATURE_MULTIPART
+//#define    MCUXCL_FEATURE_SIGNATURE_ONESHOT
+//#define    MCUXCL_FEATURE_SIGNATURE_RSA_SIGN
+//#define    MCUXCL_FEATURE_SIGNATURE_RSA_VERIFY
+//#define    MCUXCL_FEATURE_SIGNATURE_SIGN
+//#define    MCUXCL_FEATURE_SIGNATURE_VERIFY
+//#define    MCUXCL_FEATURE_SIGNATURE_SELFTEST
+//#define    MCUXCL_FEATURE_SIGNATURE_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_SIGNATURE_FAST_VERIFICATION
+//#define    MCUXCL_FEATURE_SIGNATURE_DILITHIUM_SIGN
+//#define    MCUXCL_FEATURE_SIGNATURE_DILITHIUM_VERIFY
+//#define    MCUXCL_FEATURE_TRNG_CRR_HEADER
+//#define    MCUXCL_FEATURE_TRNG_ELS
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG_256
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG_512
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG_DUAL_OSCILLATOR_MODE
+//#define    MCUXCL_FEATURE_XOF_ONESHOT
+//#define    MCUXCL_FEATURE_XOF_MULTIPART
+//#define    MCUXCL_FEATURE_XOF_C_SHAKE_128
+//#define    MCUXCL_FEATURE_XOF_C_SHAKE_256
+//#define    MCUXCL_FEATURE_XOF_LTC_SHAKE_128
+//#define    MCUXCL_FEATURE_XOF_LTC_SHAKE_256
+//#define    MCUXCL_FEATURE_XOF_LTC_CSHAKE_128
+//#define    MCUXCL_FEATURE_XOF_LTC_CSHAKE_256
+//#define    MCUXCL_FEATURE_CSSL_FP_INCLUDE_SECURE_COUNTER
+//#define    MCUXCL_FEATURE_CSSL_FP_INCLUDE_CODE_SIGNATURE
+//#define    MCUXCL_FEATURE_CSSL_FP_INCLUDE_NONE
+//#define    MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER
+//#define    MCUXCL_FEATURE_CSSL_FP_USE_CODE_SIGNATURE
+//#define    MCUXCL_FEATURE_CSSL_FP_USE_NONE
+//#define    MCUXCL_FEATURE_CSSL_FP_EXCLUDE_COVERITY_PRAGMAS
+//#define    MCUXCL_FEATURE_CSSL_ARM_M0
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COPY
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_XOR
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SET
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COMPARE
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_CLEAR
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_C_FALLBACK
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_NORMAL_OPERATION_RISCV
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SECURE_OPERATION_RISCV
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HYBRID_LOCAL_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_S3SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_LOCAL
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CALLBACK
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CONTEXT
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_GLOBAL
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_NONE
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HYBRID_LOCAL_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HW_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HW_SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HW_S3SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_CALLBACK
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_CONTEXT
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_GLOBAL
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_NONE
+//#define    MCUXCL_FEATURE_CSSL_SC_RISCV_ASM
+//#define    MCUXCL_FEATURE_CSSL_DI_USE_SECURE_COUNTER
+//#define    MCUXCL_FEATURE_CSSL_DI_USE_NONE
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_PRNG_STUB
+//#define    MCUXCL_FEATURE_SM4_CCM
+//#define    MCUXCL_FEATURE_CIPHERMODES_SM4
+//#define    MCUXCL_FEATURE_HASH_HW_SM3
+//#define    MCUXCL_FEATURE_HASH_SW_SM3
+//#define    MCUXCL_FEATURE_HASH_SM3_RISCV
+//#define    MCUXCL_FEATURE_MACMODES_HMAC_SM3
+//#define    MCUXCL_FEATURE_MACMODES_CBCMAC_SM4
+//#define    MCUXCL_FEATURE_MACMODES_CMAC_SM4
+//#define    MCUXCL_FEATURE_RANDOMMODES_OSCCA_TRNG
+//#define    MCUXCL_FEATURE_OSCCA_RNG_256
+//#define    MCUXCL_FEATURE_OSCCA_RNG_512
+//#define    MCUXCL_FEATURE_OSCCA_RNG_2_SOURCES
+//#define    MCUXCL_FEATURE_SM2_INTERNAL
+//#define    MCUXCL_FEATURE_SM2_KEYGEN
+//#define    MCUXCL_FEATURE_SM2_CIPHER
+//#define    MCUXCL_FEATURE_SM2_SIGNATURE
+//#define    MCUXCL_FEATURE_SM2_KEYAGREEMENT
+//#define    MCUXCL_FEATURE_NO_LINKER_SCRIPT
+//#define    MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_32
+//#define    MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_64
+//#define    MCUXCL_FEATURE_PROJECT_CLNS
+//#define    MCUXCL_FEATURE_SB3
+//#define    MCUXCL_FEATURE_SB3_384
+//#define    MCUXCL_FEATURE_RSA_ADAPTERCHECKS
+//#define    MCUXCL_FEATURE_BINARY_DELIVERY
+//#define    MCUXCL_FEATURE_SOURCE_DELIVERY
+//#define    MCUXCL_FEATURE_KEEP_ECLIPSE_FORMATTER_CONTROL
+//#define    MCUXCL_FEATURE_KEEP_INTERNAL_COMMENTS
+//#define    MCUXCL_FEATURE_INTERNAL_INCLUDES_FLAG
+
+//commented defines for all enabled features 
+//#define    MCUXCL_FEATURE_EXPORTED_FEATURE_HEADER
+//#define    MCUXCL_FEATURE_EXPORTED_PLATFORM_HEADERS
+//#define    MCUXCL_FEATURE_PLATFORM_RW61X
+//#define    MCUXCL_FEATURE_PLATFORM_MCXN
+//#define    MCUXCL_FEATURE_PLATFORM_LPC
+//#define    MCUXCL_FEATURE_PROJECT_VOLTA_ON_NIRVANA
+//#define    MCUXCL_FEATURE_PLATFORM_MIMXRT
+//#define    MCUXCL_FEATURE_PROJECT_BLACKBIRD
+//#define    MCUXCL_FEATURE_PROJECT_CSSL
+//#define    MCUXCL_FEATURE_PROJECT_NCCL
+//#define    MCUXCL_FEATURE_PROJECT_QUANTUM
+//#define    MCUXCL_FEATURE_PROJECT_SHARK
+//#define    MCUXCL_FEATURE_HW_ELS
+//#define    MCUXCL_FEATURE_HW_GDET
+//#define    MCUXCL_FEATURE_HW_GLIKEY
+//#define    MCUXCL_FEATURE_HW_PKC
+//#define    MCUXCL_FEATURE_HW_ROPUF
+//#define    MCUXCL_FEATURE_HW_SAFO_SM3
+//#define    MCUXCL_FEATURE_HW_SAFO_SM4
+//#define    MCUXCL_FEATURE_HW_SGI
+//#define    MCUXCL_FEATURE_HW_TRNG
+//#define    MCUXCL_FEATURE_HW_RISCV_ZBB
+//#define    MCUXCL_FEATURE_HW_RISCV_CSW
+//#define    MCUXCL_FEATURE_HW_CACHE_ENABLED
+//#define    MCUXCL_FEATURE_ELS
+//#define    MCUXCL_FEATURE_ELS_AEAD
+//#define    MCUXCL_FEATURE_ELS_API_INPUT_PARAM_CHECKS
+//#define    MCUXCL_FEATURE_ELS_CKDF
+//#define    MCUXCL_FEATURE_ELS_CKDF_SP80056C
+//#define    MCUXCL_FEATURE_ELS_CMAC
+//#define    MCUXCL_FEATURE_ELS_ECC_KEY_EXCHANGE
+//#define    MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD_EVEN
+//#define    MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD
+//#define    MCUXCL_FEATURE_ELS_GLITCHDETECTOR
+//#define    MCUXCL_FEATURE_ELS_HKDF
+//#define    MCUXCL_FEATURE_ELS_HMAC
+//#define    MCUXCL_FEATURE_ELS_HWCONFIG
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT
+//#define    MCUXCL_FEATURE_ELS_KEY_EXPORT_SW_DFA_PROTECTION
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_TEST
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM_TEST
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE
+//#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE_TEST
+//#define    MCUXCL_FEATURE_ELS_RNG
+//#define    MCUXCL_FEATURE_ELS_SHA_224
+//#define    MCUXCL_FEATURE_ELS_SHA_256
+//#define    MCUXCL_FEATURE_ELS_SHA_384
+//#define    MCUXCL_FEATURE_ELS_SHA_512
+//#define    MCUXCL_FEATURE_ELS_SHA_512_224
+//#define    MCUXCL_FEATURE_ELS_SHA_512_256
+//#define    MCUXCL_FEATURE_ELS_SHA_DIRECT
+//#define    MCUXCL_FEATURE_ELS_SHA_DIRECT_MODE_FLAG
+//#define    MCUXCL_FEATURE_ELS_AES_WITH_SIDE_CHANNEL_PROTECTION
+//#define    MCUXCL_FEATURE_ELS_TLS
+//#define    MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
+//#define    MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS_CMAC
+//#define    MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
+//#define    MCUXCL_FEATURE_ELS_PUK_INTERNAL
+//#define    MCUXCL_FEATURE_ELS_RND_RAW
+//#define    MCUXCL_FEATURE_ELS_PRND_INIT
+//#define    MCUXCL_FEATURE_ELS_DTRNG_PRV_CONFIG_LOAD
+//#define    MCUXCL_FEATURE_ELS_LOCKING
+//#define    MCUXCL_FEATURE_ELS_CMD_CRC
+//#define    MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK
+//#define    MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
+//#define    MCUXCL_FEATURE_ELS_RANDOMIZE_RFC3394_OUT
+//#define    MCUXCL_FEATURE_ELS_RESP_GEN
+//#define    MCUXCL_FEATURE_ELS_GET_FW_VERSION
+//#define    MCUXCL_FEATURE_ELS_CACHE_MAINTENANCE
+//#define    MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND
+//#define    MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND_M2
+//#define    MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING
+//#define    MCUXCL_FEATURE_ELS_HW_OUT_SLOTS
+//#define    MCUXCL_FEATURE_ELS_LINK_BASE_ADDRESS
+//#define    MCUXCL_FEATURE_ELS_ENTROPY_TEST
+//#define    MCUXCL_FEATURE_GLIKEY
+//#define    MCUXCL_FEATURE_GLIKEY_STEPS_4
+//#define    MCUXCL_FEATURE_GLIKEY_STEPS_8
+//#define    MCUXCL_FEATURE_GLIKEY_GETVERSION
+//#define    MCUXCL_FEATURE_DMA
+//#define    MCUXCL_FEATURE_DMA_SGI_HANDSHAKE
+//#define    MCUXCL_FEATURE_SGI
+//#define    MCUXCL_FEATURE_SGI_AUTOMODE
+//#define    MCUXCL_FEATURE_SGI_AUTOMODE_WORKAROUND_READ_FULL_DATOUT
+//#define    MCUXCL_FEATURE_SGI_HAS_EXTERNAL_KEYBANKS
+//#define    MCUXCL_FEATURE_SAFO
+//#define    MCUXCL_FEATURE_AEAD_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_AEAD_CRYPT
+//#define    MCUXCL_FEATURE_AEAD_ENCRYPT_DECRYPT
+//#define    MCUXCL_FEATURE_AEAD_ONESHOT
+//#define    MCUXCL_FEATURE_AEAD_MULTIPART
+//#define    MCUXCL_FEATURE_AEAD_SELFTEST
+//#define    MCUXCL_FEATURE_AEADMODES_SW
+//#define    MCUXCL_FEATURE_AEADMODES_GCM
+//#define    MCUXCL_FEATURE_AEADMODES_CCM
+//#define    MCUXCL_FEATURE_AEADMODES_CCMSTAR
+//#define    MCUXCL_FEATURE_AEADMODES_EAX
+//#define    MCUXCL_FEATURE_AES128
+//#define    MCUXCL_FEATURE_AES192
+//#define    MCUXCL_FEATURE_AES256
+//#define    MCUXCL_FEATURE_AES_SW
+//#define    MCUXCL_FEATURE_1KDES
+//#define    MCUXCL_FEATURE_2K3DES
+//#define    MCUXCL_FEATURE_3K3DES
+//#define    MCUXCL_FEATURE_DES_SW
+//#define    MCUXCL_FEATURE_BUFFER_USE_OBJECT
+//#define    MCUXCL_FEATURE_BUFFER_USE_POINTER
+//#define    MCUXCL_FEATURE_BUFFER_SCATTER_GATHER
+//#define    MCUXCL_FEATURE_CIPHER_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_CIPHER_CRYPT
+//#define    MCUXCL_FEATURE_CIPHER_ENCRYPT_DECRYPT
+//#define    MCUXCL_FEATURE_CIPHER_ONESHOT
+//#define    MCUXCL_FEATURE_CIPHER_MULTIPART
+//#define    MCUXCL_FEATURE_CIPHER_RSA_ENCRYPT
+//#define    MCUXCL_FEATURE_CIPHER_RSA_DECRYPT
+//#define    MCUXCL_FEATURE_CIPHER_SELFTEST
+//#define    MCUXCL_FEATURE_CIPHERMODES_ECB
+//#define    MCUXCL_FEATURE_CIPHERMODES_CBC
+//#define    MCUXCL_FEATURE_CIPHERMODES_CTR
+//#define    MCUXCL_FEATURE_CIPHERMODES_CFB
+//#define    MCUXCL_FEATURE_CIPHERMODES_OFB
+//#define    MCUXCL_FEATURE_CIPHERMODES_XTS
+//#define    MCUXCL_FEATURE_CIPHERMODES_DMA_BLOCKING
+//#define    MCUXCL_FEATURE_CIPHERMODES_DMA_NONBLOCKING
+//#define    MCUXCL_FEATURE_CIPHERMODES_SW
+//#define    MCUXCL_FEATURE_CRC_HW
+//#define    MCUXCL_FEATURE_CRC_SW
+//#define    MCUXCL_FEATURE_CRC_CRC32
+//#define    MCUXCL_FEATURE_ECC
+//#define    MCUXCL_FEATURE_ECC_STRENGTH_CHECK
+//#define    MCUXCL_FEATURE_ECC_INTERNAL
+//#define    MCUXCL_FEATURE_ECC_EXTERNAL
+//#define    MCUXCL_FEATURE_ECC_WEIERSTRASS
+//#define    MCUXCL_FEATURE_ECC_TWISTEDEDWARDS
+//#define    MCUXCL_FEATURE_ECC_MONTGOMERY
+//#define    MCUXCL_FEATURE_ECC_VERIFY_P384
+//#define    MCUXCL_FEATURE_ECC_MONTDH
+//#define    MCUXCL_FEATURE_ECC_CURVE25519
+//#define    MCUXCL_FEATURE_ECC_CURVE448
+//#define    MCUXCL_FEATURE_ECC_EDDSA
+//#define    MCUXCL_FEATURE_ECC_ECDSA_DETERMINISTIC
+//#define    MCUXCL_FEATURE_ECC_ED25519
+//#define    MCUXCL_FEATURE_ECC_ED448
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_GENERATECUSTOMDOMAINPARAMS
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_DECODEPOINT
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_KEYGENERATION
+//#define    MCUXCL_FEATURE_ECC_WEIERECC_KEYVALIDATION
+//#define    MCUXCL_FEATURE_ECC_ECDSA
+//#define    MCUXCL_FEATURE_ECC_ECDH
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTADD
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTSUB
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SCALARMULT
+//#define    MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SECURESCALARMULT
+//#define    MCUXCL_FEATURE_ECC_SECPK1_CURVES
+//#define    MCUXCL_FEATURE_ECC_SECPR1_CURVES
+//#define    MCUXCL_FEATURE_ECC_NISTPR1_CURVES
+//#define    MCUXCL_FEATURE_ECC_ANSIX9P_CURVES
+//#define    MCUXCL_FEATURE_ECC_BRAINPOOLR1_CURVES
+//#define    MCUXCL_FEATURE_ECC_BRAINPOOLT1_CURVES
+//#define    MCUXCL_FEATURE_EXAMPLE_PKC_ENABLED
+//#define    MCUXCL_FEATURE_HASH
+//#define    MCUXCL_FEATURE_HASH_MULTIPART
+//#define    MCUXCL_FEATURE_HASH_ONESHOT
+//#define    MCUXCL_FEATURE_HASH_COMPARE
+//#define    MCUXCL_FEATURE_HASH_COMPUTE
+//#define    MCUXCL_FEATURE_HASH_IMPORT_EXPORT_STATE
+//#define    MCUXCL_FEATURE_HASH_SELFTEST
+//#define    MCUXCL_FEATURE_HASHMODES
+//#define    MCUXCL_FEATURE_HASH_C_MD5
+//#define    MCUXCL_FEATURE_HASH_C_SHA_1
+//#define    MCUXCL_FEATURE_HASH_C_SHA_224
+//#define    MCUXCL_FEATURE_HASH_C_SHA_256
+//#define    MCUXCL_FEATURE_HASH_C_SHA_384
+//#define    MCUXCL_FEATURE_HASH_C_SHA_512
+//#define    MCUXCL_FEATURE_HASH_C_SHA_512_224
+//#define    MCUXCL_FEATURE_HASH_C_SHA_512_256
+//#define    MCUXCL_FEATURE_HASH_C_SHA3_SHAKE
+//#define    MCUXCL_FEATURE_HASH_C_SHA3
+//#define    MCUXCL_FEATURE_HASH_ELS
+//#define    MCUXCL_FEATURE_HASH_SGI
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_224
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_256
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_384
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_512
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_512_224
+//#define    MCUXCL_FEATURE_HASH_SGI_SHA_512_256
+//#define    MCUXCL_FEATURE_HASH_SGI_MIYAGUCHI_PRENEEL
+//#define    MCUXCL_FEATURE_HASH_LTC
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_224
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_256
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_384
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_512
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_128
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_256
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_128
+//#define    MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_256
+//#define    MCUXCL_FEATURE_HASH_RANGER5_LIB
+//#define    MCUXCL_FEATURE_HASH_DMA_BLOCKING
+//#define    MCUXCL_FEATURE_HASH_DMA_NONBLOCKING
+//#define    MCUXCL_FEATURE_HASH_SECSHA
+//#define    MCUXCL_FEATURE_HASH_SECSHA_1
+//#define    MCUXCL_FEATURE_HASH_SECSHA_224
+//#define    MCUXCL_FEATURE_HASH_SECSHA_256
+//#define    MCUXCL_FEATURE_HASH_SECSHA_384
+//#define    MCUXCL_FEATURE_HASH_SECSHA_512
+//#define    MCUXCL_FEATURE_HASH_SECSHA_512_224
+//#define    MCUXCL_FEATURE_HASH_SECSHA_512_256
+//#define    MCUXCL_FEATURE_HASH_SECSHA3
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_224
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_256
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_384
+//#define    MCUXCL_FEATURE_HASH_SECSHA3_512
+//#define    MCUXCL_FEATURE_HASH_SGI_COUNT_WORKAROUND
+//#define    MCUXCL_FEATURE_KEY_DERIVATION
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_108
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_56C
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_ISOIEC_18033_2
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_ANSI_X9_63
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_RFC5246_PRF
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_HKDF
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_PBKDF2
+//#define    MCUXCL_FEATURE_KEY_DERIVATION_IKEV2
+//#define    MCUXCL_FEATURE_KEY_GENERATION
+//#define    MCUXCL_FEATURE_KEY_GENERATION_RSA
+//#define    MCUXCL_FEATURE_KEY_AGREEMENT
+//#define    MCUXCL_FEATURE_KEY_PROTECT
+//#define    MCUXCL_FEATURE_KEY_SELFTEST
+//#define    MCUXCL_FEATURE_KEY_VALIDATION
+//#define    MCUXCL_FEATURE_KEM_KYBER_ENCAPS
+//#define    MCUXCL_FEATURE_KEM_KYBER_DECAPS
+//#define    MCUXCL_FEATURE_KYBER
+//#define    MCUXCL_FEATURE_LTC
+//#define    MCUXCL_FEATURE_MAC
+//#define    MCUXCL_FEATURE_MAC_COMPARE
+//#define    MCUXCL_FEATURE_MAC_COMPUTE
+//#define    MCUXCL_FEATURE_MAC_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_MAC_MULTIPART
+//#define    MCUXCL_FEATURE_MAC_ONESHOT
+//#define    MCUXCL_FEATURE_MAC_SELFTEST
+//#define    MCUXCL_FEATURE_MACMODES_CBCMAC
+//#define    MCUXCL_FEATURE_MACMODES_CMAC
+//#define    MCUXCL_FEATURE_MACMODES_SGI_CMAC_SUB_KEYS
+//#define    MCUXCL_FEATURE_MACMODES_GMAC
+//#define    MCUXCL_FEATURE_MACMODES_KMAC
+//#define    MCUXCL_FEATURE_MACMODES_XCBCMAC
+//#define    MCUXCL_FEATURE_MACMODES_DMA_BLOCKING
+//#define    MCUXCL_FEATURE_MACMODES_DMA_NONBLOCKING
+//#define    MCUXCL_FEATURE_MAC_SIPHASH
+//#define    MCUXCL_FEATURE_HMAC_ELS
+//#define    MCUXCL_FEATURE_HMAC_SW
+//#define    MCUXCL_FEATURE_MATH_SECMODEXP_RISCV_SFRMASKING
+//#define    MCUXCL_FEATURE_MATH_MOD_SQUAREROOT
+//#define    MCUXCL_FEATURE_PADDING_ISO9797_1_M1
+//#define    MCUXCL_FEATURE_PADDING_ISO9797_1_M2
+//#define    MCUXCL_FEATURE_PADDING_PKCS7
+//#define    MCUXCL_FEATURE_PADDING_REMOVAL
+//#define    MCUXCL_FEATURE_PKC_CRR_HEADER
+//#define    MCUXCL_FEATURE_PKC_RAM_4KB
+//#define    MCUXCL_FEATURE_PKC_RAM_8KB
+//#define    MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS
+//#define    MCUXCL_FEATURE_PKC_PKCRAM_EXPLICIT_INIT_WORKAROUND
+//#define    MCUXCL_FEATURE_PKC_BLOCK_CPU_WORKAROUND
+//#define    MCUXCL_FEATURE_PKC_CPUPKC_ARBITRATION_WORKAROUND
+//#define    MCUXCL_FEATURE_PKC_FLEX_MC
+//#define    MCUXCL_FEATURE_PKC_PW_READY
+//#define    MCUXCL_FEATURE_PKC_SFR_MASK
+//#define    MCUXCL_FEATURE_PRNG
+//#define    MCUXCL_FEATURE_PRNG_ELS
+//#define    MCUXCL_FEATURE_PRNG_SCM
+//#define    MCUXCL_FEATURE_PRNG_NONE
+//#define    MCUXCL_FEATURE_RANDOM
+//#define    MCUXCL_FEATURE_RANDOMMODES_ELSMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_NORMALMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_PATCHMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_TESTMODE
+//#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG
+//#define    MCUXCL_FEATURE_RANDOMMODES_HMACDRBG
+//#define    MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED
+//#define    MCUXCL_FEATURE_RANDOMMODES_PTG3
+//#define    MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_128
+//#define    MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_192
+//#define    MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256
+//#define    MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION
+//#define    MCUXCL_FEATURE_RANDOMMODES_NO_DERIVATION_FUNCTION
+//#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_ELS
+//#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_SGI
+//#define    MCUXCL_FEATURE_RSA_SIGN
+//#define    MCUXCL_FEATURE_RSA_VERIFY
+//#define    MCUXCL_FEATURE_RSA_KEYGENERATION
+//#define    MCUXCL_FEATURE_RSA_NOHWACC_2K
+//#define    MCUXCL_FEATURE_RSA_NOHWACC_3K
+//#define    MCUXCL_FEATURE_RSA_VERIFY_SWONLY
+//#define    MCUXCL_FEATURE_RSA_STRENGTH_CHECK
+//#define    MCUXCL_FEATURE_RSA_RSASSA_PSS
+//#define    MCUXCL_FEATURE_RSA_RSASSA_PKCS1v15
+//#define    MCUXCL_FEATURE_RSA_RSAES_OAEP
+//#define    MCUXCL_FEATURE_RSA_RSAES_PKCS1v15
+//#define    MCUXCL_FEATURE_RSA_NOEMSA
+//#define    MCUXCL_FEATURE_RSA_8K_KEYS
+//#define    MCUXCL_FEATURE_RSA_NOEME
+//#define    MCUXCL_FEATURE_RSA_COMPARE_NOEMSA
+//#define    MCUXCL_FEATURE_SESSION_HAS_RANDOM
+//#define    MCUXCL_FEATURE_SESSION_HAS_RTF
+//#define    MCUXCL_FEATURE_SESSION_PKCWA_CHECK
+//#define    MCUXCL_FEATURE_SESSION_JOBS
+//#define    MCUXCL_FEATURE_SESSION_ENTRYEXIT_REGULARRETURN
+//#define    MCUXCL_FEATURE_SESSION_ENTRYEXIT_EARLYEXIT
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_DUMMYCYCLES
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_ADDITIONAL_SWCOMP
+//#define    MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_DOUBLE_VERIFICATION_SIGNATURE
+//#define    MCUXCL_FEATURE_SIGNATURE_MULTIPART
+//#define    MCUXCL_FEATURE_SIGNATURE_ONESHOT
+//#define    MCUXCL_FEATURE_SIGNATURE_RSA_SIGN
+//#define    MCUXCL_FEATURE_SIGNATURE_RSA_VERIFY
+//#define    MCUXCL_FEATURE_SIGNATURE_SIGN
+//#define    MCUXCL_FEATURE_SIGNATURE_VERIFY
+//#define    MCUXCL_FEATURE_SIGNATURE_SELFTEST
+//#define    MCUXCL_FEATURE_SIGNATURE_CONTEXT_INTEGRITY_PROTECTION
+//#define    MCUXCL_FEATURE_SIGNATURE_FAST_VERIFICATION
+//#define    MCUXCL_FEATURE_SIGNATURE_DILITHIUM_SIGN
+//#define    MCUXCL_FEATURE_SIGNATURE_DILITHIUM_VERIFY
+//#define    MCUXCL_FEATURE_TRNG_CRR_HEADER
+//#define    MCUXCL_FEATURE_TRNG_ELS
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG_256
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG_512
+//#define    MCUXCL_FEATURE_TRNG_SA_TRNG_DUAL_OSCILLATOR_MODE
+//#define    MCUXCL_FEATURE_XOF_ONESHOT
+//#define    MCUXCL_FEATURE_XOF_MULTIPART
+//#define    MCUXCL_FEATURE_XOF_C_SHAKE_128
+//#define    MCUXCL_FEATURE_XOF_C_SHAKE_256
+//#define    MCUXCL_FEATURE_XOF_LTC_SHAKE_128
+//#define    MCUXCL_FEATURE_XOF_LTC_SHAKE_256
+//#define    MCUXCL_FEATURE_XOF_LTC_CSHAKE_128
+//#define    MCUXCL_FEATURE_XOF_LTC_CSHAKE_256
+//#define    MCUXCL_FEATURE_CSSL_FP_INCLUDE_SECURE_COUNTER
+//#define    MCUXCL_FEATURE_CSSL_FP_INCLUDE_CODE_SIGNATURE
+//#define    MCUXCL_FEATURE_CSSL_FP_INCLUDE_NONE
+//#define    MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER
+//#define    MCUXCL_FEATURE_CSSL_FP_USE_CODE_SIGNATURE
+//#define    MCUXCL_FEATURE_CSSL_FP_USE_NONE
+//#define    MCUXCL_FEATURE_CSSL_FP_EXCLUDE_COVERITY_PRAGMAS
+//#define    MCUXCL_FEATURE_CSSL_ARM_M0
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COPY
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_XOR
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SET
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COMPARE
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_CLEAR
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_C_FALLBACK
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_NORMAL_OPERATION_RISCV
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SECURE_OPERATION_RISCV
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HYBRID_LOCAL_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_S3SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_LOCAL
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CALLBACK
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CONTEXT
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_GLOBAL
+//#define    MCUXCL_FEATURE_CSSL_SC_INCLUDE_NONE
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HYBRID_LOCAL_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HW_CDOG
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HW_SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_HW_S3SCM
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_CALLBACK
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_CONTEXT
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_SW_GLOBAL
+//#define    MCUXCL_FEATURE_CSSL_SC_USE_NONE
+//#define    MCUXCL_FEATURE_CSSL_SC_RISCV_ASM
+//#define    MCUXCL_FEATURE_CSSL_DI_USE_SECURE_COUNTER
+//#define    MCUXCL_FEATURE_CSSL_DI_USE_NONE
+//#define    MCUXCL_FEATURE_CSSL_MEMORY_PRNG_STUB
+//#define    MCUXCL_FEATURE_SM4_CCM
+//#define    MCUXCL_FEATURE_CIPHERMODES_SM4
+//#define    MCUXCL_FEATURE_HASH_HW_SM3
+//#define    MCUXCL_FEATURE_HASH_SW_SM3
+//#define    MCUXCL_FEATURE_HASH_SM3_RISCV
+//#define    MCUXCL_FEATURE_MACMODES_HMAC_SM3
+//#define    MCUXCL_FEATURE_MACMODES_CBCMAC_SM4
+//#define    MCUXCL_FEATURE_MACMODES_CMAC_SM4
+//#define    MCUXCL_FEATURE_RANDOMMODES_OSCCA_TRNG
+//#define    MCUXCL_FEATURE_OSCCA_RNG_256
+//#define    MCUXCL_FEATURE_OSCCA_RNG_512
+//#define    MCUXCL_FEATURE_OSCCA_RNG_2_SOURCES
+//#define    MCUXCL_FEATURE_SM2_INTERNAL
+//#define    MCUXCL_FEATURE_SM2_KEYGEN
+//#define    MCUXCL_FEATURE_SM2_CIPHER
+//#define    MCUXCL_FEATURE_SM2_SIGNATURE
+//#define    MCUXCL_FEATURE_SM2_KEYAGREEMENT
+//#define    MCUXCL_FEATURE_NO_LINKER_SCRIPT
+//#define    MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_32
+//#define    MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_64
+//#define    MCUXCL_FEATURE_PROJECT_CLNS
+//#define    MCUXCL_FEATURE_SB3
+//#define    MCUXCL_FEATURE_SB3_384
+//#define    MCUXCL_FEATURE_RSA_ADAPTERCHECKS
+//#define    MCUXCL_FEATURE_BINARY_DELIVERY
+//#define    MCUXCL_FEATURE_SOURCE_DELIVERY
+//#define    MCUXCL_FEATURE_KEEP_ECLIPSE_FORMATTER_CONTROL
+//#define    MCUXCL_FEATURE_KEEP_INTERNAL_COMMENTS
+//#define    MCUXCL_FEATURE_INTERNAL_INCLUDES_FLAG
+
+//defines for exported features 
+#define    MCUXCL_FEATURE_PLATFORM_RW61X          1
+#define    MCUXCL_FEATURE_HW_ROPUF          1
+#define    MCUXCL_FEATURE_HW_TRNG          1
+#define    MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD          1
+#define    MCUXCL_FEATURE_ELS_GLITCHDETECTOR          1
+#define    MCUXCL_FEATURE_ELS_HWCONFIG          1
+#define    MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_TEST          1
+#define    MCUXCL_FEATURE_ELS_GET_FW_VERSION          1
+#define    MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND          1
+#define    MCUXCL_FEATURE_ECC_STRENGTH_CHECK          1
+#define    MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS          1
+#define    MCUXCL_FEATURE_RANDOMMODES_NORMALMODE          1
+#define    MCUXCL_FEATURE_RANDOMMODES_TESTMODE          1
+#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG          1
+#define    MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED          1
+#define    MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256          1
+#define    MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION          1
+#define    MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_ELS          1
+#define    MCUXCL_FEATURE_RSA_STRENGTH_CHECK          1
+#define    MCUXCL_FEATURE_TRNG_SA_TRNG          1
+#define    MCUXCL_FEATURE_TRNG_SA_TRNG_256          1
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/platform_specific_headers.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/platform_specific_headers.h
new file mode 100644
index 0000000000..e9cc328f04
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/platform_specific_headers.h
@@ -0,0 +1,28 @@
+ /*--------------------------------------------------------------------------*/
+ /* Copyright 2021 NXP                                                       */
+ /*                                                                          */
+ /* NXP Confidential. This software is owned or controlled by NXP and may    */
+ /* only be used strictly in accordance with the applicable license terms.   */
+ /* By expressly accepting such terms or by downloading, installing,         */
+ /* activating and/or otherwise using the software, you are agreeing that    */
+ /* you have read, and that you agree to comply with and are bound by, such  */
+ /* license terms. If you do not agree to be bound by the applicable license */
+ /* terms, then you may not retain, install, activate or otherwise use the   */
+ /* software.                                                                */
+ /*--------------------------------------------------------------------------*/
+ 
+ #ifndef PLATFORM_SPECIFIC_HEADERS_H_ 
+ #define PLATFORM_SPECIFIC_HEADERS_H_ 
+ #pragma once
+ 
+ #include "mcuxClConfig.h"
+ #include "mcuxCsslAnalysis.h"
+ 
+ MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_HEADER()
+ #include "fsl_device_registers.h" 
+ #include "ip_platform.h" 
+ #include "ip_css_constants.h" 
+ #include "ip_css_design_configuration.h" 
+ MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_HEADER()
+ 
+ #endif /*PLATFORM_SPECIFIC_HEADERS_H_*/ 
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/readme.txt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/readme.txt
new file mode 100644
index 0000000000..4d48907206
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/els_pkc/src/platforms/rw61x/readme.txt
@@ -0,0 +1,6 @@
+Purpose of this file is to explain two different components for RW61x platform:
+	- component.els_pkc.platform.rw61x_standalone_clib_gdet_sensor:
+		- This component only provides gdet sensor related interface of clib. 
+		  It shall only be used within default examples of RW61x where entire clib-interface is not required.
+	- component.els_pkc.platform.rw61x:
+		- This component includes all features supported by Clib for RW61x platform.
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu.c
new file mode 100644
index 0000000000..cbf1f0f2ef
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu.c
@@ -0,0 +1,2101 @@
+/*
+ * Copyright 2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_adapter_imu_common.h"
+#include "fsl_adapter_imu.h"
+#if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
+#include "fsl_gdma.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#ifndef IMU_ISR_PRIORITY
+#define IMU_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#endif
+#else
+#ifndef IMU_ISR_PRIORITY
+#define IMU_ISR_PRIORITY (2U)
+#endif
+#endif
+
+#ifndef IMU_LINK_WAIT_DELAY_MS
+#define IMU_LINK_WAIT_DELAY_MS 1U
+#endif
+
+#ifndef IMUMC_ALLOC_FAILED_DELAY_MS
+#define IMUMC_ALLOC_FAILED_DELAY_MS 1U
+#endif
+
+#ifndef IMUMC_ALLOC_RETRY_COUNT
+#define IMUMC_ALLOC_RETRY_COUNT 10U
+#endif
+
+#if defined(CPU2)
+#define os_InterruptMaskClear(irq_num) DisableIRQ((IRQn_Type)irq_num)
+#define os_InterruptMaskSet(irq_num)   EnableIRQ((IRQn_Type)irq_num)
+#define os_ClearPendingISR(irq_num)    NVIC_ClearPendingIRQ((IRQn_Type)irq_num)
+#else
+#define os_InterruptMaskClear(irq_num) DisableIRQ(irq_num)
+#define os_InterruptMaskSet(irq_num)   EnableIRQ(irq_num)
+#define os_ClearPendingISR(irq_num)    NVIC_ClearPendingIRQ(irq_num)
+#endif
+
+#if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
+#define HAL_GDMA            GDMA
+#define HAL_GDMA_CH         0
+#define HAL_GDMA_IRQn       GDMA_IRQn
+#define HAL_GDMA_DONE_EVENT (1U << 0U)
+#define GDMA_ISR_PRIORITY   IMU_ISR_PRIORITY
+#define HAL_IMU_MEMCPY      HAL_ImuGdmaCopyData
+#else
+#define HAL_IMU_MEMCPY memcpy
+#endif
+
+/*******************************************************************************
+ * Declaration
+ ******************************************************************************/
+
+/*! IMU handle instance for each IMU link */
+static hal_imu_handle_t imuHandleCh[kIMU_LinkMax];
+
+/*! IMU interrput callback for each IMU link */
+static imu_irq_callback_t imuIrqCallback[kIMU_LinkMax];
+
+/*! IMU message sequence number */
+static uint8_t seq_num = 0;
+
+/*! IMU initializtion flag
+    bit 0: flag for IMU link #0
+    bit 1: flag for IMU link #1
+*/
+static uint8_t imu_init_flag = 0;
+
+/*! IMUMC initializtion flag
+ */
+static uint8_t imumc_init_flag = 0;
+
+/*! imu task created flag
+ */
+static uint8_t imu_task_flag = 0;
+
+#ifndef CPU2
+/*! Sleep flag address between CPU1 and CPU3 or CPU2 and CPU3 */
+#define IMU_SLEEP_FLAG13 0x4138248C
+#define IMU_SLEEP_FLAG23 0x443CFE88
+#define IMU_SLEEP_FLAG_ADDR(imuLinkId) \
+    (((imuLinkId) == kIMU_LinkCpu1Cpu3) ? ((uint32_t *)IMU_SLEEP_FLAG13) : ((uint32_t *)IMU_SLEEP_FLAG23))
+#endif
+
+/*! wait imu task lock
+ */
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+static OSA_MUTEX_HANDLE_DEFINE(imu_task_lock);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(CPU2)
+extern IMU_Msg_Wrapper_short_t __attribute__((aligned(4))) SQRAM_CPU12_MBOX;
+extern IMU_Msg_Wrapper_long_t __attribute__((aligned(4))) SQRAM_CPU23_MBOX;
+volatile static IMU_Msg_Wrapper_short_t *imuMsgQ12 = &SQRAM_CPU12_MBOX;
+volatile static IMU_Msg_Wrapper_long_t *imuMsgQ23  = &SQRAM_CPU23_MBOX;
+__attribute__((section(".smu_cpu23_txq"))) volatile static uint8_t __attribute__((aligned(4)))
+imumcTxBuf23[IMUMC_TXQ23_BUFSIZE][IMUMC_TXQ23_BUFLENGTH];
+
+static void HAL_ImuMain(void *argv);
+static OSA_TASK_HANDLE_DEFINE(ImuTaskHandle);
+static OSA_TASK_DEFINE(HAL_ImuMain, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
+OSA_EVENT_HANDLE_DEFINE(ImuQFlagsRef);
+#else
+__attribute__((section(".smu_cpu13_mbox"))) static volatile IMU_Msg_Wrapper_long_t __attribute__((aligned(4)))
+SQRAM_CPU13_MBOX;
+__attribute__((section(".smu_cpu23_mbox"))) static volatile IMU_Msg_Wrapper_long_t __attribute__((aligned(4)))
+SQRAM_CPU23_MBOX;
+static volatile IMU_Msg_Wrapper_long_t *imuMsgQ13 = &SQRAM_CPU13_MBOX;
+static volatile IMU_Msg_Wrapper_long_t *imuMsgQ23 = &SQRAM_CPU23_MBOX;
+__attribute__((section(".smu_cpu31_txq"))) static volatile uint8_t __attribute__((aligned(4)))
+imumcTxBuf13[IMUMC_TXQ13_BUFSIZE][IMUMC_TXQ13_BUFLENGTH];
+__attribute__((section(".smu_cpu32_txq"))) static volatile uint8_t __attribute__((aligned(4)))
+imumcTxBuf23[IMUMC_TXQ23_BUFSIZE][IMUMC_TXQ23_BUFLENGTH];
+
+static void HAL_ImuMainCpu13(void *argv);
+static void HAL_ImuMainCpu23(void *argv);
+
+static OSA_TASK_HANDLE_DEFINE(ImuTaskHandleCpu13);
+static OSA_TASK_HANDLE_DEFINE(ImuTaskHandleCpu23);
+static OSA_TASK_DEFINE(HAL_ImuMainCpu13, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
+static OSA_TASK_DEFINE(HAL_ImuMainCpu23, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
+OSA_EVENT_HANDLE_DEFINE(ImuQ13FlagsRef);
+OSA_EVENT_HANDLE_DEFINE(ImuQ23FlagsRef);
+#endif
+
+OSA_EVENT_HANDLE_DEFINE(imumcQFlagsRef);
+
+#if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
+static gdma_handle_t gdmaHandle;
+OSA_SEMAPHORE_HANDLE_DEFINE(gdmaSemHandle);
+OSA_EVENT_HANDLE_DEFINE(gdmaFlagsRef);
+#endif
+
+/**************Internal helper functions***********************/
+/// \cond
+#if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
+static void HAL_GdmaCallback(gdma_handle_t *handle, void *userData, uint32_t interrupts)
+{
+    if (0UL != (interrupts & kGDMA_TransferDoneFlag))
+    {
+        (void)OSA_EventSet((osa_event_handle_t)gdmaFlagsRef, HAL_GDMA_DONE_EVENT);
+    }
+}
+
+static void HAL_InitGdma(void)
+{
+    if (gdmaHandle.callback)
+        return;
+
+    GDMA_Init(HAL_GDMA);
+    GDMA_CreateHandle(&gdmaHandle, HAL_GDMA, HAL_GDMA_CH);
+    GDMA_SetCallback(&gdmaHandle, HAL_GdmaCallback, NULL);
+    OSA_SemaphoreCreate(gdmaSemHandle, 1U);
+    (void)OSA_EventCreate(gdmaFlagsRef, 1U);
+    NVIC_SetPriority(GDMA_IRQn, GDMA_ISR_PRIORITY);
+}
+
+void HAL_ImuGdmaCopyData(void *destAddr, void *srcAddr, uint32_t len)
+{
+    uint32_t Events;
+    gdma_channel_xfer_config_t xferConfig = {0};
+
+    xferConfig.srcAddr        = (uint32_t)srcAddr;
+    xferConfig.destAddr       = (uint32_t)destAddr;
+    xferConfig.linkListAddr   = 0; /* Don't use LLI */
+    xferConfig.ahbProt        = kGDMA_ProtPrevilegedMode;
+    xferConfig.srcBurstSize   = kGDMA_BurstSize16;
+    xferConfig.destBurstSize  = kGDMA_BurstSize16;
+    xferConfig.srcWidth       = kGDMA_TransferWidth1Byte;
+    xferConfig.destWidth      = kGDMA_TransferWidth1Byte;
+    xferConfig.srcAddrInc     = true;
+    xferConfig.destAddrInc    = true;
+    xferConfig.transferLen    = len;
+    xferConfig.enableLinkList = false;
+
+    if (KOSA_StatusSuccess == OSA_SemaphoreWait(gdmaSemHandle, osaWaitForever_c))
+    {
+        GDMA_SubmitTransfer(&gdmaHandle, &xferConfig);
+        GDMA_StartTransfer(&gdmaHandle);
+        /* Wait for GMDA transfer done. */
+        (void)OSA_EventWait((osa_event_handle_t)gdmaFlagsRef, HAL_GDMA_DONE_EVENT, 0, osaWaitForever_c, &Events);
+        OSA_SemaphorePost(gdmaSemHandle);
+    }
+}
+#endif
+
+static void HAL_ImuSetCpuReadyFlag(uint8_t cpuId)
+{
+}
+
+bool HAL_ImuGetCpuReadyFlag(uint8_t cpuId)
+{
+    return TRUE;
+}
+
+/*!
+ * @brief
+ * Create a new imumc endpoint, which can be used
+ * for communication.
+ *
+ * @param handle            Imumc instance
+ * @param addr              source endpoint address
+ *
+ * @return       RL_NULL if not found, node pointer containing the ept on success
+ *
+ */
+static hal_imumc_handle_t HAL_ImumcGetEndpointFromAddr(hal_imu_handle_t *imuHandle, uint32_t addr)
+{
+    LIST_ELEM_st *cur;
+    hal_imumc_state_t *pEnd;
+
+    assert(NULL != imuHandle);
+
+    list_for_each(cur, &imuHandle->eptList)
+    {
+        pEnd = (hal_imumc_state_t *)cur;
+        if (pEnd->local_addr == addr)
+        {
+            return pEnd;
+        }
+    }
+
+    return NULL;
+}
+
+static hal_imumc_handle_t HAL_ImumcCreateEndpoint(hal_imumc_handle_t handle)
+{
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_state_t *imumcHandle;
+    assert(NULL != handle);
+
+    imumcHandle = (hal_imumc_state_t *)handle;
+    imuHandle   = &imuHandleCh[imumcHandle->imuLink];
+    // env_lock_mutex(imumcHandle->lock);
+    {
+        if (NULL == HAL_ImumcGetEndpointFromAddr(imuHandle, imumcHandle->local_addr))
+        {
+            LIST_addTail(&imuHandle->eptList, &imumcHandle->eptLink);
+            // env_unlock_mutex(imumcHandle->lock);
+            return imumcHandle;
+        }
+    }
+    // env_unlock_mutex(imumcHandle->lock);
+    return NULL;
+}
+
+static hal_imumc_status_t HAL_ImumcDestroyEndpoint(hal_imumc_handle_t handle)
+{
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_state_t *imumcHandle;
+    assert(NULL != handle);
+
+    imumcHandle = (hal_imumc_state_t *)handle;
+    imuHandle   = &imuHandleCh[imumcHandle->imuLink];
+
+    // env_lock_mutex(imumcHandle->lock);
+    {
+        imumcHandle = HAL_ImumcGetEndpointFromAddr(imuHandle, imumcHandle->local_addr);
+
+        if (NULL == imumcHandle)
+        {
+            // env_unlock_mutex(imumcHandle->lock);
+            return kStatus_HAL_ImumcError;
+        }
+        LIST_remove(&imuHandle->eptList, &imumcHandle->eptLink);
+    }
+    // env_unlock_mutex(imumcHandle->lock);
+    return kStatus_HAL_ImumcSuccess;
+}
+
+static uint8_t *HAL_ImuGetWlanTxBuf(hal_imu_handle_t *imuHandle)
+{
+    uint32_t wlanTxBuf;
+    IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
+
+    assert(NULL != imuHandle);
+    wlanTxqCtl = &imuHandle->wlanTxqCtl;
+
+    if (IS_WLAN_TXBQ_EMPTY(wlanTxqCtl))
+    {
+        return NULL;
+    }
+    else
+    {
+        wlanTxBuf = wlanTxqCtl->txBufQue[wlanTxqCtl->readIndex & IMU_TXQ_ENTRY_MASK];
+        INCR_WLAN_TXBQ_RD_INDEX(wlanTxqCtl, 1U);
+        return (uint8_t *)wlanTxBuf;
+    }
+}
+
+static hal_imumc_status_t HAL_ImuPutWlanTxBuf(hal_imu_handle_t *imuHandle, uint8_t *txBuf)
+{
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
+
+    assert(NULL != imuHandle);
+    wlanTxqCtl = &imuHandle->wlanTxqCtl;
+
+    if (IS_WLAN_TXBQ_FULL(wlanTxqCtl))
+    {
+        state = kStatus_HAL_ImumcError;
+    }
+    else
+    {
+        wlanTxqCtl->txBufQue[wlanTxqCtl->writeIndex & IMU_TXQ_ENTRY_MASK] = (uint32_t)txBuf;
+        INCR_WLAN_TXBQ_WR_INDEX(wlanTxqCtl, 1U);
+    }
+
+    return state;
+}
+
+static uint8_t *HAL_ImumcGetTxBuf(hal_imu_handle_t *imuHandle)
+{
+    uint8_t *imumcTxBuf = NULL;
+    IMUMC_TXQ_CTRL_st *imumcTxqCtl;
+    OSA_SR_ALLOC();
+
+    assert(NULL != imuHandle);
+    imumcTxqCtl = &imuHandle->imumcTxqCtl;
+
+    OSA_ENTER_CRITICAL();
+
+    do
+    {
+        if (imuHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
+        {
+            if (IS_IMUMC_TXBQ23_EMPTY(imumcTxqCtl))
+            {
+                break;
+            }
+            else
+            {
+                imumcTxBuf = (uint8_t *)(imumcTxqCtl->txBufQue[imumcTxqCtl->readIndex & IMUMC_TXQ23_ENTRY_MASK]);
+                INCR_IMUMC_TXBQ23_RD_INDEX(imumcTxqCtl, 1U);
+            }
+        }
+        else
+        {
+            if (IS_IMUMC_TXBQ13_EMPTY(imumcTxqCtl))
+            {
+                break;
+            }
+            else
+            {
+                imumcTxBuf = (uint8_t *)(imumcTxqCtl->txBufQue[imumcTxqCtl->readIndex & IMUMC_TXQ13_ENTRY_MASK]);
+                INCR_IMUMC_TXBQ13_RD_INDEX(imumcTxqCtl, 1U);
+            }
+        }
+    } while (false);
+
+    OSA_EXIT_CRITICAL();
+
+    return imumcTxBuf;
+}
+
+static hal_imumc_status_t HAL_ImumcPutTxBuf(hal_imu_handle_t *imuHandle, uint8_t *txBuf)
+{
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    IMUMC_TXQ_CTRL_st *imumcTxqCtl;
+    OSA_SR_ALLOC();
+
+    assert(NULL != imuHandle);
+    imumcTxqCtl = &imuHandle->imumcTxqCtl;
+
+    OSA_ENTER_CRITICAL();
+
+    if (imuHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
+    {
+        if (IS_IMUMC_TXBQ23_FULL(imumcTxqCtl))
+        {
+            state = kStatus_HAL_ImumcError;
+        }
+        else
+        {
+            imumcTxqCtl->txBufQue[imumcTxqCtl->writeIndex & IMUMC_TXQ23_ENTRY_MASK] = (uint32_t)txBuf;
+            INCR_IMUMC_TXBQ23_WR_INDEX(imumcTxqCtl, 1U);
+        }
+    }
+    else
+    {
+        if (IS_IMUMC_TXBQ13_FULL(imumcTxqCtl))
+        {
+            state = kStatus_HAL_ImumcError;
+        }
+        else
+        {
+            imumcTxqCtl->txBufQue[imumcTxqCtl->writeIndex & IMUMC_TXQ13_ENTRY_MASK] = (uint32_t)txBuf;
+            INCR_IMUMC_TXBQ13_WR_INDEX(imumcTxqCtl, 1U);
+        }
+    }
+
+    OSA_EXIT_CRITICAL();
+
+    return state;
+}
+
+hal_imumc_status_t HAL_ImuLinkIsUp(uint8_t imuLink)
+{
+    hal_imu_handle_t *imuHandle;
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    imuHandle = &imuHandleCh[imuLink];
+
+    if ((uint8_t)IMU_INITIALIZED == imuHandle->imuSyncState)
+    {
+        return kStatus_HAL_ImumcSuccess;
+    }
+    else
+    {
+        return kStatus_HAL_ImumcError;
+    }
+}
+
+void HAL_ImuResetWlanTxq(uint8_t imuLink)
+{
+    hal_imu_handle_t *imuHandle = NULL;
+
+    imuHandle                        = &imuHandleCh[imuLink];
+    imuHandle->wlanTxqCtl.writeIndex = 0;
+    imuHandle->wlanTxqCtl.readIndex  = 0;
+}
+
+static hal_imumc_status_t HAL_ImuSendMsgBlockingCommon(
+    hal_imu_handle_t *imuHandle, uint8_t type, uint8_t subtype, uint8_t *data, uint32_t length, bool lockTxFifo)
+{
+    IMU_Msg_t *imuMsg;
+    IMU_Msg_t localImuMsg;
+    OSA_SR_ALLOC();
+    int32_t ret = 0;
+
+    assert(NULL != imuHandle);
+    assert(IMU_PAYLOAD_SIZE >= length);
+
+    (void)memset((void *)&localImuMsg, 0, sizeof(IMU_Msg_t));
+
+    localImuMsg.Hdr.type     = type;
+    localImuMsg.Hdr.sub_type = subtype;
+    localImuMsg.Hdr.seq_num  = seq_num & (uint8_t)0xff;
+
+    switch ((imu_msg_type_t)type)
+    {
+        case IMU_MSG_CONTROL:
+            if (((uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR == subtype) ||
+                ((uint8_t)IMU_MSG_CONTROL_FREE_RX_BUF == subtype) ||
+                ((uint8_t)IMU_MSG_CONTROL_CMD_BUF_ADDR == subtype) || ((uint8_t)IMU_MSG_CONTROL_EVT_ACK == subtype) ||
+                ((uint8_t)IMU_MSG_CONTROL_COMMAND_RSP_ACK == subtype) ||
+                ((uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY == subtype) ||
+                ((uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY_RSP == subtype) ||
+                ((uint8_t)IMU_MSG_CONTROL_IMUMC_BUF_FREE == subtype) ||
+                ((uint8_t)IMU_MSG_CONTROL_EVT_DUMP == subtype) || ((uint8_t)IMU_MSG_CONTROL_ERROR == subtype))
+            {
+                (void)memcpy((void *)&localImuMsg.PayloadPtr[0], data, length << 2U);
+                localImuMsg.Hdr.length = (uint8_t)length;
+            }
+            break;
+        case IMU_MSG_COMMAND:
+            if (imuHandle->cmd_buffer_available)
+            {
+                localImuMsg.Hdr.length    = 1;
+                localImuMsg.PayloadPtr[0] = (uint32_t)imuHandle->cmd_buffer;
+            }
+            else
+            {
+                return kStatus_HAL_ImumcError;
+            }
+            break;
+        case IMU_MSG_TX_DATA:
+            localImuMsg.Hdr.length    = 1;
+            localImuMsg.PayloadPtr[0] = (uint32_t)data;
+            break;
+        case IMU_MSG_MULTI_TX_DATA:
+            (void)memcpy((void *)&localImuMsg.PayloadPtr[0], imuHandle->imuMsgBuf, (imuHandle->imuMsgBufIdx) << 2U);
+            localImuMsg.Hdr.length  = imuHandle->imuMsgBufIdx;
+            imuHandle->imuMsgBufIdx = 0;
+            break;
+        case IMU_MSG_IMUMC:
+            (void)memcpy((void *)&localImuMsg.PayloadPtr[0], data, length << 2U);
+            localImuMsg.Hdr.length = length;
+            break;
+        default:
+            // Do nothing for the commands without expansion.
+            break;
+    }
+
+    /* Added at 02/18/2022, in case second task overwriting imuMsg*/
+    while (IMU_TX_FIFO_ALMOST_FULL((imu_link_t)imuHandle->imuLink))
+    {
+    }
+
+    OSA_ENTER_CRITICAL();
+    imuMsg = (IMU_Msg_t *)&((IMU_MSG_SND_Q(imuHandle->imuLink))[IMU_WR_PTR(imuHandle->imuLink)]);
+    (void)memcpy(imuMsg, &localImuMsg, sizeof(IMU_Hdr_t) + ((uint32_t)localImuMsg.Hdr.length << 2U));
+    ret = IMU_SendMsgPtrBlocking((imu_link_t)imuHandle->imuLink, (uint32_t)imuMsg, lockTxFifo);
+    OSA_EXIT_CRITICAL();
+
+    if (0 == ret)
+    {
+        return kStatus_HAL_ImumcSuccess;
+    }
+    else
+    {
+        return kStatus_HAL_ImumcError;
+    }
+}
+
+static hal_imumc_status_t HAL_ImuSendMsgBlocking(
+    hal_imu_handle_t *imuHandle, uint8_t type, uint8_t subtype, uint8_t *data, uint32_t length)
+{
+    return HAL_ImuSendMsgBlockingCommon(imuHandle, type, subtype, data, length, FALSE);
+}
+
+static hal_imumc_status_t HAL_ImuSendSync(hal_imu_handle_t *imuHandle)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = IMU_SYNC_MAGIC_PATTERN;
+    while (IMU_SYNC_MAGIC_PATTERN != (*IMU_MSG_CUR_MAGIC_P((imu_link_t)imuHandle->imuLink)))
+    {
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (((uint8_t)IMU_UNINITIALIZED == imuHandle->imuSyncState) &&
+        (IMU_SYNC_MAGIC_PATTERN == (*IMU_MSG_PEER_MAGIC_P(imuHandle->imuLink))))
+    {
+        if (kStatus_HAL_ImumcSuccess ==
+            HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SYNC, NULL, 0))
+        {
+            imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZING;
+            seq_num++;
+        }
+        else
+        {
+            imumcStatus = kStatus_HAL_ImumcError;
+        }
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendImumcEptQuiry(hal_imu_handle_t *imuHandle, uint32_t addr)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
+                                                           (uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY, (uint8_t *)&addr,
+                                                           1))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendImumcEptQuiryRsp(hal_imu_handle_t *imuHandle, uint32_t addr, bool found)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    uint32_t quiryRsp[2];
+    OSA_SR_ALLOC();
+
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    quiryRsp[0] = addr;
+    if (TRUE == found)
+    {
+        quiryRsp[1] = 1;
+    }
+    else
+    {
+        quiryRsp[1] = 0;
+    }
+
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
+                                                           (uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY_RSP,
+                                                           (uint8_t *)&quiryRsp[0], 2))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendImumcFreeBuf(hal_imu_handle_t *imuHandle, uint8_t *buf)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess ==
+        HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_IMUMC_BUF_FREE, buf, 1U))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendEventAck(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess ==
+        HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_EVT_ACK, rxBuf, length))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuSendEventDumpAck(imu_link_t link, uint8_t *rxBuf, uint8_t length)
+{
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+
+    assert(kIMU_LinkMax > link);
+    imuHandle = &imuHandleCh[link];
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess ==
+        HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_EVT_DUMP, rxBuf, length))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendCommandRspAck(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
+                                                           (uint8_t)IMU_MSG_CONTROL_COMMAND_RSP_ACK, rxBuf, length))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuFreeRxBuf(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
+                                                           (uint8_t)IMU_MSG_CONTROL_FREE_RX_BUF, rxBuf, length))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuSendCommand(uint8_t imuLink, uint8_t *cmdBuf, uint32_t length)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    hal_imu_handle_t *imuHandle;
+    OSA_SR_ALLOC();
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    imuHandle = &imuHandleCh[imuLink];
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink) || FALSE == imuHandle->cmd_buffer_available)
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    if (length != 0U)
+    {
+        // To be DMAed
+        (void)HAL_IMU_MEMCPY((void *)imuHandle->cmd_buffer, cmdBuf, length);
+    }
+    else
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_COMMAND, 0U, NULL, 0))
+    {
+        seq_num++;
+        imuHandle->cmd_buffer_available = FALSE;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuSendTxData(uint8_t imuLink, uint8_t *txBuf, uint32_t length)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    hal_imu_handle_t *imuHandle;
+    uint8_t *wlan_tx_buf;
+    OSA_SR_ALLOC();
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    imuHandle = &imuHandleCh[imuLink];
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
+    if ((wlan_tx_buf != NULL) && (length != 0U))
+    {
+        // To be DMAed
+        (void)HAL_IMU_MEMCPY(wlan_tx_buf, txBuf, length);
+    }
+    else
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_TX_DATA, 0U, wlan_tx_buf, 1U))
+    {
+        seq_num++;
+    }
+    else
+    {
+        (void)HAL_ImuPutWlanTxBuf(imuHandle, wlan_tx_buf);
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuAddWlanTxPacket(uint8_t imuLink, uint8_t *txBuf, uint32_t length)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    hal_imu_handle_t *imuHandle;
+    uint8_t *wlan_tx_buf;
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    assert(NULL != txBuf);
+    assert(0U != length);
+    imuHandle = &imuHandleCh[imuLink];
+
+    if (imuHandle->imuMsgBufIdx > IMU_PAYLOAD_SIZE - 1U)
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
+
+    if (NULL == wlan_tx_buf)
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    // To be DMAed
+    (void)HAL_IMU_MEMCPY(wlan_tx_buf, txBuf, length);
+
+    imuHandle->imuMsgBuf[imuHandle->imuMsgBufIdx] = (uint32_t)wlan_tx_buf;
+    imuHandle->imuMsgBufIdx++;
+
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuAddWlanTxPacketExt(uint8_t imuLink,
+                                             uint8_t *txBuf,
+                                             uint32_t length,
+                                             void (*cb)(void *destAddr, void *srcAddr, uint32_t len))
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    hal_imu_handle_t *imuHandle;
+    uint8_t *wlan_tx_buf;
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    assert(NULL != txBuf);
+    assert(0U != length);
+    imuHandle = &imuHandleCh[imuLink];
+
+    if (imuHandle->imuMsgBufIdx > IMU_PAYLOAD_SIZE - 1U)
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
+
+    if (NULL == wlan_tx_buf)
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    // To be DMAed
+    cb(wlan_tx_buf, txBuf, length);
+
+    imuHandle->imuMsgBuf[imuHandle->imuMsgBufIdx] = (uint32_t)wlan_tx_buf;
+    imuHandle->imuMsgBufIdx++;
+
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuSendMultiTxData(uint8_t imuLink)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    hal_imu_handle_t *imuHandle;
+    OSA_SR_ALLOC();
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    imuHandle = &imuHandleCh[imuLink];
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_MULTI_TX_DATA, 0U, NULL, 0U))
+    {
+        seq_num++;
+        imuHandle->imuMsgBufIdx = 0;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendSyncAck(hal_imu_handle_t *imuHandle)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess ==
+        HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SYNC_ACK, NULL, 0U))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendUnlock(hal_imu_handle_t *imuHandle)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess ==
+        HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_ACK_FOR_UNLOCK, NULL, 0U))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuReturnAllTxBuf(imu_link_t link)
+{
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    uint8_t txBufCnt;
+    uint8_t *wlan_tx_buf;
+    OSA_SR_ALLOC();
+
+    assert(kIMU_LinkMax > link);
+    imuHandle = &imuHandleCh[link];
+
+    txBufCnt = 0;
+    while (TRUE)
+    {
+        wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
+        if (NULL == wlan_tx_buf) /*! all Tx buffers are consumed */
+        {
+            break;
+        }
+
+        imuHandle->imuMsgBuf[txBufCnt] = (uint32_t)wlan_tx_buf;
+        txBufCnt++;
+
+        if (IMU_PAYLOAD_SIZE == txBufCnt)
+        {
+            OSA_ENTER_CRITICAL();
+            if (kStatus_HAL_ImumcSuccess !=
+                HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR,
+                                       (uint8_t *)&imuHandle->imuMsgBuf[0], (uint32_t)IMU_PAYLOAD_SIZE))
+            {
+                OSA_EXIT_CRITICAL();
+                return kStatus_HAL_ImumcError;
+            }
+            else
+            {
+                seq_num++;
+            }
+            txBufCnt = 0;
+            OSA_EXIT_CRITICAL();
+        }
+    }
+
+    if (txBufCnt != 0U)
+    {
+        OSA_ENTER_CRITICAL();
+        if (kStatus_HAL_ImumcSuccess != HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
+                                                               (uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR,
+                                                               (uint8_t *)&imuHandle->imuMsgBuf[0], txBufCnt))
+        {
+            OSA_EXIT_CRITICAL();
+            return kStatus_HAL_ImumcError;
+        }
+        else
+        {
+            seq_num++;
+        }
+        OSA_EXIT_CRITICAL();
+    }
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuSendShutdown(hal_imu_handle_t *imuHandle)
+{
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    assert(NULL != imuHandle);
+
+    if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+        return kStatus_HAL_ImumcError;
+    }
+
+    OSA_ENTER_CRITICAL();
+    if (kStatus_HAL_ImumcSuccess ==
+        HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SHUTDOWN, NULL, 0U))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+    OSA_EXIT_CRITICAL();
+
+    return imumcStatus;
+}
+
+static hal_imumc_status_t HAL_ImuCtrlHandler(hal_imu_handle_t *imuHandle, IMU_Msg_t *data, uint32_t len)
+{
+    imu_ctrl_msg_subtype_t imuControlType;
+    IMU_Msg_t *pImuMsg             = data;
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    hal_imumc_state_t *imumcHandle;
+    OSA_SR_ALLOC();
+    LIST_ELEM_st *cur;
+    uint8_t eptQuiryRspAck;
+
+    assert(NULL != imuHandle);
+    imuControlType = (imu_ctrl_msg_subtype_t)pImuMsg->Hdr.sub_type;
+    OSA_ENTER_CRITICAL();
+
+    switch (imuControlType)
+    {
+        case IMU_MSG_CONTROL_ACK_FOR_UNLOCK:
+            IMU_UNLOCK_TX_FIFO(imuHandle->imuLink);
+            break;
+        case IMU_MSG_CONTROL_SYNC:
+            (void)HAL_ImuSendSyncAck(imuHandle);
+            if ((uint8_t)kIMU_LinkCpu2Cpu3 == imuHandle->imuLink)
+            {
+                imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
+            }
+            (void)HAL_ImuSendSyncAck(imuHandle);
+            imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
+            break;
+        case IMU_MSG_CONTROL_SYNC_ACK:
+            imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
+            break;
+        case IMU_MSG_CONTROL_CMD_BUF_ADDR:
+            imuHandle->cmd_buffer           = (uint32_t *)pImuMsg->PayloadPtr[0];
+            imuHandle->cmd_buffer_available = TRUE;
+            if ((uint8_t)IMU_INITIALIZED != imuHandle->imuSyncState)
+            {
+                imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
+            }
+            break;
+        case IMU_MSG_CONTROL_TX_BUF_ADDR:
+            for (uint8_t i = 0; i < pImuMsg->Hdr.length; i++)
+            {
+                (void)HAL_ImuPutWlanTxBuf(imuHandle, (uint8_t *)pImuMsg->PayloadPtr[i]);
+            }
+            break;
+        case IMU_MSG_CONTROL_ERROR:
+            break;
+        case IMU_MSG_CONTROL_SHUTDOWN:
+            imuHandle->imuSyncState = (uint8_t)IMU_UNINITIALIZED;
+            IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+            IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK);
+            (void)os_InterruptMaskClear(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
+            IMU_Deinit((imu_link_t)imuHandle->imuLink);
+            *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = 0;
+            imuHandle->wlanTxqCtl.writeIndex         = 0;
+            imuHandle->wlanTxqCtl.readIndex          = 0;
+            break;
+        case IMU_MSG_CONTROL_IMUMC_EPT_QUIRY:
+        {
+            hal_imumc_state_t *imumcHandle = HAL_ImumcGetEndpointFromAddr(imuHandle, pImuMsg->PayloadPtr[0]);
+            if (imumcHandle != NULL)
+            {
+                /* The remote CPU is sending an endpoint query so it implies the imumc link is ready */
+                imumcHandle->eptLinkIsReady = TRUE;
+                /* Confirm the local endpoint is ready too */
+                imumcStatus = HAL_ImuSendImumcEptQuiryRsp(imuHandle, pImuMsg->PayloadPtr[0], TRUE);
+                /* Make sure to unblock the task calling HAL_ImumcInit */
+                (void)OSA_EventSet((osa_event_handle_t)imumcQFlagsRef,
+                                   IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
+            }
+            else
+            {
+                /* Local endpoint doesn't exist yet, the remote CPU needs to wait until the local CPU initializes
+                 * the targeted endpoint, a new query will be sent then to update the link status on both sides */
+                imumcStatus = HAL_ImuSendImumcEptQuiryRsp(imuHandle, pImuMsg->PayloadPtr[0], FALSE);
+            }
+        }
+        break;
+        case IMU_MSG_CONTROL_IMUMC_EPT_QUIRY_RSP:
+            eptQuiryRspAck = 0;
+            list_for_each(cur, &imuHandle->eptList)
+            {
+                imumcHandle = (hal_imumc_state_t *)cur;
+                if (imumcHandle->remote_addr == pImuMsg->PayloadPtr[0])
+                {
+                    if (pImuMsg->PayloadPtr[1] != 0U)
+                    {
+                        eptQuiryRspAck              = 1;
+                        imumcHandle->eptLinkIsReady = TRUE;
+                    }
+                    else
+                    {
+                        imumcHandle->eptLinkIsReady = FALSE;
+                    }
+                }
+            }
+
+            if (eptQuiryRspAck != 0U)
+            {
+                /* Make sure to unblock the task calling HAL_ImumcInit */
+                (void)OSA_EventSet((osa_event_handle_t)imumcQFlagsRef,
+                                   IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
+            }
+            break;
+        case IMU_MSG_CONTROL_IMUMC_BUF_FREE:
+            (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)pImuMsg->PayloadPtr[0]);
+            break;
+        default:
+            // Do nothing for the commands without header expansion.
+            break;
+    }
+
+    OSA_EXIT_CRITICAL();
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuReceive(uint8_t imuLink)
+{
+    IMU_Msg_t *pMsg = NULL, localImuMsg;
+    IMU_Msg_t localImuMsgRx;
+
+    hal_imu_handle_t *imuHandle = NULL;
+    imu_msg_type_t msg_type     = IMU_MSG_MAX;
+    bool isUnlockMsgReqd        = FALSE;
+    hal_imumc_state_t *ept;
+    struct imumc_std_msg *imumc_msg;
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    imuHandle = &imuHandleCh[imuLink];
+
+    while (TRUE)
+    {
+        if (IMU_RX_FIFO_EMPTY((imu_link_t)imuHandle->imuLink))
+        {
+            IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+            os_ClearPendingISR(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
+#ifndef CPU2
+            *IMU_SLEEP_FLAG_ADDR(imuHandle->imuLink) |= (uint32_t)(1 << 0U);
+#endif
+            break;
+        }
+        else
+        {
+#ifndef CPU2
+            *IMU_SLEEP_FLAG_ADDR(imuHandle->imuLink) &= (uint32_t)(~(1 << 0U));
+#endif
+
+            /* Message buffer pMsg should be consumed (or copied for later
+             * processing) in handler before call for next READ_ICC_MESSAGE
+             * comes here again.
+             * Otherwise other CPU may use same pMsg for next write,
+             * when FIFO is almost full
+             */
+            pMsg = (IMU_Msg_t *)IMU_RD_MSG(imuHandle->imuLink);
+            if ((pMsg != NULL) && (IMU_RX_FIFO_LOCKED(imuHandle->imuLink)))
+            {
+                isUnlockMsgReqd = TRUE;
+            }
+        }
+
+        /* release CPU access here because message processing may take time */
+        if (pMsg != NULL)
+        {
+            (void)memcpy((uint8_t *)&localImuMsg, (uint8_t *)pMsg, sizeof(IMU_Msg_t));
+            pMsg     = &localImuMsg;
+            msg_type = (imu_msg_type_t)pMsg->Hdr.type;
+
+            switch (msg_type)
+            {
+                case IMU_MSG_CONTROL:
+                    imumcStatus = HAL_ImuCtrlHandler(imuHandle, pMsg, pMsg->Hdr.length);
+                    if (imuHandle->imuHandler[IMU_MSG_CONTROL] != NULL)
+                    {
+                        imumcStatus = imuHandle->imuHandler[IMU_MSG_CONTROL]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
+                    }
+                    break;
+                case IMU_MSG_COMMAND_RESPONSE:
+                    if (imuHandle->imuHandler[IMU_MSG_COMMAND_RESPONSE] != NULL)
+                    {
+                        imumcStatus =
+                            imuHandle->imuHandler[IMU_MSG_COMMAND_RESPONSE]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
+                    }
+                    assert(kStatus_HAL_ImumcSuccess == imumcStatus);
+                    imumcStatus = HAL_ImuSendCommandRspAck(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], 1);
+                    imuHandle->cmd_buffer_available = TRUE;
+                    break;
+
+                case IMU_MSG_EVENT:
+                    if (imuHandle->imuHandler[IMU_MSG_EVENT] != NULL)
+                    {
+                        imumcStatus = imuHandle->imuHandler[IMU_MSG_EVENT]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
+                    }
+                    assert(kStatus_HAL_ImumcSuccess == imumcStatus);
+                    imumcStatus = HAL_ImuSendEventAck(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], 1);
+                    break;
+
+                case IMU_MSG_RX_DATA:
+                case IMU_MSG_MULTI_RX_DATA:
+                    (void)memcpy((uint8_t *)&localImuMsgRx, (uint8_t *)pMsg, sizeof(IMU_Msg_t));
+                    if (imuHandle->imuHandler[IMU_MSG_RX_DATA] != NULL)
+                    {
+                        imumcStatus = imuHandle->imuHandler[IMU_MSG_RX_DATA]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
+                    }
+                    pMsg        = &localImuMsgRx;
+                    imumcStatus = HAL_ImuFreeRxBuf(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], pMsg->Hdr.length);
+                    break;
+                case IMU_MSG_IMUMC:
+                    imumc_msg = (struct imumc_std_msg *)&pMsg->PayloadPtr[0];
+                    ept       = (hal_imumc_state_t *)HAL_ImumcGetEndpointFromAddr(imuHandle, imumc_msg->hdr.dst);
+                    if (NULL != ept)
+                    {
+                        if (ept->rx.callback != NULL)
+                        {
+                            imumcStatus = (hal_imumc_status_t)ept->rx.callback(
+                                ept->rx.param, (uint8_t *)imumc_msg->data, imumc_msg->hdr.len);
+                        }
+                    }
+                    if ((hal_imumc_return_status_t)imumcStatus == kStatus_HAL_RL_RELEASE)
+                    {
+                        imumcStatus = HAL_ImuSendImumcFreeBuf(imuHandle, (uint8_t *)&imumc_msg->data);
+                    }
+                    break;
+
+                default:
+                    // Do nothing for the commands without expansion.
+                    break;
+            }
+
+            assert(kStatus_HAL_ImumcSuccess == imumcStatus);
+        }
+    }
+
+    if (isUnlockMsgReqd)
+    {
+        (void)HAL_ImuSendUnlock(imuHandle);
+    }
+
+    (void)os_InterruptMaskSet(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
+    return (hal_imumc_status_t)imumcStatus;
+}
+
+#if defined(CPU2)
+static void HAL_ImuMain(void *argv)
+{
+    uint32_t Events = 0;
+    uint32_t imuLinkId;
+
+    while (TRUE)
+    {
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+        (void)HAL_ImuPutTaskLock();
+#endif
+        (void)OSA_EventWait((osa_event_handle_t)ImuQFlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
+        if (Events == 0U)
+        {
+            if (gUseRtos_c == 0U)
+            {
+                break;
+            }
+            else
+            {
+                continue;
+            }
+        }
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+        (void)HAL_ImuGetTaskLock();
+#endif
+        /*! Check for all IMU links event/ISR has occured
+         *  Only MSG ready events considered
+         */
+        for (imuLinkId = 0; imuLinkId < (uint32_t)kIMU_LinkMax; imuLinkId++)
+        {
+            if ((Events & (1U << imuLinkId)) != 0U)
+            {
+                (void)HAL_ImuReceive((uint8_t)imuLinkId);
+            }
+        }
+        if (gUseRtos_c == 0U)
+        {
+            break;
+        }
+    }
+}
+#else
+
+static void HAL_ImuMainCpu13(void *argv)
+{
+    uint32_t Events = 0;
+
+    while (TRUE)
+    {
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+        (void)HAL_ImuPutTaskLock();
+#endif
+
+        (void)OSA_EventWait((osa_event_handle_t)ImuQ13FlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
+        if (Events == 0U)
+        {
+            if (gUseRtos_c == 0U)
+            {
+                break;
+            }
+            else
+            {
+                continue;
+            }
+        }
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+        (void)HAL_ImuGetTaskLock();
+#endif
+        /*! Check for CPU1 to CPU3 IMU links event/ISR has occured
+         *  Only MSG ready events considered
+         */
+        (void)HAL_ImuReceive(kIMU_LinkCpu1Cpu3);
+
+        if (gUseRtos_c == 0U)
+        {
+            break;
+        }
+    }
+}
+
+static void HAL_ImuMainCpu23(void *argv)
+{
+    uint32_t Events = 0;
+
+    while (TRUE)
+    {
+#if 0
+        HAL_ImuPutTaskLock();
+#endif
+
+        (void)OSA_EventWait((osa_event_handle_t)ImuQ23FlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
+
+        if (Events == 0U)
+        {
+            if (gUseRtos_c == 0U)
+            {
+                break;
+            }
+            else
+            {
+                continue;
+            }
+        }
+#if 0
+        HAL_ImuGetTaskLock();
+#endif
+        /*! Check for CPU2 to CPU3 IMU links event/ISR has occured
+         *  Only MSG ready events considered
+         */
+
+        (void)HAL_ImuReceive(kIMU_LinkCpu2Cpu3);
+
+        if (gUseRtos_c == 0U)
+        {
+            break;
+        }
+    }
+}
+#endif
+
+static void HAL_ImuTaskInit(uint8_t link)
+{
+#if defined(CPU2)
+    (void)link;
+
+    if (((imu_init_flag & ((1U << (uint8_t)kIMU_LinkMax) - 1U)) == 0U) && imu_task_flag == 0U)
+    {
+        (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandle, OSA_TASK(HAL_ImuMain), NULL);
+        (void)OSA_EventCreate((osa_event_handle_t)ImuQFlagsRef, 1U);
+        imu_task_flag = 1;
+    }
+#else
+    if (link == kIMU_LinkCpu1Cpu3 && (imu_task_flag & (1U << link)) == 0)
+    {
+        (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandleCpu13, OSA_TASK(HAL_ImuMainCpu13), NULL);
+        (void)OSA_EventCreate((osa_event_handle_t)ImuQ13FlagsRef, 1U);
+        imu_task_flag |= (1U << link);
+    }
+    else if (link == kIMU_LinkCpu2Cpu3 && (imu_task_flag & (1U << link)) == 0)
+    {
+        (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandleCpu23, OSA_TASK(HAL_ImuMainCpu23), NULL);
+        (void)OSA_EventCreate((osa_event_handle_t)ImuQ23FlagsRef, 1U);
+        imu_task_flag |= (1U << link);
+    }
+    else
+    {
+        ; /* No necessary actions. */
+    }
+#endif
+}
+
+static void HAL_ImuTaskDeinit(uint8_t link)
+{
+#if defined(CPU2)
+    (void)link;
+
+    if (imu_init_flag == 0U && imu_task_flag != 0U)
+    {
+        (void)OSA_EventDestroy((osa_event_handle_t)ImuQFlagsRef);
+        (void)OSA_TaskDestroy(ImuTaskHandle);
+        imu_task_flag = 0;
+    }
+#else
+    if (link == kIMU_LinkCpu1Cpu3 && (imu_task_flag & (1U << link)) != 0)
+    {
+        (void)OSA_EventDestroy((osa_event_handle_t)ImuQ13FlagsRef);
+        (void)OSA_TaskDestroy(ImuTaskHandleCpu13);
+        imu_task_flag &= ~(1U << link);
+    }
+    else if (link == kIMU_LinkCpu2Cpu3 && (imu_task_flag & (1U << link)) != 0)
+    {
+        (void)OSA_EventDestroy((osa_event_handle_t)ImuQ23FlagsRef);
+        (void)OSA_TaskDestroy(ImuTaskHandleCpu23);
+        imu_task_flag &= ~(1U << link);
+    }
+    else
+    {
+        ; /* No necessary actions. */
+    }
+#endif
+}
+
+hal_imumc_status_t HAL_ImuInit(imu_link_t link)
+{
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    uint8_t i;
+    OSA_SR_ALLOC();
+
+    assert(kIMU_LinkMax > link);
+    imuHandle          = &imuHandleCh[link];
+    imuHandle->imuLink = (uint8_t)link;
+    OSA_ENTER_CRITICAL();
+
+#if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
+    if (0U == imu_init_flag)
+    {
+        HAL_InitGdma();
+    }
+#endif
+
+    /*! IMU and its interrupt are initialized once for each IMU link */
+    if ((imu_init_flag & (1U << imuHandle->imuLink)) == 0U)
+    {
+        HAL_ImuTaskInit(imuHandle->imuLink);
+
+        if (IMU_Init(link) != (int)kStatus_HAL_ImumcSuccess)
+        {
+            return kStatus_HAL_ImumcError;
+        }
+        IMU_ClearPendingInterrupts(link, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+        os_ClearPendingISR(IMULINKID_TO_IRQID(link));
+        /* Interrupt must be maskable by FreeRTOS critical section */
+        NVIC_SetPriority(IMULINKID_TO_IRQID(link), IMU_ISR_PRIORITY);
+        (void)os_InterruptMaskSet(IMULINKID_TO_IRQID(link));
+#if defined(CPU2)
+        if (kIMU_LinkCpu2Cpu3 == link)
+        {
+            for (i = 0; i < IMUMC_TXQ23_BUFSIZE; i++)
+            {
+                (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)imumcTxBuf23[i]);
+            }
+        }
+#else
+        imuHandle->wlanTxqCtl.writeIndex  = 0;
+        imuHandle->wlanTxqCtl.readIndex   = 0;
+        imuHandle->imuMsgBufIdx           = 0;
+        imuHandle->imumcTxqCtl.writeIndex = 0;
+        imuHandle->imumcTxqCtl.readIndex  = 0;
+        if (kIMU_LinkCpu1Cpu3 == link)
+        {
+            for (i = 0; i < IMUMC_TXQ13_BUFSIZE; i++)
+            {
+                (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)imumcTxBuf13[i]);
+            }
+        }
+        else if (kIMU_LinkCpu2Cpu3 == link)
+        {
+            for (i = 0; i < IMUMC_TXQ23_BUFSIZE; i++)
+            {
+                (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)imumcTxBuf23[i]);
+            }
+        }
+        else
+        {
+            ; /* No necessary actions. */
+        }
+#endif
+        LIST_init(&imuHandle->eptList);
+        imu_init_flag |= (1U << imuHandle->imuLink);
+    }
+
+    /*! Could be moved out from imumc_init() */
+    if (imu_init_flag == ((1U << kIMU_LinkMax) - 1U)) /*! All IMU links are initalized */
+    {
+        HAL_ImuSetCpuReadyFlag(1U /*! Set CPU1 state */);
+    }
+
+    if ((uint8_t)IMU_UNINITIALIZED == imuHandle->imuSyncState)
+    {
+        state = HAL_ImuSendSync(imuHandle);
+    }
+
+    OSA_EXIT_CRITICAL();
+    (void)state;
+    return kStatus_HAL_ImumcSuccess;
+}
+
+hal_imumc_status_t HAL_ImuDeinit(imu_link_t link, uint32_t flag)
+{
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+
+    assert(kIMU_LinkMax > link);
+    imuHandle = &imuHandleCh[link];
+    OSA_ENTER_CRITICAL();
+
+    if ((flag & (1U << 0U)) == 0U)
+    {
+        (void)HAL_ImuReturnAllTxBuf(link);
+        state = HAL_ImuSendShutdown(imuHandle);
+        if (kStatus_HAL_ImumcError == state)
+        {
+            OSA_EXIT_CRITICAL();
+            return kStatus_HAL_ImumcError;
+        }
+    }
+
+    IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+    IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK);
+    (void)os_InterruptMaskClear(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
+    IMU_Deinit((imu_link_t)imuHandle->imuLink);
+    imuHandle->imuSyncState                  = (uint8_t)IMU_UNINITIALIZED;
+    *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = 0;
+    imu_init_flag &= ~(1U << imuHandle->imuLink);
+    imuHandle->wlanTxqCtl.writeIndex         = 0;
+    imuHandle->wlanTxqCtl.readIndex          = 0;
+    imuHandle->imuMsgBufIdx                  = 0;
+    imuHandle->cmd_buffer                    = NULL;
+    imuHandle->cmd_buffer_available          = 0;
+    imuHandle->cmd_response_buffer_available = 0;
+
+    if ((flag & (1U << 0U)) == 0U)
+    {
+        while (*IMU_MSG_PEER_MAGIC_P((imu_link_t)imuHandle->imuLink) != 0)
+        {
+        }
+    }
+
+    if ((flag & (1U << 1U)) == 0U)
+    {
+        HAL_ImuTaskDeinit(imuHandle->imuLink);
+    }
+
+    OSA_EXIT_CRITICAL();
+    return kStatus_HAL_ImumcSuccess;
+}
+
+hal_imumc_status_t HAL_ImumcInit(hal_imumc_handle_t handle, hal_imumc_config_t *config)
+{
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    hal_imumc_state_t *imumcHandle;
+    hal_imu_handle_t *imuHandle;
+    uint32_t Events;
+    OSA_SR_ALLOC();
+
+    assert(HAL_IMUMC_HANDLE_SIZE >= sizeof(hal_imumc_state_t));
+    assert(NULL != handle);
+    assert(NULL != config);
+    assert((uint8_t)kIMU_LinkMax > config->imuLink);
+    imumcHandle = (hal_imumc_state_t *)handle;
+
+    OSA_ENTER_CRITICAL();
+
+    if (imumc_init_flag == 0U)
+    {
+        (void)OSA_EventCreate((osa_event_handle_t)imumcQFlagsRef, 1U);
+        imumc_init_flag = 1U;
+    }
+
+    state = HAL_ImuInit((imu_link_t)config->imuLink);
+    if (kStatus_HAL_ImumcError == state)
+    {
+        OSA_EXIT_CRITICAL();
+        return kStatus_HAL_ImumcError;
+    }
+
+    imumcHandle->imuLink        = config->imuLink;
+    imumcHandle->local_addr     = config->local_addr;
+    imumcHandle->remote_addr    = config->remote_addr;
+    imumcHandle->rx.callback    = config->callback;
+    imumcHandle->rx.param       = config->param;
+    imumcHandle->eptLinkIsReady = FALSE;
+    LIST_elemInit(&imumcHandle->eptLink);
+
+    if (NULL == HAL_ImumcCreateEndpoint(imumcHandle))
+    {
+        OSA_EXIT_CRITICAL();
+        return kStatus_HAL_ImumcError;
+    }
+
+    imuHandle = &imuHandleCh[imumcHandle->imuLink];
+
+    OSA_EXIT_CRITICAL();
+
+    while (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
+    {
+#if defined(USE_RTOS) && (USE_RTOS == 1)
+        OSA_TimeDelay(IMU_LINK_WAIT_DELAY_MS);
+#else
+        (void)HAL_ImuReceive(imumcHandle->imuLink);
+#endif
+    }
+
+    while (FALSE == imumcHandle->eptLinkIsReady)
+    {
+        OSA_ENTER_CRITICAL();
+
+        state = HAL_ImuSendImumcEptQuiry(imuHandle, imumcHandle->remote_addr);
+
+        OSA_EXIT_CRITICAL();
+
+#if defined(USE_RTOS) && (USE_RTOS == 1U)
+        (void)OSA_EventWait((osa_event_handle_t)imumcQFlagsRef, IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0,
+                            osaWaitForever_c, &Events);
+#else
+        while (TRUE) /* Wait for IMUMC_EVENT_ENDPOINT_QUERY_RSP */
+        {
+            (void)HAL_ImuReceive(imumcHandle->imuLink);
+            (void)OSA_EventWait((osa_event_handle_t)imumcQFlagsRef,
+                                IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0, osaWaitForever_c, &Events);
+            if (Events != 0U)
+            {
+                break;
+            }
+        }
+#endif
+    }
+
+    return state;
+}
+
+hal_imumc_status_t HAL_ImumcDeinit(hal_imumc_handle_t handle)
+{
+    hal_imumc_state_t *imumcHandle;
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+
+    assert(NULL != handle);
+    imumcHandle = (hal_imumc_state_t *)handle;
+    OSA_ENTER_CRITICAL();
+    state = HAL_ImumcDestroyEndpoint(imumcHandle);
+
+    OSA_EXIT_CRITICAL();
+
+    return state;
+}
+
+hal_imumc_status_t HAL_ImumcSend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length)
+{
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    hal_imumc_state_t *imumcHandle;
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+    uint8_t *imumc_tx_buf;
+    struct imumc_std_msg localImumc;
+
+    assert(HAL_IMUMC_HANDLE_SIZE >= sizeof(hal_imumc_state_t));
+    assert(NULL != handle);
+    assert(NULL != data);
+
+    imumcHandle = (hal_imumc_state_t *)handle;
+    imuHandle   = &imuHandleCh[imumcHandle->imuLink];
+
+    assert(kStatus_HAL_ImumcSuccess == HAL_ImuLinkIsUp(imuHandle->imuLink));
+    assert(imumcHandle->eptLinkIsReady == TRUE);
+
+    if (imumcHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
+    {
+        assert(IMUMC_TXQ23_BUFLENGTH >= length);
+    }
+    else
+    {
+        assert(IMUMC_TXQ13_BUFLENGTH >= length);
+    }
+
+    imumc_tx_buf = HAL_ImumcAllocTxBuffer(handle, length);
+
+    if (NULL == imumc_tx_buf)
+    {
+        return kStatus_HAL_ImumcError;
+    }
+    else
+    {
+        OSA_ENTER_CRITICAL();
+
+        // To be DMAed
+        (void)HAL_IMU_MEMCPY(imumc_tx_buf, data, length);
+        localImumc.hdr.src   = imumcHandle->local_addr;
+        localImumc.hdr.dst   = imumcHandle->remote_addr;
+        localImumc.hdr.len   = (uint16_t)length;
+        localImumc.hdr.flags = 0;
+        localImumc.data      = (uint32_t)imumc_tx_buf;
+
+        if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_IMUMC, 0U,
+                                                               (uint8_t *)&localImumc,
+                                                               (3U + sizeof(struct imumc_std_msg)) >> 2U))
+        {
+            seq_num++;
+        }
+        else
+        {
+            (void)HAL_ImumcPutTxBuf(imuHandle, imumc_tx_buf);
+            imumcStatus = kStatus_HAL_ImumcError;
+        }
+
+        OSA_EXIT_CRITICAL();
+    }
+
+    (void)state;
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImumcNoCopySend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length)
+{
+    hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
+    hal_imumc_state_t *imumcHandle;
+    hal_imu_handle_t *imuHandle;
+    hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
+    OSA_SR_ALLOC();
+
+    struct imumc_std_msg localImumc;
+
+    assert(HAL_IMUMC_HANDLE_SIZE >= sizeof(hal_imumc_state_t));
+    assert(NULL != handle);
+    assert(NULL != data);
+
+    imumcHandle = (hal_imumc_state_t *)handle;
+    imuHandle   = &imuHandleCh[imumcHandle->imuLink];
+
+    assert(kStatus_HAL_ImumcSuccess == HAL_ImuLinkIsUp(imuHandle->imuLink));
+    assert(imumcHandle->eptLinkIsReady == TRUE);
+
+    OSA_ENTER_CRITICAL();
+
+    localImumc.hdr.src   = imumcHandle->local_addr;
+    localImumc.hdr.dst   = imumcHandle->remote_addr;
+    localImumc.hdr.len   = (uint16_t)length;
+    localImumc.hdr.flags = 0;
+    localImumc.data      = (uint32_t)data;
+
+    if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_IMUMC, 0U,
+                                                           (uint8_t *)&localImumc,
+                                                           (3U + sizeof(struct imumc_std_msg)) >> 2U))
+    {
+        seq_num++;
+    }
+    else
+    {
+        imumcStatus = kStatus_HAL_ImumcError;
+    }
+
+    OSA_EXIT_CRITICAL();
+    (void)state;
+    return imumcStatus;
+}
+
+hal_imumc_status_t HAL_ImuInstallCallback(uint8_t imuLink, imu_callback_t callback, uint8_t type)
+{
+    hal_imu_handle_t *imuHandle;
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+    assert((uint8_t)IMU_MSG_MAX > type);
+    imuHandle                   = &imuHandleCh[imuLink];
+    imuHandle->imuHandler[type] = callback;
+
+    return kStatus_HAL_ImumcSuccess;
+}
+
+hal_imumc_status_t HAL_ImuInstallIrqCallback(uint8_t imuLink, imu_irq_callback_t callback)
+{
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+
+    imuIrqCallback[imuLink] = callback;
+
+    return kStatus_HAL_ImumcSuccess;
+}
+
+hal_imumc_status_t HAL_ImumcInstallRxCallback(hal_imumc_handle_t handle, imumc_rx_callback_t callback, void *param)
+{
+    hal_imumc_state_t *imumcHandle;
+
+    imumcHandle = (hal_imumc_state_t *)handle;
+
+    imumcHandle->rx.callback = callback;
+    imumcHandle->rx.param    = param;
+
+    return kStatus_HAL_ImumcSuccess;
+}
+
+hal_imumc_status_t HAL_ImumcEnterLowpower(hal_imumc_handle_t handle)
+{
+    return kStatus_HAL_ImumcError;
+}
+
+hal_imumc_status_t HAL_ImumcExitLowpower(hal_imumc_handle_t handle)
+{
+    return kStatus_HAL_ImumcError;
+}
+
+void HAL_ImumcSetEvent(uint32_t Event)
+{
+#if defined(CPU2)
+    (void)OSA_EventSet((osa_event_handle_t)ImuQFlagsRef, Event);
+#else
+    if ((Event & (1U << kIMU_LinkCpu1Cpu3)) != 0U)
+    {
+        (void)OSA_EventSet((osa_event_handle_t)ImuQ13FlagsRef, Event);
+    }
+    else
+    {
+        (void)OSA_EventSet((osa_event_handle_t)ImuQ23FlagsRef, Event);
+    }
+#endif
+}
+
+#if defined(CPU2)
+void CPU1_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)
+{
+    uint32_t irq_num = IMULINKID_TO_IRQID(kIMU_LinkCpu1Cpu2);
+
+    /* Mask IMU ICU interrupt */
+    (void)os_InterruptMaskClear(irq_num);
+
+    if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu1Cpu2))
+    {
+        HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu1Cpu2);
+    }
+    else
+    {
+        IMU_ClearPendingInterrupts(kIMU_LinkCpu1Cpu2, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+        (void)os_InterruptMaskSet(irq_num);
+    }
+}
+
+void CPU3_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)
+{
+    uint32_t irq_num = IMULINKID_TO_IRQID(kIMU_LinkCpu2Cpu3);
+
+    /* Mask IMU ICU interrupt */
+    (void)os_InterruptMaskClear(irq_num);
+
+    if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu2Cpu3))
+    {
+        HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu2Cpu3);
+    }
+    else
+    {
+        IMU_ClearPendingInterrupts(kIMU_LinkCpu2Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+        (void)os_InterruptMaskSet(irq_num);
+    }
+}
+#else
+
+void WL_MCI_WAKEUP0_DriverIRQHandler(void)
+{
+    IRQn_Type irq_num;
+#if defined(CPU2)
+    irq_num = IRQ_IMU_CPU32;
+#else
+    irq_num = IRQ_IMU_CPU13;
+#endif
+
+    /* Mask IMU ICU interrupt */
+    (void)os_InterruptMaskClear(irq_num);
+
+    if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu1Cpu3))
+    {
+        HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu1Cpu3);
+    }
+    else
+    {
+        IMU_ClearPendingInterrupts(kIMU_LinkCpu1Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+        (void)os_InterruptMaskSet(irq_num);
+    }
+}
+
+void BLE_MCI_WAKEUP0_DriverIRQHandler(void)
+{
+    IRQn_Type irq_num;
+#if defined(CPU2)
+    irq_num = IRQ_IMU_CPU12;
+#else
+    irq_num = IRQ_IMU_CPU23;
+#endif
+
+    /* Mask IMU ICU interrupt */
+    (void)os_InterruptMaskClear(irq_num);
+
+    if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu2Cpu3))
+    {
+        HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu2Cpu3);
+    }
+    else
+    {
+        if (imuIrqCallback[kIMU_LinkCpu2Cpu3] != NULL)
+        {
+            imuIrqCallback[kIMU_LinkCpu2Cpu3]();
+        }
+
+        IMU_ClearPendingInterrupts(kIMU_LinkCpu2Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
+        (void)os_InterruptMaskSet(irq_num);
+    }
+}
+#endif
+
+void *HAL_ImumcAllocTxBuffer(hal_imumc_handle_t handle, uint32_t size)
+{
+    hal_imumc_state_t *imumcHandle;
+    hal_imu_handle_t *imuHandle;
+    uint32_t retry = IMUMC_ALLOC_RETRY_COUNT;
+    void *buf      = NULL;
+
+    imumcHandle = (hal_imumc_state_t *)handle;
+
+    if (imumcHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
+    {
+        assert(IMUMC_TXQ23_BUFLENGTH >= size);
+    }
+    else
+    {
+        assert(IMUMC_TXQ13_BUFLENGTH >= size);
+    }
+
+    assert(NULL != handle);
+
+    imuHandle = &imuHandleCh[imumcHandle->imuLink];
+
+    buf = HAL_ImumcGetTxBuf(imuHandle);
+
+    while ((buf == NULL) && (retry != 0U))
+    {
+        /* Sleep current thread, then try to allocate again */
+        OSA_TimeDelay(IMUMC_ALLOC_FAILED_DELAY_MS);
+        buf = HAL_ImumcGetTxBuf(imuHandle);
+        retry--;
+    }
+
+    return buf;
+}
+
+hal_imumc_status_t HAL_ImumcFreeRxBuffer(hal_imumc_handle_t handle, uint8_t *data)
+{
+    hal_imumc_state_t *imumcHandle;
+    hal_imu_handle_t *imuHandle;
+
+    assert(NULL != handle);
+
+    imumcHandle = (hal_imumc_state_t *)handle;
+    imuHandle   = &imuHandleCh[imumcHandle->imuLink];
+
+    return HAL_ImuSendImumcFreeBuf(imuHandle, data);
+}
+
+bool HAL_ImuIsTxBufQueueEmpty(uint8_t imuLink)
+{
+    hal_imu_handle_t *imuHandle;
+    IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
+
+    assert((uint8_t)kIMU_LinkMax > imuLink);
+
+    imuHandle  = &imuHandleCh[imuLink];
+    wlanTxqCtl = &imuHandle->wlanTxqCtl;
+
+    return (IS_WLAN_TXBQ_EMPTY(wlanTxqCtl));
+}
+
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+hal_imumc_status_t HAL_ImuCreateTaskLock(void)
+{
+    osa_status_t status;
+
+    if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
+    {
+        status = OSA_MutexCreate((osa_mutex_handle_t)imu_task_lock);
+        if (status == KOSA_StatusError)
+        {
+            return kStatus_HAL_ImumcError;
+        }
+    }
+
+    return kStatus_HAL_ImumcSuccess;
+}
+
+void HAL_ImuDeleteTaskLock(void)
+{
+    if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) != 0)
+    {
+        (void)OSA_MutexDestroy((osa_mutex_handle_t)imu_task_lock);
+        (*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) = 0;
+    }
+}
+
+hal_imumc_status_t HAL_ImuGetTaskLock(void)
+{
+    osa_status_t status;
+
+    if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
+    {
+        return kStatus_HAL_ImumcSuccess;
+    }
+
+    status = OSA_MutexLock((osa_mutex_handle_t)imu_task_lock, osaWaitForever_c);
+    return status == KOSA_StatusSuccess ? kStatus_HAL_ImumcSuccess : kStatus_HAL_ImumcError;
+}
+
+hal_imumc_status_t HAL_ImuPutTaskLock(void)
+{
+    osa_status_t status;
+
+    if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
+    {
+        return kStatus_HAL_ImumcSuccess;
+    }
+
+    status = OSA_MutexUnlock((osa_mutex_handle_t)imu_task_lock);
+    return status == KOSA_StatusSuccess ? kStatus_HAL_ImumcSuccess : kStatus_HAL_ImumcError;
+
+}
+#endif
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu.h
new file mode 100644
index 0000000000..47d11d267c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu.h
@@ -0,0 +1,1102 @@
+/*
+ * Copyright 2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_ADAPTER_RFIMU_H__
+#define __FSL_ADAPTER_RFIMU_H__
+
+#include "fsl_adapter_imu_common.h"
+
+#if defined(SDK_OS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+/*!
+ * @addtogroup IMU_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief IMUMC Msaster/Remote role definition (0 - Master, 1 - Remote) */
+#ifndef HAL_IMUMC_SELECT_ROLE
+#define HAL_IMUMC_SELECT_ROLE (1U)
+#endif
+
+/*! @brief IMUMC handle size definition */
+#define HAL_IMUMC_HANDLE_SIZE (52U)
+
+#ifndef REMOTE_CORE_BOOT_ADDRESS
+#define REMOTE_CORE_BOOT_ADDRESS (0x01000000U)
+#endif
+
+#ifndef MAX_EP_COUNT
+#define MAX_EP_COUNT (5U)
+#endif
+
+#define IMUMC_WAITFOREVER (0xFFFFFFFFU)
+
+/*!
+ * @brief Defines the imumc handle
+ *
+ * This macro is used to define a 4 byte aligned imumc handle.
+ * Then use "(hal_imumc_handle_t)name" to get the imumc handle.
+ *
+ * The macro should be global and could be optional. You could also define imumc handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * IMUMC_HANDLE_DEFINE(imumcHandle);
+ * @endcode
+ *
+ * @param name The name string of the imumc handle.
+ */
+#define IMUMC_HANDLE_DEFINE(name) uint32_t name[((HAL_IMUMC_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+/*! @brief The handle of IMUMC adapter */
+typedef void *hal_imumc_handle_t;
+
+/*! @brief IMUMC status */
+typedef enum _hal_imumc_status
+{
+    kStatus_HAL_ImumcSuccess = 0U,
+    kStatus_HAL_ImumcError,
+    kStatus_HAL_ImumcRxBusy,
+    kStatus_HAL_ImumcTxBusy,
+    kStatus_HAL_ImumcTxIdle,
+    kStatus_HAL_ImumcRxIdle,
+    kStatus_HAL_ImumcTimeout,
+} hal_imumc_status_t;
+
+/*! @brief IMUMC return status */
+typedef enum _hal_imumc_return_status
+{
+    kStatus_HAL_RL_RELEASE = 0U,
+    kStatus_HAL_RL_HOLD,
+} hal_imumc_return_status_t;
+
+/*! @brief The callback function of IMUMC adapter.
+ *
+ * @note If Imumc RX callback function return kStatus_HAL_RL_RELEASE mode, no need to call HAL_ImumcFreeRxBuffer.
+ * @note If Imumc RX callback function return kStatus_HAL_RL_HOLD mode,then need to call HAL_ImumcFreeRxBuffer.
+ *
+ */
+typedef hal_imumc_return_status_t (*imumc_rx_callback_t)(void *param, uint8_t *data, uint32_t len);
+
+/*! @brief The configure structure of IMUMC adapter. */
+typedef struct _hal_imumc_config
+{
+    uint8_t local_addr;           /* Local address for rx */
+    uint8_t remote_addr;          /* Remote address for tx */
+    imumc_rx_callback_t callback; /* RPMGS Rx callback  */
+    void *param;                  /* RPMGS Rx callback parameter */
+    uint8_t imuLink;
+} hal_imumc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Initializes the IMUMC adapter module for dual core communication.
+ *
+ * @note This API should be called at the beginning of the application using the IMUMC adapter driver.
+ *
+ * @retval kStatus_HAL_ImumcSuccess IMUMC module initialize succeed.
+ */
+hal_imumc_status_t HAL_ImumcMcmgrInit(void);
+
+/*!
+ * @brief Initializes the IMUMC adapter for IMUMC channel configure.
+ *
+ * @note This API should be called to software IMUMC communication configure, and it be
+ * called whenever application need it.
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_IMUMC_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #IMUMC_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_IMUMC_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param config           Used for config local/remote endpoint addr.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC module initialize succeed.
+ */
+hal_imumc_status_t HAL_ImumcInit(hal_imumc_handle_t handle, hal_imumc_config_t *config);
+
+/*!
+ * @brief DeInitilizate the IMUMC adapter module.
+ *
+ * @note This API should be called when not using the IMUMC adapter driver anymore.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC module deinitialize succeed.
+ */
+hal_imumc_status_t HAL_ImumcDeinit(hal_imumc_handle_t handle);
+
+/*!
+ * @brief Send data to another IMUMC module with timeout.
+ *
+ * This function will send a specified length of data to another core by IMUMC.
+ *
+ * @note This API should be called to send data.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the send data from.
+ * @param length           The send data length.
+ * @param timeout          Timeout in ms, 0 if nonblocking, IMUMC_WAITFOREVER for wait for forever.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC send data succeed.
+ */
+hal_imumc_status_t HAL_ImumcSendTimeout(hal_imumc_handle_t handle, uint8_t *data, uint32_t length, uint32_t timeout);
+
+/*!
+ * @brief Send data to another IMUMC module.
+ *
+ * This function will send a specified length of data to another core by IMUMC.
+ *
+ * @note This API should be called to send data.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the send data from.
+ * @param length           The send data length.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC send data succeed.
+ */
+hal_imumc_status_t HAL_ImumcSend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Allocates the tx buffer for message payload with timeout.
+ *
+ * This API can only be called at process context to get the tx buffer in vring. By this way, the
+ * application can directly put its message into the vring tx buffer without copy from an application buffer.
+ * It is the application responsibility to correctly fill the allocated tx buffer by data and passing correct
+ * parameters to the imumc_lite_send_nocopy() function to perform data no-copy-send mechanism.
+ *
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param size             The send data length.
+ * @param timeout          Timeout in ms, 0 if nonblocking, IMUMC_WAITFOREVER for wait for forever.
+ * @retval The tx buffer address on success and RL_NULL on failure.
+ */
+void *HAL_ImumcAllocTxBufferTimeout(hal_imumc_handle_t handle, uint32_t size, uint32_t timeout);
+
+/*!
+ * @brief Allocates the tx buffer for message payload.
+ *
+ * This API can only be called at process context to get the tx buffer in vring. By this way, the
+ * application can directly put its message into the vring tx buffer without copy from an application buffer.
+ * It is the application responsibility to correctly fill the allocated tx buffer by data and passing correct
+ * parameters to the imumc_lite_send_nocopy() function to perform data no-copy-send mechanism.
+ *
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param size           The send data length.
+ * @retval The tx buffer address on success and RL_NULL on failure.
+ */
+void *HAL_ImumcAllocTxBuffer(hal_imumc_handle_t handle, uint32_t size);
+
+/*!
+ * @brief Send data with NoCopy to another IMUMC module.
+ *
+ * This function will send a specified length of data to another core by IMUMC.
+ * This function sends txbuf of length len to the remote dst address,
+ * and uses ept->addr as the source address.
+ * The application has to take the responsibility for:
+ *  1. tx buffer allocation (HAL_ImumcAllocTxBuffer())
+ *  2. filling the data to be sent into the pre-allocated tx buffer
+ *  3. not exceeding the buffer size when filling the data
+ *  4. data cache coherency
+ *
+ * After the HAL_ImumcNoCopySend() function is issued the tx buffer is no more owned
+ * by the sending task and must not be touched anymore unless the HAL_ImumcNoCopySend()
+ * function fails and returns an error.
+ *
+ * @note This API should be called to send data.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the send data from.
+ * @param length           The send data length.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC send data succeed.
+ */
+hal_imumc_status_t HAL_ImumcNoCopySend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Releases the rx buffer for future reuse in vring.
+ * This API can be called at process context when the
+ * message in rx buffer is processed.
+ *
+ * @note The HAL_ImumcFreeRxBuffer need be called only if Imumc RX callback function return kStatus_HAL_RL_HOLD mode.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the received data from perr.
+
+ *
+ * @return Status of function execution, RL_SUCCESS on success.
+ */
+hal_imumc_status_t HAL_ImumcFreeRxBuffer(hal_imumc_handle_t handle, uint8_t *data);
+
+/*!
+ * @brief Install IMUMC rx callback.
+ *
+ * @note The function must be called because imumc adapter just support asynchronous receive mode
+ *        should make sure the callback function is installed before the data received from peer soc,
+ *        and the rx callback function will be called when the rx process complete.
+ *
+ *
+ * @param handle    IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC install rx callback succeed.
+ */
+hal_imumc_status_t HAL_ImumcInstallRxCallback(hal_imumc_handle_t handle, imumc_rx_callback_t callback, void *param);
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess Successful operation.
+ * @retval kStatus_HAL_ImumcError An error occurred.
+ */
+hal_imumc_status_t HAL_ImumcEnterLowpower(hal_imumc_handle_t handle);
+
+/*!
+ * @brief Prepares to exit low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess Successful operation.
+ * @retval kStatus_HAL_ImumcError An error occurred.
+ */
+hal_imumc_status_t HAL_ImumcExitLowpower(hal_imumc_handle_t handle);
+
+#ifndef IMU_TASK_PRIORITY
+#if defined(__ZEPHYR__)
+#define IMU_TASK_PRIORITY (3U)
+#elif defined(CPU2)
+#define IMU_TASK_PRIORITY (2U)
+#else
+#define IMU_TASK_PRIORITY                                                                                       \
+    (6U) /* makesure the calculated priority of HAL_ImuMainCpu13 task is the same with tcp/ip task(priority 2), \
+            otherwise the throughput of udp rx will be very low */
+#endif
+#endif
+
+#ifndef IMU_TASK_STACK_SIZE
+#define IMU_TASK_STACK_SIZE (2048U)
+#endif
+
+#define IMU_MAX_MSG_CNT_LONG      (16U)
+#define IMU_MAX_MSG_CNT_SHORT     (2U)
+#define IMU_SYNC_MAGIC_PATTERN    (0xABCDEF89U)
+#define IMU_TXQ_BUFSIZE           (32U) /*! must be power of 2 */
+#define IMU_TXQ_BUFSIZE_THRESHOLD (8U)
+#define IMU_TXQ_ENTRY_MASK        (IMU_TXQ_BUFSIZE - 1U)
+#define IMU_EVENT_TRIGGERS        ((1U << kIMU_LinkMax) - 1U)
+/*! @brief IMU message payload size. */
+#define IMU_PAYLOAD_SIZE (8U)
+
+#define IMUMC_EVENT_ENDPOINT_QUERY_RSP (1U << 0U)
+
+#ifndef IMUMC_TXQ13_BUFSIZE
+#define IMUMC_TXQ13_BUFSIZE (8U)
+#endif
+
+#ifndef IMUMC_TXQ23_BUFSIZE
+#define IMUMC_TXQ23_BUFSIZE (16U)
+#endif
+
+#ifndef IMUMC_TXQ13_BUFLENGTH
+#define IMUMC_TXQ13_BUFLENGTH (512U)
+#endif
+
+#ifndef IMUMC_TXQ23_BUFLENGTH
+#define IMUMC_TXQ23_BUFLENGTH (264U)
+#endif
+
+#define IMUMC_TXQ13_ENTRY_MASK (IMUMC_TXQ13_BUFSIZE - 1U)
+#define IMUMC_TXQ23_ENTRY_MASK (IMUMC_TXQ23_BUFSIZE - 1U)
+
+#if defined(CONFIG_IMU_GDMA) && (CONFIG_IMU_GDMA == 1)
+#define IMU_GDMA_ENABLE (1U)
+
+#else
+
+#define IMU_GDMA_ENABLE (0U)
+#endif
+
+/*! @brief IMU initialization state. */
+enum imu_init_state_t
+{
+    IMU_UNINITIALIZED,
+    IMU_INITIALIZING,
+    IMU_INITIALIZED
+};
+
+/*! @brief IMUMC type. */
+typedef enum _imu_msg_type_t
+{
+    IMU_MSG_CONTROL,
+    IMU_MSG_COMMAND,
+    IMU_MSG_COMMAND_RESPONSE,
+    IMU_MSG_EVENT,
+    IMU_MSG_TX_DATA,
+    IMU_MSG_RX_DATA,
+    IMU_MSG_MULTI_TX_DATA,
+    IMU_MSG_MULTI_RX_DATA,
+    IMU_MSG_IMUMC,
+    IMU_MSG_MAX,
+    /* The header is 8 bits hence max types =255 */
+} imu_msg_type_t;
+
+/*! @brief IMUMC control message subtype. */
+typedef enum _imu_ctrl_msg_subtype_t
+{
+    IMU_MSG_CONTROL_DEFAULT,
+    IMU_MSG_CONTROL_SYNC,
+    IMU_MSG_CONTROL_SYNC_ACK,
+    IMU_MSG_CONTROL_ACK_FOR_UNLOCK,
+    IMU_MSG_CONTROL_ERROR,
+    IMU_MSG_CONTROL_SHUTDOWN,
+    IMU_MSG_CONTROL_CMD_BUF_ADDR,
+    IMU_MSG_CONTROL_EVT_ACK,
+    IMU_MSG_CONTROL_COMMAND_RSP_ACK,
+    IMU_MSG_CONTROL_TX_BUF_ADDR,
+    IMU_MSG_CONTROL_FREE_RX_BUF,
+    IMU_MSG_CONTROL_IMUMC_EPT_QUIRY,
+    IMU_MSG_CONTROL_IMUMC_EPT_QUIRY_RSP,
+    IMU_MSG_CONTROL_IMUMC_BUF_FREE,
+    IMU_MSG_CONTROL_EVT_DUMP,
+    IMU_MSG_CONTROL_MAX,
+    /* The header is 8 bits hence max types =255 */
+} imu_ctrl_msg_subtype_t;
+
+/*! @brief IMU message header structure. */
+typedef struct IMU_Hdr_t_
+{
+    volatile uint8_t type;
+    volatile uint8_t sub_type; // user of icc module needs to define own msg sub_types
+    volatile uint8_t seq_num;  // may be used by user of icc module for own purpose
+    volatile uint8_t length;   // length of Payload in bytes
+} IMU_Hdr_t;
+
+/*! @brief IMU message structure. */
+typedef struct IMU_Msg_t_
+{
+    IMU_Hdr_t Hdr;
+    volatile uint32_t PayloadPtr[IMU_PAYLOAD_SIZE];
+} IMU_Msg_t;
+
+/*! @brief IMU message wrapper 1. */
+typedef struct IMU_Msg_Wrapper_long_t_
+{
+    volatile uint32_t magic[2];
+    IMU_Msg_t msgQ[2][IMU_MAX_MSG_CNT_LONG];
+} IMU_Msg_Wrapper_long_t;
+
+/*! @brief IMU message wrapper 2. */
+typedef struct IMU_Msg_Wrapper_short_t_
+{
+    volatile uint32_t magic[2];
+    IMU_Msg_t msgQ[2][IMU_MAX_MSG_CNT_SHORT];
+} IMU_Msg_Wrapper_short_t;
+
+/* imumc_std_hdr contains a reserved field,
+ * this implementation of IMUMC uses this reserved
+ * field to hold the idx and totlen of the buffer
+ * not being returned to the vring in the receive
+ * callback function. This way, the no-copy API
+ * can use this field to return the buffer later.
+ */
+struct imumc_hdr_reserved
+{
+    uint16_t rfu; /* reserved for future usage */
+    uint16_t idx;
+};
+
+/*!
+ * Common header for all imumc messages.
+ * Every message sent/received on the imumc bus begins with this header.
+ */
+struct imumc_std_hdr
+{
+    uint32_t src;                       /*!< source endpoint address */
+    uint32_t dst;                       /*!< destination endpoint address */
+    struct imumc_hdr_reserved reserved; /*!< reserved for future use */
+    uint16_t len;                       /*!< length of payload (in bytes) */
+    uint16_t flags;                     /*!< message flags */
+};
+
+/*!
+ * Common message structure.
+ * Contains the header and the payload.
+ */
+struct imumc_std_msg
+{
+    struct imumc_std_hdr hdr; /*!< Imumc message header */
+    uint32_t data;            /*!< bytes of message payload data */
+};
+
+typedef hal_imumc_status_t (*imu_callback_t)(IMU_Msg_t *pImuMsg, uint32_t length);
+
+/*! @brief IMU interrupt callback */
+typedef void (*imu_irq_callback_t)(void);
+
+/*! @brief Checks whether a tx buffer queue is empty */
+#define IS_WLAN_TXBQ_EMPTY(q) ((q)->writeIndex == (q)->readIndex)
+
+/*! @brief Checks whether a tx buffer queue is full */
+#define IS_WLAN_TXBQ_FULL(q)                                                  \
+    ((((q)->writeIndex & (1UL << 31U)) != ((q)->readIndex & (1UL << 31U))) && \
+     (((q)->writeIndex & IMU_TXQ_ENTRY_MASK) == ((q)->readIndex & IMU_TXQ_ENTRY_MASK)))
+
+/*! @brief Increments write pointer*/
+#define INCR_WLAN_TXBQ_WR_INDEX(q, n)                                \
+    {                                                                \
+        unsigned int wrapBit = (q)->writeIndex & (1UL << 31U);       \
+        unsigned int val     = (q)->writeIndex & IMU_TXQ_ENTRY_MASK; \
+        unsigned int newVal  = (val + (n)) & IMU_TXQ_ENTRY_MASK;     \
+        if ((n) > 0U)                                                \
+        {                                                            \
+            if (newVal <= val)                                       \
+            {                                                        \
+                (q)->writeIndex = newVal | (wrapBit ^ (1UL << 31U)); \
+            }                                                        \
+            else                                                     \
+            {                                                        \
+                (q)->writeIndex = newVal | wrapBit;                  \
+            }                                                        \
+        }                                                            \
+    }
+
+/*! @brief Increments read pointer */
+#define INCR_WLAN_TXBQ_RD_INDEX(q, n)                               \
+    {                                                               \
+        unsigned int wrapBit = (q)->readIndex & (1UL << 31U);       \
+        unsigned int val     = (q)->readIndex & IMU_TXQ_ENTRY_MASK; \
+        unsigned int newVal  = (val + (n)) & IMU_TXQ_ENTRY_MASK;    \
+        if ((n) > 0U)                                               \
+        {                                                           \
+            if (newVal <= val)                                      \
+            {                                                       \
+                (q)->readIndex = newVal | (wrapBit ^ (1UL << 31U)); \
+            }                                                       \
+            else                                                    \
+            {                                                       \
+                (q)->readIndex = newVal | wrapBit;                  \
+            }                                                       \
+        }                                                           \
+    }
+
+/*! @brief Checks whether a tx buffer queue is empty */
+#define IS_IMUMC_TXBQ13_EMPTY(q) ((q)->writeIndex == (q)->readIndex)
+#define IS_IMUMC_TXBQ23_EMPTY(q) ((q)->writeIndex == (q)->readIndex)
+
+/*! @brief Checks whether a tx buffer queue is full */
+#define IS_IMUMC_TXBQ13_FULL(q)                                               \
+    ((((q)->writeIndex & (1UL << 31U)) != ((q)->readIndex & (1UL << 31U))) && \
+     (((q)->writeIndex & IMUMC_TXQ13_ENTRY_MASK) == ((q)->readIndex & IMUMC_TXQ13_ENTRY_MASK)))
+#define IS_IMUMC_TXBQ23_FULL(q)                                               \
+    ((((q)->writeIndex & (1UL << 31U)) != ((q)->readIndex & (1UL << 31U))) && \
+     (((q)->writeIndex & IMUMC_TXQ23_ENTRY_MASK) == ((q)->readIndex & IMUMC_TXQ23_ENTRY_MASK)))
+
+/*! @brief Increments write pointer*/
+#define INCR_IMUMC_TXBQ13_WR_INDEX(q, n)                                 \
+    {                                                                    \
+        unsigned int wrapBit = (q)->writeIndex & (1UL << 31U);           \
+        unsigned int val     = (q)->writeIndex & IMUMC_TXQ13_ENTRY_MASK; \
+        unsigned int newVal  = (val + (n)) & IMUMC_TXQ13_ENTRY_MASK;     \
+        if ((n) > 0U)                                                    \
+        {                                                                \
+            if (newVal <= val)                                           \
+            {                                                            \
+                (q)->writeIndex = newVal | (wrapBit ^ (1UL << 31U));     \
+            }                                                            \
+            else                                                         \
+            {                                                            \
+                (q)->writeIndex = newVal | wrapBit;                      \
+            }                                                            \
+        }                                                                \
+    }
+
+#define INCR_IMUMC_TXBQ23_WR_INDEX(q, n)                                 \
+    {                                                                    \
+        unsigned int wrapBit = (q)->writeIndex & (1UL << 31U);           \
+        unsigned int val     = (q)->writeIndex & IMUMC_TXQ23_ENTRY_MASK; \
+        unsigned int newVal  = (val + (n)) & IMUMC_TXQ23_ENTRY_MASK;     \
+        if ((n) > 0U)                                                    \
+        {                                                                \
+            if (newVal <= val)                                           \
+            {                                                            \
+                (q)->writeIndex = newVal | (wrapBit ^ (1UL << 31U));     \
+            }                                                            \
+            else                                                         \
+            {                                                            \
+                (q)->writeIndex = newVal | wrapBit;                      \
+            }                                                            \
+        }                                                                \
+    }
+
+/*! @brief Increments read pointer */
+#define INCR_IMUMC_TXBQ13_RD_INDEX(q, n)                                \
+    {                                                                   \
+        unsigned int wrapBit = (q)->readIndex & (1UL << 31U);           \
+        unsigned int val     = (q)->readIndex & IMUMC_TXQ13_ENTRY_MASK; \
+        unsigned int newVal  = (val + (n)) & IMUMC_TXQ13_ENTRY_MASK;    \
+        if ((n) > 0U)                                                   \
+        {                                                               \
+            if (newVal <= val)                                          \
+            {                                                           \
+                (q)->readIndex = newVal | (wrapBit ^ (1UL << 31U));     \
+            }                                                           \
+            else                                                        \
+            {                                                           \
+                (q)->readIndex = newVal | wrapBit;                      \
+            }                                                           \
+        }                                                               \
+    }
+
+#define INCR_IMUMC_TXBQ23_RD_INDEX(q, n)                                \
+    {                                                                   \
+        unsigned int wrapBit = (q)->readIndex & (1UL << 31U);           \
+        unsigned int val     = (q)->readIndex & IMUMC_TXQ23_ENTRY_MASK; \
+        unsigned int newVal  = (val + (n)) & IMUMC_TXQ23_ENTRY_MASK;    \
+        if ((n) > 0U)                                                   \
+        {                                                               \
+            if (newVal <= val)                                          \
+            {                                                           \
+                (q)->readIndex = newVal | (wrapBit ^ (1UL << 31U));     \
+            }                                                           \
+            else                                                        \
+            {                                                           \
+                (q)->readIndex = newVal | wrapBit;                      \
+            }                                                           \
+        }                                                               \
+    }
+
+typedef struct _hal_imumc_rx_state
+{
+    imumc_rx_callback_t callback;
+    void *param;
+} hal_imumc_rx_state_t;
+
+/*! @brief imumc state structure. */
+typedef struct _hal_imumc_state
+{
+    LIST_ELEM_st eptLink;
+    uint32_t local_addr;
+    uint32_t remote_addr;
+    uint8_t imuLink;
+    bool eptLinkIsReady;
+    hal_imumc_rx_state_t rx;
+} hal_imumc_state_t;
+
+/*! @brief imumc ept buf structure. */
+typedef struct _hal_imumc_ept_uf
+{
+    LIST_ELEM_st eptLink;
+    uint32_t addr;
+} hal_imumc_ept_buf_t;
+
+/*! @brief IMU WLAN Tx buffer control structure */
+typedef struct IMU_WLAN_TXQ_CTRL_st
+{
+    uint32_t writeIndex;
+    uint32_t readIndex;
+    uint32_t txBufQue[IMU_TXQ_BUFSIZE];
+} IMU_WLAN_TXQ_CTRL_st;
+
+/*! @brief IMUMC Tx buffer control structure */
+typedef struct IMUMC_TXQ_CTRL_st
+{
+    uint32_t writeIndex;
+    uint32_t readIndex;
+    uint32_t txBufQue[IMUMC_TXQ23_BUFSIZE];
+} IMUMC_TXQ_CTRL_st;
+
+/*! @brief imu handle structure. */
+typedef struct _hal_imu_handle_t
+{
+    /*! Word 0 */
+    uint8_t imuLink;
+    uint8_t imuSyncState; /*！ 0：Link Off, 1:Link Ongoing, 2: Link Up */
+    uint8_t freeTxMportBufCnt;
+    uint8_t imuMsgBufIdx;
+    /*! Word 1 */
+    bool cmd_buffer_available;
+    bool cmd_response_buffer_available;
+    bool rsvdbool1;
+    bool rsvdbool2;
+    /*! Word 2 */
+    uint32_t *cmd_buffer;
+    /*! Word 3 */
+    IMU_WLAN_TXQ_CTRL_st wlanTxqCtl;
+    /*! Word 37 */
+    uint32_t imuMsgBuf[IMU_PAYLOAD_SIZE];
+    /*! Word 45 */
+    LIST_ELEM_st eptList;
+    /*! Word 47 */
+    IMUMC_TXQ_CTRL_st imumcTxqCtl;
+    /*! Word 57 */
+    imu_callback_t imuHandler[IMU_MSG_MAX];
+} hal_imu_handle_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Add wlan Tx packet for sending multiple Tx packets within one message.
+ *
+ * This function is used to add a wlan Tx packet for IMU_MSG_MULTI_TX_DATA.
+ *
+ * @param imuLink           IMU link ID.
+ * @param txBuf             Tx buffer to be sent.
+ * @param length            Length of Tx data.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuAddWlanTxPacket(uint8_t imuLink, uint8_t *txBuf, uint32_t length);
+
+/*!
+ * @brief Add wlan Tx packet for sending multiple Tx packets within one message.
+ *
+ * This function is used to add a wlan Tx packet with callback function for IMU_MSG_MULTI_TX_DATA.
+ *
+ * @param imuLink           IMU link ID.
+ * @param txBuf             Tx buffer to be sent.
+ * @param length            Length of Tx data.
+ * @param cb                Callback function to add packet.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuAddWlanTxPacketExt(uint8_t imuLink,
+                                             uint8_t *txBuf,
+                                             uint32_t length,
+                                             void (*cb)(void *destAddr, void *srcAddr, uint32_t len));
+
+/*!
+ * @brief Install wlan callback.
+ *
+ * This function is used to imstall wlan callback
+ *
+ * @param imuLink        IMU link ID.
+ * @param callback       Callback to be installed.
+ * @param type           Callback type.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuInstallCallback(uint8_t imuLink, imu_callback_t callback, uint8_t type);
+
+/*!
+ * @brief Install imu interrupt callback.
+ *
+ * This function is used to install imu interrupt callback
+ *
+ * @param imuLink        IMU link ID.
+ * @param callback       Callback to be installed.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuInstallIrqCallback(uint8_t imuLink, imu_irq_callback_t callback);
+
+/*!
+ * @brief Send wlan command packet.
+ *
+ * This function is used to send wlan command packet
+ *
+ * @param imuLink        IMU link ID.
+ * @param cmdBuf         Command buffer to be sent.
+ * @param length         Length of command data.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuSendCommand(uint8_t imuLink, uint8_t *cmdBuf, uint32_t length);
+
+/*!
+ * @brief Add wlan Tx packet for sending one Tx packet within one message.
+ *
+ * This function is used to send a wlan Tx packet.
+ *
+ * @param imuLink           IMU link ID.
+ * @param txBuf             Tx buffer to be sent.
+ * @param length            Length of Tx data.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuSendTxData(uint8_t imuLink, uint8_t *txBuf, uint32_t length);
+
+/*!
+ * @brief Send multiple Tx packets within one message.
+ *
+ * This function is used to send multiple wlan Tx packets within one IMU message,
+ * which have been added by HAL_ImuAddWlanTxPacket already.
+ *
+ * @param imuLink           IMU link ID.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuSendMultiTxData(uint8_t imuLink);
+
+/*!
+ * @brief Check if IMU link is up.
+ *
+ * This function is used to check if IMU link is up.
+ *
+ * @param imuLink        IMU link ID.
+ * @retval kStatus_HAL_ImumcSuccess for IMU link up or kStatus_HAL_ImumcError for IMU link not up.
+ */
+hal_imumc_status_t HAL_ImuLinkIsUp(uint8_t imuLink);
+
+/*!
+ * @brief Start IMU link
+ *
+ * This function is used to start specified IMU link.
+ *
+ * @param imuLink        IMU link ID.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuInit(imu_link_t link);
+
+/*!
+ * @brief Stop IMU link
+ *
+ * This function is used to stop specified IMU link.
+ *
+ * @param imuLink        IMU link ID.
+ * @param flag           flag with bits to control.
+ *        flag bit0: control if need send imu msg to fw (imu tx return /imu shutdown)
+ *        flag bit1: control if need destroy ImuTask and ImuQFlagsRef
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuDeinit(imu_link_t link, uint32_t flag);
+
+/*!
+ * @brief Return all tx buffer.
+ *
+ * This function is used to return all tx buffer to CPU1.
+ *
+ * @param imuLink              IMU link ID.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuReturnAllTxBuf(imu_link_t link);
+
+/*!
+ * @brief Receive IMU message.
+ *
+ * This function is used to receive and process IMU message
+ *
+ * @param imuLink              IMU link ID.
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuReceive(uint8_t imuLink);
+
+/*!
+ * @brief Check if tx buffer queue empty.
+ *
+ * This function is used to check if tx buffer queue empty
+ *
+ * @param imuLink              IMU link ID.
+ * @retval TRUE or FALSE.
+ */
+bool HAL_ImuIsTxBufQueueEmpty(uint8_t imuLink);
+
+#if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
+/*!
+ * @brief Copy data by GDMA.
+ *
+ * This function is used to copy data by GDMA between shared memory and local memory.
+ *
+ * @param destAddr          Source address of data.
+ * @param srcAddr           Destination address of data.
+ * @param len               Data Length.
+ */
+void HAL_ImuGdmaCopyData(void *destAddr, void *srcAddr, uint32_t len);
+
+/*! @}*/
+#endif
+
+#ifdef CONFIG_FW_DUMP_EVENT
+/*!
+ * @brief Send fw dump event ack.
+ *
+ * This function is used to Send fw dump event ack to fw, When the event data process is completed.
+ *
+ * @param imuLink              IMU link ID.
+ * @param rxBuf                Rx buffer to be sent.
+ * @param length               Length of Rx buffer
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuSendEventDumpAck(imu_link_t link, uint8_t *rxBuf, uint8_t length);
+#endif
+
+/*!
+ * @brief Create imu task mutex.
+ *
+ * This function creates a imu task mutex.
+ *
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuCreateTaskLock(void);
+
+/*!
+ * @brief Delete imu task mutex.
+ *
+ * This function deletes the imu task mutex.
+ */
+void HAL_ImuDeleteTaskLock(void);
+
+/*!
+ * @brief Acquire imu task mutex.
+ *
+ * This function acquires the imu task mutex. Only one thread can acquire the mutex at any
+ * given time.
+ *
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuGetTaskLock(void);
+
+/*!
+ * @brief Release imu task mutex.
+ *
+ * This function releases the imu task mutex.
+ *
+ * @retval kStatus_HAL_ImumcSuccess or kStatus_HAL_ImumcError.
+ */
+hal_imumc_status_t HAL_ImuPutTaskLock(void);
+
+/*!
+ * @brief Reset imu readIndex and writeIndex to 0.
+ *
+ * This function reset the imu txq.
+ */
+void HAL_ImuResetWlanTxq(uint8_t imuLink);
+
+
+
+/*!
+ * @addtogroup IMUMC_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief IMUMC Msaster/Remote role definition (0 - Master, 1 - Remote) */
+#ifndef HAL_IMUMC_SELECT_ROLE
+#define HAL_IMUMC_SELECT_ROLE (1U)
+#endif
+
+/*! @brief IMUMC handle size definition */
+#define HAL_IMUMC_HANDLE_SIZE (52U)
+
+#ifndef REMOTE_CORE_BOOT_ADDRESS
+#define REMOTE_CORE_BOOT_ADDRESS (0x01000000U)
+#endif
+
+#ifndef MAX_EP_COUNT
+#define MAX_EP_COUNT (5U)
+#endif
+
+#define IMUMC_WAITFOREVER (0xFFFFFFFFU)
+
+/*!
+ * @brief Defines the imumc handle
+ *
+ * This macro is used to define a 4 byte aligned imumc handle.
+ * Then use "(hal_imumc_handle_t)name" to get the imumc handle.
+ *
+ * The macro should be global and could be optional. You could also define imumc handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * IMUMC_HANDLE_DEFINE(imumcHandle);
+ * @endcode
+ *
+ * @param name The name string of the imumc handle.
+ */
+#define IMUMC_HANDLE_DEFINE(name) uint32_t name[((HAL_IMUMC_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+/*!
+ * @brief Initializes the IMUMC adapter module for dual core communication.
+ *
+ * @note This API should be called at the beginning of the application using the IMUMC adapter driver.
+ *
+ * @retval kStatus_HAL_ImumcSuccess IMUMC module initialize succeed.
+ */
+hal_imumc_status_t HAL_ImumcMcmgrInit(void);
+
+/*!
+ * @brief Initializes the IMUMC adapter for IMUMC channel configure.
+ *
+ * @note This API should be called to software IMUMC communication configure, and it be
+ * called whenever application need it.
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_IMUMC_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #IMUMC_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_IMUMC_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param config           Used for config local/remote endpoint addr.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC module initialize succeed.
+ */
+hal_imumc_status_t HAL_ImumcInit(hal_imumc_handle_t handle, hal_imumc_config_t *config);
+
+/*!
+ * @brief DeInitilizate the IMUMC adapter module.
+ *
+ * @note This API should be called when not using the IMUMC adapter driver anymore.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC module deinitialize succeed.
+ */
+hal_imumc_status_t HAL_ImumcDeinit(hal_imumc_handle_t handle);
+
+/*!
+ * @brief Send data to another IMUMC module with timeout.
+ *
+ * This function will send a specified length of data to another core by IMUMC.
+ *
+ * @note This API should be called to send data.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the send data from.
+ * @param length           The send data length.
+ * @param timeout          Timeout in ms, 0 if nonblocking, IMUMC_WAITFOREVER for wait for forever.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC send data succeed.
+ */
+hal_imumc_status_t HAL_ImumcSendTimeout(hal_imumc_handle_t handle, uint8_t *data, uint32_t length, uint32_t timeout);
+
+/*!
+ * @brief Send data to another IMUMC module.
+ *
+ * This function will send a specified length of data to another core by IMUMC.
+ *
+ * @note This API should be called to send data.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the send data from.
+ * @param length           The send data length.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC send data succeed.
+ */
+hal_imumc_status_t HAL_ImumcSend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Allocates the tx buffer for message payload with timeout.
+ *
+ * This API can only be called at process context to get the tx buffer in vring. By this way, the
+ * application can directly put its message into the vring tx buffer without copy from an application buffer.
+ * It is the application responsibility to correctly fill the allocated tx buffer by data and passing correct
+ * parameters to the imumc_lite_send_nocopy() function to perform data no-copy-send mechanism.
+ *
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param size             The send data length.
+ * @param timeout          Timeout in ms, 0 if nonblocking, IMUMC_WAITFOREVER for wait for forever.
+ * @retval The tx buffer address on success and RL_NULL on failure.
+ */
+void *HAL_ImumcAllocTxBufferTimeout(hal_imumc_handle_t handle, uint32_t size, uint32_t timeout);
+
+/*!
+ * @brief Allocates the tx buffer for message payload.
+ *
+ * This API can only be called at process context to get the tx buffer in vring. By this way, the
+ * application can directly put its message into the vring tx buffer without copy from an application buffer.
+ * It is the application responsibility to correctly fill the allocated tx buffer by data and passing correct
+ * parameters to the imumc_lite_send_nocopy() function to perform data no-copy-send mechanism.
+ *
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param size           The send data length.
+ * @retval The tx buffer address on success and RL_NULL on failure.
+ */
+void *HAL_ImumcAllocTxBuffer(hal_imumc_handle_t handle, uint32_t size);
+
+/*!
+ * @brief Send data with NoCopy to another IMUMC module.
+ *
+ * This function will send a specified length of data to another core by IMUMC.
+ * This function sends txbuf of length len to the remote dst address,
+ * and uses ept->addr as the source address.
+ * The application has to take the responsibility for:
+ *  1. tx buffer allocation (HAL_ImumcAllocTxBuffer())
+ *  2. filling the data to be sent into the pre-allocated tx buffer
+ *  3. not exceeding the buffer size when filling the data
+ *  4. data cache coherency
+ *
+ * After the HAL_ImumcNoCopySend() function is issued the tx buffer is no more owned
+ * by the sending task and must not be touched anymore unless the HAL_ImumcNoCopySend()
+ * function fails and returns an error.
+ *
+ * @note This API should be called to send data.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the send data from.
+ * @param length           The send data length.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC send data succeed.
+ */
+hal_imumc_status_t HAL_ImumcNoCopySend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Releases the rx buffer for future reuse in vring.
+ * This API can be called at process context when the
+ * message in rx buffer is processed.
+ *
+ * @note The HAL_ImumcFreeRxBuffer need be called only if Imumc RX callback function return kStatus_HAL_RL_HOLD mode.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @param data             Pointer to where the received data from perr.
+
+ *
+ * @return Status of function execution, RL_SUCCESS on success.
+ */
+hal_imumc_status_t HAL_ImumcFreeRxBuffer(hal_imumc_handle_t handle, uint8_t *data);
+
+/*!
+ * @brief Install IMUMC rx callback.
+ *
+ * @note The function must be called because imumc adapter just support asynchronous receive mode
+ *        should make sure the callback function is installed before the data received from peer soc,
+ *        and the rx callback function will be called when the rx process complete.
+ *
+ *
+ * @param handle    IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess IMUMC install rx callback succeed.
+ */
+hal_imumc_status_t HAL_ImumcInstallRxCallback(hal_imumc_handle_t handle, imumc_rx_callback_t callback, void *param);
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess Successful operation.
+ * @retval kStatus_HAL_ImumcError An error occurred.
+ */
+hal_imumc_status_t HAL_ImumcEnterLowpower(hal_imumc_handle_t handle);
+
+/*!
+ * @brief Prepares to exit low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param handle           IMUMC handle pointer.
+ * @retval kStatus_HAL_ImumcSuccess Successful operation.
+ * @retval kStatus_HAL_ImumcError An error occurred.
+ */
+hal_imumc_status_t HAL_ImumcExitLowpower(hal_imumc_handle_t handle);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __FSL_ADAPTER_RFIMU_H__ */
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu_common.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu_common.h
new file mode 100644
index 0000000000..51a3d27aa6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/imu_adapter/fsl_adapter_imu_common.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_ADAPTER_RFCOMMON_H__
+#define __FSL_ADAPTER_RFCOMMON_H__
+
+#include "fsl_os_abstraction.h"
+#include "fsl_imu.h"
+#include "assert.h"
+#if defined(CPU2)
+#include "core_cm3.h"
+#endif
+
+/*! @brief TRUE/FALSE definition. */
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+/*******************************************************************************
+ * List Definitions and APIs
+ ******************************************************************************/
+/**
+ * @brief Macro to iterate over a list using a user specified loop cursor.
+ *
+ * @param cur   the variable used for cursor, representing the current list node.
+ * @param list  the head for your list.
+ */
+#define list_for_each(cur, list) for ((cur) = (list)->next; (cur) != (list); (cur) = (cur)->next)
+
+/**
+ * @brief An element in a doubly-linked circular list.
+ *  A list is a doubly-linked circular list.
+ */
+typedef struct LIST_ELEM_st
+{
+    struct LIST_ELEM_st *next;
+    struct LIST_ELEM_st *prev;
+} LIST_ELEM_st;
+
+/**
+ *  @brief Initializes a list, as an empty list.
+ *  @param list The list descriptor, i.e. the fake list element that identifies a given list.
+ */
+static inline void LIST_init(LIST_ELEM_st *list)
+{
+    list->next = list;
+    list->prev = list;
+}
+
+/**
+ *  @brief Initializes an element, as an element not yet bound within a list.
+ *  @param elem The element to Initialize.
+ */
+static inline void LIST_elemInit(LIST_ELEM_st *elem)
+{
+    elem->next = NULL;
+    elem->prev = NULL;
+}
+
+/**
+ *  @brief  Inserts a new element in a list before a given existing element.
+ *  @param  list    The list descriptor, i.e. the fake list element that identifies a given list.
+ *  @param  elem    The new element is placed before this element.
+ *  @param  newElem New element to insert in the list.
+ */
+static inline void LIST_insertBefore(LIST_ELEM_st *list, LIST_ELEM_st *elem, LIST_ELEM_st *newElem)
+{
+    assert(newElem != list);
+
+    (void)list;
+
+    (elem->prev)->next = newElem;
+    newElem->next      = elem;
+    newElem->prev      = elem->prev;
+    elem->prev         = newElem;
+}
+
+/**
+ *  @brief  Adds an element in a list at the tail of that list.
+ *  @param  list The list descriptor, i.e. the fake list element that identifies a given list.
+ *  @param  elem New element to insert in the list.
+ */
+static inline void LIST_addTail(LIST_ELEM_st *list, LIST_ELEM_st *elem)
+{
+    LIST_insertBefore(list, list, elem);
+}
+
+/**
+ *  @brief  Removes an element from a list.
+ *  @param  list The list descriptor, i.e. the fake list element that identifies a given list.
+ *  @param  elem The element to remove.
+ */
+static inline void LIST_remove(LIST_ELEM_st *list, LIST_ELEM_st *elem)
+{
+    assert(elem != list);
+
+    (void)list;
+
+    if ((elem->next == NULL) || (elem->prev == NULL))
+    {
+        return;
+    }
+    (elem->prev)->next = elem->next;
+    (elem->next)->prev = elem->prev;
+
+    elem->next = NULL; // to indicate this is not linked yet
+    elem->prev = NULL;
+}
+
+/*!
+ * @addtogroup IMU_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+   IRQ index should come from board level definition.
+   Remove following definition after IMUMC code integration.
+*/
+#if defined(CPU2)
+#define IRQ_IMU_CPU12 CPU1_TO_CPU2_MSG_RDY_IMU_INT_IRQn
+#define IRQ_IMU_CPU32 CPU3_TO_CPU2_MSG_RDY_IMU_INT_IRQn
+#else
+#define IRQ_IMU_CPU13 WL_MCI_WAKEUP0_IRQn
+#define IRQ_IMU_CPU23 BLE_MCI_WAKEUP0_IRQn
+#endif
+
+#if defined(CPU2)
+#define IMU_MSG_SND_Q(imuLinkId) (((imuLinkId) == kIMU_LinkCpu1Cpu2) ? imuMsgQ12->msgQ[1] : imuMsgQ23->msgQ[0])
+#define IMU_MSG_CUR_MAGIC_P(imuLinkId) \
+    (((imuLinkId) == kIMU_LinkCpu1Cpu2) ? (&imuMsgQ12->magic[1]) : (&imuMsgQ23->magic[0]))
+#define IMU_MSG_PEER_MAGIC_P(imuLinkId) \
+    (((imuLinkId) == kIMU_LinkCpu1Cpu2) ? (&imuMsgQ12->magic[0]) : (&imuMsgQ23->magic[1]))
+#define IRQID_TO_IMULINKID(irqId)     (((irqId) == IRQ_IMU_CPU12) ? kIMU_LinkCpu1Cpu2 : kIMU_LinkCpu2Cpu3)
+#define IMULINKID_TO_IRQID(imuLinkId) (((imuLinkId) == kIMU_LinkCpu1Cpu2) ? IRQ_IMU_CPU12 : IRQ_IMU_CPU32)
+#else
+#define IMU_MSG_SND_Q(imuLinkId) (((imuLinkId) == kIMU_LinkCpu1Cpu3) ? imuMsgQ13->msgQ[1] : imuMsgQ23->msgQ[1])
+#define IMU_MSG_CUR_MAGIC_P(imuLinkId) \
+    (((imuLinkId) == kIMU_LinkCpu1Cpu3) ? (&imuMsgQ13->magic[1]) : (&imuMsgQ23->magic[1]))
+#define IMU_MSG_PEER_MAGIC_P(imuLinkId) \
+    (((imuLinkId) == kIMU_LinkCpu1Cpu3) ? (&imuMsgQ13->magic[0]) : (&imuMsgQ23->magic[0]))
+#define IRQID_TO_IMULINKID(irqId)     (((irqId) == IRQ_IMU_CPU13) ? kIMU_LinkCpu1Cpu3 : kIMU_LinkCpu2Cpu3)
+#define IMULINKID_TO_IRQID(imuLinkId) (((imuLinkId) == kIMU_LinkCpu1Cpu3) ? IRQ_IMU_CPU13 : IRQ_IMU_CPU23)
+#endif
+#endif /* __FSL_ADAPTER_RFCOMMON_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/lists/fsl_component_generic_list.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/lists/fsl_component_generic_list.c
new file mode 100644
index 0000000000..81fedac9f6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/lists/fsl_component_generic_list.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright 2018-2019, 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_component_generic_list.h"
+
+#if defined(OSA_USED)
+#include "fsl_os_abstraction.h"
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+#define LIST_ENTER_CRITICAL() \
+    OSA_SR_ALLOC();           \
+    OSA_ENTER_CRITICAL()
+#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL()
+#else
+#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
+#define LIST_EXIT_CRITICAL()  EnableGlobalIRQ(regPrimask);
+#endif
+#else
+#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
+#define LIST_EXIT_CRITICAL()  EnableGlobalIRQ(regPrimask);
+#endif
+
+static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement)
+{
+    list_status_t listStatus = kLIST_Ok;
+#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
+    list_element_handle_t element = list->head;
+#endif
+    if ((list->max != 0U) && (list->max == list->size))
+    {
+        listStatus = kLIST_Full; /*List is full*/
+    }
+#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
+    else
+    {
+        while (element != NULL) /*Scan list*/
+        {
+            /* Determine if element is duplicated */
+            if (element == newElement)
+            {
+                listStatus = kLIST_DuplicateError;
+                break;
+            }
+            element = element->next;
+        }
+    }
+#endif
+    return listStatus;
+}
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*! *********************************************************************************
+ * \brief     Initializes the list descriptor.
+ *
+ * \param[in] list - LIST_ handle to init.
+ *            max - Maximum number of elements in list. 0 for unlimited.
+ *
+ * \return void.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+void LIST_Init(list_handle_t list, uint32_t max)
+{
+    list->head = NULL;
+    list->tail = NULL;
+    list->max  = max;
+    list->size = 0;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the list that contains the given element.
+ *
+ * \param[in] element - Handle of the element.
+ *
+ * \return NULL if element is orphan.
+ *         Handle of the list the element is inserted into.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_handle_t LIST_GetList(list_element_handle_t listElement)
+{
+    return listElement->list;
+}
+
+/*! *********************************************************************************
+ * \brief     Links element to the tail of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ *            element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement)
+{
+    LIST_ENTER_CRITICAL();
+    list_status_t listStatus = kLIST_Ok;
+
+    listStatus = LIST_Error_Check(list, listElement);
+    if (listStatus == kLIST_Ok) /* Avoiding list status error */
+    {
+        if (list->size == 0U)
+        {
+            list->head = listElement;
+        }
+        else
+        {
+            list->tail->next = listElement;
+        }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+        listElement->prev = list->tail;
+#endif
+        listElement->list = list;
+        listElement->next = NULL;
+        list->tail        = listElement;
+        list->size++;
+    }
+
+    LIST_EXIT_CRITICAL();
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Links element to the head of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ *            element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement)
+{
+    LIST_ENTER_CRITICAL();
+    list_status_t listStatus = kLIST_Ok;
+
+    listStatus = LIST_Error_Check(list, listElement);
+    if (listStatus == kLIST_Ok) /* Avoiding list status error */
+    {
+        /* Links element to the head of the list */
+        if (list->size == 0U)
+        {
+            list->tail = listElement;
+        }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+        else
+        {
+            list->head->prev = listElement;
+        }
+        listElement->prev = NULL;
+#endif
+        listElement->list = list;
+        listElement->next = list->head;
+        list->head        = listElement;
+        list->size++;
+    }
+
+    LIST_EXIT_CRITICAL();
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Unlinks element from the head of the list.
+ *
+ * \param[in] list - ID of list to remove from.
+ *
+ * \return NULL if list is empty.
+ *         ID of removed element(pointer) if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_RemoveHead(list_handle_t list)
+{
+    list_element_handle_t listElement;
+
+    LIST_ENTER_CRITICAL();
+
+    if ((NULL == list) || (list->size == 0U))
+    {
+        listElement = NULL; /*LIST_ is empty*/
+    }
+    else
+    {
+        listElement = list->head;
+        list->size--;
+        if (list->size == 0U)
+        {
+            list->tail = NULL;
+        }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+        else
+        {
+            listElement->next->prev = NULL;
+        }
+#endif
+        listElement->list = NULL;
+        list->head        = listElement->next; /*Is NULL if element is head*/
+    }
+
+    LIST_EXIT_CRITICAL();
+    return listElement;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets head element ID.
+ *
+ * \param[in] list - ID of list.
+ *
+ * \return NULL if list is empty.
+ *         ID of head element if list is not empty.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetHead(list_handle_t list)
+{
+    return list->head;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets next element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is tail.
+ *         ID of next element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetNext(list_element_handle_t listElement)
+{
+    return listElement->next;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets previous element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is head.
+ *         ID of previous element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetPrev(list_element_handle_t listElement)
+{
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+    return NULL;
+#else
+    return listElement->prev;
+#endif
+}
+
+/*! *********************************************************************************
+ * \brief     Unlinks an element from its list.
+ *
+ * \param[in] element - ID of the element to remove.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ *         kLIST_Ok if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_RemoveElement(list_element_handle_t listElement)
+{
+    list_status_t listStatus = kLIST_Ok;
+    LIST_ENTER_CRITICAL();
+
+    if (listElement->list == NULL)
+    {
+        listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+    }
+    else
+    {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+        list_element_handle_t element_list = listElement->list->head;
+        list_element_handle_t element_Prev = NULL;
+        while (NULL != element_list)
+        {
+            if (listElement->list->head == listElement)
+            {
+                listElement->list->head = element_list->next;
+                break;
+            }
+            if (element_list->next == listElement)
+            {
+                element_Prev       = element_list;
+                element_list->next = listElement->next;
+                break;
+            }
+            element_list = element_list->next;
+        }
+        if (listElement->next == NULL)
+        {
+            listElement->list->tail = element_Prev;
+        }
+#else
+        if (listElement->prev == NULL)                   /*Element is head or solo*/
+        {
+            listElement->list->head = listElement->next; /*is null if solo*/
+        }
+        if (listElement->next == NULL)                   /*Element is tail or solo*/
+        {
+            listElement->list->tail = listElement->prev; /*is null if solo*/
+        }
+        if (listElement->prev != NULL)                   /*Element is not head*/
+        {
+            listElement->prev->next = listElement->next;
+        }
+        if (listElement->next != NULL) /*Element is not tail*/
+        {
+            listElement->next->prev = listElement->prev;
+        }
+#endif
+        listElement->list->size--;
+        listElement->list = NULL;
+    }
+
+    LIST_EXIT_CRITICAL();
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Links an element in the previous position relative to a given member
+ *            of a list.
+ *
+ * \param[in] element - ID of a member of a list.
+ *            newElement - new element to insert before the given member.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ *         kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement)
+{
+    list_status_t listStatus = kLIST_Ok;
+    LIST_ENTER_CRITICAL();
+
+    if (listElement->list == NULL)
+    {
+        listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+    }
+    else
+    {
+        listStatus = LIST_Error_Check(listElement->list, newElement);
+        if (listStatus == kLIST_Ok)
+        {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+            list_element_handle_t element_list = listElement->list->head;
+            while (NULL != element_list)
+            {
+                if ((element_list->next == listElement) || (element_list == listElement))
+                {
+                    if (element_list == listElement)
+                    {
+                        listElement->list->head = newElement;
+                    }
+                    else
+                    {
+                        element_list->next = newElement;
+                    }
+                    newElement->list = listElement->list;
+                    newElement->next = listElement;
+                    listElement->list->size++;
+                    break;
+                }
+                element_list = element_list->next;
+            }
+
+#else
+            if (listElement->prev == NULL) /*Element is list head*/
+            {
+                listElement->list->head = newElement;
+            }
+            else
+            {
+                listElement->prev->next = newElement;
+            }
+            newElement->list = listElement->list;
+            listElement->list->size++;
+            newElement->next  = listElement;
+            newElement->prev  = listElement->prev;
+            listElement->prev = newElement;
+#endif
+        }
+    }
+
+    LIST_EXIT_CRITICAL();
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the current size of a list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Current size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetSize(list_handle_t list)
+{
+    return list->size;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the number of free places in the list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Available size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetAvailableSize(list_handle_t list)
+{
+    return (list->max - list->size); /*Gets the number of free places in the list*/
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/lists/fsl_component_generic_list.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/lists/fsl_component_generic_list.h
new file mode 100644
index 0000000000..07d18359dd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/lists/fsl_component_generic_list.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2018-2020, 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _GENERIC_LIST_H_
+#define _GENERIC_LIST_H_
+
+#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON
+#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U)
+#endif
+#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
+#include "fsl_common.h"
+#else
+#endif
+/*!
+ * @addtogroup GenericList
+ * @{
+ */
+
+/**********************************************************************************
+ * Include
+ ***********************************************************************************/
+
+/**********************************************************************************
+ * Public macro definitions
+ ***********************************************************************************/
+/*! @brief Definition to determine whether use list light. */
+#ifndef GENERIC_LIST_LIGHT
+#define GENERIC_LIST_LIGHT (1)
+#endif
+
+/*! @brief Definition to determine whether enable list duplicated checking. */
+#ifndef GENERIC_LIST_DUPLICATED_CHECKING
+#define GENERIC_LIST_DUPLICATED_CHECKING (0)
+#endif
+
+/**********************************************************************************
+ * Public type definitions
+ ***********************************************************************************/
+/*! @brief The list status */
+#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
+typedef enum _list_status
+{
+    kLIST_Ok             = kStatus_Success,                   /*!< Success */
+    kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
+    kLIST_Full           = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
+    kLIST_Empty          = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
+    kLIST_OrphanElement  = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
+    kLIST_NotSupport     = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support  */
+} list_status_t;
+#else
+typedef enum _list_status
+{
+    kLIST_Ok             = 0, /*!< Success */
+    kLIST_DuplicateError = 1, /*!< Duplicate Error */
+    kLIST_Full           = 2, /*!< FULL */
+    kLIST_Empty          = 3, /*!< Empty */
+    kLIST_OrphanElement  = 4, /*!< Orphan Element */
+    kLIST_NotSupport     = 5, /*!< Not Support  */
+} list_status_t;
+#endif
+
+/*! @brief The list structure*/
+typedef struct list_label
+{
+    struct list_element_tag *head; /*!< list head */
+    struct list_element_tag *tail; /*!< list tail */
+    uint32_t size;                 /*!< list size */
+    uint32_t max;                  /*!< list max number of elements */
+} list_label_t, *list_handle_t;
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+    struct list_element_tag *next; /*!< next list element   */
+    struct list_label *list;       /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#else
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+    struct list_element_tag *next; /*!< next list element   */
+    struct list_element_tag *prev; /*!< previous list element */
+    struct list_label *list;       /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#endif
+/**********************************************************************************
+ * Public prototypes
+ ***********************************************************************************/
+/**********************************************************************************
+ * API
+ **********************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+/*!
+ * @brief Initialize the list.
+ *
+ * This function initialize the list.
+ *
+ * @param list - List handle to initialize.
+ * @param max - Maximum number of elements in list. 0 for unlimited.
+ */
+void LIST_Init(list_handle_t list, uint32_t max);
+
+/*!
+ * @brief Gets the list that contains the given element.
+ *
+ *
+ * @param listElement - Handle of the element.
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.
+ */
+list_handle_t LIST_GetList(list_element_handle_t listElement);
+
+/*!
+ * @brief Links element to the head of the list.
+ *
+ * @param list - Handle of the list.
+ * @param listElement - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement);
+
+/*!
+ * @brief Links element to the tail of the list.
+ *
+ * @param list - Handle of the list.
+ * @param listElement - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement);
+
+/*!
+ * @brief Unlinks element from the head of the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_RemoveHead(list_handle_t list);
+
+/*!
+ * @brief Gets head element handle.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetHead(list_handle_t list);
+
+/*!
+ * @brief Gets next element handle for given element handle.
+ *
+ * @param listElement - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetNext(list_element_handle_t listElement);
+
+/*!
+ * @brief Gets previous element handle for given element handle.
+ *
+ * @param listElement - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetPrev(list_element_handle_t listElement);
+
+/*!
+ * @brief Unlinks an element from its list.
+ *
+ * @param listElement - Handle of the element.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_RemoveElement(list_element_handle_t listElement);
+
+/*!
+ * @brief Links an element in the previous position relative to a given member of a list.
+ *
+ * @param listElement - Handle of the element.
+ * @param newElement - New element to insert before the given member.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement);
+
+/*!
+ * @brief Gets the current size of a list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Current size of the list.
+ */
+uint32_t LIST_GetSize(list_handle_t list);
+
+/*!
+ * @brief Gets the number of free places in the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Available size of the list.
+ */
+uint32_t LIST_GetAvailableSize(list_handle_t list);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /*_GENERIC_LIST_H_*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction.h
new file mode 100644
index 0000000000..69da7ca297
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction.h
@@ -0,0 +1,1101 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_H_
+#define _FSL_OS_ABSTRACTION_H_
+
+#ifndef __ZEPHYR__
+#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON
+#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U)
+#endif
+#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
+#include "fsl_common.h"
+#else
+#endif
+
+#include "fsl_os_abstraction_config.h"
+#include "fsl_component_generic_list.h"
+
+/*!
+ * @addtogroup osa_adapter
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Type for the Task Priority*/
+typedef uint16_t osa_task_priority_t;
+/*! @brief Type for a task handler */
+typedef void *osa_task_handle_t;
+/*! @brief Type for the parameter to be passed to the task at its creation */
+typedef void *osa_task_param_t;
+/*! @brief Type for task pointer. Task prototype declaration */
+typedef void (*osa_task_ptr_t)(osa_task_param_t task_param);
+/*! @brief Type for the semaphore handler */
+typedef void *osa_semaphore_handle_t;
+/*! @brief Type for the mutex handler */
+typedef void *osa_mutex_handle_t;
+/*! @brief Type for the event handler */
+typedef void *osa_event_handle_t;
+/*! @brief Type for an event flags group, bit 32 is reserved. */
+typedef uint32_t osa_event_flags_t;
+/*! @brief Message definition. */
+typedef void *osa_msg_handle_t;
+/*! @brief Type for the message queue handler */
+typedef void *osa_msgq_handle_t;
+/*! @brief Type for the Timer handler */
+typedef void *osa_timer_handle_t;
+/*! @brief Type for the Timer callback function pointer. */
+typedef void (*osa_timer_fct_ptr_t)(void const *argument);
+/*! @brief Thread Definition structure contains startup information of a thread.*/
+typedef struct osa_task_def_tag
+{
+    osa_task_ptr_t pthread; /*!< start address of thread function*/
+    uint32_t tpriority;     /*!< initial thread priority*/
+    uint32_t instances;     /*!< maximum number of instances of that thread function*/
+    uint32_t stacksize;     /*!< stack size requirements in bytes; 0 is default stack size*/
+    uint32_t *tstack;       /*!< stack pointer, which can be used on freertos static allocation*/
+    void *tlink;            /*!< link pointer*/
+    uint8_t *tname;         /*!< name pointer*/
+    uint8_t useFloat;       /*!< is use float*/
+} osa_task_def_t;
+/*! @brief Thread Link Definition structure .*/
+typedef struct osa_thread_link_tag
+{
+    uint8_t link[12];                  /*!< link*/
+    osa_task_handle_t osThreadId;      /*!< thread id*/
+    osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/
+    uint32_t *osThreadStackHandle;     /*!< pointer of thread stack handle*/
+} osa_thread_link_t, *osa_thread_link_handle_t;
+
+/*! @brief Definition structure contains timer parameters.*/
+typedef struct osa_time_def_tag
+{
+    osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */
+    void *argument;                 /* < argument of a timer function */
+} osa_time_def_t;
+
+/*! @brief Type for the timer definition*/
+typedef enum _osa_timer
+{
+    KOSA_TimerOnce     = 0, /*!< one-shot timer*/
+    KOSA_TimerPeriodic = 1  /*!< repeating timer*/
+} osa_timer_t;
+
+/*! @brief Defines the return status of OSA's functions */
+#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
+typedef enum _osa_status
+{
+    KOSA_StatusSuccess = kStatus_Success,                  /*!< Success */
+    KOSA_StatusError   = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */
+    KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */
+    KOSA_StatusIdle    = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready
+                                                                 and timeout still not occur */
+} osa_status_t;
+#else
+typedef enum _osa_status
+{
+    KOSA_StatusSuccess = 0, /*!< Success */
+    KOSA_StatusError   = 1, /*!< Failed */
+    KOSA_StatusTimeout = 2, /*!< Timeout occurs while waiting */
+    KOSA_StatusIdle    = 3, /*!< Used for bare metal only, the wait object is not ready
+                                                and timeout still not occur */
+} osa_status_t;
+
+#endif
+
+#ifdef USE_RTOS
+#undef USE_RTOS
+#endif
+
+#if defined(SDK_OS_FREE_RTOS)
+#include "fsl_os_abstraction_free_rtos.h"
+#elif defined(FSL_RTOS_THREADX)
+#include "fsl_os_abstraction_threadx.h"
+#elif defined(__ZEPHYR__)
+#include "fsl_os_abstraction_zephyr.h"
+#else
+#include "fsl_os_abstraction_bm.h"
+#endif
+
+extern const uint8_t gUseRtos_c;
+
+#if defined(SDK_OS_MQX)
+#define USE_RTOS (1)
+#elif defined(SDK_OS_FREE_RTOS)
+#define USE_RTOS (1)
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+#define OSA_TASK_HANDLE_SIZE (150U)
+#else
+#define OSA_TASK_HANDLE_SIZE (12U)
+#endif
+#else
+#define OSA_TASK_HANDLE_SIZE (16U)
+#endif
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+#define OSA_EVENT_HANDLE_SIZE (40U)
+#else
+#define OSA_EVENT_HANDLE_SIZE (8U)
+#endif
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+#define OSA_SEM_HANDLE_SIZE (84U)
+#else
+#define OSA_SEM_HANDLE_SIZE (4U)
+#endif
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+#define OSA_MUTEX_HANDLE_SIZE (84U)
+#else
+#define OSA_MUTEX_HANDLE_SIZE (4U)
+#endif
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+#define OSA_MSGQ_HANDLE_SIZE (84U)
+#else
+#define OSA_MSGQ_HANDLE_SIZE (4U)
+#endif
+#define OSA_MSG_HANDLE_SIZE   (0U)
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+#define OSA_TIMER_HANDLE_SIZE (48U)
+#else
+#define OSA_TIMER_HANDLE_SIZE (4U)
+#endif
+#elif defined(SDK_OS_UCOSII)
+#define USE_RTOS (1)
+#elif defined(SDK_OS_UCOSIII)
+#define USE_RTOS (1)
+#elif defined(FSL_RTOS_THREADX)
+#define USE_RTOS (1)
+#elif defined(__ZEPHYR__)
+#define USE_RTOS (1)
+#else
+#define USE_RTOS (0)
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#define OSA_TASK_HANDLE_SIZE (24U)
+#else
+#define OSA_TASK_HANDLE_SIZE (28U)
+#endif
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+#define OSA_EVENT_HANDLE_SIZE (20U)
+#else
+#define OSA_EVENT_HANDLE_SIZE (16U)
+#endif /* FSL_OSA_TASK_ENABLE */
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#define OSA_SEM_HANDLE_SIZE   (16U)
+#define OSA_MUTEX_HANDLE_SIZE (12U)
+#else
+#define OSA_SEM_HANDLE_SIZE   (8U)
+#define OSA_MUTEX_HANDLE_SIZE (4U)
+#endif
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+#define OSA_MSGQ_HANDLE_SIZE (32U)
+#else
+#define OSA_MSGQ_HANDLE_SIZE (28U)
+#endif /* FSL_OSA_TASK_ENABLE */
+#define OSA_MSG_HANDLE_SIZE (4U)
+#endif
+
+/*! @brief Priority setting for OSA. */
+#ifndef OSA_PRIORITY_IDLE
+#define OSA_PRIORITY_IDLE (6U)
+#endif
+
+#ifndef OSA_PRIORITY_LOW
+#define OSA_PRIORITY_LOW (5U)
+#endif
+
+#ifndef OSA_PRIORITY_BELOW_NORMAL
+#define OSA_PRIORITY_BELOW_NORMAL (4U)
+#endif
+
+#ifndef OSA_PRIORITY_NORMAL
+#define OSA_PRIORITY_NORMAL (3U)
+#endif
+
+#ifndef OSA_PRIORITY_ABOVE_NORMAL
+#define OSA_PRIORITY_ABOVE_NORMAL (2U)
+#endif
+
+#ifndef OSA_PRIORITY_HIGH
+#define OSA_PRIORITY_HIGH (1U)
+#endif
+
+#ifndef OSA_PRIORITY_REAL_TIME
+#define OSA_PRIORITY_REAL_TIME (0U)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MAX
+#define OSA_TASK_PRIORITY_MAX (0U)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MIN
+#define OSA_TASK_PRIORITY_MIN (15U)
+#endif
+
+/*
+ * Converse the percent of the priority to the priority of the OSA.
+ * The the range of the parameter x is 0-100.
+ */
+#define OSA_TASK_PRIORITY_PERCENT(x) \
+    ((((OSA_TASK_PRIORITY_MIN - OSA_TASK_PRIORITY_MAX) * (100 - (x))) / 100) + OSA_TASK_PRIORITY_MAX)
+
+#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t))
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define osaWaitNone_c            ((uint32_t)(0))
+#define osaWaitForever_c         ((uint32_t)(-1))
+#define osaEventFlagsAll_c       ((osa_event_flags_t)(0x00FFFFFF))
+#define osThreadStackArray(name) osThread_##name##_stack
+#define osThreadStackDef(name, stacksize, instances) \
+    const uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)];
+
+/* ==== Thread Management ==== */
+
+/* Create a Thread Definition with function, priority, and stack requirements.
+ * \param         name         name of the thread function.
+ * \param         priority     initial priority of the thread function.
+ * \param         instances    number of possible thread instances.
+ * \param         stackSz      stack size (in bytes) requirements for the thread function.
+ * \param         useFloat
+ */
+#if defined(SDK_OS_MQX)
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                                        \
+    osa_thread_link_t osThreadLink_##name[instances]                               = {0};                    \
+    osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = {                       \
+        (name),           (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+        (uint8_t *)#name, (useFloat)}
+#elif defined(SDK_OS_UCOSII)
+#if gTaskMultipleInstancesManagement_c
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                                        \
+    osa_thread_link_t osThreadLink_##name[instances]                               = {0};                    \
+    osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = {                       \
+        (name),           (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+        (uint8_t *)#name, (useFloat)}
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                  \
+    osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+        (name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)}
+#endif
+#elif defined(FSL_RTOS_THREADX)
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                   \
+    uint32_t s_stackBuffer##name[(stackSz + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]; \
+    static const osa_task_def_t os_thread_def_##name = {                                \
+        (name), (priority), (instances), (stackSz), s_stackBuffer##name, NULL, (uint8_t *)#name, (useFloat)}
+#else
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                   \
+    uint32_t s_stackBuffer##name[(stackSz + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]; \
+    static const osa_task_def_t os_thread_def_##name = {                                \
+        (name), (priority), (instances), (stackSz), s_stackBuffer##name, NULL, (uint8_t *)#name, (useFloat)}
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                             \
+    const osa_task_def_t os_thread_def_##name = {(name), (priority), (instances),      (stackSz), \
+                                                 NULL,   NULL,       (uint8_t *)#name, (useFloat)}
+#endif
+#endif
+/* Access a Thread defintion.
+ * \param         name          name of the thread definition object.
+ */
+#define OSA_TASK(name) (const osa_task_def_t *)&os_thread_def_##name
+
+#define OSA_TASK_PROTO(name) extern osa_task_def_t os_thread_def_##name
+/*  ==== Timer Management  ====
+ * Define a Timer object.
+ * \param         name          name of the timer object.
+ * \param         function      name of the timer call back function.
+ */
+
+#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL}
+
+/* Access a Timer definition.
+ * \param         name          name of the timer object.
+ */
+#define OSA_TIMER(name) &os_timer_def_##name
+
+/* ==== Buffer Definition ==== */
+
+/*!
+ * @brief Defines the semaphore handle
+ *
+ * This macro is used to define a 4 byte aligned semaphore handle.
+ * Then use "(osa_semaphore_handle_t)name" to get the semaphore handle.
+ *
+ * The macro should be global and could be optional. You could also define semaphore handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * @endcode
+ *
+ * @param name The name string of the semaphore handle.
+ */
+#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \
+    uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the mutex handle
+ *
+ * This macro is used to define a 4 byte aligned mutex handle.
+ * Then use "(osa_mutex_handle_t)name" to get the mutex handle.
+ *
+ * The macro should be global and could be optional. You could also define mutex handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * @endcode
+ *
+ * @param name The name string of the mutex handle.
+ */
+#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the event handle
+ *
+ * This macro is used to define a 4 byte aligned event handle.
+ * Then use "(osa_event_handle_t)name" to get the event handle.
+ *
+ * The macro should be global and could be optional. You could also define event handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * @endcode
+ *
+ * @param name The name string of the event handle.
+ */
+#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the message queue handle
+ *
+ * This macro is used to define a 4 byte aligned message queue handle.
+ * Then use "(osa_msgq_handle_t)name" to get the message queue handle.
+ *
+ * The macro should be global and could be optional. You could also define message queue handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct));
+ * @endcode
+ *
+ * @param name The name string of the message queue handle.
+ * @param numberOfMsgs Number of messages.
+ * @param msgSize Message size.
+ *
+ */
+#if defined(SDK_OS_FREE_RTOS) && (defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0))
+/*< Macro For FREE_RTOS dynamic allocation*/
+#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
+    uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+#else
+/*< Macro For BARE_MATEL and FREE_RTOS static allocation*/
+#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
+    uint32_t name[((OSA_MSGQ_HANDLE_SIZE + numberOfMsgs * msgSize) + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+#endif
+
+/*!
+ * @brief Defines the timer handle
+ *
+ * This macro is used to define a 4 byte aligned timer handle.
+ * Then use "(osa_timer_handle_t)name" to get the timer handle.
+ *
+ * The macro should be global and could be optional. You could also define timer handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_TIMER_HANDLE_DEFINE(timerHandle);
+ * @endcode
+ *
+ * @param name The name string of the timer handle.
+ */
+#define OSA_TIMER_HANDLE_DEFINE(name) uint32_t name[(OSA_TIMER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the TASK handle
+ *
+ * This macro is used to define a 4 byte aligned TASK handle.
+ * Then use "(osa_task_handle_t)name" to get the TASK handle.
+ *
+ * The macro should be global and could be optional. You could also define TASK handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * @endcode
+ *
+ * @param name The name string of the TASK handle.
+ */
+#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+#ifndef __DSB
+#define __DSB()
+#endif
+/*
+ * alloc the temporary memory to store the status
+ */
+#define OSA_SR_ALLOC() uint32_t osaCurrentSr = 0U;
+/*
+ * Enter critical mode
+ */
+#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr)
+/*
+ * Exit critical mode and retore the previous mode
+ */
+#define OSA_EXIT_CRITICAL() \
+    __DSB();                \
+    OSA_ExitCritical(osaCurrentSr);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * The function is used to reserve the requested amount of memory in bytes and initializes it to 0.
+ *
+ * @param memLength Amount of bytes to reserve.
+ *
+ * @return Pointer to the reserved memory. NULL if memory can't be allocated.
+ */
+void *OSA_MemoryAllocate(uint32_t memLength);
+
+/*!
+ * @brief Frees the memory previously reserved.
+ *
+ * The function is used to free the memory block previously reserved.
+ *
+ * @param p Pointer to the start of the memory block previously reserved.
+ *
+ */
+void OSA_MemoryFree(void *p);
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * The function is used to reserve the requested amount of memory in bytes and initializes it to 0.
+ * The function allocates some extra memory to ensure that the return address is aligned on a alignbytes boundary
+ * and that the memory size is a multiple of alignbytes.
+ *
+ * @param memLength Amount of bytes to reserve.
+ * @param alignbytes Bytes boundary.
+ *
+ * @return Pointer to the reserved memory. NULL if memory can't be allocated.
+ */
+void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes);
+
+/*!
+ * @brief Frees the memory previously reserved.
+ *
+ * The function is used to free the memory block previously reserved.
+ *
+ * @param p Pointer to the start of the memory block previously reserved.
+ *
+ */
+void OSA_MemoryFreeAlign(void *p);
+
+/*!
+ * @brief Enter critical with nesting mode.
+ *
+ * @param sr Store current status and return to caller.
+ */
+void OSA_EnterCritical(uint32_t *sr);
+
+/*!
+ * @brief Exit critical with nesting mode.
+ *
+ * @param sr Previous status to restore.
+ */
+void OSA_ExitCritical(uint32_t sr);
+
+/*!
+ * @name Task management
+ * @{
+ */
+
+/*!
+ * @brief Initialize OSA.
+ *
+ * This function is used to setup the basic services.
+ *
+ * Example below shows how to use this API to create the task handle.
+ * @code
+ *   OSA_Init();
+ * @endcode
+ */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Init(void);
+#endif
+
+/*!
+ * @brief Start OSA schedule.
+ *
+ * This function is used to start OSA scheduler.
+ *
+ * Example below shows how to use this API to start osa schedule.
+ * @code
+ *   OSA_Start();
+ * @endcode
+ */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Start(void);
+#endif
+
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+/*!
+ * @brief Creates a task.
+ *
+ * This function is used to create task based on the resources defined
+ * by the macro OSA_TASK_DEFINE.
+ *
+ * Example below shows how to use this API to create the task handle.
+ * @code
+ *   OSA_TASK_HANDLE_DEFINE(taskHandle);
+ *   OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);
+ *   OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL);
+ * @endcode
+ *
+ * @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * or
+ * uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param thread_def pointer to theosa_task_def_t structure which defines the task.
+ * @param task_param Pointer to be passed to the task when it is created.
+ * @retval KOSA_StatusSuccess The task is successfully created.
+ * @retval KOSA_StatusError   The task can not be created.
+ */
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle,
+                            const osa_task_def_t *thread_def,
+                            osa_task_param_t task_param);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+/*!
+ * @brief Gets the handler of active task.
+ *
+ * @return Handler to current active task.
+ */
+osa_task_handle_t OSA_TaskGetCurrentHandle(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+/*!
+ * @brief Puts the active task to the end of scheduler's queue.
+ *
+ * When a task calls this function, it gives up the CPU and puts itself to the
+ * end of a task ready list.
+ *
+ * @retval NULL
+ */
+void OSA_TaskYield(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+/*!
+ * @brief Gets the priority of a task.
+ *
+ * @param taskHandle The handler of the task whose priority is received.
+ *
+ * @return Task's priority.
+ */
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+/*!
+ * @brief Sets the priority of a task.
+ *
+ * @param taskHandle  The handler of the task whose priority is set.
+ * @param taskPriority The priority to set.
+ *
+ * @retval KOSA_StatusSuccess Task's priority is set successfully.
+ * @retval KOSA_StatusError   Task's priority can not be set.
+ */
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+/*!
+ * @brief Destroys a previously created task.
+ *
+ * @param taskHandle The handler of the task to destroy.
+ *
+ * @retval KOSA_StatusSuccess The task was successfully destroyed.
+ * @retval KOSA_StatusError   Task destruction failed or invalid parameter.
+ */
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Pre-creates a semaphore.
+ *
+ * This function pre-creates a semaphore with the task handler.
+ *
+ * Example below shows how to use this API to create the semaphore handle.
+ * @code
+ *   OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ *   OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, (osa_task_ptr_t)taskHandler);
+ * @endcode
+ *
+ * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * or
+ * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param taskHandler  The task handler this semaphore is used by.
+ *
+ * @retval KOSA_StatusSuccess  the new semaphore if the semaphore is created successfully.
+ */
+osa_status_t OSA_SemaphorePrecreate(osa_semaphore_handle_t semaphoreHandle, osa_task_ptr_t taskHandler);
+
+/*!
+ * @brief Creates a semaphore with a given value.
+ *
+ * This function creates a semaphore and sets the value to the parameter
+ * initValue.
+ *
+ * Example below shows how to use this API to create the semaphore handle.
+ * @code
+ *   OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ *   OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff);
+ * @endcode
+ *
+ * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * or
+ * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param initValue Initial value the semaphore will be set to.
+ *
+ * @retval KOSA_StatusSuccess  the new semaphore if the semaphore is created successfully.
+ * @retval KOSA_StatusError   if the semaphore can not be created.
+ */
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue);
+
+/*!
+ * @brief Creates a binary semaphore.
+ *
+ * This function creates a binary semaphore
+ *
+ * Example below shows how to use this API to create the semaphore handle.
+ * @code
+ *   OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ *   OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)semaphoreHandle);
+ * @endcode
+ *
+ * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * or
+ * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ *
+ * @retval KOSA_StatusSuccess  the new binary semaphore if the binary semaphore is created successfully.
+ * @retval KOSA_StatusError   if the binary semaphore can not be created.
+ */
+osa_status_t OSA_SemaphoreCreateBinary(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Destroys a previously created semaphore.
+ *
+ * @param semaphoreHandle The semaphore handle.
+ * The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer,
+ * and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully destroyed.
+ * @retval KOSA_StatusError   The semaphore can not be destroyed.
+ */
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Pending a semaphore with timeout.
+ *
+ * This function checks the semaphore's counting value. If it is positive,
+ * decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used
+ * to wait.
+ *
+ * @param semaphoreHandle    The semaphore handle.
+ * @param millisec The maximum number of milliseconds to wait if semaphore is not
+ *                 positive. Pass osaWaitForever_c to wait indefinitely, pass 0
+ *                 will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess  The semaphore is received.
+ * @retval KOSA_StatusTimeout  The semaphore is not received within the specified 'timeout'.
+ * @retval KOSA_StatusError    An incorrect parameter was passed.
+ */
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec);
+
+/*!
+ * @brief Signals for someone waiting on the semaphore to wake up.
+ *
+ * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
+ * the semaphore's counting value.
+ *
+ * @param semaphoreHandle The semaphore handle to signal.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully signaled.
+ * @retval KOSA_StatusError   The object can not be signaled or invalid parameter.
+ *
+ */
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Create an unlocked mutex.
+ *
+ * This function creates a non-recursive mutex and sets it to unlocked status.
+ *
+ * Example below shows how to use this API to create the mutex handle.
+ * @code
+ *   OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ *   OSA_MutexCreate((osa_mutex_handle_t)mutexHandle);
+ * @endcode
+ *
+ * @param mutexHandle       Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * or
+ * uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @retval KOSA_StatusSuccess  the new mutex if the mutex is created successfully.
+ * @retval KOSA_StatusError   if the mutex can not be created.
+ */
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Waits for a mutex and locks it.
+ *
+ * This function checks the mutex's status. If it is unlocked, locks it and returns the
+ * KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock.
+ *
+ * @param mutexHandle The mutex handle.
+ * @param millisec The maximum number of milliseconds to wait for the mutex.
+ *                 If the mutex is locked, Pass the value osaWaitForever_c will
+ *                 wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ *                 immediately.
+ *
+ * @retval KOSA_StatusSuccess The mutex is locked successfully.
+ * @retval KOSA_StatusTimeout Timeout occurred.
+ * @retval KOSA_StatusError   Incorrect parameter was passed.
+ *
+ * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked.
+ */
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec);
+
+/*!
+ * @brief Unlocks a previously locked mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully unlocked.
+ * @retval KOSA_StatusError   The mutex can not be unlocked or invalid parameter.
+ */
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Destroys a previously created mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully destroyed.
+ * @retval KOSA_StatusError   The mutex can not be destroyed.
+ *
+ */
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Pre-initializes an event object.
+ *
+ * This function pre-creates an event object and indicates which task this event is used by.
+ *
+ * Example below shows how to use this API to create the event handle.
+ * @code
+ *   OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ *   OSA_EventPrecreate((osa_event_handle_t)eventHandle, (osa_task_ptr_t)taskHandler);
+ * @endcode
+ *
+ * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * or
+ * uint32 eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32) - 1U) / sizeof(uint32))];
+ * @param taskHandler The task handler this event is used by.
+ * @retval KOSA_StatusSuccess  the new event if the event is pre-created successfully.
+ */
+osa_status_t OSA_EventPrecreate(osa_event_handle_t eventHandle, osa_task_ptr_t taskHandler);
+
+/*!
+ * @brief Initializes an event object with all flags cleared.
+ *
+ * This function creates an event object and set its clear mode. If autoClear
+ * is 1, when a task gets the event flags, these flags will be
+ * cleared automatically. Otherwise these flags must
+ * be cleared manually.
+ *
+ * Example below shows how to use this API to create the event handle.
+ * @code
+ *   OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ *   OSA_EventCreate((osa_event_handle_t)eventHandle, 0);
+ * @endcode
+ *
+ * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * or
+ * uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param autoClear 1 The event is auto-clear.
+ *                  0 The event manual-clear
+ * @retval KOSA_StatusSuccess  the new event if the event is created successfully.
+ * @retval KOSA_StatusError   if the event can not be created.
+ */
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear);
+
+/*!
+ * @brief Sets one or more event flags.
+ *
+ * Sets specified flags of an event object.
+ *
+ * @param eventHandle     The event handle.
+ * @param flagsToSet  Flags to be set.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully set.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet);
+
+/*!
+ * @brief Clears one or more flags.
+ *
+ * Clears specified flags of an event object.
+ *
+ * @param eventHandle       The event handle.
+ * @param flagsToClear  Flags to be clear.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully cleared.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear);
+
+/*!
+ * @brief Get event's flags.
+ *
+ * Get specified flags of an event object.
+ *
+ * @param eventHandle       The event handle.
+ * The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer,
+ * and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used.
+ * @param flagsMask         The flags user want to get are specified by this parameter.
+ * @param pFlagsOfEvent     The event flags are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The event flags were successfully got.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle,
+                          osa_event_flags_t flagsMask,
+                          osa_event_flags_t *pFlagsOfEvent);
+
+/*!
+ * @brief Waits for specified event flags to be set.
+ *
+ * This function waits for a combination of flags to be set in an event object.
+ * Applications can wait for any/all bits to be set. Also this function could
+ * obtain the flags who wakeup the waiting task.
+ *
+ * @param eventHandle     The event handle.
+ * @param flagsToWait Flags that to wait.
+ * @param waitAll     Wait all flags or any flag to be set.
+ * @param millisec    The maximum number of milliseconds to wait for the event.
+ *                    If the wait condition is not met, pass osaWaitForever_c will
+ *                    wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ *                    immediately.
+ * @param pSetFlags    Flags that wakeup the waiting task are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The wait condition met and function returns successfully.
+ * @retval KOSA_StatusTimeout Has not met wait condition within timeout.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+
+ *
+ * @note    Please pay attention to the flags bit width, FreeRTOS uses the most
+ *          significant 8 bis as control bits, so do not wait these bits while using
+ *          FreeRTOS.
+ *
+ */
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+                           osa_event_flags_t flagsToWait,
+                           uint8_t waitAll,
+                           uint32_t millisec,
+                           osa_event_flags_t *pSetFlags);
+
+/*!
+ * @brief Destroys a previously created event object.
+ *
+ * @param eventHandle The event handle.
+ *
+ * @retval KOSA_StatusSuccess The event is successfully destroyed.
+ * @retval KOSA_StatusError   Event destruction failed.
+ */
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle);
+
+/*!
+ * @brief Initializes a message queue.
+ *
+ * This function  allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*.
+ *
+ * Example below shows how to use this API to create the massage queue handle.
+ * @code
+ *   OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
+ *   OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg));
+ * @endcode
+ *
+ * @param msgqHandle    Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel,
+ * FreeRTOS static allocation allocated by the caller and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS dynamic allocation,
+ * message queue handle. The handle should be 4 byte aligned, because unaligned access doesn't be supported on some
+ * devices. You can define the handle in the following two ways: #OSA_MSGQ_HANDLE_DEFINE(msgqHandle); or For bm and
+ * freertos static: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) /
+ * sizeof(uint32_t))]; For freertos dynamic: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) /
+ * sizeof(uint32_t))];
+ * @param msgNo :number of messages the message queue should accommodate.
+ * @param msgSize :size of a single message structure.
+ *
+ * @retval KOSA_StatusSuccess Message queue successfully Create.
+ * @retval KOSA_StatusError     Message queue create failure.
+ */
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize);
+
+/*!
+ * @brief Puts a message at the end of the queue.
+ *
+ * This function puts a message to the end of the message queue. If the queue
+ * is full, this function returns the KOSA_StatusError;
+ *
+ * @param msgqHandle  Message Queue handler.
+ * @param pMessage Pointer to the message to be put into the queue.
+ *
+ * @retval KOSA_StatusSuccess Message successfully put into the queue.
+ * @retval KOSA_StatusError   The queue was full or an invalid parameter was passed.
+ */
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage);
+
+/*!
+ * @brief Reads and remove a message at the head of the queue.
+ *
+ * This function gets a message from the head of the message queue. If the
+ * queue is empty, timeout is used to wait.
+ *
+ * @param msgqHandle   Message Queue handler.
+ * @param pMessage Pointer to a memory to save the message.
+ * @param millisec The number of milliseconds to wait for a message. If the
+ *                 queue is empty, pass osaWaitForever_c will wait indefinitely,
+ *                 pass 0 will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess   Message successfully obtained from the queue.
+ * @retval KOSA_StatusTimeout   The queue remains empty after timeout.
+ * @retval KOSA_StatusError     Invalid parameter.
+ */
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec);
+
+/*!
+ * @brief Get the available message
+ *
+ * This function is used to get the available message.
+ *
+ * @param msgqHandle Message Queue handler.
+ *
+ * @return Available message count
+ */
+int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle);
+
+/*!
+ * @brief Destroys a previously created queue.
+ *
+ * @param msgqHandle Message Queue handler.
+ *
+ * @retval KOSA_StatusSuccess The queue was successfully destroyed.
+ * @retval KOSA_StatusError   Message queue destruction failed.
+ */
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle);
+
+/*!
+ * @brief Enable all interrupts.
+ */
+void OSA_InterruptEnable(void);
+
+/*!
+ * @brief Disable all interrupts.
+ */
+void OSA_InterruptDisable(void);
+
+/*!
+ * @brief Enable all interrupts using PRIMASK.
+ */
+void OSA_EnableIRQGlobal(void);
+
+/*!
+ * @brief Disable all interrupts using PRIMASK.
+ */
+void OSA_DisableIRQGlobal(void);
+
+/*!
+ * @brief Disable the scheduling of any task.
+ */
+void OSA_DisableScheduler(void);
+
+/*!
+ * @brief Enable the scheduling of any task.
+ */
+void OSA_EnableScheduler(void);
+
+/*!
+ * @brief Delays execution for a number of milliseconds.
+ *
+ * @param millisec The time in milliseconds to wait.
+ */
+void OSA_TimeDelay(uint32_t millisec);
+
+/*!
+ * @brief This function gets current time in milliseconds.
+ *
+ * @retval current time in milliseconds
+ */
+uint32_t OSA_TimeGetMsec(void);
+
+/*!
+ * @brief Installs the interrupt handler.
+ *
+ * @param IRQNumber IRQ number of the interrupt.
+ * @param handler The interrupt handler to install.
+ */
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void));
+
+/*! @}*/
+#ifdef __cplusplus
+}
+#endif
+/*! @}*/
+#else
+#include "fsl_os_abstraction_zephyr.h"
+#endif /* ! __ZEPHYR__ */
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_config.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_config.h
new file mode 100644
index 0000000000..288d3e6d18
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_config.h
@@ -0,0 +1,48 @@
+/*!
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
+#define _FSL_OS_ABSTRACTION_CONFIG_H_
+
+#ifndef gMainThreadStackSize_c
+#define gMainThreadStackSize_c 1024
+#endif
+
+#ifndef gMainThreadPriority_c
+#define gMainThreadPriority_c 7
+#endif
+
+#ifndef gTaskMultipleInstancesManagement_c
+#define gTaskMultipleInstancesManagement_c 0
+#endif
+
+/*! @brief Definition to determine whether enable OSA's TASK module. */
+#ifndef OSA_USED
+#ifndef FSL_OSA_TASK_ENABLE
+#define FSL_OSA_TASK_ENABLE 0U
+#endif
+#else
+#if defined(FSL_OSA_TASK_ENABLE)
+#undef FSL_OSA_TASK_ENABLE
+#endif
+#define FSL_OSA_TASK_ENABLE 1U
+#endif /* OSA_USED */
+
+#ifndef FSL_OSA_MAIN_FUNC_ENABLE
+#define FSL_OSA_MAIN_FUNC_ENABLE 0U
+#endif
+
+#ifndef FSL_OSA_BM_TIMEOUT_ENABLE
+#define FSL_OSA_BM_TIMEOUT_ENABLE 0U
+#endif
+
+#ifndef FSL_OSA_ALLOCATED_HEAP
+#define FSL_OSA_ALLOCATED_HEAP (1U)
+#endif
+
+#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_free_rtos.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_free_rtos.c
new file mode 100644
index 0000000000..90ff5a6740
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_free_rtos.c
@@ -0,0 +1,1347 @@
+/*! *********************************************************************************
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * This is the source file for the OS Abstraction layer for freertos.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_common.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_os_abstraction_free_rtos.h"
+#include <string.h>
+#include "fsl_component_generic_list.h"
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private macros
+*************************************************************************************
+********************************************************************************** */
+
+/* Weak function. */
+#if defined(__GNUC__)
+#define __WEAK_FUNC __attribute__((weak))
+#elif defined(__ICCARM__)
+#define __WEAK_FUNC __weak
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define __WEAK_FUNC __attribute__((weak))
+#endif
+
+#define millisecToTicks(millisec) (((millisec)*configTICK_RATE_HZ + 999U) / 1000U)
+
+#ifdef DEBUG_ASSERT
+#define OS_ASSERT(condition) \
+    if (!(condition))        \
+        while (1)            \
+            ;
+#else
+#define OS_ASSERT(condition) (void)(condition);
+#endif
+
+/*! @brief Converts milliseconds to ticks*/
+#define MSEC_TO_TICK(msec) \
+    (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL)
+#define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ))
+
+#define OSA_MEM_MAGIC_NUMBER (12345U)
+#define OSA_MEM_SIZE_ALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+
+/************************************************************************************
+*************************************************************************************
+* Private type definitions
+*************************************************************************************
+************************************************************************************/
+typedef struct osa_freertos_task
+{
+    list_element_t link;
+    TaskHandle_t taskHandle;
+} osa_freertos_task_t;
+
+typedef struct _osa_event_struct
+{
+    EventGroupHandle_t eventHandle; /* The event handle */
+    uint8_t autoClear;         /*!< Auto clear or manual clear   */
+} osa_event_struct_t;
+
+/*! @brief State structure for bm osa manager. */
+typedef struct _osa_state
+{
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+    list_label_t taskList;
+#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))
+    OSA_TASK_HANDLE_DEFINE(mainTaskHandle);
+#endif
+#endif
+    uint32_t basePriority;
+    int32_t basePriorityNesting;
+    uint32_t interruptDisableCount;
+} osa_state_t;
+
+/*! @brief Definition structure contains allocated memory information.*/
+typedef struct _osa_mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} osa_mem_align_cb_t;
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private prototypes
+*************************************************************************************
+********************************************************************************** */
+__WEAK_FUNC void main_task(void const *argument);
+__WEAK_FUNC void main_task(void const *argument)
+{
+}
+
+void startup_task(void *argument);
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public memory declarations
+*************************************************************************************
+********************************************************************************** */
+const uint8_t gUseRtos_c = USE_RTOS; /* USE_RTOS = 0 for BareMetal and 1 for OS */
+
+static osa_state_t s_osaState = {0};
+
+/* Allocate the memory for the heap. */
+#if (defined(FSL_OSA_ALLOCATED_HEAP) && (FSL_OSA_ALLOCATED_HEAP > 0U))
+#if defined(configAPPLICATION_ALLOCATED_HEAP) && (configAPPLICATION_ALLOCATED_HEAP)
+#if defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE)
+extern uint8_t ucHeap[configTOTAL_HEAP_SIZE];
+AT_NONCACHEABLE_SECTION_ALIGN(uint8_t ucHeap[configTOTAL_HEAP_SIZE], 4);
+#else
+extern uint8_t ucHeap[configTOTAL_HEAP_SIZE];
+SDK_ALIGN(uint8_t ucHeap[configTOTAL_HEAP_SIZE], 4);
+#endif /* DATA_SECTION_IS_CACHEABLE */
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+#endif /* FSL_OSA_ALLOCATED_HEAP */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private memory declarations
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryAllocate
+ * Description   : Reserves the requested amount of memory in bytes.
+ *
+ *END**************************************************************************/
+void *OSA_MemoryAllocate(uint32_t memLength)
+{
+#if defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0)
+
+    void *p = (void *)pvPortMalloc(memLength);
+
+    if (NULL != p)
+    {
+        (void)memset(p, 0, memLength);
+    }
+
+    return p;
+#else
+    return NULL;
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryFree
+ * Description   : Frees the memory previously reserved.
+ *
+ *END**************************************************************************/
+void OSA_MemoryFree(void *p)
+{
+#if defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0)
+    vPortFree(p);
+#endif
+}
+
+void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes)
+{
+    osa_mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)OSA_MEM_SIZE_ALIGN(memLength, alignbytes);
+    if (alignedsize < memLength)
+    {
+        return NULL;
+    }
+
+    if (alignedsize > 0xFFFFFFFFU - alignbytes - sizeof(osa_mem_align_cb_t))
+    {
+        return NULL;
+    }
+
+    alignedsize += alignbytes + (uint32_t)sizeof(osa_mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = OSA_MemoryAllocate(alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = OSA_MEM_SIZE_ALIGN(p_addr.unsigned_value + sizeof(osa_mem_align_cb_t), alignbytes);
+
+    p_cb             = (osa_mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = OSA_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void OSA_MemoryFreeAlign(void *p)
+{
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = p;
+    osa_mem_align_cb_t *p_cb = (osa_mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != OSA_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    OSA_MemoryFree(p_free.pointer_value);
+}
+
+void OSA_EnterCritical(uint32_t *sr)
+{
+#if defined(__GIC_PRIO_BITS)
+    if ((__get_CPSR() & CPSR_M_Msk) == 0x13)
+#else
+    if (0U != __get_IPSR())
+#endif
+    {
+        *sr = portSET_INTERRUPT_MASK_FROM_ISR();
+    }
+    else
+    {
+        portENTER_CRITICAL();
+    }
+}
+
+void OSA_ExitCritical(uint32_t sr)
+{
+#if defined(__GIC_PRIO_BITS)
+    if ((__get_CPSR() & CPSR_M_Msk) == 0x13)
+#else
+    if (0U != __get_IPSR())
+#endif
+    {
+        portCLEAR_INTERRUPT_MASK_FROM_ISR(sr);
+    }
+    else
+    {
+        portEXIT_CRITICAL();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : startup_task
+ * Description   : Wrapper over main_task..
+ *
+ *END**************************************************************************/
+void startup_task(void *argument)
+{
+    main_task(argument);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetCurrentHandle
+ * Description   : This function is used to get current active task's handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_handle_t OSA_TaskGetCurrentHandle(void)
+{
+    list_element_handle_t list_element;
+    osa_freertos_task_t *ptask;
+
+    list_element = LIST_GetHead(&s_osaState.taskList);
+    while (NULL != list_element)
+    {
+        ptask = (osa_freertos_task_t *)(void *)list_element;
+        if (ptask->taskHandle == xTaskGetCurrentTaskHandle())
+        {
+            return (osa_task_handle_t)ptask;
+        }
+        list_element = LIST_GetNext(list_element);
+    }
+    return NULL;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskYield
+ * Description   : When a task calls this function, it will give up CPU and put
+ * itself to the tail of ready list.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_TaskYield(void)
+{
+    taskYIELD();
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetPriority
+ * Description   : This function returns task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle)
+{
+    assert(NULL != taskHandle);
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+    return (osa_task_priority_t)(PRIORITY_RTOS_TO_OSA((uxTaskPriorityGet(ptask->taskHandle))));
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskSetPriority
+ * Description   : This function sets task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority)
+{
+    assert(NULL != taskHandle);
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+    vTaskPrioritySet((task_handler_t)ptask->taskHandle, PRIORITY_OSA_TO_RTOS(((uint32_t)taskPriority)));
+    return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskCreate
+ * Description   : This function is used to create a task and make it ready.
+ * Param[in]     :  threadDef  - Definition of the thread.
+ *                  task_param - Parameter to pass to the new thread.
+ * Return Thread handle of the new thread, or NULL if failed.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t *thread_def, osa_task_param_t task_param)
+{
+    osa_status_t status = KOSA_StatusError;
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    assert((sizeof(osa_freertos_task_t) + sizeof(StaticTask_t)) <= OSA_TASK_HANDLE_SIZE);  
+#else
+    assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE);        
+#endif
+    assert(NULL != taskHandle);
+#if defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0)
+    TaskHandle_t pxCreatedTask;
+#endif
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    TaskHandle_t xHandle = NULL;
+#endif
+    OSA_InterruptDisable();
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    xHandle = xTaskCreateStatic(
+            (TaskFunction_t)thread_def->pthread, /* pointer to the task */
+                        (const char *)thread_def->tname,     /* task name for kernel awareness debugging */
+                        (uint32_t)((uint16_t)thread_def->stacksize / sizeof(portSTACK_TYPE)), /* task stack size */
+                        (task_param_t)task_param,                      /* optional task startup argument */
+                        PRIORITY_OSA_TO_RTOS((thread_def->tpriority)), /* initial priority */
+                        thread_def->tstack,    /*Array to use as the task's stack*/
+                        (StaticTask_t *)((uint8_t *)(taskHandle) + sizeof(osa_freertos_task_t))/*Variable to hold the task's data structure*/
+                        );
+      if(xHandle != NULL)
+      {
+          ptask->taskHandle = xHandle;
+          (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link));
+          status = KOSA_StatusSuccess;
+      }
+#else
+    if (xTaskCreate(
+            (TaskFunction_t)thread_def->pthread, /* pointer to the task */
+            (char const *)thread_def->tname,     /* task name for kernel awareness debugging */
+            (configSTACK_DEPTH_TYPE)((uint16_t)thread_def->stacksize / sizeof(portSTACK_TYPE)), /* task stack size */
+            (task_param_t)task_param,                      /* optional task startup argument */
+            PRIORITY_OSA_TO_RTOS((thread_def->tpriority)), /* initial priority */
+            &pxCreatedTask                                 /* optional task handle to create */
+            ) == pdPASS)
+    {
+        ptask->taskHandle = pxCreatedTask;
+
+        (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link));
+
+        status = KOSA_StatusSuccess;
+    }
+#endif
+    OSA_InterruptEnable();
+    return status;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskDestroy
+ * Description   : This function destroy a task.
+ * Param[in]     :taskHandle - Thread handle.
+ * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle)
+{
+    assert(NULL != taskHandle);
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+    osa_status_t status;
+    UBaseType_t oldPriority;
+
+    /*Change priority to avoid context switches*/
+    oldPriority = uxTaskPriorityGet(xTaskGetCurrentTaskHandle());
+    vTaskPrioritySet(xTaskGetCurrentTaskHandle(), (configMAX_PRIORITIES - 1));
+#if INCLUDE_vTaskDelete /* vTaskDelete() enabled */
+    vTaskDelete((task_handler_t)ptask->taskHandle);
+    status = KOSA_StatusSuccess;
+#else
+    status = KOSA_StatusError; /* vTaskDelete() not available */
+#endif
+    vTaskPrioritySet(xTaskGetCurrentTaskHandle(), oldPriority);
+    OSA_InterruptDisable();
+    (void)LIST_RemoveElement(taskHandle);
+    OSA_InterruptEnable();
+    return status;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeDelay
+ * Description   : This function is used to suspend the active thread for the given number of milliseconds.
+ *
+ *END**************************************************************************/
+void OSA_TimeDelay(uint32_t millisec)
+{
+    vTaskDelay(millisecToTicks(millisec));
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeGetMsec
+ * Description   : This function gets current time in milliseconds.
+ *
+ *END**************************************************************************/
+uint32_t OSA_TimeGetMsec(void)
+{
+    TickType_t ticks;
+
+    if (0U != __get_IPSR())
+    {
+        ticks = xTaskGetTickCountFromISR();
+    }
+    else
+    {
+        ticks = xTaskGetTickCount();
+    }
+
+    return TICKS_TO_MSEC(ticks);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphorePrecreate
+ * Description   : This function is used to pre-create a semaphore.
+ * Return         : KOSA_StatusSuccess
+ *
+ *END**************************************************************************/
+
+osa_status_t OSA_SemaphorePrecreate(osa_semaphore_handle_t semaphoreHandle, osa_task_ptr_t taskHandler)
+{
+    semaphoreHandle = semaphoreHandle;
+    taskHandler     = taskHandler;
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreCreate
+ * Description   : This function is used to create a semaphore.
+ * Return         : Semaphore handle of the new semaphore, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue)
+{
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    assert((sizeof(osa_semaphore_handle_t) + sizeof(StaticQueue_t)) == OSA_SEM_HANDLE_SIZE);
+#else
+    assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE);
+#endif
+    assert(NULL != semaphoreHandle);
+
+    union
+    {
+        QueueHandle_t sem;
+        uint32_t semhandle;
+    } xSemaHandle;
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    xSemaHandle.sem = xSemaphoreCreateCountingStatic(0xFF, initValue, (StaticQueue_t *)(void *)((uint8_t *)semaphoreHandle + sizeof(osa_semaphore_handle_t)));
+#else
+    xSemaHandle.sem = xSemaphoreCreateCounting(0xFF, initValue);
+#endif
+    if (NULL != xSemaHandle.sem)
+    {
+        *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle;
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreCreateBinary
+ * Description   : This function is used to create a binary semaphore.
+ * Return        : Semaphore handle of the new binary semaphore, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreCreateBinary(osa_semaphore_handle_t semaphoreHandle)
+{
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    assert((sizeof(osa_semaphore_handle_t) + sizeof(StaticQueue_t)) == OSA_SEM_HANDLE_SIZE);
+#else
+    assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE);
+#endif
+    assert(NULL != semaphoreHandle);
+
+    union
+    {
+        QueueHandle_t sem;
+        uint32_t semhandle;
+    } xSemaHandle;
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    xSemaHandle.sem = xSemaphoreCreateBinaryStatic((StaticQueue_t *)(void *)((uint8_t *)semaphoreHandle + sizeof(osa_semaphore_handle_t)));    
+#else
+    xSemaHandle.sem = xSemaphoreCreateBinary();
+#endif
+    if (NULL != xSemaHandle.sem)
+    {
+        *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle;
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreDestroy
+ * Description   : This function is used to destroy a semaphore.
+ * Return        : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle)
+{
+    assert(NULL != semaphoreHandle);
+    QueueHandle_t sem = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+
+    vSemaphoreDelete(sem);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreWait
+ * Description   : This function checks the semaphore's counting value, if it is
+ * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout
+ * will be used for wait. The parameter timeout indicates how long should wait
+ * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will
+ * return KOSA_StatusTimeout immediately if semaphore is not positive.
+ * This function returns KOSA_StatusSuccess if the semaphore is received, returns
+ * KOSA_StatusTimeout if the semaphore is not received within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec)
+{
+    uint32_t timeoutTicks;
+    assert(NULL != semaphoreHandle);
+    QueueHandle_t sem = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+
+    /* Convert timeout from millisecond to tick. */
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = MSEC_TO_TICK(millisec);
+    }
+
+    if (((BaseType_t)0) == (BaseType_t)xSemaphoreTake(sem, timeoutTicks))
+    {
+        return KOSA_StatusTimeout; /* timeout */
+    }
+    else
+    {
+        return KOSA_StatusSuccess; /* semaphore taken */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphorePost
+ * Description   : This function is used to wake up one task that wating on the
+ * semaphore. If no task is waiting, increase the semaphore. The function returns
+ * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns
+ * KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle)
+{
+    assert(NULL != semaphoreHandle);
+    osa_status_t status = KOSA_StatusError;
+    QueueHandle_t sem   = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+
+    if (0U != __get_IPSR())
+    {
+        portBASE_TYPE taskToWake = (portBASE_TYPE)pdFALSE;
+
+        if (((BaseType_t)1) == (BaseType_t)xSemaphoreGiveFromISR(sem, &taskToWake))
+        {
+            portYIELD_FROM_ISR(((bool)(taskToWake)));
+            status = KOSA_StatusSuccess;
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+    else
+    {
+        if (((BaseType_t)1) == (BaseType_t)xSemaphoreGive(sem))
+        {
+            status = KOSA_StatusSuccess; /* sync object given */
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexCreate
+ * Description   : This function is used to create a mutex.
+ * Return        : Mutex handle of the new mutex, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle)
+{
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    assert((sizeof(osa_mutex_handle_t) + sizeof(StaticQueue_t)) == OSA_MUTEX_HANDLE_SIZE);  
+#else
+    assert(sizeof(osa_mutex_handle_t) == OSA_MUTEX_HANDLE_SIZE);
+#endif
+    assert(NULL != mutexHandle);
+
+    union
+    {
+        QueueHandle_t mutex;
+        uint32_t pmutexHandle;
+    } xMutexHandle;
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    xMutexHandle.mutex = xSemaphoreCreateRecursiveMutexStatic((StaticQueue_t *)(void *)((uint8_t *)mutexHandle + sizeof(osa_mutex_handle_t)));
+#else
+    xMutexHandle.mutex = xSemaphoreCreateRecursiveMutex();
+#endif
+    if (NULL != xMutexHandle.mutex)
+    {
+        *(uint32_t *)mutexHandle = xMutexHandle.pmutexHandle;
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexLock
+ * Description   : This function checks the mutex's status, if it is unlocked,
+ * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex.
+ * This function returns KOSA_StatusSuccess if the mutex is obtained, returns
+ * KOSA_StatusError if any errors occur during waiting. If the mutex has been
+ * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec)
+{
+    assert(NULL != mutexHandle);
+    uint32_t timeoutTicks;
+    QueueHandle_t mutex = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+
+    /* Convert timeout from millisecond to tick. */
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = MSEC_TO_TICK(millisec);
+    }
+
+    if (((BaseType_t)0) == (BaseType_t)xSemaphoreTakeRecursive(mutex, timeoutTicks))
+    {
+        return KOSA_StatusTimeout; /* timeout */
+    }
+    else
+    {
+        return KOSA_StatusSuccess; /* semaphore taken */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexUnlock
+ * Description   : This function is used to unlock a mutex.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle)
+{
+    assert(NULL != mutexHandle);
+    QueueHandle_t mutex = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+
+    if (((BaseType_t)0) == (BaseType_t)xSemaphoreGiveRecursive(mutex))
+    {
+        return KOSA_StatusError;
+    }
+    else
+    {
+        return KOSA_StatusSuccess;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexDestroy
+ * Description   : This function is used to destroy a mutex.
+ * Return        : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle)
+{
+    assert(NULL != mutexHandle);
+    QueueHandle_t mutex = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+
+    vSemaphoreDelete(mutex);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventPrecreate
+ * Description   : This function is used to pre-create a event.
+ * Return         : KOSA_StatusSuccess
+ *
+ *END**************************************************************************/
+
+osa_status_t OSA_EventPrecreate(osa_event_handle_t eventHandle, osa_task_ptr_t taskHandler)
+{
+    eventHandle = eventHandle;
+    taskHandler = taskHandler;
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventCreate
+ * Description   : This function is used to create a event object.
+ * Return        : Event handle of the new event, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear)
+{
+    assert(NULL != eventHandle);
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    assert((sizeof(osa_event_struct_t) + sizeof(StaticEventGroup_t)) <= OSA_EVENT_HANDLE_SIZE);  
+#else
+    assert(sizeof(osa_event_struct_t) == OSA_EVENT_HANDLE_SIZE);
+#endif
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; 
+    
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    pEventStruct->eventHandle = xEventGroupCreateStatic((StaticEventGroup_t *)(void *)((uint8_t *)(eventHandle) + sizeof(osa_event_struct_t)));
+#else    
+    pEventStruct->eventHandle = xEventGroupCreate();
+#endif
+    if (NULL != pEventStruct->eventHandle)
+    {
+        pEventStruct->autoClear = autoClear;
+    }
+    else
+    {
+        return KOSA_StatusError;
+    }
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventSet
+ * Description   : Set one or more event flags of an event object.
+ * Return        : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet)
+{
+    portBASE_TYPE taskToWake = (portBASE_TYPE)pdFALSE;
+    BaseType_t result;
+    assert(NULL != eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    if (NULL == pEventStruct->eventHandle)
+    {
+        return KOSA_StatusError;
+    }
+    if (0U != __get_IPSR())
+    {
+#if (configUSE_TRACE_FACILITY == 1)
+        result = xEventGroupSetBitsFromISR(pEventStruct->eventHandle, (event_flags_t)flagsToSet, &taskToWake);
+#else
+        result = xEventGroupSetBitsFromISR((void *)pEventStruct->eventHandle, (event_flags_t)flagsToSet, &taskToWake);
+#endif
+        assert(pdPASS == result);
+        (void)result;
+        portYIELD_FROM_ISR(((bool)(taskToWake)));
+    }
+    else
+    {
+        (void)xEventGroupSetBits(pEventStruct->eventHandle, (event_flags_t)flagsToSet);
+    }
+
+    (void)result;
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventClear
+ * Description   : Clear one or more event flags of an event object.
+ * Return        :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear)
+{
+    assert(NULL != eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    if (NULL == pEventStruct->eventHandle)
+    {
+        return KOSA_StatusError;
+    }
+
+    if (0U != __get_IPSR())
+    {
+#if (configUSE_TRACE_FACILITY == 1)
+        (void)xEventGroupClearBitsFromISR(pEventStruct->eventHandle, (event_flags_t)flagsToClear);
+#else
+        (void)xEventGroupClearBitsFromISR((void *)pEventStruct->eventHandle, (event_flags_t)flagsToClear);
+#endif
+    }
+    else
+    {
+        (void)xEventGroupClearBits(pEventStruct->eventHandle, (event_flags_t)flagsToClear);
+    }
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventGet
+ * Description   : This function is used to get event's flags that specified by prameter
+ * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So
+ * you should pass the parameter 0xffffffff to specify you want to check all.
+ * Return        :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent)
+{
+    assert(NULL != eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+    EventBits_t eventFlags;
+
+    if (NULL == pEventStruct->eventHandle)
+    {
+        return KOSA_StatusError;
+    }
+
+    if (NULL == pFlagsOfEvent)
+    {
+        return KOSA_StatusError;
+    }
+
+    if (0U != __get_IPSR())
+    {
+        eventFlags = xEventGroupGetBitsFromISR(pEventStruct->eventHandle);
+    }
+    else
+    {
+        eventFlags = xEventGroupGetBits(pEventStruct->eventHandle);
+    }
+
+    *pFlagsOfEvent = (osa_event_flags_t)eventFlags & flagsMask;
+
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventWait
+ * Description   : This function checks the event's status, if it meets the wait
+ * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value
+ * KOSA_StatusTimeout immediately if wait condition is not met. The event flags
+ * will be cleared if the event is auto clear mode. Flags that wakeup waiting
+ * task could be obtained from the parameter setFlags.
+ * This function returns KOSA_StatusSuccess if wait condition is met, returns
+ * KOSA_StatusTimeout if wait condition is not met within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+                           osa_event_flags_t flagsToWait,
+                           uint8_t waitAll,
+                           uint32_t millisec,
+                           osa_event_flags_t *pSetFlags)
+{
+    assert(NULL != eventHandle);
+    BaseType_t clearMode;
+    uint32_t timeoutTicks;
+    event_flags_t flagsSave;
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    /* Clean FreeRTOS cotrol flags */
+    flagsToWait = flagsToWait & 0x00FFFFFFU;
+    if (NULL == pEventStruct->eventHandle)
+    {
+        return KOSA_StatusError;
+    }
+
+    /* Convert timeout from millisecond to tick. */
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = millisec / portTICK_PERIOD_MS;
+    }
+
+    clearMode = (pEventStruct->autoClear != 0U) ? pdTRUE : pdFALSE;
+
+    flagsSave = xEventGroupWaitBits(pEventStruct->eventHandle, (event_flags_t)flagsToWait, clearMode, (BaseType_t)waitAll,
+                                    timeoutTicks);
+
+    flagsSave &= (event_flags_t)flagsToWait;
+    if (NULL != pSetFlags)
+    {
+        *pSetFlags = (osa_event_flags_t)flagsSave;
+    }
+
+    if (0U != flagsSave)
+    {
+        return KOSA_StatusSuccess;
+    }
+    else
+    {
+        return KOSA_StatusTimeout;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventDestroy
+ * Description   : This function is used to destroy a event object. Return
+ * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise
+ * return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle)
+{
+    assert(NULL != eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    if (NULL == pEventStruct->eventHandle)
+    {
+        return KOSA_StatusError;
+    }
+    vEventGroupDelete(pEventStruct->eventHandle);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQCreate
+ * Description   : This function is used to create a message queue.
+ * Return        : the handle to the message queue if create successfully, otherwise
+ * return NULL.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize)
+{
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    assert((sizeof(osa_msgq_handle_t) + sizeof(StaticQueue_t)) == OSA_MSGQ_HANDLE_SIZE);  
+#else
+    assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE);
+#endif
+    assert(NULL != msgqHandle);
+
+    union
+    {
+        QueueHandle_t msgq;
+        uint32_t pmsgqHandle;
+    } xMsgqHandle;
+
+    /* Create the message queue where the number and size is specified by msgNo and msgSize */
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    xMsgqHandle.msgq = xQueueCreateStatic(msgNo, msgSize, 
+                                          (uint8_t *)((uint8_t *)msgqHandle + sizeof(osa_msgq_handle_t) + sizeof(StaticQueue_t)),
+                                          (StaticQueue_t *)(void *)((uint8_t *)msgqHandle + sizeof(osa_msgq_handle_t)));
+#else
+    xMsgqHandle.msgq = xQueueCreate(msgNo, msgSize);
+#endif
+    if (NULL != xMsgqHandle.msgq)
+    {
+        *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle;
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQPut
+ * Description   : This function is used to put a message to a message queue.
+ * Return         : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage)
+{
+    osa_status_t osaStatus;
+    assert(NULL != msgqHandle);
+    portBASE_TYPE taskToWake = (portBASE_TYPE)pdFALSE;
+    QueueHandle_t handler    = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+    if (0U != __get_IPSR())
+    {
+        if (((BaseType_t)1) == (BaseType_t)xQueueSendToBackFromISR(handler, pMessage, &taskToWake))
+        {
+            portYIELD_FROM_ISR(((bool)(taskToWake)));
+            osaStatus = KOSA_StatusSuccess;
+        }
+        else
+        {
+            osaStatus = KOSA_StatusError;
+        }
+    }
+    else
+    {
+        osaStatus = (xQueueSendToBack(handler, pMessage, 0) == pdPASS) ? (KOSA_StatusSuccess) : (KOSA_StatusError);
+    }
+
+    return osaStatus;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQGet
+ * Description   : This function checks the queue's status, if it is not empty,
+ * get message from it and return KOSA_StatusSuccess, otherwise, timeout will
+ * be used for wait. The parameter timeout indicates how long should wait in
+ * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return
+ * KOSA_StatusTimeout immediately if queue is empty.
+ * This function returns KOSA_StatusSuccess if message is got successfully,
+ * returns KOSA_StatusTimeout if message queue is empty within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec)
+{
+    osa_status_t osaStatus;
+    assert(NULL != msgqHandle);
+    QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+    uint32_t timeoutTicks;
+
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = portMAX_DELAY;
+    }
+    else
+    {
+        timeoutTicks = MSEC_TO_TICK(millisec);
+    }
+    if (pdPASS != xQueueReceive(handler, pMessage, timeoutTicks))
+    {
+        osaStatus = KOSA_StatusTimeout; /* not able to send it to the queue? */
+    }
+    else
+    {
+        osaStatus = KOSA_StatusSuccess;
+    }
+    return osaStatus;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQAvailableMsgs
+ * Description   : This function is used to get the available message.
+ * Return        : Available message count
+ *
+ *END**************************************************************************/
+int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle)
+{
+    QueueHandle_t handler;
+    assert(NULL != msgqHandle);
+    handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+    return (int)uxQueueMessagesWaiting((QueueHandle_t)handler);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQDestroy
+ * Description   : This function is used to destroy the message queue.
+ * Return        : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle)
+{
+    assert(NULL != msgqHandle);
+    QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+    vQueueDelete(handler);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptEnable
+ * Description   : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptEnable(void)
+{
+    if (0U != __get_IPSR())
+    {
+        if (1 == s_osaState.basePriorityNesting)
+        {
+            portCLEAR_INTERRUPT_MASK_FROM_ISR(s_osaState.basePriority);
+        }
+
+        if (s_osaState.basePriorityNesting > 0)
+        {
+            s_osaState.basePriorityNesting--;
+        }
+    }
+    else
+    {
+        portEXIT_CRITICAL();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptDisable
+ * Description   : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptDisable(void)
+{
+    if (0U != __get_IPSR())
+    {
+        if (0 == s_osaState.basePriorityNesting)
+        {
+            s_osaState.basePriority = portSET_INTERRUPT_MASK_FROM_ISR();
+        }
+        s_osaState.basePriorityNesting++;
+    }
+    else
+    {
+        portENTER_CRITICAL();
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EnableIRQGlobal
+ * Description   : enable interrupts using PRIMASK register.
+ *
+ *END**************************************************************************/
+void OSA_EnableIRQGlobal(void)
+{
+    if (s_osaState.interruptDisableCount > 0U)
+    {
+        s_osaState.interruptDisableCount--;
+
+        if (0U == s_osaState.interruptDisableCount)
+        {
+            __enable_irq();
+        }
+        /* call core API to enable the global interrupt*/
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_DisableIRQGlobal
+ * Description   : disable interrupts using PRIMASK register.
+ *
+ *END**************************************************************************/
+void OSA_DisableIRQGlobal(void)
+{
+    /* call core API to disable the global interrupt*/
+    __disable_irq();
+
+    /* update counter*/
+    s_osaState.interruptDisableCount++;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_DisableScheduler
+ * Description   : Disable the scheduling of any task
+ * This function will disable the scheduling of any task
+ *
+ *END**************************************************************************/
+void OSA_DisableScheduler(void)
+{
+    vTaskSuspendAll();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EnableScheduler
+ * Description   : Enable the scheduling of any task
+ * This function will enable the scheduling of any task
+ *
+ *END**************************************************************************/
+void OSA_EnableScheduler(void)
+{
+    (void)xTaskResumeAll();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InstallIntHandler
+ * Description   : This function is used to install interrupt handler.
+ *
+ *END**************************************************************************/
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void))
+{
+#if defined(__IAR_SYSTEMS_ICC__)
+    _Pragma("diag_suppress = Pm138")
+#endif
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+        (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t)handler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#if defined(__IAR_SYSTEMS_ICC__)
+    _Pragma("diag_remark = PM138")
+#endif
+}
+
+/*!*********************************************************************************
+*************************************************************************************
+* Private functions
+*************************************************************************************
+********************************************************************************** */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))
+static OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0);
+
+int main(void)
+{
+    extern void BOARD_InitHardware(void);
+    OSA_Init();
+    /* Initialize MCU clock */
+    BOARD_InitHardware();
+
+    (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(startup_task), NULL);
+
+    OSA_Start();
+    return 0;
+}
+#endif /*(defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))*/
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Init
+ * Description   : This function is used to setup the basic services, it should
+ * be called first in function main.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Init(void)
+{
+    LIST_Init((&s_osaState.taskList), 0);
+    s_osaState.basePriorityNesting   = 0;
+    s_osaState.interruptDisableCount = 0;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Start
+ * Description   : This function is used to start RTOS scheduler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Start(void)
+{
+    vTaskStartScheduler();
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_free_rtos.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_free_rtos.h
new file mode 100644
index 0000000000..5e62e920d5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/osa/fsl_os_abstraction_free_rtos.h
@@ -0,0 +1,135 @@
+/*! *********************************************************************************
+ * Copyright (c) 2013-2014, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * ile
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ********************************************************************************** */
+#if !defined(__FSL_OS_ABSTRACTION_FREERTOS_H__)
+#define __FSL_OS_ABSTRACTION_FREERTOS_H__
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ */
+/* http://supp.iar.com/Support/?note=24725 */
+
+#define MISRAC_DISABLE \
+    _Pragma(           \
+        "diag_suppress=                       \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+
+#define MISRAC_ENABLE \
+    _Pragma(          \
+        "diag_default=                         \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+#else
+/* Empty MISRA C macros for other toolchains. */
+#define MISRAC_DISABLE
+#define MISRAC_ENABLE
+#endif
+
+MISRAC_DISABLE
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "event_groups.h"
+MISRAC_ENABLE
+
+/*!
+ * @addtogroup os_abstraction_free_rtos
+ * @{
+ */
+
+/*******************************************************************************
+ * Declarations
+ ******************************************************************************/
+/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */
+typedef TaskHandle_t task_handler_t;
+
+/*! @brief Type for a task stack.*/
+typedef portSTACK_TYPE task_stack_t;
+
+/*! @brief Type for task parameter */
+typedef void *task_param_t;
+
+/*! @brief Type for an event flags object.*/
+typedef EventBits_t event_flags_t;
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define OSA_WAIT_FOREVER 0xFFFFFFFFU
+
+/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
+#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
+
+/*! @brief The default interrupt handler installed in vector table. */
+#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR))
+
+extern void DefaultISR(void);
+
+/*!
+ * @name Thread management
+ * @{
+ */
+
+/*!
+ * @brief To provide unified task piority for upper layer, OSA layer makes conversion.
+ */
+#define PRIORITY_OSA_TO_RTOS(osa_prio) \
+    (((UBaseType_t)configMAX_PRIORITIES - 1U) * (OSA_TASK_PRIORITY_MIN - osa_prio) / OSA_TASK_PRIORITY_MIN)
+#define PRIORITY_RTOS_TO_OSA(rtos_prio)                                               \
+    (OSA_TASK_PRIORITY_MIN * (((UBaseType_t)configMAX_PRIORITIES - 1U) - rtos_prio) / \
+     ((UBaseType_t)configMAX_PRIORITIES - 1U))
+
+/*! @} */
+
+/*!
+ * @name Message queues
+ * @{
+ */
+
+/*!
+ * @brief This macro statically reserves the memory required for the queue.
+ *
+ * @param name Identifier for the memory region.
+ * @param number Number of elements in the queue.
+ * @param size Size of every elements in words.
+ */
+#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL
+
+/*! @} */
+
+/*! @}*/
+/*! @}*/
+/*! @}*/
+
+#endif /* __FSL_OS_ABSTRACTION_FREERTOS_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_manager.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_manager.c
new file mode 100644
index 0000000000..f9a233aa11
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_manager.c
@@ -0,0 +1,2098 @@
+/*
+ * Copyright 2018-2024 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include "fsl_component_serial_manager.h"
+#include "fsl_component_serial_port_internal.h"
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#include "fsl_component_generic_list.h"
+
+/*
+ * The OSA_USED macro can only be defined when the OSA component is used.
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED
+ * also cannot be defined.
+ * The source code path of the OSA component is <MCUXpresso_SDK>/components/osa.
+ *
+ */
+#if defined(OSA_USED)
+#include "fsl_os_abstraction.h"
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#include "fsl_component_common_task.h"
+#else
+
+#endif
+
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#else
+/* MISRA C-2012 Rule 17.2 */
+#undef assert
+#define assert(n) \
+    while (!(n))  \
+    {             \
+        ;         \
+    }
+#endif
+#endif
+
+/* Weak function. */
+#if defined(__GNUC__)
+#define __WEAK_FUNC __attribute__((weak))
+#elif defined(__ICCARM__)
+#define __WEAK_FUNC __weak
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define __WEAK_FUNC __attribute__((weak))
+#elif defined(__DSC__) || defined(__CW__)
+#define __WEAK_FUNC __attribute__((weak))
+#endif
+
+#define SERIAL_EVENT_DATA_RECEIVED   (0U)
+#define SERIAL_EVENT_DATA_SENT       (1U)
+#define SERIAL_EVENT_DATA_START_SEND (2U)
+#define SERIAL_EVENT_DATA_RX_NOTIFY  (3U)
+#define SERIAL_EVENT_DATA_NUMBER     (4U)
+
+#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U
+#define SERIAL_MANAGER_READ_TAG  0xBBAA5244U
+
+#ifndef RINGBUFFER_WATERMARK_THRESHOLD
+#define RINGBUFFER_WATERMARK_THRESHOLD 95U / 100U
+#endif
+
+#ifndef gSerialManagerLpConstraint_c
+#define gSerialManagerLpConstraint_c 0
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+typedef enum _serial_manager_transmission_mode
+{
+    kSerialManager_TransmissionBlocking    = 0x0U, /*!< Blocking transmission*/
+    kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/
+} serial_manager_transmission_mode_t;
+
+/* TX transfer structure */
+typedef struct _serial_manager_transfer
+{
+    uint8_t *buffer;
+    volatile uint32_t length;
+    volatile uint32_t soFar;
+    serial_manager_transmission_mode_t mode;
+    serial_manager_status_t status;
+} serial_manager_transfer_t;
+#endif
+
+/* write handle structure */
+typedef struct _serial_manager_send_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    list_element_t link; /*!< list element of the link */
+    serial_manager_transfer_t transfer;
+#endif
+    struct _serial_manager_handle *serialManagerHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_manager_callback_t callback;
+    void *callbackParam;
+    uint32_t tag;
+#endif
+} serial_manager_write_handle_t;
+typedef struct _serial_manager_send_block_handle
+{
+    struct _serial_manager_handle *serialManagerHandle;
+
+} serial_manager_write_block_handle_t;
+
+typedef serial_manager_write_handle_t serial_manager_read_handle_t;
+typedef serial_manager_write_block_handle_t serial_manager_read_block_handle_t;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* receive state structure */
+typedef struct _serial_manager_read_ring_buffer
+{
+    uint8_t *ringBuffer;
+    uint32_t ringBufferSize;
+    volatile uint32_t ringHead;
+    volatile uint32_t ringTail;
+} serial_manager_read_ring_buffer_t;
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+typedef struct _serial_manager_block_handle
+{
+    serial_manager_type_t handleType;
+    serial_port_type_t type;
+    serial_manager_read_handle_t *volatile openedReadHandleHead;
+    volatile uint32_t openedWriteHandleCount;
+    union
+    {
+        uint32_t lowLevelhandleBuffer[1];
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+        uint8_t uartHandleBuffer[SERIAL_PORT_UART_BLOCK_HANDLE_SIZE];
+#endif
+    };
+
+} serial_manager_block_handle_t;
+#endif
+
+/* The serial manager handle structure */
+typedef struct _serial_manager_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_manager_type_t handleType;
+#endif
+    serial_port_type_t serialPortType;
+    serial_manager_read_handle_t *volatile openedReadHandleHead;
+    volatile uint32_t openedWriteHandleCount;
+    union
+    {
+        uint32_t lowLevelhandleBuffer[1];
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+        uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+        uint8_t uartDmaHandleBuffer[SERIAL_PORT_UART_DMA_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_VIRTUAL_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+        uint8_t rpmsgHandleBuffer[SERIAL_PORT_RPMSG_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+        uint8_t spiMasterHandleBuffer[SERIAL_PORT_SPI_MASTER_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+        uint8_t spiSlaveHandleBuffer[SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        uint8_t bleWuHandleBuffer[SERIAL_PORT_BLE_WU_HANDLE_SIZE];
+#endif
+    };
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_manager_read_ring_buffer_t ringBuffer;
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+    common_task_message_t commontaskMsg;
+#else
+    OSA_SEMAPHORE_HANDLE_DEFINE(serSemaphore); /*!< Semaphore instance */
+    OSA_TASK_HANDLE_DEFINE(taskId);            /*!< Task handle */
+#endif
+    uint8_t serialManagerState[SERIAL_EVENT_DATA_NUMBER]; /*!< Used to indicate the serial mnager state */
+
+#endif
+
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    list_label_t runningWriteHandleHead;   /*!< The queue of running write handle */
+    list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */
+#endif
+
+} serial_manager_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_Task(void *param);
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+#else
+                                               /*
+                                                * \brief Defines the serial manager task's stack
+                                                */
+static OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false);
+#endif
+
+#endif
+
+#endif
+static const serial_manager_lowpower_critical_CBs_t *s_pfserialLowpowerCriticalCallbacks = NULL;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node)
+{
+    (void)LIST_AddTail(queue, &node->link);
+}
+
+static void SerialManager_RemoveHead(list_label_t *queue)
+{
+    (void)LIST_RemoveHead(queue);
+}
+
+static int32_t SerialManager_SetLpConstraint(int32_t power_mode)
+{
+    int32_t status = -1;
+    if ((s_pfserialLowpowerCriticalCallbacks != NULL) &&
+        (s_pfserialLowpowerCriticalCallbacks->serialEnterLowpowerCriticalFunc != NULL))
+    {
+        status = s_pfserialLowpowerCriticalCallbacks->serialEnterLowpowerCriticalFunc(power_mode);
+    }
+    return status;
+}
+static int32_t SerialManager_ReleaseLpConstraint(int32_t power_mode)
+{
+    int32_t status = -1;
+    if ((s_pfserialLowpowerCriticalCallbacks != NULL) &&
+        (s_pfserialLowpowerCriticalCallbacks->serialExitLowpowerCriticalFunc != NULL))
+    {
+        status = s_pfserialLowpowerCriticalCallbacks->serialExitLowpowerCriticalFunc(power_mode);
+    }
+    return status;
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle)
+{
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+    serial_manager_write_handle_t *writeHandle =
+        (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead);
+
+    if (writeHandle != NULL)
+    {
+        (void)SerialManager_SetLpConstraint(gSerialManagerLpConstraint_c);
+        switch (serHandle->serialPortType)
+        {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+            case kSerialPort_Uart:
+                status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                          writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+            case kSerialPort_UartDma:
+                status = Serial_UartDmaWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                             writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+            case kSerialPort_UsbCdc:
+                status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                            writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+            case kSerialPort_Swo:
+                status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                         writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+            case kSerialPort_Virtual:
+                status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                 writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+            case kSerialPort_Rpmsg:
+                status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                           writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+            case kSerialPort_SpiMaster:
+                status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                               writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+            case kSerialPort_SpiSlave:
+                status = Serial_SpiSlaveWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                              writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+            case kSerialPort_BleWu:
+                status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                               writeHandle->transfer.buffer, writeHandle->transfer.length);
+                break;
+#endif
+
+            default:
+                status = kStatus_SerialManager_Error;
+                break;
+        }
+        if (kStatus_SerialManager_Success != status)
+        {
+            (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c);
+        }
+    }
+    return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle,
+                                                          serial_manager_read_handle_t *readHandle,
+                                                          uint8_t *buffer,
+                                                          uint32_t length)
+{
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+
+    if (NULL != readHandle)
+    {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+        if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */
+        {
+            status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+        }
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        if (serHandle->serialPortType == kSerialPort_UsbCdc)
+        {
+            status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+        }
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        if (serHandle->serialPortType == kSerialPort_Virtual)
+        {
+            status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+        }
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+        if (serHandle->serialPortType == kSerialPort_SpiMaster)
+        {
+            status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+        }
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+        if (serHandle->serialPortType == kSerialPort_SpiSlave)
+        {
+            status = Serial_SpiSlaveRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+        }
+#endif
+
+#if 0
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+        if (serHandle->serialPortType == kSerialPort_Rpmsg)
+        {
+            status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+        }
+#endif
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        if (serHandle->serialPortType == kSerialPort_BleWu)
+        {
+            status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+        }
+#endif
+    }
+    return status;
+}
+
+#else /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle,
+                                                          serial_manager_write_handle_t *writeHandle,
+                                                          uint8_t *buffer,
+                                                          uint32_t length)
+{
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+    if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */
+    {
+        status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */
+    {
+        status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */
+    {
+        status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */
+    {
+        status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+        if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port Rpmsg */
+    {
+        status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+        if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */
+    {
+        status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */
+    {
+        status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+    {
+        /*MISRA rule*/
+    }
+    return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle,
+                                                          serial_manager_read_handle_t *readHandle,
+                                                          uint8_t *buffer,
+                                                          uint32_t length)
+{
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+    if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */
+    {
+        status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */
+    {
+        status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */
+    {
+        status = Serial_SwoRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */
+    {
+        status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+        if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port UsbCdcVirtual */
+    {
+        status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+        if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */
+    {
+        status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */
+    {
+        status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length);
+    }
+    else
+#endif
+    {
+        /*MISRA rule*/
+    }
+    return status;
+}
+#endif /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_IsrFunction(serial_manager_handle_t *serHandle)
+{
+    uint32_t regPrimask = DisableGlobalIRQ();
+    switch (serHandle->serialPortType)
+    {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+        case kSerialPort_Uart:
+            Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+        case kSerialPort_UartDma:
+            Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        case kSerialPort_UsbCdc:
+            Serial_UsbCdcIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        case kSerialPort_Swo:
+            Serial_SwoIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        case kSerialPort_Virtual:
+            Serial_PortVirtualIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        case kSerialPort_BleWu:
+            Serial_PortBleWuIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+        default:
+            /*MISRA rule 16.4*/
+            break;
+    }
+    EnableGlobalIRQ(regPrimask);
+}
+
+static void SerialManager_Task(void *param)
+{
+    serial_manager_handle_t *serHandle = (serial_manager_handle_t *)param;
+    serial_manager_write_handle_t *serialWriteHandle;
+    serial_manager_read_handle_t *serialReadHandle;
+    uint32_t primask;
+    serial_manager_callback_message_t serialMsg;
+#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U))
+    uint32_t ringBufferLength;
+#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */
+
+    if (NULL != serHandle)
+    {
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+
+        do
+        {
+            if (KOSA_StatusSuccess ==
+                OSA_SemaphoreWait((osa_semaphore_handle_t)serHandle->serSemaphore, osaWaitForever_c))
+            {
+#endif
+#endif
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+                primask     = DisableGlobalIRQ();
+                uint8_t *ev = serHandle->serialManagerState;
+                EnableGlobalIRQ(primask);
+                if (0U != (ev[SERIAL_EVENT_DATA_START_SEND]))
+#endif
+#endif
+        {
+#if defined(OSA_USED)
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+                    (void)SerialManager_StartWriting(serHandle);
+                    primask = DisableGlobalIRQ();
+                    serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]--;
+                    EnableGlobalIRQ(primask);
+#endif
+#endif
+        }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+                if (0U != (ev[SERIAL_EVENT_DATA_SENT]))
+#endif
+
+#endif
+        {
+            serialWriteHandle =
+                (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead);
+            while (NULL != serialWriteHandle)
+            {
+                SerialManager_RemoveHead(&serHandle->completedWriteHandleHead);
+                serialMsg.buffer                   = serialWriteHandle->transfer.buffer;
+                serialMsg.length                   = serialWriteHandle->transfer.soFar;
+                serialWriteHandle->transfer.buffer = NULL;
+                if (NULL != serialWriteHandle->callback)
+                {
+                    serialWriteHandle->callback(serialWriteHandle->callbackParam, &serialMsg,
+                                                serialWriteHandle->transfer.status);
+                }
+                serialWriteHandle =
+                    (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead);
+                (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c);
+            }
+#if defined(OSA_USED)
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+                    primask = DisableGlobalIRQ();
+                    serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]--;
+                    EnableGlobalIRQ(primask);
+#endif
+#endif
+        }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+                if (0U != (ev[SERIAL_EVENT_DATA_RECEIVED]))
+#endif
+
+#endif
+        {
+            primask          = DisableGlobalIRQ();
+            serialReadHandle = serHandle->openedReadHandleHead;
+            EnableGlobalIRQ(primask);
+
+            if (NULL != serialReadHandle)
+            {
+                if (NULL != serialReadHandle->transfer.buffer)
+                {
+                    if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+                    {
+                        serialMsg.buffer                  = serialReadHandle->transfer.buffer;
+                        serialMsg.length                  = serialReadHandle->transfer.soFar;
+                        serialReadHandle->transfer.buffer = NULL;
+                        if (NULL != serialReadHandle->callback)
+                        {
+                            serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg,
+                                                       serialReadHandle->transfer.status);
+                        }
+                    }
+                }
+            }
+#if defined(OSA_USED)
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+                    primask = DisableGlobalIRQ();
+                    serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]--;
+                    EnableGlobalIRQ(primask);
+#endif
+#endif
+        }
+
+#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U))
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+                if (0U != (ev[SERIAL_EVENT_DATA_RX_NOTIFY]))
+#endif
+        {
+            primask                                                 = DisableGlobalIRQ();
+            serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] = 0;
+            ringBufferLength =
+                serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail;
+            ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize;
+            EnableGlobalIRQ(primask);
+            /* Notify there are data in ringbuffer */
+            if (0U != ringBufferLength)
+            {
+                serialMsg.buffer = NULL;
+                serialMsg.length = ringBufferLength;
+                if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback))
+                {
+                    serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, &serialMsg,
+                                                           kStatus_SerialManager_Notify);
+                }
+            }
+        }
+#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+            }
+        } while (0U != gUseRtos_c);
+#endif
+
+#endif
+    }
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_TxCallback(void *callbackParam,
+                                     serial_manager_callback_message_t *message,
+                                     serial_manager_status_t status)
+{
+    serial_manager_handle_t *serHandle;
+    serial_manager_write_handle_t *writeHandle;
+#if (defined(OSA_USED))
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+    /* Need to support common_task. */
+#else /* SERIAL_MANAGER_USE_COMMON_TASK */
+    uint32_t primask;
+#endif
+#endif
+    assert(NULL != callbackParam);
+    assert(NULL != message);
+
+    serHandle = (serial_manager_handle_t *)callbackParam;
+
+    writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead);
+
+    if (NULL != writeHandle)
+    {
+        SerialManager_RemoveHead(&serHandle->runningWriteHandleHead);
+
+#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1))
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+        /* Need to support common_task. */
+#else  /* SERIAL_MANAGER_USE_COMMON_TASK */
+        primask = DisableGlobalIRQ();
+        serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++;
+        EnableGlobalIRQ(primask);
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore);
+
+#endif /* SERIAL_MANAGER_USE_COMMON_TASK */
+#else  /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */
+       (void)SerialManager_StartWriting(serHandle);
+#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */
+
+        writeHandle->transfer.soFar  = message->length;
+        writeHandle->transfer.status = status;
+        if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode)
+        {
+            SerialManager_AddTail(&serHandle->completedWriteHandleHead, writeHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+            serHandle->commontaskMsg.callback      = SerialManager_Task;
+            serHandle->commontaskMsg.callbackParam = serHandle;
+            COMMON_TASK_post_message(&serHandle->commontaskMsg);
+#else
+            primask = DisableGlobalIRQ();
+            serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]++;
+            EnableGlobalIRQ(primask);
+            (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore);
+#endif
+
+#else
+            SerialManager_Task(serHandle);
+#endif
+        }
+        else
+        {
+            writeHandle->transfer.buffer = NULL;
+            (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c);
+        }
+    }
+}
+
+void SerialManager_RxCallback(void *callbackParam,
+                              serial_manager_callback_message_t *message,
+                              serial_manager_status_t status);
+void SerialManager_RxCallback(void *callbackParam,
+                              serial_manager_callback_message_t *message,
+                              serial_manager_status_t status)
+{
+    serial_manager_handle_t *serHandle;
+#if (!((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))) && \
+     !((defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))))
+    uint32_t ringBufferLength = 0;
+    uint32_t primask;
+#endif
+    assert(NULL != callbackParam);
+    assert(NULL != message);
+
+    serHandle = (serial_manager_handle_t *)callbackParam;
+#if ((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) || \
+     (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)))
+    serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;
+    serHandle->openedReadHandleHead->transfer.soFar  = message->length;
+    serHandle->openedReadHandleHead->transfer.length = message->length;
+    serHandle->openedReadHandleHead->transfer.buffer = message->buffer;
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+    serHandle->commontaskMsg.callback      = SerialManager_Task;
+    serHandle->commontaskMsg.callbackParam = serHandle;
+    COMMON_TASK_post_message(&serHandle->commontaskMsg);
+#else
+    primask = DisableGlobalIRQ();
+    serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++;
+    EnableGlobalIRQ(primask);
+    (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore);
+#endif
+
+#else
+    SerialManager_Task(serHandle);
+#endif
+#else
+    status = kStatus_SerialManager_Notify;
+
+    primask = DisableGlobalIRQ();
+
+    /* If wrap around is expected copy byte one after the other. Note that this could also be done with 2 memcopy for
+     * better efficiency. */
+    if (serHandle->ringBuffer.ringHead + message->length >= serHandle->ringBuffer.ringBufferSize)
+    {
+        for (uint32_t i = 0; i < message->length; i++)
+        {
+            serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead++] = message->buffer[i];
+
+            if (serHandle->ringBuffer.ringHead >= serHandle->ringBuffer.ringBufferSize)
+            {
+                serHandle->ringBuffer.ringHead = 0U;
+            }
+            if (serHandle->ringBuffer.ringHead == serHandle->ringBuffer.ringTail)
+            {
+                status = kStatus_SerialManager_RingBufferOverflow;
+                serHandle->ringBuffer.ringTail++;
+                if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize)
+                {
+                    serHandle->ringBuffer.ringTail = 0U;
+                }
+            }
+        }
+    }
+    else /*No wrap is expected so do a memcpy*/
+    {
+        (void)memcpy(&serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead], message->buffer,
+                     message->length);
+        serHandle->ringBuffer.ringHead += message->length;
+    }
+
+    ringBufferLength =
+        serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail;
+    ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize;
+
+    if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->transfer.buffer))
+    {
+        if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar)
+        {
+            uint32_t remainLength =
+                serHandle->openedReadHandleHead->transfer.length - serHandle->openedReadHandleHead->transfer.soFar;
+            for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++)
+            {
+                serHandle->openedReadHandleHead->transfer.buffer[serHandle->openedReadHandleHead->transfer.soFar] =
+                    serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail];
+                serHandle->ringBuffer.ringTail++;
+                serHandle->openedReadHandleHead->transfer.soFar++;
+                if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize)
+                {
+                    serHandle->ringBuffer.ringTail = 0U;
+                }
+            }
+            ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength);
+        }
+
+        if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar)
+        {
+        }
+        else
+        {
+            if (kSerialManager_TransmissionBlocking == serHandle->openedReadHandleHead->transfer.mode)
+            {
+                serHandle->openedReadHandleHead->transfer.buffer = NULL;
+            }
+            else
+            {
+                serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+                serHandle->commontaskMsg.callback                = SerialManager_Task;
+                serHandle->commontaskMsg.callbackParam           = serHandle;
+                COMMON_TASK_post_message(&serHandle->commontaskMsg);
+#else
+                serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++;
+                (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore);
+#endif
+
+#else
+                SerialManager_Task(serHandle);
+#endif
+            }
+        }
+    }
+#if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U))
+    uint32_t ringBufferWaterMark =
+        serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail;
+    ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize;
+    if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD))
+    {
+        (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength);
+    }
+#else
+    (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength);
+#endif
+    if (0U != ringBufferLength)
+    {
+#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U))
+        if (serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] == 0)
+        {
+            serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY]++;
+            (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore);
+        }
+
+        (void)status; /* Fix "set but never used" warning. */
+#else  /* !SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */
+        message->buffer = NULL;
+        message->length = ringBufferLength;
+        if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback))
+        {
+            serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, message, status);
+        }
+#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */
+    }
+
+#if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \
+     !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))))
+    if (kSerialManager_Blocking ==
+        serHandle->handleType) /* No need to check for (NULL != serHandle->openedReadHandleHead) condition as it is
+                               already done in SerialManager_StartReading() */
+#else
+    if (NULL != serHandle->openedReadHandleHead)
+#endif
+    {
+        ringBufferLength = serHandle->ringBuffer.ringBufferSize - 1U - ringBufferLength;
+        (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength);
+    }
+    EnableGlobalIRQ(primask);
+#endif
+}
+
+/*
+ * This function is used for perdiodic check if the transfer is complete, and will be called in blocking transfer at
+ * non-blocking mode. The perdiodic unit is ms and default value is define by
+ * SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE/SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE. The function
+ * SerialManager_WriteTimeDelay()/SerialManager_ReadTimeDelay() is a weak function, so it could be re-implemented by
+ * upper layer.
+ */
+__WEAK_FUNC void SerialManager_WriteTimeDelay(uint32_t ms);
+__WEAK_FUNC void SerialManager_WriteTimeDelay(uint32_t ms)
+{
+#if defined(OSA_USED)
+    OSA_TimeDelay(ms);
+#endif
+}
+
+__WEAK_FUNC void SerialManager_ReadTimeDelay(uint32_t ms);
+__WEAK_FUNC void SerialManager_ReadTimeDelay(uint32_t ms)
+{
+#if defined(OSA_USED)
+    OSA_TimeDelay(ms);
+#endif
+}
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle,
+                                                   uint8_t *buffer,
+                                                   uint32_t length,
+                                                   serial_manager_transmission_mode_t mode)
+{
+    serial_manager_write_handle_t *serialWriteHandle;
+    serial_manager_handle_t *serHandle;
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+    serial_manager_status_t status = kStatus_SerialManager_Success;
+#endif /* SERIAL_PORT_TYPE_USBCDC */ 
+    uint32_t primask;
+    uint8_t isEmpty = 0U;
+
+    assert(NULL != writeHandle);
+    assert(NULL != buffer);
+    assert(length > 0U);
+
+    serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+    serHandle         = serialWriteHandle->serialManagerHandle;
+    assert(NULL != serHandle);
+
+    assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+    assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback)));
+
+    primask = DisableGlobalIRQ();
+    if (NULL != serialWriteHandle->transfer.buffer)
+    {
+        EnableGlobalIRQ(primask);
+        return kStatus_SerialManager_Busy;
+    }
+    serialWriteHandle->transfer.buffer = buffer;
+    serialWriteHandle->transfer.length = length;
+    serialWriteHandle->transfer.soFar  = 0U;
+    serialWriteHandle->transfer.mode   = mode;
+
+    if (NULL == LIST_GetHead(&serHandle->runningWriteHandleHead))
+    {
+        isEmpty = 1U;
+    }
+    SerialManager_AddTail(&serHandle->runningWriteHandleHead, serialWriteHandle);
+    EnableGlobalIRQ(primask);
+
+    if (0U != isEmpty)
+    {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+    if (serHandle->serialPortType == kSerialPort_UsbCdc)
+    {
+        status = Serial_UsbCdcGetConnectedStatus((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]);
+        if (status == kStatus_SerialManager_NotConnected)
+        {
+            SerialManager_RemoveHead(&serHandle->runningWriteHandleHead);
+            serialWriteHandle->transfer.buffer = NULL;
+            serialWriteHandle->transfer.length = 0U;
+            return status;
+        }
+    }
+#endif /* SERIAL_PORT_TYPE_USBCDC */    
+#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1))
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+        /* Need to support common_task. */
+#else  /* SERIAL_MANAGER_USE_COMMON_TASK */
+        if ((kSerialManager_TransmissionBlocking == mode) && (0U == gUseRtos_c))
+        {
+            (void)SerialManager_StartWriting(serHandle);
+        }
+        else
+        {
+            primask = DisableGlobalIRQ();
+            serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++;
+            EnableGlobalIRQ(primask);
+            (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore);
+        }
+#endif /* SERIAL_MANAGER_USE_COMMON_TASK */
+#else  /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */
+        (void)SerialManager_StartWriting(serHandle);
+#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */
+    }
+
+    if (kSerialManager_TransmissionBlocking == mode)
+    {
+        while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar)
+        {
+            if (SerialManager_needPollingIsr())
+            {
+                SerialManager_IsrFunction(serHandle);
+            }
+            else
+            {
+                SerialManager_WriteTimeDelay(SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE);
+            }
+        }
+    }
+    return kStatus_SerialManager_Success;
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle,
+                                                  uint8_t *buffer,
+                                                  uint32_t length,
+                                                  serial_manager_transmission_mode_t mode,
+                                                  uint32_t *receivedLength)
+{
+    serial_manager_read_handle_t *serialReadHandle;
+    serial_manager_handle_t *serHandle;
+    uint32_t dataLength;
+    uint32_t primask;
+
+    assert(NULL != readHandle);
+    assert(NULL != buffer);
+    assert(length > 0U);
+
+    serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+    serHandle = serialReadHandle->serialManagerHandle;
+    assert(NULL != serHandle);
+
+    assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+    assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback)));
+
+    primask = DisableGlobalIRQ();
+    if (NULL != serialReadHandle->transfer.buffer)
+    {
+        EnableGlobalIRQ(primask);
+        return kStatus_SerialManager_Busy;
+    }
+    serialReadHandle->transfer.buffer = buffer;
+    serialReadHandle->transfer.length = length;
+    serialReadHandle->transfer.soFar  = 0U;
+    serialReadHandle->transfer.mode   = mode;
+
+    /* This code is reached if (serHandle->handleType != kSerialManager_Blocking)*/
+#if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \
+     !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))))
+    if (length == 1U)
+    {
+        if (serHandle->ringBuffer.ringHead != serHandle->ringBuffer.ringTail)
+        {
+            buffer[serialReadHandle->transfer.soFar++] =
+                serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail];
+            serHandle->ringBuffer.ringTail++;
+            if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize)
+            {
+                serHandle->ringBuffer.ringTail = 0U;
+            }
+        }
+    }
+    else
+#endif /*(!defined(SERIAL_PORT_TYPE_USBCDC) && !defined(SERIAL_PORT_TYPE_VIRTUAL))*/
+    {
+        dataLength =
+            serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail;
+        dataLength = dataLength % serHandle->ringBuffer.ringBufferSize;
+
+        for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length);
+             serialReadHandle->transfer.soFar++)
+        {
+            buffer[serialReadHandle->transfer.soFar] = serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail];
+            serHandle->ringBuffer.ringTail++;
+            if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize)
+            {
+                serHandle->ringBuffer.ringTail = 0U;
+            }
+        }
+
+        dataLength =
+            serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail;
+        dataLength = dataLength % serHandle->ringBuffer.ringBufferSize;
+        dataLength = serHandle->ringBuffer.ringBufferSize - 1U - dataLength;
+
+        (void)SerialManager_StartReading(serHandle, readHandle, NULL, dataLength);
+    }
+
+    if (NULL != receivedLength)
+    {
+        *receivedLength                   = serialReadHandle->transfer.soFar;
+        serialReadHandle->transfer.buffer = NULL;
+        EnableGlobalIRQ(primask);
+    }
+    else
+    {
+        if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+        {
+            serialReadHandle->transfer.buffer = NULL;
+            EnableGlobalIRQ(primask);
+            if (kSerialManager_TransmissionNonBlocking == mode)
+            {
+                if (NULL != serialReadHandle->callback)
+                {
+                    serial_manager_callback_message_t serialMsg;
+                    serialMsg.buffer = buffer;
+                    serialMsg.length = serialReadHandle->transfer.soFar;
+                    serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg,
+                                               kStatus_SerialManager_Success);
+                }
+            }
+        }
+        else
+        {
+            EnableGlobalIRQ(primask);
+        }
+
+        if (kSerialManager_TransmissionBlocking == mode)
+        {
+            while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar)
+            {
+                SerialManager_ReadTimeDelay(SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE);
+            }
+        }
+    }
+#if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U))
+    uint32_t ringBufferWaterMark =
+        serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail;
+    ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize;
+    if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD))
+    {
+        (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL,
+                                         serialReadHandle->transfer.length);
+    }
+#endif
+    return kStatus_SerialManager_Success;
+}
+
+#else
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_manager_write_handle_t *serialWriteHandle;
+    serial_manager_handle_t *serHandle;
+
+    assert(writeHandle);
+    assert(buffer);
+    assert(length);
+
+    serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+    serHandle         = serialWriteHandle->serialManagerHandle;
+
+    assert(serHandle);
+
+    return SerialManager_StartWriting(serHandle, serialWriteHandle, buffer, length);
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_manager_read_handle_t *serialReadHandle;
+    serial_manager_handle_t *serHandle;
+
+    assert(readHandle);
+    assert(buffer);
+    assert(length);
+
+    serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+    serHandle        = serialReadHandle->serialManagerHandle;
+
+    assert(serHandle);
+
+    return SerialManager_StartReading(serHandle, serialReadHandle, buffer, length);
+}
+#endif
+
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig)
+{
+    serial_manager_handle_t *serHandle;
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
+    osa_task_def_t serTaskConfig;
+#endif
+#endif
+    assert(NULL != serialConfig);
+
+    assert(NULL != serialHandle);
+    assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t));
+
+    serHandle = (serial_manager_handle_t *)serialHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+    assert(NULL != serialConfig->ringBuffer);
+    assert(serialConfig->ringBufferSize > 0U);
+    (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE);
+    serHandle->handleType = serialConfig->blockType;
+#else
+    (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE);
+#endif
+    serHandle->serialPortType = serialConfig->type;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serHandle->ringBuffer.ringBuffer     = serialConfig->ringBuffer;
+    serHandle->ringBuffer.ringBufferSize = serialConfig->ringBufferSize;
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+    COMMON_TASK_init();
+
+#else
+    if (KOSA_StatusSuccess != OSA_SemaphoreCreate((osa_semaphore_handle_t)serHandle->serSemaphore, 1U))
+    {
+        return kStatus_SerialManager_Error;
+    }
+    (void)memcpy(&serTaskConfig, OSA_TASK(SerialManager_Task), sizeof(osa_task_def_t));
+    if (serialConfig->serialTaskConfig != NULL)
+    {
+        (void)memcpy(&serTaskConfig, serialConfig->serialTaskConfig, sizeof(osa_task_def_t));
+        serTaskConfig.pthread = (OSA_TASK(SerialManager_Task))->pthread;
+        serTaskConfig.tname = (OSA_TASK(SerialManager_Task))->tname;
+    }
+    if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)serHandle->taskId,(const osa_task_def_t *)&serTaskConfig, serHandle))
+    {
+        return kStatus_SerialManager_Error;
+    }
+#endif
+#endif
+
+#endif
+
+    switch (serialConfig->type)
+    {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+        case kSerialPort_Uart:
+            status = Serial_UartInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+            {
+                (void)Serial_UartInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                   SerialManager_TxCallback, serHandle);
+
+                (void)Serial_UartInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                   SerialManager_RxCallback, serHandle);
+            }
+#endif
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+        case kSerialPort_UartDma:
+            status = Serial_UartDmaInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+            {
+                (void)Serial_UartDmaInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                      SerialManager_TxCallback, serHandle);
+
+                (void)Serial_UartDmaInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                      SerialManager_RxCallback, serHandle);
+            }
+#endif
+            break;
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        case kSerialPort_UsbCdc:
+            status = Serial_UsbCdcInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+            if (kStatus_SerialManager_Success == status)
+            {
+                status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                        SerialManager_TxCallback, serHandle);
+                if (kStatus_SerialManager_Success == status)
+                {
+                    status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                            SerialManager_RxCallback, serHandle);
+                }
+            }
+#endif
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        case kSerialPort_Swo:
+            status = Serial_SwoInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if (kStatus_SerialManager_Success == status)
+            {
+                status = Serial_SwoInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                     SerialManager_TxCallback, serHandle);
+            }
+#endif
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        case kSerialPort_Virtual:
+            status =
+                Serial_PortVirtualInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if (kStatus_SerialManager_Success == status)
+            {
+                status = Serial_PortVirtualInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                             SerialManager_TxCallback, serHandle);
+                if (kStatus_SerialManager_Success == status)
+                {
+                    status = Serial_PortVirtualInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                                 SerialManager_RxCallback, serHandle);
+                }
+            }
+#endif
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+        case kSerialPort_Rpmsg:
+            status = Serial_RpmsgInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), (void *)serialConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if (kStatus_SerialManager_Success == status)
+            {
+                status = Serial_RpmsgInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                       SerialManager_TxCallback, serHandle);
+                if (kStatus_SerialManager_Success == status)
+                {
+                    status = Serial_RpmsgInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                           SerialManager_RxCallback, serHandle);
+                }
+            }
+#endif
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+        case kSerialPort_SpiMaster:
+            status =
+                Serial_SpiMasterInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if (kStatus_SerialManager_Success == status)
+            {
+                status = Serial_SpiMasterInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                           SerialManager_TxCallback, serHandle);
+                if (kStatus_SerialManager_Success == status)
+                {
+                    status = Serial_SpiMasterInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                               SerialManager_RxCallback, serHandle);
+                }
+            }
+#endif
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+        case kSerialPort_SpiSlave:
+            status = Serial_SpiSlaveInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if (kStatus_SerialManager_Success == status)
+            {
+                status = Serial_SpiSlaveInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                          SerialManager_TxCallback, serHandle);
+                if (kStatus_SerialManager_Success == status)
+                {
+                    status = Serial_SpiSlaveInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                              SerialManager_RxCallback, serHandle);
+                }
+            }
+#endif
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        case kSerialPort_BleWu:
+            status =
+                Serial_PortBleWuInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+            if (kStatus_SerialManager_Success == status)
+            {
+                status = Serial_PortBleWuInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                           SerialManager_TxCallback, serHandle);
+                if (kStatus_SerialManager_Success == status)
+                {
+                    status = Serial_PortBleWuInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]),
+                                                               SerialManager_RxCallback, serHandle);
+                }
+            }
+#endif
+            break;
+#endif
+        default:
+            /*MISRA rule 16.4*/
+            break;
+    }
+
+    return status;
+}
+
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle)
+{
+    serial_manager_handle_t *serHandle;
+
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
+
+    assert(NULL != serialHandle);
+
+    serHandle = (serial_manager_handle_t *)serialHandle;
+
+    if ((NULL != serHandle->openedReadHandleHead) || (0U != serHandle->openedWriteHandleCount))
+    {
+        serialManagerStatus = kStatus_SerialManager_Busy; /*Serial Manager Busy*/
+    }
+    else
+    {
+        switch (serHandle->serialPortType) /*serial port type*/
+        {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+            case kSerialPort_Uart:
+                (void)Serial_UartDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+            case kSerialPort_UsbCdc:
+                (void)Serial_UsbCdcDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+            case kSerialPort_Swo:
+                (void)Serial_SwoDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+            case kSerialPort_Virtual:
+                (void)Serial_PortVirtualDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+            case kSerialPort_Rpmsg:
+                (void)Serial_RpmsgDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+            case kSerialPort_SpiSlave:
+                (void)Serial_SpiSlaveDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+            case kSerialPort_SpiMaster:
+                (void)Serial_SpiMasterDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+            case kSerialPort_BleWu:
+                (void)Serial_PortBleWuDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+                break;
+#endif
+            default:
+                /*MISRA rule 16.4*/
+                break;
+        }
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+        (void)OSA_SemaphoreDestroy((osa_event_handle_t)serHandle->serSemaphore);
+        (void)OSA_TaskDestroy((osa_task_handle_t)serHandle->taskId);
+#endif
+
+#endif
+
+#endif
+    }
+    return serialManagerStatus;
+}
+
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle)
+{
+    serial_manager_handle_t *serHandle;
+    serial_manager_write_handle_t *serialWriteHandle;
+    uint32_t primask;
+
+    assert(NULL != serialHandle);
+    assert(NULL != writeHandle);
+    assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t));
+
+    serHandle         = (serial_manager_handle_t *)serialHandle;
+    serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+    primask = DisableGlobalIRQ();
+    serHandle->openedWriteHandleCount++;
+    EnableGlobalIRQ(primask);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    if (serHandle->handleType == kSerialManager_Blocking)
+    {
+        serialWriteHandle->serialManagerHandle = serHandle;
+        return kStatus_SerialManager_Success;
+    }
+    else
+#endif
+    {
+        (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+    }
+
+    serialWriteHandle->serialManagerHandle = serHandle;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG;
+#endif
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle)
+{
+    serial_manager_handle_t *serialHandle;
+    serial_manager_write_handle_t *serialWriteHandle;
+    uint32_t primask;
+
+    assert(NULL != writeHandle);
+
+    serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+    serialHandle      = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle;
+
+    assert(NULL != serialHandle);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    (void)SerialManager_CancelWriting(writeHandle);
+#endif
+    primask = DisableGlobalIRQ();
+    if (serialHandle->openedWriteHandleCount > 0U)
+    {
+        serialHandle->openedWriteHandleCount--;
+    }
+    EnableGlobalIRQ(primask);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+#else
+    (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE);
+#endif
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle)
+{
+    serial_manager_handle_t *serHandle;
+    serial_manager_read_handle_t *serialReadHandle; /* read handle structure */
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
+    uint32_t primask;
+
+    assert(NULL != serialHandle);
+    assert(NULL != readHandle);
+    assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t));
+
+    serHandle        = (serial_manager_handle_t *)serialHandle;
+    serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    if (serHandle->handleType == kSerialManager_Blocking)
+    {
+        serialReadHandle->serialManagerHandle = serHandle;
+        return kStatus_SerialManager_Success;
+    }
+#endif
+    primask = DisableGlobalIRQ();
+    if (serHandle->openedReadHandleHead != NULL)
+    {
+        serialManagerStatus = kStatus_SerialManager_Busy;
+    }
+    else
+    {
+        serHandle->openedReadHandleHead = serialReadHandle;
+
+        (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+
+        serialReadHandle->serialManagerHandle = serHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+        serialReadHandle->tag = SERIAL_MANAGER_READ_TAG;
+#endif
+    }
+    EnableGlobalIRQ(primask);
+    return serialManagerStatus;
+}
+
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle)
+{
+    serial_manager_handle_t *serialHandle;
+    serial_manager_read_handle_t *serialReadHandle;
+    uint32_t primask;
+
+    assert(NULL != readHandle);
+
+    serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+    serialHandle     = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle;
+
+    assert((NULL != serialHandle) && (serialHandle->openedReadHandleHead == serialReadHandle));
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    (void)SerialManager_CancelReading(readHandle);
+#endif
+
+    primask                            = DisableGlobalIRQ();
+    serialHandle->openedReadHandleHead = NULL;
+    EnableGlobalIRQ(primask);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+#else
+    (void)memset(readHandle, 0, SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE);
+#endif
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking);
+#else
+    return SerialManager_Write(writeHandle, buffer, length);
+#endif
+}
+
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL);
+#else
+    return SerialManager_Read(readHandle, buffer, length);
+#endif
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+                                                       uint8_t *buffer,
+                                                       uint32_t length)
+{
+    return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking);
+}
+
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+#if ((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) || \
+     (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)))
+
+    serial_manager_read_handle_t *serialReadHandle;
+    serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+    return (serial_manager_status_t)SerialManager_StartReading(serialReadHandle->serialManagerHandle, readHandle,
+                                                               buffer, length);
+#else
+    return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL);
+#endif
+}
+
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle)
+{
+    serial_manager_write_handle_t *serialWriteHandle;
+    uint32_t primask;
+    uint8_t isNotUsed        = 0U;
+    uint8_t isNotNeed2Cancel = 0U;
+
+    assert(NULL != writeHandle);
+
+    serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+    assert(NULL != serialWriteHandle->serialManagerHandle);
+    assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+    if ((NULL != serialWriteHandle->transfer.buffer) &&
+        (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode))
+    {
+        return kStatus_SerialManager_Error;
+    }
+
+    primask = DisableGlobalIRQ();
+    if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead(
+                                 &serialWriteHandle->serialManagerHandle->runningWriteHandleHead))
+    {
+        if (kLIST_Ok == LIST_RemoveElement(&serialWriteHandle->link))
+        {
+            isNotUsed = 1U;
+        }
+        else
+        {
+            isNotNeed2Cancel = 1U;
+        }
+    }
+    EnableGlobalIRQ(primask);
+
+    if (0U == isNotNeed2Cancel)
+    {
+        if (0U != isNotUsed)
+        {
+            serialWriteHandle->transfer.soFar  = 0;
+            serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled;
+
+            SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+            serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task;
+            serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam =
+                serialWriteHandle->serialManagerHandle;
+            COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg);
+#else
+            primask = DisableGlobalIRQ();
+            serialWriteHandle->serialManagerHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]++;
+            EnableGlobalIRQ(primask);
+            (void)OSA_SemaphorePost((osa_semaphore_handle_t)serialWriteHandle->serialManagerHandle->serSemaphore);
+#endif
+
+#else
+            SerialManager_Task(serialWriteHandle->serialManagerHandle);
+#endif
+        }
+        else
+        {
+            switch (serialWriteHandle->serialManagerHandle->serialPortType)
+            {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+                case kSerialPort_Uart:
+                    (void)Serial_UartCancelWrite(
+                        ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+                    break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+                case kSerialPort_UsbCdc:
+                    (void)Serial_UsbCdcCancelWrite(
+                        ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+                    break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+                case kSerialPort_Swo:
+                    (void)Serial_SwoCancelWrite(
+                        ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+                    break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+                case kSerialPort_Virtual:
+                    (void)Serial_PortVirtualCancelWrite(
+                        ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+                    break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+                case kSerialPort_SpiMaster:
+                    (void)Serial_SpiMasterCancelWrite(
+                        ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+                    break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+                case kSerialPort_SpiSlave:
+                    (void)Serial_SpiSlaveCancelWrite(
+                        ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+                    break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+                case kSerialPort_BleWu:
+                    (void)Serial_PortBleWuCancelWrite(
+                        ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+                    break;
+#endif
+                default:
+                    /*MISRA rule 16.4*/
+                    break;
+            }
+        }
+
+#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1))
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+        /* Need to support common_task. */
+#else  /* SERIAL_MANAGER_USE_COMMON_TASK */
+        primask = DisableGlobalIRQ();
+        serialWriteHandle->serialManagerHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++;
+        EnableGlobalIRQ(primask);
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)serialWriteHandle->serialManagerHandle->serSemaphore);
+
+#endif /* SERIAL_MANAGER_USE_COMMON_TASK */
+#else  /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */
+        (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle);
+#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */
+    }
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle)
+{
+    serial_manager_read_handle_t *serialReadHandle;
+    serial_manager_callback_message_t serialMsg;
+    uint8_t *buffer;
+    uint32_t primask;
+
+    assert(NULL != readHandle);
+
+    serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+    assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+    if ((NULL != serialReadHandle->transfer.buffer) &&
+        (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode))
+    {
+        return kStatus_SerialManager_Error;
+    }
+
+    primask                           = DisableGlobalIRQ();
+    buffer                            = serialReadHandle->transfer.buffer;
+    serialReadHandle->transfer.buffer = NULL;
+    serialReadHandle->transfer.length = 0;
+    serialMsg.buffer                  = buffer;
+    serialMsg.length                  = serialReadHandle->transfer.soFar;
+    EnableGlobalIRQ(primask);
+
+    if (NULL != buffer)
+    {
+        if (NULL != serialReadHandle->callback)
+        {
+            serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, kStatus_SerialManager_Canceled);
+        }
+    }
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+                                              uint8_t *buffer,
+                                              uint32_t length,
+                                              uint32_t *receivedLength)
+{
+    assert(NULL != receivedLength);
+
+    return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength);
+}
+
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam)
+{
+    serial_manager_write_handle_t *serialWriteHandle;
+
+    assert(NULL != writeHandle);
+
+    serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+    assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+    serialWriteHandle->callbackParam = callbackParam;
+    serialWriteHandle->callback      = callback;
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam)
+{
+    serial_manager_read_handle_t *serialReadHandle;
+
+    assert(NULL != readHandle);
+
+    serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+    assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+    serialReadHandle->callbackParam = callbackParam;
+    serialReadHandle->callback      = callback;
+
+    return kStatus_SerialManager_Success;
+}
+#endif
+
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle)
+{
+    serial_manager_handle_t *serHandle;
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+
+    assert(NULL != serialHandle);
+
+    serHandle = (serial_manager_handle_t *)serialHandle;
+
+    switch (serHandle->serialPortType)
+    {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+        case kSerialPort_Uart:
+            status = Serial_UartEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+        case kSerialPort_UartDma:
+            status = Serial_UartDmaEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        case kSerialPort_UsbCdc:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        case kSerialPort_Swo:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        case kSerialPort_Virtual:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        case kSerialPort_Rpmsg:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+        case kSerialPort_SpiMaster:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+        case kSerialPort_SpiSlave:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        case kSerialPort_BleWu:
+            break;
+#endif
+        default:
+            /*MISRA rule 16.4*/
+            break;
+    }
+    return status;
+}
+
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle)
+{
+    serial_manager_handle_t *serHandle;
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+
+    assert(NULL != serialHandle);
+
+    serHandle = (serial_manager_handle_t *)serialHandle;
+
+    switch (serHandle->serialPortType)
+    {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+        case kSerialPort_Uart:
+            status = Serial_UartExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+        case kSerialPort_UartDma:
+            status = Serial_UartDmaExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]));
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        case kSerialPort_UsbCdc:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        case kSerialPort_Swo:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        case kSerialPort_Virtual:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        case kSerialPort_Rpmsg:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+        case kSerialPort_SpiMaster:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+        case kSerialPort_SpiSlave:
+            break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        case kSerialPort_BleWu:
+            break;
+#endif
+        default:
+            /*MISRA rule 16.4*/
+            break;
+    }
+    return status;
+}
+/*!
+ * @brief This function performs initialization of the callbacks structure used to disable lowpower
+ *          when serial manager is active.
+ *
+ *
+ * @param  pfCallback Pointer to the function structure used to allow/disable lowpower.
+ *
+ */
+void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback)
+{
+    s_pfserialLowpowerCriticalCallbacks = pfCallback;
+    (void)s_pfserialLowpowerCriticalCallbacks;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_manager.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_manager.h
new file mode 100644
index 0000000000..b293283cfc
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_manager.h
@@ -0,0 +1,897 @@
+/*
+ * Copyright 2018-2024 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_MANAGER_H__
+#define __SERIAL_MANAGER_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup serialmanager
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U))
+#error When SERIAL_MANAGER_NON_BLOCKING_MODE=0, DEBUG_CONSOLE_TRANSFER_NON_BLOCKING can not be set.
+#else
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
+#endif
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
+#endif
+#endif
+
+/*! @brief Enable or ring buffer flow control (1 - enable, 0 - disable) */
+#ifndef SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL
+#define SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL (0U)
+#endif
+
+/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_UART
+#define SERIAL_PORT_TYPE_UART (0U)
+#endif
+
+/*! @brief Enable or disable uart dma port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_UART_DMA
+#define SERIAL_PORT_TYPE_UART_DMA (0U)
+#endif
+/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC
+#define SERIAL_PORT_TYPE_USBCDC (0U)
+#endif
+
+/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_SWO
+#define SERIAL_PORT_TYPE_SWO (0U)
+#endif
+
+/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_VIRTUAL
+#define SERIAL_PORT_TYPE_VIRTUAL (0U)
+#endif
+
+/*! @brief Enable or disable rPMSG port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_RPMSG
+#define SERIAL_PORT_TYPE_RPMSG (0U)
+#endif
+
+/*! @brief Enable or disable SPI Master port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_SPI_MASTER
+#define SERIAL_PORT_TYPE_SPI_MASTER (0U)
+#endif
+
+/*! @brief Enable or disable SPI Slave port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_SPI_SLAVE
+#define SERIAL_PORT_TYPE_SPI_SLAVE (0U)
+#endif
+
+/*! @brief Enable or disable BLE WU port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_BLE_WU
+#define SERIAL_PORT_TYPE_BLE_WU (0U)
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE == 1U))
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U))
+#warning When SERIAL_PORT_TYPE_SPI_SLAVE=1, SERIAL_MANAGER_NON_BLOCKING_MODE should be set.
+#undef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
+#endif
+#endif
+
+/*! @brief Set the default delay time in ms used by SerialManager_WriteTimeDelay(). */
+#ifndef SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE
+#define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE (1U)
+#endif
+
+/*! @brief Set the default delay time in ms used by SerialManager_ReadTimeDelay(). */
+#ifndef SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE
+#define SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE (1U)
+#endif
+
+/*! @brief Enable or disable SerialManager_Task() handle RX data available notify */
+#ifndef SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY
+#define SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY (0U)
+#endif
+#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U))
+#ifndef OSA_USED
+#error When SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY=1, OSA_USED must be set.
+#endif
+#endif
+
+/*! @brief Set serial manager write handle size */
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE       (44U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE        (44U)
+#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U)
+#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE  (4U)
+#else
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE       (4U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE        (4U)
+#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U)
+#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE  (4U)
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "fsl_component_serial_port_uart.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+#include "fsl_component_serial_port_uart.h"
+#endif
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+#include "fsl_component_serial_port_rpmsg.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "fsl_component_serial_port_usb.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+#include "fsl_component_serial_port_swo.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+#include "fsl_component_serial_port_spi.h"
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+#include "fsl_component_serial_port_spi.h"
+#endif
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "fsl_component_serial_port_virtual.h"
+#endif
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for BLE WU.
+#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */
+
+#include "fsl_component_serial_port_ble_wu.h"
+#endif /* SERIAL_PORT_TYPE_BLE_WU */
+
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+
+#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+#if (SERIAL_PORT_UART_DMA_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_DMA_HANDLE_SIZE
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+
+#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
+#if (SERIAL_PORT_SPI_MASTER_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_MASTER_HANDLE_SIZE
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+#if (SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+
+#if (SERIAL_PORT_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_VIRTUAL_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+
+#if (SERIAL_PORT_RPMSG_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_RPMSG_HANDLE_SIZE
+
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+
+#if (SERIAL_PORT_BLE_WU_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_BLE_WU_HANDLE_SIZE
+#endif
+
+#endif
+
+/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
+#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
+#else
+#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO, SERIAL_PORT_TYPE_VIRTUAL, and SERIAL_PORT_TYPE_BLE_WU should not be cleared at same time.
+#endif
+
+/*! @brief Macro to determine whether use common task. */
+#ifndef SERIAL_MANAGER_USE_COMMON_TASK
+#define SERIAL_MANAGER_USE_COMMON_TASK (0U)
+#endif
+
+#if defined(OSA_USED)
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#include "fsl_component_common_task.h"
+#endif
+/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */
+#ifndef SERIAL_MANAGER_TASK_HANDLE_TX
+#define SERIAL_MANAGER_TASK_HANDLE_TX (1U)
+#endif
+#endif
+
+#if (defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX > 0U))
+#ifndef OSA_USED
+#error When SERIAL_MANAGER_TASK_HANDLE_TX=1, OSA_USED must be set.
+#endif
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
+#include "fsl_os_abstraction.h"
+#endif
+#endif
+
+/*! @brief Definition of serial manager handle size. */
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
+#define SERIAL_MANAGER_HANDLE_SIZE \
+    (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U + OSA_TASK_HANDLE_SIZE + OSA_EVENT_HANDLE_SIZE)
+#else  /*defined(OSA_USED)*/
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U)
+#endif /*defined(OSA_USED)*/
+#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 16U)
+#else
+#define SERIAL_MANAGER_HANDLE_SIZE       (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
+#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
+#endif
+
+/*!
+ * @brief Defines the serial manager handle
+ *
+ * This macro is used to define a 4 byte aligned serial manager handle.
+ * Then use "(serial_handle_t)name" to get the serial manager handle.
+ *
+ * The macro should be global and could be optional. You could also define serial manager handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * SERIAL_MANAGER_HANDLE_DEFINE(serialManagerHandle);
+ * @endcode
+ *
+ * @param name The name string of the serial manager handle.
+ */
+#define SERIAL_MANAGER_HANDLE_DEFINE(name) \
+    uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+#define SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(name) \
+    uint32_t name[((SERIAL_MANAGER_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+/*!
+ * @brief Defines the serial manager write handle
+ *
+ * This macro is used to define a 4 byte aligned serial manager write handle.
+ * Then use "(serial_write_handle_t)name" to get the serial manager write handle.
+ *
+ * The macro should be global and could be optional. You could also define serial manager write handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialManagerwriteHandle);
+ * @endcode
+ *
+ * @param name The name string of the serial manager write handle.
+ */
+#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE(name) \
+    uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(name) \
+    uint32_t name[((SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+/*!
+ * @brief Defines the serial manager read handle
+ *
+ * This macro is used to define a 4 byte aligned serial manager read handle.
+ * Then use "(serial_read_handle_t)name" to get the serial manager read handle.
+ *
+ * The macro should be global and could be optional. You could also define serial manager read handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * SERIAL_MANAGER_READ_HANDLE_DEFINE(serialManagerReadHandle);
+ * @endcode
+ *
+ * @param name The name string of the serial manager read handle.
+ */
+#define SERIAL_MANAGER_READ_HANDLE_DEFINE(name) \
+    uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+#define SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(name) \
+    uint32_t name[((SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+/*! @brief Macro to set serial manager task priority. */
+#ifndef SERIAL_MANAGER_TASK_PRIORITY
+#define SERIAL_MANAGER_TASK_PRIORITY (2U)
+#endif
+
+/*! @brief Macro to set serial manager task stack size. */
+#ifndef SERIAL_MANAGER_TASK_STACK_SIZE
+#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
+#endif
+
+/*! @brief The handle of the serial manager module */
+typedef void *serial_handle_t;
+
+/*! @brief The write handle of the serial manager module */
+typedef void *serial_write_handle_t;
+
+/*! @brief The read handle of the serial manager module */
+typedef void *serial_read_handle_t;
+
+#ifndef _SERIAL_PORT_T_
+#define _SERIAL_PORT_T_
+/*! @brief serial port type*/
+typedef enum _serial_port_type
+{
+    kSerialPort_None = 0U, /*!< Serial port is none */
+    kSerialPort_Uart = 1U, /*!< Serial port UART */
+    kSerialPort_UsbCdc,    /*!< Serial port USB CDC */
+    kSerialPort_Swo,       /*!< Serial port SWO */
+    kSerialPort_Virtual,   /*!< Serial port Virtual */
+    kSerialPort_Rpmsg,     /*!< Serial port RPMSG */
+    kSerialPort_UartDma,   /*!< Serial port UART DMA*/
+    kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/
+    kSerialPort_SpiSlave,  /*!< Serial port SPISLAVE*/
+    kSerialPort_BleWu,     /*!< Serial port BLE WU */
+} serial_port_type_t;
+#endif
+
+/*! @brief serial manager type*/
+typedef enum _serial_manager_type
+{
+    kSerialManager_NonBlocking = 0x0U,    /*!< None blocking handle*/
+    kSerialManager_Blocking    = 0x8F41U, /*!< Blocking handle*/
+} serial_manager_type_t;
+/*! @brief serial manager config structure*/
+typedef struct _serial_manager_config
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    uint8_t *ringBuffer;             /*!< Ring buffer address, it is used to buffer data received by the hardware.
+                                          Besides, the memory space cannot be free during the lifetime of the serial
+                                          manager module. */
+    uint32_t ringBufferSize;         /*!< The size of the ring buffer */
+#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
+    osa_task_def_t *serialTaskConfig;  /*!< Serial manager task configuration, can be defined the serial manager 
+                                            task configuration for this instance, if serialTaskConfig is NULL, will use the 
+                                            default serial manager configure provided by serial manger module.*/
+#endif
+#endif
+    serial_port_type_t type;         /*!< Serial port type */
+    serial_manager_type_t blockType; /*!< Serial manager port type */
+    void *portConfig;                /*!< Serial port configuration */
+} serial_manager_config_t;
+
+/*! @brief serial manager error code*/
+typedef enum _serial_manager_status
+{
+    kStatus_SerialManager_Success = kStatus_Success,                            /*!< Success */
+    kStatus_SerialManager_Error   = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
+    kStatus_SerialManager_Busy    = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
+    kStatus_SerialManager_Notify  = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
+    kStatus_SerialManager_Canceled =
+        MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
+    kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
+    kStatus_SerialManager_RingBufferOverflow =
+        MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
+    kStatus_SerialManager_NotConnected = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 7), /*!< The host is not connected */
+} serial_manager_status_t;
+
+/*! @brief Callback message structure */
+typedef struct _serial_manager_callback_message
+{
+    uint8_t *buffer; /*!< Transferred buffer */
+    uint32_t length; /*!< Transferred data length */
+} serial_manager_callback_message_t;
+
+/*! @brief serial manager callback function */
+typedef void (*serial_manager_callback_t)(void *callbackParam,
+                                          serial_manager_callback_message_t *message,
+                                          serial_manager_status_t status);
+
+/*! @brief serial manager Lowpower Critical callback function */
+typedef int32_t (*serial_manager_lowpower_critical_callback_t)(int32_t power_mode);
+typedef struct _serial_manager_lowpower_critical_CBs_t
+{
+    serial_manager_lowpower_critical_callback_t serialEnterLowpowerCriticalFunc;
+    serial_manager_lowpower_critical_callback_t serialExitLowpowerCriticalFunc;
+} serial_manager_lowpower_critical_CBs_t;
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
+ *
+ * This function configures the Serial Manager module with user-defined settings.
+ * The user can configure the configuration structure.
+ * The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
+ * allocated by the caller.
+ * The Serial Manager module supports three types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc), USB
+ * CDC and swo.
+ * Please refer to #serial_port_type_t for serial port setting.
+ * These three types can be set by using #serial_manager_config_t.
+ *
+ * Example below shows how to use this API to configure the Serial Manager.
+ * For UART,
+ *  @code
+ *   #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ *   static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
+ *   static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ *   serial_manager_config_t config;
+ *   serial_port_uart_config_t uartConfig;
+ *   config.type = kSerialPort_Uart;
+ *   config.ringBuffer = &s_ringBuffer[0];
+ *   config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ *   uartConfig.instance = 0;
+ *   uartConfig.clockRate = 24000000;
+ *   uartConfig.baudRate = 115200;
+ *   uartConfig.parityMode = kSerialManager_UartParityDisabled;
+ *   uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
+ *   uartConfig.enableRx = 1;
+ *   uartConfig.enableTx = 1;
+ *   uartConfig.enableRxRTS = 0;
+ *   uartConfig.enableTxCTS = 0;
+ *   config.portConfig = &uartConfig;
+ *   SerialManager_Init((serial_handle_t)s_serialHandle, &config);
+ *  @endcode
+ * For USB CDC,
+ *  @code
+ *   #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ *   static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
+ *   static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ *   serial_manager_config_t config;
+ *   serial_port_usb_cdc_config_t usbCdcConfig;
+ *   config.type = kSerialPort_UsbCdc;
+ *   config.ringBuffer = &s_ringBuffer[0];
+ *   config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ *   usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
+ *   config.portConfig = &usbCdcConfig;
+ *   SerialManager_Init((serial_handle_t)s_serialHandle, &config);
+ *  @endcode
+ *
+ * Example below shows how to use this API to configure the Serial Manager task configuration.
+ * For example if user need do specfical configuration(s_os_thread_def_serialmanager)for the
+ * serial mananger task,
+ *  @code
+ *   #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ *   static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
+ *   static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *   const osa_task_def_t s_os_thread_def_serialmanager = {
+ *       .tpriority = 4,
+ *       .instances = 1,
+ *       .stacksize = 2048,
+ *   };
+ *   serial_manager_config_t config;
+ *   serial_port_uart_config_t uartConfig;
+ *   config.type = kSerialPort_Uart;
+ *   config.ringBuffer = &s_ringBuffer[0];
+ *   config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ *   config.serialTaskConfig = (osa_task_def_t *)&s_os_thread_def_serialmanager,
+ *   uartConfig.instance = 0;
+ *   uartConfig.clockRate = 24000000;
+ *   uartConfig.baudRate = 115200;
+ *   uartConfig.parityMode = kSerialManager_UartParityDisabled;
+ *   uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
+ *   uartConfig.enableRx = 1;
+ *   uartConfig.enableTx = 1;
+ *   uartConfig.enableRxRTS = 0;
+ *   uartConfig.enableTxCTS = 0;
+ *   config.portConfig = &uartConfig;
+ *   SerialManager_Init((serial_handle_t)s_serialHandle, &config);
+ *  @endcode
+ * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #SERIAL_MANAGER_HANDLE_DEFINE(serialHandle);
+ * or
+ * uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param serialConfig Pointer to user-defined configuration structure.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
+ */
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig);
+
+/*!
+ * @brief De-initializes the serial manager module instance.
+ *
+ * This function de-initializes the serial manager module instance. If the opened writing or
+ * reading handle is not closed, the function will return kStatus_SerialManager_Busy.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
+ * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
+ */
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
+
+/*!
+ * @brief Opens a writing handle for the serial manager module.
+ *
+ * This function Opens a writing handle for the serial manager module. If the serial manager needs to
+ * be used in different tasks, the task should open a dedicated write handle for itself by calling
+ * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
+ * handle at the same time, multiple writing handles need to be opened when the multiple transmission
+ * is needed for a task.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * @param writeHandle The serial manager module writing handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #SERIAL_MANAGER_WRITE_HANDLE_DEFINE(writeHandle);
+ * or
+ * uint32_t writeHandle[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
+ * @retval kStatus_SerialManager_Success The writing handle is opened.
+ *
+ * Example below shows how to use this API to write data.
+ * For task 1,
+ *  @code
+ *   static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle1);
+ *   static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
+ *   SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle1);
+ *   SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle1,
+ *                                    Task1_SerialManagerTxCallback,
+ *                                    s_serialWriteHandle1);
+ *   SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle1,
+ *                                   s_nonBlockingWelcome1,
+ *                                   sizeof(s_nonBlockingWelcome1) - 1U);
+ *  @endcode
+ * For task 2,
+ *  @code
+ *   static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle2);
+ *   static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
+ *   SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle2);
+ *   SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle2,
+ *                                    Task2_SerialManagerTxCallback,
+ *                                    s_serialWriteHandle2);
+ *   SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle2,
+ *                                   s_nonBlockingWelcome2,
+ *                                   sizeof(s_nonBlockingWelcome2) - 1U);
+ *  @endcode
+ */
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Closes a writing handle for the serial manager module.
+ *
+ * This function Closes a writing handle for the serial manager module.
+ *
+ * @param writeHandle The serial manager module writing handle pointer.
+ * @retval kStatus_SerialManager_Success The writing handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Opens a reading handle for the serial manager module.
+ *
+ * This function Opens a reading handle for the serial manager module. The reading handle can not be
+ * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
+ * the previous reading handle is not closed. And there can only be one buffer for receiving for the
+ * reading handle at the same time.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * @param readHandle The serial manager module reading handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #SERIAL_MANAGER_READ_HANDLE_DEFINE(readHandle);
+ * or
+ * uint32_t readHandle[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The reading handle is opened.
+ * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
+ *
+ * Example below shows how to use this API to read data.
+ *  @code
+ *   static SERIAL_MANAGER_READ_HANDLE_DEFINE(s_serialReadHandle);
+ *   SerialManager_OpenReadHandle((serial_handle_t)serialHandle, (serial_read_handle_t)s_serialReadHandle);
+ *   static uint8_t s_nonBlockingBuffer[64];
+ *   SerialManager_InstallRxCallback((serial_read_handle_t)s_serialReadHandle,
+ *                                    APP_SerialManagerRxCallback,
+ *                                    s_serialReadHandle);
+ *   SerialManager_ReadNonBlocking((serial_read_handle_t)s_serialReadHandle,
+ *                                  s_nonBlockingBuffer,
+ *                                  sizeof(s_nonBlockingBuffer));
+ *  @endcode
+ */
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
+
+/*!
+ * @brief Closes a reading for the serial manager module.
+ *
+ * This function Closes a reading for the serial manager module.
+ *
+ * @param readHandle The serial manager module reading handle pointer.
+ * @retval kStatus_SerialManager_Success The reading handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Transmits data with the blocking mode.
+ *
+ * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function SerialManager_WriteNonBlocking
+ * cannot be used at the same time.
+ * And, the function SerialManager_CancelWriting cannot be used to abort the transmission of this function.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
+                                                    uint8_t *buffer,
+                                                    uint32_t length);
+
+/*!
+ * @brief Reads data with the blocking mode.
+ *
+ * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function SerialManager_ReadNonBlocking
+ * cannot be used at the same time.
+ * And, the function SerialManager_CancelReading cannot be used to abort the transmission of this function.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief Transmits data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be sent.
+ * When all data is sent, the module notifies the upper layer through a TX callback function and passes
+ * the status parameter @ref kStatus_SerialManager_Success.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+                                                       uint8_t *buffer,
+                                                       uint32_t length);
+
+/*!
+ * @brief Reads data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be received.
+ * When all data is received, the module driver notifies the upper layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
+                                                      uint8_t *buffer,
+                                                      uint32_t length);
+
+/*!
+ * @brief Tries to read data.
+ *
+ * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
+ * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
+ * After the data is copied, the actual data length is passed by the parameter length.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @param receivedLength Length received from the ring buffer directly.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+                                              uint8_t *buffer,
+                                              uint32_t length,
+                                              uint32_t *receivedLength);
+
+/*!
+ * @brief Cancels unfinished send transmission.
+ *
+ * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
+ * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
+ * the function #SerialManager_WriteBlocking.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the sending.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Cancels unfinished receive transmission.
+ *
+ * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
+ * layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
+ * the function #SerialManager_ReadBlocking.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the receiving.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Installs a TX callback and callback parameter.
+ *
+ * This function is used to install the TX callback and callback parameter for the serial manager module.
+ * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam);
+
+/*!
+ * @brief Installs a RX callback and callback parameter.
+ *
+ * This function is used to install the RX callback and callback parameter for the serial manager module.
+ * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam);
+
+/*!
+ * @brief Check if need polling ISR.
+ *
+ * This function is used to check if need polling ISR.
+ *
+ * @retval TRUE if need polling.
+ */
+static inline bool SerialManager_needPollingIsr(void)
+{
+#if (defined(__DSC__) && defined(__CW__))
+    return !(isIRQAllowed());
+#elif defined(CPSR_M_Msk)
+    return (0x13 == (__get_CPSR() & CPSR_M_Msk));
+#elif defined(DAIF_I_BIT)
+    return (__get_DAIF() & DAIF_I_BIT);
+#elif defined(__XCC__)
+    return (xthal_get_interrupt() & xthal_get_intenable());
+#else
+    return (0U != __get_IPSR());
+#endif
+}
+#endif
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
+
+/*!
+ * @brief This function performs initialization of the callbacks structure used to disable lowpower
+ *          when serial manager is active.
+ *
+ *
+ * @param  pfCallback Pointer to the function structure used to allow/disable lowpower.
+ *
+ */
+void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback);
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif /* __SERIAL_MANAGER_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_internal.h
new file mode 100644
index 0000000000..7995090e54
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_internal.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2019-2020, 2023-2024 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_INTERNAL_H__
+#define __SERIAL_PORT_INTERNAL_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam);
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam);
+void Serial_UartIsrFunction(serial_handle_t serialHandle);
+#endif
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);
+#endif
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam);
+serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam);
+void Serial_UartDmaIsrFunction(serial_handle_t serialHandle);
+#endif
+serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
+serial_manager_status_t Serial_RpmsgInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_RpmsgDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_RpmsgWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_RpmsgWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_RpmsgRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_RpmsgCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_RpmsgInstallTxCallback(serial_handle_t serialHandle,
+                                                      serial_manager_callback_t callback,
+                                                      void *callbackParam);
+serial_manager_status_t Serial_RpmsgInstallRxCallback(serial_handle_t serialHandle,
+                                                      serial_manager_callback_t callback,
+                                                      void *callbackParam);
+#endif
+serial_manager_status_t Serial_RpmsgEnterLowpower(serial_handle_t serialHandle);
+serial_manager_status_t Serial_RpmsgExitLowpower(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
+                                                       serial_manager_callback_t callback,
+                                                       void *callbackParam);
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
+                                                       serial_manager_callback_t callback,
+                                                       void *callbackParam);
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcGetConnectedStatus(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
+                                                    serial_manager_callback_t callback,
+                                                    void *callbackParam);
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
+                                                    serial_manager_callback_t callback,
+                                                    void *callbackParam);
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+serial_manager_status_t Serial_PortVirtualInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_PortVirtualDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_PortVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_PortVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_PortVirtualCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_PortVirtualInstallTxCallback(serial_handle_t serialHandle,
+                                                            serial_manager_callback_t callback,
+                                                            void *callbackParam);
+serial_manager_status_t Serial_PortVirtualInstallRxCallback(serial_handle_t serialHandle,
+                                                            serial_manager_callback_t callback,
+                                                            void *callbackParam);
+void Serial_PortVirtualIsrFunction(serial_handle_t serialHandle);
+#endif
+#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && SERIAL_PORT_TYPE_SPI_MASTER > 0U)
+serial_manager_status_t Serial_SpiMasterInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_SpiMasterDeinit(serial_handle_t serialHandle);
+void Serial_SpiMasterTxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam);
+void Serial_SpiMasterRxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam);
+serial_manager_status_t Serial_SpiMasterWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_SpiMasterRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SpiMasterInstallTxCallback(serial_handle_t serialHandle,
+                                                          serial_manager_callback_t callback,
+                                                          void *callbackParam);
+serial_manager_status_t Serial_SpiMasterInstallRxCallback(serial_handle_t serialHandle,
+                                                          serial_manager_callback_t callback,
+                                                          void *callbackParam);
+serial_manager_status_t Serial_SpiMasterCancelWrite(serial_handle_t serialHandle);
+
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
+serial_manager_status_t Serial_SpiSlaveInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_SpiSlaveDeinit(serial_handle_t serialHandle);
+void Serial_SpiSlaveTxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam);
+void Serial_SpiSlaveRxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam);
+serial_manager_status_t Serial_SpiSlaveWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_SpiSlaveRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SpiSlaveInstallTxCallback(serial_handle_t serialHandle,
+                                                         serial_manager_callback_t callback,
+                                                         void *callbackParam);
+serial_manager_status_t Serial_SpiSlaveInstallRxCallback(serial_handle_t serialHandle,
+                                                         serial_manager_callback_t callback,
+                                                         void *callbackParam);
+serial_manager_status_t Serial_SpiSlaveCancelWrite(serial_handle_t serialHandle);
+
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+serial_manager_status_t Serial_PortBleWuInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_PortBleWuDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_PortBleWuWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_PortBleWuRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_PortBleWuCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_PortBleWuInstallTxCallback(serial_handle_t serialHandle,
+                                                          serial_manager_callback_t callback,
+                                                          void *callbackParam);
+serial_manager_status_t Serial_PortBleWuInstallRxCallback(serial_handle_t serialHandle,
+                                                          serial_manager_callback_t callback,
+                                                          void *callbackParam);
+void Serial_PortBleWuIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __SERIAL_PORT_INTERNAL_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_uart.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_uart.c
new file mode 100644
index 0000000000..ff33d27724
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_uart.c
@@ -0,0 +1,713 @@
+/*
+ * Copyright 2018 -2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_component_serial_manager.h"
+#include "fsl_component_serial_port_internal.h"
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) || \
+    (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+#include "fsl_adapter_uart.h"
+
+#include "fsl_component_serial_port_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#else
+/* MISRA C-2012 Rule 17.2 */
+#undef assert
+#define assert(n) \
+    while (!(n))  \
+    {             \
+        ;         \
+    }
+#endif
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
+typedef struct _serial_uart_send_state
+{
+    uint8_t *buffer;
+    uint32_t length;
+    serial_manager_callback_t callback;
+    void *callbackParam;
+    volatile uint8_t busy;
+} serial_uart_send_state_t;
+
+typedef struct _serial_uart_recv_state
+{
+    serial_manager_callback_t callback;
+    void *callbackParam;
+    volatile uint8_t busy;
+    volatile uint8_t rxEnable;
+    uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
+} serial_uart_recv_state_t;
+
+typedef struct _serial_uart_dma_recv_state
+{
+    serial_manager_callback_t callback;
+    void *callbackParam;
+    volatile uint8_t busy;
+    volatile uint8_t rxEnable;
+    uint8_t readBuffer[SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH];
+} serial_uart_dma_recv_state_t;
+
+typedef struct _serial_uart_block_state
+{
+    UART_HANDLE_DEFINE(usartHandleBuffer);
+} serial_uart_block_state_t;
+#endif
+
+typedef struct _serial_uart_state
+{
+    UART_HANDLE_DEFINE(usartHandleBuffer);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_uart_send_state_t tx;
+    serial_uart_recv_state_t rx;
+#endif
+} serial_uart_state_t;
+#endif
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+typedef struct _serial_uart_dma_state
+{
+    UART_HANDLE_DEFINE(usartHandleBuffer);
+    UART_DMA_HANDLE_DEFINE(uartDmaHandle);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_uart_send_state_t tx;
+    serial_uart_dma_recv_state_t rx;
+#endif
+} serial_uart_dma_state_t;
+#endif
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static serial_manager_status_t Serial_UartEnableReceiving(serial_uart_state_t *serialUartHandle)
+{
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    hal_uart_transfer_t transfer;
+#endif
+    if (1U == serialUartHandle->rx.rxEnable)
+    {
+        serialUartHandle->rx.busy = 1U;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+        transfer.data     = &serialUartHandle->rx.readBuffer[0];
+        transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+        if (kStatus_HAL_UartSuccess !=
+            HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+        if (kStatus_HAL_UartSuccess !=
+            HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                       &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+        {
+            serialUartHandle->rx.busy = 0U;
+            return kStatus_SerialManager_Error;
+        }
+    }
+    return kStatus_SerialManager_Success;
+}
+
+/* UART user callback */
+static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
+{
+    serial_uart_state_t *serialUartHandle;
+    serial_manager_callback_message_t serialMsg;
+
+    assert(userData);
+    serialUartHandle = (serial_uart_state_t *)userData;
+
+    if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
+    {
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+        (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+        (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+        if ((NULL != serialUartHandle->rx.callback))
+        {
+            serialMsg.buffer = &serialUartHandle->rx.readBuffer[0];
+            serialMsg.length = sizeof(serialUartHandle->rx.readBuffer);
+            serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &serialMsg,
+                                          kStatus_SerialManager_Success);
+        }
+    }
+    else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
+    {
+        if (0U != serialUartHandle->tx.busy)
+        {
+            serialUartHandle->tx.busy = 0U;
+            if ((NULL != serialUartHandle->tx.callback))
+            {
+                serialMsg.buffer = serialUartHandle->tx.buffer;
+                serialMsg.length = serialUartHandle->tx.length;
+                serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
+                                              kStatus_SerialManager_Success);
+            }
+        }
+    }
+    else
+    {
+    }
+}
+#endif
+
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
+{
+    serial_uart_state_t *serialUartHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_port_uart_config_t *uartConfig = (serial_port_uart_config_t *)serialConfig;
+#endif
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+#if 0 /* Not used below! */
+    hal_uart_transfer_t transfer;
+#endif
+#endif
+#endif
+
+    assert(serialConfig);
+    assert(serialHandle);
+    assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
+
+    serialUartHandle    = (serial_uart_state_t *)serialHandle;
+    serialManagerStatus = (serial_manager_status_t)HAL_UartInit(
+        ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig);
+    assert(kStatus_SerialManager_Success == serialManagerStatus);
+    (void)serialManagerStatus;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serialUartHandle->rx.rxEnable = uartConfig->enableRx;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+    (void)HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                          Serial_UartCallback, serialUartHandle);
+#else
+    (void)HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), Serial_UartCallback,
+                                  serialUartHandle);
+#endif
+#endif
+
+    return serialManagerStatus;
+}
+
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+    (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+#endif
+    (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serialUartHandle->tx.busy = 0U;
+    serialUartHandle->rx.busy = 0U;
+#endif
+
+    return kStatus_SerialManager_Success;
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_uart_state_t *serialUartHandle;
+    hal_uart_status_t uartstatus;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    hal_uart_transfer_t transfer;
+#endif
+
+    assert(serialHandle);
+    assert(buffer);
+    assert(length);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+    if (0U != serialUartHandle->tx.busy)
+    {
+        return kStatus_SerialManager_Busy;
+    }
+    serialUartHandle->tx.busy = 1U;
+
+    serialUartHandle->tx.buffer = buffer;
+    serialUartHandle->tx.length = length;
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    transfer.data     = buffer;
+    transfer.dataSize = length;
+    uartstatus =
+        HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer);
+#else
+
+    uartstatus = HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
+#endif
+    assert(kStatus_HAL_UartSuccess == uartstatus);
+    (void)uartstatus;
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    assert(serialHandle);
+    (void)buffer;
+    (void)length;
+    return (serial_manager_status_t)Serial_UartEnableReceiving(serialHandle);
+}
+
+#else
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+    assert(buffer);
+    assert(length);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                                         buffer, length);
+}
+
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+    assert(buffer);
+    assert(length);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    return (serial_manager_status_t)HAL_UartReceiveBlocking(
+        ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
+}
+
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+    serial_manager_callback_message_t serialMsg;
+    uint32_t primask;
+    uint8_t isBusy = 0U;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    primask                   = DisableGlobalIRQ();
+    isBusy                    = serialUartHandle->tx.busy;
+    serialUartHandle->tx.busy = 0U;
+    EnableGlobalIRQ(primask);
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+    (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+    if (0U != isBusy)
+    {
+        if ((NULL != serialUartHandle->tx.callback))
+        {
+            serialMsg.buffer = serialUartHandle->tx.buffer;
+            serialMsg.length = serialUartHandle->tx.length;
+            serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
+                                          kStatus_SerialManager_Canceled);
+        }
+    }
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    serialUartHandle->tx.callback      = callback;
+    serialUartHandle->tx.callbackParam = callbackParam;
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    serialUartHandle->rx.callback      = callback;
+    serialUartHandle->rx.callbackParam = callbackParam;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    (void)Serial_UartEnableReceiving(serialUartHandle);
+#endif
+    return kStatus_SerialManager_Success;
+}
+
+void Serial_UartIsrFunction(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+}
+#endif
+
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+    hal_uart_status_t uartstatus;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+    assert(kStatus_HAL_UartSuccess == uartstatus);
+    (void)uartstatus;
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+    serial_manager_status_t status = kStatus_SerialManager_Success;
+    hal_uart_status_t uartstatus;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+    assert(kStatus_HAL_UartSuccess == uartstatus);
+    (void)uartstatus;
+
+    return status;
+}
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static serial_manager_status_t Serial_UartDmaEnableReceiving(serial_uart_dma_state_t *serialUartHandle)
+{
+    if (1U == serialUartHandle->rx.rxEnable)
+    {
+        serialUartHandle->rx.busy = 1U;
+        if (kStatus_HAL_UartDmaSuccess !=
+            HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                       &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer),
+                                       false))
+
+        {
+            serialUartHandle->rx.busy = 0U;
+            return kStatus_SerialManager_Error;
+        }
+    }
+    return kStatus_SerialManager_Success;
+}
+
+/* UART user callback */
+static void Serial_UartDmaCallback(hal_uart_dma_handle_t handle, hal_dma_callback_msg_t *dmaMsg, void *callbackParam)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+    serial_manager_callback_message_t cb_msg;
+
+    assert(callbackParam);
+    serialUartHandle = (serial_uart_dma_state_t *)callbackParam;
+
+    if (((hal_uart_dma_status_t)kStatus_HAL_UartDmaRxIdle == dmaMsg->status) ||
+        (kStatus_HAL_UartDmaIdleline == dmaMsg->status))
+    {
+        if ((NULL != serialUartHandle->rx.callback))
+        {
+            cb_msg.buffer = dmaMsg->data;
+            cb_msg.length = dmaMsg->dataSize;
+            serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &cb_msg, kStatus_SerialManager_Success);
+        }
+
+        if (kStatus_HAL_UartDmaSuccess ==
+            HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                       &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer),
+                                       false))
+        {
+            serialUartHandle->rx.busy = 1U;
+        }
+    }
+    else if (kStatus_HAL_UartDmaTxIdle == dmaMsg->status)
+    {
+        if (0U != serialUartHandle->tx.busy)
+        {
+            serialUartHandle->tx.busy = 0U;
+            if ((NULL != serialUartHandle->tx.callback))
+            {
+                cb_msg.buffer = dmaMsg->data;
+                cb_msg.length = dmaMsg->dataSize;
+                serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &cb_msg,
+                                              kStatus_SerialManager_Success);
+            }
+        }
+    }
+    else
+    {
+    }
+}
+
+#endif
+
+serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+    serial_port_uart_dma_config_t *uartConfig = (serial_port_uart_dma_config_t *)serialConfig;
+#endif
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
+
+    assert(serialConfig);
+    assert(serialHandle);
+
+    assert(SERIAL_PORT_UART_DMA_HANDLE_SIZE >= sizeof(serial_uart_dma_state_t));
+
+    serialUartHandle    = (serial_uart_dma_state_t *)serialHandle;
+    serialManagerStatus = (serial_manager_status_t)HAL_UartInit(
+        ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig);
+    assert(kStatus_SerialManager_Success == serialManagerStatus);
+    (void)serialManagerStatus;
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+
+    hal_uart_dma_config_t dmaConfig;
+
+    dmaConfig.uart_instance             = uartConfig->instance;
+    dmaConfig.dma_instance              = uartConfig->dma_instance;
+    dmaConfig.rx_channel                = uartConfig->rx_channel;
+    dmaConfig.tx_channel                = uartConfig->tx_channel;
+    dmaConfig.dma_mux_configure         = uartConfig->dma_mux_configure;
+    dmaConfig.dma_channel_mux_configure = uartConfig->dma_channel_mux_configure;
+
+    // Init uart dma
+    (void)HAL_UartDMAInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                          (hal_uart_dma_handle_t *)serialUartHandle->uartDmaHandle, &dmaConfig);
+
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+    serialUartHandle->rx.rxEnable = uartConfig->enableRx;
+    (void)HAL_UartDMATransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                             Serial_UartDmaCallback, serialUartHandle);
+
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serialManagerStatus = Serial_UartDmaEnableReceiving(serialUartHandle);
+#endif
+
+    return serialManagerStatus;
+}
+
+serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    (void)HAL_UartDMAAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+    (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+    (void)HAL_UartDMADeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serialUartHandle->tx.busy = 0U;
+    serialUartHandle->rx.busy = 0U;
+#endif
+
+    return kStatus_SerialManager_Success;
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+    hal_uart_status_t uartstatus;
+
+    assert(serialHandle);
+    assert(buffer);
+    assert(length);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    if (0U != serialUartHandle->tx.busy)
+    {
+        return kStatus_SerialManager_Busy;
+    }
+    serialUartHandle->tx.busy = 1U;
+
+    serialUartHandle->tx.buffer = buffer;
+    serialUartHandle->tx.length = length;
+
+    uartstatus = (hal_uart_status_t)HAL_UartDMATransferSend(
+        ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
+
+    assert(kStatus_HAL_UartSuccess == uartstatus);
+    (void)uartstatus;
+
+    return kStatus_SerialManager_Success;
+}
+
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+    serial_manager_callback_message_t serialMsg;
+    uint32_t primask;
+    uint8_t isBusy = 0U;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    primask                   = DisableGlobalIRQ();
+    isBusy                    = serialUartHandle->tx.busy;
+    serialUartHandle->tx.busy = 0U;
+    EnableGlobalIRQ(primask);
+
+    (void)HAL_UartDMAAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+    if (0U != isBusy)
+    {
+        if ((NULL != serialUartHandle->tx.callback))
+        {
+            serialMsg.buffer = serialUartHandle->tx.buffer;
+            serialMsg.length = serialUartHandle->tx.length;
+            serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
+                                          kStatus_SerialManager_Canceled);
+        }
+    }
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    serialUartHandle->tx.callback      = callback;
+    serialUartHandle->tx.callbackParam = callbackParam;
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    serialUartHandle->rx.callback      = callback;
+    serialUartHandle->rx.callbackParam = callbackParam;
+
+    return kStatus_SerialManager_Success;
+}
+
+void Serial_UartDmaIsrFunction(serial_handle_t serialHandle)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+}
+#endif
+
+serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+    hal_uart_status_t uartstatus;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+    assert(kStatus_HAL_UartSuccess == uartstatus);
+    (void)uartstatus;
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle)
+{
+    serial_uart_dma_state_t *serialUartHandle;
+    serial_manager_status_t status = kStatus_SerialManager_Success;
+    hal_uart_status_t uartstatus;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
+
+    uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+    assert(kStatus_HAL_UartSuccess == uartstatus);
+    (void)uartstatus;
+
+    return status;
+}
+#endif
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_uart.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_uart.h
new file mode 100644
index 0000000000..ca007452e0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/serial_manager/fsl_component_serial_port_uart.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_UART_H__
+#define __SERIAL_PORT_UART_H__
+
+#include "fsl_adapter_uart.h"
+
+/*!
+ * @addtogroup serial_port_uart
+ * @ingroup serialmanager
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief serial port uart handle size*/
+
+#ifndef SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH
+#define SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH (64U)
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#define SERIAL_PORT_UART_HANDLE_SIZE       (76U + HAL_UART_HANDLE_SIZE)
+#define SERIAL_PORT_UART_BLOCK_HANDLE_SIZE (HAL_UART_BLOCK_HANDLE_SIZE)
+#else
+#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#define SERIAL_PORT_UART_DMA_HANDLE_SIZE (76U + HAL_UART_DMA_HANDLE_SIZE + 132U)
+#endif
+
+#ifndef SERIAL_USE_CONFIGURE_STRUCTURE
+#define SERIAL_USE_CONFIGURE_STRUCTURE (0U) /*!< Enable or disable the confgure structure pointer */
+#endif
+
+/*! @brief serial port uart parity mode*/
+typedef enum _serial_port_uart_parity_mode
+{
+    kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
+    kSerialManager_UartParityEven     = 0x2U, /*!< Parity even enabled */
+    kSerialManager_UartParityOdd      = 0x3U, /*!< Parity odd enabled */
+} serial_port_uart_parity_mode_t;
+
+/*! @brief serial port uart stop bit count*/
+typedef enum _serial_port_uart_stop_bit_count
+{
+    kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
+    kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
+} serial_port_uart_stop_bit_count_t;
+
+typedef struct _serial_port_uart_config
+{
+    uint32_t clockRate;                             /*!< clock rate  */
+    uint32_t baudRate;                              /*!< baud rate  */
+    serial_port_uart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+
+    uint8_t enableRx;                               /*!< Enable RX */
+    uint8_t enableTx;                               /*!< Enable TX */
+    uint8_t enableRxRTS;                            /*!< Enable RX RTS */
+    uint8_t enableTxCTS;                            /*!< Enable TX CTS */
+    uint8_t instance;                               /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
+                                                         please refer to the SOC corresponding RM. */
+
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+    uint8_t txFifoWatermark;
+    uint8_t rxFifoWatermark;
+#endif
+} serial_port_uart_config_t;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+typedef struct _serial_port_uart_dma_config
+{
+    uint32_t clockRate;                             /*!< clock rate  */
+    uint32_t baudRate;                              /*!< baud rate  */
+    serial_port_uart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+
+    uint8_t enableRx;                               /*!< Enable RX */
+    uint8_t enableTx;                               /*!< Enable TX */
+    uint8_t enableRxRTS;                            /*!< Enable RX RTS */
+    uint8_t enableTxCTS;                            /*!< Enable TX CTS */
+    uint8_t instance;                               /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
+                                                         please refer to the SOC corresponding RM. */
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+    uint8_t txFifoWatermark;
+    uint8_t rxFifoWatermark;
+#endif
+    uint8_t dma_instance;
+    uint8_t rx_channel;
+    uint8_t tx_channel;
+    void *dma_mux_configure;
+    void *dma_channel_mux_configure;
+
+} serial_port_uart_dma_config_t;
+#endif
+/*! @} */
+#endif /* __SERIAL_PORT_UART_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/uart/fsl_adapter_uart.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/uart/fsl_adapter_uart.h
new file mode 100644
index 0000000000..32a1af9d38
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/uart/fsl_adapter_uart.h
@@ -0,0 +1,829 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_UART_ADAPTER_H__
+#define __HAL_UART_ADAPTER_H__
+
+#include "fsl_common.h"
+#if defined(SDK_OS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+
+/*!
+ * @addtogroup UART_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
+#else
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (25U)
+#endif
+#else
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#endif
+#else
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
+ * priority is 3 (2^2 - 1). So, the default value is 3.
+ */
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (3U)
+#endif
+#endif
+#endif
+
+#ifndef HAL_UART_ADAPTER_LOWPOWER
+#define HAL_UART_ADAPTER_LOWPOWER (0U)
+#endif /* HAL_UART_ADAPTER_LOWPOWER */
+
+/*! @brief Enable or disable uart hardware FIFO mode (1 - enable, 0 - disable) */
+#ifndef HAL_UART_ADAPTER_FIFO
+#define HAL_UART_ADAPTER_FIFO (1U)
+#endif /* HAL_UART_ADAPTER_FIFO */
+
+#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
+#ifndef HAL_UART_DMA_ENABLE
+#define HAL_UART_DMA_ENABLE (1U)
+#endif
+#endif
+
+#ifndef HAL_UART_DMA_ENABLE
+#define HAL_UART_DMA_ENABLE (0U)
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief Enable or disable uart DMA adapter int mode (1 - enable, 0 - disable) */
+#ifndef HAL_UART_DMA_INIT_ENABLE
+#define HAL_UART_DMA_INIT_ENABLE (1U)
+#endif /* HAL_SPI_MASTER_DMA_INIT_ENABLE */
+
+/*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */
+#ifndef HAL_UART_DMA_IDLELINE_TIMEOUT
+#define HAL_UART_DMA_IDLELINE_TIMEOUT (1U)
+#endif /* HAL_UART_DMA_IDLELINE_TIMEOUT */
+
+/*! @brief Definition of uart adapter handle size. */
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#define HAL_UART_HANDLE_SIZE       (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
+#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
+#else
+#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
+#endif
+
+/*! @brief Definition of uart dma adapter handle size. */
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
+#define HAL_UART_DMA_HANDLE_SIZE (124U + HAL_UART_ADAPTER_LOWPOWER * 36U)
+#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
+#define HAL_UART_DMA_HANDLE_SIZE (140U + HAL_UART_ADAPTER_LOWPOWER * 36U)
+#else
+#error This SOC does not have DMA or EDMA available!
+#endif
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*!
+ * @brief Defines the uart handle
+ *
+ * This macro is used to define a 4 byte aligned uart handle.
+ * Then use "(hal_uart_handle_t)name" to get the uart handle.
+ *
+ * The macro should be global and could be optional. You could also define uart handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * UART_HANDLE_DEFINE(uartHandle);
+ * @endcode
+ *
+ * @param name The name string of the uart handle.
+ */
+#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#define UART_DMA_HANDLE_DEFINE(name) \
+    uint32_t name[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+#endif
+
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
+#ifndef HAL_UART_TRANSFER_MODE
+#define HAL_UART_TRANSFER_MODE (0U)
+#endif
+
+/*! @brief The handle of uart adapter. */
+typedef void *hal_uart_handle_t;
+
+/*! @brief The handle of uart dma adapter. */
+typedef void *hal_uart_dma_handle_t;
+
+/*! @brief UART status */
+typedef enum _hal_uart_status
+{
+    kStatus_HAL_UartSuccess = kStatus_Success,                       /*!< Successfully */
+    kStatus_HAL_UartTxBusy  = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
+    kStatus_HAL_UartRxBusy  = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
+    kStatus_HAL_UartTxIdle  = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
+    kStatus_HAL_UartRxIdle  = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
+    kStatus_HAL_UartBaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
+    kStatus_HAL_UartProtocolError = MAKE_STATUS(
+        kStatusGroup_HAL_UART,
+        6),                                                        /*!< Error occurs for Noise, Framing, Parity, etc.
+                                                                        For transactional transfer, The up layer needs to abort the transfer and then starts again */
+    kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
+} hal_uart_status_t;
+
+/*! @brief UART parity mode. */
+typedef enum _hal_uart_parity_mode
+{
+    kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
+    kHAL_UartParityEven     = 0x2U, /*!< Parity even enabled */
+    kHAL_UartParityOdd      = 0x3U, /*!< Parity odd enabled */
+} hal_uart_parity_mode_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _hal_uart_stop_bit_count
+{
+    kHAL_UartOneStopBit = 0U, /*!< One stop bit */
+    kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
+} hal_uart_stop_bit_count_t;
+
+/*! @brief UART configuration structure. */
+typedef struct _hal_uart_config
+{
+    uint32_t srcClock_Hz;                   /*!< Source clock */
+    uint32_t baudRate_Bps;                  /*!< Baud rate  */
+    hal_uart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    uint8_t enableRx;                       /*!< Enable RX */
+    uint8_t enableTx;                       /*!< Enable TX */
+    uint8_t enableRxRTS;                    /*!< Enable RX RTS */
+    uint8_t enableTxCTS;                    /*!< Enable TX CTS */
+    uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
+                           SOC corresponding RM.
+                           Invalid instance value will cause initialization failure. */
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+    uint8_t txFifoWatermark;
+    uint8_t rxFifoWatermark;
+#endif
+} hal_uart_config_t;
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+/*! @brief UART DMA status */
+typedef enum _hal_uart_dma_status
+{
+    kStatus_HAL_UartDmaSuccess  = 0U,
+    kStatus_HAL_UartDmaRxIdle   = (1U << 1U),
+    kStatus_HAL_UartDmaRxBusy   = (1U << 2U),
+    kStatus_HAL_UartDmaTxIdle   = (1U << 3U),
+    kStatus_HAL_UartDmaTxBusy   = (1U << 4U),
+    kStatus_HAL_UartDmaIdleline = (1U << 5U),
+    kStatus_HAL_UartDmaError    = (1U << 6U),
+} hal_uart_dma_status_t;
+
+typedef struct _dma_mux_configure_t
+{
+    union
+    {
+        struct
+        {
+            uint8_t dma_mux_instance;
+            uint32_t rx_request;
+            uint32_t tx_request;
+        } dma_dmamux_configure;
+    };
+} dma_mux_configure_t;
+typedef struct _dma_channel_mux_configure_t
+{
+    union
+    {
+        struct
+        {
+            uint32_t dma_rx_channel_mux;
+            uint32_t dma_tx_channel_mux;
+        } dma_dmamux_configure;
+    };
+} dma_channel_mux_configure_t;
+
+typedef struct _hal_uart_dma_config_t
+{
+    uint8_t uart_instance;
+    uint8_t dma_instance;
+    uint8_t rx_channel;
+    uint8_t tx_channel;
+    void *dma_mux_configure;
+    void *dma_channel_mux_configure;
+} hal_uart_dma_config_t;
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+typedef struct _dma_callback_msg
+{
+    hal_uart_dma_status_t status;
+    uint8_t *data;
+    uint32_t dataSize;
+} hal_dma_callback_msg_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_dma_transfer_callback_t)(hal_uart_dma_handle_t handle,
+                                                 hal_dma_callback_msg_t *msg,
+                                                 void *callbackParam);
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief UART transfer structure. */
+typedef struct _hal_uart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} hal_uart_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.
+ *
+ * This function configures the UART module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
+ * the caller. Example below shows how to use this API to configure the UART.
+ *  @code
+ *   UART_HANDLE_DEFINE(g_UartHandle);
+ *   hal_uart_config_t config;
+ *   config.srcClock_Hz = 48000000;
+ *   config.baudRate_Bps = 115200U;
+ *   config.parityMode = kHAL_UartParityDisabled;
+ *   config.stopBitCount = kHAL_UartOneStopBit;
+ *   config.enableRx = 1;
+ *   config.enableTx = 1;
+ *   config.enableRxRTS = 0;
+ *   config.enableTxCTS = 0;
+ *   config.instance = 0;
+ *   HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config);
+ *  @endcode
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #UART_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param uart_config Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed
+ */
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
+ */
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
+
+/*! @}*/
+
+/*!
+ * @name Blocking bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the RX register.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ * And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.
+ */
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ * And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.
+ */
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
+
+/*! @}*/
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+/*!
+ * @name Transactional
+ * @note The transactional API and the functional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+                                                  hal_uart_transfer_callback_t callback,
+                                                  void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART driver.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#else
+
+/*!
+ * @name Functional API with non-blocking mode.
+ * @note The functional API and the transactional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+                                          hal_uart_transfer_callback_t callback,
+                                          void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART adapter.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param reCount Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param seCount Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#endif
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+
+/*!
+ * @brief Initializes a UART dma instance with the UART dma handle and the user configuration structure.
+ *
+ * This function configures the UART dma module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated
+ * by the caller. Example below shows how to use this API to configure the UART.
+ *  @code
+ *
+ *  Init TimerManager, only used in UART without Idleline interrupt
+ *  timer_config_t timerConfig;
+ *  timerConfig.srcClock_Hz    = 16000000;
+ *  timerConfig.instance       = 0;
+ *  TM_Init(&timerConfig);
+ *
+ *  Init the DMA module
+ *  DMA_Init(DMA0);
+ *
+ *  Define a uart dma handle
+ *  UART_HANDLE_DEFINE(g_uartHandle);
+ *  UART_DMA_HANDLE_DEFINE(g_UartDmaHandle);
+ *
+ *  Configure uart settings
+ *  hal_uart_config_t uartConfig;
+ *  uartConfig.srcClock_Hz  = 48000000;
+ *  uartConfig.baudRate_Bps = 115200;
+ *  uartConfig.parityMode   = kHAL_UartParityDisabled;
+ *  uartConfig.stopBitCount = kHAL_UartOneStopBit;
+ *  uartConfig.enableRx     = 1;
+ *  uartConfig.enableTx     = 1;
+ *  uartConfig.enableRxRTS  = 0;
+ *  uartConfig.enableTxCTS  = 0;
+ *  uartConfig.instance     = 0;
+ *
+ *  Init uart
+ *  HAL_UartInit((hal_uart_handle_t *)g_uartHandle, &uartConfig);
+ *
+ *  Configure uart dma settings
+ *  hal_uart_dma_config_t dmaConfig;
+ *  dmaConfig.uart_instance = 0;
+ *  dmaConfig.dma_instance  = 0;
+ *  dmaConfig.rx_channel    = 0;
+ *  dmaConfig.tx_channel    = 1;
+ *
+ *  Init uart dma
+ *  HAL_UartDMAInit((hal_uart_handle_t *)g_uartHandle, (hal_uart_dma_handle_t *)g_uartDmaHandle, &dmaConfig);
+ *  @endcode
+ *
+ * @param handle UART handle pointer.
+ * @param dmaHandle Pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #UART_DMA_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param dmaConfig Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartDmaError UART dma initialization failed.
+ * @retval kStatus_HAL_UartDmaSuccess UART dma initialization succeed.
+ */
+hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
+                                      hal_uart_dma_handle_t dmaHandle,
+                                      hal_uart_dma_config_t *dmaConfig);
+
+/*!
+ * @brief Deinitializes a UART DMA instance.
+ *
+ * This function will abort uart dma receive/send transfer and deinitialize UART.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartDmaSuccess UART DMA de-initialization succeed
+ */
+hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle);
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART DMA module.
+ * When any status of the UART DMA changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully install the callback.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
+                                                         hal_uart_dma_transfer_callback_t callback,
+                                                         void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an dma method.
+ *
+ * This function receives data using an dma method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART DMA driver.
+ * When all data is received, the UART DMA adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_HAL_UartDmaRxIdle.
+ *
+ * When an idleline is detected, the UART DMA adapter notifies the upper layer through a callback function,
+ * and passes the status parameter @ref kStatus_HAL_UartDmaIdleline. For the UARTs without hardware idleline
+ * interrupt(like usart), it will use a software idleline detection method with the help of TimerManager.
+ *
+ * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
+ *
+ * @param handle UART handle pointer.
+ * @param data data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @param receiveAll Idleline interrupt will not end transfer process if set true.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully start the data receive.
+ * @retval kStatus_HAL_UartDmaRxBusy Previous receive request is not finished.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
+                                                 uint8_t *data,
+                                                 size_t length,
+                                                 bool receiveAll);
+
+/*!
+ * @brief Transmits a buffer of data using an dma method.
+ *
+ * This function sends data using an dma method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register by DMA, the UART DMA driver calls the callback
+ * function and passes the @ref kStatus_HAL_UartDmaTxIdle as status parameter.
+ *
+ * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
+ *
+ * @param handle UART handle pointer.
+ * @param data data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartDmaTxBusy Previous send request is not finished.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param reCount Receive bytes count.
+ * @retval kStatus_HAL_UartDmaError An error occurred.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p reCount.
+ */
+hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the DMA method.
+ *
+ * @param handle UART handle pointer.
+ * @param seCount Send bytes count.
+ * @retval kStatus_HAL_UartDmaError An error occurred.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount.
+ */
+hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the DMA-driven data receiving.
+ *
+ * This function aborts the DMA-driven data receiving.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully abort the receiving.
+ */
+hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the DMA-driven data sending.
+ *
+ * This function aborts the DMA-driven data sending.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle);
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param handle UART handle pointer.
+ */
+void HAL_UartIsrFunction(hal_uart_handle_t handle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __HAL_UART_ADAPTER_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/uart/fsl_adapter_usart.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/uart/fsl_adapter_usart.c
new file mode 100644
index 0000000000..59641f6102
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/uart/fsl_adapter_usart.c
@@ -0,0 +1,1101 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_usart.h"
+#include "fsl_flexcomm.h"
+
+#include "fsl_adapter_uart.h"
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#include "fsl_component_timer_manager.h"
+#include "fsl_usart_dma.h"
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_dma_receive_state
+{
+    uint8_t *volatile buffer;
+    volatile uint32_t bufferLength;
+    volatile uint32_t bufferSofar;
+    volatile uint32_t timeout;
+    volatile bool receiveAll;
+} hal_uart_dma_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_dma_send_state
+{
+    uint8_t *volatile buffer;
+    volatile uint32_t bufferLength;
+    volatile uint32_t bufferSofar;
+    volatile uint32_t timeout;
+} hal_uart_dma_send_state_t;
+
+typedef struct _hal_uart_dma_state
+{
+    struct _hal_uart_dma_state *next;
+    uint8_t instance; /* USART instance */
+    hal_uart_dma_transfer_callback_t dma_callback;
+    void *dma_callback_param;
+    usart_dma_handle_t dmaHandle;
+    dma_handle_t txDmaHandle;
+    dma_handle_t rxDmaHandle;
+    hal_uart_dma_receive_state_t dma_rx;
+    hal_uart_dma_send_state_t dma_tx;
+} hal_uart_dma_state_t;
+
+typedef struct _uart_dma_list
+{
+    TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle);
+    hal_uart_dma_state_t *dma_list;
+    volatile int8_t activeCount;
+} hal_uart_dma_list_t;
+
+static hal_uart_dma_list_t s_dmaHandleList;
+#endif /* HAL_UART_DMA_ENABLE */
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+    volatile uint8_t *buffer;
+    volatile uint32_t bufferLength;
+    volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+    volatile uint8_t *buffer;
+    volatile uint32_t bufferLength;
+    volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+    hal_uart_transfer_callback_t callback;
+    void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    usart_handle_t hardwareHandle;
+#endif
+    hal_uart_receive_state_t rx;
+    hal_uart_send_state_t tx;
+#endif
+    uint8_t instance;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+    hal_uart_dma_state_t *dmaHandle;
+#endif /* HAL_UART_DMA_ENABLE */
+#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
+    hal_uart_config_t config;
+#endif
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of USART IRQ number. */
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \
+     (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+    hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+    switch (status)
+    {
+        case kStatus_Success:
+            uartStatus = kStatus_HAL_UartSuccess;
+            break;
+        case kStatus_USART_TxBusy:
+            uartStatus = kStatus_HAL_UartTxBusy;
+            break;
+        case kStatus_USART_RxBusy:
+            uartStatus = kStatus_HAL_UartRxBusy;
+            break;
+        case kStatus_USART_TxIdle:
+            uartStatus = kStatus_HAL_UartTxIdle;
+            break;
+        case kStatus_USART_RxIdle:
+            uartStatus = kStatus_HAL_UartRxIdle;
+            break;
+        case kStatus_USART_BaudrateNotSupport:
+            uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+            break;
+        case kStatus_USART_NoiseError:
+        case kStatus_USART_FramingError:
+        case kStatus_USART_ParityError:
+            uartStatus = kStatus_HAL_UartProtocolError;
+            break;
+        default:
+            /* This comments for MISRA C-2012 Rule 16.4 */
+            break;
+    }
+    return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+    if (kStatus_Success == status)
+    {
+        return kStatus_HAL_UartSuccess;
+    }
+    else
+    {
+        return kStatus_HAL_UartError;
+    }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+    assert(callbackParam);
+
+    uartHandle = (hal_uart_state_t *)callbackParam;
+
+    if (kStatus_HAL_UartProtocolError == uartStatus)
+    {
+        if (0U != uartHandle->hardwareHandle.rxDataSize)
+        {
+            uartStatus = kStatus_HAL_UartError;
+        }
+    }
+
+    if (NULL != uartHandle->callback)
+    {
+        uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+    }
+}
+
+#else
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
+{
+    hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
+    uint32_t status;
+    uint8_t instance;
+
+    if (NULL == uartHandle)
+    {
+        return;
+    }
+    instance = uartHandle->instance;
+
+    status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
+
+    /* Receive data register full */
+    if ((0U != (USART_FIFOSTAT_RXNOTEMPTY_MASK & status)) &&
+        (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK)))
+    {
+        if (NULL != uartHandle->rx.buffer)
+        {
+            uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
+            if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+            {
+                USART_DisableInterrupts(s_UsartAdapterBase[instance],
+                                        USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+                uartHandle->rx.buffer = NULL;
+                if (NULL != uartHandle->callback)
+                {
+                    uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+                }
+            }
+        }
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((0U != (USART_FIFOSTAT_TXNOTFULL_MASK & status)) &&
+        (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK)))
+    {
+        if (NULL != uartHandle->tx.buffer)
+        {
+            USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+            if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+            {
+                USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
+                uartHandle->tx.buffer = NULL;
+                if (NULL != uartHandle->callback)
+                {
+                    uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+                }
+            }
+        }
+    }
+
+#if 1
+    USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
+#endif
+}
+
+static void HAL_UartInterruptHandle_Wapper(void *base, void *handle)
+{
+    HAL_UartInterruptHandle((USART_Type *)base, handle);
+}
+#endif
+
+#endif
+
+static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *config)
+{
+    usart_config_t usartConfig;
+    status_t status;
+
+    assert(handle);
+    assert(config);
+    assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
+    assert(s_UsartAdapterBase[config->instance]);
+    assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t));
+
+    USART_GetDefaultConfig(&usartConfig);
+    usartConfig.baudRate_Bps = config->baudRate_Bps;
+
+    if ((0U != config->enableRxRTS) || (0U != config->enableTxCTS))
+    {
+        usartConfig.enableHardwareFlowControl = true;
+    }
+
+    if (kHAL_UartParityEven == config->parityMode)
+    {
+        usartConfig.parityMode = kUSART_ParityEven;
+    }
+    else if (kHAL_UartParityOdd == config->parityMode)
+    {
+        usartConfig.parityMode = kUSART_ParityOdd;
+    }
+    else
+    {
+        usartConfig.parityMode = kUSART_ParityDisabled;
+    }
+
+    if (kHAL_UartTwoStopBit == config->stopBitCount)
+    {
+        usartConfig.stopBitCount = kUSART_TwoStopBit;
+    }
+    else
+    {
+        usartConfig.stopBitCount = kUSART_OneStopBit;
+    }
+    usartConfig.enableRx    = (bool)config->enableRx;
+    usartConfig.enableTx    = (bool)config->enableTx;
+    usartConfig.txWatermark = kUSART_TxFifo0;
+    usartConfig.rxWatermark = kUSART_RxFifo1;
+
+    status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
+
+    if (kStatus_Success != status)
+    {
+        return HAL_UartGetStatus(status);
+    }
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_status_t status;
+
+    /* Init serial port */
+    status = HAL_UartInitCommon(handle, uart_config);
+    if (kStatus_HAL_UartSuccess != status)
+    {
+        return status;
+    }
+
+    uartHandle           = (hal_uart_state_t *)handle;
+    uartHandle->instance = uart_config->instance;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+    uartHandle->dmaHandle = NULL;
+#endif /* HAL_UART_DMA_ENABLE */
+#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
+    (void)memcpy(&uartHandle->config, uart_config, sizeof(hal_uart_config_t));
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    USART_TransferCreateHandle(s_UsartAdapterBase[uart_config->instance], &uartHandle->hardwareHandle,
+                               (usart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+    /* Enable interrupt in NVIC. */
+    FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[uart_config->instance], HAL_UartInterruptHandle_Wapper, handle);
+    NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uart_config->instance], HAL_UART_ISR_PRIORITY);
+    (void)EnableIRQ(s_UsartIRQ[uart_config->instance]);
+#endif
+
+#endif
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+
+    assert(handle);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(data);
+    assert(length);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+    if (NULL != uartHandle->rx.buffer)
+    {
+        return kStatus_HAL_UartRxBusy;
+    }
+#endif
+
+    status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(data);
+    assert(length);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+    if (NULL != uartHandle->tx.buffer)
+    {
+        return kStatus_HAL_UartTxBusy;
+    }
+#endif
+
+    (void)USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
+{
+    assert(handle);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
+{
+#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    (void)HAL_UartInit(handle, &uartHandle->config);
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+    USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+#endif
+#endif
+    return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+                                                  hal_uart_transfer_callback_t callback,
+                                                  void *callbackParam)
+{
+    hal_uart_state_t *uartHandle;
+
+    assert(handle);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    uartHandle->callbackParam = callbackParam;
+    uartHandle->callback      = callback;
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(transfer);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+                                              (usart_transfer_t *)transfer, NULL);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(transfer);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+                                           (usart_transfer_t *)transfer);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(count);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status =
+        USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(count);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+                                          hal_uart_transfer_callback_t callback,
+                                          void *callbackParam)
+{
+    hal_uart_state_t *uartHandle;
+
+    assert(handle);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    uartHandle->callbackParam = callbackParam;
+    uartHandle->callback      = callback;
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(data);
+    assert(length);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (NULL != uartHandle->rx.buffer)
+    {
+        return kStatus_HAL_UartRxBusy;
+    }
+
+    uartHandle->rx.bufferLength = length;
+    uartHandle->rx.bufferSofar  = 0;
+    uartHandle->rx.buffer       = data;
+    USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(data);
+    assert(length);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (NULL != uartHandle->tx.buffer)
+    {
+        return kStatus_HAL_UartTxBusy;
+    }
+    uartHandle->tx.bufferLength = length;
+    uartHandle->tx.bufferSofar  = 0;
+    uartHandle->tx.buffer       = (volatile uint8_t *)data;
+    USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(reCount);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (NULL != uartHandle->rx.buffer)
+    {
+        *reCount = uartHandle->rx.bufferSofar;
+        return kStatus_HAL_UartSuccess;
+    }
+    return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(seCount);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (NULL != uartHandle->tx.buffer)
+    {
+        *seCount = uartHandle->tx.bufferSofar;
+        return kStatus_HAL_UartSuccess;
+    }
+    return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (NULL != uartHandle->rx.buffer)
+    {
+        USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
+                                USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+        uartHandle->rx.buffer = NULL;
+    }
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (NULL != uartHandle->tx.buffer)
+    {
+        USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
+        uartHandle->tx.buffer = NULL;
+    }
+
+    return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(0U != HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+    DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+    USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+    NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+    EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(0U == HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+    DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+    HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
+#if 0
+    NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+    EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#endif
+
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+static void USART_DMACallbacks(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData)
+{
+    hal_uart_dma_state_t *uartDmaHandle;
+    hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+    hal_dma_callback_msg_t msg;
+    assert(handle);
+
+    uartDmaHandle = (hal_uart_dma_state_t *)userData;
+
+    if (NULL != uartDmaHandle->dma_callback)
+    {
+        if (kStatus_HAL_UartTxIdle == uartStatus)
+        {
+            msg.status                   = kStatus_HAL_UartDmaTxIdle;
+            msg.data                     = uartDmaHandle->dma_tx.buffer;
+            msg.dataSize                 = uartDmaHandle->dma_tx.bufferLength;
+            uartDmaHandle->dma_tx.buffer = NULL;
+        }
+        else if (kStatus_HAL_UartRxIdle == uartStatus)
+        {
+            msg.status                   = kStatus_HAL_UartDmaRxIdle;
+            msg.data                     = uartDmaHandle->dma_rx.buffer;
+            msg.dataSize                 = uartDmaHandle->dma_rx.bufferLength;
+            uartDmaHandle->dma_rx.buffer = NULL;
+        }
+
+        uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param);
+    }
+}
+
+static void TimeoutTimer_Callbcak(void *param)
+{
+    hal_uart_dma_list_t *uartDmaHandleList;
+    hal_uart_dma_state_t *uartDmaHandle;
+    hal_dma_callback_msg_t msg;
+    uint32_t newReceived = 0U;
+
+    uartDmaHandleList = &s_dmaHandleList;
+    uartDmaHandle     = uartDmaHandleList->dma_list;
+
+    while (NULL != uartDmaHandle)
+    {
+        if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll))
+        {
+            /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */
+            USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle,
+                                             &msg.dataSize);
+            newReceived                       = msg.dataSize - uartDmaHandle->dma_rx.bufferSofar;
+            uartDmaHandle->dma_rx.bufferSofar = msg.dataSize;
+
+            /* 1, If it is in idle state. */
+            if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
+            {
+                uartDmaHandle->dma_rx.timeout++;
+                if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT)
+                {
+                    /* HAL_UartDMAAbortReceive(uartDmaHandle); */
+                    USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance],
+                                                  &uartDmaHandle->dmaHandle);
+                    msg.data                     = uartDmaHandle->dma_rx.buffer;
+                    msg.status                   = kStatus_HAL_UartDmaIdleline;
+                    uartDmaHandle->dma_rx.buffer = NULL;
+                    uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param);
+                }
+            }
+            /* 2, If got new data again. */
+            if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
+            {
+                uartDmaHandle->dma_rx.timeout = 0U;
+            }
+        }
+
+        uartDmaHandle = uartDmaHandle->next;
+    }
+}
+
+hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
+                                      hal_uart_dma_handle_t dmaHandle,
+                                      hal_uart_dma_config_t *dmaConfig)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+
+    assert(handle);
+    assert(dmaHandle);
+
+    /* DMA init process. */
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle;
+
+    uartHandle->dmaHandle = uartDmaHandle;
+
+    uartDmaHandle->instance = dmaConfig->uart_instance;
+
+    DMA_Type *dmaBases[] = DMA_BASE_PTRS;
+    DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel);
+    DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel);
+
+    DMA_CreateHandle(&uartDmaHandle->txDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel);
+    DMA_CreateHandle(&uartDmaHandle->rxDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel);
+
+    /* Timeout timer init. */
+    if (0U == s_dmaHandleList.activeCount)
+    {
+        s_dmaHandleList.dma_list = uartDmaHandle;
+        uartDmaHandle->next      = NULL;
+        s_dmaHandleList.activeCount++;
+
+        timer_status_t timerStatus;
+        timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle);
+        assert(kStatus_TimerSuccess == timerStatus);
+
+        timerStatus =
+            TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak, NULL);
+        assert(kStatus_TimerSuccess == timerStatus);
+
+        (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1);
+
+        (void)timerStatus;
+    }
+    else
+    {
+        uartDmaHandle->next      = s_dmaHandleList.dma_list;
+        s_dmaHandleList.dma_list = uartDmaHandle;
+    }
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+    hal_uart_dma_state_t *prev;
+    hal_uart_dma_state_t *curr;
+
+    assert(handle);
+
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = uartHandle->dmaHandle;
+
+    uartHandle->dmaHandle = NULL;
+
+    assert(uartDmaHandle);
+
+    /* Abort rx/tx */
+    /* Here we should not abort before create transfer handle. */
+    if (NULL != uartDmaHandle->dmaHandle.txDmaHandle)
+    {
+        USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+    }
+    if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle)
+    {
+        USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+    }
+
+    /* Disable rx/tx channels */
+    /* Here we should not disable before create transfer handle. */
+    if (NULL != uartDmaHandle->dmaHandle.txDmaHandle)
+    {
+        DMA_DisableChannel(uartDmaHandle->txDmaHandle.base, uartDmaHandle->txDmaHandle.channel);
+    }
+    if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle)
+    {
+        DMA_DisableChannel(uartDmaHandle->rxDmaHandle.base, uartDmaHandle->rxDmaHandle.channel);
+    }
+
+    /* Remove handle from list */
+    prev = NULL;
+    curr = s_dmaHandleList.dma_list;
+    while (curr != NULL)
+    {
+        if (curr == uartDmaHandle)
+        {
+            /* 1, if it is the first one */
+            if (prev == NULL)
+            {
+                s_dmaHandleList.dma_list = curr->next;
+            }
+            /* 2, if it is the last one */
+            else if (curr->next == NULL)
+            {
+                prev->next = NULL;
+            }
+            /* 3, if it is in the middle */
+            else
+            {
+                prev->next = curr->next;
+            }
+            break;
+        }
+
+        prev = curr;
+        curr = curr->next;
+    }
+
+    /* Reset all handle data. */
+    (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t));
+
+    s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0;
+    if (0 == s_dmaHandleList.activeCount)
+    {
+        (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle);
+    }
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
+                                                         hal_uart_dma_transfer_callback_t callback,
+                                                         void *callbackParam)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+
+    assert(handle);
+
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = uartHandle->dmaHandle;
+
+    assert(uartDmaHandle);
+
+    uartDmaHandle->dma_callback       = callback;
+    uartDmaHandle->dma_callback_param = callbackParam;
+
+    USART_TransferCreateHandleDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle,
+                                  USART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txDmaHandle,
+                                  &uartDmaHandle->rxDmaHandle);
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
+                                                 uint8_t *data,
+                                                 size_t length,
+                                                 bool receiveAll)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+    usart_transfer_t xfer;
+
+    assert(handle);
+    assert(data);
+
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = uartHandle->dmaHandle;
+
+    assert(uartDmaHandle);
+
+    if (NULL == uartDmaHandle->dma_rx.buffer)
+    {
+        uartDmaHandle->dma_rx.buffer       = data;
+        uartDmaHandle->dma_rx.bufferLength = length;
+        uartDmaHandle->dma_rx.timeout      = 0U;
+        uartDmaHandle->dma_rx.receiveAll   = receiveAll;
+    }
+    else
+    {
+        /* Already in reading process. */
+        return kStatus_HAL_UartDmaRxBusy;
+    }
+
+    xfer.data     = data;
+    xfer.dataSize = length;
+
+    USART_TransferReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer);
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+    usart_transfer_t xfer;
+
+    assert(handle);
+    assert(data);
+
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = uartHandle->dmaHandle;
+
+    assert(uartDmaHandle);
+
+    if (NULL == uartDmaHandle->dma_tx.buffer)
+    {
+        uartDmaHandle->dma_tx.buffer       = data;
+        uartDmaHandle->dma_tx.bufferLength = length;
+        uartDmaHandle->dma_tx.bufferSofar  = 0U;
+        uartDmaHandle->dma_tx.timeout      = 0U;
+    }
+    else
+    {
+        /* Already in writing process. */
+        return kStatus_HAL_UartDmaTxBusy;
+    }
+
+    xfer.data     = data;
+    xfer.dataSize = length;
+
+    USART_TransferSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer);
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+
+    assert(handle);
+
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = uartHandle->dmaHandle;
+
+    assert(uartDmaHandle);
+
+    if (kStatus_Success != USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance],
+                                                            &uartDmaHandle->dmaHandle, reCount))
+    {
+        return kStatus_HAL_UartDmaError;
+    }
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+    /* No get send count API */
+    return kStatus_HAL_UartDmaError;
+}
+
+hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+
+    assert(handle);
+
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = uartHandle->dmaHandle;
+
+    assert(uartDmaHandle);
+
+    USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_dma_state_t *uartDmaHandle;
+
+    assert(handle);
+
+    uartHandle    = (hal_uart_state_t *)handle;
+    uartDmaHandle = uartHandle->dmaHandle;
+
+    assert(uartDmaHandle);
+
+    USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+
+    return kStatus_HAL_UartDmaSuccess;
+}
+#endif /* HAL_UART_DMA_ENABLE */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW_rw610.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW_rw610.h
new file mode 100644
index 0000000000..2026191c0d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW_rw610.h
@@ -0,0 +1,3502 @@
+/** @file wlan_txpwrlimit_cfg_WW_rw610.h
+ *
+ *  @brief  This file provides WLAN World Wide Safe Mode Tx Power Limits.
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining
+ *  a copy of this software and associated documentation files (the
+ *  'Software'), to deal in the Software without restriction, including
+ *  without limitation the rights to use, copy, modify, merge, publish,
+ *  distribute, sub license, and/or sell copies of the Software, and to
+ *  permit persons to whom the Software is furnished to do so, subject
+ *  to the following conditions:
+ *
+ *  The above copyright notice and this permission notice (including the
+ *  next paragraph) shall be included in all copies or substantial
+ *  portions of the Software.
+ *
+ *  THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ *  IN NO EVENT SHALL NXP AND/OR ITS SUPPLIERS BE LIABLE FOR ANY
+ *  CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ *  TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ *  SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _WLAN_TXPWRLIMIT_CFG_WW_RW610_H_
+#define _WLAN_TXPWRLIMIT_CFG_WW_RW610_H_
+
+#include <wlan.h>
+#include <wifi.h>
+// coverity[MISRA C-2012 Initializers:SUPPRESS]
+static wlan_chanlist_t chanlist_2g_cfg = {
+    .num_chans = 11,
+    .chan_info[0] =
+        {
+            .chan_num                     = 1,
+            .chan_freq                    = 2412,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[1] =
+        {
+            .chan_num                     = 2,
+            .chan_freq                    = 2417,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[2] =
+        {
+            .chan_num                     = 3,
+            .chan_freq                    = 2422,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[3] =
+        {
+            .chan_num                     = 4,
+            .chan_freq                    = 2427,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[4] =
+        {
+            .chan_num                     = 5,
+            .chan_freq                    = 2432,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[5] =
+        {
+            .chan_num                     = 6,
+            .chan_freq                    = 2437,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[6] =
+        {
+            .chan_num                     = 7,
+            .chan_freq                    = 2442,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[7] =
+        {
+            .chan_num                     = 8,
+            .chan_freq                    = 2447,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[8] =
+        {
+            .chan_num                     = 9,
+            .chan_freq                    = 2452,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[9] =
+        {
+            .chan_num                     = 10,
+            .chan_freq                    = 2457,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[10] =
+        {
+            .chan_num                     = 11,
+            .chan_freq                    = 2462,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[11] = {0},
+	.chan_info[12] = {0},
+	.chan_info[13] = {0},
+    .chan_info[14] = {0},
+    .chan_info[15] = {0},
+    .chan_info[16] = {0},
+    .chan_info[17] = {0},
+    .chan_info[18] = {0},
+    .chan_info[19] = {0},
+    .chan_info[20] = {0},
+    .chan_info[21] = {0},
+    .chan_info[22] = {0},
+    .chan_info[23] = {0},
+    .chan_info[24] = {0},
+    .chan_info[25] = {0},
+    .chan_info[26] = {0},
+    .chan_info[27] = {0},
+    .chan_info[28] = {0},
+    .chan_info[29] = {0},
+    .chan_info[30] = {0},
+    .chan_info[31] = {0},
+    .chan_info[32] = {0},
+    .chan_info[33] = {0},
+    .chan_info[34] = {0},
+    .chan_info[35] = {0},
+    .chan_info[36] = {0},
+    .chan_info[37] = {0},
+    .chan_info[38] = {0},
+    .chan_info[39] = {0},
+    .chan_info[40] = {0},
+    .chan_info[41] = {0},
+    .chan_info[42] = {0},
+    .chan_info[43] = {0},
+    .chan_info[44] = {0},
+    .chan_info[45] = {0},
+    .chan_info[46] = {0},
+    .chan_info[47] = {0},
+    .chan_info[48] = {0},
+    .chan_info[49] = {0},
+    .chan_info[50] = {0},
+    .chan_info[51] = {0},
+    .chan_info[52] = {0},
+    .chan_info[53] = {0},
+};
+
+#if CONFIG_5GHz_SUPPORT
+// coverity[MISRA C-2012 Initializers:SUPPRESS]
+static wlan_chanlist_t chanlist_5g_cfg = {
+    .num_chans = 28,
+    .chan_info[0] =
+        {
+            .chan_num                     = 36,
+            .chan_freq                    = 5180,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[1] =
+        {
+            .chan_num                     = 40,
+            .chan_freq                    = 5200,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[2] =
+        {
+            .chan_num                     = 44,
+            .chan_freq                    = 5220,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[3] =
+        {
+            .chan_num                     = 48,
+            .chan_freq                    = 5240,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[4] =
+        {
+            .chan_num                     = 52,
+            .chan_freq                    = 5260,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[5] =
+        {
+            .chan_num                     = 56,
+            .chan_freq                    = 5280,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[6] =
+        {
+            .chan_num                     = 60,
+            .chan_freq                    = 5300,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[7] =
+        {
+            .chan_num                     = 64,
+            .chan_freq                    = 5320,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[8] =
+        {
+            .chan_num                     = 100,
+            .chan_freq                    = 5500,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[9] =
+        {
+            .chan_num                     = 104,
+            .chan_freq                    = 5520,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[10] =
+        {
+            .chan_num                     = 108,
+            .chan_freq                    = 5540,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[11] =
+        {
+            .chan_num                     = 112,
+            .chan_freq                    = 5560,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[12] =
+        {
+            .chan_num                     = 116,
+            .chan_freq                    = 5580,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[13] =
+        {
+            .chan_num                     = 120,
+            .chan_freq                    = 5600,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[14] =
+        {
+            .chan_num                     = 124,
+            .chan_freq                    = 5620,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[15] =
+        {
+            .chan_num                     = 128,
+            .chan_freq                    = 5640,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[16] =
+        {
+            .chan_num                     = 132,
+            .chan_freq                    = 5660,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[17] =
+        {
+            .chan_num                     = 136,
+            .chan_freq                    = 5680,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[18] =
+        {
+            .chan_num                     = 140,
+            .chan_freq                    = 5700,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[19] =
+        {
+            .chan_num                     = 144,
+            .chan_freq                    = 5720,
+            .passive_scan_or_radar_detect = true,
+        },
+    .chan_info[20] =
+        {
+            .chan_num                     = 149,
+            .chan_freq                    = 5745,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[21] =
+        {
+            .chan_num                     = 153,
+            .chan_freq                    = 5765,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[22] =
+        {
+            .chan_num                     = 157,
+            .chan_freq                    = 5785,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[23] =
+        {
+            .chan_num                     = 161,
+            .chan_freq                    = 5805,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[24] =
+        {
+            .chan_num                     = 165,
+            .chan_freq                    = 5825,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[25] =
+        {
+            .chan_num                     = 169,
+            .chan_freq                    = 5845,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[26] =
+        {
+            .chan_num                     = 173,
+            .chan_freq                    = 5865,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[27] =
+        {
+            .chan_num                     = 177,
+            .chan_freq                    = 5885,
+            .passive_scan_or_radar_detect = false,
+        },
+    .chan_info[28] = {0},
+    .chan_info[29] = {0},
+    .chan_info[30] = {0},
+    .chan_info[31] = {0},
+    .chan_info[32] = {0},
+    .chan_info[33] = {0},
+    .chan_info[34] = {0},
+    .chan_info[35] = {0},
+    .chan_info[36] = {0},
+    .chan_info[37] = {0},
+    .chan_info[38] = {0},
+    .chan_info[39] = {0},
+    .chan_info[40] = {0},
+    .chan_info[41] = {0},
+    .chan_info[42] = {0},
+    .chan_info[43] = {0},
+    .chan_info[44] = {0},
+    .chan_info[45] = {0},
+    .chan_info[46] = {0},
+    .chan_info[47] = {0},
+    .chan_info[48] = {0},
+    .chan_info[49] = {0},
+    .chan_info[50] = {0},
+    .chan_info[51] = {0},
+    .chan_info[52] = {0},
+    .chan_info[53] = {0},
+};
+#endif
+
+#if CONFIG_COMPRESS_TX_PWTBL
+static const t_u8 rg_rw610_bga[] = {
+	0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53,
+	0x20, 0x10, 0x00, 0x01, 0x06, 0x02, 0x82, 0x00, 0x88, 0x88, 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0x03, 0x07, 0x00, 0x02, 0x0c, 0x05, 0xab, 0x00, 0x61, 0x40,
+	0x58, 0x02, 0x06, 0x05, 0x0a, 0x80, 0x42, 0x80, 0x40, 0x90, 0x06, 0x0c, 0x14, 0x05, 0x43, 0x60,
+	0xc1, 0x28, 0x28, 0x0c, 0x27, 0x0a, 0x04, 0xc5, 0xe0, 0xc1, 0x38, 0xa8, 0x46, 0x0a, 0x2d, 0x8f,
+	0x00, 0x09, 0x21, 0x08, 0xf8, 0x30, 0x08, 0x0f, 0x07, 0x83, 0x01, 0x08, 0xc0, 0x70, 0x3e, 0x1c,
+	0x2a, 0x0a, 0x02, 0x22, 0xf0, 0x48, 0x48, 0x50, 0x0c, 0x00, 0x07, 0x05, 0x23, 0x30, 0xa0, 0x94,
+	0xe0, 0x28, 0x01, 0x09, 0x82, 0x02, 0x41, 0x39, 0xc4, 0x36, 0x63, 0x33, 0x9e, 0xce, 0x67, 0x61,
+	0x4a, 0x4c, 0xfc, 0x24, 0x1b, 0xa2, 0xc3, 0x8f, 0xc1, 0x1a, 0x80, 0x38, 0x23, 0x0e, 0x34, 0x80,
+	0x0d, 0x21, 0x10, 0x40, 0x42, 0x88, 0x0e, 0x08, 0x54, 0x80};
+
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+static const t_u8 rg_rw610_qfn[] = {
+    0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53, 0x20, 0x10, 0x00, 0x01, 0x06, 0x02, 0x7b, 0x00, 0x88, 0x88,
+    0x03, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0x93, 0x06, 0x00, 0x02, 0x08, 0x07,
+    0x05, 0x01, 0xa1, 0x50, 0x08, 0x50, 0x0b, 0x04, 0x0a, 0x00, 0x82, 0x70, 0x50, 0x20, 0x02, 0x0a, 0x08, 0x85,
+    0x85, 0x21, 0xa0, 0x10, 0x90, 0x36, 0x1d, 0x11, 0x88, 0x00, 0xa1, 0x31, 0x78, 0xb0, 0x04, 0x23, 0x16, 0x15,
+    0xc7, 0xc0, 0x04, 0x70, 0x84, 0x80, 0x00, 0x04, 0x01, 0x83, 0xc0, 0x00, 0x84, 0x00, 0x38, 0x06, 0x01, 0x00,
+    0x0a, 0x82, 0x81, 0x48, 0x40, 0x18, 0x01, 0x01, 0x0e, 0x4d, 0xc2, 0x80, 0x10, 0x98, 0x20, 0x24, 0x13, 0x9b,
+    0x84, 0xa0, 0xa1, 0xb9, 0xd4, 0xe6, 0x03, 0x14, 0xa2, 0x03, 0xa8, 0x40, 0x03, 0xf0, 0x46, 0x92, 0x11, 0x98,
+    0x1a, 0x40, 0x06, 0x90, 0x88, 0x20, 0x21, 0x40, 0x07, 0x04, 0x26, 0x07, 0xe0};
+
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+static const t_u8 rg_rw610_csp[] = {
+    0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53, 0x20, 0x10, 0x00, 0x01, 0x06, 0x02, 0x7f, 0x00, 0x88, 0x88,
+    0x03, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0xd3, 0x06, 0x00, 0x02, 0x08, 0x07,
+    0x05, 0x01, 0xa1, 0x50, 0x08, 0x50, 0x0b, 0x04, 0x0a, 0x00, 0x82, 0x70, 0x50, 0x20, 0x00, 0x02, 0x13, 0x06,
+    0xc3, 0x82, 0x31, 0x18, 0x7c, 0x14, 0x10, 0x13, 0x01, 0x42, 0x61, 0xd1, 0x08, 0x94, 0x44, 0x57, 0x13, 0x00,
+    0x11, 0xc2, 0x11, 0xe0, 0x00, 0x10, 0x06, 0x0f, 0x00, 0x02, 0x10, 0x00, 0xe0, 0x18, 0x04, 0x00, 0x2a, 0x0a,
+    0x02, 0x02, 0xa0, 0xb0, 0xa0, 0x06, 0x10, 0x06, 0x00, 0x03, 0xa1, 0x13, 0x29, 0xa0, 0x22, 0x73, 0x04, 0x09,
+    0x06, 0xe7, 0x21, 0x29, 0xb0, 0x4e, 0x63, 0x3f, 0x0a, 0x51, 0xe7, 0x40, 0x10, 0x88, 0x20, 0x24, 0x0b, 0xa6,
+    0xd0, 0xe5, 0xc7, 0xe0, 0x8d, 0x08, 0x1c, 0x11, 0x97, 0x1a, 0x40, 0x06, 0x90, 0x85, 0x58, 0x21, 0x53};
+
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+static const t_u8 rg_rw610_EU[] = {
+	0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x45, 0x55,
+	0x20, 0x30, 0x00, 0x02, 0x06, 0x02, 0x96, 0x00, 0x88, 0x88, 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x45, 0x55, 0x20, 0x30, 0x43, 0x08, 0x00, 0x02, 0x0c, 0x06, 0xab, 0x00, 0x21, 0x30,
+	0x68, 0x02, 0x06, 0x03, 0x0a, 0x01, 0xc2, 0x60, 0x38, 0x34, 0x2e, 0x13, 0x0b, 0x83, 0x04, 0xa0,
+	0xb0, 0x30, 0x10, 0x50, 0x12, 0x13, 0x00, 0x84, 0x80, 0x30, 0xd0, 0x64, 0x6a, 0x0c, 0x11, 0x82,
+	0x8a, 0xe4, 0x00, 0x02, 0x38, 0x42, 0x42, 0x0c, 0x02, 0x03, 0xc1, 0xe0, 0xc0, 0x42, 0x30, 0x1c,
+	0x0f, 0x8d, 0x8a, 0xa3, 0x01, 0x40, 0x34, 0xcc, 0x15, 0x18, 0x07, 0x02, 0x00, 0x00, 0xe0, 0x9c,
+	0x56, 0x6a, 0x01, 0x0a, 0x02, 0xa3, 0x53, 0x99, 0xdc, 0x68, 0x26, 0x08, 0x09, 0x02, 0xe8, 0x80,
+	0xea, 0x35, 0x02, 0x7f, 0x41, 0x08, 0x80, 0x69, 0x75, 0x19, 0x9d, 0x3c, 0x15, 0x51, 0xa9, 0xc6,
+	0x42, 0x55, 0x89, 0xd0, 0x3a, 0xa2, 0x00, 0x3f, 0x04, 0x42, 0x75, 0x90, 0x01, 0xa6, 0xca, 0x11,
+	0x04, 0x04, 0x29, 0x55, 0xd0, 0x80, 0x06, 0xd1, 0x6a, 0xa5, 0xdb, 0x40, 0x05, 0x40};
+
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+static const t_u8 rg_rw610_JP[] = {
+	0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x4a, 0x50,
+	0x20, 0x40, 0x00, 0x03, 0x06, 0x02, 0x64, 0x00, 0x88, 0x88, 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x4a, 0x50, 0x20, 0x40, 0x23, 0x05, 0x00, 0x02, 0x0c, 0x14, 0x80, 0x00, 0x20, 0xc0,
+	0x6c, 0x0a, 0x09, 0x06, 0x82, 0xc0, 0xe1, 0x30, 0x71, 0x5c, 0x1c, 0x8f, 0x0c, 0x06, 0x01, 0x01,
+	0xe0, 0xf0, 0x60, 0x21, 0x18, 0x0e, 0x07, 0x80, 0x40, 0x02, 0xa0, 0x50, 0x10, 0x0e, 0x04, 0x07,
+	0x04, 0xc0, 0x00, 0xe0, 0x70, 0x06, 0x3b, 0x1f, 0x90, 0xc8, 0xe4, 0xb2, 0x79, 0x04, 0x8a, 0x49,
+	0x26, 0x8f, 0x4b, 0x65, 0x53, 0x09, 0x44, 0xba, 0x57, 0x31, 0x94, 0xcb, 0xc0, 0x07, 0xe9, 0x64,
+	0xe6, 0x4a, 0x00, 0x34, 0xd0, 0x27, 0xb3, 0x69, 0xa4, 0xca, 0x74, 0x54};
+
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+static const t_u8 rg_rw610_CN[] = {
+	0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x43, 0x4e,
+	0x20, 0x50, 0x00, 0x02, 0x06, 0x02, 0xaa, 0x00, 0x88, 0x88, 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x43, 0x4e, 0x20, 0x50, 0x83, 0x09, 0x00, 0x02, 0x0c, 0x06, 0xab, 0x00, 0x21, 0x30,
+	0x58, 0x38, 0x02, 0x0d, 0x00, 0x80, 0x00, 0x21, 0x20, 0x40, 0x44, 0x02, 0x10, 0x00, 0x83, 0x00,
+	0x20, 0x58, 0x48, 0x0a, 0x19, 0x0e, 0x88, 0x44, 0xa2, 0x80, 0x08, 0xb4, 0x36, 0x1f, 0x11, 0x89,
+	0xc5, 0x41, 0xf1, 0xf0, 0x88, 0x1a, 0x21, 0x23, 0x8d, 0x48, 0xa4, 0x92, 0x60, 0x0c, 0xa2, 0x43,
+	0x1c, 0x91, 0xc4, 0x24, 0xb2, 0x79, 0x04, 0x6c, 0x58, 0x11, 0x04, 0x4d, 0x25, 0x20, 0x02, 0x40,
+	0x40, 0x13, 0x2e, 0x9b, 0x03, 0x00, 0x80, 0xf0, 0x78, 0x30, 0x10, 0x8c, 0x07, 0x48, 0xc0, 0x02,
+	0xa0, 0xa0, 0x4c, 0x24, 0x01, 0x0a, 0x00, 0xe2, 0x15, 0x10, 0x00, 0x38, 0x28, 0x14, 0xa7, 0xd4,
+	0x6a, 0x60, 0x3a, 0xa8, 0x52, 0x06, 0x08, 0x09, 0x03, 0xe2, 0x01, 0x2a, 0xe0, 0x3a, 0xb2, 0x13,
+	0x09, 0xd4, 0x2a, 0x56, 0xaa, 0xed, 0x36, 0xd5, 0x5b, 0xae, 0xc2, 0xc2, 0xf6, 0x3b, 0x2d, 0x3c,
+	0x00, 0x7e, 0x08, 0x86, 0xea, 0xb0, 0xe0, 0x01, 0xa6, 0xfb, 0x38, 0x08, 0x51, 0x21, 0xf6, 0x58,
+	0x85, 0xdc};
+
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+static const t_u8 rg_rw610_WW[] = {
+	0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x57, 0x57,
+	0x00, 0x00, 0x00, 0x00, 0x06, 0x02, 0x6b, 0x00, 0x88, 0x88, 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x57, 0x57, 0x00, 0x00, 0x93, 0x05, 0x00, 0x02, 0x0c, 0x13, 0x81, 0x40, 0x20, 0x00,
+	0x10, 0x30, 0x17, 0x02, 0x82, 0x41, 0xa1, 0x10, 0x58, 0x3c, 0x0e, 0x19, 0x0b, 0x85, 0x40, 0xc5,
+	0x91, 0x10, 0x01, 0x22, 0x29, 0x13, 0x02, 0x03, 0xc1, 0xe0, 0xc0, 0x42, 0x30, 0x1c, 0x0f, 0x81,
+	0x8a, 0x81, 0x40, 0x40, 0x38, 0x10, 0x1c, 0x13, 0x00, 0x03, 0x81, 0xc0, 0x19, 0x1c, 0x96, 0x4f,
+	0x29, 0x95, 0xcb, 0x64, 0xd2, 0x89, 0x54, 0xb2, 0x49, 0x33, 0x98, 0x4d, 0xa5, 0xd3, 0x49, 0x8c,
+	0xde, 0x5f, 0x35, 0x00, 0x1f, 0xa6, 0x53, 0xf9, 0x58, 0x00, 0xd3, 0x46, 0xa1, 0xcf, 0x27, 0x53,
+	0x8a, 0x01, 0x50};
+#endif
+
+#ifndef CONFIG_11AX
+#ifndef CONFIG_11AC
+static wifi_txpwrlimit_t
+    tx_pwrlimit_2g_cfg =
+        {
+            .subband   = (wifi_SubBand_t)0x00,
+            .num_chans = 14,
+            .txpwrlimit_config[0] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 1,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 15}, {2, 15}, {3, 15}, {4, 13}, {5, 13}, {6, 13}},
+                },
+            .txpwrlimit_config[1] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 2,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}},
+                },
+            .txpwrlimit_config[2] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 3,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}},
+                },
+            .txpwrlimit_config[3] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 4,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}},
+                },
+            .txpwrlimit_config[4] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 5,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}},
+                },
+            .txpwrlimit_config[5] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 6,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}},
+                },
+            .txpwrlimit_config[6] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 7,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}},
+                },
+            .txpwrlimit_config[7] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 8,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}},
+                },
+            .txpwrlimit_config[8] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 9,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 17}, {2, 17}, {3, 16}, {4, 16}, {5, 16}, {6, 16}},
+                },
+            .txpwrlimit_config[9] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 10,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}},
+                },
+            .txpwrlimit_config[10] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 11,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 13}, {2, 13}, {3, 13}, {4, 12}, {5, 12}, {6, 12}},
+                },
+            .txpwrlimit_config[11] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 12,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}},
+                },
+            .txpwrlimit_config[12] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 13,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}},
+                },
+            .txpwrlimit_config[13] =
+                {
+                    .num_mod_grps = 7,
+                    .chan_desc =
+                        {
+                            .start_freq = 2414,
+                            .chan_width = 20,
+                            .chan_num   = 14,
+                        },
+                    .txpwrlimit_entry = {{0, 19}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}},
+                },
+            .txpwrlimit_config[14] = {0},
+            .txpwrlimit_config[15] = {0},
+            .txpwrlimit_config[16] = {0},
+            .txpwrlimit_config[17] = {0},
+            .txpwrlimit_config[18] = {0},
+            .txpwrlimit_config[19] = {0},
+            .txpwrlimit_config[20] = {0},
+            .txpwrlimit_config[21] = {0},
+            .txpwrlimit_config[22] = {0},
+            .txpwrlimit_config[23] = {0},
+            .txpwrlimit_config[24] = {0},
+            .txpwrlimit_config[25] = {0},
+            .txpwrlimit_config[26] = {0},
+            .txpwrlimit_config[27] = {0},
+            .txpwrlimit_config[28] = {0},
+            .txpwrlimit_config[29] = {0},
+            .txpwrlimit_config[30] = {0},
+            .txpwrlimit_config[31] = {0},
+            .txpwrlimit_config[32] = {0},
+            .txpwrlimit_config[33] = {0},
+            .txpwrlimit_config[34] = {0},
+            .txpwrlimit_config[35] = {0},
+            .txpwrlimit_config[36] = {0},
+            .txpwrlimit_config[37] = {0},
+            .txpwrlimit_config[38] = {0},
+            .txpwrlimit_config[39] = {0},
+};
+
+#if CONFIG_5GHz_SUPPORT
+static wifi_txpwrlimit_t
+    tx_pwrlimit_5g_cfg =
+        {
+            .subband   = (wifi_SubBand_t)0x00,
+            .num_chans = 25,
+            .txpwrlimit_config[0] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 36,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[1] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 40,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[2] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 44,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[3] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 48,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 16}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[4] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 52,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 17}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[5] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 56,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[6] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 60,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[7] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 64,
+                        },
+                    .txpwrlimit_entry = {{1, 19}, {2, 19}, {3, 16}, {4, 18}, {5, 18}, {6, 15}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[8] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 100,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[9] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 104,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[10] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 108,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[11] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 112,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[12] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 116,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[13] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 120,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[14] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 124,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[15] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 128,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[16] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 132,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[17] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 136,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[18] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 140,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[19] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 144,
+                        },
+                    .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[20] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 149,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 17}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[21] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 153,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 16}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[22] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 157,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 15}, {4, 21}, {5, 21}, {6, 14}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[23] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 161,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 21}, {5, 21}, {6, 12}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[24] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 165,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 20}, {5, 20}, {6, 12}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[25] = {0},
+            .txpwrlimit_config[26] = {0},
+            .txpwrlimit_config[27] = {0},
+            .txpwrlimit_config[28] = {0},
+            .txpwrlimit_config[29] = {0},
+            .txpwrlimit_config[30] = {0},
+            .txpwrlimit_config[31] = {0},
+            .txpwrlimit_config[32] = {0},
+            .txpwrlimit_config[33] = {0},
+            .txpwrlimit_config[34] = {0},
+            .txpwrlimit_config[35] = {0},
+            .txpwrlimit_config[36] = {0},
+            .txpwrlimit_config[37] = {0},
+            .txpwrlimit_config[38] = {0},
+            .txpwrlimit_config[39] = {0},
+/* Rest of the channels listed below are not used and contains dummy power entries,
+ * they belong to 4.9GHz Band for Public Safety.
+ */
+#if 0
+            .txpwrlimit_config[25] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 183,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[26] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 184,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[27] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 185,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[28] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 187,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[29] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 188,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[30] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 189,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[31] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 192,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[32] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 196,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[33] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 7,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[34] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 8,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[35] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 11,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[36] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 12,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[37] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 16,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+            .txpwrlimit_config[38] =
+                {
+                    .num_mod_grps = 9,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 34,
+                        },
+                    .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}},
+                },
+#endif
+};
+#endif
+#else
+static wifi_txpwrlimit_t
+    tx_pwrlimit_2g_cfg =
+        {
+            .subband   = (wifi_SubBand_t)0x00,
+            .num_chans = 14,
+            .txpwrlimit_config[0] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 1,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 15},
+                                         {2, 15},
+                                         {3, 15},
+                                         {4, 13},
+                                         {5, 13},
+                                         {6, 13},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 13},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[1] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 2,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 16},
+                                         {2, 16},
+                                         {3, 16},
+                                         {4, 16},
+                                         {5, 16},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[2] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 3,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 16},
+                                         {2, 16},
+                                         {3, 16},
+                                         {4, 16},
+                                         {5, 16},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[3] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 4,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 18},
+                                         {2, 18},
+                                         {3, 17},
+                                         {4, 16},
+                                         {5, 17},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 15},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[4] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 5,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 18},
+                                         {2, 18},
+                                         {3, 17},
+                                         {4, 16},
+                                         {5, 17},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 15},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[5] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 6,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 18},
+                                         {2, 18},
+                                         {3, 17},
+                                         {4, 16},
+                                         {5, 17},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 14},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[6] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 7,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 18},
+                                         {2, 18},
+                                         {3, 17},
+                                         {4, 16},
+                                         {5, 17},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[7] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 8,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 18},
+                                         {2, 18},
+                                         {3, 17},
+                                         {4, 16},
+                                         {5, 17},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[8] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 9,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 17},
+                                         {2, 17},
+                                         {3, 16},
+                                         {4, 16},
+                                         {5, 16},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 15},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[9] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 10,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 16},
+                                         {2, 16},
+                                         {3, 16},
+                                         {4, 15},
+                                         {5, 15},
+                                         {6, 15},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 15},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[10] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 11,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 13},
+                                         {2, 13},
+                                         {3, 13},
+                                         {4, 12},
+                                         {5, 12},
+                                         {6, 12},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 12},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[11] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 12,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 18},
+                                         {2, 18},
+                                         {3, 17},
+                                         {4, 16},
+                                         {5, 17},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[12] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2407,
+                            .chan_width = 20,
+                            .chan_num   = 13,
+                        },
+                    .txpwrlimit_entry = {{0, 19},
+                                         {1, 18},
+                                         {2, 18},
+                                         {3, 17},
+                                         {4, 16},
+                                         {5, 17},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0}},
+                },
+            .txpwrlimit_config[13] =
+                {
+                    .num_mod_grps = 12,
+                    .chan_desc =
+                        {
+                            .start_freq = 2414,
+                            .chan_width = 20,
+                            .chan_num   = 14,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 19},
+                         {1, 0},
+                         {2, 0},
+                         {3, 0},
+                         {4, 0},
+                         {5, 0},
+                         {6, 0},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 0},
+                         {11, 0}},
+                },
+            .txpwrlimit_config[14] = {0},
+            .txpwrlimit_config[15] = {0},
+            .txpwrlimit_config[16] = {0},
+            .txpwrlimit_config[17] = {0},
+            .txpwrlimit_config[18] = {0},
+            .txpwrlimit_config[19] = {0},
+            .txpwrlimit_config[20] = {0},
+            .txpwrlimit_config[21] = {0},
+            .txpwrlimit_config[22] = {0},
+            .txpwrlimit_config[23] = {0},
+            .txpwrlimit_config[24] = {0},
+            .txpwrlimit_config[25] = {0},
+            .txpwrlimit_config[26] = {0},
+            .txpwrlimit_config[27] = {0},
+            .txpwrlimit_config[28] = {0},
+            .txpwrlimit_config[29] = {0},
+            .txpwrlimit_config[30] = {0},
+            .txpwrlimit_config[31] = {0},
+            .txpwrlimit_config[32] = {0},
+            .txpwrlimit_config[33] = {0},
+            .txpwrlimit_config[34] = {0},
+            .txpwrlimit_config[35] = {0},
+            .txpwrlimit_config[36] = {0},
+            .txpwrlimit_config[37] = {0},
+            .txpwrlimit_config[38] = {0},
+            .txpwrlimit_config[39] = {0},
+};
+
+#if CONFIG_5GHz_SUPPORT
+static wifi_txpwrlimit_t
+    tx_pwrlimit_5g_cfg =
+        {
+            .subband   = (wifi_SubBand_t)0x00,
+            .num_chans = 25,
+            .txpwrlimit_config[0] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 36,
+                        },
+                    .txpwrlimit_entry = {{0, 0},
+                                         {1, 20},
+                                         {2, 20},
+                                         {3, 20},
+                                         {4, 20},
+                                         {5, 20},
+                                         {6, 19},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0},
+                                         {12, 0},
+                                         {13, 0},
+                                         {14, 0},
+                                         {15, 0}},
+                },
+            .txpwrlimit_config[1] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 40,
+                        },
+                    .txpwrlimit_entry = {{0, 0},
+                                         {1, 20},
+                                         {2, 20},
+                                         {3, 19},
+                                         {4, 20},
+                                         {5, 20},
+                                         {6, 18},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0},
+                                         {12, 0},
+                                         {13, 0},
+                                         {14, 0},
+                                         {15, 0}},
+                },
+            .txpwrlimit_config[2] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 44,
+                        },
+                    .txpwrlimit_entry = {{0, 0},
+                                         {1, 20},
+                                         {2, 20},
+                                         {3, 18},
+                                         {4, 20},
+                                         {5, 20},
+                                         {6, 17},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0},
+                                         {12, 0},
+                                         {13, 0},
+                                         {14, 0},
+                                         {15, 0}},
+                },
+            .txpwrlimit_config[3] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 48,
+                        },
+                    .txpwrlimit_entry = {{0, 0},
+                                         {1, 20},
+                                         {2, 20},
+                                         {3, 16},
+                                         {4, 20},
+                                         {5, 20},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 16},
+                                         {11, 0},
+                                         {12, 0},
+                                         {13, 0},
+                                         {14, 0},
+                                         {15, 0}},
+                },
+            .txpwrlimit_config[4] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 52,
+                        },
+                    .txpwrlimit_entry = {{0, 0},
+                                         {1, 20},
+                                         {2, 20},
+                                         {3, 17},
+                                         {4, 20},
+                                         {5, 20},
+                                         {6, 16},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 15},
+                                         {11, 0},
+                                         {12, 0},
+                                         {13, 0},
+                                         {14, 0},
+                                         {15, 0}},
+                },
+            .txpwrlimit_config[5] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 56,
+                        },
+                    .txpwrlimit_entry = {{0, 0},
+                                         {1, 20},
+                                         {2, 20},
+                                         {3, 19},
+                                         {4, 20},
+                                         {5, 20},
+                                         {6, 18},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 15},
+                                         {11, 0},
+                                         {12, 0},
+                                         {13, 0},
+                                         {14, 0},
+                                         {15, 0}},
+                },
+            .txpwrlimit_config[6] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 60,
+                        },
+                    .txpwrlimit_entry = {{0, 0},
+                                         {1, 20},
+                                         {2, 20},
+                                         {3, 18},
+                                         {4, 20},
+                                         {5, 20},
+                                         {6, 17},
+                                         {7, 0},
+                                         {8, 0},
+                                         {9, 0},
+                                         {10, 15},
+                                         {11, 0},
+                                         {12, 0},
+                                         {13, 0},
+                                         {14, 0},
+                                         {15, 0}},
+                },
+            .txpwrlimit_config[7] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 64,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 19},
+                         {2, 19},
+                         {3, 16},
+                         {4, 18},
+                         {5, 18},
+                         {6, 15},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[8] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 100,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 19},
+                         {4, 20},
+                         {5, 20},
+                         {6, 18},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[9] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 104,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 18},
+                         {4, 20},
+                         {5, 21},
+                         {6, 18},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[10] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 108,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 19},
+                         {4, 20},
+                         {5, 21},
+                         {6, 18},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[11] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 112,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 19},
+                         {4, 20},
+                         {5, 21},
+                         {6, 18},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[12] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 116,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 19},
+                         {4, 21},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[13] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 120,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 19},
+                         {4, 21},
+                         {5, 20},
+                         {6, 18},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[14] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 124,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 18},
+                         {4, 21},
+                         {5, 20},
+                         {6, 16},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[15] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 128,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 18},
+                         {4, 21},
+                         {5, 20},
+                         {6, 16},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[16] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 132,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 18},
+                         {4, 21},
+                         {5, 20},
+                         {6, 18},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[17] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 136,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 18},
+                         {4, 21},
+                         {5, 20},
+                         {6, 18},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[18] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 140,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 16},
+                         {4, 21},
+                         {5, 20},
+                         {6, 15},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[19] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 144,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 21},
+                         {2, 21},
+                         {3, 16},
+                         {4, 21},
+                         {5, 20},
+                         {6, 15},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 15},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[20] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 149,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 18},
+                         {4, 21},
+                         {5, 21},
+                         {6, 17},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 12},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[21] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 153,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 18},
+                         {4, 21},
+                         {5, 21},
+                         {6, 16},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 12},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[22] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 157,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 15},
+                         {4, 21},
+                         {5, 21},
+                         {6, 14},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 12},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[23] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 161,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 13},
+                         {4, 21},
+                         {5, 21},
+                         {6, 12},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 12},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[24] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 165,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 13},
+                         {4, 20},
+                         {5, 20},
+                         {6, 12},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 12},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[25] = {0},
+            .txpwrlimit_config[26] = {0},
+            .txpwrlimit_config[27] = {0},
+            .txpwrlimit_config[28] = {0},
+            .txpwrlimit_config[29] = {0},
+            .txpwrlimit_config[30] = {0},
+            .txpwrlimit_config[31] = {0},
+            .txpwrlimit_config[32] = {0},
+            .txpwrlimit_config[33] = {0},
+            .txpwrlimit_config[34] = {0},
+            .txpwrlimit_config[35] = {0},
+            .txpwrlimit_config[36] = {0},
+            .txpwrlimit_config[37] = {0},
+            .txpwrlimit_config[38] = {0},
+            .txpwrlimit_config[39] = {0},
+/* Rest of the channels listed below are not used and contains dummy power entries,
+ * they belong to 4.9GHz Band for Public Safety.
+ */
+#if 0
+            .txpwrlimit_config[25] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 183,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[26] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 184,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 18},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[27] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 185,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[28] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 187,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[29] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 188,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[30] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 189,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[31] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 192,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[32] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 196,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[33] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 7,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[34] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 8,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[35] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 11,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[36] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 12,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[37] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 16,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+            .txpwrlimit_config[38] =
+                {
+                    .num_mod_grps = 16,
+                    .chan_desc =
+                        {
+                            .start_freq = 5000,
+                            .chan_width = 20,
+                            .chan_num   = 34,
+                        },
+                    .txpwrlimit_entry =
+                        {{0, 0},
+                         {1, 20},
+                         {2, 20},
+                         {3, 20},
+                         {4, 20},
+                         {5, 20},
+                         {6, 19},
+                         {7, 0},
+                         {8, 0},
+                         {9, 0},
+                         {10, 16},
+                         {11, 0},
+                         {12, 0},
+                         {13, 0},
+                         {14, 0},
+                         {15, 0}},
+                },
+#endif
+};
+#endif /* CONFIG_5GHz_SUPPORT */
+#endif /* CONFIG_11AC */
+#else
+// coverity[MISRA C-2012 Initializers :SUPPRESS]
+static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = {
+    .subband   = (wifi_SubBand_t)0x00,
+    .num_chans = 14,
+    .txpwrlimit_config[0] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 1,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 15}, {2, 15},  {3, 15},  {4, 13}, {5, 13}, {6, 13},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 13}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 13}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[1] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 2,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16},  {3, 16},  {4, 16}, {5, 16}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 15}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[2] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 3,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16},  {3, 16},  {4, 16}, {5, 16}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 15}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[3] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 4,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18},  {3, 17},  {4, 16}, {5, 17}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 12}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[4] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 5,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18},  {3, 17},  {4, 16}, {5, 17}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 13}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[5] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 6,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18},  {3, 17},  {4, 16}, {5, 17}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 14}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[6] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 7,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18},  {3, 17},  {4, 16}, {5, 17}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 15}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[7] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 8,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18},  {3, 17},  {4, 16}, {5, 17}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[8] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 9,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 17}, {2, 17},  {3, 16},  {4, 16}, {5, 16}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[9] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 10,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16},  {3, 16},  {4, 15}, {5, 15}, {6, 15},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[10] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 11,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 13}, {2, 13},  {3, 13},  {4, 12}, {5, 12}, {6, 12},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 12}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 12}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[11] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 12,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18},  {3, 17},  {4, 16}, {5, 17}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[12] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2407,
+                    .chan_width = 20,
+                    .chan_num   = 13,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18},  {3, 17},  {4, 16}, {5, 17}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[13] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 2414,
+                    .chan_width = 20,
+                    .chan_num   = 14,
+                },
+            .txpwrlimit_entry = {{0, 19}, {1, 0},  {2, 0},  {3, 0},  {4, 0},  {5, 0},  {6, 0},
+                                 {7, 0},  {8, 0},  {9, 0},  {10, 0}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[14] = {0},
+    .txpwrlimit_config[15] = {0},
+    .txpwrlimit_config[16] = {0},
+    .txpwrlimit_config[17] = {0},
+    .txpwrlimit_config[18] = {0},
+    .txpwrlimit_config[19] = {0},
+    .txpwrlimit_config[20] = {0},
+    .txpwrlimit_config[21] = {0},
+    .txpwrlimit_config[22] = {0},
+    .txpwrlimit_config[23] = {0},
+    .txpwrlimit_config[24] = {0},
+    .txpwrlimit_config[25] = {0},
+    .txpwrlimit_config[26] = {0},
+    .txpwrlimit_config[27] = {0},
+    .txpwrlimit_config[28] = {0},
+    .txpwrlimit_config[29] = {0},
+    .txpwrlimit_config[30] = {0},
+    .txpwrlimit_config[31] = {0},
+    .txpwrlimit_config[32] = {0},
+    .txpwrlimit_config[33] = {0},
+    .txpwrlimit_config[34] = {0},
+    .txpwrlimit_config[35] = {0},
+    .txpwrlimit_config[36] = {0},
+    .txpwrlimit_config[37] = {0},
+    .txpwrlimit_config[38] = {0},
+    .txpwrlimit_config[39] = {0},
+};
+
+#if CONFIG_5GHz_SUPPORT
+static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = {
+    .subband   = (wifi_SubBand_t)0x00,
+    .num_chans = 25,
+    .txpwrlimit_config[0] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 36,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[1] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 40,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 19},  {4, 20}, {5, 20}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[2] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 44,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 18},  {4, 20}, {5, 20}, {6, 17},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[3] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 48,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 16},  {4, 20}, {5, 20}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[4] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 52,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 17},  {4, 20}, {5, 20}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 15}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[5] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 56,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 19},  {4, 20}, {5, 20}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 15}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[6] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 60,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 18},  {4, 20}, {5, 20}, {6, 17},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 15}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[7] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 64,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 19}, {2, 19},  {3, 16},  {4, 18}, {5, 18}, {6, 15},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 15}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[8] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 100,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 19},  {4, 20}, {5, 20}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[9] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 104,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 18},  {4, 20}, {5, 21}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[10] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 108,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 19},  {4, 20}, {5, 21}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[11] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 112,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 19},  {4, 20}, {5, 21}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[12] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 116,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 19},  {4, 21}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[13] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 120,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 19},  {4, 21}, {5, 20}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[14] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 124,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 18},  {4, 21}, {5, 20}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[15] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 128,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 18},  {4, 21}, {5, 20}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[16] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 132,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 18},  {4, 21}, {5, 20}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[17] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 136,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 18},  {4, 21}, {5, 20}, {6, 18},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[18] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 140,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 16},  {4, 21}, {5, 20}, {6, 15},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[19] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 144,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 21}, {2, 21},  {3, 16},  {4, 21}, {5, 20}, {6, 15},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 15}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 14}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[20] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 149,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 18},  {4, 21}, {5, 21}, {6, 17},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 12}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 10}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[21] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 153,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 18},  {4, 21}, {5, 21}, {6, 16},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 12}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 10}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[22] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 157,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 15},  {4, 21}, {5, 21}, {6, 14},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 12}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 10}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[23] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 161,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 13},  {4, 21}, {5, 21}, {6, 12},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 12}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 10}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[24] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 165,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 13},  {4, 20}, {5, 20}, {6, 12},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 12}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 10}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[25] = {0},
+    .txpwrlimit_config[26] = {0},
+    .txpwrlimit_config[27] = {0},
+    .txpwrlimit_config[28] = {0},
+    .txpwrlimit_config[29] = {0},
+    .txpwrlimit_config[30] = {0},
+    .txpwrlimit_config[31] = {0},
+    .txpwrlimit_config[32] = {0},
+    .txpwrlimit_config[33] = {0},
+    .txpwrlimit_config[34] = {0},
+    .txpwrlimit_config[35] = {0},
+    .txpwrlimit_config[36] = {0},
+    .txpwrlimit_config[37] = {0},
+    .txpwrlimit_config[38] = {0},
+    .txpwrlimit_config[39] = {0},
+/* Rest of the channels listed below are not used and contains dummy power entries,
+ * they belong to 4.9GHz Band for Public Safety.
+ */
+#if 0
+    .txpwrlimit_config[25] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 183,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[26] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 184,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 18}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 18}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[27] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 185,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[28] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 187,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[29] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 188,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[30] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 189,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[31] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 192,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[32] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 196,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[33] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 7,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[34] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 8,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[35] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 11,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[36] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 12,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[37] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 16,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+    .txpwrlimit_config[38] =
+        {
+            .num_mod_grps = 20,
+            .chan_desc =
+                {
+                    .start_freq = 5000,
+                    .chan_width = 20,
+                    .chan_num   = 34,
+                },
+            .txpwrlimit_entry = {{0, 0},  {1, 20}, {2, 20},  {3, 20},  {4, 20}, {5, 20}, {6, 19},
+                                 {7, 0},  {8, 0},  {9, 0},   {10, 16}, {11, 0}, {12, 0}, {13, 0},
+                                 {14, 0}, {15, 0}, {16, 16}, {17, 0},  {18, 0}, {19, 0}},
+        },
+#endif
+};
+#endif /* CONFIG_5GHz_SUPPORT */
+#endif /* CONFIG_11AX */
+
+#if CONFIG_11AX
+#if CONFIG_COMPRESS_RU_TX_PWTBL
+const static uint8_t rutxpowerlimit_cfg_set_WW[] = {
+	0x6d, 0x02, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x04, 0x06, 0x0a, 0x0c,
+	0x00, 0x00, 0x00, 0x04, 0x06, 0x0a, 0x0c, 0x00, 0x00, 0x00, 0x04, 0x06, 0x0a, 0x0c, 0x00, 0x00,
+	0x00, 0x06, 0x08, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x02, 0x05, 0x07, 0x07, 0x00, 0x00, 0x00, 0x02,
+	0x05, 0x07, 0x07, 0x00, 0x00, 0x00, 0x06, 0x0b, 0x0e, 0x0e, 0x00, 0x00, 0x00, 0x06, 0x0b, 0x0e,
+	0x0e, 0x00, 0x00, 0x00, 0x06, 0x09, 0x09, 0x09, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00,
+	0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00, 0x00, 0x00, 0x08, 0x0b, 0x0e, 0x0e, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x02, 0x03, 0x00, 0x88, 0x88, 0x00};
+
+const static uint8_t rutxpowerlimit_cfg_set_FCC[] = {
+	0x6d, 0x02, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x11, 0x12, 0x12, 0x12,
+	0x00, 0x00, 0x00, 0x11, 0x12, 0x12, 0x11, 0x00, 0x00, 0x00, 0x0f, 0x12, 0x11, 0x10, 0x00, 0x00,
+	0x00, 0x0d, 0x0f, 0x11, 0x11, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0x11, 0x11, 0x00, 0x00, 0x00, 0x0d,
+	0x0f, 0x11, 0x11, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0x11, 0x11, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0x11,
+	0x11, 0x00, 0x00, 0x00, 0x09, 0x09, 0x09, 0x09, 0x00, 0x00, 0x00, 0x11, 0x11, 0x11, 0x11, 0x00,
+	0x00, 0x00, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x08, 0x0b, 0x0e, 0x11, 0x00, 0x00, 0x00,
+	0x13, 0x13, 0x12, 0x10, 0x00, 0x64, 0x02, 0x03, 0x00, 0x88, 0x88, 0x00};
+
+const static uint8_t rutxpowerlimit_cfg_set_EU[] = {
+	0x6d, 0x02, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x06, 0x0b, 0x0f, 0x12,
+	0x00, 0x00, 0x00, 0x0a, 0x0d, 0x10, 0x12, 0x00, 0x00, 0x00, 0x06, 0x09, 0x10, 0x11, 0x00, 0x00,
+	0x00, 0x0d, 0x0f, 0x11, 0x11, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0f, 0x11, 0x00, 0x00, 0x00, 0x09,
+	0x0c, 0x0f, 0x11, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0f, 0x11, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0f,
+	0x11, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0f, 0x11, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00,
+	0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x02, 0x03, 0x00, 0x88, 0x88, 0x00};
+
+const static uint8_t rutxpowerlimit_cfg_set_JP[] = {
+	0x6d, 0x02, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x04, 0x06, 0x0a, 0x0c,
+	0x00, 0x00, 0x00, 0x04, 0x06, 0x0a, 0x0c, 0x00, 0x00, 0x00, 0x04, 0x06, 0x0a, 0x0c, 0x00, 0x00,
+	0x00, 0x06, 0x08, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x02, 0x05, 0x07, 0x07, 0x00, 0x00, 0x00, 0x02,
+	0x05, 0x07, 0x07, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e,
+	0x0e, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00,
+	0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00, 0x00, 0x00, 0x09, 0x0c, 0x0e, 0x0e, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x02, 0x03, 0x00, 0x88, 0x88, 0x00};
+
+const static uint8_t rutxpowerlimit_cfg_set_CN[] = {
+	0x6d, 0x02, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x05, 0x09, 0x0c, 0x10,
+	0x00, 0x00, 0x00, 0x05, 0x09, 0x0c, 0x10, 0x00, 0x00, 0x00, 0x05, 0x09, 0x0c, 0x10, 0x00, 0x00,
+	0x00, 0x06, 0x0b, 0x0e, 0x11, 0x00, 0x00, 0x00, 0x06, 0x0b, 0x0e, 0x11, 0x00, 0x00, 0x00, 0x06,
+	0x0b, 0x0e, 0x11, 0x00, 0x00, 0x00, 0x06, 0x0b, 0x0e, 0x11, 0x00, 0x00, 0x00, 0x06, 0x0b, 0x0e,
+	0x11, 0x00, 0x00, 0x00, 0x06, 0x0b, 0x0e, 0x11, 0x00, 0x00, 0x00, 0x0e, 0x11, 0x11, 0x11, 0x00,
+	0x00, 0x00, 0x0e, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x0e, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00,
+	0x10, 0x10, 0x10, 0x0f, 0x00, 0x64, 0x02, 0x03, 0x00, 0x88, 0x88, 0x00};
+#else
+#define MAX_2G_RU_PWR_CHANNELS 26
+#define MAX_5G_RU_PWR_CHANNELS 69
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+const static wlan_rutxpwrlimit_t rutxpowerlimit_2g_cfg_set = {
+    .num_chans            = MAX_2G_RU_PWR_CHANNELS,
+    .rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[10] = {.start_freq = 2407, .width = 20, .chan_num = 11, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[11] = {.start_freq = 2407, .width = 20, .chan_num = 12, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[12] = {.start_freq = 2407, .width = 20, .chan_num = 13, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[13] = {.start_freq = 2407, .width = 40, .chan_num = 1, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[14] = {.start_freq = 2407, .width = 40, .chan_num = 2, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[15] = {.start_freq = 2407, .width = 40, .chan_num = 3, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[16] = {.start_freq = 2407, .width = 40, .chan_num = 4, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[17] = {.start_freq = 2407, .width = 40, .chan_num = 5, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[18] = {.start_freq = 2407, .width = 40, .chan_num = 6, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[19] = {.start_freq = 2407, .width = 40, .chan_num = 7, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[20] = {.start_freq = 2407, .width = 40, .chan_num = 8, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[21] = {.start_freq = 2407, .width = 40, .chan_num = 9, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[22] = {.start_freq = 2407, .width = 40, .chan_num = 10, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[23] = {.start_freq = 2407, .width = 40, .chan_num = 11, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[24] = {.start_freq = 2407, .width = 40, .chan_num = 12, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[25] = {.start_freq = 2407, .width = 40, .chan_num = 13, .ruPower = {-4, -1, 2, 5, 8, 0}},
+};
+
+#if CONFIG_5GHz_SUPPORT
+// coverity[MISRA C-2012 Rule 2.2:SUPPRESS]
+const static wlan_rutxpwrlimit_t rutxpowerlimit_5g_cfg_set = {
+    .num_chans            = MAX_5G_RU_PWR_CHANNELS,
+    .rupwrlimit_config[0] = {.start_freq = 5000, .width = 20, .chan_num = 36, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[1] = {.start_freq = 5000, .width = 20, .chan_num = 40, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[2] = {.start_freq = 5000, .width = 20, .chan_num = 44, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[3] = {.start_freq = 5000, .width = 20, .chan_num = 48, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[4] = {.start_freq = 5000, .width = 20, .chan_num = 52, .ruPower = {-2, 1, 4, 7, 0, 0}},
+
+    .rupwrlimit_config[5] = {.start_freq = 5000, .width = 20, .chan_num = 56, .ruPower = {-2, 1, 4, 7, 0, 0}},
+
+    .rupwrlimit_config[6] = {.start_freq = 5000, .width = 20, .chan_num = 60, .ruPower = {-2, 1, 4, 7, 0, 0}},
+
+    .rupwrlimit_config[7] = {.start_freq = 5000, .width = 20, .chan_num = 64, .ruPower = {-2, 1, 4, 7, 0, 0}},
+
+    .rupwrlimit_config[8] = {.start_freq = 5000, .width = 20, .chan_num = 100, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[9] = {.start_freq = 5000, .width = 20, .chan_num = 104, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[10] = {.start_freq = 5000, .width = 20, .chan_num = 108, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[11] = {.start_freq = 5000, .width = 20, .chan_num = 112, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[12] = {.start_freq = 5000, .width = 20, .chan_num = 116, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[13] = {.start_freq = 5000, .width = 20, .chan_num = 120, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[14] = {.start_freq = 5000, .width = 20, .chan_num = 124, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[15] = {.start_freq = 5000, .width = 20, .chan_num = 128, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[16] = {.start_freq = 5000, .width = 20, .chan_num = 132, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[17] = {.start_freq = 5000, .width = 20, .chan_num = 136, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[18] = {.start_freq = 5000, .width = 20, .chan_num = 140, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[19] = {.start_freq = 5000, .width = 20, .chan_num = 144, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[20] = {.start_freq = 5000, .width = 20, .chan_num = 149, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[21] = {.start_freq = 5000, .width = 20, .chan_num = 153, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[22] = {.start_freq = 5000, .width = 20, .chan_num = 157, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[23] = {.start_freq = 5000, .width = 20, .chan_num = 161, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[24] = {.start_freq = 5000, .width = 20, .chan_num = 165, .ruPower = {-1, 2, 5, 8, 0, 0}},
+
+    .rupwrlimit_config[25] = {.start_freq = 5000, .width = 40, .chan_num = 36, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[26] = {.start_freq = 5000, .width = 40, .chan_num = 40, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[27] = {.start_freq = 5000, .width = 40, .chan_num = 44, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[28] = {.start_freq = 5000, .width = 40, .chan_num = 48, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[29] = {.start_freq = 5000, .width = 40, .chan_num = 52, .ruPower = {-5, -2, 1, 4, 7, 0}},
+
+    .rupwrlimit_config[30] = {.start_freq = 5000, .width = 40, .chan_num = 56, .ruPower = {-5, -2, 1, 4, 7, 0}},
+
+    .rupwrlimit_config[31] = {.start_freq = 5000, .width = 40, .chan_num = 60, .ruPower = {-5, -2, 1, 4, 7, 0}},
+
+    .rupwrlimit_config[32] = {.start_freq = 5000, .width = 40, .chan_num = 64, .ruPower = {-5, -2, 1, 4, 7, 0}},
+
+    .rupwrlimit_config[33] = {.start_freq = 5000, .width = 40, .chan_num = 100, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[34] = {.start_freq = 5000, .width = 40, .chan_num = 104, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[35] = {.start_freq = 5000, .width = 40, .chan_num = 108, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[36] = {.start_freq = 5000, .width = 40, .chan_num = 112, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[37] = {.start_freq = 5000, .width = 40, .chan_num = 116, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[38] = {.start_freq = 5000, .width = 40, .chan_num = 120, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[39] = {.start_freq = 5000, .width = 40, .chan_num = 124, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[40] = {.start_freq = 5000, .width = 40, .chan_num = 128, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[41] = {.start_freq = 5000, .width = 40, .chan_num = 132, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[42] = {.start_freq = 5000, .width = 40, .chan_num = 136, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[43] = {.start_freq = 5000, .width = 40, .chan_num = 140, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[44] = {.start_freq = 5000, .width = 40, .chan_num = 144, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[45] = {.start_freq = 5000, .width = 40, .chan_num = 149, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[46] = {.start_freq = 5000, .width = 40, .chan_num = 153, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[47] = {.start_freq = 5000, .width = 40, .chan_num = 157, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[48] = {.start_freq = 5000, .width = 40, .chan_num = 161, .ruPower = {-4, -1, 2, 5, 8, 0}},
+
+    .rupwrlimit_config[49] = {.start_freq = 5000, .width = 80, .chan_num = 36, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[50] = {.start_freq = 5000, .width = 80, .chan_num = 40, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[51] = {.start_freq = 5000, .width = 80, .chan_num = 44, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[52] = {.start_freq = 5000, .width = 80, .chan_num = 48, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[53] = {.start_freq = 5000, .width = 80, .chan_num = 52, .ruPower = {-8, -5, -2, 1, 4, 7}},
+
+    .rupwrlimit_config[54] = {.start_freq = 5000, .width = 80, .chan_num = 56, .ruPower = {-8, -5, -2, 1, 4, 7}},
+
+    .rupwrlimit_config[55] = {.start_freq = 5000, .width = 80, .chan_num = 60, .ruPower = {-8, -5, -2, 1, 4, 7}},
+
+    .rupwrlimit_config[56] = {.start_freq = 5000, .width = 80, .chan_num = 64, .ruPower = {-8, -5, -2, 1, 4, 7}},
+
+    .rupwrlimit_config[57] = {.start_freq = 5000, .width = 80, .chan_num = 100, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[58] = {.start_freq = 5000, .width = 80, .chan_num = 104, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[59] = {.start_freq = 5000, .width = 80, .chan_num = 108, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[60] = {.start_freq = 5000, .width = 80, .chan_num = 112, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[61] = {.start_freq = 5000, .width = 80, .chan_num = 116, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[62] = {.start_freq = 5000, .width = 80, .chan_num = 120, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[63] = {.start_freq = 5000, .width = 80, .chan_num = 124, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[64] = {.start_freq = 5000, .width = 80, .chan_num = 128, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[65] = {.start_freq = 5000, .width = 80, .chan_num = 149, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[66] = {.start_freq = 5000, .width = 80, .chan_num = 153, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[67] = {.start_freq = 5000, .width = 80, .chan_num = 157, .ruPower = {-7, -4, -1, 2, 5, 8}},
+
+    .rupwrlimit_config[68] = {.start_freq = 5000, .width = 80, .chan_num = 161, .ruPower = {-7, -4, -1, 2, 5, 8}},
+};
+#endif /* CONFIG_5GHz_SUPPORT */
+#endif /* CONFIG_COMPRESS_RU_TX_PWTBL */
+#endif /* CONFIG_11AX */
+
+#endif /* _WLAN_TXPWRLIMIT_CFG_WW_RW610_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/RW612.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/RW612.h
new file mode 100644
index 0000000000..34c73b3693
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/RW612.h
@@ -0,0 +1,79854 @@
+/*
+** ###################################################################
+**     Processors:          RW612ETA2I
+**                          RW612HNA2I
+**                          RW612UKA2I
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RW61X User manual Rev. 0.95, June 2022
+**     Version:             rev. 1.0, 2021-03-16
+**     Build:               b240411
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for RW612
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2021-03-16)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RW612.h
+ * @version 1.0
+ * @date 2021-03-16
+ * @brief CMSIS Peripheral Access Layer for RW612
+ *
+ * CMSIS Peripheral Access Layer for RW612
+ */
+
+#if !defined(RW612_H_)
+#define RW612_H_                                 /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+/* ----------------------------------------------------------------------------
+   --
+   ---------------------------------------------------------------------------- */
+
+/* global Backward compatibility */
+#define MRT0_IRQn                                MRT_IRQn
+#define MRT0_IRQHandler                          MRT_IRQHandler
+#define MRT0_DriverIRQHandler                    MRT_DriverIRQHandler
+#define MRT1_IRQn                                GFMRT_IRQn
+#define MRT1_IRQHandler                          GFMRT_IRQHandler
+#define MRT1_DriverIRQHandler                    GFMRT_DriverIRQHandler
+#define DMIC0_IRQn                               DMIC_IRQn
+#define DMIC0_IRQHandler                         DMIC_IRQHandler
+#define DMIC0_DriverIRQHandler                   DMIC_DriverIRQHandler
+#define WFD_IRQn                                 WKDEEPSLEEP_IRQn
+#define WFD_IRQHandler                           WKDEEPSLEEP_IRQHandler
+#define WFD_DriverIRQHandler                     WKDEEPSLEEP_DriverIRQHandler
+#define HWVAD0_IRQn                              HWVAD_IRQn
+#define HWVAD0_IRQHandler                        HWVAD_IRQHandler
+#define HWVAD0_DriverIRQHandler                  HWVAD_DriverIRQHandler
+#define OS_EVENT_IRQn                            OS_EVENT_TIMER_IRQn
+#define OS_EVENT_IRQHandler                      OS_EVENT_TIMER_IRQHandler
+#define OS_EVENT_DriverIRQHandler                OS_EVENT_TIMER_DriverIRQHandler
+#define SDU_IRQn                                 SDIO_IRQn
+#define SDU_IRQHandler                           SDIO_IRQHandler
+#define SDU_DriverIRQHandler                     SDIO_DriverIRQHandler
+#define LCDIC_IRQn                               LCD_IRQn
+#define LCDIC_IRQHandler                         LCD_IRQHandler
+#define LCDIC_DriverIRQHandler                   LCD_DriverIRQHandler
+#define CAPT_PULSE_IRQn                          CAPTIMER_IRQn
+#define CAPT_PULSE_IRQHandler                    CAPTIMER_IRQHandler
+#define CAPT_PULSE_DriverIRQHandler              CAPTIMER_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE0_IRQn                 W2MWKUP_DONE0_IRQn
+#define WL_MCI_WAKEUP_DONE0_IRQHandler           W2MWKUP_DONE0_IRQHandler
+#define WL_MCI_WAKEUP_DONE0_DriverIRQHandler     W2MWKUP_DONE0_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE1_IRQn                 W2MWKUP_DONE1_IRQn
+#define WL_MCI_WAKEUP_DONE1_IRQHandler           W2MWKUP_DONE1_IRQHandler
+#define WL_MCI_WAKEUP_DONE1_DriverIRQHandler     W2MWKUP_DONE1_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE2_IRQn                 W2MWKUP_DONE2_IRQn
+#define WL_MCI_WAKEUP_DONE2_IRQHandler           W2MWKUP_DONE2_IRQHandler
+#define WL_MCI_WAKEUP_DONE2_DriverIRQHandler     W2MWKUP_DONE2_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE3_IRQn                 W2MWKUP_DONE3_IRQn
+#define WL_MCI_WAKEUP_DONE3_IRQHandler           W2MWKUP_DONE3_IRQHandler
+#define WL_MCI_WAKEUP_DONE3_DriverIRQHandler     W2MWKUP_DONE3_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE4_IRQn                 W2MWKUP_DONE4_IRQn
+#define WL_MCI_WAKEUP_DONE4_IRQHandler           W2MWKUP_DONE4_IRQHandler
+#define WL_MCI_WAKEUP_DONE4_DriverIRQHandler     W2MWKUP_DONE4_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE5_IRQn                 W2MWKUP_DONE5_IRQn
+#define WL_MCI_WAKEUP_DONE5_IRQHandler           W2MWKUP_DONE5_IRQHandler
+#define WL_MCI_WAKEUP_DONE5_DriverIRQHandler     W2MWKUP_DONE5_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE6_IRQn                 W2MWKUP_DONE6_IRQn
+#define WL_MCI_WAKEUP_DONE6_IRQHandler           W2MWKUP_DONE6_IRQHandler
+#define WL_MCI_WAKEUP_DONE6_DriverIRQHandler     W2MWKUP_DONE6_DriverIRQHandler
+#define WL_MCI_WAKEUP_DONE7_IRQn                 W2MWKUP_DONE7_IRQn
+#define WL_MCI_WAKEUP_DONE7_IRQHandler           W2MWKUP_DONE7_IRQHandler
+#define WL_MCI_WAKEUP_DONE7_DriverIRQHandler     W2MWKUP_DONE7_DriverIRQHandler
+#define WL_MCI_WAKEUP0_IRQn                      W2MWKUP0_IRQn
+#define WL_MCI_WAKEUP0_IRQHandler                W2MWKUP0_IRQHandler
+#define WL_MCI_WAKEUP0_DriverIRQHandler          W2MWKUP0_DriverIRQHandler
+#define WL_MCI_WAKEUP1_IRQn                      W2MWKUP1_IRQn
+#define WL_MCI_WAKEUP1_IRQHandler                W2MWKUP1_IRQHandler
+#define WL_MCI_WAKEUP1_DriverIRQHandler          W2MWKUP1_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE0_IRQn                B2MWKUP_DONE0_IRQn
+#define BLE_MCI_WAKEUP_DONE0_IRQHandler          B2MWKUP_DONE0_IRQHandler
+#define BLE_MCI_WAKEUP_DONE0_DriverIRQHandler    B2MWKUP_DONE0_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE1_IRQn                B2MWKUP_DONE1_IRQn
+#define BLE_MCI_WAKEUP_DONE1_IRQHandler          B2MWKUP_DONE1_IRQHandler
+#define BLE_MCI_WAKEUP_DONE1_DriverIRQHandler    B2MWKUP_DONE1_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE2_IRQn                B2MWKUP_DONE2_IRQn
+#define BLE_MCI_WAKEUP_DONE2_IRQHandler          B2MWKUP_DONE2_IRQHandler
+#define BLE_MCI_WAKEUP_DONE2_DriverIRQHandler    B2MWKUP_DONE2_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE3_IRQn                B2MWKUP_DONE3_IRQn
+#define BLE_MCI_WAKEUP_DONE3_IRQHandler          B2MWKUP_DONE3_IRQHandler
+#define BLE_MCI_WAKEUP_DONE3_DriverIRQHandler    B2MWKUP_DONE3_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE4_IRQn                B2MWKUP_DONE4_IRQn
+#define BLE_MCI_WAKEUP_DONE4_IRQHandler          B2MWKUP_DONE4_IRQHandler
+#define BLE_MCI_WAKEUP_DONE4_DriverIRQHandler    B2MWKUP_DONE4_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE5_IRQn                B2MWKUP_DONE5_IRQn
+#define BLE_MCI_WAKEUP_DONE5_IRQHandler          B2MWKUP_DONE5_IRQHandler
+#define BLE_MCI_WAKEUP_DONE5_DriverIRQHandler    B2MWKUP_DONE5_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE6_IRQn                B2MWKUP_DONE6_IRQn
+#define BLE_MCI_WAKEUP_DONE6_IRQHandler          B2MWKUP_DONE6_IRQHandler
+#define BLE_MCI_WAKEUP_DONE6_DriverIRQHandler    B2MWKUP_DONE6_DriverIRQHandler
+#define BLE_MCI_WAKEUP_DONE7_IRQn                B2MWKUP_DONE7_IRQn
+#define BLE_MCI_WAKEUP_DONE7_IRQHandler          B2MWKUP_DONE7_IRQHandler
+#define BLE_MCI_WAKEUP_DONE7_DriverIRQHandler    B2MWKUP_DONE7_DriverIRQHandler
+#define BLE_MCI_WAKEUP0_IRQn                     B2MWKUP0_IRQn
+#define BLE_MCI_WAKEUP0_IRQHandler               B2MWKUP0_IRQHandler
+#define BLE_MCI_WAKEUP0_DriverIRQHandler         B2MWKUP0_DriverIRQHandler
+#define BLE_MCI_WAKEUP1_IRQn                     B2MWKUP1_IRQn
+#define BLE_MCI_WAKEUP1_IRQHandler               B2MWKUP1_IRQHandler
+#define BLE_MCI_WAKEUP1_DriverIRQHandler         B2MWKUP1_DriverIRQHandler
+#define ELS_GDET_IRQ_IRQn                        ELS_GDET_IRQn
+#define ELS_GDET_IRQ_IRQHandler                  ELS_GDET_IRQHandler
+#define ELS_GDET_IRQ_DriverIRQHandler            ELS_GDET_DriverIRQHandler
+#define ELS_GDET_ERR_IRQn                        ELS_GDET_UM_IRQn
+#define ELS_GDET_ERR_IRQHandler                  ELS_GDET_UM_IRQHandler
+#define ELS_GDET_ERR_DriverIRQHandler            ELS_GDET_UM_DriverIRQHandler
+#define PKC_IRQn                                 PKC_INT_IRQn
+#define PKC_IRQHandler                           PKC_INT_IRQHandler
+#define PKC_DriverIRQHandler                     PKC_INT_DriverIRQHandler
+#define CDOG_IRQn                                CDOG_INT_IRQn
+#define CDOG_IRQHandler                          CDOG_INT_IRQHandler
+#define CDOG_DriverIRQHandler                    CDOG_INT_DriverIRQHandler
+#define GAU_GPDAC_INT_FUNC11_IRQn                GAU_DAC_IRQn
+#define GAU_GPDAC_INT_FUNC11_IRQHandler          GAU_DAC_IRQHandler
+#define GAU_GPDAC_INT_FUNC11_DriverIRQHandler    GAU_DAC_DriverIRQHandler
+#define GAU_ACOMP_INT_WKUP11_IRQn                GAU_ACOMP_WKUP_IRQn
+#define GAU_ACOMP_INT_WKUP11_IRQHandler          GAU_ACOMP_WKUP_IRQHandler
+#define GAU_ACOMP_INT_WKUP11_DriverIRQHandler    GAU_ACOMP_WKUP_DriverIRQHandler
+#define GAU_ACOMP_INT_FUNC11_IRQn                GAU_ACOMP_IRQn
+#define GAU_ACOMP_INT_FUNC11_IRQHandler          GAU_ACOMP_IRQHandler
+#define GAU_ACOMP_INT_FUNC11_DriverIRQHandler    GAU_ACOMP_DriverIRQHandler
+#define GAU_GPADC1_INT_FUNC11_IRQn               GAU_ADC1_IRQn
+#define GAU_GPADC1_INT_FUNC11_IRQHandler         GAU_ADC1_IRQHandler
+#define GAU_GPADC1_INT_FUNC11_DriverIRQHandler   GAU_ADC1_DriverIRQHandler
+#define GAU_GPADC0_INT_FUNC11_IRQn               GAU_ADC0_IRQn
+#define GAU_GPADC0_INT_FUNC11_IRQHandler         GAU_ADC0_IRQHandler
+#define GAU_GPADC0_INT_FUNC11_DriverIRQHandler   GAU_ADC0_DriverIRQHandler
+#define OCOTP_IRQn                               OTP_IRQn
+#define OCOTP_IRQHandler                         OTP_IRQHandler
+#define OCOTP_DriverIRQHandler                   OTP_DriverIRQHandler
+#define BOD_1_85_INT_IRQn                        PMIP_IRQn
+#define BOD_1_85_INT_IRQHandler                  PMIP_IRQHandler
+#define BOD_1_85_INT_DriverIRQHandler            PMIP_DriverIRQHandler
+#define BOD_1_85_NEG_IRQn                        PMIP_CHANGE_IRQn
+#define BOD_1_85_NEG_IRQHandler                  PMIP_CHANGE_IRQHandler
+#define BOD_1_85_NEG_DriverIRQHandler            PMIP_CHANGE_DriverIRQHandler
+#define AHB_MEM_ACC_CHECKER_VIO_INT_C_OR_IRQn               ACC_C_INT_IRQn
+#define AHB_MEM_ACC_CHECKER_VIO_INT_C_OR_IRQHandler         ACC_C_INT_IRQHandler
+#define AHB_MEM_ACC_CHECKER_VIO_INT_C_OR_DriverIRQHandler   ACC_C_INT_DriverIRQHandler
+#define AHB_MEM_ACC_CHECKER_VIO_INT_S_OR_IRQn               ACC_S_INT_IRQn
+#define AHB_MEM_ACC_CHECKER_VIO_INT_S_OR_IRQHandler         ACC_S_INT_IRQHandler
+#define AHB_MEM_ACC_CHECKER_VIO_INT_S_OR_DriverIRQHandler   ACC_S_INT_DriverIRQHandler
+#define WL_ACC_INT_IRQn                          WACC_IRQn
+#define WL_ACC_INT_IRQHandler                    WACC_IRQHandler
+#define WL_ACC_INT_DriverIRQHandler              WACC_DriverIRQHandler
+#define BLE_ACC_INT_IRQn                         BACC_IRQn
+#define BLE_ACC_INT_IRQHandler                   BACC_IRQHandler
+#define BLE_ACC_INT_DriverIRQHandler             BACC_DriverIRQHandler
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 145                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
+  SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT0_IRQn                    = 0,                /**< Windowed watchdog timer 0 (WDT0)(Cortex-M33 watchdog) */
+  DMA0_IRQn                    = 1,                /**< Direct memory access (DMA) controller 0 (secure or Cortex-M33 DMA) */
+  GPIO_INTA_IRQn               = 2,                /**< GPIO interrupt A */
+  GPIO_INTB_IRQn               = 3,                /**< GPIO interrupt B */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1 or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK_IRQn                   = 8,                /**< Micro-tick Timer (UTICK) */
+  MRT_IRQn                     = 9,                /**< Multi-Rate Timer (MRT). Global MRT interrupts */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S) */
+  Reserved34_IRQn              = 18,               /**< Reserved interrupt */
+  Reserved35_IRQn              = 19,               /**< Reserved interrupt */
+  FLEXCOMM14_IRQn              = 20,               /**< Flexcomm Interface 14 (USART, SPI, I2C, I2S) */
+  Reserved37_IRQn              = 21,               /**< Reserved interrupt */
+  Reserved38_IRQn              = 22,               /**< Reserved interrupt */
+  GFMRT_IRQn                   = 23,               /**< Free Multi-rate timer (GFMRT). Global MRT interrupts */
+  Reserved40_IRQn              = 24,               /**< Reserved interrupt */
+  DMIC_IRQn                    = 25,               /**< Digital microphone (DMIC) and DMIC subsystem */
+  WKDEEPSLEEP_IRQn             = 26,               /**< Wake-up from deep sleep */
+  HYPERVISOR_IRQn              = 27,               /**< Hypervisor service software interrupt */
+  SECUREVIOLATION_IRQn         = 28,               /**< Secure violation */
+  HWVAD_IRQn                   = 29,               /**< Hardware Voice Activity Detector */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt */
+  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
+  RTC_IRQn                     = 32,               /**< RTC alarm and wake-up */
+  Reserved49_IRQn              = 33,               /**< Reserved interrupt */
+  Reserved50_IRQn              = 34,               /**< Reserved interrupt */
+  PIN_INT4_IRQn                = 35,               /**< Pin interrupt 4 or pattern match engine slice 4 */
+  PIN_INT5_IRQn                = 36,               /**< Pin interrupt 5 or pattern match engine slice 5 */
+  PIN_INT6_IRQn                = 37,               /**< Pin interrupt 6 or pattern match engine slice 6 */
+  PIN_INT7_IRQn                = 38,               /**< Pin interrupt 7 or pattern match engine slice 7 */
+  CTIMER2_IRQn                 = 39,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 40,               /**< Standard counter/timer CTIMER4 */
+  OS_EVENT_TIMER_IRQn          = 41,               /**< OS event timer 0 */
+  FLEXSPI_IRQn                 = 42,               /**< FLEXSPI interface */
+  Reserved59_IRQn              = 43,               /**< Reserved interrupt */
+  Reserved60_IRQn              = 44,               /**< Reserved interrupt */
+  Reserved61_IRQn              = 45,               /**< Reserved interrupt */
+  SDIO_IRQn                    = 46,               /**< The secure digital interface */
+  SGPIO_INTA_IRQn              = 47,               /**< Secure GPIO interrupt A */
+  SGPIO_INTB_IRQn              = 48,               /**< Secure GPIO interrupt B */
+  Reserved65_IRQn              = 49,               /**< Reserved interrupt */
+  USB_IRQn                     = 50,               /**< High-speed USB device/host */
+  Reserved67_IRQn              = 51,               /**< Reserved interrupt */
+  Reserved68_IRQn              = 52,               /**< Reserved interrupt */
+  Reserved69_IRQn              = 53,               /**< Reserved interrupt */
+  DMA1_IRQn                    = 54,               /**< DMA controller 1 (non-secure or HiFi 4 DMA) */
+  PUF_IRQn                     = 55,               /**< Physical Unclonable Function */
+  POWERQUAD_IRQn               = 56,               /**< PowerQuad math coprocessor */
+  Reserved73_IRQn              = 57,               /**< Reserved interrupt */
+  Reserved74_IRQn              = 58,               /**< Reserved interrupt */
+  Reserved75_IRQn              = 59,               /**< Reserved interrupt */
+  Reserved76_IRQn              = 60,               /**< Reserved interrupt */
+  LCD_IRQn                     = 61,               /**< LCDIC */
+  CAPTIMER_IRQn                = 62,               /**< Capture timer */
+  Reserved79_IRQn              = 63,               /**< Reserved interrupt */
+  W2MWKUP_DONE0_IRQn           = 64,               /**< Wi-Fi to MCU, wakeup done 0 */
+  W2MWKUP_DONE1_IRQn           = 65,               /**< Wi-Fi to MCU, wakeup done 1 */
+  W2MWKUP_DONE2_IRQn           = 66,               /**< Wi-Fi to MCU, wakeup done 2 */
+  W2MWKUP_DONE3_IRQn           = 67,               /**< Wi-Fi to MCU, wakeup done 3 */
+  W2MWKUP_DONE4_IRQn           = 68,               /**< Wi-Fi to MCU, wakeup done 4 */
+  W2MWKUP_DONE5_IRQn           = 69,               /**< Wi-Fi to MCU, wakeup done 5 */
+  W2MWKUP_DONE6_IRQn           = 70,               /**< Wi-Fi to MCU, wakeup done 6 */
+  W2MWKUP_DONE7_IRQn           = 71,               /**< Wi-Fi to MCU, wakeup done 7 */
+  W2MWKUP0_IRQn                = 72,               /**< Wi-Fi to MCU, wakeup signal 0 */
+  W2MWKUP1_IRQn                = 73,               /**< Wi-Fi to MCU, wakueup signal 1 */
+  WL_MCI_INT0_IRQn             = 74,               /**< Wi-Fi to MCU interrupt 0 */
+  WL_MCI_INT1_IRQn             = 75,               /**< Reserved for Wi-Fi to MCU */
+  WL_MCI_INT2_IRQn             = 76,               /**< Reserved for Wi-Fi to MCU */
+  WL_MCI_INT3_IRQn             = 77,               /**< Reserved for Wi-Fi to MCU */
+  WL_MCI_INT4_IRQn             = 78,               /**< Reserved for Wi-Fi to MCU */
+  WL_MCI_INT5_IRQn             = 79,               /**< Reserved for Wi-Fi to MCU */
+  WL_MCI_INT6_IRQn             = 80,               /**< Reserved for Wi-Fi to MCU */
+  WL_MCI_INT7_IRQn             = 81,               /**< Reserved for Wi-Fi to MCU */
+  B2MWKUP_DONE0_IRQn           = 82,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 0 */
+  B2MWKUP_DONE1_IRQn           = 83,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 1 */
+  B2MWKUP_DONE2_IRQn           = 84,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 2 */
+  B2MWKUP_DONE3_IRQn           = 85,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 3 */
+  B2MWKUP_DONE4_IRQn           = 86,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 4 */
+  B2MWKUP_DONE5_IRQn           = 87,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 5 */
+  B2MWKUP_DONE6_IRQn           = 88,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 6 */
+  B2MWKUP_DONE7_IRQn           = 89,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup done 7 */
+  B2MWKUP0_IRQn                = 90,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup signal 0 */
+  B2MWKUP1_IRQn                = 91,               /**< Bluetooth LE/802.15.4 radio to MCU, wakeup signal 1 */
+  BLE_MCI_INT0_IRQn            = 92,               /**< Bluetooth LE/802.15.4 radio to MCU interrupt 0 */
+  BLE_MCI_INT1_IRQn            = 93,               /**< Reserved for Bluetooth LE/802.15.4 radio to MCU */
+  BLE_MCI_INT2_IRQn            = 94,               /**< Reserved for Bluetooth LE/802.15.4 radio to MCU */
+  BLE_MCI_INT3_IRQn            = 95,               /**< Reserved for Bluetooth LE/802.15.4 radio to MCU */
+  BLE_MCI_INT4_IRQn            = 96,               /**< Reserved for Bluetooth LE/802.15.4 radio to MCU */
+  BLE_MCI_INT5_IRQn            = 97,               /**< Reserved for Bluetooth LE/802.15.4 radio to MCU */
+  BLE_MCI_INT6_IRQn            = 98,               /**< Reserved for Bluetooth LE/802.15.4 radio to MCU */
+  BLE_MCI_INT7_IRQn            = 99,               /**< Reserved for Bluetooth LE/802.15.4 radio to MCU */
+  PIN0_INT_IRQn                = 100,              /**< From AON GPIO */
+  PIN1_INT_IRQn                = 101,              /**< From AON GPIO */
+  ELS_IRQn                     = 102,              /**< EdgeLock subsystem (ELS) */
+  ELS_GDET_IRQn                = 103,              /**< ELS IRQ line for GDET error */
+  ELS_GDET_UM_IRQn             = 104,              /**< ELS un-gated latched error */
+  PKC_INT_IRQn                 = 105,              /**< Public key crypto-processor (PKC) interrupt */
+  PKC_ERR_IRQn                 = 106,              /**< PKC error */
+  CDOG_INT_IRQn                = 107,              /**< Code watch dog timmer interrupt */
+  GAU_DAC_IRQn                 = 108,              /**< General analog unit (GAU) digital to analog converter (DAC) */
+  GAU_ACOMP_WKUP_IRQn          = 109,              /**< GAU analog comparator (ACOMP) wake-up */
+  GAU_ACOMP_IRQn               = 110,              /**< GAU analog comparator */
+  GAU_ADC1_IRQn                = 111,              /**< GAU analog to digital converter 1 (ADC1) */
+  GAU_ADC0_IRQn                = 112,              /**< GAU analog to digital converter 0 (ADC0) */
+  USIM_IRQn                    = 113,              /**< Universal subscriber identity module (USIM) interface */
+  OTP_IRQn                     = 114,              /**< One time programmable (OTP) memory interrupt */
+  ENET_IRQn                    = 115,              /**< Etheret interrupt */
+  ENET_TIMER_IRQn              = 116,              /**< Ethernet timer interrupt */
+  PMIP_IRQn                    = 117,              /**< Power management IP (PMIP) */
+  PMIP_CHANGE_IRQn             = 118,              /**< PMIP change from 1 to 0 */
+  ITRC_IRQn                    = 119,              /**< Intrusion and tamper response controller (ITRC) interrupt request */
+  Reserved136_IRQn             = 120,              /**< Reserved interrupt */
+  Reserved137_IRQn             = 121,              /**< Reserved interrupt */
+  Reserved138_IRQn             = 122,              /**< Reserved interrupt */
+  TRNG_IRQn                    = 123,              /**< TRNG interrupt request */
+  ACC_C_INT_IRQn               = 124,              /**< AHB memory access checker - Cortex-M33 code bus */
+  ACC_S_INT_IRQn               = 125,              /**< AHB memory access checker - Cortex-M33 sys bus */
+  WACC_IRQn                    = 126,              /**< Wi-Fi accessed during power off */
+  BACC_IRQn                    = 127,              /**< Bluetooth LE/802.15.4 radio accessed during power off */
+  GDMA_IRQn                    = 128               /**< General purpose direct memory access (GDMA) interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M33 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+#define __DSP_PRESENT                  0         /**< Defines if Armv8-M Mainline core supports DSP instructions */
+#define __SAUREGION_PRESENT            1         /**< Defines if an SAU is present or not */
+
+#include "core_cm33.h"                 /* Core Peripheral Access Layer */
+#include "system_RW612.h"              /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief The enumeration of dac channel trigger sources.
+ */
+
+typedef enum _dac_channel_trigger_source
+{
+    kDAC_TriggerSourceCtimer1Match2 = 0U,          /**< Use CTimer1 match 2 as trigger source. */
+    kDAC_TriggerSourceCtimer1Match1 = 1U,          /**< Use CTimer1 match 1 as trigger source. */
+    kDAC_TriggerSourceGpio50        = 2U,          /**< Use GPIO50 as trigger source. */
+    kDAC_TriggerSourceGpio55        = 3U,          /**< Use GPIO55 as trigger source. */
+} dac_channel_trigger_source_t;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief ADC trigger source, including software trigger and multiple hardware trigger sources.
+ */
+
+typedef enum _adc_trigger_source
+{
+    kADC_TriggerSourceCtimer        = 0U,          /**< Hardware trigger, trigger source 0:CTimer3_match1 for ADC0, CTimer3_match2 for ADC1. */
+    kADC_TriggerSourceAcomp         = 1U,          /**< Hardware trigger, trigger source 1: ACOMP0 for ADC0, ACMP1 for ADC1. */
+    kADC_TriggerSourceGpio50        = 2U,          /**< Hardware trigger, trigger source 2: GPIO50. */
+    kADC_TriggerSourceGpio55        = 3U,          /**< Hardware trigger, trigger source 3: GPIO55. */
+    kADC_TriggerSourceSoftware      = 4U,          /**< Software trigger. */
+} adc_trigger_source_t;
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ACOMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer
+ * @{
+ */
+
+/** ACOMP - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL0;                             /**< ACOMP0 Control Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< ACOMP1 Control Register, offset: 0x4 */
+  __I  uint32_t STATUS0;                           /**< ACOMP0 Status Register, offset: 0x8 */
+  __I  uint32_t STATUS1;                           /**< ACOMP1 Status Register, offset: 0xC */
+  __IO uint32_t ROUTE0;                            /**< ACOMP0 Route Register, offset: 0x10 */
+  __IO uint32_t ROUTE1;                            /**< ACOMP1 Route Register, offset: 0x14 */
+  __I  uint32_t ISR0;                              /**< ACOMP0 Interrupt Status Register, offset: 0x18 */
+  __I  uint32_t ISR1;                              /**< ACOMP1 Interrupt Status Register, offset: 0x1C */
+  __IO uint32_t IMR0;                              /**< ACOMP0 Interrupt Mask Register, offset: 0x20 */
+  __IO uint32_t IMR1;                              /**< ACOMP1 Interrupt Mask Register, offset: 0x24 */
+  __I  uint32_t IRSR0;                             /**< ACOMP0 Interrupt Raw Status Register, offset: 0x28 */
+  __I  uint32_t IRSR1;                             /**< ACOMP1 Interrupt Raw Status Register, offset: 0x2C */
+  __IO uint32_t ICR0;                              /**< ACOMP0 Interrupt Clear Register, offset: 0x30 */
+  __IO uint32_t ICR1;                              /**< ACOMP1 Interrupt Clear Register, offset: 0x34 */
+  __IO uint32_t RST0;                              /**< ACOMP0 Soft Reset Register, offset: 0x38 */
+  __IO uint32_t RST1;                              /**< ACOMP1 Soft Reset Register, offset: 0x3C */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CLK;                               /**< Clock Register, offset: 0x48 */
+} ACOMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ACOMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACOMP_Register_Masks ACOMP Register Masks
+ * @{
+ */
+
+/*! @name CTRL0 - ACOMP0 Control Register */
+/*! @{ */
+
+#define ACOMP_CTRL0_EN_MASK                      (0x1U)
+#define ACOMP_CTRL0_EN_SHIFT                     (0U)
+/*! EN - ACOMP0 enable
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_CTRL0_EN(x)                        (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_EN_SHIFT)) & ACOMP_CTRL0_EN_MASK)
+
+#define ACOMP_CTRL0_GPIOINV_MASK                 (0x2U)
+#define ACOMP_CTRL0_GPIOINV_SHIFT                (1U)
+/*! GPIOINV - Enable/Disable inversion of ACOMP0 output to GPIO.
+ *  0b0..do not invert ACOMP0 output
+ *  0b1..invert ACOMP0 output
+ */
+#define ACOMP_CTRL0_GPIOINV(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_GPIOINV_SHIFT)) & ACOMP_CTRL0_GPIOINV_MASK)
+
+#define ACOMP_CTRL0_WARMTIME_MASK                (0xCU)
+#define ACOMP_CTRL0_WARMTIME_SHIFT               (2U)
+/*! WARMTIME - Set ACOMP0 Warm-Up time
+ *  0b00..1 us
+ *  0b01..2 us
+ *  0b10..4 us
+ *  0b11..8 us
+ */
+#define ACOMP_CTRL0_WARMTIME(x)                  (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_WARMTIME_SHIFT)) & ACOMP_CTRL0_WARMTIME_MASK)
+
+#define ACOMP_CTRL0_HYST_SELN_MASK               (0x70U)
+#define ACOMP_CTRL0_HYST_SELN_SHIFT              (4U)
+/*! HYST_SELN - Select ACOMP0 negative hysteresis voltage level.
+ *  0b000..no hysteresis
+ *  0b001..-10 mV hysteresis
+ *  0b010..-20 mV hysteresis
+ *  0b011..-30 mV hysteresis
+ *  0b100..-40 mV hysteresis
+ *  0b101..-50 mV hysteresis
+ *  0b110..-60 mV hysteresis
+ *  0b111..-70 mV hysteresis
+ */
+#define ACOMP_CTRL0_HYST_SELN(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_HYST_SELN_SHIFT)) & ACOMP_CTRL0_HYST_SELN_MASK)
+
+#define ACOMP_CTRL0_HYST_SELP_MASK               (0x380U)
+#define ACOMP_CTRL0_HYST_SELP_SHIFT              (7U)
+/*! HYST_SELP - Select ACOMP0 positive hysteresis voltage level.
+ *  0b000..No hysteresis
+ *  0b001..+10 mV hysteresis
+ *  0b010..+20 mV hysteresis
+ *  0b011..+30 mV hysteresis
+ *  0b100..+40 mV hysteresis
+ *  0b101..+50 mV hysteresis
+ *  0b110..+60 mV hysteresis
+ *  0b111..+70 mV hysteresis
+ */
+#define ACOMP_CTRL0_HYST_SELP(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_HYST_SELP_SHIFT)) & ACOMP_CTRL0_HYST_SELP_MASK)
+
+#define ACOMP_CTRL0_BIAS_PROG_MASK               (0xC00U)
+#define ACOMP_CTRL0_BIAS_PROG_SHIFT              (10U)
+/*! BIAS_PROG - ACOMP0 bias current control bits or response time control bits.
+ *  0b00..power mode1 (fast response mode)
+ *  0b01..power mode2 (medium response mode)
+ *  0b10..power mode3 (slow response mode)
+ *  0b11..Reserved
+ */
+#define ACOMP_CTRL0_BIAS_PROG(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_BIAS_PROG_SHIFT)) & ACOMP_CTRL0_BIAS_PROG_MASK)
+
+#define ACOMP_CTRL0_LEVEL_SEL_MASK               (0x3F000U)
+#define ACOMP_CTRL0_LEVEL_SEL_SHIFT              (12U)
+/*! LEVEL_SEL - Scaling factor select bits for VIO reference level.
+ *  0b000000..Scaling factor=0.25
+ *  0b010000..Scaling factor= 0.5
+ *  0b100000..Scaling factor= 0.75
+ *  0b110000..Scaling factor= 1
+ */
+#define ACOMP_CTRL0_LEVEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_LEVEL_SEL_SHIFT)) & ACOMP_CTRL0_LEVEL_SEL_MASK)
+
+#define ACOMP_CTRL0_NEG_SEL_MASK                 (0x3C0000U)
+#define ACOMP_CTRL0_NEG_SEL_SHIFT                (18U)
+/*! NEG_SEL - ACOMP0 negative input select bits.
+ *  0b0000..acomp_ch<0>
+ *  0b0001..acomp_ch<1>
+ *  0b0010..acomp_ch<2>
+ *  0b0011..acomp_ch<3>
+ *  0b0100..acomp_ch<4>
+ *  0b0101..acomp_ch<5>
+ *  0b0110..acomp_ch<6>
+ *  0b0111..acomp_ch<7>
+ *  0b1000..
+ *  0b1001..
+ *  0b1010..
+ *  0b1011..
+ *  0b1100..vio*scaling factor
+ *  0b1101..vio*scaling factor
+ *  0b1110..vio*scaling factor
+ *  0b1111..vio*scaling factor
+ */
+#define ACOMP_CTRL0_NEG_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_NEG_SEL_SHIFT)) & ACOMP_CTRL0_NEG_SEL_MASK)
+
+#define ACOMP_CTRL0_POS_SEL_MASK                 (0x3C00000U)
+#define ACOMP_CTRL0_POS_SEL_SHIFT                (22U)
+/*! POS_SEL - ACOMP0 positive input select bits.
+ *  0b0000..acomp_ch<0>
+ *  0b0001..acomp_ch<1>
+ *  0b0010..acomp_ch<2>
+ *  0b0011..acomp_ch<3>
+ *  0b0100..acomp_ch<4>
+ *  0b0101..acomp_ch<5>
+ *  0b0110..acomp_ch<6>
+ *  0b0111..acomp_ch<7>
+ *  0b1000..
+ *  0b1001..
+ */
+#define ACOMP_CTRL0_POS_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_POS_SEL_SHIFT)) & ACOMP_CTRL0_POS_SEL_MASK)
+
+#define ACOMP_CTRL0_MUXEN_MASK                   (0x4000000U)
+#define ACOMP_CTRL0_MUXEN_SHIFT                  (26U)
+/*! MUXEN - ACOMP0 input MUX enable bit.
+ *  0b0..disable input mux
+ *  0b1..enable input mux
+ */
+#define ACOMP_CTRL0_MUXEN(x)                     (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_MUXEN_SHIFT)) & ACOMP_CTRL0_MUXEN_MASK)
+
+#define ACOMP_CTRL0_INACT_VAL_MASK               (0x8000000U)
+#define ACOMP_CTRL0_INACT_VAL_SHIFT              (27U)
+/*! INACT_VAL - Set output value when ACOMP0 is inactive.
+ *  0b0..output 0 when ACOMP0 is inactive
+ *  0b1..output 1 when ACOMP0 is inactive
+ */
+#define ACOMP_CTRL0_INACT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_INACT_VAL_SHIFT)) & ACOMP_CTRL0_INACT_VAL_MASK)
+
+#define ACOMP_CTRL0_RIE_MASK                     (0x10000000U)
+#define ACOMP_CTRL0_RIE_SHIFT                    (28U)
+/*! RIE - ACOMP0 enable/disable rising edge triggered edge pulse.
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_CTRL0_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_RIE_SHIFT)) & ACOMP_CTRL0_RIE_MASK)
+
+#define ACOMP_CTRL0_FIE_MASK                     (0x20000000U)
+#define ACOMP_CTRL0_FIE_SHIFT                    (29U)
+/*! FIE - ACOMP0 enable/disable falling edge triggered edge pulse.
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_CTRL0_FIE(x)                       (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_FIE_SHIFT)) & ACOMP_CTRL0_FIE_MASK)
+
+#define ACOMP_CTRL0_INT_ACT_HI_MASK              (0x40000000U)
+#define ACOMP_CTRL0_INT_ACT_HI_SHIFT             (30U)
+/*! INT_ACT_HI - ACOMP0 interrupt active mode select.
+ *  0b0..Low level or falling edge triggered interrupt
+ *  0b1..High level or rising edge triggered interrupt
+ */
+#define ACOMP_CTRL0_INT_ACT_HI(x)                (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_INT_ACT_HI_SHIFT)) & ACOMP_CTRL0_INT_ACT_HI_MASK)
+
+#define ACOMP_CTRL0_EDGE_LEVL_SEL_MASK           (0x80000000U)
+#define ACOMP_CTRL0_EDGE_LEVL_SEL_SHIFT          (31U)
+/*! EDGE_LEVL_SEL - ACOMP0 interrupt type select.
+ *  0b0..level triggered interrupt
+ *  0b1..edge triggered interrupt
+ */
+#define ACOMP_CTRL0_EDGE_LEVL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_EDGE_LEVL_SEL_SHIFT)) & ACOMP_CTRL0_EDGE_LEVL_SEL_MASK)
+/*! @} */
+
+/*! @name CTRL1 - ACOMP1 Control Register */
+/*! @{ */
+
+#define ACOMP_CTRL1_EN_MASK                      (0x1U)
+#define ACOMP_CTRL1_EN_SHIFT                     (0U)
+/*! EN - ACOMP1 enable bit.
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_CTRL1_EN(x)                        (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_EN_SHIFT)) & ACOMP_CTRL1_EN_MASK)
+
+#define ACOMP_CTRL1_GPIOINV_MASK                 (0x2U)
+#define ACOMP_CTRL1_GPIOINV_SHIFT                (1U)
+/*! GPIOINV - Enable/disable inversion of ACOMP1 output to GPIO.
+ *  0b0..do not invert ACOMP1 output
+ *  0b1..invert ACOMP1 output
+ */
+#define ACOMP_CTRL1_GPIOINV(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_GPIOINV_SHIFT)) & ACOMP_CTRL1_GPIOINV_MASK)
+
+#define ACOMP_CTRL1_WARMTIME_MASK                (0xCU)
+#define ACOMP_CTRL1_WARMTIME_SHIFT               (2U)
+/*! WARMTIME - Set ACOMP1 warm-up time.
+ *  0b00..1 us
+ *  0b01..2 us
+ *  0b10..4 us
+ *  0b11..8 us
+ */
+#define ACOMP_CTRL1_WARMTIME(x)                  (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_WARMTIME_SHIFT)) & ACOMP_CTRL1_WARMTIME_MASK)
+
+#define ACOMP_CTRL1_HYST_SELN_MASK               (0x70U)
+#define ACOMP_CTRL1_HYST_SELN_SHIFT              (4U)
+/*! HYST_SELN - Select ACOMP1 negative hysteresis voltage level.
+ *  0b000..No hysteresis
+ *  0b001..-10 mV hysteresis
+ *  0b010..-20 mV hysteresis
+ *  0b011..-30 mV hysteresis
+ *  0b100..-40 mV hysteresis
+ *  0b101..-50 mV hysteresis
+ *  0b110..-60 mV hysteresis
+ *  0b111..-70 mV hysteresis
+ */
+#define ACOMP_CTRL1_HYST_SELN(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_HYST_SELN_SHIFT)) & ACOMP_CTRL1_HYST_SELN_MASK)
+
+#define ACOMP_CTRL1_HYST_SELP_MASK               (0x380U)
+#define ACOMP_CTRL1_HYST_SELP_SHIFT              (7U)
+/*! HYST_SELP - Select ACOMP1 positive hysteresis voltage level.
+ *  0b000..No hysteresis
+ *  0b001..+10 mV hysteresis
+ *  0b010..+20 mV hysteresis
+ *  0b011..+30 mV hysteresis
+ *  0b100..+40 mV hysteresis
+ *  0b101..+50 mV hysteresis
+ *  0b110..+60 mV hysteresis
+ *  0b111..+70 mV hysteresis
+ */
+#define ACOMP_CTRL1_HYST_SELP(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_HYST_SELP_SHIFT)) & ACOMP_CTRL1_HYST_SELP_MASK)
+
+#define ACOMP_CTRL1_BIAS_PROG_MASK               (0xC00U)
+#define ACOMP_CTRL1_BIAS_PROG_SHIFT              (10U)
+/*! BIAS_PROG - ACOMP1 bias current control bits Or response time control bits.
+ *  0b00..power mode1 (fast response mode)
+ *  0b01..power mode2 (Medium response mode)
+ *  0b10..power mode3 (slow response mode)
+ *  0b11..Reserved
+ */
+#define ACOMP_CTRL1_BIAS_PROG(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_BIAS_PROG_SHIFT)) & ACOMP_CTRL1_BIAS_PROG_MASK)
+
+#define ACOMP_CTRL1_LEVEL_SEL_MASK               (0x3F000U)
+#define ACOMP_CTRL1_LEVEL_SEL_SHIFT              (12U)
+/*! LEVEL_SEL - Scaling factor select bits for vio reference level.
+ *  0b000000..Scaling factor=0.25
+ *  0b010000..Scaling factor= 0.5
+ *  0b100000..Scaling factor= 0.75
+ *  0b110000..Scaling factor= 1
+ */
+#define ACOMP_CTRL1_LEVEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_LEVEL_SEL_SHIFT)) & ACOMP_CTRL1_LEVEL_SEL_MASK)
+
+#define ACOMP_CTRL1_NEG_SEL_MASK                 (0x3C0000U)
+#define ACOMP_CTRL1_NEG_SEL_SHIFT                (18U)
+/*! NEG_SEL - ACOMP1 negative input select
+ *  0b0000..acomp_ch<0>
+ *  0b0001..acomp_ch<1>
+ *  0b0010..acomp_ch<2>
+ *  0b0011..acomp_ch<3>
+ *  0b0100..acomp_ch<4>
+ *  0b0101..acomp_ch<5>
+ *  0b0110..acomp_ch<6>
+ *  0b0111..acomp_ch<7>
+ *  0b1000..
+ *  0b1001..
+ *  0b1010..
+ *  0b1011..
+ *  0b1100..vio*scaling factor
+ *  0b1101..vio*scaling factor
+ *  0b1110..vio*scaling factor
+ *  0b1111..vio*scaling factor
+ */
+#define ACOMP_CTRL1_NEG_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_NEG_SEL_SHIFT)) & ACOMP_CTRL1_NEG_SEL_MASK)
+
+#define ACOMP_CTRL1_POS_SEL_MASK                 (0x3C00000U)
+#define ACOMP_CTRL1_POS_SEL_SHIFT                (22U)
+/*! POS_SEL - ACOMP1 positive input select
+ *  0b0000..acomp_ch<0>
+ *  0b0001..acomp_ch<1>
+ *  0b0010..acomp_ch<2>
+ *  0b0011..acomp_ch<3>
+ *  0b0100..acomp_ch<4>
+ *  0b0101..acomp_ch<5>
+ *  0b0110..acomp_ch<6>
+ *  0b0111..acomp_ch<7>
+ *  0b1000..
+ *  0b1001..
+ */
+#define ACOMP_CTRL1_POS_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_POS_SEL_SHIFT)) & ACOMP_CTRL1_POS_SEL_MASK)
+
+#define ACOMP_CTRL1_MUXEN_MASK                   (0x4000000U)
+#define ACOMP_CTRL1_MUXEN_SHIFT                  (26U)
+/*! MUXEN - ACOMP1 input MUX enable
+ *  0b0..disable input mux
+ *  0b1..enable input mux
+ */
+#define ACOMP_CTRL1_MUXEN(x)                     (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_MUXEN_SHIFT)) & ACOMP_CTRL1_MUXEN_MASK)
+
+#define ACOMP_CTRL1_INACT_VAL_MASK               (0x8000000U)
+#define ACOMP_CTRL1_INACT_VAL_SHIFT              (27U)
+/*! INACT_VAL - Set output value when ACOMP1 is inactive.
+ *  0b0..output 0 when ACOMP1 is inactive
+ *  0b1..output 1 when ACOMP1 is inactive
+ */
+#define ACOMP_CTRL1_INACT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_INACT_VAL_SHIFT)) & ACOMP_CTRL1_INACT_VAL_MASK)
+
+#define ACOMP_CTRL1_RIE_MASK                     (0x10000000U)
+#define ACOMP_CTRL1_RIE_SHIFT                    (28U)
+/*! RIE - ACOMP1 enable/disable rising edge triggered edge pulse.
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_CTRL1_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_RIE_SHIFT)) & ACOMP_CTRL1_RIE_MASK)
+
+#define ACOMP_CTRL1_FIE_MASK                     (0x20000000U)
+#define ACOMP_CTRL1_FIE_SHIFT                    (29U)
+/*! FIE - ACOMP1 enable/disable falling edge triggered edge pulse.
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_CTRL1_FIE(x)                       (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_FIE_SHIFT)) & ACOMP_CTRL1_FIE_MASK)
+
+#define ACOMP_CTRL1_INT_ACT_HI_MASK              (0x40000000U)
+#define ACOMP_CTRL1_INT_ACT_HI_SHIFT             (30U)
+/*! INT_ACT_HI - ACOMP1 interrupt active mode select.
+ *  0b0..Low level or falling edge triggered interrupt
+ *  0b1..High level or rising edge triggered interrupt
+ */
+#define ACOMP_CTRL1_INT_ACT_HI(x)                (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_INT_ACT_HI_SHIFT)) & ACOMP_CTRL1_INT_ACT_HI_MASK)
+
+#define ACOMP_CTRL1_EDGE_LEVL_SEL_MASK           (0x80000000U)
+#define ACOMP_CTRL1_EDGE_LEVL_SEL_SHIFT          (31U)
+/*! EDGE_LEVL_SEL - ACOMP1 interrupt type select.
+ *  0b0..level triggered interrupt
+ *  0b1..edge triggered interrupt
+ */
+#define ACOMP_CTRL1_EDGE_LEVL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_EDGE_LEVL_SEL_SHIFT)) & ACOMP_CTRL1_EDGE_LEVL_SEL_MASK)
+/*! @} */
+
+/*! @name STATUS0 - ACOMP0 Status Register */
+/*! @{ */
+
+#define ACOMP_STATUS0_ACT_MASK                   (0x1U)
+#define ACOMP_STATUS0_ACT_SHIFT                  (0U)
+/*! ACT - ACOMP0 active status.
+ *  0b0..ACOMP0 is inactive
+ *  0b1..ACOMP0 is active
+ */
+#define ACOMP_STATUS0_ACT(x)                     (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS0_ACT_SHIFT)) & ACOMP_STATUS0_ACT_MASK)
+
+#define ACOMP_STATUS0_OUT_MASK                   (0x2U)
+#define ACOMP_STATUS0_OUT_SHIFT                  (1U)
+/*! OUT - ACOMP0 comparison output value. */
+#define ACOMP_STATUS0_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS0_OUT_SHIFT)) & ACOMP_STATUS0_OUT_MASK)
+/*! @} */
+
+/*! @name STATUS1 - ACOMP1 Status Register */
+/*! @{ */
+
+#define ACOMP_STATUS1_ACT_MASK                   (0x1U)
+#define ACOMP_STATUS1_ACT_SHIFT                  (0U)
+/*! ACT - ACOMP1 active status.
+ *  0b0..ACOMP1 is inactive
+ *  0b1..ACOMP1 is active
+ */
+#define ACOMP_STATUS1_ACT(x)                     (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS1_ACT_SHIFT)) & ACOMP_STATUS1_ACT_MASK)
+
+#define ACOMP_STATUS1_OUT_MASK                   (0x2U)
+#define ACOMP_STATUS1_OUT_SHIFT                  (1U)
+/*! OUT - ACOMP1 comparison output value. */
+#define ACOMP_STATUS1_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS1_OUT_SHIFT)) & ACOMP_STATUS1_OUT_MASK)
+/*! @} */
+
+/*! @name ROUTE0 - ACOMP0 Route Register */
+/*! @{ */
+
+#define ACOMP_ROUTE0_OUTSEL_MASK                 (0x1U)
+#define ACOMP_ROUTE0_OUTSEL_SHIFT                (0U)
+/*! OUTSEL - Select ACOMP0 synchronous or asynchronous output to pin.
+ *  0b0..Synchronous output
+ *  0b1..Asynchronous output
+ */
+#define ACOMP_ROUTE0_OUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE0_OUTSEL_SHIFT)) & ACOMP_ROUTE0_OUTSEL_MASK)
+
+#define ACOMP_ROUTE0_PE_MASK                     (0x2U)
+#define ACOMP_ROUTE0_PE_SHIFT                    (1U)
+/*! PE - Enable/disable ACOMP0 output to pin.
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_ROUTE0_PE(x)                       (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE0_PE_SHIFT)) & ACOMP_ROUTE0_PE_MASK)
+/*! @} */
+
+/*! @name ROUTE1 - ACOMP1 Route Register */
+/*! @{ */
+
+#define ACOMP_ROUTE1_OUTSEL_MASK                 (0x1U)
+#define ACOMP_ROUTE1_OUTSEL_SHIFT                (0U)
+/*! OUTSEL - Select ACOMP1 synchronous or asynchronous output to pin
+ *  0b0..Synchronous output
+ *  0b1..Asynchronous output
+ */
+#define ACOMP_ROUTE1_OUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE1_OUTSEL_SHIFT)) & ACOMP_ROUTE1_OUTSEL_MASK)
+
+#define ACOMP_ROUTE1_PE_MASK                     (0x2U)
+#define ACOMP_ROUTE1_PE_SHIFT                    (1U)
+/*! PE - Enable/disable ACOMP1 output to pin
+ *  0b0..
+ *  0b1..
+ */
+#define ACOMP_ROUTE1_PE(x)                       (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE1_PE_SHIFT)) & ACOMP_ROUTE1_PE_MASK)
+/*! @} */
+
+/*! @name ISR0 - ACOMP0 Interrupt Status Register */
+/*! @{ */
+
+#define ACOMP_ISR0_OUT_INT_MASK                  (0x1U)
+#define ACOMP_ISR0_OUT_INT_SHIFT                 (0U)
+/*! OUT_INT - ACOMP0 Synchronized Output Interrupt */
+#define ACOMP_ISR0_OUT_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR0_OUT_INT_SHIFT)) & ACOMP_ISR0_OUT_INT_MASK)
+
+#define ACOMP_ISR0_OUTA_INT_MASK                 (0x2U)
+#define ACOMP_ISR0_OUTA_INT_SHIFT                (1U)
+/*! OUTA_INT - ACOMP0 Asynchronized Output Interrupt */
+#define ACOMP_ISR0_OUTA_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR0_OUTA_INT_SHIFT)) & ACOMP_ISR0_OUTA_INT_MASK)
+/*! @} */
+
+/*! @name ISR1 - ACOMP1 Interrupt Status Register */
+/*! @{ */
+
+#define ACOMP_ISR1_OUT_INT_MASK                  (0x1U)
+#define ACOMP_ISR1_OUT_INT_SHIFT                 (0U)
+/*! OUT_INT - ACOMP1 Synchronized Output Interrupt */
+#define ACOMP_ISR1_OUT_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR1_OUT_INT_SHIFT)) & ACOMP_ISR1_OUT_INT_MASK)
+
+#define ACOMP_ISR1_OUTA_INT_MASK                 (0x2U)
+#define ACOMP_ISR1_OUTA_INT_SHIFT                (1U)
+/*! OUTA_INT - ACOMP1 Asynchronized Output Interrupt */
+#define ACOMP_ISR1_OUTA_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR1_OUTA_INT_SHIFT)) & ACOMP_ISR1_OUTA_INT_MASK)
+/*! @} */
+
+/*! @name IMR0 - ACOMP0 Interrupt Mask Register */
+/*! @{ */
+
+#define ACOMP_IMR0_OUT_INT_MASK_MASK             (0x1U)
+#define ACOMP_IMR0_OUT_INT_MASK_SHIFT            (0U)
+/*! OUT_INT_MASK - Mask Synchronized Interrupt */
+#define ACOMP_IMR0_OUT_INT_MASK(x)               (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR0_OUT_INT_MASK_SHIFT)) & ACOMP_IMR0_OUT_INT_MASK_MASK)
+
+#define ACOMP_IMR0_OUTA_INT_MASK_MASK            (0x2U)
+#define ACOMP_IMR0_OUTA_INT_MASK_SHIFT           (1U)
+/*! OUTA_INT_MASK - Mask Asynchronized Interrupt */
+#define ACOMP_IMR0_OUTA_INT_MASK(x)              (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR0_OUTA_INT_MASK_SHIFT)) & ACOMP_IMR0_OUTA_INT_MASK_MASK)
+/*! @} */
+
+/*! @name IMR1 - ACOMP1 Interrupt Mask Register */
+/*! @{ */
+
+#define ACOMP_IMR1_OUT_INT_MASK_MASK             (0x1U)
+#define ACOMP_IMR1_OUT_INT_MASK_SHIFT            (0U)
+/*! OUT_INT_MASK - Mask Synchronized Interrupt */
+#define ACOMP_IMR1_OUT_INT_MASK(x)               (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR1_OUT_INT_MASK_SHIFT)) & ACOMP_IMR1_OUT_INT_MASK_MASK)
+
+#define ACOMP_IMR1_OUTA_INT_MASK_MASK            (0x2U)
+#define ACOMP_IMR1_OUTA_INT_MASK_SHIFT           (1U)
+/*! OUTA_INT_MASK - Mask Asynchronized Interrupt */
+#define ACOMP_IMR1_OUTA_INT_MASK(x)              (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR1_OUTA_INT_MASK_SHIFT)) & ACOMP_IMR1_OUTA_INT_MASK_MASK)
+/*! @} */
+
+/*! @name IRSR0 - ACOMP0 Interrupt Raw Status Register */
+/*! @{ */
+
+#define ACOMP_IRSR0_OUT_INT_RAW_MASK             (0x1U)
+#define ACOMP_IRSR0_OUT_INT_RAW_SHIFT            (0U)
+/*! OUT_INT_RAW - Raw Mask Synchronized Interrupt */
+#define ACOMP_IRSR0_OUT_INT_RAW(x)               (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR0_OUT_INT_RAW_SHIFT)) & ACOMP_IRSR0_OUT_INT_RAW_MASK)
+
+#define ACOMP_IRSR0_OUTA_INT_RAW_MASK            (0x2U)
+#define ACOMP_IRSR0_OUTA_INT_RAW_SHIFT           (1U)
+/*! OUTA_INT_RAW - Raw Mask Asynchronized Interrupt */
+#define ACOMP_IRSR0_OUTA_INT_RAW(x)              (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR0_OUTA_INT_RAW_SHIFT)) & ACOMP_IRSR0_OUTA_INT_RAW_MASK)
+/*! @} */
+
+/*! @name IRSR1 - ACOMP1 Interrupt Raw Status Register */
+/*! @{ */
+
+#define ACOMP_IRSR1_OUT_INT_RAW_MASK             (0x1U)
+#define ACOMP_IRSR1_OUT_INT_RAW_SHIFT            (0U)
+/*! OUT_INT_RAW - Raw Mask Synchronized Interrupt */
+#define ACOMP_IRSR1_OUT_INT_RAW(x)               (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR1_OUT_INT_RAW_SHIFT)) & ACOMP_IRSR1_OUT_INT_RAW_MASK)
+
+#define ACOMP_IRSR1_OUTA_INT_RAW_MASK            (0x2U)
+#define ACOMP_IRSR1_OUTA_INT_RAW_SHIFT           (1U)
+/*! OUTA_INT_RAW - Raw Mask Asynchronized Interrupt */
+#define ACOMP_IRSR1_OUTA_INT_RAW(x)              (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR1_OUTA_INT_RAW_SHIFT)) & ACOMP_IRSR1_OUTA_INT_RAW_MASK)
+/*! @} */
+
+/*! @name ICR0 - ACOMP0 Interrupt Clear Register */
+/*! @{ */
+
+#define ACOMP_ICR0_OUT_INT_CLR_MASK              (0x1U)
+#define ACOMP_ICR0_OUT_INT_CLR_SHIFT             (0U)
+/*! OUT_INT_CLR - ACOMP0 syncrhonized output interrupt flag clear signal. */
+#define ACOMP_ICR0_OUT_INT_CLR(x)                (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR0_OUT_INT_CLR_SHIFT)) & ACOMP_ICR0_OUT_INT_CLR_MASK)
+
+#define ACOMP_ICR0_OUTA_INT_CLR_MASK             (0x2U)
+#define ACOMP_ICR0_OUTA_INT_CLR_SHIFT            (1U)
+/*! OUTA_INT_CLR - ACOMP0 asyncrhonized output interrupt flag clear signal. */
+#define ACOMP_ICR0_OUTA_INT_CLR(x)               (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR0_OUTA_INT_CLR_SHIFT)) & ACOMP_ICR0_OUTA_INT_CLR_MASK)
+/*! @} */
+
+/*! @name ICR1 - ACOMP1 Interrupt Clear Register */
+/*! @{ */
+
+#define ACOMP_ICR1_OUT_INT_CLR_MASK              (0x1U)
+#define ACOMP_ICR1_OUT_INT_CLR_SHIFT             (0U)
+/*! OUT_INT_CLR - ACOMP1 syncrhonized output interrupt flag clear signal. */
+#define ACOMP_ICR1_OUT_INT_CLR(x)                (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR1_OUT_INT_CLR_SHIFT)) & ACOMP_ICR1_OUT_INT_CLR_MASK)
+
+#define ACOMP_ICR1_OUTA_INT_CLR_MASK             (0x2U)
+#define ACOMP_ICR1_OUTA_INT_CLR_SHIFT            (1U)
+/*! OUTA_INT_CLR - ACOMP1 asyncrhonized output interrupt flag clear signal. */
+#define ACOMP_ICR1_OUTA_INT_CLR(x)               (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR1_OUTA_INT_CLR_SHIFT)) & ACOMP_ICR1_OUTA_INT_CLR_MASK)
+/*! @} */
+
+/*! @name RST0 - ACOMP0 Soft Reset Register */
+/*! @{ */
+
+#define ACOMP_RST0_SOFT_RST_MASK                 (0x1U)
+#define ACOMP_RST0_SOFT_RST_SHIFT                (0U)
+/*! SOFT_RST - Soft Reset for ACOMP0 (active high)
+ *  0b0..no action
+ *  0b1..
+ */
+#define ACOMP_RST0_SOFT_RST(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_RST0_SOFT_RST_SHIFT)) & ACOMP_RST0_SOFT_RST_MASK)
+/*! @} */
+
+/*! @name RST1 - ACOMP1 Soft Reset Register */
+/*! @{ */
+
+#define ACOMP_RST1_SOFT_RST_MASK                 (0x1U)
+#define ACOMP_RST1_SOFT_RST_SHIFT                (0U)
+/*! SOFT_RST - Soft Reset for ACOMP1 (active high)
+ *  0b0..no action
+ *  0b1..
+ */
+#define ACOMP_RST1_SOFT_RST(x)                   (((uint32_t)(((uint32_t)(x)) << ACOMP_RST1_SOFT_RST_SHIFT)) & ACOMP_RST1_SOFT_RST_MASK)
+/*! @} */
+
+/*! @name CLK - Clock Register */
+/*! @{ */
+
+#define ACOMP_CLK_SOFT_CLK_RST_MASK              (0x2U)
+#define ACOMP_CLK_SOFT_CLK_RST_SHIFT             (1U)
+/*! SOFT_CLK_RST - soft reset for clock divider
+ *  0b0..no action
+ *  0b1..
+ */
+#define ACOMP_CLK_SOFT_CLK_RST(x)                (((uint32_t)(((uint32_t)(x)) << ACOMP_CLK_SOFT_CLK_RST_SHIFT)) & ACOMP_CLK_SOFT_CLK_RST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ACOMP_Register_Masks */
+
+
+/* ACOMP - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral GAU_ACOMP base address */
+  #define GAU_ACOMP_BASE                           (0x50038400u)
+  /** Peripheral GAU_ACOMP base address */
+  #define GAU_ACOMP_BASE_NS                        (0x40038400u)
+  /** Peripheral GAU_ACOMP base pointer */
+  #define GAU_ACOMP                                ((ACOMP_Type *)GAU_ACOMP_BASE)
+  /** Peripheral GAU_ACOMP base pointer */
+  #define GAU_ACOMP_NS                             ((ACOMP_Type *)GAU_ACOMP_BASE_NS)
+  /** Array initializer of ACOMP peripheral base addresses */
+  #define ACOMP_BASE_ADDRS                         { GAU_ACOMP_BASE }
+  /** Array initializer of ACOMP peripheral base pointers */
+  #define ACOMP_BASE_PTRS                          { GAU_ACOMP }
+  /** Array initializer of ACOMP peripheral base addresses */
+  #define ACOMP_BASE_ADDRS_NS                      { GAU_ACOMP_BASE_NS }
+  /** Array initializer of ACOMP peripheral base pointers */
+  #define ACOMP_BASE_PTRS_NS                       { GAU_ACOMP_NS }
+#else
+  /** Peripheral GAU_ACOMP base address */
+  #define GAU_ACOMP_BASE                           (0x40038400u)
+  /** Peripheral GAU_ACOMP base pointer */
+  #define GAU_ACOMP                                ((ACOMP_Type *)GAU_ACOMP_BASE)
+  /** Array initializer of ACOMP peripheral base addresses */
+  #define ACOMP_BASE_ADDRS                         { GAU_ACOMP_BASE }
+  /** Array initializer of ACOMP peripheral base pointers */
+  #define ACOMP_BASE_PTRS                          { GAU_ACOMP }
+#endif
+/** Interrupt vectors for the ACOMP peripheral type */
+#define ACOMP_FUNC_IRQS                          { GAU_ACOMP_IRQn }
+#define ACOMP_WAKE_IRQS                          { GAU_ACOMP_WKUP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ACOMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ADC_REG_CMD;                       /**< ADC Command Register, offset: 0x0 */
+  __IO uint32_t ADC_REG_GENERAL;                   /**< ADC General Register, offset: 0x4 */
+  __IO uint32_t ADC_REG_CONFIG;                    /**< ADC Configuration Register, offset: 0x8 */
+  __IO uint32_t ADC_REG_INTERVAL;                  /**< ADC Interval Register, offset: 0xC */
+  __IO uint32_t ADC_REG_ANA;                       /**< ADC ANA Register, offset: 0x10 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ADC_REG_SCN1;                      /**< ADC Conversion Sequence 1 Register, offset: 0x18 */
+  __IO uint32_t ADC_REG_SCN2;                      /**< ADC Conversion Sequence 2 Register, offset: 0x1C */
+  __IO uint32_t ADC_REG_RESULT_BUF;                /**< ADC Result Buffer Register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ADC_REG_DMAR;                      /**< ADC DMAR Register, offset: 0x28 */
+  __I  uint32_t ADC_REG_STATUS;                    /**< ADC Status Register, offset: 0x2C */
+  __I  uint32_t ADC_REG_ISR;                       /**< ADC ISR Register, offset: 0x30 */
+  __IO uint32_t ADC_REG_IMR;                       /**< ADC IMR Register, offset: 0x34 */
+  __I  uint32_t ADC_REG_IRSR;                      /**< ADC IRSR Register, offset: 0x38 */
+  __IO uint32_t ADC_REG_ICR;                       /**< ADC ICR Register, offset: 0x3C */
+       uint8_t RESERVED_2[4];
+  __I  uint32_t ADC_REG_RESULT;                    /**< ADC Result Register, offset: 0x44 */
+  __I  uint32_t ADC_REG_RAW_RESULT;                /**< ADC Raw Result Register, offset: 0x48 */
+  __IO uint32_t ADC_REG_OFFSET_CAL;                /**< ADC Offset Calibration Register, offset: 0x4C */
+  __IO uint32_t ADC_REG_GAIN_CAL;                  /**< ADC Gain Calibration Register, offset: 0x50 */
+  __IO uint32_t ADC_REG_TEST;                      /**< ADC Test Register, offset: 0x54 */
+  __IO uint32_t ADC_REG_AUDIO;                     /**< ADC Audio Register, offset: 0x58 */
+  __IO uint32_t ADC_REG_VOICE_DET;                 /**< ADC Voice Detect Register, offset: 0x5C */
+  __IO uint32_t ADC_REG_RSVD;                      /**< ADC Reserved Register, offset: 0x60 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name ADC_REG_CMD - ADC Command Register */
+/*! @{ */
+
+#define ADC_ADC_REG_CMD_CONV_START_MASK          (0x1U)
+#define ADC_ADC_REG_CMD_CONV_START_SHIFT         (0U)
+/*! CONV_START - converaion control bit. */
+#define ADC_ADC_REG_CMD_CONV_START(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CMD_CONV_START_SHIFT)) & ADC_ADC_REG_CMD_CONV_START_MASK)
+
+#define ADC_ADC_REG_CMD_SOFT_RST_MASK            (0x2U)
+#define ADC_ADC_REG_CMD_SOFT_RST_SHIFT           (1U)
+/*! SOFT_RST - user reset the whole block */
+#define ADC_ADC_REG_CMD_SOFT_RST(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CMD_SOFT_RST_SHIFT)) & ADC_ADC_REG_CMD_SOFT_RST_MASK)
+
+#define ADC_ADC_REG_CMD_SOFT_CLK_RST_MASK        (0x4U)
+#define ADC_ADC_REG_CMD_SOFT_CLK_RST_SHIFT       (2U)
+/*! SOFT_CLK_RST - user reset clock */
+#define ADC_ADC_REG_CMD_SOFT_CLK_RST(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CMD_SOFT_CLK_RST_SHIFT)) & ADC_ADC_REG_CMD_SOFT_CLK_RST_MASK)
+/*! @} */
+
+/*! @name ADC_REG_GENERAL - ADC General Register */
+/*! @{ */
+
+#define ADC_ADC_REG_GENERAL_GPADC_MASTER_MASK    (0x1U)
+#define ADC_ADC_REG_GENERAL_GPADC_MASTER_SHIFT   (0U)
+/*! GPADC_MASTER - play as master or slave in dual mode, master is the only controller of when slave start */
+#define ADC_ADC_REG_GENERAL_GPADC_MASTER(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_GPADC_MASTER_SHIFT)) & ADC_ADC_REG_GENERAL_GPADC_MASTER_MASK)
+
+#define ADC_ADC_REG_GENERAL_GLOBAL_EN_MASK       (0x2U)
+#define ADC_ADC_REG_GENERAL_GLOBAL_EN_SHIFT      (1U)
+/*! GLOBAL_EN - ADC enable/disable */
+#define ADC_ADC_REG_GENERAL_GLOBAL_EN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_GLOBAL_EN_SHIFT)) & ADC_ADC_REG_GENERAL_GLOBAL_EN_MASK)
+
+#define ADC_ADC_REG_GENERAL_FORCE_CLK_ON_MASK    (0x4U)
+#define ADC_ADC_REG_GENERAL_FORCE_CLK_ON_SHIFT   (2U)
+/*! FORCE_CLK_ON - override the gpadc_mclk_en from outside */
+#define ADC_ADC_REG_GENERAL_FORCE_CLK_ON(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_FORCE_CLK_ON_SHIFT)) & ADC_ADC_REG_GENERAL_FORCE_CLK_ON_MASK)
+
+#define ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_MASK  (0x8U)
+#define ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_SHIFT (3U)
+/*! CLK_ANA64M_INV - analog clock 64M inverted */
+#define ADC_ADC_REG_GENERAL_CLK_ANA64M_INV(x)    (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_SHIFT)) & ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_MASK)
+
+#define ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_MASK   (0x10U)
+#define ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_SHIFT  (4U)
+/*! CLK_ANA2M_INV - analog clock 2M inverted */
+#define ADC_ADC_REG_GENERAL_CLK_ANA2M_INV(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_SHIFT)) & ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_MASK)
+
+#define ADC_ADC_REG_GENERAL_ADC_CAL_EN_MASK      (0x20U)
+#define ADC_ADC_REG_GENERAL_ADC_CAL_EN_SHIFT     (5U)
+/*! ADC_CAL_EN - calibration enable, auto cleared after calibration done */
+#define ADC_ADC_REG_GENERAL_ADC_CAL_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_ADC_CAL_EN_SHIFT)) & ADC_ADC_REG_GENERAL_ADC_CAL_EN_MASK)
+
+#define ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_MASK   (0x3F00U)
+#define ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_SHIFT  (8U)
+/*! CLK_DIV_RATIO - analog 64M clock division ratio */
+#define ADC_ADC_REG_GENERAL_CLK_DIV_RATIO(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_SHIFT)) & ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_MASK)
+/*! @} */
+
+/*! @name ADC_REG_CONFIG - ADC Configuration Register */
+/*! @{ */
+
+#define ADC_ADC_REG_CONFIG_TRIGGER_SEL_MASK      (0xFU)
+#define ADC_ADC_REG_CONFIG_TRIGGER_SEL_SHIFT     (0U)
+/*! TRIGGER_SEL - External trigger source select bits
+ *  0b0000..ctimer3 match1 in ADC0 module, ctimer3 match2 in ADC1 module
+ *  0b0001..acomparator 0 out in ADC0 module, acomparator 1 out in ADC1 module
+ *  0b0010..GPIO50
+ *  0b0011..GPIO55
+ */
+#define ADC_ADC_REG_CONFIG_TRIGGER_SEL(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_TRIGGER_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_TRIGGER_SEL_MASK)
+
+#define ADC_ADC_REG_CONFIG_TRIGGER_EN_MASK       (0x10U)
+#define ADC_ADC_REG_CONFIG_TRIGGER_EN_SHIFT      (4U)
+/*! TRIGGER_EN - External elevel trigger enable bit, support gpadc_trigger/gpadc_data_valid handshake */
+#define ADC_ADC_REG_CONFIG_TRIGGER_EN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_TRIGGER_EN_SHIFT)) & ADC_ADC_REG_CONFIG_TRIGGER_EN_MASK)
+
+#define ADC_ADC_REG_CONFIG_DUAL_MODE_MASK        (0x20U)
+#define ADC_ADC_REG_CONFIG_DUAL_MODE_SHIFT       (5U)
+/*! DUAL_MODE - dual mode select */
+#define ADC_ADC_REG_CONFIG_DUAL_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_DUAL_MODE_SHIFT)) & ADC_ADC_REG_CONFIG_DUAL_MODE_MASK)
+
+#define ADC_ADC_REG_CONFIG_SINGLE_DUAL_MASK      (0x40U)
+#define ADC_ADC_REG_CONFIG_SINGLE_DUAL_SHIFT     (6U)
+/*! SINGLE_DUAL - work mode select */
+#define ADC_ADC_REG_CONFIG_SINGLE_DUAL(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_SINGLE_DUAL_SHIFT)) & ADC_ADC_REG_CONFIG_SINGLE_DUAL_MASK)
+
+#define ADC_ADC_REG_CONFIG_CONT_CONV_EN_MASK     (0x100U)
+#define ADC_ADC_REG_CONFIG_CONT_CONV_EN_SHIFT    (8U)
+/*! CONT_CONV_EN - To enable continuous conversion */
+#define ADC_ADC_REG_CONFIG_CONT_CONV_EN(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CONT_CONV_EN_SHIFT)) & ADC_ADC_REG_CONFIG_CONT_CONV_EN_MASK)
+
+#define ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_MASK  (0x200U)
+#define ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_SHIFT (9U)
+/*! DATA_FORMAT_SEL - set data format for the final data */
+#define ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL(x)    (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_MASK)
+
+#define ADC_ADC_REG_CONFIG_CAL_VREF_SEL_MASK     (0x400U)
+#define ADC_ADC_REG_CONFIG_CAL_VREF_SEL_SHIFT    (10U)
+/*! CAL_VREF_SEL - select input reference channel for gain calibration */
+#define ADC_ADC_REG_CONFIG_CAL_VREF_SEL(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CAL_VREF_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_CAL_VREF_SEL_MASK)
+
+#define ADC_ADC_REG_CONFIG_CAL_DATA_RST_MASK     (0x800U)
+#define ADC_ADC_REG_CONFIG_CAL_DATA_RST_SHIFT    (11U)
+/*! CAL_DATA_RST - reset the self calibration data. */
+#define ADC_ADC_REG_CONFIG_CAL_DATA_RST(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CAL_DATA_RST_SHIFT)) & ADC_ADC_REG_CONFIG_CAL_DATA_RST_MASK)
+
+#define ADC_ADC_REG_CONFIG_CAL_DATA_SEL_MASK     (0x1000U)
+#define ADC_ADC_REG_CONFIG_CAL_DATA_SEL_SHIFT    (12U)
+/*! CAL_DATA_SEL - select calibration data source. */
+#define ADC_ADC_REG_CONFIG_CAL_DATA_SEL(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CAL_DATA_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_CAL_DATA_SEL_MASK)
+
+#define ADC_ADC_REG_CONFIG_AVG_SEL_MASK          (0xE000U)
+#define ADC_ADC_REG_CONFIG_AVG_SEL_SHIFT         (13U)
+/*! AVG_SEL - moving average length */
+#define ADC_ADC_REG_CONFIG_AVG_SEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_AVG_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_AVG_SEL_MASK)
+
+#define ADC_ADC_REG_CONFIG_SCAN_LENGTH_MASK      (0xF0000U)
+#define ADC_ADC_REG_CONFIG_SCAN_LENGTH_SHIFT     (16U)
+/*! SCAN_LENGTH - scan converation length, actual length is scan_length+1. */
+#define ADC_ADC_REG_CONFIG_SCAN_LENGTH(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_SCAN_LENGTH_SHIFT)) & ADC_ADC_REG_CONFIG_SCAN_LENGTH_MASK)
+
+#define ADC_ADC_REG_CONFIG_PWR_MODE_MASK         (0x100000U)
+#define ADC_ADC_REG_CONFIG_PWR_MODE_SHIFT        (20U)
+/*! PWR_MODE - ADC power mode select. */
+#define ADC_ADC_REG_CONFIG_PWR_MODE(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_PWR_MODE_SHIFT)) & ADC_ADC_REG_CONFIG_PWR_MODE_MASK)
+/*! @} */
+
+/*! @name ADC_REG_INTERVAL - ADC Interval Register */
+/*! @{ */
+
+#define ADC_ADC_REG_INTERVAL_WARMUP_TIME_MASK    (0x1FU)
+#define ADC_ADC_REG_INTERVAL_WARMUP_TIME_SHIFT   (0U)
+/*! WARMUP_TIME - warmup time, should be set equal to or higher than 1uS. */
+#define ADC_ADC_REG_INTERVAL_WARMUP_TIME(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_INTERVAL_WARMUP_TIME_SHIFT)) & ADC_ADC_REG_INTERVAL_WARMUP_TIME_MASK)
+
+#define ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_MASK  (0x20U)
+#define ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_SHIFT (5U)
+/*! BYPASS_WARMUP - Bypass warmup state inside adc. */
+#define ADC_ADC_REG_INTERVAL_BYPASS_WARMUP(x)    (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_SHIFT)) & ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_MASK)
+/*! @} */
+
+/*! @name ADC_REG_ANA - ADC ANA Register */
+/*! @{ */
+
+#define ADC_ADC_REG_ANA_TSEXT_SEL_MASK           (0x1U)
+#define ADC_ADC_REG_ANA_TSEXT_SEL_SHIFT          (0U)
+/*! TSEXT_SEL - temperature sensor diode select */
+#define ADC_ADC_REG_ANA_TSEXT_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_TSEXT_SEL_SHIFT)) & ADC_ADC_REG_ANA_TSEXT_SEL_MASK)
+
+#define ADC_ADC_REG_ANA_TS_EN_MASK               (0x2U)
+#define ADC_ADC_REG_ANA_TS_EN_SHIFT              (1U)
+/*! TS_EN - temperature sensor enable, only enable when channel source is temperature sensor */
+#define ADC_ADC_REG_ANA_TS_EN(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_TS_EN_SHIFT)) & ADC_ADC_REG_ANA_TS_EN_MASK)
+
+#define ADC_ADC_REG_ANA_VREF_SCF_BYPASS_MASK     (0x4U)
+#define ADC_ADC_REG_ANA_VREF_SCF_BYPASS_SHIFT    (2U)
+/*! VREF_SCF_BYPASS - adc voltage reference buffer sc-filter bypass */
+#define ADC_ADC_REG_ANA_VREF_SCF_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_VREF_SCF_BYPASS_SHIFT)) & ADC_ADC_REG_ANA_VREF_SCF_BYPASS_MASK)
+
+#define ADC_ADC_REG_ANA_VREF_CHOP_EN_MASK        (0x8U)
+#define ADC_ADC_REG_ANA_VREF_CHOP_EN_SHIFT       (3U)
+/*! VREF_CHOP_EN - adc voltage reference buffer chopper enable */
+#define ADC_ADC_REG_ANA_VREF_CHOP_EN(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_VREF_CHOP_EN_SHIFT)) & ADC_ADC_REG_ANA_VREF_CHOP_EN_MASK)
+
+#define ADC_ADC_REG_ANA_VREF_SEL_MASK            (0x30U)
+#define ADC_ADC_REG_ANA_VREF_SEL_SHIFT           (4U)
+/*! VREF_SEL - adc reference voltage select. */
+#define ADC_ADC_REG_ANA_VREF_SEL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_VREF_SEL_SHIFT)) & ADC_ADC_REG_ANA_VREF_SEL_MASK)
+
+#define ADC_ADC_REG_ANA_SINGLEDIFF_MASK          (0x400U)
+#define ADC_ADC_REG_ANA_SINGLEDIFF_SHIFT         (10U)
+/*! SINGLEDIFF - Select single ended or differential input. */
+#define ADC_ADC_REG_ANA_SINGLEDIFF(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_SINGLEDIFF_SHIFT)) & ADC_ADC_REG_ANA_SINGLEDIFF_MASK)
+
+#define ADC_ADC_REG_ANA_INBUF_GAIN_MASK          (0x1800U)
+#define ADC_ADC_REG_ANA_INBUF_GAIN_SHIFT         (11U)
+/*! INBUF_GAIN - adc gain control. Also select input voltage range. */
+#define ADC_ADC_REG_ANA_INBUF_GAIN(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_INBUF_GAIN_SHIFT)) & ADC_ADC_REG_ANA_INBUF_GAIN_MASK)
+
+#define ADC_ADC_REG_ANA_INBUF_CHOP_EN_MASK       (0x2000U)
+#define ADC_ADC_REG_ANA_INBUF_CHOP_EN_SHIFT      (13U)
+/*! INBUF_CHOP_EN - Input buffer chopper enable */
+#define ADC_ADC_REG_ANA_INBUF_CHOP_EN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_INBUF_CHOP_EN_SHIFT)) & ADC_ADC_REG_ANA_INBUF_CHOP_EN_MASK)
+
+#define ADC_ADC_REG_ANA_INBUF_EN_MASK            (0x4000U)
+#define ADC_ADC_REG_ANA_INBUF_EN_SHIFT           (14U)
+/*! INBUF_EN - gpadc input gain buffer enable bit. */
+#define ADC_ADC_REG_ANA_INBUF_EN(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_INBUF_EN_SHIFT)) & ADC_ADC_REG_ANA_INBUF_EN_MASK)
+
+#define ADC_ADC_REG_ANA_CHOP_EN_MASK             (0x8000U)
+#define ADC_ADC_REG_ANA_CHOP_EN_SHIFT            (15U)
+/*! CHOP_EN - adc chopper/auto-zero(only in 12bit mode) enable */
+#define ADC_ADC_REG_ANA_CHOP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_CHOP_EN_SHIFT)) & ADC_ADC_REG_ANA_CHOP_EN_MASK)
+
+#define ADC_ADC_REG_ANA_BIAS_SEL_MASK            (0x10000U)
+#define ADC_ADC_REG_ANA_BIAS_SEL_SHIFT           (16U)
+/*! BIAS_SEL - adc analog portion low power mode select. Half the biasing current for modulator when enabled. */
+#define ADC_ADC_REG_ANA_BIAS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_BIAS_SEL_SHIFT)) & ADC_ADC_REG_ANA_BIAS_SEL_MASK)
+
+#define ADC_ADC_REG_ANA_RES_SEL_MASK             (0x60000U)
+#define ADC_ADC_REG_ANA_RES_SEL_SHIFT            (17U)
+/*! RES_SEL - adc resolution/data rate select */
+#define ADC_ADC_REG_ANA_RES_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_RES_SEL_SHIFT)) & ADC_ADC_REG_ANA_RES_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_SCN1 - ADC Conversion Sequence 1 Register */
+/*! @{ */
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_0_MASK          (0xFU)
+#define ADC_ADC_REG_SCN1_SCAN_CH_0_SHIFT         (0U)
+/*! SCAN_CH_0 - amux source 0 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_0(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_0_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_0_MASK)
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_1_MASK          (0xF0U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_1_SHIFT         (4U)
+/*! SCAN_CH_1 - amux source 1 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_1(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_1_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_1_MASK)
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_2_MASK          (0xF00U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_2_SHIFT         (8U)
+/*! SCAN_CH_2 - amux source 2 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_2(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_2_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_2_MASK)
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_3_MASK          (0xF000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_3_SHIFT         (12U)
+/*! SCAN_CH_3 - amux source 3 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_3(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_3_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_3_MASK)
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_4_MASK          (0xF0000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_4_SHIFT         (16U)
+/*! SCAN_CH_4 - amux source 4 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_4(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_4_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_4_MASK)
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_5_MASK          (0xF00000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_5_SHIFT         (20U)
+/*! SCAN_CH_5 - amux source 5 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_5(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_5_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_5_MASK)
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_6_MASK          (0xF000000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_6_SHIFT         (24U)
+/*! SCAN_CH_6 - amux source 6 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_6(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_6_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_6_MASK)
+
+#define ADC_ADC_REG_SCN1_SCAN_CH_7_MASK          (0xF0000000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_7_SHIFT         (28U)
+/*! SCAN_CH_7 - amux source 7 */
+#define ADC_ADC_REG_SCN1_SCAN_CH_7(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_7_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_7_MASK)
+/*! @} */
+
+/*! @name ADC_REG_SCN2 - ADC Conversion Sequence 2 Register */
+/*! @{ */
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_8_MASK          (0xFU)
+#define ADC_ADC_REG_SCN2_SCAN_CH_8_SHIFT         (0U)
+/*! SCAN_CH_8 - amux source 8 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_8(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_8_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_8_MASK)
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_9_MASK          (0xF0U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_9_SHIFT         (4U)
+/*! SCAN_CH_9 - amux source 9 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_9(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_9_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_9_MASK)
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_10_MASK         (0xF00U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_10_SHIFT        (8U)
+/*! SCAN_CH_10 - amux source 10 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_10(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_10_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_10_MASK)
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_11_MASK         (0xF000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_11_SHIFT        (12U)
+/*! SCAN_CH_11 - amux source 11 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_11(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_11_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_11_MASK)
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_12_MASK         (0xF0000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_12_SHIFT        (16U)
+/*! SCAN_CH_12 - amux source 12 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_12(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_12_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_12_MASK)
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_13_MASK         (0xF00000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_13_SHIFT        (20U)
+/*! SCAN_CH_13 - amux source 13 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_13(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_13_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_13_MASK)
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_14_MASK         (0xF000000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_14_SHIFT        (24U)
+/*! SCAN_CH_14 - amux source 14 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_14(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_14_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_14_MASK)
+
+#define ADC_ADC_REG_SCN2_SCAN_CH_15_MASK         (0xF0000000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_15_SHIFT        (28U)
+/*! SCAN_CH_15 - amux source 15 */
+#define ADC_ADC_REG_SCN2_SCAN_CH_15(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_15_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_15_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RESULT_BUF - ADC Result Buffer Register */
+/*! @{ */
+
+#define ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_MASK    (0x1U)
+#define ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_SHIFT   (0U)
+/*! WIDTH_SEL - adc finial result fifo data packed format select, must set scan_length as even when choose 32-bits */
+#define ADC_ADC_REG_RESULT_BUF_WIDTH_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_SHIFT)) & ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_DMAR - ADC DMAR Register */
+/*! @{ */
+
+#define ADC_ADC_REG_DMAR_DMA_EN_MASK             (0x1U)
+#define ADC_ADC_REG_DMAR_DMA_EN_SHIFT            (0U)
+/*! DMA_EN - dma enbale */
+#define ADC_ADC_REG_DMAR_DMA_EN(x)               (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_DMAR_DMA_EN_SHIFT)) & ADC_ADC_REG_DMAR_DMA_EN_MASK)
+
+#define ADC_ADC_REG_DMAR_FIFO_THL_MASK           (0x6U)
+#define ADC_ADC_REG_DMAR_FIFO_THL_SHIFT          (1U)
+/*! FIFO_THL - fifo threshold */
+#define ADC_ADC_REG_DMAR_FIFO_THL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_DMAR_FIFO_THL_SHIFT)) & ADC_ADC_REG_DMAR_FIFO_THL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_STATUS - ADC Status Register */
+/*! @{ */
+
+#define ADC_ADC_REG_STATUS_ACT_MASK              (0x1U)
+#define ADC_ADC_REG_STATUS_ACT_SHIFT             (0U)
+/*! ACT - adc status */
+#define ADC_ADC_REG_STATUS_ACT(x)                (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_ACT_SHIFT)) & ADC_ADC_REG_STATUS_ACT_MASK)
+
+#define ADC_ADC_REG_STATUS_FIFO_NE_MASK          (0x2U)
+#define ADC_ADC_REG_STATUS_FIFO_NE_SHIFT         (1U)
+/*! FIFO_NE - fifo not empty status */
+#define ADC_ADC_REG_STATUS_FIFO_NE(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_FIFO_NE_SHIFT)) & ADC_ADC_REG_STATUS_FIFO_NE_MASK)
+
+#define ADC_ADC_REG_STATUS_FIFO_FULL_MASK        (0x4U)
+#define ADC_ADC_REG_STATUS_FIFO_FULL_SHIFT       (2U)
+/*! FIFO_FULL - fifo full status */
+#define ADC_ADC_REG_STATUS_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_FIFO_FULL_SHIFT)) & ADC_ADC_REG_STATUS_FIFO_FULL_MASK)
+
+#define ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_MASK  (0x1F8U)
+#define ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_SHIFT (3U)
+/*! FIFO_DATA_COUNT - fifo data number */
+#define ADC_ADC_REG_STATUS_FIFO_DATA_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_SHIFT)) & ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_MASK)
+/*! @} */
+
+/*! @name ADC_REG_ISR - ADC ISR Register */
+/*! @{ */
+
+#define ADC_ADC_REG_ISR_RDY_MASK                 (0x1U)
+#define ADC_ADC_REG_ISR_RDY_SHIFT                (0U)
+/*! RDY - Conversion data ready interrupt flag */
+#define ADC_ADC_REG_ISR_RDY(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_RDY_SHIFT)) & ADC_ADC_REG_ISR_RDY_MASK)
+
+#define ADC_ADC_REG_ISR_GAINSAT_MASK             (0x2U)
+#define ADC_ADC_REG_ISR_GAINSAT_SHIFT            (1U)
+/*! GAINSAT - Gain correction saturation interrupt flag */
+#define ADC_ADC_REG_ISR_GAINSAT(x)               (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_GAINSAT_SHIFT)) & ADC_ADC_REG_ISR_GAINSAT_MASK)
+
+#define ADC_ADC_REG_ISR_OFFSAT_MASK              (0x4U)
+#define ADC_ADC_REG_ISR_OFFSAT_SHIFT             (2U)
+/*! OFFSAT - Offset correction saturation interrupt flag */
+#define ADC_ADC_REG_ISR_OFFSAT(x)                (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_OFFSAT_SHIFT)) & ADC_ADC_REG_ISR_OFFSAT_MASK)
+
+#define ADC_ADC_REG_ISR_DATASAT_NEG_MASK         (0x8U)
+#define ADC_ADC_REG_ISR_DATASAT_NEG_SHIFT        (3U)
+/*! DATASAT_NEG - ADC data negative side saturation interrupt flag */
+#define ADC_ADC_REG_ISR_DATASAT_NEG(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_DATASAT_NEG_SHIFT)) & ADC_ADC_REG_ISR_DATASAT_NEG_MASK)
+
+#define ADC_ADC_REG_ISR_DATASAT_POS_MASK         (0x10U)
+#define ADC_ADC_REG_ISR_DATASAT_POS_SHIFT        (4U)
+/*! DATASAT_POS - ADC data positive side saturation interrupt flag */
+#define ADC_ADC_REG_ISR_DATASAT_POS(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_DATASAT_POS_SHIFT)) & ADC_ADC_REG_ISR_DATASAT_POS_MASK)
+
+#define ADC_ADC_REG_ISR_FIFO_OVERRUN_MASK        (0x20U)
+#define ADC_ADC_REG_ISR_FIFO_OVERRUN_SHIFT       (5U)
+/*! FIFO_OVERRUN - FIFO overrun interrupt flag */
+#define ADC_ADC_REG_ISR_FIFO_OVERRUN(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_FIFO_OVERRUN_SHIFT)) & ADC_ADC_REG_ISR_FIFO_OVERRUN_MASK)
+
+#define ADC_ADC_REG_ISR_FIFO_UNDERRUN_MASK       (0x40U)
+#define ADC_ADC_REG_ISR_FIFO_UNDERRUN_SHIFT      (6U)
+/*! FIFO_UNDERRUN - FIFO underrun interrupt flag */
+#define ADC_ADC_REG_ISR_FIFO_UNDERRUN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_FIFO_UNDERRUN_SHIFT)) & ADC_ADC_REG_ISR_FIFO_UNDERRUN_MASK)
+/*! @} */
+
+/*! @name ADC_REG_IMR - ADC IMR Register */
+/*! @{ */
+
+#define ADC_ADC_REG_IMR_RDY_MASK_MASK            (0x1U)
+#define ADC_ADC_REG_IMR_RDY_MASK_SHIFT           (0U)
+/*! RDY_MASK - write 1 mask */
+#define ADC_ADC_REG_IMR_RDY_MASK(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_RDY_MASK_SHIFT)) & ADC_ADC_REG_IMR_RDY_MASK_MASK)
+
+#define ADC_ADC_REG_IMR_GAINSAT_MASK_MASK        (0x2U)
+#define ADC_ADC_REG_IMR_GAINSAT_MASK_SHIFT       (1U)
+/*! GAINSAT_MASK - write 1 mask */
+#define ADC_ADC_REG_IMR_GAINSAT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_GAINSAT_MASK_SHIFT)) & ADC_ADC_REG_IMR_GAINSAT_MASK_MASK)
+
+#define ADC_ADC_REG_IMR_OFFSAT_MASK_MASK         (0x4U)
+#define ADC_ADC_REG_IMR_OFFSAT_MASK_SHIFT        (2U)
+/*! OFFSAT_MASK - write 1 mask */
+#define ADC_ADC_REG_IMR_OFFSAT_MASK(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_OFFSAT_MASK_SHIFT)) & ADC_ADC_REG_IMR_OFFSAT_MASK_MASK)
+
+#define ADC_ADC_REG_IMR_DATASAT_NEG_MASK_MASK    (0x8U)
+#define ADC_ADC_REG_IMR_DATASAT_NEG_MASK_SHIFT   (3U)
+/*! DATASAT_NEG_MASK - write 1 mask */
+#define ADC_ADC_REG_IMR_DATASAT_NEG_MASK(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_DATASAT_NEG_MASK_SHIFT)) & ADC_ADC_REG_IMR_DATASAT_NEG_MASK_MASK)
+
+#define ADC_ADC_REG_IMR_DATASAT_POS_MASK_MASK    (0x10U)
+#define ADC_ADC_REG_IMR_DATASAT_POS_MASK_SHIFT   (4U)
+/*! DATASAT_POS_MASK - write 1 mask */
+#define ADC_ADC_REG_IMR_DATASAT_POS_MASK(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_DATASAT_POS_MASK_SHIFT)) & ADC_ADC_REG_IMR_DATASAT_POS_MASK_MASK)
+
+#define ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_MASK   (0x20U)
+#define ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_SHIFT  (5U)
+/*! FIFO_OVERRUN_MASK - write 1 mask */
+#define ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_SHIFT)) & ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_MASK)
+
+#define ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_MASK  (0x40U)
+#define ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_SHIFT (6U)
+/*! FIFO_UNDERRUN_MASK - write 1 mask */
+#define ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK(x)    (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_SHIFT)) & ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_MASK)
+/*! @} */
+
+/*! @name ADC_REG_IRSR - ADC IRSR Register */
+/*! @{ */
+
+#define ADC_ADC_REG_IRSR_RDY_RAW_MASK            (0x1U)
+#define ADC_ADC_REG_IRSR_RDY_RAW_SHIFT           (0U)
+/*! RDY_RAW - The corresponding flag will be captured into this register regardless the interrupt
+ *    mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_RDY_RAW(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_RDY_RAW_SHIFT)) & ADC_ADC_REG_IRSR_RDY_RAW_MASK)
+
+#define ADC_ADC_REG_IRSR_GAINSAT_RAW_MASK        (0x2U)
+#define ADC_ADC_REG_IRSR_GAINSAT_RAW_SHIFT       (1U)
+/*! GAINSAT_RAW - The corresponding flag will be captured into this register regardless the
+ *    interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_GAINSAT_RAW(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_GAINSAT_RAW_SHIFT)) & ADC_ADC_REG_IRSR_GAINSAT_RAW_MASK)
+
+#define ADC_ADC_REG_IRSR_OFFSAT_RAW_MASK         (0x4U)
+#define ADC_ADC_REG_IRSR_OFFSAT_RAW_SHIFT        (2U)
+/*! OFFSAT_RAW - The corresponding flag will be captured into this register regardless the interrupt
+ *    mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_OFFSAT_RAW(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_OFFSAT_RAW_SHIFT)) & ADC_ADC_REG_IRSR_OFFSAT_RAW_MASK)
+
+#define ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_MASK    (0x8U)
+#define ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_SHIFT   (3U)
+/*! DATASAT_NEG_RAW - The corresponding flag will be captured into this register regardless the
+ *    interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_DATASAT_NEG_RAW(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_SHIFT)) & ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_MASK)
+
+#define ADC_ADC_REG_IRSR_DATASAT_POS_RAW_MASK    (0x10U)
+#define ADC_ADC_REG_IRSR_DATASAT_POS_RAW_SHIFT   (4U)
+/*! DATASAT_POS_RAW - The corresponding flag will be captured into this register regardless the
+ *    interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_DATASAT_POS_RAW(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_DATASAT_POS_RAW_SHIFT)) & ADC_ADC_REG_IRSR_DATASAT_POS_RAW_MASK)
+
+#define ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_MASK   (0x20U)
+#define ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_SHIFT  (5U)
+/*! FIFO_OVERRUN_RAW - The corresponding flag will be captured into this register regardless the
+ *    interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_SHIFT)) & ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_MASK)
+
+#define ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_MASK  (0x40U)
+#define ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_SHIFT (6U)
+/*! FIFO_UNDERRUN_RAW - The corresponding flag will be captured into this register regardless the
+ *    interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW(x)    (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_SHIFT)) & ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_MASK)
+/*! @} */
+
+/*! @name ADC_REG_ICR - ADC ICR Register */
+/*! @{ */
+
+#define ADC_ADC_REG_ICR_RDY_CLR_MASK             (0x1U)
+#define ADC_ADC_REG_ICR_RDY_CLR_SHIFT            (0U)
+/*! RDY_CLR - Write 1 to clear both adc_reg_irsr and adc_reg_isr */
+#define ADC_ADC_REG_ICR_RDY_CLR(x)               (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_RDY_CLR_SHIFT)) & ADC_ADC_REG_ICR_RDY_CLR_MASK)
+
+#define ADC_ADC_REG_ICR_GAINSAT_CLR_MASK         (0x2U)
+#define ADC_ADC_REG_ICR_GAINSAT_CLR_SHIFT        (1U)
+/*! GAINSAT_CLR - Write 1 to clear both adc_reg_irsr and adc_reg_isr */
+#define ADC_ADC_REG_ICR_GAINSAT_CLR(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_GAINSAT_CLR_SHIFT)) & ADC_ADC_REG_ICR_GAINSAT_CLR_MASK)
+
+#define ADC_ADC_REG_ICR_OFFSAT_CLR_MASK          (0x4U)
+#define ADC_ADC_REG_ICR_OFFSAT_CLR_SHIFT         (2U)
+/*! OFFSAT_CLR - Write 1 to clear both adc_reg_irsr and adc_reg_isr */
+#define ADC_ADC_REG_ICR_OFFSAT_CLR(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_OFFSAT_CLR_SHIFT)) & ADC_ADC_REG_ICR_OFFSAT_CLR_MASK)
+
+#define ADC_ADC_REG_ICR_DATASAT_NEG_CLR_MASK     (0x8U)
+#define ADC_ADC_REG_ICR_DATASAT_NEG_CLR_SHIFT    (3U)
+/*! DATASAT_NEG_CLR - Write 1 to clear both adc_reg_irsr and adc_reg_isr */
+#define ADC_ADC_REG_ICR_DATASAT_NEG_CLR(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_DATASAT_NEG_CLR_SHIFT)) & ADC_ADC_REG_ICR_DATASAT_NEG_CLR_MASK)
+
+#define ADC_ADC_REG_ICR_DATASAT_POS_CLR_MASK     (0x10U)
+#define ADC_ADC_REG_ICR_DATASAT_POS_CLR_SHIFT    (4U)
+/*! DATASAT_POS_CLR - Write 1 to clear both adc_reg_irsr and adc_reg_isr */
+#define ADC_ADC_REG_ICR_DATASAT_POS_CLR(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_DATASAT_POS_CLR_SHIFT)) & ADC_ADC_REG_ICR_DATASAT_POS_CLR_MASK)
+
+#define ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_MASK    (0x20U)
+#define ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_SHIFT   (5U)
+/*! FIFO_OVERRUN_CLR - Write 1 to clear both adc_reg_irsr and adc_reg_isr */
+#define ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_SHIFT)) & ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_MASK)
+
+#define ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_MASK   (0x40U)
+#define ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_SHIFT  (6U)
+/*! FIFO_UNDERRUN_CLR - Write 1 to clear both adc_reg_irsr and adc_reg_isr */
+#define ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_SHIFT)) & ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RESULT - ADC Result Register */
+/*! @{ */
+
+#define ADC_ADC_REG_RESULT_DATA_MASK             (0xFFFFFFFFU)
+#define ADC_ADC_REG_RESULT_DATA_SHIFT            (0U)
+/*! DATA - ADC finial conversion result data, after calibratiob and signed/unsigned process */
+#define ADC_ADC_REG_RESULT_DATA(x)               (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RESULT_DATA_SHIFT)) & ADC_ADC_REG_RESULT_DATA_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RAW_RESULT - ADC Raw Result Register */
+/*! @{ */
+
+#define ADC_ADC_REG_RAW_RESULT_RAW_DATA_MASK     (0x3FFFFFU)
+#define ADC_ADC_REG_RAW_RESULT_RAW_DATA_SHIFT    (0U)
+/*! RAW_DATA - ADC Raw data in signed 22bit format */
+#define ADC_ADC_REG_RAW_RESULT_RAW_DATA(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RAW_RESULT_RAW_DATA_SHIFT)) & ADC_ADC_REG_RAW_RESULT_RAW_DATA_MASK)
+/*! @} */
+
+/*! @name ADC_REG_OFFSET_CAL - ADC Offset Calibration Register */
+/*! @{ */
+
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_MASK   (0xFFFFU)
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_SHIFT  (0U)
+/*! OFFSET_CAL - ADC self offset calibration value. 16-bit signed . */
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_SHIFT)) & ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_MASK)
+
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_MASK (0xFFFF0000U)
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_SHIFT (16U)
+/*! OFFSET_CAL_USR - User offset calibration data. 16-bit signed. */
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_SHIFT)) & ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_MASK)
+/*! @} */
+
+/*! @name ADC_REG_GAIN_CAL - ADC Gain Calibration Register */
+/*! @{ */
+
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_MASK       (0xFFFFU)
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_SHIFT      (0U)
+/*! GAIN_CAL - ADC self gain calibration value. 16-bit signed. */
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GAIN_CAL_GAIN_CAL_SHIFT)) & ADC_ADC_REG_GAIN_CAL_GAIN_CAL_MASK)
+
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_MASK   (0xFFFF0000U)
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_SHIFT  (16U)
+/*! GAIN_CAL_USR - ADC user gain calibration value. 16-bit signed. */
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_SHIFT)) & ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_MASK)
+/*! @} */
+
+/*! @name ADC_REG_TEST - ADC Test Register */
+/*! @{ */
+
+#define ADC_ADC_REG_TEST_TEST_EN_MASK            (0x1U)
+#define ADC_ADC_REG_TEST_TEST_EN_SHIFT           (0U)
+/*! TEST_EN - Analog test enable. */
+#define ADC_ADC_REG_TEST_TEST_EN(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_TEST_TEST_EN_SHIFT)) & ADC_ADC_REG_TEST_TEST_EN_MASK)
+
+#define ADC_ADC_REG_TEST_TEST_SEL_MASK           (0xEU)
+#define ADC_ADC_REG_TEST_TEST_SEL_SHIFT          (1U)
+/*! TEST_SEL - test_sel */
+#define ADC_ADC_REG_TEST_TEST_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_TEST_TEST_SEL_SHIFT)) & ADC_ADC_REG_TEST_TEST_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_AUDIO - ADC Audio Register */
+/*! @{ */
+
+#define ADC_ADC_REG_AUDIO_EN_MASK                (0x1U)
+#define ADC_ADC_REG_AUDIO_EN_SHIFT               (0U)
+/*! EN - Audio enable. */
+#define ADC_ADC_REG_AUDIO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_EN_SHIFT)) & ADC_ADC_REG_AUDIO_EN_MASK)
+
+#define ADC_ADC_REG_AUDIO_PGA_GAIN_MASK          (0x38U)
+#define ADC_ADC_REG_AUDIO_PGA_GAIN_SHIFT         (3U)
+/*! PGA_GAIN - Audio PGA voltage gain select */
+#define ADC_ADC_REG_AUDIO_PGA_GAIN(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_PGA_GAIN_SHIFT)) & ADC_ADC_REG_AUDIO_PGA_GAIN_MASK)
+
+#define ADC_ADC_REG_AUDIO_PGA_CM_MASK            (0x1C0U)
+#define ADC_ADC_REG_AUDIO_PGA_CM_SHIFT           (6U)
+/*! PGA_CM - Audio PGA output common mode control */
+#define ADC_ADC_REG_AUDIO_PGA_CM(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_PGA_CM_SHIFT)) & ADC_ADC_REG_AUDIO_PGA_CM_MASK)
+
+#define ADC_ADC_REG_AUDIO_PGA_CHOP_EN_MASK       (0x200U)
+#define ADC_ADC_REG_AUDIO_PGA_CHOP_EN_SHIFT      (9U)
+/*! PGA_CHOP_EN - Audio PGA chopper enable. */
+#define ADC_ADC_REG_AUDIO_PGA_CHOP_EN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_PGA_CHOP_EN_SHIFT)) & ADC_ADC_REG_AUDIO_PGA_CHOP_EN_MASK)
+/*! @} */
+
+/*! @name ADC_REG_VOICE_DET - ADC Voice Detect Register */
+/*! @{ */
+
+#define ADC_ADC_REG_VOICE_DET_DET_EN_MASK        (0x1U)
+#define ADC_ADC_REG_VOICE_DET_DET_EN_SHIFT       (0U)
+/*! DET_EN - Voice level detection enable select */
+#define ADC_ADC_REG_VOICE_DET_DET_EN(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_VOICE_DET_DET_EN_SHIFT)) & ADC_ADC_REG_VOICE_DET_DET_EN_MASK)
+
+#define ADC_ADC_REG_VOICE_DET_LEVEL_SEL_MASK     (0xEU)
+#define ADC_ADC_REG_VOICE_DET_LEVEL_SEL_SHIFT    (1U)
+/*! LEVEL_SEL - Voice level selection. */
+#define ADC_ADC_REG_VOICE_DET_LEVEL_SEL(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_VOICE_DET_LEVEL_SEL_SHIFT)) & ADC_ADC_REG_VOICE_DET_LEVEL_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RSVD - ADC Reserved Register */
+/*! @{ */
+
+#define ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_MASK (0xFFFFU)
+#define ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_SHIFT (0U)
+/*! UNUSED_RESERVED_ADC_CONTROL_BITS - unused_Reserved_ADC_control_bits */
+#define ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_SHIFT)) & ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral GAU_GPADC0 base address */
+  #define GAU_GPADC0_BASE                          (0x50038000u)
+  /** Peripheral GAU_GPADC0 base address */
+  #define GAU_GPADC0_BASE_NS                       (0x40038000u)
+  /** Peripheral GAU_GPADC0 base pointer */
+  #define GAU_GPADC0                               ((ADC_Type *)GAU_GPADC0_BASE)
+  /** Peripheral GAU_GPADC0 base pointer */
+  #define GAU_GPADC0_NS                            ((ADC_Type *)GAU_GPADC0_BASE_NS)
+  /** Peripheral GAU_GPADC1 base address */
+  #define GAU_GPADC1_BASE                          (0x50038100u)
+  /** Peripheral GAU_GPADC1 base address */
+  #define GAU_GPADC1_BASE_NS                       (0x40038100u)
+  /** Peripheral GAU_GPADC1 base pointer */
+  #define GAU_GPADC1                               ((ADC_Type *)GAU_GPADC1_BASE)
+  /** Peripheral GAU_GPADC1 base pointer */
+  #define GAU_GPADC1_NS                            ((ADC_Type *)GAU_GPADC1_BASE_NS)
+  /** Array initializer of ADC peripheral base addresses */
+  #define ADC_BASE_ADDRS                           { GAU_GPADC0_BASE, GAU_GPADC1_BASE }
+  /** Array initializer of ADC peripheral base pointers */
+  #define ADC_BASE_PTRS                            { GAU_GPADC0, GAU_GPADC1 }
+  /** Array initializer of ADC peripheral base addresses */
+  #define ADC_BASE_ADDRS_NS                        { GAU_GPADC0_BASE_NS, GAU_GPADC1_BASE_NS }
+  /** Array initializer of ADC peripheral base pointers */
+  #define ADC_BASE_PTRS_NS                         { GAU_GPADC0_NS, GAU_GPADC1_NS }
+#else
+  /** Peripheral GAU_GPADC0 base address */
+  #define GAU_GPADC0_BASE                          (0x40038000u)
+  /** Peripheral GAU_GPADC0 base pointer */
+  #define GAU_GPADC0                               ((ADC_Type *)GAU_GPADC0_BASE)
+  /** Peripheral GAU_GPADC1 base address */
+  #define GAU_GPADC1_BASE                          (0x40038100u)
+  /** Peripheral GAU_GPADC1 base pointer */
+  #define GAU_GPADC1                               ((ADC_Type *)GAU_GPADC1_BASE)
+  /** Array initializer of ADC peripheral base addresses */
+  #define ADC_BASE_ADDRS                           { GAU_GPADC0_BASE, GAU_GPADC1_BASE }
+  /** Array initializer of ADC peripheral base pointers */
+  #define ADC_BASE_PTRS                            { GAU_GPADC0, GAU_GPADC1 }
+#endif
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { GAU_ADC0_IRQn, GAU_ADC1_IRQn }
+/* Backward compatibility */
+#define kADC_TriggerSourceGpt                    kADC_TriggerSourceCtimer
+#define kADC_TriggerSourceGpio40                 kADC_TriggerSourceGpio50
+#define kADC_TriggerSourceGpio41                 kADC_TriggerSourceGpio55
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AHB_SECURE_CTRL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** AHB_SECURE_CTRL - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t BOOTROM0_MEM_RULE[4];              /**< 0x03000000-0x0303FFFF part0..0x03000000-0x0303FFFF part3, array offset: 0x10, array step: 0x4 */
+  struct {                                         /* offset: 0x20, array step: 0xB0 */
+         uint8_t RESERVED_0[16];
+    __IO uint32_t REGION0_MEM_RULE[4];               /**< 0x08000000--0x080FFFFF..0x48300000--0x483FFFFF, array offset: 0x30, array step: index*0xB0, index2*0x4 */
+    __IO uint32_t REGION1_MEM_RULE;                  /**< 0x08400000--0x087FFFFF..0x48400000--0x487FFFFF, array offset: 0x40, array step: 0xB0 */
+         uint8_t RESERVED_1[12];
+    __IO uint32_t REGION2_MEM_RULE;                  /**< 0x08800000--0x08FFFFFF..0x48800000--0x48FFFFFF, array offset: 0x50, array step: 0xB0 */
+         uint8_t RESERVED_2[12];
+    __IO uint32_t REGION3_MEM_RULE;                  /**< 0x09000000--0x09FFFFFF..0x49000000--0x49FFFFFF, array offset: 0x60, array step: 0xB0 */
+         uint8_t RESERVED_3[12];
+    __IO uint32_t REGION4_MEM_RULE;                  /**< 0x0A000000--0x0BFFFFFF..0x4A000000--0x4BFFFFFF, array offset: 0x70, array step: 0xB0 */
+         uint8_t RESERVED_4[12];
+    __IO uint32_t REGION5_MEM_RULE[4];               /**< 0x0C000000--0x0C0FFFFF..0x4C300000--0x4C3FFFFF, array offset: 0x80, array step: index*0xB0, index2*0x4 */
+    __IO uint32_t REGION6_MEM_RULE;                  /**< 0x0C400000--0x0C7FFFFF..0x4C400000--0x4C7FFFFF, array offset: 0x90, array step: 0xB0 */
+         uint8_t RESERVED_5[12];
+    __IO uint32_t REGION7_MEM_RULE;                  /**< 0x0C800000--0x0CFFFFFF..0x4C800000--0x4CFFFFFF, array offset: 0xA0, array step: 0xB0 */
+         uint8_t RESERVED_6[12];
+    __IO uint32_t REGION8_MEM_RULE;                  /**< 0x0D000000~0x0DFFFFFFF..0x4D000000~0x4DFFFFFFF, array offset: 0xB0, array step: 0xB0 */
+         uint8_t RESERVED_7[12];
+    __IO uint32_t REGION9_MEM_RULE;                  /**< 0x0E000000~0x0FFFFFFF..0x4E000000~0x4FFFFFFF, array offset: 0xC0, array step: 0xB0 */
+         uint8_t RESERVED_8[12];
+  } FLEXSPI_RULES[3];
+       uint8_t RESERVED_1[16];
+  __IO uint32_t RAM00_RULE[4];                     /**< 0x20000000--0x2000FFFF part0..0x20000000--0x2000FFFF part3, array offset: 0x240, array step: 0x4 */
+  __IO uint32_t RAM01_RULE[4];                     /**< 0x20010000--0x2001FFFF part0..0x20010000--0x2001FFFF part3, array offset: 0x250, array step: 0x4 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t RAM02_RULE[4];                     /**< 0x20020000--0x2002FFFF part0..0x20020000--0x2002FFFF part3, array offset: 0x270, array step: 0x4 */
+  __IO uint32_t RAM03_RULE[4];                     /**< 0x20030000--0x2003FFFF part0..0x20030000--0x2003FFFF part3, array offset: 0x280, array step: 0x4 */
+       uint8_t RESERVED_3[16];
+  __IO uint32_t RAM04_RULE[4];                     /**< 0x20040000--0x2004FFFF part0..0x20040000--0x2004FFFF part3, array offset: 0x2A0, array step: 0x4 */
+  __IO uint32_t RAM05_RULE[4];                     /**< 0x20050000--0x2005FFFF part0..0x20050000--0x2005FFFF part3, array offset: 0x2B0, array step: 0x4 */
+       uint8_t RESERVED_4[16];
+  __IO uint32_t RAM06_RULE[4];                     /**< 0x20060000--0x2006FFFF part0..0x20060000--0x2006FFFF part3, array offset: 0x2D0, array step: 0x4 */
+  __IO uint32_t RAM07_RULE[4];                     /**< 0x20070000--0x2007FFFF part0..0x20070000--0x2007FFFF part3, array offset: 0x2E0, array step: 0x4 */
+       uint8_t RESERVED_5[16];
+  __IO uint32_t RAM08_RULE[4];                     /**< 0x20080000--0x2008FFFF part0..0x20080000--0x2008FFFF part3, array offset: 0x300, array step: 0x4 */
+  __IO uint32_t RAM09_RULE[4];                     /**< 0x20090000--0x2009FFFF part0..0x20090000--0x2009FFFF part3, array offset: 0x310, array step: 0x4 */
+  __IO uint32_t RAM10_RULE[4];                     /**< 0x200A0000--0x200AFFFF part0..0x200A0000--0x200AFFFF part3, array offset: 0x320, array step: 0x4 */
+  __IO uint32_t RAM11_RULE[4];                     /**< 0x200B0000--0x200BFFFF part0..0x200B0000--0x200BFFFF part3, array offset: 0x330, array step: 0x4 */
+       uint8_t RESERVED_6[16];
+  __IO uint32_t RAM12_RULE[4];                     /**< 0x200C0000--0x200CFFFF part0..0x200C0000--0x200CFFFF part3, array offset: 0x350, array step: 0x4 */
+  __IO uint32_t RAM13_RULE[4];                     /**< 0x200D0000--0x200DFFFF part0..0x200D0000--0x200DFFFF part3, array offset: 0x360, array step: 0x4 */
+  __IO uint32_t RAM14_RULE[4];                     /**< 0x200E0000--0x200EFFFF part0..0x200E0000--0x200EFFFF part3, array offset: 0x370, array step: 0x4 */
+  __IO uint32_t RAM15_RULE[4];                     /**< 0x200F0000--0x200FFFFF part0..0x200F0000--0x200FFFFF part3, array offset: 0x380, array step: 0x4 */
+       uint8_t RESERVED_7[16];
+  __IO uint32_t RAM16_RULE[4];                     /**< 0x20100000--0x2010FFFF part0..0x20100000--0x2010FFFF part3, array offset: 0x3A0, array step: 0x4 */
+  __IO uint32_t RAM17_RULE[4];                     /**< 0x20011000--0x20011FFF part0..0x20011000--0x20011FFF part3, array offset: 0x3B0, array step: 0x4 */
+  __IO uint32_t RAM18_RULE[4];                     /**< 0x20012000--0x20012FFF part0..0x20012000--0x20012FFF part3, array offset: 0x3C0, array step: 0x4 */
+       uint8_t RESERVED_8[16];
+  __IO uint32_t APB_GRP0_MEM_RULE0;                /**< 0x4000000--0x40007FFF, offset: 0x3E0 */
+  __IO uint32_t APB_GRP0_MEM_RULE1;                /**< 0x40008000~0x4000FFFF, offset: 0x3E4 */
+  __IO uint32_t APB_GRP0_MEM_RULE2;                /**< 0x40010000--0x40017FFF, offset: 0x3E8 */
+  __IO uint32_t APB_GRP0_MEM_RULE3;                /**< 0x40018000--0x4001FFFF, offset: 0x3EC */
+  __IO uint32_t APB_GRP1_MEM_RULE0;                /**< 0x40020000--0x40027FFF, offset: 0x3F0 */
+  __IO uint32_t APB_GRP1_MEM_RULE1;                /**< 0x40028000--0x4002FFFF, offset: 0x3F4 */
+  __IO uint32_t APB_GRP1_MEM_RULE2;                /**< 0x40030000--0x40037FFF, offset: 0x3F8 */
+  __IO uint32_t APB_GRP1_MEM_RULE3;                /**< 0x40038000--0x4003FFFF, offset: 0x3FC */
+  __IO uint32_t AHB_PERIPH0_SLAVE_RULE;            /**< 0x40100000--0x4011FFFF, offset: 0x400 */
+       uint8_t RESERVED_9[12];
+  __IO uint32_t AHB_PERIPH1_SLAVE_RULE;            /**< 0x40120000--0x40127FFF, offset: 0x410 */
+       uint8_t RESERVED_10[28];
+  __IO uint32_t AIPS_BRIDGE_MEM_RULE0;             /**< 0x4013 0000 ~0x4013 7FFF, offset: 0x430 */
+  __IO uint32_t AIPS_BRIDGE_MEM_RULE1;             /**< 0x4013 8000 ~0x4013 FFFF, offset: 0x434 */
+       uint8_t RESERVED_11[8];
+  __IO uint32_t AHB_PERIPH2_SLAVE_RULE;            /**< 0x40140000--0x4014FFFF, offset: 0x440 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t SECURITY_CTRL_MEM_RULE;            /**< 0x40148000--0x4014BFFF, offset: 0x450 */
+       uint8_t RESERVED_13[12];
+  __IO uint32_t AHB_PERIPH3_SLAVE_RULE;            /**< the memory map is 0x40150000--0x40158FFF, offset: 0x460 */
+       uint8_t RESERVED_14[12];
+  __IO uint32_t AON_MEM_RULE;                      /**< 0x4015C000--0x4015FFFF, offset: 0x470 */
+       uint8_t RESERVED_15[12];
+  __IO uint32_t WLAN_S0_SLAVE_RULE;                /**< 0x41000000-0x4137FFFF, 3.5MB, offset: 0x480 */
+       uint8_t RESERVED_16[12];
+  __IO uint32_t WLAN_S1_MEM_RULE[4];               /**< 0x41380000-0x413FFFFF, part0..0x41380000-0x413FFFFF, part3, array offset: 0x490, array step: 0x4 */
+  __IO uint32_t BLE_S0_SLAVE_RULE;                 /**< 0x44000000-0x443BFFFF, offset: 0x4A0 */
+       uint8_t RESERVED_17[12];
+  __IO uint32_t BLE_S1_MEM_RULE[4];                /**< 0x443C0000-0x443FFFFF part0..0x443C0000-0x443FFFFF part3, array offset: 0x4B0, array step: 0x4 */
+       uint8_t RESERVED_18[16];
+  __IO uint32_t SOC_TOP_MEM_RULE[4];               /**< 0x45000000-0x4500FFFF part0..0x45000000-0x4500FFFF part3, array offset: 0x4D0, array step: 0x4 */
+       uint8_t RESERVED_19[2336];
+  __I  uint32_t SEC_VIO_ADDR[20];                  /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */
+       uint8_t RESERVED_20[48];
+  __I  uint32_t SEC_VIO_MISC_INFO[20];             /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */
+       uint8_t RESERVED_21[48];
+  __IO uint32_t SEC_VIO_INFO_VALID;                /**< security violation address/information registers valid flags, offset: 0xF00 */
+       uint8_t RESERVED_22[124];
+  __IO uint32_t SEC_GPIO_MASK0;                    /**< Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world., offset: 0xF80 */
+  __IO uint32_t SEC_GPIO_MASK1;                    /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
+       uint8_t RESERVED_23[52];
+  __IO uint32_t SEC_MASK_LOCK;                     /**< sec_gp_reg write-lock bits, offset: 0xFBC */
+       uint8_t RESERVED_24[16];
+  __IO uint32_t MASTER_SEC_LEVEL;                  /**< master secure level register, offset: 0xFD0 */
+  __IO uint32_t MASTER_SEC_LEVEL_ANTI_POL;         /**< master secure level anti-pole register, offset: 0xFD4 */
+       uint8_t RESERVED_25[20];
+  __IO uint32_t CM33_LOCK_REG;                     /**< m33 lock control register, offset: 0xFEC */
+       uint8_t RESERVED_26[8];
+  __IO uint32_t MISC_CTRL_DP_REG;                  /**< secure control duplicate register, offset: 0xFF8 */
+  __IO uint32_t MISC_CTRL_REG;                     /**< secure control register, offset: 0xFFC */
+} AHB_SECURE_CTRL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AHB_SECURE_CTRL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks
+ * @{
+ */
+
+/*! @name BOOTROM0_MEM_RULE - 0x03000000-0x0303FFFF part0..0x03000000-0x0303FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_BOOTROM0_MEM_RULE */
+#define AHB_SECURE_CTRL_BOOTROM0_MEM_RULE_COUNT  (4U)
+
+/*! @name FLEXSPI_RULES_REGION0_MEM_RULE - 0x08000000--0x080FFFFF..0x48300000--0x483FFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_COUNT (3U)
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION0_MEM_RULE_COUNT2 (4U)
+
+/*! @name FLEXSPI_RULES_REGION1_MEM_RULE - 0x08400000--0x087FFFFF..0x48400000--0x487FFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION1_MEM_RULE_COUNT (3U)
+
+/*! @name FLEXSPI_RULES_REGION2_MEM_RULE - 0x08800000--0x08FFFFFF..0x48800000--0x48FFFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION2_MEM_RULE_COUNT (3U)
+
+/*! @name FLEXSPI_RULES_REGION3_MEM_RULE - 0x09000000--0x09FFFFFF..0x49000000--0x49FFFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION3_MEM_RULE_COUNT (3U)
+
+/*! @name FLEXSPI_RULES_REGION4_MEM_RULE - 0x0A000000--0x0BFFFFFF..0x4A000000--0x4BFFFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION4_MEM_RULE_COUNT (3U)
+
+/*! @name FLEXSPI_RULES_REGION5_MEM_RULE - 0x0C000000--0x0C0FFFFF..0x4C300000--0x4C3FFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_COUNT (3U)
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION5_MEM_RULE_COUNT2 (4U)
+
+/*! @name FLEXSPI_RULES_REGION6_MEM_RULE - 0x0C400000--0x0C7FFFFF..0x4C400000--0x4C7FFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION6_MEM_RULE_COUNT (3U)
+
+/*! @name FLEXSPI_RULES_REGION7_MEM_RULE - 0x0C800000--0x0CFFFFFF..0x4C800000--0x4CFFFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION7_MEM_RULE_COUNT (3U)
+
+/*! @name FLEXSPI_RULES_REGION8_MEM_RULE - 0x0D000000~0x0DFFFFFFF..0x4D000000~0x4DFFFFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION8_MEM_RULE_COUNT (3U)
+
+/*! @name FLEXSPI_RULES_REGION9_MEM_RULE - 0x0E000000~0x0FFFFFFF..0x4E000000~0x4FFFFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI_RULES_REGION9_MEM_RULE_COUNT (3U)
+
+/*! @name RAM00_RULE - 0x20000000--0x2000FFFF part0..0x20000000--0x2000FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM00_RULE */
+#define AHB_SECURE_CTRL_RAM00_RULE_COUNT         (4U)
+
+/*! @name RAM01_RULE - 0x20010000--0x2001FFFF part0..0x20010000--0x2001FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM01_RULE */
+#define AHB_SECURE_CTRL_RAM01_RULE_COUNT         (4U)
+
+/*! @name RAM02_RULE - 0x20020000--0x2002FFFF part0..0x20020000--0x2002FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM02_RULE */
+#define AHB_SECURE_CTRL_RAM02_RULE_COUNT         (4U)
+
+/*! @name RAM03_RULE - 0x20030000--0x2003FFFF part0..0x20030000--0x2003FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM03_RULE */
+#define AHB_SECURE_CTRL_RAM03_RULE_COUNT         (4U)
+
+/*! @name RAM04_RULE - 0x20040000--0x2004FFFF part0..0x20040000--0x2004FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM04_RULE */
+#define AHB_SECURE_CTRL_RAM04_RULE_COUNT         (4U)
+
+/*! @name RAM05_RULE - 0x20050000--0x2005FFFF part0..0x20050000--0x2005FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM05_RULE */
+#define AHB_SECURE_CTRL_RAM05_RULE_COUNT         (4U)
+
+/*! @name RAM06_RULE - 0x20060000--0x2006FFFF part0..0x20060000--0x2006FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM06_RULE */
+#define AHB_SECURE_CTRL_RAM06_RULE_COUNT         (4U)
+
+/*! @name RAM07_RULE - 0x20070000--0x2007FFFF part0..0x20070000--0x2007FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM07_RULE */
+#define AHB_SECURE_CTRL_RAM07_RULE_COUNT         (4U)
+
+/*! @name RAM08_RULE - 0x20080000--0x2008FFFF part0..0x20080000--0x2008FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM08_RULE */
+#define AHB_SECURE_CTRL_RAM08_RULE_COUNT         (4U)
+
+/*! @name RAM09_RULE - 0x20090000--0x2009FFFF part0..0x20090000--0x2009FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM09_RULE */
+#define AHB_SECURE_CTRL_RAM09_RULE_COUNT         (4U)
+
+/*! @name RAM10_RULE - 0x200A0000--0x200AFFFF part0..0x200A0000--0x200AFFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM10_RULE */
+#define AHB_SECURE_CTRL_RAM10_RULE_COUNT         (4U)
+
+/*! @name RAM11_RULE - 0x200B0000--0x200BFFFF part0..0x200B0000--0x200BFFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM11_RULE */
+#define AHB_SECURE_CTRL_RAM11_RULE_COUNT         (4U)
+
+/*! @name RAM12_RULE - 0x200C0000--0x200CFFFF part0..0x200C0000--0x200CFFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM12_RULE */
+#define AHB_SECURE_CTRL_RAM12_RULE_COUNT         (4U)
+
+/*! @name RAM13_RULE - 0x200D0000--0x200DFFFF part0..0x200D0000--0x200DFFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM13_RULE */
+#define AHB_SECURE_CTRL_RAM13_RULE_COUNT         (4U)
+
+/*! @name RAM14_RULE - 0x200E0000--0x200EFFFF part0..0x200E0000--0x200EFFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM14_RULE */
+#define AHB_SECURE_CTRL_RAM14_RULE_COUNT         (4U)
+
+/*! @name RAM15_RULE - 0x200F0000--0x200FFFFF part0..0x200F0000--0x200FFFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM15_RULE */
+#define AHB_SECURE_CTRL_RAM15_RULE_COUNT         (4U)
+
+/*! @name RAM16_RULE - 0x20100000--0x2010FFFF part0..0x20100000--0x2010FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM16_RULE */
+#define AHB_SECURE_CTRL_RAM16_RULE_COUNT         (4U)
+
+/*! @name RAM17_RULE - 0x20011000--0x20011FFF part0..0x20011000--0x20011FFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM17_RULE */
+#define AHB_SECURE_CTRL_RAM17_RULE_COUNT         (4U)
+
+/*! @name RAM18_RULE - 0x20012000--0x20012FFF part0..0x20012000--0x20012FFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE0_MASK    (0x3U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE0_SHIFT   (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE0(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK    (0x30U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT   (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE1(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK    (0x300U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT   (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE2(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE3_MASK    (0x3000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE3_SHIFT   (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE3(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE4_MASK    (0x30000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE4_SHIFT   (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE4(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE5_MASK    (0x300000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE5_SHIFT   (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE5(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE6_MASK    (0x3000000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE6_SHIFT   (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE6(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE7_MASK    (0x30000000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE7_SHIFT   (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE7(x)      (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM18_RULE */
+#define AHB_SECURE_CTRL_RAM18_RULE_COUNT         (4U)
+
+/*! @name APB_GRP0_MEM_RULE0 - 0x4000000--0x40007FFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_RSTCTL0_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_RSTCTL0_RULE0_SHIFT (0U)
+/*! RSTCTL0_RULE0 - 0x4000 0000--0x4000 0FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_RSTCTL0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_RSTCTL0_RULE0_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_RSTCTL0_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_CLKCTL0_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_CLKCTL0_RULE1_SHIFT (4U)
+/*! CLKCTL0_RULE1 - 0x4000 1000--0x4000 1FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_CLKCTL0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_CLKCTL0_RULE1_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_CLKCTL0_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL0_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL0_RULE2_SHIFT (8U)
+/*! SYSCTL0_RULE2 - 0x4000 2000--0x4000 2FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL0_RULE2_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL0_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL2_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL2_RULE3_SHIFT (12U)
+/*! SYSCTL2_RULE3 - 0x4000 3000--0x4000 3FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL2_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL2_RULE3_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_SYSCTL2_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_IOCON_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_IOCON_RULE4_SHIFT (16U)
+/*! IOCON_RULE4 - 0x4000 4000--0x4000 4FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_IOCON_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_IOCON_RULE4_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_IOCON_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_PUFCTRL_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_PUFCTRL_RULE6_SHIFT (24U)
+/*! PUFCTRL_RULE6 - 0x4000 6000--0x4000 6FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_PUFCTRL_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_PUFCTRL_RULE6_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_PUFCTRL_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_ELS_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_ELS_RULE7_SHIFT (28U)
+/*! ELS_RULE7 - 0x4000 7000--0x4000 7FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_ELS_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_ELS_RULE7_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE0_ELS_RULE7_MASK)
+/*! @} */
+
+/*! @name APB_GRP0_MEM_RULE1 - 0x40008000~0x4000FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_USIM_RULE8_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_USIM_RULE8_SHIFT (0U)
+/*! USIM_RULE8 - 0x4000 8000--0x4000 8FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_USIM_RULE8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_USIM_RULE8_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_USIM_RULE8_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_PKC_RULE9_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_PKC_RULE9_SHIFT (4U)
+/*! PKC_RULE9 - 0x4000 9000--0x4000 9FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_PKC_RULE9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_PKC_RULE9_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_PKC_RULE9_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_RULE10_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_RULE10_SHIFT (8U)
+/*! OCOTP_RULE10 - 0x4000 A000--0x4000 AFFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_RULE10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_RULE10_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_RULE10_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_ADAP_RULE11_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_ADAP_RULE11_SHIFT (12U)
+/*! OCOTP_ADAP_RULE11 - 0x4000 A000--0x4000 AFFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_ADAP_RULE11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_ADAP_RULE11_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_OCOTP_ADAP_RULE11_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_WWDT0_RULE14_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_WWDT0_RULE14_SHIFT (24U)
+/*! WWDT0_RULE14 - 0x4000 E000--0x4000 EFFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_WWDT0_RULE14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_WWDT0_RULE14_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_WWDT0_RULE14_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_UTICK_RULE15_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_UTICK_RULE15_SHIFT (28U)
+/*! UTICK_RULE15 - 0x4000 F000--0x4000 FFFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_UTICK_RULE15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_UTICK_RULE15_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE1_UTICK_RULE15_MASK)
+/*! @} */
+
+/*! @name APB_GRP0_MEM_RULE2 - 0x40010000--0x40017FFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE2_TRNG_RULE20_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE2_TRNG_RULE20_SHIFT (16U)
+/*! TRNG_RULE20 - 0x4001 4000--0x4001 4FFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE2_TRNG_RULE20(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE2_TRNG_RULE20_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE2_TRNG_RULE20_MASK)
+/*! @} */
+
+/*! @name APB_GRP0_MEM_RULE3 - 0x40018000--0x4001FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0_DOMAIN_TESTCON_RULE27_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0_DOMAIN_TESTCON_RULE27_SHIFT (12U)
+/*! C0_DOMAIN_TESTCON_RULE27 - 0x4001 B000--0x4001 BFFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0_DOMAIN_TESTCON_RULE27(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0_DOMAIN_TESTCON_RULE27_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0_DOMAIN_TESTCON_RULE27_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0AON_DOMAIN_TESTCON_RULE28_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0AON_DOMAIN_TESTCON_RULE28_SHIFT (16U)
+/*! C0AON_DOMAIN_TESTCON_RULE28 - 0x4001 C000--0x4001 CFFF */
+#define AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0AON_DOMAIN_TESTCON_RULE28(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0AON_DOMAIN_TESTCON_RULE28_SHIFT)) & AHB_SECURE_CTRL_APB_GRP0_MEM_RULE3_C0AON_DOMAIN_TESTCON_RULE28_MASK)
+/*! @} */
+
+/*! @name APB_GRP1_MEM_RULE0 - 0x40020000--0x40027FFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_RSTCTL1_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_RSTCTL1_RULE0_SHIFT (0U)
+/*! RSTCTL1_RULE0 - 0x4002 0000--0x4002 0FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_RSTCTL1_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_RSTCTL1_RULE0_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_RSTCTL1_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_CLKCTL1_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_CLKCTL1_RULE1_SHIFT (4U)
+/*! CLKCTL1_RULE1 - 0x4002 1000--0x4002 1FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_CLKCTL1_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_CLKCTL1_RULE1_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_CLKCTL1_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_SYSCTL1_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_SYSCTL1_RULE2_SHIFT (8U)
+/*! SYSCTL1_RULE2 - 0x4002 2000--0x4002 2FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_SYSCTL1_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_SYSCTL1_RULE2_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_SYSCTL1_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_ITRC_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_ITRC_RULE4_SHIFT (16U)
+/*! ITRC_RULE4 - 0x4002 4000--0x4002 4FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_ITRC_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_ITRC_RULE4_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_ITRC_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_GPIO_INTR_CTRL_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_GPIO_INTR_CTRL_RULE5_SHIFT (20U)
+/*! GPIO_INTR_CTRL_RULE5 - 0x4002 5000--0x4002 5FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_GPIO_INTR_CTRL_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_GPIO_INTR_CTRL_RULE5_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_GPIO_INTR_CTRL_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_PERIPH_INPUT_MUX_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_PERIPH_INPUT_MUX_RULE6_SHIFT (24U)
+/*! PERIPH_INPUT_MUX_RULE6 - 0x4002 6000--0x4002 6FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_PERIPH_INPUT_MUX_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_PERIPH_INPUT_MUX_RULE6_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE0_PERIPH_INPUT_MUX_RULE6_MASK)
+/*! @} */
+
+/*! @name APB_GRP1_MEM_RULE1 - 0x40028000--0x4002FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT0_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT0_RULE0_SHIFT (0U)
+/*! CT32BIT0_RULE0 - 0x4002 8000--0x4002 8FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT0_RULE0_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT0_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT1_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT1_RULE1_SHIFT (4U)
+/*! CT32BIT1_RULE1 - 0x4002 9000--0x4002 9FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT1_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT1_RULE1_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT1_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT2_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT2_RULE2_SHIFT (8U)
+/*! CT32BIT2_RULE2 - 0x4002 A000--0x4002 AFFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT2_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT2_RULE2_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT2_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT3_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT3_RULE3_SHIFT (12U)
+/*! CT32BIT3_RULE3 - 0x4002 B000--0x4002 BFFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT3_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT3_RULE3_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_CT32BIT3_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_MRT_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_MRT_RULE5_SHIFT (20U)
+/*! MRT_RULE5 - 0x4002 D000--0x4002 DFFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_MRT_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_MRT_RULE5_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_MRT_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_FREQME_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_FREQME_RULE7_SHIFT (28U)
+/*! FREQME_RULE7 - 0x4002 F000--0x4002 FFFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_FREQME_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_FREQME_RULE7_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE1_FREQME_RULE7_MASK)
+/*! @} */
+
+/*! @name APB_GRP1_MEM_RULE2 - 0x40030000--0x40037FFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_RTC_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_RTC_RULE0_SHIFT (0U)
+/*! RTC_RULE0 - 0x4003 0000--0x4003 0FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_RTC_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_RTC_RULE0_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_RTC_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_PMU_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_PMU_RULE1_SHIFT (4U)
+/*! PMU_RULE1 - 0x4003 1000--0x4003 1FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_PMU_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_PMU_RULE1_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_PMU_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE0_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE0_RULE3_SHIFT (12U)
+/*! FLASH_CACHE0_RULE3 - 0x4003 3000--0x4003 3FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE0_RULE3_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE0_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE1_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE1_RULE4_SHIFT (16U)
+/*! FLASH_CACHE1_RULE4 - 0x4003 4000--0x4003 4FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE1_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE1_RULE4_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE2_FLASH_CACHE1_RULE4_MASK)
+/*! @} */
+
+/*! @name APB_GRP1_MEM_RULE3 - 0x40038000--0x4003FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_GAU_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_GAU_RULE0_SHIFT (0U)
+/*! GAU_RULE0 - 0x4003 8000--0x4003 8FFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_GAU_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_GAU_RULE0_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_GAU_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_RF_SYSCON_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_RF_SYSCON_RULE3_SHIFT (12U)
+/*! RF_SYSCON_RULE3 - 0x4003 B000--0x4003 BFFF */
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_RF_SYSCON_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_RF_SYSCON_RULE3_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_RF_SYSCON_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_FREEMRT_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_FREEMRT_RULE7_SHIFT (28U)
+#define AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_FREEMRT_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_FREEMRT_RULE7_SHIFT)) & AHB_SECURE_CTRL_APB_GRP1_MEM_RULE3_FREEMRT_RULE7_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH0_SLAVE_RULE - 0x40100000--0x4011FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_HSGPIO_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_HSGPIO_RULE0_SHIFT (0U)
+/*! HSGPIO_RULE0 - 0x40100000--0x40103FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_HSGPIO_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_HSGPIO_RULE0_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_HSGPIO_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA0_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA0_RULE1_SHIFT (4U)
+/*! DMA0_RULE1 - 0x40104000--0x40104FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA0_RULE1_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA0_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA1_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA1_RULE2_SHIFT (8U)
+/*! DMA1_RULE2 - 0x40105000--0x40105FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA1_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA1_RULE2_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DMA1_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM0_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM0_RULE3_SHIFT (12U)
+/*! FLEXCOMM0_RULE3 - 0x40106000--0x40106FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM0_RULE3_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM0_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM1_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM1_RULE4_SHIFT (16U)
+/*! FLEXCOMM1_RULE4 - 0x40107000--0x40107FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM1_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM1_RULE4_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM1_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM2_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM2_RULE5_SHIFT (20U)
+/*! FLEXCOMM2_RULE5 - 0x40108000--0x40108FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM2_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM2_RULE5_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM2_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM3_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM3_RULE6_SHIFT (24U)
+/*! FLEXCOMM3_RULE6 - 0x40109000--0x40109FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM3_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM3_RULE6_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_FLEXCOMM3_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DEBUG_MAILBOX_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DEBUG_MAILBOX_RULE7_SHIFT (28U)
+/*! DEBUG_MAILBOX_RULE7 - 0x4010F000--0x4010FFFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DEBUG_MAILBOX_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DEBUG_MAILBOX_RULE7_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE_DEBUG_MAILBOX_RULE7_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH1_SLAVE_RULE - 0x40120000--0x40127FFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_CRC_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_CRC_RULE0_SHIFT (0U)
+/*! CRC_RULE0 - 0x40120000--0x40120FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_CRC_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_CRC_RULE0_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_CRC_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_DMIC_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_DMIC_RULE1_SHIFT (4U)
+/*! DMIC_RULE1 - 0x40121000--0x40121FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_DMIC_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_DMIC_RULE1_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_DMIC_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM4_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM4_RULE2_SHIFT (8U)
+/*! FLEXCOMM4_RULE2 - 0x40122000--0x40122FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM4_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM4_RULE2_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM4_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM14_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM14_RULE6_SHIFT (24U)
+/*! FLEXCOMM14_RULE6 - 0x40126000--0x40126FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM14_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM14_RULE6_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE_FLEXCOMM14_RULE6_MASK)
+/*! @} */
+
+/*! @name AIPS_BRIDGE_MEM_RULE0 - 0x4013 0000 ~0x4013 7FFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE0_OSPI_AND_OTFAD_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE0_OSPI_AND_OTFAD_RULE4_SHIFT (16U)
+/*! OSPI_AND_OTFAD_RULE4 - 0x4013 4000--0x4013 4FFF */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE0_OSPI_AND_OTFAD_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE0_OSPI_AND_OTFAD_RULE4_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE0_OSPI_AND_OTFAD_RULE4_MASK)
+/*! @} */
+
+/*! @name AIPS_BRIDGE_MEM_RULE1 - 0x4013 8000 ~0x4013 FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ENET_MASK (0x3U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ENET_SHIFT (0U)
+/*! ENET - 0x4013 8000--0x4013 8FFF */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ENET_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ENET_MASK)
+
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_OSTIMER_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_OSTIMER_RULE3_SHIFT (12U)
+/*! OSTIMER_RULE3 - 0x4013 B000--0x4013 BFFF */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_OSTIMER_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_OSTIMER_RULE3_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_OSTIMER_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ROM_CTRL_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ROM_CTRL_RULE4_SHIFT (16U)
+/*! ROM_CTRL_RULE4 - 0x4013 C000--0x4013 CFFF */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ROM_CTRL_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ROM_CTRL_RULE4_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ROM_CTRL_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_MTR_TEST_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_MTR_TEST_RULE6_SHIFT (24U)
+/*! MTR_TEST_RULE6 - 0x4013 E000--0x4013 EFFF */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_MTR_TEST_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_MTR_TEST_RULE6_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_MTR_TEST_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ATX_TEST_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ATX_TEST_RULE7_SHIFT (28U)
+/*! ATX_TEST_RULE7 - 0x4013 F000--0x4013 FFFF */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ATX_TEST_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ATX_TEST_RULE7_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE_MEM_RULE1_ATX_TEST_RULE7_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH2_SLAVE_RULE - 0x40140000--0x4014FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_USBOTG_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_USBOTG_SHIFT (0U)
+/*! USBOTG - 0x40145000--0x40145FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_USBOTG_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_USBOTG_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_SCT_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_SCT_SHIFT (4U)
+/*! SCT - 0x40146000--0x40146FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_SCT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_SCT_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_SCT_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_GDMA_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_GDMA_SHIFT (8U)
+/*! GDMA - 0x4014E000--0x4014EFFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_GDMA(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_GDMA_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_GDMA_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_CDOG_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_CDOG_SHIFT (16U)
+/*! CDOG - 0x4014C000--0x4014C7FF */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_CDOG(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_CDOG_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE_CDOG_MASK)
+/*! @} */
+
+/*! @name SECURITY_CTRL_MEM_RULE - 0x40148000--0x4014BFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SECURITY_CTRL_MEM_RULE_RULE3_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH3_SLAVE_RULE - the memory map is 0x40150000--0x40158FFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PQ_COPRO_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PQ_COPRO_RULE0_SHIFT (0U)
+/*! PQ_COPRO_RULE0 - 0x40150000--0x40150FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PQ_COPRO_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PQ_COPRO_RULE0_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PQ_COPRO_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SECURE_GPIO_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SECURE_GPIO_RULE1_SHIFT (4U)
+/*! SECURE_GPIO_RULE1 - 0x40154000--0x40157FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SECURE_GPIO_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SECURE_GPIO_RULE1_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SECURE_GPIO_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SDIO_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SDIO_RULE2_SHIFT (8U)
+/*! SDIO_RULE2 - 0x40158000--0x40158FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SDIO_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SDIO_RULE2_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_SDIO_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_HPU_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_HPU_RULE3_SHIFT (12U)
+/*! HPU_RULE3 - 0x40154000--0x40157FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_HPU_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_HPU_RULE3_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_HPU_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PKC_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PKC_RULE4_SHIFT (16U)
+/*! PKC_RULE4 - 0x40158000--0x40158FFF */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PKC_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PKC_RULE4_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE_PKC_RULE4_MASK)
+/*! @} */
+
+/*! @name AON_MEM_RULE - 0x4015C000--0x4015FFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE0_MASK  (0x3U)
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE0(x)    (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AON_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_AON_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE1_MASK  (0x30U)
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE1(x)    (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AON_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_AON_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE2_MASK  (0x300U)
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE2(x)    (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AON_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_AON_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE3_MASK  (0x3000U)
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_AON_MEM_RULE_RULE3(x)    (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AON_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_AON_MEM_RULE_RULE3_MASK)
+/*! @} */
+
+/*! @name WLAN_S0_SLAVE_RULE - 0x41000000-0x4137FFFF, 3.5MB */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_WLAN_S0_SLAVE_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_WLAN_S0_SLAVE_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - 0x41000000-0x4137FFFF, 3.5MB */
+#define AHB_SECURE_CTRL_WLAN_S0_SLAVE_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S0_SLAVE_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_WLAN_S0_SLAVE_RULE_RULE0_MASK)
+/*! @} */
+
+/*! @name WLAN_S1_MEM_RULE - 0x41380000-0x413FFFFF, part0..0x41380000-0x413FFFFF, part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_WLAN_S1_MEM_RULE */
+#define AHB_SECURE_CTRL_WLAN_S1_MEM_RULE_COUNT   (4U)
+
+/*! @name BLE_S0_SLAVE_RULE - 0x44000000-0x443BFFFF */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_BLE_S0_SLAVE_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_BLE_S0_SLAVE_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - 0x44000000-0x443BFFFF */
+#define AHB_SECURE_CTRL_BLE_S0_SLAVE_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S0_SLAVE_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_BLE_S0_SLAVE_RULE_RULE0_MASK)
+/*! @} */
+
+/*! @name BLE_S1_MEM_RULE - 0x443C0000-0x443FFFFF part0..0x443C0000-0x443FFFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_BLE_S1_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_BLE_S1_MEM_RULE */
+#define AHB_SECURE_CTRL_BLE_S1_MEM_RULE_COUNT    (4U)
+
+/*! @name SOC_TOP_MEM_RULE - 0x45000000-0x4500FFFF part0..0x45000000-0x4500FFFF part3 */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE0_MASK)
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE1_MASK)
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE2_MASK)
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE3_MASK)
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE4_MASK)
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE5_MASK)
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE6_MASK)
+
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - secure control rule0. it can be set when check_reg's write_lock is '0' */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_SOC_TOP_MEM_RULE */
+#define AHB_SECURE_CTRL_SOC_TOP_MEM_RULE_COUNT   (4U)
+
+/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
+/*! SEC_VIO_ADDR - security violation address for AHB layer */
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT       (20U)
+
+/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
+/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator, 0: read, 1: write */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
+/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator, 0: code, 1 */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
+/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
+/*! SEC_VIO_INFO_MASTER - security violation master number */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT  (20U)
+
+/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
+/*! VIO_INFO_VALID0 - violation information valid flag for AHB layer 0. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
+/*! VIO_INFO_VALID1 - violation information valid flag for AHB layer 1. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
+/*! VIO_INFO_VALID2 - violation information valid flag for AHB layer 2. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
+/*! VIO_INFO_VALID3 - violation information valid flag for AHB layer 3. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
+/*! VIO_INFO_VALID4 - violation information valid flag for AHB layer 4. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
+/*! VIO_INFO_VALID5 - violation information valid flag for AHB layer 5. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
+/*! VIO_INFO_VALID6 - violation information valid flag for AHB layer 6. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
+/*! VIO_INFO_VALID7 - violation information valid flag for AHB layer 7. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
+/*! VIO_INFO_VALID8 - violation information valid flag for AHB layer 8. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
+/*! VIO_INFO_VALID9 - violation information valid flag for AHB layer 9. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
+/*! VIO_INFO_VALID10 - violation information valid flag for AHB layer 10. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
+/*! VIO_INFO_VALID11 - violation information valid flag for AHB layer 11. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)
+/*! VIO_INFO_VALID12 - violation information valid flag for AHB layer 12. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U)
+/*! VIO_INFO_VALID13 - violation information valid flag for AHB layer 13. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U)
+/*! VIO_INFO_VALID14 - violation information valid flag for AHB layer 14. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U)
+/*! VIO_INFO_VALID15 - violation information valid flag for AHB layer 15. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U)
+/*! VIO_INFO_VALID16 - violation information valid flag for AHB layer 16. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U)
+/*! VIO_INFO_VALID17 - violation information valid flag for AHB layer 17. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U)
+/*! VIO_INFO_VALID18 - violation information valid flag for AHB layer 18. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK)
+
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_MASK (0x80000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_SHIFT (19U)
+/*! VIO_INFO_VALID19 - violation information valid flag for AHB layer 19. 0: not valid. 1: valid (violation occurred). Write 1 to clear. */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID19(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID19_MASK)
+/*! @} */
+
+/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world. */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
+/*! @} */
+
+/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
+/*! @} */
+
+/*! @name SEC_MASK_LOCK - sec_gp_reg write-lock bits */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG0_LOCK_MASK (0x3U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG0_LOCK_SHIFT (0U)
+/*! SEC_GP_REG0_LOCK - 2'b10: sec_reg_reg0 can be written. All other values: sec_reg_reg0 can't be written. */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG0_LOCK_MASK)
+
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG1_LOCK_MASK (0xCU)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG1_LOCK_SHIFT (2U)
+/*! SEC_GP_REG1_LOCK - 2'b10: sec_reg_reg1 can be written. All other values: sec_reg_reg1 can't be written. */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GP_REG1_LOCK_MASK)
+/*! @} */
+
+/*! @name MASTER_SEC_LEVEL - master secure level register */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK (0x30U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT (4U)
+/*! POWERQUAD - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_SHIFT (6U)
+/*! DMA0 - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_MASK (0x300U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_SHIFT (8U)
+/*! DMA1 - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ELS_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ELS_SHIFT (10U)
+/*! ELS - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ELS(x)  (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ELS_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ELS_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USB_MASK (0x3000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USB_SHIFT (12U)
+/*! USB - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USB(x)  (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USB_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USB_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PKC_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PKC_SHIFT (14U)
+/*! PKC - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PKC(x)  (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PKC_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PKC_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U)
+/*! SDIO - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ENET_MASK (0xC0000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ENET_SHIFT (18U)
+/*! ENET - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ENET_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ENET_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GDMA_MASK (0x300000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GDMA_SHIFT (20U)
+/*! GDMA - master secure level control. */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GDMA(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GDMA_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GDMA_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
+/*! MASTER_SEC_LEVEL_LOCK - master_sec_reg write-lock. When 2'b10, this register can be written.
+ *    With any other value, this register can't be written.
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
+/*! @} */
+
+/*! @name MASTER_SEC_LEVEL_ANTI_POL - master secure level anti-pole register */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_POWERQUAD_MASK (0x30U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_POWERQUAD_SHIFT (4U)
+/*! POWERQUAD - master secure level control anti-pole value (i.e It must be written with the
+ *    inverted value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_POWERQUAD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_POWERQUAD_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA0_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA0_SHIFT (6U)
+/*! DMA0 - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA0_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA1_MASK (0x300U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA1_SHIFT (8U)
+/*! DMA1 - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_DMA1_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ELS_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ELS_SHIFT (10U)
+/*! ELS - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ELS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ELS_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ELS_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_USB_MASK (0x3000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_USB_SHIFT (12U)
+/*! USB - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_USB(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_USB_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_USB_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_PKC_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_PKC_SHIFT (14U)
+/*! PKC - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_PKC_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_PKC_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_SDIO_MASK (0x30000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_SDIO_SHIFT (16U)
+/*! SDIO - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_SDIO_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ENET_MASK (0xC0000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ENET_SHIFT (18U)
+/*! ENET - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ENET_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_ENET_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_GDMA_MASK (0x300000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_GDMA_SHIFT (20U)
+/*! GDMA - master secure level control anti-pole value (i.e It must be written with the inverted
+ *    value of the corresponding field in master_sec_reg).
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_GDMA(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_GDMA_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_GDMA_MASK)
+
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
+/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - master_sec_antipol_reg register write-lock. When 2'b10, this
+ *    register can be written. With any other value, this register can't be written.
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_ANTI_POL_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
+/*! @} */
+
+/*! @name CM33_LOCK_REG - m33 lock control register */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
+/*! LOCK_NS_VTOR - 2'b10: m33 LOCKNSVTOR is 0. All other values: m33 LOCKNSVTOR is 1 */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK)
+
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
+/*! LOCK_NS_MPU - 2'b10:m33 LOCKNSMPU is 0. All other values: m33 LOCKNSMPU is 1 */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK)
+
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
+/*! LOCK_S_VTAIRCR - 2'b10:m33 LOCKSVTAURCR is 0. All other values: m33 LOCKSVTAURCR is 1 */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK)
+
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
+/*! LOCK_S_MPU - 2'b10:m33 LOCKSMPU is 0. All other values: m33 LOCKSMPU is 1 */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK)
+
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U)
+/*! LOCK_SAU - 2'b10:m33 LOCKSAU is 0. All other values: m33 LOCKSAU is 1 */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK)
+
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_M33_LOCK_REG_LOCK_MASK (0xC0000000U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_M33_LOCK_REG_LOCK_SHIFT (30U)
+/*! M33_LOCK_REG_LOCK - 2'b10: this register can be written. All other values: this register can't be written */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_M33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_M33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_M33_LOCK_REG_LOCK_MASK)
+/*! @} */
+
+/*! @name MISC_CTRL_DP_REG - secure control duplicate register */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
+/*! @} */
+
+/*! @name MISC_CTRL_REG - secure control register */
+/*! @{ */
+
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK)
+
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AHB_SECURE_CTRL_Register_Masks */
+
+
+/* AHB_SECURE_CTRL - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral AHB_SECURE_CTRL base address */
+  #define AHB_SECURE_CTRL_BASE                     (0x50148000u)
+  /** Peripheral AHB_SECURE_CTRL base address */
+  #define AHB_SECURE_CTRL_BASE_NS                  (0x40148000u)
+  /** Peripheral AHB_SECURE_CTRL base pointer */
+  #define AHB_SECURE_CTRL                          ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
+  /** Peripheral AHB_SECURE_CTRL base pointer */
+  #define AHB_SECURE_CTRL_NS                       ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
+  /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+  #define AHB_SECURE_CTRL_BASE_ADDRS               { AHB_SECURE_CTRL_BASE }
+  /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+  #define AHB_SECURE_CTRL_BASE_PTRS                { AHB_SECURE_CTRL }
+  /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+  #define AHB_SECURE_CTRL_BASE_ADDRS_NS            { AHB_SECURE_CTRL_BASE_NS }
+  /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+  #define AHB_SECURE_CTRL_BASE_PTRS_NS             { AHB_SECURE_CTRL_NS }
+#else
+  /** Peripheral AHB_SECURE_CTRL base address */
+  #define AHB_SECURE_CTRL_BASE                     (0x40148000u)
+  /** Peripheral AHB_SECURE_CTRL base pointer */
+  #define AHB_SECURE_CTRL                          ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
+  /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+  #define AHB_SECURE_CTRL_BASE_ADDRS               { AHB_SECURE_CTRL_BASE }
+  /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+  #define AHB_SECURE_CTRL_BASE_PTRS                { AHB_SECURE_CTRL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AON_SOC_CIU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AON_SOC_CIU_Peripheral_Access_Layer AON_SOC_CIU Peripheral Access Layer
+ * @{
+ */
+
+/** AON_SOC_CIU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PAD_CONFIG0;                       /**< ", offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t PAD_PWRDOWN_CTRL2;                 /**< Pad Power-down Control 2, offset: 0x10 */
+       uint8_t RESERVED_1[60];
+  __IO uint32_t SR_CONFIG1;                        /**< GPIO Slew Rate control, offset: 0x50 */
+       uint8_t RESERVED_2[32];
+  __IO uint32_t PAD_PU_PD_EN1;                     /**< Pad Pull-up Pull-down Enable2, offset: 0x74 */
+       uint8_t RESERVED_3[20];
+  __IO uint32_t PAD_SLP_EN0;                       /**< Pad Sleep Mode Enable, offset: 0x8C */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t PAD_SLP_VAL0;                      /**< Pad Sleep Mode Value, offset: 0x98 */
+       uint8_t RESERVED_5[112];
+  __IO uint32_t RST_SW;                            /**< Reset Controls for SOC_RESET_GEN, offset: 0x10C */
+       uint8_t RESERVED_6[32];
+  __I  uint32_t STRAP_FINISH_STATUS;               /**< SOC Strap Finish Status, offset: 0x130 */
+       uint8_t RESERVED_7[8];
+  __IO uint32_t SOC_OTP_CONTROL;                   /**< Power Switch (1.8v) Control for SOC OTP, offset: 0x13C */
+       uint8_t RESERVED_8[196];
+  __IO uint32_t PAD_AON_VREG_VSENSOR_CTRL;         /**< AON Vsensor and Vreg Pad Control, offset: 0x204 */
+       uint8_t RESERVED_9[632];
+  __I  uint32_t STRAP_RDBK;                        /**< Strap Readback, offset: 0x480 */
+  __IO uint32_t STRAP_SW;                          /**< Software Strap Override, offset: 0x484 */
+       uint8_t RESERVED_10[120];
+  __IO uint32_t PAD_SLP_PU_PD_DIS0;                /**< Pad Sleep Pullup and Pulldown Disable1, offset: 0x500 */
+       uint8_t RESERVED_11[52];
+  __IO uint32_t MCI_IOMUX_EN0;                     /**< mci_iomux_enable control for GPIO[27:22], offset: 0x538 */
+} AON_SOC_CIU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AON_SOC_CIU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AON_SOC_CIU_Register_Masks AON_SOC_CIU Register Masks
+ * @{
+ */
+
+/*! @name PAD_CONFIG0 - " */
+/*! @{ */
+
+#define AON_SOC_CIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_MASK (0x2U)
+#define AON_SOC_CIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_SHIFT (1U)
+/*! PAD_PWRDOWN_LATCH - Enables the pd_sel latching */
+#define AON_SOC_CIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_SHIFT)) & AON_SOC_CIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_MASK)
+
+#define AON_SOC_CIU_PAD_CONFIG0_XOSC_OD_EN_MASK  (0x20000U)
+#define AON_SOC_CIU_PAD_CONFIG0_XOSC_OD_EN_SHIFT (17U)
+/*! XOSC_OD_EN - Crystal Oscillator Enable Output Open-Drain Enable for GPIO[0] */
+#define AON_SOC_CIU_PAD_CONFIG0_XOSC_OD_EN(x)    (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_CONFIG0_XOSC_OD_EN_SHIFT)) & AON_SOC_CIU_PAD_CONFIG0_XOSC_OD_EN_MASK)
+
+#define AON_SOC_CIU_PAD_CONFIG0_XOSC_ENA_PAD_SEL_MASK (0x80000000U)
+#define AON_SOC_CIU_PAD_CONFIG0_XOSC_ENA_PAD_SEL_SHIFT (31U)
+/*! XOSC_ENA_PAD_SEL - xosc_ena_pads selection from CAU or mci_top */
+#define AON_SOC_CIU_PAD_CONFIG0_XOSC_ENA_PAD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_CONFIG0_XOSC_ENA_PAD_SEL_SHIFT)) & AON_SOC_CIU_PAD_CONFIG0_XOSC_ENA_PAD_SEL_MASK)
+/*! @} */
+
+/*! @name PAD_PWRDOWN_CTRL2 - Pad Power-down Control 2 */
+/*! @{ */
+
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO22_PD_SEL_MASK (0x7U)
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO22_PD_SEL_SHIFT (0U)
+/*! GPIO22_PD_SEL - Power Down Output Value for GPIO[22] Pad */
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO22_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO22_PD_SEL_SHIFT)) & AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO22_PD_SEL_MASK)
+
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO23_PD_SEL_MASK (0x70U)
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO23_PD_SEL_SHIFT (4U)
+/*! GPIO23_PD_SEL - Power Down Output Value for GPIO[23] Pad */
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO23_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO23_PD_SEL_SHIFT)) & AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO23_PD_SEL_MASK)
+
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO24_PD_SEL_MASK (0x700U)
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO24_PD_SEL_SHIFT (8U)
+/*! GPIO24_PD_SEL - Power Down Output Value for GPIO[24] Pad */
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO24_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO24_PD_SEL_SHIFT)) & AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO24_PD_SEL_MASK)
+
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO25_PD_SEL_MASK (0x7000U)
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO25_PD_SEL_SHIFT (12U)
+/*! GPIO25_PD_SEL - Power Down Output Value for GPIO[25] Pad */
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO25_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO25_PD_SEL_SHIFT)) & AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO25_PD_SEL_MASK)
+
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO26_PD_SEL_MASK (0x70000U)
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO26_PD_SEL_SHIFT (16U)
+/*! GPIO26_PD_SEL - Power Down Output Value for GPIO[26] Pad */
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO26_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO26_PD_SEL_SHIFT)) & AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO26_PD_SEL_MASK)
+
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO27_PD_SEL_MASK (0x700000U)
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO27_PD_SEL_SHIFT (20U)
+/*! GPIO27_PD_SEL - Power Down Output Value for GPIO[27] Pad */
+#define AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO27_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO27_PD_SEL_SHIFT)) & AON_SOC_CIU_PAD_PWRDOWN_CTRL2_GPIO27_PD_SEL_MASK)
+/*! @} */
+
+/*! @name SR_CONFIG1 - GPIO Slew Rate control */
+/*! @{ */
+
+#define AON_SOC_CIU_SR_CONFIG1_GPIO22_SR_MASK    (0x3000U)
+#define AON_SOC_CIU_SR_CONFIG1_GPIO22_SR_SHIFT   (12U)
+/*! GPIO22_SR - Slew Rate Control for GPIO[22] */
+#define AON_SOC_CIU_SR_CONFIG1_GPIO22_SR(x)      (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_SR_CONFIG1_GPIO22_SR_SHIFT)) & AON_SOC_CIU_SR_CONFIG1_GPIO22_SR_MASK)
+
+#define AON_SOC_CIU_SR_CONFIG1_GPIO23_SR_MASK    (0xC000U)
+#define AON_SOC_CIU_SR_CONFIG1_GPIO23_SR_SHIFT   (14U)
+/*! GPIO23_SR - Slew Rate Control for GPIO[23] */
+#define AON_SOC_CIU_SR_CONFIG1_GPIO23_SR(x)      (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_SR_CONFIG1_GPIO23_SR_SHIFT)) & AON_SOC_CIU_SR_CONFIG1_GPIO23_SR_MASK)
+
+#define AON_SOC_CIU_SR_CONFIG1_GPIO24_SR_MASK    (0x30000U)
+#define AON_SOC_CIU_SR_CONFIG1_GPIO24_SR_SHIFT   (16U)
+/*! GPIO24_SR - Slew Rate Control for GPIO[24] */
+#define AON_SOC_CIU_SR_CONFIG1_GPIO24_SR(x)      (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_SR_CONFIG1_GPIO24_SR_SHIFT)) & AON_SOC_CIU_SR_CONFIG1_GPIO24_SR_MASK)
+
+#define AON_SOC_CIU_SR_CONFIG1_GPIO25_SR_MASK    (0xC0000U)
+#define AON_SOC_CIU_SR_CONFIG1_GPIO25_SR_SHIFT   (18U)
+/*! GPIO25_SR - Slew Rate Control for GPIO[25] */
+#define AON_SOC_CIU_SR_CONFIG1_GPIO25_SR(x)      (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_SR_CONFIG1_GPIO25_SR_SHIFT)) & AON_SOC_CIU_SR_CONFIG1_GPIO25_SR_MASK)
+
+#define AON_SOC_CIU_SR_CONFIG1_GPIO26_SR_MASK    (0x300000U)
+#define AON_SOC_CIU_SR_CONFIG1_GPIO26_SR_SHIFT   (20U)
+/*! GPIO26_SR - Slew Rate Control for GPIO[26] */
+#define AON_SOC_CIU_SR_CONFIG1_GPIO26_SR(x)      (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_SR_CONFIG1_GPIO26_SR_SHIFT)) & AON_SOC_CIU_SR_CONFIG1_GPIO26_SR_MASK)
+
+#define AON_SOC_CIU_SR_CONFIG1_GPIO27_SR_MASK    (0xC00000U)
+#define AON_SOC_CIU_SR_CONFIG1_GPIO27_SR_SHIFT   (22U)
+/*! GPIO27_SR - Slew Rate Control for GPIO[27] */
+#define AON_SOC_CIU_SR_CONFIG1_GPIO27_SR(x)      (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_SR_CONFIG1_GPIO27_SR_SHIFT)) & AON_SOC_CIU_SR_CONFIG1_GPIO27_SR_MASK)
+/*! @} */
+
+/*! @name PAD_PU_PD_EN1 - Pad Pull-up Pull-down Enable2 */
+/*! @{ */
+
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO22_PU_PD_EN_MASK (0x3000U)
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO22_PU_PD_EN_SHIFT (12U)
+/*! GPIO22_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[22] */
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO22_PU_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PU_PD_EN1_GPIO22_PU_PD_EN_SHIFT)) & AON_SOC_CIU_PAD_PU_PD_EN1_GPIO22_PU_PD_EN_MASK)
+
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO23_PU_PD_EN_MASK (0xC000U)
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO23_PU_PD_EN_SHIFT (14U)
+/*! GPIO23_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[23] */
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO23_PU_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PU_PD_EN1_GPIO23_PU_PD_EN_SHIFT)) & AON_SOC_CIU_PAD_PU_PD_EN1_GPIO23_PU_PD_EN_MASK)
+
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO24_PU_PD_EN_MASK (0x30000U)
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO24_PU_PD_EN_SHIFT (16U)
+/*! GPIO24_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[24] */
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO24_PU_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PU_PD_EN1_GPIO24_PU_PD_EN_SHIFT)) & AON_SOC_CIU_PAD_PU_PD_EN1_GPIO24_PU_PD_EN_MASK)
+
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO25_PU_PD_EN_MASK (0xC0000U)
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO25_PU_PD_EN_SHIFT (18U)
+/*! GPIO25_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[25] */
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO25_PU_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PU_PD_EN1_GPIO25_PU_PD_EN_SHIFT)) & AON_SOC_CIU_PAD_PU_PD_EN1_GPIO25_PU_PD_EN_MASK)
+
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO26_PU_PD_EN_MASK (0x300000U)
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO26_PU_PD_EN_SHIFT (20U)
+/*! GPIO26_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[26] */
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO26_PU_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PU_PD_EN1_GPIO26_PU_PD_EN_SHIFT)) & AON_SOC_CIU_PAD_PU_PD_EN1_GPIO26_PU_PD_EN_MASK)
+
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO27_PU_PD_EN_MASK (0xC00000U)
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO27_PU_PD_EN_SHIFT (22U)
+/*! GPIO27_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[27] */
+#define AON_SOC_CIU_PAD_PU_PD_EN1_GPIO27_PU_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_PU_PD_EN1_GPIO27_PU_PD_EN_SHIFT)) & AON_SOC_CIU_PAD_PU_PD_EN1_GPIO27_PU_PD_EN_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_EN0 - Pad Sleep Mode Enable */
+/*! @{ */
+
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO22_SLP_EN_MASK (0x400000U)
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO22_SLP_EN_SHIFT (22U)
+/*! GPIO22_SLP_EN - Enable Forcing GPIO[22] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO22_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_EN0_GPIO22_SLP_EN_SHIFT)) & AON_SOC_CIU_PAD_SLP_EN0_GPIO22_SLP_EN_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO23_SLP_EN_MASK (0x800000U)
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO23_SLP_EN_SHIFT (23U)
+/*! GPIO23_SLP_EN - Enable Forcing GPIO[23] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO23_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_EN0_GPIO23_SLP_EN_SHIFT)) & AON_SOC_CIU_PAD_SLP_EN0_GPIO23_SLP_EN_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO24_SLP_EN_MASK (0x1000000U)
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO24_SLP_EN_SHIFT (24U)
+/*! GPIO24_SLP_EN - Enable Forcing GPIO[24] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO24_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_EN0_GPIO24_SLP_EN_SHIFT)) & AON_SOC_CIU_PAD_SLP_EN0_GPIO24_SLP_EN_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO25_SLP_EN_MASK (0x2000000U)
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO25_SLP_EN_SHIFT (25U)
+/*! GPIO25_SLP_EN - Enable Forcing GPIO[25] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO25_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_EN0_GPIO25_SLP_EN_SHIFT)) & AON_SOC_CIU_PAD_SLP_EN0_GPIO25_SLP_EN_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO26_SLP_EN_MASK (0x4000000U)
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO26_SLP_EN_SHIFT (26U)
+/*! GPIO26_SLP_EN - Enable Forcing GPIO[26] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO26_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_EN0_GPIO26_SLP_EN_SHIFT)) & AON_SOC_CIU_PAD_SLP_EN0_GPIO26_SLP_EN_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO27_SLP_EN_MASK (0x8000000U)
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO27_SLP_EN_SHIFT (27U)
+/*! GPIO27_SLP_EN - Enable Forcing GPIO[27] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_EN0_GPIO27_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_EN0_GPIO27_SLP_EN_SHIFT)) & AON_SOC_CIU_PAD_SLP_EN0_GPIO27_SLP_EN_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_VAL0 - Pad Sleep Mode Value */
+/*! @{ */
+
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO22_SLP_VAL_MASK (0x400000U)
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO22_SLP_VAL_SHIFT (22U)
+/*! GPIO22_SLP_VAL - Force GPIO[22] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO22_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_VAL0_GPIO22_SLP_VAL_SHIFT)) & AON_SOC_CIU_PAD_SLP_VAL0_GPIO22_SLP_VAL_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO23_SLP_VAL_MASK (0x800000U)
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO23_SLP_VAL_SHIFT (23U)
+/*! GPIO23_SLP_VAL - Force GPIO[23] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO23_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_VAL0_GPIO23_SLP_VAL_SHIFT)) & AON_SOC_CIU_PAD_SLP_VAL0_GPIO23_SLP_VAL_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO24_SLP_VAL_MASK (0x1000000U)
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO24_SLP_VAL_SHIFT (24U)
+/*! GPIO24_SLP_VAL - Force GPIO[24] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO24_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_VAL0_GPIO24_SLP_VAL_SHIFT)) & AON_SOC_CIU_PAD_SLP_VAL0_GPIO24_SLP_VAL_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO25_SLP_VAL_MASK (0x2000000U)
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO25_SLP_VAL_SHIFT (25U)
+/*! GPIO25_SLP_VAL - Force GPIO[25] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO25_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_VAL0_GPIO25_SLP_VAL_SHIFT)) & AON_SOC_CIU_PAD_SLP_VAL0_GPIO25_SLP_VAL_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO26_SLP_VAL_MASK (0x4000000U)
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO26_SLP_VAL_SHIFT (26U)
+/*! GPIO26_SLP_VAL - Force GPIO[26] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO26_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_VAL0_GPIO26_SLP_VAL_SHIFT)) & AON_SOC_CIU_PAD_SLP_VAL0_GPIO26_SLP_VAL_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO27_SLP_VAL_MASK (0x8000000U)
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO27_SLP_VAL_SHIFT (27U)
+/*! GPIO27_SLP_VAL - Force GPIO[27] Output During Sleep */
+#define AON_SOC_CIU_PAD_SLP_VAL0_GPIO27_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_VAL0_GPIO27_SLP_VAL_SHIFT)) & AON_SOC_CIU_PAD_SLP_VAL0_GPIO27_SLP_VAL_MASK)
+/*! @} */
+
+/*! @name RST_SW - Reset Controls for SOC_RESET_GEN */
+/*! @{ */
+
+#define AON_SOC_CIU_RST_SW_BUCK_REG_RST_MASK     (0x200U)
+#define AON_SOC_CIU_RST_SW_BUCK_REG_RST_SHIFT    (9U)
+/*! BUCK_REG_RST - config reg SW reset for BUCK18 and BUCK11, active high */
+#define AON_SOC_CIU_RST_SW_BUCK_REG_RST(x)       (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_RST_SW_BUCK_REG_RST_SHIFT)) & AON_SOC_CIU_RST_SW_BUCK_REG_RST_MASK)
+
+#define AON_SOC_CIU_RST_SW_SOCAON_ITRC_CHIP_RSTB_EN_MASK (0x1000000U)
+#define AON_SOC_CIU_RST_SW_SOCAON_ITRC_CHIP_RSTB_EN_SHIFT (24U)
+/*! SOCAON_ITRC_CHIP_RSTB_EN - Default the itrc chip reset can reset SOCAON (jtag), SW can disable this if not required */
+#define AON_SOC_CIU_RST_SW_SOCAON_ITRC_CHIP_RSTB_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_RST_SW_SOCAON_ITRC_CHIP_RSTB_EN_SHIFT)) & AON_SOC_CIU_RST_SW_SOCAON_ITRC_CHIP_RSTB_EN_MASK)
+
+#define AON_SOC_CIU_RST_SW_AON_SOCCIU_RSTB_MASK  (0x2000000U)
+#define AON_SOC_CIU_RST_SW_AON_SOCCIU_RSTB_SHIFT (25U)
+/*! AON_SOCCIU_RSTB - reset for the aon socciu registers. It gets auto clear */
+#define AON_SOC_CIU_RST_SW_AON_SOCCIU_RSTB(x)    (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_RST_SW_AON_SOCCIU_RSTB_SHIFT)) & AON_SOC_CIU_RST_SW_AON_SOCCIU_RSTB_MASK)
+/*! @} */
+
+/*! @name STRAP_FINISH_STATUS - SOC Strap Finish Status */
+/*! @{ */
+
+#define AON_SOC_CIU_STRAP_FINISH_STATUS_STRAP_FINISH_MASK (0x1U)
+#define AON_SOC_CIU_STRAP_FINISH_STATUS_STRAP_FINISH_SHIFT (0U)
+/*! STRAP_FINISH - Strap Finish status from strap logic. */
+#define AON_SOC_CIU_STRAP_FINISH_STATUS_STRAP_FINISH(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_FINISH_STATUS_STRAP_FINISH_SHIFT)) & AON_SOC_CIU_STRAP_FINISH_STATUS_STRAP_FINISH_MASK)
+/*! @} */
+
+/*! @name SOC_OTP_CONTROL - Power Switch (1.8v) Control for SOC OTP */
+/*! @{ */
+
+#define AON_SOC_CIU_SOC_OTP_CONTROL_SOC_OTP_PSW18_PD_MASK (0x1U)
+#define AON_SOC_CIU_SOC_OTP_CONTROL_SOC_OTP_PSW18_PD_SHIFT (0U)
+/*! SOC_OTP_PSW18_PD - Power-Down control for the 1.8V Power-Switch for OTPs on SOC side */
+#define AON_SOC_CIU_SOC_OTP_CONTROL_SOC_OTP_PSW18_PD(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_SOC_OTP_CONTROL_SOC_OTP_PSW18_PD_SHIFT)) & AON_SOC_CIU_SOC_OTP_CONTROL_SOC_OTP_PSW18_PD_MASK)
+/*! @} */
+
+/*! @name PAD_AON_VREG_VSENSOR_CTRL - AON Vsensor and Vreg Pad Control */
+/*! @{ */
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_ENB_MASK (0x1U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_ENB_SHIFT (0U)
+/*! VIO_REG_ENB - VIO_AON Pad Regulator */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_ENB(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_ENB_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_ENB_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_MASK (0x2U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_SHIFT (1U)
+/*! VIO_REG_CTRL_EN - VIO reg control enable function */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK (0x10U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT (4U)
+/*! VSENSOR_BYPASS - Active High Enable Signal for Bypass Mode */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK (0x20U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT (5U)
+/*! VSENSOR_V18EN_12_IN - Bypass Value when Vsensor_Bypass Bit Set */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK (0x40U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT (6U)
+/*! VSENSOR_DISABLE_12 - Vsensor AON disable */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK (0x80U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT (7U)
+/*! VSENSOR_CLK_12 - Vsensor AON Clock */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_CLK_12(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK (0x100U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT (8U)
+/*! VSENSOR_TE - Vsensor AON Test Enable */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TE(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK (0xE00U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT (9U)
+/*! VSENSOR_TEST - Vsensor AON Test Point Mux Selection */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TEST(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK (0x1000U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT (12U)
+/*! VSENSOR_VTHRESH - Vsensor AON Detection Threshold */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_V25EN_CORE_MASK (0x2000U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT (13U)
+/*! V25EN_CORE - V25EN_CORE */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_V25EN_CORE(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_V25EN_CORE_MASK)
+
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DETECT_MASK (0x4000U)
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DETECT_SHIFT (14U)
+/*! VSENSOR_DETECT - VIO_AON_Vsensor_Detect_V18 Status */
+#define AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DETECT_SHIFT)) & AON_SOC_CIU_PAD_AON_VREG_VSENSOR_CTRL_VSENSOR_DETECT_MASK)
+/*! @} */
+
+/*! @name STRAP_RDBK - Strap Readback */
+/*! @{ */
+
+#define AON_SOC_CIU_STRAP_RDBK_MODE_MASK         (0xFU)
+#define AON_SOC_CIU_STRAP_RDBK_MODE_SHIFT        (0U)
+/*! MODE - Boot Options: */
+#define AON_SOC_CIU_STRAP_RDBK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_MODE_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_MODE_MASK)
+
+#define AON_SOC_CIU_STRAP_RDBK_REF_CLK_DETECT_MASK (0x10U)
+#define AON_SOC_CIU_STRAP_RDBK_REF_CLK_DETECT_SHIFT (4U)
+/*! REF_CLK_DETECT - ref_clk_detect (reserved) */
+#define AON_SOC_CIU_STRAP_RDBK_REF_CLK_DETECT(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_REF_CLK_DETECT_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_REF_CLK_DETECT_MASK)
+
+#define AON_SOC_CIU_STRAP_RDBK_XOSC_SEL_MASK     (0x60U)
+#define AON_SOC_CIU_STRAP_RDBK_XOSC_SEL_SHIFT    (5U)
+/*! XOSC_SEL - Crystal Osc Enable */
+#define AON_SOC_CIU_STRAP_RDBK_XOSC_SEL(x)       (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_XOSC_SEL_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_XOSC_SEL_MASK)
+
+#define AON_SOC_CIU_STRAP_RDBK_VTOR_SEL_MASK     (0x80U)
+#define AON_SOC_CIU_STRAP_RDBK_VTOR_SEL_SHIFT    (7U)
+/*! VTOR_SEL - Strap bit to select secure VTOR base addr of CM33 */
+#define AON_SOC_CIU_STRAP_RDBK_VTOR_SEL(x)       (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_VTOR_SEL_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_VTOR_SEL_MASK)
+
+#define AON_SOC_CIU_STRAP_RDBK_DIS_KEY_ROT_DBG_MASK (0x100U)
+#define AON_SOC_CIU_STRAP_RDBK_DIS_KEY_ROT_DBG_SHIFT (8U)
+/*! DIS_KEY_ROT_DBG - dis_key_rot_dbg */
+#define AON_SOC_CIU_STRAP_RDBK_DIS_KEY_ROT_DBG(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_DIS_KEY_ROT_DBG_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_DIS_KEY_ROT_DBG_MASK)
+
+#define AON_SOC_CIU_STRAP_RDBK_DAP_USE_JTAG_MASK (0x800U)
+#define AON_SOC_CIU_STRAP_RDBK_DAP_USE_JTAG_SHIFT (11U)
+/*! DAP_USE_JTAG - 1 (Default): DAP uses JTAG */
+#define AON_SOC_CIU_STRAP_RDBK_DAP_USE_JTAG(x)   (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_DAP_USE_JTAG_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_DAP_USE_JTAG_MASK)
+
+#define AON_SOC_CIU_STRAP_RDBK_QFN_BOND_MASK     (0x4000U)
+#define AON_SOC_CIU_STRAP_RDBK_QFN_BOND_SHIFT    (14U)
+/*! QFN_BOND - Bond Strap Value */
+#define AON_SOC_CIU_STRAP_RDBK_QFN_BOND(x)       (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_QFN_BOND_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_QFN_BOND_MASK)
+
+#define AON_SOC_CIU_STRAP_RDBK_REF_CLK_RATE_MASK (0xF00000U)
+#define AON_SOC_CIU_STRAP_RDBK_REF_CLK_RATE_SHIFT (20U)
+/*! REF_CLK_RATE - CAU Reference Clock Rate */
+#define AON_SOC_CIU_STRAP_RDBK_REF_CLK_RATE(x)   (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_RDBK_REF_CLK_RATE_SHIFT)) & AON_SOC_CIU_STRAP_RDBK_REF_CLK_RATE_MASK)
+/*! @} */
+
+/*! @name STRAP_SW - Software Strap Override */
+/*! @{ */
+
+#define AON_SOC_CIU_STRAP_SW_MODE_MASK           (0xFU)
+#define AON_SOC_CIU_STRAP_SW_MODE_SHIFT          (0U)
+/*! MODE - Below are the modes selected based on the value of this field: */
+#define AON_SOC_CIU_STRAP_SW_MODE(x)             (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_SW_MODE_SHIFT)) & AON_SOC_CIU_STRAP_SW_MODE_MASK)
+
+#define AON_SOC_CIU_STRAP_SW_XOSC_SEL_MASK       (0x60U)
+#define AON_SOC_CIU_STRAP_SW_XOSC_SEL_SHIFT      (5U)
+/*! XOSC_SEL - Crystal Osc Enable */
+#define AON_SOC_CIU_STRAP_SW_XOSC_SEL(x)         (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_SW_XOSC_SEL_SHIFT)) & AON_SOC_CIU_STRAP_SW_XOSC_SEL_MASK)
+
+#define AON_SOC_CIU_STRAP_SW_QFN_BOND_MASK       (0x4000U)
+#define AON_SOC_CIU_STRAP_SW_QFN_BOND_SHIFT      (14U)
+/*! QFN_BOND - Bond Type */
+#define AON_SOC_CIU_STRAP_SW_QFN_BOND(x)         (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_SW_QFN_BOND_SHIFT)) & AON_SOC_CIU_STRAP_SW_QFN_BOND_MASK)
+
+#define AON_SOC_CIU_STRAP_SW_REF_CLK_RATE_MASK   (0xF00000U)
+#define AON_SOC_CIU_STRAP_SW_REF_CLK_RATE_SHIFT  (20U)
+/*! REF_CLK_RATE - CAU Reference Clock Rate */
+#define AON_SOC_CIU_STRAP_SW_REF_CLK_RATE(x)     (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_SW_REF_CLK_RATE_SHIFT)) & AON_SOC_CIU_STRAP_SW_REF_CLK_RATE_MASK)
+
+#define AON_SOC_CIU_STRAP_SW_ENABLE_MASK         (0x80000000U)
+#define AON_SOC_CIU_STRAP_SW_ENABLE_SHIFT        (31U)
+/*! ENABLE - Software Strap Mode Enable */
+#define AON_SOC_CIU_STRAP_SW_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_STRAP_SW_ENABLE_SHIFT)) & AON_SOC_CIU_STRAP_SW_ENABLE_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_PU_PD_DIS0 - Pad Sleep Pullup and Pulldown Disable1 */
+/*! @{ */
+
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO22_PU_PD_DIS_MASK (0x400000U)
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO22_PU_PD_DIS_SHIFT (22U)
+/*! GPIO22_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[22] During Sleep Mode */
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO22_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO22_PU_PD_DIS_SHIFT)) & AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO22_PU_PD_DIS_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO23_PU_PD_DIS_MASK (0x800000U)
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO23_PU_PD_DIS_SHIFT (23U)
+/*! GPIO23_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[23] During Sleep Mode */
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO23_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO23_PU_PD_DIS_SHIFT)) & AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO23_PU_PD_DIS_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO24_PU_PD_DIS_MASK (0x1000000U)
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO24_PU_PD_DIS_SHIFT (24U)
+/*! GPIO24_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[24] During Sleep Mode */
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO24_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO24_PU_PD_DIS_SHIFT)) & AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO24_PU_PD_DIS_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO25_PU_PD_DIS_MASK (0x2000000U)
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO25_PU_PD_DIS_SHIFT (25U)
+/*! GPIO25_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[25] During Sleep Mode */
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO25_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO25_PU_PD_DIS_SHIFT)) & AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO25_PU_PD_DIS_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO26_PU_PD_DIS_MASK (0x4000000U)
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO26_PU_PD_DIS_SHIFT (26U)
+/*! GPIO26_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[26] During Sleep Mode */
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO26_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO26_PU_PD_DIS_SHIFT)) & AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO26_PU_PD_DIS_MASK)
+
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO27_PU_PD_DIS_MASK (0x8000000U)
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO27_PU_PD_DIS_SHIFT (27U)
+/*! GPIO27_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[27] During Sleep Mode */
+#define AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO27_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO27_PU_PD_DIS_SHIFT)) & AON_SOC_CIU_PAD_SLP_PU_PD_DIS0_GPIO27_PU_PD_DIS_MASK)
+/*! @} */
+
+/*! @name MCI_IOMUX_EN0 - mci_iomux_enable control for GPIO[27:22] */
+/*! @{ */
+
+#define AON_SOC_CIU_MCI_IOMUX_EN0_EN_27_22_MASK  (0xFC00000U)
+#define AON_SOC_CIU_MCI_IOMUX_EN0_EN_27_22_SHIFT (22U)
+/*! EN_27_22 - Bitwise enable control for mci_io_mux GPIO[27:22] */
+#define AON_SOC_CIU_MCI_IOMUX_EN0_EN_27_22(x)    (((uint32_t)(((uint32_t)(x)) << AON_SOC_CIU_MCI_IOMUX_EN0_EN_27_22_SHIFT)) & AON_SOC_CIU_MCI_IOMUX_EN0_EN_27_22_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AON_SOC_CIU_Register_Masks */
+
+
+/* AON_SOC_CIU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral AON_SOC_CIU base address */
+  #define AON_SOC_CIU_BASE                         (0x55000800u)
+  /** Peripheral AON_SOC_CIU base address */
+  #define AON_SOC_CIU_BASE_NS                      (0x45000800u)
+  /** Peripheral AON_SOC_CIU base pointer */
+  #define AON_SOC_CIU                              ((AON_SOC_CIU_Type *)AON_SOC_CIU_BASE)
+  /** Peripheral AON_SOC_CIU base pointer */
+  #define AON_SOC_CIU_NS                           ((AON_SOC_CIU_Type *)AON_SOC_CIU_BASE_NS)
+  /** Array initializer of AON_SOC_CIU peripheral base addresses */
+  #define AON_SOC_CIU_BASE_ADDRS                   { AON_SOC_CIU_BASE }
+  /** Array initializer of AON_SOC_CIU peripheral base pointers */
+  #define AON_SOC_CIU_BASE_PTRS                    { AON_SOC_CIU }
+  /** Array initializer of AON_SOC_CIU peripheral base addresses */
+  #define AON_SOC_CIU_BASE_ADDRS_NS                { AON_SOC_CIU_BASE_NS }
+  /** Array initializer of AON_SOC_CIU peripheral base pointers */
+  #define AON_SOC_CIU_BASE_PTRS_NS                 { AON_SOC_CIU_NS }
+#else
+  /** Peripheral AON_SOC_CIU base address */
+  #define AON_SOC_CIU_BASE                         (0x45000800u)
+  /** Peripheral AON_SOC_CIU base pointer */
+  #define AON_SOC_CIU                              ((AON_SOC_CIU_Type *)AON_SOC_CIU_BASE)
+  /** Array initializer of AON_SOC_CIU peripheral base addresses */
+  #define AON_SOC_CIU_BASE_ADDRS                   { AON_SOC_CIU_BASE }
+  /** Array initializer of AON_SOC_CIU peripheral base pointers */
+  #define AON_SOC_CIU_BASE_PTRS                    { AON_SOC_CIU }
+#endif
+
+/*!
+ * @}
+ */ /* end of group AON_SOC_CIU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- APU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup APU_Peripheral_Access_Layer APU Peripheral Access Layer
+ * @{
+ */
+
+/** APU - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t APU_IP_REVISION;                   /**< APU IP revision, offset: 0x0 */
+  __IO uint32_t CTRL;                              /**< Control, offset: 0x4 */
+  __IO uint32_t TIMER_PWR_MODE;                    /**< Timer Power Mode, offset: 0x8 */
+  __IO uint32_t PWR_CTRL;                          /**< Power Control, offset: 0xC */
+  __IO uint32_t PLL_CTRL;                          /**< PLL Control, offset: 0x10 */
+  __IO uint32_t PLL_DIS_CNT;                       /**< PLL Disable Count, offset: 0x14 */
+  __IO uint32_t STABLE_CNT;                        /**< Stable Count, offset: 0x18 */
+  __IO uint32_t CPU1_HOST_WKUP_MASK;               /**< CPU1 Host Wakeup Mask, offset: 0x1C */
+  __IO uint32_t CPU1_HOST_WKUP_POL;                /**< CPU1 Host Wakeup Polarity, offset: 0x20 */
+  __I  uint32_t CAL_WIN_CNT;                       /**< Calibration Window Count, offset: 0x24 */
+  __I  uint32_t AUTO_10US;                         /**< Auto 10us, offset: 0x28 */
+  __I  uint32_t ACC_CNT;                           /**< Accumulation Count, offset: 0x2C */
+  __IO uint32_t CAL_WIN_SIZE;                      /**< Calibration Window Size, offset: 0x30 */
+  __I  uint32_t SLP_CLK_TIMER;                     /**< Sleep Clock Timer, offset: 0x34 */
+  __I  uint32_t STATUS_RD;                         /**< Status Read, offset: 0x38 */
+  __IO uint32_t STABLE_CNT2;                       /**< Stable Count 2, offset: 0x3C */
+  __IO uint32_t DYN_PLL_MASK;                      /**< Dynamic PLL Mask, offset: 0x40 */
+  __I  uint32_t TESTBUS_RD1;                       /**< Testbus Read 1, offset: 0x44 */
+  __I  uint32_t TESTBUS_RD2;                       /**< Testbus Read 2, offset: 0x48 */
+  __IO uint32_t GENERIC_TIMER_CNT;                 /**< Generic Timer Count, offset: 0x4C */
+  __IO uint32_t CPU1_HOST_WKUP_CTRL;               /**< CPU1 Host Wakeup Control, offset: 0x50 */
+  __IO uint32_t DYN_PLL_CLK_EXT_CTRL;              /**< Dynamic PLL Clock Ext Control, offset: 0x54 */
+  __IO uint32_t GENERIC_SLP_START_VAL;             /**< Generic Sleep Start Value, offset: 0x58 */
+  __IO uint32_t DLY_HOST_CTRL;                     /**< Delay Host Control, offset: 0x5C */
+  __I  uint32_t HOST_WKUP_CNT;                     /**< Host Wakeup Count, offset: 0x60 */
+  __IO uint32_t CPU2_HOST_WKUP_MASK;               /**< CPU2 Host Wakeup Mask, offset: 0x64 */
+  __IO uint32_t CPU2_HOST_WKUP_POL;                /**< CPU2 Host Wakeup Polarity, offset: 0x68 */
+  __IO uint32_t CPU2_HOST_WKUP_CTRL;               /**< CPU2 Host Wakeup Control, offset: 0x6C */
+  __IO uint32_t CPU2_CTRL;                         /**< CPU2 Control, offset: 0x70 */
+  __IO uint32_t WLAN_PWR_CTRL_DLY;                 /**< Wlan domain FSM Power Control Delay, offset: 0x74 */
+  __I  uint32_t STATUS2;                           /**< Status 2, offset: 0x78 */
+  __IO uint32_t WLAN_PWR_CTRL_DLY2;                /**< Wlan domain FSM Power Control Delay 2, offset: 0x7C */
+  __IO uint32_t WL_CTRL;                           /**< WLAN Control, offset: 0x80 */
+  __IO uint32_t WL_WKUP_MASK;                      /**< WLAN Wakeup Mask, offset: 0x84 */
+  __I  uint32_t WL_STATUS;                         /**< WLAN Status, offset: 0x88 */
+  __I  uint32_t WL_ALARM_RD;                       /**< WLAN Alarm Readback, offset: 0x8C */
+  __IO uint32_t WL_BCN_XP_ALARM;                   /**< WLAN Beacon Alarm, offset: 0x90 */
+  __IO uint32_t WL_BCN_INTR_ALARM;                 /**< WLAN Beacon Interrupt Alarm, offset: 0x94 */
+  __IO uint32_t WL_HOST_INTR_ALARM;                /**< WLAN Host Interrupt Alarm, offset: 0x98 */
+  __IO uint32_t WL_BCN_PLL_ALARM;                  /**< WLAN Beacon PLL Alarm, offset: 0x9C */
+  __IO uint32_t TSF_REF_FACTOR;                    /**< TSF Reference Factor, offset: 0xA0 */
+  __IO uint32_t TSF_SLEEP_FACTOR;                  /**< TSF Sleep Factor, offset: 0xA4 */
+  __IO uint32_t BBUD_UDR_ISO_CNT;                  /**< BBUD UDR ISO Count, offset: 0xA8 */
+  __IO uint32_t WL_DVFS_CTRL;                      /**< WLAN DVFS Control, offset: 0xAC */
+  __IO uint32_t WL_CTRL2;                          /**< WLAN Control 2, offset: 0xB0 */
+  __IO uint32_t WL_WKUP_MASK2;                     /**< WLAN Wakeup Mask 2, offset: 0xB4 */
+  __I  uint32_t WL_STATUS2;                        /**< WLAN Status 2, offset: 0xB8 */
+  __I  uint32_t WL_ALARM_RD2;                      /**< WLAN Alarm Readback 2, offset: 0xBC */
+  __IO uint32_t WL_BCN_XP_ALARM2;                  /**< WLAN Beacon XP Alarm 2, offset: 0xC0 */
+  __IO uint32_t WL_BCN_INTR_ALARM2;                /**< WLAN Beacon Interrupt Alarm 2, offset: 0xC4 */
+  __IO uint32_t WL_HOST_INTR_ALARM2;               /**< WLAN Host Interrupt Alarm 2, offset: 0xC8 */
+  __IO uint32_t WL_BCN_PLL_ALARM2;                 /**< WLAN Beacon PLL Alarm 2, offset: 0xCC */
+  __IO uint32_t WLCOMN_PWR_CTRL;                   /**< WLAN Comm Powerup Control, offset: 0xD0 */
+  __I  uint32_t WLCOMN_STATUS;                     /**< WLAN Comm Status, offset: 0xD4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t BT_CTRL;                           /**< Bluetooth Control, offset: 0xE0 */
+  __IO uint32_t BT_WKUP_MASK;                      /**< Bluetooth Wakeup Mask, offset: 0xE4 */
+  __I  uint32_t BT_STATUS;                         /**< Bluetooth Status, offset: 0xE8 */
+  __IO uint32_t BT_CKEN_CTRL;                      /**< Bluetooth Clock Enable Control, offset: 0xEC */
+  __IO uint32_t BT_RESRC_CTRL;                     /**< Bluetooth RESRC Control, offset: 0xF0 */
+  __IO uint32_t BT_DVFS_CTRL;                      /**< Bluetooth DVFS Control, offset: 0xF4 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t FM_CTRL;                           /**< FM Control, offset: 0x100 */
+  __IO uint32_t FM_WKUP_MASK;                      /**< FM Wakeup Mask, offset: 0x104 */
+  __I  uint32_t FM_STATUS;                         /**< FM Status, offset: 0x108 */
+  __IO uint32_t FM_CKEN_CTRL;                      /**< FM Clock Enable Control, offset: 0x10C */
+  __IO uint32_t FM_RESRC_CTRL;                     /**< FM RESRC Control, offset: 0x110 */
+  __IO uint32_t FM_DVFS_CTRL;                      /**< FM DVFS Control, offset: 0x114 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t USB_PWR_CTRL_DLY;                  /**< USB FSM Power Control Delay, offset: 0x120 */
+  __IO uint32_t USB_PWR_CTRL_DLY2;                 /**< USB FSM Power Control Delay 2, offset: 0x124 */
+  __IO uint32_t WLCOMN_PWR_CTRL_DLY;               /**< Wlan common domain FSM Power Control Delay, offset: 0x128 */
+  __IO uint32_t WLCOMN_PWR_CTRL_DLY2;              /**< Wlan common domain FSM Power Control Delay 2, offset: 0x12C */
+       uint8_t RESERVED_3[16];
+  __IO uint32_t BLE_CTRL;                          /**< BLE Control, offset: 0x140 */
+  __IO uint32_t BLE_WKUP_MASK;                     /**< BLE Wakeup Mask, offset: 0x144 */
+  __I  uint32_t BLE_STATUS;                        /**< BLE Status, offset: 0x148 */
+       uint8_t RESERVED_4[20];
+  __IO uint32_t NFC_CTRL;                          /**< NFC Control, offset: 0x160 */
+  __IO uint32_t NFC_WKUP_MASK;                     /**< NFC Wakeup Mask, offset: 0x164 */
+  __I  uint32_t NFC_STATUS;                        /**< NFC Status, offset: 0x168 */
+  __IO uint32_t NFC_CKEN_CTRL;                     /**< NFC Clock Enable Control, offset: 0x16C */
+  __IO uint32_t NFC_RESRC_CTRL;                    /**< NFC RESRC Control, offset: 0x170 */
+  __IO uint32_t NFC_DVFS_CTRL;                     /**< NFC DVFS Control, offset: 0x174 */
+       uint8_t RESERVED_5[8];
+  __IO uint32_t FP4_CTRL;                          /**< FP4(15.4) Control, offset: 0x180 */
+  __IO uint32_t FP4_WKUP_MASK;                     /**< FP4 Wakeup Mask, offset: 0x184 */
+  __I  uint32_t FP4_STATUS;                        /**< FP4 Status, offset: 0x188 */
+  __IO uint32_t FP4_CKEN_CTRL;                     /**< FP4 Clock Enable Control, offset: 0x18C */
+  __IO uint32_t FP4_RESRC_CTRL;                    /**< FP4 RESRC Control, offset: 0x190 */
+  __IO uint32_t FP4_DVFS_CTRL;                     /**< FP4 DVFS Control, offset: 0x194 */
+  __IO uint32_t CPU2_FP4_HOST_WKUP_MASK;           /**< CPU2 15.4 Host Wakeup Mask, offset: 0x198 */
+  __IO uint32_t CPU2_FP4_HOST_WKUP_POL;            /**< CPU2 15.4 Host Wakeup Polarity, offset: 0x19C */
+  __IO uint32_t CPU2_FP4_HOST_WKUP_CTRL;           /**< CPU2 15.4 Host Wakeup Control, offset: 0x1A0 */
+  __IO uint32_t HW_IP_ACTIVE_INDEX_CTRL;           /**< HW IP active index Control, offset: 0x1A4 */
+  __IO uint32_t HW_IP_INACTIVE_INDEX_CTRL;         /**< HW IP inactive Control, offset: 0x1A8 */
+  __IO uint32_t HW_IP_DYNAMIC_CLK_SWITCH_CTRL;     /**< HW IP dynamic clock switching contrl, offset: 0x1AC */
+  __IO uint32_t IHB_CTRL;                          /**< IHB Control, offset: 0x1B0 */
+  __IO uint32_t IHB_WKUP_MASK;                     /**< IHB Wakeup Mask, offset: 0x1B4 */
+  __IO uint32_t CPU2_IHB_WKUP_MASK;                /**< CPU2 IHB Wakeup Mask, offset: 0x1B8 */
+  __I  uint32_t IHB_STATUS;                        /**< IHB Status, offset: 0x1BC */
+  __IO uint32_t USB_CTRL;                          /**< USB Control, offset: 0x1C0 */
+  __IO uint32_t USB_WKUP_MASK;                     /**< USB Wakeup Mask, offset: 0x1C4 */
+  __I  uint32_t USB_STATUS;                        /**< USB Status, offset: 0x1C8 */
+       uint8_t RESERVED_6[52];
+  __IO uint32_t CPU1_DVFS_CTRL;                    /**< CPU1 DVFS Control, offset: 0x200 */
+  __IO uint32_t CPU1_FREQ_REG1;                    /**< CPU1 Frequency 1, offset: 0x204 */
+  __IO uint32_t CPU1_FREQ_REG2;                    /**< CPU1 Frequency 2, offset: 0x208 */
+  __IO uint32_t CPU1_PLL_EN_REG;                   /**< CPU1 PLL Enable, offset: 0x20C */
+  __IO uint32_t CPU1_VOL_REG1;                     /**< CPU1 Voltage 1, offset: 0x210 */
+  __IO uint32_t CPU1_VOL_REG2;                     /**< CPU1 Voltage 2, offset: 0x214 */
+  __IO uint32_t CPU1_VOL_REG3;                     /**< CPU1 Voltage 3, offset: 0x218 */
+  __IO uint32_t CPU1_VOL_REG4;                     /**< CPU1 Voltage 4, offset: 0x21C */
+  __IO uint32_t CPU2_DVFS_CTRL;                    /**< CPU2 DVFS Control, offset: 0x220 */
+  __IO uint32_t CPU2_FREQ_REG1;                    /**< CPU2 Frequency 1, offset: 0x224 */
+  __IO uint32_t CPU2_FREQ_REG2;                    /**< CPU2 Frequency 2, offset: 0x228 */
+  __IO uint32_t CPU2_PLL_EN_REG;                   /**< CPU2 PLL Enable, offset: 0x22C */
+  __IO uint32_t CPU2_VOL_REG1;                     /**< CPU2 Voltage 1, offset: 0x230 */
+  __IO uint32_t CPU2_VOL_REG2;                     /**< CPU2 Voltage 2, offset: 0x234 */
+  __IO uint32_t CPU2_VOL_REG3;                     /**< CPU2 Voltage 3, offset: 0x238 */
+  __IO uint32_t CPU2_VOL_REG4;                     /**< CPU2 Voltage 4, offset: 0x23C */
+  __IO uint32_t SYS_FREQ_REG1;                     /**< System Frequency 1, offset: 0x240 */
+  __IO uint32_t SYS_FREQ_REG2;                     /**< System Frequency 2, offset: 0x244 */
+  __IO uint32_t SYS_PLL_EN_REG;                    /**< System PLL Enable, offset: 0x248 */
+  __IO uint32_t SYS_VOL_REG1;                      /**< System Voltage 1, offset: 0x24C */
+  __IO uint32_t SYS_VOL_REG2;                      /**< System Voltage 2, offset: 0x250 */
+  __IO uint32_t SYS_VOL_REG3;                      /**< System Voltage 3, offset: 0x254 */
+  __IO uint32_t SYS_VOL_REG4;                      /**< System Voltage 4, offset: 0x258 */
+  __IO uint32_t DVFS_CTRL;                         /**< DVFS Control, offset: 0x25C */
+  __IO uint32_t PARTIAL_DVFS_CTRL;                 /**< Partial DVFS Control, offset: 0x260 */
+  __IO uint32_t DVFS_TIMER;                        /**< DVFS Timer, offset: 0x264 */
+       uint8_t RESERVED_7[8];
+  __IO uint32_t AHB1_FREQ_REG1;                    /**< AHB1 Frequency 1, offset: 0x270 */
+  __IO uint32_t AHB1_FREQ_REG2;                    /**< AHB1 Frequency 2, offset: 0x274 */
+  __IO uint32_t AHB1_PLL_EN_REG;                   /**< AHB1 PLL Enable, offset: 0x278 */
+  __IO uint32_t AHB1_VOL_REG1;                     /**< AHB1 Voltage 1, offset: 0x27C */
+  __IO uint32_t AHB1_VOL_REG2;                     /**< AHB1 Voltage 2, offset: 0x280 */
+  __IO uint32_t AHB1_VOL_REG3;                     /**< AHB1 Voltage 3, offset: 0x284 */
+  __IO uint32_t AHB1_VOL_REG4;                     /**< AHB1 Voltage 4, offset: 0x288 */
+       uint8_t RESERVED_8[12];
+  __I  uint32_t DVFS_STATUS;                       /**< DVFS Status, offset: 0x298 */
+  __IO uint32_t DVFS_DBG_CTRL;                     /**< DVFS Debug Control, offset: 0x29C */
+  __IO uint32_t DVFS_DBG_PATTERN_DATA;             /**< DVFS Debug Pattern Data, offset: 0x2A0 */
+  __I  uint32_t DVFS_DBG_REG0;                     /**< DVFS Debug 0, offset: 0x2A4 */
+  __I  uint32_t DVFS_DBG_REG1;                     /**< DVFS Debug 1, offset: 0x2A8 */
+  __I  uint32_t DVFS_DBG_REG2;                     /**< DVFS Debug 2, offset: 0x2AC */
+  __I  uint32_t DVFS_DBG_REG3;                     /**< DVFS Debug 3, offset: 0x2B0 */
+  __I  uint32_t DVFS_DBG_REG4;                     /**< DVFS Debug 4, offset: 0x2B4 */
+  __I  uint32_t DVFS_DBG_REG5;                     /**< DVFS Debug 5, offset: 0x2B8 */
+  __I  uint32_t DVFS_DBG_STATUS;                   /**< DVFS Debug Status, offset: 0x2BC */
+  __IO uint32_t DVFS_DBG_PATTERN_MASK;             /**< DVFS Debug Patter Mask, offset: 0x2C0 */
+       uint8_t RESERVED_9[52];
+  __IO uint32_t DVFS_PMIC_TIMER;                   /**< DVFS PMIC Timer, offset: 0x2F8 */
+  __IO uint32_t DVFS_PMIC_MAP;                     /**< DVFS PMIC Map, offset: 0x2FC */
+  __IO uint32_t LDO_CTRL;                          /**< LDO Control, offset: 0x300 */
+  __IO uint32_t LDO_BACKUP_LVL_MAP1;               /**< LDO Backup Level Map 1, offset: 0x304 */
+  __IO uint32_t LDO_BACKUP_LVL_MAP2;               /**< LDO Backup Level Map 2, offset: 0x308 */
+  __I  uint32_t LDO_STATUS;                        /**< LDO Status, offset: 0x30C */
+  __IO uint32_t RC32_CAL_CTRL;                     /**< RC32 Calibration Control, offset: 0x310 */
+  __IO uint32_t RC32_CAL_SLPCLK_TIMER;             /**< RC32 Calibration Sleep Clock Timer, offset: 0x314 */
+  __I  uint32_t RC32CAL_SLPCLK_CNT_RD;             /**< RC32 Calibration Sleep Clock Count Read, offset: 0x318 */
+       uint8_t RESERVED_10[28];
+  __IO uint32_t TSTBUS_DATA;                       /**< Testbus Data, offset: 0x338 */
+  __IO uint32_t TST_CTRL;                          /**< Test Control, offset: 0x33C */
+  __IO uint32_t BCA_LTE_CTRL;                      /**< BCA LTE Control, offset: 0x340 */
+  __IO uint32_t BCA_LTE_TIMER1;                    /**< BCA LTE Timer 1, offset: 0x344 */
+  __IO uint32_t BCA_LTE_TIMER2;                    /**< BCA LTE Timer 2, offset: 0x348 */
+  __IO uint32_t BCA_MWS_WKUP_TIMER;                /**< BCA MWS Wakeup Timer, offset: 0x34C */
+  __IO uint32_t BT2_CTRL;                          /**< Bluetooth 2 Control, offset: 0x350 */
+  __IO uint32_t BT2_WKUP_MASK;                     /**< Bluetooth 2 Wakeup Mask, offset: 0x354 */
+  __I  uint32_t BT2_STATUS;                        /**< Bluetooth 2 Status, offset: 0x358 */
+  __IO uint32_t BT2_CKEN_CTRL;                     /**< Bluetooth 2 Clock Enable Control, offset: 0x35C */
+  __IO uint32_t BT2_RESRC_CTRL;                    /**< Bluetooth 2 RESRC Control, offset: 0x360 */
+  __IO uint32_t BT2_DVFS_CTRL;                     /**< Bluetooth 2 DVFS Control, offset: 0x364 */
+  __IO uint32_t BLE2_CTRL;                         /**< BLE 2 Control, offset: 0x368 */
+  __IO uint32_t BLE2_WKUP_MASK;                    /**< BLE 2 Wakeup Mask, offset: 0x36C */
+  __I  uint32_t BLE2_STATUS;                       /**< BLE 2 Status, offset: 0x370 */
+       uint8_t RESERVED_11[12];
+  __I  uint32_t LMU_IP_REVISION;                   /**< LMU IP Revision, offset: 0x380 */
+  __IO uint32_t LMU_CPU1_STA_CFG;                  /**< LMU CPU1 STA Configuration, offset: 0x384 */
+  __I  uint32_t LMU_CPU1_STA_STATUS1;              /**< LMU CPU1 STA Status 1, offset: 0x388 */
+  __I  uint32_t LMU_CPU1_STA_STATUS2;              /**< LMU CPU1 STA Status 2, offset: 0x38C */
+       uint8_t RESERVED_12[8];
+  __IO uint32_t LMU_CPU1_DYN_CTRL;                 /**< LMU CPU1 Dynamic Control, offset: 0x398 */
+  __I  uint32_t LMU_CPU1_DYN_STATUS;               /**< LMU CPU1 Dynamic Status, offset: 0x39C */
+       uint8_t RESERVED_13[8];
+  __IO uint32_t LMU_CPU2_STA_CFG;                  /**< LMU CPU2 STA Configuration, offset: 0x3A8 */
+  __I  uint32_t LMU_CPU2_STA_STATUS1;              /**< LMU CPU2 STA Status 1, offset: 0x3AC */
+  __IO uint32_t LMU_CPU3_STA_CFG;                  /**< LMU CPU3 STA Configuration, offset: 0x3B0 */
+  __I  uint32_t LMU_CPU3_STA_STATUS1;              /**< LMU CPU3 STA Status 1, offset: 0x3B4 */
+  __IO uint32_t LMU_G2BIST_CTRL;                   /**< LMU G2BIST Control, offset: 0x3B8 */
+  __I  uint32_t LMU_STATUS;                        /**< LMU Status, offset: 0x3BC */
+  __IO uint32_t LMU_STA_CFG_MASK;                  /**< LMU STA Configuration Mask, offset: 0x3C0 */
+  __I  uint32_t LMU_CPU2_STA_STATUS2;              /**< LMU CPU2 STA Status 2, offset: 0x3C4 */
+  __I  uint32_t LMU_CPU3_STA_STATUS2;              /**< LMU CPU3 STA Status 2, offset: 0x3C8 */
+       uint8_t RESERVED_14[4];
+  __IO uint32_t CPU3_HOST_WKUP_MASK;               /**< CPU3 Host Wakeup Mask, offset: 0x3D0 */
+  __IO uint32_t CPU3_HOST_WKUP_POL;                /**< CPU3 Host Wakeup Polarity, offset: 0x3D4 */
+  __IO uint32_t CPU3_HOST_WKUP_CTRL;               /**< CPU3 Host Wakeup Control, offset: 0x3D8 */
+  __IO uint32_t CPU3_CTRL;                         /**< CPU3 Control, offset: 0x3DC */
+  __IO uint32_t CPU3_DVFS_CTRL;                    /**< CPU3 DVFS Control, offset: 0x3E0 */
+  __IO uint32_t CPU3_FREQ_REG1;                    /**< CPU3 Frequency 1, offset: 0x3E4 */
+  __IO uint32_t CPU3_FREQ_REG2;                    /**< CPU3 Frequency 2, offset: 0x3E8 */
+  __IO uint32_t CPU3_PLL_EN_REG;                   /**< CPU3 PLL Enable, offset: 0x3EC */
+  __IO uint32_t CPU3_VOL_REG1;                     /**< CPU3 Voltage 1, offset: 0x3F0 */
+  __IO uint32_t CPU3_VOL_REG2;                     /**< CPU3 Voltage 2, offset: 0x3F4 */
+  __IO uint32_t CPU3_VOL_REG3;                     /**< CPU3 Voltage 3, offset: 0x3F8 */
+  __IO uint32_t CPU3_VOL_REG4;                     /**< CPU3 Voltage 4, offset: 0x3FC */
+} APU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- APU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup APU_Register_Masks APU Register Masks
+ * @{
+ */
+
+/*! @name APU_IP_REVISION - APU IP revision */
+/*! @{ */
+
+#define APU_APU_IP_REVISION_IP_REV_MASK          (0xFFFFU)
+#define APU_APU_IP_REVISION_IP_REV_SHIFT         (0U)
+/*! IP_REV - IP revision */
+#define APU_APU_IP_REVISION_IP_REV(x)            (((uint32_t)(((uint32_t)(x)) << APU_APU_IP_REVISION_IP_REV_SHIFT)) & APU_APU_IP_REVISION_IP_REV_MASK)
+/*! @} */
+
+/*! @name CTRL - Control */
+/*! @{ */
+
+#define APU_CTRL_CPU1_PD_MASK_MASK               (0x1U)
+#define APU_CTRL_CPU1_PD_MASK_SHIFT              (0U)
+/*! CPU1_PD_MASK - CPU1 Pd Mask */
+#define APU_CTRL_CPU1_PD_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << APU_CTRL_CPU1_PD_MASK_SHIFT)) & APU_CTRL_CPU1_PD_MASK_MASK)
+
+#define APU_CTRL_FW_CPU1_PD_MASK                 (0x2U)
+#define APU_CTRL_FW_CPU1_PD_SHIFT                (1U)
+/*! FW_CPU1_PD - FW CPU1 Pd */
+#define APU_CTRL_FW_CPU1_PD(x)                   (((uint32_t)(((uint32_t)(x)) << APU_CTRL_FW_CPU1_PD_SHIFT)) & APU_CTRL_FW_CPU1_PD_MASK)
+
+#define APU_CTRL_WLCOMN_USE_NOM_PWR_BYP_MASK     (0x8U)
+#define APU_CTRL_WLCOMN_USE_NOM_PWR_BYP_SHIFT    (3U)
+/*! WLCOMN_USE_NOM_PWR_BYP - WLAN comman domain uses nominal voltage */
+#define APU_CTRL_WLCOMN_USE_NOM_PWR_BYP(x)       (((uint32_t)(((uint32_t)(x)) << APU_CTRL_WLCOMN_USE_NOM_PWR_BYP_SHIFT)) & APU_CTRL_WLCOMN_USE_NOM_PWR_BYP_MASK)
+
+#define APU_CTRL_APU_SUBSYS1_HOST_MASK           (0x70U)
+#define APU_CTRL_APU_SUBSYS1_HOST_SHIFT          (4U)
+/*! APU_SUBSYS1_HOST - APU Subsystem1 Host */
+#define APU_CTRL_APU_SUBSYS1_HOST(x)             (((uint32_t)(((uint32_t)(x)) << APU_CTRL_APU_SUBSYS1_HOST_SHIFT)) & APU_CTRL_APU_SUBSYS1_HOST_MASK)
+
+#define APU_CTRL_APU_CAL_DONE_CLEAR_METHOD_MASK  (0x80U)
+#define APU_CTRL_APU_CAL_DONE_CLEAR_METHOD_SHIFT (7U)
+/*! APU_CAL_DONE_CLEAR_METHOD - 1- use falling edge of apu_sw_acc_rst to clear the apu_cal_done after FW polls the apu_cal_done = 1 */
+#define APU_CTRL_APU_CAL_DONE_CLEAR_METHOD(x)    (((uint32_t)(((uint32_t)(x)) << APU_CTRL_APU_CAL_DONE_CLEAR_METHOD_SHIFT)) & APU_CTRL_APU_CAL_DONE_CLEAR_METHOD_MASK)
+
+#define APU_CTRL_ENTER_ALL_SLEEP_MODE_MASK       (0x100U)
+#define APU_CTRL_ENTER_ALL_SLEEP_MODE_SHIFT      (8U)
+/*! ENTER_ALL_SLEEP_MODE - Enter All Sleep Mode */
+#define APU_CTRL_ENTER_ALL_SLEEP_MODE(x)         (((uint32_t)(((uint32_t)(x)) << APU_CTRL_ENTER_ALL_SLEEP_MODE_SHIFT)) & APU_CTRL_ENTER_ALL_SLEEP_MODE_MASK)
+
+#define APU_CTRL_USE_HOST_INTR_SLP_MASK          (0x200U)
+#define APU_CTRL_USE_HOST_INTR_SLP_SHIFT         (9U)
+/*! USE_HOST_INTR_SLP - Use Host Interrupt Sleep */
+#define APU_CTRL_USE_HOST_INTR_SLP(x)            (((uint32_t)(((uint32_t)(x)) << APU_CTRL_USE_HOST_INTR_SLP_SHIFT)) & APU_CTRL_USE_HOST_INTR_SLP_MASK)
+
+#define APU_CTRL_APU_ALLOW_AUTO_LOAD_MASK        (0x400U)
+#define APU_CTRL_APU_ALLOW_AUTO_LOAD_SHIFT       (10U)
+/*! APU_ALLOW_AUTO_LOAD - APU Allow Auto load */
+#define APU_CTRL_APU_ALLOW_AUTO_LOAD(x)          (((uint32_t)(((uint32_t)(x)) << APU_CTRL_APU_ALLOW_AUTO_LOAD_SHIFT)) & APU_CTRL_APU_ALLOW_AUTO_LOAD_MASK)
+
+#define APU_CTRL_APU_AUTO_CALIBRATE_MASK         (0x800U)
+#define APU_CTRL_APU_AUTO_CALIBRATE_SHIFT        (11U)
+/*! APU_AUTO_CALIBRATE - APU Auto Calibrate */
+#define APU_CTRL_APU_AUTO_CALIBRATE(x)           (((uint32_t)(((uint32_t)(x)) << APU_CTRL_APU_AUTO_CALIBRATE_SHIFT)) & APU_CTRL_APU_AUTO_CALIBRATE_MASK)
+
+#define APU_CTRL_APU_NO_TBTT_RESET_MASK          (0x1000U)
+#define APU_CTRL_APU_NO_TBTT_RESET_SHIFT         (12U)
+/*! APU_NO_TBTT_RESET - APU No TBTT Reset */
+#define APU_CTRL_APU_NO_TBTT_RESET(x)            (((uint32_t)(((uint32_t)(x)) << APU_CTRL_APU_NO_TBTT_RESET_SHIFT)) & APU_CTRL_APU_NO_TBTT_RESET_MASK)
+
+#define APU_CTRL_SW_TIMER_LD_MASK                (0x2000U)
+#define APU_CTRL_SW_TIMER_LD_SHIFT               (13U)
+/*! SW_TIMER_LD - SW Timer */
+#define APU_CTRL_SW_TIMER_LD(x)                  (((uint32_t)(((uint32_t)(x)) << APU_CTRL_SW_TIMER_LD_SHIFT)) & APU_CTRL_SW_TIMER_LD_MASK)
+
+#define APU_CTRL_RST_APU_SLPCLK_TIMER_MASK       (0x4000U)
+#define APU_CTRL_RST_APU_SLPCLK_TIMER_SHIFT      (14U)
+/*! RST_APU_SLPCLK_TIMER - Reset APU Sleep Clock Timer */
+#define APU_CTRL_RST_APU_SLPCLK_TIMER(x)         (((uint32_t)(((uint32_t)(x)) << APU_CTRL_RST_APU_SLPCLK_TIMER_SHIFT)) & APU_CTRL_RST_APU_SLPCLK_TIMER_MASK)
+
+#define APU_CTRL_APU_SW_ACC_RST_MASK             (0x8000U)
+#define APU_CTRL_APU_SW_ACC_RST_SHIFT            (15U)
+/*! APU_SW_ACC_RST - APU SW ACC Reset */
+#define APU_CTRL_APU_SW_ACC_RST(x)               (((uint32_t)(((uint32_t)(x)) << APU_CTRL_APU_SW_ACC_RST_SHIFT)) & APU_CTRL_APU_SW_ACC_RST_MASK)
+
+#define APU_CTRL_SDU_SLP_RDY_MASK_MASK           (0x20000U)
+#define APU_CTRL_SDU_SLP_RDY_MASK_SHIFT          (17U)
+/*! SDU_SLP_RDY_MASK - SDU Sleep Ready Mask */
+#define APU_CTRL_SDU_SLP_RDY_MASK(x)             (((uint32_t)(((uint32_t)(x)) << APU_CTRL_SDU_SLP_RDY_MASK_SHIFT)) & APU_CTRL_SDU_SLP_RDY_MASK_MASK)
+
+#define APU_CTRL_IPS_CP15_SLEEP_MASK_MASK        (0x200000U)
+#define APU_CTRL_IPS_CP15_SLEEP_MASK_SHIFT       (21U)
+/*! IPS_CP15_SLEEP_MASK - IPS CP15 Sleep Mask */
+#define APU_CTRL_IPS_CP15_SLEEP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << APU_CTRL_IPS_CP15_SLEEP_MASK_SHIFT)) & APU_CTRL_IPS_CP15_SLEEP_MASK_MASK)
+
+#define APU_CTRL_FW_IPS_CP15_SLEEP_MASK          (0x400000U)
+#define APU_CTRL_FW_IPS_CP15_SLEEP_SHIFT         (22U)
+/*! FW_IPS_CP15_SLEEP - FW IPS CP15 Sleep */
+#define APU_CTRL_FW_IPS_CP15_SLEEP(x)            (((uint32_t)(((uint32_t)(x)) << APU_CTRL_FW_IPS_CP15_SLEEP_SHIFT)) & APU_CTRL_FW_IPS_CP15_SLEEP_MASK)
+
+#define APU_CTRL_CP_15_SLEEP_MASK_MASK           (0x800000U)
+#define APU_CTRL_CP_15_SLEEP_MASK_SHIFT          (23U)
+/*! CP_15_SLEEP_MASK - CP15 Sleep Mask */
+#define APU_CTRL_CP_15_SLEEP_MASK(x)             (((uint32_t)(((uint32_t)(x)) << APU_CTRL_CP_15_SLEEP_MASK_SHIFT)) & APU_CTRL_CP_15_SLEEP_MASK_MASK)
+
+#define APU_CTRL_FW_CP15_SLEEP_MASK              (0x1000000U)
+#define APU_CTRL_FW_CP15_SLEEP_SHIFT             (24U)
+/*! FW_CP15_SLEEP - FW CP15 Sleep */
+#define APU_CTRL_FW_CP15_SLEEP(x)                (((uint32_t)(((uint32_t)(x)) << APU_CTRL_FW_CP15_SLEEP_SHIFT)) & APU_CTRL_FW_CP15_SLEEP_MASK)
+
+#define APU_CTRL_CPU1_MSG_RDY_MASK_MASK          (0x2000000U)
+#define APU_CTRL_CPU1_MSG_RDY_MASK_SHIFT         (25U)
+/*! CPU1_MSG_RDY_MASK - CPU1 Message Ready Mask */
+#define APU_CTRL_CPU1_MSG_RDY_MASK(x)            (((uint32_t)(((uint32_t)(x)) << APU_CTRL_CPU1_MSG_RDY_MASK_SHIFT)) & APU_CTRL_CPU1_MSG_RDY_MASK_MASK)
+/*! @} */
+
+/*! @name TIMER_PWR_MODE - Timer Power Mode */
+/*! @{ */
+
+#define APU_TIMER_PWR_MODE_MCI_XP_REQ_MASK_MASK  (0x1U)
+#define APU_TIMER_PWR_MODE_MCI_XP_REQ_MASK_SHIFT (0U)
+/*! MCI_XP_REQ_MASK - MCI XP Request Mask */
+#define APU_TIMER_PWR_MODE_MCI_XP_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_MCI_XP_REQ_MASK_SHIFT)) & APU_TIMER_PWR_MODE_MCI_XP_REQ_MASK_MASK)
+
+#define APU_TIMER_PWR_MODE_SLP_CLK_TIMER_EN_MASK (0x10U)
+#define APU_TIMER_PWR_MODE_SLP_CLK_TIMER_EN_SHIFT (4U)
+/*! SLP_CLK_TIMER_EN - free running sleep clock timer enable */
+#define APU_TIMER_PWR_MODE_SLP_CLK_TIMER_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_SLP_CLK_TIMER_EN_SHIFT)) & APU_TIMER_PWR_MODE_SLP_CLK_TIMER_EN_MASK)
+
+#define APU_TIMER_PWR_MODE_WL_BCN_ALARM_TIMER_EN_MASK (0x20U)
+#define APU_TIMER_PWR_MODE_WL_BCN_ALARM_TIMER_EN_SHIFT (5U)
+/*! WL_BCN_ALARM_TIMER_EN - WLAN beacon alarm timer enable */
+#define APU_TIMER_PWR_MODE_WL_BCN_ALARM_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_WL_BCN_ALARM_TIMER_EN_SHIFT)) & APU_TIMER_PWR_MODE_WL_BCN_ALARM_TIMER_EN_MASK)
+
+#define APU_TIMER_PWR_MODE_WL2_BCN_ALARM_TIMER_EN_MASK (0x40U)
+#define APU_TIMER_PWR_MODE_WL2_BCN_ALARM_TIMER_EN_SHIFT (6U)
+/*! WL2_BCN_ALARM_TIMER_EN - WLAN2 beacon alarm timer enable */
+#define APU_TIMER_PWR_MODE_WL2_BCN_ALARM_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_WL2_BCN_ALARM_TIMER_EN_SHIFT)) & APU_TIMER_PWR_MODE_WL2_BCN_ALARM_TIMER_EN_MASK)
+
+#define APU_TIMER_PWR_MODE_DIS_GATED_SLP_CLK_MASK (0x80U)
+#define APU_TIMER_PWR_MODE_DIS_GATED_SLP_CLK_SHIFT (7U)
+/*! DIS_GATED_SLP_CLK - Disable Gated Sleep Clock */
+#define APU_TIMER_PWR_MODE_DIS_GATED_SLP_CLK(x)  (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_DIS_GATED_SLP_CLK_SHIFT)) & APU_TIMER_PWR_MODE_DIS_GATED_SLP_CLK_MASK)
+
+#define APU_TIMER_PWR_MODE_XP_OPT_EN_MASK        (0x1000U)
+#define APU_TIMER_PWR_MODE_XP_OPT_EN_SHIFT       (12U)
+/*! XP_OPT_EN - Set to 1 to enable the sleep FSM to look for wakeup req after power shutdown and before reference clock shutdown. */
+#define APU_TIMER_PWR_MODE_XP_OPT_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_XP_OPT_EN_SHIFT)) & APU_TIMER_PWR_MODE_XP_OPT_EN_MASK)
+
+#define APU_TIMER_PWR_MODE_DIS_APU_INTR_ON_WAKEUP_MASK (0x2000U)
+#define APU_TIMER_PWR_MODE_DIS_APU_INTR_ON_WAKEUP_SHIFT (13U)
+/*! DIS_APU_INTR_ON_WAKEUP - Disable APU Interrupt on Wakeup */
+#define APU_TIMER_PWR_MODE_DIS_APU_INTR_ON_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_DIS_APU_INTR_ON_WAKEUP_SHIFT)) & APU_TIMER_PWR_MODE_DIS_APU_INTR_ON_WAKEUP_MASK)
+
+#define APU_TIMER_PWR_MODE_SOC_XOSC_PWR_ON_MASK  (0x20000U)
+#define APU_TIMER_PWR_MODE_SOC_XOSC_PWR_ON_SHIFT (17U)
+/*! SOC_XOSC_PWR_ON - SoC XOSC Power on */
+#define APU_TIMER_PWR_MODE_SOC_XOSC_PWR_ON(x)    (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_SOC_XOSC_PWR_ON_SHIFT)) & APU_TIMER_PWR_MODE_SOC_XOSC_PWR_ON_MASK)
+
+#define APU_TIMER_PWR_MODE_ENA_FAST_WKUP_MASK    (0x40000U)
+#define APU_TIMER_PWR_MODE_ENA_FAST_WKUP_SHIFT   (18U)
+/*! ENA_FAST_WKUP - Enable Fast Wakeup */
+#define APU_TIMER_PWR_MODE_ENA_FAST_WKUP(x)      (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_ENA_FAST_WKUP_SHIFT)) & APU_TIMER_PWR_MODE_ENA_FAST_WKUP_MASK)
+
+#define APU_TIMER_PWR_MODE_GENERIC_TIMER_EN_MASK (0x200000U)
+#define APU_TIMER_PWR_MODE_GENERIC_TIMER_EN_SHIFT (21U)
+/*! GENERIC_TIMER_EN - Enable sleep timer to generate interrupt when value matches generic timer value. Debug only */
+#define APU_TIMER_PWR_MODE_GENERIC_TIMER_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_GENERIC_TIMER_EN_SHIFT)) & APU_TIMER_PWR_MODE_GENERIC_TIMER_EN_MASK)
+
+#define APU_TIMER_PWR_MODE_GENERIC_TIMER_BYPASS_MASK (0x400000U)
+#define APU_TIMER_PWR_MODE_GENERIC_TIMER_BYPASS_SHIFT (22U)
+/*! GENERIC_TIMER_BYPASS - When set to 1, generic_alarm_en2 will be used for generic_alarm_en1 */
+#define APU_TIMER_PWR_MODE_GENERIC_TIMER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_GENERIC_TIMER_BYPASS_SHIFT)) & APU_TIMER_PWR_MODE_GENERIC_TIMER_BYPASS_MASK)
+
+#define APU_TIMER_PWR_MODE_XOSC_ON_WHILE_SLEEP_MASK (0x800000U)
+#define APU_TIMER_PWR_MODE_XOSC_ON_WHILE_SLEEP_SHIFT (23U)
+/*! XOSC_ON_WHILE_SLEEP - XOSC On While Sleep */
+#define APU_TIMER_PWR_MODE_XOSC_ON_WHILE_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_XOSC_ON_WHILE_SLEEP_SHIFT)) & APU_TIMER_PWR_MODE_XOSC_ON_WHILE_SLEEP_MASK)
+
+#define APU_TIMER_PWR_MODE_USE_HSIC_SLP_SYNC_MASK (0x1000000U)
+#define APU_TIMER_PWR_MODE_USE_HSIC_SLP_SYNC_SHIFT (24U)
+/*! USE_HSIC_SLP_SYNC - Use HSIC Sleep Sync */
+#define APU_TIMER_PWR_MODE_USE_HSIC_SLP_SYNC(x)  (((uint32_t)(((uint32_t)(x)) << APU_TIMER_PWR_MODE_USE_HSIC_SLP_SYNC_SHIFT)) & APU_TIMER_PWR_MODE_USE_HSIC_SLP_SYNC_MASK)
+/*! @} */
+
+/*! @name PWR_CTRL - Power Control */
+/*! @{ */
+
+#define APU_PWR_CTRL_APU_PD_CTRL_EN_MASK         (0x1U)
+#define APU_PWR_CTRL_APU_PD_CTRL_EN_SHIFT        (0U)
+/*! APU_PD_CTRL_EN - APU power domain control enable */
+#define APU_PWR_CTRL_APU_PD_CTRL_EN(x)           (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_APU_PD_CTRL_EN_SHIFT)) & APU_PWR_CTRL_APU_PD_CTRL_EN_MASK)
+
+#define APU_PWR_CTRL_APU_SW_PD_EN_MASK           (0x2U)
+#define APU_PWR_CTRL_APU_SW_PD_EN_SHIFT          (1U)
+/*! APU_SW_PD_EN - APU switch power down enable */
+#define APU_PWR_CTRL_APU_SW_PD_EN(x)             (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_APU_SW_PD_EN_SHIFT)) & APU_PWR_CTRL_APU_SW_PD_EN_MASK)
+
+#define APU_PWR_CTRL_APU_UDR_FIREWALL_BAR_EN_MASK (0x4U)
+#define APU_PWR_CTRL_APU_UDR_FIREWALL_BAR_EN_SHIFT (2U)
+/*! APU_UDR_FIREWALL_BAR_EN - APU UDR enable */
+#define APU_PWR_CTRL_APU_UDR_FIREWALL_BAR_EN(x)  (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_APU_UDR_FIREWALL_BAR_EN_SHIFT)) & APU_PWR_CTRL_APU_UDR_FIREWALL_BAR_EN_MASK)
+
+#define APU_PWR_CTRL_APU_ISO_CELL_EN_MASK        (0x8U)
+#define APU_PWR_CTRL_APU_ISO_CELL_EN_SHIFT       (3U)
+/*! APU_ISO_CELL_EN - APU isolation enable */
+#define APU_PWR_CTRL_APU_ISO_CELL_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_APU_ISO_CELL_EN_SHIFT)) & APU_PWR_CTRL_APU_ISO_CELL_EN_MASK)
+
+#define APU_PWR_CTRL_DLY_UDR2ISO_MASK            (0x10U)
+#define APU_PWR_CTRL_DLY_UDR2ISO_SHIFT           (4U)
+/*! DLY_UDR2ISO - UDR firewall_bar to isolation delay enable */
+#define APU_PWR_CTRL_DLY_UDR2ISO(x)              (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_DLY_UDR2ISO_SHIFT)) & APU_PWR_CTRL_DLY_UDR2ISO_MASK)
+
+#define APU_PWR_CTRL_ISO_ENABLE_REFCK_MASK       (0x20U)
+#define APU_PWR_CTRL_ISO_ENABLE_REFCK_SHIFT      (5U)
+/*! ISO_ENABLE_REFCK - ISO Enable Reference Clock */
+#define APU_PWR_CTRL_ISO_ENABLE_REFCK(x)         (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_ISO_ENABLE_REFCK_SHIFT)) & APU_PWR_CTRL_ISO_ENABLE_REFCK_MASK)
+
+#define APU_PWR_CTRL_NON_UDR_RSTB_EN_MASK        (0x40U)
+#define APU_PWR_CTRL_NON_UDR_RSTB_EN_SHIFT       (6U)
+/*! NON_UDR_RSTB_EN - APU non-UDR reset enable */
+#define APU_PWR_CTRL_NON_UDR_RSTB_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_NON_UDR_RSTB_EN_SHIFT)) & APU_PWR_CTRL_NON_UDR_RSTB_EN_MASK)
+
+#define APU_PWR_CTRL_XOSC_OFF_DURING_POWER_OFF_MASK (0x80U)
+#define APU_PWR_CTRL_XOSC_OFF_DURING_POWER_OFF_SHIFT (7U)
+/*! XOSC_OFF_DURING_POWER_OFF - XOSC Off During Power Off */
+#define APU_PWR_CTRL_XOSC_OFF_DURING_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_XOSC_OFF_DURING_POWER_OFF_SHIFT)) & APU_PWR_CTRL_XOSC_OFF_DURING_POWER_OFF_MASK)
+
+#define APU_PWR_CTRL_SRAM_PD_EN_MASK             (0x100U)
+#define APU_PWR_CTRL_SRAM_PD_EN_SHIFT            (8U)
+/*! SRAM_PD_EN - APU SRAM power down enable */
+#define APU_PWR_CTRL_SRAM_PD_EN(x)               (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_SRAM_PD_EN_SHIFT)) & APU_PWR_CTRL_SRAM_PD_EN_MASK)
+
+#define APU_PWR_CTRL_CLK_DIV_RESETB_ENABLE_MASK  (0x200U)
+#define APU_PWR_CTRL_CLK_DIV_RESETB_ENABLE_SHIFT (9U)
+/*! CLK_DIV_RESETB_ENABLE - CLK_DIV_RESETB Enable */
+#define APU_PWR_CTRL_CLK_DIV_RESETB_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_CLK_DIV_RESETB_ENABLE_SHIFT)) & APU_PWR_CTRL_CLK_DIV_RESETB_ENABLE_MASK)
+
+#define APU_PWR_CTRL_CLK_DIV_RESETB_REFCLK_MASK  (0x400U)
+#define APU_PWR_CTRL_CLK_DIV_RESETB_REFCLK_SHIFT (10U)
+/*! CLK_DIV_RESETB_REFCLK - CLK_DIV_RESETB Reference Clock */
+#define APU_PWR_CTRL_CLK_DIV_RESETB_REFCLK(x)    (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_CLK_DIV_RESETB_REFCLK_SHIFT)) & APU_PWR_CTRL_CLK_DIV_RESETB_REFCLK_MASK)
+
+#define APU_PWR_CTRL_SOC_USE_NOM_VOL_BYP_MASK    (0x800U)
+#define APU_PWR_CTRL_SOC_USE_NOM_VOL_BYP_SHIFT   (11U)
+/*! SOC_USE_NOM_VOL_BYP - SoC Use Nominal Vol Bypass */
+#define APU_PWR_CTRL_SOC_USE_NOM_VOL_BYP(x)      (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_SOC_USE_NOM_VOL_BYP_SHIFT)) & APU_PWR_CTRL_SOC_USE_NOM_VOL_BYP_MASK)
+
+#define APU_PWR_CTRL_SOC_USE_UNSYNC_VOL_LVL_MASK (0x1000U)
+#define APU_PWR_CTRL_SOC_USE_UNSYNC_VOL_LVL_SHIFT (12U)
+/*! SOC_USE_UNSYNC_VOL_LVL - SoC Use unSync Vol Level */
+#define APU_PWR_CTRL_SOC_USE_UNSYNC_VOL_LVL(x)   (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_SOC_USE_UNSYNC_VOL_LVL_SHIFT)) & APU_PWR_CTRL_SOC_USE_UNSYNC_VOL_LVL_MASK)
+
+#define APU_PWR_CTRL_RFU_IN_WLAN_DOMAIN_MASK     (0x2000U)
+#define APU_PWR_CTRL_RFU_IN_WLAN_DOMAIN_SHIFT    (13U)
+/*! RFU_IN_WLAN_DOMAIN - RFU WLAN mode */
+#define APU_PWR_CTRL_RFU_IN_WLAN_DOMAIN(x)       (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_RFU_IN_WLAN_DOMAIN_SHIFT)) & APU_PWR_CTRL_RFU_IN_WLAN_DOMAIN_MASK)
+
+#define APU_PWR_CTRL_DLY_NON_UDR_RSTB_MASK       (0x4000U)
+#define APU_PWR_CTRL_DLY_NON_UDR_RSTB_SHIFT      (14U)
+/*! DLY_NON_UDR_RSTB - Delay non-UDR RSTb */
+#define APU_PWR_CTRL_DLY_NON_UDR_RSTB(x)         (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_DLY_NON_UDR_RSTB_SHIFT)) & APU_PWR_CTRL_DLY_NON_UDR_RSTB_MASK)
+
+#define APU_PWR_CTRL_PCIE_P_REQ_MASK_FOR_SLPFSM_MASK (0x8000U)
+#define APU_PWR_CTRL_PCIE_P_REQ_MASK_FOR_SLPFSM_SHIFT (15U)
+/*! PCIE_P_REQ_MASK_FOR_SLPFSM - Mask pcie_p_req and pcie_xp_req for slp_fsm */
+#define APU_PWR_CTRL_PCIE_P_REQ_MASK_FOR_SLPFSM(x) (((uint32_t)(((uint32_t)(x)) << APU_PWR_CTRL_PCIE_P_REQ_MASK_FOR_SLPFSM_SHIFT)) & APU_PWR_CTRL_PCIE_P_REQ_MASK_FOR_SLPFSM_MASK)
+/*! @} */
+
+/*! @name PLL_CTRL - PLL Control */
+/*! @{ */
+
+#define APU_PLL_CTRL_DIS_APU_PLL_EN0_MASK        (0x1U)
+#define APU_PLL_CTRL_DIS_APU_PLL_EN0_SHIFT       (0U)
+/*! DIS_APU_PLL_EN0 - When set to 1, apu_pll_en[0]=0 (pll0 is Tcpu in Skyhawk) */
+#define APU_PLL_CTRL_DIS_APU_PLL_EN0(x)          (((uint32_t)(((uint32_t)(x)) << APU_PLL_CTRL_DIS_APU_PLL_EN0_SHIFT)) & APU_PLL_CTRL_DIS_APU_PLL_EN0_MASK)
+
+#define APU_PLL_CTRL_DIS_APU_PLL_EN1_MASK        (0x2U)
+#define APU_PLL_CTRL_DIS_APU_PLL_EN1_SHIFT       (1U)
+/*! DIS_APU_PLL_EN1 - When set to 1, apu_pll_en[1]=0 (pll1 is Tsoc in Skyhawk) */
+#define APU_PLL_CTRL_DIS_APU_PLL_EN1(x)          (((uint32_t)(((uint32_t)(x)) << APU_PLL_CTRL_DIS_APU_PLL_EN1_SHIFT)) & APU_PLL_CTRL_DIS_APU_PLL_EN1_MASK)
+
+#define APU_PLL_CTRL_FW_USE_PLL0_MASK            (0x10U)
+#define APU_PLL_CTRL_FW_USE_PLL0_SHIFT           (4U)
+/*! FW_USE_PLL0 - When set to 1, FW controls pll_en[0] value (pll0 is Tcpu in Skyhawk) */
+#define APU_PLL_CTRL_FW_USE_PLL0(x)              (((uint32_t)(((uint32_t)(x)) << APU_PLL_CTRL_FW_USE_PLL0_SHIFT)) & APU_PLL_CTRL_FW_USE_PLL0_MASK)
+
+#define APU_PLL_CTRL_FW_PLL0_EN_SET_MASK         (0x20U)
+#define APU_PLL_CTRL_FW_PLL0_EN_SET_SHIFT        (5U)
+/*! FW_PLL0_EN_SET - Fw sets pll_en[0] value when apu_pll_ctrl[4] = 1, */
+#define APU_PLL_CTRL_FW_PLL0_EN_SET(x)           (((uint32_t)(((uint32_t)(x)) << APU_PLL_CTRL_FW_PLL0_EN_SET_SHIFT)) & APU_PLL_CTRL_FW_PLL0_EN_SET_MASK)
+
+#define APU_PLL_CTRL_FW_USE_PLL1_MASK            (0x100U)
+#define APU_PLL_CTRL_FW_USE_PLL1_SHIFT           (8U)
+/*! FW_USE_PLL1 - When set to 1, FW controls pll_en[1] value (pll0 is Tcpu in Skyhawk) */
+#define APU_PLL_CTRL_FW_USE_PLL1(x)              (((uint32_t)(((uint32_t)(x)) << APU_PLL_CTRL_FW_USE_PLL1_SHIFT)) & APU_PLL_CTRL_FW_USE_PLL1_MASK)
+
+#define APU_PLL_CTRL_FW_PLL1_EN_SET_MASK         (0x200U)
+#define APU_PLL_CTRL_FW_PLL1_EN_SET_SHIFT        (9U)
+/*! FW_PLL1_EN_SET - Fw sets pll_en[1] value when apu_pll_ctrl[4] = 1, */
+#define APU_PLL_CTRL_FW_PLL1_EN_SET(x)           (((uint32_t)(((uint32_t)(x)) << APU_PLL_CTRL_FW_PLL1_EN_SET_SHIFT)) & APU_PLL_CTRL_FW_PLL1_EN_SET_MASK)
+/*! @} */
+
+/*! @name PLL_DIS_CNT - PLL Disable Count */
+/*! @{ */
+
+#define APU_PLL_DIS_CNT_PLL_DIS_CNT_MASK         (0xFFFFU)
+#define APU_PLL_DIS_CNT_PLL_DIS_CNT_SHIFT        (0U)
+/*! PLL_DIS_CNT - PLL disable count in reference clocks */
+#define APU_PLL_DIS_CNT_PLL_DIS_CNT(x)           (((uint32_t)(((uint32_t)(x)) << APU_PLL_DIS_CNT_PLL_DIS_CNT_SHIFT)) & APU_PLL_DIS_CNT_PLL_DIS_CNT_MASK)
+/*! @} */
+
+/*! @name STABLE_CNT - Stable Count */
+/*! @{ */
+
+#define APU_STABLE_CNT_XOSC_STABLE_CNT_MASK      (0xFFFFU)
+#define APU_STABLE_CNT_XOSC_STABLE_CNT_SHIFT     (0U)
+/*! XOSC_STABLE_CNT - XOSC stable count in sleep clocks after APU asserts xosc_en */
+#define APU_STABLE_CNT_XOSC_STABLE_CNT(x)        (((uint32_t)(((uint32_t)(x)) << APU_STABLE_CNT_XOSC_STABLE_CNT_SHIFT)) & APU_STABLE_CNT_XOSC_STABLE_CNT_MASK)
+
+#define APU_STABLE_CNT_PLL_STABLE_CNT_MASK       (0xFFFF0000U)
+#define APU_STABLE_CNT_PLL_STABLE_CNT_SHIFT      (16U)
+/*! PLL_STABLE_CNT - PLL stable count in sleep clocks after APU asserts pll_en */
+#define APU_STABLE_CNT_PLL_STABLE_CNT(x)         (((uint32_t)(((uint32_t)(x)) << APU_STABLE_CNT_PLL_STABLE_CNT_SHIFT)) & APU_STABLE_CNT_PLL_STABLE_CNT_MASK)
+/*! @} */
+
+/*! @name CPU1_HOST_WKUP_MASK - CPU1 Host Wakeup Mask */
+/*! @{ */
+
+#define APU_CPU1_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK (0xFFFFU)
+#define APU_CPU1_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT (0U)
+/*! HOST_WKUP_MASK - Host Wakeup Mask */
+#define APU_CPU1_HOST_WKUP_MASK_HOST_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT)) & APU_CPU1_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK)
+/*! @} */
+
+/*! @name CPU1_HOST_WKUP_POL - CPU1 Host Wakeup Polarity */
+/*! @{ */
+
+#define APU_CPU1_HOST_WKUP_POL_HOST_WKUP_POL_MASK (0xFFFFU)
+#define APU_CPU1_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT (0U)
+/*! HOST_WKUP_POL - Host Wakeup Polarity */
+#define APU_CPU1_HOST_WKUP_POL_HOST_WKUP_POL(x)  (((uint32_t)(((uint32_t)(x)) << APU_CPU1_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT)) & APU_CPU1_HOST_WKUP_POL_HOST_WKUP_POL_MASK)
+/*! @} */
+
+/*! @name CAL_WIN_CNT - Calibration Window Count */
+/*! @{ */
+
+#define APU_CAL_WIN_CNT_APU_CAL_WIN_CNT_MASK     (0xFFFFFFFFU)
+#define APU_CAL_WIN_CNT_APU_CAL_WIN_CNT_SHIFT    (0U)
+/*! APU_CAL_WIN_CNT - Number of calibration clocks elapsed during calibration window */
+#define APU_CAL_WIN_CNT_APU_CAL_WIN_CNT(x)       (((uint32_t)(((uint32_t)(x)) << APU_CAL_WIN_CNT_APU_CAL_WIN_CNT_SHIFT)) & APU_CAL_WIN_CNT_APU_CAL_WIN_CNT_MASK)
+/*! @} */
+
+/*! @name AUTO_10US - Auto 10us */
+/*! @{ */
+
+#define APU_AUTO_10US_APU_AUTO_10US_MASK         (0xFFFFFFFFU)
+#define APU_AUTO_10US_APU_AUTO_10US_SHIFT        (0U)
+/*! APU_AUTO_10US - auto alarm value loaded during auto calibration */
+#define APU_AUTO_10US_APU_AUTO_10US(x)           (((uint32_t)(((uint32_t)(x)) << APU_AUTO_10US_APU_AUTO_10US_SHIFT)) & APU_AUTO_10US_APU_AUTO_10US_MASK)
+/*! @} */
+
+/*! @name ACC_CNT - Accumulation Count */
+/*! @{ */
+
+#define APU_ACC_CNT_APU_ACC_CNT_MASK             (0xFFFFFFFFU)
+#define APU_ACC_CNT_APU_ACC_CNT_SHIFT            (0U)
+/*! APU_ACC_CNT - number of sleep clocks elapsed during the calibration window */
+#define APU_ACC_CNT_APU_ACC_CNT(x)               (((uint32_t)(((uint32_t)(x)) << APU_ACC_CNT_APU_ACC_CNT_SHIFT)) & APU_ACC_CNT_APU_ACC_CNT_MASK)
+/*! @} */
+
+/*! @name CAL_WIN_SIZE - Calibration Window Size */
+/*! @{ */
+
+#define APU_CAL_WIN_SIZE_APU_CAL_WIN_SIZE_MASK   (0xFFFFFFFFU)
+#define APU_CAL_WIN_SIZE_APU_CAL_WIN_SIZE_SHIFT  (0U)
+/*! APU_CAL_WIN_SIZE - calibration window size in number of calibration clocks. */
+#define APU_CAL_WIN_SIZE_APU_CAL_WIN_SIZE(x)     (((uint32_t)(((uint32_t)(x)) << APU_CAL_WIN_SIZE_APU_CAL_WIN_SIZE_SHIFT)) & APU_CAL_WIN_SIZE_APU_CAL_WIN_SIZE_MASK)
+/*! @} */
+
+/*! @name SLP_CLK_TIMER - Sleep Clock Timer */
+/*! @{ */
+
+#define APU_SLP_CLK_TIMER_APU_SLP_CLK_TIMER_MASK (0xFFFFFFFFU)
+#define APU_SLP_CLK_TIMER_APU_SLP_CLK_TIMER_SHIFT (0U)
+/*! APU_SLP_CLK_TIMER - reads back the current value of the free running sleep clock counter. */
+#define APU_SLP_CLK_TIMER_APU_SLP_CLK_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << APU_SLP_CLK_TIMER_APU_SLP_CLK_TIMER_SHIFT)) & APU_SLP_CLK_TIMER_APU_SLP_CLK_TIMER_MASK)
+/*! @} */
+
+/*! @name STATUS_RD - Status Read */
+/*! @{ */
+
+#define APU_STATUS_RD_CALIBRATION_STATUS_MASK    (0x1U)
+#define APU_STATUS_RD_CALIBRATION_STATUS_SHIFT   (0U)
+/*! CALIBRATION_STATUS - Calibration Status */
+#define APU_STATUS_RD_CALIBRATION_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_CALIBRATION_STATUS_SHIFT)) & APU_STATUS_RD_CALIBRATION_STATUS_MASK)
+
+#define APU_STATUS_RD_APU_PLL_STABLE_0_MASK      (0x2U)
+#define APU_STATUS_RD_APU_PLL_STABLE_0_SHIFT     (1U)
+/*! APU_PLL_STABLE_0 - T1 PLL stable */
+#define APU_STATUS_RD_APU_PLL_STABLE_0(x)        (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_PLL_STABLE_0_SHIFT)) & APU_STATUS_RD_APU_PLL_STABLE_0_MASK)
+
+#define APU_STATUS_RD_APU_PLL_STABLE_1_MASK      (0x4U)
+#define APU_STATUS_RD_APU_PLL_STABLE_1_SHIFT     (2U)
+/*! APU_PLL_STABLE_1 - APU PLL Stable[1] */
+#define APU_STATUS_RD_APU_PLL_STABLE_1(x)        (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_PLL_STABLE_1_SHIFT)) & APU_STATUS_RD_APU_PLL_STABLE_1_MASK)
+
+#define APU_STATUS_RD_APU_XOSC_STABLE_MASK       (0x8U)
+#define APU_STATUS_RD_APU_XOSC_STABLE_SHIFT      (3U)
+/*! APU_XOSC_STABLE - APU XOSC Stable */
+#define APU_STATUS_RD_APU_XOSC_STABLE(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_XOSC_STABLE_SHIFT)) & APU_STATUS_RD_APU_XOSC_STABLE_MASK)
+
+#define APU_STATUS_RD_APU_BT2_CLK_EN_MASK        (0x10U)
+#define APU_STATUS_RD_APU_BT2_CLK_EN_SHIFT       (4U)
+/*! APU_BT2_CLK_EN - APU Bluetooth2 Clock Enable */
+#define APU_STATUS_RD_APU_BT2_CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_BT2_CLK_EN_SHIFT)) & APU_STATUS_RD_APU_BT2_CLK_EN_MASK)
+
+#define APU_STATUS_RD_APU_MAC_CLK_EN2_MASK       (0x20U)
+#define APU_STATUS_RD_APU_MAC_CLK_EN2_SHIFT      (5U)
+/*! APU_MAC_CLK_EN2 - APU MAC Clock Enable 2 */
+#define APU_STATUS_RD_APU_MAC_CLK_EN2(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_MAC_CLK_EN2_SHIFT)) & APU_STATUS_RD_APU_MAC_CLK_EN2_MASK)
+
+#define APU_STATUS_RD_APU_BT_CLK_EN_MASK         (0x40U)
+#define APU_STATUS_RD_APU_BT_CLK_EN_SHIFT        (6U)
+/*! APU_BT_CLK_EN - APU Bluetooth Clock Enable */
+#define APU_STATUS_RD_APU_BT_CLK_EN(x)           (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_BT_CLK_EN_SHIFT)) & APU_STATUS_RD_APU_BT_CLK_EN_MASK)
+
+#define APU_STATUS_RD_APU_MAC_CLK_EN1_MASK       (0x80U)
+#define APU_STATUS_RD_APU_MAC_CLK_EN1_SHIFT      (7U)
+/*! APU_MAC_CLK_EN1 - APU MAC Clock Enable 1 */
+#define APU_STATUS_RD_APU_MAC_CLK_EN1(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_MAC_CLK_EN1_SHIFT)) & APU_STATUS_RD_APU_MAC_CLK_EN1_MASK)
+
+#define APU_STATUS_RD_APU_SYS_CLK_EN_MASK        (0x100U)
+#define APU_STATUS_RD_APU_SYS_CLK_EN_SHIFT       (8U)
+/*! APU_SYS_CLK_EN - APU System Clock Enable */
+#define APU_STATUS_RD_APU_SYS_CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_SYS_CLK_EN_SHIFT)) & APU_STATUS_RD_APU_SYS_CLK_EN_MASK)
+
+#define APU_STATUS_RD_APU_SOC_CLK_EN3_MASK       (0x200U)
+#define APU_STATUS_RD_APU_SOC_CLK_EN3_SHIFT      (9U)
+/*! APU_SOC_CLK_EN3 - APU SoC Clock Enable 3 */
+#define APU_STATUS_RD_APU_SOC_CLK_EN3(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_SOC_CLK_EN3_SHIFT)) & APU_STATUS_RD_APU_SOC_CLK_EN3_MASK)
+
+#define APU_STATUS_RD_APU_SOC_CLK_EN2_MASK       (0x400U)
+#define APU_STATUS_RD_APU_SOC_CLK_EN2_SHIFT      (10U)
+/*! APU_SOC_CLK_EN2 - APU SoC Clock Enable 2 */
+#define APU_STATUS_RD_APU_SOC_CLK_EN2(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_SOC_CLK_EN2_SHIFT)) & APU_STATUS_RD_APU_SOC_CLK_EN2_MASK)
+
+#define APU_STATUS_RD_APU_SOC_CLK_EN1_MASK       (0x800U)
+#define APU_STATUS_RD_APU_SOC_CLK_EN1_SHIFT      (11U)
+/*! APU_SOC_CLK_EN1 - APU SoC Clock Enable 1 */
+#define APU_STATUS_RD_APU_SOC_CLK_EN1(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_SOC_CLK_EN1_SHIFT)) & APU_STATUS_RD_APU_SOC_CLK_EN1_MASK)
+
+#define APU_STATUS_RD_APU_SLEEP_FSM_STATE_MASK   (0xF000U)
+#define APU_STATUS_RD_APU_SLEEP_FSM_STATE_SHIFT  (12U)
+/*! APU_SLEEP_FSM_STATE - APU Sleep FSM State */
+#define APU_STATUS_RD_APU_SLEEP_FSM_STATE(x)     (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_APU_SLEEP_FSM_STATE_SHIFT)) & APU_STATUS_RD_APU_SLEEP_FSM_STATE_MASK)
+
+#define APU_STATUS_RD_HOST_WKUP_AFTER_MASK_MASK  (0xFFFF0000U)
+#define APU_STATUS_RD_HOST_WKUP_AFTER_MASK_SHIFT (16U)
+/*! HOST_WKUP_AFTER_MASK - Host Wakeup After Mask */
+#define APU_STATUS_RD_HOST_WKUP_AFTER_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_STATUS_RD_HOST_WKUP_AFTER_MASK_SHIFT)) & APU_STATUS_RD_HOST_WKUP_AFTER_MASK_MASK)
+/*! @} */
+
+/*! @name STABLE_CNT2 - Stable Count 2 */
+/*! @{ */
+
+#define APU_STABLE_CNT2_PLL2_STBL_CNT_MASK       (0xFFFFU)
+#define APU_STABLE_CNT2_PLL2_STBL_CNT_SHIFT      (0U)
+/*! PLL2_STBL_CNT - T3 stable count in reference clocks */
+#define APU_STABLE_CNT2_PLL2_STBL_CNT(x)         (((uint32_t)(((uint32_t)(x)) << APU_STABLE_CNT2_PLL2_STBL_CNT_SHIFT)) & APU_STABLE_CNT2_PLL2_STBL_CNT_MASK)
+/*! @} */
+
+/*! @name DYN_PLL_MASK - Dynamic PLL Mask */
+/*! @{ */
+
+#define APU_DYN_PLL_MASK_BT_PLL_REQ_MASK_MASK    (0x20U)
+#define APU_DYN_PLL_MASK_BT_PLL_REQ_MASK_SHIFT   (5U)
+/*! BT_PLL_REQ_MASK - When mask =0, bt_pll_req treated as pll_req */
+#define APU_DYN_PLL_MASK_BT_PLL_REQ_MASK(x)      (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_BT_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_BT_PLL_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_BRF_PLL_REQ_MASK_MASK   (0x40U)
+#define APU_DYN_PLL_MASK_BRF_PLL_REQ_MASK_SHIFT  (6U)
+/*! BRF_PLL_REQ_MASK - When mask =0, brf_pll_req treated as pll_req */
+#define APU_DYN_PLL_MASK_BRF_PLL_REQ_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_BRF_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_BRF_PLL_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_BT_AES_CLK_REQ_MASK_MASK (0x80U)
+#define APU_DYN_PLL_MASK_BT_AES_CLK_REQ_MASK_SHIFT (7U)
+/*! BT_AES_CLK_REQ_MASK - When mask is 0, bt_aes_clk_req is treated as pll_req of bt_aes_nco_mode =0 */
+#define APU_DYN_PLL_MASK_BT_AES_CLK_REQ_MASK(x)  (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_BT_AES_CLK_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_BT_AES_CLK_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_BT_CLK_REQ_PLL_REQ_MASK_MASK (0x100U)
+#define APU_DYN_PLL_MASK_BT_CLK_REQ_PLL_REQ_MASK_SHIFT (8U)
+/*! BT_CLK_REQ_PLL_REQ_MASK - When mask is 0, bt_clk_req is treated as pll_req if soc_use_ref_only = 0 */
+#define APU_DYN_PLL_MASK_BT_CLK_REQ_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_BT_CLK_REQ_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_BT_CLK_REQ_PLL_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_BT_SLP_RDY_PLL_REQ_MASK_MASK (0x200U)
+#define APU_DYN_PLL_MASK_BT_SLP_RDY_PLL_REQ_MASK_SHIFT (9U)
+/*! BT_SLP_RDY_PLL_REQ_MASK - When mask is 0, !bt_slp_rdy is treated as pll_req if soc_use_ref_only = 0 */
+#define APU_DYN_PLL_MASK_BT_SLP_RDY_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_BT_SLP_RDY_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_BT_SLP_RDY_PLL_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_BLE_SLP_RDY_PLL_REQ_MASK_MASK (0x400U)
+#define APU_DYN_PLL_MASK_BLE_SLP_RDY_PLL_REQ_MASK_SHIFT (10U)
+/*! BLE_SLP_RDY_PLL_REQ_MASK - When mask is 0, !ble_slp_rdy is treated as pll_req if soc_use_ref_only = 0 */
+#define APU_DYN_PLL_MASK_BLE_SLP_RDY_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_BLE_SLP_RDY_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_BLE_SLP_RDY_PLL_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_CPU2_CP15_PLL_REQ_MASK_MASK (0x800U)
+#define APU_DYN_PLL_MASK_CPU2_CP15_PLL_REQ_MASK_SHIFT (11U)
+/*! CPU2_CP15_PLL_REQ_MASK - When mask is 0, !cpu2_cp15_sleep is treated as pll_req if soc_use_ref_only = 0 */
+#define APU_DYN_PLL_MASK_CPU2_CP15_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_CPU2_CP15_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_CPU2_CP15_PLL_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_SD_CLK_SWITCH_OK_MASK_MASK (0x1000U)
+#define APU_DYN_PLL_MASK_SD_CLK_SWITCH_OK_MASK_SHIFT (12U)
+/*! SD_CLK_SWITCH_OK_MASK - SD Clock Switch Ok Mask */
+#define APU_DYN_PLL_MASK_SD_CLK_SWITCH_OK_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_SD_CLK_SWITCH_OK_MASK_SHIFT)) & APU_DYN_PLL_MASK_SD_CLK_SWITCH_OK_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_GEN_TIMER_WKUP_PLL_REQ_MASK_MASK (0x2000U)
+#define APU_DYN_PLL_MASK_GEN_TIMER_WKUP_PLL_REQ_MASK_SHIFT (13U)
+/*! GEN_TIMER_WKUP_PLL_REQ_MASK - When mask is 0, gen_timer_wkup_wkup is treated as pll_req if soc_use_ref_only = 0 */
+#define APU_DYN_PLL_MASK_GEN_TIMER_WKUP_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_GEN_TIMER_WKUP_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_GEN_TIMER_WKUP_PLL_REQ_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_FULL_SLP_MASK_MASK      (0x4000U)
+#define APU_DYN_PLL_MASK_FULL_SLP_MASK_SHIFT     (14U)
+/*! FULL_SLP_MASK - Full Sleep Mask */
+#define APU_DYN_PLL_MASK_FULL_SLP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_FULL_SLP_MASK_SHIFT)) & APU_DYN_PLL_MASK_FULL_SLP_MASK_MASK)
+
+#define APU_DYN_PLL_MASK_HOST_WKUP_PLL_REQ_MASK_MASK (0xFFFF0000U)
+#define APU_DYN_PLL_MASK_HOST_WKUP_PLL_REQ_MASK_SHIFT (16U)
+/*! HOST_WKUP_PLL_REQ_MASK - When mask is 0, host_wkup is treated as pll_req if soc_use_ref_only = 0 */
+#define APU_DYN_PLL_MASK_HOST_WKUP_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_MASK_HOST_WKUP_PLL_REQ_MASK_SHIFT)) & APU_DYN_PLL_MASK_HOST_WKUP_PLL_REQ_MASK_MASK)
+/*! @} */
+
+/*! @name TESTBUS_RD1 - Testbus Read 1 */
+/*! @{ */
+
+#define APU_TESTBUS_RD1_TIMER_CNTR_MASK          (0xFFFFU)
+#define APU_TESTBUS_RD1_TIMER_CNTR_SHIFT         (0U)
+/*! TIMER_CNTR - DVFS internal counter */
+#define APU_TESTBUS_RD1_TIMER_CNTR(x)            (((uint32_t)(((uint32_t)(x)) << APU_TESTBUS_RD1_TIMER_CNTR_SHIFT)) & APU_TESTBUS_RD1_TIMER_CNTR_MASK)
+
+#define APU_TESTBUS_RD1_DVFS_TIMER_MASK          (0xFFFF0000U)
+#define APU_TESTBUS_RD1_DVFS_TIMER_SHIFT         (16U)
+/*! DVFS_TIMER - DVFS timer */
+#define APU_TESTBUS_RD1_DVFS_TIMER(x)            (((uint32_t)(((uint32_t)(x)) << APU_TESTBUS_RD1_DVFS_TIMER_SHIFT)) & APU_TESTBUS_RD1_DVFS_TIMER_MASK)
+/*! @} */
+
+/*! @name TESTBUS_RD2 - Testbus Read 2 */
+/*! @{ */
+
+#define APU_TESTBUS_RD2_APU_TESTBUS_RD2_MASK     (0xFFFFFFFFU)
+#define APU_TESTBUS_RD2_APU_TESTBUS_RD2_SHIFT    (0U)
+/*! APU_TESTBUS_RD2 - Last 8 FSM state changes are stored in the register */
+#define APU_TESTBUS_RD2_APU_TESTBUS_RD2(x)       (((uint32_t)(((uint32_t)(x)) << APU_TESTBUS_RD2_APU_TESTBUS_RD2_SHIFT)) & APU_TESTBUS_RD2_APU_TESTBUS_RD2_MASK)
+/*! @} */
+
+/*! @name GENERIC_TIMER_CNT - Generic Timer Count */
+/*! @{ */
+
+#define APU_GENERIC_TIMER_CNT_GENERIC_TIMER_CNT_MASK (0xFFFFFFFFU)
+#define APU_GENERIC_TIMER_CNT_GENERIC_TIMER_CNT_SHIFT (0U)
+/*! GENERIC_TIMER_CNT - Generic Timer Count */
+#define APU_GENERIC_TIMER_CNT_GENERIC_TIMER_CNT(x) (((uint32_t)(((uint32_t)(x)) << APU_GENERIC_TIMER_CNT_GENERIC_TIMER_CNT_SHIFT)) & APU_GENERIC_TIMER_CNT_GENERIC_TIMER_CNT_MASK)
+/*! @} */
+
+/*! @name CPU1_HOST_WKUP_CTRL - CPU1 Host Wakeup Control */
+/*! @{ */
+
+#define APU_CPU1_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK (0xFFFFU)
+#define APU_CPU1_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT (0U)
+/*! HOST_WKUP_CTRL - Host Wakeup Control */
+#define APU_CPU1_HOST_WKUP_CTRL_HOST_WKUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT)) & APU_CPU1_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK)
+
+#define APU_CPU1_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK (0xFFFF0000U)
+#define APU_CPU1_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT (16U)
+/*! HOST_INTR_MASK - Host Interrupt Mask */
+#define APU_CPU1_HOST_WKUP_CTRL_HOST_INTR_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT)) & APU_CPU1_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK)
+/*! @} */
+
+/*! @name DYN_PLL_CLK_EXT_CTRL - Dynamic PLL Clock Ext Control */
+/*! @{ */
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK1_EXT_EN_MASK (0x1U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK1_EXT_EN_SHIFT (0U)
+/*! SOC_CLK1_EXT_EN - SoC Clock 1 Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK1_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK1_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK1_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK2_EXT_EN_MASK (0x2U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK2_EXT_EN_SHIFT (1U)
+/*! SOC_CLK2_EXT_EN - SoC Clock 2 Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK2_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK2_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK2_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK3_EXT_EN_MASK (0x4U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK3_EXT_EN_SHIFT (2U)
+/*! SOC_CLK3_EXT_EN - SoC Clock 3 Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK3_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK3_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_SOC_CLK3_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU1_PLL_EXT_EN_MASK (0x10U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU1_PLL_EXT_EN_SHIFT (4U)
+/*! CPU1_PLL_EXT_EN - CPU1 PLL Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU1_PLL_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_CPU1_PLL_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_CPU1_PLL_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU1_INACTIVE_EXT_EN_MASK (0x20U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU1_INACTIVE_EXT_EN_SHIFT (5U)
+/*! CPU1_INACTIVE_EXT_EN - CPU1 Inactive Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU1_INACTIVE_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_CPU1_INACTIVE_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_CPU1_INACTIVE_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU2_PLL_EXT_EN_MASK (0x40U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU2_PLL_EXT_EN_SHIFT (6U)
+/*! CPU2_PLL_EXT_EN - CPU2 PLL Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU2_PLL_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_CPU2_PLL_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_CPU2_PLL_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU2_INACTIVE_EXT_EN_MASK (0x80U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU2_INACTIVE_EXT_EN_SHIFT (7U)
+/*! CPU2_INACTIVE_EXT_EN - CPU2 Inactive Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU2_INACTIVE_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_CPU2_INACTIVE_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_CPU2_INACTIVE_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_T1_EXT_EN_MASK  (0x100U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_T1_EXT_EN_SHIFT (8U)
+/*! T1_EXT_EN - T1 Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_T1_EXT_EN(x)    (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_T1_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_T1_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_T3_EXT_EN_MASK  (0x200U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_T3_EXT_EN_SHIFT (9U)
+/*! T3_EXT_EN - T3 Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_T3_EXT_EN(x)    (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_T3_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_T3_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_DVFS_T1_EXT_EN_MASK (0x400U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_DVFS_T1_EXT_EN_SHIFT (10U)
+/*! DVFS_T1_EXT_EN - DVFS T1 Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_DVFS_T1_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_DVFS_T1_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_DVFS_T1_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU3_PLL_EXT_EN_MASK (0x800U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU3_PLL_EXT_EN_SHIFT (11U)
+/*! CPU3_PLL_EXT_EN - CPU3 PLL Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU3_PLL_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_CPU3_PLL_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_CPU3_PLL_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU3_INACTIVE_EXT_EN_MASK (0x1000U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU3_INACTIVE_EXT_EN_SHIFT (12U)
+/*! CPU3_INACTIVE_EXT_EN - CPU3 Inactive Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_CPU3_INACTIVE_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_CPU3_INACTIVE_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_CPU3_INACTIVE_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_CLK_EXT_EN_MASK (0x10000000U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_CLK_EXT_EN_SHIFT (28U)
+/*! BT2_AES_CLK_EXT_EN - BLuetooth2 AES Clock Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_CLK_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_CLK_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_CLK_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_PLL_EXT_EN_MASK (0x20000000U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_PLL_EXT_EN_SHIFT (29U)
+/*! BT2_AES_PLL_EXT_EN - Bluetooth2 AES PLL Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_PLL_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_PLL_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_BT2_AES_PLL_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_CLK_EXT_EN_MASK (0x40000000U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_CLK_EXT_EN_SHIFT (30U)
+/*! BT_AES_CLK_EXT_EN - BLuetooth AES Clock Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_CLK_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_CLK_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_CLK_EXT_EN_MASK)
+
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_PLL_EXT_EN_MASK (0x80000000U)
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_PLL_EXT_EN_SHIFT (31U)
+/*! BT_AES_PLL_EXT_EN - Bluetooth AES PLL Ext Enable */
+#define APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_PLL_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_PLL_EXT_EN_SHIFT)) & APU_DYN_PLL_CLK_EXT_CTRL_BT_AES_PLL_EXT_EN_MASK)
+/*! @} */
+
+/*! @name GENERIC_SLP_START_VAL - Generic Sleep Start Value */
+/*! @{ */
+
+#define APU_GENERIC_SLP_START_VAL_GENERIC_SLP_START_VAL_MASK (0xFFFFFFFFU)
+#define APU_GENERIC_SLP_START_VAL_GENERIC_SLP_START_VAL_SHIFT (0U)
+/*! GENERIC_SLP_START_VAL - Generic Sleep Start Value */
+#define APU_GENERIC_SLP_START_VAL_GENERIC_SLP_START_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_GENERIC_SLP_START_VAL_GENERIC_SLP_START_VAL_SHIFT)) & APU_GENERIC_SLP_START_VAL_GENERIC_SLP_START_VAL_MASK)
+/*! @} */
+
+/*! @name DLY_HOST_CTRL - Delay Host Control */
+/*! @{ */
+
+#define APU_DLY_HOST_CTRL_DLY_HOST_WKUP_EN_MASK  (0x1U)
+#define APU_DLY_HOST_CTRL_DLY_HOST_WKUP_EN_SHIFT (0U)
+/*! DLY_HOST_WKUP_EN - Delay Host Wakeup Enable */
+#define APU_DLY_HOST_CTRL_DLY_HOST_WKUP_EN(x)    (((uint32_t)(((uint32_t)(x)) << APU_DLY_HOST_CTRL_DLY_HOST_WKUP_EN_SHIFT)) & APU_DLY_HOST_CTRL_DLY_HOST_WKUP_EN_MASK)
+
+#define APU_DLY_HOST_CTRL_HOST_WKUP_SEL_MASK     (0x78U)
+#define APU_DLY_HOST_CTRL_HOST_WKUP_SEL_SHIFT    (3U)
+/*! HOST_WKUP_SEL - selects which host wakeup to be delayed out of 16 hosts */
+#define APU_DLY_HOST_CTRL_HOST_WKUP_SEL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DLY_HOST_CTRL_HOST_WKUP_SEL_SHIFT)) & APU_DLY_HOST_CTRL_HOST_WKUP_SEL_MASK)
+
+#define APU_DLY_HOST_CTRL_RST_HOST_WKUP_CNT_MASK (0x80U)
+#define APU_DLY_HOST_CTRL_RST_HOST_WKUP_CNT_SHIFT (7U)
+/*! RST_HOST_WKUP_CNT - Reset Host Wakeup Count */
+#define APU_DLY_HOST_CTRL_RST_HOST_WKUP_CNT(x)   (((uint32_t)(((uint32_t)(x)) << APU_DLY_HOST_CTRL_RST_HOST_WKUP_CNT_SHIFT)) & APU_DLY_HOST_CTRL_RST_HOST_WKUP_CNT_MASK)
+
+#define APU_DLY_HOST_CTRL_DLY_HOST_WKUP_CNT_MASK (0xFFFFFF00U)
+#define APU_DLY_HOST_CTRL_DLY_HOST_WKUP_CNT_SHIFT (8U)
+/*! DLY_HOST_WKUP_CNT - Number of sleep clocks to delay host wakeup interrupt */
+#define APU_DLY_HOST_CTRL_DLY_HOST_WKUP_CNT(x)   (((uint32_t)(((uint32_t)(x)) << APU_DLY_HOST_CTRL_DLY_HOST_WKUP_CNT_SHIFT)) & APU_DLY_HOST_CTRL_DLY_HOST_WKUP_CNT_MASK)
+/*! @} */
+
+/*! @name HOST_WKUP_CNT - Host Wakeup Count */
+/*! @{ */
+
+#define APU_HOST_WKUP_CNT_HOST_WKUP_DLY_CNT_MASK (0xFFFFFFU)
+#define APU_HOST_WKUP_CNT_HOST_WKUP_DLY_CNT_SHIFT (0U)
+/*! HOST_WKUP_DLY_CNT - Host Wakeup Delay Count */
+#define APU_HOST_WKUP_CNT_HOST_WKUP_DLY_CNT(x)   (((uint32_t)(((uint32_t)(x)) << APU_HOST_WKUP_CNT_HOST_WKUP_DLY_CNT_SHIFT)) & APU_HOST_WKUP_CNT_HOST_WKUP_DLY_CNT_MASK)
+/*! @} */
+
+/*! @name CPU2_HOST_WKUP_MASK - CPU2 Host Wakeup Mask */
+/*! @{ */
+
+#define APU_CPU2_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK (0xFFFFU)
+#define APU_CPU2_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT (0U)
+/*! HOST_WKUP_MASK - Host Wakeup Mask */
+#define APU_CPU2_HOST_WKUP_MASK_HOST_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT)) & APU_CPU2_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK)
+/*! @} */
+
+/*! @name CPU2_HOST_WKUP_POL - CPU2 Host Wakeup Polarity */
+/*! @{ */
+
+#define APU_CPU2_HOST_WKUP_POL_HOST_WKUP_POL_MASK (0xFFFFU)
+#define APU_CPU2_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT (0U)
+/*! HOST_WKUP_POL - Host Wakeup Polarity */
+#define APU_CPU2_HOST_WKUP_POL_HOST_WKUP_POL(x)  (((uint32_t)(((uint32_t)(x)) << APU_CPU2_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT)) & APU_CPU2_HOST_WKUP_POL_HOST_WKUP_POL_MASK)
+/*! @} */
+
+/*! @name CPU2_HOST_WKUP_CTRL - CPU2 Host Wakeup Control */
+/*! @{ */
+
+#define APU_CPU2_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK (0xFFFFU)
+#define APU_CPU2_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT (0U)
+/*! HOST_WKUP_CTRL - Host Wakeup Control */
+#define APU_CPU2_HOST_WKUP_CTRL_HOST_WKUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT)) & APU_CPU2_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK)
+
+#define APU_CPU2_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK (0xFFFF0000U)
+#define APU_CPU2_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT (16U)
+/*! HOST_INTR_MASK - Host Interrupt Mask */
+#define APU_CPU2_HOST_WKUP_CTRL_HOST_INTR_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT)) & APU_CPU2_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK)
+/*! @} */
+
+/*! @name CPU2_CTRL - CPU2 Control */
+/*! @{ */
+
+#define APU_CPU2_CTRL_CPU2_MSG_RDY_MASK_MASK     (0x1U)
+#define APU_CPU2_CTRL_CPU2_MSG_RDY_MASK_SHIFT    (0U)
+/*! CPU2_MSG_RDY_MASK - CPU2 Message Ready Mask */
+#define APU_CPU2_CTRL_CPU2_MSG_RDY_MASK(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU2_CTRL_CPU2_MSG_RDY_MASK_SHIFT)) & APU_CPU2_CTRL_CPU2_MSG_RDY_MASK_MASK)
+
+#define APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_VAL_MASK (0x4U)
+#define APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_VAL_SHIFT (2U)
+/*! CPU2_CP15_SLP_BYPASS_VAL - CPU2 CP15 Sleep Bypass Value */
+#define APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_VAL_SHIFT)) & APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_VAL_MASK)
+
+#define APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_EN_MASK (0x8U)
+#define APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_EN_SHIFT (3U)
+/*! CPU2_CP15_SLP_BYPASS_EN - CPU2 CP15 Sleep Bypass Enable */
+#define APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_EN_SHIFT)) & APU_CPU2_CTRL_CPU2_CP15_SLP_BYPASS_EN_MASK)
+
+#define APU_CPU2_CTRL_SOC_USE_REF_ONLY_MASK      (0x10U)
+#define APU_CPU2_CTRL_SOC_USE_REF_ONLY_SHIFT     (4U)
+/*! SOC_USE_REF_ONLY - SoC Use Ref Only */
+#define APU_CPU2_CTRL_SOC_USE_REF_ONLY(x)        (((uint32_t)(((uint32_t)(x)) << APU_CPU2_CTRL_SOC_USE_REF_ONLY_SHIFT)) & APU_CPU2_CTRL_SOC_USE_REF_ONLY_MASK)
+
+#define APU_CPU2_CTRL_GENERIC_TIMER_EN2_MASK     (0x20U)
+#define APU_CPU2_CTRL_GENERIC_TIMER_EN2_SHIFT    (5U)
+/*! GENERIC_TIMER_EN2 - Generic Timer Enable 2 */
+#define APU_CPU2_CTRL_GENERIC_TIMER_EN2(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU2_CTRL_GENERIC_TIMER_EN2_SHIFT)) & APU_CPU2_CTRL_GENERIC_TIMER_EN2_MASK)
+
+#define APU_CPU2_CTRL_APU_SUBSYS2_HOST_MASK      (0x70000U)
+#define APU_CPU2_CTRL_APU_SUBSYS2_HOST_SHIFT     (16U)
+/*! APU_SUBSYS2_HOST - APU Subsystem 2 Host */
+#define APU_CPU2_CTRL_APU_SUBSYS2_HOST(x)        (((uint32_t)(((uint32_t)(x)) << APU_CPU2_CTRL_APU_SUBSYS2_HOST_SHIFT)) & APU_CPU2_CTRL_APU_SUBSYS2_HOST_MASK)
+/*! @} */
+
+/*! @name WLAN_PWR_CTRL_DLY - Wlan domain FSM Power Control Delay */
+/*! @{ */
+
+#define APU_WLAN_PWR_CTRL_DLY_PWR_CTRL_DLY_MASK  (0xFFFFFFFFU)
+#define APU_WLAN_PWR_CTRL_DLY_PWR_CTRL_DLY_SHIFT (0U)
+/*! PWR_CTRL_DLY - Wlan domain FSM Power Control Delay */
+#define APU_WLAN_PWR_CTRL_DLY_PWR_CTRL_DLY(x)    (((uint32_t)(((uint32_t)(x)) << APU_WLAN_PWR_CTRL_DLY_PWR_CTRL_DLY_SHIFT)) & APU_WLAN_PWR_CTRL_DLY_PWR_CTRL_DLY_MASK)
+/*! @} */
+
+/*! @name STATUS2 - Status 2 */
+/*! @{ */
+
+#define APU_STATUS2_CPU1_MSG_RDY_INT_MASK        (0x1U)
+#define APU_STATUS2_CPU1_MSG_RDY_INT_SHIFT       (0U)
+/*! CPU1_MSG_RDY_INT - CPU1 Message Ready */
+#define APU_STATUS2_CPU1_MSG_RDY_INT(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_CPU1_MSG_RDY_INT_SHIFT)) & APU_STATUS2_CPU1_MSG_RDY_INT_MASK)
+
+#define APU_STATUS2_CPU2_MSG_RDY_INT_MASK        (0x2U)
+#define APU_STATUS2_CPU2_MSG_RDY_INT_SHIFT       (1U)
+/*! CPU2_MSG_RDY_INT - CPU2 Message Ready */
+#define APU_STATUS2_CPU2_MSG_RDY_INT(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_CPU2_MSG_RDY_INT_SHIFT)) & APU_STATUS2_CPU2_MSG_RDY_INT_MASK)
+
+#define APU_STATUS2_CPU3_MSG_RDY_INT_MASK        (0x4U)
+#define APU_STATUS2_CPU3_MSG_RDY_INT_SHIFT       (2U)
+/*! CPU3_MSG_RDY_INT - CPU3 Message Ready */
+#define APU_STATUS2_CPU3_MSG_RDY_INT(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_CPU3_MSG_RDY_INT_SHIFT)) & APU_STATUS2_CPU3_MSG_RDY_INT_MASK)
+
+#define APU_STATUS2_LMU_G2BIST_FINISH_MASK       (0x8U)
+#define APU_STATUS2_LMU_G2BIST_FINISH_SHIFT      (3U)
+/*! LMU_G2BIST_FINISH - LMU G2BIST finish */
+#define APU_STATUS2_LMU_G2BIST_FINISH(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_LMU_G2BIST_FINISH_SHIFT)) & APU_STATUS2_LMU_G2BIST_FINISH_MASK)
+
+#define APU_STATUS2_APU_BT_AES_CLK_EN_MASK       (0x10U)
+#define APU_STATUS2_APU_BT_AES_CLK_EN_SHIFT      (4U)
+/*! APU_BT_AES_CLK_EN - BT AES Clk enable */
+#define APU_STATUS2_APU_BT_AES_CLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BT_AES_CLK_EN_SHIFT)) & APU_STATUS2_APU_BT_AES_CLK_EN_MASK)
+
+#define APU_STATUS2_APU_BT2_AES_CLK_EN_MASK      (0x20U)
+#define APU_STATUS2_APU_BT2_AES_CLK_EN_SHIFT     (5U)
+/*! APU_BT2_AES_CLK_EN - BT2 AES Clk enable */
+#define APU_STATUS2_APU_BT2_AES_CLK_EN(x)        (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BT2_AES_CLK_EN_SHIFT)) & APU_STATUS2_APU_BT2_AES_CLK_EN_MASK)
+
+#define APU_STATUS2_APU_BT_AES_CLK_SEL_MASK      (0x40U)
+#define APU_STATUS2_APU_BT_AES_CLK_SEL_SHIFT     (6U)
+/*! APU_BT_AES_CLK_SEL - BT AES clk select */
+#define APU_STATUS2_APU_BT_AES_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BT_AES_CLK_SEL_SHIFT)) & APU_STATUS2_APU_BT_AES_CLK_SEL_MASK)
+
+#define APU_STATUS2_APU_BT2_AES_CLK_SEL_MASK     (0x80U)
+#define APU_STATUS2_APU_BT2_AES_CLK_SEL_SHIFT    (7U)
+/*! APU_BT2_AES_CLK_SEL - BT2 AES clk select */
+#define APU_STATUS2_APU_BT2_AES_CLK_SEL(x)       (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BT2_AES_CLK_SEL_SHIFT)) & APU_STATUS2_APU_BT2_AES_CLK_SEL_MASK)
+
+#define APU_STATUS2_APU_BRF_CLK_EN_MASK          (0x100U)
+#define APU_STATUS2_APU_BRF_CLK_EN_SHIFT         (8U)
+/*! APU_BRF_CLK_EN - BRF clk enable */
+#define APU_STATUS2_APU_BRF_CLK_EN(x)            (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BRF_CLK_EN_SHIFT)) & APU_STATUS2_APU_BRF_CLK_EN_MASK)
+
+#define APU_STATUS2_APU_BRF2_CLK_EN_MASK         (0x200U)
+#define APU_STATUS2_APU_BRF2_CLK_EN_SHIFT        (9U)
+/*! APU_BRF2_CLK_EN - BRF2 clk enable */
+#define APU_STATUS2_APU_BRF2_CLK_EN(x)           (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BRF2_CLK_EN_SHIFT)) & APU_STATUS2_APU_BRF2_CLK_EN_MASK)
+
+#define APU_STATUS2_APU_INTR_BT_WAKEUP_MASK      (0x400U)
+#define APU_STATUS2_APU_INTR_BT_WAKEUP_SHIFT     (10U)
+/*! APU_INTR_BT_WAKEUP - APU BT2 wakeup interrupt */
+#define APU_STATUS2_APU_INTR_BT_WAKEUP(x)        (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_INTR_BT_WAKEUP_SHIFT)) & APU_STATUS2_APU_INTR_BT_WAKEUP_MASK)
+
+#define APU_STATUS2_APU_INTR_BT2_WAKEUP_MASK     (0x800U)
+#define APU_STATUS2_APU_INTR_BT2_WAKEUP_SHIFT    (11U)
+/*! APU_INTR_BT2_WAKEUP - APU BT2 wakeup interrupt */
+#define APU_STATUS2_APU_INTR_BT2_WAKEUP(x)       (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_INTR_BT2_WAKEUP_SHIFT)) & APU_STATUS2_APU_INTR_BT2_WAKEUP_MASK)
+
+#define APU_STATUS2_APU_BBUD_CLK_EN1_MASK        (0x1000U)
+#define APU_STATUS2_APU_BBUD_CLK_EN1_SHIFT       (12U)
+/*! APU_BBUD_CLK_EN1 - bbud2 clk enable */
+#define APU_STATUS2_APU_BBUD_CLK_EN1(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BBUD_CLK_EN1_SHIFT)) & APU_STATUS2_APU_BBUD_CLK_EN1_MASK)
+
+#define APU_STATUS2_APU_BBUD_CLK_EN2_MASK        (0x2000U)
+#define APU_STATUS2_APU_BBUD_CLK_EN2_SHIFT       (13U)
+/*! APU_BBUD_CLK_EN2 - bbud1 clk enable */
+#define APU_STATUS2_APU_BBUD_CLK_EN2(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_BBUD_CLK_EN2_SHIFT)) & APU_STATUS2_APU_BBUD_CLK_EN2_MASK)
+
+#define APU_STATUS2_APU_WL_RF_CLK_EN1_MASK       (0x4000U)
+#define APU_STATUS2_APU_WL_RF_CLK_EN1_SHIFT      (14U)
+/*! APU_WL_RF_CLK_EN1 - WLAN RFU1 clk enable */
+#define APU_STATUS2_APU_WL_RF_CLK_EN1(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_WL_RF_CLK_EN1_SHIFT)) & APU_STATUS2_APU_WL_RF_CLK_EN1_MASK)
+
+#define APU_STATUS2_APU_WL_RF_CLK_EN2_MASK       (0x8000U)
+#define APU_STATUS2_APU_WL_RF_CLK_EN2_SHIFT      (15U)
+/*! APU_WL_RF_CLK_EN2 - WLAN RFU1 clk enable */
+#define APU_STATUS2_APU_WL_RF_CLK_EN2(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_WL_RF_CLK_EN2_SHIFT)) & APU_STATUS2_APU_WL_RF_CLK_EN2_MASK)
+
+#define APU_STATUS2_APU_CAU_BT_ACTIVE_MASK       (0x10000U)
+#define APU_STATUS2_APU_CAU_BT_ACTIVE_SHIFT      (16U)
+/*! APU_CAU_BT_ACTIVE - APU CAU Bluetooth Active */
+#define APU_STATUS2_APU_CAU_BT_ACTIVE(x)         (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_CAU_BT_ACTIVE_SHIFT)) & APU_STATUS2_APU_CAU_BT_ACTIVE_MASK)
+
+#define APU_STATUS2_APU_SOC_CAU_LDO_XOSC_EN_MASK (0x20000U)
+#define APU_STATUS2_APU_SOC_CAU_LDO_XOSC_EN_SHIFT (17U)
+/*! APU_SOC_CAU_LDO_XOSC_EN - APU SoC CAU LOD XOSC Enable */
+#define APU_STATUS2_APU_SOC_CAU_LDO_XOSC_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_SOC_CAU_LDO_XOSC_EN_SHIFT)) & APU_STATUS2_APU_SOC_CAU_LDO_XOSC_EN_MASK)
+
+#define APU_STATUS2_PCIE_P_REQ_MASK              (0x40000U)
+#define APU_STATUS2_PCIE_P_REQ_SHIFT             (18U)
+/*! PCIE_P_REQ - PCIe P req */
+#define APU_STATUS2_PCIE_P_REQ(x)                (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_PCIE_P_REQ_SHIFT)) & APU_STATUS2_PCIE_P_REQ_MASK)
+
+#define APU_STATUS2_PCIE_XP_REQ_MASK             (0x80000U)
+#define APU_STATUS2_PCIE_XP_REQ_SHIFT            (19U)
+/*! PCIE_XP_REQ - PCIe XP req */
+#define APU_STATUS2_PCIE_XP_REQ(x)               (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_PCIE_XP_REQ_SHIFT)) & APU_STATUS2_PCIE_XP_REQ_MASK)
+
+#define APU_STATUS2_BCA_CLK_REQ_MASK             (0x100000U)
+#define APU_STATUS2_BCA_CLK_REQ_SHIFT            (20U)
+/*! BCA_CLK_REQ - BCA Clock Request */
+#define APU_STATUS2_BCA_CLK_REQ(x)               (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_BCA_CLK_REQ_SHIFT)) & APU_STATUS2_BCA_CLK_REQ_MASK)
+
+#define APU_STATUS2_BCA_CLK_EN_MASK              (0x200000U)
+#define APU_STATUS2_BCA_CLK_EN_SHIFT             (21U)
+/*! BCA_CLK_EN - APU BCA Clock Enable */
+#define APU_STATUS2_BCA_CLK_EN(x)                (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_BCA_CLK_EN_SHIFT)) & APU_STATUS2_BCA_CLK_EN_MASK)
+
+#define APU_STATUS2_BCA_SLNA_ON_MASK             (0x400000U)
+#define APU_STATUS2_BCA_SLNA_ON_SHIFT            (22U)
+/*! BCA_SLNA_ON - BCA SLNA On */
+#define APU_STATUS2_BCA_SLNA_ON(x)               (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_BCA_SLNA_ON_SHIFT)) & APU_STATUS2_BCA_SLNA_ON_MASK)
+
+#define APU_STATUS2_BT_CLK_REQ_MASK              (0x800000U)
+#define APU_STATUS2_BT_CLK_REQ_SHIFT             (23U)
+/*! BT_CLK_REQ - BT clk req */
+#define APU_STATUS2_BT_CLK_REQ(x)                (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_BT_CLK_REQ_SHIFT)) & APU_STATUS2_BT_CLK_REQ_MASK)
+
+#define APU_STATUS2_BT2_CLK_REQ_MASK             (0x1000000U)
+#define APU_STATUS2_BT2_CLK_REQ_SHIFT            (24U)
+/*! BT2_CLK_REQ - BT2 clk req */
+#define APU_STATUS2_BT2_CLK_REQ(x)               (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_BT2_CLK_REQ_SHIFT)) & APU_STATUS2_BT2_CLK_REQ_MASK)
+
+#define APU_STATUS2_APU_DVFS_CLK_SEL_MASK        (0x2000000U)
+#define APU_STATUS2_APU_DVFS_CLK_SEL_SHIFT       (25U)
+/*! APU_DVFS_CLK_SEL - APU DVFS Clock Select */
+#define APU_STATUS2_APU_DVFS_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_DVFS_CLK_SEL_SHIFT)) & APU_STATUS2_APU_DVFS_CLK_SEL_MASK)
+
+#define APU_STATUS2_APU_INTR_WLAN_WAKEUP2_MASK   (0x4000000U)
+#define APU_STATUS2_APU_INTR_WLAN_WAKEUP2_SHIFT  (26U)
+/*! APU_INTR_WLAN_WAKEUP2 - APU wlan2 wakeup interrupt */
+#define APU_STATUS2_APU_INTR_WLAN_WAKEUP2(x)     (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_INTR_WLAN_WAKEUP2_SHIFT)) & APU_STATUS2_APU_INTR_WLAN_WAKEUP2_MASK)
+
+#define APU_STATUS2_APU_INTR_WLAN_WAKEUP1_MASK   (0x8000000U)
+#define APU_STATUS2_APU_INTR_WLAN_WAKEUP1_SHIFT  (27U)
+/*! APU_INTR_WLAN_WAKEUP1 - APU wlan1 wakeup interrupt */
+#define APU_STATUS2_APU_INTR_WLAN_WAKEUP1(x)     (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_APU_INTR_WLAN_WAKEUP1_SHIFT)) & APU_STATUS2_APU_INTR_WLAN_WAKEUP1_MASK)
+
+#define APU_STATUS2_AMU1_CP15_SLEEP_MASK         (0x10000000U)
+#define APU_STATUS2_AMU1_CP15_SLEEP_SHIFT        (28U)
+/*! AMU1_CP15_SLEEP - CPU1 CP15 Sleep */
+#define APU_STATUS2_AMU1_CP15_SLEEP(x)           (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_AMU1_CP15_SLEEP_SHIFT)) & APU_STATUS2_AMU1_CP15_SLEEP_MASK)
+
+#define APU_STATUS2_AMU2_CP15_SLEEP_MASK         (0x20000000U)
+#define APU_STATUS2_AMU2_CP15_SLEEP_SHIFT        (29U)
+/*! AMU2_CP15_SLEEP - CPU2 CP15 Sleep */
+#define APU_STATUS2_AMU2_CP15_SLEEP(x)           (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_AMU2_CP15_SLEEP_SHIFT)) & APU_STATUS2_AMU2_CP15_SLEEP_MASK)
+
+#define APU_STATUS2_AMU3_CP15_SLEEP_MASK         (0x40000000U)
+#define APU_STATUS2_AMU3_CP15_SLEEP_SHIFT        (30U)
+/*! AMU3_CP15_SLEEP - CPU3 CP15 Sleep */
+#define APU_STATUS2_AMU3_CP15_SLEEP(x)           (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_AMU3_CP15_SLEEP_SHIFT)) & APU_STATUS2_AMU3_CP15_SLEEP_MASK)
+
+#define APU_STATUS2_CPU1_APU_PD_MASK             (0x80000000U)
+#define APU_STATUS2_CPU1_APU_PD_SHIFT            (31U)
+/*! CPU1_APU_PD - CPU1 to APU powerdown */
+#define APU_STATUS2_CPU1_APU_PD(x)               (((uint32_t)(((uint32_t)(x)) << APU_STATUS2_CPU1_APU_PD_SHIFT)) & APU_STATUS2_CPU1_APU_PD_MASK)
+/*! @} */
+
+/*! @name WLAN_PWR_CTRL_DLY2 - Wlan domain FSM Power Control Delay 2 */
+/*! @{ */
+
+#define APU_WLAN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_MASK (0xFFFFFFFFU)
+#define APU_WLAN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_SHIFT (0U)
+/*! PWR_CTRL_DLY2 - WLAN domain FSM power control delay 2 */
+#define APU_WLAN_PWR_CTRL_DLY2_PWR_CTRL_DLY2(x)  (((uint32_t)(((uint32_t)(x)) << APU_WLAN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_SHIFT)) & APU_WLAN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_MASK)
+/*! @} */
+
+/*! @name WL_CTRL - WLAN Control */
+/*! @{ */
+
+#define APU_WL_CTRL_WL_SLP_RDY_MASK              (0x1U)
+#define APU_WL_CTRL_WL_SLP_RDY_SHIFT             (0U)
+/*! WL_SLP_RDY - WLAN Sleep Ready */
+#define APU_WL_CTRL_WL_SLP_RDY(x)                (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_WL_SLP_RDY_SHIFT)) & APU_WL_CTRL_WL_SLP_RDY_MASK)
+
+#define APU_WL_CTRL_WL_SLP_RDYMASK_MASK          (0x2U)
+#define APU_WL_CTRL_WL_SLP_RDYMASK_SHIFT         (1U)
+/*! WL_SLP_RDYMASK - WLAN Sleep Ready Mask */
+#define APU_WL_CTRL_WL_SLP_RDYMASK(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_WL_SLP_RDYMASK_SHIFT)) & APU_WL_CTRL_WL_SLP_RDYMASK_MASK)
+
+#define APU_WL_CTRL_WL_SLP_RDY_FW_MASK           (0x4U)
+#define APU_WL_CTRL_WL_SLP_RDY_FW_SHIFT          (2U)
+/*! WL_SLP_RDY_FW - WLAN Sleep Ready Firmware */
+#define APU_WL_CTRL_WL_SLP_RDY_FW(x)             (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_WL_SLP_RDY_FW_SHIFT)) & APU_WL_CTRL_WL_SLP_RDY_FW_MASK)
+
+#define APU_WL_CTRL_IDLE2ISO_DLY_EN_MASK         (0x20U)
+#define APU_WL_CTRL_IDLE2ISO_DLY_EN_SHIFT        (5U)
+/*! IDLE2ISO_DLY_EN - Delay from idle to iso to ensure delay from bbud_non_udr_rst_b =0 to wlan_iso_en = 1 */
+#define APU_WL_CTRL_IDLE2ISO_DLY_EN(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_IDLE2ISO_DLY_EN_SHIFT)) & APU_WL_CTRL_IDLE2ISO_DLY_EN_MASK)
+
+#define APU_WL_CTRL_APU_WKUP_WLRF_RX_MASK        (0x40U)
+#define APU_WL_CTRL_APU_WKUP_WLRF_RX_SHIFT       (6U)
+/*! APU_WKUP_WLRF_RX - APU Wakeup WL RF Rx */
+#define APU_WL_CTRL_APU_WKUP_WLRF_RX(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_APU_WKUP_WLRF_RX_SHIFT)) & APU_WL_CTRL_APU_WKUP_WLRF_RX_MASK)
+
+#define APU_WL_CTRL_USE_WL_INTR_SLP_MASK         (0x80U)
+#define APU_WL_CTRL_USE_WL_INTR_SLP_SHIFT        (7U)
+/*! USE_WL_INTR_SLP - Use WLAN Interrupt Sleep */
+#define APU_WL_CTRL_USE_WL_INTR_SLP(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_USE_WL_INTR_SLP_SHIFT)) & APU_WL_CTRL_USE_WL_INTR_SLP_MASK)
+
+#define APU_WL_CTRL_WL_USE_NOM_PWR_BYP_MASK      (0x200U)
+#define APU_WL_CTRL_WL_USE_NOM_PWR_BYP_SHIFT     (9U)
+/*! WL_USE_NOM_PWR_BYP - WLAN Use Nominal Power Bypass */
+#define APU_WL_CTRL_WL_USE_NOM_PWR_BYP(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_WL_USE_NOM_PWR_BYP_SHIFT)) & APU_WL_CTRL_WL_USE_NOM_PWR_BYP_MASK)
+
+#define APU_WL_CTRL_USE_WL_PWR_RDY_FOR_WLRF_CLK_MASK (0x400U)
+#define APU_WL_CTRL_USE_WL_PWR_RDY_FOR_WLRF_CLK_SHIFT (10U)
+/*! USE_WL_PWR_RDY_FOR_WLRF_CLK - Use WLAN Power Ready for WL RF Clock */
+#define APU_WL_CTRL_USE_WL_PWR_RDY_FOR_WLRF_CLK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_USE_WL_PWR_RDY_FOR_WLRF_CLK_SHIFT)) & APU_WL_CTRL_USE_WL_PWR_RDY_FOR_WLRF_CLK_MASK)
+
+#define APU_WL_CTRL_APU_FW_RST_PE_MASK           (0x8000U)
+#define APU_WL_CTRL_APU_FW_RST_PE_SHIFT          (15U)
+/*! APU_FW_RST_PE - APU FW Reset PE */
+#define APU_WL_CTRL_APU_FW_RST_PE(x)             (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_APU_FW_RST_PE_SHIFT)) & APU_WL_CTRL_APU_FW_RST_PE_MASK)
+
+#define APU_WL_CTRL_APU_TSF_UPD_CNT_MASK         (0x1F0000U)
+#define APU_WL_CTRL_APU_TSF_UPD_CNT_SHIFT        (16U)
+/*! APU_TSF_UPD_CNT - APU TSF Update Count */
+#define APU_WL_CTRL_APU_TSF_UPD_CNT(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_APU_TSF_UPD_CNT_SHIFT)) & APU_WL_CTRL_APU_TSF_UPD_CNT_MASK)
+
+#define APU_WL_CTRL_APU_TSF_AUTO_UPDATE_MASK     (0x200000U)
+#define APU_WL_CTRL_APU_TSF_AUTO_UPDATE_SHIFT    (21U)
+/*! APU_TSF_AUTO_UPDATE - APU TSF Auto Update */
+#define APU_WL_CTRL_APU_TSF_AUTO_UPDATE(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_APU_TSF_AUTO_UPDATE_SHIFT)) & APU_WL_CTRL_APU_TSF_AUTO_UPDATE_MASK)
+
+#define APU_WL_CTRL_APU_WLAN_RF_MUX_SEL_MASK     (0x400000U)
+#define APU_WL_CTRL_APU_WLAN_RF_MUX_SEL_SHIFT    (22U)
+/*! APU_WLAN_RF_MUX_SEL - APU WLAN RF Mux Select */
+#define APU_WL_CTRL_APU_WLAN_RF_MUX_SEL(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_APU_WLAN_RF_MUX_SEL_SHIFT)) & APU_WL_CTRL_APU_WLAN_RF_MUX_SEL_MASK)
+
+#define APU_WL_CTRL_FW_FORCE_WL_PWRUP_MASK       (0x1000000U)
+#define APU_WL_CTRL_FW_FORCE_WL_PWRUP_SHIFT      (24U)
+/*! FW_FORCE_WL_PWRUP - FW Force WLAN Powerup */
+#define APU_WL_CTRL_FW_FORCE_WL_PWRUP(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_FW_FORCE_WL_PWRUP_SHIFT)) & APU_WL_CTRL_FW_FORCE_WL_PWRUP_MASK)
+
+#define APU_WL_CTRL_WLAN_USE_UNSYNC_PWR_LVL_MASK (0x2000000U)
+#define APU_WL_CTRL_WLAN_USE_UNSYNC_PWR_LVL_SHIFT (25U)
+/*! WLAN_USE_UNSYNC_PWR_LVL - WLAN Use Unsync Power Level */
+#define APU_WL_CTRL_WLAN_USE_UNSYNC_PWR_LVL(x)   (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_WLAN_USE_UNSYNC_PWR_LVL_SHIFT)) & APU_WL_CTRL_WLAN_USE_UNSYNC_PWR_LVL_MASK)
+
+#define APU_WL_CTRL_WL_HOST_SLP_RDY_MASK         (0x80000000U)
+#define APU_WL_CTRL_WL_HOST_SLP_RDY_SHIFT        (31U)
+/*! WL_HOST_SLP_RDY - WLAN Host Sleep Ready */
+#define APU_WL_CTRL_WL_HOST_SLP_RDY(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL_WL_HOST_SLP_RDY_SHIFT)) & APU_WL_CTRL_WL_HOST_SLP_RDY_MASK)
+/*! @} */
+
+/*! @name WL_WKUP_MASK - WLAN Wakeup Mask */
+/*! @{ */
+
+#define APU_WL_WKUP_MASK_WL_BCN_TIMER_WKUP_MASK_MASK (0x1U)
+#define APU_WL_WKUP_MASK_WL_BCN_TIMER_WKUP_MASK_SHIFT (0U)
+/*! WL_BCN_TIMER_WKUP_MASK - WLAN Beacon Timer Wakeup Mask */
+#define APU_WL_WKUP_MASK_WL_BCN_TIMER_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_WL_BCN_TIMER_WKUP_MASK_SHIFT)) & APU_WL_WKUP_MASK_WL_BCN_TIMER_WKUP_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_BBUD_T2_PLL_REQ_MASK_MASK (0x2U)
+#define APU_WL_WKUP_MASK_BBUD_T2_PLL_REQ_MASK_SHIFT (1U)
+/*! BBUD_T2_PLL_REQ_MASK - BBUD T2 PLL Request Mask */
+#define APU_WL_WKUP_MASK_BBUD_T2_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_BBUD_T2_PLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK_BBUD_T2_PLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_WL_RF_PLL_REQ_MASK_MASK (0x4U)
+#define APU_WL_WKUP_MASK_WL_RF_PLL_REQ_MASK_SHIFT (2U)
+/*! WL_RF_PLL_REQ_MASK - WLAN RF PLL Request Mask */
+#define APU_WL_WKUP_MASK_WL_RF_PLL_REQ_MASK(x)   (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_WL_RF_PLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK_WL_RF_PLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_BCA_MWS_WKUP_XP_MASK_MASK (0x8U)
+#define APU_WL_WKUP_MASK_BCA_MWS_WKUP_XP_MASK_SHIFT (3U)
+/*! BCA_MWS_WKUP_XP_MASK - BCA MWS Wakeup XP Mask */
+#define APU_WL_WKUP_MASK_BCA_MWS_WKUP_XP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_BCA_MWS_WKUP_XP_MASK_SHIFT)) & APU_WL_WKUP_MASK_BCA_MWS_WKUP_XP_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_WL_RF_PLL_DYNPLL_REQ_MASK_MASK (0x100U)
+#define APU_WL_WKUP_MASK_WL_RF_PLL_DYNPLL_REQ_MASK_SHIFT (8U)
+/*! WL_RF_PLL_DYNPLL_REQ_MASK - When mask = 0, wl_rf_pll_req is treated as pll_req */
+#define APU_WL_WKUP_MASK_WL_RF_PLL_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_WL_RF_PLL_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK_WL_RF_PLL_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_WL_HOST_DYNPLL_REQ_MASK_MASK (0x200U)
+#define APU_WL_WKUP_MASK_WL_HOST_DYNPLL_REQ_MASK_SHIFT (9U)
+/*! WL_HOST_DYNPLL_REQ_MASK - When mask = 0, wlan_host_wkup is treated as pll_req */
+#define APU_WL_WKUP_MASK_WL_HOST_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_WL_HOST_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK_WL_HOST_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_WL_TIMER_DYNPLL_REQ_MASK_MASK (0x400U)
+#define APU_WL_WKUP_MASK_WL_TIMER_DYNPLL_REQ_MASK_SHIFT (10U)
+/*! WL_TIMER_DYNPLL_REQ_MASK - When mask = 0, wlan_timer_xpp req is treated as pll_req */
+#define APU_WL_WKUP_MASK_WL_TIMER_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_WL_TIMER_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK_WL_TIMER_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_WL_SLP_RDY_DYNPLL_REQ_MASK_MASK (0x800U)
+#define APU_WL_WKUP_MASK_WL_SLP_RDY_DYNPLL_REQ_MASK_SHIFT (11U)
+/*! WL_SLP_RDY_DYNPLL_REQ_MASK - When mask = 0, !wl_slp_rdy is treated as pll_req */
+#define APU_WL_WKUP_MASK_WL_SLP_RDY_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_WL_SLP_RDY_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK_WL_SLP_RDY_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_IHB_WL_XPP_DYNPLL_REQ_MASK_MASK (0x1000U)
+#define APU_WL_WKUP_MASK_IHB_WL_XPP_DYNPLL_REQ_MASK_SHIFT (12U)
+/*! IHB_WL_XPP_DYNPLL_REQ_MASK - When mask = 0, ihb_wl_xpp_req is treated as pll_req */
+#define APU_WL_WKUP_MASK_IHB_WL_XPP_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_IHB_WL_XPP_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK_IHB_WL_XPP_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK_WL_HOST_MAP_MASK        (0xFFFF0000U)
+#define APU_WL_WKUP_MASK_WL_HOST_MAP_SHIFT       (16U)
+/*! WL_HOST_MAP - WLAN Host Map */
+#define APU_WL_WKUP_MASK_WL_HOST_MAP(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK_WL_HOST_MAP_SHIFT)) & APU_WL_WKUP_MASK_WL_HOST_MAP_MASK)
+/*! @} */
+
+/*! @name WL_STATUS - WLAN Status */
+/*! @{ */
+
+#define APU_WL_STATUS_APU_MAC_CLK_EN_MASK        (0x1U)
+#define APU_WL_STATUS_APU_MAC_CLK_EN_SHIFT       (0U)
+/*! APU_MAC_CLK_EN - APU MAC Clock Enable */
+#define APU_WL_STATUS_APU_MAC_CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_MAC_CLK_EN_SHIFT)) & APU_WL_STATUS_APU_MAC_CLK_EN_MASK)
+
+#define APU_WL_STATUS_APU_BBUD_CLK_EN_MASK       (0x2U)
+#define APU_WL_STATUS_APU_BBUD_CLK_EN_SHIFT      (1U)
+/*! APU_BBUD_CLK_EN - APU BBUD Clock Enable */
+#define APU_WL_STATUS_APU_BBUD_CLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_BBUD_CLK_EN_SHIFT)) & APU_WL_STATUS_APU_BBUD_CLK_EN_MASK)
+
+#define APU_WL_STATUS_APU_WL_RF_CLK_EN_MASK      (0x4U)
+#define APU_WL_STATUS_APU_WL_RF_CLK_EN_SHIFT     (2U)
+/*! APU_WL_RF_CLK_EN - APU WLAN Ref Clock Enable */
+#define APU_WL_STATUS_APU_WL_RF_CLK_EN(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WL_RF_CLK_EN_SHIFT)) & APU_WL_STATUS_APU_WL_RF_CLK_EN_MASK)
+
+#define APU_WL_STATUS_APU_WL_SLP_RDY_AFTER_MASK_MASK (0x8U)
+#define APU_WL_STATUS_APU_WL_SLP_RDY_AFTER_MASK_SHIFT (3U)
+/*! APU_WL_SLP_RDY_AFTER_MASK - APU WLAN Sleep Ready After Mask */
+#define APU_WL_STATUS_APU_WL_SLP_RDY_AFTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WL_SLP_RDY_AFTER_MASK_SHIFT)) & APU_WL_STATUS_APU_WL_SLP_RDY_AFTER_MASK_MASK)
+
+#define APU_WL_STATUS_APU_WL_RF_CTRL_MASK        (0x30U)
+#define APU_WL_STATUS_APU_WL_RF_CTRL_SHIFT       (4U)
+/*! APU_WL_RF_CTRL - APU WLAN RF Control for PE1/PE2 */
+#define APU_WL_STATUS_APU_WL_RF_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WL_RF_CTRL_SHIFT)) & APU_WL_STATUS_APU_WL_RF_CTRL_MASK)
+
+#define APU_WL_STATUS_APU_PLL1_EN_MASK           (0x40U)
+#define APU_WL_STATUS_APU_PLL1_EN_SHIFT          (6U)
+/*! APU_PLL1_EN - APU PLL1 Enable */
+#define APU_WL_STATUS_APU_PLL1_EN(x)             (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_PLL1_EN_SHIFT)) & APU_WL_STATUS_APU_PLL1_EN_MASK)
+
+#define APU_WL_STATUS_APU_PLL3_EN_MASK           (0x80U)
+#define APU_WL_STATUS_APU_PLL3_EN_SHIFT          (7U)
+/*! APU_PLL3_EN - APU PLL3 Enable */
+#define APU_WL_STATUS_APU_PLL3_EN(x)             (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_PLL3_EN_SHIFT)) & APU_WL_STATUS_APU_PLL3_EN_MASK)
+
+#define APU_WL_STATUS_BCA_MWS_WKUP_XP_MASK       (0x100U)
+#define APU_WL_STATUS_BCA_MWS_WKUP_XP_SHIFT      (8U)
+/*! BCA_MWS_WKUP_XP - BCA MWS Wakeup XP */
+#define APU_WL_STATUS_BCA_MWS_WKUP_XP(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_BCA_MWS_WKUP_XP_SHIFT)) & APU_WL_STATUS_BCA_MWS_WKUP_XP_MASK)
+
+#define APU_WL_STATUS_APU_RTDP_WU_RSTB_MASK      (0x200U)
+#define APU_WL_STATUS_APU_RTDP_WU_RSTB_SHIFT     (9U)
+/*! APU_RTDP_WU_RSTB - APU RTDP WU RSTb */
+#define APU_WL_STATUS_APU_RTDP_WU_RSTB(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_RTDP_WU_RSTB_SHIFT)) & APU_WL_STATUS_APU_RTDP_WU_RSTB_MASK)
+
+#define APU_WL_STATUS_APU_BBUD_NON_UDR_RST_B_MASK (0x400U)
+#define APU_WL_STATUS_APU_BBUD_NON_UDR_RST_B_SHIFT (10U)
+/*! APU_BBUD_NON_UDR_RST_B - APU BBUD non-UDR RSTb */
+#define APU_WL_STATUS_APU_BBUD_NON_UDR_RST_B(x)  (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_BBUD_NON_UDR_RST_B_SHIFT)) & APU_WL_STATUS_APU_BBUD_NON_UDR_RST_B_MASK)
+
+#define APU_WL_STATUS_APU_WL_ST_MASK             (0xF000U)
+#define APU_WL_STATUS_APU_WL_ST_SHIFT            (12U)
+/*! APU_WL_ST - APU WLAN St */
+#define APU_WL_STATUS_APU_WL_ST(x)               (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WL_ST_SHIFT)) & APU_WL_STATUS_APU_WL_ST_MASK)
+
+#define APU_WL_STATUS_APU_WLAN_SWITCH_PD_MASK    (0x10000U)
+#define APU_WL_STATUS_APU_WLAN_SWITCH_PD_SHIFT   (16U)
+/*! APU_WLAN_SWITCH_PD - APU WLAN Switch Pd */
+#define APU_WL_STATUS_APU_WLAN_SWITCH_PD(x)      (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WLAN_SWITCH_PD_SHIFT)) & APU_WL_STATUS_APU_WLAN_SWITCH_PD_MASK)
+
+#define APU_WL_STATUS_APU_WLAN_UDR_FIREWALL_B_MASK (0x20000U)
+#define APU_WL_STATUS_APU_WLAN_UDR_FIREWALL_B_SHIFT (17U)
+/*! APU_WLAN_UDR_FIREWALL_B - APU WLAN UDR Firewall b */
+#define APU_WL_STATUS_APU_WLAN_UDR_FIREWALL_B(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WLAN_UDR_FIREWALL_B_SHIFT)) & APU_WL_STATUS_APU_WLAN_UDR_FIREWALL_B_MASK)
+
+#define APU_WL_STATUS_APU_WLAN_CLK_DIV_RSTB_MASK (0x40000U)
+#define APU_WL_STATUS_APU_WLAN_CLK_DIV_RSTB_SHIFT (18U)
+/*! APU_WLAN_CLK_DIV_RSTB - APU WLAN Clock Div RSTb */
+#define APU_WL_STATUS_APU_WLAN_CLK_DIV_RSTB(x)   (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WLAN_CLK_DIV_RSTB_SHIFT)) & APU_WL_STATUS_APU_WLAN_CLK_DIV_RSTB_MASK)
+
+#define APU_WL_STATUS_APU_WLAN_ISO_EN_MASK       (0x80000U)
+#define APU_WL_STATUS_APU_WLAN_ISO_EN_SHIFT      (19U)
+/*! APU_WLAN_ISO_EN - APU WLAN ISO Enable */
+#define APU_WL_STATUS_APU_WLAN_ISO_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WLAN_ISO_EN_SHIFT)) & APU_WL_STATUS_APU_WLAN_ISO_EN_MASK)
+
+#define APU_WL_STATUS_APU_WLAN_SRAM_PD_MASK      (0x100000U)
+#define APU_WL_STATUS_APU_WLAN_SRAM_PD_SHIFT     (20U)
+/*! APU_WLAN_SRAM_PD - APU WLAN SRAM Enable */
+#define APU_WL_STATUS_APU_WLAN_SRAM_PD(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_APU_WLAN_SRAM_PD_SHIFT)) & APU_WL_STATUS_APU_WLAN_SRAM_PD_MASK)
+
+#define APU_WL_STATUS_WLAN_VOL_REACHED_MASK      (0x200000U)
+#define APU_WL_STATUS_WLAN_VOL_REACHED_SHIFT     (21U)
+/*! WLAN_VOL_REACHED - WLAN Volume Reached */
+#define APU_WL_STATUS_WLAN_VOL_REACHED(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_WLAN_VOL_REACHED_SHIFT)) & APU_WL_STATUS_WLAN_VOL_REACHED_MASK)
+
+#define APU_WL_STATUS_SOC_VOL_REACHED_MASK       (0x400000U)
+#define APU_WL_STATUS_SOC_VOL_REACHED_SHIFT      (22U)
+/*! SOC_VOL_REACHED - SoC Volume Reached */
+#define APU_WL_STATUS_SOC_VOL_REACHED(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_SOC_VOL_REACHED_SHIFT)) & APU_WL_STATUS_SOC_VOL_REACHED_MASK)
+
+#define APU_WL_STATUS_WL_PWR_RDY_MASK            (0x800000U)
+#define APU_WL_STATUS_WL_PWR_RDY_SHIFT           (23U)
+/*! WL_PWR_RDY - WLAN Power Ready */
+#define APU_WL_STATUS_WL_PWR_RDY(x)              (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_WL_PWR_RDY_SHIFT)) & APU_WL_STATUS_WL_PWR_RDY_MASK)
+
+#define APU_WL_STATUS_WL_HOST_INTR_REF_MASK      (0x1000000U)
+#define APU_WL_STATUS_WL_HOST_INTR_REF_SHIFT     (24U)
+/*! WL_HOST_INTR_REF - WLAN Host Interrupt Reference */
+#define APU_WL_STATUS_WL_HOST_INTR_REF(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_WL_HOST_INTR_REF_SHIFT)) & APU_WL_STATUS_WL_HOST_INTR_REF_MASK)
+
+#define APU_WL_STATUS_WLAN_HOST_WKUP_MASK        (0x2000000U)
+#define APU_WL_STATUS_WLAN_HOST_WKUP_SHIFT       (25U)
+/*! WLAN_HOST_WKUP - WLAN Host Wakeup */
+#define APU_WL_STATUS_WLAN_HOST_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_WLAN_HOST_WKUP_SHIFT)) & APU_WL_STATUS_WLAN_HOST_WKUP_MASK)
+
+#define APU_WL_STATUS_WL_TIMER_INTR_MASK         (0x4000000U)
+#define APU_WL_STATUS_WL_TIMER_INTR_SHIFT        (26U)
+/*! WL_TIMER_INTR - WLAN Timer Interrupt */
+#define APU_WL_STATUS_WL_TIMER_INTR(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_WL_TIMER_INTR_SHIFT)) & APU_WL_STATUS_WL_TIMER_INTR_MASK)
+
+#define APU_WL_STATUS_TIMER_XPP_WAKEUP_MASK      (0x8000000U)
+#define APU_WL_STATUS_TIMER_XPP_WAKEUP_SHIFT     (27U)
+/*! TIMER_XPP_WAKEUP - Timer XPP Wakeup */
+#define APU_WL_STATUS_TIMER_XPP_WAKEUP(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_TIMER_XPP_WAKEUP_SHIFT)) & APU_WL_STATUS_TIMER_XPP_WAKEUP_MASK)
+
+#define APU_WL_STATUS_TIMER_WAKEUP_MASK          (0x10000000U)
+#define APU_WL_STATUS_TIMER_WAKEUP_SHIFT         (28U)
+/*! TIMER_WAKEUP - Timer Wakeup */
+#define APU_WL_STATUS_TIMER_WAKEUP(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_TIMER_WAKEUP_SHIFT)) & APU_WL_STATUS_TIMER_WAKEUP_MASK)
+
+#define APU_WL_STATUS_WLRF_PLL_REQ_MASK          (0x20000000U)
+#define APU_WL_STATUS_WLRF_PLL_REQ_SHIFT         (29U)
+/*! WLRF_PLL_REQ - WL RF PLL Request */
+#define APU_WL_STATUS_WLRF_PLL_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_WLRF_PLL_REQ_SHIFT)) & APU_WL_STATUS_WLRF_PLL_REQ_MASK)
+
+#define APU_WL_STATUS_BBUD_T2_PLL_REQ_MASK       (0x40000000U)
+#define APU_WL_STATUS_BBUD_T2_PLL_REQ_SHIFT      (30U)
+/*! BBUD_T2_PLL_REQ - BBUD T2 PLL Request */
+#define APU_WL_STATUS_BBUD_T2_PLL_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_BBUD_T2_PLL_REQ_SHIFT)) & APU_WL_STATUS_BBUD_T2_PLL_REQ_MASK)
+
+#define APU_WL_STATUS_BCA_CLK_REQ_MASK           (0x80000000U)
+#define APU_WL_STATUS_BCA_CLK_REQ_SHIFT          (31U)
+/*! BCA_CLK_REQ - BCA Clock Request */
+#define APU_WL_STATUS_BCA_CLK_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS_BCA_CLK_REQ_SHIFT)) & APU_WL_STATUS_BCA_CLK_REQ_MASK)
+/*! @} */
+
+/*! @name WL_ALARM_RD - WLAN Alarm Readback */
+/*! @{ */
+
+#define APU_WL_ALARM_RD_APU_WL_ALARM_RD_MASK     (0xFFFFFFFFU)
+#define APU_WL_ALARM_RD_APU_WL_ALARM_RD_SHIFT    (0U)
+/*! APU_WL_ALARM_RD - reads back current beacon timer alarm value */
+#define APU_WL_ALARM_RD_APU_WL_ALARM_RD(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_ALARM_RD_APU_WL_ALARM_RD_SHIFT)) & APU_WL_ALARM_RD_APU_WL_ALARM_RD_MASK)
+/*! @} */
+
+/*! @name WL_BCN_XP_ALARM - WLAN Beacon Alarm */
+/*! @{ */
+
+#define APU_WL_BCN_XP_ALARM_WL_BCN_XP_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_BCN_XP_ALARM_WL_BCN_XP_ALARM_SHIFT (0U)
+/*! WL_BCN_XP_ALARM - number of sleep clocks until WLAN beacon timer requests for reference clock and power */
+#define APU_WL_BCN_XP_ALARM_WL_BCN_XP_ALARM(x)   (((uint32_t)(((uint32_t)(x)) << APU_WL_BCN_XP_ALARM_WL_BCN_XP_ALARM_SHIFT)) & APU_WL_BCN_XP_ALARM_WL_BCN_XP_ALARM_MASK)
+/*! @} */
+
+/*! @name WL_BCN_INTR_ALARM - WLAN Beacon Interrupt Alarm */
+/*! @{ */
+
+#define APU_WL_BCN_INTR_ALARM_WL_BCN_INTR_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_BCN_INTR_ALARM_WL_BCN_INTR_ALARM_SHIFT (0U)
+/*! WL_BCN_INTR_ALARM - number of ref clocks after WLAN beacon timer request to firmware wakeup */
+#define APU_WL_BCN_INTR_ALARM_WL_BCN_INTR_ALARM(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_BCN_INTR_ALARM_WL_BCN_INTR_ALARM_SHIFT)) & APU_WL_BCN_INTR_ALARM_WL_BCN_INTR_ALARM_MASK)
+/*! @} */
+
+/*! @name WL_HOST_INTR_ALARM - WLAN Host Interrupt Alarm */
+/*! @{ */
+
+#define APU_WL_HOST_INTR_ALARM_WL_HOST_INTR_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_HOST_INTR_ALARM_WL_HOST_INTR_ALARM_SHIFT (0U)
+/*! WL_HOST_INTR_ALARM - number of ref clocks after WLAN host request to firmware wakeup */
+#define APU_WL_HOST_INTR_ALARM_WL_HOST_INTR_ALARM(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_HOST_INTR_ALARM_WL_HOST_INTR_ALARM_SHIFT)) & APU_WL_HOST_INTR_ALARM_WL_HOST_INTR_ALARM_MASK)
+/*! @} */
+
+/*! @name WL_BCN_PLL_ALARM - WLAN Beacon PLL Alarm */
+/*! @{ */
+
+#define APU_WL_BCN_PLL_ALARM_WL_BCN_PLL_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_BCN_PLL_ALARM_WL_BCN_PLL_ALARM_SHIFT (0U)
+/*! WL_BCN_PLL_ALARM - number of sleep clocks until WLAN beacon timer requests for reference clock, power, and PLL */
+#define APU_WL_BCN_PLL_ALARM_WL_BCN_PLL_ALARM(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_BCN_PLL_ALARM_WL_BCN_PLL_ALARM_SHIFT)) & APU_WL_BCN_PLL_ALARM_WL_BCN_PLL_ALARM_MASK)
+/*! @} */
+
+/*! @name TSF_REF_FACTOR - TSF Reference Factor */
+/*! @{ */
+
+#define APU_TSF_REF_FACTOR_TSF_REF_FACTOR_MASK   (0x7FFFFU)
+#define APU_TSF_REF_FACTOR_TSF_REF_FACTOR_SHIFT  (0U)
+/*! TSF_REF_FACTOR - number of 1us in 1 reference clock */
+#define APU_TSF_REF_FACTOR_TSF_REF_FACTOR(x)     (((uint32_t)(((uint32_t)(x)) << APU_TSF_REF_FACTOR_TSF_REF_FACTOR_SHIFT)) & APU_TSF_REF_FACTOR_TSF_REF_FACTOR_MASK)
+/*! @} */
+
+/*! @name TSF_SLEEP_FACTOR - TSF Sleep Factor */
+/*! @{ */
+
+#define APU_TSF_SLEEP_FACTOR_TSF_SLEEP_FACTOR_MASK (0xFFFFFFFU)
+#define APU_TSF_SLEEP_FACTOR_TSF_SLEEP_FACTOR_SHIFT (0U)
+/*! TSF_SLEEP_FACTOR - number of 1us in 1 sleep clock */
+#define APU_TSF_SLEEP_FACTOR_TSF_SLEEP_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << APU_TSF_SLEEP_FACTOR_TSF_SLEEP_FACTOR_SHIFT)) & APU_TSF_SLEEP_FACTOR_TSF_SLEEP_FACTOR_MASK)
+/*! @} */
+
+/*! @name BBUD_UDR_ISO_CNT - BBUD UDR ISO Count */
+/*! @{ */
+
+#define APU_BBUD_UDR_ISO_CNT_BBUD_UDR_ASSERT_CNT_MASK (0x1FFFU)
+#define APU_BBUD_UDR_ISO_CNT_BBUD_UDR_ASSERT_CNT_SHIFT (0U)
+/*! BBUD_UDR_ASSERT_CNT - number of reference clocks before bbud_non_udr_rst de-assertion after bbud_clk_en is asserted */
+#define APU_BBUD_UDR_ISO_CNT_BBUD_UDR_ASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << APU_BBUD_UDR_ISO_CNT_BBUD_UDR_ASSERT_CNT_SHIFT)) & APU_BBUD_UDR_ISO_CNT_BBUD_UDR_ASSERT_CNT_MASK)
+
+#define APU_BBUD_UDR_ISO_CNT_BBUD_CLK_ASSERT_CNT_MASK (0x1FFF0000U)
+#define APU_BBUD_UDR_ISO_CNT_BBUD_CLK_ASSERT_CNT_SHIFT (16U)
+/*! BBUD_CLK_ASSERT_CNT - number of reference clocks before bbud_iso_en de-assertion after bbud_non_udr_rst de-asserts */
+#define APU_BBUD_UDR_ISO_CNT_BBUD_CLK_ASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << APU_BBUD_UDR_ISO_CNT_BBUD_CLK_ASSERT_CNT_SHIFT)) & APU_BBUD_UDR_ISO_CNT_BBUD_CLK_ASSERT_CNT_MASK)
+/*! @} */
+
+/*! @name WL_DVFS_CTRL - WLAN DVFS Control */
+/*! @{ */
+
+#define APU_WL_DVFS_CTRL_WLAN_VOL_VAL_MASK       (0x7FU)
+#define APU_WL_DVFS_CTRL_WLAN_VOL_VAL_SHIFT      (0U)
+/*! WLAN_VOL_VAL - WLAN Vol Value */
+#define APU_WL_DVFS_CTRL_WLAN_VOL_VAL(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_DVFS_CTRL_WLAN_VOL_VAL_SHIFT)) & APU_WL_DVFS_CTRL_WLAN_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name WL_CTRL2 - WLAN Control 2 */
+/*! @{ */
+
+#define APU_WL_CTRL2_WL_SLP_RDY_MASK             (0x1U)
+#define APU_WL_CTRL2_WL_SLP_RDY_SHIFT            (0U)
+/*! WL_SLP_RDY - WLAN Sleep Ready */
+#define APU_WL_CTRL2_WL_SLP_RDY(x)               (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_WL_SLP_RDY_SHIFT)) & APU_WL_CTRL2_WL_SLP_RDY_MASK)
+
+#define APU_WL_CTRL2_WL_SLP_RDYMASK_MASK         (0x2U)
+#define APU_WL_CTRL2_WL_SLP_RDYMASK_SHIFT        (1U)
+/*! WL_SLP_RDYMASK - WLAN Sleep Ready Mask */
+#define APU_WL_CTRL2_WL_SLP_RDYMASK(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_WL_SLP_RDYMASK_SHIFT)) & APU_WL_CTRL2_WL_SLP_RDYMASK_MASK)
+
+#define APU_WL_CTRL2_WL_SLP_RDY_FW_MASK          (0x4U)
+#define APU_WL_CTRL2_WL_SLP_RDY_FW_SHIFT         (2U)
+/*! WL_SLP_RDY_FW - WLAN Sleep Ready Firmware */
+#define APU_WL_CTRL2_WL_SLP_RDY_FW(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_WL_SLP_RDY_FW_SHIFT)) & APU_WL_CTRL2_WL_SLP_RDY_FW_MASK)
+
+#define APU_WL_CTRL2_IDLE2ISO_DLY_EN_MASK        (0x20U)
+#define APU_WL_CTRL2_IDLE2ISO_DLY_EN_SHIFT       (5U)
+/*! IDLE2ISO_DLY_EN - Delay from idle to iso to ensure delay from bbud_non_udr_rst_b =0 to wlan_iso_en = 1 */
+#define APU_WL_CTRL2_IDLE2ISO_DLY_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_IDLE2ISO_DLY_EN_SHIFT)) & APU_WL_CTRL2_IDLE2ISO_DLY_EN_MASK)
+
+#define APU_WL_CTRL2_APU_WKUP_WLRF_RX_MASK       (0x40U)
+#define APU_WL_CTRL2_APU_WKUP_WLRF_RX_SHIFT      (6U)
+/*! APU_WKUP_WLRF_RX - APU Wakeup WL RF Rx */
+#define APU_WL_CTRL2_APU_WKUP_WLRF_RX(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_APU_WKUP_WLRF_RX_SHIFT)) & APU_WL_CTRL2_APU_WKUP_WLRF_RX_MASK)
+
+#define APU_WL_CTRL2_USE_WL_INTR_SLP_MASK        (0x80U)
+#define APU_WL_CTRL2_USE_WL_INTR_SLP_SHIFT       (7U)
+/*! USE_WL_INTR_SLP - Use WLAN Interrupt Sleep */
+#define APU_WL_CTRL2_USE_WL_INTR_SLP(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_USE_WL_INTR_SLP_SHIFT)) & APU_WL_CTRL2_USE_WL_INTR_SLP_MASK)
+
+#define APU_WL_CTRL2_WL_USE_NOM_PWR_BYP_MASK     (0x200U)
+#define APU_WL_CTRL2_WL_USE_NOM_PWR_BYP_SHIFT    (9U)
+/*! WL_USE_NOM_PWR_BYP - Use nom_pwr_lvl from dvfs for wl_pwr_lvl_reached */
+#define APU_WL_CTRL2_WL_USE_NOM_PWR_BYP(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_WL_USE_NOM_PWR_BYP_SHIFT)) & APU_WL_CTRL2_WL_USE_NOM_PWR_BYP_MASK)
+
+#define APU_WL_CTRL2_USE_WL_PWR_RDY_FOR_WLRF_CLK_MASK (0x400U)
+#define APU_WL_CTRL2_USE_WL_PWR_RDY_FOR_WLRF_CLK_SHIFT (10U)
+/*! USE_WL_PWR_RDY_FOR_WLRF_CLK - Use WLAN Power Ready for WL RF Clock */
+#define APU_WL_CTRL2_USE_WL_PWR_RDY_FOR_WLRF_CLK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_USE_WL_PWR_RDY_FOR_WLRF_CLK_SHIFT)) & APU_WL_CTRL2_USE_WL_PWR_RDY_FOR_WLRF_CLK_MASK)
+
+#define APU_WL_CTRL2_APU_FW_RST_PE_MASK          (0x8000U)
+#define APU_WL_CTRL2_APU_FW_RST_PE_SHIFT         (15U)
+/*! APU_FW_RST_PE - APU FW Reset PE */
+#define APU_WL_CTRL2_APU_FW_RST_PE(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_APU_FW_RST_PE_SHIFT)) & APU_WL_CTRL2_APU_FW_RST_PE_MASK)
+
+#define APU_WL_CTRL2_APU_TSF_UPD_CNT_MASK        (0x1F0000U)
+#define APU_WL_CTRL2_APU_TSF_UPD_CNT_SHIFT       (16U)
+/*! APU_TSF_UPD_CNT - APU TSF Update Count */
+#define APU_WL_CTRL2_APU_TSF_UPD_CNT(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_APU_TSF_UPD_CNT_SHIFT)) & APU_WL_CTRL2_APU_TSF_UPD_CNT_MASK)
+
+#define APU_WL_CTRL2_APU_TSF_AUTO_UPDATE_MASK    (0x200000U)
+#define APU_WL_CTRL2_APU_TSF_AUTO_UPDATE_SHIFT   (21U)
+/*! APU_TSF_AUTO_UPDATE - APU TSF Auto Update */
+#define APU_WL_CTRL2_APU_TSF_AUTO_UPDATE(x)      (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_APU_TSF_AUTO_UPDATE_SHIFT)) & APU_WL_CTRL2_APU_TSF_AUTO_UPDATE_MASK)
+
+#define APU_WL_CTRL2_APU_WLAN_RF_MUX_SEL_MASK    (0x400000U)
+#define APU_WL_CTRL2_APU_WLAN_RF_MUX_SEL_SHIFT   (22U)
+/*! APU_WLAN_RF_MUX_SEL - APU WLAN RF Mux Select */
+#define APU_WL_CTRL2_APU_WLAN_RF_MUX_SEL(x)      (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_APU_WLAN_RF_MUX_SEL_SHIFT)) & APU_WL_CTRL2_APU_WLAN_RF_MUX_SEL_MASK)
+
+#define APU_WL_CTRL2_FW_FORCE_WL_PWRUP_MASK      (0x1000000U)
+#define APU_WL_CTRL2_FW_FORCE_WL_PWRUP_SHIFT     (24U)
+/*! FW_FORCE_WL_PWRUP - FW Force WLAN Powerup */
+#define APU_WL_CTRL2_FW_FORCE_WL_PWRUP(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_FW_FORCE_WL_PWRUP_SHIFT)) & APU_WL_CTRL2_FW_FORCE_WL_PWRUP_MASK)
+
+#define APU_WL_CTRL2_WLAN_USE_UNSYNC_PWR_LVL_MASK (0x2000000U)
+#define APU_WL_CTRL2_WLAN_USE_UNSYNC_PWR_LVL_SHIFT (25U)
+/*! WLAN_USE_UNSYNC_PWR_LVL - WLAN Use Unsync Power Level */
+#define APU_WL_CTRL2_WLAN_USE_UNSYNC_PWR_LVL(x)  (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_WLAN_USE_UNSYNC_PWR_LVL_SHIFT)) & APU_WL_CTRL2_WLAN_USE_UNSYNC_PWR_LVL_MASK)
+
+#define APU_WL_CTRL2_WL_HOST_SLP_RDY_MASK        (0x80000000U)
+#define APU_WL_CTRL2_WL_HOST_SLP_RDY_SHIFT       (31U)
+/*! WL_HOST_SLP_RDY - WLAN Host Sleep Ready */
+#define APU_WL_CTRL2_WL_HOST_SLP_RDY(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_CTRL2_WL_HOST_SLP_RDY_SHIFT)) & APU_WL_CTRL2_WL_HOST_SLP_RDY_MASK)
+/*! @} */
+
+/*! @name WL_WKUP_MASK2 - WLAN Wakeup Mask 2 */
+/*! @{ */
+
+#define APU_WL_WKUP_MASK2_WL_BCN_TIMER_WKUP_MASK_MASK (0x1U)
+#define APU_WL_WKUP_MASK2_WL_BCN_TIMER_WKUP_MASK_SHIFT (0U)
+/*! WL_BCN_TIMER_WKUP_MASK - WLAN Beacon Timer Wakeup Mask */
+#define APU_WL_WKUP_MASK2_WL_BCN_TIMER_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_WL_BCN_TIMER_WKUP_MASK_SHIFT)) & APU_WL_WKUP_MASK2_WL_BCN_TIMER_WKUP_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_BBUD_T2_PLL_REQ_MASK_MASK (0x2U)
+#define APU_WL_WKUP_MASK2_BBUD_T2_PLL_REQ_MASK_SHIFT (1U)
+/*! BBUD_T2_PLL_REQ_MASK - BBUD T2 PLL Request Mask */
+#define APU_WL_WKUP_MASK2_BBUD_T2_PLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_BBUD_T2_PLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK2_BBUD_T2_PLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_WL_RF_PLL_REQ_MASK_MASK (0x4U)
+#define APU_WL_WKUP_MASK2_WL_RF_PLL_REQ_MASK_SHIFT (2U)
+/*! WL_RF_PLL_REQ_MASK - WLAN RF PLL Request Mask */
+#define APU_WL_WKUP_MASK2_WL_RF_PLL_REQ_MASK(x)  (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_WL_RF_PLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK2_WL_RF_PLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_BCA_MWS_WKUP_XP_MASK_MASK (0x8U)
+#define APU_WL_WKUP_MASK2_BCA_MWS_WKUP_XP_MASK_SHIFT (3U)
+/*! BCA_MWS_WKUP_XP_MASK - BCA MWS Wakeup XP Mask */
+#define APU_WL_WKUP_MASK2_BCA_MWS_WKUP_XP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_BCA_MWS_WKUP_XP_MASK_SHIFT)) & APU_WL_WKUP_MASK2_BCA_MWS_WKUP_XP_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_WL_RF_PLL_DYNPLL_REQ_MASK_MASK (0x100U)
+#define APU_WL_WKUP_MASK2_WL_RF_PLL_DYNPLL_REQ_MASK_SHIFT (8U)
+/*! WL_RF_PLL_DYNPLL_REQ_MASK - When mask = 0, wl_rf_pll_req is treated as pll_req */
+#define APU_WL_WKUP_MASK2_WL_RF_PLL_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_WL_RF_PLL_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK2_WL_RF_PLL_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_WL_HOST_DYNPLL_REQ_MASK_MASK (0x200U)
+#define APU_WL_WKUP_MASK2_WL_HOST_DYNPLL_REQ_MASK_SHIFT (9U)
+/*! WL_HOST_DYNPLL_REQ_MASK - When mask = 0, wlan_host_wkup is treated as pll_req */
+#define APU_WL_WKUP_MASK2_WL_HOST_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_WL_HOST_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK2_WL_HOST_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_WL_TIMER_DYNPLL_REQ_MASK_MASK (0x400U)
+#define APU_WL_WKUP_MASK2_WL_TIMER_DYNPLL_REQ_MASK_SHIFT (10U)
+/*! WL_TIMER_DYNPLL_REQ_MASK - When mask = 0, wlan_timer_xpp req is treated as pll_req */
+#define APU_WL_WKUP_MASK2_WL_TIMER_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_WL_TIMER_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK2_WL_TIMER_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_WL_SLP_RDY_DYNPLL_REQ_MASK_MASK (0x800U)
+#define APU_WL_WKUP_MASK2_WL_SLP_RDY_DYNPLL_REQ_MASK_SHIFT (11U)
+/*! WL_SLP_RDY_DYNPLL_REQ_MASK - When mask = 0, !wl_slp_rdy is treated as pll_req */
+#define APU_WL_WKUP_MASK2_WL_SLP_RDY_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_WL_SLP_RDY_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK2_WL_SLP_RDY_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_IHB_WL_XPP_DYNPLL_REQ_MASK_MASK (0x1000U)
+#define APU_WL_WKUP_MASK2_IHB_WL_XPP_DYNPLL_REQ_MASK_SHIFT (12U)
+/*! IHB_WL_XPP_DYNPLL_REQ_MASK - When mask = 0, ihb_wl_xpp_req is treated as pll_req */
+#define APU_WL_WKUP_MASK2_IHB_WL_XPP_DYNPLL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_IHB_WL_XPP_DYNPLL_REQ_MASK_SHIFT)) & APU_WL_WKUP_MASK2_IHB_WL_XPP_DYNPLL_REQ_MASK_MASK)
+
+#define APU_WL_WKUP_MASK2_WL_HOST_MAP_MASK       (0xFFFF0000U)
+#define APU_WL_WKUP_MASK2_WL_HOST_MAP_SHIFT      (16U)
+/*! WL_HOST_MAP - WLAN Host Map */
+#define APU_WL_WKUP_MASK2_WL_HOST_MAP(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_WKUP_MASK2_WL_HOST_MAP_SHIFT)) & APU_WL_WKUP_MASK2_WL_HOST_MAP_MASK)
+/*! @} */
+
+/*! @name WL_STATUS2 - WLAN Status 2 */
+/*! @{ */
+
+#define APU_WL_STATUS2_APU_MAC_CLK_EN_MASK       (0x1U)
+#define APU_WL_STATUS2_APU_MAC_CLK_EN_SHIFT      (0U)
+/*! APU_MAC_CLK_EN - APU MAC Clock Enable */
+#define APU_WL_STATUS2_APU_MAC_CLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_MAC_CLK_EN_SHIFT)) & APU_WL_STATUS2_APU_MAC_CLK_EN_MASK)
+
+#define APU_WL_STATUS2_APU_BBUD_CLK_EN_MASK      (0x2U)
+#define APU_WL_STATUS2_APU_BBUD_CLK_EN_SHIFT     (1U)
+/*! APU_BBUD_CLK_EN - APU BBUD Clock Enable */
+#define APU_WL_STATUS2_APU_BBUD_CLK_EN(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_BBUD_CLK_EN_SHIFT)) & APU_WL_STATUS2_APU_BBUD_CLK_EN_MASK)
+
+#define APU_WL_STATUS2_APU_WL_RF_CLK_EN_MASK     (0x4U)
+#define APU_WL_STATUS2_APU_WL_RF_CLK_EN_SHIFT    (2U)
+/*! APU_WL_RF_CLK_EN - APU WLAN Ref Clock Enable */
+#define APU_WL_STATUS2_APU_WL_RF_CLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WL_RF_CLK_EN_SHIFT)) & APU_WL_STATUS2_APU_WL_RF_CLK_EN_MASK)
+
+#define APU_WL_STATUS2_APU_WL_SLP_RDY_AFTER_MASK_MASK (0x8U)
+#define APU_WL_STATUS2_APU_WL_SLP_RDY_AFTER_MASK_SHIFT (3U)
+/*! APU_WL_SLP_RDY_AFTER_MASK - APU WLAN Sleep Ready After Mask */
+#define APU_WL_STATUS2_APU_WL_SLP_RDY_AFTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WL_SLP_RDY_AFTER_MASK_SHIFT)) & APU_WL_STATUS2_APU_WL_SLP_RDY_AFTER_MASK_MASK)
+
+#define APU_WL_STATUS2_APU_WL_RF_CTRL_MASK       (0x30U)
+#define APU_WL_STATUS2_APU_WL_RF_CTRL_SHIFT      (4U)
+/*! APU_WL_RF_CTRL - APU WLAN RF Control */
+#define APU_WL_STATUS2_APU_WL_RF_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WL_RF_CTRL_SHIFT)) & APU_WL_STATUS2_APU_WL_RF_CTRL_MASK)
+
+#define APU_WL_STATUS2_APU_PLL1_EN_MASK          (0x40U)
+#define APU_WL_STATUS2_APU_PLL1_EN_SHIFT         (6U)
+/*! APU_PLL1_EN - APU PLL1 Enable */
+#define APU_WL_STATUS2_APU_PLL1_EN(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_PLL1_EN_SHIFT)) & APU_WL_STATUS2_APU_PLL1_EN_MASK)
+
+#define APU_WL_STATUS2_APU_PLL3_EN_MASK          (0x80U)
+#define APU_WL_STATUS2_APU_PLL3_EN_SHIFT         (7U)
+/*! APU_PLL3_EN - APU PLL3 Enable */
+#define APU_WL_STATUS2_APU_PLL3_EN(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_PLL3_EN_SHIFT)) & APU_WL_STATUS2_APU_PLL3_EN_MASK)
+
+#define APU_WL_STATUS2_BCA_MWS_WKUP_XP_MASK      (0x100U)
+#define APU_WL_STATUS2_BCA_MWS_WKUP_XP_SHIFT     (8U)
+/*! BCA_MWS_WKUP_XP - BCA MWS Wakeup XP */
+#define APU_WL_STATUS2_BCA_MWS_WKUP_XP(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_BCA_MWS_WKUP_XP_SHIFT)) & APU_WL_STATUS2_BCA_MWS_WKUP_XP_MASK)
+
+#define APU_WL_STATUS2_APU_RTDP_WU_RSTB_MASK     (0x200U)
+#define APU_WL_STATUS2_APU_RTDP_WU_RSTB_SHIFT    (9U)
+/*! APU_RTDP_WU_RSTB - APU RTDP WU RSTb */
+#define APU_WL_STATUS2_APU_RTDP_WU_RSTB(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_RTDP_WU_RSTB_SHIFT)) & APU_WL_STATUS2_APU_RTDP_WU_RSTB_MASK)
+
+#define APU_WL_STATUS2_APU_BBUD_NON_UDR_RST_B_MASK (0x400U)
+#define APU_WL_STATUS2_APU_BBUD_NON_UDR_RST_B_SHIFT (10U)
+/*! APU_BBUD_NON_UDR_RST_B - APU BBUD non-UDR RSTb */
+#define APU_WL_STATUS2_APU_BBUD_NON_UDR_RST_B(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_BBUD_NON_UDR_RST_B_SHIFT)) & APU_WL_STATUS2_APU_BBUD_NON_UDR_RST_B_MASK)
+
+#define APU_WL_STATUS2_APU_WL_ST_MASK            (0xF000U)
+#define APU_WL_STATUS2_APU_WL_ST_SHIFT           (12U)
+/*! APU_WL_ST - APU WLAN St */
+#define APU_WL_STATUS2_APU_WL_ST(x)              (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WL_ST_SHIFT)) & APU_WL_STATUS2_APU_WL_ST_MASK)
+
+#define APU_WL_STATUS2_APU_WLAN_SWITCH_PD_MASK   (0x10000U)
+#define APU_WL_STATUS2_APU_WLAN_SWITCH_PD_SHIFT  (16U)
+/*! APU_WLAN_SWITCH_PD - APU WLAN Switch Pd */
+#define APU_WL_STATUS2_APU_WLAN_SWITCH_PD(x)     (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WLAN_SWITCH_PD_SHIFT)) & APU_WL_STATUS2_APU_WLAN_SWITCH_PD_MASK)
+
+#define APU_WL_STATUS2_APU_WLAN_UDR_FIREWALL_B_MASK (0x20000U)
+#define APU_WL_STATUS2_APU_WLAN_UDR_FIREWALL_B_SHIFT (17U)
+/*! APU_WLAN_UDR_FIREWALL_B - APU WLAN UDR Firewall b */
+#define APU_WL_STATUS2_APU_WLAN_UDR_FIREWALL_B(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WLAN_UDR_FIREWALL_B_SHIFT)) & APU_WL_STATUS2_APU_WLAN_UDR_FIREWALL_B_MASK)
+
+#define APU_WL_STATUS2_APU_WLAN_CLK_DIV_RSTB_MASK (0x40000U)
+#define APU_WL_STATUS2_APU_WLAN_CLK_DIV_RSTB_SHIFT (18U)
+/*! APU_WLAN_CLK_DIV_RSTB - APU WLAN Clock Div RSTb */
+#define APU_WL_STATUS2_APU_WLAN_CLK_DIV_RSTB(x)  (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WLAN_CLK_DIV_RSTB_SHIFT)) & APU_WL_STATUS2_APU_WLAN_CLK_DIV_RSTB_MASK)
+
+#define APU_WL_STATUS2_APU_WLAN_ISO_EN_MASK      (0x80000U)
+#define APU_WL_STATUS2_APU_WLAN_ISO_EN_SHIFT     (19U)
+/*! APU_WLAN_ISO_EN - APU WLAN ISO Enable */
+#define APU_WL_STATUS2_APU_WLAN_ISO_EN(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WLAN_ISO_EN_SHIFT)) & APU_WL_STATUS2_APU_WLAN_ISO_EN_MASK)
+
+#define APU_WL_STATUS2_APU_WLAN_SRAM_PD_MASK     (0x100000U)
+#define APU_WL_STATUS2_APU_WLAN_SRAM_PD_SHIFT    (20U)
+/*! APU_WLAN_SRAM_PD - APU WLAN SRAM Pd */
+#define APU_WL_STATUS2_APU_WLAN_SRAM_PD(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_APU_WLAN_SRAM_PD_SHIFT)) & APU_WL_STATUS2_APU_WLAN_SRAM_PD_MASK)
+
+#define APU_WL_STATUS2_WLAN_VOL_REACHED_MASK     (0x200000U)
+#define APU_WL_STATUS2_WLAN_VOL_REACHED_SHIFT    (21U)
+/*! WLAN_VOL_REACHED - WLAN Volume Reached */
+#define APU_WL_STATUS2_WLAN_VOL_REACHED(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_WLAN_VOL_REACHED_SHIFT)) & APU_WL_STATUS2_WLAN_VOL_REACHED_MASK)
+
+#define APU_WL_STATUS2_SOC_VOL_REACHED_MASK      (0x400000U)
+#define APU_WL_STATUS2_SOC_VOL_REACHED_SHIFT     (22U)
+/*! SOC_VOL_REACHED - SoC Volume Reached */
+#define APU_WL_STATUS2_SOC_VOL_REACHED(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_SOC_VOL_REACHED_SHIFT)) & APU_WL_STATUS2_SOC_VOL_REACHED_MASK)
+
+#define APU_WL_STATUS2_WL_PWR_RDY_MASK           (0x800000U)
+#define APU_WL_STATUS2_WL_PWR_RDY_SHIFT          (23U)
+/*! WL_PWR_RDY - WLAN Power Ready */
+#define APU_WL_STATUS2_WL_PWR_RDY(x)             (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_WL_PWR_RDY_SHIFT)) & APU_WL_STATUS2_WL_PWR_RDY_MASK)
+
+#define APU_WL_STATUS2_WL_HOST_INTR_REF_MASK     (0x1000000U)
+#define APU_WL_STATUS2_WL_HOST_INTR_REF_SHIFT    (24U)
+/*! WL_HOST_INTR_REF - WLAN Host Interrupt Reference */
+#define APU_WL_STATUS2_WL_HOST_INTR_REF(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_WL_HOST_INTR_REF_SHIFT)) & APU_WL_STATUS2_WL_HOST_INTR_REF_MASK)
+
+#define APU_WL_STATUS2_WLAN_HOST_WKUP_MASK       (0x2000000U)
+#define APU_WL_STATUS2_WLAN_HOST_WKUP_SHIFT      (25U)
+/*! WLAN_HOST_WKUP - WLAN Host Wakeup */
+#define APU_WL_STATUS2_WLAN_HOST_WKUP(x)         (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_WLAN_HOST_WKUP_SHIFT)) & APU_WL_STATUS2_WLAN_HOST_WKUP_MASK)
+
+#define APU_WL_STATUS2_WL_TIMER_INTR_MASK        (0x4000000U)
+#define APU_WL_STATUS2_WL_TIMER_INTR_SHIFT       (26U)
+/*! WL_TIMER_INTR - WLAN Timer Interrupt */
+#define APU_WL_STATUS2_WL_TIMER_INTR(x)          (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_WL_TIMER_INTR_SHIFT)) & APU_WL_STATUS2_WL_TIMER_INTR_MASK)
+
+#define APU_WL_STATUS2_TIMER_XPP_WAKEUP_MASK     (0x8000000U)
+#define APU_WL_STATUS2_TIMER_XPP_WAKEUP_SHIFT    (27U)
+/*! TIMER_XPP_WAKEUP - Timer XPP Wakeup */
+#define APU_WL_STATUS2_TIMER_XPP_WAKEUP(x)       (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_TIMER_XPP_WAKEUP_SHIFT)) & APU_WL_STATUS2_TIMER_XPP_WAKEUP_MASK)
+
+#define APU_WL_STATUS2_TIMER_WAKEUP_MASK         (0x10000000U)
+#define APU_WL_STATUS2_TIMER_WAKEUP_SHIFT        (28U)
+/*! TIMER_WAKEUP - Timer Wakeup */
+#define APU_WL_STATUS2_TIMER_WAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_TIMER_WAKEUP_SHIFT)) & APU_WL_STATUS2_TIMER_WAKEUP_MASK)
+
+#define APU_WL_STATUS2_WLRF_PLL_REQ_MASK         (0x20000000U)
+#define APU_WL_STATUS2_WLRF_PLL_REQ_SHIFT        (29U)
+/*! WLRF_PLL_REQ - WLAN RF PLL Request */
+#define APU_WL_STATUS2_WLRF_PLL_REQ(x)           (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_WLRF_PLL_REQ_SHIFT)) & APU_WL_STATUS2_WLRF_PLL_REQ_MASK)
+
+#define APU_WL_STATUS2_BBUD_T2_PLL_REQ_MASK      (0x40000000U)
+#define APU_WL_STATUS2_BBUD_T2_PLL_REQ_SHIFT     (30U)
+/*! BBUD_T2_PLL_REQ - BBUD T2 PLL Request */
+#define APU_WL_STATUS2_BBUD_T2_PLL_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_BBUD_T2_PLL_REQ_SHIFT)) & APU_WL_STATUS2_BBUD_T2_PLL_REQ_MASK)
+
+#define APU_WL_STATUS2_BCA_CLK_REQ_MASK          (0x80000000U)
+#define APU_WL_STATUS2_BCA_CLK_REQ_SHIFT         (31U)
+/*! BCA_CLK_REQ - BCA Clock Request */
+#define APU_WL_STATUS2_BCA_CLK_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_WL_STATUS2_BCA_CLK_REQ_SHIFT)) & APU_WL_STATUS2_BCA_CLK_REQ_MASK)
+/*! @} */
+
+/*! @name WL_ALARM_RD2 - WLAN Alarm Readback 2 */
+/*! @{ */
+
+#define APU_WL_ALARM_RD2_APU_WL_ALARM_RD_MASK    (0xFFFFFFFFU)
+#define APU_WL_ALARM_RD2_APU_WL_ALARM_RD_SHIFT   (0U)
+/*! APU_WL_ALARM_RD - reads back current beacon timer alarm value */
+#define APU_WL_ALARM_RD2_APU_WL_ALARM_RD(x)      (((uint32_t)(((uint32_t)(x)) << APU_WL_ALARM_RD2_APU_WL_ALARM_RD_SHIFT)) & APU_WL_ALARM_RD2_APU_WL_ALARM_RD_MASK)
+/*! @} */
+
+/*! @name WL_BCN_XP_ALARM2 - WLAN Beacon XP Alarm 2 */
+/*! @{ */
+
+#define APU_WL_BCN_XP_ALARM2_WL_BCN_XP_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_BCN_XP_ALARM2_WL_BCN_XP_ALARM_SHIFT (0U)
+/*! WL_BCN_XP_ALARM - number of sleep clocks until WLAN beacon timer requests for reference clock and power */
+#define APU_WL_BCN_XP_ALARM2_WL_BCN_XP_ALARM(x)  (((uint32_t)(((uint32_t)(x)) << APU_WL_BCN_XP_ALARM2_WL_BCN_XP_ALARM_SHIFT)) & APU_WL_BCN_XP_ALARM2_WL_BCN_XP_ALARM_MASK)
+/*! @} */
+
+/*! @name WL_BCN_INTR_ALARM2 - WLAN Beacon Interrupt Alarm 2 */
+/*! @{ */
+
+#define APU_WL_BCN_INTR_ALARM2_WL_BCN_INTR_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_BCN_INTR_ALARM2_WL_BCN_INTR_ALARM_SHIFT (0U)
+/*! WL_BCN_INTR_ALARM - number of ref clocks after WLAN beacon timer request to firmware wakeup */
+#define APU_WL_BCN_INTR_ALARM2_WL_BCN_INTR_ALARM(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_BCN_INTR_ALARM2_WL_BCN_INTR_ALARM_SHIFT)) & APU_WL_BCN_INTR_ALARM2_WL_BCN_INTR_ALARM_MASK)
+/*! @} */
+
+/*! @name WL_HOST_INTR_ALARM2 - WLAN Host Interrupt Alarm 2 */
+/*! @{ */
+
+#define APU_WL_HOST_INTR_ALARM2_WL_HOST_INTR_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_HOST_INTR_ALARM2_WL_HOST_INTR_ALARM_SHIFT (0U)
+/*! WL_HOST_INTR_ALARM - number of ref clocks after WLAN host request to firmware wakeup */
+#define APU_WL_HOST_INTR_ALARM2_WL_HOST_INTR_ALARM(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_HOST_INTR_ALARM2_WL_HOST_INTR_ALARM_SHIFT)) & APU_WL_HOST_INTR_ALARM2_WL_HOST_INTR_ALARM_MASK)
+/*! @} */
+
+/*! @name WL_BCN_PLL_ALARM2 - WLAN Beacon PLL Alarm 2 */
+/*! @{ */
+
+#define APU_WL_BCN_PLL_ALARM2_WL_BCN_PLL_ALARM_MASK (0xFFFFFFFFU)
+#define APU_WL_BCN_PLL_ALARM2_WL_BCN_PLL_ALARM_SHIFT (0U)
+/*! WL_BCN_PLL_ALARM - number of sleep clocks until WLAN beacon timer requests for reference clock, power, and PLL */
+#define APU_WL_BCN_PLL_ALARM2_WL_BCN_PLL_ALARM(x) (((uint32_t)(((uint32_t)(x)) << APU_WL_BCN_PLL_ALARM2_WL_BCN_PLL_ALARM_SHIFT)) & APU_WL_BCN_PLL_ALARM2_WL_BCN_PLL_ALARM_MASK)
+/*! @} */
+
+/*! @name WLCOMN_PWR_CTRL - WLAN Comm Powerup Control */
+/*! @{ */
+
+#define APU_WLCOMN_PWR_CTRL_WLCOMN_UDR_ASSERT_CNT_MASK (0xFFU)
+#define APU_WLCOMN_PWR_CTRL_WLCOMN_UDR_ASSERT_CNT_SHIFT (0U)
+/*! WLCOMN_UDR_ASSERT_CNT - WL COMM UDR Assert Count */
+#define APU_WLCOMN_PWR_CTRL_WLCOMN_UDR_ASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_WLCOMN_UDR_ASSERT_CNT_SHIFT)) & APU_WLCOMN_PWR_CTRL_WLCOMN_UDR_ASSERT_CNT_MASK)
+
+#define APU_WLCOMN_PWR_CTRL_USE_WLCOMN_PWR_RDY_FOR_WL_MASK (0x100U)
+#define APU_WLCOMN_PWR_CTRL_USE_WLCOMN_PWR_RDY_FOR_WL_SHIFT (8U)
+/*! USE_WLCOMN_PWR_RDY_FOR_WL - Use WL COMM Power Ready fro WLAN */
+#define APU_WLCOMN_PWR_CTRL_USE_WLCOMN_PWR_RDY_FOR_WL(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_USE_WLCOMN_PWR_RDY_FOR_WL_SHIFT)) & APU_WLCOMN_PWR_CTRL_USE_WLCOMN_PWR_RDY_FOR_WL_MASK)
+
+#define APU_WLCOMN_PWR_CTRL_USE_DEEPSLEEP_FOR_SYS_CLK_EN_MASK (0x200U)
+#define APU_WLCOMN_PWR_CTRL_USE_DEEPSLEEP_FOR_SYS_CLK_EN_SHIFT (9U)
+/*! USE_DEEPSLEEP_FOR_SYS_CLK_EN - Use Deep Sleep for SYS_CLK Enable */
+#define APU_WLCOMN_PWR_CTRL_USE_DEEPSLEEP_FOR_SYS_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_USE_DEEPSLEEP_FOR_SYS_CLK_EN_SHIFT)) & APU_WLCOMN_PWR_CTRL_USE_DEEPSLEEP_FOR_SYS_CLK_EN_MASK)
+
+#define APU_WLCOMN_PWR_CTRL_IDLE2ISO_DLY_EN_MASK (0x400U)
+#define APU_WLCOMN_PWR_CTRL_IDLE2ISO_DLY_EN_SHIFT (10U)
+/*! IDLE2ISO_DLY_EN - wlcomn FSM state delay enable. When 1, use wlcomn_pwr_ctrl_dly and wlcomn_pwr_ctrl_dly2. When 0, no delay. */
+#define APU_WLCOMN_PWR_CTRL_IDLE2ISO_DLY_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_IDLE2ISO_DLY_EN_SHIFT)) & APU_WLCOMN_PWR_CTRL_IDLE2ISO_DLY_EN_MASK)
+
+#define APU_WLCOMN_PWR_CTRL_CPU_VINITHI_MASK     (0x8000U)
+#define APU_WLCOMN_PWR_CTRL_CPU_VINITHI_SHIFT    (15U)
+/*! CPU_VINITHI - CPU to CPU Delay */
+#define APU_WLCOMN_PWR_CTRL_CPU_VINITHI(x)       (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_CPU_VINITHI_SHIFT)) & APU_WLCOMN_PWR_CTRL_CPU_VINITHI_MASK)
+
+#define APU_WLCOMN_PWR_CTRL_WLCOMN_PWRUP_CNT_MASK (0xFFFF0000U)
+#define APU_WLCOMN_PWR_CTRL_WLCOMN_PWRUP_CNT_SHIFT (16U)
+/*! WLCOMN_PWRUP_CNT - number of reference clocks after soc_pwr_rdy to push wlcomn power up */
+#define APU_WLCOMN_PWR_CTRL_WLCOMN_PWRUP_CNT(x)  (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_WLCOMN_PWRUP_CNT_SHIFT)) & APU_WLCOMN_PWR_CTRL_WLCOMN_PWRUP_CNT_MASK)
+/*! @} */
+
+/*! @name WLCOMN_STATUS - WLAN Comm Status */
+/*! @{ */
+
+#define APU_WLCOMN_STATUS_START_WLCOMN_WKUP_REFCK_MASK (0x400U)
+#define APU_WLCOMN_STATUS_START_WLCOMN_WKUP_REFCK_SHIFT (10U)
+/*! START_WLCOMN_WKUP_REFCK - WLCOMN FSM start ip wake up */
+#define APU_WLCOMN_STATUS_START_WLCOMN_WKUP_REFCK(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_STATUS_START_WLCOMN_WKUP_REFCK_SHIFT)) & APU_WLCOMN_STATUS_START_WLCOMN_WKUP_REFCK_MASK)
+
+#define APU_WLCOMN_STATUS_ENTER_CPU1_SUB_DSLP_REFCK_MASK (0x800U)
+#define APU_WLCOMN_STATUS_ENTER_CPU1_SUB_DSLP_REFCK_SHIFT (11U)
+/*! ENTER_CPU1_SUB_DSLP_REFCK - WLCOMN FSM enter ip power down */
+#define APU_WLCOMN_STATUS_ENTER_CPU1_SUB_DSLP_REFCK(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_STATUS_ENTER_CPU1_SUB_DSLP_REFCK_SHIFT)) & APU_WLCOMN_STATUS_ENTER_CPU1_SUB_DSLP_REFCK_MASK)
+
+#define APU_WLCOMN_STATUS_APU_WLCOMN_ST_MASK     (0xF000U)
+#define APU_WLCOMN_STATUS_APU_WLCOMN_ST_SHIFT    (12U)
+/*! APU_WLCOMN_ST - APU WLAN COMN St */
+#define APU_WLCOMN_STATUS_APU_WLCOMN_ST(x)       (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_STATUS_APU_WLCOMN_ST_SHIFT)) & APU_WLCOMN_STATUS_APU_WLCOMN_ST_MASK)
+
+#define APU_WLCOMN_STATUS_APU_WLCOMN_SWITCH_PD_MASK (0x10000U)
+#define APU_WLCOMN_STATUS_APU_WLCOMN_SWITCH_PD_SHIFT (16U)
+/*! APU_WLCOMN_SWITCH_PD - APU WLAN COMN Switch Pd */
+#define APU_WLCOMN_STATUS_APU_WLCOMN_SWITCH_PD(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_STATUS_APU_WLCOMN_SWITCH_PD_SHIFT)) & APU_WLCOMN_STATUS_APU_WLCOMN_SWITCH_PD_MASK)
+
+#define APU_WLCOMN_STATUS_APU_WLCOMN_UDR_FIREWALL_B_MASK (0x20000U)
+#define APU_WLCOMN_STATUS_APU_WLCOMN_UDR_FIREWALL_B_SHIFT (17U)
+/*! APU_WLCOMN_UDR_FIREWALL_B - APU WLAN COMN UDR Firewall b */
+#define APU_WLCOMN_STATUS_APU_WLCOMN_UDR_FIREWALL_B(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_STATUS_APU_WLCOMN_UDR_FIREWALL_B_SHIFT)) & APU_WLCOMN_STATUS_APU_WLCOMN_UDR_FIREWALL_B_MASK)
+
+#define APU_WLCOMN_STATUS_APU_WLCOMN_CLK_DIV_RSTB_MASK (0x40000U)
+#define APU_WLCOMN_STATUS_APU_WLCOMN_CLK_DIV_RSTB_SHIFT (18U)
+/*! APU_WLCOMN_CLK_DIV_RSTB - APU WLAN COMN Clock Div RSTb */
+#define APU_WLCOMN_STATUS_APU_WLCOMN_CLK_DIV_RSTB(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_STATUS_APU_WLCOMN_CLK_DIV_RSTB_SHIFT)) & APU_WLCOMN_STATUS_APU_WLCOMN_CLK_DIV_RSTB_MASK)
+
+#define APU_WLCOMN_STATUS_APU_WLCOMN_ISO_EN_MASK (0x80000U)
+#define APU_WLCOMN_STATUS_APU_WLCOMN_ISO_EN_SHIFT (19U)
+/*! APU_WLCOMN_ISO_EN - APU WLAN COMN ISO Enable */
+#define APU_WLCOMN_STATUS_APU_WLCOMN_ISO_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_STATUS_APU_WLCOMN_ISO_EN_SHIFT)) & APU_WLCOMN_STATUS_APU_WLCOMN_ISO_EN_MASK)
+/*! @} */
+
+/*! @name BT_CTRL - Bluetooth Control */
+/*! @{ */
+
+#define APU_BT_CTRL_BT_SLP_RDY_MASK              (0x1U)
+#define APU_BT_CTRL_BT_SLP_RDY_SHIFT             (0U)
+/*! BT_SLP_RDY - Bluetooth Sleep Ready */
+#define APU_BT_CTRL_BT_SLP_RDY(x)                (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BT_SLP_RDY_SHIFT)) & APU_BT_CTRL_BT_SLP_RDY_MASK)
+
+#define APU_BT_CTRL_BT_SLP_RDYMASK_MASK          (0x2U)
+#define APU_BT_CTRL_BT_SLP_RDYMASK_SHIFT         (1U)
+/*! BT_SLP_RDYMASK - Bluetoot Sleep Ready Mask */
+#define APU_BT_CTRL_BT_SLP_RDYMASK(x)            (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BT_SLP_RDYMASK_SHIFT)) & APU_BT_CTRL_BT_SLP_RDYMASK_MASK)
+
+#define APU_BT_CTRL_BT_SLP_RDY_FW_MASK           (0x4U)
+#define APU_BT_CTRL_BT_SLP_RDY_FW_SHIFT          (2U)
+/*! BT_SLP_RDY_FW - Bluetooth Sleep Ready FW */
+#define APU_BT_CTRL_BT_SLP_RDY_FW(x)             (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BT_SLP_RDY_FW_SHIFT)) & APU_BT_CTRL_BT_SLP_RDY_FW_MASK)
+
+#define APU_BT_CTRL_BTU_CLK_NCO_MODE_SEL_EN_MASK (0x8U)
+#define APU_BT_CTRL_BTU_CLK_NCO_MODE_SEL_EN_SHIFT (3U)
+/*! BTU_CLK_NCO_MODE_SEL_EN - 0- disable the btu_clk_nco_mode from CIU2, keep the bt_clk_req as XP wakeup source */
+#define APU_BT_CTRL_BTU_CLK_NCO_MODE_SEL_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BTU_CLK_NCO_MODE_SEL_EN_SHIFT)) & APU_BT_CTRL_BTU_CLK_NCO_MODE_SEL_EN_MASK)
+
+#define APU_BT_CTRL_USE_BT_INTR_SLP_MASK         (0x80U)
+#define APU_BT_CTRL_USE_BT_INTR_SLP_SHIFT        (7U)
+/*! USE_BT_INTR_SLP - Use Bluetooth interrupt Sleep */
+#define APU_BT_CTRL_USE_BT_INTR_SLP(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_USE_BT_INTR_SLP_SHIFT)) & APU_BT_CTRL_USE_BT_INTR_SLP_MASK)
+
+#define APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL1_MASK   (0x4000000U)
+#define APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL1_SHIFT  (26U)
+/*! BT_CLK_SYNC_MODE_SEL1 - Bluetooth Clock Sync Mode Select 1 */
+#define APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL1(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL1_SHIFT)) & APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL1_MASK)
+
+#define APU_BT_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_MASK (0x8000000U)
+#define APU_BT_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_SHIFT (27U)
+/*! USE_GLITCH_FREE_BT_CLK_REQ - Use Glitch-Free Bluetooth Clock Request */
+#define APU_BT_CTRL_USE_GLITCH_FREE_BT_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_SHIFT)) & APU_BT_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_MASK)
+
+#define APU_BT_CTRL_BRF_CLK_SYNC_MODE_SEL_MASK   (0x10000000U)
+#define APU_BT_CTRL_BRF_CLK_SYNC_MODE_SEL_SHIFT  (28U)
+/*! BRF_CLK_SYNC_MODE_SEL - BRF Clock Sync Mode Select */
+#define APU_BT_CTRL_BRF_CLK_SYNC_MODE_SEL(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BRF_CLK_SYNC_MODE_SEL_SHIFT)) & APU_BT_CTRL_BRF_CLK_SYNC_MODE_SEL_MASK)
+
+#define APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL0_MASK   (0x20000000U)
+#define APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL0_SHIFT  (29U)
+/*! BT_CLK_SYNC_MODE_SEL0 - Bluetooth Clock Sync Mode Select 0 */
+#define APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL0(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL0_SHIFT)) & APU_BT_CTRL_BT_CLK_SYNC_MODE_SEL0_MASK)
+
+#define APU_BT_CTRL_BT_PLL_SYNC_MODE_SEL_MASK    (0x40000000U)
+#define APU_BT_CTRL_BT_PLL_SYNC_MODE_SEL_SHIFT   (30U)
+/*! BT_PLL_SYNC_MODE_SEL - Bluetooth PLL Sync Mode Select */
+#define APU_BT_CTRL_BT_PLL_SYNC_MODE_SEL(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BT_PLL_SYNC_MODE_SEL_SHIFT)) & APU_BT_CTRL_BT_PLL_SYNC_MODE_SEL_MASK)
+
+#define APU_BT_CTRL_BT_HOST_SLP_RDY_MASK         (0x80000000U)
+#define APU_BT_CTRL_BT_HOST_SLP_RDY_SHIFT        (31U)
+/*! BT_HOST_SLP_RDY - Bluetooth Host Sleep Ready */
+#define APU_BT_CTRL_BT_HOST_SLP_RDY(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT_CTRL_BT_HOST_SLP_RDY_SHIFT)) & APU_BT_CTRL_BT_HOST_SLP_RDY_MASK)
+/*! @} */
+
+/*! @name BT_WKUP_MASK - Bluetooth Wakeup Mask */
+/*! @{ */
+
+#define APU_BT_WKUP_MASK_BCA_CLK_REQ_MASK_MASK   (0x1U)
+#define APU_BT_WKUP_MASK_BCA_CLK_REQ_MASK_SHIFT  (0U)
+/*! BCA_CLK_REQ_MASK - BCA Clock Request Mask */
+#define APU_BT_WKUP_MASK_BCA_CLK_REQ_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT_WKUP_MASK_BCA_CLK_REQ_MASK_SHIFT)) & APU_BT_WKUP_MASK_BCA_CLK_REQ_MASK_MASK)
+
+#define APU_BT_WKUP_MASK_BT_CLK_REQ_MASK_MASK    (0x2U)
+#define APU_BT_WKUP_MASK_BT_CLK_REQ_MASK_SHIFT   (1U)
+/*! BT_CLK_REQ_MASK - Bluetooth Clock Request Mask */
+#define APU_BT_WKUP_MASK_BT_CLK_REQ_MASK(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT_WKUP_MASK_BT_CLK_REQ_MASK_SHIFT)) & APU_BT_WKUP_MASK_BT_CLK_REQ_MASK_MASK)
+
+#define APU_BT_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_MASK (0x4U)
+#define APU_BT_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_SHIFT (2U)
+/*! BT_WB_ACTIVE_REQ_MASK - Bluetooth WB Active Request Mask */
+#define APU_BT_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_BT_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_SHIFT)) & APU_BT_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_MASK)
+
+#define APU_BT_WKUP_MASK_BT_INTR_MASK_MASK       (0x8U)
+#define APU_BT_WKUP_MASK_BT_INTR_MASK_SHIFT      (3U)
+/*! BT_INTR_MASK - Bluetooth Interrupt Mask */
+#define APU_BT_WKUP_MASK_BT_INTR_MASK(x)         (((uint32_t)(((uint32_t)(x)) << APU_BT_WKUP_MASK_BT_INTR_MASK_SHIFT)) & APU_BT_WKUP_MASK_BT_INTR_MASK_MASK)
+
+#define APU_BT_WKUP_MASK_BT_PLL_REQ_MASK_MASK    (0x10U)
+#define APU_BT_WKUP_MASK_BT_PLL_REQ_MASK_SHIFT   (4U)
+/*! BT_PLL_REQ_MASK - Bluetooth PLL Request Mask */
+#define APU_BT_WKUP_MASK_BT_PLL_REQ_MASK(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT_WKUP_MASK_BT_PLL_REQ_MASK_SHIFT)) & APU_BT_WKUP_MASK_BT_PLL_REQ_MASK_MASK)
+
+#define APU_BT_WKUP_MASK_BRF_PLL_REQ_MASK_MASK   (0x20U)
+#define APU_BT_WKUP_MASK_BRF_PLL_REQ_MASK_SHIFT  (5U)
+/*! BRF_PLL_REQ_MASK - BRF PLL Request Mask */
+#define APU_BT_WKUP_MASK_BRF_PLL_REQ_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT_WKUP_MASK_BRF_PLL_REQ_MASK_SHIFT)) & APU_BT_WKUP_MASK_BRF_PLL_REQ_MASK_MASK)
+
+#define APU_BT_WKUP_MASK_BT_HOST_MAP_MASK        (0xFFFF0000U)
+#define APU_BT_WKUP_MASK_BT_HOST_MAP_SHIFT       (16U)
+/*! BT_HOST_MAP - Bluetooth Host Map */
+#define APU_BT_WKUP_MASK_BT_HOST_MAP(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT_WKUP_MASK_BT_HOST_MAP_SHIFT)) & APU_BT_WKUP_MASK_BT_HOST_MAP_MASK)
+/*! @} */
+
+/*! @name BT_STATUS - Bluetooth Status */
+/*! @{ */
+
+#define APU_BT_STATUS_APU_BT_CLK_EN_MASK         (0x1U)
+#define APU_BT_STATUS_APU_BT_CLK_EN_SHIFT        (0U)
+/*! APU_BT_CLK_EN - APU Bluetooth Clock Enable */
+#define APU_BT_STATUS_APU_BT_CLK_EN(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_APU_BT_CLK_EN_SHIFT)) & APU_BT_STATUS_APU_BT_CLK_EN_MASK)
+
+#define APU_BT_STATUS_APU_BRF_CLK_EN_MASK        (0x2U)
+#define APU_BT_STATUS_APU_BRF_CLK_EN_SHIFT       (1U)
+/*! APU_BRF_CLK_EN - APU BRF Clock Enable */
+#define APU_BT_STATUS_APU_BRF_CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_APU_BRF_CLK_EN_SHIFT)) & APU_BT_STATUS_APU_BRF_CLK_EN_MASK)
+
+#define APU_BT_STATUS_BT_ACTIVE_SLPCK_MASK       (0x4U)
+#define APU_BT_STATUS_BT_ACTIVE_SLPCK_SHIFT      (2U)
+/*! BT_ACTIVE_SLPCK - Bluetooth Active Sleep Clock */
+#define APU_BT_STATUS_BT_ACTIVE_SLPCK(x)         (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_BT_ACTIVE_SLPCK_SHIFT)) & APU_BT_STATUS_BT_ACTIVE_SLPCK_MASK)
+
+#define APU_BT_STATUS_BT_HOST_WKUP_MASK          (0x10U)
+#define APU_BT_STATUS_BT_HOST_WKUP_SHIFT         (4U)
+/*! BT_HOST_WKUP - Bluetooth Host Wakeup */
+#define APU_BT_STATUS_BT_HOST_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_BT_HOST_WKUP_SHIFT)) & APU_BT_STATUS_BT_HOST_WKUP_MASK)
+
+#define APU_BT_STATUS_BT_INTERRUPT_MASK          (0x20U)
+#define APU_BT_STATUS_BT_INTERRUPT_SHIFT         (5U)
+/*! BT_INTERRUPT - Bluetooth Interrupt */
+#define APU_BT_STATUS_BT_INTERRUPT(x)            (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_BT_INTERRUPT_SHIFT)) & APU_BT_STATUS_BT_INTERRUPT_MASK)
+
+#define APU_BT_STATUS_BT_PLL_REQ_MASK            (0x40U)
+#define APU_BT_STATUS_BT_PLL_REQ_SHIFT           (6U)
+/*! BT_PLL_REQ - Bluetooth PLL Request */
+#define APU_BT_STATUS_BT_PLL_REQ(x)              (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_BT_PLL_REQ_SHIFT)) & APU_BT_STATUS_BT_PLL_REQ_MASK)
+
+#define APU_BT_STATUS_BT_CLK_REQ_MASK            (0x80U)
+#define APU_BT_STATUS_BT_CLK_REQ_SHIFT           (7U)
+/*! BT_CLK_REQ - Bluetooth Clock Request */
+#define APU_BT_STATUS_BT_CLK_REQ(x)              (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_BT_CLK_REQ_SHIFT)) & APU_BT_STATUS_BT_CLK_REQ_MASK)
+
+#define APU_BT_STATUS_BRF_PLL_REQ_MASK           (0x100U)
+#define APU_BT_STATUS_BRF_PLL_REQ_SHIFT          (8U)
+/*! BRF_PLL_REQ - BRF PLL Request */
+#define APU_BT_STATUS_BRF_PLL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_BRF_PLL_REQ_SHIFT)) & APU_BT_STATUS_BRF_PLL_REQ_MASK)
+
+#define APU_BT_STATUS_BT_WIDEBAND_ACTIVE_MASK    (0x200U)
+#define APU_BT_STATUS_BT_WIDEBAND_ACTIVE_SHIFT   (9U)
+/*! BT_WIDEBAND_ACTIVE - Bluetooth Wideband Active */
+#define APU_BT_STATUS_BT_WIDEBAND_ACTIVE(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_BT_WIDEBAND_ACTIVE_SHIFT)) & APU_BT_STATUS_BT_WIDEBAND_ACTIVE_MASK)
+
+#define APU_BT_STATUS_HOST_WKUP_IN_MASK          (0xFFFF0000U)
+#define APU_BT_STATUS_HOST_WKUP_IN_SHIFT         (16U)
+/*! HOST_WKUP_IN - Host Wakeup In */
+#define APU_BT_STATUS_HOST_WKUP_IN(x)            (((uint32_t)(((uint32_t)(x)) << APU_BT_STATUS_HOST_WKUP_IN_SHIFT)) & APU_BT_STATUS_HOST_WKUP_IN_MASK)
+/*! @} */
+
+/*! @name BT_CKEN_CTRL - Bluetooth Clock Enable Control */
+/*! @{ */
+
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_PWR_MASK  (0x1U)
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_PWR_SHIFT (0U)
+/*! BT_CLK_EN_VAL_PWR - control value for bt_clk_en when power ready */
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_PWR(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_PWR_SHIFT)) & APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_PWR_MASK)
+
+#define APU_BT_CKEN_CTRL_BL_CLK_EN_SEL_PWR_MASK  (0x2U)
+#define APU_BT_CKEN_CTRL_BL_CLK_EN_SEL_PWR_SHIFT (1U)
+/*! BL_CLK_EN_SEL_PWR - selection for bt_clk_en when power ready */
+#define APU_BT_CKEN_CTRL_BL_CLK_EN_SEL_PWR(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT_CKEN_CTRL_BL_CLK_EN_SEL_PWR_SHIFT)) & APU_BT_CKEN_CTRL_BL_CLK_EN_SEL_PWR_MASK)
+
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_MASK (0x4U)
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_SHIFT (2U)
+/*! BT_CLK_EN_VAL_XOSC - control value for bt_clk_en when XOSC ready */
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_XOSC(x)   (((uint32_t)(((uint32_t)(x)) << APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_SHIFT)) & APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_MASK)
+
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_MASK (0x8U)
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_SHIFT (3U)
+/*! BT_CLK_EN_SEL_XOSC - selection for bt_clk_en when XOSC ready */
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_XOSC(x)   (((uint32_t)(((uint32_t)(x)) << APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_SHIFT)) & APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_MASK)
+
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_MASK      (0x10U)
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_SHIFT     (4U)
+/*! BT_CLK_EN_VAL - control value for bt_clk_en when PLL ready */
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_VAL(x)        (((uint32_t)(((uint32_t)(x)) << APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_SHIFT)) & APU_BT_CKEN_CTRL_BT_CLK_EN_VAL_MASK)
+
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_MASK      (0x20U)
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_SHIFT     (5U)
+/*! BT_CLK_EN_SEL - selection for bt_clk_en when PLL ready */
+#define APU_BT_CKEN_CTRL_BT_CLK_EN_SEL(x)        (((uint32_t)(((uint32_t)(x)) << APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_SHIFT)) & APU_BT_CKEN_CTRL_BT_CLK_EN_SEL_MASK)
+/*! @} */
+
+/*! @name BT_RESRC_CTRL - Bluetooth RESRC Control */
+/*! @{ */
+
+#define APU_BT_RESRC_CTRL_FW_PWR_REQ_MASK        (0x1U)
+#define APU_BT_RESRC_CTRL_FW_PWR_REQ_SHIFT       (0U)
+/*! FW_PWR_REQ - override hw power request */
+#define APU_BT_RESRC_CTRL_FW_PWR_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_PWR_REQ_SHIFT)) & APU_BT_RESRC_CTRL_FW_PWR_REQ_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_PWR_REQ_VAL_MASK    (0x2U)
+#define APU_BT_RESRC_CTRL_FW_PWR_REQ_VAL_SHIFT   (1U)
+/*! FW_PWR_REQ_VAL - override value when apu_bt_resrc_ctrl[0] is set */
+#define APU_BT_RESRC_CTRL_FW_PWR_REQ_VAL(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_PWR_REQ_VAL_SHIFT)) & APU_BT_RESRC_CTRL_FW_PWR_REQ_VAL_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_XOSC_REQ_MASK       (0x4U)
+#define APU_BT_RESRC_CTRL_FW_XOSC_REQ_SHIFT      (2U)
+/*! FW_XOSC_REQ - override hw xosc request */
+#define APU_BT_RESRC_CTRL_FW_XOSC_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_XOSC_REQ_SHIFT)) & APU_BT_RESRC_CTRL_FW_XOSC_REQ_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_XOSC_REQ_VAL_MASK   (0x8U)
+#define APU_BT_RESRC_CTRL_FW_XOSC_REQ_VAL_SHIFT  (3U)
+/*! FW_XOSC_REQ_VAL - override value when apu_bt_resrc_ctrl[2] is set */
+#define APU_BT_RESRC_CTRL_FW_XOSC_REQ_VAL(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_XOSC_REQ_VAL_SHIFT)) & APU_BT_RESRC_CTRL_FW_XOSC_REQ_VAL_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_XP_REQ_MASK         (0x10U)
+#define APU_BT_RESRC_CTRL_FW_XP_REQ_SHIFT        (4U)
+/*! FW_XP_REQ - override hw xosc + pwr request */
+#define APU_BT_RESRC_CTRL_FW_XP_REQ(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_XP_REQ_SHIFT)) & APU_BT_RESRC_CTRL_FW_XP_REQ_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_XP_REQ_VAL_MASK     (0x20U)
+#define APU_BT_RESRC_CTRL_FW_XP_REQ_VAL_SHIFT    (5U)
+/*! FW_XP_REQ_VAL - override value when apu_bt_resrc_ctrl[4] is set */
+#define APU_BT_RESRC_CTRL_FW_XP_REQ_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_XP_REQ_VAL_SHIFT)) & APU_BT_RESRC_CTRL_FW_XP_REQ_VAL_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_SB_REQ_MASK         (0x40U)
+#define APU_BT_RESRC_CTRL_FW_SB_REQ_SHIFT        (6U)
+/*! FW_SB_REQ - override hw xosc + pwr + pll sb request */
+#define APU_BT_RESRC_CTRL_FW_SB_REQ(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_SB_REQ_SHIFT)) & APU_BT_RESRC_CTRL_FW_SB_REQ_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_SB_REQ_VAL_MASK     (0x80U)
+#define APU_BT_RESRC_CTRL_FW_SB_REQ_VAL_SHIFT    (7U)
+/*! FW_SB_REQ_VAL - override value when apu_bt_resrc_ctrl[6] is set */
+#define APU_BT_RESRC_CTRL_FW_SB_REQ_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_SB_REQ_VAL_SHIFT)) & APU_BT_RESRC_CTRL_FW_SB_REQ_VAL_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_MASK     (0x100U)
+#define APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_SHIFT    (8U)
+/*! FW_IPWAKE_REQ - override hw xosc + pwr + pll ipwake request */
+#define APU_BT_RESRC_CTRL_FW_IPWAKE_REQ(x)       (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_SHIFT)) & APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_VAL_MASK (0x200U)
+#define APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_VAL_SHIFT (9U)
+/*! FW_IPWAKE_REQ_VAL - override value when apu_bt_resrc_ctrl[8] is set */
+#define APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_VAL(x)   (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_VAL_SHIFT)) & APU_BT_RESRC_CTRL_FW_IPWAKE_REQ_VAL_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_MASK    (0x400U)
+#define APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_SHIFT   (10U)
+/*! FW_ALLWAKE_REQ - firmware override hw xosc + pwr + pll allwake request */
+#define APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_SHIFT)) & APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_MASK)
+
+#define APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_MASK (0x800U)
+#define APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_SHIFT (11U)
+/*! FW_ALLWAKE_REQ_VAL - firmware override value when apu_bt_resrc_ctrl[10] is set */
+#define APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_VAL(x)  (((uint32_t)(((uint32_t)(x)) << APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_SHIFT)) & APU_BT_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_MASK)
+/*! @} */
+
+/*! @name BT_DVFS_CTRL - Bluetooth DVFS Control */
+/*! @{ */
+
+#define APU_BT_DVFS_CTRL_BT_VOL_VAL_MASK         (0x7FU)
+#define APU_BT_DVFS_CTRL_BT_VOL_VAL_SHIFT        (0U)
+/*! BT_VOL_VAL - Blueooth Vol Value */
+#define APU_BT_DVFS_CTRL_BT_VOL_VAL(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT_DVFS_CTRL_BT_VOL_VAL_SHIFT)) & APU_BT_DVFS_CTRL_BT_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name FM_CTRL - FM Control */
+/*! @{ */
+
+#define APU_FM_CTRL_FM_SLP_RDY_MASK              (0x1U)
+#define APU_FM_CTRL_FM_SLP_RDY_SHIFT             (0U)
+/*! FM_SLP_RDY - FM Sleep Delay */
+#define APU_FM_CTRL_FM_SLP_RDY(x)                (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_FM_SLP_RDY_SHIFT)) & APU_FM_CTRL_FM_SLP_RDY_MASK)
+
+#define APU_FM_CTRL_FM_SLP_RDYMASK_MASK          (0x2U)
+#define APU_FM_CTRL_FM_SLP_RDYMASK_SHIFT         (1U)
+/*! FM_SLP_RDYMASK - FM Sleep Ready Mask */
+#define APU_FM_CTRL_FM_SLP_RDYMASK(x)            (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_FM_SLP_RDYMASK_SHIFT)) & APU_FM_CTRL_FM_SLP_RDYMASK_MASK)
+
+#define APU_FM_CTRL_FM_SLP_RDY_FW_MASK           (0x4U)
+#define APU_FM_CTRL_FM_SLP_RDY_FW_SHIFT          (2U)
+/*! FM_SLP_RDY_FW - FM Sleep Ready FW */
+#define APU_FM_CTRL_FM_SLP_RDY_FW(x)             (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_FM_SLP_RDY_FW_SHIFT)) & APU_FM_CTRL_FM_SLP_RDY_FW_MASK)
+
+#define APU_FM_CTRL_FM_PRESENT_MASK              (0x8U)
+#define APU_FM_CTRL_FM_PRESENT_SHIFT             (3U)
+/*! FM_PRESENT - FM Present */
+#define APU_FM_CTRL_FM_PRESENT(x)                (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_FM_PRESENT_SHIFT)) & APU_FM_CTRL_FM_PRESENT_MASK)
+
+#define APU_FM_CTRL_FM_DYN_VOL_EN_MASK           (0x10U)
+#define APU_FM_CTRL_FM_DYN_VOL_EN_SHIFT          (4U)
+/*! FM_DYN_VOL_EN - FM Dynamic Vol Enable */
+#define APU_FM_CTRL_FM_DYN_VOL_EN(x)             (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_FM_DYN_VOL_EN_SHIFT)) & APU_FM_CTRL_FM_DYN_VOL_EN_MASK)
+
+#define APU_FM_CTRL_FM_CLK_SYNC_MODE_SEL_MASK    (0x20U)
+#define APU_FM_CTRL_FM_CLK_SYNC_MODE_SEL_SHIFT   (5U)
+/*! FM_CLK_SYNC_MODE_SEL - FM Clock Sync Mode Select */
+#define APU_FM_CTRL_FM_CLK_SYNC_MODE_SEL(x)      (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_FM_CLK_SYNC_MODE_SEL_SHIFT)) & APU_FM_CTRL_FM_CLK_SYNC_MODE_SEL_MASK)
+
+#define APU_FM_CTRL_USE_FM_INTR_SLP_MASK         (0x80U)
+#define APU_FM_CTRL_USE_FM_INTR_SLP_SHIFT        (7U)
+/*! USE_FM_INTR_SLP - Use FM Interrupt Sleep */
+#define APU_FM_CTRL_USE_FM_INTR_SLP(x)           (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_USE_FM_INTR_SLP_SHIFT)) & APU_FM_CTRL_USE_FM_INTR_SLP_MASK)
+
+#define APU_FM_CTRL_FM_HOST_SLP_RDY_MASK         (0x80000000U)
+#define APU_FM_CTRL_FM_HOST_SLP_RDY_SHIFT        (31U)
+/*! FM_HOST_SLP_RDY - FM Host Sleep Ready */
+#define APU_FM_CTRL_FM_HOST_SLP_RDY(x)           (((uint32_t)(((uint32_t)(x)) << APU_FM_CTRL_FM_HOST_SLP_RDY_SHIFT)) & APU_FM_CTRL_FM_HOST_SLP_RDY_MASK)
+/*! @} */
+
+/*! @name FM_WKUP_MASK - FM Wakeup Mask */
+/*! @{ */
+
+#define APU_FM_WKUP_MASK_FM_CLK_REQ_MASK_MASK    (0x1U)
+#define APU_FM_WKUP_MASK_FM_CLK_REQ_MASK_SHIFT   (0U)
+/*! FM_CLK_REQ_MASK - FM Clock Request Mask */
+#define APU_FM_WKUP_MASK_FM_CLK_REQ_MASK(x)      (((uint32_t)(((uint32_t)(x)) << APU_FM_WKUP_MASK_FM_CLK_REQ_MASK_SHIFT)) & APU_FM_WKUP_MASK_FM_CLK_REQ_MASK_MASK)
+
+#define APU_FM_WKUP_MASK_FM_INTR_MASK_MASK       (0x2U)
+#define APU_FM_WKUP_MASK_FM_INTR_MASK_SHIFT      (1U)
+/*! FM_INTR_MASK - FM Interrupt Mask */
+#define APU_FM_WKUP_MASK_FM_INTR_MASK(x)         (((uint32_t)(((uint32_t)(x)) << APU_FM_WKUP_MASK_FM_INTR_MASK_SHIFT)) & APU_FM_WKUP_MASK_FM_INTR_MASK_MASK)
+
+#define APU_FM_WKUP_MASK_FM_PRESENT_MASK_MASK    (0x4U)
+#define APU_FM_WKUP_MASK_FM_PRESENT_MASK_SHIFT   (2U)
+/*! FM_PRESENT_MASK - FM Present Mask */
+#define APU_FM_WKUP_MASK_FM_PRESENT_MASK(x)      (((uint32_t)(((uint32_t)(x)) << APU_FM_WKUP_MASK_FM_PRESENT_MASK_SHIFT)) & APU_FM_WKUP_MASK_FM_PRESENT_MASK_MASK)
+
+#define APU_FM_WKUP_MASK_FM_HOST_MAP_MASK        (0xFFFF0000U)
+#define APU_FM_WKUP_MASK_FM_HOST_MAP_SHIFT       (16U)
+/*! FM_HOST_MAP - FM to host-HOST Delay */
+#define APU_FM_WKUP_MASK_FM_HOST_MAP(x)          (((uint32_t)(((uint32_t)(x)) << APU_FM_WKUP_MASK_FM_HOST_MAP_SHIFT)) & APU_FM_WKUP_MASK_FM_HOST_MAP_MASK)
+/*! @} */
+
+/*! @name FM_STATUS - FM Status */
+/*! @{ */
+
+#define APU_FM_STATUS_APU_FM_CLK_EN_MASK         (0x1U)
+#define APU_FM_STATUS_APU_FM_CLK_EN_SHIFT        (0U)
+/*! APU_FM_CLK_EN - APU FM Clock Enable */
+#define APU_FM_STATUS_APU_FM_CLK_EN(x)           (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_APU_FM_CLK_EN_SHIFT)) & APU_FM_STATUS_APU_FM_CLK_EN_MASK)
+
+#define APU_FM_STATUS_SOC_CLK_EN2_MASK           (0x2U)
+#define APU_FM_STATUS_SOC_CLK_EN2_SHIFT          (1U)
+/*! SOC_CLK_EN2 - SoC Clock Enable 2 */
+#define APU_FM_STATUS_SOC_CLK_EN2(x)             (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_SOC_CLK_EN2_SHIFT)) & APU_FM_STATUS_SOC_CLK_EN2_MASK)
+
+#define APU_FM_STATUS_XOSC_STABLE_REFCK_MASK     (0x4U)
+#define APU_FM_STATUS_XOSC_STABLE_REFCK_SHIFT    (2U)
+/*! XOSC_STABLE_REFCK - XOSC Stable Ref Clock */
+#define APU_FM_STATUS_XOSC_STABLE_REFCK(x)       (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_XOSC_STABLE_REFCK_SHIFT)) & APU_FM_STATUS_XOSC_STABLE_REFCK_MASK)
+
+#define APU_FM_STATUS_FM_HOST_WKUP_MASK          (0x10U)
+#define APU_FM_STATUS_FM_HOST_WKUP_SHIFT         (4U)
+/*! FM_HOST_WKUP - FM Host Wakeup */
+#define APU_FM_STATUS_FM_HOST_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_FM_HOST_WKUP_SHIFT)) & APU_FM_STATUS_FM_HOST_WKUP_MASK)
+
+#define APU_FM_STATUS_FM_INTR_MASK               (0x20U)
+#define APU_FM_STATUS_FM_INTR_SHIFT              (5U)
+/*! FM_INTR - FM Interrupt */
+#define APU_FM_STATUS_FM_INTR(x)                 (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_FM_INTR_SHIFT)) & APU_FM_STATUS_FM_INTR_MASK)
+
+#define APU_FM_STATUS_FM_CLK_REQ_MASK            (0x40U)
+#define APU_FM_STATUS_FM_CLK_REQ_SHIFT           (6U)
+/*! FM_CLK_REQ - FM Clock Request */
+#define APU_FM_STATUS_FM_CLK_REQ(x)              (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_FM_CLK_REQ_SHIFT)) & APU_FM_STATUS_FM_CLK_REQ_MASK)
+
+#define APU_FM_STATUS_FM_PRESENT_MASK            (0x80U)
+#define APU_FM_STATUS_FM_PRESENT_SHIFT           (7U)
+/*! FM_PRESENT - FM Present */
+#define APU_FM_STATUS_FM_PRESENT(x)              (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_FM_PRESENT_SHIFT)) & APU_FM_STATUS_FM_PRESENT_MASK)
+
+#define APU_FM_STATUS_HOST_WKUP_IN_MASK          (0xFFFF0000U)
+#define APU_FM_STATUS_HOST_WKUP_IN_SHIFT         (16U)
+/*! HOST_WKUP_IN - Host Wakeup Interrupt */
+#define APU_FM_STATUS_HOST_WKUP_IN(x)            (((uint32_t)(((uint32_t)(x)) << APU_FM_STATUS_HOST_WKUP_IN_SHIFT)) & APU_FM_STATUS_HOST_WKUP_IN_MASK)
+/*! @} */
+
+/*! @name FM_CKEN_CTRL - FM Clock Enable Control */
+/*! @{ */
+
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_VAL_MASK  (0x1U)
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_VAL_SHIFT (0U)
+/*! FM_CLK_EN_PWR_VAL - control value for fm_clk_en when power ready */
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_VAL(x)    (((uint32_t)(((uint32_t)(x)) << APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_VAL_SHIFT)) & APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_VAL_MASK)
+
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_SEL_MASK  (0x2U)
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_SEL_SHIFT (1U)
+/*! FM_CLK_EN_PWR_SEL - selection for fm_clk_en when power ready */
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_SEL(x)    (((uint32_t)(((uint32_t)(x)) << APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_SEL_SHIFT)) & APU_FM_CKEN_CTRL_FM_CLK_EN_PWR_SEL_MASK)
+
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_VAL_MASK (0x4U)
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_VAL_SHIFT (2U)
+/*! FM_CLK_EN_XOSC_VAL - control value for fm_clk_en when xosc is ready */
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_VAL(x)   (((uint32_t)(((uint32_t)(x)) << APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_VAL_SHIFT)) & APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_VAL_MASK)
+
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_SEL_MASK (0x8U)
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_SEL_SHIFT (3U)
+/*! FM_CLK_EN_XOSC_SEL - selection for fm_clk_en when XOSC ready */
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_SEL(x)   (((uint32_t)(((uint32_t)(x)) << APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_SEL_SHIFT)) & APU_FM_CKEN_CTRL_FM_CLK_EN_XOSC_SEL_MASK)
+
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_VAL_MASK  (0x10U)
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_VAL_SHIFT (4U)
+/*! FM_CLK_EN_PLL_VAL - control value for fm_clk_en when PLL ready */
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_VAL(x)    (((uint32_t)(((uint32_t)(x)) << APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_VAL_SHIFT)) & APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_VAL_MASK)
+
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_SEL_MASK  (0x20U)
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_SEL_SHIFT (5U)
+/*! FM_CLK_EN_PLL_SEL - selection for fm_clk_en when PLL ready */
+#define APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_SEL(x)    (((uint32_t)(((uint32_t)(x)) << APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_SEL_SHIFT)) & APU_FM_CKEN_CTRL_FM_CLK_EN_PLL_SEL_MASK)
+/*! @} */
+
+/*! @name FM_RESRC_CTRL - FM RESRC Control */
+/*! @{ */
+
+#define APU_FM_RESRC_CTRL_FM_PWR_REQ_MASK        (0x1U)
+#define APU_FM_RESRC_CTRL_FM_PWR_REQ_SHIFT       (0U)
+/*! FM_PWR_REQ - override hw power request */
+#define APU_FM_RESRC_CTRL_FM_PWR_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_PWR_REQ_SHIFT)) & APU_FM_RESRC_CTRL_FM_PWR_REQ_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_PWR_REQ_VAL_MASK    (0x2U)
+#define APU_FM_RESRC_CTRL_FM_PWR_REQ_VAL_SHIFT   (1U)
+/*! FM_PWR_REQ_VAL - override value when apu_fm_resrc_ctrl[0] is set */
+#define APU_FM_RESRC_CTRL_FM_PWR_REQ_VAL(x)      (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_PWR_REQ_VAL_SHIFT)) & APU_FM_RESRC_CTRL_FM_PWR_REQ_VAL_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_XOSC_REQ_MASK       (0x4U)
+#define APU_FM_RESRC_CTRL_FM_XOSC_REQ_SHIFT      (2U)
+/*! FM_XOSC_REQ - override hw xosc request */
+#define APU_FM_RESRC_CTRL_FM_XOSC_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_XOSC_REQ_SHIFT)) & APU_FM_RESRC_CTRL_FM_XOSC_REQ_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_XOSC_REQ_VAL_MASK   (0x8U)
+#define APU_FM_RESRC_CTRL_FM_XOSC_REQ_VAL_SHIFT  (3U)
+/*! FM_XOSC_REQ_VAL - override value when apu_fm_resrc_ctrl[2] is set */
+#define APU_FM_RESRC_CTRL_FM_XOSC_REQ_VAL(x)     (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_XOSC_REQ_VAL_SHIFT)) & APU_FM_RESRC_CTRL_FM_XOSC_REQ_VAL_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_XP_REQ_MASK         (0x10U)
+#define APU_FM_RESRC_CTRL_FM_XP_REQ_SHIFT        (4U)
+/*! FM_XP_REQ - override hw xosc + pwr request */
+#define APU_FM_RESRC_CTRL_FM_XP_REQ(x)           (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_XP_REQ_SHIFT)) & APU_FM_RESRC_CTRL_FM_XP_REQ_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_XP_REQ_VAL_MASK     (0x20U)
+#define APU_FM_RESRC_CTRL_FM_XP_REQ_VAL_SHIFT    (5U)
+/*! FM_XP_REQ_VAL - override value when apu_fm_resrc_ctrl[4] is set */
+#define APU_FM_RESRC_CTRL_FM_XP_REQ_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_XP_REQ_VAL_SHIFT)) & APU_FM_RESRC_CTRL_FM_XP_REQ_VAL_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_SB_REQ_MASK         (0x40U)
+#define APU_FM_RESRC_CTRL_FM_SB_REQ_SHIFT        (6U)
+/*! FM_SB_REQ - override hw xosc + pwr + pll sb request */
+#define APU_FM_RESRC_CTRL_FM_SB_REQ(x)           (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_SB_REQ_SHIFT)) & APU_FM_RESRC_CTRL_FM_SB_REQ_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_SB_REQ_VAL_MASK     (0x80U)
+#define APU_FM_RESRC_CTRL_FM_SB_REQ_VAL_SHIFT    (7U)
+/*! FM_SB_REQ_VAL - override value when apu_fm_resrc_ctrl[6] is set */
+#define APU_FM_RESRC_CTRL_FM_SB_REQ_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_SB_REQ_VAL_SHIFT)) & APU_FM_RESRC_CTRL_FM_SB_REQ_VAL_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_MASK     (0x100U)
+#define APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_SHIFT    (8U)
+/*! FM_IPWAKE_REQ - override hw xosc + pwr + pll ipwake request */
+#define APU_FM_RESRC_CTRL_FM_IPWAKE_REQ(x)       (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_SHIFT)) & APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_VAL_MASK (0x200U)
+#define APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_VAL_SHIFT (9U)
+/*! FM_IPWAKE_REQ_VAL - override value when apu_fm_resrc_ctrl[8] is set */
+#define APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_VAL(x)   (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_VAL_SHIFT)) & APU_FM_RESRC_CTRL_FM_IPWAKE_REQ_VAL_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_MASK    (0x400U)
+#define APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_SHIFT   (10U)
+/*! FM_ALLWAKE_REQ - firmware override hw xosc + pwr + pll allwake request */
+#define APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ(x)      (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_SHIFT)) & APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_MASK)
+
+#define APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_VAL_MASK (0x800U)
+#define APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_VAL_SHIFT (11U)
+/*! FM_ALLWAKE_REQ_VAL - firmware override value when apu_fm_resrc_ctrl[10] is set */
+#define APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_VAL(x)  (((uint32_t)(((uint32_t)(x)) << APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_VAL_SHIFT)) & APU_FM_RESRC_CTRL_FM_ALLWAKE_REQ_VAL_MASK)
+/*! @} */
+
+/*! @name FM_DVFS_CTRL - FM DVFS Control */
+/*! @{ */
+
+#define APU_FM_DVFS_CTRL_FM_VOL_VAL_MASK         (0x7FU)
+#define APU_FM_DVFS_CTRL_FM_VOL_VAL_SHIFT        (0U)
+/*! FM_VOL_VAL - FM Vol Value */
+#define APU_FM_DVFS_CTRL_FM_VOL_VAL(x)           (((uint32_t)(((uint32_t)(x)) << APU_FM_DVFS_CTRL_FM_VOL_VAL_SHIFT)) & APU_FM_DVFS_CTRL_FM_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name USB_PWR_CTRL_DLY - USB FSM Power Control Delay */
+/*! @{ */
+
+#define APU_USB_PWR_CTRL_DLY_PWR_CTRL_DLY_MASK   (0xFFFFFFFFU)
+#define APU_USB_PWR_CTRL_DLY_PWR_CTRL_DLY_SHIFT  (0U)
+/*! PWR_CTRL_DLY - USB FSM Power Control Delay */
+#define APU_USB_PWR_CTRL_DLY_PWR_CTRL_DLY(x)     (((uint32_t)(((uint32_t)(x)) << APU_USB_PWR_CTRL_DLY_PWR_CTRL_DLY_SHIFT)) & APU_USB_PWR_CTRL_DLY_PWR_CTRL_DLY_MASK)
+/*! @} */
+
+/*! @name USB_PWR_CTRL_DLY2 - USB FSM Power Control Delay 2 */
+/*! @{ */
+
+#define APU_USB_PWR_CTRL_DLY2_PWR_CTRL_DLY2_MASK (0xFFFFFFFFU)
+#define APU_USB_PWR_CTRL_DLY2_PWR_CTRL_DLY2_SHIFT (0U)
+/*! PWR_CTRL_DLY2 - USB FSM Power Control Delay 2 */
+#define APU_USB_PWR_CTRL_DLY2_PWR_CTRL_DLY2(x)   (((uint32_t)(((uint32_t)(x)) << APU_USB_PWR_CTRL_DLY2_PWR_CTRL_DLY2_SHIFT)) & APU_USB_PWR_CTRL_DLY2_PWR_CTRL_DLY2_MASK)
+/*! @} */
+
+/*! @name WLCOMN_PWR_CTRL_DLY - Wlan common domain FSM Power Control Delay */
+/*! @{ */
+
+#define APU_WLCOMN_PWR_CTRL_DLY_PWR_CTRL_DLY_MASK (0xFFFFFFFFU)
+#define APU_WLCOMN_PWR_CTRL_DLY_PWR_CTRL_DLY_SHIFT (0U)
+/*! PWR_CTRL_DLY - WLAN COMN FSM power control delay */
+#define APU_WLCOMN_PWR_CTRL_DLY_PWR_CTRL_DLY(x)  (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_DLY_PWR_CTRL_DLY_SHIFT)) & APU_WLCOMN_PWR_CTRL_DLY_PWR_CTRL_DLY_MASK)
+/*! @} */
+
+/*! @name WLCOMN_PWR_CTRL_DLY2 - Wlan common domain FSM Power Control Delay 2 */
+/*! @{ */
+
+#define APU_WLCOMN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_MASK (0xFFFFFFFFU)
+#define APU_WLCOMN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_SHIFT (0U)
+/*! PWR_CTRL_DLY2 - WLAN COMN FSM power control delay */
+#define APU_WLCOMN_PWR_CTRL_DLY2_PWR_CTRL_DLY2(x) (((uint32_t)(((uint32_t)(x)) << APU_WLCOMN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_SHIFT)) & APU_WLCOMN_PWR_CTRL_DLY2_PWR_CTRL_DLY2_MASK)
+/*! @} */
+
+/*! @name BLE_CTRL - BLE Control */
+/*! @{ */
+
+#define APU_BLE_CTRL_BLE_SLP_RDY_MASK            (0x1U)
+#define APU_BLE_CTRL_BLE_SLP_RDY_SHIFT           (0U)
+/*! BLE_SLP_RDY - BLE Sleep Ready */
+#define APU_BLE_CTRL_BLE_SLP_RDY(x)              (((uint32_t)(((uint32_t)(x)) << APU_BLE_CTRL_BLE_SLP_RDY_SHIFT)) & APU_BLE_CTRL_BLE_SLP_RDY_MASK)
+
+#define APU_BLE_CTRL_BLE_SLP_RDYMASK_MASK        (0x2U)
+#define APU_BLE_CTRL_BLE_SLP_RDYMASK_SHIFT       (1U)
+/*! BLE_SLP_RDYMASK - BLE Sleep Ready Mask */
+#define APU_BLE_CTRL_BLE_SLP_RDYMASK(x)          (((uint32_t)(((uint32_t)(x)) << APU_BLE_CTRL_BLE_SLP_RDYMASK_SHIFT)) & APU_BLE_CTRL_BLE_SLP_RDYMASK_MASK)
+
+#define APU_BLE_CTRL_BLE_SLP_RDY_FW_MASK         (0x4U)
+#define APU_BLE_CTRL_BLE_SLP_RDY_FW_SHIFT        (2U)
+/*! BLE_SLP_RDY_FW - BLE Sleep Ready FW */
+#define APU_BLE_CTRL_BLE_SLP_RDY_FW(x)           (((uint32_t)(((uint32_t)(x)) << APU_BLE_CTRL_BLE_SLP_RDY_FW_SHIFT)) & APU_BLE_CTRL_BLE_SLP_RDY_FW_MASK)
+
+#define APU_BLE_CTRL_BLE_MODE_EN_MASK            (0x8U)
+#define APU_BLE_CTRL_BLE_MODE_EN_SHIFT           (3U)
+/*! BLE_MODE_EN - BLE Mode Enable */
+#define APU_BLE_CTRL_BLE_MODE_EN(x)              (((uint32_t)(((uint32_t)(x)) << APU_BLE_CTRL_BLE_MODE_EN_SHIFT)) & APU_BLE_CTRL_BLE_MODE_EN_MASK)
+
+#define APU_BLE_CTRL_BT_AES_NCO_MODE_MASK        (0x8000U)
+#define APU_BLE_CTRL_BT_AES_NCO_MODE_SHIFT       (15U)
+/*! BT_AES_NCO_MODE - Bluetooth AES NCO Mode */
+#define APU_BLE_CTRL_BT_AES_NCO_MODE(x)          (((uint32_t)(((uint32_t)(x)) << APU_BLE_CTRL_BT_AES_NCO_MODE_SHIFT)) & APU_BLE_CTRL_BT_AES_NCO_MODE_MASK)
+
+#define APU_BLE_CTRL_BLE_XP_REQ_MASK             (0x80000000U)
+#define APU_BLE_CTRL_BLE_XP_REQ_SHIFT            (31U)
+/*! BLE_XP_REQ - BLE XP Request */
+#define APU_BLE_CTRL_BLE_XP_REQ(x)               (((uint32_t)(((uint32_t)(x)) << APU_BLE_CTRL_BLE_XP_REQ_SHIFT)) & APU_BLE_CTRL_BLE_XP_REQ_MASK)
+/*! @} */
+
+/*! @name BLE_WKUP_MASK - BLE Wakeup Mask */
+/*! @{ */
+
+#define APU_BLE_WKUP_MASK_BT_AES_CLK_REQ_MASK_MASK (0x8U)
+#define APU_BLE_WKUP_MASK_BT_AES_CLK_REQ_MASK_SHIFT (3U)
+/*! BT_AES_CLK_REQ_MASK - Bluetooth AES Clock Request Mask */
+#define APU_BLE_WKUP_MASK_BT_AES_CLK_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_BLE_WKUP_MASK_BT_AES_CLK_REQ_MASK_SHIFT)) & APU_BLE_WKUP_MASK_BT_AES_CLK_REQ_MASK_MASK)
+
+#define APU_BLE_WKUP_MASK_LBC_XP_REQ_MASK_MASK   (0x10U)
+#define APU_BLE_WKUP_MASK_LBC_XP_REQ_MASK_SHIFT  (4U)
+/*! LBC_XP_REQ_MASK - LBC XP Request Mask */
+#define APU_BLE_WKUP_MASK_LBC_XP_REQ_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_BLE_WKUP_MASK_LBC_XP_REQ_MASK_SHIFT)) & APU_BLE_WKUP_MASK_LBC_XP_REQ_MASK_MASK)
+/*! @} */
+
+/*! @name BLE_STATUS - BLE Status */
+/*! @{ */
+
+#define APU_BLE_STATUS_APU_BT_AES_CLK_EN_MASK    (0x1U)
+#define APU_BLE_STATUS_APU_BT_AES_CLK_EN_SHIFT   (0U)
+/*! APU_BT_AES_CLK_EN - APU Bluetooth AES Clock Enable */
+#define APU_BLE_STATUS_APU_BT_AES_CLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_APU_BT_AES_CLK_EN_SHIFT)) & APU_BLE_STATUS_APU_BT_AES_CLK_EN_MASK)
+
+#define APU_BLE_STATUS_BT_AES_CLK_SEL_MASK       (0x2U)
+#define APU_BLE_STATUS_BT_AES_CLK_SEL_SHIFT      (1U)
+/*! BT_AES_CLK_SEL - Bluetooth AES Clock Select */
+#define APU_BLE_STATUS_BT_AES_CLK_SEL(x)         (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_BT_AES_CLK_SEL_SHIFT)) & APU_BLE_STATUS_BT_AES_CLK_SEL_MASK)
+
+#define APU_BLE_STATUS_XOSC_STABLE_REFCK_MASK    (0x4U)
+#define APU_BLE_STATUS_XOSC_STABLE_REFCK_SHIFT   (2U)
+/*! XOSC_STABLE_REFCK - XOSC Stable Ref Clock */
+#define APU_BLE_STATUS_XOSC_STABLE_REFCK(x)      (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_XOSC_STABLE_REFCK_SHIFT)) & APU_BLE_STATUS_XOSC_STABLE_REFCK_MASK)
+
+#define APU_BLE_STATUS_T1_STABLE_MASK            (0x8U)
+#define APU_BLE_STATUS_T1_STABLE_SHIFT           (3U)
+/*! T1_STABLE - T1 Delay */
+#define APU_BLE_STATUS_T1_STABLE(x)              (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_T1_STABLE_SHIFT)) & APU_BLE_STATUS_T1_STABLE_MASK)
+
+#define APU_BLE_STATUS_BT_INTERRUPT_MASK         (0x10U)
+#define APU_BLE_STATUS_BT_INTERRUPT_SHIFT        (4U)
+/*! BT_INTERRUPT - Bluetooth Interrupt */
+#define APU_BLE_STATUS_BT_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_BT_INTERRUPT_SHIFT)) & APU_BLE_STATUS_BT_INTERRUPT_MASK)
+
+#define APU_BLE_STATUS_BLE_XP_REQ_MASK           (0x20U)
+#define APU_BLE_STATUS_BLE_XP_REQ_SHIFT          (5U)
+/*! BLE_XP_REQ - BLE XP Request */
+#define APU_BLE_STATUS_BLE_XP_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_BLE_XP_REQ_SHIFT)) & APU_BLE_STATUS_BLE_XP_REQ_MASK)
+
+#define APU_BLE_STATUS_BT_AES_NCO_MODE_MASK      (0x40U)
+#define APU_BLE_STATUS_BT_AES_NCO_MODE_SHIFT     (6U)
+/*! BT_AES_NCO_MODE - Blueooth AES NCO Mode */
+#define APU_BLE_STATUS_BT_AES_NCO_MODE(x)        (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_BT_AES_NCO_MODE_SHIFT)) & APU_BLE_STATUS_BT_AES_NCO_MODE_MASK)
+
+#define APU_BLE_STATUS_LBC_XP_REQ_MASK           (0x100U)
+#define APU_BLE_STATUS_LBC_XP_REQ_SHIFT          (8U)
+/*! LBC_XP_REQ - LBC XP Request */
+#define APU_BLE_STATUS_LBC_XP_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_LBC_XP_REQ_SHIFT)) & APU_BLE_STATUS_LBC_XP_REQ_MASK)
+
+#define APU_BLE_STATUS_BT_AES_CLK_REQ_MASK       (0x200U)
+#define APU_BLE_STATUS_BT_AES_CLK_REQ_SHIFT      (9U)
+/*! BT_AES_CLK_REQ - Bluetooth AES Clock Request Mask */
+#define APU_BLE_STATUS_BT_AES_CLK_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_BLE_STATUS_BT_AES_CLK_REQ_SHIFT)) & APU_BLE_STATUS_BT_AES_CLK_REQ_MASK)
+/*! @} */
+
+/*! @name NFC_CTRL - NFC Control */
+/*! @{ */
+
+#define APU_NFC_CTRL_NFC_SLP_RDY_MASK            (0x1U)
+#define APU_NFC_CTRL_NFC_SLP_RDY_SHIFT           (0U)
+/*! NFC_SLP_RDY - NFC Sleep Ready */
+#define APU_NFC_CTRL_NFC_SLP_RDY(x)              (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_SLP_RDY_SHIFT)) & APU_NFC_CTRL_NFC_SLP_RDY_MASK)
+
+#define APU_NFC_CTRL_NFC_SLP_RDYMASK_MASK        (0x2U)
+#define APU_NFC_CTRL_NFC_SLP_RDYMASK_SHIFT       (1U)
+/*! NFC_SLP_RDYMASK - NFC Sleep Ready Mask */
+#define APU_NFC_CTRL_NFC_SLP_RDYMASK(x)          (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_SLP_RDYMASK_SHIFT)) & APU_NFC_CTRL_NFC_SLP_RDYMASK_MASK)
+
+#define APU_NFC_CTRL_NFC_SLP_RDY_FW_MASK         (0x4U)
+#define APU_NFC_CTRL_NFC_SLP_RDY_FW_SHIFT        (2U)
+/*! NFC_SLP_RDY_FW - NFC Sleep Ready FW */
+#define APU_NFC_CTRL_NFC_SLP_RDY_FW(x)           (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_SLP_RDY_FW_SHIFT)) & APU_NFC_CTRL_NFC_SLP_RDY_FW_MASK)
+
+#define APU_NFC_CTRL_USE_NFC_REF_ONLY_MASK       (0x8U)
+#define APU_NFC_CTRL_USE_NFC_REF_ONLY_SHIFT      (3U)
+/*! USE_NFC_REF_ONLY - Use NFC Reference Only */
+#define APU_NFC_CTRL_USE_NFC_REF_ONLY(x)         (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_USE_NFC_REF_ONLY_SHIFT)) & APU_NFC_CTRL_USE_NFC_REF_ONLY_MASK)
+
+#define APU_NFC_CTRL_USE_NFC_INTR_SLP_MASK       (0x10U)
+#define APU_NFC_CTRL_USE_NFC_INTR_SLP_SHIFT      (4U)
+/*! USE_NFC_INTR_SLP - Use NFC Interrupt Sleep */
+#define APU_NFC_CTRL_USE_NFC_INTR_SLP(x)         (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_USE_NFC_INTR_SLP_SHIFT)) & APU_NFC_CTRL_USE_NFC_INTR_SLP_MASK)
+
+#define APU_NFC_CTRL_NFC_USE_SOC_PWR_SEQ_MASK    (0x20U)
+#define APU_NFC_CTRL_NFC_USE_SOC_PWR_SEQ_SHIFT   (5U)
+/*! NFC_USE_SOC_PWR_SEQ - Use SoC power sequence for NFC as well */
+#define APU_NFC_CTRL_NFC_USE_SOC_PWR_SEQ(x)      (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_USE_SOC_PWR_SEQ_SHIFT)) & APU_NFC_CTRL_NFC_USE_SOC_PWR_SEQ_MASK)
+
+#define APU_NFC_CTRL_FW_CLR_NFC_INTR_MASK        (0x80U)
+#define APU_NFC_CTRL_FW_CLR_NFC_INTR_SHIFT       (7U)
+/*! FW_CLR_NFC_INTR - FW Clear NFC Interrupt */
+#define APU_NFC_CTRL_FW_CLR_NFC_INTR(x)          (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_FW_CLR_NFC_INTR_SHIFT)) & APU_NFC_CTRL_FW_CLR_NFC_INTR_MASK)
+
+#define APU_NFC_CTRL_NFC_USE_CPU2_SUBSLP_MASK    (0x100U)
+#define APU_NFC_CTRL_NFC_USE_CPU2_SUBSLP_SHIFT   (8U)
+/*! NFC_USE_CPU2_SUBSLP - Use CPU2 subsystem sleep for NFC power down */
+#define APU_NFC_CTRL_NFC_USE_CPU2_SUBSLP(x)      (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_USE_CPU2_SUBSLP_SHIFT)) & APU_NFC_CTRL_NFC_USE_CPU2_SUBSLP_MASK)
+
+#define APU_NFC_CTRL_NFC_USE_NOM_PWR_BYP_MASK    (0x200U)
+#define APU_NFC_CTRL_NFC_USE_NOM_PWR_BYP_SHIFT   (9U)
+/*! NFC_USE_NOM_PWR_BYP - Use nom_pwr_lvl from dvfs for nfc_pwr_lvl_reached */
+#define APU_NFC_CTRL_NFC_USE_NOM_PWR_BYP(x)      (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_USE_NOM_PWR_BYP_SHIFT)) & APU_NFC_CTRL_NFC_USE_NOM_PWR_BYP_MASK)
+
+#define APU_NFC_CTRL_FW_FORCE_NFC_PWRUP_MASK     (0x1000000U)
+#define APU_NFC_CTRL_FW_FORCE_NFC_PWRUP_SHIFT    (24U)
+/*! FW_FORCE_NFC_PWRUP - FW Force NFC Powerup */
+#define APU_NFC_CTRL_FW_FORCE_NFC_PWRUP(x)       (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_FW_FORCE_NFC_PWRUP_SHIFT)) & APU_NFC_CTRL_FW_FORCE_NFC_PWRUP_MASK)
+
+#define APU_NFC_CTRL_NFC_USE_UNSYNC_PWR_LVL_MASK (0x2000000U)
+#define APU_NFC_CTRL_NFC_USE_UNSYNC_PWR_LVL_SHIFT (25U)
+/*! NFC_USE_UNSYNC_PWR_LVL - NFC Use Unsync Power Level */
+#define APU_NFC_CTRL_NFC_USE_UNSYNC_PWR_LVL(x)   (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_USE_UNSYNC_PWR_LVL_SHIFT)) & APU_NFC_CTRL_NFC_USE_UNSYNC_PWR_LVL_MASK)
+
+#define APU_NFC_CTRL_NFC_HOST_SLP_RDY_MASK       (0x80000000U)
+#define APU_NFC_CTRL_NFC_HOST_SLP_RDY_SHIFT      (31U)
+/*! NFC_HOST_SLP_RDY - NFC Host Sleep Ready */
+#define APU_NFC_CTRL_NFC_HOST_SLP_RDY(x)         (((uint32_t)(((uint32_t)(x)) << APU_NFC_CTRL_NFC_HOST_SLP_RDY_SHIFT)) & APU_NFC_CTRL_NFC_HOST_SLP_RDY_MASK)
+/*! @} */
+
+/*! @name NFC_WKUP_MASK - NFC Wakeup Mask */
+/*! @{ */
+
+#define APU_NFC_WKUP_MASK_NFC_P_WKUP_MASK_MASK   (0x1U)
+#define APU_NFC_WKUP_MASK_NFC_P_WKUP_MASK_SHIFT  (0U)
+/*! NFC_P_WKUP_MASK - NFC P Wakeup Mask */
+#define APU_NFC_WKUP_MASK_NFC_P_WKUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_NFC_WKUP_MASK_NFC_P_WKUP_MASK_SHIFT)) & APU_NFC_WKUP_MASK_NFC_P_WKUP_MASK_MASK)
+
+#define APU_NFC_WKUP_MASK_NFC_XP_WKUP_MASK_MASK  (0x2U)
+#define APU_NFC_WKUP_MASK_NFC_XP_WKUP_MASK_SHIFT (1U)
+/*! NFC_XP_WKUP_MASK - NFC XP Wakeup Mask */
+#define APU_NFC_WKUP_MASK_NFC_XP_WKUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_NFC_WKUP_MASK_NFC_XP_WKUP_MASK_SHIFT)) & APU_NFC_WKUP_MASK_NFC_XP_WKUP_MASK_MASK)
+
+#define APU_NFC_WKUP_MASK_NFC_INT_WKUP_MASK_MASK (0x4U)
+#define APU_NFC_WKUP_MASK_NFC_INT_WKUP_MASK_SHIFT (2U)
+/*! NFC_INT_WKUP_MASK - NFC Interrupt Wakeup Mask */
+#define APU_NFC_WKUP_MASK_NFC_INT_WKUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << APU_NFC_WKUP_MASK_NFC_INT_WKUP_MASK_SHIFT)) & APU_NFC_WKUP_MASK_NFC_INT_WKUP_MASK_MASK)
+
+#define APU_NFC_WKUP_MASK_NFC_HOST_MAP_MASK      (0xFFFF0000U)
+#define APU_NFC_WKUP_MASK_NFC_HOST_MAP_SHIFT     (16U)
+/*! NFC_HOST_MAP - NFC Host Map */
+#define APU_NFC_WKUP_MASK_NFC_HOST_MAP(x)        (((uint32_t)(((uint32_t)(x)) << APU_NFC_WKUP_MASK_NFC_HOST_MAP_SHIFT)) & APU_NFC_WKUP_MASK_NFC_HOST_MAP_MASK)
+/*! @} */
+
+/*! @name NFC_STATUS - NFC Status */
+/*! @{ */
+
+#define APU_NFC_STATUS_APU_NFC_AHBCLK_EN_MASK    (0x1U)
+#define APU_NFC_STATUS_APU_NFC_AHBCLK_EN_SHIFT   (0U)
+/*! APU_NFC_AHBCLK_EN - APU NFC AHB Clock Enable */
+#define APU_NFC_STATUS_APU_NFC_AHBCLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_APU_NFC_AHBCLK_EN_SHIFT)) & APU_NFC_STATUS_APU_NFC_AHBCLK_EN_MASK)
+
+#define APU_NFC_STATUS_NFC_INT_MASK              (0x2U)
+#define APU_NFC_STATUS_NFC_INT_SHIFT             (1U)
+/*! NFC_INT - NFC Interrupt */
+#define APU_NFC_STATUS_NFC_INT(x)                (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_NFC_INT_SHIFT)) & APU_NFC_STATUS_NFC_INT_MASK)
+
+#define APU_NFC_STATUS_NFC_XP_REQ_MASK           (0x4U)
+#define APU_NFC_STATUS_NFC_XP_REQ_SHIFT          (2U)
+/*! NFC_XP_REQ - NFC XP Req */
+#define APU_NFC_STATUS_NFC_XP_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_NFC_XP_REQ_SHIFT)) & APU_NFC_STATUS_NFC_XP_REQ_MASK)
+
+#define APU_NFC_STATUS_NFC_P_REQ_MASK            (0x8U)
+#define APU_NFC_STATUS_NFC_P_REQ_SHIFT           (3U)
+/*! NFC_P_REQ - NFC P Req */
+#define APU_NFC_STATUS_NFC_P_REQ(x)              (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_NFC_P_REQ_SHIFT)) & APU_NFC_STATUS_NFC_P_REQ_MASK)
+
+#define APU_NFC_STATUS_APU_NFC_SWITCH_PD_AON_MASK (0x10U)
+#define APU_NFC_STATUS_APU_NFC_SWITCH_PD_AON_SHIFT (4U)
+/*! APU_NFC_SWITCH_PD_AON - APU NFC Switch PD AON */
+#define APU_NFC_STATUS_APU_NFC_SWITCH_PD_AON(x)  (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_APU_NFC_SWITCH_PD_AON_SHIFT)) & APU_NFC_STATUS_APU_NFC_SWITCH_PD_AON_MASK)
+
+#define APU_NFC_STATUS_APU_NFC_UDR_FIREWALL_B_AON_MASK (0x20U)
+#define APU_NFC_STATUS_APU_NFC_UDR_FIREWALL_B_AON_SHIFT (5U)
+/*! APU_NFC_UDR_FIREWALL_B_AON - APU NFC UDR Firewall B AON */
+#define APU_NFC_STATUS_APU_NFC_UDR_FIREWALL_B_AON(x) (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_APU_NFC_UDR_FIREWALL_B_AON_SHIFT)) & APU_NFC_STATUS_APU_NFC_UDR_FIREWALL_B_AON_MASK)
+
+#define APU_NFC_STATUS_APU_NFC_CLK_DIV_RSTB_AON_MASK (0x40U)
+#define APU_NFC_STATUS_APU_NFC_CLK_DIV_RSTB_AON_SHIFT (6U)
+/*! APU_NFC_CLK_DIV_RSTB_AON - APU NFC Clock Divider RSTb AON */
+#define APU_NFC_STATUS_APU_NFC_CLK_DIV_RSTB_AON(x) (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_APU_NFC_CLK_DIV_RSTB_AON_SHIFT)) & APU_NFC_STATUS_APU_NFC_CLK_DIV_RSTB_AON_MASK)
+
+#define APU_NFC_STATUS_APU_NFC_ISO_EN_AON_MASK   (0x80U)
+#define APU_NFC_STATUS_APU_NFC_ISO_EN_AON_SHIFT  (7U)
+/*! APU_NFC_ISO_EN_AON - APU NFC ISO Enable AON */
+#define APU_NFC_STATUS_APU_NFC_ISO_EN_AON(x)     (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_APU_NFC_ISO_EN_AON_SHIFT)) & APU_NFC_STATUS_APU_NFC_ISO_EN_AON_MASK)
+
+#define APU_NFC_STATUS_APU_NFC_SRAM_PD_AON_MASK  (0x100U)
+#define APU_NFC_STATUS_APU_NFC_SRAM_PD_AON_SHIFT (8U)
+/*! APU_NFC_SRAM_PD_AON - APU NFC SRAM PD AON */
+#define APU_NFC_STATUS_APU_NFC_SRAM_PD_AON(x)    (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_APU_NFC_SRAM_PD_AON_SHIFT)) & APU_NFC_STATUS_APU_NFC_SRAM_PD_AON_MASK)
+
+#define APU_NFC_STATUS_NFC_VOL_REACHED_MASK      (0x200U)
+#define APU_NFC_STATUS_NFC_VOL_REACHED_SHIFT     (9U)
+/*! NFC_VOL_REACHED - NFC Vol Reached */
+#define APU_NFC_STATUS_NFC_VOL_REACHED(x)        (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_NFC_VOL_REACHED_SHIFT)) & APU_NFC_STATUS_NFC_VOL_REACHED_MASK)
+
+#define APU_NFC_STATUS_SOC_VOL_REACHED_MASK      (0x400U)
+#define APU_NFC_STATUS_SOC_VOL_REACHED_SHIFT     (10U)
+/*! SOC_VOL_REACHED - SoC Vol Reached */
+#define APU_NFC_STATUS_SOC_VOL_REACHED(x)        (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_SOC_VOL_REACHED_SHIFT)) & APU_NFC_STATUS_SOC_VOL_REACHED_MASK)
+
+#define APU_NFC_STATUS_NFC_PWR_RDY_MASK          (0x800U)
+#define APU_NFC_STATUS_NFC_PWR_RDY_SHIFT         (11U)
+/*! NFC_PWR_RDY - NFC Power ready */
+#define APU_NFC_STATUS_NFC_PWR_RDY(x)            (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_NFC_PWR_RDY_SHIFT)) & APU_NFC_STATUS_NFC_PWR_RDY_MASK)
+
+#define APU_NFC_STATUS_APU_NFC_ST_MASK           (0x7000U)
+#define APU_NFC_STATUS_APU_NFC_ST_SHIFT          (12U)
+/*! APU_NFC_ST - APU NFC St */
+#define APU_NFC_STATUS_APU_NFC_ST(x)             (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_APU_NFC_ST_SHIFT)) & APU_NFC_STATUS_APU_NFC_ST_MASK)
+
+#define APU_NFC_STATUS_HOST_WKUP_IN_MASK         (0xFFFF0000U)
+#define APU_NFC_STATUS_HOST_WKUP_IN_SHIFT        (16U)
+/*! HOST_WKUP_IN - Host Wakeup Interrupt */
+#define APU_NFC_STATUS_HOST_WKUP_IN(x)           (((uint32_t)(((uint32_t)(x)) << APU_NFC_STATUS_HOST_WKUP_IN_SHIFT)) & APU_NFC_STATUS_HOST_WKUP_IN_MASK)
+/*! @} */
+
+/*! @name NFC_CKEN_CTRL - NFC Clock Enable Control */
+/*! @{ */
+
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_VAL_MASK (0x1U)
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_VAL_SHIFT (0U)
+/*! NFC_CLK_EN_PWR_VAL - control value for nfc_clk_en when power ready */
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_VAL(x)  (((uint32_t)(((uint32_t)(x)) << APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_VAL_SHIFT)) & APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_VAL_MASK)
+
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_SEL_MASK (0x2U)
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_SEL_SHIFT (1U)
+/*! NFC_CLK_EN_PWR_SEL - selection for nfc_cm3_clk_en when power ready */
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_SEL(x)  (((uint32_t)(((uint32_t)(x)) << APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_SEL_SHIFT)) & APU_NFC_CKEN_CTRL_NFC_CLK_EN_PWR_SEL_MASK)
+
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_VAL_MASK (0x4U)
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_VAL_SHIFT (2U)
+/*! NFC_CLK_EN_XOSC_VAL - Control value for nfc_cm3_clk_en when XOSC ready */
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_VAL_SHIFT)) & APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_VAL_MASK)
+
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_SEL_MASK (0x8U)
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_SEL_SHIFT (3U)
+/*! NFC_CLK_EN_XOSC_SEL - selection for nfc_cm3_clk_en when XOSC ready */
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_SEL_SHIFT)) & APU_NFC_CKEN_CTRL_NFC_CLK_EN_XOSC_SEL_MASK)
+
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_VAL_MASK (0x10U)
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_VAL_SHIFT (4U)
+/*! NFC_CLK_EN_PLL_VAL - NFC Clock Enable PLL Value */
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_VAL(x)  (((uint32_t)(((uint32_t)(x)) << APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_VAL_SHIFT)) & APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_VAL_MASK)
+
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_SEL_MASK (0x20U)
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_SEL_SHIFT (5U)
+/*! NFC_CLK_EN_PLL_SEL - selection for nfc_cm3_clk_en when PLL ready */
+#define APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_SEL(x)  (((uint32_t)(((uint32_t)(x)) << APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_SEL_SHIFT)) & APU_NFC_CKEN_CTRL_NFC_CLK_EN_PLL_SEL_MASK)
+/*! @} */
+
+/*! @name NFC_RESRC_CTRL - NFC RESRC Control */
+/*! @{ */
+
+#define APU_NFC_RESRC_CTRL_NFC_PWR_REQ_MASK      (0x1U)
+#define APU_NFC_RESRC_CTRL_NFC_PWR_REQ_SHIFT     (0U)
+/*! NFC_PWR_REQ - override hw power request */
+#define APU_NFC_RESRC_CTRL_NFC_PWR_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_PWR_REQ_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_PWR_REQ_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_PWR_REQ_VAL_MASK  (0x2U)
+#define APU_NFC_RESRC_CTRL_NFC_PWR_REQ_VAL_SHIFT (1U)
+/*! NFC_PWR_REQ_VAL - override value when apu_nfc_resrc_ctrl[0] is set */
+#define APU_NFC_RESRC_CTRL_NFC_PWR_REQ_VAL(x)    (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_PWR_REQ_VAL_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_PWR_REQ_VAL_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_MASK     (0x4U)
+#define APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_SHIFT    (2U)
+/*! NFC_XOSC_REQ - override hw xosc request */
+#define APU_NFC_RESRC_CTRL_NFC_XOSC_REQ(x)       (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_VAL_MASK (0x8U)
+#define APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_VAL_SHIFT (3U)
+/*! NFC_XOSC_REQ_VAL - override value when apu_nfc_resrc_ctrl[2] is set */
+#define APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_VAL(x)   (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_VAL_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_XOSC_REQ_VAL_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_XP_REQ_MASK       (0x10U)
+#define APU_NFC_RESRC_CTRL_NFC_XP_REQ_SHIFT      (4U)
+/*! NFC_XP_REQ - override hw xosc + pwr request */
+#define APU_NFC_RESRC_CTRL_NFC_XP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_XP_REQ_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_XP_REQ_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_XP_REQ_VAL_MASK   (0x20U)
+#define APU_NFC_RESRC_CTRL_NFC_XP_REQ_VAL_SHIFT  (5U)
+/*! NFC_XP_REQ_VAL - override value when apu_nfc_resrc_ctrl[4] is set */
+#define APU_NFC_RESRC_CTRL_NFC_XP_REQ_VAL(x)     (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_XP_REQ_VAL_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_XP_REQ_VAL_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_SB_REQ_MASK       (0x40U)
+#define APU_NFC_RESRC_CTRL_NFC_SB_REQ_SHIFT      (6U)
+/*! NFC_SB_REQ - override hw xosc + pwr + pll sb request */
+#define APU_NFC_RESRC_CTRL_NFC_SB_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_SB_REQ_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_SB_REQ_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_SB_REQ_VAL_MASK   (0x80U)
+#define APU_NFC_RESRC_CTRL_NFC_SB_REQ_VAL_SHIFT  (7U)
+/*! NFC_SB_REQ_VAL - override value when apu_nfc_resrc_ctrl[6] is set */
+#define APU_NFC_RESRC_CTRL_NFC_SB_REQ_VAL(x)     (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_SB_REQ_VAL_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_SB_REQ_VAL_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_MASK   (0x100U)
+#define APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_SHIFT  (8U)
+/*! NFC_IPWAKE_REQ - override hw xosc + pwr + pll ipwake request */
+#define APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ(x)     (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_VAL_MASK (0x200U)
+#define APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_VAL_SHIFT (9U)
+/*! NFC_IPWAKE_REQ_VAL - override value when apu_nfc_resrc_ctrl[8] is set */
+#define APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_VAL_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_IPWAKE_REQ_VAL_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_MASK  (0x400U)
+#define APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_SHIFT (10U)
+/*! NFC_ALLWAKE_REQ - firmware override hw xosc + pwr + pll allwake request */
+#define APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ(x)    (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_MASK)
+
+#define APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_VAL_MASK (0x800U)
+#define APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_VAL_SHIFT (11U)
+/*! NFC_ALLWAKE_REQ_VAL - firmware override value when apu_nfc_resrc_ctrl[10] is set */
+#define APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_VAL_SHIFT)) & APU_NFC_RESRC_CTRL_NFC_ALLWAKE_REQ_VAL_MASK)
+/*! @} */
+
+/*! @name NFC_DVFS_CTRL - NFC DVFS Control */
+/*! @{ */
+
+#define APU_NFC_DVFS_CTRL_NFC_VOL_VAL_MASK       (0x7FU)
+#define APU_NFC_DVFS_CTRL_NFC_VOL_VAL_SHIFT      (0U)
+/*! NFC_VOL_VAL - NFC Vol Value */
+#define APU_NFC_DVFS_CTRL_NFC_VOL_VAL(x)         (((uint32_t)(((uint32_t)(x)) << APU_NFC_DVFS_CTRL_NFC_VOL_VAL_SHIFT)) & APU_NFC_DVFS_CTRL_NFC_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name FP4_CTRL - FP4(15.4) Control */
+/*! @{ */
+
+#define APU_FP4_CTRL_FP4_SLP_RDY_MASK            (0x1U)
+#define APU_FP4_CTRL_FP4_SLP_RDY_SHIFT           (0U)
+/*! FP4_SLP_RDY - FP4 Sleep Ready */
+#define APU_FP4_CTRL_FP4_SLP_RDY(x)              (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FP4_SLP_RDY_SHIFT)) & APU_FP4_CTRL_FP4_SLP_RDY_MASK)
+
+#define APU_FP4_CTRL_FP4_SLP_RDYMASK_MASK        (0x2U)
+#define APU_FP4_CTRL_FP4_SLP_RDYMASK_SHIFT       (1U)
+/*! FP4_SLP_RDYMASK - FP4 Sleep Ready Mask */
+#define APU_FP4_CTRL_FP4_SLP_RDYMASK(x)          (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FP4_SLP_RDYMASK_SHIFT)) & APU_FP4_CTRL_FP4_SLP_RDYMASK_MASK)
+
+#define APU_FP4_CTRL_FP4_SLP_RDY_FW_MASK         (0x4U)
+#define APU_FP4_CTRL_FP4_SLP_RDY_FW_SHIFT        (2U)
+/*! FP4_SLP_RDY_FW - Bluetooth Sleep Ready FW */
+#define APU_FP4_CTRL_FP4_SLP_RDY_FW(x)           (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FP4_SLP_RDY_FW_SHIFT)) & APU_FP4_CTRL_FP4_SLP_RDY_FW_MASK)
+
+#define APU_FP4_CTRL_USE_FP4_INTR_SLP_MASK       (0x80U)
+#define APU_FP4_CTRL_USE_FP4_INTR_SLP_SHIFT      (7U)
+/*! USE_FP4_INTR_SLP - Use 15.4 interrupt Sleep */
+#define APU_FP4_CTRL_USE_FP4_INTR_SLP(x)         (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_USE_FP4_INTR_SLP_SHIFT)) & APU_FP4_CTRL_USE_FP4_INTR_SLP_MASK)
+
+#define APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL1_MASK (0x4000000U)
+#define APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL1_SHIFT (26U)
+/*! FP4_CLK_SYNC_MODE_SEL1 - FP4 Clock Sync Mode Select 1 */
+#define APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL1_SHIFT)) & APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL1_MASK)
+
+#define APU_FP4_CTRL_USE_GLITCH_FREE_FP4_CLK_REQ_MASK (0x8000000U)
+#define APU_FP4_CTRL_USE_GLITCH_FREE_FP4_CLK_REQ_SHIFT (27U)
+/*! USE_GLITCH_FREE_FP4_CLK_REQ - Use Glitch-Free FP4 Clock Request */
+#define APU_FP4_CTRL_USE_GLITCH_FREE_FP4_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_USE_GLITCH_FREE_FP4_CLK_REQ_SHIFT)) & APU_FP4_CTRL_USE_GLITCH_FREE_FP4_CLK_REQ_MASK)
+
+#define APU_FP4_CTRL_FRF_CLK_SYNC_MODE_SEL_MASK  (0x10000000U)
+#define APU_FP4_CTRL_FRF_CLK_SYNC_MODE_SEL_SHIFT (28U)
+/*! FRF_CLK_SYNC_MODE_SEL - FRF Clock Sync Mode Select */
+#define APU_FP4_CTRL_FRF_CLK_SYNC_MODE_SEL(x)    (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FRF_CLK_SYNC_MODE_SEL_SHIFT)) & APU_FP4_CTRL_FRF_CLK_SYNC_MODE_SEL_MASK)
+
+#define APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL0_MASK (0x20000000U)
+#define APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL0_SHIFT (29U)
+/*! FP4_CLK_SYNC_MODE_SEL0 - FP4 Clock Sync Mode Select 0 */
+#define APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL0_SHIFT)) & APU_FP4_CTRL_FP4_CLK_SYNC_MODE_SEL0_MASK)
+
+#define APU_FP4_CTRL_FRF_PLL_SYNC_MODE_SEL_MASK  (0x40000000U)
+#define APU_FP4_CTRL_FRF_PLL_SYNC_MODE_SEL_SHIFT (30U)
+/*! FRF_PLL_SYNC_MODE_SEL - FRF PLL Sync Mode Select */
+#define APU_FP4_CTRL_FRF_PLL_SYNC_MODE_SEL(x)    (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FRF_PLL_SYNC_MODE_SEL_SHIFT)) & APU_FP4_CTRL_FRF_PLL_SYNC_MODE_SEL_MASK)
+
+#define APU_FP4_CTRL_FP4_HOST_SLP_RDY_MASK       (0x80000000U)
+#define APU_FP4_CTRL_FP4_HOST_SLP_RDY_SHIFT      (31U)
+/*! FP4_HOST_SLP_RDY - FP4 Host Sleep Ready */
+#define APU_FP4_CTRL_FP4_HOST_SLP_RDY(x)         (((uint32_t)(((uint32_t)(x)) << APU_FP4_CTRL_FP4_HOST_SLP_RDY_SHIFT)) & APU_FP4_CTRL_FP4_HOST_SLP_RDY_MASK)
+/*! @} */
+
+/*! @name FP4_WKUP_MASK - FP4 Wakeup Mask */
+/*! @{ */
+
+#define APU_FP4_WKUP_MASK_FP4_CLK_REQ_MASK_MASK  (0x1U)
+#define APU_FP4_WKUP_MASK_FP4_CLK_REQ_MASK_SHIFT (0U)
+/*! FP4_CLK_REQ_MASK - FP4 Clock Request Mask */
+#define APU_FP4_WKUP_MASK_FP4_CLK_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_FP4_WKUP_MASK_FP4_CLK_REQ_MASK_SHIFT)) & APU_FP4_WKUP_MASK_FP4_CLK_REQ_MASK_MASK)
+
+#define APU_FP4_WKUP_MASK_FP4_INTERRUPT_MASK_MASK (0x2U)
+#define APU_FP4_WKUP_MASK_FP4_INTERRUPT_MASK_SHIFT (1U)
+/*! FP4_INTERRUPT_MASK - FP4 Interrupt Mask */
+#define APU_FP4_WKUP_MASK_FP4_INTERRUPT_MASK(x)  (((uint32_t)(((uint32_t)(x)) << APU_FP4_WKUP_MASK_FP4_INTERRUPT_MASK_SHIFT)) & APU_FP4_WKUP_MASK_FP4_INTERRUPT_MASK_MASK)
+
+#define APU_FP4_WKUP_MASK_FRF_PLL_REQ_MASK_MASK  (0x4U)
+#define APU_FP4_WKUP_MASK_FRF_PLL_REQ_MASK_SHIFT (2U)
+/*! FRF_PLL_REQ_MASK - FRF PLL Request Mask */
+#define APU_FP4_WKUP_MASK_FRF_PLL_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_FP4_WKUP_MASK_FRF_PLL_REQ_MASK_SHIFT)) & APU_FP4_WKUP_MASK_FRF_PLL_REQ_MASK_MASK)
+
+#define APU_FP4_WKUP_MASK_FP4_PLL_REQ_MASK_MASK  (0x8U)
+#define APU_FP4_WKUP_MASK_FP4_PLL_REQ_MASK_SHIFT (3U)
+/*! FP4_PLL_REQ_MASK - 15.4 PLL Request Mask */
+#define APU_FP4_WKUP_MASK_FP4_PLL_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_FP4_WKUP_MASK_FP4_PLL_REQ_MASK_SHIFT)) & APU_FP4_WKUP_MASK_FP4_PLL_REQ_MASK_MASK)
+
+#define APU_FP4_WKUP_MASK_FP4_HOST_MAP_MASK      (0xFFFF0000U)
+#define APU_FP4_WKUP_MASK_FP4_HOST_MAP_SHIFT     (16U)
+/*! FP4_HOST_MAP - 15.4 Host Map */
+#define APU_FP4_WKUP_MASK_FP4_HOST_MAP(x)        (((uint32_t)(((uint32_t)(x)) << APU_FP4_WKUP_MASK_FP4_HOST_MAP_SHIFT)) & APU_FP4_WKUP_MASK_FP4_HOST_MAP_MASK)
+/*! @} */
+
+/*! @name FP4_STATUS - FP4 Status */
+/*! @{ */
+
+#define APU_FP4_STATUS_APU_FP4_CLK_EN_MASK       (0x1U)
+#define APU_FP4_STATUS_APU_FP4_CLK_EN_SHIFT      (0U)
+/*! APU_FP4_CLK_EN - APU FP4 Clock Enable */
+#define APU_FP4_STATUS_APU_FP4_CLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_APU_FP4_CLK_EN_SHIFT)) & APU_FP4_STATUS_APU_FP4_CLK_EN_MASK)
+
+#define APU_FP4_STATUS_APU_FRF_CLK_EN_MASK       (0x2U)
+#define APU_FP4_STATUS_APU_FRF_CLK_EN_SHIFT      (1U)
+/*! APU_FRF_CLK_EN - APU FRF Clock Enable */
+#define APU_FP4_STATUS_APU_FRF_CLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_APU_FRF_CLK_EN_SHIFT)) & APU_FP4_STATUS_APU_FRF_CLK_EN_MASK)
+
+#define APU_FP4_STATUS_FP4_ACTIVE_SLPCK_MASK     (0x4U)
+#define APU_FP4_STATUS_FP4_ACTIVE_SLPCK_SHIFT    (2U)
+/*! FP4_ACTIVE_SLPCK - FP4 Active Sleep Clock */
+#define APU_FP4_STATUS_FP4_ACTIVE_SLPCK(x)       (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_FP4_ACTIVE_SLPCK_SHIFT)) & APU_FP4_STATUS_FP4_ACTIVE_SLPCK_MASK)
+
+#define APU_FP4_STATUS_BT_HOST_WKUP_MASK         (0x8U)
+#define APU_FP4_STATUS_BT_HOST_WKUP_SHIFT        (3U)
+/*! BT_HOST_WKUP - Bluetooth Host Wakeup */
+#define APU_FP4_STATUS_BT_HOST_WKUP(x)           (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_BT_HOST_WKUP_SHIFT)) & APU_FP4_STATUS_BT_HOST_WKUP_MASK)
+
+#define APU_FP4_STATUS_FP4_INTERRUPT_MASK        (0x10U)
+#define APU_FP4_STATUS_FP4_INTERRUPT_SHIFT       (4U)
+/*! FP4_INTERRUPT - FP4 Interrupt */
+#define APU_FP4_STATUS_FP4_INTERRUPT(x)          (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_FP4_INTERRUPT_SHIFT)) & APU_FP4_STATUS_FP4_INTERRUPT_MASK)
+
+#define APU_FP4_STATUS_FP4_PLL_REQ_MASK          (0x20U)
+#define APU_FP4_STATUS_FP4_PLL_REQ_SHIFT         (5U)
+/*! FP4_PLL_REQ - FP4 PLL Request */
+#define APU_FP4_STATUS_FP4_PLL_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_FP4_PLL_REQ_SHIFT)) & APU_FP4_STATUS_FP4_PLL_REQ_MASK)
+
+#define APU_FP4_STATUS_FP4_CLK_REQ_MASK          (0x40U)
+#define APU_FP4_STATUS_FP4_CLK_REQ_SHIFT         (6U)
+/*! FP4_CLK_REQ - FP4 Clock Request */
+#define APU_FP4_STATUS_FP4_CLK_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_FP4_CLK_REQ_SHIFT)) & APU_FP4_STATUS_FP4_CLK_REQ_MASK)
+
+#define APU_FP4_STATUS_FRF_PLL_REQ_MASK          (0x80U)
+#define APU_FP4_STATUS_FRF_PLL_REQ_SHIFT         (7U)
+/*! FRF_PLL_REQ - FRF PLL Request */
+#define APU_FP4_STATUS_FRF_PLL_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_FRF_PLL_REQ_SHIFT)) & APU_FP4_STATUS_FRF_PLL_REQ_MASK)
+
+#define APU_FP4_STATUS_HOST_WKUP_IN_MASK         (0xFFFF0000U)
+#define APU_FP4_STATUS_HOST_WKUP_IN_SHIFT        (16U)
+/*! HOST_WKUP_IN - Host Wakeup In */
+#define APU_FP4_STATUS_HOST_WKUP_IN(x)           (((uint32_t)(((uint32_t)(x)) << APU_FP4_STATUS_HOST_WKUP_IN_SHIFT)) & APU_FP4_STATUS_HOST_WKUP_IN_MASK)
+/*! @} */
+
+/*! @name FP4_CKEN_CTRL - FP4 Clock Enable Control */
+/*! @{ */
+
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_PWR_MASK (0x1U)
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_PWR_SHIFT (0U)
+/*! FP4_CLK_EN_VAL_PWR - control value for fp4_clk_en when power ready */
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_PWR(x)  (((uint32_t)(((uint32_t)(x)) << APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_PWR_SHIFT)) & APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_PWR_MASK)
+
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_PWR_MASK (0x2U)
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_PWR_SHIFT (1U)
+/*! FP4_CLK_EN_SEL_PWR - selection for fp4_clk_en when power ready */
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_PWR(x)  (((uint32_t)(((uint32_t)(x)) << APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_PWR_SHIFT)) & APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_PWR_MASK)
+
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_XOSC_MASK (0x4U)
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_XOSC_SHIFT (2U)
+/*! FP4_CLK_EN_VAL_XOSC - control value for fp4_clk_en when XOSC ready */
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_XOSC(x) (((uint32_t)(((uint32_t)(x)) << APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_XOSC_SHIFT)) & APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_XOSC_MASK)
+
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_XOSC_MASK (0x8U)
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_XOSC_SHIFT (3U)
+/*! FP4_CLK_EN_SEL_XOSC - selection for fp4_clk_en when XOSC ready */
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_XOSC(x) (((uint32_t)(((uint32_t)(x)) << APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_XOSC_SHIFT)) & APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_XOSC_MASK)
+
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_MASK    (0x10U)
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_SHIFT   (4U)
+/*! FP4_CLK_EN_VAL - control value for fp4_clk_en when PLL ready */
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL(x)      (((uint32_t)(((uint32_t)(x)) << APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_SHIFT)) & APU_FP4_CKEN_CTRL_FP4_CLK_EN_VAL_MASK)
+
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_MASK    (0x20U)
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_SHIFT   (5U)
+/*! FP4_CLK_EN_SEL - selection for fp4_clk_en when PLL ready */
+#define APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL(x)      (((uint32_t)(((uint32_t)(x)) << APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_SHIFT)) & APU_FP4_CKEN_CTRL_FP4_CLK_EN_SEL_MASK)
+/*! @} */
+
+/*! @name FP4_RESRC_CTRL - FP4 RESRC Control */
+/*! @{ */
+
+#define APU_FP4_RESRC_CTRL_FW_PWR_REQ_MASK       (0x1U)
+#define APU_FP4_RESRC_CTRL_FW_PWR_REQ_SHIFT      (0U)
+/*! FW_PWR_REQ - override hw power request */
+#define APU_FP4_RESRC_CTRL_FW_PWR_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_PWR_REQ_SHIFT)) & APU_FP4_RESRC_CTRL_FW_PWR_REQ_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_PWR_REQ_VAL_MASK   (0x2U)
+#define APU_FP4_RESRC_CTRL_FW_PWR_REQ_VAL_SHIFT  (1U)
+/*! FW_PWR_REQ_VAL - override value when apu_fp4_resrc_ctrl[0] is set */
+#define APU_FP4_RESRC_CTRL_FW_PWR_REQ_VAL(x)     (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_PWR_REQ_VAL_SHIFT)) & APU_FP4_RESRC_CTRL_FW_PWR_REQ_VAL_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_XOSC_REQ_MASK      (0x4U)
+#define APU_FP4_RESRC_CTRL_FW_XOSC_REQ_SHIFT     (2U)
+/*! FW_XOSC_REQ - override hw xosc request */
+#define APU_FP4_RESRC_CTRL_FW_XOSC_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_XOSC_REQ_SHIFT)) & APU_FP4_RESRC_CTRL_FW_XOSC_REQ_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_XOSC_REQ_VAL_MASK  (0x8U)
+#define APU_FP4_RESRC_CTRL_FW_XOSC_REQ_VAL_SHIFT (3U)
+/*! FW_XOSC_REQ_VAL - override value when apu_fp4_resrc_ctrl[2] is set */
+#define APU_FP4_RESRC_CTRL_FW_XOSC_REQ_VAL(x)    (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_XOSC_REQ_VAL_SHIFT)) & APU_FP4_RESRC_CTRL_FW_XOSC_REQ_VAL_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_XP_REQ_MASK        (0x10U)
+#define APU_FP4_RESRC_CTRL_FW_XP_REQ_SHIFT       (4U)
+/*! FW_XP_REQ - override hw xosc + pwr request */
+#define APU_FP4_RESRC_CTRL_FW_XP_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_XP_REQ_SHIFT)) & APU_FP4_RESRC_CTRL_FW_XP_REQ_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_XP_REQ_VAL_MASK    (0x20U)
+#define APU_FP4_RESRC_CTRL_FW_XP_REQ_VAL_SHIFT   (5U)
+/*! FW_XP_REQ_VAL - override value when apu_fp4_resrc_ctrl[4] is set */
+#define APU_FP4_RESRC_CTRL_FW_XP_REQ_VAL(x)      (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_XP_REQ_VAL_SHIFT)) & APU_FP4_RESRC_CTRL_FW_XP_REQ_VAL_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_SB_REQ_MASK        (0x40U)
+#define APU_FP4_RESRC_CTRL_FW_SB_REQ_SHIFT       (6U)
+/*! FW_SB_REQ - override hw xosc + pwr + pll sb request */
+#define APU_FP4_RESRC_CTRL_FW_SB_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_SB_REQ_SHIFT)) & APU_FP4_RESRC_CTRL_FW_SB_REQ_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_SB_REQ_VAL_MASK    (0x80U)
+#define APU_FP4_RESRC_CTRL_FW_SB_REQ_VAL_SHIFT   (7U)
+/*! FW_SB_REQ_VAL - override value when apu_fp4_resrc_ctrl[6] is set */
+#define APU_FP4_RESRC_CTRL_FW_SB_REQ_VAL(x)      (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_SB_REQ_VAL_SHIFT)) & APU_FP4_RESRC_CTRL_FW_SB_REQ_VAL_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_MASK    (0x100U)
+#define APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_SHIFT   (8U)
+/*! FW_IPWAKE_REQ - override hw xosc + pwr + pll ipwake request */
+#define APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ(x)      (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_SHIFT)) & APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_VAL_MASK (0x200U)
+#define APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_VAL_SHIFT (9U)
+/*! FW_IPWAKE_REQ_VAL - override value when apu_fp4_resrc_ctrl[8] is set */
+#define APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_VAL(x)  (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_VAL_SHIFT)) & APU_FP4_RESRC_CTRL_FW_IPWAKE_REQ_VAL_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_MASK   (0x400U)
+#define APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_SHIFT  (10U)
+/*! FW_ALLWAKE_REQ - firmware override hw xosc + pwr + pll allwake request */
+#define APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ(x)     (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_SHIFT)) & APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_MASK)
+
+#define APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_MASK (0x800U)
+#define APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_SHIFT (11U)
+/*! FW_ALLWAKE_REQ_VAL - firmware override value when apu_fp4_resrc_ctrl[10] is set */
+#define APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_SHIFT)) & APU_FP4_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_MASK)
+/*! @} */
+
+/*! @name FP4_DVFS_CTRL - FP4 DVFS Control */
+/*! @{ */
+
+#define APU_FP4_DVFS_CTRL_FP4_VOL_VAL_MASK       (0x7FU)
+#define APU_FP4_DVFS_CTRL_FP4_VOL_VAL_SHIFT      (0U)
+/*! FP4_VOL_VAL - FP4 Vol Value */
+#define APU_FP4_DVFS_CTRL_FP4_VOL_VAL(x)         (((uint32_t)(((uint32_t)(x)) << APU_FP4_DVFS_CTRL_FP4_VOL_VAL_SHIFT)) & APU_FP4_DVFS_CTRL_FP4_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name CPU2_FP4_HOST_WKUP_MASK - CPU2 15.4 Host Wakeup Mask */
+/*! @{ */
+
+#define APU_CPU2_FP4_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK (0xFFFFU)
+#define APU_CPU2_FP4_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT (0U)
+/*! HOST_WKUP_MASK - Host Wakeup Mask */
+#define APU_CPU2_FP4_HOST_WKUP_MASK_HOST_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_FP4_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT)) & APU_CPU2_FP4_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK)
+/*! @} */
+
+/*! @name CPU2_FP4_HOST_WKUP_POL - CPU2 15.4 Host Wakeup Polarity */
+/*! @{ */
+
+#define APU_CPU2_FP4_HOST_WKUP_POL_HOST_WKUP_POL_MASK (0xFFFFU)
+#define APU_CPU2_FP4_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT (0U)
+/*! HOST_WKUP_POL - Host Wakeup Polarity */
+#define APU_CPU2_FP4_HOST_WKUP_POL_HOST_WKUP_POL(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_FP4_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT)) & APU_CPU2_FP4_HOST_WKUP_POL_HOST_WKUP_POL_MASK)
+/*! @} */
+
+/*! @name CPU2_FP4_HOST_WKUP_CTRL - CPU2 15.4 Host Wakeup Control */
+/*! @{ */
+
+#define APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK (0xFFFFU)
+#define APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT (0U)
+/*! HOST_WKUP_CTRL - Host Wakeup Control */
+#define APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_WKUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT)) & APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK)
+
+#define APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK (0xFFFF0000U)
+#define APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT (16U)
+/*! HOST_INTR_MASK - Host Interrupt Mask */
+#define APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_INTR_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT)) & APU_CPU2_FP4_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK)
+/*! @} */
+
+/*! @name HW_IP_ACTIVE_INDEX_CTRL - HW IP active index Control */
+/*! @{ */
+
+#define APU_HW_IP_ACTIVE_INDEX_CTRL_MASTERX_ACTIVE_INDEX_MASK (0xFFFFFFFFU)
+#define APU_HW_IP_ACTIVE_INDEX_CTRL_MASTERX_ACTIVE_INDEX_SHIFT (0U)
+/*! MASTERX_ACTIVE_INDEX - master0-7 Active Index[3:0] */
+#define APU_HW_IP_ACTIVE_INDEX_CTRL_MASTERX_ACTIVE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_HW_IP_ACTIVE_INDEX_CTRL_MASTERX_ACTIVE_INDEX_SHIFT)) & APU_HW_IP_ACTIVE_INDEX_CTRL_MASTERX_ACTIVE_INDEX_MASK)
+/*! @} */
+
+/*! @name HW_IP_INACTIVE_INDEX_CTRL - HW IP inactive Control */
+/*! @{ */
+
+#define APU_HW_IP_INACTIVE_INDEX_CTRL_MASTERX_INACTIVE_INDEX_MASK (0xFFFFFFFFU)
+#define APU_HW_IP_INACTIVE_INDEX_CTRL_MASTERX_INACTIVE_INDEX_SHIFT (0U)
+/*! MASTERX_INACTIVE_INDEX - master0-7 inactive Index[3:0] */
+#define APU_HW_IP_INACTIVE_INDEX_CTRL_MASTERX_INACTIVE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_HW_IP_INACTIVE_INDEX_CTRL_MASTERX_INACTIVE_INDEX_SHIFT)) & APU_HW_IP_INACTIVE_INDEX_CTRL_MASTERX_INACTIVE_INDEX_MASK)
+/*! @} */
+
+/*! @name HW_IP_DYNAMIC_CLK_SWITCH_CTRL - HW IP dynamic clock switching contrl */
+/*! @{ */
+
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_EN_MASK (0xFFU)
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_EN_SHIFT (0U)
+/*! MASTERX_APU_IDLE_BYPASS_EN - 1-FW bypasses hw_ip_idle; 0 - use hw_ip_idle */
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_EN_SHIFT)) & APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_EN_MASK)
+
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_VAL_MASK (0xFF00U)
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_VAL_SHIFT (8U)
+/*! MASTERX_APU_IDLE_BYPASS_VAL - idle bypass val */
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_VAL_SHIFT)) & APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_APU_IDLE_BYPASS_VAL_MASK)
+
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_ACTIVE_INDEX_BYPASS_EN_MASK (0xFF0000U)
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_ACTIVE_INDEX_BYPASS_EN_SHIFT (16U)
+/*! MASTERX_ACTIVE_INDEX_BYPASS_EN - 1- use masterx_active-index from register hw_ip_active_index_ctrl; 0-use active index from HW latched version */
+#define APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_ACTIVE_INDEX_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_ACTIVE_INDEX_BYPASS_EN_SHIFT)) & APU_HW_IP_DYNAMIC_CLK_SWITCH_CTRL_MASTERX_ACTIVE_INDEX_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name IHB_CTRL - IHB Control */
+/*! @{ */
+
+#define APU_IHB_CTRL_IHB_VOL_REQ_AS_P_REQ_MASK   (0x1U)
+#define APU_IHB_CTRL_IHB_VOL_REQ_AS_P_REQ_SHIFT  (0U)
+/*! IHB_VOL_REQ_AS_P_REQ - IHB Vol Request as P Request */
+#define APU_IHB_CTRL_IHB_VOL_REQ_AS_P_REQ(x)     (((uint32_t)(((uint32_t)(x)) << APU_IHB_CTRL_IHB_VOL_REQ_AS_P_REQ_SHIFT)) & APU_IHB_CTRL_IHB_VOL_REQ_AS_P_REQ_MASK)
+
+#define APU_IHB_CTRL_IHB_VOL_REQ_AS_XP_REQ_MASK  (0x2U)
+#define APU_IHB_CTRL_IHB_VOL_REQ_AS_XP_REQ_SHIFT (1U)
+/*! IHB_VOL_REQ_AS_XP_REQ - IHB Vol Request as XP Request */
+#define APU_IHB_CTRL_IHB_VOL_REQ_AS_XP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << APU_IHB_CTRL_IHB_VOL_REQ_AS_XP_REQ_SHIFT)) & APU_IHB_CTRL_IHB_VOL_REQ_AS_XP_REQ_MASK)
+
+#define APU_IHB_CTRL_IHB_CLK_REQ_AS_XP_REQ_MASK  (0x4U)
+#define APU_IHB_CTRL_IHB_CLK_REQ_AS_XP_REQ_SHIFT (2U)
+/*! IHB_CLK_REQ_AS_XP_REQ - IHB Clock Request as XP Request */
+#define APU_IHB_CTRL_IHB_CLK_REQ_AS_XP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << APU_IHB_CTRL_IHB_CLK_REQ_AS_XP_REQ_SHIFT)) & APU_IHB_CTRL_IHB_CLK_REQ_AS_XP_REQ_MASK)
+
+#define APU_IHB_CTRL_IHB_CLK_REQ_AS_XPP_REQ_MASK (0x8U)
+#define APU_IHB_CTRL_IHB_CLK_REQ_AS_XPP_REQ_SHIFT (3U)
+/*! IHB_CLK_REQ_AS_XPP_REQ - IHB Clock Request as XPP Request */
+#define APU_IHB_CTRL_IHB_CLK_REQ_AS_XPP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << APU_IHB_CTRL_IHB_CLK_REQ_AS_XPP_REQ_SHIFT)) & APU_IHB_CTRL_IHB_CLK_REQ_AS_XPP_REQ_MASK)
+
+#define APU_IHB_CTRL_IHB_VOL_VAL_MASK            (0x7F0000U)
+#define APU_IHB_CTRL_IHB_VOL_VAL_SHIFT           (16U)
+/*! IHB_VOL_VAL - Voltage value needed for Bluetooth function */
+#define APU_IHB_CTRL_IHB_VOL_VAL(x)              (((uint32_t)(((uint32_t)(x)) << APU_IHB_CTRL_IHB_VOL_VAL_SHIFT)) & APU_IHB_CTRL_IHB_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name IHB_WKUP_MASK - IHB Wakeup Mask */
+/*! @{ */
+
+#define APU_IHB_WKUP_MASK_IHB_HI_VOL_REQ_MASK_MASK (0x1U)
+#define APU_IHB_WKUP_MASK_IHB_HI_VOL_REQ_MASK_SHIFT (0U)
+/*! IHB_HI_VOL_REQ_MASK - IHB High Vol Request Mask */
+#define APU_IHB_WKUP_MASK_IHB_HI_VOL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_IHB_WKUP_MASK_IHB_HI_VOL_REQ_MASK_SHIFT)) & APU_IHB_WKUP_MASK_IHB_HI_VOL_REQ_MASK_MASK)
+
+#define APU_IHB_WKUP_MASK_IHB_LO_VOL_REQ_MASK_MASK (0x2U)
+#define APU_IHB_WKUP_MASK_IHB_LO_VOL_REQ_MASK_SHIFT (1U)
+/*! IHB_LO_VOL_REQ_MASK - IHB Low Vol Request Mask */
+#define APU_IHB_WKUP_MASK_IHB_LO_VOL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_IHB_WKUP_MASK_IHB_LO_VOL_REQ_MASK_SHIFT)) & APU_IHB_WKUP_MASK_IHB_LO_VOL_REQ_MASK_MASK)
+
+#define APU_IHB_WKUP_MASK_IHB_CLK_REQ_MASK_MASK  (0x4U)
+#define APU_IHB_WKUP_MASK_IHB_CLK_REQ_MASK_SHIFT (2U)
+/*! IHB_CLK_REQ_MASK - IHB Clock Request Mask */
+#define APU_IHB_WKUP_MASK_IHB_CLK_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_IHB_WKUP_MASK_IHB_CLK_REQ_MASK_SHIFT)) & APU_IHB_WKUP_MASK_IHB_CLK_REQ_MASK_MASK)
+
+#define APU_IHB_WKUP_MASK_IHB_WL_WKUP_REQ_MASK_MASK (0x8U)
+#define APU_IHB_WKUP_MASK_IHB_WL_WKUP_REQ_MASK_SHIFT (3U)
+/*! IHB_WL_WKUP_REQ_MASK - IHB WLAN Wakeup Request Mask */
+#define APU_IHB_WKUP_MASK_IHB_WL_WKUP_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_IHB_WKUP_MASK_IHB_WL_WKUP_REQ_MASK_SHIFT)) & APU_IHB_WKUP_MASK_IHB_WL_WKUP_REQ_MASK_MASK)
+
+#define APU_IHB_WKUP_MASK_CPU1_IHB_PMU_WKUP_MASK_MASK (0x10U)
+#define APU_IHB_WKUP_MASK_CPU1_IHB_PMU_WKUP_MASK_SHIFT (4U)
+/*! CPU1_IHB_PMU_WKUP_MASK - CPU1 IHB PMU Wakeup Mask */
+#define APU_IHB_WKUP_MASK_CPU1_IHB_PMU_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_IHB_WKUP_MASK_CPU1_IHB_PMU_WKUP_MASK_SHIFT)) & APU_IHB_WKUP_MASK_CPU1_IHB_PMU_WKUP_MASK_MASK)
+/*! @} */
+
+/*! @name CPU2_IHB_WKUP_MASK - CPU2 IHB Wakeup Mask */
+/*! @{ */
+
+#define APU_CPU2_IHB_WKUP_MASK_CPU2_IHB_PMU_WKUP_MASK_MASK (0x1U)
+#define APU_CPU2_IHB_WKUP_MASK_CPU2_IHB_PMU_WKUP_MASK_SHIFT (0U)
+/*! CPU2_IHB_PMU_WKUP_MASK - CPU2 IHB PMU Wakeup Mask */
+#define APU_CPU2_IHB_WKUP_MASK_CPU2_IHB_PMU_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_IHB_WKUP_MASK_CPU2_IHB_PMU_WKUP_MASK_SHIFT)) & APU_CPU2_IHB_WKUP_MASK_CPU2_IHB_PMU_WKUP_MASK_MASK)
+/*! @} */
+
+/*! @name IHB_STATUS - IHB Status */
+/*! @{ */
+
+#define APU_IHB_STATUS_IHB_STATUS_MASK           (0xFFFFFFFFU)
+#define APU_IHB_STATUS_IHB_STATUS_SHIFT          (0U)
+/*! IHB_STATUS - IHB Status */
+#define APU_IHB_STATUS_IHB_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << APU_IHB_STATUS_IHB_STATUS_SHIFT)) & APU_IHB_STATUS_IHB_STATUS_MASK)
+/*! @} */
+
+/*! @name USB_CTRL - USB Control */
+/*! @{ */
+
+#define APU_USB_CTRL_USB_PWR_DWN_MASK_MASK       (0x1U)
+#define APU_USB_CTRL_USB_PWR_DWN_MASK_SHIFT      (0U)
+/*! USB_PWR_DWN_MASK - USB Power Down Mask */
+#define APU_USB_CTRL_USB_PWR_DWN_MASK(x)         (((uint32_t)(((uint32_t)(x)) << APU_USB_CTRL_USB_PWR_DWN_MASK_SHIFT)) & APU_USB_CTRL_USB_PWR_DWN_MASK_MASK)
+
+#define APU_USB_CTRL_USE_CLK_SEL_ACK_AS_USB_PWR_DWN_MASK (0x10U)
+#define APU_USB_CTRL_USE_CLK_SEL_ACK_AS_USB_PWR_DWN_SHIFT (4U)
+/*! USE_CLK_SEL_ACK_AS_USB_PWR_DWN - Use Clock Select Ack as USB Power Down */
+#define APU_USB_CTRL_USE_CLK_SEL_ACK_AS_USB_PWR_DWN(x) (((uint32_t)(((uint32_t)(x)) << APU_USB_CTRL_USE_CLK_SEL_ACK_AS_USB_PWR_DWN_SHIFT)) & APU_USB_CTRL_USE_CLK_SEL_ACK_AS_USB_PWR_DWN_MASK)
+
+#define APU_USB_CTRL_IDLE2ISO_DLY_EN_MASK        (0x20U)
+#define APU_USB_CTRL_IDLE2ISO_DLY_EN_SHIFT       (5U)
+/*! IDLE2ISO_DLY_EN - USB FSM state counter enable. When set to 1, use usb_pwr_ctrl_dly and usb_pwr_ctrl_dly2. When set to 0, no delay */
+#define APU_USB_CTRL_IDLE2ISO_DLY_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_USB_CTRL_IDLE2ISO_DLY_EN_SHIFT)) & APU_USB_CTRL_IDLE2ISO_DLY_EN_MASK)
+
+#define APU_USB_CTRL_USB_USE_NOM_PWR_BYP_MASK    (0x200U)
+#define APU_USB_CTRL_USB_USE_NOM_PWR_BYP_SHIFT   (9U)
+/*! USB_USE_NOM_PWR_BYP - USB Use Nominal Power Bypass */
+#define APU_USB_CTRL_USB_USE_NOM_PWR_BYP(x)      (((uint32_t)(((uint32_t)(x)) << APU_USB_CTRL_USB_USE_NOM_PWR_BYP_SHIFT)) & APU_USB_CTRL_USB_USE_NOM_PWR_BYP_MASK)
+
+#define APU_USB_CTRL_FW_FORCE_USB_PWRUP_MASK     (0x1000000U)
+#define APU_USB_CTRL_FW_FORCE_USB_PWRUP_SHIFT    (24U)
+/*! FW_FORCE_USB_PWRUP - FW Force USB Powerup */
+#define APU_USB_CTRL_FW_FORCE_USB_PWRUP(x)       (((uint32_t)(((uint32_t)(x)) << APU_USB_CTRL_FW_FORCE_USB_PWRUP_SHIFT)) & APU_USB_CTRL_FW_FORCE_USB_PWRUP_MASK)
+
+#define APU_USB_CTRL_USB_USE_UNSYNC_VOL_LVL_MASK (0x2000000U)
+#define APU_USB_CTRL_USB_USE_UNSYNC_VOL_LVL_SHIFT (25U)
+/*! USB_USE_UNSYNC_VOL_LVL - USB Use Unsync Vol Level */
+#define APU_USB_CTRL_USB_USE_UNSYNC_VOL_LVL(x)   (((uint32_t)(((uint32_t)(x)) << APU_USB_CTRL_USB_USE_UNSYNC_VOL_LVL_SHIFT)) & APU_USB_CTRL_USB_USE_UNSYNC_VOL_LVL_MASK)
+
+#define APU_USB_CTRL_USB_CLK_SEL_ACK_EXT_EN_MASK (0x80000000U)
+#define APU_USB_CTRL_USB_CLK_SEL_ACK_EXT_EN_SHIFT (31U)
+/*! USB_CLK_SEL_ACK_EXT_EN - USB Clock Select Ack Ext Enable */
+#define APU_USB_CTRL_USB_CLK_SEL_ACK_EXT_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_USB_CTRL_USB_CLK_SEL_ACK_EXT_EN_SHIFT)) & APU_USB_CTRL_USB_CLK_SEL_ACK_EXT_EN_MASK)
+/*! @} */
+
+/*! @name USB_WKUP_MASK - USB Wakeup Mask */
+/*! @{ */
+
+#define APU_USB_WKUP_MASK_USB_P_REQ_MASK_MASK    (0x1U)
+#define APU_USB_WKUP_MASK_USB_P_REQ_MASK_SHIFT   (0U)
+/*! USB_P_REQ_MASK - USB P Request Mask */
+#define APU_USB_WKUP_MASK_USB_P_REQ_MASK(x)      (((uint32_t)(((uint32_t)(x)) << APU_USB_WKUP_MASK_USB_P_REQ_MASK_SHIFT)) & APU_USB_WKUP_MASK_USB_P_REQ_MASK_MASK)
+
+#define APU_USB_WKUP_MASK_USB_AXI_CLK_REQ_MASK_MASK (0x2U)
+#define APU_USB_WKUP_MASK_USB_AXI_CLK_REQ_MASK_SHIFT (1U)
+/*! USB_AXI_CLK_REQ_MASK - USB AXI Clock Request Mask */
+#define APU_USB_WKUP_MASK_USB_AXI_CLK_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_USB_WKUP_MASK_USB_AXI_CLK_REQ_MASK_SHIFT)) & APU_USB_WKUP_MASK_USB_AXI_CLK_REQ_MASK_MASK)
+
+#define APU_USB_WKUP_MASK_USB_CLK_SEL_REQ_MASK_MASK (0x4U)
+#define APU_USB_WKUP_MASK_USB_CLK_SEL_REQ_MASK_SHIFT (2U)
+/*! USB_CLK_SEL_REQ_MASK - USB Clock Select Request Mask */
+#define APU_USB_WKUP_MASK_USB_CLK_SEL_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_USB_WKUP_MASK_USB_CLK_SEL_REQ_MASK_SHIFT)) & APU_USB_WKUP_MASK_USB_CLK_SEL_REQ_MASK_MASK)
+/*! @} */
+
+/*! @name USB_STATUS - USB Status */
+/*! @{ */
+
+#define APU_USB_STATUS_USB_P_REQ_MASK            (0x1U)
+#define APU_USB_STATUS_USB_P_REQ_SHIFT           (0U)
+/*! USB_P_REQ - USB P Request */
+#define APU_USB_STATUS_USB_P_REQ(x)              (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_USB_P_REQ_SHIFT)) & APU_USB_STATUS_USB_P_REQ_MASK)
+
+#define APU_USB_STATUS_APU_USB_P_ACK_MASK        (0x2U)
+#define APU_USB_STATUS_APU_USB_P_ACK_SHIFT       (1U)
+/*! APU_USB_P_ACK - APU USB P Ack */
+#define APU_USB_STATUS_APU_USB_P_ACK(x)          (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_APU_USB_P_ACK_SHIFT)) & APU_USB_STATUS_APU_USB_P_ACK_MASK)
+
+#define APU_USB_STATUS_USB_CLK_SEL_REQ_MASK      (0x4U)
+#define APU_USB_STATUS_USB_CLK_SEL_REQ_SHIFT     (2U)
+/*! USB_CLK_SEL_REQ - USB Clock Select Request */
+#define APU_USB_STATUS_USB_CLK_SEL_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_USB_CLK_SEL_REQ_SHIFT)) & APU_USB_STATUS_USB_CLK_SEL_REQ_MASK)
+
+#define APU_USB_STATUS_APU_USB_CLK_SEL_ACK_MASK  (0x8U)
+#define APU_USB_STATUS_APU_USB_CLK_SEL_ACK_SHIFT (3U)
+/*! APU_USB_CLK_SEL_ACK - APU USB Clock Select Ack */
+#define APU_USB_STATUS_APU_USB_CLK_SEL_ACK(x)    (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_APU_USB_CLK_SEL_ACK_SHIFT)) & APU_USB_STATUS_APU_USB_CLK_SEL_ACK_MASK)
+
+#define APU_USB_STATUS_USB_AXI_CLK_REQ_MASK      (0x10U)
+#define APU_USB_STATUS_USB_AXI_CLK_REQ_SHIFT     (4U)
+/*! USB_AXI_CLK_REQ - USB AXI Clock Request */
+#define APU_USB_STATUS_USB_AXI_CLK_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_USB_AXI_CLK_REQ_SHIFT)) & APU_USB_STATUS_USB_AXI_CLK_REQ_MASK)
+
+#define APU_USB_STATUS_APU_USB_AXI_CLK_ACK_MASK  (0x20U)
+#define APU_USB_STATUS_APU_USB_AXI_CLK_ACK_SHIFT (5U)
+/*! APU_USB_AXI_CLK_ACK - APU USB AXI Clock Ack */
+#define APU_USB_STATUS_APU_USB_AXI_CLK_ACK(x)    (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_APU_USB_AXI_CLK_ACK_SHIFT)) & APU_USB_STATUS_APU_USB_AXI_CLK_ACK_MASK)
+
+#define APU_USB_STATUS_SOC_PWR_RDY_MASK          (0x40U)
+#define APU_USB_STATUS_SOC_PWR_RDY_SHIFT         (6U)
+/*! SOC_PWR_RDY - SOC Power Ready */
+#define APU_USB_STATUS_SOC_PWR_RDY(x)            (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_SOC_PWR_RDY_SHIFT)) & APU_USB_STATUS_SOC_PWR_RDY_MASK)
+
+#define APU_USB_STATUS_APU_USB_SWITCH_PD_MASK    (0x80U)
+#define APU_USB_STATUS_APU_USB_SWITCH_PD_SHIFT   (7U)
+/*! APU_USB_SWITCH_PD - APU USB Switch Power Down */
+#define APU_USB_STATUS_APU_USB_SWITCH_PD(x)      (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_APU_USB_SWITCH_PD_SHIFT)) & APU_USB_STATUS_APU_USB_SWITCH_PD_MASK)
+
+#define APU_USB_STATUS_USB_CLK_SEL_ACK_EXT_EN_MASK (0x100U)
+#define APU_USB_STATUS_USB_CLK_SEL_ACK_EXT_EN_SHIFT (8U)
+/*! USB_CLK_SEL_ACK_EXT_EN - extension enable for the usb_clk_sel_ack */
+#define APU_USB_STATUS_USB_CLK_SEL_ACK_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_USB_CLK_SEL_ACK_EXT_EN_SHIFT)) & APU_USB_STATUS_USB_CLK_SEL_ACK_EXT_EN_MASK)
+
+#define APU_USB_STATUS_APU_USB_AXI_CLK_EN_MASK   (0x200U)
+#define APU_USB_STATUS_APU_USB_AXI_CLK_EN_SHIFT  (9U)
+/*! APU_USB_AXI_CLK_EN - APU USB AXI Clock Enable */
+#define APU_USB_STATUS_APU_USB_AXI_CLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_APU_USB_AXI_CLK_EN_SHIFT)) & APU_USB_STATUS_APU_USB_AXI_CLK_EN_MASK)
+
+#define APU_USB_STATUS_XOSC_STABLE_REFCK_MASK    (0x400U)
+#define APU_USB_STATUS_XOSC_STABLE_REFCK_SHIFT   (10U)
+/*! XOSC_STABLE_REFCK - OSC clock stable on ref clock domain */
+#define APU_USB_STATUS_XOSC_STABLE_REFCK(x)      (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_XOSC_STABLE_REFCK_SHIFT)) & APU_USB_STATUS_XOSC_STABLE_REFCK_MASK)
+
+#define APU_USB_STATUS_APU_USB_CLK_SEL_MASK      (0x800U)
+#define APU_USB_STATUS_APU_USB_CLK_SEL_SHIFT     (11U)
+/*! APU_USB_CLK_SEL - APU USB Clock Select */
+#define APU_USB_STATUS_APU_USB_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_APU_USB_CLK_SEL_SHIFT)) & APU_USB_STATUS_APU_USB_CLK_SEL_MASK)
+
+#define APU_USB_STATUS_USB_VOL_LVL_REACHED_MASK  (0x1000U)
+#define APU_USB_STATUS_USB_VOL_LVL_REACHED_SHIFT (12U)
+/*! USB_VOL_LVL_REACHED - USB Vol Level Reached */
+#define APU_USB_STATUS_USB_VOL_LVL_REACHED(x)    (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_USB_VOL_LVL_REACHED_SHIFT)) & APU_USB_STATUS_USB_VOL_LVL_REACHED_MASK)
+
+#define APU_USB_STATUS_DVFS_NOM_VOL_LVL_REACHED_MASK (0x2000U)
+#define APU_USB_STATUS_DVFS_NOM_VOL_LVL_REACHED_SHIFT (13U)
+/*! DVFS_NOM_VOL_LVL_REACHED - DVFS Nominal Vol Level Reached */
+#define APU_USB_STATUS_DVFS_NOM_VOL_LVL_REACHED(x) (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_DVFS_NOM_VOL_LVL_REACHED_SHIFT)) & APU_USB_STATUS_DVFS_NOM_VOL_LVL_REACHED_MASK)
+
+#define APU_USB_STATUS_DVFS_USB_VOL_LVL_REACHED_MASK (0x4000U)
+#define APU_USB_STATUS_DVFS_USB_VOL_LVL_REACHED_SHIFT (14U)
+/*! DVFS_USB_VOL_LVL_REACHED - DVFS USB Vol Level Reached */
+#define APU_USB_STATUS_DVFS_USB_VOL_LVL_REACHED(x) (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_DVFS_USB_VOL_LVL_REACHED_SHIFT)) & APU_USB_STATUS_DVFS_USB_VOL_LVL_REACHED_MASK)
+
+#define APU_USB_STATUS_USB_PWR_DWN_MASK          (0x8000U)
+#define APU_USB_STATUS_USB_PWR_DWN_SHIFT         (15U)
+/*! USB_PWR_DWN - USB Power Down */
+#define APU_USB_STATUS_USB_PWR_DWN(x)            (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_USB_PWR_DWN_SHIFT)) & APU_USB_STATUS_USB_PWR_DWN_MASK)
+
+#define APU_USB_STATUS_APU_USB_ST_MASK           (0xF0000U)
+#define APU_USB_STATUS_APU_USB_ST_SHIFT          (16U)
+/*! APU_USB_ST - APU USB St */
+#define APU_USB_STATUS_APU_USB_ST(x)             (((uint32_t)(((uint32_t)(x)) << APU_USB_STATUS_APU_USB_ST_SHIFT)) & APU_USB_STATUS_APU_USB_ST_MASK)
+/*! @} */
+
+/*! @name CPU1_DVFS_CTRL - CPU1 DVFS Control */
+/*! @{ */
+
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_INDEX_MASK (0xFU)
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_INDEX_SHIFT (0U)
+/*! CPU1_ACTIVE_INDEX - CPU1 Active Index */
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_INDEX(x)  (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_INDEX_SHIFT)) & APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_INDEX_MASK)
+
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_INDEX_MASK (0xF0U)
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_INDEX_SHIFT (4U)
+/*! CPU1_INACTIVE_INDEX - CPU1 Inactive Index */
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_INDEX_SHIFT)) & APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_INDEX_MASK)
+
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_SYS_INDEX_MASK (0xF00U)
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_SYS_INDEX_SHIFT (8U)
+/*! CPU1_ACTIVE_SYS_INDEX - CPU1 Active System Index */
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_SYS_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_SYS_INDEX_SHIFT)) & APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_SYS_INDEX_MASK)
+
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_SYS_INDEX_MASK (0xF000U)
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_SYS_INDEX_SHIFT (12U)
+/*! CPU1_INACTIVE_SYS_INDEX - CPU1 Inactive System Index */
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_SYS_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_SYS_INDEX_SHIFT)) & APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_SYS_INDEX_MASK)
+
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_AHB1_INDEX_MASK (0xF0000U)
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_AHB1_INDEX_SHIFT (16U)
+/*! CPU1_ACTIVE_AHB1_INDEX - CPU1 Active AHB1 Index */
+#define APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_AHB1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_AHB1_INDEX_SHIFT)) & APU_CPU1_DVFS_CTRL_CPU1_ACTIVE_AHB1_INDEX_MASK)
+
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_AHB1_INDEX_MASK (0xF00000U)
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_AHB1_INDEX_SHIFT (20U)
+/*! CPU1_INACTIVE_AHB1_INDEX - CPU1 Inactive AHB1 Index */
+#define APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_AHB1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_AHB1_INDEX_SHIFT)) & APU_CPU1_DVFS_CTRL_CPU1_INACTIVE_AHB1_INDEX_MASK)
+
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_WKUP_DEP_MASK (0x20000000U)
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_WKUP_DEP_SHIFT (29U)
+/*! PCIE_VOL_HOST_WKUP_DEP - PCIe Vol Host Wakeup Dep */
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_WKUP_DEP(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_WKUP_DEP_SHIFT)) & APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_WKUP_DEP_MASK)
+
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_FLR_DEP_MASK (0x40000000U)
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_FLR_DEP_SHIFT (30U)
+/*! PCIE_VOL_FLR_DEP - PCIe Vol Flr Dep */
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_FLR_DEP(x)   (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_PCIE_VOL_FLR_DEP_SHIFT)) & APU_CPU1_DVFS_CTRL_PCIE_VOL_FLR_DEP_MASK)
+
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_SLP_DEP_MASK (0x80000000U)
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_SLP_DEP_SHIFT (31U)
+/*! PCIE_VOL_HOST_SLP_DEP - PCIe Vol Host Sleep Dep */
+#define APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_SLP_DEP(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_SLP_DEP_SHIFT)) & APU_CPU1_DVFS_CTRL_PCIE_VOL_HOST_SLP_DEP_MASK)
+/*! @} */
+
+/*! @name CPU1_FREQ_REG1 - CPU1 Frequency 1 */
+/*! @{ */
+
+#define APU_CPU1_FREQ_REG1_CPU1_FREQ_REG1_MASK   (0xFFFFFFFFU)
+#define APU_CPU1_FREQ_REG1_CPU1_FREQ_REG1_SHIFT  (0U)
+/*! CPU1_FREQ_REG1 - CPU1 Frequency 1 */
+#define APU_CPU1_FREQ_REG1_CPU1_FREQ_REG1(x)     (((uint32_t)(((uint32_t)(x)) << APU_CPU1_FREQ_REG1_CPU1_FREQ_REG1_SHIFT)) & APU_CPU1_FREQ_REG1_CPU1_FREQ_REG1_MASK)
+/*! @} */
+
+/*! @name CPU1_FREQ_REG2 - CPU1 Frequency 2 */
+/*! @{ */
+
+#define APU_CPU1_FREQ_REG2_CPU1_FREQ_REG2_MASK   (0xFFFFFFFFU)
+#define APU_CPU1_FREQ_REG2_CPU1_FREQ_REG2_SHIFT  (0U)
+/*! CPU1_FREQ_REG2 - CPU1 Frequency 2 */
+#define APU_CPU1_FREQ_REG2_CPU1_FREQ_REG2(x)     (((uint32_t)(((uint32_t)(x)) << APU_CPU1_FREQ_REG2_CPU1_FREQ_REG2_SHIFT)) & APU_CPU1_FREQ_REG2_CPU1_FREQ_REG2_MASK)
+/*! @} */
+
+/*! @name CPU1_PLL_EN_REG - CPU1 PLL Enable */
+/*! @{ */
+
+#define APU_CPU1_PLL_EN_REG_CPU1_PLL_EN_REG_MASK (0xFFFFFFFFU)
+#define APU_CPU1_PLL_EN_REG_CPU1_PLL_EN_REG_SHIFT (0U)
+/*! CPU1_PLL_EN_REG - CPU1 PLL Enable */
+#define APU_CPU1_PLL_EN_REG_CPU1_PLL_EN_REG(x)   (((uint32_t)(((uint32_t)(x)) << APU_CPU1_PLL_EN_REG_CPU1_PLL_EN_REG_SHIFT)) & APU_CPU1_PLL_EN_REG_CPU1_PLL_EN_REG_MASK)
+/*! @} */
+
+/*! @name CPU1_VOL_REG1 - CPU1 Voltage 1 */
+/*! @{ */
+
+#define APU_CPU1_VOL_REG1_CPU1_VOL_REG1_MASK     (0xFFFFFFFFU)
+#define APU_CPU1_VOL_REG1_CPU1_VOL_REG1_SHIFT    (0U)
+/*! CPU1_VOL_REG1 - CPU1 Voltage 1 */
+#define APU_CPU1_VOL_REG1_CPU1_VOL_REG1(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU1_VOL_REG1_CPU1_VOL_REG1_SHIFT)) & APU_CPU1_VOL_REG1_CPU1_VOL_REG1_MASK)
+/*! @} */
+
+/*! @name CPU1_VOL_REG2 - CPU1 Voltage 2 */
+/*! @{ */
+
+#define APU_CPU1_VOL_REG2_CPU1_VOL_REG2_MASK     (0xFFFFFFFFU)
+#define APU_CPU1_VOL_REG2_CPU1_VOL_REG2_SHIFT    (0U)
+/*! CPU1_VOL_REG2 - CPU1 Voltage 2 */
+#define APU_CPU1_VOL_REG2_CPU1_VOL_REG2(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU1_VOL_REG2_CPU1_VOL_REG2_SHIFT)) & APU_CPU1_VOL_REG2_CPU1_VOL_REG2_MASK)
+/*! @} */
+
+/*! @name CPU1_VOL_REG3 - CPU1 Voltage 3 */
+/*! @{ */
+
+#define APU_CPU1_VOL_REG3_CPU1_VOL_REG3_MASK     (0xFFFFFFFFU)
+#define APU_CPU1_VOL_REG3_CPU1_VOL_REG3_SHIFT    (0U)
+/*! CPU1_VOL_REG3 - CPU1 Voltage 3 */
+#define APU_CPU1_VOL_REG3_CPU1_VOL_REG3(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU1_VOL_REG3_CPU1_VOL_REG3_SHIFT)) & APU_CPU1_VOL_REG3_CPU1_VOL_REG3_MASK)
+/*! @} */
+
+/*! @name CPU1_VOL_REG4 - CPU1 Voltage 4 */
+/*! @{ */
+
+#define APU_CPU1_VOL_REG4_CPU1_VOL_REG4_MASK     (0xFFFFFFFFU)
+#define APU_CPU1_VOL_REG4_CPU1_VOL_REG4_SHIFT    (0U)
+/*! CPU1_VOL_REG4 - CPU1 Voltage 4 */
+#define APU_CPU1_VOL_REG4_CPU1_VOL_REG4(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU1_VOL_REG4_CPU1_VOL_REG4_SHIFT)) & APU_CPU1_VOL_REG4_CPU1_VOL_REG4_MASK)
+/*! @} */
+
+/*! @name CPU2_DVFS_CTRL - CPU2 DVFS Control */
+/*! @{ */
+
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_INDEX_MASK (0xFU)
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_INDEX_SHIFT (0U)
+/*! CPU2_ACTIVE_INDEX - CPU2 Active Index */
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_INDEX(x)  (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_INDEX_SHIFT)) & APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_INDEX_MASK)
+
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_INDEX_MASK (0xF0U)
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_INDEX_SHIFT (4U)
+/*! CPU2_INACTIVE_INDEX - CPU2 Inactive Index */
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_INDEX_SHIFT)) & APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_INDEX_MASK)
+
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_SYS_INDEX_MASK (0xF00U)
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_SYS_INDEX_SHIFT (8U)
+/*! CPU2_ACTIVE_SYS_INDEX - CPU2 Active System Index */
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_SYS_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_SYS_INDEX_SHIFT)) & APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_SYS_INDEX_MASK)
+
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_SYS_INDEX_MASK (0xF000U)
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_SYS_INDEX_SHIFT (12U)
+/*! CPU2_INACTIVE_SYS_INDEX - CPU2 Inactive System Index */
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_SYS_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_SYS_INDEX_SHIFT)) & APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_SYS_INDEX_MASK)
+
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_AHB1_INDEX_MASK (0xF0000U)
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_AHB1_INDEX_SHIFT (16U)
+/*! CPU2_ACTIVE_AHB1_INDEX - CPU2 Active AHB1 Index */
+#define APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_AHB1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_AHB1_INDEX_SHIFT)) & APU_CPU2_DVFS_CTRL_CPU2_ACTIVE_AHB1_INDEX_MASK)
+
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_AHB1_INDEX_MASK (0xF00000U)
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_AHB1_INDEX_SHIFT (20U)
+/*! CPU2_INACTIVE_AHB1_INDEX - CPU2 Inactive AHB1 Index */
+#define APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_AHB1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_AHB1_INDEX_SHIFT)) & APU_CPU2_DVFS_CTRL_CPU2_INACTIVE_AHB1_INDEX_MASK)
+
+#define APU_CPU2_DVFS_CTRL_CPU2_AHB1_INDEX_SEL_METHOD_MASK (0x1000000U)
+#define APU_CPU2_DVFS_CTRL_CPU2_AHB1_INDEX_SEL_METHOD_SHIFT (24U)
+/*! CPU2_AHB1_INDEX_SEL_METHOD - CPU2 AHB1 index select method */
+#define APU_CPU2_DVFS_CTRL_CPU2_AHB1_INDEX_SEL_METHOD(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_CPU2_AHB1_INDEX_SEL_METHOD_SHIFT)) & APU_CPU2_DVFS_CTRL_CPU2_AHB1_INDEX_SEL_METHOD_MASK)
+
+#define APU_CPU2_DVFS_CTRL_UART_VOL_VAL_MASK     (0xFE000000U)
+#define APU_CPU2_DVFS_CTRL_UART_VOL_VAL_SHIFT    (25U)
+/*! UART_VOL_VAL - UART Vol Value */
+#define APU_CPU2_DVFS_CTRL_UART_VOL_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU2_DVFS_CTRL_UART_VOL_VAL_SHIFT)) & APU_CPU2_DVFS_CTRL_UART_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name CPU2_FREQ_REG1 - CPU2 Frequency 1 */
+/*! @{ */
+
+#define APU_CPU2_FREQ_REG1_CPU2_FREQ_REG1_MASK   (0xFFFFFFFFU)
+#define APU_CPU2_FREQ_REG1_CPU2_FREQ_REG1_SHIFT  (0U)
+/*! CPU2_FREQ_REG1 - CPU2 Frequency 1 */
+#define APU_CPU2_FREQ_REG1_CPU2_FREQ_REG1(x)     (((uint32_t)(((uint32_t)(x)) << APU_CPU2_FREQ_REG1_CPU2_FREQ_REG1_SHIFT)) & APU_CPU2_FREQ_REG1_CPU2_FREQ_REG1_MASK)
+/*! @} */
+
+/*! @name CPU2_FREQ_REG2 - CPU2 Frequency 2 */
+/*! @{ */
+
+#define APU_CPU2_FREQ_REG2_CPU2_FREQ_REG2_MASK   (0xFFFFFFFFU)
+#define APU_CPU2_FREQ_REG2_CPU2_FREQ_REG2_SHIFT  (0U)
+/*! CPU2_FREQ_REG2 - CPU2Frequency 2 */
+#define APU_CPU2_FREQ_REG2_CPU2_FREQ_REG2(x)     (((uint32_t)(((uint32_t)(x)) << APU_CPU2_FREQ_REG2_CPU2_FREQ_REG2_SHIFT)) & APU_CPU2_FREQ_REG2_CPU2_FREQ_REG2_MASK)
+/*! @} */
+
+/*! @name CPU2_PLL_EN_REG - CPU2 PLL Enable */
+/*! @{ */
+
+#define APU_CPU2_PLL_EN_REG_CPU2_PLL_EN_REG_MASK (0xFFFFFFFFU)
+#define APU_CPU2_PLL_EN_REG_CPU2_PLL_EN_REG_SHIFT (0U)
+/*! CPU2_PLL_EN_REG - CPU2 PLL Enable */
+#define APU_CPU2_PLL_EN_REG_CPU2_PLL_EN_REG(x)   (((uint32_t)(((uint32_t)(x)) << APU_CPU2_PLL_EN_REG_CPU2_PLL_EN_REG_SHIFT)) & APU_CPU2_PLL_EN_REG_CPU2_PLL_EN_REG_MASK)
+/*! @} */
+
+/*! @name CPU2_VOL_REG1 - CPU2 Voltage 1 */
+/*! @{ */
+
+#define APU_CPU2_VOL_REG1_CPU2_VOL_REG1_MASK     (0xFFFFFFFFU)
+#define APU_CPU2_VOL_REG1_CPU2_VOL_REG1_SHIFT    (0U)
+/*! CPU2_VOL_REG1 - CPU2 Voltage 1 */
+#define APU_CPU2_VOL_REG1_CPU2_VOL_REG1(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU2_VOL_REG1_CPU2_VOL_REG1_SHIFT)) & APU_CPU2_VOL_REG1_CPU2_VOL_REG1_MASK)
+/*! @} */
+
+/*! @name CPU2_VOL_REG2 - CPU2 Voltage 2 */
+/*! @{ */
+
+#define APU_CPU2_VOL_REG2_CPU2_VOL_REG2_MASK     (0xFFFFFFFFU)
+#define APU_CPU2_VOL_REG2_CPU2_VOL_REG2_SHIFT    (0U)
+/*! CPU2_VOL_REG2 - CPU2 Voltage 2 */
+#define APU_CPU2_VOL_REG2_CPU2_VOL_REG2(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU2_VOL_REG2_CPU2_VOL_REG2_SHIFT)) & APU_CPU2_VOL_REG2_CPU2_VOL_REG2_MASK)
+/*! @} */
+
+/*! @name CPU2_VOL_REG3 - CPU2 Voltage 3 */
+/*! @{ */
+
+#define APU_CPU2_VOL_REG3_CPU2_VOL_REG3_MASK     (0xFFFFFFFFU)
+#define APU_CPU2_VOL_REG3_CPU2_VOL_REG3_SHIFT    (0U)
+/*! CPU2_VOL_REG3 - CPU2 Voltage 3 */
+#define APU_CPU2_VOL_REG3_CPU2_VOL_REG3(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU2_VOL_REG3_CPU2_VOL_REG3_SHIFT)) & APU_CPU2_VOL_REG3_CPU2_VOL_REG3_MASK)
+/*! @} */
+
+/*! @name CPU2_VOL_REG4 - CPU2 Voltage 4 */
+/*! @{ */
+
+#define APU_CPU2_VOL_REG4_CPU2_VOL_REG4_MASK     (0xFFFFFFFFU)
+#define APU_CPU2_VOL_REG4_CPU2_VOL_REG4_SHIFT    (0U)
+/*! CPU2_VOL_REG4 - CPU2 Voltage 4 */
+#define APU_CPU2_VOL_REG4_CPU2_VOL_REG4(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU2_VOL_REG4_CPU2_VOL_REG4_SHIFT)) & APU_CPU2_VOL_REG4_CPU2_VOL_REG4_MASK)
+/*! @} */
+
+/*! @name SYS_FREQ_REG1 - System Frequency 1 */
+/*! @{ */
+
+#define APU_SYS_FREQ_REG1_SYS_FREQ_REG1_MASK     (0xFFFFFFFFU)
+#define APU_SYS_FREQ_REG1_SYS_FREQ_REG1_SHIFT    (0U)
+/*! SYS_FREQ_REG1 - System Frequency 1 */
+#define APU_SYS_FREQ_REG1_SYS_FREQ_REG1(x)       (((uint32_t)(((uint32_t)(x)) << APU_SYS_FREQ_REG1_SYS_FREQ_REG1_SHIFT)) & APU_SYS_FREQ_REG1_SYS_FREQ_REG1_MASK)
+/*! @} */
+
+/*! @name SYS_FREQ_REG2 - System Frequency 2 */
+/*! @{ */
+
+#define APU_SYS_FREQ_REG2_SYS_FREQ_REG2_MASK     (0xFFFFFFFFU)
+#define APU_SYS_FREQ_REG2_SYS_FREQ_REG2_SHIFT    (0U)
+/*! SYS_FREQ_REG2 - System Frequency 2 */
+#define APU_SYS_FREQ_REG2_SYS_FREQ_REG2(x)       (((uint32_t)(((uint32_t)(x)) << APU_SYS_FREQ_REG2_SYS_FREQ_REG2_SHIFT)) & APU_SYS_FREQ_REG2_SYS_FREQ_REG2_MASK)
+/*! @} */
+
+/*! @name SYS_PLL_EN_REG - System PLL Enable */
+/*! @{ */
+
+#define APU_SYS_PLL_EN_REG_SYS_PLL_EN_REG_MASK   (0xFFFFFFFFU)
+#define APU_SYS_PLL_EN_REG_SYS_PLL_EN_REG_SHIFT  (0U)
+/*! SYS_PLL_EN_REG - System PLL Enable */
+#define APU_SYS_PLL_EN_REG_SYS_PLL_EN_REG(x)     (((uint32_t)(((uint32_t)(x)) << APU_SYS_PLL_EN_REG_SYS_PLL_EN_REG_SHIFT)) & APU_SYS_PLL_EN_REG_SYS_PLL_EN_REG_MASK)
+/*! @} */
+
+/*! @name SYS_VOL_REG1 - System Voltage 1 */
+/*! @{ */
+
+#define APU_SYS_VOL_REG1_SYS_VOL_REG1_MASK       (0xFFFFFFFFU)
+#define APU_SYS_VOL_REG1_SYS_VOL_REG1_SHIFT      (0U)
+/*! SYS_VOL_REG1 - System Voltage 1 */
+#define APU_SYS_VOL_REG1_SYS_VOL_REG1(x)         (((uint32_t)(((uint32_t)(x)) << APU_SYS_VOL_REG1_SYS_VOL_REG1_SHIFT)) & APU_SYS_VOL_REG1_SYS_VOL_REG1_MASK)
+/*! @} */
+
+/*! @name SYS_VOL_REG2 - System Voltage 2 */
+/*! @{ */
+
+#define APU_SYS_VOL_REG2_SYS_VOL_REG2_MASK       (0xFFFFFFFFU)
+#define APU_SYS_VOL_REG2_SYS_VOL_REG2_SHIFT      (0U)
+/*! SYS_VOL_REG2 - System Voltage 2 */
+#define APU_SYS_VOL_REG2_SYS_VOL_REG2(x)         (((uint32_t)(((uint32_t)(x)) << APU_SYS_VOL_REG2_SYS_VOL_REG2_SHIFT)) & APU_SYS_VOL_REG2_SYS_VOL_REG2_MASK)
+/*! @} */
+
+/*! @name SYS_VOL_REG3 - System Voltage 3 */
+/*! @{ */
+
+#define APU_SYS_VOL_REG3_SYS_VOL_REG3_MASK       (0xFFFFFFFFU)
+#define APU_SYS_VOL_REG3_SYS_VOL_REG3_SHIFT      (0U)
+/*! SYS_VOL_REG3 - System Voltage 3 */
+#define APU_SYS_VOL_REG3_SYS_VOL_REG3(x)         (((uint32_t)(((uint32_t)(x)) << APU_SYS_VOL_REG3_SYS_VOL_REG3_SHIFT)) & APU_SYS_VOL_REG3_SYS_VOL_REG3_MASK)
+/*! @} */
+
+/*! @name SYS_VOL_REG4 - System Voltage 4 */
+/*! @{ */
+
+#define APU_SYS_VOL_REG4_SYS_VOL_REG4_MASK       (0xFFFFFFFFU)
+#define APU_SYS_VOL_REG4_SYS_VOL_REG4_SHIFT      (0U)
+/*! SYS_VOL_REG4 - System Voltage 4 */
+#define APU_SYS_VOL_REG4_SYS_VOL_REG4(x)         (((uint32_t)(((uint32_t)(x)) << APU_SYS_VOL_REG4_SYS_VOL_REG4_SHIFT)) & APU_SYS_VOL_REG4_SYS_VOL_REG4_MASK)
+/*! @} */
+
+/*! @name DVFS_CTRL - DVFS Control */
+/*! @{ */
+
+#define APU_DVFS_CTRL_DVFS_HOST_VOL_VAL_MASK     (0x7FU)
+#define APU_DVFS_CTRL_DVFS_HOST_VOL_VAL_SHIFT    (0U)
+/*! DVFS_HOST_VOL_VAL - DVFS Host Vol Value */
+#define APU_DVFS_CTRL_DVFS_HOST_VOL_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_DVFS_HOST_VOL_VAL_SHIFT)) & APU_DVFS_CTRL_DVFS_HOST_VOL_VAL_MASK)
+
+#define APU_DVFS_CTRL_DVFS_EAS_VOL_MASK          (0x3F80U)
+#define APU_DVFS_CTRL_DVFS_EAS_VOL_SHIFT         (7U)
+/*! DVFS_EAS_VOL - DVFS EAS Vol */
+#define APU_DVFS_CTRL_DVFS_EAS_VOL(x)            (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_DVFS_EAS_VOL_SHIFT)) & APU_DVFS_CTRL_DVFS_EAS_VOL_MASK)
+
+#define APU_DVFS_CTRL_DVFS_CLK_SWITCH_EN_MASK    (0x4000U)
+#define APU_DVFS_CTRL_DVFS_CLK_SWITCH_EN_SHIFT   (14U)
+/*! DVFS_CLK_SWITCH_EN - DVFS Clock Switch Enable */
+#define APU_DVFS_CTRL_DVFS_CLK_SWITCH_EN(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_DVFS_CLK_SWITCH_EN_SHIFT)) & APU_DVFS_CTRL_DVFS_CLK_SWITCH_EN_MASK)
+
+#define APU_DVFS_CTRL_DVFS_DYN_CLK_EN_MASK       (0x8000U)
+#define APU_DVFS_CTRL_DVFS_DYN_CLK_EN_SHIFT      (15U)
+/*! DVFS_DYN_CLK_EN - DVFS Dynamic Clock Enable */
+#define APU_DVFS_CTRL_DVFS_DYN_CLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_DVFS_DYN_CLK_EN_SHIFT)) & APU_DVFS_CTRL_DVFS_DYN_CLK_EN_MASK)
+
+#define APU_DVFS_CTRL_DVFS_MODE_MASK             (0x10000U)
+#define APU_DVFS_CTRL_DVFS_MODE_SHIFT            (16U)
+/*! DVFS_MODE - DVFS Mode 0: only use partial_dvfs_vol(default) */
+#define APU_DVFS_CTRL_DVFS_MODE(x)               (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_DVFS_MODE_SHIFT)) & APU_DVFS_CTRL_DVFS_MODE_MASK)
+
+#define APU_DVFS_CTRL_EN_FASTER_DYN_CLK_MASK     (0x20000U)
+#define APU_DVFS_CTRL_EN_FASTER_DYN_CLK_SHIFT    (17U)
+/*! EN_FASTER_DYN_CLK - Enable Faster Dynamic Clock */
+#define APU_DVFS_CTRL_EN_FASTER_DYN_CLK(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_EN_FASTER_DYN_CLK_SHIFT)) & APU_DVFS_CTRL_EN_FASTER_DYN_CLK_MASK)
+
+#define APU_DVFS_CTRL_DVFS_EAS_VOL_DIS_MASK      (0x40000U)
+#define APU_DVFS_CTRL_DVFS_EAS_VOL_DIS_SHIFT     (18U)
+/*! DVFS_EAS_VOL_DIS - DVFS EAS Vol Disable */
+#define APU_DVFS_CTRL_DVFS_EAS_VOL_DIS(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_DVFS_EAS_VOL_DIS_SHIFT)) & APU_DVFS_CTRL_DVFS_EAS_VOL_DIS_MASK)
+
+#define APU_DVFS_CTRL_SW_LOCK_GUARD_DIS_MASK     (0x80000U)
+#define APU_DVFS_CTRL_SW_LOCK_GUARD_DIS_SHIFT    (19U)
+/*! SW_LOCK_GUARD_DIS - SW Lock Guard Disable */
+#define APU_DVFS_CTRL_SW_LOCK_GUARD_DIS(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_SW_LOCK_GUARD_DIS_SHIFT)) & APU_DVFS_CTRL_SW_LOCK_GUARD_DIS_MASK)
+
+#define APU_DVFS_CTRL_EN_FASTER_DVFS_MASK        (0x100000U)
+#define APU_DVFS_CTRL_EN_FASTER_DVFS_SHIFT       (20U)
+/*! EN_FASTER_DVFS - Enable Faster DVFS */
+#define APU_DVFS_CTRL_EN_FASTER_DVFS(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_EN_FASTER_DVFS_SHIFT)) & APU_DVFS_CTRL_EN_FASTER_DVFS_MASK)
+
+#define APU_DVFS_CTRL_UPDATE_BUCK_EN_MASK        (0x200000U)
+#define APU_DVFS_CTRL_UPDATE_BUCK_EN_SHIFT       (21U)
+/*! UPDATE_BUCK_EN - to enable the forcing buck value when the resolution is not aligned */
+#define APU_DVFS_CTRL_UPDATE_BUCK_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_UPDATE_BUCK_EN_SHIFT)) & APU_DVFS_CTRL_UPDATE_BUCK_EN_MASK)
+
+#define APU_DVFS_CTRL_INACTIVE_ACK_EXT_EN_MASK   (0x1000000U)
+#define APU_DVFS_CTRL_INACTIVE_ACK_EXT_EN_SHIFT  (24U)
+/*! INACTIVE_ACK_EXT_EN - Inactive Ack Ext Enable */
+#define APU_DVFS_CTRL_INACTIVE_ACK_EXT_EN(x)     (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_INACTIVE_ACK_EXT_EN_SHIFT)) & APU_DVFS_CTRL_INACTIVE_ACK_EXT_EN_MASK)
+
+#define APU_DVFS_CTRL_SDIO_VOL_VAL_MASK          (0xFE000000U)
+#define APU_DVFS_CTRL_SDIO_VOL_VAL_SHIFT         (25U)
+/*! SDIO_VOL_VAL - SDIO Vol Value */
+#define APU_DVFS_CTRL_SDIO_VOL_VAL(x)            (((uint32_t)(((uint32_t)(x)) << APU_DVFS_CTRL_SDIO_VOL_VAL_SHIFT)) & APU_DVFS_CTRL_SDIO_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name PARTIAL_DVFS_CTRL - Partial DVFS Control */
+/*! @{ */
+
+#define APU_PARTIAL_DVFS_CTRL_PARTIAL_DVFS_VOL_MASK (0x7FU)
+#define APU_PARTIAL_DVFS_CTRL_PARTIAL_DVFS_VOL_SHIFT (0U)
+/*! PARTIAL_DVFS_VOL - Partial DVFS Vol */
+#define APU_PARTIAL_DVFS_CTRL_PARTIAL_DVFS_VOL(x) (((uint32_t)(((uint32_t)(x)) << APU_PARTIAL_DVFS_CTRL_PARTIAL_DVFS_VOL_SHIFT)) & APU_PARTIAL_DVFS_CTRL_PARTIAL_DVFS_VOL_MASK)
+
+#define APU_PARTIAL_DVFS_CTRL_STATIC_PLL_EN_MASK (0x80U)
+#define APU_PARTIAL_DVFS_CTRL_STATIC_PLL_EN_SHIFT (7U)
+/*! STATIC_PLL_EN - Static PLL Enable */
+#define APU_PARTIAL_DVFS_CTRL_STATIC_PLL_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_PARTIAL_DVFS_CTRL_STATIC_PLL_EN_SHIFT)) & APU_PARTIAL_DVFS_CTRL_STATIC_PLL_EN_MASK)
+
+#define APU_PARTIAL_DVFS_CTRL_STATIC_DVFS_FREQ_MASK (0xF00U)
+#define APU_PARTIAL_DVFS_CTRL_STATIC_DVFS_FREQ_SHIFT (8U)
+/*! STATIC_DVFS_FREQ - Static DVFS Frequency */
+#define APU_PARTIAL_DVFS_CTRL_STATIC_DVFS_FREQ(x) (((uint32_t)(((uint32_t)(x)) << APU_PARTIAL_DVFS_CTRL_STATIC_DVFS_FREQ_SHIFT)) & APU_PARTIAL_DVFS_CTRL_STATIC_DVFS_FREQ_MASK)
+
+#define APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_REF_MASK (0x1F0000U)
+#define APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_REF_SHIFT (16U)
+/*! VOL_RESOLUTION_REF - Vol Resolution Ref */
+#define APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_REF(x) (((uint32_t)(((uint32_t)(x)) << APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_REF_SHIFT)) & APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_REF_MASK)
+
+#define APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_SLP_MASK (0x3E00000U)
+#define APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_SLP_SHIFT (21U)
+/*! VOL_RESOLUTION_SLP - Vol Resolution Sleep */
+#define APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_SLP(x) (((uint32_t)(((uint32_t)(x)) << APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_SLP_SHIFT)) & APU_PARTIAL_DVFS_CTRL_VOL_RESOLUTION_SLP_MASK)
+
+#define APU_PARTIAL_DVFS_CTRL_BYPASS_DVFS_FSM_MASK (0x80000000U)
+#define APU_PARTIAL_DVFS_CTRL_BYPASS_DVFS_FSM_SHIFT (31U)
+/*! BYPASS_DVFS_FSM - Bypass DVFS FSM */
+#define APU_PARTIAL_DVFS_CTRL_BYPASS_DVFS_FSM(x) (((uint32_t)(((uint32_t)(x)) << APU_PARTIAL_DVFS_CTRL_BYPASS_DVFS_FSM_SHIFT)) & APU_PARTIAL_DVFS_CTRL_BYPASS_DVFS_FSM_MASK)
+/*! @} */
+
+/*! @name DVFS_TIMER - DVFS Timer */
+/*! @{ */
+
+#define APU_DVFS_TIMER_SLP_CNT_MASK              (0xFFFFU)
+#define APU_DVFS_TIMER_SLP_CNT_SHIFT             (0U)
+/*! SLP_CNT - Sleep Count */
+#define APU_DVFS_TIMER_SLP_CNT(x)                (((uint32_t)(((uint32_t)(x)) << APU_DVFS_TIMER_SLP_CNT_SHIFT)) & APU_DVFS_TIMER_SLP_CNT_MASK)
+
+#define APU_DVFS_TIMER_REF_CNT_MASK              (0xFFFF0000U)
+#define APU_DVFS_TIMER_REF_CNT_SHIFT             (16U)
+/*! REF_CNT - Reference Count */
+#define APU_DVFS_TIMER_REF_CNT(x)                (((uint32_t)(((uint32_t)(x)) << APU_DVFS_TIMER_REF_CNT_SHIFT)) & APU_DVFS_TIMER_REF_CNT_MASK)
+/*! @} */
+
+/*! @name AHB1_FREQ_REG1 - AHB1 Frequency 1 */
+/*! @{ */
+
+#define APU_AHB1_FREQ_REG1_AHB1_FREQ_REG1_MASK   (0xFFFFFFFFU)
+#define APU_AHB1_FREQ_REG1_AHB1_FREQ_REG1_SHIFT  (0U)
+/*! AHB1_FREQ_REG1 - AHB1 Frequency 1 */
+#define APU_AHB1_FREQ_REG1_AHB1_FREQ_REG1(x)     (((uint32_t)(((uint32_t)(x)) << APU_AHB1_FREQ_REG1_AHB1_FREQ_REG1_SHIFT)) & APU_AHB1_FREQ_REG1_AHB1_FREQ_REG1_MASK)
+/*! @} */
+
+/*! @name AHB1_FREQ_REG2 - AHB1 Frequency 2 */
+/*! @{ */
+
+#define APU_AHB1_FREQ_REG2_AHB1_FREQ_REG2_MASK   (0xFFFFFFFFU)
+#define APU_AHB1_FREQ_REG2_AHB1_FREQ_REG2_SHIFT  (0U)
+/*! AHB1_FREQ_REG2 - AHB1 Frequency 2 */
+#define APU_AHB1_FREQ_REG2_AHB1_FREQ_REG2(x)     (((uint32_t)(((uint32_t)(x)) << APU_AHB1_FREQ_REG2_AHB1_FREQ_REG2_SHIFT)) & APU_AHB1_FREQ_REG2_AHB1_FREQ_REG2_MASK)
+/*! @} */
+
+/*! @name AHB1_PLL_EN_REG - AHB1 PLL Enable */
+/*! @{ */
+
+#define APU_AHB1_PLL_EN_REG_AHB1_PLL_EN_REG_MASK (0xFFFFFFFFU)
+#define APU_AHB1_PLL_EN_REG_AHB1_PLL_EN_REG_SHIFT (0U)
+/*! AHB1_PLL_EN_REG - AHB1 PLL Enable */
+#define APU_AHB1_PLL_EN_REG_AHB1_PLL_EN_REG(x)   (((uint32_t)(((uint32_t)(x)) << APU_AHB1_PLL_EN_REG_AHB1_PLL_EN_REG_SHIFT)) & APU_AHB1_PLL_EN_REG_AHB1_PLL_EN_REG_MASK)
+/*! @} */
+
+/*! @name AHB1_VOL_REG1 - AHB1 Voltage 1 */
+/*! @{ */
+
+#define APU_AHB1_VOL_REG1_AHB1_VOL_REG1_MASK     (0xFFFFFFFFU)
+#define APU_AHB1_VOL_REG1_AHB1_VOL_REG1_SHIFT    (0U)
+/*! AHB1_VOL_REG1 - AHB1 Voltage 1 */
+#define APU_AHB1_VOL_REG1_AHB1_VOL_REG1(x)       (((uint32_t)(((uint32_t)(x)) << APU_AHB1_VOL_REG1_AHB1_VOL_REG1_SHIFT)) & APU_AHB1_VOL_REG1_AHB1_VOL_REG1_MASK)
+/*! @} */
+
+/*! @name AHB1_VOL_REG2 - AHB1 Voltage 2 */
+/*! @{ */
+
+#define APU_AHB1_VOL_REG2_AHB1_VOL_REG2_MASK     (0xFFFFFFFFU)
+#define APU_AHB1_VOL_REG2_AHB1_VOL_REG2_SHIFT    (0U)
+/*! AHB1_VOL_REG2 - AHB1 Voltage 2 */
+#define APU_AHB1_VOL_REG2_AHB1_VOL_REG2(x)       (((uint32_t)(((uint32_t)(x)) << APU_AHB1_VOL_REG2_AHB1_VOL_REG2_SHIFT)) & APU_AHB1_VOL_REG2_AHB1_VOL_REG2_MASK)
+/*! @} */
+
+/*! @name AHB1_VOL_REG3 - AHB1 Voltage 3 */
+/*! @{ */
+
+#define APU_AHB1_VOL_REG3_AHB1_VOL_REG3_MASK     (0xFFFFFFFFU)
+#define APU_AHB1_VOL_REG3_AHB1_VOL_REG3_SHIFT    (0U)
+/*! AHB1_VOL_REG3 - AHB1 Voltage 3 */
+#define APU_AHB1_VOL_REG3_AHB1_VOL_REG3(x)       (((uint32_t)(((uint32_t)(x)) << APU_AHB1_VOL_REG3_AHB1_VOL_REG3_SHIFT)) & APU_AHB1_VOL_REG3_AHB1_VOL_REG3_MASK)
+/*! @} */
+
+/*! @name AHB1_VOL_REG4 - AHB1 Voltage 4 */
+/*! @{ */
+
+#define APU_AHB1_VOL_REG4_AHB1_VOL_REG4_MASK     (0xFFFFFFFFU)
+#define APU_AHB1_VOL_REG4_AHB1_VOL_REG4_SHIFT    (0U)
+/*! AHB1_VOL_REG4 - AHB1 Voltage 4 */
+#define APU_AHB1_VOL_REG4_AHB1_VOL_REG4(x)       (((uint32_t)(((uint32_t)(x)) << APU_AHB1_VOL_REG4_AHB1_VOL_REG4_SHIFT)) & APU_AHB1_VOL_REG4_AHB1_VOL_REG4_MASK)
+/*! @} */
+
+/*! @name DVFS_STATUS - DVFS Status */
+/*! @{ */
+
+#define APU_DVFS_STATUS_SYS_LOCK_FREQ_MASK       (0x1U)
+#define APU_DVFS_STATUS_SYS_LOCK_FREQ_SHIFT      (0U)
+/*! SYS_LOCK_FREQ - System Lock Frequency */
+#define APU_DVFS_STATUS_SYS_LOCK_FREQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_SYS_LOCK_FREQ_SHIFT)) & APU_DVFS_STATUS_SYS_LOCK_FREQ_MASK)
+
+#define APU_DVFS_STATUS_CPU2_LOCK_FREQ_MASK      (0x2U)
+#define APU_DVFS_STATUS_CPU2_LOCK_FREQ_SHIFT     (1U)
+/*! CPU2_LOCK_FREQ - CPU2 Lock Frequency */
+#define APU_DVFS_STATUS_CPU2_LOCK_FREQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_CPU2_LOCK_FREQ_SHIFT)) & APU_DVFS_STATUS_CPU2_LOCK_FREQ_MASK)
+
+#define APU_DVFS_STATUS_CPU1_LOCK_FREQ_MASK      (0x4U)
+#define APU_DVFS_STATUS_CPU1_LOCK_FREQ_SHIFT     (2U)
+/*! CPU1_LOCK_FREQ - CPU1 Lock Frequency */
+#define APU_DVFS_STATUS_CPU1_LOCK_FREQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_CPU1_LOCK_FREQ_SHIFT)) & APU_DVFS_STATUS_CPU1_LOCK_FREQ_MASK)
+
+#define APU_DVFS_STATUS_LOCK_FREQ_REQ_MASK       (0x8U)
+#define APU_DVFS_STATUS_LOCK_FREQ_REQ_SHIFT      (3U)
+/*! LOCK_FREQ_REQ - Lock Frequency Request */
+#define APU_DVFS_STATUS_LOCK_FREQ_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_LOCK_FREQ_REQ_SHIFT)) & APU_DVFS_STATUS_LOCK_FREQ_REQ_MASK)
+
+#define APU_DVFS_STATUS_SYS_LOCK_VOL_MASK        (0x10U)
+#define APU_DVFS_STATUS_SYS_LOCK_VOL_SHIFT       (4U)
+/*! SYS_LOCK_VOL - System Lock Vol */
+#define APU_DVFS_STATUS_SYS_LOCK_VOL(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_SYS_LOCK_VOL_SHIFT)) & APU_DVFS_STATUS_SYS_LOCK_VOL_MASK)
+
+#define APU_DVFS_STATUS_CPU2_LOCK_VOL_MASK       (0x20U)
+#define APU_DVFS_STATUS_CPU2_LOCK_VOL_SHIFT      (5U)
+/*! CPU2_LOCK_VOL - CPU2 Lock Vol */
+#define APU_DVFS_STATUS_CPU2_LOCK_VOL(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_CPU2_LOCK_VOL_SHIFT)) & APU_DVFS_STATUS_CPU2_LOCK_VOL_MASK)
+
+#define APU_DVFS_STATUS_CPU1_LOCK_VOL_MASK       (0x40U)
+#define APU_DVFS_STATUS_CPU1_LOCK_VOL_SHIFT      (6U)
+/*! CPU1_LOCK_VOL - CPU1 Lock Vol */
+#define APU_DVFS_STATUS_CPU1_LOCK_VOL(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_CPU1_LOCK_VOL_SHIFT)) & APU_DVFS_STATUS_CPU1_LOCK_VOL_MASK)
+
+#define APU_DVFS_STATUS_LOCK_VOL_REQ_MASK        (0x80U)
+#define APU_DVFS_STATUS_LOCK_VOL_REQ_SHIFT       (7U)
+/*! LOCK_VOL_REQ - Lock Vol Request */
+#define APU_DVFS_STATUS_LOCK_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_LOCK_VOL_REQ_SHIFT)) & APU_DVFS_STATUS_LOCK_VOL_REQ_MASK)
+
+#define APU_DVFS_STATUS_SYS_FREQ_CTRL_MASK       (0xF00U)
+#define APU_DVFS_STATUS_SYS_FREQ_CTRL_SHIFT      (8U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_STATUS_SYS_FREQ_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_STATUS_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_STATUS_CPU2_FREQ_CTRL_MASK      (0xF000U)
+#define APU_DVFS_STATUS_CPU2_FREQ_CTRL_SHIFT     (12U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_STATUS_CPU2_FREQ_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_STATUS_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_STATUS_CPU1_FREQ_CTRL_MASK      (0xF0000U)
+#define APU_DVFS_STATUS_CPU1_FREQ_CTRL_SHIFT     (16U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_STATUS_CPU1_FREQ_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_STATUS_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_STATUS_SOC_POWER_LVL_REACHED_MASK (0x100000U)
+#define APU_DVFS_STATUS_SOC_POWER_LVL_REACHED_SHIFT (20U)
+/*! SOC_POWER_LVL_REACHED - SoC Power Level Reached */
+#define APU_DVFS_STATUS_SOC_POWER_LVL_REACHED(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_SOC_POWER_LVL_REACHED_SHIFT)) & APU_DVFS_STATUS_SOC_POWER_LVL_REACHED_MASK)
+
+#define APU_DVFS_STATUS_USB_VOL_LVL_REACHED_MASK (0x200000U)
+#define APU_DVFS_STATUS_USB_VOL_LVL_REACHED_SHIFT (21U)
+/*! USB_VOL_LVL_REACHED - USB Vol Level Reached */
+#define APU_DVFS_STATUS_USB_VOL_LVL_REACHED(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_USB_VOL_LVL_REACHED_SHIFT)) & APU_DVFS_STATUS_USB_VOL_LVL_REACHED_MASK)
+
+#define APU_DVFS_STATUS_PCIE_VOL_LVL_REACHED_MASK (0x400000U)
+#define APU_DVFS_STATUS_PCIE_VOL_LVL_REACHED_SHIFT (22U)
+/*! PCIE_VOL_LVL_REACHED - PCIe Vol Level Reached */
+#define APU_DVFS_STATUS_PCIE_VOL_LVL_REACHED(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_PCIE_VOL_LVL_REACHED_SHIFT)) & APU_DVFS_STATUS_PCIE_VOL_LVL_REACHED_MASK)
+
+#define APU_DVFS_STATUS_APU_BUCK_LVL_CTRL_MASK   (0x3F800000U)
+#define APU_DVFS_STATUS_APU_BUCK_LVL_CTRL_SHIFT  (23U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_STATUS_APU_BUCK_LVL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_STATUS_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_STATUS_SW_FREQ_GAURD_MASK       (0x40000000U)
+#define APU_DVFS_STATUS_SW_FREQ_GAURD_SHIFT      (30U)
+/*! SW_FREQ_GAURD - SW Frequency Guard */
+#define APU_DVFS_STATUS_SW_FREQ_GAURD(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_SW_FREQ_GAURD_SHIFT)) & APU_DVFS_STATUS_SW_FREQ_GAURD_MASK)
+
+#define APU_DVFS_STATUS_SW_LOCK_GAURD_MASK       (0x80000000U)
+#define APU_DVFS_STATUS_SW_LOCK_GAURD_SHIFT      (31U)
+/*! SW_LOCK_GAURD - SW Lock Guard */
+#define APU_DVFS_STATUS_SW_LOCK_GAURD(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_STATUS_SW_LOCK_GAURD_SHIFT)) & APU_DVFS_STATUS_SW_LOCK_GAURD_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_CTRL - DVFS Debug Control */
+/*! @{ */
+
+#define APU_DVFS_DBG_CTRL_DVFS_DBG_MODE_MASK     (0x1U)
+#define APU_DVFS_DBG_CTRL_DVFS_DBG_MODE_SHIFT    (0U)
+/*! DVFS_DBG_MODE - DVFS Debug Mode */
+#define APU_DVFS_DBG_CTRL_DVFS_DBG_MODE(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_DVFS_DBG_MODE_SHIFT)) & APU_DVFS_DBG_CTRL_DVFS_DBG_MODE_MASK)
+
+#define APU_DVFS_DBG_CTRL_START_TRIGGER_MASK     (0x2U)
+#define APU_DVFS_DBG_CTRL_START_TRIGGER_SHIFT    (1U)
+/*! START_TRIGGER - Start Trigger */
+#define APU_DVFS_DBG_CTRL_START_TRIGGER(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_START_TRIGGER_SHIFT)) & APU_DVFS_DBG_CTRL_START_TRIGGER_MASK)
+
+#define APU_DVFS_DBG_CTRL_END_TRIGGER_MASK       (0x4U)
+#define APU_DVFS_DBG_CTRL_END_TRIGGER_SHIFT      (2U)
+/*! END_TRIGGER - End Trigger */
+#define APU_DVFS_DBG_CTRL_END_TRIGGER(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_END_TRIGGER_SHIFT)) & APU_DVFS_DBG_CTRL_END_TRIGGER_MASK)
+
+#define APU_DVFS_DBG_CTRL_DBG_VOL_SEL_MASK       (0x70U)
+#define APU_DVFS_DBG_CTRL_DBG_VOL_SEL_SHIFT      (4U)
+/*! DBG_VOL_SEL - Debug Vol Select */
+#define APU_DVFS_DBG_CTRL_DBG_VOL_SEL(x)         (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_DBG_VOL_SEL_SHIFT)) & APU_DVFS_DBG_CTRL_DBG_VOL_SEL_MASK)
+
+#define APU_DVFS_DBG_CTRL_DBG_SLP_TIMER_SEL_MASK (0x300U)
+#define APU_DVFS_DBG_CTRL_DBG_SLP_TIMER_SEL_SHIFT (8U)
+/*! DBG_SLP_TIMER_SEL - Debug Sleep Timer Select */
+#define APU_DVFS_DBG_CTRL_DBG_SLP_TIMER_SEL(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_DBG_SLP_TIMER_SEL_SHIFT)) & APU_DVFS_DBG_CTRL_DBG_SLP_TIMER_SEL_MASK)
+
+#define APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_BYPASS_MASK (0x1000U)
+#define APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_BYPASS_SHIFT (12U)
+/*! DVFS_CLK_SEL_FW_BYPASS - DVFS Clock Select FW Bypass */
+#define APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_BYPASS_SHIFT)) & APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_BYPASS_MASK)
+
+#define APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_VAL_MASK (0x2000U)
+#define APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_VAL_SHIFT (13U)
+/*! DVFS_CLK_SEL_FW_VAL - DVFS Clock Select FW Value */
+#define APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_VAL_SHIFT)) & APU_DVFS_DBG_CTRL_DVFS_CLK_SEL_FW_VAL_MASK)
+
+#define APU_DVFS_DBG_CTRL_BUCK_EFF_MODE_FIX_MASK (0x8000U)
+#define APU_DVFS_DBG_CTRL_BUCK_EFF_MODE_FIX_SHIFT (15U)
+/*! BUCK_EFF_MODE_FIX - BUCK Efficiency Mode Fix */
+#define APU_DVFS_DBG_CTRL_BUCK_EFF_MODE_FIX(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_BUCK_EFF_MODE_FIX_SHIFT)) & APU_DVFS_DBG_CTRL_BUCK_EFF_MODE_FIX_MASK)
+
+#define APU_DVFS_DBG_CTRL_SD_CLK_SWITCH_OK_MASK_MASK (0x10000U)
+#define APU_DVFS_DBG_CTRL_SD_CLK_SWITCH_OK_MASK_SHIFT (16U)
+/*! SD_CLK_SWITCH_OK_MASK - SD Clock Switch Ok Mask */
+#define APU_DVFS_DBG_CTRL_SD_CLK_SWITCH_OK_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_CTRL_SD_CLK_SWITCH_OK_MASK_SHIFT)) & APU_DVFS_DBG_CTRL_SD_CLK_SWITCH_OK_MASK_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_PATTERN_DATA - DVFS Debug Pattern Data */
+/*! @{ */
+
+#define APU_DVFS_DBG_PATTERN_DATA_VOL_REQ_MASK   (0x1FU)
+#define APU_DVFS_DBG_PATTERN_DATA_VOL_REQ_SHIFT  (0U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_PATTERN_DATA_VOL_REQ(x)     (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_DATA_VOL_REQ_SHIFT)) & APU_DVFS_DBG_PATTERN_DATA_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_PATTERN_DATA_SYS_FREQ_CTRL_MASK (0x1E0U)
+#define APU_DVFS_DBG_PATTERN_DATA_SYS_FREQ_CTRL_SHIFT (5U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_DBG_PATTERN_DATA_SYS_FREQ_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_DATA_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_PATTERN_DATA_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_PATTERN_DATA_CPU2_FREQ_CTRL_MASK (0x1E00U)
+#define APU_DVFS_DBG_PATTERN_DATA_CPU2_FREQ_CTRL_SHIFT (9U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_DBG_PATTERN_DATA_CPU2_FREQ_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_DATA_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_PATTERN_DATA_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_PATTERN_DATA_CPU1_FREQ_CTRL_MASK (0x1E000U)
+#define APU_DVFS_DBG_PATTERN_DATA_CPU1_FREQ_CTRL_SHIFT (13U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_DBG_PATTERN_DATA_CPU1_FREQ_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_DATA_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_PATTERN_DATA_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_PATTERN_DATA_APU_BUCK_LVL_CTRL_MASK (0x3E0000U)
+#define APU_DVFS_DBG_PATTERN_DATA_APU_BUCK_LVL_CTRL_SHIFT (17U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_DBG_PATTERN_DATA_APU_BUCK_LVL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_DATA_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_DBG_PATTERN_DATA_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_DBG_PATTERN_DATA_SW_VOL_REQ_MASK (0x7C00000U)
+#define APU_DVFS_DBG_PATTERN_DATA_SW_VOL_REQ_SHIFT (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_PATTERN_DATA_SW_VOL_REQ(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_DATA_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_PATTERN_DATA_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_PATTERN_DATA_HW_VOL_REQ_MASK (0xF8000000U)
+#define APU_DVFS_DBG_PATTERN_DATA_HW_VOL_REQ_SHIFT (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_PATTERN_DATA_HW_VOL_REQ(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_DATA_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_PATTERN_DATA_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_REG0 - DVFS Debug 0 */
+/*! @{ */
+
+#define APU_DVFS_DBG_REG0_VOL_REQ_MASK           (0x1FU)
+#define APU_DVFS_DBG_REG0_VOL_REQ_SHIFT          (0U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_REG0_VOL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG0_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG0_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG0_SYS_FREQ_CTRL_MASK     (0x1E0U)
+#define APU_DVFS_DBG_REG0_SYS_FREQ_CTRL_SHIFT    (5U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_DBG_REG0_SYS_FREQ_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG0_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG0_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG0_CPU2_FREQ_CTRL_MASK    (0x1E00U)
+#define APU_DVFS_DBG_REG0_CPU2_FREQ_CTRL_SHIFT   (9U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_DBG_REG0_CPU2_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG0_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG0_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG0_CPU1_FREQ_CTRL_MASK    (0x1E000U)
+#define APU_DVFS_DBG_REG0_CPU1_FREQ_CTRL_SHIFT   (13U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_DBG_REG0_CPU1_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG0_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG0_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG0_APU_BUCK_LVL_CTRL_MASK (0x3E0000U)
+#define APU_DVFS_DBG_REG0_APU_BUCK_LVL_CTRL_SHIFT (17U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_DBG_REG0_APU_BUCK_LVL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG0_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_DBG_REG0_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG0_SW_VOL_REQ_MASK        (0x7C00000U)
+#define APU_DVFS_DBG_REG0_SW_VOL_REQ_SHIFT       (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_REG0_SW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG0_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG0_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG0_HW_VOL_REQ_MASK        (0xF8000000U)
+#define APU_DVFS_DBG_REG0_HW_VOL_REQ_SHIFT       (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_REG0_HW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG0_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG0_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_REG1 - DVFS Debug 1 */
+/*! @{ */
+
+#define APU_DVFS_DBG_REG1_VOL_REQ_MASK           (0x1FU)
+#define APU_DVFS_DBG_REG1_VOL_REQ_SHIFT          (0U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_REG1_VOL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG1_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG1_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG1_SYS_FREQ_CTRL_MASK     (0x1E0U)
+#define APU_DVFS_DBG_REG1_SYS_FREQ_CTRL_SHIFT    (5U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_DBG_REG1_SYS_FREQ_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG1_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG1_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG1_CPU2_FREQ_CTRL_MASK    (0x1E00U)
+#define APU_DVFS_DBG_REG1_CPU2_FREQ_CTRL_SHIFT   (9U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_DBG_REG1_CPU2_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG1_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG1_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG1_CPU1_FREQ_CTRL_MASK    (0x1E000U)
+#define APU_DVFS_DBG_REG1_CPU1_FREQ_CTRL_SHIFT   (13U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_DBG_REG1_CPU1_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG1_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG1_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG1_APU_BUCK_LVL_CTRL_MASK (0x3E0000U)
+#define APU_DVFS_DBG_REG1_APU_BUCK_LVL_CTRL_SHIFT (17U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_DBG_REG1_APU_BUCK_LVL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG1_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_DBG_REG1_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG1_SW_VOL_REQ_MASK        (0x7C00000U)
+#define APU_DVFS_DBG_REG1_SW_VOL_REQ_SHIFT       (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_REG1_SW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG1_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG1_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG1_HW_VOL_REQ_MASK        (0xF8000000U)
+#define APU_DVFS_DBG_REG1_HW_VOL_REQ_SHIFT       (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_REG1_HW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG1_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG1_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_REG2 - DVFS Debug 2 */
+/*! @{ */
+
+#define APU_DVFS_DBG_REG2_VOL_REQ_MASK           (0x1FU)
+#define APU_DVFS_DBG_REG2_VOL_REQ_SHIFT          (0U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_REG2_VOL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG2_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG2_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG2_SYS_FREQ_CTRL_MASK     (0x1E0U)
+#define APU_DVFS_DBG_REG2_SYS_FREQ_CTRL_SHIFT    (5U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_DBG_REG2_SYS_FREQ_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG2_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG2_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG2_CPU2_FREQ_CTRL_MASK    (0x1E00U)
+#define APU_DVFS_DBG_REG2_CPU2_FREQ_CTRL_SHIFT   (9U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_DBG_REG2_CPU2_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG2_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG2_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG2_CPU1_FREQ_CTRL_MASK    (0x1E000U)
+#define APU_DVFS_DBG_REG2_CPU1_FREQ_CTRL_SHIFT   (13U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_DBG_REG2_CPU1_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG2_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG2_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG2_APU_BUCK_LVL_CTRL_MASK (0x3E0000U)
+#define APU_DVFS_DBG_REG2_APU_BUCK_LVL_CTRL_SHIFT (17U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_DBG_REG2_APU_BUCK_LVL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG2_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_DBG_REG2_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG2_SW_VOL_REQ_MASK        (0x7C00000U)
+#define APU_DVFS_DBG_REG2_SW_VOL_REQ_SHIFT       (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_REG2_SW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG2_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG2_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG2_HW_VOL_REQ_MASK        (0xF8000000U)
+#define APU_DVFS_DBG_REG2_HW_VOL_REQ_SHIFT       (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_REG2_HW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG2_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG2_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_REG3 - DVFS Debug 3 */
+/*! @{ */
+
+#define APU_DVFS_DBG_REG3_VOL_REQ_MASK           (0x1FU)
+#define APU_DVFS_DBG_REG3_VOL_REQ_SHIFT          (0U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_REG3_VOL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG3_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG3_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG3_SYS_FREQ_CTRL_MASK     (0x1E0U)
+#define APU_DVFS_DBG_REG3_SYS_FREQ_CTRL_SHIFT    (5U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_DBG_REG3_SYS_FREQ_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG3_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG3_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG3_CPU2_FREQ_CTRL_MASK    (0x1E00U)
+#define APU_DVFS_DBG_REG3_CPU2_FREQ_CTRL_SHIFT   (9U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_DBG_REG3_CPU2_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG3_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG3_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG3_CPU1_FREQ_CTRL_MASK    (0x1E000U)
+#define APU_DVFS_DBG_REG3_CPU1_FREQ_CTRL_SHIFT   (13U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_DBG_REG3_CPU1_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG3_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG3_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG3_APU_BUCK_LVL_CTRL_MASK (0x3E0000U)
+#define APU_DVFS_DBG_REG3_APU_BUCK_LVL_CTRL_SHIFT (17U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_DBG_REG3_APU_BUCK_LVL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG3_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_DBG_REG3_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG3_SW_VOL_REQ_MASK        (0x7C00000U)
+#define APU_DVFS_DBG_REG3_SW_VOL_REQ_SHIFT       (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_REG3_SW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG3_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG3_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG3_HW_VOL_REQ_MASK        (0xF8000000U)
+#define APU_DVFS_DBG_REG3_HW_VOL_REQ_SHIFT       (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_REG3_HW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG3_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG3_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_REG4 - DVFS Debug 4 */
+/*! @{ */
+
+#define APU_DVFS_DBG_REG4_VOL_REQ_MASK           (0x1FU)
+#define APU_DVFS_DBG_REG4_VOL_REQ_SHIFT          (0U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_REG4_VOL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG4_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG4_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG4_SYS_FREQ_CTRL_MASK     (0x1E0U)
+#define APU_DVFS_DBG_REG4_SYS_FREQ_CTRL_SHIFT    (5U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_DBG_REG4_SYS_FREQ_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG4_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG4_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG4_CPU2_FREQ_CTRL_MASK    (0x1E00U)
+#define APU_DVFS_DBG_REG4_CPU2_FREQ_CTRL_SHIFT   (9U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_DBG_REG4_CPU2_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG4_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG4_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG4_CPU1_FREQ_CTRL_MASK    (0x1E000U)
+#define APU_DVFS_DBG_REG4_CPU1_FREQ_CTRL_SHIFT   (13U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_DBG_REG4_CPU1_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG4_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG4_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG4_APU_BUCK_LVL_CTRL_MASK (0x3E0000U)
+#define APU_DVFS_DBG_REG4_APU_BUCK_LVL_CTRL_SHIFT (17U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_DBG_REG4_APU_BUCK_LVL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG4_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_DBG_REG4_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG4_SW_VOL_REQ_MASK        (0x7C00000U)
+#define APU_DVFS_DBG_REG4_SW_VOL_REQ_SHIFT       (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_REG4_SW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG4_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG4_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG4_HW_VOL_REQ_MASK        (0xF8000000U)
+#define APU_DVFS_DBG_REG4_HW_VOL_REQ_SHIFT       (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_REG4_HW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG4_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG4_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_REG5 - DVFS Debug 5 */
+/*! @{ */
+
+#define APU_DVFS_DBG_REG5_VOL_REQ_MASK           (0x1FU)
+#define APU_DVFS_DBG_REG5_VOL_REQ_SHIFT          (0U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_REG5_VOL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG5_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG5_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG5_SYS_FREQ_CTRL_MASK     (0x1E0U)
+#define APU_DVFS_DBG_REG5_SYS_FREQ_CTRL_SHIFT    (5U)
+/*! SYS_FREQ_CTRL - System Frequency Control */
+#define APU_DVFS_DBG_REG5_SYS_FREQ_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG5_SYS_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG5_SYS_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG5_CPU2_FREQ_CTRL_MASK    (0x1E00U)
+#define APU_DVFS_DBG_REG5_CPU2_FREQ_CTRL_SHIFT   (9U)
+/*! CPU2_FREQ_CTRL - CPU2 Frequency Control */
+#define APU_DVFS_DBG_REG5_CPU2_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG5_CPU2_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG5_CPU2_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG5_CPU1_FREQ_CTRL_MASK    (0x1E000U)
+#define APU_DVFS_DBG_REG5_CPU1_FREQ_CTRL_SHIFT   (13U)
+/*! CPU1_FREQ_CTRL - CPU1 Frequency Control */
+#define APU_DVFS_DBG_REG5_CPU1_FREQ_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG5_CPU1_FREQ_CTRL_SHIFT)) & APU_DVFS_DBG_REG5_CPU1_FREQ_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG5_APU_BUCK_LVL_CTRL_MASK (0x3E0000U)
+#define APU_DVFS_DBG_REG5_APU_BUCK_LVL_CTRL_SHIFT (17U)
+/*! APU_BUCK_LVL_CTRL - APU BUCK Level Control */
+#define APU_DVFS_DBG_REG5_APU_BUCK_LVL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG5_APU_BUCK_LVL_CTRL_SHIFT)) & APU_DVFS_DBG_REG5_APU_BUCK_LVL_CTRL_MASK)
+
+#define APU_DVFS_DBG_REG5_SW_VOL_REQ_MASK        (0x7C00000U)
+#define APU_DVFS_DBG_REG5_SW_VOL_REQ_SHIFT       (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_REG5_SW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG5_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG5_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_REG5_HW_VOL_REQ_MASK        (0xF8000000U)
+#define APU_DVFS_DBG_REG5_HW_VOL_REQ_SHIFT       (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_REG5_HW_VOL_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_REG5_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_REG5_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_STATUS - DVFS Debug Status */
+/*! @{ */
+
+#define APU_DVFS_DBG_STATUS_DVFS_DBG_LOG_DONE_MASK (0x1U)
+#define APU_DVFS_DBG_STATUS_DVFS_DBG_LOG_DONE_SHIFT (0U)
+/*! DVFS_DBG_LOG_DONE - DVFS Debug Log Done */
+#define APU_DVFS_DBG_STATUS_DVFS_DBG_LOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_DVFS_DBG_LOG_DONE_SHIFT)) & APU_DVFS_DBG_STATUS_DVFS_DBG_LOG_DONE_MASK)
+
+#define APU_DVFS_DBG_STATUS_BUCK_LVL_REACHED_MASK (0x3EU)
+#define APU_DVFS_DBG_STATUS_BUCK_LVL_REACHED_SHIFT (1U)
+/*! BUCK_LVL_REACHED - voltage corresponding to PMIC code 0x2 */
+#define APU_DVFS_DBG_STATUS_BUCK_LVL_REACHED(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_BUCK_LVL_REACHED_SHIFT)) & APU_DVFS_DBG_STATUS_BUCK_LVL_REACHED_MASK)
+
+#define APU_DVFS_DBG_STATUS_KEEP_DVFS_LVL_ACTIVE_MASK (0x40U)
+#define APU_DVFS_DBG_STATUS_KEEP_DVFS_LVL_ACTIVE_SHIFT (6U)
+/*! KEEP_DVFS_LVL_ACTIVE - Keep DVFS Level Active */
+#define APU_DVFS_DBG_STATUS_KEEP_DVFS_LVL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_KEEP_DVFS_LVL_ACTIVE_SHIFT)) & APU_DVFS_DBG_STATUS_KEEP_DVFS_LVL_ACTIVE_MASK)
+
+#define APU_DVFS_DBG_STATUS_RESET_COUNTER_SYNCED_MASK (0x80U)
+#define APU_DVFS_DBG_STATUS_RESET_COUNTER_SYNCED_SHIFT (7U)
+/*! RESET_COUNTER_SYNCED - voltage corresponding to PMIC code 0x3 */
+#define APU_DVFS_DBG_STATUS_RESET_COUNTER_SYNCED(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_RESET_COUNTER_SYNCED_SHIFT)) & APU_DVFS_DBG_STATUS_RESET_COUNTER_SYNCED_MASK)
+
+#define APU_DVFS_DBG_STATUS_SW_LOCK_GAURD_EN_MASK (0x100U)
+#define APU_DVFS_DBG_STATUS_SW_LOCK_GAURD_EN_SHIFT (8U)
+/*! SW_LOCK_GAURD_EN - SW Lock Guard Enable */
+#define APU_DVFS_DBG_STATUS_SW_LOCK_GAURD_EN(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_SW_LOCK_GAURD_EN_SHIFT)) & APU_DVFS_DBG_STATUS_SW_LOCK_GAURD_EN_MASK)
+
+#define APU_DVFS_DBG_STATUS_DVFS_CLK_SEL_DVFSCK_MASK (0x200U)
+#define APU_DVFS_DBG_STATUS_DVFS_CLK_SEL_DVFSCK_SHIFT (9U)
+/*! DVFS_CLK_SEL_DVFSCK - DVFS Clock Select DVFSCK */
+#define APU_DVFS_DBG_STATUS_DVFS_CLK_SEL_DVFSCK(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_DVFS_CLK_SEL_DVFSCK_SHIFT)) & APU_DVFS_DBG_STATUS_DVFS_CLK_SEL_DVFSCK_MASK)
+
+#define APU_DVFS_DBG_STATUS_EAS_SEL_MASK         (0x400U)
+#define APU_DVFS_DBG_STATUS_EAS_SEL_SHIFT        (10U)
+/*! EAS_SEL - EAS Select */
+#define APU_DVFS_DBG_STATUS_EAS_SEL(x)           (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_EAS_SEL_SHIFT)) & APU_DVFS_DBG_STATUS_EAS_SEL_MASK)
+
+#define APU_DVFS_DBG_STATUS_SW_FREQ_GAURD_EN_MASK (0x800U)
+#define APU_DVFS_DBG_STATUS_SW_FREQ_GAURD_EN_SHIFT (11U)
+/*! SW_FREQ_GAURD_EN - SW Frequency Guard Enable */
+#define APU_DVFS_DBG_STATUS_SW_FREQ_GAURD_EN(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_SW_FREQ_GAURD_EN_SHIFT)) & APU_DVFS_DBG_STATUS_SW_FREQ_GAURD_EN_MASK)
+
+#define APU_DVFS_DBG_STATUS_PMIC_TIMER_DONE_REG_MASK (0x1000U)
+#define APU_DVFS_DBG_STATUS_PMIC_TIMER_DONE_REG_SHIFT (12U)
+/*! PMIC_TIMER_DONE_REG - PMIC Timer Done */
+#define APU_DVFS_DBG_STATUS_PMIC_TIMER_DONE_REG(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_PMIC_TIMER_DONE_REG_SHIFT)) & APU_DVFS_DBG_STATUS_PMIC_TIMER_DONE_REG_MASK)
+
+#define APU_DVFS_DBG_STATUS_WLAN_VOL_LVL_REACHED_MASK (0x8000U)
+#define APU_DVFS_DBG_STATUS_WLAN_VOL_LVL_REACHED_SHIFT (15U)
+/*! WLAN_VOL_LVL_REACHED - WLAN Vol Level Reached */
+#define APU_DVFS_DBG_STATUS_WLAN_VOL_LVL_REACHED(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_WLAN_VOL_LVL_REACHED_SHIFT)) & APU_DVFS_DBG_STATUS_WLAN_VOL_LVL_REACHED_MASK)
+
+#define APU_DVFS_DBG_STATUS_NFC_VOL_LVL_REACHED_MASK (0x10000U)
+#define APU_DVFS_DBG_STATUS_NFC_VOL_LVL_REACHED_SHIFT (16U)
+/*! NFC_VOL_LVL_REACHED - NFC Vol Level Reached */
+#define APU_DVFS_DBG_STATUS_NFC_VOL_LVL_REACHED(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_NFC_VOL_LVL_REACHED_SHIFT)) & APU_DVFS_DBG_STATUS_NFC_VOL_LVL_REACHED_MASK)
+
+#define APU_DVFS_DBG_STATUS_NOM_VOL_LVL_REACHED_MASK (0x20000U)
+#define APU_DVFS_DBG_STATUS_NOM_VOL_LVL_REACHED_SHIFT (17U)
+/*! NOM_VOL_LVL_REACHED - Nominal Vol Level Reached */
+#define APU_DVFS_DBG_STATUS_NOM_VOL_LVL_REACHED(x) (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_NOM_VOL_LVL_REACHED_SHIFT)) & APU_DVFS_DBG_STATUS_NOM_VOL_LVL_REACHED_MASK)
+
+#define APU_DVFS_DBG_STATUS_VOL_REQ_MASK         (0x3C0000U)
+#define APU_DVFS_DBG_STATUS_VOL_REQ_SHIFT        (18U)
+/*! VOL_REQ - Vol Request */
+#define APU_DVFS_DBG_STATUS_VOL_REQ(x)           (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_VOL_REQ_SHIFT)) & APU_DVFS_DBG_STATUS_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_STATUS_SW_VOL_REQ_MASK      (0x7C00000U)
+#define APU_DVFS_DBG_STATUS_SW_VOL_REQ_SHIFT     (22U)
+/*! SW_VOL_REQ - SW Vol Request */
+#define APU_DVFS_DBG_STATUS_SW_VOL_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_SW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_STATUS_SW_VOL_REQ_MASK)
+
+#define APU_DVFS_DBG_STATUS_HW_VOL_REQ_MASK      (0xF8000000U)
+#define APU_DVFS_DBG_STATUS_HW_VOL_REQ_SHIFT     (27U)
+/*! HW_VOL_REQ - HW Vol Request */
+#define APU_DVFS_DBG_STATUS_HW_VOL_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_STATUS_HW_VOL_REQ_SHIFT)) & APU_DVFS_DBG_STATUS_HW_VOL_REQ_MASK)
+/*! @} */
+
+/*! @name DVFS_DBG_PATTERN_MASK - DVFS Debug Patter Mask */
+/*! @{ */
+
+#define APU_DVFS_DBG_PATTERN_MASK_MASK_MASK      (0xFFFFFFFFU)
+#define APU_DVFS_DBG_PATTERN_MASK_MASK_SHIFT     (0U)
+/*! MASK - Mask to Delay */
+#define APU_DVFS_DBG_PATTERN_MASK_MASK(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_DBG_PATTERN_MASK_MASK_SHIFT)) & APU_DVFS_DBG_PATTERN_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name DVFS_PMIC_TIMER - DVFS PMIC Timer */
+/*! @{ */
+
+#define APU_DVFS_PMIC_TIMER_REF_CNT_MASK         (0xFFFFU)
+#define APU_DVFS_PMIC_TIMER_REF_CNT_SHIFT        (0U)
+/*! REF_CNT - Reference Count */
+#define APU_DVFS_PMIC_TIMER_REF_CNT(x)           (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_TIMER_REF_CNT_SHIFT)) & APU_DVFS_PMIC_TIMER_REF_CNT_MASK)
+
+#define APU_DVFS_PMIC_TIMER_SLP_CNT_MASK         (0xF0000U)
+#define APU_DVFS_PMIC_TIMER_SLP_CNT_SHIFT        (16U)
+/*! SLP_CNT - Sleep Counts */
+#define APU_DVFS_PMIC_TIMER_SLP_CNT(x)           (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_TIMER_SLP_CNT_SHIFT)) & APU_DVFS_PMIC_TIMER_SLP_CNT_MASK)
+
+#define APU_DVFS_PMIC_TIMER_ACTIVE_CNT_MASK      (0xFFF00000U)
+#define APU_DVFS_PMIC_TIMER_ACTIVE_CNT_SHIFT     (20U)
+/*! ACTIVE_CNT - Active Count */
+#define APU_DVFS_PMIC_TIMER_ACTIVE_CNT(x)        (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_TIMER_ACTIVE_CNT_SHIFT)) & APU_DVFS_PMIC_TIMER_ACTIVE_CNT_MASK)
+/*! @} */
+
+/*! @name DVFS_PMIC_MAP - DVFS PMIC Map */
+/*! @{ */
+
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC0_MASK (0x7FU)
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC0_SHIFT (0U)
+/*! DVFS_VOL_FOR_PMIC0 - DVFS Vol for PMIC 0 */
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC0(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC0_SHIFT)) & APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC0_MASK)
+
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC1_MASK (0x7F00U)
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC1_SHIFT (8U)
+/*! DVFS_VOL_FOR_PMIC1 - DVFS Vol for PMIC 1 */
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC1(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC1_SHIFT)) & APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC1_MASK)
+
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC2_MASK (0x7F0000U)
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC2_SHIFT (16U)
+/*! DVFS_VOL_FOR_PMIC2 - DVFS Vol for PMIC 2 */
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC2(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC2_SHIFT)) & APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC2_MASK)
+
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC3_MASK (0x7F000000U)
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC3_SHIFT (24U)
+/*! DVFS_VOL_FOR_PMIC3 - DVFS Vol for PMIC 3 */
+#define APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC3(x)  (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC3_SHIFT)) & APU_DVFS_PMIC_MAP_DVFS_VOL_FOR_PMIC3_MASK)
+
+#define APU_DVFS_PMIC_MAP_USE_PMIC_TIMER_MASK    (0x80000000U)
+#define APU_DVFS_PMIC_MAP_USE_PMIC_TIMER_SHIFT   (31U)
+/*! USE_PMIC_TIMER - Use PMIC Timer */
+#define APU_DVFS_PMIC_MAP_USE_PMIC_TIMER(x)      (((uint32_t)(((uint32_t)(x)) << APU_DVFS_PMIC_MAP_USE_PMIC_TIMER_SHIFT)) & APU_DVFS_PMIC_MAP_USE_PMIC_TIMER_MASK)
+/*! @} */
+
+/*! @name LDO_CTRL - LDO Control */
+/*! @{ */
+
+#define APU_LDO_CTRL_MAIN_DELAY_CNT_EN_MASK      (0x1U)
+#define APU_LDO_CTRL_MAIN_DELAY_CNT_EN_SHIFT     (0U)
+/*! MAIN_DELAY_CNT_EN - Main Delay Count Enable */
+#define APU_LDO_CTRL_MAIN_DELAY_CNT_EN(x)        (((uint32_t)(((uint32_t)(x)) << APU_LDO_CTRL_MAIN_DELAY_CNT_EN_SHIFT)) & APU_LDO_CTRL_MAIN_DELAY_CNT_EN_MASK)
+
+#define APU_LDO_CTRL_BACKUP_DELAY_CNT_EN_MASK    (0x2U)
+#define APU_LDO_CTRL_BACKUP_DELAY_CNT_EN_SHIFT   (1U)
+/*! BACKUP_DELAY_CNT_EN - Backup Delay Count Enable */
+#define APU_LDO_CTRL_BACKUP_DELAY_CNT_EN(x)      (((uint32_t)(((uint32_t)(x)) << APU_LDO_CTRL_BACKUP_DELAY_CNT_EN_SHIFT)) & APU_LDO_CTRL_BACKUP_DELAY_CNT_EN_MASK)
+
+#define APU_LDO_CTRL_MAIN_DELAY_COUNTER_VAL_MASK (0x30U)
+#define APU_LDO_CTRL_MAIN_DELAY_COUNTER_VAL_SHIFT (4U)
+/*! MAIN_DELAY_COUNTER_VAL - Main Delay Counter Value */
+#define APU_LDO_CTRL_MAIN_DELAY_COUNTER_VAL(x)   (((uint32_t)(((uint32_t)(x)) << APU_LDO_CTRL_MAIN_DELAY_COUNTER_VAL_SHIFT)) & APU_LDO_CTRL_MAIN_DELAY_COUNTER_VAL_MASK)
+
+#define APU_LDO_CTRL_BACKUP_DELAY_COUNTER_VAL_MASK (0xFF00U)
+#define APU_LDO_CTRL_BACKUP_DELAY_COUNTER_VAL_SHIFT (8U)
+/*! BACKUP_DELAY_COUNTER_VAL - Backup Delay Counter Value */
+#define APU_LDO_CTRL_BACKUP_DELAY_COUNTER_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_LDO_CTRL_BACKUP_DELAY_COUNTER_VAL_SHIFT)) & APU_LDO_CTRL_BACKUP_DELAY_COUNTER_VAL_MASK)
+
+#define APU_LDO_CTRL_USE_XOSC_EN_AS_SEL_MASK     (0x40000000U)
+#define APU_LDO_CTRL_USE_XOSC_EN_AS_SEL_SHIFT    (30U)
+/*! USE_XOSC_EN_AS_SEL - Use XOSC Enable as Select */
+#define APU_LDO_CTRL_USE_XOSC_EN_AS_SEL(x)       (((uint32_t)(((uint32_t)(x)) << APU_LDO_CTRL_USE_XOSC_EN_AS_SEL_SHIFT)) & APU_LDO_CTRL_USE_XOSC_EN_AS_SEL_MASK)
+
+#define APU_LDO_CTRL_KEEP_LDO_MAIN_WHILE_SLP_MASK (0x80000000U)
+#define APU_LDO_CTRL_KEEP_LDO_MAIN_WHILE_SLP_SHIFT (31U)
+/*! KEEP_LDO_MAIN_WHILE_SLP - Keep LDO Main While Sleep */
+#define APU_LDO_CTRL_KEEP_LDO_MAIN_WHILE_SLP(x)  (((uint32_t)(((uint32_t)(x)) << APU_LDO_CTRL_KEEP_LDO_MAIN_WHILE_SLP_SHIFT)) & APU_LDO_CTRL_KEEP_LDO_MAIN_WHILE_SLP_MASK)
+/*! @} */
+
+/*! @name LDO_BACKUP_LVL_MAP1 - LDO Backup Level Map 1 */
+/*! @{ */
+
+#define APU_LDO_BACKUP_LVL_MAP1_LDO_BACKUP_LVL_MAP1_MASK (0xFFFFFFFFU)
+#define APU_LDO_BACKUP_LVL_MAP1_LDO_BACKUP_LVL_MAP1_SHIFT (0U)
+/*! LDO_BACKUP_LVL_MAP1 - LDO Backup Level Map 1 */
+#define APU_LDO_BACKUP_LVL_MAP1_LDO_BACKUP_LVL_MAP1(x) (((uint32_t)(((uint32_t)(x)) << APU_LDO_BACKUP_LVL_MAP1_LDO_BACKUP_LVL_MAP1_SHIFT)) & APU_LDO_BACKUP_LVL_MAP1_LDO_BACKUP_LVL_MAP1_MASK)
+/*! @} */
+
+/*! @name LDO_BACKUP_LVL_MAP2 - LDO Backup Level Map 2 */
+/*! @{ */
+
+#define APU_LDO_BACKUP_LVL_MAP2_LDO_BACKUP_LVL_MAP2_MASK (0xFFFFFFFFU)
+#define APU_LDO_BACKUP_LVL_MAP2_LDO_BACKUP_LVL_MAP2_SHIFT (0U)
+/*! LDO_BACKUP_LVL_MAP2 - LDO Backup Level Map 2 */
+#define APU_LDO_BACKUP_LVL_MAP2_LDO_BACKUP_LVL_MAP2(x) (((uint32_t)(((uint32_t)(x)) << APU_LDO_BACKUP_LVL_MAP2_LDO_BACKUP_LVL_MAP2_SHIFT)) & APU_LDO_BACKUP_LVL_MAP2_LDO_BACKUP_LVL_MAP2_MASK)
+/*! @} */
+
+/*! @name LDO_STATUS - LDO Status */
+/*! @{ */
+
+#define APU_LDO_STATUS_LDO_BACKUP_LVL_MASK       (0x7U)
+#define APU_LDO_STATUS_LDO_BACKUP_LVL_SHIFT      (0U)
+/*! LDO_BACKUP_LVL - LDO Backup Level */
+#define APU_LDO_STATUS_LDO_BACKUP_LVL(x)         (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_LDO_BACKUP_LVL_SHIFT)) & APU_LDO_STATUS_LDO_BACKUP_LVL_MASK)
+
+#define APU_LDO_STATUS_LDO_MAIN_LVL_MASK         (0xF0U)
+#define APU_LDO_STATUS_LDO_MAIN_LVL_SHIFT        (4U)
+/*! LDO_MAIN_LVL - LDO Main Level */
+#define APU_LDO_STATUS_LDO_MAIN_LVL(x)           (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_LDO_MAIN_LVL_SHIFT)) & APU_LDO_STATUS_LDO_MAIN_LVL_MASK)
+
+#define APU_LDO_STATUS_MAIN_PD_DELAY_CNT_MASK    (0x300U)
+#define APU_LDO_STATUS_MAIN_PD_DELAY_CNT_SHIFT   (8U)
+/*! MAIN_PD_DELAY_CNT - Main Powerdown Delay Count */
+#define APU_LDO_STATUS_MAIN_PD_DELAY_CNT(x)      (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_MAIN_PD_DELAY_CNT_SHIFT)) & APU_LDO_STATUS_MAIN_PD_DELAY_CNT_MASK)
+
+#define APU_LDO_STATUS_MAIN_PD_DELAY_CNT_MET_MASK (0x400U)
+#define APU_LDO_STATUS_MAIN_PD_DELAY_CNT_MET_SHIFT (10U)
+/*! MAIN_PD_DELAY_CNT_MET - Main Powerdown Delay Count Met */
+#define APU_LDO_STATUS_MAIN_PD_DELAY_CNT_MET(x)  (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_MAIN_PD_DELAY_CNT_MET_SHIFT)) & APU_LDO_STATUS_MAIN_PD_DELAY_CNT_MET_MASK)
+
+#define APU_LDO_STATUS_LDO_MAIN_PD_MASK          (0x800U)
+#define APU_LDO_STATUS_LDO_MAIN_PD_SHIFT         (11U)
+/*! LDO_MAIN_PD - LDO Main Powerdown */
+#define APU_LDO_STATUS_LDO_MAIN_PD(x)            (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_LDO_MAIN_PD_SHIFT)) & APU_LDO_STATUS_LDO_MAIN_PD_MASK)
+
+#define APU_LDO_STATUS_ACTIVE_SEL_MASK           (0x1000U)
+#define APU_LDO_STATUS_ACTIVE_SEL_SHIFT          (12U)
+/*! ACTIVE_SEL - Active Select */
+#define APU_LDO_STATUS_ACTIVE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_ACTIVE_SEL_SHIFT)) & APU_LDO_STATUS_ACTIVE_SEL_MASK)
+
+#define APU_LDO_STATUS_BACK_DELAY_CNT_MET_MASK   (0x2000U)
+#define APU_LDO_STATUS_BACK_DELAY_CNT_MET_SHIFT  (13U)
+/*! BACK_DELAY_CNT_MET - Back Delay Count Met */
+#define APU_LDO_STATUS_BACK_DELAY_CNT_MET(x)     (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_BACK_DELAY_CNT_MET_SHIFT)) & APU_LDO_STATUS_BACK_DELAY_CNT_MET_MASK)
+
+#define APU_LDO_STATUS_D_LDO_BACKUP_EN_MASK      (0x4000U)
+#define APU_LDO_STATUS_D_LDO_BACKUP_EN_SHIFT     (14U)
+/*! D_LDO_BACKUP_EN - D LDO Backup Enable */
+#define APU_LDO_STATUS_D_LDO_BACKUP_EN(x)        (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_D_LDO_BACKUP_EN_SHIFT)) & APU_LDO_STATUS_D_LDO_BACKUP_EN_MASK)
+
+#define APU_LDO_STATUS_LDO_BACKUP_EN_MASK        (0x8000U)
+#define APU_LDO_STATUS_LDO_BACKUP_EN_SHIFT       (15U)
+/*! LDO_BACKUP_EN - LDO Backup Enable */
+#define APU_LDO_STATUS_LDO_BACKUP_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_LDO_BACKUP_EN_SHIFT)) & APU_LDO_STATUS_LDO_BACKUP_EN_MASK)
+
+#define APU_LDO_STATUS_BACKUP_DELAY_CNT_MASK     (0xFF0000U)
+#define APU_LDO_STATUS_BACKUP_DELAY_CNT_SHIFT    (16U)
+/*! BACKUP_DELAY_CNT - Backup Delay Count (to check testbus) */
+#define APU_LDO_STATUS_BACKUP_DELAY_CNT(x)       (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_BACKUP_DELAY_CNT_SHIFT)) & APU_LDO_STATUS_BACKUP_DELAY_CNT_MASK)
+
+#define APU_LDO_STATUS_BKUP_LVL2_SEL_MASK        (0x1000000U)
+#define APU_LDO_STATUS_BKUP_LVL2_SEL_SHIFT       (24U)
+/*! BKUP_LVL2_SEL - Backup Level 2 Select */
+#define APU_LDO_STATUS_BKUP_LVL2_SEL(x)          (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_BKUP_LVL2_SEL_SHIFT)) & APU_LDO_STATUS_BKUP_LVL2_SEL_MASK)
+
+#define APU_LDO_STATUS_BKUP_LVL1_SEL_MASK        (0x2000000U)
+#define APU_LDO_STATUS_BKUP_LVL1_SEL_SHIFT       (25U)
+/*! BKUP_LVL1_SEL - Backup Level 1 Select */
+#define APU_LDO_STATUS_BKUP_LVL1_SEL(x)          (((uint32_t)(((uint32_t)(x)) << APU_LDO_STATUS_BKUP_LVL1_SEL_SHIFT)) & APU_LDO_STATUS_BKUP_LVL1_SEL_MASK)
+/*! @} */
+
+/*! @name RC32_CAL_CTRL - RC32 Calibration Control */
+/*! @{ */
+
+#define APU_RC32_CAL_CTRL_RC32_FULL_CAL_EN_MASK  (0x1U)
+#define APU_RC32_CAL_CTRL_RC32_FULL_CAL_EN_SHIFT (0U)
+/*! RC32_FULL_CAL_EN - RC32 Full Calibration Enable */
+#define APU_RC32_CAL_CTRL_RC32_FULL_CAL_EN(x)    (((uint32_t)(((uint32_t)(x)) << APU_RC32_CAL_CTRL_RC32_FULL_CAL_EN_SHIFT)) & APU_RC32_CAL_CTRL_RC32_FULL_CAL_EN_MASK)
+
+#define APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_MASK (0x2U)
+#define APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_SHIFT (1U)
+/*! RC32_PARTIAL_CAL_EN - RC32 Partial Calibration Enable */
+#define APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_SHIFT)) & APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_MASK)
+
+#define APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_ON_BT_WKUP_MASK (0x4U)
+#define APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_ON_BT_WKUP_SHIFT (2U)
+/*! RC32_PARTIAL_CAL_EN_ON_BT_WKUP - RC32 Partial Calibration Enable on Bluetooth Wakeup */
+#define APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_ON_BT_WKUP(x) (((uint32_t)(((uint32_t)(x)) << APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_ON_BT_WKUP_SHIFT)) & APU_RC32_CAL_CTRL_RC32_PARTIAL_CAL_EN_ON_BT_WKUP_MASK)
+
+#define APU_RC32_CAL_CTRL_USE_RC32_CAL_DONE_MASK (0x8U)
+#define APU_RC32_CAL_CTRL_USE_RC32_CAL_DONE_SHIFT (3U)
+/*! USE_RC32_CAL_DONE - Use RC32 Calibration Done */
+#define APU_RC32_CAL_CTRL_USE_RC32_CAL_DONE(x)   (((uint32_t)(((uint32_t)(x)) << APU_RC32_CAL_CTRL_USE_RC32_CAL_DONE_SHIFT)) & APU_RC32_CAL_CTRL_USE_RC32_CAL_DONE_MASK)
+
+#define APU_RC32_CAL_CTRL_RC32_CAL_VOL_VAL_MASK  (0x7F0U)
+#define APU_RC32_CAL_CTRL_RC32_CAL_VOL_VAL_SHIFT (4U)
+/*! RC32_CAL_VOL_VAL - RC32 Calibration Vol Value */
+#define APU_RC32_CAL_CTRL_RC32_CAL_VOL_VAL(x)    (((uint32_t)(((uint32_t)(x)) << APU_RC32_CAL_CTRL_RC32_CAL_VOL_VAL_SHIFT)) & APU_RC32_CAL_CTRL_RC32_CAL_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name RC32_CAL_SLPCLK_TIMER - RC32 Calibration Sleep Clock Timer */
+/*! @{ */
+
+#define APU_RC32_CAL_SLPCLK_TIMER_RC32_CAL_SLPCLK_TIMER_MASK (0xFFFFFFFFU)
+#define APU_RC32_CAL_SLPCLK_TIMER_RC32_CAL_SLPCLK_TIMER_SHIFT (0U)
+/*! RC32_CAL_SLPCLK_TIMER - RC32 Calibration Sleep Clock Timer */
+#define APU_RC32_CAL_SLPCLK_TIMER_RC32_CAL_SLPCLK_TIMER(x) (((uint32_t)(((uint32_t)(x)) << APU_RC32_CAL_SLPCLK_TIMER_RC32_CAL_SLPCLK_TIMER_SHIFT)) & APU_RC32_CAL_SLPCLK_TIMER_RC32_CAL_SLPCLK_TIMER_MASK)
+/*! @} */
+
+/*! @name RC32CAL_SLPCLK_CNT_RD - RC32 Calibration Sleep Clock Count Read */
+/*! @{ */
+
+#define APU_RC32CAL_SLPCLK_CNT_RD_RC32CAL_SLPCLK_CNT_RD_MASK (0xFFFFFFFFU)
+#define APU_RC32CAL_SLPCLK_CNT_RD_RC32CAL_SLPCLK_CNT_RD_SHIFT (0U)
+/*! RC32CAL_SLPCLK_CNT_RD - RC32 Calibration Sleep Clock Count Read */
+#define APU_RC32CAL_SLPCLK_CNT_RD_RC32CAL_SLPCLK_CNT_RD(x) (((uint32_t)(((uint32_t)(x)) << APU_RC32CAL_SLPCLK_CNT_RD_RC32CAL_SLPCLK_CNT_RD_SHIFT)) & APU_RC32CAL_SLPCLK_CNT_RD_RC32CAL_SLPCLK_CNT_RD_MASK)
+/*! @} */
+
+/*! @name TSTBUS_DATA - Testbus Data */
+/*! @{ */
+
+#define APU_TSTBUS_DATA_TSTBUS_DATA_MASK         (0xFFFFFFFFU)
+#define APU_TSTBUS_DATA_TSTBUS_DATA_SHIFT        (0U)
+/*! TSTBUS_DATA - Testbus Data */
+#define APU_TSTBUS_DATA_TSTBUS_DATA(x)           (((uint32_t)(((uint32_t)(x)) << APU_TSTBUS_DATA_TSTBUS_DATA_SHIFT)) & APU_TSTBUS_DATA_TSTBUS_DATA_MASK)
+/*! @} */
+
+/*! @name TST_CTRL - Test Control */
+/*! @{ */
+
+#define APU_TST_CTRL_BT_BLE_TST_CTRL_MASK        (0x1U)
+#define APU_TST_CTRL_BT_BLE_TST_CTRL_SHIFT       (0U)
+/*! BT_BLE_TST_CTRL - Bluetooth BLE Test Control */
+#define APU_TST_CTRL_BT_BLE_TST_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_BT_BLE_TST_CTRL_SHIFT)) & APU_TST_CTRL_BT_BLE_TST_CTRL_MASK)
+
+#define APU_TST_CTRL_FM_TST_CTRL_MASK            (0x2U)
+#define APU_TST_CTRL_FM_TST_CTRL_SHIFT           (1U)
+/*! FM_TST_CTRL - FM Test Control */
+#define APU_TST_CTRL_FM_TST_CTRL(x)              (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_FM_TST_CTRL_SHIFT)) & APU_TST_CTRL_FM_TST_CTRL_MASK)
+
+#define APU_TST_CTRL_NFC_TST_CTRL_MASK           (0x4U)
+#define APU_TST_CTRL_NFC_TST_CTRL_SHIFT          (2U)
+/*! NFC_TST_CTRL - NFC Test Control */
+#define APU_TST_CTRL_NFC_TST_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_NFC_TST_CTRL_SHIFT)) & APU_TST_CTRL_NFC_TST_CTRL_MASK)
+
+#define APU_TST_CTRL_CPU2_CP15_SLP_CTRL_MASK     (0x8U)
+#define APU_TST_CTRL_CPU2_CP15_SLP_CTRL_SHIFT    (3U)
+/*! CPU2_CP15_SLP_CTRL - CPU2 CP15 Sleep Control */
+#define APU_TST_CTRL_CPU2_CP15_SLP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_CPU2_CP15_SLP_CTRL_SHIFT)) & APU_TST_CTRL_CPU2_CP15_SLP_CTRL_MASK)
+
+#define APU_TST_CTRL_WLAN_TST_CTRL_MASK          (0x10U)
+#define APU_TST_CTRL_WLAN_TST_CTRL_SHIFT         (4U)
+/*! WLAN_TST_CTRL - WLAN Test Control */
+#define APU_TST_CTRL_WLAN_TST_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_WLAN_TST_CTRL_SHIFT)) & APU_TST_CTRL_WLAN_TST_CTRL_MASK)
+
+#define APU_TST_CTRL_CPU1_CP15_SLP_CTRL_MASK     (0x20U)
+#define APU_TST_CTRL_CPU1_CP15_SLP_CTRL_SHIFT    (5U)
+/*! CPU1_CP15_SLP_CTRL - CPU1 CP15 Sleep Control */
+#define APU_TST_CTRL_CPU1_CP15_SLP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_CPU1_CP15_SLP_CTRL_SHIFT)) & APU_TST_CTRL_CPU1_CP15_SLP_CTRL_MASK)
+
+#define APU_TST_CTRL_CPU2_HOST_TST_CTRL_MASK     (0xF80U)
+#define APU_TST_CTRL_CPU2_HOST_TST_CTRL_SHIFT    (7U)
+/*! CPU2_HOST_TST_CTRL - CPU2 Host Test Control */
+#define APU_TST_CTRL_CPU2_HOST_TST_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_CPU2_HOST_TST_CTRL_SHIFT)) & APU_TST_CTRL_CPU2_HOST_TST_CTRL_MASK)
+
+#define APU_TST_CTRL_TEST_MUX_SEL_SHIFT_BIT_MASK (0xF000U)
+#define APU_TST_CTRL_TEST_MUX_SEL_SHIFT_BIT_SHIFT (12U)
+/*! TEST_MUX_SEL_SHIFT_BIT - Test MUX Select Shift */
+#define APU_TST_CTRL_TEST_MUX_SEL_SHIFT_BIT(x)   (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_TEST_MUX_SEL_SHIFT_BIT_SHIFT)) & APU_TST_CTRL_TEST_MUX_SEL_SHIFT_BIT_MASK)
+
+#define APU_TST_CTRL_APU_TESTBUS_SEL_MASK        (0x1F0000U)
+#define APU_TST_CTRL_APU_TESTBUS_SEL_SHIFT       (16U)
+/*! APU_TESTBUS_SEL - APU Testbus Select */
+#define APU_TST_CTRL_APU_TESTBUS_SEL(x)          (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_APU_TESTBUS_SEL_SHIFT)) & APU_TST_CTRL_APU_TESTBUS_SEL_MASK)
+
+#define APU_TST_CTRL_APU_REG_SUBTEST_SEL_MASK    (0x600000U)
+#define APU_TST_CTRL_APU_REG_SUBTEST_SEL_SHIFT   (21U)
+/*! APU_REG_SUBTEST_SEL - APU Reg Subtest Select */
+#define APU_TST_CTRL_APU_REG_SUBTEST_SEL(x)      (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_APU_REG_SUBTEST_SEL_SHIFT)) & APU_TST_CTRL_APU_REG_SUBTEST_SEL_MASK)
+
+#define APU_TST_CTRL_USE_SOC_APU_SUBTEST_MASK    (0x800000U)
+#define APU_TST_CTRL_USE_SOC_APU_SUBTEST_SHIFT   (23U)
+/*! USE_SOC_APU_SUBTEST - Use SoC APU Subtest */
+#define APU_TST_CTRL_USE_SOC_APU_SUBTEST(x)      (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_USE_SOC_APU_SUBTEST_SHIFT)) & APU_TST_CTRL_USE_SOC_APU_SUBTEST_MASK)
+
+#define APU_TST_CTRL_HOST_TST_CTRL_MASK          (0x3000000U)
+#define APU_TST_CTRL_HOST_TST_CTRL_SHIFT         (24U)
+/*! HOST_TST_CTRL - Host Test Control */
+#define APU_TST_CTRL_HOST_TST_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_HOST_TST_CTRL_SHIFT)) & APU_TST_CTRL_HOST_TST_CTRL_MASK)
+
+#define APU_TST_CTRL_CPU1_HOST_TST_CTRL_MASK     (0x70000000U)
+#define APU_TST_CTRL_CPU1_HOST_TST_CTRL_SHIFT    (28U)
+/*! CPU1_HOST_TST_CTRL - CPU1 Host Test Control */
+#define APU_TST_CTRL_CPU1_HOST_TST_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << APU_TST_CTRL_CPU1_HOST_TST_CTRL_SHIFT)) & APU_TST_CTRL_CPU1_HOST_TST_CTRL_MASK)
+/*! @} */
+
+/*! @name BCA_LTE_CTRL - BCA LTE Control */
+/*! @{ */
+
+#define APU_BCA_LTE_CTRL_LTE_CNT_START_MASK      (0x1U)
+#define APU_BCA_LTE_CTRL_LTE_CNT_START_SHIFT     (0U)
+/*! LTE_CNT_START - LTE Count Start */
+#define APU_BCA_LTE_CTRL_LTE_CNT_START(x)        (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_LTE_CNT_START_SHIFT)) & APU_BCA_LTE_CTRL_LTE_CNT_START_MASK)
+
+#define APU_BCA_LTE_CTRL_LTE_TMR1_INT_MASK       (0x2U)
+#define APU_BCA_LTE_CTRL_LTE_TMR1_INT_SHIFT      (1U)
+/*! LTE_TMR1_INT - LTE TMR1 Interrupt */
+#define APU_BCA_LTE_CTRL_LTE_TMR1_INT(x)         (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_LTE_TMR1_INT_SHIFT)) & APU_BCA_LTE_CTRL_LTE_TMR1_INT_MASK)
+
+#define APU_BCA_LTE_CTRL_LTE_TMR2_INT_MASK       (0x4U)
+#define APU_BCA_LTE_CTRL_LTE_TMR2_INT_SHIFT      (2U)
+/*! LTE_TMR2_INT - LTE TMR2 Interrupt */
+#define APU_BCA_LTE_CTRL_LTE_TMR2_INT(x)         (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_LTE_TMR2_INT_SHIFT)) & APU_BCA_LTE_CTRL_LTE_TMR2_INT_MASK)
+
+#define APU_BCA_LTE_CTRL_LTE_TMR1_CNT_FREEZE_MASK (0x8U)
+#define APU_BCA_LTE_CTRL_LTE_TMR1_CNT_FREEZE_SHIFT (3U)
+/*! LTE_TMR1_CNT_FREEZE - LTE TMR1 Count Freeze */
+#define APU_BCA_LTE_CTRL_LTE_TMR1_CNT_FREEZE(x)  (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_LTE_TMR1_CNT_FREEZE_SHIFT)) & APU_BCA_LTE_CTRL_LTE_TMR1_CNT_FREEZE_MASK)
+
+#define APU_BCA_LTE_CTRL_LTE_TMR2_CNT_FREEZE_MASK (0x10U)
+#define APU_BCA_LTE_CTRL_LTE_TMR2_CNT_FREEZE_SHIFT (4U)
+/*! LTE_TMR2_CNT_FREEZE - LTE TMR2 Count Freeze */
+#define APU_BCA_LTE_CTRL_LTE_TMR2_CNT_FREEZE(x)  (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_LTE_TMR2_CNT_FREEZE_SHIFT)) & APU_BCA_LTE_CTRL_LTE_TMR2_CNT_FREEZE_MASK)
+
+#define APU_BCA_LTE_CTRL_BCA_LTE_CLK_BYP_MASK    (0x80U)
+#define APU_BCA_LTE_CTRL_BCA_LTE_CLK_BYP_SHIFT   (7U)
+/*! BCA_LTE_CLK_BYP - BCA LTE Clock Bypass */
+#define APU_BCA_LTE_CTRL_BCA_LTE_CLK_BYP(x)      (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_BCA_LTE_CLK_BYP_SHIFT)) & APU_BCA_LTE_CTRL_BCA_LTE_CLK_BYP_MASK)
+
+#define APU_BCA_LTE_CTRL_BCA_WL_LTE_COEX_EN_MASK (0x8000U)
+#define APU_BCA_LTE_CTRL_BCA_WL_LTE_COEX_EN_SHIFT (15U)
+/*! BCA_WL_LTE_COEX_EN - BCA WLAN LTE Coexistence Enable */
+#define APU_BCA_LTE_CTRL_BCA_WL_LTE_COEX_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_BCA_WL_LTE_COEX_EN_SHIFT)) & APU_BCA_LTE_CTRL_BCA_WL_LTE_COEX_EN_MASK)
+
+#define APU_BCA_LTE_CTRL_BCA_BT_LTE_COEX_EN_MASK (0x10000U)
+#define APU_BCA_LTE_CTRL_BCA_BT_LTE_COEX_EN_SHIFT (16U)
+/*! BCA_BT_LTE_COEX_EN - BCA Bluetooth LTE Coexistence Enable */
+#define APU_BCA_LTE_CTRL_BCA_BT_LTE_COEX_EN(x)   (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_BCA_BT_LTE_COEX_EN_SHIFT)) & APU_BCA_LTE_CTRL_BCA_BT_LTE_COEX_EN_MASK)
+
+#define APU_BCA_LTE_CTRL_USE_SLNA_WHILE_BT_MASK  (0x100000U)
+#define APU_BCA_LTE_CTRL_USE_SLNA_WHILE_BT_SHIFT (20U)
+/*! USE_SLNA_WHILE_BT - Use sLNA While Bluetooth */
+#define APU_BCA_LTE_CTRL_USE_SLNA_WHILE_BT(x)    (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_USE_SLNA_WHILE_BT_SHIFT)) & APU_BCA_LTE_CTRL_USE_SLNA_WHILE_BT_MASK)
+
+#define APU_BCA_LTE_CTRL_BCA_FORCE_ON_WHILE_BT_MASK (0x40000000U)
+#define APU_BCA_LTE_CTRL_BCA_FORCE_ON_WHILE_BT_SHIFT (30U)
+/*! BCA_FORCE_ON_WHILE_BT - BCA Force on While Bluetooth */
+#define APU_BCA_LTE_CTRL_BCA_FORCE_ON_WHILE_BT(x) (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_BCA_FORCE_ON_WHILE_BT_SHIFT)) & APU_BCA_LTE_CTRL_BCA_FORCE_ON_WHILE_BT_MASK)
+
+#define APU_BCA_LTE_CTRL_BCA_CLK_FW_EN_MASK      (0x80000000U)
+#define APU_BCA_LTE_CTRL_BCA_CLK_FW_EN_SHIFT     (31U)
+/*! BCA_CLK_FW_EN - BCA Clock FW Enable */
+#define APU_BCA_LTE_CTRL_BCA_CLK_FW_EN(x)        (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_CTRL_BCA_CLK_FW_EN_SHIFT)) & APU_BCA_LTE_CTRL_BCA_CLK_FW_EN_MASK)
+/*! @} */
+
+/*! @name BCA_LTE_TIMER1 - BCA LTE Timer 1 */
+/*! @{ */
+
+#define APU_BCA_LTE_TIMER1_BCA_LTE_TIMER1_MASK   (0xFFFFFFFFU)
+#define APU_BCA_LTE_TIMER1_BCA_LTE_TIMER1_SHIFT  (0U)
+/*! BCA_LTE_TIMER1 - BCA LTE Timer 1 */
+#define APU_BCA_LTE_TIMER1_BCA_LTE_TIMER1(x)     (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_TIMER1_BCA_LTE_TIMER1_SHIFT)) & APU_BCA_LTE_TIMER1_BCA_LTE_TIMER1_MASK)
+/*! @} */
+
+/*! @name BCA_LTE_TIMER2 - BCA LTE Timer 2 */
+/*! @{ */
+
+#define APU_BCA_LTE_TIMER2_BCA_LTE_TIMER2_MASK   (0xFFFFFFFFU)
+#define APU_BCA_LTE_TIMER2_BCA_LTE_TIMER2_SHIFT  (0U)
+/*! BCA_LTE_TIMER2 - BCA LTE Timer 2 */
+#define APU_BCA_LTE_TIMER2_BCA_LTE_TIMER2(x)     (((uint32_t)(((uint32_t)(x)) << APU_BCA_LTE_TIMER2_BCA_LTE_TIMER2_SHIFT)) & APU_BCA_LTE_TIMER2_BCA_LTE_TIMER2_MASK)
+/*! @} */
+
+/*! @name BCA_MWS_WKUP_TIMER - BCA MWS Wakeup Timer */
+/*! @{ */
+
+#define APU_BCA_MWS_WKUP_TIMER_BCA_MWS_TIMER_MASK (0xFFFFU)
+#define APU_BCA_MWS_WKUP_TIMER_BCA_MWS_TIMER_SHIFT (0U)
+/*! BCA_MWS_TIMER - BCA MWS Timer */
+#define APU_BCA_MWS_WKUP_TIMER_BCA_MWS_TIMER(x)  (((uint32_t)(((uint32_t)(x)) << APU_BCA_MWS_WKUP_TIMER_BCA_MWS_TIMER_SHIFT)) & APU_BCA_MWS_WKUP_TIMER_BCA_MWS_TIMER_MASK)
+
+#define APU_BCA_MWS_WKUP_TIMER_BCA_BCN_WKUP_CNT_MASK (0xF0000000U)
+#define APU_BCA_MWS_WKUP_TIMER_BCA_BCN_WKUP_CNT_SHIFT (28U)
+/*! BCA_BCN_WKUP_CNT - BCA Beacon Wakeup Count */
+#define APU_BCA_MWS_WKUP_TIMER_BCA_BCN_WKUP_CNT(x) (((uint32_t)(((uint32_t)(x)) << APU_BCA_MWS_WKUP_TIMER_BCA_BCN_WKUP_CNT_SHIFT)) & APU_BCA_MWS_WKUP_TIMER_BCA_BCN_WKUP_CNT_MASK)
+/*! @} */
+
+/*! @name BT2_CTRL - Bluetooth 2 Control */
+/*! @{ */
+
+#define APU_BT2_CTRL_BT_SLP_RDY_MASK             (0x1U)
+#define APU_BT2_CTRL_BT_SLP_RDY_SHIFT            (0U)
+/*! BT_SLP_RDY - Bluetooth Sleep Ready */
+#define APU_BT2_CTRL_BT_SLP_RDY(x)               (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BT_SLP_RDY_SHIFT)) & APU_BT2_CTRL_BT_SLP_RDY_MASK)
+
+#define APU_BT2_CTRL_BT_SLP_RDYMASK_MASK         (0x2U)
+#define APU_BT2_CTRL_BT_SLP_RDYMASK_SHIFT        (1U)
+/*! BT_SLP_RDYMASK - Bluetoot Sleep Ready Mask */
+#define APU_BT2_CTRL_BT_SLP_RDYMASK(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BT_SLP_RDYMASK_SHIFT)) & APU_BT2_CTRL_BT_SLP_RDYMASK_MASK)
+
+#define APU_BT2_CTRL_BT_SLP_RDY_FW_MASK          (0x4U)
+#define APU_BT2_CTRL_BT_SLP_RDY_FW_SHIFT         (2U)
+/*! BT_SLP_RDY_FW - Bluetooth Sleep Ready FW */
+#define APU_BT2_CTRL_BT_SLP_RDY_FW(x)            (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BT_SLP_RDY_FW_SHIFT)) & APU_BT2_CTRL_BT_SLP_RDY_FW_MASK)
+
+#define APU_BT2_CTRL_BTU_CLK_NCO_MODE_SEL_EN_MASK (0x8U)
+#define APU_BT2_CTRL_BTU_CLK_NCO_MODE_SEL_EN_SHIFT (3U)
+/*! BTU_CLK_NCO_MODE_SEL_EN - 1- ignore the btu_clk_nco_mode from CIU2, keep the bt_clk_req as XP wakeup source */
+#define APU_BT2_CTRL_BTU_CLK_NCO_MODE_SEL_EN(x)  (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BTU_CLK_NCO_MODE_SEL_EN_SHIFT)) & APU_BT2_CTRL_BTU_CLK_NCO_MODE_SEL_EN_MASK)
+
+#define APU_BT2_CTRL_USE_BT_INTR_SLP_MASK        (0x80U)
+#define APU_BT2_CTRL_USE_BT_INTR_SLP_SHIFT       (7U)
+/*! USE_BT_INTR_SLP - Use Bluetooth interrupt Sleep */
+#define APU_BT2_CTRL_USE_BT_INTR_SLP(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_USE_BT_INTR_SLP_SHIFT)) & APU_BT2_CTRL_USE_BT_INTR_SLP_MASK)
+
+#define APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL1_MASK  (0x4000000U)
+#define APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL1_SHIFT (26U)
+/*! BT_CLK_SYNC_MODE_SEL1 - Bluetooth Clock Sync Mode Select 1 */
+#define APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL1(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL1_SHIFT)) & APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL1_MASK)
+
+#define APU_BT2_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_MASK (0x8000000U)
+#define APU_BT2_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_SHIFT (27U)
+/*! USE_GLITCH_FREE_BT_CLK_REQ - Use Glitch-Free Bluetooth Clock Request */
+#define APU_BT2_CTRL_USE_GLITCH_FREE_BT_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_SHIFT)) & APU_BT2_CTRL_USE_GLITCH_FREE_BT_CLK_REQ_MASK)
+
+#define APU_BT2_CTRL_BRF_CLK_SYNC_MODE_SEL_MASK  (0x10000000U)
+#define APU_BT2_CTRL_BRF_CLK_SYNC_MODE_SEL_SHIFT (28U)
+/*! BRF_CLK_SYNC_MODE_SEL - BRF Clock Sync Mode Select */
+#define APU_BT2_CTRL_BRF_CLK_SYNC_MODE_SEL(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BRF_CLK_SYNC_MODE_SEL_SHIFT)) & APU_BT2_CTRL_BRF_CLK_SYNC_MODE_SEL_MASK)
+
+#define APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL0_MASK  (0x20000000U)
+#define APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL0_SHIFT (29U)
+/*! BT_CLK_SYNC_MODE_SEL0 - Bluetooth Clock Sync Mode Select 0 */
+#define APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL0(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL0_SHIFT)) & APU_BT2_CTRL_BT_CLK_SYNC_MODE_SEL0_MASK)
+
+#define APU_BT2_CTRL_BT_PLL_SYNC_MODE_SEL_MASK   (0x40000000U)
+#define APU_BT2_CTRL_BT_PLL_SYNC_MODE_SEL_SHIFT  (30U)
+/*! BT_PLL_SYNC_MODE_SEL - Bluetooth PLL Sync Mode Select */
+#define APU_BT2_CTRL_BT_PLL_SYNC_MODE_SEL(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BT_PLL_SYNC_MODE_SEL_SHIFT)) & APU_BT2_CTRL_BT_PLL_SYNC_MODE_SEL_MASK)
+
+#define APU_BT2_CTRL_BT_HOST_SLP_RDY_MASK        (0x80000000U)
+#define APU_BT2_CTRL_BT_HOST_SLP_RDY_SHIFT       (31U)
+/*! BT_HOST_SLP_RDY - Bluetooth Host Sleep Ready */
+#define APU_BT2_CTRL_BT_HOST_SLP_RDY(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT2_CTRL_BT_HOST_SLP_RDY_SHIFT)) & APU_BT2_CTRL_BT_HOST_SLP_RDY_MASK)
+/*! @} */
+
+/*! @name BT2_WKUP_MASK - Bluetooth 2 Wakeup Mask */
+/*! @{ */
+
+#define APU_BT2_WKUP_MASK_BCA_CLK_REQ_MASK_MASK  (0x1U)
+#define APU_BT2_WKUP_MASK_BCA_CLK_REQ_MASK_SHIFT (0U)
+/*! BCA_CLK_REQ_MASK - BCA Clock Request Mask */
+#define APU_BT2_WKUP_MASK_BCA_CLK_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT2_WKUP_MASK_BCA_CLK_REQ_MASK_SHIFT)) & APU_BT2_WKUP_MASK_BCA_CLK_REQ_MASK_MASK)
+
+#define APU_BT2_WKUP_MASK_BT_CLK_REQ_MASK_MASK   (0x2U)
+#define APU_BT2_WKUP_MASK_BT_CLK_REQ_MASK_SHIFT  (1U)
+/*! BT_CLK_REQ_MASK - Bluetooth Clock Request Mask */
+#define APU_BT2_WKUP_MASK_BT_CLK_REQ_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT2_WKUP_MASK_BT_CLK_REQ_MASK_SHIFT)) & APU_BT2_WKUP_MASK_BT_CLK_REQ_MASK_MASK)
+
+#define APU_BT2_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_MASK (0x4U)
+#define APU_BT2_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_SHIFT (2U)
+/*! BT_WB_ACTIVE_REQ_MASK - Bluetooth WB Active Request Mask */
+#define APU_BT2_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_BT2_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_SHIFT)) & APU_BT2_WKUP_MASK_BT_WB_ACTIVE_REQ_MASK_MASK)
+
+#define APU_BT2_WKUP_MASK_BT_INTR_MASK_MASK      (0x8U)
+#define APU_BT2_WKUP_MASK_BT_INTR_MASK_SHIFT     (3U)
+/*! BT_INTR_MASK - Bluetooth Interrupt Mask */
+#define APU_BT2_WKUP_MASK_BT_INTR_MASK(x)        (((uint32_t)(((uint32_t)(x)) << APU_BT2_WKUP_MASK_BT_INTR_MASK_SHIFT)) & APU_BT2_WKUP_MASK_BT_INTR_MASK_MASK)
+
+#define APU_BT2_WKUP_MASK_BT_PLL_REQ_MASK_MASK   (0x10U)
+#define APU_BT2_WKUP_MASK_BT_PLL_REQ_MASK_SHIFT  (4U)
+/*! BT_PLL_REQ_MASK - Bluetooth PLL Request Mask */
+#define APU_BT2_WKUP_MASK_BT_PLL_REQ_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT2_WKUP_MASK_BT_PLL_REQ_MASK_SHIFT)) & APU_BT2_WKUP_MASK_BT_PLL_REQ_MASK_MASK)
+
+#define APU_BT2_WKUP_MASK_BRF_PLL_REQ_MASK_MASK  (0x20U)
+#define APU_BT2_WKUP_MASK_BRF_PLL_REQ_MASK_SHIFT (5U)
+/*! BRF_PLL_REQ_MASK - BRF PLL Request Mask */
+#define APU_BT2_WKUP_MASK_BRF_PLL_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT2_WKUP_MASK_BRF_PLL_REQ_MASK_SHIFT)) & APU_BT2_WKUP_MASK_BRF_PLL_REQ_MASK_MASK)
+
+#define APU_BT2_WKUP_MASK_BT_HOST_MAP_MASK       (0xFFFF0000U)
+#define APU_BT2_WKUP_MASK_BT_HOST_MAP_SHIFT      (16U)
+/*! BT_HOST_MAP - Bluetooth Host Map */
+#define APU_BT2_WKUP_MASK_BT_HOST_MAP(x)         (((uint32_t)(((uint32_t)(x)) << APU_BT2_WKUP_MASK_BT_HOST_MAP_SHIFT)) & APU_BT2_WKUP_MASK_BT_HOST_MAP_MASK)
+/*! @} */
+
+/*! @name BT2_STATUS - Bluetooth 2 Status */
+/*! @{ */
+
+#define APU_BT2_STATUS_APU_BT_CLK_EN_MASK        (0x1U)
+#define APU_BT2_STATUS_APU_BT_CLK_EN_SHIFT       (0U)
+/*! APU_BT_CLK_EN - APU Bluetooth Clock Enable */
+#define APU_BT2_STATUS_APU_BT_CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_APU_BT_CLK_EN_SHIFT)) & APU_BT2_STATUS_APU_BT_CLK_EN_MASK)
+
+#define APU_BT2_STATUS_APU_BRF_CLK_EN_MASK       (0x2U)
+#define APU_BT2_STATUS_APU_BRF_CLK_EN_SHIFT      (1U)
+/*! APU_BRF_CLK_EN - APU BRF Clock Enable */
+#define APU_BT2_STATUS_APU_BRF_CLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_APU_BRF_CLK_EN_SHIFT)) & APU_BT2_STATUS_APU_BRF_CLK_EN_MASK)
+
+#define APU_BT2_STATUS_BT_ACTIVE_SLPCK_MASK      (0x4U)
+#define APU_BT2_STATUS_BT_ACTIVE_SLPCK_SHIFT     (2U)
+/*! BT_ACTIVE_SLPCK - Bluetooth Active Sleep Clock */
+#define APU_BT2_STATUS_BT_ACTIVE_SLPCK(x)        (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_BT_ACTIVE_SLPCK_SHIFT)) & APU_BT2_STATUS_BT_ACTIVE_SLPCK_MASK)
+
+#define APU_BT2_STATUS_BT_HOST_WKUP_MASK         (0x10U)
+#define APU_BT2_STATUS_BT_HOST_WKUP_SHIFT        (4U)
+/*! BT_HOST_WKUP - Bluetooth Host Wakeup */
+#define APU_BT2_STATUS_BT_HOST_WKUP(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_BT_HOST_WKUP_SHIFT)) & APU_BT2_STATUS_BT_HOST_WKUP_MASK)
+
+#define APU_BT2_STATUS_BT_INTERRUPT_MASK         (0x20U)
+#define APU_BT2_STATUS_BT_INTERRUPT_SHIFT        (5U)
+/*! BT_INTERRUPT - Bluetooth Interrupt */
+#define APU_BT2_STATUS_BT_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_BT_INTERRUPT_SHIFT)) & APU_BT2_STATUS_BT_INTERRUPT_MASK)
+
+#define APU_BT2_STATUS_BT_PLL_REQ_MASK           (0x40U)
+#define APU_BT2_STATUS_BT_PLL_REQ_SHIFT          (6U)
+/*! BT_PLL_REQ - Bluetooth PLL Request */
+#define APU_BT2_STATUS_BT_PLL_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_BT_PLL_REQ_SHIFT)) & APU_BT2_STATUS_BT_PLL_REQ_MASK)
+
+#define APU_BT2_STATUS_BT_CLK_REQ_MASK           (0x80U)
+#define APU_BT2_STATUS_BT_CLK_REQ_SHIFT          (7U)
+/*! BT_CLK_REQ - Bluetooth Clock Request */
+#define APU_BT2_STATUS_BT_CLK_REQ(x)             (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_BT_CLK_REQ_SHIFT)) & APU_BT2_STATUS_BT_CLK_REQ_MASK)
+
+#define APU_BT2_STATUS_BRF_PLL_REQ_MASK          (0x100U)
+#define APU_BT2_STATUS_BRF_PLL_REQ_SHIFT         (8U)
+/*! BRF_PLL_REQ - BRF PLL Request */
+#define APU_BT2_STATUS_BRF_PLL_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_BRF_PLL_REQ_SHIFT)) & APU_BT2_STATUS_BRF_PLL_REQ_MASK)
+
+#define APU_BT2_STATUS_BT_WIDEBAND_ACTIVE_MASK   (0x200U)
+#define APU_BT2_STATUS_BT_WIDEBAND_ACTIVE_SHIFT  (9U)
+/*! BT_WIDEBAND_ACTIVE - Bluetooth Wideband Active */
+#define APU_BT2_STATUS_BT_WIDEBAND_ACTIVE(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_BT_WIDEBAND_ACTIVE_SHIFT)) & APU_BT2_STATUS_BT_WIDEBAND_ACTIVE_MASK)
+
+#define APU_BT2_STATUS_HOST_WKUP_IN_MASK         (0xFFFF0000U)
+#define APU_BT2_STATUS_HOST_WKUP_IN_SHIFT        (16U)
+/*! HOST_WKUP_IN - Host Wakeup In */
+#define APU_BT2_STATUS_HOST_WKUP_IN(x)           (((uint32_t)(((uint32_t)(x)) << APU_BT2_STATUS_HOST_WKUP_IN_SHIFT)) & APU_BT2_STATUS_HOST_WKUP_IN_MASK)
+/*! @} */
+
+/*! @name BT2_CKEN_CTRL - Bluetooth 2 Clock Enable Control */
+/*! @{ */
+
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_PWR_MASK (0x1U)
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_PWR_SHIFT (0U)
+/*! BT_CLK_EN_VAL_PWR - control value for bt_clk_en when power ready */
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_PWR(x)   (((uint32_t)(((uint32_t)(x)) << APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_PWR_SHIFT)) & APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_PWR_MASK)
+
+#define APU_BT2_CKEN_CTRL_BL_CLK_EN_SEL_PWR_MASK (0x2U)
+#define APU_BT2_CKEN_CTRL_BL_CLK_EN_SEL_PWR_SHIFT (1U)
+/*! BL_CLK_EN_SEL_PWR - selection for bt_clk_en when power ready */
+#define APU_BT2_CKEN_CTRL_BL_CLK_EN_SEL_PWR(x)   (((uint32_t)(((uint32_t)(x)) << APU_BT2_CKEN_CTRL_BL_CLK_EN_SEL_PWR_SHIFT)) & APU_BT2_CKEN_CTRL_BL_CLK_EN_SEL_PWR_MASK)
+
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_MASK (0x4U)
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_SHIFT (2U)
+/*! BT_CLK_EN_VAL_XOSC - control value for bt_clk_en when XOSC ready */
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_XOSC(x)  (((uint32_t)(((uint32_t)(x)) << APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_SHIFT)) & APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_XOSC_MASK)
+
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_MASK (0x8U)
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_SHIFT (3U)
+/*! BT_CLK_EN_SEL_XOSC - selection for bt_clk_en when XOSC ready */
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_XOSC(x)  (((uint32_t)(((uint32_t)(x)) << APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_SHIFT)) & APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_XOSC_MASK)
+
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_MASK     (0x10U)
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_SHIFT    (4U)
+/*! BT_CLK_EN_VAL - control value for bt_clk_en when PLL ready */
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_SHIFT)) & APU_BT2_CKEN_CTRL_BT_CLK_EN_VAL_MASK)
+
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_MASK     (0x20U)
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_SHIFT    (5U)
+/*! BT_CLK_EN_SEL - selection for bt_clk_en when PLL ready */
+#define APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL(x)       (((uint32_t)(((uint32_t)(x)) << APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_SHIFT)) & APU_BT2_CKEN_CTRL_BT_CLK_EN_SEL_MASK)
+/*! @} */
+
+/*! @name BT2_RESRC_CTRL - Bluetooth 2 RESRC Control */
+/*! @{ */
+
+#define APU_BT2_RESRC_CTRL_FW_PWR_REQ_MASK       (0x1U)
+#define APU_BT2_RESRC_CTRL_FW_PWR_REQ_SHIFT      (0U)
+/*! FW_PWR_REQ - override hw power request */
+#define APU_BT2_RESRC_CTRL_FW_PWR_REQ(x)         (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_PWR_REQ_SHIFT)) & APU_BT2_RESRC_CTRL_FW_PWR_REQ_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_PWR_REQ_VAL_MASK   (0x2U)
+#define APU_BT2_RESRC_CTRL_FW_PWR_REQ_VAL_SHIFT  (1U)
+/*! FW_PWR_REQ_VAL - override value when apu_bt_resrc_ctrl[0] is set */
+#define APU_BT2_RESRC_CTRL_FW_PWR_REQ_VAL(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_PWR_REQ_VAL_SHIFT)) & APU_BT2_RESRC_CTRL_FW_PWR_REQ_VAL_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_XOSC_REQ_MASK      (0x4U)
+#define APU_BT2_RESRC_CTRL_FW_XOSC_REQ_SHIFT     (2U)
+/*! FW_XOSC_REQ - override hw xosc request */
+#define APU_BT2_RESRC_CTRL_FW_XOSC_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_XOSC_REQ_SHIFT)) & APU_BT2_RESRC_CTRL_FW_XOSC_REQ_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_XOSC_REQ_VAL_MASK  (0x8U)
+#define APU_BT2_RESRC_CTRL_FW_XOSC_REQ_VAL_SHIFT (3U)
+/*! FW_XOSC_REQ_VAL - override value when apu_bt_resrc_ctrl[2] is set */
+#define APU_BT2_RESRC_CTRL_FW_XOSC_REQ_VAL(x)    (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_XOSC_REQ_VAL_SHIFT)) & APU_BT2_RESRC_CTRL_FW_XOSC_REQ_VAL_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_XP_REQ_MASK        (0x10U)
+#define APU_BT2_RESRC_CTRL_FW_XP_REQ_SHIFT       (4U)
+/*! FW_XP_REQ - override hw xosc + pwr request */
+#define APU_BT2_RESRC_CTRL_FW_XP_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_XP_REQ_SHIFT)) & APU_BT2_RESRC_CTRL_FW_XP_REQ_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_XP_REQ_VAL_MASK    (0x20U)
+#define APU_BT2_RESRC_CTRL_FW_XP_REQ_VAL_SHIFT   (5U)
+/*! FW_XP_REQ_VAL - override value when apu_bt_resrc_ctrl[4] is set */
+#define APU_BT2_RESRC_CTRL_FW_XP_REQ_VAL(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_XP_REQ_VAL_SHIFT)) & APU_BT2_RESRC_CTRL_FW_XP_REQ_VAL_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_SB_REQ_MASK        (0x40U)
+#define APU_BT2_RESRC_CTRL_FW_SB_REQ_SHIFT       (6U)
+/*! FW_SB_REQ - override hw xosc + pwr + pll sb request */
+#define APU_BT2_RESRC_CTRL_FW_SB_REQ(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_SB_REQ_SHIFT)) & APU_BT2_RESRC_CTRL_FW_SB_REQ_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_SB_REQ_VAL_MASK    (0x80U)
+#define APU_BT2_RESRC_CTRL_FW_SB_REQ_VAL_SHIFT   (7U)
+/*! FW_SB_REQ_VAL - override value when apu_bt_resrc_ctrl[6] is set */
+#define APU_BT2_RESRC_CTRL_FW_SB_REQ_VAL(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_SB_REQ_VAL_SHIFT)) & APU_BT2_RESRC_CTRL_FW_SB_REQ_VAL_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_MASK    (0x100U)
+#define APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_SHIFT   (8U)
+/*! FW_IPWAKE_REQ - override hw xosc + pwr + pll ipwake request */
+#define APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ(x)      (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_SHIFT)) & APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_VAL_MASK (0x200U)
+#define APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_VAL_SHIFT (9U)
+/*! FW_IPWAKE_REQ_VAL - override value when apu_bt_resrc_ctrl[8] is set */
+#define APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_VAL(x)  (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_VAL_SHIFT)) & APU_BT2_RESRC_CTRL_FW_IPWAKE_REQ_VAL_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_MASK   (0x400U)
+#define APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_SHIFT  (10U)
+/*! FW_ALLWAKE_REQ - firmware override hw xosc + pwr + pll allwake request */
+#define APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ(x)     (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_SHIFT)) & APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_MASK)
+
+#define APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_MASK (0x800U)
+#define APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_SHIFT (11U)
+/*! FW_ALLWAKE_REQ_VAL - firmware override value when apu_bt_resrc_ctrl[10] is set */
+#define APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_SHIFT)) & APU_BT2_RESRC_CTRL_FW_ALLWAKE_REQ_VAL_MASK)
+/*! @} */
+
+/*! @name BT2_DVFS_CTRL - Bluetooth 2 DVFS Control */
+/*! @{ */
+
+#define APU_BT2_DVFS_CTRL_BT_VOL_VAL_MASK        (0x7FU)
+#define APU_BT2_DVFS_CTRL_BT_VOL_VAL_SHIFT       (0U)
+/*! BT_VOL_VAL - Blueooth Vol Value */
+#define APU_BT2_DVFS_CTRL_BT_VOL_VAL(x)          (((uint32_t)(((uint32_t)(x)) << APU_BT2_DVFS_CTRL_BT_VOL_VAL_SHIFT)) & APU_BT2_DVFS_CTRL_BT_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name BLE2_CTRL - BLE 2 Control */
+/*! @{ */
+
+#define APU_BLE2_CTRL_BLE_SLP_RDY_MASK           (0x1U)
+#define APU_BLE2_CTRL_BLE_SLP_RDY_SHIFT          (0U)
+/*! BLE_SLP_RDY - BLE Sleep Ready */
+#define APU_BLE2_CTRL_BLE_SLP_RDY(x)             (((uint32_t)(((uint32_t)(x)) << APU_BLE2_CTRL_BLE_SLP_RDY_SHIFT)) & APU_BLE2_CTRL_BLE_SLP_RDY_MASK)
+
+#define APU_BLE2_CTRL_BLE_SLP_RDYMASK_MASK       (0x2U)
+#define APU_BLE2_CTRL_BLE_SLP_RDYMASK_SHIFT      (1U)
+/*! BLE_SLP_RDYMASK - BLE Sleep Ready Mask */
+#define APU_BLE2_CTRL_BLE_SLP_RDYMASK(x)         (((uint32_t)(((uint32_t)(x)) << APU_BLE2_CTRL_BLE_SLP_RDYMASK_SHIFT)) & APU_BLE2_CTRL_BLE_SLP_RDYMASK_MASK)
+
+#define APU_BLE2_CTRL_BLE_SLP_RDY_FW_MASK        (0x4U)
+#define APU_BLE2_CTRL_BLE_SLP_RDY_FW_SHIFT       (2U)
+/*! BLE_SLP_RDY_FW - BLE Sleep Ready FW */
+#define APU_BLE2_CTRL_BLE_SLP_RDY_FW(x)          (((uint32_t)(((uint32_t)(x)) << APU_BLE2_CTRL_BLE_SLP_RDY_FW_SHIFT)) & APU_BLE2_CTRL_BLE_SLP_RDY_FW_MASK)
+
+#define APU_BLE2_CTRL_BLE_MODE_EN_MASK           (0x8U)
+#define APU_BLE2_CTRL_BLE_MODE_EN_SHIFT          (3U)
+/*! BLE_MODE_EN - BLE Mode Enable */
+#define APU_BLE2_CTRL_BLE_MODE_EN(x)             (((uint32_t)(((uint32_t)(x)) << APU_BLE2_CTRL_BLE_MODE_EN_SHIFT)) & APU_BLE2_CTRL_BLE_MODE_EN_MASK)
+
+#define APU_BLE2_CTRL_BT_AES_NCO_MODE_MASK       (0x8000U)
+#define APU_BLE2_CTRL_BT_AES_NCO_MODE_SHIFT      (15U)
+/*! BT_AES_NCO_MODE - Bluetooth AES NCO Mode */
+#define APU_BLE2_CTRL_BT_AES_NCO_MODE(x)         (((uint32_t)(((uint32_t)(x)) << APU_BLE2_CTRL_BT_AES_NCO_MODE_SHIFT)) & APU_BLE2_CTRL_BT_AES_NCO_MODE_MASK)
+
+#define APU_BLE2_CTRL_BLE_XP_REQ_MASK            (0x80000000U)
+#define APU_BLE2_CTRL_BLE_XP_REQ_SHIFT           (31U)
+/*! BLE_XP_REQ - BLE XP Request */
+#define APU_BLE2_CTRL_BLE_XP_REQ(x)              (((uint32_t)(((uint32_t)(x)) << APU_BLE2_CTRL_BLE_XP_REQ_SHIFT)) & APU_BLE2_CTRL_BLE_XP_REQ_MASK)
+/*! @} */
+
+/*! @name BLE2_WKUP_MASK - BLE 2 Wakeup Mask */
+/*! @{ */
+
+#define APU_BLE2_WKUP_MASK_BT_AES_CLK_REQ_MASK_MASK (0x8U)
+#define APU_BLE2_WKUP_MASK_BT_AES_CLK_REQ_MASK_SHIFT (3U)
+/*! BT_AES_CLK_REQ_MASK - Bluetooth AES Clock Request Mask */
+#define APU_BLE2_WKUP_MASK_BT_AES_CLK_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_BLE2_WKUP_MASK_BT_AES_CLK_REQ_MASK_SHIFT)) & APU_BLE2_WKUP_MASK_BT_AES_CLK_REQ_MASK_MASK)
+
+#define APU_BLE2_WKUP_MASK_LBC_XP_REQ_MASK_MASK  (0x10U)
+#define APU_BLE2_WKUP_MASK_LBC_XP_REQ_MASK_SHIFT (4U)
+/*! LBC_XP_REQ_MASK - LBC XP Request Mask */
+#define APU_BLE2_WKUP_MASK_LBC_XP_REQ_MASK(x)    (((uint32_t)(((uint32_t)(x)) << APU_BLE2_WKUP_MASK_LBC_XP_REQ_MASK_SHIFT)) & APU_BLE2_WKUP_MASK_LBC_XP_REQ_MASK_MASK)
+/*! @} */
+
+/*! @name BLE2_STATUS - BLE 2 Status */
+/*! @{ */
+
+#define APU_BLE2_STATUS_APU_BT_AES_CLK_EN_MASK   (0x1U)
+#define APU_BLE2_STATUS_APU_BT_AES_CLK_EN_SHIFT  (0U)
+/*! APU_BT_AES_CLK_EN - APU Bluetooth AES Clock Enable */
+#define APU_BLE2_STATUS_APU_BT_AES_CLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_APU_BT_AES_CLK_EN_SHIFT)) & APU_BLE2_STATUS_APU_BT_AES_CLK_EN_MASK)
+
+#define APU_BLE2_STATUS_BT_AES_CLK_SEL_MASK      (0x2U)
+#define APU_BLE2_STATUS_BT_AES_CLK_SEL_SHIFT     (1U)
+/*! BT_AES_CLK_SEL - Bluetooth AES Clock Select */
+#define APU_BLE2_STATUS_BT_AES_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_BT_AES_CLK_SEL_SHIFT)) & APU_BLE2_STATUS_BT_AES_CLK_SEL_MASK)
+
+#define APU_BLE2_STATUS_XOSC_STABLE_REFCK_MASK   (0x4U)
+#define APU_BLE2_STATUS_XOSC_STABLE_REFCK_SHIFT  (2U)
+/*! XOSC_STABLE_REFCK - XOSC Stable Ref Clock */
+#define APU_BLE2_STATUS_XOSC_STABLE_REFCK(x)     (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_XOSC_STABLE_REFCK_SHIFT)) & APU_BLE2_STATUS_XOSC_STABLE_REFCK_MASK)
+
+#define APU_BLE2_STATUS_T1_STABLE_MASK           (0x8U)
+#define APU_BLE2_STATUS_T1_STABLE_SHIFT          (3U)
+/*! T1_STABLE - T1 Delay */
+#define APU_BLE2_STATUS_T1_STABLE(x)             (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_T1_STABLE_SHIFT)) & APU_BLE2_STATUS_T1_STABLE_MASK)
+
+#define APU_BLE2_STATUS_BT_INTERRUPT_MASK        (0x10U)
+#define APU_BLE2_STATUS_BT_INTERRUPT_SHIFT       (4U)
+/*! BT_INTERRUPT - Bluetooth Interrupt */
+#define APU_BLE2_STATUS_BT_INTERRUPT(x)          (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_BT_INTERRUPT_SHIFT)) & APU_BLE2_STATUS_BT_INTERRUPT_MASK)
+
+#define APU_BLE2_STATUS_BLE_XP_REQ_MASK          (0x20U)
+#define APU_BLE2_STATUS_BLE_XP_REQ_SHIFT         (5U)
+/*! BLE_XP_REQ - BLE XP Request */
+#define APU_BLE2_STATUS_BLE_XP_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_BLE_XP_REQ_SHIFT)) & APU_BLE2_STATUS_BLE_XP_REQ_MASK)
+
+#define APU_BLE2_STATUS_BT_AES_NCO_MODE_MASK     (0x40U)
+#define APU_BLE2_STATUS_BT_AES_NCO_MODE_SHIFT    (6U)
+/*! BT_AES_NCO_MODE - Blueooth AES NCO Mode */
+#define APU_BLE2_STATUS_BT_AES_NCO_MODE(x)       (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_BT_AES_NCO_MODE_SHIFT)) & APU_BLE2_STATUS_BT_AES_NCO_MODE_MASK)
+
+#define APU_BLE2_STATUS_LBC_XP_REQ_MASK          (0x100U)
+#define APU_BLE2_STATUS_LBC_XP_REQ_SHIFT         (8U)
+/*! LBC_XP_REQ - LBC XP Request */
+#define APU_BLE2_STATUS_LBC_XP_REQ(x)            (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_LBC_XP_REQ_SHIFT)) & APU_BLE2_STATUS_LBC_XP_REQ_MASK)
+
+#define APU_BLE2_STATUS_BT_AES_CLK_REQ_MASK      (0x200U)
+#define APU_BLE2_STATUS_BT_AES_CLK_REQ_SHIFT     (9U)
+/*! BT_AES_CLK_REQ - Bluetooth AES Clock Request Mask */
+#define APU_BLE2_STATUS_BT_AES_CLK_REQ(x)        (((uint32_t)(((uint32_t)(x)) << APU_BLE2_STATUS_BT_AES_CLK_REQ_SHIFT)) & APU_BLE2_STATUS_BT_AES_CLK_REQ_MASK)
+/*! @} */
+
+/*! @name LMU_IP_REVISION - LMU IP Revision */
+/*! @{ */
+
+#define APU_LMU_IP_REVISION_IP_REV_MASK          (0xFFFFU)
+#define APU_LMU_IP_REVISION_IP_REV_SHIFT         (0U)
+/*! IP_REV - IP Revision */
+#define APU_LMU_IP_REVISION_IP_REV(x)            (((uint32_t)(((uint32_t)(x)) << APU_LMU_IP_REVISION_IP_REV_SHIFT)) & APU_LMU_IP_REVISION_IP_REV_MASK)
+/*! @} */
+
+/*! @name LMU_CPU1_STA_CFG - LMU CPU1 STA Configuration */
+/*! @{ */
+
+#define APU_LMU_CPU1_STA_CFG_BANK0_STA_OFF_EN_MASK (0x1U)
+#define APU_LMU_CPU1_STA_CFG_BANK0_STA_OFF_EN_SHIFT (0U)
+/*! BANK0_STA_OFF_EN - Bank0 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK0_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK0_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK0_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED15_MASK     (0x2U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED15_SHIFT    (1U)
+/*! RESERVED15 - Reserved 15 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED15(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED15_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED15_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK1_STA_OFF_EN_MASK (0x4U)
+#define APU_LMU_CPU1_STA_CFG_BANK1_STA_OFF_EN_SHIFT (2U)
+/*! BANK1_STA_OFF_EN - Bank1 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK1_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK1_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK1_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED14_MASK     (0x8U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED14_SHIFT    (3U)
+/*! RESERVED14 - Reserved 14 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED14(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED14_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED14_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK2_STA_OFF_EN_MASK (0x10U)
+#define APU_LMU_CPU1_STA_CFG_BANK2_STA_OFF_EN_SHIFT (4U)
+/*! BANK2_STA_OFF_EN - Bank2 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK2_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK2_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK2_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED13_MASK     (0x20U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED13_SHIFT    (5U)
+/*! RESERVED13 - Reserved 13 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED13(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED13_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED13_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK3_STA_OFF_EN_MASK (0x40U)
+#define APU_LMU_CPU1_STA_CFG_BANK3_STA_OFF_EN_SHIFT (6U)
+/*! BANK3_STA_OFF_EN - Bank3 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK3_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK3_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK3_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED12_MASK     (0x80U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED12_SHIFT    (7U)
+/*! RESERVED12 - Reserved 12 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED12(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED12_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED12_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK4_STA_OFF_EN_MASK (0x100U)
+#define APU_LMU_CPU1_STA_CFG_BANK4_STA_OFF_EN_SHIFT (8U)
+/*! BANK4_STA_OFF_EN - Bank4 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK4_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK4_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK4_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED11_MASK     (0x200U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED11_SHIFT    (9U)
+/*! RESERVED11 - Reserved 11 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED11(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED11_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED11_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK5_STA_OFF_EN_MASK (0x400U)
+#define APU_LMU_CPU1_STA_CFG_BANK5_STA_OFF_EN_SHIFT (10U)
+/*! BANK5_STA_OFF_EN - Bank5 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK5_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK5_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK5_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED10_MASK     (0x800U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED10_SHIFT    (11U)
+/*! RESERVED10 - Reserved 10 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED10(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED10_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED10_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK6_STA_OFF_EN_MASK (0x1000U)
+#define APU_LMU_CPU1_STA_CFG_BANK6_STA_OFF_EN_SHIFT (12U)
+/*! BANK6_STA_OFF_EN - Bank6 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK6_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK6_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK6_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED9_MASK      (0x2000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED9_SHIFT     (13U)
+/*! RESERVED9 - Reserved 9 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED9(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED9_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED9_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK7_STA_OFF_EN_MASK (0x4000U)
+#define APU_LMU_CPU1_STA_CFG_BANK7_STA_OFF_EN_SHIFT (14U)
+/*! BANK7_STA_OFF_EN - Bank7 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK7_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK7_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK7_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED8_MASK      (0x8000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED8_SHIFT     (15U)
+/*! RESERVED8 - Reserved 8 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED8(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED8_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED8_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK8_STA_OFF_EN_MASK (0x10000U)
+#define APU_LMU_CPU1_STA_CFG_BANK8_STA_OFF_EN_SHIFT (16U)
+/*! BANK8_STA_OFF_EN - Bank8 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK8_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK8_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK8_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED7_MASK      (0x20000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED7_SHIFT     (17U)
+/*! RESERVED7 - Reserved 7 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED7(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED7_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED7_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK9_STA_OFF_EN_MASK (0x40000U)
+#define APU_LMU_CPU1_STA_CFG_BANK9_STA_OFF_EN_SHIFT (18U)
+/*! BANK9_STA_OFF_EN - Bank9 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK9_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK9_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK9_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED6_MASK      (0x80000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED6_SHIFT     (19U)
+/*! RESERVED6 - Reserved 6 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED6(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED6_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED6_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK10_STA_OFF_EN_MASK (0x100000U)
+#define APU_LMU_CPU1_STA_CFG_BANK10_STA_OFF_EN_SHIFT (20U)
+/*! BANK10_STA_OFF_EN - Bank10 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK10_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK10_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK10_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED5_MASK      (0x200000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED5_SHIFT     (21U)
+/*! RESERVED5 - Reserved 5 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED5(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED5_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED5_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK11_STA_OFF_EN_MASK (0x400000U)
+#define APU_LMU_CPU1_STA_CFG_BANK11_STA_OFF_EN_SHIFT (22U)
+/*! BANK11_STA_OFF_EN - Bank11 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK11_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK11_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK11_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED4_MASK      (0x800000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED4_SHIFT     (23U)
+/*! RESERVED4 - Reserved 4 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED4(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED4_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED4_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK12_STA_OFF_EN_MASK (0x1000000U)
+#define APU_LMU_CPU1_STA_CFG_BANK12_STA_OFF_EN_SHIFT (24U)
+/*! BANK12_STA_OFF_EN - Bank12 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK12_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK12_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK12_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED3_MASK      (0x2000000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED3_SHIFT     (25U)
+/*! RESERVED3 - Reserved 3 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED3(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED3_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED3_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK13_STA_OFF_EN_MASK (0x4000000U)
+#define APU_LMU_CPU1_STA_CFG_BANK13_STA_OFF_EN_SHIFT (26U)
+/*! BANK13_STA_OFF_EN - Bank13 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK13_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK13_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK13_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED2_MASK      (0x8000000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED2_SHIFT     (27U)
+/*! RESERVED2 - Reserved 2 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED2(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED2_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED2_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK14_STA_OFF_EN_MASK (0x10000000U)
+#define APU_LMU_CPU1_STA_CFG_BANK14_STA_OFF_EN_SHIFT (28U)
+/*! BANK14_STA_OFF_EN - Bank14 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK14_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK14_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK14_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED1_MASK      (0x20000000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED1_SHIFT     (29U)
+/*! RESERVED1 - Reserved 1 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED1(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED1_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED1_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_BANK15_STA_OFF_EN_MASK (0x40000000U)
+#define APU_LMU_CPU1_STA_CFG_BANK15_STA_OFF_EN_SHIFT (30U)
+/*! BANK15_STA_OFF_EN - Bank15 STA Off Enable */
+#define APU_LMU_CPU1_STA_CFG_BANK15_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_BANK15_STA_OFF_EN_SHIFT)) & APU_LMU_CPU1_STA_CFG_BANK15_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU1_STA_CFG_RESERVED0_MASK      (0x80000000U)
+#define APU_LMU_CPU1_STA_CFG_RESERVED0_SHIFT     (31U)
+/*! RESERVED0 - Reserved 0 */
+#define APU_LMU_CPU1_STA_CFG_RESERVED0(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_CFG_RESERVED0_SHIFT)) & APU_LMU_CPU1_STA_CFG_RESERVED0_MASK)
+/*! @} */
+
+/*! @name LMU_CPU1_STA_STATUS1 - LMU CPU1 STA Status 1 */
+/*! @{ */
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_REP_DONE_MASK (0x1U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_REP_DONE_SHIFT (0U)
+/*! BANK0_FSM_ST_REP_DONE - Bank0 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_MASK (0xEU)
+#define APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_SHIFT (1U)
+/*! BANK0_FSM_ST - Bank0 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK0_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_REP_DONE_MASK (0x10U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_REP_DONE_SHIFT (4U)
+/*! BANK1_FSM_ST_REP_DONE - Bank1FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_MASK (0xE0U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_SHIFT (5U)
+/*! BANK1_FSM_ST - Bank1 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK1_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_REP_DONE_MASK (0x100U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_REP_DONE_SHIFT (8U)
+/*! BANK2_FSM_ST_REP_DONE - Bank2 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_MASK (0xE00U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_SHIFT (9U)
+/*! BANK2_FSM_ST - Bank2 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK2_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_REP_DONE_MASK (0x1000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_REP_DONE_SHIFT (12U)
+/*! BANK3_FSM_ST_REP_DONE - Bank3 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_MASK (0xE000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_SHIFT (13U)
+/*! BANK3_FSM_ST - Bank3 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK3_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_REP_DONE_MASK (0x10000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_REP_DONE_SHIFT (16U)
+/*! BANK4_FSM_ST_REP_DONE - Bank4 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_MASK (0xE0000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_SHIFT (17U)
+/*! BANK4_FSM_ST - Bank4 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK4_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_REP_DONE_MASK (0x100000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_REP_DONE_SHIFT (20U)
+/*! BANK5_FSM_ST_REP_DONE - Bank5 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_MASK (0xE00000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_SHIFT (21U)
+/*! BANK5_FSM_ST - Bank5 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK5_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_REP_DONE_MASK (0x1000000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_REP_DONE_SHIFT (24U)
+/*! BANK6_FSM_ST_REP_DONE - Bank6 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_MASK (0xE000000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_SHIFT (25U)
+/*! BANK6_FSM_ST - Bank6 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK6_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_REP_DONE_MASK (0x10000000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_REP_DONE_SHIFT (28U)
+/*! BANK7_FSM_ST_REP_DONE - Bank7 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_MASK (0xE0000000U)
+#define APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_SHIFT (29U)
+/*! BANK7_FSM_ST - Bank7 FSM St */
+#define APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS1_BANK7_FSM_ST_MASK)
+/*! @} */
+
+/*! @name LMU_CPU1_STA_STATUS2 - LMU CPU1 STA Status 2 */
+/*! @{ */
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_REP_DONE_MASK (0x1U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_REP_DONE_SHIFT (0U)
+/*! BANK8_FSM_ST_REP_DONE - Bank8 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_MASK (0xEU)
+#define APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_SHIFT (1U)
+/*! BANK8_FSM_ST - Bank8 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK8_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_REP_DONE_MASK (0x10U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_REP_DONE_SHIFT (4U)
+/*! BANK9_FSM_ST_REP_DONE - Bank9 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_MASK (0xE0U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_SHIFT (5U)
+/*! BANK9_FSM_ST - Bank9 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK9_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_REP_DONE_MASK (0x100U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_REP_DONE_SHIFT (8U)
+/*! BANK10_FSM_ST_REP_DONE - Bank10 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_MASK (0xE00U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_SHIFT (9U)
+/*! BANK10_FSM_ST - Bank10 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK10_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_REP_DONE_MASK (0x1000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_REP_DONE_SHIFT (12U)
+/*! BANK11_FSM_ST_REP_DONE - Bank11 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_MASK (0xE000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_SHIFT (13U)
+/*! BANK11_FSM_ST - Bank11 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK11_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_REP_DONE_MASK (0x10000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_REP_DONE_SHIFT (16U)
+/*! BANK12_FSM_ST_REP_DONE - Bank12 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_MASK (0xE0000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_SHIFT (17U)
+/*! BANK12_FSM_ST - Bank12 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK12_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_REP_DONE_MASK (0x100000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_REP_DONE_SHIFT (20U)
+/*! BANK13_FSM_ST_REP_DONE - Bank13 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_MASK (0xE00000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_SHIFT (21U)
+/*! BANK13_FSM_ST - Bank13 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK13_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_REP_DONE_MASK (0x1000000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_REP_DONE_SHIFT (24U)
+/*! BANK14_FSM_ST_REP_DONE - Bank14 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_MASK (0xE000000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_SHIFT (25U)
+/*! BANK14_FSM_ST - Bank14 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK14_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_REP_DONE_MASK (0x10000000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_REP_DONE_SHIFT (28U)
+/*! BANK15_FSM_ST_REP_DONE - Bank15 FSM St Rep Done */
+#define APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_MASK (0xE0000000U)
+#define APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_SHIFT (29U)
+/*! BANK15_FSM_ST - Bank15 FSM St */
+#define APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_SHIFT)) & APU_LMU_CPU1_STA_STATUS2_BANK15_FSM_ST_MASK)
+/*! @} */
+
+/*! @name LMU_CPU1_DYN_CTRL - LMU CPU1 Dynamic Control */
+/*! @{ */
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_MODE_EN_MASK (0x1U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_MODE_EN_SHIFT (0U)
+/*! BANK0_DYN_MODE_EN - Bank0 Dynamic Mode Enable */
+#define APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_MODE_EN_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_MODE_EN_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_PD_MASK  (0x2U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_PD_SHIFT (1U)
+/*! BANK0_DYN_PD - Bank0 Dynamic Powerdown */
+#define APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_PD(x)    (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_PD_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK0_DYN_PD_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED3_MASK     (0xCU)
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED3_SHIFT    (2U)
+/*! RESERVED3 - Reserved 3 */
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED3(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_RESERVED3_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_RESERVED3_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_MODE_EN_MASK (0x10U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_MODE_EN_SHIFT (4U)
+/*! BANK1_DYN_MODE_EN - Bank1 Dynamic Mode Enable */
+#define APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_MODE_EN_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_MODE_EN_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_PD_MASK  (0x20U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_PD_SHIFT (5U)
+/*! BANK1_DYN_PD - Bank1 Dynamic Powerdown */
+#define APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_PD(x)    (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_PD_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK1_DYN_PD_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED2_MASK     (0xC0U)
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED2_SHIFT    (6U)
+/*! RESERVED2 - Reserved 2 */
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED2(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_RESERVED2_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_RESERVED2_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_MODE_EN_MASK (0x100U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_MODE_EN_SHIFT (8U)
+/*! BANK2_DYN_MODE_EN - Bank2 Dynamic Mode Enable */
+#define APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_MODE_EN_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_MODE_EN_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_PD_MASK  (0x200U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_PD_SHIFT (9U)
+/*! BANK2_DYN_PD - Bank2 Dynamic Powerdown */
+#define APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_PD(x)    (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_PD_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK2_DYN_PD_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED1_MASK     (0xC00U)
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED1_SHIFT    (10U)
+/*! RESERVED1 - Reserved 1 */
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED1(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_RESERVED1_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_RESERVED1_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_MODE_EN_MASK (0x1000U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_MODE_EN_SHIFT (12U)
+/*! BANK3_DYN_MODE_EN - Bank3 Dynamic Mode Enable */
+#define APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_MODE_EN_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_MODE_EN_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_PD_MASK  (0x2000U)
+#define APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_PD_SHIFT (13U)
+/*! BANK3_DYN_PD - Bank3 Dynamic Powerdown */
+#define APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_PD(x)    (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_PD_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_BANK3_DYN_PD_MASK)
+
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED0_MASK     (0xFFFFC000U)
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED0_SHIFT    (14U)
+/*! RESERVED0 - Reserved 0 */
+#define APU_LMU_CPU1_DYN_CTRL_RESERVED0(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_CTRL_RESERVED0_SHIFT)) & APU_LMU_CPU1_DYN_CTRL_RESERVED0_MASK)
+/*! @} */
+
+/*! @name LMU_CPU1_DYN_STATUS - LMU CPU1 Dynamic Status */
+/*! @{ */
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_REQ_MASK (0x1U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_REQ_SHIFT (0U)
+/*! BANK0_DYN_REP_REQ - Bank0 Dynamic Rep Request */
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_REQ_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_REQ_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_MASK (0x2U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_SHIFT (1U)
+/*! BANK0_DYN_REP - Bank0 Dynamic Rep */
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK0_DYN_REP_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_FSM_ST_MASK (0xCU)
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_FSM_ST_SHIFT (2U)
+/*! BANK0_FSM_ST - Bank0 FSM St */
+#define APU_LMU_CPU1_DYN_STATUS_BANK0_FSM_ST(x)  (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK0_FSM_ST_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK0_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_REQ_MASK (0x10U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_REQ_SHIFT (4U)
+/*! BANK1_DYN_REP_REQ - Bank1 Dynamic Rep Request */
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_REQ_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_REQ_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_MASK (0x20U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_SHIFT (5U)
+/*! BANK1_DYN_REP - Bank1 Dynamic Rep */
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK1_DYN_REP_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_FSM_ST_MASK (0xC0U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_FSM_ST_SHIFT (6U)
+/*! BANK1_FSM_ST - Bank1 FSM St */
+#define APU_LMU_CPU1_DYN_STATUS_BANK1_FSM_ST(x)  (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK1_FSM_ST_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK1_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_REQ_MASK (0x100U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_REQ_SHIFT (8U)
+/*! BANK2_DYN_REP_REQ - Bank2 Dynamic Rep Request */
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_REQ_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_REQ_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_MASK (0x200U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_SHIFT (9U)
+/*! BANK2_DYN_REP - Bank2 Dynamic Rep */
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK2_DYN_REP_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_FSM_ST_MASK (0xC00U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_FSM_ST_SHIFT (10U)
+/*! BANK2_FSM_ST - Bank2 FSM St */
+#define APU_LMU_CPU1_DYN_STATUS_BANK2_FSM_ST(x)  (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK2_FSM_ST_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK2_FSM_ST_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_REQ_MASK (0x1000U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_REQ_SHIFT (12U)
+/*! BANK3_DYN_REP_REQ - Bank3 Dynamic Rep Request */
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_REQ_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_REQ_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_MASK (0x2000U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_SHIFT (13U)
+/*! BANK3_DYN_REP - Bank3 Dynamic Rep */
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK3_DYN_REP_MASK)
+
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_FSM_ST_MASK (0xC000U)
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_FSM_ST_SHIFT (14U)
+/*! BANK3_FSM_ST - Bank3 FSM St */
+#define APU_LMU_CPU1_DYN_STATUS_BANK3_FSM_ST(x)  (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU1_DYN_STATUS_BANK3_FSM_ST_SHIFT)) & APU_LMU_CPU1_DYN_STATUS_BANK3_FSM_ST_MASK)
+/*! @} */
+
+/*! @name LMU_CPU2_STA_CFG - LMU CPU2 STA Configuration */
+/*! @{ */
+
+#define APU_LMU_CPU2_STA_CFG_BANK0_STA_OFF_EN_MASK (0x1U)
+#define APU_LMU_CPU2_STA_CFG_BANK0_STA_OFF_EN_SHIFT (0U)
+/*! BANK0_STA_OFF_EN - Bank0 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK0_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK0_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK0_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED7_MASK      (0x2U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED7_SHIFT     (1U)
+/*! RESERVED7 - Reserved 7 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED7(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED7_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED7_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_BANK1_STA_OFF_EN_MASK (0x4U)
+#define APU_LMU_CPU2_STA_CFG_BANK1_STA_OFF_EN_SHIFT (2U)
+/*! BANK1_STA_OFF_EN - Bank1 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK1_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK1_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK1_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED6_MASK      (0x8U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED6_SHIFT     (3U)
+/*! RESERVED6 - Reserved 6 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED6(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED6_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED6_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_BANK2_STA_OFF_EN_MASK (0x10U)
+#define APU_LMU_CPU2_STA_CFG_BANK2_STA_OFF_EN_SHIFT (4U)
+/*! BANK2_STA_OFF_EN - Bank2 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK2_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK2_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK2_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED5_MASK      (0x20U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED5_SHIFT     (5U)
+/*! RESERVED5 - Reserved 5 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED5(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED5_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED5_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_BANK3_STA_OFF_EN_MASK (0x40U)
+#define APU_LMU_CPU2_STA_CFG_BANK3_STA_OFF_EN_SHIFT (6U)
+/*! BANK3_STA_OFF_EN - Bank3 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK3_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK3_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK3_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED4_MASK      (0x80U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED4_SHIFT     (7U)
+/*! RESERVED4 - Reserved 4 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED4(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED4_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED4_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_BANK4_STA_OFF_EN_MASK (0x100U)
+#define APU_LMU_CPU2_STA_CFG_BANK4_STA_OFF_EN_SHIFT (8U)
+/*! BANK4_STA_OFF_EN - Bank4 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK4_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK4_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK4_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED3_MASK      (0x200U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED3_SHIFT     (9U)
+/*! RESERVED3 - Reserved 3 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED3(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED3_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED3_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_BANK5_STA_OFF_EN_MASK (0x400U)
+#define APU_LMU_CPU2_STA_CFG_BANK5_STA_OFF_EN_SHIFT (10U)
+/*! BANK5_STA_OFF_EN - Bank5 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK5_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK5_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK5_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED2_MASK      (0x800U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED2_SHIFT     (11U)
+/*! RESERVED2 - Reserved 2 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED2(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED2_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED2_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_BANK6_STA_OFF_EN_MASK (0x1000U)
+#define APU_LMU_CPU2_STA_CFG_BANK6_STA_OFF_EN_SHIFT (12U)
+/*! BANK6_STA_OFF_EN - Bank6 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK6_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK6_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK6_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED1_MASK      (0x2000U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED1_SHIFT     (13U)
+/*! RESERVED1 - Reserved 1 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED1(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED1_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED1_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_BANK7_STA_OFF_EN_MASK (0x4000U)
+#define APU_LMU_CPU2_STA_CFG_BANK7_STA_OFF_EN_SHIFT (14U)
+/*! BANK7_STA_OFF_EN - Bank7 STA Off Enable */
+#define APU_LMU_CPU2_STA_CFG_BANK7_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_BANK7_STA_OFF_EN_SHIFT)) & APU_LMU_CPU2_STA_CFG_BANK7_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU2_STA_CFG_RESERVED0_MASK      (0xFFFF8000U)
+#define APU_LMU_CPU2_STA_CFG_RESERVED0_SHIFT     (15U)
+/*! RESERVED0 - Reserved 0 */
+#define APU_LMU_CPU2_STA_CFG_RESERVED0(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_CFG_RESERVED0_SHIFT)) & APU_LMU_CPU2_STA_CFG_RESERVED0_MASK)
+/*! @} */
+
+/*! @name LMU_CPU2_STA_STATUS1 - LMU CPU2 STA Status 1 */
+/*! @{ */
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_REP_DONE_MASK (0x1U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_REP_DONE_SHIFT (0U)
+/*! BANK0_FSM_ST_REP_DONE - Bank0 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_MASK (0xEU)
+#define APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_SHIFT (1U)
+/*! BANK0_FSM_ST - Bank0 FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK0_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_REP_DONE_MASK (0x10U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_REP_DONE_SHIFT (4U)
+/*! BANK1_FSM_ST_REP_DONE - Bank1 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_MASK (0xE0U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_SHIFT (5U)
+/*! BANK1_FSM_ST - Bank1 FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK1_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_REP_DONE_MASK (0x100U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_REP_DONE_SHIFT (8U)
+/*! BANK2_FSM_ST_REP_DONE - Bank2 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_MASK (0xE00U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_SHIFT (9U)
+/*! BANK2_FSM_ST - Bank2FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK2_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_REP_DONE_MASK (0x1000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_REP_DONE_SHIFT (12U)
+/*! BANK3_FSM_ST_REP_DONE - Bank3 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_MASK (0xE000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_SHIFT (13U)
+/*! BANK3_FSM_ST - Bank3 FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK3_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_REP_DONE_MASK (0x10000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_REP_DONE_SHIFT (16U)
+/*! BANK4_FSM_ST_REP_DONE - Bank4 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_MASK (0xE0000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_SHIFT (17U)
+/*! BANK4_FSM_ST - Bank4 FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK4_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_REP_DONE_MASK (0x100000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_REP_DONE_SHIFT (20U)
+/*! BANK5_FSM_ST_REP_DONE - Bank5 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_MASK (0xE00000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_SHIFT (21U)
+/*! BANK5_FSM_ST - Bank5 FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK5_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_REP_DONE_MASK (0x1000000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_REP_DONE_SHIFT (24U)
+/*! BANK6_FSM_ST_REP_DONE - Bank6 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_MASK (0xE000000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_SHIFT (25U)
+/*! BANK6_FSM_ST - Bank6 FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK6_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_REP_DONE_MASK (0x10000000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_REP_DONE_SHIFT (28U)
+/*! BANK7_FSM_ST_REP_DONE - Bank7 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_MASK (0xE0000000U)
+#define APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_SHIFT (29U)
+/*! BANK7_FSM_ST - Bank7 FSM St */
+#define APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS1_BANK7_FSM_ST_MASK)
+/*! @} */
+
+/*! @name LMU_CPU3_STA_CFG - LMU CPU3 STA Configuration */
+/*! @{ */
+
+#define APU_LMU_CPU3_STA_CFG_BANK0_STA_OFF_EN_MASK (0x1U)
+#define APU_LMU_CPU3_STA_CFG_BANK0_STA_OFF_EN_SHIFT (0U)
+/*! BANK0_STA_OFF_EN - Bank0 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK0_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK0_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK0_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED7_MASK      (0x2U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED7_SHIFT     (1U)
+/*! RESERVED7 - Reserved 7 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED7(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED7_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED7_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_BANK1_STA_OFF_EN_MASK (0x4U)
+#define APU_LMU_CPU3_STA_CFG_BANK1_STA_OFF_EN_SHIFT (2U)
+/*! BANK1_STA_OFF_EN - Bank1 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK1_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK1_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK1_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED6_MASK      (0x8U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED6_SHIFT     (3U)
+/*! RESERVED6 - Reserved 6 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED6(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED6_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED6_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_BANK2_STA_OFF_EN_MASK (0x10U)
+#define APU_LMU_CPU3_STA_CFG_BANK2_STA_OFF_EN_SHIFT (4U)
+/*! BANK2_STA_OFF_EN - Bank2 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK2_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK2_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK2_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED5_MASK      (0x20U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED5_SHIFT     (5U)
+/*! RESERVED5 - Reserved 5 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED5(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED5_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED5_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_BANK3_STA_OFF_EN_MASK (0x40U)
+#define APU_LMU_CPU3_STA_CFG_BANK3_STA_OFF_EN_SHIFT (6U)
+/*! BANK3_STA_OFF_EN - Bank3 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK3_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK3_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK3_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED4_MASK      (0x80U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED4_SHIFT     (7U)
+/*! RESERVED4 - Reserved 4 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED4(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED4_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED4_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_BANK4_STA_OFF_EN_MASK (0x100U)
+#define APU_LMU_CPU3_STA_CFG_BANK4_STA_OFF_EN_SHIFT (8U)
+/*! BANK4_STA_OFF_EN - Bank4 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK4_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK4_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK4_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED3_MASK      (0x200U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED3_SHIFT     (9U)
+/*! RESERVED3 - Reserved 3 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED3(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED3_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED3_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_BANK5_STA_OFF_EN_MASK (0x400U)
+#define APU_LMU_CPU3_STA_CFG_BANK5_STA_OFF_EN_SHIFT (10U)
+/*! BANK5_STA_OFF_EN - Bank5 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK5_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK5_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK5_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED2_MASK      (0x800U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED2_SHIFT     (11U)
+/*! RESERVED2 - Reserved 2 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED2(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED2_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED2_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_BANK6_STA_OFF_EN_MASK (0x1000U)
+#define APU_LMU_CPU3_STA_CFG_BANK6_STA_OFF_EN_SHIFT (12U)
+/*! BANK6_STA_OFF_EN - Bank6 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK6_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK6_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK6_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED1_MASK      (0x2000U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED1_SHIFT     (13U)
+/*! RESERVED1 - Reserved 1 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED1(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED1_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED1_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_BANK7_STA_OFF_EN_MASK (0x4000U)
+#define APU_LMU_CPU3_STA_CFG_BANK7_STA_OFF_EN_SHIFT (14U)
+/*! BANK7_STA_OFF_EN - Bank7 STA Off Enable */
+#define APU_LMU_CPU3_STA_CFG_BANK7_STA_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_BANK7_STA_OFF_EN_SHIFT)) & APU_LMU_CPU3_STA_CFG_BANK7_STA_OFF_EN_MASK)
+
+#define APU_LMU_CPU3_STA_CFG_RESERVED0_MASK      (0xFFFF8000U)
+#define APU_LMU_CPU3_STA_CFG_RESERVED0_SHIFT     (15U)
+/*! RESERVED0 - Reserved 0 */
+#define APU_LMU_CPU3_STA_CFG_RESERVED0(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_CFG_RESERVED0_SHIFT)) & APU_LMU_CPU3_STA_CFG_RESERVED0_MASK)
+/*! @} */
+
+/*! @name LMU_CPU3_STA_STATUS1 - LMU CPU3 STA Status 1 */
+/*! @{ */
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_REP_DONE_MASK (0x1U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_REP_DONE_SHIFT (0U)
+/*! BANK0_FSM_ST_REP_DONE - Bank0 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_MASK (0xEU)
+#define APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_SHIFT (1U)
+/*! BANK0_FSM_ST - Bank0 FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK0_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_REP_DONE_MASK (0x10U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_REP_DONE_SHIFT (4U)
+/*! BANK1_FSM_ST_REP_DONE - Bank1 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_MASK (0xE0U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_SHIFT (5U)
+/*! BANK1_FSM_ST - Bank1 FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK1_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_REP_DONE_MASK (0x100U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_REP_DONE_SHIFT (8U)
+/*! BANK2_FSM_ST_REP_DONE - Bank2 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_MASK (0xE00U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_SHIFT (9U)
+/*! BANK2_FSM_ST - Bank2FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK2_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_REP_DONE_MASK (0x1000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_REP_DONE_SHIFT (12U)
+/*! BANK3_FSM_ST_REP_DONE - Bank3 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_MASK (0xE000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_SHIFT (13U)
+/*! BANK3_FSM_ST - Bank3 FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK3_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_REP_DONE_MASK (0x10000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_REP_DONE_SHIFT (16U)
+/*! BANK4_FSM_ST_REP_DONE - Bank4 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_MASK (0xE0000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_SHIFT (17U)
+/*! BANK4_FSM_ST - Bank4 FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK4_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_REP_DONE_MASK (0x100000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_REP_DONE_SHIFT (20U)
+/*! BANK5_FSM_ST_REP_DONE - Bank5 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_MASK (0xE00000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_SHIFT (21U)
+/*! BANK5_FSM_ST - Bank5 FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK5_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_REP_DONE_MASK (0x1000000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_REP_DONE_SHIFT (24U)
+/*! BANK6_FSM_ST_REP_DONE - Bank6 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_MASK (0xE000000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_SHIFT (25U)
+/*! BANK6_FSM_ST - Bank6 FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK6_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_REP_DONE_MASK (0x10000000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_REP_DONE_SHIFT (28U)
+/*! BANK7_FSM_ST_REP_DONE - Bank7 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_MASK (0xE0000000U)
+#define APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_SHIFT (29U)
+/*! BANK7_FSM_ST - Bank7 FSM St */
+#define APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS1_BANK7_FSM_ST_MASK)
+/*! @} */
+
+/*! @name LMU_G2BIST_CTRL - LMU G2BIST Control */
+/*! @{ */
+
+#define APU_LMU_G2BIST_CTRL_LMU_G2BIST_MODE_MASK (0x1FU)
+#define APU_LMU_G2BIST_CTRL_LMU_G2BIST_MODE_SHIFT (0U)
+/*! LMU_G2BIST_MODE - 1 = fuse load mode, default mode when powered up. All repairable memories will be repaired by g2bist engine */
+#define APU_LMU_G2BIST_CTRL_LMU_G2BIST_MODE(x)   (((uint32_t)(((uint32_t)(x)) << APU_LMU_G2BIST_CTRL_LMU_G2BIST_MODE_SHIFT)) & APU_LMU_G2BIST_CTRL_LMU_G2BIST_MODE_MASK)
+
+#define APU_LMU_G2BIST_CTRL_DISABLE_STA_REPAIR_MASK (0x20000000U)
+#define APU_LMU_G2BIST_CTRL_DISABLE_STA_REPAIR_SHIFT (29U)
+/*! DISABLE_STA_REPAIR - 1= disable static memory repair */
+#define APU_LMU_G2BIST_CTRL_DISABLE_STA_REPAIR(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_G2BIST_CTRL_DISABLE_STA_REPAIR_SHIFT)) & APU_LMU_G2BIST_CTRL_DISABLE_STA_REPAIR_MASK)
+
+#define APU_LMU_G2BIST_CTRL_DISABLE_DYN_REPAIR_MASK (0x40000000U)
+#define APU_LMU_G2BIST_CTRL_DISABLE_DYN_REPAIR_SHIFT (30U)
+/*! DISABLE_DYN_REPAIR - 1= disable dynamic memory repair */
+#define APU_LMU_G2BIST_CTRL_DISABLE_DYN_REPAIR(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_G2BIST_CTRL_DISABLE_DYN_REPAIR_SHIFT)) & APU_LMU_G2BIST_CTRL_DISABLE_DYN_REPAIR_MASK)
+/*! @} */
+
+/*! @name LMU_STATUS - LMU Status */
+/*! @{ */
+
+#define APU_LMU_STATUS_REPAIR_FSM_ST_MASK        (0xFU)
+#define APU_LMU_STATUS_REPAIR_FSM_ST_SHIFT       (0U)
+/*! REPAIR_FSM_ST - Repair FSM St */
+#define APU_LMU_STATUS_REPAIR_FSM_ST(x)          (((uint32_t)(((uint32_t)(x)) << APU_LMU_STATUS_REPAIR_FSM_ST_SHIFT)) & APU_LMU_STATUS_REPAIR_FSM_ST_MASK)
+
+#define APU_LMU_STATUS_NXT_ST_MASK               (0xF0U)
+#define APU_LMU_STATUS_NXT_ST_SHIFT              (4U)
+/*! NXT_ST - NXT St */
+#define APU_LMU_STATUS_NXT_ST(x)                 (((uint32_t)(((uint32_t)(x)) << APU_LMU_STATUS_NXT_ST_SHIFT)) & APU_LMU_STATUS_NXT_ST_MASK)
+
+#define APU_LMU_STATUS_LMU_G2BIST_MODE_MASK      (0xF00U)
+#define APU_LMU_STATUS_LMU_G2BIST_MODE_SHIFT     (8U)
+/*! LMU_G2BIST_MODE - LMU_g to BIST Mode */
+#define APU_LMU_STATUS_LMU_G2BIST_MODE(x)        (((uint32_t)(((uint32_t)(x)) << APU_LMU_STATUS_LMU_G2BIST_MODE_SHIFT)) & APU_LMU_STATUS_LMU_G2BIST_MODE_MASK)
+
+#define APU_LMU_STATUS_LMU_G2BIST_PWRDMN_RPR_REQ_MASK (0xFF000U)
+#define APU_LMU_STATUS_LMU_G2BIST_PWRDMN_RPR_REQ_SHIFT (12U)
+/*! LMU_G2BIST_PWRDMN_RPR_REQ - LMU_g to BIST Powerdown RPR Request */
+#define APU_LMU_STATUS_LMU_G2BIST_PWRDMN_RPR_REQ(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_STATUS_LMU_G2BIST_PWRDMN_RPR_REQ_SHIFT)) & APU_LMU_STATUS_LMU_G2BIST_PWRDMN_RPR_REQ_MASK)
+
+#define APU_LMU_STATUS_LMU_G2BIST_START_MASK     (0x100000U)
+#define APU_LMU_STATUS_LMU_G2BIST_START_SHIFT    (20U)
+/*! LMU_G2BIST_START - LMU_g to BIST Start */
+#define APU_LMU_STATUS_LMU_G2BIST_START(x)       (((uint32_t)(((uint32_t)(x)) << APU_LMU_STATUS_LMU_G2BIST_START_SHIFT)) & APU_LMU_STATUS_LMU_G2BIST_START_MASK)
+/*! @} */
+
+/*! @name LMU_STA_CFG_MASK - LMU STA Configuration Mask */
+/*! @{ */
+
+#define APU_LMU_STA_CFG_MASK_STA_CFG_MASK_MASK   (0xFFU)
+#define APU_LMU_STA_CFG_MASK_STA_CFG_MASK_SHIFT  (0U)
+/*! STA_CFG_MASK - STA Configuration Mask */
+#define APU_LMU_STA_CFG_MASK_STA_CFG_MASK(x)     (((uint32_t)(((uint32_t)(x)) << APU_LMU_STA_CFG_MASK_STA_CFG_MASK_SHIFT)) & APU_LMU_STA_CFG_MASK_STA_CFG_MASK_MASK)
+/*! @} */
+
+/*! @name LMU_CPU2_STA_STATUS2 - LMU CPU2 STA Status 2 */
+/*! @{ */
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_REP_DONE_MASK (0x1U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_REP_DONE_SHIFT (0U)
+/*! BANK8_FSM_ST_REP_DONE - Bank8 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_MASK (0xEU)
+#define APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_SHIFT (1U)
+/*! BANK8_FSM_ST - Bank8 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK8_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_REP_DONE_MASK (0x10U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_REP_DONE_SHIFT (4U)
+/*! BANK9_FSM_ST_REP_DONE - Bank9 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_MASK (0xE0U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_SHIFT (5U)
+/*! BANK9_FSM_ST - Bank9 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK9_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_REP_DONE_MASK (0x100U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_REP_DONE_SHIFT (8U)
+/*! BANK10_FSM_ST_REP_DONE - Bank10 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_MASK (0xE00U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_SHIFT (9U)
+/*! BANK10_FSM_ST - Bank10 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK10_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_REP_DONE_MASK (0x1000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_REP_DONE_SHIFT (12U)
+/*! BANK11_FSM_ST_REP_DONE - Bank11 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_MASK (0xE000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_SHIFT (13U)
+/*! BANK11_FSM_ST - Bank11 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK11_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_REP_DONE_MASK (0x10000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_REP_DONE_SHIFT (16U)
+/*! BANK12_FSM_ST_REP_DONE - Bank12 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_MASK (0xE0000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_SHIFT (17U)
+/*! BANK12_FSM_ST - Bank12 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK12_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_REP_DONE_MASK (0x100000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_REP_DONE_SHIFT (20U)
+/*! BANK13_FSM_ST_REP_DONE - Bank13 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_MASK (0xE00000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_SHIFT (21U)
+/*! BANK13_FSM_ST - Bank13 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK13_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_REP_DONE_MASK (0x1000000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_REP_DONE_SHIFT (24U)
+/*! BANK14_FSM_ST_REP_DONE - Bank14 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_MASK (0xE000000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_SHIFT (25U)
+/*! BANK14_FSM_ST - Bank14 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK14_FSM_ST_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_REP_DONE_MASK (0x10000000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_REP_DONE_SHIFT (28U)
+/*! BANK15_FSM_ST_REP_DONE - Bank15 FSM St Rep Done */
+#define APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_MASK (0xE0000000U)
+#define APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_SHIFT (29U)
+/*! BANK15_FSM_ST - Bank15 FSM St */
+#define APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_SHIFT)) & APU_LMU_CPU2_STA_STATUS2_BANK15_FSM_ST_MASK)
+/*! @} */
+
+/*! @name LMU_CPU3_STA_STATUS2 - LMU CPU3 STA Status 2 */
+/*! @{ */
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_REP_DONE_MASK (0x1U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_REP_DONE_SHIFT (0U)
+/*! BANK8_FSM_ST_REP_DONE - Bank8 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_MASK (0xEU)
+#define APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_SHIFT (1U)
+/*! BANK8_FSM_ST - Bank8 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK8_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_REP_DONE_MASK (0x10U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_REP_DONE_SHIFT (4U)
+/*! BANK9_FSM_ST_REP_DONE - Bank9 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_MASK (0xE0U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_SHIFT (5U)
+/*! BANK9_FSM_ST - Bank9 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK9_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_REP_DONE_MASK (0x100U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_REP_DONE_SHIFT (8U)
+/*! BANK10_FSM_ST_REP_DONE - Bank10 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_MASK (0xE00U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_SHIFT (9U)
+/*! BANK10_FSM_ST - Bank10 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK10_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_REP_DONE_MASK (0x1000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_REP_DONE_SHIFT (12U)
+/*! BANK11_FSM_ST_REP_DONE - Bank11 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_MASK (0xE000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_SHIFT (13U)
+/*! BANK11_FSM_ST - Bank11 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK11_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_REP_DONE_MASK (0x10000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_REP_DONE_SHIFT (16U)
+/*! BANK12_FSM_ST_REP_DONE - Bank12 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_MASK (0xE0000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_SHIFT (17U)
+/*! BANK12_FSM_ST - Bank12 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK12_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_REP_DONE_MASK (0x100000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_REP_DONE_SHIFT (20U)
+/*! BANK13_FSM_ST_REP_DONE - Bank13 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_MASK (0xE00000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_SHIFT (21U)
+/*! BANK13_FSM_ST - Bank13 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK13_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_REP_DONE_MASK (0x1000000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_REP_DONE_SHIFT (24U)
+/*! BANK14_FSM_ST_REP_DONE - Bank14 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_MASK (0xE000000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_SHIFT (25U)
+/*! BANK14_FSM_ST - Bank14 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK14_FSM_ST_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_REP_DONE_MASK (0x10000000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_REP_DONE_SHIFT (28U)
+/*! BANK15_FSM_ST_REP_DONE - Bank15 FSM St Rep Done */
+#define APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_REP_DONE(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_REP_DONE_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_REP_DONE_MASK)
+
+#define APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_MASK (0xE0000000U)
+#define APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_SHIFT (29U)
+/*! BANK15_FSM_ST - Bank15 FSM St */
+#define APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_SHIFT)) & APU_LMU_CPU3_STA_STATUS2_BANK15_FSM_ST_MASK)
+/*! @} */
+
+/*! @name CPU3_HOST_WKUP_MASK - CPU3 Host Wakeup Mask */
+/*! @{ */
+
+#define APU_CPU3_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK (0xFFFFU)
+#define APU_CPU3_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT (0U)
+/*! HOST_WKUP_MASK - Host Wakeup Mask */
+#define APU_CPU3_HOST_WKUP_MASK_HOST_WKUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_HOST_WKUP_MASK_HOST_WKUP_MASK_SHIFT)) & APU_CPU3_HOST_WKUP_MASK_HOST_WKUP_MASK_MASK)
+/*! @} */
+
+/*! @name CPU3_HOST_WKUP_POL - CPU3 Host Wakeup Polarity */
+/*! @{ */
+
+#define APU_CPU3_HOST_WKUP_POL_HOST_WKUP_POL_MASK (0xFFFFU)
+#define APU_CPU3_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT (0U)
+/*! HOST_WKUP_POL - Host Wakeup Polarity */
+#define APU_CPU3_HOST_WKUP_POL_HOST_WKUP_POL(x)  (((uint32_t)(((uint32_t)(x)) << APU_CPU3_HOST_WKUP_POL_HOST_WKUP_POL_SHIFT)) & APU_CPU3_HOST_WKUP_POL_HOST_WKUP_POL_MASK)
+/*! @} */
+
+/*! @name CPU3_HOST_WKUP_CTRL - CPU3 Host Wakeup Control */
+/*! @{ */
+
+#define APU_CPU3_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK (0xFFFFU)
+#define APU_CPU3_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT (0U)
+/*! HOST_WKUP_CTRL - Host Wakeup Control */
+#define APU_CPU3_HOST_WKUP_CTRL_HOST_WKUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_HOST_WKUP_CTRL_HOST_WKUP_CTRL_SHIFT)) & APU_CPU3_HOST_WKUP_CTRL_HOST_WKUP_CTRL_MASK)
+
+#define APU_CPU3_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK (0xFFFF0000U)
+#define APU_CPU3_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT (16U)
+/*! HOST_INTR_MASK - Host Interrupt Mask */
+#define APU_CPU3_HOST_WKUP_CTRL_HOST_INTR_MASK(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_HOST_WKUP_CTRL_HOST_INTR_MASK_SHIFT)) & APU_CPU3_HOST_WKUP_CTRL_HOST_INTR_MASK_MASK)
+/*! @} */
+
+/*! @name CPU3_CTRL - CPU3 Control */
+/*! @{ */
+
+#define APU_CPU3_CTRL_CPU3_MSG_RDY_MASK_MASK     (0x1U)
+#define APU_CPU3_CTRL_CPU3_MSG_RDY_MASK_SHIFT    (0U)
+/*! CPU3_MSG_RDY_MASK - CPU3 Message Ready Mask */
+#define APU_CPU3_CTRL_CPU3_MSG_RDY_MASK(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU3_CTRL_CPU3_MSG_RDY_MASK_SHIFT)) & APU_CPU3_CTRL_CPU3_MSG_RDY_MASK_MASK)
+
+#define APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_VAL_MASK (0x4U)
+#define APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_VAL_SHIFT (2U)
+/*! CPU3_CP15_SLP_BYPASS_VAL - CPU3 CP15 Sleep Bypass Value */
+#define APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_VAL_SHIFT)) & APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_VAL_MASK)
+
+#define APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_EN_MASK (0x8U)
+#define APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_EN_SHIFT (3U)
+/*! CPU3_CP15_SLP_BYPASS_EN - CPU3 CP15 Sleep Bypass Enable */
+#define APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_EN_SHIFT)) & APU_CPU3_CTRL_CPU3_CP15_SLP_BYPASS_EN_MASK)
+
+#define APU_CPU3_CTRL_SOC_USE_REF_ONLY_MASK      (0x10U)
+#define APU_CPU3_CTRL_SOC_USE_REF_ONLY_SHIFT     (4U)
+/*! SOC_USE_REF_ONLY - SoC Use Ref Only */
+#define APU_CPU3_CTRL_SOC_USE_REF_ONLY(x)        (((uint32_t)(((uint32_t)(x)) << APU_CPU3_CTRL_SOC_USE_REF_ONLY_SHIFT)) & APU_CPU3_CTRL_SOC_USE_REF_ONLY_MASK)
+
+#define APU_CPU3_CTRL_GENERIC_TIMER_EN2_MASK     (0x20U)
+#define APU_CPU3_CTRL_GENERIC_TIMER_EN2_SHIFT    (5U)
+/*! GENERIC_TIMER_EN2 - Generic Timer Enable 2 */
+#define APU_CPU3_CTRL_GENERIC_TIMER_EN2(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU3_CTRL_GENERIC_TIMER_EN2_SHIFT)) & APU_CPU3_CTRL_GENERIC_TIMER_EN2_MASK)
+
+#define APU_CPU3_CTRL_APU_SUBSYS3_HOST_MASK      (0x70000U)
+#define APU_CPU3_CTRL_APU_SUBSYS3_HOST_SHIFT     (16U)
+/*! APU_SUBSYS3_HOST - APU Subsystem 2 Host */
+#define APU_CPU3_CTRL_APU_SUBSYS3_HOST(x)        (((uint32_t)(((uint32_t)(x)) << APU_CPU3_CTRL_APU_SUBSYS3_HOST_SHIFT)) & APU_CPU3_CTRL_APU_SUBSYS3_HOST_MASK)
+/*! @} */
+
+/*! @name CPU3_DVFS_CTRL - CPU3 DVFS Control */
+/*! @{ */
+
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_INDEX_MASK (0xFU)
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_INDEX_SHIFT (0U)
+/*! CPU3_ACTIVE_INDEX - CPU3 Active Index */
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_INDEX(x)  (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_INDEX_SHIFT)) & APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_INDEX_MASK)
+
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_INDEX_MASK (0xF0U)
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_INDEX_SHIFT (4U)
+/*! CPU3_INACTIVE_INDEX - CPU3 Inactive Index */
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_INDEX_SHIFT)) & APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_INDEX_MASK)
+
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_SYS_INDEX_MASK (0xF00U)
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_SYS_INDEX_SHIFT (8U)
+/*! CPU3_ACTIVE_SYS_INDEX - CPU3 Active System Index */
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_SYS_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_SYS_INDEX_SHIFT)) & APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_SYS_INDEX_MASK)
+
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_SYS_INDEX_MASK (0xF000U)
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_SYS_INDEX_SHIFT (12U)
+/*! CPU3_INACTIVE_SYS_INDEX - CPU3 Inactive System Index */
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_SYS_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_SYS_INDEX_SHIFT)) & APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_SYS_INDEX_MASK)
+
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_AHB1_INDEX_MASK (0xF0000U)
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_AHB1_INDEX_SHIFT (16U)
+/*! CPU3_ACTIVE_AHB1_INDEX - CPU3 Active AHB1 Index */
+#define APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_AHB1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_AHB1_INDEX_SHIFT)) & APU_CPU3_DVFS_CTRL_CPU3_ACTIVE_AHB1_INDEX_MASK)
+
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_AHB1_INDEX_MASK (0xF00000U)
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_AHB1_INDEX_SHIFT (20U)
+/*! CPU3_INACTIVE_AHB1_INDEX - CPU3 Inactive AHB1 Index */
+#define APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_AHB1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_AHB1_INDEX_SHIFT)) & APU_CPU3_DVFS_CTRL_CPU3_INACTIVE_AHB1_INDEX_MASK)
+
+#define APU_CPU3_DVFS_CTRL_CPU3_AHB1_INDEX_SEL_METHOD_MASK (0x1000000U)
+#define APU_CPU3_DVFS_CTRL_CPU3_AHB1_INDEX_SEL_METHOD_SHIFT (24U)
+/*! CPU3_AHB1_INDEX_SEL_METHOD - CPU3 AHB1 index select method */
+#define APU_CPU3_DVFS_CTRL_CPU3_AHB1_INDEX_SEL_METHOD(x) (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_CPU3_AHB1_INDEX_SEL_METHOD_SHIFT)) & APU_CPU3_DVFS_CTRL_CPU3_AHB1_INDEX_SEL_METHOD_MASK)
+
+#define APU_CPU3_DVFS_CTRL_UART_VOL_VAL_MASK     (0xFE000000U)
+#define APU_CPU3_DVFS_CTRL_UART_VOL_VAL_SHIFT    (25U)
+/*! UART_VOL_VAL - UART Vol Value */
+#define APU_CPU3_DVFS_CTRL_UART_VOL_VAL(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU3_DVFS_CTRL_UART_VOL_VAL_SHIFT)) & APU_CPU3_DVFS_CTRL_UART_VOL_VAL_MASK)
+/*! @} */
+
+/*! @name CPU3_FREQ_REG1 - CPU3 Frequency 1 */
+/*! @{ */
+
+#define APU_CPU3_FREQ_REG1_CPU3_FREQ_REG1_MASK   (0xFFFFFFFFU)
+#define APU_CPU3_FREQ_REG1_CPU3_FREQ_REG1_SHIFT  (0U)
+/*! CPU3_FREQ_REG1 - CPU3 Frequency 1 */
+#define APU_CPU3_FREQ_REG1_CPU3_FREQ_REG1(x)     (((uint32_t)(((uint32_t)(x)) << APU_CPU3_FREQ_REG1_CPU3_FREQ_REG1_SHIFT)) & APU_CPU3_FREQ_REG1_CPU3_FREQ_REG1_MASK)
+/*! @} */
+
+/*! @name CPU3_FREQ_REG2 - CPU3 Frequency 2 */
+/*! @{ */
+
+#define APU_CPU3_FREQ_REG2_CPU3_FREQ_REG2_MASK   (0xFFFFFFFFU)
+#define APU_CPU3_FREQ_REG2_CPU3_FREQ_REG2_SHIFT  (0U)
+/*! CPU3_FREQ_REG2 - CPU3Frequency 2 */
+#define APU_CPU3_FREQ_REG2_CPU3_FREQ_REG2(x)     (((uint32_t)(((uint32_t)(x)) << APU_CPU3_FREQ_REG2_CPU3_FREQ_REG2_SHIFT)) & APU_CPU3_FREQ_REG2_CPU3_FREQ_REG2_MASK)
+/*! @} */
+
+/*! @name CPU3_PLL_EN_REG - CPU3 PLL Enable */
+/*! @{ */
+
+#define APU_CPU3_PLL_EN_REG_CPU3_PLL_EN_REG_MASK (0xFFFFFFFFU)
+#define APU_CPU3_PLL_EN_REG_CPU3_PLL_EN_REG_SHIFT (0U)
+/*! CPU3_PLL_EN_REG - CPU3 PLL Enable */
+#define APU_CPU3_PLL_EN_REG_CPU3_PLL_EN_REG(x)   (((uint32_t)(((uint32_t)(x)) << APU_CPU3_PLL_EN_REG_CPU3_PLL_EN_REG_SHIFT)) & APU_CPU3_PLL_EN_REG_CPU3_PLL_EN_REG_MASK)
+/*! @} */
+
+/*! @name CPU3_VOL_REG1 - CPU3 Voltage 1 */
+/*! @{ */
+
+#define APU_CPU3_VOL_REG1_CPU3_VOL_REG1_MASK     (0xFFFFFFFFU)
+#define APU_CPU3_VOL_REG1_CPU3_VOL_REG1_SHIFT    (0U)
+/*! CPU3_VOL_REG1 - CPU3 Voltage 1 */
+#define APU_CPU3_VOL_REG1_CPU3_VOL_REG1(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU3_VOL_REG1_CPU3_VOL_REG1_SHIFT)) & APU_CPU3_VOL_REG1_CPU3_VOL_REG1_MASK)
+/*! @} */
+
+/*! @name CPU3_VOL_REG2 - CPU3 Voltage 2 */
+/*! @{ */
+
+#define APU_CPU3_VOL_REG2_CPU3_VOL_REG2_MASK     (0xFFFFFFFFU)
+#define APU_CPU3_VOL_REG2_CPU3_VOL_REG2_SHIFT    (0U)
+/*! CPU3_VOL_REG2 - CPU3 Voltage 2 */
+#define APU_CPU3_VOL_REG2_CPU3_VOL_REG2(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU3_VOL_REG2_CPU3_VOL_REG2_SHIFT)) & APU_CPU3_VOL_REG2_CPU3_VOL_REG2_MASK)
+/*! @} */
+
+/*! @name CPU3_VOL_REG3 - CPU3 Voltage 3 */
+/*! @{ */
+
+#define APU_CPU3_VOL_REG3_CPU3_VOL_REG3_MASK     (0xFFFFFFFFU)
+#define APU_CPU3_VOL_REG3_CPU3_VOL_REG3_SHIFT    (0U)
+/*! CPU3_VOL_REG3 - CPU3 Voltage 3 */
+#define APU_CPU3_VOL_REG3_CPU3_VOL_REG3(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU3_VOL_REG3_CPU3_VOL_REG3_SHIFT)) & APU_CPU3_VOL_REG3_CPU3_VOL_REG3_MASK)
+/*! @} */
+
+/*! @name CPU3_VOL_REG4 - CPU3 Voltage 4 */
+/*! @{ */
+
+#define APU_CPU3_VOL_REG4_CPU3_VOL_REG4_MASK     (0xFFFFFFFFU)
+#define APU_CPU3_VOL_REG4_CPU3_VOL_REG4_SHIFT    (0U)
+/*! CPU3_VOL_REG4 - CPU3 Voltage 4 */
+#define APU_CPU3_VOL_REG4_CPU3_VOL_REG4(x)       (((uint32_t)(((uint32_t)(x)) << APU_CPU3_VOL_REG4_CPU3_VOL_REG4_SHIFT)) & APU_CPU3_VOL_REG4_CPU3_VOL_REG4_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group APU_Register_Masks */
+
+
+/* APU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral APU0 base address */
+  #define APU0_BASE                                (0x51258400u)
+  /** Peripheral APU0 base address */
+  #define APU0_BASE_NS                             (0x41258400u)
+  /** Peripheral APU0 base pointer */
+  #define APU0                                     ((APU_Type *)APU0_BASE)
+  /** Peripheral APU0 base pointer */
+  #define APU0_NS                                  ((APU_Type *)APU0_BASE_NS)
+  /** Peripheral APU1 base address */
+  #define APU1_BASE                                (0x54258400u)
+  /** Peripheral APU1 base address */
+  #define APU1_BASE_NS                             (0x44258400u)
+  /** Peripheral APU1 base pointer */
+  #define APU1                                     ((APU_Type *)APU1_BASE)
+  /** Peripheral APU1 base pointer */
+  #define APU1_NS                                  ((APU_Type *)APU1_BASE_NS)
+  /** Array initializer of APU peripheral base addresses */
+  #define APU_BASE_ADDRS                           { APU0_BASE, APU1_BASE }
+  /** Array initializer of APU peripheral base pointers */
+  #define APU_BASE_PTRS                            { APU0, APU1 }
+  /** Array initializer of APU peripheral base addresses */
+  #define APU_BASE_ADDRS_NS                        { APU0_BASE_NS, APU1_BASE_NS }
+  /** Array initializer of APU peripheral base pointers */
+  #define APU_BASE_PTRS_NS                         { APU0_NS, APU1_NS }
+#else
+  /** Peripheral APU0 base address */
+  #define APU0_BASE                                (0x41258400u)
+  /** Peripheral APU0 base pointer */
+  #define APU0                                     ((APU_Type *)APU0_BASE)
+  /** Peripheral APU1 base address */
+  #define APU1_BASE                                (0x44258400u)
+  /** Peripheral APU1 base pointer */
+  #define APU1                                     ((APU_Type *)APU1_BASE)
+  /** Array initializer of APU peripheral base addresses */
+  #define APU_BASE_ADDRS                           { APU0_BASE, APU1_BASE }
+  /** Array initializer of APU peripheral base pointers */
+  #define APU_BASE_PTRS                            { APU0, APU1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group APU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- BG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BG_Peripheral_Access_Layer BG Peripheral Access Layer
+ * @{
+ */
+
+/** BG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control Register, offset: 0x0 */
+  __I  uint32_t STATUS;                            /**< Status Register, offset: 0x4 */
+} BG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- BG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BG_Register_Masks BG Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+
+#define BG_CTRL_PD_MASK                          (0x1U)
+#define BG_CTRL_PD_SHIFT                         (0U)
+/*! PD - Bandgap power down.
+ *  0b1..Power down
+ *  0b0..Power up
+ */
+#define BG_CTRL_PD(x)                            (((uint32_t)(((uint32_t)(x)) << BG_CTRL_PD_SHIFT)) & BG_CTRL_PD_MASK)
+
+#define BG_CTRL_RES_TRIM_MASK                    (0xF0U)
+#define BG_CTRL_RES_TRIM_SHIFT                   (4U)
+/*! RES_TRIM - 1.2V voltage reference resistor trim.
+ *  0b0000..1.159V
+ *  0b0001..1.163V
+ *  0b0010..1.168V
+ *  0b0011..1.172V
+ *  0b0100..1.177V
+ *  0b0101..1.181V
+ *  0b0110..1.186V
+ *  0b0111..1.190V
+ *  0b1000..1.194V
+ *  0b1001..1.199V
+ *  0b1010..1.204V
+ *  0b1011..1.208V
+ *  0b1100..1.213V
+ *  0b1101..1.217V
+ *  0b1110..1.222V
+ *  0b1111..1.226V
+ */
+#define BG_CTRL_RES_TRIM(x)                      (((uint32_t)(((uint32_t)(x)) << BG_CTRL_RES_TRIM_SHIFT)) & BG_CTRL_RES_TRIM_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+
+#define BG_STATUS_RDY_MASK                       (0x1U)
+#define BG_STATUS_RDY_SHIFT                      (0U)
+/*! RDY - 1'b1 indicates BG ready flag. */
+#define BG_STATUS_RDY(x)                         (((uint32_t)(((uint32_t)(x)) << BG_STATUS_RDY_SHIFT)) & BG_STATUS_RDY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BG_Register_Masks */
+
+
+/* BG - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral GAU_BG base address */
+  #define GAU_BG_BASE                              (0x50038700u)
+  /** Peripheral GAU_BG base address */
+  #define GAU_BG_BASE_NS                           (0x40038700u)
+  /** Peripheral GAU_BG base pointer */
+  #define GAU_BG                                   ((BG_Type *)GAU_BG_BASE)
+  /** Peripheral GAU_BG base pointer */
+  #define GAU_BG_NS                                ((BG_Type *)GAU_BG_BASE_NS)
+  /** Array initializer of BG peripheral base addresses */
+  #define BG_BASE_ADDRS                            { GAU_BG_BASE }
+  /** Array initializer of BG peripheral base pointers */
+  #define BG_BASE_PTRS                             { GAU_BG }
+  /** Array initializer of BG peripheral base addresses */
+  #define BG_BASE_ADDRS_NS                         { GAU_BG_BASE_NS }
+  /** Array initializer of BG peripheral base pointers */
+  #define BG_BASE_PTRS_NS                          { GAU_BG_NS }
+#else
+  /** Peripheral GAU_BG base address */
+  #define GAU_BG_BASE                              (0x40038700u)
+  /** Peripheral GAU_BG base pointer */
+  #define GAU_BG                                   ((BG_Type *)GAU_BG_BASE)
+  /** Array initializer of BG peripheral base addresses */
+  #define BG_BASE_ADDRS                            { GAU_BG_BASE }
+  /** Array initializer of BG peripheral base pointers */
+  #define BG_BASE_PTRS                             { GAU_BG }
+#endif
+
+/*!
+ * @}
+ */ /* end of group BG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- BLEAPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BLEAPU_Peripheral_Access_Layer BLEAPU Peripheral Access Layer
+ * @{
+ */
+
+/** BLEAPU - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __IO uint32_t SOCBTAPU_APU_BYPASS0;              /**< APU Bypass0, offset: 0x8 */
+  __IO uint32_t SOCBTAPU_APU_PWR_CTRL_BYPASS0;     /**< APU power control Bypass Register 0, offset: 0xC */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t SOCBTAPU_APU_BYPASS1;              /**< APU Bypass Register 1, offset: 0x1C */
+  __IO uint32_t SOCBTAPU_APU_BYPASS2;              /**< APU Bypass Register 2, offset: 0x20 */
+  __IO uint32_t SOCBTAPU_APU_BYPASS3;              /**< APU Bypass Register 3, offset: 0x24 */
+  __IO uint32_t SOCBTAPU_APU_CTRL;                 /**< APU Control, offset: 0x28 */
+  __I  uint32_t SOCBTAPU_APU_STATUS;               /**< APU Status Register, offset: 0x2C */
+  __IO uint32_t SOCBTAPU_CPU1_LMU_STA_BYPASS0;     /**< LMU static bank control byapss0 Register, offset: 0x30 */
+  __IO uint32_t SOCBTAPU_CPU1_LMU_STA_BYPASS1;     /**< LMU static bank control byapss1 Register, offset: 0x34 */
+  __IO uint32_t SOCBTAPU_CPU1_LMU_STA_BYPASS2;     /**< LMU static bank byapss2 Register, offset: 0x38 */
+  __IO uint32_t SOCBTAPU_LMU_DYN_BYPASS0;          /**< LMU dynamic bank control byapss0 Register, offset: 0x3C */
+  __IO uint32_t SOCBTAPU_LMU_G2BIST_CTRL_BYPASS;   /**< LMU G2Bist control bypass Register, offset: 0x40 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS; /**< LMU G2Bist control bypass Register for CPU1, offset: 0x50 */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t SOCBTAPU_APU_PWR_CTRL_BYPASS5;     /**< ", offset: 0x5C */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0;  /**< LMU static bank control byapss0 Register for smu1 hybrid banks mem, offset: 0x68 */
+  __IO uint32_t SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1;  /**< LMU static bank control byapss1 Register for smu1 hybrid banks mem, offset: 0x6C */
+  __IO uint32_t SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2;  /**< LMU static bank control byapss2 Register for smu1 hybrid banks mem, offset: 0x70 */
+       uint8_t RESERVED_5[8];
+  __IO uint32_t SOCBTAPU_APU_ECO_CTRL;             /**< APU ECO Control, offset: 0x7C */
+  __IO uint32_t SOCBTAPU_GPIO_WKUP_CTRL0;          /**< ", offset: 0x80 */
+  __IO uint32_t SOCBTAPU_GPIO_WKUP_CTRL1;          /**< ", offset: 0x84 */
+  __IO uint32_t SOCBTAPU_GPIO_WKUP_CTRL2;          /**< ", offset: 0x88 */
+  __IO uint32_t SOCBTAPU_GPIO_WKUP_CTRL3;          /**< ", offset: 0x8C */
+  __IO uint32_t SOCBTAPU_HOST_WKUP_MODE;           /**< ", offset: 0x90 */
+  __IO uint32_t SOCBTAPU_T3_CLK_DIV_EN_BYPASS;     /**< ", offset: 0x94 */
+  __IO uint32_t SOCBTAPU_LDO_LV_CTRL2;             /**< LV LDO Control 2, offset: 0x98 */
+  __IO uint32_t SOCBTAPU_CAU_BYPASS;               /**< CAU Bypass, offset: 0x9C */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t SOCBTAPU_MEM_PWDN2;                /**< Memory Powerdown Control, offset: 0xA4 */
+       uint8_t RESERVED_7[8];
+  __IO uint32_t SOCBTAPU_HOST_WKUP_SOURCE;         /**< Host Wakeup Source Control, offset: 0xB0 */
+} BLEAPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- BLEAPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BLEAPU_Register_Masks BLEAPU Register Masks
+ * @{
+ */
+
+/*! @name SOCBTAPU_APU_BYPASS0 - APU Bypass0 */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_MASK (0x1U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_SHIFT (0U)
+/*! C2P_XOSC_EN_BYPASS_EN - C2p_Xosc_En_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_MASK (0x2U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_SHIFT (1U)
+/*! TBG_TCPU_PDB_BYPASS_EN - TCPU_Pdb_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_MASK (0x4U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_SHIFT (2U)
+/*! TBG_BBU1_CLK_EN_BYPASS_EN - TBG512_320_176_BBU1_Clk_En_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_MASK (0x8U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_SHIFT (3U)
+/*! TBG_T2_PDB_BYPASS_EN - tbg t2_Pdb_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_MASK (0x10U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_SHIFT (4U)
+/*! TBG_MAC1_CLK_EN_BYPASS_EN - TBG512_320_176_MAC1_Clk_En_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_MASK (0x20U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_SHIFT (5U)
+/*! TBG_SOC_CLK_EN_BYPASS_EN - TBG512_320_176_SoC_Clk_En_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_MASK (0x40U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_SHIFT (6U)
+/*! TBG_BBU2_CLK_EN_BYPASS_EN - TBG512_320_176_BBU2_Clk_En_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_MASK (0x80U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_SHIFT (7U)
+/*! TBG_MAC2_CLK_EN_BYPASS_EN - TBG512_320_176_MAC2_Clk_En_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_EN_MASK (0x400U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_EN_SHIFT (10U)
+/*! TX_PE_BYPASS_EN - BBU_Rx_Pe_Bypass Enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_EN_MASK (0x800U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_EN_SHIFT (11U)
+/*! RX_PE_BYPASS_EN - BBU_Rx_Pe_Bypass Enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_MASK (0x1000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_SHIFT (12U)
+/*! RFU_PE1_BYPASS_EN - RFU_PE1_Bypass Enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_MASK (0x2000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_SHIFT (13U)
+/*! RFU_PE2_BYPASS_EN - RFU_PE2_Bypass Enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_MASK (0x4000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_SHIFT (14U)
+/*! RFU_PA_PE_A_BYPASS_EN - RFU_PA_PE_A_Bypass Enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_MASK (0x8000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_SHIFT (15U)
+/*! RFU_PA_PE_G_BYPASS_EN - RFU_PA_PE_G_Bypass Enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_MASK (0x10000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_SHIFT (16U)
+/*! C2P_XOSC_EN_BYPASS_VAL - C2p_Xosc_En Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_MASK (0x20000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_SHIFT (17U)
+/*! TBG_TCPU_PDB_BYPASS_VAL - TCPU_Pdb Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_MASK (0x40000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_SHIFT (18U)
+/*! TBG_BBU1_CLK_EN_BYPASS_VAL - TBG512_320_176_BBU1_Clk_En Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_MASK (0x80000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_SHIFT (19U)
+/*! TBG_T2_PDB_BYPASS_VAL - TBF176_Pdb Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_MASK (0x100000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_SHIFT (20U)
+/*! TBG_MAC1_CLK_EN_BYPASS_VAL - TBG512_320_176_MAC1_Clk_En Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_MASK (0x200000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_SHIFT (21U)
+/*! TBG_SOC_CLK_EN_BYPASS_VAL - TBG512_320_176_SoC_Clk_En Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_MASK (0x400000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_SHIFT (22U)
+/*! TBG_BBU2_CLK_EN_BYPASS_VAL - TBG512_320_176_BBU2_Clk_En Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_MASK (0x800000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_SHIFT (23U)
+/*! TBG_MAC2_CLK_EN_BYPASS_VAL - TBG512_320_176_MAC2_Clk_En Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_MASK (0x4000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_SHIFT (26U)
+/*! TX_PE_BYPASS_VAL - Tx_Pe Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_MASK (0x8000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_SHIFT (27U)
+/*! RX_PE_BYPASS_VAL - Rx_Pe Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_MASK (0x10000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_SHIFT (28U)
+/*! RFU_PE1_BYPASS_VAL - RFU PE1 Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_MASK (0x20000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_SHIFT (29U)
+/*! RFU_PE2_BYPASS_VAL - RFU PE2 Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_MASK (0x40000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_SHIFT (30U)
+/*! RFU_PA_PE_A_BYPASS_VAL - RFU PA_PE_A Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_MASK (0x80000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_SHIFT (31U)
+/*! RFU_PA_PE_G_BYPASS_VAL - RFU PA_PE_G Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_PWR_CTRL_BYPASS0 - APU power control Bypass Register 0 */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_MASK (0x1U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_SHIFT (0U)
+/*! SOC_PSW_BYPASS_VAL - SoC Power Switch Control */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_MASK (0x2U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_SHIFT (1U)
+/*! SOC_PSW_BYPASS_EN - SoC Power Switch Control Enable */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_MASK (0x4U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_SHIFT (2U)
+/*! SOC_FWBAR_BYPASS_VAL - SoC Firewallbar Control */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_MASK (0x8U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_SHIFT (3U)
+/*! SOC_FWBAR_BYPASS_EN - SoC Firewallbar Control Enable */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_MASK (0x10U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_SHIFT (4U)
+/*! SOC_ISO_EN_BYPASS_VAL - SoC Isolation Cell Control */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_MASK (0x20U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_SHIFT (5U)
+/*! SOC_ISO_EN_BYPASS_EN - SoC Isolation Cell Control Enable */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_MASK (0x40U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_SHIFT (6U)
+/*! SOC_CLK_DIV_RSTB_BYPASS_VAL - Firmware Bypass Value for SoC Dlk_Div_Rstb (active low signal) */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_MASK (0x80U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_SHIFT (7U)
+/*! SOC_CLK_DIV_RSTB_BYPASS_EN - Firmware Bypass SoC Clk_Div_Rstb from APU */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_MASK (0x100U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_SHIFT (8U)
+/*! SOC_NON_UDR_RST_BYPASS_VAL - Firmware Bypass Value for SoC non udr rst (active low signal) */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_MASK (0x200U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_SHIFT (9U)
+/*! SOC_NON_UDR_RST_BYPASS_EN - Firmware Bypass SoC non udr rst from APU (used for brf sif only in KF2) */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_BYPASS1 - APU Bypass Register 1 */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_MASK (0x40U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_SHIFT (6U)
+/*! SOC_CAU_XOSC_EN_BP_EN - Firmware Bypass Xosc_En to CAU and other parts of the chip including pads */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_MASK (0x80U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_SHIFT (7U)
+/*! SOC_CAU_XOSC_EN_BP_VAL - Firmware Bypass Xosc_En Value for SoC_CAU_Xosc_En_Bp_En */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_RXPE_DYN_BYPASS_MASK (0x100U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_RXPE_DYN_BYPASS_SHIFT (8U)
+/*! RXPE_DYN_BYPASS - Rxpe_Dyn_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_RXPE_DYN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_RXPE_DYN_BYPASS_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_RXPE_DYN_BYPASS_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_PE1_DYN_BYPASS_MASK (0x200U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_PE1_DYN_BYPASS_SHIFT (9U)
+/*! PE1_DYN_BYPASS - PE1_Dyn_Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_PE1_DYN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_PE1_DYN_BYPASS_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_PE1_DYN_BYPASS_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_MASK (0x400U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_SHIFT (10U)
+/*! PLL_OVERRIDE_BYPASS - PLL Override Bypass */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_MASK (0x40000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_SHIFT (18U)
+/*! BCA_CLK_EN_BYPASS_EN - Firmware Bypass BCA_Clk_En */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_MASK (0x80000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_SHIFT (19U)
+/*! BCA_CLK_EN_BYPASS_VAL - Firmware Bypass Value for BCA_Clk_En (active high signal) */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_MASK (0x4000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_SHIFT (26U)
+/*! SLNA_CLK_EN_BYPASS_EN - Firmware Bypass for SLNA_Clk_En */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_MASK (0x8000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_SHIFT (27U)
+/*! SLNA_CLK_EN_BYPASS_VAL - Firmware Bypass Value for SLNA_Clk_En (active high signal) */
+#define BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_BYPASS2 - APU Bypass Register 2 */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_MASK (0x100U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_SHIFT (8U)
+/*! TBG_T3_PDB_BYPASS_EN - Firmware Bypass for T3_pdb pll */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_MASK (0x200U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_SHIFT (9U)
+/*! TBG_T3_PDB_BYPASS_VAL - T3_Pdb Bypass Value */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_MASK (0x400U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_SHIFT (10U)
+/*! T3_PI1_PDB_BYPASS_EN - Firmware Bypass for TBG256 aiu_pi1 */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_MASK (0x800U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_SHIFT (11U)
+/*! T3_PI1_PDB_BYPASS_VAL - Firmware Bypass Value for TBG256 aiu pi1 */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_MASK (0x1000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_SHIFT (12U)
+/*! T3_PI2_PDB_BYPASS_EN - Firmware Bypass for TBG256 aiu_pi2 */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_MASK (0x2000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_SHIFT (13U)
+/*! T3_PI2_PDB_BYPASS_VAL - Firmware Bypass Value for TBG256 aiu_pi2 */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_MASK (0x2000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_SHIFT (25U)
+/*! TBG_T1_STABLE_BYPASS_EN - Firmware Bypass enable for T1 pll_stable signal from APU */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_MASK (0x4000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_SHIFT (26U)
+/*! TBG_T1_STABLE_BYPASS_VAL - Firmware Bypass value for T1 pll_stable signal from APU */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_MASK (0x8000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_SHIFT (27U)
+/*! PMIC_DVSC_CTRL_BYPASS_EN - Firmware Bypass enable for pmic dvsc ctrl from APU */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_MASK (0x30000000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_SHIFT (28U)
+/*! PMIC_DVSC_CTRL_BYPASS_VAL - Firmware Bypass value for pmic dvsc ctrl from APU (default high power WLAN ode) */
+#define BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_BYPASS3 - APU Bypass Register 3 */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_MASK (0x10U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_SHIFT (4U)
+/*! SYS_CLK_EN_BYPASS_EN - Firmware Bypass for sys clock domain clock enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_MASK (0x20U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_SHIFT (5U)
+/*! SYS_CLK_EN_BYPASS_VAL - Firmware Bypass Value for sys clock domain clock enable(active high signal) */
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_MASK (0x4000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_SHIFT (14U)
+/*! SPSRAM_RST_BYPASS_EN - Firmware Bypass for Single power SRAM reset enable */
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_MASK (0x8000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_SHIFT (15U)
+/*! SPSRAM_RST_BYPASS_VAL - Firmware Bypass Value for single power sram reset(active low signal) */
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_MASK (0x10000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_SHIFT (16U)
+/*! SLNA_BBUD_BRF_BYPASS_EN - Firmware Bypass for apu mux control of SLNA gain from bbud/brf */
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_MASK (0x20000U)
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_SHIFT (17U)
+/*! SLNA_BBUD_BRF_BYPASS_VAL - Firmware Bypass Value for apu mux control of SLNA gain from bbud/brf */
+#define BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_CTRL - APU Control */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_REFCLK_DIV_SEL_MASK (0xFU)
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_REFCLK_DIV_SEL_SHIFT (0U)
+/*! APU_REFCLK_DIV_SEL - APU Reference Clock Divider Select */
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_REFCLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_APU_REFCLK_DIV_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_APU_REFCLK_DIV_SEL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU_WAKEUP_MASK (0x10U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU_WAKEUP_SHIFT (4U)
+/*! FORCE_BTU_WAKEUP - Force BTU Wakeup */
+#define BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU_WAKEUP_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU_WAKEUP_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_ISU_WKUP_IN_USE_MASK (0x40U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_ISU_WKUP_IN_USE_SHIFT (6U)
+/*! ISU_WKUP_IN_USE - APU Wakeup */
+#define BLEAPU_SOCBTAPU_APU_CTRL_ISU_WKUP_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_ISU_WKUP_IN_USE_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_ISU_WKUP_IN_USE_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_MASK (0x80U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_SHIFT (7U)
+/*! APU_HOST_WKUP - APU Wakeup triggered by CPU2 */
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_BRF_INT_WAKEUP_MASK (0x100U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_BRF_INT_WAKEUP_SHIFT (8U)
+/*! BRF_INT_WAKEUP - APU Wakeup */
+#define BLEAPU_SOCBTAPU_APU_CTRL_BRF_INT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_BRF_INT_WAKEUP_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_BRF_INT_WAKEUP_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_MASK (0x200U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_SHIFT (9U)
+/*! SOC_PA_PE_EN - PA_PE control from SoC to RFU SoC_PA_PE Input */
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_A_EN_MASK (0x400U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_A_EN_SHIFT (10U)
+/*! SOC_PA_PE_A_EN - PA_PE_A control from SoC to Pad */
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_A_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_A_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_A_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_G_EN_MASK (0x800U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_G_EN_SHIFT (11U)
+/*! SOC_PA_PE_G_EN - PA_PE_G control from SoC to Pad */
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_G_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_G_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_G_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_MASK (0x1000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_SHIFT (12U)
+/*! RFU_2G_SRAM_PD_METHOD_SEL - Choose apu signal to use for SRAM PD of RFU 2G memories */
+#define BLEAPU_SOCBTAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_BRF_SRAM_PD_METHOD_SEL_MASK (0x2000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_BRF_SRAM_PD_METHOD_SEL_SHIFT (13U)
+/*! BRF_SRAM_PD_METHOD_SEL - Choose apu signal to use for SRAM PD of BRF memories */
+#define BLEAPU_SOCBTAPU_APU_CTRL_BRF_SRAM_PD_METHOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_BRF_SRAM_PD_METHOD_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_BRF_SRAM_PD_METHOD_SEL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_LMU_BYPASS_MASK (0x8000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_LMU_BYPASS_SHIFT (15U)
+/*! LMU_BYPASS - LMU global bypass bit */
+#define BLEAPU_SOCBTAPU_APU_CTRL_LMU_BYPASS(x)   (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_LMU_BYPASS_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_LMU_BYPASS_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_MASK (0x10000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_SHIFT (16U)
+/*! SOC_PA_PE_EN_MAC2 - PA_PE control from MAC2 to RFU SoC_PA_PE Input */
+#define BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_MAC2(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_RFU_5G_SRAM_PD_METHOD_SEL_MASK (0x20000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_RFU_5G_SRAM_PD_METHOD_SEL_SHIFT (17U)
+/*! RFU_5G_SRAM_PD_METHOD_SEL - Choose apu signal to use for SRAM PD of RFU 5G memories */
+#define BLEAPU_SOCBTAPU_APU_CTRL_RFU_5G_SRAM_PD_METHOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_RFU_5G_SRAM_PD_METHOD_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_RFU_5G_SRAM_PD_METHOD_SEL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU1_MASK (0x40000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU1_SHIFT (18U)
+/*! APU_HOST_WKUP_CPU1 - APU Wakeup triggered by CPU1 */
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU1(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU1_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU1_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU3_MASK (0x80000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU3_SHIFT (19U)
+/*! APU_HOST_WKUP_CPU3 - APU Wakeup triggered by CPU3 */
+#define BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU3(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU3_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_APU_HOST_WKUP_CPU3_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU2_WAKEUP_MASK (0x100000U)
+#define BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU2_WAKEUP_SHIFT (20U)
+/*! FORCE_BTU2_WAKEUP - Force BTU2 Wakeup */
+#define BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU2_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU2_WAKEUP_SHIFT)) & BLEAPU_SOCBTAPU_APU_CTRL_FORCE_BTU2_WAKEUP_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_STATUS - APU Status Register */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_STATUS_BRF_CLK_TBG_SEL_MASK (0x1U)
+#define BLEAPU_SOCBTAPU_APU_STATUS_BRF_CLK_TBG_SEL_SHIFT (0U)
+/*! BRF_CLK_TBG_SEL - Monitor BRF_Clk_TBG_Sel */
+#define BLEAPU_SOCBTAPU_APU_STATUS_BRF_CLK_TBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_STATUS_BRF_CLK_TBG_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_STATUS_BRF_CLK_TBG_SEL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_STATUS_BTU_CLK_TBG_SEL_MASK (0x2U)
+#define BLEAPU_SOCBTAPU_APU_STATUS_BTU_CLK_TBG_SEL_SHIFT (1U)
+/*! BTU_CLK_TBG_SEL - Monitor BTU_Clk_TBG_Sel */
+#define BLEAPU_SOCBTAPU_APU_STATUS_BTU_CLK_TBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_STATUS_BTU_CLK_TBG_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_STATUS_BTU_CLK_TBG_SEL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_MASK (0x4U)
+#define BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_SHIFT (2U)
+/*! SOC_CLK_T3_REF_SEL - Monitor SoC_Clk_T3_Ref_Sel */
+#define BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_T3_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_TBG_SEL_MASK (0x8U)
+#define BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_TBG_SEL_SHIFT (3U)
+/*! SOC_CLK_TBG_SEL - Monitor SoC_Clk_TBG_Sel */
+#define BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_TBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_TBG_SEL_SHIFT)) & BLEAPU_SOCBTAPU_APU_STATUS_SOC_CLK_TBG_SEL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_CPU1_LMU_STA_BYPASS0 - LMU static bank control byapss0 Register */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK (0xFFU)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_ISO_EN_BP_EN - Firmware Bypass enable for lmu static banks iso_en */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK (0xFF00U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_ISO_EN_BP_VAL - Firmware Bypass value for lmu static banks iso_en */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK (0xFF0000U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT (16U)
+/*! LMU_STA_BANKS_PSW_EN_BP_EN - Firmware Bypass enable for lmu static banks psw_en */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK (0xFF000000U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT (24U)
+/*! LMU_STA_BANKS_PSW_EN_BP_VAL - Firmware Bypass value for lmu static banks psw_en */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_CPU1_LMU_STA_BYPASS1 - LMU static bank control byapss1 Register */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK (0xFFU)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_SRAM_PD_BP_EN - Firmware Bypass enable for lmu static banks sram_pd */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK (0xFF00U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_SRAM_PD_BP_VAL - Firmware Bypass value for lmu static banks sram_pd */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK (0xFF0000U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT (16U)
+/*! LMU_STA_BANKS_FNRST_BP_EN - Firmware Bypass enable for lmu static banks fnrst */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK (0xFF000000U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT (24U)
+/*! LMU_STA_BANKS_FNRST_BP_VAL - Firmware Bypass value for lmu static banks fnrst */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_CPU1_LMU_STA_BYPASS2 - LMU static bank byapss2 Register */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0xFFU)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN - Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0xFF00U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL - Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_LMU_DYN_BYPASS0 - LMU dynamic bank control byapss0 Register */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0x7U)
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
+/*! LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN - Firmware Bypass enable for lmu dynamic banks vddmc_sw_pd_ctrl */
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0x700U)
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
+/*! LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL - Firmware Bypass value for lmu dynamic banks vddmc_sw_pd_ctrl */
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_MASK (0x70000U)
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_SHIFT (16U)
+/*! LMU_DYN_BANKS_FNRST_BP_EN - Firmware Bypass enable for lmu dynamic banks fnrst */
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_MASK (0x7000000U)
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_SHIFT (24U)
+/*! LMU_DYN_BANKS_FNRST_BP_VAL - Firmware Bypass value for lmu dynamic banks fnrst */
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_MASK (0x80000000U)
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_SHIFT (31U)
+/*! LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST - 1: By default WLAN_SRAM_FNRST is used for SMU off domain banks */
+#define BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_SHIFT)) & BLEAPU_SOCBTAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_LMU_G2BIST_CTRL_BYPASS - LMU G2Bist control bypass Register */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_MASK (0x1U)
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_SHIFT (0U)
+/*! LMU_G2BIST_MODE_BYPASS_EN - Firmware Bypass enable for lmu g2bist mode */
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_MASK (0x3EU)
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_SHIFT (1U)
+/*! LMU_G2BIST_MODE_BYPASS_VAL - Firmware Bypass value for lmu g2bist mode */
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_MASK (0x1000000U)
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_SHIFT (24U)
+/*! LMU_G2BIST_START_BP_EN - Firmware Bypass enable for lmu g2bist start */
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_MASK (0x2000000U)
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_SHIFT (25U)
+/*! LMU_G2BIST_START_BP_VAL - Firmware Bypass value for lmu g2bist start */
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_MASK (0x4000000U)
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_SHIFT (26U)
+/*! LMU_G2BIST_CLK_EN_BP_EN - Firmware Bypass enable for lmu g2bist clock en */
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_MASK (0x8000000U)
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_SHIFT (27U)
+/*! LMU_G2BIST_CLK_EN_BP_VAL - Firmware Bypass value for lmu g2bist clock en */
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_MASK (0xF0000000U)
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_SHIFT (28U)
+/*! G2BIST_STATUS - g2bist status */
+#define BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_SHIFT)) & BLEAPU_SOCBTAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS - LMU G2Bist control bypass Register for CPU1 */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_MASK (0x1U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT (0U)
+/*! LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN - Firmware Bypass enable for CPU1 static banks lmu powerdomain repair request */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_MASK (0xFFF0U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT (4U)
+/*! LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL - Firmware Bypass value for CPU1 static banks lmu powerdomain repair request */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_MASK (0x100000U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_SHIFT (20U)
+/*! LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN - Firmware Bypass enable for SMU1 dynamic banks lmu powerdomain repair request */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_MASK (0xF000000U)
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_SHIFT (24U)
+/*! LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL - Firmware Bypass value for SMU1 dynamic banks lmu powerdomain repair request */
+#define BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_PWR_CTRL_BYPASS5 - " */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_MASK (0x1000U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_SHIFT (12U)
+/*! CPU1_VINITHI_BYPASS_VAL - Firmware Bypass Value for CPU1 Vinithi (default boot from ROM) */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_MASK (0x2000U)
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_SHIFT (13U)
+/*! CPU1_VINITHI_BYPASS_EN - Firmware Bypass enable for CPU1 Vinithi */
+#define BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0 - LMU static bank control byapss0 Register for smu1 hybrid banks mem */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_MASK (0xFFU)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_SHIFT (0U)
+/*! LMU_HYBRID_BANKS_ISO_EN_BP_EN - Firmware Bypass enable for lmu static banks iso_en */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_MASK (0xFF00U)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_SHIFT (8U)
+/*! LMU_HYBRID_BANKS_ISO_EN_BP_VAL - Firmware Bypass value for lmu static banks iso_en */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_MASK (0xFF0000U)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_SHIFT (16U)
+/*! LMU_HYBRID_BANKS_PSW_EN_BP_EN - Firmware Bypass enable for lmu static banks psw_en */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_MASK (0xFF000000U)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_SHIFT (24U)
+/*! LMU_HYBRID_BANKS_PSW_EN_BP_VAL - Firmware Bypass value for lmu static banks psw_en */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1 - LMU static bank control byapss1 Register for smu1 hybrid banks mem */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_MASK (0xFFU)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_SHIFT (0U)
+/*! LMU_HYBRID_BANKS_SRAM_PD_BP_EN - Firmware Bypass enable for lmu static banks sram_pd */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_MASK (0xFF00U)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_SHIFT (8U)
+/*! LMU_HYBRID_BANKS_SRAM_PD_BP_VAL - Firmware Bypass value for lmu static banks sram_pd */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_MASK (0xFF0000U)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_SHIFT (16U)
+/*! LMU_HYBRID_BANKS_FNRST_BP_EN - Firmware Bypass enable for lmu static banks fnrst */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_MASK (0xFF000000U)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_SHIFT (24U)
+/*! LMU_HYBRID_BANKS_FNRST_BP_VAL - Firmware Bypass value for lmu static banks fnrst */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2 - LMU static bank control byapss2 Register for smu1 hybrid banks mem */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0xFFU)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
+/*! LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN - Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0xFF00U)
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
+/*! LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL - Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl */
+#define BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & BLEAPU_SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_APU_ECO_CTRL - APU ECO Control */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_APU_ECO_CTRL_ECO_BITS_MASK (0xFFFFFFFFU)
+#define BLEAPU_SOCBTAPU_APU_ECO_CTRL_ECO_BITS_SHIFT (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define BLEAPU_SOCBTAPU_APU_ECO_CTRL_ECO_BITS(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_APU_ECO_CTRL_ECO_BITS_SHIFT)) & BLEAPU_SOCBTAPU_APU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_GPIO_WKUP_CTRL0 - " */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [0] */
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_SHIFT)) & BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_GPIO_WKUP_CTRL1 - " */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [4] */
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_SHIFT)) & BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_GPIO_WKUP_CTRL2 - " */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [8] */
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_SHIFT)) & BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_GPIO_WKUP_CTRL3 - " */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [12] */
+#define BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_SHIFT)) & BLEAPU_SOCBTAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_HOST_WKUP_MODE - " */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_HOST_WKUP_MODE_GPIO_SEL_MASK (0xFFFFU)
+#define BLEAPU_SOCBTAPU_HOST_WKUP_MODE_GPIO_SEL_SHIFT (0U)
+/*! GPIO_SEL - GPIO select */
+#define BLEAPU_SOCBTAPU_HOST_WKUP_MODE_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_HOST_WKUP_MODE_GPIO_SEL_SHIFT)) & BLEAPU_SOCBTAPU_HOST_WKUP_MODE_GPIO_SEL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_T3_CLK_DIV_EN_BYPASS - " */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_MASK (0x1U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_SHIFT (0U)
+/*! T3_SOC_256_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_MASK (0x2U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_SHIFT (1U)
+/*! T3_SOC_256_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_MASK (0x4U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_SHIFT (2U)
+/*! T3_SOC_320_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_MASK (0x8U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_SHIFT (3U)
+/*! T3_SOC_320_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_MASK (0x10U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_SHIFT (4U)
+/*! T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_MASK (0x20U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_SHIFT (5U)
+/*! T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_MASK (0x40U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_SHIFT (6U)
+/*! T3_SOC_426_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_MASK (0x80U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_SHIFT (7U)
+/*! T3_SOC_426_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_MASK (0x100U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_SHIFT (8U)
+/*! T3_SOC_512_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_MASK (0x200U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_SHIFT (9U)
+/*! T3_SOC_512_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_MASK (0x400U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_SHIFT (10U)
+/*! T3_213P3_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_MASK (0x800U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_SHIFT (11U)
+/*! T3_213P3_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_MASK (0x1000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_SHIFT (12U)
+/*! T3_MAC1_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_MASK (0x2000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_SHIFT (13U)
+/*! T3_MAC1_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_MASK (0x4000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_SHIFT (14U)
+/*! T3_MAC2_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_MASK (0x8000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_SHIFT (15U)
+/*! T3_MAC2_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_MASK (0x10000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_SHIFT (16U)
+/*! T3_BBUD_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_MASK (0x20000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_SHIFT (17U)
+/*! T3_BBUD_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_MASK (0x40000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_SHIFT (18U)
+/*! TCPU_CPU_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_MASK (0x80000U)
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_SHIFT (19U)
+/*! TCPU_CPU_CLK_DIV_EN_BYPASS_VAL - bypass value for tcpu cpu_clk_en */
+#define BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_LDO_LV_CTRL2 - LV LDO Control 2 */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_MASK (0x10U)
+#define BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_SHIFT (4U)
+/*! LDO_GLU_XOSC_VAL - XOSC_EN value for ldo control logic set by FW */
+#define BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_SHIFT)) & BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_MASK (0x20U)
+#define BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_SHIFT (5U)
+/*! LDO_GLU_XOSC_BYPASS_EN - XOSC_EN control bypass for ldo control logic */
+#define BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_CAU_BYPASS - CAU Bypass */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_MASK (0x1U)
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_SHIFT (0U)
+/*! PHY_REF_CLK_BYPASS_VAL - bypass value for phy ref clk enable */
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_MASK (0x2U)
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_SHIFT (1U)
+/*! PHY_REF_CLK_BYPASS_EN - bypass enable for phy ref clk enable */
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_VAL_MASK (0x4U)
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_VAL_SHIFT (2U)
+/*! BT_CLK_BYPASS_VAL - bypass value for bt clk enable */
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_EN_MASK (0x8U)
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_EN_SHIFT (3U)
+/*! BT_CLK_BYPASS_EN - bypass enable for bt clk enable */
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_CAU_BYPASS_BT_CLK_BYPASS_EN_MASK)
+
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_VAL_MASK (0x40U)
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_VAL_SHIFT (6U)
+/*! BRF_CLK_BYPASS_VAL - bypass value for brf clk */
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_EN_MASK (0x80U)
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_EN_SHIFT (7U)
+/*! BRF_CLK_BYPASS_EN - bypass enable for brf clk */
+#define BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_CAU_BYPASS_BRF_CLK_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_MEM_PWDN2 - Memory Powerdown Control */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_VAL_MASK (0x2U)
+#define BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_VAL_SHIFT (1U)
+/*! OTP_BYPASS_VAL - Firmware Bypass Value for OTP Power Down */
+#define BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_VAL_SHIFT)) & BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_VAL_MASK)
+
+#define BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_EN_MASK (0x20000U)
+#define BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_EN_SHIFT (17U)
+/*! OTP_BYPASS_EN - Firmware Bypass Enable for OTP Power Down */
+#define BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_EN_SHIFT)) & BLEAPU_SOCBTAPU_MEM_PWDN2_OTP_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCBTAPU_HOST_WKUP_SOURCE - Host Wakeup Source Control */
+/*! @{ */
+
+#define BLEAPU_SOCBTAPU_HOST_WKUP_SOURCE_ENABLE_MASK (0xFFFFU)
+#define BLEAPU_SOCBTAPU_HOST_WKUP_SOURCE_ENABLE_SHIFT (0U)
+/*! ENABLE - Enable/ disable value: */
+#define BLEAPU_SOCBTAPU_HOST_WKUP_SOURCE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLEAPU_SOCBTAPU_HOST_WKUP_SOURCE_ENABLE_SHIFT)) & BLEAPU_SOCBTAPU_HOST_WKUP_SOURCE_ENABLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BLEAPU_Register_Masks */
+
+
+/* BLEAPU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral BLEAPU base address */
+  #define BLEAPU_BASE                              (0x54258000u)
+  /** Peripheral BLEAPU base address */
+  #define BLEAPU_BASE_NS                           (0x44258000u)
+  /** Peripheral BLEAPU base pointer */
+  #define BLEAPU                                   ((BLEAPU_Type *)BLEAPU_BASE)
+  /** Peripheral BLEAPU base pointer */
+  #define BLEAPU_NS                                ((BLEAPU_Type *)BLEAPU_BASE_NS)
+  /** Array initializer of BLEAPU peripheral base addresses */
+  #define BLEAPU_BASE_ADDRS                        { BLEAPU_BASE }
+  /** Array initializer of BLEAPU peripheral base pointers */
+  #define BLEAPU_BASE_PTRS                         { BLEAPU }
+  /** Array initializer of BLEAPU peripheral base addresses */
+  #define BLEAPU_BASE_ADDRS_NS                     { BLEAPU_BASE_NS }
+  /** Array initializer of BLEAPU peripheral base pointers */
+  #define BLEAPU_BASE_PTRS_NS                      { BLEAPU_NS }
+#else
+  /** Peripheral BLEAPU base address */
+  #define BLEAPU_BASE                              (0x44258000u)
+  /** Peripheral BLEAPU base pointer */
+  #define BLEAPU                                   ((BLEAPU_Type *)BLEAPU_BASE)
+  /** Array initializer of BLEAPU peripheral base addresses */
+  #define BLEAPU_BASE_ADDRS                        { BLEAPU_BASE }
+  /** Array initializer of BLEAPU peripheral base pointers */
+  #define BLEAPU_BASE_PTRS                         { BLEAPU }
+#endif
+
+/*!
+ * @}
+ */ /* end of group BLEAPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- BUCK11 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BUCK11_Peripheral_Access_Layer BUCK11 Peripheral Access Layer
+ * @{
+ */
+
+/** BUCK11 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[64];
+  __I  uint8_t BUCK_BYPASS_SOC_CTRL_ONE_RO_REG;    /**< offset: 0x40 */
+  __I  uint8_t BUCK_BYPASS_SOC_CTRL_TWO_RO_REG;    /**< offset: 0x41 */
+  __I  uint8_t REG_RO_ONE_REG;                     /**< offset: 0x42 */
+  __I  uint8_t REG_RO_TWO_REG;                     /**< offset: 0x43 */
+  __I  uint8_t REG_RO_THREE_REG;                   /**< offset: 0x44 */
+  __I  uint8_t REG_RO_FOUR_REG;                    /**< offset: 0x45 */
+  __IO uint8_t SYS_CTRL_REG;                       /**< offset: 0x46 */
+  __IO uint8_t BUCK_BYPASS_SOC_CTRL_ONE_RW_REG;    /**< offset: 0x47 */
+  __IO uint8_t BUCK_BYPASS_SOC_CTRL_TWO_RW_REG;    /**< offset: 0x48 */
+  __IO uint8_t BUCK_CTRL_ONE_REG;                  /**< offset: 0x49 */
+  __IO uint8_t BUCK_CTRL_TWO_REG;                  /**< offset: 0x4A */
+  __IO uint8_t BUCK_CTRL_THREE_REG;                /**< offset: 0x4B */
+  __IO uint8_t BUCK_CTRL_FOUR_REG;                 /**< offset: 0x4C */
+  __IO uint8_t BUCK_CTRL_FIVE_REG;                 /**< offset: 0x4D */
+  __IO uint8_t BUCK_CTRL_SIX_REG;                  /**< offset: 0x4E */
+  __IO uint8_t BUCK_CTRL_SEVEN_REG;                /**< offset: 0x4F */
+  __IO uint8_t BUCK_CTRL_EIGHT_REG;                /**< offset: 0x50 */
+  __IO uint8_t BUCK_CTRL_NINE_REG;                 /**< offset: 0x51 */
+  __IO uint8_t BUCK_CTRL_TEN_REG;                  /**< offset: 0x52 */
+  __IO uint8_t BUCK_CTRL_ELEVEN_REG;               /**< offset: 0x53 */
+  __IO uint8_t BUCK_CTRL_TWELVE_REG;               /**< offset: 0x54 */
+  __IO uint8_t BUCK_CTRL_THIRTEEN_REG;             /**< offset: 0x55 */
+  __IO uint8_t BUCK_CTRL_FOURTEEN_REG;             /**< offset: 0x56 */
+  __IO uint8_t BUCK_CTRL_FIFTEEN_REG;              /**< offset: 0x57 */
+  __IO uint8_t BUCK_CTRL_SIXTEEN_REG;              /**< offset: 0x58 */
+  __IO uint8_t BUCK_CTRL_SEVENTEEN_REG;            /**< offset: 0x59 */
+  __IO uint8_t BUCK_CTRL_EIGHTEEN_REG;             /**< offset: 0x5A */
+  __IO uint8_t BUCK_CTRL_NINTEEN_REG;              /**< offset: 0x5B */
+  __IO uint8_t BUCK_CTRL_TWENTY_REG;               /**< offset: 0x5C */
+} BUCK11_Type;
+
+/* ----------------------------------------------------------------------------
+   -- BUCK11 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BUCK11_Register_Masks BUCK11 Register Masks
+ * @{
+ */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_MASK (0xFFU)
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_SHIFT (0U)
+/*! BUCK_BYPASS_SOC_CTRL_ONE_RO - BUCK_BYPASS_SOC_CTRL_ONE_RO */
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_SHIFT)) & BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_MASK)
+/*! @} */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_TWO_RO_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_MASK (0xFFU)
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_SHIFT (0U)
+/*! BUCK_BYPASS_SOC_CTRL_TWO_RO - BUCK_BYPASS_SOC_CTRL_TWO_RO */
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_SHIFT)) & BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_MASK)
+/*! @} */
+
+/*! @name REG_RO_ONE_REG -  */
+/*! @{ */
+
+#define BUCK11_REG_RO_ONE_REG_REG_RO_ONE_MASK    (0xFFU)
+#define BUCK11_REG_RO_ONE_REG_REG_RO_ONE_SHIFT   (0U)
+/*! REG_RO_ONE - REG_RO_ONE */
+#define BUCK11_REG_RO_ONE_REG_REG_RO_ONE(x)      (((uint8_t)(((uint8_t)(x)) << BUCK11_REG_RO_ONE_REG_REG_RO_ONE_SHIFT)) & BUCK11_REG_RO_ONE_REG_REG_RO_ONE_MASK)
+/*! @} */
+
+/*! @name REG_RO_TWO_REG -  */
+/*! @{ */
+
+#define BUCK11_REG_RO_TWO_REG_REG_RO_TWO_MASK    (0xFFU)
+#define BUCK11_REG_RO_TWO_REG_REG_RO_TWO_SHIFT   (0U)
+/*! REG_RO_TWO - REG_RO_TWO */
+#define BUCK11_REG_RO_TWO_REG_REG_RO_TWO(x)      (((uint8_t)(((uint8_t)(x)) << BUCK11_REG_RO_TWO_REG_REG_RO_TWO_SHIFT)) & BUCK11_REG_RO_TWO_REG_REG_RO_TWO_MASK)
+/*! @} */
+
+/*! @name REG_RO_THREE_REG -  */
+/*! @{ */
+
+#define BUCK11_REG_RO_THREE_REG_REG_RO_THREE_MASK (0xFFU)
+#define BUCK11_REG_RO_THREE_REG_REG_RO_THREE_SHIFT (0U)
+/*! REG_RO_THREE - REG_RO_THREE */
+#define BUCK11_REG_RO_THREE_REG_REG_RO_THREE(x)  (((uint8_t)(((uint8_t)(x)) << BUCK11_REG_RO_THREE_REG_REG_RO_THREE_SHIFT)) & BUCK11_REG_RO_THREE_REG_REG_RO_THREE_MASK)
+/*! @} */
+
+/*! @name REG_RO_FOUR_REG -  */
+/*! @{ */
+
+#define BUCK11_REG_RO_FOUR_REG_REG_RO_FOUR_MASK  (0xFFU)
+#define BUCK11_REG_RO_FOUR_REG_REG_RO_FOUR_SHIFT (0U)
+/*! REG_RO_FOUR - REG_RO_FOUR */
+#define BUCK11_REG_RO_FOUR_REG_REG_RO_FOUR(x)    (((uint8_t)(((uint8_t)(x)) << BUCK11_REG_RO_FOUR_REG_REG_RO_FOUR_SHIFT)) & BUCK11_REG_RO_FOUR_REG_REG_RO_FOUR_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL_REG -  */
+/*! @{ */
+
+#define BUCK11_SYS_CTRL_REG_REG_SYS_CTRL_MASK    (0xFFU)
+#define BUCK11_SYS_CTRL_REG_REG_SYS_CTRL_SHIFT   (0U)
+/*! REG_SYS_CTRL - REG_SYS_CTRL */
+#define BUCK11_SYS_CTRL_REG_REG_SYS_CTRL(x)      (((uint8_t)(((uint8_t)(x)) << BUCK11_SYS_CTRL_REG_REG_SYS_CTRL_SHIFT)) & BUCK11_SYS_CTRL_REG_REG_SYS_CTRL_MASK)
+/*! @} */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_ONE_RW_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_MASK (0xFFU)
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_SHIFT (0U)
+/*! REG_BUCK_BYPASS_SOC_CTRL_ONE_RW - REG_BUCK_BYPASS_SOC_CTRL_ONE_RW */
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_SHIFT)) & BUCK11_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_MASK)
+/*! @} */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_TWO_RW_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_MASK (0xFFU)
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_SHIFT (0U)
+/*! REG_BUCK_BYPASS_SOC_CTRL_TWO_RW - REG_BUCK_BYPASS_SOC_CTRL_TWO_RW */
+#define BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_SHIFT)) & BUCK11_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_SHIFT (0U)
+/*! REG_BUCK_CTRL_ONE - REG_BUCK_CTRL_ONE */
+#define BUCK11_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_SHIFT)) & BUCK11_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_SHIFT (0U)
+/*! REG_BUCK_CTRL_TWO - REG_BUCK_CTRL_TWO */
+#define BUCK11_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_SHIFT)) & BUCK11_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_SHIFT (0U)
+/*! REG_BUCK_CTRL_THREE - REG_BUCK_CTRL_THREE */
+#define BUCK11_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_SHIFT)) & BUCK11_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_SHIFT (0U)
+/*! REG_BUCK_CTRL_FOUR - REG_BUCK_CTRL_FOUR */
+#define BUCK11_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_SHIFT)) & BUCK11_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_SHIFT (0U)
+/*! REG_BUCK_CTRL_FIVE - REG_BUCK_CTRL_FIVE */
+#define BUCK11_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_SHIFT)) & BUCK11_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_SHIFT (0U)
+/*! REG_BUCK_CTRL_SIX - REG_BUCK_CTRL_SIX */
+#define BUCK11_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_SHIFT)) & BUCK11_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SEVEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_SEVEN - REG_BUCK_CTRL_SEVEN */
+#define BUCK11_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_SHIFT)) & BUCK11_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_EIGHT_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_SHIFT (0U)
+/*! REG_BUCK_CTRL_EIGHT - REG_BUCK_CTRL_EIGHT */
+#define BUCK11_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_SHIFT)) & BUCK11_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_NINE_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_SHIFT (0U)
+/*! REG_BUCK_CTRL_NINE - REG_BUCK_CTRL_NINE */
+#define BUCK11_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_SHIFT)) & BUCK11_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_TEN - REG_BUCK_CTRL_TEN */
+#define BUCK11_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_SHIFT)) & BUCK11_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_ELEVEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_ELEVEN - REG_BUCK_CTRL_ELEVEN */
+#define BUCK11_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_SHIFT)) & BUCK11_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TWELVE_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_SHIFT (0U)
+/*! REG_BUCK_CTRL_TWELVE - REG_BUCK_CTRL_TWELVE */
+#define BUCK11_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_SHIFT)) & BUCK11_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_THIRTEEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_THIRTEEN - REG_BUCK_CTRL_THIRTEEN */
+#define BUCK11_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_SHIFT)) & BUCK11_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FOURTEEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_FOURTEEN - REG_BUCK_CTRL_FOURTEEN */
+#define BUCK11_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_SHIFT)) & BUCK11_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FIFTEEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_FIFTEEN - REG_BUCK_CTRL_FIFTEEN */
+#define BUCK11_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_SHIFT)) & BUCK11_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SIXTEEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_SIXTEEN - REG_BUCK_CTRL_SIXTEEN */
+#define BUCK11_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_SHIFT)) & BUCK11_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SEVENTEEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_SEVENTEEN - REG_BUCK_CTRL_SEVENTEEN */
+#define BUCK11_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_SHIFT)) & BUCK11_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_EIGHTEEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_EXT_BG_CAL_CODE_MASK (0xFU)
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_EXT_BG_CAL_CODE_SHIFT (0U)
+/*! EXT_BG_CAL_CODE - External calibration code for BG */
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_EXT_BG_CAL_CODE(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_EIGHTEEN_REG_EXT_BG_CAL_CODE_SHIFT)) & BUCK11_BUCK_CTRL_EIGHTEEN_REG_EXT_BG_CAL_CODE_MASK)
+
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_SEL_BG_CAL_CODE_MASK (0x10U)
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_SEL_BG_CAL_CODE_SHIFT (4U)
+/*! SEL_BG_CAL_CODE - Select internal or external calibration code for BG */
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_SEL_BG_CAL_CODE(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_EIGHTEEN_REG_SEL_BG_CAL_CODE_SHIFT)) & BUCK11_BUCK_CTRL_EIGHTEEN_REG_SEL_BG_CAL_CODE_MASK)
+
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_SHORT_C11_ENB_MASK (0x20U)
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_SHORT_C11_ENB_SHIFT (5U)
+/*! SHORT_C11_ENB - Short switch enable signal for internal C11 */
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_SHORT_C11_ENB(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_EIGHTEEN_REG_SHORT_C11_ENB_SHIFT)) & BUCK11_BUCK_CTRL_EIGHTEEN_REG_SHORT_C11_ENB_MASK)
+
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_MASK (0xC0U)
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_SHIFT (6U)
+/*! LPBG_TRIM - Bandgap temperature curve trimming */
+#define BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_SHIFT)) & BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_NINTEEN_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_NINTEEN - REG_BUCK_CTRL_NINTEEN */
+#define BUCK11_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_SHIFT)) & BUCK11_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TWENTY_REG -  */
+/*! @{ */
+
+#define BUCK11_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_MASK (0xFFU)
+#define BUCK11_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_SHIFT (0U)
+/*! REG_BUCK_CTRL_TWENTY - REG_BUCK_CTRL_TWENTY */
+#define BUCK11_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY(x) (((uint8_t)(((uint8_t)(x)) << BUCK11_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_SHIFT)) & BUCK11_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BUCK11_Register_Masks */
+
+
+/* BUCK11 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral BUCK11 base address */
+  #define BUCK11_BASE                              (0x55002000u)
+  /** Peripheral BUCK11 base address */
+  #define BUCK11_BASE_NS                           (0x45002000u)
+  /** Peripheral BUCK11 base pointer */
+  #define BUCK11                                   ((BUCK11_Type *)BUCK11_BASE)
+  /** Peripheral BUCK11 base pointer */
+  #define BUCK11_NS                                ((BUCK11_Type *)BUCK11_BASE_NS)
+  /** Array initializer of BUCK11 peripheral base addresses */
+  #define BUCK11_BASE_ADDRS                        { BUCK11_BASE }
+  /** Array initializer of BUCK11 peripheral base pointers */
+  #define BUCK11_BASE_PTRS                         { BUCK11 }
+  /** Array initializer of BUCK11 peripheral base addresses */
+  #define BUCK11_BASE_ADDRS_NS                     { BUCK11_BASE_NS }
+  /** Array initializer of BUCK11 peripheral base pointers */
+  #define BUCK11_BASE_PTRS_NS                      { BUCK11_NS }
+#else
+  /** Peripheral BUCK11 base address */
+  #define BUCK11_BASE                              (0x45002000u)
+  /** Peripheral BUCK11 base pointer */
+  #define BUCK11                                   ((BUCK11_Type *)BUCK11_BASE)
+  /** Array initializer of BUCK11 peripheral base addresses */
+  #define BUCK11_BASE_ADDRS                        { BUCK11_BASE }
+  /** Array initializer of BUCK11 peripheral base pointers */
+  #define BUCK11_BASE_PTRS                         { BUCK11 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group BUCK11_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- BUCK18 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BUCK18_Peripheral_Access_Layer BUCK18 Peripheral Access Layer
+ * @{
+ */
+
+/** BUCK18 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[96];
+  __I  uint8_t BUCK_BYPASS_SOC_CTRL_ONE_RO_REG;    /**< offset: 0x60 */
+  __I  uint8_t BUCK_BYPASS_SOC_CTRL_TWO_RO_REG;    /**< offset: 0x61 */
+  __I  uint8_t REG_RO_ONE_REG;                     /**< offset: 0x62 */
+  __I  uint8_t REG_RO_TWO_REG;                     /**< offset: 0x63 */
+  __I  uint8_t REG_RO_THREE_REG;                   /**< offset: 0x64 */
+  __I  uint8_t REG_RO_FOUR_REG;                    /**< offset: 0x65 */
+  __IO uint8_t SYS_CTRL_REG;                       /**< offset: 0x66 */
+  __IO uint8_t BUCK_BYPASS_SOC_CTRL_ONE_RW_REG;    /**< offset: 0x67 */
+  __IO uint8_t BUCK_BYPASS_SOC_CTRL_TWO_RW_REG;    /**< offset: 0x68 */
+  __IO uint8_t BUCK_CTRL_ONE_REG;                  /**< offset: 0x69 */
+  __IO uint8_t BUCK_CTRL_TWO_REG;                  /**< offset: 0x6A */
+  __IO uint8_t BUCK_CTRL_THREE_REG;                /**< offset: 0x6B */
+  __IO uint8_t BUCK_CTRL_FOUR_REG;                 /**< offset: 0x6C */
+  __IO uint8_t BUCK_CTRL_FIVE_REG;                 /**< offset: 0x6D */
+  __IO uint8_t BUCK_CTRL_SIX_REG;                  /**< offset: 0x6E */
+  __IO uint8_t BUCK_CTRL_SEVEN_REG;                /**< offset: 0x6F */
+  __IO uint8_t BUCK_CTRL_EIGHT_REG;                /**< offset: 0x70 */
+  __IO uint8_t BUCK_CTRL_NINE_REG;                 /**< offset: 0x71 */
+  __IO uint8_t BUCK_CTRL_TEN_REG;                  /**< offset: 0x72 */
+  __IO uint8_t BUCK_CTRL_ELEVEN_REG;               /**< offset: 0x73 */
+  __IO uint8_t BUCK_CTRL_TWELVE_REG;               /**< offset: 0x74 */
+  __IO uint8_t BUCK_CTRL_THIRTEEN_REG;             /**< offset: 0x75 */
+  __IO uint8_t BUCK_CTRL_FOURTEEN_REG;             /**< offset: 0x76 */
+  __IO uint8_t BUCK_CTRL_FIFTEEN_REG;              /**< offset: 0x77 */
+  __IO uint8_t BUCK_CTRL_SIXTEEN_REG;              /**< offset: 0x78 */
+  __IO uint8_t BUCK_CTRL_SEVENTEEN_REG;            /**< offset: 0x79 */
+  __IO uint8_t BUCK_CTRL_EIGHTEEN_REG;             /**< offset: 0x7A */
+  __IO uint8_t BUCK_CTRL_NINTEEN_REG;              /**< offset: 0x7B */
+  __IO uint8_t BUCK_CTRL_TWENTY_REG;               /**< offset: 0x7C */
+} BUCK18_Type;
+
+/* ----------------------------------------------------------------------------
+   -- BUCK18 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BUCK18_Register_Masks BUCK18 Register Masks
+ * @{
+ */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_MASK (0xFFU)
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_SHIFT (0U)
+/*! BUCK_BYPASS_SOC_CTRL_ONE_RO - BUCK_BYPASS_SOC_CTRL_ONE_RO */
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_SHIFT)) & BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RO_REG_BUCK_BYPASS_SOC_CTRL_ONE_RO_MASK)
+/*! @} */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_TWO_RO_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_MASK (0xFFU)
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_SHIFT (0U)
+/*! BUCK_BYPASS_SOC_CTRL_TWO_RO - BUCK_BYPASS_SOC_CTRL_TWO_RO */
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_SHIFT)) & BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RO_REG_BUCK_BYPASS_SOC_CTRL_TWO_RO_MASK)
+/*! @} */
+
+/*! @name REG_RO_ONE_REG -  */
+/*! @{ */
+
+#define BUCK18_REG_RO_ONE_REG_REG_RO_ONE_MASK    (0xFFU)
+#define BUCK18_REG_RO_ONE_REG_REG_RO_ONE_SHIFT   (0U)
+/*! REG_RO_ONE - REG_RO_ONE */
+#define BUCK18_REG_RO_ONE_REG_REG_RO_ONE(x)      (((uint8_t)(((uint8_t)(x)) << BUCK18_REG_RO_ONE_REG_REG_RO_ONE_SHIFT)) & BUCK18_REG_RO_ONE_REG_REG_RO_ONE_MASK)
+/*! @} */
+
+/*! @name REG_RO_TWO_REG -  */
+/*! @{ */
+
+#define BUCK18_REG_RO_TWO_REG_REG_RO_TWO_MASK    (0xFFU)
+#define BUCK18_REG_RO_TWO_REG_REG_RO_TWO_SHIFT   (0U)
+/*! REG_RO_TWO - REG_RO_TWO */
+#define BUCK18_REG_RO_TWO_REG_REG_RO_TWO(x)      (((uint8_t)(((uint8_t)(x)) << BUCK18_REG_RO_TWO_REG_REG_RO_TWO_SHIFT)) & BUCK18_REG_RO_TWO_REG_REG_RO_TWO_MASK)
+/*! @} */
+
+/*! @name REG_RO_THREE_REG -  */
+/*! @{ */
+
+#define BUCK18_REG_RO_THREE_REG_REG_RO_THREE_MASK (0xFFU)
+#define BUCK18_REG_RO_THREE_REG_REG_RO_THREE_SHIFT (0U)
+/*! REG_RO_THREE - REG_RO_THREE */
+#define BUCK18_REG_RO_THREE_REG_REG_RO_THREE(x)  (((uint8_t)(((uint8_t)(x)) << BUCK18_REG_RO_THREE_REG_REG_RO_THREE_SHIFT)) & BUCK18_REG_RO_THREE_REG_REG_RO_THREE_MASK)
+/*! @} */
+
+/*! @name REG_RO_FOUR_REG -  */
+/*! @{ */
+
+#define BUCK18_REG_RO_FOUR_REG_REG_RO_FOUR_MASK  (0xFFU)
+#define BUCK18_REG_RO_FOUR_REG_REG_RO_FOUR_SHIFT (0U)
+/*! REG_RO_FOUR - REG_RO_FOUR */
+#define BUCK18_REG_RO_FOUR_REG_REG_RO_FOUR(x)    (((uint8_t)(((uint8_t)(x)) << BUCK18_REG_RO_FOUR_REG_REG_RO_FOUR_SHIFT)) & BUCK18_REG_RO_FOUR_REG_REG_RO_FOUR_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL_REG -  */
+/*! @{ */
+
+#define BUCK18_SYS_CTRL_REG_REG_SYS_CTRL_MASK    (0xFFU)
+#define BUCK18_SYS_CTRL_REG_REG_SYS_CTRL_SHIFT   (0U)
+/*! REG_SYS_CTRL - REG_SYS_CTRL */
+#define BUCK18_SYS_CTRL_REG_REG_SYS_CTRL(x)      (((uint8_t)(((uint8_t)(x)) << BUCK18_SYS_CTRL_REG_REG_SYS_CTRL_SHIFT)) & BUCK18_SYS_CTRL_REG_REG_SYS_CTRL_MASK)
+/*! @} */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_ONE_RW_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_MASK (0xFFU)
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_SHIFT (0U)
+/*! REG_BUCK_BYPASS_SOC_CTRL_ONE_RW - REG_BUCK_BYPASS_SOC_CTRL_ONE_RW */
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_SHIFT)) & BUCK18_BUCK_BYPASS_SOC_CTRL_ONE_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_ONE_RW_MASK)
+/*! @} */
+
+/*! @name BUCK_BYPASS_SOC_CTRL_TWO_RW_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_MASK (0xFFU)
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_SHIFT (0U)
+/*! REG_BUCK_BYPASS_SOC_CTRL_TWO_RW - REG_BUCK_BYPASS_SOC_CTRL_TWO_RW */
+#define BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_SHIFT)) & BUCK18_BUCK_BYPASS_SOC_CTRL_TWO_RW_REG_REG_BUCK_BYPASS_SOC_CTRL_TWO_RW_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_SHIFT (0U)
+/*! REG_BUCK_CTRL_ONE - REG_BUCK_CTRL_ONE */
+#define BUCK18_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_SHIFT)) & BUCK18_BUCK_CTRL_ONE_REG_REG_BUCK_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_SHIFT (0U)
+/*! REG_BUCK_CTRL_TWO - REG_BUCK_CTRL_TWO */
+#define BUCK18_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_SHIFT)) & BUCK18_BUCK_CTRL_TWO_REG_REG_BUCK_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_SHIFT (0U)
+/*! REG_BUCK_CTRL_THREE - REG_BUCK_CTRL_THREE */
+#define BUCK18_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_SHIFT)) & BUCK18_BUCK_CTRL_THREE_REG_REG_BUCK_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_SHIFT (0U)
+/*! REG_BUCK_CTRL_FOUR - REG_BUCK_CTRL_FOUR */
+#define BUCK18_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_SHIFT)) & BUCK18_BUCK_CTRL_FOUR_REG_REG_BUCK_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_SHIFT (0U)
+/*! REG_BUCK_CTRL_FIVE - REG_BUCK_CTRL_FIVE */
+#define BUCK18_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_SHIFT)) & BUCK18_BUCK_CTRL_FIVE_REG_REG_BUCK_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_SHIFT (0U)
+/*! REG_BUCK_CTRL_SIX - REG_BUCK_CTRL_SIX */
+#define BUCK18_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_SHIFT)) & BUCK18_BUCK_CTRL_SIX_REG_REG_BUCK_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SEVEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_SEVEN - REG_BUCK_CTRL_SEVEN */
+#define BUCK18_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_SHIFT)) & BUCK18_BUCK_CTRL_SEVEN_REG_REG_BUCK_CTRL_SEVEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_EIGHT_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_SHIFT (0U)
+/*! REG_BUCK_CTRL_EIGHT - REG_BUCK_CTRL_EIGHT */
+#define BUCK18_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_SHIFT)) & BUCK18_BUCK_CTRL_EIGHT_REG_REG_BUCK_CTRL_EIGHT_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_NINE_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_SHIFT (0U)
+/*! REG_BUCK_CTRL_NINE - REG_BUCK_CTRL_NINE */
+#define BUCK18_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_SHIFT)) & BUCK18_BUCK_CTRL_NINE_REG_REG_BUCK_CTRL_NINE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_TEN - REG_BUCK_CTRL_TEN */
+#define BUCK18_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_SHIFT)) & BUCK18_BUCK_CTRL_TEN_REG_REG_BUCK_CTRL_TEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_ELEVEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_ELEVEN - REG_BUCK_CTRL_ELEVEN */
+#define BUCK18_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_SHIFT)) & BUCK18_BUCK_CTRL_ELEVEN_REG_REG_BUCK_CTRL_ELEVEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TWELVE_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_SHIFT (0U)
+/*! REG_BUCK_CTRL_TWELVE - REG_BUCK_CTRL_TWELVE */
+#define BUCK18_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_SHIFT)) & BUCK18_BUCK_CTRL_TWELVE_REG_REG_BUCK_CTRL_TWELVE_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_THIRTEEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_THIRTEEN - REG_BUCK_CTRL_THIRTEEN */
+#define BUCK18_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_SHIFT)) & BUCK18_BUCK_CTRL_THIRTEEN_REG_REG_BUCK_CTRL_THIRTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FOURTEEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_FOURTEEN - REG_BUCK_CTRL_FOURTEEN */
+#define BUCK18_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_SHIFT)) & BUCK18_BUCK_CTRL_FOURTEEN_REG_REG_BUCK_CTRL_FOURTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_FIFTEEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_FIFTEEN - REG_BUCK_CTRL_FIFTEEN */
+#define BUCK18_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_SHIFT)) & BUCK18_BUCK_CTRL_FIFTEEN_REG_REG_BUCK_CTRL_FIFTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SIXTEEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_SIXTEEN - REG_BUCK_CTRL_SIXTEEN */
+#define BUCK18_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_SHIFT)) & BUCK18_BUCK_CTRL_SIXTEEN_REG_REG_BUCK_CTRL_SIXTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_SEVENTEEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_SEVENTEEN - REG_BUCK_CTRL_SEVENTEEN */
+#define BUCK18_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_SHIFT)) & BUCK18_BUCK_CTRL_SEVENTEEN_REG_REG_BUCK_CTRL_SEVENTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_EIGHTEEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_EIGHTEEN_REG_REG_BUCK_CTRL_EIGHTEEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_EIGHTEEN_REG_REG_BUCK_CTRL_EIGHTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_EIGHTEEN - REG_BUCK_CTRL_EIGHTEEN */
+#define BUCK18_BUCK_CTRL_EIGHTEEN_REG_REG_BUCK_CTRL_EIGHTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_EIGHTEEN_REG_REG_BUCK_CTRL_EIGHTEEN_SHIFT)) & BUCK18_BUCK_CTRL_EIGHTEEN_REG_REG_BUCK_CTRL_EIGHTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_NINTEEN_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_SHIFT (0U)
+/*! REG_BUCK_CTRL_NINTEEN - REG_BUCK_CTRL_NINTEEN */
+#define BUCK18_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_SHIFT)) & BUCK18_BUCK_CTRL_NINTEEN_REG_REG_BUCK_CTRL_NINTEEN_MASK)
+/*! @} */
+
+/*! @name BUCK_CTRL_TWENTY_REG -  */
+/*! @{ */
+
+#define BUCK18_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_MASK (0xFFU)
+#define BUCK18_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_SHIFT (0U)
+/*! REG_BUCK_CTRL_TWENTY - REG_BUCK_CTRL_TWENTY */
+#define BUCK18_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY(x) (((uint8_t)(((uint8_t)(x)) << BUCK18_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_SHIFT)) & BUCK18_BUCK_CTRL_TWENTY_REG_REG_BUCK_CTRL_TWENTY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BUCK18_Register_Masks */
+
+
+/* BUCK18 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral BUCK18 base address */
+  #define BUCK18_BASE                              (0x55002000u)
+  /** Peripheral BUCK18 base address */
+  #define BUCK18_BASE_NS                           (0x45002000u)
+  /** Peripheral BUCK18 base pointer */
+  #define BUCK18                                   ((BUCK18_Type *)BUCK18_BASE)
+  /** Peripheral BUCK18 base pointer */
+  #define BUCK18_NS                                ((BUCK18_Type *)BUCK18_BASE_NS)
+  /** Array initializer of BUCK18 peripheral base addresses */
+  #define BUCK18_BASE_ADDRS                        { BUCK18_BASE }
+  /** Array initializer of BUCK18 peripheral base pointers */
+  #define BUCK18_BASE_PTRS                         { BUCK18 }
+  /** Array initializer of BUCK18 peripheral base addresses */
+  #define BUCK18_BASE_ADDRS_NS                     { BUCK18_BASE_NS }
+  /** Array initializer of BUCK18 peripheral base pointers */
+  #define BUCK18_BASE_PTRS_NS                      { BUCK18_NS }
+#else
+  /** Peripheral BUCK18 base address */
+  #define BUCK18_BASE                              (0x45002000u)
+  /** Peripheral BUCK18 base pointer */
+  #define BUCK18                                   ((BUCK18_Type *)BUCK18_BASE)
+  /** Array initializer of BUCK18 peripheral base addresses */
+  #define BUCK18_BASE_ADDRS                        { BUCK18_BASE }
+  /** Array initializer of BUCK18 peripheral base pointers */
+  #define BUCK18_BASE_PTRS                         { BUCK18 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group BUCK18_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CACHE64_CTRL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** CACHE64_CTRL - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2048];
+  __IO uint32_t CCR;                               /**< Cache control register, offset: 0x800 */
+  __IO uint32_t CLCR;                              /**< Cache line control register, offset: 0x804 */
+  __IO uint32_t CSAR;                              /**< Cache search address register, offset: 0x808 */
+  __IO uint32_t CCVR;                              /**< Cache read/write value register, offset: 0x80C */
+} CACHE64_CTRL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CACHE64_CTRL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks
+ * @{
+ */
+
+/*! @name CCR - Cache control register */
+/*! @{ */
+
+#define CACHE64_CTRL_CCR_ENCACHE_MASK            (0x1U)
+#define CACHE64_CTRL_CCR_ENCACHE_SHIFT           (0U)
+/*! ENCACHE - Cache enable
+ *  0b0..Cache disabled
+ *  0b1..Cache enabled
+ */
+#define CACHE64_CTRL_CCR_ENCACHE(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK)
+
+#define CACHE64_CTRL_CCR_ENWRBUF_MASK            (0x2U)
+#define CACHE64_CTRL_CCR_ENWRBUF_SHIFT           (1U)
+/*! ENWRBUF - Enable Write Buffer
+ *  0b0..Write buffer disabled
+ *  0b1..Write buffer enabled
+ */
+#define CACHE64_CTRL_CCR_ENWRBUF(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK)
+
+#define CACHE64_CTRL_CCR_INVW0_MASK              (0x1000000U)
+#define CACHE64_CTRL_CCR_INVW0_SHIFT             (24U)
+/*! INVW0 - Invalidate Way 0
+ *  0b0..No operation
+ *  0b1..When setting the GO bit, invalidate all lines in way 0.
+ */
+#define CACHE64_CTRL_CCR_INVW0(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK)
+
+#define CACHE64_CTRL_CCR_PUSHW0_MASK             (0x2000000U)
+#define CACHE64_CTRL_CCR_PUSHW0_SHIFT            (25U)
+/*! PUSHW0 - Push Way 0
+ *  0b0..No operation
+ *  0b1..When setting the GO bit, push all modified lines in way 0
+ */
+#define CACHE64_CTRL_CCR_PUSHW0(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK)
+
+#define CACHE64_CTRL_CCR_INVW1_MASK              (0x4000000U)
+#define CACHE64_CTRL_CCR_INVW1_SHIFT             (26U)
+/*! INVW1 - Invalidate Way 1
+ *  0b0..No operation
+ *  0b1..When setting the GO bit, invalidate all lines in way 1
+ */
+#define CACHE64_CTRL_CCR_INVW1(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
+
+#define CACHE64_CTRL_CCR_PUSHW1_MASK             (0x8000000U)
+#define CACHE64_CTRL_CCR_PUSHW1_SHIFT            (27U)
+/*! PUSHW1 - Push Way 1
+ *  0b0..No operation
+ *  0b1..When setting the GO bit, push all modified lines in way 1
+ */
+#define CACHE64_CTRL_CCR_PUSHW1(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK)
+
+#define CACHE64_CTRL_CCR_GO_MASK                 (0x80000000U)
+#define CACHE64_CTRL_CCR_GO_SHIFT                (31U)
+/*! GO - Initiate Cache Command
+ *  0b0..Write: no effect. Read: no cache command active.
+ *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
+ */
+#define CACHE64_CTRL_CCR_GO(x)                   (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
+/*! @} */
+
+/*! @name CLCR - Cache line control register */
+/*! @{ */
+
+#define CACHE64_CTRL_CLCR_LGO_MASK               (0x1U)
+#define CACHE64_CTRL_CLCR_LGO_SHIFT              (0U)
+/*! LGO - Initiate Cache Line Command
+ *  0b0..Write: no effect. Read: no line command active.
+ *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
+ */
+#define CACHE64_CTRL_CLCR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
+
+#define CACHE64_CTRL_CLCR_CACHEADDR_MASK         (0x3FFCU)
+#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT        (2U)
+/*! CACHEADDR - Cache address */
+#define CACHE64_CTRL_CLCR_CACHEADDR(x)           (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK)
+
+#define CACHE64_CTRL_CLCR_WSEL_MASK              (0x4000U)
+#define CACHE64_CTRL_CLCR_WSEL_SHIFT             (14U)
+/*! WSEL - Way select
+ *  0b0..Way 0
+ *  0b1..Way 1
+ */
+#define CACHE64_CTRL_CLCR_WSEL(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK)
+
+#define CACHE64_CTRL_CLCR_TDSEL_MASK             (0x10000U)
+#define CACHE64_CTRL_CLCR_TDSEL_SHIFT            (16U)
+/*! TDSEL - Tag/Data Select
+ *  0b0..Data
+ *  0b1..Tag
+ */
+#define CACHE64_CTRL_CLCR_TDSEL(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK)
+
+#define CACHE64_CTRL_CLCR_LCIVB_MASK             (0x100000U)
+#define CACHE64_CTRL_CLCR_LCIVB_SHIFT            (20U)
+/*! LCIVB - Line Command Initial Valid Bit */
+#define CACHE64_CTRL_CLCR_LCIVB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK)
+
+#define CACHE64_CTRL_CLCR_LCIMB_MASK             (0x200000U)
+#define CACHE64_CTRL_CLCR_LCIMB_SHIFT            (21U)
+/*! LCIMB - Line Command Initial Modified Bit */
+#define CACHE64_CTRL_CLCR_LCIMB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK)
+
+#define CACHE64_CTRL_CLCR_LCWAY_MASK             (0x400000U)
+#define CACHE64_CTRL_CLCR_LCWAY_SHIFT            (22U)
+/*! LCWAY - Line Command Way */
+#define CACHE64_CTRL_CLCR_LCWAY(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK)
+
+#define CACHE64_CTRL_CLCR_LCMD_MASK              (0x3000000U)
+#define CACHE64_CTRL_CLCR_LCMD_SHIFT             (24U)
+/*! LCMD - Line Command
+ *  0b00..Search and read or write
+ *  0b01..Invalidate
+ *  0b10..Push
+ *  0b11..Clear
+ */
+#define CACHE64_CTRL_CLCR_LCMD(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK)
+
+#define CACHE64_CTRL_CLCR_LADSEL_MASK            (0x4000000U)
+#define CACHE64_CTRL_CLCR_LADSEL_SHIFT           (26U)
+/*! LADSEL - Line Address Select
+ *  0b0..Cache address
+ *  0b1..Physical address
+ */
+#define CACHE64_CTRL_CLCR_LADSEL(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
+
+#define CACHE64_CTRL_CLCR_LACC_MASK              (0x8000000U)
+#define CACHE64_CTRL_CLCR_LACC_SHIFT             (27U)
+/*! LACC - Line access type
+ *  0b0..Read
+ *  0b1..Write
+ */
+#define CACHE64_CTRL_CLCR_LACC(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
+/*! @} */
+
+/*! @name CSAR - Cache search address register */
+/*! @{ */
+
+#define CACHE64_CTRL_CSAR_LGO_MASK               (0x1U)
+#define CACHE64_CTRL_CSAR_LGO_SHIFT              (0U)
+/*! LGO - Initiate Cache Line Command
+ *  0b0..Write: no effect. Read: no line command active.
+ *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
+ */
+#define CACHE64_CTRL_CSAR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK)
+
+#define CACHE64_CTRL_CSAR_PHYADDR27_1_MASK       (0xFFFFFFEU)
+#define CACHE64_CTRL_CSAR_PHYADDR27_1_SHIFT      (1U)
+/*! PHYADDR27_1 - Physical Address */
+#define CACHE64_CTRL_CSAR_PHYADDR27_1(x)         (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR27_1_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR27_1_MASK)
+
+#define CACHE64_CTRL_CSAR_PHYADDR31_29_MASK      (0xE0000000U)
+#define CACHE64_CTRL_CSAR_PHYADDR31_29_SHIFT     (29U)
+/*! PHYADDR31_29 - Physical Address */
+#define CACHE64_CTRL_CSAR_PHYADDR31_29(x)        (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR31_29_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR31_29_MASK)
+/*! @} */
+
+/*! @name CCVR - Cache read/write value register */
+/*! @{ */
+
+#define CACHE64_CTRL_CCVR_DATA_MASK              (0xFFFFFFFFU)
+#define CACHE64_CTRL_CCVR_DATA_SHIFT             (0U)
+/*! DATA - Cache read/write Data */
+#define CACHE64_CTRL_CCVR_DATA(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CACHE64_CTRL_Register_Masks */
+
+
+/* CACHE64_CTRL - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CACHE64_CTRL0 base address */
+  #define CACHE64_CTRL0_BASE                       (0x50033000u)
+  /** Peripheral CACHE64_CTRL0 base address */
+  #define CACHE64_CTRL0_BASE_NS                    (0x40033000u)
+  /** Peripheral CACHE64_CTRL0 base pointer */
+  #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
+  /** Peripheral CACHE64_CTRL0 base pointer */
+  #define CACHE64_CTRL0_NS                         ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS)
+  /** Peripheral CACHE64_CTRL1 base address */
+  #define CACHE64_CTRL1_BASE                       (0x50034000u)
+  /** Peripheral CACHE64_CTRL1 base address */
+  #define CACHE64_CTRL1_BASE_NS                    (0x40034000u)
+  /** Peripheral CACHE64_CTRL1 base pointer */
+  #define CACHE64_CTRL1                            ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
+  /** Peripheral CACHE64_CTRL1 base pointer */
+  #define CACHE64_CTRL1_NS                         ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE_NS)
+  /** Array initializer of CACHE64_CTRL peripheral base addresses */
+  #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
+  /** Array initializer of CACHE64_CTRL peripheral base pointers */
+  #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0, CACHE64_CTRL1 }
+  /** Array initializer of CACHE64_CTRL peripheral base addresses */
+  #define CACHE64_CTRL_BASE_ADDRS_NS               { CACHE64_CTRL0_BASE_NS, CACHE64_CTRL1_BASE_NS }
+  /** Array initializer of CACHE64_CTRL peripheral base pointers */
+  #define CACHE64_CTRL_BASE_PTRS_NS                { CACHE64_CTRL0_NS, CACHE64_CTRL1_NS }
+#else
+  /** Peripheral CACHE64_CTRL0 base address */
+  #define CACHE64_CTRL0_BASE                       (0x40033000u)
+  /** Peripheral CACHE64_CTRL0 base pointer */
+  #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
+  /** Peripheral CACHE64_CTRL1 base address */
+  #define CACHE64_CTRL1_BASE                       (0x40034000u)
+  /** Peripheral CACHE64_CTRL1 base pointer */
+  #define CACHE64_CTRL1                            ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
+  /** Array initializer of CACHE64_CTRL peripheral base addresses */
+  #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
+  /** Array initializer of CACHE64_CTRL peripheral base pointers */
+  #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0, CACHE64_CTRL1 }
+#endif
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+/** CACHE64_CTRL physical memory base address */
+ #define CACHE64_CTRL_PHYMEM_BASES                { 0x18000000u, 0x38000000u }
+/** CACHE64_CTRL physical memory size */
+ #define CACHE64_CTRL_PHYMEM_SIZES                { 0x08000000u, 0x08000000u }
+/** CACHE64_CTRL physical memory base address */
+ #define CACHE64_CTRL_PHYMEM_BASES_NS             { 0x08000000u, 0x28000000u }
+/** CACHE64_CTRL physical memory size */
+ #define CACHE64_CTRL_PHYMEM_SIZES_NS             { 0x08000000u, 0x08000000u }
+#else
+/** CACHE64_CTRL physical memory base address */
+ #define CACHE64_CTRL_PHYMEM_BASES                { 0x08000000u, 0x28000000u }
+/** CACHE64_CTRL physical memory size */
+ #define CACHE64_CTRL_PHYMEM_SIZES                { 0x08000000u, 0x08000000u }
+#endif
+/* Backward compatibility */
+#define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYADDR31_29_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CACHE64_POLSEL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer
+ * @{
+ */
+
+/** CACHE64_POLSEL - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[20];
+  __IO uint32_t REG0_TOP;                          /**< Region 0 Top Boundary, offset: 0x14 */
+  __IO uint32_t REG1_TOP;                          /**< Region 1 Top Boundary, offset: 0x18 */
+  __IO uint32_t POLSEL;                            /**< Policy Select, offset: 0x1C */
+} CACHE64_POLSEL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CACHE64_POLSEL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks
+ * @{
+ */
+
+/*! @name REG0_TOP - Region 0 Top Boundary */
+/*! @{ */
+
+#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK    (0x7FFFC00U)
+#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT   (10U)
+/*! REG0_TOP - Upper limit of Region 0 */
+#define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK)
+/*! @} */
+
+/*! @name REG1_TOP - Region 1 Top Boundary */
+/*! @{ */
+
+#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK    (0x7FFFC00U)
+#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT   (10U)
+/*! REG1_TOP - Upper limit of Region 1 */
+#define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK)
+/*! @} */
+
+/*! @name POLSEL - Policy Select */
+/*! @{ */
+
+#define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK   (0x3U)
+#define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT  (0U)
+/*! REG0_POLICY - Policy Select for Region 0
+ *  0b00..Non-cache
+ *  0b01..Write-thru
+ *  0b10..Write-back
+ *  0b11..Invalid
+ */
+#define CACHE64_POLSEL_POLSEL_REG0_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK)
+
+#define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK   (0xCU)
+#define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT  (2U)
+/*! REG1_POLICY - Policy Select for Region 0
+ *  0b00..Non-cache
+ *  0b01..Write-thru
+ *  0b10..Write-back
+ *  0b11..Invalid
+ */
+#define CACHE64_POLSEL_POLSEL_REG1_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK)
+
+#define CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK  (0x30U)
+#define CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT (4U)
+/*! REG02_POLICY - Policy Select for Region 0
+ *  0b00..Non-cache
+ *  0b01..Write-thru
+ *  0b10..Write-back
+ *  0b11..Invalid
+ */
+#define CACHE64_POLSEL_POLSEL_REG02_POLICY(x)    (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CACHE64_POLSEL_Register_Masks */
+
+
+/* CACHE64_POLSEL - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CACHE64_POLSEL0 base address */
+  #define CACHE64_POLSEL0_BASE                     (0x50033000u)
+  /** Peripheral CACHE64_POLSEL0 base address */
+  #define CACHE64_POLSEL0_BASE_NS                  (0x40033000u)
+  /** Peripheral CACHE64_POLSEL0 base pointer */
+  #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
+  /** Peripheral CACHE64_POLSEL0 base pointer */
+  #define CACHE64_POLSEL0_NS                       ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS)
+  /** Peripheral CACHE64_POLSEL1 base address */
+  #define CACHE64_POLSEL1_BASE                     (0x50034000u)
+  /** Peripheral CACHE64_POLSEL1 base address */
+  #define CACHE64_POLSEL1_BASE_NS                  (0x40034000u)
+  /** Peripheral CACHE64_POLSEL1 base pointer */
+  #define CACHE64_POLSEL1                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE)
+  /** Peripheral CACHE64_POLSEL1 base pointer */
+  #define CACHE64_POLSEL1_NS                       ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE_NS)
+  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
+  #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE, CACHE64_POLSEL1_BASE }
+  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
+  #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0, CACHE64_POLSEL1 }
+  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
+  #define CACHE64_POLSEL_BASE_ADDRS_NS             { CACHE64_POLSEL0_BASE_NS, CACHE64_POLSEL1_BASE_NS }
+  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
+  #define CACHE64_POLSEL_BASE_PTRS_NS              { CACHE64_POLSEL0_NS, CACHE64_POLSEL1_NS }
+#else
+  /** Peripheral CACHE64_POLSEL0 base address */
+  #define CACHE64_POLSEL0_BASE                     (0x40033000u)
+  /** Peripheral CACHE64_POLSEL0 base pointer */
+  #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
+  /** Peripheral CACHE64_POLSEL1 base address */
+  #define CACHE64_POLSEL1_BASE                     (0x40034000u)
+  /** Peripheral CACHE64_POLSEL1 base pointer */
+  #define CACHE64_POLSEL1                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE)
+  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
+  #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE, CACHE64_POLSEL1_BASE }
+  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
+  #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0, CACHE64_POLSEL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BYPASS_SOC_PD_CTRL_RO_REG;          /**< offset: 0x0 */
+  __I  uint8_t BYPASS_SOC_CTRL_ONE_RO_REG;         /**< offset: 0x1 */
+  __I  uint8_t BYPASS_SOC_CTRL_TWO_RO_REG;         /**< offset: 0x2 */
+  __I  uint8_t BYPASS_RFU_CTRL_ONE_RO_REG;         /**< offset: 0x3 */
+  __I  uint8_t REG_RO_ONE_REG;                     /**< offset: 0x4 */
+  __I  uint8_t REG_RO_TWO_REG;                     /**< offset: 0x5 */
+  __I  uint8_t REG_RO_THREE_REG;                   /**< offset: 0x6 */
+  __I  uint8_t REG_RO_FOUR_REG;                    /**< offset: 0x7 */
+  __I  uint8_t REG_RO_FIVE_REG;                    /**< offset: 0x8 */
+  __I  uint8_t REG_RO_SIX_REG;                     /**< offset: 0x9 */
+  __IO uint8_t SW_RESET_B_REG;                     /**< offset: 0xA */
+  __IO uint8_t SYS_CTRL_REG;                       /**< offset: 0xB */
+  __IO uint8_t SYS_CTRL_PWR_OPT_SEL_REG;           /**< offset: 0xC */
+  __IO uint8_t BYPASS_SOC_PD_CTRL_RW_REG;          /**< offset: 0xD */
+  __IO uint8_t BYPASS_SOC_CTRL_ONE_RW_REG;         /**< offset: 0xE */
+  __IO uint8_t BYPASS_SOC_CTRL_TWO_RW_REG;         /**< offset: 0xF */
+  __IO uint8_t BYPASS_RFU_CTRL_ONE_RW_REG;         /**< offset: 0x10 */
+  __IO uint8_t PD_CTRL_ONE_REG;                    /**< offset: 0x11 */
+  __IO uint8_t PD_CTRL_TWO_REG;                    /**< offset: 0x12 */
+  __IO uint8_t SLP_CTRL_ONE_REG;                   /**< offset: 0x13 */
+  __IO uint8_t SLP_CTRL_TWO_REG;                   /**< offset: 0x14 */
+  __IO uint8_t BG_CTRL_REG;                        /**< offset: 0x15 */
+  __IO uint8_t CPREG_CTRL_ONE_REG;                 /**< offset: 0x16 */
+  __IO uint8_t CPREG_CTRL_TWO_REG;                 /**< offset: 0x17 */
+  __IO uint8_t CPREG_CTRL_THREE_REG;               /**< offset: 0x18 */
+  __IO uint8_t PSEN_CTRL_ONE_REG;                  /**< offset: 0x19 */
+  __IO uint8_t PSEN_CTRL_TWO_REG;                  /**< offset: 0x1A */
+  __IO uint8_t TSEN_CTRL_ONE_REG;                  /**< offset: 0x1B */
+  __IO uint8_t TSEN_CTRL_THREE_REG;                /**< offset: 0x1C */
+  __IO uint8_t ADC_CTRL_ONE_REG;                   /**< offset: 0x1D */
+  __IO uint8_t RCAL_CTRL_ONE_REG;                  /**< offset: 0x1E */
+  __IO uint8_t RCAL_CTRL_TWO_REG;                  /**< offset: 0x1F */
+  __IO uint8_t XTAL_CTRL_ONE_REG;                  /**< offset: 0x20 */
+  __IO uint8_t XTAL_CTRL_TWO_REG;                  /**< offset: 0x21 */
+  __IO uint8_t XTAL_CTRL_THREE_REG;                /**< offset: 0x22 */
+  __IO uint8_t XTAL_CTRL_FOUR_REG;                 /**< offset: 0x23 */
+  __IO uint8_t XTAL_CTRL_FIVE_REG;                 /**< offset: 0x24 */
+  __IO uint8_t XTAL_CTRL_SIX_REG;                  /**< offset: 0x25 */
+  __IO uint8_t XTAL_CTRL_SEVEN_REG;                /**< offset: 0x26 */
+  __IO uint8_t XTAL_CTRL_EIGHT_REG;                /**< offset: 0x27 */
+  __IO uint8_t XTAL_CTRL_NINE_REG;                 /**< offset: 0x28 */
+  __IO uint8_t XTAL_CTRL_TEN_REG;                  /**< offset: 0x29 */
+  __IO uint8_t XTAL_CTRL_ELEVEN_REG;               /**< offset: 0x2A */
+  __IO uint8_t XTAL_CTRL_TWELVE_REG;               /**< offset: 0x2B */
+  __IO uint8_t XTAL_CTRL_THIRTEEN_REG;             /**< offset: 0x2C */
+  __IO uint8_t XTAL_CTRL_FOURTEEN_REG;             /**< offset: 0x2D */
+  __IO uint8_t XTAL_CTRL_FIFTEEN_REG;              /**< offset: 0x2E */
+  __IO uint8_t T1_CTRL_RSVD_HI_REG;                /**< offset: 0x2F */
+  __IO uint8_t T1_CTRL_RSVD_LO_REG;                /**< offset: 0x30 */
+  __IO uint8_t GPIO_CTRL_REG;                      /**< offset: 0x31 */
+  __IO uint8_t ATEST_CTRL_ONE_REG;                 /**< offset: 0x32 */
+  __IO uint8_t ATEST_CTRL_TWO_REG;                 /**< offset: 0x33 */
+  __IO uint8_t ATEST_CTRL_THREE_REG;               /**< offset: 0x34 */
+  __IO uint8_t ATEST_CTRL_FOUR_REG;                /**< offset: 0x35 */
+  __IO uint8_t ATEST_CTRL_FIVE_REG;                /**< offset: 0x36 */
+  __IO uint8_t ATEST_CTRL_SIX_REG;                 /**< offset: 0x37 */
+  __IO uint8_t ATEST_CTRL_SEVEN_REG;               /**< offset: 0x38 */
+  __IO uint8_t RESERVED_LO_ONE_REG;                /**< offset: 0x39 */
+  __IO uint8_t RESERVED_LO_TWO_REG;                /**< offset: 0x3A */
+  __IO uint8_t RESERVED_HI_ONE_REG;                /**< offset: 0x3B */
+  __IO uint8_t RESERVED_HI_TWO_REG;                /**< offset: 0x3C */
+} CAU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/*! @name BYPASS_SOC_PD_CTRL_RO_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_SOC_PD_CTRL_RO_REG_BYPASS_SOC_PD_CTRL_RO_MASK (0xFFU)
+#define CAU_BYPASS_SOC_PD_CTRL_RO_REG_BYPASS_SOC_PD_CTRL_RO_SHIFT (0U)
+/*! BYPASS_SOC_PD_CTRL_RO - BYPASS_SOC_PD_CTRL_RO */
+#define CAU_BYPASS_SOC_PD_CTRL_RO_REG_BYPASS_SOC_PD_CTRL_RO(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_SOC_PD_CTRL_RO_REG_BYPASS_SOC_PD_CTRL_RO_SHIFT)) & CAU_BYPASS_SOC_PD_CTRL_RO_REG_BYPASS_SOC_PD_CTRL_RO_MASK)
+/*! @} */
+
+/*! @name BYPASS_SOC_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_SOC_CTRL_ONE_RO_REG_BYPASS_SOC_CTRL_ONE_RO_MASK (0xFFU)
+#define CAU_BYPASS_SOC_CTRL_ONE_RO_REG_BYPASS_SOC_CTRL_ONE_RO_SHIFT (0U)
+/*! BYPASS_SOC_CTRL_ONE_RO - BYPASS_SOC_CTRL_ONE_RO */
+#define CAU_BYPASS_SOC_CTRL_ONE_RO_REG_BYPASS_SOC_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_SOC_CTRL_ONE_RO_REG_BYPASS_SOC_CTRL_ONE_RO_SHIFT)) & CAU_BYPASS_SOC_CTRL_ONE_RO_REG_BYPASS_SOC_CTRL_ONE_RO_MASK)
+/*! @} */
+
+/*! @name BYPASS_SOC_CTRL_TWO_RO_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_SOC_CTRL_TWO_RO_REG_BYPASS_SOC_CTRL_TWO_RO_MASK (0xFFU)
+#define CAU_BYPASS_SOC_CTRL_TWO_RO_REG_BYPASS_SOC_CTRL_TWO_RO_SHIFT (0U)
+/*! BYPASS_SOC_CTRL_TWO_RO - BYPASS_SOC_CTRL_TWO_RO */
+#define CAU_BYPASS_SOC_CTRL_TWO_RO_REG_BYPASS_SOC_CTRL_TWO_RO(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_SOC_CTRL_TWO_RO_REG_BYPASS_SOC_CTRL_TWO_RO_SHIFT)) & CAU_BYPASS_SOC_CTRL_TWO_RO_REG_BYPASS_SOC_CTRL_TWO_RO_MASK)
+/*! @} */
+
+/*! @name BYPASS_RFU_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_RFU_CTRL_ONE_RO_REG_BYPASS_RFU_CTRL_ONE_RO_MASK (0xFFU)
+#define CAU_BYPASS_RFU_CTRL_ONE_RO_REG_BYPASS_RFU_CTRL_ONE_RO_SHIFT (0U)
+/*! BYPASS_RFU_CTRL_ONE_RO - BYPASS_RFU_CTRL_ONE_RO */
+#define CAU_BYPASS_RFU_CTRL_ONE_RO_REG_BYPASS_RFU_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_RFU_CTRL_ONE_RO_REG_BYPASS_RFU_CTRL_ONE_RO_SHIFT)) & CAU_BYPASS_RFU_CTRL_ONE_RO_REG_BYPASS_RFU_CTRL_ONE_RO_MASK)
+/*! @} */
+
+/*! @name REG_RO_ONE_REG -  */
+/*! @{ */
+
+#define CAU_REG_RO_ONE_REG_REG_RO_ONE_MASK       (0xFFU)
+#define CAU_REG_RO_ONE_REG_REG_RO_ONE_SHIFT      (0U)
+/*! REG_RO_ONE - REG_RO_ONE */
+#define CAU_REG_RO_ONE_REG_REG_RO_ONE(x)         (((uint8_t)(((uint8_t)(x)) << CAU_REG_RO_ONE_REG_REG_RO_ONE_SHIFT)) & CAU_REG_RO_ONE_REG_REG_RO_ONE_MASK)
+/*! @} */
+
+/*! @name REG_RO_TWO_REG -  */
+/*! @{ */
+
+#define CAU_REG_RO_TWO_REG_REG_RO_TWO_MASK       (0xFFU)
+#define CAU_REG_RO_TWO_REG_REG_RO_TWO_SHIFT      (0U)
+/*! REG_RO_TWO - REG_RO_TWO */
+#define CAU_REG_RO_TWO_REG_REG_RO_TWO(x)         (((uint8_t)(((uint8_t)(x)) << CAU_REG_RO_TWO_REG_REG_RO_TWO_SHIFT)) & CAU_REG_RO_TWO_REG_REG_RO_TWO_MASK)
+/*! @} */
+
+/*! @name REG_RO_THREE_REG -  */
+/*! @{ */
+
+#define CAU_REG_RO_THREE_REG_REG_RO_THREE_MASK   (0xFFU)
+#define CAU_REG_RO_THREE_REG_REG_RO_THREE_SHIFT  (0U)
+/*! REG_RO_THREE - REG_RO_THREE */
+#define CAU_REG_RO_THREE_REG_REG_RO_THREE(x)     (((uint8_t)(((uint8_t)(x)) << CAU_REG_RO_THREE_REG_REG_RO_THREE_SHIFT)) & CAU_REG_RO_THREE_REG_REG_RO_THREE_MASK)
+/*! @} */
+
+/*! @name REG_RO_FOUR_REG -  */
+/*! @{ */
+
+#define CAU_REG_RO_FOUR_REG_REG_RO_FOUR_MASK     (0xFFU)
+#define CAU_REG_RO_FOUR_REG_REG_RO_FOUR_SHIFT    (0U)
+/*! REG_RO_FOUR - REG_RO_FOUR */
+#define CAU_REG_RO_FOUR_REG_REG_RO_FOUR(x)       (((uint8_t)(((uint8_t)(x)) << CAU_REG_RO_FOUR_REG_REG_RO_FOUR_SHIFT)) & CAU_REG_RO_FOUR_REG_REG_RO_FOUR_MASK)
+/*! @} */
+
+/*! @name REG_RO_FIVE_REG -  */
+/*! @{ */
+
+#define CAU_REG_RO_FIVE_REG_REG_RO_FIVE_MASK     (0xFFU)
+#define CAU_REG_RO_FIVE_REG_REG_RO_FIVE_SHIFT    (0U)
+/*! REG_RO_FIVE - REG_RO_FIVE */
+#define CAU_REG_RO_FIVE_REG_REG_RO_FIVE(x)       (((uint8_t)(((uint8_t)(x)) << CAU_REG_RO_FIVE_REG_REG_RO_FIVE_SHIFT)) & CAU_REG_RO_FIVE_REG_REG_RO_FIVE_MASK)
+/*! @} */
+
+/*! @name REG_RO_SIX_REG -  */
+/*! @{ */
+
+#define CAU_REG_RO_SIX_REG_REG_RO_SIX_MASK       (0xFFU)
+#define CAU_REG_RO_SIX_REG_REG_RO_SIX_SHIFT      (0U)
+/*! REG_RO_SIX - REG_RO_SIX */
+#define CAU_REG_RO_SIX_REG_REG_RO_SIX(x)         (((uint8_t)(((uint8_t)(x)) << CAU_REG_RO_SIX_REG_REG_RO_SIX_SHIFT)) & CAU_REG_RO_SIX_REG_REG_RO_SIX_MASK)
+/*! @} */
+
+/*! @name SW_RESET_B_REG -  */
+/*! @{ */
+
+#define CAU_SW_RESET_B_REG_SW_RESET_B_MASK       (0xFFU)
+#define CAU_SW_RESET_B_REG_SW_RESET_B_SHIFT      (0U)
+/*! SW_RESET_B - SW_RESET_B */
+#define CAU_SW_RESET_B_REG_SW_RESET_B(x)         (((uint8_t)(((uint8_t)(x)) << CAU_SW_RESET_B_REG_SW_RESET_B_SHIFT)) & CAU_SW_RESET_B_REG_SW_RESET_B_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL_REG -  */
+/*! @{ */
+
+#define CAU_SYS_CTRL_REG_SYS_CTRL_MASK           (0xFFU)
+#define CAU_SYS_CTRL_REG_SYS_CTRL_SHIFT          (0U)
+/*! SYS_CTRL - SYS_CTRL */
+#define CAU_SYS_CTRL_REG_SYS_CTRL(x)             (((uint8_t)(((uint8_t)(x)) << CAU_SYS_CTRL_REG_SYS_CTRL_SHIFT)) & CAU_SYS_CTRL_REG_SYS_CTRL_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL_PWR_OPT_SEL_REG -  */
+/*! @{ */
+
+#define CAU_SYS_CTRL_PWR_OPT_SEL_REG_SYS_CTRL_PWR_OPT_SEL_MASK (0xFFU)
+#define CAU_SYS_CTRL_PWR_OPT_SEL_REG_SYS_CTRL_PWR_OPT_SEL_SHIFT (0U)
+/*! SYS_CTRL_PWR_OPT_SEL - SYS_CTRL_PWR_OPT_SEL */
+#define CAU_SYS_CTRL_PWR_OPT_SEL_REG_SYS_CTRL_PWR_OPT_SEL(x) (((uint8_t)(((uint8_t)(x)) << CAU_SYS_CTRL_PWR_OPT_SEL_REG_SYS_CTRL_PWR_OPT_SEL_SHIFT)) & CAU_SYS_CTRL_PWR_OPT_SEL_REG_SYS_CTRL_PWR_OPT_SEL_MASK)
+/*! @} */
+
+/*! @name BYPASS_SOC_PD_CTRL_RW_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_SOC_PD_CTRL_RW_REG_BYPASS_SOC_PD_CTRL_RW_MASK (0xFFU)
+#define CAU_BYPASS_SOC_PD_CTRL_RW_REG_BYPASS_SOC_PD_CTRL_RW_SHIFT (0U)
+/*! BYPASS_SOC_PD_CTRL_RW - BYPASS_SOC_PD_CTRL_RW */
+#define CAU_BYPASS_SOC_PD_CTRL_RW_REG_BYPASS_SOC_PD_CTRL_RW(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_SOC_PD_CTRL_RW_REG_BYPASS_SOC_PD_CTRL_RW_SHIFT)) & CAU_BYPASS_SOC_PD_CTRL_RW_REG_BYPASS_SOC_PD_CTRL_RW_MASK)
+/*! @} */
+
+/*! @name BYPASS_SOC_CTRL_ONE_RW_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_SOC_CTRL_ONE_RW_REG_BYPASS_SOC_CTRL_ONE_RW_MASK (0xFFU)
+#define CAU_BYPASS_SOC_CTRL_ONE_RW_REG_BYPASS_SOC_CTRL_ONE_RW_SHIFT (0U)
+/*! BYPASS_SOC_CTRL_ONE_RW - BYPASS_SOC_CTRL_ONE_RW */
+#define CAU_BYPASS_SOC_CTRL_ONE_RW_REG_BYPASS_SOC_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_SOC_CTRL_ONE_RW_REG_BYPASS_SOC_CTRL_ONE_RW_SHIFT)) & CAU_BYPASS_SOC_CTRL_ONE_RW_REG_BYPASS_SOC_CTRL_ONE_RW_MASK)
+/*! @} */
+
+/*! @name BYPASS_SOC_CTRL_TWO_RW_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_SOC_CTRL_TWO_RW_REG_BYPASS_SOC_CTRL_TWO_RW_MASK (0xFFU)
+#define CAU_BYPASS_SOC_CTRL_TWO_RW_REG_BYPASS_SOC_CTRL_TWO_RW_SHIFT (0U)
+/*! BYPASS_SOC_CTRL_TWO_RW - BYPASS_SOC_CTRL_TWO_RW */
+#define CAU_BYPASS_SOC_CTRL_TWO_RW_REG_BYPASS_SOC_CTRL_TWO_RW(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_SOC_CTRL_TWO_RW_REG_BYPASS_SOC_CTRL_TWO_RW_SHIFT)) & CAU_BYPASS_SOC_CTRL_TWO_RW_REG_BYPASS_SOC_CTRL_TWO_RW_MASK)
+/*! @} */
+
+/*! @name BYPASS_RFU_CTRL_ONE_RW_REG -  */
+/*! @{ */
+
+#define CAU_BYPASS_RFU_CTRL_ONE_RW_REG_BYPASS_RFU_CTRL_ONE_RW_MASK (0xFFU)
+#define CAU_BYPASS_RFU_CTRL_ONE_RW_REG_BYPASS_RFU_CTRL_ONE_RW_SHIFT (0U)
+/*! BYPASS_RFU_CTRL_ONE_RW - BYPASS_RFU_CTRL_ONE_RW */
+#define CAU_BYPASS_RFU_CTRL_ONE_RW_REG_BYPASS_RFU_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << CAU_BYPASS_RFU_CTRL_ONE_RW_REG_BYPASS_RFU_CTRL_ONE_RW_SHIFT)) & CAU_BYPASS_RFU_CTRL_ONE_RW_REG_BYPASS_RFU_CTRL_ONE_RW_MASK)
+/*! @} */
+
+/*! @name PD_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_PD_CTRL_ONE_REG_PD_CTRL_ONE_MASK     (0xFFU)
+#define CAU_PD_CTRL_ONE_REG_PD_CTRL_ONE_SHIFT    (0U)
+/*! PD_CTRL_ONE - PD_CTRL_ONE */
+#define CAU_PD_CTRL_ONE_REG_PD_CTRL_ONE(x)       (((uint8_t)(((uint8_t)(x)) << CAU_PD_CTRL_ONE_REG_PD_CTRL_ONE_SHIFT)) & CAU_PD_CTRL_ONE_REG_PD_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name PD_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define CAU_PD_CTRL_TWO_REG_PD_CTRL_TWO_MASK     (0xFFU)
+#define CAU_PD_CTRL_TWO_REG_PD_CTRL_TWO_SHIFT    (0U)
+/*! PD_CTRL_TWO - PD_CTRL_TWO */
+#define CAU_PD_CTRL_TWO_REG_PD_CTRL_TWO(x)       (((uint8_t)(((uint8_t)(x)) << CAU_PD_CTRL_TWO_REG_PD_CTRL_TWO_SHIFT)) & CAU_PD_CTRL_TWO_REG_PD_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name SLP_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_SLP_CTRL_ONE_REG_SLP_CTRL_ONE_MASK   (0xFFU)
+#define CAU_SLP_CTRL_ONE_REG_SLP_CTRL_ONE_SHIFT  (0U)
+/*! SLP_CTRL_ONE - SLP_CTRL_ONE */
+#define CAU_SLP_CTRL_ONE_REG_SLP_CTRL_ONE(x)     (((uint8_t)(((uint8_t)(x)) << CAU_SLP_CTRL_ONE_REG_SLP_CTRL_ONE_SHIFT)) & CAU_SLP_CTRL_ONE_REG_SLP_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name SLP_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define CAU_SLP_CTRL_TWO_REG_SLP_CTRL_TWO_MASK   (0xFFU)
+#define CAU_SLP_CTRL_TWO_REG_SLP_CTRL_TWO_SHIFT  (0U)
+/*! SLP_CTRL_TWO - SLP_CTRL_TWO */
+#define CAU_SLP_CTRL_TWO_REG_SLP_CTRL_TWO(x)     (((uint8_t)(((uint8_t)(x)) << CAU_SLP_CTRL_TWO_REG_SLP_CTRL_TWO_SHIFT)) & CAU_SLP_CTRL_TWO_REG_SLP_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name BG_CTRL_REG -  */
+/*! @{ */
+
+#define CAU_BG_CTRL_REG_BG_CTRL_MASK             (0xFFU)
+#define CAU_BG_CTRL_REG_BG_CTRL_SHIFT            (0U)
+/*! BG_CTRL - BG_CTRL */
+#define CAU_BG_CTRL_REG_BG_CTRL(x)               (((uint8_t)(((uint8_t)(x)) << CAU_BG_CTRL_REG_BG_CTRL_SHIFT)) & CAU_BG_CTRL_REG_BG_CTRL_MASK)
+/*! @} */
+
+/*! @name CPREG_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_CPREG_CTRL_ONE_REG_CPREG_CTRL_ONE_MASK (0xFFU)
+#define CAU_CPREG_CTRL_ONE_REG_CPREG_CTRL_ONE_SHIFT (0U)
+/*! CPREG_CTRL_ONE - CPREG_CTRL_ONE */
+#define CAU_CPREG_CTRL_ONE_REG_CPREG_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << CAU_CPREG_CTRL_ONE_REG_CPREG_CTRL_ONE_SHIFT)) & CAU_CPREG_CTRL_ONE_REG_CPREG_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name CPREG_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define CAU_CPREG_CTRL_TWO_REG_CPREG_CTRL_TWO_MASK (0xFFU)
+#define CAU_CPREG_CTRL_TWO_REG_CPREG_CTRL_TWO_SHIFT (0U)
+/*! CPREG_CTRL_TWO - CPREG_CTRL_TWO */
+#define CAU_CPREG_CTRL_TWO_REG_CPREG_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << CAU_CPREG_CTRL_TWO_REG_CPREG_CTRL_TWO_SHIFT)) & CAU_CPREG_CTRL_TWO_REG_CPREG_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name CPREG_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define CAU_CPREG_CTRL_THREE_REG_CPREG_CTRL_THREE_MASK (0xFFU)
+#define CAU_CPREG_CTRL_THREE_REG_CPREG_CTRL_THREE_SHIFT (0U)
+/*! CPREG_CTRL_THREE - CPREG_CTRL_THREE */
+#define CAU_CPREG_CTRL_THREE_REG_CPREG_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << CAU_CPREG_CTRL_THREE_REG_CPREG_CTRL_THREE_SHIFT)) & CAU_CPREG_CTRL_THREE_REG_CPREG_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name PSEN_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_PSEN_CTRL_ONE_REG_PSEN_CTRL_ONE_MASK (0xFFU)
+#define CAU_PSEN_CTRL_ONE_REG_PSEN_CTRL_ONE_SHIFT (0U)
+/*! PSEN_CTRL_ONE - PSEN_CTRL_ONE */
+#define CAU_PSEN_CTRL_ONE_REG_PSEN_CTRL_ONE(x)   (((uint8_t)(((uint8_t)(x)) << CAU_PSEN_CTRL_ONE_REG_PSEN_CTRL_ONE_SHIFT)) & CAU_PSEN_CTRL_ONE_REG_PSEN_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name PSEN_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define CAU_PSEN_CTRL_TWO_REG_PSEN_CTRL_TWO_MASK (0xFFU)
+#define CAU_PSEN_CTRL_TWO_REG_PSEN_CTRL_TWO_SHIFT (0U)
+/*! PSEN_CTRL_TWO - PSEN_CTRL_TWO */
+#define CAU_PSEN_CTRL_TWO_REG_PSEN_CTRL_TWO(x)   (((uint8_t)(((uint8_t)(x)) << CAU_PSEN_CTRL_TWO_REG_PSEN_CTRL_TWO_SHIFT)) & CAU_PSEN_CTRL_TWO_REG_PSEN_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name TSEN_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_TSEN_CTRL_ONE_REG_TSEN_CTRL_ONE_MASK (0xFFU)
+#define CAU_TSEN_CTRL_ONE_REG_TSEN_CTRL_ONE_SHIFT (0U)
+/*! TSEN_CTRL_ONE - TSEN_CTRL_ONE */
+#define CAU_TSEN_CTRL_ONE_REG_TSEN_CTRL_ONE(x)   (((uint8_t)(((uint8_t)(x)) << CAU_TSEN_CTRL_ONE_REG_TSEN_CTRL_ONE_SHIFT)) & CAU_TSEN_CTRL_ONE_REG_TSEN_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name TSEN_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define CAU_TSEN_CTRL_THREE_REG_TSEN_CTRL_TWO_MASK (0xFFU)
+#define CAU_TSEN_CTRL_THREE_REG_TSEN_CTRL_TWO_SHIFT (0U)
+/*! TSEN_CTRL_TWO - TSEN_CTRL_TWO */
+#define CAU_TSEN_CTRL_THREE_REG_TSEN_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << CAU_TSEN_CTRL_THREE_REG_TSEN_CTRL_TWO_SHIFT)) & CAU_TSEN_CTRL_THREE_REG_TSEN_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name ADC_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_ADC_CTRL_ONE_REG_ADC_CTRL_MASK       (0xFFU)
+#define CAU_ADC_CTRL_ONE_REG_ADC_CTRL_SHIFT      (0U)
+/*! ADC_CTRL - ADC_CTRL */
+#define CAU_ADC_CTRL_ONE_REG_ADC_CTRL(x)         (((uint8_t)(((uint8_t)(x)) << CAU_ADC_CTRL_ONE_REG_ADC_CTRL_SHIFT)) & CAU_ADC_CTRL_ONE_REG_ADC_CTRL_MASK)
+/*! @} */
+
+/*! @name RCAL_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_RCAL_CTRL_ONE_REG_RCAL_CTRL_ONE_MASK (0xFFU)
+#define CAU_RCAL_CTRL_ONE_REG_RCAL_CTRL_ONE_SHIFT (0U)
+/*! RCAL_CTRL_ONE - RCAL_CTRL_ONE */
+#define CAU_RCAL_CTRL_ONE_REG_RCAL_CTRL_ONE(x)   (((uint8_t)(((uint8_t)(x)) << CAU_RCAL_CTRL_ONE_REG_RCAL_CTRL_ONE_SHIFT)) & CAU_RCAL_CTRL_ONE_REG_RCAL_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name RCAL_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define CAU_RCAL_CTRL_TWO_REG_RCAL_CTRL_TWO_MASK (0xFFU)
+#define CAU_RCAL_CTRL_TWO_REG_RCAL_CTRL_TWO_SHIFT (0U)
+/*! RCAL_CTRL_TWO - RCAL_CTRL_TWO */
+#define CAU_RCAL_CTRL_TWO_REG_RCAL_CTRL_TWO(x)   (((uint8_t)(((uint8_t)(x)) << CAU_RCAL_CTRL_TWO_REG_RCAL_CTRL_TWO_SHIFT)) & CAU_RCAL_CTRL_TWO_REG_RCAL_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_ONE_REG_XTAL_CTRL_ONE_MASK (0xFFU)
+#define CAU_XTAL_CTRL_ONE_REG_XTAL_CTRL_ONE_SHIFT (0U)
+/*! XTAL_CTRL_ONE - XTAL_CTRL_ONE */
+#define CAU_XTAL_CTRL_ONE_REG_XTAL_CTRL_ONE(x)   (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_ONE_REG_XTAL_CTRL_ONE_SHIFT)) & CAU_XTAL_CTRL_ONE_REG_XTAL_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_TWO_REG_XTAL_CTRL_TWO_MASK (0xFFU)
+#define CAU_XTAL_CTRL_TWO_REG_XTAL_CTRL_TWO_SHIFT (0U)
+/*! XTAL_CTRL_TWO - XTAL_CTRL_TWO */
+#define CAU_XTAL_CTRL_TWO_REG_XTAL_CTRL_TWO(x)   (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_TWO_REG_XTAL_CTRL_TWO_SHIFT)) & CAU_XTAL_CTRL_TWO_REG_XTAL_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_THREE_REG_XTAL_CTRL_THREE_MASK (0xFFU)
+#define CAU_XTAL_CTRL_THREE_REG_XTAL_CTRL_THREE_SHIFT (0U)
+/*! XTAL_CTRL_THREE - XTAL_CTRL_THREE */
+#define CAU_XTAL_CTRL_THREE_REG_XTAL_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_THREE_REG_XTAL_CTRL_THREE_SHIFT)) & CAU_XTAL_CTRL_THREE_REG_XTAL_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_FOUR_REG_XTAL_CTRL_FOUR_MASK (0xFFU)
+#define CAU_XTAL_CTRL_FOUR_REG_XTAL_CTRL_FOUR_SHIFT (0U)
+/*! XTAL_CTRL_FOUR - XTAL_CTRL_FOUR */
+#define CAU_XTAL_CTRL_FOUR_REG_XTAL_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_FOUR_REG_XTAL_CTRL_FOUR_SHIFT)) & CAU_XTAL_CTRL_FOUR_REG_XTAL_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_FIVE_REG_XTAL_CTRL_FIVE_MASK (0xFFU)
+#define CAU_XTAL_CTRL_FIVE_REG_XTAL_CTRL_FIVE_SHIFT (0U)
+/*! XTAL_CTRL_FIVE - XTAL_CTRL_FIVE */
+#define CAU_XTAL_CTRL_FIVE_REG_XTAL_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_FIVE_REG_XTAL_CTRL_FIVE_SHIFT)) & CAU_XTAL_CTRL_FIVE_REG_XTAL_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_SIX_REG_XTAL_CTRL_SIX_MASK (0xFFU)
+#define CAU_XTAL_CTRL_SIX_REG_XTAL_CTRL_SIX_SHIFT (0U)
+/*! XTAL_CTRL_SIX - XTAL_CTRL_SIX */
+#define CAU_XTAL_CTRL_SIX_REG_XTAL_CTRL_SIX(x)   (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_SIX_REG_XTAL_CTRL_SIX_SHIFT)) & CAU_XTAL_CTRL_SIX_REG_XTAL_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_SEVEN_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_SEVEN_REG_XTAL_CTRL_SEVEN_MASK (0xFFU)
+#define CAU_XTAL_CTRL_SEVEN_REG_XTAL_CTRL_SEVEN_SHIFT (0U)
+/*! XTAL_CTRL_SEVEN - XTAL_CTRL_SEVEN */
+#define CAU_XTAL_CTRL_SEVEN_REG_XTAL_CTRL_SEVEN(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_SEVEN_REG_XTAL_CTRL_SEVEN_SHIFT)) & CAU_XTAL_CTRL_SEVEN_REG_XTAL_CTRL_SEVEN_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_EIGHT_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_EIGHT_REG_XTAL_CTRL_EIGHT_MASK (0xFFU)
+#define CAU_XTAL_CTRL_EIGHT_REG_XTAL_CTRL_EIGHT_SHIFT (0U)
+/*! XTAL_CTRL_EIGHT - XTAL_CTRL_EIGHT */
+#define CAU_XTAL_CTRL_EIGHT_REG_XTAL_CTRL_EIGHT(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_EIGHT_REG_XTAL_CTRL_EIGHT_SHIFT)) & CAU_XTAL_CTRL_EIGHT_REG_XTAL_CTRL_EIGHT_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_NINE_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_NINE_REG_XTAL_CTRL_NINE_MASK (0xFFU)
+#define CAU_XTAL_CTRL_NINE_REG_XTAL_CTRL_NINE_SHIFT (0U)
+/*! XTAL_CTRL_NINE - XTAL_CTRL_NINE */
+#define CAU_XTAL_CTRL_NINE_REG_XTAL_CTRL_NINE(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_NINE_REG_XTAL_CTRL_NINE_SHIFT)) & CAU_XTAL_CTRL_NINE_REG_XTAL_CTRL_NINE_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_TEN_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_TEN_REG_XTAL_CTRL_TEN_MASK (0xFFU)
+#define CAU_XTAL_CTRL_TEN_REG_XTAL_CTRL_TEN_SHIFT (0U)
+/*! XTAL_CTRL_TEN - XTAL_CTRL_TEN */
+#define CAU_XTAL_CTRL_TEN_REG_XTAL_CTRL_TEN(x)   (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_TEN_REG_XTAL_CTRL_TEN_SHIFT)) & CAU_XTAL_CTRL_TEN_REG_XTAL_CTRL_TEN_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_ELEVEN_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_ELEVEN_REG_XTAL_CTRL_ELEVEN_MASK (0xFFU)
+#define CAU_XTAL_CTRL_ELEVEN_REG_XTAL_CTRL_ELEVEN_SHIFT (0U)
+/*! XTAL_CTRL_ELEVEN - XTAL_CTRL_ELEVEN */
+#define CAU_XTAL_CTRL_ELEVEN_REG_XTAL_CTRL_ELEVEN(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_ELEVEN_REG_XTAL_CTRL_ELEVEN_SHIFT)) & CAU_XTAL_CTRL_ELEVEN_REG_XTAL_CTRL_ELEVEN_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_TWELVE_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_TWELVE_REG_XTAL_CTRL_TWELVE_MASK (0xFFU)
+#define CAU_XTAL_CTRL_TWELVE_REG_XTAL_CTRL_TWELVE_SHIFT (0U)
+/*! XTAL_CTRL_TWELVE - XTAL_CTRL_TWELVE */
+#define CAU_XTAL_CTRL_TWELVE_REG_XTAL_CTRL_TWELVE(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_TWELVE_REG_XTAL_CTRL_TWELVE_SHIFT)) & CAU_XTAL_CTRL_TWELVE_REG_XTAL_CTRL_TWELVE_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_THIRTEEN_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_THIRTEEN_REG_XTAL_CTRL_THIRTEEN_MASK (0xFFU)
+#define CAU_XTAL_CTRL_THIRTEEN_REG_XTAL_CTRL_THIRTEEN_SHIFT (0U)
+/*! XTAL_CTRL_THIRTEEN - XTAL_CTRL_THIRTEEN */
+#define CAU_XTAL_CTRL_THIRTEEN_REG_XTAL_CTRL_THIRTEEN(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_THIRTEEN_REG_XTAL_CTRL_THIRTEEN_SHIFT)) & CAU_XTAL_CTRL_THIRTEEN_REG_XTAL_CTRL_THIRTEEN_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_FOURTEEN_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_FOURTEEN_REG_XTAL_CTRL_FOURTEEN_MASK (0xFFU)
+#define CAU_XTAL_CTRL_FOURTEEN_REG_XTAL_CTRL_FOURTEEN_SHIFT (0U)
+/*! XTAL_CTRL_FOURTEEN - XTAL_CTRL_FOURTEEN */
+#define CAU_XTAL_CTRL_FOURTEEN_REG_XTAL_CTRL_FOURTEEN(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_FOURTEEN_REG_XTAL_CTRL_FOURTEEN_SHIFT)) & CAU_XTAL_CTRL_FOURTEEN_REG_XTAL_CTRL_FOURTEEN_MASK)
+/*! @} */
+
+/*! @name XTAL_CTRL_FIFTEEN_REG -  */
+/*! @{ */
+
+#define CAU_XTAL_CTRL_FIFTEEN_REG_XTAL_CTRL_FIFTEEN_MASK (0xFFU)
+#define CAU_XTAL_CTRL_FIFTEEN_REG_XTAL_CTRL_FIFTEEN_SHIFT (0U)
+/*! XTAL_CTRL_FIFTEEN - XTAL_CTRL_FIFTEEN */
+#define CAU_XTAL_CTRL_FIFTEEN_REG_XTAL_CTRL_FIFTEEN(x) (((uint8_t)(((uint8_t)(x)) << CAU_XTAL_CTRL_FIFTEEN_REG_XTAL_CTRL_FIFTEEN_SHIFT)) & CAU_XTAL_CTRL_FIFTEEN_REG_XTAL_CTRL_FIFTEEN_MASK)
+/*! @} */
+
+/*! @name T1_CTRL_RSVD_HI_REG -  */
+/*! @{ */
+
+#define CAU_T1_CTRL_RSVD_HI_REG_XTAL_CTRL_RSVD_HI_MASK (0xFFU)
+#define CAU_T1_CTRL_RSVD_HI_REG_XTAL_CTRL_RSVD_HI_SHIFT (0U)
+/*! XTAL_CTRL_RSVD_HI - XTAL_CTRL_RSVD_HI */
+#define CAU_T1_CTRL_RSVD_HI_REG_XTAL_CTRL_RSVD_HI(x) (((uint8_t)(((uint8_t)(x)) << CAU_T1_CTRL_RSVD_HI_REG_XTAL_CTRL_RSVD_HI_SHIFT)) & CAU_T1_CTRL_RSVD_HI_REG_XTAL_CTRL_RSVD_HI_MASK)
+/*! @} */
+
+/*! @name T1_CTRL_RSVD_LO_REG -  */
+/*! @{ */
+
+#define CAU_T1_CTRL_RSVD_LO_REG_XTAL_CTRL_RSVD_LO_MASK (0xFFU)
+#define CAU_T1_CTRL_RSVD_LO_REG_XTAL_CTRL_RSVD_LO_SHIFT (0U)
+/*! XTAL_CTRL_RSVD_LO - XTAL_CTRL_RSVD_LO */
+#define CAU_T1_CTRL_RSVD_LO_REG_XTAL_CTRL_RSVD_LO(x) (((uint8_t)(((uint8_t)(x)) << CAU_T1_CTRL_RSVD_LO_REG_XTAL_CTRL_RSVD_LO_SHIFT)) & CAU_T1_CTRL_RSVD_LO_REG_XTAL_CTRL_RSVD_LO_MASK)
+/*! @} */
+
+/*! @name GPIO_CTRL_REG -  */
+/*! @{ */
+
+#define CAU_GPIO_CTRL_REG_GPIO_CTRL_MASK         (0xFFU)
+#define CAU_GPIO_CTRL_REG_GPIO_CTRL_SHIFT        (0U)
+/*! GPIO_CTRL - GPIO_CTRL */
+#define CAU_GPIO_CTRL_REG_GPIO_CTRL(x)           (((uint8_t)(((uint8_t)(x)) << CAU_GPIO_CTRL_REG_GPIO_CTRL_SHIFT)) & CAU_GPIO_CTRL_REG_GPIO_CTRL_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define CAU_ATEST_CTRL_ONE_REG_ATEST_CTRL_ONE_MASK (0xFFU)
+#define CAU_ATEST_CTRL_ONE_REG_ATEST_CTRL_ONE_SHIFT (0U)
+/*! ATEST_CTRL_ONE - ATEST_CTRL_ONE */
+#define CAU_ATEST_CTRL_ONE_REG_ATEST_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << CAU_ATEST_CTRL_ONE_REG_ATEST_CTRL_ONE_SHIFT)) & CAU_ATEST_CTRL_ONE_REG_ATEST_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define CAU_ATEST_CTRL_TWO_REG_ATEST_CTRL_TWO_MASK (0xFFU)
+#define CAU_ATEST_CTRL_TWO_REG_ATEST_CTRL_TWO_SHIFT (0U)
+/*! ATEST_CTRL_TWO - ATEST_CTRL_TWO */
+#define CAU_ATEST_CTRL_TWO_REG_ATEST_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << CAU_ATEST_CTRL_TWO_REG_ATEST_CTRL_TWO_SHIFT)) & CAU_ATEST_CTRL_TWO_REG_ATEST_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define CAU_ATEST_CTRL_THREE_REG_ATEST_CTRL_THREE_MASK (0xFFU)
+#define CAU_ATEST_CTRL_THREE_REG_ATEST_CTRL_THREE_SHIFT (0U)
+/*! ATEST_CTRL_THREE - ATEST_CTRL_THREE */
+#define CAU_ATEST_CTRL_THREE_REG_ATEST_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << CAU_ATEST_CTRL_THREE_REG_ATEST_CTRL_THREE_SHIFT)) & CAU_ATEST_CTRL_THREE_REG_ATEST_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define CAU_ATEST_CTRL_FOUR_REG_ATEST_CTRL_FOUR_MASK (0xFFU)
+#define CAU_ATEST_CTRL_FOUR_REG_ATEST_CTRL_FOUR_SHIFT (0U)
+/*! ATEST_CTRL_FOUR - ATEST_CTRL_FOUR */
+#define CAU_ATEST_CTRL_FOUR_REG_ATEST_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << CAU_ATEST_CTRL_FOUR_REG_ATEST_CTRL_FOUR_SHIFT)) & CAU_ATEST_CTRL_FOUR_REG_ATEST_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define CAU_ATEST_CTRL_FIVE_REG_ATEST_CTRL_FIVE_MASK (0xFFU)
+#define CAU_ATEST_CTRL_FIVE_REG_ATEST_CTRL_FIVE_SHIFT (0U)
+/*! ATEST_CTRL_FIVE - ATEST_CTRL_FIVE */
+#define CAU_ATEST_CTRL_FIVE_REG_ATEST_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << CAU_ATEST_CTRL_FIVE_REG_ATEST_CTRL_FIVE_SHIFT)) & CAU_ATEST_CTRL_FIVE_REG_ATEST_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define CAU_ATEST_CTRL_SIX_REG_ATEST_CTRL_SIX_MASK (0xFFU)
+#define CAU_ATEST_CTRL_SIX_REG_ATEST_CTRL_SIX_SHIFT (0U)
+/*! ATEST_CTRL_SIX - ATEST_CTRL_SIX */
+#define CAU_ATEST_CTRL_SIX_REG_ATEST_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << CAU_ATEST_CTRL_SIX_REG_ATEST_CTRL_SIX_SHIFT)) & CAU_ATEST_CTRL_SIX_REG_ATEST_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_SEVEN_REG -  */
+/*! @{ */
+
+#define CAU_ATEST_CTRL_SEVEN_REG_ATEST_CTRL_SEVEN_MASK (0xFFU)
+#define CAU_ATEST_CTRL_SEVEN_REG_ATEST_CTRL_SEVEN_SHIFT (0U)
+/*! ATEST_CTRL_SEVEN - ATEST_CTRL_SEVEN */
+#define CAU_ATEST_CTRL_SEVEN_REG_ATEST_CTRL_SEVEN(x) (((uint8_t)(((uint8_t)(x)) << CAU_ATEST_CTRL_SEVEN_REG_ATEST_CTRL_SEVEN_SHIFT)) & CAU_ATEST_CTRL_SEVEN_REG_ATEST_CTRL_SEVEN_MASK)
+/*! @} */
+
+/*! @name RESERVED_LO_ONE_REG -  */
+/*! @{ */
+
+#define CAU_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_MASK (0xFFU)
+#define CAU_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_SHIFT (0U)
+/*! RESERVED_LO_ONE - RESERVED_LO_ONE */
+#define CAU_RESERVED_LO_ONE_REG_RESERVED_LO_ONE(x) (((uint8_t)(((uint8_t)(x)) << CAU_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_SHIFT)) & CAU_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_MASK)
+/*! @} */
+
+/*! @name RESERVED_LO_TWO_REG -  */
+/*! @{ */
+
+#define CAU_RESERVED_LO_TWO_REG_RESERVED_LO_TWO_MASK (0xFFU)
+#define CAU_RESERVED_LO_TWO_REG_RESERVED_LO_TWO_SHIFT (0U)
+/*! RESERVED_LO_TWO - RESERVED_LO_TWO */
+#define CAU_RESERVED_LO_TWO_REG_RESERVED_LO_TWO(x) (((uint8_t)(((uint8_t)(x)) << CAU_RESERVED_LO_TWO_REG_RESERVED_LO_TWO_SHIFT)) & CAU_RESERVED_LO_TWO_REG_RESERVED_LO_TWO_MASK)
+/*! @} */
+
+/*! @name RESERVED_HI_ONE_REG -  */
+/*! @{ */
+
+#define CAU_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_MASK (0xFFU)
+#define CAU_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_SHIFT (0U)
+/*! RESERVED_HI_ONE - RESERVED_HI_ONE */
+#define CAU_RESERVED_HI_ONE_REG_RESERVED_HI_ONE(x) (((uint8_t)(((uint8_t)(x)) << CAU_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_SHIFT)) & CAU_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_MASK)
+/*! @} */
+
+/*! @name RESERVED_HI_TWO_REG -  */
+/*! @{ */
+
+#define CAU_RESERVED_HI_TWO_REG_RESERVED_HI_TWO_MASK (0xFFU)
+#define CAU_RESERVED_HI_TWO_REG_RESERVED_HI_TWO_SHIFT (0U)
+/*! RESERVED_HI_TWO - RESERVED_HI_TWO */
+#define CAU_RESERVED_HI_TWO_REG_RESERVED_HI_TWO(x) (((uint8_t)(((uint8_t)(x)) << CAU_RESERVED_HI_TWO_REG_RESERVED_HI_TWO_SHIFT)) & CAU_RESERVED_HI_TWO_REG_RESERVED_HI_TWO_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CAU base address */
+  #define CAU_BASE                                 (0x55002000u)
+  /** Peripheral CAU base address */
+  #define CAU_BASE_NS                              (0x45002000u)
+  /** Peripheral CAU base pointer */
+  #define CAU                                      ((CAU_Type *)CAU_BASE)
+  /** Peripheral CAU base pointer */
+  #define CAU_NS                                   ((CAU_Type *)CAU_BASE_NS)
+  /** Array initializer of CAU peripheral base addresses */
+  #define CAU_BASE_ADDRS                           { CAU_BASE }
+  /** Array initializer of CAU peripheral base pointers */
+  #define CAU_BASE_PTRS                            { CAU }
+  /** Array initializer of CAU peripheral base addresses */
+  #define CAU_BASE_ADDRS_NS                        { CAU_BASE_NS }
+  /** Array initializer of CAU peripheral base pointers */
+  #define CAU_BASE_PTRS_NS                         { CAU_NS }
+#else
+  /** Peripheral CAU base address */
+  #define CAU_BASE                                 (0x45002000u)
+  /** Peripheral CAU base pointer */
+  #define CAU                                      ((CAU_Type *)CAU_BASE)
+  /** Array initializer of CAU peripheral base addresses */
+  #define CAU_BASE_ADDRS                           { CAU_BASE }
+  /** Array initializer of CAU peripheral base pointers */
+  #define CAU_BASE_PTRS                            { CAU }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
+ * @{
+ */
+
+/** CDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
+  __IO uint32_t RELOAD;                            /**< Instruction Timer reload, offset: 0x4 */
+  __IO uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer, offset: 0x8 */
+  __IO uint32_t SECURE_COUNTER;                    /**< Secure Counter, offset: 0xC */
+  __I  uint32_t STATUS;                            /**< Status 1, offset: 0x10 */
+  __I  uint32_t STATUS2;                           /**< Status 2, offset: 0x14 */
+  __IO uint32_t FLAGS;                             /**< Flags, offset: 0x18 */
+  __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage, offset: 0x1C */
+  __O  uint32_t START;                             /**< START Command, offset: 0x20 */
+  __O  uint32_t STOP;                              /**< STOP Command, offset: 0x24 */
+  __O  uint32_t RESTART;                           /**< RESTART Command, offset: 0x28 */
+  __O  uint32_t ADD;                               /**< ADD Command, offset: 0x2C */
+  __O  uint32_t ADD1;                              /**< ADD1 Command, offset: 0x30 */
+  __O  uint32_t ADD16;                             /**< ADD16 Command, offset: 0x34 */
+  __O  uint32_t ADD256;                            /**< ADD256 Command, offset: 0x38 */
+  __O  uint32_t SUB;                               /**< SUB Command, offset: 0x3C */
+  __O  uint32_t SUB1;                              /**< SUB1 Command, offset: 0x40 */
+  __O  uint32_t SUB16;                             /**< SUB16 Command, offset: 0x44 */
+  __O  uint32_t SUB256;                            /**< SUB256 Command, offset: 0x48 */
+} CDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CDOG_Register_Masks CDOG Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control */
+/*! @{ */
+
+#define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
+#define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
+/*! LOCK_CTRL - Lock control
+ *  0b01..Locked
+ *  0b10..Unlocked
+ */
+#define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
+
+#define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
+#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
+/*! TIMEOUT_CTRL - TIMEOUT fault control
+ *  0b100..Disable both reset and interrupt
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ */
+#define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
+
+#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
+#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
+/*! MISCOMPARE_CTRL - MISCOMPARE fault control
+ *  0b100..Disable both reset and interrupt
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ */
+#define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
+
+#define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
+#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
+/*! SEQUENCE_CTRL - SEQUENCE fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
+
+#define CDOG_CONTROL_CONTROL_CTRL_MASK           (0x3800U)
+#define CDOG_CONTROL_CONTROL_CTRL_SHIFT          (11U)
+/*! CONTROL_CTRL - CONTROL fault control
+ *  0b001..Enable reset
+ *  0b100..Disable reset
+ */
+#define CDOG_CONTROL_CONTROL_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK)
+
+#define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
+#define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
+/*! STATE_CTRL - STATE fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
+
+#define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
+#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
+/*! ADDRESS_CTRL - ADDRESS fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
+
+#define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
+#define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
+/*! IRQ_PAUSE - IRQ pause control
+ *  0b01..Keep the timer running
+ *  0b10..Stop the timer
+ */
+#define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
+
+#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
+#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
+/*! DEBUG_HALT_CTRL - DEBUG_HALT control
+ *  0b01..Keep the timer running
+ *  0b10..Stop the timer
+ */
+#define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
+/*! @} */
+
+/*! @name RELOAD - Instruction Timer reload */
+/*! @{ */
+
+#define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
+#define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
+/*! RLOAD - Instruction Timer reload value */
+#define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
+/*! @} */
+
+/*! @name INSTRUCTION_TIMER - Instruction Timer */
+/*! @{ */
+
+#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
+#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
+/*! INSTIM - Current value of the Instruction Timer */
+#define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
+/*! @} */
+
+/*! @name SECURE_COUNTER - Secure Counter */
+/*! @{ */
+
+#define CDOG_SECURE_COUNTER_SECCNT_MASK          (0xFFFFFFFFU)
+#define CDOG_SECURE_COUNTER_SECCNT_SHIFT         (0U)
+/*! SECCNT - Secure Counter */
+#define CDOG_SECURE_COUNTER_SECCNT(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK)
+/*! @} */
+
+/*! @name STATUS - Status 1 */
+/*! @{ */
+
+#define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
+#define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
+/*! NUMTOF - Number of TIMEOUT faults since the last POR */
+#define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
+
+#define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
+#define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
+/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */
+#define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
+
+#define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
+#define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
+/*! NUMILSEQF - Number of SEQUENCE faults since the last POR */
+#define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
+
+#define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
+#define CDOG_STATUS_CURST_SHIFT                  (28U)
+/*! CURST - Current State */
+#define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
+/*! @} */
+
+/*! @name STATUS2 - Status 2 */
+/*! @{ */
+
+#define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
+#define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
+/*! NUMCNTF - Number of CONTROL faults since the last POR */
+#define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
+
+#define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
+#define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
+/*! NUMILLSTF - Number of STATE faults since the last POR */
+#define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
+
+#define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
+#define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
+/*! NUMILLA - Number of ADDRESS faults since the last POR */
+#define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
+/*! @} */
+
+/*! @name FLAGS - Flags */
+/*! @{ */
+
+#define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
+#define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
+/*! TO_FLAG - TIMEOUT fault flag
+ *  0b0..A TIMEOUT fault has not occurred
+ *  0b1..A TIMEOUT fault has occurred
+ */
+#define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
+
+#define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
+#define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
+/*! MISCOM_FLAG - MISCOMPARE fault flag
+ *  0b0..A MISCOMPARE fault has not occurred
+ *  0b1..A MISCOMPARE fault has occurred
+ */
+#define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
+
+#define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
+#define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
+/*! SEQ_FLAG - SEQUENCE fault flag
+ *  0b0..A SEQUENCE fault has not occurred
+ *  0b1..A SEQUENCE fault has occurred
+ */
+#define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
+
+#define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
+#define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
+/*! CNT_FLAG - CONTROL fault flag
+ *  0b0..A CONTROL fault has not occurred
+ *  0b1..A CONTROL fault has occurred
+ */
+#define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
+
+#define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
+#define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
+/*! STATE_FLAG - STATE fault flag
+ *  0b0..A STATE fault has not occurred
+ *  0b1..A STATE fault has occurred
+ */
+#define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
+
+#define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
+#define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
+/*! ADDR_FLAG - ADDRESS fault flag
+ *  0b0..An ADDRESS fault has not occurred
+ *  0b1..An ADDRESS fault has occurred
+ */
+#define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
+
+#define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
+#define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
+/*! POR_FLAG - Power-on reset flag
+ *  0b0..A Power-on reset event has not occurred
+ *  0b1..A Power-on reset event has occurred
+ */
+#define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
+/*! @} */
+
+/*! @name PERSISTENT - Persistent Data Storage */
+/*! @{ */
+
+#define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
+#define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
+/*! PERSIS - Persistent Storage */
+#define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
+/*! @} */
+
+/*! @name START - START Command */
+/*! @{ */
+
+#define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
+#define CDOG_START_STRT_SHIFT                    (0U)
+/*! STRT - Start command */
+#define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
+/*! @} */
+
+/*! @name STOP - STOP Command */
+/*! @{ */
+
+#define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
+#define CDOG_STOP_STP_SHIFT                      (0U)
+/*! STP - Stop command */
+#define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
+/*! @} */
+
+/*! @name RESTART - RESTART Command */
+/*! @{ */
+
+#define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
+#define CDOG_RESTART_RSTRT_SHIFT                 (0U)
+/*! RSTRT - Restart command */
+#define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
+/*! @} */
+
+/*! @name ADD - ADD Command */
+/*! @{ */
+
+#define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
+#define CDOG_ADD_AD_SHIFT                        (0U)
+/*! AD - ADD Write Value */
+#define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
+/*! @} */
+
+/*! @name ADD1 - ADD1 Command */
+/*! @{ */
+
+#define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
+#define CDOG_ADD1_AD1_SHIFT                      (0U)
+/*! AD1 - ADD 1 */
+#define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
+/*! @} */
+
+/*! @name ADD16 - ADD16 Command */
+/*! @{ */
+
+#define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
+#define CDOG_ADD16_AD16_SHIFT                    (0U)
+/*! AD16 - ADD 16 */
+#define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
+/*! @} */
+
+/*! @name ADD256 - ADD256 Command */
+/*! @{ */
+
+#define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
+#define CDOG_ADD256_AD256_SHIFT                  (0U)
+/*! AD256 - ADD 256 */
+#define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
+/*! @} */
+
+/*! @name SUB - SUB Command */
+/*! @{ */
+
+#define CDOG_SUB_S0B_MASK                        (0xFFFFFFFFU)
+#define CDOG_SUB_S0B_SHIFT                       (0U)
+/*! S0B - Subtract Write Value */
+#define CDOG_SUB_S0B(x)                          (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
+/*! @} */
+
+/*! @name SUB1 - SUB1 Command */
+/*! @{ */
+
+#define CDOG_SUB1_S1B_MASK                       (0xFFFFFFFFU)
+#define CDOG_SUB1_S1B_SHIFT                      (0U)
+/*! S1B - Subtract 1 */
+#define CDOG_SUB1_S1B(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK)
+/*! @} */
+
+/*! @name SUB16 - SUB16 Command */
+/*! @{ */
+
+#define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
+#define CDOG_SUB16_SB16_SHIFT                    (0U)
+/*! SB16 - Subtract 16 */
+#define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
+/*! @} */
+
+/*! @name SUB256 - SUB256 Command */
+/*! @{ */
+
+#define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
+#define CDOG_SUB256_SB256_SHIFT                  (0U)
+/*! SB256 - Subtract 256 */
+#define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CDOG_Register_Masks */
+
+
+/* CDOG - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CDOG base address */
+  #define CDOG_BASE                                (0x5014C000u)
+  /** Peripheral CDOG base address */
+  #define CDOG_BASE_NS                             (0x4014C000u)
+  /** Peripheral CDOG base pointer */
+  #define CDOG                                     ((CDOG_Type *)CDOG_BASE)
+  /** Peripheral CDOG base pointer */
+  #define CDOG_NS                                  ((CDOG_Type *)CDOG_BASE_NS)
+  /** Array initializer of CDOG peripheral base addresses */
+  #define CDOG_BASE_ADDRS                          { CDOG_BASE }
+  /** Array initializer of CDOG peripheral base pointers */
+  #define CDOG_BASE_PTRS                           { CDOG }
+  /** Array initializer of CDOG peripheral base addresses */
+  #define CDOG_BASE_ADDRS_NS                       { CDOG_BASE_NS }
+  /** Array initializer of CDOG peripheral base pointers */
+  #define CDOG_BASE_PTRS_NS                        { CDOG_NS }
+#else
+  /** Peripheral CDOG base address */
+  #define CDOG_BASE                                (0x4014C000u)
+  /** Peripheral CDOG base pointer */
+  #define CDOG                                     ((CDOG_Type *)CDOG_BASE)
+  /** Array initializer of CDOG peripheral base addresses */
+  #define CDOG_BASE_ADDRS                          { CDOG_BASE }
+  /** Array initializer of CDOG peripheral base pointers */
+  #define CDOG_BASE_PTRS                           { CDOG }
+#endif
+/** Interrupt vectors for the CDOG peripheral type */
+#define CDOG_IRQS                                { CDOG_INT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CDOG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CIU1 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CIU1_Peripheral_Access_Layer CIU1 Peripheral Access Layer
+ * @{
+ */
+
+/** CIU1 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[132];
+  __I  uint32_t CIU_CHIP_REV;                      /**< CIU Revision, offset: 0x84 */
+       uint8_t RESERVED_1[116];
+  __IO uint32_t CIU_CHIP_ECO_CTRL;                 /**< Chip ECO Control, offset: 0xFC */
+  __IO uint32_t CIU_CLK_ENABLE;                    /**< Clock Enable, offset: 0x100 */
+  __IO uint32_t CIU_CLK_ENABLE2;                   /**< Clock enable2, offset: 0x104 */
+  __IO uint32_t CIU_CLK_ENABLE3;                   /**< Clock Enable 3, offset: 0x108 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CIU_CLK_CPU1CLK_CTRL;              /**< CPU1_AHB1 Clock Control, offset: 0x114 */
+  __IO uint32_t CIU_CLK_SYSCLK_CTRL;               /**< SYS Clock Control, offset: 0x118 */
+       uint8_t RESERVED_3[16];
+  __IO uint32_t CIU_CLK_RTU_NCO_CTRL;              /**< RTU NCO Clock Control, offset: 0x12C */
+  __IO uint32_t CIU_CLK_LBU1_WLRTU_CTRL;           /**< LBU1 WLRTU1 Clock Control, offset: 0x130 */
+  __IO uint32_t CIU_CLK_SOCCLK_CTRL;               /**< SOC Clock Control, offset: 0x134 */
+  __IO uint32_t CIU_CLK_SLEEPCLK_CTRL;             /**< Sleep Clock Control, offset: 0x138 */
+  __IO uint32_t CIU_CLK_CP15_DIS1;                 /**< Clock Auto Shut-off Enable1, offset: 0x13C */
+  __IO uint32_t CIU_CLK_CP15_DIS2;                 /**< Clock Auto Shut-off Enable2, offset: 0x140 */
+  __IO uint32_t CIU_CLK_CP15_DIS3;                 /**< Clock Auto Shut-off Enable3, offset: 0x144 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t CIU_CLK_ENABLE6;                   /**< Clock Enable 6, offset: 0x14C */
+  __IO uint32_t CIU_CLK_SLEEPCLK_CTRL2;            /**< Sleep Clock Control 2, offset: 0x150 */
+       uint8_t RESERVED_5[36];
+  __IO uint32_t CIU_MAC_CLK_CTRL;                  /**< MAC clock CTRL, offset: 0x178 */
+  __IO uint32_t CIU_CLK_ECO_CTRL;                  /**< Clock ECO Control, offset: 0x17C */
+  __IO uint32_t CIU_RST_SW1;                       /**< Software Module Reset, offset: 0x180 */
+  __IO uint32_t CIU_RST_SW2;                       /**< Software Module Reset, offset: 0x184 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t CIU_RST_SW4;                       /**< Software Module Reset, offset: 0x18C */
+  __IO uint32_t CIU_RST_SW5;                       /**< Software Module Reset, offset: 0x190 */
+       uint8_t RESERVED_7[104];
+  __IO uint32_t CIU_RST_ECO_CTRL;                  /**< Reset ECO Control, offset: 0x1FC */
+       uint8_t RESERVED_8[4];
+  __IO uint32_t CIU_MEM_WRTC2;                     /**< Memory WRTC Control2, offset: 0x204 */
+  __IO uint32_t CIU_MEM_WRTC3;                     /**< Memory WRTC Control 3, offset: 0x208 */
+       uint8_t RESERVED_9[16];
+  __IO uint32_t CIU_MEM_CTRL;                      /**< Memory Control, offset: 0x21C */
+  __I  uint32_t CIU_SMU1_DBG_STAT0;                /**< SMU1 debug register0, offset: 0x220 */
+  __I  uint32_t CIU_SMU1_DBG_STAT1;                /**< SMU1 debug register1, offset: 0x224 */
+  __I  uint32_t CIU_SMU1_DBG_STAT2;                /**< SMU1 debug register2, offset: 0x228 */
+       uint8_t RESERVED_10[80];
+  __IO uint32_t CIU_MEM_ECO_CTRL;                  /**< Memory ECO Control, offset: 0x27C */
+  __IO uint32_t CIU1_INT_MASK;                     /**< CIU1 Interrupt Mask, offset: 0x280 */
+  __IO uint32_t CIU1_INT_SELECT;                   /**< CIU1 Interrupt Select, offset: 0x284 */
+  __IO uint32_t CIU1_INT_EVENT_MASK;               /**< CIU1 Interrupt Event Mask, offset: 0x288 */
+  __I  uint32_t CIU1_INT_STATUS;                   /**< CIU1 Interrupt Status, offset: 0x28C */
+  __IO uint32_t CIU_INT_HOST_CTRL;                 /**< Host Interrupt Control, offset: 0x290 */
+  __IO uint32_t CIU_BCA1_INT_MASK;                 /**< BCA1 to CPU1 Interrupt Mask, offset: 0x294 */
+  __IO uint32_t CIU_BCA1_INT_SELECT;               /**< BCA1 to CPU1 Interrupt Select, offset: 0x298 */
+  __IO uint32_t CIU_BCA1_INT_EVENT_MASK;           /**< BCA1 to CPU1 Interrupt Event Mask, offset: 0x29C */
+  __I  uint32_t CIU_BCA1_INT_STATUS;               /**< BCA1 to CPU1 Interrupt Status, offset: 0x2A0 */
+       uint8_t RESERVED_11[16];
+  __IO uint32_t CPU1_ERR_INT_MASK;                 /**< CPU1 ERR Interrupt Mask, offset: 0x2B4 */
+  __IO uint32_t CPU1_ERR_INT_SELECT;               /**< CPU1 ERR Interrupt Clear Select, offset: 0x2B8 */
+  __IO uint32_t CPU1_ERR_INT_EVENT_MASK;           /**< CPU1 ERR Interrupt Event Mask, offset: 0x2BC */
+  __I  uint32_t CPU1_ERR_INT_STATUS;               /**< CPU1 ERR Interrupt Status, offset: 0x2C0 */
+       uint8_t RESERVED_12[32];
+  __IO uint32_t CPU2_INT_CTRL;                     /**< CPU2 INT control, offset: 0x2E4 */
+       uint8_t RESERVED_13[16];
+  __IO uint32_t CPU3_INT_CTRL;                     /**< CPU3 INT control, offset: 0x2F8 */
+  __IO uint32_t CIU_INT_ECO_CTRL;                  /**< Interrupt ECO Control, offset: 0x2FC */
+  __IO uint32_t CIU_PTP_CTRL;                      /**< Vsensor and Vreg Pad Control, offset: 0x300 */
+       uint8_t RESERVED_14[156];
+  __IO uint32_t CIU_RFU_DBC_MUX_SEL;               /**< RFU related DBC mux selection for different mode, offset: 0x3A0 */
+  __IO uint32_t CIU_BCA_DBC_MUX_SEL;               /**< BCA related DBC mux selection for different mode, offset: 0x3A4 */
+       uint8_t RESERVED_15[88];
+  __I  uint32_t CIU_TST_G2BIST_STATUS;             /**< WL G2BIST Status, offset: 0x400 */
+  __I  uint32_t CIU_TST_MBIST_READY;               /**< MBIST Status (BIST_READY), offset: 0x404 */
+  __I  uint32_t CIU_TST_MBIST_FAIL;                /**< MBIST Status (BIST_FAIL), offset: 0x408 */
+       uint8_t RESERVED_16[28];
+  __IO uint32_t CIU_TST_TSTBUS_CTRL2;              /**< Testbux Mux Control2, offset: 0x428 */
+       uint8_t RESERVED_17[4];
+  __IO uint32_t CIU_TST_CTRL;                      /**< Test Control, offset: 0x430 */
+       uint8_t RESERVED_18[72];
+  __IO uint32_t CIU_TST_ECO_CTRL;                  /**< Test ECO Control, offset: 0x47C */
+       uint8_t RESERVED_19[128];
+  __IO uint32_t CIU_GPS_GPIO_MASK;                 /**< GPS GPIO MASK, offset: 0x500 */
+  __IO uint32_t CIU_GPS_SW_PERIOD;                 /**< GPS SWITCH CHANNEL PERIOD, offset: 0x504 */
+  __IO uint32_t CIU_GPS_SW_EARLY;                  /**< GPS SWITCH CHANNEL EARLY, offset: 0x508 */
+  __I  uint32_t CIU_GPS_TMR_RD;                    /**< GPS TIMER READ, offset: 0x50C */
+       uint8_t RESERVED_20[1132];
+  __IO uint32_t CIU_LDO_ECO_CTRL;                  /**< LDO ECO Control, offset: 0x97C */
+       uint8_t RESERVED_21[24];
+  __IO uint32_t CIU_AXI_CLK_CTRL2;                 /**< AXI clk bypass contrl2, offset: 0x998 */
+  __IO uint32_t CIU_FABRIC_TESTBUS_CTRL;           /**< fabric(scm, wlm) testbus select, offset: 0x99C */
+  __IO uint32_t CIU_FABRIC_CREQ_DLY_TIMER;         /**< fabric(scm, wlm) delay timer for c_req, offset: 0x9A0 */
+       uint8_t RESERVED_22[88];
+  __IO uint32_t CIU_ABU_ECO_CTRL;                  /**< ABU ECO Control, offset: 0x9FC */
+  __IO uint32_t CIU1_AHB1_TO_CLEAR;                /**< AHB1 timeout logic clear register, offset: 0xA00 */
+  __I  uint32_t CIU_ARB_TO_LAST_ADDR;              /**< AHB Timeout Last Address, offset: 0xA04 */
+  __I  uint32_t CIU_ARB_TO_CUR_ADDR;               /**< AHB Current Timeout Address, offset: 0xA08 */
+  __IO uint32_t CIU_ARB_CTRL;                      /**< AHB ARB Control, offset: 0xA0C */
+       uint8_t RESERVED_23[68];
+  __IO uint32_t CIU1_CPU1_ICODE_INV_ADDR_CTRL;     /**< CPU1 Icode invalid address access control, offset: 0xA54 */
+  __I  uint32_t CIU1_CPU1_ICODE_INV_ADDR;          /**< CPU1 Icode invalid address, offset: 0xA58 */
+  __IO uint32_t CIU1_CPU1_DCODE_INV_ADDR_CTRL;     /**< CPU1 Dcode invalid address access control, offset: 0xA5C */
+  __I  uint32_t CIU1_CPU1_DCODE_INV_ADDR;          /**< CPU1 Dcode invalid address, offset: 0xA60 */
+  __IO uint32_t CIU1_AHB2AHB_BRIDGE_CTRL;          /**< AHB2AHB Bridge Control Register, offset: 0xA64 */
+  __IO uint32_t WL_RAACS_CTRL;                     /**< RAACS control registers, offset: 0xA68 */
+  __IO uint32_t WL_RAACS_PERFORMANCE_STATISTICS;   /**< RAACS performance statistics counter., offset: 0xA6C */
+  __IO uint32_t CIU_AHB1_TSTBUS_SEL;               /**< AHB1 Control Signals testbus select, offset: 0xA70 */
+       uint8_t RESERVED_24[8];
+  __IO uint32_t CIU_ARB_ECO_CTRL;                  /**< ARB ECO Control, offset: 0xA7C */
+       uint8_t RESERVED_25[8];
+  __IO uint32_t CIU_CPU_DYN_CLK_CTRL;              /**< Dynamic CPU Clock Control, offset: 0xA88 */
+       uint8_t RESERVED_26[12];
+  __I  uint32_t CIU_CPU_DYN_CPUCLK_MONITOR;        /**< Dynamic ahb clock Monitor, offset: 0xA98 */
+  __I  uint32_t CIU_CPU_DYN_SYSCLK_MONITOR;        /**< Dynamic sysclk Monitor, offset: 0xA9C */
+       uint8_t RESERVED_27[16];
+  __IO uint32_t CIU_CPU_CPU1_CTRL;                 /**< CPU1 control register, offset: 0xAB0 */
+       uint8_t RESERVED_28[12];
+  __IO uint32_t CIU_CPU_CPU1_ACCESS_CTRL;          /**< CPU1 access control register, offset: 0xAC0 */
+  __IO uint32_t CIU_CPU_CPU2_ACCESS_CTRL;          /**< CPU2 access control register, offset: 0xAC4 */
+  __IO uint32_t CIU_CPU_CPU3_ACCESS_CTRL;          /**< CPU3 access control register, offset: 0xAC8 */
+  __I  uint32_t CIU_CPU_CPU1_DBG_STAT1;            /**< CPU1 debug register1, offset: 0xACC */
+       uint8_t RESERVED_29[8];
+  __IO uint32_t CIU_CPU1_CPU2_FW_DWLD_CTRL;        /**< CPUs FW dwld control register, offset: 0xAD8 */
+  __IO uint32_t CIU_CPU_COMM0;                     /**< CPU Communication reserved0, offset: 0xADC */
+  __IO uint32_t CIU_CPU_COMM1;                     /**< CPU Communication reserved1, offset: 0xAE0 */
+       uint8_t RESERVED_30[88];
+  __IO uint32_t CIU_CPU_ECO_CTRL;                  /**< CPU ECO control, offset: 0xB3C */
+       uint8_t RESERVED_31[32];
+  __IO uint32_t CIU_RFU_CTRL;                      /**< RFU Control and Status, offset: 0xB60 */
+  __IO uint32_t CIU_RFU_EXTRA_PORT;                /**< RFU Extra Port Connection, offset: 0xB64 */
+       uint8_t RESERVED_32[20];
+  __IO uint32_t CIU_RFU_ECO_CTRL;                  /**< RFU ECO Control, offset: 0xB7C */
+       uint8_t RESERVED_33[128];
+  __IO uint32_t CIU_MCI_EXTRA;                     /**< MCI EXTRA Ports, offset: 0xC00 */
+       uint8_t RESERVED_34[252];
+  __IO uint32_t CIU_BBUD_CTRL;                     /**< BBUD Control Register, offset: 0xD00 */
+  __IO uint32_t CIU_BBUD_EXTRA_PORT;               /**< BBUD Extra Port Connection, offset: 0xD04 */
+  __IO uint32_t CIU_BBUD_PTP_INTR_CTRL;            /**< PTP Input capture interrupt control, offset: 0xD08 */
+       uint8_t RESERVED_35[112];
+  __IO uint32_t CIU_BBUD_ECO_CTRL;                 /**< BBUD ECO Control, offset: 0xD7C */
+  __IO uint32_t CIU_AIU_CTRL;                      /**< AIU Control Register, offset: 0xD80 */
+       uint8_t RESERVED_36[120];
+  __IO uint32_t CIU_AIU_ECO_CTRL;                  /**< AIU ECO Control, offset: 0xDFC */
+       uint8_t RESERVED_37[252];
+  __IO uint32_t CIU_CBU_ECO_CTRL;                  /**< CBU ECO Control, offset: 0xEFC */
+       uint8_t RESERVED_38[1829120];
+  __IO uint32_t CIU1_IMU_CPU1_WR_MSG_TO_CPU3;      /**< CPU1(WL) write message to CPU3(MCI) (0xAF0-0xAF4 IMU register access by CPU1), offset: 0x1BF800 */
+  __I  uint32_t CIU1_IMU_CPU1_RD_MSG_FROM_CPU3;    /**< cpu1 read message from CPU3, offset: 0x1BF804 */
+  __I  uint32_t CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS; /**< cpu1 to CPU3 message FIFO status, offset: 0x1BF808 */
+  __IO uint32_t CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL;  /**< cpu1 to CPU3 message FIFO control, offset: 0x1BF80C */
+  __I  uint32_t CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG; /**< CPU3 last message read (from cpu1), offset: 0x1BF810 */
+       uint8_t RESERVED_39[12];
+  __IO uint32_t CIU1_IMU_CPU3_WR_MSG_TO_CPU1;      /**< CPU3 write message to cpu1 (0xB04-0xB14 IMU register access by CPU3), offset: 0x1BF820 */
+  __I  uint32_t CIU1_IMU_CPU3_RD_MSG_FROM_CPU1;    /**< CPU3 read message from cpu1, offset: 0x1BF824 */
+  __I  uint32_t CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS; /**< CPU3 to cpu1 message FIFO status, offset: 0x1BF828 */
+  __IO uint32_t CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL;  /**< CPU3 to cpu1 message FIFO control, offset: 0x1BF82C */
+  __I  uint32_t CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG; /**< cpu1 last message read (from cpu3), offset: 0x1BF830 */
+  __IO uint32_t CIU_CPU1_CPU3_MSG_CTRL;            /**< CPU1_CPU3 message register, offset: 0x1BF834 */
+  __IO uint32_t CIU1_CPU3_WAKEUP_CTRL;             /**< CIU1 register to wakeup CPU3, offset: 0x1BF838 */
+  __IO uint32_t CIU1_CPU1_WAKEUP_DONE;             /**< Wakeup done Control Register to CPU3, offset: 0x1BF83C */
+  __IO uint32_t CIU1_CPU3_NS_GP_INT;               /**< Non Secure region GP interrupt to CPU3, offset: 0x1BF840 */
+       uint8_t RESERVED_40[184];
+  __IO uint32_t CIU_IMU_ECO_BITS;                  /**< IMU ECO Control, offset: 0x1BF8FC */
+} CIU1_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CIU1 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CIU1_Register_Masks CIU1 Register Masks
+ * @{
+ */
+
+/*! @name CIU_CHIP_REV - CIU Revision */
+/*! @{ */
+
+#define CIU1_CIU_CHIP_REV_CIU_IP_REVISION_MASK   (0xFFFFU)
+#define CIU1_CIU_CHIP_REV_CIU_IP_REVISION_SHIFT  (0U)
+/*! CIU_IP_REVISION - CIU Revision Number */
+#define CIU1_CIU_CHIP_REV_CIU_IP_REVISION(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CHIP_REV_CIU_IP_REVISION_SHIFT)) & CIU1_CIU_CHIP_REV_CIU_IP_REVISION_MASK)
+/*! @} */
+
+/*! @name CIU_CHIP_ECO_CTRL - Chip ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_CHIP_ECO_CTRL_ECO_BITS_MASK     (0xFFFFFFFFU)
+#define CIU1_CIU_CHIP_ECO_CTRL_ECO_BITS_SHIFT    (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_CHIP_ECO_CTRL_ECO_BITS(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CHIP_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_CHIP_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_ENABLE - Clock Enable */
+/*! @{ */
+
+#define CIU1_CIU_CLK_ENABLE_BIST_AHB1_CLK_GATING_EN_MASK (0x1U)
+#define CIU1_CIU_CLK_ENABLE_BIST_AHB1_CLK_GATING_EN_SHIFT (0U)
+/*! BIST_AHB1_CLK_GATING_EN - bist Clock gating for IMEM/DMEM/SMU1/ROM */
+#define CIU1_CIU_CLK_ENABLE_BIST_AHB1_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_BIST_AHB1_CLK_GATING_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_BIST_AHB1_CLK_GATING_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CPU1_GATEHCLK_EN_MASK (0x8U)
+#define CIU1_CIU_CLK_ENABLE_CPU1_GATEHCLK_EN_SHIFT (3U)
+/*! CPU1_GATEHCLK_EN - CPU1 Gate HCLK Control Feature */
+#define CIU1_CIU_CLK_ENABLE_CPU1_GATEHCLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CPU1_GATEHCLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CPU1_GATEHCLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CPU1_FABRIC_CLK_EN_MASK (0x10U)
+#define CIU1_CIU_CLK_ENABLE_CPU1_FABRIC_CLK_EN_SHIFT (4U)
+/*! CPU1_FABRIC_CLK_EN - CPU1 Fabric Clock Control Feature */
+#define CIU1_CIU_CLK_ENABLE_CPU1_FABRIC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CPU1_FABRIC_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CPU1_FABRIC_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CPU1_MEM_SLV_CLK_EN_MASK (0x20U)
+#define CIU1_CIU_CLK_ENABLE_CPU1_MEM_SLV_CLK_EN_SHIFT (5U)
+/*! CPU1_MEM_SLV_CLK_EN - CPU1 Memory Slave Clock Control Feature */
+#define CIU1_CIU_CLK_ENABLE_CPU1_MEM_SLV_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CPU1_MEM_SLV_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CPU1_MEM_SLV_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_SMU1_DYN_CLK_GATING_DIS_MASK (0x40U)
+#define CIU1_CIU_CLK_ENABLE_SMU1_DYN_CLK_GATING_DIS_SHIFT (6U)
+/*! SMU1_DYN_CLK_GATING_DIS - SMU1 Dynamic Clock Gating Feature */
+#define CIU1_CIU_CLK_ENABLE_SMU1_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_SMU1_DYN_CLK_GATING_DIS_SHIFT)) & CIU1_CIU_CLK_ENABLE_SMU1_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_WLRTU1_AHB_CLK_EN_MASK (0x100U)
+#define CIU1_CIU_CLK_ENABLE_WLRTU1_AHB_CLK_EN_SHIFT (8U)
+/*! WLRTU1_AHB_CLK_EN - WLRTU1 AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_WLRTU1_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_WLRTU1_AHB_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_WLRTU1_AHB_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_SMU1_AHB_CLK_EN_MASK (0x200U)
+#define CIU1_CIU_CLK_ENABLE_SMU1_AHB_CLK_EN_SHIFT (9U)
+/*! SMU1_AHB_CLK_EN - SMU1 AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_SMU1_AHB_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_SMU1_AHB_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_SMU1_AHB_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_IPS_HCLK_EN_MASK     (0x400U)
+#define CIU1_CIU_CLK_ENABLE_IPS_HCLK_EN_SHIFT    (10U)
+/*! IPS_HCLK_EN - IPS AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_IPS_HCLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_IPS_HCLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_IPS_HCLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_LBU1_AHB_CLK_EN_MASK (0x800U)
+#define CIU1_CIU_CLK_ENABLE_LBU1_AHB_CLK_EN_SHIFT (11U)
+/*! LBU1_AHB_CLK_EN - PBU AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_LBU1_AHB_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_LBU1_AHB_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_LBU1_AHB_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_AHB_CLK_EN_MASK (0x1000U)
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_AHB_CLK_EN_SHIFT (12U)
+/*! CIU_WLAPU_AHB_CLK_EN - APU AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CIU_WLAPU_AHB_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CIU_WLAPU_AHB_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_SLPCLK_EN_MASK (0x2000U)
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_SLPCLK_EN_SHIFT (13U)
+/*! CIU_WLAPU_SLPCLK_EN - APU Sleep Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_SLPCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CIU_WLAPU_SLPCLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CIU_WLAPU_SLPCLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_CAL_CLK_EN_MASK (0x4000U)
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_CAL_CLK_EN_SHIFT (14U)
+/*! CIU_WLAPU_CAL_CLK_EN - APU Calibration Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_CAL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CIU_WLAPU_CAL_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CIU_WLAPU_CAL_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_REF_CLK_EN_MASK (0x8000U)
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_REF_CLK_EN_SHIFT (15U)
+/*! CIU_WLAPU_REF_CLK_EN - APU Reference Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_REF_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CIU_WLAPU_REF_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CIU_WLAPU_REF_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_IPS_CLK_EN_MASK      (0x10000U)
+#define CIU1_CIU_CLK_ENABLE_IPS_CLK_EN_SHIFT     (16U)
+/*! IPS_CLK_EN - Enable for ips functional clock */
+#define CIU1_CIU_CLK_ENABLE_IPS_CLK_EN(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_IPS_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_IPS_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_IPS_PCLK_EN_MASK     (0x20000U)
+#define CIU1_CIU_CLK_ENABLE_IPS_PCLK_EN_SHIFT    (17U)
+/*! IPS_PCLK_EN - Enable for ips apb clock */
+#define CIU1_CIU_CLK_ENABLE_IPS_PCLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_IPS_PCLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_IPS_PCLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_MCI_LITE2AHB_HCLK_EN_MASK (0x40000U)
+#define CIU1_CIU_CLK_ENABLE_MCI_LITE2AHB_HCLK_EN_SHIFT (18U)
+/*! MCI_LITE2AHB_HCLK_EN - Enable for mci lite2ahb module in wl_top */
+#define CIU1_CIU_CLK_ENABLE_MCI_LITE2AHB_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_MCI_LITE2AHB_HCLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_MCI_LITE2AHB_HCLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_LBU1_LSBIF_CLK_EN_MASK (0x100000U)
+#define CIU1_CIU_CLK_ENABLE_LBU1_LSBIF_CLK_EN_SHIFT (20U)
+/*! LBU1_LSBIF_CLK_EN - PBU Device Clock (PCLK) Enable */
+#define CIU1_CIU_CLK_ENABLE_LBU1_LSBIF_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_LBU1_LSBIF_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_LBU1_LSBIF_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_EU1_CORE_CLK_EN_MASK (0x400000U)
+#define CIU1_CIU_CLK_ENABLE_EU1_CORE_CLK_EN_SHIFT (22U)
+/*! EU1_CORE_CLK_EN - EU1 Core Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_EU1_CORE_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_EU1_CORE_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_EU1_CORE_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_MCU1_AHB_CLK_EN_MASK (0x800000U)
+#define CIU1_CIU_CLK_ENABLE_MCU1_AHB_CLK_EN_SHIFT (23U)
+/*! MCU1_AHB_CLK_EN - MCU1 AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_MCU1_AHB_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_MCU1_AHB_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_MCU1_AHB_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_WL_AHB2APB_HCLK_EN_MASK (0x2000000U)
+#define CIU1_CIU_CLK_ENABLE_WL_AHB2APB_HCLK_EN_SHIFT (25U)
+/*! WL_AHB2APB_HCLK_EN - Wireless AHB to APB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_WL_AHB2APB_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_WL_AHB2APB_HCLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_WL_AHB2APB_HCLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_MCU1_SYS_CLK_EN_MASK (0x4000000U)
+#define CIU1_CIU_CLK_ENABLE_MCU1_SYS_CLK_EN_SHIFT (26U)
+/*! MCU1_SYS_CLK_EN - MCU1 System Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_MCU1_SYS_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_MCU1_SYS_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_MCU1_SYS_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_DVFS_CLK_EN_MASK (0x80000000U)
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_DVFS_CLK_EN_SHIFT (31U)
+/*! CIU_WLAPU_DVFS_CLK_EN - APU DVFS Clock Enable */
+#define CIU1_CIU_CLK_ENABLE_CIU_WLAPU_DVFS_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE_CIU_WLAPU_DVFS_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE_CIU_WLAPU_DVFS_CLK_EN_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_ENABLE2 - Clock enable2 */
+/*! @{ */
+
+#define CIU1_CIU_CLK_ENABLE2_IPS_PROM_ADDR_MASK_DIS_MASK (0x1U)
+#define CIU1_CIU_CLK_ENABLE2_IPS_PROM_ADDR_MASK_DIS_SHIFT (0U)
+/*! IPS_PROM_ADDR_MASK_DIS - ips prom ROM Address Mask Selection */
+#define CIU1_CIU_CLK_ENABLE2_IPS_PROM_ADDR_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_IPS_PROM_ADDR_MASK_DIS_SHIFT)) & CIU1_CIU_CLK_ENABLE2_IPS_PROM_ADDR_MASK_DIS_MASK)
+
+#define CIU1_CIU_CLK_ENABLE2_IPS_PROM_DYN_CLK_DIS_MASK (0x2U)
+#define CIU1_CIU_CLK_ENABLE2_IPS_PROM_DYN_CLK_DIS_SHIFT (1U)
+/*! IPS_PROM_DYN_CLK_DIS - ips ROM Dynamic Clock Gating Feature */
+#define CIU1_CIU_CLK_ENABLE2_IPS_PROM_DYN_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_IPS_PROM_DYN_CLK_DIS_SHIFT)) & CIU1_CIU_CLK_ENABLE2_IPS_PROM_DYN_CLK_DIS_MASK)
+
+#define CIU1_CIU_CLK_ENABLE2_BR_AHB1_CLK_EN_MASK (0x1F0000U)
+#define CIU1_CIU_CLK_ENABLE2_BR_AHB1_CLK_EN_SHIFT (16U)
+/*! BR_AHB1_CLK_EN - BRU AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE2_BR_AHB1_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_BR_AHB1_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE2_BR_AHB1_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE2_WEU_AHB_CLK_EN_MASK (0x4000000U)
+#define CIU1_CIU_CLK_ENABLE2_WEU_AHB_CLK_EN_SHIFT (26U)
+/*! WEU_AHB_CLK_EN - WEU AHB Clock Enable */
+#define CIU1_CIU_CLK_ENABLE2_WEU_AHB_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_WEU_AHB_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE2_WEU_AHB_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE2_WEU_SYS_CLK_EN_MASK (0x8000000U)
+#define CIU1_CIU_CLK_ENABLE2_WEU_SYS_CLK_EN_SHIFT (27U)
+/*! WEU_SYS_CLK_EN - WEU SYS Clock Enable */
+#define CIU1_CIU_CLK_ENABLE2_WEU_SYS_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_WEU_SYS_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE2_WEU_SYS_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE2_HPU1_CIU_CLK_EN_MASK (0x10000000U)
+#define CIU1_CIU_CLK_ENABLE2_HPU1_CIU_CLK_EN_SHIFT (28U)
+/*! HPU1_CIU_CLK_EN - HPU1 CIU Clock Enable */
+#define CIU1_CIU_CLK_ENABLE2_HPU1_CIU_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_HPU1_CIU_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE2_HPU1_CIU_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE2_SMU1_TOP_CLK_EN_MASK (0x20000000U)
+#define CIU1_CIU_CLK_ENABLE2_SMU1_TOP_CLK_EN_SHIFT (29U)
+/*! SMU1_TOP_CLK_EN - SMU1 Top Clock Enable */
+#define CIU1_CIU_CLK_ENABLE2_SMU1_TOP_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_SMU1_TOP_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE2_SMU1_TOP_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE2_SMU1_PORT0_SYS_CLK_EN_MASK (0x40000000U)
+#define CIU1_CIU_CLK_ENABLE2_SMU1_PORT0_SYS_CLK_EN_SHIFT (30U)
+/*! SMU1_PORT0_SYS_CLK_EN - SMU1 Port 0 System Clock Enable */
+#define CIU1_CIU_CLK_ENABLE2_SMU1_PORT0_SYS_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE2_SMU1_PORT0_SYS_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE2_SMU1_PORT0_SYS_CLK_EN_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_ENABLE3 - Clock Enable 3 */
+/*! @{ */
+
+#define CIU1_CIU_CLK_ENABLE3_WL_MSC_A2A_CLK_EN_MASK (0x1U)
+#define CIU1_CIU_CLK_ENABLE3_WL_MSC_A2A_CLK_EN_SHIFT (0U)
+/*! WL_MSC_A2A_CLK_EN - Enable Clock for MSC A2A */
+#define CIU1_CIU_CLK_ENABLE3_WL_MSC_A2A_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_WL_MSC_A2A_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE3_WL_MSC_A2A_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_WL_SOC_A2A_CLK_EN_MASK (0x2U)
+#define CIU1_CIU_CLK_ENABLE3_WL_SOC_A2A_CLK_EN_SHIFT (1U)
+/*! WL_SOC_A2A_CLK_EN - Enable Clock for SOC A2A */
+#define CIU1_CIU_CLK_ENABLE3_WL_SOC_A2A_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_WL_SOC_A2A_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE3_WL_SOC_A2A_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_WLRTU1_CLK_EN_MASK  (0x40U)
+#define CIU1_CIU_CLK_ENABLE3_WLRTU1_CLK_EN_SHIFT (6U)
+/*! WLRTU1_CLK_EN - Enable WL RTU1 timer clock */
+#define CIU1_CIU_CLK_ENABLE3_WLRTU1_CLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_WLRTU1_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE3_WLRTU1_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_BRU_AHB1_ADDR_MASK_DIS_MASK (0x1000U)
+#define CIU1_CIU_CLK_ENABLE3_BRU_AHB1_ADDR_MASK_DIS_SHIFT (12U)
+/*! BRU_AHB1_ADDR_MASK_DIS - CPU1 ROM Address Mask Selection */
+#define CIU1_CIU_CLK_ENABLE3_BRU_AHB1_ADDR_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_BRU_AHB1_ADDR_MASK_DIS_SHIFT)) & CIU1_CIU_CLK_ENABLE3_BRU_AHB1_ADDR_MASK_DIS_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_BRU_AHB1_DYN_CLK_GATING_DIS_MASK (0x2000U)
+#define CIU1_CIU_CLK_ENABLE3_BRU_AHB1_DYN_CLK_GATING_DIS_SHIFT (13U)
+/*! BRU_AHB1_DYN_CLK_GATING_DIS - CPU1 ROM Dynamic Clock Gating Feature */
+#define CIU1_CIU_CLK_ENABLE3_BRU_AHB1_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_BRU_AHB1_DYN_CLK_GATING_DIS_SHIFT)) & CIU1_CIU_CLK_ENABLE3_BRU_AHB1_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_ITCM_AHB1_DYN_CLK_GATING_DIS_MASK (0x4000U)
+#define CIU1_CIU_CLK_ENABLE3_ITCM_AHB1_DYN_CLK_GATING_DIS_SHIFT (14U)
+/*! ITCM_AHB1_DYN_CLK_GATING_DIS - CPU1 ITCM/IMEM Dynamic Clock Gating Feature */
+#define CIU1_CIU_CLK_ENABLE3_ITCM_AHB1_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_ITCM_AHB1_DYN_CLK_GATING_DIS_SHIFT)) & CIU1_CIU_CLK_ENABLE3_ITCM_AHB1_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_DTCM_AHB1_DYN_CLK_GATING_DIS_MASK (0x8000U)
+#define CIU1_CIU_CLK_ENABLE3_DTCM_AHB1_DYN_CLK_GATING_DIS_SHIFT (15U)
+/*! DTCM_AHB1_DYN_CLK_GATING_DIS - CPU1 DTCM/DMEM Dynamic Clock Gating Feature */
+#define CIU1_CIU_CLK_ENABLE3_DTCM_AHB1_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_DTCM_AHB1_DYN_CLK_GATING_DIS_SHIFT)) & CIU1_CIU_CLK_ENABLE3_DTCM_AHB1_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_SMU1_BANK_SEG_CLK_EN_MASK (0xFF0000U)
+#define CIU1_CIU_CLK_ENABLE3_SMU1_BANK_SEG_CLK_EN_SHIFT (16U)
+/*! SMU1_BANK_SEG_CLK_EN - SMU1 bank segment Clock Enable */
+#define CIU1_CIU_CLK_ENABLE3_SMU1_BANK_SEG_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_SMU1_BANK_SEG_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE3_SMU1_BANK_SEG_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_MCI_A2A_CLK_EN_MASK (0x40000000U)
+#define CIU1_CIU_CLK_ENABLE3_MCI_A2A_CLK_EN_SHIFT (30U)
+/*! MCI_A2A_CLK_EN - Enable Clock for MCI A2A */
+#define CIU1_CIU_CLK_ENABLE3_MCI_A2A_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_MCI_A2A_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE3_MCI_A2A_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE3_SMU1_MEM_SYS_CLK_EN_MASK (0x80000000U)
+#define CIU1_CIU_CLK_ENABLE3_SMU1_MEM_SYS_CLK_EN_SHIFT (31U)
+/*! SMU1_MEM_SYS_CLK_EN - SMU1 mem banks and peripheral control logic Clock Enable */
+#define CIU1_CIU_CLK_ENABLE3_SMU1_MEM_SYS_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE3_SMU1_MEM_SYS_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE3_SMU1_MEM_SYS_CLK_EN_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_CPU1CLK_CTRL - CPU1_AHB1 Clock Control */
+/*! @{ */
+
+#define CIU1_CIU_CLK_CPU1CLK_CTRL_T1_FREQ_SEL_MASK (0xFU)
+#define CIU1_CIU_CLK_CPU1CLK_CTRL_T1_FREQ_SEL_SHIFT (0U)
+/*! T1_FREQ_SEL - CPU1 Clock Frequency Select */
+#define CIU1_CIU_CLK_CPU1CLK_CTRL_T1_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_CPU1CLK_CTRL_T1_FREQ_SEL_SHIFT)) & CIU1_CIU_CLK_CPU1CLK_CTRL_T1_FREQ_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_SYSCLK_CTRL - SYS Clock Control */
+/*! @{ */
+
+#define CIU1_CIU_CLK_SYSCLK_CTRL_T1_FREQ_SEL_MASK (0xFU)
+#define CIU1_CIU_CLK_SYSCLK_CTRL_T1_FREQ_SEL_SHIFT (0U)
+/*! T1_FREQ_SEL - Sys Clock Frequency Select */
+#define CIU1_CIU_CLK_SYSCLK_CTRL_T1_FREQ_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SYSCLK_CTRL_T1_FREQ_SEL_SHIFT)) & CIU1_CIU_CLK_SYSCLK_CTRL_T1_FREQ_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_RTU_NCO_CTRL - RTU NCO Clock Control */
+/*! @{ */
+
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_REF_CLK_SEL_MASK (0x1U)
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_REF_CLK_SEL_SHIFT (0U)
+/*! CIU_WLRTU_REF_CLK_SEL - RTU Reference Clock from UART reference clock tree */
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_REF_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_REF_CLK_SEL_MASK)
+
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_OUT_SEL_MASK (0x2U)
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_OUT_SEL_SHIFT (1U)
+/*! CIU_WLRTU_NCO_OUT_SEL - RTU NCO Mode Select (Reference Clock Based) */
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_OUT_SEL_SHIFT)) & CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_OUT_SEL_MASK)
+
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_ENABLE_MASK (0x4U)
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_ENABLE_SHIFT (2U)
+/*! CIU_WLRTU_NCO_ENABLE - RTU NCO Enable (Reference Clock Based) */
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_ENABLE_SHIFT)) & CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_ENABLE_MASK)
+
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_STEP_MASK (0xFFFF0000U)
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_STEP_SHIFT (16U)
+/*! CIU_WLRTU_NCO_STEP - Step size for RTU clock NCO (Reference Clock Based) */
+#define CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_STEP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_STEP_SHIFT)) & CIU1_CIU_CLK_RTU_NCO_CTRL_CIU_WLRTU_NCO_STEP_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_LBU1_WLRTU_CTRL - LBU1 WLRTU1 Clock Control */
+/*! @{ */
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_USE_REFCLK_MASK (0x2U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_USE_REFCLK_SHIFT (1U)
+/*! LBU1_USE_REFCLK - Static bit set by FW based on Reference Clock Frequency. If reference clock
+ *    frequency is lower and LBU can not support high baud rate of UART, then FW will set
+ *    soc_use_ref_mode = 0. This is an indication for Bluetooth subsystem that there is some IP which need PLL
+ *    to function which is LBU in this case.
+ */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_USE_REFCLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_USE_REFCLK_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_USE_REFCLK_MASK)
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_EN_MASK (0x4U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_EN_SHIFT (2U)
+/*! LBU1_CLK_SCALE_EN - Enable lbu1 lsb clock div (upto div by 3/4/5/6 only) */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_EN_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_EN_MASK)
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_FACTOR_MASK (0x38U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_FACTOR_SHIFT (3U)
+/*! LBU1_CLK_SCALE_FACTOR - lbu1 lsb clock divider value[2:0] */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_FACTOR_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_CLK_SCALE_FACTOR_MASK)
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_HIGH_BAUD_SEL_MASK (0x40U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_HIGH_BAUD_SEL_SHIFT (6U)
+/*! LBU1_HIGH_BAUD_SEL - PBU Bus Reference Clock */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_HIGH_BAUD_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_HIGH_BAUD_SEL_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_HIGH_BAUD_SEL_MASK)
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_DIV_BY_2_SEL_MASK (0x80U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_DIV_BY_2_SEL_SHIFT (7U)
+/*! LBU1_DIV_BY_2_SEL - PBU Bus Reference Clock */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_DIV_BY_2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_DIV_BY_2_SEL_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_LBU1_DIV_BY_2_SEL_MASK)
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_TIMER1_USE_SLP_CLK_MASK (0x800U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_TIMER1_USE_SLP_CLK_SHIFT (11U)
+/*! WLRTU1_TIMER1_USE_SLP_CLK - Timer 1 WL_RTU1 Clock */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_TIMER1_USE_SLP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_TIMER1_USE_SLP_CLK_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_TIMER1_USE_SLP_CLK_MASK)
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_USE_REF_CLK_MASK (0x1000U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_USE_REF_CLK_SHIFT (12U)
+/*! WLRTU1_USE_REF_CLK - Static bit set by FW. If it is required that timers need not be programmed
+ *    with dynamic switching of T1/Reference, the WL_RTU1 source clock is set on reference clock so
+ *    that the timer are not disturbed.
+ */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_USE_REF_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_USE_REF_CLK_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_USE_REF_CLK_MASK)
+
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_DBG_CLK_CTRL_MASK (0x8000U)
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_DBG_CLK_CTRL_SHIFT (15U)
+/*! WLRTU1_DBG_CLK_CTRL - WLRTU1 Debug Clock Control Feature */
+#define CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_DBG_CLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_DBG_CLK_CTRL_SHIFT)) & CIU1_CIU_CLK_LBU1_WLRTU_CTRL_WLRTU1_DBG_CLK_CTRL_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_SOCCLK_CTRL - SOC Clock Control */
+/*! @{ */
+
+#define CIU1_CIU_CLK_SOCCLK_CTRL_EU1_CORE_CLK_SEL_MASK (0x3U)
+#define CIU1_CIU_CLK_SOCCLK_CTRL_EU1_CORE_CLK_SEL_SHIFT (0U)
+/*! EU1_CORE_CLK_SEL - EU1 Core Clock Select */
+#define CIU1_CIU_CLK_SOCCLK_CTRL_EU1_CORE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SOCCLK_CTRL_EU1_CORE_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_SOCCLK_CTRL_EU1_CORE_CLK_SEL_MASK)
+
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CONST_CAL_CLK_SEL_MASK (0x400U)
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CONST_CAL_CLK_SEL_SHIFT (10U)
+/*! CIU_WLAPU_CONST_CAL_CLK_SEL - PMU Constant Calibration Clock Select */
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CONST_CAL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CONST_CAL_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CONST_CAL_CLK_SEL_MASK)
+
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CAL_CLK_SEL_MASK (0x800U)
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CAL_CLK_SEL_SHIFT (11U)
+/*! CIU_WLAPU_CAL_CLK_SEL - PMU Calibration Clock */
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CAL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CAL_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_SOCCLK_CTRL_CIU_WLAPU_CAL_CLK_SEL_MASK)
+
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_MASK (0x4000U)
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_SHIFT (14U)
+/*! CIU_USE_REFCLK - SoC_Clk Clock */
+#define CIU1_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_SHIFT)) & CIU1_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_MASK)
+
+#define CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_PCLK_DIV_SEL_MASK (0xF0000U)
+#define CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_PCLK_DIV_SEL_SHIFT (16U)
+/*! WL_AHB2APB_PCLK_DIV_SEL - WL AHB2APB PCLK Divider Select */
+#define CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_PCLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_PCLK_DIV_SEL_SHIFT)) & CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_PCLK_DIV_SEL_MASK)
+
+#define CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_WAIT_CYCLES_MASK (0xF0000000U)
+#define CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_WAIT_CYCLES_SHIFT (28U)
+/*! WL_AHB2APB_WAIT_CYCLES - WL AHB2APB Wait Cycles between each APB transaction */
+#define CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_WAIT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_WAIT_CYCLES_SHIFT)) & CIU1_CIU_CLK_SOCCLK_CTRL_WL_AHB2APB_WAIT_CYCLES_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_SLEEPCLK_CTRL - Sleep Clock Control */
+/*! @{ */
+
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_MASK (0xFFFFFFU)
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_SHIFT (0U)
+/*! CIU_SLEEP_CLK_NCO_MVAL - Sleep Clock NCO */
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_SHIFT)) & CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_MASK)
+
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_MASK (0x2000000U)
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_SHIFT (25U)
+/*! CIU_NCO_SLEEP_CLK_SEL - NCO Sleep Clock Select */
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_MASK)
+
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_MASK (0x10000000U)
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_SHIFT (28U)
+/*! CIU_REFCLK_SLEEP_CLK_SEL - Reference Clock Sleep Clock Select */
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_CP15_DIS1 - Clock Auto Shut-off Enable1 */
+/*! @{ */
+
+#define CIU1_CIU_CLK_CP15_DIS1_WLAN_HCLK_MASK    (0x40000U)
+#define CIU1_CIU_CLK_CP15_DIS1_WLAN_HCLK_SHIFT   (18U)
+/*! WLAN_HCLK - WLAN ahb Arbiter/Decoder Shut Off */
+#define CIU1_CIU_CLK_CP15_DIS1_WLAN_HCLK(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_CP15_DIS1_WLAN_HCLK_SHIFT)) & CIU1_CIU_CLK_CP15_DIS1_WLAN_HCLK_MASK)
+
+#define CIU1_CIU_CLK_CP15_DIS1_CP15_DIS_WLAPU_AHB_CLK_MASK (0x100000U)
+#define CIU1_CIU_CLK_CP15_DIS1_CP15_DIS_WLAPU_AHB_CLK_SHIFT (20U)
+/*! CP15_DIS_WLAPU_AHB_CLK - APU Shut Off */
+#define CIU1_CIU_CLK_CP15_DIS1_CP15_DIS_WLAPU_AHB_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_CP15_DIS1_CP15_DIS_WLAPU_AHB_CLK_SHIFT)) & CIU1_CIU_CLK_CP15_DIS1_CP15_DIS_WLAPU_AHB_CLK_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_CP15_DIS2 - Clock Auto Shut-off Enable2 */
+/*! @{ */
+
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_BROM_CLK_MASK (0x1FU)
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_BROM_CLK_SHIFT (0U)
+/*! CP15_DIS_CPU1_BROM_CLK - APU Shut Off */
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_BROM_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_BROM_CLK_SHIFT)) & CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_BROM_CLK_MASK)
+
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_DMEM_CLK_MASK (0x300U)
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_DMEM_CLK_SHIFT (8U)
+/*! CP15_DIS_CPU1_DMEM_CLK - APU Shut Off */
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_DMEM_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_DMEM_CLK_SHIFT)) & CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_DMEM_CLK_MASK)
+
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_IMEM_CLK_MASK (0x1F0000U)
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_IMEM_CLK_SHIFT (16U)
+/*! CP15_DIS_CPU1_IMEM_CLK - APU Shut Off 0 = disable this auto shut off feature 1 = AHB clock for
+ *    the IMEM is automatically shut off while CPU is asleep
+ */
+#define CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_IMEM_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_IMEM_CLK_SHIFT)) & CIU1_CIU_CLK_CP15_DIS2_CP15_DIS_CPU1_IMEM_CLK_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_CP15_DIS3 - Clock Auto Shut-off Enable3 */
+/*! @{ */
+
+#define CIU1_CIU_CLK_CP15_DIS3_CP15_DIS_WEU_AHB_CLK_MASK (0x100000U)
+#define CIU1_CIU_CLK_CP15_DIS3_CP15_DIS_WEU_AHB_CLK_SHIFT (20U)
+/*! CP15_DIS_WEU_AHB_CLK - TKIP/WEP WEU AHB Shut Off */
+#define CIU1_CIU_CLK_CP15_DIS3_CP15_DIS_WEU_AHB_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_CP15_DIS3_CP15_DIS_WEU_AHB_CLK_SHIFT)) & CIU1_CIU_CLK_CP15_DIS3_CP15_DIS_WEU_AHB_CLK_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_ENABLE6 - Clock Enable 6 */
+/*! @{ */
+
+#define CIU1_CIU_CLK_ENABLE6_CAU_SIF_CLK_SEL_MASK (0x100U)
+#define CIU1_CIU_CLK_ENABLE6_CAU_SIF_CLK_SEL_SHIFT (8U)
+/*! CAU_SIF_CLK_SEL - CAU SIF Clock Select */
+#define CIU1_CIU_CLK_ENABLE6_CAU_SIF_CLK_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE6_CAU_SIF_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_ENABLE6_CAU_SIF_CLK_SEL_MASK)
+
+#define CIU1_CIU_CLK_ENABLE6_CAU_SIF_AHB1_CLK_EN_MASK (0x200U)
+#define CIU1_CIU_CLK_ENABLE6_CAU_SIF_AHB1_CLK_EN_SHIFT (9U)
+/*! CAU_SIF_AHB1_CLK_EN - CAU AHB2SIF AHB clock enable */
+#define CIU1_CIU_CLK_ENABLE6_CAU_SIF_AHB1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE6_CAU_SIF_AHB1_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE6_CAU_SIF_AHB1_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE6_GPS_PPS_CLK_EN_MASK (0x400U)
+#define CIU1_CIU_CLK_ENABLE6_GPS_PPS_CLK_EN_SHIFT (10U)
+/*! GPS_PPS_CLK_EN - GPS PPS Clock Enable */
+#define CIU1_CIU_CLK_ENABLE6_GPS_PPS_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE6_GPS_PPS_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE6_GPS_PPS_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE6_MAC1_G2BIST_CLK_EN_MASK (0x800U)
+#define CIU1_CIU_CLK_ENABLE6_MAC1_G2BIST_CLK_EN_SHIFT (11U)
+/*! MAC1_G2BIST_CLK_EN - Clock Enable for MAC1 BIST Controller Clock */
+#define CIU1_CIU_CLK_ENABLE6_MAC1_G2BIST_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE6_MAC1_G2BIST_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE6_MAC1_G2BIST_CLK_EN_MASK)
+
+#define CIU1_CIU_CLK_ENABLE6_BBUD_MAC_CLK_SEL_MASK (0x2000U)
+#define CIU1_CIU_CLK_ENABLE6_BBUD_MAC_CLK_SEL_SHIFT (13U)
+/*! BBUD_MAC_CLK_SEL - BBUD MAC Clock Select */
+#define CIU1_CIU_CLK_ENABLE6_BBUD_MAC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE6_BBUD_MAC_CLK_SEL_SHIFT)) & CIU1_CIU_CLK_ENABLE6_BBUD_MAC_CLK_SEL_MASK)
+
+#define CIU1_CIU_CLK_ENABLE6_PTP_CLK_EN_MASK     (0x4000U)
+#define CIU1_CIU_CLK_ENABLE6_PTP_CLK_EN_SHIFT    (14U)
+/*! PTP_CLK_EN - PTP input capture pulse interrupt clock enable */
+#define CIU1_CIU_CLK_ENABLE6_PTP_CLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ENABLE6_PTP_CLK_EN_SHIFT)) & CIU1_CIU_CLK_ENABLE6_PTP_CLK_EN_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_SLEEPCLK_CTRL2 - Sleep Clock Control 2 */
+/*! @{ */
+
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_MASK (0xFFFFFFU)
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_SHIFT (0U)
+/*! CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP - Sleep Clock NCO value for the sleep mode */
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_SHIFT)) & CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_MASK)
+
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_MASK (0x1000000U)
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_SHIFT (24U)
+/*! CIU_SLEEP_CLK_NCO_MVAL_BYPASS - Sleep Clock NCO MVAL Bypass Feature */
+#define CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_SHIFT)) & CIU1_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_MASK)
+/*! @} */
+
+/*! @name CIU_MAC_CLK_CTRL - MAC clock CTRL */
+/*! @{ */
+
+#define CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_EN_MASK (0x1U)
+#define CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_EN_SHIFT (0U)
+/*! MAC1_BBUD_BYPASS_EN - Bypass 11J_EN and PUB_SFT from BBUD1 */
+#define CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_EN_SHIFT)) & CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_EN_MASK)
+
+#define CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_VAL_MASK (0x6U)
+#define CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_VAL_SHIFT (1U)
+/*! MAC1_BBUD_BYPASS_VAL - Bypass value */
+#define CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_VAL_SHIFT)) & CIU1_CIU_MAC_CLK_CTRL_MAC1_BBUD_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_ECO_CTRL - Clock ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_CLK_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_CLK_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_CLK_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CLK_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_CLK_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_RST_SW1 - Software Module Reset */
+/*! @{ */
+
+#define CIU1_CIU_RST_SW1_HPU1__MASK              (0x1U)
+#define CIU1_CIU_RST_SW1_HPU1__SHIFT             (0U)
+/*! HPU1_ - HPU1 Reset */
+#define CIU1_CIU_RST_SW1_HPU1_(x)                (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_HPU1__SHIFT)) & CIU1_CIU_RST_SW1_HPU1__MASK)
+
+#define CIU1_CIU_RST_SW1_SMU1_PORT0_SYS_CLK_N_MASK (0x4U)
+#define CIU1_CIU_RST_SW1_SMU1_PORT0_SYS_CLK_N_SHIFT (2U)
+/*! SMU1_PORT0_SYS_CLK_N - SMU1 port 0 (SYS_Clk) Soft Reset */
+#define CIU1_CIU_RST_SW1_SMU1_PORT0_SYS_CLK_N(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_SMU1_PORT0_SYS_CLK_N_SHIFT)) & CIU1_CIU_RST_SW1_SMU1_PORT0_SYS_CLK_N_MASK)
+
+#define CIU1_CIU_RST_SW1_SMU1_MEM_CLK__MASK      (0x8U)
+#define CIU1_CIU_RST_SW1_SMU1_MEM_CLK__SHIFT     (3U)
+/*! SMU1_MEM_CLK_ - SMU1 bank clock Soft Reset */
+#define CIU1_CIU_RST_SW1_SMU1_MEM_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_SMU1_MEM_CLK__SHIFT)) & CIU1_CIU_RST_SW1_SMU1_MEM_CLK__MASK)
+
+#define CIU1_CIU_RST_SW1_SMU1_TM_RST__MASK       (0x80U)
+#define CIU1_CIU_RST_SW1_SMU1_TM_RST__SHIFT      (7U)
+/*! SMU1_TM_RST_ - SMU1 testmode logic reset */
+#define CIU1_CIU_RST_SW1_SMU1_TM_RST_(x)         (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_SMU1_TM_RST__SHIFT)) & CIU1_CIU_RST_SW1_SMU1_TM_RST__MASK)
+
+#define CIU1_CIU_RST_SW1_WEU_SYS_CLK_N_MASK      (0x100U)
+#define CIU1_CIU_RST_SW1_WEU_SYS_CLK_N_SHIFT     (8U)
+/*! WEU_SYS_CLK_N - WEU sys clock domain soft reset */
+#define CIU1_CIU_RST_SW1_WEU_SYS_CLK_N(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_WEU_SYS_CLK_N_SHIFT)) & CIU1_CIU_RST_SW1_WEU_SYS_CLK_N_MASK)
+
+#define CIU1_CIU_RST_SW1_WEU_AHB_CLK_N_MASK      (0x200U)
+#define CIU1_CIU_RST_SW1_WEU_AHB_CLK_N_SHIFT     (9U)
+/*! WEU_AHB_CLK_N - WEU ahb clock domain soft reset */
+#define CIU1_CIU_RST_SW1_WEU_AHB_CLK_N(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_WEU_AHB_CLK_N_SHIFT)) & CIU1_CIU_RST_SW1_WEU_AHB_CLK_N_MASK)
+
+#define CIU1_CIU_RST_SW1_CIU1_CFG_RST__MASK      (0x400U)
+#define CIU1_CIU_RST_SW1_CIU1_CFG_RST__SHIFT     (10U)
+/*! CIU1_CFG_RST_ - CIU ahb clock domain Soft Reset */
+#define CIU1_CIU_RST_SW1_CIU1_CFG_RST_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_CIU1_CFG_RST__SHIFT)) & CIU1_CIU_RST_SW1_CIU1_CFG_RST__MASK)
+
+#define CIU1_CIU_RST_SW1_CIU1_REGISTER_RST__MASK (0x800U)
+#define CIU1_CIU_RST_SW1_CIU1_REGISTER_RST__SHIFT (11U)
+/*! CIU1_REGISTER_RST_ - CIU_Reg Module Soft Reset */
+#define CIU1_CIU_RST_SW1_CIU1_REGISTER_RST_(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_CIU1_REGISTER_RST__SHIFT)) & CIU1_CIU_RST_SW1_CIU1_REGISTER_RST__MASK)
+
+#define CIU1_CIU_RST_SW1_MCU1_SYS_CLK__MASK      (0x8000U)
+#define CIU1_CIU_RST_SW1_MCU1_SYS_CLK__SHIFT     (15U)
+/*! MCU1_SYS_CLK_ - MCU1 sysclk domain Soft Reset */
+#define CIU1_CIU_RST_SW1_MCU1_SYS_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_MCU1_SYS_CLK__SHIFT)) & CIU1_CIU_RST_SW1_MCU1_SYS_CLK__MASK)
+
+#define CIU1_CIU_RST_SW1_WL_AHB2APB_CLK_N_MASK   (0x10000U)
+#define CIU1_CIU_RST_SW1_WL_AHB2APB_CLK_N_SHIFT  (16U)
+/*! WL_AHB2APB_CLK_N - WL AHB2APB AHB clock domain reset */
+#define CIU1_CIU_RST_SW1_WL_AHB2APB_CLK_N(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_WL_AHB2APB_CLK_N_SHIFT)) & CIU1_CIU_RST_SW1_WL_AHB2APB_CLK_N_MASK)
+
+#define CIU1_CIU_RST_SW1_WL_AHB_RST__MASK        (0x80000U)
+#define CIU1_CIU_RST_SW1_WL_AHB_RST__SHIFT       (19U)
+/*! WL_AHB_RST_ - WL AHB Decoder Mux and Arbiter and CIU AHB intf Soft Reset */
+#define CIU1_CIU_RST_SW1_WL_AHB_RST_(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_WL_AHB_RST__SHIFT)) & CIU1_CIU_RST_SW1_WL_AHB_RST__MASK)
+
+#define CIU1_CIU_RST_SW1_LBU1__MASK              (0x100000U)
+#define CIU1_CIU_RST_SW1_LBU1__SHIFT             (20U)
+/*! LBU1_ - LBU1 Soft Reset */
+#define CIU1_CIU_RST_SW1_LBU1_(x)                (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_LBU1__SHIFT)) & CIU1_CIU_RST_SW1_LBU1__MASK)
+
+#define CIU1_CIU_RST_SW1_WLAPU_REF_CLK__MASK     (0x200000U)
+#define CIU1_CIU_RST_SW1_WLAPU_REF_CLK__SHIFT    (21U)
+/*! WLAPU_REF_CLK_ - APU ref Clock Reset */
+#define CIU1_CIU_RST_SW1_WLAPU_REF_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_WLAPU_REF_CLK__SHIFT)) & CIU1_CIU_RST_SW1_WLAPU_REF_CLK__MASK)
+
+#define CIU1_CIU_RST_SW1_BBU1_DSP__MASK          (0x1000000U)
+#define CIU1_CIU_RST_SW1_BBU1_DSP__SHIFT         (24U)
+/*! BBU1_DSP_ - BBU1_DSP Reset */
+#define CIU1_CIU_RST_SW1_BBU1_DSP_(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_BBU1_DSP__SHIFT)) & CIU1_CIU_RST_SW1_BBU1_DSP__MASK)
+
+#define CIU1_CIU_RST_SW1_RFU1_PR__MASK           (0x2000000U)
+#define CIU1_CIU_RST_SW1_RFU1_PR__SHIFT          (25U)
+/*! RFU1_PR_ - RFU1_PR Reset */
+#define CIU1_CIU_RST_SW1_RFU1_PR_(x)             (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_RFU1_PR__SHIFT)) & CIU1_CIU_RST_SW1_RFU1_PR__MASK)
+
+#define CIU1_CIU_RST_SW1_WLAPU_AHB_CLK__MASK     (0x4000000U)
+#define CIU1_CIU_RST_SW1_WLAPU_AHB_CLK__SHIFT    (26U)
+/*! WLAPU_AHB_CLK_ - APU ARM Clock Reset */
+#define CIU1_CIU_RST_SW1_WLAPU_AHB_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_WLAPU_AHB_CLK__SHIFT)) & CIU1_CIU_RST_SW1_WLAPU_AHB_CLK__MASK)
+
+#define CIU1_CIU_RST_SW1_WLAPU_SLP_CLK__MASK     (0x8000000U)
+#define CIU1_CIU_RST_SW1_WLAPU_SLP_CLK__SHIFT    (27U)
+/*! WLAPU_SLP_CLK_ - APU Sleep Clock domain Reset */
+#define CIU1_CIU_RST_SW1_WLAPU_SLP_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_WLAPU_SLP_CLK__SHIFT)) & CIU1_CIU_RST_SW1_WLAPU_SLP_CLK__MASK)
+
+#define CIU1_CIU_RST_SW1_MCU1_MCLK__MASK         (0x10000000U)
+#define CIU1_CIU_RST_SW1_MCU1_MCLK__SHIFT        (28U)
+/*! MCU1_MCLK_ - MCU1 MCLK domain reset */
+#define CIU1_CIU_RST_SW1_MCU1_MCLK_(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_MCU1_MCLK__SHIFT)) & CIU1_CIU_RST_SW1_MCU1_MCLK__MASK)
+
+#define CIU1_CIU_RST_SW1_EU1_CORE_CLK__MASK      (0x20000000U)
+#define CIU1_CIU_RST_SW1_EU1_CORE_CLK__SHIFT     (29U)
+/*! EU1_CORE_CLK_ - EU1 Core Soft Reset */
+#define CIU1_CIU_RST_SW1_EU1_CORE_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_EU1_CORE_CLK__SHIFT)) & CIU1_CIU_RST_SW1_EU1_CORE_CLK__MASK)
+
+#define CIU1_CIU_RST_SW1_MCU1_AHB_CLK__MASK      (0x80000000U)
+#define CIU1_CIU_RST_SW1_MCU1_AHB_CLK__SHIFT     (31U)
+/*! MCU1_AHB_CLK_ - MCU1 AHB Soft Reset */
+#define CIU1_CIU_RST_SW1_MCU1_AHB_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW1_MCU1_AHB_CLK__SHIFT)) & CIU1_CIU_RST_SW1_MCU1_AHB_CLK__MASK)
+/*! @} */
+
+/*! @name CIU_RST_SW2 - Software Module Reset */
+/*! @{ */
+
+#define CIU1_CIU_RST_SW2_W1_CLK__MASK            (0x1U)
+#define CIU1_CIU_RST_SW2_W1_CLK__SHIFT           (0U)
+/*! W1_CLK_ - W1 Interface (PM chip) Soft Reset */
+#define CIU1_CIU_RST_SW2_W1_CLK_(x)              (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_W1_CLK__SHIFT)) & CIU1_CIU_RST_SW2_W1_CLK__MASK)
+
+#define CIU1_CIU_RST_SW2_BRU_AHB1_CLK__MASK      (0x8U)
+#define CIU1_CIU_RST_SW2_BRU_AHB1_CLK__SHIFT     (3U)
+/*! BRU_AHB1_CLK_ - BRU_AHB1 Soft Reset */
+#define CIU1_CIU_RST_SW2_BRU_AHB1_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_BRU_AHB1_CLK__SHIFT)) & CIU1_CIU_RST_SW2_BRU_AHB1_CLK__MASK)
+
+#define CIU1_CIU_RST_SW2_IPS_CLK__MASK           (0x2000U)
+#define CIU1_CIU_RST_SW2_IPS_CLK__SHIFT          (13U)
+/*! IPS_CLK_ - ips functional clock SW reset */
+#define CIU1_CIU_RST_SW2_IPS_CLK_(x)             (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_IPS_CLK__SHIFT)) & CIU1_CIU_RST_SW2_IPS_CLK__MASK)
+
+#define CIU1_CIU_RST_SW2_IPS_PROM_CLK__MASK      (0x4000U)
+#define CIU1_CIU_RST_SW2_IPS_PROM_CLK__SHIFT     (14U)
+/*! IPS_PROM_CLK_ - SW reset for ips_prom_clk */
+#define CIU1_CIU_RST_SW2_IPS_PROM_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_IPS_PROM_CLK__SHIFT)) & CIU1_CIU_RST_SW2_IPS_PROM_CLK__MASK)
+
+#define CIU1_CIU_RST_SW2_WLAN_SUB_G2BIST_RSTB_MASK (0x8000U)
+#define CIU1_CIU_RST_SW2_WLAN_SUB_G2BIST_RSTB_SHIFT (15U)
+/*! WLAN_SUB_G2BIST_RSTB - SW reset for wlan sub-system g2bist controller */
+#define CIU1_CIU_RST_SW2_WLAN_SUB_G2BIST_RSTB(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_WLAN_SUB_G2BIST_RSTB_SHIFT)) & CIU1_CIU_RST_SW2_WLAN_SUB_G2BIST_RSTB_MASK)
+
+#define CIU1_CIU_RST_SW2_IPS_HCLK__MASK          (0x80000U)
+#define CIU1_CIU_RST_SW2_IPS_HCLK__SHIFT         (19U)
+/*! IPS_HCLK_ - ips block hresetn */
+#define CIU1_CIU_RST_SW2_IPS_HCLK_(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_IPS_HCLK__SHIFT)) & CIU1_CIU_RST_SW2_IPS_HCLK__MASK)
+
+#define CIU1_CIU_RST_SW2_CPU1_TCM__MASK          (0x400000U)
+#define CIU1_CIU_RST_SW2_CPU1_TCM__SHIFT         (22U)
+/*! CPU1_TCM_ - CPU1 TCM/DMA/Arbiter reset */
+#define CIU1_CIU_RST_SW2_CPU1_TCM_(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_CPU1_TCM__SHIFT)) & CIU1_CIU_RST_SW2_CPU1_TCM__MASK)
+
+#define CIU1_CIU_RST_SW2_APB__MASK               (0x800000U)
+#define CIU1_CIU_RST_SW2_APB__SHIFT              (23U)
+/*! APB_ - APB core clock Soft Reset (TBD_TREEPIE may not need this) */
+#define CIU1_CIU_RST_SW2_APB_(x)                 (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_APB__SHIFT)) & CIU1_CIU_RST_SW2_APB__MASK)
+
+#define CIU1_CIU_RST_SW2_WD1_CHIP_RST_DISABLE_MASK (0x10000000U)
+#define CIU1_CIU_RST_SW2_WD1_CHIP_RST_DISABLE_SHIFT (28U)
+/*! WD1_CHIP_RST_DISABLE - WD1 Chip Reset Disable Feature */
+#define CIU1_CIU_RST_SW2_WD1_CHIP_RST_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_WD1_CHIP_RST_DISABLE_SHIFT)) & CIU1_CIU_RST_SW2_WD1_CHIP_RST_DISABLE_MASK)
+
+#define CIU1_CIU_RST_SW2_WD1_CPU1_RST_DISABLE_MASK (0x20000000U)
+#define CIU1_CIU_RST_SW2_WD1_CPU1_RST_DISABLE_SHIFT (29U)
+/*! WD1_CPU1_RST_DISABLE - CPU1 Reset Disable Feature */
+#define CIU1_CIU_RST_SW2_WD1_CPU1_RST_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_WD1_CPU1_RST_DISABLE_SHIFT)) & CIU1_CIU_RST_SW2_WD1_CPU1_RST_DISABLE_MASK)
+
+#define CIU1_CIU_RST_SW2_CPU1_CORE__MASK         (0x40000000U)
+#define CIU1_CIU_RST_SW2_CPU1_CORE__SHIFT        (30U)
+/*! CPU1_CORE_ - CPU1 core reset */
+#define CIU1_CIU_RST_SW2_CPU1_CORE_(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW2_CPU1_CORE__SHIFT)) & CIU1_CIU_RST_SW2_CPU1_CORE__MASK)
+/*! @} */
+
+/*! @name CIU_RST_SW4 - Software Module Reset */
+/*! @{ */
+
+#define CIU1_CIU_RST_SW4_CPU1_DBG__MASK          (0x1U)
+#define CIU1_CIU_RST_SW4_CPU1_DBG__SHIFT         (0U)
+/*! CPU1_DBG_ - CPU1 debug logic soft reset. */
+#define CIU1_CIU_RST_SW4_CPU1_DBG_(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_CPU1_DBG__SHIFT)) & CIU1_CIU_RST_SW4_CPU1_DBG__MASK)
+
+#define CIU1_CIU_RST_SW4_CPU1_WATCHDOG__MASK     (0x2U)
+#define CIU1_CIU_RST_SW4_CPU1_WATCHDOG__SHIFT    (1U)
+/*! CPU1_WATCHDOG_ - CPU1 watchdog logic soft reset */
+#define CIU1_CIU_RST_SW4_CPU1_WATCHDOG_(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_CPU1_WATCHDOG__SHIFT)) & CIU1_CIU_RST_SW4_CPU1_WATCHDOG__MASK)
+
+#define CIU1_CIU_RST_SW4_CPU1_G2BIST__MASK       (0x8U)
+#define CIU1_CIU_RST_SW4_CPU1_G2BIST__SHIFT      (3U)
+/*! CPU1_G2BIST_ - CPU1 g2bist soft reset */
+#define CIU1_CIU_RST_SW4_CPU1_G2BIST_(x)         (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_CPU1_G2BIST__SHIFT)) & CIU1_CIU_RST_SW4_CPU1_G2BIST__MASK)
+
+#define CIU1_CIU_RST_SW4_CAU_SIF__MASK           (0x10U)
+#define CIU1_CIU_RST_SW4_CAU_SIF__SHIFT          (4U)
+/*! CAU_SIF_ - CAU sif clock Soft Reset */
+#define CIU1_CIU_RST_SW4_CAU_SIF_(x)             (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_CAU_SIF__SHIFT)) & CIU1_CIU_RST_SW4_CAU_SIF__MASK)
+
+#define CIU1_CIU_RST_SW4_CAU_SIF_AHB1_CLK__MASK  (0x20U)
+#define CIU1_CIU_RST_SW4_CAU_SIF_AHB1_CLK__SHIFT (5U)
+/*! CAU_SIF_AHB1_CLK_ - CAU sif ahb1 Clock Soft Reset */
+#define CIU1_CIU_RST_SW4_CAU_SIF_AHB1_CLK_(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_CAU_SIF_AHB1_CLK__SHIFT)) & CIU1_CIU_RST_SW4_CAU_SIF_AHB1_CLK__MASK)
+
+#define CIU1_CIU_RST_SW4_WLM_SYS_CLK__MASK       (0x200000U)
+#define CIU1_CIU_RST_SW4_WLM_SYS_CLK__SHIFT      (21U)
+/*! WLM_SYS_CLK_ - WLM SYS CLK Soft Reset */
+#define CIU1_CIU_RST_SW4_WLM_SYS_CLK_(x)         (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_WLM_SYS_CLK__SHIFT)) & CIU1_CIU_RST_SW4_WLM_SYS_CLK__MASK)
+
+#define CIU1_CIU_RST_SW4_WL_SYS_CLK__MASK        (0x400000U)
+#define CIU1_CIU_RST_SW4_WL_SYS_CLK__SHIFT       (22U)
+/*! WL_SYS_CLK_ - WL SYS CLK Soft Reset (Not used in Rendfinch) */
+#define CIU1_CIU_RST_SW4_WL_SYS_CLK_(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_WL_SYS_CLK__SHIFT)) & CIU1_CIU_RST_SW4_WL_SYS_CLK__MASK)
+
+#define CIU1_CIU_RST_SW4_MCU1_AHB_CLK_RETENTION__MASK (0x1000000U)
+#define CIU1_CIU_RST_SW4_MCU1_AHB_CLK_RETENTION__SHIFT (24U)
+/*! MCU1_AHB_CLK_RETENTION_ - MCU1 AHB Soft Retention Reset */
+#define CIU1_CIU_RST_SW4_MCU1_AHB_CLK_RETENTION_(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_MCU1_AHB_CLK_RETENTION__SHIFT)) & CIU1_CIU_RST_SW4_MCU1_AHB_CLK_RETENTION__MASK)
+
+#define CIU1_CIU_RST_SW4_MCU1_MCLK_RETENTION__MASK (0x2000000U)
+#define CIU1_CIU_RST_SW4_MCU1_MCLK_RETENTION__SHIFT (25U)
+/*! MCU1_MCLK_RETENTION_ - MCU1 MCLK domain retention reset */
+#define CIU1_CIU_RST_SW4_MCU1_MCLK_RETENTION_(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_MCU1_MCLK_RETENTION__SHIFT)) & CIU1_CIU_RST_SW4_MCU1_MCLK_RETENTION__MASK)
+
+#define CIU1_CIU_RST_SW4_MCU1_SYS_CLK_RETENTION__MASK (0x4000000U)
+#define CIU1_CIU_RST_SW4_MCU1_SYS_CLK_RETENTION__SHIFT (26U)
+/*! MCU1_SYS_CLK_RETENTION_ - MCU1 sysclk domain Soft Retention Reset */
+#define CIU1_CIU_RST_SW4_MCU1_SYS_CLK_RETENTION_(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW4_MCU1_SYS_CLK_RETENTION__SHIFT)) & CIU1_CIU_RST_SW4_MCU1_SYS_CLK_RETENTION__MASK)
+/*! @} */
+
+/*! @name CIU_RST_SW5 - Software Module Reset */
+/*! @{ */
+
+#define CIU1_CIU_RST_SW5_WL_MSC_A2A__MASK        (0x8U)
+#define CIU1_CIU_RST_SW5_WL_MSC_A2A__SHIFT       (3U)
+/*! WL_MSC_A2A_ - MSC a2a soft reset */
+#define CIU1_CIU_RST_SW5_WL_MSC_A2A_(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_WL_MSC_A2A__SHIFT)) & CIU1_CIU_RST_SW5_WL_MSC_A2A__MASK)
+
+#define CIU1_CIU_RST_SW5_WL_SOC_A2A__MASK        (0x10U)
+#define CIU1_CIU_RST_SW5_WL_SOC_A2A__SHIFT       (4U)
+/*! WL_SOC_A2A_ - SOC TOP a2a soft reset */
+#define CIU1_CIU_RST_SW5_WL_SOC_A2A_(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_WL_SOC_A2A__SHIFT)) & CIU1_CIU_RST_SW5_WL_SOC_A2A__MASK)
+
+#define CIU1_CIU_RST_SW5_SMU1_AHB_RST__MASK      (0x20U)
+#define CIU1_CIU_RST_SW5_SMU1_AHB_RST__SHIFT     (5U)
+/*! SMU1_AHB_RST_ - SW reset for smu1 ahb */
+#define CIU1_CIU_RST_SW5_SMU1_AHB_RST_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_SMU1_AHB_RST__SHIFT)) & CIU1_CIU_RST_SW5_SMU1_AHB_RST__MASK)
+
+#define CIU1_CIU_RST_SW5_MCI_LITE2AHB_RST__MASK  (0x40U)
+#define CIU1_CIU_RST_SW5_MCI_LITE2AHB_RST__SHIFT (6U)
+/*! MCI_LITE2AHB_RST_ - SW reset to mci lite2ahb in wl_top */
+#define CIU1_CIU_RST_SW5_MCI_LITE2AHB_RST_(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_MCI_LITE2AHB_RST__SHIFT)) & CIU1_CIU_RST_SW5_MCI_LITE2AHB_RST__MASK)
+
+#define CIU1_CIU_RST_SW5_SMU1_CFG_RST__MASK      (0x80U)
+#define CIU1_CIU_RST_SW5_SMU1_CFG_RST__SHIFT     (7U)
+/*! SMU1_CFG_RST_ - SW reset for smu1 reg */
+#define CIU1_CIU_RST_SW5_SMU1_CFG_RST_(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_SMU1_CFG_RST__SHIFT)) & CIU1_CIU_RST_SW5_SMU1_CFG_RST__MASK)
+
+#define CIU1_CIU_RST_SW5_SMU1_UNGATED_CLK_RST__MASK (0x100U)
+#define CIU1_CIU_RST_SW5_SMU1_UNGATED_CLK_RST__SHIFT (8U)
+/*! SMU1_UNGATED_CLK_RST_ - SW reset for the NIC of smu1 */
+#define CIU1_CIU_RST_SW5_SMU1_UNGATED_CLK_RST_(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_SMU1_UNGATED_CLK_RST__SHIFT)) & CIU1_CIU_RST_SW5_SMU1_UNGATED_CLK_RST__MASK)
+
+#define CIU1_CIU_RST_SW5_GPS_PPS_RST__MASK       (0x200U)
+#define CIU1_CIU_RST_SW5_GPS_PPS_RST__SHIFT      (9U)
+/*! GPS_PPS_RST_ - SW Reset for the gps pss */
+#define CIU1_CIU_RST_SW5_GPS_PPS_RST_(x)         (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_GPS_PPS_RST__SHIFT)) & CIU1_CIU_RST_SW5_GPS_PPS_RST__MASK)
+
+#define CIU1_CIU_RST_SW5_MCI_WL_A2A_MHRESETN_MASK (0x400U)
+#define CIU1_CIU_RST_SW5_MCI_WL_A2A_MHRESETN_SHIFT (10U)
+/*! MCI_WL_A2A_MHRESETN - SW Reset for mci_wl_a2a_mhresetn */
+#define CIU1_CIU_RST_SW5_MCI_WL_A2A_MHRESETN(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_MCI_WL_A2A_MHRESETN_SHIFT)) & CIU1_CIU_RST_SW5_MCI_WL_A2A_MHRESETN_MASK)
+
+#define CIU1_CIU_RST_SW5_PTP_RST__MASK           (0x800U)
+#define CIU1_CIU_RST_SW5_PTP_RST__SHIFT          (11U)
+/*! PTP_RST_ - SW reset for ptp input capture logic */
+#define CIU1_CIU_RST_SW5_PTP_RST_(x)             (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_SW5_PTP_RST__SHIFT)) & CIU1_CIU_RST_SW5_PTP_RST__MASK)
+/*! @} */
+
+/*! @name CIU_RST_ECO_CTRL - Reset ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_RST_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_RST_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - ECO Bits */
+#define CIU1_CIU_RST_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RST_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_RST_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_MEM_WRTC2 - Memory WRTC Control2 */
+/*! @{ */
+
+#define CIU1_CIU_MEM_WRTC2_SMU1_RTC_MASK         (0x3000U)
+#define CIU1_CIU_MEM_WRTC2_SMU1_RTC_SHIFT        (12U)
+/*! SMU1_RTC - SMU1 SEG1 RTC */
+#define CIU1_CIU_MEM_WRTC2_SMU1_RTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_SMU1_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_SMU1_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC2_SMU1_WTC_MASK         (0xC000U)
+#define CIU1_CIU_MEM_WRTC2_SMU1_WTC_SHIFT        (14U)
+/*! SMU1_WTC - SMU1 SEG1 WTC */
+#define CIU1_CIU_MEM_WRTC2_SMU1_WTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_SMU1_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_SMU1_WTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC2_R1P_RTC_MASK          (0x30000U)
+#define CIU1_CIU_MEM_WRTC2_R1P_RTC_SHIFT         (16U)
+/*! R1P_RTC - Small Single Port SRAM RTC */
+#define CIU1_CIU_MEM_WRTC2_R1P_RTC(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_R1P_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_R1P_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC2_R1P_WTC_MASK          (0xC0000U)
+#define CIU1_CIU_MEM_WRTC2_R1P_WTC_SHIFT         (18U)
+/*! R1P_WTC - Small Single Port SRAM WTC */
+#define CIU1_CIU_MEM_WRTC2_R1P_WTC(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_R1P_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_R1P_WTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC2_R2P_RTC_MASK          (0x300000U)
+#define CIU1_CIU_MEM_WRTC2_R2P_RTC_SHIFT         (20U)
+/*! R2P_RTC - Small Dual Port SRAM RTC */
+#define CIU1_CIU_MEM_WRTC2_R2P_RTC(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_R2P_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_R2P_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC2_R2P_WTC_MASK          (0xC00000U)
+#define CIU1_CIU_MEM_WRTC2_R2P_WTC_SHIFT         (22U)
+/*! R2P_WTC - Small Dual Port SRAM WTC */
+#define CIU1_CIU_MEM_WRTC2_R2P_WTC(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_R2P_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_R2P_WTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC2_SMU1_SEG0_RTC_MASK    (0xC000000U)
+#define CIU1_CIU_MEM_WRTC2_SMU1_SEG0_RTC_SHIFT   (26U)
+/*! SMU1_SEG0_RTC - SMU1 SEG0 RTC */
+#define CIU1_CIU_MEM_WRTC2_SMU1_SEG0_RTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_SMU1_SEG0_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_SMU1_SEG0_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC2_SMU1_SEG0_WTC_MASK    (0xC0000000U)
+#define CIU1_CIU_MEM_WRTC2_SMU1_SEG0_WTC_SHIFT   (30U)
+/*! SMU1_SEG0_WTC - SMU1 SEG0 WTC */
+#define CIU1_CIU_MEM_WRTC2_SMU1_SEG0_WTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC2_SMU1_SEG0_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC2_SMU1_SEG0_WTC_MASK)
+/*! @} */
+
+/*! @name CIU_MEM_WRTC3 - Memory WRTC Control 3 */
+/*! @{ */
+
+#define CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_MASK      (0x7U)
+#define CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_SHIFT     (0U)
+/*! WEU_ROM_RTC - WEU 256x15 ROM RTC */
+#define CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_REF_MASK  (0x30U)
+#define CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_REF_SHIFT (4U)
+/*! WEU_ROM_RTC_REF - WEU 256x16 ROM RTC_REF */
+#define CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_REF(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_REF_SHIFT)) & CIU1_CIU_MEM_WRTC3_WEU_ROM_RTC_REF_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_CPU1_ITCM_RTC_MASK    (0xC0U)
+#define CIU1_CIU_MEM_WRTC3_CPU1_ITCM_RTC_SHIFT   (6U)
+/*! CPU1_ITCM_RTC - CPU1 ITCM RTC */
+#define CIU1_CIU_MEM_WRTC3_CPU1_ITCM_RTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_CPU1_ITCM_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_CPU1_ITCM_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_CPU1_ITCM_WTC_MASK    (0x300U)
+#define CIU1_CIU_MEM_WRTC3_CPU1_ITCM_WTC_SHIFT   (8U)
+/*! CPU1_ITCM_WTC - CPU1 ITCM WTC */
+#define CIU1_CIU_MEM_WRTC3_CPU1_ITCM_WTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_CPU1_ITCM_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_CPU1_ITCM_WTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_CPU1_DTCM_RTC_MASK    (0xC00U)
+#define CIU1_CIU_MEM_WRTC3_CPU1_DTCM_RTC_SHIFT   (10U)
+/*! CPU1_DTCM_RTC - CPU1 DTCM RTC */
+#define CIU1_CIU_MEM_WRTC3_CPU1_DTCM_RTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_CPU1_DTCM_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_CPU1_DTCM_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_CPU1_DTCM_WTC_MASK    (0x3000U)
+#define CIU1_CIU_MEM_WRTC3_CPU1_DTCM_WTC_SHIFT   (12U)
+/*! CPU1_DTCM_WTC - CPU1 DTCM WTC */
+#define CIU1_CIU_MEM_WRTC3_CPU1_DTCM_WTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_CPU1_DTCM_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_CPU1_DTCM_WTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_MASK     (0x1C000U)
+#define CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_SHIFT    (14U)
+/*! CPU1_ROM_RTC - CPU1 ROM RTC */
+#define CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_REF_MASK (0x60000U)
+#define CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_REF_SHIFT (17U)
+/*! CPU1_ROM_RTC_REF - Cpu1 ROM RTC_REF */
+#define CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_REF(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_REF_SHIFT)) & CIU1_CIU_MEM_WRTC3_CPU1_ROM_RTC_REF_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_IPS_IRAM_RTC_MASK     (0x180000U)
+#define CIU1_CIU_MEM_WRTC3_IPS_IRAM_RTC_SHIFT    (19U)
+/*! IPS_IRAM_RTC - IPS IRAM RTC */
+#define CIU1_CIU_MEM_WRTC3_IPS_IRAM_RTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_IPS_IRAM_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_IPS_IRAM_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_IPS_IRAM_WTC_MASK     (0x600000U)
+#define CIU1_CIU_MEM_WRTC3_IPS_IRAM_WTC_SHIFT    (21U)
+/*! IPS_IRAM_WTC - IPS IRAM WTC */
+#define CIU1_CIU_MEM_WRTC3_IPS_IRAM_WTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_IPS_IRAM_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_IPS_IRAM_WTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_IPS_PRAM_RTC_MASK     (0x1800000U)
+#define CIU1_CIU_MEM_WRTC3_IPS_PRAM_RTC_SHIFT    (23U)
+/*! IPS_PRAM_RTC - IPS PRAM RTC */
+#define CIU1_CIU_MEM_WRTC3_IPS_PRAM_RTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_IPS_PRAM_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_IPS_PRAM_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_IPS_PRAM_WTC_MASK     (0x6000000U)
+#define CIU1_CIU_MEM_WRTC3_IPS_PRAM_WTC_SHIFT    (25U)
+/*! IPS_PRAM_WTC - IPS PRAM WTC */
+#define CIU1_CIU_MEM_WRTC3_IPS_PRAM_WTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_IPS_PRAM_WTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_IPS_PRAM_WTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_MASK     (0x38000000U)
+#define CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_SHIFT    (27U)
+/*! IPS_PROM_RTC - IPS PROM RTC */
+#define CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_SHIFT)) & CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_MASK)
+
+#define CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_REF_MASK (0xC0000000U)
+#define CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_REF_SHIFT (30U)
+/*! IPS_PROM_RTC_REF - IPS PROM RTC_REF */
+#define CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_REF(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_REF_SHIFT)) & CIU1_CIU_MEM_WRTC3_IPS_PROM_RTC_REF_MASK)
+/*! @} */
+
+/*! @name CIU_MEM_CTRL - Memory Control */
+/*! @{ */
+
+#define CIU1_CIU_MEM_CTRL_SMU1_DEBUG_ON_MASK     (0x20U)
+#define CIU1_CIU_MEM_CTRL_SMU1_DEBUG_ON_SHIFT    (5U)
+/*! SMU1_DEBUG_ON - 1= enable smu internal register latch for debug */
+#define CIU1_CIU_MEM_CTRL_SMU1_DEBUG_ON(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_CTRL_SMU1_DEBUG_ON_SHIFT)) & CIU1_CIU_MEM_CTRL_SMU1_DEBUG_ON_MASK)
+/*! @} */
+
+/*! @name CIU_SMU1_DBG_STAT0 - SMU1 debug register0 */
+/*! @{ */
+
+#define CIU1_CIU_SMU1_DBG_STAT0_SMU1_DBG_STAT0_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_SMU1_DBG_STAT0_SMU1_DBG_STAT0_SHIFT (0U)
+/*! SMU1_DBG_STAT0 - smu1 debug addr output */
+#define CIU1_CIU_SMU1_DBG_STAT0_SMU1_DBG_STAT0(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_SMU1_DBG_STAT0_SMU1_DBG_STAT0_SHIFT)) & CIU1_CIU_SMU1_DBG_STAT0_SMU1_DBG_STAT0_MASK)
+/*! @} */
+
+/*! @name CIU_SMU1_DBG_STAT1 - SMU1 debug register1 */
+/*! @{ */
+
+#define CIU1_CIU_SMU1_DBG_STAT1_SMU1_DBG_STAT1_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_SMU1_DBG_STAT1_SMU1_DBG_STAT1_SHIFT (0U)
+/*! SMU1_DBG_STAT1 - smu1 debug data output */
+#define CIU1_CIU_SMU1_DBG_STAT1_SMU1_DBG_STAT1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_SMU1_DBG_STAT1_SMU1_DBG_STAT1_SHIFT)) & CIU1_CIU_SMU1_DBG_STAT1_SMU1_DBG_STAT1_MASK)
+/*! @} */
+
+/*! @name CIU_SMU1_DBG_STAT2 - SMU1 debug register2 */
+/*! @{ */
+
+#define CIU1_CIU_SMU1_DBG_STAT2_SMU1_DBG_STAT2_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_SMU1_DBG_STAT2_SMU1_DBG_STAT2_SHIFT (0U)
+/*! SMU1_DBG_STAT2 - smu1 debug ctrl output */
+#define CIU1_CIU_SMU1_DBG_STAT2_SMU1_DBG_STAT2(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_SMU1_DBG_STAT2_SMU1_DBG_STAT2_SHIFT)) & CIU1_CIU_SMU1_DBG_STAT2_SMU1_DBG_STAT2_MASK)
+/*! @} */
+
+/*! @name CIU_MEM_ECO_CTRL - Memory ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_MEM_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_MEM_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_MEM_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MEM_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_MEM_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU1_INT_MASK - CIU1 Interrupt Mask */
+/*! @{ */
+
+#define CIU1_CIU1_INT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_MASK (0x2U)
+#define CIU1_CIU1_INT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_SHIFT (1U)
+/*! PTP_INPUTCAPTURE_EVENT_INTR - PTP Input Capture Event Interrupt for Time Synchronization. In
+ *    case of PTP mode input capture pulse from PAD or HMAC is used to latched PHC Value inside BBUD.
+ *    On receiving this interrupt SW will read the PHC timestamp Value from BBUD register
+ */
+#define CIU1_CIU1_INT_MASK_PTP_INPUTCAPTURE_EVENT_INTR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_SHIFT)) & CIU1_CIU1_INT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_MASK)
+
+#define CIU1_CIU1_INT_MASK_MCI_WL_WAKEUP_DONE_INT_MASK (0xCU)
+#define CIU1_CIU1_INT_MASK_MCI_WL_WAKEUP_DONE_INT_SHIFT (2U)
+/*! MCI_WL_WAKEUP_DONE_INT - Wake up Interrupt done, from MCI (CPU3) to WL (CPU1) */
+#define CIU1_CIU1_INT_MASK_MCI_WL_WAKEUP_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_MCI_WL_WAKEUP_DONE_INT_SHIFT)) & CIU1_CIU1_INT_MASK_MCI_WL_WAKEUP_DONE_INT_MASK)
+
+#define CIU1_CIU1_INT_MASK_CPU1_TO_CPU3_MSG_DONE_MASK (0x10U)
+#define CIU1_CIU1_INT_MASK_CPU1_TO_CPU3_MSG_DONE_SHIFT (4U)
+/*! CPU1_TO_CPU3_MSG_DONE - CPU1 to CPU3 Message Done Interrupt. After CPU3 completed message
+ *    processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU3_MSG_CTRL[8]
+ */
+#define CIU1_CIU1_INT_MASK_CPU1_TO_CPU3_MSG_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_CPU1_TO_CPU3_MSG_DONE_SHIFT)) & CIU1_CIU1_INT_MASK_CPU1_TO_CPU3_MSG_DONE_MASK)
+
+#define CIU1_CIU1_INT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_MASK (0x20U)
+#define CIU1_CIU1_INT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT (5U)
+/*! IMU13_CPU1_MSG_SPACE_AVAIL_IMU - CPU1 to CPU3 message FIFO space available for CPU1 to write more messages. (Not used) */
+#define CIU1_CIU1_INT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT)) & CIU1_CIU1_INT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_MASK)
+
+#define CIU1_CIU1_INT_MASK_CPU1_TO_CPU2_MSG_DONE_MASK (0x40U)
+#define CIU1_CIU1_INT_MASK_CPU1_TO_CPU2_MSG_DONE_SHIFT (6U)
+/*! CPU1_TO_CPU2_MSG_DONE - CPU1 to CPU2 Message Done Interrupt. After CPU2 completed message
+ *    processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU2_MSG_CTRL[8]
+ */
+#define CIU1_CIU1_INT_MASK_CPU1_TO_CPU2_MSG_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_CPU1_TO_CPU2_MSG_DONE_SHIFT)) & CIU1_CIU1_INT_MASK_CPU1_TO_CPU2_MSG_DONE_MASK)
+
+#define CIU1_CIU1_INT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_MASK (0x80U)
+#define CIU1_CIU1_INT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT (7U)
+/*! IMU12_CPU1_MSG_SPACE_AVAIL_IMU - CPU1 to CPU2 message FIFO space available for CPU1 to write more messages.(Not used) */
+#define CIU1_CIU1_INT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT)) & CIU1_CIU1_INT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_MASK)
+
+#define CIU1_CIU1_INT_MASK_RFU_INT_2G_MASK       (0x100U)
+#define CIU1_CIU1_INT_MASK_RFU_INT_2G_SHIFT      (8U)
+/*! RFU_INT_2G - RFU2G interrupt */
+#define CIU1_CIU1_INT_MASK_RFU_INT_2G(x)         (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_RFU_INT_2G_SHIFT)) & CIU1_CIU1_INT_MASK_RFU_INT_2G_MASK)
+
+#define CIU1_CIU1_INT_MASK_RFU_INT_5G_A_MASK     (0x200U)
+#define CIU1_CIU1_INT_MASK_RFU_INT_5G_A_SHIFT    (9U)
+/*! RFU_INT_5G_A - RFU5G channel A interrupt */
+#define CIU1_CIU1_INT_MASK_RFU_INT_5G_A(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_RFU_INT_5G_A_SHIFT)) & CIU1_CIU1_INT_MASK_RFU_INT_5G_A_MASK)
+
+#define CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_EARLY_MASK (0x400U)
+#define CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_EARLY_SHIFT (10U)
+/*! GPS_INTR_CH_SW_EARLY - GPS PPS timer early interrupt */
+#define CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_EARLY_SHIFT)) & CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_EARLY_MASK)
+
+#define CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_MASK   (0x800U)
+#define CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_SHIFT  (11U)
+/*! GPS_INTR_CH_SW - GPS PPS timer interrupt */
+#define CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_SHIFT)) & CIU1_CIU1_INT_MASK_GPS_INTR_CH_SW_MASK)
+
+#define CIU1_CIU1_INT_MASK_APU_INTR_BT_WAKEUP_MASK (0x1000U)
+#define CIU1_CIU1_INT_MASK_APU_INTR_BT_WAKEUP_SHIFT (12U)
+/*! APU_INTR_BT_WAKEUP - APU BT interrupt. This bit indicates that the BTU has encountered some
+ *    event during hardware sleep and would like the firmware to intervene. During BT wake time, this
+ *    interrupt path should not be taken. Refer to APU doc for more details on the sleep/wakeup
+ *    interrupt split.
+ */
+#define CIU1_CIU1_INT_MASK_APU_INTR_BT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_APU_INTR_BT_WAKEUP_SHIFT)) & CIU1_CIU1_INT_MASK_APU_INTR_BT_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_MASK_APU_INTR_WLAN_WAKEUP1_MASK (0x2000U)
+#define CIU1_CIU1_INT_MASK_APU_INTR_WLAN_WAKEUP1_SHIFT (13U)
+/*! APU_INTR_WLAN_WAKEUP1 - APU WLAN1 interrupt. This bit indicates that the WLAN hardware needs to
+ *    wakeup for an incoming beacon. During WLAN wake time, this interrupt path should not be taken.
+ *    Refer to APU doc for more details on the sleep/wakeup interrupt split.
+ */
+#define CIU1_CIU1_INT_MASK_APU_INTR_WLAN_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_APU_INTR_WLAN_WAKEUP1_SHIFT)) & CIU1_CIU1_INT_MASK_APU_INTR_WLAN_WAKEUP1_MASK)
+
+#define CIU1_CIU1_INT_MASK_APU_INTR_GEN_TIMER_WAKEUP_MASK (0x4000U)
+#define CIU1_CIU1_INT_MASK_APU_INTR_GEN_TIMER_WAKEUP_SHIFT (14U)
+/*! APU_INTR_GEN_TIMER_WAKEUP - APU beacon Timer wakeup interrupt */
+#define CIU1_CIU1_INT_MASK_APU_INTR_GEN_TIMER_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_APU_INTR_GEN_TIMER_WAKEUP_SHIFT)) & CIU1_CIU1_INT_MASK_APU_INTR_GEN_TIMER_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_MASK_APU_INTR_WAKEUP_MASK  (0x8000U)
+#define CIU1_CIU1_INT_MASK_APU_INTR_WAKEUP_SHIFT (15U)
+/*! APU_INTR_WAKEUP - APU default interrupt. The purpose of this interrupt is to catch any erroneous
+ *    host wakeup case. In the event of an erroneous host wakeup, it is possible that the host
+ *    wakeup interrupt will not assert. In order to ensure that the APU does not get stuck in some
+ *    unknown state, this dummy interrupt will be thrown in it's place. Firmware should only care about
+ *    this bit if no other interrupts are set in this register.
+ */
+#define CIU1_CIU1_INT_MASK_APU_INTR_WAKEUP(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_APU_INTR_WAKEUP_SHIFT)) & CIU1_CIU1_INT_MASK_APU_INTR_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_MASK_APU_INTR_HOST_WAKEUP_MASK (0xFFFF0000U)
+#define CIU1_CIU1_INT_MASK_APU_INTR_HOST_WAKEUP_SHIFT (16U)
+/*! APU_INTR_HOST_WAKEUP - APU Host wakeup interrupt */
+#define CIU1_CIU1_INT_MASK_APU_INTR_HOST_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_MASK_APU_INTR_HOST_WAKEUP_SHIFT)) & CIU1_CIU1_INT_MASK_APU_INTR_HOST_WAKEUP_MASK)
+/*! @} */
+
+/*! @name CIU1_INT_SELECT - CIU1 Interrupt Select */
+/*! @{ */
+
+#define CIU1_CIU1_INT_SELECT_SEL_MASK            (0xFFFFFFFFU)
+#define CIU1_CIU1_INT_SELECT_SEL_SHIFT           (0U)
+/*! SEL - Interrupt Read/Write Clear for CIU1 Interrupts */
+#define CIU1_CIU1_INT_SELECT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_SELECT_SEL_SHIFT)) & CIU1_CIU1_INT_SELECT_SEL_MASK)
+/*! @} */
+
+/*! @name CIU1_INT_EVENT_MASK - CIU1 Interrupt Event Mask */
+/*! @{ */
+
+#define CIU1_CIU1_INT_EVENT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_MASK (0x2U)
+#define CIU1_CIU1_INT_EVENT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_SHIFT (1U)
+/*! PTP_INPUTCAPTURE_EVENT_INTR - PTP Input Capture Event Interrupt for Time Synchronization. In
+ *    case of PTP mode input capture pulse from PAD or HMAC is used to latched PHC Value inside BBUD.
+ *    On receiving this interrupt SW will read the PHC timestamp Value from BBUD register
+ */
+#define CIU1_CIU1_INT_EVENT_MASK_PTP_INPUTCAPTURE_EVENT_INTR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_PTP_INPUTCAPTURE_EVENT_INTR_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_MCI_WL_WAKEUP_DONE_INT_MASK (0xCU)
+#define CIU1_CIU1_INT_EVENT_MASK_MCI_WL_WAKEUP_DONE_INT_SHIFT (2U)
+/*! MCI_WL_WAKEUP_DONE_INT - Wake up Interrupt done, from MCI (CPU3) to WL (CPU1) */
+#define CIU1_CIU1_INT_EVENT_MASK_MCI_WL_WAKEUP_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_MCI_WL_WAKEUP_DONE_INT_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_MCI_WL_WAKEUP_DONE_INT_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU3_MSG_DONE_MASK (0x10U)
+#define CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU3_MSG_DONE_SHIFT (4U)
+/*! CPU1_TO_CPU3_MSG_DONE - CPU1 to CPU3 Message Done Interrupt. After CPU3 completed message
+ *    processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU3_MSG_CTRL[8]
+ */
+#define CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU3_MSG_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU3_MSG_DONE_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU3_MSG_DONE_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_MASK (0x20U)
+#define CIU1_CIU1_INT_EVENT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT (5U)
+/*! IMU13_CPU1_MSG_SPACE_AVAIL_IMU - CPU1 to CPU3 message FIFO space available for CPU1 to write more messages. (Not used) */
+#define CIU1_CIU1_INT_EVENT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU2_MSG_DONE_MASK (0x40U)
+#define CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU2_MSG_DONE_SHIFT (6U)
+/*! CPU1_TO_CPU2_MSG_DONE - CPU1 to CPU2 Message Done Interrupt. After CPU2 completed message
+ *    processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU2_MSG_CTRL[8]
+ */
+#define CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU2_MSG_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU2_MSG_DONE_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_CPU1_TO_CPU2_MSG_DONE_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_MASK (0x80U)
+#define CIU1_CIU1_INT_EVENT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT (7U)
+/*! IMU12_CPU1_MSG_SPACE_AVAIL_IMU - CPU1 to CPU2 message FIFO space available for CPU1 to write more messages.(Not used) */
+#define CIU1_CIU1_INT_EVENT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_RFU_INT_2G_MASK (0x100U)
+#define CIU1_CIU1_INT_EVENT_MASK_RFU_INT_2G_SHIFT (8U)
+/*! RFU_INT_2G - RFU2G interrupt */
+#define CIU1_CIU1_INT_EVENT_MASK_RFU_INT_2G(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_RFU_INT_2G_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_RFU_INT_2G_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_RFU_INT_5G_A_MASK (0x200U)
+#define CIU1_CIU1_INT_EVENT_MASK_RFU_INT_5G_A_SHIFT (9U)
+/*! RFU_INT_5G_A - RFU5G channel A interrupt */
+#define CIU1_CIU1_INT_EVENT_MASK_RFU_INT_5G_A(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_RFU_INT_5G_A_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_RFU_INT_5G_A_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_EARLY_MASK (0x400U)
+#define CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_EARLY_SHIFT (10U)
+/*! GPS_INTR_CH_SW_EARLY - GPS PPS timer early interrupt */
+#define CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_EARLY_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_EARLY_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_MASK (0x800U)
+#define CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_SHIFT (11U)
+/*! GPS_INTR_CH_SW - GPS PPS timer interrupt */
+#define CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_GPS_INTR_CH_SW_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_BT_WAKEUP_MASK (0x1000U)
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_BT_WAKEUP_SHIFT (12U)
+/*! APU_INTR_BT_WAKEUP - APU BT interrupt. This bit indicates that the BTU has encountered some
+ *    event during hardware sleep and would like the firmware to intervene. During BT wake time, this
+ *    interrupt path should not be taken. Refer to APU doc for more details on the sleep/wakeup
+ *    interrupt split.
+ */
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_BT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_APU_INTR_BT_WAKEUP_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_APU_INTR_BT_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WLAN_WAKEUP1_MASK (0x2000U)
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WLAN_WAKEUP1_SHIFT (13U)
+/*! APU_INTR_WLAN_WAKEUP1 - APU WLAN1 interrupt. This bit indicates that the WLAN hardware needs to
+ *    wakeup for an incoming beacon. During WLAN wake time, this interrupt path should not be taken.
+ *    Refer to APU doc for more details on the sleep/wakeup interrupt split.
+ */
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WLAN_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WLAN_WAKEUP1_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WLAN_WAKEUP1_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_GEN_TIMER_WAKEUP_MASK (0x4000U)
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_GEN_TIMER_WAKEUP_SHIFT (14U)
+/*! APU_INTR_GEN_TIMER_WAKEUP - APU beacon Timer wakeup interrupt */
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_GEN_TIMER_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_APU_INTR_GEN_TIMER_WAKEUP_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_APU_INTR_GEN_TIMER_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WAKEUP_MASK (0x8000U)
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WAKEUP_SHIFT (15U)
+/*! APU_INTR_WAKEUP - APU default interrupt. The purpose of this interrupt is to catch any erroneous
+ *    host wakeup case. In the event of an erroneous host wakeup, it is possible that the host
+ *    wakeup interrupt will not assert. In order to ensure that the APU does not get stuck in some
+ *    unknown state, this dummy interrupt will be thrown in it's place. Firmware should only care about
+ *    this bit if no other interrupts are set in this register.
+ */
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WAKEUP_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_APU_INTR_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_HOST_WAKEUP_MASK (0xFFFF0000U)
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_HOST_WAKEUP_SHIFT (16U)
+/*! APU_INTR_HOST_WAKEUP - APU Host wakeup interrupt */
+#define CIU1_CIU1_INT_EVENT_MASK_APU_INTR_HOST_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_EVENT_MASK_APU_INTR_HOST_WAKEUP_SHIFT)) & CIU1_CIU1_INT_EVENT_MASK_APU_INTR_HOST_WAKEUP_MASK)
+/*! @} */
+
+/*! @name CIU1_INT_STATUS - CIU1 Interrupt Status */
+/*! @{ */
+
+#define CIU1_CIU1_INT_STATUS_PTP_INPUTCAPTURE_EVENT_INTR_MASK (0x2U)
+#define CIU1_CIU1_INT_STATUS_PTP_INPUTCAPTURE_EVENT_INTR_SHIFT (1U)
+/*! PTP_INPUTCAPTURE_EVENT_INTR - PTP Input Capture Event Interrupt for Time Synchronization. In
+ *    case of PTP mode input capture pulse from PAD or HMAC is used to latched PHC Value inside BBUD.
+ *    On receiving this interrupt SW will read the PHC timestamp Value from BBUD register
+ */
+#define CIU1_CIU1_INT_STATUS_PTP_INPUTCAPTURE_EVENT_INTR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_PTP_INPUTCAPTURE_EVENT_INTR_SHIFT)) & CIU1_CIU1_INT_STATUS_PTP_INPUTCAPTURE_EVENT_INTR_MASK)
+
+#define CIU1_CIU1_INT_STATUS_MCI_WL_WAKEUP_DONE_INT_MASK (0xCU)
+#define CIU1_CIU1_INT_STATUS_MCI_WL_WAKEUP_DONE_INT_SHIFT (2U)
+/*! MCI_WL_WAKEUP_DONE_INT - Wake up Interrupt done, from MCI (CPU3) to WL (CPU1) */
+#define CIU1_CIU1_INT_STATUS_MCI_WL_WAKEUP_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_MCI_WL_WAKEUP_DONE_INT_SHIFT)) & CIU1_CIU1_INT_STATUS_MCI_WL_WAKEUP_DONE_INT_MASK)
+
+#define CIU1_CIU1_INT_STATUS_CPU1_TO_CPU3_MSG_DONE_MASK (0x10U)
+#define CIU1_CIU1_INT_STATUS_CPU1_TO_CPU3_MSG_DONE_SHIFT (4U)
+/*! CPU1_TO_CPU3_MSG_DONE - CPU1 to CPU3 Message Done Interrupt. After CPU3 completed message
+ *    processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU3_MSG_CTRL[8]
+ */
+#define CIU1_CIU1_INT_STATUS_CPU1_TO_CPU3_MSG_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_CPU1_TO_CPU3_MSG_DONE_SHIFT)) & CIU1_CIU1_INT_STATUS_CPU1_TO_CPU3_MSG_DONE_MASK)
+
+#define CIU1_CIU1_INT_STATUS_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_MASK (0x20U)
+#define CIU1_CIU1_INT_STATUS_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT (5U)
+/*! IMU13_CPU1_MSG_SPACE_AVAIL_IMU - CPU1 to CPU3 message FIFO space available for CPU1 to write more messages. (Not used) */
+#define CIU1_CIU1_INT_STATUS_IMU13_CPU1_MSG_SPACE_AVAIL_IMU(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT)) & CIU1_CIU1_INT_STATUS_IMU13_CPU1_MSG_SPACE_AVAIL_IMU_MASK)
+
+#define CIU1_CIU1_INT_STATUS_CPU1_TO_CPU2_MSG_DONE_MASK (0x40U)
+#define CIU1_CIU1_INT_STATUS_CPU1_TO_CPU2_MSG_DONE_SHIFT (6U)
+/*! CPU1_TO_CPU2_MSG_DONE - CPU1 to CPU2 Message Done Interrupt. After CPU2 completed message
+ *    processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU2_MSG_CTRL[8]
+ */
+#define CIU1_CIU1_INT_STATUS_CPU1_TO_CPU2_MSG_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_CPU1_TO_CPU2_MSG_DONE_SHIFT)) & CIU1_CIU1_INT_STATUS_CPU1_TO_CPU2_MSG_DONE_MASK)
+
+#define CIU1_CIU1_INT_STATUS_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_MASK (0x80U)
+#define CIU1_CIU1_INT_STATUS_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT (7U)
+/*! IMU12_CPU1_MSG_SPACE_AVAIL_IMU - CPU1 to CPU2 message FIFO space available for CPU1 to write more messages.(Not used) */
+#define CIU1_CIU1_INT_STATUS_IMU12_CPU1_MSG_SPACE_AVAIL_IMU(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_SHIFT)) & CIU1_CIU1_INT_STATUS_IMU12_CPU1_MSG_SPACE_AVAIL_IMU_MASK)
+
+#define CIU1_CIU1_INT_STATUS_RFU_INT_2G_MASK     (0x100U)
+#define CIU1_CIU1_INT_STATUS_RFU_INT_2G_SHIFT    (8U)
+/*! RFU_INT_2G - RFU2G interrupt */
+#define CIU1_CIU1_INT_STATUS_RFU_INT_2G(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_RFU_INT_2G_SHIFT)) & CIU1_CIU1_INT_STATUS_RFU_INT_2G_MASK)
+
+#define CIU1_CIU1_INT_STATUS_RFU_INT_5G_A_MASK   (0x200U)
+#define CIU1_CIU1_INT_STATUS_RFU_INT_5G_A_SHIFT  (9U)
+/*! RFU_INT_5G_A - RFU5G channel A interrupt */
+#define CIU1_CIU1_INT_STATUS_RFU_INT_5G_A(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_RFU_INT_5G_A_SHIFT)) & CIU1_CIU1_INT_STATUS_RFU_INT_5G_A_MASK)
+
+#define CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_EARLY_MASK (0x400U)
+#define CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_EARLY_SHIFT (10U)
+/*! GPS_INTR_CH_SW_EARLY - GPS PPS timer early interrupt */
+#define CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_EARLY_SHIFT)) & CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_EARLY_MASK)
+
+#define CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_MASK (0x800U)
+#define CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_SHIFT (11U)
+/*! GPS_INTR_CH_SW - GPS PPS timer interrupt */
+#define CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_SHIFT)) & CIU1_CIU1_INT_STATUS_GPS_INTR_CH_SW_MASK)
+
+#define CIU1_CIU1_INT_STATUS_APU_INTR_BT_WAKEUP_MASK (0x1000U)
+#define CIU1_CIU1_INT_STATUS_APU_INTR_BT_WAKEUP_SHIFT (12U)
+/*! APU_INTR_BT_WAKEUP - APU BT interrupt. This bit indicates that the BTU has encountered some
+ *    event during hardware sleep and would like the firmware to intervene. During BT wake time, this
+ *    interrupt path should not be taken. Refer to APU doc for more details on the sleep/wakeup
+ *    interrupt split.
+ */
+#define CIU1_CIU1_INT_STATUS_APU_INTR_BT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_APU_INTR_BT_WAKEUP_SHIFT)) & CIU1_CIU1_INT_STATUS_APU_INTR_BT_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_STATUS_APU_INTR_WLAN_WAKEUP1_MASK (0x2000U)
+#define CIU1_CIU1_INT_STATUS_APU_INTR_WLAN_WAKEUP1_SHIFT (13U)
+/*! APU_INTR_WLAN_WAKEUP1 - APU WLAN1 interrupt. This bit indicates that the WLAN hardware needs to
+ *    wakeup for an incoming beacon. During WLAN wake time, this interrupt path should not be taken.
+ *    Refer to APU doc for more details on the sleep/wakeup interrupt split.
+ */
+#define CIU1_CIU1_INT_STATUS_APU_INTR_WLAN_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_APU_INTR_WLAN_WAKEUP1_SHIFT)) & CIU1_CIU1_INT_STATUS_APU_INTR_WLAN_WAKEUP1_MASK)
+
+#define CIU1_CIU1_INT_STATUS_APU_INTR_GEN_TIMER_WAKEUP_MASK (0x4000U)
+#define CIU1_CIU1_INT_STATUS_APU_INTR_GEN_TIMER_WAKEUP_SHIFT (14U)
+/*! APU_INTR_GEN_TIMER_WAKEUP - APU beacon Timer wakeup interrupt */
+#define CIU1_CIU1_INT_STATUS_APU_INTR_GEN_TIMER_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_APU_INTR_GEN_TIMER_WAKEUP_SHIFT)) & CIU1_CIU1_INT_STATUS_APU_INTR_GEN_TIMER_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_STATUS_APU_INTR_WAKEUP_MASK (0x8000U)
+#define CIU1_CIU1_INT_STATUS_APU_INTR_WAKEUP_SHIFT (15U)
+/*! APU_INTR_WAKEUP - APU default interrupt. The purpose of this interrupt is to catch any erroneous
+ *    host wakeup case. In the event of an erroneous host wakeup, it is possible that the host
+ *    wakeup interrupt will not assert. In order to ensure that the APU does not get stuck in some
+ *    unknown state, this dummy interrupt will be thrown in it's place. Firmware should only care about
+ *    this bit if no other interrupts are set in this register.
+ */
+#define CIU1_CIU1_INT_STATUS_APU_INTR_WAKEUP(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_APU_INTR_WAKEUP_SHIFT)) & CIU1_CIU1_INT_STATUS_APU_INTR_WAKEUP_MASK)
+
+#define CIU1_CIU1_INT_STATUS_APU_INTR_HOST_WAKEUP_MASK (0xFFFF0000U)
+#define CIU1_CIU1_INT_STATUS_APU_INTR_HOST_WAKEUP_SHIFT (16U)
+/*! APU_INTR_HOST_WAKEUP - APU Host wakeup interrupt */
+#define CIU1_CIU1_INT_STATUS_APU_INTR_HOST_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_INT_STATUS_APU_INTR_HOST_WAKEUP_SHIFT)) & CIU1_CIU1_INT_STATUS_APU_INTR_HOST_WAKEUP_MASK)
+/*! @} */
+
+/*! @name CIU_INT_HOST_CTRL - Host Interrupt Control */
+/*! @{ */
+
+#define CIU1_CIU_INT_HOST_CTRL_UART_RX_IDLE_STATE_DETECT_MODE_MASK (0x1U)
+#define CIU1_CIU_INT_HOST_CTRL_UART_RX_IDLE_STATE_DETECT_MODE_SHIFT (0U)
+/*! UART_RX_IDLE_STATE_DETECT_MODE - UART Rx IDLE State Detection Mode. */
+#define CIU1_CIU_INT_HOST_CTRL_UART_RX_IDLE_STATE_DETECT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_INT_HOST_CTRL_UART_RX_IDLE_STATE_DETECT_MODE_SHIFT)) & CIU1_CIU_INT_HOST_CTRL_UART_RX_IDLE_STATE_DETECT_MODE_MASK)
+/*! @} */
+
+/*! @name CIU_BCA1_INT_MASK - BCA1 to CPU1 Interrupt Mask */
+/*! @{ */
+
+#define CIU1_CIU_BCA1_INT_MASK_IMR_MASK          (0xFFFFFFFFU)
+#define CIU1_CIU_BCA1_INT_MASK_IMR_SHIFT         (0U)
+/*! IMR - Interrupt Mask for BCA1 to CPU1 Interrupts */
+#define CIU1_CIU_BCA1_INT_MASK_IMR(x)            (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA1_INT_MASK_IMR_SHIFT)) & CIU1_CIU_BCA1_INT_MASK_IMR_MASK)
+/*! @} */
+
+/*! @name CIU_BCA1_INT_SELECT - BCA1 to CPU1 Interrupt Select */
+/*! @{ */
+
+#define CIU1_CIU_BCA1_INT_SELECT_RSR_MASK        (0xFFFFFFFFU)
+#define CIU1_CIU_BCA1_INT_SELECT_RSR_SHIFT       (0U)
+/*! RSR - Interrupt Read/Write Clear for BCA1 to CPU1 Interrupts */
+#define CIU1_CIU_BCA1_INT_SELECT_RSR(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA1_INT_SELECT_RSR_SHIFT)) & CIU1_CIU_BCA1_INT_SELECT_RSR_MASK)
+/*! @} */
+
+/*! @name CIU_BCA1_INT_EVENT_MASK - BCA1 to CPU1 Interrupt Event Mask */
+/*! @{ */
+
+#define CIU1_CIU_BCA1_INT_EVENT_MASK_SMR_MASK    (0xFFFFFFFFU)
+#define CIU1_CIU_BCA1_INT_EVENT_MASK_SMR_SHIFT   (0U)
+/*! SMR - Interrupt Event Mask for BCA1 to CPU1 Interrupts */
+#define CIU1_CIU_BCA1_INT_EVENT_MASK_SMR(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA1_INT_EVENT_MASK_SMR_SHIFT)) & CIU1_CIU_BCA1_INT_EVENT_MASK_SMR_MASK)
+/*! @} */
+
+/*! @name CIU_BCA1_INT_STATUS - BCA1 to CPU1 Interrupt Status */
+/*! @{ */
+
+#define CIU1_CIU_BCA1_INT_STATUS_ISR_MASK        (0xFFFFFFFFU)
+#define CIU1_CIU_BCA1_INT_STATUS_ISR_SHIFT       (0U)
+/*! ISR - BCA1 to CPU1 Interrupt Status */
+#define CIU1_CIU_BCA1_INT_STATUS_ISR(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA1_INT_STATUS_ISR_SHIFT)) & CIU1_CIU_BCA1_INT_STATUS_ISR_MASK)
+/*! @} */
+
+/*! @name CPU1_ERR_INT_MASK - CPU1 ERR Interrupt Mask */
+/*! @{ */
+
+#define CIU1_CPU1_ERR_INT_MASK_MASK_MASK         (0xFFFFFFFFU)
+#define CIU1_CPU1_ERR_INT_MASK_MASK_SHIFT        (0U)
+/*! MASK - Interrupt Mask for CPU1 ERR Interrupts */
+#define CIU1_CPU1_ERR_INT_MASK_MASK(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_CPU1_ERR_INT_MASK_MASK_SHIFT)) & CIU1_CPU1_ERR_INT_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name CPU1_ERR_INT_SELECT - CPU1 ERR Interrupt Clear Select */
+/*! @{ */
+
+#define CIU1_CPU1_ERR_INT_SELECT_SEL_MASK        (0xFFFFFFFFU)
+#define CIU1_CPU1_ERR_INT_SELECT_SEL_SHIFT       (0U)
+/*! SEL - Interrupt Read/Write Clear for CPU1 ERR Interrupts */
+#define CIU1_CPU1_ERR_INT_SELECT_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CPU1_ERR_INT_SELECT_SEL_SHIFT)) & CIU1_CPU1_ERR_INT_SELECT_SEL_MASK)
+/*! @} */
+
+/*! @name CPU1_ERR_INT_EVENT_MASK - CPU1 ERR Interrupt Event Mask */
+/*! @{ */
+
+#define CIU1_CPU1_ERR_INT_EVENT_MASK_MASK_MASK   (0xFFFFFFFFU)
+#define CIU1_CPU1_ERR_INT_EVENT_MASK_MASK_SHIFT  (0U)
+/*! MASK - Interrupt Event Mask for CPU1 ERR Interrupts */
+#define CIU1_CPU1_ERR_INT_EVENT_MASK_MASK(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CPU1_ERR_INT_EVENT_MASK_MASK_SHIFT)) & CIU1_CPU1_ERR_INT_EVENT_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name CPU1_ERR_INT_STATUS - CPU1 ERR Interrupt Status */
+/*! @{ */
+
+#define CIU1_CPU1_ERR_INT_STATUS_ERR_ISR_MASK    (0xFFFFFFFFU)
+#define CIU1_CPU1_ERR_INT_STATUS_ERR_ISR_SHIFT   (0U)
+/*! ERR_ISR - CPU1 ERR Interrupt Status (ISR) */
+#define CIU1_CPU1_ERR_INT_STATUS_ERR_ISR(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CPU1_ERR_INT_STATUS_ERR_ISR_SHIFT)) & CIU1_CPU1_ERR_INT_STATUS_ERR_ISR_MASK)
+/*! @} */
+
+/*! @name CPU2_INT_CTRL - CPU2 INT control */
+/*! @{ */
+
+#define CIU1_CPU2_INT_CTRL_CPU2_SW_INT_MASK      (0x1U)
+#define CIU1_CPU2_INT_CTRL_CPU2_SW_INT_SHIFT     (0U)
+/*! CPU2_SW_INT - SW programmed interrupt register for cpu2. write 1 to generate interrupt to CPU2. */
+#define CIU1_CPU2_INT_CTRL_CPU2_SW_INT(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CPU2_INT_CTRL_CPU2_SW_INT_SHIFT)) & CIU1_CPU2_INT_CTRL_CPU2_SW_INT_MASK)
+/*! @} */
+
+/*! @name CPU3_INT_CTRL - CPU3 INT control */
+/*! @{ */
+
+#define CIU1_CPU3_INT_CTRL_CPU1_CPU3_GP_INT_MASK (0xFU)
+#define CIU1_CPU3_INT_CTRL_CPU1_CPU3_GP_INT_SHIFT (0U)
+/*! CPU1_CPU3_GP_INT - SW programmed interrupt register for cpu3. write 1 to generate interrupt to CPU3. */
+#define CIU1_CPU3_INT_CTRL_CPU1_CPU3_GP_INT(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CPU3_INT_CTRL_CPU1_CPU3_GP_INT_SHIFT)) & CIU1_CPU3_INT_CTRL_CPU1_CPU3_GP_INT_MASK)
+/*! @} */
+
+/*! @name CIU_INT_ECO_CTRL - Interrupt ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_INT_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_INT_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_INT_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_INT_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_INT_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_PTP_CTRL - Vsensor and Vreg Pad Control */
+/*! @{ */
+
+#define CIU1_CIU_PTP_CTRL_MODE_EN_MASK           (0xFFU)
+#define CIU1_CIU_PTP_CTRL_MODE_EN_SHIFT          (0U)
+/*! MODE_EN - PTP mode enable in iomux (bitwise) */
+#define CIU1_CIU_PTP_CTRL_MODE_EN(x)             (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_PTP_CTRL_MODE_EN_SHIFT)) & CIU1_CIU_PTP_CTRL_MODE_EN_MASK)
+/*! @} */
+
+/*! @name CIU_RFU_DBC_MUX_SEL - RFU related DBC mux selection for different mode */
+/*! @{ */
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX17_SEL_MASK (0x2U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX17_SEL_SHIFT (1U)
+/*! RFU5G_A_MUX17_SEL - RFU 5G path A input selection from two bca */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX17_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX17_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX18_SEL_MASK (0x4U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX18_SEL_SHIFT (2U)
+/*! RFU5G_B_MUX18_SEL - RFU 5G path B input selection from two bca */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX18_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX18_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX18_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX1_SEL_MASK (0x8U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX1_SEL_SHIFT (3U)
+/*! RFU5G_A_MUX1_SEL - RFU 5G path A input selection from two bbud */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX1_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX1_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX2_SEL_MASK (0x10U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX2_SEL_SHIFT (4U)
+/*! RFU5G_B_MUX2_SEL - RFU 5G path B input selection from two bbud */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX2_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX2_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX3_SEL_MASK (0x20U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX3_SEL_SHIFT (5U)
+/*! RFU2G_A_MUX3_SEL - RFU 2G path A input selection from two bbud */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX3_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX3_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX4_SEL_MASK (0x40U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX4_SEL_SHIFT (6U)
+/*! RFU2G_B_MUX4_SEL - RFU 2G path B input selection from two bbud */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX4_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX4_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX4_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_A_MUX5_SEL_MASK (0x80U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_A_MUX5_SEL_SHIFT (7U)
+/*! BBUD1_A_MUX5_SEL - bbud1 path A input selection from two RFU */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_A_MUX5_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_A_MUX5_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_A_MUX5_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_B_MUX6_SEL_MASK (0x100U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_B_MUX6_SEL_SHIFT (8U)
+/*! BBUD1_B_MUX6_SEL - bbud1 path B input selection from two RFU */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_B_MUX6_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_B_MUX6_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_B_MUX6_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_B_MUX7_SEL_MASK (0x200U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_B_MUX7_SEL_SHIFT (9U)
+/*! BBUD2_B_MUX7_SEL - bbud2 path B input selection from two RFU */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_B_MUX7_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_B_MUX7_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_B_MUX7_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_A_MUX8_SEL_MASK (0x400U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_A_MUX8_SEL_SHIFT (10U)
+/*! BBUD2_A_MUX8_SEL - bbud2 path A input selection from two RFU */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_A_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_A_MUX8_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_A_MUX8_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_0_MASK (0x1800U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_0_SHIFT (11U)
+/*! RFU5G_A_MUX13_SEL_0 - RFU 5G path A PE1/PE2/PAPE input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_0_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_0_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_0_MASK (0x6000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_0_SHIFT (13U)
+/*! RFU5G_B_MUX14_SEL_0 - RFU 5G path B PE1/PE2/PAPE input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_0_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_0_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_0_MASK (0x18000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_0_SHIFT (15U)
+/*! RFU2G_A_MUX15_SEL_0 - RFU 2G path A PE1/PE2/PAPE input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_0_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_0_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_0_MASK (0x60000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_0_SHIFT (17U)
+/*! RFU2G_B_MUX16_SEL_0 - RFU 2G path B PE1/PE2/PAPE input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_0_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_0_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_1_MASK (0x80000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_1_SHIFT (19U)
+/*! RFU5G_A_MUX13_SEL_1 - RFU 5G path A other input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_1_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_A_MUX13_SEL_1_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_1_MASK (0x100000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_1_SHIFT (20U)
+/*! RFU5G_B_MUX14_SEL_1 - RFU 5G path B other input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_1_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU5G_B_MUX14_SEL_1_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_1_MASK (0x200000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_1_SHIFT (21U)
+/*! RFU2G_A_MUX15_SEL_1 - RFU 2G path A other input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_1_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_A_MUX15_SEL_1_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_1_MASK (0x400000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_1_SHIFT (22U)
+/*! RFU2G_B_MUX16_SEL_1 - RFU 2G path B other input selection from two mac */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_1_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_RFU2G_B_MUX16_SEL_1_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_A_SEL_MASK (0x1800000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_A_SEL_SHIFT (23U)
+/*! BBUD1_TRX_RDY_A_SEL - bbud1_RFU_RDY_A and bbud1_RFU_INC_CAL_A selection */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_A_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_A_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_A_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_TRX_RDY_SEL_MASK (0x6000000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_TRX_RDY_SEL_SHIFT (25U)
+/*! BBUD2_TRX_RDY_SEL - bbud2_RFU_RDY and bbud2_RFU_INC_CAL selection */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_TRX_RDY_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_TRX_RDY_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BBUD2_TRX_RDY_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_B_SEL_MASK (0x18000000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_B_SEL_SHIFT (27U)
+/*! BBUD1_TRX_RDY_B_SEL - bbud1_RFU_RDY_E and bbud1_RFU_INC_CAL_E selection */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_B_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_B_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BBUD1_TRX_RDY_B_SEL_MASK)
+
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BRF_TXPWR_SEL_MASK (0x80000000U)
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BRF_TXPWR_SEL_SHIFT (31U)
+/*! BRF_TXPWR_SEL - SOC_BRF_PE1/2_2G and SOC_BRF_TXPWR_2G selection */
+#define CIU1_CIU_RFU_DBC_MUX_SEL_BRF_TXPWR_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_DBC_MUX_SEL_BRF_TXPWR_SEL_SHIFT)) & CIU1_CIU_RFU_DBC_MUX_SEL_BRF_TXPWR_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_BCA_DBC_MUX_SEL - BCA related DBC mux selection for different mode */
+/*! @{ */
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX11_SEL_MASK (0x1U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX11_SEL_SHIFT (0U)
+/*! BCA1_MUX11_SEL - bca1 input selection from two mcu */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX11_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX11_SEL_MASK)
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX12_SEL_MASK (0x2U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX12_SEL_SHIFT (1U)
+/*! BCA2_MUX12_SEL - bca2 input selection from two mcu */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX12_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX12_SEL_MASK)
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_MCU1_MUX9_SEL_MASK (0x4U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_MCU1_MUX9_SEL_SHIFT (2U)
+/*! MCU1_MUX9_SEL - mcu1 input selection from two bca */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_MCU1_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_MCU1_MUX9_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_MCU1_MUX9_SEL_MASK)
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_MCU2_MUX10_SEL_MASK (0x8U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_MCU2_MUX10_SEL_SHIFT (3U)
+/*! MCU2_MUX10_SEL - mcu2 input selection from two bca */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_MCU2_MUX10_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_MCU2_MUX10_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_MCU2_MUX10_SEL_MASK)
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX19_SEL_MASK (0x30U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX19_SEL_SHIFT (4U)
+/*! BCA1_MUX19_SEL - bca1 ros cal input selection from two RFU */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX19_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX19_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_MUX19_SEL_MASK)
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX20_SEL_MASK (0xC0U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX20_SEL_SHIFT (6U)
+/*! BCA2_MUX20_SEL - bca2 ros cal input selection from two RFU */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX20_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX20_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_MUX20_SEL_MASK)
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_EPA_BYPASS_SEL_MASK (0x100U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_EPA_BYPASS_SEL_SHIFT (8U)
+/*! BCA1_EPA_BYPASS_SEL - bca1 epa_bypass signal selction from two RFU */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_EPA_BYPASS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_EPA_BYPASS_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_BCA1_EPA_BYPASS_SEL_MASK)
+
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_EPA_BYPASS_SEL_MASK (0x200U)
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_EPA_BYPASS_SEL_SHIFT (9U)
+/*! BCA2_EPA_BYPASS_SEL - bca2 epa_bypass signal selction from two RFU */
+#define CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_EPA_BYPASS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_EPA_BYPASS_SEL_SHIFT)) & CIU1_CIU_BCA_DBC_MUX_SEL_BCA2_EPA_BYPASS_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_TST_G2BIST_STATUS - WL G2BIST Status */
+/*! @{ */
+
+#define CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_STATUS_MASK (0xFU)
+#define CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_STATUS_SHIFT (0U)
+/*! WL_G2B_STATUS - Redundant Bist Selection */
+#define CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_STATUS_SHIFT)) & CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_STATUS_MASK)
+
+#define CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_FINISH_MASK (0x10U)
+#define CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_FINISH_SHIFT (4U)
+/*! WL_G2B_FINISH - WL Bist Done */
+#define CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_FINISH(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_FINISH_SHIFT)) & CIU1_CIU_TST_G2BIST_STATUS_WL_G2B_FINISH_MASK)
+
+#define CIU1_CIU_TST_G2BIST_STATUS_MAC1_G2B_FINISH_MASK (0x20U)
+#define CIU1_CIU_TST_G2BIST_STATUS_MAC1_G2B_FINISH_SHIFT (5U)
+/*! MAC1_G2B_FINISH - MAC1 Bist Done */
+#define CIU1_CIU_TST_G2BIST_STATUS_MAC1_G2B_FINISH(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_G2BIST_STATUS_MAC1_G2B_FINISH_SHIFT)) & CIU1_CIU_TST_G2BIST_STATUS_MAC1_G2B_FINISH_MASK)
+/*! @} */
+
+/*! @name CIU_TST_MBIST_READY - MBIST Status (BIST_READY) */
+/*! @{ */
+
+#define CIU1_CIU_TST_MBIST_READY_BIST_READY_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_TST_MBIST_READY_BIST_READY_SHIFT (0U)
+/*! BIST_READY - Bist ready[31:0] */
+#define CIU1_CIU_TST_MBIST_READY_BIST_READY(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_MBIST_READY_BIST_READY_SHIFT)) & CIU1_CIU_TST_MBIST_READY_BIST_READY_MASK)
+/*! @} */
+
+/*! @name CIU_TST_MBIST_FAIL - MBIST Status (BIST_FAIL) */
+/*! @{ */
+
+#define CIU1_CIU_TST_MBIST_FAIL_BIST_FAIL_MASK   (0xFFFFFFFFU)
+#define CIU1_CIU_TST_MBIST_FAIL_BIST_FAIL_SHIFT  (0U)
+/*! BIST_FAIL - Bist Fail[31:0] */
+#define CIU1_CIU_TST_MBIST_FAIL_BIST_FAIL(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_MBIST_FAIL_BIST_FAIL_SHIFT)) & CIU1_CIU_TST_MBIST_FAIL_BIST_FAIL_MASK)
+/*! @} */
+
+/*! @name CIU_TST_TSTBUS_CTRL2 - Testbux Mux Control2 */
+/*! @{ */
+
+#define CIU1_CIU_TST_TSTBUS_CTRL2_SMU_DEBUG_SEL_MASK (0xF8U)
+#define CIU1_CIU_TST_TSTBUS_CTRL2_SMU_DEBUG_SEL_SHIFT (3U)
+/*! SMU_DEBUG_SEL - SMU1/SMU2 Debug Select */
+#define CIU1_CIU_TST_TSTBUS_CTRL2_SMU_DEBUG_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_TSTBUS_CTRL2_SMU_DEBUG_SEL_SHIFT)) & CIU1_CIU_TST_TSTBUS_CTRL2_SMU_DEBUG_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_TST_CTRL - Test Control */
+/*! @{ */
+
+#define CIU1_CIU_TST_CTRL_BBU_TEST_MODE_EN_MASK  (0x200000U)
+#define CIU1_CIU_TST_CTRL_BBU_TEST_MODE_EN_SHIFT (21U)
+/*! BBU_TEST_MODE_EN - Baseband Test Mode Enable */
+#define CIU1_CIU_TST_CTRL_BBU_TEST_MODE_EN(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_CTRL_BBU_TEST_MODE_EN_SHIFT)) & CIU1_CIU_TST_CTRL_BBU_TEST_MODE_EN_MASK)
+/*! @} */
+
+/*! @name CIU_TST_ECO_CTRL - Test ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_TST_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_TST_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_TST_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_TST_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_TST_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_GPS_GPIO_MASK - GPS GPIO MASK */
+/*! @{ */
+
+#define CIU1_CIU_GPS_GPIO_MASK_GPIO2GPS_PPS_MASK_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_GPS_GPIO_MASK_GPIO2GPS_PPS_MASK_SHIFT (0U)
+/*! GPIO2GPS_PPS_MASK - gpio to gps pps mask. '1' is to enable the gpio bit as PPS. Only 1 bit can be set */
+#define CIU1_CIU_GPS_GPIO_MASK_GPIO2GPS_PPS_MASK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_GPS_GPIO_MASK_GPIO2GPS_PPS_MASK_SHIFT)) & CIU1_CIU_GPS_GPIO_MASK_GPIO2GPS_PPS_MASK_MASK)
+/*! @} */
+
+/*! @name CIU_GPS_SW_PERIOD - GPS SWITCH CHANNEL PERIOD */
+/*! @{ */
+
+#define CIU1_CIU_GPS_SW_PERIOD_CH_SW_PERIOD_MASK (0x1FFFFFU)
+#define CIU1_CIU_GPS_SW_PERIOD_CH_SW_PERIOD_SHIFT (0U)
+/*! CH_SW_PERIOD - period for channel switch. default to 50 ms */
+#define CIU1_CIU_GPS_SW_PERIOD_CH_SW_PERIOD(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_GPS_SW_PERIOD_CH_SW_PERIOD_SHIFT)) & CIU1_CIU_GPS_SW_PERIOD_CH_SW_PERIOD_MASK)
+/*! @} */
+
+/*! @name CIU_GPS_SW_EARLY - GPS SWITCH CHANNEL EARLY */
+/*! @{ */
+
+#define CIU1_CIU_GPS_SW_EARLY_CH_SW_EARLY_TIME_MASK (0xFFFFU)
+#define CIU1_CIU_GPS_SW_EARLY_CH_SW_EARLY_TIME_SHIFT (0U)
+/*! CH_SW_EARLY_TIME - time offset from switch channel. default to 1 ms */
+#define CIU1_CIU_GPS_SW_EARLY_CH_SW_EARLY_TIME(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_GPS_SW_EARLY_CH_SW_EARLY_TIME_SHIFT)) & CIU1_CIU_GPS_SW_EARLY_CH_SW_EARLY_TIME_MASK)
+/*! @} */
+
+/*! @name CIU_GPS_TMR_RD - GPS TIMER READ */
+/*! @{ */
+
+#define CIU1_CIU_GPS_TMR_RD_GPS_PPS_TMR_STATUS_MASK (0x3FFFFFU)
+#define CIU1_CIU_GPS_TMR_RD_GPS_PPS_TMR_STATUS_SHIFT (0U)
+/*! GPS_PPS_TMR_STATUS - gps pps timer status read */
+#define CIU1_CIU_GPS_TMR_RD_GPS_PPS_TMR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_GPS_TMR_RD_GPS_PPS_TMR_STATUS_SHIFT)) & CIU1_CIU_GPS_TMR_RD_GPS_PPS_TMR_STATUS_MASK)
+/*! @} */
+
+/*! @name CIU_LDO_ECO_CTRL - LDO ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_LDO_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_LDO_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_LDO_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_LDO_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_LDO_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_AXI_CLK_CTRL2 - AXI clk bypass contrl2 */
+/*! @{ */
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_VAL_MASK (0x1U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_VAL_SHIFT (0U)
+/*! WLM_M_WIP_CG_BYPASS_VAL - AXI Clock gate enable value if bypass is enable. */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_VAL_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_VAL_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_EN_MASK (0x2U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_EN_SHIFT (1U)
+/*! WLM_M_WIP_CG_BYPASS_EN - AXI Dynamic Clock gating Bypass for WEU */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_EN_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_M_WIP_CG_BYPASS_EN_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_VAL_MASK (0x4U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_VAL_SHIFT (2U)
+/*! WLM_M_TBUS_CG_BYPASS_VAL - AXI Clock gate enable value if bypass is enable. */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_VAL_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_VAL_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_EN_MASK (0x8U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_EN_SHIFT (3U)
+/*! WLM_M_TBUS_CG_BYPASS_EN - AXI Dynamic Clock gating Bypass for BBUd SQU Testbus master */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_EN_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_M_TBUS_CG_BYPASS_EN_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_VAL_MASK (0x10U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_VAL_SHIFT (4U)
+/*! WLM_MCU1_64B_CG_BYPASS_VAL - AXI Clock gate enable value for HMAC if bypass is enable. */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_VAL_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_VAL_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_EN_MASK (0x20U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_EN_SHIFT (5U)
+/*! WLM_MCU1_64B_CG_BYPASS_EN - AXI Dynamic Clock gating Bypass for HMAC */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_EN_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_MCU1_64B_CG_BYPASS_EN_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_VAL_MASK (0x40U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_VAL_SHIFT (6U)
+/*! WLM_S_WL_CG_BYPASS_VAL - wlm_soc_wl_cg_bypass_val */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_VAL_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_VAL_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_EN_MASK (0x80U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_EN_SHIFT (7U)
+/*! WLM_S_WL_CG_BYPASS_EN - wlm_soc_wl_cg_bypass_en */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_EN_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_S_WL_CG_BYPASS_EN_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_VAL_MASK (0x100U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_VAL_SHIFT (8U)
+/*! WLM_GPV_CG_BYPASS_VAL - wlm_gpv_cg_bypass_val */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_VAL_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_VAL_MASK)
+
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_EN_MASK (0x200U)
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_EN_SHIFT (9U)
+/*! WLM_GPV_CG_BYPASS_EN - wlm_gpv_cg_bypass_en */
+#define CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_EN_SHIFT)) & CIU1_CIU_AXI_CLK_CTRL2_WLM_GPV_CG_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name CIU_FABRIC_TESTBUS_CTRL - fabric(scm, wlm) testbus select */
+/*! @{ */
+
+#define CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_HIGH_TESTBUS_SEL_MASK (0x3F0000U)
+#define CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_HIGH_TESTBUS_SEL_SHIFT (16U)
+/*! WLM_HIGH_TESTBUS_SEL - testbus select for smu1_nic_testbus[15:8] */
+#define CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_HIGH_TESTBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_HIGH_TESTBUS_SEL_SHIFT)) & CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_HIGH_TESTBUS_SEL_MASK)
+
+#define CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_LOW_TESTBUS_SEL_MASK (0x3F000000U)
+#define CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_LOW_TESTBUS_SEL_SHIFT (24U)
+/*! WLM_LOW_TESTBUS_SEL - testbus select for smu1_nic_testbus[7:0] */
+#define CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_LOW_TESTBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_LOW_TESTBUS_SEL_SHIFT)) & CIU1_CIU_FABRIC_TESTBUS_CTRL_WLM_LOW_TESTBUS_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_FABRIC_CREQ_DLY_TIMER - fabric(scm, wlm) delay timer for c_req */
+/*! @{ */
+
+#define CIU1_CIU_FABRIC_CREQ_DLY_TIMER_WLM_CREQ_DLY_TIMER_MASK (0x3FF00000U)
+#define CIU1_CIU_FABRIC_CREQ_DLY_TIMER_WLM_CREQ_DLY_TIMER_SHIFT (20U)
+/*! WLM_CREQ_DLY_TIMER - wlm delay timer for c_req */
+#define CIU1_CIU_FABRIC_CREQ_DLY_TIMER_WLM_CREQ_DLY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_FABRIC_CREQ_DLY_TIMER_WLM_CREQ_DLY_TIMER_SHIFT)) & CIU1_CIU_FABRIC_CREQ_DLY_TIMER_WLM_CREQ_DLY_TIMER_MASK)
+/*! @} */
+
+/*! @name CIU_ABU_ECO_CTRL - ABU ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_ABU_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_ABU_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_ABU_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ABU_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_ABU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU1_AHB1_TO_CLEAR - AHB1 timeout logic clear register */
+/*! @{ */
+
+#define CIU1_CIU1_AHB1_TO_CLEAR_AHB1_TIMEOUT_CLEAR_MASK (0x1U)
+#define CIU1_CIU1_AHB1_TO_CLEAR_AHB1_TIMEOUT_CLEAR_SHIFT (0U)
+/*! AHB1_TIMEOUT_CLEAR - After the timeout happened on AHB1 bus, the cpu will read the ERR ISR and
+ *    read the bus state which cause the timeout and then set this bit to 1 to clear the AHB1 timeout
+ *    logic to start recroding next transaction. This is self clearing bit
+ */
+#define CIU1_CIU1_AHB1_TO_CLEAR_AHB1_TIMEOUT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_AHB1_TO_CLEAR_AHB1_TIMEOUT_CLEAR_SHIFT)) & CIU1_CIU1_AHB1_TO_CLEAR_AHB1_TIMEOUT_CLEAR_MASK)
+
+#define CIU1_CIU1_AHB1_TO_CLEAR_CPU1_DCODE_INV_ADDR_CLR_MASK (0x2U)
+#define CIU1_CIU1_AHB1_TO_CLEAR_CPU1_DCODE_INV_ADDR_CLR_SHIFT (1U)
+/*! CPU1_DCODE_INV_ADDR_CLR - After the invalid address int happened on CPU1 dcode bus, the cpu1
+ *    will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1
+ *    to clear the CPU1 Dcode invalid addr logic to start recroding next transaction. This is self
+ *    clearing bit
+ */
+#define CIU1_CIU1_AHB1_TO_CLEAR_CPU1_DCODE_INV_ADDR_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_AHB1_TO_CLEAR_CPU1_DCODE_INV_ADDR_CLR_SHIFT)) & CIU1_CIU1_AHB1_TO_CLEAR_CPU1_DCODE_INV_ADDR_CLR_MASK)
+
+#define CIU1_CIU1_AHB1_TO_CLEAR_CPU1_ICODE_INV_ADDR_CLR_MASK (0x4U)
+#define CIU1_CIU1_AHB1_TO_CLEAR_CPU1_ICODE_INV_ADDR_CLR_SHIFT (2U)
+/*! CPU1_ICODE_INV_ADDR_CLR - After the invalid address int happened on CPU1 icode bus, the cpu1
+ *    will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1
+ *    to clear the CPU1 Icode invalid addr logic to start recroding next transaction. This is self
+ *    clearing bit
+ */
+#define CIU1_CIU1_AHB1_TO_CLEAR_CPU1_ICODE_INV_ADDR_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_AHB1_TO_CLEAR_CPU1_ICODE_INV_ADDR_CLR_SHIFT)) & CIU1_CIU1_AHB1_TO_CLEAR_CPU1_ICODE_INV_ADDR_CLR_MASK)
+/*! @} */
+
+/*! @name CIU_ARB_TO_LAST_ADDR - AHB Timeout Last Address */
+/*! @{ */
+
+#define CIU1_CIU_ARB_TO_LAST_ADDR_ADDRESS_MASK   (0xFFFFFFFFU)
+#define CIU1_CIU_ARB_TO_LAST_ADDR_ADDRESS_SHIFT  (0U)
+/*! ADDRESS - Last AHB1 Address Right Before the Current Timeout */
+#define CIU1_CIU_ARB_TO_LAST_ADDR_ADDRESS(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_TO_LAST_ADDR_ADDRESS_SHIFT)) & CIU1_CIU_ARB_TO_LAST_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name CIU_ARB_TO_CUR_ADDR - AHB Current Timeout Address */
+/*! @{ */
+
+#define CIU1_CIU_ARB_TO_CUR_ADDR_ADDRESS_MASK    (0xFFFFFFFFU)
+#define CIU1_CIU_ARB_TO_CUR_ADDR_ADDRESS_SHIFT   (0U)
+/*! ADDRESS - Current_TO_Addr */
+#define CIU1_CIU_ARB_TO_CUR_ADDR_ADDRESS(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_TO_CUR_ADDR_ADDRESS_SHIFT)) & CIU1_CIU_ARB_TO_CUR_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name CIU_ARB_CTRL - AHB ARB Control */
+/*! @{ */
+
+#define CIU1_CIU_ARB_CTRL_CURRENT_TO_SLAVE_ID_MASK (0xFU)
+#define CIU1_CIU_ARB_CTRL_CURRENT_TO_SLAVE_ID_SHIFT (0U)
+/*! CURRENT_TO_SLAVE_ID - Current_TO_Slave_ID */
+#define CIU1_CIU_ARB_CTRL_CURRENT_TO_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_CURRENT_TO_SLAVE_ID_SHIFT)) & CIU1_CIU_ARB_CTRL_CURRENT_TO_SLAVE_ID_MASK)
+
+#define CIU1_CIU_ARB_CTRL_LAST_TO_SLAVE_ID_MASK  (0xF0U)
+#define CIU1_CIU_ARB_CTRL_LAST_TO_SLAVE_ID_SHIFT (4U)
+/*! LAST_TO_SLAVE_ID - Last_TO_Slave_ID */
+#define CIU1_CIU_ARB_CTRL_LAST_TO_SLAVE_ID(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_LAST_TO_SLAVE_ID_SHIFT)) & CIU1_CIU_ARB_CTRL_LAST_TO_SLAVE_ID_MASK)
+
+#define CIU1_CIU_ARB_CTRL_CURRENT_TO_MASTER_ID_MASK (0x700U)
+#define CIU1_CIU_ARB_CTRL_CURRENT_TO_MASTER_ID_SHIFT (8U)
+/*! CURRENT_TO_MASTER_ID - Current_TO_Master_ID */
+#define CIU1_CIU_ARB_CTRL_CURRENT_TO_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_CURRENT_TO_MASTER_ID_SHIFT)) & CIU1_CIU_ARB_CTRL_CURRENT_TO_MASTER_ID_MASK)
+
+#define CIU1_CIU_ARB_CTRL_LAST_TO_MASTER_ID_MASK (0x3800U)
+#define CIU1_CIU_ARB_CTRL_LAST_TO_MASTER_ID_SHIFT (11U)
+/*! LAST_TO_MASTER_ID - Last_TO_Master_ID */
+#define CIU1_CIU_ARB_CTRL_LAST_TO_MASTER_ID(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_LAST_TO_MASTER_ID_SHIFT)) & CIU1_CIU_ARB_CTRL_LAST_TO_MASTER_ID_MASK)
+
+#define CIU1_CIU_ARB_CTRL_AHB1_SMU1_MEM_PROT_DIS_MASK (0x10000U)
+#define CIU1_CIU_ARB_CTRL_AHB1_SMU1_MEM_PROT_DIS_SHIFT (16U)
+/*! AHB1_SMU1_MEM_PROT_DIS - Disable SMU1 Memory Protection from AHB2 side */
+#define CIU1_CIU_ARB_CTRL_AHB1_SMU1_MEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_AHB1_SMU1_MEM_PROT_DIS_SHIFT)) & CIU1_CIU_ARB_CTRL_AHB1_SMU1_MEM_PROT_DIS_MASK)
+
+#define CIU1_CIU_ARB_CTRL_AHB1_CPU1_IMEM_PROT_DIS_MASK (0x20000U)
+#define CIU1_CIU_ARB_CTRL_AHB1_CPU1_IMEM_PROT_DIS_SHIFT (17U)
+/*! AHB1_CPU1_IMEM_PROT_DIS - 1 = Disable CPU1 Imem Memory Protection from AHB1 side and allow AHB1 to read/write Imem */
+#define CIU1_CIU_ARB_CTRL_AHB1_CPU1_IMEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_AHB1_CPU1_IMEM_PROT_DIS_SHIFT)) & CIU1_CIU_ARB_CTRL_AHB1_CPU1_IMEM_PROT_DIS_MASK)
+
+#define CIU1_CIU_ARB_CTRL_AHB1_CPU1_DMEM_PROT_DIS_MASK (0x40000U)
+#define CIU1_CIU_ARB_CTRL_AHB1_CPU1_DMEM_PROT_DIS_SHIFT (18U)
+/*! AHB1_CPU1_DMEM_PROT_DIS - 1 = Disable CPU1 Dmem Memory Protection from AHB1 side and allow AHB1 to read/write Dmem */
+#define CIU1_CIU_ARB_CTRL_AHB1_CPU1_DMEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_AHB1_CPU1_DMEM_PROT_DIS_SHIFT)) & CIU1_CIU_ARB_CTRL_AHB1_CPU1_DMEM_PROT_DIS_MASK)
+
+#define CIU1_CIU_ARB_CTRL_AHB1_A2A_PROT_DIS_MASK (0x80000U)
+#define CIU1_CIU_ARB_CTRL_AHB1_A2A_PROT_DIS_SHIFT (19U)
+/*! AHB1_A2A_PROT_DIS - 1 = Disable A2A Memory Protection from AHB1 side and allow AHB1 to A2A */
+#define CIU1_CIU_ARB_CTRL_AHB1_A2A_PROT_DIS(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_AHB1_A2A_PROT_DIS_SHIFT)) & CIU1_CIU_ARB_CTRL_AHB1_A2A_PROT_DIS_MASK)
+
+#define CIU1_CIU_ARB_CTRL_ARB_TIMEOUT_MODE_MASK  (0xC0000000U)
+#define CIU1_CIU_ARB_CTRL_ARB_TIMEOUT_MODE_SHIFT (30U)
+/*! ARB_TIMEOUT_MODE - AHB1_TimeoutMode[1:0] */
+#define CIU1_CIU_ARB_CTRL_ARB_TIMEOUT_MODE(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_CTRL_ARB_TIMEOUT_MODE_SHIFT)) & CIU1_CIU_ARB_CTRL_ARB_TIMEOUT_MODE_MASK)
+/*! @} */
+
+/*! @name CIU1_CPU1_ICODE_INV_ADDR_CTRL - CPU1 Icode invalid address access control */
+/*! @{ */
+
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK (0xFU)
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT (0U)
+/*! LAST2_INV_ADDR_SLAVE_ID - Last2_inv_addr_Slave_ID */
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT)) & CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK (0xF0U)
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT (4U)
+/*! LAST_INV_ADDR_SLAVE_ID - Last_inv_addr_Slave_ID */
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT)) & CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK (0xF00U)
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT (8U)
+/*! CUR_INV_ADDR_SLAVE_ID - Cur_inv_addr_Slave_ID */
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT)) & CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK (0xC0000000U)
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT (30U)
+/*! HADDR_ICOD_SEL - There are 3 haddr which can be observed by selecting this: */
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT)) & CIU1_CIU1_CPU1_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK)
+/*! @} */
+
+/*! @name CIU1_CPU1_ICODE_INV_ADDR - CPU1 Icode invalid address */
+/*! @{ */
+
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_HADDR_INV_ADDR_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_HADDR_INV_ADDR_SHIFT (0U)
+/*! HADDR_INV_ADDR - based on CIU1_CPU1_ICODE_INV_ADDR_CTRL[31:30], the address status is observed in this register */
+#define CIU1_CIU1_CPU1_ICODE_INV_ADDR_HADDR_INV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_ICODE_INV_ADDR_HADDR_INV_ADDR_SHIFT)) & CIU1_CIU1_CPU1_ICODE_INV_ADDR_HADDR_INV_ADDR_MASK)
+/*! @} */
+
+/*! @name CIU1_CPU1_DCODE_INV_ADDR_CTRL - CPU1 Dcode invalid address access control */
+/*! @{ */
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK (0xFU)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT (0U)
+/*! LAST2_INV_ADDR_SLAVE_ID - Last2_inv_addr_Slave_ID */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK (0xF0U)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT (4U)
+/*! LAST_INV_ADDR_SLAVE_ID - Last_inv_addr_Slave_ID */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK (0xF00U)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT (8U)
+/*! CUR_INV_ADDR_SLAVE_ID - Cur_inv_addr_Slave_ID */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_MASK (0xF000U)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_SHIFT (12U)
+/*! LAST2_INV_ADDR_MASTER_ID - Last2_inv_addr_master_ID */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_MASK)
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_MASK (0xF0000U)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_SHIFT (16U)
+/*! LAST_INV_ADDR_MASTER_ID - Last_inv_addr_master_ID */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_MASK)
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_MASK (0xF00000U)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_SHIFT (20U)
+/*! CUR_INV_ADDR_MASTER_ID - Cur_inv_addr_master_ID */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_MASK)
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_HADDR_DCOD_SEL_MASK (0xC0000000U)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_HADDR_DCOD_SEL_SHIFT (30U)
+/*! HADDR_DCOD_SEL - There are 3 haddr which can be observed by selecting this: */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_HADDR_DCOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_HADDR_DCOD_SEL_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_CTRL_HADDR_DCOD_SEL_MASK)
+/*! @} */
+
+/*! @name CIU1_CPU1_DCODE_INV_ADDR - CPU1 Dcode invalid address */
+/*! @{ */
+
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_HADDR_INV_ADDR_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_HADDR_INV_ADDR_SHIFT (0U)
+/*! HADDR_INV_ADDR - based on CIU1_CPU1_DCODE_INV_ADDR_CTRL[31:30], the address status is observed in this register */
+#define CIU1_CIU1_CPU1_DCODE_INV_ADDR_HADDR_INV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_DCODE_INV_ADDR_HADDR_INV_ADDR_SHIFT)) & CIU1_CIU1_CPU1_DCODE_INV_ADDR_HADDR_INV_ADDR_MASK)
+/*! @} */
+
+/*! @name CIU1_AHB2AHB_BRIDGE_CTRL - AHB2AHB Bridge Control Register */
+/*! @{ */
+
+#define CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_MASK (0x1U)
+#define CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_SHIFT (0U)
+/*! PREFETCH_HSEL_EN - ahb2ahb bridge pre-fetch hsel enable */
+#define CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_SHIFT)) & CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_MASK)
+
+#define CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_MCI_WL_A2A_PREFETCH_EN_MASK (0x2U)
+#define CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_MCI_WL_A2A_PREFETCH_EN_SHIFT (1U)
+/*! MCI_WL_A2A_PREFETCH_EN - MCI-WL ahb2ahb bridge pre-fetch hsel enable */
+#define CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_MCI_WL_A2A_PREFETCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_MCI_WL_A2A_PREFETCH_EN_SHIFT)) & CIU1_CIU1_AHB2AHB_BRIDGE_CTRL_MCI_WL_A2A_PREFETCH_EN_MASK)
+/*! @} */
+
+/*! @name WL_RAACS_CTRL - RAACS control registers */
+/*! @{ */
+
+#define CIU1_WL_RAACS_CTRL_RAACS_EN_MASK         (0x1U)
+#define CIU1_WL_RAACS_CTRL_RAACS_EN_SHIFT        (0U)
+/*! RAACS_EN - raacs en . S/W Write 1 to enable raacs block. */
+#define CIU1_WL_RAACS_CTRL_RAACS_EN(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_WL_RAACS_CTRL_RAACS_EN_SHIFT)) & CIU1_WL_RAACS_CTRL_RAACS_EN_MASK)
+
+#define CIU1_WL_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_MASK (0x2U)
+#define CIU1_WL_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_SHIFT (1U)
+/*! USE_RAACS_CLK_FOR_CPU - SW write 0 to use RAACS clock for CPU. SW write 1 to select clock gating
+ *    based alternate implementation of RAACS clocking for CM3 CPU.
+ */
+#define CIU1_WL_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU(x) (((uint32_t)(((uint32_t)(x)) << CIU1_WL_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_SHIFT)) & CIU1_WL_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_MASK)
+
+#define CIU1_WL_RAACS_CTRL_RAACS_CLK_SEL_MASK    (0x1CU)
+#define CIU1_WL_RAACS_CTRL_RAACS_CLK_SEL_SHIFT   (2U)
+/*! RAACS_CLK_SEL - defines the lowest clock to which RAACS will go down to during IDLE period (x/2;
+ *    x/4; x/8; ... ;x/128) for the given test.
+ */
+#define CIU1_WL_RAACS_CTRL_RAACS_CLK_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_WL_RAACS_CTRL_RAACS_CLK_SEL_SHIFT)) & CIU1_WL_RAACS_CTRL_RAACS_CLK_SEL_MASK)
+
+#define CIU1_WL_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_MASK (0x7FFE0U)
+#define CIU1_WL_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_SHIFT (5U)
+/*! RAACS_WAIT_COUNTER_VALUE - initial IDLE-time for which RAACS FSM waits before starting to scale down the clock. */
+#define CIU1_WL_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_WL_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_SHIFT)) & CIU1_WL_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_MASK)
+
+#define CIU1_WL_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_MASK (0xFFF80000U)
+#define CIU1_WL_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_SHIFT (19U)
+/*! RAACS_IDLE_COUNTER_VALUE - IDLE time for which RAACS-FSM waits before shifting to next successive scaled clock. */
+#define CIU1_WL_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_WL_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_SHIFT)) & CIU1_WL_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_MASK)
+/*! @} */
+
+/*! @name WL_RAACS_PERFORMANCE_STATISTICS - RAACS performance statistics counter. */
+/*! @{ */
+
+#define CIU1_WL_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_MASK (0x1U)
+#define CIU1_WL_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_SHIFT (0U)
+/*! PERFORMANCE_STATISTICS_CNT_EN - performance counter en. S/W write 1 to enable performance counter. */
+#define CIU1_WL_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU1_WL_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_SHIFT)) & CIU1_WL_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_MASK)
+
+#define CIU1_WL_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_MASK (0xFFFFFFEU)
+#define CIU1_WL_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_SHIFT (1U)
+/*! RAACS_PERFORMANCE_STATISTICS - This counter is maintaining RAACS performance count. This counter
+ *    will increment by one after every 1 us(1MHZ) when RAACS is in scaled clk state.
+ */
+#define CIU1_WL_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_WL_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_SHIFT)) & CIU1_WL_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_MASK)
+/*! @} */
+
+/*! @name CIU_AHB1_TSTBUS_SEL - AHB1 Control Signals testbus select */
+/*! @{ */
+
+#define CIU1_CIU_AHB1_TSTBUS_SEL_AHB1_TSTBUS_SEL_MASK (0x1U)
+#define CIU1_CIU_AHB1_TSTBUS_SEL_AHB1_TSTBUS_SEL_SHIFT (0U)
+/*! AHB1_TSTBUS_SEL - Select AHB1 Arbiter Testbus for testing */
+#define CIU1_CIU_AHB1_TSTBUS_SEL_AHB1_TSTBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AHB1_TSTBUS_SEL_AHB1_TSTBUS_SEL_SHIFT)) & CIU1_CIU_AHB1_TSTBUS_SEL_AHB1_TSTBUS_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_ARB_ECO_CTRL - ARB ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_ARB_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_ARB_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_ARB_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_ARB_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_ARB_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_DYN_CLK_CTRL - Dynamic CPU Clock Control */
+/*! @{ */
+
+#define CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_CPU1_CTRL_DIS_MASK (0x10000000U)
+#define CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_CPU1_CTRL_DIS_SHIFT (28U)
+/*! DYN_CPU1_CTRL_DIS - Disable Dynamic CPU1 Clock Control Feature */
+#define CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_CPU1_CTRL_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_CPU1_CTRL_DIS_SHIFT)) & CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_CPU1_CTRL_DIS_MASK)
+
+#define CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_SYS_CTRL_DIS_MASK (0x20000000U)
+#define CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_SYS_CTRL_DIS_SHIFT (29U)
+/*! DYN_SYS_CTRL_DIS - Disable Dynamic SYS Clock Control Feature */
+#define CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_SYS_CTRL_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_SYS_CTRL_DIS_SHIFT)) & CIU1_CIU_CPU_DYN_CLK_CTRL_DYN_SYS_CTRL_DIS_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_DYN_CPUCLK_MONITOR - Dynamic ahb clock Monitor */
+/*! @{ */
+
+#define CIU1_CIU_CPU_DYN_CPUCLK_MONITOR_DYN_CPU1_CLK_MON_T1_MASK (0xFU)
+#define CIU1_CIU_CPU_DYN_CPUCLK_MONITOR_DYN_CPU1_CLK_MON_T1_SHIFT (0U)
+/*! DYN_CPU1_CLK_MON_T1 - Dynamic CPU1 Clock Monitor T1 */
+#define CIU1_CIU_CPU_DYN_CPUCLK_MONITOR_DYN_CPU1_CLK_MON_T1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_DYN_CPUCLK_MONITOR_DYN_CPU1_CLK_MON_T1_SHIFT)) & CIU1_CIU_CPU_DYN_CPUCLK_MONITOR_DYN_CPU1_CLK_MON_T1_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_DYN_SYSCLK_MONITOR - Dynamic sysclk Monitor */
+/*! @{ */
+
+#define CIU1_CIU_CPU_DYN_SYSCLK_MONITOR_DYN_SYSCLK_MON_T1_MASK (0xFU)
+#define CIU1_CIU_CPU_DYN_SYSCLK_MONITOR_DYN_SYSCLK_MON_T1_SHIFT (0U)
+/*! DYN_SYSCLK_MON_T1 - Dynamic System Clock Monitor T1 */
+#define CIU1_CIU_CPU_DYN_SYSCLK_MONITOR_DYN_SYSCLK_MON_T1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_DYN_SYSCLK_MONITOR_DYN_SYSCLK_MON_T1_SHIFT)) & CIU1_CIU_CPU_DYN_SYSCLK_MONITOR_DYN_SYSCLK_MON_T1_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_CPU1_CTRL - CPU1 control register */
+/*! @{ */
+
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU1_DBG_CTRL_MASK (0xFF00U)
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU1_DBG_CTRL_SHIFT (8U)
+/*! CPU1_DBG_CTRL - cpu2 debug control */
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU1_DBG_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU1_CTRL_CPU1_DBG_CTRL_SHIFT)) & CIU1_CIU_CPU_CPU1_CTRL_CPU1_DBG_CTRL_MASK)
+
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU1_CPU3_MSG_SCHEME_MASK (0x40000U)
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU1_CPU3_MSG_SCHEME_SHIFT (18U)
+/*! CPU1_CPU3_MSG_SCHEME - CPU1 to CPU3 Message Scheme */
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU1_CPU3_MSG_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU1_CTRL_CPU1_CPU3_MSG_SCHEME_SHIFT)) & CIU1_CIU_CPU_CPU1_CTRL_CPU1_CPU3_MSG_SCHEME_MASK)
+
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU3_RESET_INT_MASK (0x20000000U)
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU3_RESET_INT_SHIFT (29U)
+/*! CPU3_RESET_INT - cpu1 fw reset cpu3 */
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU3_RESET_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU1_CTRL_CPU3_RESET_INT_SHIFT)) & CIU1_CIU_CPU_CPU1_CTRL_CPU3_RESET_INT_MASK)
+
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU2_RESET_INT_MASK (0x80000000U)
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU2_RESET_INT_SHIFT (31U)
+/*! CPU2_RESET_INT - cpu1 fw reset cpu2 */
+#define CIU1_CIU_CPU_CPU1_CTRL_CPU2_RESET_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU1_CTRL_CPU2_RESET_INT_SHIFT)) & CIU1_CIU_CPU_CPU1_CTRL_CPU2_RESET_INT_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_CPU1_ACCESS_CTRL - CPU1 access control register */
+/*! @{ */
+
+#define CIU1_CIU_CPU_CPU1_ACCESS_CTRL_CPU1_ACCESS_CTRL_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_CPU_CPU1_ACCESS_CTRL_CPU1_ACCESS_CTRL_SHIFT (0U)
+/*! CPU1_ACCESS_CTRL - CPU1 will read CIU_CPU_CPU1_ACCESS_CRTL and set CIU_CPU1_ACCESS_CRTL bit.
+ *    After writing the bit, the CPU1 will check if the CIU_CPU_CPU1_ACCESS_CRTL bit is set or not. If
+ *    set then CPU1 will access the resource (for e.g CSU).
+ */
+#define CIU1_CIU_CPU_CPU1_ACCESS_CTRL_CPU1_ACCESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU1_ACCESS_CTRL_CPU1_ACCESS_CTRL_SHIFT)) & CIU1_CIU_CPU_CPU1_ACCESS_CTRL_CPU1_ACCESS_CTRL_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_CPU2_ACCESS_CTRL - CPU2 access control register */
+/*! @{ */
+
+#define CIU1_CIU_CPU_CPU2_ACCESS_CTRL_CPU2_ACCESS_CTRL_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_CPU_CPU2_ACCESS_CTRL_CPU2_ACCESS_CTRL_SHIFT (0U)
+/*! CPU2_ACCESS_CTRL - CPU2 will read CIU_CPU_CPU2_ACCESS_CRTL and set CIU_CPU2_ACCESS_CRTL bit.
+ *    After writing the bit, the CPU2 will check if the CIU_CPU_CPU2_ACCESS_CRTL bit is set or not. If
+ *    set then CPU2 will access the resource (for e.g CSU).
+ */
+#define CIU1_CIU_CPU_CPU2_ACCESS_CTRL_CPU2_ACCESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU2_ACCESS_CTRL_CPU2_ACCESS_CTRL_SHIFT)) & CIU1_CIU_CPU_CPU2_ACCESS_CTRL_CPU2_ACCESS_CTRL_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_CPU3_ACCESS_CTRL - CPU3 access control register */
+/*! @{ */
+
+#define CIU1_CIU_CPU_CPU3_ACCESS_CTRL_CPU3_ACCESS_CTRL_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_CPU_CPU3_ACCESS_CTRL_CPU3_ACCESS_CTRL_SHIFT (0U)
+/*! CPU3_ACCESS_CTRL - CPU3 will read CIU_CPU_CPU3_ACCESS_CRTL and set CIU_CPU3_ACCESS_CRTL bit.
+ *    After writing the bit, the CPU3 will check if the CIU_CPU_CPU3_ACCESS_CRTL bit is set or not. If
+ *    set then CPU3 will access the resource (for e.g CSU).
+ */
+#define CIU1_CIU_CPU_CPU3_ACCESS_CTRL_CPU3_ACCESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU3_ACCESS_CTRL_CPU3_ACCESS_CTRL_SHIFT)) & CIU1_CIU_CPU_CPU3_ACCESS_CTRL_CPU3_ACCESS_CTRL_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_CPU1_DBG_STAT1 - CPU1 debug register1 */
+/*! @{ */
+
+#define CIU1_CIU_CPU_CPU1_DBG_STAT1_CPU1_RO_STATUS_MASK (0xFFFFFFFFU)
+#define CIU1_CIU_CPU_CPU1_DBG_STAT1_CPU1_RO_STATUS_SHIFT (0U)
+/*! CPU1_RO_STATUS - cpu1 debug output */
+#define CIU1_CIU_CPU_CPU1_DBG_STAT1_CPU1_RO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_CPU1_DBG_STAT1_CPU1_RO_STATUS_SHIFT)) & CIU1_CIU_CPU_CPU1_DBG_STAT1_CPU1_RO_STATUS_MASK)
+/*! @} */
+
+/*! @name CIU_CPU1_CPU2_FW_DWLD_CTRL - CPUs FW dwld control register */
+/*! @{ */
+
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_FW_DWLD_INFO_VALID_MASK (0x1U)
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_FW_DWLD_INFO_VALID_SHIFT (0U)
+/*! FW_DWLD_INFO_VALID - After writing the bit[8] and bit[16], the CPU1 writes valid bit to indicate
+ *    to cpu2 that information is valid and ready to use. CPU2 polls this bit and once set take
+ *    appropriate action based on bit[8] and bit[16]
+ */
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_FW_DWLD_INFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_FW_DWLD_INFO_VALID_SHIFT)) & CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_FW_DWLD_INFO_VALID_MASK)
+
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_SKETCH_MASK (0xFEU)
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_SKETCH_SHIFT (1U)
+/*! PARALLEL_DWLD_SKETCH - SKETCH register for Parallel download */
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_SKETCH(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_SKETCH_SHIFT)) & CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_SKETCH_MASK)
+
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_MASK (0x100U)
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_SHIFT (8U)
+/*! PARALLEL_DWLD - For the parallel mode of FW download, CPU1 assert this bit to provide information to CPU2. */
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_SHIFT)) & CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_PARALLEL_DWLD_MASK)
+
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_SKETCH_MASK (0xFE00U)
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_SKETCH_SHIFT (9U)
+/*! CPU2_FW_DWLD_SKETCH - Sketch registers for Chip Download */
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_SKETCH(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_SKETCH_SHIFT)) & CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_SKETCH_MASK)
+
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_DONE_MASK (0x10000U)
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_DONE_SHIFT (16U)
+/*! CPU2_FW_DWLD_DONE - For the serial mode of FW download, when CPU1 done with FW download for CPU2
+ *    also, then it assert this bit. After this CPU2 can jump to it's ITCM to start execution
+ */
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_DONE_SHIFT)) & CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CPU2_FW_DWLD_DONE_MASK)
+
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_SKETCH_MASK (0x7FFE0000U)
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_SKETCH_SHIFT (17U)
+/*! CHIP_INIT_DONE_SKETCH - Sketch registers for Chip Init */
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_SKETCH(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_SKETCH_SHIFT)) & CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_SKETCH_MASK)
+
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_MASK (0x80000000U)
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_SHIFT (31U)
+/*! CHIP_INIT_DONE - After the FW is downloaded (serial or parallel), the CPU1 does the chip init
+ *    and set this bit. It is used later by boot code in case the FW crash happen, then it doesn't
+ *    need to do chip init again
+ */
+#define CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_SHIFT)) & CIU1_CIU_CPU1_CPU2_FW_DWLD_CTRL_CHIP_INIT_DONE_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_COMM0 - CPU Communication reserved0 */
+/*! @{ */
+
+#define CIU1_CIU_CPU_COMM0_CPU_COMM0_MASK        (0xFFFFFFFFU)
+#define CIU1_CIU_CPU_COMM0_CPU_COMM0_SHIFT       (0U)
+/*! CPU_COMM0 - CPUs extra reserved communication reg to be used by FW */
+#define CIU1_CIU_CPU_COMM0_CPU_COMM0(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_COMM0_CPU_COMM0_SHIFT)) & CIU1_CIU_CPU_COMM0_CPU_COMM0_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_COMM1 - CPU Communication reserved1 */
+/*! @{ */
+
+#define CIU1_CIU_CPU_COMM1_CPU_COMM1_MASK        (0xFFFFFFFFU)
+#define CIU1_CIU_CPU_COMM1_CPU_COMM1_SHIFT       (0U)
+/*! CPU_COMM1 - CPUs extra reserved communication reg to be used by FW */
+#define CIU1_CIU_CPU_COMM1_CPU_COMM1(x)          (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_COMM1_CPU_COMM1_SHIFT)) & CIU1_CIU_CPU_COMM1_CPU_COMM1_MASK)
+/*! @} */
+
+/*! @name CIU_CPU_ECO_CTRL - CPU ECO control */
+/*! @{ */
+
+#define CIU1_CIU_CPU_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_CPU_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_CPU_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_CPU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_RFU_CTRL - RFU Control and Status */
+/*! @{ */
+
+#define CIU1_CIU_RFU_CTRL_APB_EN_5G_MASK         (0x2U)
+#define CIU1_CIU_RFU_CTRL_APB_EN_5G_SHIFT        (1U)
+/*! APB_EN_5G - Enable RFU5G APB Interface for Register Programming */
+#define CIU1_CIU_RFU_CTRL_APB_EN_5G(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_CTRL_APB_EN_5G_SHIFT)) & CIU1_CIU_RFU_CTRL_APB_EN_5G_MASK)
+
+#define CIU1_CIU_RFU_CTRL_APB_DWORD_SEL_MASK     (0x4U)
+#define CIU1_CIU_RFU_CTRL_APB_DWORD_SEL_SHIFT    (2U)
+/*! APB_DWORD_SEL - RFU APB DWORD Select */
+#define CIU1_CIU_RFU_CTRL_APB_DWORD_SEL(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_CTRL_APB_DWORD_SEL_SHIFT)) & CIU1_CIU_RFU_CTRL_APB_DWORD_SEL_MASK)
+
+#define CIU1_CIU_RFU_CTRL_APB_EN_2G_MASK         (0x8U)
+#define CIU1_CIU_RFU_CTRL_APB_EN_2G_SHIFT        (3U)
+/*! APB_EN_2G - Enable RFU2G APB Interface for Register Programming */
+#define CIU1_CIU_RFU_CTRL_APB_EN_2G(x)           (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_CTRL_APB_EN_2G_SHIFT)) & CIU1_CIU_RFU_CTRL_APB_EN_2G_MASK)
+
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_2G_A_MASK  (0x20000000U)
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_2G_A_SHIFT (29U)
+/*! RFU_TRX_RDY_2G_A - RFU2G channel A Rdy Status */
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_2G_A(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_2G_A_SHIFT)) & CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_2G_A_MASK)
+
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_A_MASK  (0x40000000U)
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_A_SHIFT (30U)
+/*! RFU_TRX_RDY_5G_A - RFU5G channel A Rdy Status */
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_A(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_A_SHIFT)) & CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_A_MASK)
+
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_B_MASK  (0x80000000U)
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_B_SHIFT (31U)
+/*! RFU_TRX_RDY_5G_B - RFU5G channel B Rdy Status */
+#define CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_B(x)    (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_B_SHIFT)) & CIU1_CIU_RFU_CTRL_RFU_TRX_RDY_5G_B_MASK)
+/*! @} */
+
+/*! @name CIU_RFU_EXTRA_PORT - RFU Extra Port Connection */
+/*! @{ */
+
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_A_MASK (0xFFU)
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_A_SHIFT (0U)
+/*! SOC_RFU5G_EXTRA_A - SOC_RFU5G_EXTRA_A[7:0] */
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_A(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_A_SHIFT)) & CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_A_MASK)
+
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_B_MASK (0xFF00U)
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_B_SHIFT (8U)
+/*! SOC_RFU5G_EXTRA_B - SOC_RFU5G_EXTRA_B[7:0] */
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_B(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_B_SHIFT)) & CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU5G_EXTRA_B_MASK)
+
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_A_MASK (0xFF0000U)
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_A_SHIFT (16U)
+/*! SOC_RFU2G_EXTRA_A - SOC_RFU2G_EXTRA_A[7:0] */
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_A(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_A_SHIFT)) & CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_A_MASK)
+
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_B_MASK (0xF000000U)
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_B_SHIFT (24U)
+/*! SOC_RFU2G_EXTRA_B - SOC_RFU2G_EXTRA_B[3:0] */
+#define CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_B(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_B_SHIFT)) & CIU1_CIU_RFU_EXTRA_PORT_SOC_RFU2G_EXTRA_B_MASK)
+/*! @} */
+
+/*! @name CIU_RFU_ECO_CTRL - RFU ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_RFU_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_RFU_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_RFU_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_RFU_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_RFU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_MCI_EXTRA - MCI EXTRA Ports */
+/*! @{ */
+
+#define CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_OUT_MASK (0xFU)
+#define CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_OUT_SHIFT (0U)
+/*! CIU_MCI_EXTRA_OUT - Extra Ports to MCI */
+#define CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_OUT(x)  (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_OUT_SHIFT)) & CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_OUT_MASK)
+
+#define CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_IN_MASK (0xF0U)
+#define CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_IN_SHIFT (4U)
+/*! CIU_MCI_EXTRA_IN - Extra Ports from MCI */
+#define CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_IN(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_IN_SHIFT)) & CIU1_CIU_MCI_EXTRA_CIU_MCI_EXTRA_IN_MASK)
+/*! @} */
+
+/*! @name CIU_BBUD_CTRL - BBUD Control Register */
+/*! @{ */
+
+#define CIU1_CIU_BBUD_CTRL_APB_EN_BBU1_MASK      (0x1U)
+#define CIU1_CIU_BBUD_CTRL_APB_EN_BBU1_SHIFT     (0U)
+/*! APB_EN_BBU1 - Enable BBUD1 APB Interface for Register Programming */
+#define CIU1_CIU_BBUD_CTRL_APB_EN_BBU1(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_CTRL_APB_EN_BBU1_SHIFT)) & CIU1_CIU_BBUD_CTRL_APB_EN_BBU1_MASK)
+
+#define CIU1_CIU_BBUD_CTRL_APB_DWORD_SEL_MASK    (0x2U)
+#define CIU1_CIU_BBUD_CTRL_APB_DWORD_SEL_SHIFT   (1U)
+/*! APB_DWORD_SEL - BBUD APB DWORD Select */
+#define CIU1_CIU_BBUD_CTRL_APB_DWORD_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_CTRL_APB_DWORD_SEL_SHIFT)) & CIU1_CIU_BBUD_CTRL_APB_DWORD_SEL_MASK)
+
+#define CIU1_CIU_BBUD_CTRL_BBUD_SPEC_SEL_MASK    (0x4U)
+#define CIU1_CIU_BBUD_CTRL_BBUD_SPEC_SEL_SHIFT   (2U)
+/*! BBUD_SPEC_SEL - BBUD SPEC CLK select */
+#define CIU1_CIU_BBUD_CTRL_BBUD_SPEC_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_CTRL_BBUD_SPEC_SEL_SHIFT)) & CIU1_CIU_BBUD_CTRL_BBUD_SPEC_SEL_MASK)
+
+#define CIU1_CIU_BBUD_CTRL_APB_EN_BBU2_MASK      (0x10U)
+#define CIU1_CIU_BBUD_CTRL_APB_EN_BBU2_SHIFT     (4U)
+/*! APB_EN_BBU2 - Enable BBUD2 APB Interface for Register Programming */
+#define CIU1_CIU_BBUD_CTRL_APB_EN_BBU2(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_CTRL_APB_EN_BBU2_SHIFT)) & CIU1_CIU_BBUD_CTRL_APB_EN_BBU2_MASK)
+
+#define CIU1_CIU_BBUD_CTRL_PPS_IN_SEL_MASK       (0x300U)
+#define CIU1_CIU_BBUD_CTRL_PPS_IN_SEL_SHIFT      (8U)
+/*! PPS_IN_SEL - BBUD PPS input select */
+#define CIU1_CIU_BBUD_CTRL_PPS_IN_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_CTRL_PPS_IN_SEL_SHIFT)) & CIU1_CIU_BBUD_CTRL_PPS_IN_SEL_MASK)
+
+#define CIU1_CIU_BBUD_CTRL_PTP_SYNC_PULSE_SEL_MASK (0x10000U)
+#define CIU1_CIU_BBUD_CTRL_PTP_SYNC_PULSE_SEL_SHIFT (16U)
+/*! PTP_SYNC_PULSE_SEL - Mux select control to select between */
+#define CIU1_CIU_BBUD_CTRL_PTP_SYNC_PULSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_CTRL_PTP_SYNC_PULSE_SEL_SHIFT)) & CIU1_CIU_BBUD_CTRL_PTP_SYNC_PULSE_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_BBUD_EXTRA_PORT - BBUD Extra Port Connection */
+/*! @{ */
+
+#define CIU1_CIU_BBUD_EXTRA_PORT_SOC_BBUD_EXTRA_MASK (0xFFU)
+#define CIU1_CIU_BBUD_EXTRA_PORT_SOC_BBUD_EXTRA_SHIFT (0U)
+/*! SOC_BBUD_EXTRA - SOC_BBUD_EXTRA[7:0] */
+#define CIU1_CIU_BBUD_EXTRA_PORT_SOC_BBUD_EXTRA(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_EXTRA_PORT_SOC_BBUD_EXTRA_SHIFT)) & CIU1_CIU_BBUD_EXTRA_PORT_SOC_BBUD_EXTRA_MASK)
+/*! @} */
+
+/*! @name CIU_BBUD_PTP_INTR_CTRL - PTP Input capture interrupt control */
+/*! @{ */
+
+#define CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_INTR_MASK_MASK (0x1U)
+#define CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_INTR_MASK_SHIFT (0U)
+/*! PTP_INPUTCAPTURE_INTR_MASK - Mask control for ptp_inputcaptue interrupt generation */
+#define CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_INTR_MASK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_INTR_MASK_SHIFT)) & CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_INTR_MASK_MASK)
+
+#define CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_EDGE_SEL_MASK (0x80U)
+#define CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_EDGE_SEL_SHIFT (7U)
+/*! PTP_INPUTCAPTURE_EDGE_SEL - Select edge for generation of PTP interrupt */
+#define CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_EDGE_SEL_SHIFT)) & CIU1_CIU_BBUD_PTP_INTR_CTRL_PTP_INPUTCAPTURE_EDGE_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_BBUD_ECO_CTRL - BBUD ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_BBUD_ECO_CTRL_ECO_BITS_MASK     (0xFFFFFFFFU)
+#define CIU1_CIU_BBUD_ECO_CTRL_ECO_BITS_SHIFT    (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_BBUD_ECO_CTRL_ECO_BITS(x)       (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_BBUD_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_BBUD_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_AIU_CTRL - AIU Control Register */
+/*! @{ */
+
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_EN_MASK   (0x4U)
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_EN_SHIFT  (2U)
+/*! AIU_MCLK_NCO_EN - AIU_MCLK NCO */
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_EN_SHIFT)) & CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_EN_MASK)
+
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_TYPE_MASK (0x8U)
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_TYPE_SHIFT (3U)
+/*! AIU_MCLK_NCO_TYPE - NCO */
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_TYPE_SHIFT)) & CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_TYPE_MASK)
+
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_INPUT_SEL_MASK (0x10U)
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_INPUT_SEL_SHIFT (4U)
+/*! AIU_MCLK_NCO_INPUT_SEL - AIU NCO Input */
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_INPUT_SEL_SHIFT)) & CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_INPUT_SEL_MASK)
+
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_SEL_MASK      (0x20U)
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_SEL_SHIFT     (5U)
+/*! AIU_MCLK_SEL - AIU MCLK */
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AIU_CTRL_AIU_MCLK_SEL_SHIFT)) & CIU1_CIU_AIU_CTRL_AIU_MCLK_SEL_MASK)
+
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_STEP_SIZE_MASK (0xFFFFFF00U)
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_STEP_SIZE_SHIFT (8U)
+/*! AIU_MCLK_NCO_STEP_SIZE - AIU NCO Step Size */
+#define CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_STEP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_STEP_SIZE_SHIFT)) & CIU1_CIU_AIU_CTRL_AIU_MCLK_NCO_STEP_SIZE_MASK)
+/*! @} */
+
+/*! @name CIU_AIU_ECO_CTRL - AIU ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_AIU_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_AIU_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_AIU_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_AIU_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_AIU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU_CBU_ECO_CTRL - CBU ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_CBU_ECO_CTRL_ECO_BITS_MASK      (0xFFFFFFFFU)
+#define CIU1_CIU_CBU_ECO_CTRL_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_CBU_ECO_CTRL_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CBU_ECO_CTRL_ECO_BITS_SHIFT)) & CIU1_CIU_CBU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU1_WR_MSG_TO_CPU3 - CPU1(WL) write message to CPU3(MCI) (0xAF0-0xAF4 IMU register access by CPU1) */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU1_WR_MSG_TO_CPU3_CPU1_WR_MSG_CPU3_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_IMU_CPU1_WR_MSG_TO_CPU3_CPU1_WR_MSG_CPU3_SHIFT (0U)
+/*! CPU1_WR_MSG_CPU3 - Write cpu1 message data to CPU3 (push to FIFO) */
+#define CIU1_CIU1_IMU_CPU1_WR_MSG_TO_CPU3_CPU1_WR_MSG_CPU3(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_WR_MSG_TO_CPU3_CPU1_WR_MSG_CPU3_SHIFT)) & CIU1_CIU1_IMU_CPU1_WR_MSG_TO_CPU3_CPU1_WR_MSG_CPU3_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU1_RD_MSG_FROM_CPU3 - cpu1 read message from CPU3 */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_CPU1_RD_MSG_CPU3_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_CPU1_RD_MSG_CPU3_SHIFT (0U)
+/*! CPU1_RD_MSG_CPU3 - cpu1 read message data from CPU3 (pop from FIFO) */
+#define CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_CPU1_RD_MSG_CPU3(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_CPU1_RD_MSG_CPU3_SHIFT)) & CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_CPU1_RD_MSG_CPU3_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS - cpu1 to CPU3 message FIFO status */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_LOCKED_MASK (0x1U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_LOCKED_SHIFT (0U)
+/*! CPU1_TO_CPU3_MSG_FIFO_LOCKED - cpu1_to_cpu3_msg_fifo_locked */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_LOCKED_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_LOCKED_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_ALMOST_FULL_MASK (0x2U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_ALMOST_FULL_SHIFT (1U)
+/*! CPU1_TO_CPU3_MSG_FIFO_ALMOST_FULL - cpu1_to_cpu3_msg_fifo_almost_full (based upon FIFO watermark) */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_ALMOST_FULL_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_ALMOST_FULL_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_FULL_MASK (0x4U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_FULL_SHIFT (2U)
+/*! CPU1_TO_CPU3_MSG_FIFO_FULL - cpu1_to_cpu3_msg_fifo_full (based upon FIFO depth) */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_FULL_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_FULL_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_EMPTY_MASK (0x8U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_EMPTY_SHIFT (3U)
+/*! CPU1_TO_CPU3_MSG_FIFO_EMPTY - cpu1_to_cpu3_msg_fifo_empty */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_EMPTY_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_EMPTY_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_COUNT_MASK (0x1F0U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_COUNT_SHIFT (4U)
+/*! CPU1_TO_CPU3_MSG_COUNT - cpu1_to_cpu3_msg_count */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_COUNT_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_COUNT_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_WR_PTR_MASK (0xF0000U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_WR_PTR_SHIFT (16U)
+/*! CPU1_TO_CPU3_MSG_FIFO_WR_PTR - cpu1 to cpu3 msg fifo write pointer for debug */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_WR_PTR_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_WR_PTR_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_RD_PTR_MASK (0xF00000U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_RD_PTR_SHIFT (20U)
+/*! CPU1_TO_CPU3_MSG_FIFO_RD_PTR - cpu1 to cpu3 msg fifo read pointer for debug */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_RD_PTR_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS_CPU1_TO_CPU3_MSG_FIFO_RD_PTR_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL - cpu1 to CPU3 message FIFO control */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_MASK (0x1U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_SHIFT (0U)
+/*! CPU1_MSG_RDY_INT_CLR - Writing 1 to this bit will clear message ready interrupt to CPU1 (self clear bit) */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_MASK (0x100U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_SHIFT (8U)
+/*! CPU1_MSG_SP_AV_INT_CLR - Writing 1 to this bit will clear message space available interrupt to CPU1 (self clear bit) */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FLUSH_MASK (0x10000U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FLUSH_SHIFT (16U)
+/*! CPU1_TO_CPU3_MSG_FIFO_FLUSH - Writing 1 to this bit will flush cpu1_to_cpu3 message fifo */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FLUSH_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FLUSH_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_MASK (0x20000U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_SHIFT (17U)
+/*! CPU1_WAIT_FOR_ACK - CPU1 Wait for Acknowledgment */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_MASK)
+
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FULL_WATERMARK_MASK (0xF00000U)
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FULL_WATERMARK_SHIFT (20U)
+/*! CPU1_TO_CPU3_MSG_FIFO_FULL_WATERMARK - cpu1_to_cpu3 message fifo full watermark (space avail intr based upon it) */
+#define CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FULL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FULL_WATERMARK_SHIFT)) & CIU1_CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL_CPU1_TO_CPU3_MSG_FIFO_FULL_WATERMARK_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG - CPU3 last message read (from cpu1) */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG_CPU3_RD_MSG_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG_CPU3_RD_MSG_SHIFT (0U)
+/*! CPU3_RD_MSG - CPU3 last message read (from cpu1) */
+#define CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG_CPU3_RD_MSG(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG_CPU3_RD_MSG_SHIFT)) & CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG_CPU3_RD_MSG_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU3_WR_MSG_TO_CPU1 - CPU3 write message to cpu1 (0xB04-0xB14 IMU register access by CPU3) */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU3_WR_MSG_TO_CPU1_CPU3_WR_MSG_CPU1_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_IMU_CPU3_WR_MSG_TO_CPU1_CPU3_WR_MSG_CPU1_SHIFT (0U)
+/*! CPU3_WR_MSG_CPU1 - Write CPU3 message data to cpu1 (push to FIFO) */
+#define CIU1_CIU1_IMU_CPU3_WR_MSG_TO_CPU1_CPU3_WR_MSG_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_WR_MSG_TO_CPU1_CPU3_WR_MSG_CPU1_SHIFT)) & CIU1_CIU1_IMU_CPU3_WR_MSG_TO_CPU1_CPU3_WR_MSG_CPU1_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU3_RD_MSG_FROM_CPU1 - CPU3 read message from cpu1 */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_CPU3_RD_MSG_CPU1_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_CPU3_RD_MSG_CPU1_SHIFT (0U)
+/*! CPU3_RD_MSG_CPU1 - CPU3 read message data from cpu1 (pop from FIFO) */
+#define CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_CPU3_RD_MSG_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_CPU3_RD_MSG_CPU1_SHIFT)) & CIU1_CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_CPU3_RD_MSG_CPU1_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS - CPU3 to cpu1 message FIFO status */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_LOCKED_MASK (0x1U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_LOCKED_SHIFT (0U)
+/*! CPU3_TO_CPU1_MSG_FIFO_LOCKED - cpu3_to_cpu1_msg_fifo_locked */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_LOCKED_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_LOCKED_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_ALMOST_FULL_MASK (0x2U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_ALMOST_FULL_SHIFT (1U)
+/*! CPU3_TO_CPU1_MSG_FIFO_ALMOST_FULL - cpu3_to_cpu1_msg_fifo_almost_full (based upon FIFO watermark) */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_ALMOST_FULL_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_ALMOST_FULL_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_FULL_MASK (0x4U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_FULL_SHIFT (2U)
+/*! CPU3_TO_CPU1_MSG_FIFO_FULL - cpu3_to_cpu1_msg_fifo_full (based upon FIFO depth) */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_FULL_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_FULL_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_EMPTY_MASK (0x8U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_EMPTY_SHIFT (3U)
+/*! CPU3_TO_CPU1_MSG_FIFO_EMPTY - cpu3_to_cpu1_msg_fifo_empty */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_EMPTY_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_EMPTY_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_COUNT_MASK (0x1F0U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_COUNT_SHIFT (4U)
+/*! CPU3_TO_CPU1_MSG_COUNT - cpu3_to_cpu1_msg_count */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_COUNT_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_COUNT_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_WR_PTR_MASK (0xF0000U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_WR_PTR_SHIFT (16U)
+/*! CPU3_TO_CPU1_MSG_FIFO_WR_PTR - cpu3 to cpu1 msg fifo write pointer for debug */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_WR_PTR_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_WR_PTR_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_RD_PTR_MASK (0xF00000U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_RD_PTR_SHIFT (20U)
+/*! CPU3_TO_CPU1_MSG_FIFO_RD_PTR - cpu3 to cpu1 msg fifo read pointer for debug */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_RD_PTR_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS_CPU3_TO_CPU1_MSG_FIFO_RD_PTR_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL - CPU3 to cpu1 message FIFO control */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_MASK (0x1U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_SHIFT (0U)
+/*! CPU3_MSG_RDY_INT_CLR - Writing 1 to this bit will clear message ready interrupt to cpu3 (self clear bit) */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_MASK (0x100U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_SHIFT (8U)
+/*! CPU3_MSG_SP_AV_INT_CLR - Writing 1 to this bit will clear message space available interrupt to CPU3 (self clear bit) */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FLUSH_MASK (0x10000U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FLUSH_SHIFT (16U)
+/*! CPU3_TO_CPU1_MSG_FIFO_FLUSH - Writing 1 to this bit will flush cpu3_to_cpu1 message fifo */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FLUSH_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FLUSH_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_MASK (0x20000U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_SHIFT (17U)
+/*! CPU3_WAIT_FOR_ACK - CPU3 Wait for Acknowledgment */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_MASK)
+
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FULL_WATERMARK_MASK (0xF00000U)
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FULL_WATERMARK_SHIFT (20U)
+/*! CPU3_TO_CPU1_MSG_FIFO_FULL_WATERMARK - cpu3_to_cpu1 message fifo full watermark (space avail intr based upon it) */
+#define CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FULL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FULL_WATERMARK_SHIFT)) & CIU1_CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL_CPU3_TO_CPU1_MSG_FIFO_FULL_WATERMARK_MASK)
+/*! @} */
+
+/*! @name CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG - cpu1 last message read (from cpu3) */
+/*! @{ */
+
+#define CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG_CPU1_RD_MSG_MASK (0xFFFFFFFFU)
+#define CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG_CPU1_RD_MSG_SHIFT (0U)
+/*! CPU1_RD_MSG - cpu1 last message read (from cpu3) */
+#define CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG_CPU1_RD_MSG(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG_CPU1_RD_MSG_SHIFT)) & CIU1_CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG_CPU1_RD_MSG_MASK)
+/*! @} */
+
+/*! @name CIU_CPU1_CPU3_MSG_CTRL - CPU1_CPU3 message register */
+/*! @{ */
+
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_RDY_MASK (0x1U)
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_RDY_SHIFT (0U)
+/*! CPU1_TO_CPU3_MSG_RDY - CPU1 Message for CPU3 is ready. This is self clearing bit. The CPU1
+ *    writes 1 to indicate that message for CPU3 is ready. This generates an Interrupt to CPU3 via APU.
+ *    This is old schema and we should use IMU based scheme.
+ */
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_RDY(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_RDY_SHIFT)) & CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_RDY_MASK)
+
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_RDY_MASK (0x2U)
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_RDY_SHIFT (1U)
+/*! CPU3_TO_CPU1_MSG_RDY - CPU3 Message for CPU1 is ready. This is self clearing bit. The CPU3
+ *    writes 1 to indicate that message for CPU1 is ready. This generates an Interrupt to CPU1 via APU.
+ *    This is old schema and we should use IMU based scheme.
+ */
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_RDY(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_RDY_SHIFT)) & CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_RDY_MASK)
+
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_PROCESS_DONE_MASK (0x100U)
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_PROCESS_DONE_SHIFT (8U)
+/*! CPU1_TO_CPU3_MSG_PROCESS_DONE - CPU1 Message for CPU3 has been read by CPU3 and executed. This
+ *    is self clearing bit. The CPU3 writes 1 to indicate that message sent by CPU1 is executed. This
+ *    generates an Interrupt to CPU1 via CIU1.
+ */
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_PROCESS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_PROCESS_DONE_SHIFT)) & CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU1_TO_CPU3_MSG_PROCESS_DONE_MASK)
+
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_PROCESS_DONE_MASK (0x200U)
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_PROCESS_DONE_SHIFT (9U)
+/*! CPU3_TO_CPU1_MSG_PROCESS_DONE - CPU3 Message for CPU1 has been read by CPU1 and executed. This
+ *    is self clearing bit. The CPU1 writes 1 to indicate that message send by CPU3 is executed. This
+ *    generates an Interrupt to CPU3 via CIU1.
+ */
+#define CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_PROCESS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_PROCESS_DONE_SHIFT)) & CIU1_CIU_CPU1_CPU3_MSG_CTRL_CPU3_TO_CPU1_MSG_PROCESS_DONE_MASK)
+/*! @} */
+
+/*! @name CIU1_CPU3_WAKEUP_CTRL - CIU1 register to wakeup CPU3 */
+/*! @{ */
+
+#define CIU1_CIU1_CPU3_WAKEUP_CTRL_CPU3_WAKEUP_CTRL_MASK (0x1U)
+#define CIU1_CIU1_CPU3_WAKEUP_CTRL_CPU3_WAKEUP_CTRL_SHIFT (0U)
+/*! CPU3_WAKEUP_CTRL - CPU3 Wakeup Control Register. S/W Write 1 to generate a wake up interrupt to
+ *    CPU3.Clear by S/W once mci_wl_wakeup_done[1] interrupt is received from CPU3.
+ */
+#define CIU1_CIU1_CPU3_WAKEUP_CTRL_CPU3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU3_WAKEUP_CTRL_CPU3_WAKEUP_CTRL_SHIFT)) & CIU1_CIU1_CPU3_WAKEUP_CTRL_CPU3_WAKEUP_CTRL_MASK)
+/*! @} */
+
+/*! @name CIU1_CPU1_WAKEUP_DONE - Wakeup done Control Register to CPU3 */
+/*! @{ */
+
+#define CIU1_CIU1_CPU1_WAKEUP_DONE_CPU1_WAKEUP_DONE_MASK (0xFFU)
+#define CIU1_CIU1_CPU1_WAKEUP_DONE_CPU1_WAKEUP_DONE_SHIFT (0U)
+/*! CPU1_WAKEUP_DONE - CPU1 Wakeup is done . This bit is set to 1 by S/W when CPU3 wakesup CPU1.This
+ *    is self clearing bit. This generates an interrupt to CPU3 via wl_mci_wakeup_done[7:0] signal.
+ */
+#define CIU1_CIU1_CPU1_WAKEUP_DONE_CPU1_WAKEUP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU1_WAKEUP_DONE_CPU1_WAKEUP_DONE_SHIFT)) & CIU1_CIU1_CPU1_WAKEUP_DONE_CPU1_WAKEUP_DONE_MASK)
+/*! @} */
+
+/*! @name CIU1_CPU3_NS_GP_INT - Non Secure region GP interrupt to CPU3 */
+/*! @{ */
+
+#define CIU1_CIU1_CPU3_NS_GP_INT_CPU1_CPU3_GP_NS_INT_MASK (0x3U)
+#define CIU1_CIU1_CPU3_NS_GP_INT_CPU1_CPU3_GP_NS_INT_SHIFT (0U)
+/*! CPU1_CPU3_GP_NS_INT - General Purpose interrupt to CPU3 from non secure registers */
+#define CIU1_CIU1_CPU3_NS_GP_INT_CPU1_CPU3_GP_NS_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU1_CIU1_CPU3_NS_GP_INT_CPU1_CPU3_GP_NS_INT_SHIFT)) & CIU1_CIU1_CPU3_NS_GP_INT_CPU1_CPU3_GP_NS_INT_MASK)
+/*! @} */
+
+/*! @name CIU_IMU_ECO_BITS - IMU ECO Control */
+/*! @{ */
+
+#define CIU1_CIU_IMU_ECO_BITS_ECO_BITS_MASK      (0xFFFFU)
+#define CIU1_CIU_IMU_ECO_BITS_ECO_BITS_SHIFT     (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define CIU1_CIU_IMU_ECO_BITS_ECO_BITS(x)        (((uint32_t)(((uint32_t)(x)) << CIU1_CIU_IMU_ECO_BITS_ECO_BITS_SHIFT)) & CIU1_CIU_IMU_ECO_BITS_ECO_BITS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CIU1_Register_Masks */
+
+
+/* CIU1 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral WLCTRL base address */
+  #define WLCTRL_BASE                              (0x51240000u)
+  /** Peripheral WLCTRL base address */
+  #define WLCTRL_BASE_NS                           (0x41240000u)
+  /** Peripheral WLCTRL base pointer */
+  #define WLCTRL                                   ((CIU1_Type *)WLCTRL_BASE)
+  /** Peripheral WLCTRL base pointer */
+  #define WLCTRL_NS                                ((CIU1_Type *)WLCTRL_BASE_NS)
+  /** Array initializer of CIU1 peripheral base addresses */
+  #define CIU1_BASE_ADDRS                          { WLCTRL_BASE }
+  /** Array initializer of CIU1 peripheral base pointers */
+  #define CIU1_BASE_PTRS                           { WLCTRL }
+  /** Array initializer of CIU1 peripheral base addresses */
+  #define CIU1_BASE_ADDRS_NS                       { WLCTRL_BASE_NS }
+  /** Array initializer of CIU1 peripheral base pointers */
+  #define CIU1_BASE_PTRS_NS                        { WLCTRL_NS }
+#else
+  /** Peripheral WLCTRL base address */
+  #define WLCTRL_BASE                              (0x41240000u)
+  /** Peripheral WLCTRL base pointer */
+  #define WLCTRL                                   ((CIU1_Type *)WLCTRL_BASE)
+  /** Array initializer of CIU1 peripheral base addresses */
+  #define CIU1_BASE_ADDRS                          { WLCTRL_BASE }
+  /** Array initializer of CIU1 peripheral base pointers */
+  #define CIU1_BASE_PTRS                           { WLCTRL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CIU1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CIU2 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CIU2_Peripheral_Access_Layer CIU2 Peripheral Access Layer
+ * @{
+ */
+
+/** CIU2 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CIU2_CLK_ENABLE;                   /**< Clock enable, offset: 0x0 */
+  __IO uint32_t CIU2_ECO_0;                        /**< ECO Register 0, offset: 0x4 */
+  __IO uint32_t CIU2_ECO_1;                        /**< ECO Register 1, offset: 0x8 */
+  __IO uint32_t CIU2_ECO_2;                        /**< ECO Register 2, offset: 0xC */
+  __IO uint32_t CIU2_ECO_3;                        /**< ECO Register 3, offset: 0x10 */
+  __IO uint32_t CIU2_ECO_4;                        /**< ECO Register 4, offset: 0x14 */
+  __IO uint32_t CIU2_ECO_5;                        /**< ECO Register 5, offset: 0x18 */
+  __IO uint32_t CIU2_ECO_6;                        /**< ECO Register 6, offset: 0x1C */
+  __IO uint32_t CIU2_ECO_7;                        /**< ECO Register 7, offset: 0x20 */
+  __IO uint32_t CIU2_ECO_8;                        /**< ECO Register 8, offset: 0x24 */
+  __IO uint32_t CIU2_ECO_9;                        /**< ECO Register 9, offset: 0x28 */
+  __IO uint32_t CIU2_ECO_10;                       /**< ECO Register 10, offset: 0x2C */
+  __IO uint32_t CIU2_ECO_11;                       /**< ECO Register 11, offset: 0x30 */
+  __IO uint32_t CIU2_ECO_12;                       /**< ECO Register 12, offset: 0x34 */
+  __IO uint32_t CIU2_ECO_13;                       /**< ECO Register 13, offset: 0x38 */
+  __IO uint32_t CIU2_ECO_14;                       /**< ECO Register 14, offset: 0x3C */
+  __IO uint32_t CIU2_ECO_15;                       /**< ECO Register 15, offset: 0x40 */
+       uint8_t RESERVED_0[188];
+  __IO uint32_t CIU2_CLK_ENABLE4;                  /**< Clock Enable 4, offset: 0x100 */
+  __IO uint32_t CIU2_CLK_ENABLE5;                  /**< Clock Enable 5, offset: 0x104 */
+  __IO uint32_t CIU2_CLK_CPU2CLK_CTRL;             /**< CPU2_AHB2 Clock Control, offset: 0x108 */
+  __IO uint32_t CIU2_CLK_UARTCLK_CTRL;             /**< UART Clock Control, offset: 0x10C */
+  __IO uint32_t CIU2_CLK_LBU2_BTRTU1_CTRL;         /**< LBU2 BT_RTU1 Clock Control, offset: 0x110 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t CIU2_CLK_CP15_DIS3;                /**< Clock Auto Shut-off Enable3, offset: 0x118 */
+  __IO uint32_t CIU2_RST_SW3;                      /**< Software Module Reset, offset: 0x11C */
+  __IO uint32_t CIU2_MEM_WRTC3;                    /**< Memory WRTC Control 3, offset: 0x120 */
+  __IO uint32_t CIU2_MEM_WRTC4;                    /**< Memory WRTC Control 4, offset: 0x124 */
+  __IO uint32_t CIU2_MEM_PWDN3;                    /**< Memory Power down Control, offset: 0x128 */
+  __I  uint32_t CIU2_SOC_AHB2APB_STATUS;           /**< SOC AHB2APB Status, offset: 0x12C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t CIU2_BLE_CTRL;                     /**< BLE Control and Status, offset: 0x140 */
+  __I  uint32_t CIU2_AHB2_TO_LAST_ADDR;            /**< AHB2 Timeout Last Address, offset: 0x144 */
+  __I  uint32_t CIU2_AHB2_TO_CUR_ADDR;             /**< AHB2 Current Timeout Address, offset: 0x148 */
+  __IO uint32_t CIU2_AHB2_TO_CTRL;                 /**< AHB2 ARB Control, offset: 0x14C */
+  __IO uint32_t CIU2_AHB2_SMU1_ACCESS_ADDR;        /**< AHB2 to SMU1 Accessible Address, offset: 0x150 */
+  __IO uint32_t CIU2_AHB2_SMU1_ACCESS_MASK;        /**< AHB2 to SMU1 Accessible Mask, offset: 0x154 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t CIU2_CPU2_ICODE_INV_ADDR_CTRL;     /**< CPU2 Icode invalid address access control, offset: 0x15C */
+  __I  uint32_t CIU2_CPU2_ICODE_INV_ADDR;          /**< CPU2 Icode invalid address, offset: 0x160 */
+  __IO uint32_t CIU2_CPU2_DCODE_INV_ADDR_CTRL;     /**< CPU2 Dcode invalid address access control, offset: 0x164 */
+  __I  uint32_t CIU2_CPU2_DCODE_INV_ADDR;          /**< CPU2 Dcode invalid address, offset: 0x168 */
+  __IO uint32_t CIU2_CPU_CPU2_CTRL;                /**< CPU2 control register, offset: 0x16C */
+  __IO uint32_t CIU2_BRF_CTRL;                     /**< BRF Control and Status, offset: 0x170 */
+  __IO uint32_t CIU2_BRF_EXTRA_PORT;               /**< BRF Extra Port Connection, offset: 0x174 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t CIU2_BRF_ECO_CTRL;                 /**< BRF ECO Control, offset: 0x17C */
+  __IO uint32_t CIU2_BTU_CTRL;                     /**< BTU Control and Status, offset: 0x180 */
+  __IO uint32_t CIU2_BT_PS;                        /**< BT Clock Power Save, offset: 0x184 */
+  __IO uint32_t CIU2_BT_PS2;                       /**< BT Clock Power Save 2, offset: 0x188 */
+  __IO uint32_t CIU2_BT_REF_CTRL;                  /**< BT Ref Control, offset: 0x18C */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t CIU2_BT_PS3;                       /**< BT Clock Power Save 3, offset: 0x194 */
+  __IO uint32_t CIU2_BTU_ECO_CTRL;                 /**< BTU ECO Control, offset: 0x198 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t CIU2_INT_MASK;                     /**< CIU2 Interrupt Mask, offset: 0x1A0 */
+  __IO uint32_t CIU2_INT_SELECT;                   /**< CIU2 Interrupt Select, offset: 0x1A4 */
+  __IO uint32_t CIU2_INT_EVENT_MASK;               /**< CIU2 Interrupt Event Mask, offset: 0x1A8 */
+  __I  uint32_t CIU2_INT_STATUS;                   /**< CIU2 Interrupt Status, offset: 0x1AC */
+  __IO uint32_t CPU2_ERR_INT_MASK;                 /**< CPU2 ERR Interrupt Mask, offset: 0x1B0 */
+  __IO uint32_t CPU2_ERR_INT_SELECT;               /**< CPU2 ERR Interrupt Clear Select, offset: 0x1B4 */
+  __IO uint32_t CPU2_ERR_INT_EVENT_MASK;           /**< CPU2 ERR Interrupt Event Mask, offset: 0x1B8 */
+  __I  uint32_t CPU2_ERR_INT_STATUS;               /**< CPU2 ERR Interrupt Status, offset: 0x1BC */
+       uint8_t RESERVED_7[64];
+  __IO uint32_t CIU2_BCA1_CPU2_INT_MASK;           /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */
+  __IO uint32_t CIU2_BCA1_CPU2_INT_SELECT;         /**< BCA1 to CPU2 Interrupt Select, offset: 0x204 */
+  __IO uint32_t CIU2_BCA1_CPU2_INT_EVENT_MASK;     /**< BCA1 to CPU2 Interrupt Event Mask, offset: 0x208 */
+  __I  uint32_t CIU2_BCA1_CPU2_INT_STATUS;         /**< BCA1 to CPU2 Interrupt Status, offset: 0x20C */
+  __IO uint32_t CIU2_APU_BYPASS1;                  /**< CIU2 APU Bypass Register 1, offset: 0x210 */
+  __IO uint32_t CIU2_CPU2_LMU_STA_BYPASS0;         /**< LMU static bank control byapss0 Register for CPU2 mem, offset: 0x214 */
+  __IO uint32_t CIU2_CPU2_LMU_STA_BYPASS1;         /**< LMU static bank control byapss1 Register for CPU2, offset: 0x218 */
+  __IO uint32_t CIU2_CPU2_LMU_STA_BYPASS2;         /**< LMU static bank byapss2 Register for CPU2, offset: 0x21C */
+  __IO uint32_t CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS;  /**< LMU G2Bist control bypass Register for CPU2, offset: 0x220 */
+       uint8_t RESERVED_8[8];
+  __IO uint32_t CIU2_APU_PWR_CTRL_BYPASS1;         /**< APU power control Bypass Register 1, offset: 0x22C */
+  __IO uint32_t CIU2_AHB2AHB_BRIDGE_CTRL;          /**< AHB2AHB Bridge Control Register, offset: 0x230 */
+  __IO uint32_t CIU2_CLK_CP15_DIS1;                /**< Clock Auto Shut-off Enable1, offset: 0x234 */
+  __IO uint32_t CIU_CLK_RTU_NCO_CTRL;              /**< RTU NCO Clock Control, offset: 0x238 */
+  __IO uint32_t CIU_CLK_SOCCLK_CTRL;               /**< SOC Clock Control, offset: 0x23C */
+  __IO uint32_t CIU_CLK_SLEEPCLK_CTRL;             /**< Sleep Clock Control, offset: 0x240 */
+  __IO uint32_t CIU_CLK_SLEEPCLK_CTRL2;            /**< Sleep Clock Control 2, offset: 0x244 */
+       uint8_t RESERVED_9[8];
+  __IO uint32_t CIU2_IOMUX_MODE_CTRL;              /**< Test Bus Select, offset: 0x250 */
+  __IO uint32_t CIU2_RST_SW2;                      /**< Software Module Reset, offset: 0x254 */
+       uint8_t RESERVED_10[8];
+  __IO uint32_t CIU2_AHB2_TO_CLEAR;                /**< AHB2 timeout logic clear register, offset: 0x260 */
+  __IO uint32_t CIU2_CPU_DYN_CLK_CTRL;             /**< Dynamic CPU Clock Control, offset: 0x264 */
+  __I  uint32_t CPU2_DBG_STAT;                     /**< CPU2 debug register, offset: 0x268 */
+  __I  uint32_t BTSS_MBIST_STAT;                   /**< offset: 0x26C */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t CIU2_TEST_MODE;                    /**< ", offset: 0x274 */
+       uint8_t RESERVED_12[4];
+  __IO uint32_t CIU2_APU_BYPASS2;                  /**< CIU2 APU Bypass Register 2, offset: 0x27C */
+  __I  uint32_t CIU2_TST_G2BIST_STATUS;            /**< WL G2BIST Status, offset: 0x280 */
+  __IO uint32_t CIU2_LPO_CLK_GEN_CTRL;             /**< BLE LPO CLK GEN Control, offset: 0x284 */
+  __I  uint32_t CIU2_LPO_CLK_GEN_STATUS;           /**< BLE LPO CLK GEN Status, offset: 0x288 */
+  __IO uint32_t CIU2_LPO_SLP_CLK_GEN_CTRL;         /**< ", offset: 0x28C */
+  __IO uint32_t CPU2_INT_CTRL;                     /**< ", offset: 0x290 */
+  __I  uint32_t CIU2_BRF_EXTRA_PORT_STATUS;        /**< ", offset: 0x294 */
+  __I  uint32_t CIU2_DEBUG;                        /**< ", offset: 0x298 */
+       uint8_t RESERVED_13[100];
+  __IO uint32_t CIU2_MCI_EXTRA;                    /**< MCI EXTRA Ports, offset: 0x300 */
+  __IO uint32_t CIU2_TSTBUS_SEL;                   /**< Test Bus Select, offset: 0x304 */
+  __IO uint32_t FFU_CTRL;                          /**< FFU Specific Control Register, offset: 0x308 */
+       uint8_t RESERVED_14[116];
+  __IO uint32_t BLE_RAACS_CTRL;                    /**< RAACS control registers, offset: 0x380 */
+  __IO uint32_t BLE_RAACS_PERFORMANCE_STATISTICS;  /**< RAACS performance statistics counter., offset: 0x384 */
+       uint8_t RESERVED_15[1832056];
+  __IO uint32_t CIU2_CPU_CPU2_MSG_CTRL;            /**< CPU2 message register, offset: 0x1BF800 */
+  __IO uint32_t CIU2_IMU_CPU3_WR_MSG_TO_CPU2;      /**< CPU3 write message to CPU2, offset: 0x1BF804 */
+  __I  uint32_t CIU2_IMU_CPU3_RD_MSG_FROM_CPU2;    /**< CPU3 read message from CPU2, offset: 0x1BF808 */
+  __I  uint32_t CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS; /**< CPU3 to CPU2 message FIFO status, offset: 0x1BF80C */
+  __IO uint32_t CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL;  /**< CPU3 to CPU2 message FIFO control, offset: 0x1BF810 */
+  __I  uint32_t CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG; /**< CPU2 last message read (from cpu3), offset: 0x1BF814 */
+  __IO uint32_t CIU2_IMU_CPU2_WR_MSG_TO_CPU3;      /**< CPU2 write message to CPU3, offset: 0x1BF818 */
+  __I  uint32_t CIU2_IMU_CPU2_RD_MSG_FROM_CPU3;    /**< CPU2 read message from CPU3, offset: 0x1BF81C */
+  __I  uint32_t CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS; /**< CPU2 to CPU3 message FIFO status, offset: 0x1BF820 */
+  __IO uint32_t CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL;  /**< CPU2 to CPU3 message FIFO control, offset: 0x1BF824 */
+  __I  uint32_t CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG; /**< CPU3 last message read (from cpu2), offset: 0x1BF828 */
+  __IO uint32_t CIU2_CPU3_WAKEUP_CTRL;             /**< CIU2 register to wakeup CPU3, offset: 0x1BF82C */
+  __IO uint32_t CIU2_CPU2_WAKEUP_DONE;             /**< Wakeup done Control Register to CPU3, offset: 0x1BF830 */
+  __IO uint32_t CIU2_CPU3_NS_GP_INT;               /**< Non Secure region GP interrupt to CPU3, offset: 0x1BF834 */
+  __IO uint32_t CIU2_IMU_ECO_BITS;                 /**< IMU ECO Control, offset: 0x1BF838 */
+} CIU2_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CIU2 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CIU2_Register_Masks CIU2 Register Masks
+ * @{
+ */
+
+/*! @name CIU2_CLK_ENABLE - Clock enable */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_ENABLE_CIU2_AHB2APB_CLK_EN_MASK (0x40000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU2_AHB2APB_CLK_EN_SHIFT (18U)
+/*! CIU2_AHB2APB_CLK_EN - Enable AHB2APB HCLK */
+#define CIU2_CIU2_CLK_ENABLE_CIU2_AHB2APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU2_AHB2APB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU2_AHB2APB_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU2_MCI_A2A_CLK_EN_MASK (0x80000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU2_MCI_A2A_CLK_EN_SHIFT (19U)
+/*! CIU2_MCI_A2A_CLK_EN - Enable AHB2 Clock to A2A in MCI */
+#define CIU2_CIU2_CLK_ENABLE_CIU2_MCI_A2A_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU2_MCI_A2A_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU2_MCI_A2A_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU2_FP4_SLP_CLK_EN_MASK (0x100000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU2_FP4_SLP_CLK_EN_SHIFT (20U)
+/*! CIU2_FP4_SLP_CLK_EN - Enable FFU Sleep Clock */
+#define CIU2_CIU2_CLK_ENABLE_CIU2_FP4_SLP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU2_FP4_SLP_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU2_FP4_SLP_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU2_FFU_OSC_CLK_EN_MASK (0x200000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU2_FFU_OSC_CLK_EN_SHIFT (21U)
+/*! CIU2_FFU_OSC_CLK_EN - Enable FFU Oscillator Clock */
+#define CIU2_CIU2_CLK_ENABLE_CIU2_FFU_OSC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU2_FFU_OSC_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU2_FFU_OSC_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU_SOCCIU_A2A_CLK_EN_MASK (0x400000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU_SOCCIU_A2A_CLK_EN_SHIFT (22U)
+/*! CIU_SOCCIU_A2A_CLK_EN - Enable AHB2 Clock to A2A in SOCCIU */
+#define CIU2_CIU2_CLK_ENABLE_CIU_SOCCIU_A2A_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU_SOCCIU_A2A_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU_SOCCIU_A2A_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU_MSC_A2A_CLK_EN_MASK (0x800000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU_MSC_A2A_CLK_EN_SHIFT (23U)
+/*! CIU_MSC_A2A_CLK_EN - Enable AHB2 Clock to A2A in MSC */
+#define CIU2_CIU2_CLK_ENABLE_CIU_MSC_A2A_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU_MSC_A2A_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU_MSC_A2A_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_DVFS_CLK_EN_MASK (0x1000000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_DVFS_CLK_EN_SHIFT (24U)
+/*! CIU_BTAPU_DVFS_CLK_EN - APU DVFS Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_DVFS_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_DVFS_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_DVFS_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_AHB_CLK_EN_MASK (0x2000000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_AHB_CLK_EN_SHIFT (25U)
+/*! CIU_BTAPU_AHB_CLK_EN - APU AHB Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_AHB_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_SLPCLK_EN_MASK (0x4000000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_SLPCLK_EN_SHIFT (26U)
+/*! CIU_BTAPU_SLPCLK_EN - APU Sleep Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_SLPCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_SLPCLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_SLPCLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_CAL_CLK_EN_MASK (0x8000000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_CAL_CLK_EN_SHIFT (27U)
+/*! CIU_BTAPU_CAL_CLK_EN - APU Calibration Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_CAL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_CAL_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_CAL_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_REF_CLK_EN_MASK (0x10000000U)
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_REF_CLK_EN_SHIFT (28U)
+/*! CIU_BTAPU_REF_CLK_EN - APU Reference Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_REF_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_REF_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CIU_BTAPU_REF_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_MASK (0x20000000U)
+#define CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_SHIFT (29U)
+/*! AHB2_CLK_ENABLE - Clock ahb2_clk enable signal. Ahb2_clk enable. 1: enable, 0: disable */
+#define CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_SHIFT)) & CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_MASK (0x40000000U)
+#define CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_SHIFT (30U)
+/*! CPU1_DIV_CLK_ENABLE - Clock cpu1_div_clk enable signal. cpu1_div_clk enable. 1: enable, 0: disable */
+#define CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_MASK (0x80000000U)
+#define CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_SHIFT (31U)
+/*! SOC_AHB_CLK_SEL - Clock selection for soc_ahb_clk. 0: AHB2_CLK, 1: CPU1_CLK_DIV */
+#define CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_SHIFT)) & CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_0 - ECO Register 0 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_0_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_0_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_0_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_0_SPARE_SHIFT)) & CIU2_CIU2_ECO_0_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_1 - ECO Register 1 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_1_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_1_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_1_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_1_SPARE_SHIFT)) & CIU2_CIU2_ECO_1_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_2 - ECO Register 2 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_2_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_2_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_2_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_2_SPARE_SHIFT)) & CIU2_CIU2_ECO_2_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_3 - ECO Register 3 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_3_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_3_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_3_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_3_SPARE_SHIFT)) & CIU2_CIU2_ECO_3_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_4 - ECO Register 4 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_4_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_4_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_4_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_4_SPARE_SHIFT)) & CIU2_CIU2_ECO_4_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_5 - ECO Register 5 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_5_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_5_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_5_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_5_SPARE_SHIFT)) & CIU2_CIU2_ECO_5_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_6 - ECO Register 6 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_6_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_6_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_6_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_6_SPARE_SHIFT)) & CIU2_CIU2_ECO_6_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_7 - ECO Register 7 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_7_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_7_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_7_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_7_SPARE_SHIFT)) & CIU2_CIU2_ECO_7_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_8 - ECO Register 8 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_8_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_8_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_8_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_8_SPARE_SHIFT)) & CIU2_CIU2_ECO_8_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_9 - ECO Register 9 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_9_SPARE_MASK               (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_9_SPARE_SHIFT              (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_9_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_9_SPARE_SHIFT)) & CIU2_CIU2_ECO_9_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_10 - ECO Register 10 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_10_SPARE_MASK              (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_10_SPARE_SHIFT             (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_10_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_10_SPARE_SHIFT)) & CIU2_CIU2_ECO_10_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_11 - ECO Register 11 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_11_SPARE_MASK              (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_11_SPARE_SHIFT             (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_11_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_11_SPARE_SHIFT)) & CIU2_CIU2_ECO_11_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_12 - ECO Register 12 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_12_SPARE_MASK              (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_12_SPARE_SHIFT             (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_12_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_12_SPARE_SHIFT)) & CIU2_CIU2_ECO_12_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_13 - ECO Register 13 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_13_SPARE_MASK              (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_13_SPARE_SHIFT             (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_13_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_13_SPARE_SHIFT)) & CIU2_CIU2_ECO_13_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_14 - ECO Register 14 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_14_SPARE_MASK              (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_14_SPARE_SHIFT             (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_14_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_14_SPARE_SHIFT)) & CIU2_CIU2_ECO_14_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_ECO_15 - ECO Register 15 */
+/*! @{ */
+
+#define CIU2_CIU2_ECO_15_SPARE_MASK              (0xFFFFFFFFU)
+#define CIU2_CIU2_ECO_15_SPARE_SHIFT             (0U)
+/*! SPARE - Eco Reserve Register */
+#define CIU2_CIU2_ECO_15_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_15_SPARE_SHIFT)) & CIU2_CIU2_ECO_15_SPARE_MASK)
+/*! @} */
+
+/*! @name CIU2_CLK_ENABLE4 - Clock Enable 4 */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_MASK (0x1U)
+#define CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_SHIFT (0U)
+/*! BIST_AHB2_CLK_GATING_EN - CPU2 bist Clock for IMEM/DMEM/SMU2/EBRAM/ROM */
+#define CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_MASK (0x2U)
+#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_SHIFT (1U)
+/*! BRU_AHB2_ADDR_MASK_DIS - CPU2 ROM Address Mask Selection */
+#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_MASK (0x4U)
+#define CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_SHIFT (2U)
+/*! ITCM_AHB2_DYN_CLK_GATING_DIS - CPU2 ITCM Dynamic Clock Gating Feature */
+#define CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_MASK (0x8U)
+#define CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_SHIFT (3U)
+/*! DTCM_AHB2_DYN_CLK_GATING_DIS - CPU2 DTCM Dynamic Clock Gating Feature */
+#define CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_MASK (0x10U)
+#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_SHIFT (4U)
+/*! BRU_AHB2_DYN_CLK_GATING_DIS - CPU2 ROM Dynamic Clock Gating Feature */
+#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_MASK (0x20U)
+#define CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_SHIFT (5U)
+/*! SMU2_DYN_CLK_GATING_DIS - SMU2 Dynamic Clock Gating Feature */
+#define CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_MASK (0x100U)
+#define CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_SHIFT (8U)
+/*! EBRAM_BIST_CLK_EN - EBRAM BIST Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_MASK    (0x200U)
+#define CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_SHIFT   (9U)
+/*! BT_ECLK_EN - BTU EBC Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_MASK   (0x400U)
+#define CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_SHIFT  (10U)
+/*! BT_4MCLK_EN - BTU 4 MHz Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_MASK (0x2000U)
+#define CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_SHIFT (13U)
+/*! BTU_AHB_CLK_EN - BTU AHB Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_MASK    (0x4000U)
+#define CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_SHIFT   (14U)
+/*! SIU_CLK_EN - BT SIU (UART) clock enable */
+#define CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_MASK (0x10000U)
+#define CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_SHIFT (16U)
+/*! SMU2_AHB_CLK_EN - SMU2 AHB Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_MASK (0x80000U)
+#define CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_SHIFT (19U)
+/*! HPU2_CIU_CLK_EN - HPU2 CIU Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_MASK (0x100000U)
+#define CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_SHIFT (20U)
+/*! BLE_AHB_CLK_EN - BLE ARM Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_MASK (0x200000U)
+#define CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_SHIFT (21U)
+/*! BLE_SYS_CLK_EN - BLE SYS Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_MASK (0x400000U)
+#define CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_SHIFT (22U)
+/*! BLE_AEU_CLK_EN - BT/BLE AEU Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_MASK (0x800000U)
+#define CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_SHIFT (23U)
+/*! BT_16M_CLK_EN - BT 16MHz Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_MASK   (0x1000000U)
+#define CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_SHIFT  (24U)
+/*! DBUS_CLK_EN - BLE DBUS Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_MASK (0x20000000U)
+#define CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_SHIFT (29U)
+/*! SIU_AHB2_CLK_EN - BT SIU (UART) AHB clock enable */
+#define CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_MASK (0x40000000U)
+#define CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_SHIFT (30U)
+/*! BTRTU1_CLK_EN - BT RTU1 clock enable */
+#define CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_MASK)
+/*! @} */
+
+/*! @name CIU2_CLK_ENABLE5 - Clock Enable 5 */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_MASK (0x7U)
+#define CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_SHIFT (0U)
+/*! ITCM_AHB2_CLK_EN - Enable CPU2 ITCM Banks 1-2 */
+#define CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_CIU2_FFU_AHB_CLK_EN_MASK (0x40U)
+#define CIU2_CIU2_CLK_ENABLE5_CIU2_FFU_AHB_CLK_EN_SHIFT (6U)
+/*! CIU2_FFU_AHB_CLK_EN - Enable for AHB Clock to FFU */
+#define CIU2_CIU2_CLK_ENABLE5_CIU2_FFU_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CIU2_FFU_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CIU2_FFU_AHB_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_MASK (0x80U)
+#define CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_SHIFT (7U)
+/*! CIU2_REG_CLK_EN - CIU2 Reg Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_MASK (0x7FFF00U)
+#define CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_SHIFT (8U)
+/*! BR_AHB2_CLK_EN - CPU2 BROM AHB Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_MASK   (0x800000U)
+#define CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_SHIFT  (23U)
+/*! BTU_MCLK_EN - BTU MCLK Enable */
+#define CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_MASK (0x3000000U)
+#define CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_SHIFT (24U)
+/*! SMU2_BANK_CLK_EN - SMU2 bank Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_BTRTU1_AHB_CLK_EN_MASK (0x4000000U)
+#define CIU2_CIU2_CLK_ENABLE5_BTRTU1_AHB_CLK_EN_SHIFT (26U)
+/*! BTRTU1_AHB_CLK_EN - SW enable for btrtu ahb clock */
+#define CIU2_CIU2_CLK_ENABLE5_BTRTU1_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_BTRTU1_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_BTRTU1_AHB_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_MASK   (0x8000000U)
+#define CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_SHIFT  (27U)
+/*! SIF_CLK_SEL - SIF Clock Select */
+#define CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_MASK (0x10000000U)
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_SHIFT (28U)
+/*! CPU2_GATEHCLK_EN - CPU2gate HCLK Feature */
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_MASK (0x20000000U)
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_SHIFT (29U)
+/*! CPU2_FABRIC_CLK_EN - CPU2 Fabric Clock Control Feature */
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_MASK (0x40000000U)
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_SHIFT (30U)
+/*! CPU2_MEM_SLV_CLK_EN - CPU2 Memory Slave Clock Control Feature */
+#define CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_MASK)
+
+#define CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_MASK (0x80000000U)
+#define CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_SHIFT (31U)
+/*! SIF_AHB2_CLK_EN - SIF ahb2 Clock Enable */
+#define CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_MASK)
+/*! @} */
+
+/*! @name CIU2_CLK_CPU2CLK_CTRL - CPU2_AHB2 Clock Control */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_MASK (0xFU)
+#define CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_SHIFT (0U)
+/*! T1_FREQ_SEL - AHB2 Clock Frequency Select */
+#define CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_SHIFT)) & CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_CLK_UARTCLK_CTRL - UART Clock Control */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_MASK (0x1U)
+#define CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_SHIFT (0U)
+/*! REFCLK_SEL - Reference Clock Select */
+#define CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_SHIFT)) & CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_MASK)
+
+#define CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_MASK (0xFFFFFF80U)
+#define CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_SHIFT (7U)
+/*! NCO_STEP_SIZE - Programmable UART Clock Frequency */
+#define CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_SHIFT)) & CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_MASK)
+/*! @} */
+
+/*! @name CIU2_CLK_LBU2_BTRTU1_CTRL - LBU2 BT_RTU1 Clock Control */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_MASK (0x2U)
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_SHIFT (1U)
+/*! LBU2_USE_REFCLK - Static bit set by FW based on Reference Clock Frequency. If reference clock
+ *    frequency is lower and LBU can not support high baud rate of UART, then FW will set
+ *    soc_use_ref_mode = 0. This is an indication for Bluetooth subsystem that there is some IP which need PLL
+ *    to function which is LBU in this case.
+ */
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_MASK)
+
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_MASK (0x800U)
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_SHIFT (11U)
+/*! BTRTU1_TIMER1_USE_SLP_CLK - Timer 1 BT_RTU1 Clock */
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_MASK)
+
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_MASK (0x1000U)
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_SHIFT (12U)
+/*! BTRTU1_USE_REF_CLK - Static bit set by FW. If it is required that timers need not be programmed
+ *    with dynamic switching of T1/Reference, the BT_RTU1 source clock is set on reference clock so
+ *    that the timer are not disturbed.
+ */
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_MASK)
+
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_MASK (0x8000U)
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_SHIFT (15U)
+/*! BTRTU1_DBG_CLK_CTRL - BTRTU1 Debug Clock Control Feature */
+#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_MASK)
+/*! @} */
+
+/*! @name CIU2_CLK_CP15_DIS3 - Clock Auto Shut-off Enable3 */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_MASK (0xFFFFU)
+#define CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_SHIFT (0U)
+/*! BR_AHB2_CLK - BRU_AHB2 Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_MASK)
+
+#define CIU2_CIU2_CLK_CP15_DIS3_FFU_AHB2_CLK_MASK (0x100000U)
+#define CIU2_CIU2_CLK_CP15_DIS3_FFU_AHB2_CLK_SHIFT (20U)
+/*! FFU_AHB2_CLK - FFU_AHB Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS3_FFU_AHB2_CLK(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_FFU_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_FFU_AHB2_CLK_MASK)
+
+#define CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_MASK (0x1E00000U)
+#define CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_SHIFT (21U)
+/*! IMEM_AHB2_CLK - IMEM_AHB2 Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_MASK)
+
+#define CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_MASK (0x6000000U)
+#define CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_SHIFT (25U)
+/*! DMEM_AHB2_CLK - DMEM_AHB2 Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_MASK)
+
+#define CIU2_CIU2_CLK_CP15_DIS3_BLE_HCLK_MASK    (0x10000000U)
+#define CIU2_CIU2_CLK_CP15_DIS3_BLE_HCLK_SHIFT   (28U)
+/*! BLE_HCLK - BLE ahb Arbiter/Decoder Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS3_BLE_HCLK(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_BLE_HCLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_BLE_HCLK_MASK)
+
+#define CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_MASK (0x40000000U)
+#define CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_SHIFT (30U)
+/*! BTU_AHB_CLK - BTU Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_MASK)
+
+#define CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_MASK (0x80000000U)
+#define CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_SHIFT (31U)
+/*! BLE_AHB_CLK - BLE Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_MASK)
+/*! @} */
+
+/*! @name CIU2_RST_SW3 - Software Module Reset */
+/*! @{ */
+
+#define CIU2_CIU2_RST_SW3_BTU_AHB_CLK__MASK      (0x1U)
+#define CIU2_CIU2_RST_SW3_BTU_AHB_CLK__SHIFT     (0U)
+/*! BTU_AHB_CLK_ - BTU (ARM_Clk) Soft Reset */
+#define CIU2_CIU2_RST_SW3_BTU_AHB_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BTU_AHB_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_BTU_AHB_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW3_BLE_SOC__MASK          (0x2U)
+#define CIU2_CIU2_RST_SW3_BLE_SOC__SHIFT         (1U)
+/*! BLE_SOC_ - BLE SoC Soft Reset */
+#define CIU2_CIU2_RST_SW3_BLE_SOC_(x)            (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BLE_SOC__SHIFT)) & CIU2_CIU2_RST_SW3_BLE_SOC__MASK)
+
+#define CIU2_CIU2_RST_SW3_BT_COMMON__MASK        (0x4U)
+#define CIU2_CIU2_RST_SW3_BT_COMMON__SHIFT       (2U)
+/*! BT_COMMON_ - BT Common Soft Rest */
+#define CIU2_CIU2_RST_SW3_BT_COMMON_(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BT_COMMON__SHIFT)) & CIU2_CIU2_RST_SW3_BT_COMMON__MASK)
+
+#define CIU2_CIU2_RST_SW3_CPU2_CORE__MASK        (0x10U)
+#define CIU2_CIU2_RST_SW3_CPU2_CORE__SHIFT       (4U)
+/*! CPU2_CORE_ - CPU2 core reset */
+#define CIU2_CIU2_RST_SW3_CPU2_CORE_(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_CPU2_CORE__SHIFT)) & CIU2_CIU2_RST_SW3_CPU2_CORE__MASK)
+
+#define CIU2_CIU2_RST_SW3_CPU2_TCM__MASK         (0x20U)
+#define CIU2_CIU2_RST_SW3_CPU2_TCM__SHIFT        (5U)
+/*! CPU2_TCM_ - CPU2 TCM/DMA/Arbiter reset */
+#define CIU2_CIU2_RST_SW3_CPU2_TCM_(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_CPU2_TCM__SHIFT)) & CIU2_CIU2_RST_SW3_CPU2_TCM__MASK)
+
+#define CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__MASK     (0x80U)
+#define CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__SHIFT    (7U)
+/*! ARB_AHB2_CLK_ - AHB2 Arbiter Soft Reset */
+#define CIU2_CIU2_RST_SW3_ARB_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__MASK     (0x100U)
+#define CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__SHIFT    (8U)
+/*! DEC_AHB2_CLK_ - AHB2 Decoder Mux Soft Reset */
+#define CIU2_CIU2_RST_SW3_DEC_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__MASK     (0x200U)
+#define CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__SHIFT    (9U)
+/*! BRU_AHB2_CLK_ - BRU_AHB2 Soft Reset */
+#define CIU2_CIU2_RST_SW3_BRU_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW3_BT_UART_N_MASK         (0x400U)
+#define CIU2_CIU2_RST_SW3_BT_UART_N_SHIFT        (10U)
+/*! BT_UART_N - BT UART soft reset */
+#define CIU2_CIU2_RST_SW3_BT_UART_N(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BT_UART_N_SHIFT)) & CIU2_CIU2_RST_SW3_BT_UART_N_MASK)
+
+#define CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_MASK    (0x800U)
+#define CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_SHIFT   (11U)
+/*! SIU_AHB2_CLK_N - BT SIU (UART) AHB soft reset */
+#define CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_SHIFT)) & CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_MASK)
+
+#define CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__MASK     (0x10000U)
+#define CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__SHIFT    (16U)
+/*! SMU2_AHB_CLK_ - SMU2 (AHB_Clk) Soft Reset */
+#define CIU2_CIU2_RST_SW3_SMU2_AHB_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW3_SIF__MASK              (0x40000U)
+#define CIU2_CIU2_RST_SW3_SIF__SHIFT             (18U)
+/*! SIF_ - sif clock Soft Reset */
+#define CIU2_CIU2_RST_SW3_SIF_(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SIF__SHIFT)) & CIU2_CIU2_RST_SW3_SIF__MASK)
+
+#define CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__MASK     (0x80000U)
+#define CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__SHIFT    (19U)
+/*! SIF_AHB2_CLK_ - sif ahb2 Clock Soft Reset */
+#define CIU2_CIU2_RST_SW3_SIF_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW3_HPU2__MASK             (0x100000U)
+#define CIU2_CIU2_RST_SW3_HPU2__SHIFT            (20U)
+/*! HPU2_ - HPU2 Reset */
+#define CIU2_CIU2_RST_SW3_HPU2_(x)               (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_HPU2__SHIFT)) & CIU2_CIU2_RST_SW3_HPU2__MASK)
+
+#define CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__MASK     (0x400000U)
+#define CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__SHIFT    (22U)
+/*! CIU2_AHB_CLK_ - CIU2 AHB Soft Reset */
+#define CIU2_CIU2_RST_SW3_CIU2_AHB_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW3_BRF_PR__MASK           (0x4000000U)
+#define CIU2_CIU2_RST_SW3_BRF_PR__SHIFT          (26U)
+/*! BRF_PR_ - BRF_PR Reset */
+#define CIU2_CIU2_RST_SW3_BRF_PR_(x)             (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BRF_PR__SHIFT)) & CIU2_CIU2_RST_SW3_BRF_PR__MASK)
+
+#define CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_MASK (0x10000000U)
+#define CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_SHIFT (28U)
+/*! WD2_CHIP_RST_DISABLE - WD2 Chip Reset Control */
+#define CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_SHIFT)) & CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_MASK)
+
+#define CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_MASK (0x20000000U)
+#define CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_SHIFT (29U)
+/*! WD2_CPU2_RST_DISABLE - WD2 CPU2 Reset Control */
+#define CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_SHIFT)) & CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_MASK)
+
+#define CIU2_CIU2_RST_SW3_BT_16M_CLK__MASK       (0x40000000U)
+#define CIU2_CIU2_RST_SW3_BT_16M_CLK__SHIFT      (30U)
+/*! BT_16M_CLK_ - Bt 16M clock reset */
+#define CIU2_CIU2_RST_SW3_BT_16M_CLK_(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BT_16M_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_BT_16M_CLK__MASK)
+/*! @} */
+
+/*! @name CIU2_MEM_WRTC3 - Memory WRTC Control 3 */
+/*! @{ */
+
+#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_MASK     (0x700U)
+#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_SHIFT    (8U)
+/*! BLE_ROM_RTC - BLE ROM RTC */
+#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_MASK (0x3000U)
+#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_SHIFT (12U)
+/*! BLE_ROM_RTC_REF - BLE ROM RTC_REF */
+#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_SHIFT)) & CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_MASK)
+
+#define CIU2_CIU2_MEM_WRTC3_R1P_RTC_MASK         (0xC0000U)
+#define CIU2_CIU2_MEM_WRTC3_R1P_RTC_SHIFT        (18U)
+/*! R1P_RTC - RTC for small memory for UART in AHB2_TOP */
+#define CIU2_CIU2_MEM_WRTC3_R1P_RTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC3_R1P_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC3_R1P_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC3_R1P_WTC_MASK         (0x300000U)
+#define CIU2_CIU2_MEM_WRTC3_R1P_WTC_SHIFT        (20U)
+/*! R1P_WTC - WTC for small memory for UART in AHB2_TOP */
+#define CIU2_CIU2_MEM_WRTC3_R1P_WTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC3_R1P_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC3_R1P_WTC_MASK)
+/*! @} */
+
+/*! @name CIU2_MEM_WRTC4 - Memory WRTC Control 4 */
+/*! @{ */
+
+#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_MASK   (0x3U)
+#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_SHIFT  (0U)
+/*! CPU2_ITCM_RTC - CPU2 ITCM RTC */
+#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_MASK   (0xCU)
+#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_SHIFT  (2U)
+/*! CPU2_ITCM_WTC - CPU2 ITCM WTC */
+#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_MASK   (0x30U)
+#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_SHIFT  (4U)
+/*! CPU2_DTCM_RTC - CPU2 DTCM RTC */
+#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_MASK   (0xC0U)
+#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_SHIFT  (6U)
+/*! CPU2_DTCM_WTC - CPU2 DTCM WTC */
+#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_SMU2_RTC_MASK        (0x300U)
+#define CIU2_CIU2_MEM_WRTC4_SMU2_RTC_SHIFT       (8U)
+/*! SMU2_RTC - SMU2 RTC */
+#define CIU2_CIU2_MEM_WRTC4_SMU2_RTC(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_SMU2_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_SMU2_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_SMU2_WTC_MASK        (0xC00U)
+#define CIU2_CIU2_MEM_WRTC4_SMU2_WTC_SHIFT       (10U)
+/*! SMU2_WTC - SMU2 WTC */
+#define CIU2_CIU2_MEM_WRTC4_SMU2_WTC(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_SMU2_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_SMU2_WTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_MASK    (0x7000U)
+#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_SHIFT   (12U)
+/*! CPU2_BRU_RTC - CPU2 BROM RTC */
+#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_MASK (0x30000U)
+#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_SHIFT (16U)
+/*! CPU2_BRU_RTC_REF - CPU2 BROM RTC_REF */
+#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_BTU_RTC_MASK         (0xC0000U)
+#define CIU2_CIU2_MEM_WRTC4_BTU_RTC_SHIFT        (18U)
+/*! BTU_RTC - BTU EBRAM RTC */
+#define CIU2_CIU2_MEM_WRTC4_BTU_RTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BTU_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BTU_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_BTU_WTC_MASK         (0x300000U)
+#define CIU2_CIU2_MEM_WRTC4_BTU_WTC_SHIFT        (20U)
+/*! BTU_WTC - BTU EBRAM WTC */
+#define CIU2_CIU2_MEM_WRTC4_BTU_WTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BTU_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BTU_WTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_BLE_RTC_MASK         (0xC000000U)
+#define CIU2_CIU2_MEM_WRTC4_BLE_RTC_SHIFT        (26U)
+/*! BLE_RTC - ble RTC */
+#define CIU2_CIU2_MEM_WRTC4_BLE_RTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BLE_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BLE_RTC_MASK)
+
+#define CIU2_CIU2_MEM_WRTC4_BLE_WTC_MASK         (0x30000000U)
+#define CIU2_CIU2_MEM_WRTC4_BLE_WTC_SHIFT        (28U)
+/*! BLE_WTC - ble WTC */
+#define CIU2_CIU2_MEM_WRTC4_BLE_WTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BLE_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BLE_WTC_MASK)
+/*! @} */
+
+/*! @name CIU2_MEM_PWDN3 - Memory Power down Control */
+/*! @{ */
+
+#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_MASK (0x1U)
+#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_SHIFT (0U)
+/*! CPU2_BRU_BYPASS_VAL - Firmware Bypass value for CPU2 Boot ROM Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_MASK (0x2U)
+#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_SHIFT (1U)
+/*! CPU2_DTCM_BYPASS_VAL - Firmware Bypass value for CPU2 DTCM Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_MASK (0x4U)
+#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_SHIFT (2U)
+/*! CPU2_ITCM_BYPASS_VAL - Firmware Bypass value for CPU2 ITCM Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_MASK (0x10U)
+#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_SHIFT (4U)
+/*! SMU2_BYPASS_VAL - Firmware Bypass value for SMU2 Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_MASK  (0x20U)
+#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_SHIFT (5U)
+/*! SIU_BYPASS_VAL - Firmware Bypass value for UART Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_MASK  (0x40U)
+#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_SHIFT (6U)
+/*! BTU_BYPASS_VAL - Firmware Bypass value for BTU Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_MASK (0x200U)
+#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_SHIFT (9U)
+/*! BT_ADMA_BYPASS_VAL - Firmware Bypass value for BT ADMA Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_MASK (0x10000U)
+#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_SHIFT (16U)
+/*! CPU2_BRU_BYPASS_EN - Firmware Bypass Enable for CPU2 Boot ROM Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_MASK (0x20000U)
+#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_SHIFT (17U)
+/*! CPU2_DTCM_BYPASS_EN - Firmware Bypass Enable for CPU2 DTCM Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_MASK (0x40000U)
+#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_SHIFT (18U)
+/*! CPU2_ITCM_BYPASS_EN - Firmware Bypass Enable for CPU2 ITCM Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_MASK  (0x100000U)
+#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_SHIFT (20U)
+/*! SMU2_BYPASS_EN - Firmware Bypass Enable for SMU2 Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_MASK   (0x200000U)
+#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_SHIFT  (21U)
+/*! SIU_BYPASS_EN - Firmware Bypass Enable for UART Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_MASK   (0x400000U)
+#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_SHIFT  (22U)
+/*! BTU_BYPASS_EN - Firmware Bypass Enable for BTU Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_MASK (0x2000000U)
+#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_SHIFT (25U)
+/*! BT_ADMA_BYPASS_EN - Firmware Bypass Enable for BT ADMA Memories Power Down */
+#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name CIU2_SOC_AHB2APB_STATUS - SOC AHB2APB Status */
+/*! @{ */
+
+#define CIU2_CIU2_SOC_AHB2APB_STATUS_CMD_FIFO_AFULL_MASK (0x1U)
+#define CIU2_CIU2_SOC_AHB2APB_STATUS_CMD_FIFO_AFULL_SHIFT (0U)
+/*! CMD_FIFO_AFULL - soc_io_top ahb2apb command fifo almost full status */
+#define CIU2_CIU2_SOC_AHB2APB_STATUS_CMD_FIFO_AFULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_SOC_AHB2APB_STATUS_CMD_FIFO_AFULL_SHIFT)) & CIU2_CIU2_SOC_AHB2APB_STATUS_CMD_FIFO_AFULL_MASK)
+/*! @} */
+
+/*! @name CIU2_BLE_CTRL - BLE Control and Status */
+/*! @{ */
+
+#define CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_MASK (0x100U)
+#define CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_SHIFT (8U)
+/*! BT_AES_CLK_FREQ_SEL - btu_aes_clk Frequency Select */
+#define CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_SHIFT)) & CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_AHB2_TO_LAST_ADDR - AHB2 Timeout Last Address */
+/*! @{ */
+
+#define CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_SHIFT (0U)
+/*! ADDRESS - Last AHB2 Address Right Before the Current Timeout */
+#define CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_SHIFT)) & CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name CIU2_AHB2_TO_CUR_ADDR - AHB2 Current Timeout Address */
+/*! @{ */
+
+#define CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_MASK  (0xFFFFFFFFU)
+#define CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_SHIFT (0U)
+/*! ADDRESS - Current_TO_Addr */
+#define CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_SHIFT)) & CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name CIU2_AHB2_TO_CTRL - AHB2 ARB Control */
+/*! @{ */
+
+#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_MASK (0xFU)
+#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_SHIFT (0U)
+/*! CURRENT_TO_SLAVE_ID - Current_TO_Slave_ID */
+#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_MASK (0xF0U)
+#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_SHIFT (4U)
+/*! LAST_TO_SLAVE_ID - Last_TO_Slave_ID */
+#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_MASK (0xF00U)
+#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_SHIFT (8U)
+/*! CURRENT_TO_MASTER_ID - AHB2 Current_TO_Master_ID */
+#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_MASK (0xF000U)
+#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_SHIFT (12U)
+/*! LAST_TO_MASTER_ID - AHB2 Last_TO_Master_ID */
+#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_MASK (0x10000U)
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_SHIFT (16U)
+/*! AHB2_SMU1_MEM_PROT_DIS - Disable SMU1 Memory Protection from AHB2 side */
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_MASK (0x20000U)
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_SHIFT (17U)
+/*! AHB2_CPU2_IMEM_PROT_DIS - 1 = Disable CPU2 Imem Memory Protection from AHB2 side and allow AHB2 to read/write Imem */
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_MASK (0x40000U)
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_SHIFT (18U)
+/*! AHB2_CPU2_DMEM_PROT_DIS - 1 = Disable CPU2 Dmem Memory Protection from AHB2 side and allow AHB2 to read/write Dmem */
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_MASK (0xC0000000U)
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_SHIFT (30U)
+/*! AHB2_TIMEOUT_MODE - AHB2_TimeoutMode[1:0] */
+#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_MASK)
+/*! @} */
+
+/*! @name CIU2_AHB2_SMU1_ACCESS_ADDR - AHB2 to SMU1 Accessible Address */
+/*! @{ */
+
+#define CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_SHIFT (0U)
+/*! AHB2_SMU1_ACCESS_ADDR - SMU1 Accessible Memory Address from AHB2 side */
+#define CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_SHIFT)) & CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_MASK)
+/*! @} */
+
+/*! @name CIU2_AHB2_SMU1_ACCESS_MASK - AHB2 to SMU1 Accessible Mask */
+/*! @{ */
+
+#define CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_SHIFT (0U)
+/*! AHB2_SMU1_ACCESS_MASK - SMU1 Accessible Memory Mask from AHB2 side */
+#define CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_SHIFT)) & CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_ICODE_INV_ADDR_CTRL - CPU2 Icode invalid address access control */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK (0xFU)
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT (0U)
+/*! LAST2_INV_ADDR_SLAVE_ID - Last2_inv_addr_Slave_ID */
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK (0xF0U)
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT (4U)
+/*! LAST_INV_ADDR_SLAVE_ID - Last_inv_addr_Slave_ID */
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK (0xF00U)
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT (8U)
+/*! CUR_INV_ADDR_SLAVE_ID - Cur_inv_addr_Slave_ID */
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK (0xC0000000U)
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT (30U)
+/*! HADDR_ICOD_SEL - There are 3 haddr which can be observed by selecting this: */
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_ICODE_INV_ADDR - CPU2 Icode invalid address */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_SHIFT (0U)
+/*! HADDR_INV_ADDR - based on CIU_CPU2_ICODE_INV_ADDR_CTRL[31:30], the address status is observed in this register */
+#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_DCODE_INV_ADDR_CTRL - CPU2 Dcode invalid address access control */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK (0xFU)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT (0U)
+/*! LAST2_INV_ADDR_SLAVE_ID - Last2_inv_addr_Slave_ID */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK (0xF0U)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT (4U)
+/*! LAST_INV_ADDR_SLAVE_ID - Last_inv_addr_Slave_ID */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK (0xF00U)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT (8U)
+/*! CUR_INV_ADDR_SLAVE_ID - Cur_inv_addr_Slave_ID */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK)
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_MASK (0xF000U)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_SHIFT (12U)
+/*! LAST2_INV_ADDR_MASTER_ID - Last2_inv_addr_master_ID */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_MASK)
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_MASK (0xF0000U)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_SHIFT (16U)
+/*! LAST_INV_ADDR_MASTER_ID - Last_inv_addr_master_ID */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_MASK)
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_MASK (0xF00000U)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_SHIFT (20U)
+/*! CUR_INV_ADDR_MASTER_ID - Cur_inv_addr_master_ID */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_MASK)
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK (0xC0000000U)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT (30U)
+/*! HADDR_ICOD_SEL - There are 3 haddr which can be observed by selecting this: */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_DCODE_INV_ADDR - CPU2 Dcode invalid address */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_SHIFT (0U)
+/*! HADDR_INV_ADDR - based on CIU_CPU2_DCODE_INV_ADDR_CTRL[31:30], the address status is observed in this register */
+#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU_CPU2_CTRL - CPU2 control register */
+/*! @{ */
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_MASK     (0x1U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_SHIFT    (0U)
+/*! VINITHI - Boot Address Control */
+#define CIU2_CIU2_CPU_CPU2_CTRL_VINITHI(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_MASK (0x4U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_SHIFT (2U)
+/*! CPU2_JTAG_CHAIN_BYPASS - CPU2 JTAG Chain Bypass Control */
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_MASK (0x10U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_SHIFT (4U)
+/*! CPU2_BOOT_IMEM_MUX_EN - CPU2 Boot IMEM mux Enable */
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_MASK (0x20U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_SHIFT (5U)
+/*! CPU2_BOOT_DMEM_MUX_EN - CPU2 DMEM mux Enable */
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_MASK (0xFFF0000U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_SHIFT (16U)
+/*! CPU2_DBG_CTRL - cpu2 debug control */
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_MCI_AHB2_MSG_SCHEME_MASK (0x10000000U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_MCI_AHB2_MSG_SCHEME_SHIFT (28U)
+/*! MCI_AHB2_MSG_SCHEME - IMU Scheme Select for Communication between AHB2 & MCI */
+#define CIU2_CIU2_CPU_CPU2_CTRL_MCI_AHB2_MSG_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_MCI_AHB2_MSG_SCHEME_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_MCI_AHB2_MSG_SCHEME_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_MASK (0x20000000U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_SHIFT (29U)
+/*! CPU3_RESET_INT - CPU2 fw resets cpu3(or cpu3 fw resets CPU2 if this register is used by cpu3) */
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_MASK (0x40000000U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_SHIFT (30U)
+/*! DSR_WKUP_IN_USE - dsr wkup when dsr_wkup_in_use = 1'b1 */
+#define CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_MASK (0x80000000U)
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_SHIFT (31U)
+/*! CPU1_RESET_INT - CPU2 fw resets cpu1( or cpu3 fw resets cpu1 if this register is used by cpu3) */
+#define CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_MASK)
+/*! @} */
+
+/*! @name CIU2_BRF_CTRL - BRF Control and Status */
+/*! @{ */
+
+#define CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_MASK (0x1U)
+#define CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_SHIFT (0U)
+/*! AHB_SLV_BRF_SER_EN - When set to 1, BRF serial interface will be accessed thru AHB slave memory mapped from 0xA800A000 to 0xA8011FFF */
+#define CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_SHIFT)) & CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_MASK)
+
+#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_MASK (0x100U)
+#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_SHIFT (8U)
+/*! CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN - BRF REF1X Clock Control Bypass Enable */
+#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_SHIFT)) & CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_MASK (0x200U)
+#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_SHIFT (9U)
+/*! CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL - 1. brf ref clk 1x is enabled */
+#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_SHIFT)) & CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_BRF_CTRL_BRF_SQU_DUMP_EN_MASK  (0x400U)
+#define CIU2_CIU2_BRF_CTRL_BRF_SQU_DUMP_EN_SHIFT (10U)
+/*! BRF_SQU_DUMP_EN - Enable SQU data dump from BRF */
+#define CIU2_CIU2_BRF_CTRL_BRF_SQU_DUMP_EN(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_BRF_SQU_DUMP_EN_SHIFT)) & CIU2_CIU2_BRF_CTRL_BRF_SQU_DUMP_EN_MASK)
+
+#define CIU2_CIU2_BRF_CTRL_FFU_USE_BRF_RX_PATH_MASK (0x800U)
+#define CIU2_CIU2_BRF_CTRL_FFU_USE_BRF_RX_PATH_SHIFT (11U)
+/*! FFU_USE_BRF_RX_PATH - This bit is connected to FRF_15P4_USE_BRF_RX_PATH input of BRF as recommended by Sridhar. */
+#define CIU2_CIU2_BRF_CTRL_FFU_USE_BRF_RX_PATH(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_FFU_USE_BRF_RX_PATH_SHIFT)) & CIU2_CIU2_BRF_CTRL_FFU_USE_BRF_RX_PATH_MASK)
+
+#define CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_MASK     (0x80000000U)
+#define CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_SHIFT    (31U)
+/*! BRF_CHIP_RDY - BRF Chip_Rdy Status */
+#define CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_SHIFT)) & CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_MASK)
+/*! @} */
+
+/*! @name CIU2_BRF_EXTRA_PORT - BRF Extra Port Connection */
+/*! @{ */
+
+#define CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_MASK (0xFU)
+#define CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_SHIFT (0U)
+/*! SOC_BRF_EXTRA - SOC_BRF_EXTRA[3:0] */
+#define CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_SHIFT)) & CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_MASK)
+/*! @} */
+
+/*! @name CIU2_BRF_ECO_CTRL - BRF ECO Control */
+/*! @{ */
+
+#define CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_MASK     (0xFFFFFFFFU)
+#define CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_SHIFT    (0U)
+/*! ECO_BITS - Reserved */
+#define CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_SHIFT)) & CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU2_BTU_CTRL - BTU Control and Status */
+/*! @{ */
+
+#define CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_MASK    (0x1U)
+#define CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_SHIFT   (0U)
+/*! BTU_CIPHER_EN - Bluetooth Cipher Logic */
+#define CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_SHIFT)) & CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_MASK)
+
+#define CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_MASK (0x2U)
+#define CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_SHIFT (1U)
+/*! DBUS_HIGH_SPEED_SEL - Dbus High Speed Select Signal for Greater than 4 MHz */
+#define CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_SHIFT)) & CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_MASK)
+
+#define CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_MASK       (0xCU)
+#define CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_SHIFT      (2U)
+/*! BT_CLK_SEL - Bluetooth sys Clock Select */
+#define CIU2_CIU2_BTU_CTRL_BT_CLK_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_SHIFT)) & CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_MASK)
+
+#define CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_MASK    (0x700U)
+#define CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_SHIFT   (8U)
+/*! BT_IP_SER_SEL - bt_ip_ser_sel */
+#define CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_SHIFT)) & CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_MASK)
+
+#define CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_MASK    (0x80000000U)
+#define CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_SHIFT   (31U)
+/*! BTU_MC_WAKEUP - BTU MC_Wakeup Status */
+#define CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_SHIFT)) & CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_MASK)
+/*! @} */
+
+/*! @name CIU2_BT_PS - BT Clock Power Save */
+/*! @{ */
+
+#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_MASK    (0x3FFFFFFU)
+#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_SHIFT   (0U)
+/*! BT_MCLK_NCO_MVAL - BT_MCLK NCO Module Step Control (default 0x0) */
+#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_MASK)
+
+#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_MASK      (0x4000000U)
+#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_SHIFT     (26U)
+/*! BT_MCLK_NCO_EN - BT_MCLK_NCO logic to count */
+#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_MASK)
+
+#define CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_MASK (0x8000000U)
+#define CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_SHIFT (27U)
+/*! BT_MCLK_TBG_NCO_SEL - BT_4M_PCM_CLK */
+#define CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_MASK)
+
+#define CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_MASK (0x10000000U)
+#define CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_SHIFT (28U)
+/*! BT_MCLK_FROM_SOC_SEL - BT_MCLK */
+#define CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_BT_PS2 - BT Clock Power Save 2 */
+/*! @{ */
+
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_MASK (0x3FFFFFFU)
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_SHIFT (0U)
+/*! BT_PCM_CLK_NCO_MVAL - BT_PCM_CLK NCO Module Step Control (default 0x0) */
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_SHIFT)) & CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_MASK)
+
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_MASK  (0x4000000U)
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_SHIFT (26U)
+/*! BT_PCM_CLK_NCO_EN - BT_PCM_CLK_NCO logic to count */
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_SHIFT)) & CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_MASK)
+
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_MASK (0x8000000U)
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_SHIFT (27U)
+/*! BT_PCM_CLK_TBG_NCO_SEL - BT_4M_PCM_CLK */
+#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_BT_REF_CTRL - BT Ref Control */
+/*! @{ */
+
+#define CIU2_CIU2_BT_REF_CTRL_NCO_EN_MASK        (0x1U)
+#define CIU2_CIU2_BT_REF_CTRL_NCO_EN_SHIFT       (0U)
+/*! NCO_EN - Bluetooth Reference Clock NCO Enable information to APU. */
+#define CIU2_CIU2_BT_REF_CTRL_NCO_EN(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_NCO_EN_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_NCO_EN_MASK)
+
+#define CIU2_CIU2_BT_REF_CTRL_NCO_SEL_MASK       (0x2U)
+#define CIU2_CIU2_BT_REF_CTRL_NCO_SEL_SHIFT      (1U)
+/*! NCO_SEL - Bluetooth Reference Clock NCO Select Value */
+#define CIU2_CIU2_BT_REF_CTRL_NCO_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_NCO_SEL_MASK)
+
+#define CIU2_CIU2_BT_REF_CTRL_NCO_GEN_MASK       (0x3FFFCU)
+#define CIU2_CIU2_BT_REF_CTRL_NCO_GEN_SHIFT      (2U)
+/*! NCO_GEN - Bluetooth Reference Clock NCO Gen Value */
+#define CIU2_CIU2_BT_REF_CTRL_NCO_GEN(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_NCO_GEN_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_NCO_GEN_MASK)
+
+#define CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_MASK (0x100000U)
+#define CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_SHIFT (20U)
+/*! BT_CLK_NCO_REFCLK_SEL - BT clk (bt sys clk) selection */
+#define CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_BT_PS3 - BT Clock Power Save 3 */
+/*! @{ */
+
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_MASK (0x3FFFFFFU)
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_SHIFT (0U)
+/*! BTU_16M_CLK_NCO_STEP_CTRL - BT_16M_CLK NCO Module Step Control */
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_MASK)
+
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_MASK (0x4000000U)
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_SHIFT (26U)
+/*! BTU_16M_CLK_NCO_EN - BTU 16M Clock NCO Enable */
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_MASK)
+
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_MASK (0x8000000U)
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_SHIFT (27U)
+/*! BTU_16M_CLK_NCO_SEL - BTU 16M clock NCO Select Value */
+#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_MASK)
+
+#define CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_MASK   (0x20000000U)
+#define CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_SHIFT  (29U)
+/*! BTU_CLK_NCO_MODE - BTU Clock source from ref clock (nco mode) */
+#define CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_MASK)
+/*! @} */
+
+/*! @name CIU2_BTU_ECO_CTRL - BTU ECO Control */
+/*! @{ */
+
+#define CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_MASK     (0xFFFFFFFFU)
+#define CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_SHIFT    (0U)
+/*! ECO_BITS - Reserved */
+#define CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_SHIFT)) & CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CIU2_INT_MASK - CIU2 Interrupt Mask */
+/*! @{ */
+
+#define CIU2_CIU2_INT_MASK_MASK_MASK             (0xFFFFFFFFU)
+#define CIU2_CIU2_INT_MASK_MASK_SHIFT            (0U)
+/*! MASK - Interrupt Mask for CIU2 Interrupts */
+#define CIU2_CIU2_INT_MASK_MASK(x)               (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_MASK_MASK_SHIFT)) & CIU2_CIU2_INT_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name CIU2_INT_SELECT - CIU2 Interrupt Select */
+/*! @{ */
+
+#define CIU2_CIU2_INT_SELECT_SEL_MASK            (0xFFFFFFFFU)
+#define CIU2_CIU2_INT_SELECT_SEL_SHIFT           (0U)
+/*! SEL - Interrupt Read/Write Clear for CIU2 Interrupts */
+#define CIU2_CIU2_INT_SELECT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_SELECT_SEL_SHIFT)) & CIU2_CIU2_INT_SELECT_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_INT_EVENT_MASK - CIU2 Interrupt Event Mask */
+/*! @{ */
+
+#define CIU2_CIU2_INT_EVENT_MASK_MASK_MASK       (0xFFFFFFFFU)
+#define CIU2_CIU2_INT_EVENT_MASK_MASK_SHIFT      (0U)
+/*! MASK - Interrupt Event Mask for CIU2 Interrupts */
+#define CIU2_CIU2_INT_EVENT_MASK_MASK(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_EVENT_MASK_MASK_SHIFT)) & CIU2_CIU2_INT_EVENT_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name CIU2_INT_STATUS - CIU2 Interrupt Status */
+/*! @{ */
+
+#define CIU2_CIU2_INT_STATUS_CIU_ISR_MASK        (0xFFFFFFFFU)
+#define CIU2_CIU2_INT_STATUS_CIU_ISR_SHIFT       (0U)
+/*! CIU_ISR - CIU2 Interrupt Status (ISR) */
+#define CIU2_CIU2_INT_STATUS_CIU_ISR(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_STATUS_CIU_ISR_SHIFT)) & CIU2_CIU2_INT_STATUS_CIU_ISR_MASK)
+/*! @} */
+
+/*! @name CPU2_ERR_INT_MASK - CPU2 ERR Interrupt Mask */
+/*! @{ */
+
+#define CIU2_CPU2_ERR_INT_MASK_MASK_MASK         (0xFFFFFFFFU)
+#define CIU2_CPU2_ERR_INT_MASK_MASK_SHIFT        (0U)
+/*! MASK - Interrupt Mask for CPU2 ERR Interrupts */
+#define CIU2_CPU2_ERR_INT_MASK_MASK(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_MASK_MASK_SHIFT)) & CIU2_CPU2_ERR_INT_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name CPU2_ERR_INT_SELECT - CPU2 ERR Interrupt Clear Select */
+/*! @{ */
+
+#define CIU2_CPU2_ERR_INT_SELECT_SEL_MASK        (0xFFFFFFFFU)
+#define CIU2_CPU2_ERR_INT_SELECT_SEL_SHIFT       (0U)
+/*! SEL - Interrupt Read/Write Clear for CPU2 ERR Interrupts */
+#define CIU2_CPU2_ERR_INT_SELECT_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_SELECT_SEL_SHIFT)) & CIU2_CPU2_ERR_INT_SELECT_SEL_MASK)
+/*! @} */
+
+/*! @name CPU2_ERR_INT_EVENT_MASK - CPU2 ERR Interrupt Event Mask */
+/*! @{ */
+
+#define CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_MASK   (0xFFFFFFFFU)
+#define CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_SHIFT  (0U)
+/*! MASK - Interrupt Event Mask for CPU2 ERR Interrupts */
+#define CIU2_CPU2_ERR_INT_EVENT_MASK_MASK(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_SHIFT)) & CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name CPU2_ERR_INT_STATUS - CPU2 ERR Interrupt Status */
+/*! @{ */
+
+#define CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_MASK    (0xFFFFFFFFU)
+#define CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_SHIFT   (0U)
+/*! ERR_ISR - CPU2 ERR Interrupt Status (ISR) */
+#define CIU2_CPU2_ERR_INT_STATUS_ERR_ISR(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_SHIFT)) & CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_MASK)
+/*! @} */
+
+/*! @name CIU2_BCA1_CPU2_INT_MASK - BCA1 to CPU2 Interrupt Mask */
+/*! @{ */
+
+#define CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_MASK    (0xFFFFFFFFU)
+#define CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_SHIFT   (0U)
+/*! IMR - Interrupt Mask for BCA1 to CPU2 Interrupts */
+#define CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_MASK)
+/*! @} */
+
+/*! @name CIU2_BCA1_CPU2_INT_SELECT - BCA1 to CPU2 Interrupt Select */
+/*! @{ */
+
+#define CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_MASK  (0xFFFFFFFFU)
+#define CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_SHIFT (0U)
+/*! RSR - Interrupt Read/Write Clear for BCA1 to CPU2 Interrupts */
+#define CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_MASK)
+/*! @} */
+
+/*! @name CIU2_BCA1_CPU2_INT_EVENT_MASK - BCA1 to CPU2 Interrupt Event Mask */
+/*! @{ */
+
+#define CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_SHIFT (0U)
+/*! SMR - Interrupt Event Mask for BCA1 to CPU2 Interrupts */
+#define CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_MASK)
+/*! @} */
+
+/*! @name CIU2_BCA1_CPU2_INT_STATUS - BCA1 to CPU2 Interrupt Status */
+/*! @{ */
+
+#define CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_MASK  (0xFFFFFFFFU)
+#define CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_SHIFT (0U)
+/*! ISR - BCA1 to CPU2 Interrupt Status */
+#define CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_MASK)
+/*! @} */
+
+/*! @name CIU2_APU_BYPASS1 - CIU2 APU Bypass Register 1 */
+/*! @{ */
+
+#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_MASK (0x1U)
+#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_SHIFT (0U)
+/*! BRF_CLK_EN_BYPASS_EN - Firmware Bypass BRF_Clk_En */
+#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_MASK (0x2U)
+#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_SHIFT (1U)
+/*! BRF_CLK_EN_BYPASS_VAL - Firmware Bypass Value for BRF_Clk_En (active high signal) */
+#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_MASK (0x4U)
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_SHIFT (2U)
+/*! BT_AES_CLK_EN_BYPASS_EN - Firmware Bypass for Btu_Aes_Clk */
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_MASK (0x8U)
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_SHIFT (3U)
+/*! BT_AES_CLK_EN_BYPASS_VAL - Firmware Bypass Value for Btu_Aes_Clk */
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_MASK (0x10U)
+#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_SHIFT (4U)
+/*! SOC_CLK_EN2_T1_BYPASS_EN - Firmware Bypass for SoC_Clk_En2 */
+#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_MASK (0x20U)
+#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_SHIFT (5U)
+/*! SOC_CLK_EN2_T1_BYPASS_VAL - Firmware Bypass Value for SoC_Clk_En2(active high signal) */
+#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_MASK (0xC0U)
+#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_SHIFT (6U)
+/*! TBG_BTU_CLK_EN_BYPASS_SEL - TBG512_320_176_BTU_Clk_En_Sel to TBG512_320_176 of CAU */
+#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_MASK (0x100U)
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_SHIFT (8U)
+/*! BT_AES_CLK_SEL_BYPASS_EN - Firmware Bypass for Btu_Aes_Clk_Sel */
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_MASK (0x200U)
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_SHIFT (9U)
+/*! BT_AES_CLK_SEL_BYPASS_VAL - Firmware Bypass Value for Btu_Aes_Clk_Sel */
+#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_MASK (0x400U)
+#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_SHIFT (10U)
+/*! TBG_BTU_CLK_EN_BYPASS_VAL - TBG512_320_176_BTU_Clk_En Bypass Value */
+#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_LMU_STA_BYPASS0 - LMU static bank control byapss0 Register for CPU2 mem */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK (0xFFU)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_ISO_EN_BP_EN - Firmware Bypass enable for lmu static banks iso_en */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK (0xFF00U)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_ISO_EN_BP_VAL - Firmware Bypass value for lmu static banks iso_en */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK (0xFF0000U)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT (16U)
+/*! LMU_STA_BANKS_PSW_EN_BP_EN - Firmware Bypass enable for lmu static banks psw_en */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK (0xFF000000U)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT (24U)
+/*! LMU_STA_BANKS_PSW_EN_BP_VAL - Firmware Bypass value for lmu static banks psw_en */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_LMU_STA_BYPASS1 - LMU static bank control byapss1 Register for CPU2 */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK (0xFFU)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_SRAM_PD_BP_EN - Firmware Bypass enable for lmu static banks sram_pd */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK (0xFF00U)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_SRAM_PD_BP_VAL - Firmware Bypass value for lmu static banks sram_pd */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK (0xFF0000U)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT (16U)
+/*! LMU_STA_BANKS_FNRST_BP_EN - Firmware Bypass enable for lmu static banks fnrst */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK (0xFF000000U)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT (24U)
+/*! LMU_STA_BANKS_FNRST_BP_VAL - Firmware Bypass value for lmu static banks fnrst */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_LMU_STA_BYPASS2 - LMU static bank byapss2 Register for CPU2 */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0xFFU)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN - Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0xFF00U)
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL - Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl */
+#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS - LMU G2Bist control bypass Register for CPU2 */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_MASK (0x1U)
+#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT (0U)
+/*! LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN - Firmware Bypass enable for CPU2 static banks lmu power domain repair request */
+#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_MASK)
+
+#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_MASK (0xFEU)
+#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT (1U)
+/*! LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL - Firmware Bypass value for CPU2 static banks lmu power domain repair request */
+#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_MASK)
+/*! @} */
+
+/*! @name CIU2_APU_PWR_CTRL_BYPASS1 - APU power control Bypass Register 1 */
+/*! @{ */
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_MASK (0x1U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_SHIFT (0U)
+/*! BRF_PSW_BYPASS_VAL - brf Power Switch Control */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_MASK (0x2U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_SHIFT (1U)
+/*! BRF_PSW_BYPASS_EN - brf Power Switch Control Enable */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_MASK (0x4U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_SHIFT (2U)
+/*! BRF_FWBAR_BYPASS_VAL - brf Firewallbar Control */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_MASK (0x8U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_SHIFT (3U)
+/*! BRF_FWBAR_BYPASS_EN - brf Firewallbar Control Enable */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_MASK (0x10U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_SHIFT (4U)
+/*! BRF_ISO_EN_BYPASS_VAL - brf Isolation Cell Control */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_MASK (0x20U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_SHIFT (5U)
+/*! BRF_ISO_EN_BYPASS_EN - brf Isolation Cell Control Enable */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_MASK (0x40U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_SHIFT (6U)
+/*! BRF_CLK_DIV_RSTB_BYPASS_VAL - Firmware Bypass Value for brf Clk_Div_Rstb (active low signal) */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_MASK (0x80U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_SHIFT (7U)
+/*! BRF_CLK_DIV_RSTB_BYPASS_EN - Firmware Bypass brf Clk_Div_Rstb from APU */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_MASK (0x100U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_SHIFT (8U)
+/*! BRF_SRAM_PD_BYPASS_VAL - Firmware Bypass Value for SRAM_PD (active high signal) */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_MASK)
+
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_MASK (0x200U)
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_SHIFT (9U)
+/*! BRF_SRAM_PD_BYPASS_EN - Firmware Bypass SRAM_PD from APU */
+#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name CIU2_AHB2AHB_BRIDGE_CTRL - AHB2AHB Bridge Control Register */
+/*! @{ */
+
+#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_MASK (0x1U)
+#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_SHIFT (0U)
+/*! PREFETCH_HSEL_EN - ahb2ahb bridge pre-fetch hsel enable */
+#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_SHIFT)) & CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_MASK)
+
+#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_MCI_AHB2_A2A_PREFETCH_EN_MASK (0x2U)
+#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_MCI_AHB2_A2A_PREFETCH_EN_SHIFT (1U)
+/*! MCI_AHB2_A2A_PREFETCH_EN - MCI-AHB2 ahb2ahb bridge pre-fetch hsel enable */
+#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_MCI_AHB2_A2A_PREFETCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_MCI_AHB2_A2A_PREFETCH_EN_SHIFT)) & CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_MCI_AHB2_A2A_PREFETCH_EN_MASK)
+/*! @} */
+
+/*! @name CIU2_CLK_CP15_DIS1 - Clock Auto Shut-off Enable1 */
+/*! @{ */
+
+#define CIU2_CIU2_CLK_CP15_DIS1_CIU_BTAPU_AHB_CLK_DIS_ON_SLP_MASK (0x100000U)
+#define CIU2_CIU2_CLK_CP15_DIS1_CIU_BTAPU_AHB_CLK_DIS_ON_SLP_SHIFT (20U)
+/*! CIU_BTAPU_AHB_CLK_DIS_ON_SLP - APU Shut Off */
+#define CIU2_CIU2_CLK_CP15_DIS1_CIU_BTAPU_AHB_CLK_DIS_ON_SLP(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS1_CIU_BTAPU_AHB_CLK_DIS_ON_SLP_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS1_CIU_BTAPU_AHB_CLK_DIS_ON_SLP_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_RTU_NCO_CTRL - RTU NCO Clock Control */
+/*! @{ */
+
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_REF_CLK_SEL_MASK (0x1U)
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_REF_CLK_SEL_SHIFT (0U)
+/*! CIU_BTRTU_REF_CLK_SEL - RTU Reference Clock from UART reference clock tree */
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_REF_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_REF_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_OUT_SEL_MASK (0x2U)
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_OUT_SEL_SHIFT (1U)
+/*! CIU_BTRTU_NCO_OUT_SEL - RTU NCO Mode Select (Reference Clock Based) */
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_OUT_SEL_SHIFT)) & CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_OUT_SEL_MASK)
+
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_ENABLE_MASK (0x4U)
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_ENABLE_SHIFT (2U)
+/*! CIU_BTRTU_NCO_ENABLE - RTU NCO Enable (Reference Clock Based) */
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_ENABLE_SHIFT)) & CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_ENABLE_MASK)
+
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_STEP_MASK (0xFFFF0000U)
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_STEP_SHIFT (16U)
+/*! CIU_BTRTU_NCO_STEP - Step size for RTU clock NCO (Reference Clock Based) */
+#define CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_STEP(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_STEP_SHIFT)) & CIU2_CIU_CLK_RTU_NCO_CTRL_CIU_BTRTU_NCO_STEP_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_SOCCLK_CTRL - SOC Clock Control */
+/*! @{ */
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_EN_MASK (0x40U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_EN_SHIFT (6U)
+/*! BTU_PCM_CLK_T3_256_DIV125_EN - T3_256 DIV125 Enable */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_EN_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_EN_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_CLK_SEL_MASK (0x80U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_CLK_SEL_SHIFT (7U)
+/*! BTU_PCM_CLK_T3_256_DIV125_CLK_SEL - T3_256 DIV125 Clock Select */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_BTU_PCM_CLK_T3_256_DIV125_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_EN_MASK (0x100U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_EN_SHIFT (8U)
+/*! BTU_MCLK_T3_512_DIV125_EN - T3_512 DIV125 Enable */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_EN_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_EN_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_CLK_SEL_MASK (0x200U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_CLK_SEL_SHIFT (9U)
+/*! BTU_MCLK_T3_512_DIV125_CLK_SEL - T3_512 DIV125 Clock Select */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_BTU_MCLK_T3_512_DIV125_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CONST_CAL_CLK_SEL_MASK (0x400U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CONST_CAL_CLK_SEL_SHIFT (10U)
+/*! CIU_BTAPU_CONST_CAL_CLK_SEL - PMU Constant Calibration Clock Select */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CONST_CAL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CONST_CAL_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CONST_CAL_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CAL_CLK_SEL_MASK (0x800U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CAL_CLK_SEL_SHIFT (11U)
+/*! CIU_BTAPU_CAL_CLK_SEL - PMU Calibration Clock */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CAL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CAL_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_CIU_BTAPU_CAL_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_SEL_MASK (0x1000U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_SEL_SHIFT (12U)
+/*! PM_CLK_SEL - PM Clock source select */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_TBG_SEL_MASK (0x2000U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_TBG_SEL_SHIFT (13U)
+/*! PM_CLK_TBG_SEL - PM Clock */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_TBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_TBG_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_PM_CLK_TBG_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_MASK (0x4000U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_SHIFT (14U)
+/*! CIU_USE_REFCLK - SoC_Clk Clock */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_CIU_USE_REFCLK_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BT_AES_CLK_32_64_SEL_MASK (0x8000U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BT_AES_CLK_32_64_SEL_SHIFT (15U)
+/*! BT_AES_CLK_32_64_SEL - BT AES Clock Select 32 MHz or 64 MHz select */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_BT_AES_CLK_32_64_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_BT_AES_CLK_32_64_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_BT_AES_CLK_32_64_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_PCLK_DIV_SEL_MASK (0xF0000U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_PCLK_DIV_SEL_SHIFT (16U)
+/*! AHB2_AHB2APB_PCLK_DIV_SEL - AHB2 AHB2APB PCLK Divider Select */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_PCLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_PCLK_DIV_SEL_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_PCLK_DIV_SEL_MASK)
+
+#define CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_WAIT_CYCLES_MASK (0xF0000000U)
+#define CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_WAIT_CYCLES_SHIFT (28U)
+/*! AHB2_AHB2APB_WAIT_CYCLES - AH2 AHB2APB Wait Cycles between each APB transaction */
+#define CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_WAIT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_WAIT_CYCLES_SHIFT)) & CIU2_CIU_CLK_SOCCLK_CTRL_AHB2_AHB2APB_WAIT_CYCLES_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_SLEEPCLK_CTRL - Sleep Clock Control */
+/*! @{ */
+
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_MASK (0xFFFFFFU)
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_SHIFT (0U)
+/*! CIU_SLEEP_CLK_NCO_MVAL - Sleep Clock NCO */
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_SHIFT)) & CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_SLEEP_CLK_NCO_MVAL_MASK)
+
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_MASK (0x2000000U)
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_SHIFT (25U)
+/*! CIU_NCO_SLEEP_CLK_SEL - NCO Sleep Clock Select */
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_NCO_SLEEP_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_MASK (0x10000000U)
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_SHIFT (28U)
+/*! CIU_REFCLK_SLEEP_CLK_SEL - Reference Clock Sleep Clock Select */
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_REFCLK_SLEEP_CLK_SEL_MASK)
+
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_PCIE_SLP_CLK_SEL_MASK (0x40000000U)
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_PCIE_SLP_CLK_SEL_SHIFT (30U)
+/*! CIU_PCIE_SLP_CLK_SEL - PCIE Sleep Clock Select */
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_PCIE_SLP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_PCIE_SLP_CLK_SEL_SHIFT)) & CIU2_CIU_CLK_SLEEPCLK_CTRL_CIU_PCIE_SLP_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CIU_CLK_SLEEPCLK_CTRL2 - Sleep Clock Control 2 */
+/*! @{ */
+
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_MASK (0xFFFFFFU)
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_SHIFT (0U)
+/*! CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP - Sleep Clock NCO value for the sleep mode */
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_SHIFT)) & CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP_MASK)
+
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_MASK (0x1000000U)
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_SHIFT (24U)
+/*! CIU_SLEEP_CLK_NCO_MVAL_BYPASS - Sleep Clock NCO mval Bypass */
+#define CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_SHIFT)) & CIU2_CIU_CLK_SLEEPCLK_CTRL2_CIU_SLEEP_CLK_NCO_MVAL_BYPASS_MASK)
+/*! @} */
+
+/*! @name CIU2_IOMUX_MODE_CTRL - Test Bus Select */
+/*! @{ */
+
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_BRF_BIDI_MODE_MASK (0x1U)
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_BRF_BIDI_MODE_SHIFT (0U)
+/*! CIU2_EXT_BRF_BIDI_MODE - " */
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_BRF_BIDI_MODE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_BRF_BIDI_MODE_SHIFT)) & CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_BRF_BIDI_MODE_MASK)
+
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_BRF_STANDALONE_DATA_MODE_MASK (0x2U)
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_BRF_STANDALONE_DATA_MODE_SHIFT (1U)
+/*! CIU2_BRF_STANDALONE_DATA_MODE - " */
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_BRF_STANDALONE_DATA_MODE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_BRF_STANDALONE_DATA_MODE_SHIFT)) & CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_BRF_STANDALONE_DATA_MODE_MASK)
+
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_FRF_MODE_MASK (0x4U)
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_FRF_MODE_SHIFT (2U)
+/*! CIU2_EXT_FRF_MODE - 0: On Chip BRF is used for 15. */
+#define CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_FRF_MODE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_FRF_MODE_SHIFT)) & CIU2_CIU2_IOMUX_MODE_CTRL_CIU2_EXT_FRF_MODE_MASK)
+/*! @} */
+
+/*! @name CIU2_RST_SW2 - Software Module Reset */
+/*! @{ */
+
+#define CIU2_CIU2_RST_SW2_DRO__MASK              (0x2U)
+#define CIU2_CIU2_RST_SW2_DRO__SHIFT             (1U)
+/*! DRO_ - DRO Clock Reset */
+#define CIU2_CIU2_RST_SW2_DRO_(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_DRO__SHIFT)) & CIU2_CIU2_RST_SW2_DRO__MASK)
+
+#define CIU2_CIU2_RST_SW2_BTAPU_AHB_CLK__MASK    (0x4U)
+#define CIU2_CIU2_RST_SW2_BTAPU_AHB_CLK__SHIFT   (2U)
+/*! BTAPU_AHB_CLK_ - AHB Clock Logic reset for BTAPU */
+#define CIU2_CIU2_RST_SW2_BTAPU_AHB_CLK_(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_BTAPU_AHB_CLK__SHIFT)) & CIU2_CIU2_RST_SW2_BTAPU_AHB_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW2_BTAPU_REF_CLK__MASK    (0x8U)
+#define CIU2_CIU2_RST_SW2_BTAPU_REF_CLK__SHIFT   (3U)
+/*! BTAPU_REF_CLK_ - Ref Clock Logic reset for BTAPU */
+#define CIU2_CIU2_RST_SW2_BTAPU_REF_CLK_(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_BTAPU_REF_CLK__SHIFT)) & CIU2_CIU2_RST_SW2_BTAPU_REF_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW2_BTAPU_SLP_CLK__MASK    (0x10U)
+#define CIU2_CIU2_RST_SW2_BTAPU_SLP_CLK__SHIFT   (4U)
+/*! BTAPU_SLP_CLK_ - Sleep Clock Logic reset for BTAPU */
+#define CIU2_CIU2_RST_SW2_BTAPU_SLP_CLK_(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_BTAPU_SLP_CLK__SHIFT)) & CIU2_CIU2_RST_SW2_BTAPU_SLP_CLK__MASK)
+
+#define CIU2_CIU2_RST_SW2_CIU2_REGISTER_RST__MASK (0x20U)
+#define CIU2_CIU2_RST_SW2_CIU2_REGISTER_RST__SHIFT (5U)
+/*! CIU2_REGISTER_RST_ - CIU_Reg Module Soft Reset */
+#define CIU2_CIU2_RST_SW2_CIU2_REGISTER_RST_(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_CIU2_REGISTER_RST__SHIFT)) & CIU2_CIU2_RST_SW2_CIU2_REGISTER_RST__MASK)
+
+#define CIU2_CIU2_RST_SW2_SMU2_TM__MASK          (0x40U)
+#define CIU2_CIU2_RST_SW2_SMU2_TM__SHIFT         (6U)
+/*! SMU2_TM_ - Test Mode Reset for SMU2 */
+#define CIU2_CIU2_RST_SW2_SMU2_TM_(x)            (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_SMU2_TM__SHIFT)) & CIU2_CIU2_RST_SW2_SMU2_TM__MASK)
+
+#define CIU2_CIU2_RST_SW2_MSC_A2A__MASK          (0x80U)
+#define CIU2_CIU2_RST_SW2_MSC_A2A__SHIFT         (7U)
+/*! MSC_A2A_ - Soft Reset to A2A in MSC */
+#define CIU2_CIU2_RST_SW2_MSC_A2A_(x)            (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_MSC_A2A__SHIFT)) & CIU2_CIU2_RST_SW2_MSC_A2A__MASK)
+
+#define CIU2_CIU2_RST_SW2_SOCCIU_A2A_RST__MASK   (0x100U)
+#define CIU2_CIU2_RST_SW2_SOCCIU_A2A_RST__SHIFT  (8U)
+/*! SOCCIU_A2A_RST_ - Soft Reset to A2A in SOCCIU */
+#define CIU2_CIU2_RST_SW2_SOCCIU_A2A_RST_(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_SOCCIU_A2A_RST__SHIFT)) & CIU2_CIU2_RST_SW2_SOCCIU_A2A_RST__MASK)
+
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_RST__MASK     (0x200U)
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_RST__SHIFT    (9U)
+/*! CIU2_FFU_RST_ - Soft Reset to FFU */
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_RST_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_CIU2_FFU_RST__SHIFT)) & CIU2_CIU2_RST_SW2_CIU2_FFU_RST__MASK)
+
+#define CIU2_CIU2_RST_SW2_CIU2_AHB2APB_SW_RESETN_MASK (0x400U)
+#define CIU2_CIU2_RST_SW2_CIU2_AHB2APB_SW_RESETN_SHIFT (10U)
+/*! CIU2_AHB2APB_SW_RESETN - SW reset to the ahb2apb hresetn */
+#define CIU2_CIU2_RST_SW2_CIU2_AHB2APB_SW_RESETN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_CIU2_AHB2APB_SW_RESETN_SHIFT)) & CIU2_CIU2_RST_SW2_CIU2_AHB2APB_SW_RESETN_MASK)
+
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_AHB_RST__MASK (0x10000U)
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_AHB_RST__SHIFT (16U)
+/*! CIU2_FFU_AHB_RST_ - Soft Reset to FFU AHB I/F logic */
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_AHB_RST_(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_CIU2_FFU_AHB_RST__SHIFT)) & CIU2_CIU2_RST_SW2_CIU2_FFU_AHB_RST__MASK)
+
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_SLP_RST__MASK (0x20000U)
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_SLP_RST__SHIFT (17U)
+/*! CIU2_FFU_SLP_RST_ - Soft Reset to FFU Sleep Clock Domain Logic */
+#define CIU2_CIU2_RST_SW2_CIU2_FFU_SLP_RST_(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_CIU2_FFU_SLP_RST__SHIFT)) & CIU2_CIU2_RST_SW2_CIU2_FFU_SLP_RST__MASK)
+
+#define CIU2_CIU2_RST_SW2_ABH2_SUB_G2BIST_RSTB_MASK (0x40000U)
+#define CIU2_CIU2_RST_SW2_ABH2_SUB_G2BIST_RSTB_SHIFT (18U)
+/*! ABH2_SUB_G2BIST_RSTB - SW reset for ble abh2-system g2bist controller */
+#define CIU2_CIU2_RST_SW2_ABH2_SUB_G2BIST_RSTB(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_ABH2_SUB_G2BIST_RSTB_SHIFT)) & CIU2_CIU2_RST_SW2_ABH2_SUB_G2BIST_RSTB_MASK)
+
+#define CIU2_CIU2_RST_SW2_BLE_AHB_RST__MASK      (0x80000U)
+#define CIU2_CIU2_RST_SW2_BLE_AHB_RST__SHIFT     (19U)
+/*! BLE_AHB_RST_ - SW reset for ble ahb arb/dec/ciu */
+#define CIU2_CIU2_RST_SW2_BLE_AHB_RST_(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_BLE_AHB_RST__SHIFT)) & CIU2_CIU2_RST_SW2_BLE_AHB_RST__MASK)
+
+#define CIU2_CIU2_RST_SW2_CIU2_BTU_SLP_RST__MASK (0x100000U)
+#define CIU2_CIU2_RST_SW2_CIU2_BTU_SLP_RST__SHIFT (20U)
+/*! CIU2_BTU_SLP_RST_ - Soft Reset to BTU Sleep Clock Domain Logic */
+#define CIU2_CIU2_RST_SW2_CIU2_BTU_SLP_RST_(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_CIU2_BTU_SLP_RST__SHIFT)) & CIU2_CIU2_RST_SW2_CIU2_BTU_SLP_RST__MASK)
+
+#define CIU2_CIU2_RST_SW2_MCI_BLE_A2A_MHRESETN_MASK (0x200000U)
+#define CIU2_CIU2_RST_SW2_MCI_BLE_A2A_MHRESETN_SHIFT (21U)
+/*! MCI_BLE_A2A_MHRESETN - SW Reset for mci_wl_a2a_mhresetn */
+#define CIU2_CIU2_RST_SW2_MCI_BLE_A2A_MHRESETN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_MCI_BLE_A2A_MHRESETN_SHIFT)) & CIU2_CIU2_RST_SW2_MCI_BLE_A2A_MHRESETN_MASK)
+
+#define CIU2_CIU2_RST_SW2_CIU2_CFG_RST__MASK     (0x400000U)
+#define CIU2_CIU2_RST_SW2_CIU2_CFG_RST__SHIFT    (22U)
+/*! CIU2_CFG_RST_ - CIU config reset for IMU, RTU, CIU debug sync */
+#define CIU2_CIU2_RST_SW2_CIU2_CFG_RST_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW2_CIU2_CFG_RST__SHIFT)) & CIU2_CIU2_RST_SW2_CIU2_CFG_RST__MASK)
+/*! @} */
+
+/*! @name CIU2_AHB2_TO_CLEAR - AHB2 timeout logic clear register */
+/*! @{ */
+
+#define CIU2_CIU2_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_MASK (0x100U)
+#define CIU2_CIU2_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_SHIFT (8U)
+/*! AHB2_TIMEOUT_CLEAR - After the timeout happened on AHB2 bus, the cpu will read the ERR ISR and
+ *    read the bus state which cause the timeout and then set this bit to 1 to clear the AHB2 timeout
+ *    logic to start recording next transaction. This is self clearing bit
+ */
+#define CIU2_CIU2_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_SHIFT)) & CIU2_CIU2_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_MASK (0x200U)
+#define CIU2_CIU2_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_SHIFT (9U)
+/*! CPU2_DCODE_INV_ADDR_CLR - After the invalid address int happened on CPU2 dcode bus, the cpu2
+ *    will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1
+ *    to clear the CPU2 Dcode invalid addr logic to start recording next transaction. This is self
+ *    clearing bit
+ */
+#define CIU2_CIU2_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_SHIFT)) & CIU2_CIU2_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_MASK)
+
+#define CIU2_CIU2_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_MASK (0x400U)
+#define CIU2_CIU2_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_SHIFT (10U)
+/*! CPU2_ICODE_INV_ADDR_CLR - After the invalid address int happened on CPU2 icode bus, the cpu2
+ *    will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1
+ *    to clear the CPU2 Icode invalid addr logic to start recording next transaction. This is self
+ *    clearing bit
+ */
+#define CIU2_CIU2_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_SHIFT)) & CIU2_CIU2_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU_DYN_CLK_CTRL - Dynamic CPU Clock Control */
+/*! @{ */
+
+#define CIU2_CIU2_CPU_DYN_CLK_CTRL_DYN_CPU2_CTRL_DIS_MASK (0x40000000U)
+#define CIU2_CIU2_CPU_DYN_CLK_CTRL_DYN_CPU2_CTRL_DIS_SHIFT (30U)
+/*! DYN_CPU2_CTRL_DIS - Disable Dynamic CPU2 Clock Control Feature */
+#define CIU2_CIU2_CPU_DYN_CLK_CTRL_DYN_CPU2_CTRL_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_DYN_CLK_CTRL_DYN_CPU2_CTRL_DIS_SHIFT)) & CIU2_CIU2_CPU_DYN_CLK_CTRL_DYN_CPU2_CTRL_DIS_MASK)
+/*! @} */
+
+/*! @name CPU2_DBG_STAT - CPU2 debug register */
+/*! @{ */
+
+#define CIU2_CPU2_DBG_STAT_CPU2_STATUS_MASK      (0xFFFFFFFFU)
+#define CIU2_CPU2_DBG_STAT_CPU2_STATUS_SHIFT     (0U)
+/*! CPU2_STATUS - cpu2 debug output */
+#define CIU2_CPU2_DBG_STAT_CPU2_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_DBG_STAT_CPU2_STATUS_SHIFT)) & CIU2_CPU2_DBG_STAT_CPU2_STATUS_MASK)
+/*! @} */
+
+/*! @name BTSS_MBIST_STAT -  */
+/*! @{ */
+
+#define CIU2_BTSS_MBIST_STAT_BLESS_MBIST_FAIL_MASK (0x1FFU)
+#define CIU2_BTSS_MBIST_STAT_BLESS_MBIST_FAIL_SHIFT (0U)
+/*! BLESS_MBIST_FAIL - BIST Fail Indication from memories in BT Sub System */
+#define CIU2_BTSS_MBIST_STAT_BLESS_MBIST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_BTSS_MBIST_STAT_BLESS_MBIST_FAIL_SHIFT)) & CIU2_BTSS_MBIST_STAT_BLESS_MBIST_FAIL_MASK)
+
+#define CIU2_BTSS_MBIST_STAT_BLESS_MBIST_READY_MASK (0x1FF0000U)
+#define CIU2_BTSS_MBIST_STAT_BLESS_MBIST_READY_SHIFT (16U)
+/*! BLESS_MBIST_READY - BIST Ready from memories in BT Sub System */
+#define CIU2_BTSS_MBIST_STAT_BLESS_MBIST_READY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_BTSS_MBIST_STAT_BLESS_MBIST_READY_SHIFT)) & CIU2_BTSS_MBIST_STAT_BLESS_MBIST_READY_MASK)
+/*! @} */
+
+/*! @name CIU2_TEST_MODE - " */
+/*! @{ */
+
+#define CIU2_CIU2_TEST_MODE_BT_UART_MODE_MASK    (0x1U)
+#define CIU2_CIU2_TEST_MODE_BT_UART_MODE_SHIFT   (0U)
+/*! BT_UART_MODE - Indicates UART Mode for I/O muxing */
+#define CIU2_CIU2_TEST_MODE_BT_UART_MODE(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_TEST_MODE_BT_UART_MODE_SHIFT)) & CIU2_CIU2_TEST_MODE_BT_UART_MODE_MASK)
+/*! @} */
+
+/*! @name CIU2_APU_BYPASS2 - CIU2 APU Bypass Register 2 */
+/*! @{ */
+
+#define CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_SEL_MASK (0xC0000U)
+#define CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_SEL_SHIFT (18U)
+/*! TBG_FFU_CLK_EN_BYPASS_SEL - TBG FFU clock enable bypass select */
+#define CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_SEL_SHIFT)) & CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_SEL_MASK)
+
+#define CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_VAL_MASK (0x100000U)
+#define CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_VAL_SHIFT (20U)
+/*! TBG_FFU_CLK_EN_BYPASS_VAL - TBG FFU clock enable bypass value */
+#define CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS2_TBG_FFU_CLK_EN_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name CIU2_TST_G2BIST_STATUS - WL G2BIST Status */
+/*! @{ */
+
+#define CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_STATUS_MASK (0xFU)
+#define CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_STATUS_SHIFT (0U)
+/*! AHB2_G2B_STATUS - Redundant Bist Selection */
+#define CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_STATUS_SHIFT)) & CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_STATUS_MASK)
+
+#define CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_FINIH_MASK (0x100U)
+#define CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_FINIH_SHIFT (8U)
+/*! AHB2_G2B_FINIH - AHB2 Bist Done */
+#define CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_FINIH(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_FINIH_SHIFT)) & CIU2_CIU2_TST_G2BIST_STATUS_AHB2_G2B_FINIH_MASK)
+/*! @} */
+
+/*! @name CIU2_LPO_CLK_GEN_CTRL - BLE LPO CLK GEN Control */
+/*! @{ */
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_AUTO_DEJIT_MASK (0x1U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_AUTO_DEJIT_SHIFT (0U)
+/*! AUTO_DEJIT - Enable Auto Dejitter */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_AUTO_DEJIT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_AUTO_DEJIT_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_AUTO_DEJIT_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_DEJIT_EN_MASK (0x2U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_DEJIT_EN_SHIFT (1U)
+/*! DEJIT_EN - Enable De-jitter block */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_DEJIT_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_DEJIT_EN_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_DEJIT_EN_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_MAN_SEL_NCO_MASK (0x4U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_MAN_SEL_NCO_SHIFT (2U)
+/*! MAN_SEL_NCO - Manually Switch back to NCO Version */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_MAN_SEL_NCO(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_MAN_SEL_NCO_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_MAN_SEL_NCO_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_NCO_EN_MASK (0x8U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_NCO_EN_SHIFT (3U)
+/*! SLP_CLK_NCO_EN - Enable NCO Counter in ble_lpoClk_gen */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_NCO_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_NCO_EN_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_NCO_EN_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_LBC_DEBUG_CTRL_MASK (0x30U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_LBC_DEBUG_CTRL_SHIFT (4U)
+/*! LBC_DEBUG_CTRL - LBC Debug Control Signal */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_LBC_DEBUG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_LBC_DEBUG_CTRL_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_LBC_DEBUG_CTRL_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_RST__MASK (0x40U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_RST__SHIFT (6U)
+/*! SLP_CLK_RST_ - Soft Reset to LPO Clock Generator for NCO Sleep Clock Domain Logic */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_RST_(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_RST__SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_SLP_CLK_RST__MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_REF_4M_RST__MASK (0x80U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_REF_4M_RST__SHIFT (7U)
+/*! REF_4M_RST_ - Soft Reset to LPO Clock Generator for 4M Clock Domain Logic */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_REF_4M_RST_(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_REF_4M_RST__SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_REF_4M_RST__MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_LPO_CLK_SEL_MASK (0x300U)
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_LPO_CLK_SEL_SHIFT (8U)
+/*! LPO_CLK_SEL - Selects the source of 4 MHz clock input to BLE LPO Clock Generator */
+#define CIU2_CIU2_LPO_CLK_GEN_CTRL_LPO_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_CTRL_LPO_CLK_SEL_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_CTRL_LPO_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CIU2_LPO_CLK_GEN_STATUS - BLE LPO CLK GEN Status */
+/*! @{ */
+
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_3K2_CNT_MASK (0x1FU)
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_3K2_CNT_SHIFT (0U)
+/*! LPO_CLK_3K2_CNT - " */
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_3K2_CNT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_3K2_CNT_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_3K2_CNT_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_SEL_FSM_MASK (0x100U)
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_SEL_FSM_SHIFT (8U)
+/*! LPO_CLK_SEL_FSM - " */
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_SEL_FSM(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_SEL_FSM_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_STATUS_LPO_CLK_SEL_FSM_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_RAMP_DN_MASK (0x200U)
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_RAMP_DN_SHIFT (9U)
+/*! REF_LPO_RAMP_DN - " */
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_RAMP_DN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_RAMP_DN_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_RAMP_DN_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_CLK_GOOD_MASK (0x400U)
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_CLK_GOOD_SHIFT (10U)
+/*! REF_LPO_CLK_GOOD - " */
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_CLK_GOOD(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_CLK_GOOD_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_STATUS_REF_LPO_CLK_GOOD_MASK)
+
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_NCO_LPO_RAMP_DN_LV_MASK (0x800U)
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_NCO_LPO_RAMP_DN_LV_SHIFT (11U)
+/*! NCO_LPO_RAMP_DN_LV - " */
+#define CIU2_CIU2_LPO_CLK_GEN_STATUS_NCO_LPO_RAMP_DN_LV(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_CLK_GEN_STATUS_NCO_LPO_RAMP_DN_LV_SHIFT)) & CIU2_CIU2_LPO_CLK_GEN_STATUS_NCO_LPO_RAMP_DN_LV_MASK)
+/*! @} */
+
+/*! @name CIU2_LPO_SLP_CLK_GEN_CTRL - " */
+/*! @{ */
+
+#define CIU2_CIU2_LPO_SLP_CLK_GEN_CTRL_SLP_CLK_NCO_STEP_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_LPO_SLP_CLK_GEN_CTRL_SLP_CLK_NCO_STEP_SHIFT (0U)
+/*! SLP_CLK_NCO_STEP - " */
+#define CIU2_CIU2_LPO_SLP_CLK_GEN_CTRL_SLP_CLK_NCO_STEP(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LPO_SLP_CLK_GEN_CTRL_SLP_CLK_NCO_STEP_SHIFT)) & CIU2_CIU2_LPO_SLP_CLK_GEN_CTRL_SLP_CLK_NCO_STEP_MASK)
+/*! @} */
+
+/*! @name CPU2_INT_CTRL - " */
+/*! @{ */
+
+#define CIU2_CPU2_INT_CTRL_CPU2_CPU3_GP_INT_MASK (0xFU)
+#define CIU2_CPU2_INT_CTRL_CPU2_CPU3_GP_INT_SHIFT (0U)
+/*! CPU2_CPU3_GP_INT - General Purpose Interrupt in Secure Region */
+#define CIU2_CPU2_INT_CTRL_CPU2_CPU3_GP_INT(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_INT_CTRL_CPU2_CPU3_GP_INT_SHIFT)) & CIU2_CPU2_INT_CTRL_CPU2_CPU3_GP_INT_MASK)
+/*! @} */
+
+/*! @name CIU2_BRF_EXTRA_PORT_STATUS - " */
+/*! @{ */
+
+#define CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_CIU2_EXTRA_STATUS_MASK (0x3U)
+#define CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_CIU2_EXTRA_STATUS_SHIFT (0U)
+/*! BRF_CIU2_EXTRA_STATUS - [1:0] of BRF_SOC_EXTRA output of BRF are made available as status register bits. */
+#define CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_CIU2_EXTRA_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_CIU2_EXTRA_STATUS_SHIFT)) & CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_CIU2_EXTRA_STATUS_MASK)
+
+#define CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_ERR_FLAG_MASK (0x100U)
+#define CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_ERR_FLAG_SHIFT (8U)
+/*! BRF_ERR_FLAG - Error Flag Output from BRF is reported here. */
+#define CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_ERR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_ERR_FLAG_SHIFT)) & CIU2_CIU2_BRF_EXTRA_PORT_STATUS_BRF_ERR_FLAG_MASK)
+/*! @} */
+
+/*! @name CIU2_DEBUG - " */
+/*! @{ */
+
+#define CIU2_CIU2_DEBUG_P2C_UART_SIN_MASK        (0x1U)
+#define CIU2_CIU2_DEBUG_P2C_UART_SIN_SHIFT       (0U)
+/*! P2C_UART_SIN - Status of UART SIN (p2c_uart_sin) net is captured here. */
+#define CIU2_CIU2_DEBUG_P2C_UART_SIN(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_DEBUG_P2C_UART_SIN_SHIFT)) & CIU2_CIU2_DEBUG_P2C_UART_SIN_MASK)
+/*! @} */
+
+/*! @name CIU2_MCI_EXTRA - MCI EXTRA Ports */
+/*! @{ */
+
+#define CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_OUT_MASK (0xFU)
+#define CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_OUT_SHIFT (0U)
+/*! CIU2_MCI_EXTRA_OUT - Extra Ports to MCI */
+#define CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_OUT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_OUT_SHIFT)) & CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_OUT_MASK)
+
+#define CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_IN_MASK (0xF0U)
+#define CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_IN_SHIFT (4U)
+/*! CIU2_MCI_EXTRA_IN - Extra Ports from MCI */
+#define CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_IN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_IN_SHIFT)) & CIU2_CIU2_MCI_EXTRA_CIU2_MCI_EXTRA_IN_MASK)
+/*! @} */
+
+/*! @name CIU2_TSTBUS_SEL - Test Bus Select */
+/*! @{ */
+
+#define CIU2_CIU2_TSTBUS_SEL_AHB2_TSTBUS_SEL_MASK (0x1U)
+#define CIU2_CIU2_TSTBUS_SEL_AHB2_TSTBUS_SEL_SHIFT (0U)
+/*! AHB2_TSTBUS_SEL - Select between 2 groups of signals; The output of the mux is driven to BLE
+ *    Test Mux Logic so that it can be observed on GPIOs.
+ */
+#define CIU2_CIU2_TSTBUS_SEL_AHB2_TSTBUS_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_TSTBUS_SEL_AHB2_TSTBUS_SEL_SHIFT)) & CIU2_CIU2_TSTBUS_SEL_AHB2_TSTBUS_SEL_MASK)
+
+#define CIU2_CIU2_TSTBUS_SEL_SMU2_TSTBUS_SEL_MASK (0x10U)
+#define CIU2_CIU2_TSTBUS_SEL_SMU2_TSTBUS_SEL_SHIFT (4U)
+/*! SMU2_TSTBUS_SEL - Selects between following 2 Test Buses in SMU2 */
+#define CIU2_CIU2_TSTBUS_SEL_SMU2_TSTBUS_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_TSTBUS_SEL_SMU2_TSTBUS_SEL_SHIFT)) & CIU2_CIU2_TSTBUS_SEL_SMU2_TSTBUS_SEL_MASK)
+/*! @} */
+
+/*! @name FFU_CTRL - FFU Specific Control Register */
+/*! @{ */
+
+#define CIU2_FFU_CTRL_USE_TX_EN_EXTEND_MASK      (0x1U)
+#define CIU2_FFU_CTRL_USE_TX_EN_EXTEND_SHIFT     (0U)
+/*! USE_TX_EN_EXTEND - Selects tx_en_extend port of FFU & drives it on c2p_soc_zigbee_tx_en. */
+#define CIU2_FFU_CTRL_USE_TX_EN_EXTEND(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_FFU_CTRL_USE_TX_EN_EXTEND_SHIFT)) & CIU2_FFU_CTRL_USE_TX_EN_EXTEND_MASK)
+/*! @} */
+
+/*! @name BLE_RAACS_CTRL - RAACS control registers */
+/*! @{ */
+
+#define CIU2_BLE_RAACS_CTRL_RAACS_EN_MASK        (0x1U)
+#define CIU2_BLE_RAACS_CTRL_RAACS_EN_SHIFT       (0U)
+/*! RAACS_EN - raacs en . S/W Write 1 to enable raacs block. */
+#define CIU2_BLE_RAACS_CTRL_RAACS_EN(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_BLE_RAACS_CTRL_RAACS_EN_SHIFT)) & CIU2_BLE_RAACS_CTRL_RAACS_EN_MASK)
+
+#define CIU2_BLE_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_MASK (0x2U)
+#define CIU2_BLE_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_SHIFT (1U)
+/*! USE_RAACS_CLK_FOR_CPU - SW write 0 to use RAACS clock for CPU. SW write 1 to select clock gating
+ *    based alternate implementation of RAACS clocking for CM3 CPU.
+ */
+#define CIU2_BLE_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU(x) (((uint32_t)(((uint32_t)(x)) << CIU2_BLE_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_SHIFT)) & CIU2_BLE_RAACS_CTRL_USE_RAACS_CLK_FOR_CPU_MASK)
+
+#define CIU2_BLE_RAACS_CTRL_RAACS_CLK_SEL_MASK   (0x1CU)
+#define CIU2_BLE_RAACS_CTRL_RAACS_CLK_SEL_SHIFT  (2U)
+/*! RAACS_CLK_SEL - defines the lowest clock to which RAACS will go down to during IDLE period (x/2;
+ *    x/4; x/8; ... ;x/128) for the given test.
+ */
+#define CIU2_BLE_RAACS_CTRL_RAACS_CLK_SEL(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_BLE_RAACS_CTRL_RAACS_CLK_SEL_SHIFT)) & CIU2_BLE_RAACS_CTRL_RAACS_CLK_SEL_MASK)
+
+#define CIU2_BLE_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_MASK (0x7FFE0U)
+#define CIU2_BLE_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_SHIFT (5U)
+/*! RAACS_WAIT_COUNTER_VALUE - initial IDLE-time for which RAACS FSM waits before starting to scale down the clock. */
+#define CIU2_BLE_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_BLE_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_SHIFT)) & CIU2_BLE_RAACS_CTRL_RAACS_WAIT_COUNTER_VALUE_MASK)
+
+#define CIU2_BLE_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_MASK (0xFFF80000U)
+#define CIU2_BLE_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_SHIFT (19U)
+/*! RAACS_IDLE_COUNTER_VALUE - IDLE time for which RAACS-FSM waits before shifting to next successive scaled clock. */
+#define CIU2_BLE_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_BLE_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_SHIFT)) & CIU2_BLE_RAACS_CTRL_RAACS_IDLE_COUNTER_VALUE_MASK)
+/*! @} */
+
+/*! @name BLE_RAACS_PERFORMANCE_STATISTICS - RAACS performance statistics counter. */
+/*! @{ */
+
+#define CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_MASK (0x1U)
+#define CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_SHIFT (0U)
+/*! PERFORMANCE_STATISTICS_CNT_EN - performance counter en. S/W write 1 to enable performance counter. */
+#define CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_SHIFT)) & CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_PERFORMANCE_STATISTICS_CNT_EN_MASK)
+
+#define CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_MASK (0xFFFFFFEU)
+#define CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_SHIFT (1U)
+/*! RAACS_PERFORMANCE_STATISTICS - This counter is maintaining RAACS performance count. This counter
+ *    will increment by one after every 1 us(1MHZ) when RAACS is in scaled clk state.
+ */
+#define CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_SHIFT)) & CIU2_BLE_RAACS_PERFORMANCE_STATISTICS_RAACS_PERFORMANCE_STATISTICS_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU_CPU2_MSG_CTRL - CPU2 message register */
+/*! @{ */
+
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_RDY_MASK (0x1U)
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_RDY_SHIFT (0U)
+/*! CPU2_TO_CPU3_MSG_RDY - CPU2 Message for CPU3 is ready. This is self clearing bit. The CPU2
+ *    writes 1 to indicate that message for CPU3is ready. This generates an Interrupt to CPU3 via APU.
+ *    This is old scheme and we should use IMU based scheme.
+ */
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_RDY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_RDY_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_RDY_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_MASK (0x2U)
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_SHIFT (1U)
+/*! CPU3_TO_CPU2_MSG_RDY - CPU3 Message for CPU2 is ready. This is self clearing bit. The CPU3
+ *    writes 1 to indicate that message for CPU2 is ready. This generates an Interrupt to CPU2 via APU.
+ *    This is old scheme and we should use IMU based scheme.
+ */
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_PROCESS_DONE_MASK (0x100U)
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_PROCESS_DONE_SHIFT (8U)
+/*! CPU2_TO_CPU3_MSG_PROCESS_DONE - CPU2 Message for CPU3 has been read by CPU3 and executed. This
+ *    is self clearing bit. The CPU3 writes 1 to indicate that message send by CPU2 is executed. This
+ *    generates an Interrupt to CPU2 via CIU1.
+ */
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_PROCESS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_PROCESS_DONE_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU2_TO_CPU3_MSG_PROCESS_DONE_MASK)
+
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_MASK (0x200U)
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_SHIFT (9U)
+/*! CPU3_TO_CPU2_MSG_PROCESS_DONE - CPU3 Message for CPU2 has been read by CPU2 and executed. This
+ *    is self clearing bit. The CPU2 writes 1 to indicate that message send by CPU3 is executed. This
+ *    generates an Interrupt to CPU3 via CIU1.
+ */
+#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU3_WR_MSG_TO_CPU2 - CPU3 write message to CPU2 */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU3_WR_MSG_TO_CPU2_CPU3_WR_MSG_CPU2_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_IMU_CPU3_WR_MSG_TO_CPU2_CPU3_WR_MSG_CPU2_SHIFT (0U)
+/*! CPU3_WR_MSG_CPU2 - Write CPU3 message data to CPU2 (push to FIFO) */
+#define CIU2_CIU2_IMU_CPU3_WR_MSG_TO_CPU2_CPU3_WR_MSG_CPU2(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_WR_MSG_TO_CPU2_CPU3_WR_MSG_CPU2_SHIFT)) & CIU2_CIU2_IMU_CPU3_WR_MSG_TO_CPU2_CPU3_WR_MSG_CPU2_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU3_RD_MSG_FROM_CPU2 - CPU3 read message from CPU2 */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_CPU3_RD_MSG_CPU2_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_CPU3_RD_MSG_CPU2_SHIFT (0U)
+/*! CPU3_RD_MSG_CPU2 - CPU3 read message data from CPU2 (pop from FIFO) */
+#define CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_CPU3_RD_MSG_CPU2(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_CPU3_RD_MSG_CPU2_SHIFT)) & CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_CPU3_RD_MSG_CPU2_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS - CPU3 to CPU2 message FIFO status */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_LOCKED_MASK (0x1U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_LOCKED_SHIFT (0U)
+/*! CPU3_TO_CPU2_MSG_FIFO_LOCKED - cpu3_to_cpu2_msg_fifo_locked */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_LOCKED_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_LOCKED_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_ALMOST_FULL_MASK (0x2U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_ALMOST_FULL_SHIFT (1U)
+/*! CPU3_TO_CPU2_MSG_FIFO_ALMOST_FULL - cpu3_to_cpu2_msg_fifo_almost_full (based upon FIFO watermark) */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_ALMOST_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_ALMOST_FULL_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_FULL_MASK (0x4U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_FULL_SHIFT (2U)
+/*! CPU3_TO_CPU2_MSG_FIFO_FULL - cpu3_to_cpu2_msg_fifo_full (based upon FIFO depth) */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_FULL_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_EMPTY_MASK (0x8U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_EMPTY_SHIFT (3U)
+/*! CPU3_TO_CPU2_MSG_FIFO_EMPTY - cpu3_to_cpu2_msg_fifo_empty */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_EMPTY_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_EMPTY_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_COUNT_MASK (0x1F0U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_COUNT_SHIFT (4U)
+/*! CPU3_TO_CPU2_MSG_COUNT - cpu3_to_cpu2_msg_count */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_COUNT_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_COUNT_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_WR_PTR_MASK (0xF0000U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_WR_PTR_SHIFT (16U)
+/*! CPU3_TO_CPU2_MSG_FIFO_WR_PTR - cpu3 to cpu2 msg fifo write pointer for debug */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_WR_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_WR_PTR_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_RD_PTR_MASK (0xF00000U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_RD_PTR_SHIFT (20U)
+/*! CPU3_TO_CPU2_MSG_FIFO_RD_PTR - cpu3 to cpu2 msg fifo read pointer for debug */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_RD_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS_CPU3_TO_CPU2_MSG_FIFO_RD_PTR_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL - CPU3 to CPU2 message FIFO control */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_MASK (0x1U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_SHIFT (0U)
+/*! CPU3_MSG_RDY_INT_CLR - Writing 1 to this bit will clear message ready interrupt to CPU3 (self clear bit) */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_RDY_INT_CLR_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_MASK (0x100U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_SHIFT (8U)
+/*! CPU3_MSG_SP_AV_INT_CLR - Writing 1 to this bit will clear message space available interrupt to CPU3 (self clear bit) */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_MSG_SP_AV_INT_CLR_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_TO_CPU2_MSG_FIFO_FLUSH_MASK (0x10000U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_TO_CPU2_MSG_FIFO_FLUSH_SHIFT (16U)
+/*! CPU3_TO_CPU2_MSG_FIFO_FLUSH - Writing 1 to this bit will flush cpu3_to_cpu2 message fifo */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_TO_CPU2_MSG_FIFO_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_TO_CPU2_MSG_FIFO_FLUSH_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_TO_CPU2_MSG_FIFO_FLUSH_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_MASK (0x20000U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_SHIFT (17U)
+/*! CPU3_WAIT_FOR_ACK - CPU3 wait for Acknowledgment */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_WAIT_FOR_ACK_MASK)
+
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_CPU2_MSG_FIFO_FULL_WATERMARK_MASK (0xF00000U)
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_CPU2_MSG_FIFO_FULL_WATERMARK_SHIFT (20U)
+/*! CPU3_CPU2_MSG_FIFO_FULL_WATERMARK - cpu3_to_cpu2 message fifo full watermark (space avail intr based upon it) */
+#define CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_CPU2_MSG_FIFO_FULL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_CPU2_MSG_FIFO_FULL_WATERMARK_SHIFT)) & CIU2_CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL_CPU3_CPU2_MSG_FIFO_FULL_WATERMARK_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG - CPU2 last message read (from cpu3) */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG_CPU2_RD_MSG_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG_CPU2_RD_MSG_SHIFT (0U)
+/*! CPU2_RD_MSG - CPU2 last message read (from cpu3) */
+#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG_CPU2_RD_MSG(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG_CPU2_RD_MSG_SHIFT)) & CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG_CPU2_RD_MSG_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU2_WR_MSG_TO_CPU3 - CPU2 write message to CPU3 */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU3_CPU2_WR_MSG_CPU3_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU3_CPU2_WR_MSG_CPU3_SHIFT (0U)
+/*! CPU2_WR_MSG_CPU3 - Write CPU2 message data to CPU3 (push to FIFO) */
+#define CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU3_CPU2_WR_MSG_CPU3(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU3_CPU2_WR_MSG_CPU3_SHIFT)) & CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU3_CPU2_WR_MSG_CPU3_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU2_RD_MSG_FROM_CPU3 - CPU2 read message from CPU3 */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_CPU2_RD_MSG_CPU3_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_CPU2_RD_MSG_CPU3_SHIFT (0U)
+/*! CPU2_RD_MSG_CPU3 - CPU2 read message data from CPU3 (pop from FIFO) */
+#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_CPU2_RD_MSG_CPU3(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_CPU2_RD_MSG_CPU3_SHIFT)) & CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_CPU2_RD_MSG_CPU3_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS - CPU2 to CPU3 message FIFO status */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_LOCKED_MASK (0x1U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_LOCKED_SHIFT (0U)
+/*! CPU2_TO_CPU3_MSG_FIFO_LOCKED - cpu2_to_cpu3_msg_fifo_locked */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_LOCKED_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_LOCKED_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_ALMOST_FULL_MASK (0x2U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_ALMOST_FULL_SHIFT (1U)
+/*! CPU2_TO_CPU3_MSG_FIFO_ALMOST_FULL - cpu2_to_cpu3_msg_fifo_almost_full (based upon FIFO watermark) */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_ALMOST_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_ALMOST_FULL_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_FULL_MASK (0x4U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_FULL_SHIFT (2U)
+/*! CPU2_TO_CPU3_MSG_FIFO_FULL - cpu2_to_cpu3_msg_fifo_full (based upon FIFO depth) */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_FULL_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_EMPTY_MASK (0x8U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_EMPTY_SHIFT (3U)
+/*! CPU2_TO_CPU3_MSG_FIFO_EMPTY - cpu2_to_cpu3_msg_fifo_empty */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_EMPTY_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_EMPTY_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_COUNT_MASK (0x1F0U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_COUNT_SHIFT (4U)
+/*! CPU2_TO_CPU3_MSG_COUNT - cpu2_to_cpu3_msg_count */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_COUNT_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_COUNT_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_WR_PTR_MASK (0xF0000U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_WR_PTR_SHIFT (16U)
+/*! CPU2_TO_CPU3_MSG_FIFO_WR_PTR - cpu3 to cpu2 msg fifo write pointer for debug */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_WR_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_WR_PTR_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_RD_PTR_MASK (0xF00000U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_RD_PTR_SHIFT (20U)
+/*! CPU2_TO_CPU3_MSG_FIFO_RD_PTR - cpu3 to cpu2 msg fifo read pointer for debug */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_RD_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS_CPU2_TO_CPU3_MSG_FIFO_RD_PTR_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL - CPU2 to CPU3 message FIFO control */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_MASK (0x1U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_SHIFT (0U)
+/*! CPU2_MSG_RDY_INT_CLR - Writing 1 to this bit will clear message ready interrupt to CPU2 (self clear bit) */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_MASK (0x100U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_SHIFT (8U)
+/*! CPU2_MSG_SP_AV_INT_CLR - Writing 1 to this bit will clear message space available interrupt to CPU2 (self clear bit) */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_TO_CPU3_MSG_FIFO_FLUSH_MASK (0x10000U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_TO_CPU3_MSG_FIFO_FLUSH_SHIFT (16U)
+/*! CPU2_TO_CPU3_MSG_FIFO_FLUSH - Writing 1 to this bit will flush cpu2_to_cpu3 message fifo */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_TO_CPU3_MSG_FIFO_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_TO_CPU3_MSG_FIFO_FLUSH_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_TO_CPU3_MSG_FIFO_FLUSH_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_MASK (0x20000U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_SHIFT (17U)
+/*! CPU2_WAIT_FOR_ACK - CPU2 wait for Acknowledgment */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_MASK)
+
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_CPU3_MSG_FIFO_FULL_WATERMARK_MASK (0xF00000U)
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_CPU3_MSG_FIFO_FULL_WATERMARK_SHIFT (20U)
+/*! CPU2_CPU3_MSG_FIFO_FULL_WATERMARK - cpu2_to_cpu3 message fifo full watermark (space avail intr based upon it) */
+#define CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_CPU3_MSG_FIFO_FULL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_CPU3_MSG_FIFO_FULL_WATERMARK_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL_CPU2_CPU3_MSG_FIFO_FULL_WATERMARK_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG - CPU3 last message read (from cpu2) */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG_CPU3_RD_MSG_MASK (0xFFFFFFFFU)
+#define CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG_CPU3_RD_MSG_SHIFT (0U)
+/*! CPU3_RD_MSG - CPU3 last message read (from cpu2) */
+#define CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG_CPU3_RD_MSG(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG_CPU3_RD_MSG_SHIFT)) & CIU2_CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG_CPU3_RD_MSG_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU3_WAKEUP_CTRL - CIU2 register to wakeup CPU3 */
+/*! @{ */
+
+#define CIU2_CIU2_CPU3_WAKEUP_CTRL_CPU3_WAKE_UP_MASK (0x1U)
+#define CIU2_CIU2_CPU3_WAKEUP_CTRL_CPU3_WAKE_UP_SHIFT (0U)
+/*! CPU3_WAKE_UP - CPU3 Wakeup Control Register. S/W Write 1 to generate a wake up interrupt to
+ *    CPU3.Clear by S/W once mci_wl_wakeup_done[1] interrupt is received from CPU3.
+ */
+#define CIU2_CIU2_CPU3_WAKEUP_CTRL_CPU3_WAKE_UP(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU3_WAKEUP_CTRL_CPU3_WAKE_UP_SHIFT)) & CIU2_CIU2_CPU3_WAKEUP_CTRL_CPU3_WAKE_UP_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU2_WAKEUP_DONE - Wakeup done Control Register to CPU3 */
+/*! @{ */
+
+#define CIU2_CIU2_CPU2_WAKEUP_DONE_CPU2_WAKEUP_DONE_MASK (0xFFU)
+#define CIU2_CIU2_CPU2_WAKEUP_DONE_CPU2_WAKEUP_DONE_SHIFT (0U)
+/*! CPU2_WAKEUP_DONE - CPU2 Wakeup is done . This bit is set to 1 by S/W when CPU3 wakesup CPU2.This
+ *    is self clearing bit. This generates an interrupt to CPU3 via wl_mci_wakeup_done[7:0] signal.
+ */
+#define CIU2_CIU2_CPU2_WAKEUP_DONE_CPU2_WAKEUP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_WAKEUP_DONE_CPU2_WAKEUP_DONE_SHIFT)) & CIU2_CIU2_CPU2_WAKEUP_DONE_CPU2_WAKEUP_DONE_MASK)
+/*! @} */
+
+/*! @name CIU2_CPU3_NS_GP_INT - Non Secure region GP interrupt to CPU3 */
+/*! @{ */
+
+#define CIU2_CIU2_CPU3_NS_GP_INT_CPU2_CPU3_GP_NS_INT_MASK (0x3U)
+#define CIU2_CIU2_CPU3_NS_GP_INT_CPU2_CPU3_GP_NS_INT_SHIFT (0U)
+/*! CPU2_CPU3_GP_NS_INT - General Purpose interrupt to CPU3 from non secure registers */
+#define CIU2_CIU2_CPU3_NS_GP_INT_CPU2_CPU3_GP_NS_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU3_NS_GP_INT_CPU2_CPU3_GP_NS_INT_SHIFT)) & CIU2_CIU2_CPU3_NS_GP_INT_CPU2_CPU3_GP_NS_INT_MASK)
+/*! @} */
+
+/*! @name CIU2_IMU_ECO_BITS - IMU ECO Control */
+/*! @{ */
+
+#define CIU2_CIU2_IMU_ECO_BITS_IMU_ECO_BITS_MASK (0xFFFFU)
+#define CIU2_CIU2_IMU_ECO_BITS_IMU_ECO_BITS_SHIFT (0U)
+/*! IMU_ECO_BITS - Reserved for ECOs */
+#define CIU2_CIU2_IMU_ECO_BITS_IMU_ECO_BITS(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_ECO_BITS_IMU_ECO_BITS_SHIFT)) & CIU2_CIU2_IMU_ECO_BITS_IMU_ECO_BITS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CIU2_Register_Masks */
+
+
+/* CIU2 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral BLECTRL base address */
+  #define BLECTRL_BASE                             (0x54240000u)
+  /** Peripheral BLECTRL base address */
+  #define BLECTRL_BASE_NS                          (0x44240000u)
+  /** Peripheral BLECTRL base pointer */
+  #define BLECTRL                                  ((CIU2_Type *)BLECTRL_BASE)
+  /** Peripheral BLECTRL base pointer */
+  #define BLECTRL_NS                               ((CIU2_Type *)BLECTRL_BASE_NS)
+  /** Array initializer of CIU2 peripheral base addresses */
+  #define CIU2_BASE_ADDRS                          { BLECTRL_BASE }
+  /** Array initializer of CIU2 peripheral base pointers */
+  #define CIU2_BASE_PTRS                           { BLECTRL }
+  /** Array initializer of CIU2 peripheral base addresses */
+  #define CIU2_BASE_ADDRS_NS                       { BLECTRL_BASE_NS }
+  /** Array initializer of CIU2 peripheral base pointers */
+  #define CIU2_BASE_PTRS_NS                        { BLECTRL_NS }
+#else
+  /** Peripheral BLECTRL base address */
+  #define BLECTRL_BASE                             (0x44240000u)
+  /** Peripheral BLECTRL base pointer */
+  #define BLECTRL                                  ((CIU2_Type *)BLECTRL_BASE)
+  /** Array initializer of CIU2 peripheral base addresses */
+  #define CIU2_BASE_ADDRS                          { BLECTRL_BASE }
+  /** Array initializer of CIU2 peripheral base pointers */
+  #define CIU2_BASE_PTRS                           { BLECTRL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CIU2_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CLKCTL0 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL0_Peripheral_Access_Layer CLKCTL0 Peripheral Access Layer
+ * @{
+ */
+
+/** CLKCTL0 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t PSCCTL0;                           /**< clock control 0, offset: 0x10 */
+  __IO uint32_t PSCCTL1;                           /**< clock control 1, offset: 0x14 */
+  __IO uint32_t PSCCTL2;                           /**< clock control 2, offset: 0x18 */
+       uint8_t RESERVED_1[36];
+  __O  uint32_t PSCCTL0_SET;                       /**< Peripheral clock set 0, offset: 0x40 */
+  __O  uint32_t PSCCTL1_SET;                       /**< Peripheral clock set 1, offset: 0x44 */
+  __O  uint32_t PSCCTL2_SET;                       /**< Peripheral clock set 2, offset: 0x48 */
+       uint8_t RESERVED_2[36];
+  __O  uint32_t PSCCTL0_CLR;                       /**< Peripheral clock clear 0, offset: 0x70 */
+  __O  uint32_t PSCCTL1_CLR;                       /**< Peripheral clock clear 1, offset: 0x74 */
+  __O  uint32_t PSCCTL2_CLR;                       /**< Peripheral clock clear 2, offset: 0x78 */
+       uint8_t RESERVED_3[236];
+  __IO uint32_t SYSOSCBYPASS;                      /**< System oscillator bypass, offset: 0x168 */
+       uint8_t RESERVED_4[84];
+  __IO uint32_t CLK32KHZCTL0;                      /**< 32k control 0, offset: 0x1C0 */
+       uint8_t RESERVED_5[124];
+  __IO uint32_t MAINPLLCLKDIV;                     /**< Main PLL clock divider, offset: 0x240 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t AUX0PLLCLKDIV;                     /**< AUX0 PLL clock divider, offset: 0x248 */
+  __IO uint32_t AUX1PLLCLKDIV;                     /**< AUX1 PLL clock divider, offset: 0x24C */
+       uint8_t RESERVED_7[432];
+  __IO uint32_t SYSCPUAHBCLKDIV;                   /**< System CPU AHB clock divider, offset: 0x400 */
+       uint8_t RESERVED_8[44];
+  __IO uint32_t MAINCLKSELA;                       /**< Main clock selection A, offset: 0x430 */
+  __IO uint32_t MAINCLKSELB;                       /**< Main clock selection B, offset: 0x434 */
+       uint8_t RESERVED_9[488];
+  __IO uint32_t FLEXSPIFCLKSEL;                    /**< FlexSPI FCLK selection, offset: 0x620 */
+  __IO uint32_t FLEXSPIFCLKDIV;                    /**< FlexSPI FCLK divider, offset: 0x624 */
+       uint8_t RESERVED_10[24];
+  __IO uint32_t SCTFCLKSEL;                        /**< SCT FCLK selection, offset: 0x640 */
+  __IO uint32_t SCTFCLKDIV;                        /**< SCT FCLK divider, offset: 0x644 */
+       uint8_t RESERVED_11[184];
+  __IO uint32_t UTICKFCLKSEL;                      /**< UTICK FCLK selection, offset: 0x700 */
+       uint8_t RESERVED_12[28];
+  __IO uint32_t WDT0FCLKSEL;                       /**< WDT clock selection, offset: 0x720 */
+       uint8_t RESERVED_13[60];
+  __IO uint32_t SYSTICKFCLKSEL;                    /**< System tick FCLK selection, offset: 0x760 */
+  __IO uint32_t SYSTICKFCLKDIV;                    /**< System tick FCLK divider, offset: 0x764 */
+  __IO uint32_t LCDFCLKDIV;                        /**< Lcd FCLK divider, offset: 0x768 */
+  __IO uint32_t GAUFCLKDIV;                        /**< Gau FCLK divider, offset: 0x76C */
+  __IO uint32_t USIMFCLKDIV;                       /**< Usim FCLK divider, offset: 0x770 */
+  __IO uint32_t USIMFCLKSEL;                       /**< USIM FCLK selection, offset: 0x774 */
+  __IO uint32_t LCDFCLKSEL;                        /**< LCD FCLK selection, offset: 0x778 */
+  __IO uint32_t GAUFCLKSEL;                        /**< GAU FCLK selection, offset: 0x77C */
+  __IO uint32_t PMUFCLKDIV;                        /**< Pmu FCLK divider, offset: 0x780 */
+       uint8_t RESERVED_14[12];
+  __IO uint32_t BRG_CLK_EN;                        /**< wl/ble/soc bridge clock enable signal, offset: 0x790 */
+       uint8_t RESERVED_15[12];
+  __IO uint32_t G2BIST_CLK_EN;                     /**< g2bist clock enable signal, offset: 0x7A0 */
+  __IO uint32_t MAIN_RAM_CLK_EN;                   /**< main ram clock enable signal, offset: 0x7A4 */
+  __IO uint32_t ELS_GDET_CLK_SEL;                  /**< ELS GDET CLK selection, offset: 0x7A8 */
+} CLKCTL0_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CLKCTL0 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL0_Register_Masks CLKCTL0 Register Masks
+ * @{
+ */
+
+/*! @name PSCCTL0 - clock control 0 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL0_PQ_MASK                  (0x100U)
+#define CLKCTL0_PSCCTL0_PQ_SHIFT                 (8U)
+/*! PQ - pq clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_PQ(x)                    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_PQ_SHIFT)) & CLKCTL0_PSCCTL0_PQ_MASK)
+
+#define CLKCTL0_PSCCTL0_PKC_MASK                 (0x200U)
+#define CLKCTL0_PSCCTL0_PKC_SHIFT                (9U)
+/*! PKC - pkc clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_PKC(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_PKC_SHIFT)) & CLKCTL0_PSCCTL0_PKC_MASK)
+
+#define CLKCTL0_PSCCTL0_ELS_MASK                 (0x400U)
+#define CLKCTL0_PSCCTL0_ELS_SHIFT                (10U)
+/*! ELS - els clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_ELS(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_ELS_SHIFT)) & CLKCTL0_PSCCTL0_ELS_MASK)
+
+#define CLKCTL0_PSCCTL0_PUF_MASK                 (0x800U)
+#define CLKCTL0_PSCCTL0_PUF_SHIFT                (11U)
+/*! PUF - puf clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_PUF(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_PUF_SHIFT)) & CLKCTL0_PSCCTL0_PUF_MASK)
+
+#define CLKCTL0_PSCCTL0_FLEXSPI0_MASK            (0x10000U)
+#define CLKCTL0_PSCCTL0_FLEXSPI0_SHIFT           (16U)
+/*! FLEXSPI0 - flexspi0 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_FLEXSPI0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_FLEXSPI0_SHIFT)) & CLKCTL0_PSCCTL0_FLEXSPI0_MASK)
+
+#define CLKCTL0_PSCCTL0_HPU_MASK                 (0x100000U)
+#define CLKCTL0_PSCCTL0_HPU_SHIFT                (20U)
+/*! HPU - hpu clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_HPU(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_HPU_SHIFT)) & CLKCTL0_PSCCTL0_HPU_MASK)
+
+#define CLKCTL0_PSCCTL0_USB_MASK                 (0x400000U)
+#define CLKCTL0_PSCCTL0_USB_SHIFT                (22U)
+/*! USB - usb clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_USB(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USB_SHIFT)) & CLKCTL0_PSCCTL0_USB_MASK)
+
+#define CLKCTL0_PSCCTL0_SCT_MASK                 (0x1000000U)
+#define CLKCTL0_PSCCTL0_SCT_SHIFT                (24U)
+/*! SCT - sct clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_SCT(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SCT_SHIFT)) & CLKCTL0_PSCCTL0_SCT_MASK)
+
+#define CLKCTL0_PSCCTL0_AON_MEM_MASK             (0x2000000U)
+#define CLKCTL0_PSCCTL0_AON_MEM_SHIFT            (25U)
+/*! AON_MEM - aon_mem clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_AON_MEM(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_AON_MEM_SHIFT)) & CLKCTL0_PSCCTL0_AON_MEM_MASK)
+
+#define CLKCTL0_PSCCTL0_GDMA_MASK                (0x10000000U)
+#define CLKCTL0_PSCCTL0_GDMA_SHIFT               (28U)
+/*! GDMA - gdma clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_GDMA(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_GDMA_SHIFT)) & CLKCTL0_PSCCTL0_GDMA_MASK)
+
+#define CLKCTL0_PSCCTL0_DMA0_MASK                (0x20000000U)
+#define CLKCTL0_PSCCTL0_DMA0_SHIFT               (29U)
+/*! DMA0 - dma0 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_DMA0(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_DMA0_SHIFT)) & CLKCTL0_PSCCTL0_DMA0_MASK)
+
+#define CLKCTL0_PSCCTL0_DMA1_MASK                (0x40000000U)
+#define CLKCTL0_PSCCTL0_DMA1_SHIFT               (30U)
+/*! DMA1 - dma1 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_DMA1(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_DMA1_SHIFT)) & CLKCTL0_PSCCTL0_DMA1_MASK)
+
+#define CLKCTL0_PSCCTL0_SDIO_MASK                (0x80000000U)
+#define CLKCTL0_PSCCTL0_SDIO_SHIFT               (31U)
+/*! SDIO - sdio clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_SDIO(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SDIO_SHIFT)) & CLKCTL0_PSCCTL0_SDIO_MASK)
+/*! @} */
+
+/*! @name PSCCTL1 - clock control 1 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL1_ELS_APB_MASK             (0x1U)
+#define CLKCTL0_PSCCTL1_ELS_APB_SHIFT            (0U)
+/*! ELS_APB - els_apb clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_ELS_APB(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ELS_APB_SHIFT)) & CLKCTL0_PSCCTL1_ELS_APB_MASK)
+
+#define CLKCTL0_PSCCTL1_SDIO_SLV_MASK            (0x4U)
+#define CLKCTL0_PSCCTL1_SDIO_SLV_SHIFT           (2U)
+/*! SDIO_SLV - sdio_slv clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_SDIO_SLV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SDIO_SLV_SHIFT)) & CLKCTL0_PSCCTL1_SDIO_SLV_MASK)
+
+#define CLKCTL0_PSCCTL1_GAU_MASK                 (0x10000U)
+#define CLKCTL0_PSCCTL1_GAU_SHIFT                (16U)
+/*! GAU - gau clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_GAU(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_GAU_SHIFT)) & CLKCTL0_PSCCTL1_GAU_MASK)
+
+#define CLKCTL0_PSCCTL1_OTP_MASK                 (0x20000U)
+#define CLKCTL0_PSCCTL1_OTP_SHIFT                (17U)
+/*! OTP - otp clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_OTP(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_OTP_SHIFT)) & CLKCTL0_PSCCTL1_OTP_MASK)
+
+#define CLKCTL0_PSCCTL1_SECURE_GPIO_MASK         (0x1000000U)
+#define CLKCTL0_PSCCTL1_SECURE_GPIO_SHIFT        (24U)
+/*! SECURE_GPIO - secure_gpio clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_SECURE_GPIO(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SECURE_GPIO_SHIFT)) & CLKCTL0_PSCCTL1_SECURE_GPIO_MASK)
+
+#define CLKCTL0_PSCCTL1_ENET_IPG_MASK            (0x2000000U)
+#define CLKCTL0_PSCCTL1_ENET_IPG_SHIFT           (25U)
+/*! ENET_IPG - enet_ipg clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_ENET_IPG(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ENET_IPG_SHIFT)) & CLKCTL0_PSCCTL1_ENET_IPG_MASK)
+
+#define CLKCTL0_PSCCTL1_ENET_IPG_S_MASK          (0x4000000U)
+#define CLKCTL0_PSCCTL1_ENET_IPG_S_SHIFT         (26U)
+/*! ENET_IPG_S - enet_ipg_s clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_ENET_IPG_S(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ENET_IPG_S_SHIFT)) & CLKCTL0_PSCCTL1_ENET_IPG_S_MASK)
+
+#define CLKCTL0_PSCCTL1_TRNG_MASK                (0x8000000U)
+#define CLKCTL0_PSCCTL1_TRNG_SHIFT               (27U)
+/*! TRNG - trng clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_TRNG(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_TRNG_SHIFT)) & CLKCTL0_PSCCTL1_TRNG_MASK)
+/*! @} */
+
+/*! @name PSCCTL2 - clock control 2 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL2_UTICK_MASK               (0x1U)
+#define CLKCTL0_PSCCTL2_UTICK_SHIFT              (0U)
+/*! UTICK - utick clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_UTICK(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_UTICK_SHIFT)) & CLKCTL0_PSCCTL2_UTICK_MASK)
+
+#define CLKCTL0_PSCCTL2_WWDT0_MASK               (0x2U)
+#define CLKCTL0_PSCCTL2_WWDT0_SHIFT              (1U)
+/*! WWDT0 - wwdt0 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_WWDT0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_WWDT0_SHIFT)) & CLKCTL0_PSCCTL2_WWDT0_MASK)
+
+#define CLKCTL0_PSCCTL2_USIM_MASK                (0x4U)
+#define CLKCTL0_PSCCTL2_USIM_SHIFT               (2U)
+/*! USIM - usim clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_USIM(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_USIM_SHIFT)) & CLKCTL0_PSCCTL2_USIM_MASK)
+
+#define CLKCTL0_PSCCTL2_ITRC_MASK                (0x8U)
+#define CLKCTL0_PSCCTL2_ITRC_SHIFT               (3U)
+/*! ITRC - itrc clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_ITRC(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_ITRC_SHIFT)) & CLKCTL0_PSCCTL2_ITRC_MASK)
+
+#define CLKCTL0_PSCCTL2_FREEMRT_MASK             (0x4000000U)
+#define CLKCTL0_PSCCTL2_FREEMRT_SHIFT            (26U)
+/*! FREEMRT - freemrt clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_FREEMRT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_FREEMRT_SHIFT)) & CLKCTL0_PSCCTL2_FREEMRT_MASK)
+
+#define CLKCTL0_PSCCTL2_LCDIC_MASK               (0x8000000U)
+#define CLKCTL0_PSCCTL2_LCDIC_SHIFT              (27U)
+/*! LCDIC - lcdic clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_LCDIC(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_LCDIC_SHIFT)) & CLKCTL0_PSCCTL2_LCDIC_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_SET - Peripheral clock set 0 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL0_SET_PQ_MASK              (0x100U)
+#define CLKCTL0_PSCCTL0_SET_PQ_SHIFT             (8U)
+/*! PQ - pq clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_PQ(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_PQ_SHIFT)) & CLKCTL0_PSCCTL0_SET_PQ_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_PKC_MASK             (0x200U)
+#define CLKCTL0_PSCCTL0_SET_PKC_SHIFT            (9U)
+/*! PKC - pkc clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_PKC(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_PKC_SHIFT)) & CLKCTL0_PSCCTL0_SET_PKC_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_ELS_MASK             (0x400U)
+#define CLKCTL0_PSCCTL0_SET_ELS_SHIFT            (10U)
+/*! ELS - els clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_ELS(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_ELS_SHIFT)) & CLKCTL0_PSCCTL0_SET_ELS_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_PUF_MASK             (0x800U)
+#define CLKCTL0_PSCCTL0_SET_PUF_SHIFT            (11U)
+/*! PUF - puf clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_PUF(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_PUF_SHIFT)) & CLKCTL0_PSCCTL0_SET_PUF_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK        (0x10000U)
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_SHIFT       (16U)
+/*! FLEXSPI0 - flexspi0 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_FLEXSPI0_SHIFT)) & CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_HPU_MASK             (0x100000U)
+#define CLKCTL0_PSCCTL0_SET_HPU_SHIFT            (20U)
+/*! HPU - hpu clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_HPU(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_HPU_SHIFT)) & CLKCTL0_PSCCTL0_SET_HPU_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_USB_MASK             (0x400000U)
+#define CLKCTL0_PSCCTL0_SET_USB_SHIFT            (22U)
+/*! USB - usb clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_USB(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USB_SHIFT)) & CLKCTL0_PSCCTL0_SET_USB_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_SCT_MASK             (0x1000000U)
+#define CLKCTL0_PSCCTL0_SET_SCT_SHIFT            (24U)
+/*! SCT - sct clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_SCT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SCT_SHIFT)) & CLKCTL0_PSCCTL0_SET_SCT_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_AON_MEM_MASK         (0x2000000U)
+#define CLKCTL0_PSCCTL0_SET_AON_MEM_SHIFT        (25U)
+/*! AON_MEM - aon_mem clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_AON_MEM(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_AON_MEM_SHIFT)) & CLKCTL0_PSCCTL0_SET_AON_MEM_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_GDMA_MASK            (0x10000000U)
+#define CLKCTL0_PSCCTL0_SET_GDMA_SHIFT           (28U)
+/*! GDMA - gdma clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_GDMA(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_GDMA_SHIFT)) & CLKCTL0_PSCCTL0_SET_GDMA_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_DMA0_MASK            (0x20000000U)
+#define CLKCTL0_PSCCTL0_SET_DMA0_SHIFT           (29U)
+/*! DMA0 - dma0 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_DMA0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_DMA0_SHIFT)) & CLKCTL0_PSCCTL0_SET_DMA0_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_DMA1_MASK            (0x40000000U)
+#define CLKCTL0_PSCCTL0_SET_DMA1_SHIFT           (30U)
+/*! DMA1 - dma1 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_DMA1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_DMA1_SHIFT)) & CLKCTL0_PSCCTL0_SET_DMA1_MASK)
+
+#define CLKCTL0_PSCCTL0_SET_SDIO_MASK            (0x80000000U)
+#define CLKCTL0_PSCCTL0_SET_SDIO_SHIFT           (31U)
+/*! SDIO - sdio clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_SET_SDIO(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SDIO_SHIFT)) & CLKCTL0_PSCCTL0_SET_SDIO_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_SET - Peripheral clock set 1 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL1_SET_ELS_APB_MASK         (0x1U)
+#define CLKCTL0_PSCCTL1_SET_ELS_APB_SHIFT        (0U)
+/*! ELS_APB - els_apb clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_ELS_APB(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ELS_APB_SHIFT)) & CLKCTL0_PSCCTL1_SET_ELS_APB_MASK)
+
+#define CLKCTL0_PSCCTL1_SET_SDIO_SLV_MASK        (0x4U)
+#define CLKCTL0_PSCCTL1_SET_SDIO_SLV_SHIFT       (2U)
+/*! SDIO_SLV - sdio_slv clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_SDIO_SLV(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SDIO_SLV_SHIFT)) & CLKCTL0_PSCCTL1_SET_SDIO_SLV_MASK)
+
+#define CLKCTL0_PSCCTL1_SET_GAU_MASK             (0x10000U)
+#define CLKCTL0_PSCCTL1_SET_GAU_SHIFT            (16U)
+/*! GAU - gau clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_GAU(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_GAU_SHIFT)) & CLKCTL0_PSCCTL1_SET_GAU_MASK)
+
+#define CLKCTL0_PSCCTL1_SET_OTP_MASK             (0x20000U)
+#define CLKCTL0_PSCCTL1_SET_OTP_SHIFT            (17U)
+/*! OTP - otp clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_OTP(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_OTP_SHIFT)) & CLKCTL0_PSCCTL1_SET_OTP_MASK)
+
+#define CLKCTL0_PSCCTL1_SET_SECURE_GPIO_MASK     (0x1000000U)
+#define CLKCTL0_PSCCTL1_SET_SECURE_GPIO_SHIFT    (24U)
+/*! SECURE_GPIO - secure_gpio clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_SECURE_GPIO(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SECURE_GPIO_SHIFT)) & CLKCTL0_PSCCTL1_SET_SECURE_GPIO_MASK)
+
+#define CLKCTL0_PSCCTL1_SET_ENET_IPG_MASK        (0x2000000U)
+#define CLKCTL0_PSCCTL1_SET_ENET_IPG_SHIFT       (25U)
+/*! ENET_IPG - enet_ipg clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_ENET_IPG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ENET_IPG_SHIFT)) & CLKCTL0_PSCCTL1_SET_ENET_IPG_MASK)
+
+#define CLKCTL0_PSCCTL1_SET_ENET_IPG_S_MASK      (0x4000000U)
+#define CLKCTL0_PSCCTL1_SET_ENET_IPG_S_SHIFT     (26U)
+/*! ENET_IPG_S - enet_ipg_s clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_ENET_IPG_S(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ENET_IPG_S_SHIFT)) & CLKCTL0_PSCCTL1_SET_ENET_IPG_S_MASK)
+
+#define CLKCTL0_PSCCTL1_SET_TRNG_MASK            (0x8000000U)
+#define CLKCTL0_PSCCTL1_SET_TRNG_SHIFT           (27U)
+/*! TRNG - trng clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_SET_TRNG(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_TRNG_SHIFT)) & CLKCTL0_PSCCTL1_SET_TRNG_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_SET - Peripheral clock set 2 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL2_SET_UTICK_MASK           (0x1U)
+#define CLKCTL0_PSCCTL2_SET_UTICK_SHIFT          (0U)
+/*! UTICK - utick clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_SET_UTICK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_UTICK_SHIFT)) & CLKCTL0_PSCCTL2_SET_UTICK_MASK)
+
+#define CLKCTL0_PSCCTL2_SET_WWDT0_MASK           (0x2U)
+#define CLKCTL0_PSCCTL2_SET_WWDT0_SHIFT          (1U)
+/*! WWDT0 - wwdt0 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_SET_WWDT0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_WWDT0_SHIFT)) & CLKCTL0_PSCCTL2_SET_WWDT0_MASK)
+
+#define CLKCTL0_PSCCTL2_SET_USIM_MASK            (0x4U)
+#define CLKCTL0_PSCCTL2_SET_USIM_SHIFT           (2U)
+/*! USIM - usim clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_SET_USIM(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_USIM_SHIFT)) & CLKCTL0_PSCCTL2_SET_USIM_MASK)
+
+#define CLKCTL0_PSCCTL2_SET_ITRC_MASK            (0x8U)
+#define CLKCTL0_PSCCTL2_SET_ITRC_SHIFT           (3U)
+/*! ITRC - itrc clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_SET_ITRC(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_ITRC_SHIFT)) & CLKCTL0_PSCCTL2_SET_ITRC_MASK)
+
+#define CLKCTL0_PSCCTL2_SET_FREEMRT_MASK         (0x4000000U)
+#define CLKCTL0_PSCCTL2_SET_FREEMRT_SHIFT        (26U)
+/*! FREEMRT - freemrt clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_SET_FREEMRT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_FREEMRT_SHIFT)) & CLKCTL0_PSCCTL2_SET_FREEMRT_MASK)
+
+#define CLKCTL0_PSCCTL2_SET_LCDIC_MASK           (0x8000000U)
+#define CLKCTL0_PSCCTL2_SET_LCDIC_SHIFT          (27U)
+/*! LCDIC - lcdic clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_SET_LCDIC(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_LCDIC_SHIFT)) & CLKCTL0_PSCCTL2_SET_LCDIC_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_CLR - Peripheral clock clear 0 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL0_CLR_PQ_MASK              (0x100U)
+#define CLKCTL0_PSCCTL0_CLR_PQ_SHIFT             (8U)
+/*! PQ - pq clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_PQ(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_PQ_SHIFT)) & CLKCTL0_PSCCTL0_CLR_PQ_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_PKC_MASK             (0x200U)
+#define CLKCTL0_PSCCTL0_CLR_PKC_SHIFT            (9U)
+/*! PKC - pkc clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_PKC(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_PKC_SHIFT)) & CLKCTL0_PSCCTL0_CLR_PKC_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_ELS_MASK             (0x400U)
+#define CLKCTL0_PSCCTL0_CLR_ELS_SHIFT            (10U)
+/*! ELS - els clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_ELS(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_ELS_SHIFT)) & CLKCTL0_PSCCTL0_CLR_ELS_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_PUF_MASK             (0x800U)
+#define CLKCTL0_PSCCTL0_CLR_PUF_SHIFT            (11U)
+/*! PUF - puf clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_PUF(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_PUF_SHIFT)) & CLKCTL0_PSCCTL0_CLR_PUF_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK        (0x10000U)
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_SHIFT       (16U)
+/*! FLEXSPI0 - flexspi0 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_FLEXSPI0_SHIFT)) & CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_HPU_MASK             (0x100000U)
+#define CLKCTL0_PSCCTL0_CLR_HPU_SHIFT            (20U)
+/*! HPU - hpu clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_HPU(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_HPU_SHIFT)) & CLKCTL0_PSCCTL0_CLR_HPU_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_USB_MASK             (0x400000U)
+#define CLKCTL0_PSCCTL0_CLR_USB_SHIFT            (22U)
+/*! USB - usb clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_USB(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USB_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USB_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_SCT_MASK             (0x1000000U)
+#define CLKCTL0_PSCCTL0_CLR_SCT_SHIFT            (24U)
+/*! SCT - sct clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_SCT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SCT_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SCT_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_AON_MEM_MASK         (0x2000000U)
+#define CLKCTL0_PSCCTL0_CLR_AON_MEM_SHIFT        (25U)
+/*! AON_MEM - aon_mem clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_AON_MEM(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_AON_MEM_SHIFT)) & CLKCTL0_PSCCTL0_CLR_AON_MEM_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_GDMA_MASK            (0x10000000U)
+#define CLKCTL0_PSCCTL0_CLR_GDMA_SHIFT           (28U)
+/*! GDMA - gdma clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_GDMA(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_GDMA_SHIFT)) & CLKCTL0_PSCCTL0_CLR_GDMA_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_DMA0_MASK            (0x20000000U)
+#define CLKCTL0_PSCCTL0_CLR_DMA0_SHIFT           (29U)
+/*! DMA0 - dma0 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_DMA0(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_DMA0_SHIFT)) & CLKCTL0_PSCCTL0_CLR_DMA0_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_DMA1_MASK            (0x40000000U)
+#define CLKCTL0_PSCCTL0_CLR_DMA1_SHIFT           (30U)
+/*! DMA1 - dma1 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_DMA1(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_DMA1_SHIFT)) & CLKCTL0_PSCCTL0_CLR_DMA1_MASK)
+
+#define CLKCTL0_PSCCTL0_CLR_SDIO_MASK            (0x80000000U)
+#define CLKCTL0_PSCCTL0_CLR_SDIO_SHIFT           (31U)
+/*! SDIO - sdio clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL0_CLR_SDIO(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SDIO_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SDIO_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_CLR - Peripheral clock clear 1 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL1_CLR_ELS_APB_MASK         (0x1U)
+#define CLKCTL0_PSCCTL1_CLR_ELS_APB_SHIFT        (0U)
+/*! ELS_APB - els_apb clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_ELS_APB(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ELS_APB_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ELS_APB_MASK)
+
+#define CLKCTL0_PSCCTL1_CLR_SDIO_SLV_MASK        (0x4U)
+#define CLKCTL0_PSCCTL1_CLR_SDIO_SLV_SHIFT       (2U)
+/*! SDIO_SLV - sdio_slv clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_SDIO_SLV(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SDIO_SLV_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SDIO_SLV_MASK)
+
+#define CLKCTL0_PSCCTL1_CLR_GAU_MASK             (0x10000U)
+#define CLKCTL0_PSCCTL1_CLR_GAU_SHIFT            (16U)
+/*! GAU - gau clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_GAU(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_GAU_SHIFT)) & CLKCTL0_PSCCTL1_CLR_GAU_MASK)
+
+#define CLKCTL0_PSCCTL1_CLR_OTP_MASK             (0x20000U)
+#define CLKCTL0_PSCCTL1_CLR_OTP_SHIFT            (17U)
+/*! OTP - otp clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_OTP(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_OTP_SHIFT)) & CLKCTL0_PSCCTL1_CLR_OTP_MASK)
+
+#define CLKCTL0_PSCCTL1_CLR_SECURE_GPIO_MASK     (0x1000000U)
+#define CLKCTL0_PSCCTL1_CLR_SECURE_GPIO_SHIFT    (24U)
+/*! SECURE_GPIO - secure_gpio clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_SECURE_GPIO(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SECURE_GPIO_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SECURE_GPIO_MASK)
+
+#define CLKCTL0_PSCCTL1_CLR_ENET_IPG_MASK        (0x2000000U)
+#define CLKCTL0_PSCCTL1_CLR_ENET_IPG_SHIFT       (25U)
+/*! ENET_IPG - enet_ipg clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_ENET_IPG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ENET_IPG_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ENET_IPG_MASK)
+
+#define CLKCTL0_PSCCTL1_CLR_ENET_IPG_S_MASK      (0x4000000U)
+#define CLKCTL0_PSCCTL1_CLR_ENET_IPG_S_SHIFT     (26U)
+/*! ENET_IPG_S - enet_ipg_s clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_ENET_IPG_S(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ENET_IPG_S_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ENET_IPG_S_MASK)
+
+#define CLKCTL0_PSCCTL1_CLR_TRNG_MASK            (0x8000000U)
+#define CLKCTL0_PSCCTL1_CLR_TRNG_SHIFT           (27U)
+/*! TRNG - trng clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL0_PSCCTL1_CLR_TRNG(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_TRNG_SHIFT)) & CLKCTL0_PSCCTL1_CLR_TRNG_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_CLR - Peripheral clock clear 2 */
+/*! @{ */
+
+#define CLKCTL0_PSCCTL2_CLR_UTICK_MASK           (0x1U)
+#define CLKCTL0_PSCCTL2_CLR_UTICK_SHIFT          (0U)
+/*! UTICK - utick clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_CLR_UTICK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_UTICK_SHIFT)) & CLKCTL0_PSCCTL2_CLR_UTICK_MASK)
+
+#define CLKCTL0_PSCCTL2_CLR_WWDT0_MASK           (0x2U)
+#define CLKCTL0_PSCCTL2_CLR_WWDT0_SHIFT          (1U)
+/*! WWDT0 - wwdt0 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_CLR_WWDT0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_WWDT0_SHIFT)) & CLKCTL0_PSCCTL2_CLR_WWDT0_MASK)
+
+#define CLKCTL0_PSCCTL2_CLR_USIM_MASK            (0x4U)
+#define CLKCTL0_PSCCTL2_CLR_USIM_SHIFT           (2U)
+/*! USIM - usim clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_CLR_USIM(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_USIM_SHIFT)) & CLKCTL0_PSCCTL2_CLR_USIM_MASK)
+
+#define CLKCTL0_PSCCTL2_CLR_ITRC_MASK            (0x8U)
+#define CLKCTL0_PSCCTL2_CLR_ITRC_SHIFT           (3U)
+/*! ITRC - itrc clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_CLR_ITRC(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_ITRC_SHIFT)) & CLKCTL0_PSCCTL2_CLR_ITRC_MASK)
+
+#define CLKCTL0_PSCCTL2_CLR_FREEMRT_MASK         (0x4000000U)
+#define CLKCTL0_PSCCTL2_CLR_FREEMRT_SHIFT        (26U)
+/*! FREEMRT - freemrt clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_CLR_FREEMRT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_FREEMRT_SHIFT)) & CLKCTL0_PSCCTL2_CLR_FREEMRT_MASK)
+
+#define CLKCTL0_PSCCTL2_CLR_LCDIC_MASK           (0x8000000U)
+#define CLKCTL0_PSCCTL2_CLR_LCDIC_SHIFT          (27U)
+/*! LCDIC - lcdic clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL0_PSCCTL2_CLR_LCDIC(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_LCDIC_SHIFT)) & CLKCTL0_PSCCTL2_CLR_LCDIC_MASK)
+/*! @} */
+
+/*! @name SYSOSCBYPASS - System oscillator bypass */
+/*! @{ */
+
+#define CLKCTL0_SYSOSCBYPASS_SEL_MASK            (0x7U)
+#define CLKCTL0_SYSOSCBYPASS_SEL_SHIFT           (0U)
+/*! SEL - External clock source selection
+ *  0b000..Output of the external crystal oscillator
+ *  0b001..External clock input (CLKIN function from a pin, selected by IOCON)
+ *  0b010..Reserved
+ *  0b011..Reserved
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..NONE.this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_SYSOSCBYPASS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSOSCBYPASS_SEL_SHIFT)) & CLKCTL0_SYSOSCBYPASS_SEL_MASK)
+/*! @} */
+
+/*! @name CLK32KHZCTL0 - 32k control 0 */
+/*! @{ */
+
+#define CLKCTL0_CLK32KHZCTL0_ENA_32KHZ_MASK      (0x1U)
+#define CLKCTL0_CLK32KHZCTL0_ENA_32KHZ_SHIFT     (0U)
+/*! ENA_32KHZ - 32 kHz Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CLKCTL0_CLK32KHZCTL0_ENA_32KHZ(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_CLK32KHZCTL0_ENA_32KHZ_SHIFT)) & CLKCTL0_CLK32KHZCTL0_ENA_32KHZ_MASK)
+/*! @} */
+
+/*! @name MAINPLLCLKDIV - Main PLL clock divider */
+/*! @{ */
+
+#define CLKCTL0_MAINPLLCLKDIV_DIV_MASK           (0xFFU)
+#define CLKCTL0_MAINPLLCLKDIV_DIV_SHIFT          (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_MAINPLLCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_DIV_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_DIV_MASK)
+
+#define CLKCTL0_MAINPLLCLKDIV_RESET_MASK         (0x20000000U)
+#define CLKCTL0_MAINPLLCLKDIV_RESET_SHIFT        (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_MAINPLLCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_RESET_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_RESET_MASK)
+
+#define CLKCTL0_MAINPLLCLKDIV_HALT_MASK          (0x40000000U)
+#define CLKCTL0_MAINPLLCLKDIV_HALT_SHIFT         (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_MAINPLLCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_HALT_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_HALT_MASK)
+
+#define CLKCTL0_MAINPLLCLKDIV_REQFLAG_MASK       (0x80000000U)
+#define CLKCTL0_MAINPLLCLKDIV_REQFLAG_SHIFT      (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_MAINPLLCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name AUX0PLLCLKDIV - AUX0 PLL clock divider */
+/*! @{ */
+
+#define CLKCTL0_AUX0PLLCLKDIV_DIV_MASK           (0xFFU)
+#define CLKCTL0_AUX0PLLCLKDIV_DIV_SHIFT          (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_AUX0PLLCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_DIV_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK)
+
+#define CLKCTL0_AUX0PLLCLKDIV_RESET_MASK         (0x20000000U)
+#define CLKCTL0_AUX0PLLCLKDIV_RESET_SHIFT        (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_AUX0PLLCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_RESET_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_RESET_MASK)
+
+#define CLKCTL0_AUX0PLLCLKDIV_HALT_MASK          (0x40000000U)
+#define CLKCTL0_AUX0PLLCLKDIV_HALT_SHIFT         (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_AUX0PLLCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_HALT_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_HALT_MASK)
+
+#define CLKCTL0_AUX0PLLCLKDIV_REQFLAG_MASK       (0x80000000U)
+#define CLKCTL0_AUX0PLLCLKDIV_REQFLAG_SHIFT      (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_AUX0PLLCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name AUX1PLLCLKDIV - AUX1 PLL clock divider */
+/*! @{ */
+
+#define CLKCTL0_AUX1PLLCLKDIV_DIV_MASK           (0xFFU)
+#define CLKCTL0_AUX1PLLCLKDIV_DIV_SHIFT          (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_AUX1PLLCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_DIV_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_DIV_MASK)
+
+#define CLKCTL0_AUX1PLLCLKDIV_RESET_MASK         (0x20000000U)
+#define CLKCTL0_AUX1PLLCLKDIV_RESET_SHIFT        (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_AUX1PLLCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_RESET_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_RESET_MASK)
+
+#define CLKCTL0_AUX1PLLCLKDIV_HALT_MASK          (0x40000000U)
+#define CLKCTL0_AUX1PLLCLKDIV_HALT_SHIFT         (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_AUX1PLLCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_HALT_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_HALT_MASK)
+
+#define CLKCTL0_AUX1PLLCLKDIV_REQFLAG_MASK       (0x80000000U)
+#define CLKCTL0_AUX1PLLCLKDIV_REQFLAG_SHIFT      (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_AUX1PLLCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SYSCPUAHBCLKDIV - System CPU AHB clock divider */
+/*! @{ */
+
+#define CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK         (0xFFU)
+#define CLKCTL0_SYSCPUAHBCLKDIV_DIV_SHIFT        (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_SYSCPUAHBCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSCPUAHBCLKDIV_DIV_SHIFT)) & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK)
+
+#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK     (0x80000000U)
+#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_SHIFT    (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELA - Main clock selection A */
+/*! @{ */
+
+#define CLKCTL0_MAINCLKSELA_SEL_MASK             (0x3U)
+#define CLKCTL0_MAINCLKSELA_SEL_SHIFT            (0U)
+/*! SEL - Control Main 1st Stage Control Clock Source
+ *  0b00..External clock (clk_in) or REFCLK_SYS
+ *  0b01..FFRO Clock (48/60m_irc) divided by 4
+ *  0b10..1m_lposc
+ *  0b11..FFRO Clock
+ */
+#define CLKCTL0_MAINCLKSELA_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKSELA_SEL_SHIFT)) & CLKCTL0_MAINCLKSELA_SEL_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELB - Main clock selection B */
+/*! @{ */
+
+#define CLKCTL0_MAINCLKSELB_SEL_MASK             (0x3U)
+#define CLKCTL0_MAINCLKSELB_SEL_SHIFT            (0U)
+/*! SEL - Control Main 2nd Stage Control Clock Source
+ *  0b00..MAINCLKSELA 1st Stage Clock
+ *  0b01..SFRO Clock
+ *  0b10..Main PLL Clock (main_pll_clk).
+ *  0b11..32 kHz Clock
+ */
+#define CLKCTL0_MAINCLKSELB_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKSELB_SEL_SHIFT)) & CLKCTL0_MAINCLKSELB_SEL_MASK)
+/*! @} */
+
+/*! @name FLEXSPIFCLKSEL - FlexSPI FCLK selection */
+/*! @{ */
+
+#define CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK          (0x7U)
+#define CLKCTL0_FLEXSPIFCLKSEL_SEL_SHIFT         (0U)
+/*! SEL - FlexSPI Functional Clock Source Selection
+ *  0b000..Main Clock
+ *  0b001..t3pll_mci_flexspi_clk(365M)
+ *  0b010..AUX0 PLL clock (aux0_pll_clk).
+ *  0b011..tcpu_mci_flexspi_clk(312M)
+ *  0b100..AUX1 PLL clock (aux1_pll_clk).
+ *  0b101..tddr_mci_flexspi_clk(320/355/400M)
+ *  0b110..t3pll_mci_256m
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_FLEXSPIFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPIFCLKSEL_SEL_SHIFT)) & CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FLEXSPIFCLKDIV - FlexSPI FCLK divider */
+/*! @{ */
+
+#define CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK          (0xFFU)
+#define CLKCTL0_FLEXSPIFCLKDIV_DIV_SHIFT         (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_FLEXSPIFCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPIFCLKDIV_DIV_SHIFT)) & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK)
+
+#define CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK        (0x20000000U)
+#define CLKCTL0_FLEXSPIFCLKDIV_RESET_SHIFT       (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_FLEXSPIFCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPIFCLKDIV_RESET_SHIFT)) & CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK)
+
+#define CLKCTL0_FLEXSPIFCLKDIV_HALT_MASK         (0x40000000U)
+#define CLKCTL0_FLEXSPIFCLKDIV_HALT_SHIFT        (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_FLEXSPIFCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPIFCLKDIV_HALT_SHIFT)) & CLKCTL0_FLEXSPIFCLKDIV_HALT_MASK)
+
+#define CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK      (0x80000000U)
+#define CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_SHIFT     (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_FLEXSPIFCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SCTFCLKSEL - SCT FCLK selection */
+/*! @{ */
+
+#define CLKCTL0_SCTFCLKSEL_SEL_MASK              (0x7U)
+#define CLKCTL0_SCTFCLKSEL_SEL_SHIFT             (0U)
+/*! SEL - SCT Functional Clock Source Selection
+ *  0b000..Main Clock
+ *  0b001..Main PLL Clock (main_pll_clk).
+ *  0b010..AUX0 PLL clock (aux0_pll_clk).
+ *  0b011..FFRO Clock (48/60m_irc).
+ *  0b100..AUX1 PLL clock (aux1_pll_clk).
+ *  0b101..Audio PLL Clock (audio_pll_clk).
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_SCTFCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKSEL_SEL_SHIFT)) & CLKCTL0_SCTFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SCTFCLKDIV - SCT FCLK divider */
+/*! @{ */
+
+#define CLKCTL0_SCTFCLKDIV_DIV_MASK              (0xFFU)
+#define CLKCTL0_SCTFCLKDIV_DIV_SHIFT             (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_SCTFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_DIV_SHIFT)) & CLKCTL0_SCTFCLKDIV_DIV_MASK)
+
+#define CLKCTL0_SCTFCLKDIV_RESET_MASK            (0x20000000U)
+#define CLKCTL0_SCTFCLKDIV_RESET_SHIFT           (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_SCTFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_RESET_SHIFT)) & CLKCTL0_SCTFCLKDIV_RESET_MASK)
+
+#define CLKCTL0_SCTFCLKDIV_HALT_MASK             (0x40000000U)
+#define CLKCTL0_SCTFCLKDIV_HALT_SHIFT            (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_SCTFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_HALT_SHIFT)) & CLKCTL0_SCTFCLKDIV_HALT_MASK)
+
+#define CLKCTL0_SCTFCLKDIV_REQFLAG_MASK          (0x80000000U)
+#define CLKCTL0_SCTFCLKDIV_REQFLAG_SHIFT         (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_SCTFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SCTFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name UTICKFCLKSEL - UTICK FCLK selection */
+/*! @{ */
+
+#define CLKCTL0_UTICKFCLKSEL_SEL_MASK            (0x7U)
+#define CLKCTL0_UTICKFCLKSEL_SEL_SHIFT           (0U)
+/*! SEL - UTICK Functional Clock Source Selection
+ *  0b000..1m_lposc
+ *  0b001..Main Clock
+ *  0b010..Reserved
+ *  0b011..Reserved
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_UTICKFCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICKFCLKSEL_SEL_SHIFT)) & CLKCTL0_UTICKFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name WDT0FCLKSEL - WDT clock selection */
+/*! @{ */
+
+#define CLKCTL0_WDT0FCLKSEL_SEL_MASK             (0x7U)
+#define CLKCTL0_WDT0FCLKSEL_SEL_SHIFT            (0U)
+/*! SEL - WDT0 Functional Clock Source Selection
+ *  0b000..1m_lposc
+ *  0b001..Main Clock
+ *  0b010..Reserved
+ *  0b011..Reserved
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_WDT0FCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_WDT0FCLKSEL_SEL_SHIFT)) & CLKCTL0_WDT0FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SYSTICKFCLKSEL - System tick FCLK selection */
+/*! @{ */
+
+#define CLKCTL0_SYSTICKFCLKSEL_SEL_MASK          (0x7U)
+#define CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT         (0U)
+/*! SEL - SYSTICK Functional Clock Source Selection
+ *  0b000..Systick Divider Output Clock
+ *  0b001..1m_lposc
+ *  0b010..32 kHz Clock
+ *  0b011..SFRO Clock (16m_irc).
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_SYSTICKFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT)) & CLKCTL0_SYSTICKFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SYSTICKFCLKDIV - System tick FCLK divider */
+/*! @{ */
+
+#define CLKCTL0_SYSTICKFCLKDIV_DIV_MASK          (0xFFU)
+#define CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT         (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_SYSTICKFCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK)
+
+#define CLKCTL0_SYSTICKFCLKDIV_RESET_MASK        (0x20000000U)
+#define CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT       (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_SYSTICKFCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_RESET_MASK)
+
+#define CLKCTL0_SYSTICKFCLKDIV_HALT_MASK         (0x40000000U)
+#define CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT        (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_SYSTICKFCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_HALT_MASK)
+
+#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK      (0x80000000U)
+#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT     (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name LCDFCLKDIV - Lcd FCLK divider */
+/*! @{ */
+
+#define CLKCTL0_LCDFCLKDIV_DIV_MASK              (0xFFU)
+#define CLKCTL0_LCDFCLKDIV_DIV_SHIFT             (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_LCDFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LCDFCLKDIV_DIV_SHIFT)) & CLKCTL0_LCDFCLKDIV_DIV_MASK)
+
+#define CLKCTL0_LCDFCLKDIV_RESET_MASK            (0x20000000U)
+#define CLKCTL0_LCDFCLKDIV_RESET_SHIFT           (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_LCDFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LCDFCLKDIV_RESET_SHIFT)) & CLKCTL0_LCDFCLKDIV_RESET_MASK)
+
+#define CLKCTL0_LCDFCLKDIV_HALT_MASK             (0x40000000U)
+#define CLKCTL0_LCDFCLKDIV_HALT_SHIFT            (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_LCDFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LCDFCLKDIV_HALT_SHIFT)) & CLKCTL0_LCDFCLKDIV_HALT_MASK)
+
+#define CLKCTL0_LCDFCLKDIV_REQFLAG_MASK          (0x80000000U)
+#define CLKCTL0_LCDFCLKDIV_REQFLAG_SHIFT         (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_LCDFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LCDFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_LCDFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name GAUFCLKDIV - Gau FCLK divider */
+/*! @{ */
+
+#define CLKCTL0_GAUFCLKDIV_DIV_MASK              (0xFFU)
+#define CLKCTL0_GAUFCLKDIV_DIV_SHIFT             (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_GAUFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GAUFCLKDIV_DIV_SHIFT)) & CLKCTL0_GAUFCLKDIV_DIV_MASK)
+
+#define CLKCTL0_GAUFCLKDIV_RESET_MASK            (0x20000000U)
+#define CLKCTL0_GAUFCLKDIV_RESET_SHIFT           (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_GAUFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GAUFCLKDIV_RESET_SHIFT)) & CLKCTL0_GAUFCLKDIV_RESET_MASK)
+
+#define CLKCTL0_GAUFCLKDIV_HALT_MASK             (0x40000000U)
+#define CLKCTL0_GAUFCLKDIV_HALT_SHIFT            (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_GAUFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GAUFCLKDIV_HALT_SHIFT)) & CLKCTL0_GAUFCLKDIV_HALT_MASK)
+
+#define CLKCTL0_GAUFCLKDIV_REQFLAG_MASK          (0x80000000U)
+#define CLKCTL0_GAUFCLKDIV_REQFLAG_SHIFT         (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_GAUFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GAUFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_GAUFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USIMFCLKDIV - Usim FCLK divider */
+/*! @{ */
+
+#define CLKCTL0_USIMFCLKDIV_DIV_MASK             (0xFFU)
+#define CLKCTL0_USIMFCLKDIV_DIV_SHIFT            (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_USIMFCLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USIMFCLKDIV_DIV_SHIFT)) & CLKCTL0_USIMFCLKDIV_DIV_MASK)
+
+#define CLKCTL0_USIMFCLKDIV_RESET_MASK           (0x20000000U)
+#define CLKCTL0_USIMFCLKDIV_RESET_SHIFT          (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_USIMFCLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USIMFCLKDIV_RESET_SHIFT)) & CLKCTL0_USIMFCLKDIV_RESET_MASK)
+
+#define CLKCTL0_USIMFCLKDIV_HALT_MASK            (0x40000000U)
+#define CLKCTL0_USIMFCLKDIV_HALT_SHIFT           (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_USIMFCLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USIMFCLKDIV_HALT_SHIFT)) & CLKCTL0_USIMFCLKDIV_HALT_MASK)
+
+#define CLKCTL0_USIMFCLKDIV_REQFLAG_MASK         (0x80000000U)
+#define CLKCTL0_USIMFCLKDIV_REQFLAG_SHIFT        (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_USIMFCLKDIV_REQFLAG(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USIMFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_USIMFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USIMFCLKSEL - USIM FCLK selection */
+/*! @{ */
+
+#define CLKCTL0_USIMFCLKSEL_SEL_MASK             (0x7U)
+#define CLKCTL0_USIMFCLKSEL_SEL_SHIFT            (0U)
+/*! SEL - USIM Functional Clock Source Selection
+ *  0b000..Main Clock
+ *  0b001..Audio PLL Clock (audio_pll_clk).
+ *  0b010..FFRO clock
+ *  0b011..Reserved
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_USIMFCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USIMFCLKSEL_SEL_SHIFT)) & CLKCTL0_USIMFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name LCDFCLKSEL - LCD FCLK selection */
+/*! @{ */
+
+#define CLKCTL0_LCDFCLKSEL_SEL_MASK              (0x7U)
+#define CLKCTL0_LCDFCLKSEL_SEL_SHIFT             (0U)
+/*! SEL - LCD Functional Clock Source Selection
+ *  0b000..Main Clock
+ *  0b001..t3pll_mci_flexspi_clk
+ *  0b010..tcpu_mci_flexspi_clk
+ *  0b011..tddr_mci_flexspi_clk
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_LCDFCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LCDFCLKSEL_SEL_SHIFT)) & CLKCTL0_LCDFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name GAUFCLKSEL - GAU FCLK selection */
+/*! @{ */
+
+#define CLKCTL0_GAUFCLKSEL_SEL_MASK              (0x3U)
+#define CLKCTL0_GAUFCLKSEL_SEL_SHIFT             (0U)
+/*! SEL - GAU Functional Clock Source Selection
+ *  0b00..Main Clock
+ *  0b01..t3pll_mci_256m
+ *  0b10..avpll_ch2_CLKOUT--64MHz
+ *  0b11..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_GAUFCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GAUFCLKSEL_SEL_SHIFT)) & CLKCTL0_GAUFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name PMUFCLKDIV - Pmu FCLK divider */
+/*! @{ */
+
+#define CLKCTL0_PMUFCLKDIV_DIV_MASK              (0xFFU)
+#define CLKCTL0_PMUFCLKDIV_DIV_SHIFT             (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL0_PMUFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PMUFCLKDIV_DIV_SHIFT)) & CLKCTL0_PMUFCLKDIV_DIV_MASK)
+
+#define CLKCTL0_PMUFCLKDIV_RESET_MASK            (0x20000000U)
+#define CLKCTL0_PMUFCLKDIV_RESET_SHIFT           (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL0_PMUFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PMUFCLKDIV_RESET_SHIFT)) & CLKCTL0_PMUFCLKDIV_RESET_MASK)
+
+#define CLKCTL0_PMUFCLKDIV_HALT_MASK             (0x40000000U)
+#define CLKCTL0_PMUFCLKDIV_HALT_SHIFT            (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL0_PMUFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PMUFCLKDIV_HALT_SHIFT)) & CLKCTL0_PMUFCLKDIV_HALT_MASK)
+
+#define CLKCTL0_PMUFCLKDIV_REQFLAG_MASK          (0x80000000U)
+#define CLKCTL0_PMUFCLKDIV_REQFLAG_SHIFT         (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL0_PMUFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PMUFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_PMUFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name BRG_CLK_EN - wl/ble/soc bridge clock enable signal */
+/*! @{ */
+
+#define CLKCTL0_BRG_CLK_EN_WL_MASK               (0x1U)
+#define CLKCTL0_BRG_CLK_EN_WL_SHIFT              (0U)
+/*! WL - 1:enable, clock running 0:disable, clock gated */
+#define CLKCTL0_BRG_CLK_EN_WL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_BRG_CLK_EN_WL_SHIFT)) & CLKCTL0_BRG_CLK_EN_WL_MASK)
+
+#define CLKCTL0_BRG_CLK_EN_BLE_MASK              (0x2U)
+#define CLKCTL0_BRG_CLK_EN_BLE_SHIFT             (1U)
+/*! BLE - 1:enable, clock running 0:disable, clock gated */
+#define CLKCTL0_BRG_CLK_EN_BLE(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_BRG_CLK_EN_BLE_SHIFT)) & CLKCTL0_BRG_CLK_EN_BLE_MASK)
+
+#define CLKCTL0_BRG_CLK_EN_SOC_MASK              (0x4U)
+#define CLKCTL0_BRG_CLK_EN_SOC_SHIFT             (2U)
+/*! SOC - 1:enable, clock running 0:disable, clock gated */
+#define CLKCTL0_BRG_CLK_EN_SOC(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_BRG_CLK_EN_SOC_SHIFT)) & CLKCTL0_BRG_CLK_EN_SOC_MASK)
+/*! @} */
+
+/*! @name G2BIST_CLK_EN - g2bist clock enable signal */
+/*! @{ */
+
+#define CLKCTL0_G2BIST_CLK_EN_VALUE_MASK         (0x1U)
+#define CLKCTL0_G2BIST_CLK_EN_VALUE_SHIFT        (0U)
+/*! VALUE - 1:enable, g2bist_clk running 0:disable, g2bist_clk gated */
+#define CLKCTL0_G2BIST_CLK_EN_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_G2BIST_CLK_EN_VALUE_SHIFT)) & CLKCTL0_G2BIST_CLK_EN_VALUE_MASK)
+/*! @} */
+
+/*! @name MAIN_RAM_CLK_EN - main ram clock enable signal */
+/*! @{ */
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY0_MASK      (0x1U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY0_SHIFT     (0U)
+/*! ARRAY0 - 1:enable, main ram array0 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY0(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY0_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY0_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY1_MASK      (0x2U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY1_SHIFT     (1U)
+/*! ARRAY1 - 1:enable, main ram array1 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY1(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY1_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY1_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY2_MASK      (0x4U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY2_SHIFT     (2U)
+/*! ARRAY2 - 1:enable, main ram array2 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY2(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY2_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY2_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY3_MASK      (0x8U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY3_SHIFT     (3U)
+/*! ARRAY3 - 1:enable, main ram array3 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY3(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY3_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY3_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY4_MASK      (0x10U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY4_SHIFT     (4U)
+/*! ARRAY4 - 1:enable, main ram array4 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY4(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY4_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY4_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY5_MASK      (0x20U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY5_SHIFT     (5U)
+/*! ARRAY5 - 1:enable, main ram array5 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY5(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY5_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY5_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY6_MASK      (0x40U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY6_SHIFT     (6U)
+/*! ARRAY6 - 1:enable, main ram array6 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY6(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY6_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY6_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY7_MASK      (0x80U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY7_SHIFT     (7U)
+/*! ARRAY7 - 1:enable, main ram array7 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY7(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY7_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY7_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY8_MASK      (0x100U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY8_SHIFT     (8U)
+/*! ARRAY8 - 1:enable, main ram array8 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY8(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY8_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY8_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY9_MASK      (0x200U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY9_SHIFT     (9U)
+/*! ARRAY9 - 1:enable, main ram array9 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY9(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY9_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY9_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY10_MASK     (0x400U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY10_SHIFT    (10U)
+/*! ARRAY10 - 1:enable, main ram array10 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY10(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY10_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY10_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY11_MASK     (0x800U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY11_SHIFT    (11U)
+/*! ARRAY11 - 1:enable, main ram array11 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY11(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY11_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY11_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY12_MASK     (0x1000U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY12_SHIFT    (12U)
+/*! ARRAY12 - 1:enable, main ram array12 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY12(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY12_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY12_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY13_MASK     (0x2000U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY13_SHIFT    (13U)
+/*! ARRAY13 - 1:enable, main ram array13 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY13(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY13_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY13_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY14_MASK     (0x4000U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY14_SHIFT    (14U)
+/*! ARRAY14 - 1:enable, main ram array14 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY14(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY14_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY14_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY15_MASK     (0x8000U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY15_SHIFT    (15U)
+/*! ARRAY15 - 1:enable, main ram array15 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY15(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY15_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY15_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY16_MASK     (0x10000U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY16_SHIFT    (16U)
+/*! ARRAY16 - 1:enable, main ram array16 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY16(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY16_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY16_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY17_MASK     (0x20000U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY17_SHIFT    (17U)
+/*! ARRAY17 - 1:enable, main ram array17 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY17(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY17_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY17_MASK)
+
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY18_MASK     (0x40000U)
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY18_SHIFT    (18U)
+/*! ARRAY18 - 1:enable, main ram array18 clock running 0:disable, main ram array0 clock gated */
+#define CLKCTL0_MAIN_RAM_CLK_EN_ARRAY18(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAIN_RAM_CLK_EN_ARRAY18_SHIFT)) & CLKCTL0_MAIN_RAM_CLK_EN_ARRAY18_MASK)
+/*! @} */
+
+/*! @name ELS_GDET_CLK_SEL - ELS GDET CLK selection */
+/*! @{ */
+
+#define CLKCTL0_ELS_GDET_CLK_SEL_SEL_MASK        (0x7U)
+#define CLKCTL0_ELS_GDET_CLK_SEL_SEL_SHIFT       (0U)
+/*! SEL - ELS GDET Clock Source Selection
+ *  0b000..t3pll_mci_256m:256Mhz
+ *  0b001..t3pll_mci_256m/2:128Mhz
+ *  0b010..t3pll_mci_256m/4:64Mhz
+ *  0b011..t3pll_mci_256m/8:32Mhz
+ *  0b100..reserved
+ *  0b101..reserved
+ *  0b110..reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL0_ELS_GDET_CLK_SEL_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ELS_GDET_CLK_SEL_SEL_SHIFT)) & CLKCTL0_ELS_GDET_CLK_SEL_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CLKCTL0_Register_Masks */
+
+
+/* CLKCTL0 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CLKCTL0 base address */
+  #define CLKCTL0_BASE                             (0x50001000u)
+  /** Peripheral CLKCTL0 base address */
+  #define CLKCTL0_BASE_NS                          (0x40001000u)
+  /** Peripheral CLKCTL0 base pointer */
+  #define CLKCTL0                                  ((CLKCTL0_Type *)CLKCTL0_BASE)
+  /** Peripheral CLKCTL0 base pointer */
+  #define CLKCTL0_NS                               ((CLKCTL0_Type *)CLKCTL0_BASE_NS)
+  /** Array initializer of CLKCTL0 peripheral base addresses */
+  #define CLKCTL0_BASE_ADDRS                       { CLKCTL0_BASE }
+  /** Array initializer of CLKCTL0 peripheral base pointers */
+  #define CLKCTL0_BASE_PTRS                        { CLKCTL0 }
+  /** Array initializer of CLKCTL0 peripheral base addresses */
+  #define CLKCTL0_BASE_ADDRS_NS                    { CLKCTL0_BASE_NS }
+  /** Array initializer of CLKCTL0 peripheral base pointers */
+  #define CLKCTL0_BASE_PTRS_NS                     { CLKCTL0_NS }
+#else
+  /** Peripheral CLKCTL0 base address */
+  #define CLKCTL0_BASE                             (0x40001000u)
+  /** Peripheral CLKCTL0 base pointer */
+  #define CLKCTL0                                  ((CLKCTL0_Type *)CLKCTL0_BASE)
+  /** Array initializer of CLKCTL0 peripheral base addresses */
+  #define CLKCTL0_BASE_ADDRS                       { CLKCTL0_BASE }
+  /** Array initializer of CLKCTL0 peripheral base pointers */
+  #define CLKCTL0_BASE_PTRS                        { CLKCTL0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CLKCTL0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CLKCTL1 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL1_Peripheral_Access_Layer CLKCTL1 Peripheral Access Layer
+ * @{
+ */
+
+/** CLKCTL1 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t PSCCTL0;                           /**< Peripheral clock control 0, offset: 0x10 */
+  __IO uint32_t PSCCTL1;                           /**< Peripheral clock control 1, offset: 0x14 */
+  __IO uint32_t PSCCTL2;                           /**< Peripheral clock control 2, offset: 0x18 */
+       uint8_t RESERVED_1[36];
+  __O  uint32_t PSCCTL0_SET;                       /**< Peripheral clock set 0, offset: 0x40 */
+  __O  uint32_t PSCCTL1_SET;                       /**< Peripheral clock set 1, offset: 0x44 */
+  __O  uint32_t PSCCTL2_SET;                       /**< Peripheral clock set 2, offset: 0x48 */
+       uint8_t RESERVED_2[36];
+  __O  uint32_t PSCCTL0_CLR;                       /**< Peripheral clock clear 0, offset: 0x70 */
+  __O  uint32_t PSCCTL1_CLR;                       /**< Peripheral clock clear 1, offset: 0x74 */
+  __O  uint32_t PSCCTL2_CLR;                       /**< Peripheral clock clear 2, offset: 0x78 */
+       uint8_t RESERVED_3[452];
+  __IO uint32_t AUDIOPLLCLKDIV;                    /**< Audio PLL0 clock divider, offset: 0x240 */
+       uint8_t RESERVED_4[572];
+  __IO uint32_t OSEVENTFCLKSEL;                    /**< OS EVENT clock selection, offset: 0x480 */
+       uint8_t RESERVED_5[124];
+  struct {                                         /* offset: 0x500, array step: 0x20 */
+    __IO uint32_t FRGCLKSEL;                         /**< FRG clock selection 0..FRG clock selection 3, array offset: 0x500, array step: 0x20 */
+    __IO uint32_t FRGCTL;                            /**< FRG clock controller 0..FRG clock controller 3, array offset: 0x504, array step: 0x20 */
+    __IO uint32_t FCFCLKSEL;                         /**< Flexcomm Interface clock selection 0..Flexcomm Interface clock selection 3, array offset: 0x508, array step: 0x20 */
+         uint8_t RESERVED_0[20];
+  } FLEXCOMM[4];
+       uint8_t RESERVED_6[320];
+  __IO uint32_t FRG14CLKSEL;                       /**< FRG clock selection 14, offset: 0x6C0 */
+  __IO uint32_t FRG14CTL;                          /**< FRG clock controller 14, offset: 0x6C4 */
+  __IO uint32_t FC14FCLKSEL;                       /**< Flexcomm Interface clock selection 14, offset: 0x6C8 */
+       uint8_t RESERVED_7[48];
+  __IO uint32_t FRGPLLCLKDIV;                      /**< FRG PLL clock divider, offset: 0x6FC */
+  __IO uint32_t DMIC0FCLKSEL;                      /**< DMIC0 clock selection, offset: 0x700 */
+  __IO uint32_t DMIC0CLKDIV;                       /**< DMIC clock divider, offset: 0x704 */
+       uint8_t RESERVED_8[24];
+  __IO uint32_t CT32BITFCLKSEL[4];                 /**< Ct32bit timer 0 clock selection..Ct32bit timer 3 clock selection, array offset: 0x720, array step: 0x4 */
+       uint8_t RESERVED_9[16];
+  __IO uint32_t AUDIOMCLKSEL;                      /**< Audio MCLK selection, offset: 0x740 */
+  __IO uint32_t AUDIOMCLKDIV;                      /**< Audio MCLK divider, offset: 0x744 */
+       uint8_t RESERVED_10[24];
+  __IO uint32_t CLKOUTSEL0;                        /**< Clock out selection 0, offset: 0x760 */
+  __IO uint32_t CLKOUTSEL1;                        /**< Clock out selection 1, offset: 0x764 */
+  __IO uint32_t CLKOUTDIV;                         /**< Clock out divider, offset: 0x768 */
+  __IO uint32_t CLKOUTSEL2;                        /**< Clock out selection 2, offset: 0x76C */
+} CLKCTL1_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CLKCTL1 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL1_Register_Masks CLKCTL1 Register Masks
+ * @{
+ */
+
+/*! @name PSCCTL0 - Peripheral clock control 0 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL0_FC0_MASK                 (0x100U)
+#define CLKCTL1_PSCCTL0_FC0_SHIFT                (8U)
+/*! FC0 - fc0 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL0_FC0(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC0_SHIFT)) & CLKCTL1_PSCCTL0_FC0_MASK)
+
+#define CLKCTL1_PSCCTL0_FC1_MASK                 (0x200U)
+#define CLKCTL1_PSCCTL0_FC1_SHIFT                (9U)
+/*! FC1 - fc1 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL0_FC1(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_SHIFT)) & CLKCTL1_PSCCTL0_FC1_MASK)
+
+#define CLKCTL1_PSCCTL0_FC2_MASK                 (0x400U)
+#define CLKCTL1_PSCCTL0_FC2_SHIFT                (10U)
+/*! FC2 - fc2 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL0_FC2(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC2_SHIFT)) & CLKCTL1_PSCCTL0_FC2_MASK)
+
+#define CLKCTL1_PSCCTL0_FC3_MASK                 (0x800U)
+#define CLKCTL1_PSCCTL0_FC3_SHIFT                (11U)
+/*! FC3 - fc3 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL0_FC3(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC3_SHIFT)) & CLKCTL1_PSCCTL0_FC3_MASK)
+
+#define CLKCTL1_PSCCTL0_FC14_MASK                (0x400000U)
+#define CLKCTL1_PSCCTL0_FC14_SHIFT               (22U)
+/*! FC14 - fc14 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL0_FC14(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC14_SHIFT)) & CLKCTL1_PSCCTL0_FC14_MASK)
+
+#define CLKCTL1_PSCCTL0_DMIC0_MASK               (0x1000000U)
+#define CLKCTL1_PSCCTL0_DMIC0_SHIFT              (24U)
+/*! DMIC0 - dmic0 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL0_DMIC0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_DMIC0_MASK)
+
+#define CLKCTL1_PSCCTL0_OSEVENTTIMER_MASK        (0x8000000U)
+#define CLKCTL1_PSCCTL0_OSEVENTTIMER_SHIFT       (27U)
+/*! OSEVENTTIMER - oseventtimer clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL0_OSEVENTTIMER(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_OSEVENTTIMER_SHIFT)) & CLKCTL1_PSCCTL0_OSEVENTTIMER_MASK)
+/*! @} */
+
+/*! @name PSCCTL1 - Peripheral clock control 1 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL1_HSGPIO0_MASK             (0x1U)
+#define CLKCTL1_PSCCTL1_HSGPIO0_SHIFT            (0U)
+/*! HSGPIO0 - hsgpio0 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO0_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO0_MASK)
+
+#define CLKCTL1_PSCCTL1_HSGPIO1_MASK             (0x2U)
+#define CLKCTL1_PSCCTL1_HSGPIO1_SHIFT            (1U)
+/*! HSGPIO1 - hsgpio1 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO1(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO1_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO1_MASK)
+
+#define CLKCTL1_PSCCTL1_CRC_MASK                 (0x10000U)
+#define CLKCTL1_PSCCTL1_CRC_SHIFT                (16U)
+/*! CRC - crc clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL1_CRC(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CRC_SHIFT)) & CLKCTL1_PSCCTL1_CRC_MASK)
+
+#define CLKCTL1_PSCCTL1_FREQME_MASK              (0x80000000U)
+#define CLKCTL1_PSCCTL1_FREQME_SHIFT             (31U)
+/*! FREQME - freqme clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL1_FREQME(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_FREQME_SHIFT)) & CLKCTL1_PSCCTL1_FREQME_MASK)
+/*! @} */
+
+/*! @name PSCCTL2 - Peripheral clock control 2 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL2_CT32B0_MASK              (0x1U)
+#define CLKCTL1_PSCCTL2_CT32B0_SHIFT             (0U)
+/*! CT32B0 - ct32b0 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_CT32B0(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32B0_SHIFT)) & CLKCTL1_PSCCTL2_CT32B0_MASK)
+
+#define CLKCTL1_PSCCTL2_CT32B1_MASK              (0x2U)
+#define CLKCTL1_PSCCTL2_CT32B1_SHIFT             (1U)
+/*! CT32B1 - ct32b1 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_CT32B1(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32B1_SHIFT)) & CLKCTL1_PSCCTL2_CT32B1_MASK)
+
+#define CLKCTL1_PSCCTL2_CT32B2_MASK              (0x4U)
+#define CLKCTL1_PSCCTL2_CT32B2_SHIFT             (2U)
+/*! CT32B2 - ct32b2 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_CT32B2(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32B2_SHIFT)) & CLKCTL1_PSCCTL2_CT32B2_MASK)
+
+#define CLKCTL1_PSCCTL2_CT32B3_MASK              (0x8U)
+#define CLKCTL1_PSCCTL2_CT32B3_SHIFT             (3U)
+/*! CT32B3 - ct32b3 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_CT32B3(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32B3_SHIFT)) & CLKCTL1_PSCCTL2_CT32B3_MASK)
+
+#define CLKCTL1_PSCCTL2_CT32B4_MASK              (0x10U)
+#define CLKCTL1_PSCCTL2_CT32B4_SHIFT             (4U)
+/*! CT32B4 - ct32b4 clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_CT32B4(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32B4_SHIFT)) & CLKCTL1_PSCCTL2_CT32B4_MASK)
+
+#define CLKCTL1_PSCCTL2_PMU_MASK                 (0x40U)
+#define CLKCTL1_PSCCTL2_PMU_SHIFT                (6U)
+/*! PMU - pmu clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_PMU(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_PMU_SHIFT)) & CLKCTL1_PSCCTL2_PMU_MASK)
+
+#define CLKCTL1_PSCCTL2_RTC_LITE_MASK            (0x80U)
+#define CLKCTL1_PSCCTL2_RTC_LITE_SHIFT           (7U)
+/*! RTC_LITE - rtc_lite clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_RTC_LITE(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_RTC_LITE_SHIFT)) & CLKCTL1_PSCCTL2_RTC_LITE_MASK)
+
+#define CLKCTL1_PSCCTL2_MRT_MASK                 (0x100U)
+#define CLKCTL1_PSCCTL2_MRT_SHIFT                (8U)
+/*! MRT - mrt clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_MRT(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_MRT_SHIFT)) & CLKCTL1_PSCCTL2_MRT_MASK)
+
+#define CLKCTL1_PSCCTL2_GPIO_INT_MASK            (0x40000000U)
+#define CLKCTL1_PSCCTL2_GPIO_INT_SHIFT           (30U)
+/*! GPIO_INT - gpio_int clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_GPIO_INT(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_GPIO_INT_SHIFT)) & CLKCTL1_PSCCTL2_GPIO_INT_MASK)
+
+#define CLKCTL1_PSCCTL2_PMUX_MASK                (0x80000000U)
+#define CLKCTL1_PSCCTL2_PMUX_SHIFT               (31U)
+/*! PMUX - pmux clock control
+ *  0b0..Disable clock
+ *  0b1..Enable clock
+ */
+#define CLKCTL1_PSCCTL2_PMUX(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_PMUX_SHIFT)) & CLKCTL1_PSCCTL2_PMUX_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_SET - Peripheral clock set 0 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL0_SET_FC0_MASK             (0x100U)
+#define CLKCTL1_PSCCTL0_SET_FC0_SHIFT            (8U)
+/*! FC0 - fc0 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC0_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC0_MASK)
+
+#define CLKCTL1_PSCCTL0_SET_FC1_MASK             (0x200U)
+#define CLKCTL1_PSCCTL0_SET_FC1_SHIFT            (9U)
+/*! FC1 - fc1 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC1(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC1_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC1_MASK)
+
+#define CLKCTL1_PSCCTL0_SET_FC2_MASK             (0x400U)
+#define CLKCTL1_PSCCTL0_SET_FC2_SHIFT            (10U)
+/*! FC2 - fc2 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC2(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC2_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC2_MASK)
+
+#define CLKCTL1_PSCCTL0_SET_FC3_MASK             (0x800U)
+#define CLKCTL1_PSCCTL0_SET_FC3_SHIFT            (11U)
+/*! FC3 - fc3 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC3(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC3_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC3_MASK)
+
+#define CLKCTL1_PSCCTL0_SET_FC14_MASK            (0x400000U)
+#define CLKCTL1_PSCCTL0_SET_FC14_SHIFT           (22U)
+/*! FC14 - fc14 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC14(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC14_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC14_MASK)
+
+#define CLKCTL1_PSCCTL0_SET_DMIC0_MASK           (0x1000000U)
+#define CLKCTL1_PSCCTL0_SET_DMIC0_SHIFT          (24U)
+/*! DMIC0 - dmic0 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_SET_DMIC0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_SET_DMIC0_MASK)
+
+#define CLKCTL1_PSCCTL0_SET_OSEVENTTIMER_MASK    (0x8000000U)
+#define CLKCTL1_PSCCTL0_SET_OSEVENTTIMER_SHIFT   (27U)
+/*! OSEVENTTIMER - oseventtimer clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_SET_OSEVENTTIMER(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_OSEVENTTIMER_SHIFT)) & CLKCTL1_PSCCTL0_SET_OSEVENTTIMER_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_SET - Peripheral clock set 1 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL1_SET_HSGPIO0_MASK         (0x1U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO0_SHIFT        (0U)
+/*! HSGPIO0 - hsgpio0 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO0_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO0_MASK)
+
+#define CLKCTL1_PSCCTL1_SET_HSGPIO1_MASK         (0x2U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO1_SHIFT        (1U)
+/*! HSGPIO1 - hsgpio1 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO1(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO1_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO1_MASK)
+
+#define CLKCTL1_PSCCTL1_SET_CRC_MASK             (0x10000U)
+#define CLKCTL1_PSCCTL1_SET_CRC_SHIFT            (16U)
+/*! CRC - crc clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_SET_CRC(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CRC_SHIFT)) & CLKCTL1_PSCCTL1_SET_CRC_MASK)
+
+#define CLKCTL1_PSCCTL1_SET_FREQME_MASK          (0x80000000U)
+#define CLKCTL1_PSCCTL1_SET_FREQME_SHIFT         (31U)
+/*! FREQME - freqme clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_SET_FREQME(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_FREQME_SHIFT)) & CLKCTL1_PSCCTL1_SET_FREQME_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_SET - Peripheral clock set 2 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL2_SET_CT32B0_MASK          (0x1U)
+#define CLKCTL1_PSCCTL2_SET_CT32B0_SHIFT         (0U)
+/*! CT32B0 - ct32b0 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32B0(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32B0_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32B0_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_CT32B1_MASK          (0x2U)
+#define CLKCTL1_PSCCTL2_SET_CT32B1_SHIFT         (1U)
+/*! CT32B1 - ct32b1 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32B1(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32B1_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32B1_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_CT32B2_MASK          (0x4U)
+#define CLKCTL1_PSCCTL2_SET_CT32B2_SHIFT         (2U)
+/*! CT32B2 - ct32b2 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32B2(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32B2_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32B2_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_CT32B3_MASK          (0x8U)
+#define CLKCTL1_PSCCTL2_SET_CT32B3_SHIFT         (3U)
+/*! CT32B3 - ct32b3 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32B3(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32B3_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32B3_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_CT32B4_MASK          (0x10U)
+#define CLKCTL1_PSCCTL2_SET_CT32B4_SHIFT         (4U)
+/*! CT32B4 - ct32b4 clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32B4(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32B4_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32B4_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_PMU_MASK             (0x40U)
+#define CLKCTL1_PSCCTL2_SET_PMU_SHIFT            (6U)
+/*! PMU - pmu clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_PMU(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_PMU_SHIFT)) & CLKCTL1_PSCCTL2_SET_PMU_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_RTC_LITE_MASK        (0x80U)
+#define CLKCTL1_PSCCTL2_SET_RTC_LITE_SHIFT       (7U)
+/*! RTC_LITE - rtc_lite clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_RTC_LITE(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_RTC_LITE_SHIFT)) & CLKCTL1_PSCCTL2_SET_RTC_LITE_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_MRT_MASK             (0x100U)
+#define CLKCTL1_PSCCTL2_SET_MRT_SHIFT            (8U)
+/*! MRT - mrt clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_MRT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_MRT_SHIFT)) & CLKCTL1_PSCCTL2_SET_MRT_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_GPIO_INT_MASK        (0x40000000U)
+#define CLKCTL1_PSCCTL2_SET_GPIO_INT_SHIFT       (30U)
+/*! GPIO_INT - gpio_int clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_GPIO_INT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_GPIO_INT_SHIFT)) & CLKCTL1_PSCCTL2_SET_GPIO_INT_MASK)
+
+#define CLKCTL1_PSCCTL2_SET_PMUX_MASK            (0x80000000U)
+#define CLKCTL1_PSCCTL2_SET_PMUX_SHIFT           (31U)
+/*! PMUX - pmux clock set
+ *  0b0..No effect
+ *  0b1..Sets the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_PMUX(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_PMUX_SHIFT)) & CLKCTL1_PSCCTL2_SET_PMUX_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_CLR - Peripheral clock clear 0 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL0_CLR_FC0_MASK             (0x100U)
+#define CLKCTL1_PSCCTL0_CLR_FC0_SHIFT            (8U)
+/*! FC0 - fc0 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC0_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC0_MASK)
+
+#define CLKCTL1_PSCCTL0_CLR_FC1_MASK             (0x200U)
+#define CLKCTL1_PSCCTL0_CLR_FC1_SHIFT            (9U)
+/*! FC1 - fc1 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC1(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC1_MASK)
+
+#define CLKCTL1_PSCCTL0_CLR_FC2_MASK             (0x400U)
+#define CLKCTL1_PSCCTL0_CLR_FC2_SHIFT            (10U)
+/*! FC2 - fc2 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC2(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC2_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC2_MASK)
+
+#define CLKCTL1_PSCCTL0_CLR_FC3_MASK             (0x800U)
+#define CLKCTL1_PSCCTL0_CLR_FC3_SHIFT            (11U)
+/*! FC3 - fc3 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC3(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC3_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC3_MASK)
+
+#define CLKCTL1_PSCCTL0_CLR_FC14_MASK            (0x400000U)
+#define CLKCTL1_PSCCTL0_CLR_FC14_SHIFT           (22U)
+/*! FC14 - fc14 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC14(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC14_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC14_MASK)
+
+#define CLKCTL1_PSCCTL0_CLR_DMIC0_MASK           (0x1000000U)
+#define CLKCTL1_PSCCTL0_CLR_DMIC0_SHIFT          (24U)
+/*! DMIC0 - dmic0 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_DMIC0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_CLR_DMIC0_MASK)
+
+#define CLKCTL1_PSCCTL0_CLR_OSEVENTTIMER_MASK    (0x8000000U)
+#define CLKCTL1_PSCCTL0_CLR_OSEVENTTIMER_SHIFT   (27U)
+/*! OSEVENTTIMER - oseventtimer clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL0 Bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_OSEVENTTIMER(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_OSEVENTTIMER_SHIFT)) & CLKCTL1_PSCCTL0_CLR_OSEVENTTIMER_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_CLR - Peripheral clock clear 1 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_MASK         (0x1U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_SHIFT        (0U)
+/*! HSGPIO0 - hsgpio0 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO0(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO0_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO0_MASK)
+
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_MASK         (0x2U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_SHIFT        (1U)
+/*! HSGPIO1 - hsgpio1 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO1(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO1_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO1_MASK)
+
+#define CLKCTL1_PSCCTL1_CLR_CRC_MASK             (0x10000U)
+#define CLKCTL1_PSCCTL1_CLR_CRC_SHIFT            (16U)
+/*! CRC - crc clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_CRC(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_CRC_SHIFT)) & CLKCTL1_PSCCTL1_CLR_CRC_MASK)
+
+#define CLKCTL1_PSCCTL1_CLR_FREQME_MASK          (0x80000000U)
+#define CLKCTL1_PSCCTL1_CLR_FREQME_SHIFT         (31U)
+/*! FREQME - freqme clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL1 Bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_FREQME(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_FREQME_SHIFT)) & CLKCTL1_PSCCTL1_CLR_FREQME_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_CLR - Peripheral clock clear 2 */
+/*! @{ */
+
+#define CLKCTL1_PSCCTL2_CLR_CT32B0_MASK          (0x1U)
+#define CLKCTL1_PSCCTL2_CLR_CT32B0_SHIFT         (0U)
+/*! CT32B0 - ct32b0 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32B0(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32B0_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32B0_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_CT32B1_MASK          (0x2U)
+#define CLKCTL1_PSCCTL2_CLR_CT32B1_SHIFT         (1U)
+/*! CT32B1 - ct32b1 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32B1(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32B1_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32B1_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_CT32B2_MASK          (0x4U)
+#define CLKCTL1_PSCCTL2_CLR_CT32B2_SHIFT         (2U)
+/*! CT32B2 - ct32b2 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32B2(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32B2_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32B2_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_CT32B3_MASK          (0x8U)
+#define CLKCTL1_PSCCTL2_CLR_CT32B3_SHIFT         (3U)
+/*! CT32B3 - ct32b3 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32B3(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32B3_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32B3_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_CT32B4_MASK          (0x10U)
+#define CLKCTL1_PSCCTL2_CLR_CT32B4_SHIFT         (4U)
+/*! CT32B4 - ct32b4 clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32B4(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32B4_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32B4_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_PMU_MASK             (0x40U)
+#define CLKCTL1_PSCCTL2_CLR_PMU_SHIFT            (6U)
+/*! PMU - pmu clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_PMU(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_PMU_SHIFT)) & CLKCTL1_PSCCTL2_CLR_PMU_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_RTC_LITE_MASK        (0x80U)
+#define CLKCTL1_PSCCTL2_CLR_RTC_LITE_SHIFT       (7U)
+/*! RTC_LITE - rtc_lite clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_RTC_LITE(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_RTC_LITE_SHIFT)) & CLKCTL1_PSCCTL2_CLR_RTC_LITE_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_MRT_MASK             (0x100U)
+#define CLKCTL1_PSCCTL2_CLR_MRT_SHIFT            (8U)
+/*! MRT - mrt clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_MRT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_MRT_SHIFT)) & CLKCTL1_PSCCTL2_CLR_MRT_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_GPIO_INT_MASK        (0x40000000U)
+#define CLKCTL1_PSCCTL2_CLR_GPIO_INT_SHIFT       (30U)
+/*! GPIO_INT - gpio_int clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_GPIO_INT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_GPIO_INT_SHIFT)) & CLKCTL1_PSCCTL2_CLR_GPIO_INT_MASK)
+
+#define CLKCTL1_PSCCTL2_CLR_PMUX_MASK            (0x80000000U)
+#define CLKCTL1_PSCCTL2_CLR_PMUX_SHIFT           (31U)
+/*! PMUX - pmux clock clear
+ *  0b0..No effect
+ *  0b1..Clears the PSCCTL2 Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_PMUX(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_PMUX_SHIFT)) & CLKCTL1_PSCCTL2_CLR_PMUX_MASK)
+/*! @} */
+
+/*! @name AUDIOPLLCLKDIV - Audio PLL0 clock divider */
+/*! @{ */
+
+#define CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK          (0xFFU)
+#define CLKCTL1_AUDIOPLLCLKDIV_DIV_SHIFT         (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL1_AUDIOPLLCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_DIV_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK)
+
+#define CLKCTL1_AUDIOPLLCLKDIV_RESET_MASK        (0x20000000U)
+#define CLKCTL1_AUDIOPLLCLKDIV_RESET_SHIFT       (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL1_AUDIOPLLCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_RESET_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_RESET_MASK)
+
+#define CLKCTL1_AUDIOPLLCLKDIV_HALT_MASK         (0x40000000U)
+#define CLKCTL1_AUDIOPLLCLKDIV_HALT_SHIFT        (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL1_AUDIOPLLCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_HALT_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_HALT_MASK)
+
+#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_MASK      (0x80000000U)
+#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_SHIFT     (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name OSEVENTFCLKSEL - OS EVENT clock selection */
+/*! @{ */
+
+#define CLKCTL1_OSEVENTFCLKSEL_SEL_MASK          (0x7U)
+#define CLKCTL1_OSEVENTFCLKSEL_SEL_SHIFT         (0U)
+/*! SEL - OS Event Timer Functional Clock Source Selection
+ *  0b000..1m_lposc
+ *  0b001..32 kHz Clock
+ *  0b010..Cortex-M33 clock (hclk)
+ *  0b011..Reserved
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_OSEVENTFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_OSEVENTFCLKSEL_SEL_SHIFT)) & CLKCTL1_OSEVENTFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FRGCLKSEL - FRG clock selection 0..FRG clock selection 3 */
+/*! @{ */
+
+#define CLKCTL1_FRGCLKSEL_SEL_MASK               (0x7U)
+#define CLKCTL1_FRGCLKSEL_SEL_SHIFT              (0U)
+/*! SEL - Fractional Gen. Clock Source Selection
+ *  0b000..Main Clock
+ *  0b001..FRG PLL Clock
+ *  0b010..SFRO Clock (16m_irc).
+ *  0b011..FFRO Clock (48/60m_irc).
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_FRGCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCLKSEL_SEL_SHIFT)) & CLKCTL1_FRGCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_FRGCLKSEL */
+#define CLKCTL1_FRGCLKSEL_COUNT                  (4U)
+
+/*! @name FRGCTL - FRG clock controller 0..FRG clock controller 3 */
+/*! @{ */
+
+#define CLKCTL1_FRGCTL_DIV_MASK                  (0xFFU)
+#define CLKCTL1_FRGCTL_DIV_SHIFT                 (0U)
+/*! DIV - Denominator of the fractional divider. DIV is minus 1 encoded, the denominator value is
+ *    the value of this field + 1. Always set to 0xFF (denominator = 256) to use with the fractional
+ *    baud rate generator.
+ */
+#define CLKCTL1_FRGCTL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCTL_DIV_SHIFT)) & CLKCTL1_FRGCTL_DIV_MASK)
+
+#define CLKCTL1_FRGCTL_MULT_MASK                 (0xFF00U)
+#define CLKCTL1_FRGCTL_MULT_SHIFT                (8U)
+/*! MULT - Numerator of the fractional divider. MULT is not minus 1 encoded, so the numerator value
+ *    is simply the value in this field.
+ */
+#define CLKCTL1_FRGCTL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCTL_MULT_SHIFT)) & CLKCTL1_FRGCTL_MULT_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_FRGCTL */
+#define CLKCTL1_FRGCTL_COUNT                     (4U)
+
+/*! @name FCFCLKSEL - Flexcomm Interface clock selection 0..Flexcomm Interface clock selection 3 */
+/*! @{ */
+
+#define CLKCTL1_FCFCLKSEL_SEL_MASK               (0x7U)
+#define CLKCTL1_FCFCLKSEL_SEL_SHIFT              (0U)
+/*! SEL - Flexcomm Functional Clock Source Selection
+ *  0b000..SFRO Clock (16m_irc)
+ *  0b001..FFRO Clock (48/60m_irc).
+ *  0b010..Audio PLL Clock (audio_pll_clk).
+ *  0b011..Master Clock In (mclk_in).
+ *  0b100..FCn FRG Clock (frg_clk n).
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_FCFCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FCFCLKSEL_SEL_SHIFT)) & CLKCTL1_FCFCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_FCFCLKSEL */
+#define CLKCTL1_FCFCLKSEL_COUNT                  (4U)
+
+/*! @name FRG14CLKSEL - FRG clock selection 14 */
+/*! @{ */
+
+#define CLKCTL1_FRG14CLKSEL_SEL_MASK             (0x7U)
+#define CLKCTL1_FRG14CLKSEL_SEL_SHIFT            (0U)
+/*! SEL - Fractional Gen. Clock Source Selection
+ *  0b000..Main Clock
+ *  0b001..FRG PLL Clock
+ *  0b010..SFRO Clock (16m_irc).
+ *  0b011..FFRO Clock (48/60m_irc).
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_FRG14CLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG14CLKSEL_SEL_SHIFT)) & CLKCTL1_FRG14CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FRG14CTL - FRG clock controller 14 */
+/*! @{ */
+
+#define CLKCTL1_FRG14CTL_DIV_MASK                (0xFFU)
+#define CLKCTL1_FRG14CTL_DIV_SHIFT               (0U)
+/*! DIV - Denominator of the fractional divider. DIV is minus 1 encoded, the denominator value is
+ *    the value of this field + 1. Always set to 0xFF (denominator = 256) to use with the fractional
+ *    baud rate generator.
+ */
+#define CLKCTL1_FRG14CTL_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG14CTL_DIV_SHIFT)) & CLKCTL1_FRG14CTL_DIV_MASK)
+
+#define CLKCTL1_FRG14CTL_MULT_MASK               (0xFF00U)
+#define CLKCTL1_FRG14CTL_MULT_SHIFT              (8U)
+/*! MULT - Numerator of the fractional divider. MULT is not minus 1 encoded, so the numerator value
+ *    is simply the value in this field.
+ */
+#define CLKCTL1_FRG14CTL_MULT(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG14CTL_MULT_SHIFT)) & CLKCTL1_FRG14CTL_MULT_MASK)
+/*! @} */
+
+/*! @name FC14FCLKSEL - Flexcomm Interface clock selection 14 */
+/*! @{ */
+
+#define CLKCTL1_FC14FCLKSEL_SEL_MASK             (0x7U)
+#define CLKCTL1_FC14FCLKSEL_SEL_SHIFT            (0U)
+/*! SEL - Flexcomm Functional Clock Source Selection
+ *  0b000..SFRO Clock (16m_irc)
+ *  0b001..FFRO Clock (48/60m_irc).
+ *  0b010..Audio PLL Clock (audio_pll_clk).
+ *  0b011..Master Clock In (mclk_in).
+ *  0b100..FCn FRG Clock (frg_clk n).
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_FC14FCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FC14FCLKSEL_SEL_SHIFT)) & CLKCTL1_FC14FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FRGPLLCLKDIV - FRG PLL clock divider */
+/*! @{ */
+
+#define CLKCTL1_FRGPLLCLKDIV_DIV_MASK            (0xFFU)
+#define CLKCTL1_FRGPLLCLKDIV_DIV_SHIFT           (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL1_FRGPLLCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_DIV_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_DIV_MASK)
+
+#define CLKCTL1_FRGPLLCLKDIV_RESET_MASK          (0x20000000U)
+#define CLKCTL1_FRGPLLCLKDIV_RESET_SHIFT         (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL1_FRGPLLCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_RESET_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_RESET_MASK)
+
+#define CLKCTL1_FRGPLLCLKDIV_HALT_MASK           (0x40000000U)
+#define CLKCTL1_FRGPLLCLKDIV_HALT_SHIFT          (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL1_FRGPLLCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_HALT_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_HALT_MASK)
+
+#define CLKCTL1_FRGPLLCLKDIV_REQFLAG_MASK        (0x80000000U)
+#define CLKCTL1_FRGPLLCLKDIV_REQFLAG_SHIFT       (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL1_FRGPLLCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DMIC0FCLKSEL - DMIC0 clock selection */
+/*! @{ */
+
+#define CLKCTL1_DMIC0FCLKSEL_SEL_MASK            (0x7U)
+#define CLKCTL1_DMIC0FCLKSEL_SEL_SHIFT           (0U)
+/*! SEL - DMIC Functional Clock Source Selection
+ *  0b000..SFRO Clock (16m_irc)
+ *  0b001..FFRO Clock (48/60m_irc).
+ *  0b010..Audio PLL Clock (audio_pll_clk).
+ *  0b011..Master Clock In (mclk_in).
+ *  0b100..1m_lposc
+ *  0b101..32 kHz Wake Clk
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_DMIC0FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKSEL_SEL_SHIFT)) & CLKCTL1_DMIC0FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name DMIC0CLKDIV - DMIC clock divider */
+/*! @{ */
+
+#define CLKCTL1_DMIC0CLKDIV_DIV_MASK             (0xFFU)
+#define CLKCTL1_DMIC0CLKDIV_DIV_SHIFT            (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL1_DMIC0CLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0CLKDIV_DIV_SHIFT)) & CLKCTL1_DMIC0CLKDIV_DIV_MASK)
+
+#define CLKCTL1_DMIC0CLKDIV_RESET_MASK           (0x20000000U)
+#define CLKCTL1_DMIC0CLKDIV_RESET_SHIFT          (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL1_DMIC0CLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0CLKDIV_RESET_SHIFT)) & CLKCTL1_DMIC0CLKDIV_RESET_MASK)
+
+#define CLKCTL1_DMIC0CLKDIV_HALT_MASK            (0x40000000U)
+#define CLKCTL1_DMIC0CLKDIV_HALT_SHIFT           (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL1_DMIC0CLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0CLKDIV_HALT_SHIFT)) & CLKCTL1_DMIC0CLKDIV_HALT_MASK)
+
+#define CLKCTL1_DMIC0CLKDIV_REQFLAG_MASK         (0x80000000U)
+#define CLKCTL1_DMIC0CLKDIV_REQFLAG_SHIFT        (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL1_DMIC0CLKDIV_REQFLAG(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0CLKDIV_REQFLAG_SHIFT)) & CLKCTL1_DMIC0CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CT32BITFCLKSEL - Ct32bit timer 0 clock selection..Ct32bit timer 3 clock selection */
+/*! @{ */
+
+#define CLKCTL1_CT32BITFCLKSEL_SEL_MASK          (0x7U)
+#define CLKCTL1_CT32BITFCLKSEL_SEL_SHIFT         (0U)
+/*! SEL - CT32Bit Functional Clock Source Selection
+ *  0b000..Main Clock
+ *  0b001..SFRO Clock (16m_irc).
+ *  0b010..FFRO Clock (48/60m_irc).
+ *  0b011..Audio PLL Clock (audio_pll_clk).
+ *  0b100..Master Clock In (mclk_in).
+ *  0b101..1m_lposc
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_CT32BITFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CT32BITFCLKSEL_SEL_SHIFT)) & CLKCTL1_CT32BITFCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_CT32BITFCLKSEL */
+#define CLKCTL1_CT32BITFCLKSEL_COUNT             (4U)
+
+/*! @name AUDIOMCLKSEL - Audio MCLK selection */
+/*! @{ */
+
+#define CLKCTL1_AUDIOMCLKSEL_SEL_MASK            (0x7U)
+#define CLKCTL1_AUDIOMCLKSEL_SEL_SHIFT           (0U)
+/*! SEL - Audio MCLK Clock Source Selection
+ *  0b000..FFRO Clock (48/60m_irc).
+ *  0b001..Audio PLL Clock (audio_pll_clk).
+ *  0b010..main_clk
+ *  0b011..Reserved
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_AUDIOMCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKSEL_SEL_SHIFT)) & CLKCTL1_AUDIOMCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name AUDIOMCLKDIV - Audio MCLK divider */
+/*! @{ */
+
+#define CLKCTL1_AUDIOMCLKDIV_DIV_MASK            (0xFFU)
+#define CLKCTL1_AUDIOMCLKDIV_DIV_SHIFT           (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL1_AUDIOMCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_DIV_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_DIV_MASK)
+
+#define CLKCTL1_AUDIOMCLKDIV_RESET_MASK          (0x20000000U)
+#define CLKCTL1_AUDIOMCLKDIV_RESET_SHIFT         (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL1_AUDIOMCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_RESET_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_RESET_MASK)
+
+#define CLKCTL1_AUDIOMCLKDIV_HALT_MASK           (0x40000000U)
+#define CLKCTL1_AUDIOMCLKDIV_HALT_SHIFT          (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL1_AUDIOMCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_HALT_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_HALT_MASK)
+
+#define CLKCTL1_AUDIOMCLKDIV_REQFLAG_MASK        (0x80000000U)
+#define CLKCTL1_AUDIOMCLKDIV_REQFLAG_SHIFT       (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL1_AUDIOMCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CLKOUTSEL0 - Clock out selection 0 */
+/*! @{ */
+
+#define CLKCTL1_CLKOUTSEL0_SEL_MASK              (0x7U)
+#define CLKCTL1_CLKOUTSEL0_SEL_SHIFT             (0U)
+/*! SEL - Clock Output Select 1st Stage
+ *  0b000..SFRO Clock
+ *  0b001..External clock (clk_in).
+ *  0b010..1m_lposc
+ *  0b011..FFRO Clock
+ *  0b100..Main Clock (main_clk).
+ *  0b101..refclk_sys(38.4M).
+ *  0b110..avpll_ch2_CLKOUT(64M)
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_CLKOUTSEL0_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTSEL0_SEL_SHIFT)) & CLKCTL1_CLKOUTSEL0_SEL_MASK)
+/*! @} */
+
+/*! @name CLKOUTSEL1 - Clock out selection 1 */
+/*! @{ */
+
+#define CLKCTL1_CLKOUTSEL1_SEL_MASK              (0x7U)
+#define CLKCTL1_CLKOUTSEL1_SEL_SHIFT             (0U)
+/*! SEL - Clock Output Select 2nd Stage
+ *  0b000..CLKOUTSEL0 Multiplexed Output
+ *  0b001..Main PLL Clock (main_pll_clk).
+ *  0b010..AUX0 PLL clock (aux0_pll_clk).
+ *  0b011..Reserved
+ *  0b100..AUX1 PLL clock (aux1_pll_clk)
+ *  0b101..Audio PLL Clock (audio_pll_clk).
+ *  0b110..32 kHz RTC Clock.
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_CLKOUTSEL1_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTSEL1_SEL_SHIFT)) & CLKCTL1_CLKOUTSEL1_SEL_MASK)
+/*! @} */
+
+/*! @name CLKOUTDIV - Clock out divider */
+/*! @{ */
+
+#define CLKCTL1_CLKOUTDIV_DIV_MASK               (0xFFU)
+#define CLKCTL1_CLKOUTDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256 */
+#define CLKCTL1_CLKOUTDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTDIV_DIV_SHIFT)) & CLKCTL1_CLKOUTDIV_DIV_MASK)
+
+#define CLKCTL1_CLKOUTDIV_RESET_MASK             (0x20000000U)
+#define CLKCTL1_CLKOUTDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ *    away rather than completing the previous count
+ */
+#define CLKCTL1_CLKOUTDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTDIV_RESET_SHIFT)) & CLKCTL1_CLKOUTDIV_RESET_MASK)
+
+#define CLKCTL1_CLKOUTDIV_HALT_MASK              (0x40000000U)
+#define CLKCTL1_CLKOUTDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
+ *    without the risk of a glitch at the output
+ */
+#define CLKCTL1_CLKOUTDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTDIV_HALT_SHIFT)) & CLKCTL1_CLKOUTDIV_HALT_MASK)
+
+#define CLKCTL1_CLKOUTDIV_REQFLAG_MASK           (0x80000000U)
+#define CLKCTL1_CLKOUTDIV_REQFLAG_SHIFT          (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the
+ *    change is complete. The clock being divided must be running for this status to change
+ */
+#define CLKCTL1_CLKOUTDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTDIV_REQFLAG_SHIFT)) & CLKCTL1_CLKOUTDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CLKOUTSEL2 - Clock out selection 2 */
+/*! @{ */
+
+#define CLKCTL1_CLKOUTSEL2_SEL_MASK              (0x7U)
+#define CLKCTL1_CLKOUTSEL2_SEL_SHIFT             (0U)
+/*! SEL - Clock Output Select 3rd Stage
+ *  0b000..CLKOUTSEL1 Multiplexed Output
+ *  0b001..tcpu_mci_flexspi_clk
+ *  0b010..tddr_mci_flexspi_clk
+ *  0b011..t3pll_mci_flexspi_clk
+ *  0b100..t3pll_mci_256m
+ *  0b101..cau_slp_ref_clk
+ *  0b110..tddr_mci_enet_clk
+ *  0b111..None, this may be selected in order to reduce power when no output is needed
+ */
+#define CLKCTL1_CLKOUTSEL2_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTSEL2_SEL_SHIFT)) & CLKCTL1_CLKOUTSEL2_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CLKCTL1_Register_Masks */
+
+
+/* CLKCTL1 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CLKCTL1 base address */
+  #define CLKCTL1_BASE                             (0x50021000u)
+  /** Peripheral CLKCTL1 base address */
+  #define CLKCTL1_BASE_NS                          (0x40021000u)
+  /** Peripheral CLKCTL1 base pointer */
+  #define CLKCTL1                                  ((CLKCTL1_Type *)CLKCTL1_BASE)
+  /** Peripheral CLKCTL1 base pointer */
+  #define CLKCTL1_NS                               ((CLKCTL1_Type *)CLKCTL1_BASE_NS)
+  /** Array initializer of CLKCTL1 peripheral base addresses */
+  #define CLKCTL1_BASE_ADDRS                       { CLKCTL1_BASE }
+  /** Array initializer of CLKCTL1 peripheral base pointers */
+  #define CLKCTL1_BASE_PTRS                        { CLKCTL1 }
+  /** Array initializer of CLKCTL1 peripheral base addresses */
+  #define CLKCTL1_BASE_ADDRS_NS                    { CLKCTL1_BASE_NS }
+  /** Array initializer of CLKCTL1 peripheral base pointers */
+  #define CLKCTL1_BASE_PTRS_NS                     { CLKCTL1_NS }
+#else
+  /** Peripheral CLKCTL1 base address */
+  #define CLKCTL1_BASE                             (0x40021000u)
+  /** Peripheral CLKCTL1 base pointer */
+  #define CLKCTL1                                  ((CLKCTL1_Type *)CLKCTL1_BASE)
+  /** Array initializer of CLKCTL1 peripheral base addresses */
+  #define CLKCTL1_BASE_ADDRS                       { CLKCTL1_BASE }
+  /** Array initializer of CLKCTL1 peripheral base pointers */
+  #define CLKCTL1_BASE_PTRS                        { CLKCTL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CLKCTL1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+/*! @{ */
+
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial */
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) */
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA */
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM */
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM */
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+/*! @} */
+
+/*! @name SEED - CRC seed register */
+/*! @{ */
+
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
+ *    selected bit order and 1's complement pre-processes. A write access to this register will
+ *    overrule the CRC calculation in progresses.
+ */
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name SUM - CRC checksum register */
+/*! @{ */
+
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. */
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+/*! @} */
+
+/*! @name WR_DATA - CRC data register */
+/*! @{ */
+
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
+ *    selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
+ *    accept back-to-back transactions.
+ */
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CRC base address */
+  #define CRC_BASE                                 (0x50120000u)
+  /** Peripheral CRC base address */
+  #define CRC_BASE_NS                              (0x40120000u)
+  /** Peripheral CRC base pointer */
+  #define CRC                                      ((CRC_Type *)CRC_BASE)
+  /** Peripheral CRC base pointer */
+  #define CRC_NS                                   ((CRC_Type *)CRC_BASE_NS)
+  /** Array initializer of CRC peripheral base addresses */
+  #define CRC_BASE_ADDRS                           { CRC_BASE }
+  /** Array initializer of CRC peripheral base pointers */
+  #define CRC_BASE_PTRS                            { CRC }
+  /** Array initializer of CRC peripheral base addresses */
+  #define CRC_BASE_ADDRS_NS                        { CRC_BASE_NS }
+  /** Array initializer of CRC peripheral base pointers */
+  #define CRC_BASE_PTRS_NS                         { CRC_NS }
+#else
+  /** Peripheral CRC base address */
+  #define CRC_BASE                                 (0x40120000u)
+  /** Peripheral CRC base pointer */
+  #define CRC                                      ((CRC_Type *)CRC_BASE)
+  /** Array initializer of CRC peripheral base addresses */
+  #define CRC_BASE_ADDRS                           { CRC_BASE }
+  /** Array initializer of CRC peripheral base pointers */
+  #define CRC_BASE_PTRS                            { CRC }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register, offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter., offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register, array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register, offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register, array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register, offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register, offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register, offset: 0x74 */
+  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. */
+/*! @{ */
+
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+/*! MR0INT - Interrupt flag for match channel 0 */
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+/*! MR1INT - Interrupt flag for match channel 1 */
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+/*! MR2INT - Interrupt flag for match channel 2 */
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+/*! MR3INT - Interrupt flag for match channel 3 */
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+/*! CR0INT - Interrupt flag for capture channel 0 event */
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+/*! CR1INT - Interrupt flag for capture channel 1 event */
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+/*! CR2INT - Interrupt flag for capture channel 2 event */
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+/*! CR3INT - Interrupt flag for capture channel 3 event */
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control Register */
+/*! @{ */
+
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+/*! CEN - Counter enable.
+ *  0b0..Disabled. The counters are disabled.
+ *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled. When the timer is enabled by an external
+ *       trigger or globally enabled by the external global start enable register, the CEN bit will automatically be
+ *       set to 1.
+ */
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+/*! CRST - Counter reset.
+ *  0b0..Disabled. Do nothing.
+ *  0b1..Enabled
+ */
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+
+#define CTIMER_TCR_AGCEN_MASK                    (0x10U)
+#define CTIMER_TCR_AGCEN_SHIFT                   (4U)
+/*! AGCEN - Allow Global Count Enable
+ *  0b0..Not allowed
+ *  0b1..Allow input global_enable=1 action to take effect
+ */
+#define CTIMER_TCR_AGCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK)
+
+#define CTIMER_TCR_ATCEN_MASK                    (0x20U)
+#define CTIMER_TCR_ATCEN_SHIFT                   (5U)
+/*! ATCEN - Allow Trigger Count Enable
+ *  0b0..Not allowed
+ *  0b1..Allow input trigger_enable=1 action to take effect
+ */
+#define CTIMER_TCR_ATCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+/*! TCVAL - Timer counter value. */
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale Register */
+/*! @{ */
+
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+/*! PRVAL - Prescale reload value. */
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter. */
+/*! @{ */
+
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+/*! PCVAL - Prescale counter value */
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control Register */
+/*! @{ */
+
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+/*! MR0I - Interrupt on MR0
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+/*! MR0R - Reset on MR0
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+/*! MR0S - Stop on MR0
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+/*! MR1I - Interrupt on MR1
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+/*! MR1R - Reset on MR1
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+/*! MR1S - Stop on MR1
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+/*! MR2I - Interrupt on MR2
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+/*! MR2R - Reset on MR2
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+/*! MR2S - Stop on MR2
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+/*! MR3I - Interrupt on MR3
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+/*! MR3R - Reset on MR3
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+/*! MR3S - Stop on MR3
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+/*! MR0RL - Reload MR0
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+/*! MR1RL - Reload MR1
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+/*! MR2RL - Reload MR2
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+/*! MR3RL - Reload MR3
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match Register */
+/*! @{ */
+
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+/*! MATCH - Timer counter match value */
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register */
+/*! @{ */
+
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture Register */
+/*! @{ */
+
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+/*! CAP - Timer counter capture value. */
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register */
+/*! @{ */
+
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+/*! EM0 - External Match 0 */
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+/*! EM1 - External Match 1 */
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+/*! EM2 - External Match 2 */
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+/*! EM3 - External Match 3 */
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+/*! EMC0 - External Match Control 0
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+/*! EMC1 - External Match Control 1
+ *  0b00..Do Nothing
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+/*! EMC2 - External Match Control 2
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+/*! EMC3 - External Match Control 3
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control Register */
+/*! @{ */
+
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+/*! CTMODE - The Count Control Register (CTCR) is used to select between Timer and Counter mode, and
+ *    in Counter mode to select the pin and edge(s) for counting.
+ *  0b00..Timer Mode
+ *  0b01..Counter Mode rising edge
+ *  0b10..Counter Mode falling edge
+ *  0b11..Counter Mode dual edge
+ */
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+/*! CINSEL - Count Input Select
+ *  0b00..Channel 0. CAPn.0 for CTIMERn
+ *  0b01..Channel 1. CAPn.1 for CTIMERn
+ *  0b10..Channel 2. CAPn.2 for CTIMERn
+ *  0b11..Channel 3. CAPn.3 for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+/*! SELCC - Edge select
+ *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ */
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control Register */
+/*! @{ */
+
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+/*! PWMEN0 - PWM mode enable for channel0.
+ *  0b0..Match. CTIMERn_MAT0 is controlled by EM0.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
+ */
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+/*! PWMEN1 - PWM mode enable for channel1.
+ *  0b0..Match. CTIMERn_MAT01 is controlled by EM1.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
+ */
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+/*! PWMEN2 - PWM mode enable for channel2.
+ *  0b0..Match. CTIMERn_MAT2 is controlled by EM2.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
+ */
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
+ *  0b0..Match. CTIMERn_MAT3 is controlled by EM3.
+ *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
+ */
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow Register */
+/*! @{ */
+
+#define CTIMER_MSR_MATCH_SHADOW_MASK             (0xFFFFFFFFU)
+#define CTIMER_MSR_MATCH_SHADOW_SHIFT            (0U)
+/*! MATCH_SHADOW - Timer counter match shadow value. */
+#define CTIMER_MSR_MATCH_SHADOW(x)               (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
+/*! @} */
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral CTIMER0 base address */
+  #define CTIMER0_BASE                             (0x50028000u)
+  /** Peripheral CTIMER0 base address */
+  #define CTIMER0_BASE_NS                          (0x40028000u)
+  /** Peripheral CTIMER0 base pointer */
+  #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+  /** Peripheral CTIMER0 base pointer */
+  #define CTIMER0_NS                               ((CTIMER_Type *)CTIMER0_BASE_NS)
+  /** Peripheral CTIMER1 base address */
+  #define CTIMER1_BASE                             (0x50029000u)
+  /** Peripheral CTIMER1 base address */
+  #define CTIMER1_BASE_NS                          (0x40029000u)
+  /** Peripheral CTIMER1 base pointer */
+  #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+  /** Peripheral CTIMER1 base pointer */
+  #define CTIMER1_NS                               ((CTIMER_Type *)CTIMER1_BASE_NS)
+  /** Peripheral CTIMER2 base address */
+  #define CTIMER2_BASE                             (0x5002A000u)
+  /** Peripheral CTIMER2 base address */
+  #define CTIMER2_BASE_NS                          (0x4002A000u)
+  /** Peripheral CTIMER2 base pointer */
+  #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+  /** Peripheral CTIMER2 base pointer */
+  #define CTIMER2_NS                               ((CTIMER_Type *)CTIMER2_BASE_NS)
+  /** Peripheral CTIMER3 base address */
+  #define CTIMER3_BASE                             (0x5002B000u)
+  /** Peripheral CTIMER3 base address */
+  #define CTIMER3_BASE_NS                          (0x4002B000u)
+  /** Peripheral CTIMER3 base pointer */
+  #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+  /** Peripheral CTIMER3 base pointer */
+  #define CTIMER3_NS                               ((CTIMER_Type *)CTIMER3_BASE_NS)
+  /** Array initializer of CTIMER peripheral base addresses */
+  #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE }
+  /** Array initializer of CTIMER peripheral base pointers */
+  #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3 }
+  /** Array initializer of CTIMER peripheral base addresses */
+  #define CTIMER_BASE_ADDRS_NS                     { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS }
+  /** Array initializer of CTIMER peripheral base pointers */
+  #define CTIMER_BASE_PTRS_NS                      { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS }
+#else
+  /** Peripheral CTIMER0 base address */
+  #define CTIMER0_BASE                             (0x40028000u)
+  /** Peripheral CTIMER0 base pointer */
+  #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+  /** Peripheral CTIMER1 base address */
+  #define CTIMER1_BASE                             (0x40029000u)
+  /** Peripheral CTIMER1 base pointer */
+  #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+  /** Peripheral CTIMER2 base address */
+  #define CTIMER2_BASE                             (0x4002A000u)
+  /** Peripheral CTIMER2 base pointer */
+  #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+  /** Peripheral CTIMER3 base address */
+  #define CTIMER3_BASE                             (0x4002B000u)
+  /** Peripheral CTIMER3 base pointer */
+  #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+  /** Array initializer of CTIMER peripheral base addresses */
+  #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE }
+  /** Array initializer of CTIMER peripheral base pointers */
+  #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3 }
+#endif
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DAC Control Register, offset: 0x0 */
+  __I  uint32_t STATUS;                            /**< DAC Status Register, offset: 0x4 */
+  __IO uint32_t ACTRL;                             /**< Channel A Control Register, offset: 0x8 */
+  __IO uint32_t BCTRL;                             /**< Channel B Control Register, offset: 0xC */
+  __IO uint32_t ADATA;                             /**< Channel A Data Register, offset: 0x10 */
+  __IO uint32_t BDATA;                             /**< Channel B Data Register, offset: 0x14 */
+  __I  uint32_t ISR;                               /**< Interrupt Status Register, offset: 0x18 */
+  __IO uint32_t IMR;                               /**< Interrupt Mask Register, offset: 0x1C */
+  __I  uint32_t IRSR;                              /**< Interrupt Raw Status Register, offset: 0x20 */
+  __IO uint32_t ICR;                               /**< Interrupt Clear Register, offset: 0x24 */
+  __IO uint32_t CLK;                               /**< Clock Register, offset: 0x28 */
+  __IO uint32_t RST;                               /**< Soft Reset Register, offset: 0x2C */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DAC Control Register */
+/*! @{ */
+
+#define DAC_CTRL_REF_SEL_MASK                    (0x1U)
+#define DAC_CTRL_REF_SEL_SHIFT                   (0U)
+/*! REF_SEL - Reference selector
+ *  0b0..internal reference
+ *  0b1..external reference
+ */
+#define DAC_CTRL_REF_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_REF_SEL_SHIFT)) & DAC_CTRL_REF_SEL_MASK)
+/*! @} */
+
+/*! @name STATUS - DAC Status Register */
+/*! @{ */
+
+#define DAC_STATUS_A_DV_MASK                     (0x1U)
+#define DAC_STATUS_A_DV_SHIFT                    (0U)
+/*! A_DV - DACA conversion status.
+ *  0b0..channel A conversion is not done
+ *  0b1..channel A conversion complete
+ */
+#define DAC_STATUS_A_DV(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_STATUS_A_DV_SHIFT)) & DAC_STATUS_A_DV_MASK)
+
+#define DAC_STATUS_B_DV_MASK                     (0x2U)
+#define DAC_STATUS_B_DV_SHIFT                    (1U)
+/*! B_DV - DACB conversion status
+ *  0b0..channel B conversion is not done
+ *  0b1..channel B conversion complete
+ */
+#define DAC_STATUS_B_DV(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_STATUS_B_DV_SHIFT)) & DAC_STATUS_B_DV_MASK)
+/*! @} */
+
+/*! @name ACTRL - Channel A Control Register */
+/*! @{ */
+
+#define DAC_ACTRL_A_EN_MASK                      (0x1U)
+#define DAC_ACTRL_A_EN_SHIFT                     (0U)
+/*! A_EN - Channel A Enable/Disable signal
+ *  0b0..disable channel A conversion
+ *  0b1..enable channel A conversion
+ */
+#define DAC_ACTRL_A_EN(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_EN_SHIFT)) & DAC_ACTRL_A_EN_MASK)
+
+#define DAC_ACTRL_A_IO_EN_MASK                   (0x2U)
+#define DAC_ACTRL_A_IO_EN_SHIFT                  (1U)
+/*! A_IO_EN - Channel A conversion output to pad enable
+ *  0b0..disable channel A conversion result to GPIO
+ *  0b1..enable channel A conversion result to GPIO
+ */
+#define DAC_ACTRL_A_IO_EN(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_IO_EN_SHIFT)) & DAC_ACTRL_A_IO_EN_MASK)
+
+#define DAC_ACTRL_A_TRIG_EN_MASK                 (0x4U)
+#define DAC_ACTRL_A_TRIG_EN_SHIFT                (2U)
+/*! A_TRIG_EN - Channel A trigger enable
+ *  0b0..Channel A conversion triggered by external event disabled
+ *  0b1..Channel A conversion triggered by external event enabled
+ */
+#define DAC_ACTRL_A_TRIG_EN(x)                   (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIG_EN_SHIFT)) & DAC_ACTRL_A_TRIG_EN_MASK)
+
+#define DAC_ACTRL_A_TRIG_SEL_MASK                (0x18U)
+#define DAC_ACTRL_A_TRIG_SEL_SHIFT               (3U)
+/*! A_TRIG_SEL - Channel A trigger selector
+ *  0b00..ctimer1 match2
+ *  0b01..ctimer1 match1
+ *  0b10..GPIO50
+ *  0b11..GPIO55
+ */
+#define DAC_ACTRL_A_TRIG_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIG_SEL_SHIFT)) & DAC_ACTRL_A_TRIG_SEL_MASK)
+
+#define DAC_ACTRL_A_TRIG_TYP_MASK                (0x60U)
+#define DAC_ACTRL_A_TRIG_TYP_SHIFT               (5U)
+/*! A_TRIG_TYP - Channel A trigger type
+ *  0b00..reserved
+ *  0b01..rising edge trigger
+ *  0b10..falling edge trigger
+ *  0b11..both rising and falling edge trigger
+ */
+#define DAC_ACTRL_A_TRIG_TYP(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIG_TYP_SHIFT)) & DAC_ACTRL_A_TRIG_TYP_MASK)
+
+#define DAC_ACTRL_A_DEN_MASK                     (0x80U)
+#define DAC_ACTRL_A_DEN_SHIFT                    (7U)
+/*! A_DEN - Channel A DMA enable
+ *  0b0..DMA data transfer disabled
+ *  0b1..DMA data transfer enabled
+ */
+#define DAC_ACTRL_A_DEN(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_DEN_SHIFT)) & DAC_ACTRL_A_DEN_MASK)
+
+#define DAC_ACTRL_A_TIME_MODE_MASK               (0x100U)
+#define DAC_ACTRL_A_TIME_MODE_SHIFT              (8U)
+/*! A_TIME_MODE - Channel A Mode
+ *  0b0..non-timing related
+ *  0b1..timing related
+ */
+#define DAC_ACTRL_A_TIME_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TIME_MODE_SHIFT)) & DAC_ACTRL_A_TIME_MODE_MASK)
+
+#define DAC_ACTRL_A_TRIA_HALF_MASK               (0x200U)
+#define DAC_ACTRL_A_TRIA_HALF_SHIFT              (9U)
+/*! A_TRIA_HALF - Channel A triangle wave type selector.
+ *  0b0..full triangle
+ *  0b1..half triangle
+ */
+#define DAC_ACTRL_A_TRIA_HALF(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIA_HALF_SHIFT)) & DAC_ACTRL_A_TRIA_HALF_MASK)
+
+#define DAC_ACTRL_A_TRIA_MAMP_SEL_MASK           (0x3C00U)
+#define DAC_ACTRL_A_TRIA_MAMP_SEL_SHIFT          (10U)
+/*! A_TRIA_MAMP_SEL - Channel A triangle wave max amplitude selector.
+ *  0b0000..63
+ *  0b0001..127
+ *  0b0010..191
+ *  0b0011..255
+ *  0b0100..319
+ *  0b0101..383
+ *  0b0110..447
+ *  0b0111..511
+ *  0b1000..575
+ *  0b1001..639
+ *  0b1010..703
+ *  0b1011..767
+ *  0b1100..831
+ *  0b1101..895
+ *  0b1110..959
+ *  0b1111..1023
+ */
+#define DAC_ACTRL_A_TRIA_MAMP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIA_MAMP_SEL_SHIFT)) & DAC_ACTRL_A_TRIA_MAMP_SEL_MASK)
+
+#define DAC_ACTRL_A_TRIA_STEP_SEL_MASK           (0xC000U)
+#define DAC_ACTRL_A_TRIA_STEP_SEL_SHIFT          (14U)
+/*! A_TRIA_STEP_SEL - Channel A triangle wave step selector.
+ *  0b00..1
+ *  0b01..3
+ *  0b10..15
+ *  0b11..511
+ */
+#define DAC_ACTRL_A_TRIA_STEP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIA_STEP_SEL_SHIFT)) & DAC_ACTRL_A_TRIA_STEP_SEL_MASK)
+
+#define DAC_ACTRL_A_WAVE_MASK                    (0x30000U)
+#define DAC_ACTRL_A_WAVE_SHIFT                   (16U)
+/*! A_WAVE - Channel A wave type select.
+ *  0b00..
+ *  0b01..triangle wave
+ *  0b11..
+ *  0b10..sine wave
+ */
+#define DAC_ACTRL_A_WAVE(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_WAVE_SHIFT)) & DAC_ACTRL_A_WAVE_MASK)
+
+#define DAC_ACTRL_A_RANGE_MASK                   (0xC0000U)
+#define DAC_ACTRL_A_RANGE_SHIFT                  (18U)
+/*! A_RANGE - Output voltage range control, with Internal/External reference
+ *  0b00..0.16+(0.64*input code/1023) with ref_sel=0(internal)/0.08* Vref_ext+(0.32* Vref_ext*input_code/1023) with ref_sel=1(external)
+ *  0b01..0.19+(1.01*input code /1023) with ref_sel=0(internal)/0.095* Vref_ext+(0.505* Vref_ext*input_code/1023) with ref_sel=1(external)
+ *  0b10..0.19+(1.01*input code /1023) with ref_sel=0(internal)/0.095* Vref_ext+(0.505* Vref_ext*input_code/1023) with ref_sel=1(external)
+ *  0b11..0.18+(1.42*input code /1023) with ref_sel=0(internal)/0.09*Vref_ext+(0.71* Vref_ext*input_code/1023) with ref_sel=1(external)
+ */
+#define DAC_ACTRL_A_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_RANGE_SHIFT)) & DAC_ACTRL_A_RANGE_MASK)
+/*! @} */
+
+/*! @name BCTRL - Channel B Control Register */
+/*! @{ */
+
+#define DAC_BCTRL_B_EN_MASK                      (0x1U)
+#define DAC_BCTRL_B_EN_SHIFT                     (0U)
+/*! B_EN - Channel B Enable/Disable signal
+ *  0b0..disable channel B conversion
+ *  0b1..enable channel B conversion
+ */
+#define DAC_BCTRL_B_EN(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_EN_SHIFT)) & DAC_BCTRL_B_EN_MASK)
+
+#define DAC_BCTRL_B_IO_EN_MASK                   (0x2U)
+#define DAC_BCTRL_B_IO_EN_SHIFT                  (1U)
+/*! B_IO_EN - Channel B conversion output to pad enable
+ *  0b0..disable channel B conversion result to GPIO
+ *  0b1..enable channel B conversion result to GPIO
+ */
+#define DAC_BCTRL_B_IO_EN(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_IO_EN_SHIFT)) & DAC_BCTRL_B_IO_EN_MASK)
+
+#define DAC_BCTRL_B_TRIG_EN_MASK                 (0x4U)
+#define DAC_BCTRL_B_TRIG_EN_SHIFT                (2U)
+/*! B_TRIG_EN - Channel B trigger enable
+ *  0b0..Channel B conversion triggered by external event disabled
+ *  0b1..Channel B conversion triggered by external event enabled
+ */
+#define DAC_BCTRL_B_TRIG_EN(x)                   (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TRIG_EN_SHIFT)) & DAC_BCTRL_B_TRIG_EN_MASK)
+
+#define DAC_BCTRL_B_TRIG_SEL_MASK                (0x18U)
+#define DAC_BCTRL_B_TRIG_SEL_SHIFT               (3U)
+/*! B_TRIG_SEL - Channel B trigger selector
+ *  0b00..ctimer1 match2
+ *  0b01..ctimer1 match1
+ *  0b10..GPIO50
+ *  0b11..GPIO55
+ */
+#define DAC_BCTRL_B_TRIG_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TRIG_SEL_SHIFT)) & DAC_BCTRL_B_TRIG_SEL_MASK)
+
+#define DAC_BCTRL_B_TRIG_TYP_MASK                (0x60U)
+#define DAC_BCTRL_B_TRIG_TYP_SHIFT               (5U)
+/*! B_TRIG_TYP - Channel B trigger type
+ *  0b00..reserved
+ *  0b01..rising edge trigger
+ *  0b10..falling edge trigger
+ *  0b11..both rising and falling edge trigger
+ */
+#define DAC_BCTRL_B_TRIG_TYP(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TRIG_TYP_SHIFT)) & DAC_BCTRL_B_TRIG_TYP_MASK)
+
+#define DAC_BCTRL_B_DEN_MASK                     (0x80U)
+#define DAC_BCTRL_B_DEN_SHIFT                    (7U)
+/*! B_DEN - Channel B DMA enable
+ *  0b0..DMA data transfer disabled
+ *  0b1..DMA data transfer enabled
+ */
+#define DAC_BCTRL_B_DEN(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_DEN_SHIFT)) & DAC_BCTRL_B_DEN_MASK)
+
+#define DAC_BCTRL_B_TIME_MODE_MASK               (0x100U)
+#define DAC_BCTRL_B_TIME_MODE_SHIFT              (8U)
+/*! B_TIME_MODE - Channel B Mode
+ *  0b0..non-timing related
+ *  0b1..timing related
+ */
+#define DAC_BCTRL_B_TIME_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TIME_MODE_SHIFT)) & DAC_BCTRL_B_TIME_MODE_MASK)
+
+#define DAC_BCTRL_B_WAVE_MASK                    (0x600U)
+#define DAC_BCTRL_B_WAVE_SHIFT                   (9U)
+/*! B_WAVE - Channel B wave type select.
+ *  0b00..
+ *  0b01..reserved
+ *  0b10..reserved
+ *  0b11..differential mode with channel A
+ */
+#define DAC_BCTRL_B_WAVE(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_WAVE_SHIFT)) & DAC_BCTRL_B_WAVE_MASK)
+/*! @} */
+
+/*! @name ADATA - Channel A Data Register */
+/*! @{ */
+
+#define DAC_ADATA_A_DATA_MASK                    (0x3FFU)
+#define DAC_ADATA_A_DATA_SHIFT                   (0U)
+/*! A_DATA - Channel A Data input */
+#define DAC_ADATA_A_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_ADATA_A_DATA_SHIFT)) & DAC_ADATA_A_DATA_MASK)
+/*! @} */
+
+/*! @name BDATA - Channel B Data Register */
+/*! @{ */
+
+#define DAC_BDATA_B_DATA_MASK                    (0x3FFU)
+#define DAC_BDATA_B_DATA_SHIFT                   (0U)
+/*! B_DATA - Channel B Data input */
+#define DAC_BDATA_B_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_BDATA_B_DATA_SHIFT)) & DAC_BDATA_B_DATA_MASK)
+/*! @} */
+
+/*! @name ISR - Interrupt Status Register */
+/*! @{ */
+
+#define DAC_ISR_A_RDY_INT_MASK                   (0x1U)
+#define DAC_ISR_A_RDY_INT_SHIFT                  (0U)
+/*! A_RDY_INT - Channel A Data Ready */
+#define DAC_ISR_A_RDY_INT(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_ISR_A_RDY_INT_SHIFT)) & DAC_ISR_A_RDY_INT_MASK)
+
+#define DAC_ISR_B_RDY_INT_MASK                   (0x2U)
+#define DAC_ISR_B_RDY_INT_SHIFT                  (1U)
+/*! B_RDY_INT - Channel B Data Ready */
+#define DAC_ISR_B_RDY_INT(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_ISR_B_RDY_INT_SHIFT)) & DAC_ISR_B_RDY_INT_MASK)
+
+#define DAC_ISR_A_TO_INT_MASK                    (0x4U)
+#define DAC_ISR_A_TO_INT_SHIFT                   (2U)
+/*! A_TO_INT - Channel A Timeout */
+#define DAC_ISR_A_TO_INT(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_ISR_A_TO_INT_SHIFT)) & DAC_ISR_A_TO_INT_MASK)
+
+#define DAC_ISR_B_TO_INT_MASK                    (0x8U)
+#define DAC_ISR_B_TO_INT_SHIFT                   (3U)
+/*! B_TO_INT - Channel B Timeout */
+#define DAC_ISR_B_TO_INT(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_ISR_B_TO_INT_SHIFT)) & DAC_ISR_B_TO_INT_MASK)
+
+#define DAC_ISR_TRIA_OVFL_INT_MASK               (0x10U)
+#define DAC_ISR_TRIA_OVFL_INT_SHIFT              (4U)
+/*! TRIA_OVFL_INT - Triangle Overflow */
+#define DAC_ISR_TRIA_OVFL_INT(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_ISR_TRIA_OVFL_INT_SHIFT)) & DAC_ISR_TRIA_OVFL_INT_MASK)
+/*! @} */
+
+/*! @name IMR - Interrupt Mask Register */
+/*! @{ */
+
+#define DAC_IMR_A_RDY_INT_MSK_MASK               (0x1U)
+#define DAC_IMR_A_RDY_INT_MSK_SHIFT              (0U)
+/*! A_RDY_INT_MSK - Channel A Data Ready Mask */
+#define DAC_IMR_A_RDY_INT_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_IMR_A_RDY_INT_MSK_SHIFT)) & DAC_IMR_A_RDY_INT_MSK_MASK)
+
+#define DAC_IMR_B_RDY_INT_MSK_MASK               (0x2U)
+#define DAC_IMR_B_RDY_INT_MSK_SHIFT              (1U)
+/*! B_RDY_INT_MSK - Channel B Data Ready Mask */
+#define DAC_IMR_B_RDY_INT_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_IMR_B_RDY_INT_MSK_SHIFT)) & DAC_IMR_B_RDY_INT_MSK_MASK)
+
+#define DAC_IMR_A_TO_INT_MSK_MASK                (0x4U)
+#define DAC_IMR_A_TO_INT_MSK_SHIFT               (2U)
+/*! A_TO_INT_MSK - Channel A Timeout Mask */
+#define DAC_IMR_A_TO_INT_MSK(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_IMR_A_TO_INT_MSK_SHIFT)) & DAC_IMR_A_TO_INT_MSK_MASK)
+
+#define DAC_IMR_B_TO_INT_MSK_MASK                (0x8U)
+#define DAC_IMR_B_TO_INT_MSK_SHIFT               (3U)
+/*! B_TO_INT_MSK - Channel B Timeout Mask */
+#define DAC_IMR_B_TO_INT_MSK(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_IMR_B_TO_INT_MSK_SHIFT)) & DAC_IMR_B_TO_INT_MSK_MASK)
+
+#define DAC_IMR_TRIA_OVFL_INT_MSK_MASK           (0x10U)
+#define DAC_IMR_TRIA_OVFL_INT_MSK_SHIFT          (4U)
+/*! TRIA_OVFL_INT_MSK - Triangle Overflow Mask */
+#define DAC_IMR_TRIA_OVFL_INT_MSK(x)             (((uint32_t)(((uint32_t)(x)) << DAC_IMR_TRIA_OVFL_INT_MSK_SHIFT)) & DAC_IMR_TRIA_OVFL_INT_MSK_MASK)
+/*! @} */
+
+/*! @name IRSR - Interrupt Raw Status Register */
+/*! @{ */
+
+#define DAC_IRSR_A_RDY_INT_RAW_MASK              (0x1U)
+#define DAC_IRSR_A_RDY_INT_RAW_SHIFT             (0U)
+/*! A_RDY_INT_RAW - Channel A Data Ready Raw */
+#define DAC_IRSR_A_RDY_INT_RAW(x)                (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_A_RDY_INT_RAW_SHIFT)) & DAC_IRSR_A_RDY_INT_RAW_MASK)
+
+#define DAC_IRSR_B_RDY_INT_RAW_MASK              (0x2U)
+#define DAC_IRSR_B_RDY_INT_RAW_SHIFT             (1U)
+/*! B_RDY_INT_RAW - Channel B Data Ready Raw */
+#define DAC_IRSR_B_RDY_INT_RAW(x)                (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_B_RDY_INT_RAW_SHIFT)) & DAC_IRSR_B_RDY_INT_RAW_MASK)
+
+#define DAC_IRSR_A_TO_INT_RAW_MASK               (0x4U)
+#define DAC_IRSR_A_TO_INT_RAW_SHIFT              (2U)
+/*! A_TO_INT_RAW - Channel A Timeout Raw */
+#define DAC_IRSR_A_TO_INT_RAW(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_A_TO_INT_RAW_SHIFT)) & DAC_IRSR_A_TO_INT_RAW_MASK)
+
+#define DAC_IRSR_B_TO_INT_RAW_MASK               (0x8U)
+#define DAC_IRSR_B_TO_INT_RAW_SHIFT              (3U)
+/*! B_TO_INT_RAW - Channel B Timeout Raw */
+#define DAC_IRSR_B_TO_INT_RAW(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_B_TO_INT_RAW_SHIFT)) & DAC_IRSR_B_TO_INT_RAW_MASK)
+
+#define DAC_IRSR_TRIA_OVFL_INT_RAW_MASK          (0x10U)
+#define DAC_IRSR_TRIA_OVFL_INT_RAW_SHIFT         (4U)
+/*! TRIA_OVFL_INT_RAW - Triangle Overflow Raw */
+#define DAC_IRSR_TRIA_OVFL_INT_RAW(x)            (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_TRIA_OVFL_INT_RAW_SHIFT)) & DAC_IRSR_TRIA_OVFL_INT_RAW_MASK)
+/*! @} */
+
+/*! @name ICR - Interrupt Clear Register */
+/*! @{ */
+
+#define DAC_ICR_A_RDY_INT_CLR_MASK               (0x1U)
+#define DAC_ICR_A_RDY_INT_CLR_SHIFT              (0U)
+/*! A_RDY_INT_CLR - Channel A Data Ready Clear */
+#define DAC_ICR_A_RDY_INT_CLR(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_ICR_A_RDY_INT_CLR_SHIFT)) & DAC_ICR_A_RDY_INT_CLR_MASK)
+
+#define DAC_ICR_B_RDY_INT_CLR_MASK               (0x2U)
+#define DAC_ICR_B_RDY_INT_CLR_SHIFT              (1U)
+/*! B_RDY_INT_CLR - Channel B Data Ready Clear */
+#define DAC_ICR_B_RDY_INT_CLR(x)                 (((uint32_t)(((uint32_t)(x)) << DAC_ICR_B_RDY_INT_CLR_SHIFT)) & DAC_ICR_B_RDY_INT_CLR_MASK)
+
+#define DAC_ICR_A_TO_INT_CLR_MASK                (0x4U)
+#define DAC_ICR_A_TO_INT_CLR_SHIFT               (2U)
+/*! A_TO_INT_CLR - Channel A Timeout Clear */
+#define DAC_ICR_A_TO_INT_CLR(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_ICR_A_TO_INT_CLR_SHIFT)) & DAC_ICR_A_TO_INT_CLR_MASK)
+
+#define DAC_ICR_B_TO_INT_CLR_MASK                (0x8U)
+#define DAC_ICR_B_TO_INT_CLR_SHIFT               (3U)
+/*! B_TO_INT_CLR - Channel B Timeout Clear */
+#define DAC_ICR_B_TO_INT_CLR(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_ICR_B_TO_INT_CLR_SHIFT)) & DAC_ICR_B_TO_INT_CLR_MASK)
+
+#define DAC_ICR_TRIA_OVFL_INT_CLR_MASK           (0x10U)
+#define DAC_ICR_TRIA_OVFL_INT_CLR_SHIFT          (4U)
+/*! TRIA_OVFL_INT_CLR - Triangle Overflow Clear */
+#define DAC_ICR_TRIA_OVFL_INT_CLR(x)             (((uint32_t)(((uint32_t)(x)) << DAC_ICR_TRIA_OVFL_INT_CLR_SHIFT)) & DAC_ICR_TRIA_OVFL_INT_CLR_MASK)
+/*! @} */
+
+/*! @name CLK - Clock Register */
+/*! @{ */
+
+#define DAC_CLK_CLK_CTRL_MASK                    (0x6U)
+#define DAC_CLK_CLK_CTRL_SHIFT                   (1U)
+/*! CLK_CTRL - DAC conversion rate selector.
+ *  0b00..62.5K
+ *  0b01..125K
+ *  0b10..250K
+ *  0b11..500K
+ */
+#define DAC_CLK_CLK_CTRL(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_CLK_CLK_CTRL_SHIFT)) & DAC_CLK_CLK_CTRL_MASK)
+
+#define DAC_CLK_SOFT_CLK_RST_MASK                (0x10U)
+#define DAC_CLK_SOFT_CLK_RST_SHIFT               (4U)
+/*! SOFT_CLK_RST - Soft reset for clock divider
+ *  0b0..
+ *  0b1..
+ */
+#define DAC_CLK_SOFT_CLK_RST(x)                  (((uint32_t)(((uint32_t)(x)) << DAC_CLK_SOFT_CLK_RST_SHIFT)) & DAC_CLK_SOFT_CLK_RST_MASK)
+/*! @} */
+
+/*! @name RST - Soft Reset Register */
+/*! @{ */
+
+#define DAC_RST_A_SOFT_RST_MASK                  (0x1U)
+#define DAC_RST_A_SOFT_RST_SHIFT                 (0U)
+/*! A_SOFT_RST - Soft reset for DAC channel A, active high
+ *  0b0..no action
+ *  0b1..
+ */
+#define DAC_RST_A_SOFT_RST(x)                    (((uint32_t)(((uint32_t)(x)) << DAC_RST_A_SOFT_RST_SHIFT)) & DAC_RST_A_SOFT_RST_MASK)
+
+#define DAC_RST_B_SOFT_RST_MASK                  (0x2U)
+#define DAC_RST_B_SOFT_RST_SHIFT                 (1U)
+/*! B_SOFT_RST - Soft reset for DAC channel B, active high
+ *  0b0..no action
+ *  0b1..
+ */
+#define DAC_RST_B_SOFT_RST(x)                    (((uint32_t)(((uint32_t)(x)) << DAC_RST_B_SOFT_RST_SHIFT)) & DAC_RST_B_SOFT_RST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral GAU_DAC0 base address */
+  #define GAU_DAC0_BASE                            (0x50038200u)
+  /** Peripheral GAU_DAC0 base address */
+  #define GAU_DAC0_BASE_NS                         (0x40038200u)
+  /** Peripheral GAU_DAC0 base pointer */
+  #define GAU_DAC0                                 ((DAC_Type *)GAU_DAC0_BASE)
+  /** Peripheral GAU_DAC0 base pointer */
+  #define GAU_DAC0_NS                              ((DAC_Type *)GAU_DAC0_BASE_NS)
+  /** Array initializer of DAC peripheral base addresses */
+  #define DAC_BASE_ADDRS                           { GAU_DAC0_BASE }
+  /** Array initializer of DAC peripheral base pointers */
+  #define DAC_BASE_PTRS                            { GAU_DAC0 }
+  /** Array initializer of DAC peripheral base addresses */
+  #define DAC_BASE_ADDRS_NS                        { GAU_DAC0_BASE_NS }
+  /** Array initializer of DAC peripheral base pointers */
+  #define DAC_BASE_PTRS_NS                         { GAU_DAC0_NS }
+#else
+  /** Peripheral GAU_DAC0 base address */
+  #define GAU_DAC0_BASE                            (0x40038200u)
+  /** Peripheral GAU_DAC0 base pointer */
+  #define GAU_DAC0                                 ((DAC_Type *)GAU_DAC0_BASE)
+  /** Array initializer of DAC peripheral base addresses */
+  #define DAC_BASE_ADDRS                           { GAU_DAC0_BASE }
+  /** Array initializer of DAC peripheral base pointers */
+  #define DAC_BASE_PTRS                            { GAU_DAC0 }
+#endif
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { GAU_DAC_IRQn }
+/* Backward compatibility */
+#define kDAC_GPT2Trigger                         kDAC_TriggerSourceCtimer1Match2
+#define kDAC_GPT3Trigger                         kDAC_TriggerSourceCtimer1Match1
+#define kDAC_GPIO45Trigger                       kDAC_TriggerSourceGpio50
+#define kDAC_GPIO44Trigger                       kDAC_TriggerSourceGpio55
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DBGMAILBOX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer
+ * @{
+ */
+
+/** DBGMAILBOX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSW;                               /**< Command and status word, offset: 0x0 */
+  __IO uint32_t REQUEST;                           /**< Request Value, offset: 0x4 */
+  __IO uint32_t RETURN;                            /**< Return Value, offset: 0x8 */
+       uint8_t RESERVED_0[240];
+  __I  uint32_t ID;                                /**< Identification, offset: 0xFC */
+} DBGMAILBOX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DBGMAILBOX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks
+ * @{
+ */
+
+/*! @name CSW - Command and status word */
+/*! @{ */
+
+#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK          (0x1U)
+#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT         (0U)
+/*! RESYNCH_REQ - Re-synchronization Request
+ *  0b0..No Request
+ *  0b1..Request for re-synchronization
+ */
+#define DBGMAILBOX_CSW_RESYNCH_REQ(x)            (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK)
+
+#define DBGMAILBOX_CSW_REQ_PENDING_MASK          (0x2U)
+#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT         (1U)
+/*! REQ_PENDING - Request Pending
+ *  0b0..No Request Pending
+ *  0b1..Request for Re-synchronization Pending
+ */
+#define DBGMAILBOX_CSW_REQ_PENDING(x)            (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK)
+
+#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK           (0x4U)
+#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT          (2U)
+/*! DBG_OR_ERR - Debug Overrun Error
+ *  0b0..No Debug Overrun error
+ *  0b1..Debug Overrun Error. A debug overrun occurred.
+ */
+#define DBGMAILBOX_CSW_DBG_OR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
+
+#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK           (0x8U)
+#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT          (3U)
+/*! AHB_OR_ERR - AHB Overrun Error
+ *  0b0..No AHB Overrun Error
+ *  0b1..AHB Overrun Error. An AHB overrun occurred.
+ */
+#define DBGMAILBOX_CSW_AHB_OR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
+
+#define DBGMAILBOX_CSW_SOFT_RESET_MASK           (0x10U)
+#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT          (4U)
+/*! SOFT_RESET - Soft Reset */
+#define DBGMAILBOX_CSW_SOFT_RESET(x)             (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK)
+
+#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK       (0x20U)
+#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT      (5U)
+/*! CHIP_RESET_REQ - Chip Reset Request */
+#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x)         (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK)
+/*! @} */
+
+/*! @name REQUEST - Request Value */
+/*! @{ */
+
+#define DBGMAILBOX_REQUEST_REQUEST_MASK          (0xFFFFFFFFU)
+#define DBGMAILBOX_REQUEST_REQUEST_SHIFT         (0U)
+/*! REQUEST - Request Value */
+#define DBGMAILBOX_REQUEST_REQUEST(x)            (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQUEST_SHIFT)) & DBGMAILBOX_REQUEST_REQUEST_MASK)
+/*! @} */
+
+/*! @name RETURN - Return Value */
+/*! @{ */
+
+#define DBGMAILBOX_RETURN_RET_MASK               (0xFFFFFFFFU)
+#define DBGMAILBOX_RETURN_RET_SHIFT              (0U)
+/*! RET - Return Value */
+#define DBGMAILBOX_RETURN_RET(x)                 (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK)
+/*! @} */
+
+/*! @name ID - Identification */
+/*! @{ */
+
+#define DBGMAILBOX_ID_ID_MASK                    (0xFFFFFFFFU)
+#define DBGMAILBOX_ID_ID_SHIFT                   (0U)
+/*! ID - Identification Value */
+#define DBGMAILBOX_ID_ID(x)                      (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DBGMAILBOX_Register_Masks */
+
+
+/* DBGMAILBOX - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral DBGMAILBOX base address */
+  #define DBGMAILBOX_BASE                          (0x5010F000u)
+  /** Peripheral DBGMAILBOX base address */
+  #define DBGMAILBOX_BASE_NS                       (0x4010F000u)
+  /** Peripheral DBGMAILBOX base pointer */
+  #define DBGMAILBOX                               ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
+  /** Peripheral DBGMAILBOX base pointer */
+  #define DBGMAILBOX_NS                            ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS)
+  /** Array initializer of DBGMAILBOX peripheral base addresses */
+  #define DBGMAILBOX_BASE_ADDRS                    { DBGMAILBOX_BASE }
+  /** Array initializer of DBGMAILBOX peripheral base pointers */
+  #define DBGMAILBOX_BASE_PTRS                     { DBGMAILBOX }
+  /** Array initializer of DBGMAILBOX peripheral base addresses */
+  #define DBGMAILBOX_BASE_ADDRS_NS                 { DBGMAILBOX_BASE_NS }
+  /** Array initializer of DBGMAILBOX peripheral base pointers */
+  #define DBGMAILBOX_BASE_PTRS_NS                  { DBGMAILBOX_NS }
+#else
+  /** Peripheral DBGMAILBOX base address */
+  #define DBGMAILBOX_BASE                          (0x4010F000u)
+  /** Peripheral DBGMAILBOX base pointer */
+  #define DBGMAILBOX                               ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
+  /** Array initializer of DBGMAILBOX peripheral base addresses */
+  #define DBGMAILBOX_BASE_ADDRS                    { DBGMAILBOX_BASE }
+  /** Array initializer of DBGMAILBOX peripheral base pointers */
+  #define DBGMAILBOX_BASE_PTRS                     { DBGMAILBOX }
+#endif
+
+/*!
+ * @}
+ */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control, offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status, offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table, offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x60 */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and set for all DMA channels, array offset: 0x20, array step: 0x60 */
+    __IO uint32_t ENABLESET1;                        /**< Channel Enable read and set for all DMA channels, array offset: 0x24, array step: 0x60 */
+    __IO uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels, array offset: 0x28, array step: 0x60 */
+    __IO uint32_t ENABLECLR1;                        /**< Channel Enable Clear for all DMA channels, array offset: 0x2C, array step: 0x60 */
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels, array offset: 0x30, array step: 0x60 */
+    __I  uint32_t ACTIVE1;                           /**< Channel Active status for all DMA channels, array offset: 0x34, array step: 0x60 */
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels, array offset: 0x38, array step: 0x60 */
+    __I  uint32_t BUSY1;                             /**< Channel Busy status for all DMA channels, array offset: 0x3C, array step: 0x60 */
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels, array offset: 0x40, array step: 0x60 */
+    __IO uint32_t ERRINT1;                           /**< Error Interrupt status for all DMA channels, array offset: 0x44, array step: 0x60 */
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x48, array step: 0x60 */
+    __IO uint32_t INTENSET1;                         /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x4C, array step: 0x60 */
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels, array offset: 0x50, array step: 0x60 */
+    __O  uint32_t INTENCLR1;                         /**< Interrupt Enable Clear for all DMA channels, array offset: 0x54, array step: 0x60 */
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels, array offset: 0x58, array step: 0x60 */
+    __IO uint32_t INTA1;                             /**< Interrupt A status for all DMA channels, array offset: 0x5C, array step: 0x60 */
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels, array offset: 0x60, array step: 0x60 */
+    __IO uint32_t INTB1;                             /**< Interrupt B status for all DMA channels, array offset: 0x64, array step: 0x60 */
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels, array offset: 0x68, array step: 0x60 */
+    __O  uint32_t SETVALID1;                         /**< Set ValidPending control bits for all DMA channels, array offset: 0x6C, array step: 0x60 */
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels, array offset: 0x70, array step: 0x60 */
+    __O  uint32_t SETTRIG1;                          /**< Set Trigger control bits for all DMA channels, array offset: 0x74, array step: 0x60 */
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels, array offset: 0x78, array step: 0x60 */
+    __O  uint32_t ABORT1;                            /**< Channel Abort control for all DMA channels, array offset: 0x7C, array step: 0x60 */
+  } COMMON[1];
+       uint8_t RESERVED_1[896];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel, array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel, array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel, array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[33];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control */
+/*! @{ */
+
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+/*! ENABLE - DMA controller master enable.
+ *  0b0..DMA controller is disabled.
+ *  0b1..Enabled.
+ */
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status */
+/*! @{ */
+
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
+ *  0b0..No enabled interrupts are pending.
+ *  0b1..At least one enabled interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
+ *  0b0..No error interrupts are pending.
+ *  0b1..At least one error interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+/*! @} */
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table */
+/*! @{ */
+
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+/*! OFFSET - Offset */
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+/*! @} */
+
+/*! @name COMMON_ENABLESET - Channel Enable read and set for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ENABLESET_ENABLE0_MASK        (0x1U)
+#define DMA_COMMON_ENABLESET_ENABLE0_SHIFT       (0U)
+/*! ENABLE0 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE0(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE1_MASK        (0x2U)
+#define DMA_COMMON_ENABLESET_ENABLE1_SHIFT       (1U)
+/*! ENABLE1 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE1(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE1_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE1_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE2_MASK        (0x4U)
+#define DMA_COMMON_ENABLESET_ENABLE2_SHIFT       (2U)
+/*! ENABLE2 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE2(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE2_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE2_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE3_MASK        (0x8U)
+#define DMA_COMMON_ENABLESET_ENABLE3_SHIFT       (3U)
+/*! ENABLE3 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE3(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE3_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE3_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE4_MASK        (0x10U)
+#define DMA_COMMON_ENABLESET_ENABLE4_SHIFT       (4U)
+/*! ENABLE4 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE4(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE4_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE4_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE5_MASK        (0x20U)
+#define DMA_COMMON_ENABLESET_ENABLE5_SHIFT       (5U)
+/*! ENABLE5 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE5(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE5_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE5_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE6_MASK        (0x40U)
+#define DMA_COMMON_ENABLESET_ENABLE6_SHIFT       (6U)
+/*! ENABLE6 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE6(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE6_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE6_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE7_MASK        (0x80U)
+#define DMA_COMMON_ENABLESET_ENABLE7_SHIFT       (7U)
+/*! ENABLE7 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE7(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE7_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE7_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE8_MASK        (0x100U)
+#define DMA_COMMON_ENABLESET_ENABLE8_SHIFT       (8U)
+/*! ENABLE8 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE8(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE8_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE8_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE9_MASK        (0x200U)
+#define DMA_COMMON_ENABLESET_ENABLE9_SHIFT       (9U)
+/*! ENABLE9 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE9(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE9_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE9_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE10_MASK       (0x400U)
+#define DMA_COMMON_ENABLESET_ENABLE10_SHIFT      (10U)
+/*! ENABLE10 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE10(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE10_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE10_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE11_MASK       (0x800U)
+#define DMA_COMMON_ENABLESET_ENABLE11_SHIFT      (11U)
+/*! ENABLE11 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE11(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE11_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE11_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE12_MASK       (0x1000U)
+#define DMA_COMMON_ENABLESET_ENABLE12_SHIFT      (12U)
+/*! ENABLE12 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE12(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE12_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE12_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE13_MASK       (0x2000U)
+#define DMA_COMMON_ENABLESET_ENABLE13_SHIFT      (13U)
+/*! ENABLE13 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE13(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE13_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE13_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE14_MASK       (0x4000U)
+#define DMA_COMMON_ENABLESET_ENABLE14_SHIFT      (14U)
+/*! ENABLE14 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE14(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE14_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE14_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE15_MASK       (0x8000U)
+#define DMA_COMMON_ENABLESET_ENABLE15_SHIFT      (15U)
+/*! ENABLE15 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE15(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE15_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE15_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE16_MASK       (0x10000U)
+#define DMA_COMMON_ENABLESET_ENABLE16_SHIFT      (16U)
+/*! ENABLE16 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE16(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE16_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE16_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE17_MASK       (0x20000U)
+#define DMA_COMMON_ENABLESET_ENABLE17_SHIFT      (17U)
+/*! ENABLE17 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE17(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE17_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE17_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE18_MASK       (0x40000U)
+#define DMA_COMMON_ENABLESET_ENABLE18_SHIFT      (18U)
+/*! ENABLE18 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE18(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE18_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE18_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE19_MASK       (0x80000U)
+#define DMA_COMMON_ENABLESET_ENABLE19_SHIFT      (19U)
+/*! ENABLE19 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE19(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE19_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE19_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE20_MASK       (0x100000U)
+#define DMA_COMMON_ENABLESET_ENABLE20_SHIFT      (20U)
+/*! ENABLE20 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE20(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE20_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE20_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE21_MASK       (0x200000U)
+#define DMA_COMMON_ENABLESET_ENABLE21_SHIFT      (21U)
+/*! ENABLE21 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE21(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE21_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE21_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE22_MASK       (0x400000U)
+#define DMA_COMMON_ENABLESET_ENABLE22_SHIFT      (22U)
+/*! ENABLE22 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE22(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE22_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE22_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE23_MASK       (0x800000U)
+#define DMA_COMMON_ENABLESET_ENABLE23_SHIFT      (23U)
+/*! ENABLE23 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE23(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE23_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE23_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE24_MASK       (0x1000000U)
+#define DMA_COMMON_ENABLESET_ENABLE24_SHIFT      (24U)
+/*! ENABLE24 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE24(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE24_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE24_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE25_MASK       (0x2000000U)
+#define DMA_COMMON_ENABLESET_ENABLE25_SHIFT      (25U)
+/*! ENABLE25 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE25(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE25_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE25_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE26_MASK       (0x4000000U)
+#define DMA_COMMON_ENABLESET_ENABLE26_SHIFT      (26U)
+/*! ENABLE26 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE26(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE26_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE26_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE27_MASK       (0x8000000U)
+#define DMA_COMMON_ENABLESET_ENABLE27_SHIFT      (27U)
+/*! ENABLE27 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE27(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE27_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE27_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE28_MASK       (0x10000000U)
+#define DMA_COMMON_ENABLESET_ENABLE28_SHIFT      (28U)
+/*! ENABLE28 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE28(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE28_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE28_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE29_MASK       (0x20000000U)
+#define DMA_COMMON_ENABLESET_ENABLE29_SHIFT      (29U)
+/*! ENABLE29 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE29(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE29_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE29_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE30_MASK       (0x40000000U)
+#define DMA_COMMON_ENABLESET_ENABLE30_SHIFT      (30U)
+/*! ENABLE30 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE30(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE30_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE30_MASK)
+
+#define DMA_COMMON_ENABLESET_ENABLE31_MASK       (0x80000000U)
+#define DMA_COMMON_ENABLESET_ENABLE31_SHIFT      (31U)
+/*! ENABLE31 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE31(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE31_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLESET1 - Channel Enable read and set for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ENABLESET1_ENABLE32_MASK      (0x1U)
+#define DMA_COMMON_ENABLESET1_ENABLE32_SHIFT     (0U)
+/*! ENABLE32 - Enable for DMA channel
+ *  0b0..DMA channel is disabled.
+ *  0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET1_ENABLE32(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE32_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET1 */
+#define DMA_COMMON_ENABLESET1_COUNT              (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ENABLECLR_CLR0_MASK           (0x1U)
+#define DMA_COMMON_ENABLECLR_CLR0_SHIFT          (0U)
+/*! CLR0 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR0(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR1_MASK           (0x2U)
+#define DMA_COMMON_ENABLECLR_CLR1_SHIFT          (1U)
+/*! CLR1 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR1(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR1_SHIFT)) & DMA_COMMON_ENABLECLR_CLR1_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR2_MASK           (0x4U)
+#define DMA_COMMON_ENABLECLR_CLR2_SHIFT          (2U)
+/*! CLR2 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR2(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR2_SHIFT)) & DMA_COMMON_ENABLECLR_CLR2_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR3_MASK           (0x8U)
+#define DMA_COMMON_ENABLECLR_CLR3_SHIFT          (3U)
+/*! CLR3 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR3(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR3_SHIFT)) & DMA_COMMON_ENABLECLR_CLR3_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR4_MASK           (0x10U)
+#define DMA_COMMON_ENABLECLR_CLR4_SHIFT          (4U)
+/*! CLR4 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR4(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR4_SHIFT)) & DMA_COMMON_ENABLECLR_CLR4_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR5_MASK           (0x20U)
+#define DMA_COMMON_ENABLECLR_CLR5_SHIFT          (5U)
+/*! CLR5 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR5(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR5_SHIFT)) & DMA_COMMON_ENABLECLR_CLR5_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR6_MASK           (0x40U)
+#define DMA_COMMON_ENABLECLR_CLR6_SHIFT          (6U)
+/*! CLR6 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR6(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR6_SHIFT)) & DMA_COMMON_ENABLECLR_CLR6_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR7_MASK           (0x80U)
+#define DMA_COMMON_ENABLECLR_CLR7_SHIFT          (7U)
+/*! CLR7 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR7(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR7_SHIFT)) & DMA_COMMON_ENABLECLR_CLR7_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR8_MASK           (0x100U)
+#define DMA_COMMON_ENABLECLR_CLR8_SHIFT          (8U)
+/*! CLR8 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR8(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR8_SHIFT)) & DMA_COMMON_ENABLECLR_CLR8_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR9_MASK           (0x200U)
+#define DMA_COMMON_ENABLECLR_CLR9_SHIFT          (9U)
+/*! CLR9 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR9(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR9_SHIFT)) & DMA_COMMON_ENABLECLR_CLR9_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR10_MASK          (0x400U)
+#define DMA_COMMON_ENABLECLR_CLR10_SHIFT         (10U)
+/*! CLR10 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR10(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR10_SHIFT)) & DMA_COMMON_ENABLECLR_CLR10_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR11_MASK          (0x800U)
+#define DMA_COMMON_ENABLECLR_CLR11_SHIFT         (11U)
+/*! CLR11 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR11(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR11_SHIFT)) & DMA_COMMON_ENABLECLR_CLR11_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR12_MASK          (0x1000U)
+#define DMA_COMMON_ENABLECLR_CLR12_SHIFT         (12U)
+/*! CLR12 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR12(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR12_SHIFT)) & DMA_COMMON_ENABLECLR_CLR12_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR13_MASK          (0x2000U)
+#define DMA_COMMON_ENABLECLR_CLR13_SHIFT         (13U)
+/*! CLR13 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR13(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR13_SHIFT)) & DMA_COMMON_ENABLECLR_CLR13_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR14_MASK          (0x4000U)
+#define DMA_COMMON_ENABLECLR_CLR14_SHIFT         (14U)
+/*! CLR14 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR14(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR14_SHIFT)) & DMA_COMMON_ENABLECLR_CLR14_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR15_MASK          (0x8000U)
+#define DMA_COMMON_ENABLECLR_CLR15_SHIFT         (15U)
+/*! CLR15 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR15(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR15_SHIFT)) & DMA_COMMON_ENABLECLR_CLR15_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR16_MASK          (0x10000U)
+#define DMA_COMMON_ENABLECLR_CLR16_SHIFT         (16U)
+/*! CLR16 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR16(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR16_SHIFT)) & DMA_COMMON_ENABLECLR_CLR16_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR17_MASK          (0x20000U)
+#define DMA_COMMON_ENABLECLR_CLR17_SHIFT         (17U)
+/*! CLR17 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR17(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR17_SHIFT)) & DMA_COMMON_ENABLECLR_CLR17_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR18_MASK          (0x40000U)
+#define DMA_COMMON_ENABLECLR_CLR18_SHIFT         (18U)
+/*! CLR18 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR18(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR18_SHIFT)) & DMA_COMMON_ENABLECLR_CLR18_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR19_MASK          (0x80000U)
+#define DMA_COMMON_ENABLECLR_CLR19_SHIFT         (19U)
+/*! CLR19 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR19(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR19_SHIFT)) & DMA_COMMON_ENABLECLR_CLR19_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR20_MASK          (0x100000U)
+#define DMA_COMMON_ENABLECLR_CLR20_SHIFT         (20U)
+/*! CLR20 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR20(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR20_SHIFT)) & DMA_COMMON_ENABLECLR_CLR20_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR21_MASK          (0x200000U)
+#define DMA_COMMON_ENABLECLR_CLR21_SHIFT         (21U)
+/*! CLR21 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR21(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR21_SHIFT)) & DMA_COMMON_ENABLECLR_CLR21_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR22_MASK          (0x400000U)
+#define DMA_COMMON_ENABLECLR_CLR22_SHIFT         (22U)
+/*! CLR22 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR22(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR22_SHIFT)) & DMA_COMMON_ENABLECLR_CLR22_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR23_MASK          (0x800000U)
+#define DMA_COMMON_ENABLECLR_CLR23_SHIFT         (23U)
+/*! CLR23 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR23(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR23_SHIFT)) & DMA_COMMON_ENABLECLR_CLR23_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR24_MASK          (0x1000000U)
+#define DMA_COMMON_ENABLECLR_CLR24_SHIFT         (24U)
+/*! CLR24 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR24(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR24_SHIFT)) & DMA_COMMON_ENABLECLR_CLR24_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR25_MASK          (0x2000000U)
+#define DMA_COMMON_ENABLECLR_CLR25_SHIFT         (25U)
+/*! CLR25 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR25(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR25_SHIFT)) & DMA_COMMON_ENABLECLR_CLR25_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR26_MASK          (0x4000000U)
+#define DMA_COMMON_ENABLECLR_CLR26_SHIFT         (26U)
+/*! CLR26 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR26(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR26_SHIFT)) & DMA_COMMON_ENABLECLR_CLR26_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR27_MASK          (0x8000000U)
+#define DMA_COMMON_ENABLECLR_CLR27_SHIFT         (27U)
+/*! CLR27 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR27(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR27_SHIFT)) & DMA_COMMON_ENABLECLR_CLR27_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR28_MASK          (0x10000000U)
+#define DMA_COMMON_ENABLECLR_CLR28_SHIFT         (28U)
+/*! CLR28 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR28(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR28_SHIFT)) & DMA_COMMON_ENABLECLR_CLR28_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR29_MASK          (0x20000000U)
+#define DMA_COMMON_ENABLECLR_CLR29_SHIFT         (29U)
+/*! CLR29 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR29(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR29_SHIFT)) & DMA_COMMON_ENABLECLR_CLR29_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR30_MASK          (0x40000000U)
+#define DMA_COMMON_ENABLECLR_CLR30_SHIFT         (30U)
+/*! CLR30 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR30(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR30_SHIFT)) & DMA_COMMON_ENABLECLR_CLR30_MASK)
+
+#define DMA_COMMON_ENABLECLR_CLR31_MASK          (0x80000000U)
+#define DMA_COMMON_ENABLECLR_CLR31_SHIFT         (31U)
+/*! CLR31 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR31(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR31_SHIFT)) & DMA_COMMON_ENABLECLR_CLR31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR1 - Channel Enable Clear for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ENABLECLR1_CLR32_MASK         (0x1U)
+#define DMA_COMMON_ENABLECLR1_CLR32_SHIFT        (0U)
+/*! CLR32 - Writing ones to this register clears the corresponding bits in ENABLESET1.
+ *  0b0..No effect.
+ *  0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR1_CLR32(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR1 */
+#define DMA_COMMON_ENABLECLR1_COUNT              (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ACTIVE_ACTIVE0_MASK           (0x1U)
+#define DMA_COMMON_ACTIVE_ACTIVE0_SHIFT          (0U)
+/*! ACTIVE0 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE0(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE0_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE0_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE1_MASK           (0x2U)
+#define DMA_COMMON_ACTIVE_ACTIVE1_SHIFT          (1U)
+/*! ACTIVE1 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE1(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE1_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE1_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE2_MASK           (0x4U)
+#define DMA_COMMON_ACTIVE_ACTIVE2_SHIFT          (2U)
+/*! ACTIVE2 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE2(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE2_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE2_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE3_MASK           (0x8U)
+#define DMA_COMMON_ACTIVE_ACTIVE3_SHIFT          (3U)
+/*! ACTIVE3 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE3(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE3_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE3_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE4_MASK           (0x10U)
+#define DMA_COMMON_ACTIVE_ACTIVE4_SHIFT          (4U)
+/*! ACTIVE4 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE4(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE4_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE4_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE5_MASK           (0x20U)
+#define DMA_COMMON_ACTIVE_ACTIVE5_SHIFT          (5U)
+/*! ACTIVE5 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE5(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE5_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE5_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE6_MASK           (0x40U)
+#define DMA_COMMON_ACTIVE_ACTIVE6_SHIFT          (6U)
+/*! ACTIVE6 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE6(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE6_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE6_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE7_MASK           (0x80U)
+#define DMA_COMMON_ACTIVE_ACTIVE7_SHIFT          (7U)
+/*! ACTIVE7 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE7(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE7_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE7_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE8_MASK           (0x100U)
+#define DMA_COMMON_ACTIVE_ACTIVE8_SHIFT          (8U)
+/*! ACTIVE8 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE8(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE8_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE8_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE9_MASK           (0x200U)
+#define DMA_COMMON_ACTIVE_ACTIVE9_SHIFT          (9U)
+/*! ACTIVE9 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE9(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE9_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE9_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE10_MASK          (0x400U)
+#define DMA_COMMON_ACTIVE_ACTIVE10_SHIFT         (10U)
+/*! ACTIVE10 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE10(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE10_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE10_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE11_MASK          (0x800U)
+#define DMA_COMMON_ACTIVE_ACTIVE11_SHIFT         (11U)
+/*! ACTIVE11 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE11(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE11_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE11_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE12_MASK          (0x1000U)
+#define DMA_COMMON_ACTIVE_ACTIVE12_SHIFT         (12U)
+/*! ACTIVE12 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE12(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE12_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE12_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE13_MASK          (0x2000U)
+#define DMA_COMMON_ACTIVE_ACTIVE13_SHIFT         (13U)
+/*! ACTIVE13 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE13(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE13_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE13_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE14_MASK          (0x4000U)
+#define DMA_COMMON_ACTIVE_ACTIVE14_SHIFT         (14U)
+/*! ACTIVE14 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE14(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE14_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE14_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE15_MASK          (0x8000U)
+#define DMA_COMMON_ACTIVE_ACTIVE15_SHIFT         (15U)
+/*! ACTIVE15 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE15(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE15_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE15_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE16_MASK          (0x10000U)
+#define DMA_COMMON_ACTIVE_ACTIVE16_SHIFT         (16U)
+/*! ACTIVE16 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE16(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE16_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE16_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE17_MASK          (0x20000U)
+#define DMA_COMMON_ACTIVE_ACTIVE17_SHIFT         (17U)
+/*! ACTIVE17 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE17(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE17_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE17_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE18_MASK          (0x40000U)
+#define DMA_COMMON_ACTIVE_ACTIVE18_SHIFT         (18U)
+/*! ACTIVE18 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE18(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE18_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE18_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE19_MASK          (0x80000U)
+#define DMA_COMMON_ACTIVE_ACTIVE19_SHIFT         (19U)
+/*! ACTIVE19 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE19(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE19_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE19_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE20_MASK          (0x100000U)
+#define DMA_COMMON_ACTIVE_ACTIVE20_SHIFT         (20U)
+/*! ACTIVE20 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE20(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE20_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE20_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE21_MASK          (0x200000U)
+#define DMA_COMMON_ACTIVE_ACTIVE21_SHIFT         (21U)
+/*! ACTIVE21 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE21(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE21_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE21_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE22_MASK          (0x400000U)
+#define DMA_COMMON_ACTIVE_ACTIVE22_SHIFT         (22U)
+/*! ACTIVE22 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE22(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE22_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE22_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE23_MASK          (0x800000U)
+#define DMA_COMMON_ACTIVE_ACTIVE23_SHIFT         (23U)
+/*! ACTIVE23 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE23(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE23_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE23_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE24_MASK          (0x1000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE24_SHIFT         (24U)
+/*! ACTIVE24 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE24(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE24_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE24_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE25_MASK          (0x2000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE25_SHIFT         (25U)
+/*! ACTIVE25 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE25(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE25_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE25_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE26_MASK          (0x4000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE26_SHIFT         (26U)
+/*! ACTIVE26 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE26(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE26_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE26_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE27_MASK          (0x8000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE27_SHIFT         (27U)
+/*! ACTIVE27 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE27(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE27_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE27_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE28_MASK          (0x10000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE28_SHIFT         (28U)
+/*! ACTIVE28 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE28(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE28_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE28_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE29_MASK          (0x20000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE29_SHIFT         (29U)
+/*! ACTIVE29 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE29(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE29_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE29_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE30_MASK          (0x40000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE30_SHIFT         (30U)
+/*! ACTIVE30 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE30(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE30_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE30_MASK)
+
+#define DMA_COMMON_ACTIVE_ACTIVE31_MASK          (0x80000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE31_SHIFT         (31U)
+/*! ACTIVE31 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE31(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE31_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_ACTIVE1 - Channel Active status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ACTIVE1_ACTIVE32_MASK         (0x1U)
+#define DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT        (0U)
+/*! ACTIVE32 - Active flag for DMA channel.
+ *  0b0..DMA channel is not active.
+ *  0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE1_ACTIVE32(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE1 */
+#define DMA_COMMON_ACTIVE1_COUNT                 (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_BUSY_BUSY0_MASK               (0x1U)
+#define DMA_COMMON_BUSY_BUSY0_SHIFT              (0U)
+/*! BUSY0 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY0_SHIFT)) & DMA_COMMON_BUSY_BUSY0_MASK)
+
+#define DMA_COMMON_BUSY_BUSY1_MASK               (0x2U)
+#define DMA_COMMON_BUSY_BUSY1_SHIFT              (1U)
+/*! BUSY1 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY1_SHIFT)) & DMA_COMMON_BUSY_BUSY1_MASK)
+
+#define DMA_COMMON_BUSY_BUSY2_MASK               (0x4U)
+#define DMA_COMMON_BUSY_BUSY2_SHIFT              (2U)
+/*! BUSY2 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY2_SHIFT)) & DMA_COMMON_BUSY_BUSY2_MASK)
+
+#define DMA_COMMON_BUSY_BUSY3_MASK               (0x8U)
+#define DMA_COMMON_BUSY_BUSY3_SHIFT              (3U)
+/*! BUSY3 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY3_SHIFT)) & DMA_COMMON_BUSY_BUSY3_MASK)
+
+#define DMA_COMMON_BUSY_BUSY4_MASK               (0x10U)
+#define DMA_COMMON_BUSY_BUSY4_SHIFT              (4U)
+/*! BUSY4 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY4_SHIFT)) & DMA_COMMON_BUSY_BUSY4_MASK)
+
+#define DMA_COMMON_BUSY_BUSY5_MASK               (0x20U)
+#define DMA_COMMON_BUSY_BUSY5_SHIFT              (5U)
+/*! BUSY5 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY5_SHIFT)) & DMA_COMMON_BUSY_BUSY5_MASK)
+
+#define DMA_COMMON_BUSY_BUSY6_MASK               (0x40U)
+#define DMA_COMMON_BUSY_BUSY6_SHIFT              (6U)
+/*! BUSY6 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY6_SHIFT)) & DMA_COMMON_BUSY_BUSY6_MASK)
+
+#define DMA_COMMON_BUSY_BUSY7_MASK               (0x80U)
+#define DMA_COMMON_BUSY_BUSY7_SHIFT              (7U)
+/*! BUSY7 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY7_SHIFT)) & DMA_COMMON_BUSY_BUSY7_MASK)
+
+#define DMA_COMMON_BUSY_BUSY8_MASK               (0x100U)
+#define DMA_COMMON_BUSY_BUSY8_SHIFT              (8U)
+/*! BUSY8 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY8_SHIFT)) & DMA_COMMON_BUSY_BUSY8_MASK)
+
+#define DMA_COMMON_BUSY_BUSY9_MASK               (0x200U)
+#define DMA_COMMON_BUSY_BUSY9_SHIFT              (9U)
+/*! BUSY9 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY9_SHIFT)) & DMA_COMMON_BUSY_BUSY9_MASK)
+
+#define DMA_COMMON_BUSY_BUSY10_MASK              (0x400U)
+#define DMA_COMMON_BUSY_BUSY10_SHIFT             (10U)
+/*! BUSY10 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY10_SHIFT)) & DMA_COMMON_BUSY_BUSY10_MASK)
+
+#define DMA_COMMON_BUSY_BUSY11_MASK              (0x800U)
+#define DMA_COMMON_BUSY_BUSY11_SHIFT             (11U)
+/*! BUSY11 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY11_SHIFT)) & DMA_COMMON_BUSY_BUSY11_MASK)
+
+#define DMA_COMMON_BUSY_BUSY12_MASK              (0x1000U)
+#define DMA_COMMON_BUSY_BUSY12_SHIFT             (12U)
+/*! BUSY12 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY12_SHIFT)) & DMA_COMMON_BUSY_BUSY12_MASK)
+
+#define DMA_COMMON_BUSY_BUSY13_MASK              (0x2000U)
+#define DMA_COMMON_BUSY_BUSY13_SHIFT             (13U)
+/*! BUSY13 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY13_SHIFT)) & DMA_COMMON_BUSY_BUSY13_MASK)
+
+#define DMA_COMMON_BUSY_BUSY14_MASK              (0x4000U)
+#define DMA_COMMON_BUSY_BUSY14_SHIFT             (14U)
+/*! BUSY14 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY14_SHIFT)) & DMA_COMMON_BUSY_BUSY14_MASK)
+
+#define DMA_COMMON_BUSY_BUSY15_MASK              (0x8000U)
+#define DMA_COMMON_BUSY_BUSY15_SHIFT             (15U)
+/*! BUSY15 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY15_SHIFT)) & DMA_COMMON_BUSY_BUSY15_MASK)
+
+#define DMA_COMMON_BUSY_BUSY16_MASK              (0x10000U)
+#define DMA_COMMON_BUSY_BUSY16_SHIFT             (16U)
+/*! BUSY16 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY16_SHIFT)) & DMA_COMMON_BUSY_BUSY16_MASK)
+
+#define DMA_COMMON_BUSY_BUSY17_MASK              (0x20000U)
+#define DMA_COMMON_BUSY_BUSY17_SHIFT             (17U)
+/*! BUSY17 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY17_SHIFT)) & DMA_COMMON_BUSY_BUSY17_MASK)
+
+#define DMA_COMMON_BUSY_BUSY18_MASK              (0x40000U)
+#define DMA_COMMON_BUSY_BUSY18_SHIFT             (18U)
+/*! BUSY18 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY18_SHIFT)) & DMA_COMMON_BUSY_BUSY18_MASK)
+
+#define DMA_COMMON_BUSY_BUSY19_MASK              (0x80000U)
+#define DMA_COMMON_BUSY_BUSY19_SHIFT             (19U)
+/*! BUSY19 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY19_SHIFT)) & DMA_COMMON_BUSY_BUSY19_MASK)
+
+#define DMA_COMMON_BUSY_BUSY20_MASK              (0x100000U)
+#define DMA_COMMON_BUSY_BUSY20_SHIFT             (20U)
+/*! BUSY20 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY20_SHIFT)) & DMA_COMMON_BUSY_BUSY20_MASK)
+
+#define DMA_COMMON_BUSY_BUSY21_MASK              (0x200000U)
+#define DMA_COMMON_BUSY_BUSY21_SHIFT             (21U)
+/*! BUSY21 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY21_SHIFT)) & DMA_COMMON_BUSY_BUSY21_MASK)
+
+#define DMA_COMMON_BUSY_BUSY22_MASK              (0x400000U)
+#define DMA_COMMON_BUSY_BUSY22_SHIFT             (22U)
+/*! BUSY22 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY22_SHIFT)) & DMA_COMMON_BUSY_BUSY22_MASK)
+
+#define DMA_COMMON_BUSY_BUSY23_MASK              (0x800000U)
+#define DMA_COMMON_BUSY_BUSY23_SHIFT             (23U)
+/*! BUSY23 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY23_SHIFT)) & DMA_COMMON_BUSY_BUSY23_MASK)
+
+#define DMA_COMMON_BUSY_BUSY24_MASK              (0x1000000U)
+#define DMA_COMMON_BUSY_BUSY24_SHIFT             (24U)
+/*! BUSY24 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY24_SHIFT)) & DMA_COMMON_BUSY_BUSY24_MASK)
+
+#define DMA_COMMON_BUSY_BUSY25_MASK              (0x2000000U)
+#define DMA_COMMON_BUSY_BUSY25_SHIFT             (25U)
+/*! BUSY25 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY25_SHIFT)) & DMA_COMMON_BUSY_BUSY25_MASK)
+
+#define DMA_COMMON_BUSY_BUSY26_MASK              (0x4000000U)
+#define DMA_COMMON_BUSY_BUSY26_SHIFT             (26U)
+/*! BUSY26 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY26_SHIFT)) & DMA_COMMON_BUSY_BUSY26_MASK)
+
+#define DMA_COMMON_BUSY_BUSY27_MASK              (0x8000000U)
+#define DMA_COMMON_BUSY_BUSY27_SHIFT             (27U)
+/*! BUSY27 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY27_SHIFT)) & DMA_COMMON_BUSY_BUSY27_MASK)
+
+#define DMA_COMMON_BUSY_BUSY28_MASK              (0x10000000U)
+#define DMA_COMMON_BUSY_BUSY28_SHIFT             (28U)
+/*! BUSY28 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY28_SHIFT)) & DMA_COMMON_BUSY_BUSY28_MASK)
+
+#define DMA_COMMON_BUSY_BUSY29_MASK              (0x20000000U)
+#define DMA_COMMON_BUSY_BUSY29_SHIFT             (29U)
+/*! BUSY29 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY29_SHIFT)) & DMA_COMMON_BUSY_BUSY29_MASK)
+
+#define DMA_COMMON_BUSY_BUSY30_MASK              (0x40000000U)
+#define DMA_COMMON_BUSY_BUSY30_SHIFT             (30U)
+/*! BUSY30 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY30_SHIFT)) & DMA_COMMON_BUSY_BUSY30_MASK)
+
+#define DMA_COMMON_BUSY_BUSY31_MASK              (0x80000000U)
+#define DMA_COMMON_BUSY_BUSY31_SHIFT             (31U)
+/*! BUSY31 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY31_SHIFT)) & DMA_COMMON_BUSY_BUSY31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_BUSY1 - Channel Busy status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_BUSY1_BUSY32_MASK             (0x1U)
+#define DMA_COMMON_BUSY1_BUSY32_SHIFT            (0U)
+/*! BUSY32 - Busy flag for DMA channel.
+ *  0b0..DMA channel is not busy.
+ *  0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY1_BUSY32(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY32_SHIFT)) & DMA_COMMON_BUSY1_BUSY32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY1 */
+#define DMA_COMMON_BUSY1_COUNT                   (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ERRINT_ERR0_MASK              (0x1U)
+#define DMA_COMMON_ERRINT_ERR0_SHIFT             (0U)
+/*! ERR0 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR0(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR0_SHIFT)) & DMA_COMMON_ERRINT_ERR0_MASK)
+
+#define DMA_COMMON_ERRINT_ERR1_MASK              (0x2U)
+#define DMA_COMMON_ERRINT_ERR1_SHIFT             (1U)
+/*! ERR1 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR1(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR1_SHIFT)) & DMA_COMMON_ERRINT_ERR1_MASK)
+
+#define DMA_COMMON_ERRINT_ERR2_MASK              (0x4U)
+#define DMA_COMMON_ERRINT_ERR2_SHIFT             (2U)
+/*! ERR2 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR2(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR2_SHIFT)) & DMA_COMMON_ERRINT_ERR2_MASK)
+
+#define DMA_COMMON_ERRINT_ERR3_MASK              (0x8U)
+#define DMA_COMMON_ERRINT_ERR3_SHIFT             (3U)
+/*! ERR3 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR3(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR3_SHIFT)) & DMA_COMMON_ERRINT_ERR3_MASK)
+
+#define DMA_COMMON_ERRINT_ERR4_MASK              (0x10U)
+#define DMA_COMMON_ERRINT_ERR4_SHIFT             (4U)
+/*! ERR4 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR4(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR4_SHIFT)) & DMA_COMMON_ERRINT_ERR4_MASK)
+
+#define DMA_COMMON_ERRINT_ERR5_MASK              (0x20U)
+#define DMA_COMMON_ERRINT_ERR5_SHIFT             (5U)
+/*! ERR5 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR5(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR5_SHIFT)) & DMA_COMMON_ERRINT_ERR5_MASK)
+
+#define DMA_COMMON_ERRINT_ERR6_MASK              (0x40U)
+#define DMA_COMMON_ERRINT_ERR6_SHIFT             (6U)
+/*! ERR6 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR6(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR6_SHIFT)) & DMA_COMMON_ERRINT_ERR6_MASK)
+
+#define DMA_COMMON_ERRINT_ERR7_MASK              (0x80U)
+#define DMA_COMMON_ERRINT_ERR7_SHIFT             (7U)
+/*! ERR7 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR7(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR7_SHIFT)) & DMA_COMMON_ERRINT_ERR7_MASK)
+
+#define DMA_COMMON_ERRINT_ERR8_MASK              (0x100U)
+#define DMA_COMMON_ERRINT_ERR8_SHIFT             (8U)
+/*! ERR8 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR8(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR8_SHIFT)) & DMA_COMMON_ERRINT_ERR8_MASK)
+
+#define DMA_COMMON_ERRINT_ERR9_MASK              (0x200U)
+#define DMA_COMMON_ERRINT_ERR9_SHIFT             (9U)
+/*! ERR9 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR9(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR9_SHIFT)) & DMA_COMMON_ERRINT_ERR9_MASK)
+
+#define DMA_COMMON_ERRINT_ERR10_MASK             (0x400U)
+#define DMA_COMMON_ERRINT_ERR10_SHIFT            (10U)
+/*! ERR10 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR10(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR10_SHIFT)) & DMA_COMMON_ERRINT_ERR10_MASK)
+
+#define DMA_COMMON_ERRINT_ERR11_MASK             (0x800U)
+#define DMA_COMMON_ERRINT_ERR11_SHIFT            (11U)
+/*! ERR11 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR11(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR11_SHIFT)) & DMA_COMMON_ERRINT_ERR11_MASK)
+
+#define DMA_COMMON_ERRINT_ERR12_MASK             (0x1000U)
+#define DMA_COMMON_ERRINT_ERR12_SHIFT            (12U)
+/*! ERR12 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR12(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR12_SHIFT)) & DMA_COMMON_ERRINT_ERR12_MASK)
+
+#define DMA_COMMON_ERRINT_ERR13_MASK             (0x2000U)
+#define DMA_COMMON_ERRINT_ERR13_SHIFT            (13U)
+/*! ERR13 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR13(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR13_SHIFT)) & DMA_COMMON_ERRINT_ERR13_MASK)
+
+#define DMA_COMMON_ERRINT_ERR14_MASK             (0x4000U)
+#define DMA_COMMON_ERRINT_ERR14_SHIFT            (14U)
+/*! ERR14 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR14(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR14_SHIFT)) & DMA_COMMON_ERRINT_ERR14_MASK)
+
+#define DMA_COMMON_ERRINT_ERR15_MASK             (0x8000U)
+#define DMA_COMMON_ERRINT_ERR15_SHIFT            (15U)
+/*! ERR15 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR15(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR15_SHIFT)) & DMA_COMMON_ERRINT_ERR15_MASK)
+
+#define DMA_COMMON_ERRINT_ERR16_MASK             (0x10000U)
+#define DMA_COMMON_ERRINT_ERR16_SHIFT            (16U)
+/*! ERR16 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR16(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR16_SHIFT)) & DMA_COMMON_ERRINT_ERR16_MASK)
+
+#define DMA_COMMON_ERRINT_ERR17_MASK             (0x20000U)
+#define DMA_COMMON_ERRINT_ERR17_SHIFT            (17U)
+/*! ERR17 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR17(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR17_SHIFT)) & DMA_COMMON_ERRINT_ERR17_MASK)
+
+#define DMA_COMMON_ERRINT_ERR18_MASK             (0x40000U)
+#define DMA_COMMON_ERRINT_ERR18_SHIFT            (18U)
+/*! ERR18 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR18(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR18_SHIFT)) & DMA_COMMON_ERRINT_ERR18_MASK)
+
+#define DMA_COMMON_ERRINT_ERR19_MASK             (0x80000U)
+#define DMA_COMMON_ERRINT_ERR19_SHIFT            (19U)
+/*! ERR19 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR19(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR19_SHIFT)) & DMA_COMMON_ERRINT_ERR19_MASK)
+
+#define DMA_COMMON_ERRINT_ERR20_MASK             (0x100000U)
+#define DMA_COMMON_ERRINT_ERR20_SHIFT            (20U)
+/*! ERR20 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR20(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR20_SHIFT)) & DMA_COMMON_ERRINT_ERR20_MASK)
+
+#define DMA_COMMON_ERRINT_ERR21_MASK             (0x200000U)
+#define DMA_COMMON_ERRINT_ERR21_SHIFT            (21U)
+/*! ERR21 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR21(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR21_SHIFT)) & DMA_COMMON_ERRINT_ERR21_MASK)
+
+#define DMA_COMMON_ERRINT_ERR22_MASK             (0x400000U)
+#define DMA_COMMON_ERRINT_ERR22_SHIFT            (22U)
+/*! ERR22 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR22(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR22_SHIFT)) & DMA_COMMON_ERRINT_ERR22_MASK)
+
+#define DMA_COMMON_ERRINT_ERR23_MASK             (0x800000U)
+#define DMA_COMMON_ERRINT_ERR23_SHIFT            (23U)
+/*! ERR23 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR23(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR23_SHIFT)) & DMA_COMMON_ERRINT_ERR23_MASK)
+
+#define DMA_COMMON_ERRINT_ERR24_MASK             (0x1000000U)
+#define DMA_COMMON_ERRINT_ERR24_SHIFT            (24U)
+/*! ERR24 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR24(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR24_SHIFT)) & DMA_COMMON_ERRINT_ERR24_MASK)
+
+#define DMA_COMMON_ERRINT_ERR25_MASK             (0x2000000U)
+#define DMA_COMMON_ERRINT_ERR25_SHIFT            (25U)
+/*! ERR25 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR25(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR25_SHIFT)) & DMA_COMMON_ERRINT_ERR25_MASK)
+
+#define DMA_COMMON_ERRINT_ERR26_MASK             (0x4000000U)
+#define DMA_COMMON_ERRINT_ERR26_SHIFT            (26U)
+/*! ERR26 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR26(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR26_SHIFT)) & DMA_COMMON_ERRINT_ERR26_MASK)
+
+#define DMA_COMMON_ERRINT_ERR27_MASK             (0x8000000U)
+#define DMA_COMMON_ERRINT_ERR27_SHIFT            (27U)
+/*! ERR27 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR27(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR27_SHIFT)) & DMA_COMMON_ERRINT_ERR27_MASK)
+
+#define DMA_COMMON_ERRINT_ERR28_MASK             (0x10000000U)
+#define DMA_COMMON_ERRINT_ERR28_SHIFT            (28U)
+/*! ERR28 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR28(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR28_SHIFT)) & DMA_COMMON_ERRINT_ERR28_MASK)
+
+#define DMA_COMMON_ERRINT_ERR29_MASK             (0x20000000U)
+#define DMA_COMMON_ERRINT_ERR29_SHIFT            (29U)
+/*! ERR29 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR29(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR29_SHIFT)) & DMA_COMMON_ERRINT_ERR29_MASK)
+
+#define DMA_COMMON_ERRINT_ERR30_MASK             (0x40000000U)
+#define DMA_COMMON_ERRINT_ERR30_SHIFT            (30U)
+/*! ERR30 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR30(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR30_SHIFT)) & DMA_COMMON_ERRINT_ERR30_MASK)
+
+#define DMA_COMMON_ERRINT_ERR31_MASK             (0x80000000U)
+#define DMA_COMMON_ERRINT_ERR31_SHIFT            (31U)
+/*! ERR31 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR31(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR31_SHIFT)) & DMA_COMMON_ERRINT_ERR31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_ERRINT1 - Error Interrupt status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ERRINT1_ERR32_MASK            (0x1U)
+#define DMA_COMMON_ERRINT1_ERR32_SHIFT           (0U)
+/*! ERR32 - Error Interrupt flag for DMA channel.
+ *  0b0..The Error Interrupt is not active for DMA channel.
+ *  0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT1_ERR32(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR32_SHIFT)) & DMA_COMMON_ERRINT1_ERR32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT1 */
+#define DMA_COMMON_ERRINT1_COUNT                 (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTENSET_INTEN0_MASK          (0x1U)
+#define DMA_COMMON_INTENSET_INTEN0_SHIFT         (0U)
+/*! INTEN0 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN0(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN0_SHIFT)) & DMA_COMMON_INTENSET_INTEN0_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN1_MASK          (0x2U)
+#define DMA_COMMON_INTENSET_INTEN1_SHIFT         (1U)
+/*! INTEN1 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN1(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN1_SHIFT)) & DMA_COMMON_INTENSET_INTEN1_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN2_MASK          (0x4U)
+#define DMA_COMMON_INTENSET_INTEN2_SHIFT         (2U)
+/*! INTEN2 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN2(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN2_SHIFT)) & DMA_COMMON_INTENSET_INTEN2_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN3_MASK          (0x8U)
+#define DMA_COMMON_INTENSET_INTEN3_SHIFT         (3U)
+/*! INTEN3 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN3(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN3_SHIFT)) & DMA_COMMON_INTENSET_INTEN3_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN4_MASK          (0x10U)
+#define DMA_COMMON_INTENSET_INTEN4_SHIFT         (4U)
+/*! INTEN4 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN4(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN4_SHIFT)) & DMA_COMMON_INTENSET_INTEN4_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN5_MASK          (0x20U)
+#define DMA_COMMON_INTENSET_INTEN5_SHIFT         (5U)
+/*! INTEN5 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN5(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN5_SHIFT)) & DMA_COMMON_INTENSET_INTEN5_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN6_MASK          (0x40U)
+#define DMA_COMMON_INTENSET_INTEN6_SHIFT         (6U)
+/*! INTEN6 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN6(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN6_SHIFT)) & DMA_COMMON_INTENSET_INTEN6_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN7_MASK          (0x80U)
+#define DMA_COMMON_INTENSET_INTEN7_SHIFT         (7U)
+/*! INTEN7 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN7(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN7_SHIFT)) & DMA_COMMON_INTENSET_INTEN7_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN8_MASK          (0x100U)
+#define DMA_COMMON_INTENSET_INTEN8_SHIFT         (8U)
+/*! INTEN8 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN8(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN8_SHIFT)) & DMA_COMMON_INTENSET_INTEN8_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN9_MASK          (0x200U)
+#define DMA_COMMON_INTENSET_INTEN9_SHIFT         (9U)
+/*! INTEN9 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN9(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN9_SHIFT)) & DMA_COMMON_INTENSET_INTEN9_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN10_MASK         (0x400U)
+#define DMA_COMMON_INTENSET_INTEN10_SHIFT        (10U)
+/*! INTEN10 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN10(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN10_SHIFT)) & DMA_COMMON_INTENSET_INTEN10_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN11_MASK         (0x800U)
+#define DMA_COMMON_INTENSET_INTEN11_SHIFT        (11U)
+/*! INTEN11 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN11(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN11_SHIFT)) & DMA_COMMON_INTENSET_INTEN11_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN12_MASK         (0x1000U)
+#define DMA_COMMON_INTENSET_INTEN12_SHIFT        (12U)
+/*! INTEN12 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN12(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN12_SHIFT)) & DMA_COMMON_INTENSET_INTEN12_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN13_MASK         (0x2000U)
+#define DMA_COMMON_INTENSET_INTEN13_SHIFT        (13U)
+/*! INTEN13 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN13(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN13_SHIFT)) & DMA_COMMON_INTENSET_INTEN13_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN14_MASK         (0x4000U)
+#define DMA_COMMON_INTENSET_INTEN14_SHIFT        (14U)
+/*! INTEN14 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN14(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN14_SHIFT)) & DMA_COMMON_INTENSET_INTEN14_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN15_MASK         (0x8000U)
+#define DMA_COMMON_INTENSET_INTEN15_SHIFT        (15U)
+/*! INTEN15 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN15(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN15_SHIFT)) & DMA_COMMON_INTENSET_INTEN15_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN16_MASK         (0x10000U)
+#define DMA_COMMON_INTENSET_INTEN16_SHIFT        (16U)
+/*! INTEN16 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN16(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN16_SHIFT)) & DMA_COMMON_INTENSET_INTEN16_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN17_MASK         (0x20000U)
+#define DMA_COMMON_INTENSET_INTEN17_SHIFT        (17U)
+/*! INTEN17 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN17(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN17_SHIFT)) & DMA_COMMON_INTENSET_INTEN17_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN18_MASK         (0x40000U)
+#define DMA_COMMON_INTENSET_INTEN18_SHIFT        (18U)
+/*! INTEN18 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN18(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN18_SHIFT)) & DMA_COMMON_INTENSET_INTEN18_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN19_MASK         (0x80000U)
+#define DMA_COMMON_INTENSET_INTEN19_SHIFT        (19U)
+/*! INTEN19 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN19(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN19_SHIFT)) & DMA_COMMON_INTENSET_INTEN19_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN20_MASK         (0x100000U)
+#define DMA_COMMON_INTENSET_INTEN20_SHIFT        (20U)
+/*! INTEN20 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN20(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN20_SHIFT)) & DMA_COMMON_INTENSET_INTEN20_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN21_MASK         (0x200000U)
+#define DMA_COMMON_INTENSET_INTEN21_SHIFT        (21U)
+/*! INTEN21 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN21(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN21_SHIFT)) & DMA_COMMON_INTENSET_INTEN21_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN22_MASK         (0x400000U)
+#define DMA_COMMON_INTENSET_INTEN22_SHIFT        (22U)
+/*! INTEN22 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN22(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN22_SHIFT)) & DMA_COMMON_INTENSET_INTEN22_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN23_MASK         (0x800000U)
+#define DMA_COMMON_INTENSET_INTEN23_SHIFT        (23U)
+/*! INTEN23 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN23(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN23_SHIFT)) & DMA_COMMON_INTENSET_INTEN23_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN24_MASK         (0x1000000U)
+#define DMA_COMMON_INTENSET_INTEN24_SHIFT        (24U)
+/*! INTEN24 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN24(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN24_SHIFT)) & DMA_COMMON_INTENSET_INTEN24_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN25_MASK         (0x2000000U)
+#define DMA_COMMON_INTENSET_INTEN25_SHIFT        (25U)
+/*! INTEN25 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN25(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN25_SHIFT)) & DMA_COMMON_INTENSET_INTEN25_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN26_MASK         (0x4000000U)
+#define DMA_COMMON_INTENSET_INTEN26_SHIFT        (26U)
+/*! INTEN26 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN26(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN26_SHIFT)) & DMA_COMMON_INTENSET_INTEN26_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN27_MASK         (0x8000000U)
+#define DMA_COMMON_INTENSET_INTEN27_SHIFT        (27U)
+/*! INTEN27 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN27(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN27_SHIFT)) & DMA_COMMON_INTENSET_INTEN27_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN28_MASK         (0x10000000U)
+#define DMA_COMMON_INTENSET_INTEN28_SHIFT        (28U)
+/*! INTEN28 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN28(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN28_SHIFT)) & DMA_COMMON_INTENSET_INTEN28_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN29_MASK         (0x20000000U)
+#define DMA_COMMON_INTENSET_INTEN29_SHIFT        (29U)
+/*! INTEN29 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN29(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN29_SHIFT)) & DMA_COMMON_INTENSET_INTEN29_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN30_MASK         (0x40000000U)
+#define DMA_COMMON_INTENSET_INTEN30_SHIFT        (30U)
+/*! INTEN30 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN30(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN30_SHIFT)) & DMA_COMMON_INTENSET_INTEN30_MASK)
+
+#define DMA_COMMON_INTENSET_INTEN31_MASK         (0x80000000U)
+#define DMA_COMMON_INTENSET_INTEN31_SHIFT        (31U)
+/*! INTEN31 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN31(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN31_SHIFT)) & DMA_COMMON_INTENSET_INTEN31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENSET1 - Interrupt Enable read and Set for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTENSET1_INTEN32_MASK        (0x1U)
+#define DMA_COMMON_INTENSET1_INTEN32_SHIFT       (0U)
+/*! INTEN32 - Interrupt Enable read and set for DMA channel.
+ *  0b0..The Interrupt for DMA channel is disabled.
+ *  0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET1_INTEN32(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET1 */
+#define DMA_COMMON_INTENSET1_COUNT               (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTENCLR_CLR0_MASK            (0x1U)
+#define DMA_COMMON_INTENCLR_CLR0_SHIFT           (0U)
+/*! CLR0 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR0(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR0_SHIFT)) & DMA_COMMON_INTENCLR_CLR0_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR1_MASK            (0x2U)
+#define DMA_COMMON_INTENCLR_CLR1_SHIFT           (1U)
+/*! CLR1 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR1(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR1_SHIFT)) & DMA_COMMON_INTENCLR_CLR1_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR2_MASK            (0x4U)
+#define DMA_COMMON_INTENCLR_CLR2_SHIFT           (2U)
+/*! CLR2 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR2(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR2_SHIFT)) & DMA_COMMON_INTENCLR_CLR2_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR3_MASK            (0x8U)
+#define DMA_COMMON_INTENCLR_CLR3_SHIFT           (3U)
+/*! CLR3 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR3(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR3_SHIFT)) & DMA_COMMON_INTENCLR_CLR3_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR4_MASK            (0x10U)
+#define DMA_COMMON_INTENCLR_CLR4_SHIFT           (4U)
+/*! CLR4 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR4(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR4_SHIFT)) & DMA_COMMON_INTENCLR_CLR4_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR5_MASK            (0x20U)
+#define DMA_COMMON_INTENCLR_CLR5_SHIFT           (5U)
+/*! CLR5 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR5(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR5_SHIFT)) & DMA_COMMON_INTENCLR_CLR5_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR6_MASK            (0x40U)
+#define DMA_COMMON_INTENCLR_CLR6_SHIFT           (6U)
+/*! CLR6 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR6(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR6_SHIFT)) & DMA_COMMON_INTENCLR_CLR6_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR7_MASK            (0x80U)
+#define DMA_COMMON_INTENCLR_CLR7_SHIFT           (7U)
+/*! CLR7 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR7(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR7_SHIFT)) & DMA_COMMON_INTENCLR_CLR7_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR8_MASK            (0x100U)
+#define DMA_COMMON_INTENCLR_CLR8_SHIFT           (8U)
+/*! CLR8 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR8(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR8_SHIFT)) & DMA_COMMON_INTENCLR_CLR8_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR9_MASK            (0x200U)
+#define DMA_COMMON_INTENCLR_CLR9_SHIFT           (9U)
+/*! CLR9 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR9(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR9_SHIFT)) & DMA_COMMON_INTENCLR_CLR9_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR10_MASK           (0x400U)
+#define DMA_COMMON_INTENCLR_CLR10_SHIFT          (10U)
+/*! CLR10 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR10(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR10_SHIFT)) & DMA_COMMON_INTENCLR_CLR10_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR11_MASK           (0x800U)
+#define DMA_COMMON_INTENCLR_CLR11_SHIFT          (11U)
+/*! CLR11 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR11(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR11_SHIFT)) & DMA_COMMON_INTENCLR_CLR11_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR12_MASK           (0x1000U)
+#define DMA_COMMON_INTENCLR_CLR12_SHIFT          (12U)
+/*! CLR12 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR12(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR12_SHIFT)) & DMA_COMMON_INTENCLR_CLR12_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR13_MASK           (0x2000U)
+#define DMA_COMMON_INTENCLR_CLR13_SHIFT          (13U)
+/*! CLR13 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR13(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR13_SHIFT)) & DMA_COMMON_INTENCLR_CLR13_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR14_MASK           (0x4000U)
+#define DMA_COMMON_INTENCLR_CLR14_SHIFT          (14U)
+/*! CLR14 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR14(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR14_SHIFT)) & DMA_COMMON_INTENCLR_CLR14_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR15_MASK           (0x8000U)
+#define DMA_COMMON_INTENCLR_CLR15_SHIFT          (15U)
+/*! CLR15 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR15(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR15_SHIFT)) & DMA_COMMON_INTENCLR_CLR15_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR16_MASK           (0x10000U)
+#define DMA_COMMON_INTENCLR_CLR16_SHIFT          (16U)
+/*! CLR16 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR16(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR16_SHIFT)) & DMA_COMMON_INTENCLR_CLR16_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR17_MASK           (0x20000U)
+#define DMA_COMMON_INTENCLR_CLR17_SHIFT          (17U)
+/*! CLR17 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR17(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR17_SHIFT)) & DMA_COMMON_INTENCLR_CLR17_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR18_MASK           (0x40000U)
+#define DMA_COMMON_INTENCLR_CLR18_SHIFT          (18U)
+/*! CLR18 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR18(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR18_SHIFT)) & DMA_COMMON_INTENCLR_CLR18_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR19_MASK           (0x80000U)
+#define DMA_COMMON_INTENCLR_CLR19_SHIFT          (19U)
+/*! CLR19 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR19(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR19_SHIFT)) & DMA_COMMON_INTENCLR_CLR19_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR20_MASK           (0x100000U)
+#define DMA_COMMON_INTENCLR_CLR20_SHIFT          (20U)
+/*! CLR20 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR20(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR20_SHIFT)) & DMA_COMMON_INTENCLR_CLR20_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR21_MASK           (0x200000U)
+#define DMA_COMMON_INTENCLR_CLR21_SHIFT          (21U)
+/*! CLR21 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR21(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR21_SHIFT)) & DMA_COMMON_INTENCLR_CLR21_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR22_MASK           (0x400000U)
+#define DMA_COMMON_INTENCLR_CLR22_SHIFT          (22U)
+/*! CLR22 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR22(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR22_SHIFT)) & DMA_COMMON_INTENCLR_CLR22_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR23_MASK           (0x800000U)
+#define DMA_COMMON_INTENCLR_CLR23_SHIFT          (23U)
+/*! CLR23 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR23(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR23_SHIFT)) & DMA_COMMON_INTENCLR_CLR23_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR24_MASK           (0x1000000U)
+#define DMA_COMMON_INTENCLR_CLR24_SHIFT          (24U)
+/*! CLR24 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR24(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR24_SHIFT)) & DMA_COMMON_INTENCLR_CLR24_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR25_MASK           (0x2000000U)
+#define DMA_COMMON_INTENCLR_CLR25_SHIFT          (25U)
+/*! CLR25 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR25(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR25_SHIFT)) & DMA_COMMON_INTENCLR_CLR25_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR26_MASK           (0x4000000U)
+#define DMA_COMMON_INTENCLR_CLR26_SHIFT          (26U)
+/*! CLR26 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR26(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR26_SHIFT)) & DMA_COMMON_INTENCLR_CLR26_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR27_MASK           (0x8000000U)
+#define DMA_COMMON_INTENCLR_CLR27_SHIFT          (27U)
+/*! CLR27 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR27(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR27_SHIFT)) & DMA_COMMON_INTENCLR_CLR27_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR28_MASK           (0x10000000U)
+#define DMA_COMMON_INTENCLR_CLR28_SHIFT          (28U)
+/*! CLR28 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR28(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR28_SHIFT)) & DMA_COMMON_INTENCLR_CLR28_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR29_MASK           (0x20000000U)
+#define DMA_COMMON_INTENCLR_CLR29_SHIFT          (29U)
+/*! CLR29 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR29(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR29_SHIFT)) & DMA_COMMON_INTENCLR_CLR29_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR30_MASK           (0x40000000U)
+#define DMA_COMMON_INTENCLR_CLR30_SHIFT          (30U)
+/*! CLR30 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR30(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR30_SHIFT)) & DMA_COMMON_INTENCLR_CLR30_MASK)
+
+#define DMA_COMMON_INTENCLR_CLR31_MASK           (0x80000000U)
+#define DMA_COMMON_INTENCLR_CLR31_SHIFT          (31U)
+/*! CLR31 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. */
+#define DMA_COMMON_INTENCLR_CLR31(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR31_SHIFT)) & DMA_COMMON_INTENCLR_CLR31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR1 - Interrupt Enable Clear for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTENCLR1_CLR32_MASK          (0x1U)
+#define DMA_COMMON_INTENCLR1_CLR32_SHIFT         (0U)
+/*! CLR32 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. */
+#define DMA_COMMON_INTENCLR1_CLR32(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR32_SHIFT)) & DMA_COMMON_INTENCLR1_CLR32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR1 */
+#define DMA_COMMON_INTENCLR1_COUNT               (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTA_INTA0_MASK               (0x1U)
+#define DMA_COMMON_INTA_INTA0_SHIFT              (0U)
+/*! INTA0 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA0_SHIFT)) & DMA_COMMON_INTA_INTA0_MASK)
+
+#define DMA_COMMON_INTA_INTA1_MASK               (0x2U)
+#define DMA_COMMON_INTA_INTA1_SHIFT              (1U)
+/*! INTA1 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA1_SHIFT)) & DMA_COMMON_INTA_INTA1_MASK)
+
+#define DMA_COMMON_INTA_INTA2_MASK               (0x4U)
+#define DMA_COMMON_INTA_INTA2_SHIFT              (2U)
+/*! INTA2 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA2_SHIFT)) & DMA_COMMON_INTA_INTA2_MASK)
+
+#define DMA_COMMON_INTA_INTA3_MASK               (0x8U)
+#define DMA_COMMON_INTA_INTA3_SHIFT              (3U)
+/*! INTA3 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA3_SHIFT)) & DMA_COMMON_INTA_INTA3_MASK)
+
+#define DMA_COMMON_INTA_INTA4_MASK               (0x10U)
+#define DMA_COMMON_INTA_INTA4_SHIFT              (4U)
+/*! INTA4 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA4_SHIFT)) & DMA_COMMON_INTA_INTA4_MASK)
+
+#define DMA_COMMON_INTA_INTA5_MASK               (0x20U)
+#define DMA_COMMON_INTA_INTA5_SHIFT              (5U)
+/*! INTA5 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA5_SHIFT)) & DMA_COMMON_INTA_INTA5_MASK)
+
+#define DMA_COMMON_INTA_INTA6_MASK               (0x40U)
+#define DMA_COMMON_INTA_INTA6_SHIFT              (6U)
+/*! INTA6 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA6_SHIFT)) & DMA_COMMON_INTA_INTA6_MASK)
+
+#define DMA_COMMON_INTA_INTA7_MASK               (0x80U)
+#define DMA_COMMON_INTA_INTA7_SHIFT              (7U)
+/*! INTA7 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA7_SHIFT)) & DMA_COMMON_INTA_INTA7_MASK)
+
+#define DMA_COMMON_INTA_INTA8_MASK               (0x100U)
+#define DMA_COMMON_INTA_INTA8_SHIFT              (8U)
+/*! INTA8 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA8_SHIFT)) & DMA_COMMON_INTA_INTA8_MASK)
+
+#define DMA_COMMON_INTA_INTA9_MASK               (0x200U)
+#define DMA_COMMON_INTA_INTA9_SHIFT              (9U)
+/*! INTA9 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA9_SHIFT)) & DMA_COMMON_INTA_INTA9_MASK)
+
+#define DMA_COMMON_INTA_INTA10_MASK              (0x400U)
+#define DMA_COMMON_INTA_INTA10_SHIFT             (10U)
+/*! INTA10 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA10_SHIFT)) & DMA_COMMON_INTA_INTA10_MASK)
+
+#define DMA_COMMON_INTA_INTA11_MASK              (0x800U)
+#define DMA_COMMON_INTA_INTA11_SHIFT             (11U)
+/*! INTA11 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA11_SHIFT)) & DMA_COMMON_INTA_INTA11_MASK)
+
+#define DMA_COMMON_INTA_INTA12_MASK              (0x1000U)
+#define DMA_COMMON_INTA_INTA12_SHIFT             (12U)
+/*! INTA12 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA12_SHIFT)) & DMA_COMMON_INTA_INTA12_MASK)
+
+#define DMA_COMMON_INTA_INTA13_MASK              (0x2000U)
+#define DMA_COMMON_INTA_INTA13_SHIFT             (13U)
+/*! INTA13 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA13_SHIFT)) & DMA_COMMON_INTA_INTA13_MASK)
+
+#define DMA_COMMON_INTA_INTA14_MASK              (0x4000U)
+#define DMA_COMMON_INTA_INTA14_SHIFT             (14U)
+/*! INTA14 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA14_SHIFT)) & DMA_COMMON_INTA_INTA14_MASK)
+
+#define DMA_COMMON_INTA_INTA15_MASK              (0x8000U)
+#define DMA_COMMON_INTA_INTA15_SHIFT             (15U)
+/*! INTA15 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA15_SHIFT)) & DMA_COMMON_INTA_INTA15_MASK)
+
+#define DMA_COMMON_INTA_INTA16_MASK              (0x10000U)
+#define DMA_COMMON_INTA_INTA16_SHIFT             (16U)
+/*! INTA16 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA16_SHIFT)) & DMA_COMMON_INTA_INTA16_MASK)
+
+#define DMA_COMMON_INTA_INTA17_MASK              (0x20000U)
+#define DMA_COMMON_INTA_INTA17_SHIFT             (17U)
+/*! INTA17 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA17_SHIFT)) & DMA_COMMON_INTA_INTA17_MASK)
+
+#define DMA_COMMON_INTA_INTA18_MASK              (0x40000U)
+#define DMA_COMMON_INTA_INTA18_SHIFT             (18U)
+/*! INTA18 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA18_SHIFT)) & DMA_COMMON_INTA_INTA18_MASK)
+
+#define DMA_COMMON_INTA_INTA19_MASK              (0x80000U)
+#define DMA_COMMON_INTA_INTA19_SHIFT             (19U)
+/*! INTA19 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA19_SHIFT)) & DMA_COMMON_INTA_INTA19_MASK)
+
+#define DMA_COMMON_INTA_INTA20_MASK              (0x100000U)
+#define DMA_COMMON_INTA_INTA20_SHIFT             (20U)
+/*! INTA20 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA20_SHIFT)) & DMA_COMMON_INTA_INTA20_MASK)
+
+#define DMA_COMMON_INTA_INTA21_MASK              (0x200000U)
+#define DMA_COMMON_INTA_INTA21_SHIFT             (21U)
+/*! INTA21 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA21_SHIFT)) & DMA_COMMON_INTA_INTA21_MASK)
+
+#define DMA_COMMON_INTA_INTA22_MASK              (0x400000U)
+#define DMA_COMMON_INTA_INTA22_SHIFT             (22U)
+/*! INTA22 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA22_SHIFT)) & DMA_COMMON_INTA_INTA22_MASK)
+
+#define DMA_COMMON_INTA_INTA23_MASK              (0x800000U)
+#define DMA_COMMON_INTA_INTA23_SHIFT             (23U)
+/*! INTA23 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA23_SHIFT)) & DMA_COMMON_INTA_INTA23_MASK)
+
+#define DMA_COMMON_INTA_INTA24_MASK              (0x1000000U)
+#define DMA_COMMON_INTA_INTA24_SHIFT             (24U)
+/*! INTA24 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA24_SHIFT)) & DMA_COMMON_INTA_INTA24_MASK)
+
+#define DMA_COMMON_INTA_INTA25_MASK              (0x2000000U)
+#define DMA_COMMON_INTA_INTA25_SHIFT             (25U)
+/*! INTA25 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA25_SHIFT)) & DMA_COMMON_INTA_INTA25_MASK)
+
+#define DMA_COMMON_INTA_INTA26_MASK              (0x4000000U)
+#define DMA_COMMON_INTA_INTA26_SHIFT             (26U)
+/*! INTA26 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA26_SHIFT)) & DMA_COMMON_INTA_INTA26_MASK)
+
+#define DMA_COMMON_INTA_INTA27_MASK              (0x8000000U)
+#define DMA_COMMON_INTA_INTA27_SHIFT             (27U)
+/*! INTA27 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA27_SHIFT)) & DMA_COMMON_INTA_INTA27_MASK)
+
+#define DMA_COMMON_INTA_INTA28_MASK              (0x10000000U)
+#define DMA_COMMON_INTA_INTA28_SHIFT             (28U)
+/*! INTA28 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA28_SHIFT)) & DMA_COMMON_INTA_INTA28_MASK)
+
+#define DMA_COMMON_INTA_INTA29_MASK              (0x20000000U)
+#define DMA_COMMON_INTA_INTA29_SHIFT             (29U)
+/*! INTA29 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA29_SHIFT)) & DMA_COMMON_INTA_INTA29_MASK)
+
+#define DMA_COMMON_INTA_INTA30_MASK              (0x40000000U)
+#define DMA_COMMON_INTA_INTA30_SHIFT             (30U)
+/*! INTA30 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA30_SHIFT)) & DMA_COMMON_INTA_INTA30_MASK)
+
+#define DMA_COMMON_INTA_INTA31_MASK              (0x80000000U)
+#define DMA_COMMON_INTA_INTA31_SHIFT             (31U)
+/*! INTA31 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA31_SHIFT)) & DMA_COMMON_INTA_INTA31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTA1 - Interrupt A status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTA1_INTA32_MASK             (0x1U)
+#define DMA_COMMON_INTA1_INTA32_SHIFT            (0U)
+/*! INTA32 - Interrupt A status for DMA channel.
+ *  0b0..The DMA channel interrupt A is not active.
+ *  0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA1_INTA32(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA32_SHIFT)) & DMA_COMMON_INTA1_INTA32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA1 */
+#define DMA_COMMON_INTA1_COUNT                   (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTB_INTB0_MASK               (0x1U)
+#define DMA_COMMON_INTB_INTB0_SHIFT              (0U)
+/*! INTB0 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB0_SHIFT)) & DMA_COMMON_INTB_INTB0_MASK)
+
+#define DMA_COMMON_INTB_INTB1_MASK               (0x2U)
+#define DMA_COMMON_INTB_INTB1_SHIFT              (1U)
+/*! INTB1 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB1_SHIFT)) & DMA_COMMON_INTB_INTB1_MASK)
+
+#define DMA_COMMON_INTB_INTB2_MASK               (0x4U)
+#define DMA_COMMON_INTB_INTB2_SHIFT              (2U)
+/*! INTB2 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB2_SHIFT)) & DMA_COMMON_INTB_INTB2_MASK)
+
+#define DMA_COMMON_INTB_INTB3_MASK               (0x8U)
+#define DMA_COMMON_INTB_INTB3_SHIFT              (3U)
+/*! INTB3 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB3_SHIFT)) & DMA_COMMON_INTB_INTB3_MASK)
+
+#define DMA_COMMON_INTB_INTB4_MASK               (0x10U)
+#define DMA_COMMON_INTB_INTB4_SHIFT              (4U)
+/*! INTB4 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB4_SHIFT)) & DMA_COMMON_INTB_INTB4_MASK)
+
+#define DMA_COMMON_INTB_INTB5_MASK               (0x20U)
+#define DMA_COMMON_INTB_INTB5_SHIFT              (5U)
+/*! INTB5 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB5_SHIFT)) & DMA_COMMON_INTB_INTB5_MASK)
+
+#define DMA_COMMON_INTB_INTB6_MASK               (0x40U)
+#define DMA_COMMON_INTB_INTB6_SHIFT              (6U)
+/*! INTB6 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB6_SHIFT)) & DMA_COMMON_INTB_INTB6_MASK)
+
+#define DMA_COMMON_INTB_INTB7_MASK               (0x80U)
+#define DMA_COMMON_INTB_INTB7_SHIFT              (7U)
+/*! INTB7 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB7_SHIFT)) & DMA_COMMON_INTB_INTB7_MASK)
+
+#define DMA_COMMON_INTB_INTB8_MASK               (0x100U)
+#define DMA_COMMON_INTB_INTB8_SHIFT              (8U)
+/*! INTB8 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB8_SHIFT)) & DMA_COMMON_INTB_INTB8_MASK)
+
+#define DMA_COMMON_INTB_INTB9_MASK               (0x200U)
+#define DMA_COMMON_INTB_INTB9_SHIFT              (9U)
+/*! INTB9 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB9_SHIFT)) & DMA_COMMON_INTB_INTB9_MASK)
+
+#define DMA_COMMON_INTB_INTB10_MASK              (0x400U)
+#define DMA_COMMON_INTB_INTB10_SHIFT             (10U)
+/*! INTB10 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB10_SHIFT)) & DMA_COMMON_INTB_INTB10_MASK)
+
+#define DMA_COMMON_INTB_INTB11_MASK              (0x800U)
+#define DMA_COMMON_INTB_INTB11_SHIFT             (11U)
+/*! INTB11 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB11_SHIFT)) & DMA_COMMON_INTB_INTB11_MASK)
+
+#define DMA_COMMON_INTB_INTB12_MASK              (0x1000U)
+#define DMA_COMMON_INTB_INTB12_SHIFT             (12U)
+/*! INTB12 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB12_SHIFT)) & DMA_COMMON_INTB_INTB12_MASK)
+
+#define DMA_COMMON_INTB_INTB13_MASK              (0x2000U)
+#define DMA_COMMON_INTB_INTB13_SHIFT             (13U)
+/*! INTB13 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB13_SHIFT)) & DMA_COMMON_INTB_INTB13_MASK)
+
+#define DMA_COMMON_INTB_INTB14_MASK              (0x4000U)
+#define DMA_COMMON_INTB_INTB14_SHIFT             (14U)
+/*! INTB14 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB14_SHIFT)) & DMA_COMMON_INTB_INTB14_MASK)
+
+#define DMA_COMMON_INTB_INTB15_MASK              (0x8000U)
+#define DMA_COMMON_INTB_INTB15_SHIFT             (15U)
+/*! INTB15 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB15_SHIFT)) & DMA_COMMON_INTB_INTB15_MASK)
+
+#define DMA_COMMON_INTB_INTB16_MASK              (0x10000U)
+#define DMA_COMMON_INTB_INTB16_SHIFT             (16U)
+/*! INTB16 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB16_SHIFT)) & DMA_COMMON_INTB_INTB16_MASK)
+
+#define DMA_COMMON_INTB_INTB17_MASK              (0x20000U)
+#define DMA_COMMON_INTB_INTB17_SHIFT             (17U)
+/*! INTB17 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB17_SHIFT)) & DMA_COMMON_INTB_INTB17_MASK)
+
+#define DMA_COMMON_INTB_INTB18_MASK              (0x40000U)
+#define DMA_COMMON_INTB_INTB18_SHIFT             (18U)
+/*! INTB18 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB18_SHIFT)) & DMA_COMMON_INTB_INTB18_MASK)
+
+#define DMA_COMMON_INTB_INTB19_MASK              (0x80000U)
+#define DMA_COMMON_INTB_INTB19_SHIFT             (19U)
+/*! INTB19 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB19_SHIFT)) & DMA_COMMON_INTB_INTB19_MASK)
+
+#define DMA_COMMON_INTB_INTB20_MASK              (0x100000U)
+#define DMA_COMMON_INTB_INTB20_SHIFT             (20U)
+/*! INTB20 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB20_SHIFT)) & DMA_COMMON_INTB_INTB20_MASK)
+
+#define DMA_COMMON_INTB_INTB21_MASK              (0x200000U)
+#define DMA_COMMON_INTB_INTB21_SHIFT             (21U)
+/*! INTB21 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB21_SHIFT)) & DMA_COMMON_INTB_INTB21_MASK)
+
+#define DMA_COMMON_INTB_INTB22_MASK              (0x400000U)
+#define DMA_COMMON_INTB_INTB22_SHIFT             (22U)
+/*! INTB22 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB22_SHIFT)) & DMA_COMMON_INTB_INTB22_MASK)
+
+#define DMA_COMMON_INTB_INTB23_MASK              (0x800000U)
+#define DMA_COMMON_INTB_INTB23_SHIFT             (23U)
+/*! INTB23 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB23_SHIFT)) & DMA_COMMON_INTB_INTB23_MASK)
+
+#define DMA_COMMON_INTB_INTB24_MASK              (0x1000000U)
+#define DMA_COMMON_INTB_INTB24_SHIFT             (24U)
+/*! INTB24 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB24_SHIFT)) & DMA_COMMON_INTB_INTB24_MASK)
+
+#define DMA_COMMON_INTB_INTB25_MASK              (0x2000000U)
+#define DMA_COMMON_INTB_INTB25_SHIFT             (25U)
+/*! INTB25 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB25_SHIFT)) & DMA_COMMON_INTB_INTB25_MASK)
+
+#define DMA_COMMON_INTB_INTB26_MASK              (0x4000000U)
+#define DMA_COMMON_INTB_INTB26_SHIFT             (26U)
+/*! INTB26 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB26_SHIFT)) & DMA_COMMON_INTB_INTB26_MASK)
+
+#define DMA_COMMON_INTB_INTB27_MASK              (0x8000000U)
+#define DMA_COMMON_INTB_INTB27_SHIFT             (27U)
+/*! INTB27 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB27_SHIFT)) & DMA_COMMON_INTB_INTB27_MASK)
+
+#define DMA_COMMON_INTB_INTB28_MASK              (0x10000000U)
+#define DMA_COMMON_INTB_INTB28_SHIFT             (28U)
+/*! INTB28 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB28_SHIFT)) & DMA_COMMON_INTB_INTB28_MASK)
+
+#define DMA_COMMON_INTB_INTB29_MASK              (0x20000000U)
+#define DMA_COMMON_INTB_INTB29_SHIFT             (29U)
+/*! INTB29 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB29_SHIFT)) & DMA_COMMON_INTB_INTB29_MASK)
+
+#define DMA_COMMON_INTB_INTB30_MASK              (0x40000000U)
+#define DMA_COMMON_INTB_INTB30_SHIFT             (30U)
+/*! INTB30 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB30_SHIFT)) & DMA_COMMON_INTB_INTB30_MASK)
+
+#define DMA_COMMON_INTB_INTB31_MASK              (0x80000000U)
+#define DMA_COMMON_INTB_INTB31_SHIFT             (31U)
+/*! INTB31 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB31_SHIFT)) & DMA_COMMON_INTB_INTB31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_INTB1 - Interrupt B status for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_INTB1_INTB0_MASK              (0x1U)
+#define DMA_COMMON_INTB1_INTB0_SHIFT             (0U)
+/*! INTB0 - Interrupt B status for DMA channel.
+ *  0b0..The DMA channel interrupt B is not active.
+ *  0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB1_INTB0(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB0_SHIFT)) & DMA_COMMON_INTB1_INTB0_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB1 */
+#define DMA_COMMON_INTB1_COUNT                   (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_SETVALID_SETVALID0_MASK       (0x1U)
+#define DMA_COMMON_SETVALID_SETVALID0_SHIFT      (0U)
+/*! SETVALID0 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID0(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID0_SHIFT)) & DMA_COMMON_SETVALID_SETVALID0_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID1_MASK       (0x2U)
+#define DMA_COMMON_SETVALID_SETVALID1_SHIFT      (1U)
+/*! SETVALID1 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID1(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID1_SHIFT)) & DMA_COMMON_SETVALID_SETVALID1_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID2_MASK       (0x4U)
+#define DMA_COMMON_SETVALID_SETVALID2_SHIFT      (2U)
+/*! SETVALID2 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID2(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID2_SHIFT)) & DMA_COMMON_SETVALID_SETVALID2_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID3_MASK       (0x8U)
+#define DMA_COMMON_SETVALID_SETVALID3_SHIFT      (3U)
+/*! SETVALID3 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID3(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID3_SHIFT)) & DMA_COMMON_SETVALID_SETVALID3_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID4_MASK       (0x10U)
+#define DMA_COMMON_SETVALID_SETVALID4_SHIFT      (4U)
+/*! SETVALID4 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID4(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID4_SHIFT)) & DMA_COMMON_SETVALID_SETVALID4_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID5_MASK       (0x20U)
+#define DMA_COMMON_SETVALID_SETVALID5_SHIFT      (5U)
+/*! SETVALID5 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID5(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID5_SHIFT)) & DMA_COMMON_SETVALID_SETVALID5_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID6_MASK       (0x40U)
+#define DMA_COMMON_SETVALID_SETVALID6_SHIFT      (6U)
+/*! SETVALID6 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID6(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID6_SHIFT)) & DMA_COMMON_SETVALID_SETVALID6_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID7_MASK       (0x80U)
+#define DMA_COMMON_SETVALID_SETVALID7_SHIFT      (7U)
+/*! SETVALID7 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID7(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID7_SHIFT)) & DMA_COMMON_SETVALID_SETVALID7_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID8_MASK       (0x100U)
+#define DMA_COMMON_SETVALID_SETVALID8_SHIFT      (8U)
+/*! SETVALID8 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID8(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID8_SHIFT)) & DMA_COMMON_SETVALID_SETVALID8_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID9_MASK       (0x200U)
+#define DMA_COMMON_SETVALID_SETVALID9_SHIFT      (9U)
+/*! SETVALID9 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID9(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID9_SHIFT)) & DMA_COMMON_SETVALID_SETVALID9_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID10_MASK      (0x400U)
+#define DMA_COMMON_SETVALID_SETVALID10_SHIFT     (10U)
+/*! SETVALID10 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID10(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID10_SHIFT)) & DMA_COMMON_SETVALID_SETVALID10_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID11_MASK      (0x800U)
+#define DMA_COMMON_SETVALID_SETVALID11_SHIFT     (11U)
+/*! SETVALID11 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID11(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID11_SHIFT)) & DMA_COMMON_SETVALID_SETVALID11_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID12_MASK      (0x1000U)
+#define DMA_COMMON_SETVALID_SETVALID12_SHIFT     (12U)
+/*! SETVALID12 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID12(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID12_SHIFT)) & DMA_COMMON_SETVALID_SETVALID12_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID13_MASK      (0x2000U)
+#define DMA_COMMON_SETVALID_SETVALID13_SHIFT     (13U)
+/*! SETVALID13 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID13(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID13_SHIFT)) & DMA_COMMON_SETVALID_SETVALID13_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID14_MASK      (0x4000U)
+#define DMA_COMMON_SETVALID_SETVALID14_SHIFT     (14U)
+/*! SETVALID14 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID14(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID14_SHIFT)) & DMA_COMMON_SETVALID_SETVALID14_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID15_MASK      (0x8000U)
+#define DMA_COMMON_SETVALID_SETVALID15_SHIFT     (15U)
+/*! SETVALID15 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID15(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID15_SHIFT)) & DMA_COMMON_SETVALID_SETVALID15_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID16_MASK      (0x10000U)
+#define DMA_COMMON_SETVALID_SETVALID16_SHIFT     (16U)
+/*! SETVALID16 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID16(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID16_SHIFT)) & DMA_COMMON_SETVALID_SETVALID16_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID17_MASK      (0x20000U)
+#define DMA_COMMON_SETVALID_SETVALID17_SHIFT     (17U)
+/*! SETVALID17 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID17(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID17_SHIFT)) & DMA_COMMON_SETVALID_SETVALID17_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID18_MASK      (0x40000U)
+#define DMA_COMMON_SETVALID_SETVALID18_SHIFT     (18U)
+/*! SETVALID18 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID18(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID18_SHIFT)) & DMA_COMMON_SETVALID_SETVALID18_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID19_MASK      (0x80000U)
+#define DMA_COMMON_SETVALID_SETVALID19_SHIFT     (19U)
+/*! SETVALID19 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID19(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID19_SHIFT)) & DMA_COMMON_SETVALID_SETVALID19_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID20_MASK      (0x100000U)
+#define DMA_COMMON_SETVALID_SETVALID20_SHIFT     (20U)
+/*! SETVALID20 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID20(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID20_SHIFT)) & DMA_COMMON_SETVALID_SETVALID20_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID21_MASK      (0x200000U)
+#define DMA_COMMON_SETVALID_SETVALID21_SHIFT     (21U)
+/*! SETVALID21 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID21(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID21_SHIFT)) & DMA_COMMON_SETVALID_SETVALID21_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID22_MASK      (0x400000U)
+#define DMA_COMMON_SETVALID_SETVALID22_SHIFT     (22U)
+/*! SETVALID22 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID22(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID22_SHIFT)) & DMA_COMMON_SETVALID_SETVALID22_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID23_MASK      (0x800000U)
+#define DMA_COMMON_SETVALID_SETVALID23_SHIFT     (23U)
+/*! SETVALID23 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID23(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID23_SHIFT)) & DMA_COMMON_SETVALID_SETVALID23_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID24_MASK      (0x1000000U)
+#define DMA_COMMON_SETVALID_SETVALID24_SHIFT     (24U)
+/*! SETVALID24 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID24(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID24_SHIFT)) & DMA_COMMON_SETVALID_SETVALID24_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID25_MASK      (0x2000000U)
+#define DMA_COMMON_SETVALID_SETVALID25_SHIFT     (25U)
+/*! SETVALID25 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID25(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID25_SHIFT)) & DMA_COMMON_SETVALID_SETVALID25_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID26_MASK      (0x4000000U)
+#define DMA_COMMON_SETVALID_SETVALID26_SHIFT     (26U)
+/*! SETVALID26 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID26(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID26_SHIFT)) & DMA_COMMON_SETVALID_SETVALID26_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID27_MASK      (0x8000000U)
+#define DMA_COMMON_SETVALID_SETVALID27_SHIFT     (27U)
+/*! SETVALID27 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID27(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID27_SHIFT)) & DMA_COMMON_SETVALID_SETVALID27_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID28_MASK      (0x10000000U)
+#define DMA_COMMON_SETVALID_SETVALID28_SHIFT     (28U)
+/*! SETVALID28 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID28(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID28_SHIFT)) & DMA_COMMON_SETVALID_SETVALID28_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID29_MASK      (0x20000000U)
+#define DMA_COMMON_SETVALID_SETVALID29_SHIFT     (29U)
+/*! SETVALID29 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID29(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID29_SHIFT)) & DMA_COMMON_SETVALID_SETVALID29_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID30_MASK      (0x40000000U)
+#define DMA_COMMON_SETVALID_SETVALID30_SHIFT     (30U)
+/*! SETVALID30 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID30(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID30_SHIFT)) & DMA_COMMON_SETVALID_SETVALID30_MASK)
+
+#define DMA_COMMON_SETVALID_SETVALID31_MASK      (0x80000000U)
+#define DMA_COMMON_SETVALID_SETVALID31_SHIFT     (31U)
+/*! SETVALID31 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID31(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID31_SHIFT)) & DMA_COMMON_SETVALID_SETVALID31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETVALID1 - Set ValidPending control bits for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_SETVALID1_SETVALID32_MASK     (0x1U)
+#define DMA_COMMON_SETVALID1_SETVALID32_SHIFT    (0U)
+/*! SETVALID32 - SetValid control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID1_SETVALID32(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID32_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID1 */
+#define DMA_COMMON_SETVALID1_COUNT               (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_SETTRIG_SETTRIG0_MASK         (0x1U)
+#define DMA_COMMON_SETTRIG_SETTRIG0_SHIFT        (0U)
+/*! SETTRIG0 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG0(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG0_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG0_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG1_MASK         (0x2U)
+#define DMA_COMMON_SETTRIG_SETTRIG1_SHIFT        (1U)
+/*! SETTRIG1 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG1(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG1_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG1_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG2_MASK         (0x4U)
+#define DMA_COMMON_SETTRIG_SETTRIG2_SHIFT        (2U)
+/*! SETTRIG2 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG2(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG2_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG2_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG3_MASK         (0x8U)
+#define DMA_COMMON_SETTRIG_SETTRIG3_SHIFT        (3U)
+/*! SETTRIG3 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG3(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG3_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG3_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG4_MASK         (0x10U)
+#define DMA_COMMON_SETTRIG_SETTRIG4_SHIFT        (4U)
+/*! SETTRIG4 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG4(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG4_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG4_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG5_MASK         (0x20U)
+#define DMA_COMMON_SETTRIG_SETTRIG5_SHIFT        (5U)
+/*! SETTRIG5 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG5(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG5_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG5_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG6_MASK         (0x40U)
+#define DMA_COMMON_SETTRIG_SETTRIG6_SHIFT        (6U)
+/*! SETTRIG6 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG6(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG6_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG6_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG7_MASK         (0x80U)
+#define DMA_COMMON_SETTRIG_SETTRIG7_SHIFT        (7U)
+/*! SETTRIG7 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG7(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG7_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG7_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG8_MASK         (0x100U)
+#define DMA_COMMON_SETTRIG_SETTRIG8_SHIFT        (8U)
+/*! SETTRIG8 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG8(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG8_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG8_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG9_MASK         (0x200U)
+#define DMA_COMMON_SETTRIG_SETTRIG9_SHIFT        (9U)
+/*! SETTRIG9 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG9(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG9_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG9_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG10_MASK        (0x400U)
+#define DMA_COMMON_SETTRIG_SETTRIG10_SHIFT       (10U)
+/*! SETTRIG10 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG10(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG10_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG10_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG11_MASK        (0x800U)
+#define DMA_COMMON_SETTRIG_SETTRIG11_SHIFT       (11U)
+/*! SETTRIG11 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG11(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG11_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG11_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG12_MASK        (0x1000U)
+#define DMA_COMMON_SETTRIG_SETTRIG12_SHIFT       (12U)
+/*! SETTRIG12 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG12(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG12_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG12_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG13_MASK        (0x2000U)
+#define DMA_COMMON_SETTRIG_SETTRIG13_SHIFT       (13U)
+/*! SETTRIG13 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG13(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG13_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG13_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG14_MASK        (0x4000U)
+#define DMA_COMMON_SETTRIG_SETTRIG14_SHIFT       (14U)
+/*! SETTRIG14 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG14(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG14_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG14_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG15_MASK        (0x8000U)
+#define DMA_COMMON_SETTRIG_SETTRIG15_SHIFT       (15U)
+/*! SETTRIG15 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG15(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG15_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG15_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG16_MASK        (0x10000U)
+#define DMA_COMMON_SETTRIG_SETTRIG16_SHIFT       (16U)
+/*! SETTRIG16 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG16(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG16_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG16_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG17_MASK        (0x20000U)
+#define DMA_COMMON_SETTRIG_SETTRIG17_SHIFT       (17U)
+/*! SETTRIG17 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG17(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG17_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG17_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG18_MASK        (0x40000U)
+#define DMA_COMMON_SETTRIG_SETTRIG18_SHIFT       (18U)
+/*! SETTRIG18 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG18(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG18_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG18_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG19_MASK        (0x80000U)
+#define DMA_COMMON_SETTRIG_SETTRIG19_SHIFT       (19U)
+/*! SETTRIG19 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG19(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG19_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG19_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG20_MASK        (0x100000U)
+#define DMA_COMMON_SETTRIG_SETTRIG20_SHIFT       (20U)
+/*! SETTRIG20 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG20(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG20_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG20_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG21_MASK        (0x200000U)
+#define DMA_COMMON_SETTRIG_SETTRIG21_SHIFT       (21U)
+/*! SETTRIG21 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG21(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG21_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG21_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG22_MASK        (0x400000U)
+#define DMA_COMMON_SETTRIG_SETTRIG22_SHIFT       (22U)
+/*! SETTRIG22 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG22(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG22_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG22_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG23_MASK        (0x800000U)
+#define DMA_COMMON_SETTRIG_SETTRIG23_SHIFT       (23U)
+/*! SETTRIG23 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG23(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG23_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG23_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG24_MASK        (0x1000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG24_SHIFT       (24U)
+/*! SETTRIG24 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG24(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG24_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG24_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG25_MASK        (0x2000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG25_SHIFT       (25U)
+/*! SETTRIG25 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG25(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG25_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG25_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG26_MASK        (0x4000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG26_SHIFT       (26U)
+/*! SETTRIG26 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG26(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG26_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG26_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG27_MASK        (0x8000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG27_SHIFT       (27U)
+/*! SETTRIG27 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG27(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG27_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG27_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG28_MASK        (0x10000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG28_SHIFT       (28U)
+/*! SETTRIG28 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG28(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG28_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG28_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG29_MASK        (0x20000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG29_SHIFT       (29U)
+/*! SETTRIG29 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG29(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG29_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG29_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG30_MASK        (0x40000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG30_SHIFT       (30U)
+/*! SETTRIG30 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG30(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG30_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG30_MASK)
+
+#define DMA_COMMON_SETTRIG_SETTRIG31_MASK        (0x80000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG31_SHIFT       (31U)
+/*! SETTRIG31 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG31(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG31_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_SETTRIG1 - Set Trigger control bits for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_SETTRIG1_SETTRIG32_MASK       (0x1U)
+#define DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT      (0U)
+/*! SETTRIG32 - Set Trigger control bit for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG1_SETTRIG32(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG1 */
+#define DMA_COMMON_SETTRIG1_COUNT                (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ABORT_ABORT0_MASK             (0x1U)
+#define DMA_COMMON_ABORT_ABORT0_SHIFT            (0U)
+/*! ABORT0 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT0(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT0_SHIFT)) & DMA_COMMON_ABORT_ABORT0_MASK)
+
+#define DMA_COMMON_ABORT_ABORT1_MASK             (0x2U)
+#define DMA_COMMON_ABORT_ABORT1_SHIFT            (1U)
+/*! ABORT1 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT1(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT1_SHIFT)) & DMA_COMMON_ABORT_ABORT1_MASK)
+
+#define DMA_COMMON_ABORT_ABORT2_MASK             (0x4U)
+#define DMA_COMMON_ABORT_ABORT2_SHIFT            (2U)
+/*! ABORT2 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT2(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT2_SHIFT)) & DMA_COMMON_ABORT_ABORT2_MASK)
+
+#define DMA_COMMON_ABORT_ABORT3_MASK             (0x8U)
+#define DMA_COMMON_ABORT_ABORT3_SHIFT            (3U)
+/*! ABORT3 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT3(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT3_SHIFT)) & DMA_COMMON_ABORT_ABORT3_MASK)
+
+#define DMA_COMMON_ABORT_ABORT4_MASK             (0x10U)
+#define DMA_COMMON_ABORT_ABORT4_SHIFT            (4U)
+/*! ABORT4 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT4(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT4_SHIFT)) & DMA_COMMON_ABORT_ABORT4_MASK)
+
+#define DMA_COMMON_ABORT_ABORT5_MASK             (0x20U)
+#define DMA_COMMON_ABORT_ABORT5_SHIFT            (5U)
+/*! ABORT5 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT5(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT5_SHIFT)) & DMA_COMMON_ABORT_ABORT5_MASK)
+
+#define DMA_COMMON_ABORT_ABORT6_MASK             (0x40U)
+#define DMA_COMMON_ABORT_ABORT6_SHIFT            (6U)
+/*! ABORT6 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT6(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT6_SHIFT)) & DMA_COMMON_ABORT_ABORT6_MASK)
+
+#define DMA_COMMON_ABORT_ABORT7_MASK             (0x80U)
+#define DMA_COMMON_ABORT_ABORT7_SHIFT            (7U)
+/*! ABORT7 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT7(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT7_SHIFT)) & DMA_COMMON_ABORT_ABORT7_MASK)
+
+#define DMA_COMMON_ABORT_ABORT8_MASK             (0x100U)
+#define DMA_COMMON_ABORT_ABORT8_SHIFT            (8U)
+/*! ABORT8 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT8(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT8_SHIFT)) & DMA_COMMON_ABORT_ABORT8_MASK)
+
+#define DMA_COMMON_ABORT_ABORT9_MASK             (0x200U)
+#define DMA_COMMON_ABORT_ABORT9_SHIFT            (9U)
+/*! ABORT9 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT9(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT9_SHIFT)) & DMA_COMMON_ABORT_ABORT9_MASK)
+
+#define DMA_COMMON_ABORT_ABORT10_MASK            (0x400U)
+#define DMA_COMMON_ABORT_ABORT10_SHIFT           (10U)
+/*! ABORT10 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT10(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT10_SHIFT)) & DMA_COMMON_ABORT_ABORT10_MASK)
+
+#define DMA_COMMON_ABORT_ABORT11_MASK            (0x800U)
+#define DMA_COMMON_ABORT_ABORT11_SHIFT           (11U)
+/*! ABORT11 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT11(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT11_SHIFT)) & DMA_COMMON_ABORT_ABORT11_MASK)
+
+#define DMA_COMMON_ABORT_ABORT12_MASK            (0x1000U)
+#define DMA_COMMON_ABORT_ABORT12_SHIFT           (12U)
+/*! ABORT12 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT12(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT12_SHIFT)) & DMA_COMMON_ABORT_ABORT12_MASK)
+
+#define DMA_COMMON_ABORT_ABORT13_MASK            (0x2000U)
+#define DMA_COMMON_ABORT_ABORT13_SHIFT           (13U)
+/*! ABORT13 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT13(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT13_SHIFT)) & DMA_COMMON_ABORT_ABORT13_MASK)
+
+#define DMA_COMMON_ABORT_ABORT14_MASK            (0x4000U)
+#define DMA_COMMON_ABORT_ABORT14_SHIFT           (14U)
+/*! ABORT14 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT14(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT14_SHIFT)) & DMA_COMMON_ABORT_ABORT14_MASK)
+
+#define DMA_COMMON_ABORT_ABORT15_MASK            (0x8000U)
+#define DMA_COMMON_ABORT_ABORT15_SHIFT           (15U)
+/*! ABORT15 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT15(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT15_SHIFT)) & DMA_COMMON_ABORT_ABORT15_MASK)
+
+#define DMA_COMMON_ABORT_ABORT16_MASK            (0x10000U)
+#define DMA_COMMON_ABORT_ABORT16_SHIFT           (16U)
+/*! ABORT16 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT16(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT16_SHIFT)) & DMA_COMMON_ABORT_ABORT16_MASK)
+
+#define DMA_COMMON_ABORT_ABORT17_MASK            (0x20000U)
+#define DMA_COMMON_ABORT_ABORT17_SHIFT           (17U)
+/*! ABORT17 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT17(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT17_SHIFT)) & DMA_COMMON_ABORT_ABORT17_MASK)
+
+#define DMA_COMMON_ABORT_ABORT18_MASK            (0x40000U)
+#define DMA_COMMON_ABORT_ABORT18_SHIFT           (18U)
+/*! ABORT18 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT18(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT18_SHIFT)) & DMA_COMMON_ABORT_ABORT18_MASK)
+
+#define DMA_COMMON_ABORT_ABORT19_MASK            (0x80000U)
+#define DMA_COMMON_ABORT_ABORT19_SHIFT           (19U)
+/*! ABORT19 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT19(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT19_SHIFT)) & DMA_COMMON_ABORT_ABORT19_MASK)
+
+#define DMA_COMMON_ABORT_ABORT20_MASK            (0x100000U)
+#define DMA_COMMON_ABORT_ABORT20_SHIFT           (20U)
+/*! ABORT20 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT20(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT20_SHIFT)) & DMA_COMMON_ABORT_ABORT20_MASK)
+
+#define DMA_COMMON_ABORT_ABORT21_MASK            (0x200000U)
+#define DMA_COMMON_ABORT_ABORT21_SHIFT           (21U)
+/*! ABORT21 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT21(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT21_SHIFT)) & DMA_COMMON_ABORT_ABORT21_MASK)
+
+#define DMA_COMMON_ABORT_ABORT22_MASK            (0x400000U)
+#define DMA_COMMON_ABORT_ABORT22_SHIFT           (22U)
+/*! ABORT22 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT22(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT22_SHIFT)) & DMA_COMMON_ABORT_ABORT22_MASK)
+
+#define DMA_COMMON_ABORT_ABORT23_MASK            (0x800000U)
+#define DMA_COMMON_ABORT_ABORT23_SHIFT           (23U)
+/*! ABORT23 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT23(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT23_SHIFT)) & DMA_COMMON_ABORT_ABORT23_MASK)
+
+#define DMA_COMMON_ABORT_ABORT24_MASK            (0x1000000U)
+#define DMA_COMMON_ABORT_ABORT24_SHIFT           (24U)
+/*! ABORT24 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT24(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT24_SHIFT)) & DMA_COMMON_ABORT_ABORT24_MASK)
+
+#define DMA_COMMON_ABORT_ABORT25_MASK            (0x2000000U)
+#define DMA_COMMON_ABORT_ABORT25_SHIFT           (25U)
+/*! ABORT25 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT25(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT25_SHIFT)) & DMA_COMMON_ABORT_ABORT25_MASK)
+
+#define DMA_COMMON_ABORT_ABORT26_MASK            (0x4000000U)
+#define DMA_COMMON_ABORT_ABORT26_SHIFT           (26U)
+/*! ABORT26 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT26(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT26_SHIFT)) & DMA_COMMON_ABORT_ABORT26_MASK)
+
+#define DMA_COMMON_ABORT_ABORT27_MASK            (0x8000000U)
+#define DMA_COMMON_ABORT_ABORT27_SHIFT           (27U)
+/*! ABORT27 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT27(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT27_SHIFT)) & DMA_COMMON_ABORT_ABORT27_MASK)
+
+#define DMA_COMMON_ABORT_ABORT28_MASK            (0x10000000U)
+#define DMA_COMMON_ABORT_ABORT28_SHIFT           (28U)
+/*! ABORT28 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT28(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT28_SHIFT)) & DMA_COMMON_ABORT_ABORT28_MASK)
+
+#define DMA_COMMON_ABORT_ABORT29_MASK            (0x20000000U)
+#define DMA_COMMON_ABORT_ABORT29_SHIFT           (29U)
+/*! ABORT29 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT29(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT29_SHIFT)) & DMA_COMMON_ABORT_ABORT29_MASK)
+
+#define DMA_COMMON_ABORT_ABORT30_MASK            (0x40000000U)
+#define DMA_COMMON_ABORT_ABORT30_SHIFT           (30U)
+/*! ABORT30 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT30(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT30_SHIFT)) & DMA_COMMON_ABORT_ABORT30_MASK)
+
+#define DMA_COMMON_ABORT_ABORT31_MASK            (0x80000000U)
+#define DMA_COMMON_ABORT_ABORT31_SHIFT           (31U)
+/*! ABORT31 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT31(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT31_SHIFT)) & DMA_COMMON_ABORT_ABORT31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name COMMON_ABORT1 - Channel Abort control for all DMA channels */
+/*! @{ */
+
+#define DMA_COMMON_ABORT1_ABORT32_MASK           (0x1U)
+#define DMA_COMMON_ABORT1_ABORT32_SHIFT          (0U)
+/*! ABORT32 - Abort control for DMA channel.
+ *  0b0..No effect.
+ *  0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT1_ABORT32(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT32_SHIFT)) & DMA_COMMON_ABORT1_ABORT32_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT1 */
+#define DMA_COMMON_ABORT1_COUNT                  (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel */
+/*! @{ */
+
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+/*! PERIPHREQEN - Peripheral request Enable.
+ *  0b0..Peripheral DMA requests disabled.
+ *  0b1..Peripheral DMA requests enabled.
+ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+/*! HWTRIGEN - Hardware Triggering Enable for channel.
+ *  0b0..Hardware triggering not used for channel.
+ *  0b1..Hardware triggering used for channel.
+ */
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+/*! TRIGPOL - Trigger Polarity.
+ *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
+ *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
+ */
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+/*! TRIGTYPE - Trigger Type.
+ *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ *  0b1..Level.
+ */
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+/*! TRIGBURST - Trigger Burst.
+ *  0b0..Single transfer.
+ *  0b1..Burst transfer.
+ */
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+/*! BURSTPOWER - Burst Power. */
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+/*! SRCBURSTWRAP - Source Burst Wrap.
+ *  0b0..Disabled.
+ *  0b1..Enabled.
+ */
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+/*! DSTBURSTWRAP - Destination Burst Wrap.
+ *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+/*! CHPRIORITY - Priority of channel when multiple DMA requests are pending. */
+#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT                    (33U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel */
+/*! @{ */
+
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
+/*! VALIDPENDING - Valid pending flag for this channel.
+ *  0b0..No effect on DMA operation.
+ *  0b1..Valid pending.
+ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
+/*! TRIG - Trigger flag.
+ *  0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
+ *  0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
+ */
+#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT                (33U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel */
+/*! @{ */
+
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
+/*! CFGVALID - Configuration Valid flag.
+ *  0b0..Not valid.
+ *  0b1..Valid.
+ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
+/*! RELOAD - Reload.
+ *  0b0..Disabled. The channels' control structure should not be reloaded when the current descriptor is exhausted.
+ *  0b1..Enabled. The channels' control structure should be reloaded when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
+/*! SWTRIG - Software Trigger.
+ *  0b0..Not set.
+ *  0b1..Set.
+ */
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
+/*! CLRTRIG - Clear Trigger.
+ *  0b0..Not cleared.
+ *  0b1..Cleared.
+ */
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
+/*! SETINTA - Set Interrupt flag A for channel.
+ *  0b0..No effect.
+ *  0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
+/*! SETINTB - Set Interrupt flag B for channel.
+ *  0b0..No effect.
+ *  0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
+/*! WIDTH - Transfer width used for this DMA channel.
+ *  0b00..8-bit.
+ *  0b01..16-bit.
+ *  0b10..32-bit.
+ *  0b11..Reserved.
+ */
+#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
+/*! SRCINC - Source address increment
+ *  0b00..No increment.
+ *  0b01..1 x width.
+ *  0b10..2 x width.
+ *  0b11..4 x width.
+ */
+#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
+/*! DSTINC - Destination address increment
+ *  0b00..No increment.
+ *  0b01..1 x width.
+ *  0b10..2 x width.
+ *  0b11..4 x width.
+ */
+#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
+/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. */
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT                (33U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral DMA0 base address */
+  #define DMA0_BASE                                (0x50104000u)
+  /** Peripheral DMA0 base address */
+  #define DMA0_BASE_NS                             (0x40104000u)
+  /** Peripheral DMA0 base pointer */
+  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
+  /** Peripheral DMA0 base pointer */
+  #define DMA0_NS                                  ((DMA_Type *)DMA0_BASE_NS)
+  /** Peripheral DMA1 base address */
+  #define DMA1_BASE                                (0x50105000u)
+  /** Peripheral DMA1 base address */
+  #define DMA1_BASE_NS                             (0x40105000u)
+  /** Peripheral DMA1 base pointer */
+  #define DMA1                                     ((DMA_Type *)DMA1_BASE)
+  /** Peripheral DMA1 base pointer */
+  #define DMA1_NS                                  ((DMA_Type *)DMA1_BASE_NS)
+  /** Array initializer of DMA peripheral base addresses */
+  #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
+  /** Array initializer of DMA peripheral base pointers */
+  #define DMA_BASE_PTRS                            { DMA0, DMA1 }
+  /** Array initializer of DMA peripheral base addresses */
+  #define DMA_BASE_ADDRS_NS                        { DMA0_BASE_NS, DMA1_BASE_NS }
+  /** Array initializer of DMA peripheral base pointers */
+  #define DMA_BASE_PTRS_NS                         { DMA0_NS, DMA1_NS }
+#else
+  /** Peripheral DMA0 base address */
+  #define DMA0_BASE                                (0x40104000u)
+  /** Peripheral DMA0 base pointer */
+  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
+  /** Peripheral DMA1 base address */
+  #define DMA1_BASE                                (0x40105000u)
+  /** Peripheral DMA1 base pointer */
+  #define DMA1                                     ((DMA_Type *)DMA1_BASE)
+  /** Array initializer of DMA peripheral base addresses */
+  #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
+  /** Array initializer of DMA peripheral base pointers */
+  #define DMA_BASE_PTRS                            { DMA0, DMA1 }
+#endif
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS                                 { DMA0_IRQn, DMA1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t OSR;                               /**< Oversample Rate, array offset: 0x0, array step: 0x100 */
+    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock, array offset: 0x4, array step: 0x100 */
+    __IO uint32_t PREAC2FSCOEF;                      /**< Compensation Filter for 2 FS, array offset: 0x8, array step: 0x100 */
+    __IO uint32_t PREAC4FSCOEF;                      /**< Compensation Filter for 4 FS, array offset: 0xC, array step: 0x100 */
+    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_0[108];
+    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control, array offset: 0x80, array step: 0x100 */
+    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status, array offset: 0x84, array step: 0x100 */
+    __I  uint32_t FIFO_DATA;                         /**< FIFO Data, array offset: 0x88, array step: 0x100 */
+    __IO uint32_t PHY_CTRL;                          /**< Physical Control, array offset: 0x8C, array step: 0x100 */
+    __IO uint32_t DC_CTRL;                           /**< DC Filter Control, array offset: 0x90, array step: 0x100 */
+         uint8_t RESERVED_1[108];
+  } CHANNEL[4];
+       uint8_t RESERVED_0[2816];
+  __IO uint32_t CHANEN;                            /**< Channel Enable, offset: 0xF00 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t USE2FS;                            /**< Use 2 FS register, offset: 0xF10 */
+  __IO uint32_t GLOBAL_SYCN_EN;                    /**< Global Channel Synchronization Enable, offset: 0xF14 */
+  __IO uint32_t GLOBAL_COUNT_VAL;                  /**< Global channel synchronization counter value, offset: 0xF18 */
+  __IO uint32_t DECRESET;                          /**< DMIC decimator reset, offset: 0xF1C */
+       uint8_t RESERVED_2[96];
+  __IO uint32_t HWVADGAIN;                         /**< HWVAD Input Gain, offset: 0xF80 */
+  __IO uint32_t HWVADHPFS;                         /**< HWVAD Filter Control, offset: 0xF84 */
+  __IO uint32_t HWVADST10;                         /**< HWVAD Control, offset: 0xF88 */
+  __IO uint32_t HWVADRSTT;                         /**< HWVAD Filter Reset, offset: 0xF8C */
+  __IO uint32_t HWVADTHGN;                         /**< HWVAD Noise Estimator Gain, offset: 0xF90 */
+  __IO uint32_t HWVADTHGS;                         /**< HWVAD Signal Estimator Gain, offset: 0xF94 */
+  __I  uint32_t HWVADLOWZ;                         /**< HWVAD Noise Envelope Estimator, offset: 0xF98 */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate */
+/*! @{ */
+
+#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
+/*! OSR - Oversample Rate */
+#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT                   (4U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock */
+/*! @{ */
+
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
+/*! PDMDIV - PDM Clock Divider Value
+ *  0b0000..Divide by 1
+ *  0b0001..Divide by 2
+ *  0b0010..Divide by 3
+ *  0b0011..Divide by 4
+ *  0b0100..Divide by 6
+ *  0b0101..Divide by 8
+ *  0b0110..Divide by 12
+ *  0b0111..Divide by 16
+ *  0b1000..Divide by 24
+ *  0b1001..Divide by 32
+ *  0b1010..Divide by 48
+ *  0b1011..Divide by 64
+ *  0b1100..Divide by 96
+ *  0b1101..Divide by 128
+ *  0b1110-0b1111..Reserved
+ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT              (4U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Compensation Filter for 2 FS */
+/*! @{ */
+
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Compensation value
+ *  0b00..Compensation = 0. This is the recommended setting.
+ *  0b01..Compensation = -0.16
+ *  0b10..Compensation = -0.15
+ *  0b11..Compensation = -0.13
+ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (4U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Compensation Filter for 4 FS */
+/*! @{ */
+
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Compensation value
+ *  0b00..Compensation = 0. This is the recommended setting.
+ *  0b01..Compensation = -0.16
+ *  0b10..Compensation = -0.15
+ *  0b11..Compensation = -0.13
+ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (4U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift */
+/*! @{ */
+
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
+/*! GAIN - Gain */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT             (4U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control */
+/*! @{ */
+
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
+/*! ENABLE - FIFO Enable.
+ *  0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
+ *       streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
+ *       period when the data was not needed.
+ *  0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
+/*! RESETN - FIFO Reset
+ *  0b0..Reset the FIFO. This must be cleared before resuming operation.
+ *  0b1..Normal operation
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
+/*! INTEN - Interrupt Enable.
+ *  0b0..FIFO level interrupts are not enabled.
+ *  0b1..FIFO level interrupts are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
+/*! DMAEN - DMA Enable
+ *  0b0..DMA requests are not enabled.
+ *  0b1..DMA requests based on FIFO level are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
+/*! TRIGLVL - FIFO Trigger Level for Interrupt
+ *  0b00000..Trigger when the FIFO has received one entry (is no longer empty).
+ *  0b00001..Trigger when the FIFO has received two entries.
+ *  0b01110..Trigger when the FIFO has received 15 entries.
+ *  0b01111..Trigger when the FIFO has received 16 entries (has become full).
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (4U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status */
+/*! @{ */
+
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
+/*! INT - Status of Interrupt (write 1 to clear) */
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
+/*! OVERRUN - Overrun Detected (write 1 to clear) */
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
+/*! UNDERRUN - Underrun Detected (write 1 to clear) */
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (4U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data */
+/*! @{ */
+
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
+/*! DATA - PCM Data */
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT             (4U)
+
+/*! @name CHANNEL_PHY_CTRL - Physical Control */
+/*! @{ */
+
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
+/*! PHY_FALL - Capture DMIC on Falling edge (0 means on rising)
+ *  0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
+ *  0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
+/*! PHY_HALF - Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
+ *  0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
+ *  0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate that the decimator is providing.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT              (4U)
+
+/*! @name CHANNEL_DC_CTRL - DC Filter Control */
+/*! @{ */
+
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
+/*! DCPOLE - DC Block Filter
+ *  0b00..Flat Response, no filter
+ *  0b01..155 Hz
+ *  0b10..78 Hz
+ *  0b11..39 Hz
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
+/*! DCGAIN - DC Gain */
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+/*! SATURATEAT16BIT - Saturate at 16 Bit
+ *  0b0..Do not Saturate. Results roll over if out range and do not saturate.
+ *  0b1..Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
+ */
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+
+#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK     (0x200U)
+#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT    (9U)
+/*! SIGNEXTEND - Sign Extend
+ *  0b0..The top byte of the FIFODATA register is always 0.
+ *  0b1..The top byte of the FIFODATA register is sign extended.
+ */
+#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(x)       (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT               (4U)
+
+/*! @name CHANEN - Channel Enable */
+/*! @{ */
+
+#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
+/*! EN_CH0 - Enable Channel n
+ *  0b0..PDM channel n is disabled.
+ *  0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+
+#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
+/*! EN_CH1 - Enable Channel n
+ *  0b0..PDM channel n is disabled.
+ *  0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+
+#define DMIC_CHANEN_EN_CH2_MASK                  (0x4U)
+#define DMIC_CHANEN_EN_CH2_SHIFT                 (2U)
+/*! EN_CH2 - Enable Channel n
+ *  0b0..PDM channel n is disabled.
+ *  0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH2(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH2_SHIFT)) & DMIC_CHANEN_EN_CH2_MASK)
+
+#define DMIC_CHANEN_EN_CH3_MASK                  (0x8U)
+#define DMIC_CHANEN_EN_CH3_SHIFT                 (3U)
+/*! EN_CH3 - Enable Channel n
+ *  0b0..PDM channel n is disabled.
+ *  0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH3(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH3_SHIFT)) & DMIC_CHANEN_EN_CH3_MASK)
+/*! @} */
+
+/*! @name USE2FS - Use 2 FS register */
+/*! @{ */
+
+#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
+/*! USE2FS - Use 2FS register
+ *  0b0..Use 1 FS output for PCM data.
+ *  0b1..Use 2 FS output for PCM data.
+ */
+#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+/*! @} */
+
+/*! @name GLOBAL_SYCN_EN - Global Channel Synchronization Enable */
+/*! @{ */
+
+#define DMIC_GLOBAL_SYCN_EN_CH_SYNC_EN_MASK      (0xFU)
+#define DMIC_GLOBAL_SYCN_EN_CH_SYNC_EN_SHIFT     (0U)
+/*! CH_SYNC_EN - Channel synch enable */
+#define DMIC_GLOBAL_SYCN_EN_CH_SYNC_EN(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_SYCN_EN_CH_SYNC_EN_SHIFT)) & DMIC_GLOBAL_SYCN_EN_CH_SYNC_EN_MASK)
+/*! @} */
+
+/*! @name GLOBAL_COUNT_VAL - Global channel synchronization counter value */
+/*! @{ */
+
+#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK     (0xFFFFFFFFU)
+#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT    (0U)
+/*! CCOUNTVAL - Channel Counter Value */
+#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL(x)       (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT)) & DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK)
+/*! @} */
+
+/*! @name DECRESET - DMIC decimator reset */
+/*! @{ */
+
+#define DMIC_DECRESET_DECRESET_MASK              (0xFU)
+#define DMIC_DECRESET_DECRESET_SHIFT             (0U)
+/*! DECRESET - Decimator reset
+ *  0b0000..Release reset to decimator
+ *  0b0001..Assert reset to decimator
+ */
+#define DMIC_DECRESET_DECRESET(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_DECRESET_DECRESET_SHIFT)) & DMIC_DECRESET_DECRESET_MASK)
+/*! @} */
+
+/*! @name HWVADGAIN - HWVAD Input Gain */
+/*! @{ */
+
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
+/*! INPUTGAIN
+ *  0b0000..-10 bits
+ *  0b0001..-8 bits
+ *  0b0010..-6 bits
+ *  0b0011..-4 bits
+ *  0b0100..-2 bits
+ *  0b0101..0 bits (default)
+ *  0b0110..+2 bits
+ *  0b0111..+4 bits
+ *  0b1000..+6 bits
+ *  0b1001..+8 bits
+ *  0b1010..+10 bits
+ *  0b1011..+12 bits
+ *  0b1100..+14 bits
+ *  0b1101-0b1111..Reserved
+ */
+#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+/*! @} */
+
+/*! @name HWVADHPFS - HWVAD Filter Control */
+/*! @{ */
+
+#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
+/*! HPFS - The HPFS field chooses the High Pass filter in first part of HWVAD.
+ *  0b00..BYPASS. First filter by-pass.
+ *  0b01..HIGH_PASS_1750HZ. High pass filter with -3dB cut-off at 1750 Hz.
+ *  0b10..HIGH_PASS_215HZ. High pass filter with -3dB cut-off at 215 Hz.
+ *  0b11..Reserved
+ */
+#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+/*! @} */
+
+/*! @name HWVADST10 - HWVAD Control */
+/*! @{ */
+
+#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT                (0U)
+/*! ST10 - STAGE 1
+ *  0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
+ *  0b1..Reset internal interrupt flag by writing a '1' (stage 1) pulse.
+ */
+#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+/*! @} */
+
+/*! @name HWVADRSTT - HWVAD Filter Reset */
+/*! @{ */
+
+#define DMIC_HWVADRSTT_RSST_MASK                 (0x1U)
+#define DMIC_HWVADRSTT_RSST_SHIFT                (0U)
+/*! RSST - Reset HWVAD */
+#define DMIC_HWVADRSTT_RSST(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSST_SHIFT)) & DMIC_HWVADRSTT_RSST_MASK)
+/*! @} */
+
+/*! @name HWVADTHGN - HWVAD Noise Estimator Gain */
+/*! @{ */
+
+#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
+/*! THGN - Gain Factor for Noise Estimator */
+#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+/*! @} */
+
+/*! @name HWVADTHGS - HWVAD Signal Estimator Gain */
+/*! @{ */
+
+#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
+/*! THGS - Signal Gain Factor */
+#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+/*! @} */
+
+/*! @name HWVADLOWZ - HWVAD Noise Envelope Estimator */
+/*! @{ */
+
+#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
+/*! LOWZ - Average Noise-floor Value */
+#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral DMIC0 base address */
+  #define DMIC0_BASE                               (0x50121000u)
+  /** Peripheral DMIC0 base address */
+  #define DMIC0_BASE_NS                            (0x40121000u)
+  /** Peripheral DMIC0 base pointer */
+  #define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+  /** Peripheral DMIC0 base pointer */
+  #define DMIC0_NS                                 ((DMIC_Type *)DMIC0_BASE_NS)
+  /** Array initializer of DMIC peripheral base addresses */
+  #define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+  /** Array initializer of DMIC peripheral base pointers */
+  #define DMIC_BASE_PTRS                           { DMIC0 }
+  /** Array initializer of DMIC peripheral base addresses */
+  #define DMIC_BASE_ADDRS_NS                       { DMIC0_BASE_NS }
+  /** Array initializer of DMIC peripheral base pointers */
+  #define DMIC_BASE_PTRS_NS                        { DMIC0_NS }
+#else
+  /** Peripheral DMIC0 base address */
+  #define DMIC0_BASE                               (0x40121000u)
+  /** Peripheral DMIC0 base pointer */
+  #define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+  /** Array initializer of DMIC peripheral base addresses */
+  #define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+  /** Array initializer of DMIC peripheral base pointers */
+  #define DMIC_BASE_PTRS                           { DMIC0 }
+#endif
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS                                { DMIC_IRQn }
+#define DMIC_HWVAD_IRQS                          { HWVAD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ELS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ELS_Peripheral_Access_Layer ELS Peripheral Access Layer
+ * @{
+ */
+
+/** ELS - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ELS_STATUS;                        /**< Status register, offset: 0x0 */
+  __IO uint32_t ELS_CTRL;                          /**< ELS Control register, offset: 0x4 */
+  __IO uint32_t ELS_CMDCFG0;                       /**< ELS command configuration register, offset: 0x8 */
+  __IO uint32_t ELS_CFG;                           /**< ELS configuration register, offset: 0xC */
+  __IO uint32_t ELS_KIDX0;                         /**< Keystore index 0 - for commands that access a single key, offset: 0x10 */
+  __IO uint32_t ELS_KIDX1;                         /**< Keystore index 1 - for commands that access 2 keys, offset: 0x14 */
+  __IO uint32_t ELS_KPROPIN;                       /**< key properties request, offset: 0x18 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ELS_DMA_SRC0;                      /**< ELS DMA Source 0, offset: 0x20 */
+  __IO uint32_t ELS_DMA_SRC0_LEN;                  /**< ELS DMA Source 0 length, offset: 0x24 */
+  __IO uint32_t ELS_DMA_SRC1;                      /**< ELS DMA Source 1, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ELS_DMA_SRC2;                      /**< ELS DMA Source 2, offset: 0x30 */
+  __IO uint32_t ELS_DMA_SRC2_LEN;                  /**< ELS DMA Source 2 length, offset: 0x34 */
+  __IO uint32_t ELS_DMA_RES0;                      /**< ELS DMA Result 0, offset: 0x38 */
+  __IO uint32_t ELS_DMA_RES0_LEN;                  /**< ELS DMA Result 0 Size, offset: 0x3C */
+  __IO uint32_t ELS_INT_ENABLE;                    /**< Interrupt enable, offset: 0x40 */
+  __O  uint32_t ELS_INT_STATUS_CLR;                /**< Interrupt status clear, offset: 0x44 */
+  __O  uint32_t ELS_INT_STATUS_SET;                /**< Interrupt status set, offset: 0x48 */
+  __I  uint32_t ELS_ERR_STATUS;                    /**< Status register, offset: 0x4C */
+  __O  uint32_t ELS_ERR_STATUS_CLR;                /**< Interrupt status clear, offset: 0x50 */
+  __I  uint32_t ELS_VERSION;                       /**< ELS Version, offset: 0x54 */
+  __I  uint32_t ELS_CONFIG;                        /**< ELS Config, offset: 0x58 */
+  __I  uint32_t ELS_PRNG_DATOUT;                   /**< PRNG SW read out register, offset: 0x5C */
+  __I  uint32_t ELS_GDET_EVTCNT;                   /**< ELS GDET Event Counter, offset: 0x60 */
+  __O  uint32_t ELS_GDET_EVTCNT_CLR;               /**< ELS GDET Event Counter Clear, offset: 0x64 */
+       uint8_t RESERVED_2[152];
+  __I  uint32_t ELS_SHA2_STATUS;                   /**< ELS SHA2 Status Register, offset: 0x100 */
+  __IO uint32_t ELS_SHA2_CTRL;                     /**< SHA2 Control register, offset: 0x104 */
+  __IO uint32_t ELS_SHA2_DIN;                      /**< ELS SHA_DATA IN Register 0, offset: 0x108 */
+  __I  uint32_t ELS_SHA2_DOUT0;                    /**< ELS ELS_SHA_DATA Out Register 0, offset: 0x10C */
+  __I  uint32_t ELS_SHA2_DOUT1;                    /**< ELS SHA_DATA Out Register 1, offset: 0x110 */
+  __I  uint32_t ELS_SHA2_DOUT2;                    /**< ELS SHA_DATA Out Register 2, offset: 0x114 */
+  __I  uint32_t ELS_SHA2_DOUT3;                    /**< ELS SHA_DATA Out Register 3, offset: 0x118 */
+  __I  uint32_t ELS_SHA2_DOUT4;                    /**< ELS SHA_DATA Out Register 4, offset: 0x11C */
+  __I  uint32_t ELS_SHA2_DOUT5;                    /**< ELS SHA_DATA Out Register 5, offset: 0x120 */
+  __I  uint32_t ELS_SHA2_DOUT6;                    /**< ELS SHA_DATA Out Register 6, offset: 0x124 */
+  __I  uint32_t ELS_SHA2_DOUT7;                    /**< ELS SHA_DATA Out Register 7, offset: 0x128 */
+  __I  uint32_t ELS_SHA2_DOUT8;                    /**< ELS ELS_SHA_DATA Out Register 8, offset: 0x12C */
+  __I  uint32_t ELS_SHA2_DOUT9;                    /**< ELS SHA_DATA Out Register 9, offset: 0x130 */
+  __I  uint32_t ELS_SHA2_DOUT10;                   /**< ELS SHA_DATA Out Register 10, offset: 0x134 */
+  __I  uint32_t ELS_SHA2_DOUT11;                   /**< ELS SHA_DATA Out Register 11, offset: 0x138 */
+  __I  uint32_t ELS_SHA2_DOUT12;                   /**< ELS SHA_DATA Out Register 12, offset: 0x13C */
+  __I  uint32_t ELS_SHA2_DOUT13;                   /**< ELS SHA_DATA Out Register 13, offset: 0x140 */
+  __I  uint32_t ELS_SHA2_DOUT14;                   /**< ELS SHA_DATA Out Register 14, offset: 0x144 */
+  __I  uint32_t ELS_SHA2_DOUT15;                   /**< ELS SHA_DATA Out Register 15, offset: 0x148 */
+       uint8_t RESERVED_3[4];
+  __I  uint32_t ELS_KS0;                           /**< Status register, offset: 0x150 */
+  __I  uint32_t ELS_KS1;                           /**< Status register, offset: 0x154 */
+  __I  uint32_t ELS_KS2;                           /**< Status register, offset: 0x158 */
+  __I  uint32_t ELS_KS3;                           /**< Status register, offset: 0x15C */
+  __I  uint32_t ELS_KS4;                           /**< Status register, offset: 0x160 */
+  __I  uint32_t ELS_KS5;                           /**< Status register, offset: 0x164 */
+  __I  uint32_t ELS_KS6;                           /**< Status register, offset: 0x168 */
+  __I  uint32_t ELS_KS7;                           /**< Status register, offset: 0x16C */
+  __I  uint32_t ELS_KS8;                           /**< Status register, offset: 0x170 */
+  __I  uint32_t ELS_KS9;                           /**< Status register, offset: 0x174 */
+  __I  uint32_t ELS_KS10;                          /**< Status register, offset: 0x178 */
+  __I  uint32_t ELS_KS11;                          /**< Status register, offset: 0x17C */
+  __I  uint32_t ELS_KS12;                          /**< Status register, offset: 0x180 */
+  __I  uint32_t ELS_KS13;                          /**< Status register, offset: 0x184 */
+  __I  uint32_t ELS_KS14;                          /**< Status register, offset: 0x188 */
+  __I  uint32_t ELS_KS15;                          /**< Status register, offset: 0x18C */
+  __I  uint32_t ELS_KS16;                          /**< Status register, offset: 0x190 */
+  __I  uint32_t ELS_KS17;                          /**< Status register, offset: 0x194 */
+  __I  uint32_t ELS_KS18;                          /**< Status register, offset: 0x198 */
+  __I  uint32_t ELS_KS19;                          /**< Status register, offset: 0x19C */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t ELS_BOOT_ADDR;                     /**< SW control for the ELS boot addr, offset: 0x1A4 */
+  __IO uint32_t ELS_DBG_CFG;                       /**< ELS Debug Config SFR, offset: 0x1A8 */
+} ELS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ELS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ELS_Register_Masks ELS Register Masks
+ * @{
+ */
+
+/*! @name ELS_STATUS - Status register */
+/*! @{ */
+
+#define ELS_ELS_STATUS_ELS_BUSY_MASK             (0x1U)
+#define ELS_ELS_STATUS_ELS_BUSY_SHIFT            (0U)
+/*! ELS_BUSY - High to indicate the ELS is executing a Crypto Sequence */
+#define ELS_ELS_STATUS_ELS_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ELS_BUSY_SHIFT)) & ELS_ELS_STATUS_ELS_BUSY_MASK)
+
+#define ELS_ELS_STATUS_ELS_IRQ_MASK              (0x2U)
+#define ELS_ELS_STATUS_ELS_IRQ_SHIFT             (1U)
+/*! ELS_IRQ - High to indicate the ELS has an active interrupt */
+#define ELS_ELS_STATUS_ELS_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ELS_IRQ_SHIFT)) & ELS_ELS_STATUS_ELS_IRQ_MASK)
+
+#define ELS_ELS_STATUS_ELS_ERR_MASK              (0x4U)
+#define ELS_ELS_STATUS_ELS_ERR_SHIFT             (2U)
+/*! ELS_ERR - High to indicate the ELS has detected an internal error */
+#define ELS_ELS_STATUS_ELS_ERR(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ELS_ERR_SHIFT)) & ELS_ELS_STATUS_ELS_ERR_MASK)
+
+#define ELS_ELS_STATUS_PRNG_RDY_MASK             (0x8U)
+#define ELS_ELS_STATUS_PRNG_RDY_SHIFT            (3U)
+/*! PRNG_RDY - High to indicate the internal PRNG is ready. */
+#define ELS_ELS_STATUS_PRNG_RDY(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_PRNG_RDY_SHIFT)) & ELS_ELS_STATUS_PRNG_RDY_MASK)
+
+#define ELS_ELS_STATUS_ECDSA_VFY_STATUS_MASK     (0x30U)
+#define ELS_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT    (4U)
+/*! ECDSA_VFY_STATUS - Signature Verify Result Status; 0 == No Verify Run; 1 == Signature Verify
+ *    Failed; 2 == Signature Verify Passed; 3 == Invalid , Error
+ */
+#define ELS_ELS_STATUS_ECDSA_VFY_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & ELS_ELS_STATUS_ECDSA_VFY_STATUS_MASK)
+
+#define ELS_ELS_STATUS_PPROT_MASK                (0xC0U)
+#define ELS_ELS_STATUS_PPROT_SHIFT               (6U)
+/*! PPROT - Current command privilege level */
+#define ELS_ELS_STATUS_PPROT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_PPROT_SHIFT)) & ELS_ELS_STATUS_PPROT_MASK)
+
+#define ELS_ELS_STATUS_DRBG_ENT_LVL_MASK         (0x300U)
+#define ELS_ELS_STATUS_DRBG_ENT_LVL_SHIFT        (8U)
+/*! DRBG_ENT_LVL - Entropy quality of the current DRBG instance. */
+#define ELS_ELS_STATUS_DRBG_ENT_LVL(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & ELS_ELS_STATUS_DRBG_ENT_LVL_MASK)
+
+#define ELS_ELS_STATUS_DTRNG_BUSY_MASK           (0x400U)
+#define ELS_ELS_STATUS_DTRNG_BUSY_SHIFT          (10U)
+/*! DTRNG_BUSY - When set, it indicates the DTRNG is gathering entropy */
+#define ELS_ELS_STATUS_DTRNG_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_DTRNG_BUSY_SHIFT)) & ELS_ELS_STATUS_DTRNG_BUSY_MASK)
+
+#define ELS_ELS_STATUS_GDET_IRQ_POS_MASK         (0x800U)
+#define ELS_ELS_STATUS_GDET_IRQ_POS_SHIFT        (11U)
+/*! GDET_IRQ_POS - IRQ for GDET has detected a negative glitch: active high irq */
+#define ELS_ELS_STATUS_GDET_IRQ_POS(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_GDET_IRQ_POS_SHIFT)) & ELS_ELS_STATUS_GDET_IRQ_POS_MASK)
+
+#define ELS_ELS_STATUS_GDET_IRQ_NEG_MASK         (0x1000U)
+#define ELS_ELS_STATUS_GDET_IRQ_NEG_SHIFT        (12U)
+/*! GDET_IRQ_NEG - IRQ for GDET has detected a positive glitch: active high irq */
+#define ELS_ELS_STATUS_GDET_IRQ_NEG(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_GDET_IRQ_NEG_SHIFT)) & ELS_ELS_STATUS_GDET_IRQ_NEG_MASK)
+
+#define ELS_ELS_STATUS_STATUS_RSVD_MASK          (0xFFFFE000U)
+#define ELS_ELS_STATUS_STATUS_RSVD_SHIFT         (13U)
+#define ELS_ELS_STATUS_STATUS_RSVD(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_STATUS_STATUS_RSVD_SHIFT)) & ELS_ELS_STATUS_STATUS_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_CTRL - ELS Control register */
+/*! @{ */
+
+#define ELS_ELS_CTRL_ELS_EN_MASK                 (0x1U)
+#define ELS_ELS_CTRL_ELS_EN_SHIFT                (0U)
+/*! ELS_EN - ELS enable 0=ELS disabled, 1= ELS is enabled */
+#define ELS_ELS_CTRL_ELS_EN(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_EN_SHIFT)) & ELS_ELS_CTRL_ELS_EN_MASK)
+
+#define ELS_ELS_CTRL_ELS_START_MASK              (0x2U)
+#define ELS_ELS_CTRL_ELS_START_SHIFT             (1U)
+/*! ELS_START - Write to 1 to start a ELS Operation */
+#define ELS_ELS_CTRL_ELS_START(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_START_SHIFT)) & ELS_ELS_CTRL_ELS_START_MASK)
+
+#define ELS_ELS_CTRL_ELS_RESET_MASK              (0x4U)
+#define ELS_ELS_CTRL_ELS_RESET_SHIFT             (2U)
+/*! ELS_RESET - Write to 1 to perform a ELS synchronous Reset */
+#define ELS_ELS_CTRL_ELS_RESET(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_RESET_SHIFT)) & ELS_ELS_CTRL_ELS_RESET_MASK)
+
+#define ELS_ELS_CTRL_ELS_CMD_MASK                (0xF8U)
+#define ELS_ELS_CTRL_ELS_CMD_SHIFT               (3U)
+/*! ELS_CMD - ELS Command Field: List of Valid commands:; CIPHER; AUTH_CIPHER; ECSIGN; ECVFY;
+ *    ECKXCH; KEYGEN; KEYIN; KEYOUT; KDELETE; KEYPROV; CKDF; HKDF; TLS_INIT; HASH; HMAC; CMAC; DRBG_REQ;
+ *    DRBG_TEST; DTRNG_CFG_LOAD; DTRNG_EVAL; GDET_CFG_LOAD; GDET_TRIM
+ */
+#define ELS_ELS_CTRL_ELS_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_ELS_CMD_SHIFT)) & ELS_ELS_CTRL_ELS_CMD_MASK)
+
+#define ELS_ELS_CTRL_BYTE_ORDER_MASK             (0x100U)
+#define ELS_ELS_CTRL_BYTE_ORDER_SHIFT            (8U)
+/*! BYTE_ORDER - Defines Endianness - 1: BigEndian, 0: Little Endian */
+#define ELS_ELS_CTRL_BYTE_ORDER(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_BYTE_ORDER_SHIFT)) & ELS_ELS_CTRL_BYTE_ORDER_MASK)
+
+#define ELS_ELS_CTRL_CTRL_RFU_MASK               (0xFFFFFE00U)
+#define ELS_ELS_CTRL_CTRL_RFU_SHIFT              (9U)
+/*! CTRL_RFU - reserved */
+#define ELS_ELS_CTRL_CTRL_RFU(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CTRL_CTRL_RFU_SHIFT)) & ELS_ELS_CTRL_CTRL_RFU_MASK)
+/*! @} */
+
+/*! @name ELS_CMDCFG0 - ELS command configuration register */
+/*! @{ */
+
+#define ELS_ELS_CMDCFG0_CMDCFG0_MASK             (0xFFFFFFFFU)
+#define ELS_ELS_CMDCFG0_CMDCFG0_SHIFT            (0U)
+/*! CMDCFG0 - refer to reference manual for assignment of this field */
+#define ELS_ELS_CMDCFG0_CMDCFG0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CMDCFG0_CMDCFG0_SHIFT)) & ELS_ELS_CMDCFG0_CMDCFG0_MASK)
+/*! @} */
+
+/*! @name ELS_CFG - ELS configuration register */
+/*! @{ */
+
+#define ELS_ELS_CFG_CFG_RSVD0_MASK               (0xFFFFU)
+#define ELS_ELS_CFG_CFG_RSVD0_SHIFT              (0U)
+/*! CFG_RSVD0 - reserved */
+#define ELS_ELS_CFG_CFG_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CFG_CFG_RSVD0_SHIFT)) & ELS_ELS_CFG_CFG_RSVD0_MASK)
+
+#define ELS_ELS_CFG_ADCTRL_MASK                  (0x3FF0000U)
+#define ELS_ELS_CFG_ADCTRL_SHIFT                 (16U)
+/*! ADCTRL - maximum aes start delay */
+#define ELS_ELS_CFG_ADCTRL(x)                    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CFG_ADCTRL_SHIFT)) & ELS_ELS_CFG_ADCTRL_MASK)
+
+#define ELS_ELS_CFG_CFG_RSVD1_MASK               (0x7C000000U)
+#define ELS_ELS_CFG_CFG_RSVD1_SHIFT              (26U)
+/*! CFG_RSVD1 - reserved */
+#define ELS_ELS_CFG_CFG_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CFG_CFG_RSVD1_SHIFT)) & ELS_ELS_CFG_CFG_RSVD1_MASK)
+
+#define ELS_ELS_CFG_SHA2_DIRECT_MASK             (0x80000000U)
+#define ELS_ELS_CFG_SHA2_DIRECT_SHIFT            (31U)
+/*! SHA2_DIRECT - 1=enable sha2 direct mode: direct access from external; bus to els internal sha */
+#define ELS_ELS_CFG_SHA2_DIRECT(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CFG_SHA2_DIRECT_SHIFT)) & ELS_ELS_CFG_SHA2_DIRECT_MASK)
+/*! @} */
+
+/*! @name ELS_KIDX0 - Keystore index 0 - for commands that access a single key */
+/*! @{ */
+
+#define ELS_ELS_KIDX0_KIDX0_MASK                 (0x7FU)
+#define ELS_ELS_KIDX0_KIDX0_SHIFT                (0U)
+/*! KIDX0 - keystore is indexed as an array of 128 bit key slots */
+#define ELS_ELS_KIDX0_KIDX0(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KIDX0_KIDX0_SHIFT)) & ELS_ELS_KIDX0_KIDX0_MASK)
+/*! @} */
+
+/*! @name ELS_KIDX1 - Keystore index 1 - for commands that access 2 keys */
+/*! @{ */
+
+#define ELS_ELS_KIDX1_KIDX1_MASK                 (0x7FU)
+#define ELS_ELS_KIDX1_KIDX1_SHIFT                (0U)
+/*! KIDX1 - keystore is indexed as an array of 128 bit key slots */
+#define ELS_ELS_KIDX1_KIDX1(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KIDX1_KIDX1_SHIFT)) & ELS_ELS_KIDX1_KIDX1_MASK)
+/*! @} */
+
+/*! @name ELS_KPROPIN - key properties request */
+/*! @{ */
+
+#define ELS_ELS_KPROPIN_KPROPIN_MASK             (0xFFFFFFFFU)
+#define ELS_ELS_KPROPIN_KPROPIN_SHIFT            (0U)
+/*! KPROPIN - for commands that create a key - requested properties; of the key that is being created */
+#define ELS_ELS_KPROPIN_KPROPIN(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KPROPIN_KPROPIN_SHIFT)) & ELS_ELS_KPROPIN_KPROPIN_MASK)
+/*! @} */
+
+/*! @name ELS_DMA_SRC0 - ELS DMA Source 0 */
+/*! @{ */
+
+#define ELS_ELS_DMA_SRC0_ADDR_SRC0_MASK          (0xFFFFFFFFU)
+#define ELS_ELS_DMA_SRC0_ADDR_SRC0_SHIFT         (0U)
+/*! ADDR_SRC0 - defines the System address of the start of the; data to be transferred to the ELS via DMA */
+#define ELS_ELS_DMA_SRC0_ADDR_SRC0(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & ELS_ELS_DMA_SRC0_ADDR_SRC0_MASK)
+/*! @} */
+
+/*! @name ELS_DMA_SRC0_LEN - ELS DMA Source 0 length */
+/*! @{ */
+
+#define ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK  (0xFFFFFFFFU)
+#define ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U)
+/*! SIZE_SRC0_LEN - Size in bytes of the data to be transferred from; the target defined in SFR ELS_DMA_SRC0 */
+#define ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x)    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & ELS_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK)
+/*! @} */
+
+/*! @name ELS_DMA_SRC1 - ELS DMA Source 1 */
+/*! @{ */
+
+#define ELS_ELS_DMA_SRC1_ADDR_SRC1_MASK          (0xFFFFFFFFU)
+#define ELS_ELS_DMA_SRC1_ADDR_SRC1_SHIFT         (0U)
+/*! ADDR_SRC1 - defines the System address of the start of the; data to be transferred to the ELS via DMA */
+#define ELS_ELS_DMA_SRC1_ADDR_SRC1(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & ELS_ELS_DMA_SRC1_ADDR_SRC1_MASK)
+/*! @} */
+
+/*! @name ELS_DMA_SRC2 - ELS DMA Source 2 */
+/*! @{ */
+
+#define ELS_ELS_DMA_SRC2_ADDR_SRC2_MASK          (0xFFFFFFFFU)
+#define ELS_ELS_DMA_SRC2_ADDR_SRC2_SHIFT         (0U)
+/*! ADDR_SRC2 - defines the System address of the start of the; data to be transferred to the ELS via DMA */
+#define ELS_ELS_DMA_SRC2_ADDR_SRC2(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & ELS_ELS_DMA_SRC2_ADDR_SRC2_MASK)
+/*! @} */
+
+/*! @name ELS_DMA_SRC2_LEN - ELS DMA Source 2 length */
+/*! @{ */
+
+#define ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK  (0xFFFFFFFFU)
+#define ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U)
+/*! SIZE_SRC2_LEN - Size in bytes of the data to be transferred from; the target defined in SFR ELS_DMA_SRC2 */
+#define ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x)    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & ELS_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK)
+/*! @} */
+
+/*! @name ELS_DMA_RES0 - ELS DMA Result 0 */
+/*! @{ */
+
+#define ELS_ELS_DMA_RES0_ADDR_RES0_MASK          (0xFFFFFFFFU)
+#define ELS_ELS_DMA_RES0_ADDR_RES0_SHIFT         (0U)
+/*! ADDR_RES0 - defines the System Start address of where the result; of the ELS operation will be transferred via DMA */
+#define ELS_ELS_DMA_RES0_ADDR_RES0(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & ELS_ELS_DMA_RES0_ADDR_RES0_MASK)
+/*! @} */
+
+/*! @name ELS_DMA_RES0_LEN - ELS DMA Result 0 Size */
+/*! @{ */
+
+#define ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK  (0xFFFFFFFFU)
+#define ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U)
+/*! SIZE_RES0_LEN - Size in bytes of the data to be transferred to */
+#define ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x)    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & ELS_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK)
+/*! @} */
+
+/*! @name ELS_INT_ENABLE - Interrupt enable */
+/*! @{ */
+
+#define ELS_ELS_INT_ENABLE_INT_EN_MASK           (0x1U)
+#define ELS_ELS_INT_ENABLE_INT_EN_SHIFT          (0U)
+/*! INT_EN - Interrupt enable bit */
+#define ELS_ELS_INT_ENABLE_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_ENABLE_INT_EN_SHIFT)) & ELS_ELS_INT_ENABLE_INT_EN_MASK)
+
+#define ELS_ELS_INT_ENABLE_GDET_INT_EN_MASK      (0x2U)
+#define ELS_ELS_INT_ENABLE_GDET_INT_EN_SHIFT     (1U)
+/*! GDET_INT_EN - GDET Interrupt enable bit */
+#define ELS_ELS_INT_ENABLE_GDET_INT_EN(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_ENABLE_GDET_INT_EN_SHIFT)) & ELS_ELS_INT_ENABLE_GDET_INT_EN_MASK)
+
+#define ELS_ELS_INT_ENABLE_INT_ENA_RSVD_MASK     (0xFFFFFFFCU)
+#define ELS_ELS_INT_ENABLE_INT_ENA_RSVD_SHIFT    (2U)
+/*! INT_ENA_RSVD - reserved */
+#define ELS_ELS_INT_ENABLE_INT_ENA_RSVD(x)       (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_ENABLE_INT_ENA_RSVD_SHIFT)) & ELS_ELS_INT_ENABLE_INT_ENA_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_INT_STATUS_CLR - Interrupt status clear */
+/*! @{ */
+
+#define ELS_ELS_INT_STATUS_CLR_INT_CLR_MASK      (0x1U)
+#define ELS_ELS_INT_STATUS_CLR_INT_CLR_SHIFT     (0U)
+/*! INT_CLR - Interrupt status clear */
+#define ELS_ELS_INT_STATUS_CLR_INT_CLR(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & ELS_ELS_INT_STATUS_CLR_INT_CLR_MASK)
+
+#define ELS_ELS_INT_STATUS_CLR_GDET_INT_CLR_MASK (0x2U)
+#define ELS_ELS_INT_STATUS_CLR_GDET_INT_CLR_SHIFT (1U)
+/*! GDET_INT_CLR - GDET Interrupt status clear */
+#define ELS_ELS_INT_STATUS_CLR_GDET_INT_CLR(x)   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_CLR_GDET_INT_CLR_SHIFT)) & ELS_ELS_INT_STATUS_CLR_GDET_INT_CLR_MASK)
+
+#define ELS_ELS_INT_STATUS_CLR_INT_STSC_RSVD_MASK (0xFFFFFFFCU)
+#define ELS_ELS_INT_STATUS_CLR_INT_STSC_RSVD_SHIFT (2U)
+/*! INT_STSC_RSVD - reserved */
+#define ELS_ELS_INT_STATUS_CLR_INT_STSC_RSVD(x)  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_CLR_INT_STSC_RSVD_SHIFT)) & ELS_ELS_INT_STATUS_CLR_INT_STSC_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_INT_STATUS_SET - Interrupt status set */
+/*! @{ */
+
+#define ELS_ELS_INT_STATUS_SET_INT_SET_MASK      (0x1U)
+#define ELS_ELS_INT_STATUS_SET_INT_SET_SHIFT     (0U)
+/*! INT_SET - Set interrupt by software */
+#define ELS_ELS_INT_STATUS_SET_INT_SET(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & ELS_ELS_INT_STATUS_SET_INT_SET_MASK)
+
+#define ELS_ELS_INT_STATUS_SET_GDET_INT_NEG_SET_MASK (0x2U)
+#define ELS_ELS_INT_STATUS_SET_GDET_INT_NEG_SET_SHIFT (1U)
+/*! GDET_INT_NEG_SET - Set GDET interrupt by software */
+#define ELS_ELS_INT_STATUS_SET_GDET_INT_NEG_SET(x) (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_SET_GDET_INT_NEG_SET_SHIFT)) & ELS_ELS_INT_STATUS_SET_GDET_INT_NEG_SET_MASK)
+
+#define ELS_ELS_INT_STATUS_SET_GDET_INT_POS_SET_MASK (0x4U)
+#define ELS_ELS_INT_STATUS_SET_GDET_INT_POS_SET_SHIFT (2U)
+/*! GDET_INT_POS_SET - Set GDET interrupt by software */
+#define ELS_ELS_INT_STATUS_SET_GDET_INT_POS_SET(x) (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_SET_GDET_INT_POS_SET_SHIFT)) & ELS_ELS_INT_STATUS_SET_GDET_INT_POS_SET_MASK)
+
+#define ELS_ELS_INT_STATUS_SET_INT_STSS_RSVD_MASK (0xFFFFFFF8U)
+#define ELS_ELS_INT_STATUS_SET_INT_STSS_RSVD_SHIFT (3U)
+/*! INT_STSS_RSVD - reserved */
+#define ELS_ELS_INT_STATUS_SET_INT_STSS_RSVD(x)  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_INT_STATUS_SET_INT_STSS_RSVD_SHIFT)) & ELS_ELS_INT_STATUS_SET_INT_STSS_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_ERR_STATUS - Status register */
+/*! @{ */
+
+#define ELS_ELS_ERR_STATUS_BUS_ERR_MASK          (0x1U)
+#define ELS_ELS_ERR_STATUS_BUS_ERR_SHIFT         (0U)
+/*! BUS_ERR - Bus access error: public or private bus */
+#define ELS_ELS_ERR_STATUS_BUS_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_BUS_ERR_MASK)
+
+#define ELS_ELS_ERR_STATUS_OPN_ERR_MASK          (0x2U)
+#define ELS_ELS_ERR_STATUS_OPN_ERR_SHIFT         (1U)
+/*! OPN_ERR - Operational error:; ELS has been incorrectly operated */
+#define ELS_ELS_ERR_STATUS_OPN_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_OPN_ERR_MASK)
+
+#define ELS_ELS_ERR_STATUS_ALG_ERR_MASK          (0x4U)
+#define ELS_ELS_ERR_STATUS_ALG_ERR_SHIFT         (2U)
+/*! ALG_ERR - Algorithm error: An internal algorithm has; produced an unexpected result. */
+#define ELS_ELS_ERR_STATUS_ALG_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_ALG_ERR_MASK)
+
+#define ELS_ELS_ERR_STATUS_ITG_ERR_MASK          (0x8U)
+#define ELS_ELS_ERR_STATUS_ITG_ERR_SHIFT         (3U)
+/*! ITG_ERR - Data integrity error:; Internal data integrity check failed */
+#define ELS_ELS_ERR_STATUS_ITG_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_ITG_ERR_MASK)
+
+#define ELS_ELS_ERR_STATUS_FLT_ERR_MASK          (0x10U)
+#define ELS_ELS_ERR_STATUS_FLT_ERR_SHIFT         (4U)
+/*! FLT_ERR - Hardware fault error: Attempt to change the value; of an internal register */
+#define ELS_ELS_ERR_STATUS_FLT_ERR(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_FLT_ERR_MASK)
+
+#define ELS_ELS_ERR_STATUS_PRNG_ERR_MASK         (0x20U)
+#define ELS_ELS_ERR_STATUS_PRNG_ERR_SHIFT        (5U)
+/*! PRNG_ERR - User Read of ELS_PRNG_DATOUT when ELS_STATUS. */
+#define ELS_ELS_ERR_STATUS_PRNG_ERR(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_PRNG_ERR_MASK)
+
+#define ELS_ELS_ERR_STATUS_ERR_LVL_MASK          (0xC0U)
+#define ELS_ELS_ERR_STATUS_ERR_LVL_SHIFT         (6U)
+/*! ERR_LVL - Indicates Error Level which has been triggerer. */
+#define ELS_ELS_ERR_STATUS_ERR_LVL(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & ELS_ELS_ERR_STATUS_ERR_LVL_MASK)
+
+#define ELS_ELS_ERR_STATUS_DTRNG_ERR_MASK        (0x100U)
+#define ELS_ELS_ERR_STATUS_DTRNG_ERR_SHIFT       (8U)
+/*! DTRNG_ERR - DTRNG unable to gather entropy with the current; configuration. */
+#define ELS_ELS_ERR_STATUS_DTRNG_ERR(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & ELS_ELS_ERR_STATUS_DTRNG_ERR_MASK)
+
+#define ELS_ELS_ERR_STATUS_ERR_STAT_RSVD_MASK    (0xFFFFFE00U)
+#define ELS_ELS_ERR_STATUS_ERR_STAT_RSVD_SHIFT   (9U)
+#define ELS_ELS_ERR_STATUS_ERR_STAT_RSVD(x)      (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_ERR_STAT_RSVD_SHIFT)) & ELS_ELS_ERR_STATUS_ERR_STAT_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_ERR_STATUS_CLR - Interrupt status clear */
+/*! @{ */
+
+#define ELS_ELS_ERR_STATUS_CLR_ERR_CLR_MASK      (0x1U)
+#define ELS_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT     (0U)
+/*! ERR_CLR - 1=clear ELS error status bits and exit ELS error state */
+#define ELS_ELS_ERR_STATUS_CLR_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & ELS_ELS_ERR_STATUS_CLR_ERR_CLR_MASK)
+
+#define ELS_ELS_ERR_STATUS_CLR_ERR_STSC_RSVD_MASK (0xFFFFFFFEU)
+#define ELS_ELS_ERR_STATUS_CLR_ERR_STSC_RSVD_SHIFT (1U)
+/*! ERR_STSC_RSVD - reserved */
+#define ELS_ELS_ERR_STATUS_CLR_ERR_STSC_RSVD(x)  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_ERR_STATUS_CLR_ERR_STSC_RSVD_SHIFT)) & ELS_ELS_ERR_STATUS_CLR_ERR_STSC_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_VERSION - ELS Version */
+/*! @{ */
+
+#define ELS_ELS_VERSION_Z_MASK                   (0xFU)
+#define ELS_ELS_VERSION_Z_SHIFT                  (0U)
+/*! Z - extended revision version: possible values 0-9 */
+#define ELS_ELS_VERSION_Z(x)                     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_Z_SHIFT)) & ELS_ELS_VERSION_Z_MASK)
+
+#define ELS_ELS_VERSION_Y2_MASK                  (0xF0U)
+#define ELS_ELS_VERSION_Y2_SHIFT                 (4U)
+/*! Y2 - minor release version digit0: possible values 0-9 */
+#define ELS_ELS_VERSION_Y2(x)                    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_Y2_SHIFT)) & ELS_ELS_VERSION_Y2_MASK)
+
+#define ELS_ELS_VERSION_Y1_MASK                  (0xF00U)
+#define ELS_ELS_VERSION_Y1_SHIFT                 (8U)
+/*! Y1 - minor release version digit1: possible values 0-9 */
+#define ELS_ELS_VERSION_Y1(x)                    (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_Y1_SHIFT)) & ELS_ELS_VERSION_Y1_MASK)
+
+#define ELS_ELS_VERSION_X_MASK                   (0xF000U)
+#define ELS_ELS_VERSION_X_SHIFT                  (12U)
+/*! X - major release version: possible values 1-9 */
+#define ELS_ELS_VERSION_X(x)                     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_X_SHIFT)) & ELS_ELS_VERSION_X_MASK)
+
+#define ELS_ELS_VERSION_SW_Z_MASK                (0xF0000U)
+#define ELS_ELS_VERSION_SW_Z_SHIFT               (16U)
+/*! SW_Z - software extended revision version: possible values 0-9 */
+#define ELS_ELS_VERSION_SW_Z(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_Z_SHIFT)) & ELS_ELS_VERSION_SW_Z_MASK)
+
+#define ELS_ELS_VERSION_SW_Y2_MASK               (0xF00000U)
+#define ELS_ELS_VERSION_SW_Y2_SHIFT              (20U)
+/*! SW_Y2 - software minor release version digit0: possible values 0-9 */
+#define ELS_ELS_VERSION_SW_Y2(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_Y2_SHIFT)) & ELS_ELS_VERSION_SW_Y2_MASK)
+
+#define ELS_ELS_VERSION_SW_Y1_MASK               (0xF000000U)
+#define ELS_ELS_VERSION_SW_Y1_SHIFT              (24U)
+/*! SW_Y1 - software minor release version digit1: possible values 0-9 */
+#define ELS_ELS_VERSION_SW_Y1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_Y1_SHIFT)) & ELS_ELS_VERSION_SW_Y1_MASK)
+
+#define ELS_ELS_VERSION_SW_X_MASK                (0xF0000000U)
+#define ELS_ELS_VERSION_SW_X_SHIFT               (28U)
+/*! SW_X - software major release version: possible values 1-9 */
+#define ELS_ELS_VERSION_SW_X(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_VERSION_SW_X_SHIFT)) & ELS_ELS_VERSION_SW_X_MASK)
+/*! @} */
+
+/*! @name ELS_CONFIG - ELS Config */
+/*! @{ */
+
+#define ELS_ELS_CONFIG_CIPHER_SUP_MASK           (0x1U)
+#define ELS_ELS_CONFIG_CIPHER_SUP_SHIFT          (0U)
+/*! CIPHER_SUP - cipher command is supported */
+#define ELS_ELS_CONFIG_CIPHER_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_CIPHER_SUP_SHIFT)) & ELS_ELS_CONFIG_CIPHER_SUP_MASK)
+
+#define ELS_ELS_CONFIG_AUTH_CIPHER_SUP_MASK      (0x2U)
+#define ELS_ELS_CONFIG_AUTH_CIPHER_SUP_SHIFT     (1U)
+/*! AUTH_CIPHER_SUP - auth_cipher command is supported */
+#define ELS_ELS_CONFIG_AUTH_CIPHER_SUP(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_AUTH_CIPHER_SUP_SHIFT)) & ELS_ELS_CONFIG_AUTH_CIPHER_SUP_MASK)
+
+#define ELS_ELS_CONFIG_ECSIGN_SUP_MASK           (0x4U)
+#define ELS_ELS_CONFIG_ECSIGN_SUP_SHIFT          (2U)
+/*! ECSIGN_SUP - ecsign command is supported */
+#define ELS_ELS_CONFIG_ECSIGN_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_ECSIGN_SUP_SHIFT)) & ELS_ELS_CONFIG_ECSIGN_SUP_MASK)
+
+#define ELS_ELS_CONFIG_ECVFY_SUP_MASK            (0x8U)
+#define ELS_ELS_CONFIG_ECVFY_SUP_SHIFT           (3U)
+/*! ECVFY_SUP - ecvfy command is supported */
+#define ELS_ELS_CONFIG_ECVFY_SUP(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_ECVFY_SUP_SHIFT)) & ELS_ELS_CONFIG_ECVFY_SUP_MASK)
+
+#define ELS_ELS_CONFIG_ECKXCH_SUP_MASK           (0x10U)
+#define ELS_ELS_CONFIG_ECKXCH_SUP_SHIFT          (4U)
+/*! ECKXCH_SUP - dhkey_xch command is supported */
+#define ELS_ELS_CONFIG_ECKXCH_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_ECKXCH_SUP_SHIFT)) & ELS_ELS_CONFIG_ECKXCH_SUP_MASK)
+
+#define ELS_ELS_CONFIG_KEYGEN_SUP_MASK           (0x20U)
+#define ELS_ELS_CONFIG_KEYGEN_SUP_SHIFT          (5U)
+/*! KEYGEN_SUP - keygen command is supported */
+#define ELS_ELS_CONFIG_KEYGEN_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KEYGEN_SUP_SHIFT)) & ELS_ELS_CONFIG_KEYGEN_SUP_MASK)
+
+#define ELS_ELS_CONFIG_KEYIN_SUP_MASK            (0x40U)
+#define ELS_ELS_CONFIG_KEYIN_SUP_SHIFT           (6U)
+/*! KEYIN_SUP - keyin command is supported */
+#define ELS_ELS_CONFIG_KEYIN_SUP(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KEYIN_SUP_SHIFT)) & ELS_ELS_CONFIG_KEYIN_SUP_MASK)
+
+#define ELS_ELS_CONFIG_KEYOUT_SUP_MASK           (0x80U)
+#define ELS_ELS_CONFIG_KEYOUT_SUP_SHIFT          (7U)
+/*! KEYOUT_SUP - keyout command is supported */
+#define ELS_ELS_CONFIG_KEYOUT_SUP(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KEYOUT_SUP_SHIFT)) & ELS_ELS_CONFIG_KEYOUT_SUP_MASK)
+
+#define ELS_ELS_CONFIG_KDELETE_SUP_MASK          (0x100U)
+#define ELS_ELS_CONFIG_KDELETE_SUP_SHIFT         (8U)
+/*! KDELETE_SUP - kdelete command is supported */
+#define ELS_ELS_CONFIG_KDELETE_SUP(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KDELETE_SUP_SHIFT)) & ELS_ELS_CONFIG_KDELETE_SUP_MASK)
+
+#define ELS_ELS_CONFIG_KEYPROV_SUP_MASK          (0x200U)
+#define ELS_ELS_CONFIG_KEYPROV_SUP_SHIFT         (9U)
+/*! KEYPROV_SUP - keyprov command is supported */
+#define ELS_ELS_CONFIG_KEYPROV_SUP(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_KEYPROV_SUP_SHIFT)) & ELS_ELS_CONFIG_KEYPROV_SUP_MASK)
+
+#define ELS_ELS_CONFIG_CKDF_SUP_MASK             (0x400U)
+#define ELS_ELS_CONFIG_CKDF_SUP_SHIFT            (10U)
+/*! CKDF_SUP - ckdf command is supported */
+#define ELS_ELS_CONFIG_CKDF_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_CKDF_SUP_SHIFT)) & ELS_ELS_CONFIG_CKDF_SUP_MASK)
+
+#define ELS_ELS_CONFIG_HKDF_SUP_MASK             (0x800U)
+#define ELS_ELS_CONFIG_HKDF_SUP_SHIFT            (11U)
+/*! HKDF_SUP - hkdf command is supported */
+#define ELS_ELS_CONFIG_HKDF_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_HKDF_SUP_SHIFT)) & ELS_ELS_CONFIG_HKDF_SUP_MASK)
+
+#define ELS_ELS_CONFIG_TLS_INIT_SUP_MASK         (0x1000U)
+#define ELS_ELS_CONFIG_TLS_INIT_SUP_SHIFT        (12U)
+/*! TLS_INIT_SUP - tls_init command is supported */
+#define ELS_ELS_CONFIG_TLS_INIT_SUP(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_TLS_INIT_SUP_SHIFT)) & ELS_ELS_CONFIG_TLS_INIT_SUP_MASK)
+
+#define ELS_ELS_CONFIG_HASH_SUP_MASK             (0x2000U)
+#define ELS_ELS_CONFIG_HASH_SUP_SHIFT            (13U)
+/*! HASH_SUP - hash command is supported */
+#define ELS_ELS_CONFIG_HASH_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_HASH_SUP_SHIFT)) & ELS_ELS_CONFIG_HASH_SUP_MASK)
+
+#define ELS_ELS_CONFIG_HMAC_SUP_MASK             (0x4000U)
+#define ELS_ELS_CONFIG_HMAC_SUP_SHIFT            (14U)
+/*! HMAC_SUP - hmac command is supported */
+#define ELS_ELS_CONFIG_HMAC_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_HMAC_SUP_SHIFT)) & ELS_ELS_CONFIG_HMAC_SUP_MASK)
+
+#define ELS_ELS_CONFIG_CMAC_SUP_MASK             (0x8000U)
+#define ELS_ELS_CONFIG_CMAC_SUP_SHIFT            (15U)
+/*! CMAC_SUP - cmac command is supported */
+#define ELS_ELS_CONFIG_CMAC_SUP(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_CMAC_SUP_SHIFT)) & ELS_ELS_CONFIG_CMAC_SUP_MASK)
+
+#define ELS_ELS_CONFIG_DRBG_REQ_SUP_MASK         (0x10000U)
+#define ELS_ELS_CONFIG_DRBG_REQ_SUP_SHIFT        (16U)
+/*! DRBG_REQ_SUP - drbg_req command is supported */
+#define ELS_ELS_CONFIG_DRBG_REQ_SUP(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DRBG_REQ_SUP_SHIFT)) & ELS_ELS_CONFIG_DRBG_REQ_SUP_MASK)
+
+#define ELS_ELS_CONFIG_DRBG_TEST_SUP_MASK        (0x20000U)
+#define ELS_ELS_CONFIG_DRBG_TEST_SUP_SHIFT       (17U)
+/*! DRBG_TEST_SUP - drbg_test command is supported */
+#define ELS_ELS_CONFIG_DRBG_TEST_SUP(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DRBG_TEST_SUP_SHIFT)) & ELS_ELS_CONFIG_DRBG_TEST_SUP_MASK)
+
+#define ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_MASK   (0x40000U)
+#define ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_SHIFT  (18U)
+/*! DTRNG_CFG_LOAD_SUP - dtrng_cfg_load command is supported */
+#define ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP(x)     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_SHIFT)) & ELS_ELS_CONFIG_DTRNG_CFG_LOAD_SUP_MASK)
+
+#define ELS_ELS_CONFIG_DTRNG_EVAL_SUP_MASK       (0x80000U)
+#define ELS_ELS_CONFIG_DTRNG_EVAL_SUP_SHIFT      (19U)
+/*! DTRNG_EVAL_SUP - dtrng_eval command is supported */
+#define ELS_ELS_CONFIG_DTRNG_EVAL_SUP(x)         (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_DTRNG_EVAL_SUP_SHIFT)) & ELS_ELS_CONFIG_DTRNG_EVAL_SUP_MASK)
+
+#define ELS_ELS_CONFIG_GDET_CFG_LOAD_SUP_MASK    (0x100000U)
+#define ELS_ELS_CONFIG_GDET_CFG_LOAD_SUP_SHIFT   (20U)
+/*! GDET_CFG_LOAD_SUP - gdet_cfg_load command is supported */
+#define ELS_ELS_CONFIG_GDET_CFG_LOAD_SUP(x)      (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_GDET_CFG_LOAD_SUP_SHIFT)) & ELS_ELS_CONFIG_GDET_CFG_LOAD_SUP_MASK)
+
+#define ELS_ELS_CONFIG_GDET_TRIM_SUP_MASK        (0x200000U)
+#define ELS_ELS_CONFIG_GDET_TRIM_SUP_SHIFT       (21U)
+/*! GDET_TRIM_SUP - gdet_trim command is supported */
+#define ELS_ELS_CONFIG_GDET_TRIM_SUP(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_GDET_TRIM_SUP_SHIFT)) & ELS_ELS_CONFIG_GDET_TRIM_SUP_MASK)
+
+#define ELS_ELS_CONFIG_CONFIG_RSVD_MASK          (0xFFC00000U)
+#define ELS_ELS_CONFIG_CONFIG_RSVD_SHIFT         (22U)
+/*! CONFIG_RSVD - reserved */
+#define ELS_ELS_CONFIG_CONFIG_RSVD(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_CONFIG_CONFIG_RSVD_SHIFT)) & ELS_ELS_CONFIG_CONFIG_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_PRNG_DATOUT - PRNG SW read out register */
+/*! @{ */
+
+#define ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK     (0xFFFFFFFFU)
+#define ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT    (0U)
+/*! PRNG_DATOUT - 32-bit wide pseudo-random number */
+#define ELS_ELS_PRNG_DATOUT_PRNG_DATOUT(x)       (((uint32_t)(((uint32_t)(x)) << ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & ELS_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK)
+/*! @} */
+
+/*! @name ELS_GDET_EVTCNT - ELS GDET Event Counter */
+/*! @{ */
+
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_MASK     (0xFFU)
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_SHIFT    (0U)
+/*! GDET_EVTCNT - Number of glitch event recorded */
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT(x)       (((uint32_t)(((uint32_t)(x)) << ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_SHIFT)) & ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_MASK)
+
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE_MASK (0x100U)
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE_SHIFT (8U)
+/*! GDET_EVTCNT_CLR_DONE - The GDET event counter has been cleared */
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE_SHIFT)) & ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE_MASK)
+
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_RSVD_MASK (0xFFFFFE00U)
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_RSVD_SHIFT (9U)
+/*! GDET_EVTCNT_RSVD - reserved */
+#define ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_RSVD(x)  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_RSVD_SHIFT)) & ELS_ELS_GDET_EVTCNT_GDET_EVTCNT_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_GDET_EVTCNT_CLR - ELS GDET Event Counter Clear */
+/*! @{ */
+
+#define ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_MASK (0x1U)
+#define ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_SHIFT (0U)
+/*! GDET_EVTCNT_CLR - 1=clear GDET event counter clear */
+#define ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_SHIFT)) & ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_MASK)
+
+#define ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_RSVD_MASK (0xFFFFFFFEU)
+#define ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_RSVD_SHIFT (1U)
+/*! GDET_EVTCNT_CLR_RSVD - reserved */
+#define ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_RSVD_SHIFT)) & ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_STATUS - ELS SHA2 Status Register */
+/*! @{ */
+
+#define ELS_ELS_SHA2_STATUS_SHA2_BUSY_MASK       (0x1U)
+#define ELS_ELS_SHA2_STATUS_SHA2_BUSY_SHIFT      (0U)
+#define ELS_ELS_SHA2_STATUS_SHA2_BUSY(x)         (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_STATUS_SHA2_BUSY_SHIFT)) & ELS_ELS_SHA2_STATUS_SHA2_BUSY_MASK)
+
+#define ELS_ELS_SHA2_STATUS_STATUS_RSVD1_MASK    (0xFFFFFFFEU)
+#define ELS_ELS_SHA2_STATUS_STATUS_RSVD1_SHIFT   (1U)
+/*! STATUS_RSVD1 - reserved */
+#define ELS_ELS_SHA2_STATUS_STATUS_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_STATUS_STATUS_RSVD1_SHIFT)) & ELS_ELS_SHA2_STATUS_STATUS_RSVD1_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_CTRL - SHA2 Control register */
+/*! @{ */
+
+#define ELS_ELS_SHA2_CTRL_SHA2_START_MASK        (0x1U)
+#define ELS_ELS_SHA2_CTRL_SHA2_START_SHIFT       (0U)
+/*! SHA2_START - Write to 1 to Init the SHA2 Module */
+#define ELS_ELS_SHA2_CTRL_SHA2_START(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_START_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_START_MASK)
+
+#define ELS_ELS_SHA2_CTRL_SHA2_RST_MASK          (0x2U)
+#define ELS_ELS_SHA2_CTRL_SHA2_RST_SHIFT         (1U)
+/*! SHA2_RST - Write to 1 to Reset a SHA2 operation */
+#define ELS_ELS_SHA2_CTRL_SHA2_RST(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_RST_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_RST_MASK)
+
+#define ELS_ELS_SHA2_CTRL_SHA2_INIT_MASK         (0x4U)
+#define ELS_ELS_SHA2_CTRL_SHA2_INIT_SHIFT        (2U)
+/*! SHA2_INIT - Write to 1 to Init the SHA2 Kernel */
+#define ELS_ELS_SHA2_CTRL_SHA2_INIT(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_INIT_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_INIT_MASK)
+
+#define ELS_ELS_SHA2_CTRL_SHA2_LOAD_MASK         (0x8U)
+#define ELS_ELS_SHA2_CTRL_SHA2_LOAD_SHIFT        (3U)
+/*! SHA2_LOAD - Write to 1 to Load the SHA2 Kernel */
+#define ELS_ELS_SHA2_CTRL_SHA2_LOAD(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_LOAD_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_LOAD_MASK)
+
+#define ELS_ELS_SHA2_CTRL_SHA2_MODE_MASK         (0x30U)
+#define ELS_ELS_SHA2_CTRL_SHA2_MODE_SHIFT        (4U)
+/*! SHA2_MODE - SHA2 MODE:; 2'b11 - SHA512; 2'b10 - SHA384; 2'b01 - SHA224; 2'b00 - SHA256 */
+#define ELS_ELS_SHA2_CTRL_SHA2_MODE(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_MODE_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_MODE_MASK)
+
+#define ELS_ELS_SHA2_CTRL_CTRL_RSVD1_MASK        (0x1C0U)
+#define ELS_ELS_SHA2_CTRL_CTRL_RSVD1_SHIFT       (6U)
+/*! CTRL_RSVD1 - r-eserved */
+#define ELS_ELS_SHA2_CTRL_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_CTRL_RSVD1_SHIFT)) & ELS_ELS_SHA2_CTRL_CTRL_RSVD1_MASK)
+
+#define ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_MASK   (0x200U)
+#define ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_SHIFT  (9U)
+/*! SHA2_BYTE_ORDER - Write to 1 to Reverse byte endianess */
+#define ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER(x)     (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_SHIFT)) & ELS_ELS_SHA2_CTRL_SHA2_BYTE_ORDER_MASK)
+
+#define ELS_ELS_SHA2_CTRL_CTRL_RSVD_MASK         (0xFFFFFC00U)
+#define ELS_ELS_SHA2_CTRL_CTRL_RSVD_SHIFT        (10U)
+/*! CTRL_RSVD - r-eserved */
+#define ELS_ELS_SHA2_CTRL_CTRL_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_CTRL_CTRL_RSVD_SHIFT)) & ELS_ELS_SHA2_CTRL_CTRL_RSVD_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DIN - ELS SHA_DATA IN Register 0 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DIN_SHA_DATIN_MASK          (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DIN_SHA_DATIN_SHIFT         (0U)
+/*! SHA_DATIN - Output ELS_SHA_DATIN from ELS Application being executed */
+#define ELS_ELS_SHA2_DIN_SHA_DATIN(x)            (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DIN_SHA_DATIN_SHIFT)) & ELS_ELS_SHA2_DIN_SHA_DATIN_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT0 - ELS ELS_SHA_DATA Out Register 0 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT0_SHA_DATA0_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT0_SHA_DATA0_SHIFT       (0U)
+/*! SHA_DATA0 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT0_SHA_DATA0(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT0_SHA_DATA0_SHIFT)) & ELS_ELS_SHA2_DOUT0_SHA_DATA0_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT1 - ELS SHA_DATA Out Register 1 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT1_SHA_DATA1_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT1_SHA_DATA1_SHIFT       (0U)
+/*! SHA_DATA1 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT1_SHA_DATA1(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT1_SHA_DATA1_SHIFT)) & ELS_ELS_SHA2_DOUT1_SHA_DATA1_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT2 - ELS SHA_DATA Out Register 2 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT2_SHA_DATA2_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT2_SHA_DATA2_SHIFT       (0U)
+/*! SHA_DATA2 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT2_SHA_DATA2(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT2_SHA_DATA2_SHIFT)) & ELS_ELS_SHA2_DOUT2_SHA_DATA2_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT3 - ELS SHA_DATA Out Register 3 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT3_SHA_DATA3_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT3_SHA_DATA3_SHIFT       (0U)
+/*! SHA_DATA3 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT3_SHA_DATA3(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT3_SHA_DATA3_SHIFT)) & ELS_ELS_SHA2_DOUT3_SHA_DATA3_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT4 - ELS SHA_DATA Out Register 4 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT4_SHA_DATA4_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT4_SHA_DATA4_SHIFT       (0U)
+/*! SHA_DATA4 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT4_SHA_DATA4(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT4_SHA_DATA4_SHIFT)) & ELS_ELS_SHA2_DOUT4_SHA_DATA4_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT5 - ELS SHA_DATA Out Register 5 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT5_SHA_DATA5_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT5_SHA_DATA5_SHIFT       (0U)
+/*! SHA_DATA5 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT5_SHA_DATA5(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT5_SHA_DATA5_SHIFT)) & ELS_ELS_SHA2_DOUT5_SHA_DATA5_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT6 - ELS SHA_DATA Out Register 6 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT6_SHA_DATA6_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT6_SHA_DATA6_SHIFT       (0U)
+/*! SHA_DATA6 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT6_SHA_DATA6(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT6_SHA_DATA6_SHIFT)) & ELS_ELS_SHA2_DOUT6_SHA_DATA6_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT7 - ELS SHA_DATA Out Register 7 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT7_SHA_DATA7_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT7_SHA_DATA7_SHIFT       (0U)
+/*! SHA_DATA7 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT7_SHA_DATA7(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT7_SHA_DATA7_SHIFT)) & ELS_ELS_SHA2_DOUT7_SHA_DATA7_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT8 - ELS ELS_SHA_DATA Out Register 8 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT8_SHA_DATA8_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT8_SHA_DATA8_SHIFT       (0U)
+/*! SHA_DATA8 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT8_SHA_DATA8(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT8_SHA_DATA8_SHIFT)) & ELS_ELS_SHA2_DOUT8_SHA_DATA8_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT9 - ELS SHA_DATA Out Register 9 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT9_SHA_DATA9_MASK        (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT9_SHA_DATA9_SHIFT       (0U)
+/*! SHA_DATA9 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT9_SHA_DATA9(x)          (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT9_SHA_DATA9_SHIFT)) & ELS_ELS_SHA2_DOUT9_SHA_DATA9_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT10 - ELS SHA_DATA Out Register 10 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT10_SHA_DATA10_MASK      (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT10_SHA_DATA10_SHIFT     (0U)
+/*! SHA_DATA10 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT10_SHA_DATA10(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT10_SHA_DATA10_SHIFT)) & ELS_ELS_SHA2_DOUT10_SHA_DATA10_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT11 - ELS SHA_DATA Out Register 11 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT11_SHA_DATA11_MASK      (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT11_SHA_DATA11_SHIFT     (0U)
+/*! SHA_DATA11 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT11_SHA_DATA11(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT11_SHA_DATA11_SHIFT)) & ELS_ELS_SHA2_DOUT11_SHA_DATA11_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT12 - ELS SHA_DATA Out Register 12 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT12_SHA_DATA12_MASK      (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT12_SHA_DATA12_SHIFT     (0U)
+/*! SHA_DATA12 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT12_SHA_DATA12(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT12_SHA_DATA12_SHIFT)) & ELS_ELS_SHA2_DOUT12_SHA_DATA12_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT13 - ELS SHA_DATA Out Register 13 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT13_SHA_DATA13_MASK      (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT13_SHA_DATA13_SHIFT     (0U)
+/*! SHA_DATA13 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT13_SHA_DATA13(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT13_SHA_DATA13_SHIFT)) & ELS_ELS_SHA2_DOUT13_SHA_DATA13_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT14 - ELS SHA_DATA Out Register 14 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT14_SHA_DATA14_MASK      (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT14_SHA_DATA14_SHIFT     (0U)
+/*! SHA_DATA14 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT14_SHA_DATA14(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT14_SHA_DATA14_SHIFT)) & ELS_ELS_SHA2_DOUT14_SHA_DATA14_MASK)
+/*! @} */
+
+/*! @name ELS_SHA2_DOUT15 - ELS SHA_DATA Out Register 15 */
+/*! @{ */
+
+#define ELS_ELS_SHA2_DOUT15_SHA_DATA15_MASK      (0xFFFFFFFFU)
+#define ELS_ELS_SHA2_DOUT15_SHA_DATA15_SHIFT     (0U)
+/*! SHA_DATA15 - Output SHA_DATA from ELS Application being executed */
+#define ELS_ELS_SHA2_DOUT15_SHA_DATA15(x)        (((uint32_t)(((uint32_t)(x)) << ELS_ELS_SHA2_DOUT15_SHA_DATA15_SHIFT)) & ELS_ELS_SHA2_DOUT15_SHA_DATA15_MASK)
+/*! @} */
+
+/*! @name ELS_KS0 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS0_KS0_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS0_KS0_KSIZE_SHIFT              (0U)
+/*! KS0_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS0_KS0_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_KSIZE_SHIFT)) & ELS_ELS_KS0_KS0_KSIZE_MASK)
+
+#define ELS_ELS_KS0_KS0_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS0_KS0_RSVD0_SHIFT              (1U)
+/*! KS0_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS0_KS0_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_RSVD0_SHIFT)) & ELS_ELS_KS0_KS0_RSVD0_MASK)
+
+#define ELS_ELS_KS0_KS0_KACT_MASK                (0x20U)
+#define ELS_ELS_KS0_KS0_KACT_SHIFT               (5U)
+/*! KS0_KACT - Key is active */
+#define ELS_ELS_KS0_KS0_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_KACT_SHIFT)) & ELS_ELS_KS0_KS0_KACT_MASK)
+
+#define ELS_ELS_KS0_KS0_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS0_KS0_KBASE_SHIFT              (6U)
+/*! KS0_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS0_KS0_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_KBASE_SHIFT)) & ELS_ELS_KS0_KS0_KBASE_MASK)
+
+#define ELS_ELS_KS0_KS0_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS0_KS0_FGP_SHIFT                (7U)
+/*! KS0_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS0_KS0_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_FGP_SHIFT)) & ELS_ELS_KS0_KS0_FGP_MASK)
+
+#define ELS_ELS_KS0_KS0_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS0_KS0_FRTN_SHIFT               (8U)
+/*! KS0_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS0_KS0_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_FRTN_SHIFT)) & ELS_ELS_KS0_KS0_FRTN_MASK)
+
+#define ELS_ELS_KS0_KS0_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS0_KS0_FHWO_SHIFT               (9U)
+/*! KS0_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS0_KS0_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_FHWO_SHIFT)) & ELS_ELS_KS0_KS0_FHWO_MASK)
+
+#define ELS_ELS_KS0_KS0_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS0_KS0_RSVD1_SHIFT              (10U)
+/*! KS0_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS0_KS0_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_RSVD1_SHIFT)) & ELS_ELS_KS0_KS0_RSVD1_MASK)
+
+#define ELS_ELS_KS0_KS0_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS0_KS0_UCMAC_SHIFT              (13U)
+/*! KS0_UCMAC - CMAC key */
+#define ELS_ELS_KS0_KS0_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UCMAC_SHIFT)) & ELS_ELS_KS0_KS0_UCMAC_MASK)
+
+#define ELS_ELS_KS0_KS0_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS0_KS0_UKSK_SHIFT               (14U)
+/*! KS0_UKSK - KSK key */
+#define ELS_ELS_KS0_KS0_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKSK_SHIFT)) & ELS_ELS_KS0_KS0_UKSK_MASK)
+
+#define ELS_ELS_KS0_KS0_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS0_KS0_URTF_SHIFT               (15U)
+/*! KS0_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS0_KS0_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_URTF_SHIFT)) & ELS_ELS_KS0_KS0_URTF_MASK)
+
+#define ELS_ELS_KS0_KS0_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS0_KS0_UCKDF_SHIFT              (16U)
+/*! KS0_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS0_KS0_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UCKDF_SHIFT)) & ELS_ELS_KS0_KS0_UCKDF_MASK)
+
+#define ELS_ELS_KS0_KS0_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS0_KS0_UHKDF_SHIFT              (17U)
+/*! KS0_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS0_KS0_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UHKDF_SHIFT)) & ELS_ELS_KS0_KS0_UHKDF_MASK)
+
+#define ELS_ELS_KS0_KS0_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS0_KS0_UECSG_SHIFT              (18U)
+/*! KS0_UECSG - Ecc signing key */
+#define ELS_ELS_KS0_KS0_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UECSG_SHIFT)) & ELS_ELS_KS0_KS0_UECSG_MASK)
+
+#define ELS_ELS_KS0_KS0_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS0_KS0_UECDH_SHIFT              (19U)
+/*! KS0_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS0_KS0_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UECDH_SHIFT)) & ELS_ELS_KS0_KS0_UECDH_MASK)
+
+#define ELS_ELS_KS0_KS0_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS0_KS0_UAES_SHIFT               (20U)
+/*! KS0_UAES - Aes key */
+#define ELS_ELS_KS0_KS0_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UAES_SHIFT)) & ELS_ELS_KS0_KS0_UAES_MASK)
+
+#define ELS_ELS_KS0_KS0_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS0_KS0_UHMAC_SHIFT              (21U)
+/*! KS0_UHMAC - Hmac key */
+#define ELS_ELS_KS0_KS0_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UHMAC_SHIFT)) & ELS_ELS_KS0_KS0_UHMAC_MASK)
+
+#define ELS_ELS_KS0_KS0_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS0_KS0_UKWK_SHIFT               (22U)
+/*! KS0_UKWK - Key wrapping key */
+#define ELS_ELS_KS0_KS0_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKWK_SHIFT)) & ELS_ELS_KS0_KS0_UKWK_MASK)
+
+#define ELS_ELS_KS0_KS0_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS0_KS0_UKUOK_SHIFT              (23U)
+/*! KS0_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS0_KS0_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKUOK_SHIFT)) & ELS_ELS_KS0_KS0_UKUOK_MASK)
+
+#define ELS_ELS_KS0_KS0_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS0_KS0_UTLSPMS_SHIFT            (24U)
+/*! KS0_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS0_KS0_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UTLSPMS_SHIFT)) & ELS_ELS_KS0_KS0_UTLSPMS_MASK)
+
+#define ELS_ELS_KS0_KS0_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS0_KS0_UTLSMS_SHIFT             (25U)
+/*! KS0_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS0_KS0_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UTLSMS_SHIFT)) & ELS_ELS_KS0_KS0_UTLSMS_MASK)
+
+#define ELS_ELS_KS0_KS0_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS0_KS0_UKGSRC_SHIFT             (26U)
+/*! KS0_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS0_KS0_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UKGSRC_SHIFT)) & ELS_ELS_KS0_KS0_UKGSRC_MASK)
+
+#define ELS_ELS_KS0_KS0_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS0_KS0_UHWO_SHIFT               (27U)
+/*! KS0_UHWO - Hardware out key */
+#define ELS_ELS_KS0_KS0_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UHWO_SHIFT)) & ELS_ELS_KS0_KS0_UHWO_MASK)
+
+#define ELS_ELS_KS0_KS0_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS0_KS0_UWRPOK_SHIFT             (28U)
+/*! KS0_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS0_KS0_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UWRPOK_SHIFT)) & ELS_ELS_KS0_KS0_UWRPOK_MASK)
+
+#define ELS_ELS_KS0_KS0_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS0_KS0_UDUK_SHIFT               (29U)
+/*! KS0_UDUK - Device Unique Key */
+#define ELS_ELS_KS0_KS0_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UDUK_SHIFT)) & ELS_ELS_KS0_KS0_UDUK_MASK)
+
+#define ELS_ELS_KS0_KS0_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS0_KS0_UPPROT_SHIFT             (30U)
+/*! KS0_UPPROT - Priviledge level */
+#define ELS_ELS_KS0_KS0_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS0_KS0_UPPROT_SHIFT)) & ELS_ELS_KS0_KS0_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS1 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS1_KS1_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS1_KS1_KSIZE_SHIFT              (0U)
+/*! KS1_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS1_KS1_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_KSIZE_SHIFT)) & ELS_ELS_KS1_KS1_KSIZE_MASK)
+
+#define ELS_ELS_KS1_KS1_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS1_KS1_RSVD0_SHIFT              (1U)
+/*! KS1_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS1_KS1_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_RSVD0_SHIFT)) & ELS_ELS_KS1_KS1_RSVD0_MASK)
+
+#define ELS_ELS_KS1_KS1_KACT_MASK                (0x20U)
+#define ELS_ELS_KS1_KS1_KACT_SHIFT               (5U)
+/*! KS1_KACT - Key is active */
+#define ELS_ELS_KS1_KS1_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_KACT_SHIFT)) & ELS_ELS_KS1_KS1_KACT_MASK)
+
+#define ELS_ELS_KS1_KS1_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS1_KS1_KBASE_SHIFT              (6U)
+/*! KS1_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS1_KS1_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_KBASE_SHIFT)) & ELS_ELS_KS1_KS1_KBASE_MASK)
+
+#define ELS_ELS_KS1_KS1_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS1_KS1_FGP_SHIFT                (7U)
+/*! KS1_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS1_KS1_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_FGP_SHIFT)) & ELS_ELS_KS1_KS1_FGP_MASK)
+
+#define ELS_ELS_KS1_KS1_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS1_KS1_FRTN_SHIFT               (8U)
+/*! KS1_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS1_KS1_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_FRTN_SHIFT)) & ELS_ELS_KS1_KS1_FRTN_MASK)
+
+#define ELS_ELS_KS1_KS1_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS1_KS1_FHWO_SHIFT               (9U)
+/*! KS1_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS1_KS1_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_FHWO_SHIFT)) & ELS_ELS_KS1_KS1_FHWO_MASK)
+
+#define ELS_ELS_KS1_KS1_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS1_KS1_RSVD1_SHIFT              (10U)
+/*! KS1_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS1_KS1_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_RSVD1_SHIFT)) & ELS_ELS_KS1_KS1_RSVD1_MASK)
+
+#define ELS_ELS_KS1_KS1_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS1_KS1_UCMAC_SHIFT              (13U)
+/*! KS1_UCMAC - CMAC key */
+#define ELS_ELS_KS1_KS1_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UCMAC_SHIFT)) & ELS_ELS_KS1_KS1_UCMAC_MASK)
+
+#define ELS_ELS_KS1_KS1_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS1_KS1_UKSK_SHIFT               (14U)
+/*! KS1_UKSK - KSK key */
+#define ELS_ELS_KS1_KS1_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKSK_SHIFT)) & ELS_ELS_KS1_KS1_UKSK_MASK)
+
+#define ELS_ELS_KS1_KS1_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS1_KS1_URTF_SHIFT               (15U)
+/*! KS1_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS1_KS1_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_URTF_SHIFT)) & ELS_ELS_KS1_KS1_URTF_MASK)
+
+#define ELS_ELS_KS1_KS1_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS1_KS1_UCKDF_SHIFT              (16U)
+/*! KS1_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS1_KS1_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UCKDF_SHIFT)) & ELS_ELS_KS1_KS1_UCKDF_MASK)
+
+#define ELS_ELS_KS1_KS1_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS1_KS1_UHKDF_SHIFT              (17U)
+/*! KS1_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS1_KS1_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UHKDF_SHIFT)) & ELS_ELS_KS1_KS1_UHKDF_MASK)
+
+#define ELS_ELS_KS1_KS1_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS1_KS1_UECSG_SHIFT              (18U)
+/*! KS1_UECSG - Ecc signing key */
+#define ELS_ELS_KS1_KS1_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UECSG_SHIFT)) & ELS_ELS_KS1_KS1_UECSG_MASK)
+
+#define ELS_ELS_KS1_KS1_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS1_KS1_UECDH_SHIFT              (19U)
+/*! KS1_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS1_KS1_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UECDH_SHIFT)) & ELS_ELS_KS1_KS1_UECDH_MASK)
+
+#define ELS_ELS_KS1_KS1_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS1_KS1_UAES_SHIFT               (20U)
+/*! KS1_UAES - Aes key */
+#define ELS_ELS_KS1_KS1_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UAES_SHIFT)) & ELS_ELS_KS1_KS1_UAES_MASK)
+
+#define ELS_ELS_KS1_KS1_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS1_KS1_UHMAC_SHIFT              (21U)
+/*! KS1_UHMAC - Hmac key */
+#define ELS_ELS_KS1_KS1_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UHMAC_SHIFT)) & ELS_ELS_KS1_KS1_UHMAC_MASK)
+
+#define ELS_ELS_KS1_KS1_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS1_KS1_UKWK_SHIFT               (22U)
+/*! KS1_UKWK - Key wrapping key */
+#define ELS_ELS_KS1_KS1_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKWK_SHIFT)) & ELS_ELS_KS1_KS1_UKWK_MASK)
+
+#define ELS_ELS_KS1_KS1_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS1_KS1_UKUOK_SHIFT              (23U)
+/*! KS1_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS1_KS1_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKUOK_SHIFT)) & ELS_ELS_KS1_KS1_UKUOK_MASK)
+
+#define ELS_ELS_KS1_KS1_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS1_KS1_UTLSPMS_SHIFT            (24U)
+/*! KS1_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS1_KS1_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UTLSPMS_SHIFT)) & ELS_ELS_KS1_KS1_UTLSPMS_MASK)
+
+#define ELS_ELS_KS1_KS1_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS1_KS1_UTLSMS_SHIFT             (25U)
+/*! KS1_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS1_KS1_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UTLSMS_SHIFT)) & ELS_ELS_KS1_KS1_UTLSMS_MASK)
+
+#define ELS_ELS_KS1_KS1_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS1_KS1_UKGSRC_SHIFT             (26U)
+/*! KS1_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS1_KS1_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UKGSRC_SHIFT)) & ELS_ELS_KS1_KS1_UKGSRC_MASK)
+
+#define ELS_ELS_KS1_KS1_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS1_KS1_UHWO_SHIFT               (27U)
+/*! KS1_UHWO - Hardware out key */
+#define ELS_ELS_KS1_KS1_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UHWO_SHIFT)) & ELS_ELS_KS1_KS1_UHWO_MASK)
+
+#define ELS_ELS_KS1_KS1_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS1_KS1_UWRPOK_SHIFT             (28U)
+/*! KS1_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS1_KS1_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UWRPOK_SHIFT)) & ELS_ELS_KS1_KS1_UWRPOK_MASK)
+
+#define ELS_ELS_KS1_KS1_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS1_KS1_UDUK_SHIFT               (29U)
+/*! KS1_UDUK - Device Unique Key */
+#define ELS_ELS_KS1_KS1_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UDUK_SHIFT)) & ELS_ELS_KS1_KS1_UDUK_MASK)
+
+#define ELS_ELS_KS1_KS1_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS1_KS1_UPPROT_SHIFT             (30U)
+/*! KS1_UPPROT - Priviledge level */
+#define ELS_ELS_KS1_KS1_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS1_KS1_UPPROT_SHIFT)) & ELS_ELS_KS1_KS1_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS2 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS2_KS2_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS2_KS2_KSIZE_SHIFT              (0U)
+/*! KS2_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS2_KS2_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_KSIZE_SHIFT)) & ELS_ELS_KS2_KS2_KSIZE_MASK)
+
+#define ELS_ELS_KS2_KS2_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS2_KS2_RSVD0_SHIFT              (1U)
+/*! KS2_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS2_KS2_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_RSVD0_SHIFT)) & ELS_ELS_KS2_KS2_RSVD0_MASK)
+
+#define ELS_ELS_KS2_KS2_KACT_MASK                (0x20U)
+#define ELS_ELS_KS2_KS2_KACT_SHIFT               (5U)
+/*! KS2_KACT - Key is active */
+#define ELS_ELS_KS2_KS2_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_KACT_SHIFT)) & ELS_ELS_KS2_KS2_KACT_MASK)
+
+#define ELS_ELS_KS2_KS2_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS2_KS2_KBASE_SHIFT              (6U)
+/*! KS2_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS2_KS2_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_KBASE_SHIFT)) & ELS_ELS_KS2_KS2_KBASE_MASK)
+
+#define ELS_ELS_KS2_KS2_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS2_KS2_FGP_SHIFT                (7U)
+/*! KS2_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS2_KS2_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_FGP_SHIFT)) & ELS_ELS_KS2_KS2_FGP_MASK)
+
+#define ELS_ELS_KS2_KS2_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS2_KS2_FRTN_SHIFT               (8U)
+/*! KS2_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS2_KS2_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_FRTN_SHIFT)) & ELS_ELS_KS2_KS2_FRTN_MASK)
+
+#define ELS_ELS_KS2_KS2_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS2_KS2_FHWO_SHIFT               (9U)
+/*! KS2_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS2_KS2_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_FHWO_SHIFT)) & ELS_ELS_KS2_KS2_FHWO_MASK)
+
+#define ELS_ELS_KS2_KS2_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS2_KS2_RSVD1_SHIFT              (10U)
+/*! KS2_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS2_KS2_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_RSVD1_SHIFT)) & ELS_ELS_KS2_KS2_RSVD1_MASK)
+
+#define ELS_ELS_KS2_KS2_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS2_KS2_UCMAC_SHIFT              (13U)
+/*! KS2_UCMAC - CMAC key */
+#define ELS_ELS_KS2_KS2_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UCMAC_SHIFT)) & ELS_ELS_KS2_KS2_UCMAC_MASK)
+
+#define ELS_ELS_KS2_KS2_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS2_KS2_UKSK_SHIFT               (14U)
+/*! KS2_UKSK - KSK key */
+#define ELS_ELS_KS2_KS2_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKSK_SHIFT)) & ELS_ELS_KS2_KS2_UKSK_MASK)
+
+#define ELS_ELS_KS2_KS2_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS2_KS2_URTF_SHIFT               (15U)
+/*! KS2_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS2_KS2_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_URTF_SHIFT)) & ELS_ELS_KS2_KS2_URTF_MASK)
+
+#define ELS_ELS_KS2_KS2_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS2_KS2_UCKDF_SHIFT              (16U)
+/*! KS2_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS2_KS2_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UCKDF_SHIFT)) & ELS_ELS_KS2_KS2_UCKDF_MASK)
+
+#define ELS_ELS_KS2_KS2_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS2_KS2_UHKDF_SHIFT              (17U)
+/*! KS2_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS2_KS2_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UHKDF_SHIFT)) & ELS_ELS_KS2_KS2_UHKDF_MASK)
+
+#define ELS_ELS_KS2_KS2_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS2_KS2_UECSG_SHIFT              (18U)
+/*! KS2_UECSG - Ecc signing key */
+#define ELS_ELS_KS2_KS2_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UECSG_SHIFT)) & ELS_ELS_KS2_KS2_UECSG_MASK)
+
+#define ELS_ELS_KS2_KS2_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS2_KS2_UECDH_SHIFT              (19U)
+/*! KS2_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS2_KS2_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UECDH_SHIFT)) & ELS_ELS_KS2_KS2_UECDH_MASK)
+
+#define ELS_ELS_KS2_KS2_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS2_KS2_UAES_SHIFT               (20U)
+/*! KS2_UAES - Aes key */
+#define ELS_ELS_KS2_KS2_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UAES_SHIFT)) & ELS_ELS_KS2_KS2_UAES_MASK)
+
+#define ELS_ELS_KS2_KS2_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS2_KS2_UHMAC_SHIFT              (21U)
+/*! KS2_UHMAC - Hmac key */
+#define ELS_ELS_KS2_KS2_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UHMAC_SHIFT)) & ELS_ELS_KS2_KS2_UHMAC_MASK)
+
+#define ELS_ELS_KS2_KS2_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS2_KS2_UKWK_SHIFT               (22U)
+/*! KS2_UKWK - Key wrapping key */
+#define ELS_ELS_KS2_KS2_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKWK_SHIFT)) & ELS_ELS_KS2_KS2_UKWK_MASK)
+
+#define ELS_ELS_KS2_KS2_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS2_KS2_UKUOK_SHIFT              (23U)
+/*! KS2_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS2_KS2_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKUOK_SHIFT)) & ELS_ELS_KS2_KS2_UKUOK_MASK)
+
+#define ELS_ELS_KS2_KS2_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS2_KS2_UTLSPMS_SHIFT            (24U)
+/*! KS2_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS2_KS2_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UTLSPMS_SHIFT)) & ELS_ELS_KS2_KS2_UTLSPMS_MASK)
+
+#define ELS_ELS_KS2_KS2_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS2_KS2_UTLSMS_SHIFT             (25U)
+/*! KS2_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS2_KS2_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UTLSMS_SHIFT)) & ELS_ELS_KS2_KS2_UTLSMS_MASK)
+
+#define ELS_ELS_KS2_KS2_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS2_KS2_UKGSRC_SHIFT             (26U)
+/*! KS2_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS2_KS2_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UKGSRC_SHIFT)) & ELS_ELS_KS2_KS2_UKGSRC_MASK)
+
+#define ELS_ELS_KS2_KS2_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS2_KS2_UHWO_SHIFT               (27U)
+/*! KS2_UHWO - Hardware out key */
+#define ELS_ELS_KS2_KS2_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UHWO_SHIFT)) & ELS_ELS_KS2_KS2_UHWO_MASK)
+
+#define ELS_ELS_KS2_KS2_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS2_KS2_UWRPOK_SHIFT             (28U)
+/*! KS2_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS2_KS2_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UWRPOK_SHIFT)) & ELS_ELS_KS2_KS2_UWRPOK_MASK)
+
+#define ELS_ELS_KS2_KS2_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS2_KS2_UDUK_SHIFT               (29U)
+/*! KS2_UDUK - Device Unique Key */
+#define ELS_ELS_KS2_KS2_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UDUK_SHIFT)) & ELS_ELS_KS2_KS2_UDUK_MASK)
+
+#define ELS_ELS_KS2_KS2_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS2_KS2_UPPROT_SHIFT             (30U)
+/*! KS2_UPPROT - Priviledge level */
+#define ELS_ELS_KS2_KS2_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS2_KS2_UPPROT_SHIFT)) & ELS_ELS_KS2_KS2_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS3 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS3_KS3_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS3_KS3_KSIZE_SHIFT              (0U)
+/*! KS3_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS3_KS3_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_KSIZE_SHIFT)) & ELS_ELS_KS3_KS3_KSIZE_MASK)
+
+#define ELS_ELS_KS3_KS3_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS3_KS3_RSVD0_SHIFT              (1U)
+/*! KS3_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS3_KS3_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_RSVD0_SHIFT)) & ELS_ELS_KS3_KS3_RSVD0_MASK)
+
+#define ELS_ELS_KS3_KS3_KACT_MASK                (0x20U)
+#define ELS_ELS_KS3_KS3_KACT_SHIFT               (5U)
+/*! KS3_KACT - Key is active */
+#define ELS_ELS_KS3_KS3_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_KACT_SHIFT)) & ELS_ELS_KS3_KS3_KACT_MASK)
+
+#define ELS_ELS_KS3_KS3_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS3_KS3_KBASE_SHIFT              (6U)
+/*! KS3_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS3_KS3_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_KBASE_SHIFT)) & ELS_ELS_KS3_KS3_KBASE_MASK)
+
+#define ELS_ELS_KS3_KS3_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS3_KS3_FGP_SHIFT                (7U)
+/*! KS3_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS3_KS3_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_FGP_SHIFT)) & ELS_ELS_KS3_KS3_FGP_MASK)
+
+#define ELS_ELS_KS3_KS3_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS3_KS3_FRTN_SHIFT               (8U)
+/*! KS3_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS3_KS3_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_FRTN_SHIFT)) & ELS_ELS_KS3_KS3_FRTN_MASK)
+
+#define ELS_ELS_KS3_KS3_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS3_KS3_FHWO_SHIFT               (9U)
+/*! KS3_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS3_KS3_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_FHWO_SHIFT)) & ELS_ELS_KS3_KS3_FHWO_MASK)
+
+#define ELS_ELS_KS3_KS3_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS3_KS3_RSVD1_SHIFT              (10U)
+/*! KS3_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS3_KS3_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_RSVD1_SHIFT)) & ELS_ELS_KS3_KS3_RSVD1_MASK)
+
+#define ELS_ELS_KS3_KS3_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS3_KS3_UCMAC_SHIFT              (13U)
+/*! KS3_UCMAC - CMAC key */
+#define ELS_ELS_KS3_KS3_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UCMAC_SHIFT)) & ELS_ELS_KS3_KS3_UCMAC_MASK)
+
+#define ELS_ELS_KS3_KS3_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS3_KS3_UKSK_SHIFT               (14U)
+/*! KS3_UKSK - KSK key */
+#define ELS_ELS_KS3_KS3_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKSK_SHIFT)) & ELS_ELS_KS3_KS3_UKSK_MASK)
+
+#define ELS_ELS_KS3_KS3_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS3_KS3_URTF_SHIFT               (15U)
+/*! KS3_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS3_KS3_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_URTF_SHIFT)) & ELS_ELS_KS3_KS3_URTF_MASK)
+
+#define ELS_ELS_KS3_KS3_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS3_KS3_UCKDF_SHIFT              (16U)
+/*! KS3_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS3_KS3_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UCKDF_SHIFT)) & ELS_ELS_KS3_KS3_UCKDF_MASK)
+
+#define ELS_ELS_KS3_KS3_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS3_KS3_UHKDF_SHIFT              (17U)
+/*! KS3_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS3_KS3_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UHKDF_SHIFT)) & ELS_ELS_KS3_KS3_UHKDF_MASK)
+
+#define ELS_ELS_KS3_KS3_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS3_KS3_UECSG_SHIFT              (18U)
+/*! KS3_UECSG - Ecc signing key */
+#define ELS_ELS_KS3_KS3_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UECSG_SHIFT)) & ELS_ELS_KS3_KS3_UECSG_MASK)
+
+#define ELS_ELS_KS3_KS3_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS3_KS3_UECDH_SHIFT              (19U)
+/*! KS3_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS3_KS3_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UECDH_SHIFT)) & ELS_ELS_KS3_KS3_UECDH_MASK)
+
+#define ELS_ELS_KS3_KS3_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS3_KS3_UAES_SHIFT               (20U)
+/*! KS3_UAES - Aes key */
+#define ELS_ELS_KS3_KS3_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UAES_SHIFT)) & ELS_ELS_KS3_KS3_UAES_MASK)
+
+#define ELS_ELS_KS3_KS3_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS3_KS3_UHMAC_SHIFT              (21U)
+/*! KS3_UHMAC - Hmac key */
+#define ELS_ELS_KS3_KS3_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UHMAC_SHIFT)) & ELS_ELS_KS3_KS3_UHMAC_MASK)
+
+#define ELS_ELS_KS3_KS3_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS3_KS3_UKWK_SHIFT               (22U)
+/*! KS3_UKWK - Key wrapping key */
+#define ELS_ELS_KS3_KS3_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKWK_SHIFT)) & ELS_ELS_KS3_KS3_UKWK_MASK)
+
+#define ELS_ELS_KS3_KS3_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS3_KS3_UKUOK_SHIFT              (23U)
+/*! KS3_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS3_KS3_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKUOK_SHIFT)) & ELS_ELS_KS3_KS3_UKUOK_MASK)
+
+#define ELS_ELS_KS3_KS3_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS3_KS3_UTLSPMS_SHIFT            (24U)
+/*! KS3_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS3_KS3_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UTLSPMS_SHIFT)) & ELS_ELS_KS3_KS3_UTLSPMS_MASK)
+
+#define ELS_ELS_KS3_KS3_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS3_KS3_UTLSMS_SHIFT             (25U)
+/*! KS3_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS3_KS3_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UTLSMS_SHIFT)) & ELS_ELS_KS3_KS3_UTLSMS_MASK)
+
+#define ELS_ELS_KS3_KS3_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS3_KS3_UKGSRC_SHIFT             (26U)
+/*! KS3_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS3_KS3_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UKGSRC_SHIFT)) & ELS_ELS_KS3_KS3_UKGSRC_MASK)
+
+#define ELS_ELS_KS3_KS3_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS3_KS3_UHWO_SHIFT               (27U)
+/*! KS3_UHWO - Hardware out key */
+#define ELS_ELS_KS3_KS3_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UHWO_SHIFT)) & ELS_ELS_KS3_KS3_UHWO_MASK)
+
+#define ELS_ELS_KS3_KS3_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS3_KS3_UWRPOK_SHIFT             (28U)
+/*! KS3_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS3_KS3_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UWRPOK_SHIFT)) & ELS_ELS_KS3_KS3_UWRPOK_MASK)
+
+#define ELS_ELS_KS3_KS3_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS3_KS3_UDUK_SHIFT               (29U)
+/*! KS3_UDUK - Device Unique Key */
+#define ELS_ELS_KS3_KS3_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UDUK_SHIFT)) & ELS_ELS_KS3_KS3_UDUK_MASK)
+
+#define ELS_ELS_KS3_KS3_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS3_KS3_UPPROT_SHIFT             (30U)
+/*! KS3_UPPROT - Priviledge level */
+#define ELS_ELS_KS3_KS3_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS3_KS3_UPPROT_SHIFT)) & ELS_ELS_KS3_KS3_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS4 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS4_KS4_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS4_KS4_KSIZE_SHIFT              (0U)
+/*! KS4_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS4_KS4_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_KSIZE_SHIFT)) & ELS_ELS_KS4_KS4_KSIZE_MASK)
+
+#define ELS_ELS_KS4_KS4_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS4_KS4_RSVD0_SHIFT              (1U)
+/*! KS4_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS4_KS4_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_RSVD0_SHIFT)) & ELS_ELS_KS4_KS4_RSVD0_MASK)
+
+#define ELS_ELS_KS4_KS4_KACT_MASK                (0x20U)
+#define ELS_ELS_KS4_KS4_KACT_SHIFT               (5U)
+/*! KS4_KACT - Key is active */
+#define ELS_ELS_KS4_KS4_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_KACT_SHIFT)) & ELS_ELS_KS4_KS4_KACT_MASK)
+
+#define ELS_ELS_KS4_KS4_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS4_KS4_KBASE_SHIFT              (6U)
+/*! KS4_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS4_KS4_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_KBASE_SHIFT)) & ELS_ELS_KS4_KS4_KBASE_MASK)
+
+#define ELS_ELS_KS4_KS4_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS4_KS4_FGP_SHIFT                (7U)
+/*! KS4_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS4_KS4_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_FGP_SHIFT)) & ELS_ELS_KS4_KS4_FGP_MASK)
+
+#define ELS_ELS_KS4_KS4_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS4_KS4_FRTN_SHIFT               (8U)
+/*! KS4_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS4_KS4_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_FRTN_SHIFT)) & ELS_ELS_KS4_KS4_FRTN_MASK)
+
+#define ELS_ELS_KS4_KS4_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS4_KS4_FHWO_SHIFT               (9U)
+/*! KS4_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS4_KS4_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_FHWO_SHIFT)) & ELS_ELS_KS4_KS4_FHWO_MASK)
+
+#define ELS_ELS_KS4_KS4_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS4_KS4_RSVD1_SHIFT              (10U)
+/*! KS4_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS4_KS4_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_RSVD1_SHIFT)) & ELS_ELS_KS4_KS4_RSVD1_MASK)
+
+#define ELS_ELS_KS4_KS4_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS4_KS4_UCMAC_SHIFT              (13U)
+/*! KS4_UCMAC - CMAC key */
+#define ELS_ELS_KS4_KS4_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UCMAC_SHIFT)) & ELS_ELS_KS4_KS4_UCMAC_MASK)
+
+#define ELS_ELS_KS4_KS4_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS4_KS4_UKSK_SHIFT               (14U)
+/*! KS4_UKSK - KSK key */
+#define ELS_ELS_KS4_KS4_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKSK_SHIFT)) & ELS_ELS_KS4_KS4_UKSK_MASK)
+
+#define ELS_ELS_KS4_KS4_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS4_KS4_URTF_SHIFT               (15U)
+/*! KS4_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS4_KS4_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_URTF_SHIFT)) & ELS_ELS_KS4_KS4_URTF_MASK)
+
+#define ELS_ELS_KS4_KS4_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS4_KS4_UCKDF_SHIFT              (16U)
+/*! KS4_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS4_KS4_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UCKDF_SHIFT)) & ELS_ELS_KS4_KS4_UCKDF_MASK)
+
+#define ELS_ELS_KS4_KS4_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS4_KS4_UHKDF_SHIFT              (17U)
+/*! KS4_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS4_KS4_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UHKDF_SHIFT)) & ELS_ELS_KS4_KS4_UHKDF_MASK)
+
+#define ELS_ELS_KS4_KS4_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS4_KS4_UECSG_SHIFT              (18U)
+/*! KS4_UECSG - Ecc signing key */
+#define ELS_ELS_KS4_KS4_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UECSG_SHIFT)) & ELS_ELS_KS4_KS4_UECSG_MASK)
+
+#define ELS_ELS_KS4_KS4_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS4_KS4_UECDH_SHIFT              (19U)
+/*! KS4_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS4_KS4_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UECDH_SHIFT)) & ELS_ELS_KS4_KS4_UECDH_MASK)
+
+#define ELS_ELS_KS4_KS4_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS4_KS4_UAES_SHIFT               (20U)
+/*! KS4_UAES - Aes key */
+#define ELS_ELS_KS4_KS4_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UAES_SHIFT)) & ELS_ELS_KS4_KS4_UAES_MASK)
+
+#define ELS_ELS_KS4_KS4_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS4_KS4_UHMAC_SHIFT              (21U)
+/*! KS4_UHMAC - Hmac key */
+#define ELS_ELS_KS4_KS4_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UHMAC_SHIFT)) & ELS_ELS_KS4_KS4_UHMAC_MASK)
+
+#define ELS_ELS_KS4_KS4_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS4_KS4_UKWK_SHIFT               (22U)
+/*! KS4_UKWK - Key wrapping key */
+#define ELS_ELS_KS4_KS4_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKWK_SHIFT)) & ELS_ELS_KS4_KS4_UKWK_MASK)
+
+#define ELS_ELS_KS4_KS4_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS4_KS4_UKUOK_SHIFT              (23U)
+/*! KS4_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS4_KS4_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKUOK_SHIFT)) & ELS_ELS_KS4_KS4_UKUOK_MASK)
+
+#define ELS_ELS_KS4_KS4_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS4_KS4_UTLSPMS_SHIFT            (24U)
+/*! KS4_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS4_KS4_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UTLSPMS_SHIFT)) & ELS_ELS_KS4_KS4_UTLSPMS_MASK)
+
+#define ELS_ELS_KS4_KS4_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS4_KS4_UTLSMS_SHIFT             (25U)
+/*! KS4_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS4_KS4_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UTLSMS_SHIFT)) & ELS_ELS_KS4_KS4_UTLSMS_MASK)
+
+#define ELS_ELS_KS4_KS4_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS4_KS4_UKGSRC_SHIFT             (26U)
+/*! KS4_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS4_KS4_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UKGSRC_SHIFT)) & ELS_ELS_KS4_KS4_UKGSRC_MASK)
+
+#define ELS_ELS_KS4_KS4_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS4_KS4_UHWO_SHIFT               (27U)
+/*! KS4_UHWO - Hardware out key */
+#define ELS_ELS_KS4_KS4_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UHWO_SHIFT)) & ELS_ELS_KS4_KS4_UHWO_MASK)
+
+#define ELS_ELS_KS4_KS4_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS4_KS4_UWRPOK_SHIFT             (28U)
+/*! KS4_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS4_KS4_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UWRPOK_SHIFT)) & ELS_ELS_KS4_KS4_UWRPOK_MASK)
+
+#define ELS_ELS_KS4_KS4_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS4_KS4_UDUK_SHIFT               (29U)
+/*! KS4_UDUK - Device Unique Key */
+#define ELS_ELS_KS4_KS4_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UDUK_SHIFT)) & ELS_ELS_KS4_KS4_UDUK_MASK)
+
+#define ELS_ELS_KS4_KS4_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS4_KS4_UPPROT_SHIFT             (30U)
+/*! KS4_UPPROT - Priviledge level */
+#define ELS_ELS_KS4_KS4_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS4_KS4_UPPROT_SHIFT)) & ELS_ELS_KS4_KS4_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS5 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS5_KS5_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS5_KS5_KSIZE_SHIFT              (0U)
+/*! KS5_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS5_KS5_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_KSIZE_SHIFT)) & ELS_ELS_KS5_KS5_KSIZE_MASK)
+
+#define ELS_ELS_KS5_KS5_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS5_KS5_RSVD0_SHIFT              (1U)
+/*! KS5_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS5_KS5_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_RSVD0_SHIFT)) & ELS_ELS_KS5_KS5_RSVD0_MASK)
+
+#define ELS_ELS_KS5_KS5_KACT_MASK                (0x20U)
+#define ELS_ELS_KS5_KS5_KACT_SHIFT               (5U)
+/*! KS5_KACT - Key is active */
+#define ELS_ELS_KS5_KS5_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_KACT_SHIFT)) & ELS_ELS_KS5_KS5_KACT_MASK)
+
+#define ELS_ELS_KS5_KS5_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS5_KS5_KBASE_SHIFT              (6U)
+/*! KS5_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS5_KS5_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_KBASE_SHIFT)) & ELS_ELS_KS5_KS5_KBASE_MASK)
+
+#define ELS_ELS_KS5_KS5_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS5_KS5_FGP_SHIFT                (7U)
+/*! KS5_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS5_KS5_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_FGP_SHIFT)) & ELS_ELS_KS5_KS5_FGP_MASK)
+
+#define ELS_ELS_KS5_KS5_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS5_KS5_FRTN_SHIFT               (8U)
+/*! KS5_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS5_KS5_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_FRTN_SHIFT)) & ELS_ELS_KS5_KS5_FRTN_MASK)
+
+#define ELS_ELS_KS5_KS5_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS5_KS5_FHWO_SHIFT               (9U)
+/*! KS5_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS5_KS5_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_FHWO_SHIFT)) & ELS_ELS_KS5_KS5_FHWO_MASK)
+
+#define ELS_ELS_KS5_KS5_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS5_KS5_RSVD1_SHIFT              (10U)
+/*! KS5_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS5_KS5_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_RSVD1_SHIFT)) & ELS_ELS_KS5_KS5_RSVD1_MASK)
+
+#define ELS_ELS_KS5_KS5_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS5_KS5_UCMAC_SHIFT              (13U)
+/*! KS5_UCMAC - CMAC key */
+#define ELS_ELS_KS5_KS5_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UCMAC_SHIFT)) & ELS_ELS_KS5_KS5_UCMAC_MASK)
+
+#define ELS_ELS_KS5_KS5_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS5_KS5_UKSK_SHIFT               (14U)
+/*! KS5_UKSK - KSK key */
+#define ELS_ELS_KS5_KS5_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKSK_SHIFT)) & ELS_ELS_KS5_KS5_UKSK_MASK)
+
+#define ELS_ELS_KS5_KS5_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS5_KS5_URTF_SHIFT               (15U)
+/*! KS5_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS5_KS5_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_URTF_SHIFT)) & ELS_ELS_KS5_KS5_URTF_MASK)
+
+#define ELS_ELS_KS5_KS5_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS5_KS5_UCKDF_SHIFT              (16U)
+/*! KS5_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS5_KS5_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UCKDF_SHIFT)) & ELS_ELS_KS5_KS5_UCKDF_MASK)
+
+#define ELS_ELS_KS5_KS5_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS5_KS5_UHKDF_SHIFT              (17U)
+/*! KS5_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS5_KS5_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UHKDF_SHIFT)) & ELS_ELS_KS5_KS5_UHKDF_MASK)
+
+#define ELS_ELS_KS5_KS5_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS5_KS5_UECSG_SHIFT              (18U)
+/*! KS5_UECSG - Ecc signing key */
+#define ELS_ELS_KS5_KS5_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UECSG_SHIFT)) & ELS_ELS_KS5_KS5_UECSG_MASK)
+
+#define ELS_ELS_KS5_KS5_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS5_KS5_UECDH_SHIFT              (19U)
+/*! KS5_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS5_KS5_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UECDH_SHIFT)) & ELS_ELS_KS5_KS5_UECDH_MASK)
+
+#define ELS_ELS_KS5_KS5_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS5_KS5_UAES_SHIFT               (20U)
+/*! KS5_UAES - Aes key */
+#define ELS_ELS_KS5_KS5_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UAES_SHIFT)) & ELS_ELS_KS5_KS5_UAES_MASK)
+
+#define ELS_ELS_KS5_KS5_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS5_KS5_UHMAC_SHIFT              (21U)
+/*! KS5_UHMAC - Hmac key */
+#define ELS_ELS_KS5_KS5_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UHMAC_SHIFT)) & ELS_ELS_KS5_KS5_UHMAC_MASK)
+
+#define ELS_ELS_KS5_KS5_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS5_KS5_UKWK_SHIFT               (22U)
+/*! KS5_UKWK - Key wrapping key */
+#define ELS_ELS_KS5_KS5_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKWK_SHIFT)) & ELS_ELS_KS5_KS5_UKWK_MASK)
+
+#define ELS_ELS_KS5_KS5_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS5_KS5_UKUOK_SHIFT              (23U)
+/*! KS5_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS5_KS5_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKUOK_SHIFT)) & ELS_ELS_KS5_KS5_UKUOK_MASK)
+
+#define ELS_ELS_KS5_KS5_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS5_KS5_UTLSPMS_SHIFT            (24U)
+/*! KS5_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS5_KS5_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UTLSPMS_SHIFT)) & ELS_ELS_KS5_KS5_UTLSPMS_MASK)
+
+#define ELS_ELS_KS5_KS5_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS5_KS5_UTLSMS_SHIFT             (25U)
+/*! KS5_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS5_KS5_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UTLSMS_SHIFT)) & ELS_ELS_KS5_KS5_UTLSMS_MASK)
+
+#define ELS_ELS_KS5_KS5_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS5_KS5_UKGSRC_SHIFT             (26U)
+/*! KS5_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS5_KS5_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UKGSRC_SHIFT)) & ELS_ELS_KS5_KS5_UKGSRC_MASK)
+
+#define ELS_ELS_KS5_KS5_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS5_KS5_UHWO_SHIFT               (27U)
+/*! KS5_UHWO - Hardware out key */
+#define ELS_ELS_KS5_KS5_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UHWO_SHIFT)) & ELS_ELS_KS5_KS5_UHWO_MASK)
+
+#define ELS_ELS_KS5_KS5_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS5_KS5_UWRPOK_SHIFT             (28U)
+/*! KS5_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS5_KS5_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UWRPOK_SHIFT)) & ELS_ELS_KS5_KS5_UWRPOK_MASK)
+
+#define ELS_ELS_KS5_KS5_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS5_KS5_UDUK_SHIFT               (29U)
+/*! KS5_UDUK - Device Unique Key */
+#define ELS_ELS_KS5_KS5_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UDUK_SHIFT)) & ELS_ELS_KS5_KS5_UDUK_MASK)
+
+#define ELS_ELS_KS5_KS5_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS5_KS5_UPPROT_SHIFT             (30U)
+/*! KS5_UPPROT - Priviledge level */
+#define ELS_ELS_KS5_KS5_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS5_KS5_UPPROT_SHIFT)) & ELS_ELS_KS5_KS5_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS6 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS6_KS6_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS6_KS6_KSIZE_SHIFT              (0U)
+/*! KS6_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS6_KS6_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_KSIZE_SHIFT)) & ELS_ELS_KS6_KS6_KSIZE_MASK)
+
+#define ELS_ELS_KS6_KS6_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS6_KS6_RSVD0_SHIFT              (1U)
+/*! KS6_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS6_KS6_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_RSVD0_SHIFT)) & ELS_ELS_KS6_KS6_RSVD0_MASK)
+
+#define ELS_ELS_KS6_KS6_KACT_MASK                (0x20U)
+#define ELS_ELS_KS6_KS6_KACT_SHIFT               (5U)
+/*! KS6_KACT - Key is active */
+#define ELS_ELS_KS6_KS6_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_KACT_SHIFT)) & ELS_ELS_KS6_KS6_KACT_MASK)
+
+#define ELS_ELS_KS6_KS6_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS6_KS6_KBASE_SHIFT              (6U)
+/*! KS6_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS6_KS6_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_KBASE_SHIFT)) & ELS_ELS_KS6_KS6_KBASE_MASK)
+
+#define ELS_ELS_KS6_KS6_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS6_KS6_FGP_SHIFT                (7U)
+/*! KS6_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS6_KS6_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_FGP_SHIFT)) & ELS_ELS_KS6_KS6_FGP_MASK)
+
+#define ELS_ELS_KS6_KS6_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS6_KS6_FRTN_SHIFT               (8U)
+/*! KS6_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS6_KS6_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_FRTN_SHIFT)) & ELS_ELS_KS6_KS6_FRTN_MASK)
+
+#define ELS_ELS_KS6_KS6_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS6_KS6_FHWO_SHIFT               (9U)
+/*! KS6_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS6_KS6_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_FHWO_SHIFT)) & ELS_ELS_KS6_KS6_FHWO_MASK)
+
+#define ELS_ELS_KS6_KS6_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS6_KS6_RSVD1_SHIFT              (10U)
+/*! KS6_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS6_KS6_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_RSVD1_SHIFT)) & ELS_ELS_KS6_KS6_RSVD1_MASK)
+
+#define ELS_ELS_KS6_KS6_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS6_KS6_UCMAC_SHIFT              (13U)
+/*! KS6_UCMAC - CMAC key */
+#define ELS_ELS_KS6_KS6_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UCMAC_SHIFT)) & ELS_ELS_KS6_KS6_UCMAC_MASK)
+
+#define ELS_ELS_KS6_KS6_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS6_KS6_UKSK_SHIFT               (14U)
+/*! KS6_UKSK - KSK key */
+#define ELS_ELS_KS6_KS6_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKSK_SHIFT)) & ELS_ELS_KS6_KS6_UKSK_MASK)
+
+#define ELS_ELS_KS6_KS6_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS6_KS6_URTF_SHIFT               (15U)
+/*! KS6_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS6_KS6_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_URTF_SHIFT)) & ELS_ELS_KS6_KS6_URTF_MASK)
+
+#define ELS_ELS_KS6_KS6_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS6_KS6_UCKDF_SHIFT              (16U)
+/*! KS6_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS6_KS6_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UCKDF_SHIFT)) & ELS_ELS_KS6_KS6_UCKDF_MASK)
+
+#define ELS_ELS_KS6_KS6_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS6_KS6_UHKDF_SHIFT              (17U)
+/*! KS6_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS6_KS6_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UHKDF_SHIFT)) & ELS_ELS_KS6_KS6_UHKDF_MASK)
+
+#define ELS_ELS_KS6_KS6_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS6_KS6_UECSG_SHIFT              (18U)
+/*! KS6_UECSG - Ecc signing key */
+#define ELS_ELS_KS6_KS6_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UECSG_SHIFT)) & ELS_ELS_KS6_KS6_UECSG_MASK)
+
+#define ELS_ELS_KS6_KS6_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS6_KS6_UECDH_SHIFT              (19U)
+/*! KS6_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS6_KS6_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UECDH_SHIFT)) & ELS_ELS_KS6_KS6_UECDH_MASK)
+
+#define ELS_ELS_KS6_KS6_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS6_KS6_UAES_SHIFT               (20U)
+/*! KS6_UAES - Aes key */
+#define ELS_ELS_KS6_KS6_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UAES_SHIFT)) & ELS_ELS_KS6_KS6_UAES_MASK)
+
+#define ELS_ELS_KS6_KS6_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS6_KS6_UHMAC_SHIFT              (21U)
+/*! KS6_UHMAC - Hmac key */
+#define ELS_ELS_KS6_KS6_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UHMAC_SHIFT)) & ELS_ELS_KS6_KS6_UHMAC_MASK)
+
+#define ELS_ELS_KS6_KS6_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS6_KS6_UKWK_SHIFT               (22U)
+/*! KS6_UKWK - Key wrapping key */
+#define ELS_ELS_KS6_KS6_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKWK_SHIFT)) & ELS_ELS_KS6_KS6_UKWK_MASK)
+
+#define ELS_ELS_KS6_KS6_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS6_KS6_UKUOK_SHIFT              (23U)
+/*! KS6_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS6_KS6_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKUOK_SHIFT)) & ELS_ELS_KS6_KS6_UKUOK_MASK)
+
+#define ELS_ELS_KS6_KS6_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS6_KS6_UTLSPMS_SHIFT            (24U)
+/*! KS6_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS6_KS6_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UTLSPMS_SHIFT)) & ELS_ELS_KS6_KS6_UTLSPMS_MASK)
+
+#define ELS_ELS_KS6_KS6_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS6_KS6_UTLSMS_SHIFT             (25U)
+/*! KS6_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS6_KS6_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UTLSMS_SHIFT)) & ELS_ELS_KS6_KS6_UTLSMS_MASK)
+
+#define ELS_ELS_KS6_KS6_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS6_KS6_UKGSRC_SHIFT             (26U)
+/*! KS6_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS6_KS6_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UKGSRC_SHIFT)) & ELS_ELS_KS6_KS6_UKGSRC_MASK)
+
+#define ELS_ELS_KS6_KS6_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS6_KS6_UHWO_SHIFT               (27U)
+/*! KS6_UHWO - Hardware out key */
+#define ELS_ELS_KS6_KS6_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UHWO_SHIFT)) & ELS_ELS_KS6_KS6_UHWO_MASK)
+
+#define ELS_ELS_KS6_KS6_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS6_KS6_UWRPOK_SHIFT             (28U)
+/*! KS6_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS6_KS6_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UWRPOK_SHIFT)) & ELS_ELS_KS6_KS6_UWRPOK_MASK)
+
+#define ELS_ELS_KS6_KS6_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS6_KS6_UDUK_SHIFT               (29U)
+/*! KS6_UDUK - Device Unique Key */
+#define ELS_ELS_KS6_KS6_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UDUK_SHIFT)) & ELS_ELS_KS6_KS6_UDUK_MASK)
+
+#define ELS_ELS_KS6_KS6_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS6_KS6_UPPROT_SHIFT             (30U)
+/*! KS6_UPPROT - Priviledge level */
+#define ELS_ELS_KS6_KS6_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS6_KS6_UPPROT_SHIFT)) & ELS_ELS_KS6_KS6_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS7 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS7_KS7_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS7_KS7_KSIZE_SHIFT              (0U)
+/*! KS7_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS7_KS7_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_KSIZE_SHIFT)) & ELS_ELS_KS7_KS7_KSIZE_MASK)
+
+#define ELS_ELS_KS7_KS7_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS7_KS7_RSVD0_SHIFT              (1U)
+/*! KS7_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS7_KS7_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_RSVD0_SHIFT)) & ELS_ELS_KS7_KS7_RSVD0_MASK)
+
+#define ELS_ELS_KS7_KS7_KACT_MASK                (0x20U)
+#define ELS_ELS_KS7_KS7_KACT_SHIFT               (5U)
+/*! KS7_KACT - Key is active */
+#define ELS_ELS_KS7_KS7_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_KACT_SHIFT)) & ELS_ELS_KS7_KS7_KACT_MASK)
+
+#define ELS_ELS_KS7_KS7_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS7_KS7_KBASE_SHIFT              (6U)
+/*! KS7_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS7_KS7_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_KBASE_SHIFT)) & ELS_ELS_KS7_KS7_KBASE_MASK)
+
+#define ELS_ELS_KS7_KS7_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS7_KS7_FGP_SHIFT                (7U)
+/*! KS7_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS7_KS7_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_FGP_SHIFT)) & ELS_ELS_KS7_KS7_FGP_MASK)
+
+#define ELS_ELS_KS7_KS7_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS7_KS7_FRTN_SHIFT               (8U)
+/*! KS7_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS7_KS7_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_FRTN_SHIFT)) & ELS_ELS_KS7_KS7_FRTN_MASK)
+
+#define ELS_ELS_KS7_KS7_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS7_KS7_FHWO_SHIFT               (9U)
+/*! KS7_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS7_KS7_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_FHWO_SHIFT)) & ELS_ELS_KS7_KS7_FHWO_MASK)
+
+#define ELS_ELS_KS7_KS7_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS7_KS7_RSVD1_SHIFT              (10U)
+/*! KS7_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS7_KS7_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_RSVD1_SHIFT)) & ELS_ELS_KS7_KS7_RSVD1_MASK)
+
+#define ELS_ELS_KS7_KS7_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS7_KS7_UCMAC_SHIFT              (13U)
+/*! KS7_UCMAC - CMAC key */
+#define ELS_ELS_KS7_KS7_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UCMAC_SHIFT)) & ELS_ELS_KS7_KS7_UCMAC_MASK)
+
+#define ELS_ELS_KS7_KS7_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS7_KS7_UKSK_SHIFT               (14U)
+/*! KS7_UKSK - KSK key */
+#define ELS_ELS_KS7_KS7_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKSK_SHIFT)) & ELS_ELS_KS7_KS7_UKSK_MASK)
+
+#define ELS_ELS_KS7_KS7_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS7_KS7_URTF_SHIFT               (15U)
+/*! KS7_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS7_KS7_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_URTF_SHIFT)) & ELS_ELS_KS7_KS7_URTF_MASK)
+
+#define ELS_ELS_KS7_KS7_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS7_KS7_UCKDF_SHIFT              (16U)
+/*! KS7_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS7_KS7_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UCKDF_SHIFT)) & ELS_ELS_KS7_KS7_UCKDF_MASK)
+
+#define ELS_ELS_KS7_KS7_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS7_KS7_UHKDF_SHIFT              (17U)
+/*! KS7_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS7_KS7_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UHKDF_SHIFT)) & ELS_ELS_KS7_KS7_UHKDF_MASK)
+
+#define ELS_ELS_KS7_KS7_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS7_KS7_UECSG_SHIFT              (18U)
+/*! KS7_UECSG - Ecc signing key */
+#define ELS_ELS_KS7_KS7_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UECSG_SHIFT)) & ELS_ELS_KS7_KS7_UECSG_MASK)
+
+#define ELS_ELS_KS7_KS7_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS7_KS7_UECDH_SHIFT              (19U)
+/*! KS7_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS7_KS7_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UECDH_SHIFT)) & ELS_ELS_KS7_KS7_UECDH_MASK)
+
+#define ELS_ELS_KS7_KS7_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS7_KS7_UAES_SHIFT               (20U)
+/*! KS7_UAES - Aes key */
+#define ELS_ELS_KS7_KS7_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UAES_SHIFT)) & ELS_ELS_KS7_KS7_UAES_MASK)
+
+#define ELS_ELS_KS7_KS7_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS7_KS7_UHMAC_SHIFT              (21U)
+/*! KS7_UHMAC - Hmac key */
+#define ELS_ELS_KS7_KS7_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UHMAC_SHIFT)) & ELS_ELS_KS7_KS7_UHMAC_MASK)
+
+#define ELS_ELS_KS7_KS7_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS7_KS7_UKWK_SHIFT               (22U)
+/*! KS7_UKWK - Key wrapping key */
+#define ELS_ELS_KS7_KS7_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKWK_SHIFT)) & ELS_ELS_KS7_KS7_UKWK_MASK)
+
+#define ELS_ELS_KS7_KS7_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS7_KS7_UKUOK_SHIFT              (23U)
+/*! KS7_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS7_KS7_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKUOK_SHIFT)) & ELS_ELS_KS7_KS7_UKUOK_MASK)
+
+#define ELS_ELS_KS7_KS7_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS7_KS7_UTLSPMS_SHIFT            (24U)
+/*! KS7_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS7_KS7_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UTLSPMS_SHIFT)) & ELS_ELS_KS7_KS7_UTLSPMS_MASK)
+
+#define ELS_ELS_KS7_KS7_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS7_KS7_UTLSMS_SHIFT             (25U)
+/*! KS7_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS7_KS7_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UTLSMS_SHIFT)) & ELS_ELS_KS7_KS7_UTLSMS_MASK)
+
+#define ELS_ELS_KS7_KS7_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS7_KS7_UKGSRC_SHIFT             (26U)
+/*! KS7_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS7_KS7_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UKGSRC_SHIFT)) & ELS_ELS_KS7_KS7_UKGSRC_MASK)
+
+#define ELS_ELS_KS7_KS7_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS7_KS7_UHWO_SHIFT               (27U)
+/*! KS7_UHWO - Hardware out key */
+#define ELS_ELS_KS7_KS7_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UHWO_SHIFT)) & ELS_ELS_KS7_KS7_UHWO_MASK)
+
+#define ELS_ELS_KS7_KS7_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS7_KS7_UWRPOK_SHIFT             (28U)
+/*! KS7_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS7_KS7_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UWRPOK_SHIFT)) & ELS_ELS_KS7_KS7_UWRPOK_MASK)
+
+#define ELS_ELS_KS7_KS7_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS7_KS7_UDUK_SHIFT               (29U)
+/*! KS7_UDUK - Device Unique Key */
+#define ELS_ELS_KS7_KS7_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UDUK_SHIFT)) & ELS_ELS_KS7_KS7_UDUK_MASK)
+
+#define ELS_ELS_KS7_KS7_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS7_KS7_UPPROT_SHIFT             (30U)
+/*! KS7_UPPROT - Priviledge level */
+#define ELS_ELS_KS7_KS7_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS7_KS7_UPPROT_SHIFT)) & ELS_ELS_KS7_KS7_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS8 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS8_KS8_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS8_KS8_KSIZE_SHIFT              (0U)
+/*! KS8_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS8_KS8_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_KSIZE_SHIFT)) & ELS_ELS_KS8_KS8_KSIZE_MASK)
+
+#define ELS_ELS_KS8_KS8_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS8_KS8_RSVD0_SHIFT              (1U)
+/*! KS8_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS8_KS8_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_RSVD0_SHIFT)) & ELS_ELS_KS8_KS8_RSVD0_MASK)
+
+#define ELS_ELS_KS8_KS8_KACT_MASK                (0x20U)
+#define ELS_ELS_KS8_KS8_KACT_SHIFT               (5U)
+/*! KS8_KACT - Key is active */
+#define ELS_ELS_KS8_KS8_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_KACT_SHIFT)) & ELS_ELS_KS8_KS8_KACT_MASK)
+
+#define ELS_ELS_KS8_KS8_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS8_KS8_KBASE_SHIFT              (6U)
+/*! KS8_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS8_KS8_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_KBASE_SHIFT)) & ELS_ELS_KS8_KS8_KBASE_MASK)
+
+#define ELS_ELS_KS8_KS8_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS8_KS8_FGP_SHIFT                (7U)
+/*! KS8_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS8_KS8_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_FGP_SHIFT)) & ELS_ELS_KS8_KS8_FGP_MASK)
+
+#define ELS_ELS_KS8_KS8_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS8_KS8_FRTN_SHIFT               (8U)
+/*! KS8_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS8_KS8_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_FRTN_SHIFT)) & ELS_ELS_KS8_KS8_FRTN_MASK)
+
+#define ELS_ELS_KS8_KS8_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS8_KS8_FHWO_SHIFT               (9U)
+/*! KS8_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS8_KS8_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_FHWO_SHIFT)) & ELS_ELS_KS8_KS8_FHWO_MASK)
+
+#define ELS_ELS_KS8_KS8_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS8_KS8_RSVD1_SHIFT              (10U)
+/*! KS8_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS8_KS8_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_RSVD1_SHIFT)) & ELS_ELS_KS8_KS8_RSVD1_MASK)
+
+#define ELS_ELS_KS8_KS8_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS8_KS8_UCMAC_SHIFT              (13U)
+/*! KS8_UCMAC - CMAC key */
+#define ELS_ELS_KS8_KS8_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UCMAC_SHIFT)) & ELS_ELS_KS8_KS8_UCMAC_MASK)
+
+#define ELS_ELS_KS8_KS8_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS8_KS8_UKSK_SHIFT               (14U)
+/*! KS8_UKSK - KSK key */
+#define ELS_ELS_KS8_KS8_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKSK_SHIFT)) & ELS_ELS_KS8_KS8_UKSK_MASK)
+
+#define ELS_ELS_KS8_KS8_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS8_KS8_URTF_SHIFT               (15U)
+/*! KS8_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS8_KS8_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_URTF_SHIFT)) & ELS_ELS_KS8_KS8_URTF_MASK)
+
+#define ELS_ELS_KS8_KS8_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS8_KS8_UCKDF_SHIFT              (16U)
+/*! KS8_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS8_KS8_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UCKDF_SHIFT)) & ELS_ELS_KS8_KS8_UCKDF_MASK)
+
+#define ELS_ELS_KS8_KS8_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS8_KS8_UHKDF_SHIFT              (17U)
+/*! KS8_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS8_KS8_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UHKDF_SHIFT)) & ELS_ELS_KS8_KS8_UHKDF_MASK)
+
+#define ELS_ELS_KS8_KS8_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS8_KS8_UECSG_SHIFT              (18U)
+/*! KS8_UECSG - Ecc signing key */
+#define ELS_ELS_KS8_KS8_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UECSG_SHIFT)) & ELS_ELS_KS8_KS8_UECSG_MASK)
+
+#define ELS_ELS_KS8_KS8_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS8_KS8_UECDH_SHIFT              (19U)
+/*! KS8_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS8_KS8_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UECDH_SHIFT)) & ELS_ELS_KS8_KS8_UECDH_MASK)
+
+#define ELS_ELS_KS8_KS8_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS8_KS8_UAES_SHIFT               (20U)
+/*! KS8_UAES - Aes key */
+#define ELS_ELS_KS8_KS8_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UAES_SHIFT)) & ELS_ELS_KS8_KS8_UAES_MASK)
+
+#define ELS_ELS_KS8_KS8_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS8_KS8_UHMAC_SHIFT              (21U)
+/*! KS8_UHMAC - Hmac key */
+#define ELS_ELS_KS8_KS8_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UHMAC_SHIFT)) & ELS_ELS_KS8_KS8_UHMAC_MASK)
+
+#define ELS_ELS_KS8_KS8_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS8_KS8_UKWK_SHIFT               (22U)
+/*! KS8_UKWK - Key wrapping key */
+#define ELS_ELS_KS8_KS8_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKWK_SHIFT)) & ELS_ELS_KS8_KS8_UKWK_MASK)
+
+#define ELS_ELS_KS8_KS8_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS8_KS8_UKUOK_SHIFT              (23U)
+/*! KS8_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS8_KS8_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKUOK_SHIFT)) & ELS_ELS_KS8_KS8_UKUOK_MASK)
+
+#define ELS_ELS_KS8_KS8_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS8_KS8_UTLSPMS_SHIFT            (24U)
+/*! KS8_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS8_KS8_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UTLSPMS_SHIFT)) & ELS_ELS_KS8_KS8_UTLSPMS_MASK)
+
+#define ELS_ELS_KS8_KS8_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS8_KS8_UTLSMS_SHIFT             (25U)
+/*! KS8_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS8_KS8_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UTLSMS_SHIFT)) & ELS_ELS_KS8_KS8_UTLSMS_MASK)
+
+#define ELS_ELS_KS8_KS8_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS8_KS8_UKGSRC_SHIFT             (26U)
+/*! KS8_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS8_KS8_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UKGSRC_SHIFT)) & ELS_ELS_KS8_KS8_UKGSRC_MASK)
+
+#define ELS_ELS_KS8_KS8_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS8_KS8_UHWO_SHIFT               (27U)
+/*! KS8_UHWO - Hardware out key */
+#define ELS_ELS_KS8_KS8_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UHWO_SHIFT)) & ELS_ELS_KS8_KS8_UHWO_MASK)
+
+#define ELS_ELS_KS8_KS8_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS8_KS8_UWRPOK_SHIFT             (28U)
+/*! KS8_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS8_KS8_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UWRPOK_SHIFT)) & ELS_ELS_KS8_KS8_UWRPOK_MASK)
+
+#define ELS_ELS_KS8_KS8_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS8_KS8_UDUK_SHIFT               (29U)
+/*! KS8_UDUK - Device Unique Key */
+#define ELS_ELS_KS8_KS8_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UDUK_SHIFT)) & ELS_ELS_KS8_KS8_UDUK_MASK)
+
+#define ELS_ELS_KS8_KS8_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS8_KS8_UPPROT_SHIFT             (30U)
+/*! KS8_UPPROT - Priviledge level */
+#define ELS_ELS_KS8_KS8_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS8_KS8_UPPROT_SHIFT)) & ELS_ELS_KS8_KS8_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS9 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS9_KS9_KSIZE_MASK               (0x1U)
+#define ELS_ELS_KS9_KS9_KSIZE_SHIFT              (0U)
+/*! KS9_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS9_KS9_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_KSIZE_SHIFT)) & ELS_ELS_KS9_KS9_KSIZE_MASK)
+
+#define ELS_ELS_KS9_KS9_RSVD0_MASK               (0x1EU)
+#define ELS_ELS_KS9_KS9_RSVD0_SHIFT              (1U)
+/*! KS9_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS9_KS9_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_RSVD0_SHIFT)) & ELS_ELS_KS9_KS9_RSVD0_MASK)
+
+#define ELS_ELS_KS9_KS9_KACT_MASK                (0x20U)
+#define ELS_ELS_KS9_KS9_KACT_SHIFT               (5U)
+/*! KS9_KACT - Key is active */
+#define ELS_ELS_KS9_KS9_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_KACT_SHIFT)) & ELS_ELS_KS9_KS9_KACT_MASK)
+
+#define ELS_ELS_KS9_KS9_KBASE_MASK               (0x40U)
+#define ELS_ELS_KS9_KS9_KBASE_SHIFT              (6U)
+/*! KS9_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS9_KS9_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_KBASE_SHIFT)) & ELS_ELS_KS9_KS9_KBASE_MASK)
+
+#define ELS_ELS_KS9_KS9_FGP_MASK                 (0x80U)
+#define ELS_ELS_KS9_KS9_FGP_SHIFT                (7U)
+/*! KS9_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS9_KS9_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_FGP_SHIFT)) & ELS_ELS_KS9_KS9_FGP_MASK)
+
+#define ELS_ELS_KS9_KS9_FRTN_MASK                (0x100U)
+#define ELS_ELS_KS9_KS9_FRTN_SHIFT               (8U)
+/*! KS9_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS9_KS9_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_FRTN_SHIFT)) & ELS_ELS_KS9_KS9_FRTN_MASK)
+
+#define ELS_ELS_KS9_KS9_FHWO_MASK                (0x200U)
+#define ELS_ELS_KS9_KS9_FHWO_SHIFT               (9U)
+/*! KS9_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS9_KS9_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_FHWO_SHIFT)) & ELS_ELS_KS9_KS9_FHWO_MASK)
+
+#define ELS_ELS_KS9_KS9_RSVD1_MASK               (0x1C00U)
+#define ELS_ELS_KS9_KS9_RSVD1_SHIFT              (10U)
+/*! KS9_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS9_KS9_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_RSVD1_SHIFT)) & ELS_ELS_KS9_KS9_RSVD1_MASK)
+
+#define ELS_ELS_KS9_KS9_UCMAC_MASK               (0x2000U)
+#define ELS_ELS_KS9_KS9_UCMAC_SHIFT              (13U)
+/*! KS9_UCMAC - CMAC key */
+#define ELS_ELS_KS9_KS9_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UCMAC_SHIFT)) & ELS_ELS_KS9_KS9_UCMAC_MASK)
+
+#define ELS_ELS_KS9_KS9_UKSK_MASK                (0x4000U)
+#define ELS_ELS_KS9_KS9_UKSK_SHIFT               (14U)
+/*! KS9_UKSK - KSK key */
+#define ELS_ELS_KS9_KS9_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKSK_SHIFT)) & ELS_ELS_KS9_KS9_UKSK_MASK)
+
+#define ELS_ELS_KS9_KS9_URTF_MASK                (0x8000U)
+#define ELS_ELS_KS9_KS9_URTF_SHIFT               (15U)
+/*! KS9_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS9_KS9_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_URTF_SHIFT)) & ELS_ELS_KS9_KS9_URTF_MASK)
+
+#define ELS_ELS_KS9_KS9_UCKDF_MASK               (0x10000U)
+#define ELS_ELS_KS9_KS9_UCKDF_SHIFT              (16U)
+/*! KS9_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS9_KS9_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UCKDF_SHIFT)) & ELS_ELS_KS9_KS9_UCKDF_MASK)
+
+#define ELS_ELS_KS9_KS9_UHKDF_MASK               (0x20000U)
+#define ELS_ELS_KS9_KS9_UHKDF_SHIFT              (17U)
+/*! KS9_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS9_KS9_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UHKDF_SHIFT)) & ELS_ELS_KS9_KS9_UHKDF_MASK)
+
+#define ELS_ELS_KS9_KS9_UECSG_MASK               (0x40000U)
+#define ELS_ELS_KS9_KS9_UECSG_SHIFT              (18U)
+/*! KS9_UECSG - Ecc signing key */
+#define ELS_ELS_KS9_KS9_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UECSG_SHIFT)) & ELS_ELS_KS9_KS9_UECSG_MASK)
+
+#define ELS_ELS_KS9_KS9_UECDH_MASK               (0x80000U)
+#define ELS_ELS_KS9_KS9_UECDH_SHIFT              (19U)
+/*! KS9_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS9_KS9_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UECDH_SHIFT)) & ELS_ELS_KS9_KS9_UECDH_MASK)
+
+#define ELS_ELS_KS9_KS9_UAES_MASK                (0x100000U)
+#define ELS_ELS_KS9_KS9_UAES_SHIFT               (20U)
+/*! KS9_UAES - Aes key */
+#define ELS_ELS_KS9_KS9_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UAES_SHIFT)) & ELS_ELS_KS9_KS9_UAES_MASK)
+
+#define ELS_ELS_KS9_KS9_UHMAC_MASK               (0x200000U)
+#define ELS_ELS_KS9_KS9_UHMAC_SHIFT              (21U)
+/*! KS9_UHMAC - Hmac key */
+#define ELS_ELS_KS9_KS9_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UHMAC_SHIFT)) & ELS_ELS_KS9_KS9_UHMAC_MASK)
+
+#define ELS_ELS_KS9_KS9_UKWK_MASK                (0x400000U)
+#define ELS_ELS_KS9_KS9_UKWK_SHIFT               (22U)
+/*! KS9_UKWK - Key wrapping key */
+#define ELS_ELS_KS9_KS9_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKWK_SHIFT)) & ELS_ELS_KS9_KS9_UKWK_MASK)
+
+#define ELS_ELS_KS9_KS9_UKUOK_MASK               (0x800000U)
+#define ELS_ELS_KS9_KS9_UKUOK_SHIFT              (23U)
+/*! KS9_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS9_KS9_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKUOK_SHIFT)) & ELS_ELS_KS9_KS9_UKUOK_MASK)
+
+#define ELS_ELS_KS9_KS9_UTLSPMS_MASK             (0x1000000U)
+#define ELS_ELS_KS9_KS9_UTLSPMS_SHIFT            (24U)
+/*! KS9_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS9_KS9_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UTLSPMS_SHIFT)) & ELS_ELS_KS9_KS9_UTLSPMS_MASK)
+
+#define ELS_ELS_KS9_KS9_UTLSMS_MASK              (0x2000000U)
+#define ELS_ELS_KS9_KS9_UTLSMS_SHIFT             (25U)
+/*! KS9_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS9_KS9_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UTLSMS_SHIFT)) & ELS_ELS_KS9_KS9_UTLSMS_MASK)
+
+#define ELS_ELS_KS9_KS9_UKGSRC_MASK              (0x4000000U)
+#define ELS_ELS_KS9_KS9_UKGSRC_SHIFT             (26U)
+/*! KS9_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS9_KS9_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UKGSRC_SHIFT)) & ELS_ELS_KS9_KS9_UKGSRC_MASK)
+
+#define ELS_ELS_KS9_KS9_UHWO_MASK                (0x8000000U)
+#define ELS_ELS_KS9_KS9_UHWO_SHIFT               (27U)
+/*! KS9_UHWO - Hardware out key */
+#define ELS_ELS_KS9_KS9_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UHWO_SHIFT)) & ELS_ELS_KS9_KS9_UHWO_MASK)
+
+#define ELS_ELS_KS9_KS9_UWRPOK_MASK              (0x10000000U)
+#define ELS_ELS_KS9_KS9_UWRPOK_SHIFT             (28U)
+/*! KS9_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS9_KS9_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UWRPOK_SHIFT)) & ELS_ELS_KS9_KS9_UWRPOK_MASK)
+
+#define ELS_ELS_KS9_KS9_UDUK_MASK                (0x20000000U)
+#define ELS_ELS_KS9_KS9_UDUK_SHIFT               (29U)
+/*! KS9_UDUK - Device Unique Key */
+#define ELS_ELS_KS9_KS9_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UDUK_SHIFT)) & ELS_ELS_KS9_KS9_UDUK_MASK)
+
+#define ELS_ELS_KS9_KS9_UPPROT_MASK              (0xC0000000U)
+#define ELS_ELS_KS9_KS9_UPPROT_SHIFT             (30U)
+/*! KS9_UPPROT - Priviledge level */
+#define ELS_ELS_KS9_KS9_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS9_KS9_UPPROT_SHIFT)) & ELS_ELS_KS9_KS9_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS10 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS10_KS10_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS10_KS10_KSIZE_SHIFT            (0U)
+/*! KS10_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS10_KS10_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_KSIZE_SHIFT)) & ELS_ELS_KS10_KS10_KSIZE_MASK)
+
+#define ELS_ELS_KS10_KS10_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS10_KS10_RSVD0_SHIFT            (1U)
+/*! KS10_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS10_KS10_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_RSVD0_SHIFT)) & ELS_ELS_KS10_KS10_RSVD0_MASK)
+
+#define ELS_ELS_KS10_KS10_KACT_MASK              (0x20U)
+#define ELS_ELS_KS10_KS10_KACT_SHIFT             (5U)
+/*! KS10_KACT - Key is active */
+#define ELS_ELS_KS10_KS10_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_KACT_SHIFT)) & ELS_ELS_KS10_KS10_KACT_MASK)
+
+#define ELS_ELS_KS10_KS10_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS10_KS10_KBASE_SHIFT            (6U)
+/*! KS10_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS10_KS10_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_KBASE_SHIFT)) & ELS_ELS_KS10_KS10_KBASE_MASK)
+
+#define ELS_ELS_KS10_KS10_FGP_MASK               (0x80U)
+#define ELS_ELS_KS10_KS10_FGP_SHIFT              (7U)
+/*! KS10_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS10_KS10_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_FGP_SHIFT)) & ELS_ELS_KS10_KS10_FGP_MASK)
+
+#define ELS_ELS_KS10_KS10_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS10_KS10_FRTN_SHIFT             (8U)
+/*! KS10_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS10_KS10_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_FRTN_SHIFT)) & ELS_ELS_KS10_KS10_FRTN_MASK)
+
+#define ELS_ELS_KS10_KS10_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS10_KS10_FHWO_SHIFT             (9U)
+/*! KS10_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS10_KS10_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_FHWO_SHIFT)) & ELS_ELS_KS10_KS10_FHWO_MASK)
+
+#define ELS_ELS_KS10_KS10_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS10_KS10_RSVD1_SHIFT            (10U)
+/*! KS10_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS10_KS10_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_RSVD1_SHIFT)) & ELS_ELS_KS10_KS10_RSVD1_MASK)
+
+#define ELS_ELS_KS10_KS10_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS10_KS10_UCMAC_SHIFT            (13U)
+/*! KS10_UCMAC - CMAC key */
+#define ELS_ELS_KS10_KS10_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UCMAC_SHIFT)) & ELS_ELS_KS10_KS10_UCMAC_MASK)
+
+#define ELS_ELS_KS10_KS10_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS10_KS10_UKSK_SHIFT             (14U)
+/*! KS10_UKSK - KSK key */
+#define ELS_ELS_KS10_KS10_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKSK_SHIFT)) & ELS_ELS_KS10_KS10_UKSK_MASK)
+
+#define ELS_ELS_KS10_KS10_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS10_KS10_URTF_SHIFT             (15U)
+/*! KS10_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS10_KS10_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_URTF_SHIFT)) & ELS_ELS_KS10_KS10_URTF_MASK)
+
+#define ELS_ELS_KS10_KS10_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS10_KS10_UCKDF_SHIFT            (16U)
+/*! KS10_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS10_KS10_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UCKDF_SHIFT)) & ELS_ELS_KS10_KS10_UCKDF_MASK)
+
+#define ELS_ELS_KS10_KS10_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS10_KS10_UHKDF_SHIFT            (17U)
+/*! KS10_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS10_KS10_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UHKDF_SHIFT)) & ELS_ELS_KS10_KS10_UHKDF_MASK)
+
+#define ELS_ELS_KS10_KS10_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS10_KS10_UECSG_SHIFT            (18U)
+/*! KS10_UECSG - Ecc signing key */
+#define ELS_ELS_KS10_KS10_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UECSG_SHIFT)) & ELS_ELS_KS10_KS10_UECSG_MASK)
+
+#define ELS_ELS_KS10_KS10_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS10_KS10_UECDH_SHIFT            (19U)
+/*! KS10_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS10_KS10_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UECDH_SHIFT)) & ELS_ELS_KS10_KS10_UECDH_MASK)
+
+#define ELS_ELS_KS10_KS10_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS10_KS10_UAES_SHIFT             (20U)
+/*! KS10_UAES - Aes key */
+#define ELS_ELS_KS10_KS10_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UAES_SHIFT)) & ELS_ELS_KS10_KS10_UAES_MASK)
+
+#define ELS_ELS_KS10_KS10_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS10_KS10_UHMAC_SHIFT            (21U)
+/*! KS10_UHMAC - Hmac key */
+#define ELS_ELS_KS10_KS10_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UHMAC_SHIFT)) & ELS_ELS_KS10_KS10_UHMAC_MASK)
+
+#define ELS_ELS_KS10_KS10_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS10_KS10_UKWK_SHIFT             (22U)
+/*! KS10_UKWK - Key wrapping key */
+#define ELS_ELS_KS10_KS10_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKWK_SHIFT)) & ELS_ELS_KS10_KS10_UKWK_MASK)
+
+#define ELS_ELS_KS10_KS10_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS10_KS10_UKUOK_SHIFT            (23U)
+/*! KS10_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS10_KS10_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKUOK_SHIFT)) & ELS_ELS_KS10_KS10_UKUOK_MASK)
+
+#define ELS_ELS_KS10_KS10_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS10_KS10_UTLSPMS_SHIFT          (24U)
+/*! KS10_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS10_KS10_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UTLSPMS_SHIFT)) & ELS_ELS_KS10_KS10_UTLSPMS_MASK)
+
+#define ELS_ELS_KS10_KS10_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS10_KS10_UTLSMS_SHIFT           (25U)
+/*! KS10_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS10_KS10_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UTLSMS_SHIFT)) & ELS_ELS_KS10_KS10_UTLSMS_MASK)
+
+#define ELS_ELS_KS10_KS10_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS10_KS10_UKGSRC_SHIFT           (26U)
+/*! KS10_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS10_KS10_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UKGSRC_SHIFT)) & ELS_ELS_KS10_KS10_UKGSRC_MASK)
+
+#define ELS_ELS_KS10_KS10_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS10_KS10_UHWO_SHIFT             (27U)
+/*! KS10_UHWO - Hardware out key */
+#define ELS_ELS_KS10_KS10_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UHWO_SHIFT)) & ELS_ELS_KS10_KS10_UHWO_MASK)
+
+#define ELS_ELS_KS10_KS10_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS10_KS10_UWRPOK_SHIFT           (28U)
+/*! KS10_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS10_KS10_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UWRPOK_SHIFT)) & ELS_ELS_KS10_KS10_UWRPOK_MASK)
+
+#define ELS_ELS_KS10_KS10_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS10_KS10_UDUK_SHIFT             (29U)
+/*! KS10_UDUK - Device Unique Key */
+#define ELS_ELS_KS10_KS10_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UDUK_SHIFT)) & ELS_ELS_KS10_KS10_UDUK_MASK)
+
+#define ELS_ELS_KS10_KS10_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS10_KS10_UPPROT_SHIFT           (30U)
+/*! KS10_UPPROT - Priviledge level */
+#define ELS_ELS_KS10_KS10_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS10_KS10_UPPROT_SHIFT)) & ELS_ELS_KS10_KS10_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS11 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS11_KS11_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS11_KS11_KSIZE_SHIFT            (0U)
+/*! KS11_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS11_KS11_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_KSIZE_SHIFT)) & ELS_ELS_KS11_KS11_KSIZE_MASK)
+
+#define ELS_ELS_KS11_KS11_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS11_KS11_RSVD0_SHIFT            (1U)
+/*! KS11_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS11_KS11_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_RSVD0_SHIFT)) & ELS_ELS_KS11_KS11_RSVD0_MASK)
+
+#define ELS_ELS_KS11_KS11_KACT_MASK              (0x20U)
+#define ELS_ELS_KS11_KS11_KACT_SHIFT             (5U)
+/*! KS11_KACT - Key is active */
+#define ELS_ELS_KS11_KS11_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_KACT_SHIFT)) & ELS_ELS_KS11_KS11_KACT_MASK)
+
+#define ELS_ELS_KS11_KS11_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS11_KS11_KBASE_SHIFT            (6U)
+/*! KS11_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS11_KS11_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_KBASE_SHIFT)) & ELS_ELS_KS11_KS11_KBASE_MASK)
+
+#define ELS_ELS_KS11_KS11_FGP_MASK               (0x80U)
+#define ELS_ELS_KS11_KS11_FGP_SHIFT              (7U)
+/*! KS11_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS11_KS11_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_FGP_SHIFT)) & ELS_ELS_KS11_KS11_FGP_MASK)
+
+#define ELS_ELS_KS11_KS11_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS11_KS11_FRTN_SHIFT             (8U)
+/*! KS11_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS11_KS11_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_FRTN_SHIFT)) & ELS_ELS_KS11_KS11_FRTN_MASK)
+
+#define ELS_ELS_KS11_KS11_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS11_KS11_FHWO_SHIFT             (9U)
+/*! KS11_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS11_KS11_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_FHWO_SHIFT)) & ELS_ELS_KS11_KS11_FHWO_MASK)
+
+#define ELS_ELS_KS11_KS11_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS11_KS11_RSVD1_SHIFT            (10U)
+/*! KS11_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS11_KS11_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_RSVD1_SHIFT)) & ELS_ELS_KS11_KS11_RSVD1_MASK)
+
+#define ELS_ELS_KS11_KS11_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS11_KS11_UCMAC_SHIFT            (13U)
+/*! KS11_UCMAC - CMAC key */
+#define ELS_ELS_KS11_KS11_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UCMAC_SHIFT)) & ELS_ELS_KS11_KS11_UCMAC_MASK)
+
+#define ELS_ELS_KS11_KS11_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS11_KS11_UKSK_SHIFT             (14U)
+/*! KS11_UKSK - KSK key */
+#define ELS_ELS_KS11_KS11_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKSK_SHIFT)) & ELS_ELS_KS11_KS11_UKSK_MASK)
+
+#define ELS_ELS_KS11_KS11_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS11_KS11_URTF_SHIFT             (15U)
+/*! KS11_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS11_KS11_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_URTF_SHIFT)) & ELS_ELS_KS11_KS11_URTF_MASK)
+
+#define ELS_ELS_KS11_KS11_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS11_KS11_UCKDF_SHIFT            (16U)
+/*! KS11_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS11_KS11_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UCKDF_SHIFT)) & ELS_ELS_KS11_KS11_UCKDF_MASK)
+
+#define ELS_ELS_KS11_KS11_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS11_KS11_UHKDF_SHIFT            (17U)
+/*! KS11_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS11_KS11_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UHKDF_SHIFT)) & ELS_ELS_KS11_KS11_UHKDF_MASK)
+
+#define ELS_ELS_KS11_KS11_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS11_KS11_UECSG_SHIFT            (18U)
+/*! KS11_UECSG - Ecc signing key */
+#define ELS_ELS_KS11_KS11_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UECSG_SHIFT)) & ELS_ELS_KS11_KS11_UECSG_MASK)
+
+#define ELS_ELS_KS11_KS11_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS11_KS11_UECDH_SHIFT            (19U)
+/*! KS11_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS11_KS11_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UECDH_SHIFT)) & ELS_ELS_KS11_KS11_UECDH_MASK)
+
+#define ELS_ELS_KS11_KS11_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS11_KS11_UAES_SHIFT             (20U)
+/*! KS11_UAES - Aes key */
+#define ELS_ELS_KS11_KS11_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UAES_SHIFT)) & ELS_ELS_KS11_KS11_UAES_MASK)
+
+#define ELS_ELS_KS11_KS11_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS11_KS11_UHMAC_SHIFT            (21U)
+/*! KS11_UHMAC - Hmac key */
+#define ELS_ELS_KS11_KS11_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UHMAC_SHIFT)) & ELS_ELS_KS11_KS11_UHMAC_MASK)
+
+#define ELS_ELS_KS11_KS11_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS11_KS11_UKWK_SHIFT             (22U)
+/*! KS11_UKWK - Key wrapping key */
+#define ELS_ELS_KS11_KS11_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKWK_SHIFT)) & ELS_ELS_KS11_KS11_UKWK_MASK)
+
+#define ELS_ELS_KS11_KS11_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS11_KS11_UKUOK_SHIFT            (23U)
+/*! KS11_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS11_KS11_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKUOK_SHIFT)) & ELS_ELS_KS11_KS11_UKUOK_MASK)
+
+#define ELS_ELS_KS11_KS11_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS11_KS11_UTLSPMS_SHIFT          (24U)
+/*! KS11_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS11_KS11_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UTLSPMS_SHIFT)) & ELS_ELS_KS11_KS11_UTLSPMS_MASK)
+
+#define ELS_ELS_KS11_KS11_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS11_KS11_UTLSMS_SHIFT           (25U)
+/*! KS11_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS11_KS11_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UTLSMS_SHIFT)) & ELS_ELS_KS11_KS11_UTLSMS_MASK)
+
+#define ELS_ELS_KS11_KS11_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS11_KS11_UKGSRC_SHIFT           (26U)
+/*! KS11_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS11_KS11_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UKGSRC_SHIFT)) & ELS_ELS_KS11_KS11_UKGSRC_MASK)
+
+#define ELS_ELS_KS11_KS11_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS11_KS11_UHWO_SHIFT             (27U)
+/*! KS11_UHWO - Hardware out key */
+#define ELS_ELS_KS11_KS11_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UHWO_SHIFT)) & ELS_ELS_KS11_KS11_UHWO_MASK)
+
+#define ELS_ELS_KS11_KS11_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS11_KS11_UWRPOK_SHIFT           (28U)
+/*! KS11_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS11_KS11_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UWRPOK_SHIFT)) & ELS_ELS_KS11_KS11_UWRPOK_MASK)
+
+#define ELS_ELS_KS11_KS11_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS11_KS11_UDUK_SHIFT             (29U)
+/*! KS11_UDUK - Device Unique Key */
+#define ELS_ELS_KS11_KS11_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UDUK_SHIFT)) & ELS_ELS_KS11_KS11_UDUK_MASK)
+
+#define ELS_ELS_KS11_KS11_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS11_KS11_UPPROT_SHIFT           (30U)
+/*! KS11_UPPROT - Priviledge level */
+#define ELS_ELS_KS11_KS11_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS11_KS11_UPPROT_SHIFT)) & ELS_ELS_KS11_KS11_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS12 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS12_KS12_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS12_KS12_KSIZE_SHIFT            (0U)
+/*! KS12_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS12_KS12_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_KSIZE_SHIFT)) & ELS_ELS_KS12_KS12_KSIZE_MASK)
+
+#define ELS_ELS_KS12_KS12_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS12_KS12_RSVD0_SHIFT            (1U)
+/*! KS12_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS12_KS12_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_RSVD0_SHIFT)) & ELS_ELS_KS12_KS12_RSVD0_MASK)
+
+#define ELS_ELS_KS12_KS12_KACT_MASK              (0x20U)
+#define ELS_ELS_KS12_KS12_KACT_SHIFT             (5U)
+/*! KS12_KACT - Key is active */
+#define ELS_ELS_KS12_KS12_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_KACT_SHIFT)) & ELS_ELS_KS12_KS12_KACT_MASK)
+
+#define ELS_ELS_KS12_KS12_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS12_KS12_KBASE_SHIFT            (6U)
+/*! KS12_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS12_KS12_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_KBASE_SHIFT)) & ELS_ELS_KS12_KS12_KBASE_MASK)
+
+#define ELS_ELS_KS12_KS12_FGP_MASK               (0x80U)
+#define ELS_ELS_KS12_KS12_FGP_SHIFT              (7U)
+/*! KS12_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS12_KS12_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_FGP_SHIFT)) & ELS_ELS_KS12_KS12_FGP_MASK)
+
+#define ELS_ELS_KS12_KS12_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS12_KS12_FRTN_SHIFT             (8U)
+/*! KS12_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS12_KS12_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_FRTN_SHIFT)) & ELS_ELS_KS12_KS12_FRTN_MASK)
+
+#define ELS_ELS_KS12_KS12_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS12_KS12_FHWO_SHIFT             (9U)
+/*! KS12_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS12_KS12_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_FHWO_SHIFT)) & ELS_ELS_KS12_KS12_FHWO_MASK)
+
+#define ELS_ELS_KS12_KS12_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS12_KS12_RSVD1_SHIFT            (10U)
+/*! KS12_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS12_KS12_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_RSVD1_SHIFT)) & ELS_ELS_KS12_KS12_RSVD1_MASK)
+
+#define ELS_ELS_KS12_KS12_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS12_KS12_UCMAC_SHIFT            (13U)
+/*! KS12_UCMAC - CMAC key */
+#define ELS_ELS_KS12_KS12_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UCMAC_SHIFT)) & ELS_ELS_KS12_KS12_UCMAC_MASK)
+
+#define ELS_ELS_KS12_KS12_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS12_KS12_UKSK_SHIFT             (14U)
+/*! KS12_UKSK - KSK key */
+#define ELS_ELS_KS12_KS12_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKSK_SHIFT)) & ELS_ELS_KS12_KS12_UKSK_MASK)
+
+#define ELS_ELS_KS12_KS12_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS12_KS12_URTF_SHIFT             (15U)
+/*! KS12_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS12_KS12_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_URTF_SHIFT)) & ELS_ELS_KS12_KS12_URTF_MASK)
+
+#define ELS_ELS_KS12_KS12_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS12_KS12_UCKDF_SHIFT            (16U)
+/*! KS12_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS12_KS12_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UCKDF_SHIFT)) & ELS_ELS_KS12_KS12_UCKDF_MASK)
+
+#define ELS_ELS_KS12_KS12_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS12_KS12_UHKDF_SHIFT            (17U)
+/*! KS12_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS12_KS12_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UHKDF_SHIFT)) & ELS_ELS_KS12_KS12_UHKDF_MASK)
+
+#define ELS_ELS_KS12_KS12_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS12_KS12_UECSG_SHIFT            (18U)
+/*! KS12_UECSG - Ecc signing key */
+#define ELS_ELS_KS12_KS12_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UECSG_SHIFT)) & ELS_ELS_KS12_KS12_UECSG_MASK)
+
+#define ELS_ELS_KS12_KS12_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS12_KS12_UECDH_SHIFT            (19U)
+/*! KS12_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS12_KS12_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UECDH_SHIFT)) & ELS_ELS_KS12_KS12_UECDH_MASK)
+
+#define ELS_ELS_KS12_KS12_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS12_KS12_UAES_SHIFT             (20U)
+/*! KS12_UAES - Aes key */
+#define ELS_ELS_KS12_KS12_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UAES_SHIFT)) & ELS_ELS_KS12_KS12_UAES_MASK)
+
+#define ELS_ELS_KS12_KS12_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS12_KS12_UHMAC_SHIFT            (21U)
+/*! KS12_UHMAC - Hmac key */
+#define ELS_ELS_KS12_KS12_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UHMAC_SHIFT)) & ELS_ELS_KS12_KS12_UHMAC_MASK)
+
+#define ELS_ELS_KS12_KS12_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS12_KS12_UKWK_SHIFT             (22U)
+/*! KS12_UKWK - Key wrapping key */
+#define ELS_ELS_KS12_KS12_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKWK_SHIFT)) & ELS_ELS_KS12_KS12_UKWK_MASK)
+
+#define ELS_ELS_KS12_KS12_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS12_KS12_UKUOK_SHIFT            (23U)
+/*! KS12_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS12_KS12_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKUOK_SHIFT)) & ELS_ELS_KS12_KS12_UKUOK_MASK)
+
+#define ELS_ELS_KS12_KS12_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS12_KS12_UTLSPMS_SHIFT          (24U)
+/*! KS12_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS12_KS12_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UTLSPMS_SHIFT)) & ELS_ELS_KS12_KS12_UTLSPMS_MASK)
+
+#define ELS_ELS_KS12_KS12_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS12_KS12_UTLSMS_SHIFT           (25U)
+/*! KS12_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS12_KS12_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UTLSMS_SHIFT)) & ELS_ELS_KS12_KS12_UTLSMS_MASK)
+
+#define ELS_ELS_KS12_KS12_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS12_KS12_UKGSRC_SHIFT           (26U)
+/*! KS12_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS12_KS12_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UKGSRC_SHIFT)) & ELS_ELS_KS12_KS12_UKGSRC_MASK)
+
+#define ELS_ELS_KS12_KS12_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS12_KS12_UHWO_SHIFT             (27U)
+/*! KS12_UHWO - Hardware out key */
+#define ELS_ELS_KS12_KS12_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UHWO_SHIFT)) & ELS_ELS_KS12_KS12_UHWO_MASK)
+
+#define ELS_ELS_KS12_KS12_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS12_KS12_UWRPOK_SHIFT           (28U)
+/*! KS12_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS12_KS12_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UWRPOK_SHIFT)) & ELS_ELS_KS12_KS12_UWRPOK_MASK)
+
+#define ELS_ELS_KS12_KS12_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS12_KS12_UDUK_SHIFT             (29U)
+/*! KS12_UDUK - Device Unique Key */
+#define ELS_ELS_KS12_KS12_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UDUK_SHIFT)) & ELS_ELS_KS12_KS12_UDUK_MASK)
+
+#define ELS_ELS_KS12_KS12_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS12_KS12_UPPROT_SHIFT           (30U)
+/*! KS12_UPPROT - Priviledge level */
+#define ELS_ELS_KS12_KS12_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS12_KS12_UPPROT_SHIFT)) & ELS_ELS_KS12_KS12_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS13 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS13_KS13_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS13_KS13_KSIZE_SHIFT            (0U)
+/*! KS13_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS13_KS13_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_KSIZE_SHIFT)) & ELS_ELS_KS13_KS13_KSIZE_MASK)
+
+#define ELS_ELS_KS13_KS13_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS13_KS13_RSVD0_SHIFT            (1U)
+/*! KS13_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS13_KS13_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_RSVD0_SHIFT)) & ELS_ELS_KS13_KS13_RSVD0_MASK)
+
+#define ELS_ELS_KS13_KS13_KACT_MASK              (0x20U)
+#define ELS_ELS_KS13_KS13_KACT_SHIFT             (5U)
+/*! KS13_KACT - Key is active */
+#define ELS_ELS_KS13_KS13_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_KACT_SHIFT)) & ELS_ELS_KS13_KS13_KACT_MASK)
+
+#define ELS_ELS_KS13_KS13_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS13_KS13_KBASE_SHIFT            (6U)
+/*! KS13_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS13_KS13_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_KBASE_SHIFT)) & ELS_ELS_KS13_KS13_KBASE_MASK)
+
+#define ELS_ELS_KS13_KS13_FGP_MASK               (0x80U)
+#define ELS_ELS_KS13_KS13_FGP_SHIFT              (7U)
+/*! KS13_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS13_KS13_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_FGP_SHIFT)) & ELS_ELS_KS13_KS13_FGP_MASK)
+
+#define ELS_ELS_KS13_KS13_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS13_KS13_FRTN_SHIFT             (8U)
+/*! KS13_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS13_KS13_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_FRTN_SHIFT)) & ELS_ELS_KS13_KS13_FRTN_MASK)
+
+#define ELS_ELS_KS13_KS13_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS13_KS13_FHWO_SHIFT             (9U)
+/*! KS13_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS13_KS13_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_FHWO_SHIFT)) & ELS_ELS_KS13_KS13_FHWO_MASK)
+
+#define ELS_ELS_KS13_KS13_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS13_KS13_RSVD1_SHIFT            (10U)
+/*! KS13_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS13_KS13_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_RSVD1_SHIFT)) & ELS_ELS_KS13_KS13_RSVD1_MASK)
+
+#define ELS_ELS_KS13_KS13_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS13_KS13_UCMAC_SHIFT            (13U)
+/*! KS13_UCMAC - CMAC key */
+#define ELS_ELS_KS13_KS13_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UCMAC_SHIFT)) & ELS_ELS_KS13_KS13_UCMAC_MASK)
+
+#define ELS_ELS_KS13_KS13_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS13_KS13_UKSK_SHIFT             (14U)
+/*! KS13_UKSK - KSK key */
+#define ELS_ELS_KS13_KS13_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKSK_SHIFT)) & ELS_ELS_KS13_KS13_UKSK_MASK)
+
+#define ELS_ELS_KS13_KS13_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS13_KS13_URTF_SHIFT             (15U)
+/*! KS13_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS13_KS13_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_URTF_SHIFT)) & ELS_ELS_KS13_KS13_URTF_MASK)
+
+#define ELS_ELS_KS13_KS13_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS13_KS13_UCKDF_SHIFT            (16U)
+/*! KS13_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS13_KS13_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UCKDF_SHIFT)) & ELS_ELS_KS13_KS13_UCKDF_MASK)
+
+#define ELS_ELS_KS13_KS13_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS13_KS13_UHKDF_SHIFT            (17U)
+/*! KS13_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS13_KS13_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UHKDF_SHIFT)) & ELS_ELS_KS13_KS13_UHKDF_MASK)
+
+#define ELS_ELS_KS13_KS13_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS13_KS13_UECSG_SHIFT            (18U)
+/*! KS13_UECSG - Ecc signing key */
+#define ELS_ELS_KS13_KS13_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UECSG_SHIFT)) & ELS_ELS_KS13_KS13_UECSG_MASK)
+
+#define ELS_ELS_KS13_KS13_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS13_KS13_UECDH_SHIFT            (19U)
+/*! KS13_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS13_KS13_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UECDH_SHIFT)) & ELS_ELS_KS13_KS13_UECDH_MASK)
+
+#define ELS_ELS_KS13_KS13_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS13_KS13_UAES_SHIFT             (20U)
+/*! KS13_UAES - Aes key */
+#define ELS_ELS_KS13_KS13_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UAES_SHIFT)) & ELS_ELS_KS13_KS13_UAES_MASK)
+
+#define ELS_ELS_KS13_KS13_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS13_KS13_UHMAC_SHIFT            (21U)
+/*! KS13_UHMAC - Hmac key */
+#define ELS_ELS_KS13_KS13_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UHMAC_SHIFT)) & ELS_ELS_KS13_KS13_UHMAC_MASK)
+
+#define ELS_ELS_KS13_KS13_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS13_KS13_UKWK_SHIFT             (22U)
+/*! KS13_UKWK - Key wrapping key */
+#define ELS_ELS_KS13_KS13_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKWK_SHIFT)) & ELS_ELS_KS13_KS13_UKWK_MASK)
+
+#define ELS_ELS_KS13_KS13_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS13_KS13_UKUOK_SHIFT            (23U)
+/*! KS13_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS13_KS13_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKUOK_SHIFT)) & ELS_ELS_KS13_KS13_UKUOK_MASK)
+
+#define ELS_ELS_KS13_KS13_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS13_KS13_UTLSPMS_SHIFT          (24U)
+/*! KS13_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS13_KS13_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UTLSPMS_SHIFT)) & ELS_ELS_KS13_KS13_UTLSPMS_MASK)
+
+#define ELS_ELS_KS13_KS13_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS13_KS13_UTLSMS_SHIFT           (25U)
+/*! KS13_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS13_KS13_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UTLSMS_SHIFT)) & ELS_ELS_KS13_KS13_UTLSMS_MASK)
+
+#define ELS_ELS_KS13_KS13_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS13_KS13_UKGSRC_SHIFT           (26U)
+/*! KS13_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS13_KS13_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UKGSRC_SHIFT)) & ELS_ELS_KS13_KS13_UKGSRC_MASK)
+
+#define ELS_ELS_KS13_KS13_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS13_KS13_UHWO_SHIFT             (27U)
+/*! KS13_UHWO - Hardware out key */
+#define ELS_ELS_KS13_KS13_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UHWO_SHIFT)) & ELS_ELS_KS13_KS13_UHWO_MASK)
+
+#define ELS_ELS_KS13_KS13_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS13_KS13_UWRPOK_SHIFT           (28U)
+/*! KS13_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS13_KS13_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UWRPOK_SHIFT)) & ELS_ELS_KS13_KS13_UWRPOK_MASK)
+
+#define ELS_ELS_KS13_KS13_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS13_KS13_UDUK_SHIFT             (29U)
+/*! KS13_UDUK - Device Unique Key */
+#define ELS_ELS_KS13_KS13_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UDUK_SHIFT)) & ELS_ELS_KS13_KS13_UDUK_MASK)
+
+#define ELS_ELS_KS13_KS13_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS13_KS13_UPPROT_SHIFT           (30U)
+/*! KS13_UPPROT - Priviledge level */
+#define ELS_ELS_KS13_KS13_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS13_KS13_UPPROT_SHIFT)) & ELS_ELS_KS13_KS13_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS14 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS14_KS14_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS14_KS14_KSIZE_SHIFT            (0U)
+/*! KS14_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS14_KS14_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_KSIZE_SHIFT)) & ELS_ELS_KS14_KS14_KSIZE_MASK)
+
+#define ELS_ELS_KS14_KS14_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS14_KS14_RSVD0_SHIFT            (1U)
+/*! KS14_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS14_KS14_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_RSVD0_SHIFT)) & ELS_ELS_KS14_KS14_RSVD0_MASK)
+
+#define ELS_ELS_KS14_KS14_KACT_MASK              (0x20U)
+#define ELS_ELS_KS14_KS14_KACT_SHIFT             (5U)
+/*! KS14_KACT - Key is active */
+#define ELS_ELS_KS14_KS14_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_KACT_SHIFT)) & ELS_ELS_KS14_KS14_KACT_MASK)
+
+#define ELS_ELS_KS14_KS14_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS14_KS14_KBASE_SHIFT            (6U)
+/*! KS14_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS14_KS14_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_KBASE_SHIFT)) & ELS_ELS_KS14_KS14_KBASE_MASK)
+
+#define ELS_ELS_KS14_KS14_FGP_MASK               (0x80U)
+#define ELS_ELS_KS14_KS14_FGP_SHIFT              (7U)
+/*! KS14_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS14_KS14_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_FGP_SHIFT)) & ELS_ELS_KS14_KS14_FGP_MASK)
+
+#define ELS_ELS_KS14_KS14_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS14_KS14_FRTN_SHIFT             (8U)
+/*! KS14_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS14_KS14_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_FRTN_SHIFT)) & ELS_ELS_KS14_KS14_FRTN_MASK)
+
+#define ELS_ELS_KS14_KS14_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS14_KS14_FHWO_SHIFT             (9U)
+/*! KS14_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS14_KS14_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_FHWO_SHIFT)) & ELS_ELS_KS14_KS14_FHWO_MASK)
+
+#define ELS_ELS_KS14_KS14_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS14_KS14_RSVD1_SHIFT            (10U)
+/*! KS14_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS14_KS14_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_RSVD1_SHIFT)) & ELS_ELS_KS14_KS14_RSVD1_MASK)
+
+#define ELS_ELS_KS14_KS14_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS14_KS14_UCMAC_SHIFT            (13U)
+/*! KS14_UCMAC - CMAC key */
+#define ELS_ELS_KS14_KS14_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UCMAC_SHIFT)) & ELS_ELS_KS14_KS14_UCMAC_MASK)
+
+#define ELS_ELS_KS14_KS14_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS14_KS14_UKSK_SHIFT             (14U)
+/*! KS14_UKSK - KSK key */
+#define ELS_ELS_KS14_KS14_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKSK_SHIFT)) & ELS_ELS_KS14_KS14_UKSK_MASK)
+
+#define ELS_ELS_KS14_KS14_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS14_KS14_URTF_SHIFT             (15U)
+/*! KS14_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS14_KS14_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_URTF_SHIFT)) & ELS_ELS_KS14_KS14_URTF_MASK)
+
+#define ELS_ELS_KS14_KS14_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS14_KS14_UCKDF_SHIFT            (16U)
+/*! KS14_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS14_KS14_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UCKDF_SHIFT)) & ELS_ELS_KS14_KS14_UCKDF_MASK)
+
+#define ELS_ELS_KS14_KS14_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS14_KS14_UHKDF_SHIFT            (17U)
+/*! KS14_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS14_KS14_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UHKDF_SHIFT)) & ELS_ELS_KS14_KS14_UHKDF_MASK)
+
+#define ELS_ELS_KS14_KS14_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS14_KS14_UECSG_SHIFT            (18U)
+/*! KS14_UECSG - Ecc signing key */
+#define ELS_ELS_KS14_KS14_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UECSG_SHIFT)) & ELS_ELS_KS14_KS14_UECSG_MASK)
+
+#define ELS_ELS_KS14_KS14_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS14_KS14_UECDH_SHIFT            (19U)
+/*! KS14_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS14_KS14_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UECDH_SHIFT)) & ELS_ELS_KS14_KS14_UECDH_MASK)
+
+#define ELS_ELS_KS14_KS14_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS14_KS14_UAES_SHIFT             (20U)
+/*! KS14_UAES - Aes key */
+#define ELS_ELS_KS14_KS14_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UAES_SHIFT)) & ELS_ELS_KS14_KS14_UAES_MASK)
+
+#define ELS_ELS_KS14_KS14_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS14_KS14_UHMAC_SHIFT            (21U)
+/*! KS14_UHMAC - Hmac key */
+#define ELS_ELS_KS14_KS14_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UHMAC_SHIFT)) & ELS_ELS_KS14_KS14_UHMAC_MASK)
+
+#define ELS_ELS_KS14_KS14_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS14_KS14_UKWK_SHIFT             (22U)
+/*! KS14_UKWK - Key wrapping key */
+#define ELS_ELS_KS14_KS14_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKWK_SHIFT)) & ELS_ELS_KS14_KS14_UKWK_MASK)
+
+#define ELS_ELS_KS14_KS14_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS14_KS14_UKUOK_SHIFT            (23U)
+/*! KS14_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS14_KS14_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKUOK_SHIFT)) & ELS_ELS_KS14_KS14_UKUOK_MASK)
+
+#define ELS_ELS_KS14_KS14_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS14_KS14_UTLSPMS_SHIFT          (24U)
+/*! KS14_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS14_KS14_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UTLSPMS_SHIFT)) & ELS_ELS_KS14_KS14_UTLSPMS_MASK)
+
+#define ELS_ELS_KS14_KS14_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS14_KS14_UTLSMS_SHIFT           (25U)
+/*! KS14_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS14_KS14_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UTLSMS_SHIFT)) & ELS_ELS_KS14_KS14_UTLSMS_MASK)
+
+#define ELS_ELS_KS14_KS14_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS14_KS14_UKGSRC_SHIFT           (26U)
+/*! KS14_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS14_KS14_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UKGSRC_SHIFT)) & ELS_ELS_KS14_KS14_UKGSRC_MASK)
+
+#define ELS_ELS_KS14_KS14_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS14_KS14_UHWO_SHIFT             (27U)
+/*! KS14_UHWO - Hardware out key */
+#define ELS_ELS_KS14_KS14_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UHWO_SHIFT)) & ELS_ELS_KS14_KS14_UHWO_MASK)
+
+#define ELS_ELS_KS14_KS14_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS14_KS14_UWRPOK_SHIFT           (28U)
+/*! KS14_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS14_KS14_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UWRPOK_SHIFT)) & ELS_ELS_KS14_KS14_UWRPOK_MASK)
+
+#define ELS_ELS_KS14_KS14_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS14_KS14_UDUK_SHIFT             (29U)
+/*! KS14_UDUK - Device Unique Key */
+#define ELS_ELS_KS14_KS14_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UDUK_SHIFT)) & ELS_ELS_KS14_KS14_UDUK_MASK)
+
+#define ELS_ELS_KS14_KS14_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS14_KS14_UPPROT_SHIFT           (30U)
+/*! KS14_UPPROT - Priviledge level */
+#define ELS_ELS_KS14_KS14_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS14_KS14_UPPROT_SHIFT)) & ELS_ELS_KS14_KS14_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS15 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS15_KS15_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS15_KS15_KSIZE_SHIFT            (0U)
+/*! KS15_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS15_KS15_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_KSIZE_SHIFT)) & ELS_ELS_KS15_KS15_KSIZE_MASK)
+
+#define ELS_ELS_KS15_KS15_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS15_KS15_RSVD0_SHIFT            (1U)
+/*! KS15_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS15_KS15_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_RSVD0_SHIFT)) & ELS_ELS_KS15_KS15_RSVD0_MASK)
+
+#define ELS_ELS_KS15_KS15_KACT_MASK              (0x20U)
+#define ELS_ELS_KS15_KS15_KACT_SHIFT             (5U)
+/*! KS15_KACT - Key is active */
+#define ELS_ELS_KS15_KS15_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_KACT_SHIFT)) & ELS_ELS_KS15_KS15_KACT_MASK)
+
+#define ELS_ELS_KS15_KS15_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS15_KS15_KBASE_SHIFT            (6U)
+/*! KS15_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS15_KS15_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_KBASE_SHIFT)) & ELS_ELS_KS15_KS15_KBASE_MASK)
+
+#define ELS_ELS_KS15_KS15_FGP_MASK               (0x80U)
+#define ELS_ELS_KS15_KS15_FGP_SHIFT              (7U)
+/*! KS15_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS15_KS15_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_FGP_SHIFT)) & ELS_ELS_KS15_KS15_FGP_MASK)
+
+#define ELS_ELS_KS15_KS15_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS15_KS15_FRTN_SHIFT             (8U)
+/*! KS15_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS15_KS15_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_FRTN_SHIFT)) & ELS_ELS_KS15_KS15_FRTN_MASK)
+
+#define ELS_ELS_KS15_KS15_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS15_KS15_FHWO_SHIFT             (9U)
+/*! KS15_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS15_KS15_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_FHWO_SHIFT)) & ELS_ELS_KS15_KS15_FHWO_MASK)
+
+#define ELS_ELS_KS15_KS15_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS15_KS15_RSVD1_SHIFT            (10U)
+/*! KS15_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS15_KS15_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_RSVD1_SHIFT)) & ELS_ELS_KS15_KS15_RSVD1_MASK)
+
+#define ELS_ELS_KS15_KS15_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS15_KS15_UCMAC_SHIFT            (13U)
+/*! KS15_UCMAC - CMAC key */
+#define ELS_ELS_KS15_KS15_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UCMAC_SHIFT)) & ELS_ELS_KS15_KS15_UCMAC_MASK)
+
+#define ELS_ELS_KS15_KS15_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS15_KS15_UKSK_SHIFT             (14U)
+/*! KS15_UKSK - KSK key */
+#define ELS_ELS_KS15_KS15_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKSK_SHIFT)) & ELS_ELS_KS15_KS15_UKSK_MASK)
+
+#define ELS_ELS_KS15_KS15_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS15_KS15_URTF_SHIFT             (15U)
+/*! KS15_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS15_KS15_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_URTF_SHIFT)) & ELS_ELS_KS15_KS15_URTF_MASK)
+
+#define ELS_ELS_KS15_KS15_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS15_KS15_UCKDF_SHIFT            (16U)
+/*! KS15_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS15_KS15_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UCKDF_SHIFT)) & ELS_ELS_KS15_KS15_UCKDF_MASK)
+
+#define ELS_ELS_KS15_KS15_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS15_KS15_UHKDF_SHIFT            (17U)
+/*! KS15_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS15_KS15_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UHKDF_SHIFT)) & ELS_ELS_KS15_KS15_UHKDF_MASK)
+
+#define ELS_ELS_KS15_KS15_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS15_KS15_UECSG_SHIFT            (18U)
+/*! KS15_UECSG - Ecc signing key */
+#define ELS_ELS_KS15_KS15_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UECSG_SHIFT)) & ELS_ELS_KS15_KS15_UECSG_MASK)
+
+#define ELS_ELS_KS15_KS15_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS15_KS15_UECDH_SHIFT            (19U)
+/*! KS15_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS15_KS15_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UECDH_SHIFT)) & ELS_ELS_KS15_KS15_UECDH_MASK)
+
+#define ELS_ELS_KS15_KS15_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS15_KS15_UAES_SHIFT             (20U)
+/*! KS15_UAES - Aes key */
+#define ELS_ELS_KS15_KS15_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UAES_SHIFT)) & ELS_ELS_KS15_KS15_UAES_MASK)
+
+#define ELS_ELS_KS15_KS15_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS15_KS15_UHMAC_SHIFT            (21U)
+/*! KS15_UHMAC - Hmac key */
+#define ELS_ELS_KS15_KS15_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UHMAC_SHIFT)) & ELS_ELS_KS15_KS15_UHMAC_MASK)
+
+#define ELS_ELS_KS15_KS15_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS15_KS15_UKWK_SHIFT             (22U)
+/*! KS15_UKWK - Key wrapping key */
+#define ELS_ELS_KS15_KS15_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKWK_SHIFT)) & ELS_ELS_KS15_KS15_UKWK_MASK)
+
+#define ELS_ELS_KS15_KS15_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS15_KS15_UKUOK_SHIFT            (23U)
+/*! KS15_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS15_KS15_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKUOK_SHIFT)) & ELS_ELS_KS15_KS15_UKUOK_MASK)
+
+#define ELS_ELS_KS15_KS15_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS15_KS15_UTLSPMS_SHIFT          (24U)
+/*! KS15_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS15_KS15_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UTLSPMS_SHIFT)) & ELS_ELS_KS15_KS15_UTLSPMS_MASK)
+
+#define ELS_ELS_KS15_KS15_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS15_KS15_UTLSMS_SHIFT           (25U)
+/*! KS15_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS15_KS15_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UTLSMS_SHIFT)) & ELS_ELS_KS15_KS15_UTLSMS_MASK)
+
+#define ELS_ELS_KS15_KS15_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS15_KS15_UKGSRC_SHIFT           (26U)
+/*! KS15_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS15_KS15_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UKGSRC_SHIFT)) & ELS_ELS_KS15_KS15_UKGSRC_MASK)
+
+#define ELS_ELS_KS15_KS15_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS15_KS15_UHWO_SHIFT             (27U)
+/*! KS15_UHWO - Hardware out key */
+#define ELS_ELS_KS15_KS15_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UHWO_SHIFT)) & ELS_ELS_KS15_KS15_UHWO_MASK)
+
+#define ELS_ELS_KS15_KS15_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS15_KS15_UWRPOK_SHIFT           (28U)
+/*! KS15_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS15_KS15_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UWRPOK_SHIFT)) & ELS_ELS_KS15_KS15_UWRPOK_MASK)
+
+#define ELS_ELS_KS15_KS15_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS15_KS15_UDUK_SHIFT             (29U)
+/*! KS15_UDUK - Device Unique Key */
+#define ELS_ELS_KS15_KS15_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UDUK_SHIFT)) & ELS_ELS_KS15_KS15_UDUK_MASK)
+
+#define ELS_ELS_KS15_KS15_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS15_KS15_UPPROT_SHIFT           (30U)
+/*! KS15_UPPROT - Priviledge level */
+#define ELS_ELS_KS15_KS15_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS15_KS15_UPPROT_SHIFT)) & ELS_ELS_KS15_KS15_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS16 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS16_KS16_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS16_KS16_KSIZE_SHIFT            (0U)
+/*! KS16_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS16_KS16_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_KSIZE_SHIFT)) & ELS_ELS_KS16_KS16_KSIZE_MASK)
+
+#define ELS_ELS_KS16_KS16_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS16_KS16_RSVD0_SHIFT            (1U)
+/*! KS16_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS16_KS16_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_RSVD0_SHIFT)) & ELS_ELS_KS16_KS16_RSVD0_MASK)
+
+#define ELS_ELS_KS16_KS16_KACT_MASK              (0x20U)
+#define ELS_ELS_KS16_KS16_KACT_SHIFT             (5U)
+/*! KS16_KACT - Key is active */
+#define ELS_ELS_KS16_KS16_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_KACT_SHIFT)) & ELS_ELS_KS16_KS16_KACT_MASK)
+
+#define ELS_ELS_KS16_KS16_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS16_KS16_KBASE_SHIFT            (6U)
+/*! KS16_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS16_KS16_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_KBASE_SHIFT)) & ELS_ELS_KS16_KS16_KBASE_MASK)
+
+#define ELS_ELS_KS16_KS16_FGP_MASK               (0x80U)
+#define ELS_ELS_KS16_KS16_FGP_SHIFT              (7U)
+/*! KS16_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS16_KS16_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_FGP_SHIFT)) & ELS_ELS_KS16_KS16_FGP_MASK)
+
+#define ELS_ELS_KS16_KS16_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS16_KS16_FRTN_SHIFT             (8U)
+/*! KS16_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS16_KS16_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_FRTN_SHIFT)) & ELS_ELS_KS16_KS16_FRTN_MASK)
+
+#define ELS_ELS_KS16_KS16_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS16_KS16_FHWO_SHIFT             (9U)
+/*! KS16_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS16_KS16_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_FHWO_SHIFT)) & ELS_ELS_KS16_KS16_FHWO_MASK)
+
+#define ELS_ELS_KS16_KS16_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS16_KS16_RSVD1_SHIFT            (10U)
+/*! KS16_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS16_KS16_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_RSVD1_SHIFT)) & ELS_ELS_KS16_KS16_RSVD1_MASK)
+
+#define ELS_ELS_KS16_KS16_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS16_KS16_UCMAC_SHIFT            (13U)
+/*! KS16_UCMAC - CMAC key */
+#define ELS_ELS_KS16_KS16_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UCMAC_SHIFT)) & ELS_ELS_KS16_KS16_UCMAC_MASK)
+
+#define ELS_ELS_KS16_KS16_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS16_KS16_UKSK_SHIFT             (14U)
+/*! KS16_UKSK - KSK key */
+#define ELS_ELS_KS16_KS16_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKSK_SHIFT)) & ELS_ELS_KS16_KS16_UKSK_MASK)
+
+#define ELS_ELS_KS16_KS16_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS16_KS16_URTF_SHIFT             (15U)
+/*! KS16_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS16_KS16_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_URTF_SHIFT)) & ELS_ELS_KS16_KS16_URTF_MASK)
+
+#define ELS_ELS_KS16_KS16_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS16_KS16_UCKDF_SHIFT            (16U)
+/*! KS16_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS16_KS16_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UCKDF_SHIFT)) & ELS_ELS_KS16_KS16_UCKDF_MASK)
+
+#define ELS_ELS_KS16_KS16_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS16_KS16_UHKDF_SHIFT            (17U)
+/*! KS16_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS16_KS16_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UHKDF_SHIFT)) & ELS_ELS_KS16_KS16_UHKDF_MASK)
+
+#define ELS_ELS_KS16_KS16_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS16_KS16_UECSG_SHIFT            (18U)
+/*! KS16_UECSG - Ecc signing key */
+#define ELS_ELS_KS16_KS16_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UECSG_SHIFT)) & ELS_ELS_KS16_KS16_UECSG_MASK)
+
+#define ELS_ELS_KS16_KS16_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS16_KS16_UECDH_SHIFT            (19U)
+/*! KS16_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS16_KS16_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UECDH_SHIFT)) & ELS_ELS_KS16_KS16_UECDH_MASK)
+
+#define ELS_ELS_KS16_KS16_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS16_KS16_UAES_SHIFT             (20U)
+/*! KS16_UAES - Aes key */
+#define ELS_ELS_KS16_KS16_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UAES_SHIFT)) & ELS_ELS_KS16_KS16_UAES_MASK)
+
+#define ELS_ELS_KS16_KS16_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS16_KS16_UHMAC_SHIFT            (21U)
+/*! KS16_UHMAC - Hmac key */
+#define ELS_ELS_KS16_KS16_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UHMAC_SHIFT)) & ELS_ELS_KS16_KS16_UHMAC_MASK)
+
+#define ELS_ELS_KS16_KS16_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS16_KS16_UKWK_SHIFT             (22U)
+/*! KS16_UKWK - Key wrapping key */
+#define ELS_ELS_KS16_KS16_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKWK_SHIFT)) & ELS_ELS_KS16_KS16_UKWK_MASK)
+
+#define ELS_ELS_KS16_KS16_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS16_KS16_UKUOK_SHIFT            (23U)
+/*! KS16_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS16_KS16_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKUOK_SHIFT)) & ELS_ELS_KS16_KS16_UKUOK_MASK)
+
+#define ELS_ELS_KS16_KS16_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS16_KS16_UTLSPMS_SHIFT          (24U)
+/*! KS16_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS16_KS16_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UTLSPMS_SHIFT)) & ELS_ELS_KS16_KS16_UTLSPMS_MASK)
+
+#define ELS_ELS_KS16_KS16_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS16_KS16_UTLSMS_SHIFT           (25U)
+/*! KS16_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS16_KS16_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UTLSMS_SHIFT)) & ELS_ELS_KS16_KS16_UTLSMS_MASK)
+
+#define ELS_ELS_KS16_KS16_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS16_KS16_UKGSRC_SHIFT           (26U)
+/*! KS16_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS16_KS16_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UKGSRC_SHIFT)) & ELS_ELS_KS16_KS16_UKGSRC_MASK)
+
+#define ELS_ELS_KS16_KS16_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS16_KS16_UHWO_SHIFT             (27U)
+/*! KS16_UHWO - Hardware out key */
+#define ELS_ELS_KS16_KS16_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UHWO_SHIFT)) & ELS_ELS_KS16_KS16_UHWO_MASK)
+
+#define ELS_ELS_KS16_KS16_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS16_KS16_UWRPOK_SHIFT           (28U)
+/*! KS16_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS16_KS16_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UWRPOK_SHIFT)) & ELS_ELS_KS16_KS16_UWRPOK_MASK)
+
+#define ELS_ELS_KS16_KS16_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS16_KS16_UDUK_SHIFT             (29U)
+/*! KS16_UDUK - Device Unique Key */
+#define ELS_ELS_KS16_KS16_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UDUK_SHIFT)) & ELS_ELS_KS16_KS16_UDUK_MASK)
+
+#define ELS_ELS_KS16_KS16_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS16_KS16_UPPROT_SHIFT           (30U)
+/*! KS16_UPPROT - Priviledge level */
+#define ELS_ELS_KS16_KS16_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS16_KS16_UPPROT_SHIFT)) & ELS_ELS_KS16_KS16_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS17 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS17_KS17_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS17_KS17_KSIZE_SHIFT            (0U)
+/*! KS17_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS17_KS17_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_KSIZE_SHIFT)) & ELS_ELS_KS17_KS17_KSIZE_MASK)
+
+#define ELS_ELS_KS17_KS17_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS17_KS17_RSVD0_SHIFT            (1U)
+/*! KS17_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS17_KS17_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_RSVD0_SHIFT)) & ELS_ELS_KS17_KS17_RSVD0_MASK)
+
+#define ELS_ELS_KS17_KS17_KACT_MASK              (0x20U)
+#define ELS_ELS_KS17_KS17_KACT_SHIFT             (5U)
+/*! KS17_KACT - Key is active */
+#define ELS_ELS_KS17_KS17_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_KACT_SHIFT)) & ELS_ELS_KS17_KS17_KACT_MASK)
+
+#define ELS_ELS_KS17_KS17_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS17_KS17_KBASE_SHIFT            (6U)
+/*! KS17_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS17_KS17_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_KBASE_SHIFT)) & ELS_ELS_KS17_KS17_KBASE_MASK)
+
+#define ELS_ELS_KS17_KS17_FGP_MASK               (0x80U)
+#define ELS_ELS_KS17_KS17_FGP_SHIFT              (7U)
+/*! KS17_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS17_KS17_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_FGP_SHIFT)) & ELS_ELS_KS17_KS17_FGP_MASK)
+
+#define ELS_ELS_KS17_KS17_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS17_KS17_FRTN_SHIFT             (8U)
+/*! KS17_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS17_KS17_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_FRTN_SHIFT)) & ELS_ELS_KS17_KS17_FRTN_MASK)
+
+#define ELS_ELS_KS17_KS17_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS17_KS17_FHWO_SHIFT             (9U)
+/*! KS17_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS17_KS17_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_FHWO_SHIFT)) & ELS_ELS_KS17_KS17_FHWO_MASK)
+
+#define ELS_ELS_KS17_KS17_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS17_KS17_RSVD1_SHIFT            (10U)
+/*! KS17_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS17_KS17_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_RSVD1_SHIFT)) & ELS_ELS_KS17_KS17_RSVD1_MASK)
+
+#define ELS_ELS_KS17_KS17_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS17_KS17_UCMAC_SHIFT            (13U)
+/*! KS17_UCMAC - CMAC key */
+#define ELS_ELS_KS17_KS17_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UCMAC_SHIFT)) & ELS_ELS_KS17_KS17_UCMAC_MASK)
+
+#define ELS_ELS_KS17_KS17_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS17_KS17_UKSK_SHIFT             (14U)
+/*! KS17_UKSK - KSK key */
+#define ELS_ELS_KS17_KS17_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKSK_SHIFT)) & ELS_ELS_KS17_KS17_UKSK_MASK)
+
+#define ELS_ELS_KS17_KS17_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS17_KS17_URTF_SHIFT             (15U)
+/*! KS17_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS17_KS17_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_URTF_SHIFT)) & ELS_ELS_KS17_KS17_URTF_MASK)
+
+#define ELS_ELS_KS17_KS17_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS17_KS17_UCKDF_SHIFT            (16U)
+/*! KS17_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS17_KS17_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UCKDF_SHIFT)) & ELS_ELS_KS17_KS17_UCKDF_MASK)
+
+#define ELS_ELS_KS17_KS17_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS17_KS17_UHKDF_SHIFT            (17U)
+/*! KS17_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS17_KS17_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UHKDF_SHIFT)) & ELS_ELS_KS17_KS17_UHKDF_MASK)
+
+#define ELS_ELS_KS17_KS17_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS17_KS17_UECSG_SHIFT            (18U)
+/*! KS17_UECSG - Ecc signing key */
+#define ELS_ELS_KS17_KS17_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UECSG_SHIFT)) & ELS_ELS_KS17_KS17_UECSG_MASK)
+
+#define ELS_ELS_KS17_KS17_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS17_KS17_UECDH_SHIFT            (19U)
+/*! KS17_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS17_KS17_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UECDH_SHIFT)) & ELS_ELS_KS17_KS17_UECDH_MASK)
+
+#define ELS_ELS_KS17_KS17_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS17_KS17_UAES_SHIFT             (20U)
+/*! KS17_UAES - Aes key */
+#define ELS_ELS_KS17_KS17_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UAES_SHIFT)) & ELS_ELS_KS17_KS17_UAES_MASK)
+
+#define ELS_ELS_KS17_KS17_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS17_KS17_UHMAC_SHIFT            (21U)
+/*! KS17_UHMAC - Hmac key */
+#define ELS_ELS_KS17_KS17_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UHMAC_SHIFT)) & ELS_ELS_KS17_KS17_UHMAC_MASK)
+
+#define ELS_ELS_KS17_KS17_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS17_KS17_UKWK_SHIFT             (22U)
+/*! KS17_UKWK - Key wrapping key */
+#define ELS_ELS_KS17_KS17_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKWK_SHIFT)) & ELS_ELS_KS17_KS17_UKWK_MASK)
+
+#define ELS_ELS_KS17_KS17_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS17_KS17_UKUOK_SHIFT            (23U)
+/*! KS17_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS17_KS17_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKUOK_SHIFT)) & ELS_ELS_KS17_KS17_UKUOK_MASK)
+
+#define ELS_ELS_KS17_KS17_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS17_KS17_UTLSPMS_SHIFT          (24U)
+/*! KS17_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS17_KS17_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UTLSPMS_SHIFT)) & ELS_ELS_KS17_KS17_UTLSPMS_MASK)
+
+#define ELS_ELS_KS17_KS17_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS17_KS17_UTLSMS_SHIFT           (25U)
+/*! KS17_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS17_KS17_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UTLSMS_SHIFT)) & ELS_ELS_KS17_KS17_UTLSMS_MASK)
+
+#define ELS_ELS_KS17_KS17_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS17_KS17_UKGSRC_SHIFT           (26U)
+/*! KS17_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS17_KS17_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UKGSRC_SHIFT)) & ELS_ELS_KS17_KS17_UKGSRC_MASK)
+
+#define ELS_ELS_KS17_KS17_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS17_KS17_UHWO_SHIFT             (27U)
+/*! KS17_UHWO - Hardware out key */
+#define ELS_ELS_KS17_KS17_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UHWO_SHIFT)) & ELS_ELS_KS17_KS17_UHWO_MASK)
+
+#define ELS_ELS_KS17_KS17_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS17_KS17_UWRPOK_SHIFT           (28U)
+/*! KS17_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS17_KS17_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UWRPOK_SHIFT)) & ELS_ELS_KS17_KS17_UWRPOK_MASK)
+
+#define ELS_ELS_KS17_KS17_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS17_KS17_UDUK_SHIFT             (29U)
+/*! KS17_UDUK - Device Unique Key */
+#define ELS_ELS_KS17_KS17_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UDUK_SHIFT)) & ELS_ELS_KS17_KS17_UDUK_MASK)
+
+#define ELS_ELS_KS17_KS17_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS17_KS17_UPPROT_SHIFT           (30U)
+/*! KS17_UPPROT - Priviledge level */
+#define ELS_ELS_KS17_KS17_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS17_KS17_UPPROT_SHIFT)) & ELS_ELS_KS17_KS17_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS18 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS18_KS18_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS18_KS18_KSIZE_SHIFT            (0U)
+/*! KS18_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS18_KS18_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_KSIZE_SHIFT)) & ELS_ELS_KS18_KS18_KSIZE_MASK)
+
+#define ELS_ELS_KS18_KS18_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS18_KS18_RSVD0_SHIFT            (1U)
+/*! KS18_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS18_KS18_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_RSVD0_SHIFT)) & ELS_ELS_KS18_KS18_RSVD0_MASK)
+
+#define ELS_ELS_KS18_KS18_KACT_MASK              (0x20U)
+#define ELS_ELS_KS18_KS18_KACT_SHIFT             (5U)
+/*! KS18_KACT - Key is active */
+#define ELS_ELS_KS18_KS18_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_KACT_SHIFT)) & ELS_ELS_KS18_KS18_KACT_MASK)
+
+#define ELS_ELS_KS18_KS18_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS18_KS18_KBASE_SHIFT            (6U)
+/*! KS18_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS18_KS18_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_KBASE_SHIFT)) & ELS_ELS_KS18_KS18_KBASE_MASK)
+
+#define ELS_ELS_KS18_KS18_FGP_MASK               (0x80U)
+#define ELS_ELS_KS18_KS18_FGP_SHIFT              (7U)
+/*! KS18_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS18_KS18_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_FGP_SHIFT)) & ELS_ELS_KS18_KS18_FGP_MASK)
+
+#define ELS_ELS_KS18_KS18_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS18_KS18_FRTN_SHIFT             (8U)
+/*! KS18_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS18_KS18_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_FRTN_SHIFT)) & ELS_ELS_KS18_KS18_FRTN_MASK)
+
+#define ELS_ELS_KS18_KS18_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS18_KS18_FHWO_SHIFT             (9U)
+/*! KS18_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS18_KS18_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_FHWO_SHIFT)) & ELS_ELS_KS18_KS18_FHWO_MASK)
+
+#define ELS_ELS_KS18_KS18_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS18_KS18_RSVD1_SHIFT            (10U)
+/*! KS18_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS18_KS18_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_RSVD1_SHIFT)) & ELS_ELS_KS18_KS18_RSVD1_MASK)
+
+#define ELS_ELS_KS18_KS18_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS18_KS18_UCMAC_SHIFT            (13U)
+/*! KS18_UCMAC - CMAC key */
+#define ELS_ELS_KS18_KS18_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UCMAC_SHIFT)) & ELS_ELS_KS18_KS18_UCMAC_MASK)
+
+#define ELS_ELS_KS18_KS18_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS18_KS18_UKSK_SHIFT             (14U)
+/*! KS18_UKSK - KSK key */
+#define ELS_ELS_KS18_KS18_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKSK_SHIFT)) & ELS_ELS_KS18_KS18_UKSK_MASK)
+
+#define ELS_ELS_KS18_KS18_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS18_KS18_URTF_SHIFT             (15U)
+/*! KS18_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS18_KS18_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_URTF_SHIFT)) & ELS_ELS_KS18_KS18_URTF_MASK)
+
+#define ELS_ELS_KS18_KS18_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS18_KS18_UCKDF_SHIFT            (16U)
+/*! KS18_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS18_KS18_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UCKDF_SHIFT)) & ELS_ELS_KS18_KS18_UCKDF_MASK)
+
+#define ELS_ELS_KS18_KS18_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS18_KS18_UHKDF_SHIFT            (17U)
+/*! KS18_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS18_KS18_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UHKDF_SHIFT)) & ELS_ELS_KS18_KS18_UHKDF_MASK)
+
+#define ELS_ELS_KS18_KS18_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS18_KS18_UECSG_SHIFT            (18U)
+/*! KS18_UECSG - Ecc signing key */
+#define ELS_ELS_KS18_KS18_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UECSG_SHIFT)) & ELS_ELS_KS18_KS18_UECSG_MASK)
+
+#define ELS_ELS_KS18_KS18_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS18_KS18_UECDH_SHIFT            (19U)
+/*! KS18_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS18_KS18_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UECDH_SHIFT)) & ELS_ELS_KS18_KS18_UECDH_MASK)
+
+#define ELS_ELS_KS18_KS18_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS18_KS18_UAES_SHIFT             (20U)
+/*! KS18_UAES - Aes key */
+#define ELS_ELS_KS18_KS18_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UAES_SHIFT)) & ELS_ELS_KS18_KS18_UAES_MASK)
+
+#define ELS_ELS_KS18_KS18_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS18_KS18_UHMAC_SHIFT            (21U)
+/*! KS18_UHMAC - Hmac key */
+#define ELS_ELS_KS18_KS18_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UHMAC_SHIFT)) & ELS_ELS_KS18_KS18_UHMAC_MASK)
+
+#define ELS_ELS_KS18_KS18_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS18_KS18_UKWK_SHIFT             (22U)
+/*! KS18_UKWK - Key wrapping key */
+#define ELS_ELS_KS18_KS18_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKWK_SHIFT)) & ELS_ELS_KS18_KS18_UKWK_MASK)
+
+#define ELS_ELS_KS18_KS18_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS18_KS18_UKUOK_SHIFT            (23U)
+/*! KS18_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS18_KS18_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKUOK_SHIFT)) & ELS_ELS_KS18_KS18_UKUOK_MASK)
+
+#define ELS_ELS_KS18_KS18_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS18_KS18_UTLSPMS_SHIFT          (24U)
+/*! KS18_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS18_KS18_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UTLSPMS_SHIFT)) & ELS_ELS_KS18_KS18_UTLSPMS_MASK)
+
+#define ELS_ELS_KS18_KS18_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS18_KS18_UTLSMS_SHIFT           (25U)
+/*! KS18_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS18_KS18_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UTLSMS_SHIFT)) & ELS_ELS_KS18_KS18_UTLSMS_MASK)
+
+#define ELS_ELS_KS18_KS18_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS18_KS18_UKGSRC_SHIFT           (26U)
+/*! KS18_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS18_KS18_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UKGSRC_SHIFT)) & ELS_ELS_KS18_KS18_UKGSRC_MASK)
+
+#define ELS_ELS_KS18_KS18_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS18_KS18_UHWO_SHIFT             (27U)
+/*! KS18_UHWO - Hardware out key */
+#define ELS_ELS_KS18_KS18_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UHWO_SHIFT)) & ELS_ELS_KS18_KS18_UHWO_MASK)
+
+#define ELS_ELS_KS18_KS18_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS18_KS18_UWRPOK_SHIFT           (28U)
+/*! KS18_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS18_KS18_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UWRPOK_SHIFT)) & ELS_ELS_KS18_KS18_UWRPOK_MASK)
+
+#define ELS_ELS_KS18_KS18_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS18_KS18_UDUK_SHIFT             (29U)
+/*! KS18_UDUK - Device Unique Key */
+#define ELS_ELS_KS18_KS18_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UDUK_SHIFT)) & ELS_ELS_KS18_KS18_UDUK_MASK)
+
+#define ELS_ELS_KS18_KS18_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS18_KS18_UPPROT_SHIFT           (30U)
+/*! KS18_UPPROT - Priviledge level */
+#define ELS_ELS_KS18_KS18_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS18_KS18_UPPROT_SHIFT)) & ELS_ELS_KS18_KS18_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_KS19 - Status register */
+/*! @{ */
+
+#define ELS_ELS_KS19_KS19_KSIZE_MASK             (0x1U)
+#define ELS_ELS_KS19_KS19_KSIZE_SHIFT            (0U)
+/*! KS19_KSIZE - Key size: 0-128, 1-256 */
+#define ELS_ELS_KS19_KS19_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_KSIZE_SHIFT)) & ELS_ELS_KS19_KS19_KSIZE_MASK)
+
+#define ELS_ELS_KS19_KS19_RSVD0_MASK             (0x1EU)
+#define ELS_ELS_KS19_KS19_RSVD0_SHIFT            (1U)
+/*! KS19_RSVD0 - Reserved 0 */
+#define ELS_ELS_KS19_KS19_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_RSVD0_SHIFT)) & ELS_ELS_KS19_KS19_RSVD0_MASK)
+
+#define ELS_ELS_KS19_KS19_KACT_MASK              (0x20U)
+#define ELS_ELS_KS19_KS19_KACT_SHIFT             (5U)
+/*! KS19_KACT - Key is active */
+#define ELS_ELS_KS19_KS19_KACT(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_KACT_SHIFT)) & ELS_ELS_KS19_KS19_KACT_MASK)
+
+#define ELS_ELS_KS19_KS19_KBASE_MASK             (0x40U)
+#define ELS_ELS_KS19_KS19_KBASE_SHIFT            (6U)
+/*! KS19_KBASE - First slot in a multislot key */
+#define ELS_ELS_KS19_KS19_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_KBASE_SHIFT)) & ELS_ELS_KS19_KS19_KBASE_MASK)
+
+#define ELS_ELS_KS19_KS19_FGP_MASK               (0x80U)
+#define ELS_ELS_KS19_KS19_FGP_SHIFT              (7U)
+/*! KS19_FGP - Hardware Feature General Purpose */
+#define ELS_ELS_KS19_KS19_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_FGP_SHIFT)) & ELS_ELS_KS19_KS19_FGP_MASK)
+
+#define ELS_ELS_KS19_KS19_FRTN_MASK              (0x100U)
+#define ELS_ELS_KS19_KS19_FRTN_SHIFT             (8U)
+/*! KS19_FRTN - Hardware Feature Retention */
+#define ELS_ELS_KS19_KS19_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_FRTN_SHIFT)) & ELS_ELS_KS19_KS19_FRTN_MASK)
+
+#define ELS_ELS_KS19_KS19_FHWO_MASK              (0x200U)
+#define ELS_ELS_KS19_KS19_FHWO_SHIFT             (9U)
+/*! KS19_FHWO - Hardware Feature Output */
+#define ELS_ELS_KS19_KS19_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_FHWO_SHIFT)) & ELS_ELS_KS19_KS19_FHWO_MASK)
+
+#define ELS_ELS_KS19_KS19_RSVD1_MASK             (0x1C00U)
+#define ELS_ELS_KS19_KS19_RSVD1_SHIFT            (10U)
+/*! KS19_RSVD1 - Reserved 1 */
+#define ELS_ELS_KS19_KS19_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_RSVD1_SHIFT)) & ELS_ELS_KS19_KS19_RSVD1_MASK)
+
+#define ELS_ELS_KS19_KS19_UCMAC_MASK             (0x2000U)
+#define ELS_ELS_KS19_KS19_UCMAC_SHIFT            (13U)
+/*! KS19_UCMAC - CMAC key */
+#define ELS_ELS_KS19_KS19_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UCMAC_SHIFT)) & ELS_ELS_KS19_KS19_UCMAC_MASK)
+
+#define ELS_ELS_KS19_KS19_UKSK_MASK              (0x4000U)
+#define ELS_ELS_KS19_KS19_UKSK_SHIFT             (14U)
+/*! KS19_UKSK - KSK key */
+#define ELS_ELS_KS19_KS19_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKSK_SHIFT)) & ELS_ELS_KS19_KS19_UKSK_MASK)
+
+#define ELS_ELS_KS19_KS19_URTF_MASK              (0x8000U)
+#define ELS_ELS_KS19_KS19_URTF_SHIFT             (15U)
+/*! KS19_URTF - Real Time Fingerprint key */
+#define ELS_ELS_KS19_KS19_URTF(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_URTF_SHIFT)) & ELS_ELS_KS19_KS19_URTF_MASK)
+
+#define ELS_ELS_KS19_KS19_UCKDF_MASK             (0x10000U)
+#define ELS_ELS_KS19_KS19_UCKDF_SHIFT            (16U)
+/*! KS19_UCKDF - Derivation key for CKDF command */
+#define ELS_ELS_KS19_KS19_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UCKDF_SHIFT)) & ELS_ELS_KS19_KS19_UCKDF_MASK)
+
+#define ELS_ELS_KS19_KS19_UHKDF_MASK             (0x20000U)
+#define ELS_ELS_KS19_KS19_UHKDF_SHIFT            (17U)
+/*! KS19_UHKDF - Derivation key for HKDF command */
+#define ELS_ELS_KS19_KS19_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UHKDF_SHIFT)) & ELS_ELS_KS19_KS19_UHKDF_MASK)
+
+#define ELS_ELS_KS19_KS19_UECSG_MASK             (0x40000U)
+#define ELS_ELS_KS19_KS19_UECSG_SHIFT            (18U)
+/*! KS19_UECSG - Ecc signing key */
+#define ELS_ELS_KS19_KS19_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UECSG_SHIFT)) & ELS_ELS_KS19_KS19_UECSG_MASK)
+
+#define ELS_ELS_KS19_KS19_UECDH_MASK             (0x80000U)
+#define ELS_ELS_KS19_KS19_UECDH_SHIFT            (19U)
+/*! KS19_UECDH - Ecc diffie hellman key */
+#define ELS_ELS_KS19_KS19_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UECDH_SHIFT)) & ELS_ELS_KS19_KS19_UECDH_MASK)
+
+#define ELS_ELS_KS19_KS19_UAES_MASK              (0x100000U)
+#define ELS_ELS_KS19_KS19_UAES_SHIFT             (20U)
+/*! KS19_UAES - Aes key */
+#define ELS_ELS_KS19_KS19_UAES(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UAES_SHIFT)) & ELS_ELS_KS19_KS19_UAES_MASK)
+
+#define ELS_ELS_KS19_KS19_UHMAC_MASK             (0x200000U)
+#define ELS_ELS_KS19_KS19_UHMAC_SHIFT            (21U)
+/*! KS19_UHMAC - Hmac key */
+#define ELS_ELS_KS19_KS19_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UHMAC_SHIFT)) & ELS_ELS_KS19_KS19_UHMAC_MASK)
+
+#define ELS_ELS_KS19_KS19_UKWK_MASK              (0x400000U)
+#define ELS_ELS_KS19_KS19_UKWK_SHIFT             (22U)
+/*! KS19_UKWK - Key wrapping key */
+#define ELS_ELS_KS19_KS19_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKWK_SHIFT)) & ELS_ELS_KS19_KS19_UKWK_MASK)
+
+#define ELS_ELS_KS19_KS19_UKUOK_MASK             (0x800000U)
+#define ELS_ELS_KS19_KS19_UKUOK_SHIFT            (23U)
+/*! KS19_UKUOK - Key unwrapping key */
+#define ELS_ELS_KS19_KS19_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKUOK_SHIFT)) & ELS_ELS_KS19_KS19_UKUOK_MASK)
+
+#define ELS_ELS_KS19_KS19_UTLSPMS_MASK           (0x1000000U)
+#define ELS_ELS_KS19_KS19_UTLSPMS_SHIFT          (24U)
+/*! KS19_UTLSPMS - TLS Pre Master Secret */
+#define ELS_ELS_KS19_KS19_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UTLSPMS_SHIFT)) & ELS_ELS_KS19_KS19_UTLSPMS_MASK)
+
+#define ELS_ELS_KS19_KS19_UTLSMS_MASK            (0x2000000U)
+#define ELS_ELS_KS19_KS19_UTLSMS_SHIFT           (25U)
+/*! KS19_UTLSMS - TLS Master Secret */
+#define ELS_ELS_KS19_KS19_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UTLSMS_SHIFT)) & ELS_ELS_KS19_KS19_UTLSMS_MASK)
+
+#define ELS_ELS_KS19_KS19_UKGSRC_MASK            (0x4000000U)
+#define ELS_ELS_KS19_KS19_UKGSRC_SHIFT           (26U)
+/*! KS19_UKGSRC - Supply KEYGEN source */
+#define ELS_ELS_KS19_KS19_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UKGSRC_SHIFT)) & ELS_ELS_KS19_KS19_UKGSRC_MASK)
+
+#define ELS_ELS_KS19_KS19_UHWO_MASK              (0x8000000U)
+#define ELS_ELS_KS19_KS19_UHWO_SHIFT             (27U)
+/*! KS19_UHWO - Hardware out key */
+#define ELS_ELS_KS19_KS19_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UHWO_SHIFT)) & ELS_ELS_KS19_KS19_UHWO_MASK)
+
+#define ELS_ELS_KS19_KS19_UWRPOK_MASK            (0x10000000U)
+#define ELS_ELS_KS19_KS19_UWRPOK_SHIFT           (28U)
+/*! KS19_UWRPOK - Ok to wrap key */
+#define ELS_ELS_KS19_KS19_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UWRPOK_SHIFT)) & ELS_ELS_KS19_KS19_UWRPOK_MASK)
+
+#define ELS_ELS_KS19_KS19_UDUK_MASK              (0x20000000U)
+#define ELS_ELS_KS19_KS19_UDUK_SHIFT             (29U)
+/*! KS19_UDUK - Device Unique Key */
+#define ELS_ELS_KS19_KS19_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UDUK_SHIFT)) & ELS_ELS_KS19_KS19_UDUK_MASK)
+
+#define ELS_ELS_KS19_KS19_UPPROT_MASK            (0xC0000000U)
+#define ELS_ELS_KS19_KS19_UPPROT_SHIFT           (30U)
+/*! KS19_UPPROT - Priviledge level */
+#define ELS_ELS_KS19_KS19_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_KS19_KS19_UPPROT_SHIFT)) & ELS_ELS_KS19_KS19_UPPROT_MASK)
+/*! @} */
+
+/*! @name ELS_BOOT_ADDR - SW control for the ELS boot addr */
+/*! @{ */
+
+#define ELS_ELS_BOOT_ADDR_BOOT_ADDR_MASK         (0xFFFFFFFFU)
+#define ELS_ELS_BOOT_ADDR_BOOT_ADDR_SHIFT        (0U)
+/*! BOOT_ADDR - 32-bit wide boot offset */
+#define ELS_ELS_BOOT_ADDR_BOOT_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_BOOT_ADDR_BOOT_ADDR_SHIFT)) & ELS_ELS_BOOT_ADDR_BOOT_ADDR_MASK)
+/*! @} */
+
+/*! @name ELS_DBG_CFG - ELS Debug Config SFR */
+/*! @{ */
+
+#define ELS_ELS_DBG_CFG_DBG_CFG0_MASK            (0x7U)
+#define ELS_ELS_DBG_CFG_DBG_CFG0_SHIFT           (0U)
+/*! DBG_CFG0 - Debug Config 0 */
+#define ELS_ELS_DBG_CFG_DBG_CFG0(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DBG_CFG_DBG_CFG0_SHIFT)) & ELS_ELS_DBG_CFG_DBG_CFG0_MASK)
+
+#define ELS_ELS_DBG_CFG_DBG_CFG1_MASK            (0x38U)
+#define ELS_ELS_DBG_CFG_DBG_CFG1_SHIFT           (3U)
+/*! DBG_CFG1 - Debug Config 1 */
+#define ELS_ELS_DBG_CFG_DBG_CFG1(x)              (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DBG_CFG_DBG_CFG1_SHIFT)) & ELS_ELS_DBG_CFG_DBG_CFG1_MASK)
+
+#define ELS_ELS_DBG_CFG_DBG_CFG_RFU_MASK         (0xFFFFFFC0U)
+#define ELS_ELS_DBG_CFG_DBG_CFG_RFU_SHIFT        (6U)
+/*! DBG_CFG_RFU - reserved */
+#define ELS_ELS_DBG_CFG_DBG_CFG_RFU(x)           (((uint32_t)(((uint32_t)(x)) << ELS_ELS_DBG_CFG_DBG_CFG_RFU_SHIFT)) & ELS_ELS_DBG_CFG_DBG_CFG_RFU_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ELS_Register_Masks */
+
+
+/* ELS - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral ELS base address */
+  #define ELS_BASE                                 (0x50007000u)
+  /** Peripheral ELS base address */
+  #define ELS_BASE_NS                              (0x40007000u)
+  /** Peripheral ELS base pointer */
+  #define ELS                                      ((ELS_Type *)ELS_BASE)
+  /** Peripheral ELS base pointer */
+  #define ELS_NS                                   ((ELS_Type *)ELS_BASE_NS)
+  /** Array initializer of ELS peripheral base addresses */
+  #define ELS_BASE_ADDRS                           { ELS_BASE }
+  /** Array initializer of ELS peripheral base pointers */
+  #define ELS_BASE_PTRS                            { ELS }
+  /** Array initializer of ELS peripheral base addresses */
+  #define ELS_BASE_ADDRS_NS                        { ELS_BASE_NS }
+  /** Array initializer of ELS peripheral base pointers */
+  #define ELS_BASE_PTRS_NS                         { ELS_NS }
+#else
+  /** Peripheral ELS base address */
+  #define ELS_BASE                                 (0x40007000u)
+  /** Peripheral ELS base pointer */
+  #define ELS                                      ((ELS_Type *)ELS_BASE)
+  /** Array initializer of ELS peripheral base addresses */
+  #define ELS_BASE_ADDRS                           { ELS_BASE }
+  /** Array initializer of ELS peripheral base pointers */
+  #define ELS_BASE_PTRS                            { ELS }
+#endif
+
+/*!
+ * @}
+ */ /* end of group ELS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+  __IO uint32_t TXIC[1];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
+       uint8_t RESERVED_8[12];
+  __IO uint32_t RXIC[1];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_9[20];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_10[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_11[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
+       uint8_t RESERVED_12[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_13[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_14[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint32_t IEEE_T_DROP;                       /**< Reserved Statistic Register, offset: 0x248 */
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+  __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_15[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_16[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_17[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_18[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name EIR - Interrupt Event Register */
+/*! @{ */
+
+#define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
+#define ENET_EIR_TS_TIMER_SHIFT                  (15U)
+/*! TS_TIMER - Timestamp Timer */
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
+
+#define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
+#define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
+/*! TS_AVAIL - Transmit Timestamp Available */
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
+
+#define ENET_EIR_WAKEUP_MASK                     (0x20000U)
+#define ENET_EIR_WAKEUP_SHIFT                    (17U)
+/*! WAKEUP - Node Wakeup Request Indication */
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
+
+#define ENET_EIR_PLR_MASK                        (0x40000U)
+#define ENET_EIR_PLR_SHIFT                       (18U)
+/*! PLR - Payload Receive Error */
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
+
+#define ENET_EIR_UN_MASK                         (0x80000U)
+#define ENET_EIR_UN_SHIFT                        (19U)
+/*! UN - Transmit FIFO Underrun */
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
+
+#define ENET_EIR_RL_MASK                         (0x100000U)
+#define ENET_EIR_RL_SHIFT                        (20U)
+/*! RL - Collision Retry Limit */
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
+
+#define ENET_EIR_LC_MASK                         (0x200000U)
+#define ENET_EIR_LC_SHIFT                        (21U)
+/*! LC - Late Collision */
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
+
+#define ENET_EIR_EBERR_MASK                      (0x400000U)
+#define ENET_EIR_EBERR_SHIFT                     (22U)
+/*! EBERR - Ethernet Bus Error */
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
+
+#define ENET_EIR_MII_MASK                        (0x800000U)
+#define ENET_EIR_MII_SHIFT                       (23U)
+/*! MII - MII Interrupt. */
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
+
+#define ENET_EIR_RXB_MASK                        (0x1000000U)
+#define ENET_EIR_RXB_SHIFT                       (24U)
+/*! RXB - Receive Buffer Interrupt */
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
+
+#define ENET_EIR_RXF_MASK                        (0x2000000U)
+#define ENET_EIR_RXF_SHIFT                       (25U)
+/*! RXF - Receive Frame Interrupt */
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
+
+#define ENET_EIR_TXB_MASK                        (0x4000000U)
+#define ENET_EIR_TXB_SHIFT                       (26U)
+/*! TXB - Transmit Buffer Interrupt */
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
+
+#define ENET_EIR_TXF_MASK                        (0x8000000U)
+#define ENET_EIR_TXF_SHIFT                       (27U)
+/*! TXF - Transmit Frame Interrupt */
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
+
+#define ENET_EIR_GRA_MASK                        (0x10000000U)
+#define ENET_EIR_GRA_SHIFT                       (28U)
+/*! GRA - Graceful Stop Complete */
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
+
+#define ENET_EIR_BABT_MASK                       (0x20000000U)
+#define ENET_EIR_BABT_SHIFT                      (29U)
+/*! BABT - Babbling Transmit Error */
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
+
+#define ENET_EIR_BABR_MASK                       (0x40000000U)
+#define ENET_EIR_BABR_SHIFT                      (30U)
+/*! BABR - Babbling Receive Error */
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
+/*! @} */
+
+/*! @name EIMR - Interrupt Mask Register */
+/*! @{ */
+
+#define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
+#define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
+/*! TS_TIMER - TS_TIMER Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
+
+#define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
+#define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
+/*! TS_AVAIL - TS_AVAIL Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
+
+#define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
+#define ENET_EIMR_WAKEUP_SHIFT                   (17U)
+/*! WAKEUP - WAKEUP Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
+
+#define ENET_EIMR_PLR_MASK                       (0x40000U)
+#define ENET_EIMR_PLR_SHIFT                      (18U)
+/*! PLR - PLR Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
+
+#define ENET_EIMR_UN_MASK                        (0x80000U)
+#define ENET_EIMR_UN_SHIFT                       (19U)
+/*! UN - UN Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
+
+#define ENET_EIMR_RL_MASK                        (0x100000U)
+#define ENET_EIMR_RL_SHIFT                       (20U)
+/*! RL - RL Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
+
+#define ENET_EIMR_LC_MASK                        (0x200000U)
+#define ENET_EIMR_LC_SHIFT                       (21U)
+/*! LC - LC Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
+
+#define ENET_EIMR_EBERR_MASK                     (0x400000U)
+#define ENET_EIMR_EBERR_SHIFT                    (22U)
+/*! EBERR - EBERR Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
+
+#define ENET_EIMR_MII_MASK                       (0x800000U)
+#define ENET_EIMR_MII_SHIFT                      (23U)
+/*! MII - MII Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
+
+#define ENET_EIMR_RXB_MASK                       (0x1000000U)
+#define ENET_EIMR_RXB_SHIFT                      (24U)
+/*! RXB - RXB Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
+
+#define ENET_EIMR_RXF_MASK                       (0x2000000U)
+#define ENET_EIMR_RXF_SHIFT                      (25U)
+/*! RXF - RXF Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
+
+#define ENET_EIMR_TXB_MASK                       (0x4000000U)
+#define ENET_EIMR_TXB_SHIFT                      (26U)
+/*! TXB - TXB Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
+
+#define ENET_EIMR_TXF_MASK                       (0x8000000U)
+#define ENET_EIMR_TXF_SHIFT                      (27U)
+/*! TXF - TXF Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
+
+#define ENET_EIMR_GRA_MASK                       (0x10000000U)
+#define ENET_EIMR_GRA_SHIFT                      (28U)
+/*! GRA - GRA Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
+
+#define ENET_EIMR_BABT_MASK                      (0x20000000U)
+#define ENET_EIMR_BABT_SHIFT                     (29U)
+/*! BABT - BABT Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
+
+#define ENET_EIMR_BABR_MASK                      (0x40000000U)
+#define ENET_EIMR_BABR_SHIFT                     (30U)
+/*! BABR - BABR Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
+/*! @} */
+
+/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
+/*! @{ */
+
+#define ENET_RDAR_RDAR_MASK                      (0x1000000U)
+#define ENET_RDAR_RDAR_SHIFT                     (24U)
+/*! RDAR - Receive Descriptor Active */
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
+/*! @} */
+
+/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
+/*! @{ */
+
+#define ENET_TDAR_TDAR_MASK                      (0x1000000U)
+#define ENET_TDAR_TDAR_SHIFT                     (24U)
+/*! TDAR - Transmit Descriptor Active */
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
+/*! @} */
+
+/*! @name ECR - Ethernet Control Register */
+/*! @{ */
+
+#define ENET_ECR_RESET_MASK                      (0x1U)
+#define ENET_ECR_RESET_SHIFT                     (0U)
+/*! RESET - Ethernet MAC Reset */
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
+
+#define ENET_ECR_ETHEREN_MASK                    (0x2U)
+#define ENET_ECR_ETHEREN_SHIFT                   (1U)
+/*! ETHEREN - Ethernet Enable
+ *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
+ *  0b1..MAC is enabled, and reception and transmission are possible.
+ */
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
+
+#define ENET_ECR_MAGICEN_MASK                    (0x4U)
+#define ENET_ECR_MAGICEN_SHIFT                   (2U)
+/*! MAGICEN - Magic Packet Detection Enable
+ *  0b0..Magic detection logic disabled.
+ *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
+ */
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
+
+#define ENET_ECR_SLEEP_MASK                      (0x8U)
+#define ENET_ECR_SLEEP_SHIFT                     (3U)
+/*! SLEEP - Sleep Mode Enable
+ *  0b0..Normal operating mode.
+ *  0b1..Sleep mode.
+ */
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
+
+#define ENET_ECR_EN1588_MASK                     (0x10U)
+#define ENET_ECR_EN1588_SHIFT                    (4U)
+/*! EN1588 - EN1588 Enable
+ *  0b0..Legacy FEC buffer descriptors and functions enabled.
+ *  0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
+ */
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
+
+#define ENET_ECR_DBGEN_MASK                      (0x40U)
+#define ENET_ECR_DBGEN_SHIFT                     (6U)
+/*! DBGEN - Debug Enable
+ *  0b0..MAC continues operation in debug mode.
+ *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
+
+#define ENET_ECR_DBSWP_MASK                      (0x100U)
+#define ENET_ECR_DBSWP_SHIFT                     (8U)
+/*! DBSWP - Descriptor Byte Swapping Enable
+ *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
+ *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
+ */
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
+/*! @} */
+
+/*! @name MMFR - MII Management Frame Register */
+/*! @{ */
+
+#define ENET_MMFR_DATA_MASK                      (0xFFFFU)
+#define ENET_MMFR_DATA_SHIFT                     (0U)
+/*! DATA - Management Frame Data */
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
+
+#define ENET_MMFR_TA_MASK                        (0x30000U)
+#define ENET_MMFR_TA_SHIFT                       (16U)
+/*! TA - Turn Around */
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
+
+#define ENET_MMFR_RA_MASK                        (0x7C0000U)
+#define ENET_MMFR_RA_SHIFT                       (18U)
+/*! RA - Register Address */
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
+
+#define ENET_MMFR_PA_MASK                        (0xF800000U)
+#define ENET_MMFR_PA_SHIFT                       (23U)
+/*! PA - PHY Address */
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
+
+#define ENET_MMFR_OP_MASK                        (0x30000000U)
+#define ENET_MMFR_OP_SHIFT                       (28U)
+/*! OP - Operation Code */
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
+
+#define ENET_MMFR_ST_MASK                        (0xC0000000U)
+#define ENET_MMFR_ST_SHIFT                       (30U)
+/*! ST - Start Of Frame Delimiter */
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
+/*! @} */
+
+/*! @name MSCR - MII Speed Control Register */
+/*! @{ */
+
+#define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
+#define ENET_MSCR_MII_SPEED_SHIFT                (1U)
+/*! MII_SPEED - MII Speed */
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
+
+#define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
+#define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
+/*! DIS_PRE - Disable Preamble
+ *  0b0..Preamble enabled.
+ *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
+ */
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
+
+#define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
+#define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
+/*! HOLDTIME - Hold time On MDIO Output
+ *  0b000..1 internal module clock cycle
+ *  0b001..2 internal module clock cycles
+ *  0b010..3 internal module clock cycles
+ *  0b111..8 internal module clock cycles
+ */
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
+/*! @} */
+
+/*! @name MIBC - MIB Control Register */
+/*! @{ */
+
+#define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
+#define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
+/*! MIB_CLEAR - MIB Clear
+ *  0b0..See note above.
+ *  0b1..All statistics counters are reset to 0.
+ */
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
+
+#define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
+#define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
+/*! MIB_IDLE - MIB Idle
+ *  0b0..The MIB block is updating MIB counters.
+ *  0b1..The MIB block is not currently updating any MIB counters.
+ */
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
+
+#define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
+#define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
+/*! MIB_DIS - Disable MIB Logic
+ *  0b0..MIB logic is enabled.
+ *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
+ */
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
+/*! @} */
+
+/*! @name RCR - Receive Control Register */
+/*! @{ */
+
+#define ENET_RCR_LOOP_MASK                       (0x1U)
+#define ENET_RCR_LOOP_SHIFT                      (0U)
+/*! LOOP - Internal Loopback
+ *  0b0..Loopback disabled.
+ *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
+ */
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
+
+#define ENET_RCR_DRT_MASK                        (0x2U)
+#define ENET_RCR_DRT_SHIFT                       (1U)
+/*! DRT - Disable Receive On Transmit
+ *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
+ *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
+ */
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
+
+#define ENET_RCR_MII_MODE_MASK                   (0x4U)
+#define ENET_RCR_MII_MODE_SHIFT                  (2U)
+/*! MII_MODE - Media Independent Interface Mode
+ *  0b0..Reserved.
+ *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
+
+#define ENET_RCR_PROM_MASK                       (0x8U)
+#define ENET_RCR_PROM_SHIFT                      (3U)
+/*! PROM - Promiscuous Mode
+ *  0b0..Disabled.
+ *  0b1..Enabled.
+ */
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
+
+#define ENET_RCR_BC_REJ_MASK                     (0x10U)
+#define ENET_RCR_BC_REJ_SHIFT                    (4U)
+/*! BC_REJ - Broadcast Frame Reject
+ *  0b0..Will not reject frames as described above
+ *  0b1..Will reject frames as described above
+ */
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
+
+#define ENET_RCR_FCE_MASK                        (0x20U)
+#define ENET_RCR_FCE_SHIFT                       (5U)
+/*! FCE - Flow Control Enable
+ *  0b0..Disable flow control
+ *  0b1..Enable flow control
+ */
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
+
+#define ENET_RCR_RMII_MODE_MASK                  (0x100U)
+#define ENET_RCR_RMII_MODE_SHIFT                 (8U)
+/*! RMII_MODE - RMII Mode Enable
+ *  0b0..MAC configured for MII mode.
+ *  0b1..MAC configured for RMII operation.
+ */
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
+
+#define ENET_RCR_RMII_10T_MASK                   (0x200U)
+#define ENET_RCR_RMII_10T_SHIFT                  (9U)
+/*! RMII_10T
+ *  0b0..100-Mbit/s operation.
+ *  0b1..10-Mbit/s operation.
+ */
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
+
+#define ENET_RCR_PADEN_MASK                      (0x1000U)
+#define ENET_RCR_PADEN_SHIFT                     (12U)
+/*! PADEN - Enable Frame Padding Remove On Receive
+ *  0b0..No padding is removed on receive by the MAC.
+ *  0b1..Padding is removed from received frames.
+ */
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
+
+#define ENET_RCR_PAUFWD_MASK                     (0x2000U)
+#define ENET_RCR_PAUFWD_SHIFT                    (13U)
+/*! PAUFWD - Terminate/Forward Pause Frames
+ *  0b0..Pause frames are terminated and discarded in the MAC.
+ *  0b1..Pause frames are forwarded to the user application.
+ */
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
+
+#define ENET_RCR_CRCFWD_MASK                     (0x4000U)
+#define ENET_RCR_CRCFWD_SHIFT                    (14U)
+/*! CRCFWD - Terminate/Forward Received CRC
+ *  0b0..The CRC field of received frames is transmitted to the user application.
+ *  0b1..The CRC field is stripped from the frame.
+ */
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
+
+#define ENET_RCR_CFEN_MASK                       (0x8000U)
+#define ENET_RCR_CFEN_SHIFT                      (15U)
+/*! CFEN - MAC Control Frame Enable
+ *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
+ *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
+ */
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
+
+#define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
+#define ENET_RCR_MAX_FL_SHIFT                    (16U)
+/*! MAX_FL - Maximum Frame Length */
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
+
+#define ENET_RCR_NLC_MASK                        (0x40000000U)
+#define ENET_RCR_NLC_SHIFT                       (30U)
+/*! NLC - Payload Length Check Disable
+ *  0b0..The payload length check is disabled.
+ *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
+ */
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
+
+#define ENET_RCR_GRS_MASK                        (0x80000000U)
+#define ENET_RCR_GRS_SHIFT                       (31U)
+/*! GRS - Graceful Receive Stopped
+ *  0b0..Receive not stopped
+ *  0b1..Receive stopped
+ */
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
+/*! @} */
+
+/*! @name TCR - Transmit Control Register */
+/*! @{ */
+
+#define ENET_TCR_GTS_MASK                        (0x1U)
+#define ENET_TCR_GTS_SHIFT                       (0U)
+/*! GTS - Graceful Transmit Stop
+ *  0b0..Disable graceful transmit stop
+ *  0b1..Enable graceful transmit stop
+ */
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
+
+#define ENET_TCR_FDEN_MASK                       (0x4U)
+#define ENET_TCR_FDEN_SHIFT                      (2U)
+/*! FDEN - Full-Duplex Enable
+ *  0b0..Disable full-duplex
+ *  0b1..Enable full-duplex
+ */
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
+
+#define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
+#define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
+/*! TFC_PAUSE - Transmit Frame Control Pause
+ *  0b0..No PAUSE frame transmitted.
+ *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
+ */
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
+
+#define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
+#define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
+/*! RFC_PAUSE - Receive Frame Control Pause */
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
+
+#define ENET_TCR_ADDSEL_MASK                     (0xE0U)
+#define ENET_TCR_ADDSEL_SHIFT                    (5U)
+/*! ADDSEL - Source MAC Address Select On Transmit
+ *  0b000..Node MAC address programmed on PADDR1/2 registers.
+ *  0b100..Reserved.
+ *  0b101..Reserved.
+ *  0b110..Reserved.
+ */
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
+
+#define ENET_TCR_ADDINS_MASK                     (0x100U)
+#define ENET_TCR_ADDINS_SHIFT                    (8U)
+/*! ADDINS - Set MAC Address On Transmit
+ *  0b0..The source MAC address is not modified by the MAC.
+ *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
+ */
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
+
+#define ENET_TCR_CRCFWD_MASK                     (0x200U)
+#define ENET_TCR_CRCFWD_SHIFT                    (9U)
+/*! CRCFWD - Forward Frame From Application With CRC
+ *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
+ *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
+ */
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
+/*! @} */
+
+/*! @name PALR - Physical Address Lower Register */
+/*! @{ */
+
+#define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_PALR_PADDR1_SHIFT                   (0U)
+/*! PADDR1 - Pause Address */
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
+/*! @} */
+
+/*! @name PAUR - Physical Address Upper Register */
+/*! @{ */
+
+#define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
+#define ENET_PAUR_TYPE_SHIFT                     (0U)
+/*! TYPE - Type Field In PAUSE Frames */
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
+
+#define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
+#define ENET_PAUR_PADDR2_SHIFT                   (16U)
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
+/*! @} */
+
+/*! @name OPD - Opcode/Pause Duration Register */
+/*! @{ */
+
+#define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
+#define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
+/*! PAUSE_DUR - Pause Duration */
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
+
+#define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
+#define ENET_OPD_OPCODE_SHIFT                    (16U)
+/*! OPCODE - Opcode Field In PAUSE Frames */
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
+/*! @} */
+
+/*! @name TXIC - Transmit Interrupt Coalescing Register */
+/*! @{ */
+
+#define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
+#define ENET_TXIC_ICTT_SHIFT                     (0U)
+/*! ICTT - Interrupt coalescing timer threshold */
+#define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
+
+#define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
+#define ENET_TXIC_ICFT_SHIFT                     (20U)
+/*! ICFT - Interrupt coalescing frame count threshold */
+#define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
+
+#define ENET_TXIC_ICCS_MASK                      (0x40000000U)
+#define ENET_TXIC_ICCS_SHIFT                     (30U)
+/*! ICCS - Interrupt Coalescing Timer Clock Source Select
+ *  0b0..Use MII/GMII TX clocks.
+ *  0b1..Use ENET system clock.
+ */
+#define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
+
+#define ENET_TXIC_ICEN_MASK                      (0x80000000U)
+#define ENET_TXIC_ICEN_SHIFT                     (31U)
+/*! ICEN - Interrupt Coalescing Enable
+ *  0b0..Disable Interrupt coalescing.
+ *  0b1..Enable Interrupt coalescing.
+ */
+#define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
+/*! @} */
+
+/* The count of ENET_TXIC */
+#define ENET_TXIC_COUNT                          (1U)
+
+/*! @name RXIC - Receive Interrupt Coalescing Register */
+/*! @{ */
+
+#define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
+#define ENET_RXIC_ICTT_SHIFT                     (0U)
+/*! ICTT - Interrupt coalescing timer threshold */
+#define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
+
+#define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
+#define ENET_RXIC_ICFT_SHIFT                     (20U)
+/*! ICFT - Interrupt coalescing frame count threshold */
+#define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
+
+#define ENET_RXIC_ICCS_MASK                      (0x40000000U)
+#define ENET_RXIC_ICCS_SHIFT                     (30U)
+/*! ICCS - Interrupt Coalescing Timer Clock Source Select
+ *  0b0..Use MII/GMII TX clocks.
+ *  0b1..Use ENET system clock.
+ */
+#define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
+
+#define ENET_RXIC_ICEN_MASK                      (0x80000000U)
+#define ENET_RXIC_ICEN_SHIFT                     (31U)
+/*! ICEN - Interrupt Coalescing Enable
+ *  0b0..Disable Interrupt coalescing.
+ *  0b1..Enable Interrupt coalescing.
+ */
+#define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
+/*! @} */
+
+/* The count of ENET_RXIC */
+#define ENET_RXIC_COUNT                          (1U)
+
+/*! @name IAUR - Descriptor Individual Upper Address Register */
+/*! @{ */
+
+#define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_IAUR_IADDR1_SHIFT                   (0U)
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
+/*! @} */
+
+/*! @name IALR - Descriptor Individual Lower Address Register */
+/*! @{ */
+
+#define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
+#define ENET_IALR_IADDR2_SHIFT                   (0U)
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
+/*! @} */
+
+/*! @name GAUR - Descriptor Group Upper Address Register */
+/*! @{ */
+
+#define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_GAUR_GADDR1_SHIFT                   (0U)
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
+/*! @} */
+
+/*! @name GALR - Descriptor Group Lower Address Register */
+/*! @{ */
+
+#define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
+#define ENET_GALR_GADDR2_SHIFT                   (0U)
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
+/*! @} */
+
+/*! @name TFWR - Transmit FIFO Watermark Register */
+/*! @{ */
+
+#define ENET_TFWR_TFWR_MASK                      (0x3FU)
+#define ENET_TFWR_TFWR_SHIFT                     (0U)
+/*! TFWR - Transmit FIFO Write
+ *  0b000000..64 bytes written.
+ *  0b000001..64 bytes written.
+ *  0b000010..128 bytes written.
+ *  0b000011..192 bytes written.
+ *  0b011111..1984 bytes written.
+ */
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
+
+#define ENET_TFWR_STRFWD_MASK                    (0x100U)
+#define ENET_TFWR_STRFWD_SHIFT                   (8U)
+/*! STRFWD - Store And Forward Enable
+ *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ *  0b1..Enabled.
+ */
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
+/*! @} */
+
+/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
+/*! @{ */
+
+#define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_RDSR_R_DES_START_SHIFT              (3U)
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
+/*! @} */
+
+/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
+/*! @{ */
+
+#define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_TDSR_X_DES_START_SHIFT              (3U)
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
+/*! @} */
+
+/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
+/*! @{ */
+
+#define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
+/*! @} */
+
+/*! @name RSFL - Receive FIFO Section Full Threshold */
+/*! @{ */
+
+#define ENET_RSFL_RX_SECTION_FULL_MASK           (0xFFU)
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
+/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold */
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
+/*! @} */
+
+/*! @name RSEM - Receive FIFO Section Empty Threshold */
+/*! @{ */
+
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
+/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
+
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
+/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold */
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/*! @} */
+
+/*! @name RAEM - Receive FIFO Almost Empty Threshold */
+/*! @{ */
+
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
+/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold */
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/*! @} */
+
+/*! @name RAFL - Receive FIFO Almost Full Threshold */
+/*! @{ */
+
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
+/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold */
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
+/*! @} */
+
+/*! @name TSEM - Transmit FIFO Section Empty Threshold */
+/*! @{ */
+
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
+/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold */
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/*! @} */
+
+/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
+/*! @{ */
+
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
+/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold */
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/*! @} */
+
+/*! @name TAFL - Transmit FIFO Almost Full Threshold */
+/*! @{ */
+
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
+/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold */
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
+/*! @} */
+
+/*! @name TIPG - Transmit Inter-Packet Gap */
+/*! @{ */
+
+#define ENET_TIPG_IPG_MASK                       (0x1FU)
+#define ENET_TIPG_IPG_SHIFT                      (0U)
+/*! IPG - Transmit Inter-Packet Gap */
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
+/*! @} */
+
+/*! @name FTRL - Frame Truncation Length */
+/*! @{ */
+
+#define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
+#define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
+/*! TRUNC_FL - Frame Truncation Length */
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
+/*! @} */
+
+/*! @name TACC - Transmit Accelerator Function Configuration */
+/*! @{ */
+
+#define ENET_TACC_SHIFT16_MASK                   (0x1U)
+#define ENET_TACC_SHIFT16_SHIFT                  (0U)
+/*! SHIFT16 - TX FIFO Shift-16
+ *  0b0..Disabled.
+ *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
+ *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
+ *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
+ *       extended to a 16-byte header.
+ */
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
+
+#define ENET_TACC_IPCHK_MASK                     (0x8U)
+#define ENET_TACC_IPCHK_SHIFT                    (3U)
+/*! IPCHK
+ *  0b0..Checksum is not inserted.
+ *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
+ *       be cleared. If a non-IP frame is transmitted the frame is not modified.
+ */
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
+
+#define ENET_TACC_PROCHK_MASK                    (0x10U)
+#define ENET_TACC_PROCHK_SHIFT                   (4U)
+/*! PROCHK
+ *  0b0..Checksum not inserted.
+ *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
+ *       frame. The checksum field must be cleared. The other frames are not modified.
+ */
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
+/*! @} */
+
+/*! @name RACC - Receive Accelerator Function Configuration */
+/*! @{ */
+
+#define ENET_RACC_PADREM_MASK                    (0x1U)
+#define ENET_RACC_PADREM_SHIFT                   (0U)
+/*! PADREM - Enable Padding Removal For Short IP Frames
+ *  0b0..Padding not removed.
+ *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
+ */
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
+
+#define ENET_RACC_IPDIS_MASK                     (0x2U)
+#define ENET_RACC_IPDIS_SHIFT                    (1U)
+/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
+ *  0b0..Frames with wrong IPv4 header checksum are not discarded.
+ *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
+ *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
+ *       store and forward mode (RSFL cleared).
+ */
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
+
+#define ENET_RACC_PRODIS_MASK                    (0x4U)
+#define ENET_RACC_PRODIS_SHIFT                   (2U)
+/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
+ *  0b0..Frames with wrong checksum are not discarded.
+ *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
+ *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
+ *       cleared).
+ */
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
+
+#define ENET_RACC_LINEDIS_MASK                   (0x40U)
+#define ENET_RACC_LINEDIS_SHIFT                  (6U)
+/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
+ *  0b0..Frames with errors are not discarded.
+ *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
+ */
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
+
+#define ENET_RACC_SHIFT16_MASK                   (0x80U)
+#define ENET_RACC_SHIFT16_SHIFT                  (7U)
+/*! SHIFT16 - RX FIFO Shift-16
+ *  0b0..Disabled.
+ *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
+ */
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
+/*! @} */
+
+/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
+/*! TXPKTS - Packet count */
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
+/*! TXPKTS - Broadcast packets */
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
+/*! TXPKTS - Multicast packets */
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
+/*! TXPKTS - Packets with CRC/align error */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
+/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
+/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC */
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
+/*! TXPKTS - Number of packets less than 64 bytes with bad CRC */
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
+/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC */
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
+/*! TXPKTS - Number of transmit collisions */
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
+/*! TXPKTS - Number of 64-byte transmit packets */
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
+/*! TXPKTS - Number of 65- to 127-byte transmit packets */
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
+/*! TXPKTS - Number of 128- to 255-byte transmit packets */
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
+/*! TXPKTS - Number of 256- to 511-byte transmit packets */
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
+/*! TXPKTS - Number of 512- to 1023-byte transmit packets */
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
+/*! TXPKTS - Number of 1024- to 2047-byte transmit packets */
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
+/*! TXPKTS - Number of transmit packets greater than 2048 bytes */
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/*! @} */
+
+/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
+/*! TXOCTS - Number of transmit octets */
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/*! @} */
+
+/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
+/*! COUNT - Number of frames transmitted OK */
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
+/*! COUNT - Number of frames transmitted with one collision */
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
+/*! COUNT - Number of frames transmitted with multiple collisions */
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
+/*! COUNT - Number of frames transmitted with deferral delay */
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
+/*! COUNT - Number of frames transmitted with late collision */
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
+/*! COUNT - Number of frames transmitted with excessive collisions */
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
+/*! COUNT - Number of frames transmitted with transmit FIFO underrun */
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
+/*! COUNT - Number of frames transmitted with carrier sense error */
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_SQE - Reserved Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
+/*! COUNT - This read-only field is reserved and always has the value 0 */
+#define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
+/*! COUNT - Number of flow-control pause frames transmitted */
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
+/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). */
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
+/*! COUNT - Number of packets received */
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
+/*! COUNT - Number of receive broadcast packets */
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
+/*! COUNT - Number of receive multicast packets */
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
+/*! COUNT - Number of receive packets with CRC or align error */
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
+/*! COUNT - Number of receive packets with less than 64 bytes and good CRC */
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
+/*! COUNT - Number of receive packets greater than MAX_FL and good CRC */
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
+/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC */
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
+/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC */
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
+/*! COUNT - Number of 64-byte receive packets */
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
+/*! COUNT - Number of 65- to 127-byte recieve packets */
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
+/*! COUNT - Number of 128- to 255-byte recieve packets */
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
+/*! COUNT - Number of 256- to 511-byte recieve packets */
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
+/*! COUNT - Number of 512- to 1023-byte recieve packets */
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
+/*! COUNT - Number of 1024- to 2047-byte recieve packets */
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
+/*! COUNT - Number of greater-than-2048-byte recieve packets */
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/*! @} */
+
+/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
+/*! @{ */
+
+#define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
+/*! COUNT - Number of receive octets */
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
+/*! COUNT - Frame count */
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
+/*! COUNT - Number of frames received OK */
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
+/*! COUNT - Number of frames received with CRC error */
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
+/*! COUNT - Number of frames received with alignment error */
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
+/*! COUNT - Receive FIFO overflow count */
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
+/*! COUNT - Number of flow-control pause frames received */
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
+/*! @} */
+
+/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
+/*! @{ */
+
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
+/*! COUNT - Number of octets for frames received without error */
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/*! @} */
+
+/*! @name ATCR - Adjustable Timer Control Register */
+/*! @{ */
+
+#define ENET_ATCR_EN_MASK                        (0x1U)
+#define ENET_ATCR_EN_SHIFT                       (0U)
+/*! EN - Enable Timer
+ *  0b0..The timer stops at the current value.
+ *  0b1..The timer starts incrementing.
+ */
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
+
+#define ENET_ATCR_OFFEN_MASK                     (0x4U)
+#define ENET_ATCR_OFFEN_SHIFT                    (2U)
+/*! OFFEN - Enable One-Shot Offset Event
+ *  0b0..Disable.
+ *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
+ *       when the offset event is reached, so no further event occurs until the field is set again. The timer
+ *       offset value must be set before setting this field.
+ */
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
+
+#define ENET_ATCR_OFFRST_MASK                    (0x8U)
+#define ENET_ATCR_OFFRST_SHIFT                   (3U)
+/*! OFFRST - Reset Timer On Offset Event
+ *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
+ *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
+ */
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
+
+#define ENET_ATCR_PEREN_MASK                     (0x10U)
+#define ENET_ATCR_PEREN_SHIFT                    (4U)
+/*! PEREN - Enable Periodical Event
+ *  0b0..Disable.
+ *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
+ *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
+ *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
+ */
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
+
+#define ENET_ATCR_PINPER_MASK                    (0x80U)
+#define ENET_ATCR_PINPER_SHIFT                   (7U)
+/*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
+
+#define ENET_ATCR_RESTART_MASK                   (0x200U)
+#define ENET_ATCR_RESTART_SHIFT                  (9U)
+/*! RESTART - Reset Timer */
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
+
+#define ENET_ATCR_CAPTURE_MASK                   (0x800U)
+#define ENET_ATCR_CAPTURE_SHIFT                  (11U)
+/*! CAPTURE - Capture Timer Value
+ *  0b0..No effect.
+ *  0b1..The current time is captured and can be read from the ATVR register.
+ */
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
+
+#define ENET_ATCR_SLAVE_MASK                     (0x2000U)
+#define ENET_ATCR_SLAVE_SHIFT                    (13U)
+/*! SLAVE - Enable Timer Slave Mode
+ *  0b0..The timer is active and all configuration fields in this register are relevant.
+ *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
+ *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
+ */
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
+/*! @} */
+
+/*! @name ATVR - Timer Value Register */
+/*! @{ */
+
+#define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
+#define ENET_ATVR_ATIME_SHIFT                    (0U)
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
+/*! @} */
+
+/*! @name ATOFF - Timer Offset Register */
+/*! @{ */
+
+#define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
+#define ENET_ATOFF_OFFSET_SHIFT                  (0U)
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
+/*! @} */
+
+/*! @name ATPER - Timer Period Register */
+/*! @{ */
+
+#define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
+#define ENET_ATPER_PERIOD_SHIFT                  (0U)
+/*! PERIOD - Value for generating periodic events */
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
+/*! @} */
+
+/*! @name ATCOR - Timer Correction Register */
+/*! @{ */
+
+#define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
+#define ENET_ATCOR_COR_SHIFT                     (0U)
+/*! COR - Correction Counter Wrap-Around Value */
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
+/*! @} */
+
+/*! @name ATINC - Time-Stamping Clock Period Register */
+/*! @{ */
+
+#define ENET_ATINC_INC_MASK                      (0x7FU)
+#define ENET_ATINC_INC_SHIFT                     (0U)
+/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
+
+#define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
+#define ENET_ATINC_INC_CORR_SHIFT                (8U)
+/*! INC_CORR - Correction Increment Value */
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
+/*! @} */
+
+/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
+/*! @{ */
+
+#define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
+/*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
+ *    ff_tx_ts_frm signal asserted from the user application
+ */
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
+/*! @} */
+
+/*! @name TGSR - Timer Global Status Register */
+/*! @{ */
+
+#define ENET_TGSR_TF0_MASK                       (0x1U)
+#define ENET_TGSR_TF0_SHIFT                      (0U)
+/*! TF0 - Copy Of Timer Flag For Channel 0
+ *  0b0..Timer Flag for Channel 0 is clear
+ *  0b1..Timer Flag for Channel 0 is set
+ */
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
+
+#define ENET_TGSR_TF1_MASK                       (0x2U)
+#define ENET_TGSR_TF1_SHIFT                      (1U)
+/*! TF1 - Copy Of Timer Flag For Channel 1
+ *  0b0..Timer Flag for Channel 1 is clear
+ *  0b1..Timer Flag for Channel 1 is set
+ */
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
+
+#define ENET_TGSR_TF2_MASK                       (0x4U)
+#define ENET_TGSR_TF2_SHIFT                      (2U)
+/*! TF2 - Copy Of Timer Flag For Channel 2
+ *  0b0..Timer Flag for Channel 2 is clear
+ *  0b1..Timer Flag for Channel 2 is set
+ */
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
+
+#define ENET_TGSR_TF3_MASK                       (0x8U)
+#define ENET_TGSR_TF3_SHIFT                      (3U)
+/*! TF3 - Copy Of Timer Flag For Channel 3
+ *  0b0..Timer Flag for Channel 3 is clear
+ *  0b1..Timer Flag for Channel 3 is set
+ */
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
+/*! @} */
+
+/*! @name TCSR - Timer Control Status Register */
+/*! @{ */
+
+#define ENET_TCSR_TDRE_MASK                      (0x1U)
+#define ENET_TCSR_TDRE_SHIFT                     (0U)
+/*! TDRE - Timer DMA Request Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
+
+#define ENET_TCSR_TMODE_MASK                     (0x3CU)
+#define ENET_TCSR_TMODE_SHIFT                    (2U)
+/*! TMODE - Timer Mode
+ *  0b0000..Timer Channel is disabled.
+ *  0b0001..Timer Channel is configured for Input Capture on rising edge.
+ *  0b0010..Timer Channel is configured for Input Capture on falling edge.
+ *  0b0011..Timer Channel is configured for Input Capture on both edges.
+ *  0b0100..Timer Channel is configured for Output Compare - software only.
+ *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
+ *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
+ *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
+ *  0b1000..Reserved
+ *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
+ *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
+ *  0b110x..Reserved
+ *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
+ *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
+ */
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
+
+#define ENET_TCSR_TIE_MASK                       (0x40U)
+#define ENET_TCSR_TIE_SHIFT                      (6U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Interrupt is disabled
+ *  0b1..Interrupt is enabled
+ */
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
+
+#define ENET_TCSR_TF_MASK                        (0x80U)
+#define ENET_TCSR_TF_SHIFT                       (7U)
+/*! TF - Timer Flag
+ *  0b0..Input Capture or Output Compare has not occurred.
+ *  0b1..Input Capture or Output Compare has occurred.
+ */
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
+
+#define ENET_TCSR_TPWC_MASK                      (0xF800U)
+#define ENET_TCSR_TPWC_SHIFT                     (11U)
+/*! TPWC - Timer PulseWidth Control
+ *  0b00000..Pulse width is one 1588-clock cycle.
+ *  0b00001..Pulse width is two 1588-clock cycles.
+ *  0b00010..Pulse width is three 1588-clock cycles.
+ *  0b00011..Pulse width is four 1588-clock cycles.
+ *  0b11111..Pulse width is 32 1588-clock cycles.
+ */
+#define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
+/*! @} */
+
+/* The count of ENET_TCSR */
+#define ENET_TCSR_COUNT                          (4U)
+
+/*! @name TCCR - Timer Compare Capture Register */
+/*! @{ */
+
+#define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
+#define ENET_TCCR_TCC_SHIFT                      (0U)
+/*! TCC - Timer Capture Compare */
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
+/*! @} */
+
+/* The count of ENET_TCCR */
+#define ENET_TCCR_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral ENET base address */
+  #define ENET_BASE                                (0x50138000u)
+  /** Peripheral ENET base address */
+  #define ENET_BASE_NS                             (0x40138000u)
+  /** Peripheral ENET base pointer */
+  #define ENET                                     ((ENET_Type *)ENET_BASE)
+  /** Peripheral ENET base pointer */
+  #define ENET_NS                                  ((ENET_Type *)ENET_BASE_NS)
+  /** Array initializer of ENET peripheral base addresses */
+  #define ENET_BASE_ADDRS                          { ENET_BASE }
+  /** Array initializer of ENET peripheral base pointers */
+  #define ENET_BASE_PTRS                           { ENET }
+  /** Array initializer of ENET peripheral base addresses */
+  #define ENET_BASE_ADDRS_NS                       { ENET_BASE_NS }
+  /** Array initializer of ENET peripheral base pointers */
+  #define ENET_BASE_PTRS_NS                        { ENET_NS }
+#else
+  /** Peripheral ENET base address */
+  #define ENET_BASE                                (0x40138000u)
+  /** Peripheral ENET base pointer */
+  #define ENET                                     ((ENET_Type *)ENET_BASE)
+  /** Array initializer of ENET peripheral base addresses */
+  #define ENET_BASE_ADDRS                          { ENET_BASE }
+  /** Array initializer of ENET peripheral base pointers */
+  #define ENET_BASE_PTRS                           { ENET }
+#endif
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_IRQn }
+#define ENET_Receive_IRQS                        { ENET_IRQn }
+#define ENET_Error_IRQS                          { ENET_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_TIMER_IRQn }
+#define ENET_Ts_IRQS                             { ENET_IRQn }
+/* ENET Buffer Descriptor and Buffer Address Alignment. */
+#define ENET_BUFF_ALIGNMENT                      (64U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4088];
+  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm module ID, offset: 0xFF8 */
+  __I  uint32_t PID;                               /**< Peripheral Identification, offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm module ID */
+/*! @{ */
+
+#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
+/*! PERSEL - Peripheral Select
+ *  0b000..No peripheral selected.
+ *  0b001..USART function selected
+ *  0b010..SPI function selected
+ *  0b011..I2C
+ *  0b100..I2S Transmit
+ *  0b101..I2S Receive
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+
+#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
+/*! LOCK - Lock the peripheral select
+ *  0b0..Peripheral select can be changed by software.
+ *  0b1..Peripheral select is locked and cannot be changed until this Flexcomm module or the entire device is reset.
+ */
+#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
+/*! USARTPRESENT - USART present indicator
+ *  0b0..This Flexcomm module does not include the USART function.
+ *  0b1..This Flexcomm module includes the USART function.
+ */
+#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
+/*! SPIPRESENT - SPI present indicator
+ *  0b0..This Flexcomm module does not include the SPI function.
+ *  0b1..This Flexcomm module includes the SPI function.
+ */
+#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
+/*! I2CPRESENT - I2C present indicator
+ *  0b0..I2C Not Present
+ *  0b1..I2C Present
+ */
+#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
+/*! I2SPRESENT - I2S Present
+ *  0b0..I2S Not Present
+ *  0b1..I2S Present
+ */
+#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
+/*! ID - Flexcomm ID */
+#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+/*! @} */
+
+/*! @name PID - Peripheral Identification */
+/*! @{ */
+
+#define FLEXCOMM_PID_MINOR_REV_MASK              (0xF00U)
+#define FLEXCOMM_PID_MINOR_REV_SHIFT             (8U)
+/*! MINOR_REV - Minor revision of module implementation */
+#define FLEXCOMM_PID_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK)
+
+#define FLEXCOMM_PID_MAJOR_REV_MASK              (0xF000U)
+#define FLEXCOMM_PID_MAJOR_REV_SHIFT             (12U)
+/*! MAJOR_REV - Major revision of module implementation */
+#define FLEXCOMM_PID_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK)
+
+#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT                    (16U)
+/*! ID - Module identifier for the selected function */
+#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral FLEXCOMM0 base address */
+  #define FLEXCOMM0_BASE                           (0x50106000u)
+  /** Peripheral FLEXCOMM0 base address */
+  #define FLEXCOMM0_BASE_NS                        (0x40106000u)
+  /** Peripheral FLEXCOMM0 base pointer */
+  #define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+  /** Peripheral FLEXCOMM0 base pointer */
+  #define FLEXCOMM0_NS                             ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS)
+  /** Peripheral FLEXCOMM1 base address */
+  #define FLEXCOMM1_BASE                           (0x50107000u)
+  /** Peripheral FLEXCOMM1 base address */
+  #define FLEXCOMM1_BASE_NS                        (0x40107000u)
+  /** Peripheral FLEXCOMM1 base pointer */
+  #define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+  /** Peripheral FLEXCOMM1 base pointer */
+  #define FLEXCOMM1_NS                             ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS)
+  /** Peripheral FLEXCOMM2 base address */
+  #define FLEXCOMM2_BASE                           (0x50108000u)
+  /** Peripheral FLEXCOMM2 base address */
+  #define FLEXCOMM2_BASE_NS                        (0x40108000u)
+  /** Peripheral FLEXCOMM2 base pointer */
+  #define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+  /** Peripheral FLEXCOMM2 base pointer */
+  #define FLEXCOMM2_NS                             ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS)
+  /** Peripheral FLEXCOMM3 base address */
+  #define FLEXCOMM3_BASE                           (0x50109000u)
+  /** Peripheral FLEXCOMM3 base address */
+  #define FLEXCOMM3_BASE_NS                        (0x40109000u)
+  /** Peripheral FLEXCOMM3 base pointer */
+  #define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+  /** Peripheral FLEXCOMM3 base pointer */
+  #define FLEXCOMM3_NS                             ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS)
+  /** Peripheral FLEXCOMM14 base address */
+  #define FLEXCOMM14_BASE                          (0x50126000u)
+  /** Peripheral FLEXCOMM14 base address */
+  #define FLEXCOMM14_BASE_NS                       (0x40126000u)
+  /** Peripheral FLEXCOMM14 base pointer */
+  #define FLEXCOMM14                               ((FLEXCOMM_Type *)FLEXCOMM14_BASE)
+  /** Peripheral FLEXCOMM14 base pointer */
+  #define FLEXCOMM14_NS                            ((FLEXCOMM_Type *)FLEXCOMM14_BASE_NS)
+  /** Array initializer of FLEXCOMM peripheral base addresses */
+  #define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM14_BASE }
+  /** Array initializer of FLEXCOMM peripheral base pointers */
+  #define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM14 }
+  /** Array initializer of FLEXCOMM peripheral base addresses */
+  #define FLEXCOMM_BASE_ADDRS_NS                   { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM14_BASE_NS }
+  /** Array initializer of FLEXCOMM peripheral base pointers */
+  #define FLEXCOMM_BASE_PTRS_NS                    { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM14_NS }
+#else
+  /** Peripheral FLEXCOMM0 base address */
+  #define FLEXCOMM0_BASE                           (0x40106000u)
+  /** Peripheral FLEXCOMM0 base pointer */
+  #define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+  /** Peripheral FLEXCOMM1 base address */
+  #define FLEXCOMM1_BASE                           (0x40107000u)
+  /** Peripheral FLEXCOMM1 base pointer */
+  #define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+  /** Peripheral FLEXCOMM2 base address */
+  #define FLEXCOMM2_BASE                           (0x40108000u)
+  /** Peripheral FLEXCOMM2 base pointer */
+  #define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+  /** Peripheral FLEXCOMM3 base address */
+  #define FLEXCOMM3_BASE                           (0x40109000u)
+  /** Peripheral FLEXCOMM3 base pointer */
+  #define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+  /** Peripheral FLEXCOMM14 base address */
+  #define FLEXCOMM14_BASE                          (0x40126000u)
+  /** Peripheral FLEXCOMM14 base pointer */
+  #define FLEXCOMM14                               ((FLEXCOMM_Type *)FLEXCOMM14_BASE)
+  /** Array initializer of FLEXCOMM peripheral base addresses */
+  #define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM14_BASE }
+  /** Array initializer of FLEXCOMM peripheral base pointers */
+  #define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM14 }
+#endif
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM14_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXSPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXSPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
+  __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
+  __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
+  __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
+  __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
+  __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
+  __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
+  __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
+  __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_0[32];
+  __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
+  __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
+  __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
+  __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
+  __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0xB4 */
+  __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
+  __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
+  __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[24];
+  __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
+  __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
+  __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
+  __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
+  __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
+  __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
+       uint8_t RESERVED_5[8];
+  __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
+  __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
+  __IO uint32_t LUT[64];                           /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[288];
+  __IO uint32_t HADDRSTART;                        /**< HADDR REMAP START ADDR, offset: 0x420 */
+  __IO uint32_t HADDREND;                          /**< HADDR REMAP END ADDR, offset: 0x424 */
+  __IO uint32_t HADDROFFSET;                       /**< HADDR REMAP OFFSET, offset: 0x428 */
+  __IO uint32_t IPEDCTRL;                          /**< IPED function control, offset: 0x42C */
+  __IO uint32_t IPSNSZSTART0;                      /**< IPS nonsecure region Start address of region 0, offset: 0x430 */
+  __IO uint32_t IPSNSZEND0;                        /**< IPS nonsecure region End address of region 0, offset: 0x434 */
+  __IO uint32_t IPSNSZSTART1;                      /**< IPS nonsecure region Start address of region 1, offset: 0x438 */
+  __IO uint32_t IPSNSZEND1;                        /**< IPS nonsecure region End address of region 1, offset: 0x43C */
+  __IO uint32_t AHBBUFREGIONSTART0;                /**< RX BUF Start address of region 0, offset: 0x440 */
+  __IO uint32_t AHBBUFREGIONEND0;                  /**< RX BUF region End address of region 0, offset: 0x444 */
+  __IO uint32_t AHBBUFREGIONSTART1;                /**< RX BUF Start address of region 1, offset: 0x448 */
+  __IO uint32_t AHBBUFREGIONEND1;                  /**< RX BUF region End address of region 1, offset: 0x44C */
+  __IO uint32_t AHBBUFREGIONSTART2;                /**< RX BUF Start address of region 2, offset: 0x450 */
+  __IO uint32_t AHBBUFREGIONEND2;                  /**< RX BUF region End address of region 2, offset: 0x454 */
+  __IO uint32_t AHBBUFREGIONSTART3;                /**< RX BUF Start address of region 3, offset: 0x458 */
+  __IO uint32_t AHBBUFREGIONEND3;                  /**< RX BUF region End address of region 3, offset: 0x45C */
+       uint8_t RESERVED_7[160];
+  __IO uint32_t IPEDCTXCTRL[2];                    /**< IPED context control 0..IPED context control 1, array offset: 0x500, array step: 0x4 */
+       uint8_t RESERVED_8[24];
+  __IO uint32_t IPEDCTX0IV0;                       /**< IPED context0 IV0, offset: 0x520 */
+  __IO uint32_t IPEDCTX0IV1;                       /**< IPED context0 IV1, offset: 0x524 */
+  __IO uint32_t IPEDCTX0START;                     /**< Start address of region 0, offset: 0x528 */
+  __IO uint32_t IPEDCTX0END;                       /**< End address of region 0, offset: 0x52C */
+  __IO uint32_t IPEDCTX0AAD0;                      /**< IPED context0 AAD0, offset: 0x530 */
+  __IO uint32_t IPEDCTX0AAD1;                      /**< IPED context0 AAD1, offset: 0x534 */
+       uint8_t RESERVED_9[8];
+  __IO uint32_t IPEDCTX1IV0;                       /**< IPED context1 IV0, offset: 0x540 */
+  __IO uint32_t IPEDCTX1IV1;                       /**< IPED context1 IV1, offset: 0x544 */
+  __IO uint32_t IPEDCTX1START;                     /**< Start address of region 1, offset: 0x548 */
+  __IO uint32_t IPEDCTX1END;                       /**< End address of region 1, offset: 0x54C */
+  __IO uint32_t IPEDCTX1AAD0;                      /**< IPED context1 AAD0, offset: 0x550 */
+  __IO uint32_t IPEDCTX1AAD1;                      /**< IPED context1 AAD1, offset: 0x554 */
+       uint8_t RESERVED_10[8];
+  __IO uint32_t IPEDCTX2IV0;                       /**< IPED context2 IV0, offset: 0x560 */
+  __IO uint32_t IPEDCTX2IV1;                       /**< IPED context2 IV1, offset: 0x564 */
+  __IO uint32_t IPEDCTX2START;                     /**< Start address of region 2, offset: 0x568 */
+  __IO uint32_t IPEDCTX2END;                       /**< End address of region 2, offset: 0x56C */
+  __IO uint32_t IPEDCTX2AAD0;                      /**< IPED context2 AAD0, offset: 0x570 */
+  __IO uint32_t IPEDCTX2AAD1;                      /**< IPED context2 AAD1, offset: 0x574 */
+       uint8_t RESERVED_11[8];
+  __IO uint32_t IPEDCTX3IV0;                       /**< IPED context3 IV0, offset: 0x580 */
+  __IO uint32_t IPEDCTX3IV1;                       /**< IPED context3 IV1, offset: 0x584 */
+  __IO uint32_t IPEDCTX3START;                     /**< Start address of region 3, offset: 0x588 */
+  __IO uint32_t IPEDCTX3END;                       /**< End address of region 3, offset: 0x58C */
+  __IO uint32_t IPEDCTX3AAD0;                      /**< IPED context3 AAD0, offset: 0x590 */
+  __IO uint32_t IPEDCTX3AAD1;                      /**< IPED context3 AAD1, offset: 0x594 */
+       uint8_t RESERVED_12[8];
+  __IO uint32_t IPEDCTX4IV0;                       /**< IPED context4 IV0, offset: 0x5A0 */
+  __IO uint32_t IPEDCTX4IV1;                       /**< IPED context4 IV1, offset: 0x5A4 */
+  __IO uint32_t IPEDCTX4START;                     /**< Start address of region 4, offset: 0x5A8 */
+  __IO uint32_t IPEDCTX4END;                       /**< End address of region 4, offset: 0x5AC */
+  __IO uint32_t IPEDCTX4AAD0;                      /**< IPED context4 AAD0, offset: 0x5B0 */
+  __IO uint32_t IPEDCTX4AAD1;                      /**< IPED context4 AAD1, offset: 0x5B4 */
+       uint8_t RESERVED_13[8];
+  __IO uint32_t IPEDCTX5IV0;                       /**< IPED context5 IV0, offset: 0x5C0 */
+  __IO uint32_t IPEDCTX5IV1;                       /**< IPED context5 IV1, offset: 0x5C4 */
+  __IO uint32_t IPEDCTX5START;                     /**< Start address of region 5, offset: 0x5C8 */
+  __IO uint32_t IPEDCTX5END;                       /**< End address of region 5, offset: 0x5CC */
+  __IO uint32_t IPEDCTX5AAD0;                      /**< IPED context5 AAD0, offset: 0x5D0 */
+  __IO uint32_t IPEDCTX5AAD1;                      /**< IPED context5 AAD1, offset: 0x5D4 */
+       uint8_t RESERVED_14[8];
+  __IO uint32_t IPEDCTX6IV0;                       /**< IPED context6 IV0, offset: 0x5E0 */
+  __IO uint32_t IPEDCTX6IV1;                       /**< IPED context6 IV1, offset: 0x5E4 */
+  __IO uint32_t IPEDCTX6START;                     /**< Start address of region 6, offset: 0x5E8 */
+  __IO uint32_t IPEDCTX6END;                       /**< End address of region 6, offset: 0x5EC */
+  __IO uint32_t IPEDCTX6AAD0;                      /**< IPED context6 AAD0, offset: 0x5F0 */
+  __IO uint32_t IPEDCTX6AAD1;                      /**< IPED context6 AAD1, offset: 0x5F4 */
+       uint8_t RESERVED_15[8];
+  __IO uint32_t IPEDCTX7IV0;                       /**< IPED context7 IV0, offset: 0x600 */
+  __IO uint32_t IPEDCTX7IV1;                       /**< IPED context7 IV1, offset: 0x604 */
+  __IO uint32_t IPEDCTX7START;                     /**< Start address of region 7, offset: 0x608 */
+  __IO uint32_t IPEDCTX7END;                       /**< End address of region 7, offset: 0x60C */
+  __IO uint32_t IPEDCTX7AAD0;                      /**< IPED context7 AAD0, offset: 0x610 */
+  __IO uint32_t IPEDCTX7AAD1;                      /**< IPED context7 AAD1, offset: 0x614 */
+       uint8_t RESERVED_16[8];
+  __IO uint32_t IPEDCTX8IV0;                       /**< IPED context8 IV0, offset: 0x620 */
+  __IO uint32_t IPEDCTX8IV1;                       /**< IPED context8 IV1, offset: 0x624 */
+  __IO uint32_t IPEDCTX8START;                     /**< Start address of region 8, offset: 0x628 */
+  __IO uint32_t IPEDCTX8END;                       /**< End address of region 8, offset: 0x62C */
+  __IO uint32_t IPEDCTX8AAD0;                      /**< IPED context8 AAD0, offset: 0x630 */
+  __IO uint32_t IPEDCTX8AAD1;                      /**< IPED context8 AAD1, offset: 0x634 */
+       uint8_t RESERVED_17[8];
+  __IO uint32_t IPEDCTX9IV0;                       /**< IPED context9 IV0, offset: 0x640 */
+  __IO uint32_t IPEDCTX9IV1;                       /**< IPED context9 IV1, offset: 0x644 */
+  __IO uint32_t IPEDCTX9START;                     /**< Start address of region 9, offset: 0x648 */
+  __IO uint32_t IPEDCTX9END;                       /**< End address of region 9, offset: 0x64C */
+  __IO uint32_t IPEDCTX9AAD0;                      /**< IPED context9 AAD0, offset: 0x650 */
+  __IO uint32_t IPEDCTX9AAD1;                      /**< IPED context9 AAD1, offset: 0x654 */
+       uint8_t RESERVED_18[8];
+  __IO uint32_t IPEDCTX10IV0;                      /**< IPED context10 IV0, offset: 0x660 */
+  __IO uint32_t IPEDCTX10IV1;                      /**< IPED context10 IV1, offset: 0x664 */
+  __IO uint32_t IPEDCTX10START;                    /**< Start address of region 10, offset: 0x668 */
+  __IO uint32_t IPEDCTX10END;                      /**< End address of region 10, offset: 0x66C */
+  __IO uint32_t IPEDCTX10AAD0;                     /**< IPED context10 AAD0, offset: 0x670 */
+  __IO uint32_t IPEDCTX10AAD1;                     /**< IPED context10 AAD1, offset: 0x674 */
+       uint8_t RESERVED_19[8];
+  __IO uint32_t IPEDCTX11IV0;                      /**< IPED context11 IV0, offset: 0x680 */
+  __IO uint32_t IPEDCTX11IV1;                      /**< IPED context11 IV1, offset: 0x684 */
+  __IO uint32_t IPEDCTX11START;                    /**< Start address of region 11, offset: 0x688 */
+  __IO uint32_t IPEDCTX11END;                      /**< End address of region 11, offset: 0x68C */
+  __IO uint32_t IPEDCTX11AAD0;                     /**< IPED context11 AAD0, offset: 0x690 */
+  __IO uint32_t IPEDCTX11AAD1;                     /**< IPED context11 AAD1, offset: 0x694 */
+       uint8_t RESERVED_20[8];
+  __IO uint32_t IPEDCTX12IV0;                      /**< IPED context12 IV0, offset: 0x6A0 */
+  __IO uint32_t IPEDCTX12IV1;                      /**< IPED context12 IV1, offset: 0x6A4 */
+  __IO uint32_t IPEDCTX12START;                    /**< Start address of region 12, offset: 0x6A8 */
+  __IO uint32_t IPEDCTX12END;                      /**< End address of region 12, offset: 0x6AC */
+  __IO uint32_t IPEDCTX12AAD0;                     /**< IPED context12 AAD0, offset: 0x6B0 */
+  __IO uint32_t IPEDCTX12AAD1;                     /**< IPED context12 AAD1, offset: 0x6B4 */
+       uint8_t RESERVED_21[8];
+  __IO uint32_t IPEDCTX13IV0;                      /**< IPED context13 IV0, offset: 0x6C0 */
+  __IO uint32_t IPEDCTX13IV1;                      /**< IPED context13 IV1, offset: 0x6C4 */
+  __IO uint32_t IPEDCTX13START;                    /**< Start address of region 13, offset: 0x6C8 */
+  __IO uint32_t IPEDCTX13END;                      /**< End address of region 13, offset: 0x6CC */
+  __IO uint32_t IPEDCTX13AAD0;                     /**< IPED context13 AAD0, offset: 0x6D0 */
+  __IO uint32_t IPEDCTX13AAD1;                     /**< IPED context13 AAD1, offset: 0x6D4 */
+       uint8_t RESERVED_22[8];
+  __IO uint32_t IPEDCTX14IV0;                      /**< IPED context14 IV0, offset: 0x6E0 */
+  __IO uint32_t IPEDCTX14IV1;                      /**< IPED context14 IV1, offset: 0x6E4 */
+  __IO uint32_t IPEDCTX14START;                    /**< Start address of region 14, offset: 0x6E8 */
+  __IO uint32_t IPEDCTX14END;                      /**< End address of region 14, offset: 0x6EC */
+  __IO uint32_t IPEDCTX14AAD0;                     /**< IPED context14 AAD0, offset: 0x6F0 */
+  __IO uint32_t IPEDCTX14AAD1;                     /**< IPED context14 AAD1, offset: 0x6F4 */
+} FLEXSPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXSPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
+ * @{
+ */
+
+/*! @name MCR0 - Module Control Register 0 */
+/*! @{ */
+
+#define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
+#define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
+/*! SWRESET - Software Reset */
+#define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
+
+#define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
+#define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
+/*! MDIS - Module Disable */
+#define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
+
+#define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
+#define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
+/*! RXCLKSRC - Sample Clock source selection for Flash Reading
+ *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
+ *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
+ *  0b10..Reserved
+ *  0b11..Flash provided Read strobe and input from DQS pad
+ */
+#define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
+
+#define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
+#define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
+/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
+ *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
+ *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
+ */
+#define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
+
+#define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
+#define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
+/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
+ *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
+ *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
+ */
+#define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
+
+#define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
+#define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
+/*! SERCLKDIV - Serial root clock
+ *  0b000..Divided by 1
+ *  0b001..Divided by 2
+ *  0b010..Divided by 3
+ *  0b011..Divided by 4
+ *  0b100..Divided by 5
+ *  0b101..Divided by 6
+ *  0b110..Divided by 7
+ *  0b111..Divided by 8
+ */
+#define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
+
+#define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
+#define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
+/*! HSEN - Half Speed Serial Flash access Enable.
+ *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
+ *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
+ */
+#define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
+
+#define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
+#define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
+/*! DOZEEN - Doze mode enable bit
+ *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
+ *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
+ */
+#define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
+
+#define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
+#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
+/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data
+ *    pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width.
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
+#define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
+
+#define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
+#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
+/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
+ *    external device may use SCLK as reference clock to its internal PLL.
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
+#define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
+
+#define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
+#define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
+/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
+ *    disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
+ *    is correctly executed.
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
+#define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
+
+#define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
+#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
+/*! IPGRANTWAIT - Timeout wait cycle for IP command grant. */
+#define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
+
+#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
+#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
+/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. */
+#define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
+/*! @} */
+
+/*! @name MCR1 - Module Control Register 1 */
+/*! @{ */
+
+#define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
+#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
+/*! AHBBUSWAIT - AHB Bus wait */
+#define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
+
+#define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
+#define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
+/*! SEQWAIT - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root
+ *    Clock cycles. When sequence execution timeout occurs, there will be an interrupt generated
+ *    (INTR[SEQTIMEOUT]) if this interrupt is enabled (INTEN[SEQTIMEOUTEN] is set 0x1) and AHB command is
+ *    ignored by arbitrator.
+ */
+#define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
+/*! @} */
+
+/*! @name MCR2 - Module Control Register 2 */
+/*! @{ */
+
+#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
+#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
+/*! CLRAHBBUFOPT - Clear AHB buffer
+ *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
+ *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
+ */
+#define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
+
+#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
+#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
+/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
+ *    written with 0x1. This bit will be auto-cleared immediately.
+ */
+#define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
+
+#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
+#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
+/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
+ *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. Disabled.
+ *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
+ */
+#define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
+
+#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
+#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
+/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
+ *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
+ *    field, MCR0[SWRESET] should be set.
+ *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
+ *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
+ */
+#define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
+
+#define FLEXSPI_MCR2_RXCLKSRC_B_MASK             (0x600000U)
+#define FLEXSPI_MCR2_RXCLKSRC_B_SHIFT            (21U)
+/*! RXCLKSRC_B - Sample Clock source selection for Flash Reading
+ *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
+ *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
+ *  0b10..SCLK output clock and loopback from SCLK padReserved
+ *  0b11..Flash provided Read strobe and input from DQS pad
+ */
+#define FLEXSPI_MCR2_RXCLKSRC_B(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RXCLKSRC_B_SHIFT)) & FLEXSPI_MCR2_RXCLKSRC_B_MASK)
+
+#define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK        (0x800000U)
+#define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT       (23U)
+/*! RX_CLK_SRC_DIFF - Sample Clock source or source_b selection for Flash Reading */
+#define FLEXSPI_MCR2_RX_CLK_SRC_DIFF(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT)) & FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK)
+
+#define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
+#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
+/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. */
+#define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
+/*! @} */
+
+/*! @name AHBCR - AHB Bus Control Register */
+/*! @{ */
+
+#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK           (0x2U)
+#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT          (1U)
+/*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared. */
+#define FLEXSPI_AHBCR_CLRAHBRXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
+
+#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK           (0x4U)
+#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT          (2U)
+/*! CLRAHBTXBUF - Clear the status/pointers of AHB TX Buffer. Auto-cleared. */
+#define FLEXSPI_AHBCR_CLRAHBTXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)
+
+#define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
+#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
+/*! CACHABLEEN - Enable AHB bus cachable read access support.
+ *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
+ *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
+ */
+#define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
+
+#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
+#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
+/*! BUFFERABLEEN - Enable AHB bus bufferable write access support.
+ *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
+ *       ready after all data is transmitted to External device and AHB command finished.
+ *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
+ *       granted by arbitrator and will not wait for AHB command finished.
+ */
+#define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
+
+#define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
+#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
+/*! PREFETCHEN - AHB Read Prefetch Enable. */
+#define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
+
+#define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
+#define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
+/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
+ *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in flash is word-addressable.
+ *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
+ *       burst required to meet the alignment requirement.
+ */
+#define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
+
+#define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
+#define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
+/*! READSZALIGN - AHB Read Size Alignment
+ *  0b0..AHB read size will be decided by other register setting like PREFETCH_EN
+ *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
+ */
+#define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
+
+#define FLEXSPI_AHBCR_ALIGNMENT_MASK             (0x300000U)
+#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT            (20U)
+/*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses.
+ *  0b00..No limit
+ *  0b01..1 KBytes
+ *  0b10..512 Bytes
+ *  0b11..256 Bytes
+ */
+#define FLEXSPI_AHBCR_ALIGNMENT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
+/*! @} */
+
+/*! @name INTEN - Interrupt Enable Register */
+/*! @{ */
+
+#define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
+#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
+/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. */
+#define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
+
+#define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
+#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
+/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. */
+#define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
+
+#define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
+#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
+/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. */
+#define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
+
+#define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
+#define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
+/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. */
+#define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
+
+#define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
+#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
+/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. */
+#define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
+
+#define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
+#define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
+/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. */
+#define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
+
+#define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
+#define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
+/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. */
+#define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
+
+#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
+#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
+/*! DATALEARNFAILEN - Data Learning failed interrupt enable. */
+#define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
+
+#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
+#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
+/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. */
+#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
+
+#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
+#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
+/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. */
+#define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
+
+#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
+#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
+/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt. */
+#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
+
+#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
+#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
+/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable. */
+#define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
+
+#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK      (0x10000U)
+#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT     (16U)
+/*! IPCMDSECUREVIOEN - IP command security violation interrupt enable. */
+#define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK)
+
+#define FLEXSPI_INTEN_AHBGCMERREN_MASK           (0x20000U)
+#define FLEXSPI_INTEN_AHBGCMERREN_SHIFT          (17U)
+/*! AHBGCMERREN - AHB read gcm error interrupt enable. */
+#define FLEXSPI_INTEN_AHBGCMERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBGCMERREN_SHIFT)) & FLEXSPI_INTEN_AHBGCMERREN_MASK)
+/*! @} */
+
+/*! @name INTR - Interrupt Register */
+/*! @{ */
+
+#define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
+#define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
+/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
+ *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
+ */
+#define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
+
+#define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
+#define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
+/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. */
+#define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
+
+#define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
+#define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
+/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. */
+#define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
+
+#define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
+#define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
+/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
+ *    IP command, this command will be ignored and not executed at all.
+ */
+#define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
+
+#define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
+#define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
+/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
+ *    AHB command, this command will be ignored and not executed at all.
+ */
+#define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
+
+#define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
+#define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
+/*! IPRXWA - IP RX FIFO watermark available interrupt. */
+#define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
+
+#define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
+#define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
+/*! IPTXWE - IP TX FIFO watermark empty interrupt. */
+#define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
+
+#define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
+#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
+/*! DATALEARNFAIL - Data Learning failed interrupt. */
+#define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
+
+#define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
+#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
+/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. */
+#define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
+
+#define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
+#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
+/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. */
+#define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
+
+#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
+#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
+/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt. */
+#define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
+
+#define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
+#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
+/*! SEQTIMEOUT - Sequence execution timeout interrupt. */
+#define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
+
+#define FLEXSPI_INTR_IPCMDSECUREVIO_MASK         (0x10000U)
+#define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT        (16U)
+/*! IPCMDSECUREVIO - IP command security violation interrupt. */
+#define FLEXSPI_INTR_IPCMDSECUREVIO(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK)
+
+#define FLEXSPI_INTR_AHBGCMERR_MASK              (0x20000U)
+#define FLEXSPI_INTR_AHBGCMERR_SHIFT             (17U)
+/*! AHBGCMERR - AHB read gcm error interrupt. */
+#define FLEXSPI_INTR_AHBGCMERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBGCMERR_SHIFT)) & FLEXSPI_INTR_AHBGCMERR_MASK)
+/*! @} */
+
+/*! @name LUTKEY - LUT Key Register */
+/*! @{ */
+
+#define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
+#define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
+/*! KEY - The Key to lock or unlock LUT. */
+#define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
+/*! @} */
+
+/*! @name LUTCR - LUT Control Register */
+/*! @{ */
+
+#define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
+#define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
+/*! LOCK - Lock LUT */
+#define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
+
+#define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
+#define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
+/*! UNLOCK - Unlock LUT */
+#define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
+
+#define FLEXSPI_LUTCR_PROTECT_MASK               (0x4U)
+#define FLEXSPI_LUTCR_PROTECT_SHIFT              (2U)
+/*! PROTECT - LUT protection */
+#define FLEXSPI_LUTCR_PROTECT(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK)
+/*! @} */
+
+/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
+/*! @{ */
+
+#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0xFFU)
+#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
+/*! BUFSZ - AHB RX Buffer Size in 64 bits. */
+#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
+
+#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
+#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
+/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). */
+#define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
+
+#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
+#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
+/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. */
+#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
+
+#define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK        (0x40000000U)
+#define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT       (30U)
+/*! REGIONEN - AHB RX Buffer address region funciton enable */
+#define FLEXSPI_AHBRXBUFCR0_REGIONEN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK)
+
+#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
+#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
+/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. */
+#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_AHBRXBUFCR0 */
+#define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
+
+/*! @name FLSHCR0 - Flash Control Register 0 */
+/*! @{ */
+
+#define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
+#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
+/*! FLSHSZ - Flash Size in KByte. */
+#define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
+
+#define FLEXSPI_FLSHCR0_ADDRSHIFT_MASK           (0x20000000U)
+#define FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT          (29U)
+/*! ADDRSHIFT - AHB address shift function control.
+ *  0b0..Disabled.
+ *  0b1..Enabled.
+ */
+#define FLEXSPI_FLSHCR0_ADDRSHIFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK)
+
+#define FLEXSPI_FLSHCR0_SPLITWREN_MASK           (0x40000000U)
+#define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT          (30U)
+/*! SPLITWREN - AHB write access split function control. */
+#define FLEXSPI_FLSHCR0_SPLITWREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)
+
+#define FLEXSPI_FLSHCR0_SPLITRDEN_MASK           (0x80000000U)
+#define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT          (31U)
+/*! SPLITRDEN - AHB read access split function control. */
+#define FLEXSPI_FLSHCR0_SPLITRDEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_FLSHCR0 */
+#define FLEXSPI_FLSHCR0_COUNT                    (4U)
+
+/*! @name FLSHCR1 - Flash Control Register 1 */
+/*! @{ */
+
+#define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
+#define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
+/*! TCSS - Serial Flash CS setup time. */
+#define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
+
+#define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
+#define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
+/*! TCSH - Serial Flash CS Hold time. */
+#define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
+
+#define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
+#define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
+/*! WA - Word Addressable. */
+#define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
+
+#define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
+#define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
+/*! CAS - Column Address Size. */
+#define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
+
+#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
+#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
+/*! CSINTERVALUNIT - CS interval unit
+ *  0b0..The CS interval unit is 1 serial clock cycle
+ *  0b1..The CS interval unit is 256 serial clock cycle
+ */
+#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
+
+#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
+#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
+/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
+ *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
+ *    the interval between command sequences, this field should be set accordingly. If there is no
+ *    limitation, set this field with value 0x0.
+ */
+#define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_FLSHCR1 */
+#define FLEXSPI_FLSHCR1_COUNT                    (4U)
+
+/*! @name FLSHCR2 - Flash Control Register 2 */
+/*! @{ */
+
+#define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
+#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
+/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. */
+#define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
+
+#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
+#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
+/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. */
+#define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
+
+#define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
+#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
+/*! AWRSEQID - Sequence Index for AHB Write triggered Command. */
+#define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
+
+#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
+#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
+/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. */
+#define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
+
+#define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
+#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
+/*! AWRWAIT - For certain devices (such as FPGA), it need some time to write data into internal
+ *    memory after the command sequences finished on FlexSPI interface. If another Read command sequence
+ *    comes before previous programming finished internally, the read data may be wrong. This field
+ *    is used to hold AHB Bus ready for AHB write access to wait the programming finished in
+ *    external device. Then there will be no AHB read command triggered before the programming finished in
+ *    external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI
+ *    interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT
+ */
+#define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
+
+#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
+#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
+/*! AWRWAITUNIT - AWRWAIT unit
+ *  0b000..The AWRWAIT unit is 2 ahb clock cycle
+ *  0b001..The AWRWAIT unit is 8 ahb clock cycle
+ *  0b010..The AWRWAIT unit is 32 ahb clock cycle
+ *  0b011..The AWRWAIT unit is 128 ahb clock cycle
+ *  0b100..The AWRWAIT unit is 512 ahb clock cycle
+ *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
+ *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
+ *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
+ */
+#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
+
+#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
+#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
+/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. */
+#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_FLSHCR2 */
+#define FLEXSPI_FLSHCR2_COUNT                    (4U)
+
+/*! @name FLSHCR4 - Flash Control Register 4 */
+/*! @{ */
+
+#define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
+#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
+/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
+ *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
+ *       burst start address alignment when flash is accessed in individual mode.
+ *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
+ *       burst start address alignment when flash is accessed in individual mode.
+ */
+#define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
+
+#define FLEXSPI_FLSHCR4_WMOPT2_MASK              (0x2U)
+#define FLEXSPI_FLSHCR4_WMOPT2_SHIFT             (1U)
+/*! WMOPT2 - Write mask option bit 2. When using AP memory, This option bit could be used to remove
+ *    AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set.
+ *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
+ *       burst length when flash is accessed in individual mode.
+ *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
+ *       burst length when flash is accessed in individual mode, the minimal write burst length should be 4.
+ */
+#define FLEXSPI_FLSHCR4_WMOPT2(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)
+
+#define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
+#define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
+/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
+ *    memory device on port A, this bit must be set.
+ *  0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device.
+ *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
+ */
+#define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
+
+#define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
+#define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
+/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
+ *    memory device on port B, this bit must be set.
+ *  0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device.
+ *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
+ */
+#define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
+
+#define FLEXSPI_FLSHCR4_PAR_WM_MASK              (0x600U)
+#define FLEXSPI_FLSHCR4_PAR_WM_SHIFT             (9U)
+/*! PAR_WM - Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair. */
+#define FLEXSPI_FLSHCR4_PAR_WM(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK)
+
+#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK    (0x800U)
+#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT   (11U)
+/*! PAR_ADDR_ADJ_DIS - Disable the address shift logic for lower density of 16 bit PSRAM. */
+#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK)
+/*! @} */
+
+/*! @name IPCR0 - IP Control Register 0 */
+/*! @{ */
+
+#define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
+#define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
+/*! SFAR - Serial Flash Address for IP command. */
+#define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
+/*! @} */
+
+/*! @name IPCR1 - IP Control Register 1 */
+/*! @{ */
+
+#define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
+#define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
+/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. */
+#define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
+
+#define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
+#define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
+/*! ISEQID - Sequence Index in LUT for IP command. */
+#define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
+
+#define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
+#define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
+/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */
+#define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
+/*! @} */
+
+/*! @name IPCMD - IP Command Register */
+/*! @{ */
+
+#define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
+#define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
+/*! TRG - Setting this bit will trigger an IP Command. */
+#define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
+/*! @} */
+
+/*! @name DLPR - Data Learn Pattern Register */
+/*! @{ */
+
+#define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
+#define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
+/*! DLP - Data Learning Pattern. */
+#define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
+/*! @} */
+
+/*! @name IPRXFCR - IP RX FIFO Control Register */
+/*! @{ */
+
+#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
+#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
+/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. */
+#define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
+
+#define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
+#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
+/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
+ *  0b0..IP RX FIFO would be read by processor.
+ *  0b1..IP RX FIFO would be read by DMA.
+ */
+#define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
+
+#define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x1FCU)
+#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
+/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. */
+#define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
+/*! @} */
+
+/*! @name IPTXFCR - IP TX FIFO Control Register */
+/*! @{ */
+
+#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
+#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
+/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. */
+#define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
+
+#define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
+#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
+/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
+ *  0b0..IP TX FIFO would be filled by processor.
+ *  0b1..IP TX FIFO would be filled by DMA.
+ */
+#define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
+
+#define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
+#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
+/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. */
+#define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
+/*! @} */
+
+/*! @name DLLCR - DLL Control Register 0 */
+/*! @{ */
+
+#define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
+#define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
+/*! DLLEN - DLL calibration enable. */
+#define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
+
+#define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
+#define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
+/*! DLLRESET - DLL reset */
+#define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
+
+#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
+#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
+/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
+ *    of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
+ *    OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
+ */
+#define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
+
+#define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
+#define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
+/*! OVRDEN - Slave clock delay line delay cell number selection override enable. */
+#define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
+
+#define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
+#define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
+/*! OVRDVAL - Slave clock delay line delay cell number selection override value. */
+#define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_DLLCR */
+#define FLEXSPI_DLLCR_COUNT                      (2U)
+
+/*! @name STS0 - Status Register 0 */
+/*! @{ */
+
+#define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
+#define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
+/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
+ *    sequence executing on FlexSPI interface.
+ */
+#define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
+
+#define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
+#define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
+/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
+ *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
+ *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
+ *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
+ */
+#define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
+
+#define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
+#define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
+/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
+ *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
+ *  0b00..Triggered by AHB read command (triggered by AHB read).
+ *  0b01..Triggered by AHB write command (triggered by AHB Write).
+ *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
+ *  0b11..Triggered by suspended command (resumed).
+ */
+#define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
+
+#define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
+#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
+/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. */
+#define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
+
+#define FLEXSPI_STS0_DATALEARNPHASEB_MASK        (0xF00U)
+#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT       (8U)
+/*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning. */
+#define FLEXSPI_STS0_DATALEARNPHASEB(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
+/*! @} */
+
+/*! @name STS1 - Status Register 1 */
+/*! @{ */
+
+#define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
+#define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
+/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
+ *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
+ */
+#define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
+
+#define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
+#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
+/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
+ *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
+ *  0b0000..No error.
+ *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
+ *  0b0011..There is unknown instruction opcode in the sequence.
+ *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
+ *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
+ *  0b1110..Sequence execution timeout.
+ */
+#define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
+
+#define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
+#define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
+/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. */
+#define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
+
+#define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
+#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
+/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
+ *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
+ *  0b0000..No error.
+ *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
+ *  0b0011..There is unknown instruction opcode in the sequence.
+ *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
+ *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
+ *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
+ *  0b1110..Sequence execution timeout.
+ *  0b1111..Flash boundary crossed.
+ */
+#define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
+/*! @} */
+
+/*! @name STS2 - Status Register 2 */
+/*! @{ */
+
+#define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
+#define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
+/*! ASLVLOCK - Flash A sample clock slave delay line locked. */
+#define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
+
+#define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
+#define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
+/*! AREFLOCK - Flash A sample clock reference delay line locked. */
+#define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
+
+#define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
+#define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
+/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . */
+#define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
+
+#define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
+#define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
+/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. */
+#define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
+
+#define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
+#define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
+/*! BSLVLOCK - Flash B sample clock slave delay line locked. */
+#define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
+
+#define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
+#define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
+/*! BREFLOCK - Flash B sample clock reference delay line locked. */
+#define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
+
+#define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
+#define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
+/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. */
+#define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
+
+#define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
+#define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
+/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. */
+#define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
+/*! @} */
+
+/*! @name AHBSPNDSTS - AHB Suspend Status Register */
+/*! @{ */
+
+#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
+#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
+/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. */
+#define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
+
+#define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
+#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
+/*! BUFID - AHB RX BUF ID for suspended command sequence. */
+#define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
+
+#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
+#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
+/*! DATLFT - Left Data size for suspended command sequence (in byte). */
+#define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
+/*! @} */
+
+/*! @name IPRXFSTS - IP RX FIFO Status Register */
+/*! @{ */
+
+#define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
+#define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
+/*! FILL - Fill level of IP RX FIFO. */
+#define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
+
+#define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
+#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
+/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. */
+#define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
+/*! @} */
+
+/*! @name IPTXFSTS - IP TX FIFO Status Register */
+/*! @{ */
+
+#define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
+#define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
+/*! FILL - Fill level of IP TX FIFO. */
+#define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
+
+#define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
+#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
+/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. */
+#define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
+/*! @} */
+
+/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
+/*! @{ */
+
+#define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
+#define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
+/*! RXDATA - RX Data */
+#define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_RFDR */
+#define FLEXSPI_RFDR_COUNT                       (32U)
+
+/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
+/*! @{ */
+
+#define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
+#define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
+/*! TXDATA - TX Data */
+#define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_TFDR */
+#define FLEXSPI_TFDR_COUNT                       (32U)
+
+/*! @name LUT - LUT 0..LUT 63 */
+/*! @{ */
+
+#define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
+#define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
+/*! OPERAND0 - OPERAND0 */
+#define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
+
+#define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
+#define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
+/*! NUM_PADS0 - NUM_PADS0 */
+#define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
+
+#define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
+#define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
+/*! OPCODE0 - OPCODE */
+#define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
+
+#define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
+#define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
+/*! OPERAND1 - OPERAND1 */
+#define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
+
+#define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
+#define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
+/*! NUM_PADS1 - NUM_PADS1 */
+#define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
+
+#define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
+#define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
+/*! OPCODE1 - OPCODE1 */
+#define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_LUT */
+#define FLEXSPI_LUT_COUNT                        (64U)
+
+/*! @name HADDRSTART - HADDR REMAP START ADDR */
+/*! @{ */
+
+#define FLEXSPI_HADDRSTART_REMAPEN_MASK          (0x1U)
+#define FLEXSPI_HADDRSTART_REMAPEN_SHIFT         (0U)
+/*! REMAPEN - AHB Bus address remap function enable
+ *  0b0..HADDR REMAP Disabled
+ *  0b1..HADDR REMAP Enabled
+ */
+#define FLEXSPI_HADDRSTART_REMAPEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)
+
+#define FLEXSPI_HADDRSTART_ADDRSTART_MASK        (0xFFFFF000U)
+#define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT       (12U)
+/*! ADDRSTART - HADDR start address */
+#define FLEXSPI_HADDRSTART_ADDRSTART(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
+/*! @} */
+
+/*! @name HADDREND - HADDR REMAP END ADDR */
+/*! @{ */
+
+#define FLEXSPI_HADDREND_ENDSTART_MASK           (0xFFFFF000U)
+#define FLEXSPI_HADDREND_ENDSTART_SHIFT          (12U)
+/*! ENDSTART - HADDR remap range's end addr, 4K aligned */
+#define FLEXSPI_HADDREND_ENDSTART(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
+/*! @} */
+
+/*! @name HADDROFFSET - HADDR REMAP OFFSET */
+/*! @{ */
+
+#define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK      (0xFFFFF000U)
+#define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT     (12U)
+/*! ADDROFFSET - HADDR offset field, remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFFSET */
+#define FLEXSPI_HADDROFFSET_ADDROFFSET(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
+/*! @} */
+
+/*! @name IPEDCTRL - IPED function control */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTRL_CONFIG_MASK             (0x1U)
+#define FLEXSPI_IPEDCTRL_CONFIG_SHIFT            (0U)
+/*! CONFIG - Drive IPED interface i_config. */
+#define FLEXSPI_IPEDCTRL_CONFIG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_CONFIG_SHIFT)) & FLEXSPI_IPEDCTRL_CONFIG_MASK)
+
+#define FLEXSPI_IPEDCTRL_IPED_EN_MASK            (0x2U)
+#define FLEXSPI_IPEDCTRL_IPED_EN_SHIFT           (1U)
+/*! IPED_EN - Drive IPED interface i_enable */
+#define FLEXSPI_IPEDCTRL_IPED_EN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_EN_MASK)
+
+#define FLEXSPI_IPEDCTRL_IPWR_EN_MASK            (0x4U)
+#define FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT           (2U)
+/*! IPWR_EN - IP write IPED CTR mode encryption enable */
+#define FLEXSPI_IPEDCTRL_IPWR_EN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPWR_EN_MASK)
+
+#define FLEXSPI_IPEDCTRL_AHBWR_EN_MASK           (0x8U)
+#define FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT          (3U)
+/*! AHBWR_EN - AHB write IPED CTR mode encryption enable */
+#define FLEXSPI_IPEDCTRL_AHBWR_EN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBWR_EN_MASK)
+
+#define FLEXSPI_IPEDCTRL_AHBRD_EN_MASK           (0x10U)
+#define FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT          (4U)
+/*! AHBRD_EN - AHB read IPED CTR mode decryption enable */
+#define FLEXSPI_IPEDCTRL_AHBRD_EN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBRD_EN_MASK)
+
+#define FLEXSPI_IPEDCTRL_IPWROTA_MASK            (0x20U)
+#define FLEXSPI_IPEDCTRL_IPWROTA_SHIFT           (5U)
+/*! IPWROTA - IP GCM mode command write OTA region */
+#define FLEXSPI_IPEDCTRL_IPWROTA(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPWROTA_SHIFT)) & FLEXSPI_IPEDCTRL_IPWROTA_MASK)
+
+#define FLEXSPI_IPEDCTRL_IPGCMWR_MASK            (0x40U)
+#define FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT           (6U)
+/*! IPGCMWR - IP write GCM mode enable */
+#define FLEXSPI_IPEDCTRL_IPGCMWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_IPGCMWR_MASK)
+
+#define FLEXSPI_IPEDCTRL_AHGCMWR_MASK            (0x80U)
+#define FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT           (7U)
+/*! AHGCMWR - AHB write IPED GCM mode encryption enable */
+#define FLEXSPI_IPEDCTRL_AHGCMWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_AHGCMWR_MASK)
+
+#define FLEXSPI_IPEDCTRL_AHBGCMRD_MASK           (0x100U)
+#define FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT          (8U)
+/*! AHBGCMRD - AHB read IPED GCM mode decryption enable */
+#define FLEXSPI_IPEDCTRL_AHBGCMRD(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT)) & FLEXSPI_IPEDCTRL_AHBGCMRD_MASK)
+
+#define FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK       (0x200U)
+#define FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT      (9U)
+/*! IPED_PROTECT - when ipedctrl protect = 0 or priviledge access, no restriction when ipedctrl
+ *    protect = 1, only priviledge access can write.
+ */
+#define FLEXSPI_IPEDCTRL_IPED_PROTECT(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK)
+
+#define FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK       (0x400U)
+#define FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT      (10U)
+/*! IPED_SWRESET - Drive IPED interface i_abort. */
+#define FLEXSPI_IPEDCTRL_IPED_SWRESET(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK)
+/*! @} */
+
+/*! @name IPSNSZSTART0 - IPS nonsecure region Start address of region 0 */
+/*! @{ */
+
+#define FLEXSPI_IPSNSZSTART0_START_ADDRESS_MASK  (0xFFFFF000U)
+#define FLEXSPI_IPSNSZSTART0_START_ADDRESS_SHIFT (12U)
+/*! START_ADDRESS - Start address of region 0. Minimal 4K Bytes aligned. It is flash address. */
+#define FLEXSPI_IPSNSZSTART0_START_ADDRESS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_IPSNSZSTART0_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPSNSZEND0 - IPS nonsecure region End address of region 0 */
+/*! @{ */
+
+#define FLEXSPI_IPSNSZEND0_END_ADDRESS_MASK      (0xFFFFF000U)
+#define FLEXSPI_IPSNSZEND0_END_ADDRESS_SHIFT     (12U)
+/*! END_ADDRESS - End address of region 0. Minimal 4K Bytes aligned. It is flash address. */
+#define FLEXSPI_IPSNSZEND0_END_ADDRESS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_END_ADDRESS_SHIFT)) & FLEXSPI_IPSNSZEND0_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPSNSZSTART1 - IPS nonsecure region Start address of region 1 */
+/*! @{ */
+
+#define FLEXSPI_IPSNSZSTART1_START_ADDRESS_MASK  (0xFFFFF000U)
+#define FLEXSPI_IPSNSZSTART1_START_ADDRESS_SHIFT (12U)
+/*! START_ADDRESS - Start address of region 1. Minimal 4K Bytes aligned. It is flash address. */
+#define FLEXSPI_IPSNSZSTART1_START_ADDRESS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_IPSNSZSTART1_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPSNSZEND1 - IPS nonsecure region End address of region 1 */
+/*! @{ */
+
+#define FLEXSPI_IPSNSZEND1_END_ADDRESS_MASK      (0xFFFFF000U)
+#define FLEXSPI_IPSNSZEND1_END_ADDRESS_SHIFT     (12U)
+/*! END_ADDRESS - End address of region 1. Minimal 4K Bytes aligned. It is flash address. */
+#define FLEXSPI_IPSNSZEND1_END_ADDRESS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_END_ADDRESS_SHIFT)) & FLEXSPI_IPSNSZEND1_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONSTART0 - RX BUF Start address of region 0 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT (12U)
+/*! START_ADDRESS - Start address of region 0. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONEND0 - RX BUF region End address of region 0 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT (12U)
+/*! END_ADDRESS - End address of region 0. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONSTART1 - RX BUF Start address of region 1 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT (12U)
+/*! START_ADDRESS - Start address of region 1. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONEND1 - RX BUF region End address of region 1 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT (12U)
+/*! END_ADDRESS - End address of region 1. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONSTART2 - RX BUF Start address of region 2 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT (12U)
+/*! START_ADDRESS - Start address of region 2. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONEND2 - RX BUF region End address of region 2 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT (12U)
+/*! END_ADDRESS - End address of region 2. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONSTART3 - RX BUF Start address of region 3 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT (12U)
+/*! START_ADDRESS - Start address of region 3. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name AHBBUFREGIONEND3 - RX BUF region End address of region 3 */
+/*! @{ */
+
+#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK (0xFFFFF000U)
+#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT (12U)
+/*! END_ADDRESS - End address of region 3. Minimal 4K Bytes aligned. It is system address. */
+#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTXCTRL - IPED context control 0..IPED context control 1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK    (0x3U)
+#define FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT   (0U)
+/*! CTX0_FREEZE0 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_MASK    (0x3U)
+#define FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT   (0U)
+/*! CTX0_FREEZE1 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE0_MASK    (0xCU)
+#define FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT   (2U)
+/*! CTX1_FREEZE0 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE1_MASK    (0xCU)
+#define FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT   (2U)
+/*! CTX1_FREEZE1 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX1_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE0_MASK    (0x30U)
+#define FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT   (4U)
+/*! CTX2_FREEZE0 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE1_MASK    (0x30U)
+#define FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT   (4U)
+/*! CTX2_FREEZE1 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX2_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE0_MASK    (0xC0U)
+#define FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT   (6U)
+/*! CTX3_FREEZE0 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE1_MASK    (0xC0U)
+#define FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT   (6U)
+/*! CTX3_FREEZE1 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX3_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE0_MASK    (0x300U)
+#define FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE0_SHIFT   (8U)
+/*! CTX4_FREEZE0 - Controls the RW properties of this field and region 4 context registers (CTX4_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE1_MASK    (0x300U)
+#define FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE1_SHIFT   (8U)
+/*! CTX4_FREEZE1 - Controls the RW properties of this field and region 4 context registers (CTX4_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX4_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE0_MASK    (0xC00U)
+#define FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE0_SHIFT   (10U)
+/*! CTX5_FREEZE0 - Controls the RW properties of this field and region 5 context registers (CTX5_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE1_MASK    (0xC00U)
+#define FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE1_SHIFT   (10U)
+/*! CTX5_FREEZE1 - Controls the RW properties of this field and region 5 context registers (CTX5_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX5_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE0_MASK    (0x3000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE0_SHIFT   (12U)
+/*! CTX6_FREEZE0 - Controls the RW properties of this field and region 6 context registers (CTX6_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE1_MASK    (0x3000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE1_SHIFT   (12U)
+/*! CTX6_FREEZE1 - Controls the RW properties of this field and region 6 context registers (CTX6_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX6_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE0_MASK    (0xC000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE0_SHIFT   (14U)
+/*! CTX7_FREEZE0 - Controls the RW properties of this field and region 7 context registers (CTX7_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE1_MASK    (0xC000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE1_SHIFT   (14U)
+/*! CTX7_FREEZE1 - Controls the RW properties of this field and region 7 context registers (CTX7_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX7_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE0_MASK    (0x30000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE0_SHIFT   (16U)
+/*! CTX8_FREEZE0 - Controls the RW properties of this field and region 8 context registers (CTX8_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE1_MASK    (0x30000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE1_SHIFT   (16U)
+/*! CTX8_FREEZE1 - Controls the RW properties of this field and region 8 context registers (CTX8_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX8_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE0_MASK    (0xC0000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE0_SHIFT   (18U)
+/*! CTX9_FREEZE0 - Controls the RW properties of this field and region 9 context registers (CTX9_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE1_MASK    (0xC0000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE1_SHIFT   (18U)
+/*! CTX9_FREEZE1 - Controls the RW properties of this field and region 9 context registers (CTX9_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX9_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE0_MASK   (0x300000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE0_SHIFT  (20U)
+/*! CTX10_FREEZE0 - Controls the RW properties of this field and region 10 context registers (CTX10_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE0(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE1_MASK   (0x300000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE1_SHIFT  (20U)
+/*! CTX10_FREEZE1 - Controls the RW properties of this field and region 10 context registers (CTX10_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE1(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX10_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE0_MASK   (0xC00000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE0_SHIFT  (22U)
+/*! CTX11_FREEZE0 - Controls the RW properties of this field and region 11 context registers (CTX11_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE0(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE1_MASK   (0xC00000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE1_SHIFT  (22U)
+/*! CTX11_FREEZE1 - Controls the RW properties of this field and region 11 context registers (CTX11_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE1(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX11_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE0_MASK   (0x3000000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE0_SHIFT  (24U)
+/*! CTX12_FREEZE0 - Controls the RW properties of this field and region 12 context registers (CTX12_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE0(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE1_MASK   (0x3000000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE1_SHIFT  (24U)
+/*! CTX12_FREEZE1 - Controls the RW properties of this field and region 12 context registers (CTX12_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE1(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX12_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE0_MASK   (0xC000000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE0_SHIFT  (26U)
+/*! CTX13_FREEZE0 - Controls the RW properties of this field and region 13 context registers (CTX13_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE0(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE1_MASK   (0xC000000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE1_SHIFT  (26U)
+/*! CTX13_FREEZE1 - Controls the RW properties of this field and region 13 context registers (CTX13_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE1(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX13_FREEZE1_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE0_MASK   (0x30000000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE0_SHIFT  (28U)
+/*! CTX14_FREEZE0 - Controls the RW properties of this field and region 14 context registers (CTX14_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE0(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE0_MASK)
+
+#define FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE1_MASK   (0x30000000U)
+#define FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE1_SHIFT  (28U)
+/*! CTX14_FREEZE1 - Controls the RW properties of this field and region 14 context registers (CTX14_xxxx). */
+#define FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE1(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRL_CTX14_FREEZE1_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_IPEDCTXCTRL */
+#define FLEXSPI_IPEDCTXCTRL_COUNT                (2U)
+
+/*! @name IPEDCTX0IV0 - IPED context0 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT       (0U)
+/*! CTX0_IV0 - Lowest 32 bits of IV for region 0. */
+#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT)) & FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX0IV1 - IPED context0 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT       (0U)
+/*! CTX0_IV1 - Highest 32 bits of IV for region 0. */
+#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT)) & FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX0START - Start address of region 0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX0START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX0START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX0START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_GCM_SHIFT)) & FLEXSPI_IPEDCTX0START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX0START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX0START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX0START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX0START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX0START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX0START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 0. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX0START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX0START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX0END - End address of region 0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX0END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX0END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 0. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX0END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX0END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX0AAD0 - IPED context0 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT     (0U)
+/*! CTX0_AAD0 - Lowest 32 bits of AAD for region 0. */
+#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT)) & FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX0AAD1 - IPED context0 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT     (0U)
+/*! CTX0_AAD1 - Highest 32 bits of AAD for region 0. */
+#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT)) & FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX1IV0 - IPED context1 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT       (0U)
+/*! CTX1_IV0 - Lowest 32 bits of IV for region 1. */
+#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT)) & FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX1IV1 - IPED context1 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT       (0U)
+/*! CTX1_IV1 - Highest 32 bits of IV for region 1. */
+#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT)) & FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX1START - Start address of region 1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX1START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX1START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX1START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_GCM_SHIFT)) & FLEXSPI_IPEDCTX1START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX1START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX1START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX1START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX1START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX1START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX1START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 1. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX1START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX1START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX1END - End address of region 1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX1END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX1END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 1. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX1END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX1END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX1AAD0 - IPED context1 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT     (0U)
+/*! CTX1_AAD0 - Lowest 32 bits of AAD for region 1. */
+#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT)) & FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX1AAD1 - IPED context1 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT     (0U)
+/*! CTX1_AAD1 - Highest 32 bits of AAD for region 1. */
+#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT)) & FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX2IV0 - IPED context2 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT       (0U)
+/*! CTX2_IV0 - Lowest 32 bits of IV for region 2. */
+#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT)) & FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX2IV1 - IPED context2 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT       (0U)
+/*! CTX2_IV1 - Highest 32 bits of IV for region 2. */
+#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT)) & FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX2START - Start address of region 2 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX2START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX2START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX2START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_GCM_SHIFT)) & FLEXSPI_IPEDCTX2START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX2START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX2START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX2START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX2START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX2START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX2START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 2. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX2START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX2START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX2END - End address of region 2 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX2END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX2END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 2. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX2END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX2END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX2AAD0 - IPED context2 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT     (0U)
+/*! CTX2_AAD0 - Lowest 32 bits of AAD for region 2. */
+#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT)) & FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX2AAD1 - IPED context2 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT     (0U)
+/*! CTX2_AAD1 - Highest 32 bits of AAD for region 2. */
+#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT)) & FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX3IV0 - IPED context3 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT       (0U)
+/*! CTX3_IV0 - Lowest 32 bits of IV for region 3. */
+#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT)) & FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX3IV1 - IPED context3 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT       (0U)
+/*! CTX3_IV1 - Highest 32 bits of IV for region 3. */
+#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT)) & FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX3START - Start address of region 3 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX3START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX3START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX3START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_GCM_SHIFT)) & FLEXSPI_IPEDCTX3START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX3START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX3START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX3START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX3START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX3START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX3START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 3. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX3START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX3START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX3END - End address of region 3 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX3END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX3END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 3. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX3END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX3END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX3AAD0 - IPED context3 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT     (0U)
+/*! CTX3_AAD0 - Lowest 32 bits of AAD for region 3. */
+#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT)) & FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX3AAD1 - IPED context3 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT     (0U)
+/*! CTX3_AAD1 - Highest 32 bits of AAD for region 3. */
+#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT)) & FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX4IV0 - IPED context4 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX4IV0_CTX4_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX4IV0_CTX4_IV0_SHIFT       (0U)
+/*! CTX4_IV0 - Lowest 32 bits of IV for region 4. */
+#define FLEXSPI_IPEDCTX4IV0_CTX4_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4IV0_CTX4_IV0_SHIFT)) & FLEXSPI_IPEDCTX4IV0_CTX4_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX4IV1 - IPED context4 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX4IV1_CTX4_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX4IV1_CTX4_IV1_SHIFT       (0U)
+/*! CTX4_IV1 - Highest 32 bits of IV for region 4. */
+#define FLEXSPI_IPEDCTX4IV1_CTX4_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4IV1_CTX4_IV1_SHIFT)) & FLEXSPI_IPEDCTX4IV1_CTX4_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX4START - Start address of region 4 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX4START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX4START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX4START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_GCM_SHIFT)) & FLEXSPI_IPEDCTX4START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX4START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX4START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX4START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX4START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX4START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX4START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 4. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX4START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX4START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX4END - End address of region 4 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX4END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX4END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 4. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX4END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX4END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX4AAD0 - IPED context4 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_SHIFT     (0U)
+/*! CTX4_AAD0 - Lowest 32 bits of AAD for region 4. */
+#define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_SHIFT)) & FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX4AAD1 - IPED context4 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_SHIFT     (0U)
+/*! CTX4_AAD1 - Highest 32 bits of AAD for region 4. */
+#define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_SHIFT)) & FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX5IV0 - IPED context5 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX5IV0_CTX5_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX5IV0_CTX5_IV0_SHIFT       (0U)
+/*! CTX5_IV0 - Lowest 32 bits of IV for region 5. */
+#define FLEXSPI_IPEDCTX5IV0_CTX5_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5IV0_CTX5_IV0_SHIFT)) & FLEXSPI_IPEDCTX5IV0_CTX5_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX5IV1 - IPED context5 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX5IV1_CTX5_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX5IV1_CTX5_IV1_SHIFT       (0U)
+/*! CTX5_IV1 - Highest 32 bits of IV for region 5. */
+#define FLEXSPI_IPEDCTX5IV1_CTX5_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5IV1_CTX5_IV1_SHIFT)) & FLEXSPI_IPEDCTX5IV1_CTX5_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX5START - Start address of region 5 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX5START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX5START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX5START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_GCM_SHIFT)) & FLEXSPI_IPEDCTX5START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX5START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX5START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX5START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX5START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX5START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX5START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 5. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX5START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX5START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX5END - End address of region 5 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX5END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX5END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 5. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX5END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX5END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX5AAD0 - IPED context5 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_SHIFT     (0U)
+/*! CTX5_AAD0 - Lowest 32 bits of AAD for region 5. */
+#define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_SHIFT)) & FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX5AAD1 - IPED context5 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_SHIFT     (0U)
+/*! CTX5_AAD1 - Highest 32 bits of AAD for region 5. */
+#define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_SHIFT)) & FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX6IV0 - IPED context6 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX6IV0_CTX6_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX6IV0_CTX6_IV0_SHIFT       (0U)
+/*! CTX6_IV0 - Lowest 32 bits of IV for region 6. */
+#define FLEXSPI_IPEDCTX6IV0_CTX6_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6IV0_CTX6_IV0_SHIFT)) & FLEXSPI_IPEDCTX6IV0_CTX6_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX6IV1 - IPED context6 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX6IV1_CTX6_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX6IV1_CTX6_IV1_SHIFT       (0U)
+/*! CTX6_IV1 - Highest 32 bits of IV for region 6. */
+#define FLEXSPI_IPEDCTX6IV1_CTX6_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6IV1_CTX6_IV1_SHIFT)) & FLEXSPI_IPEDCTX6IV1_CTX6_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX6START - Start address of region 6 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX6START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX6START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX6START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_GCM_SHIFT)) & FLEXSPI_IPEDCTX6START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX6START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX6START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX6START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX6START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX6START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX6START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 6. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX6START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX6START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX6END - End address of region 6 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX6END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX6END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 6. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX6END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX6END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX6AAD0 - IPED context6 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_SHIFT     (0U)
+/*! CTX6_AAD0 - Lowest 32 bits of AAD for region 6. */
+#define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_SHIFT)) & FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX6AAD1 - IPED context6 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_SHIFT     (0U)
+/*! CTX6_AAD1 - Highest 32 bits of AAD for region 6. */
+#define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_SHIFT)) & FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX7IV0 - IPED context7 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX7IV0_CTX7_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX7IV0_CTX7_IV0_SHIFT       (0U)
+/*! CTX7_IV0 - Lowest 32 bits of IV for region 7. */
+#define FLEXSPI_IPEDCTX7IV0_CTX7_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7IV0_CTX7_IV0_SHIFT)) & FLEXSPI_IPEDCTX7IV0_CTX7_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX7IV1 - IPED context7 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX7IV1_CTX7_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX7IV1_CTX7_IV1_SHIFT       (0U)
+/*! CTX7_IV1 - Highest 32 bits of IV for region 7. */
+#define FLEXSPI_IPEDCTX7IV1_CTX7_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7IV1_CTX7_IV1_SHIFT)) & FLEXSPI_IPEDCTX7IV1_CTX7_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX7START - Start address of region 7 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX7START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX7START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX7START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7START_GCM_SHIFT)) & FLEXSPI_IPEDCTX7START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX7START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX7START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX7START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX7START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX7START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX7START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 7. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX7START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX7START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX7END - End address of region 7 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX7END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX7END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 7. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX7END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX7END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX7AAD0 - IPED context7 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX7AAD0_CTX7_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX7AAD0_CTX7_AAD0_SHIFT     (0U)
+/*! CTX7_AAD0 - Lowest 32 bits of AAD for region 7. */
+#define FLEXSPI_IPEDCTX7AAD0_CTX7_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7AAD0_CTX7_AAD0_SHIFT)) & FLEXSPI_IPEDCTX7AAD0_CTX7_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX7AAD1 - IPED context7 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX7AAD1_CTX7_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX7AAD1_CTX7_AAD1_SHIFT     (0U)
+/*! CTX7_AAD1 - Highest 32 bits of AAD for region 7. */
+#define FLEXSPI_IPEDCTX7AAD1_CTX7_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX7AAD1_CTX7_AAD1_SHIFT)) & FLEXSPI_IPEDCTX7AAD1_CTX7_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX8IV0 - IPED context8 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX8IV0_CTX8_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX8IV0_CTX8_IV0_SHIFT       (0U)
+/*! CTX8_IV0 - Lowest 32 bits of IV for region 8. */
+#define FLEXSPI_IPEDCTX8IV0_CTX8_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8IV0_CTX8_IV0_SHIFT)) & FLEXSPI_IPEDCTX8IV0_CTX8_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX8IV1 - IPED context8 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX8IV1_CTX8_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX8IV1_CTX8_IV1_SHIFT       (0U)
+/*! CTX8_IV1 - Highest 32 bits of IV for region 8. */
+#define FLEXSPI_IPEDCTX8IV1_CTX8_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8IV1_CTX8_IV1_SHIFT)) & FLEXSPI_IPEDCTX8IV1_CTX8_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX8START - Start address of region 8 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX8START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX8START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX8START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8START_GCM_SHIFT)) & FLEXSPI_IPEDCTX8START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX8START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX8START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX8START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX8START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX8START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX8START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 8. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX8START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX8START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX8END - End address of region 8 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX8END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX8END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 8. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX8END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX8END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX8AAD0 - IPED context8 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX8AAD0_CTX8_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX8AAD0_CTX8_AAD0_SHIFT     (0U)
+/*! CTX8_AAD0 - Lowest 32 bits of AAD for region 8. */
+#define FLEXSPI_IPEDCTX8AAD0_CTX8_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8AAD0_CTX8_AAD0_SHIFT)) & FLEXSPI_IPEDCTX8AAD0_CTX8_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX8AAD1 - IPED context8 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX8AAD1_CTX8_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX8AAD1_CTX8_AAD1_SHIFT     (0U)
+/*! CTX8_AAD1 - Highest 32 bits of AAD for region 8. */
+#define FLEXSPI_IPEDCTX8AAD1_CTX8_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX8AAD1_CTX8_AAD1_SHIFT)) & FLEXSPI_IPEDCTX8AAD1_CTX8_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX9IV0 - IPED context9 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX9IV0_CTX9_IV0_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX9IV0_CTX9_IV0_SHIFT       (0U)
+/*! CTX9_IV0 - Lowest 32 bits of IV for region 9. */
+#define FLEXSPI_IPEDCTX9IV0_CTX9_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9IV0_CTX9_IV0_SHIFT)) & FLEXSPI_IPEDCTX9IV0_CTX9_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX9IV1 - IPED context9 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX9IV1_CTX9_IV1_MASK        (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX9IV1_CTX9_IV1_SHIFT       (0U)
+/*! CTX9_IV1 - Highest 32 bits of IV for region 9. */
+#define FLEXSPI_IPEDCTX9IV1_CTX9_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9IV1_CTX9_IV1_SHIFT)) & FLEXSPI_IPEDCTX9IV1_CTX9_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX9START - Start address of region 9 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX9START_GCM_MASK           (0x1U)
+#define FLEXSPI_IPEDCTX9START_GCM_SHIFT          (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX9START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9START_GCM_SHIFT)) & FLEXSPI_IPEDCTX9START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX9START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX9START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX9START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX9START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX9START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX9START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 9. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX9START_START_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX9START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX9END - End address of region 9 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX9END_END_ADDRESS_MASK     (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX9END_END_ADDRESS_SHIFT    (8U)
+/*! END_ADDRESS - End address of region 9. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX9END_END_ADDRESS(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX9END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX9AAD0 - IPED context9 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX9AAD0_CTX9_AAD0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX9AAD0_CTX9_AAD0_SHIFT     (0U)
+/*! CTX9_AAD0 - Lowest 32 bits of AAD for region 9. */
+#define FLEXSPI_IPEDCTX9AAD0_CTX9_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9AAD0_CTX9_AAD0_SHIFT)) & FLEXSPI_IPEDCTX9AAD0_CTX9_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX9AAD1 - IPED context9 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX9AAD1_CTX9_AAD1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX9AAD1_CTX9_AAD1_SHIFT     (0U)
+/*! CTX9_AAD1 - Highest 32 bits of AAD for region 9. */
+#define FLEXSPI_IPEDCTX9AAD1_CTX9_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX9AAD1_CTX9_AAD1_SHIFT)) & FLEXSPI_IPEDCTX9AAD1_CTX9_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX10IV0 - IPED context10 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX10IV0_CTX10_IV0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX10IV0_CTX10_IV0_SHIFT     (0U)
+/*! CTX10_IV0 - Lowest 32 bits of IV for region 10. */
+#define FLEXSPI_IPEDCTX10IV0_CTX10_IV0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10IV0_CTX10_IV0_SHIFT)) & FLEXSPI_IPEDCTX10IV0_CTX10_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX10IV1 - IPED context10 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX10IV1_CTX10_IV1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX10IV1_CTX10_IV1_SHIFT     (0U)
+/*! CTX10_IV1 - Highest 32 bits of IV for region 10. */
+#define FLEXSPI_IPEDCTX10IV1_CTX10_IV1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10IV1_CTX10_IV1_SHIFT)) & FLEXSPI_IPEDCTX10IV1_CTX10_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX10START - Start address of region 10 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX10START_GCM_MASK          (0x1U)
+#define FLEXSPI_IPEDCTX10START_GCM_SHIFT         (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX10START_GCM(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10START_GCM_SHIFT)) & FLEXSPI_IPEDCTX10START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX10START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX10START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX10START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX10START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX10START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX10START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 10. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX10START_START_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX10START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX10END - End address of region 10 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX10END_END_ADDRESS_MASK    (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX10END_END_ADDRESS_SHIFT   (8U)
+/*! END_ADDRESS - End address of region 10. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX10END_END_ADDRESS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX10END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX10AAD0 - IPED context10 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX10AAD0_CTX10_AAD0_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX10AAD0_CTX10_AAD0_SHIFT   (0U)
+/*! CTX10_AAD0 - Lowest 32 bits of AAD for region 10. */
+#define FLEXSPI_IPEDCTX10AAD0_CTX10_AAD0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10AAD0_CTX10_AAD0_SHIFT)) & FLEXSPI_IPEDCTX10AAD0_CTX10_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX10AAD1 - IPED context10 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX10AAD1_CTX10_AAD1_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX10AAD1_CTX10_AAD1_SHIFT   (0U)
+/*! CTX10_AAD1 - Highest 32 bits of AAD for region 10. */
+#define FLEXSPI_IPEDCTX10AAD1_CTX10_AAD1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX10AAD1_CTX10_AAD1_SHIFT)) & FLEXSPI_IPEDCTX10AAD1_CTX10_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX11IV0 - IPED context11 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX11IV0_CTX11_IV0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX11IV0_CTX11_IV0_SHIFT     (0U)
+/*! CTX11_IV0 - Lowest 32 bits of IV for region 11. */
+#define FLEXSPI_IPEDCTX11IV0_CTX11_IV0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11IV0_CTX11_IV0_SHIFT)) & FLEXSPI_IPEDCTX11IV0_CTX11_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX11IV1 - IPED context11 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX11IV1_CTX11_IV1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX11IV1_CTX11_IV1_SHIFT     (0U)
+/*! CTX11_IV1 - Highest 32 bits of IV for region 11. */
+#define FLEXSPI_IPEDCTX11IV1_CTX11_IV1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11IV1_CTX11_IV1_SHIFT)) & FLEXSPI_IPEDCTX11IV1_CTX11_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX11START - Start address of region 11 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX11START_GCM_MASK          (0x1U)
+#define FLEXSPI_IPEDCTX11START_GCM_SHIFT         (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX11START_GCM(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11START_GCM_SHIFT)) & FLEXSPI_IPEDCTX11START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX11START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX11START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX11START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX11START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX11START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX11START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 11. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX11START_START_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX11START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX11END - End address of region 11 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX11END_END_ADDRESS_MASK    (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX11END_END_ADDRESS_SHIFT   (8U)
+/*! END_ADDRESS - End address of region 11. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX11END_END_ADDRESS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX11END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX11AAD0 - IPED context11 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX11AAD0_CTX11_AAD0_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX11AAD0_CTX11_AAD0_SHIFT   (0U)
+/*! CTX11_AAD0 - Lowest 32 bits of AAD for region 11. */
+#define FLEXSPI_IPEDCTX11AAD0_CTX11_AAD0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11AAD0_CTX11_AAD0_SHIFT)) & FLEXSPI_IPEDCTX11AAD0_CTX11_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX11AAD1 - IPED context11 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX11AAD1_CTX11_AAD1_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX11AAD1_CTX11_AAD1_SHIFT   (0U)
+/*! CTX11_AAD1 - Highest 32 bits of AAD for region 11. */
+#define FLEXSPI_IPEDCTX11AAD1_CTX11_AAD1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX11AAD1_CTX11_AAD1_SHIFT)) & FLEXSPI_IPEDCTX11AAD1_CTX11_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX12IV0 - IPED context12 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX12IV0_CTX12_IV0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX12IV0_CTX12_IV0_SHIFT     (0U)
+/*! CTX12_IV0 - Lowest 32 bits of IV for region 12. */
+#define FLEXSPI_IPEDCTX12IV0_CTX12_IV0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12IV0_CTX12_IV0_SHIFT)) & FLEXSPI_IPEDCTX12IV0_CTX12_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX12IV1 - IPED context12 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX12IV1_CTX12_IV1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX12IV1_CTX12_IV1_SHIFT     (0U)
+/*! CTX12_IV1 - Highest 32 bits of IV for region 12. */
+#define FLEXSPI_IPEDCTX12IV1_CTX12_IV1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12IV1_CTX12_IV1_SHIFT)) & FLEXSPI_IPEDCTX12IV1_CTX12_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX12START - Start address of region 12 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX12START_GCM_MASK          (0x1U)
+#define FLEXSPI_IPEDCTX12START_GCM_SHIFT         (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX12START_GCM(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12START_GCM_SHIFT)) & FLEXSPI_IPEDCTX12START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX12START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX12START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX12START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX12START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX12START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX12START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 12. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX12START_START_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX12START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX12END - End address of region 12 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX12END_END_ADDRESS_MASK    (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX12END_END_ADDRESS_SHIFT   (8U)
+/*! END_ADDRESS - End address of region 12. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX12END_END_ADDRESS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX12END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX12AAD0 - IPED context12 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX12AAD0_CTX12_AAD0_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX12AAD0_CTX12_AAD0_SHIFT   (0U)
+/*! CTX12_AAD0 - Lowest 32 bits of AAD for region 12. */
+#define FLEXSPI_IPEDCTX12AAD0_CTX12_AAD0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12AAD0_CTX12_AAD0_SHIFT)) & FLEXSPI_IPEDCTX12AAD0_CTX12_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX12AAD1 - IPED context12 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX12AAD1_CTX12_AAD1_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX12AAD1_CTX12_AAD1_SHIFT   (0U)
+/*! CTX12_AAD1 - Highest 32 bits of AAD for region 12. */
+#define FLEXSPI_IPEDCTX12AAD1_CTX12_AAD1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX12AAD1_CTX12_AAD1_SHIFT)) & FLEXSPI_IPEDCTX12AAD1_CTX12_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX13IV0 - IPED context13 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX13IV0_CTX13_IV0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX13IV0_CTX13_IV0_SHIFT     (0U)
+/*! CTX13_IV0 - Lowest 32 bits of IV for region 13. */
+#define FLEXSPI_IPEDCTX13IV0_CTX13_IV0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13IV0_CTX13_IV0_SHIFT)) & FLEXSPI_IPEDCTX13IV0_CTX13_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX13IV1 - IPED context13 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX13IV1_CTX13_IV1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX13IV1_CTX13_IV1_SHIFT     (0U)
+/*! CTX13_IV1 - Highest 32 bits of IV for region 13. */
+#define FLEXSPI_IPEDCTX13IV1_CTX13_IV1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13IV1_CTX13_IV1_SHIFT)) & FLEXSPI_IPEDCTX13IV1_CTX13_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX13START - Start address of region 13 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX13START_GCM_MASK          (0x1U)
+#define FLEXSPI_IPEDCTX13START_GCM_SHIFT         (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX13START_GCM(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13START_GCM_SHIFT)) & FLEXSPI_IPEDCTX13START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX13START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX13START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX13START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX13START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX13START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX13START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 13. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX13START_START_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX13START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX13END - End address of region 13 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX13END_END_ADDRESS_MASK    (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX13END_END_ADDRESS_SHIFT   (8U)
+/*! END_ADDRESS - End address of region 13. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX13END_END_ADDRESS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX13END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX13AAD0 - IPED context13 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX13AAD0_CTX13_AAD0_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX13AAD0_CTX13_AAD0_SHIFT   (0U)
+/*! CTX13_AAD0 - Lowest 32 bits of AAD for region 13. */
+#define FLEXSPI_IPEDCTX13AAD0_CTX13_AAD0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13AAD0_CTX13_AAD0_SHIFT)) & FLEXSPI_IPEDCTX13AAD0_CTX13_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX13AAD1 - IPED context13 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX13AAD1_CTX13_AAD1_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX13AAD1_CTX13_AAD1_SHIFT   (0U)
+/*! CTX13_AAD1 - Highest 32 bits of AAD for region 13. */
+#define FLEXSPI_IPEDCTX13AAD1_CTX13_AAD1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX13AAD1_CTX13_AAD1_SHIFT)) & FLEXSPI_IPEDCTX13AAD1_CTX13_AAD1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX14IV0 - IPED context14 IV0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX14IV0_CTX14_IV0_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX14IV0_CTX14_IV0_SHIFT     (0U)
+/*! CTX14_IV0 - Lowest 32 bits of IV for region 14. */
+#define FLEXSPI_IPEDCTX14IV0_CTX14_IV0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14IV0_CTX14_IV0_SHIFT)) & FLEXSPI_IPEDCTX14IV0_CTX14_IV0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX14IV1 - IPED context14 IV1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX14IV1_CTX14_IV1_MASK      (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX14IV1_CTX14_IV1_SHIFT     (0U)
+/*! CTX14_IV1 - Highest 32 bits of IV for region 14. */
+#define FLEXSPI_IPEDCTX14IV1_CTX14_IV1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14IV1_CTX14_IV1_SHIFT)) & FLEXSPI_IPEDCTX14IV1_CTX14_IV1_MASK)
+/*! @} */
+
+/*! @name IPEDCTX14START - Start address of region 14 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX14START_GCM_MASK          (0x1U)
+#define FLEXSPI_IPEDCTX14START_GCM_SHIFT         (0U)
+/*! GCM - If this bit is 1, current region is GCM mode region. */
+#define FLEXSPI_IPEDCTX14START_GCM(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14START_GCM_SHIFT)) & FLEXSPI_IPEDCTX14START_GCM_MASK)
+
+#define FLEXSPI_IPEDCTX14START_AHBBUSERROR_DIS_MASK (0x2U)
+#define FLEXSPI_IPEDCTX14START_AHBBUSERROR_DIS_SHIFT (1U)
+/*! AHBBUSERROR_DIS - If this bit is 1, ahb bus error is disable. */
+#define FLEXSPI_IPEDCTX14START_AHBBUSERROR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14START_AHBBUSERROR_DIS_SHIFT)) & FLEXSPI_IPEDCTX14START_AHBBUSERROR_DIS_MASK)
+
+#define FLEXSPI_IPEDCTX14START_START_ADDRESS_MASK (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX14START_START_ADDRESS_SHIFT (8U)
+/*! START_ADDRESS - Start address of region 14. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX14START_START_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14START_START_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX14START_START_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX14END - End address of region 14 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX14END_END_ADDRESS_MASK    (0xFFFFFF00U)
+#define FLEXSPI_IPEDCTX14END_END_ADDRESS_SHIFT   (8U)
+/*! END_ADDRESS - End address of region 14. Minimal 256 Bytes aligned. It is system address. */
+#define FLEXSPI_IPEDCTX14END_END_ADDRESS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14END_END_ADDRESS_SHIFT)) & FLEXSPI_IPEDCTX14END_END_ADDRESS_MASK)
+/*! @} */
+
+/*! @name IPEDCTX14AAD0 - IPED context14 AAD0 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX14AAD0_CTX14_AAD0_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX14AAD0_CTX14_AAD0_SHIFT   (0U)
+/*! CTX14_AAD0 - Lowest 32 bits of AAD for region 14. */
+#define FLEXSPI_IPEDCTX14AAD0_CTX14_AAD0(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14AAD0_CTX14_AAD0_SHIFT)) & FLEXSPI_IPEDCTX14AAD0_CTX14_AAD0_MASK)
+/*! @} */
+
+/*! @name IPEDCTX14AAD1 - IPED context14 AAD1 */
+/*! @{ */
+
+#define FLEXSPI_IPEDCTX14AAD1_CTX14_AAD1_MASK    (0xFFFFFFFFU)
+#define FLEXSPI_IPEDCTX14AAD1_CTX14_AAD1_SHIFT   (0U)
+/*! CTX14_AAD1 - Highest 32 bits of AAD for region 14. */
+#define FLEXSPI_IPEDCTX14AAD1_CTX14_AAD1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX14AAD1_CTX14_AAD1_SHIFT)) & FLEXSPI_IPEDCTX14AAD1_CTX14_AAD1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXSPI_Register_Masks */
+
+
+/* FLEXSPI - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral FLEXSPI base address */
+  #define FLEXSPI_BASE                             (0x50134000u)
+  /** Peripheral FLEXSPI base address */
+  #define FLEXSPI_BASE_NS                          (0x40134000u)
+  /** Peripheral FLEXSPI base pointer */
+  #define FLEXSPI                                  ((FLEXSPI_Type *)FLEXSPI_BASE)
+  /** Peripheral FLEXSPI base pointer */
+  #define FLEXSPI_NS                               ((FLEXSPI_Type *)FLEXSPI_BASE_NS)
+  /** Array initializer of FLEXSPI peripheral base addresses */
+  #define FLEXSPI_BASE_ADDRS                       { FLEXSPI_BASE }
+  /** Array initializer of FLEXSPI peripheral base pointers */
+  #define FLEXSPI_BASE_PTRS                        { FLEXSPI }
+  /** Array initializer of FLEXSPI peripheral base addresses */
+  #define FLEXSPI_BASE_ADDRS_NS                    { FLEXSPI_BASE_NS }
+  /** Array initializer of FLEXSPI peripheral base pointers */
+  #define FLEXSPI_BASE_PTRS_NS                     { FLEXSPI_NS }
+#else
+  /** Peripheral FLEXSPI base address */
+  #define FLEXSPI_BASE                             (0x40134000u)
+  /** Peripheral FLEXSPI base pointer */
+  #define FLEXSPI                                  ((FLEXSPI_Type *)FLEXSPI_BASE)
+  /** Array initializer of FLEXSPI peripheral base addresses */
+  #define FLEXSPI_BASE_ADDRS                       { FLEXSPI_BASE }
+  /** Array initializer of FLEXSPI peripheral base pointers */
+  #define FLEXSPI_BASE_PTRS                        { FLEXSPI }
+#endif
+/** Interrupt vectors for the FLEXSPI peripheral type */
+#define FLEXSPI_IRQS                             { FLEXSPI_IRQn }
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+/** FlexSPI AMBA Cache0 address. */
+#define FlexSPI_AMBA_PC_CACHE_BASE                 (0x18000000u)
+/** FlexSPI AMBA Cache1 address. */
+#define FlexSPI_AMBA_PS_CACHE_BASE                 (0x38000000u)
+/** FlexSPI AMBA Non-Cache address. */
+#define FlexSPI_AMBA_PS_NCACHE_BASE                (0x58000000u)
+/** FlexSPI AMBA Cache0 address */
+#define FlexSPI_AMBA_PC_CACHE_BASE_NS              (0x08000000u)
+/** FlexSPI AMBA Cache1 address */
+#define FlexSPI_AMBA_PS_CACHE_BASE_NS              (0x28000000u)
+/** FlexSPI AMBA Non-Cache address */
+#define FlexSPI_AMBA_PS_NCACHE_BASE_NS             (0x48000000u)
+#else
+/** FlexSPI AMBA Cache0 address. */
+#define FlexSPI_AMBA_PC_CACHE_BASE                 (0x08000000u)
+/** FlexSPI AMBA Cache1 address. */
+#define FlexSPI_AMBA_PS_CACHE_BASE                 (0x28000000u)
+/** FlexSPI AMBA Non-cache address. */
+#define FlexSPI_AMBA_PS_NCACHE_BASE                (0x48000000u)
+#endif
+
+
+/*!
+ * @}
+ */ /* end of group FLEXSPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FREQME Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
+ * @{
+ */
+
+/** FREQME - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __I  uint32_t FREQMECTRL_R;                      /**< Frequency Measurement (in Read mode), offset: 0x0 */
+    __O  uint32_t FREQMECTRL_W;                      /**< Freqeuncy Measurement (in Write mode), offset: 0x0 */
+  };
+} FREQME_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FREQME Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FREQME_Register_Masks FREQME Register Masks
+ * @{
+ */
+
+/*! @name FREQMECTRL_R - Frequency Measurement (in Read mode) */
+/*! @{ */
+
+#define FREQME_FREQMECTRL_R_RESULT_MASK          (0x7FFFFFFFU)
+#define FREQME_FREQMECTRL_R_RESULT_SHIFT         (0U)
+/*! RESULT - Result */
+#define FREQME_FREQMECTRL_R_RESULT(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_RESULT_SHIFT)) & FREQME_FREQMECTRL_R_RESULT_MASK)
+
+#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U)
+#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U)
+/*! MEASURE_IN_PROGRESS - Measure in Progress
+ *  0b0..Process complete. Measurement cycle is complete. The results are ready in the RESULT field.
+ *  0b1..In Progress. Measurement cycle is in progress.
+ */
+#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK)
+/*! @} */
+
+/*! @name FREQMECTRL_W - Freqeuncy Measurement (in Write mode) */
+/*! @{ */
+
+#define FREQME_FREQMECTRL_W_REF_SCALE_MASK       (0x1FU)
+#define FREQME_FREQMECTRL_W_REF_SCALE_SHIFT      (0U)
+/*! REF_SCALE - Reference Clock Scaling Factor
+ *  0b00000..Count cycle = 2^0 = 1
+ *  0b00001..Count cycle = 2^1 = 2
+ *  0b00010..Count cycle = 2^4 = 4
+ *  0b11111..Count cycle = 2^31 = 2,147,483,648
+ */
+#define FREQME_FREQMECTRL_W_REF_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_REF_SCALE_SHIFT)) & FREQME_FREQMECTRL_W_REF_SCALE_MASK)
+
+#define FREQME_FREQMECTRL_W_PULSE_MODE_MASK      (0x100U)
+#define FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT     (8U)
+/*! PULSE_MODE - Pulse Width Measurement mode select
+ *  0b0..Frequency Measurement Mode. FREQMECTRL works in a Frequency Measurement mode. Once the measurement starts
+ *       (real count start is aligned at rising edge arrival on reference clock), the target counter increments by
+ *       the target clock until the reference counter running by the reference clock reaches the count end point
+ *       selected by REF_SCALE.
+ *  0b1..Pulse Width Measurement mode. FREQMECTRL works in a Pulse Width Measurement mode, measuring the high or
+ *       low period of reference clock input selected by PULSE_POL. The target counter starts incrementing by the
+ *       target clock once a corresponding trigger edge (rising edge for high period measurement and falling edge for
+ *       low period) occurs.
+ */
+#define FREQME_FREQMECTRL_W_PULSE_MODE(x)        (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_MODE_MASK)
+
+#define FREQME_FREQMECTRL_W_PULSE_POL_MASK       (0x200U)
+#define FREQME_FREQMECTRL_W_PULSE_POL_SHIFT      (9U)
+/*! PULSE_POL - Pulse Polarity
+ *  0b0..High Period. High period of reference clock is measured in Pulse Width Measurement mode triggered by the
+ *       rising edge on the reference clock input.
+ *  0b1..Low Period. Low period of reference clock is measured in Pulse Width Measurement mode triggered by the
+ *       falling edge on the reference clock input.
+ */
+#define FREQME_FREQMECTRL_W_PULSE_POL(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_POL_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_POL_MASK)
+
+#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U)
+#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U)
+/*! MEASURE_IN_PROGRESS - Measure in Progress
+ *  0b0..Force Terminate. Forces the termination of any measurement cycle currently in progress and resets RESULT or just resets RESULT if in idle.
+ *  0b1..Initiates Measurement Cycle. Initiates frequency or pulse width measurement process. Hardware clears the
+ *       MEASURE_IN_PROGRESS bit when the measurement cycle completes. A new measurement starts if there is an
+ *       active measurement in progress.
+ */
+#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FREQME_Register_Masks */
+
+
+/* FREQME - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral FREQME base address */
+  #define FREQME_BASE                              (0x5002F000u)
+  /** Peripheral FREQME base address */
+  #define FREQME_BASE_NS                           (0x4002F000u)
+  /** Peripheral FREQME base pointer */
+  #define FREQME                                   ((FREQME_Type *)FREQME_BASE)
+  /** Peripheral FREQME base pointer */
+  #define FREQME_NS                                ((FREQME_Type *)FREQME_BASE_NS)
+  /** Array initializer of FREQME peripheral base addresses */
+  #define FREQME_BASE_ADDRS                        { FREQME_BASE }
+  /** Array initializer of FREQME peripheral base pointers */
+  #define FREQME_BASE_PTRS                         { FREQME }
+  /** Array initializer of FREQME peripheral base addresses */
+  #define FREQME_BASE_ADDRS_NS                     { FREQME_BASE_NS }
+  /** Array initializer of FREQME peripheral base pointers */
+  #define FREQME_BASE_PTRS_NS                      { FREQME_NS }
+#else
+  /** Peripheral FREQME base address */
+  #define FREQME_BASE                              (0x4002F000u)
+  /** Peripheral FREQME base pointer */
+  #define FREQME                                   ((FREQME_Type *)FREQME_BASE)
+  /** Array initializer of FREQME peripheral base addresses */
+  #define FREQME_BASE_ADDRS                        { FREQME_BASE }
+  /** Array initializer of FREQME peripheral base pointers */
+  #define FREQME_BASE_PTRS                         { FREQME }
+#endif
+
+/*!
+ * @}
+ */ /* end of group FREQME_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GDMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GDMA_Peripheral_Access_Layer GDMA Peripheral Access Layer
+ * @{
+ */
+
+/** GDMA - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[64];
+  struct {                                         /* offset: 0x40, array step: 0x40 */
+    __IO uint32_t SADR;                              /**< DMA SOURCE ADDRESS REGISTERS, array offset: 0x40, array step: 0x40 */
+    __IO uint32_t DADR;                              /**< DMA DESTINATION ADDRESS REGISTERS, array offset: 0x44, array step: 0x40 */
+    __IO uint32_t LLI;                               /**< DMA CHANNEL LINKED LIST ITEM REGISTERS, array offset: 0x48, array step: 0x40 */
+    __IO uint32_t CTRL;                              /**< DMA CONTROL REGISTERS, array offset: 0x4C, array step: 0x40 */
+    __IO uint32_t CONFIG;                            /**< DMA CONFIGURE REGISTERS, array offset: 0x50, array step: 0x40 */
+    __IO uint32_t CHL_EN;                            /**< DMA CHANNEL ENABLE REGISTERS, array offset: 0x54, array step: 0x40 */
+    __IO uint32_t CHL_STOP;                          /**< DMA CHANNEL STOP REGISTERS, array offset: 0x58, array step: 0x40 */
+    __IO uint32_t CHNL_INT;                          /**< DMA INT REGISTERS, array offset: 0x5C, array step: 0x40 */
+         uint8_t RESERVED_0[16];
+    __IO uint32_t NUM_OF_DESCRIPTOR;                 /**< the number of descriptor, array offset: 0x70, array step: 0x40 */
+         uint8_t RESERVED_1[12];
+  } CH[4];
+} GDMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GDMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GDMA_Register_Masks GDMA Register Masks
+ * @{
+ */
+
+/*! @name SADR - DMA SOURCE ADDRESS REGISTERS */
+/*! @{ */
+
+#define GDMA_SADR_SRCADDR_MASK                   (0xFFFFFFFFU)
+#define GDMA_SADR_SRCADDR_SHIFT                  (0U)
+/*! SRCADDR - SOURCE ADDRESS */
+#define GDMA_SADR_SRCADDR(x)                     (((uint32_t)(((uint32_t)(x)) << GDMA_SADR_SRCADDR_SHIFT)) & GDMA_SADR_SRCADDR_MASK)
+/*! @} */
+
+/* The count of GDMA_SADR */
+#define GDMA_SADR_COUNT                          (4U)
+
+/*! @name DADR - DMA DESTINATION ADDRESS REGISTERS */
+/*! @{ */
+
+#define GDMA_DADR_DESTADDR_MASK                  (0xFFFFFFFFU)
+#define GDMA_DADR_DESTADDR_SHIFT                 (0U)
+/*! DESTADDR - DESTINATION ADDRESS */
+#define GDMA_DADR_DESTADDR(x)                    (((uint32_t)(((uint32_t)(x)) << GDMA_DADR_DESTADDR_SHIFT)) & GDMA_DADR_DESTADDR_MASK)
+/*! @} */
+
+/* The count of GDMA_DADR */
+#define GDMA_DADR_COUNT                          (4U)
+
+/*! @name LLI - DMA CHANNEL LINKED LIST ITEM REGISTERS */
+/*! @{ */
+
+#define GDMA_LLI_STOP_MASK                       (0x1U)
+#define GDMA_LLI_STOP_SHIFT                      (0U)
+/*! STOP - STOP the channel after transaction is finished */
+#define GDMA_LLI_STOP(x)                         (((uint32_t)(((uint32_t)(x)) << GDMA_LLI_STOP_SHIFT)) & GDMA_LLI_STOP_MASK)
+
+#define GDMA_LLI_DESC_INT_EN_MASK                (0x2U)
+#define GDMA_LLI_DESC_INT_EN_SHIFT               (1U)
+/*! DESC_INT_EN - the interrupt enable for descriptor finish */
+#define GDMA_LLI_DESC_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << GDMA_LLI_DESC_INT_EN_SHIFT)) & GDMA_LLI_DESC_INT_EN_MASK)
+
+#define GDMA_LLI_LLI_MASK                        (0xFFFFFFF0U)
+#define GDMA_LLI_LLI_SHIFT                       (4U)
+/*! LLI - LINKED LIST ITEM ADDRESS */
+#define GDMA_LLI_LLI(x)                          (((uint32_t)(((uint32_t)(x)) << GDMA_LLI_LLI_SHIFT)) & GDMA_LLI_LLI_MASK)
+/*! @} */
+
+/* The count of GDMA_LLI */
+#define GDMA_LLI_COUNT                           (4U)
+
+/*! @name CTRL - DMA CONTROL REGISTERS */
+/*! @{ */
+
+#define GDMA_CTRL_LEN_MASK                       (0x1FFFU)
+#define GDMA_CTRL_LEN_SHIFT                      (0U)
+/*! LEN - Length of the transfer in bytes */
+#define GDMA_CTRL_LEN(x)                         (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_LEN_SHIFT)) & GDMA_CTRL_LEN_MASK)
+
+#define GDMA_CTRL_DESTBSIZE_MASK                 (0xE0000U)
+#define GDMA_CTRL_DESTBSIZE_SHIFT                (17U)
+/*! DESTBSIZE - Destination peripheral/memory transfer burst size */
+#define GDMA_CTRL_DESTBSIZE(x)                   (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_DESTBSIZE_SHIFT)) & GDMA_CTRL_DESTBSIZE_MASK)
+
+#define GDMA_CTRL_SRCBSIZE_MASK                  (0x700000U)
+#define GDMA_CTRL_SRCBSIZE_SHIFT                 (20U)
+/*! SRCBSIZE - Source peripheral/memory transfer burst size */
+#define GDMA_CTRL_SRCBSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_SRCBSIZE_SHIFT)) & GDMA_CTRL_SRCBSIZE_MASK)
+
+#define GDMA_CTRL_DESTWIDTH_MASK                 (0x1800000U)
+#define GDMA_CTRL_DESTWIDTH_SHIFT                (23U)
+/*! DESTWIDTH - Destination peripheral/memory transfer width */
+#define GDMA_CTRL_DESTWIDTH(x)                   (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_DESTWIDTH_SHIFT)) & GDMA_CTRL_DESTWIDTH_MASK)
+
+#define GDMA_CTRL_SRCWIDTH_MASK                  (0x6000000U)
+#define GDMA_CTRL_SRCWIDTH_SHIFT                 (25U)
+/*! SRCWIDTH - Source peripheral/memory transfer width */
+#define GDMA_CTRL_SRCWIDTH(x)                    (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_SRCWIDTH_SHIFT)) & GDMA_CTRL_SRCWIDTH_MASK)
+
+#define GDMA_CTRL_DESTADDRINC_MASK               (0x8000000U)
+#define GDMA_CTRL_DESTADDRINC_SHIFT              (27U)
+/*! DESTADDRINC - destination address increment */
+#define GDMA_CTRL_DESTADDRINC(x)                 (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_DESTADDRINC_SHIFT)) & GDMA_CTRL_DESTADDRINC_MASK)
+
+#define GDMA_CTRL_SRCADDRINC_MASK                (0x10000000U)
+#define GDMA_CTRL_SRCADDRINC_SHIFT               (28U)
+/*! SRCADDRINC - Source address increment */
+#define GDMA_CTRL_SRCADDRINC(x)                  (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_SRCADDRINC_SHIFT)) & GDMA_CTRL_SRCADDRINC_MASK)
+
+#define GDMA_CTRL_PROT_MASK                      (0xE0000000U)
+#define GDMA_CTRL_PROT_SHIFT                     (29U)
+/*! PROT - Protection info for AHB master bus */
+#define GDMA_CTRL_PROT(x)                        (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_PROT_SHIFT)) & GDMA_CTRL_PROT_MASK)
+/*! @} */
+
+/* The count of GDMA_CTRL */
+#define GDMA_CTRL_COUNT                          (4U)
+
+/*! @name CONFIG - DMA CONFIGURE REGISTERS */
+/*! @{ */
+
+#define GDMA_CONFIG_LLE_MASK                     (0x1U)
+#define GDMA_CONFIG_LLE_SHIFT                    (0U)
+/*! LLE - Link List Enable */
+#define GDMA_CONFIG_LLE(x)                       (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_LLE_SHIFT)) & GDMA_CONFIG_LLE_MASK)
+
+#define GDMA_CONFIG_HW_EN_SRC_MASK               (0x38000000U)
+#define GDMA_CONFIG_HW_EN_SRC_SHIFT              (27U)
+/*! HW_EN_SRC - hardware enable trigger source */
+#define GDMA_CONFIG_HW_EN_SRC(x)                 (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_HW_EN_SRC_SHIFT)) & GDMA_CONFIG_HW_EN_SRC_MASK)
+
+#define GDMA_CONFIG_HW_EN_MASK                   (0x40000000U)
+#define GDMA_CONFIG_HW_EN_SHIFT                  (30U)
+/*! HW_EN - Hardware enable configuration of current channel */
+#define GDMA_CONFIG_HW_EN(x)                     (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_HW_EN_SHIFT)) & GDMA_CONFIG_HW_EN_MASK)
+
+#define GDMA_CONFIG_FIFO_EMPTY_MASK              (0x80000000U)
+#define GDMA_CONFIG_FIFO_EMPTY_SHIFT             (31U)
+/*! FIFO_EMPTY - FIFO status of current channel */
+#define GDMA_CONFIG_FIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_FIFO_EMPTY_SHIFT)) & GDMA_CONFIG_FIFO_EMPTY_MASK)
+/*! @} */
+
+/* The count of GDMA_CONFIG */
+#define GDMA_CONFIG_COUNT                        (4U)
+
+/*! @name CHL_EN - DMA CHANNEL ENABLE REGISTERS */
+/*! @{ */
+
+#define GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_MASK     (0xFU)
+#define GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_SHIFT    (0U)
+/*! CHL_PRIORITY_WEIGHT - DMA Channel Priority Weight */
+#define GDMA_CHL_EN_CHL_PRIORITY_WEIGHT(x)       (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_SHIFT)) & GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_MASK)
+
+#define GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_MASK     (0xF0U)
+#define GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_SHIFT    (4U)
+/*! TEST_BUS_SIGNAL_SEL - TEST_BUS_SIGNAL_SEL */
+#define GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL(x)       (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_SHIFT)) & GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_MASK)
+
+#define GDMA_CHL_EN_CHL_EN_MASK                  (0x80000000U)
+#define GDMA_CHL_EN_CHL_EN_SHIFT                 (31U)
+/*! CHL_EN - Enable/Disable the channel */
+#define GDMA_CHL_EN_CHL_EN(x)                    (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_EN_CHL_EN_SHIFT)) & GDMA_CHL_EN_CHL_EN_MASK)
+/*! @} */
+
+/* The count of GDMA_CHL_EN */
+#define GDMA_CHL_EN_COUNT                        (4U)
+
+/*! @name CHL_STOP - DMA CHANNEL STOP REGISTERS */
+/*! @{ */
+
+#define GDMA_CHL_STOP_CHL_STOP_MASK              (0x80000000U)
+#define GDMA_CHL_STOP_CHL_STOP_SHIFT             (31U)
+/*! CHL_STOP - Stop the running channel */
+#define GDMA_CHL_STOP_CHL_STOP(x)                (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_STOP_CHL_STOP_SHIFT)) & GDMA_CHL_STOP_CHL_STOP_MASK)
+/*! @} */
+
+/* The count of GDMA_CHL_STOP */
+#define GDMA_CHL_STOP_COUNT                      (4U)
+
+/*! @name CHNL_INT - DMA INT REGISTERS */
+/*! @{ */
+
+#define GDMA_CHNL_INT_MASK_BLOCKINT_MASK         (0x1U)
+#define GDMA_CHNL_INT_MASK_BLOCKINT_SHIFT        (0U)
+/*! MASK_BLOCKINT - DMA channel block transfer interrupt mask bit */
+#define GDMA_CHNL_INT_MASK_BLOCKINT(x)           (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_BLOCKINT_SHIFT)) & GDMA_CHNL_INT_MASK_BLOCKINT_MASK)
+
+#define GDMA_CHNL_INT_STATUS_BLOCKINT_MASK       (0x2U)
+#define GDMA_CHNL_INT_STATUS_BLOCKINT_SHIFT      (1U)
+/*! STATUS_BLOCKINT - DMA channel block transfer interrupt bit */
+#define GDMA_CHNL_INT_STATUS_BLOCKINT(x)         (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_BLOCKINT_SHIFT)) & GDMA_CHNL_INT_STATUS_BLOCKINT_MASK)
+
+#define GDMA_CHNL_INT_MASK_TFRINT_MASK           (0x4U)
+#define GDMA_CHNL_INT_MASK_TFRINT_SHIFT          (2U)
+/*! MASK_TFRINT - transfer interrupt mask bit */
+#define GDMA_CHNL_INT_MASK_TFRINT(x)             (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_TFRINT_SHIFT)) & GDMA_CHNL_INT_MASK_TFRINT_MASK)
+
+#define GDMA_CHNL_INT_STATUS_TFRINT_MASK         (0x8U)
+#define GDMA_CHNL_INT_STATUS_TFRINT_SHIFT        (3U)
+/*! STATUS_TFRINT - transfer interrupt bit */
+#define GDMA_CHNL_INT_STATUS_TFRINT(x)           (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_TFRINT_SHIFT)) & GDMA_CHNL_INT_STATUS_TFRINT_MASK)
+
+#define GDMA_CHNL_INT_MASK_BUSERRINT_MASK        (0x10U)
+#define GDMA_CHNL_INT_MASK_BUSERRINT_SHIFT       (4U)
+/*! MASK_BUSERRINT - DMA channel bus error interrupt mask bit */
+#define GDMA_CHNL_INT_MASK_BUSERRINT(x)          (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_BUSERRINT_SHIFT)) & GDMA_CHNL_INT_MASK_BUSERRINT_MASK)
+
+#define GDMA_CHNL_INT_STATUS_BUSERRINT_MASK      (0x20U)
+#define GDMA_CHNL_INT_STATUS_BUSERRINT_SHIFT     (5U)
+/*! STATUS_BUSERRINT - DMA channel bus error interrupt bit */
+#define GDMA_CHNL_INT_STATUS_BUSERRINT(x)        (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_BUSERRINT_SHIFT)) & GDMA_CHNL_INT_STATUS_BUSERRINT_MASK)
+
+#define GDMA_CHNL_INT_MASK_ADDRERRINT_MASK       (0x40U)
+#define GDMA_CHNL_INT_MASK_ADDRERRINT_SHIFT      (6U)
+/*! MASK_ADDRERRINT - DMA Channel source/destination address alignment error interrupt mask bit */
+#define GDMA_CHNL_INT_MASK_ADDRERRINT(x)         (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_ADDRERRINT_SHIFT)) & GDMA_CHNL_INT_MASK_ADDRERRINT_MASK)
+
+#define GDMA_CHNL_INT_STATUS_ADDRERRINT_MASK     (0x80U)
+#define GDMA_CHNL_INT_STATUS_ADDRERRINT_SHIFT    (7U)
+/*! STATUS_ADDRERRINT - DMA Channel source/destination address alignment error interrupt bit */
+#define GDMA_CHNL_INT_STATUS_ADDRERRINT(x)       (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_ADDRERRINT_SHIFT)) & GDMA_CHNL_INT_STATUS_ADDRERRINT_MASK)
+
+#define GDMA_CHNL_INT_STATUS_CHLINT_MASK         (0x100U)
+#define GDMA_CHNL_INT_STATUS_CHLINT_SHIFT        (8U)
+/*! STATUS_CHLINT - DMA channel interrupt */
+#define GDMA_CHNL_INT_STATUS_CHLINT(x)           (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_CHLINT_SHIFT)) & GDMA_CHNL_INT_STATUS_CHLINT_MASK)
+
+#define GDMA_CHNL_INT_MASK_DESC_TFRINT_MASK      (0x200U)
+#define GDMA_CHNL_INT_MASK_DESC_TFRINT_SHIFT     (9U)
+/*! MASK_DESC_TFRINT - descriptor transfer interrupt mask bit */
+#define GDMA_CHNL_INT_MASK_DESC_TFRINT(x)        (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_DESC_TFRINT_SHIFT)) & GDMA_CHNL_INT_MASK_DESC_TFRINT_MASK)
+
+#define GDMA_CHNL_INT_DESC_STATUS_TFRINT_MASK    (0x400U)
+#define GDMA_CHNL_INT_DESC_STATUS_TFRINT_SHIFT   (10U)
+/*! DESC_STATUS_TFRINT - configurable descriptor transfer interrupt bit */
+#define GDMA_CHNL_INT_DESC_STATUS_TFRINT(x)      (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_DESC_STATUS_TFRINT_SHIFT)) & GDMA_CHNL_INT_DESC_STATUS_TFRINT_MASK)
+/*! @} */
+
+/* The count of GDMA_CHNL_INT */
+#define GDMA_CHNL_INT_COUNT                      (4U)
+
+/*! @name NUM_OF_DESCRIPTOR - the number of descriptor */
+/*! @{ */
+
+#define GDMA_NUM_OF_DESCRIPTOR_DATA_MASK         (0xFFFFFFFFU)
+#define GDMA_NUM_OF_DESCRIPTOR_DATA_SHIFT        (0U)
+/*! DATA - the number of descriptor */
+#define GDMA_NUM_OF_DESCRIPTOR_DATA(x)           (((uint32_t)(((uint32_t)(x)) << GDMA_NUM_OF_DESCRIPTOR_DATA_SHIFT)) & GDMA_NUM_OF_DESCRIPTOR_DATA_MASK)
+/*! @} */
+
+/* The count of GDMA_NUM_OF_DESCRIPTOR */
+#define GDMA_NUM_OF_DESCRIPTOR_COUNT             (4U)
+
+
+/*!
+ * @}
+ */ /* end of group GDMA_Register_Masks */
+
+
+/* GDMA - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral GDMA base address */
+  #define GDMA_BASE                                (0x5014E000u)
+  /** Peripheral GDMA base address */
+  #define GDMA_BASE_NS                             (0x4014E000u)
+  /** Peripheral GDMA base pointer */
+  #define GDMA                                     ((GDMA_Type *)GDMA_BASE)
+  /** Peripheral GDMA base pointer */
+  #define GDMA_NS                                  ((GDMA_Type *)GDMA_BASE_NS)
+  /** Array initializer of GDMA peripheral base addresses */
+  #define GDMA_BASE_ADDRS                          { GDMA_BASE }
+  /** Array initializer of GDMA peripheral base pointers */
+  #define GDMA_BASE_PTRS                           { GDMA }
+  /** Array initializer of GDMA peripheral base addresses */
+  #define GDMA_BASE_ADDRS_NS                       { GDMA_BASE_NS }
+  /** Array initializer of GDMA peripheral base pointers */
+  #define GDMA_BASE_PTRS_NS                        { GDMA_NS }
+#else
+  /** Peripheral GDMA base address */
+  #define GDMA_BASE                                (0x4014E000u)
+  /** Peripheral GDMA base pointer */
+  #define GDMA                                     ((GDMA_Type *)GDMA_BASE)
+  /** Array initializer of GDMA peripheral base addresses */
+  #define GDMA_BASE_ADDRS                          { GDMA_BASE }
+  /** Array initializer of GDMA peripheral base pointers */
+  #define GDMA_BASE_PTRS                           { GDMA }
+#endif
+/** Interrupt vectors for the GDMA peripheral type */
+#define GDMA_IRQS                                { GDMA_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GDMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t B[2][32];                           /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1, irregular array, not all indices are valid */
+       uint8_t RESERVED_0[4032];
+  __IO uint32_t W[2][32];                          /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_1[3840];
+  __O  uint32_t DIR[2];                            /**< Port direction, array offset: 0x2000, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_2[120];
+  __IO uint32_t MASK[2];                           /**< Port mask, array offset: 0x2080, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_3[120];
+  __IO uint32_t PIN[2];                            /**< Port pin, array offset: 0x2100, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_4[120];
+  __IO uint32_t MPIN[2];                           /**< Masked Port Pin, array offset: 0x2180, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_5[120];
+  __IO uint32_t SET[2];                            /**< Port set, array offset: 0x2200, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_6[120];
+  __IO uint32_t CLR[2];                            /**< Port clear, array offset: 0x2280, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_7[120];
+  __O  uint32_t NOT[2];                            /**< Port toggle, array offset: 0x2300, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_8[120];
+  __O  uint32_t DIRSET[2];                         /**< Port direction set, array offset: 0x2380, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_9[120];
+  __IO uint32_t DIRCLR[2];                         /**< Port direction clear, array offset: 0x2400, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_10[120];
+  __O  uint32_t DIRNOT[2];                         /**< Port direction toggle, array offset: 0x2480, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_11[120];
+  __IO uint32_t INTENA[2];                         /**< Interrupt A enable control, array offset: 0x2500, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_12[120];
+  __IO uint32_t INTENB[2];                         /**< Interrupt B enable control, array offset: 0x2580, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_13[120];
+  __IO uint32_t INTPOL[2];                         /**< Interupt polarity control, array offset: 0x2600, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_14[120];
+  __IO uint32_t INTEDG[2];                         /**< Interrupt edge select, array offset: 0x2680, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_15[120];
+  __IO uint32_t INTSTATA[2];                       /**< Interrupt status for interrupt A, array offset: 0x2700, array step: 0x4, irregular array, not all indices are valid */
+       uint8_t RESERVED_16[120];
+  __IO uint32_t INTSTATB[2];                       /**< Interrupt status for interrupt B, array offset: 0x2780, array step: 0x4, irregular array, not all indices are valid */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port GPIO pins */
+/*! @{ */
+
+#define GPIO_B_PBYTE_MASK                        (0x1U)
+#define GPIO_B_PBYTE_SHIFT                       (0U)
+/*! PBYTE - Port Byte */
+#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+/*! @} */
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT                             (2U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2                            (32U)
+
+/*! @name W - Word pin registers for all port GPIO pins */
+/*! @{ */
+
+#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT                       (0U)
+/*! PWORD - PWORD */
+#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+/*! @} */
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT                             (2U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2                            (32U)
+
+/*! @name DIR - Port direction */
+/*! @{ */
+
+#define GPIO_DIR_DIRP0_MASK                      (0x1U)
+#define GPIO_DIR_DIRP0_SHIFT                     (0U)
+/*! DIRP0 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP0_SHIFT)) & GPIO_DIR_DIRP0_MASK)
+
+#define GPIO_DIR_DIRP1_MASK                      (0x2U)
+#define GPIO_DIR_DIRP1_SHIFT                     (1U)
+/*! DIRP1 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP1_SHIFT)) & GPIO_DIR_DIRP1_MASK)
+
+#define GPIO_DIR_DIRP2_MASK                      (0x4U)
+#define GPIO_DIR_DIRP2_SHIFT                     (2U)
+/*! DIRP2 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP2_SHIFT)) & GPIO_DIR_DIRP2_MASK)
+
+#define GPIO_DIR_DIRP3_MASK                      (0x8U)
+#define GPIO_DIR_DIRP3_SHIFT                     (3U)
+/*! DIRP3 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP3_SHIFT)) & GPIO_DIR_DIRP3_MASK)
+
+#define GPIO_DIR_DIRP4_MASK                      (0x10U)
+#define GPIO_DIR_DIRP4_SHIFT                     (4U)
+/*! DIRP4 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP4_SHIFT)) & GPIO_DIR_DIRP4_MASK)
+
+#define GPIO_DIR_DIRP5_MASK                      (0x20U)
+#define GPIO_DIR_DIRP5_SHIFT                     (5U)
+/*! DIRP5 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP5_SHIFT)) & GPIO_DIR_DIRP5_MASK)
+
+#define GPIO_DIR_DIRP6_MASK                      (0x40U)
+#define GPIO_DIR_DIRP6_SHIFT                     (6U)
+/*! DIRP6 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP6_SHIFT)) & GPIO_DIR_DIRP6_MASK)
+
+#define GPIO_DIR_DIRP7_MASK                      (0x80U)
+#define GPIO_DIR_DIRP7_SHIFT                     (7U)
+/*! DIRP7 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP7_SHIFT)) & GPIO_DIR_DIRP7_MASK)
+
+#define GPIO_DIR_DIRP8_MASK                      (0x100U)
+#define GPIO_DIR_DIRP8_SHIFT                     (8U)
+/*! DIRP8 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP8_SHIFT)) & GPIO_DIR_DIRP8_MASK)
+
+#define GPIO_DIR_DIRP9_MASK                      (0x200U)
+#define GPIO_DIR_DIRP9_SHIFT                     (9U)
+/*! DIRP9 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP9_SHIFT)) & GPIO_DIR_DIRP9_MASK)
+
+#define GPIO_DIR_DIRP10_MASK                     (0x400U)
+#define GPIO_DIR_DIRP10_SHIFT                    (10U)
+/*! DIRP10 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP10_SHIFT)) & GPIO_DIR_DIRP10_MASK)
+
+#define GPIO_DIR_DIRP11_MASK                     (0x800U)
+#define GPIO_DIR_DIRP11_SHIFT                    (11U)
+/*! DIRP11 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP11_SHIFT)) & GPIO_DIR_DIRP11_MASK)
+
+#define GPIO_DIR_DIRP12_MASK                     (0x1000U)
+#define GPIO_DIR_DIRP12_SHIFT                    (12U)
+/*! DIRP12 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP12_SHIFT)) & GPIO_DIR_DIRP12_MASK)
+
+#define GPIO_DIR_DIRP13_MASK                     (0x2000U)
+#define GPIO_DIR_DIRP13_SHIFT                    (13U)
+/*! DIRP13 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP13_SHIFT)) & GPIO_DIR_DIRP13_MASK)
+
+#define GPIO_DIR_DIRP14_MASK                     (0x4000U)
+#define GPIO_DIR_DIRP14_SHIFT                    (14U)
+/*! DIRP14 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP14_SHIFT)) & GPIO_DIR_DIRP14_MASK)
+
+#define GPIO_DIR_DIRP15_MASK                     (0x8000U)
+#define GPIO_DIR_DIRP15_SHIFT                    (15U)
+/*! DIRP15 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP15_SHIFT)) & GPIO_DIR_DIRP15_MASK)
+
+#define GPIO_DIR_DIRP16_MASK                     (0x10000U)
+#define GPIO_DIR_DIRP16_SHIFT                    (16U)
+/*! DIRP16 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP16_SHIFT)) & GPIO_DIR_DIRP16_MASK)
+
+#define GPIO_DIR_DIRP17_MASK                     (0x20000U)
+#define GPIO_DIR_DIRP17_SHIFT                    (17U)
+/*! DIRP17 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP17_SHIFT)) & GPIO_DIR_DIRP17_MASK)
+
+#define GPIO_DIR_DIRP18_MASK                     (0x40000U)
+#define GPIO_DIR_DIRP18_SHIFT                    (18U)
+/*! DIRP18 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP18_SHIFT)) & GPIO_DIR_DIRP18_MASK)
+
+#define GPIO_DIR_DIRP19_MASK                     (0x80000U)
+#define GPIO_DIR_DIRP19_SHIFT                    (19U)
+/*! DIRP19 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP19_SHIFT)) & GPIO_DIR_DIRP19_MASK)
+
+#define GPIO_DIR_DIRP20_MASK                     (0x100000U)
+#define GPIO_DIR_DIRP20_SHIFT                    (20U)
+/*! DIRP20 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP20_SHIFT)) & GPIO_DIR_DIRP20_MASK)
+
+#define GPIO_DIR_DIRP21_MASK                     (0x200000U)
+#define GPIO_DIR_DIRP21_SHIFT                    (21U)
+/*! DIRP21 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP21_SHIFT)) & GPIO_DIR_DIRP21_MASK)
+
+#define GPIO_DIR_DIRP22_MASK                     (0x400000U)
+#define GPIO_DIR_DIRP22_SHIFT                    (22U)
+/*! DIRP22 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP22_SHIFT)) & GPIO_DIR_DIRP22_MASK)
+
+#define GPIO_DIR_DIRP23_MASK                     (0x800000U)
+#define GPIO_DIR_DIRP23_SHIFT                    (23U)
+/*! DIRP23 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP23_SHIFT)) & GPIO_DIR_DIRP23_MASK)
+
+#define GPIO_DIR_DIRP24_MASK                     (0x1000000U)
+#define GPIO_DIR_DIRP24_SHIFT                    (24U)
+/*! DIRP24 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP24_SHIFT)) & GPIO_DIR_DIRP24_MASK)
+
+#define GPIO_DIR_DIRP25_MASK                     (0x2000000U)
+#define GPIO_DIR_DIRP25_SHIFT                    (25U)
+/*! DIRP25 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP25_SHIFT)) & GPIO_DIR_DIRP25_MASK)
+
+#define GPIO_DIR_DIRP26_MASK                     (0x4000000U)
+#define GPIO_DIR_DIRP26_SHIFT                    (26U)
+/*! DIRP26 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP26_SHIFT)) & GPIO_DIR_DIRP26_MASK)
+
+#define GPIO_DIR_DIRP27_MASK                     (0x8000000U)
+#define GPIO_DIR_DIRP27_SHIFT                    (27U)
+/*! DIRP27 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP27_SHIFT)) & GPIO_DIR_DIRP27_MASK)
+
+#define GPIO_DIR_DIRP28_MASK                     (0x10000000U)
+#define GPIO_DIR_DIRP28_SHIFT                    (28U)
+/*! DIRP28 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP28_SHIFT)) & GPIO_DIR_DIRP28_MASK)
+
+#define GPIO_DIR_DIRP29_MASK                     (0x20000000U)
+#define GPIO_DIR_DIRP29_SHIFT                    (29U)
+/*! DIRP29 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP29_SHIFT)) & GPIO_DIR_DIRP29_MASK)
+
+#define GPIO_DIR_DIRP30_MASK                     (0x40000000U)
+#define GPIO_DIR_DIRP30_SHIFT                    (30U)
+/*! DIRP30 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP30_SHIFT)) & GPIO_DIR_DIRP30_MASK)
+
+#define GPIO_DIR_DIRP31_MASK                     (0x80000000U)
+#define GPIO_DIR_DIRP31_SHIFT                    (31U)
+/*! DIRP31 - Selects pin direction for pin PIOa_b.
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_DIR_DIRP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP31_SHIFT)) & GPIO_DIR_DIRP31_MASK)
+/*! @} */
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT                           (2U)
+
+/*! @name MASK - Port mask */
+/*! @{ */
+
+#define GPIO_MASK_MASKP0_MASK                    (0x1U)
+#define GPIO_MASK_MASKP0_SHIFT                   (0U)
+/*! MASKP0 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP0(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP0_SHIFT)) & GPIO_MASK_MASKP0_MASK)
+
+#define GPIO_MASK_MASKP1_MASK                    (0x2U)
+#define GPIO_MASK_MASKP1_SHIFT                   (1U)
+/*! MASKP1 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP1(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP1_SHIFT)) & GPIO_MASK_MASKP1_MASK)
+
+#define GPIO_MASK_MASKP2_MASK                    (0x4U)
+#define GPIO_MASK_MASKP2_SHIFT                   (2U)
+/*! MASKP2 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP2(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP2_SHIFT)) & GPIO_MASK_MASKP2_MASK)
+
+#define GPIO_MASK_MASKP3_MASK                    (0x8U)
+#define GPIO_MASK_MASKP3_SHIFT                   (3U)
+/*! MASKP3 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP3(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP3_SHIFT)) & GPIO_MASK_MASKP3_MASK)
+
+#define GPIO_MASK_MASKP4_MASK                    (0x10U)
+#define GPIO_MASK_MASKP4_SHIFT                   (4U)
+/*! MASKP4 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP4(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP4_SHIFT)) & GPIO_MASK_MASKP4_MASK)
+
+#define GPIO_MASK_MASKP5_MASK                    (0x20U)
+#define GPIO_MASK_MASKP5_SHIFT                   (5U)
+/*! MASKP5 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP5(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP5_SHIFT)) & GPIO_MASK_MASKP5_MASK)
+
+#define GPIO_MASK_MASKP6_MASK                    (0x40U)
+#define GPIO_MASK_MASKP6_SHIFT                   (6U)
+/*! MASKP6 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP6(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP6_SHIFT)) & GPIO_MASK_MASKP6_MASK)
+
+#define GPIO_MASK_MASKP7_MASK                    (0x80U)
+#define GPIO_MASK_MASKP7_SHIFT                   (7U)
+/*! MASKP7 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP7(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP7_SHIFT)) & GPIO_MASK_MASKP7_MASK)
+
+#define GPIO_MASK_MASKP8_MASK                    (0x100U)
+#define GPIO_MASK_MASKP8_SHIFT                   (8U)
+/*! MASKP8 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP8(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP8_SHIFT)) & GPIO_MASK_MASKP8_MASK)
+
+#define GPIO_MASK_MASKP9_MASK                    (0x200U)
+#define GPIO_MASK_MASKP9_SHIFT                   (9U)
+/*! MASKP9 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP9(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP9_SHIFT)) & GPIO_MASK_MASKP9_MASK)
+
+#define GPIO_MASK_MASKP10_MASK                   (0x400U)
+#define GPIO_MASK_MASKP10_SHIFT                  (10U)
+/*! MASKP10 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP10(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP10_SHIFT)) & GPIO_MASK_MASKP10_MASK)
+
+#define GPIO_MASK_MASKP11_MASK                   (0x800U)
+#define GPIO_MASK_MASKP11_SHIFT                  (11U)
+/*! MASKP11 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP11(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP11_SHIFT)) & GPIO_MASK_MASKP11_MASK)
+
+#define GPIO_MASK_MASKP12_MASK                   (0x1000U)
+#define GPIO_MASK_MASKP12_SHIFT                  (12U)
+/*! MASKP12 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP12(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP12_SHIFT)) & GPIO_MASK_MASKP12_MASK)
+
+#define GPIO_MASK_MASKP13_MASK                   (0x2000U)
+#define GPIO_MASK_MASKP13_SHIFT                  (13U)
+/*! MASKP13 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP13(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP13_SHIFT)) & GPIO_MASK_MASKP13_MASK)
+
+#define GPIO_MASK_MASKP14_MASK                   (0x4000U)
+#define GPIO_MASK_MASKP14_SHIFT                  (14U)
+/*! MASKP14 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP14(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP14_SHIFT)) & GPIO_MASK_MASKP14_MASK)
+
+#define GPIO_MASK_MASKP15_MASK                   (0x8000U)
+#define GPIO_MASK_MASKP15_SHIFT                  (15U)
+/*! MASKP15 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP15(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP15_SHIFT)) & GPIO_MASK_MASKP15_MASK)
+
+#define GPIO_MASK_MASKP16_MASK                   (0x10000U)
+#define GPIO_MASK_MASKP16_SHIFT                  (16U)
+/*! MASKP16 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP16(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP16_SHIFT)) & GPIO_MASK_MASKP16_MASK)
+
+#define GPIO_MASK_MASKP17_MASK                   (0x20000U)
+#define GPIO_MASK_MASKP17_SHIFT                  (17U)
+/*! MASKP17 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP17(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP17_SHIFT)) & GPIO_MASK_MASKP17_MASK)
+
+#define GPIO_MASK_MASKP18_MASK                   (0x40000U)
+#define GPIO_MASK_MASKP18_SHIFT                  (18U)
+/*! MASKP18 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP18(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP18_SHIFT)) & GPIO_MASK_MASKP18_MASK)
+
+#define GPIO_MASK_MASKP19_MASK                   (0x80000U)
+#define GPIO_MASK_MASKP19_SHIFT                  (19U)
+/*! MASKP19 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP19(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP19_SHIFT)) & GPIO_MASK_MASKP19_MASK)
+
+#define GPIO_MASK_MASKP20_MASK                   (0x100000U)
+#define GPIO_MASK_MASKP20_SHIFT                  (20U)
+/*! MASKP20 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP20(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP20_SHIFT)) & GPIO_MASK_MASKP20_MASK)
+
+#define GPIO_MASK_MASKP21_MASK                   (0x200000U)
+#define GPIO_MASK_MASKP21_SHIFT                  (21U)
+/*! MASKP21 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP21(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP21_SHIFT)) & GPIO_MASK_MASKP21_MASK)
+
+#define GPIO_MASK_MASKP22_MASK                   (0x400000U)
+#define GPIO_MASK_MASKP22_SHIFT                  (22U)
+/*! MASKP22 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP22(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP22_SHIFT)) & GPIO_MASK_MASKP22_MASK)
+
+#define GPIO_MASK_MASKP23_MASK                   (0x800000U)
+#define GPIO_MASK_MASKP23_SHIFT                  (23U)
+/*! MASKP23 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP23(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP23_SHIFT)) & GPIO_MASK_MASKP23_MASK)
+
+#define GPIO_MASK_MASKP24_MASK                   (0x1000000U)
+#define GPIO_MASK_MASKP24_SHIFT                  (24U)
+/*! MASKP24 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP24(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP24_SHIFT)) & GPIO_MASK_MASKP24_MASK)
+
+#define GPIO_MASK_MASKP25_MASK                   (0x2000000U)
+#define GPIO_MASK_MASKP25_SHIFT                  (25U)
+/*! MASKP25 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP25(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP25_SHIFT)) & GPIO_MASK_MASKP25_MASK)
+
+#define GPIO_MASK_MASKP26_MASK                   (0x4000000U)
+#define GPIO_MASK_MASKP26_SHIFT                  (26U)
+/*! MASKP26 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP26(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP26_SHIFT)) & GPIO_MASK_MASKP26_MASK)
+
+#define GPIO_MASK_MASKP27_MASK                   (0x8000000U)
+#define GPIO_MASK_MASKP27_SHIFT                  (27U)
+/*! MASKP27 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP27(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP27_SHIFT)) & GPIO_MASK_MASKP27_MASK)
+
+#define GPIO_MASK_MASKP28_MASK                   (0x10000000U)
+#define GPIO_MASK_MASKP28_SHIFT                  (28U)
+/*! MASKP28 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP28(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP28_SHIFT)) & GPIO_MASK_MASKP28_MASK)
+
+#define GPIO_MASK_MASKP29_MASK                   (0x20000000U)
+#define GPIO_MASK_MASKP29_SHIFT                  (29U)
+/*! MASKP29 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP29(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP29_SHIFT)) & GPIO_MASK_MASKP29_MASK)
+
+#define GPIO_MASK_MASKP30_MASK                   (0x40000000U)
+#define GPIO_MASK_MASKP30_SHIFT                  (30U)
+/*! MASKP30 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP30(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP30_SHIFT)) & GPIO_MASK_MASKP30_MASK)
+
+#define GPIO_MASK_MASKP31_MASK                   (0x80000000U)
+#define GPIO_MASK_MASKP31_SHIFT                  (31U)
+/*! MASKP31 - Port Mask
+ *  0b0..Read MPIN: pin state; write MPIN: load output bit
+ *  0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP31(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP31_SHIFT)) & GPIO_MASK_MASKP31_MASK)
+/*! @} */
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT                          (2U)
+
+/*! @name PIN - Port pin */
+/*! @{ */
+
+#define GPIO_PIN_PORT0_MASK                      (0x1U)
+#define GPIO_PIN_PORT0_SHIFT                     (0U)
+/*! PORT0 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT0_SHIFT)) & GPIO_PIN_PORT0_MASK)
+
+#define GPIO_PIN_PORT1_MASK                      (0x2U)
+#define GPIO_PIN_PORT1_SHIFT                     (1U)
+/*! PORT1 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT1_SHIFT)) & GPIO_PIN_PORT1_MASK)
+
+#define GPIO_PIN_PORT2_MASK                      (0x4U)
+#define GPIO_PIN_PORT2_SHIFT                     (2U)
+/*! PORT2 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT2_SHIFT)) & GPIO_PIN_PORT2_MASK)
+
+#define GPIO_PIN_PORT3_MASK                      (0x8U)
+#define GPIO_PIN_PORT3_SHIFT                     (3U)
+/*! PORT3 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT3_SHIFT)) & GPIO_PIN_PORT3_MASK)
+
+#define GPIO_PIN_PORT4_MASK                      (0x10U)
+#define GPIO_PIN_PORT4_SHIFT                     (4U)
+/*! PORT4 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT4_SHIFT)) & GPIO_PIN_PORT4_MASK)
+
+#define GPIO_PIN_PORT5_MASK                      (0x20U)
+#define GPIO_PIN_PORT5_SHIFT                     (5U)
+/*! PORT5 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT5_SHIFT)) & GPIO_PIN_PORT5_MASK)
+
+#define GPIO_PIN_PORT6_MASK                      (0x40U)
+#define GPIO_PIN_PORT6_SHIFT                     (6U)
+/*! PORT6 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT6_SHIFT)) & GPIO_PIN_PORT6_MASK)
+
+#define GPIO_PIN_PORT7_MASK                      (0x80U)
+#define GPIO_PIN_PORT7_SHIFT                     (7U)
+/*! PORT7 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT7_SHIFT)) & GPIO_PIN_PORT7_MASK)
+
+#define GPIO_PIN_PORT8_MASK                      (0x100U)
+#define GPIO_PIN_PORT8_SHIFT                     (8U)
+/*! PORT8 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT8_SHIFT)) & GPIO_PIN_PORT8_MASK)
+
+#define GPIO_PIN_PORT9_MASK                      (0x200U)
+#define GPIO_PIN_PORT9_SHIFT                     (9U)
+/*! PORT9 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT9_SHIFT)) & GPIO_PIN_PORT9_MASK)
+
+#define GPIO_PIN_PORT10_MASK                     (0x400U)
+#define GPIO_PIN_PORT10_SHIFT                    (10U)
+/*! PORT10 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT10_SHIFT)) & GPIO_PIN_PORT10_MASK)
+
+#define GPIO_PIN_PORT11_MASK                     (0x800U)
+#define GPIO_PIN_PORT11_SHIFT                    (11U)
+/*! PORT11 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT11_SHIFT)) & GPIO_PIN_PORT11_MASK)
+
+#define GPIO_PIN_PORT12_MASK                     (0x1000U)
+#define GPIO_PIN_PORT12_SHIFT                    (12U)
+/*! PORT12 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT12_SHIFT)) & GPIO_PIN_PORT12_MASK)
+
+#define GPIO_PIN_PORT13_MASK                     (0x2000U)
+#define GPIO_PIN_PORT13_SHIFT                    (13U)
+/*! PORT13 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT13_SHIFT)) & GPIO_PIN_PORT13_MASK)
+
+#define GPIO_PIN_PORT14_MASK                     (0x4000U)
+#define GPIO_PIN_PORT14_SHIFT                    (14U)
+/*! PORT14 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT14_SHIFT)) & GPIO_PIN_PORT14_MASK)
+
+#define GPIO_PIN_PORT15_MASK                     (0x8000U)
+#define GPIO_PIN_PORT15_SHIFT                    (15U)
+/*! PORT15 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT15_SHIFT)) & GPIO_PIN_PORT15_MASK)
+
+#define GPIO_PIN_PORT16_MASK                     (0x10000U)
+#define GPIO_PIN_PORT16_SHIFT                    (16U)
+/*! PORT16 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT16_SHIFT)) & GPIO_PIN_PORT16_MASK)
+
+#define GPIO_PIN_PORT17_MASK                     (0x20000U)
+#define GPIO_PIN_PORT17_SHIFT                    (17U)
+/*! PORT17 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT17_SHIFT)) & GPIO_PIN_PORT17_MASK)
+
+#define GPIO_PIN_PORT18_MASK                     (0x40000U)
+#define GPIO_PIN_PORT18_SHIFT                    (18U)
+/*! PORT18 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT18_SHIFT)) & GPIO_PIN_PORT18_MASK)
+
+#define GPIO_PIN_PORT19_MASK                     (0x80000U)
+#define GPIO_PIN_PORT19_SHIFT                    (19U)
+/*! PORT19 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT19_SHIFT)) & GPIO_PIN_PORT19_MASK)
+
+#define GPIO_PIN_PORT20_MASK                     (0x100000U)
+#define GPIO_PIN_PORT20_SHIFT                    (20U)
+/*! PORT20 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT20_SHIFT)) & GPIO_PIN_PORT20_MASK)
+
+#define GPIO_PIN_PORT21_MASK                     (0x200000U)
+#define GPIO_PIN_PORT21_SHIFT                    (21U)
+/*! PORT21 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT21_SHIFT)) & GPIO_PIN_PORT21_MASK)
+
+#define GPIO_PIN_PORT22_MASK                     (0x400000U)
+#define GPIO_PIN_PORT22_SHIFT                    (22U)
+/*! PORT22 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT22_SHIFT)) & GPIO_PIN_PORT22_MASK)
+
+#define GPIO_PIN_PORT23_MASK                     (0x800000U)
+#define GPIO_PIN_PORT23_SHIFT                    (23U)
+/*! PORT23 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT23_SHIFT)) & GPIO_PIN_PORT23_MASK)
+
+#define GPIO_PIN_PORT24_MASK                     (0x1000000U)
+#define GPIO_PIN_PORT24_SHIFT                    (24U)
+/*! PORT24 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT24_SHIFT)) & GPIO_PIN_PORT24_MASK)
+
+#define GPIO_PIN_PORT25_MASK                     (0x2000000U)
+#define GPIO_PIN_PORT25_SHIFT                    (25U)
+/*! PORT25 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT25_SHIFT)) & GPIO_PIN_PORT25_MASK)
+
+#define GPIO_PIN_PORT26_MASK                     (0x4000000U)
+#define GPIO_PIN_PORT26_SHIFT                    (26U)
+/*! PORT26 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT26_SHIFT)) & GPIO_PIN_PORT26_MASK)
+
+#define GPIO_PIN_PORT27_MASK                     (0x8000000U)
+#define GPIO_PIN_PORT27_SHIFT                    (27U)
+/*! PORT27 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT27_SHIFT)) & GPIO_PIN_PORT27_MASK)
+
+#define GPIO_PIN_PORT28_MASK                     (0x10000000U)
+#define GPIO_PIN_PORT28_SHIFT                    (28U)
+/*! PORT28 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT28_SHIFT)) & GPIO_PIN_PORT28_MASK)
+
+#define GPIO_PIN_PORT29_MASK                     (0x20000000U)
+#define GPIO_PIN_PORT29_SHIFT                    (29U)
+/*! PORT29 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT29_SHIFT)) & GPIO_PIN_PORT29_MASK)
+
+#define GPIO_PIN_PORT30_MASK                     (0x40000000U)
+#define GPIO_PIN_PORT30_SHIFT                    (30U)
+/*! PORT30 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT30_SHIFT)) & GPIO_PIN_PORT30_MASK)
+
+#define GPIO_PIN_PORT31_MASK                     (0x80000000U)
+#define GPIO_PIN_PORT31_SHIFT                    (31U)
+/*! PORT31 - Port pins
+ *  0b0..Read- pin is low; Write- clear output bit
+ *  0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT31_SHIFT)) & GPIO_PIN_PORT31_MASK)
+/*! @} */
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT                           (2U)
+
+/*! @name MPIN - Masked Port Pin */
+/*! @{ */
+
+#define GPIO_MPIN_MPORTP0_MASK                   (0x1U)
+#define GPIO_MPIN_MPORTP0_SHIFT                  (0U)
+/*! MPORTP0 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP0(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP0_SHIFT)) & GPIO_MPIN_MPORTP0_MASK)
+
+#define GPIO_MPIN_MPORTP1_MASK                   (0x2U)
+#define GPIO_MPIN_MPORTP1_SHIFT                  (1U)
+/*! MPORTP1 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP1(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP1_SHIFT)) & GPIO_MPIN_MPORTP1_MASK)
+
+#define GPIO_MPIN_MPORTP2_MASK                   (0x4U)
+#define GPIO_MPIN_MPORTP2_SHIFT                  (2U)
+/*! MPORTP2 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP2(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP2_SHIFT)) & GPIO_MPIN_MPORTP2_MASK)
+
+#define GPIO_MPIN_MPORTP3_MASK                   (0x8U)
+#define GPIO_MPIN_MPORTP3_SHIFT                  (3U)
+/*! MPORTP3 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP3(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP3_SHIFT)) & GPIO_MPIN_MPORTP3_MASK)
+
+#define GPIO_MPIN_MPORTP4_MASK                   (0x10U)
+#define GPIO_MPIN_MPORTP4_SHIFT                  (4U)
+/*! MPORTP4 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP4(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP4_SHIFT)) & GPIO_MPIN_MPORTP4_MASK)
+
+#define GPIO_MPIN_MPORTP5_MASK                   (0x20U)
+#define GPIO_MPIN_MPORTP5_SHIFT                  (5U)
+/*! MPORTP5 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP5(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP5_SHIFT)) & GPIO_MPIN_MPORTP5_MASK)
+
+#define GPIO_MPIN_MPORTP6_MASK                   (0x40U)
+#define GPIO_MPIN_MPORTP6_SHIFT                  (6U)
+/*! MPORTP6 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP6(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP6_SHIFT)) & GPIO_MPIN_MPORTP6_MASK)
+
+#define GPIO_MPIN_MPORTP7_MASK                   (0x80U)
+#define GPIO_MPIN_MPORTP7_SHIFT                  (7U)
+/*! MPORTP7 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP7(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP7_SHIFT)) & GPIO_MPIN_MPORTP7_MASK)
+
+#define GPIO_MPIN_MPORTP8_MASK                   (0x100U)
+#define GPIO_MPIN_MPORTP8_SHIFT                  (8U)
+/*! MPORTP8 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP8(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP8_SHIFT)) & GPIO_MPIN_MPORTP8_MASK)
+
+#define GPIO_MPIN_MPORTP9_MASK                   (0x200U)
+#define GPIO_MPIN_MPORTP9_SHIFT                  (9U)
+/*! MPORTP9 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP9(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP9_SHIFT)) & GPIO_MPIN_MPORTP9_MASK)
+
+#define GPIO_MPIN_MPORTP10_MASK                  (0x400U)
+#define GPIO_MPIN_MPORTP10_SHIFT                 (10U)
+/*! MPORTP10 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP10(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP10_SHIFT)) & GPIO_MPIN_MPORTP10_MASK)
+
+#define GPIO_MPIN_MPORTP11_MASK                  (0x800U)
+#define GPIO_MPIN_MPORTP11_SHIFT                 (11U)
+/*! MPORTP11 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP11(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP11_SHIFT)) & GPIO_MPIN_MPORTP11_MASK)
+
+#define GPIO_MPIN_MPORTP12_MASK                  (0x1000U)
+#define GPIO_MPIN_MPORTP12_SHIFT                 (12U)
+/*! MPORTP12 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP12(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP12_SHIFT)) & GPIO_MPIN_MPORTP12_MASK)
+
+#define GPIO_MPIN_MPORTP13_MASK                  (0x2000U)
+#define GPIO_MPIN_MPORTP13_SHIFT                 (13U)
+/*! MPORTP13 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP13(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP13_SHIFT)) & GPIO_MPIN_MPORTP13_MASK)
+
+#define GPIO_MPIN_MPORTP14_MASK                  (0x4000U)
+#define GPIO_MPIN_MPORTP14_SHIFT                 (14U)
+/*! MPORTP14 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP14(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP14_SHIFT)) & GPIO_MPIN_MPORTP14_MASK)
+
+#define GPIO_MPIN_MPORTP15_MASK                  (0x8000U)
+#define GPIO_MPIN_MPORTP15_SHIFT                 (15U)
+/*! MPORTP15 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP15(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP15_SHIFT)) & GPIO_MPIN_MPORTP15_MASK)
+
+#define GPIO_MPIN_MPORTP16_MASK                  (0x10000U)
+#define GPIO_MPIN_MPORTP16_SHIFT                 (16U)
+/*! MPORTP16 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP16(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP16_SHIFT)) & GPIO_MPIN_MPORTP16_MASK)
+
+#define GPIO_MPIN_MPORTP17_MASK                  (0x20000U)
+#define GPIO_MPIN_MPORTP17_SHIFT                 (17U)
+/*! MPORTP17 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP17(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP17_SHIFT)) & GPIO_MPIN_MPORTP17_MASK)
+
+#define GPIO_MPIN_MPORTP18_MASK                  (0x40000U)
+#define GPIO_MPIN_MPORTP18_SHIFT                 (18U)
+/*! MPORTP18 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP18(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP18_SHIFT)) & GPIO_MPIN_MPORTP18_MASK)
+
+#define GPIO_MPIN_MPORTP19_MASK                  (0x80000U)
+#define GPIO_MPIN_MPORTP19_SHIFT                 (19U)
+/*! MPORTP19 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP19(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP19_SHIFT)) & GPIO_MPIN_MPORTP19_MASK)
+
+#define GPIO_MPIN_MPORTP20_MASK                  (0x100000U)
+#define GPIO_MPIN_MPORTP20_SHIFT                 (20U)
+/*! MPORTP20 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP20(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP20_SHIFT)) & GPIO_MPIN_MPORTP20_MASK)
+
+#define GPIO_MPIN_MPORTP21_MASK                  (0x200000U)
+#define GPIO_MPIN_MPORTP21_SHIFT                 (21U)
+/*! MPORTP21 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP21(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP21_SHIFT)) & GPIO_MPIN_MPORTP21_MASK)
+
+#define GPIO_MPIN_MPORTP22_MASK                  (0x400000U)
+#define GPIO_MPIN_MPORTP22_SHIFT                 (22U)
+/*! MPORTP22 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP22(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP22_SHIFT)) & GPIO_MPIN_MPORTP22_MASK)
+
+#define GPIO_MPIN_MPORTP23_MASK                  (0x800000U)
+#define GPIO_MPIN_MPORTP23_SHIFT                 (23U)
+/*! MPORTP23 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP23(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP23_SHIFT)) & GPIO_MPIN_MPORTP23_MASK)
+
+#define GPIO_MPIN_MPORTP24_MASK                  (0x1000000U)
+#define GPIO_MPIN_MPORTP24_SHIFT                 (24U)
+/*! MPORTP24 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP24(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP24_SHIFT)) & GPIO_MPIN_MPORTP24_MASK)
+
+#define GPIO_MPIN_MPORTP25_MASK                  (0x2000000U)
+#define GPIO_MPIN_MPORTP25_SHIFT                 (25U)
+/*! MPORTP25 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP25(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP25_SHIFT)) & GPIO_MPIN_MPORTP25_MASK)
+
+#define GPIO_MPIN_MPORTP26_MASK                  (0x4000000U)
+#define GPIO_MPIN_MPORTP26_SHIFT                 (26U)
+/*! MPORTP26 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP26(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP26_SHIFT)) & GPIO_MPIN_MPORTP26_MASK)
+
+#define GPIO_MPIN_MPORTP27_MASK                  (0x8000000U)
+#define GPIO_MPIN_MPORTP27_SHIFT                 (27U)
+/*! MPORTP27 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP27(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP27_SHIFT)) & GPIO_MPIN_MPORTP27_MASK)
+
+#define GPIO_MPIN_MPORTP28_MASK                  (0x10000000U)
+#define GPIO_MPIN_MPORTP28_SHIFT                 (28U)
+/*! MPORTP28 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP28(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP28_SHIFT)) & GPIO_MPIN_MPORTP28_MASK)
+
+#define GPIO_MPIN_MPORTP29_MASK                  (0x20000000U)
+#define GPIO_MPIN_MPORTP29_SHIFT                 (29U)
+/*! MPORTP29 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP29(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP29_SHIFT)) & GPIO_MPIN_MPORTP29_MASK)
+
+#define GPIO_MPIN_MPORTP30_MASK                  (0x40000000U)
+#define GPIO_MPIN_MPORTP30_SHIFT                 (30U)
+/*! MPORTP30 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP30(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP30_SHIFT)) & GPIO_MPIN_MPORTP30_MASK)
+
+#define GPIO_MPIN_MPORTP31_MASK                  (0x80000000U)
+#define GPIO_MPIN_MPORTP31_SHIFT                 (31U)
+/*! MPORTP31 - Mask bits for port pins
+ *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ *       corresponding bit in the MASK register is 0
+ *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ *       corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP31(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP31_SHIFT)) & GPIO_MPIN_MPORTP31_MASK)
+/*! @} */
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT                          (2U)
+
+/*! @name SET - Port set */
+/*! @{ */
+
+#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT                      (0U)
+/*! SETP - Read or set output bits
+ *  0b00000000000000000000000000000000..Read- output bit; write- no operation
+ *  0b00000000000000000000000000000001..Read- output bit; write- set output bit
+ */
+#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+/*! @} */
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT                           (2U)
+
+/*! @name CLR - Port clear */
+/*! @{ */
+
+#define GPIO_CLR_CLRP0_MASK                      (0x1U)
+#define GPIO_CLR_CLRP0_SHIFT                     (0U)
+/*! CLRP0 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP0_SHIFT)) & GPIO_CLR_CLRP0_MASK)
+
+#define GPIO_CLR_CLRP1_MASK                      (0x2U)
+#define GPIO_CLR_CLRP1_SHIFT                     (1U)
+/*! CLRP1 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP1_SHIFT)) & GPIO_CLR_CLRP1_MASK)
+
+#define GPIO_CLR_CLRP2_MASK                      (0x4U)
+#define GPIO_CLR_CLRP2_SHIFT                     (2U)
+/*! CLRP2 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP2_SHIFT)) & GPIO_CLR_CLRP2_MASK)
+
+#define GPIO_CLR_CLRP3_MASK                      (0x8U)
+#define GPIO_CLR_CLRP3_SHIFT                     (3U)
+/*! CLRP3 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP3_SHIFT)) & GPIO_CLR_CLRP3_MASK)
+
+#define GPIO_CLR_CLRP4_MASK                      (0x10U)
+#define GPIO_CLR_CLRP4_SHIFT                     (4U)
+/*! CLRP4 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP4_SHIFT)) & GPIO_CLR_CLRP4_MASK)
+
+#define GPIO_CLR_CLRP5_MASK                      (0x20U)
+#define GPIO_CLR_CLRP5_SHIFT                     (5U)
+/*! CLRP5 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP5_SHIFT)) & GPIO_CLR_CLRP5_MASK)
+
+#define GPIO_CLR_CLRP6_MASK                      (0x40U)
+#define GPIO_CLR_CLRP6_SHIFT                     (6U)
+/*! CLRP6 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP6_SHIFT)) & GPIO_CLR_CLRP6_MASK)
+
+#define GPIO_CLR_CLRP7_MASK                      (0x80U)
+#define GPIO_CLR_CLRP7_SHIFT                     (7U)
+/*! CLRP7 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP7_SHIFT)) & GPIO_CLR_CLRP7_MASK)
+
+#define GPIO_CLR_CLRP8_MASK                      (0x100U)
+#define GPIO_CLR_CLRP8_SHIFT                     (8U)
+/*! CLRP8 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP8_SHIFT)) & GPIO_CLR_CLRP8_MASK)
+
+#define GPIO_CLR_CLRP9_MASK                      (0x200U)
+#define GPIO_CLR_CLRP9_SHIFT                     (9U)
+/*! CLRP9 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP9_SHIFT)) & GPIO_CLR_CLRP9_MASK)
+
+#define GPIO_CLR_CLRP10_MASK                     (0x400U)
+#define GPIO_CLR_CLRP10_SHIFT                    (10U)
+/*! CLRP10 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP10_SHIFT)) & GPIO_CLR_CLRP10_MASK)
+
+#define GPIO_CLR_CLRP11_MASK                     (0x800U)
+#define GPIO_CLR_CLRP11_SHIFT                    (11U)
+/*! CLRP11 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP11_SHIFT)) & GPIO_CLR_CLRP11_MASK)
+
+#define GPIO_CLR_CLRP12_MASK                     (0x1000U)
+#define GPIO_CLR_CLRP12_SHIFT                    (12U)
+/*! CLRP12 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP12_SHIFT)) & GPIO_CLR_CLRP12_MASK)
+
+#define GPIO_CLR_CLRP13_MASK                     (0x2000U)
+#define GPIO_CLR_CLRP13_SHIFT                    (13U)
+/*! CLRP13 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP13_SHIFT)) & GPIO_CLR_CLRP13_MASK)
+
+#define GPIO_CLR_CLRP14_MASK                     (0x4000U)
+#define GPIO_CLR_CLRP14_SHIFT                    (14U)
+/*! CLRP14 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP14_SHIFT)) & GPIO_CLR_CLRP14_MASK)
+
+#define GPIO_CLR_CLRP15_MASK                     (0x8000U)
+#define GPIO_CLR_CLRP15_SHIFT                    (15U)
+/*! CLRP15 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP15_SHIFT)) & GPIO_CLR_CLRP15_MASK)
+
+#define GPIO_CLR_CLRP16_MASK                     (0x10000U)
+#define GPIO_CLR_CLRP16_SHIFT                    (16U)
+/*! CLRP16 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP16_SHIFT)) & GPIO_CLR_CLRP16_MASK)
+
+#define GPIO_CLR_CLRP17_MASK                     (0x20000U)
+#define GPIO_CLR_CLRP17_SHIFT                    (17U)
+/*! CLRP17 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP17_SHIFT)) & GPIO_CLR_CLRP17_MASK)
+
+#define GPIO_CLR_CLRP18_MASK                     (0x40000U)
+#define GPIO_CLR_CLRP18_SHIFT                    (18U)
+/*! CLRP18 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP18_SHIFT)) & GPIO_CLR_CLRP18_MASK)
+
+#define GPIO_CLR_CLRP19_MASK                     (0x80000U)
+#define GPIO_CLR_CLRP19_SHIFT                    (19U)
+/*! CLRP19 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP19_SHIFT)) & GPIO_CLR_CLRP19_MASK)
+
+#define GPIO_CLR_CLRP20_MASK                     (0x100000U)
+#define GPIO_CLR_CLRP20_SHIFT                    (20U)
+/*! CLRP20 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP20_SHIFT)) & GPIO_CLR_CLRP20_MASK)
+
+#define GPIO_CLR_CLRP21_MASK                     (0x200000U)
+#define GPIO_CLR_CLRP21_SHIFT                    (21U)
+/*! CLRP21 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP21_SHIFT)) & GPIO_CLR_CLRP21_MASK)
+
+#define GPIO_CLR_CLRP22_MASK                     (0x400000U)
+#define GPIO_CLR_CLRP22_SHIFT                    (22U)
+/*! CLRP22 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP22_SHIFT)) & GPIO_CLR_CLRP22_MASK)
+
+#define GPIO_CLR_CLRP23_MASK                     (0x800000U)
+#define GPIO_CLR_CLRP23_SHIFT                    (23U)
+/*! CLRP23 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP23_SHIFT)) & GPIO_CLR_CLRP23_MASK)
+
+#define GPIO_CLR_CLRP24_MASK                     (0x1000000U)
+#define GPIO_CLR_CLRP24_SHIFT                    (24U)
+/*! CLRP24 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP24_SHIFT)) & GPIO_CLR_CLRP24_MASK)
+
+#define GPIO_CLR_CLRP25_MASK                     (0x2000000U)
+#define GPIO_CLR_CLRP25_SHIFT                    (25U)
+/*! CLRP25 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP25_SHIFT)) & GPIO_CLR_CLRP25_MASK)
+
+#define GPIO_CLR_CLRP26_MASK                     (0x4000000U)
+#define GPIO_CLR_CLRP26_SHIFT                    (26U)
+/*! CLRP26 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP26_SHIFT)) & GPIO_CLR_CLRP26_MASK)
+
+#define GPIO_CLR_CLRP27_MASK                     (0x8000000U)
+#define GPIO_CLR_CLRP27_SHIFT                    (27U)
+/*! CLRP27 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP27_SHIFT)) & GPIO_CLR_CLRP27_MASK)
+
+#define GPIO_CLR_CLRP28_MASK                     (0x10000000U)
+#define GPIO_CLR_CLRP28_SHIFT                    (28U)
+/*! CLRP28 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP28_SHIFT)) & GPIO_CLR_CLRP28_MASK)
+
+#define GPIO_CLR_CLRP29_MASK                     (0x20000000U)
+#define GPIO_CLR_CLRP29_SHIFT                    (29U)
+/*! CLRP29 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP29_SHIFT)) & GPIO_CLR_CLRP29_MASK)
+
+#define GPIO_CLR_CLRP30_MASK                     (0x40000000U)
+#define GPIO_CLR_CLRP30_SHIFT                    (30U)
+/*! CLRP30 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP30_SHIFT)) & GPIO_CLR_CLRP30_MASK)
+
+#define GPIO_CLR_CLRP31_MASK                     (0x80000000U)
+#define GPIO_CLR_CLRP31_SHIFT                    (31U)
+/*! CLRP31 - Clear output bits
+ *  0b0..No operation
+ *  0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP31_SHIFT)) & GPIO_CLR_CLRP31_MASK)
+/*! @} */
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT                           (2U)
+
+/*! @name NOT - Port toggle */
+/*! @{ */
+
+#define GPIO_NOT_NOTP0_MASK                      (0x1U)
+#define GPIO_NOT_NOTP0_SHIFT                     (0U)
+/*! NOTP0 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP0_SHIFT)) & GPIO_NOT_NOTP0_MASK)
+
+#define GPIO_NOT_NOTP1_MASK                      (0x2U)
+#define GPIO_NOT_NOTP1_SHIFT                     (1U)
+/*! NOTP1 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP1_SHIFT)) & GPIO_NOT_NOTP1_MASK)
+
+#define GPIO_NOT_NOTP2_MASK                      (0x4U)
+#define GPIO_NOT_NOTP2_SHIFT                     (2U)
+/*! NOTP2 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP2_SHIFT)) & GPIO_NOT_NOTP2_MASK)
+
+#define GPIO_NOT_NOTP3_MASK                      (0x8U)
+#define GPIO_NOT_NOTP3_SHIFT                     (3U)
+/*! NOTP3 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP3_SHIFT)) & GPIO_NOT_NOTP3_MASK)
+
+#define GPIO_NOT_NOTP4_MASK                      (0x10U)
+#define GPIO_NOT_NOTP4_SHIFT                     (4U)
+/*! NOTP4 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP4_SHIFT)) & GPIO_NOT_NOTP4_MASK)
+
+#define GPIO_NOT_NOTP5_MASK                      (0x20U)
+#define GPIO_NOT_NOTP5_SHIFT                     (5U)
+/*! NOTP5 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP5_SHIFT)) & GPIO_NOT_NOTP5_MASK)
+
+#define GPIO_NOT_NOTP6_MASK                      (0x40U)
+#define GPIO_NOT_NOTP6_SHIFT                     (6U)
+/*! NOTP6 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP6_SHIFT)) & GPIO_NOT_NOTP6_MASK)
+
+#define GPIO_NOT_NOTP7_MASK                      (0x80U)
+#define GPIO_NOT_NOTP7_SHIFT                     (7U)
+/*! NOTP7 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP7_SHIFT)) & GPIO_NOT_NOTP7_MASK)
+
+#define GPIO_NOT_NOTP8_MASK                      (0x100U)
+#define GPIO_NOT_NOTP8_SHIFT                     (8U)
+/*! NOTP8 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP8_SHIFT)) & GPIO_NOT_NOTP8_MASK)
+
+#define GPIO_NOT_NOTP9_MASK                      (0x200U)
+#define GPIO_NOT_NOTP9_SHIFT                     (9U)
+/*! NOTP9 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP9_SHIFT)) & GPIO_NOT_NOTP9_MASK)
+
+#define GPIO_NOT_NOTP10_MASK                     (0x400U)
+#define GPIO_NOT_NOTP10_SHIFT                    (10U)
+/*! NOTP10 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP10_SHIFT)) & GPIO_NOT_NOTP10_MASK)
+
+#define GPIO_NOT_NOTP11_MASK                     (0x800U)
+#define GPIO_NOT_NOTP11_SHIFT                    (11U)
+/*! NOTP11 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP11_SHIFT)) & GPIO_NOT_NOTP11_MASK)
+
+#define GPIO_NOT_NOTP12_MASK                     (0x1000U)
+#define GPIO_NOT_NOTP12_SHIFT                    (12U)
+/*! NOTP12 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP12_SHIFT)) & GPIO_NOT_NOTP12_MASK)
+
+#define GPIO_NOT_NOTP13_MASK                     (0x2000U)
+#define GPIO_NOT_NOTP13_SHIFT                    (13U)
+/*! NOTP13 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP13_SHIFT)) & GPIO_NOT_NOTP13_MASK)
+
+#define GPIO_NOT_NOTP14_MASK                     (0x4000U)
+#define GPIO_NOT_NOTP14_SHIFT                    (14U)
+/*! NOTP14 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP14_SHIFT)) & GPIO_NOT_NOTP14_MASK)
+
+#define GPIO_NOT_NOTP15_MASK                     (0x8000U)
+#define GPIO_NOT_NOTP15_SHIFT                    (15U)
+/*! NOTP15 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP15_SHIFT)) & GPIO_NOT_NOTP15_MASK)
+
+#define GPIO_NOT_NOTP16_MASK                     (0x10000U)
+#define GPIO_NOT_NOTP16_SHIFT                    (16U)
+/*! NOTP16 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP16_SHIFT)) & GPIO_NOT_NOTP16_MASK)
+
+#define GPIO_NOT_NOTP17_MASK                     (0x20000U)
+#define GPIO_NOT_NOTP17_SHIFT                    (17U)
+/*! NOTP17 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP17_SHIFT)) & GPIO_NOT_NOTP17_MASK)
+
+#define GPIO_NOT_NOTP18_MASK                     (0x40000U)
+#define GPIO_NOT_NOTP18_SHIFT                    (18U)
+/*! NOTP18 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP18_SHIFT)) & GPIO_NOT_NOTP18_MASK)
+
+#define GPIO_NOT_NOTP19_MASK                     (0x80000U)
+#define GPIO_NOT_NOTP19_SHIFT                    (19U)
+/*! NOTP19 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP19_SHIFT)) & GPIO_NOT_NOTP19_MASK)
+
+#define GPIO_NOT_NOTP20_MASK                     (0x100000U)
+#define GPIO_NOT_NOTP20_SHIFT                    (20U)
+/*! NOTP20 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP20_SHIFT)) & GPIO_NOT_NOTP20_MASK)
+
+#define GPIO_NOT_NOTP21_MASK                     (0x200000U)
+#define GPIO_NOT_NOTP21_SHIFT                    (21U)
+/*! NOTP21 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP21_SHIFT)) & GPIO_NOT_NOTP21_MASK)
+
+#define GPIO_NOT_NOTP22_MASK                     (0x400000U)
+#define GPIO_NOT_NOTP22_SHIFT                    (22U)
+/*! NOTP22 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP22_SHIFT)) & GPIO_NOT_NOTP22_MASK)
+
+#define GPIO_NOT_NOTP23_MASK                     (0x800000U)
+#define GPIO_NOT_NOTP23_SHIFT                    (23U)
+/*! NOTP23 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP23_SHIFT)) & GPIO_NOT_NOTP23_MASK)
+
+#define GPIO_NOT_NOTP24_MASK                     (0x1000000U)
+#define GPIO_NOT_NOTP24_SHIFT                    (24U)
+/*! NOTP24 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP24_SHIFT)) & GPIO_NOT_NOTP24_MASK)
+
+#define GPIO_NOT_NOTP25_MASK                     (0x2000000U)
+#define GPIO_NOT_NOTP25_SHIFT                    (25U)
+/*! NOTP25 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP25_SHIFT)) & GPIO_NOT_NOTP25_MASK)
+
+#define GPIO_NOT_NOTP26_MASK                     (0x4000000U)
+#define GPIO_NOT_NOTP26_SHIFT                    (26U)
+/*! NOTP26 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP26_SHIFT)) & GPIO_NOT_NOTP26_MASK)
+
+#define GPIO_NOT_NOTP27_MASK                     (0x8000000U)
+#define GPIO_NOT_NOTP27_SHIFT                    (27U)
+/*! NOTP27 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP27_SHIFT)) & GPIO_NOT_NOTP27_MASK)
+
+#define GPIO_NOT_NOTP28_MASK                     (0x10000000U)
+#define GPIO_NOT_NOTP28_SHIFT                    (28U)
+/*! NOTP28 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP28_SHIFT)) & GPIO_NOT_NOTP28_MASK)
+
+#define GPIO_NOT_NOTP29_MASK                     (0x20000000U)
+#define GPIO_NOT_NOTP29_SHIFT                    (29U)
+/*! NOTP29 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP29_SHIFT)) & GPIO_NOT_NOTP29_MASK)
+
+#define GPIO_NOT_NOTP30_MASK                     (0x40000000U)
+#define GPIO_NOT_NOTP30_SHIFT                    (30U)
+/*! NOTP30 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP30_SHIFT)) & GPIO_NOT_NOTP30_MASK)
+
+#define GPIO_NOT_NOTP31_MASK                     (0x80000000U)
+#define GPIO_NOT_NOTP31_SHIFT                    (31U)
+/*! NOTP31 - Toggle output bits
+ *  0b0..No operation
+ *  0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP31_SHIFT)) & GPIO_NOT_NOTP31_MASK)
+/*! @} */
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT                           (2U)
+
+/*! @name DIRSET - Port direction set */
+/*! @{ */
+
+#define GPIO_DIRSET_DIRSETP0_MASK                (0x1U)
+#define GPIO_DIRSET_DIRSETP0_SHIFT               (0U)
+/*! DIRSETP0 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP0_SHIFT)) & GPIO_DIRSET_DIRSETP0_MASK)
+
+#define GPIO_DIRSET_DIRSETP1_MASK                (0x2U)
+#define GPIO_DIRSET_DIRSETP1_SHIFT               (1U)
+/*! DIRSETP1 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP1_SHIFT)) & GPIO_DIRSET_DIRSETP1_MASK)
+
+#define GPIO_DIRSET_DIRSETP2_MASK                (0x4U)
+#define GPIO_DIRSET_DIRSETP2_SHIFT               (2U)
+/*! DIRSETP2 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP2_SHIFT)) & GPIO_DIRSET_DIRSETP2_MASK)
+
+#define GPIO_DIRSET_DIRSETP3_MASK                (0x8U)
+#define GPIO_DIRSET_DIRSETP3_SHIFT               (3U)
+/*! DIRSETP3 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP3_SHIFT)) & GPIO_DIRSET_DIRSETP3_MASK)
+
+#define GPIO_DIRSET_DIRSETP4_MASK                (0x10U)
+#define GPIO_DIRSET_DIRSETP4_SHIFT               (4U)
+/*! DIRSETP4 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP4_SHIFT)) & GPIO_DIRSET_DIRSETP4_MASK)
+
+#define GPIO_DIRSET_DIRSETP5_MASK                (0x20U)
+#define GPIO_DIRSET_DIRSETP5_SHIFT               (5U)
+/*! DIRSETP5 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP5_SHIFT)) & GPIO_DIRSET_DIRSETP5_MASK)
+
+#define GPIO_DIRSET_DIRSETP6_MASK                (0x40U)
+#define GPIO_DIRSET_DIRSETP6_SHIFT               (6U)
+/*! DIRSETP6 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP6_SHIFT)) & GPIO_DIRSET_DIRSETP6_MASK)
+
+#define GPIO_DIRSET_DIRSETP7_MASK                (0x80U)
+#define GPIO_DIRSET_DIRSETP7_SHIFT               (7U)
+/*! DIRSETP7 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP7_SHIFT)) & GPIO_DIRSET_DIRSETP7_MASK)
+
+#define GPIO_DIRSET_DIRSETP8_MASK                (0x100U)
+#define GPIO_DIRSET_DIRSETP8_SHIFT               (8U)
+/*! DIRSETP8 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP8_SHIFT)) & GPIO_DIRSET_DIRSETP8_MASK)
+
+#define GPIO_DIRSET_DIRSETP9_MASK                (0x200U)
+#define GPIO_DIRSET_DIRSETP9_SHIFT               (9U)
+/*! DIRSETP9 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP9_SHIFT)) & GPIO_DIRSET_DIRSETP9_MASK)
+
+#define GPIO_DIRSET_DIRSETP10_MASK               (0x400U)
+#define GPIO_DIRSET_DIRSETP10_SHIFT              (10U)
+/*! DIRSETP10 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP10_SHIFT)) & GPIO_DIRSET_DIRSETP10_MASK)
+
+#define GPIO_DIRSET_DIRSETP11_MASK               (0x800U)
+#define GPIO_DIRSET_DIRSETP11_SHIFT              (11U)
+/*! DIRSETP11 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP11_SHIFT)) & GPIO_DIRSET_DIRSETP11_MASK)
+
+#define GPIO_DIRSET_DIRSETP12_MASK               (0x1000U)
+#define GPIO_DIRSET_DIRSETP12_SHIFT              (12U)
+/*! DIRSETP12 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP12_SHIFT)) & GPIO_DIRSET_DIRSETP12_MASK)
+
+#define GPIO_DIRSET_DIRSETP13_MASK               (0x2000U)
+#define GPIO_DIRSET_DIRSETP13_SHIFT              (13U)
+/*! DIRSETP13 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP13_SHIFT)) & GPIO_DIRSET_DIRSETP13_MASK)
+
+#define GPIO_DIRSET_DIRSETP14_MASK               (0x4000U)
+#define GPIO_DIRSET_DIRSETP14_SHIFT              (14U)
+/*! DIRSETP14 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP14_SHIFT)) & GPIO_DIRSET_DIRSETP14_MASK)
+
+#define GPIO_DIRSET_DIRSETP15_MASK               (0x8000U)
+#define GPIO_DIRSET_DIRSETP15_SHIFT              (15U)
+/*! DIRSETP15 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP15_SHIFT)) & GPIO_DIRSET_DIRSETP15_MASK)
+
+#define GPIO_DIRSET_DIRSETP16_MASK               (0x10000U)
+#define GPIO_DIRSET_DIRSETP16_SHIFT              (16U)
+/*! DIRSETP16 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP16_SHIFT)) & GPIO_DIRSET_DIRSETP16_MASK)
+
+#define GPIO_DIRSET_DIRSETP17_MASK               (0x20000U)
+#define GPIO_DIRSET_DIRSETP17_SHIFT              (17U)
+/*! DIRSETP17 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP17_SHIFT)) & GPIO_DIRSET_DIRSETP17_MASK)
+
+#define GPIO_DIRSET_DIRSETP18_MASK               (0x40000U)
+#define GPIO_DIRSET_DIRSETP18_SHIFT              (18U)
+/*! DIRSETP18 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP18_SHIFT)) & GPIO_DIRSET_DIRSETP18_MASK)
+
+#define GPIO_DIRSET_DIRSETP19_MASK               (0x80000U)
+#define GPIO_DIRSET_DIRSETP19_SHIFT              (19U)
+/*! DIRSETP19 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP19_SHIFT)) & GPIO_DIRSET_DIRSETP19_MASK)
+
+#define GPIO_DIRSET_DIRSETP20_MASK               (0x100000U)
+#define GPIO_DIRSET_DIRSETP20_SHIFT              (20U)
+/*! DIRSETP20 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP20_SHIFT)) & GPIO_DIRSET_DIRSETP20_MASK)
+
+#define GPIO_DIRSET_DIRSETP21_MASK               (0x200000U)
+#define GPIO_DIRSET_DIRSETP21_SHIFT              (21U)
+/*! DIRSETP21 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP21_SHIFT)) & GPIO_DIRSET_DIRSETP21_MASK)
+
+#define GPIO_DIRSET_DIRSETP22_MASK               (0x400000U)
+#define GPIO_DIRSET_DIRSETP22_SHIFT              (22U)
+/*! DIRSETP22 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP22_SHIFT)) & GPIO_DIRSET_DIRSETP22_MASK)
+
+#define GPIO_DIRSET_DIRSETP23_MASK               (0x800000U)
+#define GPIO_DIRSET_DIRSETP23_SHIFT              (23U)
+/*! DIRSETP23 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP23_SHIFT)) & GPIO_DIRSET_DIRSETP23_MASK)
+
+#define GPIO_DIRSET_DIRSETP24_MASK               (0x1000000U)
+#define GPIO_DIRSET_DIRSETP24_SHIFT              (24U)
+/*! DIRSETP24 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP24_SHIFT)) & GPIO_DIRSET_DIRSETP24_MASK)
+
+#define GPIO_DIRSET_DIRSETP25_MASK               (0x2000000U)
+#define GPIO_DIRSET_DIRSETP25_SHIFT              (25U)
+/*! DIRSETP25 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP25_SHIFT)) & GPIO_DIRSET_DIRSETP25_MASK)
+
+#define GPIO_DIRSET_DIRSETP26_MASK               (0x4000000U)
+#define GPIO_DIRSET_DIRSETP26_SHIFT              (26U)
+/*! DIRSETP26 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP26_SHIFT)) & GPIO_DIRSET_DIRSETP26_MASK)
+
+#define GPIO_DIRSET_DIRSETP27_MASK               (0x8000000U)
+#define GPIO_DIRSET_DIRSETP27_SHIFT              (27U)
+/*! DIRSETP27 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP27_SHIFT)) & GPIO_DIRSET_DIRSETP27_MASK)
+
+#define GPIO_DIRSET_DIRSETP28_MASK               (0x10000000U)
+#define GPIO_DIRSET_DIRSETP28_SHIFT              (28U)
+/*! DIRSETP28 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP28_SHIFT)) & GPIO_DIRSET_DIRSETP28_MASK)
+
+#define GPIO_DIRSET_DIRSETP29_MASK               (0x20000000U)
+#define GPIO_DIRSET_DIRSETP29_SHIFT              (29U)
+/*! DIRSETP29 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP29_SHIFT)) & GPIO_DIRSET_DIRSETP29_MASK)
+
+#define GPIO_DIRSET_DIRSETP30_MASK               (0x40000000U)
+#define GPIO_DIRSET_DIRSETP30_SHIFT              (30U)
+/*! DIRSETP30 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP30_SHIFT)) & GPIO_DIRSET_DIRSETP30_MASK)
+
+#define GPIO_DIRSET_DIRSETP31_MASK               (0x80000000U)
+#define GPIO_DIRSET_DIRSETP31_SHIFT              (31U)
+/*! DIRSETP31 - Direction set bits for Port pins
+ *  0b0..No operation
+ *  0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP31_SHIFT)) & GPIO_DIRSET_DIRSETP31_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT                        (2U)
+
+/*! @name DIRCLR - Port direction clear */
+/*! @{ */
+
+#define GPIO_DIRCLR_DIRCLRP0_MASK                (0x1U)
+#define GPIO_DIRCLR_DIRCLRP0_SHIFT               (0U)
+/*! DIRCLRP0 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP0_SHIFT)) & GPIO_DIRCLR_DIRCLRP0_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP1_MASK                (0x2U)
+#define GPIO_DIRCLR_DIRCLRP1_SHIFT               (1U)
+/*! DIRCLRP1 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP1_SHIFT)) & GPIO_DIRCLR_DIRCLRP1_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP2_MASK                (0x4U)
+#define GPIO_DIRCLR_DIRCLRP2_SHIFT               (2U)
+/*! DIRCLRP2 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP2_SHIFT)) & GPIO_DIRCLR_DIRCLRP2_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP3_MASK                (0x8U)
+#define GPIO_DIRCLR_DIRCLRP3_SHIFT               (3U)
+/*! DIRCLRP3 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP3_SHIFT)) & GPIO_DIRCLR_DIRCLRP3_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP4_MASK                (0x10U)
+#define GPIO_DIRCLR_DIRCLRP4_SHIFT               (4U)
+/*! DIRCLRP4 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP4_SHIFT)) & GPIO_DIRCLR_DIRCLRP4_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP5_MASK                (0x20U)
+#define GPIO_DIRCLR_DIRCLRP5_SHIFT               (5U)
+/*! DIRCLRP5 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP5_SHIFT)) & GPIO_DIRCLR_DIRCLRP5_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP6_MASK                (0x40U)
+#define GPIO_DIRCLR_DIRCLRP6_SHIFT               (6U)
+/*! DIRCLRP6 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP6_SHIFT)) & GPIO_DIRCLR_DIRCLRP6_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP7_MASK                (0x80U)
+#define GPIO_DIRCLR_DIRCLRP7_SHIFT               (7U)
+/*! DIRCLRP7 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP7_SHIFT)) & GPIO_DIRCLR_DIRCLRP7_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP8_MASK                (0x100U)
+#define GPIO_DIRCLR_DIRCLRP8_SHIFT               (8U)
+/*! DIRCLRP8 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP8_SHIFT)) & GPIO_DIRCLR_DIRCLRP8_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP9_MASK                (0x200U)
+#define GPIO_DIRCLR_DIRCLRP9_SHIFT               (9U)
+/*! DIRCLRP9 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP9_SHIFT)) & GPIO_DIRCLR_DIRCLRP9_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP10_MASK               (0x400U)
+#define GPIO_DIRCLR_DIRCLRP10_SHIFT              (10U)
+/*! DIRCLRP10 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP10_SHIFT)) & GPIO_DIRCLR_DIRCLRP10_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP11_MASK               (0x800U)
+#define GPIO_DIRCLR_DIRCLRP11_SHIFT              (11U)
+/*! DIRCLRP11 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP11_SHIFT)) & GPIO_DIRCLR_DIRCLRP11_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP12_MASK               (0x1000U)
+#define GPIO_DIRCLR_DIRCLRP12_SHIFT              (12U)
+/*! DIRCLRP12 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP12_SHIFT)) & GPIO_DIRCLR_DIRCLRP12_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP13_MASK               (0x2000U)
+#define GPIO_DIRCLR_DIRCLRP13_SHIFT              (13U)
+/*! DIRCLRP13 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP13_SHIFT)) & GPIO_DIRCLR_DIRCLRP13_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP14_MASK               (0x4000U)
+#define GPIO_DIRCLR_DIRCLRP14_SHIFT              (14U)
+/*! DIRCLRP14 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP14_SHIFT)) & GPIO_DIRCLR_DIRCLRP14_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP15_MASK               (0x8000U)
+#define GPIO_DIRCLR_DIRCLRP15_SHIFT              (15U)
+/*! DIRCLRP15 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP15_SHIFT)) & GPIO_DIRCLR_DIRCLRP15_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP16_MASK               (0x10000U)
+#define GPIO_DIRCLR_DIRCLRP16_SHIFT              (16U)
+/*! DIRCLRP16 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP16_SHIFT)) & GPIO_DIRCLR_DIRCLRP16_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP17_MASK               (0x20000U)
+#define GPIO_DIRCLR_DIRCLRP17_SHIFT              (17U)
+/*! DIRCLRP17 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP17_SHIFT)) & GPIO_DIRCLR_DIRCLRP17_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP18_MASK               (0x40000U)
+#define GPIO_DIRCLR_DIRCLRP18_SHIFT              (18U)
+/*! DIRCLRP18 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP18_SHIFT)) & GPIO_DIRCLR_DIRCLRP18_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP19_MASK               (0x80000U)
+#define GPIO_DIRCLR_DIRCLRP19_SHIFT              (19U)
+/*! DIRCLRP19 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP19_SHIFT)) & GPIO_DIRCLR_DIRCLRP19_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP20_MASK               (0x100000U)
+#define GPIO_DIRCLR_DIRCLRP20_SHIFT              (20U)
+/*! DIRCLRP20 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP20_SHIFT)) & GPIO_DIRCLR_DIRCLRP20_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP21_MASK               (0x200000U)
+#define GPIO_DIRCLR_DIRCLRP21_SHIFT              (21U)
+/*! DIRCLRP21 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP21_SHIFT)) & GPIO_DIRCLR_DIRCLRP21_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP22_MASK               (0x400000U)
+#define GPIO_DIRCLR_DIRCLRP22_SHIFT              (22U)
+/*! DIRCLRP22 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP22_SHIFT)) & GPIO_DIRCLR_DIRCLRP22_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP23_MASK               (0x800000U)
+#define GPIO_DIRCLR_DIRCLRP23_SHIFT              (23U)
+/*! DIRCLRP23 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP23_SHIFT)) & GPIO_DIRCLR_DIRCLRP23_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP24_MASK               (0x1000000U)
+#define GPIO_DIRCLR_DIRCLRP24_SHIFT              (24U)
+/*! DIRCLRP24 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP24_SHIFT)) & GPIO_DIRCLR_DIRCLRP24_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP25_MASK               (0x2000000U)
+#define GPIO_DIRCLR_DIRCLRP25_SHIFT              (25U)
+/*! DIRCLRP25 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP25_SHIFT)) & GPIO_DIRCLR_DIRCLRP25_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP26_MASK               (0x4000000U)
+#define GPIO_DIRCLR_DIRCLRP26_SHIFT              (26U)
+/*! DIRCLRP26 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP26_SHIFT)) & GPIO_DIRCLR_DIRCLRP26_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP27_MASK               (0x8000000U)
+#define GPIO_DIRCLR_DIRCLRP27_SHIFT              (27U)
+/*! DIRCLRP27 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP27_SHIFT)) & GPIO_DIRCLR_DIRCLRP27_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP28_MASK               (0x10000000U)
+#define GPIO_DIRCLR_DIRCLRP28_SHIFT              (28U)
+/*! DIRCLRP28 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP28_SHIFT)) & GPIO_DIRCLR_DIRCLRP28_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP29_MASK               (0x20000000U)
+#define GPIO_DIRCLR_DIRCLRP29_SHIFT              (29U)
+/*! DIRCLRP29 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP29_SHIFT)) & GPIO_DIRCLR_DIRCLRP29_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP30_MASK               (0x40000000U)
+#define GPIO_DIRCLR_DIRCLRP30_SHIFT              (30U)
+/*! DIRCLRP30 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP30_SHIFT)) & GPIO_DIRCLR_DIRCLRP30_MASK)
+
+#define GPIO_DIRCLR_DIRCLRP31_MASK               (0x80000000U)
+#define GPIO_DIRCLR_DIRCLRP31_SHIFT              (31U)
+/*! DIRCLRP31 - Clear direction bits.
+ *  0b0..No operation
+ *  0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP31_SHIFT)) & GPIO_DIRCLR_DIRCLRP31_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT                        (2U)
+
+/*! @name DIRNOT - Port direction toggle */
+/*! @{ */
+
+#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
+/*! DIRNOTP - Toggle direction bits.
+ *  0b00000000000000000000000000000..No operation
+ *  0b00000000000000000000000000001..Toggles direction bit
+ */
+#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT                        (2U)
+
+/*! @name INTENA - Interrupt A enable control */
+/*! @{ */
+
+#define GPIO_INTENA_INT_EN0_MASK                 (0x1U)
+#define GPIO_INTENA_INT_EN0_SHIFT                (0U)
+/*! INT_EN0 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN0(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN0_SHIFT)) & GPIO_INTENA_INT_EN0_MASK)
+
+#define GPIO_INTENA_INT_EN1_MASK                 (0x2U)
+#define GPIO_INTENA_INT_EN1_SHIFT                (1U)
+/*! INT_EN1 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN1(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN1_SHIFT)) & GPIO_INTENA_INT_EN1_MASK)
+
+#define GPIO_INTENA_INT_EN2_MASK                 (0x4U)
+#define GPIO_INTENA_INT_EN2_SHIFT                (2U)
+/*! INT_EN2 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN2(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN2_SHIFT)) & GPIO_INTENA_INT_EN2_MASK)
+
+#define GPIO_INTENA_INT_EN3_MASK                 (0x8U)
+#define GPIO_INTENA_INT_EN3_SHIFT                (3U)
+/*! INT_EN3 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN3(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN3_SHIFT)) & GPIO_INTENA_INT_EN3_MASK)
+
+#define GPIO_INTENA_INT_EN4_MASK                 (0x10U)
+#define GPIO_INTENA_INT_EN4_SHIFT                (4U)
+/*! INT_EN4 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN4(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN4_SHIFT)) & GPIO_INTENA_INT_EN4_MASK)
+
+#define GPIO_INTENA_INT_EN5_MASK                 (0x20U)
+#define GPIO_INTENA_INT_EN5_SHIFT                (5U)
+/*! INT_EN5 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN5(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN5_SHIFT)) & GPIO_INTENA_INT_EN5_MASK)
+
+#define GPIO_INTENA_INT_EN6_MASK                 (0x40U)
+#define GPIO_INTENA_INT_EN6_SHIFT                (6U)
+/*! INT_EN6 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN6(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN6_SHIFT)) & GPIO_INTENA_INT_EN6_MASK)
+
+#define GPIO_INTENA_INT_EN7_MASK                 (0x80U)
+#define GPIO_INTENA_INT_EN7_SHIFT                (7U)
+/*! INT_EN7 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN7(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN7_SHIFT)) & GPIO_INTENA_INT_EN7_MASK)
+
+#define GPIO_INTENA_INT_EN8_MASK                 (0x100U)
+#define GPIO_INTENA_INT_EN8_SHIFT                (8U)
+/*! INT_EN8 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN8(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN8_SHIFT)) & GPIO_INTENA_INT_EN8_MASK)
+
+#define GPIO_INTENA_INT_EN9_MASK                 (0x200U)
+#define GPIO_INTENA_INT_EN9_SHIFT                (9U)
+/*! INT_EN9 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN9(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN9_SHIFT)) & GPIO_INTENA_INT_EN9_MASK)
+
+#define GPIO_INTENA_INT_EN10_MASK                (0x400U)
+#define GPIO_INTENA_INT_EN10_SHIFT               (10U)
+/*! INT_EN10 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN10(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN10_SHIFT)) & GPIO_INTENA_INT_EN10_MASK)
+
+#define GPIO_INTENA_INT_EN11_MASK                (0x800U)
+#define GPIO_INTENA_INT_EN11_SHIFT               (11U)
+/*! INT_EN11 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN11(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN11_SHIFT)) & GPIO_INTENA_INT_EN11_MASK)
+
+#define GPIO_INTENA_INT_EN12_MASK                (0x1000U)
+#define GPIO_INTENA_INT_EN12_SHIFT               (12U)
+/*! INT_EN12 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN12(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN12_SHIFT)) & GPIO_INTENA_INT_EN12_MASK)
+
+#define GPIO_INTENA_INT_EN13_MASK                (0x2000U)
+#define GPIO_INTENA_INT_EN13_SHIFT               (13U)
+/*! INT_EN13 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN13(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN13_SHIFT)) & GPIO_INTENA_INT_EN13_MASK)
+
+#define GPIO_INTENA_INT_EN14_MASK                (0x4000U)
+#define GPIO_INTENA_INT_EN14_SHIFT               (14U)
+/*! INT_EN14 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN14(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN14_SHIFT)) & GPIO_INTENA_INT_EN14_MASK)
+
+#define GPIO_INTENA_INT_EN15_MASK                (0x8000U)
+#define GPIO_INTENA_INT_EN15_SHIFT               (15U)
+/*! INT_EN15 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN15(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN15_SHIFT)) & GPIO_INTENA_INT_EN15_MASK)
+
+#define GPIO_INTENA_INT_EN16_MASK                (0x10000U)
+#define GPIO_INTENA_INT_EN16_SHIFT               (16U)
+/*! INT_EN16 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN16(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN16_SHIFT)) & GPIO_INTENA_INT_EN16_MASK)
+
+#define GPIO_INTENA_INT_EN17_MASK                (0x20000U)
+#define GPIO_INTENA_INT_EN17_SHIFT               (17U)
+/*! INT_EN17 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN17(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN17_SHIFT)) & GPIO_INTENA_INT_EN17_MASK)
+
+#define GPIO_INTENA_INT_EN18_MASK                (0x40000U)
+#define GPIO_INTENA_INT_EN18_SHIFT               (18U)
+/*! INT_EN18 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN18(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN18_SHIFT)) & GPIO_INTENA_INT_EN18_MASK)
+
+#define GPIO_INTENA_INT_EN19_MASK                (0x80000U)
+#define GPIO_INTENA_INT_EN19_SHIFT               (19U)
+/*! INT_EN19 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN19(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN19_SHIFT)) & GPIO_INTENA_INT_EN19_MASK)
+
+#define GPIO_INTENA_INT_EN20_MASK                (0x100000U)
+#define GPIO_INTENA_INT_EN20_SHIFT               (20U)
+/*! INT_EN20 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN20(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN20_SHIFT)) & GPIO_INTENA_INT_EN20_MASK)
+
+#define GPIO_INTENA_INT_EN21_MASK                (0x200000U)
+#define GPIO_INTENA_INT_EN21_SHIFT               (21U)
+/*! INT_EN21 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN21(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN21_SHIFT)) & GPIO_INTENA_INT_EN21_MASK)
+
+#define GPIO_INTENA_INT_EN22_MASK                (0x400000U)
+#define GPIO_INTENA_INT_EN22_SHIFT               (22U)
+/*! INT_EN22 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN22(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN22_SHIFT)) & GPIO_INTENA_INT_EN22_MASK)
+
+#define GPIO_INTENA_INT_EN23_MASK                (0x800000U)
+#define GPIO_INTENA_INT_EN23_SHIFT               (23U)
+/*! INT_EN23 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN23(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN23_SHIFT)) & GPIO_INTENA_INT_EN23_MASK)
+
+#define GPIO_INTENA_INT_EN24_MASK                (0x1000000U)
+#define GPIO_INTENA_INT_EN24_SHIFT               (24U)
+/*! INT_EN24 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN24(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN24_SHIFT)) & GPIO_INTENA_INT_EN24_MASK)
+
+#define GPIO_INTENA_INT_EN25_MASK                (0x2000000U)
+#define GPIO_INTENA_INT_EN25_SHIFT               (25U)
+/*! INT_EN25 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN25(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN25_SHIFT)) & GPIO_INTENA_INT_EN25_MASK)
+
+#define GPIO_INTENA_INT_EN26_MASK                (0x4000000U)
+#define GPIO_INTENA_INT_EN26_SHIFT               (26U)
+/*! INT_EN26 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN26(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN26_SHIFT)) & GPIO_INTENA_INT_EN26_MASK)
+
+#define GPIO_INTENA_INT_EN27_MASK                (0x8000000U)
+#define GPIO_INTENA_INT_EN27_SHIFT               (27U)
+/*! INT_EN27 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN27(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN27_SHIFT)) & GPIO_INTENA_INT_EN27_MASK)
+
+#define GPIO_INTENA_INT_EN28_MASK                (0x10000000U)
+#define GPIO_INTENA_INT_EN28_SHIFT               (28U)
+/*! INT_EN28 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN28(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN28_SHIFT)) & GPIO_INTENA_INT_EN28_MASK)
+
+#define GPIO_INTENA_INT_EN29_MASK                (0x20000000U)
+#define GPIO_INTENA_INT_EN29_SHIFT               (29U)
+/*! INT_EN29 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN29(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN29_SHIFT)) & GPIO_INTENA_INT_EN29_MASK)
+
+#define GPIO_INTENA_INT_EN30_MASK                (0x40000000U)
+#define GPIO_INTENA_INT_EN30_SHIFT               (30U)
+/*! INT_EN30 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN30(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN30_SHIFT)) & GPIO_INTENA_INT_EN30_MASK)
+
+#define GPIO_INTENA_INT_EN31_MASK                (0x80000000U)
+#define GPIO_INTENA_INT_EN31_SHIFT               (31U)
+/*! INT_EN31 - Interrupt A enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt A
+ *  0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN31(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN31_SHIFT)) & GPIO_INTENA_INT_EN31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTENA */
+#define GPIO_INTENA_COUNT                        (2U)
+
+/*! @name INTENB - Interrupt B enable control */
+/*! @{ */
+
+#define GPIO_INTENB_INT_EN0_MASK                 (0x1U)
+#define GPIO_INTENB_INT_EN0_SHIFT                (0U)
+/*! INT_EN0 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN0(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN0_SHIFT)) & GPIO_INTENB_INT_EN0_MASK)
+
+#define GPIO_INTENB_INT_EN1_MASK                 (0x2U)
+#define GPIO_INTENB_INT_EN1_SHIFT                (1U)
+/*! INT_EN1 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN1(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN1_SHIFT)) & GPIO_INTENB_INT_EN1_MASK)
+
+#define GPIO_INTENB_INT_EN2_MASK                 (0x4U)
+#define GPIO_INTENB_INT_EN2_SHIFT                (2U)
+/*! INT_EN2 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN2(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN2_SHIFT)) & GPIO_INTENB_INT_EN2_MASK)
+
+#define GPIO_INTENB_INT_EN3_MASK                 (0x8U)
+#define GPIO_INTENB_INT_EN3_SHIFT                (3U)
+/*! INT_EN3 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN3(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN3_SHIFT)) & GPIO_INTENB_INT_EN3_MASK)
+
+#define GPIO_INTENB_INT_EN4_MASK                 (0x10U)
+#define GPIO_INTENB_INT_EN4_SHIFT                (4U)
+/*! INT_EN4 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN4(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN4_SHIFT)) & GPIO_INTENB_INT_EN4_MASK)
+
+#define GPIO_INTENB_INT_EN5_MASK                 (0x20U)
+#define GPIO_INTENB_INT_EN5_SHIFT                (5U)
+/*! INT_EN5 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN5(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN5_SHIFT)) & GPIO_INTENB_INT_EN5_MASK)
+
+#define GPIO_INTENB_INT_EN6_MASK                 (0x40U)
+#define GPIO_INTENB_INT_EN6_SHIFT                (6U)
+/*! INT_EN6 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN6(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN6_SHIFT)) & GPIO_INTENB_INT_EN6_MASK)
+
+#define GPIO_INTENB_INT_EN7_MASK                 (0x80U)
+#define GPIO_INTENB_INT_EN7_SHIFT                (7U)
+/*! INT_EN7 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN7(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN7_SHIFT)) & GPIO_INTENB_INT_EN7_MASK)
+
+#define GPIO_INTENB_INT_EN8_MASK                 (0x100U)
+#define GPIO_INTENB_INT_EN8_SHIFT                (8U)
+/*! INT_EN8 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN8(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN8_SHIFT)) & GPIO_INTENB_INT_EN8_MASK)
+
+#define GPIO_INTENB_INT_EN9_MASK                 (0x200U)
+#define GPIO_INTENB_INT_EN9_SHIFT                (9U)
+/*! INT_EN9 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN9(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN9_SHIFT)) & GPIO_INTENB_INT_EN9_MASK)
+
+#define GPIO_INTENB_INT_EN10_MASK                (0x400U)
+#define GPIO_INTENB_INT_EN10_SHIFT               (10U)
+/*! INT_EN10 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN10(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN10_SHIFT)) & GPIO_INTENB_INT_EN10_MASK)
+
+#define GPIO_INTENB_INT_EN11_MASK                (0x800U)
+#define GPIO_INTENB_INT_EN11_SHIFT               (11U)
+/*! INT_EN11 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN11(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN11_SHIFT)) & GPIO_INTENB_INT_EN11_MASK)
+
+#define GPIO_INTENB_INT_EN12_MASK                (0x1000U)
+#define GPIO_INTENB_INT_EN12_SHIFT               (12U)
+/*! INT_EN12 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN12(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN12_SHIFT)) & GPIO_INTENB_INT_EN12_MASK)
+
+#define GPIO_INTENB_INT_EN13_MASK                (0x2000U)
+#define GPIO_INTENB_INT_EN13_SHIFT               (13U)
+/*! INT_EN13 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN13(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN13_SHIFT)) & GPIO_INTENB_INT_EN13_MASK)
+
+#define GPIO_INTENB_INT_EN14_MASK                (0x4000U)
+#define GPIO_INTENB_INT_EN14_SHIFT               (14U)
+/*! INT_EN14 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN14(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN14_SHIFT)) & GPIO_INTENB_INT_EN14_MASK)
+
+#define GPIO_INTENB_INT_EN15_MASK                (0x8000U)
+#define GPIO_INTENB_INT_EN15_SHIFT               (15U)
+/*! INT_EN15 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN15(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN15_SHIFT)) & GPIO_INTENB_INT_EN15_MASK)
+
+#define GPIO_INTENB_INT_EN16_MASK                (0x10000U)
+#define GPIO_INTENB_INT_EN16_SHIFT               (16U)
+/*! INT_EN16 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN16(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN16_SHIFT)) & GPIO_INTENB_INT_EN16_MASK)
+
+#define GPIO_INTENB_INT_EN17_MASK                (0x20000U)
+#define GPIO_INTENB_INT_EN17_SHIFT               (17U)
+/*! INT_EN17 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN17(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN17_SHIFT)) & GPIO_INTENB_INT_EN17_MASK)
+
+#define GPIO_INTENB_INT_EN18_MASK                (0x40000U)
+#define GPIO_INTENB_INT_EN18_SHIFT               (18U)
+/*! INT_EN18 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN18(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN18_SHIFT)) & GPIO_INTENB_INT_EN18_MASK)
+
+#define GPIO_INTENB_INT_EN19_MASK                (0x80000U)
+#define GPIO_INTENB_INT_EN19_SHIFT               (19U)
+/*! INT_EN19 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN19(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN19_SHIFT)) & GPIO_INTENB_INT_EN19_MASK)
+
+#define GPIO_INTENB_INT_EN20_MASK                (0x100000U)
+#define GPIO_INTENB_INT_EN20_SHIFT               (20U)
+/*! INT_EN20 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN20(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN20_SHIFT)) & GPIO_INTENB_INT_EN20_MASK)
+
+#define GPIO_INTENB_INT_EN21_MASK                (0x200000U)
+#define GPIO_INTENB_INT_EN21_SHIFT               (21U)
+/*! INT_EN21 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN21(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN21_SHIFT)) & GPIO_INTENB_INT_EN21_MASK)
+
+#define GPIO_INTENB_INT_EN22_MASK                (0x400000U)
+#define GPIO_INTENB_INT_EN22_SHIFT               (22U)
+/*! INT_EN22 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN22(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN22_SHIFT)) & GPIO_INTENB_INT_EN22_MASK)
+
+#define GPIO_INTENB_INT_EN23_MASK                (0x800000U)
+#define GPIO_INTENB_INT_EN23_SHIFT               (23U)
+/*! INT_EN23 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN23(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN23_SHIFT)) & GPIO_INTENB_INT_EN23_MASK)
+
+#define GPIO_INTENB_INT_EN24_MASK                (0x1000000U)
+#define GPIO_INTENB_INT_EN24_SHIFT               (24U)
+/*! INT_EN24 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN24(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN24_SHIFT)) & GPIO_INTENB_INT_EN24_MASK)
+
+#define GPIO_INTENB_INT_EN25_MASK                (0x2000000U)
+#define GPIO_INTENB_INT_EN25_SHIFT               (25U)
+/*! INT_EN25 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN25(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN25_SHIFT)) & GPIO_INTENB_INT_EN25_MASK)
+
+#define GPIO_INTENB_INT_EN26_MASK                (0x4000000U)
+#define GPIO_INTENB_INT_EN26_SHIFT               (26U)
+/*! INT_EN26 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN26(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN26_SHIFT)) & GPIO_INTENB_INT_EN26_MASK)
+
+#define GPIO_INTENB_INT_EN27_MASK                (0x8000000U)
+#define GPIO_INTENB_INT_EN27_SHIFT               (27U)
+/*! INT_EN27 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN27(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN27_SHIFT)) & GPIO_INTENB_INT_EN27_MASK)
+
+#define GPIO_INTENB_INT_EN28_MASK                (0x10000000U)
+#define GPIO_INTENB_INT_EN28_SHIFT               (28U)
+/*! INT_EN28 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN28(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN28_SHIFT)) & GPIO_INTENB_INT_EN28_MASK)
+
+#define GPIO_INTENB_INT_EN29_MASK                (0x20000000U)
+#define GPIO_INTENB_INT_EN29_SHIFT               (29U)
+/*! INT_EN29 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN29(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN29_SHIFT)) & GPIO_INTENB_INT_EN29_MASK)
+
+#define GPIO_INTENB_INT_EN30_MASK                (0x40000000U)
+#define GPIO_INTENB_INT_EN30_SHIFT               (30U)
+/*! INT_EN30 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN30(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN30_SHIFT)) & GPIO_INTENB_INT_EN30_MASK)
+
+#define GPIO_INTENB_INT_EN31_MASK                (0x80000000U)
+#define GPIO_INTENB_INT_EN31_SHIFT               (31U)
+/*! INT_EN31 - Interrupt B enable bits.
+ *  0b0..Pin does not contribute to GPIO interrupt B
+ *  0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN31(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN31_SHIFT)) & GPIO_INTENB_INT_EN31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTENB */
+#define GPIO_INTENB_COUNT                        (2U)
+
+/*! @name INTPOL - Interupt polarity control */
+/*! @{ */
+
+#define GPIO_INTPOL_POL_CTL0_MASK                (0x1U)
+#define GPIO_INTPOL_POL_CTL0_SHIFT               (0U)
+/*! POL_CTL0 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL0_SHIFT)) & GPIO_INTPOL_POL_CTL0_MASK)
+
+#define GPIO_INTPOL_POL_CTL1_MASK                (0x2U)
+#define GPIO_INTPOL_POL_CTL1_SHIFT               (1U)
+/*! POL_CTL1 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL1_SHIFT)) & GPIO_INTPOL_POL_CTL1_MASK)
+
+#define GPIO_INTPOL_POL_CTL2_MASK                (0x4U)
+#define GPIO_INTPOL_POL_CTL2_SHIFT               (2U)
+/*! POL_CTL2 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL2_SHIFT)) & GPIO_INTPOL_POL_CTL2_MASK)
+
+#define GPIO_INTPOL_POL_CTL3_MASK                (0x8U)
+#define GPIO_INTPOL_POL_CTL3_SHIFT               (3U)
+/*! POL_CTL3 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL3_SHIFT)) & GPIO_INTPOL_POL_CTL3_MASK)
+
+#define GPIO_INTPOL_POL_CTL4_MASK                (0x10U)
+#define GPIO_INTPOL_POL_CTL4_SHIFT               (4U)
+/*! POL_CTL4 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL4_SHIFT)) & GPIO_INTPOL_POL_CTL4_MASK)
+
+#define GPIO_INTPOL_POL_CTL5_MASK                (0x20U)
+#define GPIO_INTPOL_POL_CTL5_SHIFT               (5U)
+/*! POL_CTL5 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL5_SHIFT)) & GPIO_INTPOL_POL_CTL5_MASK)
+
+#define GPIO_INTPOL_POL_CTL6_MASK                (0x40U)
+#define GPIO_INTPOL_POL_CTL6_SHIFT               (6U)
+/*! POL_CTL6 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL6_SHIFT)) & GPIO_INTPOL_POL_CTL6_MASK)
+
+#define GPIO_INTPOL_POL_CTL7_MASK                (0x80U)
+#define GPIO_INTPOL_POL_CTL7_SHIFT               (7U)
+/*! POL_CTL7 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL7_SHIFT)) & GPIO_INTPOL_POL_CTL7_MASK)
+
+#define GPIO_INTPOL_POL_CTL8_MASK                (0x100U)
+#define GPIO_INTPOL_POL_CTL8_SHIFT               (8U)
+/*! POL_CTL8 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL8_SHIFT)) & GPIO_INTPOL_POL_CTL8_MASK)
+
+#define GPIO_INTPOL_POL_CTL9_MASK                (0x200U)
+#define GPIO_INTPOL_POL_CTL9_SHIFT               (9U)
+/*! POL_CTL9 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL9_SHIFT)) & GPIO_INTPOL_POL_CTL9_MASK)
+
+#define GPIO_INTPOL_POL_CTL10_MASK               (0x400U)
+#define GPIO_INTPOL_POL_CTL10_SHIFT              (10U)
+/*! POL_CTL10 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL10_SHIFT)) & GPIO_INTPOL_POL_CTL10_MASK)
+
+#define GPIO_INTPOL_POL_CTL11_MASK               (0x800U)
+#define GPIO_INTPOL_POL_CTL11_SHIFT              (11U)
+/*! POL_CTL11 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL11_SHIFT)) & GPIO_INTPOL_POL_CTL11_MASK)
+
+#define GPIO_INTPOL_POL_CTL12_MASK               (0x1000U)
+#define GPIO_INTPOL_POL_CTL12_SHIFT              (12U)
+/*! POL_CTL12 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL12_SHIFT)) & GPIO_INTPOL_POL_CTL12_MASK)
+
+#define GPIO_INTPOL_POL_CTL13_MASK               (0x2000U)
+#define GPIO_INTPOL_POL_CTL13_SHIFT              (13U)
+/*! POL_CTL13 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL13_SHIFT)) & GPIO_INTPOL_POL_CTL13_MASK)
+
+#define GPIO_INTPOL_POL_CTL14_MASK               (0x4000U)
+#define GPIO_INTPOL_POL_CTL14_SHIFT              (14U)
+/*! POL_CTL14 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL14_SHIFT)) & GPIO_INTPOL_POL_CTL14_MASK)
+
+#define GPIO_INTPOL_POL_CTL15_MASK               (0x8000U)
+#define GPIO_INTPOL_POL_CTL15_SHIFT              (15U)
+/*! POL_CTL15 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL15_SHIFT)) & GPIO_INTPOL_POL_CTL15_MASK)
+
+#define GPIO_INTPOL_POL_CTL16_MASK               (0x10000U)
+#define GPIO_INTPOL_POL_CTL16_SHIFT              (16U)
+/*! POL_CTL16 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL16_SHIFT)) & GPIO_INTPOL_POL_CTL16_MASK)
+
+#define GPIO_INTPOL_POL_CTL17_MASK               (0x20000U)
+#define GPIO_INTPOL_POL_CTL17_SHIFT              (17U)
+/*! POL_CTL17 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL17_SHIFT)) & GPIO_INTPOL_POL_CTL17_MASK)
+
+#define GPIO_INTPOL_POL_CTL18_MASK               (0x40000U)
+#define GPIO_INTPOL_POL_CTL18_SHIFT              (18U)
+/*! POL_CTL18 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL18_SHIFT)) & GPIO_INTPOL_POL_CTL18_MASK)
+
+#define GPIO_INTPOL_POL_CTL19_MASK               (0x80000U)
+#define GPIO_INTPOL_POL_CTL19_SHIFT              (19U)
+/*! POL_CTL19 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL19_SHIFT)) & GPIO_INTPOL_POL_CTL19_MASK)
+
+#define GPIO_INTPOL_POL_CTL20_MASK               (0x100000U)
+#define GPIO_INTPOL_POL_CTL20_SHIFT              (20U)
+/*! POL_CTL20 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL20_SHIFT)) & GPIO_INTPOL_POL_CTL20_MASK)
+
+#define GPIO_INTPOL_POL_CTL21_MASK               (0x200000U)
+#define GPIO_INTPOL_POL_CTL21_SHIFT              (21U)
+/*! POL_CTL21 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL21_SHIFT)) & GPIO_INTPOL_POL_CTL21_MASK)
+
+#define GPIO_INTPOL_POL_CTL22_MASK               (0x400000U)
+#define GPIO_INTPOL_POL_CTL22_SHIFT              (22U)
+/*! POL_CTL22 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL22_SHIFT)) & GPIO_INTPOL_POL_CTL22_MASK)
+
+#define GPIO_INTPOL_POL_CTL23_MASK               (0x800000U)
+#define GPIO_INTPOL_POL_CTL23_SHIFT              (23U)
+/*! POL_CTL23 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL23_SHIFT)) & GPIO_INTPOL_POL_CTL23_MASK)
+
+#define GPIO_INTPOL_POL_CTL24_MASK               (0x1000000U)
+#define GPIO_INTPOL_POL_CTL24_SHIFT              (24U)
+/*! POL_CTL24 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL24_SHIFT)) & GPIO_INTPOL_POL_CTL24_MASK)
+
+#define GPIO_INTPOL_POL_CTL25_MASK               (0x2000000U)
+#define GPIO_INTPOL_POL_CTL25_SHIFT              (25U)
+/*! POL_CTL25 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL25_SHIFT)) & GPIO_INTPOL_POL_CTL25_MASK)
+
+#define GPIO_INTPOL_POL_CTL26_MASK               (0x4000000U)
+#define GPIO_INTPOL_POL_CTL26_SHIFT              (26U)
+/*! POL_CTL26 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL26_SHIFT)) & GPIO_INTPOL_POL_CTL26_MASK)
+
+#define GPIO_INTPOL_POL_CTL27_MASK               (0x8000000U)
+#define GPIO_INTPOL_POL_CTL27_SHIFT              (27U)
+/*! POL_CTL27 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL27_SHIFT)) & GPIO_INTPOL_POL_CTL27_MASK)
+
+#define GPIO_INTPOL_POL_CTL28_MASK               (0x10000000U)
+#define GPIO_INTPOL_POL_CTL28_SHIFT              (28U)
+/*! POL_CTL28 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL28_SHIFT)) & GPIO_INTPOL_POL_CTL28_MASK)
+
+#define GPIO_INTPOL_POL_CTL29_MASK               (0x20000000U)
+#define GPIO_INTPOL_POL_CTL29_SHIFT              (29U)
+/*! POL_CTL29 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL29_SHIFT)) & GPIO_INTPOL_POL_CTL29_MASK)
+
+#define GPIO_INTPOL_POL_CTL30_MASK               (0x40000000U)
+#define GPIO_INTPOL_POL_CTL30_SHIFT              (30U)
+/*! POL_CTL30 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL30_SHIFT)) & GPIO_INTPOL_POL_CTL30_MASK)
+
+#define GPIO_INTPOL_POL_CTL31_MASK               (0x80000000U)
+#define GPIO_INTPOL_POL_CTL31_SHIFT              (31U)
+/*! POL_CTL31 - Polarity control for each pin
+ *  0b0..High level or rising edge triggered
+ *  0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL31_SHIFT)) & GPIO_INTPOL_POL_CTL31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTPOL */
+#define GPIO_INTPOL_COUNT                        (2U)
+
+/*! @name INTEDG - Interrupt edge select */
+/*! @{ */
+
+#define GPIO_INTEDG_EDGE0_MASK                   (0x1U)
+#define GPIO_INTEDG_EDGE0_SHIFT                  (0U)
+/*! EDGE0 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE0(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE0_SHIFT)) & GPIO_INTEDG_EDGE0_MASK)
+
+#define GPIO_INTEDG_EDGE1_MASK                   (0x2U)
+#define GPIO_INTEDG_EDGE1_SHIFT                  (1U)
+/*! EDGE1 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE1(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE1_SHIFT)) & GPIO_INTEDG_EDGE1_MASK)
+
+#define GPIO_INTEDG_EDGE2_MASK                   (0x4U)
+#define GPIO_INTEDG_EDGE2_SHIFT                  (2U)
+/*! EDGE2 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE2(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE2_SHIFT)) & GPIO_INTEDG_EDGE2_MASK)
+
+#define GPIO_INTEDG_EDGE3_MASK                   (0x8U)
+#define GPIO_INTEDG_EDGE3_SHIFT                  (3U)
+/*! EDGE3 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE3(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE3_SHIFT)) & GPIO_INTEDG_EDGE3_MASK)
+
+#define GPIO_INTEDG_EDGE4_MASK                   (0x10U)
+#define GPIO_INTEDG_EDGE4_SHIFT                  (4U)
+/*! EDGE4 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE4(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE4_SHIFT)) & GPIO_INTEDG_EDGE4_MASK)
+
+#define GPIO_INTEDG_EDGE5_MASK                   (0x20U)
+#define GPIO_INTEDG_EDGE5_SHIFT                  (5U)
+/*! EDGE5 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE5(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE5_SHIFT)) & GPIO_INTEDG_EDGE5_MASK)
+
+#define GPIO_INTEDG_EDGE6_MASK                   (0x40U)
+#define GPIO_INTEDG_EDGE6_SHIFT                  (6U)
+/*! EDGE6 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE6(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE6_SHIFT)) & GPIO_INTEDG_EDGE6_MASK)
+
+#define GPIO_INTEDG_EDGE7_MASK                   (0x80U)
+#define GPIO_INTEDG_EDGE7_SHIFT                  (7U)
+/*! EDGE7 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE7(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE7_SHIFT)) & GPIO_INTEDG_EDGE7_MASK)
+
+#define GPIO_INTEDG_EDGE8_MASK                   (0x100U)
+#define GPIO_INTEDG_EDGE8_SHIFT                  (8U)
+/*! EDGE8 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE8(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE8_SHIFT)) & GPIO_INTEDG_EDGE8_MASK)
+
+#define GPIO_INTEDG_EDGE9_MASK                   (0x200U)
+#define GPIO_INTEDG_EDGE9_SHIFT                  (9U)
+/*! EDGE9 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE9(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE9_SHIFT)) & GPIO_INTEDG_EDGE9_MASK)
+
+#define GPIO_INTEDG_EDGE10_MASK                  (0x400U)
+#define GPIO_INTEDG_EDGE10_SHIFT                 (10U)
+/*! EDGE10 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE10(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE10_SHIFT)) & GPIO_INTEDG_EDGE10_MASK)
+
+#define GPIO_INTEDG_EDGE11_MASK                  (0x800U)
+#define GPIO_INTEDG_EDGE11_SHIFT                 (11U)
+/*! EDGE11 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE11(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE11_SHIFT)) & GPIO_INTEDG_EDGE11_MASK)
+
+#define GPIO_INTEDG_EDGE12_MASK                  (0x1000U)
+#define GPIO_INTEDG_EDGE12_SHIFT                 (12U)
+/*! EDGE12 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE12(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE12_SHIFT)) & GPIO_INTEDG_EDGE12_MASK)
+
+#define GPIO_INTEDG_EDGE13_MASK                  (0x2000U)
+#define GPIO_INTEDG_EDGE13_SHIFT                 (13U)
+/*! EDGE13 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE13(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE13_SHIFT)) & GPIO_INTEDG_EDGE13_MASK)
+
+#define GPIO_INTEDG_EDGE14_MASK                  (0x4000U)
+#define GPIO_INTEDG_EDGE14_SHIFT                 (14U)
+/*! EDGE14 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE14(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE14_SHIFT)) & GPIO_INTEDG_EDGE14_MASK)
+
+#define GPIO_INTEDG_EDGE15_MASK                  (0x8000U)
+#define GPIO_INTEDG_EDGE15_SHIFT                 (15U)
+/*! EDGE15 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE15(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE15_SHIFT)) & GPIO_INTEDG_EDGE15_MASK)
+
+#define GPIO_INTEDG_EDGE16_MASK                  (0x10000U)
+#define GPIO_INTEDG_EDGE16_SHIFT                 (16U)
+/*! EDGE16 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE16(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE16_SHIFT)) & GPIO_INTEDG_EDGE16_MASK)
+
+#define GPIO_INTEDG_EDGE17_MASK                  (0x20000U)
+#define GPIO_INTEDG_EDGE17_SHIFT                 (17U)
+/*! EDGE17 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE17(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE17_SHIFT)) & GPIO_INTEDG_EDGE17_MASK)
+
+#define GPIO_INTEDG_EDGE18_MASK                  (0x40000U)
+#define GPIO_INTEDG_EDGE18_SHIFT                 (18U)
+/*! EDGE18 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE18(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE18_SHIFT)) & GPIO_INTEDG_EDGE18_MASK)
+
+#define GPIO_INTEDG_EDGE19_MASK                  (0x80000U)
+#define GPIO_INTEDG_EDGE19_SHIFT                 (19U)
+/*! EDGE19 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE19(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE19_SHIFT)) & GPIO_INTEDG_EDGE19_MASK)
+
+#define GPIO_INTEDG_EDGE20_MASK                  (0x100000U)
+#define GPIO_INTEDG_EDGE20_SHIFT                 (20U)
+/*! EDGE20 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE20(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE20_SHIFT)) & GPIO_INTEDG_EDGE20_MASK)
+
+#define GPIO_INTEDG_EDGE21_MASK                  (0x200000U)
+#define GPIO_INTEDG_EDGE21_SHIFT                 (21U)
+/*! EDGE21 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE21(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE21_SHIFT)) & GPIO_INTEDG_EDGE21_MASK)
+
+#define GPIO_INTEDG_EDGE22_MASK                  (0x400000U)
+#define GPIO_INTEDG_EDGE22_SHIFT                 (22U)
+/*! EDGE22 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE22(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE22_SHIFT)) & GPIO_INTEDG_EDGE22_MASK)
+
+#define GPIO_INTEDG_EDGE23_MASK                  (0x800000U)
+#define GPIO_INTEDG_EDGE23_SHIFT                 (23U)
+/*! EDGE23 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE23(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE23_SHIFT)) & GPIO_INTEDG_EDGE23_MASK)
+
+#define GPIO_INTEDG_EDGE24_MASK                  (0x1000000U)
+#define GPIO_INTEDG_EDGE24_SHIFT                 (24U)
+/*! EDGE24 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE24(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE24_SHIFT)) & GPIO_INTEDG_EDGE24_MASK)
+
+#define GPIO_INTEDG_EDGE25_MASK                  (0x2000000U)
+#define GPIO_INTEDG_EDGE25_SHIFT                 (25U)
+/*! EDGE25 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE25(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE25_SHIFT)) & GPIO_INTEDG_EDGE25_MASK)
+
+#define GPIO_INTEDG_EDGE26_MASK                  (0x4000000U)
+#define GPIO_INTEDG_EDGE26_SHIFT                 (26U)
+/*! EDGE26 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE26(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE26_SHIFT)) & GPIO_INTEDG_EDGE26_MASK)
+
+#define GPIO_INTEDG_EDGE27_MASK                  (0x8000000U)
+#define GPIO_INTEDG_EDGE27_SHIFT                 (27U)
+/*! EDGE27 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE27(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE27_SHIFT)) & GPIO_INTEDG_EDGE27_MASK)
+
+#define GPIO_INTEDG_EDGE28_MASK                  (0x10000000U)
+#define GPIO_INTEDG_EDGE28_SHIFT                 (28U)
+/*! EDGE28 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE28(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE28_SHIFT)) & GPIO_INTEDG_EDGE28_MASK)
+
+#define GPIO_INTEDG_EDGE29_MASK                  (0x20000000U)
+#define GPIO_INTEDG_EDGE29_SHIFT                 (29U)
+/*! EDGE29 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE29(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE29_SHIFT)) & GPIO_INTEDG_EDGE29_MASK)
+
+#define GPIO_INTEDG_EDGE30_MASK                  (0x40000000U)
+#define GPIO_INTEDG_EDGE30_SHIFT                 (30U)
+/*! EDGE30 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE30(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE30_SHIFT)) & GPIO_INTEDG_EDGE30_MASK)
+
+#define GPIO_INTEDG_EDGE31_MASK                  (0x80000000U)
+#define GPIO_INTEDG_EDGE31_SHIFT                 (31U)
+/*! EDGE31 - Edge or level mode select bits.
+ *  0b0..Level mode
+ *  0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE31(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE31_SHIFT)) & GPIO_INTEDG_EDGE31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTEDG */
+#define GPIO_INTEDG_COUNT                        (2U)
+
+/*! @name INTSTATA - Interrupt status for interrupt A */
+/*! @{ */
+
+#define GPIO_INTSTATA_STATUS_MASK                (0xFFFFFFFFU)
+#define GPIO_INTSTATA_STATUS_SHIFT               (0U)
+/*! STATUS - Interrupt status. */
+#define GPIO_INTSTATA_STATUS(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATA_STATUS_SHIFT)) & GPIO_INTSTATA_STATUS_MASK)
+/*! @} */
+
+/* The count of GPIO_INTSTATA */
+#define GPIO_INTSTATA_COUNT                      (2U)
+
+/*! @name INTSTATB - Interrupt status for interrupt B */
+/*! @{ */
+
+#define GPIO_INTSTATB_STATUS_MASK                (0xFFFFFFFFU)
+#define GPIO_INTSTATB_STATUS_SHIFT               (0U)
+/*! STATUS - Interrupt status */
+#define GPIO_INTSTATB_STATUS(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATB_STATUS_SHIFT)) & GPIO_INTSTATB_STATUS_MASK)
+/*! @} */
+
+/* The count of GPIO_INTSTATB */
+#define GPIO_INTSTATB_COUNT                      (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral GPIO base address */
+  #define GPIO_BASE                                (0x50100000u)
+  /** Peripheral GPIO base address */
+  #define GPIO_BASE_NS                             (0x40100000u)
+  /** Peripheral GPIO base pointer */
+  #define GPIO                                     ((GPIO_Type *)GPIO_BASE)
+  /** Peripheral GPIO base pointer */
+  #define GPIO_NS                                  ((GPIO_Type *)GPIO_BASE_NS)
+  /** Peripheral SECGPIO base address */
+  #define SECGPIO_BASE                             (0x50154000u)
+  /** Peripheral SECGPIO base address */
+  #define SECGPIO_BASE_NS                          (0x40154000u)
+  /** Peripheral SECGPIO base pointer */
+  #define SECGPIO                                  ((GPIO_Type *)SECGPIO_BASE)
+  /** Peripheral SECGPIO base pointer */
+  #define SECGPIO_NS                               ((GPIO_Type *)SECGPIO_BASE_NS)
+  /** Array initializer of GPIO peripheral base addresses */
+  #define GPIO_BASE_ADDRS                          { GPIO_BASE, SECGPIO_BASE }
+  /** Array initializer of GPIO peripheral base pointers */
+  #define GPIO_BASE_PTRS                           { GPIO, SECGPIO }
+  /** Array initializer of GPIO peripheral base addresses */
+  #define GPIO_BASE_ADDRS_NS                       { GPIO_BASE_NS, SECGPIO_BASE_NS }
+  /** Array initializer of GPIO peripheral base pointers */
+  #define GPIO_BASE_PTRS_NS                        { GPIO_NS, SECGPIO_NS }
+#else
+  /** Peripheral GPIO base address */
+  #define GPIO_BASE                                (0x40100000u)
+  /** Peripheral GPIO base pointer */
+  #define GPIO                                     ((GPIO_Type *)GPIO_BASE)
+  /** Peripheral SECGPIO base address */
+  #define SECGPIO_BASE                             (0x40154000u)
+  /** Peripheral SECGPIO base pointer */
+  #define SECGPIO                                  ((GPIO_Type *)SECGPIO_BASE)
+  /** Array initializer of GPIO peripheral base addresses */
+  #define GPIO_BASE_ADDRS                          { GPIO_BASE, SECGPIO_BASE }
+  /** Array initializer of GPIO peripheral base pointers */
+  #define GPIO_BASE_PTRS                           { GPIO, SECGPIO }
+#endif
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2048];
+  __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x800 */
+  __IO uint32_t STAT;                              /**< Status Register, offset: 0x804 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set Register, offset: 0x808 */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear Register, offset: 0x80C */
+  __IO uint32_t TIMEOUT;                           /**< Time-out Register, offset: 0x810 */
+  __IO uint32_t CLKDIV;                            /**< Clock Divider Register, offset: 0x814 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status Register, offset: 0x818 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t MSTCTL;                            /**< Master Control Register, offset: 0x820 */
+  __IO uint32_t MSTTIME;                           /**< Master Timing Register, offset: 0x824 */
+  __IO uint32_t MSTDAT;                            /**< Master Data Register, offset: 0x828 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t SLVCTL;                            /**< Slave Control Register, offset: 0x840 */
+  __IO uint32_t SLVDAT;                            /**< Slave Data Register, offset: 0x844 */
+  __IO uint32_t SLVADR[4];                         /**< Slave Address Register, array offset: 0x848, array step: 0x4 */
+  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for Address 0 Register, offset: 0x858 */
+       uint8_t RESERVED_3[36];
+  __I  uint32_t MONRXDAT;                          /**< Monitor Receiver Data Register, offset: 0x880 */
+       uint8_t RESERVED_4[1912];
+  __I  uint32_t ID;                                /**< Peripheral Identification Register, offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration Register */
+/*! @{ */
+
+#define I2C_CFG_MSTEN_MASK                       (0x1U)
+#define I2C_CFG_MSTEN_SHIFT                      (0U)
+/*! MSTEN - Master Enable
+ *  0b0..Disabled. The I2C Master function is disabled. When disabled, the Master configuration settings are not
+ *       changed, but the Master function is internally reset.
+ *  0b1..Enabled. The I2C Master function is enabled.
+ */
+#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+
+#define I2C_CFG_SLVEN_MASK                       (0x2U)
+#define I2C_CFG_SLVEN_SHIFT                      (1U)
+/*! SLVEN - Slave Enable
+ *  0b0..Disabled. The I2C slave function is disabled. When disabled, the Slave configuration settings are not
+ *       changed, but the Slave function is internally reset.
+ *  0b1..Enabled. The I2C slave function is enabled.
+ */
+#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+
+#define I2C_CFG_MONEN_MASK                       (0x4U)
+#define I2C_CFG_MONEN_SHIFT                      (2U)
+/*! MONEN - Monitor Enable
+ *  0b0..Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function configuration
+ *       settings are not changed, but the Monitor function is internally reset.
+ *  0b1..Enabled. The I2C Monitor function is enabled.
+ */
+#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+
+#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
+/*! TIMEOUTEN - I2C bus Time-out Enable
+ *  0b0..Disabled. The time-out function is disabled. When disabled, the time-out function is internally reset.
+ *  0b1..Enabled. The time-out function is enabled. Both types of time-out flags will be generated and will cause
+ *       interrupts if those flags are enabled. Typically, only one time-out flag will be used in a system.
+ */
+#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+
+#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
+/*! MONCLKSTR - Monitor function Clock Stretching
+ *  0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
+ *       to read data provided by the Monitor function before it (the data) is overwritten. This mode can be used
+ *       when non-invasive monitoring is critical.
+ *  0b1..Enabled. The Monitor function will perform clock stretching, to ensure that the software or DMA can read
+ *       all incoming data supplied by the Monitor function.
+ */
+#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+
+#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
+/*! HSCAPABLE - High Speed mode Capable enable
+ *  0b0..Fast mode Plus enable
+ *  0b1..High Speed mode enable
+ */
+#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+/*! @} */
+
+/*! @name STAT - Status Register */
+/*! @{ */
+
+#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT                (0U)
+/*! MSTPENDING - Master Pending
+ *  0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
+ *  0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
+ *       idle state, then the master is waiting to receive or transmit data, or is waiting for the NACK bit.
+ */
+#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+
+#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
+/*! MSTSTATE - Master State code
+ *  0b000..Idle. The Master function is available to be used for a new transaction.
+ *  0b001..Receive ready. Received data is available (in Master Receiver mode). Address plus Read was previously sent and Acknowledged by a slave.
+ *  0b010..Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Write was previously sent and Acknowledged by a slave.
+ *  0b011..NACK Address. Slave NACKed address.
+ *  0b100..NACK Data. Slave NACKed transmitted data.
+ */
+#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+
+#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag
+ *  0b0..No Arbitration Loss has occurred
+ *  0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
+ *       function has already stopped driving the bus and has gone into an idle state. Software can respond by doing
+ *       nothing, or by sending a Start (to attempt to gain control of the bus when the bus next becomes idle).
+ */
+#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+
+#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag
+ *  0b0..No Start/Stop Error has occurred.
+ *  0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when Start
+ *       or Stop is not allowed by the I2C specification. The Master interface has stopped driving the bus and
+ *       gone into an idle state; no action is required. A request for a Start could be made, or software could
+ *       attempt to make sure that the bus has not stalled.
+ */
+#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+
+#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT                (8U)
+/*! SLVPENDING - Slave Pending
+ *  0b0..In progress. The Slave function does not currently need software service.
+ *  0b1..Pending. The Slave function needs software service. Information about what is needed is in the Slave state field (SLVSTATE).
+ */
+#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+
+#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
+/*! SLVSTATE - Slave State
+ *  0b00..Slave address. Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware.
+ *  0b01..Slave receive. Received data is available (in Slave Receiver mode).
+ *  0b10..Slave transmit. Data can be transmitted (in Slave Transmitter mode).
+ *  0b11..Reserved
+ */
+#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+
+#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
+/*! SLVNOTSTR - Slave Not Stretching
+ *  0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepmode cannot be entered at this time.
+ *  0b1..Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep mode can be entered at this time.
+ */
+#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+
+#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT                    (12U)
+/*! SLVIDX - Slave address match Index T
+ *  0b00..Address 0. Slave address 0 was matched.
+ *  0b01..Address 1. Slave address 1 was matched.
+ *  0b10..Address 2. Slave address 2 was matched.
+ *  0b11..Address 3. Slave address 3 was matched.
+ */
+#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+
+#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT                    (14U)
+/*! SLVSEL - Slave selected flag
+ *  0b0..Not selected. The Slave function is not currently selected.
+ *  0b1..Selected. The Slave function is currently selected.
+ */
+#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+
+#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
+/*! SLVDESEL - Slave Deselected flag
+ *  0b0..Not deselected. The Slave function has not become deselected. This does not mean that the Slave is
+ *       currently selected. That information is in the SLVSEL flag.
+ *  0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
+ *       changing from 1 to 0. See SLVSEL for details about when that event occurs.
+ */
+#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+
+#define I2C_STAT_MONRDY_MASK                     (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT                    (16U)
+/*! MONRDY - Monitor Ready
+ *  0b0..No data. The Monitor function does not currently have data available.
+ *  0b1..Data waiting. The Monitor function has data waiting to be read.
+ */
+#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+
+#define I2C_STAT_MONOV_MASK                      (0x20000U)
+#define I2C_STAT_MONOV_SHIFT                     (17U)
+/*! MONOV - Monitor Overflow flag
+ *  0b0..No overrun. Monitor data has not overrun.
+ *  0b1..Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor clock stretching
+ *       not enabled via the CFG[MONCLKSTR] bit. Writing 1 to MONOV bit clears the MONOV flag.
+ */
+#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+
+#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
+/*! MONACTIVE - Monitor Active flag
+ *  0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
+ *  0b1..Active. The Monitor function considers the I2C bus to be active.
+ */
+#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+
+#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT                   (19U)
+/*! MONIDLE - Monitor Idle flag
+ *  0b0..Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software.
+ *  0b1..Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was cleared by software.
+ */
+#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+
+#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag
+ *  0b0..No time-out. I2C bus events have not caused a time-out.
+ *  0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
+ */
+#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+
+#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag
+ *  0b0..No time-out. SCL low time has not caused a time-out.
+ *  0b1..Time-out. SCL low time has caused a time-out.
+ */
+#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Set Register */
+/*! @{ */
+
+#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
+/*! MSTPENDINGEN - Master Pending interrupt Enable
+ *  0b0..Disabled. The MstPending interrupt is disabled.
+ *  0b1..Enabled. The MstPending interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+
+#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
+/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable
+ *  0b0..Disabled. The MstArbLoss interrupt is disabled.
+ *  0b1..Enabled. The MstArbLoss interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+
+#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
+/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable
+ *  0b0..Disabled. The MstStStpErr interrupt is disabled.
+ *  0b1..Enabled. The MstStStpErr interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+
+#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
+/*! SLVPENDINGEN - Slave Pending interrupt Enable
+ *  0b0..Disabled. The SlvPending interrupt is disabled.
+ *  0b1..Enabled. The SlvPending interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+
+#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
+/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable
+ *  0b0..Disabled. The SlvNotStr interrupt is disabled.
+ *  0b1..Enabled. The SlvNotStr interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+
+#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
+/*! SLVDESELEN - Slave Deselect interrupt Enable
+ *  0b0..Disabled. The SlvDeSel interrupt is disabled.
+ *  0b1..Enabled. The SlvDeSel interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+
+#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
+/*! MONRDYEN - Monitor data Ready interrupt Enable
+ *  0b0..Disabled. The MonRdy interrupt is disabled.
+ *  0b1..Enabled. The MonRdy interrupt is enabled.
+ */
+#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+
+#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
+/*! MONOVEN - Monitor Overrun interrupt Enable
+ *  0b0..Disabled. The MonOv interrupt is disabled.
+ *  0b1..Enabled. The MonOv interrupt is enabled.
+ */
+#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+
+#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
+/*! MONIDLEEN - Monitor Idle interrupt Enable
+ *  0b0..Disabled. The MonIdle interrupt is disabled.
+ *  0b1..Enabled. The MonIdle interrupt is enabled.
+ */
+#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
+/*! EVENTTIMEOUTEN - Event Time-out interrupt Enable
+ *  0b0..Disabled. The Event time-out interrupt is disabled.
+ *  0b1..Enabled. The Event time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
+/*! SCLTIMEOUTEN - SCL Time-out interrupt Enable
+ *  0b0..Disabled. The SCL time-out interrupt is disabled.
+ *  0b1..Enabled. The SCL time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear Register */
+/*! @{ */
+
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
+/*! MSTPENDINGCLR - Master Pending interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
+/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
+/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
+/*! SLVPENDINGCLR - Slave Pending interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
+/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+
+#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
+/*! SLVDESELCLR - Slave Deselect interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+
+#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
+/*! MONRDYCLR - Monitor data Ready interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+
+#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
+/*! MONOVCLR - Monitor Overrun interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+
+#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
+/*! MONIDLECLR - Monitor Idle interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
+/*! EVENTTIMEOUTCLR - Event time-out interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
+/*! SCLTIMEOUTCLR - SCL time-out interrupt clear
+ *  0b0..No effect on interrupt
+ *  0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+/*! @} */
+
+/*! @name TIMEOUT - Time-out Register */
+/*! @{ */
+
+#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
+/*! TOMIN - Time-out time value, the bottom 4 bits */
+#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+
+#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT                     (4U)
+/*! TO - Time-out time value
+ *  0b000000000000..A time-out will occur after 16 counts of the I2C function clock.
+ *  0b000000000001..A time-out will occur after 32 counts of the I2C function clock.
+ *  0b111111111111..A time-out will occur after 65,536 counts of the I2C function clock.
+ */
+#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock Divider Register */
+/*! @{ */
+
+#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
+/*! DIVVAL - Divider Value
+ *  0b0000000000000000..FCLK is used directly by the I2C.
+ *  0b0000000000000001..FCLK is divided by 2 before being used by the I2C.
+ *  0b0000000000000010..FCLK is divided by 3 before being used by the I2C.
+ *  0b1111111111111111..FCLK is divided by 65,536 before being used by the I2C.
+ */
+#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status Register */
+/*! @{ */
+
+#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
+/*! MSTPENDING - Master Pending
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+
+#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+
+#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+
+#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
+/*! SLVPENDING - Slave Pending
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+
+#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
+/*! SLVNOTSTR - Slave Not Stretching status
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+
+#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
+/*! SLVDESEL - Slave Deselected flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+
+#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
+/*! MONRDY - Monitor Ready
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+
+#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
+/*! MONOV - Monitor Overflow flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+
+#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
+/*! MONIDLE - Monitor Idle flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+
+#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name MSTCTL - Master Control Register */
+/*! @{ */
+
+#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
+/*! MSTCONTINUE - Master Continue(write-only)
+ *  0b0..No effect
+ *  0b1..Continue. Informs the Master function to continue to the next operation. This action must done after
+ *       writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
+ */
+#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+
+#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
+/*! MSTSTART - Master Start control(write-only)
+ *  0b0..No effect
+ *  0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
+ */
+#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+
+#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
+/*! MSTSTOP - Master Stop control(write-only)
+ *  0b0..No effect
+ *  0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
+ *       if the master is receiving data from the slave (in Master Receiver mode).
+ */
+#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+
+#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
+/*! MSTDMA - Master DMA enable
+ *  0b0..Disable. No DMA requests are generated for master operation.
+ *  0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
+ *       Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
+ */
+#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+/*! @} */
+
+/*! @name MSTTIME - Master Timing Register */
+/*! @{ */
+
+#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
+/*! MSTSCLLOW - Master SCL Low time
+ *  0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
+ *  0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
+ *  0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
+ *  0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
+ *  0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
+ *  0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
+ *  0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
+ *  0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+
+#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
+/*! MSTSCLHIGH - Master SCL High time
+ *  0b000..2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider.
+ *  0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
+ *  0b010..4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider.
+ *  0b011..5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider.
+ *  0b100..6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider.
+ *  0b101..7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider.
+ *  0b110..8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider.
+ *  0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+/*! @} */
+
+/*! @name MSTDAT - Master Data Register */
+/*! @{ */
+
+#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT                    (0U)
+/*! DATA - Master function data register */
+#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVCTL - Slave Control Register */
+/*! @{ */
+
+#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
+/*! SLVCONTINUE - Slave Continue
+ *  0b0..No effect
+ *  0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the STAT[SLVPENDING]
+ *       flag. This must be done after writing transmit data, reading received data, or any other housekeeping
+ *       related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be
+ *       set unless SLVPENDING = 1.
+ */
+#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+
+#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
+/*! SLVNACK - Slave NACK
+ *  0b0..No effect
+ *  0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (in Slave Receiver mode).
+ */
+#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+
+#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
+/*! SLVDMA - Slave DMA enable
+ *  0b0..Disabled. No DMA requests are issued for Slave mode operation.
+ *  0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
+ */
+#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+
+#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
+/*! AUTOACK - Automatic Acknowledge
+ *  0b0..Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is generated when a
+ *       matching address is received. If AUTONACK = 1, then received addresses are NACKed (ignored).
+ *  0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
+ *       allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
+ *       not match AUTOMATCHREAD, then the behavior will depend on the SLVADR0[AUTONACK] bit: if AUTONACK is set,
+ *       then it will be Nacked; if AUTONACK is clear, then a SlvPending interrupt is generated.
+ */
+#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
+/*! AUTOMATCHREAD - Automatic Match Read
+ *  0b0..In Automatic Mode, the expected next operation is an I2C write.
+ *  0b1..In Automatic Mode, the expected next operation is an I2C read.
+ */
+#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+/*! @} */
+
+/*! @name SLVDAT - Slave Data Register */
+/*! @{ */
+
+#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT                    (0U)
+/*! DATA - Slave function data register */
+#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVADR - Slave Address Register */
+/*! @{ */
+
+#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
+/*! SADISABLE - Slave Address n Disable
+ *  0b0..Enabled. Slave Address n is enabled.
+ *  0b1..Ignored. Slave Address n is ignored.
+ */
+#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+
+#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
+/*! SLVADR - Slave Address. */
+#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+
+#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
+/*! AUTONACK - Automatic NACK operation
+ *  0b0..Normal operation, matching I2C addresses are not ignored.
+ *  0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, and the address
+ *       matches SLVADRn, and AUTOMATCHREAD matches the direction.
+ */
+#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+/*! @} */
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT                         (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for Address 0 Register */
+/*! @{ */
+
+#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
+/*! QUALMODE0 - Qualify mode for slave address 0
+ *  0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
+ *  0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
+ */
+#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+
+#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
+/*! SLVQUAL0 - Slave address Qualifier for address 0 */
+#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+/*! @} */
+
+/*! @name MONRXDAT - Monitor Receiver Data Register */
+/*! @{ */
+
+#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
+/*! MONRXDAT - Monitor function Receiver Data */
+#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+
+#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
+/*! MONSTART - Monitor Received Start
+ *  0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
+ *  0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+
+#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
+/*! MONRESTART - Monitor Received Repeated Start
+ *  0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
+ *  0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+
+#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
+/*! MONNACK - Monitor Received NACK
+ *  0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
+ *  0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
+ */
+#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral Identification Register */
+/*! @{ */
+
+#define I2C_ID_APERTURE_MASK                     (0xFFU)
+#define I2C_ID_APERTURE_SHIFT                    (0U)
+/*! APERTURE - Aperture */
+#define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+
+#define I2C_ID_MINOR_REV_MASK                    (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT                   (8U)
+/*! MINOR_REV - Minor revision of module implementation */
+#define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+
+#define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT                   (12U)
+/*! MAJOR_REV - Major revision of module implementation */
+#define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+
+#define I2C_ID_ID_MASK                           (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT                          (16U)
+/*! ID - Module identifier for the selected function */
+#define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral I2C0 base address */
+  #define I2C0_BASE                                (0x50106000u)
+  /** Peripheral I2C0 base address */
+  #define I2C0_BASE_NS                             (0x40106000u)
+  /** Peripheral I2C0 base pointer */
+  #define I2C0                                     ((I2C_Type *)I2C0_BASE)
+  /** Peripheral I2C0 base pointer */
+  #define I2C0_NS                                  ((I2C_Type *)I2C0_BASE_NS)
+  /** Peripheral I2C1 base address */
+  #define I2C1_BASE                                (0x50107000u)
+  /** Peripheral I2C1 base address */
+  #define I2C1_BASE_NS                             (0x40107000u)
+  /** Peripheral I2C1 base pointer */
+  #define I2C1                                     ((I2C_Type *)I2C1_BASE)
+  /** Peripheral I2C1 base pointer */
+  #define I2C1_NS                                  ((I2C_Type *)I2C1_BASE_NS)
+  /** Peripheral I2C2 base address */
+  #define I2C2_BASE                                (0x50108000u)
+  /** Peripheral I2C2 base address */
+  #define I2C2_BASE_NS                             (0x40108000u)
+  /** Peripheral I2C2 base pointer */
+  #define I2C2                                     ((I2C_Type *)I2C2_BASE)
+  /** Peripheral I2C2 base pointer */
+  #define I2C2_NS                                  ((I2C_Type *)I2C2_BASE_NS)
+  /** Peripheral I2C3 base address */
+  #define I2C3_BASE                                (0x50109000u)
+  /** Peripheral I2C3 base address */
+  #define I2C3_BASE_NS                             (0x40109000u)
+  /** Peripheral I2C3 base pointer */
+  #define I2C3                                     ((I2C_Type *)I2C3_BASE)
+  /** Peripheral I2C3 base pointer */
+  #define I2C3_NS                                  ((I2C_Type *)I2C3_BASE_NS)
+  /** Peripheral I2C14 base address */
+  #define I2C14_BASE                               (0x50126000u)
+  /** Peripheral I2C14 base address */
+  #define I2C14_BASE_NS                            (0x40126000u)
+  /** Peripheral I2C14 base pointer */
+  #define I2C14                                    ((I2C_Type *)I2C14_BASE)
+  /** Peripheral I2C14 base pointer */
+  #define I2C14_NS                                 ((I2C_Type *)I2C14_BASE_NS)
+  /** Array initializer of I2C peripheral base addresses */
+  #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C14_BASE }
+  /** Array initializer of I2C peripheral base pointers */
+  #define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C14 }
+  /** Array initializer of I2C peripheral base addresses */
+  #define I2C_BASE_ADDRS_NS                        { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C14_BASE_NS }
+  /** Array initializer of I2C peripheral base pointers */
+  #define I2C_BASE_PTRS_NS                         { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C14_NS }
+#else
+  /** Peripheral I2C0 base address */
+  #define I2C0_BASE                                (0x40106000u)
+  /** Peripheral I2C0 base pointer */
+  #define I2C0                                     ((I2C_Type *)I2C0_BASE)
+  /** Peripheral I2C1 base address */
+  #define I2C1_BASE                                (0x40107000u)
+  /** Peripheral I2C1 base pointer */
+  #define I2C1                                     ((I2C_Type *)I2C1_BASE)
+  /** Peripheral I2C2 base address */
+  #define I2C2_BASE                                (0x40108000u)
+  /** Peripheral I2C2 base pointer */
+  #define I2C2                                     ((I2C_Type *)I2C2_BASE)
+  /** Peripheral I2C3 base address */
+  #define I2C3_BASE                                (0x40109000u)
+  /** Peripheral I2C3 base pointer */
+  #define I2C3                                     ((I2C_Type *)I2C3_BASE)
+  /** Peripheral I2C14 base address */
+  #define I2C14_BASE                               (0x40126000u)
+  /** Peripheral I2C14 base pointer */
+  #define I2C14                                    ((I2C_Type *)I2C14_BASE)
+  /** Array initializer of I2C peripheral base addresses */
+  #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C14_BASE }
+  /** Array initializer of I2C peripheral base pointers */
+  #define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C14 }
+#endif
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM14_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[3072];
+  __IO uint32_t CFG1;                              /**< Configuration Register 1 for the Primary Channel Pair, offset: 0xC00 */
+  __IO uint32_t CFG2;                              /**< Configuration Register 2 for the Primary Channel Pair, offset: 0xC04 */
+  __IO uint32_t STAT;                              /**< Status Register for the Primary Channel Pair, offset: 0xC08 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< Clock Divider, offset: 0xC1C */
+  struct {                                         /* offset: 0xC20, array step: 0x20 */
+    __IO uint32_t PCFG1;                             /**< Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3, array offset: 0xC20, array step: 0x20 */
+    __IO uint32_t PCFG2;                             /**< Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3, array offset: 0xC24, array step: 0x20 */
+    __I  uint32_t PSTAT;                             /**< Status Register for Channel Pair 1..Status Register for Channel Pair 3, array offset: 0xC28, array step: 0x20 */
+         uint8_t RESERVED_0[20];
+  } SECCHANNEL[3];
+       uint8_t RESERVED_2[384];
+  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration and Enable, offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO Status, offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Settings, offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable Set and Read, offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear and Read, offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status, offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO Write Data, offset: 0xE20 */
+  __O  uint32_t FIFOWR48H;                         /**< FIFO Write Data for Upper Data Bits, offset: 0xE24 */
+       uint8_t RESERVED_5[8];
+  __I  uint32_t FIFORD;                            /**< FIFO Read Data, offset: 0xE30 */
+  __I  uint32_t FIFORD48H;                         /**< FIFO Read Data for Upper Data Bits, offset: 0xE34 */
+       uint8_t RESERVED_6[8];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
+  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO Data Read for Upper Data Bits with No FIFO Pop, offset: 0xE44 */
+  __I  uint32_t FIFOSIZE;                          /**< FIFO Size Register, offset: 0xE48 */
+  struct {                                         /* offset: 0xE4C */
+    __IO uint32_t FIFORXTIMEOUTCFG;                  /**< FIFO Receive Timeout Configuration, offset: 0xE4C */
+    __I  uint32_t FIFORXTIMEOUTCNT;                  /**< FIFO Receive Timeout Counter, offset: 0xE50 */
+  } FIFO_I2S;
+       uint8_t RESERVED_7[424];
+  __I  uint32_t ID;                                /**< I2S Module Identification, offset: 0xFFC */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name CFG1 - Configuration Register 1 for the Primary Channel Pair */
+/*! @{ */
+
+#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
+/*! MAINENABLE - Main Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+
+#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
+/*! DATAPAUSE - Data Flow Pause
+ *  0b0..Normal operation
+ *  0b1..Pause
+ */
+#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+
+#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
+/*! PAIRCOUNT - Pair Count
+ *  0b00..One Pair
+ *  0b01..Two Pairs
+ *  0b10..Three Pairs
+ *  0b11..Four Pairs
+ */
+#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+
+#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
+/*! MSTSLVCFG - Master/Slave Configuration Selection
+ *  0b00..Normal Slave Mode
+ *  0b01..WS Synchronized Master Mode
+ *  0b10..Master Using an Existing SCK Mode
+ *  0b11..Normal Master Mode
+ */
+#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+
+#define I2S_CFG1_MODE_MASK                       (0xC0U)
+#define I2S_CFG1_MODE_SHIFT                      (6U)
+/*! MODE - Mode
+ *  0b00..Classic Mode
+ *  0b01..DSP mode WS 50% duty cycle
+ *  0b10..DSP mode WS 1 clock
+ *  0b11..DSP mode WS 1 data
+ */
+#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+
+#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
+/*! RIGHTLOW - Right Channel Low
+ *  0b0..Right high
+ *  0b1..Right low
+ */
+#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+
+#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
+/*! LEFTJUST - Left-Justify Data
+ *  0b0..Right-justified
+ *  0b1..Left-justified
+ */
+#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+
+#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
+/*! ONECHANNEL - Single Channel Mode
+ *  0b0..Dual channel
+ *  0b1..Single channel
+ */
+#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+
+#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
+/*! PDMDATA - PDM Data Selection
+ *  0b0..Normal Operation
+ *  0b1..DMIC subsystem
+ */
+#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+
+#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
+/*! SCK_POL - SCK Polarity
+ *  0b0..Falling edge
+ *  0b1..Rising edge
+ */
+#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+
+#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT                    (13U)
+/*! WS_POL - WS Polarity
+ *  0b0..Not inverted
+ *  0b1..Inverted. The WS signal is inverted.
+ */
+#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+
+#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT                   (16U)
+/*! DATALEN - Data Length
+ *  0b00011..Data is 4 bits in length.
+ *  0b00100..Data is 5 bits in length.
+ *  0b00111..Data is 8 bits in length.
+ *  0b11110..Data is 31 bits in length.
+ *  0b11111..Data is 32 bits in length.
+ */
+#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+/*! @} */
+
+/*! @name CFG2 - Configuration Register 2 for the Primary Channel Pair */
+/*! @{ */
+
+#define I2S_CFG2_FRAMELEN_MASK                   (0x7FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
+/*! FRAMELEN - Frame Length
+ *  0b00000000011..Frame is 4 bits in total length
+ *  0b00000000100..Frame is 5 bits in total length
+ *  0b00111111111..Frame is 512 bits in total length
+ *  0b11111111111..Frame is 2048 bits in total length
+ */
+#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+
+#define I2S_CFG2_POSITION_MASK                   (0x7FF0000U)
+#define I2S_CFG2_POSITION_SHIFT                  (16U)
+/*! POSITION - Data Position
+ *  0b00000000000..Data begins at bit position 0 (the first bit position) within the frame or WS phase
+ *  0b00000000001..Data begins at bit position 1 within the frame or WS phase
+ *  0b00000000010..Data begins at bit position 2 within the frame or WS phase
+ */
+#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+/*! @} */
+
+/*! @name STAT - Status Register for the Primary Channel Pair */
+/*! @{ */
+
+#define I2S_STAT_BUSY_MASK                       (0x1U)
+#define I2S_STAT_BUSY_SHIFT                      (0U)
+/*! BUSY - Busy Status
+ *  0b0..Idle
+ *  0b1..Busy
+ */
+#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+
+#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
+/*! SLVFRMERR - Slave Frame Error
+ *  0b0..No error
+ *  0b1..Error
+ */
+#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+
+#define I2S_STAT_LR_MASK                         (0x4U)
+#define I2S_STAT_LR_SHIFT                        (2U)
+/*! LR - Left/Right Indication
+ *  0b0..Left channel
+ *  0b1..Right channel
+ */
+#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+
+#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
+/*! DATAPAUSED - Data Paused
+ *  0b0..Not Paused
+ *  0b1..Paused
+ */
+#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+/*! @} */
+
+/*! @name DIV - Clock Divider */
+/*! @{ */
+
+#define I2S_DIV_DIV_MASK                         (0xFFFU)
+#define I2S_DIV_DIV_SHIFT                        (0U)
+/*! DIV - Divider
+ *  0b000000000000..FCLK is used directly.
+ *  0b000000000001..FCLK is divided by 2.
+ *  0b000000000010..FCLK is divided by 3.
+ *  0b111111111111..FCLK is divided by 4,096.
+ */
+#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+/*! @} */
+
+/*! @name SECCHANNEL_PCFG1 - Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3 */
+/*! @{ */
+
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK     (0x1U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT    (0U)
+/*! PAIRENABLE - Pair Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
+
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK     (0x400U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT    (10U)
+/*! ONECHANNEL - Single Channel Mode
+ *  0b0..Dual Channel
+ *  0b1..Single Channel
+ */
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG1 */
+#define I2S_SECCHANNEL_PCFG1_COUNT               (3U)
+
+/*! @name SECCHANNEL_PCFG2 - Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3 */
+/*! @{ */
+
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK       (0x1FF0000U)
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT      (16U)
+/*! POSITION - Data Position */
+#define I2S_SECCHANNEL_PCFG2_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG2 */
+#define I2S_SECCHANNEL_PCFG2_COUNT               (3U)
+
+/*! @name SECCHANNEL_PSTAT - Status Register for Channel Pair 1..Status Register for Channel Pair 3 */
+/*! @{ */
+
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK           (0x1U)
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT          (0U)
+/*! BUSY - Busy Status for Channel Pair
+ *  0b0..Idle. The transmitter/receiver for this channel pair is currently idle.
+ *  0b1..Busy. The transmitter/receiver for this channel pair is currently processing data.
+ */
+#define I2S_SECCHANNEL_PSTAT_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
+
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK      (0x2U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT     (1U)
+/*! SLVFRMERR - Save Frame Error Flag
+ *  0b0..No Error
+ *  0b1..Error
+ */
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x)        (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
+
+#define I2S_SECCHANNEL_PSTAT_LR_MASK             (0x4U)
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT            (2U)
+/*! LR - Left/Right Indication
+ *  0b0..Left channel
+ *  0b1..Right channel
+ */
+#define I2S_SECCHANNEL_PSTAT_LR(x)               (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
+
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK     (0x8U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT    (3U)
+/*! DATAPAUSED - Data Paused Status Flag
+ *  0b0..Data Not Paused. Data is not currently paused. A data pause may have been requested but is not yet in
+ *       force, waiting for an allowed pause point. Refer to the description in CFG1[DATAPAUSE].
+ *  0b1..Data Paused. A data pause has been requested and is now in force.
+ */
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PSTAT */
+#define I2S_SECCHANNEL_PSTAT_COUNT               (3U)
+
+/*! @name FIFOCFG - FIFO Configuration and Enable */
+/*! @{ */
+
+#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
+/*! ENABLETX - Enable Transmit FIFO
+ *  0b0..Disabled Transmit. The transmit FIFO is not enabled.
+ *  0b1..Enabled transmit. The transmit FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+
+#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
+/*! ENABLERX - Enable Receive FIFO
+ *  0b0..Disabled. The receive FIFO is not enabled.
+ *  0b1..Enabled. The receive FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+
+#define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
+/*! TXI2SE0 - Transmit I2S Empty 0
+ *  0b0..Last value
+ *  0b1..Zero
+ */
+#define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+
+#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
+/*! PACK48 - Packing Format 48-bit data
+ *  0b0..Bits_24
+ *  0b1..Bits_32_16
+ */
+#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+
+#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
+/*! SIZE - FIFO Size Configuration
+ *  0b10..Size 32 Bits
+ *  0b11..Size 48 Bits
+ */
+#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+
+#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
+/*! DMATX - DMA Transmit
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+
+#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
+/*! DMARX - DMA Receive
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+
+#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
+/*! WAKETX - Wake-up for Transmit FIFO Level
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+
+#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
+/*! WAKERX - Wake-up for Receive FIFO Level
+ *  0b0..Only enabled interrupts wake up the device from reduced power modes.
+ *  0b1..A device wake-up for DMA occurs if the receive FIFO level reaches the value specified by FIFOTRIG[RXLVL],
+ *       even when the RXLVL interrupt is not enabled.
+ */
+#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+
+#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. */
+#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+
+#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */
+#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+
+#define I2S_FIFOCFG_POPDBG_MASK                  (0x40000U)
+#define I2S_FIFOCFG_POPDBG_SHIFT                 (18U)
+/*! POPDBG - Pop FIFO for Debug Reads
+ *  0b0..Debug reads of the FIFO do not pop the FIFO.
+ *  0b1..A debug read causes the FIFO to pop.
+ */
+#define I2S_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO Status */
+/*! @{ */
+
+#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
+/*! TXERR - TX FIFO Error
+ *  0b0..No transmit FIFO error occured
+ *  0b1..Transmit FIFO error occured
+ */
+#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+
+#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
+/*! RXERR - RX FIFO Error
+ *  0b0..No receive FIFO error occured
+ *  0b1..Receive FIFO error occured
+ */
+#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+
+#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
+/*! PERINT - Peripheral Interrupt
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+
+#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+/*! TXEMPTY - Transmit FIFO Empty
+ *  0b0..Transmit FIFO is not empty
+ *  0b1..Transmit FIFO is empty; however, the peripheral may still be processing the last piece of data.
+ */
+#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+
+#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+/*! TXNOTFULL - Transmit FIFO Not Full
+ *  0b0..Transmit FIFO is full, and another write would cause an overflow
+ *  0b1..Transmit FIFO is not full, so more data can be written
+ */
+#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+/*! RXNOTEMPTY - Receive FIFO Not Empty
+ *  0b0..Receive FIFO is empty
+ *  0b1..Receive FIFO is not empty, so data can be read.
+ */
+#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+
+#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
+/*! RXFULL - Receive FIFO Full
+ *  0b0..Receive FIFO is not full
+ *  0b1..Receive FIFO is full
+ */
+#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+
+#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO Current Level
+ *  0b00000..TX FIFO is empty
+ */
+#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+
+#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO Current Level
+ *  0b00000..RX FIFO is empty
+ */
+#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+
+#define I2S_FIFOSTAT_RXTIMEOUT_MASK              (0x1000000U)
+#define I2S_FIFOSTAT_RXTIMEOUT_SHIFT             (24U)
+/*! RXTIMEOUT - Receive FIFO Timeout
+ *  0b0..RX FIFO on
+ *  0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register.
+ */
+#define I2S_FIFOSTAT_RXTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOSTAT_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO Trigger Settings */
+/*! @{ */
+
+#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+/*! TXLVLENA - Transmit FIFO Level Trigger Enable
+ *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger generates if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+
+#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+/*! RXLVLENA - Receive FIFO Level Trigger Enable
+ *  0b0..Receive FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger generates if the receive FIFO level reaches the value specified by the RXLVL.
+ */
+#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+
+#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO Level Trigger Point
+ *  0b0000..Trigger when the TX FIFO becomes empty.
+ *  0b0001..Trigger when the TX FIFO level decreases to one entry.
+ *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full).
+ */
+#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+
+#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO Level Trigger Point
+ *  0b0000..Trigger when the RX FIFO has received 1 entry (the FIFO is no longer empty).
+ *  0b0001..Trigger when the RX FIFO has received 2 entries.
+ *  0b1111..Trigger when the RX FIFO has received 16 entries (the FIFO has become full).
+ */
+#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO Interrupt Enable Set and Read */
+/*! @{ */
+
+#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
+/*! TXERR - Transmit Error Interrupt
+ *  0b0..Disabled. No interrupt generates for a transmit error.
+ *  0b1..Enabled. An interrupt generates when a transmit error occurs.
+ */
+#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+
+#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
+/*! RXERR - Receive Error Interrupt
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+
+#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
+/*! TXLVL - Transmit Level Interrupt
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+
+#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
+/*! RXLVL - Receive Level Interrupt
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+
+#define I2S_FIFOINTENSET_RXTIMEOUT_MASK          (0x1000000U)
+#define I2S_FIFOINTENSET_RXTIMEOUT_SHIFT         (24U)
+/*! RXTIMEOUT - Receive Timeout
+ *  0b0..No RX interrupt will be generated.
+ *  0b1..Asserts RX interrupt if RX FIFO Timeout event occurs.
+ */
+#define I2S_FIFOINTENSET_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENSET_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear and Read */
+/*! @{ */
+
+#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
+/*! TXERR - Transmit Error Interrupt Clear
+ *  0b0..Interrupt is not cleared.
+ *  0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+
+#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
+/*! RXERR - Receive Error Interrupt Clear
+ *  0b0..Interrupt is not cleared.
+ *  0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+
+#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+/*! TXLVL - Transmit Level Interrupt Clear
+ *  0b0..Interrupt is not cleared.
+ *  0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+
+#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+/*! RXLVL - Receive Level Interrupt Clear
+ *  0b0..Interrupt is not cleared.
+ *  0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+
+#define I2S_FIFOINTENCLR_RXTIMEOUT_MASK          (0x1000000U)
+#define I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT         (24U)
+/*! RXTIMEOUT - Receive Timeout
+ *  0b0..No effect
+ *  0b1..Clear the interrupt
+ */
+#define I2S_FIFOINTENCLR_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENCLR_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO Interrupt Status */
+/*! @{ */
+
+#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
+/*! TXERR - TX FIFO Error Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+
+#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
+/*! RXERR - RX FIFO Error Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+
+#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+
+#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+
+#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
+/*! PERINT - Peripheral Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+
+#define I2S_FIFOINTSTAT_RXTIMEOUT_MASK           (0x1000000U)
+#define I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT          (24U)
+/*! RXTIMEOUT - Receive Timeout Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_RXTIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOINTSTAT_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO Write Data */
+/*! @{ */
+
+#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
+/*! TXDATA - Transmit Data to the FIFO */
+#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFOWR48H - FIFO Write Data for Upper Data Bits */
+/*! @{ */
+
+#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
+/*! TXDATA - Transmit Data to the FIFO */
+#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO Read Data */
+/*! @{ */
+
+#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48H - FIFO Read Data for Upper Data Bits */
+/*! @{ */
+
+#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
+/*! @{ */
+
+#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48HNOPOP - FIFO Data Read for Upper Data Bits with No FIFO Pop */
+/*! @{ */
+
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFOSIZE - FIFO Size Register */
+/*! @{ */
+
+#define I2S_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
+#define I2S_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
+#define I2S_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK)
+/*! @} */
+
+/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */
+/*! @{ */
+
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU)
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U)
+/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler */
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK)
+
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U)
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U)
+/*! RXTIMEOUT_VALUE - Receive Timeout Value */
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK)
+
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK   (0x1000000U)
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT  (24U)
+/*! RXTIMEOUT_EN - Receive Timeout Enable
+ *  0b0..Disable RX FIFO timeout
+ *  0b1..Enable RX FIFO timeout
+ */
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x)     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK)
+
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK  (0x2000000U)
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U)
+/*! RXTIMEOUT_COW - Receive Timeout Continue On Write
+ *  0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO.
+ *  0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO.
+ */
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x)    (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK)
+
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK  (0x4000000U)
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U)
+/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty
+ *  0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty.
+ *  0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty.
+ */
+#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x)    (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK)
+/*! @} */
+
+/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */
+/*! @{ */
+
+#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK  (0xFFFFU)
+#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U)
+/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value */
+#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x)    (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK)
+/*! @} */
+
+/*! @name ID - I2S Module Identification */
+/*! @{ */
+
+#define I2S_ID_APERTURE_MASK                     (0xFFU)
+#define I2S_ID_APERTURE_SHIFT                    (0U)
+/*! APERTURE - Aperture */
+#define I2S_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK)
+
+#define I2S_ID_MINOR_REV_MASK                    (0xF00U)
+#define I2S_ID_MINOR_REV_SHIFT                   (8U)
+/*! MINOR_REV - Minor Revision */
+#define I2S_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK)
+
+#define I2S_ID_MAJOR_REV_MASK                    (0xF000U)
+#define I2S_ID_MAJOR_REV_SHIFT                   (12U)
+/*! MAJOR_REV - Major Revision */
+#define I2S_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK)
+
+#define I2S_ID_ID_MASK                           (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT                          (16U)
+/*! ID - Module Identifier */
+#define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral I2S0 base address */
+  #define I2S0_BASE                                (0x50106000u)
+  /** Peripheral I2S0 base address */
+  #define I2S0_BASE_NS                             (0x40106000u)
+  /** Peripheral I2S0 base pointer */
+  #define I2S0                                     ((I2S_Type *)I2S0_BASE)
+  /** Peripheral I2S0 base pointer */
+  #define I2S0_NS                                  ((I2S_Type *)I2S0_BASE_NS)
+  /** Peripheral I2S1 base address */
+  #define I2S1_BASE                                (0x50107000u)
+  /** Peripheral I2S1 base address */
+  #define I2S1_BASE_NS                             (0x40107000u)
+  /** Peripheral I2S1 base pointer */
+  #define I2S1                                     ((I2S_Type *)I2S1_BASE)
+  /** Peripheral I2S1 base pointer */
+  #define I2S1_NS                                  ((I2S_Type *)I2S1_BASE_NS)
+  /** Peripheral I2S2 base address */
+  #define I2S2_BASE                                (0x50108000u)
+  /** Peripheral I2S2 base address */
+  #define I2S2_BASE_NS                             (0x40108000u)
+  /** Peripheral I2S2 base pointer */
+  #define I2S2                                     ((I2S_Type *)I2S2_BASE)
+  /** Peripheral I2S2 base pointer */
+  #define I2S2_NS                                  ((I2S_Type *)I2S2_BASE_NS)
+  /** Peripheral I2S3 base address */
+  #define I2S3_BASE                                (0x50109000u)
+  /** Peripheral I2S3 base address */
+  #define I2S3_BASE_NS                             (0x40109000u)
+  /** Peripheral I2S3 base pointer */
+  #define I2S3                                     ((I2S_Type *)I2S3_BASE)
+  /** Peripheral I2S3 base pointer */
+  #define I2S3_NS                                  ((I2S_Type *)I2S3_BASE_NS)
+  /** Peripheral I2S14 base address */
+  #define I2S14_BASE                               (0x50126000u)
+  /** Peripheral I2S14 base address */
+  #define I2S14_BASE_NS                            (0x40126000u)
+  /** Peripheral I2S14 base pointer */
+  #define I2S14                                    ((I2S_Type *)I2S14_BASE)
+  /** Peripheral I2S14 base pointer */
+  #define I2S14_NS                                 ((I2S_Type *)I2S14_BASE_NS)
+  /** Array initializer of I2S peripheral base addresses */
+  #define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S14_BASE }
+  /** Array initializer of I2S peripheral base pointers */
+  #define I2S_BASE_PTRS                            { I2S0, I2S1, I2S2, I2S3, I2S14 }
+  /** Array initializer of I2S peripheral base addresses */
+  #define I2S_BASE_ADDRS_NS                        { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S14_BASE_NS }
+  /** Array initializer of I2S peripheral base pointers */
+  #define I2S_BASE_PTRS_NS                         { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S14_NS }
+#else
+  /** Peripheral I2S0 base address */
+  #define I2S0_BASE                                (0x40106000u)
+  /** Peripheral I2S0 base pointer */
+  #define I2S0                                     ((I2S_Type *)I2S0_BASE)
+  /** Peripheral I2S1 base address */
+  #define I2S1_BASE                                (0x40107000u)
+  /** Peripheral I2S1 base pointer */
+  #define I2S1                                     ((I2S_Type *)I2S1_BASE)
+  /** Peripheral I2S2 base address */
+  #define I2S2_BASE                                (0x40108000u)
+  /** Peripheral I2S2 base pointer */
+  #define I2S2                                     ((I2S_Type *)I2S2_BASE)
+  /** Peripheral I2S3 base address */
+  #define I2S3_BASE                                (0x40109000u)
+  /** Peripheral I2S3 base pointer */
+  #define I2S3                                     ((I2S_Type *)I2S3_BASE)
+  /** Peripheral I2S14 base address */
+  #define I2S14_BASE                               (0x40126000u)
+  /** Peripheral I2S14 base pointer */
+  #define I2S14                                    ((I2S_Type *)I2S14_BASE)
+  /** Array initializer of I2S peripheral base addresses */
+  #define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S14_BASE }
+  /** Array initializer of I2S peripheral base pointers */
+  #define I2S_BASE_PTRS                            { I2S0, I2S1, I2S2, I2S3, I2S14 }
+#endif
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM14_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SCT0_IN_SEL[7];                    /**< SCT Peripheral Input Multiplexers N, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[228];
+  __IO uint32_t PINT_SEL[8];                       /**< GPIO Pin Input Multiplexer N, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_1[224];
+  __IO uint32_t DMAC0_ITRIG_SEL[33];               /**< DMAC0 Input Trigger Multiplexers N, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_2[124];
+  __IO uint32_t DMAC0_OTRIG_SEL[4];                /**< DMAC0 Output Trigger Multiplexers N, array offset: 0x300, array step: 0x4 */
+       uint8_t RESERVED_3[240];
+  __IO uint32_t DMAC1_ITRIG_SEL[33];               /**< DMAC1 Input Trigger Multiplexers N, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_4[124];
+  __IO uint32_t DMAC1_OTRIG_SEL[4];                /**< DMAC1 Output Trigger Multiplexers N, array offset: 0x500, array step: 0x4 */
+       uint8_t RESERVED_5[240];
+  __IO uint32_t CT32BIT_CAP_SEL[4][4];             /**< CT32BIT N Counter Timer Capture Trigger Multiplexers M, array offset: 0x600, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_6[192];
+  __IO uint32_t FMEASURE_CH_SEL[2];                /**< Frequency Measurement Input Channel Multiplexers, array offset: 0x700, array step: 0x4 */
+       uint8_t RESERVED_7[56];
+  __IO uint32_t DMAC0_REQ_ENA0;                    /**< DMAC0 request enable 0, offset: 0x740 */
+       uint8_t RESERVED_8[4];
+  __O  uint32_t DMAC0_REQ_ENA0_SET;                /**< DMAC0 request enable set 0, offset: 0x748 */
+       uint8_t RESERVED_9[4];
+  __O  uint32_t DMAC0_REQ_ENA0_CLR;                /**< DMAC0 request enable clear 0, offset: 0x750 */
+       uint8_t RESERVED_10[12];
+  __IO uint32_t DMAC1_REQ_ENA0;                    /**< DMAC1 request enable 0, offset: 0x760 */
+       uint8_t RESERVED_11[4];
+  __O  uint32_t DMAC1_REQ_ENA0_SET;                /**< DMAC1 request enable set 0, offset: 0x768 */
+       uint8_t RESERVED_12[4];
+  __O  uint32_t DMAC1_REQ_ENA0_CLR;                /**< DMAC1 request enable clear 0, offset: 0x770 */
+       uint8_t RESERVED_13[12];
+  __IO uint32_t DMAC0_ITRIG_ENA0;                  /**< DMAC0 input trigger enable 0, offset: 0x780 */
+  __IO uint32_t DMAC0_ITRIG_ENA1;                  /**< DMAC0 input trigger enable 1, offset: 0x784 */
+  __O  uint32_t DMAC0_ITRIG_ENA0_SET;              /**< DMAC0 input trigger enable set 0, offset: 0x788 */
+  __O  uint32_t DMAC0_ITRIG_ENA1_SET;              /**< DMAC0 input trigger enable set 1, offset: 0x78C */
+  __O  uint32_t DMAC0_ITRIG_ENA0_CLR;              /**< DMAC0 input trigger enable clear 0, offset: 0x790 */
+  __O  uint32_t DMAC0_ITRIG_ENA1_CLR;              /**< DMAC0 input trigger enable clear 1, offset: 0x794 */
+       uint8_t RESERVED_14[8];
+  __IO uint32_t DMAC1_ITRIG_ENA0;                  /**< DMAC1 input trigger enable 0, offset: 0x7A0 */
+  __IO uint32_t DMAC1_ITRIG_ENA1;                  /**< DMAC1 input trigger enable 1, offset: 0x7A4 */
+  __O  uint32_t DMAC1_ITRIG_ENA0_SET;              /**< DMAC1 input trigger enable set 0, offset: 0x7A8 */
+  __O  uint32_t DMAC1_ITRIG_ENA1_SET;              /**< DMAC1 input trigger enable set 1, offset: 0x7AC */
+  __O  uint32_t DMAC1_ITRIG_ENA0_CLR;              /**< DMAC1 input trigger enable clear 0, offset: 0x7B0 */
+  __O  uint32_t DMAC1_ITRIG_ENA1_CLR;              /**< DMAC1 input trigger enable clear 1, offset: 0x7B4 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name SCT0_IN_SEL - SCT Peripheral Input Multiplexers N */
+/*! @{ */
+
+#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_MASK     (0x1FU)
+#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_SHIFT    (0U)
+/*! SCT_IN_SEL - SCT0 Input(n) Selection. 24:1 Selection for each. . .
+ *  0b00000..SCT0_PIN_INP0
+ *  0b00001..SCT0_PIN_INP1
+ *  0b00010..SCT0_PIN_INP2
+ *  0b00011..SCT0_PIN_INP3
+ *  0b00100..SCT0_PIN_INP4
+ *  0b00101..SCT0_PIN_INP5
+ *  0b00110..SCT0_PIN_INP6
+ *  0b00111..SCT0_PIN_INP7
+ *  0b01000..CT32BIT0_MAT0
+ *  0b01001..CT32BIT1_MAT0
+ *  0b01010..CT32BIT2_MAT0
+ *  0b01011..CT32BIT3_MAT0
+ *  0b01100..RESERVED
+ *  0b01101..RESERVED
+ *  0b01110..GPIOINT_BMATCH
+ *  0b01111..NOT_CONNECTED
+ *  0b10000..NOT_CONNECTED
+ *  0b10001..SHARED I2S0_SCLK
+ *  0b10010..SHARED I2S1_SCLK
+ *  0b10011..SHARED I2S0_WS
+ *  0b10100..SHARED I2S1_WS
+ *  0b10101..MCLK
+ *  0b10110..ARM_TXEV
+ *  0b10111..DEBUG_HALTED
+ *  0b11000..RESERVED
+ *  0b11001..RESERVED
+ *  0b11010..RESERVED
+ *  0b11011..RESERVED
+ *  0b11100..RESERVED
+ *  0b11101..RESERVED
+ *  0b11110..RESERVED
+ *  0b11111..RESERVED
+ */
+#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_SHIFT)) & INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_SCT0_IN_SEL */
+#define INPUTMUX_SCT0_IN_SEL_COUNT               (7U)
+
+/*! @name PINT_SEL - GPIO Pin Input Multiplexer N */
+/*! @{ */
+
+#define INPUTMUX_PINT_SEL_PINT_SEL_MASK          (0xFFU)
+#define INPUTMUX_PINT_SEL_PINT_SEL_SHIFT         (0U)
+/*! PINT_SEL - Port Input (PIOx.y) 64 to 8 Mux Select. . . Pin number select for pin interrupt or
+ *    pattern match engine input. (For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to
+ *    numbers 0 to 63.
+ */
+#define INPUTMUX_PINT_SEL_PINT_SEL(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINT_SEL_PINT_SEL_SHIFT)) & INPUTMUX_PINT_SEL_PINT_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_PINT_SEL */
+#define INPUTMUX_PINT_SEL_COUNT                  (8U)
+
+/*! @name DMAC0_ITRIG_SEL - DMAC0 Input Trigger Multiplexers N */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_ITRIG_SEL_DMA0_ITRIG_SEL_MASK (0x3FU)
+#define INPUTMUX_DMAC0_ITRIG_SEL_DMA0_ITRIG_SEL_SHIFT (0U)
+/*! DMA0_ITRIG_SEL - DMA Input Triggers(n) Selection. 22:1 Selection for each. . .
+ *  0b000000..NSGPIOPINT0_INT0
+ *  0b000001..NSGPIOPINT0_INT1
+ *  0b000010..NSGPIOPINT0_INT2
+ *  0b000011..NSGPIOPINT0_INT3
+ *  0b000100..CT32BIT0_DMAREQ_M0
+ *  0b000101..CT32BIT0_DMAREQ_M1
+ *  0b000110..CT32BIT1_DMAREQ_M0
+ *  0b000111..CT32BIT1_DMAREQ_M1
+ *  0b001000..CT32BIT2_DMAREQ_M0
+ *  0b001001..CT32BIT2_DMAREQ_M1
+ *  0b001010..CT32BIT3_DMAREQ_M0
+ *  0b001011..CT32BIT3_DMAREQ_M1
+ *  0b001100..RESERVED
+ *  0b001101..RESERVED
+ *  0b001110..DMAC0_TRIGOUT_A
+ *  0b001111..DMAC0_TRIGOUT_B
+ *  0b010000..DMAC0_TRIGOUT_C
+ *  0b010001..DMAC0_TRIGOUT_D
+ *  0b010010..SCT0_DMA0
+ *  0b010011..SCT0_DMA1
+ *  0b010100..ENET_MAC0_DMA_REQ0
+ *  0b010101..ENET_MAC0_DMA_REQ1
+ *  0b010110..USIM_DMA_RX_SINGLE
+ *  0b010111..USIM_DMA_TX_SINGLE
+ *  0b011000..GAU_GPADC0_DMA_SINGLE
+ *  0b011001..GAU_GPADC1_DMA_SINGLE
+ *  0b011010..GAU_GPADCA_DMA_REQ
+ *  0b011011..GAU_GPADCB_DMA_REQ
+ *  0b011100..FLEXSPI_RX
+ *  0b011101..FLEXSPI_TX
+ *  0b011110..RESERVED
+ *  0b011111..RESERVED
+ *  0b100000..LCD_RX_REQ_TO_DMA_SINGLE
+ *  0b100001..LCD_TX_REQ_TO_DMA_SINGLE
+ *  0b100010..RESERVED
+ *  0b100011..RESERVED
+ *  0b100100..RESERVED
+ *  0b100101..RESERVED
+ *  0b100110..RESERVED
+ *  0b100111..RESERVED
+ *  0b101000..RESERVED
+ *  0b101001..RESERVED
+ *  0b101010..RESERVED
+ *  0b101011..RESERVED
+ *  0b101100..RESERVED
+ *  0b101101..RESERVED
+ *  0b101110..RESERVED
+ *  0b101111..RESERVED
+ *  0b110000..RESERVED
+ *  0b110001..RESERVED
+ *  0b110010..RESERVED
+ *  0b110011..RESERVED
+ *  0b110100..RESERVED
+ *  0b110101..RESERVED
+ *  0b110110..RESERVED
+ *  0b110111..RESERVED
+ *  0b111000..RESERVED
+ *  0b111001..RESERVED
+ *  0b111010..RESERVED
+ *  0b111011..RESERVED
+ *  0b111100..RESERVED
+ *  0b111101..RESERVED
+ *  0b111110..RESERVED
+ *  0b111111..RESERVED
+ */
+#define INPUTMUX_DMAC0_ITRIG_SEL_DMA0_ITRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_SEL_DMA0_ITRIG_SEL_SHIFT)) & INPUTMUX_DMAC0_ITRIG_SEL_DMA0_ITRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC0_ITRIG_SEL */
+#define INPUTMUX_DMAC0_ITRIG_SEL_COUNT           (33U)
+
+/*! @name DMAC0_OTRIG_SEL - DMAC0 Output Trigger Multiplexers N */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_MASK (0x3FU)
+#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_SHIFT (0U)
+/*! DMAC0_OTRIG_SEL - DMAC0 Output Triggers Select for A, B, C, D IE.,DMAC0_OTRIG_A, DMAC0_OTRIG_B,
+ *    DMAC0_OTRIG_C, DMAC0_OTRIG_D DMA0 Output Triggers(n) Selection. 32:1 Selection for each. . .
+ *  0b000000..DMAC0_OTRIG_CH0
+ *  0b000001..DMAC0_OTRIG_CH1
+ *  0b000010..DMAC0_OTRIG_CH2
+ *  0b000011..DMAC0_OTRIG_CH3
+ *  0b000100..DMAC0_OTRIG_CH4
+ *  0b000101..DMAC0_OTRIG_CH5
+ *  0b000110..DMAC0_OTRIG_CH6
+ *  0b000111..DMAC0_OTRIG_CH7
+ *  0b001000..DMAC0_OTRIG_CH8
+ *  0b001001..DMAC0_OTRIG_CH9
+ *  0b001010..DMAC0_OTRIG_CH10
+ *  0b001011..DMAC0_OTRIG_CH11
+ *  0b001100..DMAC0_OTRIG_CH12
+ *  0b001101..DMAC0_OTRIG_CH13
+ *  0b001110..DMAC0_OTRIG_CH14
+ *  0b001111..DMAC0_OTRIG_CH15
+ *  0b010000..DMAC0_OTRIG_CH16
+ *  0b010001..DMAC0_OTRIG_CH17
+ *  0b010010..DMAC0_OTRIG_CH18
+ *  0b010011..DMAC0_OTRIG_CH19
+ *  0b010100..DMAC0_OTRIG_CH20
+ *  0b010101..DMAC0_OTRIG_CH21
+ *  0b010110..DMAC0_OTRIG_CH22
+ *  0b010111..DMAC0_OTRIG_CH23
+ *  0b011000..DMAC0_OTRIG_CH24
+ *  0b011001..DMAC0_OTRIG_CH25
+ *  0b011010..DMAC0_OTRIG_CH26
+ *  0b011011..DMAC0_OTRIG_CH27
+ *  0b011100..DMAC0_OTRIG_CH28
+ *  0b011101..DMAC0_OTRIG_CH29
+ *  0b011110..DMAC0_OTRIG_CH30
+ *  0b011111..DMAC0_OTRIG_CH31
+ *  0b100000..DMAC0_OTRIG_CH32
+ */
+#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_SHIFT)) & INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC0_OTRIG_SEL */
+#define INPUTMUX_DMAC0_OTRIG_SEL_COUNT           (4U)
+
+/*! @name DMAC1_ITRIG_SEL - DMAC1 Input Trigger Multiplexers N */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_ITRIG_SEL_DMA1_ITRIG_SEL_MASK (0x3FU)
+#define INPUTMUX_DMAC1_ITRIG_SEL_DMA1_ITRIG_SEL_SHIFT (0U)
+/*! DMA1_ITRIG_SEL - DMA Input Triggers(n) Selection. 18:1 Selection for each. . .
+ *  0b000000..NSGPIOPINT0_INT0
+ *  0b000001..NSGPIOPINT0_INT1
+ *  0b000010..NSGPIOPINT0_INT2
+ *  0b000011..NSGPIOPINT0_INT3
+ *  0b000100..CT32BIT0_DMAREQ_M0
+ *  0b000101..CT32BIT0_DMAREQ_M1
+ *  0b000110..CT32BIT1_DMAREQ_M0
+ *  0b000111..CT32BIT1_DMAREQ_M1
+ *  0b001000..CT32BIT2_DMAREQ_M0
+ *  0b001001..CT32BIT2_DMAREQ_M1
+ *  0b001010..CT32BIT3_DMAREQ_M0
+ *  0b001011..CT32BIT3_DMAREQ_M1
+ *  0b001100..RESERVED
+ *  0b001101..RESERVED
+ *  0b001110..DMAC1_TRIGOUT_A
+ *  0b001111..DMAC1_TRIGOUT_B
+ *  0b010000..DMAC1_TRIGOUT_C
+ *  0b010001..DMAC1_TRIGOUT_D
+ *  0b010010..SCT0_DMAC0
+ *  0b010011..SCT0_DMAC1
+ *  0b010100..ENET_MAC0_DMA_REQ0
+ *  0b010101..ENET_MAC0_DMA_REQ1
+ *  0b010110..USIM_DMA_RX_SINGLE
+ *  0b010111..USIM_DMA_TX_SINGLE
+ *  0b011000..GAU_GPADC0_DMA_SINGLE
+ *  0b011001..GAU_GPADC1_DMA_SINGLE
+ *  0b011010..RESERVED
+ *  0b011011..RESERVED
+ *  0b011100..FLEXSPI_RX
+ *  0b011101..FLEXSPI_TX
+ *  0b011110..RESERVED
+ *  0b011111..RESERVED
+ *  0b100000..LCD_RX_REQ_TO_DMA_SINGLE
+ *  0b100001..LCD_TX_REQ_TO_DMA_SINGLE
+ *  0b100010..RESERVED
+ *  0b100011..RESERVED
+ *  0b100100..RESERVED
+ *  0b100101..RESERVED
+ *  0b100110..RESERVED
+ *  0b100111..RESERVED
+ *  0b101000..RESERVED
+ *  0b101001..RESERVED
+ *  0b101010..RESERVED
+ *  0b101011..RESERVED
+ *  0b101100..RESERVED
+ *  0b101101..RESERVED
+ *  0b101110..RESERVED
+ *  0b101111..RESERVED
+ *  0b110000..RESERVED
+ *  0b110001..RESERVED
+ *  0b110010..RESERVED
+ *  0b110011..RESERVED
+ *  0b110100..RESERVED
+ *  0b110101..RESERVED
+ *  0b110110..RESERVED
+ *  0b110111..RESERVED
+ *  0b111000..RESERVED
+ *  0b111001..RESERVED
+ *  0b111010..RESERVED
+ *  0b111011..RESERVED
+ *  0b111100..RESERVED
+ *  0b111101..RESERVED
+ *  0b111110..RESERVED
+ *  0b111111..RESERVED
+ */
+#define INPUTMUX_DMAC1_ITRIG_SEL_DMA1_ITRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_SEL_DMA1_ITRIG_SEL_SHIFT)) & INPUTMUX_DMAC1_ITRIG_SEL_DMA1_ITRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC1_ITRIG_SEL */
+#define INPUTMUX_DMAC1_ITRIG_SEL_COUNT           (33U)
+
+/*! @name DMAC1_OTRIG_SEL - DMAC1 Output Trigger Multiplexers N */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_OTRIG_SEL_DMA1_OTRIG_SEL_MASK (0x3FU)
+#define INPUTMUX_DMAC1_OTRIG_SEL_DMA1_OTRIG_SEL_SHIFT (0U)
+/*! DMA1_OTRIG_SEL - DMA1 Output Triggers Select for A, B, C, D IE., DMA1_OTRIG_A, DMA1_OTRIG_B,
+ *    DM1_OTRIG_C, DMA1_OTRIG_D DMA0 Output Triggers(n) Selection. 32:1 Selection for each. . .
+ *  0b000000..DMAC1_OTRIG_CH0
+ *  0b000001..DMAC1_OTRIG_CH1
+ *  0b000010..DMAC1_OTRIG_CH2
+ *  0b000011..DMAC1_OTRIG_CH3
+ *  0b000100..DMAC1_OTRIG_CH4
+ *  0b000101..DMAC1_OTRIG_CH5
+ *  0b000110..DMAC1_OTRIG_CH6
+ *  0b000111..DMAC1_OTRIG_CH7
+ *  0b001000..DMAC1_OTRIG_CH8
+ *  0b001001..DMAC1_OTRIG_CH9
+ *  0b001010..DMAC1_OTRIG_CH10
+ *  0b001011..DMAC1_OTRIG_CH11
+ *  0b001100..DMAC1_OTRIG_CH12
+ *  0b001101..DMAC1_OTRIG_CH13
+ *  0b001110..DMAC1_OTRIG_CH14
+ *  0b001111..DMAC1_OTRIG_CH15
+ *  0b010000..DMAC1_OTRIG_CH16
+ *  0b010001..DMAC1_OTRIG_CH17
+ *  0b010010..DMAC1_OTRIG_CH18
+ *  0b010011..DMAC1_OTRIG_CH19
+ *  0b010100..DMAC1_OTRIG_CH20
+ *  0b010101..DMAC1_OTRIG_CH21
+ *  0b010110..DMAC1_OTRIG_CH22
+ *  0b010111..DMAC1_OTRIG_CH23
+ *  0b011000..DMAC1_OTRIG_CH24
+ *  0b011001..DMAC1_OTRIG_CH25
+ *  0b011010..DMAC1_OTRIG_CH26
+ *  0b011011..DMAC1_OTRIG_CH27
+ *  0b011100..DMAC1_OTRIG_CH28
+ *  0b011101..DMAC1_OTRIG_CH29
+ *  0b011110..DMAC1_OTRIG_CH30
+ *  0b011111..DMAC1_OTRIG_CH31
+ *  0b100000..DMAC1_OTRIG_CH32
+ */
+#define INPUTMUX_DMAC1_OTRIG_SEL_DMA1_OTRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_OTRIG_SEL_DMA1_OTRIG_SEL_SHIFT)) & INPUTMUX_DMAC1_OTRIG_SEL_DMA1_OTRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC1_OTRIG_SEL */
+#define INPUTMUX_DMAC1_OTRIG_SEL_COUNT           (4U)
+
+/*! @name CT32BIT_CAP_SEL - CT32BIT N Counter Timer Capture Trigger Multiplexers M */
+/*! @{ */
+
+#define INPUTMUX_CT32BIT_CAP_SEL_CAPN_SEL_MASK   (0x1FU)
+#define INPUTMUX_CT32BIT_CAP_SEL_CAPN_SEL_SHIFT  (0U)
+/*! CAPN_SEL - Counter Timer m, Capture Port Input n 19:1 Mux Select. . .
+ *  0b00000..CT_INP0
+ *  0b00001..CT_INP1
+ *  0b00010..CT_INP2
+ *  0b00011..CT_INP3
+ *  0b00100..CT_INP4
+ *  0b00101..CT_INP5
+ *  0b00110..CT_INP6
+ *  0b00111..CT_INP7
+ *  0b01000..CT_INP8
+ *  0b01001..CT_INP9
+ *  0b01010..CT_INP10
+ *  0b01011..CT_INP11
+ *  0b01100..CT_INP12
+ *  0b01101..CT_INP13
+ *  0b01110..CT_INP14
+ *  0b01111..RESERVED
+ *  0b10000..SHARED I2S0_WS
+ *  0b10001..SHARED I2S1_WS
+ *  0b10010..ENET(only for timer1)
+ *  0b10011..BTU_HOST_TRIGGER_0
+ *  0b10100..BTU_HOST_TRIGGER_1
+ *  0b10101..BTU_HOST_TRIGGER_2
+ *  0b10110..FLEXCOMM_DMA_DONE0(only for timer0 and timer2)
+ *  0b10111..FLEXCOMM_DMA_DONE1(only for timer0 and timer2)
+ *  0b11000..FLEXCOMM_DMA_CMPLT_DONE0(only for timer0 and timer2)
+ *  0b11001..FLEXCOMM_DMA_CMPLT_DONE1(only for timer0 and timer2)
+ *  0b11010..RESERVED
+ *  0b11011..RESERVED
+ *  0b11100..RESERVED
+ *  0b11101..RESERVED
+ *  0b11110..RESERVED
+ *  0b11111..RESERVED
+ */
+#define INPUTMUX_CT32BIT_CAP_SEL_CAPN_SEL(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CT32BIT_CAP_SEL_CAPN_SEL_SHIFT)) & INPUTMUX_CT32BIT_CAP_SEL_CAPN_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_CT32BIT_CAP_SEL */
+#define INPUTMUX_CT32BIT_CAP_SEL_COUNT           (4U)
+
+/* The count of INPUTMUX_CT32BIT_CAP_SEL */
+#define INPUTMUX_CT32BIT_CAP_SEL_COUNT2          (4U)
+
+/*! @name FMEASURE_CH_SEL - Frequency Measurement Input Channel Multiplexers */
+/*! @{ */
+
+#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_MASK (0x1FU)
+#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_SHIFT (0U)
+/*! FMEASURE_SEL - Frequency Measure Channel n Selection 7:1 Mux Select. . .
+ *  0b00000..SYSOSC Clock
+ *  0b00001..SFRO
+ *  0b00010..FFRO
+ *  0b00011..Low Power Oscillator Clock (LPOSC)
+ *  0b00100..XTAL32K
+ *  0b00101..c0_fr_hclk
+ *  0b00110..FREQME_GPIO_CLK_IN
+ *  0b00111..T3PLL_MCU_FLEXSPI_CLK
+ *  0b01000..TDDR_MCU_FLEXSPI_CLK
+ *  0b01001..TDDR_MCU_ENET_CLK
+ *  0b01010..TCPU_MCU_FLEXSPI_CLK
+ *  0b10010..NCO_32K
+ *  0b10011..PMU_FCLK
+ *  0b10100..OSC32K_CLK_1HZ
+ *  0b10101..OSC32K_CLK_1KHZ
+ *  0b10110..LCD_FCLK
+ *  0b10111..FLEXCOMM0_FCLK
+ *  0b11000..DMIC_FCLK
+ *  0b11001..FLEXSPI0_FCLK
+ *  0b11010..TCPU_MCU_CLK
+ *  0b11011..AVPLL_CH2_CLKOUT(64M)
+ *  0b11100..RESERVED
+ *  0b11101..RESERVED
+ *  0b11110..RESERVED
+ *  0b11111..RESERVED
+ */
+#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_SHIFT)) & INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_FMEASURE_CH_SEL */
+#define INPUTMUX_FMEASURE_CH_SEL_COUNT           (2U)
+
+/*! @name DMAC0_REQ_ENA0 - DMAC0 request enable 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH0_MASK    (0x10000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH0_SHIFT   (16U)
+/*! DMIC0CH0 - DMIC0 channel 0 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH0(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH0_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH0_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH1_MASK    (0x20000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH1_SHIFT   (17U)
+/*! DMIC0CH1 - DMIC0 channel 1 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH1(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH1_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH1_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH2_MASK    (0x40000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH2_SHIFT   (18U)
+/*! DMIC0CH2 - DMIC0 channel 2 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH2(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH2_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH2_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH3_MASK    (0x80000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH3_SHIFT   (19U)
+/*! DMIC0CH3 - DMIC0 channel 3 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH3(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH3_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0CH3_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_REQ_ENA0_SET - DMAC0 request enable set 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH0_MASK (0x10000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH0_SHIFT (16U)
+/*! DMIC0CH0 - DMIC0 channel 0 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH0_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH0_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH1_MASK (0x20000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH1_SHIFT (17U)
+/*! DMIC0CH1 - DMIC0 channel 1 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH1_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH1_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH2_MASK (0x40000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH2_SHIFT (18U)
+/*! DMIC0CH2 - DMIC0 channel 2 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH2(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH2_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH2_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH3_MASK (0x80000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH3_SHIFT (19U)
+/*! DMIC0CH3 - DMIC0 channel 3 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH3(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH3_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0CH3_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_REQ_ENA0_CLR - DMAC0 request enable clear 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH0_MASK (0x10000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH0_SHIFT (16U)
+/*! DMIC0CH0 - DMIC0 channel 0 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH0_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH0_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH1_MASK (0x20000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH1_SHIFT (17U)
+/*! DMIC0CH1 - DMIC0 channel 1 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH1_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH1_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH2_MASK (0x40000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH2_SHIFT (18U)
+/*! DMIC0CH2 - DMIC0 channel 2 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH2(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH2_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH2_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH3_MASK (0x80000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH3_SHIFT (19U)
+/*! DMIC0CH3 - DMIC0 channel 3 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH3(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH3_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0CH3_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK)
+
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA0 - DMAC1 request enable 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH0_MASK    (0x10000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH0_SHIFT   (16U)
+/*! DMIC0CH0 - DMIC0 channel 0 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH0(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH0_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH0_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH1_MASK    (0x20000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH1_SHIFT   (17U)
+/*! DMIC0CH1 - DMIC0 channel 1 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH1(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH1_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH1_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH2_MASK    (0x40000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH2_SHIFT   (18U)
+/*! DMIC0CH2 - DMIC0 channel 2 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH2(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH2_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH2_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH3_MASK    (0x80000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH3_SHIFT   (19U)
+/*! DMIC0CH3 - DMIC0 channel 3 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH3(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH3_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0CH3_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA0_SET - DMAC1 request enable set 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH0_MASK (0x10000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH0_SHIFT (16U)
+/*! DMIC0CH0 - DMIC0 channel 0 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH0_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH0_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH1_MASK (0x20000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH1_SHIFT (17U)
+/*! DMIC0CH1 - DMIC0 channel 1 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH1_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH1_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH2_MASK (0x40000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH2_SHIFT (18U)
+/*! DMIC0CH2 - DMIC0 channel 2 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH2(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH2_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH2_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH3_MASK (0x80000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH3_SHIFT (19U)
+/*! DMIC0CH3 - DMIC0 channel 3 enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH3(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH3_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0CH3_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA0_CLR - DMAC1 request enable clear 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH0_MASK (0x10000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH0_SHIFT (16U)
+/*! DMIC0CH0 - DMIC0 channel 0 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH0_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH0_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH1_MASK (0x20000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH1_SHIFT (17U)
+/*! DMIC0CH1 - DMIC0 channel 1 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH1_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH1_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH2_MASK (0x40000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH2_SHIFT (18U)
+/*! DMIC0CH2 - DMIC0 channel 2 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH2(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH2_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH2_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH3_MASK (0x80000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH3_SHIFT (19U)
+/*! DMIC0CH3 - DMIC0 channel 3 enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH3(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH3_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0CH3_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK)
+
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable clear
+ *  0b0..No Effect
+ *  0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA0 - DMAC0 input trigger enable 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC0_ITRIG_INMUX0 - DMAC0 input trigger inmux 0 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC0_ITRIG_INMUX1 - DMAC0 input trigger inmux 1 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX1_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX2_MASK (0x4U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX2_SHIFT (2U)
+/*! DMAC0_ITRIG_INMUX2 - DMAC0 input trigger inmux 2 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX2_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX3_MASK (0x8U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX3_SHIFT (3U)
+/*! DMAC0_ITRIG_INMUX3 - DMAC0 input trigger inmux 3 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX3_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX4_MASK (0x10U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX4_SHIFT (4U)
+/*! DMAC0_ITRIG_INMUX4 - DMAC0 input trigger inmux 4 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX4_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX4_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX5_MASK (0x20U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX5_SHIFT (5U)
+/*! DMAC0_ITRIG_INMUX5 - DMAC0 input trigger inmux 5 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX5_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX5_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX6_MASK (0x40U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX6_SHIFT (6U)
+/*! DMAC0_ITRIG_INMUX6 - DMAC0 input trigger inmux 6 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX6_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX6_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX7_MASK (0x80U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX7_SHIFT (7U)
+/*! DMAC0_ITRIG_INMUX7 - DMAC0 input trigger inmux 7 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX7_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX7_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX8_MASK (0x100U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX8_SHIFT (8U)
+/*! DMAC0_ITRIG_INMUX8 - DMAC0 input trigger inmux 8 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX8_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX8_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX9_MASK (0x200U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX9_SHIFT (9U)
+/*! DMAC0_ITRIG_INMUX9 - DMAC0 input trigger inmux 9 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX9_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX9_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX10_MASK (0x400U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX10_SHIFT (10U)
+/*! DMAC0_ITRIG_INMUX10 - DMAC0 input trigger inmux 10 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX10_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX10_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX11_MASK (0x800U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX11_SHIFT (11U)
+/*! DMAC0_ITRIG_INMUX11 - DMAC0 input trigger inmux 11 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX11_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX11_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX12_MASK (0x1000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX12_SHIFT (12U)
+/*! DMAC0_ITRIG_INMUX12 - DMAC0 input trigger inmux 12 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX12_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX12_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX13_MASK (0x2000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX13_SHIFT (13U)
+/*! DMAC0_ITRIG_INMUX13 - DMAC0 input trigger inmux 13 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX13_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX13_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX14_MASK (0x4000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX14_SHIFT (14U)
+/*! DMAC0_ITRIG_INMUX14 - DMAC0 input trigger inmux 14 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX14_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX14_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX15_MASK (0x8000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX15_SHIFT (15U)
+/*! DMAC0_ITRIG_INMUX15 - DMAC0 input trigger inmux 15 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX15_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX15_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX16_MASK (0x10000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX16_SHIFT (16U)
+/*! DMAC0_ITRIG_INMUX16 - DMAC0 input trigger inmux 16 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX16_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX16_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX17_MASK (0x20000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX17_SHIFT (17U)
+/*! DMAC0_ITRIG_INMUX17 - DMAC0 input trigger inmux 17 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX17_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX17_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX18_MASK (0x40000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX18_SHIFT (18U)
+/*! DMAC0_ITRIG_INMUX18 - DMAC0 input trigger inmux 18 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX18_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX18_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX19_MASK (0x80000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX19_SHIFT (19U)
+/*! DMAC0_ITRIG_INMUX19 - DMAC0 input trigger inmux 19 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX19_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX19_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX20_MASK (0x100000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX20_SHIFT (20U)
+/*! DMAC0_ITRIG_INMUX20 - DMAC0 input trigger inmux 20 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX20_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX20_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX21_MASK (0x200000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX21_SHIFT (21U)
+/*! DMAC0_ITRIG_INMUX21 - DMAC0 input trigger inmux 21 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX21_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX21_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX22_MASK (0x400000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX22_SHIFT (22U)
+/*! DMAC0_ITRIG_INMUX22 - DMAC0 input trigger inmux 22 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX22_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX22_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX23_MASK (0x800000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX23_SHIFT (23U)
+/*! DMAC0_ITRIG_INMUX23 - DMAC0 input trigger inmux 23 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX23_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX23_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX24_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX24_SHIFT (24U)
+/*! DMAC0_ITRIG_INMUX24 - DMAC0 input trigger inmux 24 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX24_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX24_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX25_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX25_SHIFT (25U)
+/*! DMAC0_ITRIG_INMUX25 - DMAC0 input trigger inmux 25 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX25_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX25_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX26_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX26_SHIFT (26U)
+/*! DMAC0_ITRIG_INMUX26 - DMAC0 input trigger inmux 26 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX26_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX26_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX27_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX27_SHIFT (27U)
+/*! DMAC0_ITRIG_INMUX27 - DMAC0 input trigger inmux 27 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX27_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX27_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX28_MASK (0x10000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX28_SHIFT (28U)
+/*! DMAC0_ITRIG_INMUX28 - DMAC0 input trigger inmux 28 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX28_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX28_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX29_MASK (0x20000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX29_SHIFT (29U)
+/*! DMAC0_ITRIG_INMUX29 - DMAC0 input trigger inmux 29 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX29_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMAC0_ITRIG_INMUX29_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA1 - DMAC0 input trigger enable 1 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC0_ITRIG_INMUX0 - DMAC0 input trigger inmux 0 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC0_ITRIG_INMUX1 - DMAC0 input trigger inmux 1 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA1_DMAC0_ITRIG_INMUX1_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA0_SET - DMAC0 input trigger enable set 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC0_ITRIG_INMUX0 - DMAC0 input trigger inmux 0 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC0_ITRIG_INMUX1 - DMAC0 input trigger inmux 1 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX1_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX2_MASK (0x4U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX2_SHIFT (2U)
+/*! DMAC0_ITRIG_INMUX2 - DMAC0 input trigger inmux 2 enable set */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX2_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX3_MASK (0x8U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX3_SHIFT (3U)
+/*! DMAC0_ITRIG_INMUX3 - DMAC0 input trigger inmux 3 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX3_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX4_MASK (0x10U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX4_SHIFT (4U)
+/*! DMAC0_ITRIG_INMUX4 - DMAC0 input trigger inmux 4 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX4_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX4_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX5_MASK (0x20U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX5_SHIFT (5U)
+/*! DMAC0_ITRIG_INMUX5 - DMAC0 input trigger inmux 5 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX5_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX5_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX6_MASK (0x40U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX6_SHIFT (6U)
+/*! DMAC0_ITRIG_INMUX6 - DMAC0 input trigger inmux 6 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX6_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX6_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX7_MASK (0x80U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX7_SHIFT (7U)
+/*! DMAC0_ITRIG_INMUX7 - DMAC0 input trigger inmux 7 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX7_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX7_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX8_MASK (0x100U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX8_SHIFT (8U)
+/*! DMAC0_ITRIG_INMUX8 - DMAC0 input trigger inmux 8 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX8_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX8_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX9_MASK (0x200U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX9_SHIFT (9U)
+/*! DMAC0_ITRIG_INMUX9 - DMAC0 input trigger inmux 9 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX9_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX9_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX10_MASK (0x400U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX10_SHIFT (10U)
+/*! DMAC0_ITRIG_INMUX10 - DMAC0 input trigger inmux 10 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX10_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX10_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX11_MASK (0x800U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX11_SHIFT (11U)
+/*! DMAC0_ITRIG_INMUX11 - DMAC0 input trigger inmux 11 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX11_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX11_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX12_MASK (0x1000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX12_SHIFT (12U)
+/*! DMAC0_ITRIG_INMUX12 - DMAC0 input trigger inmux 12 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX12_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX12_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX13_MASK (0x2000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX13_SHIFT (13U)
+/*! DMAC0_ITRIG_INMUX13 - DMAC0 input trigger inmux 13 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX13_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX13_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX14_MASK (0x4000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX14_SHIFT (14U)
+/*! DMAC0_ITRIG_INMUX14 - DMAC0 input trigger inmux 14 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX14_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX14_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX15_MASK (0x8000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX15_SHIFT (15U)
+/*! DMAC0_ITRIG_INMUX15 - DMAC0 input trigger inmux 15 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX15_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX15_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX16_MASK (0x10000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX16_SHIFT (16U)
+/*! DMAC0_ITRIG_INMUX16 - DMAC0 input trigger inmux 16 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX16_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX16_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX17_MASK (0x20000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX17_SHIFT (17U)
+/*! DMAC0_ITRIG_INMUX17 - DMAC0 input trigger inmux 17 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX17_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX17_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX18_MASK (0x40000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX18_SHIFT (18U)
+/*! DMAC0_ITRIG_INMUX18 - DMAC0 input trigger inmux 18 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX18_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX18_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX19_MASK (0x80000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX19_SHIFT (19U)
+/*! DMAC0_ITRIG_INMUX19 - DMAC0 input trigger inmux 19 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX19_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX19_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX20_MASK (0x100000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX20_SHIFT (20U)
+/*! DMAC0_ITRIG_INMUX20 - DMAC0 input trigger inmux 20 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX20_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX20_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX21_MASK (0x200000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX21_SHIFT (21U)
+/*! DMAC0_ITRIG_INMUX21 - DMAC0 input trigger inmux 21 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX21_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX21_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX22_MASK (0x400000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX22_SHIFT (22U)
+/*! DMAC0_ITRIG_INMUX22 - DMAC0 input trigger inmux 22 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX22_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX22_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX23_MASK (0x800000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX23_SHIFT (23U)
+/*! DMAC0_ITRIG_INMUX23 - DMAC0 input trigger inmux 23 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX23_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX23_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX24_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX24_SHIFT (24U)
+/*! DMAC0_ITRIG_INMUX24 - DMAC0 input trigger inmux 24 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX24_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX24_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX25_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX25_SHIFT (25U)
+/*! DMAC0_ITRIG_INMUX25 - DMAC0 input trigger inmux 25 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX25_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX25_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX26_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX26_SHIFT (26U)
+/*! DMAC0_ITRIG_INMUX26 - DMAC0 input trigger inmux 26 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX26_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX26_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX27_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX27_SHIFT (27U)
+/*! DMAC0_ITRIG_INMUX27 - DMAC0 input trigger inmux 27 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX27_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX27_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX28_MASK (0x10000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX28_SHIFT (28U)
+/*! DMAC0_ITRIG_INMUX28 - DMAC0 input trigger inmux 28 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX28_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX28_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX29_MASK (0x20000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX29_SHIFT (29U)
+/*! DMAC0_ITRIG_INMUX29 - DMAC0 input trigger inmux 29 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX29_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_DMAC0_ITRIG_INMUX29_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA1_SET - DMAC0 input trigger enable set 1 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC0_ITRIG_INMUX0 - DMAC0 input trigger inmux 0 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC0_ITRIG_INMUX1 - DMAC0 input trigger inmux 1 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA1_SET_DMAC0_ITRIG_INMUX1_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA0_CLR - DMAC0 input trigger enable clear 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC0_ITRIG_INMUX0 - DMAC0 input trigger inmux 0 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC0_ITRIG_INMUX1 - DMAC0 input trigger inmux 1 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX1_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX2_MASK (0x4U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX2_SHIFT (2U)
+/*! DMAC0_ITRIG_INMUX2 - DMAC0 input trigger inmux 2 enable clear */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX2_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX3_MASK (0x8U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX3_SHIFT (3U)
+/*! DMAC0_ITRIG_INMUX3 - DMAC0 input trigger inmux 3 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX3_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX4_MASK (0x10U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX4_SHIFT (4U)
+/*! DMAC0_ITRIG_INMUX4 - DMAC0 input trigger inmux 4 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX4_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX4_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX5_MASK (0x20U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX5_SHIFT (5U)
+/*! DMAC0_ITRIG_INMUX5 - DMAC0 input trigger inmux 5 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX5_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX5_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX6_MASK (0x40U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX6_SHIFT (6U)
+/*! DMAC0_ITRIG_INMUX6 - DMAC0 input trigger inmux 6 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX6_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX6_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX7_MASK (0x80U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX7_SHIFT (7U)
+/*! DMAC0_ITRIG_INMUX7 - DMAC0 input trigger inmux 7 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX7_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX7_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX8_MASK (0x100U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX8_SHIFT (8U)
+/*! DMAC0_ITRIG_INMUX8 - DMAC0 input trigger inmux 8 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX8_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX8_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX9_MASK (0x200U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX9_SHIFT (9U)
+/*! DMAC0_ITRIG_INMUX9 - DMAC0 input trigger inmux 9 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX9_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX9_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX10_MASK (0x400U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX10_SHIFT (10U)
+/*! DMAC0_ITRIG_INMUX10 - DMAC0 input trigger inmux 10 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX10_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX10_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX11_MASK (0x800U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX11_SHIFT (11U)
+/*! DMAC0_ITRIG_INMUX11 - DMAC0 input trigger inmux 11 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX11_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX11_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX12_MASK (0x1000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX12_SHIFT (12U)
+/*! DMAC0_ITRIG_INMUX12 - DMAC0 input trigger inmux 12 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX12_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX12_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX13_MASK (0x2000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX13_SHIFT (13U)
+/*! DMAC0_ITRIG_INMUX13 - DMAC0 input trigger inmux 13 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX13_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX13_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX14_MASK (0x4000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX14_SHIFT (14U)
+/*! DMAC0_ITRIG_INMUX14 - DMAC0 input trigger inmux 14 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX14_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX14_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX15_MASK (0x8000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX15_SHIFT (15U)
+/*! DMAC0_ITRIG_INMUX15 - DMAC0 input trigger inmux 15 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX15_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX15_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX16_MASK (0x10000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX16_SHIFT (16U)
+/*! DMAC0_ITRIG_INMUX16 - DMAC0 input trigger inmux 16 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX16_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX16_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX17_MASK (0x20000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX17_SHIFT (17U)
+/*! DMAC0_ITRIG_INMUX17 - DMAC0 input trigger inmux 17 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX17_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX17_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX18_MASK (0x40000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX18_SHIFT (18U)
+/*! DMAC0_ITRIG_INMUX18 - DMAC0 input trigger inmux 18 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX18_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX18_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX19_MASK (0x80000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX19_SHIFT (19U)
+/*! DMAC0_ITRIG_INMUX19 - DMAC0 input trigger inmux 19 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX19_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX19_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX20_MASK (0x100000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX20_SHIFT (20U)
+/*! DMAC0_ITRIG_INMUX20 - DMAC0 input trigger inmux 20 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX20_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX20_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX21_MASK (0x200000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX21_SHIFT (21U)
+/*! DMAC0_ITRIG_INMUX21 - DMAC0 input trigger inmux 21 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX21_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX21_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX22_MASK (0x400000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX22_SHIFT (22U)
+/*! DMAC0_ITRIG_INMUX22 - DMAC0 input trigger inmux 22 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX22_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX22_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX23_MASK (0x800000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX23_SHIFT (23U)
+/*! DMAC0_ITRIG_INMUX23 - DMAC0 input trigger inmux 23 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX23_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX23_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX24_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX24_SHIFT (24U)
+/*! DMAC0_ITRIG_INMUX24 - DMAC0 input trigger inmux 24 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX24_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX24_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX25_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX25_SHIFT (25U)
+/*! DMAC0_ITRIG_INMUX25 - DMAC0 input trigger inmux 25 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX25_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX25_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX26_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX26_SHIFT (26U)
+/*! DMAC0_ITRIG_INMUX26 - DMAC0 input trigger inmux 26 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX26_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX26_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX27_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX27_SHIFT (27U)
+/*! DMAC0_ITRIG_INMUX27 - DMAC0 input trigger inmux 27 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX27_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX27_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX28_MASK (0x10000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX28_SHIFT (28U)
+/*! DMAC0_ITRIG_INMUX28 - DMAC0 input trigger inmux 28 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX28_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX28_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX29_MASK (0x20000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX29_SHIFT (29U)
+/*! DMAC0_ITRIG_INMUX29 - DMAC0 input trigger inmux 29 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX29_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_DMAC0_ITRIG_INMUX29_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA1_CLR - DMAC0 input trigger enable clear 1 */
+/*! @{ */
+
+#define INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC0_ITRIG_INMUX0 - DMAC0 input trigger inmux 0 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC0_ITRIG_INMUX1 - DMAC0 input trigger inmux 1 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA1_CLR_DMAC0_ITRIG_INMUX1_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA0 - DMAC1 input trigger enable 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC1_ITRIG_INMUX0 - DMAC1 input trigger inmux 0 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC1_ITRIG_INMUX1 - DMAC1 input trigger inmux 1 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX1_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX2_MASK (0x4U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX2_SHIFT (2U)
+/*! DMAC1_ITRIG_INMUX2 - DMAC1 input trigger inmux 2 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX2_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX3_MASK (0x8U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX3_SHIFT (3U)
+/*! DMAC1_ITRIG_INMUX3 - DMAC1 input trigger inmux 3 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX3_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX4_MASK (0x10U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX4_SHIFT (4U)
+/*! DMAC1_ITRIG_INMUX4 - DMAC1 input trigger inmux 4 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX4_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX4_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX5_MASK (0x20U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX5_SHIFT (5U)
+/*! DMAC1_ITRIG_INMUX5 - DMAC1 input trigger inmux 5 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX5_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX5_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX6_MASK (0x40U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX6_SHIFT (6U)
+/*! DMAC1_ITRIG_INMUX6 - DMAC1 input trigger inmux 6 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX6_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX6_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX7_MASK (0x80U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX7_SHIFT (7U)
+/*! DMAC1_ITRIG_INMUX7 - DMAC1 input trigger inmux 7 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX7_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX7_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX8_MASK (0x100U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX8_SHIFT (8U)
+/*! DMAC1_ITRIG_INMUX8 - DMAC1 input trigger inmux 8 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX8_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX8_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX9_MASK (0x200U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX9_SHIFT (9U)
+/*! DMAC1_ITRIG_INMUX9 - DMAC1 input trigger inmux 9 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX9_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX9_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX10_MASK (0x400U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX10_SHIFT (10U)
+/*! DMAC1_ITRIG_INMUX10 - DMAC1 input trigger inmux 10 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX10_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX10_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX11_MASK (0x800U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX11_SHIFT (11U)
+/*! DMAC1_ITRIG_INMUX11 - DMAC1 input trigger inmux 11 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX11_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX11_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX12_MASK (0x1000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX12_SHIFT (12U)
+/*! DMAC1_ITRIG_INMUX12 - DMAC1 input trigger inmux 12 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX12_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX12_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX13_MASK (0x2000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX13_SHIFT (13U)
+/*! DMAC1_ITRIG_INMUX13 - DMAC1 input trigger inmux 13 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX13_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX13_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX14_MASK (0x4000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX14_SHIFT (14U)
+/*! DMAC1_ITRIG_INMUX14 - DMAC1 input trigger inmux 14 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX14_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX14_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX15_MASK (0x8000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX15_SHIFT (15U)
+/*! DMAC1_ITRIG_INMUX15 - DMAC1 input trigger inmux 15 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX15_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX15_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX16_MASK (0x10000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX16_SHIFT (16U)
+/*! DMAC1_ITRIG_INMUX16 - DMAC1 input trigger inmux 16 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX16_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX16_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX17_MASK (0x20000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX17_SHIFT (17U)
+/*! DMAC1_ITRIG_INMUX17 - DMAC1 input trigger inmux 17 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX17_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX17_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX18_MASK (0x40000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX18_SHIFT (18U)
+/*! DMAC1_ITRIG_INMUX18 - DMAC1 input trigger inmux 18 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX18_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX18_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX19_MASK (0x80000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX19_SHIFT (19U)
+/*! DMAC1_ITRIG_INMUX19 - DMAC1 input trigger inmux 19 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX19_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX19_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX20_MASK (0x100000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX20_SHIFT (20U)
+/*! DMAC1_ITRIG_INMUX20 - DMAC1 input trigger inmux 20 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX20_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX20_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX21_MASK (0x200000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX21_SHIFT (21U)
+/*! DMAC1_ITRIG_INMUX21 - DMAC1 input trigger inmux 21 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX21_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX21_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX22_MASK (0x400000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX22_SHIFT (22U)
+/*! DMAC1_ITRIG_INMUX22 - DMAC1 input trigger inmux 22 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX22_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX22_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX23_MASK (0x800000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX23_SHIFT (23U)
+/*! DMAC1_ITRIG_INMUX23 - DMAC1 input trigger inmux 23 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX23_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX23_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX24_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX24_SHIFT (24U)
+/*! DMAC1_ITRIG_INMUX24 - DMAC1 input trigger inmux 24 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX24_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX24_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX25_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX25_SHIFT (25U)
+/*! DMAC1_ITRIG_INMUX25 - DMAC1 input trigger inmux 25 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX25_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX25_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX26_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX26_SHIFT (26U)
+/*! DMAC1_ITRIG_INMUX26 - DMAC1 input trigger inmux 25 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX26_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX26_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX27_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX27_SHIFT (27U)
+/*! DMAC1_ITRIG_INMUX27 - DMAC1 input trigger inmux 25 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX27_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX27_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX28_MASK (0x10000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX28_SHIFT (28U)
+/*! DMAC1_ITRIG_INMUX28 - DMAC1 input trigger inmux 25 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX28_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX28_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX29_MASK (0x20000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX29_SHIFT (29U)
+/*! DMAC1_ITRIG_INMUX29 - DMAC1 input trigger inmux 25 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX29_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMAC1_ITRIG_INMUX29_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA1 - DMAC1 input trigger enable 1 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC1_ITRIG_INMUX0 - DMAC1 input trigger inmux 0 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC1_ITRIG_INMUX1 - DMAC1 input trigger inmux 1 enable
+ *  0b0..disable
+ *  0b1..enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA1_DMAC1_ITRIG_INMUX1_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA0_SET - DMAC1 input trigger enable set 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC1_ITRIG_INMUX0 - DMAC1 input trigger inmux 0 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC1_ITRIG_INMUX1 - DMAC1 input trigger inmux 1 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX1_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX2_MASK (0x4U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX2_SHIFT (2U)
+/*! DMAC1_ITRIG_INMUX2 - DMAC1 input trigger inmux 2 enable set */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX2_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX3_MASK (0x8U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX3_SHIFT (3U)
+/*! DMAC1_ITRIG_INMUX3 - DMAC1 input trigger inmux 3 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX3_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX4_MASK (0x10U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX4_SHIFT (4U)
+/*! DMAC1_ITRIG_INMUX4 - DMAC1 input trigger inmux 4 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX4_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX4_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX5_MASK (0x20U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX5_SHIFT (5U)
+/*! DMAC1_ITRIG_INMUX5 - DMAC1 input trigger inmux 5 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX5_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX5_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX6_MASK (0x40U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX6_SHIFT (6U)
+/*! DMAC1_ITRIG_INMUX6 - DMAC1 input trigger inmux 6 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX6_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX6_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX7_MASK (0x80U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX7_SHIFT (7U)
+/*! DMAC1_ITRIG_INMUX7 - DMAC1 input trigger inmux 7 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX7_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX7_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX8_MASK (0x100U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX8_SHIFT (8U)
+/*! DMAC1_ITRIG_INMUX8 - DMAC1 input trigger inmux 8 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX8_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX8_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX9_MASK (0x200U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX9_SHIFT (9U)
+/*! DMAC1_ITRIG_INMUX9 - DMAC1 input trigger inmux 9 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX9_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX9_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX10_MASK (0x400U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX10_SHIFT (10U)
+/*! DMAC1_ITRIG_INMUX10 - DMAC1 input trigger inmux 10 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX10_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX10_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX11_MASK (0x800U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX11_SHIFT (11U)
+/*! DMAC1_ITRIG_INMUX11 - DMAC1 input trigger inmux 11 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX11_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX11_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX12_MASK (0x1000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX12_SHIFT (12U)
+/*! DMAC1_ITRIG_INMUX12 - DMAC1 input trigger inmux 12 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX12_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX12_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX13_MASK (0x2000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX13_SHIFT (13U)
+/*! DMAC1_ITRIG_INMUX13 - DMAC1 input trigger inmux 13 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX13_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX13_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX14_MASK (0x4000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX14_SHIFT (14U)
+/*! DMAC1_ITRIG_INMUX14 - DMAC1 input trigger inmux 14 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX14_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX14_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX15_MASK (0x8000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX15_SHIFT (15U)
+/*! DMAC1_ITRIG_INMUX15 - DMAC1 input trigger inmux 15 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX15_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX15_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX16_MASK (0x10000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX16_SHIFT (16U)
+/*! DMAC1_ITRIG_INMUX16 - DMAC1 input trigger inmux 16 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX16_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX16_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX17_MASK (0x20000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX17_SHIFT (17U)
+/*! DMAC1_ITRIG_INMUX17 - DMAC1 input trigger inmux 17 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX17_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX17_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX18_MASK (0x40000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX18_SHIFT (18U)
+/*! DMAC1_ITRIG_INMUX18 - DMAC1 input trigger inmux 18 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX18_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX18_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX19_MASK (0x80000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX19_SHIFT (19U)
+/*! DMAC1_ITRIG_INMUX19 - DMAC1 input trigger inmux 19 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX19_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX19_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX20_MASK (0x100000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX20_SHIFT (20U)
+/*! DMAC1_ITRIG_INMUX20 - DMAC1 input trigger inmux 20 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX20_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX20_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX21_MASK (0x200000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX21_SHIFT (21U)
+/*! DMAC1_ITRIG_INMUX21 - DMAC1 input trigger inmux 21 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX21_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX21_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX22_MASK (0x400000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX22_SHIFT (22U)
+/*! DMAC1_ITRIG_INMUX22 - DMAC1 input trigger inmux 22 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX22_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX22_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX23_MASK (0x800000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX23_SHIFT (23U)
+/*! DMAC1_ITRIG_INMUX23 - DMAC1 input trigger inmux 23 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX23_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX23_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX24_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX24_SHIFT (24U)
+/*! DMAC1_ITRIG_INMUX24 - DMAC1 input trigger inmux 24 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX24_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX24_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX25_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX25_SHIFT (25U)
+/*! DMAC1_ITRIG_INMUX25 - DMAC1 input trigger inmux 25 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX25_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX25_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX26_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX26_SHIFT (26U)
+/*! DMAC1_ITRIG_INMUX26 - DMAC1 input trigger inmux 25 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX26_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX26_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX27_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX27_SHIFT (27U)
+/*! DMAC1_ITRIG_INMUX27 - DMAC1 input trigger inmux 25 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX27_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX27_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX28_MASK (0x10000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX28_SHIFT (28U)
+/*! DMAC1_ITRIG_INMUX28 - DMAC1 input trigger inmux 25 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX28_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX28_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX29_MASK (0x20000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX29_SHIFT (29U)
+/*! DMAC1_ITRIG_INMUX29 - DMAC1 input trigger inmux 25 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX29_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_DMAC1_ITRIG_INMUX29_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA1_SET - DMAC1 input trigger enable set 1 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC1_ITRIG_INMUX0 - DMAC1 input trigger inmux 0 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC1_ITRIG_INMUX1 - DMAC1 input trigger inmux 1 enable set
+ *  0b0..No Effect
+ *  0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA1_SET_DMAC1_ITRIG_INMUX1_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA0_CLR - DMAC1 input trigger enable clear 0 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC1_ITRIG_INMUX0 - DMAC1 input trigger inmux 0 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC1_ITRIG_INMUX1 - DMAC1 input trigger inmux 1 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX1_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX2_MASK (0x4U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX2_SHIFT (2U)
+/*! DMAC1_ITRIG_INMUX2 - DMAC1 input trigger inmux 2 enable clear */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX2_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX3_MASK (0x8U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX3_SHIFT (3U)
+/*! DMAC1_ITRIG_INMUX3 - DMAC1 input trigger inmux 3 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX3_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX4_MASK (0x10U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX4_SHIFT (4U)
+/*! DMAC1_ITRIG_INMUX4 - DMAC1 input trigger inmux 4 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX4_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX4_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX5_MASK (0x20U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX5_SHIFT (5U)
+/*! DMAC1_ITRIG_INMUX5 - DMAC1 input trigger inmux 5 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX5_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX5_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX6_MASK (0x40U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX6_SHIFT (6U)
+/*! DMAC1_ITRIG_INMUX6 - DMAC1 input trigger inmux 6 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX6_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX6_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX7_MASK (0x80U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX7_SHIFT (7U)
+/*! DMAC1_ITRIG_INMUX7 - DMAC1 input trigger inmux 7 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX7_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX7_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX8_MASK (0x100U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX8_SHIFT (8U)
+/*! DMAC1_ITRIG_INMUX8 - DMAC1 input trigger inmux 8 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX8_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX8_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX9_MASK (0x200U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX9_SHIFT (9U)
+/*! DMAC1_ITRIG_INMUX9 - DMAC1 input trigger inmux 9 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX9_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX9_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX10_MASK (0x400U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX10_SHIFT (10U)
+/*! DMAC1_ITRIG_INMUX10 - DMAC1 input trigger inmux 10 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX10_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX10_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX11_MASK (0x800U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX11_SHIFT (11U)
+/*! DMAC1_ITRIG_INMUX11 - DMAC1 input trigger inmux 11 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX11_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX11_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX12_MASK (0x1000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX12_SHIFT (12U)
+/*! DMAC1_ITRIG_INMUX12 - DMAC1 input trigger inmux 12 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX12_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX12_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX13_MASK (0x2000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX13_SHIFT (13U)
+/*! DMAC1_ITRIG_INMUX13 - DMAC1 input trigger inmux 13 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX13_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX13_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX14_MASK (0x4000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX14_SHIFT (14U)
+/*! DMAC1_ITRIG_INMUX14 - DMAC1 input trigger inmux 14 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX14_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX14_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX15_MASK (0x8000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX15_SHIFT (15U)
+/*! DMAC1_ITRIG_INMUX15 - DMAC1 input trigger inmux 15 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX15_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX15_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX16_MASK (0x10000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX16_SHIFT (16U)
+/*! DMAC1_ITRIG_INMUX16 - DMAC1 input trigger inmux 16 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX16_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX16_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX17_MASK (0x20000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX17_SHIFT (17U)
+/*! DMAC1_ITRIG_INMUX17 - DMAC1 input trigger inmux 17 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX17_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX17_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX18_MASK (0x40000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX18_SHIFT (18U)
+/*! DMAC1_ITRIG_INMUX18 - DMAC1 input trigger inmux 18 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX18_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX18_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX19_MASK (0x80000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX19_SHIFT (19U)
+/*! DMAC1_ITRIG_INMUX19 - DMAC1 input trigger inmux 19 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX19_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX19_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX20_MASK (0x100000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX20_SHIFT (20U)
+/*! DMAC1_ITRIG_INMUX20 - DMAC1 input trigger inmux 20 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX20_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX20_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX21_MASK (0x200000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX21_SHIFT (21U)
+/*! DMAC1_ITRIG_INMUX21 - DMAC1 input trigger inmux 21 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX21_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX21_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX22_MASK (0x400000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX22_SHIFT (22U)
+/*! DMAC1_ITRIG_INMUX22 - DMAC1 input trigger inmux 22 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX22_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX22_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX23_MASK (0x800000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX23_SHIFT (23U)
+/*! DMAC1_ITRIG_INMUX23 - DMAC1 input trigger inmux 23 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX23_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX23_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX24_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX24_SHIFT (24U)
+/*! DMAC1_ITRIG_INMUX24 - DMAC1 input trigger inmux 24 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX24_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX24_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX25_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX25_SHIFT (25U)
+/*! DMAC1_ITRIG_INMUX25 - DMAC1 input trigger inmux 25 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX25_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX25_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX26_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX26_SHIFT (26U)
+/*! DMAC1_ITRIG_INMUX26 - DMAC1 input trigger inmux 25 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX26_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX26_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX27_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX27_SHIFT (27U)
+/*! DMAC1_ITRIG_INMUX27 - DMAC1 input trigger inmux 25 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX27_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX27_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX28_MASK (0x10000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX28_SHIFT (28U)
+/*! DMAC1_ITRIG_INMUX28 - DMAC1 input trigger inmux 25 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX28_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX28_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX29_MASK (0x20000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX29_SHIFT (29U)
+/*! DMAC1_ITRIG_INMUX29 - DMAC1 input trigger inmux 25 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX29_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_DMAC1_ITRIG_INMUX29_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA1_CLR - DMAC1 input trigger enable clear 1 */
+/*! @{ */
+
+#define INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX0_SHIFT (0U)
+/*! DMAC1_ITRIG_INMUX0 - DMAC1 input trigger inmux 0 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX0_MASK)
+
+#define INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX1_SHIFT (1U)
+/*! DMAC1_ITRIG_INMUX1 - DMAC1 input trigger inmux 1 enable clear
+ *  0b0..No Effect
+ *  0b1..clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA1_CLR_DMAC1_ITRIG_INMUX1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral INPUTMUX base address */
+  #define INPUTMUX_BASE                            (0x50026000u)
+  /** Peripheral INPUTMUX base address */
+  #define INPUTMUX_BASE_NS                         (0x40026000u)
+  /** Peripheral INPUTMUX base pointer */
+  #define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
+  /** Peripheral INPUTMUX base pointer */
+  #define INPUTMUX_NS                              ((INPUTMUX_Type *)INPUTMUX_BASE_NS)
+  /** Array initializer of INPUTMUX peripheral base addresses */
+  #define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
+  /** Array initializer of INPUTMUX peripheral base pointers */
+  #define INPUTMUX_BASE_PTRS                       { INPUTMUX }
+  /** Array initializer of INPUTMUX peripheral base addresses */
+  #define INPUTMUX_BASE_ADDRS_NS                   { INPUTMUX_BASE_NS }
+  /** Array initializer of INPUTMUX peripheral base pointers */
+  #define INPUTMUX_BASE_PTRS_NS                    { INPUTMUX_NS }
+#else
+  /** Peripheral INPUTMUX base address */
+  #define INPUTMUX_BASE                            (0x40026000u)
+  /** Peripheral INPUTMUX base pointer */
+  #define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
+  /** Array initializer of INPUTMUX peripheral base addresses */
+  #define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
+  /** Array initializer of INPUTMUX peripheral base pointers */
+  #define INPUTMUX_BASE_PTRS                       { INPUTMUX }
+#endif
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ITRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer
+ * @{
+ */
+
+/** ITRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t STATUS0;                           /**< Status0 register, offset: 0x0 */
+  __IO uint32_t STATUS1;                           /**< Status1 register, offset: 0x4 */
+  __IO uint32_t OUT0_SEL0;                         /**< ITRC_IRQ Trigger source selector 0 register for Event 0 to 15., offset: 0x8 */
+  __IO uint32_t OUT0_SEL1;                         /**< ITRC_IRQ Trigger source selector 1 register for Event 0 to 15., offset: 0xC */
+  __IO uint32_t OUT1_SEL0;                         /**< CHIP_RESET Trigger source selector 0 register for Event 0 to 15., offset: 0x10 */
+  __IO uint32_t OUT1_SEL1;                         /**< CHIP_RESET Trigger source selector 1 register for Event 0 to 15., offset: 0x14 */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t OUT0_SEL0_EVENT16_31;              /**< ITRC_IRQ Trigger source selector 0 register for Event 16 to 31., offset: 0x48 */
+  __IO uint32_t OUT0_SEL1_EVENT16_31;              /**< ITRC_IRQ Trigger source selector 1 register for Event 16 to 31., offset: 0x4C */
+  __IO uint32_t OUT1_SEL0_EVENT16_31;              /**< CHIP_RESET Trigger source selector 0 register for Event 16 to 31., offset: 0x50 */
+  __IO uint32_t OUT1_SEL1_EVENT16_31;              /**< CHIP_RESET Trigger source selector 1 register for Event 16 to 31., offset: 0x54 */
+       uint8_t RESERVED_1[152];
+  __O  uint32_t SW_EVENT0;                         /**< Software event 0, offset: 0xF0 */
+  __O  uint32_t SW_EVENT1;                         /**< Software event 1, offset: 0xF4 */
+} ITRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ITRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ITRC_Register_Masks ITRC Register Masks
+ * @{
+ */
+
+/*! @name STATUS0 - Status0 register */
+/*! @{ */
+
+#define ITRC_STATUS0_IN0_STATUS_MASK             (0x1U)
+#define ITRC_STATUS0_IN0_STATUS_SHIFT            (0U)
+/*! IN0_STATUS - CAU Temeprature Sensor detector event occurred. */
+#define ITRC_STATUS0_IN0_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN0_STATUS_SHIFT)) & ITRC_STATUS0_IN0_STATUS_MASK)
+
+#define ITRC_STATUS0_IN1_STATUS_MASK             (0x2U)
+#define ITRC_STATUS0_IN1_STATUS_SHIFT            (1U)
+/*! IN1_STATUS - PMIP Temperature Sensor detector event occurred. */
+#define ITRC_STATUS0_IN1_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN1_STATUS_SHIFT)) & ITRC_STATUS0_IN1_STATUS_MASK)
+
+#define ITRC_STATUS0_IN2_STATUS_MASK             (0x4U)
+#define ITRC_STATUS0_IN2_STATUS_SHIFT            (2U)
+/*! IN2_STATUS - Voltage Sensor detector event occured on VDD_CORE rail. */
+#define ITRC_STATUS0_IN2_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN2_STATUS_SHIFT)) & ITRC_STATUS0_IN2_STATUS_MASK)
+
+#define ITRC_STATUS0_IN3_STATUS_MASK             (0x8U)
+#define ITRC_STATUS0_IN3_STATUS_SHIFT            (3U)
+/*! IN3_STATUS - Voltage Sensor detector event occured on VDD_18 rail. */
+#define ITRC_STATUS0_IN3_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN3_STATUS_SHIFT)) & ITRC_STATUS0_IN3_STATUS_MASK)
+
+#define ITRC_STATUS0_IN4_STATUS_MASK             (0x10U)
+#define ITRC_STATUS0_IN4_STATUS_SHIFT            (4U)
+/*! IN4_STATUS - Voltage Sensor detector event occured on VDD_33 rail. */
+#define ITRC_STATUS0_IN4_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN4_STATUS_SHIFT)) & ITRC_STATUS0_IN4_STATUS_MASK)
+
+#define ITRC_STATUS0_IN5_STATUS_MASK             (0x20U)
+#define ITRC_STATUS0_IN5_STATUS_SHIFT            (5U)
+/*! IN5_STATUS - CAU Analog glitch sensor event occurred on VDD_CORE rail. */
+#define ITRC_STATUS0_IN5_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN5_STATUS_SHIFT)) & ITRC_STATUS0_IN5_STATUS_MASK)
+
+#define ITRC_STATUS0_IN6_STATUS_MASK             (0x40U)
+#define ITRC_STATUS0_IN6_STATUS_SHIFT            (6U)
+/*! IN6_STATUS - Analog Sensor configuration control anamoly detected. */
+#define ITRC_STATUS0_IN6_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN6_STATUS_SHIFT)) & ITRC_STATUS0_IN6_STATUS_MASK)
+
+#define ITRC_STATUS0_IN7_STATUS_MASK             (0x80U)
+#define ITRC_STATUS0_IN7_STATUS_SHIFT            (7U)
+/*! IN7_STATUS - AHB secure bus checkers detected illegal access. */
+#define ITRC_STATUS0_IN7_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN7_STATUS_SHIFT)) & ITRC_STATUS0_IN7_STATUS_MASK)
+
+#define ITRC_STATUS0_IN8_STATUS_MASK             (0x100U)
+#define ITRC_STATUS0_IN8_STATUS_SHIFT            (8U)
+/*! IN8_STATUS - Code watchdog detected an code execution anomaly. */
+#define ITRC_STATUS0_IN8_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN8_STATUS_SHIFT)) & ITRC_STATUS0_IN8_STATUS_MASK)
+
+#define ITRC_STATUS0_IN9_STATUS_MASK             (0x200U)
+#define ITRC_STATUS0_IN9_STATUS_SHIFT            (9U)
+/*! IN9_STATUS - ELS error event occurred. */
+#define ITRC_STATUS0_IN9_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN9_STATUS_SHIFT)) & ITRC_STATUS0_IN9_STATUS_MASK)
+
+#define ITRC_STATUS0_IN10_STATUS_MASK            (0x400U)
+#define ITRC_STATUS0_IN10_STATUS_SHIFT           (10U)
+/*! IN10_STATUS - PKC module detected an error event. */
+#define ITRC_STATUS0_IN10_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN10_STATUS_SHIFT)) & ITRC_STATUS0_IN10_STATUS_MASK)
+
+#define ITRC_STATUS0_IN11_STATUS_MASK            (0x800U)
+#define ITRC_STATUS0_IN11_STATUS_SHIFT           (11U)
+/*! IN11_STATUS - OTP module detected an error event. */
+#define ITRC_STATUS0_IN11_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN11_STATUS_SHIFT)) & ITRC_STATUS0_IN11_STATUS_MASK)
+
+#define ITRC_STATUS0_IN12_STATUS_MASK            (0x1000U)
+#define ITRC_STATUS0_IN12_STATUS_SHIFT           (12U)
+/*! IN12_STATUS - Prince IP module detected an error event. */
+#define ITRC_STATUS0_IN12_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN12_STATUS_SHIFT)) & ITRC_STATUS0_IN12_STATUS_MASK)
+
+#define ITRC_STATUS0_IN13_STATUS_MASK            (0x2000U)
+#define ITRC_STATUS0_IN13_STATUS_SHIFT           (13U)
+/*! IN13_STATUS - ELS glitch detector module detected an error event. */
+#define ITRC_STATUS0_IN13_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN13_STATUS_SHIFT)) & ITRC_STATUS0_IN13_STATUS_MASK)
+
+#define ITRC_STATUS0_IN14_STATUS_MASK            (0x4000U)
+#define ITRC_STATUS0_IN14_STATUS_SHIFT           (14U)
+/*! IN14_STATUS - Security IP Command violation error event. */
+#define ITRC_STATUS0_IN14_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN14_STATUS_SHIFT)) & ITRC_STATUS0_IN14_STATUS_MASK)
+
+#define ITRC_STATUS0_IN15_STATUS_MASK            (0x8000U)
+#define ITRC_STATUS0_IN15_STATUS_SHIFT           (15U)
+/*! IN15_STATUS - True Random Number generator error event. */
+#define ITRC_STATUS0_IN15_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_IN15_STATUS_SHIFT)) & ITRC_STATUS0_IN15_STATUS_MASK)
+
+#define ITRC_STATUS0_OUT0_STATUS_MASK            (0x10000U)
+#define ITRC_STATUS0_OUT0_STATUS_SHIFT           (16U)
+/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output. */
+#define ITRC_STATUS0_OUT0_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_OUT0_STATUS_SHIFT)) & ITRC_STATUS0_OUT0_STATUS_MASK)
+
+#define ITRC_STATUS0_OUT1_STATUS_MASK            (0x20000U)
+#define ITRC_STATUS0_OUT1_STATUS_SHIFT           (17U)
+/*! OUT1_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished. */
+#define ITRC_STATUS0_OUT1_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS0_OUT1_STATUS_SHIFT)) & ITRC_STATUS0_OUT1_STATUS_MASK)
+/*! @} */
+
+/*! @name STATUS1 - Status1 register */
+/*! @{ */
+
+#define ITRC_STATUS1_IN16_STATUS_MASK            (0x1U)
+#define ITRC_STATUS1_IN16_STATUS_SHIFT           (0U)
+/*! IN16_STATUS - PMIP Analog glitch sensor event occurred on VDD_18 rail. */
+#define ITRC_STATUS1_IN16_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN16_STATUS_SHIFT)) & ITRC_STATUS1_IN16_STATUS_MASK)
+
+#define ITRC_STATUS1_IN17_STATUS_MASK            (0x2U)
+#define ITRC_STATUS1_IN17_STATUS_SHIFT           (1U)
+/*! IN17_STATUS - PMIP Analog glitch sensor event occurred on VDD_CORE rail. */
+#define ITRC_STATUS1_IN17_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN17_STATUS_SHIFT)) & ITRC_STATUS1_IN17_STATUS_MASK)
+
+#define ITRC_STATUS1_IN18_STATUS_MASK            (0x4U)
+#define ITRC_STATUS1_IN18_STATUS_SHIFT           (2U)
+/*! IN18_STATUS - TCPU PLL UnLock Error occurred. */
+#define ITRC_STATUS1_IN18_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN18_STATUS_SHIFT)) & ITRC_STATUS1_IN18_STATUS_MASK)
+
+#define ITRC_STATUS1_IN19_STATUS_MASK            (0x8U)
+#define ITRC_STATUS1_IN19_STATUS_SHIFT           (3U)
+/*! IN19_STATUS - T3 PLL UnLock Error occurred. */
+#define ITRC_STATUS1_IN19_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN19_STATUS_SHIFT)) & ITRC_STATUS1_IN19_STATUS_MASK)
+
+#define ITRC_STATUS1_IN20_STATUS_MASK            (0x10U)
+#define ITRC_STATUS1_IN20_STATUS_SHIFT           (4U)
+/*! IN20_STATUS - Software event 0 occurred. */
+#define ITRC_STATUS1_IN20_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN20_STATUS_SHIFT)) & ITRC_STATUS1_IN20_STATUS_MASK)
+
+#define ITRC_STATUS1_IN21_STATUS_MASK            (0x20U)
+#define ITRC_STATUS1_IN21_STATUS_SHIFT           (5U)
+/*! IN21_STATUS - Software event 1 occurred. */
+#define ITRC_STATUS1_IN21_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN21_STATUS_SHIFT)) & ITRC_STATUS1_IN21_STATUS_MASK)
+/*! @} */
+
+/*! @name OUT0_SEL0 - ITRC_IRQ Trigger source selector 0 register for Event 0 to 15. */
+/*! @{ */
+
+#define ITRC_OUT0_SEL0_IN0_SEL0_MASK             (0x3U)
+#define ITRC_OUT0_SEL0_IN0_SEL0_SHIFT            (0U)
+/*! IN0_SEL0 - Selects CAU Temeprature Sensor event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN0_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN1_SEL0_MASK             (0xCU)
+#define ITRC_OUT0_SEL0_IN1_SEL0_SHIFT            (2U)
+/*! IN1_SEL0 - Selects PMIP Temperature Sensor event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN1_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN2_SEL0_MASK             (0x30U)
+#define ITRC_OUT0_SEL0_IN2_SEL0_SHIFT            (4U)
+/*! IN2_SEL0 - Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT0_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN2_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN3_SEL0_MASK             (0xC0U)
+#define ITRC_OUT0_SEL0_IN3_SEL0_SHIFT            (6U)
+/*! IN3_SEL0 - Selects Voltage Sensor detector event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT0_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN3_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN4_SEL0_MASK             (0x300U)
+#define ITRC_OUT0_SEL0_IN4_SEL0_SHIFT            (8U)
+/*! IN4_SEL0 - Selects Voltage Sensor detector event on VDD_33 rail as a trigger source. */
+#define ITRC_OUT0_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN4_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN5_SEL0_MASK             (0xC00U)
+#define ITRC_OUT0_SEL0_IN5_SEL0_SHIFT            (10U)
+/*! IN5_SEL0 - Selects Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT0_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN5_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN6_SEL0_MASK             (0x3000U)
+#define ITRC_OUT0_SEL0_IN6_SEL0_SHIFT            (12U)
+/*! IN6_SEL0 - Selects Analog Sensor configuration anamoly event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN6_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN7_SEL0_MASK             (0xC000U)
+#define ITRC_OUT0_SEL0_IN7_SEL0_SHIFT            (14U)
+/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN7_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN8_SEL0_MASK             (0x30000U)
+#define ITRC_OUT0_SEL0_IN8_SEL0_SHIFT            (16U)
+/*! IN8_SEL0 - Selects Code Watch Dog event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN8_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN9_SEL0_MASK             (0xC0000U)
+#define ITRC_OUT0_SEL0_IN9_SEL0_SHIFT            (18U)
+/*! IN9_SEL0 - Selects ELS error event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN9_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN9_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN9_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN10_SEL0_MASK            (0x300000U)
+#define ITRC_OUT0_SEL0_IN10_SEL0_SHIFT           (20U)
+/*! IN10_SEL0 - Selects PKC error event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN10_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN11_SEL0_MASK            (0xC00000U)
+#define ITRC_OUT0_SEL0_IN11_SEL0_SHIFT           (22U)
+/*! IN11_SEL0 - Selects OTP error event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN11_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN11_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN11_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN12_SEL0_MASK            (0x3000000U)
+#define ITRC_OUT0_SEL0_IN12_SEL0_SHIFT           (24U)
+/*! IN12_SEL0 - Selects PRINCE IP error event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN12_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN12_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN12_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN13_SEL0_MASK            (0xC000000U)
+#define ITRC_OUT0_SEL0_IN13_SEL0_SHIFT           (26U)
+/*! IN13_SEL0 - Selects ELS glitch detector error event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN13_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN13_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN13_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN14_SEL0_MASK            (0x30000000U)
+#define ITRC_OUT0_SEL0_IN14_SEL0_SHIFT           (28U)
+/*! IN14_SEL0 - Selects Security IP Command violation error event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN14_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_IN15_SEL0_MASK            (0xC0000000U)
+#define ITRC_OUT0_SEL0_IN15_SEL0_SHIFT           (30U)
+/*! IN15_SEL0 - Selects TRNG violation error event as a trigger source. */
+#define ITRC_OUT0_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN15_SEL0_MASK)
+/*! @} */
+
+/*! @name OUT0_SEL1 - ITRC_IRQ Trigger source selector 1 register for Event 0 to 15. */
+/*! @{ */
+
+#define ITRC_OUT0_SEL1_IN0_SEL1_MASK             (0x3U)
+#define ITRC_OUT0_SEL1_IN0_SEL1_SHIFT            (0U)
+/*! IN0_SEL1 - Selects CAU Temeprature Sensor event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN0_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN1_SEL1_MASK             (0xCU)
+#define ITRC_OUT0_SEL1_IN1_SEL1_SHIFT            (2U)
+/*! IN1_SEL1 - Selects PMIP Temperature Sensor event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN1_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN2_SEL1_MASK             (0x30U)
+#define ITRC_OUT0_SEL1_IN2_SEL1_SHIFT            (4U)
+/*! IN2_SEL1 - Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT0_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN2_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN3_SEL1_MASK             (0xC0U)
+#define ITRC_OUT0_SEL1_IN3_SEL1_SHIFT            (6U)
+/*! IN3_SEL1 - Selects Voltage Sensor detector event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT0_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN3_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN4_SEL1_MASK             (0x300U)
+#define ITRC_OUT0_SEL1_IN4_SEL1_SHIFT            (8U)
+/*! IN4_SEL1 - Selects Voltage Sensor detector event on VDD_33 rail as a trigger source. */
+#define ITRC_OUT0_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN4_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN5_SEL1_MASK             (0xC00U)
+#define ITRC_OUT0_SEL1_IN5_SEL1_SHIFT            (10U)
+/*! IN5_SEL1 - Selects Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT0_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN5_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN6_SEL1_MASK             (0x3000U)
+#define ITRC_OUT0_SEL1_IN6_SEL1_SHIFT            (12U)
+/*! IN6_SEL1 - >Selects Analog Sensor configuration anamoly event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN6_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN7_SEL1_MASK             (0xC000U)
+#define ITRC_OUT0_SEL1_IN7_SEL1_SHIFT            (14U)
+/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN7_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN8_SEL1_MASK             (0x30000U)
+#define ITRC_OUT0_SEL1_IN8_SEL1_SHIFT            (16U)
+/*! IN8_SEL1 - Selects Code Watch Dog event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN8_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN9_SEL1_MASK             (0xC0000U)
+#define ITRC_OUT0_SEL1_IN9_SEL1_SHIFT            (18U)
+/*! IN9_SEL1 - Selects ELS error event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN9_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN9_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN9_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN10_SEL1_MASK            (0x300000U)
+#define ITRC_OUT0_SEL1_IN10_SEL1_SHIFT           (20U)
+/*! IN10_SEL1 - Selects PKC error event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN10_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN11_SEL1_MASK            (0xC00000U)
+#define ITRC_OUT0_SEL1_IN11_SEL1_SHIFT           (22U)
+/*! IN11_SEL1 - Selects OTP error event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN11_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN11_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN11_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN12_SEL1_MASK            (0x3000000U)
+#define ITRC_OUT0_SEL1_IN12_SEL1_SHIFT           (24U)
+/*! IN12_SEL1 - Selects PRINCE IP error event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN12_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN12_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN12_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN13_SEL1_MASK            (0xC000000U)
+#define ITRC_OUT0_SEL1_IN13_SEL1_SHIFT           (26U)
+/*! IN13_SEL1 - Selects ELS glitch detector error event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN13_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN13_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN13_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN14_SEL1_MASK            (0x30000000U)
+#define ITRC_OUT0_SEL1_IN14_SEL1_SHIFT           (28U)
+/*! IN14_SEL1 - Selects Security IP Command violation error event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN14_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_IN15_SEL1_MASK            (0xC0000000U)
+#define ITRC_OUT0_SEL1_IN15_SEL1_SHIFT           (30U)
+/*! IN15_SEL1 - Selects TRNG violation error event as a trigger source. */
+#define ITRC_OUT0_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN15_SEL1_MASK)
+/*! @} */
+
+/*! @name OUT1_SEL0 - CHIP_RESET Trigger source selector 0 register for Event 0 to 15. */
+/*! @{ */
+
+#define ITRC_OUT1_SEL0_IN0_SEL0_MASK             (0x3U)
+#define ITRC_OUT1_SEL0_IN0_SEL0_SHIFT            (0U)
+/*! IN0_SEL0 - Selects CAU Temeprature Sensor event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN0_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN1_SEL0_MASK             (0xCU)
+#define ITRC_OUT1_SEL0_IN1_SEL0_SHIFT            (2U)
+/*! IN1_SEL0 - Selects PMIP Temperature Sensor event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN1_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN2_SEL0_MASK             (0x30U)
+#define ITRC_OUT1_SEL0_IN2_SEL0_SHIFT            (4U)
+/*! IN2_SEL0 - Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT1_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN2_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN3_SEL0_MASK             (0xC0U)
+#define ITRC_OUT1_SEL0_IN3_SEL0_SHIFT            (6U)
+/*! IN3_SEL0 - Selects Voltage Sensor detector event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT1_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN3_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN4_SEL0_MASK             (0x300U)
+#define ITRC_OUT1_SEL0_IN4_SEL0_SHIFT            (8U)
+/*! IN4_SEL0 - Selects Voltage Sensor detector event on VDD_33 rail as a trigger source. */
+#define ITRC_OUT1_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN4_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN5_SEL0_MASK             (0xC00U)
+#define ITRC_OUT1_SEL0_IN5_SEL0_SHIFT            (10U)
+/*! IN5_SEL0 - Selects Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT1_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN5_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN6_SEL0_MASK             (0x3000U)
+#define ITRC_OUT1_SEL0_IN6_SEL0_SHIFT            (12U)
+/*! IN6_SEL0 - >Selects Analog Sensor configuration anamoly event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN6_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN7_SEL0_MASK             (0xC000U)
+#define ITRC_OUT1_SEL0_IN7_SEL0_SHIFT            (14U)
+/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN7_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN8_SEL0_MASK             (0x30000U)
+#define ITRC_OUT1_SEL0_IN8_SEL0_SHIFT            (16U)
+/*! IN8_SEL0 - Selects Code Watch Dog event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN8_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN9_SEL0_MASK             (0xC0000U)
+#define ITRC_OUT1_SEL0_IN9_SEL0_SHIFT            (18U)
+/*! IN9_SEL0 - Selects ELS error event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN9_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN9_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN9_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN10_SEL0_MASK            (0x300000U)
+#define ITRC_OUT1_SEL0_IN10_SEL0_SHIFT           (20U)
+/*! IN10_SEL0 - Selects PKC error event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN10_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN11_SEL0_MASK            (0xC00000U)
+#define ITRC_OUT1_SEL0_IN11_SEL0_SHIFT           (22U)
+/*! IN11_SEL0 - Selects OTP error event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN11_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN11_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN11_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN12_SEL0_MASK            (0x3000000U)
+#define ITRC_OUT1_SEL0_IN12_SEL0_SHIFT           (24U)
+/*! IN12_SEL0 - Selects PRINCE IP error event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN12_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN12_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN12_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN13_SEL0_MASK            (0xC000000U)
+#define ITRC_OUT1_SEL0_IN13_SEL0_SHIFT           (26U)
+/*! IN13_SEL0 - Selects ELS glitch detector error event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN13_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN13_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN13_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN14_SEL0_MASK            (0x30000000U)
+#define ITRC_OUT1_SEL0_IN14_SEL0_SHIFT           (28U)
+/*! IN14_SEL0 - Selects Security IP Command violation error event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN14_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_IN15_SEL0_MASK            (0xC0000000U)
+#define ITRC_OUT1_SEL0_IN15_SEL0_SHIFT           (30U)
+/*! IN15_SEL0 - Selects TRNG violation error event as a trigger source. */
+#define ITRC_OUT1_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN15_SEL0_MASK)
+/*! @} */
+
+/*! @name OUT1_SEL1 - CHIP_RESET Trigger source selector 1 register for Event 0 to 15. */
+/*! @{ */
+
+#define ITRC_OUT1_SEL1_IN0_SEL1_MASK             (0x3U)
+#define ITRC_OUT1_SEL1_IN0_SEL1_SHIFT            (0U)
+/*! IN0_SEL1 - Selects CAU Temeprature Sensor event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN0_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN1_SEL1_MASK             (0xCU)
+#define ITRC_OUT1_SEL1_IN1_SEL1_SHIFT            (2U)
+/*! IN1_SEL1 - Selects PMIP Temperature Sensor event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN1_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN2_SEL1_MASK             (0x30U)
+#define ITRC_OUT1_SEL1_IN2_SEL1_SHIFT            (4U)
+/*! IN2_SEL1 - Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT1_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN2_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN3_SEL1_MASK             (0xC0U)
+#define ITRC_OUT1_SEL1_IN3_SEL1_SHIFT            (6U)
+/*! IN3_SEL1 - Selects Voltage Sensor detector event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT1_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN3_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN4_SEL1_MASK             (0x300U)
+#define ITRC_OUT1_SEL1_IN4_SEL1_SHIFT            (8U)
+/*! IN4_SEL1 - Selects Voltage Sensor detector event on VDD_33 rail as a trigger source. */
+#define ITRC_OUT1_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN4_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN5_SEL1_MASK             (0xC00U)
+#define ITRC_OUT1_SEL1_IN5_SEL1_SHIFT            (10U)
+/*! IN5_SEL1 - Selects Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT1_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN5_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN6_SEL1_MASK             (0x3000U)
+#define ITRC_OUT1_SEL1_IN6_SEL1_SHIFT            (12U)
+/*! IN6_SEL1 - >Selects Analog Sensor configuration anamoly event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN6_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN7_SEL1_MASK             (0xC000U)
+#define ITRC_OUT1_SEL1_IN7_SEL1_SHIFT            (14U)
+/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN7_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN8_SEL1_MASK             (0x30000U)
+#define ITRC_OUT1_SEL1_IN8_SEL1_SHIFT            (16U)
+/*! IN8_SEL1 - Selects Code Watch Dog event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN8_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN9_SEL1_MASK             (0xC0000U)
+#define ITRC_OUT1_SEL1_IN9_SEL1_SHIFT            (18U)
+/*! IN9_SEL1 - Selects ELS error event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN9_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN9_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN9_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN10_SEL1_MASK            (0x300000U)
+#define ITRC_OUT1_SEL1_IN10_SEL1_SHIFT           (20U)
+/*! IN10_SEL1 - Selects PKC error event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN10_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN11_SEL1_MASK            (0xC00000U)
+#define ITRC_OUT1_SEL1_IN11_SEL1_SHIFT           (22U)
+/*! IN11_SEL1 - Selects OTP error event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN11_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN11_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN11_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN12_SEL1_MASK            (0x3000000U)
+#define ITRC_OUT1_SEL1_IN12_SEL1_SHIFT           (24U)
+/*! IN12_SEL1 - Selects PRINCE IP error event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN12_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN12_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN12_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN13_SEL1_MASK            (0xC000000U)
+#define ITRC_OUT1_SEL1_IN13_SEL1_SHIFT           (26U)
+/*! IN13_SEL1 - Selects ELS glitch detector error event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN13_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN13_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN13_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN14_SEL1_MASK            (0x30000000U)
+#define ITRC_OUT1_SEL1_IN14_SEL1_SHIFT           (28U)
+/*! IN14_SEL1 - Selects Security IP Command violation error event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN14_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_IN15_SEL1_MASK            (0xC0000000U)
+#define ITRC_OUT1_SEL1_IN15_SEL1_SHIFT           (30U)
+/*! IN15_SEL1 - Selects TRNG violation error event as a trigger source. */
+#define ITRC_OUT1_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN15_SEL1_MASK)
+/*! @} */
+
+/*! @name OUT0_SEL0_EVENT16_31 - ITRC_IRQ Trigger source selector 0 register for Event 16 to 31. */
+/*! @{ */
+
+#define ITRC_OUT0_SEL0_EVENT16_31_IN16_SEL0_MASK (0x3U)
+#define ITRC_OUT0_SEL0_EVENT16_31_IN16_SEL0_SHIFT (0U)
+/*! IN16_SEL0 - Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT0_SEL0_EVENT16_31_IN16_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_EVENT16_31_IN16_SEL0_SHIFT)) & ITRC_OUT0_SEL0_EVENT16_31_IN16_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_EVENT16_31_IN17_SEL0_MASK (0xCU)
+#define ITRC_OUT0_SEL0_EVENT16_31_IN17_SEL0_SHIFT (2U)
+/*! IN17_SEL0 - Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT0_SEL0_EVENT16_31_IN17_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_EVENT16_31_IN17_SEL0_SHIFT)) & ITRC_OUT0_SEL0_EVENT16_31_IN17_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_EVENT16_31_IN18_SEL0_MASK (0x30U)
+#define ITRC_OUT0_SEL0_EVENT16_31_IN18_SEL0_SHIFT (4U)
+/*! IN18_SEL0 - Selects TCPU PLL Unlock event as a trigger source. */
+#define ITRC_OUT0_SEL0_EVENT16_31_IN18_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_EVENT16_31_IN18_SEL0_SHIFT)) & ITRC_OUT0_SEL0_EVENT16_31_IN18_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_EVENT16_31_IN19_SEL0_MASK (0xC0U)
+#define ITRC_OUT0_SEL0_EVENT16_31_IN19_SEL0_SHIFT (6U)
+/*! IN19_SEL0 - Selects T3 PLL Unlock event as a trigger source. */
+#define ITRC_OUT0_SEL0_EVENT16_31_IN19_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_EVENT16_31_IN19_SEL0_SHIFT)) & ITRC_OUT0_SEL0_EVENT16_31_IN19_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_EVENT16_31_IN20_SEL0_MASK (0x300U)
+#define ITRC_OUT0_SEL0_EVENT16_31_IN20_SEL0_SHIFT (8U)
+/*! IN20_SEL0 - Selects software event 0 as a trigger source. */
+#define ITRC_OUT0_SEL0_EVENT16_31_IN20_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_EVENT16_31_IN20_SEL0_SHIFT)) & ITRC_OUT0_SEL0_EVENT16_31_IN20_SEL0_MASK)
+
+#define ITRC_OUT0_SEL0_EVENT16_31_IN21_SEL0_MASK (0xC00U)
+#define ITRC_OUT0_SEL0_EVENT16_31_IN21_SEL0_SHIFT (10U)
+/*! IN21_SEL0 - Selects software event 1 as a trigger source. */
+#define ITRC_OUT0_SEL0_EVENT16_31_IN21_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_EVENT16_31_IN21_SEL0_SHIFT)) & ITRC_OUT0_SEL0_EVENT16_31_IN21_SEL0_MASK)
+/*! @} */
+
+/*! @name OUT0_SEL1_EVENT16_31 - ITRC_IRQ Trigger source selector 1 register for Event 16 to 31. */
+/*! @{ */
+
+#define ITRC_OUT0_SEL1_EVENT16_31_IN16_SEL1_MASK (0x3U)
+#define ITRC_OUT0_SEL1_EVENT16_31_IN16_SEL1_SHIFT (0U)
+/*! IN16_SEL1 - Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT0_SEL1_EVENT16_31_IN16_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_EVENT16_31_IN16_SEL1_SHIFT)) & ITRC_OUT0_SEL1_EVENT16_31_IN16_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_EVENT16_31_IN17_SEL1_MASK (0xCU)
+#define ITRC_OUT0_SEL1_EVENT16_31_IN17_SEL1_SHIFT (2U)
+/*! IN17_SEL1 - Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT0_SEL1_EVENT16_31_IN17_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_EVENT16_31_IN17_SEL1_SHIFT)) & ITRC_OUT0_SEL1_EVENT16_31_IN17_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_EVENT16_31_IN18_SEL1_MASK (0x30U)
+#define ITRC_OUT0_SEL1_EVENT16_31_IN18_SEL1_SHIFT (4U)
+/*! IN18_SEL1 - Selects TCPU PLL Unlock event as a trigger source. */
+#define ITRC_OUT0_SEL1_EVENT16_31_IN18_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_EVENT16_31_IN18_SEL1_SHIFT)) & ITRC_OUT0_SEL1_EVENT16_31_IN18_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_EVENT16_31_IN19_SEL1_MASK (0xC0U)
+#define ITRC_OUT0_SEL1_EVENT16_31_IN19_SEL1_SHIFT (6U)
+/*! IN19_SEL1 - Selects T3 PLL Unlock event as a trigger source. */
+#define ITRC_OUT0_SEL1_EVENT16_31_IN19_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_EVENT16_31_IN19_SEL1_SHIFT)) & ITRC_OUT0_SEL1_EVENT16_31_IN19_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_EVENT16_31_IN20_SEL1_MASK (0x300U)
+#define ITRC_OUT0_SEL1_EVENT16_31_IN20_SEL1_SHIFT (8U)
+/*! IN20_SEL1 - Selects software event 0 as a trigger source. */
+#define ITRC_OUT0_SEL1_EVENT16_31_IN20_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_EVENT16_31_IN20_SEL1_SHIFT)) & ITRC_OUT0_SEL1_EVENT16_31_IN20_SEL1_MASK)
+
+#define ITRC_OUT0_SEL1_EVENT16_31_IN21_SEL1_MASK (0xC00U)
+#define ITRC_OUT0_SEL1_EVENT16_31_IN21_SEL1_SHIFT (10U)
+/*! IN21_SEL1 - Selects software event 1 as a trigger source. */
+#define ITRC_OUT0_SEL1_EVENT16_31_IN21_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_EVENT16_31_IN21_SEL1_SHIFT)) & ITRC_OUT0_SEL1_EVENT16_31_IN21_SEL1_MASK)
+/*! @} */
+
+/*! @name OUT1_SEL0_EVENT16_31 - CHIP_RESET Trigger source selector 0 register for Event 16 to 31. */
+/*! @{ */
+
+#define ITRC_OUT1_SEL0_EVENT16_31_IN16_SEL0_MASK (0x3U)
+#define ITRC_OUT1_SEL0_EVENT16_31_IN16_SEL0_SHIFT (0U)
+/*! IN16_SEL0 - Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT1_SEL0_EVENT16_31_IN16_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_EVENT16_31_IN16_SEL0_SHIFT)) & ITRC_OUT1_SEL0_EVENT16_31_IN16_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_EVENT16_31_IN17_SEL0_MASK (0xCU)
+#define ITRC_OUT1_SEL0_EVENT16_31_IN17_SEL0_SHIFT (2U)
+/*! IN17_SEL0 - Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT1_SEL0_EVENT16_31_IN17_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_EVENT16_31_IN17_SEL0_SHIFT)) & ITRC_OUT1_SEL0_EVENT16_31_IN17_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_EVENT16_31_IN18_SEL0_MASK (0x30U)
+#define ITRC_OUT1_SEL0_EVENT16_31_IN18_SEL0_SHIFT (4U)
+/*! IN18_SEL0 - Selects TCPU PLL Unlock event as a trigger source. */
+#define ITRC_OUT1_SEL0_EVENT16_31_IN18_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_EVENT16_31_IN18_SEL0_SHIFT)) & ITRC_OUT1_SEL0_EVENT16_31_IN18_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_EVENT16_31_IN19_SEL0_MASK (0xC0U)
+#define ITRC_OUT1_SEL0_EVENT16_31_IN19_SEL0_SHIFT (6U)
+/*! IN19_SEL0 - Selects T3 PLL Unlock event as a trigger source. */
+#define ITRC_OUT1_SEL0_EVENT16_31_IN19_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_EVENT16_31_IN19_SEL0_SHIFT)) & ITRC_OUT1_SEL0_EVENT16_31_IN19_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_EVENT16_31_IN20_SEL0_MASK (0x300U)
+#define ITRC_OUT1_SEL0_EVENT16_31_IN20_SEL0_SHIFT (8U)
+/*! IN20_SEL0 - Selects software event 0 as a trigger source. */
+#define ITRC_OUT1_SEL0_EVENT16_31_IN20_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_EVENT16_31_IN20_SEL0_SHIFT)) & ITRC_OUT1_SEL0_EVENT16_31_IN20_SEL0_MASK)
+
+#define ITRC_OUT1_SEL0_EVENT16_31_IN21_SEL0_MASK (0xC00U)
+#define ITRC_OUT1_SEL0_EVENT16_31_IN21_SEL0_SHIFT (10U)
+/*! IN21_SEL0 - Selects software event 1 as a trigger source. */
+#define ITRC_OUT1_SEL0_EVENT16_31_IN21_SEL0(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_EVENT16_31_IN21_SEL0_SHIFT)) & ITRC_OUT1_SEL0_EVENT16_31_IN21_SEL0_MASK)
+/*! @} */
+
+/*! @name OUT1_SEL1_EVENT16_31 - CHIP_RESET Trigger source selector 1 register for Event 16 to 31. */
+/*! @{ */
+
+#define ITRC_OUT1_SEL1_EVENT16_31_IN16_SEL1_MASK (0x3U)
+#define ITRC_OUT1_SEL1_EVENT16_31_IN16_SEL1_SHIFT (0U)
+/*! IN16_SEL1 - Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source. */
+#define ITRC_OUT1_SEL1_EVENT16_31_IN16_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_EVENT16_31_IN16_SEL1_SHIFT)) & ITRC_OUT1_SEL1_EVENT16_31_IN16_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_EVENT16_31_IN17_SEL1_MASK (0xCU)
+#define ITRC_OUT1_SEL1_EVENT16_31_IN17_SEL1_SHIFT (2U)
+/*! IN17_SEL1 - Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source. */
+#define ITRC_OUT1_SEL1_EVENT16_31_IN17_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_EVENT16_31_IN17_SEL1_SHIFT)) & ITRC_OUT1_SEL1_EVENT16_31_IN17_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_EVENT16_31_IN18_SEL1_MASK (0x30U)
+#define ITRC_OUT1_SEL1_EVENT16_31_IN18_SEL1_SHIFT (4U)
+/*! IN18_SEL1 - Selects TCPU PLL Unlock event as a trigger source. */
+#define ITRC_OUT1_SEL1_EVENT16_31_IN18_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_EVENT16_31_IN18_SEL1_SHIFT)) & ITRC_OUT1_SEL1_EVENT16_31_IN18_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_EVENT16_31_IN19_SEL1_MASK (0xC0U)
+#define ITRC_OUT1_SEL1_EVENT16_31_IN19_SEL1_SHIFT (6U)
+/*! IN19_SEL1 - Selects T3 PLL Unlock event as a trigger source. */
+#define ITRC_OUT1_SEL1_EVENT16_31_IN19_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_EVENT16_31_IN19_SEL1_SHIFT)) & ITRC_OUT1_SEL1_EVENT16_31_IN19_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_EVENT16_31_IN20_SEL1_MASK (0x300U)
+#define ITRC_OUT1_SEL1_EVENT16_31_IN20_SEL1_SHIFT (8U)
+/*! IN20_SEL1 - Selects software event 0 as a trigger source. */
+#define ITRC_OUT1_SEL1_EVENT16_31_IN20_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_EVENT16_31_IN20_SEL1_SHIFT)) & ITRC_OUT1_SEL1_EVENT16_31_IN20_SEL1_MASK)
+
+#define ITRC_OUT1_SEL1_EVENT16_31_IN21_SEL1_MASK (0xC00U)
+#define ITRC_OUT1_SEL1_EVENT16_31_IN21_SEL1_SHIFT (10U)
+/*! IN21_SEL1 - Selects software event 1 as a trigger source. */
+#define ITRC_OUT1_SEL1_EVENT16_31_IN21_SEL1(x)   (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_EVENT16_31_IN21_SEL1_SHIFT)) & ITRC_OUT1_SEL1_EVENT16_31_IN21_SEL1_MASK)
+/*! @} */
+
+/*! @name SW_EVENT0 - Software event 0 */
+/*! @{ */
+
+#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK   (0xFFFFFFFFU)
+#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT  (0U)
+/*! TRIGGER_SW_EVENT_0 - Trigger software event 0. */
+#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK)
+/*! @} */
+
+/*! @name SW_EVENT1 - Software event 1 */
+/*! @{ */
+
+#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK   (0xFFFFFFFFU)
+#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT  (0U)
+/*! TRIGGER_SW_EVENT_1 - Trigger software event 1. */
+#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ITRC_Register_Masks */
+
+
+/* ITRC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral ITRC base address */
+  #define ITRC_BASE                                (0x50024000u)
+  /** Peripheral ITRC base address */
+  #define ITRC_BASE_NS                             (0x40024000u)
+  /** Peripheral ITRC base pointer */
+  #define ITRC                                     ((ITRC_Type *)ITRC_BASE)
+  /** Peripheral ITRC base pointer */
+  #define ITRC_NS                                  ((ITRC_Type *)ITRC_BASE_NS)
+  /** Array initializer of ITRC peripheral base addresses */
+  #define ITRC_BASE_ADDRS                          { ITRC_BASE }
+  /** Array initializer of ITRC peripheral base pointers */
+  #define ITRC_BASE_PTRS                           { ITRC }
+  /** Array initializer of ITRC peripheral base addresses */
+  #define ITRC_BASE_ADDRS_NS                       { ITRC_BASE_NS }
+  /** Array initializer of ITRC peripheral base pointers */
+  #define ITRC_BASE_PTRS_NS                        { ITRC_NS }
+#else
+  /** Peripheral ITRC base address */
+  #define ITRC_BASE                                (0x40024000u)
+  /** Peripheral ITRC base pointer */
+  #define ITRC                                     ((ITRC_Type *)ITRC_BASE)
+  /** Array initializer of ITRC peripheral base addresses */
+  #define ITRC_BASE_ADDRS                          { ITRC_BASE }
+  /** Array initializer of ITRC peripheral base pointers */
+  #define ITRC_BASE_PTRS                           { ITRC }
+#endif
+
+/*!
+ * @}
+ */ /* end of group ITRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LCDIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCDIC_Peripheral_Access_Layer LCDIC Peripheral Access Layer
+ * @{
+ */
+
+/** LCDIC - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CTRL;                              /**< LCDIC Control Register, offset: 0x8 */
+  __IO uint32_t FIFO_CTRL;                         /**< FIFO Control Register, offset: 0xC */
+  __IO uint32_t TIMER_CTRL;                        /**< Timer Control Register, offset: 0x10 */
+  __IO uint32_t RST_CTRL;                          /**< Reset Control Register, offset: 0x14 */
+  __IO uint32_t I8080_CTRL0;                       /**< I8080 Control0 Register, offset: 0x18 */
+  __IO uint32_t I8080_CTRL1;                       /**< I8080 Control1 Reigster, offset: 0x1C */
+  __IO uint32_t SPI_CTRL;                          /**< SPI Control, offset: 0x20 */
+  __IO uint32_t TE_CTRL;                           /**< Tearing Effect Control, offset: 0x24 */
+  __IO uint32_t TO_CTRL;                           /**< Baseline Control Register 0, offset: 0x28 */
+  __O  uint32_t TFIFO_WDATA;                       /**< Baseline Control Register 1, offset: 0x2C */
+  __I  uint32_t RFIFO_RDATA;                       /**< Baseline Control Register 2, offset: 0x30 */
+  __I  uint32_t ISR;                               /**< Interrupt Status Register, offset: 0x34 */
+  __I  uint32_t IRSR;                              /**< Interrupt Raw Status Register, offset: 0x38 */
+  __IO uint32_t ICR;                               /**< Interrupt Clear Register, offset: 0x3C */
+  __IO uint32_t IMR;                               /**< Touch Detection Control Register2, offset: 0x40 */
+  __I  uint32_t STATUS0;                           /**< Status Register, offset: 0x44 */
+  __I  uint32_t STATUS1;                           /**< Touch Detection Control Register4, offset: 0x48 */
+} LCDIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LCDIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCDIC_Register_Masks LCDIC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - LCDIC Control Register */
+/*! @{ */
+
+#define LCDIC_CTRL_LCDIC_EN_MASK                 (0x1U)
+#define LCDIC_CTRL_LCDIC_EN_SHIFT                (0U)
+/*! LCDIC_EN - LCDIC enable. */
+#define LCDIC_CTRL_LCDIC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIC_CTRL_LCDIC_EN_SHIFT)) & LCDIC_CTRL_LCDIC_EN_MASK)
+
+#define LCDIC_CTRL_LCDIC_MD_MASK                 (0x2U)
+#define LCDIC_CTRL_LCDIC_MD_SHIFT                (1U)
+/*! LCDIC_MD - LCDIC mode. */
+#define LCDIC_CTRL_LCDIC_MD(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIC_CTRL_LCDIC_MD_SHIFT)) & LCDIC_CTRL_LCDIC_MD_MASK)
+
+#define LCDIC_CTRL_SPI_MD_MASK                   (0x4U)
+#define LCDIC_CTRL_SPI_MD_SHIFT                  (2U)
+/*! SPI_MD - SPI mode. Only valid when lcdic_md = 1'd0. */
+#define LCDIC_CTRL_SPI_MD(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIC_CTRL_SPI_MD_SHIFT)) & LCDIC_CTRL_SPI_MD_MASK)
+
+#define LCDIC_CTRL_DMA_EN_MASK                   (0x8U)
+#define LCDIC_CTRL_DMA_EN_SHIFT                  (3U)
+/*! DMA_EN - DMA enable. */
+#define LCDIC_CTRL_DMA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIC_CTRL_DMA_EN_SHIFT)) & LCDIC_CTRL_DMA_EN_MASK)
+
+#define LCDIC_CTRL_DAT_ENDIAN_MASK               (0x10U)
+#define LCDIC_CTRL_DAT_ENDIAN_SHIFT              (4U)
+/*! DAT_ENDIAN - Byte data endian. */
+#define LCDIC_CTRL_DAT_ENDIAN(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIC_CTRL_DAT_ENDIAN_SHIFT)) & LCDIC_CTRL_DAT_ENDIAN_MASK)
+/*! @} */
+
+/*! @name FIFO_CTRL - FIFO Control Register */
+/*! @{ */
+
+#define LCDIC_FIFO_CTRL_TFIFO_THRES_MASK         (0x7U)
+#define LCDIC_FIFO_CTRL_TFIFO_THRES_SHIFT        (0U)
+/*! TFIFO_THRES - TX FIFO threshold. */
+#define LCDIC_FIFO_CTRL_TFIFO_THRES(x)           (((uint32_t)(((uint32_t)(x)) << LCDIC_FIFO_CTRL_TFIFO_THRES_SHIFT)) & LCDIC_FIFO_CTRL_TFIFO_THRES_MASK)
+
+#define LCDIC_FIFO_CTRL_RFIFO_THRES_MASK         (0x8U)
+#define LCDIC_FIFO_CTRL_RFIFO_THRES_SHIFT        (3U)
+/*! RFIFO_THRES - RX FIFO threshold. */
+#define LCDIC_FIFO_CTRL_RFIFO_THRES(x)           (((uint32_t)(((uint32_t)(x)) << LCDIC_FIFO_CTRL_RFIFO_THRES_SHIFT)) & LCDIC_FIFO_CTRL_RFIFO_THRES_MASK)
+/*! @} */
+
+/*! @name TIMER_CTRL - Timer Control Register */
+/*! @{ */
+
+#define LCDIC_TIMER_CTRL_TIMER_RATIO0_MASK       (0xFU)
+#define LCDIC_TIMER_CTRL_TIMER_RATIO0_SHIFT      (0U)
+/*! TIMER_RATIO0 - Timer ratio0. */
+#define LCDIC_TIMER_CTRL_TIMER_RATIO0(x)         (((uint32_t)(((uint32_t)(x)) << LCDIC_TIMER_CTRL_TIMER_RATIO0_SHIFT)) & LCDIC_TIMER_CTRL_TIMER_RATIO0_MASK)
+
+#define LCDIC_TIMER_CTRL_TIMER_RATIO1_MASK       (0xF0U)
+#define LCDIC_TIMER_CTRL_TIMER_RATIO1_SHIFT      (4U)
+/*! TIMER_RATIO1 - Timer ratio1. */
+#define LCDIC_TIMER_CTRL_TIMER_RATIO1(x)         (((uint32_t)(((uint32_t)(x)) << LCDIC_TIMER_CTRL_TIMER_RATIO1_SHIFT)) & LCDIC_TIMER_CTRL_TIMER_RATIO1_MASK)
+/*! @} */
+
+/*! @name RST_CTRL - Reset Control Register */
+/*! @{ */
+
+#define LCDIC_RST_CTRL_RST_START_MASK            (0x1U)
+#define LCDIC_RST_CTRL_RST_START_SHIFT           (0U)
+/*! RST_START - LCD reset start signal. Single pulse. */
+#define LCDIC_RST_CTRL_RST_START(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_RST_CTRL_RST_START_SHIFT)) & LCDIC_RST_CTRL_RST_START_MASK)
+
+#define LCDIC_RST_CTRL_RST_POL_MASK              (0x2U)
+#define LCDIC_RST_CTRL_RST_POL_SHIFT             (1U)
+/*! RST_POL - Reset signal polarity. */
+#define LCDIC_RST_CTRL_RST_POL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_RST_CTRL_RST_POL_SHIFT)) & LCDIC_RST_CTRL_RST_POL_MASK)
+
+#define LCDIC_RST_CTRL_RST_SEQ_NUM_MASK          (0x1CU)
+#define LCDIC_RST_CTRL_RST_SEQ_NUM_SHIFT         (2U)
+/*! RST_SEQ_NUM - Reset sequence pulse number. 3'd0: 1 pulse; 3'd7: 8 pulse. */
+#define LCDIC_RST_CTRL_RST_SEQ_NUM(x)            (((uint32_t)(((uint32_t)(x)) << LCDIC_RST_CTRL_RST_SEQ_NUM_SHIFT)) & LCDIC_RST_CTRL_RST_SEQ_NUM_MASK)
+
+#define LCDIC_RST_CTRL_RST_SEQ_MASK              (0x1FE0U)
+#define LCDIC_RST_CTRL_RST_SEQ_SHIFT             (5U)
+/*! RST_SEQ - Reset sequence. LCD_RST will send rst_seq[0] onto lcd_reset first, and then followed
+ *    by rst_seq[1] until rst_seq_num is reached.
+ */
+#define LCDIC_RST_CTRL_RST_SEQ(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_RST_CTRL_RST_SEQ_SHIFT)) & LCDIC_RST_CTRL_RST_SEQ_MASK)
+
+#define LCDIC_RST_CTRL_RST_WIDTH_MASK            (0x7E000U)
+#define LCDIC_RST_CTRL_RST_WIDTH_SHIFT           (13U)
+/*! RST_WIDTH - Width of each reset pulse. Unit is T(timer_base0). T(reset pulse) = T(timer_base0)*(rst_width+1). */
+#define LCDIC_RST_CTRL_RST_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_RST_CTRL_RST_WIDTH_SHIFT)) & LCDIC_RST_CTRL_RST_WIDTH_MASK)
+/*! @} */
+
+/*! @name I8080_CTRL0 - I8080 Control0 Register */
+/*! @{ */
+
+#define LCDIC_I8080_CTRL0_CS_POL_MASK            (0x1U)
+#define LCDIC_I8080_CTRL0_CS_POL_SHIFT           (0U)
+/*! CS_POL - CS polarity. */
+#define LCDIC_I8080_CTRL0_CS_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_CS_POL_SHIFT)) & LCDIC_I8080_CTRL0_CS_POL_MASK)
+
+#define LCDIC_I8080_CTRL0_DC_POL_MASK            (0x2U)
+#define LCDIC_I8080_CTRL0_DC_POL_SHIFT           (1U)
+/*! DC_POL - DC polarity. */
+#define LCDIC_I8080_CTRL0_DC_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_DC_POL_SHIFT)) & LCDIC_I8080_CTRL0_DC_POL_MASK)
+
+#define LCDIC_I8080_CTRL0_RD_POL_MASK            (0x4U)
+#define LCDIC_I8080_CTRL0_RD_POL_SHIFT           (2U)
+/*! RD_POL - RD polarity. */
+#define LCDIC_I8080_CTRL0_RD_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_RD_POL_SHIFT)) & LCDIC_I8080_CTRL0_RD_POL_MASK)
+
+#define LCDIC_I8080_CTRL0_WR_POL_MASK            (0x8U)
+#define LCDIC_I8080_CTRL0_WR_POL_SHIFT           (3U)
+/*! WR_POL - WR polarity. */
+#define LCDIC_I8080_CTRL0_WR_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_WR_POL_SHIFT)) & LCDIC_I8080_CTRL0_WR_POL_MASK)
+
+#define LCDIC_I8080_CTRL0_EN_DC_OFF_MASK         (0x10U)
+#define LCDIC_I8080_CTRL0_EN_DC_OFF_SHIFT        (4U)
+/*! EN_DC_OFF - CS off while DC switches. */
+#define LCDIC_I8080_CTRL0_EN_DC_OFF(x)           (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_EN_DC_OFF_SHIFT)) & LCDIC_I8080_CTRL0_EN_DC_OFF_MASK)
+
+#define LCDIC_I8080_CTRL0_EN_IDLE_OFF_MASK       (0x20U)
+#define LCDIC_I8080_CTRL0_EN_IDLE_OFF_SHIFT      (5U)
+/*! EN_IDLE_OFF - CS off while no transmission. */
+#define LCDIC_I8080_CTRL0_EN_IDLE_OFF(x)         (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_EN_IDLE_OFF_SHIFT)) & LCDIC_I8080_CTRL0_EN_IDLE_OFF_MASK)
+
+#define LCDIC_I8080_CTRL0_TCSW_MASK              (0x1C0U)
+#define LCDIC_I8080_CTRL0_TCSW_SHIFT             (6U)
+/*! TCSW - CS wait time. Minimum CS inactive pulse width. T(csw)=T(lcdic_clk)*tcsw. */
+#define LCDIC_I8080_CTRL0_TCSW(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_TCSW_SHIFT)) & LCDIC_I8080_CTRL0_TCSW_MASK)
+
+#define LCDIC_I8080_CTRL0_TCSS_MASK              (0x1FE00U)
+#define LCDIC_I8080_CTRL0_TCSS_SHIFT             (9U)
+/*! TCSS - CS setup time. Minimum CS setup time before WR/RD. T(css)=T(lcdic_clk)*tcss. */
+#define LCDIC_I8080_CTRL0_TCSS(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_TCSS_SHIFT)) & LCDIC_I8080_CTRL0_TCSS_MASK)
+
+#define LCDIC_I8080_CTRL0_TCSH_MASK              (0xE0000U)
+#define LCDIC_I8080_CTRL0_TCSH_SHIFT             (17U)
+/*! TCSH - CS hold time. Minimum CS hold time after WR/RD. T(csh)=T(lcdic_clk)*tcsh. */
+#define LCDIC_I8080_CTRL0_TCSH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_TCSH_SHIFT)) & LCDIC_I8080_CTRL0_TCSH_MASK)
+
+#define LCDIC_I8080_CTRL0_TDCS_MASK              (0x700000U)
+#define LCDIC_I8080_CTRL0_TDCS_SHIFT             (20U)
+/*! TDCS - DC setupt time. Minimum DC setup time before WR/RD/CS. T(dcs)=T(lcdic_clk)*tdcs. */
+#define LCDIC_I8080_CTRL0_TDCS(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_TDCS_SHIFT)) & LCDIC_I8080_CTRL0_TDCS_MASK)
+
+#define LCDIC_I8080_CTRL0_TDCH_MASK              (0x3800000U)
+#define LCDIC_I8080_CTRL0_TDCH_SHIFT             (23U)
+/*! TDCH - DC hold time. Minimum DC hold time after WR/RD/CS. T(dch)=T(lcdic_clk)*tdch. */
+#define LCDIC_I8080_CTRL0_TDCH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_TDCH_SHIFT)) & LCDIC_I8080_CTRL0_TDCH_MASK)
+
+#define LCDIC_I8080_CTRL0_TWDS_MASK              (0x1C000000U)
+#define LCDIC_I8080_CTRL0_TWDS_SHIFT             (26U)
+/*! TWDS - Write data setup time. Minimum write data setup time before WR active. T(wds)=T(lcdic_clk)*twds. */
+#define LCDIC_I8080_CTRL0_TWDS(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_TWDS_SHIFT)) & LCDIC_I8080_CTRL0_TWDS_MASK)
+
+#define LCDIC_I8080_CTRL0_TWDH_MASK              (0xE0000000U)
+#define LCDIC_I8080_CTRL0_TWDH_SHIFT             (29U)
+/*! TWDH - Write data hold time. Minimum write data setup time after WR active. T(wdh)=T(lcdic_clk)*twdh. */
+#define LCDIC_I8080_CTRL0_TWDH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL0_TWDH_SHIFT)) & LCDIC_I8080_CTRL0_TWDH_MASK)
+/*! @} */
+
+/*! @name I8080_CTRL1 - I8080 Control1 Reigster */
+/*! @{ */
+
+#define LCDIC_I8080_CTRL1_TWAW_MASK              (0x3FU)
+#define LCDIC_I8080_CTRL1_TWAW_SHIFT             (0U)
+/*! TWAW - Minmum write enable active pulse width. T(waw)=T(lcdic_clk)*twaw. */
+#define LCDIC_I8080_CTRL1_TWAW(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL1_TWAW_SHIFT)) & LCDIC_I8080_CTRL1_TWAW_MASK)
+
+#define LCDIC_I8080_CTRL1_TWIW_MASK              (0xFC0U)
+#define LCDIC_I8080_CTRL1_TWIW_SHIFT             (6U)
+/*! TWIW - Minmum write enable inactive pulse width. T(wiw)=T(lcdic_clk)*twiw. */
+#define LCDIC_I8080_CTRL1_TWIW(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL1_TWIW_SHIFT)) & LCDIC_I8080_CTRL1_TWIW_MASK)
+
+#define LCDIC_I8080_CTRL1_TRAW_MASK              (0xFF000U)
+#define LCDIC_I8080_CTRL1_TRAW_SHIFT             (12U)
+/*! TRAW - Minmum read enable active pulse width. T(raw)=T(lcdic_clk)*traw. */
+#define LCDIC_I8080_CTRL1_TRAW(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL1_TRAW_SHIFT)) & LCDIC_I8080_CTRL1_TRAW_MASK)
+
+#define LCDIC_I8080_CTRL1_TRIW_MASK              (0xFF00000U)
+#define LCDIC_I8080_CTRL1_TRIW_SHIFT             (20U)
+/*! TRIW - Minmum read enable inactive pulse width. T(riw)=T(lcdic_clk)*triw. */
+#define LCDIC_I8080_CTRL1_TRIW(x)                (((uint32_t)(((uint32_t)(x)) << LCDIC_I8080_CTRL1_TRIW_SHIFT)) & LCDIC_I8080_CTRL1_TRIW_MASK)
+/*! @} */
+
+/*! @name SPI_CTRL - SPI Control */
+/*! @{ */
+
+#define LCDIC_SPI_CTRL_DC_POL_MASK               (0x1U)
+#define LCDIC_SPI_CTRL_DC_POL_SHIFT              (0U)
+/*! DC_POL - DC polarity. */
+#define LCDIC_SPI_CTRL_DC_POL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIC_SPI_CTRL_DC_POL_SHIFT)) & LCDIC_SPI_CTRL_DC_POL_MASK)
+
+#define LCDIC_SPI_CTRL_CPOL_MASK                 (0x2U)
+#define LCDIC_SPI_CTRL_CPOL_SHIFT                (1U)
+/*! CPOL - SPI CPOL. */
+#define LCDIC_SPI_CTRL_CPOL(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIC_SPI_CTRL_CPOL_SHIFT)) & LCDIC_SPI_CTRL_CPOL_MASK)
+
+#define LCDIC_SPI_CTRL_CPHA_MASK                 (0x4U)
+#define LCDIC_SPI_CTRL_CPHA_SHIFT                (2U)
+/*! CPHA - SPI CPHA. */
+#define LCDIC_SPI_CTRL_CPHA(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIC_SPI_CTRL_CPHA_SHIFT)) & LCDIC_SPI_CTRL_CPHA_MASK)
+
+#define LCDIC_SPI_CTRL_SDAT_ENDIAN_MASK          (0x8U)
+#define LCDIC_SPI_CTRL_SDAT_ENDIAN_SHIFT         (3U)
+/*! SDAT_ENDIAN - SPI serial data endian. */
+#define LCDIC_SPI_CTRL_SDAT_ENDIAN(x)            (((uint32_t)(((uint32_t)(x)) << LCDIC_SPI_CTRL_SDAT_ENDIAN_SHIFT)) & LCDIC_SPI_CTRL_SDAT_ENDIAN_MASK)
+/*! @} */
+
+/*! @name TE_CTRL - Tearing Effect Control */
+/*! @{ */
+
+#define LCDIC_TE_CTRL_TTEW_MASK                  (0x3FU)
+#define LCDIC_TE_CTRL_TTEW_SHIFT                 (0U)
+/*! TTEW - Tearing effect signal synchronization wait time. Unit is T(timer_base1). T(tew)=T(timer_base1)*ttew. */
+#define LCDIC_TE_CTRL_TTEW(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIC_TE_CTRL_TTEW_SHIFT)) & LCDIC_TE_CTRL_TTEW_MASK)
+
+#define LCDIC_TE_CTRL_TE_TO_MASK                 (0xFC0U)
+#define LCDIC_TE_CTRL_TE_TO_SHIFT                (6U)
+/*! TE_TO - Tearing effect timeout time. Unit is T(timer_base1). T(te_to)=T(timer_base1)*te_to. 6'd0 means no te_to check. */
+#define LCDIC_TE_CTRL_TE_TO(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIC_TE_CTRL_TE_TO_SHIFT)) & LCDIC_TE_CTRL_TE_TO_MASK)
+/*! @} */
+
+/*! @name TO_CTRL - Baseline Control Register 0 */
+/*! @{ */
+
+#define LCDIC_TO_CTRL_CMD_SHORT_TO_MASK          (0xFU)
+#define LCDIC_TO_CTRL_CMD_SHORT_TO_SHIFT         (0U)
+/*! CMD_SHORT_TO - Command short timeout. Unit is T(timer_base0).
+ *    T(cmd_short_to)=T(timer_base0)*cmd_short_to. 4'd0 means no cmd_short_to check.
+ */
+#define LCDIC_TO_CTRL_CMD_SHORT_TO(x)            (((uint32_t)(((uint32_t)(x)) << LCDIC_TO_CTRL_CMD_SHORT_TO_SHIFT)) & LCDIC_TO_CTRL_CMD_SHORT_TO_MASK)
+
+#define LCDIC_TO_CTRL_CMD_LONG_TO_MASK           (0x3F0U)
+#define LCDIC_TO_CTRL_CMD_LONG_TO_SHIFT          (4U)
+/*! CMD_LONG_TO - Command long timeout. Unit is T(timer_base1).
+ *    T(cmd_long_to)=T(timer_base1)*cmd_long_to. 16'd0 means no cmd_long_to check.
+ */
+#define LCDIC_TO_CTRL_CMD_LONG_TO(x)             (((uint32_t)(((uint32_t)(x)) << LCDIC_TO_CTRL_CMD_LONG_TO_SHIFT)) & LCDIC_TO_CTRL_CMD_LONG_TO_MASK)
+/*! @} */
+
+/*! @name TFIFO_WDATA - Baseline Control Register 1 */
+/*! @{ */
+
+#define LCDIC_TFIFO_WDATA_TFIFO_WDATA_MASK       (0xFFFFFFFFU)
+#define LCDIC_TFIFO_WDATA_TFIFO_WDATA_SHIFT      (0U)
+/*! TFIFO_WDATA - TX FIFO write data. */
+#define LCDIC_TFIFO_WDATA_TFIFO_WDATA(x)         (((uint32_t)(((uint32_t)(x)) << LCDIC_TFIFO_WDATA_TFIFO_WDATA_SHIFT)) & LCDIC_TFIFO_WDATA_TFIFO_WDATA_MASK)
+/*! @} */
+
+/*! @name RFIFO_RDATA - Baseline Control Register 2 */
+/*! @{ */
+
+#define LCDIC_RFIFO_RDATA_RFIFO_RDATA_MASK       (0xFFFFFFFFU)
+#define LCDIC_RFIFO_RDATA_RFIFO_RDATA_SHIFT      (0U)
+/*! RFIFO_RDATA - RX FIFO read data. */
+#define LCDIC_RFIFO_RDATA_RFIFO_RDATA(x)         (((uint32_t)(((uint32_t)(x)) << LCDIC_RFIFO_RDATA_RFIFO_RDATA_SHIFT)) & LCDIC_RFIFO_RDATA_RFIFO_RDATA_MASK)
+/*! @} */
+
+/*! @name ISR - Interrupt Status Register */
+/*! @{ */
+
+#define LCDIC_ISR_RFIFO_THRES_INTR_MASK          (0x1U)
+#define LCDIC_ISR_RFIFO_THRES_INTR_SHIFT         (0U)
+/*! RFIFO_THRES_INTR - RX FIFO threshold interrupt. */
+#define LCDIC_ISR_RFIFO_THRES_INTR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_RFIFO_THRES_INTR_SHIFT)) & LCDIC_ISR_RFIFO_THRES_INTR_MASK)
+
+#define LCDIC_ISR_RFIFO_UNDERFLOW_INTR_MASK      (0x2U)
+#define LCDIC_ISR_RFIFO_UNDERFLOW_INTR_SHIFT     (1U)
+/*! RFIFO_UNDERFLOW_INTR - RX FIFO underflow interrupt. */
+#define LCDIC_ISR_RFIFO_UNDERFLOW_INTR(x)        (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_RFIFO_UNDERFLOW_INTR_SHIFT)) & LCDIC_ISR_RFIFO_UNDERFLOW_INTR_MASK)
+
+#define LCDIC_ISR_TFIFO_THRES_INTR_MASK          (0x4U)
+#define LCDIC_ISR_TFIFO_THRES_INTR_SHIFT         (2U)
+/*! TFIFO_THRES_INTR - TX FIFO threshold interrupt. */
+#define LCDIC_ISR_TFIFO_THRES_INTR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_TFIFO_THRES_INTR_SHIFT)) & LCDIC_ISR_TFIFO_THRES_INTR_MASK)
+
+#define LCDIC_ISR_TFIFO_OVERFLOW_INTR_MASK       (0x8U)
+#define LCDIC_ISR_TFIFO_OVERFLOW_INTR_SHIFT      (3U)
+/*! TFIFO_OVERFLOW_INTR - TX FIFO overflow interrupt. */
+#define LCDIC_ISR_TFIFO_OVERFLOW_INTR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_TFIFO_OVERFLOW_INTR_SHIFT)) & LCDIC_ISR_TFIFO_OVERFLOW_INTR_MASK)
+
+#define LCDIC_ISR_TE_TO_INTR_MASK                (0x10U)
+#define LCDIC_ISR_TE_TO_INTR_SHIFT               (4U)
+/*! TE_TO_INTR - TE timeout interrupt. */
+#define LCDIC_ISR_TE_TO_INTR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_TE_TO_INTR_SHIFT)) & LCDIC_ISR_TE_TO_INTR_MASK)
+
+#define LCDIC_ISR_CMD_TO_INTR_MASK               (0x20U)
+#define LCDIC_ISR_CMD_TO_INTR_SHIFT              (5U)
+/*! CMD_TO_INTR - TRX command timeout interrupt. */
+#define LCDIC_ISR_CMD_TO_INTR(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_CMD_TO_INTR_SHIFT)) & LCDIC_ISR_CMD_TO_INTR_MASK)
+
+#define LCDIC_ISR_CMD_DONE_INTR_MASK             (0x40U)
+#define LCDIC_ISR_CMD_DONE_INTR_SHIFT            (6U)
+/*! CMD_DONE_INTR - TRX command done interrupt. */
+#define LCDIC_ISR_CMD_DONE_INTR(x)               (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_CMD_DONE_INTR_SHIFT)) & LCDIC_ISR_CMD_DONE_INTR_MASK)
+
+#define LCDIC_ISR_RST_DONE_INTR_MASK             (0x80U)
+#define LCDIC_ISR_RST_DONE_INTR_SHIFT            (7U)
+/*! RST_DONE_INTR - Reset done interrupt. */
+#define LCDIC_ISR_RST_DONE_INTR(x)               (((uint32_t)(((uint32_t)(x)) << LCDIC_ISR_RST_DONE_INTR_SHIFT)) & LCDIC_ISR_RST_DONE_INTR_MASK)
+/*! @} */
+
+/*! @name IRSR - Interrupt Raw Status Register */
+/*! @{ */
+
+#define LCDIC_IRSR_RFIFO_THRES_RAW_INTR_MASK     (0x1U)
+#define LCDIC_IRSR_RFIFO_THRES_RAW_INTR_SHIFT    (0U)
+/*! RFIFO_THRES_RAW_INTR - RX FIFO threshold raw interrupt. */
+#define LCDIC_IRSR_RFIFO_THRES_RAW_INTR(x)       (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_RFIFO_THRES_RAW_INTR_SHIFT)) & LCDIC_IRSR_RFIFO_THRES_RAW_INTR_MASK)
+
+#define LCDIC_IRSR_RFIFO_UNDERFLOW_RAW_INTR_MASK (0x2U)
+#define LCDIC_IRSR_RFIFO_UNDERFLOW_RAW_INTR_SHIFT (1U)
+/*! RFIFO_UNDERFLOW_RAW_INTR - RX FIFO underflow raw interrupt. */
+#define LCDIC_IRSR_RFIFO_UNDERFLOW_RAW_INTR(x)   (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_RFIFO_UNDERFLOW_RAW_INTR_SHIFT)) & LCDIC_IRSR_RFIFO_UNDERFLOW_RAW_INTR_MASK)
+
+#define LCDIC_IRSR_TFIFO_THRES_RAW_INTR_MASK     (0x4U)
+#define LCDIC_IRSR_TFIFO_THRES_RAW_INTR_SHIFT    (2U)
+/*! TFIFO_THRES_RAW_INTR - TX FIFO threshold raw interrupt. */
+#define LCDIC_IRSR_TFIFO_THRES_RAW_INTR(x)       (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_TFIFO_THRES_RAW_INTR_SHIFT)) & LCDIC_IRSR_TFIFO_THRES_RAW_INTR_MASK)
+
+#define LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR_MASK  (0x8U)
+#define LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR_SHIFT (3U)
+/*! TFIFO_OVERFLOW_RAW_INTR - TX FIFO overflow raw interrupt. */
+#define LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR(x)    (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR_SHIFT)) & LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR_MASK)
+
+#define LCDIC_IRSR_TE_TO_RAW_INTR_MASK           (0x10U)
+#define LCDIC_IRSR_TE_TO_RAW_INTR_SHIFT          (4U)
+/*! TE_TO_RAW_INTR - TE timeout raw interrupt. */
+#define LCDIC_IRSR_TE_TO_RAW_INTR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_TE_TO_RAW_INTR_SHIFT)) & LCDIC_IRSR_TE_TO_RAW_INTR_MASK)
+
+#define LCDIC_IRSR_CMD_TO_RAW_INTR_MASK          (0x20U)
+#define LCDIC_IRSR_CMD_TO_RAW_INTR_SHIFT         (5U)
+/*! CMD_TO_RAW_INTR - TRX command timeout raw interrupt. */
+#define LCDIC_IRSR_CMD_TO_RAW_INTR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_CMD_TO_RAW_INTR_SHIFT)) & LCDIC_IRSR_CMD_TO_RAW_INTR_MASK)
+
+#define LCDIC_IRSR_CMD_DONE_RAW_INTR_MASK        (0x40U)
+#define LCDIC_IRSR_CMD_DONE_RAW_INTR_SHIFT       (6U)
+/*! CMD_DONE_RAW_INTR - TRX command done raw interrupt. */
+#define LCDIC_IRSR_CMD_DONE_RAW_INTR(x)          (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_CMD_DONE_RAW_INTR_SHIFT)) & LCDIC_IRSR_CMD_DONE_RAW_INTR_MASK)
+
+#define LCDIC_IRSR_RST_DONE_RAW_INTR_MASK        (0x80U)
+#define LCDIC_IRSR_RST_DONE_RAW_INTR_SHIFT       (7U)
+/*! RST_DONE_RAW_INTR - Reset done raw interrupt. */
+#define LCDIC_IRSR_RST_DONE_RAW_INTR(x)          (((uint32_t)(((uint32_t)(x)) << LCDIC_IRSR_RST_DONE_RAW_INTR_SHIFT)) & LCDIC_IRSR_RST_DONE_RAW_INTR_MASK)
+/*! @} */
+
+/*! @name ICR - Interrupt Clear Register */
+/*! @{ */
+
+#define LCDIC_ICR_RFIFO_THRES_INTR_CLR_MASK      (0x1U)
+#define LCDIC_ICR_RFIFO_THRES_INTR_CLR_SHIFT     (0U)
+/*! RFIFO_THRES_INTR_CLR - RX FIFO threshold interrupt clear. */
+#define LCDIC_ICR_RFIFO_THRES_INTR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_RFIFO_THRES_INTR_CLR_SHIFT)) & LCDIC_ICR_RFIFO_THRES_INTR_CLR_MASK)
+
+#define LCDIC_ICR_RFIFO_UNDERFLOW_INTR_CLR_MASK  (0x2U)
+#define LCDIC_ICR_RFIFO_UNDERFLOW_INTR_CLR_SHIFT (1U)
+/*! RFIFO_UNDERFLOW_INTR_CLR - RX FIFO underflow interrupt clear. */
+#define LCDIC_ICR_RFIFO_UNDERFLOW_INTR_CLR(x)    (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_RFIFO_UNDERFLOW_INTR_CLR_SHIFT)) & LCDIC_ICR_RFIFO_UNDERFLOW_INTR_CLR_MASK)
+
+#define LCDIC_ICR_TFIFO_THRES_INTR_CLR_MASK      (0x4U)
+#define LCDIC_ICR_TFIFO_THRES_INTR_CLR_SHIFT     (2U)
+/*! TFIFO_THRES_INTR_CLR - TX FIFO threshold interrupt clear. */
+#define LCDIC_ICR_TFIFO_THRES_INTR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_TFIFO_THRES_INTR_CLR_SHIFT)) & LCDIC_ICR_TFIFO_THRES_INTR_CLR_MASK)
+
+#define LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_MASK   (0x8U)
+#define LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_SHIFT  (3U)
+/*! TFIFO_OVERFLOW_INTR_CLR - TX FIFO overflow interrupt clear. */
+#define LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR(x)     (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_SHIFT)) & LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_MASK)
+
+#define LCDIC_ICR_TE_TO_INTR_CLR_MASK            (0x10U)
+#define LCDIC_ICR_TE_TO_INTR_CLR_SHIFT           (4U)
+/*! TE_TO_INTR_CLR - TE timeout interrupt clear. */
+#define LCDIC_ICR_TE_TO_INTR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_TE_TO_INTR_CLR_SHIFT)) & LCDIC_ICR_TE_TO_INTR_CLR_MASK)
+
+#define LCDIC_ICR_CMD_TO_INTR_CLR_MASK           (0x20U)
+#define LCDIC_ICR_CMD_TO_INTR_CLR_SHIFT          (5U)
+/*! CMD_TO_INTR_CLR - TRX command timeout interrupt clear. */
+#define LCDIC_ICR_CMD_TO_INTR_CLR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_CMD_TO_INTR_CLR_SHIFT)) & LCDIC_ICR_CMD_TO_INTR_CLR_MASK)
+
+#define LCDIC_ICR_CMD_DONE_INTR_CLR_MASK         (0x40U)
+#define LCDIC_ICR_CMD_DONE_INTR_CLR_SHIFT        (6U)
+/*! CMD_DONE_INTR_CLR - TRX command done interrupt clear. */
+#define LCDIC_ICR_CMD_DONE_INTR_CLR(x)           (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_CMD_DONE_INTR_CLR_SHIFT)) & LCDIC_ICR_CMD_DONE_INTR_CLR_MASK)
+
+#define LCDIC_ICR_RST_DONE_INTR_CLR_MASK         (0x80U)
+#define LCDIC_ICR_RST_DONE_INTR_CLR_SHIFT        (7U)
+/*! RST_DONE_INTR_CLR - Reset done interrupt clear. */
+#define LCDIC_ICR_RST_DONE_INTR_CLR(x)           (((uint32_t)(((uint32_t)(x)) << LCDIC_ICR_RST_DONE_INTR_CLR_SHIFT)) & LCDIC_ICR_RST_DONE_INTR_CLR_MASK)
+/*! @} */
+
+/*! @name IMR - Touch Detection Control Register2 */
+/*! @{ */
+
+#define LCDIC_IMR_RFIFO_THRES_INTR_MSK_MASK      (0x1U)
+#define LCDIC_IMR_RFIFO_THRES_INTR_MSK_SHIFT     (0U)
+/*! RFIFO_THRES_INTR_MSK - RX FIFO threshold interrupt mask. */
+#define LCDIC_IMR_RFIFO_THRES_INTR_MSK(x)        (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_RFIFO_THRES_INTR_MSK_SHIFT)) & LCDIC_IMR_RFIFO_THRES_INTR_MSK_MASK)
+
+#define LCDIC_IMR_RFIFO_UNDERFLOW_INTR_MSK_MASK  (0x2U)
+#define LCDIC_IMR_RFIFO_UNDERFLOW_INTR_MSK_SHIFT (1U)
+/*! RFIFO_UNDERFLOW_INTR_MSK - RX FIFO underflow interrupt mask. */
+#define LCDIC_IMR_RFIFO_UNDERFLOW_INTR_MSK(x)    (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_RFIFO_UNDERFLOW_INTR_MSK_SHIFT)) & LCDIC_IMR_RFIFO_UNDERFLOW_INTR_MSK_MASK)
+
+#define LCDIC_IMR_TFIFO_THRES_INTR_MSK_MASK      (0x4U)
+#define LCDIC_IMR_TFIFO_THRES_INTR_MSK_SHIFT     (2U)
+/*! TFIFO_THRES_INTR_MSK - TX FIFO threshold interrupt mask. */
+#define LCDIC_IMR_TFIFO_THRES_INTR_MSK(x)        (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_TFIFO_THRES_INTR_MSK_SHIFT)) & LCDIC_IMR_TFIFO_THRES_INTR_MSK_MASK)
+
+#define LCDIC_IMR_TFIFO_OVERFLOW_INTR_MSK_MASK   (0x8U)
+#define LCDIC_IMR_TFIFO_OVERFLOW_INTR_MSK_SHIFT  (3U)
+/*! TFIFO_OVERFLOW_INTR_MSK - TX FIFO overflow interrupt mask. */
+#define LCDIC_IMR_TFIFO_OVERFLOW_INTR_MSK(x)     (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_TFIFO_OVERFLOW_INTR_MSK_SHIFT)) & LCDIC_IMR_TFIFO_OVERFLOW_INTR_MSK_MASK)
+
+#define LCDIC_IMR_TE_TO_INTR_MSK_MASK            (0x10U)
+#define LCDIC_IMR_TE_TO_INTR_MSK_SHIFT           (4U)
+/*! TE_TO_INTR_MSK - TE timeout interrupt mask. */
+#define LCDIC_IMR_TE_TO_INTR_MSK(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_TE_TO_INTR_MSK_SHIFT)) & LCDIC_IMR_TE_TO_INTR_MSK_MASK)
+
+#define LCDIC_IMR_CMD_TO_INTR_MSK_MASK           (0x20U)
+#define LCDIC_IMR_CMD_TO_INTR_MSK_SHIFT          (5U)
+/*! CMD_TO_INTR_MSK - TRX command timeout interrupt mask. */
+#define LCDIC_IMR_CMD_TO_INTR_MSK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_CMD_TO_INTR_MSK_SHIFT)) & LCDIC_IMR_CMD_TO_INTR_MSK_MASK)
+
+#define LCDIC_IMR_CMD_DONE_INTR_MSK_MASK         (0x40U)
+#define LCDIC_IMR_CMD_DONE_INTR_MSK_SHIFT        (6U)
+/*! CMD_DONE_INTR_MSK - TRX command done interrupt mask. */
+#define LCDIC_IMR_CMD_DONE_INTR_MSK(x)           (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_CMD_DONE_INTR_MSK_SHIFT)) & LCDIC_IMR_CMD_DONE_INTR_MSK_MASK)
+
+#define LCDIC_IMR_RST_DONE_INTR_MSK_MASK         (0x80U)
+#define LCDIC_IMR_RST_DONE_INTR_MSK_SHIFT        (7U)
+/*! RST_DONE_INTR_MSK - Reset done interrupt mask. */
+#define LCDIC_IMR_RST_DONE_INTR_MSK(x)           (((uint32_t)(((uint32_t)(x)) << LCDIC_IMR_RST_DONE_INTR_MSK_SHIFT)) & LCDIC_IMR_RST_DONE_INTR_MSK_MASK)
+/*! @} */
+
+/*! @name STATUS0 - Status Register */
+/*! @{ */
+
+#define LCDIC_STATUS0_LCDIC_IDLE_MASK            (0x1U)
+#define LCDIC_STATUS0_LCDIC_IDLE_SHIFT           (0U)
+/*! LCDIC_IDLE - lcdic system idle. */
+#define LCDIC_STATUS0_LCDIC_IDLE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_STATUS0_LCDIC_IDLE_SHIFT)) & LCDIC_STATUS0_LCDIC_IDLE_MASK)
+
+#define LCDIC_STATUS0_TFIFO_THRES_MASK           (0x2U)
+#define LCDIC_STATUS0_TFIFO_THRES_SHIFT          (1U)
+/*! TFIFO_THRES - TX FIFO threshold status. */
+#define LCDIC_STATUS0_TFIFO_THRES(x)             (((uint32_t)(((uint32_t)(x)) << LCDIC_STATUS0_TFIFO_THRES_SHIFT)) & LCDIC_STATUS0_TFIFO_THRES_MASK)
+
+#define LCDIC_STATUS0_TFIFO_FULL_MASK            (0x4U)
+#define LCDIC_STATUS0_TFIFO_FULL_SHIFT           (2U)
+/*! TFIFO_FULL - TX FIFO full. */
+#define LCDIC_STATUS0_TFIFO_FULL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIC_STATUS0_TFIFO_FULL_SHIFT)) & LCDIC_STATUS0_TFIFO_FULL_MASK)
+
+#define LCDIC_STATUS0_RFIFO_THRES_MASK           (0x8U)
+#define LCDIC_STATUS0_RFIFO_THRES_SHIFT          (3U)
+/*! RFIFO_THRES - RX FIFO threshold status. */
+#define LCDIC_STATUS0_RFIFO_THRES(x)             (((uint32_t)(((uint32_t)(x)) << LCDIC_STATUS0_RFIFO_THRES_SHIFT)) & LCDIC_STATUS0_RFIFO_THRES_MASK)
+
+#define LCDIC_STATUS0_RFIFO_EMPTY_MASK           (0x10U)
+#define LCDIC_STATUS0_RFIFO_EMPTY_SHIFT          (4U)
+/*! RFIFO_EMPTY - RX FIFO empty. */
+#define LCDIC_STATUS0_RFIFO_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << LCDIC_STATUS0_RFIFO_EMPTY_SHIFT)) & LCDIC_STATUS0_RFIFO_EMPTY_MASK)
+
+#define LCDIC_STATUS0_TB_CNT_MASK                (0x7FFFE0U)
+#define LCDIC_STATUS0_TB_CNT_SHIFT               (5U)
+/*! TB_CNT - Transmission byte counter which indicates how many TB has been successfully transmitted. */
+#define LCDIC_STATUS0_TB_CNT(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIC_STATUS0_TB_CNT_SHIFT)) & LCDIC_STATUS0_TB_CNT_MASK)
+/*! @} */
+
+/*! @name STATUS1 - Touch Detection Control Register4 */
+/*! @{ */
+
+#define LCDIC_STATUS1_TRX_CMD_MASK               (0xFFFFFFFFU)
+#define LCDIC_STATUS1_TRX_CMD_SHIFT              (0U)
+/*! TRX_CMD - TRX command which is under processing. */
+#define LCDIC_STATUS1_TRX_CMD(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIC_STATUS1_TRX_CMD_SHIFT)) & LCDIC_STATUS1_TRX_CMD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LCDIC_Register_Masks */
+
+
+/* LCDIC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral LCDIC base address */
+  #define LCDIC_BASE                               (0x50128000u)
+  /** Peripheral LCDIC base address */
+  #define LCDIC_BASE_NS                            (0x40128000u)
+  /** Peripheral LCDIC base pointer */
+  #define LCDIC                                    ((LCDIC_Type *)LCDIC_BASE)
+  /** Peripheral LCDIC base pointer */
+  #define LCDIC_NS                                 ((LCDIC_Type *)LCDIC_BASE_NS)
+  /** Array initializer of LCDIC peripheral base addresses */
+  #define LCDIC_BASE_ADDRS                         { LCDIC_BASE }
+  /** Array initializer of LCDIC peripheral base pointers */
+  #define LCDIC_BASE_PTRS                          { LCDIC }
+  /** Array initializer of LCDIC peripheral base addresses */
+  #define LCDIC_BASE_ADDRS_NS                      { LCDIC_BASE_NS }
+  /** Array initializer of LCDIC peripheral base pointers */
+  #define LCDIC_BASE_PTRS_NS                       { LCDIC_NS }
+#else
+  /** Peripheral LCDIC base address */
+  #define LCDIC_BASE                               (0x40128000u)
+  /** Peripheral LCDIC base pointer */
+  #define LCDIC                                    ((LCDIC_Type *)LCDIC_BASE)
+  /** Array initializer of LCDIC peripheral base addresses */
+  #define LCDIC_BASE_ADDRS                         { LCDIC_BASE }
+  /** Array initializer of LCDIC peripheral base pointers */
+  #define LCDIC_BASE_PTRS                          { LCDIC }
+#endif
+/** Interrupt vectors for the LCDIC peripheral type */
+#define LCDIC_IRQS                               { LCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LCDIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCI_IO_MUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCI_IO_MUX_Peripheral_Access_Layer MCI_IO_MUX Peripheral Access Layer
+ * @{
+ */
+
+/** MCI_IO_MUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t S_GPIO;                            /**< security GPIO sel, offset: 0x0 */
+  __IO uint32_t FC0;                               /**< flexcomm0 function sel, offset: 0x4 */
+  __IO uint32_t FC1;                               /**< flexcomm1 function sel, offset: 0x8 */
+  __IO uint32_t FC2;                               /**< flexcomm2 function sel, offset: 0xC */
+  __IO uint32_t FC3;                               /**< flexcomm3 function sel, offset: 0x10 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t FC14;                              /**< flexcomm14 function sel, offset: 0x1C */
+  __IO uint32_t FSEL;                              /**< function sel, offset: 0x20 */
+  __IO uint32_t C_TIMER_IN;                        /**< ctimer input function sel, offset: 0x24 */
+  __IO uint32_t C_TIMER_OUT;                       /**< ctimer output function sel, offset: 0x28 */
+  __IO uint32_t SC_TIMER;                          /**< sctimer function sel, offset: 0x2C */
+  __IO uint32_t GPIO_GRP0;                         /**< GPIO[31:0] sel, offset: 0x30 */
+  __IO uint32_t GPIO_GRP1;                         /**< GPIO[63:32] sel, offset: 0x34 */
+} MCI_IO_MUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCI_IO_MUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCI_IO_MUX_Register_Masks MCI_IO_MUX Register Masks
+ * @{
+ */
+
+/*! @name S_GPIO - security GPIO sel */
+/*! @{ */
+
+#define MCI_IO_MUX_S_GPIO_SEL_MASK               (0xFFFFFFFFU)
+#define MCI_IO_MUX_S_GPIO_SEL_SHIFT              (0U)
+/*! SEL - spio0[31:0] selection, high valid; sel[i]->spio0[i]->GPIO[i+32] */
+#define MCI_IO_MUX_S_GPIO_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_S_GPIO_SEL_SHIFT)) & MCI_IO_MUX_S_GPIO_SEL_MASK)
+/*! @} */
+
+/*! @name FC0 - flexcomm0 function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_SCK_MASK    (0x1U)
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_SCK_SHIFT   (0U)
+/*! SEL_FC0_USART_SCK - flexcomm0:select GPIO-4 as usart sck */
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_SCK(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC0_SEL_FC0_USART_SCK_SHIFT)) & MCI_IO_MUX_FC0_SEL_FC0_USART_SCK_MASK)
+
+#define MCI_IO_MUX_FC0_SEL_FC0_I2C_MASK          (0x2U)
+#define MCI_IO_MUX_FC0_SEL_FC0_I2C_SHIFT         (1U)
+/*! SEL_FC0_I2C - flexcomm0:select GPIO-2/3 as i2c function */
+#define MCI_IO_MUX_FC0_SEL_FC0_I2C(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC0_SEL_FC0_I2C_SHIFT)) & MCI_IO_MUX_FC0_SEL_FC0_I2C_MASK)
+
+#define MCI_IO_MUX_FC0_SEL_FC0_I2S_MASK          (0x4U)
+#define MCI_IO_MUX_FC0_SEL_FC0_I2S_SHIFT         (2U)
+/*! SEL_FC0_I2S - flexcomm0:select GPIO-2/3/4 as i2s function */
+#define MCI_IO_MUX_FC0_SEL_FC0_I2S(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC0_SEL_FC0_I2S_SHIFT)) & MCI_IO_MUX_FC0_SEL_FC0_I2S_MASK)
+
+#define MCI_IO_MUX_FC0_SEL_FC0_SPI_MASK          (0x8U)
+#define MCI_IO_MUX_FC0_SEL_FC0_SPI_SHIFT         (3U)
+/*! SEL_FC0_SPI - flexcomm0:select GPIO-0/2/3/4 as spi function */
+#define MCI_IO_MUX_FC0_SEL_FC0_SPI(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC0_SEL_FC0_SPI_SHIFT)) & MCI_IO_MUX_FC0_SEL_FC0_SPI_MASK)
+
+#define MCI_IO_MUX_FC0_SEL_FC0_I2S_DATA_ONLY_MASK (0x100U)
+#define MCI_IO_MUX_FC0_SEL_FC0_I2S_DATA_ONLY_SHIFT (8U)
+/*! SEL_FC0_I2S_DATA_ONLY - flexcomm0:select GPIO-2 as i2s data */
+#define MCI_IO_MUX_FC0_SEL_FC0_I2S_DATA_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC0_SEL_FC0_I2S_DATA_ONLY_SHIFT)) & MCI_IO_MUX_FC0_SEL_FC0_I2S_DATA_ONLY_MASK)
+
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_DATA_MASK   (0x200U)
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_DATA_SHIFT  (9U)
+/*! SEL_FC0_USART_DATA - flexcomm0:select GPIO-2/3 as usart rxd/txd */
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_DATA(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC0_SEL_FC0_USART_DATA_SHIFT)) & MCI_IO_MUX_FC0_SEL_FC0_USART_DATA_MASK)
+
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_CMD_MASK    (0x400U)
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_CMD_SHIFT   (10U)
+/*! SEL_FC0_USART_CMD - flexcomm0:select GPIO-0/5 as usart cts/rts */
+#define MCI_IO_MUX_FC0_SEL_FC0_USART_CMD(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC0_SEL_FC0_USART_CMD_SHIFT)) & MCI_IO_MUX_FC0_SEL_FC0_USART_CMD_MASK)
+/*! @} */
+
+/*! @name FC1 - flexcomm1 function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_SCK_MASK    (0x1U)
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_SCK_SHIFT   (0U)
+/*! SEL_FC1_USART_SCK - flexcomm1:select GPIO-7 as usart sck */
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_SCK(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC1_SEL_FC1_USART_SCK_SHIFT)) & MCI_IO_MUX_FC1_SEL_FC1_USART_SCK_MASK)
+
+#define MCI_IO_MUX_FC1_SEL_FC1_I2C_MASK          (0x2U)
+#define MCI_IO_MUX_FC1_SEL_FC1_I2C_SHIFT         (1U)
+/*! SEL_FC1_I2C - flexcomm1:select GPIO-8/9 as i2c function */
+#define MCI_IO_MUX_FC1_SEL_FC1_I2C(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC1_SEL_FC1_I2C_SHIFT)) & MCI_IO_MUX_FC1_SEL_FC1_I2C_MASK)
+
+#define MCI_IO_MUX_FC1_SEL_FC1_I2S_MASK          (0x4U)
+#define MCI_IO_MUX_FC1_SEL_FC1_I2S_SHIFT         (2U)
+/*! SEL_FC1_I2S - flexcomm1:select GPIO-7/8/9 as i2s function */
+#define MCI_IO_MUX_FC1_SEL_FC1_I2S(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC1_SEL_FC1_I2S_SHIFT)) & MCI_IO_MUX_FC1_SEL_FC1_I2S_MASK)
+
+#define MCI_IO_MUX_FC1_SEL_FC1_SPI_MASK          (0x8U)
+#define MCI_IO_MUX_FC1_SEL_FC1_SPI_SHIFT         (3U)
+/*! SEL_FC1_SPI - flexcomm1:select GPIO-6/7/8/9 as spi function */
+#define MCI_IO_MUX_FC1_SEL_FC1_SPI(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC1_SEL_FC1_SPI_SHIFT)) & MCI_IO_MUX_FC1_SEL_FC1_SPI_MASK)
+
+#define MCI_IO_MUX_FC1_SEL_FC1_I2S_DATA_ONLY_MASK (0x100U)
+#define MCI_IO_MUX_FC1_SEL_FC1_I2S_DATA_ONLY_SHIFT (8U)
+/*! SEL_FC1_I2S_DATA_ONLY - flexcomm1:select GPIO-9 as i2s data */
+#define MCI_IO_MUX_FC1_SEL_FC1_I2S_DATA_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC1_SEL_FC1_I2S_DATA_ONLY_SHIFT)) & MCI_IO_MUX_FC1_SEL_FC1_I2S_DATA_ONLY_MASK)
+
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_DATA_MASK   (0x200U)
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_DATA_SHIFT  (9U)
+/*! SEL_FC1_USART_DATA - flexcomm1:select GPIO-8/9 as usart txd/rxd */
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_DATA(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC1_SEL_FC1_USART_DATA_SHIFT)) & MCI_IO_MUX_FC1_SEL_FC1_USART_DATA_MASK)
+
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_CMD_MASK    (0x400U)
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_CMD_SHIFT   (10U)
+/*! SEL_FC1_USART_CMD - flexcomm1:select GPIO-6/10 as usart cts/rts */
+#define MCI_IO_MUX_FC1_SEL_FC1_USART_CMD(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC1_SEL_FC1_USART_CMD_SHIFT)) & MCI_IO_MUX_FC1_SEL_FC1_USART_CMD_MASK)
+/*! @} */
+
+/*! @name FC2 - flexcomm2 function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_SCK_MASK    (0x1U)
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_SCK_SHIFT   (0U)
+/*! SEL_FC2_USART_SCK - flexcomm2:select GPIO-15 as usart sck */
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_SCK(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_USART_SCK_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_USART_SCK_MASK)
+
+#define MCI_IO_MUX_FC2_SEL_FC2_I2C_MASK          (0x2U)
+#define MCI_IO_MUX_FC2_SEL_FC2_I2C_SHIFT         (1U)
+/*! SEL_FC2_I2C - flexcomm2:select GPIO-13/14 as i2c function */
+#define MCI_IO_MUX_FC2_SEL_FC2_I2C(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_I2C_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_I2C_MASK)
+
+#define MCI_IO_MUX_FC2_SEL_FC2_I2S_MASK          (0x4U)
+#define MCI_IO_MUX_FC2_SEL_FC2_I2S_SHIFT         (2U)
+/*! SEL_FC2_I2S - flexcomm2:select GPIO-13/14/15 as i2s function */
+#define MCI_IO_MUX_FC2_SEL_FC2_I2S(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_I2S_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_I2S_MASK)
+
+#define MCI_IO_MUX_FC2_SEL_FC2_SPI_MASK          (0x8U)
+#define MCI_IO_MUX_FC2_SEL_FC2_SPI_SHIFT         (3U)
+/*! SEL_FC2_SPI - flexcomm2:select GPIO-13/14/15/16 as spi function */
+#define MCI_IO_MUX_FC2_SEL_FC2_SPI(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_SPI_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_SPI_MASK)
+
+#define MCI_IO_MUX_FC2_SEL_FC2_I2C_COPY_PIN_MASK (0x10U)
+#define MCI_IO_MUX_FC2_SEL_FC2_I2C_COPY_PIN_SHIFT (4U)
+/*! SEL_FC2_I2C_COPY_PIN - flexcomm2:select GPIO-16/17 as i2c function */
+#define MCI_IO_MUX_FC2_SEL_FC2_I2C_COPY_PIN(x)   (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_I2C_COPY_PIN_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_I2C_COPY_PIN_MASK)
+
+#define MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY_MASK (0x100U)
+#define MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY_SHIFT (8U)
+/*! SEL_FC2_I2S_DATA_ONLY - flexcomm2:select GPIO-13 as i2s data function */
+#define MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_I2S_DATA_ONLY_MASK)
+
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_DATA_MASK   (0x200U)
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_DATA_SHIFT  (9U)
+/*! SEL_FC2_USART_DATA - flexcomm2:select GPIO-13/14 as usart rxd/txd */
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_DATA(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_USART_DATA_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_USART_DATA_MASK)
+
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_CMD_MASK    (0x400U)
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_CMD_SHIFT   (10U)
+/*! SEL_FC2_USART_CMD - flexcomm2:select GPIO-16/17 as usart cts/rts */
+#define MCI_IO_MUX_FC2_SEL_FC2_USART_CMD(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC2_SEL_FC2_USART_CMD_SHIFT)) & MCI_IO_MUX_FC2_SEL_FC2_USART_CMD_MASK)
+/*! @} */
+
+/*! @name FC3 - flexcomm3 function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_SCK_MASK    (0x1U)
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_SCK_SHIFT   (0U)
+/*! SEL_FC3_USART_SCK - flexcomm3:select GPIO-25 as usart sck */
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_SCK(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_USART_SCK_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_USART_SCK_MASK)
+
+#define MCI_IO_MUX_FC3_SEL_FC3_I2C_MASK          (0x2U)
+#define MCI_IO_MUX_FC3_SEL_FC3_I2C_SHIFT         (1U)
+/*! SEL_FC3_I2C - flexcomm3:select GPIO-24/26 as i2c function */
+#define MCI_IO_MUX_FC3_SEL_FC3_I2C(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_I2C_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_I2C_MASK)
+
+#define MCI_IO_MUX_FC3_SEL_FC3_I2S_MASK          (0x4U)
+#define MCI_IO_MUX_FC3_SEL_FC3_I2S_SHIFT         (2U)
+/*! SEL_FC3_I2S - flexcomm3:select GPIO-24/25/26 as i2s function */
+#define MCI_IO_MUX_FC3_SEL_FC3_I2S(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_I2S_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_I2S_MASK)
+
+#define MCI_IO_MUX_FC3_SEL_FC3_SPI_MASK          (0x8U)
+#define MCI_IO_MUX_FC3_SEL_FC3_SPI_SHIFT         (3U)
+/*! SEL_FC3_SPI - flexcomm3:select GPIO-20/24/25/26 as spi function */
+#define MCI_IO_MUX_FC3_SEL_FC3_SPI(x)            (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_SPI_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_SPI_MASK)
+
+#define MCI_IO_MUX_FC3_SEL_FC3_I2C_COPY_PIN_MASK (0x10U)
+#define MCI_IO_MUX_FC3_SEL_FC3_I2C_COPY_PIN_SHIFT (4U)
+/*! SEL_FC3_I2C_COPY_PIN - flexcomm3:select GPIO-19/20 as i2c function */
+#define MCI_IO_MUX_FC3_SEL_FC3_I2C_COPY_PIN(x)   (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_I2C_COPY_PIN_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_I2C_COPY_PIN_MASK)
+
+#define MCI_IO_MUX_FC3_SEL_FC3_I2S_DATA_ONLY_MASK (0x100U)
+#define MCI_IO_MUX_FC3_SEL_FC3_I2S_DATA_ONLY_SHIFT (8U)
+/*! SEL_FC3_I2S_DATA_ONLY - flexcomm3:select GPIO-24 as i2s data */
+#define MCI_IO_MUX_FC3_SEL_FC3_I2S_DATA_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_I2S_DATA_ONLY_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_I2S_DATA_ONLY_MASK)
+
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_DATA_MASK   (0x200U)
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_DATA_SHIFT  (9U)
+/*! SEL_FC3_USART_DATA - flexcomm3:select GPIO-24/26 as usart rxd/txd */
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_DATA(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_USART_DATA_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_USART_DATA_MASK)
+
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_CMD_MASK    (0x400U)
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_CMD_SHIFT   (10U)
+/*! SEL_FC3_USART_CMD - flexcomm3:select GPIO-19/20 as usart rts/cts */
+#define MCI_IO_MUX_FC3_SEL_FC3_USART_CMD(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC3_SEL_FC3_USART_CMD_SHIFT)) & MCI_IO_MUX_FC3_SEL_FC3_USART_CMD_MASK)
+/*! @} */
+
+/*! @name FC14 - flexcomm14 function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_SCK_MASK  (0x1U)
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_SCK_SHIFT (0U)
+/*! SEL_FC14_USART_SCK - flexcomm14:select GPIO-54 as usart sck */
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_SCK(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC14_SEL_FC14_USART_SCK_SHIFT)) & MCI_IO_MUX_FC14_SEL_FC14_USART_SCK_MASK)
+
+#define MCI_IO_MUX_FC14_SEL_FC14_I2C_MASK        (0x2U)
+#define MCI_IO_MUX_FC14_SEL_FC14_I2C_SHIFT       (1U)
+/*! SEL_FC14_I2C - flexcomm14:select GPIO-56/57 as i2c function */
+#define MCI_IO_MUX_FC14_SEL_FC14_I2C(x)          (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC14_SEL_FC14_I2C_SHIFT)) & MCI_IO_MUX_FC14_SEL_FC14_I2C_MASK)
+
+#define MCI_IO_MUX_FC14_SEL_FC14_I2S_MASK        (0x4U)
+#define MCI_IO_MUX_FC14_SEL_FC14_I2S_SHIFT       (2U)
+/*! SEL_FC14_I2S - flexcomm14:select GPIO-54/56/57 as i2s function */
+#define MCI_IO_MUX_FC14_SEL_FC14_I2S(x)          (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC14_SEL_FC14_I2S_SHIFT)) & MCI_IO_MUX_FC14_SEL_FC14_I2S_MASK)
+
+#define MCI_IO_MUX_FC14_SEL_FC14_SPI_MASK        (0x8U)
+#define MCI_IO_MUX_FC14_SEL_FC14_SPI_SHIFT       (3U)
+/*! SEL_FC14_SPI - flexcomm14:select GPIO-53/54/56/57 as spi function */
+#define MCI_IO_MUX_FC14_SEL_FC14_SPI(x)          (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC14_SEL_FC14_SPI_SHIFT)) & MCI_IO_MUX_FC14_SEL_FC14_SPI_MASK)
+
+#define MCI_IO_MUX_FC14_SEL_FC14_I2S_DATA_ONLY_MASK (0x100U)
+#define MCI_IO_MUX_FC14_SEL_FC14_I2S_DATA_ONLY_SHIFT (8U)
+/*! SEL_FC14_I2S_DATA_ONLY - flexcomm14:select GPIO-57 as i2s data */
+#define MCI_IO_MUX_FC14_SEL_FC14_I2S_DATA_ONLY(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC14_SEL_FC14_I2S_DATA_ONLY_SHIFT)) & MCI_IO_MUX_FC14_SEL_FC14_I2S_DATA_ONLY_MASK)
+
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_DATA_MASK (0x200U)
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_DATA_SHIFT (9U)
+/*! SEL_FC14_USART_DATA - flexcomm14:select GPIO-56/57 as usart txd/rxd */
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_DATA(x)   (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC14_SEL_FC14_USART_DATA_SHIFT)) & MCI_IO_MUX_FC14_SEL_FC14_USART_DATA_MASK)
+
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_CMD_MASK  (0x400U)
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_CMD_SHIFT (10U)
+/*! SEL_FC14_USART_CMD - flexcomm14:select GPIO-53/55 as usart cts/rts */
+#define MCI_IO_MUX_FC14_SEL_FC14_USART_CMD(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FC14_SEL_FC14_USART_CMD_SHIFT)) & MCI_IO_MUX_FC14_SEL_FC14_USART_CMD_MASK)
+/*! @} */
+
+/*! @name FSEL - function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_FSEL_SEL_QUAD_SPI_FLASH_MASK  (0x2U)
+#define MCI_IO_MUX_FSEL_SEL_QUAD_SPI_FLASH_SHIFT (1U)
+/*! SEL_QUAD_SPI_FLASH - select quad_spi_flash function */
+#define MCI_IO_MUX_FSEL_SEL_QUAD_SPI_FLASH(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_QUAD_SPI_FLASH_SHIFT)) & MCI_IO_MUX_FSEL_SEL_QUAD_SPI_FLASH_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_QUAD_SPI_PSRAM_MASK  (0x8U)
+#define MCI_IO_MUX_FSEL_SEL_QUAD_SPI_PSRAM_SHIFT (3U)
+/*! SEL_QUAD_SPI_PSRAM - select quad_spi_psram function */
+#define MCI_IO_MUX_FSEL_SEL_QUAD_SPI_PSRAM(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_QUAD_SPI_PSRAM_SHIFT)) & MCI_IO_MUX_FSEL_SEL_QUAD_SPI_PSRAM_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_PDM_MASK             (0x10U)
+#define MCI_IO_MUX_FSEL_SEL_PDM_SHIFT            (4U)
+/*! SEL_PDM - select pdm function */
+#define MCI_IO_MUX_FSEL_SEL_PDM(x)               (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_PDM_SHIFT)) & MCI_IO_MUX_FSEL_SEL_PDM_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_USB_MASK             (0x20U)
+#define MCI_IO_MUX_FSEL_SEL_USB_SHIFT            (5U)
+/*! SEL_USB - select usb function */
+#define MCI_IO_MUX_FSEL_SEL_USB(x)               (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_USB_SHIFT)) & MCI_IO_MUX_FSEL_SEL_USB_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_MCLK_MASK            (0x40U)
+#define MCI_IO_MUX_FSEL_SEL_MCLK_SHIFT           (6U)
+/*! SEL_MCLK - select mclk function */
+#define MCI_IO_MUX_FSEL_SEL_MCLK(x)              (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_MCLK_SHIFT)) & MCI_IO_MUX_FSEL_SEL_MCLK_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_UTICK_MASK           (0x200U)
+#define MCI_IO_MUX_FSEL_SEL_UTICK_SHIFT          (9U)
+/*! SEL_UTICK - select utick function */
+#define MCI_IO_MUX_FSEL_SEL_UTICK(x)             (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_UTICK_SHIFT)) & MCI_IO_MUX_FSEL_SEL_UTICK_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_USIM_MASK            (0x400U)
+#define MCI_IO_MUX_FSEL_SEL_USIM_SHIFT           (10U)
+/*! SEL_USIM - select usim function */
+#define MCI_IO_MUX_FSEL_SEL_USIM(x)              (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_USIM_SHIFT)) & MCI_IO_MUX_FSEL_SEL_USIM_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_LCD_8080_MASK        (0x800U)
+#define MCI_IO_MUX_FSEL_SEL_LCD_8080_SHIFT       (11U)
+/*! SEL_LCD_8080 - select lcd_8080 function */
+#define MCI_IO_MUX_FSEL_SEL_LCD_8080(x)          (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_LCD_8080_SHIFT)) & MCI_IO_MUX_FSEL_SEL_LCD_8080_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_LCD_SPI_MASK         (0x1000U)
+#define MCI_IO_MUX_FSEL_SEL_LCD_SPI_SHIFT        (12U)
+/*! SEL_LCD_SPI - select lcd_spi function */
+#define MCI_IO_MUX_FSEL_SEL_LCD_SPI(x)           (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_LCD_SPI_SHIFT)) & MCI_IO_MUX_FSEL_SEL_LCD_SPI_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_FREQ_GPIO_CLK_MASK   (0x2000U)
+#define MCI_IO_MUX_FSEL_SEL_FREQ_GPIO_CLK_SHIFT  (13U)
+/*! SEL_FREQ_GPIO_CLK - select freq_gpio_clk function */
+#define MCI_IO_MUX_FSEL_SEL_FREQ_GPIO_CLK(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_FREQ_GPIO_CLK_SHIFT)) & MCI_IO_MUX_FSEL_SEL_FREQ_GPIO_CLK_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_GPIO_INT_BMATCH_MASK (0x4000U)
+#define MCI_IO_MUX_FSEL_SEL_GPIO_INT_BMATCH_SHIFT (14U)
+/*! SEL_GPIO_INT_BMATCH - select gpio_int_bmatch function */
+#define MCI_IO_MUX_FSEL_SEL_GPIO_INT_BMATCH(x)   (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_GPIO_INT_BMATCH_SHIFT)) & MCI_IO_MUX_FSEL_SEL_GPIO_INT_BMATCH_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_SDIO_MASK            (0x8000U)
+#define MCI_IO_MUX_FSEL_SEL_SDIO_SHIFT           (15U)
+/*! SEL_SDIO - select sdio function */
+#define MCI_IO_MUX_FSEL_SEL_SDIO(x)              (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_SDIO_SHIFT)) & MCI_IO_MUX_FSEL_SEL_SDIO_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_CLK_MASK        (0x10000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_CLK_SHIFT       (16U)
+/*! SEL_ENET_CLK - select enet function clk pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_CLK(x)          (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_CLK_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_CLK_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER0_MASK    (0x20000U)
+#define MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER0_SHIFT   (17U)
+/*! SEL_GAU_TRIGGER0 - select gau trigger0 function */
+#define MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER0(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER0_SHIFT)) & MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER0_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ACOMP0_GPIO_OUT_MASK (0x40000U)
+#define MCI_IO_MUX_FSEL_SEL_ACOMP0_GPIO_OUT_SHIFT (18U)
+/*! SEL_ACOMP0_GPIO_OUT - select gau acomp0_gpio_out function */
+#define MCI_IO_MUX_FSEL_SEL_ACOMP0_GPIO_OUT(x)   (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ACOMP0_GPIO_OUT_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ACOMP0_GPIO_OUT_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ACOMP0_EDGE_PULSE_MASK (0x80000U)
+#define MCI_IO_MUX_FSEL_SEL_ACOMP0_EDGE_PULSE_SHIFT (19U)
+/*! SEL_ACOMP0_EDGE_PULSE - select gau acomp0_edge_pulse function */
+#define MCI_IO_MUX_FSEL_SEL_ACOMP0_EDGE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ACOMP0_EDGE_PULSE_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ACOMP0_EDGE_PULSE_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ACOMP1_GPIO_OUT_MASK (0x100000U)
+#define MCI_IO_MUX_FSEL_SEL_ACOMP1_GPIO_OUT_SHIFT (20U)
+/*! SEL_ACOMP1_GPIO_OUT - select gau acomp1_gpio_out function */
+#define MCI_IO_MUX_FSEL_SEL_ACOMP1_GPIO_OUT(x)   (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ACOMP1_GPIO_OUT_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ACOMP1_GPIO_OUT_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ACOMP1_EDGE_PULSE_MASK (0x200000U)
+#define MCI_IO_MUX_FSEL_SEL_ACOMP1_EDGE_PULSE_SHIFT (21U)
+/*! SEL_ACOMP1_EDGE_PULSE - select gau acomp1_edge_pulse function */
+#define MCI_IO_MUX_FSEL_SEL_ACOMP1_EDGE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ACOMP1_EDGE_PULSE_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ACOMP1_EDGE_PULSE_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER1_MASK    (0x400000U)
+#define MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER1_SHIFT   (22U)
+/*! SEL_GAU_TRIGGER1 - select gau trigger1 function */
+#define MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER1(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER1_SHIFT)) & MCI_IO_MUX_FSEL_SEL_GAU_TRIGGER1_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_CLKIN_FRM_PD_MASK    (0x800000U)
+#define MCI_IO_MUX_FSEL_SEL_CLKIN_FRM_PD_SHIFT   (23U)
+/*! SEL_CLKIN_FRM_PD - select clkin function */
+#define MCI_IO_MUX_FSEL_SEL_CLKIN_FRM_PD(x)      (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_CLKIN_FRM_PD_SHIFT)) & MCI_IO_MUX_FSEL_SEL_CLKIN_FRM_PD_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_TX_MASK         (0x2000000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_TX_SHIFT        (25U)
+/*! SEL_ENET_TX - select enet function tx pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_TX(x)           (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_TX_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_TX_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_RX_MASK         (0x4000000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_RX_SHIFT        (26U)
+/*! SEL_ENET_RX - select enet function rx pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_RX(x)           (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_RX_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_RX_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_MDIO_MASK       (0x8000000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_MDIO_SHIFT      (27U)
+/*! SEL_ENET_MDIO - select enet function mdio pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_MDIO(x)         (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_MDIO_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_MDIO_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER0_MASK     (0x10000000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER0_SHIFT    (28U)
+/*! SEL_ENET_TIMER0 - select enet function timer0 pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER0(x)       (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_TIMER0_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_TIMER0_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER1_MASK     (0x20000000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER1_SHIFT    (29U)
+/*! SEL_ENET_TIMER1 - select enet function timer1 pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER1(x)       (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_TIMER1_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_TIMER1_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER2_MASK     (0x40000000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER2_SHIFT    (30U)
+/*! SEL_ENET_TIMER2 - select enet function timer2 pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER2(x)       (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_TIMER2_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_TIMER2_MASK)
+
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER3_MASK     (0x80000000U)
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER3_SHIFT    (31U)
+/*! SEL_ENET_TIMER3 - select enet function timer3 pin */
+#define MCI_IO_MUX_FSEL_SEL_ENET_TIMER3(x)       (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_FSEL_SEL_ENET_TIMER3_SHIFT)) & MCI_IO_MUX_FSEL_SEL_ENET_TIMER3_MASK)
+/*! @} */
+
+/*! @name C_TIMER_IN - ctimer input function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP0_SEL_MASK   (0x1U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP0_SEL_SHIFT  (0U)
+/*! CT_INP0_SEL - ct_inp0 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP0_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP0_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP0_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP1_SEL_MASK   (0x2U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP1_SEL_SHIFT  (1U)
+/*! CT_INP1_SEL - ct_inp1 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP1_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP1_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP1_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP2_SEL_MASK   (0x4U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP2_SEL_SHIFT  (2U)
+/*! CT_INP2_SEL - ct_inp2 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP2_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP2_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP2_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL_MASK   (0x8U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL_SHIFT  (3U)
+/*! CT_INP3_SEL - ct_inp3 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP3_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL_MASK   (0x10U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL_SHIFT  (4U)
+/*! CT_INP4_SEL - ct_inp4 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP4_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP5_SEL_MASK   (0x20U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP5_SEL_SHIFT  (5U)
+/*! CT_INP5_SEL - ct_inp5 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP5_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP5_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP5_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP6_SEL_MASK   (0x40U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP6_SEL_SHIFT  (6U)
+/*! CT_INP6_SEL - ct_inp6 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP6_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP6_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP6_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP7_SEL_MASK   (0x80U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP7_SEL_SHIFT  (7U)
+/*! CT_INP7_SEL - ct_inp7 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP7_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP7_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP7_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP8_SEL_MASK   (0x100U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP8_SEL_SHIFT  (8U)
+/*! CT_INP8_SEL - ct_inp8 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP8_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP8_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP8_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP9_SEL_MASK   (0x200U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP9_SEL_SHIFT  (9U)
+/*! CT_INP9_SEL - ct_inp9 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP9_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP9_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP9_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP10_SEL_MASK  (0x400U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP10_SEL_SHIFT (10U)
+/*! CT_INP10_SEL - ct_inp10 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP10_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP10_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP10_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP11_SEL_MASK  (0x800U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP11_SEL_SHIFT (11U)
+/*! CT_INP11_SEL - ct_inp11 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP11_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP11_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP11_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP12_SEL_MASK  (0x1000U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP12_SEL_SHIFT (12U)
+/*! CT_INP12_SEL - ct_inp12 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP12_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP12_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP12_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP13_SEL_MASK  (0x2000U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP13_SEL_SHIFT (13U)
+/*! CT_INP13_SEL - ct_inp13 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP13_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP13_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP13_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP14_SEL_MASK  (0x4000U)
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP14_SEL_SHIFT (14U)
+/*! CT_INP14_SEL - ct_inp14 sel */
+#define MCI_IO_MUX_C_TIMER_IN_CT_INP14_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_IN_CT_INP14_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_IN_CT_INP14_SEL_MASK)
+/*! @} */
+
+/*! @name C_TIMER_OUT - ctimer output function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT0_SEL_MASK  (0x1U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT0_SEL_SHIFT (0U)
+/*! CT0MAT0_SEL - ct0mat0 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT0_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT0MAT0_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT0MAT0_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT1_SEL_MASK  (0x2U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT1_SEL_SHIFT (1U)
+/*! CT0MAT1_SEL - ct0mat1 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT1_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT0MAT1_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT0MAT1_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT2_SEL_MASK  (0x4U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT2_SEL_SHIFT (2U)
+/*! CT0MAT2_SEL - ct0mat2 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT2_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT0MAT2_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT0MAT2_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL_MASK  (0x8U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL_SHIFT (3U)
+/*! CT0MAT3_SEL - ct0mat3 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT0MAT3_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL_MASK  (0x10U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL_SHIFT (4U)
+/*! CT1MAT0_SEL - ct1mat0 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT1MAT0_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT1_SEL_MASK  (0x20U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT1_SEL_SHIFT (5U)
+/*! CT1MAT1_SEL - ct1mat1 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT1_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT1MAT1_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT1MAT1_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT2_SEL_MASK  (0x40U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT2_SEL_SHIFT (6U)
+/*! CT1MAT2_SEL - ct1mat2 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT2_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT1MAT2_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT1MAT2_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT3_SEL_MASK  (0x80U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT3_SEL_SHIFT (7U)
+/*! CT1MAT3_SEL - ct1mat3 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT1MAT3_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT1MAT3_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT1MAT3_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT0_SEL_MASK  (0x100U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT0_SEL_SHIFT (8U)
+/*! CT2MAT0_SEL - ct2mat0 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT0_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT2MAT0_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT2MAT0_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT1_SEL_MASK  (0x200U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT1_SEL_SHIFT (9U)
+/*! CT2MAT1_SEL - ct2mat1 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT1_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT2MAT1_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT2MAT1_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT2_SEL_MASK  (0x400U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT2_SEL_SHIFT (10U)
+/*! CT2MAT2_SEL - ct2mat2 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT2_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT2MAT2_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT2MAT2_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT3_SEL_MASK  (0x800U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT3_SEL_SHIFT (11U)
+/*! CT2MAT3_SEL - ct2mat3 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT2MAT3_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT2MAT3_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT2MAT3_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT0_SEL_MASK  (0x1000U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT0_SEL_SHIFT (12U)
+/*! CT3MAT0_SEL - ct3mat0 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT0_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT3MAT0_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT3MAT0_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT1_SEL_MASK  (0x2000U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT1_SEL_SHIFT (13U)
+/*! CT3MAT1_SEL - ct3mat1 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT1_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT3MAT1_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT3MAT1_SEL_MASK)
+
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT2_SEL_MASK  (0x4000U)
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT2_SEL_SHIFT (14U)
+/*! CT3MAT2_SEL - ct3mat2 sel */
+#define MCI_IO_MUX_C_TIMER_OUT_CT3MAT2_SEL(x)    (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_C_TIMER_OUT_CT3MAT2_SEL_SHIFT)) & MCI_IO_MUX_C_TIMER_OUT_CT3MAT2_SEL_MASK)
+/*! @} */
+
+/*! @name SC_TIMER - sctimer function sel */
+/*! @{ */
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP0_SEL_MASK (0x1U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP0_SEL_SHIFT (0U)
+/*! SCT0_PIN_INP0_SEL - sct0_pin_inp0 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP0_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP0_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP0_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP1_SEL_MASK (0x2U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP1_SEL_SHIFT (1U)
+/*! SCT0_PIN_INP1_SEL - sct0_pin_inp1 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP1_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP1_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP1_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP2_SEL_MASK (0x4U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP2_SEL_SHIFT (2U)
+/*! SCT0_PIN_INP2_SEL - sct0_pin_inp2 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP2_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP2_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP2_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP3_SEL_MASK (0x8U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP3_SEL_SHIFT (3U)
+/*! SCT0_PIN_INP3_SEL - sct0_pin_inp3 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP3_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP3_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP3_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP4_SEL_MASK (0x10U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP4_SEL_SHIFT (4U)
+/*! SCT0_PIN_INP4_SEL - sct0_pin_inp4 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP4_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP4_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP4_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP5_SEL_MASK (0x20U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP5_SEL_SHIFT (5U)
+/*! SCT0_PIN_INP5_SEL - sct0_pin_inp5 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP5_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP5_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP5_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP6_SEL_MASK (0x40U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP6_SEL_SHIFT (6U)
+/*! SCT0_PIN_INP6_SEL - sct0_pin_inp6 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP6_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP6_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP6_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP7_SEL_MASK (0x80U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP7_SEL_SHIFT (7U)
+/*! SCT0_PIN_INP7_SEL - sct0_pin_inp7 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP7_SEL(x) (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP7_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_PIN_INP7_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT0_SEL_MASK   (0x10000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT0_SEL_SHIFT  (16U)
+/*! SCT0_OUT0_SEL - sct0_out0 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT0_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT0_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT0_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT1_SEL_MASK   (0x20000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT1_SEL_SHIFT  (17U)
+/*! SCT0_OUT1_SEL - sct0_out1 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT1_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT1_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT1_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT4_SEL_MASK   (0x100000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT4_SEL_SHIFT  (20U)
+/*! SCT0_OUT4_SEL - sct0_out4 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT4_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT4_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT4_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT5_SEL_MASK   (0x200000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT5_SEL_SHIFT  (21U)
+/*! SCT0_OUT5_SEL - sct0_out5 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT5_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT5_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT5_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT6_SEL_MASK   (0x400000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT6_SEL_SHIFT  (22U)
+/*! SCT0_OUT6_SEL - sct0_out6 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT6_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT6_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT6_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT7_SEL_MASK   (0x800000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT7_SEL_SHIFT  (23U)
+/*! SCT0_OUT7_SEL - sct0_out7 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT7_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT7_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT7_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT8_SEL_MASK   (0x1000000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT8_SEL_SHIFT  (24U)
+/*! SCT0_OUT8_SEL - sct0_out8 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT8_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT8_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT8_SEL_MASK)
+
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT9_SEL_MASK   (0x2000000U)
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT9_SEL_SHIFT  (25U)
+/*! SCT0_OUT9_SEL - sct0_out9 sel */
+#define MCI_IO_MUX_SC_TIMER_SCT0_OUT9_SEL(x)     (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_SC_TIMER_SCT0_OUT9_SEL_SHIFT)) & MCI_IO_MUX_SC_TIMER_SCT0_OUT9_SEL_MASK)
+/*! @} */
+
+/*! @name GPIO_GRP0 - GPIO[31:0] sel */
+/*! @{ */
+
+#define MCI_IO_MUX_GPIO_GRP0_SEL_MASK            (0xFFFFFFFFU)
+#define MCI_IO_MUX_GPIO_GRP0_SEL_SHIFT           (0U)
+/*! SEL - pio0[31:0] selection, high valid; sel[i]->pio0[i]->GPIO[i] */
+#define MCI_IO_MUX_GPIO_GRP0_SEL(x)              (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_GPIO_GRP0_SEL_SHIFT)) & MCI_IO_MUX_GPIO_GRP0_SEL_MASK)
+/*! @} */
+
+/*! @name GPIO_GRP1 - GPIO[63:32] sel */
+/*! @{ */
+
+#define MCI_IO_MUX_GPIO_GRP1_SEL_MASK            (0xFFFFFFFFU)
+#define MCI_IO_MUX_GPIO_GRP1_SEL_SHIFT           (0U)
+/*! SEL - pio0[63:32] selection, high valid; sel[i]->pio0[i+32]->GPIO[i+32] */
+#define MCI_IO_MUX_GPIO_GRP1_SEL(x)              (((uint32_t)(((uint32_t)(x)) << MCI_IO_MUX_GPIO_GRP1_SEL_SHIFT)) & MCI_IO_MUX_GPIO_GRP1_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MCI_IO_MUX_Register_Masks */
+
+
+/* MCI_IO_MUX - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral MCI_IO_MUX base address */
+  #define MCI_IO_MUX_BASE                          (0x50004000u)
+  /** Peripheral MCI_IO_MUX base address */
+  #define MCI_IO_MUX_BASE_NS                       (0x40004000u)
+  /** Peripheral MCI_IO_MUX base pointer */
+  #define MCI_IO_MUX                               ((MCI_IO_MUX_Type *)MCI_IO_MUX_BASE)
+  /** Peripheral MCI_IO_MUX base pointer */
+  #define MCI_IO_MUX_NS                            ((MCI_IO_MUX_Type *)MCI_IO_MUX_BASE_NS)
+  /** Array initializer of MCI_IO_MUX peripheral base addresses */
+  #define MCI_IO_MUX_BASE_ADDRS                    { MCI_IO_MUX_BASE }
+  /** Array initializer of MCI_IO_MUX peripheral base pointers */
+  #define MCI_IO_MUX_BASE_PTRS                     { MCI_IO_MUX }
+  /** Array initializer of MCI_IO_MUX peripheral base addresses */
+  #define MCI_IO_MUX_BASE_ADDRS_NS                 { MCI_IO_MUX_BASE_NS }
+  /** Array initializer of MCI_IO_MUX peripheral base pointers */
+  #define MCI_IO_MUX_BASE_PTRS_NS                  { MCI_IO_MUX_NS }
+#else
+  /** Peripheral MCI_IO_MUX base address */
+  #define MCI_IO_MUX_BASE                          (0x40004000u)
+  /** Peripheral MCI_IO_MUX base pointer */
+  #define MCI_IO_MUX                               ((MCI_IO_MUX_Type *)MCI_IO_MUX_BASE)
+  /** Array initializer of MCI_IO_MUX peripheral base addresses */
+  #define MCI_IO_MUX_BASE_ADDRS                    { MCI_IO_MUX_BASE }
+  /** Array initializer of MCI_IO_MUX peripheral base pointers */
+  #define MCI_IO_MUX_BASE_PTRS                     { MCI_IO_MUX }
+#endif
+
+/*!
+ * @}
+ */ /* end of group MCI_IO_MUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MRT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x10 */
+    __IO uint32_t INTVAL;                            /**< Time Interval Value, array offset: 0x0, array step: 0x10, irregular array, not all indices are valid */
+    __I  uint32_t TIMER;                             /**< Timer, array offset: 0x4, array step: 0x10, irregular array, not all indices are valid */
+    __IO uint32_t CTRL;                              /**< Control, array offset: 0x8, array step: 0x10, irregular array, not all indices are valid */
+    __IO uint32_t STAT;                              /**< Status, array offset: 0xC, array step: 0x10, irregular array, not all indices are valid */
+  } CHANNEL[8];
+       uint8_t RESERVED_0[112];
+  __IO uint32_t MODCFG;                            /**< Module Configuration, offset: 0xF0 */
+  __I  uint32_t IDLE_CH;                           /**< Idle Channel, offset: 0xF4 */
+  __IO uint32_t IRQ_FLAG;                          /**< Global Interrupt Flag, offset: 0xF8 */
+  __I  uint32_t ID_CODE;                           /**< Multi-Rate Timer ID code, offset: 0xFC */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MRT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - Time Interval Value */
+/*! @{ */
+
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
+/*! IVALUE - Time interval load value. */
+#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+
+#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
+/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register.
+ *  0b0..No force load.
+ *  0b1..Force load. T
+ */
+#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT                 (8U)
+
+/*! @name CHANNEL_TIMER - Timer */
+/*! @{ */
+
+#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
+/*! VALUE - Holds the current timer value of the down-counter. */
+#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT                  (8U)
+
+/*! @name CHANNEL_CTRL - Control */
+/*! @{ */
+
+#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
+/*! INTEN - Enable the TIMER n interrupt.
+ *  0b0..Disabled. TIMER n interrupt is disabled.
+ *  0b1..Enabled. TIMER n interrupt is enabled.
+ */
+#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+
+#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
+/*! MODE - Selects the timer mode
+ *  0b00..Repeat interrupt mode
+ *  0b01..One-shot interrupt mode
+ *  0b10..One-shot stall mode
+ *  0b11..Reserved
+ */
+#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT                   (8U)
+
+/*! @name CHANNEL_STAT - Status */
+/*! @{ */
+
+#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
+/*! INTFLAG - Monitors the interrupt flag
+ *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ *  0b1..Pending interrupt.
+ */
+#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+
+#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
+/*! RUN - Indicates the state of TIMER n . RUN bit is read-only.
+ *  0b0..Idle state. TIMER n has stopped.
+ *  0b1..Running. TIMER n is running.
+ */
+#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+
+#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
+/*! INUSE - Channel-In-Use flag. Operating details depend on the operating mode bit
+ *    (MODCFG.MULTITASK), and affects the use of the Idle Channel register (IDLE_CH).
+ *  0b0..This timer channel is not in use.
+ *  0b1..This timer channel is in use.
+ */
+#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT                   (8U)
+
+/*! @name MODCFG - Module Configuration */
+/*! @{ */
+
+#define MRT_MODCFG_NOC_MASK                      (0xFU)
+#define MRT_MODCFG_NOC_SHIFT                     (0U)
+/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded) */
+#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+
+#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT                     (4U)
+/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device) */
+#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+
+#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
+/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
+ *  0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
+ *  0b1..Multi-task mode
+ */
+#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+/*! @} */
+
+/*! @name IDLE_CH - Idle Channel */
+/*! @{ */
+
+#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
+/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
+ *    positioned so that it can be used as an offset from the MRT base address, to access the
+ *    registers for the allocated channel. If all timer channels are running, then CHAN = 0xF.
+ */
+#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+/*! @} */
+
+/*! @name IRQ_FLAG - Global Interrupt Flag */
+/*! @{ */
+
+#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
+/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
+ *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ *  0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
+ *       the INTEN bit in the CONTROL0 register is also set to 1, then the interrupt for timer channel 0 and the
+ *       global interrupt are generated. Writing a 1 to GFLAG0 bit clears the interrupt request.
+ */
+#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+
+#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
+/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0. */
+#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+
+#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
+/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0. */
+#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+
+#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
+/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0. */
+#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+/*! @} */
+
+/*! @name ID_CODE - Multi-Rate Timer ID code */
+/*! @{ */
+
+#define MRT_ID_CODE_ID_CODE_MASK                 (0xFFFFFFFFU)
+#define MRT_ID_CODE_ID_CODE_SHIFT                (0U)
+/*! ID_CODE - Multi-Rate Timer ID code */
+#define MRT_ID_CODE_ID_CODE(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_ID_CODE_ID_CODE_SHIFT)) & MRT_ID_CODE_ID_CODE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral MRT0 base address */
+  #define MRT0_BASE                                (0x5002D000u)
+  /** Peripheral MRT0 base address */
+  #define MRT0_BASE_NS                             (0x4002D000u)
+  /** Peripheral MRT0 base pointer */
+  #define MRT0                                     ((MRT_Type *)MRT0_BASE)
+  /** Peripheral MRT0 base pointer */
+  #define MRT0_NS                                  ((MRT_Type *)MRT0_BASE_NS)
+  /** Peripheral MRT1 base address */
+  #define MRT1_BASE                                (0x5003F000u)
+  /** Peripheral MRT1 base address */
+  #define MRT1_BASE_NS                             (0x4003F000u)
+  /** Peripheral MRT1 base pointer */
+  #define MRT1                                     ((MRT_Type *)MRT1_BASE)
+  /** Peripheral MRT1 base pointer */
+  #define MRT1_NS                                  ((MRT_Type *)MRT1_BASE_NS)
+  /** Array initializer of MRT peripheral base addresses */
+  #define MRT_BASE_ADDRS                           { MRT0_BASE, MRT1_BASE }
+  /** Array initializer of MRT peripheral base pointers */
+  #define MRT_BASE_PTRS                            { MRT0, MRT1 }
+  /** Array initializer of MRT peripheral base addresses */
+  #define MRT_BASE_ADDRS_NS                        { MRT0_BASE_NS, MRT1_BASE_NS }
+  /** Array initializer of MRT peripheral base pointers */
+  #define MRT_BASE_PTRS_NS                         { MRT0_NS, MRT1_NS }
+#else
+  /** Peripheral MRT0 base address */
+  #define MRT0_BASE                                (0x4002D000u)
+  /** Peripheral MRT0 base pointer */
+  #define MRT0                                     ((MRT_Type *)MRT0_BASE)
+  /** Peripheral MRT1 base address */
+  #define MRT1_BASE                                (0x4003F000u)
+  /** Peripheral MRT1 base pointer */
+  #define MRT1                                     ((MRT_Type *)MRT1_BASE)
+  /** Array initializer of MRT peripheral base addresses */
+  #define MRT_BASE_ADDRS                           { MRT0_BASE, MRT1_BASE }
+  /** Array initializer of MRT peripheral base pointers */
+  #define MRT_BASE_PTRS                            { MRT0, MRT1 }
+#endif
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS                                 { MRT_IRQn, GFMRT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OCOTP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
+ * @{
+ */
+
+/** OCOTP - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t OTP_SHADOW[420];                   /**< OTP shadow register N, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[368];
+  __IO uint32_t OTP_CTRL;                          /**< OTP Controller Control Register, offset: 0x800 */
+  __IO uint32_t OTP_PDN;                           /**< OTP Controller PDN Register, offset: 0x804 */
+  __IO uint32_t OTP_WRITE_DATA;                    /**< OTP Controller Write Data Register, offset: 0x808 */
+  __IO uint32_t OTP_READ_CTRL;                     /**< OTP Controller Read Ctrl Register, offset: 0x80C */
+  __IO uint32_t OTP_READ_DATA;                     /**< OTP Controller Read Data Register, offset: 0x810 */
+  __IO uint32_t OTP_CLK_DIV;                       /**< OTP Controller Clock Divider register, offset: 0x814 */
+  __IO uint32_t OTP_CRC_CTRL;                      /**< OTP Controller CRC Ctrl Register, offset: 0x818 */
+  __I  uint32_t OTP_CRC_VALUE;                     /**< OTP Controller CRC Value Register, offset: 0x81C */
+  __IO uint32_t OTP_STATUS;                        /**< OTP Controller Status Register, offset: 0x820 */
+  __I  uint32_t OTP_STARTWORD;                     /**< OTP Controller Startword Register, offset: 0x824 */
+  __I  uint32_t OTP_VERSION;                       /**< OTP Controller Version Register, offset: 0x828 */
+  __IO uint32_t OTP_NONMASK_STATUS1;               /**< OTP Controller Nonmask Status1 Register, offset: 0x82C */
+  __IO uint32_t OTP_MASK_CTRL1;                    /**< OTP Controller Mask Ctrl1 Register, offset: 0x830 */
+  __IO uint32_t OTP_MASK_STATUS1;                  /**< OTP Controller Nonmask Status1 Register, offset: 0x834 */
+  __IO uint32_t OTP_ECC_CTRL;                      /**< OTP Controller ECC Ctrl Register, offset: 0x838 */
+  __IO uint32_t OTP_ECC_DATA;                      /**< OTP Controller ECC Date Register, offset: 0x83C */
+  __I  uint32_t OTP_ECC_DBG1;                      /**< OTP Controller ECC DBG Register1, offset: 0x840 */
+  __I  uint32_t OTP_ECC_DBG2;                      /**< OTP Controller ECC DBG Register2, offset: 0x844 */
+  __IO uint32_t OTP_ECC_DBG3;                      /**< OTP Controller ECC DBG Register3, offset: 0x848 */
+  __IO uint32_t OTP_PRNG_RAND_SEED;                /**< OTP Controller PRNG Random Seed Register, offset: 0x84C */
+  __I  uint32_t OTP_SRAM_ENTROPY_DATA;             /**< OTP Controller SRAM Entropy Data Register, offset: 0x850 */
+  __I  uint32_t OTP_PRNG_OUTPUT_DATA;              /**< OTP Controller PRNG Output Data Register, offset: 0x854 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t OTP_CRC_LUT[8];                    /**< OTP Controller CRC LUT Register0..OTP Controller CRC LUT Register7, array offset: 0x85C, array step: 0x4 */
+  __IO uint32_t OTP_LOCK_STICKY_0;                 /**< OTP Controller Lock Sticky Register0, offset: 0x87C */
+  __IO uint32_t OTP_LOCK_STICKY_1;                 /**< OTP Controller Lock Sticky Register1, offset: 0x880 */
+  __IO uint32_t OTP_LOCK_STICKY_2;                 /**< OTP Controller Lock Sticky Register2, offset: 0x884 */
+  __IO uint32_t OTP_LOCK_STICKY_3;                 /**< OTP Controller Lock Sticky Register3, offset: 0x888 */
+  __IO uint32_t OTP_LOCK_STICKY_4;                 /**< OTP Controller Lock Sticky Register4, offset: 0x88C */
+  __IO uint32_t OTP_LOCK_STICKY_5;                 /**< OTP Controller Lock Sticky Register5, offset: 0x890 */
+  __IO uint32_t OTP_LOCK_STICKY_6;                 /**< OTP Controller Lock Sticky Register6, offset: 0x894 */
+  __IO uint32_t OTP_LOCK_STICKY_7;                 /**< OTP Controller Lock Sticky Register7, offset: 0x898 */
+  __IO uint32_t OTP_LOCK_STICKY_8;                 /**< OTP Controller Lock Sticky Register8, offset: 0x89C */
+  __IO uint32_t OTP_LOCK_STICKY_9;                 /**< OTP Controller Lock Sticky Register9, offset: 0x8A0 */
+  __IO uint32_t OTP_LOCK_STICKY_10;                /**< OTP Controller Lock Sticky Register10, offset: 0x8A4 */
+  __IO uint32_t OTP_LOCK_STICKY_11;                /**< OTP Controller Lock Sticky Register11, offset: 0x8A8 */
+} OCOTP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OCOTP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
+ * @{
+ */
+
+/*! @name OTP_SHADOW - OTP shadow register N */
+/*! @{ */
+
+#define OCOTP_OTP_SHADOW_SHADOW_MASK             (0xFFFFFFFFU)
+#define OCOTP_OTP_SHADOW_SHADOW_SHIFT            (0U)
+/*! SHADOW - OTP shadow register */
+#define OCOTP_OTP_SHADOW_SHADOW(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_SHADOW_SHADOW_SHIFT)) & OCOTP_OTP_SHADOW_SHADOW_MASK)
+/*! @} */
+
+/* The count of OCOTP_OTP_SHADOW */
+#define OCOTP_OTP_SHADOW_COUNT                   (420U)
+
+/*! @name OTP_CTRL - OTP Controller Control Register */
+/*! @{ */
+
+#define OCOTP_OTP_CTRL_ADDR_MASK                 (0x1FFU)
+#define OCOTP_OTP_CTRL_ADDR_SHIFT                (0U)
+#define OCOTP_OTP_CTRL_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_ADDR_SHIFT)) & OCOTP_OTP_CTRL_ADDR_MASK)
+
+#define OCOTP_OTP_CTRL_PRNG_OUTPUT_DATA_EN_MASK  (0x200U)
+#define OCOTP_OTP_CTRL_PRNG_OUTPUT_DATA_EN_SHIFT (9U)
+#define OCOTP_OTP_CTRL_PRNG_OUTPUT_DATA_EN(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_PRNG_OUTPUT_DATA_EN_SHIFT)) & OCOTP_OTP_CTRL_PRNG_OUTPUT_DATA_EN_MASK)
+
+#define OCOTP_OTP_CTRL_SRAM_ENTROPY_DATA_EN_MASK (0x400U)
+#define OCOTP_OTP_CTRL_SRAM_ENTROPY_DATA_EN_SHIFT (10U)
+#define OCOTP_OTP_CTRL_SRAM_ENTROPY_DATA_EN(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_SRAM_ENTROPY_DATA_EN_SHIFT)) & OCOTP_OTP_CTRL_SRAM_ENTROPY_DATA_EN_MASK)
+
+#define OCOTP_OTP_CTRL_RELOAD_SHADOWS_MASK       (0x800U)
+#define OCOTP_OTP_CTRL_RELOAD_SHADOWS_SHIFT      (11U)
+#define OCOTP_OTP_CTRL_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_OTP_CTRL_RELOAD_SHADOWS_MASK)
+
+#define OCOTP_OTP_CTRL_RED_MUX_SEL_MASK          (0x3000U)
+#define OCOTP_OTP_CTRL_RED_MUX_SEL_SHIFT         (12U)
+#define OCOTP_OTP_CTRL_RED_MUX_SEL(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_RED_MUX_SEL_SHIFT)) & OCOTP_OTP_CTRL_RED_MUX_SEL_MASK)
+
+#define OCOTP_OTP_CTRL_SUPPADD_MASK              (0x4000U)
+#define OCOTP_OTP_CTRL_SUPPADD_SHIFT             (14U)
+#define OCOTP_OTP_CTRL_SUPPADD(x)                (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_SUPPADD_SHIFT)) & OCOTP_OTP_CTRL_SUPPADD_MASK)
+
+#define OCOTP_OTP_CTRL_WR_UNLOCK_MASK            (0xFFFF0000U)
+#define OCOTP_OTP_CTRL_WR_UNLOCK_SHIFT           (16U)
+#define OCOTP_OTP_CTRL_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_OTP_CTRL_WR_UNLOCK_MASK)
+/*! @} */
+
+/*! @name OTP_PDN - OTP Controller PDN Register */
+/*! @{ */
+
+#define OCOTP_OTP_PDN_PDN_MASK                   (0x1U)
+#define OCOTP_OTP_PDN_PDN_SHIFT                  (0U)
+#define OCOTP_OTP_PDN_PDN(x)                     (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_PDN_PDN_SHIFT)) & OCOTP_OTP_PDN_PDN_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DATA - OTP Controller Write Data Register */
+/*! @{ */
+
+#define OCOTP_OTP_WRITE_DATA_WRITE_DATA_MASK     (0xFFFFFFFFU)
+#define OCOTP_OTP_WRITE_DATA_WRITE_DATA_SHIFT    (0U)
+#define OCOTP_OTP_WRITE_DATA_WRITE_DATA(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_WRITE_DATA_WRITE_DATA_SHIFT)) & OCOTP_OTP_WRITE_DATA_WRITE_DATA_MASK)
+/*! @} */
+
+/*! @name OTP_READ_CTRL - OTP Controller Read Ctrl Register */
+/*! @{ */
+
+#define OCOTP_OTP_READ_CTRL_READ_MASK            (0x1U)
+#define OCOTP_OTP_READ_CTRL_READ_SHIFT           (0U)
+#define OCOTP_OTP_READ_CTRL_READ(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_READ_CTRL_READ_SHIFT)) & OCOTP_OTP_READ_CTRL_READ_MASK)
+/*! @} */
+
+/*! @name OTP_READ_DATA - OTP Controller Read Data Register */
+/*! @{ */
+
+#define OCOTP_OTP_READ_DATA_READ_DATA_MASK       (0xFFFFFFFFU)
+#define OCOTP_OTP_READ_DATA_READ_DATA_SHIFT      (0U)
+#define OCOTP_OTP_READ_DATA_READ_DATA(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_READ_DATA_READ_DATA_SHIFT)) & OCOTP_OTP_READ_DATA_READ_DATA_MASK)
+/*! @} */
+
+/*! @name OTP_CLK_DIV - OTP Controller Clock Divider register */
+/*! @{ */
+
+#define OCOTP_OTP_CLK_DIV_DIV_MASK               (0xFU)
+#define OCOTP_OTP_CLK_DIV_DIV_SHIFT              (0U)
+#define OCOTP_OTP_CLK_DIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_DIV_SHIFT)) & OCOTP_OTP_CLK_DIV_DIV_MASK)
+
+#define OCOTP_OTP_CLK_DIV_RESET_MASK             (0x20000000U)
+#define OCOTP_OTP_CLK_DIV_RESET_SHIFT            (29U)
+#define OCOTP_OTP_CLK_DIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_RESET_SHIFT)) & OCOTP_OTP_CLK_DIV_RESET_MASK)
+
+#define OCOTP_OTP_CLK_DIV_HALT_MASK              (0x40000000U)
+#define OCOTP_OTP_CLK_DIV_HALT_SHIFT             (30U)
+#define OCOTP_OTP_CLK_DIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_HALT_SHIFT)) & OCOTP_OTP_CLK_DIV_HALT_MASK)
+
+#define OCOTP_OTP_CLK_DIV_REQFLAG_MASK           (0x80000000U)
+#define OCOTP_OTP_CLK_DIV_REQFLAG_SHIFT          (31U)
+#define OCOTP_OTP_CLK_DIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_REQFLAG_SHIFT)) & OCOTP_OTP_CLK_DIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name OTP_CRC_CTRL - OTP Controller CRC Ctrl Register */
+/*! @{ */
+
+#define OCOTP_OTP_CRC_CTRL_CRC_RUN_MASK          (0x1U)
+#define OCOTP_OTP_CRC_CTRL_CRC_RUN_SHIFT         (0U)
+#define OCOTP_OTP_CRC_CTRL_CRC_RUN(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_CTRL_CRC_RUN_SHIFT)) & OCOTP_OTP_CRC_CTRL_CRC_RUN_MASK)
+
+#define OCOTP_OTP_CRC_CTRL_CRC_DONE_MASK         (0x2U)
+#define OCOTP_OTP_CRC_CTRL_CRC_DONE_SHIFT        (1U)
+#define OCOTP_OTP_CRC_CTRL_CRC_DONE(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_CTRL_CRC_DONE_SHIFT)) & OCOTP_OTP_CRC_CTRL_CRC_DONE_MASK)
+
+#define OCOTP_OTP_CRC_CTRL_CRC_STATUS_MASK       (0x4U)
+#define OCOTP_OTP_CRC_CTRL_CRC_STATUS_SHIFT      (2U)
+#define OCOTP_OTP_CRC_CTRL_CRC_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_CTRL_CRC_STATUS_SHIFT)) & OCOTP_OTP_CRC_CTRL_CRC_STATUS_MASK)
+
+#define OCOTP_OTP_CRC_CTRL_CRC_RUN_LOCK_MASK     (0x8U)
+#define OCOTP_OTP_CRC_CTRL_CRC_RUN_LOCK_SHIFT    (3U)
+#define OCOTP_OTP_CRC_CTRL_CRC_RUN_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_CTRL_CRC_RUN_LOCK_SHIFT)) & OCOTP_OTP_CRC_CTRL_CRC_RUN_LOCK_MASK)
+
+#define OCOTP_OTP_CRC_CTRL_CRC_LUT_SEL_MASK      (0xF0000U)
+#define OCOTP_OTP_CRC_CTRL_CRC_LUT_SEL_SHIFT     (16U)
+#define OCOTP_OTP_CRC_CTRL_CRC_LUT_SEL(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_CTRL_CRC_LUT_SEL_SHIFT)) & OCOTP_OTP_CRC_CTRL_CRC_LUT_SEL_MASK)
+/*! @} */
+
+/*! @name OTP_CRC_VALUE - OTP Controller CRC Value Register */
+/*! @{ */
+
+#define OCOTP_OTP_CRC_VALUE_CRC_VALUE_MASK       (0xFFFFFFFFU)
+#define OCOTP_OTP_CRC_VALUE_CRC_VALUE_SHIFT      (0U)
+#define OCOTP_OTP_CRC_VALUE_CRC_VALUE(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_VALUE_CRC_VALUE_SHIFT)) & OCOTP_OTP_CRC_VALUE_CRC_VALUE_MASK)
+/*! @} */
+
+/*! @name OTP_STATUS - OTP Controller Status Register */
+/*! @{ */
+
+#define OCOTP_OTP_STATUS_LOAD_COUNTER_MASK       (0x1FFU)
+#define OCOTP_OTP_STATUS_LOAD_COUNTER_SHIFT      (0U)
+#define OCOTP_OTP_STATUS_LOAD_COUNTER(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_LOAD_COUNTER_SHIFT)) & OCOTP_OTP_STATUS_LOAD_COUNTER_MASK)
+
+#define OCOTP_OTP_STATUS_LC_NOT_BLANK_STICKY_MASK (0x200U)
+#define OCOTP_OTP_STATUS_LC_NOT_BLANK_STICKY_SHIFT (9U)
+#define OCOTP_OTP_STATUS_LC_NOT_BLANK_STICKY(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_LC_NOT_BLANK_STICKY_SHIFT)) & OCOTP_OTP_STATUS_LC_NOT_BLANK_STICKY_MASK)
+
+#define OCOTP_OTP_STATUS_LOCKED_MASK             (0x800U)
+#define OCOTP_OTP_STATUS_LOCKED_SHIFT            (11U)
+#define OCOTP_OTP_STATUS_LOCKED(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_LOCKED_SHIFT)) & OCOTP_OTP_STATUS_LOCKED_MASK)
+
+#define OCOTP_OTP_STATUS_PROGFAIL_MASK           (0x1000U)
+#define OCOTP_OTP_STATUS_PROGFAIL_SHIFT          (12U)
+#define OCOTP_OTP_STATUS_PROGFAIL(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_PROGFAIL_SHIFT)) & OCOTP_OTP_STATUS_PROGFAIL_MASK)
+
+#define OCOTP_OTP_STATUS_ACK_MASK                (0x2000U)
+#define OCOTP_OTP_STATUS_ACK_SHIFT               (13U)
+#define OCOTP_OTP_STATUS_ACK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_ACK_SHIFT)) & OCOTP_OTP_STATUS_ACK_MASK)
+
+#define OCOTP_OTP_STATUS_PWOK_MASK               (0x4000U)
+#define OCOTP_OTP_STATUS_PWOK_SHIFT              (14U)
+#define OCOTP_OTP_STATUS_PWOK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_PWOK_SHIFT)) & OCOTP_OTP_STATUS_PWOK_MASK)
+
+#define OCOTP_OTP_STATUS_FLAGSTATE_MASK          (0xF0000U)
+#define OCOTP_OTP_STATUS_FLAGSTATE_SHIFT         (16U)
+#define OCOTP_OTP_STATUS_FLAGSTATE(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OTP_STATUS_FLAGSTATE_MASK)
+
+#define OCOTP_OTP_STATUS_BUSY_MASK               (0x400000U)
+#define OCOTP_OTP_STATUS_BUSY_SHIFT              (22U)
+#define OCOTP_OTP_STATUS_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_BUSY_SHIFT)) & OCOTP_OTP_STATUS_BUSY_MASK)
+
+#define OCOTP_OTP_STATUS_FUSE_LATCHED_MASK       (0x2000000U)
+#define OCOTP_OTP_STATUS_FUSE_LATCHED_SHIFT      (25U)
+#define OCOTP_OTP_STATUS_FUSE_LATCHED(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_FUSE_LATCHED_SHIFT)) & OCOTP_OTP_STATUS_FUSE_LATCHED_MASK)
+
+#define OCOTP_OTP_STATUS_CALIBRATED_MASK         (0x4000000U)
+#define OCOTP_OTP_STATUS_CALIBRATED_SHIFT        (26U)
+#define OCOTP_OTP_STATUS_CALIBRATED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_CALIBRATED_SHIFT)) & OCOTP_OTP_STATUS_CALIBRATED_MASK)
+/*! @} */
+
+/*! @name OTP_STARTWORD - OTP Controller Startword Register */
+/*! @{ */
+
+#define OCOTP_OTP_STARTWORD_STARTWORD_MASK       (0xFFFFU)
+#define OCOTP_OTP_STARTWORD_STARTWORD_SHIFT      (0U)
+#define OCOTP_OTP_STARTWORD_STARTWORD(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STARTWORD_STARTWORD_SHIFT)) & OCOTP_OTP_STARTWORD_STARTWORD_MASK)
+/*! @} */
+
+/*! @name OTP_VERSION - OTP Controller Version Register */
+/*! @{ */
+
+#define OCOTP_OTP_VERSION_STEP_VER_MASK          (0xFFFFU)
+#define OCOTP_OTP_VERSION_STEP_VER_SHIFT         (0U)
+#define OCOTP_OTP_VERSION_STEP_VER(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_STEP_VER_SHIFT)) & OCOTP_OTP_VERSION_STEP_VER_MASK)
+
+#define OCOTP_OTP_VERSION_MINOR_VER_MASK         (0xFF0000U)
+#define OCOTP_OTP_VERSION_MINOR_VER_SHIFT        (16U)
+#define OCOTP_OTP_VERSION_MINOR_VER(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_MINOR_VER_SHIFT)) & OCOTP_OTP_VERSION_MINOR_VER_MASK)
+
+#define OCOTP_OTP_VERSION_MAJOR_VER_MASK         (0xFF000000U)
+#define OCOTP_OTP_VERSION_MAJOR_VER_SHIFT        (24U)
+#define OCOTP_OTP_VERSION_MAJOR_VER(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_MAJOR_VER_SHIFT)) & OCOTP_OTP_VERSION_MAJOR_VER_MASK)
+/*! @} */
+
+/*! @name OTP_NONMASK_STATUS1 - OTP Controller Nonmask Status1 Register */
+/*! @{ */
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_PBRICK_ERR_MASK (0x20U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_PBRICK_ERR_SHIFT (5U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_PBRICK_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_PBRICK_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_PBRICK_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_OTP_STATE_ERR_MASK (0x40U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_OTP_STATE_ERR_SHIFT (6U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_OTP_STATE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_OTP_STATE_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_OTP_STATE_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_RELOAD_MASK (0x80U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_RELOAD_SHIFT (7U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_RELOAD_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_RELOAD_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_MASK (0x100U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_SHIFT (8U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_RELOAD_MASK (0x200U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_RELOAD_SHIFT (9U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_RELOAD_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_RELOAD_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_MASK (0x400U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_SHIFT (10U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_SEC_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_DONE_MASK (0x800U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_DONE_SHIFT (11U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_DONE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_DONE_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_DONE_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_LUT_SEL_ERR_MASK (0x1000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_LUT_SEL_ERR_SHIFT (12U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_LUT_SEL_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_LUT_SEL_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_LUT_SEL_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_ADDRESS_RANGE_ERR_MASK (0x2000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_ADDRESS_RANGE_ERR_SHIFT (13U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_ADDRESS_RANGE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_ADDRESS_RANGE_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_ADDRESS_RANGE_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_WRITE_PROTECT_ERR_MASK (0x4000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_WRITE_PROTECT_ERR_SHIFT (14U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_WRITE_PROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_WRITE_PROTECT_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_WRITE_PROTECT_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_SECURTY_PROTECT_ERR_MASK (0x8000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_SECURTY_PROTECT_ERR_SHIFT (15U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_SECURTY_PROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_SECURTY_PROTECT_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_SECURTY_PROTECT_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_ERR_MASK (0x10000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_ERR_SHIFT (16U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_LOAD_ERR_MASK (0x20000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_LOAD_ERR_SHIFT (17U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_LOAD_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_LOAD_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_LOAD_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_COUNTER_ERR_MASK (0x40000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_COUNTER_ERR_SHIFT (18U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_COUNTER_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_COUNTER_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_COUNTER_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_BITPROTECT_ERR_MASK (0x80000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_BITPROTECT_ERR_SHIFT (19U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_BITPROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_BITPROTECT_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_BITPROTECT_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_PRNG_O_FAULT_MASK (0x100000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_PRNG_O_FAULT_SHIFT (20U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_PRNG_O_FAULT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_PRNG_O_FAULT_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_PRNG_O_FAULT_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_ECC_ZEROIZED_ERR_MASK (0x200000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_ECC_ZEROIZED_ERR_SHIFT (21U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_ECC_ZEROIZED_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_ECC_ZEROIZED_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_ECC_ZEROIZED_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_ACCESS_ERR_MASK (0x400000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_ACCESS_ERR_SHIFT (22U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_ACCESS_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_ACCESS_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_ACCESS_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_RELOAD_REQ_ERR_MASK (0x800000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_RELOAD_REQ_ERR_SHIFT (23U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_RELOAD_REQ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_RELOAD_REQ_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_RELOAD_REQ_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_DURING_RELOAD_ERR_MASK (0x1000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_DURING_RELOAD_ERR_SHIFT (24U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_DURING_RELOAD_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_DURING_RELOAD_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_DURING_RELOAD_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_READ_ERR_MASK (0x2000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_READ_ERR_SHIFT (25U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_READ_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_READ_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_WRITE_ERR_MASK (0x4000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_WRITE_ERR_SHIFT (26U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_WRITE_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_READ_ERR_MASK (0x8000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_READ_ERR_SHIFT (27U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_READ_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_READ_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_WRITE_ERR_MASK (0x10000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_WRITE_ERR_SHIFT (28U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_WRITE_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_READ_ERR_MASK (0x20000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_READ_ERR_SHIFT (29U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_READ_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_READ_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_PROG_ERR_MASK (0x40000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_PROG_ERR_SHIFT (30U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_PROG_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_PROG_ERR_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_PROG_ERR_MASK)
+
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_NO_ACCESS_MASK (0x80000000U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_NO_ACCESS_SHIFT (31U)
+#define OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_NO_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_NO_ACCESS_SHIFT)) & OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_NO_ACCESS_MASK)
+/*! @} */
+
+/*! @name OTP_MASK_CTRL1 - OTP Controller Mask Ctrl1 Register */
+/*! @{ */
+
+#define OCOTP_OTP_MASK_CTRL1_TIMEOUT_COUNTER_MASK (0x7U)
+#define OCOTP_OTP_MASK_CTRL1_TIMEOUT_COUNTER_SHIFT (0U)
+#define OCOTP_OTP_MASK_CTRL1_TIMEOUT_COUNTER(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_TIMEOUT_COUNTER_SHIFT)) & OCOTP_OTP_MASK_CTRL1_TIMEOUT_COUNTER_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_TMEOUT_COUNTER_EN_MASK (0x8U)
+#define OCOTP_OTP_MASK_CTRL1_TMEOUT_COUNTER_EN_SHIFT (3U)
+#define OCOTP_OTP_MASK_CTRL1_TMEOUT_COUNTER_EN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_TMEOUT_COUNTER_EN_SHIFT)) & OCOTP_OTP_MASK_CTRL1_TMEOUT_COUNTER_EN_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PBRICK_ERR_MASK (0x20U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PBRICK_ERR_SHIFT (5U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PBRICK_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PBRICK_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PBRICK_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_OTP_STATE_ERR_MASK (0x40U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_OTP_STATE_ERR_SHIFT (6U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_OTP_STATE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_OTP_STATE_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_OTP_STATE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_RELOAD_MASK (0x80U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_RELOAD_SHIFT (7U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_RELOAD_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_RELOAD_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_MASK  (0x100U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_SHIFT (8U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_DED_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_RELOAD_MASK (0x200U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_RELOAD_SHIFT (9U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_RELOAD_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_RELOAD_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_MASK  (0x400U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_SHIFT (10U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SEC_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_DONE_MASK (0x800U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_DONE_SHIFT (11U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_DONE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_DONE_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_DONE_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_LUT_SEL_ERR_MASK (0x1000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_LUT_SEL_ERR_SHIFT (12U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_LUT_SEL_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_LUT_SEL_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_LUT_SEL_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_ADDRESS_RANGE_ERR_MASK (0x2000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_ADDRESS_RANGE_ERR_SHIFT (13U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_ADDRESS_RANGE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_ADDRESS_RANGE_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_ADDRESS_RANGE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_WRITE_PROTECT_ERR_MASK (0x4000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_WRITE_PROTECT_ERR_SHIFT (14U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_WRITE_PROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_WRITE_PROTECT_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_WRITE_PROTECT_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_SECURTY_PROTECT_ERR_MASK (0x8000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_SECURTY_PROTECT_ERR_SHIFT (15U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_SECURTY_PROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_SECURTY_PROTECT_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_CRC_SECURTY_PROTECT_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_ERR_MASK (0x10000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_ERR_SHIFT (16U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_LOAD_ERR_MASK (0x20000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_LOAD_ERR_SHIFT (17U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_LOAD_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_LOAD_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_LOAD_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_COUNTER_ERR_MASK (0x40000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_COUNTER_ERR_SHIFT (18U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_COUNTER_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_COUNTER_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_COUNTER_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_BITPROTECT_ERR_MASK (0x80000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_BITPROTECT_ERR_SHIFT (19U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_BITPROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_BITPROTECT_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_BITPROTECT_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PRNG_O_FAULT_MASK (0x100000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PRNG_O_FAULT_SHIFT (20U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PRNG_O_FAULT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PRNG_O_FAULT_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_PRNG_O_FAULT_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_ECC_ZEROIZED_ERR_MASK (0x200000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_ECC_ZEROIZED_ERR_SHIFT (21U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_ECC_ZEROIZED_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_ECC_ZEROIZED_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_ECC_ZEROIZED_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_ACCESS_ERR_MASK (0x400000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_ACCESS_ERR_SHIFT (22U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_ACCESS_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_ACCESS_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_ACCESS_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_RELOAD_REQ_ERR_MASK (0x800000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_RELOAD_REQ_ERR_SHIFT (23U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_RELOAD_REQ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_RELOAD_REQ_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_RELOAD_REQ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_DURING_RELOAD_ERR_MASK (0x1000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_DURING_RELOAD_ERR_SHIFT (24U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_DURING_RELOAD_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_DURING_RELOAD_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_WRITE_DURING_RELOAD_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_READ_ERR_MASK (0x2000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_READ_ERR_SHIFT (25U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_READ_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_READ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_WRITE_ERR_MASK (0x4000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_WRITE_ERR_SHIFT (26U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_WRITE_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_HVF_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_READ_ERR_MASK (0x8000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_READ_ERR_SHIFT (27U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_READ_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_READ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_WRITE_ERR_MASK (0x10000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_WRITE_ERR_SHIFT (28U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_WRITE_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_SRAM_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_READ_ERR_MASK (0x20000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_READ_ERR_SHIFT (29U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_READ_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_READ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_PROG_ERR_MASK (0x40000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_PROG_ERR_SHIFT (30U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_PROG_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_PROG_ERR_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_FUSE_PROG_ERR_MASK)
+
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_NO_ACCESS_MASK (0x80000000U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_NO_ACCESS_SHIFT (31U)
+#define OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_NO_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_NO_ACCESS_SHIFT)) & OCOTP_OTP_MASK_CTRL1_CTRL_MASK_SHADOW_NO_ACCESS_MASK)
+/*! @} */
+
+/*! @name OTP_MASK_STATUS1 - OTP Controller Nonmask Status1 Register */
+/*! @{ */
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_PBRICK_ERR_MASK (0x20U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_PBRICK_ERR_SHIFT (5U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_PBRICK_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_PBRICK_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_PBRICK_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_OTP_STATE_ERR_MASK (0x40U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_OTP_STATE_ERR_SHIFT (6U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_OTP_STATE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_OTP_STATE_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_OTP_STATE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_DED_RELOAD_MASK   (0x80U)
+#define OCOTP_OTP_MASK_STATUS1_DED_RELOAD_SHIFT  (7U)
+#define OCOTP_OTP_MASK_STATUS1_DED_RELOAD(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_DED_RELOAD_SHIFT)) & OCOTP_OTP_MASK_STATUS1_DED_RELOAD_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_DED_MASK     (0x100U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_DED_SHIFT    (8U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_DED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_DED_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_DED_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_SEC_RELOAD_MASK   (0x200U)
+#define OCOTP_OTP_MASK_STATUS1_SEC_RELOAD_SHIFT  (9U)
+#define OCOTP_OTP_MASK_STATUS1_SEC_RELOAD(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_SEC_RELOAD_SHIFT)) & OCOTP_OTP_MASK_STATUS1_SEC_RELOAD_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_SEC_MASK     (0x400U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SEC_SHIFT    (10U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SEC(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_SEC_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_SEC_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_DONE_MASK (0x800U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_DONE_SHIFT (11U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_DONE(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_CRC_DONE_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_CRC_DONE_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_LUT_SEL_ERR_MASK (0x1000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_LUT_SEL_ERR_SHIFT (12U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_LUT_SEL_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_CRC_LUT_SEL_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_CRC_LUT_SEL_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_ADDRESS_RANGE_ERR_MASK (0x2000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_ADDRESS_RANGE_ERR_SHIFT (13U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_ADDRESS_RANGE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_CRC_ADDRESS_RANGE_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_CRC_ADDRESS_RANGE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_WRITE_PROTECT_ERR_MASK (0x4000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_WRITE_PROTECT_ERR_SHIFT (14U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_WRITE_PROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_CRC_WRITE_PROTECT_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_CRC_WRITE_PROTECT_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_SECURTY_PROTECT_ERR_MASK (0x8000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_SECURTY_PROTECT_ERR_SHIFT (15U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_CRC_SECURTY_PROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_CRC_SECURTY_PROTECT_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_CRC_SECURTY_PROTECT_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_WRITE_ERR_MASK (0x10000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_WRITE_ERR_SHIFT (16U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_WRITE_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_LOAD_ERR_MASK (0x20000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_LOAD_ERR_SHIFT (17U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_LOAD_ERR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_LOAD_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_LOAD_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_COUNTER_ERR_MASK (0x40000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_COUNTER_ERR_SHIFT (18U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_COUNTER_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_COUNTER_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_COUNTER_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_BITPROTECT_ERR_MASK (0x80000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_BITPROTECT_ERR_SHIFT (19U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_BITPROTECT_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_BITPROTECT_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_BITPROTECT_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_PRNG_O_FAULT_MASK (0x100000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_PRNG_O_FAULT_SHIFT (20U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_PRNG_O_FAULT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_PRNG_O_FAULT_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_PRNG_O_FAULT_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_ECC_ZEROIZED_ERR_MASK (0x200000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_ECC_ZEROIZED_ERR_SHIFT (21U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_ECC_ZEROIZED_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_ECC_ZEROIZED_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_ECC_ZEROIZED_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_ACCESS_ERR_MASK (0x400000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_ACCESS_ERR_SHIFT (22U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_ACCESS_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_FUSE_ACCESS_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_FUSE_ACCESS_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_RELOAD_REQ_ERR_MASK (0x800000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_RELOAD_REQ_ERR_SHIFT (23U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_RELOAD_REQ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_RELOAD_REQ_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_RELOAD_REQ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_WRITE_DURING_RELOAD_ERR_MASK (0x1000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_WRITE_DURING_RELOAD_ERR_SHIFT (24U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_WRITE_DURING_RELOAD_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_WRITE_DURING_RELOAD_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_WRITE_DURING_RELOAD_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_READ_ERR_MASK (0x2000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_READ_ERR_SHIFT (25U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_READ_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_READ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_WRITE_ERR_MASK (0x4000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_WRITE_ERR_SHIFT (26U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_WRITE_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_HVF_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_READ_ERR_MASK (0x8000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_READ_ERR_SHIFT (27U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_READ_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_READ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_WRITE_ERR_MASK (0x10000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_WRITE_ERR_SHIFT (28U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_WRITE_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_SRAM_WRITE_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_READ_ERR_MASK (0x20000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_READ_ERR_SHIFT (29U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_FUSE_READ_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_FUSE_READ_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_PROG_ERR_MASK (0x40000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_PROG_ERR_SHIFT (30U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_FUSE_PROG_ERR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_FUSE_PROG_ERR_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_FUSE_PROG_ERR_MASK)
+
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_NO_ACCESS_MASK (0x80000000U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_NO_ACCESS_SHIFT (31U)
+#define OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_NO_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_NO_ACCESS_SHIFT)) & OCOTP_OTP_MASK_STATUS1_MASK_SHADOW_NO_ACCESS_MASK)
+/*! @} */
+
+/*! @name OTP_ECC_CTRL - OTP Controller ECC Ctrl Register */
+/*! @{ */
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_ADDR_MASK (0x1FFU)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_ADDR_SHIFT (0U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_ADDR_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_ADDR_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_MASK (0x7F0000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_SHIFT (16U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_RD_DATA_SEL_MASK (0x2000000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_RD_DATA_SEL_SHIFT (25U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_RD_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_RD_DATA_SEL_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_RD_DATA_SEL_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_SEC_DISABLE_MASK (0x4000000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_SEC_DISABLE_SHIFT (26U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_SEC_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_SEC_DISABLE_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_SEC_DISABLE_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_EN_MASK  (0x8000000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_EN_SHIFT (27U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_EN(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_EN_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_EN_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_SEL_MASK (0x10000000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_SEL_SHIFT (28U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_SEL_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_GEN_DATA_SEL_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_DISABLE_MASK (0x20000000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_DISABLE_SHIFT (29U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_DISABLE_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_DISABLE_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_MASK   (0x40000000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_SHIFT  (30U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_BLOCK_MASK)
+
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_ZERO_MASK    (0x80000000U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_ZERO_SHIFT   (31U)
+#define OCOTP_OTP_ECC_CTRL_CTRL_ECC_ZERO(x)      (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_CTRL_CTRL_ECC_ZERO_SHIFT)) & OCOTP_OTP_ECC_CTRL_CTRL_ECC_ZERO_MASK)
+/*! @} */
+
+/*! @name OTP_ECC_DATA - OTP Controller ECC Date Register */
+/*! @{ */
+
+#define OCOTP_OTP_ECC_DATA_DATA_MASK             (0xFFFFFFFFU)
+#define OCOTP_OTP_ECC_DATA_DATA_SHIFT            (0U)
+#define OCOTP_OTP_ECC_DATA_DATA(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DATA_DATA_SHIFT)) & OCOTP_OTP_ECC_DATA_DATA_MASK)
+/*! @} */
+
+/*! @name OTP_ECC_DBG1 - OTP Controller ECC DBG Register1 */
+/*! @{ */
+
+#define OCOTP_OTP_ECC_DBG1_SEC_ADDR_MASK         (0x1FFU)
+#define OCOTP_OTP_ECC_DBG1_SEC_ADDR_SHIFT        (0U)
+#define OCOTP_OTP_ECC_DBG1_SEC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DBG1_SEC_ADDR_SHIFT)) & OCOTP_OTP_ECC_DBG1_SEC_ADDR_MASK)
+
+#define OCOTP_OTP_ECC_DBG1_DED_ADDR_MASK         (0x1FF0000U)
+#define OCOTP_OTP_ECC_DBG1_DED_ADDR_SHIFT        (16U)
+#define OCOTP_OTP_ECC_DBG1_DED_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DBG1_DED_ADDR_SHIFT)) & OCOTP_OTP_ECC_DBG1_DED_ADDR_MASK)
+/*! @} */
+
+/*! @name OTP_ECC_DBG2 - OTP Controller ECC DBG Register2 */
+/*! @{ */
+
+#define OCOTP_OTP_ECC_DBG2_WRITE_ECC_PARITY_MASK (0x7FU)
+#define OCOTP_OTP_ECC_DBG2_WRITE_ECC_PARITY_SHIFT (0U)
+#define OCOTP_OTP_ECC_DBG2_WRITE_ECC_PARITY(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DBG2_WRITE_ECC_PARITY_SHIFT)) & OCOTP_OTP_ECC_DBG2_WRITE_ECC_PARITY_MASK)
+
+#define OCOTP_OTP_ECC_DBG2_READ_ECC_PARITY_MASK  (0x7F00U)
+#define OCOTP_OTP_ECC_DBG2_READ_ECC_PARITY_SHIFT (8U)
+#define OCOTP_OTP_ECC_DBG2_READ_ECC_PARITY(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DBG2_READ_ECC_PARITY_SHIFT)) & OCOTP_OTP_ECC_DBG2_READ_ECC_PARITY_MASK)
+
+#define OCOTP_OTP_ECC_DBG2_ECC_SYNDROME_MASK     (0x7F0000U)
+#define OCOTP_OTP_ECC_DBG2_ECC_SYNDROME_SHIFT    (16U)
+#define OCOTP_OTP_ECC_DBG2_ECC_SYNDROME(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DBG2_ECC_SYNDROME_SHIFT)) & OCOTP_OTP_ECC_DBG2_ECC_SYNDROME_MASK)
+
+#define OCOTP_OTP_ECC_DBG2_ECC_CORRECTION_DETECTION_PARITYBITS_MASK (0x7F000000U)
+#define OCOTP_OTP_ECC_DBG2_ECC_CORRECTION_DETECTION_PARITYBITS_SHIFT (24U)
+#define OCOTP_OTP_ECC_DBG2_ECC_CORRECTION_DETECTION_PARITYBITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DBG2_ECC_CORRECTION_DETECTION_PARITYBITS_SHIFT)) & OCOTP_OTP_ECC_DBG2_ECC_CORRECTION_DETECTION_PARITYBITS_MASK)
+/*! @} */
+
+/*! @name OTP_ECC_DBG3 - OTP Controller ECC DBG Register3 */
+/*! @{ */
+
+#define OCOTP_OTP_ECC_DBG3_BITS_MASK             (0xFFFFFFFFU)
+#define OCOTP_OTP_ECC_DBG3_BITS_SHIFT            (0U)
+#define OCOTP_OTP_ECC_DBG3_BITS(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_ECC_DBG3_BITS_SHIFT)) & OCOTP_OTP_ECC_DBG3_BITS_MASK)
+/*! @} */
+
+/*! @name OTP_PRNG_RAND_SEED - OTP Controller PRNG Random Seed Register */
+/*! @{ */
+
+#define OCOTP_OTP_PRNG_RAND_SEED_PRNG_RAND_SEED_MASK (0xFFFFFFFFU)
+#define OCOTP_OTP_PRNG_RAND_SEED_PRNG_RAND_SEED_SHIFT (0U)
+#define OCOTP_OTP_PRNG_RAND_SEED_PRNG_RAND_SEED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_PRNG_RAND_SEED_PRNG_RAND_SEED_SHIFT)) & OCOTP_OTP_PRNG_RAND_SEED_PRNG_RAND_SEED_MASK)
+/*! @} */
+
+/*! @name OTP_SRAM_ENTROPY_DATA - OTP Controller SRAM Entropy Data Register */
+/*! @{ */
+
+#define OCOTP_OTP_SRAM_ENTROPY_DATA_SRAM_ENTROPY_DATA_MASK (0xFFFFFFFFU)
+#define OCOTP_OTP_SRAM_ENTROPY_DATA_SRAM_ENTROPY_DATA_SHIFT (0U)
+#define OCOTP_OTP_SRAM_ENTROPY_DATA_SRAM_ENTROPY_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_SRAM_ENTROPY_DATA_SRAM_ENTROPY_DATA_SHIFT)) & OCOTP_OTP_SRAM_ENTROPY_DATA_SRAM_ENTROPY_DATA_MASK)
+/*! @} */
+
+/*! @name OTP_PRNG_OUTPUT_DATA - OTP Controller PRNG Output Data Register */
+/*! @{ */
+
+#define OCOTP_OTP_PRNG_OUTPUT_DATA_PRNG_OUTPUT_DATA_MASK (0x3FFFFU)
+#define OCOTP_OTP_PRNG_OUTPUT_DATA_PRNG_OUTPUT_DATA_SHIFT (0U)
+#define OCOTP_OTP_PRNG_OUTPUT_DATA_PRNG_OUTPUT_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_PRNG_OUTPUT_DATA_PRNG_OUTPUT_DATA_SHIFT)) & OCOTP_OTP_PRNG_OUTPUT_DATA_PRNG_OUTPUT_DATA_MASK)
+/*! @} */
+
+/*! @name OTP_CRC_LUT - OTP Controller CRC LUT Register0..OTP Controller CRC LUT Register7 */
+/*! @{ */
+
+#define OCOTP_OTP_CRC_LUT_CRC_FUSE_START_ADDR_MASK (0x7FU)
+#define OCOTP_OTP_CRC_LUT_CRC_FUSE_START_ADDR_SHIFT (0U)
+#define OCOTP_OTP_CRC_LUT_CRC_FUSE_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_LUT_CRC_FUSE_START_ADDR_SHIFT)) & OCOTP_OTP_CRC_LUT_CRC_FUSE_START_ADDR_MASK)
+
+#define OCOTP_OTP_CRC_LUT_CRC_EXP_VAL_FUSE_ADDR_MASK (0x700U)
+#define OCOTP_OTP_CRC_LUT_CRC_EXP_VAL_FUSE_ADDR_SHIFT (8U)
+#define OCOTP_OTP_CRC_LUT_CRC_EXP_VAL_FUSE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_LUT_CRC_EXP_VAL_FUSE_ADDR_SHIFT)) & OCOTP_OTP_CRC_LUT_CRC_EXP_VAL_FUSE_ADDR_MASK)
+
+#define OCOTP_OTP_CRC_LUT_CRC_FUSE_END_ADDR_MASK (0x7F0000U)
+#define OCOTP_OTP_CRC_LUT_CRC_FUSE_END_ADDR_SHIFT (16U)
+#define OCOTP_OTP_CRC_LUT_CRC_FUSE_END_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_LUT_CRC_FUSE_END_ADDR_SHIFT)) & OCOTP_OTP_CRC_LUT_CRC_FUSE_END_ADDR_MASK)
+
+#define OCOTP_OTP_CRC_LUT_READ_PROTECTION_MASK   (0x20000000U)
+#define OCOTP_OTP_CRC_LUT_READ_PROTECTION_SHIFT  (29U)
+#define OCOTP_OTP_CRC_LUT_READ_PROTECTION(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_LUT_READ_PROTECTION_SHIFT)) & OCOTP_OTP_CRC_LUT_READ_PROTECTION_MASK)
+
+#define OCOTP_OTP_CRC_LUT_SECURITY_PROTECTION_MASK (0x40000000U)
+#define OCOTP_OTP_CRC_LUT_SECURITY_PROTECTION_SHIFT (30U)
+#define OCOTP_OTP_CRC_LUT_SECURITY_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_LUT_SECURITY_PROTECTION_SHIFT)) & OCOTP_OTP_CRC_LUT_SECURITY_PROTECTION_MASK)
+
+#define OCOTP_OTP_CRC_LUT_WRITE_PROTECTION_MASK  (0x80000000U)
+#define OCOTP_OTP_CRC_LUT_WRITE_PROTECTION_SHIFT (31U)
+#define OCOTP_OTP_CRC_LUT_WRITE_PROTECTION(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_LUT_WRITE_PROTECTION_SHIFT)) & OCOTP_OTP_CRC_LUT_WRITE_PROTECTION_MASK)
+/*! @} */
+
+/* The count of OCOTP_OTP_CRC_LUT */
+#define OCOTP_OTP_CRC_LUT_COUNT                  (8U)
+
+/*! @name OTP_LOCK_STICKY_0 - OTP Controller Lock Sticky Register0 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT0_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT0_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT0_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT0_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT1_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT1_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT1_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT1_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT2_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT2_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT2_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT2_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT3_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT3_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT3_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT3_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT4_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT4_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT4_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT4_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT5_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT5_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT5(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT5_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT5_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT6_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT6_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT6(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT6_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT6_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT7_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT7_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT7(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT7_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT7_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT8_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT8_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT8(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT8_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT8_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT9_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT9_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT9(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT9_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT9_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT10_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT10_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT10(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT10_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT10_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT11_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT11_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT11(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT11_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT11_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT12_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT12_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT12(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT12_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT12_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT13_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT13_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT13(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT13_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT13_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT14_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT14_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT14(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT14_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT14_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT15_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT15_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT15(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT15_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT15_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT16_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT16_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT16(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT16_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT16_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT17_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT17_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT17(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT17_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT17_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT18_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT18_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT18(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT18_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT18_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT19_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT19_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT19(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT19_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT19_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT20_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT20_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT20(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT20_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT20_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT21_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT21_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT21(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT21_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT21_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT22_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT22_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT22(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT22_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT22_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT23_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT23_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT23(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT23_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT23_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT24_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT24_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT24(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT24_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT24_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT25_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT25_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT25(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT25_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT25_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT26_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT26_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT26(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT26_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT26_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT27_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT27_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT27(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT27_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT27_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT28_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT28_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT28(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT28_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT28_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT29_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT29_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT29(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT29_SHIFT)) & OCOTP_OTP_LOCK_STICKY_0_LOCK_STICKY_BIT29_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_1 - OTP Controller Lock Sticky Register1 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT30_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT30_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT30(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT30_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT30_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT31_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT31_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT31(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT31_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT31_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT32_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT32_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT32(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT32_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT32_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT33_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT33_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT33(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT33_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT33_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT34_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT34_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT34(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT34_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT34_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT35_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT35_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT35(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT35_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT35_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT36_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT36_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT36(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT36_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT36_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT37_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT37_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT37(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT37_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT37_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT38_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT38_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT38(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT38_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT38_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT39_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT39_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT39(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT39_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT39_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT40_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT40_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT40(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT40_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT40_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT41_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT41_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT41(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT41_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT41_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT42_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT42_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT42(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT42_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT42_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT43_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT43_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT43(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT43_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT43_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT44_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT44_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT44(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT44_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT44_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT45_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT45_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT45(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT45_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT45_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT46_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT46_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT46(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT46_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT46_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT47_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT47_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT47(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT47_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT47_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT48_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT48_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT48(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT48_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT48_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT49_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT49_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT49(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT49_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT49_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT50_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT50_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT50(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT50_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT50_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT51_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT51_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT51(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT51_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT51_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT52_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT52_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT52(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT52_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT52_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT53_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT53_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT53(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT53_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT53_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT54_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT54_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT54(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT54_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT54_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT55_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT55_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT55(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT55_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT55_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT56_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT56_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT56(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT56_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT56_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT57_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT57_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT57(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT57_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT57_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT58_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT58_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT58(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT58_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT58_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT59_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT59_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT59(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT59_SHIFT)) & OCOTP_OTP_LOCK_STICKY_1_LOCK_STICKY_BIT59_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_2 - OTP Controller Lock Sticky Register2 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT60_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT60_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT60(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT60_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT60_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT61_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT61_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT61(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT61_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT61_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT62_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT62_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT62(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT62_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT62_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT63_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT63_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT63(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT63_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT63_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT64_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT64_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT64(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT64_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT64_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT65_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT65_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT65(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT65_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT65_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT66_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT66_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT66(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT66_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT66_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT67_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT67_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT67(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT67_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT67_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT68_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT68_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT68(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT68_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT68_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT69_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT69_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT69(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT69_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT69_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT70_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT70_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT70(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT70_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT70_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT71_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT71_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT71(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT71_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT71_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT72_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT72_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT72(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT72_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT72_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT73_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT73_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT73(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT73_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT73_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT74_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT74_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT74(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT74_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT74_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT75_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT75_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT75(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT75_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT75_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT76_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT76_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT76(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT76_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT76_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT77_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT77_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT77(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT77_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT77_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT78_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT78_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT78(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT78_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT78_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT79_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT79_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT79(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT79_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT79_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT80_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT80_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT80(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT80_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT80_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT81_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT81_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT81(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT81_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT81_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT82_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT82_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT82(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT82_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT82_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT83_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT83_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT83(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT83_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT83_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT84_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT84_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT84(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT84_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT84_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT85_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT85_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT85(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT85_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT85_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT86_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT86_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT86(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT86_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT86_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT87_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT87_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT87(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT87_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT87_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT88_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT88_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT88(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT88_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT88_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT89_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT89_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT89(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT89_SHIFT)) & OCOTP_OTP_LOCK_STICKY_2_LOCK_STICKY_BIT89_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_3 - OTP Controller Lock Sticky Register3 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT90_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT90_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT90(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT90_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT90_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT91_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT91_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT91(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT91_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT91_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT92_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT92_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT92(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT92_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT92_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT93_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT93_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT93(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT93_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT93_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT94_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT94_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT94(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT94_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT94_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT95_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT95_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT95(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT95_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT95_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT96_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT96_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT96(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT96_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT96_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT97_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT97_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT97(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT97_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT97_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT98_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT98_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT98(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT98_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT98_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT99_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT99_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT99(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT99_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT99_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT100_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT100_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT100(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT100_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT100_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT101_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT101_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT101(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT101_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT101_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT102_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT102_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT102(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT102_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT102_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT103_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT103_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT103(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT103_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT103_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT104_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT104_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT104(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT104_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT104_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT105_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT105_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT105(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT105_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT105_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT106_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT106_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT106(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT106_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT106_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT107_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT107_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT107(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT107_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT107_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT108_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT108_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT108(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT108_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT108_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT109_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT109_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT109(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT109_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT109_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT110_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT110_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT110(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT110_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT110_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT111_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT111_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT111(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT111_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT111_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT112_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT112_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT112(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT112_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT112_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT113_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT113_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT113(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT113_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT113_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT114_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT114_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT114(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT114_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT114_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT115_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT115_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT115(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT115_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT115_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT116_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT116_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT116(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT116_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT116_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT117_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT117_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT117(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT117_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT117_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT118_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT118_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT118(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT118_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT118_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT119_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT119_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT119(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT119_SHIFT)) & OCOTP_OTP_LOCK_STICKY_3_LOCK_STICKY_BIT119_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_4 - OTP Controller Lock Sticky Register4 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT120_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT120_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT120(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT120_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT120_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT121_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT121_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT121(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT121_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT121_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT122_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT122_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT122(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT122_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT122_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT123_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT123_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT123(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT123_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT123_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT124_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT124_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT124(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT124_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT124_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT125_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT125_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT125(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT125_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT125_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT126_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT126_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT126(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT126_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT126_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT127_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT127_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT127(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT127_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT127_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT128_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT128_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT128(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT128_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT128_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT129_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT129_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT129(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT129_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT129_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT130_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT130_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT130(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT130_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT130_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT131_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT131_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT131(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT131_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT131_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT132_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT132_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT132(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT132_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT132_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT133_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT133_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT133(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT133_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT133_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT134_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT134_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT134(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT134_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT134_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT135_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT135_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT135(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT135_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT135_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT136_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT136_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT136(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT136_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT136_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT137_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT137_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT137(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT137_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT137_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT138_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT138_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT138(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT138_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT138_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT139_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT139_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT139(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT139_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT139_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT140_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT140_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT140(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT140_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT140_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT141_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT141_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT141(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT141_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT141_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT142_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT142_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT142(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT142_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT142_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT143_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT143_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT143(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT143_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT143_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT144_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT144_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT144(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT144_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT144_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT145_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT145_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT145(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT145_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT145_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT146_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT146_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT146(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT146_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT146_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT147_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT147_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT147(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT147_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT147_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT148_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT148_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT148(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT148_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT148_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT149_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT149_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT149(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT149_SHIFT)) & OCOTP_OTP_LOCK_STICKY_4_LOCK_STICKY_BIT149_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_5 - OTP Controller Lock Sticky Register5 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT150_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT150_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT150(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT150_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT150_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT151_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT151_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT151(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT151_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT151_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT152_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT152_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT152(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT152_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT152_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT153_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT153_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT153(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT153_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT153_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT154_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT154_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT154(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT154_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT154_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT155_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT155_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT155(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT155_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT155_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT156_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT156_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT156(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT156_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT156_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT157_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT157_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT157(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT157_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT157_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT158_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT158_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT158(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT158_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT158_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT159_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT159_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT159(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT159_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT159_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT160_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT160_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT160(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT160_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT160_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT161_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT161_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT161(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT161_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT161_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT162_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT162_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT162(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT162_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT162_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT163_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT163_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT163(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT163_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT163_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT164_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT164_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT164(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT164_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT164_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT165_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT165_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT165(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT165_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT165_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT166_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT166_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT166(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT166_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT166_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT167_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT167_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT167(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT167_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT167_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT168_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT168_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT168(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT168_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT168_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT169_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT169_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT169(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT169_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT169_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT170_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT170_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT170(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT170_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT170_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT171_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT171_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT171(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT171_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT171_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT172_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT172_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT172(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT172_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT172_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT173_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT173_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT173(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT173_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT173_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT174_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT174_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT174(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT174_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT174_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT175_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT175_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT175(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT175_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT175_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT176_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT176_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT176(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT176_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT176_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT177_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT177_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT177(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT177_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT177_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT178_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT178_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT178(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT178_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT178_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT179_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT179_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT179(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT179_SHIFT)) & OCOTP_OTP_LOCK_STICKY_5_LOCK_STICKY_BIT179_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_6 - OTP Controller Lock Sticky Register6 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT180_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT180_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT180(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT180_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT180_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT181_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT181_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT181(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT181_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT181_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT182_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT182_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT182(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT182_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT182_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT183_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT183_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT183(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT183_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT183_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT184_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT184_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT184(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT184_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT184_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT185_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT185_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT185(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT185_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT185_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT186_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT186_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT186(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT186_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT186_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT187_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT187_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT187(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT187_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT187_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT188_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT188_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT188(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT188_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT188_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT189_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT189_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT189(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT189_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT189_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT190_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT190_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT190(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT190_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT190_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT191_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT191_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT191(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT191_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT191_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT192_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT192_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT192(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT192_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT192_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT193_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT193_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT193(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT193_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT193_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT194_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT194_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT194(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT194_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT194_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT195_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT195_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT195(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT195_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT195_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT196_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT196_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT196(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT196_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT196_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT197_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT197_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT197(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT197_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT197_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT198_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT198_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT198(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT198_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT198_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT199_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT199_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT199(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT199_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT199_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT200_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT200_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT200(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT200_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT200_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT201_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT201_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT201(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT201_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT201_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT202_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT202_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT202(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT202_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT202_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT203_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT203_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT203(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT203_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT203_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT204_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT204_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT204(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT204_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT204_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT205_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT205_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT205(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT205_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT205_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT206_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT206_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT206(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT206_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT206_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT207_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT207_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT207(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT207_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT207_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT208_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT208_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT208(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT208_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT208_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT209_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT209_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT209(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT209_SHIFT)) & OCOTP_OTP_LOCK_STICKY_6_LOCK_STICKY_BIT209_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_7 - OTP Controller Lock Sticky Register7 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT210_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT210_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT210(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT210_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT210_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT211_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT211_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT211(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT211_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT211_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT212_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT212_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT212(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT212_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT212_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT213_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT213_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT213(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT213_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT213_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT214_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT214_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT214(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT214_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT214_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT215_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT215_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT215(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT215_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT215_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT216_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT216_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT216(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT216_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT216_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT217_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT217_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT217(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT217_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT217_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT218_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT218_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT218(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT218_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT218_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT219_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT219_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT219(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT219_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT219_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT220_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT220_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT220(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT220_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT220_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT221_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT221_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT221(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT221_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT221_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT222_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT222_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT222(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT222_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT222_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT223_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT223_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT223(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT223_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT223_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT224_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT224_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT224(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT224_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT224_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT225_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT225_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT225(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT225_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT225_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT226_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT226_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT226(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT226_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT226_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT227_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT227_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT227(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT227_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT227_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT228_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT228_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT228(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT228_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT228_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT229_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT229_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT229(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT229_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT229_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT230_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT230_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT230(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT230_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT230_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT231_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT231_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT231(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT231_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT231_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT232_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT232_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT232(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT232_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT232_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT233_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT233_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT233(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT233_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT233_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT234_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT234_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT234(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT234_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT234_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT235_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT235_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT235(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT235_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT235_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT236_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT236_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT236(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT236_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT236_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT237_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT237_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT237(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT237_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT237_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT238_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT238_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT238(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT238_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT238_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT239_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT239_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT239(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT239_SHIFT)) & OCOTP_OTP_LOCK_STICKY_7_LOCK_STICKY_BIT239_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_8 - OTP Controller Lock Sticky Register8 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT240_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT240_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT240(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT240_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT240_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT241_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT241_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT241(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT241_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT241_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT242_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT242_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT242(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT242_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT242_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT243_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT243_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT243(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT243_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT243_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT244_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT244_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT244(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT244_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT244_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT245_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT245_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT245(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT245_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT245_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT246_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT246_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT246(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT246_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT246_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT247_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT247_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT247(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT247_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT247_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT248_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT248_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT248(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT248_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT248_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT249_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT249_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT249(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT249_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT249_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT250_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT250_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT250(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT250_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT250_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT251_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT251_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT251(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT251_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT251_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT252_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT252_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT252(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT252_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT252_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT253_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT253_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT253(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT253_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT253_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT254_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT254_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT254(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT254_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT254_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT255_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT255_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT255(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT255_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT255_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT256_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT256_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT256(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT256_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT256_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT257_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT257_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT257(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT257_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT257_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT258_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT258_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT258(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT258_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT258_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT259_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT259_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT259(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT259_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT259_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT260_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT260_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT260(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT260_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT260_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT261_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT261_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT261(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT261_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT261_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT262_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT262_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT262(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT262_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT262_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT263_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT263_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT263(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT263_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT263_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT264_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT264_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT264(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT264_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT264_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT265_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT265_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT265(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT265_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT265_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT266_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT266_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT266(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT266_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT266_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT267_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT267_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT267(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT267_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT267_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT268_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT268_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT268(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT268_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT268_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT269_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT269_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT269(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT269_SHIFT)) & OCOTP_OTP_LOCK_STICKY_8_LOCK_STICKY_BIT269_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_9 - OTP Controller Lock Sticky Register9 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT270_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT270_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT270(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT270_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT270_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT271_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT271_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT271(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT271_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT271_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT272_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT272_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT272(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT272_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT272_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT273_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT273_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT273(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT273_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT273_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT274_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT274_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT274(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT274_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT274_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT275_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT275_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT275(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT275_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT275_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT276_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT276_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT276(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT276_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT276_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT277_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT277_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT277(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT277_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT277_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT278_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT278_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT278(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT278_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT278_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT279_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT279_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT279(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT279_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT279_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT280_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT280_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT280(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT280_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT280_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT281_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT281_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT281(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT281_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT281_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT282_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT282_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT282(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT282_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT282_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT283_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT283_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT283(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT283_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT283_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT284_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT284_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT284(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT284_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT284_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT285_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT285_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT285(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT285_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT285_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT286_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT286_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT286(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT286_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT286_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT287_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT287_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT287(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT287_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT287_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT288_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT288_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT288(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT288_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT288_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT289_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT289_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT289(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT289_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT289_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT290_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT290_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT290(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT290_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT290_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT291_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT291_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT291(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT291_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT291_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT292_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT292_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT292(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT292_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT292_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT293_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT293_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT293(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT293_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT293_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT294_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT294_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT294(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT294_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT294_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT295_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT295_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT295(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT295_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT295_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT296_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT296_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT296(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT296_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT296_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT297_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT297_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT297(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT297_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT297_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT298_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT298_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT298(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT298_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT298_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT299_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT299_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT299(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT299_SHIFT)) & OCOTP_OTP_LOCK_STICKY_9_LOCK_STICKY_BIT299_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_10 - OTP Controller Lock Sticky Register10 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT300_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT300_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT300(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT300_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT300_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT301_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT301_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT301(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT301_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT301_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT302_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT302_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT302(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT302_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT302_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT303_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT303_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT303(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT303_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT303_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT304_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT304_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT304(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT304_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT304_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT305_MASK (0x20U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT305_SHIFT (5U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT305(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT305_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT305_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT306_MASK (0x40U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT306_SHIFT (6U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT306(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT306_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT306_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT307_MASK (0x80U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT307_SHIFT (7U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT307(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT307_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT307_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT308_MASK (0x100U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT308_SHIFT (8U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT308(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT308_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT308_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT309_MASK (0x200U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT309_SHIFT (9U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT309(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT309_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT309_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT310_MASK (0x400U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT310_SHIFT (10U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT310(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT310_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT310_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT311_MASK (0x800U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT311_SHIFT (11U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT311(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT311_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT311_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT312_MASK (0x1000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT312_SHIFT (12U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT312(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT312_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT312_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT313_MASK (0x2000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT313_SHIFT (13U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT313(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT313_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT313_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT314_MASK (0x4000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT314_SHIFT (14U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT314(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT314_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT314_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT315_MASK (0x8000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT315_SHIFT (15U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT315(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT315_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT315_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT316_MASK (0x10000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT316_SHIFT (16U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT316(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT316_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT316_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT317_MASK (0x20000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT317_SHIFT (17U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT317(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT317_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT317_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT318_MASK (0x40000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT318_SHIFT (18U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT318(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT318_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT318_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT319_MASK (0x80000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT319_SHIFT (19U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT319(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT319_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT319_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT320_MASK (0x100000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT320_SHIFT (20U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT320(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT320_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT320_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT321_MASK (0x200000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT321_SHIFT (21U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT321(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT321_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT321_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT322_MASK (0x400000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT322_SHIFT (22U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT322(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT322_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT322_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT323_MASK (0x800000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT323_SHIFT (23U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT323(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT323_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT323_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT324_MASK (0x1000000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT324_SHIFT (24U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT324(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT324_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT324_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT325_MASK (0x2000000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT325_SHIFT (25U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT325(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT325_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT325_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT326_MASK (0x4000000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT326_SHIFT (26U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT326(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT326_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT326_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT327_MASK (0x8000000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT327_SHIFT (27U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT327(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT327_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT327_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT328_MASK (0x10000000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT328_SHIFT (28U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT328(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT328_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT328_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT329_MASK (0x20000000U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT329_SHIFT (29U)
+#define OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT329(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT329_SHIFT)) & OCOTP_OTP_LOCK_STICKY_10_LOCK_STICKY_BIT329_MASK)
+/*! @} */
+
+/*! @name OTP_LOCK_STICKY_11 - OTP Controller Lock Sticky Register11 */
+/*! @{ */
+
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT330_MASK (0x1U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT330_SHIFT (0U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT330(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT330_SHIFT)) & OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT330_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT331_MASK (0x2U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT331_SHIFT (1U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT331(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT331_SHIFT)) & OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT331_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT332_MASK (0x4U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT332_SHIFT (2U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT332(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT332_SHIFT)) & OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT332_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT333_MASK (0x8U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT333_SHIFT (3U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT333(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT333_SHIFT)) & OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT333_MASK)
+
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT334_MASK (0x10U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT334_SHIFT (4U)
+#define OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT334(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT334_SHIFT)) & OCOTP_OTP_LOCK_STICKY_11_LOCK_STICKY_BIT334_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OCOTP_Register_Masks */
+
+
+/* OCOTP - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral OCOTP base address */
+  #define OCOTP_BASE                               (0x5000A000u)
+  /** Peripheral OCOTP base address */
+  #define OCOTP_BASE_NS                            (0x4000A000u)
+  /** Peripheral OCOTP base pointer */
+  #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
+  /** Peripheral OCOTP base pointer */
+  #define OCOTP_NS                                 ((OCOTP_Type *)OCOTP_BASE_NS)
+  /** Array initializer of OCOTP peripheral base addresses */
+  #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
+  /** Array initializer of OCOTP peripheral base pointers */
+  #define OCOTP_BASE_PTRS                          { OCOTP }
+  /** Array initializer of OCOTP peripheral base addresses */
+  #define OCOTP_BASE_ADDRS_NS                      { OCOTP_BASE_NS }
+  /** Array initializer of OCOTP peripheral base pointers */
+  #define OCOTP_BASE_PTRS_NS                       { OCOTP_NS }
+#else
+  /** Peripheral OCOTP base address */
+  #define OCOTP_BASE                               (0x4000A000u)
+  /** Peripheral OCOTP base pointer */
+  #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
+  /** Array initializer of OCOTP peripheral base addresses */
+  #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
+  /** Array initializer of OCOTP peripheral base pointers */
+  #define OCOTP_BASE_PTRS                          { OCOTP }
+#endif
+
+/*!
+ * @}
+ */ /* end of group OCOTP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** OSTIMER - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t EVTIMERL;                          /**< EVTIMER Low Register, offset: 0x0 */
+  __I  uint32_t EVTIMERH;                          /**< EVTIMER High Register, offset: 0x4 */
+  __I  uint32_t CAPTURE_L;                         /**< Local Capture Low Register for CPU, offset: 0x8 */
+  __I  uint32_t CAPTURE_H;                         /**< Local Capture High Register for CPU, offset: 0xC */
+  __IO uint32_t MATCH_L;                           /**< Local Match Low Register for CPU, offset: 0x10 */
+  __IO uint32_t MATCH_H;                           /**< Local Match High Register for CPU, offset: 0x14 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t OSEVENT_CTRL;                      /**< OS Event Timer Control Register for CPU, offset: 0x1C */
+} OSTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
+ * @{
+ */
+
+/*! @name EVTIMERL - EVTIMER Low Register */
+/*! @{ */
+
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
+/*! EVTIMER_COUNT_VALUE - EVTimer Count value */
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
+/*! @} */
+
+/*! @name EVTIMERH - EVTIMER High Register */
+/*! @{ */
+
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
+/*! EVTIMER_COUNT_VALUE - EVTimer Count value */
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
+/*! @} */
+
+/*! @name CAPTURE_L - Local Capture Low Register for CPU */
+/*! @{ */
+
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT    (0U)
+/*! CAPTURE_VALUE - EVTimer Capture value */
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
+/*! @} */
+
+/*! @name CAPTURE_H - Local Capture High Register for CPU */
+/*! @{ */
+
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT    (0U)
+/*! CAPTURE_VALUE - EVTimer Capture value */
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
+/*! @} */
+
+/*! @name MATCH_L - Local Match Low Register for CPU */
+/*! @{ */
+
+#define OSTIMER_MATCH_L_MATCH_VALUE_MASK         (0xFFFFFFFFU)
+#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT        (0U)
+/*! MATCH_VALUE - EVTimer Match value */
+#define OSTIMER_MATCH_L_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
+/*! @} */
+
+/*! @name MATCH_H - Local Match High Register for CPU */
+/*! @{ */
+
+#define OSTIMER_MATCH_H_MATCH_VALUE_MASK         (0xFFFFFFFFU)
+#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT        (0U)
+/*! MATCH_VALUE - EVTimer Match value */
+#define OSTIMER_MATCH_H_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
+/*! @} */
+
+/*! @name OSEVENT_CTRL - OS Event Timer Control Register for CPU */
+/*! @{ */
+
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
+/*! OSTIMER_INTRFLAG - Interrupt Flag */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
+
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
+/*! OSTIMER_INTENA - Interrupt/Wake-up Request
+ *  0b0..Interrupt/wake-up requests due to the OSTIMER_INTR flag are blocked.
+ *  0b1..An interrupt/wake-up request to the domain processor will be asserted when the OSTIMER_INTR flag is set.
+ */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x)   (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
+
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK   (0x4U)
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT  (2U)
+/*! MATCH_WR_RDY - EVTimer Match Write Ready */
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OSTIMER_Register_Masks */
+
+
+/* OSTIMER - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral OSTIMER base address */
+  #define OSTIMER_BASE                             (0x5013B000u)
+  /** Peripheral OSTIMER base address */
+  #define OSTIMER_BASE_NS                          (0x4013B000u)
+  /** Peripheral OSTIMER base pointer */
+  #define OSTIMER                                  ((OSTIMER_Type *)OSTIMER_BASE)
+  /** Peripheral OSTIMER base pointer */
+  #define OSTIMER_NS                               ((OSTIMER_Type *)OSTIMER_BASE_NS)
+  /** Array initializer of OSTIMER peripheral base addresses */
+  #define OSTIMER_BASE_ADDRS                       { OSTIMER_BASE }
+  /** Array initializer of OSTIMER peripheral base pointers */
+  #define OSTIMER_BASE_PTRS                        { OSTIMER }
+  /** Array initializer of OSTIMER peripheral base addresses */
+  #define OSTIMER_BASE_ADDRS_NS                    { OSTIMER_BASE_NS }
+  /** Array initializer of OSTIMER peripheral base pointers */
+  #define OSTIMER_BASE_PTRS_NS                     { OSTIMER_NS }
+#else
+  /** Peripheral OSTIMER base address */
+  #define OSTIMER_BASE                             (0x4013B000u)
+  /** Peripheral OSTIMER base pointer */
+  #define OSTIMER                                  ((OSTIMER_Type *)OSTIMER_BASE)
+  /** Array initializer of OSTIMER peripheral base addresses */
+  #define OSTIMER_BASE_ADDRS                       { OSTIMER_BASE }
+  /** Array initializer of OSTIMER peripheral base pointers */
+  #define OSTIMER_BASE_PTRS                        { OSTIMER }
+#endif
+/** Interrupt vectors for the OSTIMER peripheral type */
+#define OSTIMER_IRQS                             { OS_EVENT_TIMER_IRQn }
+
+/*!
+ * @}
+ */ /* end of group OSTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode, offset: 0x0 */
+  __IO uint32_t IENR;                              /**< Pin Interrupt Level or Rising Edge Interrupt Enable, offset: 0x4 */
+  __O  uint32_t SIENR;                             /**< Pin Interrupt Level or Rising Edge Interrupt Set, offset: 0x8 */
+  __IO uint32_t CIENR;                             /**< Pin Interrupt Level (Rising Edge Interrupt) Clear, offset: 0xC */
+  __IO uint32_t IENF;                              /**< Pin Interrupt Active Level or Falling Edge Interrupt Enable, offset: 0x10 */
+  __O  uint32_t SIENF;                             /**< Pin Interrupt Active Level or Falling Edge Interrupt Set, offset: 0x14 */
+  __O  uint32_t CIENF;                             /**< Pin Interrupt Active Level or Falling Edge Interrupt Clear, offset: 0x18 */
+  __IO uint32_t RISE;                              /**< Pin Interrupt Rising Edge, offset: 0x1C */
+  __IO uint32_t FALL;                              /**< Pin Interrupt Falling Edge, offset: 0x20 */
+  __IO uint32_t IST;                               /**< Pin Interrupt Status, offset: 0x24 */
+  __IO uint32_t PMCTRL;                            /**< Pattern Match Interrupt Control, offset: 0x28 */
+  __IO uint32_t PMSRC;                             /**< Pattern Match Interrupt Bit-Slice Source, offset: 0x2C */
+  __IO uint32_t PMCFG;                             /**< Pattern Match Interrupt Bit Slice Configuration, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode */
+/*! @{ */
+
+#define PINT_ISEL_PMODE_MASK                     (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT                    (0U)
+/*! PMODE - Interrupt mode
+ *  0b00000000..Edge-sensitive
+ *  0b00000001..Level-sensitive
+ */
+#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+/*! @} */
+
+/*! @name IENR - Pin Interrupt Level or Rising Edge Interrupt Enable */
+/*! @{ */
+
+#define PINT_IENR_ENRL_MASK                      (0xFFU)
+#define PINT_IENR_ENRL_SHIFT                     (0U)
+/*! ENRL - Enable Interrupt
+ *  0b00000000..Disable rising edge or level interrupt
+ *  0b00000001..Enable rising edge or level interrupt
+ */
+#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+/*! @} */
+
+/*! @name SIENR - Pin Interrupt Level or Rising Edge Interrupt Set */
+/*! @{ */
+
+#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT                 (0U)
+/*! SETENRL - Set bits in the IENR
+ *  0b00000000..No operation
+ *  0b00000001..Enable rising edge or level interrupt
+ */
+#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+/*! @} */
+
+/*! @name CIENR - Pin Interrupt Level (Rising Edge Interrupt) Clear */
+/*! @{ */
+
+#define PINT_CIENR_CENRL_MASK                    (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT                   (0U)
+/*! CENRL - Clear bits in the IENR
+ *  0b00000000..No operation
+ *  0b00000001..Disable rising edge or level interrupt
+ */
+#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+/*! @} */
+
+/*! @name IENF - Pin Interrupt Active Level or Falling Edge Interrupt Enable */
+/*! @{ */
+
+#define PINT_IENF_ENAF_MASK                      (0xFFU)
+#define PINT_IENF_ENAF_SHIFT                     (0U)
+/*! ENAF - Enable Interrupt
+ *  0b00000000..Disable falling edge interrupt or set active interrupt level LOW
+ *  0b00000001..Enable falling edge interrupt enabled or set active interrupt level HIGH
+ */
+#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+/*! @} */
+
+/*! @name SIENF - Pin Interrupt Active Level or Falling Edge Interrupt Set */
+/*! @{ */
+
+#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT                 (0U)
+/*! SETENAF - Set bits in the IENF
+ *  0b00000000..No operation
+ *  0b00000001..Select HIGH-active interrupt or enable falling edge interrupt
+ */
+#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+/*! @} */
+
+/*! @name CIENF - Pin Interrupt Active Level or Falling Edge Interrupt Clear */
+/*! @{ */
+
+#define PINT_CIENF_CENAF_MASK                    (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT                   (0U)
+/*! CENAF - Clear bits in the IENF
+ *  0b00000000..No operation
+ *  0b00000001..LOW-active interrupt selected or falling edge interrupt disabled
+ */
+#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+/*! @} */
+
+/*! @name RISE - Pin Interrupt Rising Edge */
+/*! @{ */
+
+#define PINT_RISE_RDET_MASK                      (0xFFU)
+#define PINT_RISE_RDET_SHIFT                     (0U)
+/*! RDET - Rising edge detect
+ *  0b00000000..Read 0- No rising edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
+ *  0b00000001..Read 1- a rising edge has been detected since Reset or the last time a one was written to this
+ *              bit, Write 1- clear rising edge detection for this pin
+ */
+#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+/*! @} */
+
+/*! @name FALL - Pin Interrupt Falling Edge */
+/*! @{ */
+
+#define PINT_FALL_FDET_MASK                      (0xFFU)
+#define PINT_FALL_FDET_SHIFT                     (0U)
+/*! FDET - Falling edge detect
+ *  0b00000000..Read 0- No falling edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
+ *  0b00000001..Read 1- a falling edge has been detected since Reset or the last time a one was written to this
+ *              bit, Write 1- clear falling edge detection for this bit
+ */
+#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+/*! @} */
+
+/*! @name IST - Pin Interrupt Status */
+/*! @{ */
+
+#define PINT_IST_PSTAT_MASK                      (0xFFU)
+#define PINT_IST_PSTAT_SHIFT                     (0U)
+/*! PSTAT - Pin interrupt status
+ *  0b00000000..Read 0- interrupt is not being requested for this pin, Write 0- no operation.
+ *  0b00000001..Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear rising- and
+ *              falling-edge detection for this pin, Write 1 (level-sensitive)- switch the active level for this pin
+ *              (in the IENF register).
+ */
+#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Pattern Match Interrupt Control */
+/*! @{ */
+
+#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
+/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function.
+ *  0b0..Pin interrupt- interrupts are driven in response to the standard pin interrupt function.
+ *  0b1..Pattern match- interrupts are driven in response to pattern matches.
+ */
+#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+
+#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
+/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolean expression evaluates to true.
+ *  0b0..Disabled- RXEV output to the CPU is disabled.
+ *  0b1..Enabled- RXEV output to the CPU is enabled.
+ */
+#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+
+#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
+/*! PMAT - Pattern Matches
+ *  0b00000001..The corresponding product term is matched by the current state of the appropriate inputs.
+ */
+#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+/*! @} */
+
+/*! @name PMSRC - Pattern Match Interrupt Bit-Slice Source */
+/*! @{ */
+
+#define PINT_PMSRC_SRC0_MASK                     (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT                    (8U)
+/*! SRC0 - Selects the input source for bit slice 0
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+
+#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT                    (11U)
+/*! SRC1 - Selects the input source for bit slice 1
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+
+#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT                    (14U)
+/*! SRC2 - Selects the input source for bit slice 2
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+
+#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT                    (17U)
+/*! SRC3 - Selects the input source for bit slice 3
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+
+#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT                    (20U)
+/*! SRC4 - Selects the input source for bit slice 4
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+
+#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT                    (23U)
+/*! SRC5 - Selects the input source for bit slice 5
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+
+#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT                    (26U)
+/*! SRC6 - Selects the input source for bit slice 6
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+
+#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT                    (29U)
+/*! SRC7 - Selects the input source for bit slice 7
+ *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+/*! @} */
+
+/*! @name PMCFG - Pattern Match Interrupt Bit Slice Configuration */
+/*! @{ */
+
+#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
+/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
+ *  0b0..No effect. Slice 0 is not an endpoint.
+ *  0b1..Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
+/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
+ *  0b0..No effect. Slice 1 is not an endpoint.
+ *  0b1..Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
+/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
+ *  0b0..No effect. Slice 2 is not an endpoint.
+ *  0b1..Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
+/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
+ *  0b0..No effect. Slice 3 is not an endpoint.
+ *  0b1..Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
+/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
+ *  0b0..No effect. Slice 4 is not an endpoint.
+ *  0b1..Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
+/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
+ *  0b0..No effect. Slice 5 is not an endpoint.
+ *  0b1..Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
+/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
+ *  0b0..No effect. Slice 6 is not an endpoint.
+ *  0b1..Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+
+#define PINT_PMCFG_CFG0_MASK                     (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT                    (8U)
+/*! CFG0 - Specifies the match contribution condition for bit slice 0.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+
+#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT                    (11U)
+/*! CFG1 - Specifies the match contribution condition for bit slice 1.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+
+#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT                    (14U)
+/*! CFG2 - Specifies the match contribution condition for bit slice 2.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+
+#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT                    (17U)
+/*! CFG3 - Specifies the match contribution condition for bit slice 3.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+
+#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT                    (20U)
+/*! CFG4 - Specifies the match contribution condition for bit slice 4.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+
+#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT                    (23U)
+/*! CFG5 - Specifies the match contribution condition for bit slice 5.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+
+#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT                    (26U)
+/*! CFG6 - Specifies the match contribution condition for bit slice 6.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+
+#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT                    (29U)
+/*! CFG7 - Specifies the match contribution condition for bit slice 7.
+ *  0b000..Constant HIGH
+ *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ *         PMCFG or the PMSRC registers are written to.
+ *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ *         is only cleared when the PMCFG or the PMSRC registers are written to.
+ *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ *  0b101..Low level. Match occurs when there is a low level on the specified input.
+ *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ *         cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral PINT base address */
+  #define PINT_BASE                                (0x50025000u)
+  /** Peripheral PINT base address */
+  #define PINT_BASE_NS                             (0x40025000u)
+  /** Peripheral PINT base pointer */
+  #define PINT                                     ((PINT_Type *)PINT_BASE)
+  /** Peripheral PINT base pointer */
+  #define PINT_NS                                  ((PINT_Type *)PINT_BASE_NS)
+  /** Array initializer of PINT peripheral base addresses */
+  #define PINT_BASE_ADDRS                          { PINT_BASE }
+  /** Array initializer of PINT peripheral base pointers */
+  #define PINT_BASE_PTRS                           { PINT }
+  /** Array initializer of PINT peripheral base addresses */
+  #define PINT_BASE_ADDRS_NS                       { PINT_BASE_NS }
+  /** Array initializer of PINT peripheral base pointers */
+  #define PINT_BASE_PTRS_NS                        { PINT_NS }
+#else
+  /** Peripheral PINT base address */
+  #define PINT_BASE                                (0x40025000u)
+  /** Peripheral PINT base pointer */
+  #define PINT                                     ((PINT_Type *)PINT_BASE)
+  /** Array initializer of PINT peripheral base addresses */
+  #define PINT_BASE_ADDRS                          { PINT_BASE }
+  /** Array initializer of PINT peripheral base pointers */
+  #define PINT_BASE_PTRS                           { PINT }
+#endif
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PKC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer
+ * @{
+ */
+
+/** PKC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t PKC_STATUS;                        /**< Status register, offset: 0x0 */
+  __IO uint32_t PKC_CTRL;                          /**< Control register, offset: 0x4 */
+  __IO uint32_t PKC_CFG;                           /**< Configuration register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PKC_MODE1;                         /**< Mode register, parameter set 1, offset: 0x10 */
+  __IO uint32_t PKC_XYPTR1;                        /**< X+Y pointer register, parameter set 1, offset: 0x14 */
+  __IO uint32_t PKC_ZRPTR1;                        /**< Z+R pointer register, parameter set 1, offset: 0x18 */
+  __IO uint32_t PKC_LEN1;                          /**< Length register, parameter set 1, offset: 0x1C */
+  __IO uint32_t PKC_MODE2;                         /**< Mode register, parameter set 2, offset: 0x20 */
+  __IO uint32_t PKC_XYPTR2;                        /**< X+Y pointer register, parameter set 2, offset: 0x24 */
+  __IO uint32_t PKC_ZRPTR2;                        /**< Z+R pointer register, parameter set 2, offset: 0x28 */
+  __IO uint32_t PKC_LEN2;                          /**< Length register, parameter set 2, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PKC_UPTR;                          /**< Universal pointer FUP program, offset: 0x40 */
+  __IO uint32_t PKC_UPTRT;                         /**< Universal pointer FUP table, offset: 0x44 */
+  __IO uint32_t PKC_ULEN;                          /**< Universal pointer length, offset: 0x48 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t PKC_MCDATA;                        /**< MC pattern data interface, offset: 0x50 */
+       uint8_t RESERVED_3[12];
+  __I  uint32_t PKC_VERSION;                       /**< PKC version register, offset: 0x60 */
+       uint8_t RESERVED_4[3916];
+  __O  uint32_t PKC_SOFT_RST;                      /**< Software reset, offset: 0xFB0 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t PKC_ACCESS_ERR;                    /**< Access Error, offset: 0xFC0 */
+  __O  uint32_t PKC_ACCESS_ERR_CLR;                /**< Clear Access Error, offset: 0xFC4 */
+       uint8_t RESERVED_6[16];
+  __O  uint32_t PKC_INT_CLR_ENABLE;                /**< Interrupt enable clear, offset: 0xFD8 */
+  __O  uint32_t PKC_INT_SET_ENABLE;                /**< Interrupt enable set, offset: 0xFDC */
+  __I  uint32_t PKC_INT_STATUS;                    /**< Interrupt status, offset: 0xFE0 */
+  __I  uint32_t PKC_INT_ENABLE;                    /**< Interrupt enable, offset: 0xFE4 */
+  __O  uint32_t PKC_INT_CLR_STATUS;                /**< Interrupt status clear, offset: 0xFE8 */
+  __O  uint32_t PKC_INT_SET_STATUS;                /**< Interrupt status set, offset: 0xFEC */
+       uint8_t RESERVED_7[12];
+  __I  uint32_t PKC_MODULE_ID;                     /**< Module ID, offset: 0xFFC */
+} PKC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PKC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PKC_Register_Masks PKC Register Masks
+ * @{
+ */
+
+/*! @name PKC_STATUS - Status register */
+/*! @{ */
+
+#define PKC_PKC_STATUS_ACTIV_MASK                (0x1U)
+#define PKC_PKC_STATUS_ACTIV_SHIFT               (0U)
+/*! ACTIV - PKC active: ACTIV=1 signals that a calculation is in progress or about to start. */
+#define PKC_PKC_STATUS_ACTIV(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK)
+
+#define PKC_PKC_STATUS_CARRY_MASK                (0x2U)
+#define PKC_PKC_STATUS_CARRY_SHIFT               (1U)
+/*! CARRY - Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case; - an
+ *    addition or multiplication with addition operation has been executed and an overflow in the
+ *    most significant bit has occured.
+ */
+#define PKC_PKC_STATUS_CARRY(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK)
+
+#define PKC_PKC_STATUS_ZERO_MASK                 (0x4U)
+#define PKC_PKC_STATUS_ZERO_SHIFT                (2U)
+/*! ZERO - Zero result flag: ZERO is set by the PKC at the end of a calculation in case the result
+ *    of the calculation is equal zero.
+ */
+#define PKC_PKC_STATUS_ZERO(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK)
+
+#define PKC_PKC_STATUS_GOANY_MASK                (0x8U)
+#define PKC_PKC_STATUS_GOANY_SHIFT               (3U)
+/*! GOANY - Combined GO status flag: GOANY is set in case either PKC_CTRL. */
+#define PKC_PKC_STATUS_GOANY(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK)
+
+#define PKC_PKC_STATUS_LOCKED_MASK               (0x60U)
+#define PKC_PKC_STATUS_LOCKED_SHIFT              (5U)
+/*! LOCKED - Parameter set locked: Indicates if parameter set is locked due to a pending calculation start or can be overwritten. */
+#define PKC_PKC_STATUS_LOCKED(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK)
+/*! @} */
+
+/*! @name PKC_CTRL - Control register */
+/*! @{ */
+
+#define PKC_PKC_CTRL_RESET_MASK                  (0x1U)
+#define PKC_PKC_CTRL_RESET_SHIFT                 (0U)
+/*! RESET - PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculation
+ *    cannot be started and by which any ongoing calculation process is stopped.
+ */
+#define PKC_PKC_CTRL_RESET(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK)
+
+#define PKC_PKC_CTRL_STOP_MASK                   (0x2U)
+#define PKC_PKC_CTRL_STOP_SHIFT                  (1U)
+/*! STOP - Freeze PKC calculation: STOP=1 freezes all PKC activity incl. */
+#define PKC_PKC_CTRL_STOP(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK)
+
+#define PKC_PKC_CTRL_GOD1_MASK                   (0x4U)
+#define PKC_PKC_CTRL_GOD1_SHIFT                  (2U)
+/*! GOD1 - Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will
+ *    start a direct / layer0 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1,
+ *    PKC_LEN1).
+ */
+#define PKC_PKC_CTRL_GOD1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK)
+
+#define PKC_PKC_CTRL_GOD2_MASK                   (0x8U)
+#define PKC_PKC_CTRL_GOD2_SHIFT                  (3U)
+/*! GOD2 - Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will
+ *    start a direct / layer0 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2,
+ *    PKC_LEN2).
+ */
+#define PKC_PKC_CTRL_GOD2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK)
+
+#define PKC_PKC_CTRL_GOM1_MASK                   (0x10U)
+#define PKC_PKC_CTRL_GOM1_SHIFT                  (4U)
+/*! GOM1 - Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a MC
+ *    pattern / layer1 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1,
+ *    PKC_LEN1).
+ */
+#define PKC_PKC_CTRL_GOM1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK)
+
+#define PKC_PKC_CTRL_GOM2_MASK                   (0x20U)
+#define PKC_PKC_CTRL_GOM2_SHIFT                  (5U)
+/*! GOM2 - Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a MC
+ *    pattern / layer1 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2,
+ *    PKC_LEN2).
+ */
+#define PKC_PKC_CTRL_GOM2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK)
+
+#define PKC_PKC_CTRL_GOU_MASK                    (0x40U)
+#define PKC_PKC_CTRL_GOU_SHIFT                   (6U)
+/*! GOU - Control bit to start pipe operation: If GOU is set PKC will start the pipe / layer2
+ *    operation (parameter fetch & calculation) described in section 'PKC Universal Pointer Fetch
+ *    Operation'.
+ */
+#define PKC_PKC_CTRL_GOU(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK)
+
+#define PKC_PKC_CTRL_GF2CONV_MASK                (0x80U)
+#define PKC_PKC_CTRL_GF2CONV_SHIFT               (7U)
+/*! GF2CONV - Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF(2) equivalent operation modes. */
+#define PKC_PKC_CTRL_GF2CONV(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK)
+
+#define PKC_PKC_CTRL_CLRCACHE_MASK               (0x100U)
+#define PKC_PKC_CTRL_CLRCACHE_SHIFT              (8U)
+/*! CLRCACHE - Clear universal pointer cache: Invalidates the cache such that all previously fetched
+ *    parameters are withdrawn and have to be fetched again via DMA accesses.
+ */
+#define PKC_PKC_CTRL_CLRCACHE(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK)
+
+#define PKC_PKC_CTRL_CACHE_EN_MASK               (0x200U)
+#define PKC_PKC_CTRL_CACHE_EN_SHIFT              (9U)
+/*! CACHE_EN - Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer parameters is enabled. */
+#define PKC_PKC_CTRL_CACHE_EN(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK)
+
+#define PKC_PKC_CTRL_REDMUL_MASK                 (0xC00U)
+#define PKC_PKC_CTRL_REDMUL_SHIFT                (10U)
+/*! REDMUL - Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coprocessor. */
+#define PKC_PKC_CTRL_REDMUL(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK)
+/*! @} */
+
+/*! @name PKC_CFG - Configuration register */
+/*! @{ */
+
+#define PKC_PKC_CFG_IDLEOP_MASK                  (0x1U)
+#define PKC_PKC_CFG_IDLEOP_SHIFT                 (0U)
+/*! IDLEOP - Idle operation feature not available in this version (flag is don't care). */
+#define PKC_PKC_CFG_IDLEOP(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK)
+
+#define PKC_PKC_CFG_RFU1_MASK                    (0x2U)
+#define PKC_PKC_CFG_RFU1_SHIFT                   (1U)
+/*! RFU1 - RFU */
+#define PKC_PKC_CFG_RFU1(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK)
+
+#define PKC_PKC_CFG_RFU2_MASK                    (0x4U)
+#define PKC_PKC_CFG_RFU2_SHIFT                   (2U)
+/*! RFU2 - RFU */
+#define PKC_PKC_CFG_RFU2(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK)
+
+#define PKC_PKC_CFG_CLKRND_MASK                  (0x8U)
+#define PKC_PKC_CFG_CLKRND_SHIFT                 (3U)
+/*! CLKRND - Clock randomization feature not available in this version (flag is don't care). */
+#define PKC_PKC_CFG_CLKRND(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK)
+
+#define PKC_PKC_CFG_REDMULNOISE_MASK             (0x10U)
+#define PKC_PKC_CFG_REDMULNOISE_SHIFT            (4U)
+/*! REDMULNOISE - Noise in reduced multiplier mode feature not available in this version (flag is don't care). */
+#define PKC_PKC_CFG_REDMULNOISE(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK)
+
+#define PKC_PKC_CFG_RNDDLY_MASK                  (0xE0U)
+#define PKC_PKC_CFG_RNDDLY_SHIFT                 (5U)
+/*! RNDDLY - Random delay feature not available in this version (flag is don't care). */
+#define PKC_PKC_CFG_RNDDLY(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK)
+
+#define PKC_PKC_CFG_SBXNOISE_MASK                (0x100U)
+#define PKC_PKC_CFG_SBXNOISE_SHIFT               (8U)
+/*! SBXNOISE - Noise feature not available in this version (flag is don't care). */
+#define PKC_PKC_CFG_SBXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK)
+
+#define PKC_PKC_CFG_ALPNOISE_MASK                (0x200U)
+#define PKC_PKC_CFG_ALPNOISE_SHIFT               (9U)
+/*! ALPNOISE - Noise feature not available in this version (flag is don't care). */
+#define PKC_PKC_CFG_ALPNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK)
+
+#define PKC_PKC_CFG_FMULNOISE_MASK               (0x400U)
+#define PKC_PKC_CFG_FMULNOISE_SHIFT              (10U)
+/*! FMULNOISE - Noise feature not available in this version (flag is don't care). */
+#define PKC_PKC_CFG_FMULNOISE(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK)
+/*! @} */
+
+/*! @name PKC_MODE1 - Mode register, parameter set 1 */
+/*! @{ */
+
+#define PKC_PKC_MODE1_MODE_MASK                  (0xFFU)
+#define PKC_PKC_MODE1_MODE_SHIFT                 (0U)
+/*! MODE - Calculation Mode / MC Start address:; Calculation mode of direct calculation (layer0) are
+ *    listed in a table in Section 'PKC arithmetic unit (layer 0)'.
+ */
+#define PKC_PKC_MODE1_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK)
+/*! @} */
+
+/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */
+/*! @{ */
+
+#define PKC_PKC_XYPTR1_XPTR_MASK                 (0xFFFFU)
+#define PKC_PKC_XYPTR1_XPTR_SHIFT                (0U)
+/*! XPTR - Start address of X operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL. */
+#define PKC_PKC_XYPTR1_XPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK)
+
+#define PKC_PKC_XYPTR1_YPTR_MASK                 (0xFFFF0000U)
+#define PKC_PKC_XYPTR1_YPTR_SHIFT                (16U)
+/*! YPTR - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL. */
+#define PKC_PKC_XYPTR1_YPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK)
+/*! @} */
+
+/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */
+/*! @{ */
+
+#define PKC_PKC_ZRPTR1_ZPTR_MASK                 (0xFFFFU)
+#define PKC_PKC_ZRPTR1_ZPTR_SHIFT                (0U)
+/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation
+ *    modes using CONST:; If ZPTR is used as address pointer the least significant bits are ignored
+ *    depending on PKC_CTRL.
+ */
+#define PKC_PKC_ZRPTR1_ZPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK)
+
+#define PKC_PKC_ZRPTR1_RPTR_MASK                 (0xFFFF0000U)
+#define PKC_PKC_ZRPTR1_RPTR_SHIFT                (16U)
+/*! RPTR - Start address of R result in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL. */
+#define PKC_PKC_ZRPTR1_RPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK)
+/*! @} */
+
+/*! @name PKC_LEN1 - Length register, parameter set 1 */
+/*! @{ */
+
+#define PKC_PKC_LEN1_LEN_MASK                    (0xFFFFU)
+#define PKC_PKC_LEN1_LEN_SHIFT                   (0U)
+/*! LEN - Operand length: LEN defines the length of the operands and the result in bytes. */
+#define PKC_PKC_LEN1_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK)
+
+#define PKC_PKC_LEN1_MCLEN_MASK                  (0xFFFF0000U)
+#define PKC_PKC_LEN1_MCLEN_SHIFT                 (16U)
+/*! MCLEN - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that
+ *    can be used in layer1 calculation mode, e.
+ */
+#define PKC_PKC_LEN1_MCLEN(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK)
+/*! @} */
+
+/*! @name PKC_MODE2 - Mode register, parameter set 2 */
+/*! @{ */
+
+#define PKC_PKC_MODE2_MODE_MASK                  (0xFFU)
+#define PKC_PKC_MODE2_MODE_SHIFT                 (0U)
+/*! MODE - Calculation Mode / MC Start address:; Calculation mode of direct calculation (layer0) are
+ *    listed in a table in Section 'PKC arithmetic unit (layer 0)'.
+ */
+#define PKC_PKC_MODE2_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK)
+/*! @} */
+
+/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */
+/*! @{ */
+
+#define PKC_PKC_XYPTR2_XPTR_MASK                 (0xFFFFU)
+#define PKC_PKC_XYPTR2_XPTR_SHIFT                (0U)
+/*! XPTR - Start address of X operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL. */
+#define PKC_PKC_XYPTR2_XPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK)
+
+#define PKC_PKC_XYPTR2_YPTR_MASK                 (0xFFFF0000U)
+#define PKC_PKC_XYPTR2_YPTR_SHIFT                (16U)
+/*! YPTR - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL. */
+#define PKC_PKC_XYPTR2_YPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK)
+/*! @} */
+
+/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */
+/*! @{ */
+
+#define PKC_PKC_ZRPTR2_ZPTR_MASK                 (0xFFFFU)
+#define PKC_PKC_ZRPTR2_ZPTR_SHIFT                (0U)
+/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation
+ *    modes using CONST:; If ZPTR is used as address pointer the least significant bits are ignored
+ *    depending on PKC_CTRL.
+ */
+#define PKC_PKC_ZRPTR2_ZPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPTR_SHIFT)) & PKC_PKC_ZRPTR2_ZPTR_MASK)
+
+#define PKC_PKC_ZRPTR2_RPTR_MASK                 (0xFFFF0000U)
+#define PKC_PKC_ZRPTR2_RPTR_SHIFT                (16U)
+/*! RPTR - Start address of R result in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL. */
+#define PKC_PKC_ZRPTR2_RPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK)
+/*! @} */
+
+/*! @name PKC_LEN2 - Length register, parameter set 2 */
+/*! @{ */
+
+#define PKC_PKC_LEN2_LEN_MASK                    (0xFFFFU)
+#define PKC_PKC_LEN2_LEN_SHIFT                   (0U)
+/*! LEN - Operand length: LEN defines the length of the operands and the result in bytes. */
+#define PKC_PKC_LEN2_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK)
+
+#define PKC_PKC_LEN2_MCLEN_MASK                  (0xFFFF0000U)
+#define PKC_PKC_LEN2_MCLEN_SHIFT                 (16U)
+/*! MCLEN - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that
+ *    can be used in layer1 calculation mode, e.
+ */
+#define PKC_PKC_LEN2_MCLEN(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK)
+/*! @} */
+
+/*! @name PKC_UPTR - Universal pointer FUP program */
+/*! @{ */
+
+#define PKC_PKC_UPTR_PTR_MASK                    (0xFFFFFFFFU)
+#define PKC_PKC_UPTR_PTR_SHIFT                   (0U)
+/*! PTR - Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before starting
+ *    a universal pointer PKC calculation (layer2) via PKC_CTRL.
+ */
+#define PKC_PKC_UPTR_PTR(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK)
+/*! @} */
+
+/*! @name PKC_UPTRT - Universal pointer FUP table */
+/*! @{ */
+
+#define PKC_PKC_UPTRT_PTR_MASK                   (0xFFFFFFFFU)
+#define PKC_PKC_UPTRT_PTR_SHIFT                  (0U)
+/*! PTR - Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starting a
+ *    universal pointer PKC calculation (layer2) via PKC_CTRL.
+ */
+#define PKC_PKC_UPTRT_PTR(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK)
+/*! @} */
+
+/*! @name PKC_ULEN - Universal pointer length */
+/*! @{ */
+
+#define PKC_PKC_ULEN_LEN_MASK                    (0xFFU)
+#define PKC_PKC_ULEN_LEN_SHIFT                   (0U)
+/*! LEN - Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries
+ *    shall be processed for one layer2 calculation started via PKC_CTRL.
+ */
+#define PKC_PKC_ULEN_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK)
+/*! @} */
+
+/*! @name PKC_MCDATA - MC pattern data interface */
+/*! @{ */
+
+#define PKC_PKC_MCDATA_MCDATA_MASK               (0xFFFFFFFFU)
+#define PKC_PKC_MCDATA_MCDATA_SHIFT              (0U)
+/*! MCDATA - Microcode read/write data: This IP version does not support flexible MC patterns (only hard coded ones). */
+#define PKC_PKC_MCDATA_MCDATA(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK)
+/*! @} */
+
+/*! @name PKC_VERSION - PKC version register */
+/*! @{ */
+
+#define PKC_PKC_VERSION_MULSIZE_MASK             (0x3U)
+#define PKC_PKC_VERSION_MULSIZE_SHIFT            (0U)
+/*! MULSIZE - native multiplier size and operand granularity */
+#define PKC_PKC_VERSION_MULSIZE(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK)
+
+#define PKC_PKC_VERSION_MCAVAIL_MASK             (0x4U)
+#define PKC_PKC_VERSION_MCAVAIL_SHIFT            (2U)
+/*! MCAVAIL - MC feature (layer1 calculation) is available */
+#define PKC_PKC_VERSION_MCAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK)
+
+#define PKC_PKC_VERSION_UPAVAIL_MASK             (0x8U)
+#define PKC_PKC_VERSION_UPAVAIL_SHIFT            (3U)
+/*! UPAVAIL - UP feature (layer2 calculation) is available */
+#define PKC_PKC_VERSION_UPAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK)
+
+#define PKC_PKC_VERSION_UPCACHEAVAIL_MASK        (0x10U)
+#define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT       (4U)
+/*! UPCACHEAVAIL - UP cache is available */
+#define PKC_PKC_VERSION_UPCACHEAVAIL(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK)
+
+#define PKC_PKC_VERSION_GF2AVAIL_MASK            (0x20U)
+#define PKC_PKC_VERSION_GF2AVAIL_SHIFT           (5U)
+/*! GF2AVAIL - GF2 calculation modes are available */
+#define PKC_PKC_VERSION_GF2AVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK)
+
+#define PKC_PKC_VERSION_PARAMNUM_MASK            (0xC0U)
+#define PKC_PKC_VERSION_PARAMNUM_SHIFT           (6U)
+/*! PARAMNUM - Number of parameter sets for real calculation */
+#define PKC_PKC_VERSION_PARAMNUM(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK)
+
+#define PKC_PKC_VERSION_SBX0AVAIL_MASK           (0x100U)
+#define PKC_PKC_VERSION_SBX0AVAIL_SHIFT          (8U)
+/*! SBX0AVAIL - SBX0 operation is available */
+#define PKC_PKC_VERSION_SBX0AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK)
+
+#define PKC_PKC_VERSION_SBX1AVAIL_MASK           (0x200U)
+#define PKC_PKC_VERSION_SBX1AVAIL_SHIFT          (9U)
+/*! SBX1AVAIL - SBX1 operation is available */
+#define PKC_PKC_VERSION_SBX1AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK)
+
+#define PKC_PKC_VERSION_SBX2AVAIL_MASK           (0x400U)
+#define PKC_PKC_VERSION_SBX2AVAIL_SHIFT          (10U)
+/*! SBX2AVAIL - SBX2 operation is available */
+#define PKC_PKC_VERSION_SBX2AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK)
+
+#define PKC_PKC_VERSION_SBX3AVAIL_MASK           (0x800U)
+#define PKC_PKC_VERSION_SBX3AVAIL_SHIFT          (11U)
+/*! SBX3AVAIL - SBX3 operation is available */
+#define PKC_PKC_VERSION_SBX3AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK)
+
+#define PKC_PKC_VERSION_MCRECONF_SIZE_MASK       (0xFF000U)
+#define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT      (12U)
+/*! MCRECONF_SIZE - Size of reconfigurable MC table in bytes */
+#define PKC_PKC_VERSION_MCRECONF_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK)
+/*! @} */
+
+/*! @name PKC_SOFT_RST - Software reset */
+/*! @{ */
+
+#define PKC_PKC_SOFT_RST_SOFT_RST_MASK           (0x1U)
+#define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT          (0U)
+/*! SOFT_RST - Write 1 to reset module (0 has no effect). */
+#define PKC_PKC_SOFT_RST_SOFT_RST(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK)
+/*! @} */
+
+/*! @name PKC_ACCESS_ERR - Access Error */
+/*! @{ */
+
+#define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK        (0x1U)
+#define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT       (0U)
+/*! APB_NOTAV - APB Error: address not available */
+#define PKC_PKC_ACCESS_ERR_APB_NOTAV(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK)
+
+#define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK        (0x2U)
+#define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT       (1U)
+/*! APB_WRGMD - APB Error: Wrong access mode */
+#define PKC_PKC_ACCESS_ERR_APB_WRGMD(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK)
+
+#define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK       (0xF0U)
+#define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT      (4U)
+/*! APB_MASTER - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV) */
+#define PKC_PKC_ACCESS_ERR_APB_MASTER(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK)
+
+#define PKC_PKC_ACCESS_ERR_AHB_MASK              (0x400U)
+#define PKC_PKC_ACCESS_ERR_AHB_SHIFT             (10U)
+/*! AHB - AHB Error: invalid AHB access Layer2 Only */
+#define PKC_PKC_ACCESS_ERR_AHB(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK)
+
+#define PKC_PKC_ACCESS_ERR_PKCC_MASK             (0x10000U)
+#define PKC_PKC_ACCESS_ERR_PKCC_SHIFT            (16U)
+/*! PKCC - Error in PKC coprocessor kernel */
+#define PKC_PKC_ACCESS_ERR_PKCC(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK)
+
+#define PKC_PKC_ACCESS_ERR_FDET_MASK             (0x20000U)
+#define PKC_PKC_ACCESS_ERR_FDET_SHIFT            (17U)
+/*! FDET - Error due to error detection circuitry */
+#define PKC_PKC_ACCESS_ERR_FDET(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK)
+
+#define PKC_PKC_ACCESS_ERR_CTRL_MASK             (0x40000U)
+#define PKC_PKC_ACCESS_ERR_CTRL_SHIFT            (18U)
+/*! CTRL - Error in PKC software control */
+#define PKC_PKC_ACCESS_ERR_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK)
+
+#define PKC_PKC_ACCESS_ERR_UCRC_MASK             (0x80000U)
+#define PKC_PKC_ACCESS_ERR_UCRC_SHIFT            (19U)
+/*! UCRC - Error in layer2 CRC check */
+#define PKC_PKC_ACCESS_ERR_UCRC(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK)
+/*! @} */
+
+/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */
+/*! @{ */
+
+#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK      (0x1U)
+#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT     (0U)
+/*! ERR_CLR - Write 1 to reset PKC_ACCESS_ERR SFR. */
+#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK)
+/*! @} */
+
+/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */
+/*! @{ */
+
+#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK     (0x1U)
+#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT    (0U)
+/*! EN_PDONE - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE. */
+#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK)
+/*! @} */
+
+/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */
+/*! @{ */
+
+#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK     (0x1U)
+#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT    (0U)
+/*! EN_PDONE - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE. */
+#define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK)
+/*! @} */
+
+/*! @name PKC_INT_STATUS - Interrupt status */
+/*! @{ */
+
+#define PKC_PKC_INT_STATUS_INT_PDONE_MASK        (0x1U)
+#define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT       (0U)
+/*! INT_PDONE - End-of-computation status flag: INT_PDONE is set after EACH single PKC layer0 or layer1 calculation. */
+#define PKC_PKC_INT_STATUS_INT_PDONE(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK)
+/*! @} */
+
+/*! @name PKC_INT_ENABLE - Interrupt enable */
+/*! @{ */
+
+#define PKC_PKC_INT_ENABLE_EN_PDONE_MASK         (0x1U)
+#define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT        (0U)
+/*! EN_PDONE - PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time PKC_INT_STATUS. */
+#define PKC_PKC_INT_ENABLE_EN_PDONE(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK)
+/*! @} */
+
+/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */
+/*! @{ */
+
+#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK    (0x1U)
+#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT   (0U)
+/*! INT_PDONE - Write to clear End-of-computation status flag (PKC_INT_STATUS. */
+#define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK)
+/*! @} */
+
+/*! @name PKC_INT_SET_STATUS - Interrupt status set */
+/*! @{ */
+
+#define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK    (0x1U)
+#define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT   (0U)
+/*! INT_PDONE - Write to set End-of-computation status flag (PKC_INT_STATUS. */
+#define PKC_PKC_INT_SET_STATUS_INT_PDONE(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK)
+/*! @} */
+
+/*! @name PKC_MODULE_ID - Module ID */
+/*! @{ */
+
+#define PKC_PKC_MODULE_ID_SIZE_MASK              (0xFFU)
+#define PKC_PKC_MODULE_ID_SIZE_SHIFT             (0U)
+/*! SIZE - Address space of the IP */
+#define PKC_PKC_MODULE_ID_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK)
+
+#define PKC_PKC_MODULE_ID_MINOR_REV_MASK         (0xF00U)
+#define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT        (8U)
+/*! MINOR_REV - Minor revision */
+#define PKC_PKC_MODULE_ID_MINOR_REV(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK)
+
+#define PKC_PKC_MODULE_ID_MAJOR_REV_MASK         (0xF000U)
+#define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT        (12U)
+/*! MAJOR_REV - Major revision */
+#define PKC_PKC_MODULE_ID_MAJOR_REV(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK)
+
+#define PKC_PKC_MODULE_ID_ID_MASK                (0xFFFF0000U)
+#define PKC_PKC_MODULE_ID_ID_SHIFT               (16U)
+/*! ID - Module ID */
+#define PKC_PKC_MODULE_ID_ID(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PKC_Register_Masks */
+
+
+/* PKC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral PKC base address */
+  #define PKC_BASE                                 (0x50009000u)
+  /** Peripheral PKC base address */
+  #define PKC_BASE_NS                              (0x40009000u)
+  /** Peripheral PKC base pointer */
+  #define PKC                                      ((PKC_Type *)PKC_BASE)
+  /** Peripheral PKC base pointer */
+  #define PKC_NS                                   ((PKC_Type *)PKC_BASE_NS)
+  /** Array initializer of PKC peripheral base addresses */
+  #define PKC_BASE_ADDRS                           { PKC_BASE }
+  /** Array initializer of PKC peripheral base pointers */
+  #define PKC_BASE_PTRS                            { PKC }
+  /** Array initializer of PKC peripheral base addresses */
+  #define PKC_BASE_ADDRS_NS                        { PKC_BASE_NS }
+  /** Array initializer of PKC peripheral base pointers */
+  #define PKC_BASE_PTRS_NS                         { PKC_NS }
+#else
+  /** Peripheral PKC base address */
+  #define PKC_BASE                                 (0x40009000u)
+  /** Peripheral PKC base pointer */
+  #define PKC                                      ((PKC_Type *)PKC_BASE)
+  /** Array initializer of PKC peripheral base addresses */
+  #define PKC_BASE_ADDRS                           { PKC_BASE }
+  /** Array initializer of PKC peripheral base pointers */
+  #define PKC_BASE_PTRS                            { PKC }
+#endif
+
+/*!
+ * @}
+ */ /* end of group PKC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
+ * @{
+ */
+
+/** PMU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PWR_MODE;                          /**< Power mode control register, offset: 0x0 */
+  __I  uint32_t PWR_MODE_STATUS;                   /**< Power mode status register, offset: 0x4 */
+  __IO uint32_t SYS_RST_EN;                        /**< sys reset enable resister, offset: 0x8 */
+  __I  uint32_t SYS_RST_STATUS;                    /**< Reset status Register, offset: 0xC */
+  __IO uint32_t SYS_RST_CLR;                       /**< sys reset clear resister, offset: 0x10 */
+  __IO uint32_t WAKEUP_LEVEL;                      /**< Wakeup Level Register, offset: 0x14 */
+  __IO uint32_t WAKEUP_MASK;                       /**< Wakeup Mask Interrupt Register, offset: 0x18 */
+  __I  uint32_t WAKEUP_STATUS;                     /**< Wakeup status register, offset: 0x1C */
+  __IO uint32_t WAKE_SRC_CLR;                      /**< Wake up source clear register, offset: 0x20 */
+  __IO uint32_t WL_BLE_WAKEUP_DONE;                /**< Wake up done register, offset: 0x24 */
+  __IO uint32_t CAU_SLP_CTRL;                      /**< CAU sleep clock control register, offset: 0x28 */
+  __I  uint32_t SOC_CIU_RDY;                       /**< soc_ciu_rdy register, offset: 0x2C */
+  __IO uint32_t CAPT_PULSE;                        /**< pulse in register, offset: 0x30 */
+  __IO uint32_t CAPT_PULSE_BASE_VAL;               /**< capt_pulse_base_val, offset: 0x34 */
+  __I  uint32_t CAPT_PULSE_VAL;                    /**< capt_pulse_val, offset: 0x38 */
+  __IO uint32_t XTAL32K_CTRL;                      /**< XTAL32k Control Register, offset: 0x3C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PMIP_BUCK_LVL;                     /**< PMIP BUCK LEVEL, offset: 0x44 */
+  __IO uint32_t PMIP_BUCK_CTRL;                    /**< PMIP BUCK ctrl, offset: 0x48 */
+  __IO uint32_t PMIP_LDO_LVL;                      /**< PMIP LDO level ctrl, offset: 0x4C */
+  __IO uint32_t PMIP_RST;                          /**< PMIP reset request register, offset: 0x50 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t BOD;                               /**< BOD register, offset: 0x5C */
+  __IO uint32_t MEM_CFG;                           /**< mem configuration register, offset: 0x60 */
+  __IO uint32_t RESET_DISABLE;                     /**< reset disable register, offset: 0x64 */
+  __IO uint32_t WLAN_CTRL;                         /**< WLAN Control Register, offset: 0x68 */
+  __IO uint32_t BLE_CTRL;                          /**< BLEControl Register, offset: 0x6C */
+  __IO uint32_t CLK_AON;                           /**< Always on Domain Clock select, offset: 0x70 */
+  __IO uint32_t SOC_MEM_PDWN;                      /**< soc mem pdwn register, offset: 0x74 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t AON_PAD_OUT_CTRL;                  /**< aon pad out control, offset: 0x80 */
+  __IO uint32_t WAKEUP_PM2_MASK0;                  /**< Wakeup PM2 state Mask Interrupt Register, offset: 0x84 */
+  __IO uint32_t WAKEUP_PM2_MASK1;                  /**< Wakeup PM2 state Mask Interrupt Register, offset: 0x88 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t WAKEUP_PM2_MASK3;                  /**< Wakeup PM2 state Mask Interrupt Register, offset: 0x90 */
+  __I  uint32_t WAKEUP_PM2_STATUS0;                /**< Wakeup PM2 status Register, offset: 0x94 */
+  __I  uint32_t WAKEUP_PM2_STATUS1;                /**< Wakeup PM2 status Register, offset: 0x98 */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t WAKEUP_PM2_STATUS3;                /**< WAKEUP_PM2_STATUS3, offset: 0xA0 */
+  __IO uint32_t WAKEUP_PM2_SRC_CLR0;               /**< Wakeup PM2 source clear Register, offset: 0xA4 */
+  __IO uint32_t WAKEUP_PM2_SRC_CLR1;               /**< Wakeup PM2 source clear Register, offset: 0xA8 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t WAKEUP_PM2_SRC_CLR3;               /**< Wakeup PM2 source clear Register, offset: 0xB0 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t SW_CTRL_WL;                        /**< WL part-SW Control register bypass HW output, offset: 0xB8 */
+  __IO uint32_t SW_CTRL_BLE;                       /**< BLE part-SW Control register bypass HW output, offset: 0xBC */
+       uint8_t RESERVED_7[76];
+  __IO uint32_t PSW18_OTP;                         /**< PSW18 OTP psw control signal, offset: 0x10C */
+  __IO uint32_t TIME_OUT_CTRL;                     /**< tieme out control signal, offset: 0x110 */
+  __IO uint32_t TIME_OUT_CFG_VALUE;                /**< tieme out configure value, offset: 0x114 */
+       uint8_t RESERVED_8[12];
+  __IO uint32_t RESERVE_REG0;                      /**< reserve R/W regs, offset: 0x124 */
+  __I  uint32_t RESERVE_REG1;                      /**< reserve Read only regs, offset: 0x128 */
+} PMU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMU_Register_Masks PMU Register Masks
+ * @{
+ */
+
+/*! @name PWR_MODE - Power mode control register */
+/*! @{ */
+
+#define PMU_PWR_MODE_PWR_MODE_MASK               (0x3U)
+#define PMU_PWR_MODE_PWR_MODE_SHIFT              (0U)
+/*! PWR_MODE - Power mode switch
+ *  0b00..PM0 or PM1
+ *  0b01..PM2
+ *  0b10..PM3
+ *  0b11..PM4
+ */
+#define PMU_PWR_MODE_PWR_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_PWR_MODE_PWR_MODE_SHIFT)) & PMU_PWR_MODE_PWR_MODE_MASK)
+/*! @} */
+
+/*! @name PWR_MODE_STATUS - Power mode status register */
+/*! @{ */
+
+#define PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_MASK (0x3U)
+#define PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_SHIFT (0U)
+/*! PWR_MODE_STATUS - Power mode status
+ *  0b00..PM0 or PM1
+ *  0b01..
+ *  0b10..
+ *  0b11..
+ */
+#define PMU_PWR_MODE_STATUS_PWR_MODE_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_SHIFT)) & PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_MASK)
+/*! @} */
+
+/*! @name SYS_RST_EN - sys reset enable resister */
+/*! @{ */
+
+#define PMU_SYS_RST_EN_CM33_SYSRESETREQ_EN_MASK  (0x1U)
+#define PMU_SYS_RST_EN_CM33_SYSRESETREQ_EN_SHIFT (0U)
+/*! CM33_SYSRESETREQ_EN - cm33_sysresetreq reset enable */
+#define PMU_SYS_RST_EN_CM33_SYSRESETREQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_EN_CM33_SYSRESETREQ_EN_SHIFT)) & PMU_SYS_RST_EN_CM33_SYSRESETREQ_EN_MASK)
+
+#define PMU_SYS_RST_EN_CM33_LOCKUP_EN_MASK       (0x2U)
+#define PMU_SYS_RST_EN_CM33_LOCKUP_EN_SHIFT      (1U)
+/*! CM33_LOCKUP_EN - cm33_lockup reset enable */
+#define PMU_SYS_RST_EN_CM33_LOCKUP_EN(x)         (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_EN_CM33_LOCKUP_EN_SHIFT)) & PMU_SYS_RST_EN_CM33_LOCKUP_EN_MASK)
+
+#define PMU_SYS_RST_EN_WDT_EN_MASK               (0x4U)
+#define PMU_SYS_RST_EN_WDT_EN_SHIFT              (2U)
+/*! WDT_EN - wdt rst enable */
+#define PMU_SYS_RST_EN_WDT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_EN_WDT_EN_SHIFT)) & PMU_SYS_RST_EN_WDT_EN_MASK)
+
+#define PMU_SYS_RST_EN_AP_SYSRESETREQ_EN_MASK    (0x8U)
+#define PMU_SYS_RST_EN_AP_SYSRESETREQ_EN_SHIFT   (3U)
+/*! AP_SYSRESETREQ_EN - ap_sysresetreq rst enable */
+#define PMU_SYS_RST_EN_AP_SYSRESETREQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_EN_AP_SYSRESETREQ_EN_SHIFT)) & PMU_SYS_RST_EN_AP_SYSRESETREQ_EN_MASK)
+
+#define PMU_SYS_RST_EN_CODE_WDT_EN_MASK          (0x10U)
+#define PMU_SYS_RST_EN_CODE_WDT_EN_SHIFT         (4U)
+/*! CODE_WDT_EN - code_wdt rst enable */
+#define PMU_SYS_RST_EN_CODE_WDT_EN(x)            (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_EN_CODE_WDT_EN_SHIFT)) & PMU_SYS_RST_EN_CODE_WDT_EN_MASK)
+
+#define PMU_SYS_RST_EN_ITRC_EN_MASK              (0x20U)
+#define PMU_SYS_RST_EN_ITRC_EN_SHIFT             (5U)
+/*! ITRC_EN - itrc_chip rst enable */
+#define PMU_SYS_RST_EN_ITRC_EN(x)                (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_EN_ITRC_EN_SHIFT)) & PMU_SYS_RST_EN_ITRC_EN_MASK)
+/*! @} */
+
+/*! @name SYS_RST_STATUS - Reset status Register */
+/*! @{ */
+
+#define PMU_SYS_RST_STATUS_CM33_SYSRESETREQ_MASK (0x1U)
+#define PMU_SYS_RST_STATUS_CM33_SYSRESETREQ_SHIFT (0U)
+/*! CM33_SYSRESETREQ - CM4 System software reset request
+ *  0b0..reset cause is not system software reset request
+ *  0b1..reset cause is system software reset request
+ */
+#define PMU_SYS_RST_STATUS_CM33_SYSRESETREQ(x)   (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_STATUS_CM33_SYSRESETREQ_SHIFT)) & PMU_SYS_RST_STATUS_CM33_SYSRESETREQ_MASK)
+
+#define PMU_SYS_RST_STATUS_CM33_LOCKUP_MASK      (0x2U)
+#define PMU_SYS_RST_STATUS_CM33_LOCKUP_SHIFT     (1U)
+/*! CM33_LOCKUP - CM4 Lockup
+ *  0b0..reset cause is not lockup
+ *  0b1..reset cause is lockup
+ */
+#define PMU_SYS_RST_STATUS_CM33_LOCKUP(x)        (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_STATUS_CM33_LOCKUP_SHIFT)) & PMU_SYS_RST_STATUS_CM33_LOCKUP_MASK)
+
+#define PMU_SYS_RST_STATUS_WDT_RST_MASK          (0x4U)
+#define PMU_SYS_RST_STATUS_WDT_RST_SHIFT         (2U)
+/*! WDT_RST - WDT Reset
+ *  0b0..reset cause is not watchdog timer
+ *  0b1..reset cause is watchdog timer
+ */
+#define PMU_SYS_RST_STATUS_WDT_RST(x)            (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_STATUS_WDT_RST_SHIFT)) & PMU_SYS_RST_STATUS_WDT_RST_MASK)
+
+#define PMU_SYS_RST_STATUS_AP_SYSRESETREQ_MASK   (0x8U)
+#define PMU_SYS_RST_STATUS_AP_SYSRESETREQ_SHIFT  (3U)
+/*! AP_SYSRESETREQ - Debug mailbox Reset
+ *  0b0..reset cause is not ap_sysresetreq
+ *  0b1..reset cause is ap_sysresetreq
+ */
+#define PMU_SYS_RST_STATUS_AP_SYSRESETREQ(x)     (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_STATUS_AP_SYSRESETREQ_SHIFT)) & PMU_SYS_RST_STATUS_AP_SYSRESETREQ_MASK)
+
+#define PMU_SYS_RST_STATUS_CODE_WDT_RST_MASK     (0x10U)
+#define PMU_SYS_RST_STATUS_CODE_WDT_RST_SHIFT    (4U)
+/*! CODE_WDT_RST - CODE_WDT Reset
+ *  0b0..reset cause is not code watchdog timer
+ *  0b1..reset cause is code watchdog timer
+ */
+#define PMU_SYS_RST_STATUS_CODE_WDT_RST(x)       (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_STATUS_CODE_WDT_RST_SHIFT)) & PMU_SYS_RST_STATUS_CODE_WDT_RST_MASK)
+
+#define PMU_SYS_RST_STATUS_ITRC_CHIP_RST_MASK    (0x20U)
+#define PMU_SYS_RST_STATUS_ITRC_CHIP_RST_SHIFT   (5U)
+/*! ITRC_CHIP_RST - ITRC_CHIP Reset
+ *  0b0..reset cause is not itrc chip reset
+ *  0b1..reset cause is itrc chip reset
+ */
+#define PMU_SYS_RST_STATUS_ITRC_CHIP_RST(x)      (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_STATUS_ITRC_CHIP_RST_SHIFT)) & PMU_SYS_RST_STATUS_ITRC_CHIP_RST_MASK)
+
+#define PMU_SYS_RST_STATUS_SW_RESETB_SCANTEST_MASK (0x40U)
+#define PMU_SYS_RST_STATUS_SW_RESETB_SCANTEST_SHIFT (6U)
+/*! SW_RESETB_SCANTEST - sw_resetb_scantest Reset
+ *  0b0..reset cause is not sw_resetb_scantest reset
+ *  0b1..reset cause is sw_resetb_scantest reset
+ */
+#define PMU_SYS_RST_STATUS_SW_RESETB_SCANTEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_STATUS_SW_RESETB_SCANTEST_SHIFT)) & PMU_SYS_RST_STATUS_SW_RESETB_SCANTEST_MASK)
+/*! @} */
+
+/*! @name SYS_RST_CLR - sys reset clear resister */
+/*! @{ */
+
+#define PMU_SYS_RST_CLR_CM33_SYSRESETREQ_CLR_MASK (0x1U)
+#define PMU_SYS_RST_CLR_CM33_SYSRESETREQ_CLR_SHIFT (0U)
+/*! CM33_SYSRESETREQ_CLR - cm33_sysresetreq reset clear */
+#define PMU_SYS_RST_CLR_CM33_SYSRESETREQ_CLR(x)  (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_CLR_CM33_SYSRESETREQ_CLR_SHIFT)) & PMU_SYS_RST_CLR_CM33_SYSRESETREQ_CLR_MASK)
+
+#define PMU_SYS_RST_CLR_CM33_LOCKUP_CLR_MASK     (0x2U)
+#define PMU_SYS_RST_CLR_CM33_LOCKUP_CLR_SHIFT    (1U)
+/*! CM33_LOCKUP_CLR - cm33_lockup reset clear */
+#define PMU_SYS_RST_CLR_CM33_LOCKUP_CLR(x)       (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_CLR_CM33_LOCKUP_CLR_SHIFT)) & PMU_SYS_RST_CLR_CM33_LOCKUP_CLR_MASK)
+
+#define PMU_SYS_RST_CLR_WDT_CLR_MASK             (0x4U)
+#define PMU_SYS_RST_CLR_WDT_CLR_SHIFT            (2U)
+/*! WDT_CLR - wdt rst clear */
+#define PMU_SYS_RST_CLR_WDT_CLR(x)               (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_CLR_WDT_CLR_SHIFT)) & PMU_SYS_RST_CLR_WDT_CLR_MASK)
+
+#define PMU_SYS_RST_CLR_AP_SYSRESETREQ_CLR_MASK  (0x8U)
+#define PMU_SYS_RST_CLR_AP_SYSRESETREQ_CLR_SHIFT (3U)
+/*! AP_SYSRESETREQ_CLR - ap_sysresetreq rst clear */
+#define PMU_SYS_RST_CLR_AP_SYSRESETREQ_CLR(x)    (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_CLR_AP_SYSRESETREQ_CLR_SHIFT)) & PMU_SYS_RST_CLR_AP_SYSRESETREQ_CLR_MASK)
+
+#define PMU_SYS_RST_CLR_CODE_WDT_CLR_MASK        (0x10U)
+#define PMU_SYS_RST_CLR_CODE_WDT_CLR_SHIFT       (4U)
+/*! CODE_WDT_CLR - code_wdt rst clear */
+#define PMU_SYS_RST_CLR_CODE_WDT_CLR(x)          (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_CLR_CODE_WDT_CLR_SHIFT)) & PMU_SYS_RST_CLR_CODE_WDT_CLR_MASK)
+
+#define PMU_SYS_RST_CLR_ITRC_CLR_MASK            (0x20U)
+#define PMU_SYS_RST_CLR_ITRC_CLR_SHIFT           (5U)
+/*! ITRC_CLR - itrc chip rst clear */
+#define PMU_SYS_RST_CLR_ITRC_CLR(x)              (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_CLR_ITRC_CLR_SHIFT)) & PMU_SYS_RST_CLR_ITRC_CLR_MASK)
+
+#define PMU_SYS_RST_CLR_SW_RESETB_SCANTEST_CLR_MASK (0x40U)
+#define PMU_SYS_RST_CLR_SW_RESETB_SCANTEST_CLR_SHIFT (6U)
+/*! SW_RESETB_SCANTEST_CLR - sw_resetb_scantest rst clear */
+#define PMU_SYS_RST_CLR_SW_RESETB_SCANTEST_CLR(x) (((uint32_t)(((uint32_t)(x)) << PMU_SYS_RST_CLR_SW_RESETB_SCANTEST_CLR_SHIFT)) & PMU_SYS_RST_CLR_SW_RESETB_SCANTEST_CLR_MASK)
+/*! @} */
+
+/*! @name WAKEUP_LEVEL - Wakeup Level Register */
+/*! @{ */
+
+#define PMU_WAKEUP_LEVEL_PIN0_MASK               (0x1U)
+#define PMU_WAKEUP_LEVEL_PIN0_SHIFT              (0U)
+/*! PIN0 - 0 = connect to gound wake up
+ *  0b1..connect to VDDO wake up
+ */
+#define PMU_WAKEUP_LEVEL_PIN0(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_LEVEL_PIN0_SHIFT)) & PMU_WAKEUP_LEVEL_PIN0_MASK)
+
+#define PMU_WAKEUP_LEVEL_PIN1_MASK               (0x2U)
+#define PMU_WAKEUP_LEVEL_PIN1_SHIFT              (1U)
+/*! PIN1 - 0 = connect to gound wake up
+ *  0b1..connect to VDDO wake up
+ */
+#define PMU_WAKEUP_LEVEL_PIN1(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_LEVEL_PIN1_SHIFT)) & PMU_WAKEUP_LEVEL_PIN1_MASK)
+/*! @} */
+
+/*! @name WAKEUP_MASK - Wakeup Mask Interrupt Register */
+/*! @{ */
+
+#define PMU_WAKEUP_MASK_PIN0_MASK_MASK           (0x1U)
+#define PMU_WAKEUP_MASK_PIN0_MASK_SHIFT          (0U)
+/*! PIN0_MASK - Pin0 Wakeup Mask
+ *  0b0..mask pin0 wakeup interrupt
+ *  0b1..unmask pin0 wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_PIN0_MASK(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_PIN0_MASK_SHIFT)) & PMU_WAKEUP_MASK_PIN0_MASK_MASK)
+
+#define PMU_WAKEUP_MASK_PIN1_MASK_MASK           (0x2U)
+#define PMU_WAKEUP_MASK_PIN1_MASK_SHIFT          (1U)
+/*! PIN1_MASK - Pin1 Wakeup Mask
+ *  0b0..mask pin1 wakeup interrupt
+ *  0b1..unmask pin1 wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_PIN1_MASK(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_PIN1_MASK_SHIFT)) & PMU_WAKEUP_MASK_PIN1_MASK_MASK)
+
+#define PMU_WAKEUP_MASK_RTC_MASK_MASK            (0x4U)
+#define PMU_WAKEUP_MASK_RTC_MASK_SHIFT           (2U)
+/*! RTC_MASK - RTC Wakeup Mask
+ *  0b0..mask RTC wakeup interrupt
+ *  0b1..unmask RTC wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_RTC_MASK(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_RTC_MASK_SHIFT)) & PMU_WAKEUP_MASK_RTC_MASK_MASK)
+
+#define PMU_WAKEUP_MASK_CAPT_MASK_MASK           (0x10U)
+#define PMU_WAKEUP_MASK_CAPT_MASK_SHIFT          (4U)
+/*! CAPT_MASK - capture pulse Wakeup Mask
+ *  0b0..mask capt wakeup interrupt
+ *  0b1..unmask capt wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_CAPT_MASK(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_CAPT_MASK_SHIFT)) & PMU_WAKEUP_MASK_CAPT_MASK_MASK)
+
+#define PMU_WAKEUP_MASK_WL_MASK_MASK             (0x60U)
+#define PMU_WAKEUP_MASK_WL_MASK_SHIFT            (5U)
+/*! WL_MASK - WLAN Wakeup Mask
+ *  0b00..mask WLAN wakeup interrupt
+ *  0b01..unmask WLAN wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_WL_MASK(x)               (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_WL_MASK_SHIFT)) & PMU_WAKEUP_MASK_WL_MASK_MASK)
+
+#define PMU_WAKEUP_MASK_BLE_MASK_MASK            (0x180U)
+#define PMU_WAKEUP_MASK_BLE_MASK_SHIFT           (7U)
+/*! BLE_MASK - BLE Wakeup Mask
+ *  0b00..mask BLE wakeup interrupt
+ *  0b01..unmask BLE wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_BLE_MASK(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_BLE_MASK_SHIFT)) & PMU_WAKEUP_MASK_BLE_MASK_MASK)
+
+#define PMU_WAKEUP_MASK_BOD1_MASK_MASK           (0x200U)
+#define PMU_WAKEUP_MASK_BOD1_MASK_SHIFT          (9U)
+/*! BOD1_MASK - bod1 Wakeup Mask
+ *  0b0..mask bod1 wakeup interrupt
+ *  0b1..unmask bod1 wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_BOD1_MASK(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_BOD1_MASK_SHIFT)) & PMU_WAKEUP_MASK_BOD1_MASK_MASK)
+/*! @} */
+
+/*! @name WAKEUP_STATUS - Wakeup status register */
+/*! @{ */
+
+#define PMU_WAKEUP_STATUS_PIN0_MASK              (0x1U)
+#define PMU_WAKEUP_STATUS_PIN0_SHIFT             (0U)
+/*! PIN0 - External Pin0 wakeup status */
+#define PMU_WAKEUP_STATUS_PIN0(x)                (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_PIN0_SHIFT)) & PMU_WAKEUP_STATUS_PIN0_MASK)
+
+#define PMU_WAKEUP_STATUS_PIN1_MASK              (0x2U)
+#define PMU_WAKEUP_STATUS_PIN1_SHIFT             (1U)
+/*! PIN1 - External Pin1 wakeup status */
+#define PMU_WAKEUP_STATUS_PIN1(x)                (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_PIN1_SHIFT)) & PMU_WAKEUP_STATUS_PIN1_MASK)
+
+#define PMU_WAKEUP_STATUS_RTC_MASK               (0x4U)
+#define PMU_WAKEUP_STATUS_RTC_SHIFT              (2U)
+/*! RTC - RTC wakeup status */
+#define PMU_WAKEUP_STATUS_RTC(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_RTC_SHIFT)) & PMU_WAKEUP_STATUS_RTC_MASK)
+
+#define PMU_WAKEUP_STATUS_CAPT_MASK              (0x10U)
+#define PMU_WAKEUP_STATUS_CAPT_SHIFT             (4U)
+/*! CAPT - capt interrupt wakeup status */
+#define PMU_WAKEUP_STATUS_CAPT(x)                (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_CAPT_SHIFT)) & PMU_WAKEUP_STATUS_CAPT_MASK)
+
+#define PMU_WAKEUP_STATUS_WL_MASK                (0x60U)
+#define PMU_WAKEUP_STATUS_WL_SHIFT               (5U)
+/*! WL - WL interrupt wakeup status */
+#define PMU_WAKEUP_STATUS_WL(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_WL_SHIFT)) & PMU_WAKEUP_STATUS_WL_MASK)
+
+#define PMU_WAKEUP_STATUS_BLE_MASK               (0x180U)
+#define PMU_WAKEUP_STATUS_BLE_SHIFT              (7U)
+/*! BLE - BLE interrupt wakeup status */
+#define PMU_WAKEUP_STATUS_BLE(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_BLE_SHIFT)) & PMU_WAKEUP_STATUS_BLE_MASK)
+
+#define PMU_WAKEUP_STATUS_BOD1_MASK              (0x200U)
+#define PMU_WAKEUP_STATUS_BOD1_SHIFT             (9U)
+/*! BOD1 - bod1 wakeup status */
+#define PMU_WAKEUP_STATUS_BOD1(x)                (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_BOD1_SHIFT)) & PMU_WAKEUP_STATUS_BOD1_MASK)
+/*! @} */
+
+/*! @name WAKE_SRC_CLR - Wake up source clear register */
+/*! @{ */
+
+#define PMU_WAKE_SRC_CLR_PIN0_CLR_MASK           (0x1U)
+#define PMU_WAKE_SRC_CLR_PIN0_CLR_SHIFT          (0U)
+/*! PIN0_CLR - Clear Pin0 interrupt request */
+#define PMU_WAKE_SRC_CLR_PIN0_CLR(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_PIN0_CLR_SHIFT)) & PMU_WAKE_SRC_CLR_PIN0_CLR_MASK)
+
+#define PMU_WAKE_SRC_CLR_PIN1_CLR_MASK           (0x2U)
+#define PMU_WAKE_SRC_CLR_PIN1_CLR_SHIFT          (1U)
+/*! PIN1_CLR - Clear Pin1 interrupt request */
+#define PMU_WAKE_SRC_CLR_PIN1_CLR(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_PIN1_CLR_SHIFT)) & PMU_WAKE_SRC_CLR_PIN1_CLR_MASK)
+
+#define PMU_WAKE_SRC_CLR_RTC_CLR_MASK            (0x4U)
+#define PMU_WAKE_SRC_CLR_RTC_CLR_SHIFT           (2U)
+/*! RTC_CLR - Clear RTC interrupt request */
+#define PMU_WAKE_SRC_CLR_RTC_CLR(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_RTC_CLR_SHIFT)) & PMU_WAKE_SRC_CLR_RTC_CLR_MASK)
+
+#define PMU_WAKE_SRC_CLR_CAPT_CLR_MASK           (0x10U)
+#define PMU_WAKE_SRC_CLR_CAPT_CLR_SHIFT          (4U)
+/*! CAPT_CLR - Clear capture interrupt request */
+#define PMU_WAKE_SRC_CLR_CAPT_CLR(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_CAPT_CLR_SHIFT)) & PMU_WAKE_SRC_CLR_CAPT_CLR_MASK)
+
+#define PMU_WAKE_SRC_CLR_WL_CLR_MASK             (0x60U)
+#define PMU_WAKE_SRC_CLR_WL_CLR_SHIFT            (5U)
+/*! WL_CLR - Clear WL interrupt request */
+#define PMU_WAKE_SRC_CLR_WL_CLR(x)               (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_WL_CLR_SHIFT)) & PMU_WAKE_SRC_CLR_WL_CLR_MASK)
+
+#define PMU_WAKE_SRC_CLR_BLE_CLR_MASK            (0x180U)
+#define PMU_WAKE_SRC_CLR_BLE_CLR_SHIFT           (7U)
+/*! BLE_CLR - Clear BLE interrupt request */
+#define PMU_WAKE_SRC_CLR_BLE_CLR(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_BLE_CLR_SHIFT)) & PMU_WAKE_SRC_CLR_BLE_CLR_MASK)
+
+#define PMU_WAKE_SRC_CLR_BOD1_CLR_MASK           (0x200U)
+#define PMU_WAKE_SRC_CLR_BOD1_CLR_SHIFT          (9U)
+/*! BOD1_CLR - Clear bod1 interrupt request */
+#define PMU_WAKE_SRC_CLR_BOD1_CLR(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_BOD1_CLR_SHIFT)) & PMU_WAKE_SRC_CLR_BOD1_CLR_MASK)
+/*! @} */
+
+/*! @name WL_BLE_WAKEUP_DONE - Wake up done register */
+/*! @{ */
+
+#define PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT0_MASK (0x20U)
+#define PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT0_SHIFT (5U)
+/*! WL_DONE_BIT0 - WL wake up MCI done bit0 signal */
+#define PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT0(x)   (((uint32_t)(((uint32_t)(x)) << PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT0_SHIFT)) & PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT0_MASK)
+
+#define PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT1_MASK (0x40U)
+#define PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT1_SHIFT (6U)
+/*! WL_DONE_BIT1 - WL wake up MCI done bit1 signal */
+#define PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT1(x)   (((uint32_t)(((uint32_t)(x)) << PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT1_SHIFT)) & PMU_WL_BLE_WAKEUP_DONE_WL_DONE_BIT1_MASK)
+
+#define PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT0_MASK (0x80U)
+#define PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT0_SHIFT (7U)
+/*! BLE_DONE_BIT0 - BLE wake up MCI done signal */
+#define PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT0(x)  (((uint32_t)(((uint32_t)(x)) << PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT0_SHIFT)) & PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT0_MASK)
+
+#define PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT1_MASK (0x100U)
+#define PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT1_SHIFT (8U)
+/*! BLE_DONE_BIT1 - BLE wake up MCI done signal */
+#define PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT1(x)  (((uint32_t)(((uint32_t)(x)) << PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT1_SHIFT)) & PMU_WL_BLE_WAKEUP_DONE_BLE_DONE_BIT1_MASK)
+/*! @} */
+
+/*! @name CAU_SLP_CTRL - CAU sleep clock control register */
+/*! @{ */
+
+#define PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK        (0x2U)
+#define PMU_CAU_SLP_CTRL_SOC_SLP_RDY_SHIFT       (1U)
+/*! SOC_SLP_RDY - CAU_SOC_SLP_REF_GEN_CLK is ready */
+#define PMU_CAU_SLP_CTRL_SOC_SLP_RDY(x)          (((uint32_t)(((uint32_t)(x)) << PMU_CAU_SLP_CTRL_SOC_SLP_RDY_SHIFT)) & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK)
+
+#define PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG_MASK     (0x4U)
+#define PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG_SHIFT    (2U)
+/*! CAU_SOC_SLP_CG - gate cau_soc_slp_ref_gen_clk */
+#define PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG(x)       (((uint32_t)(((uint32_t)(x)) << PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG_SHIFT)) & PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG_MASK)
+/*! @} */
+
+/*! @name SOC_CIU_RDY - soc_ciu_rdy register */
+/*! @{ */
+
+#define PMU_SOC_CIU_RDY_VAL_MASK                 (0x4U)
+#define PMU_SOC_CIU_RDY_VAL_SHIFT                (2U)
+/*! VAL - indicate soc IO strap finish, boot rom can read strap value */
+#define PMU_SOC_CIU_RDY_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_SOC_CIU_RDY_VAL_SHIFT)) & PMU_SOC_CIU_RDY_VAL_MASK)
+/*! @} */
+
+/*! @name CAPT_PULSE - pulse in register */
+/*! @{ */
+
+#define PMU_CAPT_PULSE_CAPTURE_SLOW_PULSE_CNT_EN_MASK (0x1U)
+#define PMU_CAPT_PULSE_CAPTURE_SLOW_PULSE_CNT_EN_SHIFT (0U)
+/*! CAPTURE_SLOW_PULSE_CNT_EN - enable signal */
+#define PMU_CAPT_PULSE_CAPTURE_SLOW_PULSE_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_CAPTURE_SLOW_PULSE_CNT_EN_SHIFT)) & PMU_CAPT_PULSE_CAPTURE_SLOW_PULSE_CNT_EN_MASK)
+
+#define PMU_CAPT_PULSE_CAPTURE_FAST_PULSE_CNT_EN_MASK (0x2U)
+#define PMU_CAPT_PULSE_CAPTURE_FAST_PULSE_CNT_EN_SHIFT (1U)
+/*! CAPTURE_FAST_PULSE_CNT_EN - enable signal */
+#define PMU_CAPT_PULSE_CAPTURE_FAST_PULSE_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_CAPTURE_FAST_PULSE_CNT_EN_SHIFT)) & PMU_CAPT_PULSE_CAPTURE_FAST_PULSE_CNT_EN_MASK)
+
+#define PMU_CAPT_PULSE_IC_EDGE_CLK_CNT_MASK      (0xCU)
+#define PMU_CAPT_PULSE_IC_EDGE_CLK_CNT_SHIFT     (2U)
+/*! IC_EDGE_CLK_CNT - when capture_slow_pulse_cnt_en=1, indicate the trigger condition of counter,
+ *    0: rising edge 1: falling edge ; others: both
+ */
+#define PMU_CAPT_PULSE_IC_EDGE_CLK_CNT(x)        (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_IC_EDGE_CLK_CNT_SHIFT)) & PMU_CAPT_PULSE_IC_EDGE_CLK_CNT_MASK)
+
+#define PMU_CAPT_PULSE_IC_WIDTH_CLK_CNT_MASK     (0x70U)
+#define PMU_CAPT_PULSE_IC_WIDTH_CLK_CNT_SHIFT    (4U)
+/*! IC_WIDTH_CLK_CNT - Input Capture Filter Width only used when capture_slow_pulse_cnt_en=1 */
+#define PMU_CAPT_PULSE_IC_WIDTH_CLK_CNT(x)       (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_IC_WIDTH_CLK_CNT_SHIFT)) & PMU_CAPT_PULSE_IC_WIDTH_CLK_CNT_MASK)
+
+#define PMU_CAPT_PULSE_IRQ_CLR_MASK              (0x80U)
+#define PMU_CAPT_PULSE_IRQ_CLR_SHIFT             (7U)
+/*! IRQ_CLR - clear the interrupt and wakeup */
+#define PMU_CAPT_PULSE_IRQ_CLR(x)                (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_IRQ_CLR_SHIFT)) & PMU_CAPT_PULSE_IRQ_CLR_MASK)
+
+#define PMU_CAPT_PULSE_IRQ_STATUS_MASK           (0x100U)
+#define PMU_CAPT_PULSE_IRQ_STATUS_SHIFT          (8U)
+/*! IRQ_STATUS - interrupt status */
+#define PMU_CAPT_PULSE_IRQ_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_IRQ_STATUS_SHIFT)) & PMU_CAPT_PULSE_IRQ_STATUS_MASK)
+
+#define PMU_CAPT_PULSE_IRQ_MSK_MASK              (0x200U)
+#define PMU_CAPT_PULSE_IRQ_MSK_SHIFT             (9U)
+/*! IRQ_MSK - only mask the interrupt */
+#define PMU_CAPT_PULSE_IRQ_MSK(x)                (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_IRQ_MSK_SHIFT)) & PMU_CAPT_PULSE_IRQ_MSK_MASK)
+
+#define PMU_CAPT_PULSE_CLK_SEL_MASK              (0x400U)
+#define PMU_CAPT_PULSE_CLK_SEL_SHIFT             (10U)
+/*! CLK_SEL - 0 choose 32k for slow capture,1 choose 3.84/4M for fast capture as functional clock */
+#define PMU_CAPT_PULSE_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_CLK_SEL_SHIFT)) & PMU_CAPT_PULSE_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CAPT_PULSE_BASE_VAL - capt_pulse_base_val */
+/*! @{ */
+
+#define PMU_CAPT_PULSE_BASE_VAL_CAPTURE_CNT_BASE_VAL_MASK (0xFFFFFFFFU)
+#define PMU_CAPT_PULSE_BASE_VAL_CAPTURE_CNT_BASE_VAL_SHIFT (0U)
+/*! CAPTURE_CNT_BASE_VAL - the counter reaches this register value, interrupt will be generated */
+#define PMU_CAPT_PULSE_BASE_VAL_CAPTURE_CNT_BASE_VAL(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_BASE_VAL_CAPTURE_CNT_BASE_VAL_SHIFT)) & PMU_CAPT_PULSE_BASE_VAL_CAPTURE_CNT_BASE_VAL_MASK)
+/*! @} */
+
+/*! @name CAPT_PULSE_VAL - capt_pulse_val */
+/*! @{ */
+
+#define PMU_CAPT_PULSE_VAL_CAPTURE_CNT_VAL_MASK  (0xFFFFFFFFU)
+#define PMU_CAPT_PULSE_VAL_CAPTURE_CNT_VAL_SHIFT (0U)
+/*! CAPTURE_CNT_VAL - counter pulse value */
+#define PMU_CAPT_PULSE_VAL_CAPTURE_CNT_VAL(x)    (((uint32_t)(((uint32_t)(x)) << PMU_CAPT_PULSE_VAL_CAPTURE_CNT_VAL_SHIFT)) & PMU_CAPT_PULSE_VAL_CAPTURE_CNT_VAL_MASK)
+/*! @} */
+
+/*! @name XTAL32K_CTRL - XTAL32k Control Register */
+/*! @{ */
+
+#define PMU_XTAL32K_CTRL_X32K_RDY_MASK           (0x1U)
+#define PMU_XTAL32K_CTRL_X32K_RDY_SHIFT          (0U)
+/*! X32K_RDY - Assert high when ready */
+#define PMU_XTAL32K_CTRL_X32K_RDY(x)             (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_RDY_SHIFT)) & PMU_XTAL32K_CTRL_X32K_RDY_MASK)
+
+#define PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_MASK   (0x6U)
+#define PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_SHIFT  (1U)
+/*! X32K_STUP_ASSIST - Use startup assist ckt for 32 kHz xosc */
+#define PMU_XTAL32K_CTRL_X32K_STUP_ASSIST(x)     (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_SHIFT)) & PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_MASK)
+
+#define PMU_XTAL32K_CTRL_X32K_TEST_EN_MASK       (0x8U)
+#define PMU_XTAL32K_CTRL_X32K_TEST_EN_SHIFT      (3U)
+/*! X32K_TEST_EN - Test enabling for 32k xtal ckt */
+#define PMU_XTAL32K_CTRL_X32K_TEST_EN(x)         (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_TEST_EN_SHIFT)) & PMU_XTAL32K_CTRL_X32K_TEST_EN_MASK)
+
+#define PMU_XTAL32K_CTRL_X32K_TMODE_MASK         (0x30U)
+#define PMU_XTAL32K_CTRL_X32K_TMODE_SHIFT        (4U)
+/*! X32K_TMODE - Test mode enabling for 32k xtal ckt */
+#define PMU_XTAL32K_CTRL_X32K_TMODE(x)           (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_TMODE_SHIFT)) & PMU_XTAL32K_CTRL_X32K_TMODE_MASK)
+
+#define PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_MASK    (0x300U)
+#define PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_SHIFT   (8U)
+/*! X32K_VDDXO_CNTL - Control VDDXO level */
+#define PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL(x)      (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_SHIFT)) & PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_MASK)
+
+#define PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_MASK    (0x400U)
+#define PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_SHIFT   (10U)
+/*! X32K_EXT_OSC_EN - Enable external oscillator mode for outside clock */
+#define PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN(x)      (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_SHIFT)) & PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_MASK)
+
+#define PMU_XTAL32K_CTRL_X32K_EN_MASK            (0x800U)
+#define PMU_XTAL32K_CTRL_X32K_EN_SHIFT           (11U)
+/*! X32K_EN - Enable 32k oscillator */
+#define PMU_XTAL32K_CTRL_X32K_EN(x)              (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_EN_SHIFT)) & PMU_XTAL32K_CTRL_X32K_EN_MASK)
+
+#define PMU_XTAL32K_CTRL_X32K_DLY_SEL_MASK       (0x3000U)
+#define PMU_XTAL32K_CTRL_X32K_DLY_SEL_SHIFT      (12U)
+/*! X32K_DLY_SEL - 32k Delay Select */
+#define PMU_XTAL32K_CTRL_X32K_DLY_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_DLY_SEL_SHIFT)) & PMU_XTAL32K_CTRL_X32K_DLY_SEL_MASK)
+/*! @} */
+
+/*! @name PMIP_BUCK_LVL - PMIP BUCK LEVEL */
+/*! @{ */
+
+#define PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL_MASK (0x7FU)
+#define PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL_SHIFT (0U)
+/*! NORMAL_BUCK11_SEL - Select normal mode output voltage for v11_aon VOUT = LVL*5mV + 630mV */
+#define PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL(x)   (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL_SHIFT)) & PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL_MASK)
+
+#define PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL_MASK (0x7F00U)
+#define PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL_SHIFT (8U)
+/*! NORMAL_BUCK18_SEL - Select normal mode output voltage for v18_aon VOUT = LVL*10mV + 840mV */
+#define PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL(x)   (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL_SHIFT)) & PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL_MASK)
+
+#define PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL_MASK  (0x7F0000U)
+#define PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL_SHIFT (16U)
+/*! SLEEP_BUCK11_SEL - Select sleep mode output voltage for v11_aon VOUT = LVL*5mV + 630mV */
+#define PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL(x)    (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL_SHIFT)) & PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL_MASK)
+
+#define PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL_MASK  (0x7F000000U)
+#define PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL_SHIFT (24U)
+/*! SLEEP_BUCK18_SEL - Select sleep mode output voltage for v18_aon VOUT = LVL*10mV + 840mV */
+#define PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL(x)    (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL_SHIFT)) & PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL_MASK)
+/*! @} */
+
+/*! @name PMIP_BUCK_CTRL - PMIP BUCK ctrl */
+/*! @{ */
+
+#define PMU_PMIP_BUCK_CTRL_BUCK11_SLP_EN_MASK    (0x1U)
+#define PMU_PMIP_BUCK_CTRL_BUCK11_SLP_EN_SHIFT   (0U)
+/*! BUCK11_SLP_EN - 1'b1: sleep mode; 1'b0: active mode. */
+#define PMU_PMIP_BUCK_CTRL_BUCK11_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_CTRL_BUCK11_SLP_EN_SHIFT)) & PMU_PMIP_BUCK_CTRL_BUCK11_SLP_EN_MASK)
+
+#define PMU_PMIP_BUCK_CTRL_BUCK11_SW_PD_MASK     (0x2U)
+#define PMU_PMIP_BUCK_CTRL_BUCK11_SW_PD_SHIFT    (1U)
+/*! BUCK11_SW_PD - Power Down BUCK11 */
+#define PMU_PMIP_BUCK_CTRL_BUCK11_SW_PD(x)       (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_CTRL_BUCK11_SW_PD_SHIFT)) & PMU_PMIP_BUCK_CTRL_BUCK11_SW_PD_MASK)
+
+#define PMU_PMIP_BUCK_CTRL_BUCK18_SLP_EN_MASK    (0x4U)
+#define PMU_PMIP_BUCK_CTRL_BUCK18_SLP_EN_SHIFT   (2U)
+/*! BUCK18_SLP_EN - 1'b1: sleep mode; 1'b0: active mode. */
+#define PMU_PMIP_BUCK_CTRL_BUCK18_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_CTRL_BUCK18_SLP_EN_SHIFT)) & PMU_PMIP_BUCK_CTRL_BUCK18_SLP_EN_MASK)
+
+#define PMU_PMIP_BUCK_CTRL_BUCK18_SW_PD_MASK     (0x8U)
+#define PMU_PMIP_BUCK_CTRL_BUCK18_SW_PD_SHIFT    (3U)
+/*! BUCK18_SW_PD - Power Down BUCK18 */
+#define PMU_PMIP_BUCK_CTRL_BUCK18_SW_PD(x)       (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_CTRL_BUCK18_SW_PD_SHIFT)) & PMU_PMIP_BUCK_CTRL_BUCK18_SW_PD_MASK)
+
+#define PMU_PMIP_BUCK_CTRL_PM3_BUCK11_ON_MASK    (0x40U)
+#define PMU_PMIP_BUCK_CTRL_PM3_BUCK11_ON_SHIFT   (6U)
+/*! PM3_BUCK11_ON - provide a enable when sleep condition:1'b1:PM3 BUCK11 ON;1'b0:PM3 BUCK11 SLEEP */
+#define PMU_PMIP_BUCK_CTRL_PM3_BUCK11_ON(x)      (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_CTRL_PM3_BUCK11_ON_SHIFT)) & PMU_PMIP_BUCK_CTRL_PM3_BUCK11_ON_MASK)
+
+#define PMU_PMIP_BUCK_CTRL_PM3_BUCK18_ON_MASK    (0x80U)
+#define PMU_PMIP_BUCK_CTRL_PM3_BUCK18_ON_SHIFT   (7U)
+/*! PM3_BUCK18_ON - provide a enable when sleep condition:1'b1:PM3 BUCK18 ON;1'b0:PM3 BUCK18 SLEEP */
+#define PMU_PMIP_BUCK_CTRL_PM3_BUCK18_ON(x)      (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BUCK_CTRL_PM3_BUCK18_ON_SHIFT)) & PMU_PMIP_BUCK_CTRL_PM3_BUCK18_ON_MASK)
+/*! @} */
+
+/*! @name PMIP_LDO_LVL - PMIP LDO level ctrl */
+/*! @{ */
+
+#define PMU_PMIP_LDO_LVL_LDO18_SEL_MASK          (0x7U)
+#define PMU_PMIP_LDO_LVL_LDO18_SEL_SHIFT         (0U)
+/*! LDO18_SEL - Select output voltage for v18_aon
+ *  0b000..1.60V
+ *  0b001..1.65V
+ *  0b010..1.70V
+ *  0b011..1.75V
+ *  0b100..1.80V
+ *  0b101..1.85V
+ *  0b110..1.90V
+ *  0b111..1.95V
+ */
+#define PMU_PMIP_LDO_LVL_LDO18_SEL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_LVL_LDO18_SEL_SHIFT)) & PMU_PMIP_LDO_LVL_LDO18_SEL_MASK)
+
+#define PMU_PMIP_LDO_LVL_LDO11_SEL_MASK          (0x70U)
+#define PMU_PMIP_LDO_LVL_LDO11_SEL_SHIFT         (4U)
+/*! LDO11_SEL - Select output voltage for v11_aon
+ *  0b000..0.75V
+ *  0b001..0.80V
+ *  0b010..0.85V
+ *  0b011..0.90V
+ *  0b100..0.95V
+ *  0b101..1.00V
+ *  0b110..1.05V
+ *  0b111..1.10V
+ */
+#define PMU_PMIP_LDO_LVL_LDO11_SEL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_LVL_LDO11_SEL_SHIFT)) & PMU_PMIP_LDO_LVL_LDO11_SEL_MASK)
+/*! @} */
+
+/*! @name PMIP_RST - PMIP reset request register */
+/*! @{ */
+
+#define PMU_PMIP_RST_SW_RST_REQ_MASK             (0x1U)
+#define PMU_PMIP_RST_SW_RST_REQ_SHIFT            (0U)
+/*! SW_RST_REQ - PMIP software por request
+ *  0b0..no rst request
+ *  0b1..send rst request, need write 1->0->1->0 sequence
+ */
+#define PMU_PMIP_RST_SW_RST_REQ(x)               (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_RST_SW_RST_REQ_SHIFT)) & PMU_PMIP_RST_SW_RST_REQ_MASK)
+/*! @} */
+
+/*! @name BOD - BOD register */
+/*! @{ */
+
+#define PMU_BOD_EN_MASK                          (0x1U)
+#define PMU_BOD_EN_SHIFT                         (0U)
+/*! EN - bod enable */
+#define PMU_BOD_EN(x)                            (((uint32_t)(((uint32_t)(x)) << PMU_BOD_EN_SHIFT)) & PMU_BOD_EN_MASK)
+
+#define PMU_BOD__1_85_INT_NEG_MASK               (0x10U)
+#define PMU_BOD__1_85_INT_NEG_SHIFT              (4U)
+/*! _1_85_INT_NEG - bod_1_85_int negedge */
+#define PMU_BOD__1_85_INT_NEG(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_BOD__1_85_INT_NEG_SHIFT)) & PMU_BOD__1_85_INT_NEG_MASK)
+
+#define PMU_BOD__1_85_INT_CLR_NEG_MASK           (0x20U)
+#define PMU_BOD__1_85_INT_CLR_NEG_SHIFT          (5U)
+/*! _1_85_INT_CLR_NEG - clr bod_1_85_int negedge */
+#define PMU_BOD__1_85_INT_CLR_NEG(x)             (((uint32_t)(((uint32_t)(x)) << PMU_BOD__1_85_INT_CLR_NEG_SHIFT)) & PMU_BOD__1_85_INT_CLR_NEG_MASK)
+/*! @} */
+
+/*! @name MEM_CFG - mem configuration register */
+/*! @{ */
+
+#define PMU_MEM_CFG_MEM_RET_MASK                 (0x3FU)
+#define PMU_MEM_CFG_MEM_RET_SHIFT                (0U)
+/*! MEM_RET - mem Retention enable register in PM3 mode
+ *  0b000000..in PM3, it will keep retention
+ *  0b000001..in PM3, it will shut down
+ */
+#define PMU_MEM_CFG_MEM_RET(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MEM_CFG_MEM_RET_SHIFT)) & PMU_MEM_CFG_MEM_RET_MASK)
+
+#define PMU_MEM_CFG_AON_MEM_RET_MASK             (0x100U)
+#define PMU_MEM_CFG_AON_MEM_RET_SHIFT            (8U)
+/*! AON_MEM_RET - aon mem Retention enable register in PM4 mode
+ *  0b0..in PM4, it will keep retention
+ *  0b1..in PM4, it will shut down
+ */
+#define PMU_MEM_CFG_AON_MEM_RET(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MEM_CFG_AON_MEM_RET_SHIFT)) & PMU_MEM_CFG_AON_MEM_RET_MASK)
+/*! @} */
+
+/*! @name RESET_DISABLE - reset disable register */
+/*! @{ */
+
+#define PMU_RESET_DISABLE_PINMUX_MASK            (0x1U)
+#define PMU_RESET_DISABLE_PINMUX_SHIFT           (0U)
+/*! PINMUX - avoid reset warm reset
+ *  0b0..not disable warm reset for pinmux
+ *  0b1..disable warm reset for pinmux
+ */
+#define PMU_RESET_DISABLE_PINMUX(x)              (((uint32_t)(((uint32_t)(x)) << PMU_RESET_DISABLE_PINMUX_SHIFT)) & PMU_RESET_DISABLE_PINMUX_MASK)
+/*! @} */
+
+/*! @name WLAN_CTRL - WLAN Control Register */
+/*! @{ */
+
+#define PMU_WLAN_CTRL_WL_XOSC_EN_MASK            (0x2U)
+#define PMU_WLAN_CTRL_WL_XOSC_EN_SHIFT           (1U)
+/*! WL_XOSC_EN - wl request control different modes for CAU XTAL (1 for normal mode, 0 for sleep/full PD) */
+#define PMU_WLAN_CTRL_WL_XOSC_EN(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_WL_XOSC_EN_SHIFT)) & PMU_WLAN_CTRL_WL_XOSC_EN_MASK)
+
+#define PMU_WLAN_CTRL_WL_SLEEP_MASK              (0xCU)
+#define PMU_WLAN_CTRL_WL_SLEEP_SHIFT             (2U)
+/*! WL_SLEEP - WLAN SYS sleep; bit[0]:SOCWLAPU_WLGATED_PSW_PD_AON, bit[1]:cpu1_cp15_sleep */
+#define PMU_WLAN_CTRL_WL_SLEEP(x)                (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_WL_SLEEP_SHIFT)) & PMU_WLAN_CTRL_WL_SLEEP_MASK)
+
+#define PMU_WLAN_CTRL_WL_WAKEUP_MASK             (0xFF00U)
+#define PMU_WLAN_CTRL_WL_WAKEUP_SHIFT            (8U)
+/*! WL_WAKEUP - MCI_WL_WAKEUP */
+#define PMU_WLAN_CTRL_WL_WAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_WL_WAKEUP_SHIFT)) & PMU_WLAN_CTRL_WL_WAKEUP_MASK)
+/*! @} */
+
+/*! @name BLE_CTRL - BLEControl Register */
+/*! @{ */
+
+#define PMU_BLE_CTRL_BLE_XOSC_EN_MASK            (0x2U)
+#define PMU_BLE_CTRL_BLE_XOSC_EN_SHIFT           (1U)
+/*! BLE_XOSC_EN - ble request control different modes for CAU XTAL (1 for normal mode, 0 for sleep/full PD) */
+#define PMU_BLE_CTRL_BLE_XOSC_EN(x)              (((uint32_t)(((uint32_t)(x)) << PMU_BLE_CTRL_BLE_XOSC_EN_SHIFT)) & PMU_BLE_CTRL_BLE_XOSC_EN_MASK)
+
+#define PMU_BLE_CTRL_BLE_SLEEP_MASK              (0xCU)
+#define PMU_BLE_CTRL_BLE_SLEEP_SHIFT             (2U)
+/*! BLE_SLEEP - BLE SYS sleep; bit[0]:SOCBTAPU_BLEGATED_PSW_PD_AON, bit[1]:cpu2_cp15_sleep */
+#define PMU_BLE_CTRL_BLE_SLEEP(x)                (((uint32_t)(((uint32_t)(x)) << PMU_BLE_CTRL_BLE_SLEEP_SHIFT)) & PMU_BLE_CTRL_BLE_SLEEP_MASK)
+
+#define PMU_BLE_CTRL_BLE_WAKEUP_MASK             (0xFF00U)
+#define PMU_BLE_CTRL_BLE_WAKEUP_SHIFT            (8U)
+/*! BLE_WAKEUP - MCI_BLE_WAKEUP */
+#define PMU_BLE_CTRL_BLE_WAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << PMU_BLE_CTRL_BLE_WAKEUP_SHIFT)) & PMU_BLE_CTRL_BLE_WAKEUP_MASK)
+/*! @} */
+
+/*! @name CLK_AON - Always on Domain Clock select */
+/*! @{ */
+
+#define PMU_CLK_AON_CLK_32K_AON_MASK             (0x3U)
+#define PMU_CLK_AON_CLK_32K_AON_SHIFT            (0U)
+/*! CLK_32K_AON - 32K clock select for PMU and RTC
+ *  0b00..RC32K clock
+ *  0b01..XTAL32K clock
+ *  0b10..NCO32K clock
+ */
+#define PMU_CLK_AON_CLK_32K_AON(x)               (((uint32_t)(((uint32_t)(x)) << PMU_CLK_AON_CLK_32K_AON_SHIFT)) & PMU_CLK_AON_CLK_32K_AON_MASK)
+
+#define PMU_CLK_AON_PMU_CLK_MASK                 (0x4U)
+#define PMU_CLK_AON_PMU_CLK_SHIFT                (2U)
+/*! PMU_CLK - pmu clock select
+ *  0b0..fast clock, sys clock after divider
+ *  0b1..slow clock,clk_32k
+ */
+#define PMU_CLK_AON_PMU_CLK(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_CLK_AON_PMU_CLK_SHIFT)) & PMU_CLK_AON_PMU_CLK_MASK)
+
+#define PMU_CLK_AON_PMIP_SLOW_CLK_RDY_MASK       (0x10U)
+#define PMU_CLK_AON_PMIP_SLOW_CLK_RDY_SHIFT      (4U)
+/*! PMIP_SLOW_CLK_RDY - one of 32k source ready signal
+ *  0b0..none 32k is ready
+ *  0b1..one of 32k source is ready
+ */
+#define PMU_CLK_AON_PMIP_SLOW_CLK_RDY(x)         (((uint32_t)(((uint32_t)(x)) << PMU_CLK_AON_PMIP_SLOW_CLK_RDY_SHIFT)) & PMU_CLK_AON_PMIP_SLOW_CLK_RDY_MASK)
+/*! @} */
+
+/*! @name SOC_MEM_PDWN - soc mem pdwn register */
+/*! @{ */
+
+#define PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_CTRL_MASK  (0x1U)
+#define PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_CTRL_SHIFT (0U)
+/*! MSC_MEM_PDWN_CTRL - msc mem pdwn control register
+ *  0b0..HW control mem_pdwn
+ *  0b1..SW CFG mem_pdwn
+ */
+#define PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_CTRL_SHIFT)) & PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_CTRL_MASK)
+
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN_CTRL_MASK (0x2U)
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN_CTRL_SHIFT (1U)
+/*! SOCTOP_OTP_PDWN_CTRL - soc top otp pdwn control register
+ *  0b0..HW control pdwn
+ *  0b1..SW CFG pdwn
+ */
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN_CTRL_SHIFT)) & PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN_CTRL_MASK)
+
+#define PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_MASK       (0x10U)
+#define PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_SHIFT      (4U)
+/*! MSC_MEM_PDWN - msc mem pdwn cfg register
+ *  0b0..de-assert mem_pdwn
+ *  0b1..assert mem_pdwn
+ */
+#define PMU_SOC_MEM_PDWN_MSC_MEM_PDWN(x)         (((uint32_t)(((uint32_t)(x)) << PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_SHIFT)) & PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_MASK)
+
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN0_MASK   (0x20U)
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN0_SHIFT  (5U)
+/*! SOCTOP_OTP_PDWN0 - soc_top_otp_pdwn0 cfg register
+ *  0b0..de-assert pdwn
+ *  0b1..assert pdwn
+ */
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN0(x)     (((uint32_t)(((uint32_t)(x)) << PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN0_SHIFT)) & PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN0_MASK)
+
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN1_MASK   (0x40U)
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN1_SHIFT  (6U)
+/*! SOCTOP_OTP_PDWN1 - soc_top_otp_pdwn1 cfg register
+ *  0b0..de-assert pdwn
+ *  0b1..assert pdwn
+ */
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN1(x)     (((uint32_t)(((uint32_t)(x)) << PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN1_SHIFT)) & PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN1_MASK)
+
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN2_MASK   (0x80U)
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN2_SHIFT  (7U)
+/*! SOCTOP_OTP_PDWN2 - soc_top_otp_pdwn2 cfg register
+ *  0b0..de-assert pdwn
+ *  0b1..assert pdwn
+ */
+#define PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN2(x)     (((uint32_t)(((uint32_t)(x)) << PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN2_SHIFT)) & PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN2_MASK)
+/*! @} */
+
+/*! @name AON_PAD_OUT_CTRL - aon pad out control */
+/*! @{ */
+
+#define PMU_AON_PAD_OUT_CTRL_EN_MASK             (0x1U)
+#define PMU_AON_PAD_OUT_CTRL_EN_SHIFT            (0U)
+/*! EN - aon pad ouput en */
+#define PMU_AON_PAD_OUT_CTRL_EN(x)               (((uint32_t)(((uint32_t)(x)) << PMU_AON_PAD_OUT_CTRL_EN_SHIFT)) & PMU_AON_PAD_OUT_CTRL_EN_MASK)
+
+#define PMU_AON_PAD_OUT_CTRL_VALUE_MASK          (0x2U)
+#define PMU_AON_PAD_OUT_CTRL_VALUE_SHIFT         (1U)
+/*! VALUE - aon pad output value */
+#define PMU_AON_PAD_OUT_CTRL_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << PMU_AON_PAD_OUT_CTRL_VALUE_SHIFT)) & PMU_AON_PAD_OUT_CTRL_VALUE_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_MASK0 - Wakeup PM2 state Mask Interrupt Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_MASK0_WDT0_MASK           (0x1U)
+#define PMU_WAKEUP_PM2_MASK0_WDT0_SHIFT          (0U)
+/*! WDT0 - WDT0 Wakeup Mask
+ *  0b0..mask wdt0 wakeup interrupt
+ *  0b1..unmask wdt0 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_WDT0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_WDT0_SHIFT)) & PMU_WAKEUP_PM2_MASK0_WDT0_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_DMA0_MASK           (0x2U)
+#define PMU_WAKEUP_PM2_MASK0_DMA0_SHIFT          (1U)
+/*! DMA0 - DMA0 Wakeup Mask
+ *  0b0..mask dma0 wakeup interrupt
+ *  0b1..unmask dma0 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_DMA0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_DMA0_SHIFT)) & PMU_WAKEUP_PM2_MASK0_DMA0_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_GPIO_INTA_MASK      (0x4U)
+#define PMU_WAKEUP_PM2_MASK0_GPIO_INTA_SHIFT     (2U)
+/*! GPIO_INTA - GPIO_INTA Wakeup Mask
+ *  0b0..mask gpio_inta wakeup interrupt
+ *  0b1..unmask gpio_inta wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_GPIO_INTA(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_GPIO_INTA_SHIFT)) & PMU_WAKEUP_PM2_MASK0_GPIO_INTA_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_GPIO_INTB_MASK      (0x8U)
+#define PMU_WAKEUP_PM2_MASK0_GPIO_INTB_SHIFT     (3U)
+/*! GPIO_INTB - GPIO_INTB Wakeup Mask
+ *  0b0..mask gpio_intb wakeup interrupt
+ *  0b1..unmask gpio_intb wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_GPIO_INTB(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_GPIO_INTB_SHIFT)) & PMU_WAKEUP_PM2_MASK0_GPIO_INTB_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT0_MASK       (0x10U)
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT0_SHIFT      (4U)
+/*! PIN_INT0 - PIN_INT0 Wakeup Mask
+ *  0b0..mask pin_int0 wakeup interrupt
+ *  0b1..unmask pin_int0 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT0(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_PIN_INT0_SHIFT)) & PMU_WAKEUP_PM2_MASK0_PIN_INT0_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT1_MASK       (0x20U)
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT1_SHIFT      (5U)
+/*! PIN_INT1 - PIN_INT1 Wakeup Mask
+ *  0b0..mask pin_int1 wakeup interrupt
+ *  0b1..unmask pin_int1 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT1(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_PIN_INT1_SHIFT)) & PMU_WAKEUP_PM2_MASK0_PIN_INT1_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT2_MASK       (0x40U)
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT2_SHIFT      (6U)
+/*! PIN_INT2 - PIN_INT2 Wakeup Mask
+ *  0b0..mask pin_int2 wakeup interrupt
+ *  0b1..unmask pin_int2 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT2(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_PIN_INT2_SHIFT)) & PMU_WAKEUP_PM2_MASK0_PIN_INT2_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT3_MASK       (0x80U)
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT3_SHIFT      (7U)
+/*! PIN_INT3 - PIN_INT3 Wakeup Mask
+ *  0b0..mask pin_int3 wakeup interrupt
+ *  0b1..unmask pin_int3 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_PIN_INT3(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_PIN_INT3_SHIFT)) & PMU_WAKEUP_PM2_MASK0_PIN_INT3_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_UTICK_MASK          (0x100U)
+#define PMU_WAKEUP_PM2_MASK0_UTICK_SHIFT         (8U)
+/*! UTICK - UTICK Wakeup Mask
+ *  0b0..mask utick wakeup interrupt
+ *  0b1..unmask utick wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_UTICK(x)            (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_UTICK_SHIFT)) & PMU_WAKEUP_PM2_MASK0_UTICK_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_MRT_MASK            (0x200U)
+#define PMU_WAKEUP_PM2_MASK0_MRT_SHIFT           (9U)
+/*! MRT - MRT Wakeup Mask
+ *  0b0..mask mrt wakeup interrupt
+ *  0b1..unmask mrt wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_MRT(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_MRT_SHIFT)) & PMU_WAKEUP_PM2_MASK0_MRT_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_CTIMER0_MASK        (0x400U)
+#define PMU_WAKEUP_PM2_MASK0_CTIMER0_SHIFT       (10U)
+/*! CTIMER0 - CTIMER0 Wakeup Mask
+ *  0b0..mask ctimer0 wakeup interrupt
+ *  0b1..unmask ctimer0 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_CTIMER0(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_CTIMER0_SHIFT)) & PMU_WAKEUP_PM2_MASK0_CTIMER0_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_CTIMER1_MASK        (0x800U)
+#define PMU_WAKEUP_PM2_MASK0_CTIMER1_SHIFT       (11U)
+/*! CTIMER1 - CTIMER1 Wakeup Mask
+ *  0b0..mask CTIMER1 wakeup interrupt
+ *  0b1..unmask CTIMER1 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_CTIMER1(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_CTIMER1_SHIFT)) & PMU_WAKEUP_PM2_MASK0_CTIMER1_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_SCT0_MASK           (0x1000U)
+#define PMU_WAKEUP_PM2_MASK0_SCT0_SHIFT          (12U)
+/*! SCT0 - SCT0 Wakeup Mask
+ *  0b0..mask sct0 wakeup interrupt
+ *  0b1..unmask sct0 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_SCT0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_SCT0_SHIFT)) & PMU_WAKEUP_PM2_MASK0_SCT0_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_CTIMER3_MASK        (0x2000U)
+#define PMU_WAKEUP_PM2_MASK0_CTIMER3_SHIFT       (13U)
+/*! CTIMER3 - CTIMER3 Wakeup Mask
+ *  0b0..mask ctimer3 wakeup interrupt
+ *  0b1..unmask ctimer3 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_CTIMER3(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_CTIMER3_SHIFT)) & PMU_WAKEUP_PM2_MASK0_CTIMER3_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM0_MASK      (0x4000U)
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM0_SHIFT     (14U)
+/*! FLEXCOMM0 - FLEXCOMM0 Wakeup Mask
+ *  0b0..mask flexcomm0 wakeup interrupt
+ *  0b1..unmask flexcomm0 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM0(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_FLEXCOMM0_SHIFT)) & PMU_WAKEUP_PM2_MASK0_FLEXCOMM0_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM1_MASK      (0x8000U)
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM1_SHIFT     (15U)
+/*! FLEXCOMM1 - FLEXCOMM1 Wakeup Mask
+ *  0b0..mask flexcomm1 wakeup interrupt
+ *  0b1..unmask flexcomm1 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM1(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_FLEXCOMM1_SHIFT)) & PMU_WAKEUP_PM2_MASK0_FLEXCOMM1_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM2_MASK      (0x10000U)
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM2_SHIFT     (16U)
+/*! FLEXCOMM2 - FLEXCOMM2 Wakeup Mask
+ *  0b0..mask flexcomm2 wakeup interrupt
+ *  0b1..unmask flexcomm2 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM2(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_FLEXCOMM2_SHIFT)) & PMU_WAKEUP_PM2_MASK0_FLEXCOMM2_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM3_MASK      (0x20000U)
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM3_SHIFT     (17U)
+/*! FLEXCOMM3 - FLEXCOMM3 Wakeup Mask
+ *  0b0..mask flexcomm3 wakeup interrupt
+ *  0b1..unmask flexcomm3 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM3(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_FLEXCOMM3_SHIFT)) & PMU_WAKEUP_PM2_MASK0_FLEXCOMM3_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM14_MASK     (0x100000U)
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM14_SHIFT    (20U)
+/*! FLEXCOMM14 - FLEXCOMM14 Wakeup Mask
+ *  0b0..mask flexcomm14 wakeup interrupt
+ *  0b1..unmask flexcomm14 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_FLEXCOMM14(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_FLEXCOMM14_SHIFT)) & PMU_WAKEUP_PM2_MASK0_FLEXCOMM14_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_FREEMRT_GLOBAL_MASK (0x800000U)
+#define PMU_WAKEUP_PM2_MASK0_FREEMRT_GLOBAL_SHIFT (23U)
+/*! FREEMRT_GLOBAL - Free Multi-rate timer Wakeup Mask
+ *  0b0..mask freemrt_global wakeup interrupt
+ *  0b1..unmask freemrt_global wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_FREEMRT_GLOBAL(x)   (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_FREEMRT_GLOBAL_SHIFT)) & PMU_WAKEUP_PM2_MASK0_FREEMRT_GLOBAL_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_DMIC_MASK           (0x2000000U)
+#define PMU_WAKEUP_PM2_MASK0_DMIC_SHIFT          (25U)
+/*! DMIC - DMIC Wakeup Mask
+ *  0b0..mask dmic wakeup interrupt
+ *  0b1..unmask dmic wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_DMIC(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_DMIC_SHIFT)) & PMU_WAKEUP_PM2_MASK0_DMIC_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_WAKEUP_FROM_DEEPSLEEP_MASK (0x4000000U)
+#define PMU_WAKEUP_PM2_MASK0_WAKEUP_FROM_DEEPSLEEP_SHIFT (26U)
+/*! WAKEUP_FROM_DEEPSLEEP - Wakeup from Deepsleep Wakeup Mask
+ *  0b0..mask wakeup_from_deepsleep wakeup interrupt
+ *  0b1..unmask wakeup_from_deepsleep wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_WAKEUP_FROM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_WAKEUP_FROM_DEEPSLEEP_SHIFT)) & PMU_WAKEUP_PM2_MASK0_WAKEUP_FROM_DEEPSLEEP_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_HYPERVISOR_MASK     (0x8000000U)
+#define PMU_WAKEUP_PM2_MASK0_HYPERVISOR_SHIFT    (27U)
+/*! HYPERVISOR - HYPERVISOR Wakeup Mask
+ *  0b0..mask hypervisor wakeup interrupt
+ *  0b1..unmask hypervisor wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_HYPERVISOR(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_HYPERVISOR_SHIFT)) & PMU_WAKEUP_PM2_MASK0_HYPERVISOR_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_SECUREVIOLATION_MASK (0x10000000U)
+#define PMU_WAKEUP_PM2_MASK0_SECUREVIOLATION_SHIFT (28U)
+/*! SECUREVIOLATION - Secure Violation Wakeup Mask
+ *  0b0..mask secure violation wakeup interrupt
+ *  0b1..unmask secure violation wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_SECUREVIOLATION(x)  (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_SECUREVIOLATION_SHIFT)) & PMU_WAKEUP_PM2_MASK0_SECUREVIOLATION_MASK)
+
+#define PMU_WAKEUP_PM2_MASK0_HWVAD_MASK          (0x20000000U)
+#define PMU_WAKEUP_PM2_MASK0_HWVAD_SHIFT         (29U)
+/*! HWVAD - Hardware Voice Activity Detector Wakeup Mask
+ *  0b0..mask hwvad wakeup interrupt
+ *  0b1..unmask hwvad wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK0_HWVAD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK0_HWVAD_SHIFT)) & PMU_WAKEUP_PM2_MASK0_HWVAD_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_MASK1 - Wakeup PM2 state Mask Interrupt Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_MASK1_RTC_MASK            (0x1U)
+#define PMU_WAKEUP_PM2_MASK1_RTC_SHIFT           (0U)
+/*! RTC - RTC Wakeup Mask
+ *  0b0..mask rtc wakeup interrupt
+ *  0b1..unmask rtc wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_RTC(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_RTC_SHIFT)) & PMU_WAKEUP_PM2_MASK1_RTC_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT4_MASK       (0x8U)
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT4_SHIFT      (3U)
+/*! PIN_INT4 - PIN_INT4 Wakeup Mask
+ *  0b0..mask pin_int4 wakeup interrupt
+ *  0b1..unmask pin_int4 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT4(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_PIN_INT4_SHIFT)) & PMU_WAKEUP_PM2_MASK1_PIN_INT4_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT5_MASK       (0x10U)
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT5_SHIFT      (4U)
+/*! PIN_INT5 - PIN_INT5 Wakeup Mask
+ *  0b0..mask pin_int5 wakeup interrupt
+ *  0b1..unmask pin_int5 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT5(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_PIN_INT5_SHIFT)) & PMU_WAKEUP_PM2_MASK1_PIN_INT5_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT6_MASK       (0x20U)
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT6_SHIFT      (5U)
+/*! PIN_INT6 - PIN_INT6 Wakeup Mask
+ *  0b0..mask pin_int6 wakeup interrupt
+ *  0b1..unmask pin_int6 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT6(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_PIN_INT6_SHIFT)) & PMU_WAKEUP_PM2_MASK1_PIN_INT6_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT7_MASK       (0x40U)
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT7_SHIFT      (6U)
+/*! PIN_INT7 - PIN_INT7 Wakeup Mask
+ *  0b0..mask pin_int7 wakeup interrupt
+ *  0b1..unmask pin_int7 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_PIN_INT7(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_PIN_INT7_SHIFT)) & PMU_WAKEUP_PM2_MASK1_PIN_INT7_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_CTIMER2_MASK        (0x80U)
+#define PMU_WAKEUP_PM2_MASK1_CTIMER2_SHIFT       (7U)
+/*! CTIMER2 - CTIMER2 Wakeup Mask
+ *  0b0..mask ctimer2 wakeup interrupt
+ *  0b1..unmask ctimer2 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_CTIMER2(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_CTIMER2_SHIFT)) & PMU_WAKEUP_PM2_MASK1_CTIMER2_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_OS_EVENT_TIMER_MASK (0x200U)
+#define PMU_WAKEUP_PM2_MASK1_OS_EVENT_TIMER_SHIFT (9U)
+/*! OS_EVENT_TIMER - OS_EVENT_TIMER Wakeup Mask
+ *  0b0..mask os_event_timer wakeup interrupt
+ *  0b1..unmask os_event_timer wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_OS_EVENT_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_OS_EVENT_TIMER_SHIFT)) & PMU_WAKEUP_PM2_MASK1_OS_EVENT_TIMER_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_FLEX_SPI_MASK       (0x400U)
+#define PMU_WAKEUP_PM2_MASK1_FLEX_SPI_SHIFT      (10U)
+/*! FLEX_SPI - Flex SPI Wakeup Mask
+ *  0b0..mask flex_spi wakeup interrupt
+ *  0b1..unmask flex_spi wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_FLEX_SPI(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_FLEX_SPI_SHIFT)) & PMU_WAKEUP_PM2_MASK1_FLEX_SPI_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_SDU_MASK            (0x4000U)
+#define PMU_WAKEUP_PM2_MASK1_SDU_SHIFT           (14U)
+/*! SDU - SDU Wakeup Mask
+ *  0b0..mask sdu wakeup interrupt
+ *  0b1..unmask sdu wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_SDU(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_SDU_SHIFT)) & PMU_WAKEUP_PM2_MASK1_SDU_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_SGPIO_INTA_MASK     (0x8000U)
+#define PMU_WAKEUP_PM2_MASK1_SGPIO_INTA_SHIFT    (15U)
+/*! SGPIO_INTA - SGPIO_INTA Wakeup Mask
+ *  0b0..mask sgpio_inta wakeup interrupt
+ *  0b1..unmask sgpio_inta wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_SGPIO_INTA(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_SGPIO_INTA_SHIFT)) & PMU_WAKEUP_PM2_MASK1_SGPIO_INTA_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_SGPIO_INTB_MASK     (0x10000U)
+#define PMU_WAKEUP_PM2_MASK1_SGPIO_INTB_SHIFT    (16U)
+/*! SGPIO_INTB - SGPIO_INTB Wakeup Mask
+ *  0b0..mask sgpio_intb wakeup interrupt
+ *  0b1..unmask sgpio_intb wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_SGPIO_INTB(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_SGPIO_INTB_SHIFT)) & PMU_WAKEUP_PM2_MASK1_SGPIO_INTB_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_USB_MASK            (0x40000U)
+#define PMU_WAKEUP_PM2_MASK1_USB_SHIFT           (18U)
+/*! USB - USB Wakeup Mask
+ *  0b0..mask usb wakeup interrupt
+ *  0b1..unmask usb wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_USB(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_USB_SHIFT)) & PMU_WAKEUP_PM2_MASK1_USB_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_DMA1_MASK           (0x400000U)
+#define PMU_WAKEUP_PM2_MASK1_DMA1_SHIFT          (22U)
+/*! DMA1 - DMA1 Wakeup Mask
+ *  0b0..mask dma1 wakeup interrupt
+ *  0b1..unmask dma1 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_DMA1(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_DMA1_SHIFT)) & PMU_WAKEUP_PM2_MASK1_DMA1_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_PUF_MASK            (0x800000U)
+#define PMU_WAKEUP_PM2_MASK1_PUF_SHIFT           (23U)
+/*! PUF - PUF Wakeup Mask
+ *  0b0..mask puf wakeup interrupt
+ *  0b1..unmask puf wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_PUF(x)              (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_PUF_SHIFT)) & PMU_WAKEUP_PM2_MASK1_PUF_MASK)
+
+#define PMU_WAKEUP_PM2_MASK1_POWER_QUAD_MASK     (0x1000000U)
+#define PMU_WAKEUP_PM2_MASK1_POWER_QUAD_SHIFT    (24U)
+/*! POWER_QUAD - POWER QUAD Wakeup Mask
+ *  0b0..mask power_quad wakeup interrupt
+ *  0b1..unmask power_quad wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK1_POWER_QUAD(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK1_POWER_QUAD_SHIFT)) & PMU_WAKEUP_PM2_MASK1_POWER_QUAD_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_MASK3 - Wakeup PM2 state Mask Interrupt Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPDAC_INT_FUN11_MASK (0x1000U)
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPDAC_INT_FUN11_SHIFT (12U)
+/*! GAU_GPDAC_INT_FUN11 - gau_gpdac_int_fun11 Wakeup Mask
+ *  0b0..mask gau_gpdac_int_fun11 wakeup interrupt
+ *  0b1..unmask gau_gpdac_int_fun11 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPDAC_INT_FUN11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_GAU_GPDAC_INT_FUN11_SHIFT)) & PMU_WAKEUP_PM2_MASK3_GAU_GPDAC_INT_FUN11_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_WKUP11_MASK (0x2000U)
+#define PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_WKUP11_SHIFT (13U)
+/*! GAU_ACOMP_INT_WKUP11 - gau_acomp_int_wkup11 Wakeup Mask
+ *  0b0..mask gau_acomp_int_wkup11 wakeup interrupt
+ *  0b1..unmask gau_acomp_int_wkup11 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_WKUP11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_WKUP11_SHIFT)) & PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_WKUP11_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_FUNC11_MASK (0x4000U)
+#define PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_FUNC11_SHIFT (14U)
+/*! GAU_ACOMP_INT_FUNC11 - gau_acomp_int_func11 Wakeup Mask
+ *  0b0..mask gau_acomp_int_func11 wakeup interrupt
+ *  0b1..unmask gau_acomp_int_func11 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_MASK3_GAU_ACOMP_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPADC1_INT_FUNC11_MASK (0x8000U)
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPADC1_INT_FUNC11_SHIFT (15U)
+/*! GAU_GPADC1_INT_FUNC11 - gau_gpadc1_int_func11 Wakeup Mask
+ *  0b0..mask gau_gpadc1_int_func11 wakeup interrupt
+ *  0b1..unmask gau_gpadc1_int_func11 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPADC1_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_GAU_GPADC1_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_MASK3_GAU_GPADC1_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPADC0_INT_FUNC11_MASK (0x10000U)
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPADC0_INT_FUNC11_SHIFT (16U)
+/*! GAU_GPADC0_INT_FUNC11 - gau_gpadc0_int_func11 Wakeup Mask
+ *  0b0..mask gau_gpadc0_int_func11 wakeup interrupt
+ *  0b1..unmask gau_gpadc0_int_func11 wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_GAU_GPADC0_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_GAU_GPADC0_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_MASK3_GAU_GPADC0_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_USIM_MASK           (0x20000U)
+#define PMU_WAKEUP_PM2_MASK3_USIM_SHIFT          (17U)
+/*! USIM - usim Wakeup Mask
+ *  0b0..mask usim wakeup interrupt
+ *  0b1..unmask usim wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_USIM(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_USIM_SHIFT)) & PMU_WAKEUP_PM2_MASK3_USIM_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_ENET_MASK           (0x80000U)
+#define PMU_WAKEUP_PM2_MASK3_ENET_SHIFT          (19U)
+/*! ENET - enet Wakeup Mask
+ *  0b0..mask enet wakeup interrupt
+ *  0b1..unmask enet wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_ENET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_ENET_SHIFT)) & PMU_WAKEUP_PM2_MASK3_ENET_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_ENET_TIMER_MASK     (0x100000U)
+#define PMU_WAKEUP_PM2_MASK3_ENET_TIMER_SHIFT    (20U)
+/*! ENET_TIMER - enet_timer Wakeup Mask
+ *  0b0..mask enet_timer wakeup interrupt
+ *  0b1..unmask enet_timer wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_ENET_TIMER(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_ENET_TIMER_SHIFT)) & PMU_WAKEUP_PM2_MASK3_ENET_TIMER_MASK)
+
+#define PMU_WAKEUP_PM2_MASK3_ITRC_RST_MASK       (0x800000U)
+#define PMU_WAKEUP_PM2_MASK3_ITRC_RST_SHIFT      (23U)
+/*! ITRC_RST - itrc_rst Wakeup Mask
+ *  0b0..mask itrc_rst wakeup interrupt
+ *  0b1..unmask itrc_rst wakeup interrupt
+ */
+#define PMU_WAKEUP_PM2_MASK3_ITRC_RST(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_MASK3_ITRC_RST_SHIFT)) & PMU_WAKEUP_PM2_MASK3_ITRC_RST_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_STATUS0 - Wakeup PM2 status Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_STATUS0_WDT0_MASK         (0x1U)
+#define PMU_WAKEUP_PM2_STATUS0_WDT0_SHIFT        (0U)
+/*! WDT0 - WDT0 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_WDT0(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_WDT0_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_WDT0_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_DMA0_MASK         (0x2U)
+#define PMU_WAKEUP_PM2_STATUS0_DMA0_SHIFT        (1U)
+/*! DMA0 - DMA0 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_DMA0(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_DMA0_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_DMA0_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_GPIO_INTA_MASK    (0x4U)
+#define PMU_WAKEUP_PM2_STATUS0_GPIO_INTA_SHIFT   (2U)
+/*! GPIO_INTA - GPIO_INTA interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_GPIO_INTA(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_GPIO_INTA_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_GPIO_INTA_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_GPIO_INTB_MASK    (0x8U)
+#define PMU_WAKEUP_PM2_STATUS0_GPIO_INTB_SHIFT   (3U)
+/*! GPIO_INTB - GPIO_INTB interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_GPIO_INTB(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_GPIO_INTB_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_GPIO_INTB_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT0_MASK     (0x10U)
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT0_SHIFT    (4U)
+/*! PIN_INT0 - PIN_INT0 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT0(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_PIN_INT0_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_PIN_INT0_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT1_MASK     (0x20U)
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT1_SHIFT    (5U)
+/*! PIN_INT1 - PIN_INT1 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT1(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_PIN_INT1_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_PIN_INT1_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT2_MASK     (0x40U)
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT2_SHIFT    (6U)
+/*! PIN_INT2 - PIN_INT2 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT2(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_PIN_INT2_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_PIN_INT2_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT3_MASK     (0x80U)
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT3_SHIFT    (7U)
+/*! PIN_INT3 - PIN_INT3 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_PIN_INT3(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_PIN_INT3_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_PIN_INT3_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_UTICK_MASK        (0x100U)
+#define PMU_WAKEUP_PM2_STATUS0_UTICK_SHIFT       (8U)
+/*! UTICK - UTICK interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_UTICK(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_UTICK_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_UTICK_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_MRT_MASK          (0x200U)
+#define PMU_WAKEUP_PM2_STATUS0_MRT_SHIFT         (9U)
+/*! MRT - MRT interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_MRT(x)            (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_MRT_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_MRT_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER0_MASK      (0x400U)
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER0_SHIFT     (10U)
+/*! CTIMER0 - CTIMER0 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER0(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_CTIMER0_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_CTIMER0_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER1_MASK      (0x800U)
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER1_SHIFT     (11U)
+/*! CTIMER1 - CTIMER1 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER1(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_CTIMER1_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_CTIMER1_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_SCT0_MASK         (0x1000U)
+#define PMU_WAKEUP_PM2_STATUS0_SCT0_SHIFT        (12U)
+/*! SCT0 - SCT0 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_SCT0(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_SCT0_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_SCT0_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER3_MASK      (0x2000U)
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER3_SHIFT     (13U)
+/*! CTIMER3 - CTIMER3 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_CTIMER3(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_CTIMER3_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_CTIMER3_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM0_MASK    (0x4000U)
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM0_SHIFT   (14U)
+/*! FLEXCOMM0 - FLEXCOMM0 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM0(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_FLEXCOMM0_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_FLEXCOMM0_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM1_MASK    (0x8000U)
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM1_SHIFT   (15U)
+/*! FLEXCOMM1 - FLEXCOMM1 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM1(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_FLEXCOMM1_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_FLEXCOMM1_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM2_MASK    (0x10000U)
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM2_SHIFT   (16U)
+/*! FLEXCOMM2 - FLEXCOMM2 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM2(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_FLEXCOMM2_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_FLEXCOMM2_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM3_MASK    (0x20000U)
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM3_SHIFT   (17U)
+/*! FLEXCOMM3 - FLEXCOMM3 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM3(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_FLEXCOMM3_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_FLEXCOMM3_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM14_MASK   (0x100000U)
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM14_SHIFT  (20U)
+/*! FLEXCOMM14 - FLEXCOMM14 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_FLEXCOMM14(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_FLEXCOMM14_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_FLEXCOMM14_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_FREEMRT_GLOBAL_MASK (0x800000U)
+#define PMU_WAKEUP_PM2_STATUS0_FREEMRT_GLOBAL_SHIFT (23U)
+/*! FREEMRT_GLOBAL - Free Multi-rate timer interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_FREEMRT_GLOBAL(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_FREEMRT_GLOBAL_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_FREEMRT_GLOBAL_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_DMIC_MASK         (0x2000000U)
+#define PMU_WAKEUP_PM2_STATUS0_DMIC_SHIFT        (25U)
+/*! DMIC - DMIC interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_DMIC(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_DMIC_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_DMIC_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_WAKEUP_FROM_DEEPSLEEP_MASK (0x4000000U)
+#define PMU_WAKEUP_PM2_STATUS0_WAKEUP_FROM_DEEPSLEEP_SHIFT (26U)
+/*! WAKEUP_FROM_DEEPSLEEP - Wakeup from Deepsleep interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_WAKEUP_FROM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_WAKEUP_FROM_DEEPSLEEP_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_WAKEUP_FROM_DEEPSLEEP_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_HYPERVISOR_MASK   (0x8000000U)
+#define PMU_WAKEUP_PM2_STATUS0_HYPERVISOR_SHIFT  (27U)
+/*! HYPERVISOR - HYPERVISOR interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_HYPERVISOR(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_HYPERVISOR_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_HYPERVISOR_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_SECUREVIOLATION_MASK (0x10000000U)
+#define PMU_WAKEUP_PM2_STATUS0_SECUREVIOLATION_SHIFT (28U)
+/*! SECUREVIOLATION - Secure Violation interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_SECUREVIOLATION(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_SECUREVIOLATION_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_SECUREVIOLATION_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS0_HWVAD_MASK        (0x20000000U)
+#define PMU_WAKEUP_PM2_STATUS0_HWVAD_SHIFT       (29U)
+/*! HWVAD - Hardware Voice Activity Detector interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS0_HWVAD(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS0_HWVAD_SHIFT)) & PMU_WAKEUP_PM2_STATUS0_HWVAD_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_STATUS1 - Wakeup PM2 status Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_STATUS1_RTC_MASK          (0x1U)
+#define PMU_WAKEUP_PM2_STATUS1_RTC_SHIFT         (0U)
+/*! RTC - rtc interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_RTC(x)            (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_RTC_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_RTC_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT4_MASK     (0x8U)
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT4_SHIFT    (3U)
+/*! PIN_INT4 - PIN_INT4 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT4(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_PIN_INT4_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_PIN_INT4_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT5_MASK     (0x10U)
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT5_SHIFT    (4U)
+/*! PIN_INT5 - PIN_INT5 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT5(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_PIN_INT5_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_PIN_INT5_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT6_MASK     (0x20U)
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT6_SHIFT    (5U)
+/*! PIN_INT6 - PIN_INT6 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT6(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_PIN_INT6_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_PIN_INT6_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT7_MASK     (0x40U)
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT7_SHIFT    (6U)
+/*! PIN_INT7 - PIN_INT7 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_PIN_INT7(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_PIN_INT7_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_PIN_INT7_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_CTIMER2_MASK      (0x80U)
+#define PMU_WAKEUP_PM2_STATUS1_CTIMER2_SHIFT     (7U)
+/*! CTIMER2 - CTIMER2 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_CTIMER2(x)        (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_CTIMER2_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_CTIMER2_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_OS_EVENT_TIMER_MASK (0x200U)
+#define PMU_WAKEUP_PM2_STATUS1_OS_EVENT_TIMER_SHIFT (9U)
+/*! OS_EVENT_TIMER - OS_EVENT_TIMER interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_OS_EVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_OS_EVENT_TIMER_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_OS_EVENT_TIMER_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_FLEX_SPI_MASK     (0x400U)
+#define PMU_WAKEUP_PM2_STATUS1_FLEX_SPI_SHIFT    (10U)
+/*! FLEX_SPI - Flex SPI interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_FLEX_SPI(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_FLEX_SPI_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_FLEX_SPI_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_SDU_MASK          (0x4000U)
+#define PMU_WAKEUP_PM2_STATUS1_SDU_SHIFT         (14U)
+/*! SDU - SDU interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_SDU(x)            (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_SDU_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_SDU_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_SGPIO_INTA_MASK   (0x8000U)
+#define PMU_WAKEUP_PM2_STATUS1_SGPIO_INTA_SHIFT  (15U)
+/*! SGPIO_INTA - SGPIO_INTA interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_SGPIO_INTA(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_SGPIO_INTA_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_SGPIO_INTA_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_SGPIO_INTB_MASK   (0x10000U)
+#define PMU_WAKEUP_PM2_STATUS1_SGPIO_INTB_SHIFT  (16U)
+/*! SGPIO_INTB - SGPIO_INTB interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_SGPIO_INTB(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_SGPIO_INTB_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_SGPIO_INTB_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_USB_MASK          (0x40000U)
+#define PMU_WAKEUP_PM2_STATUS1_USB_SHIFT         (18U)
+/*! USB - USB interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_USB(x)            (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_USB_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_USB_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_DMA1_MASK         (0x400000U)
+#define PMU_WAKEUP_PM2_STATUS1_DMA1_SHIFT        (22U)
+/*! DMA1 - DMA1 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_DMA1(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_DMA1_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_DMA1_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_PUF_MASK          (0x800000U)
+#define PMU_WAKEUP_PM2_STATUS1_PUF_SHIFT         (23U)
+/*! PUF - PUF interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_PUF(x)            (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_PUF_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_PUF_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS1_POWER_QUAD_MASK   (0x1000000U)
+#define PMU_WAKEUP_PM2_STATUS1_POWER_QUAD_SHIFT  (24U)
+/*! POWER_QUAD - POWER QUAD interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS1_POWER_QUAD(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS1_POWER_QUAD_SHIFT)) & PMU_WAKEUP_PM2_STATUS1_POWER_QUAD_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_STATUS3 - WAKEUP_PM2_STATUS3 */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPDAC_INT_FUN11_MASK (0x1000U)
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPDAC_INT_FUN11_SHIFT (12U)
+/*! GAU_GPDAC_INT_FUN11 - gau_gpdac_int_fun11 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPDAC_INT_FUN11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_GAU_GPDAC_INT_FUN11_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_GAU_GPDAC_INT_FUN11_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_WKUP11_MASK (0x2000U)
+#define PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_WKUP11_SHIFT (13U)
+/*! GAU_ACOMP_INT_WKUP11 - gau_acomp_int_wkup11 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_WKUP11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_WKUP11_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_WKUP11_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_FUNC11_MASK (0x4000U)
+#define PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_FUNC11_SHIFT (14U)
+/*! GAU_ACOMP_INT_FUNC11 - gau_acomp_int_func11 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_GAU_ACOMP_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPADC1_INT_FUNC11_MASK (0x8000U)
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPADC1_INT_FUNC11_SHIFT (15U)
+/*! GAU_GPADC1_INT_FUNC11 - gau_gpadc1_int_func11 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPADC1_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_GAU_GPADC1_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_GAU_GPADC1_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPADC0_INT_FUNC11_MASK (0x10000U)
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPADC0_INT_FUNC11_SHIFT (16U)
+/*! GAU_GPADC0_INT_FUNC11 - gau_gpadc0_int_func11 interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_GAU_GPADC0_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_GAU_GPADC0_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_GAU_GPADC0_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_USIM_MASK         (0x20000U)
+#define PMU_WAKEUP_PM2_STATUS3_USIM_SHIFT        (17U)
+/*! USIM - usim interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_USIM(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_USIM_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_USIM_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_ENET_MASK         (0x80000U)
+#define PMU_WAKEUP_PM2_STATUS3_ENET_SHIFT        (19U)
+/*! ENET - enet interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_ENET(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_ENET_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_ENET_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_ENET_TIMER_MASK   (0x100000U)
+#define PMU_WAKEUP_PM2_STATUS3_ENET_TIMER_SHIFT  (20U)
+/*! ENET_TIMER - enet_timer interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_ENET_TIMER(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_ENET_TIMER_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_ENET_TIMER_MASK)
+
+#define PMU_WAKEUP_PM2_STATUS3_ITRC_RST_MASK     (0x800000U)
+#define PMU_WAKEUP_PM2_STATUS3_ITRC_RST_SHIFT    (23U)
+/*! ITRC_RST - itrc_rst interrupt wakeup status */
+#define PMU_WAKEUP_PM2_STATUS3_ITRC_RST(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_STATUS3_ITRC_RST_SHIFT)) & PMU_WAKEUP_PM2_STATUS3_ITRC_RST_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_SRC_CLR0 - Wakeup PM2 source clear Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_WDT0_MASK        (0x1U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_WDT0_SHIFT       (0U)
+/*! WDT0 - clear WDT0 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_WDT0(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_WDT0_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_WDT0_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_DMA0_MASK        (0x2U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_DMA0_SHIFT       (1U)
+/*! DMA0 - clear DMA0 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_DMA0(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_DMA0_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_DMA0_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTA_MASK   (0x4U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTA_SHIFT  (2U)
+/*! GPIO_INTA - clear GPIO_INTA interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTA(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTA_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTA_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTB_MASK   (0x8U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTB_SHIFT  (3U)
+/*! GPIO_INTB - clear GPIO_INTB interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTB(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTB_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_GPIO_INTB_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT0_MASK    (0x10U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT0_SHIFT   (4U)
+/*! PIN_INT0 - clear PIN_INT0 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT0(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT0_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT0_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT1_MASK    (0x20U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT1_SHIFT   (5U)
+/*! PIN_INT1 - clear PIN_INT1 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT1(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT1_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT1_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT2_MASK    (0x40U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT2_SHIFT   (6U)
+/*! PIN_INT2 - clear PIN_INT2 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT2(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT2_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT2_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT3_MASK    (0x80U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT3_SHIFT   (7U)
+/*! PIN_INT3 - clear PIN_INT3 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT3(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT3_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_PIN_INT3_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_UTICK_MASK       (0x100U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_UTICK_SHIFT      (8U)
+/*! UTICK - clear UTICK interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_UTICK(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_UTICK_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_UTICK_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_MRT_MASK         (0x200U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_MRT_SHIFT        (9U)
+/*! MRT - clear MRT interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_MRT(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_MRT_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_MRT_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER0_MASK     (0x400U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER0_SHIFT    (10U)
+/*! CTIMER0 - clear CTIMER0 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER0(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_CTIMER0_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_CTIMER0_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER1_MASK     (0x800U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER1_SHIFT    (11U)
+/*! CTIMER1 - clear CTIMER1 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER1(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_CTIMER1_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_CTIMER1_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_SCT0_MASK        (0x1000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_SCT0_SHIFT       (12U)
+/*! SCT0 - clear SCT0 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_SCT0(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_SCT0_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_SCT0_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER3_MASK     (0x2000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER3_SHIFT    (13U)
+/*! CTIMER3 - clear CTIMER3 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_CTIMER3(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_CTIMER3_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_CTIMER3_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM0_MASK   (0x4000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM0_SHIFT  (14U)
+/*! FLEXCOMM0 - clear FLEXCOMM0 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM0(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM0_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM0_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM1_MASK   (0x8000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM1_SHIFT  (15U)
+/*! FLEXCOMM1 - clear FLEXCOMM1 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM1(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM1_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM1_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM2_MASK   (0x10000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM2_SHIFT  (16U)
+/*! FLEXCOMM2 - clear FLEXCOMM2 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM2(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM2_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM2_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM3_MASK   (0x20000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM3_SHIFT  (17U)
+/*! FLEXCOMM3 - clear FLEXCOMM3 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM3(x)     (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM3_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM3_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM14_MASK  (0x100000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM14_SHIFT (20U)
+/*! FLEXCOMM14 - clear FLEXCOMM14 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM14(x)    (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM14_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_FLEXCOMM14_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_FREEMRT_GLOBAL_MASK (0x800000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_FREEMRT_GLOBAL_SHIFT (23U)
+/*! FREEMRT_GLOBAL - clear Free Multi-rate timer interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_FREEMRT_GLOBAL(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_FREEMRT_GLOBAL_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_FREEMRT_GLOBAL_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_DMIC_MASK        (0x2000000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_DMIC_SHIFT       (25U)
+/*! DMIC - clear DMIC interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_DMIC(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_DMIC_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_DMIC_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_WAKEUP_FROM_DEEPSLEEP_MASK (0x4000000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_WAKEUP_FROM_DEEPSLEEP_SHIFT (26U)
+/*! WAKEUP_FROM_DEEPSLEEP - clear Wakeup from Deepsleep interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_WAKEUP_FROM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_WAKEUP_FROM_DEEPSLEEP_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_WAKEUP_FROM_DEEPSLEEP_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_HYPERVISOR_MASK  (0x8000000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_HYPERVISOR_SHIFT (27U)
+/*! HYPERVISOR - clear HYPERVISOR interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_HYPERVISOR(x)    (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_HYPERVISOR_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_HYPERVISOR_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_SECUREVIOLATION_MASK (0x10000000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_SECUREVIOLATION_SHIFT (28U)
+/*! SECUREVIOLATION - clear Secure Violation interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_SECUREVIOLATION(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_SECUREVIOLATION_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_SECUREVIOLATION_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR0_HWVAD_MASK       (0x20000000U)
+#define PMU_WAKEUP_PM2_SRC_CLR0_HWVAD_SHIFT      (29U)
+/*! HWVAD - clear Hardware Voice Activity Detector interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR0_HWVAD(x)         (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR0_HWVAD_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR0_HWVAD_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_SRC_CLR1 - Wakeup PM2 source clear Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_RTC_MASK         (0x1U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_RTC_SHIFT        (0U)
+/*! RTC - clear rtc interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_RTC(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_RTC_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_RTC_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT4_MASK    (0x8U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT4_SHIFT   (3U)
+/*! PIN_INT4 - clear PIN_INT4 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT4(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT4_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT4_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT5_MASK    (0x10U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT5_SHIFT   (4U)
+/*! PIN_INT5 - clear PIN_INT5 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT5(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT5_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT5_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT6_MASK    (0x20U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT6_SHIFT   (5U)
+/*! PIN_INT6 - clear PIN_INT6 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT6(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT6_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT6_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT7_MASK    (0x40U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT7_SHIFT   (6U)
+/*! PIN_INT7 - clear PIN_INT7 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT7(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT7_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_PIN_INT7_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_CTIMER2_MASK     (0x80U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_CTIMER2_SHIFT    (7U)
+/*! CTIMER2 - clear CTIMER2 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_CTIMER2(x)       (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_CTIMER2_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_CTIMER2_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_OS_EVENT_TIMER_MASK (0x200U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_OS_EVENT_TIMER_SHIFT (9U)
+/*! OS_EVENT_TIMER - clear OS_EVENT_TIMER interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_OS_EVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_OS_EVENT_TIMER_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_OS_EVENT_TIMER_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_FLEX_SPI_MASK    (0x400U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_FLEX_SPI_SHIFT   (10U)
+/*! FLEX_SPI - clear Flex SPI interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_FLEX_SPI(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_FLEX_SPI_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_FLEX_SPI_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_SDU_MASK         (0x4000U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_SDU_SHIFT        (14U)
+/*! SDU - clear SDU interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_SDU(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_SDU_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_SDU_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTA_MASK  (0x8000U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTA_SHIFT (15U)
+/*! SGPIO_INTA - clear SGPIO_INTA interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTA(x)    (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTA_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTA_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTB_MASK  (0x10000U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTB_SHIFT (16U)
+/*! SGPIO_INTB - clear SGPIO_INTB interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTB(x)    (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTB_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_SGPIO_INTB_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_USB_MASK         (0x40000U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_USB_SHIFT        (18U)
+/*! USB - clear USB interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_USB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_USB_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_USB_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_DMA1_MASK        (0x400000U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_DMA1_SHIFT       (22U)
+/*! DMA1 - clear DMA1 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_DMA1(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_DMA1_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_DMA1_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_PUF_MASK         (0x800000U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_PUF_SHIFT        (23U)
+/*! PUF - clear PUF interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_PUF(x)           (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_PUF_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_PUF_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR1_POWER_QUAD_MASK  (0x1000000U)
+#define PMU_WAKEUP_PM2_SRC_CLR1_POWER_QUAD_SHIFT (24U)
+/*! POWER_QUAD - clear POWER QUAD interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR1_POWER_QUAD(x)    (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR1_POWER_QUAD_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR1_POWER_QUAD_MASK)
+/*! @} */
+
+/*! @name WAKEUP_PM2_SRC_CLR3 - Wakeup PM2 source clear Register */
+/*! @{ */
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPDAC_INT_FUN11_MASK (0x1000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPDAC_INT_FUN11_SHIFT (12U)
+/*! GAU_GPDAC_INT_FUN11 - clear gau_gpdac_int_fun11 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPDAC_INT_FUN11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPDAC_INT_FUN11_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPDAC_INT_FUN11_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_WKUP11_MASK (0x2000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_WKUP11_SHIFT (13U)
+/*! GAU_ACOMP_INT_WKUP11 - clear gau_acomp_int_wkup11 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_WKUP11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_WKUP11_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_WKUP11_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_FUNC11_MASK (0x4000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_FUNC11_SHIFT (14U)
+/*! GAU_ACOMP_INT_FUNC11 - clear gau_acomp_int_func11 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_GAU_ACOMP_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC1_INT_FUNC11_MASK (0x8000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC1_INT_FUNC11_SHIFT (15U)
+/*! GAU_GPADC1_INT_FUNC11 - clear gau_gpadc1_int_func11 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC1_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC1_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC1_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC0_INT_FUNC11_MASK (0x10000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC0_INT_FUNC11_SHIFT (16U)
+/*! GAU_GPADC0_INT_FUNC11 - clear gau_gpadc0_int_func11 interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC0_INT_FUNC11(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC0_INT_FUNC11_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_GAU_GPADC0_INT_FUNC11_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_USIM_MASK        (0x20000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_USIM_SHIFT       (17U)
+/*! USIM - clear usim interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_USIM(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_USIM_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_USIM_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_ENET_MASK        (0x80000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_ENET_SHIFT       (19U)
+/*! ENET - clear enet interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_ENET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_ENET_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_ENET_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_ENET_TIMER_MASK  (0x100000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_ENET_TIMER_SHIFT (20U)
+/*! ENET_TIMER - clear enet_timer interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_ENET_TIMER(x)    (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_ENET_TIMER_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_ENET_TIMER_MASK)
+
+#define PMU_WAKEUP_PM2_SRC_CLR3_ITRC_RST_MASK    (0x800000U)
+#define PMU_WAKEUP_PM2_SRC_CLR3_ITRC_RST_SHIFT   (23U)
+/*! ITRC_RST - clear itrc_rst interrupt request */
+#define PMU_WAKEUP_PM2_SRC_CLR3_ITRC_RST(x)      (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_PM2_SRC_CLR3_ITRC_RST_SHIFT)) & PMU_WAKEUP_PM2_SRC_CLR3_ITRC_RST_MASK)
+/*! @} */
+
+/*! @name SW_CTRL_WL - WL part-SW Control register bypass HW output */
+/*! @{ */
+
+#define PMU_SW_CTRL_WL_WL_EN_MASK                (0x1U)
+#define PMU_SW_CTRL_WL_WL_EN_SHIFT               (0U)
+/*! WL_EN - WL part-SW bypass pmu HW output enable;1:SW mode;0:HW mode */
+#define PMU_SW_CTRL_WL_WL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_WL_WL_EN_SHIFT)) & PMU_SW_CTRL_WL_WL_EN_MASK)
+
+#define PMU_SW_CTRL_WL_MCI_ISO_WL_N_MASK         (0x8U)
+#define PMU_SW_CTRL_WL_MCI_ISO_WL_N_SHIFT        (3U)
+/*! MCI_ISO_WL_N - MCI_ISO_WL_EN_N, 0:iso enable,assert iso before psw off; 1:iso disable,release iso after psw on; */
+#define PMU_SW_CTRL_WL_MCI_ISO_WL_N(x)           (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_WL_MCI_ISO_WL_N_SHIFT)) & PMU_SW_CTRL_WL_MCI_ISO_WL_N_MASK)
+
+#define PMU_SW_CTRL_WL_PSW_WL_PD_MASK            (0x40U)
+#define PMU_SW_CTRL_WL_PSW_WL_PD_SHIFT           (6U)
+/*! PSW_WL_PD - psw_wl, 0:power on, after request buck on,then delay some time to set psw on;
+ *    1:power gated, do it before request buck off
+ */
+#define PMU_SW_CTRL_WL_PSW_WL_PD(x)              (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_WL_PSW_WL_PD_SHIFT)) & PMU_SW_CTRL_WL_PSW_WL_PD_MASK)
+
+#define PMU_SW_CTRL_WL_MCI_WL_PU_RST_MASK        (0x200U)
+#define PMU_SW_CTRL_WL_MCI_WL_PU_RST_SHIFT       (9U)
+/*! MCI_WL_PU_RST - mci_wl_pu_rst, 0:reset release; 1:reset assert */
+#define PMU_SW_CTRL_WL_MCI_WL_PU_RST(x)          (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_WL_MCI_WL_PU_RST_SHIFT)) & PMU_SW_CTRL_WL_MCI_WL_PU_RST_MASK)
+
+#define PMU_SW_CTRL_WL_WL_BUCK_ON_REQ_MASK       (0x800U)
+#define PMU_SW_CTRL_WL_WL_BUCK_ON_REQ_SHIFT      (11U)
+/*! WL_BUCK_ON_REQ - wl request buck on,then need wait 5 fast clk_pmu cycles(about 96ns),do psw on, then iso release */
+#define PMU_SW_CTRL_WL_WL_BUCK_ON_REQ(x)         (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_WL_WL_BUCK_ON_REQ_SHIFT)) & PMU_SW_CTRL_WL_WL_BUCK_ON_REQ_MASK)
+
+#define PMU_SW_CTRL_WL_WL_BUCK_OFF_REQ_MASK      (0x2000U)
+#define PMU_SW_CTRL_WL_WL_BUCK_OFF_REQ_SHIFT     (13U)
+/*! WL_BUCK_OFF_REQ - wl request buck off,need to be cfg after iso en, psw pd */
+#define PMU_SW_CTRL_WL_WL_BUCK_OFF_REQ(x)        (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_WL_WL_BUCK_OFF_REQ_SHIFT)) & PMU_SW_CTRL_WL_WL_BUCK_OFF_REQ_MASK)
+
+#define PMU_SW_CTRL_WL_SET_WL_SLP_MASK           (0x8000U)
+#define PMU_SW_CTRL_WL_SET_WL_SLP_SHIFT          (15U)
+/*! SET_WL_SLP - set_wl_slp,provide another slp way, if you don't want use HW slp signal */
+#define PMU_SW_CTRL_WL_SET_WL_SLP(x)             (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_WL_SET_WL_SLP_SHIFT)) & PMU_SW_CTRL_WL_SET_WL_SLP_MASK)
+/*! @} */
+
+/*! @name SW_CTRL_BLE - BLE part-SW Control register bypass HW output */
+/*! @{ */
+
+#define PMU_SW_CTRL_BLE_BLE_EN_MASK              (0x1U)
+#define PMU_SW_CTRL_BLE_BLE_EN_SHIFT             (0U)
+/*! BLE_EN - BLE part-SW bypass pmu HW output enable;1:SW mode;0:HW mode */
+#define PMU_SW_CTRL_BLE_BLE_EN(x)                (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_BLE_BLE_EN_SHIFT)) & PMU_SW_CTRL_BLE_BLE_EN_MASK)
+
+#define PMU_SW_CTRL_BLE_MCI_ISO_BLE_N_MASK       (0x8U)
+#define PMU_SW_CTRL_BLE_MCI_ISO_BLE_N_SHIFT      (3U)
+/*! MCI_ISO_BLE_N - MCI_ISO_BLE_EN_N, 0:iso enable,assert iso before psw off; 1:iso disable,release iso after psw on; */
+#define PMU_SW_CTRL_BLE_MCI_ISO_BLE_N(x)         (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_BLE_MCI_ISO_BLE_N_SHIFT)) & PMU_SW_CTRL_BLE_MCI_ISO_BLE_N_MASK)
+
+#define PMU_SW_CTRL_BLE_PSW_BLE_PD_MASK          (0x40U)
+#define PMU_SW_CTRL_BLE_PSW_BLE_PD_SHIFT         (6U)
+/*! PSW_BLE_PD - psw_ble, 0:power on, after request buck on,then delay some time to set psw on;
+ *    1:power gated, do it before request buck off
+ */
+#define PMU_SW_CTRL_BLE_PSW_BLE_PD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_BLE_PSW_BLE_PD_SHIFT)) & PMU_SW_CTRL_BLE_PSW_BLE_PD_MASK)
+
+#define PMU_SW_CTRL_BLE_MCI_BLE_PU_RST_MASK      (0x200U)
+#define PMU_SW_CTRL_BLE_MCI_BLE_PU_RST_SHIFT     (9U)
+/*! MCI_BLE_PU_RST - mci_ble_pu_rst, 0:reset release; 1:reset assert */
+#define PMU_SW_CTRL_BLE_MCI_BLE_PU_RST(x)        (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_BLE_MCI_BLE_PU_RST_SHIFT)) & PMU_SW_CTRL_BLE_MCI_BLE_PU_RST_MASK)
+
+#define PMU_SW_CTRL_BLE_BLE_BUCK_ON_REQ_MASK     (0x800U)
+#define PMU_SW_CTRL_BLE_BLE_BUCK_ON_REQ_SHIFT    (11U)
+/*! BLE_BUCK_ON_REQ - ble request buck on,then need wait 5 fast clk_pmu cycles(about 96ns), do psw on, then iso release */
+#define PMU_SW_CTRL_BLE_BLE_BUCK_ON_REQ(x)       (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_BLE_BLE_BUCK_ON_REQ_SHIFT)) & PMU_SW_CTRL_BLE_BLE_BUCK_ON_REQ_MASK)
+
+#define PMU_SW_CTRL_BLE_BLE_BUCK_OFF_REQ_MASK    (0x2000U)
+#define PMU_SW_CTRL_BLE_BLE_BUCK_OFF_REQ_SHIFT   (13U)
+/*! BLE_BUCK_OFF_REQ - ble request buck off,need to be cfg after iso en, psw pd */
+#define PMU_SW_CTRL_BLE_BLE_BUCK_OFF_REQ(x)      (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_BLE_BLE_BUCK_OFF_REQ_SHIFT)) & PMU_SW_CTRL_BLE_BLE_BUCK_OFF_REQ_MASK)
+
+#define PMU_SW_CTRL_BLE_SET_BLE_SLP_MASK         (0x8000U)
+#define PMU_SW_CTRL_BLE_SET_BLE_SLP_SHIFT        (15U)
+/*! SET_BLE_SLP - set_ble_slp,provide another slp way, if you don't want use HW slp signal */
+#define PMU_SW_CTRL_BLE_SET_BLE_SLP(x)           (((uint32_t)(((uint32_t)(x)) << PMU_SW_CTRL_BLE_SET_BLE_SLP_SHIFT)) & PMU_SW_CTRL_BLE_SET_BLE_SLP_MASK)
+/*! @} */
+
+/*! @name PSW18_OTP - PSW18 OTP psw control signal */
+/*! @{ */
+
+#define PMU_PSW18_OTP_CTRL_MASK                  (0x1U)
+#define PMU_PSW18_OTP_CTRL_SHIFT                 (0U)
+/*! CTRL - 0:power on; 1:power down */
+#define PMU_PSW18_OTP_CTRL(x)                    (((uint32_t)(((uint32_t)(x)) << PMU_PSW18_OTP_CTRL_SHIFT)) & PMU_PSW18_OTP_CTRL_MASK)
+/*! @} */
+
+/*! @name TIME_OUT_CTRL - tieme out control signal */
+/*! @{ */
+
+#define PMU_TIME_OUT_CTRL_V11_RDY_NO_TMT_MASK    (0x1U)
+#define PMU_TIME_OUT_CTRL_V11_RDY_NO_TMT_SHIFT   (0U)
+/*! V11_RDY_NO_TMT - v11_rdy use PMIP output/time out generated logic;
+ *  0b0..use time out generated, for external supply
+ *  0b1..use PMIP output signal, for internal supply-BUCK
+ */
+#define PMU_TIME_OUT_CTRL_V11_RDY_NO_TMT(x)      (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CTRL_V11_RDY_NO_TMT_SHIFT)) & PMU_TIME_OUT_CTRL_V11_RDY_NO_TMT_MASK)
+
+#define PMU_TIME_OUT_CTRL_V18_RDY_NO_TMT_MASK    (0x2U)
+#define PMU_TIME_OUT_CTRL_V18_RDY_NO_TMT_SHIFT   (1U)
+/*! V18_RDY_NO_TMT - v18_rdy use PMIP output/time out generated logic;
+ *  0b0..use time out generated, for external supply
+ *  0b1..use PMIP output signal, for internal supply-BUCK
+ */
+#define PMU_TIME_OUT_CTRL_V18_RDY_NO_TMT(x)      (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CTRL_V18_RDY_NO_TMT_SHIFT)) & PMU_TIME_OUT_CTRL_V18_RDY_NO_TMT_MASK)
+
+#define PMU_TIME_OUT_CTRL_PSW_MCI_RDY_NO_TMT_MASK (0x4U)
+#define PMU_TIME_OUT_CTRL_PSW_MCI_RDY_NO_TMT_SHIFT (2U)
+/*! PSW_MCI_RDY_NO_TMT - psw_mci_rdy_n use psw output/time out generated logic;
+ *  0b0..use time out generated
+ *  0b1..use PSW output signal
+ */
+#define PMU_TIME_OUT_CTRL_PSW_MCI_RDY_NO_TMT(x)  (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CTRL_PSW_MCI_RDY_NO_TMT_SHIFT)) & PMU_TIME_OUT_CTRL_PSW_MCI_RDY_NO_TMT_MASK)
+/*! @} */
+
+/*! @name TIME_OUT_CFG_VALUE - tieme out configure value */
+/*! @{ */
+
+#define PMU_TIME_OUT_CFG_VALUE_V11_RDY_ASRT_MASK (0x1FU)
+#define PMU_TIME_OUT_CFG_VALUE_V11_RDY_ASRT_SHIFT (0U)
+/*! V11_RDY_ASRT - the time from buck11 on to v11_rdy assert, suggest use the max value 5'h1f */
+#define PMU_TIME_OUT_CFG_VALUE_V11_RDY_ASRT(x)   (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CFG_VALUE_V11_RDY_ASRT_SHIFT)) & PMU_TIME_OUT_CFG_VALUE_V11_RDY_ASRT_MASK)
+
+#define PMU_TIME_OUT_CFG_VALUE_V11_RDY_DE_ASRT_MASK (0x3E0U)
+#define PMU_TIME_OUT_CFG_VALUE_V11_RDY_DE_ASRT_SHIFT (5U)
+/*! V11_RDY_DE_ASRT - the time from buck11 off to v11_rdy de-assert, suggest use the max value 5'h1f */
+#define PMU_TIME_OUT_CFG_VALUE_V11_RDY_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CFG_VALUE_V11_RDY_DE_ASRT_SHIFT)) & PMU_TIME_OUT_CFG_VALUE_V11_RDY_DE_ASRT_MASK)
+
+#define PMU_TIME_OUT_CFG_VALUE_V18_RDY_ASRT_MASK (0x7C00U)
+#define PMU_TIME_OUT_CFG_VALUE_V18_RDY_ASRT_SHIFT (10U)
+/*! V18_RDY_ASRT - the time from buck18 on to v18_rdy assert, suggest use the max value 5'h1f */
+#define PMU_TIME_OUT_CFG_VALUE_V18_RDY_ASRT(x)   (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CFG_VALUE_V18_RDY_ASRT_SHIFT)) & PMU_TIME_OUT_CFG_VALUE_V18_RDY_ASRT_MASK)
+
+#define PMU_TIME_OUT_CFG_VALUE_V18_RDY_DE_ASRT_MASK (0xF8000U)
+#define PMU_TIME_OUT_CFG_VALUE_V18_RDY_DE_ASRT_SHIFT (15U)
+/*! V18_RDY_DE_ASRT - the time from buck18 off to v18_rdy de-assert, suggest use the max value 5'h1f */
+#define PMU_TIME_OUT_CFG_VALUE_V18_RDY_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CFG_VALUE_V18_RDY_DE_ASRT_SHIFT)) & PMU_TIME_OUT_CFG_VALUE_V18_RDY_DE_ASRT_MASK)
+
+#define PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_ASRT_MASK (0x1F00000U)
+#define PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_ASRT_SHIFT (20U)
+/*! PSW_MCI_RDY_ASRT - the time from psw_mci on to psw_mci_rdy assert */
+#define PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_ASRT(x) (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_ASRT_SHIFT)) & PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_ASRT_MASK)
+
+#define PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_DE_ASRT_MASK (0x3E000000U)
+#define PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_DE_ASRT_SHIFT (25U)
+/*! PSW_MCI_RDY_DE_ASRT - the time from psw_mci off to psw_mci_rdy de-assert */
+#define PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_DE_ASRT_SHIFT)) & PMU_TIME_OUT_CFG_VALUE_PSW_MCI_RDY_DE_ASRT_MASK)
+/*! @} */
+
+/*! @name RESERVE_REG0 - reserve R/W regs */
+/*! @{ */
+
+#define PMU_RESERVE_REG0_VALUE_MASK              (0xFFFFFFFFU)
+#define PMU_RESERVE_REG0_VALUE_SHIFT             (0U)
+/*! VALUE - reserve R/W regs */
+#define PMU_RESERVE_REG0_VALUE(x)                (((uint32_t)(((uint32_t)(x)) << PMU_RESERVE_REG0_VALUE_SHIFT)) & PMU_RESERVE_REG0_VALUE_MASK)
+/*! @} */
+
+/*! @name RESERVE_REG1 - reserve Read only regs */
+/*! @{ */
+
+#define PMU_RESERVE_REG1_VALUE_MASK              (0xFFFFFFFFU)
+#define PMU_RESERVE_REG1_VALUE_SHIFT             (0U)
+/*! VALUE - reserve Read only regs */
+#define PMU_RESERVE_REG1_VALUE(x)                (((uint32_t)(((uint32_t)(x)) << PMU_RESERVE_REG1_VALUE_SHIFT)) & PMU_RESERVE_REG1_VALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PMU_Register_Masks */
+
+
+/* PMU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral PMU base address */
+  #define PMU_BASE                                 (0x50031000u)
+  /** Peripheral PMU base address */
+  #define PMU_BASE_NS                              (0x40031000u)
+  /** Peripheral PMU base pointer */
+  #define PMU                                      ((PMU_Type *)PMU_BASE)
+  /** Peripheral PMU base pointer */
+  #define PMU_NS                                   ((PMU_Type *)PMU_BASE_NS)
+  /** Array initializer of PMU peripheral base addresses */
+  #define PMU_BASE_ADDRS                           { PMU_BASE }
+  /** Array initializer of PMU peripheral base pointers */
+  #define PMU_BASE_PTRS                            { PMU }
+  /** Array initializer of PMU peripheral base addresses */
+  #define PMU_BASE_ADDRS_NS                        { PMU_BASE_NS }
+  /** Array initializer of PMU peripheral base pointers */
+  #define PMU_BASE_PTRS_NS                         { PMU_NS }
+#else
+  /** Peripheral PMU base address */
+  #define PMU_BASE                                 (0x40031000u)
+  /** Peripheral PMU base pointer */
+  #define PMU                                      ((PMU_Type *)PMU_BASE)
+  /** Array initializer of PMU peripheral base addresses */
+  #define PMU_BASE_ADDRS                           { PMU_BASE }
+  /** Array initializer of PMU peripheral base pointers */
+  #define PMU_BASE_PTRS                            { PMU }
+#endif
+
+/*!
+ * @}
+ */ /* end of group PMU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- POWERQUAD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer
+ * @{
+ */
+
+/** POWERQUAD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t OUTBASE;                           /**< Base address register for output region, offset: 0x0 */
+  __IO uint32_t OUTFORMAT;                         /**< Output format, offset: 0x4 */
+  __IO uint32_t TMPBASE;                           /**< Base address register for temp region, offset: 0x8 */
+  __IO uint32_t TMPFORMAT;                         /**< Temp format, offset: 0xC */
+  __IO uint32_t INABASE;                           /**< Base address register for input A region, offset: 0x10 */
+  __IO uint32_t INAFORMAT;                         /**< Input A format, offset: 0x14 */
+  __IO uint32_t INBBASE;                           /**< Base address register for input B region, offset: 0x18 */
+  __IO uint32_t INBFORMAT;                         /**< Input B format, offset: 0x1C */
+       uint8_t RESERVED_0[224];
+  __IO uint32_t CONTROL;                           /**< PowerQuad Control register, offset: 0x100 */
+  __IO uint32_t LENGTH;                            /**< Length register, offset: 0x104 */
+  __IO uint32_t CPPRE;                             /**< Pre-scale register, offset: 0x108 */
+  __IO uint32_t MISC;                              /**< Misc register, offset: 0x10C */
+  __IO uint32_t CURSORY;                           /**< Cursory register, offset: 0x110 */
+       uint8_t RESERVED_1[108];
+  __IO uint32_t CORDIC_X;                          /**< Cordic input X register, offset: 0x180 */
+  __IO uint32_t CORDIC_Y;                          /**< Cordic input Y register, offset: 0x184 */
+  __IO uint32_t CORDIC_Z;                          /**< Cordic input Z register, offset: 0x188 */
+  __IO uint32_t ERRSTAT;                           /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */
+  __IO uint32_t INTREN;                            /**< INTERRUPT enable register, offset: 0x190 */
+  __IO uint32_t EVENTEN;                           /**< Event Enable register, offset: 0x194 */
+  __IO uint32_t INTRSTAT;                          /**< INTERRUPT STATUS register, offset: 0x198 */
+       uint8_t RESERVED_2[100];
+  __IO uint32_t GPREG[16];                         /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */
+  __IO uint32_t COMPREG[8];                        /**< Compute register bank, array offset: 0x240, array step: 0x4 */
+} POWERQUAD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- POWERQUAD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks
+ * @{
+ */
+
+/*! @name OUTBASE - Base address register for output region */
+/*! @{ */
+
+#define POWERQUAD_OUTBASE_OUTBASE_MASK           (0xFFFFFFFFU)
+#define POWERQUAD_OUTBASE_OUTBASE_SHIFT          (0U)
+/*! OUTBASE - Base address register for the output region */
+#define POWERQUAD_OUTBASE_OUTBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
+/*! @} */
+
+/*! @name OUTFORMAT - Output format */
+/*! @{ */
+
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK   (0x3U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT  (0U)
+/*! OUT_FORMATINT - Output Internal format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)
+
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK   (0x30U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT  (4U)
+/*! OUT_FORMATEXT - Output External format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)
+
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK      (0xFF00U)
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT     (8U)
+/*! OUT_SCALER - Output Scaler value (for scaled 'q31' formats) */
+#define POWERQUAD_OUTFORMAT_OUT_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
+/*! @} */
+
+/*! @name TMPBASE - Base address register for temp region */
+/*! @{ */
+
+#define POWERQUAD_TMPBASE_TMPBASE_MASK           (0xFFFFFFFFU)
+#define POWERQUAD_TMPBASE_TMPBASE_SHIFT          (0U)
+/*! TMPBASE - Base address register for the temporary region */
+#define POWERQUAD_TMPBASE_TMPBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
+/*! @} */
+
+/*! @name TMPFORMAT - Temp format */
+/*! @{ */
+
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK   (0x3U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT  (0U)
+/*! TMP_FORMATINT - Temp Internal format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)
+
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK   (0x30U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT  (4U)
+/*! TMP_FORMATEXT - Temp External format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)
+
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK      (0xFF00U)
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT     (8U)
+/*! TMP_SCALER - Temp Scaler value (for scaled 'q31' formats) */
+#define POWERQUAD_TMPFORMAT_TMP_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
+/*! @} */
+
+/*! @name INABASE - Base address register for input A region */
+/*! @{ */
+
+#define POWERQUAD_INABASE_INABASE_MASK           (0xFFFFFFFFU)
+#define POWERQUAD_INABASE_INABASE_SHIFT          (0U)
+/*! INABASE - Base address register for the input A region */
+#define POWERQUAD_INABASE_INABASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
+/*! @} */
+
+/*! @name INAFORMAT - Input A format */
+/*! @{ */
+
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK   (0x3U)
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT  (0U)
+/*! INA_FORMATINT - Input A Internal format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_INAFORMAT_INA_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)
+
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK   (0x30U)
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT  (4U)
+/*! INA_FORMATEXT - Input A External format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)
+
+#define POWERQUAD_INAFORMAT_INA_SCALER_MASK      (0xFF00U)
+#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT     (8U)
+/*! INA_SCALER - Input A Scaler value (for scaled 'q31' formats) */
+#define POWERQUAD_INAFORMAT_INA_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
+/*! @} */
+
+/*! @name INBBASE - Base address register for input B region */
+/*! @{ */
+
+#define POWERQUAD_INBBASE_INBBASE_MASK           (0xFFFFFFFFU)
+#define POWERQUAD_INBBASE_INBBASE_SHIFT          (0U)
+/*! INBBASE - Base address register for the input B region */
+#define POWERQUAD_INBBASE_INBBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
+/*! @} */
+
+/*! @name INBFORMAT - Input B format */
+/*! @{ */
+
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK   (0x3U)
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT  (0U)
+/*! INB_FORMATINT - Input B Internal format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_INBFORMAT_INB_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)
+
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK   (0x30U)
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT  (4U)
+/*! INB_FORMATEXT - Input B External format (00: q15; 01:q31; 10:float) */
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)
+
+#define POWERQUAD_INBFORMAT_INB_SCALER_MASK      (0xFF00U)
+#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT     (8U)
+/*! INB_SCALER - Input B Scaler value (for scaled 'q31' formats) */
+#define POWERQUAD_INBFORMAT_INB_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
+/*! @} */
+
+/*! @name CONTROL - PowerQuad Control register */
+/*! @{ */
+
+#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK     (0xFU)
+#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT    (0U)
+/*! DECODE_OPCODE - opcode specific to decode_machine */
+#define POWERQUAD_CONTROL_DECODE_OPCODE(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)
+
+#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK    (0xF0U)
+#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT   (4U)
+/*! DECODE_MACHINE - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA */
+#define POWERQUAD_CONTROL_DECODE_MACHINE(x)      (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)
+
+#define POWERQUAD_CONTROL_INST_BUSY_MASK         (0x80000000U)
+#define POWERQUAD_CONTROL_INST_BUSY_SHIFT        (31U)
+/*! INST_BUSY - Instruction busy signal when high indicates processing is on */
+#define POWERQUAD_CONTROL_INST_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
+/*! @} */
+
+/*! @name LENGTH - Length register */
+/*! @{ */
+
+#define POWERQUAD_LENGTH_INST_LENGTH_MASK        (0xFFFFFFFFU)
+#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT       (0U)
+/*! INST_LENGTH - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength =
+ *    inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b =
+ *    inst_length[20:16]
+ */
+#define POWERQUAD_LENGTH_INST_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
+/*! @} */
+
+/*! @name CPPRE - Pre-scale register */
+/*! @{ */
+
+#define POWERQUAD_CPPRE_CPPRE_IN_MASK            (0xFFU)
+#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT           (0U)
+/*! CPPRE_IN - co-processor scaling of input */
+#define POWERQUAD_CPPRE_CPPRE_IN(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)
+
+#define POWERQUAD_CPPRE_CPPRE_OUT_MASK           (0xFF00U)
+#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT          (8U)
+/*! CPPRE_OUT - co-processor fixed point output */
+#define POWERQUAD_CPPRE_CPPRE_OUT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)
+
+#define POWERQUAD_CPPRE_CPPRE_SAT_MASK           (0x10000U)
+#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT          (16U)
+/*! CPPRE_SAT - 1 : forces sub-32 bit saturation */
+#define POWERQUAD_CPPRE_CPPRE_SAT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)
+
+#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK          (0x20000U)
+#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT         (17U)
+/*! CPPRE_SAT8 - 0 = 8bits, 1 = 16bits */
+#define POWERQUAD_CPPRE_CPPRE_SAT8(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
+/*! @} */
+
+/*! @name MISC - Misc register */
+/*! @{ */
+
+#define POWERQUAD_MISC_INST_MISC_MASK            (0xFFFFFFFFU)
+#define POWERQUAD_MISC_INST_MISC_SHIFT           (0U)
+/*! INST_MISC - Misc register. For Matrix : Used for scale factor */
+#define POWERQUAD_MISC_INST_MISC(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
+/*! @} */
+
+/*! @name CURSORY - Cursory register */
+/*! @{ */
+
+#define POWERQUAD_CURSORY_CURSORY_MASK           (0x1U)
+#define POWERQUAD_CURSORY_CURSORY_SHIFT          (0U)
+/*! CURSORY - 1 : Enable cursory mode */
+#define POWERQUAD_CURSORY_CURSORY(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
+/*! @} */
+
+/*! @name CORDIC_X - Cordic input X register */
+/*! @{ */
+
+#define POWERQUAD_CORDIC_X_CORDIC_X_MASK         (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT        (0U)
+/*! CORDIC_X - Cordic input x */
+#define POWERQUAD_CORDIC_X_CORDIC_X(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
+/*! @} */
+
+/*! @name CORDIC_Y - Cordic input Y register */
+/*! @{ */
+
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK         (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT        (0U)
+/*! CORDIC_Y - Cordic input y */
+#define POWERQUAD_CORDIC_Y_CORDIC_Y(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
+/*! @} */
+
+/*! @name CORDIC_Z - Cordic input Z register */
+/*! @{ */
+
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK         (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT        (0U)
+/*! CORDIC_Z - Cordic input z */
+#define POWERQUAD_CORDIC_Z_CORDIC_Z(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
+/*! @} */
+
+/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */
+/*! @{ */
+
+#define POWERQUAD_ERRSTAT_OVERFLOW_MASK          (0x1U)
+#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT         (0U)
+/*! OVERFLOW - overflow */
+#define POWERQUAD_ERRSTAT_OVERFLOW(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)
+
+#define POWERQUAD_ERRSTAT_NAN_MASK               (0x2U)
+#define POWERQUAD_ERRSTAT_NAN_SHIFT              (1U)
+/*! NAN - nan */
+#define POWERQUAD_ERRSTAT_NAN(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)
+
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK     (0x4U)
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT    (2U)
+/*! FIXEDOVERFLOW - fixed_pt_overflow */
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)
+
+#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK         (0x8U)
+#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT        (3U)
+/*! UNDERFLOW - underflow */
+#define POWERQUAD_ERRSTAT_UNDERFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)
+
+#define POWERQUAD_ERRSTAT_BUSERROR_MASK          (0x10U)
+#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT         (4U)
+/*! BUSERROR - bus_error */
+#define POWERQUAD_ERRSTAT_BUSERROR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
+/*! @} */
+
+/*! @name INTREN - INTERRUPT enable register */
+/*! @{ */
+
+#define POWERQUAD_INTREN_INTR_OFLOW_MASK         (0x1U)
+#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT        (0U)
+/*! INTR_OFLOW - 1 : Enable interrupt on Floating point overflow */
+#define POWERQUAD_INTREN_INTR_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)
+
+#define POWERQUAD_INTREN_INTR_NAN_MASK           (0x2U)
+#define POWERQUAD_INTREN_INTR_NAN_SHIFT          (1U)
+/*! INTR_NAN - 1 : Enable interrupt on Floating point NaN */
+#define POWERQUAD_INTREN_INTR_NAN(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)
+
+#define POWERQUAD_INTREN_INTR_FIXED_MASK         (0x4U)
+#define POWERQUAD_INTREN_INTR_FIXED_SHIFT        (2U)
+/*! INTR_FIXED - 1: Enable interrupt on Fixed point Overflow */
+#define POWERQUAD_INTREN_INTR_FIXED(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)
+
+#define POWERQUAD_INTREN_INTR_UFLOW_MASK         (0x8U)
+#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT        (3U)
+/*! INTR_UFLOW - 1 : Enable interrupt on Subnormal truncation */
+#define POWERQUAD_INTREN_INTR_UFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)
+
+#define POWERQUAD_INTREN_INTR_BERR_MASK          (0x10U)
+#define POWERQUAD_INTREN_INTR_BERR_SHIFT         (4U)
+/*! INTR_BERR - 1: Enable interrupt on AHBM Buss Error */
+#define POWERQUAD_INTREN_INTR_BERR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)
+
+#define POWERQUAD_INTREN_INTR_COMP_MASK          (0x80U)
+#define POWERQUAD_INTREN_INTR_COMP_SHIFT         (7U)
+/*! INTR_COMP - 1: Enable interrupt on instruction completion */
+#define POWERQUAD_INTREN_INTR_COMP(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
+/*! @} */
+
+/*! @name EVENTEN - Event Enable register */
+/*! @{ */
+
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK       (0x1U)
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT      (0U)
+/*! EVENT_OFLOW - 1 : Enable event trigger on Floating point overflow */
+#define POWERQUAD_EVENTEN_EVENT_OFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_NAN_MASK         (0x2U)
+#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT        (1U)
+/*! EVENT_NAN - 1 : Enable event trigger on Floating point NaN */
+#define POWERQUAD_EVENTEN_EVENT_NAN(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK       (0x4U)
+#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT      (2U)
+/*! EVENT_FIXED - 1: Enable event trigger on Fixed point Overflow */
+#define POWERQUAD_EVENTEN_EVENT_FIXED(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK       (0x8U)
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT      (3U)
+/*! EVENT_UFLOW - 1 : Enable event trigger on Subnormal truncation */
+#define POWERQUAD_EVENTEN_EVENT_UFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_BERR_MASK        (0x10U)
+#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT       (4U)
+/*! EVENT_BERR - 1: Enable event trigger on AHBM Buss Error */
+#define POWERQUAD_EVENTEN_EVENT_BERR(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_COMP_MASK        (0x80U)
+#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT       (7U)
+/*! EVENT_COMP - 1: Enable event trigger on instruction completion */
+#define POWERQUAD_EVENTEN_EVENT_COMP(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
+/*! @} */
+
+/*! @name INTRSTAT - INTERRUPT STATUS register */
+/*! @{ */
+
+#define POWERQUAD_INTRSTAT_INTR_STAT_MASK        (0x1U)
+#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT       (0U)
+/*! INTR_STAT - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit */
+#define POWERQUAD_INTRSTAT_INTR_STAT(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
+/*! @} */
+
+/*! @name GPREG - General purpose register bank N. */
+/*! @{ */
+
+#define POWERQUAD_GPREG_GPREG_MASK               (0xFFFFFFFFU)
+#define POWERQUAD_GPREG_GPREG_SHIFT              (0U)
+/*! GPREG - General purpose register bank */
+#define POWERQUAD_GPREG_GPREG(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
+/*! @} */
+
+/* The count of POWERQUAD_GPREG */
+#define POWERQUAD_GPREG_COUNT                    (16U)
+
+/*! @name COMPREGS_COMPREG - Compute register bank */
+/*! @{ */
+
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK  (0xFFFFFFFFU)
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
+/*! COMPREG - Compute register bank */
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x)    (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
+/*! @} */
+
+/* The count of POWERQUAD_COMPREGS_COMPREG */
+#define POWERQUAD_COMPREGS_COMPREG_COUNT         (8U)
+
+
+/*!
+ * @}
+ */ /* end of group POWERQUAD_Register_Masks */
+
+
+/* POWERQUAD - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral POWERQUAD base address */
+  #define POWERQUAD_BASE                           (0x50150000u)
+  /** Peripheral POWERQUAD base address */
+  #define POWERQUAD_BASE_NS                        (0x40150000u)
+  /** Peripheral POWERQUAD base pointer */
+  #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
+  /** Peripheral POWERQUAD base pointer */
+  #define POWERQUAD_NS                             ((POWERQUAD_Type *)POWERQUAD_BASE_NS)
+  /** Array initializer of POWERQUAD peripheral base addresses */
+  #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
+  /** Array initializer of POWERQUAD peripheral base pointers */
+  #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
+  /** Array initializer of POWERQUAD peripheral base addresses */
+  #define POWERQUAD_BASE_ADDRS_NS                  { POWERQUAD_BASE_NS }
+  /** Array initializer of POWERQUAD peripheral base pointers */
+  #define POWERQUAD_BASE_PTRS_NS                   { POWERQUAD_NS }
+#else
+  /** Peripheral POWERQUAD base address */
+  #define POWERQUAD_BASE                           (0x40150000u)
+  /** Peripheral POWERQUAD base pointer */
+  #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
+  /** Array initializer of POWERQUAD peripheral base addresses */
+  #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
+  /** Array initializer of POWERQUAD peripheral base pointers */
+  #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
+#endif
+/** Interrupt vectors for the POWERQUAD peripheral type */
+#define POWERQUAD_IRQS                           { POWERQUAD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group POWERQUAD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PUF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
+ * @{
+ */
+
+/** PUF - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< Mode register, offset: 0x0 */
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+  __I  uint32_t VERSION;                           /**< Version register, offset: 0xC */
+  __IO uint32_t CKSUM;                             /**< Checksum register, offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t PARITY_0;                          /**< Parity register, offset: 0x20 */
+  __IO uint32_t PARITY_1;                          /**< Parity register, offset: 0x24 */
+  __IO uint32_t PARITY_2;                          /**< Parity register, offset: 0x28 */
+       uint8_t RESERVED_1[20];
+  __IO uint32_t IGNORE;                            /**< Ignore register, offset: 0x40 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t RNG;                               /**< Random Number register, offset: 0x50 */
+       uint8_t RESERVED_3[12];
+  __I  uint32_t KEY_0;                             /**< Key register, offset: 0x60 */
+  __I  uint32_t KEY_1;                             /**< Key register, offset: 0x64 */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t LOCK;                              /**< Lock register, offset: 0x70 */
+  __I  uint32_t RO_FREQ;                           /**< RO Frequency register, offset: 0x74 */
+  __I  uint32_t SLW_RO;                            /**< Slow RO register, offset: 0x78 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t EVAL_SEL;                          /**< Evaluation Select register, offset: 0x80 */
+  __I  uint32_t EVAL_VAL;                          /**< Evaluation Value register, offset: 0x84 */
+  __I  uint32_t EVAL_RAW;                          /**< Evaluation Raw register, offset: 0x88 */
+  __I  uint32_t EVAL_BCH;                          /**< Evaluation BCH register, offset: 0x8C */
+  __I  uint32_t EVAL_ERR_LOC_0_1;                  /**< Error Location register, offset: 0x90 */
+  __I  uint32_t EVAL_ERR_LOC_2_3;                  /**< Error Location register, offset: 0x94 */
+  __I  uint32_t EVAL_ERR_LOC_4_5;                  /**< Error Location register, offset: 0x98 */
+  __I  uint32_t EVAL_ERR_LOC_6_7;                  /**< Error Location register, offset: 0x9C */
+  __I  uint32_t EVAL_ERR_LOC_8_9;                  /**< Error Location register, offset: 0xA0 */
+       uint8_t RESERVED_6[76];
+  __I  uint32_t EVAL_RND_KEY_0;                    /**< Evaluation Round Key register, offset: 0xF0 */
+  __I  uint32_t EVAL_RND_KEY_1;                    /**< Evaluation Round Key register, offset: 0xF4 */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t EVAL_CTRL;                         /**< Evaluation Control register, offset: 0xFC */
+       uint8_t RESERVED_8[3776];
+  __I  uint32_t ACCESS_ERR;                        /**< Access Error register, offset: 0xFC0 */
+  __IO uint32_t ACCESS_ERR_CLR;                    /**< Access Error Clear register, offset: 0xFC4 */
+       uint8_t RESERVED_9[24];
+  __I  uint32_t INT_STATUS;                        /**< Interrupt Status register, offset: 0xFE0 */
+  __IO uint32_t INT_ENABLE;                        /**< Interrupt Enable register, offset: 0xFE4 */
+  __IO uint32_t INT_STATUS_CLR;                    /**< Interrupt Status Clear register, offset: 0xFE8 */
+  __IO uint32_t INT_STATUS_SET;                    /**< Interrupt Status Set register, offset: 0xFEC */
+       uint8_t RESERVED_10[12];
+  __I  uint32_t MODULE_ID;                         /**< Module ID register, offset: 0xFFC */
+} PUF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PUF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PUF_Register_Masks PUF Register Masks
+ * @{
+ */
+
+/*! @name MODE - Mode register */
+/*! @{ */
+
+#define PUF_MODE_START_MASK                      (0x1U)
+#define PUF_MODE_START_SHIFT                     (0U)
+/*! START - Start */
+#define PUF_MODE_START(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_MODE_START_SHIFT)) & PUF_MODE_START_MASK)
+
+#define PUF_MODE_ENROLL_MASK                     (0x2U)
+#define PUF_MODE_ENROLL_SHIFT                    (1U)
+/*! ENROLL - Enrollment; 1'b0 - Reconstruction; 1'b1 - Enrollment */
+#define PUF_MODE_ENROLL(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_MODE_ENROLL_SHIFT)) & PUF_MODE_ENROLL_MASK)
+
+#define PUF_MODE_MODE_RSVD_3_MASK                (0xCU)
+#define PUF_MODE_MODE_RSVD_3_SHIFT               (2U)
+/*! MODE_RSVD_3 - Reserved */
+#define PUF_MODE_MODE_RSVD_3(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_MODE_MODE_RSVD_3_SHIFT)) & PUF_MODE_MODE_RSVD_3_MASK)
+
+#define PUF_MODE_SLW_LMT_MASK                    (0xF0U)
+#define PUF_MODE_SLW_LMT_SHIFT                   (4U)
+/*! SLW_LMT - Power of 2 count limit for slow limit */
+#define PUF_MODE_SLW_LMT(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_MODE_SLW_LMT_SHIFT)) & PUF_MODE_SLW_LMT_MASK)
+
+#define PUF_MODE_MODE_RSVD_2_MASK                (0xF00U)
+#define PUF_MODE_MODE_RSVD_2_SHIFT               (8U)
+/*! MODE_RSVD_2 - Reserved */
+#define PUF_MODE_MODE_RSVD_2(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_MODE_MODE_RSVD_2_SHIFT)) & PUF_MODE_MODE_RSVD_2_MASK)
+
+#define PUF_MODE_WRM_LMT_MASK                    (0xF000U)
+#define PUF_MODE_WRM_LMT_SHIFT                   (12U)
+/*! WRM_LMT - Power of 2 count limit for warmup */
+#define PUF_MODE_WRM_LMT(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_MODE_WRM_LMT_SHIFT)) & PUF_MODE_WRM_LMT_MASK)
+
+#define PUF_MODE_MODE_RSVD_1_MASK                (0xF0000U)
+#define PUF_MODE_MODE_RSVD_1_SHIFT               (16U)
+/*! MODE_RSVD_1 - Reserved */
+#define PUF_MODE_MODE_RSVD_1(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_MODE_MODE_RSVD_1_SHIFT)) & PUF_MODE_MODE_RSVD_1_MASK)
+
+#define PUF_MODE_REC_LMT_MASK                    (0xF00000U)
+#define PUF_MODE_REC_LMT_SHIFT                   (20U)
+/*! REC_LMT - Power of 2 count limit for reconstruction */
+#define PUF_MODE_REC_LMT(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_MODE_REC_LMT_SHIFT)) & PUF_MODE_REC_LMT_MASK)
+
+#define PUF_MODE_MODE_RSVD_0_MASK                (0xF000000U)
+#define PUF_MODE_MODE_RSVD_0_SHIFT               (24U)
+/*! MODE_RSVD_0 - Reserved */
+#define PUF_MODE_MODE_RSVD_0(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_MODE_MODE_RSVD_0_SHIFT)) & PUF_MODE_MODE_RSVD_0_MASK)
+
+#define PUF_MODE_ENR_LMT_MASK                    (0xF0000000U)
+#define PUF_MODE_ENR_LMT_SHIFT                   (28U)
+/*! ENR_LMT - Power of 2 count limit for enrollment */
+#define PUF_MODE_ENR_LMT(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_MODE_ENR_LMT_SHIFT)) & PUF_MODE_ENR_LMT_MASK)
+/*! @} */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+
+#define PUF_CTRL_GEN_KEY_MASK                    (0x1U)
+#define PUF_CTRL_GEN_KEY_SHIFT                   (0U)
+/*! GEN_KEY - Generate Next Key; Request another key of a different KEY_ID */
+#define PUF_CTRL_GEN_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GEN_KEY_SHIFT)) & PUF_CTRL_GEN_KEY_MASK)
+
+#define PUF_CTRL_NEXT_CHUNK_MASK                 (0x2U)
+#define PUF_CTRL_NEXT_CHUNK_SHIFT                (1U)
+/*! NEXT_CHUNK - Next Key Chunk; Request next chunk of key with current key ID */
+#define PUF_CTRL_NEXT_CHUNK(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_NEXT_CHUNK_SHIFT)) & PUF_CTRL_NEXT_CHUNK_MASK)
+
+#define PUF_CTRL_CTRL_RSVD_1_MASK                (0xCU)
+#define PUF_CTRL_CTRL_RSVD_1_SHIFT               (2U)
+/*! CTRL_RSVD_1 - Reserved */
+#define PUF_CTRL_CTRL_RSVD_1(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CTRL_RSVD_1_SHIFT)) & PUF_CTRL_CTRL_RSVD_1_MASK)
+
+#define PUF_CTRL_KEY_ID_MASK                     (0xF0U)
+#define PUF_CTRL_KEY_ID_SHIFT                    (4U)
+/*! KEY_ID - Key ID; Upper nibble of the key generation seed. */
+#define PUF_CTRL_KEY_ID(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_KEY_ID_SHIFT)) & PUF_CTRL_KEY_ID_MASK)
+
+#define PUF_CTRL_CTRL_RSVD_0_MASK                (0x7FFFFF00U)
+#define PUF_CTRL_CTRL_RSVD_0_SHIFT               (8U)
+/*! CTRL_RSVD_0 - Reserved */
+#define PUF_CTRL_CTRL_RSVD_0(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CTRL_RSVD_0_SHIFT)) & PUF_CTRL_CTRL_RSVD_0_MASK)
+
+#define PUF_CTRL_PUF_RST_MASK                    (0x80000000U)
+#define PUF_CTRL_PUF_RST_SHIFT                   (31U)
+/*! PUF_RST - Synchronous Reset */
+#define PUF_CTRL_PUF_RST(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_PUF_RST_SHIFT)) & PUF_CTRL_PUF_RST_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+
+#define PUF_STATUS_BUSY_MASK                     (0x1U)
+#define PUF_STATUS_BUSY_SHIFT                    (0U)
+/*! BUSY - PUF is busy */
+#define PUF_STATUS_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_STATUS_BUSY_SHIFT)) & PUF_STATUS_BUSY_MASK)
+
+#define PUF_STATUS_STATUS_RSVD_1_MASK            (0xFFFFFEU)
+#define PUF_STATUS_STATUS_RSVD_1_SHIFT           (1U)
+/*! STATUS_RSVD_1 - Reserved */
+#define PUF_STATUS_STATUS_RSVD_1(x)              (((uint32_t)(((uint32_t)(x)) << PUF_STATUS_STATUS_RSVD_1_SHIFT)) & PUF_STATUS_STATUS_RSVD_1_MASK)
+
+#define PUF_STATUS_ERROR_MASK                    (0xF000000U)
+#define PUF_STATUS_ERROR_SHIFT                   (24U)
+/*! ERROR - Error Code; 4'b0001 - Checksum mismatch; 4'b0010 - Chunk overflow, next chunk invalid;
+ *    4'b0011 - Key ID requested is locked; 4'b0100 - Invalid counter limit; 4'b0101 -
+ *    Enroll/reconstruction is locked; 4'b0110 - Next chunk requested before key requested; 4'b0111 - Invalid lock
+ *    code
+ */
+#define PUF_STATUS_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_STATUS_ERROR_SHIFT)) & PUF_STATUS_ERROR_MASK)
+
+#define PUF_STATUS_STATUS_RSVD_0_MASK            (0xF0000000U)
+#define PUF_STATUS_STATUS_RSVD_0_SHIFT           (28U)
+/*! STATUS_RSVD_0 - Reserved */
+#define PUF_STATUS_STATUS_RSVD_0(x)              (((uint32_t)(((uint32_t)(x)) << PUF_STATUS_STATUS_RSVD_0_SHIFT)) & PUF_STATUS_STATUS_RSVD_0_MASK)
+/*! @} */
+
+/*! @name VERSION - Version register */
+/*! @{ */
+
+#define PUF_VERSION_ENTROPY_MASK                 (0xFFU)
+#define PUF_VERSION_ENTROPY_SHIFT                (0U)
+/*! ENTROPY - Entropy Divided by Four */
+#define PUF_VERSION_ENTROPY(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_ENTROPY_SHIFT)) & PUF_VERSION_ENTROPY_MASK)
+
+#define PUF_VERSION_NUM_RO_GRP_MASK              (0xFF00U)
+#define PUF_VERSION_NUM_RO_GRP_SHIFT             (8U)
+/*! NUM_RO_GRP - Number of RO Groups */
+#define PUF_VERSION_NUM_RO_GRP(x)                (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_NUM_RO_GRP_SHIFT)) & PUF_VERSION_NUM_RO_GRP_MASK)
+
+#define PUF_VERSION_MIN_VER_MASK                 (0xFF0000U)
+#define PUF_VERSION_MIN_VER_SHIFT                (16U)
+/*! MIN_VER - Minor Version */
+#define PUF_VERSION_MIN_VER(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_MIN_VER_SHIFT)) & PUF_VERSION_MIN_VER_MASK)
+
+#define PUF_VERSION_MAJ_VER_MASK                 (0xFF000000U)
+#define PUF_VERSION_MAJ_VER_SHIFT                (24U)
+/*! MAJ_VER - Major Version */
+#define PUF_VERSION_MAJ_VER(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_MAJ_VER_SHIFT)) & PUF_VERSION_MAJ_VER_MASK)
+/*! @} */
+
+/*! @name CKSUM - Checksum register */
+/*! @{ */
+
+#define PUF_CKSUM_CKSUM_MASK                     (0xFFFFFFFFU)
+#define PUF_CKSUM_CKSUM_SHIFT                    (0U)
+/*! CKSUM - Checksum; Enrollment: read after operation to store computed checksum; Reconstruction:
+ *    rxpected checksum to compare written before operation
+ */
+#define PUF_CKSUM_CKSUM(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CKSUM_CKSUM_SHIFT)) & PUF_CKSUM_CKSUM_MASK)
+/*! @} */
+
+/*! @name PARITY_0 - Parity register */
+/*! @{ */
+
+#define PUF_PARITY_0_PARITY_0_MASK               (0xFFFFFFFFU)
+#define PUF_PARITY_0_PARITY_0_SHIFT              (0U)
+/*! PARITY_0 - Bits [31:0] of the helper parity data */
+#define PUF_PARITY_0_PARITY_0(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_PARITY_0_PARITY_0_SHIFT)) & PUF_PARITY_0_PARITY_0_MASK)
+/*! @} */
+
+/*! @name PARITY_1 - Parity register */
+/*! @{ */
+
+#define PUF_PARITY_1_PARITY_1_MASK               (0xFFFFFFFFU)
+#define PUF_PARITY_1_PARITY_1_SHIFT              (0U)
+/*! PARITY_1 - Bits [63:32] of the helper parity data */
+#define PUF_PARITY_1_PARITY_1(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_PARITY_1_PARITY_1_SHIFT)) & PUF_PARITY_1_PARITY_1_MASK)
+/*! @} */
+
+/*! @name PARITY_2 - Parity register */
+/*! @{ */
+
+#define PUF_PARITY_2_PARITY_2_MASK               (0xFFFU)
+#define PUF_PARITY_2_PARITY_2_SHIFT              (0U)
+/*! PARITY_2 - Bits [75:64] of the helper parity data */
+#define PUF_PARITY_2_PARITY_2(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_PARITY_2_PARITY_2_SHIFT)) & PUF_PARITY_2_PARITY_2_MASK)
+
+#define PUF_PARITY_2_PAR_RSVD_MASK               (0xFFFFF000U)
+#define PUF_PARITY_2_PAR_RSVD_SHIFT              (12U)
+/*! PAR_RSVD - Reserved */
+#define PUF_PARITY_2_PAR_RSVD(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_PARITY_2_PAR_RSVD_SHIFT)) & PUF_PARITY_2_PAR_RSVD_MASK)
+/*! @} */
+
+/*! @name IGNORE - Ignore register */
+/*! @{ */
+
+#define PUF_IGNORE_IGNORE_MASK                   (0xFFFFFFFFU)
+#define PUF_IGNORE_IGNORE_SHIFT                  (0U)
+/*! IGNORE - Ignore data; Enrollment: Read after operation to store computed ignore tags;
+ *    Reconstruction: Written before operation to load ignore tags
+ */
+#define PUF_IGNORE_IGNORE(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IGNORE_IGNORE_SHIFT)) & PUF_IGNORE_IGNORE_MASK)
+/*! @} */
+
+/*! @name RNG - Random Number register */
+/*! @{ */
+
+#define PUF_RNG_RNG_MASK                         (0xFFFFFFFFU)
+#define PUF_RNG_RNG_SHIFT                        (0U)
+/*! RNG - Random bits used for masking during reconstruction */
+#define PUF_RNG_RNG(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_RNG_RNG_SHIFT)) & PUF_RNG_RNG_MASK)
+/*! @} */
+
+/*! @name KEY_0 - Key register */
+/*! @{ */
+
+#define PUF_KEY_0_KEY_0_MASK                     (0xFFFFFFFFU)
+#define PUF_KEY_0_KEY_0_SHIFT                    (0U)
+/*! KEY_0 - Bits [31:0] of generated key chunk */
+#define PUF_KEY_0_KEY_0(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_KEY_0_KEY_0_SHIFT)) & PUF_KEY_0_KEY_0_MASK)
+/*! @} */
+
+/*! @name KEY_1 - Key register */
+/*! @{ */
+
+#define PUF_KEY_1_KEY_1_MASK                     (0xFFFFFFFFU)
+#define PUF_KEY_1_KEY_1_SHIFT                    (0U)
+/*! KEY_1 - Bits [63:32] of generated key chunk */
+#define PUF_KEY_1_KEY_1(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_KEY_1_KEY_1_SHIFT)) & PUF_KEY_1_KEY_1_MASK)
+/*! @} */
+
+/*! @name LOCK - Lock register */
+/*! @{ */
+
+#define PUF_LOCK_KEY_ID_LCK_MASK                 (0xFFFFU)
+#define PUF_LOCK_KEY_ID_LCK_SHIFT                (0U)
+/*! KEY_ID_LCK - Key Lock; Each bit position represents the Key ID of a key; 1'b0 - Unlocked; 1'b1 - Locked */
+#define PUF_LOCK_KEY_ID_LCK(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_LOCK_KEY_ID_LCK_SHIFT)) & PUF_LOCK_KEY_ID_LCK_MASK)
+
+#define PUF_LOCK_LOCK_RSVD_MASK                  (0xFF0000U)
+#define PUF_LOCK_LOCK_RSVD_SHIFT                 (16U)
+/*! LOCK_RSVD - Reserved */
+#define PUF_LOCK_LOCK_RSVD(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_LOCK_LOCK_RSVD_SHIFT)) & PUF_LOCK_LOCK_RSVD_MASK)
+
+#define PUF_LOCK_REC_LCK_MASK                    (0xF000000U)
+#define PUF_LOCK_REC_LCK_SHIFT                   (24U)
+/*! REC_LCK - Reconstruction lock; 4'h5 - Locked; 4'hA - Unlocked */
+#define PUF_LOCK_REC_LCK(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_LOCK_REC_LCK_SHIFT)) & PUF_LOCK_REC_LCK_MASK)
+
+#define PUF_LOCK_ENR_LCK_MASK                    (0xF0000000U)
+#define PUF_LOCK_ENR_LCK_SHIFT                   (28U)
+/*! ENR_LCK - Enrollment lock; 4'h5 - Locked; 4'hA - Unlocked */
+#define PUF_LOCK_ENR_LCK(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_LOCK_ENR_LCK_SHIFT)) & PUF_LOCK_ENR_LCK_MASK)
+/*! @} */
+
+/*! @name RO_FREQ - RO Frequency register */
+/*! @{ */
+
+#define PUF_RO_FREQ_RO_FREQ_MASK                 (0xFFFFFFFFU)
+#define PUF_RO_FREQ_RO_FREQ_SHIFT                (0U)
+/*! RO_FREQ - System clock count it takes for the fastest RO of each group to reach the limit */
+#define PUF_RO_FREQ_RO_FREQ(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_RO_FREQ_RO_FREQ_SHIFT)) & PUF_RO_FREQ_RO_FREQ_MASK)
+/*! @} */
+
+/*! @name SLW_RO - Slow RO register */
+/*! @{ */
+
+#define PUF_SLW_RO_SLW_RO_MASK                   (0x1FU)
+#define PUF_SLW_RO_SLW_RO_SHIFT                  (0U)
+/*! SLW_RO - Number of slow ROs in the current group. */
+#define PUF_SLW_RO_SLW_RO(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_SLW_RO_SLW_RO_SHIFT)) & PUF_SLW_RO_SLW_RO_MASK)
+
+#define PUF_SLW_RO_SLW_MAX_PER_GRP_MASK          (0x1F00U)
+#define PUF_SLW_RO_SLW_MAX_PER_GRP_SHIFT         (8U)
+/*! SLW_MAX_PER_GRP - Largest number of slow ROs detected in a single group */
+#define PUF_SLW_RO_SLW_MAX_PER_GRP(x)            (((uint32_t)(((uint32_t)(x)) << PUF_SLW_RO_SLW_MAX_PER_GRP_SHIFT)) & PUF_SLW_RO_SLW_MAX_PER_GRP_MASK)
+
+#define PUF_SLW_RO_SLW_TOTAL_MASK                (0x1FF0000U)
+#define PUF_SLW_RO_SLW_TOTAL_SHIFT               (16U)
+/*! SLW_TOTAL - Running total number of slow ROs */
+#define PUF_SLW_RO_SLW_TOTAL(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_SLW_RO_SLW_TOTAL_SHIFT)) & PUF_SLW_RO_SLW_TOTAL_MASK)
+/*! @} */
+
+/*! @name EVAL_SEL - Evaluation Select register */
+/*! @{ */
+
+#define PUF_EVAL_SEL_E_RANK_SEL_MASK             (0x1FU)
+#define PUF_EVAL_SEL_E_RANK_SEL_SHIFT            (0U)
+/*! E_RANK_SEL - Select RO based its post-ranking position */
+#define PUF_EVAL_SEL_E_RANK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_SEL_E_RANK_SEL_SHIFT)) & PUF_EVAL_SEL_E_RANK_SEL_MASK)
+
+#define PUF_EVAL_SEL_E_RSVD_2_MASK               (0xE0U)
+#define PUF_EVAL_SEL_E_RSVD_2_SHIFT              (5U)
+/*! E_RSVD_2 - Reserved */
+#define PUF_EVAL_SEL_E_RSVD_2(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_SEL_E_RSVD_2_SHIFT)) & PUF_EVAL_SEL_E_RSVD_2_MASK)
+
+#define PUF_EVAL_SEL_E_FREE_GRP_MASK             (0x300U)
+#define PUF_EVAL_SEL_E_FREE_GRP_SHIFT            (8U)
+/*! E_FREE_GRP - Free run mode group select */
+#define PUF_EVAL_SEL_E_FREE_GRP(x)               (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_SEL_E_FREE_GRP_SHIFT)) & PUF_EVAL_SEL_E_FREE_GRP_MASK)
+
+#define PUF_EVAL_SEL_E_RSVD_1_MASK               (0xC00U)
+#define PUF_EVAL_SEL_E_RSVD_1_SHIFT              (10U)
+/*! E_RSVD_1 - Reserved */
+#define PUF_EVAL_SEL_E_RSVD_1(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_SEL_E_RSVD_1_SHIFT)) & PUF_EVAL_SEL_E_RSVD_1_MASK)
+
+#define PUF_EVAL_SEL_E_FREE_SEC_MASK             (0x7000U)
+#define PUF_EVAL_SEL_E_FREE_SEC_SHIFT            (12U)
+/*! E_FREE_SEC - Free run mode section select */
+#define PUF_EVAL_SEL_E_FREE_SEC(x)               (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_SEL_E_FREE_SEC_SHIFT)) & PUF_EVAL_SEL_E_FREE_SEC_MASK)
+
+#define PUF_EVAL_SEL_E_RSVD_0_MASK               (0xFFFF8000U)
+#define PUF_EVAL_SEL_E_RSVD_0_SHIFT              (15U)
+/*! E_RSVD_0 - Reserved */
+#define PUF_EVAL_SEL_E_RSVD_0(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_SEL_E_RSVD_0_SHIFT)) & PUF_EVAL_SEL_E_RSVD_0_MASK)
+/*! @} */
+
+/*! @name EVAL_VAL - Evaluation Value register */
+/*! @{ */
+
+#define PUF_EVAL_VAL_E_CNT_MASK                  (0xFFFFU)
+#define PUF_EVAL_VAL_E_CNT_SHIFT                 (0U)
+/*! E_CNT - Counter value of the selected RO in PUF_EVAL_SEL */
+#define PUF_EVAL_VAL_E_CNT(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_VAL_E_CNT_SHIFT)) & PUF_EVAL_VAL_E_CNT_MASK)
+
+#define PUF_EVAL_VAL_E_RSVD_4_MASK               (0xFF0000U)
+#define PUF_EVAL_VAL_E_RSVD_4_SHIFT              (16U)
+/*! E_RSVD_4 - Reserved */
+#define PUF_EVAL_VAL_E_RSVD_4(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_VAL_E_RSVD_4_SHIFT)) & PUF_EVAL_VAL_E_RSVD_4_MASK)
+
+#define PUF_EVAL_VAL_E_RO_NUM_MASK               (0x1F000000U)
+#define PUF_EVAL_VAL_E_RO_NUM_SHIFT              (24U)
+/*! E_RO_NUM - Original position of the selected RO in PUF_EVAL_SEL */
+#define PUF_EVAL_VAL_E_RO_NUM(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_VAL_E_RO_NUM_SHIFT)) & PUF_EVAL_VAL_E_RO_NUM_MASK)
+
+#define PUF_EVAL_VAL_E_RSVD_3_MASK               (0xE0000000U)
+#define PUF_EVAL_VAL_E_RSVD_3_SHIFT              (29U)
+/*! E_RSVD_3 - Reserved */
+#define PUF_EVAL_VAL_E_RSVD_3(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_VAL_E_RSVD_3_SHIFT)) & PUF_EVAL_VAL_E_RSVD_3_MASK)
+/*! @} */
+
+/*! @name EVAL_RAW - Evaluation Raw register */
+/*! @{ */
+
+#define PUF_EVAL_RAW_E_RAW_MASK                  (0xFFFU)
+#define PUF_EVAL_RAW_E_RAW_SHIFT                 (0U)
+/*! E_RAW - Raw value generated by the current group of ROs */
+#define PUF_EVAL_RAW_E_RAW(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_RAW_E_RAW_SHIFT)) & PUF_EVAL_RAW_E_RAW_MASK)
+
+#define PUF_EVAL_RAW_E_RSVD_5_MASK               (0xFFFFF000U)
+#define PUF_EVAL_RAW_E_RSVD_5_SHIFT              (12U)
+/*! E_RSVD_5 - Reserved */
+#define PUF_EVAL_RAW_E_RSVD_5(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_RAW_E_RSVD_5_SHIFT)) & PUF_EVAL_RAW_E_RSVD_5_MASK)
+/*! @} */
+
+/*! @name EVAL_BCH - Evaluation BCH register */
+/*! @{ */
+
+#define PUF_EVAL_BCH_E_BCH_ERR_MASK              (0xFU)
+#define PUF_EVAL_BCH_E_BCH_ERR_SHIFT             (0U)
+/*! E_BCH_ERR - Number of errors PUF detected */
+#define PUF_EVAL_BCH_E_BCH_ERR(x)                (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_BCH_E_BCH_ERR_SHIFT)) & PUF_EVAL_BCH_E_BCH_ERR_MASK)
+
+#define PUF_EVAL_BCH_E_RSVD_7_MASK               (0xF0U)
+#define PUF_EVAL_BCH_E_RSVD_7_SHIFT              (4U)
+/*! E_RSVD_7 - Reserved */
+#define PUF_EVAL_BCH_E_RSVD_7(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_BCH_E_RSVD_7_SHIFT)) & PUF_EVAL_BCH_E_RSVD_7_MASK)
+
+#define PUF_EVAL_BCH_E_ERR_LMT_MASK              (0xF00U)
+#define PUF_EVAL_BCH_E_ERR_LMT_SHIFT             (8U)
+/*! E_ERR_LMT - Number of errors PUF can detect */
+#define PUF_EVAL_BCH_E_ERR_LMT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_BCH_E_ERR_LMT_SHIFT)) & PUF_EVAL_BCH_E_ERR_LMT_MASK)
+
+#define PUF_EVAL_BCH_E_RSVD_6_MASK               (0xFFFFF000U)
+#define PUF_EVAL_BCH_E_RSVD_6_SHIFT              (12U)
+/*! E_RSVD_6 - Reserved */
+#define PUF_EVAL_BCH_E_RSVD_6(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_BCH_E_RSVD_6_SHIFT)) & PUF_EVAL_BCH_E_RSVD_6_MASK)
+/*! @} */
+
+/*! @name EVAL_ERR_LOC_0_1 - Error Location register */
+/*! @{ */
+
+#define PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_0_MASK    (0xFFU)
+#define PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_0_SHIFT   (0U)
+/*! E_ERR_LOC_0 - Error location 0 */
+#define PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_0(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_0_SHIFT)) & PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_0_MASK)
+
+#define PUF_EVAL_ERR_LOC_0_1_E_RSVD_9_MASK       (0xFF00U)
+#define PUF_EVAL_ERR_LOC_0_1_E_RSVD_9_SHIFT      (8U)
+/*! E_RSVD_9 - Reserved */
+#define PUF_EVAL_ERR_LOC_0_1_E_RSVD_9(x)         (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_0_1_E_RSVD_9_SHIFT)) & PUF_EVAL_ERR_LOC_0_1_E_RSVD_9_MASK)
+
+#define PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_1_MASK    (0xFF0000U)
+#define PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_1_SHIFT   (16U)
+/*! E_ERR_LOC_1 - Error location 1 */
+#define PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_1(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_1_SHIFT)) & PUF_EVAL_ERR_LOC_0_1_E_ERR_LOC_1_MASK)
+
+#define PUF_EVAL_ERR_LOC_0_1_E_RSVD_8_MASK       (0xFF000000U)
+#define PUF_EVAL_ERR_LOC_0_1_E_RSVD_8_SHIFT      (24U)
+/*! E_RSVD_8 - Reserved */
+#define PUF_EVAL_ERR_LOC_0_1_E_RSVD_8(x)         (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_0_1_E_RSVD_8_SHIFT)) & PUF_EVAL_ERR_LOC_0_1_E_RSVD_8_MASK)
+/*! @} */
+
+/*! @name EVAL_ERR_LOC_2_3 - Error Location register */
+/*! @{ */
+
+#define PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_2_MASK    (0xFFU)
+#define PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_2_SHIFT   (0U)
+/*! E_ERR_LOC_2 - Error location 2 */
+#define PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_2(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_2_SHIFT)) & PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_2_MASK)
+
+#define PUF_EVAL_ERR_LOC_2_3_E_RSVD_11_MASK      (0xFF00U)
+#define PUF_EVAL_ERR_LOC_2_3_E_RSVD_11_SHIFT     (8U)
+/*! E_RSVD_11 - Reserved */
+#define PUF_EVAL_ERR_LOC_2_3_E_RSVD_11(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_2_3_E_RSVD_11_SHIFT)) & PUF_EVAL_ERR_LOC_2_3_E_RSVD_11_MASK)
+
+#define PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_3_MASK    (0xFF0000U)
+#define PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_3_SHIFT   (16U)
+/*! E_ERR_LOC_3 - Error location 3 */
+#define PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_3(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_3_SHIFT)) & PUF_EVAL_ERR_LOC_2_3_E_ERR_LOC_3_MASK)
+
+#define PUF_EVAL_ERR_LOC_2_3_E_RSVD_10_MASK      (0xFF000000U)
+#define PUF_EVAL_ERR_LOC_2_3_E_RSVD_10_SHIFT     (24U)
+/*! E_RSVD_10 - Reserved */
+#define PUF_EVAL_ERR_LOC_2_3_E_RSVD_10(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_2_3_E_RSVD_10_SHIFT)) & PUF_EVAL_ERR_LOC_2_3_E_RSVD_10_MASK)
+/*! @} */
+
+/*! @name EVAL_ERR_LOC_4_5 - Error Location register */
+/*! @{ */
+
+#define PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_4_MASK    (0xFFU)
+#define PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_4_SHIFT   (0U)
+/*! E_ERR_LOC_4 - Error location 4 */
+#define PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_4(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_4_SHIFT)) & PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_4_MASK)
+
+#define PUF_EVAL_ERR_LOC_4_5_E_RSVD_13_MASK      (0xFF00U)
+#define PUF_EVAL_ERR_LOC_4_5_E_RSVD_13_SHIFT     (8U)
+/*! E_RSVD_13 - Reserved */
+#define PUF_EVAL_ERR_LOC_4_5_E_RSVD_13(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_4_5_E_RSVD_13_SHIFT)) & PUF_EVAL_ERR_LOC_4_5_E_RSVD_13_MASK)
+
+#define PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_5_MASK    (0xFF0000U)
+#define PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_5_SHIFT   (16U)
+/*! E_ERR_LOC_5 - Error location 5 */
+#define PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_5(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_5_SHIFT)) & PUF_EVAL_ERR_LOC_4_5_E_ERR_LOC_5_MASK)
+
+#define PUF_EVAL_ERR_LOC_4_5_E_RSVD_12_MASK      (0xFF000000U)
+#define PUF_EVAL_ERR_LOC_4_5_E_RSVD_12_SHIFT     (24U)
+/*! E_RSVD_12 - Reserved */
+#define PUF_EVAL_ERR_LOC_4_5_E_RSVD_12(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_4_5_E_RSVD_12_SHIFT)) & PUF_EVAL_ERR_LOC_4_5_E_RSVD_12_MASK)
+/*! @} */
+
+/*! @name EVAL_ERR_LOC_6_7 - Error Location register */
+/*! @{ */
+
+#define PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_6_MASK    (0xFFU)
+#define PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_6_SHIFT   (0U)
+/*! E_ERR_LOC_6 - Error location 6 */
+#define PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_6(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_6_SHIFT)) & PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_6_MASK)
+
+#define PUF_EVAL_ERR_LOC_6_7_E_RSVD_15_MASK      (0xFF00U)
+#define PUF_EVAL_ERR_LOC_6_7_E_RSVD_15_SHIFT     (8U)
+/*! E_RSVD_15 - Reserved */
+#define PUF_EVAL_ERR_LOC_6_7_E_RSVD_15(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_6_7_E_RSVD_15_SHIFT)) & PUF_EVAL_ERR_LOC_6_7_E_RSVD_15_MASK)
+
+#define PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_7_MASK    (0xFF0000U)
+#define PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_7_SHIFT   (16U)
+/*! E_ERR_LOC_7 - Error location 7 */
+#define PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_7(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_7_SHIFT)) & PUF_EVAL_ERR_LOC_6_7_E_ERR_LOC_7_MASK)
+
+#define PUF_EVAL_ERR_LOC_6_7_E_RSVD_14_MASK      (0xFF000000U)
+#define PUF_EVAL_ERR_LOC_6_7_E_RSVD_14_SHIFT     (24U)
+/*! E_RSVD_14 - Reserved */
+#define PUF_EVAL_ERR_LOC_6_7_E_RSVD_14(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_6_7_E_RSVD_14_SHIFT)) & PUF_EVAL_ERR_LOC_6_7_E_RSVD_14_MASK)
+/*! @} */
+
+/*! @name EVAL_ERR_LOC_8_9 - Error Location register */
+/*! @{ */
+
+#define PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_8_MASK    (0xFFU)
+#define PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_8_SHIFT   (0U)
+/*! E_ERR_LOC_8 - Error location 8 */
+#define PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_8(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_8_SHIFT)) & PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_8_MASK)
+
+#define PUF_EVAL_ERR_LOC_8_9_E_RSVD_17_MASK      (0xFF00U)
+#define PUF_EVAL_ERR_LOC_8_9_E_RSVD_17_SHIFT     (8U)
+/*! E_RSVD_17 - Reserved */
+#define PUF_EVAL_ERR_LOC_8_9_E_RSVD_17(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_8_9_E_RSVD_17_SHIFT)) & PUF_EVAL_ERR_LOC_8_9_E_RSVD_17_MASK)
+
+#define PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_9_MASK    (0xFF0000U)
+#define PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_9_SHIFT   (16U)
+/*! E_ERR_LOC_9 - Error location 9 */
+#define PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_9(x)      (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_9_SHIFT)) & PUF_EVAL_ERR_LOC_8_9_E_ERR_LOC_9_MASK)
+
+#define PUF_EVAL_ERR_LOC_8_9_E_RSVD_16_MASK      (0xFF000000U)
+#define PUF_EVAL_ERR_LOC_8_9_E_RSVD_16_SHIFT     (24U)
+/*! E_RSVD_16 - Reserved */
+#define PUF_EVAL_ERR_LOC_8_9_E_RSVD_16(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_ERR_LOC_8_9_E_RSVD_16_SHIFT)) & PUF_EVAL_ERR_LOC_8_9_E_RSVD_16_MASK)
+/*! @} */
+
+/*! @name EVAL_RND_KEY_0 - Evaluation Round Key register */
+/*! @{ */
+
+#define PUF_EVAL_RND_KEY_0_E_RND_KEY_0_MASK      (0xFFFFFFFFU)
+#define PUF_EVAL_RND_KEY_0_E_RND_KEY_0_SHIFT     (0U)
+/*! E_RND_KEY_0 - Bits [31:0] of current round key used in PRASH */
+#define PUF_EVAL_RND_KEY_0_E_RND_KEY_0(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_RND_KEY_0_E_RND_KEY_0_SHIFT)) & PUF_EVAL_RND_KEY_0_E_RND_KEY_0_MASK)
+/*! @} */
+
+/*! @name EVAL_RND_KEY_1 - Evaluation Round Key register */
+/*! @{ */
+
+#define PUF_EVAL_RND_KEY_1_E_RND_KEY_1_MASK      (0xFFFFFFFFU)
+#define PUF_EVAL_RND_KEY_1_E_RND_KEY_1_SHIFT     (0U)
+/*! E_RND_KEY_1 - Bits [63:32] of current round key used in PRASH */
+#define PUF_EVAL_RND_KEY_1_E_RND_KEY_1(x)        (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_RND_KEY_1_E_RND_KEY_1_SHIFT)) & PUF_EVAL_RND_KEY_1_E_RND_KEY_1_MASK)
+/*! @} */
+
+/*! @name EVAL_CTRL - Evaluation Control register */
+/*! @{ */
+
+#define PUF_EVAL_CTRL_E_EVAL_EN_MASK             (0xFU)
+#define PUF_EVAL_CTRL_E_EVAL_EN_SHIFT            (0U)
+/*! E_EVAL_EN - Evaluation mode enable; 4'h5 - Disabled; 4'hA - Enabled */
+#define PUF_EVAL_CTRL_E_EVAL_EN(x)               (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_CTRL_E_EVAL_EN_SHIFT)) & PUF_EVAL_CTRL_E_EVAL_EN_MASK)
+
+#define PUF_EVAL_CTRL_E_EVAL_LCK_MASK            (0xF0U)
+#define PUF_EVAL_CTRL_E_EVAL_LCK_SHIFT           (4U)
+/*! E_EVAL_LCK - Evaluation mode lock; 4'h5 - Locked; 4'hA - Unlocked */
+#define PUF_EVAL_CTRL_E_EVAL_LCK(x)              (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_CTRL_E_EVAL_LCK_SHIFT)) & PUF_EVAL_CTRL_E_EVAL_LCK_MASK)
+
+#define PUF_EVAL_CTRL_E_FREE_MASK                (0x100U)
+#define PUF_EVAL_CTRL_E_FREE_SHIFT               (8U)
+/*! E_FREE - Free running mode; 1'b0 - Off; 1'b1 - On */
+#define PUF_EVAL_CTRL_E_FREE(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_CTRL_E_FREE_SHIFT)) & PUF_EVAL_CTRL_E_FREE_MASK)
+
+#define PUF_EVAL_CTRL_E_RSVD_18_MASK             (0xFFFFFE00U)
+#define PUF_EVAL_CTRL_E_RSVD_18_SHIFT            (9U)
+/*! E_RSVD_18 - Reserved */
+#define PUF_EVAL_CTRL_E_RSVD_18(x)               (((uint32_t)(((uint32_t)(x)) << PUF_EVAL_CTRL_E_RSVD_18_SHIFT)) & PUF_EVAL_CTRL_E_RSVD_18_MASK)
+/*! @} */
+
+/*! @name ACCESS_ERR - Access Error register */
+/*! @{ */
+
+#define PUF_ACCESS_ERR_APB_NOTAV_MASK            (0x1U)
+#define PUF_ACCESS_ERR_APB_NOTAV_SHIFT           (0U)
+/*! APB_NOTAV - APB error: address not available */
+#define PUF_ACCESS_ERR_APB_NOTAV(x)              (((uint32_t)(((uint32_t)(x)) << PUF_ACCESS_ERR_APB_NOTAV_SHIFT)) & PUF_ACCESS_ERR_APB_NOTAV_MASK)
+
+#define PUF_ACCESS_ERR_APB_WRGMD_MASK            (0x2U)
+#define PUF_ACCESS_ERR_APB_WRGMD_SHIFT           (1U)
+/*! APB_WRGMD - APB error: wrong access mode */
+#define PUF_ACCESS_ERR_APB_WRGMD(x)              (((uint32_t)(((uint32_t)(x)) << PUF_ACCESS_ERR_APB_WRGMD_SHIFT)) & PUF_ACCESS_ERR_APB_WRGMD_MASK)
+
+#define PUF_ACCESS_ERR_ACCESS_ERR_RSVD_1_MASK    (0xCU)
+#define PUF_ACCESS_ERR_ACCESS_ERR_RSVD_1_SHIFT   (2U)
+/*! ACCESS_ERR_RSVD_1 - Reserved */
+#define PUF_ACCESS_ERR_ACCESS_ERR_RSVD_1(x)      (((uint32_t)(((uint32_t)(x)) << PUF_ACCESS_ERR_ACCESS_ERR_RSVD_1_SHIFT)) & PUF_ACCESS_ERR_ACCESS_ERR_RSVD_1_MASK)
+
+#define PUF_ACCESS_ERR_APB_MASTER_MASK           (0xF0U)
+#define PUF_ACCESS_ERR_APB_MASTER_SHIFT          (4U)
+/*! APB_MASTER - APB Master that triggered the APB error */
+#define PUF_ACCESS_ERR_APB_MASTER(x)             (((uint32_t)(((uint32_t)(x)) << PUF_ACCESS_ERR_APB_MASTER_SHIFT)) & PUF_ACCESS_ERR_APB_MASTER_MASK)
+
+#define PUF_ACCESS_ERR_ACCESS_ERR_RSVD_0_MASK    (0xFFFFFF00U)
+#define PUF_ACCESS_ERR_ACCESS_ERR_RSVD_0_SHIFT   (8U)
+/*! ACCESS_ERR_RSVD_0 - Reserved */
+#define PUF_ACCESS_ERR_ACCESS_ERR_RSVD_0(x)      (((uint32_t)(((uint32_t)(x)) << PUF_ACCESS_ERR_ACCESS_ERR_RSVD_0_SHIFT)) & PUF_ACCESS_ERR_ACCESS_ERR_RSVD_0_MASK)
+/*! @} */
+
+/*! @name ACCESS_ERR_CLR - Access Error Clear register */
+/*! @{ */
+
+#define PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_MASK   (0x1U)
+#define PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_SHIFT  (0U)
+/*! ACCESS_ERR_CLR - Clear access errors */
+#define PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR(x)     (((uint32_t)(((uint32_t)(x)) << PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_SHIFT)) & PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_MASK)
+
+#define PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_RSVD_MASK (0xFFFFFFFEU)
+#define PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_RSVD_SHIFT (1U)
+/*! ACCESS_ERR_CLR_RSVD - Reserved */
+#define PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_RSVD_SHIFT)) & PUF_ACCESS_ERR_CLR_ACCESS_ERR_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status register */
+/*! @{ */
+
+#define PUF_INT_STATUS_INT_ERROR_MASK            (0x1U)
+#define PUF_INT_STATUS_INT_ERROR_SHIFT           (0U)
+/*! INT_ERROR - Error has occured */
+#define PUF_INT_STATUS_INT_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_INT_ERROR_SHIFT)) & PUF_INT_STATUS_INT_ERROR_MASK)
+
+#define PUF_INT_STATUS_RNG_RDY_MASK              (0x2U)
+#define PUF_INT_STATUS_RNG_RDY_SHIFT             (1U)
+/*! RNG_RDY - Reconstruction only: more random data is required */
+#define PUF_INT_STATUS_RNG_RDY(x)                (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_RNG_RDY_SHIFT)) & PUF_INT_STATUS_RNG_RDY_MASK)
+
+#define PUF_INT_STATUS_RANK_DONE_MASK            (0x4U)
+#define PUF_INT_STATUS_RANK_DONE_SHIFT           (2U)
+/*! RANK_DONE - Enrollment only: Ranking is complete and ignore data is ready to be read */
+#define PUF_INT_STATUS_RANK_DONE(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_RANK_DONE_SHIFT)) & PUF_INT_STATUS_RANK_DONE_MASK)
+
+#define PUF_INT_STATUS_PAR_RDY_MASK              (0x8U)
+#define PUF_INT_STATUS_PAR_RDY_SHIFT             (3U)
+/*! PAR_RDY - Parity data has been calculated and ready to be read */
+#define PUF_INT_STATUS_PAR_RDY(x)                (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_PAR_RDY_SHIFT)) & PUF_INT_STATUS_PAR_RDY_MASK)
+
+#define PUF_INT_STATUS_CKS_RDY_MASK              (0x10U)
+#define PUF_INT_STATUS_CKS_RDY_SHIFT             (4U)
+/*! CKS_RDY - Checksum has been calculated and ready to be read */
+#define PUF_INT_STATUS_CKS_RDY(x)                (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CKS_RDY_SHIFT)) & PUF_INT_STATUS_CKS_RDY_MASK)
+
+#define PUF_INT_STATUS_IGN_LOAD_MASK             (0x20U)
+#define PUF_INT_STATUS_IGN_LOAD_SHIFT            (5U)
+/*! IGN_LOAD - Reconstruction only: ignore data is required to be loaded */
+#define PUF_INT_STATUS_IGN_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_IGN_LOAD_SHIFT)) & PUF_INT_STATUS_IGN_LOAD_MASK)
+
+#define PUF_INT_STATUS_KEY_RDY_MASK              (0x40U)
+#define PUF_INT_STATUS_KEY_RDY_SHIFT             (6U)
+/*! KEY_RDY - Key chunk has been generated and ready to be read */
+#define PUF_INT_STATUS_KEY_RDY(x)                (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_KEY_RDY_SHIFT)) & PUF_INT_STATUS_KEY_RDY_MASK)
+
+#define PUF_INT_STATUS_INT_RSVD_MASK             (0xFFFFFF80U)
+#define PUF_INT_STATUS_INT_RSVD_SHIFT            (7U)
+/*! INT_RSVD - Reserved */
+#define PUF_INT_STATUS_INT_RSVD(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_INT_RSVD_SHIFT)) & PUF_INT_STATUS_INT_RSVD_MASK)
+/*! @} */
+
+/*! @name INT_ENABLE - Interrupt Enable register */
+/*! @{ */
+
+#define PUF_INT_ENABLE_INT_EN_ERROR_MASK         (0x1U)
+#define PUF_INT_ENABLE_INT_EN_ERROR_SHIFT        (0U)
+/*! INT_EN_ERROR - Interrupt enable for error interrupt */
+#define PUF_INT_ENABLE_INT_EN_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_ERROR_SHIFT)) & PUF_INT_ENABLE_INT_EN_ERROR_MASK)
+
+#define PUF_INT_ENABLE_INT_EN_RNG_RDY_MASK       (0x2U)
+#define PUF_INT_ENABLE_INT_EN_RNG_RDY_SHIFT      (1U)
+/*! INT_EN_RNG_RDY - Interrupt enable for RNG_RDY */
+#define PUF_INT_ENABLE_INT_EN_RNG_RDY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_RNG_RDY_SHIFT)) & PUF_INT_ENABLE_INT_EN_RNG_RDY_MASK)
+
+#define PUF_INT_ENABLE_INT_EN_RANK_DONE_MASK     (0x4U)
+#define PUF_INT_ENABLE_INT_EN_RANK_DONE_SHIFT    (2U)
+/*! INT_EN_RANK_DONE - Interrupt enable for RANK_DONE */
+#define PUF_INT_ENABLE_INT_EN_RANK_DONE(x)       (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_RANK_DONE_SHIFT)) & PUF_INT_ENABLE_INT_EN_RANK_DONE_MASK)
+
+#define PUF_INT_ENABLE_INT_EN_PAR_RDY_MASK       (0x8U)
+#define PUF_INT_ENABLE_INT_EN_PAR_RDY_SHIFT      (3U)
+/*! INT_EN_PAR_RDY - Interrupt enable for PAR_RDY */
+#define PUF_INT_ENABLE_INT_EN_PAR_RDY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_PAR_RDY_SHIFT)) & PUF_INT_ENABLE_INT_EN_PAR_RDY_MASK)
+
+#define PUF_INT_ENABLE_INT_EN_CKS_RDY_MASK       (0x10U)
+#define PUF_INT_ENABLE_INT_EN_CKS_RDY_SHIFT      (4U)
+/*! INT_EN_CKS_RDY - Interrupt enable for CKS_RDY */
+#define PUF_INT_ENABLE_INT_EN_CKS_RDY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_CKS_RDY_SHIFT)) & PUF_INT_ENABLE_INT_EN_CKS_RDY_MASK)
+
+#define PUF_INT_ENABLE_INT_EN_IGN_LOAD_MASK      (0x20U)
+#define PUF_INT_ENABLE_INT_EN_IGN_LOAD_SHIFT     (5U)
+/*! INT_EN_IGN_LOAD - Interrupt enable for IGN_LOAD */
+#define PUF_INT_ENABLE_INT_EN_IGN_LOAD(x)        (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_IGN_LOAD_SHIFT)) & PUF_INT_ENABLE_INT_EN_IGN_LOAD_MASK)
+
+#define PUF_INT_ENABLE_INT_EN_KEY_RDY_MASK       (0x40U)
+#define PUF_INT_ENABLE_INT_EN_KEY_RDY_SHIFT      (6U)
+/*! INT_EN_KEY_RDY - Interrupt enable for KEY_RDY */
+#define PUF_INT_ENABLE_INT_EN_KEY_RDY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_KEY_RDY_SHIFT)) & PUF_INT_ENABLE_INT_EN_KEY_RDY_MASK)
+
+#define PUF_INT_ENABLE_INT_EN_RSVD_MASK          (0xFFFFFF80U)
+#define PUF_INT_ENABLE_INT_EN_RSVD_SHIFT         (7U)
+/*! INT_EN_RSVD - Reserved */
+#define PUF_INT_ENABLE_INT_EN_RSVD(x)            (((uint32_t)(((uint32_t)(x)) << PUF_INT_ENABLE_INT_EN_RSVD_SHIFT)) & PUF_INT_ENABLE_INT_EN_RSVD_MASK)
+/*! @} */
+
+/*! @name INT_STATUS_CLR - Interrupt Status Clear register */
+/*! @{ */
+
+#define PUF_INT_STATUS_CLR_INT_CLR_ERROR_MASK    (0x1U)
+#define PUF_INT_STATUS_CLR_INT_CLR_ERROR_SHIFT   (0U)
+/*! INT_CLR_ERROR - Interrupt clear for error interrupt */
+#define PUF_INT_STATUS_CLR_INT_CLR_ERROR(x)      (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_ERROR_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_ERROR_MASK)
+
+#define PUF_INT_STATUS_CLR_INT_CLR_RNG_RDY_MASK  (0x2U)
+#define PUF_INT_STATUS_CLR_INT_CLR_RNG_RDY_SHIFT (1U)
+/*! INT_CLR_RNG_RDY - Interrupt clear for RNG_RDY */
+#define PUF_INT_STATUS_CLR_INT_CLR_RNG_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_RNG_RDY_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_RNG_RDY_MASK)
+
+#define PUF_INT_STATUS_CLR_INT_CLR_RANK_DONE_MASK (0x4U)
+#define PUF_INT_STATUS_CLR_INT_CLR_RANK_DONE_SHIFT (2U)
+/*! INT_CLR_RANK_DONE - Interrupt clear for RANK_DONE */
+#define PUF_INT_STATUS_CLR_INT_CLR_RANK_DONE(x)  (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_RANK_DONE_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_RANK_DONE_MASK)
+
+#define PUF_INT_STATUS_CLR_INT_CLR_PAR_RDY_MASK  (0x8U)
+#define PUF_INT_STATUS_CLR_INT_CLR_PAR_RDY_SHIFT (3U)
+/*! INT_CLR_PAR_RDY - Interrupt clear for PAR_RDY */
+#define PUF_INT_STATUS_CLR_INT_CLR_PAR_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_PAR_RDY_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_PAR_RDY_MASK)
+
+#define PUF_INT_STATUS_CLR_INT_CLR_CKS_RDY_MASK  (0x10U)
+#define PUF_INT_STATUS_CLR_INT_CLR_CKS_RDY_SHIFT (4U)
+/*! INT_CLR_CKS_RDY - Interrupt clear for CKS_RDY */
+#define PUF_INT_STATUS_CLR_INT_CLR_CKS_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_CKS_RDY_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_CKS_RDY_MASK)
+
+#define PUF_INT_STATUS_CLR_INT_CLR_IGN_LOAD_MASK (0x20U)
+#define PUF_INT_STATUS_CLR_INT_CLR_IGN_LOAD_SHIFT (5U)
+/*! INT_CLR_IGN_LOAD - Interrupt clear for IGN_LOAD */
+#define PUF_INT_STATUS_CLR_INT_CLR_IGN_LOAD(x)   (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_IGN_LOAD_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_IGN_LOAD_MASK)
+
+#define PUF_INT_STATUS_CLR_INT_CLR_KEY_RDY_MASK  (0x40U)
+#define PUF_INT_STATUS_CLR_INT_CLR_KEY_RDY_SHIFT (6U)
+/*! INT_CLR_KEY_RDY - Interrupt clear for KEY_RDY */
+#define PUF_INT_STATUS_CLR_INT_CLR_KEY_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_KEY_RDY_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_KEY_RDY_MASK)
+
+#define PUF_INT_STATUS_CLR_INT_CLR_RSVD_MASK     (0xFFFFFF80U)
+#define PUF_INT_STATUS_CLR_INT_CLR_RSVD_SHIFT    (7U)
+/*! INT_CLR_RSVD - Reserved */
+#define PUF_INT_STATUS_CLR_INT_CLR_RSVD(x)       (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_CLR_INT_CLR_RSVD_SHIFT)) & PUF_INT_STATUS_CLR_INT_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name INT_STATUS_SET - Interrupt Status Set register */
+/*! @{ */
+
+#define PUF_INT_STATUS_SET_INT_SET_ERROR_MASK    (0x1U)
+#define PUF_INT_STATUS_SET_INT_SET_ERROR_SHIFT   (0U)
+/*! INT_SET_ERROR - Interrupt set for error interrupt */
+#define PUF_INT_STATUS_SET_INT_SET_ERROR(x)      (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_ERROR_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_ERROR_MASK)
+
+#define PUF_INT_STATUS_SET_INT_SET_RNG_RDY_MASK  (0x2U)
+#define PUF_INT_STATUS_SET_INT_SET_RNG_RDY_SHIFT (1U)
+/*! INT_SET_RNG_RDY - Interrupt set for RNG_RDY */
+#define PUF_INT_STATUS_SET_INT_SET_RNG_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_RNG_RDY_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_RNG_RDY_MASK)
+
+#define PUF_INT_STATUS_SET_INT_SET_RANK_DONE_MASK (0x4U)
+#define PUF_INT_STATUS_SET_INT_SET_RANK_DONE_SHIFT (2U)
+/*! INT_SET_RANK_DONE - Interrupt set for RANK_DONE */
+#define PUF_INT_STATUS_SET_INT_SET_RANK_DONE(x)  (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_RANK_DONE_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_RANK_DONE_MASK)
+
+#define PUF_INT_STATUS_SET_INT_SET_PAR_RDY_MASK  (0x8U)
+#define PUF_INT_STATUS_SET_INT_SET_PAR_RDY_SHIFT (3U)
+/*! INT_SET_PAR_RDY - Interrupt set for PAR_RDY */
+#define PUF_INT_STATUS_SET_INT_SET_PAR_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_PAR_RDY_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_PAR_RDY_MASK)
+
+#define PUF_INT_STATUS_SET_INT_SET_CKS_RDY_MASK  (0x10U)
+#define PUF_INT_STATUS_SET_INT_SET_CKS_RDY_SHIFT (4U)
+/*! INT_SET_CKS_RDY - Interrupt set for CKS_RDY */
+#define PUF_INT_STATUS_SET_INT_SET_CKS_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_CKS_RDY_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_CKS_RDY_MASK)
+
+#define PUF_INT_STATUS_SET_INT_SET_IGN_LOAD_MASK (0x20U)
+#define PUF_INT_STATUS_SET_INT_SET_IGN_LOAD_SHIFT (5U)
+/*! INT_SET_IGN_LOAD - Interrupt set for IGN_LOAD */
+#define PUF_INT_STATUS_SET_INT_SET_IGN_LOAD(x)   (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_IGN_LOAD_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_IGN_LOAD_MASK)
+
+#define PUF_INT_STATUS_SET_INT_SET_KEY_RDY_MASK  (0x40U)
+#define PUF_INT_STATUS_SET_INT_SET_KEY_RDY_SHIFT (6U)
+/*! INT_SET_KEY_RDY - Interrupt set for KEY_RDY */
+#define PUF_INT_STATUS_SET_INT_SET_KEY_RDY(x)    (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_KEY_RDY_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_KEY_RDY_MASK)
+
+#define PUF_INT_STATUS_SET_INT_SET_RSVD_MASK     (0xFFFFFF80U)
+#define PUF_INT_STATUS_SET_INT_SET_RSVD_SHIFT    (7U)
+/*! INT_SET_RSVD - Reserved */
+#define PUF_INT_STATUS_SET_INT_SET_RSVD(x)       (((uint32_t)(((uint32_t)(x)) << PUF_INT_STATUS_SET_INT_SET_RSVD_SHIFT)) & PUF_INT_STATUS_SET_INT_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name MODULE_ID - Module ID register */
+/*! @{ */
+
+#define PUF_MODULE_ID_PLACEHOLDER_MASK           (0xFFFFFFFFU)
+#define PUF_MODULE_ID_PLACEHOLDER_SHIFT          (0U)
+/*! PLACEHOLDER - Module ID */
+#define PUF_MODULE_ID_PLACEHOLDER(x)             (((uint32_t)(((uint32_t)(x)) << PUF_MODULE_ID_PLACEHOLDER_SHIFT)) & PUF_MODULE_ID_PLACEHOLDER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PUF_Register_Masks */
+
+
+/* PUF - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral PUF base address */
+  #define PUF_BASE                                 (0x50006000u)
+  /** Peripheral PUF base address */
+  #define PUF_BASE_NS                              (0x40006000u)
+  /** Peripheral PUF base pointer */
+  #define PUF                                      ((PUF_Type *)PUF_BASE)
+  /** Peripheral PUF base pointer */
+  #define PUF_NS                                   ((PUF_Type *)PUF_BASE_NS)
+  /** Array initializer of PUF peripheral base addresses */
+  #define PUF_BASE_ADDRS                           { PUF_BASE }
+  /** Array initializer of PUF peripheral base pointers */
+  #define PUF_BASE_PTRS                            { PUF }
+  /** Array initializer of PUF peripheral base addresses */
+  #define PUF_BASE_ADDRS_NS                        { PUF_BASE_NS }
+  /** Array initializer of PUF peripheral base pointers */
+  #define PUF_BASE_PTRS_NS                         { PUF_NS }
+#else
+  /** Peripheral PUF base address */
+  #define PUF_BASE                                 (0x40006000u)
+  /** Peripheral PUF base pointer */
+  #define PUF                                      ((PUF_Type *)PUF_BASE)
+  /** Array initializer of PUF peripheral base addresses */
+  #define PUF_BASE_ADDRS                           { PUF_BASE }
+  /** Array initializer of PUF peripheral base pointers */
+  #define PUF_BASE_PTRS                            { PUF }
+#endif
+
+/*!
+ * @}
+ */ /* end of group PUF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RF_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RF_SYSCON_Peripheral_Access_Layer RF_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** RF_SYSCON - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1024];
+  __I  uint32_t WO_SCRATCH_REG[8];                 /**< Write once scratch register 0..Write once scratch register 7, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_1[96];
+  __IO uint32_t RW_SCRATCH_REG[8];                 /**< Scratch register 0..Scratch register 7, array offset: 0x480, array step: 0x4 */
+} RF_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RF_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RF_SYSCON_Register_Masks RF_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name WO_SCRATCH_REG - Write once scratch register 0..Write once scratch register 7 */
+/*! @{ */
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_SHIFT (0U)
+/*! WO_SCRATCH_REG0 - Write once scratch register 0 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_MASK)
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_SHIFT (0U)
+/*! WO_SCRATCH_REG1 - Write once scratch register 1 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_MASK)
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_SHIFT (0U)
+/*! WO_SCRATCH_REG2 - Write once scratch register 2 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_MASK)
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_SHIFT (0U)
+/*! WO_SCRATCH_REG3 - Write once scratch register 3 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_MASK)
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_SHIFT (0U)
+/*! WO_SCRATCH_REG4 - Write once scratch register 4 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_MASK)
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_SHIFT (0U)
+/*! WO_SCRATCH_REG5 - Write once scratch register 5 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_MASK)
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_SHIFT (0U)
+/*! WO_SCRATCH_REG6 - Write once scratch register 6 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_MASK)
+
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_SHIFT (0U)
+/*! WO_SCRATCH_REG7 - Write once scratch register 7 */
+#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_MASK)
+/*! @} */
+
+/* The count of RF_SYSCON_WO_SCRATCH_REG */
+#define RF_SYSCON_WO_SCRATCH_REG_COUNT           (8U)
+
+/*! @name RW_SCRATCH_REG - Scratch register 0..Scratch register 7 */
+/*! @{ */
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_SHIFT (0U)
+/*! RW_SCRATCH_REG0 - Scratch register 0 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_MASK)
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_SHIFT (0U)
+/*! RW_SCRATCH_REG1 - Scratch register 1 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_MASK)
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_SHIFT (0U)
+/*! RW_SCRATCH_REG2 - Scratch register 2 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_MASK)
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_SHIFT (0U)
+/*! RW_SCRATCH_REG3 - Scratch register 3 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_MASK)
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_SHIFT (0U)
+/*! RW_SCRATCH_REG4 - Scratch register 4 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_MASK)
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_SHIFT (0U)
+/*! RW_SCRATCH_REG5 - Scratch register 5 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_MASK)
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_SHIFT (0U)
+/*! RW_SCRATCH_REG6 - Scratch register 6 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_MASK)
+
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_MASK (0xFFFFFFFFU)
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_SHIFT (0U)
+/*! RW_SCRATCH_REG7 - Scratch register 7 */
+#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_MASK)
+/*! @} */
+
+/* The count of RF_SYSCON_RW_SCRATCH_REG */
+#define RF_SYSCON_RW_SCRATCH_REG_COUNT           (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RF_SYSCON_Register_Masks */
+
+
+/* RF_SYSCON - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral RF_SYSCON base address */
+  #define RF_SYSCON_BASE                           (0x5003B000u)
+  /** Peripheral RF_SYSCON base address */
+  #define RF_SYSCON_BASE_NS                        (0x4003B000u)
+  /** Peripheral RF_SYSCON base pointer */
+  #define RF_SYSCON                                ((RF_SYSCON_Type *)RF_SYSCON_BASE)
+  /** Peripheral RF_SYSCON base pointer */
+  #define RF_SYSCON_NS                             ((RF_SYSCON_Type *)RF_SYSCON_BASE_NS)
+  /** Array initializer of RF_SYSCON peripheral base addresses */
+  #define RF_SYSCON_BASE_ADDRS                     { RF_SYSCON_BASE }
+  /** Array initializer of RF_SYSCON peripheral base pointers */
+  #define RF_SYSCON_BASE_PTRS                      { RF_SYSCON }
+  /** Array initializer of RF_SYSCON peripheral base addresses */
+  #define RF_SYSCON_BASE_ADDRS_NS                  { RF_SYSCON_BASE_NS }
+  /** Array initializer of RF_SYSCON peripheral base pointers */
+  #define RF_SYSCON_BASE_PTRS_NS                   { RF_SYSCON_NS }
+#else
+  /** Peripheral RF_SYSCON base address */
+  #define RF_SYSCON_BASE                           (0x4003B000u)
+  /** Peripheral RF_SYSCON base pointer */
+  #define RF_SYSCON                                ((RF_SYSCON_Type *)RF_SYSCON_BASE)
+  /** Array initializer of RF_SYSCON peripheral base addresses */
+  #define RF_SYSCON_BASE_ADDRS                     { RF_SYSCON_BASE }
+  /** Array initializer of RF_SYSCON peripheral base pointers */
+  #define RF_SYSCON_BASE_PTRS                      { RF_SYSCON }
+#endif
+
+/*!
+ * @}
+ */ /* end of group RF_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ROMCP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROMCP_Peripheral_Access_Layer ROMCP Peripheral Access Layer
+ * @{
+ */
+
+/** ROMCP - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[212];
+  __IO uint32_t ROMPATCHD[8];                      /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
+  __IO uint32_t ROMPATCHCNTL;                      /**< ROMC Control Register, offset: 0xF4 */
+       uint32_t ROMPATCHENH;                       /**< ROMC Enable Register High, offset: 0xF8 */
+  __IO uint32_t ROMPATCHENL;                       /**< ROMC Enable Register Low, offset: 0xFC */
+  __IO uint32_t ROMPATCHA[16];                     /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_1[200];
+  __IO uint32_t ROMPATCHSR;                        /**< ROMC Status Register, offset: 0x208 */
+} ROMCP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ROMCP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROMCP_Register_Masks ROMCP Register Masks
+ * @{
+ */
+
+/*! @name ROMPATCHD - ROMC Data Registers */
+/*! @{ */
+
+#define ROMCP_ROMPATCHD_DATAX_MASK               (0xFFFFFFFFU)
+#define ROMCP_ROMPATCHD_DATAX_SHIFT              (0U)
+/*! DATAX - Data Fix Registers */
+#define ROMCP_ROMPATCHD_DATAX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHD_DATAX_SHIFT)) & ROMCP_ROMPATCHD_DATAX_MASK)
+/*! @} */
+
+/* The count of ROMCP_ROMPATCHD */
+#define ROMCP_ROMPATCHD_COUNT                    (8U)
+
+/*! @name ROMPATCHCNTL - ROMC Control Register */
+/*! @{ */
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX0_MASK         (0x1U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT        (0U)
+/*! DATAFIX0 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX0(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX0_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX1_MASK         (0x2U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT        (1U)
+/*! DATAFIX1 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX1(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX1_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX2_MASK         (0x4U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT        (2U)
+/*! DATAFIX2 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX2(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX2_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX3_MASK         (0x8U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT        (3U)
+/*! DATAFIX3 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX3(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX3_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX4_MASK         (0x10U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT        (4U)
+/*! DATAFIX4 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX4(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX4_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX5_MASK         (0x20U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT        (5U)
+/*! DATAFIX5 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX5(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX5_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX6_MASK         (0x40U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT        (6U)
+/*! DATAFIX6 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX6(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX6_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DATAFIX7_MASK         (0x80U)
+#define ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT        (7U)
+/*! DATAFIX7 - Data Fix Enable
+ *  0b0..Trigger an opcode patch
+ *  0b1..Trigger a data fix
+ */
+#define ROMCP_ROMPATCHCNTL_DATAFIX7(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX7_MASK)
+
+#define ROMCP_ROMPATCHCNTL_DIS_MASK              (0x20000000U)
+#define ROMCP_ROMPATCHCNTL_DIS_SHIFT             (29U)
+/*! DIS - ROMC Disable
+ *  0b0..Does not affect any ROMC functions (default)
+ *  0b1..Disables all ROMC functions: data fixing and opcode patching
+ */
+#define ROMCP_ROMPATCHCNTL_DIS(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & ROMCP_ROMPATCHCNTL_DIS_MASK)
+
+#define ROMCP_ROMPATCHCNTL_LK_MASK               (0x80000000U)
+#define ROMCP_ROMPATCHCNTL_LK_SHIFT              (31U)
+/*! LK - Register Lock
+ *  0b0..All registers remain accessible (unlocked).
+ *  0b1..Lock access to all registers. All ROMCP register accesses are treated as read-as-zero, except for this LK
+ *       bit which reads as set. All writes are ignored.
+ */
+#define ROMCP_ROMPATCHCNTL_LK(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_LK_SHIFT)) & ROMCP_ROMPATCHCNTL_LK_MASK)
+/*! @} */
+
+/*! @name ROMPATCHENL - ROMC Enable Register Low */
+/*! @{ */
+
+#define ROMCP_ROMPATCHENL_ENABLE0_MASK           (0x1U)
+#define ROMCP_ROMPATCHENL_ENABLE0_SHIFT          (0U)
+/*! ENABLE0 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE0(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE0_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE0_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE1_MASK           (0x2U)
+#define ROMCP_ROMPATCHENL_ENABLE1_SHIFT          (1U)
+/*! ENABLE1 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE1(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE1_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE1_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE2_MASK           (0x4U)
+#define ROMCP_ROMPATCHENL_ENABLE2_SHIFT          (2U)
+/*! ENABLE2 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE2(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE2_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE2_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE3_MASK           (0x8U)
+#define ROMCP_ROMPATCHENL_ENABLE3_SHIFT          (3U)
+/*! ENABLE3 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE3(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE3_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE3_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE4_MASK           (0x10U)
+#define ROMCP_ROMPATCHENL_ENABLE4_SHIFT          (4U)
+/*! ENABLE4 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE4(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE4_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE4_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE5_MASK           (0x20U)
+#define ROMCP_ROMPATCHENL_ENABLE5_SHIFT          (5U)
+/*! ENABLE5 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE5(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE5_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE5_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE6_MASK           (0x40U)
+#define ROMCP_ROMPATCHENL_ENABLE6_SHIFT          (6U)
+/*! ENABLE6 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE6(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE6_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE6_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE7_MASK           (0x80U)
+#define ROMCP_ROMPATCHENL_ENABLE7_SHIFT          (7U)
+/*! ENABLE7 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE7(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE7_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE7_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE8_MASK           (0x100U)
+#define ROMCP_ROMPATCHENL_ENABLE8_SHIFT          (8U)
+/*! ENABLE8 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE8(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE8_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE8_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE9_MASK           (0x200U)
+#define ROMCP_ROMPATCHENL_ENABLE9_SHIFT          (9U)
+/*! ENABLE9 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE9(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE9_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE9_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE10_MASK          (0x400U)
+#define ROMCP_ROMPATCHENL_ENABLE10_SHIFT         (10U)
+/*! ENABLE10 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE10(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE10_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE10_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE11_MASK          (0x800U)
+#define ROMCP_ROMPATCHENL_ENABLE11_SHIFT         (11U)
+/*! ENABLE11 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE11(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE11_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE11_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE12_MASK          (0x1000U)
+#define ROMCP_ROMPATCHENL_ENABLE12_SHIFT         (12U)
+/*! ENABLE12 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE12(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE12_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE12_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE13_MASK          (0x2000U)
+#define ROMCP_ROMPATCHENL_ENABLE13_SHIFT         (13U)
+/*! ENABLE13 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE13(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE13_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE13_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE14_MASK          (0x4000U)
+#define ROMCP_ROMPATCHENL_ENABLE14_SHIFT         (14U)
+/*! ENABLE14 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE14(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE14_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE14_MASK)
+
+#define ROMCP_ROMPATCHENL_ENABLE15_MASK          (0x8000U)
+#define ROMCP_ROMPATCHENL_ENABLE15_SHIFT         (15U)
+/*! ENABLE15 - Enable Address Comparator n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define ROMCP_ROMPATCHENL_ENABLE15(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE15_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE15_MASK)
+/*! @} */
+
+/*! @name ROMPATCHA - ROMC Address Registers */
+/*! @{ */
+
+#define ROMCP_ROMPATCHA_THUMBX_MASK              (0x1U)
+#define ROMCP_ROMPATCHA_THUMBX_SHIFT             (0U)
+/*! THUMBX - THUMB Comparator Select
+ *  0b0..ARM patch
+ *  0b1..THUMB patch (ignore if a data fix)
+ */
+#define ROMCP_ROMPATCHA_THUMBX(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_THUMBX_SHIFT)) & ROMCP_ROMPATCHA_THUMBX_MASK)
+
+#define ROMCP_ROMPATCHA_ADDRX_MASK               (0x7FFFFEU)
+#define ROMCP_ROMPATCHA_ADDRX_SHIFT              (1U)
+/*! ADDRX - Address Comparator Registers */
+#define ROMCP_ROMPATCHA_ADDRX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_ADDRX_SHIFT)) & ROMCP_ROMPATCHA_ADDRX_MASK)
+/*! @} */
+
+/* The count of ROMCP_ROMPATCHA */
+#define ROMCP_ROMPATCHA_COUNT                    (16U)
+
+/*! @name ROMPATCHSR - ROMC Status Register */
+/*! @{ */
+
+#define ROMCP_ROMPATCHSR_SOURCE_MASK             (0x3FU)
+#define ROMCP_ROMPATCHSR_SOURCE_SHIFT            (0U)
+/*! SOURCE - ROMC Source Number
+ *  0b000000..Address Comparator 0 matched
+ *  0b000001..Address Comparator 1 matched
+ *  0b001111..Address Comparator 15 matched
+ */
+#define ROMCP_ROMPATCHSR_SOURCE(x)               (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & ROMCP_ROMPATCHSR_SOURCE_MASK)
+
+#define ROMCP_ROMPATCHSR_SW_MASK                 (0x20000U)
+#define ROMCP_ROMPATCHSR_SW_SHIFT                (17U)
+/*! SW - ROMC AHB Multiple Address Comparator Match Indicator
+ *  0b0..No event or comparator collisions have occurred
+ *  0b1..A collision has occurred
+ */
+#define ROMCP_ROMPATCHSR_SW(x)                   (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SW_SHIFT)) & ROMCP_ROMPATCHSR_SW_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ROMCP_Register_Masks */
+
+
+/* ROMCP - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral ROMCP base address */
+  #define ROMCP_BASE                               (0x5013C000u)
+  /** Peripheral ROMCP base address */
+  #define ROMCP_BASE_NS                            (0x4013C000u)
+  /** Peripheral ROMCP base pointer */
+  #define ROMCP                                    ((ROMCP_Type *)ROMCP_BASE)
+  /** Peripheral ROMCP base pointer */
+  #define ROMCP_NS                                 ((ROMCP_Type *)ROMCP_BASE_NS)
+  /** Array initializer of ROMCP peripheral base addresses */
+  #define ROMCP_BASE_ADDRS                         { ROMCP_BASE }
+  /** Array initializer of ROMCP peripheral base pointers */
+  #define ROMCP_BASE_PTRS                          { ROMCP }
+  /** Array initializer of ROMCP peripheral base addresses */
+  #define ROMCP_BASE_ADDRS_NS                      { ROMCP_BASE_NS }
+  /** Array initializer of ROMCP peripheral base pointers */
+  #define ROMCP_BASE_PTRS_NS                       { ROMCP_NS }
+#else
+  /** Peripheral ROMCP base address */
+  #define ROMCP_BASE                               (0x4013C000u)
+  /** Peripheral ROMCP base pointer */
+  #define ROMCP                                    ((ROMCP_Type *)ROMCP_BASE)
+  /** Array initializer of ROMCP peripheral base addresses */
+  #define ROMCP_BASE_ADDRS                         { ROMCP_BASE }
+  /** Array initializer of ROMCP peripheral base pointers */
+  #define ROMCP_BASE_PTRS                          { ROMCP }
+#endif
+
+/*!
+ * @}
+ */ /* end of group ROMCP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RSTCTL0 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL0_Peripheral_Access_Layer RSTCTL0 Peripheral Access Layer
+ * @{
+ */
+
+/** RSTCTL0 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t PRSTCTL0;                          /**< Peripheral reset control 0, offset: 0x10 */
+  __IO uint32_t PRSTCTL1;                          /**< Peripheral reset control 1, offset: 0x14 */
+  __IO uint32_t PRSTCTL2;                          /**< Peripheral reset control 2, offset: 0x18 */
+       uint8_t RESERVED_1[36];
+  __IO uint32_t PRSTCTL0_SET;                      /**< Peripheral reset set 0, offset: 0x40 */
+  __O  uint32_t PRSTCTL1_SET;                      /**< Peripheral reset set 1, offset: 0x44 */
+  __O  uint32_t PRSTCTL2_SET;                      /**< Peripheral reset set 2, offset: 0x48 */
+       uint8_t RESERVED_2[36];
+  __O  uint32_t PRSTCTL0_CLR;                      /**< Peripheral reset clear 0, offset: 0x70 */
+  __O  uint32_t PRSTCTL1_CLR;                      /**< Peripheral reset clear 1, offset: 0x74 */
+  __O  uint32_t PRSTCTL2_CLR;                      /**< Peripheral reset clear 2, offset: 0x78 */
+} RSTCTL0_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RSTCTL0 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL0_Register_Masks RSTCTL0 Register Masks
+ * @{
+ */
+
+/*! @name PRSTCTL0 - Peripheral reset control 0 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL0_PQ_MASK                 (0x100U)
+#define RSTCTL0_PRSTCTL0_PQ_SHIFT                (8U)
+/*! PQ - pq reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_PQ(x)                   (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_PQ_SHIFT)) & RSTCTL0_PRSTCTL0_PQ_MASK)
+
+#define RSTCTL0_PRSTCTL0_PKC_MASK                (0x200U)
+#define RSTCTL0_PRSTCTL0_PKC_SHIFT               (9U)
+/*! PKC - pkc reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_PKC(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_PKC_SHIFT)) & RSTCTL0_PRSTCTL0_PKC_MASK)
+
+#define RSTCTL0_PRSTCTL0_ELS_MASK                (0x400U)
+#define RSTCTL0_PRSTCTL0_ELS_SHIFT               (10U)
+/*! ELS - els reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_ELS(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_ELS_SHIFT)) & RSTCTL0_PRSTCTL0_ELS_MASK)
+
+#define RSTCTL0_PRSTCTL0_PUF_MASK                (0x800U)
+#define RSTCTL0_PRSTCTL0_PUF_SHIFT               (11U)
+/*! PUF - puf reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_PUF(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_PUF_MASK)
+
+#define RSTCTL0_PRSTCTL0_FLEXSPI0_MASK           (0x10000U)
+#define RSTCTL0_PRSTCTL0_FLEXSPI0_SHIFT          (16U)
+/*! FLEXSPI0 - flexspi0 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_FLEXSPI0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_FLEXSPI0_SHIFT)) & RSTCTL0_PRSTCTL0_FLEXSPI0_MASK)
+
+#define RSTCTL0_PRSTCTL0_HPU_MASK                (0x100000U)
+#define RSTCTL0_PRSTCTL0_HPU_SHIFT               (20U)
+/*! HPU - hpu reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_HPU(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_HPU_SHIFT)) & RSTCTL0_PRSTCTL0_HPU_MASK)
+
+#define RSTCTL0_PRSTCTL0_USB_MASK                (0x400000U)
+#define RSTCTL0_PRSTCTL0_USB_SHIFT               (22U)
+/*! USB - usb reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_USB(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USB_SHIFT)) & RSTCTL0_PRSTCTL0_USB_MASK)
+
+#define RSTCTL0_PRSTCTL0_SCT_MASK                (0x1000000U)
+#define RSTCTL0_PRSTCTL0_SCT_SHIFT               (24U)
+/*! SCT - sct reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_SCT(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_SCT_MASK)
+
+#define RSTCTL0_PRSTCTL0_AON_MEM_MASK            (0x2000000U)
+#define RSTCTL0_PRSTCTL0_AON_MEM_SHIFT           (25U)
+/*! AON_MEM - aon_mem reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_AON_MEM(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_AON_MEM_SHIFT)) & RSTCTL0_PRSTCTL0_AON_MEM_MASK)
+
+#define RSTCTL0_PRSTCTL0_GDMA_MASK               (0x10000000U)
+#define RSTCTL0_PRSTCTL0_GDMA_SHIFT              (28U)
+/*! GDMA - gdma reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_GDMA(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_GDMA_SHIFT)) & RSTCTL0_PRSTCTL0_GDMA_MASK)
+
+#define RSTCTL0_PRSTCTL0_DMA0_MASK               (0x20000000U)
+#define RSTCTL0_PRSTCTL0_DMA0_SHIFT              (29U)
+/*! DMA0 - dma0 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_DMA0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_DMA0_SHIFT)) & RSTCTL0_PRSTCTL0_DMA0_MASK)
+
+#define RSTCTL0_PRSTCTL0_DMA1_MASK               (0x40000000U)
+#define RSTCTL0_PRSTCTL0_DMA1_SHIFT              (30U)
+/*! DMA1 - dma1 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_DMA1(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_DMA1_SHIFT)) & RSTCTL0_PRSTCTL0_DMA1_MASK)
+
+#define RSTCTL0_PRSTCTL0_SDIO_MASK               (0x80000000U)
+#define RSTCTL0_PRSTCTL0_SDIO_SHIFT              (31U)
+/*! SDIO - sdio reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL0_SDIO(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SDIO_SHIFT)) & RSTCTL0_PRSTCTL0_SDIO_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1 - Peripheral reset control 1 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL1_ELS_APB_MASK            (0x1U)
+#define RSTCTL0_PRSTCTL1_ELS_APB_SHIFT           (0U)
+/*! ELS_APB - els_apb reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_ELS_APB(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ELS_APB_SHIFT)) & RSTCTL0_PRSTCTL1_ELS_APB_MASK)
+
+#define RSTCTL0_PRSTCTL1_ELS_GDET_REF_RST_N_MASK (0x2U)
+#define RSTCTL0_PRSTCTL1_ELS_GDET_REF_RST_N_SHIFT (1U)
+/*! ELS_GDET_REF_RST_N - els_gdet_ref_rst_n control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_ELS_GDET_REF_RST_N(x)   (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ELS_GDET_REF_RST_N_SHIFT)) & RSTCTL0_PRSTCTL1_ELS_GDET_REF_RST_N_MASK)
+
+#define RSTCTL0_PRSTCTL1_SDIO_SLV_MASK           (0x4U)
+#define RSTCTL0_PRSTCTL1_SDIO_SLV_SHIFT          (2U)
+/*! SDIO_SLV - sdio_slv reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_SDIO_SLV(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SDIO_SLV_SHIFT)) & RSTCTL0_PRSTCTL1_SDIO_SLV_MASK)
+
+#define RSTCTL0_PRSTCTL1_GAU_MASK                (0x10000U)
+#define RSTCTL0_PRSTCTL1_GAU_SHIFT               (16U)
+/*! GAU - gau reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_GAU(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_GAU_SHIFT)) & RSTCTL0_PRSTCTL1_GAU_MASK)
+
+#define RSTCTL0_PRSTCTL1_OTP_MASK                (0x20000U)
+#define RSTCTL0_PRSTCTL1_OTP_SHIFT               (17U)
+/*! OTP - otp reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_OTP(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_OTP_SHIFT)) & RSTCTL0_PRSTCTL1_OTP_MASK)
+
+#define RSTCTL0_PRSTCTL1_SECURE_GPIO_MASK        (0x1000000U)
+#define RSTCTL0_PRSTCTL1_SECURE_GPIO_SHIFT       (24U)
+/*! SECURE_GPIO - secure_gpio reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_SECURE_GPIO(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SECURE_GPIO_SHIFT)) & RSTCTL0_PRSTCTL1_SECURE_GPIO_MASK)
+
+#define RSTCTL0_PRSTCTL1_ENET_IPG_MASK           (0x2000000U)
+#define RSTCTL0_PRSTCTL1_ENET_IPG_SHIFT          (25U)
+/*! ENET_IPG - enet_ipg reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_ENET_IPG(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ENET_IPG_SHIFT)) & RSTCTL0_PRSTCTL1_ENET_IPG_MASK)
+
+#define RSTCTL0_PRSTCTL1_ENET_IPG_S_MASK         (0x4000000U)
+#define RSTCTL0_PRSTCTL1_ENET_IPG_S_SHIFT        (26U)
+/*! ENET_IPG_S - enet_ipg_s reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_ENET_IPG_S(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ENET_IPG_S_SHIFT)) & RSTCTL0_PRSTCTL1_ENET_IPG_S_MASK)
+
+#define RSTCTL0_PRSTCTL1_TRNG_MASK               (0x8000000U)
+#define RSTCTL0_PRSTCTL1_TRNG_SHIFT              (27U)
+/*! TRNG - trng reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL1_TRNG(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_TRNG_SHIFT)) & RSTCTL0_PRSTCTL1_TRNG_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2 - Peripheral reset control 2 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL2_UTICK_MASK              (0x1U)
+#define RSTCTL0_PRSTCTL2_UTICK_SHIFT             (0U)
+/*! UTICK - utick reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL2_UTICK(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_UTICK_SHIFT)) & RSTCTL0_PRSTCTL2_UTICK_MASK)
+
+#define RSTCTL0_PRSTCTL2_WWDT0_MASK              (0x2U)
+#define RSTCTL0_PRSTCTL2_WWDT0_SHIFT             (1U)
+/*! WWDT0 - wwdt0 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL2_WWDT0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_WWDT0_MASK)
+
+#define RSTCTL0_PRSTCTL2_USIM_MASK               (0x4U)
+#define RSTCTL0_PRSTCTL2_USIM_SHIFT              (2U)
+/*! USIM - usim reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL2_USIM(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_USIM_SHIFT)) & RSTCTL0_PRSTCTL2_USIM_MASK)
+
+#define RSTCTL0_PRSTCTL2_FREEMRT_MASK            (0x4000000U)
+#define RSTCTL0_PRSTCTL2_FREEMRT_SHIFT           (26U)
+/*! FREEMRT - freemrt reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL2_FREEMRT(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_FREEMRT_SHIFT)) & RSTCTL0_PRSTCTL2_FREEMRT_MASK)
+
+#define RSTCTL0_PRSTCTL2_LCDIC_MASK              (0x8000000U)
+#define RSTCTL0_PRSTCTL2_LCDIC_SHIFT             (27U)
+/*! LCDIC - lcdic reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL0_PRSTCTL2_LCDIC(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_LCDIC_SHIFT)) & RSTCTL0_PRSTCTL2_LCDIC_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_SET - Peripheral reset set 0 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL0_SET_PQ_MASK             (0x100U)
+#define RSTCTL0_PRSTCTL0_SET_PQ_SHIFT            (8U)
+/*! PQ - pq reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_PQ(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_PQ_SHIFT)) & RSTCTL0_PRSTCTL0_SET_PQ_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_PKC_MASK            (0x200U)
+#define RSTCTL0_PRSTCTL0_SET_PKC_SHIFT           (9U)
+/*! PKC - pkc reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_PKC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_PKC_SHIFT)) & RSTCTL0_PRSTCTL0_SET_PKC_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_ELS_MASK            (0x400U)
+#define RSTCTL0_PRSTCTL0_SET_ELS_SHIFT           (10U)
+/*! ELS - els reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_ELS(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_ELS_SHIFT)) & RSTCTL0_PRSTCTL0_SET_ELS_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_PUF_MASK            (0x800U)
+#define RSTCTL0_PRSTCTL0_SET_PUF_SHIFT           (11U)
+/*! PUF - puf reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_PUF(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_SET_PUF_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_MASK       (0x10000U)
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_SHIFT      (16U)
+/*! FLEXSPI0 - flexspi0 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_FLEXSPI0_SHIFT)) & RSTCTL0_PRSTCTL0_SET_FLEXSPI0_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_HPU_MASK            (0x100000U)
+#define RSTCTL0_PRSTCTL0_SET_HPU_SHIFT           (20U)
+/*! HPU - hpu reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_HPU(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_HPU_SHIFT)) & RSTCTL0_PRSTCTL0_SET_HPU_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_USB_MASK            (0x400000U)
+#define RSTCTL0_PRSTCTL0_SET_USB_SHIFT           (22U)
+/*! USB - usb reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_USB(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USB_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USB_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_SCT_MASK            (0x1000000U)
+#define RSTCTL0_PRSTCTL0_SET_SCT_SHIFT           (24U)
+/*! SCT - sct reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_SCT(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_SET_SCT_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_AON_MEM_MASK        (0x2000000U)
+#define RSTCTL0_PRSTCTL0_SET_AON_MEM_SHIFT       (25U)
+/*! AON_MEM - aon_mem reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_AON_MEM(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_AON_MEM_SHIFT)) & RSTCTL0_PRSTCTL0_SET_AON_MEM_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_GDMA_MASK           (0x10000000U)
+#define RSTCTL0_PRSTCTL0_SET_GDMA_SHIFT          (28U)
+/*! GDMA - gdma reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_GDMA(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_GDMA_SHIFT)) & RSTCTL0_PRSTCTL0_SET_GDMA_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_DMA0_MASK           (0x20000000U)
+#define RSTCTL0_PRSTCTL0_SET_DMA0_SHIFT          (29U)
+/*! DMA0 - dma0 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_DMA0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_DMA0_SHIFT)) & RSTCTL0_PRSTCTL0_SET_DMA0_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_DMA1_MASK           (0x40000000U)
+#define RSTCTL0_PRSTCTL0_SET_DMA1_SHIFT          (30U)
+/*! DMA1 - dma1 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_DMA1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_DMA1_SHIFT)) & RSTCTL0_PRSTCTL0_SET_DMA1_MASK)
+
+#define RSTCTL0_PRSTCTL0_SET_SDIO_MASK           (0x80000000U)
+#define RSTCTL0_PRSTCTL0_SET_SDIO_SHIFT          (31U)
+/*! SDIO - sdio reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_SDIO(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_SDIO_SHIFT)) & RSTCTL0_PRSTCTL0_SET_SDIO_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_SET - Peripheral reset set 1 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL1_SET_ELS_APB_MASK        (0x1U)
+#define RSTCTL0_PRSTCTL1_SET_ELS_APB_SHIFT       (0U)
+/*! ELS_APB - els_apb reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_ELS_APB(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ELS_APB_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ELS_APB_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_ELS_GDET_REF_RST_N_MASK (0x2U)
+#define RSTCTL0_PRSTCTL1_SET_ELS_GDET_REF_RST_N_SHIFT (1U)
+/*! ELS_GDET_REF_RST_N - els_gdet_ref_rst_n reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_ELS_GDET_REF_RST_N(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ELS_GDET_REF_RST_N_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ELS_GDET_REF_RST_N_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_SDIO_SLV_MASK       (0x4U)
+#define RSTCTL0_PRSTCTL1_SET_SDIO_SLV_SHIFT      (2U)
+/*! SDIO_SLV - sdio_slv reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_SDIO_SLV(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SDIO_SLV_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SDIO_SLV_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_GAU_MASK            (0x10000U)
+#define RSTCTL0_PRSTCTL1_SET_GAU_SHIFT           (16U)
+/*! GAU - gau reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_GAU(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_GAU_SHIFT)) & RSTCTL0_PRSTCTL1_SET_GAU_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_OTP_MASK            (0x20000U)
+#define RSTCTL0_PRSTCTL1_SET_OTP_SHIFT           (17U)
+/*! OTP - otp reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_OTP(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_OTP_SHIFT)) & RSTCTL0_PRSTCTL1_SET_OTP_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_SECURE_GPIO_MASK    (0x1000000U)
+#define RSTCTL0_PRSTCTL1_SET_SECURE_GPIO_SHIFT   (24U)
+/*! SECURE_GPIO - secure_gpio reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_SECURE_GPIO(x)      (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SECURE_GPIO_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SECURE_GPIO_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_ENET_IPG_MASK       (0x2000000U)
+#define RSTCTL0_PRSTCTL1_SET_ENET_IPG_SHIFT      (25U)
+/*! ENET_IPG - enet_ipg reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_ENET_IPG(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ENET_IPG_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ENET_IPG_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_ENET_IPG_S_MASK     (0x4000000U)
+#define RSTCTL0_PRSTCTL1_SET_ENET_IPG_S_SHIFT    (26U)
+/*! ENET_IPG_S - enet_ipg_s reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_ENET_IPG_S(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ENET_IPG_S_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ENET_IPG_S_MASK)
+
+#define RSTCTL0_PRSTCTL1_SET_TRNG_MASK           (0x8000000U)
+#define RSTCTL0_PRSTCTL1_SET_TRNG_SHIFT          (27U)
+/*! TRNG - trng reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_TRNG(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_TRNG_SHIFT)) & RSTCTL0_PRSTCTL1_SET_TRNG_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_SET - Peripheral reset set 2 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL2_SET_UTICK_MASK          (0x1U)
+#define RSTCTL0_PRSTCTL2_SET_UTICK_SHIFT         (0U)
+/*! UTICK - utick reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_SET_UTICK(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_UTICK_SHIFT)) & RSTCTL0_PRSTCTL2_SET_UTICK_MASK)
+
+#define RSTCTL0_PRSTCTL2_SET_WWDT0_MASK          (0x2U)
+#define RSTCTL0_PRSTCTL2_SET_WWDT0_SHIFT         (1U)
+/*! WWDT0 - wwdt0 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_SET_WWDT0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_WWDT0_MASK)
+
+#define RSTCTL0_PRSTCTL2_SET_USIM_MASK           (0x4U)
+#define RSTCTL0_PRSTCTL2_SET_USIM_SHIFT          (2U)
+/*! USIM - usim reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_SET_USIM(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_USIM_SHIFT)) & RSTCTL0_PRSTCTL2_SET_USIM_MASK)
+
+#define RSTCTL0_PRSTCTL2_SET_FREEMRT_MASK        (0x4000000U)
+#define RSTCTL0_PRSTCTL2_SET_FREEMRT_SHIFT       (26U)
+/*! FREEMRT - freemrt reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_SET_FREEMRT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_FREEMRT_SHIFT)) & RSTCTL0_PRSTCTL2_SET_FREEMRT_MASK)
+
+#define RSTCTL0_PRSTCTL2_SET_LCDIC_MASK          (0x8000000U)
+#define RSTCTL0_PRSTCTL2_SET_LCDIC_SHIFT         (27U)
+/*! LCDIC - lcdic reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_SET_LCDIC(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_LCDIC_SHIFT)) & RSTCTL0_PRSTCTL2_SET_LCDIC_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_CLR - Peripheral reset clear 0 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL0_CLR_PQ_MASK             (0x100U)
+#define RSTCTL0_PRSTCTL0_CLR_PQ_SHIFT            (8U)
+/*! PQ - pq reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_PQ(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_PQ_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_PQ_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_PKC_MASK            (0x200U)
+#define RSTCTL0_PRSTCTL0_CLR_PKC_SHIFT           (9U)
+/*! PKC - pkc reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_PKC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_PKC_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_PKC_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_ELS_MASK            (0x400U)
+#define RSTCTL0_PRSTCTL0_CLR_ELS_SHIFT           (10U)
+/*! ELS - els reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_ELS(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_ELS_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_ELS_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_PUF_MASK            (0x800U)
+#define RSTCTL0_PRSTCTL0_CLR_PUF_SHIFT           (11U)
+/*! PUF - puf reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_PUF(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_PUF_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_MASK       (0x10000U)
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_SHIFT      (16U)
+/*! FLEXSPI0 - flexspi0 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_HPU_MASK            (0x100000U)
+#define RSTCTL0_PRSTCTL0_CLR_HPU_SHIFT           (20U)
+/*! HPU - hpu reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_HPU(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_HPU_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_HPU_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_USB_MASK            (0x400000U)
+#define RSTCTL0_PRSTCTL0_CLR_USB_SHIFT           (22U)
+/*! USB - usb reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_USB(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USB_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USB_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_SCT_MASK            (0x1000000U)
+#define RSTCTL0_PRSTCTL0_CLR_SCT_SHIFT           (24U)
+/*! SCT - sct reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_SCT(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_SCT_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_AON_MEM_MASK        (0x2000000U)
+#define RSTCTL0_PRSTCTL0_CLR_AON_MEM_SHIFT       (25U)
+/*! AON_MEM - aon_mem reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_AON_MEM(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_AON_MEM_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_AON_MEM_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_GDMA_MASK           (0x10000000U)
+#define RSTCTL0_PRSTCTL0_CLR_GDMA_SHIFT          (28U)
+/*! GDMA - gdma reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_GDMA(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_GDMA_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_GDMA_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_DMA0_MASK           (0x20000000U)
+#define RSTCTL0_PRSTCTL0_CLR_DMA0_SHIFT          (29U)
+/*! DMA0 - dma0 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_DMA0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_DMA0_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_DMA0_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_DMA1_MASK           (0x40000000U)
+#define RSTCTL0_PRSTCTL0_CLR_DMA1_SHIFT          (30U)
+/*! DMA1 - dma1 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_DMA1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_DMA1_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_DMA1_MASK)
+
+#define RSTCTL0_PRSTCTL0_CLR_SDIO_MASK           (0x80000000U)
+#define RSTCTL0_PRSTCTL0_CLR_SDIO_SHIFT          (31U)
+/*! SDIO - sdio reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_SDIO(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_SDIO_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_SDIO_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_CLR - Peripheral reset clear 1 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL1_CLR_ELS_APB_MASK        (0x1U)
+#define RSTCTL0_PRSTCTL1_CLR_ELS_APB_SHIFT       (0U)
+/*! ELS_APB - els_apb reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_ELS_APB(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ELS_APB_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ELS_APB_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_ELS_GDET_REF_RST_N_MASK (0x2U)
+#define RSTCTL0_PRSTCTL1_CLR_ELS_GDET_REF_RST_N_SHIFT (1U)
+/*! ELS_GDET_REF_RST_N - els_gdet_ref_rst_n reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_ELS_GDET_REF_RST_N(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ELS_GDET_REF_RST_N_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ELS_GDET_REF_RST_N_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_SDIO_SLV_MASK       (0x4U)
+#define RSTCTL0_PRSTCTL1_CLR_SDIO_SLV_SHIFT      (2U)
+/*! SDIO_SLV - sdio_slv reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_SDIO_SLV(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SDIO_SLV_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SDIO_SLV_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_GAU_MASK            (0x10000U)
+#define RSTCTL0_PRSTCTL1_CLR_GAU_SHIFT           (16U)
+/*! GAU - gau reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_GAU(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_GAU_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_GAU_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_OTP_MASK            (0x20000U)
+#define RSTCTL0_PRSTCTL1_CLR_OTP_SHIFT           (17U)
+/*! OTP - otp reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_OTP(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_OTP_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_OTP_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_SECURE_GPIO_MASK    (0x1000000U)
+#define RSTCTL0_PRSTCTL1_CLR_SECURE_GPIO_SHIFT   (24U)
+/*! SECURE_GPIO - secure_gpio reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_SECURE_GPIO(x)      (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SECURE_GPIO_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SECURE_GPIO_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_ENET_IPG_MASK       (0x2000000U)
+#define RSTCTL0_PRSTCTL1_CLR_ENET_IPG_SHIFT      (25U)
+/*! ENET_IPG - enet_ipg reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_ENET_IPG(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ENET_IPG_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ENET_IPG_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_ENET_IPG_S_MASK     (0x4000000U)
+#define RSTCTL0_PRSTCTL1_CLR_ENET_IPG_S_SHIFT    (26U)
+/*! ENET_IPG_S - enet_ipg_s reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_ENET_IPG_S(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ENET_IPG_S_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ENET_IPG_S_MASK)
+
+#define RSTCTL0_PRSTCTL1_CLR_TRNG_MASK           (0x8000000U)
+#define RSTCTL0_PRSTCTL1_CLR_TRNG_SHIFT          (27U)
+/*! TRNG - trng reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_TRNG(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_TRNG_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_TRNG_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_CLR - Peripheral reset clear 2 */
+/*! @{ */
+
+#define RSTCTL0_PRSTCTL2_CLR_UTICK_MASK          (0x1U)
+#define RSTCTL0_PRSTCTL2_CLR_UTICK_SHIFT         (0U)
+/*! UTICK - utick reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_CLR_UTICK(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_UTICK_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_UTICK_MASK)
+
+#define RSTCTL0_PRSTCTL2_CLR_WWDT0_MASK          (0x2U)
+#define RSTCTL0_PRSTCTL2_CLR_WWDT0_SHIFT         (1U)
+/*! WWDT0 - wwdt0 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_CLR_WWDT0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_WWDT0_MASK)
+
+#define RSTCTL0_PRSTCTL2_CLR_USIM_MASK           (0x4U)
+#define RSTCTL0_PRSTCTL2_CLR_USIM_SHIFT          (2U)
+/*! USIM - usim reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_CLR_USIM(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_USIM_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_USIM_MASK)
+
+#define RSTCTL0_PRSTCTL2_CLR_FREEMRT_MASK        (0x4000000U)
+#define RSTCTL0_PRSTCTL2_CLR_FREEMRT_SHIFT       (26U)
+/*! FREEMRT - freemrt reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_CLR_FREEMRT(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_FREEMRT_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_FREEMRT_MASK)
+
+#define RSTCTL0_PRSTCTL2_CLR_LCDIC_MASK          (0x8000000U)
+#define RSTCTL0_PRSTCTL2_CLR_LCDIC_SHIFT         (27U)
+/*! LCDIC - lcdic reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_CLR_LCDIC(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_LCDIC_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_LCDIC_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RSTCTL0_Register_Masks */
+
+
+/* RSTCTL0 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral RSTCTL0 base address */
+  #define RSTCTL0_BASE                             (0x50000000u)
+  /** Peripheral RSTCTL0 base address */
+  #define RSTCTL0_BASE_NS                          (0x40000000u)
+  /** Peripheral RSTCTL0 base pointer */
+  #define RSTCTL0                                  ((RSTCTL0_Type *)RSTCTL0_BASE)
+  /** Peripheral RSTCTL0 base pointer */
+  #define RSTCTL0_NS                               ((RSTCTL0_Type *)RSTCTL0_BASE_NS)
+  /** Array initializer of RSTCTL0 peripheral base addresses */
+  #define RSTCTL0_BASE_ADDRS                       { RSTCTL0_BASE }
+  /** Array initializer of RSTCTL0 peripheral base pointers */
+  #define RSTCTL0_BASE_PTRS                        { RSTCTL0 }
+  /** Array initializer of RSTCTL0 peripheral base addresses */
+  #define RSTCTL0_BASE_ADDRS_NS                    { RSTCTL0_BASE_NS }
+  /** Array initializer of RSTCTL0 peripheral base pointers */
+  #define RSTCTL0_BASE_PTRS_NS                     { RSTCTL0_NS }
+#else
+  /** Peripheral RSTCTL0 base address */
+  #define RSTCTL0_BASE                             (0x40000000u)
+  /** Peripheral RSTCTL0 base pointer */
+  #define RSTCTL0                                  ((RSTCTL0_Type *)RSTCTL0_BASE)
+  /** Array initializer of RSTCTL0 peripheral base addresses */
+  #define RSTCTL0_BASE_ADDRS                       { RSTCTL0_BASE }
+  /** Array initializer of RSTCTL0 peripheral base pointers */
+  #define RSTCTL0_BASE_PTRS                        { RSTCTL0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group RSTCTL0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RSTCTL1 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL1_Peripheral_Access_Layer RSTCTL1 Peripheral Access Layer
+ * @{
+ */
+
+/** RSTCTL1 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t PRSTCTL0;                          /**< Peripheral reset control 0, offset: 0x10 */
+  __IO uint32_t PRSTCTL1;                          /**< Peripheral reset control 1, offset: 0x14 */
+  __IO uint32_t PRSTCTL2;                          /**< Peripheral reset control 2, offset: 0x18 */
+       uint8_t RESERVED_1[36];
+  __O  uint32_t PRSTCTL0_SET;                      /**< Peripheral reset set 0, offset: 0x40 */
+  __IO uint32_t PRSTCTL1_SET;                      /**< Peripheral reset set 1, offset: 0x44 */
+  __O  uint32_t PRSTCTL2_SET;                      /**< Peripheral reset set 2, offset: 0x48 */
+       uint8_t RESERVED_2[36];
+  __O  uint32_t PRSTCTL0_CLR;                      /**< Peripheral reset clear 0, offset: 0x70 */
+  __O  uint32_t PRSTCTL1_CLR;                      /**< Peripheral reset clear 1, offset: 0x74 */
+  __O  uint32_t PRSTCTL2_CLR;                      /**< Peripheral reset clear 2, offset: 0x78 */
+       uint8_t RESERVED_3[20];
+  __IO uint32_t SDIO;                              /**< SDIO sdclk_sw_rst_n control, offset: 0x90 */
+} RSTCTL1_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RSTCTL1 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL1_Register_Masks RSTCTL1 Register Masks
+ * @{
+ */
+
+/*! @name PRSTCTL0 - Peripheral reset control 0 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL0_FC0_MASK                (0x100U)
+#define RSTCTL1_PRSTCTL0_FC0_SHIFT               (8U)
+/*! FC0 - fc0 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL0_FC0(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FC0_SHIFT)) & RSTCTL1_PRSTCTL0_FC0_MASK)
+
+#define RSTCTL1_PRSTCTL0_FC1_MASK                (0x200U)
+#define RSTCTL1_PRSTCTL0_FC1_SHIFT               (9U)
+/*! FC1 - fc1 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL0_FC1(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FC1_SHIFT)) & RSTCTL1_PRSTCTL0_FC1_MASK)
+
+#define RSTCTL1_PRSTCTL0_FC2_MASK                (0x400U)
+#define RSTCTL1_PRSTCTL0_FC2_SHIFT               (10U)
+/*! FC2 - fc2 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL0_FC2(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FC2_SHIFT)) & RSTCTL1_PRSTCTL0_FC2_MASK)
+
+#define RSTCTL1_PRSTCTL0_FC3_MASK                (0x800U)
+#define RSTCTL1_PRSTCTL0_FC3_SHIFT               (11U)
+/*! FC3 - fc3 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL0_FC3(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FC3_SHIFT)) & RSTCTL1_PRSTCTL0_FC3_MASK)
+
+#define RSTCTL1_PRSTCTL0_FC14_MASK               (0x400000U)
+#define RSTCTL1_PRSTCTL0_FC14_SHIFT              (22U)
+/*! FC14 - fc14 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL0_FC14(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FC14_SHIFT)) & RSTCTL1_PRSTCTL0_FC14_MASK)
+
+#define RSTCTL1_PRSTCTL0_DMIC0_MASK              (0x1000000U)
+#define RSTCTL1_PRSTCTL0_DMIC0_SHIFT             (24U)
+/*! DMIC0 - dmic0 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL0_DMIC0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_DMIC0_MASK)
+
+#define RSTCTL1_PRSTCTL0_OSEVENTTIMER_MASK       (0x8000000U)
+#define RSTCTL1_PRSTCTL0_OSEVENTTIMER_SHIFT      (27U)
+/*! OSEVENTTIMER - oseventtimer reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL0_OSEVENTTIMER(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_OSEVENTTIMER_SHIFT)) & RSTCTL1_PRSTCTL0_OSEVENTTIMER_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1 - Peripheral reset control 1 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL1_HSGPIO0_MASK            (0x1U)
+#define RSTCTL1_PRSTCTL1_HSGPIO0_SHIFT           (0U)
+/*! HSGPIO0 - hsgpio0 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO0_MASK)
+
+#define RSTCTL1_PRSTCTL1_HSGPIO1_MASK            (0x2U)
+#define RSTCTL1_PRSTCTL1_HSGPIO1_SHIFT           (1U)
+/*! HSGPIO1 - hsgpio1 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO1_MASK)
+
+#define RSTCTL1_PRSTCTL1_CRC_MASK                (0x10000U)
+#define RSTCTL1_PRSTCTL1_CRC_SHIFT               (16U)
+/*! CRC - crc reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL1_CRC(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_CRC_MASK)
+
+#define RSTCTL1_PRSTCTL1_FREQME_MASK             (0x80000000U)
+#define RSTCTL1_PRSTCTL1_FREQME_SHIFT            (31U)
+/*! FREQME - freqme reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL1_FREQME(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_FREQME_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2 - Peripheral reset control 2 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL2_CT32B0_MASK             (0x1U)
+#define RSTCTL1_PRSTCTL2_CT32B0_SHIFT            (0U)
+/*! CT32B0 - ct32b0 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32B0(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32B0_SHIFT)) & RSTCTL1_PRSTCTL2_CT32B0_MASK)
+
+#define RSTCTL1_PRSTCTL2_CT32B1_MASK             (0x2U)
+#define RSTCTL1_PRSTCTL2_CT32B1_SHIFT            (1U)
+/*! CT32B1 - ct32b1 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32B1(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32B1_SHIFT)) & RSTCTL1_PRSTCTL2_CT32B1_MASK)
+
+#define RSTCTL1_PRSTCTL2_CT32B2_MASK             (0x4U)
+#define RSTCTL1_PRSTCTL2_CT32B2_SHIFT            (2U)
+/*! CT32B2 - ct32b2 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32B2(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32B2_SHIFT)) & RSTCTL1_PRSTCTL2_CT32B2_MASK)
+
+#define RSTCTL1_PRSTCTL2_CT32B3_MASK             (0x8U)
+#define RSTCTL1_PRSTCTL2_CT32B3_SHIFT            (3U)
+/*! CT32B3 - ct32b3 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32B3(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32B3_SHIFT)) & RSTCTL1_PRSTCTL2_CT32B3_MASK)
+
+#define RSTCTL1_PRSTCTL2_CT32B4_MASK             (0x10U)
+#define RSTCTL1_PRSTCTL2_CT32B4_SHIFT            (4U)
+/*! CT32B4 - ct32b4 reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32B4(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32B4_SHIFT)) & RSTCTL1_PRSTCTL2_CT32B4_MASK)
+
+#define RSTCTL1_PRSTCTL2_MRT_MASK                (0x100U)
+#define RSTCTL1_PRSTCTL2_MRT_SHIFT               (8U)
+/*! MRT - mrt reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_MRT(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_MRT_SHIFT)) & RSTCTL1_PRSTCTL2_MRT_MASK)
+
+#define RSTCTL1_PRSTCTL2_GPIO_INT_MASK           (0x40000000U)
+#define RSTCTL1_PRSTCTL2_GPIO_INT_SHIFT          (30U)
+/*! GPIO_INT - gpio_int reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_GPIO_INT(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_GPIO_INT_SHIFT)) & RSTCTL1_PRSTCTL2_GPIO_INT_MASK)
+
+#define RSTCTL1_PRSTCTL2_PMUX_MASK               (0x80000000U)
+#define RSTCTL1_PRSTCTL2_PMUX_SHIFT              (31U)
+/*! PMUX - pmux reset control
+ *  0b0..Clear reset
+ *  0b1..Set reset
+ */
+#define RSTCTL1_PRSTCTL2_PMUX(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_PMUX_SHIFT)) & RSTCTL1_PRSTCTL2_PMUX_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_SET - Peripheral reset set 0 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL0_SET_FC0_MASK            (0x100U)
+#define RSTCTL1_PRSTCTL0_SET_FC0_SHIFT           (8U)
+/*! FC0 - fc0 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_SET_FC0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FC0_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FC0_MASK)
+
+#define RSTCTL1_PRSTCTL0_SET_FC1_MASK            (0x200U)
+#define RSTCTL1_PRSTCTL0_SET_FC1_SHIFT           (9U)
+/*! FC1 - fc1 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_SET_FC1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FC1_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FC1_MASK)
+
+#define RSTCTL1_PRSTCTL0_SET_FC2_MASK            (0x400U)
+#define RSTCTL1_PRSTCTL0_SET_FC2_SHIFT           (10U)
+/*! FC2 - fc2 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_SET_FC2(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FC2_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FC2_MASK)
+
+#define RSTCTL1_PRSTCTL0_SET_FC3_MASK            (0x800U)
+#define RSTCTL1_PRSTCTL0_SET_FC3_SHIFT           (11U)
+/*! FC3 - fc3 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_SET_FC3(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FC3_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FC3_MASK)
+
+#define RSTCTL1_PRSTCTL0_SET_FC14_MASK           (0x400000U)
+#define RSTCTL1_PRSTCTL0_SET_FC14_SHIFT          (22U)
+/*! FC14 - fc14 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_SET_FC14(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FC14_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FC14_MASK)
+
+#define RSTCTL1_PRSTCTL0_SET_DMIC0_MASK          (0x1000000U)
+#define RSTCTL1_PRSTCTL0_SET_DMIC0_SHIFT         (24U)
+/*! DMIC0 - dmic0 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_SET_DMIC0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_SET_DMIC0_MASK)
+
+#define RSTCTL1_PRSTCTL0_SET_OSEVENTTIMER_MASK   (0x8000000U)
+#define RSTCTL1_PRSTCTL0_SET_OSEVENTTIMER_SHIFT  (27U)
+/*! OSEVENTTIMER - oseventtimer reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_SET_OSEVENTTIMER(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_OSEVENTTIMER_SHIFT)) & RSTCTL1_PRSTCTL0_SET_OSEVENTTIMER_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_SET - Peripheral reset set 1 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO0_MASK        (0x1U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO0_SHIFT       (0U)
+/*! HSGPIO0 - hsgpio0 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO0_MASK)
+
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO1_MASK        (0x2U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO1_SHIFT       (1U)
+/*! HSGPIO1 - hsgpio1 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO1_MASK)
+
+#define RSTCTL1_PRSTCTL1_SET_CRC_MASK            (0x10000U)
+#define RSTCTL1_PRSTCTL1_SET_CRC_SHIFT           (16U)
+/*! CRC - crc reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_SET_CRC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_SET_CRC_MASK)
+
+#define RSTCTL1_PRSTCTL1_SET_FREQME_MASK         (0x80000000U)
+#define RSTCTL1_PRSTCTL1_SET_FREQME_SHIFT        (31U)
+/*! FREQME - freqme reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_SET_FREQME(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_SET_FREQME_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_SET - Peripheral reset set 2 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL2_SET_CT32B0_MASK         (0x1U)
+#define RSTCTL1_PRSTCTL2_SET_CT32B0_SHIFT        (0U)
+/*! CT32B0 - ct32b0 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32B0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32B0_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32B0_MASK)
+
+#define RSTCTL1_PRSTCTL2_SET_CT32B1_MASK         (0x2U)
+#define RSTCTL1_PRSTCTL2_SET_CT32B1_SHIFT        (1U)
+/*! CT32B1 - ct32b1 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32B1(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32B1_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32B1_MASK)
+
+#define RSTCTL1_PRSTCTL2_SET_CT32B2_MASK         (0x4U)
+#define RSTCTL1_PRSTCTL2_SET_CT32B2_SHIFT        (2U)
+/*! CT32B2 - ct32b2 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32B2(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32B2_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32B2_MASK)
+
+#define RSTCTL1_PRSTCTL2_SET_CT32B3_MASK         (0x8U)
+#define RSTCTL1_PRSTCTL2_SET_CT32B3_SHIFT        (3U)
+/*! CT32B3 - ct32b3 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32B3(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32B3_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32B3_MASK)
+
+#define RSTCTL1_PRSTCTL2_SET_CT32B4_MASK         (0x10U)
+#define RSTCTL1_PRSTCTL2_SET_CT32B4_SHIFT        (4U)
+/*! CT32B4 - ct32b4 reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32B4(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32B4_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32B4_MASK)
+
+#define RSTCTL1_PRSTCTL2_SET_MRT_MASK            (0x100U)
+#define RSTCTL1_PRSTCTL2_SET_MRT_SHIFT           (8U)
+/*! MRT - mrt reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_MRT(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_MRT_SHIFT)) & RSTCTL1_PRSTCTL2_SET_MRT_MASK)
+
+#define RSTCTL1_PRSTCTL2_SET_GPIO_INT_MASK       (0x40000000U)
+#define RSTCTL1_PRSTCTL2_SET_GPIO_INT_SHIFT      (30U)
+/*! GPIO_INT - gpio_int reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_GPIO_INT(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_GPIO_INT_SHIFT)) & RSTCTL1_PRSTCTL2_SET_GPIO_INT_MASK)
+
+#define RSTCTL1_PRSTCTL2_SET_PMUX_MASK           (0x80000000U)
+#define RSTCTL1_PRSTCTL2_SET_PMUX_SHIFT          (31U)
+/*! PMUX - pmux reset set
+ *  0b0..No effect
+ *  0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_SET_PMUX(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_PMUX_SHIFT)) & RSTCTL1_PRSTCTL2_SET_PMUX_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_CLR - Peripheral reset clear 0 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL0_CLR_FC0_MASK            (0x100U)
+#define RSTCTL1_PRSTCTL0_CLR_FC0_SHIFT           (8U)
+/*! FC0 - fc0 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FC0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FC0_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FC0_MASK)
+
+#define RSTCTL1_PRSTCTL0_CLR_FC1_MASK            (0x200U)
+#define RSTCTL1_PRSTCTL0_CLR_FC1_SHIFT           (9U)
+/*! FC1 - fc1 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FC1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FC1_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FC1_MASK)
+
+#define RSTCTL1_PRSTCTL0_CLR_FC2_MASK            (0x400U)
+#define RSTCTL1_PRSTCTL0_CLR_FC2_SHIFT           (10U)
+/*! FC2 - fc2 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FC2(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FC2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FC2_MASK)
+
+#define RSTCTL1_PRSTCTL0_CLR_FC3_MASK            (0x800U)
+#define RSTCTL1_PRSTCTL0_CLR_FC3_SHIFT           (11U)
+/*! FC3 - fc3 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FC3(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FC3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FC3_MASK)
+
+#define RSTCTL1_PRSTCTL0_CLR_FC14_MASK           (0x400000U)
+#define RSTCTL1_PRSTCTL0_CLR_FC14_SHIFT          (22U)
+/*! FC14 - fc14 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FC14(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FC14_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FC14_MASK)
+
+#define RSTCTL1_PRSTCTL0_CLR_DMIC0_MASK          (0x1000000U)
+#define RSTCTL1_PRSTCTL0_CLR_DMIC0_SHIFT         (24U)
+/*! DMIC0 - dmic0 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_CLR_DMIC0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_DMIC0_MASK)
+
+#define RSTCTL1_PRSTCTL0_CLR_OSEVENTTIMER_MASK   (0x8000000U)
+#define RSTCTL1_PRSTCTL0_CLR_OSEVENTTIMER_SHIFT  (27U)
+/*! OSEVENTTIMER - oseventtimer reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL1_PRSTCTL0_CLR_OSEVENTTIMER(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_OSEVENTTIMER_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_OSEVENTTIMER_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_CLR - Peripheral reset clear 1 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0_MASK        (0x1U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0_SHIFT       (0U)
+/*! HSGPIO0 - hsgpio0 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO0_MASK)
+
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1_MASK        (0x2U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1_SHIFT       (1U)
+/*! HSGPIO1 - hsgpio1 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO1_MASK)
+
+#define RSTCTL1_PRSTCTL1_CLR_CRC_MASK            (0x10000U)
+#define RSTCTL1_PRSTCTL1_CLR_CRC_SHIFT           (16U)
+/*! CRC - crc reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_CLR_CRC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_CRC_MASK)
+
+#define RSTCTL1_PRSTCTL1_CLR_FREQME_MASK         (0x80000000U)
+#define RSTCTL1_PRSTCTL1_CLR_FREQME_SHIFT        (31U)
+/*! FREQME - freqme reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL1_PRSTCTL1_CLR_FREQME(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_FREQME_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_CLR - Peripheral reset clear 2 */
+/*! @{ */
+
+#define RSTCTL1_PRSTCTL2_CLR_CT32B0_MASK         (0x1U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32B0_SHIFT        (0U)
+/*! CT32B0 - ct32b0 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32B0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32B0_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32B0_MASK)
+
+#define RSTCTL1_PRSTCTL2_CLR_CT32B1_MASK         (0x2U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32B1_SHIFT        (1U)
+/*! CT32B1 - ct32b1 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32B1(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32B1_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32B1_MASK)
+
+#define RSTCTL1_PRSTCTL2_CLR_CT32B2_MASK         (0x4U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32B2_SHIFT        (2U)
+/*! CT32B2 - ct32b2 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32B2(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32B2_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32B2_MASK)
+
+#define RSTCTL1_PRSTCTL2_CLR_CT32B3_MASK         (0x8U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32B3_SHIFT        (3U)
+/*! CT32B3 - ct32b3 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32B3(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32B3_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32B3_MASK)
+
+#define RSTCTL1_PRSTCTL2_CLR_CT32B4_MASK         (0x10U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32B4_SHIFT        (4U)
+/*! CT32B4 - ct32b4 reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32B4(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32B4_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32B4_MASK)
+
+#define RSTCTL1_PRSTCTL2_CLR_MRT_MASK            (0x100U)
+#define RSTCTL1_PRSTCTL2_CLR_MRT_SHIFT           (8U)
+/*! MRT - mrt reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_MRT(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_MRT_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_MRT_MASK)
+
+#define RSTCTL1_PRSTCTL2_CLR_GPIO_INT_MASK       (0x40000000U)
+#define RSTCTL1_PRSTCTL2_CLR_GPIO_INT_SHIFT      (30U)
+/*! GPIO_INT - gpio_int reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_GPIO_INT(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_GPIO_INT_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_GPIO_INT_MASK)
+
+#define RSTCTL1_PRSTCTL2_CLR_PMUX_MASK           (0x80000000U)
+#define RSTCTL1_PRSTCTL2_CLR_PMUX_SHIFT          (31U)
+/*! PMUX - pmux reset clear
+ *  0b0..No effect
+ *  0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL1_PRSTCTL2_CLR_PMUX(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_PMUX_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_PMUX_MASK)
+/*! @} */
+
+/*! @name SDIO - SDIO sdclk_sw_rst_n control */
+/*! @{ */
+
+#define RSTCTL1_SDIO_SDCLK_SW_RST_N_MASK         (0x1U)
+#define RSTCTL1_SDIO_SDCLK_SW_RST_N_SHIFT        (0U)
+/*! SDCLK_SW_RST_N - 0: sw reset 1: reset release */
+#define RSTCTL1_SDIO_SDCLK_SW_RST_N(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SDIO_SDCLK_SW_RST_N_SHIFT)) & RSTCTL1_SDIO_SDCLK_SW_RST_N_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RSTCTL1_Register_Masks */
+
+
+/* RSTCTL1 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral RSTCTL1 base address */
+  #define RSTCTL1_BASE                             (0x50020000u)
+  /** Peripheral RSTCTL1 base address */
+  #define RSTCTL1_BASE_NS                          (0x40020000u)
+  /** Peripheral RSTCTL1 base pointer */
+  #define RSTCTL1                                  ((RSTCTL1_Type *)RSTCTL1_BASE)
+  /** Peripheral RSTCTL1 base pointer */
+  #define RSTCTL1_NS                               ((RSTCTL1_Type *)RSTCTL1_BASE_NS)
+  /** Array initializer of RSTCTL1 peripheral base addresses */
+  #define RSTCTL1_BASE_ADDRS                       { RSTCTL1_BASE }
+  /** Array initializer of RSTCTL1 peripheral base pointers */
+  #define RSTCTL1_BASE_PTRS                        { RSTCTL1 }
+  /** Array initializer of RSTCTL1 peripheral base addresses */
+  #define RSTCTL1_BASE_ADDRS_NS                    { RSTCTL1_BASE_NS }
+  /** Array initializer of RSTCTL1 peripheral base pointers */
+  #define RSTCTL1_BASE_PTRS_NS                     { RSTCTL1_NS }
+#else
+  /** Peripheral RSTCTL1 base address */
+  #define RSTCTL1_BASE                             (0x40020000u)
+  /** Peripheral RSTCTL1 base pointer */
+  #define RSTCTL1                                  ((RSTCTL1_Type *)RSTCTL1_BASE)
+  /** Array initializer of RSTCTL1 peripheral base addresses */
+  #define RSTCTL1_BASE_ADDRS                       { RSTCTL1_BASE }
+  /** Array initializer of RSTCTL1 peripheral base pointers */
+  #define RSTCTL1_BASE_PTRS                        { RSTCTL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group RSTCTL1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< RTC control register, offset: 0x0 */
+  __IO uint32_t MATCH;                             /**< RTC match register, offset: 0x4 */
+  __IO uint32_t COUNT;                             /**< RTC counter register, offset: 0x8 */
+  __IO uint32_t WAKE;                              /**< High-resolution/wake-up timer control register, offset: 0xC */
+  __I  uint32_t SUBSEC;                            /**< RTC Sub-second Counter register, offset: 0x10 */
+       uint8_t RESERVED_0[108];
+  __IO uint32_t GPREG[8];                          /**< General Purpose register, array offset: 0x80, array step: 0x4 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC control register */
+/*! @{ */
+
+#define RTC_CTRL_SWRESET_MASK                    (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT                   (0U)
+/*! SWRESET - Software reset control
+ *  0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
+ *  0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value
+ *       except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes
+ *       to set any of the other bits within this register. Do not attempt to write to any bits of this register at
+ *       the same time that the reset bit is being cleared.
+ */
+#define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+
+#define RTC_CTRL_OFD_MASK                        (0x2U)
+#define RTC_CTRL_OFD_SHIFT                       (1U)
+/*! OFD - Oscillator fail detect status.
+ *  0b0..Run. The RTC oscillator is running properly. Writing a 0 has no effect.
+ *  0b1..Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit.
+ */
+#define RTC_CTRL_OFD(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_OFD_SHIFT)) & RTC_CTRL_OFD_MASK)
+
+#define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
+/*! ALARM1HZ - RTC 1 Hz timer alarm flag status.
+ *  0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
+ *  0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt
+ *       request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
+ */
+#define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+
+#define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
+/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.
+ *  0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
+ *  0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
+ *       interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
+ */
+#define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+
+#define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
+/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.
+ *  0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
+ *  0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.
+ */
+#define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+
+#define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
+/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.
+ *  0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
+ *  0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.
+ */
+#define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+
+#define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
+/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz
+ *    timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
+ *  0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
+ *  0b1..Enable. The 1 kHz RTC timer is enabled.
+ */
+#define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+
+#define RTC_CTRL_RTC_EN_MASK                     (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT                    (7U)
+/*! RTC_EN - RTC enable.
+ *  0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should
+ *       be 0 when writing to load a value in the RTC counter register.
+ *  0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate
+ *       operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the
+ *       high-resolution, 1 kHz clock, set bit 6 in this register.
+ */
+#define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+
+#define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
+/*! RTC_OSC_PD - The RTC oscillator enable
+ *  0b0..The RTC oscillator is enabled. This bit must be cleared in order for the RTC module to function
+ *  0b1..The RTC oscillator is shut-off to reserve power consumption. RTC operation is disabled.
+ */
+#define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+
+#define RTC_CTRL_RTC_OSC_BYPASS_MASK             (0x200U)
+#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT            (9U)
+/*! RTC_OSC_BYPASS - The RTC Oscillator bypass
+ *  0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTLALIN and RTC_XTALOUT pins.
+ *  0b1..The RTC oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin.
+ */
+#define RTC_CTRL_RTC_OSC_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK)
+
+#define RTC_CTRL_RTC_SUBSEC_ENA_MASK             (0x400U)
+#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT            (10U)
+/*! RTC_SUBSEC_ENA - The 32 KHz sub-second counter enable
+ *  0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD
+ *       reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second
+ *       counter, this bit will always read-back as a '0'
+ *  0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting will commence on the start of the
+ *       first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7)
+ *       has been set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever
+ *       the chip exits deep_powerdown mode.
+ */
+#define RTC_CTRL_RTC_SUBSEC_ENA(x)               (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK)
+
+#define RTC_CTRL_RTC_OSC_LOADCAP_MASK            (0xF0000000U)
+#define RTC_CTRL_RTC_OSC_LOADCAP_SHIFT           (28U)
+/*! RTC_OSC_LOADCAP - capacitive load selection */
+#define RTC_CTRL_RTC_OSC_LOADCAP(x)              (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_LOADCAP_SHIFT)) & RTC_CTRL_RTC_OSC_LOADCAP_MASK)
+/*! @} */
+
+/*! @name MATCH - RTC match register */
+/*! @{ */
+
+#define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT                   (0U)
+/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the
+ *    alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
+ */
+#define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+/*! @} */
+
+/*! @name COUNT - RTC counter register */
+/*! @{ */
+
+#define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT                      (0U)
+/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial
+ *    value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC
+ *    Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this
+ *    register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after
+ *    the RTC_EN bit is set.
+ */
+#define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+/*! @} */
+
+/*! @name WAKE - High-resolution/wake-up timer control register */
+/*! @{ */
+
+#define RTC_WAKE_VAL_MASK                        (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT                       (0U)
+/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads
+ *    a start count value into the wake-up timer and initializes a count-down sequence. Do not write
+ *    to this register while counting is in progress.
+ */
+#define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+/*! @} */
+
+/*! @name SUBSEC - RTC Sub-second Counter register */
+/*! @{ */
+
+#define RTC_SUBSEC_RTC_SUBSEC_MASK               (0x7FFFU)
+#define RTC_SUBSEC_RTC_SUBSEC_SHIFT              (0U)
+/*! RTC_SUBSEC - A read reflects the current value of the 32Khz sub-second counter. This counter
+ *    will be cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a
+ *    32 KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is
+ *    set. This counter must be re-enabled after exiting deep_powerdown mode or after the main RTC
+ *    module has been disabled and re-enabled. On modules not equipped with a sub-second counter,
+ *    this register will read-back as all zeroes.
+ */
+#define RTC_SUBSEC_RTC_SUBSEC(x)                 (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_RTC_SUBSEC_SHIFT)) & RTC_SUBSEC_RTC_SUBSEC_MASK)
+/*! @} */
+
+/*! @name GPREG - General Purpose register */
+/*! @{ */
+
+#define RTC_GPREG_GPDATA_MASK                    (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT                   (0U)
+/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. */
+#define RTC_GPREG_GPDATA(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+/*! @} */
+
+/* The count of RTC_GPREG */
+#define RTC_GPREG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral RTC base address */
+  #define RTC_BASE                                 (0x50030000u)
+  /** Peripheral RTC base address */
+  #define RTC_BASE_NS                              (0x40030000u)
+  /** Peripheral RTC base pointer */
+  #define RTC                                      ((RTC_Type *)RTC_BASE)
+  /** Peripheral RTC base pointer */
+  #define RTC_NS                                   ((RTC_Type *)RTC_BASE_NS)
+  /** Array initializer of RTC peripheral base addresses */
+  #define RTC_BASE_ADDRS                           { RTC_BASE }
+  /** Array initializer of RTC peripheral base pointers */
+  #define RTC_BASE_PTRS                            { RTC }
+  /** Array initializer of RTC peripheral base addresses */
+  #define RTC_BASE_ADDRS_NS                        { RTC_BASE_NS }
+  /** Array initializer of RTC peripheral base pointers */
+  #define RTC_BASE_PTRS_NS                         { RTC_NS }
+#else
+  /** Peripheral RTC base address */
+  #define RTC_BASE                                 (0x40030000u)
+  /** Peripheral RTC base pointer */
+  #define RTC                                      ((RTC_Type *)RTC_BASE)
+  /** Array initializer of RTC peripheral base addresses */
+  #define RTC_BASE_ADDRS                           { RTC_BASE }
+  /** Array initializer of RTC peripheral base pointers */
+  #define RTC_BASE_PTRS                            { RTC }
+#endif
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SCT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONFIG;                            /**< SCTimer Configuration, offset: 0x0 */
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t CTRLL;                             /**< SCT_CTRLL register, offset: 0x4 */
+      __IO uint16_t CTRLH;                             /**< SCT_CTRLH register, offset: 0x6 */
+    } CTRL_ACCESS16BIT;
+    __IO uint32_t CTRL;                              /**< SCT Control, offset: 0x4 */
+  };
+  union {                                          /* offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+      __IO uint16_t LIMITL;                            /**< SCT_LIMITL register, offset: 0x8 */
+      __IO uint16_t LIMITH;                            /**< SCT_LIMITH register, offset: 0xA */
+    } LIMIT_ACCESS16BIT;
+    __IO uint32_t LIMIT;                             /**< SCT Limit Event Select, offset: 0x8 */
+  };
+  union {                                          /* offset: 0xC */
+    struct {                                         /* offset: 0xC */
+      __IO uint16_t HALTL;                             /**< SCT_HALTL register, offset: 0xC */
+      __IO uint16_t HALTH;                             /**< SCT_HALTH register, offset: 0xE */
+    } HALT_ACCESS16BIT;
+    __IO uint32_t HALT;                              /**< Halt Event Select, offset: 0xC */
+  };
+  union {                                          /* offset: 0x10 */
+    struct {                                         /* offset: 0x10 */
+      __IO uint16_t STOPL;                             /**< SCT_STOPL register, offset: 0x10 */
+      __IO uint16_t STOPH;                             /**< SCT_STOPH register, offset: 0x12 */
+    } STOP_ACCESS16BIT;
+    __IO uint32_t STOP;                              /**< Stop Event Select, offset: 0x10 */
+  };
+  union {                                          /* offset: 0x14 */
+    struct {                                         /* offset: 0x14 */
+      __IO uint16_t STARTL;                            /**< SCT_STARTL register, offset: 0x14 */
+      __IO uint16_t STARTH;                            /**< SCT_STARTH register, offset: 0x16 */
+    } START_ACCESS16BIT;
+    __IO uint32_t START;                             /**< Start Event Select, offset: 0x14 */
+  };
+       uint8_t RESERVED_0[40];
+  union {                                          /* offset: 0x40 */
+    struct {                                         /* offset: 0x40 */
+      __IO uint16_t COUNTL;                            /**< SCT_COUNTL register, offset: 0x40 */
+      __IO uint16_t COUNTH;                            /**< SCT_COUNTH register, offset: 0x42 */
+    } COUNT_ACCESS16BIT;
+    __IO uint32_t COUNT;                             /**< Counter, offset: 0x40 */
+  };
+  union {                                          /* offset: 0x44 */
+    struct {                                         /* offset: 0x44 */
+      __IO uint16_t STATEL;                            /**< SCT_STATEL register, offset: 0x44 */
+      __IO uint16_t STATEH;                            /**< SCT_STATEH register, offset: 0x46 */
+    } STATE_ACCESS16BIT;
+    __IO uint32_t STATE;                             /**< State, offset: 0x44 */
+  };
+  __I  uint32_t INPUT;                             /**< Input, offset: 0x48 */
+  union {                                          /* offset: 0x4C */
+    struct {                                         /* offset: 0x4C */
+      __IO uint16_t REGMODEL;                          /**< SCT_REGMODEL register, offset: 0x4C */
+      __IO uint16_t REGMODEH;                          /**< SCT_REGMODEH register, offset: 0x4E */
+    } REGMODE_ACCESS16BIT;
+    __IO uint32_t REGMODE;                           /**< Match/Capture Mode, offset: 0x4C */
+  };
+  __IO uint32_t OUTPUT;                            /**< Output, offset: 0x50 */
+  __IO uint32_t OUTPUTDIRCTRL;                     /**< Output Counter Direction Control, offset: 0x54 */
+  __IO uint32_t RES;                               /**< Output Conflict Resolution, offset: 0x58 */
+  __IO uint32_t DMAREQ0;                           /**< DMA Request 0, offset: 0x5C */
+  __IO uint32_t DMAREQ1;                           /**< DMA Request 1, offset: 0x60 */
+       uint8_t RESERVED_1[140];
+  __IO uint32_t EVEN;                              /**< Event Interrupt Enable, offset: 0xF0 */
+  __IO uint32_t EVFLAG;                            /**< Event Flag, offset: 0xF4 */
+  __IO uint32_t CONEN;                             /**< Conflict Interrupt Enable, offset: 0xF8 */
+  __IO uint32_t CONFLAG;                           /**< Conflict Flag, offset: 0xFC */
+  union {                                          /* offset: 0x100 */
+    union {                                          /* offset: 0x100, array step: 0x4 */
+      struct {                                         /* offset: 0x100, array step: 0x4 */
+        __IO uint16_t CAPL;                              /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
+        __IO uint16_t CAPH;                              /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
+      } CAP_ACCESS16BIT[16];
+      __IO uint32_t CAP[16];                           /**< Capture Value, array offset: 0x100, array step: 0x4 */
+    };
+    union {                                          /* offset: 0x100, array step: 0x4 */
+      struct {                                         /* offset: 0x100, array step: 0x4 */
+        __IO uint16_t MATCHL;                            /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
+        __IO uint16_t MATCHH;                            /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
+      } MATCH_ACCESS16BIT[16];
+      __IO uint32_t MATCH[16];                         /**< Match Value, array offset: 0x100, array step: 0x4 */
+    };
+  };
+       uint8_t RESERVED_2[192];
+  union {                                          /* offset: 0x200 */
+    union {                                          /* offset: 0x200, array step: 0x4 */
+      struct {                                         /* offset: 0x200, array step: 0x4 */
+        __IO uint16_t CAPCTRLL;                          /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
+        __IO uint16_t CAPCTRLH;                          /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
+      } CAPCTRL_ACCESS16BIT[16];
+      __IO uint32_t CAPCTRL[16];                       /**< Capture Control, array offset: 0x200, array step: 0x4 */
+    };
+    union {                                          /* offset: 0x200, array step: 0x4 */
+      struct {                                         /* offset: 0x200, array step: 0x4 */
+        __IO uint16_t MATCHRELL;                         /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
+        __IO uint16_t MATCHRELH;                         /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
+      } MATCHREL_ACCESS16BIT[16];
+      __IO uint32_t MATCHREL[16];                      /**< Match Reload Value, array offset: 0x200, array step: 0x4 */
+    };
+  };
+       uint8_t RESERVED_3[192];
+  struct {                                         /* offset: 0x300, array step: 0x8 */
+    __IO uint32_t STATE;                             /**< Event n State, array offset: 0x300, array step: 0x8 */
+    __IO uint32_t CTRL;                              /**< Event n Control, array offset: 0x304, array step: 0x8 */
+  } EV[16];
+       uint8_t RESERVED_4[384];
+  struct {                                         /* offset: 0x500, array step: 0x8 */
+    __IO uint32_t SET;                               /**< Output n Set, array offset: 0x500, array step: 0x8 */
+    __IO uint32_t CLR;                               /**< Output n Clear, array offset: 0x504, array step: 0x8 */
+  } OUT[10];
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCTimer Configuration */
+/*! @{ */
+
+#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
+/*! UNIFY - SCT Operation
+ *  0b0..Dual counter. The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
+ *  0b1..Unified counter. The SCT operates as a unified 32-bit counter.
+ */
+#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+
+#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
+/*! CLKMODE - SCT Clock Mode
+ *  0b00..System Clock Mode. The system clock clocks the entire SCT module including all counters and counter prescalers.
+ *  0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
+ *        only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
+ *        minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
+ *        high-performance, sampled-clock mode.
+ *  0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including all
+ *        counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
+ *        clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
+ *  0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
+ *        field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
+ *        clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
+ *        the system clock.
+ */
+#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+
+#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
+/*! CKSEL - SCT Clock Select. The specific functionality of the designated input/edge is dependent
+ *    on the CLKMODE bit selection in this register.
+ *  0b0000..Rising edges on input 0
+ *  0b0001..Falling edges on input 0
+ *  0b0010..Rising edges on input 1
+ *  0b0011..Falling edges on input 1
+ *  0b0100..Rising edges on input 2
+ *  0b0101..Falling edges on input 2
+ *  0b0110..Rising edges on input 3
+ *  0b0111..Falling edges on input 3
+ *  0b1000..Rising edges on input 4
+ *  0b1001..Falling edges on input 4
+ *  0b1010..Rising edges on input 5
+ *  0b1011..Falling edges on input 5
+ *  0b1100..Rising edges on input 6
+ *  0b1101..Falling edges on input 6
+ *  0b1110..Rising edges on input 7
+ *  0b1111..Falling edges on input 7
+ */
+#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+
+#define SCT_CONFIG_NORELOAD_L_MASK               (0x80U)
+#define SCT_CONFIG_NORELOAD_L_SHIFT              (7U)
+/*! NORELOAD_L - No Reload Lower Match
+ *  0b0..Reload. The default setting.
+ *  0b1..No Reload. Prevents the lower match registers from being reloaded from their respective reload registers.
+ */
+#define SCT_CONFIG_NORELOAD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
+
+#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
+/*! NORELOAD_H - No Reload Higher Match
+ *  0b0..Reload. The default setting.
+ *  0b1..No Reload. Prevents the higher match registers from being reloaded from their respective reload registers.
+ */
+#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+
+#define SCT_CONFIG_INSYNC_MASK                   (0x1FE00U)
+#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
+/*! INSYNC - Input Synchronization */
+#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+
+#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
+/*! AUTOLIMIT_L - Auto Limit Lower
+ *  0b0..Disable.
+ *  0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
+ */
+#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+
+#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
+/*! AUTOLIMIT_H - Auto Limit Higher
+ *  0b0..Disable.
+ *  0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
+ */
+#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+/*! @} */
+
+/*! @name CTRLL - SCT_CTRLL register */
+/*! @{ */
+
+#define SCT_CTRLL_DOWN_L_MASK                    (0x1U)
+#define SCT_CTRLL_DOWN_L_SHIFT                   (0U)
+/*! DOWN_L - Down Counter Low
+ *  0b0..Up. The L or unified counter is counting up.
+ *  0b1..Down. The L or unified counter is counting down.
+ */
+#define SCT_CTRLL_DOWN_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
+
+#define SCT_CTRLL_STOP_L_MASK                    (0x2U)
+#define SCT_CTRLL_STOP_L_SHIFT                   (1U)
+/*! STOP_L - Stop Counter Low
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRLL_STOP_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
+
+#define SCT_CTRLL_HALT_L_MASK                    (0x4U)
+#define SCT_CTRLL_HALT_L_SHIFT                   (2U)
+/*! HALT_L - Halt Counter Low
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRLL_HALT_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
+
+#define SCT_CTRLL_CLRCTR_L_MASK                  (0x8U)
+#define SCT_CTRLL_CLRCTR_L_SHIFT                 (3U)
+/*! CLRCTR_L - Clear Counter Low */
+#define SCT_CTRLL_CLRCTR_L(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
+
+#define SCT_CTRLL_BIDIR_L_MASK                   (0x10U)
+#define SCT_CTRLL_BIDIR_L_SHIFT                  (4U)
+/*! BIDIR_L - Bidirectional Select Low
+ *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLL_BIDIR_L(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
+
+#define SCT_CTRLL_PRE_L_MASK                     (0x1FE0U)
+#define SCT_CTRLL_PRE_L_SHIFT                    (5U)
+/*! PRE_L - Prescaler for Low Counter */
+#define SCT_CTRLL_PRE_L(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
+/*! @} */
+
+/*! @name CTRLH - SCT_CTRLH register */
+/*! @{ */
+
+#define SCT_CTRLH_DOWN_H_MASK                    (0x1U)
+#define SCT_CTRLH_DOWN_H_SHIFT                   (0U)
+/*! DOWN_H - Down Counter High
+ *  0b0..Up. The H counter is counting up.
+ *  0b1..Down. The H counter is counting down.
+ */
+#define SCT_CTRLH_DOWN_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
+
+#define SCT_CTRLH_STOP_H_MASK                    (0x2U)
+#define SCT_CTRLH_STOP_H_SHIFT                   (1U)
+/*! STOP_H - Stop Counter High
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRLH_STOP_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
+
+#define SCT_CTRLH_HALT_H_MASK                    (0x4U)
+#define SCT_CTRLH_HALT_H_SHIFT                   (2U)
+/*! HALT_H - Halt Counter High
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRLH_HALT_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
+
+#define SCT_CTRLH_CLRCTR_H_MASK                  (0x8U)
+#define SCT_CTRLH_CLRCTR_H_SHIFT                 (3U)
+/*! CLRCTR_H - Clear Counter High */
+#define SCT_CTRLH_CLRCTR_H(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
+
+#define SCT_CTRLH_BIDIR_H_MASK                   (0x10U)
+#define SCT_CTRLH_BIDIR_H_SHIFT                  (4U)
+/*! BIDIR_H - Bidirectional Select High
+ *  0b0..Up. The H counter counts up to its limit condition, then is cleared to zero.
+ *  0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLH_BIDIR_H(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
+
+#define SCT_CTRLH_PRE_H_MASK                     (0x1FE0U)
+#define SCT_CTRLH_PRE_H_SHIFT                    (5U)
+/*! PRE_H - Prescaler for High Counter */
+#define SCT_CTRLH_PRE_H(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
+/*! @} */
+
+/*! @name CTRL - SCT Control */
+/*! @{ */
+
+#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
+/*! DOWN_L - Down Counter Low
+ *  0b0..Up. The L or unified counter is counting up.
+ *  0b1..Down. The L or unified counter is counting down.
+ */
+#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+
+#define SCT_CTRL_STOP_L_MASK                     (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT                    (1U)
+/*! STOP_L - Stop Counter Low
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+
+#define SCT_CTRL_HALT_L_MASK                     (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT                    (2U)
+/*! HALT_L - Halt Counter Low
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+
+#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
+/*! CLRCTR_L - Clear Counter Low */
+#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+
+#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
+/*! BIDIR_L - Bidirectional Select Low
+ *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+
+#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT                     (5U)
+/*! PRE_L - Prescaler for Low Counter */
+#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+
+#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
+/*! DOWN_H - Down Counter High
+ *  0b0..Up. The H counter is counting up.
+ *  0b1..Down. The H counter is counting down.
+ */
+#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+
+#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT                    (17U)
+/*! STOP_H - Stop Counter High
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+
+#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT                    (18U)
+/*! HALT_H - Halt Counter High
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+
+#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
+/*! CLRCTR_H - Clear Counter High */
+#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+
+#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
+/*! BIDIR_H - Bidirectional Select High
+ *  0b0..Up. The H counter counts up to its limit condition, then is cleared to zero.
+ *  0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+
+#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT                     (21U)
+/*! PRE_H - Prescaler for High Counter */
+#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+/*! @} */
+
+/*! @name LIMITL - SCT_LIMITL register */
+/*! @{ */
+
+#define SCT_LIMITL_LIMITL_MASK                   (0xFFFFU)
+#define SCT_LIMITL_LIMITL_SHIFT                  (0U)
+#define SCT_LIMITL_LIMITL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
+/*! @} */
+
+/*! @name LIMITH - SCT_LIMITH register */
+/*! @{ */
+
+#define SCT_LIMITH_LIMITH_MASK                   (0xFFFFU)
+#define SCT_LIMITH_LIMITH_SHIFT                  (0U)
+#define SCT_LIMITH_LIMITH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
+/*! @} */
+
+/*! @name LIMIT - SCT Limit Event Select */
+/*! @{ */
+
+#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
+/*! LIMMSK_L - Limit Event Counter Low */
+#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+
+#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
+/*! LIMMSK_H - Limit Event Counter High */
+#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+/*! @} */
+
+/*! @name HALTL - SCT_HALTL register */
+/*! @{ */
+
+#define SCT_HALTL_HALTL_MASK                     (0xFFFFU)
+#define SCT_HALTL_HALTL_SHIFT                    (0U)
+#define SCT_HALTL_HALTL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
+/*! @} */
+
+/*! @name HALTH - SCT_HALTH register */
+/*! @{ */
+
+#define SCT_HALTH_HALTH_MASK                     (0xFFFFU)
+#define SCT_HALTH_HALTH_SHIFT                    (0U)
+#define SCT_HALTH_HALTH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
+/*! @} */
+
+/*! @name HALT - Halt Event Select */
+/*! @{ */
+
+#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
+/*! HALTMSK_L - Halt Event Low */
+#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+
+#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
+/*! HALTMSK_H - Halt Event High */
+#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+/*! @} */
+
+/*! @name STOPL - SCT_STOPL register */
+/*! @{ */
+
+#define SCT_STOPL_STOPL_MASK                     (0xFFFFU)
+#define SCT_STOPL_STOPL_SHIFT                    (0U)
+#define SCT_STOPL_STOPL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
+/*! @} */
+
+/*! @name STOPH - SCT_STOPH register */
+/*! @{ */
+
+#define SCT_STOPH_STOPH_MASK                     (0xFFFFU)
+#define SCT_STOPH_STOPH_SHIFT                    (0U)
+#define SCT_STOPH_STOPH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
+/*! @} */
+
+/*! @name STOP - Stop Event Select */
+/*! @{ */
+
+#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
+/*! STOPMSK_L - Stop Event Low */
+#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+
+#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
+/*! STOPMSK_H - Stop Event High */
+#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+/*! @} */
+
+/*! @name STARTL - SCT_STARTL register */
+/*! @{ */
+
+#define SCT_STARTL_STARTL_MASK                   (0xFFFFU)
+#define SCT_STARTL_STARTL_SHIFT                  (0U)
+#define SCT_STARTL_STARTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
+/*! @} */
+
+/*! @name STARTH - SCT_STARTH register */
+/*! @{ */
+
+#define SCT_STARTH_STARTH_MASK                   (0xFFFFU)
+#define SCT_STARTH_STARTH_SHIFT                  (0U)
+#define SCT_STARTH_STARTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
+/*! @} */
+
+/*! @name START - Start Event Select */
+/*! @{ */
+
+#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT               (0U)
+/*! STARTMSK_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 =
+ *    bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+
+#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT               (16U)
+/*! STARTMSK_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 =
+ *    bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+/*! @} */
+
+/*! @name COUNTL - SCT_COUNTL register */
+/*! @{ */
+
+#define SCT_COUNTL_COUNTL_MASK                   (0xFFFFU)
+#define SCT_COUNTL_COUNTL_SHIFT                  (0U)
+#define SCT_COUNTL_COUNTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
+/*! @} */
+
+/*! @name COUNTH - SCT_COUNTH register */
+/*! @{ */
+
+#define SCT_COUNTH_COUNTH_MASK                   (0xFFFFU)
+#define SCT_COUNTH_COUNTH_SHIFT                  (0U)
+#define SCT_COUNTH_COUNTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
+/*! @} */
+
+/*! @name COUNT - Counter */
+/*! @{ */
+
+#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT                    (0U)
+/*! CTR_L - Counter Low */
+#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+
+#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT                    (16U)
+/*! CTR_H - Counter High */
+#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+/*! @} */
+
+/*! @name STATEL - SCT_STATEL register */
+/*! @{ */
+
+#define SCT_STATEL_STATEL_MASK                   (0xFFFFU)
+#define SCT_STATEL_STATEL_SHIFT                  (0U)
+#define SCT_STATEL_STATEL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
+/*! @} */
+
+/*! @name STATEH - SCT_STATEH register */
+/*! @{ */
+
+#define SCT_STATEH_STATEH_MASK                   (0xFFFFU)
+#define SCT_STATEH_STATEH_SHIFT                  (0U)
+#define SCT_STATEH_STATEH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
+/*! @} */
+
+/*! @name STATE - State */
+/*! @{ */
+
+#define SCT_STATE_STATE_L_MASK                   (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT                  (0U)
+/*! STATE_L - State variable */
+#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+
+#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT                  (16U)
+/*! STATE_H - State variable */
+#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+/*! @} */
+
+/*! @name INPUT - Input */
+/*! @{ */
+
+#define SCT_INPUT_AIN0_MASK                      (0x1U)
+#define SCT_INPUT_AIN0_SHIFT                     (0U)
+/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+
+#define SCT_INPUT_AIN1_MASK                      (0x2U)
+#define SCT_INPUT_AIN1_SHIFT                     (1U)
+/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+
+#define SCT_INPUT_AIN2_MASK                      (0x4U)
+#define SCT_INPUT_AIN2_SHIFT                     (2U)
+/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+
+#define SCT_INPUT_AIN3_MASK                      (0x8U)
+#define SCT_INPUT_AIN3_SHIFT                     (3U)
+/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+
+#define SCT_INPUT_AIN4_MASK                      (0x10U)
+#define SCT_INPUT_AIN4_SHIFT                     (4U)
+/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+
+#define SCT_INPUT_AIN5_MASK                      (0x20U)
+#define SCT_INPUT_AIN5_SHIFT                     (5U)
+/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+
+#define SCT_INPUT_AIN6_MASK                      (0x40U)
+#define SCT_INPUT_AIN6_SHIFT                     (6U)
+/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+
+#define SCT_INPUT_AIN7_MASK                      (0x80U)
+#define SCT_INPUT_AIN7_SHIFT                     (7U)
+/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+
+#define SCT_INPUT_AIN8_MASK                      (0x100U)
+#define SCT_INPUT_AIN8_SHIFT                     (8U)
+/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+
+#define SCT_INPUT_AIN9_MASK                      (0x200U)
+#define SCT_INPUT_AIN9_SHIFT                     (9U)
+/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+
+#define SCT_INPUT_AIN10_MASK                     (0x400U)
+#define SCT_INPUT_AIN10_SHIFT                    (10U)
+/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+
+#define SCT_INPUT_AIN11_MASK                     (0x800U)
+#define SCT_INPUT_AIN11_SHIFT                    (11U)
+/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+
+#define SCT_INPUT_AIN12_MASK                     (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT                    (12U)
+/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+
+#define SCT_INPUT_AIN13_MASK                     (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT                    (13U)
+/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+
+#define SCT_INPUT_AIN14_MASK                     (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT                    (14U)
+/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+
+#define SCT_INPUT_AIN15_MASK                     (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT                    (15U)
+/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. */
+#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+
+#define SCT_INPUT_SIN0_MASK                      (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT                     (16U)
+/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+
+#define SCT_INPUT_SIN1_MASK                      (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT                     (17U)
+/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+
+#define SCT_INPUT_SIN2_MASK                      (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT                     (18U)
+/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+
+#define SCT_INPUT_SIN3_MASK                      (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT                     (19U)
+/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+
+#define SCT_INPUT_SIN4_MASK                      (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT                     (20U)
+/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+
+#define SCT_INPUT_SIN5_MASK                      (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT                     (21U)
+/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+
+#define SCT_INPUT_SIN6_MASK                      (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT                     (22U)
+/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+
+#define SCT_INPUT_SIN7_MASK                      (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT                     (23U)
+/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+
+#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT                     (24U)
+/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+
+#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT                     (25U)
+/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+
+#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT                    (26U)
+/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+
+#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT                    (27U)
+/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+
+#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT                    (28U)
+/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+
+#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT                    (29U)
+/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+
+#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT                    (30U)
+/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+
+#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT                    (31U)
+/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. */
+#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+/*! @} */
+
+/*! @name REGMODEL - SCT_REGMODEL register */
+/*! @{ */
+
+#define SCT_REGMODEL_REGMODEL_MASK               (0xFFFFU)
+#define SCT_REGMODEL_REGMODEL_SHIFT              (0U)
+/*! REGMODEL
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEL_REGMODEL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
+/*! @} */
+
+/*! @name REGMODEH - SCT_REGMODEH register */
+/*! @{ */
+
+#define SCT_REGMODEH_REGMODEH_MASK               (0xFFFFU)
+#define SCT_REGMODEH_REGMODEH_SHIFT              (0U)
+/*! REGMODEH
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEH_REGMODEH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
+/*! @} */
+
+/*! @name REGMODE - Match/Capture Mode */
+/*! @{ */
+
+#define SCT_REGMODE_REGMOD_L0_MASK               (0x1U)
+#define SCT_REGMODE_REGMOD_L0_SHIFT              (0U)
+/*! REGMOD_L0 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK)
+
+#define SCT_REGMODE_REGMOD_L1_MASK               (0x2U)
+#define SCT_REGMODE_REGMOD_L1_SHIFT              (1U)
+/*! REGMOD_L1 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK)
+
+#define SCT_REGMODE_REGMOD_L2_MASK               (0x4U)
+#define SCT_REGMODE_REGMOD_L2_SHIFT              (2U)
+/*! REGMOD_L2 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK)
+
+#define SCT_REGMODE_REGMOD_L3_MASK               (0x8U)
+#define SCT_REGMODE_REGMOD_L3_SHIFT              (3U)
+/*! REGMOD_L3 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK)
+
+#define SCT_REGMODE_REGMOD_L4_MASK               (0x10U)
+#define SCT_REGMODE_REGMOD_L4_SHIFT              (4U)
+/*! REGMOD_L4 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK)
+
+#define SCT_REGMODE_REGMOD_L5_MASK               (0x20U)
+#define SCT_REGMODE_REGMOD_L5_SHIFT              (5U)
+/*! REGMOD_L5 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK)
+
+#define SCT_REGMODE_REGMOD_L6_MASK               (0x40U)
+#define SCT_REGMODE_REGMOD_L6_SHIFT              (6U)
+/*! REGMOD_L6 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK)
+
+#define SCT_REGMODE_REGMOD_L7_MASK               (0x80U)
+#define SCT_REGMODE_REGMOD_L7_SHIFT              (7U)
+/*! REGMOD_L7 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK)
+
+#define SCT_REGMODE_REGMOD_L8_MASK               (0x100U)
+#define SCT_REGMODE_REGMOD_L8_SHIFT              (8U)
+/*! REGMOD_L8 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK)
+
+#define SCT_REGMODE_REGMOD_L9_MASK               (0x200U)
+#define SCT_REGMODE_REGMOD_L9_SHIFT              (9U)
+/*! REGMOD_L9 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK)
+
+#define SCT_REGMODE_REGMOD_L10_MASK              (0x400U)
+#define SCT_REGMODE_REGMOD_L10_SHIFT             (10U)
+/*! REGMOD_L10 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK)
+
+#define SCT_REGMODE_REGMOD_L11_MASK              (0x800U)
+#define SCT_REGMODE_REGMOD_L11_SHIFT             (11U)
+/*! REGMOD_L11 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK)
+
+#define SCT_REGMODE_REGMOD_L12_MASK              (0x1000U)
+#define SCT_REGMODE_REGMOD_L12_SHIFT             (12U)
+/*! REGMOD_L12 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK)
+
+#define SCT_REGMODE_REGMOD_L13_MASK              (0x2000U)
+#define SCT_REGMODE_REGMOD_L13_SHIFT             (13U)
+/*! REGMOD_L13 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK)
+
+#define SCT_REGMODE_REGMOD_L14_MASK              (0x4000U)
+#define SCT_REGMODE_REGMOD_L14_SHIFT             (14U)
+/*! REGMOD_L14 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK)
+
+#define SCT_REGMODE_REGMOD_L15_MASK              (0x8000U)
+#define SCT_REGMODE_REGMOD_L15_SHIFT             (15U)
+/*! REGMOD_L15 - Register Mode Low n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK)
+
+#define SCT_REGMODE_REGMOD_H0_MASK               (0x10000U)
+#define SCT_REGMODE_REGMOD_H0_SHIFT              (16U)
+/*! REGMOD_H0 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK)
+
+#define SCT_REGMODE_REGMOD_H1_MASK               (0x20000U)
+#define SCT_REGMODE_REGMOD_H1_SHIFT              (17U)
+/*! REGMOD_H1 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK)
+
+#define SCT_REGMODE_REGMOD_H2_MASK               (0x40000U)
+#define SCT_REGMODE_REGMOD_H2_SHIFT              (18U)
+/*! REGMOD_H2 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK)
+
+#define SCT_REGMODE_REGMOD_H3_MASK               (0x80000U)
+#define SCT_REGMODE_REGMOD_H3_SHIFT              (19U)
+/*! REGMOD_H3 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK)
+
+#define SCT_REGMODE_REGMOD_H4_MASK               (0x100000U)
+#define SCT_REGMODE_REGMOD_H4_SHIFT              (20U)
+/*! REGMOD_H4 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK)
+
+#define SCT_REGMODE_REGMOD_H5_MASK               (0x200000U)
+#define SCT_REGMODE_REGMOD_H5_SHIFT              (21U)
+/*! REGMOD_H5 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK)
+
+#define SCT_REGMODE_REGMOD_H6_MASK               (0x400000U)
+#define SCT_REGMODE_REGMOD_H6_SHIFT              (22U)
+/*! REGMOD_H6 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK)
+
+#define SCT_REGMODE_REGMOD_H7_MASK               (0x800000U)
+#define SCT_REGMODE_REGMOD_H7_SHIFT              (23U)
+/*! REGMOD_H7 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK)
+
+#define SCT_REGMODE_REGMOD_H8_MASK               (0x1000000U)
+#define SCT_REGMODE_REGMOD_H8_SHIFT              (24U)
+/*! REGMOD_H8 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK)
+
+#define SCT_REGMODE_REGMOD_H9_MASK               (0x2000000U)
+#define SCT_REGMODE_REGMOD_H9_SHIFT              (25U)
+/*! REGMOD_H9 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK)
+
+#define SCT_REGMODE_REGMOD_H10_MASK              (0x4000000U)
+#define SCT_REGMODE_REGMOD_H10_SHIFT             (26U)
+/*! REGMOD_H10 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK)
+
+#define SCT_REGMODE_REGMOD_H11_MASK              (0x8000000U)
+#define SCT_REGMODE_REGMOD_H11_SHIFT             (27U)
+/*! REGMOD_H11 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK)
+
+#define SCT_REGMODE_REGMOD_H12_MASK              (0x10000000U)
+#define SCT_REGMODE_REGMOD_H12_SHIFT             (28U)
+/*! REGMOD_H12 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK)
+
+#define SCT_REGMODE_REGMOD_H13_MASK              (0x20000000U)
+#define SCT_REGMODE_REGMOD_H13_SHIFT             (29U)
+/*! REGMOD_H13 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK)
+
+#define SCT_REGMODE_REGMOD_H14_MASK              (0x40000000U)
+#define SCT_REGMODE_REGMOD_H14_SHIFT             (30U)
+/*! REGMOD_H14 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK)
+
+#define SCT_REGMODE_REGMOD_H15_MASK              (0x80000000U)
+#define SCT_REGMODE_REGMOD_H15_SHIFT             (31U)
+/*! REGMOD_H15 - Register Mode High n
+ *  0b0..Match. Register n operates as a match register
+ *  0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK)
+/*! @} */
+
+/*! @name OUTPUT - Output */
+/*! @{ */
+
+#define SCT_OUTPUT_OUT0_MASK                     (0x1U)
+#define SCT_OUTPUT_OUT0_SHIFT                    (0U)
+/*! OUT0 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK)
+
+#define SCT_OUTPUT_OUT1_MASK                     (0x2U)
+#define SCT_OUTPUT_OUT1_SHIFT                    (1U)
+/*! OUT1 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK)
+
+#define SCT_OUTPUT_OUT2_MASK                     (0x4U)
+#define SCT_OUTPUT_OUT2_SHIFT                    (2U)
+/*! OUT2 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK)
+
+#define SCT_OUTPUT_OUT3_MASK                     (0x8U)
+#define SCT_OUTPUT_OUT3_SHIFT                    (3U)
+/*! OUT3 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK)
+
+#define SCT_OUTPUT_OUT4_MASK                     (0x10U)
+#define SCT_OUTPUT_OUT4_SHIFT                    (4U)
+/*! OUT4 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK)
+
+#define SCT_OUTPUT_OUT5_MASK                     (0x20U)
+#define SCT_OUTPUT_OUT5_SHIFT                    (5U)
+/*! OUT5 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK)
+
+#define SCT_OUTPUT_OUT6_MASK                     (0x40U)
+#define SCT_OUTPUT_OUT6_SHIFT                    (6U)
+/*! OUT6 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK)
+
+#define SCT_OUTPUT_OUT7_MASK                     (0x80U)
+#define SCT_OUTPUT_OUT7_SHIFT                    (7U)
+/*! OUT7 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK)
+
+#define SCT_OUTPUT_OUT8_MASK                     (0x100U)
+#define SCT_OUTPUT_OUT8_SHIFT                    (8U)
+/*! OUT8 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK)
+
+#define SCT_OUTPUT_OUT9_MASK                     (0x200U)
+#define SCT_OUTPUT_OUT9_SHIFT                    (9U)
+/*! OUT9 - Output n
+ *  0b0..Writing a 0 forces the corresponding output low
+ *  0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK)
+/*! @} */
+
+/*! @name OUTPUTDIRCTRL - Output Counter Direction Control */
+/*! @{ */
+
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
+/*! SETCLR0 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
+/*! SETCLR1 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
+/*! SETCLR2 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
+/*! SETCLR3 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
+/*! SETCLR4 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
+/*! SETCLR5 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
+/*! SETCLR6 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
+/*! SETCLR7 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
+/*! SETCLR8 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
+/*! SETCLR9 - Set/Clear Operation on Output n
+ *  0b00..Set and clear do not depend on the direction of any counter.
+ *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ *  0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+/*! @} */
+
+/*! @name RES - Output Conflict Resolution */
+/*! @{ */
+
+#define SCT_RES_O0RES_MASK                       (0x3U)
+#define SCT_RES_O0RES_SHIFT                      (0U)
+/*! O0RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+
+#define SCT_RES_O1RES_MASK                       (0xCU)
+#define SCT_RES_O1RES_SHIFT                      (2U)
+/*! O1RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+
+#define SCT_RES_O2RES_MASK                       (0x30U)
+#define SCT_RES_O2RES_SHIFT                      (4U)
+/*! O2RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+
+#define SCT_RES_O3RES_MASK                       (0xC0U)
+#define SCT_RES_O3RES_SHIFT                      (6U)
+/*! O3RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+
+#define SCT_RES_O4RES_MASK                       (0x300U)
+#define SCT_RES_O4RES_SHIFT                      (8U)
+/*! O4RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+
+#define SCT_RES_O5RES_MASK                       (0xC00U)
+#define SCT_RES_O5RES_SHIFT                      (10U)
+/*! O5RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+
+#define SCT_RES_O6RES_MASK                       (0x3000U)
+#define SCT_RES_O6RES_SHIFT                      (12U)
+/*! O6RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+
+#define SCT_RES_O7RES_MASK                       (0xC000U)
+#define SCT_RES_O7RES_SHIFT                      (14U)
+/*! O7RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+
+#define SCT_RES_O8RES_MASK                       (0x30000U)
+#define SCT_RES_O8RES_SHIFT                      (16U)
+/*! O8RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+
+#define SCT_RES_O9RES_MASK                       (0xC0000U)
+#define SCT_RES_O9RES_SHIFT                      (18U)
+/*! O9RES - Effect of simultaneous set and clear on output n
+ *  0b00..No change
+ *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ *  0b11..Toggle output
+ */
+#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+/*! @} */
+
+/*! @name DMAREQ0 - DMA Request 0 */
+/*! @{ */
+
+#define SCT_DMAREQ0_DEV_0_MASK                   (0x1U)
+#define SCT_DMAREQ0_DEV_0_SHIFT                  (0U)
+/*! DEV_0 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
+
+#define SCT_DMAREQ0_DEV_1_MASK                   (0x2U)
+#define SCT_DMAREQ0_DEV_1_SHIFT                  (1U)
+/*! DEV_1 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK)
+
+#define SCT_DMAREQ0_DEV_2_MASK                   (0x4U)
+#define SCT_DMAREQ0_DEV_2_SHIFT                  (2U)
+/*! DEV_2 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK)
+
+#define SCT_DMAREQ0_DEV_3_MASK                   (0x8U)
+#define SCT_DMAREQ0_DEV_3_SHIFT                  (3U)
+/*! DEV_3 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK)
+
+#define SCT_DMAREQ0_DEV_4_MASK                   (0x10U)
+#define SCT_DMAREQ0_DEV_4_SHIFT                  (4U)
+/*! DEV_4 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK)
+
+#define SCT_DMAREQ0_DEV_5_MASK                   (0x20U)
+#define SCT_DMAREQ0_DEV_5_SHIFT                  (5U)
+/*! DEV_5 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK)
+
+#define SCT_DMAREQ0_DEV_6_MASK                   (0x40U)
+#define SCT_DMAREQ0_DEV_6_SHIFT                  (6U)
+/*! DEV_6 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK)
+
+#define SCT_DMAREQ0_DEV_7_MASK                   (0x80U)
+#define SCT_DMAREQ0_DEV_7_SHIFT                  (7U)
+/*! DEV_7 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK)
+
+#define SCT_DMAREQ0_DEV_8_MASK                   (0x100U)
+#define SCT_DMAREQ0_DEV_8_SHIFT                  (8U)
+/*! DEV_8 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK)
+
+#define SCT_DMAREQ0_DEV_9_MASK                   (0x200U)
+#define SCT_DMAREQ0_DEV_9_SHIFT                  (9U)
+/*! DEV_9 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK)
+
+#define SCT_DMAREQ0_DEV_10_MASK                  (0x400U)
+#define SCT_DMAREQ0_DEV_10_SHIFT                 (10U)
+/*! DEV_10 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK)
+
+#define SCT_DMAREQ0_DEV_11_MASK                  (0x800U)
+#define SCT_DMAREQ0_DEV_11_SHIFT                 (11U)
+/*! DEV_11 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK)
+
+#define SCT_DMAREQ0_DEV_12_MASK                  (0x1000U)
+#define SCT_DMAREQ0_DEV_12_SHIFT                 (12U)
+/*! DEV_12 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK)
+
+#define SCT_DMAREQ0_DEV_13_MASK                  (0x2000U)
+#define SCT_DMAREQ0_DEV_13_SHIFT                 (13U)
+/*! DEV_13 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK)
+
+#define SCT_DMAREQ0_DEV_14_MASK                  (0x4000U)
+#define SCT_DMAREQ0_DEV_14_SHIFT                 (14U)
+/*! DEV_14 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK)
+
+#define SCT_DMAREQ0_DEV_15_MASK                  (0x8000U)
+#define SCT_DMAREQ0_DEV_15_SHIFT                 (15U)
+/*! DEV_15 - DMA Request Event n */
+#define SCT_DMAREQ0_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK)
+
+#define SCT_DMAREQ0_DRL0_MASK                    (0x40000000U)
+#define SCT_DMAREQ0_DRL0_SHIFT                   (30U)
+/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. */
+#define SCT_DMAREQ0_DRL0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
+
+#define SCT_DMAREQ0_DRQ0_MASK                    (0x80000000U)
+#define SCT_DMAREQ0_DRQ0_SHIFT                   (31U)
+/*! DRQ0 - DMA Request 0 State */
+#define SCT_DMAREQ0_DRQ0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
+/*! @} */
+
+/*! @name DMAREQ1 - DMA Request 1 */
+/*! @{ */
+
+#define SCT_DMAREQ1_DEV_0_MASK                   (0x1U)
+#define SCT_DMAREQ1_DEV_0_SHIFT                  (0U)
+/*! DEV_0 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK)
+
+#define SCT_DMAREQ1_DEV_1_MASK                   (0x2U)
+#define SCT_DMAREQ1_DEV_1_SHIFT                  (1U)
+/*! DEV_1 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
+
+#define SCT_DMAREQ1_DEV_2_MASK                   (0x4U)
+#define SCT_DMAREQ1_DEV_2_SHIFT                  (2U)
+/*! DEV_2 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK)
+
+#define SCT_DMAREQ1_DEV_3_MASK                   (0x8U)
+#define SCT_DMAREQ1_DEV_3_SHIFT                  (3U)
+/*! DEV_3 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK)
+
+#define SCT_DMAREQ1_DEV_4_MASK                   (0x10U)
+#define SCT_DMAREQ1_DEV_4_SHIFT                  (4U)
+/*! DEV_4 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK)
+
+#define SCT_DMAREQ1_DEV_5_MASK                   (0x20U)
+#define SCT_DMAREQ1_DEV_5_SHIFT                  (5U)
+/*! DEV_5 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK)
+
+#define SCT_DMAREQ1_DEV_6_MASK                   (0x40U)
+#define SCT_DMAREQ1_DEV_6_SHIFT                  (6U)
+/*! DEV_6 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK)
+
+#define SCT_DMAREQ1_DEV_7_MASK                   (0x80U)
+#define SCT_DMAREQ1_DEV_7_SHIFT                  (7U)
+/*! DEV_7 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK)
+
+#define SCT_DMAREQ1_DEV_8_MASK                   (0x100U)
+#define SCT_DMAREQ1_DEV_8_SHIFT                  (8U)
+/*! DEV_8 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK)
+
+#define SCT_DMAREQ1_DEV_9_MASK                   (0x200U)
+#define SCT_DMAREQ1_DEV_9_SHIFT                  (9U)
+/*! DEV_9 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK)
+
+#define SCT_DMAREQ1_DEV_10_MASK                  (0x400U)
+#define SCT_DMAREQ1_DEV_10_SHIFT                 (10U)
+/*! DEV_10 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK)
+
+#define SCT_DMAREQ1_DEV_11_MASK                  (0x800U)
+#define SCT_DMAREQ1_DEV_11_SHIFT                 (11U)
+/*! DEV_11 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK)
+
+#define SCT_DMAREQ1_DEV_12_MASK                  (0x1000U)
+#define SCT_DMAREQ1_DEV_12_SHIFT                 (12U)
+/*! DEV_12 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK)
+
+#define SCT_DMAREQ1_DEV_13_MASK                  (0x2000U)
+#define SCT_DMAREQ1_DEV_13_SHIFT                 (13U)
+/*! DEV_13 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK)
+
+#define SCT_DMAREQ1_DEV_14_MASK                  (0x4000U)
+#define SCT_DMAREQ1_DEV_14_SHIFT                 (14U)
+/*! DEV_14 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK)
+
+#define SCT_DMAREQ1_DEV_15_MASK                  (0x8000U)
+#define SCT_DMAREQ1_DEV_15_SHIFT                 (15U)
+/*! DEV_15 - DMA Request Event n */
+#define SCT_DMAREQ1_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK)
+
+#define SCT_DMAREQ1_DRL1_MASK                    (0x40000000U)
+#define SCT_DMAREQ1_DRL1_SHIFT                   (30U)
+/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. */
+#define SCT_DMAREQ1_DRL1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
+
+#define SCT_DMAREQ1_DRQ1_MASK                    (0x80000000U)
+#define SCT_DMAREQ1_DRQ1_SHIFT                   (31U)
+/*! DRQ1 - DMA Request 1 State */
+#define SCT_DMAREQ1_DRQ1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
+/*! @} */
+
+/*! @name EVEN - Event Interrupt Enable */
+/*! @{ */
+
+#define SCT_EVEN_IEN0_MASK                       (0x1U)
+#define SCT_EVEN_IEN0_SHIFT                      (0U)
+/*! IEN0 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN0(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK)
+
+#define SCT_EVEN_IEN1_MASK                       (0x2U)
+#define SCT_EVEN_IEN1_SHIFT                      (1U)
+/*! IEN1 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN1(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK)
+
+#define SCT_EVEN_IEN2_MASK                       (0x4U)
+#define SCT_EVEN_IEN2_SHIFT                      (2U)
+/*! IEN2 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN2(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK)
+
+#define SCT_EVEN_IEN3_MASK                       (0x8U)
+#define SCT_EVEN_IEN3_SHIFT                      (3U)
+/*! IEN3 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN3(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK)
+
+#define SCT_EVEN_IEN4_MASK                       (0x10U)
+#define SCT_EVEN_IEN4_SHIFT                      (4U)
+/*! IEN4 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN4(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK)
+
+#define SCT_EVEN_IEN5_MASK                       (0x20U)
+#define SCT_EVEN_IEN5_SHIFT                      (5U)
+/*! IEN5 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN5(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK)
+
+#define SCT_EVEN_IEN6_MASK                       (0x40U)
+#define SCT_EVEN_IEN6_SHIFT                      (6U)
+/*! IEN6 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN6(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK)
+
+#define SCT_EVEN_IEN7_MASK                       (0x80U)
+#define SCT_EVEN_IEN7_SHIFT                      (7U)
+/*! IEN7 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN7(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK)
+
+#define SCT_EVEN_IEN8_MASK                       (0x100U)
+#define SCT_EVEN_IEN8_SHIFT                      (8U)
+/*! IEN8 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN8(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK)
+
+#define SCT_EVEN_IEN9_MASK                       (0x200U)
+#define SCT_EVEN_IEN9_SHIFT                      (9U)
+/*! IEN9 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN9(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK)
+
+#define SCT_EVEN_IEN10_MASK                      (0x400U)
+#define SCT_EVEN_IEN10_SHIFT                     (10U)
+/*! IEN10 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN10(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK)
+
+#define SCT_EVEN_IEN11_MASK                      (0x800U)
+#define SCT_EVEN_IEN11_SHIFT                     (11U)
+/*! IEN11 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN11(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK)
+
+#define SCT_EVEN_IEN12_MASK                      (0x1000U)
+#define SCT_EVEN_IEN12_SHIFT                     (12U)
+/*! IEN12 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN12(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK)
+
+#define SCT_EVEN_IEN13_MASK                      (0x2000U)
+#define SCT_EVEN_IEN13_SHIFT                     (13U)
+/*! IEN13 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN13(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK)
+
+#define SCT_EVEN_IEN14_MASK                      (0x4000U)
+#define SCT_EVEN_IEN14_SHIFT                     (14U)
+/*! IEN14 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN14(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK)
+
+#define SCT_EVEN_IEN15_MASK                      (0x8000U)
+#define SCT_EVEN_IEN15_SHIFT                     (15U)
+/*! IEN15 - Event Interrupt Enable n
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SCT_EVEN_IEN15(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK)
+/*! @} */
+
+/*! @name EVFLAG - Event Flag */
+/*! @{ */
+
+#define SCT_EVFLAG_FLAG0_MASK                    (0x1U)
+#define SCT_EVFLAG_FLAG0_SHIFT                   (0U)
+/*! FLAG0 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK)
+
+#define SCT_EVFLAG_FLAG1_MASK                    (0x2U)
+#define SCT_EVFLAG_FLAG1_SHIFT                   (1U)
+/*! FLAG1 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK)
+
+#define SCT_EVFLAG_FLAG2_MASK                    (0x4U)
+#define SCT_EVFLAG_FLAG2_SHIFT                   (2U)
+/*! FLAG2 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG2(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK)
+
+#define SCT_EVFLAG_FLAG3_MASK                    (0x8U)
+#define SCT_EVFLAG_FLAG3_SHIFT                   (3U)
+/*! FLAG3 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG3(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK)
+
+#define SCT_EVFLAG_FLAG4_MASK                    (0x10U)
+#define SCT_EVFLAG_FLAG4_SHIFT                   (4U)
+/*! FLAG4 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG4(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK)
+
+#define SCT_EVFLAG_FLAG5_MASK                    (0x20U)
+#define SCT_EVFLAG_FLAG5_SHIFT                   (5U)
+/*! FLAG5 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG5(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK)
+
+#define SCT_EVFLAG_FLAG6_MASK                    (0x40U)
+#define SCT_EVFLAG_FLAG6_SHIFT                   (6U)
+/*! FLAG6 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG6(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK)
+
+#define SCT_EVFLAG_FLAG7_MASK                    (0x80U)
+#define SCT_EVFLAG_FLAG7_SHIFT                   (7U)
+/*! FLAG7 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG7(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK)
+
+#define SCT_EVFLAG_FLAG8_MASK                    (0x100U)
+#define SCT_EVFLAG_FLAG8_SHIFT                   (8U)
+/*! FLAG8 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG8(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK)
+
+#define SCT_EVFLAG_FLAG9_MASK                    (0x200U)
+#define SCT_EVFLAG_FLAG9_SHIFT                   (9U)
+/*! FLAG9 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG9(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK)
+
+#define SCT_EVFLAG_FLAG10_MASK                   (0x400U)
+#define SCT_EVFLAG_FLAG10_SHIFT                  (10U)
+/*! FLAG10 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG10(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK)
+
+#define SCT_EVFLAG_FLAG11_MASK                   (0x800U)
+#define SCT_EVFLAG_FLAG11_SHIFT                  (11U)
+/*! FLAG11 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG11(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK)
+
+#define SCT_EVFLAG_FLAG12_MASK                   (0x1000U)
+#define SCT_EVFLAG_FLAG12_SHIFT                  (12U)
+/*! FLAG12 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG12(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK)
+
+#define SCT_EVFLAG_FLAG13_MASK                   (0x2000U)
+#define SCT_EVFLAG_FLAG13_SHIFT                  (13U)
+/*! FLAG13 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG13(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK)
+
+#define SCT_EVFLAG_FLAG14_MASK                   (0x4000U)
+#define SCT_EVFLAG_FLAG14_SHIFT                  (14U)
+/*! FLAG14 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG14(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK)
+
+#define SCT_EVFLAG_FLAG15_MASK                   (0x8000U)
+#define SCT_EVFLAG_FLAG15_SHIFT                  (15U)
+/*! FLAG15 - Event Flag n
+ *  0b0..No Flag
+ *  0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG15(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK)
+/*! @} */
+
+/*! @name CONEN - Conflict Interrupt Enable */
+/*! @{ */
+
+#define SCT_CONEN_NCEN0_MASK                     (0x1U)
+#define SCT_CONEN_NCEN0_SHIFT                    (0U)
+/*! NCEN0 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK)
+
+#define SCT_CONEN_NCEN1_MASK                     (0x2U)
+#define SCT_CONEN_NCEN1_SHIFT                    (1U)
+/*! NCEN1 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK)
+
+#define SCT_CONEN_NCEN2_MASK                     (0x4U)
+#define SCT_CONEN_NCEN2_SHIFT                    (2U)
+/*! NCEN2 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK)
+
+#define SCT_CONEN_NCEN3_MASK                     (0x8U)
+#define SCT_CONEN_NCEN3_SHIFT                    (3U)
+/*! NCEN3 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK)
+
+#define SCT_CONEN_NCEN4_MASK                     (0x10U)
+#define SCT_CONEN_NCEN4_SHIFT                    (4U)
+/*! NCEN4 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK)
+
+#define SCT_CONEN_NCEN5_MASK                     (0x20U)
+#define SCT_CONEN_NCEN5_SHIFT                    (5U)
+/*! NCEN5 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK)
+
+#define SCT_CONEN_NCEN6_MASK                     (0x40U)
+#define SCT_CONEN_NCEN6_SHIFT                    (6U)
+/*! NCEN6 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK)
+
+#define SCT_CONEN_NCEN7_MASK                     (0x80U)
+#define SCT_CONEN_NCEN7_SHIFT                    (7U)
+/*! NCEN7 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK)
+
+#define SCT_CONEN_NCEN8_MASK                     (0x100U)
+#define SCT_CONEN_NCEN8_SHIFT                    (8U)
+/*! NCEN8 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK)
+
+#define SCT_CONEN_NCEN9_MASK                     (0x200U)
+#define SCT_CONEN_NCEN9_SHIFT                    (9U)
+/*! NCEN9 - No Change Conflict Event/Interrupt Enable
+ *  0b0..No interrupt
+ *  0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK)
+/*! @} */
+
+/*! @name CONFLAG - Conflict Flag */
+/*! @{ */
+
+#define SCT_CONFLAG_NCFLAG0_MASK                 (0x1U)
+#define SCT_CONFLAG_NCFLAG0_SHIFT                (0U)
+/*! NCFLAG0 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK)
+
+#define SCT_CONFLAG_NCFLAG1_MASK                 (0x2U)
+#define SCT_CONFLAG_NCFLAG1_SHIFT                (1U)
+/*! NCFLAG1 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK)
+
+#define SCT_CONFLAG_NCFLAG2_MASK                 (0x4U)
+#define SCT_CONFLAG_NCFLAG2_SHIFT                (2U)
+/*! NCFLAG2 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK)
+
+#define SCT_CONFLAG_NCFLAG3_MASK                 (0x8U)
+#define SCT_CONFLAG_NCFLAG3_SHIFT                (3U)
+/*! NCFLAG3 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK)
+
+#define SCT_CONFLAG_NCFLAG4_MASK                 (0x10U)
+#define SCT_CONFLAG_NCFLAG4_SHIFT                (4U)
+/*! NCFLAG4 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG4(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK)
+
+#define SCT_CONFLAG_NCFLAG5_MASK                 (0x20U)
+#define SCT_CONFLAG_NCFLAG5_SHIFT                (5U)
+/*! NCFLAG5 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG5(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK)
+
+#define SCT_CONFLAG_NCFLAG6_MASK                 (0x40U)
+#define SCT_CONFLAG_NCFLAG6_SHIFT                (6U)
+/*! NCFLAG6 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG6(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK)
+
+#define SCT_CONFLAG_NCFLAG7_MASK                 (0x80U)
+#define SCT_CONFLAG_NCFLAG7_SHIFT                (7U)
+/*! NCFLAG7 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG7(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK)
+
+#define SCT_CONFLAG_NCFLAG8_MASK                 (0x100U)
+#define SCT_CONFLAG_NCFLAG8_SHIFT                (8U)
+/*! NCFLAG8 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG8(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK)
+
+#define SCT_CONFLAG_NCFLAG9_MASK                 (0x200U)
+#define SCT_CONFLAG_NCFLAG9_SHIFT                (9U)
+/*! NCFLAG9 - No Change Conflict Event Flag
+ *  0b0..No Conflict Event
+ *  0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG9(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK)
+
+#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
+/*! BUSERRL - Bus Error Low/Unified */
+#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+
+#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
+/*! BUSERRH - Bus Error High */
+#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+/*! @} */
+
+/*! @name CAPL - SCT_CAPL register */
+/*! @{ */
+
+#define SCT_CAPL_CAPL_MASK                       (0xFFFFU)
+#define SCT_CAPL_CAPL_SHIFT                      (0U)
+#define SCT_CAPL_CAPL(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPL */
+#define SCT_CAPL_COUNT                           (16U)
+
+/*! @name CAPH - SCT_CAPH register */
+/*! @{ */
+
+#define SCT_CAPH_CAPH_MASK                       (0xFFFFU)
+#define SCT_CAPH_CAPH_SHIFT                      (0U)
+#define SCT_CAPH_CAPH(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
+/*! @} */
+
+/* The count of SCT_CAPH */
+#define SCT_CAPH_COUNT                           (16U)
+
+/*! @name CAP - Capture Value */
+/*! @{ */
+
+#define SCT_CAP_CAPN_L_MASK                      (0xFFFFU)
+#define SCT_CAP_CAPN_L_SHIFT                     (0U)
+/*! CAPN_L - Capture n Low */
+#define SCT_CAP_CAPN_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPN_L_SHIFT)) & SCT_CAP_CAPN_L_MASK)
+
+#define SCT_CAP_CAPN_H_MASK                      (0xFFFF0000U)
+#define SCT_CAP_CAPN_H_SHIFT                     (16U)
+/*! CAPN_H - Capture n High */
+#define SCT_CAP_CAPN_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPN_H_SHIFT)) & SCT_CAP_CAPN_H_MASK)
+/*! @} */
+
+/* The count of SCT_CAP */
+#define SCT_CAP_COUNT                            (16U)
+
+/*! @name MATCHL - SCT_MATCHL register */
+/*! @{ */
+
+#define SCT_MATCHL_MATCHL_MASK                   (0xFFFFU)
+#define SCT_MATCHL_MATCHL_SHIFT                  (0U)
+#define SCT_MATCHL_MATCHL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHL */
+#define SCT_MATCHL_COUNT                         (16U)
+
+/*! @name MATCHH - SCT_MATCHH register */
+/*! @{ */
+
+#define SCT_MATCHH_MATCHH_MASK                   (0xFFFFU)
+#define SCT_MATCHH_MATCHH_SHIFT                  (0U)
+#define SCT_MATCHH_MATCHH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHH */
+#define SCT_MATCHH_COUNT                         (16U)
+
+/*! @name MATCH - Match Value */
+/*! @{ */
+
+#define SCT_MATCH_MATCHN_L_MASK                  (0xFFFFU)
+#define SCT_MATCH_MATCHN_L_SHIFT                 (0U)
+/*! MATCHN_L - Match n Low */
+#define SCT_MATCH_MATCHN_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHN_L_SHIFT)) & SCT_MATCH_MATCHN_L_MASK)
+
+#define SCT_MATCH_MATCHN_H_MASK                  (0xFFFF0000U)
+#define SCT_MATCH_MATCHN_H_SHIFT                 (16U)
+/*! MATCHN_H - Match n High */
+#define SCT_MATCH_MATCHN_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHN_H_SHIFT)) & SCT_MATCH_MATCHN_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCH */
+#define SCT_MATCH_COUNT                          (16U)
+
+/*! @name CAPCTRLL - SCT_CAPCTRLL register */
+/*! @{ */
+
+#define SCT_CAPCTRLL_CAPCTRLL_MASK               (0xFFFFU)
+#define SCT_CAPCTRLL_CAPCTRLL_SHIFT              (0U)
+#define SCT_CAPCTRLL_CAPCTRLL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRLL */
+#define SCT_CAPCTRLL_COUNT                       (16U)
+
+/*! @name CAPCTRLH - SCT_CAPCTRLH register */
+/*! @{ */
+
+#define SCT_CAPCTRLH_CAPCTRLH_MASK               (0xFFFFU)
+#define SCT_CAPCTRLH_CAPCTRLH_SHIFT              (0U)
+#define SCT_CAPCTRLH_CAPCTRLH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRLH */
+#define SCT_CAPCTRLH_COUNT                       (16U)
+
+/*! @name SCTCAPCTRL_CAPCTRL - Capture Control */
+/*! @{ */
+
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L_MASK    (0xFFFFU)
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L_SHIFT   (0U)
+/*! CAPCONN_L - Capture Control n Low */
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L_MASK)
+
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H_MASK    (0xFFFF0000U)
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H_SHIFT   (16U)
+/*! CAPCONN_H - Capture Control n High */
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H_MASK)
+/*! @} */
+
+/* The count of SCT_SCTCAPCTRL_CAPCTRL */
+#define SCT_SCTCAPCTRL_CAPCTRL_COUNT             (16U)
+
+/*! @name MATCHRELL - SCT_MATCHRELL register */
+/*! @{ */
+
+#define SCT_MATCHRELL_MATCHRELL_MASK             (0xFFFFU)
+#define SCT_MATCHRELL_MATCHRELL_SHIFT            (0U)
+#define SCT_MATCHRELL_MATCHRELL(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELL */
+#define SCT_MATCHRELL_COUNT                      (16U)
+
+/*! @name MATCHRELH - SCT_MATCHRELH register */
+/*! @{ */
+
+#define SCT_MATCHRELH_MATCHRELH_MASK             (0xFFFFU)
+#define SCT_MATCHRELH_MATCHRELH_SHIFT            (0U)
+#define SCT_MATCHRELH_MATCHRELH(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELH */
+#define SCT_MATCHRELH_COUNT                      (16U)
+
+/*! @name MATCHREL - Match Reload Value */
+/*! @{ */
+
+#define SCT_MATCHREL_RELOADN_L_MASK              (0xFFFFU)
+#define SCT_MATCHREL_RELOADN_L_SHIFT             (0U)
+/*! RELOADN_L - Reload n Low */
+#define SCT_MATCHREL_RELOADN_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADN_L_SHIFT)) & SCT_MATCHREL_RELOADN_L_MASK)
+
+#define SCT_MATCHREL_RELOADN_H_MASK              (0xFFFF0000U)
+#define SCT_MATCHREL_RELOADN_H_SHIFT             (16U)
+/*! RELOADN_H - Reload n High */
+#define SCT_MATCHREL_RELOADN_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADN_H_SHIFT)) & SCT_MATCHREL_RELOADN_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHREL */
+#define SCT_MATCHREL_COUNT                       (16U)
+
+/*! @name EV_STATE - Event n State */
+/*! @{ */
+
+#define SCT_EV_STATE_STATEMSKN_MASK              (0xFFFFFFFFU)
+#define SCT_EV_STATE_STATEMSKN_SHIFT             (0U)
+/*! STATEMSKN - Event State Mask n */
+#define SCT_EV_STATE_STATEMSKN(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKN_SHIFT)) & SCT_EV_STATE_STATEMSKN_MASK)
+/*! @} */
+
+/* The count of SCT_EV_STATE */
+#define SCT_EV_STATE_COUNT                       (16U)
+
+/*! @name EV_CTRL - Event n Control */
+/*! @{ */
+
+#define SCT_EV_CTRL_MATCHSEL_MASK                (0xFU)
+#define SCT_EV_CTRL_MATCHSEL_SHIFT               (0U)
+/*! MATCHSEL - Match Select */
+#define SCT_EV_CTRL_MATCHSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
+
+#define SCT_EV_CTRL_HEVENT_MASK                  (0x10U)
+#define SCT_EV_CTRL_HEVENT_SHIFT                 (4U)
+/*! HEVENT - High Event
+ *  0b0..Low Counter
+ *  0b1..High Counter
+ */
+#define SCT_EV_CTRL_HEVENT(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
+
+#define SCT_EV_CTRL_OUTSEL_MASK                  (0x20U)
+#define SCT_EV_CTRL_OUTSEL_SHIFT                 (5U)
+/*! OUTSEL - Input/Output Select
+ *  0b0..Selects the inputs selected by IOSEL.
+ *  0b1..Selects the outputs selected by IOSEL.
+ */
+#define SCT_EV_CTRL_OUTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
+
+#define SCT_EV_CTRL_IOSEL_MASK                   (0x3C0U)
+#define SCT_EV_CTRL_IOSEL_SHIFT                  (6U)
+/*! IOSEL - Input/Output Signal Select */
+#define SCT_EV_CTRL_IOSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
+
+#define SCT_EV_CTRL_IOCOND_MASK                  (0xC00U)
+#define SCT_EV_CTRL_IOCOND_SHIFT                 (10U)
+/*! IOCOND - Input/Output Condition
+ *  0b00..Low
+ *  0b01..Rise
+ *  0b10..Fall
+ *  0b11..High
+ */
+#define SCT_EV_CTRL_IOCOND(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
+
+#define SCT_EV_CTRL_COMBMODE_MASK                (0x3000U)
+#define SCT_EV_CTRL_COMBMODE_SHIFT               (12U)
+/*! COMBMODE - Combination Mode
+ *  0b00..OR. The event occurs when either the specified match or I/O condition occurs.
+ *  0b01..MATCH. Uses the specified match only.
+ *  0b10..IO. Uses the specified I/O condition only.
+ *  0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
+ */
+#define SCT_EV_CTRL_COMBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
+
+#define SCT_EV_CTRL_STATELD_MASK                 (0x4000U)
+#define SCT_EV_CTRL_STATELD_SHIFT                (14U)
+/*! STATELD - State Load
+ *  0b0..Add. STATEV value is added into STATE (the carry-out is ignored).
+ *  0b1..Load. STATEV value is loaded into STATE.
+ */
+#define SCT_EV_CTRL_STATELD(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
+
+#define SCT_EV_CTRL_STATEV_MASK                  (0xF8000U)
+#define SCT_EV_CTRL_STATEV_SHIFT                 (15U)
+/*! STATEV - State Value */
+#define SCT_EV_CTRL_STATEV(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
+
+#define SCT_EV_CTRL_MATCHMEM_MASK                (0x100000U)
+#define SCT_EV_CTRL_MATCHMEM_SHIFT               (20U)
+/*! MATCHMEM - Match Mem */
+#define SCT_EV_CTRL_MATCHMEM(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
+
+#define SCT_EV_CTRL_DIRECTION_MASK               (0x600000U)
+#define SCT_EV_CTRL_DIRECTION_SHIFT              (21U)
+/*! DIRECTION - Direction
+ *  0b00..Direction independent. This event is triggered regardless of the count direction.
+ *  0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
+ *  0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
+ *  0b11..Reserved
+ */
+#define SCT_EV_CTRL_DIRECTION(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
+/*! @} */
+
+/* The count of SCT_EV_CTRL */
+#define SCT_EV_CTRL_COUNT                        (16U)
+
+/*! @name OUT_SET - Output n Set */
+/*! @{ */
+
+#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT                    (0U)
+/*! SET - Set */
+#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT                        (10U)
+
+/*! @name OUT_CLR - Output n Clear */
+/*! @{ */
+
+#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
+/*! CLR - Clear */
+#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT                        (10U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SCT0 base address */
+  #define SCT0_BASE                                (0x50146000u)
+  /** Peripheral SCT0 base address */
+  #define SCT0_BASE_NS                             (0x40146000u)
+  /** Peripheral SCT0 base pointer */
+  #define SCT0                                     ((SCT_Type *)SCT0_BASE)
+  /** Peripheral SCT0 base pointer */
+  #define SCT0_NS                                  ((SCT_Type *)SCT0_BASE_NS)
+  /** Array initializer of SCT peripheral base addresses */
+  #define SCT_BASE_ADDRS                           { SCT0_BASE }
+  /** Array initializer of SCT peripheral base pointers */
+  #define SCT_BASE_PTRS                            { SCT0 }
+  /** Array initializer of SCT peripheral base addresses */
+  #define SCT_BASE_ADDRS_NS                        { SCT0_BASE_NS }
+  /** Array initializer of SCT peripheral base pointers */
+  #define SCT_BASE_PTRS_NS                         { SCT0_NS }
+#else
+  /** Peripheral SCT0 base address */
+  #define SCT0_BASE                                (0x40146000u)
+  /** Peripheral SCT0 base pointer */
+  #define SCT0                                     ((SCT_Type *)SCT0_BASE)
+  /** Array initializer of SCT peripheral base addresses */
+  #define SCT_BASE_ADDRS                           { SCT0_BASE }
+  /** Array initializer of SCT peripheral base pointers */
+  #define SCT_BASE_PTRS                            { SCT0 }
+#endif
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS                                 { SCT0_IRQn }
+/* Backward compatibility */
+#define SCT_CAP_CAPn_L_MASK                      SCT_CAP_CAPN_L_MASK
+#define SCT_CAP_CAPn_L_SHIFT                     SCT_CAP_CAPN_L_SHIFT
+#define SCT_CAP_CAPn_L(x)                        SCT_CAP_CAPN_L(x)
+#define SCT_CAP_CAPn_H_MASK                      SCT_CAP_CAPN_H_MASK
+#define SCT_CAP_CAPn_H_SHIFT                     SCT_CAP_CAPN_H_SHIFT
+#define SCT_CAP_CAPn_H(x)                        SCT_CAP_CAPN_H(x)
+#define SCT_MATCH_MATCHn_L_MASK                  SCT_MATCH_MATCHN_L_MASK
+#define SCT_MATCH_MATCHn_L_SHIFT                 SCT_MATCH_MATCHN_L_SHIFT
+#define SCT_MATCH_MATCHn_L(x)                    SCT_MATCH_MATCHN_L(x)
+#define SCT_MATCH_MATCHn_H_MASK                  SCT_MATCH_MATCHN_H_MASK
+#define SCT_MATCH_MATCHn_H_SHIFT                 SCT_MATCH_MATCHN_H_SHIFT
+#define SCT_MATCH_MATCHn_H(x)                    SCT_MATCH_MATCHN_H(x)
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK    SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L_MASK
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT   SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L_SHIFT
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L(x)      SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_L(x)
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK    SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H_MASK
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT   SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H_SHIFT
+#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H(x)      SCT_SCTCAPCTRL_CAPCTRL_CAPCONN_H(x)
+#define SCT_MATCHREL_RELOADn_L_MASK              SCT_MATCHREL_RELOADN_L_MASK
+#define SCT_MATCHREL_RELOADn_L_SHIFT             SCT_MATCHREL_RELOADN_L_SHIFT
+#define SCT_MATCHREL_RELOADn_L(x)                SCT_MATCHREL_RELOADN_L(x)
+#define SCT_MATCHREL_RELOADn_H_MASK              SCT_MATCHREL_RELOADN_H_MASK
+#define SCT_MATCHREL_RELOADn_H_SHIFT             SCT_MATCHREL_RELOADN_H_SHIFT
+#define SCT_MATCHREL_RELOADn_H(x)                SCT_MATCHREL_RELOADN_H(x)
+#define SCT_EV_STATE_STATEMSKn_MASK              SCT_EV_STATE_STATEMSKN_MASK
+#define SCT_EV_STATE_STATEMSKn_SHIFT             SCT_EV_STATE_STATEMSKN_SHIFT
+#define SCT_EV_STATE_STATEMSKn(x)                SCT_EV_STATE_STATEMSKN(x)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDU_FBR_CARD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDU_FBR_CARD_Peripheral_Access_Layer SDU_FBR_CARD Peripheral Access Layer
+ * @{
+ */
+
+/** SDU_FBR_CARD - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FN_CODE;                            /**< Function Code, offset: 0x0 */
+  __I  uint8_t FN_EXT_CODE;                        /**< Extended Function Code, offset: 0x1 */
+  __IO uint8_t FN_POWER_SELECT;                    /**< Function Power Select, offset: 0x2 */
+       uint8_t RESERVED_0[2];
+  __I  uint8_t FN_CIS_0;                           /**< Function CIS Pointer 0, offset: 0x5 */
+  __I  uint8_t FN_CIS_1;                           /**< Function CIS Pointer 1, offset: 0x6 */
+  __I  uint8_t FN_CIS_2;                           /**< Function CIS Pointer 2, offset: 0x7 */
+  __I  uint8_t FN_BLOCK_SIZE_0;                    /**< Function Block Size 0, offset: 0x8 */
+  __I  uint8_t FN_BLOCK_SIZE_1;                    /**< Function Block Size 1, offset: 0x9 */
+} SDU_FBR_CARD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDU_FBR_CARD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDU_FBR_CARD_Register_Masks SDU_FBR_CARD Register Masks
+ * @{
+ */
+
+/*! @name FN_CODE - Function Code */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_CODE_CODE_MASK           (0xFU)
+#define SDU_FBR_CARD_FN_CODE_CODE_SHIFT          (0U)
+/*! CODE - Standard I/O device interface code */
+#define SDU_FBR_CARD_FN_CODE_CODE(x)             (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_CODE_CODE_SHIFT)) & SDU_FBR_CARD_FN_CODE_CODE_MASK)
+
+#define SDU_FBR_CARD_FN_CODE_CSA_MASK            (0x40U)
+#define SDU_FBR_CARD_FN_CODE_CSA_SHIFT           (6U)
+/*! CSA - Function supports Code Storage Area (CSA) 0 = function does not support CSA 1 = function supports CSA */
+#define SDU_FBR_CARD_FN_CODE_CSA(x)              (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_CODE_CSA_SHIFT)) & SDU_FBR_CARD_FN_CODE_CSA_MASK)
+
+#define SDU_FBR_CARD_FN_CODE_CSA_EN_MASK         (0x80U)
+#define SDU_FBR_CARD_FN_CODE_CSA_EN_SHIFT        (7U)
+/*! CSA_EN - Function CSA Enable */
+#define SDU_FBR_CARD_FN_CODE_CSA_EN(x)           (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_CODE_CSA_EN_SHIFT)) & SDU_FBR_CARD_FN_CODE_CSA_EN_MASK)
+/*! @} */
+
+/*! @name FN_EXT_CODE - Extended Function Code */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_EXT_CODE_FN_EXT_CODE_MASK (0xFFU)
+#define SDU_FBR_CARD_FN_EXT_CODE_FN_EXT_CODE_SHIFT (0U)
+/*! FN_EXT_CODE - Extended SDIO standard function interface code. */
+#define SDU_FBR_CARD_FN_EXT_CODE_FN_EXT_CODE(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_EXT_CODE_FN_EXT_CODE_SHIFT)) & SDU_FBR_CARD_FN_EXT_CODE_FN_EXT_CODE_MASK)
+/*! @} */
+
+/*! @name FN_POWER_SELECT - Function Power Select */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_POWER_SELECT_SPS_MASK    (0x1U)
+#define SDU_FBR_CARD_FN_POWER_SELECT_SPS_SHIFT   (0U)
+/*! SPS - Power Selection 0 = no power selection 1 = two power modes selected by EPS bit */
+#define SDU_FBR_CARD_FN_POWER_SELECT_SPS(x)      (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_POWER_SELECT_SPS_SHIFT)) & SDU_FBR_CARD_FN_POWER_SELECT_SPS_MASK)
+
+#define SDU_FBR_CARD_FN_POWER_SELECT_EPS_MASK    (0x2U)
+#define SDU_FBR_CARD_FN_POWER_SELECT_EPS_SHIFT   (1U)
+/*! EPS - Current Mode 0 = function operates in high current mode 1 = function operates in low current mode */
+#define SDU_FBR_CARD_FN_POWER_SELECT_EPS(x)      (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_POWER_SELECT_EPS_SHIFT)) & SDU_FBR_CARD_FN_POWER_SELECT_EPS_MASK)
+
+#define SDU_FBR_CARD_FN_POWER_SELECT_FN_PS_MASK  (0xF0U)
+#define SDU_FBR_CARD_FN_POWER_SELECT_FN_PS_SHIFT (4U)
+/*! FN_PS - Power State */
+#define SDU_FBR_CARD_FN_POWER_SELECT_FN_PS(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_POWER_SELECT_FN_PS_SHIFT)) & SDU_FBR_CARD_FN_POWER_SELECT_FN_PS_MASK)
+/*! @} */
+
+/*! @name FN_CIS_0 - Function CIS Pointer 0 */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_CIS_0_FN_CIS_PTR0_MASK   (0xFFU)
+#define SDU_FBR_CARD_FN_CIS_0_FN_CIS_PTR0_SHIFT  (0U)
+/*! FN_CIS_PTR0 - 24b Function Pointer [7:0] Function card information structure pointer [7:0]
+ *    Function n CIS pointer is (0x8000 | n << 7) Therefore, Function 1 CIS pointer is 0x008080 Function
+ *    2 CIS pointer is 0x008100 Function 3 CIS pointer is 0x008180 ... Function 7 CIS pointer is
+ *    0x008380
+ */
+#define SDU_FBR_CARD_FN_CIS_0_FN_CIS_PTR0(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_CIS_0_FN_CIS_PTR0_SHIFT)) & SDU_FBR_CARD_FN_CIS_0_FN_CIS_PTR0_MASK)
+/*! @} */
+
+/*! @name FN_CIS_1 - Function CIS Pointer 1 */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_CIS_1_FN_CIS_PTR1_MASK   (0xFFU)
+#define SDU_FBR_CARD_FN_CIS_1_FN_CIS_PTR1_SHIFT  (0U)
+/*! FN_CIS_PTR1 - 24b Function 1 Pointer [15:8] Function card information structure pointer [15:8] */
+#define SDU_FBR_CARD_FN_CIS_1_FN_CIS_PTR1(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_CIS_1_FN_CIS_PTR1_SHIFT)) & SDU_FBR_CARD_FN_CIS_1_FN_CIS_PTR1_MASK)
+/*! @} */
+
+/*! @name FN_CIS_2 - Function CIS Pointer 2 */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_CIS_2_FN_CIS_PTR2_MASK   (0xFFU)
+#define SDU_FBR_CARD_FN_CIS_2_FN_CIS_PTR2_SHIFT  (0U)
+/*! FN_CIS_PTR2 - 24b Function 1 Pointer [23:16] Function card information structure pointer [23:16] */
+#define SDU_FBR_CARD_FN_CIS_2_FN_CIS_PTR2(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_CIS_2_FN_CIS_PTR2_SHIFT)) & SDU_FBR_CARD_FN_CIS_2_FN_CIS_PTR2_MASK)
+/*! @} */
+
+/*! @name FN_BLOCK_SIZE_0 - Function Block Size 0 */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_BLOCK_SIZE_0_FN_BLK_SIZE0_MASK (0xFFU)
+#define SDU_FBR_CARD_FN_BLOCK_SIZE_0_FN_BLK_SIZE0_SHIFT (0U)
+/*! FN_BLK_SIZE0 - Block Size [7:0] for I/O Block Operation */
+#define SDU_FBR_CARD_FN_BLOCK_SIZE_0_FN_BLK_SIZE0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_BLOCK_SIZE_0_FN_BLK_SIZE0_SHIFT)) & SDU_FBR_CARD_FN_BLOCK_SIZE_0_FN_BLK_SIZE0_MASK)
+/*! @} */
+
+/*! @name FN_BLOCK_SIZE_1 - Function Block Size 1 */
+/*! @{ */
+
+#define SDU_FBR_CARD_FN_BLOCK_SIZE_1_FN_BLK_SIZE1_MASK (0x1U)
+#define SDU_FBR_CARD_FN_BLOCK_SIZE_1_FN_BLK_SIZE1_SHIFT (0U)
+/*! FN_BLK_SIZE1 - Block Size [8] for I/O Block Operation */
+#define SDU_FBR_CARD_FN_BLOCK_SIZE_1_FN_BLK_SIZE1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FBR_CARD_FN_BLOCK_SIZE_1_FN_BLK_SIZE1_SHIFT)) & SDU_FBR_CARD_FN_BLOCK_SIZE_1_FN_BLK_SIZE1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SDU_FBR_CARD_Register_Masks */
+
+
+/* SDU_FBR_CARD - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SDU_FBR_CARD base address */
+  #define SDU_FBR_CARD_BASE                        (0x50158020u)
+  /** Peripheral SDU_FBR_CARD base address */
+  #define SDU_FBR_CARD_BASE_NS                     (0x40158020u)
+  /** Peripheral SDU_FBR_CARD base pointer */
+  #define SDU_FBR_CARD                             ((SDU_FBR_CARD_Type *)SDU_FBR_CARD_BASE)
+  /** Peripheral SDU_FBR_CARD base pointer */
+  #define SDU_FBR_CARD_NS                          ((SDU_FBR_CARD_Type *)SDU_FBR_CARD_BASE_NS)
+  /** Array initializer of SDU_FBR_CARD peripheral base addresses */
+  #define SDU_FBR_CARD_BASE_ADDRS                  { SDU_FBR_CARD_BASE }
+  /** Array initializer of SDU_FBR_CARD peripheral base pointers */
+  #define SDU_FBR_CARD_BASE_PTRS                   { SDU_FBR_CARD }
+  /** Array initializer of SDU_FBR_CARD peripheral base addresses */
+  #define SDU_FBR_CARD_BASE_ADDRS_NS               { SDU_FBR_CARD_BASE_NS }
+  /** Array initializer of SDU_FBR_CARD peripheral base pointers */
+  #define SDU_FBR_CARD_BASE_PTRS_NS                { SDU_FBR_CARD_NS }
+#else
+  /** Peripheral SDU_FBR_CARD base address */
+  #define SDU_FBR_CARD_BASE                        (0x40158020u)
+  /** Peripheral SDU_FBR_CARD base pointer */
+  #define SDU_FBR_CARD                             ((SDU_FBR_CARD_Type *)SDU_FBR_CARD_BASE)
+  /** Array initializer of SDU_FBR_CARD peripheral base addresses */
+  #define SDU_FBR_CARD_BASE_ADDRS                  { SDU_FBR_CARD_BASE }
+  /** Array initializer of SDU_FBR_CARD peripheral base pointers */
+  #define SDU_FBR_CARD_BASE_PTRS                   { SDU_FBR_CARD }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SDU_FBR_CARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDU_FN0_CARD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDU_FN0_CARD_Peripheral_Access_Layer SDU_FN0_CARD Peripheral Access Layer
+ * @{
+ */
+
+/** SDU_FN0_CARD - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CCCR;                               /**< CCCR/SDIO Revision, offset: 0x0 */
+  __IO uint8_t VER;                                /**< SD Specification Revision, offset: 0x1 */
+  __I  uint8_t IO_ENABLE;                          /**< I/O Enable, offset: 0x2 */
+  __I  uint8_t IO_READY;                           /**< I/O Function Ready, offset: 0x3 */
+  __I  uint8_t INT_ENABLE;                         /**< Interrupt Enable, offset: 0x4 */
+  __I  uint8_t INT_PENDING;                        /**< Interrupt Pending, offset: 0x5 */
+  __I  uint8_t IO_ABORT;                           /**< I/O Abort, offset: 0x6 */
+  __IO uint8_t BUS_INTF_CTRL;                      /**< Bus Interface Control, offset: 0x7 */
+  __I  uint8_t CAPAB;                              /**< Card Capability, offset: 0x8 */
+  __I  uint8_t FUNC0_CIS_0;                        /**< Function 0 CIS Pointer 0, offset: 0x9 */
+  __I  uint8_t FUNC0_CIS_1;                        /**< Function 0 CIS Pointer 1, offset: 0xA */
+  __I  uint8_t FUNC0_CIS_2;                        /**< Function 0 CIS Pointer 2, offset: 0xB */
+  __I  uint8_t BUS_SUSP;                           /**< Bus Suspend, offset: 0xC */
+  __I  uint8_t BUS_SEL;                            /**< Function Select, offset: 0xD */
+  __I  uint8_t EXEC;                               /**< Execute Flags, offset: 0xE */
+  __I  uint8_t READY;                              /**< Ready Flags, offset: 0xF */
+  __I  uint8_t FN0_BLOCK_SIZE_0;                   /**< Function 0 Block Size 0, offset: 0x10 */
+  __I  uint8_t FN0_BLOCK_SIZE_1;                   /**< Function 0 Block Size 1, offset: 0x11 */
+  __IO uint8_t POWER_CONTROL;                      /**< Power Control, offset: 0x12 */
+  __IO uint8_t BUS_SPEED_SELECT;                   /**< Bus Speed Select, offset: 0x13 */
+  __IO uint8_t UHS_SUPPORT;                        /**< UHS-I Support, offset: 0x14 */
+  __IO uint8_t DRIVER_STR;                         /**< Driver Strength, offset: 0x15 */
+  __IO uint8_t INTERRUPT_EXT;                      /**< Interrupt Extension, offset: 0x16 */
+       uint8_t RESERVED_0[117];
+  __IO uint8_t CARD_CTRL1;                         /**< Card Control 1, offset: 0x8C */
+  __IO uint8_t CARD_CTRL2;                         /**< Card Control 2, offset: 0x8D */
+  __IO uint8_t CMD19_CTRL1;                        /**< CMD19 Control1, offset: 0x8E */
+  __IO uint8_t CMD19_CTRL2;                        /**< CMD19 Control2, offset: 0x8F */
+  __I  uint8_t FUNC_CARD_INT;                      /**< Function Card Interrupt, offset: 0x90 */
+  __IO uint8_t FUNC0_CARD_INTMASK;                 /**< Function Card Interrupt Mask, offset: 0x91 */
+  __IO uint8_t DEV_SLEEP;                          /**< Device Sleep, offset: 0x92 */
+  __IO uint8_t CARD_CTRL3;                         /**< Card Control 3, offset: 0x93 */
+  __IO uint8_t FN0_CARD_INTMASK0;                  /**< Function 0 Card Interrupt Mask 0, offset: 0x94 */
+  __IO uint8_t FN0_CARD_INTMASK1;                  /**< Function 0 Card Interrupt Mask 1, offset: 0x95 */
+  __IO uint8_t FN0_CARD_INTRSR0;                   /**< Function 0 Card Interrupt Reset Select 0, offset: 0x96 */
+  __IO uint8_t FN0_CARD_INTRSR1;                   /**< Function 0 Card Interrupt Reset Select 1, offset: 0x97 */
+  __I  uint8_t FN0_CARD_INTSTATUS0;                /**< Function 0 Card Interrupt Status 0, offset: 0x98 */
+  __I  uint8_t FN0_CARD_INTSTATUS1;                /**< Function 0 Card Interrupt Status 1, offset: 0x99 */
+  __I  uint8_t FN0_CARD_ACTVINTMASK0;              /**< Function 0 Card Active Interrupt Mask 0, offset: 0x9A */
+  __I  uint8_t FN0_CARD_ACTVINTMASK1;              /**< Function 0 Card Active Interrupt Mask 1, offset: 0x9B */
+  __IO uint8_t CARD_CTRL4;                         /**< Card Control 4, offset: 0x9C */
+  __IO uint8_t CARD_CTRL5;                         /**< Card Control 5, offset: 0x9D */
+  __IO uint8_t CARD_CTRL6;                         /**< Card Control 6, offset: 0x9E */
+  __IO uint8_t CARD_CTRL7;                         /**< Card Control 7, offset: 0x9F */
+} SDU_FN0_CARD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDU_FN0_CARD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDU_FN0_CARD_Register_Masks SDU_FN0_CARD Register Masks
+ * @{
+ */
+
+/*! @name CCCR - CCCR/SDIO Revision */
+/*! @{ */
+
+#define SDU_FN0_CARD_CCCR_CCCR_REV_MASK          (0xFU)
+#define SDU_FN0_CARD_CCCR_CCCR_REV_SHIFT         (0U)
+/*! CCCR_REV - CCCR Format Version Number Version of the CCCR format that this card supports. */
+#define SDU_FN0_CARD_CCCR_CCCR_REV(x)            (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CCCR_CCCR_REV_SHIFT)) & SDU_FN0_CARD_CCCR_CCCR_REV_MASK)
+
+#define SDU_FN0_CARD_CCCR_SDIO_REV_MASK          (0xF0U)
+#define SDU_FN0_CARD_CCCR_SDIO_REV_SHIFT         (4U)
+/*! SDIO_REV - SDIO Specification Revision Number Version of the SDIO specification that this card supports. */
+#define SDU_FN0_CARD_CCCR_SDIO_REV(x)            (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CCCR_SDIO_REV_SHIFT)) & SDU_FN0_CARD_CCCR_SDIO_REV_MASK)
+/*! @} */
+
+/*! @name VER - SD Specification Revision */
+/*! @{ */
+
+#define SDU_FN0_CARD_VER_SD_PHY_REV_MASK         (0xFU)
+#define SDU_FN0_CARD_VER_SD_PHY_REV_SHIFT        (0U)
+/*! SD_PHY_REV - SD Format Version Number Version of the SD Physical specification that this card supports. */
+#define SDU_FN0_CARD_VER_SD_PHY_REV(x)           (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_VER_SD_PHY_REV_SHIFT)) & SDU_FN0_CARD_VER_SD_PHY_REV_MASK)
+/*! @} */
+
+/*! @name IO_ENABLE - I/O Enable */
+/*! @{ */
+
+#define SDU_FN0_CARD_IO_ENABLE_IOE_MASK          (0xFEU)
+#define SDU_FN0_CARD_IO_ENABLE_IOE_SHIFT         (1U)
+/*! IOE - Function I/O enable 0 = function disabled 1 = function enabled */
+#define SDU_FN0_CARD_IO_ENABLE_IOE(x)            (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_IO_ENABLE_IOE_SHIFT)) & SDU_FN0_CARD_IO_ENABLE_IOE_MASK)
+/*! @} */
+
+/*! @name IO_READY - I/O Function Ready */
+/*! @{ */
+
+#define SDU_FN0_CARD_IO_READY_FN_IO_RDY_MASK     (0xFEU)
+#define SDU_FN0_CARD_IO_READY_FN_IO_RDY_SHIFT    (1U)
+/*! FN_IO_RDY - Function I/O ready 0 = function not ready to operate 1 = function ready to operate */
+#define SDU_FN0_CARD_IO_READY_FN_IO_RDY(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_IO_READY_FN_IO_RDY_SHIFT)) & SDU_FN0_CARD_IO_READY_FN_IO_RDY_MASK)
+/*! @} */
+
+/*! @name INT_ENABLE - Interrupt Enable */
+/*! @{ */
+
+#define SDU_FN0_CARD_INT_ENABLE_HOST_IEN_MASK    (0x1U)
+#define SDU_FN0_CARD_INT_ENABLE_HOST_IEN_SHIFT   (0U)
+/*! HOST_IEN - Host Interrupt Enable 0 = no interrupts from this card sent to host 1 = any function's interrupt sent to host */
+#define SDU_FN0_CARD_INT_ENABLE_HOST_IEN(x)      (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_INT_ENABLE_HOST_IEN_SHIFT)) & SDU_FN0_CARD_INT_ENABLE_HOST_IEN_MASK)
+
+#define SDU_FN0_CARD_INT_ENABLE_IEN_MASK         (0xFEU)
+#define SDU_FN0_CARD_INT_ENABLE_IEN_SHIFT        (1U)
+/*! IEN - Function Interrupt Enable 0 = interrupt from this function not sent to host 1 = interrupt
+ *    from this function sent to host (host_ien must also be set)
+ */
+#define SDU_FN0_CARD_INT_ENABLE_IEN(x)           (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_INT_ENABLE_IEN_SHIFT)) & SDU_FN0_CARD_INT_ENABLE_IEN_MASK)
+/*! @} */
+
+/*! @name INT_PENDING - Interrupt Pending */
+/*! @{ */
+
+#define SDU_FN0_CARD_INT_PENDING_FN_INT_HOST_MASK (0xFEU)
+#define SDU_FN0_CARD_INT_PENDING_FN_INT_HOST_SHIFT (1U)
+/*! FN_INT_HOST - Function Interrupt Pending 0 = no interrupts pending from this function 1 =
+ *    interrupt pending If the ien[x] or host_ien bits are not set in INT_ENABLE, the host will not
+ *    receive the pending interrupt.
+ */
+#define SDU_FN0_CARD_INT_PENDING_FN_INT_HOST(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_INT_PENDING_FN_INT_HOST_SHIFT)) & SDU_FN0_CARD_INT_PENDING_FN_INT_HOST_MASK)
+/*! @} */
+
+/*! @name IO_ABORT - I/O Abort */
+/*! @{ */
+
+#define SDU_FN0_CARD_IO_ABORT_ABORT_SEL_MASK     (0x7U)
+#define SDU_FN0_CARD_IO_ABORT_ABORT_SEL_SHIFT    (0U)
+/*! ABORT_SEL - Abort Select To abort an I/O read or write to free the SD bus, the function that is
+ *    currently transferring data must be addressed.
+ */
+#define SDU_FN0_CARD_IO_ABORT_ABORT_SEL(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_IO_ABORT_ABORT_SEL_SHIFT)) & SDU_FN0_CARD_IO_ABORT_ABORT_SEL_MASK)
+
+#define SDU_FN0_CARD_IO_ABORT_IO_CARD_RST_MASK   (0x8U)
+#define SDU_FN0_CARD_IO_ABORT_IO_CARD_RST_SHIFT  (3U)
+/*! IO_CARD_RST - I/O Card Reset If host sets this bit, an interrupt is generated to the card. */
+#define SDU_FN0_CARD_IO_ABORT_IO_CARD_RST(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_IO_ABORT_IO_CARD_RST_SHIFT)) & SDU_FN0_CARD_IO_ABORT_IO_CARD_RST_MASK)
+/*! @} */
+
+/*! @name BUS_INTF_CTRL - Bus Interface Control */
+/*! @{ */
+
+#define SDU_FN0_CARD_BUS_INTF_CTRL_BUS_WIDTH_MASK (0x3U)
+#define SDU_FN0_CARD_BUS_INTF_CTRL_BUS_WIDTH_SHIFT (0U)
+/*! BUS_WIDTH - Bus Width Data bus width used for data transfer 00 = 1 bit 10 = 4 bits All
+ *    full-speed SDIO cards support both 1-bit and 4-bit bus.
+ */
+#define SDU_FN0_CARD_BUS_INTF_CTRL_BUS_WIDTH(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_INTF_CTRL_BUS_WIDTH_SHIFT)) & SDU_FN0_CARD_BUS_INTF_CTRL_BUS_WIDTH_MASK)
+
+#define SDU_FN0_CARD_BUS_INTF_CTRL_ECSI_MASK     (0x20U)
+#define SDU_FN0_CARD_BUS_INTF_CTRL_ECSI_SHIFT    (5U)
+/*! ECSI - ecsi */
+#define SDU_FN0_CARD_BUS_INTF_CTRL_ECSI(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_INTF_CTRL_ECSI_SHIFT)) & SDU_FN0_CARD_BUS_INTF_CTRL_ECSI_MASK)
+
+#define SDU_FN0_CARD_BUS_INTF_CTRL_SCSI_MASK     (0x40U)
+#define SDU_FN0_CARD_BUS_INTF_CTRL_SCSI_SHIFT    (6U)
+/*! SCSI - Support continuous SPI Interrupt writable from internal bus only 0 = SPI supports
+ *    interrupt assertion only when CS (SD)DAT[3] pin) is asserted 1 = SPI supports interrupt assertion
+ *    independent of CS
+ */
+#define SDU_FN0_CARD_BUS_INTF_CTRL_SCSI(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_INTF_CTRL_SCSI_SHIFT)) & SDU_FN0_CARD_BUS_INTF_CTRL_SCSI_MASK)
+
+#define SDU_FN0_CARD_BUS_INTF_CTRL_CD_DISABLE_MASK (0x80U)
+#define SDU_FN0_CARD_BUS_INTF_CTRL_CD_DISABLE_SHIFT (7U)
+/*! CD_DISABLE - Connect/Disconnet Disable Connect[0]/disconnect[1] the 10K-90 kO pull-up resistor on pin 1 of card. */
+#define SDU_FN0_CARD_BUS_INTF_CTRL_CD_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_INTF_CTRL_CD_DISABLE_SHIFT)) & SDU_FN0_CARD_BUS_INTF_CTRL_CD_DISABLE_MASK)
+/*! @} */
+
+/*! @name CAPAB - Card Capability */
+/*! @{ */
+
+#define SDU_FN0_CARD_CAPAB_SDC_MASK              (0x1U)
+#define SDU_FN0_CARD_CAPAB_SDC_SHIFT             (0U)
+/*! SDC - Support Direct Commands Card supports direct commands during multi-byte transfer 0 = all
+ *    I/O functions do not accept and execute 1 = all I/O functions accept and execute
+ */
+#define SDU_FN0_CARD_CAPAB_SDC(x)                (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CAPAB_SDC_SHIFT)) & SDU_FN0_CARD_CAPAB_SDC_MASK)
+
+#define SDU_FN0_CARD_CAPAB_SMB_MASK              (0x2U)
+#define SDU_FN0_CARD_CAPAB_SMB_SHIFT             (1U)
+/*! SMB - Support Multi-Block Card supports multi block indicator 0 = all I/O functions do not
+ *    accept and execute 1 = all I/O functions accept and execute
+ */
+#define SDU_FN0_CARD_CAPAB_SMB(x)                (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CAPAB_SMB_SHIFT)) & SDU_FN0_CARD_CAPAB_SMB_MASK)
+
+#define SDU_FN0_CARD_CAPAB_S4MI_MASK             (0x10U)
+#define SDU_FN0_CARD_CAPAB_S4MI_SHIFT            (4U)
+/*! S4MI - Support 4-bit Mode Interrupt Supports interrupt between blocks of data in 4-bit mode 0 =
+ *    card not able to signal an interrupt during a 4-bit multi-block data transfer 1 = card is able
+ *    to signal an interrupt between blocks during data transfer
+ */
+#define SDU_FN0_CARD_CAPAB_S4MI(x)               (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CAPAB_S4MI_SHIFT)) & SDU_FN0_CARD_CAPAB_S4MI_MASK)
+
+#define SDU_FN0_CARD_CAPAB_E4MI_MASK             (0x20U)
+#define SDU_FN0_CARD_CAPAB_E4MI_SHIFT            (5U)
+/*! E4MI - Enable 4-bit Mode Interrupt Enable interrupt between blocks of data in 4-bit mode. */
+#define SDU_FN0_CARD_CAPAB_E4MI(x)               (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CAPAB_E4MI_SHIFT)) & SDU_FN0_CARD_CAPAB_E4MI_MASK)
+/*! @} */
+
+/*! @name FUNC0_CIS_0 - Function 0 CIS Pointer 0 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FUNC0_CIS_0_F0_CIS_PTR0_MASK (0xFFU)
+#define SDU_FN0_CARD_FUNC0_CIS_0_F0_CIS_PTR0_SHIFT (0U)
+/*! F0_CIS_PTR0 - CIS Pointer Bits[7:0] */
+#define SDU_FN0_CARD_FUNC0_CIS_0_F0_CIS_PTR0(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FUNC0_CIS_0_F0_CIS_PTR0_SHIFT)) & SDU_FN0_CARD_FUNC0_CIS_0_F0_CIS_PTR0_MASK)
+/*! @} */
+
+/*! @name FUNC0_CIS_1 - Function 0 CIS Pointer 1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FUNC0_CIS_1_F0_CIS_PTR1_MASK (0xFFU)
+#define SDU_FN0_CARD_FUNC0_CIS_1_F0_CIS_PTR1_SHIFT (0U)
+/*! F0_CIS_PTR1 - CIS Pointer Bits[15:8] */
+#define SDU_FN0_CARD_FUNC0_CIS_1_F0_CIS_PTR1(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FUNC0_CIS_1_F0_CIS_PTR1_SHIFT)) & SDU_FN0_CARD_FUNC0_CIS_1_F0_CIS_PTR1_MASK)
+/*! @} */
+
+/*! @name FUNC0_CIS_2 - Function 0 CIS Pointer 2 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FUNC0_CIS_2_F0_CIS_PTR2_MASK (0xFFU)
+#define SDU_FN0_CARD_FUNC0_CIS_2_F0_CIS_PTR2_SHIFT (0U)
+/*! F0_CIS_PTR2 - CIS Pointer Bits[23:16] */
+#define SDU_FN0_CARD_FUNC0_CIS_2_F0_CIS_PTR2(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FUNC0_CIS_2_F0_CIS_PTR2_SHIFT)) & SDU_FN0_CARD_FUNC0_CIS_2_F0_CIS_PTR2_MASK)
+/*! @} */
+
+/*! @name BUS_SUSP - Bus Suspend */
+/*! @{ */
+
+#define SDU_FN0_CARD_BUS_SUSP_BUS_STATUS_MASK    (0x1U)
+#define SDU_FN0_CARD_BUS_SUSP_BUS_STATUS_SHIFT   (0U)
+/*! BUS_STATUS - Bus Status Bus status indicator 0 = N/A 1 = currently addressed function is currently executing a command */
+#define SDU_FN0_CARD_BUS_SUSP_BUS_STATUS(x)      (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_SUSP_BUS_STATUS_SHIFT)) & SDU_FN0_CARD_BUS_SUSP_BUS_STATUS_MASK)
+
+#define SDU_FN0_CARD_BUS_SUSP_BUS_RELEASE_MASK   (0x2U)
+#define SDU_FN0_CARD_BUS_SUSP_BUS_RELEASE_SHIFT  (1U)
+/*! BUS_RELEASE - Bus Release Bus release request/status indicator 0 = N/A 1 = suspend request still in progress */
+#define SDU_FN0_CARD_BUS_SUSP_BUS_RELEASE(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_SUSP_BUS_RELEASE_SHIFT)) & SDU_FN0_CARD_BUS_SUSP_BUS_RELEASE_MASK)
+/*! @} */
+
+/*! @name BUS_SEL - Function Select */
+/*! @{ */
+
+#define SDU_FN0_CARD_BUS_SEL_FN_SELECT_MASK      (0xFU)
+#define SDU_FN0_CARD_BUS_SEL_FN_SELECT_SHIFT     (0U)
+/*! FN_SELECT - Select Function (Not used) */
+#define SDU_FN0_CARD_BUS_SEL_FN_SELECT(x)        (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_SEL_FN_SELECT_SHIFT)) & SDU_FN0_CARD_BUS_SEL_FN_SELECT_MASK)
+
+#define SDU_FN0_CARD_BUS_SEL_DATA_FLAG_MASK      (0x80U)
+#define SDU_FN0_CARD_BUS_SEL_DATA_FLAG_SHIFT     (7U)
+/*! DATA_FLAG - Data Flag (Not used) */
+#define SDU_FN0_CARD_BUS_SEL_DATA_FLAG(x)        (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_SEL_DATA_FLAG_SHIFT)) & SDU_FN0_CARD_BUS_SEL_DATA_FLAG_MASK)
+/*! @} */
+
+/*! @name EXEC - Execute Flags */
+/*! @{ */
+
+#define SDU_FN0_CARD_EXEC_MEM_EXEC_MASK          (0x1U)
+#define SDU_FN0_CARD_EXEC_MEM_EXEC_SHIFT         (0U)
+/*! MEM_EXEC - Execution Flag for memory (Not used) */
+#define SDU_FN0_CARD_EXEC_MEM_EXEC(x)            (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_EXEC_MEM_EXEC_SHIFT)) & SDU_FN0_CARD_EXEC_MEM_EXEC_MASK)
+
+#define SDU_FN0_CARD_EXEC_FN_EXEC_MASK           (0xFEU)
+#define SDU_FN0_CARD_EXEC_FN_EXEC_SHIFT          (1U)
+/*! FN_EXEC - Execution Flag for functions (Not used) */
+#define SDU_FN0_CARD_EXEC_FN_EXEC(x)             (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_EXEC_FN_EXEC_SHIFT)) & SDU_FN0_CARD_EXEC_FN_EXEC_MASK)
+/*! @} */
+
+/*! @name READY - Ready Flags */
+/*! @{ */
+
+#define SDU_FN0_CARD_READY_MEM_RDY_FLAG_MASK     (0x1U)
+#define SDU_FN0_CARD_READY_MEM_RDY_FLAG_SHIFT    (0U)
+/*! MEM_RDY_FLAG - Ready Flag for memory (Not used) */
+#define SDU_FN0_CARD_READY_MEM_RDY_FLAG(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_READY_MEM_RDY_FLAG_SHIFT)) & SDU_FN0_CARD_READY_MEM_RDY_FLAG_MASK)
+
+#define SDU_FN0_CARD_READY_FN_RDY_FLAG_MASK      (0xFEU)
+#define SDU_FN0_CARD_READY_FN_RDY_FLAG_SHIFT     (1U)
+/*! FN_RDY_FLAG - Ready Flag for functions (Not used) */
+#define SDU_FN0_CARD_READY_FN_RDY_FLAG(x)        (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_READY_FN_RDY_FLAG_SHIFT)) & SDU_FN0_CARD_READY_FN_RDY_FLAG_MASK)
+/*! @} */
+
+/*! @name FN0_BLOCK_SIZE_0 - Function 0 Block Size 0 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_BLOCK_SIZE_0_FN0_BLK_SIZE0_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_BLOCK_SIZE_0_FN0_BLK_SIZE0_SHIFT (0U)
+/*! FN0_BLK_SIZE0 - Block size [7:0] for Function 0 I/O block operations */
+#define SDU_FN0_CARD_FN0_BLOCK_SIZE_0_FN0_BLK_SIZE0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_BLOCK_SIZE_0_FN0_BLK_SIZE0_SHIFT)) & SDU_FN0_CARD_FN0_BLOCK_SIZE_0_FN0_BLK_SIZE0_MASK)
+/*! @} */
+
+/*! @name FN0_BLOCK_SIZE_1 - Function 0 Block Size 1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_BLOCK_SIZE_1_FN0_BLK_SIZE1_MASK (0x1U)
+#define SDU_FN0_CARD_FN0_BLOCK_SIZE_1_FN0_BLK_SIZE1_SHIFT (0U)
+/*! FN0_BLK_SIZE1 - Block size [8] for Function 0 I/O block operations */
+#define SDU_FN0_CARD_FN0_BLOCK_SIZE_1_FN0_BLK_SIZE1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_BLOCK_SIZE_1_FN0_BLK_SIZE1_SHIFT)) & SDU_FN0_CARD_FN0_BLOCK_SIZE_1_FN0_BLK_SIZE1_MASK)
+/*! @} */
+
+/*! @name POWER_CONTROL - Power Control */
+/*! @{ */
+
+#define SDU_FN0_CARD_POWER_CONTROL_SMPC_MASK     (0x1U)
+#define SDU_FN0_CARD_POWER_CONTROL_SMPC_SHIFT    (0U)
+/*! SMPC - Support Master Power Control 0 = do not support 1 = support */
+#define SDU_FN0_CARD_POWER_CONTROL_SMPC(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_POWER_CONTROL_SMPC_SHIFT)) & SDU_FN0_CARD_POWER_CONTROL_SMPC_MASK)
+
+#define SDU_FN0_CARD_POWER_CONTROL_EMPC_MASK     (0x2U)
+#define SDU_FN0_CARD_POWER_CONTROL_EMPC_SHIFT    (1U)
+/*! EMPC - Enable Master Power Control 0 = disable 1 = enable */
+#define SDU_FN0_CARD_POWER_CONTROL_EMPC(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_POWER_CONTROL_EMPC_SHIFT)) & SDU_FN0_CARD_POWER_CONTROL_EMPC_MASK)
+/*! @} */
+
+/*! @name BUS_SPEED_SELECT - Bus Speed Select */
+/*! @{ */
+
+#define SDU_FN0_CARD_BUS_SPEED_SELECT_SHS_MASK   (0x1U)
+#define SDU_FN0_CARD_BUS_SPEED_SELECT_SHS_SHIFT  (0U)
+/*! SHS - Support High Speed Mode 0 = do not support 1 = support */
+#define SDU_FN0_CARD_BUS_SPEED_SELECT_SHS(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_SPEED_SELECT_SHS_SHIFT)) & SDU_FN0_CARD_BUS_SPEED_SELECT_SHS_MASK)
+
+#define SDU_FN0_CARD_BUS_SPEED_SELECT_BSS_MASK   (0xEU)
+#define SDU_FN0_CARD_BUS_SPEED_SELECT_BSS_SHIFT  (1U)
+/*! BSS - Select Ultra High Speed Mode BSS Bus speed(1. */
+#define SDU_FN0_CARD_BUS_SPEED_SELECT_BSS(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_BUS_SPEED_SELECT_BSS_SHIFT)) & SDU_FN0_CARD_BUS_SPEED_SELECT_BSS_MASK)
+/*! @} */
+
+/*! @name UHS_SUPPORT - UHS-I Support */
+/*! @{ */
+
+#define SDU_FN0_CARD_UHS_SUPPORT_SSDR50_MASK     (0x1U)
+#define SDU_FN0_CARD_UHS_SUPPORT_SSDR50_SHIFT    (0U)
+/*! SSDR50 - This bit indicates support of sdr50. */
+#define SDU_FN0_CARD_UHS_SUPPORT_SSDR50(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_UHS_SUPPORT_SSDR50_SHIFT)) & SDU_FN0_CARD_UHS_SUPPORT_SSDR50_MASK)
+
+#define SDU_FN0_CARD_UHS_SUPPORT_SSDR104_MASK    (0x2U)
+#define SDU_FN0_CARD_UHS_SUPPORT_SSDR104_SHIFT   (1U)
+/*! SSDR104 - This bit indicates support of sdr104. */
+#define SDU_FN0_CARD_UHS_SUPPORT_SSDR104(x)      (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_UHS_SUPPORT_SSDR104_SHIFT)) & SDU_FN0_CARD_UHS_SUPPORT_SSDR104_MASK)
+
+#define SDU_FN0_CARD_UHS_SUPPORT_SDDR50_MASK     (0x4U)
+#define SDU_FN0_CARD_UHS_SUPPORT_SDDR50_SHIFT    (2U)
+/*! SDDR50 - This bit indicates support of ddr50. */
+#define SDU_FN0_CARD_UHS_SUPPORT_SDDR50(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_UHS_SUPPORT_SDDR50_SHIFT)) & SDU_FN0_CARD_UHS_SUPPORT_SDDR50_MASK)
+/*! @} */
+
+/*! @name DRIVER_STR - Driver Strength */
+/*! @{ */
+
+#define SDU_FN0_CARD_DRIVER_STR_SDTA_MASK        (0x1U)
+#define SDU_FN0_CARD_DRIVER_STR_SDTA_SHIFT       (0U)
+/*! SDTA - Support Driver Type A This bit indicates support of Driver Type A */
+#define SDU_FN0_CARD_DRIVER_STR_SDTA(x)          (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_DRIVER_STR_SDTA_SHIFT)) & SDU_FN0_CARD_DRIVER_STR_SDTA_MASK)
+
+#define SDU_FN0_CARD_DRIVER_STR_SDTC_MASK        (0x2U)
+#define SDU_FN0_CARD_DRIVER_STR_SDTC_SHIFT       (1U)
+/*! SDTC - Support Driver Type C This bit indicates support of Driver Type C */
+#define SDU_FN0_CARD_DRIVER_STR_SDTC(x)          (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_DRIVER_STR_SDTC_SHIFT)) & SDU_FN0_CARD_DRIVER_STR_SDTC_MASK)
+
+#define SDU_FN0_CARD_DRIVER_STR_SDTD_MASK        (0x4U)
+#define SDU_FN0_CARD_DRIVER_STR_SDTD_SHIFT       (2U)
+/*! SDTD - Support Driver Type D This bit indicates support of Driver Type D */
+#define SDU_FN0_CARD_DRIVER_STR_SDTD(x)          (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_DRIVER_STR_SDTD_SHIFT)) & SDU_FN0_CARD_DRIVER_STR_SDTD_MASK)
+
+#define SDU_FN0_CARD_DRIVER_STR_DTS_MASK         (0x30U)
+#define SDU_FN0_CARD_DRIVER_STR_DTS_SHIFT        (4U)
+/*! DTS - Driver Type Select */
+#define SDU_FN0_CARD_DRIVER_STR_DTS(x)           (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_DRIVER_STR_DTS_SHIFT)) & SDU_FN0_CARD_DRIVER_STR_DTS_MASK)
+/*! @} */
+
+/*! @name INTERRUPT_EXT - Interrupt Extension */
+/*! @{ */
+
+#define SDU_FN0_CARD_INTERRUPT_EXT_SAI_MASK      (0x1U)
+#define SDU_FN0_CARD_INTERRUPT_EXT_SAI_SHIFT     (0U)
+/*! SAI - Support Asynchronous Interrupt Support bit of asynchronous interrupt. */
+#define SDU_FN0_CARD_INTERRUPT_EXT_SAI(x)        (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_INTERRUPT_EXT_SAI_SHIFT)) & SDU_FN0_CARD_INTERRUPT_EXT_SAI_MASK)
+
+#define SDU_FN0_CARD_INTERRUPT_EXT_EAI_MASK      (0x2U)
+#define SDU_FN0_CARD_INTERRUPT_EXT_EAI_SHIFT     (1U)
+/*! EAI - Enable Asynchronous Interrupt Enable bit of asynchronous interrupt. */
+#define SDU_FN0_CARD_INTERRUPT_EXT_EAI(x)        (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_INTERRUPT_EXT_EAI_SHIFT)) & SDU_FN0_CARD_INTERRUPT_EXT_EAI_MASK)
+/*! @} */
+
+/*! @name CARD_CTRL1 - Card Control 1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CARD_CTRL1_CMD52_WR_ERR_WKUP_EN_MASK (0x1U)
+#define SDU_FN0_CARD_CARD_CTRL1_CMD52_WR_ERR_WKUP_EN_SHIFT (0U)
+/*! CMD52_WR_ERR_WKUP_EN - CMD52 Write Error Wakeup Enable If host issues CMD52 write access to any
+ *    off-domain register during sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN0_CARD_CARD_CTRL1_CMD52_WR_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL1_CMD52_WR_ERR_WKUP_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL1_CMD52_WR_ERR_WKUP_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL1_CMD52_RD_ERR_WKUP_EN_MASK (0x2U)
+#define SDU_FN0_CARD_CARD_CTRL1_CMD52_RD_ERR_WKUP_EN_SHIFT (1U)
+/*! CMD52_RD_ERR_WKUP_EN - CMD52 Read Error Wakeup Enable If host issues CMD52 read access to any
+ *    off-domain register during sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN0_CARD_CARD_CTRL1_CMD52_RD_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL1_CMD52_RD_ERR_WKUP_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL1_CMD52_RD_ERR_WKUP_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_WR_ERR_WKUP_EN_MASK (0x4U)
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_WR_ERR_WKUP_EN_SHIFT (2U)
+/*! CMD53_WR_ERR_WKUP_EN - CMD53 Write Error Wakeup Enable If host issues CMD53 write access during
+ *    sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_WR_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL1_CMD53_WR_ERR_WKUP_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL1_CMD53_WR_ERR_WKUP_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_RD_ERR_WKUP_EN_MASK (0x8U)
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_RD_ERR_WKUP_EN_SHIFT (3U)
+/*! CMD53_RD_ERR_WKUP_EN - CMD53 Read Error Wakeup Enable If host issues CMD53 read access during
+ *    sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_RD_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL1_CMD53_RD_ERR_WKUP_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL1_CMD53_RD_ERR_WKUP_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL1_SD_HOST_INT_ACT_LVL_MASK (0x10U)
+#define SDU_FN0_CARD_CARD_CTRL1_SD_HOST_INT_ACT_LVL_SHIFT (4U)
+/*! SD_HOST_INT_ACT_LVL - SD Host Interrupt Active Level 0 = Active Low 1 = Active High */
+#define SDU_FN0_CARD_CARD_CTRL1_SD_HOST_INT_ACT_LVL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL1_SD_HOST_INT_ACT_LVL_SHIFT)) & SDU_FN0_CARD_CARD_CTRL1_SD_HOST_INT_ACT_LVL_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_RFIFO_TH_MASK (0xC0U)
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_RFIFO_TH_SHIFT (6U)
+/*! CMD53_RFIFO_TH - CMD53 read fifo threshold 00 = 1 block size 01 = .5 block size 10 = ¼ block size 11 = ¾ block size */
+#define SDU_FN0_CARD_CARD_CTRL1_CMD53_RFIFO_TH(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL1_CMD53_RFIFO_TH_SHIFT)) & SDU_FN0_CARD_CARD_CTRL1_CMD53_RFIFO_TH_MASK)
+/*! @} */
+
+/*! @name CARD_CTRL2 - Card Control 2 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CARD_CTRL2_ASYNC_INT_MASK_EN_MASK (0x1U)
+#define SDU_FN0_CARD_CARD_CTRL2_ASYNC_INT_MASK_EN_SHIFT (0U)
+/*! ASYNC_INT_MASK_EN - Enable asynchronous interrupt mask */
+#define SDU_FN0_CARD_CARD_CTRL2_ASYNC_INT_MASK_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL2_ASYNC_INT_MASK_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL2_ASYNC_INT_MASK_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL2_NGFF_SD_RST_EN_MASK (0x2U)
+#define SDU_FN0_CARD_CARD_CTRL2_NGFF_SD_RST_EN_SHIFT (1U)
+/*! NGFF_SD_RST_EN - Allow NGFF SDIO RESET# to reset OCR value. */
+#define SDU_FN0_CARD_CARD_CTRL2_NGFF_SD_RST_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL2_NGFF_SD_RST_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL2_NGFF_SD_RST_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_WR_RESP_EN_MASK (0x4U)
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_WR_RESP_EN_SHIFT (2U)
+/*! CMD52_WR_RESP_EN - Enable delay of CMD52 write response (Not used) */
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_WR_RESP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL2_CMD52_WR_RESP_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL2_CMD52_WR_RESP_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_DLY_RES_RDATA_EN_MASK (0x8U)
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_DLY_RES_RDATA_EN_SHIFT (3U)
+/*! CMD52_DLY_RES_RDATA_EN - Delay latching of CMD52 read data until it is serially shifted out */
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_DLY_RES_RDATA_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL2_CMD52_DLY_RES_RDATA_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL2_CMD52_DLY_RES_RDATA_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_PWUP_EN_MASK (0x10U)
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_PWUP_EN_SHIFT (4U)
+/*! CMD52_PWUP_EN - If this is set to 1, host can issue any CMD52 to wake up the chip. */
+#define SDU_FN0_CARD_CARD_CTRL2_CMD52_PWUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL2_CMD52_PWUP_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL2_CMD52_PWUP_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL2_APU_DEV_SLEEP_EN_MASK (0x20U)
+#define SDU_FN0_CARD_CARD_CTRL2_APU_DEV_SLEEP_EN_SHIFT (5U)
+/*! APU_DEV_SLEEP_EN - If this is set to 1, the IO_READY status and Card Ready status depend on APU sleep/wake state. */
+#define SDU_FN0_CARD_CARD_CTRL2_APU_DEV_SLEEP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL2_APU_DEV_SLEEP_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL2_APU_DEV_SLEEP_EN_MASK)
+/*! @} */
+
+/*! @name CMD19_CTRL1 - CMD19 Control1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CMD19_CTRL1_CMD19_TP_ADDR_MASK (0xFFU)
+#define SDU_FN0_CARD_CMD19_CTRL1_CMD19_TP_ADDR_SHIFT (0U)
+/*! CMD19_TP_ADDR - CMD19 tuning pattern address Set address value for CMD19 tuning pattern array */
+#define SDU_FN0_CARD_CMD19_CTRL1_CMD19_TP_ADDR(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CMD19_CTRL1_CMD19_TP_ADDR_SHIFT)) & SDU_FN0_CARD_CMD19_CTRL1_CMD19_TP_ADDR_MASK)
+/*! @} */
+
+/*! @name CMD19_CTRL2 - CMD19 Control2 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CMD19_CTRL2_CMD19_TP_DATA_MASK (0xFFU)
+#define SDU_FN0_CARD_CMD19_CTRL2_CMD19_TP_DATA_SHIFT (0U)
+/*! CMD19_TP_DATA - CMD19 tuning pattern data CMD19 tuning pattern data at cmd19_tp_addr */
+#define SDU_FN0_CARD_CMD19_CTRL2_CMD19_TP_DATA(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CMD19_CTRL2_CMD19_TP_DATA_SHIFT)) & SDU_FN0_CARD_CMD19_CTRL2_CMD19_TP_DATA_MASK)
+/*! @} */
+
+/*! @name FUNC_CARD_INT - Function Card Interrupt */
+/*! @{ */
+
+#define SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT1_MASK (0xFU)
+#define SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT1_SHIFT (0U)
+/*! FN_CARD_INT1 - Pending card interrupt for each function to cpu1 */
+#define SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT1_SHIFT)) & SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT1_MASK)
+
+#define SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT2_MASK (0xF0U)
+#define SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT2_SHIFT (4U)
+/*! FN_CARD_INT2 - Pending card interrupt for each function to cpu2 */
+#define SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT2_SHIFT)) & SDU_FN0_CARD_FUNC_CARD_INT_FN_CARD_INT2_MASK)
+/*! @} */
+
+/*! @name FUNC0_CARD_INTMASK - Function Card Interrupt Mask */
+/*! @{ */
+
+#define SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN0_CARD_INTMASK_MASK (0x7U)
+#define SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN0_CARD_INTMASK_SHIFT (0U)
+/*! FN0_CARD_INTMASK - Card interrupt mask for function 0. */
+#define SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN0_CARD_INTMASK(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN0_CARD_INTMASK_SHIFT)) & SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN0_CARD_INTMASK_MASK)
+
+#define SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN_CARD_INT3_MASK (0xF0U)
+#define SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN_CARD_INT3_SHIFT (4U)
+/*! FN_CARD_INT3 - Pending card interrupt for each function to cpu3 */
+#define SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN_CARD_INT3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN_CARD_INT3_SHIFT)) & SDU_FN0_CARD_FUNC0_CARD_INTMASK_FN_CARD_INT3_MASK)
+/*! @} */
+
+/*! @name DEV_SLEEP - Device Sleep */
+/*! @{ */
+
+#define SDU_FN0_CARD_DEV_SLEEP_DEV_SLEEP_MASK    (0x1U)
+#define SDU_FN0_CARD_DEV_SLEEP_DEV_SLEEP_SHIFT   (0U)
+/*! DEV_SLEEP - Device Sleep If this is set to 1, IO_READY and CARD_READY status will be 0. */
+#define SDU_FN0_CARD_DEV_SLEEP_DEV_SLEEP(x)      (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_DEV_SLEEP_DEV_SLEEP_SHIFT)) & SDU_FN0_CARD_DEV_SLEEP_DEV_SLEEP_MASK)
+/*! @} */
+
+/*! @name CARD_CTRL3 - Card Control 3 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CARD_CTRL3_CMD53_WR_BUSY_HW_EN_MASK (0x1U)
+#define SDU_FN0_CARD_CARD_CTRL3_CMD53_WR_BUSY_HW_EN_SHIFT (0U)
+/*! CMD53_WR_BUSY_HW_EN - Main enable bit for cmd53_wr_busy_hw_ctrl feature. */
+#define SDU_FN0_CARD_CARD_CTRL3_CMD53_WR_BUSY_HW_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL3_CMD53_WR_BUSY_HW_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL3_CMD53_WR_BUSY_HW_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL3_CMD52_PWUP_MASK  (0x40U)
+#define SDU_FN0_CARD_CARD_CTRL3_CMD52_PWUP_SHIFT (6U)
+/*! CMD52_PWUP - Wakeup signal to APU. */
+#define SDU_FN0_CARD_CARD_CTRL3_CMD52_PWUP(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL3_CMD52_PWUP_SHIFT)) & SDU_FN0_CARD_CARD_CTRL3_CMD52_PWUP_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_INTMASK0 - Function 0 Card Interrupt Mask 0 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_INTMASK0_FN0_CARD_INTMASK0_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_INTMASK0_FN0_CARD_INTMASK0_SHIFT (0U)
+/*! FN0_CARD_INTMASK0 - Function 0 card interrupt mask [7:0] */
+#define SDU_FN0_CARD_FN0_CARD_INTMASK0_FN0_CARD_INTMASK0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_INTMASK0_FN0_CARD_INTMASK0_SHIFT)) & SDU_FN0_CARD_FN0_CARD_INTMASK0_FN0_CARD_INTMASK0_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_INTMASK1 - Function 0 Card Interrupt Mask 1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_INTMASK1_FN0_CARD_INTMASK1_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_INTMASK1_FN0_CARD_INTMASK1_SHIFT (0U)
+/*! FN0_CARD_INTMASK1 - Function 0 card interrupt mask [15:8] */
+#define SDU_FN0_CARD_FN0_CARD_INTMASK1_FN0_CARD_INTMASK1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_INTMASK1_FN0_CARD_INTMASK1_SHIFT)) & SDU_FN0_CARD_FN0_CARD_INTMASK1_FN0_CARD_INTMASK1_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_INTRSR0 - Function 0 Card Interrupt Reset Select 0 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_INTRSR0_FN0_CARD_INTRSR0_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_INTRSR0_FN0_CARD_INTRSR0_SHIFT (0U)
+/*! FN0_CARD_INTRSR0 - Function 0 card interrupt reset select [7:0] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read */
+#define SDU_FN0_CARD_FN0_CARD_INTRSR0_FN0_CARD_INTRSR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_INTRSR0_FN0_CARD_INTRSR0_SHIFT)) & SDU_FN0_CARD_FN0_CARD_INTRSR0_FN0_CARD_INTRSR0_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_INTRSR1 - Function 0 Card Interrupt Reset Select 1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_INTRSR1_FN0_CARD_INTRSR1_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_INTRSR1_FN0_CARD_INTRSR1_SHIFT (0U)
+/*! FN0_CARD_INTRSR1 - Function 0 card interrupt reset select [15:8] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read */
+#define SDU_FN0_CARD_FN0_CARD_INTRSR1_FN0_CARD_INTRSR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_INTRSR1_FN0_CARD_INTRSR1_SHIFT)) & SDU_FN0_CARD_FN0_CARD_INTRSR1_FN0_CARD_INTRSR1_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_INTSTATUS0 - Function 0 Card Interrupt Status 0 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_INTSTATUS0_FN0_CARD_INTSTAT0_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_INTSTATUS0_FN0_CARD_INTSTAT0_SHIFT (0U)
+/*! FN0_CARD_INTSTAT0 - Function 0 card interrupt status [7:0] of the following events: [7:1] = fn_ps_event [0] = drv_snth_event */
+#define SDU_FN0_CARD_FN0_CARD_INTSTATUS0_FN0_CARD_INTSTAT0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_INTSTATUS0_FN0_CARD_INTSTAT0_SHIFT)) & SDU_FN0_CARD_FN0_CARD_INTSTATUS0_FN0_CARD_INTSTAT0_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_INTSTATUS1 - Function 0 Card Interrupt Status 1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_INTSTATUS1_FN0_CARD_INTSTAT1_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_INTSTATUS1_FN0_CARD_INTSTAT1_SHIFT (0U)
+/*! FN0_CARD_INTSTAT1 - Function 0 card interrupt status [15:8] of the following events: [7] = FN0
+ *    CMD53 read access during sleep mode [6] = FN0 CMD53 write access during sleep mode [5] = FN0
+ *    CMD52 read access to off-domain sdu register during sleep mode [4] = FN0 CMD52 write access to
+ *    off-domain sdu register during sleep mode [3] = CMD5 is received [2] = CMD11 start [1] = CMD11
+ *    switch start [0] = CMD11 succeeded
+ */
+#define SDU_FN0_CARD_FN0_CARD_INTSTATUS1_FN0_CARD_INTSTAT1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_INTSTATUS1_FN0_CARD_INTSTAT1_SHIFT)) & SDU_FN0_CARD_FN0_CARD_INTSTATUS1_FN0_CARD_INTSTAT1_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_ACTVINTMASK0 - Function 0 Card Active Interrupt Mask 0 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_ACTVINTMASK0_FN0_CARD_ACTVINTMASK0_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_ACTVINTMASK0_FN0_CARD_ACTVINTMASK0_SHIFT (0U)
+/*! FN0_CARD_ACTVINTMASK0 - Function 0 card active interrupt mask[7:0] */
+#define SDU_FN0_CARD_FN0_CARD_ACTVINTMASK0_FN0_CARD_ACTVINTMASK0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_ACTVINTMASK0_FN0_CARD_ACTVINTMASK0_SHIFT)) & SDU_FN0_CARD_FN0_CARD_ACTVINTMASK0_FN0_CARD_ACTVINTMASK0_MASK)
+/*! @} */
+
+/*! @name FN0_CARD_ACTVINTMASK1 - Function 0 Card Active Interrupt Mask 1 */
+/*! @{ */
+
+#define SDU_FN0_CARD_FN0_CARD_ACTVINTMASK1_FN0_CARD_ACTVINTMASK1_MASK (0xFFU)
+#define SDU_FN0_CARD_FN0_CARD_ACTVINTMASK1_FN0_CARD_ACTVINTMASK1_SHIFT (0U)
+/*! FN0_CARD_ACTVINTMASK1 - Function 0 card active interrupt mask[15:8] */
+#define SDU_FN0_CARD_FN0_CARD_ACTVINTMASK1_FN0_CARD_ACTVINTMASK1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_FN0_CARD_ACTVINTMASK1_FN0_CARD_ACTVINTMASK1_SHIFT)) & SDU_FN0_CARD_FN0_CARD_ACTVINTMASK1_FN0_CARD_ACTVINTMASK1_MASK)
+/*! @} */
+
+/*! @name CARD_CTRL4 - Card Control 4 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_VAL_MASK (0x1U)
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_VAL_SHIFT (0U)
+/*! CMD11_V18_BYPASS_VAL - FW bypass value that overrides the V18 signal from the SD pad voltage sensor. */
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_VAL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_VAL_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_VAL_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_EN_MASK (0x2U)
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_EN_SHIFT (1U)
+/*! CMD11_V18_BYPASS_EN - If this is set, the V18 signal from the SD pad voltage sensor is bypassed. */
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_CMD11_V18_BYPASS_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_VIO_CHK_BYPASS_MASK (0x4U)
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_VIO_CHK_BYPASS_SHIFT (2U)
+/*! CMD11_VIO_CHK_BYPASS - If this is set, the cmd11 state machine will bypass the VIO pad sensor check. */
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_VIO_CHK_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_CMD11_VIO_CHK_BYPASS_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_CMD11_VIO_CHK_BYPASS_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_SD_CLK_STOP_BYPASS_MASK (0x8U)
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_SD_CLK_STOP_BYPASS_SHIFT (3U)
+/*! CMD11_SD_CLK_STOP_BYPASS - If this is set, the cmd11 state machine will bypass the SD clk idle checking logic. */
+#define SDU_FN0_CARD_CARD_CTRL4_CMD11_SD_CLK_STOP_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_CMD11_SD_CLK_STOP_BYPASS_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_CMD11_SD_CLK_STOP_BYPASS_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_VAL_MASK (0x10U)
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_VAL_SHIFT (4U)
+/*! CMD5_R4_S18A_BYPASS_VAL - FW bypass value that overrides the S18A field in cmd5 R4 response. */
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_VAL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_VAL_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_VAL_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_EN_MASK (0x20U)
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_EN_SHIFT (5U)
+/*! CMD5_R4_S18A_BYPASS_EN - If this is set, the S18A field in cmd5 R4 response is bypassed. */
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_CMD5_R4_S18A_BYPASS_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL4_SET_CMD11_ILLEGAL_MASK (0x40U)
+#define SDU_FN0_CARD_CARD_CTRL4_SET_CMD11_ILLEGAL_SHIFT (6U)
+/*! SET_CMD11_ILLEGAL - If this is set and SD VIO pad sensor V18=1 (1. */
+#define SDU_FN0_CARD_CARD_CTRL4_SET_CMD11_ILLEGAL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_SET_CMD11_ILLEGAL_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_SET_CMD11_ILLEGAL_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_S18R_CHK_MASK (0x80U)
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_S18R_CHK_SHIFT (7U)
+/*! CMD5_S18R_CHK - If this is set, S18A in R4 depends on CMD5 S18R bit. */
+#define SDU_FN0_CARD_CARD_CTRL4_CMD5_S18R_CHK(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL4_CMD5_S18R_CHK_SHIFT)) & SDU_FN0_CARD_CARD_CTRL4_CMD5_S18R_CHK_MASK)
+/*! @} */
+
+/*! @name CARD_CTRL5 - Card Control 5 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_VAL_MASK (0x7U)
+#define SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_VAL_SHIFT (0U)
+/*! CMD5_R4_FN_BYPASS_VAL - FW bypass value that overrides the function number derived from chip strap settings. */
+#define SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_VAL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_VAL_SHIFT)) & SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_VAL_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_EN_MASK (0x8U)
+#define SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_EN_SHIFT (3U)
+/*! CMD5_R4_FN_BYPASS_EN - If this is set, the function number field of R4 is controlled by
+ *    cmd5_r4_fn_bypass_val rather than from chip strap settings.
+ */
+#define SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_EN_SHIFT)) & SDU_FN0_CARD_CARD_CTRL5_CMD5_R4_FN_BYPASS_EN_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL5_REPEAT_SDU_INIT_MASK (0x10U)
+#define SDU_FN0_CARD_CARD_CTRL5_REPEAT_SDU_INIT_SHIFT (4U)
+/*! REPEAT_SDU_INIT - If this is set, sdu can handle enumeration sequence initiated by host multiple times */
+#define SDU_FN0_CARD_CARD_CTRL5_REPEAT_SDU_INIT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL5_REPEAT_SDU_INIT_SHIFT)) & SDU_FN0_CARD_CARD_CTRL5_REPEAT_SDU_INIT_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL5_RESET_RCA_MASK   (0x20U)
+#define SDU_FN0_CARD_CARD_CTRL5_RESET_RCA_SHIFT  (5U)
+/*! RESET_RCA - Reset RCA. */
+#define SDU_FN0_CARD_CARD_CTRL5_RESET_RCA(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL5_RESET_RCA_SHIFT)) & SDU_FN0_CARD_CARD_CTRL5_RESET_RCA_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL5_SD_RESET_AFTER_CMD52_R5_MASK (0x40U)
+#define SDU_FN0_CARD_CARD_CTRL5_SD_RESET_AFTER_CMD52_R5_SHIFT (6U)
+/*! SD_RESET_AFTER_CMD52_R5 - Generate sd_reset after cmd52 R5 response. */
+#define SDU_FN0_CARD_CARD_CTRL5_SD_RESET_AFTER_CMD52_R5(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL5_SD_RESET_AFTER_CMD52_R5_SHIFT)) & SDU_FN0_CARD_CARD_CTRL5_SD_RESET_AFTER_CMD52_R5_MASK)
+
+#define SDU_FN0_CARD_CARD_CTRL5_CMD52_RES_VALID_MODE_MASK (0x80U)
+#define SDU_FN0_CARD_CARD_CTRL5_CMD52_RES_VALID_MODE_SHIFT (7U)
+/*! CMD52_RES_VALID_MODE - CMD52 response valid mode 0 = CMD52 response valid is generated only
+ *    after write operation is completed in the ahb_clk domain.
+ */
+#define SDU_FN0_CARD_CARD_CTRL5_CMD52_RES_VALID_MODE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL5_CMD52_RES_VALID_MODE_SHIFT)) & SDU_FN0_CARD_CARD_CTRL5_CMD52_RES_VALID_MODE_MASK)
+/*! @} */
+
+/*! @name CARD_CTRL6 - Card Control 6 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CARD_CTRL6_TESTBUS_SEL_LO_MASK (0xFFU)
+#define SDU_FN0_CARD_CARD_CTRL6_TESTBUS_SEL_LO_SHIFT (0U)
+/*! TESTBUS_SEL_LO - SDU testbus select [7:0] */
+#define SDU_FN0_CARD_CARD_CTRL6_TESTBUS_SEL_LO(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL6_TESTBUS_SEL_LO_SHIFT)) & SDU_FN0_CARD_CARD_CTRL6_TESTBUS_SEL_LO_MASK)
+/*! @} */
+
+/*! @name CARD_CTRL7 - Card Control 7 */
+/*! @{ */
+
+#define SDU_FN0_CARD_CARD_CTRL7_TESTBUS_SEL_HI_MASK (0xFFU)
+#define SDU_FN0_CARD_CARD_CTRL7_TESTBUS_SEL_HI_SHIFT (0U)
+/*! TESTBUS_SEL_HI - SDU testbus select [15:8] */
+#define SDU_FN0_CARD_CARD_CTRL7_TESTBUS_SEL_HI(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN0_CARD_CARD_CTRL7_TESTBUS_SEL_HI_SHIFT)) & SDU_FN0_CARD_CARD_CTRL7_TESTBUS_SEL_HI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SDU_FN0_CARD_Register_Masks */
+
+
+/* SDU_FN0_CARD - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SDU_FN0_CARD base address */
+  #define SDU_FN0_CARD_BASE                        (0x50158000u)
+  /** Peripheral SDU_FN0_CARD base address */
+  #define SDU_FN0_CARD_BASE_NS                     (0x40158000u)
+  /** Peripheral SDU_FN0_CARD base pointer */
+  #define SDU_FN0_CARD                             ((SDU_FN0_CARD_Type *)SDU_FN0_CARD_BASE)
+  /** Peripheral SDU_FN0_CARD base pointer */
+  #define SDU_FN0_CARD_NS                          ((SDU_FN0_CARD_Type *)SDU_FN0_CARD_BASE_NS)
+  /** Array initializer of SDU_FN0_CARD peripheral base addresses */
+  #define SDU_FN0_CARD_BASE_ADDRS                  { SDU_FN0_CARD_BASE }
+  /** Array initializer of SDU_FN0_CARD peripheral base pointers */
+  #define SDU_FN0_CARD_BASE_PTRS                   { SDU_FN0_CARD }
+  /** Array initializer of SDU_FN0_CARD peripheral base addresses */
+  #define SDU_FN0_CARD_BASE_ADDRS_NS               { SDU_FN0_CARD_BASE_NS }
+  /** Array initializer of SDU_FN0_CARD peripheral base pointers */
+  #define SDU_FN0_CARD_BASE_PTRS_NS                { SDU_FN0_CARD_NS }
+#else
+  /** Peripheral SDU_FN0_CARD base address */
+  #define SDU_FN0_CARD_BASE                        (0x40158000u)
+  /** Peripheral SDU_FN0_CARD base pointer */
+  #define SDU_FN0_CARD                             ((SDU_FN0_CARD_Type *)SDU_FN0_CARD_BASE)
+  /** Array initializer of SDU_FN0_CARD peripheral base addresses */
+  #define SDU_FN0_CARD_BASE_ADDRS                  { SDU_FN0_CARD_BASE }
+  /** Array initializer of SDU_FN0_CARD peripheral base pointers */
+  #define SDU_FN0_CARD_BASE_PTRS                   { SDU_FN0_CARD }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SDU_FN0_CARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDU_FN_CARD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDU_FN_CARD_Peripheral_Access_Layer SDU_FN_CARD Peripheral Access Layer
+ * @{
+ */
+
+/** SDU_FN_CARD - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t H2C_INTEVENT;                       /**< Host to Card Interrupt Event, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t HOST_INTRSR0;                       /**< Host Interrupt Reset Select 0, offset: 0x4 */
+  __I  uint8_t HOST_INTRSR1;                       /**< Host Interrupt Reset Select 1, offset: 0x5 */
+       uint8_t RESERVED_1[2];
+  __I  uint8_t HOST_INTMASK0;                      /**< Host Interrupt Mask 0, offset: 0x8 */
+  __I  uint8_t HOST_INTMASK1;                      /**< Host Interrupt Mask 1, offset: 0x9 */
+       uint8_t RESERVED_2[2];
+  __I  uint8_t HOST_INTSTATUS0;                    /**< Host Interrupt Status 0, offset: 0xC */
+  __I  uint8_t HOST_INTSTATUS1;                    /**< Host Interrupt Status 1, offset: 0xD */
+       uint8_t RESERVED_3[2];
+  __IO uint8_t PKT_RD_BITMAP0;                     /**< Packet Read Bitmap 0, offset: 0x10 */
+  __IO uint8_t PKT_RD_BITMAP1;                     /**< Packet Read Bitmap 1, offset: 0x11 */
+  __IO uint8_t PKT_RD_BITMAP2;                     /**< Packet Read Bitmap 2, offset: 0x12 */
+  __IO uint8_t PKT_RD_BITMAP3;                     /**< Packet Read Bitmap 3, offset: 0x13 */
+  __IO uint8_t PKT_WR_BITMAP0;                     /**< Packet Write Bitmap 0, offset: 0x14 */
+  __IO uint8_t PKT_WR_BITMAP1;                     /**< Packet Write Bitmap 1, offset: 0x15 */
+  __IO uint8_t PKT_WR_BITMAP2;                     /**< Packet Write Bitmap 2, offset: 0x16 */
+  __IO uint8_t PKT_WR_BITMAP3;                     /**< Packet Write Bitmap 3, offset: 0x17 */
+  __IO uint8_t PORT0_RD_LEN0;                      /**< Port 0 Packet Read Length 0, offset: 0x18 */
+  __IO uint8_t PORT0_RD_LEN1;                      /**< Port 0 Packet Read Length 1, offset: 0x19 */
+  __IO uint8_t PORT1_RD_LEN0;                      /**< Port 1 Packet Read Length 0, offset: 0x1A */
+  __IO uint8_t PORT1_RD_LEN1;                      /**< Port 1 Packet Read Length 1, offset: 0x1B */
+  __IO uint8_t PORT2_RD_LEN0;                      /**< Port 2 Packet Read Length 0, offset: 0x1C */
+  __IO uint8_t PORT2_RD_LEN1;                      /**< Port 2 Packet Read Length 1, offset: 0x1D */
+  __IO uint8_t PORT3_RD_LEN0;                      /**< Port 3 Packet Read Length 0, offset: 0x1E */
+  __IO uint8_t PORT3_RD_LEN1;                      /**< Port 3 Packet Read Length 1, offset: 0x1F */
+  __IO uint8_t PORT4_RD_LEN0;                      /**< Port 4 Packet Read Length 0, offset: 0x20 */
+  __IO uint8_t PORT4_RD_LEN1;                      /**< Port 4 Packet Read Length 1, offset: 0x21 */
+  __IO uint8_t PORT5_RD_LEN0;                      /**< Port 5 Packet Read Length 0, offset: 0x22 */
+  __IO uint8_t PORT5_RD_LEN1;                      /**< Port 5 Packet Read Length 1, offset: 0x23 */
+  __IO uint8_t PORT6_RD_LEN0;                      /**< Port 6 Packet Read Length 0, offset: 0x24 */
+  __IO uint8_t PORT6_RD_LEN1;                      /**< Port 6 Packet Read Length 1, offset: 0x25 */
+  __IO uint8_t PORT7_RD_LEN0;                      /**< Port 7 Packet Read Length 0, offset: 0x26 */
+  __IO uint8_t PORT7_RD_LEN1;                      /**< Port 7 Packet Read Length 1, offset: 0x27 */
+  __IO uint8_t PORT8_RD_LEN0;                      /**< Port 8 Packet Read Length 0, offset: 0x28 */
+  __IO uint8_t PORT8_RD_LEN1;                      /**< Port 8 Packet Read Length 1, offset: 0x29 */
+  __IO uint8_t PORT9_RD_LEN0;                      /**< Port 9 Packet Read Length 0, offset: 0x2A */
+  __IO uint8_t PORT9_RD_LEN1;                      /**< Port 9 Packet Read Length 1, offset: 0x2B */
+  __IO uint8_t PORT10_RD_LEN0;                     /**< Port 10 Packet Read Length 0, offset: 0x2C */
+  __IO uint8_t PORT10_RD_LEN1;                     /**< Port 10 Packet Read Length 1, offset: 0x2D */
+  __IO uint8_t PORT11_RD_LEN0;                     /**< Port 11 Packet Read Length 0, offset: 0x2E */
+  __IO uint8_t PORT11_RD_LEN1;                     /**< Port 11 Packet Read Length 1, offset: 0x2F */
+  __IO uint8_t PORT12_RD_LEN0;                     /**< Port 12 Packet Read Length 0, offset: 0x30 */
+  __IO uint8_t PORT12_RD_LEN1;                     /**< Port 12 Packet Read Length 1, offset: 0x31 */
+  __IO uint8_t PORT13_RD_LEN0;                     /**< Port 13 Packet Read Length 0, offset: 0x32 */
+  __IO uint8_t PORT13_RD_LEN1;                     /**< Port 13 Packet Read Length 1, offset: 0x33 */
+  __IO uint8_t PORT14_RD_LEN0;                     /**< Port 14 Packet Read Length 0, offset: 0x34 */
+  __IO uint8_t PORT14_RD_LEN1;                     /**< Port 14 Packet Read Length 1, offset: 0x35 */
+  __IO uint8_t PORT15_RD_LEN0;                     /**< Port 15 Packet Read Length 0, offset: 0x36 */
+  __IO uint8_t PORT15_RD_LEN1;                     /**< Port 15 Packet Read Length 1, offset: 0x37 */
+  __IO uint8_t PORT16_RD_LEN0;                     /**< Port 16 Packet Read Length 0, offset: 0x38 */
+  __IO uint8_t PORT16_RD_LEN1;                     /**< Port 16 Packet Read Length 1, offset: 0x39 */
+  __IO uint8_t PORT17_RD_LEN0;                     /**< Port 17 Packet Read Length 0, offset: 0x3A */
+  __IO uint8_t PORT17_RD_LEN1;                     /**< Port 17 Packet Read Length 1, offset: 0x3B */
+  __IO uint8_t PORT18_RD_LEN0;                     /**< Port 18 Packet Read Length 0, offset: 0x3C */
+  __IO uint8_t PORT18_RD_LEN1;                     /**< Port 18 Packet Read Length 1, offset: 0x3D */
+  __IO uint8_t PORT19_RD_LEN0;                     /**< Port 19 Packet Read Length 0, offset: 0x3E */
+  __IO uint8_t PORT19_RD_LEN1;                     /**< Port 19 Packet Read Length 1, offset: 0x3F */
+  __IO uint8_t PORT20_RD_LEN0;                     /**< Port 20 Packet Read Length 0, offset: 0x40 */
+  __IO uint8_t PORT20_RD_LEN1;                     /**< Port 20 Packet Read Length 1, offset: 0x41 */
+  __IO uint8_t PORT21_RD_LEN0;                     /**< Port 21 Packet Read Length 0, offset: 0x42 */
+  __IO uint8_t PORT21_RD_LEN1;                     /**< Port 21 Packet Read Length 1, offset: 0x43 */
+  __IO uint8_t PORT22_RD_LEN0;                     /**< Port 22 Packet Read Length 0, offset: 0x44 */
+  __IO uint8_t PORT22_RD_LEN1;                     /**< Port 22 Packet Read Length 1, offset: 0x45 */
+  __IO uint8_t PORT23_RD_LEN0;                     /**< Port 23 Packet Read Length 0, offset: 0x46 */
+  __IO uint8_t PORT23_RD_LEN1;                     /**< Port 23 Packet Read Length 1, offset: 0x47 */
+  __IO uint8_t PORT24_RD_LEN0;                     /**< Port 24 Packet Read Length 0, offset: 0x48 */
+  __IO uint8_t PORT24_RD_LEN1;                     /**< Port 24 Packet Read Length 1, offset: 0x49 */
+  __IO uint8_t PORT25_RD_LEN0;                     /**< Port 25 Packet Read Length 0, offset: 0x4A */
+  __IO uint8_t PORT25_RD_LEN1;                     /**< Port 25 Packet Read Length 1, offset: 0x4B */
+  __IO uint8_t PORT26_RD_LEN0;                     /**< Port 26 Packet Read Length 0, offset: 0x4C */
+  __IO uint8_t PORT26_RD_LEN1;                     /**< Port 26 Packet Read Length 1, offset: 0x4D */
+  __IO uint8_t PORT27_RD_LEN0;                     /**< Port 27 Packet Read Length 0, offset: 0x4E */
+  __IO uint8_t PORT27_RD_LEN1;                     /**< Port 27 Packet Read Length 1, offset: 0x4F */
+  __IO uint8_t PORT28_RD_LEN0;                     /**< Port 28 Packet Read Length 0, offset: 0x50 */
+  __IO uint8_t PORT28_RD_LEN1;                     /**< Port 28 Packet Read Length 1, offset: 0x51 */
+  __IO uint8_t PORT29_RD_LEN0;                     /**< Port 29 Packet Read Length 0, offset: 0x52 */
+  __IO uint8_t PORT29_RD_LEN1;                     /**< Port 29 Packet Read Length 1, offset: 0x53 */
+  __IO uint8_t PORT30_RD_LEN0;                     /**< Port 30 Packet Read Length 0, offset: 0x54 */
+  __IO uint8_t PORT30_RD_LEN1;                     /**< Port 30 Packet Read Length 1, offset: 0x55 */
+  __IO uint8_t PORT31_RD_LEN0;                     /**< Port 31 Packet Read Length 0, offset: 0x56 */
+  __IO uint8_t PORT31_RD_LEN1;                     /**< Port 31 Packet Read Length 1, offset: 0x57 */
+  __I  uint8_t HOST_RESTART;                       /**< Host Transfer Status, offset: 0x58 */
+  __IO uint8_t FN_CARD_INTMASK;                    /**< Function Card Interrupt Mask, offset: 0x59 */
+  __IO uint8_t Q_PRT_RANGE0;                       /**< Queue Port Range 0, offset: 0x5A */
+  __IO uint8_t Q_PRT_RANGE1;                       /**< Queue Port Range 1, offset: 0x5B */
+  __IO uint8_t C2H_INTEVENT0;                      /**< Card to Host Event 0, offset: 0x5C */
+  __IO uint8_t C2H_INTEVENT1;                      /**< Card to Host Event 1, offset: 0x5D */
+       uint8_t RESERVED_4[2];
+  __IO uint8_t CARD_INTMASK0;                      /**< Card Interrupt Mask 0, offset: 0x60 */
+  __IO uint8_t CARD_INTMASK1;                      /**< Card Interrupt Mask 1, offset: 0x61 */
+  __IO uint8_t CARD_INTMASK2;                      /**< Card Interrupt Mask 2, offset: 0x62 */
+       uint8_t RESERVED_5[1];
+  __I  uint8_t CARD_INTSTATUS0;                    /**< Card Interrupt Status 0, offset: 0x64 */
+  __I  uint8_t CARD_INTSTATUS1;                    /**< Card Interrupt Status 1, offset: 0x65 */
+  __I  uint8_t CARD_INTSTATUS2;                    /**< Card Interrupt Status 2, offset: 0x66 */
+       uint8_t RESERVED_6[1];
+  __IO uint8_t CARD_INTRSR0;                       /**< Card Interrupt Reset Select 0, offset: 0x68 */
+  __IO uint8_t CARD_INTRSR1;                       /**< Card Interrupt Reset Select 1, offset: 0x69 */
+  __IO uint8_t CARD_INTRSR2;                       /**< Card Interrupt Reset Select 2, offset: 0x6A */
+       uint8_t RESERVED_7[1];
+  __IO uint8_t RD_BASE0;                           /**< SQ Read Base Address 0, offset: 0x6C */
+  __IO uint8_t RD_BASE1;                           /**< SQ Read Base Address 1, offset: 0x6D */
+  __IO uint8_t RD_BASE2;                           /**< SQ Read Base Address 2, offset: 0x6E */
+  __IO uint8_t RD_BASE3;                           /**< SQ Read Base Address 3, offset: 0x6F */
+  __IO uint8_t WR_BASE0;                           /**< SQ Write Base Address 0, offset: 0x70 */
+  __IO uint8_t WR_BASE1;                           /**< SQ Write Base Address 1, offset: 0x71 */
+  __IO uint8_t WR_BASE2;                           /**< SQ Write Base Address 2, offset: 0x72 */
+  __IO uint8_t WR_BASE3;                           /**< SQ Write Base Address 3, offset: 0x73 */
+  __IO uint8_t RD_IDX;                             /**< Read Base Address Index, offset: 0x74 */
+  __IO uint8_t WR_IDX;                             /**< Write Base Address Index, offset: 0x75 */
+       uint8_t RESERVED_8[2];
+  __IO uint8_t APU_SLP_RDY_EN;                     /**< APU Sleep Ready Enable, offset: 0x78 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t HOST_ERR_WKUP_EN;                   /**< Host Error Wakeup Enable, offset: 0x7C */
+       uint8_t RESERVED_10[3];
+  __I  uint8_t HOST_ERR_CMD0;                      /**< Host Error Command 0, offset: 0x80 */
+  __I  uint8_t HOST_ERR_CMD1;                      /**< Host Error Command 1, offset: 0x81 */
+  __I  uint8_t HOST_ERR_CMD2;                      /**< Host Error Command 2, offset: 0x82 */
+  __I  uint8_t HOST_ERR_CMD3;                      /**< Host Error Command 3, offset: 0x83 */
+  __I  uint8_t HOST_ERR_CMD4;                      /**< Host Error Command 4, offset: 0x84 */
+  __I  uint8_t HOST_ERR_CMD5;                      /**< Host Error Command 5, offset: 0x85 */
+       uint8_t RESERVED_11[2];
+  __O  uint8_t PKT_WR_BITMAP_CLR0;                 /**< Packet Write Bitmap Clear 0, offset: 0x88 */
+  __O  uint8_t PKT_WR_BITMAP_CLR1;                 /**< Packet Write Bitmap Clear 1, offset: 0x89 */
+  __O  uint8_t PKT_WR_BITMAP_CLR2;                 /**< Packet Write Bitmap Clear 2, offset: 0x8A */
+  __O  uint8_t PKT_WR_BITMAP_CLR3;                 /**< Packet Write Bitmap Clear 3, offset: 0x8B */
+  __O  uint8_t PKT_RD_BITMAP_CLR0;                 /**< Packet Read Bitmap Clear 0, offset: 0x8C */
+  __O  uint8_t PKT_RD_BITMAP_CLR1;                 /**< Packet Read Bitmap Clear 1, offset: 0x8D */
+  __O  uint8_t PKT_RD_BITMAP_CLR2;                 /**< Packet Read Bitmap Clear 2, offset: 0x8E */
+  __O  uint8_t PKT_RD_BITMAP_CLR3;                 /**< Packet Read Bitmap Clear 3, offset: 0x8F */
+  __IO uint8_t HOST_INT_ACT_MASK_EN0;              /**< Host Interrupt Active Mask Enable 0, offset: 0x90 */
+  __IO uint8_t HOST_INT_ACT_MASK_EN1;              /**< Host Interrupt Active Mask Enable 1, offset: 0x91 */
+  __IO uint8_t HOST_INT_ACT_MASK_EN2;              /**< Host Interrupt Active Mask Enable 2, offset: 0x92 */
+  __IO uint8_t HOST_INT_ACT_MASK_EN3;              /**< Host Interrupt Active Mask Enable 3, offset: 0x93 */
+  __O  uint8_t HOST_INT_ACT_MASK_CLR0;             /**< Host Interrupt Active Mask Clear 0, offset: 0x94 */
+  __O  uint8_t HOST_INT_ACT_MASK_CLR1;             /**< Host Interrupt Active Mask Clear 1, offset: 0x95 */
+  __O  uint8_t HOST_INT_ACT_MASK_CLR2;             /**< Host Interrupt Active Mask Clear 2, offset: 0x96 */
+  __O  uint8_t HOST_INT_ACT_MASK_CLR3;             /**< Host Interrupt Active Mask Clear 3, offset: 0x97 */
+  __I  uint8_t HOST_INT_ACT_MASK_STATUS0;          /**< Host Interrupt Active Mask Status 0, offset: 0x98 */
+  __I  uint8_t HOST_INT_ACT_MASK_STATUS1;          /**< Host Interrupt Active Mask Status 1, offset: 0x99 */
+  __I  uint8_t HOST_INT_ACT_MASK_STATUS2;          /**< Host Interrupt Active Mask Status 2, offset: 0x9A */
+  __I  uint8_t HOST_INT_ACT_MASK_STATUS3;          /**< Host Interrupt Active Mask Status 3, offset: 0x9B */
+  __IO uint8_t CARD_INT_ACT_MASK_EN0;              /**< Card Interrupt Active Mask Enable 0, offset: 0x9C */
+  __IO uint8_t CARD_INT_ACT_MASK_EN1;              /**< Card Interrupt Active Mask Enable 1, offset: 0x9D */
+  __IO uint8_t CARD_INT_ACT_MASK_EN2;              /**< Card Interrupt Active Mask Enable 2, offset: 0x9E */
+  __IO uint8_t CARD_INT_ACT_MASK_EN3;              /**< Card Interrupt Active Mask Enable 3, offset: 0x9F */
+  __O  uint8_t CARD_INT_ACT_MASK_CLR0;             /**< Card Interrupt Active Mask Clear 0, offset: 0xA0 */
+  __O  uint8_t CARD_INT_ACT_MASK_CLR1;             /**< Card Interrupt Active Mask Clear 1, offset: 0xA1 */
+  __O  uint8_t CARD_INT_ACT_MASK_CLR2;             /**< Card Interrupt Active Mask Clear 2, offset: 0xA2 */
+  __O  uint8_t CARD_INT_ACT_MASK_CLR3;             /**< Card Interrupt Active Mask Clear 3, offset: 0xA3 */
+  __I  uint8_t CARD_INT_ACT_MASK_STATUS0;          /**< Card Interrupt Active Mask Status 0, offset: 0xA4 */
+  __I  uint8_t CARD_INT_ACT_MASK_STATUS1;          /**< Card Interrupt Active Mask Status 1, offset: 0xA5 */
+  __I  uint8_t CARD_INT_ACT_MASK_STATUS2;          /**< Card Interrupt Active Mask Status 2, offset: 0xA6 */
+  __I  uint8_t CARD_INT_ACT_MASK_STATUS3;          /**< Card Interrupt Active Mask Status 3, offset: 0xA7 */
+       uint8_t RESERVED_12[16];
+  __IO uint8_t CMD_PORT_WR_BASE_0;                 /**< Command Port SQ Write Base Address 0, offset: 0xB8 */
+  __IO uint8_t CMD_PORT_WR_BASE_1;                 /**< Command Port SQ Write Base Address 1, offset: 0xB9 */
+  __IO uint8_t CMD_PORT_WR_BASE_2;                 /**< Command Port SQ Write Base Address 2, offset: 0xBA */
+  __IO uint8_t CMD_PORT_WR_BASE_3;                 /**< Command Port SQ Write Base Address 3, offset: 0xBB */
+  __IO uint8_t CMD_PORT_RD_BASE_0;                 /**< Command Port SQ Read Base Address 0, offset: 0xBC */
+  __IO uint8_t CMD_PORT_RD_BASE_1;                 /**< Command Port SQ Read Base Address 1, offset: 0xBD */
+  __IO uint8_t CMD_PORT_RD_BASE_2;                 /**< Command Port SQ Read Base Address 2, offset: 0xBE */
+  __IO uint8_t CMD_PORT_RD_BASE_3;                 /**< Command Port SQ Read Base Address 3, offset: 0xBF */
+  __IO uint8_t CMD_PORT_RD_LEN_0;                  /**< Command Port Read Length 0, offset: 0xC0 */
+  __IO uint8_t CMD_PORT_RD_LEN_1;                  /**< Command Port Read Length 1, offset: 0xC1 */
+       uint8_t RESERVED_13[2];
+  __IO uint8_t CMD_PORT_CONFIG_0;                  /**< Command Port Config 0, offset: 0xC4 */
+  __IO uint8_t CMD_PORT_CONFIG_1;                  /**< Command Port Config 1, offset: 0xC5 */
+  __I  uint8_t CMD_PORT_CONFIG_2;                  /**< Command Port Config 2, offset: 0xC6 */
+  __I  uint8_t CMD_PORT_CONFIG_3;                  /**< Command Port Config 3, offset: 0xC7 */
+  __I  uint8_t CHIP_REV;                           /**< Chip Revision, offset: 0xC8 */
+       uint8_t RESERVED_14[1];
+  __I  uint8_t IP_REV0;                            /**< SDU Minor IP Revision, offset: 0xCA */
+  __I  uint8_t IP_REV1;                            /**< SDU Major IP Revision, offset: 0xCB */
+  __IO uint8_t PKT_END_RADDR0;                     /**< PKT_END_RADDR0, offset: 0xCC */
+  __IO uint8_t PKT_END_RADDR1;                     /**< PKT_END_RADDR1, offset: 0xCD */
+  __IO uint8_t PKT_END_RADDR2;                     /**< PKT_END_RADDR2, offset: 0xCE */
+  __IO uint8_t PKT_END_RADDR3;                     /**< PKT_END_RADDR3, offset: 0xCF */
+  __IO uint8_t PKT_END_WADDR0;                     /**< PKT_END_WADDR0, offset: 0xD0 */
+  __IO uint8_t PKT_END_WADDR1;                     /**< PKT_END_WADDR1, offset: 0xD1 */
+  __IO uint8_t PKT_END_WADDR2;                     /**< PKT_END_WADDR2, offset: 0xD2 */
+  __IO uint8_t PKT_END_WADDR3;                     /**< PKT_END_WADDR3, offset: 0xD3 */
+  __I  uint8_t OCR_0;                              /**< Operation Conditions 0, offset: 0xD4 */
+  __I  uint8_t OCR_1;                              /**< Operation Conditions 1, offset: 0xD5 */
+  __I  uint8_t OCR_2;                              /**< Operation Conditions 2, offset: 0xD6 */
+  __IO uint8_t CARD_CONFIG_1;                      /**< Card Config1, offset: 0xD7 */
+  __IO uint8_t CARD_CONFIG2_0;                     /**< Card Config2 0, offset: 0xD8 */
+  __IO uint8_t CARD_CONFIG2_1;                     /**< Card Config2 1, offset: 0xD9 */
+  __IO uint8_t CARD_CONFIG2_2;                     /**< Card Config2 2, offset: 0xDA */
+  __IO uint8_t CARD_CONFIG2_3;                     /**< Card Config2 3, offset: 0xDB */
+  __I  uint8_t TESTBUS0;                           /**< Testbus 0, offset: 0xDC */
+  __I  uint8_t TESTBUS1;                           /**< Testbus 1, offset: 0xDD */
+  __I  uint8_t RCA0;                               /**< RCA 0, offset: 0xDE */
+  __I  uint8_t RCA1;                               /**< RCA 1, offset: 0xDF */
+  __I  uint8_t DMA_ADDR0;                          /**< DMA Address 0, offset: 0xE0 */
+  __I  uint8_t DMA_ADDR1;                          /**< DMA Address 1, offset: 0xE1 */
+  __I  uint8_t DMA_ADDR2;                          /**< DMA Address 2, offset: 0xE2 */
+  __I  uint8_t DMA_ADDR3;                          /**< DMA Address 3, offset: 0xE3 */
+  __I  uint8_t IO_PORT0;                           /**< I/O Port 0, offset: 0xE4 */
+  __I  uint8_t IO_PORT1;                           /**< I/O Port 1, offset: 0xE5 */
+  __I  uint8_t IO_PORT2;                           /**< I/O Port 2, offset: 0xE6 */
+       uint8_t RESERVED_15[1];
+  __IO uint8_t SCRATCH2_0;                         /**< Scratch 2 0, offset: 0xE8 */
+  __IO uint8_t SCRATCH2_1;                         /**< Scratch 2 1, offset: 0xE9 */
+  __IO uint8_t SCRATCH2_2;                         /**< Scratch 2 2, offset: 0xEA */
+  __IO uint8_t SCRATCH2_3;                         /**< Scratch 2 3, offset: 0xEB */
+  __IO uint8_t SCRATCH3_0;                         /**< Scratch 3 0, offset: 0xEC */
+  __IO uint8_t SCRATCH3_1;                         /**< Scratch 3 1, offset: 0xED */
+  __IO uint8_t SCRATCH3_2;                         /**< Scratch 3 2, offset: 0xEE */
+  __IO uint8_t SCRATCH3_3;                         /**< Scratch 3 3, offset: 0xEF */
+  __IO uint8_t SCRATCH4_0;                         /**< Scratch 4 0, offset: 0xF0 */
+  __IO uint8_t SCRATCH4_1;                         /**< Scratch 4 1, offset: 0xF1 */
+  __IO uint8_t SCRATCH4_2;                         /**< Scratch 4 2, offset: 0xF2 */
+  __IO uint8_t SCRATCH4_3;                         /**< Scratch 4 3, offset: 0xF3 */
+  __IO uint8_t SCRATCH5_0;                         /**< Scratch 5 0, offset: 0xF4 */
+  __IO uint8_t SCRATCH5_1;                         /**< Scratch 5 1, offset: 0xF5 */
+  __IO uint8_t SCRATCH5_2;                         /**< Scratch 5 2, offset: 0xF6 */
+  __IO uint8_t SCRATCH5_3;                         /**< Scratch 5 3, offset: 0xF7 */
+  __IO uint8_t SCRATCH6_0;                         /**< Scratch 6 0, offset: 0xF8 */
+  __IO uint8_t SCRATCH6_1;                         /**< Scratch 6 1, offset: 0xF9 */
+  __IO uint8_t SCRATCH6_2;                         /**< Scratch 6 2, offset: 0xFA */
+  __IO uint8_t SCRATCH6_3;                         /**< Scratch 6 3, offset: 0xFB */
+  __IO uint8_t SCRATCH7_0;                         /**< Scratch 7 0, offset: 0xFC */
+  __IO uint8_t SCRATCH7_1;                         /**< Scratch 7 1, offset: 0xFD */
+  __IO uint8_t SCRATCH7_2;                         /**< Scratch 7 2, offset: 0xFE */
+  __IO uint8_t SCRATCH7_3;                         /**< Scratch 7 3, offset: 0xFF */
+} SDU_FN_CARD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDU_FN_CARD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDU_FN_CARD_Register_Masks SDU_FN_CARD Register Masks
+ * @{
+ */
+
+/*! @name H2C_INTEVENT - Host to Card Interrupt Event */
+/*! @{ */
+
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_DOWN_MASK (0x1U)
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_DOWN_SHIFT (0U)
+/*! HOST_PWR_DOWN - Host power down event When host sets this bit, interrupt is generated to the CPU. */
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_DOWN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_DOWN_SHIFT)) & SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_DOWN_MASK)
+
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_UP_MASK (0x2U)
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_UP_SHIFT (1U)
+/*! HOST_PWR_UP - Host power up event When host sets this bit, interrupt is generated to the CPU. */
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_UP(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_UP_SHIFT)) & SDU_FN_CARD_H2C_INTEVENT_HOST_PWR_UP_MASK)
+
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_TERMINATE_CMD53_MASK (0x4U)
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_TERMINATE_CMD53_SHIFT (2U)
+/*! HOST_TERMINATE_CMD53 - Host terminates CMD53 When host sets this bit, current cmd53 data transfer will terminate. */
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_TERMINATE_CMD53(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_H2C_INTEVENT_HOST_TERMINATE_CMD53_SHIFT)) & SDU_FN_CARD_H2C_INTEVENT_HOST_TERMINATE_CMD53_MASK)
+
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_TO_CARD_EVENT_MASK (0x8U)
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_TO_CARD_EVENT_SHIFT (3U)
+/*! HOST_TO_CARD_EVENT - Host to card event When host sets this bit, interrupt is generated to the CPU. */
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_TO_CARD_EVENT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_H2C_INTEVENT_HOST_TO_CARD_EVENT_SHIFT)) & SDU_FN_CARD_H2C_INTEVENT_HOST_TO_CARD_EVENT_MASK)
+
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_RST_EVENT_MASK (0x10U)
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_RST_EVENT_SHIFT (4U)
+/*! HOST_RST_EVENT - Host reset event When host sets this bit, interrupt is generated to the CPU. */
+#define SDU_FN_CARD_H2C_INTEVENT_HOST_RST_EVENT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_H2C_INTEVENT_HOST_RST_EVENT_SHIFT)) & SDU_FN_CARD_H2C_INTEVENT_HOST_RST_EVENT_MASK)
+/*! @} */
+
+/*! @name HOST_INTRSR0 - Host Interrupt Reset Select 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INTRSR0_HOST_INT_RSR0_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INTRSR0_HOST_INT_RSR0_SHIFT (0U)
+/*! HOST_INT_RSR0 - Host Interrupt Reset Select [7:0] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read */
+#define SDU_FN_CARD_HOST_INTRSR0_HOST_INT_RSR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTRSR0_HOST_INT_RSR0_SHIFT)) & SDU_FN_CARD_HOST_INTRSR0_HOST_INT_RSR0_MASK)
+/*! @} */
+
+/*! @name HOST_INTRSR1 - Host Interrupt Reset Select 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INTRSR1_HOST_INT_RSR1_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INTRSR1_HOST_INT_RSR1_SHIFT (0U)
+/*! HOST_INT_RSR1 - Host Interrupt Reset Select [15:8] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read */
+#define SDU_FN_CARD_HOST_INTRSR1_HOST_INT_RSR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTRSR1_HOST_INT_RSR1_SHIFT)) & SDU_FN_CARD_HOST_INTRSR1_HOST_INT_RSR1_MASK)
+/*! @} */
+
+/*! @name HOST_INTMASK0 - Host Interrupt Mask 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INTMASK0_HOST_INT_MASK0_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INTMASK0_HOST_INT_MASK0_SHIFT (0U)
+/*! HOST_INT_MASK0 - Host Interrupt Mask [7:0] 0 = disable card to host interrupt 1 = enable card to host interrupt */
+#define SDU_FN_CARD_HOST_INTMASK0_HOST_INT_MASK0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTMASK0_HOST_INT_MASK0_SHIFT)) & SDU_FN_CARD_HOST_INTMASK0_HOST_INT_MASK0_MASK)
+/*! @} */
+
+/*! @name HOST_INTMASK1 - Host Interrupt Mask 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INTMASK1_HOST_INT_MASK1_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INTMASK1_HOST_INT_MASK1_SHIFT (0U)
+/*! HOST_INT_MASK1 - Host Interrupt Mask [15:8] 0 = disable card to host interrupt 1 = enable card to host interrupt */
+#define SDU_FN_CARD_HOST_INTMASK1_HOST_INT_MASK1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTMASK1_HOST_INT_MASK1_SHIFT)) & SDU_FN_CARD_HOST_INTMASK1_HOST_INT_MASK1_MASK)
+/*! @} */
+
+/*! @name HOST_INTSTATUS0 - Host Interrupt Status 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INTSTATUS0_Q0_UPLD_HOST_INT_MASK (0x1U)
+#define SDU_FN_CARD_HOST_INTSTATUS0_Q0_UPLD_HOST_INT_SHIFT (0U)
+/*! Q0_UPLD_HOST_INT - Queue 0 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state. */
+#define SDU_FN_CARD_HOST_INTSTATUS0_Q0_UPLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS0_Q0_UPLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS0_Q0_UPLD_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS0_Q0_DNLD_HOST_INT_MASK (0x2U)
+#define SDU_FN_CARD_HOST_INTSTATUS0_Q0_DNLD_HOST_INT_SHIFT (1U)
+/*! Q0_DNLD_HOST_INT - Queue 0 Download Host Interrupt Status Set when card is ready for download from host. */
+#define SDU_FN_CARD_HOST_INTSTATUS0_Q0_DNLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS0_Q0_DNLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS0_Q0_DNLD_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS0_FIFO_UNDERFLOW_MASK (0x4U)
+#define SDU_FN_CARD_HOST_INTSTATUS0_FIFO_UNDERFLOW_SHIFT (2U)
+/*! FIFO_UNDERFLOW - Fifo Underflow Set when FIFO underflow occurs during upload. */
+#define SDU_FN_CARD_HOST_INTSTATUS0_FIFO_UNDERFLOW(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS0_FIFO_UNDERFLOW_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS0_FIFO_UNDERFLOW_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS0_FIFO_OVERFLOW_MASK (0x8U)
+#define SDU_FN_CARD_HOST_INTSTATUS0_FIFO_OVERFLOW_SHIFT (3U)
+/*! FIFO_OVERFLOW - Fifo Overflow Set when FIFO overflow occurs during download. */
+#define SDU_FN_CARD_HOST_INTSTATUS0_FIFO_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS0_FIFO_OVERFLOW_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS0_FIFO_OVERFLOW_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS0_CARD_TO_HOST_INT_MASK (0x30U)
+#define SDU_FN_CARD_HOST_INTSTATUS0_CARD_TO_HOST_INT_SHIFT (4U)
+/*! CARD_TO_HOST_INT - 2-bit FW controlled interrupts to host. */
+#define SDU_FN_CARD_HOST_INTSTATUS0_CARD_TO_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS0_CARD_TO_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS0_CARD_TO_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_UPLD_INT_MASK (0x40U)
+#define SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_UPLD_INT_SHIFT (6U)
+/*! CMD_PORT_UPLD_INT - Command Port Upload Host Interrupt Status Set when card has packet ready for
+ *    command port upload and card is in I/O ready state.
+ */
+#define SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_UPLD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_UPLD_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_UPLD_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_DNLD_INT_MASK (0x80U)
+#define SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_DNLD_INT_SHIFT (7U)
+/*! CMD_PORT_DNLD_INT - Command Port Download Host Interrupt Status Set when card is ready for command port download from host. */
+#define SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_DNLD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_DNLD_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS0_CMD_PORT_DNLD_INT_MASK)
+/*! @} */
+
+/*! @name HOST_INTSTATUS1 - Host Interrupt Status 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q1_UPLD_HOST_INT_MASK (0x1U)
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q1_UPLD_HOST_INT_SHIFT (0U)
+/*! Q1_UPLD_HOST_INT - Queue 1 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state. */
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q1_UPLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS1_Q1_UPLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS1_Q1_UPLD_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q2_UPLD_HOST_INT_MASK (0x2U)
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q2_UPLD_HOST_INT_SHIFT (1U)
+/*! Q2_UPLD_HOST_INT - Queue 2 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state. */
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q2_UPLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS1_Q2_UPLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS1_Q2_UPLD_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q3_UPLD_HOST_INT_MASK (0x4U)
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q3_UPLD_HOST_INT_SHIFT (2U)
+/*! Q3_UPLD_HOST_INT - Queue 3 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state. */
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q3_UPLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS1_Q3_UPLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS1_Q3_UPLD_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q1_DNLD_HOST_INT_MASK (0x8U)
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q1_DNLD_HOST_INT_SHIFT (3U)
+/*! Q1_DNLD_HOST_INT - Queue 1 Download Host Interrupt Status Set when card is ready for download from host. */
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q1_DNLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS1_Q1_DNLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS1_Q1_DNLD_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q2_DNLD_HOST_INT_MASK (0x10U)
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q2_DNLD_HOST_INT_SHIFT (4U)
+/*! Q2_DNLD_HOST_INT - Queue 2 Download Host Interrupt Status Set when card is ready for download from host. */
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q2_DNLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS1_Q2_DNLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS1_Q2_DNLD_HOST_INT_MASK)
+
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q3_DNLD_HOST_INT_MASK (0x20U)
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q3_DNLD_HOST_INT_SHIFT (5U)
+/*! Q3_DNLD_HOST_INT - Queue 3 Download Host Interrupt Status Set when card is ready for download from host. */
+#define SDU_FN_CARD_HOST_INTSTATUS1_Q3_DNLD_HOST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INTSTATUS1_Q3_DNLD_HOST_INT_SHIFT)) & SDU_FN_CARD_HOST_INTSTATUS1_Q3_DNLD_HOST_INT_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP0 - Packet Read Bitmap 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP0_MASK (0x1U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP0_SHIFT (0U)
+/*! PKT_RD_BITMAP0 - Packet read bitmap[0] */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP0_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP0_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP1_MASK (0x2U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP1_SHIFT (1U)
+/*! PKT_RD_BITMAP1 - Packet read bitmap[1] */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP1_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP1_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP2_MASK (0x4U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP2_SHIFT (2U)
+/*! PKT_RD_BITMAP2 - Packet read bitmap[2] */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP2_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP2_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP3_MASK (0x8U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP3_SHIFT (3U)
+/*! PKT_RD_BITMAP3 - Packet read bitmap[3] */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP3_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP3_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP4_MASK (0x10U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP4_SHIFT (4U)
+/*! PKT_RD_BITMAP4 - Packet read bitmap[4] */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP4(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP4_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP4_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP5_MASK (0x20U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP5_SHIFT (5U)
+/*! PKT_RD_BITMAP5 - Packet read bitmap[5] */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP5(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP5_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP5_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP6_MASK (0x40U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP6_SHIFT (6U)
+/*! PKT_RD_BITMAP6 - Packet read bitmap[6] */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP6(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP6_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP6_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP7_MASK (0x80U)
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP7_SHIFT (7U)
+/*! PKT_RD_BITMAP7 - Packet read bitmap[7]. */
+#define SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP7(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP7_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP0_PKT_RD_BITMAP7_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP1 - Packet Read Bitmap 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP8_MASK (0x1U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP8_SHIFT (0U)
+/*! PKT_RD_BITMAP8 - Packet read bitmap[8] */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP8(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP8_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP8_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP9_MASK (0x2U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP9_SHIFT (1U)
+/*! PKT_RD_BITMAP9 - Packet read bitmap[9] */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP9(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP9_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP9_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP10_MASK (0x4U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP10_SHIFT (2U)
+/*! PKT_RD_BITMAP10 - Packet read bitmap[10] */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP10(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP10_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP10_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP11_MASK (0x8U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP11_SHIFT (3U)
+/*! PKT_RD_BITMAP11 - Packet read bitmap[11] */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP11(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP11_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP11_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP12_MASK (0x10U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP12_SHIFT (4U)
+/*! PKT_RD_BITMAP12 - Packet read bitmap[12] */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP12(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP12_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP12_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP13_MASK (0x20U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP13_SHIFT (5U)
+/*! PKT_RD_BITMAP13 - Packet read bitmap[13] */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP13(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP13_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP13_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP14_MASK (0x40U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP14_SHIFT (6U)
+/*! PKT_RD_BITMAP14 - Packet read bitmap[14] */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP14(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP14_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP14_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP15_MASK (0x80U)
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP15_SHIFT (7U)
+/*! PKT_RD_BITMAP15 - Packet read bitmap[15]. */
+#define SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP15(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP15_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP1_PKT_RD_BITMAP15_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP2 - Packet Read Bitmap 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP16_MASK (0x1U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP16_SHIFT (0U)
+/*! PKT_RD_BITMAP16 - Packet read bitmap[16] */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP16(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP16_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP16_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP17_MASK (0x2U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP17_SHIFT (1U)
+/*! PKT_RD_BITMAP17 - Packet read bitmap[17] */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP17(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP17_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP17_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP18_MASK (0x4U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP18_SHIFT (2U)
+/*! PKT_RD_BITMAP18 - Packet read bitmap[18] */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP18(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP18_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP18_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP19_MASK (0x8U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP19_SHIFT (3U)
+/*! PKT_RD_BITMAP19 - Packet read bitmap[19] */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP19(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP19_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP19_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP20_MASK (0x10U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP20_SHIFT (4U)
+/*! PKT_RD_BITMAP20 - Packet read bitmap[20] */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP20(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP20_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP20_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP21_MASK (0x20U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP21_SHIFT (5U)
+/*! PKT_RD_BITMAP21 - Packet read bitmap[21] */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP21(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP21_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP21_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP22_MASK (0x40U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP22_SHIFT (6U)
+/*! PKT_RD_BITMAP22 - Packet read bitmap[22] */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP22(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP22_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP22_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP23_MASK (0x80U)
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP23_SHIFT (7U)
+/*! PKT_RD_BITMAP23 - Packet read bitmap[23]. */
+#define SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP23(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP23_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP2_PKT_RD_BITMAP23_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP3 - Packet Read Bitmap 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP24_MASK (0x1U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP24_SHIFT (0U)
+/*! PKT_RD_BITMAP24 - Packet read bitmap[24] */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP24(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP24_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP24_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP25_MASK (0x2U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP25_SHIFT (1U)
+/*! PKT_RD_BITMAP25 - Packet read bitmap[25] */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP25(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP25_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP25_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP26_MASK (0x4U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP26_SHIFT (2U)
+/*! PKT_RD_BITMAP26 - Packet read bitmap[26] */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP26(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP26_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP26_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP27_MASK (0x8U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP27_SHIFT (3U)
+/*! PKT_RD_BITMAP27 - Packet read bitmap[27] */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP27(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP27_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP27_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP28_MASK (0x10U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP28_SHIFT (4U)
+/*! PKT_RD_BITMAP28 - Packet read bitmap[28] */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP28(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP28_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP28_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP29_MASK (0x20U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP29_SHIFT (5U)
+/*! PKT_RD_BITMAP29 - Packet read bitmap[29] */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP29(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP29_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP29_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP30_MASK (0x40U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP30_SHIFT (6U)
+/*! PKT_RD_BITMAP30 - Packet read bitmap[30] */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP30(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP30_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP30_MASK)
+
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP31_MASK (0x80U)
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP31_SHIFT (7U)
+/*! PKT_RD_BITMAP31 - Packet read bitmap[31]. */
+#define SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP31(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP31_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP3_PKT_RD_BITMAP31_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP0 - Packet Write Bitmap 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP0_MASK (0x1U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP0_SHIFT (0U)
+/*! PKT_WR_BITMAP0 - Packet write bitmap[0] */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP0_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP0_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP1_MASK (0x2U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP1_SHIFT (1U)
+/*! PKT_WR_BITMAP1 - Packet write bitmap[1] */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP1_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP1_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP2_MASK (0x4U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP2_SHIFT (2U)
+/*! PKT_WR_BITMAP2 - Packet write bitmap[2] */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP2_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP2_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP3_MASK (0x8U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP3_SHIFT (3U)
+/*! PKT_WR_BITMAP3 - Packet write bitmap[3] */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP3_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP3_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP4_MASK (0x10U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP4_SHIFT (4U)
+/*! PKT_WR_BITMAP4 - Packet write bitmap[4] */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP4(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP4_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP4_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP5_MASK (0x20U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP5_SHIFT (5U)
+/*! PKT_WR_BITMAP5 - Packet write bitmap[5] */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP5(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP5_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP5_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP6_MASK (0x40U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP6_SHIFT (6U)
+/*! PKT_WR_BITMAP6 - Packet write bitmap[6] */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP6(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP6_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP6_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP7_MASK (0x80U)
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP7_SHIFT (7U)
+/*! PKT_WR_BITMAP7 - Packet write bitmap[7]. */
+#define SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP7(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP7_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP0_PKT_WR_BITMAP7_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP1 - Packet Write Bitmap 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP8_MASK (0x1U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP8_SHIFT (0U)
+/*! PKT_WR_BITMAP8 - Packet write bitmap[8] */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP8(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP8_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP8_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP9_MASK (0x2U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP9_SHIFT (1U)
+/*! PKT_WR_BITMAP9 - Packet write bitmap[9] */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP9(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP9_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP9_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP10_MASK (0x4U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP10_SHIFT (2U)
+/*! PKT_WR_BITMAP10 - Packet write bitmap[10] */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP10(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP10_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP10_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP11_MASK (0x8U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP11_SHIFT (3U)
+/*! PKT_WR_BITMAP11 - Packet write bitmap[11] */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP11(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP11_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP11_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP12_MASK (0x10U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP12_SHIFT (4U)
+/*! PKT_WR_BITMAP12 - Packet write bitmap[12] */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP12(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP12_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP12_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP13_MASK (0x20U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP13_SHIFT (5U)
+/*! PKT_WR_BITMAP13 - Packet write bitmap[13] */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP13(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP13_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP13_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP14_MASK (0x40U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP14_SHIFT (6U)
+/*! PKT_WR_BITMAP14 - Packet write bitmap[14] */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP14(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP14_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP14_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP15_MASK (0x80U)
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP15_SHIFT (7U)
+/*! PKT_WR_BITMAP15 - Packet write bitmap[15]. */
+#define SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP15(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP15_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP1_PKT_WR_BITMAP15_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP2 - Packet Write Bitmap 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP16_MASK (0x1U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP16_SHIFT (0U)
+/*! PKT_WR_BITMAP16 - Packet write bitmap[16] */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP16(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP16_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP16_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP17_MASK (0x2U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP17_SHIFT (1U)
+/*! PKT_WR_BITMAP17 - Packet write bitmap[17] */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP17(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP17_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP17_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP18_MASK (0x4U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP18_SHIFT (2U)
+/*! PKT_WR_BITMAP18 - Packet write bitmap[18] */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP18(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP18_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP18_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP19_MASK (0x8U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP19_SHIFT (3U)
+/*! PKT_WR_BITMAP19 - Packet write bitmap[19] */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP19(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP19_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP19_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP20_MASK (0x10U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP20_SHIFT (4U)
+/*! PKT_WR_BITMAP20 - Packet write bitmap[20] */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP20(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP20_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP20_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP21_MASK (0x20U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP21_SHIFT (5U)
+/*! PKT_WR_BITMAP21 - Packet write bitmap[21] */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP21(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP21_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP21_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP22_MASK (0x40U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP22_SHIFT (6U)
+/*! PKT_WR_BITMAP22 - Packet write bitmap[22] */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP22(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP22_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP22_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP23_MASK (0x80U)
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP23_SHIFT (7U)
+/*! PKT_WR_BITMAP23 - Packet write bitmap[23]. */
+#define SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP23(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP23_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP2_PKT_WR_BITMAP23_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP3 - Packet Write Bitmap 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP24_MASK (0x1U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP24_SHIFT (0U)
+/*! PKT_WR_BITMAP24 - Packet write bitmap[24] */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP24(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP24_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP24_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP25_MASK (0x2U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP25_SHIFT (1U)
+/*! PKT_WR_BITMAP25 - Packet write bitmap[25] */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP25(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP25_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP25_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP26_MASK (0x4U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP26_SHIFT (2U)
+/*! PKT_WR_BITMAP26 - Packet write bitmap[26] */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP26(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP26_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP26_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP27_MASK (0x8U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP27_SHIFT (3U)
+/*! PKT_WR_BITMAP27 - Packet write bitmap[27] */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP27(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP27_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP27_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP28_MASK (0x10U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP28_SHIFT (4U)
+/*! PKT_WR_BITMAP28 - Packet write bitmap[28] */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP28(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP28_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP28_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP29_MASK (0x20U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP29_SHIFT (5U)
+/*! PKT_WR_BITMAP29 - Packet write bitmap[29] */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP29(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP29_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP29_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP30_MASK (0x40U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP30_SHIFT (6U)
+/*! PKT_WR_BITMAP30 - Packet write bitmap[30] */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP30(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP30_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP30_MASK)
+
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP31_MASK (0x80U)
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP31_SHIFT (7U)
+/*! PKT_WR_BITMAP31 - Packet write bitmap[31]. */
+#define SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP31(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP31_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP3_PKT_WR_BITMAP31_MASK)
+/*! @} */
+
+/*! @name PORT0_RD_LEN0 - Port 0 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT0_RD_LEN0_PORT0_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT0_RD_LEN0_PORT0_RD_LEN0_SHIFT (0U)
+/*! PORT0_RD_LEN0 - Port 0 read length [7:0] */
+#define SDU_FN_CARD_PORT0_RD_LEN0_PORT0_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT0_RD_LEN0_PORT0_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT0_RD_LEN0_PORT0_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT0_RD_LEN1 - Port 0 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT0_RD_LEN1_PORT0_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT0_RD_LEN1_PORT0_RD_LEN1_SHIFT (0U)
+/*! PORT0_RD_LEN1 - Port 0 read length [15:8] */
+#define SDU_FN_CARD_PORT0_RD_LEN1_PORT0_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT0_RD_LEN1_PORT0_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT0_RD_LEN1_PORT0_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT1_RD_LEN0 - Port 1 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT1_RD_LEN0_PORT1_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT1_RD_LEN0_PORT1_RD_LEN0_SHIFT (0U)
+/*! PORT1_RD_LEN0 - Port 1 read length [7:0] */
+#define SDU_FN_CARD_PORT1_RD_LEN0_PORT1_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT1_RD_LEN0_PORT1_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT1_RD_LEN0_PORT1_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT1_RD_LEN1 - Port 1 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT1_RD_LEN1_PORT1_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT1_RD_LEN1_PORT1_RD_LEN1_SHIFT (0U)
+/*! PORT1_RD_LEN1 - Port 1 read length [15:8] */
+#define SDU_FN_CARD_PORT1_RD_LEN1_PORT1_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT1_RD_LEN1_PORT1_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT1_RD_LEN1_PORT1_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT2_RD_LEN0 - Port 2 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT2_RD_LEN0_PORT2_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT2_RD_LEN0_PORT2_RD_LEN0_SHIFT (0U)
+/*! PORT2_RD_LEN0 - Port 2 read length [7:0] */
+#define SDU_FN_CARD_PORT2_RD_LEN0_PORT2_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT2_RD_LEN0_PORT2_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT2_RD_LEN0_PORT2_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT2_RD_LEN1 - Port 2 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT2_RD_LEN1_PORT2_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT2_RD_LEN1_PORT2_RD_LEN1_SHIFT (0U)
+/*! PORT2_RD_LEN1 - Port 2 read length [15:8] */
+#define SDU_FN_CARD_PORT2_RD_LEN1_PORT2_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT2_RD_LEN1_PORT2_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT2_RD_LEN1_PORT2_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT3_RD_LEN0 - Port 3 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT3_RD_LEN0_PORT3_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT3_RD_LEN0_PORT3_RD_LEN0_SHIFT (0U)
+/*! PORT3_RD_LEN0 - Port 3 read length [7:0] */
+#define SDU_FN_CARD_PORT3_RD_LEN0_PORT3_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT3_RD_LEN0_PORT3_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT3_RD_LEN0_PORT3_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT3_RD_LEN1 - Port 3 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT3_RD_LEN1_PORT3_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT3_RD_LEN1_PORT3_RD_LEN1_SHIFT (0U)
+/*! PORT3_RD_LEN1 - Port 3 read length [15:8] */
+#define SDU_FN_CARD_PORT3_RD_LEN1_PORT3_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT3_RD_LEN1_PORT3_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT3_RD_LEN1_PORT3_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT4_RD_LEN0 - Port 4 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT4_RD_LEN0_PORT4_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT4_RD_LEN0_PORT4_RD_LEN0_SHIFT (0U)
+/*! PORT4_RD_LEN0 - Port 4 read length [7:0] */
+#define SDU_FN_CARD_PORT4_RD_LEN0_PORT4_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT4_RD_LEN0_PORT4_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT4_RD_LEN0_PORT4_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT4_RD_LEN1 - Port 4 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT4_RD_LEN1_PORT4_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT4_RD_LEN1_PORT4_RD_LEN1_SHIFT (0U)
+/*! PORT4_RD_LEN1 - Port 4 read length [15:8] */
+#define SDU_FN_CARD_PORT4_RD_LEN1_PORT4_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT4_RD_LEN1_PORT4_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT4_RD_LEN1_PORT4_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT5_RD_LEN0 - Port 5 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT5_RD_LEN0_PORT5_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT5_RD_LEN0_PORT5_RD_LEN0_SHIFT (0U)
+/*! PORT5_RD_LEN0 - Port 5 read length [7:0] */
+#define SDU_FN_CARD_PORT5_RD_LEN0_PORT5_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT5_RD_LEN0_PORT5_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT5_RD_LEN0_PORT5_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT5_RD_LEN1 - Port 5 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT5_RD_LEN1_PORT5_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT5_RD_LEN1_PORT5_RD_LEN1_SHIFT (0U)
+/*! PORT5_RD_LEN1 - Port 5 read length [15:8] */
+#define SDU_FN_CARD_PORT5_RD_LEN1_PORT5_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT5_RD_LEN1_PORT5_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT5_RD_LEN1_PORT5_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT6_RD_LEN0 - Port 6 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT6_RD_LEN0_PORT6_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT6_RD_LEN0_PORT6_RD_LEN0_SHIFT (0U)
+/*! PORT6_RD_LEN0 - Port 6 read length [7:0] */
+#define SDU_FN_CARD_PORT6_RD_LEN0_PORT6_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT6_RD_LEN0_PORT6_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT6_RD_LEN0_PORT6_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT6_RD_LEN1 - Port 6 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT6_RD_LEN1_PORT6_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT6_RD_LEN1_PORT6_RD_LEN1_SHIFT (0U)
+/*! PORT6_RD_LEN1 - Port 6 read length [15:8] */
+#define SDU_FN_CARD_PORT6_RD_LEN1_PORT6_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT6_RD_LEN1_PORT6_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT6_RD_LEN1_PORT6_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT7_RD_LEN0 - Port 7 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT7_RD_LEN0_PORT7_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT7_RD_LEN0_PORT7_RD_LEN0_SHIFT (0U)
+/*! PORT7_RD_LEN0 - Port 7 read length [7:0] */
+#define SDU_FN_CARD_PORT7_RD_LEN0_PORT7_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT7_RD_LEN0_PORT7_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT7_RD_LEN0_PORT7_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT7_RD_LEN1 - Port 7 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT7_RD_LEN1_PORT7_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT7_RD_LEN1_PORT7_RD_LEN1_SHIFT (0U)
+/*! PORT7_RD_LEN1 - Port 7 read length [15:8] */
+#define SDU_FN_CARD_PORT7_RD_LEN1_PORT7_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT7_RD_LEN1_PORT7_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT7_RD_LEN1_PORT7_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT8_RD_LEN0 - Port 8 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT8_RD_LEN0_PORT8_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT8_RD_LEN0_PORT8_RD_LEN0_SHIFT (0U)
+/*! PORT8_RD_LEN0 - Port 8 read length [7:0] */
+#define SDU_FN_CARD_PORT8_RD_LEN0_PORT8_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT8_RD_LEN0_PORT8_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT8_RD_LEN0_PORT8_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT8_RD_LEN1 - Port 8 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT8_RD_LEN1_PORT8_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT8_RD_LEN1_PORT8_RD_LEN1_SHIFT (0U)
+/*! PORT8_RD_LEN1 - Port 8 read length [15:8] */
+#define SDU_FN_CARD_PORT8_RD_LEN1_PORT8_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT8_RD_LEN1_PORT8_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT8_RD_LEN1_PORT8_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT9_RD_LEN0 - Port 9 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT9_RD_LEN0_PORT9_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT9_RD_LEN0_PORT9_RD_LEN0_SHIFT (0U)
+/*! PORT9_RD_LEN0 - Port 9 read length [7:0] */
+#define SDU_FN_CARD_PORT9_RD_LEN0_PORT9_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT9_RD_LEN0_PORT9_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT9_RD_LEN0_PORT9_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT9_RD_LEN1 - Port 9 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT9_RD_LEN1_PORT9_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT9_RD_LEN1_PORT9_RD_LEN1_SHIFT (0U)
+/*! PORT9_RD_LEN1 - Port 9 read length [15:8] */
+#define SDU_FN_CARD_PORT9_RD_LEN1_PORT9_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT9_RD_LEN1_PORT9_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT9_RD_LEN1_PORT9_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT10_RD_LEN0 - Port 10 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT10_RD_LEN0_PORT10_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT10_RD_LEN0_PORT10_RD_LEN0_SHIFT (0U)
+/*! PORT10_RD_LEN0 - Port 10 read length [7:0] */
+#define SDU_FN_CARD_PORT10_RD_LEN0_PORT10_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT10_RD_LEN0_PORT10_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT10_RD_LEN0_PORT10_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT10_RD_LEN1 - Port 10 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT10_RD_LEN1_PORT10_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT10_RD_LEN1_PORT10_RD_LEN1_SHIFT (0U)
+/*! PORT10_RD_LEN1 - Port 10 read length [15:8] */
+#define SDU_FN_CARD_PORT10_RD_LEN1_PORT10_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT10_RD_LEN1_PORT10_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT10_RD_LEN1_PORT10_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT11_RD_LEN0 - Port 11 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT11_RD_LEN0_PORT11_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT11_RD_LEN0_PORT11_RD_LEN0_SHIFT (0U)
+/*! PORT11_RD_LEN0 - Port 11 read length [7:0] */
+#define SDU_FN_CARD_PORT11_RD_LEN0_PORT11_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT11_RD_LEN0_PORT11_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT11_RD_LEN0_PORT11_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT11_RD_LEN1 - Port 11 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT11_RD_LEN1_PORT11_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT11_RD_LEN1_PORT11_RD_LEN1_SHIFT (0U)
+/*! PORT11_RD_LEN1 - Port 11 read length [15:8] */
+#define SDU_FN_CARD_PORT11_RD_LEN1_PORT11_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT11_RD_LEN1_PORT11_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT11_RD_LEN1_PORT11_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT12_RD_LEN0 - Port 12 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT12_RD_LEN0_PORT12_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT12_RD_LEN0_PORT12_RD_LEN0_SHIFT (0U)
+/*! PORT12_RD_LEN0 - Port 12 read length [7:0] */
+#define SDU_FN_CARD_PORT12_RD_LEN0_PORT12_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT12_RD_LEN0_PORT12_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT12_RD_LEN0_PORT12_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT12_RD_LEN1 - Port 12 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT12_RD_LEN1_PORT12_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT12_RD_LEN1_PORT12_RD_LEN1_SHIFT (0U)
+/*! PORT12_RD_LEN1 - Port 12 read length [15:8] */
+#define SDU_FN_CARD_PORT12_RD_LEN1_PORT12_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT12_RD_LEN1_PORT12_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT12_RD_LEN1_PORT12_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT13_RD_LEN0 - Port 13 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT13_RD_LEN0_PORT13_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT13_RD_LEN0_PORT13_RD_LEN0_SHIFT (0U)
+/*! PORT13_RD_LEN0 - Port 13 read length [7:0] */
+#define SDU_FN_CARD_PORT13_RD_LEN0_PORT13_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT13_RD_LEN0_PORT13_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT13_RD_LEN0_PORT13_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT13_RD_LEN1 - Port 13 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT13_RD_LEN1_PORT13_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT13_RD_LEN1_PORT13_RD_LEN1_SHIFT (0U)
+/*! PORT13_RD_LEN1 - Port 13 read length [15:8] */
+#define SDU_FN_CARD_PORT13_RD_LEN1_PORT13_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT13_RD_LEN1_PORT13_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT13_RD_LEN1_PORT13_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT14_RD_LEN0 - Port 14 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT14_RD_LEN0_PORT14_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT14_RD_LEN0_PORT14_RD_LEN0_SHIFT (0U)
+/*! PORT14_RD_LEN0 - Port 14 read length [7:0] */
+#define SDU_FN_CARD_PORT14_RD_LEN0_PORT14_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT14_RD_LEN0_PORT14_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT14_RD_LEN0_PORT14_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT14_RD_LEN1 - Port 14 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT14_RD_LEN1_PORT14_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT14_RD_LEN1_PORT14_RD_LEN1_SHIFT (0U)
+/*! PORT14_RD_LEN1 - Port 14 read length [15:8] */
+#define SDU_FN_CARD_PORT14_RD_LEN1_PORT14_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT14_RD_LEN1_PORT14_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT14_RD_LEN1_PORT14_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT15_RD_LEN0 - Port 15 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT15_RD_LEN0_PORT15_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT15_RD_LEN0_PORT15_RD_LEN0_SHIFT (0U)
+/*! PORT15_RD_LEN0 - Port 15 read length [7:0] */
+#define SDU_FN_CARD_PORT15_RD_LEN0_PORT15_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT15_RD_LEN0_PORT15_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT15_RD_LEN0_PORT15_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT15_RD_LEN1 - Port 15 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT15_RD_LEN1_PORT15_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT15_RD_LEN1_PORT15_RD_LEN1_SHIFT (0U)
+/*! PORT15_RD_LEN1 - Port 15 read length [15:8] */
+#define SDU_FN_CARD_PORT15_RD_LEN1_PORT15_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT15_RD_LEN1_PORT15_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT15_RD_LEN1_PORT15_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT16_RD_LEN0 - Port 16 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT16_RD_LEN0_PORT16_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT16_RD_LEN0_PORT16_RD_LEN0_SHIFT (0U)
+/*! PORT16_RD_LEN0 - Port 16 read length [7:0] */
+#define SDU_FN_CARD_PORT16_RD_LEN0_PORT16_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT16_RD_LEN0_PORT16_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT16_RD_LEN0_PORT16_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT16_RD_LEN1 - Port 16 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT16_RD_LEN1_PORT16_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT16_RD_LEN1_PORT16_RD_LEN1_SHIFT (0U)
+/*! PORT16_RD_LEN1 - Port 16 read length [15:8] */
+#define SDU_FN_CARD_PORT16_RD_LEN1_PORT16_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT16_RD_LEN1_PORT16_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT16_RD_LEN1_PORT16_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT17_RD_LEN0 - Port 17 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT17_RD_LEN0_PORT17_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT17_RD_LEN0_PORT17_RD_LEN0_SHIFT (0U)
+/*! PORT17_RD_LEN0 - Port 17 read length [7:0] */
+#define SDU_FN_CARD_PORT17_RD_LEN0_PORT17_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT17_RD_LEN0_PORT17_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT17_RD_LEN0_PORT17_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT17_RD_LEN1 - Port 17 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT17_RD_LEN1_PORT17_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT17_RD_LEN1_PORT17_RD_LEN1_SHIFT (0U)
+/*! PORT17_RD_LEN1 - Port 17 read length [15:8] */
+#define SDU_FN_CARD_PORT17_RD_LEN1_PORT17_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT17_RD_LEN1_PORT17_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT17_RD_LEN1_PORT17_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT18_RD_LEN0 - Port 18 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT18_RD_LEN0_PORT18_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT18_RD_LEN0_PORT18_RD_LEN0_SHIFT (0U)
+/*! PORT18_RD_LEN0 - Port 18 read length [7:0] */
+#define SDU_FN_CARD_PORT18_RD_LEN0_PORT18_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT18_RD_LEN0_PORT18_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT18_RD_LEN0_PORT18_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT18_RD_LEN1 - Port 18 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT18_RD_LEN1_PORT18_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT18_RD_LEN1_PORT18_RD_LEN1_SHIFT (0U)
+/*! PORT18_RD_LEN1 - Port 18 read length [15:8] */
+#define SDU_FN_CARD_PORT18_RD_LEN1_PORT18_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT18_RD_LEN1_PORT18_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT18_RD_LEN1_PORT18_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT19_RD_LEN0 - Port 19 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT19_RD_LEN0_PORT19_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT19_RD_LEN0_PORT19_RD_LEN0_SHIFT (0U)
+/*! PORT19_RD_LEN0 - Port 19 read length [7:0] */
+#define SDU_FN_CARD_PORT19_RD_LEN0_PORT19_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT19_RD_LEN0_PORT19_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT19_RD_LEN0_PORT19_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT19_RD_LEN1 - Port 19 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT19_RD_LEN1_PORT19_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT19_RD_LEN1_PORT19_RD_LEN1_SHIFT (0U)
+/*! PORT19_RD_LEN1 - Port 19 read length [15:8] */
+#define SDU_FN_CARD_PORT19_RD_LEN1_PORT19_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT19_RD_LEN1_PORT19_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT19_RD_LEN1_PORT19_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT20_RD_LEN0 - Port 20 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT20_RD_LEN0_PORT20_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT20_RD_LEN0_PORT20_RD_LEN0_SHIFT (0U)
+/*! PORT20_RD_LEN0 - Port 20 read length [7:0] */
+#define SDU_FN_CARD_PORT20_RD_LEN0_PORT20_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT20_RD_LEN0_PORT20_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT20_RD_LEN0_PORT20_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT20_RD_LEN1 - Port 20 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT20_RD_LEN1_PORT20_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT20_RD_LEN1_PORT20_RD_LEN1_SHIFT (0U)
+/*! PORT20_RD_LEN1 - Port 20 read length [15:8] */
+#define SDU_FN_CARD_PORT20_RD_LEN1_PORT20_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT20_RD_LEN1_PORT20_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT20_RD_LEN1_PORT20_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT21_RD_LEN0 - Port 21 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT21_RD_LEN0_PORT21_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT21_RD_LEN0_PORT21_RD_LEN0_SHIFT (0U)
+/*! PORT21_RD_LEN0 - Port 21 read length [7:0] */
+#define SDU_FN_CARD_PORT21_RD_LEN0_PORT21_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT21_RD_LEN0_PORT21_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT21_RD_LEN0_PORT21_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT21_RD_LEN1 - Port 21 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT21_RD_LEN1_PORT21_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT21_RD_LEN1_PORT21_RD_LEN1_SHIFT (0U)
+/*! PORT21_RD_LEN1 - Port 21 read length [15:8] */
+#define SDU_FN_CARD_PORT21_RD_LEN1_PORT21_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT21_RD_LEN1_PORT21_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT21_RD_LEN1_PORT21_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT22_RD_LEN0 - Port 22 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT22_RD_LEN0_PORT22_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT22_RD_LEN0_PORT22_RD_LEN0_SHIFT (0U)
+/*! PORT22_RD_LEN0 - Port 22 read length [7:0] */
+#define SDU_FN_CARD_PORT22_RD_LEN0_PORT22_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT22_RD_LEN0_PORT22_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT22_RD_LEN0_PORT22_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT22_RD_LEN1 - Port 22 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT22_RD_LEN1_PORT22_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT22_RD_LEN1_PORT22_RD_LEN1_SHIFT (0U)
+/*! PORT22_RD_LEN1 - Port 22 read length [15:8] */
+#define SDU_FN_CARD_PORT22_RD_LEN1_PORT22_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT22_RD_LEN1_PORT22_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT22_RD_LEN1_PORT22_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT23_RD_LEN0 - Port 23 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT23_RD_LEN0_PORT23_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT23_RD_LEN0_PORT23_RD_LEN0_SHIFT (0U)
+/*! PORT23_RD_LEN0 - Port 23 read length [7:0] */
+#define SDU_FN_CARD_PORT23_RD_LEN0_PORT23_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT23_RD_LEN0_PORT23_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT23_RD_LEN0_PORT23_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT23_RD_LEN1 - Port 23 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT23_RD_LEN1_PORT23_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT23_RD_LEN1_PORT23_RD_LEN1_SHIFT (0U)
+/*! PORT23_RD_LEN1 - Port 23 read length [15:8] */
+#define SDU_FN_CARD_PORT23_RD_LEN1_PORT23_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT23_RD_LEN1_PORT23_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT23_RD_LEN1_PORT23_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT24_RD_LEN0 - Port 24 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT24_RD_LEN0_PORT24_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT24_RD_LEN0_PORT24_RD_LEN0_SHIFT (0U)
+/*! PORT24_RD_LEN0 - Port 24 read length [7:0] */
+#define SDU_FN_CARD_PORT24_RD_LEN0_PORT24_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT24_RD_LEN0_PORT24_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT24_RD_LEN0_PORT24_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT24_RD_LEN1 - Port 24 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT24_RD_LEN1_PORT24_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT24_RD_LEN1_PORT24_RD_LEN1_SHIFT (0U)
+/*! PORT24_RD_LEN1 - Port 24 read length [15:8] */
+#define SDU_FN_CARD_PORT24_RD_LEN1_PORT24_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT24_RD_LEN1_PORT24_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT24_RD_LEN1_PORT24_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT25_RD_LEN0 - Port 25 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT25_RD_LEN0_PORT25_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT25_RD_LEN0_PORT25_RD_LEN0_SHIFT (0U)
+/*! PORT25_RD_LEN0 - Port 25 read length [7:0] */
+#define SDU_FN_CARD_PORT25_RD_LEN0_PORT25_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT25_RD_LEN0_PORT25_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT25_RD_LEN0_PORT25_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT25_RD_LEN1 - Port 25 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT25_RD_LEN1_PORT25_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT25_RD_LEN1_PORT25_RD_LEN1_SHIFT (0U)
+/*! PORT25_RD_LEN1 - Port 25 read length [15:8] */
+#define SDU_FN_CARD_PORT25_RD_LEN1_PORT25_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT25_RD_LEN1_PORT25_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT25_RD_LEN1_PORT25_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT26_RD_LEN0 - Port 26 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT26_RD_LEN0_PORT26_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT26_RD_LEN0_PORT26_RD_LEN0_SHIFT (0U)
+/*! PORT26_RD_LEN0 - Port 26 read length [7:0] */
+#define SDU_FN_CARD_PORT26_RD_LEN0_PORT26_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT26_RD_LEN0_PORT26_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT26_RD_LEN0_PORT26_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT26_RD_LEN1 - Port 26 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT26_RD_LEN1_PORT26_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT26_RD_LEN1_PORT26_RD_LEN1_SHIFT (0U)
+/*! PORT26_RD_LEN1 - Port 26 read length [15:8] */
+#define SDU_FN_CARD_PORT26_RD_LEN1_PORT26_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT26_RD_LEN1_PORT26_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT26_RD_LEN1_PORT26_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT27_RD_LEN0 - Port 27 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT27_RD_LEN0_PORT27_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT27_RD_LEN0_PORT27_RD_LEN0_SHIFT (0U)
+/*! PORT27_RD_LEN0 - Port 27 read length [7:0] */
+#define SDU_FN_CARD_PORT27_RD_LEN0_PORT27_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT27_RD_LEN0_PORT27_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT27_RD_LEN0_PORT27_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT27_RD_LEN1 - Port 27 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT27_RD_LEN1_PORT27_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT27_RD_LEN1_PORT27_RD_LEN1_SHIFT (0U)
+/*! PORT27_RD_LEN1 - Port 27 read length [15:8] */
+#define SDU_FN_CARD_PORT27_RD_LEN1_PORT27_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT27_RD_LEN1_PORT27_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT27_RD_LEN1_PORT27_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT28_RD_LEN0 - Port 28 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT28_RD_LEN0_PORT28_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT28_RD_LEN0_PORT28_RD_LEN0_SHIFT (0U)
+/*! PORT28_RD_LEN0 - Port 28 read length [7:0] */
+#define SDU_FN_CARD_PORT28_RD_LEN0_PORT28_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT28_RD_LEN0_PORT28_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT28_RD_LEN0_PORT28_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT28_RD_LEN1 - Port 28 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT28_RD_LEN1_PORT28_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT28_RD_LEN1_PORT28_RD_LEN1_SHIFT (0U)
+/*! PORT28_RD_LEN1 - Port 28 read length [15:8] */
+#define SDU_FN_CARD_PORT28_RD_LEN1_PORT28_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT28_RD_LEN1_PORT28_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT28_RD_LEN1_PORT28_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT29_RD_LEN0 - Port 29 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT29_RD_LEN0_PORT29_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT29_RD_LEN0_PORT29_RD_LEN0_SHIFT (0U)
+/*! PORT29_RD_LEN0 - Port 29 read length [7:0] */
+#define SDU_FN_CARD_PORT29_RD_LEN0_PORT29_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT29_RD_LEN0_PORT29_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT29_RD_LEN0_PORT29_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT29_RD_LEN1 - Port 29 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT29_RD_LEN1_PORT29_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT29_RD_LEN1_PORT29_RD_LEN1_SHIFT (0U)
+/*! PORT29_RD_LEN1 - Port 29 read length [15:8] */
+#define SDU_FN_CARD_PORT29_RD_LEN1_PORT29_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT29_RD_LEN1_PORT29_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT29_RD_LEN1_PORT29_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT30_RD_LEN0 - Port 30 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT30_RD_LEN0_PORT30_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT30_RD_LEN0_PORT30_RD_LEN0_SHIFT (0U)
+/*! PORT30_RD_LEN0 - Port 30 read length [7:0] */
+#define SDU_FN_CARD_PORT30_RD_LEN0_PORT30_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT30_RD_LEN0_PORT30_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT30_RD_LEN0_PORT30_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT30_RD_LEN1 - Port 30 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT30_RD_LEN1_PORT30_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT30_RD_LEN1_PORT30_RD_LEN1_SHIFT (0U)
+/*! PORT30_RD_LEN1 - Port 30 read length [15:8] */
+#define SDU_FN_CARD_PORT30_RD_LEN1_PORT30_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT30_RD_LEN1_PORT30_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT30_RD_LEN1_PORT30_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name PORT31_RD_LEN0 - Port 31 Packet Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT31_RD_LEN0_PORT31_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_PORT31_RD_LEN0_PORT31_RD_LEN0_SHIFT (0U)
+/*! PORT31_RD_LEN0 - Port 31 read length [7:0] */
+#define SDU_FN_CARD_PORT31_RD_LEN0_PORT31_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT31_RD_LEN0_PORT31_RD_LEN0_SHIFT)) & SDU_FN_CARD_PORT31_RD_LEN0_PORT31_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name PORT31_RD_LEN1 - Port 31 Packet Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PORT31_RD_LEN1_PORT31_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_PORT31_RD_LEN1_PORT31_RD_LEN1_SHIFT (0U)
+/*! PORT31_RD_LEN1 - Port 31 read length [15:8] */
+#define SDU_FN_CARD_PORT31_RD_LEN1_PORT31_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PORT31_RD_LEN1_PORT31_RD_LEN1_SHIFT)) & SDU_FN_CARD_PORT31_RD_LEN1_PORT31_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name HOST_RESTART - Host Transfer Status */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_RESTART_DNLD_RESTART_MASK (0x1U)
+#define SDU_FN_CARD_HOST_RESTART_DNLD_RESTART_SHIFT (0U)
+/*! DNLD_RESTART - Download Restart Host sets this bit for the card to retransmit packet. */
+#define SDU_FN_CARD_HOST_RESTART_DNLD_RESTART(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_RESTART_DNLD_RESTART_SHIFT)) & SDU_FN_CARD_HOST_RESTART_DNLD_RESTART_MASK)
+
+#define SDU_FN_CARD_HOST_RESTART_UPLD_RESTART_MASK (0x2U)
+#define SDU_FN_CARD_HOST_RESTART_UPLD_RESTART_SHIFT (1U)
+/*! UPLD_RESTART - Upload Restart Host sets this bit for the card to retransmit packet. */
+#define SDU_FN_CARD_HOST_RESTART_UPLD_RESTART(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_RESTART_UPLD_RESTART_SHIFT)) & SDU_FN_CARD_HOST_RESTART_UPLD_RESTART_MASK)
+
+#define SDU_FN_CARD_HOST_RESTART_DNLD_CRC_ERR_MASK (0x4U)
+#define SDU_FN_CARD_HOST_RESTART_DNLD_CRC_ERR_SHIFT (2U)
+/*! DNLD_CRC_ERR - Download Cyclic Redundancy Check Error This bit is set by HW if there is a data
+ *    CRC error after a data block is downloaded.
+ */
+#define SDU_FN_CARD_HOST_RESTART_DNLD_CRC_ERR(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_RESTART_DNLD_CRC_ERR_SHIFT)) & SDU_FN_CARD_HOST_RESTART_DNLD_CRC_ERR_MASK)
+/*! @} */
+
+/*! @name FN_CARD_INTMASK - Function Card Interrupt Mask */
+/*! @{ */
+
+#define SDU_FN_CARD_FN_CARD_INTMASK_FN_CARD_INT_MASK_MASK (0x7U)
+#define SDU_FN_CARD_FN_CARD_INTMASK_FN_CARD_INT_MASK_SHIFT (0U)
+/*! FN_CARD_INT_MASK - Function card interrupt masks. */
+#define SDU_FN_CARD_FN_CARD_INTMASK_FN_CARD_INT_MASK(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_FN_CARD_INTMASK_FN_CARD_INT_MASK_SHIFT)) & SDU_FN_CARD_FN_CARD_INTMASK_FN_CARD_INT_MASK_MASK)
+/*! @} */
+
+/*! @name Q_PRT_RANGE0 - Queue Port Range 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_Q_PRT_RANGE0_Q0_PRT_RANGE_MASK (0x7U)
+#define SDU_FN_CARD_Q_PRT_RANGE0_Q0_PRT_RANGE_SHIFT (0U)
+/*! Q0_PRT_RANGE - Queue 0 Port Range Number of ports assigned per queue. */
+#define SDU_FN_CARD_Q_PRT_RANGE0_Q0_PRT_RANGE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_Q_PRT_RANGE0_Q0_PRT_RANGE_SHIFT)) & SDU_FN_CARD_Q_PRT_RANGE0_Q0_PRT_RANGE_MASK)
+
+#define SDU_FN_CARD_Q_PRT_RANGE0_Q1_PRT_RANGE_MASK (0x70U)
+#define SDU_FN_CARD_Q_PRT_RANGE0_Q1_PRT_RANGE_SHIFT (4U)
+/*! Q1_PRT_RANGE - Queue 1 Port Range Number of ports assigned per queue. */
+#define SDU_FN_CARD_Q_PRT_RANGE0_Q1_PRT_RANGE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_Q_PRT_RANGE0_Q1_PRT_RANGE_SHIFT)) & SDU_FN_CARD_Q_PRT_RANGE0_Q1_PRT_RANGE_MASK)
+/*! @} */
+
+/*! @name Q_PRT_RANGE1 - Queue Port Range 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_Q_PRT_RANGE1_Q2_PRT_RANGE_MASK (0x7U)
+#define SDU_FN_CARD_Q_PRT_RANGE1_Q2_PRT_RANGE_SHIFT (0U)
+/*! Q2_PRT_RANGE - Queue 2 Port Range Number of ports assigned per queue. */
+#define SDU_FN_CARD_Q_PRT_RANGE1_Q2_PRT_RANGE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_Q_PRT_RANGE1_Q2_PRT_RANGE_SHIFT)) & SDU_FN_CARD_Q_PRT_RANGE1_Q2_PRT_RANGE_MASK)
+
+#define SDU_FN_CARD_Q_PRT_RANGE1_Q3_PRT_RANGE_MASK (0x70U)
+#define SDU_FN_CARD_Q_PRT_RANGE1_Q3_PRT_RANGE_SHIFT (4U)
+/*! Q3_PRT_RANGE - Queue 3 Port Range Number of ports assigned per queue. */
+#define SDU_FN_CARD_Q_PRT_RANGE1_Q3_PRT_RANGE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_Q_PRT_RANGE1_Q3_PRT_RANGE_SHIFT)) & SDU_FN_CARD_Q_PRT_RANGE1_Q3_PRT_RANGE_MASK)
+/*! @} */
+
+/*! @name C2H_INTEVENT0 - Card to Host Event 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_C2H_INTEVENT0_Q0_DNLD_CARD_RDY_MASK (0x1U)
+#define SDU_FN_CARD_C2H_INTEVENT0_Q0_DNLD_CARD_RDY_SHIFT (0U)
+/*! Q0_DNLD_CARD_RDY - Queue 0 Download Card Ready Firmware sets this bit when one packet is ready. */
+#define SDU_FN_CARD_C2H_INTEVENT0_Q0_DNLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT0_Q0_DNLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT0_Q0_DNLD_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT0_Q0_UPLD_CARD_RDY_MASK (0x2U)
+#define SDU_FN_CARD_C2H_INTEVENT0_Q0_UPLD_CARD_RDY_SHIFT (1U)
+/*! Q0_UPLD_CARD_RDY - Queue 0 Upload Card Ready Firmware sets this bit when one packet is ready. */
+#define SDU_FN_CARD_C2H_INTEVENT0_Q0_UPLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT0_Q0_UPLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT0_Q0_UPLD_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT0_CIS_CARD_RDY_MASK (0x4U)
+#define SDU_FN_CARD_C2H_INTEVENT0_CIS_CARD_RDY_SHIFT (2U)
+/*! CIS_CARD_RDY - Card Information Structure Card Ready Firmware sets this bit after CIS table is initialized */
+#define SDU_FN_CARD_C2H_INTEVENT0_CIS_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT0_CIS_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT0_CIS_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT0_IO_READY_MASK  (0x8U)
+#define SDU_FN_CARD_C2H_INTEVENT0_IO_READY_SHIFT (3U)
+/*! IO_READY - I/O Ready Indicator SD target device accepts CMD53 only after the previous CMD53 has finished. */
+#define SDU_FN_CARD_C2H_INTEVENT0_IO_READY(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT0_IO_READY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT0_IO_READY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT0_CARD_TO_HOST_EVENT_MASK (0x30U)
+#define SDU_FN_CARD_C2H_INTEVENT0_CARD_TO_HOST_EVENT_SHIFT (4U)
+/*! CARD_TO_HOST_EVENT - Firmware controlled events to host. */
+#define SDU_FN_CARD_C2H_INTEVENT0_CARD_TO_HOST_EVENT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT0_CARD_TO_HOST_EVENT_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT0_CARD_TO_HOST_EVENT_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_UPLD_RDY_MASK (0x40U)
+#define SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_UPLD_RDY_SHIFT (6U)
+/*! CMD_PORT_UPLD_RDY - Command Port Upload Ready */
+#define SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_UPLD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_UPLD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_UPLD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_DNLD_RDY_MASK (0x80U)
+#define SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_DNLD_RDY_SHIFT (7U)
+/*! CMD_PORT_DNLD_RDY - Command Port Download Ready */
+#define SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_DNLD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_DNLD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT0_CMD_PORT_DNLD_RDY_MASK)
+/*! @} */
+
+/*! @name C2H_INTEVENT1 - Card to Host Event 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_C2H_INTEVENT1_Q1_DNLD_CARD_RDY_MASK (0x1U)
+#define SDU_FN_CARD_C2H_INTEVENT1_Q1_DNLD_CARD_RDY_SHIFT (0U)
+/*! Q1_DNLD_CARD_RDY - Queue 1 Download Card Ready */
+#define SDU_FN_CARD_C2H_INTEVENT1_Q1_DNLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT1_Q1_DNLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT1_Q1_DNLD_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT1_Q2_DNLD_CARD_RDY_MASK (0x2U)
+#define SDU_FN_CARD_C2H_INTEVENT1_Q2_DNLD_CARD_RDY_SHIFT (1U)
+/*! Q2_DNLD_CARD_RDY - Queue 2 Download Card Ready */
+#define SDU_FN_CARD_C2H_INTEVENT1_Q2_DNLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT1_Q2_DNLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT1_Q2_DNLD_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT1_Q3_DNLD_CARD_RDY_MASK (0x4U)
+#define SDU_FN_CARD_C2H_INTEVENT1_Q3_DNLD_CARD_RDY_SHIFT (2U)
+/*! Q3_DNLD_CARD_RDY - Queue 3 Download Card Ready */
+#define SDU_FN_CARD_C2H_INTEVENT1_Q3_DNLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT1_Q3_DNLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT1_Q3_DNLD_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT1_Q1_UPLD_CARD_RDY_MASK (0x8U)
+#define SDU_FN_CARD_C2H_INTEVENT1_Q1_UPLD_CARD_RDY_SHIFT (3U)
+/*! Q1_UPLD_CARD_RDY - Queue 1 Upload Card Ready */
+#define SDU_FN_CARD_C2H_INTEVENT1_Q1_UPLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT1_Q1_UPLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT1_Q1_UPLD_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT1_Q2_UPLD_CARD_RDY_MASK (0x10U)
+#define SDU_FN_CARD_C2H_INTEVENT1_Q2_UPLD_CARD_RDY_SHIFT (4U)
+/*! Q2_UPLD_CARD_RDY - Queue 2 Upload Card Ready */
+#define SDU_FN_CARD_C2H_INTEVENT1_Q2_UPLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT1_Q2_UPLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT1_Q2_UPLD_CARD_RDY_MASK)
+
+#define SDU_FN_CARD_C2H_INTEVENT1_Q3_UPLD_CARD_RDY_MASK (0x20U)
+#define SDU_FN_CARD_C2H_INTEVENT1_Q3_UPLD_CARD_RDY_SHIFT (5U)
+/*! Q3_UPLD_CARD_RDY - Queue 3 Upload Card Ready */
+#define SDU_FN_CARD_C2H_INTEVENT1_Q3_UPLD_CARD_RDY(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_C2H_INTEVENT1_Q3_UPLD_CARD_RDY_SHIFT)) & SDU_FN_CARD_C2H_INTEVENT1_Q3_UPLD_CARD_RDY_MASK)
+/*! @} */
+
+/*! @name CARD_INTMASK0 - Card Interrupt Mask 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTMASK0_CARD_INT_MASK0_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INTMASK0_CARD_INT_MASK0_SHIFT (0U)
+/*! CARD_INT_MASK0 - Host to Card Interrupt Mask[7:0] 0 = disable host to card interrupt 1 = enable host to card interrupt */
+#define SDU_FN_CARD_CARD_INTMASK0_CARD_INT_MASK0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTMASK0_CARD_INT_MASK0_SHIFT)) & SDU_FN_CARD_CARD_INTMASK0_CARD_INT_MASK0_MASK)
+/*! @} */
+
+/*! @name CARD_INTMASK1 - Card Interrupt Mask 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTMASK1_CARD_INT_MASK1_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INTMASK1_CARD_INT_MASK1_SHIFT (0U)
+/*! CARD_INT_MASK1 - Host to Card Interrupt Mask[15:8] 0 = disable host to card interrupt 1 = enable host to card interrupt */
+#define SDU_FN_CARD_CARD_INTMASK1_CARD_INT_MASK1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTMASK1_CARD_INT_MASK1_SHIFT)) & SDU_FN_CARD_CARD_INTMASK1_CARD_INT_MASK1_MASK)
+/*! @} */
+
+/*! @name CARD_INTMASK2 - Card Interrupt Mask 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTMASK2_CARD_INT_MASK2_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INTMASK2_CARD_INT_MASK2_SHIFT (0U)
+/*! CARD_INT_MASK2 - Host to Card Interrupt Mask [23:16] 0 = disable host to card interrupt 1 = enable host to card interrupt */
+#define SDU_FN_CARD_CARD_INTMASK2_CARD_INT_MASK2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTMASK2_CARD_INT_MASK2_SHIFT)) & SDU_FN_CARD_CARD_INTMASK2_CARD_INT_MASK2_MASK)
+/*! @} */
+
+/*! @name CARD_INTSTATUS0 - Card Interrupt Status 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_Q0_DNLD_CARD_INT_MASK (0x1U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_Q0_DNLD_CARD_INT_SHIFT (0U)
+/*! Q0_DNLD_CARD_INT - Queue 0 DnldCardInt event when (IO_Write) && DMA_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS0_Q0_DNLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_Q0_DNLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_Q0_DNLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_Q0_UPLD_CARD_INT_MASK (0x2U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_Q0_UPLD_CARD_INT_SHIFT (1U)
+/*! Q0_UPLD_CARD_INT - Queue 0 UpldCardInt event when (IO_Ready) && SD_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS0_Q0_UPLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_Q0_UPLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_Q0_UPLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_ABORT_CARD_INT_MASK (0x4U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_ABORT_CARD_INT_SHIFT (2U)
+/*! ABORT_CARD_INT - Abort CardInt event when abort pulse. */
+#define SDU_FN_CARD_CARD_INTSTATUS0_ABORT_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_ABORT_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_ABORT_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_DOWN_INT_MASK (0x8U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_DOWN_INT_SHIFT (3U)
+/*! HOST_PWR_DOWN_INT - Power down interrupt */
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_DOWN_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_DOWN_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_DOWN_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_UP_INT_MASK (0x10U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_UP_INT_SHIFT (4U)
+/*! HOST_PWR_UP_INT - Power up interrupt */
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_UP_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_UP_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_HOST_PWR_UP_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_UNDERFLOW_CARD_INT_MASK (0x20U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_UNDERFLOW_CARD_INT_SHIFT (5U)
+/*! UNDERFLOW_CARD_INT - Fifo underflow */
+#define SDU_FN_CARD_CARD_INTSTATUS0_UNDERFLOW_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_UNDERFLOW_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_UNDERFLOW_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_OVERFLOW_CARD_INT_MASK (0x40U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_OVERFLOW_CARD_INT_SHIFT (6U)
+/*! OVERFLOW_CARD_INT - Fifo overflow */
+#define SDU_FN_CARD_CARD_INTSTATUS0_OVERFLOW_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_OVERFLOW_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_OVERFLOW_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_TO_CARD_EVENT_MASK (0x80U)
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_TO_CARD_EVENT_SHIFT (7U)
+/*! HOST_TO_CARD_EVENT - Host interrupt to card */
+#define SDU_FN_CARD_CARD_INTSTATUS0_HOST_TO_CARD_EVENT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS0_HOST_TO_CARD_EVENT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS0_HOST_TO_CARD_EVENT_MASK)
+/*! @} */
+
+/*! @name CARD_INTSTATUS1 - Card Interrupt Status 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_IO_ENABLE_INT_MASK (0x1U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_IO_ENABLE_INT_SHIFT (0U)
+/*! IO_ENABLE_INT - This event is set when IO_ENABLE[fn] at FN0 0x02 is transitioned from 0-to-1 that is written by host */
+#define SDU_FN_CARD_CARD_INTSTATUS1_IO_ENABLE_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_IO_ENABLE_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_IO_ENABLE_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_IO_DISABLE_INT_MASK (0x2U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_IO_DISABLE_INT_SHIFT (1U)
+/*! IO_DISABLE_INT - This event is set when IO_ENABLE[fn] at FN0 0x02 is transitioned from 1-to-0 that is written by host */
+#define SDU_FN_CARD_CARD_INTSTATUS1_IO_DISABLE_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_IO_DISABLE_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_IO_DISABLE_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_UPLD_CARD_INT_MASK (0x4U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_UPLD_CARD_INT_SHIFT (2U)
+/*! CMD_PORT_UPLD_CARD_INT - This event is set if current cmd53 upload/rx data transfer is completed. */
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_UPLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_UPLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_UPLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_DNLD_CARD_INT_MASK (0x8U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_DNLD_CARD_INT_SHIFT (3U)
+/*! CMD_PORT_DNLD_CARD_INT - This event is set if current cmd53 download/tx data transfer is completed. */
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_DNLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_DNLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_CMD_PORT_DNLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD52_WR_ERR_INT_MASK (0x10U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD52_WR_ERR_INT_SHIFT (4U)
+/*! CMD52_WR_ERR_INT - This event is set if host issues cmd52 write access to off-domain register during sleep mode. */
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD52_WR_ERR_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_CMD52_WR_ERR_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_CMD52_WR_ERR_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD52_RD_ERR_INT_MASK (0x20U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD52_RD_ERR_INT_SHIFT (5U)
+/*! CMD52_RD_ERR_INT - This event is set if host issues cmd52 read access to off-domain register during sleep mode. */
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD52_RD_ERR_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_CMD52_RD_ERR_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_CMD52_RD_ERR_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD53_WR_ERR_INT_MASK (0x40U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD53_WR_ERR_INT_SHIFT (6U)
+/*! CMD53_WR_ERR_INT - This event is set if host issues cmd53 write access to off-domain register during sleep mode. */
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD53_WR_ERR_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_CMD53_WR_ERR_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_CMD53_WR_ERR_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD53_RD_ERR_INT_MASK (0x80U)
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD53_RD_ERR_INT_SHIFT (7U)
+/*! CMD53_RD_ERR_INT - This event is set if host issues cmd53 read access to off-domain register during sleep mode. */
+#define SDU_FN_CARD_CARD_INTSTATUS1_CMD53_RD_ERR_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS1_CMD53_RD_ERR_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS1_CMD53_RD_ERR_INT_MASK)
+/*! @} */
+
+/*! @name CARD_INTSTATUS2 - Card Interrupt Status 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q1_DNLD_CARD_INT_MASK (0x1U)
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q1_DNLD_CARD_INT_SHIFT (0U)
+/*! Q1_DNLD_CARD_INT - Queue 1 DnldCardInt event when (IO_Write) && DMA_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q1_DNLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS2_Q1_DNLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS2_Q1_DNLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q2_DNLD_CARD_INT_MASK (0x2U)
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q2_DNLD_CARD_INT_SHIFT (1U)
+/*! Q2_DNLD_CARD_INT - Queue 2 DnldCardInt event when (IO_Write) && DMA_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q2_DNLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS2_Q2_DNLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS2_Q2_DNLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q3_DNLD_CARD_INT_MASK (0x4U)
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q3_DNLD_CARD_INT_SHIFT (2U)
+/*! Q3_DNLD_CARD_INT - Queue 3 DnldCardInt event when (IO_Write) && DMA_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q3_DNLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS2_Q3_DNLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS2_Q3_DNLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q1_UPLD_CARD_INT_MASK (0x8U)
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q1_UPLD_CARD_INT_SHIFT (3U)
+/*! Q1_UPLD_CARD_INT - Queue 1 UpldCardInt event when (IO_Ready) && SD_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q1_UPLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS2_Q1_UPLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS2_Q1_UPLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q2_UPLD_CARD_INT_MASK (0x10U)
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q2_UPLD_CARD_INT_SHIFT (4U)
+/*! Q2_UPLD_CARD_INT - Queue 2 UpldCardInt event when (IO_Ready) && SD_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q2_UPLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS2_Q2_UPLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS2_Q2_UPLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q3_UPLD_CARD_INT_MASK (0x20U)
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q3_UPLD_CARD_INT_SHIFT (5U)
+/*! Q3_UPLD_CARD_INT - Queue 3 UpldCardInt event when (IO_Ready) && SD_Finish. */
+#define SDU_FN_CARD_CARD_INTSTATUS2_Q3_UPLD_CARD_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS2_Q3_UPLD_CARD_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS2_Q3_UPLD_CARD_INT_MASK)
+
+#define SDU_FN_CARD_CARD_INTSTATUS2_HOST_RST_INT_MASK (0x40U)
+#define SDU_FN_CARD_CARD_INTSTATUS2_HOST_RST_INT_SHIFT (6U)
+/*! HOST_RST_INT - Host reset event. */
+#define SDU_FN_CARD_CARD_INTSTATUS2_HOST_RST_INT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTSTATUS2_HOST_RST_INT_SHIFT)) & SDU_FN_CARD_CARD_INTSTATUS2_HOST_RST_INT_MASK)
+/*! @} */
+
+/*! @name CARD_INTRSR0 - Card Interrupt Reset Select 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTRSR0_CARD_INT_RSR0_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INTRSR0_CARD_INT_RSR0_SHIFT (0U)
+/*! CARD_INT_RSR0 - Card Interrupt Reset Select[7:0] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read */
+#define SDU_FN_CARD_CARD_INTRSR0_CARD_INT_RSR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTRSR0_CARD_INT_RSR0_SHIFT)) & SDU_FN_CARD_CARD_INTRSR0_CARD_INT_RSR0_MASK)
+/*! @} */
+
+/*! @name CARD_INTRSR1 - Card Interrupt Reset Select 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTRSR1_CARD_INT_RSR1_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INTRSR1_CARD_INT_RSR1_SHIFT (0U)
+/*! CARD_INT_RSR1 - Card Interrupt Reset Select[15:8] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read */
+#define SDU_FN_CARD_CARD_INTRSR1_CARD_INT_RSR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTRSR1_CARD_INT_RSR1_SHIFT)) & SDU_FN_CARD_CARD_INTRSR1_CARD_INT_RSR1_MASK)
+/*! @} */
+
+/*! @name CARD_INTRSR2 - Card Interrupt Reset Select 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INTRSR2_CARD_INT_RSR2_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INTRSR2_CARD_INT_RSR2_SHIFT (0U)
+/*! CARD_INT_RSR2 - Card Interrupt Reset Select[23:16] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read */
+#define SDU_FN_CARD_CARD_INTRSR2_CARD_INT_RSR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INTRSR2_CARD_INT_RSR2_SHIFT)) & SDU_FN_CARD_CARD_INTRSR2_CARD_INT_RSR2_MASK)
+/*! @} */
+
+/*! @name RD_BASE0 - SQ Read Base Address 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_RD_BASE0_SQ_READ_ADDR0_MASK  (0xFFU)
+#define SDU_FN_CARD_RD_BASE0_SQ_READ_ADDR0_SHIFT (0U)
+/*! SQ_READ_ADDR0 - SQ read base address bit [7:0]. */
+#define SDU_FN_CARD_RD_BASE0_SQ_READ_ADDR0(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_RD_BASE0_SQ_READ_ADDR0_SHIFT)) & SDU_FN_CARD_RD_BASE0_SQ_READ_ADDR0_MASK)
+/*! @} */
+
+/*! @name RD_BASE1 - SQ Read Base Address 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_RD_BASE1_SQ_READ_ADDR1_MASK  (0xFFU)
+#define SDU_FN_CARD_RD_BASE1_SQ_READ_ADDR1_SHIFT (0U)
+/*! SQ_READ_ADDR1 - SQ read base address bit [15:8] */
+#define SDU_FN_CARD_RD_BASE1_SQ_READ_ADDR1(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_RD_BASE1_SQ_READ_ADDR1_SHIFT)) & SDU_FN_CARD_RD_BASE1_SQ_READ_ADDR1_MASK)
+/*! @} */
+
+/*! @name RD_BASE2 - SQ Read Base Address 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_RD_BASE2_SQ_READ_ADDR2_MASK  (0xFFU)
+#define SDU_FN_CARD_RD_BASE2_SQ_READ_ADDR2_SHIFT (0U)
+/*! SQ_READ_ADDR2 - SQ read base address bit [23:16] */
+#define SDU_FN_CARD_RD_BASE2_SQ_READ_ADDR2(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_RD_BASE2_SQ_READ_ADDR2_SHIFT)) & SDU_FN_CARD_RD_BASE2_SQ_READ_ADDR2_MASK)
+/*! @} */
+
+/*! @name RD_BASE3 - SQ Read Base Address 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_RD_BASE3_SQ_READ_ADDR3_MASK  (0xFFU)
+#define SDU_FN_CARD_RD_BASE3_SQ_READ_ADDR3_SHIFT (0U)
+/*! SQ_READ_ADDR3 - SQ read base address bit [31:24] */
+#define SDU_FN_CARD_RD_BASE3_SQ_READ_ADDR3(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_RD_BASE3_SQ_READ_ADDR3_SHIFT)) & SDU_FN_CARD_RD_BASE3_SQ_READ_ADDR3_MASK)
+/*! @} */
+
+/*! @name WR_BASE0 - SQ Write Base Address 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_WR_BASE0_SQ_WRITE_ADDR0_MASK (0xFFU)
+#define SDU_FN_CARD_WR_BASE0_SQ_WRITE_ADDR0_SHIFT (0U)
+/*! SQ_WRITE_ADDR0 - SQ Write base address bit [7:0]. */
+#define SDU_FN_CARD_WR_BASE0_SQ_WRITE_ADDR0(x)   (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_WR_BASE0_SQ_WRITE_ADDR0_SHIFT)) & SDU_FN_CARD_WR_BASE0_SQ_WRITE_ADDR0_MASK)
+/*! @} */
+
+/*! @name WR_BASE1 - SQ Write Base Address 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_WR_BASE1_SQ_WRITE_ADDR1_MASK (0xFFU)
+#define SDU_FN_CARD_WR_BASE1_SQ_WRITE_ADDR1_SHIFT (0U)
+/*! SQ_WRITE_ADDR1 - SQ Write base address bit [15:8] */
+#define SDU_FN_CARD_WR_BASE1_SQ_WRITE_ADDR1(x)   (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_WR_BASE1_SQ_WRITE_ADDR1_SHIFT)) & SDU_FN_CARD_WR_BASE1_SQ_WRITE_ADDR1_MASK)
+/*! @} */
+
+/*! @name WR_BASE2 - SQ Write Base Address 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_WR_BASE2_SQ_WRITE_ADDR2_MASK (0xFFU)
+#define SDU_FN_CARD_WR_BASE2_SQ_WRITE_ADDR2_SHIFT (0U)
+/*! SQ_WRITE_ADDR2 - SQ Write base address bit [23:16] */
+#define SDU_FN_CARD_WR_BASE2_SQ_WRITE_ADDR2(x)   (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_WR_BASE2_SQ_WRITE_ADDR2_SHIFT)) & SDU_FN_CARD_WR_BASE2_SQ_WRITE_ADDR2_MASK)
+/*! @} */
+
+/*! @name WR_BASE3 - SQ Write Base Address 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_WR_BASE3_SQ_WRITE_ADDR3_MASK (0xFFU)
+#define SDU_FN_CARD_WR_BASE3_SQ_WRITE_ADDR3_SHIFT (0U)
+/*! SQ_WRITE_ADDR3 - SQ Write base address bit [31:24] */
+#define SDU_FN_CARD_WR_BASE3_SQ_WRITE_ADDR3(x)   (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_WR_BASE3_SQ_WRITE_ADDR3_SHIFT)) & SDU_FN_CARD_WR_BASE3_SQ_WRITE_ADDR3_MASK)
+/*! @} */
+
+/*! @name RD_IDX - Read Base Address Index */
+/*! @{ */
+
+#define SDU_FN_CARD_RD_IDX_RD_INDEX_MASK         (0x1FU)
+#define SDU_FN_CARD_RD_IDX_RD_INDEX_SHIFT        (0U)
+/*! RD_INDEX - Index to current read base address [15:0] */
+#define SDU_FN_CARD_RD_IDX_RD_INDEX(x)           (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_RD_IDX_RD_INDEX_SHIFT)) & SDU_FN_CARD_RD_IDX_RD_INDEX_MASK)
+/*! @} */
+
+/*! @name WR_IDX - Write Base Address Index */
+/*! @{ */
+
+#define SDU_FN_CARD_WR_IDX_WR_INDEX_MASK         (0x1FU)
+#define SDU_FN_CARD_WR_IDX_WR_INDEX_SHIFT        (0U)
+/*! WR_INDEX - Index to current write base address [15:0] */
+#define SDU_FN_CARD_WR_IDX_WR_INDEX(x)           (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_WR_IDX_WR_INDEX_SHIFT)) & SDU_FN_CARD_WR_IDX_WR_INDEX_MASK)
+/*! @} */
+
+/*! @name APU_SLP_RDY_EN - APU Sleep Ready Enable */
+/*! @{ */
+
+#define SDU_FN_CARD_APU_SLP_RDY_EN_APU_SLP_RDY_EN_MASK (0x1U)
+#define SDU_FN_CARD_APU_SLP_RDY_EN_APU_SLP_RDY_EN_SHIFT (0U)
+/*! APU_SLP_RDY_EN - APU Sleep Ready Enable If this bit is enabled, any pending host interrupt
+ *    status will deassert sdu_apu_slp_rdy to prevent APU from going into sleep mode.
+ */
+#define SDU_FN_CARD_APU_SLP_RDY_EN_APU_SLP_RDY_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_APU_SLP_RDY_EN_APU_SLP_RDY_EN_SHIFT)) & SDU_FN_CARD_APU_SLP_RDY_EN_APU_SLP_RDY_EN_MASK)
+/*! @} */
+
+/*! @name HOST_ERR_WKUP_EN - Host Error Wakeup Enable */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_WR_ERR_WKUP_EN_MASK (0x1U)
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_WR_ERR_WKUP_EN_SHIFT (0U)
+/*! CMD52_WR_ERR_WKUP_EN - CMD52 Write Error Wakeup Enable If host issues CMD52 write access to any
+ *    off-domain register during sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_WR_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_WR_ERR_WKUP_EN_SHIFT)) & SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_WR_ERR_WKUP_EN_MASK)
+
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_RD_ERR_WKUP_EN_MASK (0x2U)
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_RD_ERR_WKUP_EN_SHIFT (1U)
+/*! CMD52_RD_ERR_WKUP_EN - CMD52 Read Error Wakeup Enable If host issues CMD52 read access to any
+ *    off-domain register during sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_RD_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_RD_ERR_WKUP_EN_SHIFT)) & SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD52_RD_ERR_WKUP_EN_MASK)
+
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_WR_ERR_WKUP_EN_MASK (0x4U)
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_WR_ERR_WKUP_EN_SHIFT (2U)
+/*! CMD53_WR_ERR_WKUP_EN - CMD53 Write Error Wakeup Enable If host issues CMD53 write access during
+ *    sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_WR_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_WR_ERR_WKUP_EN_SHIFT)) & SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_WR_ERR_WKUP_EN_MASK)
+
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_RD_ERR_WKUP_EN_MASK (0x8U)
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_RD_ERR_WKUP_EN_SHIFT (3U)
+/*! CMD53_RD_ERR_WKUP_EN - CMD53 Read Error Wakeup Enable If host issues CMD53 read access during
+ *    sleep mode, setting this bit will trigger wakeup event to the APU.
+ */
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_RD_ERR_WKUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_RD_ERR_WKUP_EN_SHIFT)) & SDU_FN_CARD_HOST_ERR_WKUP_EN_CMD53_RD_ERR_WKUP_EN_MASK)
+
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_TESTBUS_BIT_SEL_EN_MASK (0x30U)
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_TESTBUS_BIT_SEL_EN_SHIFT (4U)
+/*! TESTBUS_BIT_SEL_EN - If bit 0 is 1, testbus_lo bits are individually selected by TESTBUS_BIT_SEL0 and TESTBUS_BIT_SEL1. */
+#define SDU_FN_CARD_HOST_ERR_WKUP_EN_TESTBUS_BIT_SEL_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_WKUP_EN_TESTBUS_BIT_SEL_EN_SHIFT)) & SDU_FN_CARD_HOST_ERR_WKUP_EN_TESTBUS_BIT_SEL_EN_MASK)
+/*! @} */
+
+/*! @name HOST_ERR_CMD0 - Host Error Command 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_ERR_CMD0_HOST_ERR_CMD0_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_ERR_CMD0_HOST_ERR_CMD0_SHIFT (0U)
+/*! HOST_ERR_CMD0 - Host Error Command[7:0] Capture 48-bit content of either CMD52 or CMD53
+ *    depending on one of the four error conditions in CARD_INTSTATUS1[7:4].
+ */
+#define SDU_FN_CARD_HOST_ERR_CMD0_HOST_ERR_CMD0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_CMD0_HOST_ERR_CMD0_SHIFT)) & SDU_FN_CARD_HOST_ERR_CMD0_HOST_ERR_CMD0_MASK)
+/*! @} */
+
+/*! @name HOST_ERR_CMD1 - Host Error Command 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_ERR_CMD1_HOST_ERR_CMD1_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_ERR_CMD1_HOST_ERR_CMD1_SHIFT (0U)
+/*! HOST_ERR_CMD1 - Host Error Command[15:8] Capture 48-bit content of either CMD52 or CMD53
+ *    depending on one of the four error conditions in CARD_INTSTATUS1[7:4].
+ */
+#define SDU_FN_CARD_HOST_ERR_CMD1_HOST_ERR_CMD1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_CMD1_HOST_ERR_CMD1_SHIFT)) & SDU_FN_CARD_HOST_ERR_CMD1_HOST_ERR_CMD1_MASK)
+/*! @} */
+
+/*! @name HOST_ERR_CMD2 - Host Error Command 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_ERR_CMD2_HOST_ERR_CMD2_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_ERR_CMD2_HOST_ERR_CMD2_SHIFT (0U)
+/*! HOST_ERR_CMD2 - Host Error Command[23:16] Capture 48-bit content of either CMD52 or CMD53
+ *    depending on one of the four error conditions in CARD_INTSTATUS1[7:4].
+ */
+#define SDU_FN_CARD_HOST_ERR_CMD2_HOST_ERR_CMD2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_CMD2_HOST_ERR_CMD2_SHIFT)) & SDU_FN_CARD_HOST_ERR_CMD2_HOST_ERR_CMD2_MASK)
+/*! @} */
+
+/*! @name HOST_ERR_CMD3 - Host Error Command 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_ERR_CMD3_HOST_ERR_CMD3_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_ERR_CMD3_HOST_ERR_CMD3_SHIFT (0U)
+/*! HOST_ERR_CMD3 - Host Error Command[31:24] Capture 48-bit content of either CMD52 or CMD53
+ *    depending on one of the four error conditions in CARD_INTSTATUS1[7:4].
+ */
+#define SDU_FN_CARD_HOST_ERR_CMD3_HOST_ERR_CMD3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_CMD3_HOST_ERR_CMD3_SHIFT)) & SDU_FN_CARD_HOST_ERR_CMD3_HOST_ERR_CMD3_MASK)
+/*! @} */
+
+/*! @name HOST_ERR_CMD4 - Host Error Command 4 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_ERR_CMD4_HOST_ERR_CMD4_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_ERR_CMD4_HOST_ERR_CMD4_SHIFT (0U)
+/*! HOST_ERR_CMD4 - Host Error Command[39:32] Capture 48-bit content of either CMD52 or CMD53
+ *    depending on one of the four error conditions in CARD_INTSTATUS1[7:4].
+ */
+#define SDU_FN_CARD_HOST_ERR_CMD4_HOST_ERR_CMD4(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_CMD4_HOST_ERR_CMD4_SHIFT)) & SDU_FN_CARD_HOST_ERR_CMD4_HOST_ERR_CMD4_MASK)
+/*! @} */
+
+/*! @name HOST_ERR_CMD5 - Host Error Command 5 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_ERR_CMD5_HOST_ERR_CMD5_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_ERR_CMD5_HOST_ERR_CMD5_SHIFT (0U)
+/*! HOST_ERR_CMD5 - Host Error Command[47:40] Capture 48-bit content of either CMD52 or CMD53
+ *    depending on one of the four error conditions in CARD_INTSTATUS1[7:4].
+ */
+#define SDU_FN_CARD_HOST_ERR_CMD5_HOST_ERR_CMD5(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_ERR_CMD5_HOST_ERR_CMD5_SHIFT)) & SDU_FN_CARD_HOST_ERR_CMD5_HOST_ERR_CMD5_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP_CLR0 - Packet Write Bitmap Clear 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR0_PKT_WR_BITMAP_SW_CLR0_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR0_PKT_WR_BITMAP_SW_CLR0_SHIFT (0U)
+/*! PKT_WR_BITMAP_SW_CLR0 - Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit. */
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR0_PKT_WR_BITMAP_SW_CLR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP_CLR0_PKT_WR_BITMAP_SW_CLR0_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP_CLR0_PKT_WR_BITMAP_SW_CLR0_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP_CLR1 - Packet Write Bitmap Clear 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR1_PKT_WR_BITMAP_SW_CLR1_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR1_PKT_WR_BITMAP_SW_CLR1_SHIFT (0U)
+/*! PKT_WR_BITMAP_SW_CLR1 - Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit. */
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR1_PKT_WR_BITMAP_SW_CLR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP_CLR1_PKT_WR_BITMAP_SW_CLR1_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP_CLR1_PKT_WR_BITMAP_SW_CLR1_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP_CLR2 - Packet Write Bitmap Clear 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR2_PKT_WR_BITMAP_SW_CLR2_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR2_PKT_WR_BITMAP_SW_CLR2_SHIFT (0U)
+/*! PKT_WR_BITMAP_SW_CLR2 - Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit. */
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR2_PKT_WR_BITMAP_SW_CLR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP_CLR2_PKT_WR_BITMAP_SW_CLR2_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP_CLR2_PKT_WR_BITMAP_SW_CLR2_MASK)
+/*! @} */
+
+/*! @name PKT_WR_BITMAP_CLR3 - Packet Write Bitmap Clear 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR3_PKT_WR_BITMAP_SW_CLR3_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR3_PKT_WR_BITMAP_SW_CLR3_SHIFT (0U)
+/*! PKT_WR_BITMAP_SW_CLR3 - Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit. */
+#define SDU_FN_CARD_PKT_WR_BITMAP_CLR3_PKT_WR_BITMAP_SW_CLR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_WR_BITMAP_CLR3_PKT_WR_BITMAP_SW_CLR3_SHIFT)) & SDU_FN_CARD_PKT_WR_BITMAP_CLR3_PKT_WR_BITMAP_SW_CLR3_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP_CLR0 - Packet Read Bitmap Clear 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR0_PKT_RD_BITMAP_SW_CLR0_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR0_PKT_RD_BITMAP_SW_CLR0_SHIFT (0U)
+/*! PKT_RD_BITMAP_SW_CLR0 - Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit. */
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR0_PKT_RD_BITMAP_SW_CLR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP_CLR0_PKT_RD_BITMAP_SW_CLR0_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP_CLR0_PKT_RD_BITMAP_SW_CLR0_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP_CLR1 - Packet Read Bitmap Clear 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR1_PKT_RD_BITMAP_SW_CLR1_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR1_PKT_RD_BITMAP_SW_CLR1_SHIFT (0U)
+/*! PKT_RD_BITMAP_SW_CLR1 - Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit. */
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR1_PKT_RD_BITMAP_SW_CLR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP_CLR1_PKT_RD_BITMAP_SW_CLR1_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP_CLR1_PKT_RD_BITMAP_SW_CLR1_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP_CLR2 - Packet Read Bitmap Clear 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR2_PKT_RD_BITMAP_SW_CLR2_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR2_PKT_RD_BITMAP_SW_CLR2_SHIFT (0U)
+/*! PKT_RD_BITMAP_SW_CLR2 - Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit. */
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR2_PKT_RD_BITMAP_SW_CLR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP_CLR2_PKT_RD_BITMAP_SW_CLR2_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP_CLR2_PKT_RD_BITMAP_SW_CLR2_MASK)
+/*! @} */
+
+/*! @name PKT_RD_BITMAP_CLR3 - Packet Read Bitmap Clear 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR3_PKT_RD_BITMAP_SW_CLR3_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR3_PKT_RD_BITMAP_SW_CLR3_SHIFT (0U)
+/*! PKT_RD_BITMAP_SW_CLR3 - Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit. */
+#define SDU_FN_CARD_PKT_RD_BITMAP_CLR3_PKT_RD_BITMAP_SW_CLR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_RD_BITMAP_CLR3_PKT_RD_BITMAP_SW_CLR3_SHIFT)) & SDU_FN_CARD_PKT_RD_BITMAP_CLR3_PKT_RD_BITMAP_SW_CLR3_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_EN0 - Host Interrupt Active Mask Enable 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN0_HOST_INT_ACT_MASK_EN0_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN0_HOST_INT_ACT_MASK_EN0_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_EN0 - Enable host interrupt controller active mask [7:0] */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN0_HOST_INT_ACT_MASK_EN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_EN0_HOST_INT_ACT_MASK_EN0_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_EN0_HOST_INT_ACT_MASK_EN0_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_EN1 - Host Interrupt Active Mask Enable 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN1_HOST_INT_ACT_MASK_EN1_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN1_HOST_INT_ACT_MASK_EN1_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_EN1 - Enable host interrupt controller active mask [15:8] */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN1_HOST_INT_ACT_MASK_EN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_EN1_HOST_INT_ACT_MASK_EN1_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_EN1_HOST_INT_ACT_MASK_EN1_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_EN2 - Host Interrupt Active Mask Enable 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN2_HOST_INT_ACT_MASK_EN2_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN2_HOST_INT_ACT_MASK_EN2_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_EN2 - Enable host interrupt controller active mask [23:16] */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN2_HOST_INT_ACT_MASK_EN2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_EN2_HOST_INT_ACT_MASK_EN2_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_EN2_HOST_INT_ACT_MASK_EN2_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_EN3 - Host Interrupt Active Mask Enable 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN3_HOST_INT_ACT_MASK_EN3_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN3_HOST_INT_ACT_MASK_EN3_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_EN3 - Enable host interrupt controller active mask [31:24] */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_EN3_HOST_INT_ACT_MASK_EN3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_EN3_HOST_INT_ACT_MASK_EN3_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_EN3_HOST_INT_ACT_MASK_EN3_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_CLR0 - Host Interrupt Active Mask Clear 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR0_HOST_INT_ACT_MASK_CLR0_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR0_HOST_INT_ACT_MASK_CLR0_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_CLR0 - Host interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding host interrupt active mask bit.
+ */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR0_HOST_INT_ACT_MASK_CLR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_CLR0_HOST_INT_ACT_MASK_CLR0_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_CLR0_HOST_INT_ACT_MASK_CLR0_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_CLR1 - Host Interrupt Active Mask Clear 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR1_HOST_INT_ACT_MASK_CLR1_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR1_HOST_INT_ACT_MASK_CLR1_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_CLR1 - Host interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding host interrupt active mask bit.
+ */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR1_HOST_INT_ACT_MASK_CLR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_CLR1_HOST_INT_ACT_MASK_CLR1_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_CLR1_HOST_INT_ACT_MASK_CLR1_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_CLR2 - Host Interrupt Active Mask Clear 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR2_HOST_INT_ACT_MASK_CLR2_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR2_HOST_INT_ACT_MASK_CLR2_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_CLR2 - Host interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding host interrupt active mask bit.
+ */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR2_HOST_INT_ACT_MASK_CLR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_CLR2_HOST_INT_ACT_MASK_CLR2_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_CLR2_HOST_INT_ACT_MASK_CLR2_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_CLR3 - Host Interrupt Active Mask Clear 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR3_HOST_INT_ACT_MASK_CLR3_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR3_HOST_INT_ACT_MASK_CLR3_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_CLR3 - Host interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding host interrupt active mask bit.
+ */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_CLR3_HOST_INT_ACT_MASK_CLR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_CLR3_HOST_INT_ACT_MASK_CLR3_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_CLR3_HOST_INT_ACT_MASK_CLR3_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_STATUS0 - Host Interrupt Active Mask Status 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS0_HOST_INT_ACT_MASK_STATUS0_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS0_HOST_INT_ACT_MASK_STATUS0_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_STATUS0 - Host interrupt active mask status */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS0_HOST_INT_ACT_MASK_STATUS0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS0_HOST_INT_ACT_MASK_STATUS0_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS0_HOST_INT_ACT_MASK_STATUS0_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_STATUS1 - Host Interrupt Active Mask Status 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS1_HOST_INT_ACT_MASK_STATUS1_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS1_HOST_INT_ACT_MASK_STATUS1_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_STATUS1 - Host interrupt active mask status */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS1_HOST_INT_ACT_MASK_STATUS1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS1_HOST_INT_ACT_MASK_STATUS1_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS1_HOST_INT_ACT_MASK_STATUS1_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_STATUS2 - Host Interrupt Active Mask Status 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS2_HOST_INT_ACT_MASK_STATUS2_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS2_HOST_INT_ACT_MASK_STATUS2_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_STATUS2 - Host interrupt active mask status */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS2_HOST_INT_ACT_MASK_STATUS2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS2_HOST_INT_ACT_MASK_STATUS2_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS2_HOST_INT_ACT_MASK_STATUS2_MASK)
+/*! @} */
+
+/*! @name HOST_INT_ACT_MASK_STATUS3 - Host Interrupt Active Mask Status 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS3_HOST_INT_ACT_MASK_STATUS3_MASK (0xFFU)
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS3_HOST_INT_ACT_MASK_STATUS3_SHIFT (0U)
+/*! HOST_INT_ACT_MASK_STATUS3 - Host interrupt active mask status */
+#define SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS3_HOST_INT_ACT_MASK_STATUS3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS3_HOST_INT_ACT_MASK_STATUS3_SHIFT)) & SDU_FN_CARD_HOST_INT_ACT_MASK_STATUS3_HOST_INT_ACT_MASK_STATUS3_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_EN0 - Card Interrupt Active Mask Enable 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN0_CARD_INT_ACT_MASK_EN0_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN0_CARD_INT_ACT_MASK_EN0_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_EN0 - Enable card interrupt controller active mask [7:0] */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN0_CARD_INT_ACT_MASK_EN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_EN0_CARD_INT_ACT_MASK_EN0_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_EN0_CARD_INT_ACT_MASK_EN0_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_EN1 - Card Interrupt Active Mask Enable 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN1_CARD_INT_ACT_MASK_EN1_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN1_CARD_INT_ACT_MASK_EN1_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_EN1 - Enable card interrupt controller active mask [15:8] */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN1_CARD_INT_ACT_MASK_EN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_EN1_CARD_INT_ACT_MASK_EN1_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_EN1_CARD_INT_ACT_MASK_EN1_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_EN2 - Card Interrupt Active Mask Enable 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN2_CARD_INT_ACT_MASK_EN2_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN2_CARD_INT_ACT_MASK_EN2_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_EN2 - Enable card interrupt controller active mask [23:16] */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN2_CARD_INT_ACT_MASK_EN2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_EN2_CARD_INT_ACT_MASK_EN2_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_EN2_CARD_INT_ACT_MASK_EN2_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_EN3 - Card Interrupt Active Mask Enable 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN3_CARD_INT_ACT_MASK_EN3_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN3_CARD_INT_ACT_MASK_EN3_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_EN3 - Enable card interrupt controller active mask [31:24] */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_EN3_CARD_INT_ACT_MASK_EN3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_EN3_CARD_INT_ACT_MASK_EN3_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_EN3_CARD_INT_ACT_MASK_EN3_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_CLR0 - Card Interrupt Active Mask Clear 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR0_CARD_INT_ACT_MASK_CLR0_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR0_CARD_INT_ACT_MASK_CLR0_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_CLR0 - Card interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding card interrupt active mask bit.
+ */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR0_CARD_INT_ACT_MASK_CLR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_CLR0_CARD_INT_ACT_MASK_CLR0_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_CLR0_CARD_INT_ACT_MASK_CLR0_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_CLR1 - Card Interrupt Active Mask Clear 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR1_CARD_INT_ACT_MASK_CLR1_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR1_CARD_INT_ACT_MASK_CLR1_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_CLR1 - Card interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding card interrupt active mask bit.
+ */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR1_CARD_INT_ACT_MASK_CLR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_CLR1_CARD_INT_ACT_MASK_CLR1_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_CLR1_CARD_INT_ACT_MASK_CLR1_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_CLR2 - Card Interrupt Active Mask Clear 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR2_CARD_INT_ACT_MASK_CLR2_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR2_CARD_INT_ACT_MASK_CLR2_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_CLR2 - Card interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding card interrupt active mask bit.
+ */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR2_CARD_INT_ACT_MASK_CLR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_CLR2_CARD_INT_ACT_MASK_CLR2_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_CLR2_CARD_INT_ACT_MASK_CLR2_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_CLR3 - Card Interrupt Active Mask Clear 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR3_CARD_INT_ACT_MASK_CLR3_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR3_CARD_INT_ACT_MASK_CLR3_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_CLR3 - Card interrupt active mask write-1-to-clear Setting 1 to each bit will
+ *    clear the corresponding card interrupt active mask bit.
+ */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_CLR3_CARD_INT_ACT_MASK_CLR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_CLR3_CARD_INT_ACT_MASK_CLR3_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_CLR3_CARD_INT_ACT_MASK_CLR3_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_STATUS0 - Card Interrupt Active Mask Status 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS0_CARD_INT_ACT_MASK_STATUS0_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS0_CARD_INT_ACT_MASK_STATUS0_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_STATUS0 - Card interrupt active mask status */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS0_CARD_INT_ACT_MASK_STATUS0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS0_CARD_INT_ACT_MASK_STATUS0_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS0_CARD_INT_ACT_MASK_STATUS0_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_STATUS1 - Card Interrupt Active Mask Status 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS1_CARD_INT_ACT_MASK_STATUS1_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS1_CARD_INT_ACT_MASK_STATUS1_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_STATUS1 - Card interrupt active mask status */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS1_CARD_INT_ACT_MASK_STATUS1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS1_CARD_INT_ACT_MASK_STATUS1_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS1_CARD_INT_ACT_MASK_STATUS1_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_STATUS2 - Card Interrupt Active Mask Status 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS2_CARD_INT_ACT_MASK_STATUS2_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS2_CARD_INT_ACT_MASK_STATUS2_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_STATUS2 - Card interrupt active mask status */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS2_CARD_INT_ACT_MASK_STATUS2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS2_CARD_INT_ACT_MASK_STATUS2_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS2_CARD_INT_ACT_MASK_STATUS2_MASK)
+/*! @} */
+
+/*! @name CARD_INT_ACT_MASK_STATUS3 - Card Interrupt Active Mask Status 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS3_CARD_INT_ACT_MASK_STATUS3_MASK (0xFFU)
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS3_CARD_INT_ACT_MASK_STATUS3_SHIFT (0U)
+/*! CARD_INT_ACT_MASK_STATUS3 - Card interrupt active mask status */
+#define SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS3_CARD_INT_ACT_MASK_STATUS3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS3_CARD_INT_ACT_MASK_STATUS3_SHIFT)) & SDU_FN_CARD_CARD_INT_ACT_MASK_STATUS3_CARD_INT_ACT_MASK_STATUS3_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_WR_BASE_0 - Command Port SQ Write Base Address 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_0_CMD_SQ_WRITE_ADDR0_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_0_CMD_SQ_WRITE_ADDR0_SHIFT (0U)
+/*! CMD_SQ_WRITE_ADDR0 - Command Port SQ Write base address bit [7:0]. */
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_0_CMD_SQ_WRITE_ADDR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_WR_BASE_0_CMD_SQ_WRITE_ADDR0_SHIFT)) & SDU_FN_CARD_CMD_PORT_WR_BASE_0_CMD_SQ_WRITE_ADDR0_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_WR_BASE_1 - Command Port SQ Write Base Address 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_1_CMD_SQ_WRITE_ADDR1_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_1_CMD_SQ_WRITE_ADDR1_SHIFT (0U)
+/*! CMD_SQ_WRITE_ADDR1 - Command Port SQ Write base address bit [15:8]. */
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_1_CMD_SQ_WRITE_ADDR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_WR_BASE_1_CMD_SQ_WRITE_ADDR1_SHIFT)) & SDU_FN_CARD_CMD_PORT_WR_BASE_1_CMD_SQ_WRITE_ADDR1_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_WR_BASE_2 - Command Port SQ Write Base Address 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_2_CMD_SQ_WRITE_ADDR2_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_2_CMD_SQ_WRITE_ADDR2_SHIFT (0U)
+/*! CMD_SQ_WRITE_ADDR2 - Command Port SQ Write base address bit [23:16]. */
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_2_CMD_SQ_WRITE_ADDR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_WR_BASE_2_CMD_SQ_WRITE_ADDR2_SHIFT)) & SDU_FN_CARD_CMD_PORT_WR_BASE_2_CMD_SQ_WRITE_ADDR2_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_WR_BASE_3 - Command Port SQ Write Base Address 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_3_CMD_SQ_WRITE_ADDR3_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_3_CMD_SQ_WRITE_ADDR3_SHIFT (0U)
+/*! CMD_SQ_WRITE_ADDR3 - Command Port SQ Write base address bit [31:24]. */
+#define SDU_FN_CARD_CMD_PORT_WR_BASE_3_CMD_SQ_WRITE_ADDR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_WR_BASE_3_CMD_SQ_WRITE_ADDR3_SHIFT)) & SDU_FN_CARD_CMD_PORT_WR_BASE_3_CMD_SQ_WRITE_ADDR3_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_RD_BASE_0 - Command Port SQ Read Base Address 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_0_CMD_SQ_READ_ADDR0_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_0_CMD_SQ_READ_ADDR0_SHIFT (0U)
+/*! CMD_SQ_READ_ADDR0 - Command Port SQ Read base address bit [7:0]. */
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_0_CMD_SQ_READ_ADDR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_RD_BASE_0_CMD_SQ_READ_ADDR0_SHIFT)) & SDU_FN_CARD_CMD_PORT_RD_BASE_0_CMD_SQ_READ_ADDR0_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_RD_BASE_1 - Command Port SQ Read Base Address 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_1_CMD_SQ_READ_ADDR1_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_1_CMD_SQ_READ_ADDR1_SHIFT (0U)
+/*! CMD_SQ_READ_ADDR1 - Command Port SQ Read base address bit [15:8]. */
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_1_CMD_SQ_READ_ADDR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_RD_BASE_1_CMD_SQ_READ_ADDR1_SHIFT)) & SDU_FN_CARD_CMD_PORT_RD_BASE_1_CMD_SQ_READ_ADDR1_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_RD_BASE_2 - Command Port SQ Read Base Address 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_2_CMD_SQ_READ_ADDR2_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_2_CMD_SQ_READ_ADDR2_SHIFT (0U)
+/*! CMD_SQ_READ_ADDR2 - Command Port SQ Read base address bit [23:16]. */
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_2_CMD_SQ_READ_ADDR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_RD_BASE_2_CMD_SQ_READ_ADDR2_SHIFT)) & SDU_FN_CARD_CMD_PORT_RD_BASE_2_CMD_SQ_READ_ADDR2_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_RD_BASE_3 - Command Port SQ Read Base Address 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_3_CMD_SQ_READ_ADDR3_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_3_CMD_SQ_READ_ADDR3_SHIFT (0U)
+/*! CMD_SQ_READ_ADDR3 - Command Port SQ Read base address bit [31:24]. */
+#define SDU_FN_CARD_CMD_PORT_RD_BASE_3_CMD_SQ_READ_ADDR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_RD_BASE_3_CMD_SQ_READ_ADDR3_SHIFT)) & SDU_FN_CARD_CMD_PORT_RD_BASE_3_CMD_SQ_READ_ADDR3_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_RD_LEN_0 - Command Port Read Length 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_RD_LEN_0_CMD_PORT_RD_LEN0_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_RD_LEN_0_CMD_PORT_RD_LEN0_SHIFT (0U)
+/*! CMD_PORT_RD_LEN0 - Command Port Read Length [7:0] */
+#define SDU_FN_CARD_CMD_PORT_RD_LEN_0_CMD_PORT_RD_LEN0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_RD_LEN_0_CMD_PORT_RD_LEN0_SHIFT)) & SDU_FN_CARD_CMD_PORT_RD_LEN_0_CMD_PORT_RD_LEN0_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_RD_LEN_1 - Command Port Read Length 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_RD_LEN_1_CMD_PORT_RD_LEN1_MASK (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_RD_LEN_1_CMD_PORT_RD_LEN1_SHIFT (0U)
+/*! CMD_PORT_RD_LEN1 - Command Port Read Length [15:8] */
+#define SDU_FN_CARD_CMD_PORT_RD_LEN_1_CMD_PORT_RD_LEN1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_RD_LEN_1_CMD_PORT_RD_LEN1_SHIFT)) & SDU_FN_CARD_CMD_PORT_RD_LEN_1_CMD_PORT_RD_LEN1_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_CONFIG_0 - Command Port Config 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_TX_LEN_FORMAT_MASK (0x3U)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_TX_LEN_FORMAT_SHIFT (0U)
+/*! CMD_PORT_TX_LEN_FORMAT - Define the cmd53 command port tx length (tx_len) header format attached
+ *    in the beginning of data payload: 0 = no tx_len header info.
+ */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_TX_LEN_FORMAT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_TX_LEN_FORMAT_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_TX_LEN_FORMAT_MASK)
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_RD_LEN_EN_MASK (0x4U)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_RD_LEN_EN_SHIFT (2U)
+/*! CMD_PORT_RD_LEN_EN - cmd_port_rd_len_en */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_RD_LEN_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_RD_LEN_EN_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_RD_LEN_EN_MASK)
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_UPLD_AUTO_RESET_MASK (0x10U)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_UPLD_AUTO_RESET_SHIFT (4U)
+/*! CMD_PORT_UPLD_AUTO_RESET - Reset control for cmd_port_upld_card_rdy event in C2H_INTEVENT 0 =
+ *    upload ready event is reset to 0 after the current cmd53 is completed.
+ */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_UPLD_AUTO_RESET(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_UPLD_AUTO_RESET_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_UPLD_AUTO_RESET_MASK)
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_DNLD_AUTO_RESET_MASK (0x20U)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_DNLD_AUTO_RESET_SHIFT (5U)
+/*! CMD_PORT_DNLD_AUTO_RESET - Reset control for cmd_port_dnld_card_rdy event in C2H_INTEVENT 0 =
+ *    download ready event is reset to 0 after the current cmd53 is completed.
+ */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_DNLD_AUTO_RESET(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_DNLD_AUTO_RESET_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_0_CMD_PORT_DNLD_AUTO_RESET_MASK)
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_UPLD_OVER_MASK (0x40U)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_UPLD_OVER_SHIFT (6U)
+/*! EXPLICIT_CMD_PORT_UPLD_OVER - Explicit Upload Update 0 = bitmap update is done on completion of
+ *    CMD53 read 1 = bitmap update is done when host clears upload
+ */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_UPLD_OVER(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_UPLD_OVER_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_UPLD_OVER_MASK)
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_DNLD_OVER_MASK (0x80U)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_DNLD_OVER_SHIFT (7U)
+/*! EXPLICIT_CMD_PORT_DNLD_OVER - Explicit Download Over 0 = download over is generated on
+ *    completion of CMD53 write 1 = download over is generated when host clears download ready interrupt
+ */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_DNLD_OVER(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_DNLD_OVER_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_0_EXPLICIT_CMD_PORT_DNLD_OVER_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_CONFIG_1 - Command Port Config 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_1_CMD_PORT_AUTO_ENABLE_MASK (0x1U)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_1_CMD_PORT_AUTO_ENABLE_SHIFT (0U)
+/*! CMD_PORT_AUTO_ENABLE - If this is enabled, download and upload ready host interrupt is
+ *    automatically cleared and re-enabled after the current cmd53 is completed.
+ */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_1_CMD_PORT_AUTO_ENABLE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_1_CMD_PORT_AUTO_ENABLE_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_1_CMD_PORT_AUTO_ENABLE_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_CONFIG_2 - Command Port Config 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_2_RSVD_MASK  (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_2_RSVD_SHIFT (0U)
+/*! RSVD - Reserved */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_2_RSVD(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_2_RSVD_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_2_RSVD_MASK)
+/*! @} */
+
+/*! @name CMD_PORT_CONFIG_3 - Command Port Config 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_CMD_PORT_CONFIG_3_RSVD_MASK  (0xFFU)
+#define SDU_FN_CARD_CMD_PORT_CONFIG_3_RSVD_SHIFT (0U)
+/*! RSVD - Reserved */
+#define SDU_FN_CARD_CMD_PORT_CONFIG_3_RSVD(x)    (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CMD_PORT_CONFIG_3_RSVD_SHIFT)) & SDU_FN_CARD_CMD_PORT_CONFIG_3_RSVD_MASK)
+/*! @} */
+
+/*! @name CHIP_REV - Chip Revision */
+/*! @{ */
+
+#define SDU_FN_CARD_CHIP_REV_CHIP_REV_MASK       (0xFFU)
+#define SDU_FN_CARD_CHIP_REV_CHIP_REV_SHIFT      (0U)
+/*! CHIP_REV - Chip Revision (same as CIU) */
+#define SDU_FN_CARD_CHIP_REV_CHIP_REV(x)         (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CHIP_REV_CHIP_REV_SHIFT)) & SDU_FN_CARD_CHIP_REV_CHIP_REV_MASK)
+/*! @} */
+
+/*! @name IP_REV0 - SDU Minor IP Revision */
+/*! @{ */
+
+#define SDU_FN_CARD_IP_REV0_SDU_MINOR_IP_REV_MASK (0xFFU)
+#define SDU_FN_CARD_IP_REV0_SDU_MINOR_IP_REV_SHIFT (0U)
+/*! SDU_MINOR_IP_REV - SDU minor IP revision */
+#define SDU_FN_CARD_IP_REV0_SDU_MINOR_IP_REV(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_IP_REV0_SDU_MINOR_IP_REV_SHIFT)) & SDU_FN_CARD_IP_REV0_SDU_MINOR_IP_REV_MASK)
+/*! @} */
+
+/*! @name IP_REV1 - SDU Major IP Revision */
+/*! @{ */
+
+#define SDU_FN_CARD_IP_REV1_SDU_MAJOR_IP_REV_MASK (0xFFU)
+#define SDU_FN_CARD_IP_REV1_SDU_MAJOR_IP_REV_SHIFT (0U)
+/*! SDU_MAJOR_IP_REV - SDU major IP revision */
+#define SDU_FN_CARD_IP_REV1_SDU_MAJOR_IP_REV(x)  (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_IP_REV1_SDU_MAJOR_IP_REV_SHIFT)) & SDU_FN_CARD_IP_REV1_SDU_MAJOR_IP_REV_MASK)
+/*! @} */
+
+/*! @name PKT_END_RADDR0 - PKT_END_RADDR0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_RADDR0_PACKET_END_RADDR0_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_RADDR0_PACKET_END_RADDR0_SHIFT (0U)
+/*! PACKET_END_RADDR0 - For function 1, this is used as CMD53 DMA read packet end addr [7:0] For other functions, this is a scratch pad register */
+#define SDU_FN_CARD_PKT_END_RADDR0_PACKET_END_RADDR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_RADDR0_PACKET_END_RADDR0_SHIFT)) & SDU_FN_CARD_PKT_END_RADDR0_PACKET_END_RADDR0_MASK)
+/*! @} */
+
+/*! @name PKT_END_RADDR1 - PKT_END_RADDR1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_RADDR1_PACKET_END_RADDR1_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_RADDR1_PACKET_END_RADDR1_SHIFT (0U)
+/*! PACKET_END_RADDR1 - For function 1, this is used as CMD53 DMA read packet end addr [15:8] For
+ *    other functions, this is a scratch pad register
+ */
+#define SDU_FN_CARD_PKT_END_RADDR1_PACKET_END_RADDR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_RADDR1_PACKET_END_RADDR1_SHIFT)) & SDU_FN_CARD_PKT_END_RADDR1_PACKET_END_RADDR1_MASK)
+/*! @} */
+
+/*! @name PKT_END_RADDR2 - PKT_END_RADDR2 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_RADDR2_PACKET_END_RADDR2_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_RADDR2_PACKET_END_RADDR2_SHIFT (0U)
+/*! PACKET_END_RADDR2 - For function 1, this is used as CMD53 DMA read packet end addr [23:16] For
+ *    other functions, this is a scratch pad register
+ */
+#define SDU_FN_CARD_PKT_END_RADDR2_PACKET_END_RADDR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_RADDR2_PACKET_END_RADDR2_SHIFT)) & SDU_FN_CARD_PKT_END_RADDR2_PACKET_END_RADDR2_MASK)
+/*! @} */
+
+/*! @name PKT_END_RADDR3 - PKT_END_RADDR3 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_RADDR3_PACKET_END_RADDR3_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_RADDR3_PACKET_END_RADDR3_SHIFT (0U)
+/*! PACKET_END_RADDR3 - For function 1, this is used as CMD53 DMA read packet end addr [31:24] For
+ *    other functions, this is a scratch pad register
+ */
+#define SDU_FN_CARD_PKT_END_RADDR3_PACKET_END_RADDR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_RADDR3_PACKET_END_RADDR3_SHIFT)) & SDU_FN_CARD_PKT_END_RADDR3_PACKET_END_RADDR3_MASK)
+/*! @} */
+
+/*! @name PKT_END_WADDR0 - PKT_END_WADDR0 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_WADDR0_PACKET_END_WADDR0_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_WADDR0_PACKET_END_WADDR0_SHIFT (0U)
+/*! PACKET_END_WADDR0 - For function 1, this is used as CMD53 DMA write packet end addr [7:0] For
+ *    other functions, this is a scratch pad register
+ */
+#define SDU_FN_CARD_PKT_END_WADDR0_PACKET_END_WADDR0(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_WADDR0_PACKET_END_WADDR0_SHIFT)) & SDU_FN_CARD_PKT_END_WADDR0_PACKET_END_WADDR0_MASK)
+/*! @} */
+
+/*! @name PKT_END_WADDR1 - PKT_END_WADDR1 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_WADDR1_PACKET_END_WADDR1_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_WADDR1_PACKET_END_WADDR1_SHIFT (0U)
+/*! PACKET_END_WADDR1 - For function 1, this is used as CMD53 DMA write packet end addr [15:8] For
+ *    other functions, this is a scratch pad register
+ */
+#define SDU_FN_CARD_PKT_END_WADDR1_PACKET_END_WADDR1(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_WADDR1_PACKET_END_WADDR1_SHIFT)) & SDU_FN_CARD_PKT_END_WADDR1_PACKET_END_WADDR1_MASK)
+/*! @} */
+
+/*! @name PKT_END_WADDR2 - PKT_END_WADDR2 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_WADDR2_PACKET_END_WADDR2_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_WADDR2_PACKET_END_WADDR2_SHIFT (0U)
+/*! PACKET_END_WADDR2 - For function 1, this is used as CMD53 DMA write packet end addr [23:16] For
+ *    other functions, this is a scratch pad register
+ */
+#define SDU_FN_CARD_PKT_END_WADDR2_PACKET_END_WADDR2(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_WADDR2_PACKET_END_WADDR2_SHIFT)) & SDU_FN_CARD_PKT_END_WADDR2_PACKET_END_WADDR2_MASK)
+/*! @} */
+
+/*! @name PKT_END_WADDR3 - PKT_END_WADDR3 */
+/*! @{ */
+
+#define SDU_FN_CARD_PKT_END_WADDR3_PACKET_END_WADDR3_MASK (0xFFU)
+#define SDU_FN_CARD_PKT_END_WADDR3_PACKET_END_WADDR3_SHIFT (0U)
+/*! PACKET_END_WADDR3 - For function 1, this is used as CMD53 DMA write packet end addr [31:24] For
+ *    other functions, this is a scratch pad register
+ */
+#define SDU_FN_CARD_PKT_END_WADDR3_PACKET_END_WADDR3(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_PKT_END_WADDR3_PACKET_END_WADDR3_SHIFT)) & SDU_FN_CARD_PKT_END_WADDR3_PACKET_END_WADDR3_MASK)
+/*! @} */
+
+/*! @name OCR_0 - Operation Conditions 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_OCR_0_OCR0_MASK              (0xFFU)
+#define SDU_FN_CARD_OCR_0_OCR0_SHIFT             (0U)
+/*! OCR0 - Operation Conditions 0 */
+#define SDU_FN_CARD_OCR_0_OCR0(x)                (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_OCR_0_OCR0_SHIFT)) & SDU_FN_CARD_OCR_0_OCR0_MASK)
+/*! @} */
+
+/*! @name OCR_1 - Operation Conditions 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_OCR_1_OCR1_MASK              (0xFFU)
+#define SDU_FN_CARD_OCR_1_OCR1_SHIFT             (0U)
+/*! OCR1 - Operation Conditions 1 */
+#define SDU_FN_CARD_OCR_1_OCR1(x)                (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_OCR_1_OCR1_SHIFT)) & SDU_FN_CARD_OCR_1_OCR1_MASK)
+/*! @} */
+
+/*! @name OCR_2 - Operation Conditions 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_OCR_2_OCR2_MASK              (0xFFU)
+#define SDU_FN_CARD_OCR_2_OCR2_SHIFT             (0U)
+/*! OCR2 - Operation Conditions 2 */
+#define SDU_FN_CARD_OCR_2_OCR2(x)                (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_OCR_2_OCR2_SHIFT)) & SDU_FN_CARD_OCR_2_OCR2_MASK)
+/*! @} */
+
+/*! @name CARD_CONFIG_1 - Card Config1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_CONFIG_1_SD_NEG_EDGE_MASK (0x1U)
+#define SDU_FN_CARD_CARD_CONFIG_1_SD_NEG_EDGE_SHIFT (0U)
+/*! SD_NEG_EDGE - Sample Data Negative Edge SD interface data sampling edge. */
+#define SDU_FN_CARD_CARD_CONFIG_1_SD_NEG_EDGE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_SD_NEG_EDGE_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_SD_NEG_EDGE_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG_1_CMD53_FINISH_GBUS_MASK (0x2U)
+#define SDU_FN_CARD_CARD_CONFIG_1_CMD53_FINISH_GBUS_SHIFT (1U)
+/*! CMD53_FINISH_GBUS - Command 53 Finish Ahb Data transfer termination. */
+#define SDU_FN_CARD_CARD_CONFIG_1_CMD53_FINISH_GBUS(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_CMD53_FINISH_GBUS_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_CMD53_FINISH_GBUS_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_OVER_MASK (0x4U)
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_OVER_SHIFT (2U)
+/*! EXPLICIT_DNLD_OVER - Explicit Download Over 0 = download over is generated on completion of
+ *    CMD53 write 1 = download over is generated when host clears download ready interrupt
+ */
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_OVER(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_OVER_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_OVER_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_OVER_MASK (0x8U)
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_OVER_SHIFT (3U)
+/*! EXPLICIT_UPLD_OVER - Explicit Upload Over 0 = upload over is generated on completion of CMD53
+ *    read 1 = upload over is generated when host clears upload ready interrupt
+ */
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_OVER(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_OVER_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_OVER_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG_1_AGGR_INTR_EN_MASK (0x10U)
+#define SDU_FN_CARD_CARD_CONFIG_1_AGGR_INTR_EN_SHIFT (4U)
+/*! AGGR_INTR_EN - Aggregation Interrupt Enable 0 = only one download/upload over interrupt per
+ *    aggregate 1 = generate interrupt for each PDU in aggregate
+ */
+#define SDU_FN_CARD_CARD_CONFIG_1_AGGR_INTR_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_AGGR_INTR_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_AGGR_INTR_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_UPDATE_MASK (0x20U)
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_UPDATE_SHIFT (5U)
+/*! EXPLICIT_DNLD_UPDATE - Explicit Download Update 0 = bitmap update is done on completion of CMD53
+ *    write 1 = bitmap update is done when host clears download ready interrupt
+ */
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_UPDATE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_UPDATE_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_DNLD_UPDATE_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_UPDATE_MASK (0x40U)
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_UPDATE_SHIFT (6U)
+/*! EXPLICIT_UPLD_UPDATE - Explicit Upload Update 0 = bitmap update is done on completion of CMD53
+ *    read 1 = bitmap update is done when host clears upload
+ */
+#define SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_UPDATE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_UPDATE_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_EXPLICIT_UPLD_UPDATE_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG_1_IOE_WAKEUP_EN_MASK (0x80U)
+#define SDU_FN_CARD_CARD_CONFIG_1_IOE_WAKEUP_EN_SHIFT (7U)
+/*! IOE_WAKEUP_EN - If this is enabled, the 0-to-1 transition of the IO_ENABLE register bit of each
+ *    function that is written by host will generate a function-specific wakeup event to the APU.
+ */
+#define SDU_FN_CARD_CARD_CONFIG_1_IOE_WAKEUP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG_1_IOE_WAKEUP_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG_1_IOE_WAKEUP_EN_MASK)
+/*! @} */
+
+/*! @name CARD_CONFIG2_0 - Card Config2 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_FORCE_EN_MASK (0x1U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_FORCE_EN_SHIFT (0U)
+/*! CMD53_WR_BUSY_FORCE_EN - If this is enabled, write busy signal can be forced to 1 or 0
+ *    (specified by cmd53_wr_busy_force_val) and sent to host during cmd53 write operation.
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_FORCE_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_FORCE_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_FORCE_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_SQ_ADDR_WRAP_EN_MASK (0x2U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_SQ_ADDR_WRAP_EN_SHIFT (1U)
+/*! SQ_ADDR_WRAP_EN - If this is enabled, the DMA address of the current cmd53 access is wrapped
+ *    back to its starting address once it reaches the end address.
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_0_SQ_ADDR_WRAP_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_SQ_ADDR_WRAP_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_SQ_ADDR_WRAP_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_SD_POSEDGE_DRV_FORCE_EN_MASK (0x4U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_SD_POSEDGE_DRV_FORCE_EN_SHIFT (2U)
+/*! SD_POSEDGE_DRV_FORCE_EN - sd_posedge_drv_force_en */
+#define SDU_FN_CARD_CARD_CONFIG2_0_SD_POSEDGE_DRV_FORCE_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_SD_POSEDGE_DRV_FORCE_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_SD_POSEDGE_DRV_FORCE_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_FORCE_ASYNC_4BIT_INT_EN_MASK (0x8U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_FORCE_ASYNC_4BIT_INT_EN_SHIFT (3U)
+/*! FORCE_ASYNC_4BIT_INT_EN - Force asynchronous interrupt in SD 4-bit mode enable. */
+#define SDU_FN_CARD_CARD_CONFIG2_0_FORCE_ASYNC_4BIT_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_FORCE_ASYNC_4BIT_INT_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_FORCE_ASYNC_4BIT_INT_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_HOST_INT_AUTO_ENABLE_MASK (0x10U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_HOST_INT_AUTO_ENABLE_SHIFT (4U)
+/*! HOST_INT_AUTO_ENABLE - If this is enabled, download and upload ready host interrupt is
+ *    automatically cleared and re-enabled after the current cmd53 is completed.
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_0_HOST_INT_AUTO_ENABLE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_HOST_INT_AUTO_ENABLE_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_HOST_INT_AUTO_ENABLE_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_ONE_BLOCK_XFRD_SLCT_MASK (0x20U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_ONE_BLOCK_XFRD_SLCT_SHIFT (5U)
+/*! ONE_BLOCK_XFRD_SLCT - Firmware control to enable packet length issue fix for aggregation mode. */
+#define SDU_FN_CARD_CARD_CONFIG2_0_ONE_BLOCK_XFRD_SLCT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_ONE_BLOCK_XFRD_SLCT_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_ONE_BLOCK_XFRD_SLCT_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_SIGNAL_MASK (0x40U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_SIGNAL_SHIFT (6U)
+/*! CMD53_WR_BUSY_SIGNAL - Generate cmd53 write busy signal 0 = Write busy signal is not generated
+ *    on SD_DAT[0] line after each block of cmd53 write.
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_SIGNAL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_SIGNAL_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_SIGNAL_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_WIDTH_MASK (0x80U)
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_WIDTH_SHIFT (7U)
+/*! CMD53_WR_BUSY_WIDTH - cmd53_wr_busy_width */
+#define SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_WIDTH(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_WIDTH_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_0_CMD53_WR_BUSY_WIDTH_MASK)
+/*! @} */
+
+/*! @name CARD_CONFIG2_1 - Card Config2 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_NEW_MODE_MASK (0x1U)
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_NEW_MODE_SHIFT (0U)
+/*! CMD53_NEW_MODE - Enable new encoding scheme of the 17b register address field in CMD53. */
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_NEW_MODE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_1_CMD53_NEW_MODE_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_1_CMD53_NEW_MODE_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_1_SD_POSEDGE_DRV_FORCE_VAL_MASK (0x2U)
+#define SDU_FN_CARD_CARD_CONFIG2_1_SD_POSEDGE_DRV_FORCE_VAL_SHIFT (1U)
+/*! SD_POSEDGE_DRV_FORCE_VAL - If this is set to 1, SD output is driven at rising edge. */
+#define SDU_FN_CARD_CARD_CONFIG2_1_SD_POSEDGE_DRV_FORCE_VAL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_1_SD_POSEDGE_DRV_FORCE_VAL_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_1_SD_POSEDGE_DRV_FORCE_VAL_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_1_DNLD_RDY_AUTO_RESET_MASK (0x4U)
+#define SDU_FN_CARD_CARD_CONFIG2_1_DNLD_RDY_AUTO_RESET_SHIFT (2U)
+/*! DNLD_RDY_AUTO_RESET - Reset control for dnld_card_rdy event in C2H_INTEVENT 0 = download ready
+ *    event is reset to 0 after the current cmd53 is completed.
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_1_DNLD_RDY_AUTO_RESET(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_1_DNLD_RDY_AUTO_RESET_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_1_DNLD_RDY_AUTO_RESET_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_1_UPLD_RDY_AUTO_RESET_MASK (0x8U)
+#define SDU_FN_CARD_CARD_CONFIG2_1_UPLD_RDY_AUTO_RESET_SHIFT (3U)
+/*! UPLD_RDY_AUTO_RESET - Reset control for upld_card_rdy event in C2H_INTEVENT 0 = upload ready
+ *    event is reset to 0 after the current cmd53 is completed.
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_1_UPLD_RDY_AUTO_RESET(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_1_UPLD_RDY_AUTO_RESET_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_1_UPLD_RDY_AUTO_RESET_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_TX_LEN_FORMAT_MASK (0x30U)
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_TX_LEN_FORMAT_SHIFT (4U)
+/*! CMD53_TX_LEN_FORMAT - Define the cmd53 transmit/download length (tx_len) header format attached
+ *    in the beginning of data payload: 0 = no tx_len header info 1= first 2 bytes contain tx_len
+ *    info 2 = first 3 bytes contain tx_len info This field is applicable for non-aggregation mode only
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_TX_LEN_FORMAT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_1_CMD53_TX_LEN_FORMAT_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_1_CMD53_TX_LEN_FORMAT_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_RD_LEN_FORMAT_MASK (0xC0U)
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_RD_LEN_FORMAT_SHIFT (6U)
+/*! CMD53_RD_LEN_FORMAT - cmd53_rd_len_format */
+#define SDU_FN_CARD_CARD_CONFIG2_1_CMD53_RD_LEN_FORMAT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_1_CMD53_RD_LEN_FORMAT_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_1_CMD53_RD_LEN_FORMAT_MASK)
+/*! @} */
+
+/*! @name CARD_CONFIG2_2 - Card Config2 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_CONFIG2_2_TEST_DATA_OUT_MASK (0xFU)
+#define SDU_FN_CARD_CARD_CONFIG2_2_TEST_DATA_OUT_SHIFT (0U)
+/*! TEST_DATA_OUT - Test output data for SD_DAT. */
+#define SDU_FN_CARD_CARD_CONFIG2_2_TEST_DATA_OUT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_2_TEST_DATA_OUT_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_2_TEST_DATA_OUT_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_2_TEST_CMD_OUT_MASK (0x10U)
+#define SDU_FN_CARD_CARD_CONFIG2_2_TEST_CMD_OUT_SHIFT (4U)
+/*! TEST_CMD_OUT - Test output data for SD_CMD. */
+#define SDU_FN_CARD_CARD_CONFIG2_2_TEST_CMD_OUT(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_2_TEST_CMD_OUT_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_2_TEST_CMD_OUT_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_BUSY_FORCE_VAL_MASK (0x20U)
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_BUSY_FORCE_VAL_SHIFT (5U)
+/*! CMD53_WR_BUSY_FORCE_VAL - If cmd53_wr_busy_force_en is enabled, this register bit is used to force write busy signal to host. */
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_BUSY_FORCE_VAL(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_BUSY_FORCE_VAL_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_BUSY_FORCE_VAL_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_Q_EN_MASK (0x40U)
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_Q_EN_SHIFT (6U)
+/*! CMD53_WR_Q_EN - If this bit is 0, multiple queue feature is disabled for CMD53 write operation. */
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_Q_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_Q_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_2_CMD53_WR_Q_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_RD_Q_EN_MASK (0x80U)
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_RD_Q_EN_SHIFT (7U)
+/*! CMD53_RD_Q_EN - If this bit is 0, multiple queue feature is disabled for CMD53 read operation. */
+#define SDU_FN_CARD_CARD_CONFIG2_2_CMD53_RD_Q_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_2_CMD53_RD_Q_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_2_CMD53_RD_Q_EN_MASK)
+/*! @} */
+
+/*! @name CARD_CONFIG2_3 - Card Config2 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_CARD_CONFIG2_3_TEST_DATA_EN_MASK (0xFU)
+#define SDU_FN_CARD_CARD_CONFIG2_3_TEST_DATA_EN_SHIFT (0U)
+/*! TEST_DATA_EN - Test output enable for SD_DAT. */
+#define SDU_FN_CARD_CARD_CONFIG2_3_TEST_DATA_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_3_TEST_DATA_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_3_TEST_DATA_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_3_TEST_CMD_EN_MASK (0x10U)
+#define SDU_FN_CARD_CARD_CONFIG2_3_TEST_CMD_EN_SHIFT (4U)
+/*! TEST_CMD_EN - Test output enable for SD_CMD. */
+#define SDU_FN_CARD_CARD_CONFIG2_3_TEST_CMD_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_3_TEST_CMD_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_3_TEST_CMD_EN_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_3_PAD_TEST_MODE_MASK (0x20U)
+#define SDU_FN_CARD_CARD_CONFIG2_3_PAD_TEST_MODE_SHIFT (5U)
+/*! PAD_TEST_MODE - Enable test mode to directly drive SD_DAT and SD_CMD with test data specified by
+ *    test_data_out, test_cmd_out, test_data_en, and test_cmd_en fields.
+ */
+#define SDU_FN_CARD_CARD_CONFIG2_3_PAD_TEST_MODE(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_3_PAD_TEST_MODE_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_3_PAD_TEST_MODE_MASK)
+
+#define SDU_FN_CARD_CARD_CONFIG2_3_CMD53_WR_BUSY_HW_CTRL_EN_MASK (0x40U)
+#define SDU_FN_CARD_CARD_CONFIG2_3_CMD53_WR_BUSY_HW_CTRL_EN_SHIFT (6U)
+/*! CMD53_WR_BUSY_HW_CTRL_EN - Enable cmd53_wr_busy_hw_ctrl feature for each function. */
+#define SDU_FN_CARD_CARD_CONFIG2_3_CMD53_WR_BUSY_HW_CTRL_EN(x) (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_CARD_CONFIG2_3_CMD53_WR_BUSY_HW_CTRL_EN_SHIFT)) & SDU_FN_CARD_CARD_CONFIG2_3_CMD53_WR_BUSY_HW_CTRL_EN_MASK)
+/*! @} */
+
+/*! @name TESTBUS0 - Testbus 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_TESTBUS0_TESTBUS0_MASK       (0xFFU)
+#define SDU_FN_CARD_TESTBUS0_TESTBUS0_SHIFT      (0U)
+/*! TESTBUS0 - SDU testbus0 */
+#define SDU_FN_CARD_TESTBUS0_TESTBUS0(x)         (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_TESTBUS0_TESTBUS0_SHIFT)) & SDU_FN_CARD_TESTBUS0_TESTBUS0_MASK)
+/*! @} */
+
+/*! @name TESTBUS1 - Testbus 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_TESTBUS1_TESTBUS1_MASK       (0xFFU)
+#define SDU_FN_CARD_TESTBUS1_TESTBUS1_SHIFT      (0U)
+/*! TESTBUS1 - SDU testbus1 */
+#define SDU_FN_CARD_TESTBUS1_TESTBUS1(x)         (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_TESTBUS1_TESTBUS1_SHIFT)) & SDU_FN_CARD_TESTBUS1_TESTBUS1_MASK)
+/*! @} */
+
+/*! @name RCA0 - RCA 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_RCA0_RCA0_MASK               (0xFFU)
+#define SDU_FN_CARD_RCA0_RCA0_SHIFT              (0U)
+/*! RCA0 - RCA[7:0] */
+#define SDU_FN_CARD_RCA0_RCA0(x)                 (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_RCA0_RCA0_SHIFT)) & SDU_FN_CARD_RCA0_RCA0_MASK)
+/*! @} */
+
+/*! @name RCA1 - RCA 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_RCA1_RCA1_MASK               (0xFFU)
+#define SDU_FN_CARD_RCA1_RCA1_SHIFT              (0U)
+/*! RCA1 - RCA[15:8] */
+#define SDU_FN_CARD_RCA1_RCA1(x)                 (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_RCA1_RCA1_SHIFT)) & SDU_FN_CARD_RCA1_RCA1_MASK)
+/*! @} */
+
+/*! @name DMA_ADDR0 - DMA Address 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_DMA_ADDR0_DMA_ADDR0_MASK     (0xFFU)
+#define SDU_FN_CARD_DMA_ADDR0_DMA_ADDR0_SHIFT    (0U)
+/*! DMA_ADDR0 - DMA address [7:0] of last system bus transfer */
+#define SDU_FN_CARD_DMA_ADDR0_DMA_ADDR0(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_DMA_ADDR0_DMA_ADDR0_SHIFT)) & SDU_FN_CARD_DMA_ADDR0_DMA_ADDR0_MASK)
+/*! @} */
+
+/*! @name DMA_ADDR1 - DMA Address 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_DMA_ADDR1_DMA_ADDR1_MASK     (0xFFU)
+#define SDU_FN_CARD_DMA_ADDR1_DMA_ADDR1_SHIFT    (0U)
+/*! DMA_ADDR1 - DMA address [15:8] of last system bus transfer */
+#define SDU_FN_CARD_DMA_ADDR1_DMA_ADDR1(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_DMA_ADDR1_DMA_ADDR1_SHIFT)) & SDU_FN_CARD_DMA_ADDR1_DMA_ADDR1_MASK)
+/*! @} */
+
+/*! @name DMA_ADDR2 - DMA Address 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_DMA_ADDR2_DMA_ADDR2_MASK     (0xFFU)
+#define SDU_FN_CARD_DMA_ADDR2_DMA_ADDR2_SHIFT    (0U)
+/*! DMA_ADDR2 - DMA address [23:16] of last system bus transfer */
+#define SDU_FN_CARD_DMA_ADDR2_DMA_ADDR2(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_DMA_ADDR2_DMA_ADDR2_SHIFT)) & SDU_FN_CARD_DMA_ADDR2_DMA_ADDR2_MASK)
+/*! @} */
+
+/*! @name DMA_ADDR3 - DMA Address 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_DMA_ADDR3_DMA_ADDR3_MASK     (0xFFU)
+#define SDU_FN_CARD_DMA_ADDR3_DMA_ADDR3_SHIFT    (0U)
+/*! DMA_ADDR3 - DMA address [31:24] of last system bus transfer */
+#define SDU_FN_CARD_DMA_ADDR3_DMA_ADDR3(x)       (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_DMA_ADDR3_DMA_ADDR3_SHIFT)) & SDU_FN_CARD_DMA_ADDR3_DMA_ADDR3_MASK)
+/*! @} */
+
+/*! @name IO_PORT0 - I/O Port 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_IO_PORT0_IO_ADDR0_MASK       (0xFFU)
+#define SDU_FN_CARD_IO_PORT0_IO_ADDR0_SHIFT      (0U)
+/*! IO_ADDR0 - I/O port address [7:0] */
+#define SDU_FN_CARD_IO_PORT0_IO_ADDR0(x)         (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_IO_PORT0_IO_ADDR0_SHIFT)) & SDU_FN_CARD_IO_PORT0_IO_ADDR0_MASK)
+/*! @} */
+
+/*! @name IO_PORT1 - I/O Port 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_IO_PORT1_IO_ADDR1_MASK       (0xFFU)
+#define SDU_FN_CARD_IO_PORT1_IO_ADDR1_SHIFT      (0U)
+/*! IO_ADDR1 - I/O port address [15:8] */
+#define SDU_FN_CARD_IO_PORT1_IO_ADDR1(x)         (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_IO_PORT1_IO_ADDR1_SHIFT)) & SDU_FN_CARD_IO_PORT1_IO_ADDR1_MASK)
+/*! @} */
+
+/*! @name IO_PORT2 - I/O Port 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_IO_PORT2_IO_ADDR2_MASK       (0x1U)
+#define SDU_FN_CARD_IO_PORT2_IO_ADDR2_SHIFT      (0U)
+/*! IO_ADDR2 - I/O port address [16] */
+#define SDU_FN_CARD_IO_PORT2_IO_ADDR2(x)         (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_IO_PORT2_IO_ADDR2_SHIFT)) & SDU_FN_CARD_IO_PORT2_IO_ADDR2_MASK)
+/*! @} */
+
+/*! @name SCRATCH2_0 - Scratch 2 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH2_0_SCRATCH2_0_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH2_0_SCRATCH2_0_SHIFT  (0U)
+/*! SCRATCH2_0 - Scratch register 2 [7:0] */
+#define SDU_FN_CARD_SCRATCH2_0_SCRATCH2_0(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH2_0_SCRATCH2_0_SHIFT)) & SDU_FN_CARD_SCRATCH2_0_SCRATCH2_0_MASK)
+/*! @} */
+
+/*! @name SCRATCH2_1 - Scratch 2 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH2_1_SCRATCH2_1_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH2_1_SCRATCH2_1_SHIFT  (0U)
+/*! SCRATCH2_1 - Scratch register 2 [15:8] */
+#define SDU_FN_CARD_SCRATCH2_1_SCRATCH2_1(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH2_1_SCRATCH2_1_SHIFT)) & SDU_FN_CARD_SCRATCH2_1_SCRATCH2_1_MASK)
+/*! @} */
+
+/*! @name SCRATCH2_2 - Scratch 2 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH2_2_SCRATCH2_2_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH2_2_SCRATCH2_2_SHIFT  (0U)
+/*! SCRATCH2_2 - Scratch register 2 [23:16] */
+#define SDU_FN_CARD_SCRATCH2_2_SCRATCH2_2(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH2_2_SCRATCH2_2_SHIFT)) & SDU_FN_CARD_SCRATCH2_2_SCRATCH2_2_MASK)
+/*! @} */
+
+/*! @name SCRATCH2_3 - Scratch 2 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH2_3_SCRATCH2_3_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH2_3_SCRATCH2_3_SHIFT  (0U)
+/*! SCRATCH2_3 - Scratch register 2 [31:24] */
+#define SDU_FN_CARD_SCRATCH2_3_SCRATCH2_3(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH2_3_SCRATCH2_3_SHIFT)) & SDU_FN_CARD_SCRATCH2_3_SCRATCH2_3_MASK)
+/*! @} */
+
+/*! @name SCRATCH3_0 - Scratch 3 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH3_0_SCRATCH3_0_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH3_0_SCRATCH3_0_SHIFT  (0U)
+/*! SCRATCH3_0 - Scratch register 3 [7:0] */
+#define SDU_FN_CARD_SCRATCH3_0_SCRATCH3_0(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH3_0_SCRATCH3_0_SHIFT)) & SDU_FN_CARD_SCRATCH3_0_SCRATCH3_0_MASK)
+/*! @} */
+
+/*! @name SCRATCH3_1 - Scratch 3 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH3_1_SCRATCH3_1_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH3_1_SCRATCH3_1_SHIFT  (0U)
+/*! SCRATCH3_1 - Scratch register 3 [15:8] */
+#define SDU_FN_CARD_SCRATCH3_1_SCRATCH3_1(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH3_1_SCRATCH3_1_SHIFT)) & SDU_FN_CARD_SCRATCH3_1_SCRATCH3_1_MASK)
+/*! @} */
+
+/*! @name SCRATCH3_2 - Scratch 3 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH3_2_SCRATCH3_2_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH3_2_SCRATCH3_2_SHIFT  (0U)
+/*! SCRATCH3_2 - Scratch register 3 [23:16] */
+#define SDU_FN_CARD_SCRATCH3_2_SCRATCH3_2(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH3_2_SCRATCH3_2_SHIFT)) & SDU_FN_CARD_SCRATCH3_2_SCRATCH3_2_MASK)
+/*! @} */
+
+/*! @name SCRATCH3_3 - Scratch 3 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH3_3_SCRATCH3_3_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH3_3_SCRATCH3_3_SHIFT  (0U)
+/*! SCRATCH3_3 - Scratch register 3 [31:24] */
+#define SDU_FN_CARD_SCRATCH3_3_SCRATCH3_3(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH3_3_SCRATCH3_3_SHIFT)) & SDU_FN_CARD_SCRATCH3_3_SCRATCH3_3_MASK)
+/*! @} */
+
+/*! @name SCRATCH4_0 - Scratch 4 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH4_0_SCRATCH4_0_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH4_0_SCRATCH4_0_SHIFT  (0U)
+/*! SCRATCH4_0 - Scratch register 4 [7:0] */
+#define SDU_FN_CARD_SCRATCH4_0_SCRATCH4_0(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH4_0_SCRATCH4_0_SHIFT)) & SDU_FN_CARD_SCRATCH4_0_SCRATCH4_0_MASK)
+/*! @} */
+
+/*! @name SCRATCH4_1 - Scratch 4 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH4_1_SCRATCH4_1_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH4_1_SCRATCH4_1_SHIFT  (0U)
+/*! SCRATCH4_1 - Scratch register 4 [15:8] */
+#define SDU_FN_CARD_SCRATCH4_1_SCRATCH4_1(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH4_1_SCRATCH4_1_SHIFT)) & SDU_FN_CARD_SCRATCH4_1_SCRATCH4_1_MASK)
+/*! @} */
+
+/*! @name SCRATCH4_2 - Scratch 4 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH4_2_SCRATCH4_2_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH4_2_SCRATCH4_2_SHIFT  (0U)
+/*! SCRATCH4_2 - Scratch register 4 [23:16] */
+#define SDU_FN_CARD_SCRATCH4_2_SCRATCH4_2(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH4_2_SCRATCH4_2_SHIFT)) & SDU_FN_CARD_SCRATCH4_2_SCRATCH4_2_MASK)
+/*! @} */
+
+/*! @name SCRATCH4_3 - Scratch 4 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH4_3_SCRATCH4_3_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH4_3_SCRATCH4_3_SHIFT  (0U)
+/*! SCRATCH4_3 - Scratch register 4 [31:24] */
+#define SDU_FN_CARD_SCRATCH4_3_SCRATCH4_3(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH4_3_SCRATCH4_3_SHIFT)) & SDU_FN_CARD_SCRATCH4_3_SCRATCH4_3_MASK)
+/*! @} */
+
+/*! @name SCRATCH5_0 - Scratch 5 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH5_0_SCRATCH5_0_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH5_0_SCRATCH5_0_SHIFT  (0U)
+/*! SCRATCH5_0 - Scratch register 5 [7:0] */
+#define SDU_FN_CARD_SCRATCH5_0_SCRATCH5_0(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH5_0_SCRATCH5_0_SHIFT)) & SDU_FN_CARD_SCRATCH5_0_SCRATCH5_0_MASK)
+/*! @} */
+
+/*! @name SCRATCH5_1 - Scratch 5 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH5_1_SCRATCH5_1_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH5_1_SCRATCH5_1_SHIFT  (0U)
+/*! SCRATCH5_1 - Scratch register 5 [15:8] */
+#define SDU_FN_CARD_SCRATCH5_1_SCRATCH5_1(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH5_1_SCRATCH5_1_SHIFT)) & SDU_FN_CARD_SCRATCH5_1_SCRATCH5_1_MASK)
+/*! @} */
+
+/*! @name SCRATCH5_2 - Scratch 5 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH5_2_SCRATCH5_2_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH5_2_SCRATCH5_2_SHIFT  (0U)
+/*! SCRATCH5_2 - Scratch register 5 [23:16] */
+#define SDU_FN_CARD_SCRATCH5_2_SCRATCH5_2(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH5_2_SCRATCH5_2_SHIFT)) & SDU_FN_CARD_SCRATCH5_2_SCRATCH5_2_MASK)
+/*! @} */
+
+/*! @name SCRATCH5_3 - Scratch 5 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH5_3_SCRATCH5_3_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH5_3_SCRATCH5_3_SHIFT  (0U)
+/*! SCRATCH5_3 - Scratch register 5 [31:24] */
+#define SDU_FN_CARD_SCRATCH5_3_SCRATCH5_3(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH5_3_SCRATCH5_3_SHIFT)) & SDU_FN_CARD_SCRATCH5_3_SCRATCH5_3_MASK)
+/*! @} */
+
+/*! @name SCRATCH6_0 - Scratch 6 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH6_0_SCRATCH6_0_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH6_0_SCRATCH6_0_SHIFT  (0U)
+/*! SCRATCH6_0 - Scratch register 6 [7:0] */
+#define SDU_FN_CARD_SCRATCH6_0_SCRATCH6_0(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH6_0_SCRATCH6_0_SHIFT)) & SDU_FN_CARD_SCRATCH6_0_SCRATCH6_0_MASK)
+/*! @} */
+
+/*! @name SCRATCH6_1 - Scratch 6 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH6_1_SCRATCH6_1_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH6_1_SCRATCH6_1_SHIFT  (0U)
+/*! SCRATCH6_1 - Scratch register 6 [15:8] */
+#define SDU_FN_CARD_SCRATCH6_1_SCRATCH6_1(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH6_1_SCRATCH6_1_SHIFT)) & SDU_FN_CARD_SCRATCH6_1_SCRATCH6_1_MASK)
+/*! @} */
+
+/*! @name SCRATCH6_2 - Scratch 6 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH6_2_SCRATCH6_2_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH6_2_SCRATCH6_2_SHIFT  (0U)
+/*! SCRATCH6_2 - Scratch register 6 [23:16] */
+#define SDU_FN_CARD_SCRATCH6_2_SCRATCH6_2(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH6_2_SCRATCH6_2_SHIFT)) & SDU_FN_CARD_SCRATCH6_2_SCRATCH6_2_MASK)
+/*! @} */
+
+/*! @name SCRATCH6_3 - Scratch 6 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH6_3_SCRATCH6_3_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH6_3_SCRATCH6_3_SHIFT  (0U)
+/*! SCRATCH6_3 - Scratch register 6 [31:24] */
+#define SDU_FN_CARD_SCRATCH6_3_SCRATCH6_3(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH6_3_SCRATCH6_3_SHIFT)) & SDU_FN_CARD_SCRATCH6_3_SCRATCH6_3_MASK)
+/*! @} */
+
+/*! @name SCRATCH7_0 - Scratch 7 0 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH7_0_SCRATCH7_0_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH7_0_SCRATCH7_0_SHIFT  (0U)
+/*! SCRATCH7_0 - Scratch register 7 [7:0] */
+#define SDU_FN_CARD_SCRATCH7_0_SCRATCH7_0(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH7_0_SCRATCH7_0_SHIFT)) & SDU_FN_CARD_SCRATCH7_0_SCRATCH7_0_MASK)
+/*! @} */
+
+/*! @name SCRATCH7_1 - Scratch 7 1 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH7_1_SCRATCH7_1_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH7_1_SCRATCH7_1_SHIFT  (0U)
+/*! SCRATCH7_1 - Scratch register 7 [15:8] */
+#define SDU_FN_CARD_SCRATCH7_1_SCRATCH7_1(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH7_1_SCRATCH7_1_SHIFT)) & SDU_FN_CARD_SCRATCH7_1_SCRATCH7_1_MASK)
+/*! @} */
+
+/*! @name SCRATCH7_2 - Scratch 7 2 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH7_2_SCRATCH7_2_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH7_2_SCRATCH7_2_SHIFT  (0U)
+/*! SCRATCH7_2 - Scratch register 7 [23:16] */
+#define SDU_FN_CARD_SCRATCH7_2_SCRATCH7_2(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH7_2_SCRATCH7_2_SHIFT)) & SDU_FN_CARD_SCRATCH7_2_SCRATCH7_2_MASK)
+/*! @} */
+
+/*! @name SCRATCH7_3 - Scratch 7 3 */
+/*! @{ */
+
+#define SDU_FN_CARD_SCRATCH7_3_SCRATCH7_3_MASK   (0xFFU)
+#define SDU_FN_CARD_SCRATCH7_3_SCRATCH7_3_SHIFT  (0U)
+/*! SCRATCH7_3 - Scratch register 7 [31:24] */
+#define SDU_FN_CARD_SCRATCH7_3_SCRATCH7_3(x)     (((uint8_t)(((uint8_t)(x)) << SDU_FN_CARD_SCRATCH7_3_SCRATCH7_3_SHIFT)) & SDU_FN_CARD_SCRATCH7_3_SCRATCH7_3_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SDU_FN_CARD_Register_Masks */
+
+
+/* SDU_FN_CARD - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SDU_FN_CARD base address */
+  #define SDU_FN_CARD_BASE                         (0x50158100u)
+  /** Peripheral SDU_FN_CARD base address */
+  #define SDU_FN_CARD_BASE_NS                      (0x40158100u)
+  /** Peripheral SDU_FN_CARD base pointer */
+  #define SDU_FN_CARD                              ((SDU_FN_CARD_Type *)SDU_FN_CARD_BASE)
+  /** Peripheral SDU_FN_CARD base pointer */
+  #define SDU_FN_CARD_NS                           ((SDU_FN_CARD_Type *)SDU_FN_CARD_BASE_NS)
+  /** Array initializer of SDU_FN_CARD peripheral base addresses */
+  #define SDU_FN_CARD_BASE_ADDRS                   { SDU_FN_CARD_BASE }
+  /** Array initializer of SDU_FN_CARD peripheral base pointers */
+  #define SDU_FN_CARD_BASE_PTRS                    { SDU_FN_CARD }
+  /** Array initializer of SDU_FN_CARD peripheral base addresses */
+  #define SDU_FN_CARD_BASE_ADDRS_NS                { SDU_FN_CARD_BASE_NS }
+  /** Array initializer of SDU_FN_CARD peripheral base pointers */
+  #define SDU_FN_CARD_BASE_PTRS_NS                 { SDU_FN_CARD_NS }
+#else
+  /** Peripheral SDU_FN_CARD base address */
+  #define SDU_FN_CARD_BASE                         (0x40158100u)
+  /** Peripheral SDU_FN_CARD base pointer */
+  #define SDU_FN_CARD                              ((SDU_FN_CARD_Type *)SDU_FN_CARD_BASE)
+  /** Array initializer of SDU_FN_CARD peripheral base addresses */
+  #define SDU_FN_CARD_BASE_ADDRS                   { SDU_FN_CARD_BASE }
+  /** Array initializer of SDU_FN_CARD peripheral base pointers */
+  #define SDU_FN_CARD_BASE_PTRS                    { SDU_FN_CARD }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SDU_FN_CARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SENSOR_CTRL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SENSOR_CTRL_Peripheral_Access_Layer SENSOR_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** SENSOR_CTRL - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ADC_CTRL_REG_1;                    /**< General configuration of ADCC, offset: 0x0 */
+  __I  uint32_t ADC_STATUS_REG;                    /**< status of ADC and ADCC, offset: 0x4 */
+  __IO uint32_t TSEN_CTRL_1_REG_1;                 /**< TSEN Controller configuration, offset: 0x8 */
+  __I  uint32_t TSEN_CTRL_1_REG_2;                 /**< TSEN Controller Output status register, offset: 0xC */
+  __IO uint32_t TSEN_CTRL_2_REG_1;                 /**< TSEN Controller configuration, offset: 0x10 */
+  __I  uint32_t TSEN_CTRL_2_REG_2;                 /**< TSEN Controller Output status register, offset: 0x14 */
+  __IO uint32_t VSEN_CTRL_1_REG_1;                 /**< VSEN Controller configuration, offset: 0x18 */
+  __I  uint32_t VSEN_CTRL_1_REG_2;                 /**< VSEN Controller Output status register, offset: 0x1C */
+  __IO uint32_t VSEN_CTRL_2_REG_1;                 /**< VSEN2 Controller configuration, offset: 0x20 */
+  __I  uint32_t VSEN_CTRL_2_REG_2;                 /**< VSEN2 Controller Output status register, offset: 0x24 */
+  __IO uint32_t VSEN_CTRL_3_REG_1;                 /**< VSEN3 Controller configuration, offset: 0x28 */
+  __I  uint32_t VSEN_CTRL_3_REG_2;                 /**< VSEN3 Controller Output status register, offset: 0x2C */
+  __IO uint32_t VGLITCH_CTRL_REG_1;                /**< Voltage Glitch sensor controller configuration, offset: 0x30 */
+  __IO uint32_t MISC_CTRL_REG;                     /**< Miscellaneous controls, offset: 0x34 */
+  __IO uint32_t CFG_ERR_STATUS_REG;                /**< CFG ERROR Control, offset: 0x38 */
+  __IO uint32_t SEN_CLR_REG;                       /**< CFG ERROR Control, offset: 0x3C */
+  __IO uint32_t SEC_ECO_REG;                       /**< ECO Bits, offset: 0x40 */
+} SENSOR_CTRL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SENSOR_CTRL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SENSOR_CTRL_Register_Masks SENSOR_CTRL Register Masks
+ * @{
+ */
+
+/*! @name ADC_CTRL_REG_1 - General configuration of ADCC */
+/*! @{ */
+
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_RESET_MASK (0x1U)
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_RESET_SHIFT (0U)
+/*! ADCC_SW_RESET - sw reset from CPU for sensor and controller */
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_RESET_SHIFT)) & SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_RESET_MASK)
+
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_CAL_ENABLE_MASK (0x2U)
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_CAL_ENABLE_SHIFT (1U)
+/*! ADCC_SW_CAL_ENABLE - SW triggered calibration enable. */
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_CAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_CAL_ENABLE_SHIFT)) & SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_CAL_ENABLE_MASK)
+
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_ENABLE_MASK (0x4U)
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_ENABLE_SHIFT (2U)
+/*! ADCC_SW_ENABLE - sw enable from CPU for sensor and controller */
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_ENABLE_SHIFT)) & SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_SW_ENABLE_MASK)
+
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TEST_CAL_BYPASS_MASK (0x8U)
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TEST_CAL_BYPASS_SHIFT (3U)
+/*! ADCC_TEST_CAL_BYPASS - bypass calibration for ATE or other test */
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TEST_CAL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TEST_CAL_BYPASS_SHIFT)) & SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TEST_CAL_BYPASS_MASK)
+
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TB_SEL_MASK (0x30U)
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TB_SEL_SHIFT (4U)
+/*! ADCC_TB_SEL - It selects one of the testbuses of ADCC. */
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TB_SEL_SHIFT)) & SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_TB_SEL_MASK)
+
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_BYPASS_MASK (0x40U)
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_BYPASS_SHIFT (6U)
+/*! ADCC_ERR_GAIN_BYPASS - Bypass error gain adjustment in ADCC data output */
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_BYPASS_SHIFT)) & SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_BYPASS_MASK)
+
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_MASK (0x780U)
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_SHIFT (7U)
+/*! ADCC_ERR_GAIN - IT is 4 bIT signed integer value of error gain of SARADC. If
+ *    adcc_err_gain_bypass is set as 1, then this value is not considered for error gain adjustment of ADCC data
+ *    output. Example: If value of this field is 4'b1110, then IT is -2 in decimal.
+ */
+#define SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_SHIFT)) & SENSOR_CTRL_ADC_CTRL_REG_1_ADCC_ERR_GAIN_MASK)
+/*! @} */
+
+/*! @name ADC_STATUS_REG - status of ADC and ADCC */
+/*! @{ */
+
+#define SENSOR_CTRL_ADC_STATUS_REG_ADCC_OFFSET_CODE_MASK (0xFFFU)
+#define SENSOR_CTRL_ADC_STATUS_REG_ADCC_OFFSET_CODE_SHIFT (0U)
+/*! ADCC_OFFSET_CODE - OFFSET of ADC computed after calibration. It is a signed number (2's
+ *    complement format) with 1 fractional bit. Example, If binary value of this field is 1111_1111_0011
+ *    then it represents -6.5 in decimal. Note that, this field is valid only when adcc_cal_done bit is
+ *    1.
+ */
+#define SENSOR_CTRL_ADC_STATUS_REG_ADCC_OFFSET_CODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_STATUS_REG_ADCC_OFFSET_CODE_SHIFT)) & SENSOR_CTRL_ADC_STATUS_REG_ADCC_OFFSET_CODE_MASK)
+
+#define SENSOR_CTRL_ADC_STATUS_REG_ADCC_CAL_DONE_MASK (0x1000U)
+#define SENSOR_CTRL_ADC_STATUS_REG_ADCC_CAL_DONE_SHIFT (12U)
+/*! ADCC_CAL_DONE - Valid value: */
+#define SENSOR_CTRL_ADC_STATUS_REG_ADCC_CAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_STATUS_REG_ADCC_CAL_DONE_SHIFT)) & SENSOR_CTRL_ADC_STATUS_REG_ADCC_CAL_DONE_MASK)
+
+#define SENSOR_CTRL_ADC_STATUS_REG_PU_ADC_REG_MASK (0x2000U)
+#define SENSOR_CTRL_ADC_STATUS_REG_PU_ADC_REG_SHIFT (13U)
+/*! PU_ADC_REG - Powerup/ power down value: */
+#define SENSOR_CTRL_ADC_STATUS_REG_PU_ADC_REG(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_STATUS_REG_PU_ADC_REG_SHIFT)) & SENSOR_CTRL_ADC_STATUS_REG_PU_ADC_REG_MASK)
+
+#define SENSOR_CTRL_ADC_STATUS_REG_ADC_OUT_DFF_RSTB_MASK (0x4000U)
+#define SENSOR_CTRL_ADC_STATUS_REG_ADC_OUT_DFF_RSTB_SHIFT (14U)
+/*! ADC_OUT_DFF_RSTB - Reset value: */
+#define SENSOR_CTRL_ADC_STATUS_REG_ADC_OUT_DFF_RSTB(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_ADC_STATUS_REG_ADC_OUT_DFF_RSTB_SHIFT)) & SENSOR_CTRL_ADC_STATUS_REG_ADC_OUT_DFF_RSTB_MASK)
+/*! @} */
+
+/*! @name TSEN_CTRL_1_REG_1 - TSEN Controller configuration */
+/*! @{ */
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_RESET_MASK (0x1U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_RESET_SHIFT (0U)
+/*! TSEN_SW_RESET - sw reset from CPU for sensor and controller */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_RESET_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_RESET_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_ENABLE_MASK (0x2U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_ENABLE_SHIFT (1U)
+/*! TSEN_SW_ENABLE - sw enable from CPU for sensor and controller */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_ENABLE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_ENABLE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TRIGGER_MODE_MASK (0xCU)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TRIGGER_MODE_SHIFT (2U)
+/*! TSEN_TRIGGER_MODE - Trigger mode for sensor => DEFAULT: periodic */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TRIGGER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TRIGGER_MODE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TRIGGER_MODE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TESTMODE_MASK (0x10U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TESTMODE_SHIFT (4U)
+/*! TSEN_TESTMODE - This bit is used to test sensor controller. */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TESTMODE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_TESTMODE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_TEMP_READ_EN_MASK (0x20U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_TEMP_READ_EN_SHIFT (5U)
+/*! TSEN_SW_TEMP_READ_EN - SW based temperature reading enable for tsen (corresponding to tsen_trigger_mode = 1) */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_TEMP_READ_EN(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_TEMP_READ_EN_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_SW_TEMP_READ_EN_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MIN_TEMP_THR_MASK (0x3FF00U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MIN_TEMP_THR_SHIFT (8U)
+/*! TSEN_MIN_TEMP_THR - SW programmed minimum threshold for sensor. Default is -37C. */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MIN_TEMP_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MIN_TEMP_THR_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MIN_TEMP_THR_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MAX_TEMP_THR_MASK (0x3FF00000U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MAX_TEMP_THR_SHIFT (20U)
+/*! TSEN_MAX_TEMP_THR - SW programmed maximum threshold for sensor. Default is 137C. */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MAX_TEMP_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MAX_TEMP_THR_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_1_TSEN_MAX_TEMP_THR_MASK)
+/*! @} */
+
+/*! @name TSEN_CTRL_1_REG_2 - TSEN Controller Output status register */
+/*! @{ */
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERR_TEMP_PVALUE_MASK (0x3FFU)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERR_TEMP_PVALUE_SHIFT (0U)
+/*! TSEN_ERR_TEMP_PVALUE - The sensor reading captured at the time of *sen_error event -> this is for SW */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERR_TEMP_PVALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERR_TEMP_PVALUE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERR_TEMP_PVALUE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_TEMP_VALUE_MASK (0xFFC00U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_TEMP_VALUE_SHIFT (10U)
+/*! TSEN_TEMP_VALUE - reading from last sensor sampling available for SW to read out */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_TEMP_VALUE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_TEMP_VALUE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERROR_MASK (0x100000U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERROR_SHIFT (20U)
+/*! TSEN_ERROR - Error indication from sensor */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERROR_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSEN_ERROR_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_MASK (0x200000U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_SHIFT (21U)
+/*! SW_ON_DEMAND_TSEN_RD_DONE_STATUS - Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode. */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSENDC_DEBUG_MASK (0xFFC00000U)
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSENDC_DEBUG_SHIFT (22U)
+/*! TSENDC_DEBUG - Field description: */
+#define SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSENDC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSENDC_DEBUG_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_1_REG_2_TSENDC_DEBUG_MASK)
+/*! @} */
+
+/*! @name TSEN_CTRL_2_REG_1 - TSEN Controller configuration */
+/*! @{ */
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_RESET_MASK (0x1U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_RESET_SHIFT (0U)
+/*! TSEN_SW_RESET - sw reset from CPU for sensor and controller */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_RESET_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_RESET_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_ENABLE_MASK (0x2U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_ENABLE_SHIFT (1U)
+/*! TSEN_SW_ENABLE - sw enable from CPU for sensor and controller(TSEN_PMIP is disabled by default) */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_ENABLE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_ENABLE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TRIGGER_MODE_MASK (0xCU)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TRIGGER_MODE_SHIFT (2U)
+/*! TSEN_TRIGGER_MODE - Trigger mode for sensor => DEFAULT: periodic */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TRIGGER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TRIGGER_MODE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TRIGGER_MODE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TESTMODE_MASK (0x10U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TESTMODE_SHIFT (4U)
+/*! TSEN_TESTMODE - This bit is used to test sensor controller. */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TESTMODE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_TESTMODE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_TEMP_READ_EN_MASK (0x20U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_TEMP_READ_EN_SHIFT (5U)
+/*! TSEN_SW_TEMP_READ_EN - SW based temperature reading enable for tsen (corresponding to tsen_trigger_mode = 1) */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_TEMP_READ_EN(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_TEMP_READ_EN_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_SW_TEMP_READ_EN_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MIN_TEMP_THR_MASK (0x3FF00U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MIN_TEMP_THR_SHIFT (8U)
+/*! TSEN_MIN_TEMP_THR - SW programmed minimum threshold for sensor. Default is -37C. */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MIN_TEMP_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MIN_TEMP_THR_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MIN_TEMP_THR_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MAX_TEMP_THR_MASK (0x3FF00000U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MAX_TEMP_THR_SHIFT (20U)
+/*! TSEN_MAX_TEMP_THR - SW programmed maximum threshold for sensor. Default is 137C */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MAX_TEMP_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MAX_TEMP_THR_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_1_TSEN_MAX_TEMP_THR_MASK)
+/*! @} */
+
+/*! @name TSEN_CTRL_2_REG_2 - TSEN Controller Output status register */
+/*! @{ */
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERR_TEMP_PVALUE_MASK (0x3FFU)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERR_TEMP_PVALUE_SHIFT (0U)
+/*! TSEN_ERR_TEMP_PVALUE - The sensor reading captured at the time of *sen_error event -> this is for SW */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERR_TEMP_PVALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERR_TEMP_PVALUE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERR_TEMP_PVALUE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_TEMP_VALUE_MASK (0xFFC00U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_TEMP_VALUE_SHIFT (10U)
+/*! TSEN_TEMP_VALUE - reading from last sensor sampling available for SW to read out */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_TEMP_VALUE_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_TEMP_VALUE_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERROR_MASK (0x100000U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERROR_SHIFT (20U)
+/*! TSEN_ERROR - Error indication from sensor */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERROR_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSEN_ERROR_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_MASK (0x200000U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_SHIFT (21U)
+/*! SW_ON_DEMAND_TSEN_RD_DONE_STATUS - Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode. */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_2_SW_ON_DEMAND_TSEN_RD_DONE_STATUS_MASK)
+
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSENDC_DEBUG_MASK (0xFFC00000U)
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSENDC_DEBUG_SHIFT (22U)
+/*! TSENDC_DEBUG - Field description: */
+#define SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSENDC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSENDC_DEBUG_SHIFT)) & SENSOR_CTRL_TSEN_CTRL_2_REG_2_TSENDC_DEBUG_MASK)
+/*! @} */
+
+/*! @name VSEN_CTRL_1_REG_1 - VSEN Controller configuration */
+/*! @{ */
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_RESET_MASK (0x1U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_RESET_SHIFT (0U)
+/*! VSEN_SW_RESET - sw reset from CPU for sensor and controller */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_RESET_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_RESET_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK (0x2U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_SHIFT (1U)
+/*! VSEN_SW_ENABLE - sw enable from CPU for sensor and controller */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TRIGGER_MODE_MASK (0xCU)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TRIGGER_MODE_SHIFT (2U)
+/*! VSEN_TRIGGER_MODE - Trigger mode for sensor => DEFAULT: periodic */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TRIGGER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TRIGGER_MODE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TRIGGER_MODE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TESTMODE_MASK (0x10U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TESTMODE_SHIFT (4U)
+/*! VSEN_TESTMODE - This bit is used to test sensor controller. */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TESTMODE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_TESTMODE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_VOLTAGE_READ_EN_MASK (0x20U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_VOLTAGE_READ_EN_SHIFT (5U)
+/*! VSEN_SW_VOLTAGE_READ_EN - SW based reading enable for sensor (corresponding to *sen_trigger_mode = 1) */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_VOLTAGE_READ_EN(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_VOLTAGE_READ_EN_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_VOLTAGE_READ_EN_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR_MASK (0x3FF00U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR_SHIFT (8U)
+/*! VSEN_MIN_VOLTAGE_THR - SW programmed minimum threshold for sensor. Default value is 0.925v. */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR_MASK (0x3FF00000U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR_SHIFT (20U)
+/*! VSEN_MAX_VOLTAGE_THR - SW programmed maximum threshold for sensor. Default */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR_MASK)
+/*! @} */
+
+/*! @name VSEN_CTRL_1_REG_2 - VSEN Controller Output status register */
+/*! @{ */
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERR_VOLTAGE_PVALUE_MASK (0x3FFU)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERR_VOLTAGE_PVALUE_SHIFT (0U)
+/*! VSEN_ERR_VOLTAGE_PVALUE - The sensor reading captured at the time of *sen_error event -> this is for SW */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERR_VOLTAGE_PVALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERR_VOLTAGE_PVALUE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERR_VOLTAGE_PVALUE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_VOLTAGE_VALUE_MASK (0xFFC00U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_VOLTAGE_VALUE_SHIFT (10U)
+/*! VSEN_VOLTAGE_VALUE - reading from last sensor sampling available for SW to read out */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_VOLTAGE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_VOLTAGE_VALUE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_VOLTAGE_VALUE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERROR_MASK (0x100000U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERROR_SHIFT (20U)
+/*! VSEN_ERROR - Error indication from sensor */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERROR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSEN_ERROR_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_MASK (0x200000U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_SHIFT (21U)
+/*! SW_ON_DEMAND_VSEN_RD_DONE_STATUS - Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode. */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSENDC_DEBUG_MASK (0xFFC00000U)
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSENDC_DEBUG_SHIFT (22U)
+/*! VSENDC_DEBUG - Field description: */
+#define SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSENDC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSENDC_DEBUG_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_1_REG_2_VSENDC_DEBUG_MASK)
+/*! @} */
+
+/*! @name VSEN_CTRL_2_REG_1 - VSEN2 Controller configuration */
+/*! @{ */
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_RESET_MASK (0x1U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_RESET_SHIFT (0U)
+/*! VSEN_SW_RESET - sw reset from CPU for sensor and controller */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_RESET_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_RESET_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_MASK (0x2U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_SHIFT (1U)
+/*! VSEN_SW_ENABLE - sw enable from CPU for sensor and controller */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TRIGGER_MODE_MASK (0xCU)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TRIGGER_MODE_SHIFT (2U)
+/*! VSEN_TRIGGER_MODE - Trigger mode for sensor => DEFAULT: periodic */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TRIGGER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TRIGGER_MODE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TRIGGER_MODE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TESTMODE_MASK (0x10U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TESTMODE_SHIFT (4U)
+/*! VSEN_TESTMODE - This bit is used to test sensor controller. */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TESTMODE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_TESTMODE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_VOLTAGE_READ_EN_MASK (0x20U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_VOLTAGE_READ_EN_SHIFT (5U)
+/*! VSEN_SW_VOLTAGE_READ_EN - SW based reading enable for sensor (corresponding to *sen_trigger_mode = 1) */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_VOLTAGE_READ_EN(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_VOLTAGE_READ_EN_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_VOLTAGE_READ_EN_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MIN_VOLTAGE_THR_MASK (0x3FF00U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MIN_VOLTAGE_THR_SHIFT (8U)
+/*! VSEN_MIN_VOLTAGE_THR - SW programmed minimum threshold for sensor. Default */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MIN_VOLTAGE_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MIN_VOLTAGE_THR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MIN_VOLTAGE_THR_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MAX_VOLTAGE_THR_MASK (0x3FF00000U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MAX_VOLTAGE_THR_SHIFT (20U)
+/*! VSEN_MAX_VOLTAGE_THR - SW programmed maximum threshold for sensor. Default */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MAX_VOLTAGE_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MAX_VOLTAGE_THR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MAX_VOLTAGE_THR_MASK)
+/*! @} */
+
+/*! @name VSEN_CTRL_2_REG_2 - VSEN2 Controller Output status register */
+/*! @{ */
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERR_VOLTAGE_PVALUE_MASK (0x3FFU)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERR_VOLTAGE_PVALUE_SHIFT (0U)
+/*! VSEN_ERR_VOLTAGE_PVALUE - The sensor reading captured at the time of *sen_error event -> this is for SW */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERR_VOLTAGE_PVALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERR_VOLTAGE_PVALUE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERR_VOLTAGE_PVALUE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_VOLTAGE_VALUE_MASK (0xFFC00U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_VOLTAGE_VALUE_SHIFT (10U)
+/*! VSEN_VOLTAGE_VALUE - reading from last sensor sampling available for SW to read out */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_VOLTAGE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_VOLTAGE_VALUE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_VOLTAGE_VALUE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERROR_MASK (0x100000U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERROR_SHIFT (20U)
+/*! VSEN_ERROR - Error indication from sensor */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERROR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSEN_ERROR_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_MASK (0x200000U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_SHIFT (21U)
+/*! SW_ON_DEMAND_VSEN_RD_DONE_STATUS - Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode. */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSENDC_DEBUG_MASK (0xFFC00000U)
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSENDC_DEBUG_SHIFT (22U)
+/*! VSENDC_DEBUG - Field description: */
+#define SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSENDC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSENDC_DEBUG_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_2_REG_2_VSENDC_DEBUG_MASK)
+/*! @} */
+
+/*! @name VSEN_CTRL_3_REG_1 - VSEN3 Controller configuration */
+/*! @{ */
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_RESET_MASK (0x1U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_RESET_SHIFT (0U)
+/*! VSEN_SW_RESET - sw reset from CPU for sensor and controller */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_RESET_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_RESET_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_MASK (0x2U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_SHIFT (1U)
+/*! VSEN_SW_ENABLE - sw enable from CPU for sensor and controller */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TRIGGER_MODE_MASK (0xCU)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TRIGGER_MODE_SHIFT (2U)
+/*! VSEN_TRIGGER_MODE - Trigger mode for sensor => DEFAULT: periodic */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TRIGGER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TRIGGER_MODE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TRIGGER_MODE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TESTMODE_MASK (0x10U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TESTMODE_SHIFT (4U)
+/*! VSEN_TESTMODE - This bit is used to test sensor controller. */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TESTMODE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_TESTMODE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_VOLTAGE_READ_EN_MASK (0x20U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_VOLTAGE_READ_EN_SHIFT (5U)
+/*! VSEN_SW_VOLTAGE_READ_EN - SW based reading enable for sensor (corresponding to *sen_trigger_mode = 1) */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_VOLTAGE_READ_EN(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_VOLTAGE_READ_EN_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_VOLTAGE_READ_EN_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MIN_VOLTAGE_THR_MASK (0x3FF00U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MIN_VOLTAGE_THR_SHIFT (8U)
+/*! VSEN_MIN_VOLTAGE_THR - SW programmed minimum threshold for sensor. Default */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MIN_VOLTAGE_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MIN_VOLTAGE_THR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MIN_VOLTAGE_THR_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MAX_VOLTAGE_THR_MASK (0x3FF00000U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MAX_VOLTAGE_THR_SHIFT (20U)
+/*! VSEN_MAX_VOLTAGE_THR - SW programmed maximum threshold for sensor. Default */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MAX_VOLTAGE_THR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MAX_VOLTAGE_THR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MAX_VOLTAGE_THR_MASK)
+/*! @} */
+
+/*! @name VSEN_CTRL_3_REG_2 - VSEN3 Controller Output status register */
+/*! @{ */
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERR_VOLTAGE_PVALUE_MASK (0x3FFU)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERR_VOLTAGE_PVALUE_SHIFT (0U)
+/*! VSEN_ERR_VOLTAGE_PVALUE - The sensor reading captured at the time of *sen_error event -> this is for SW */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERR_VOLTAGE_PVALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERR_VOLTAGE_PVALUE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERR_VOLTAGE_PVALUE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_VOLTAGE_VALUE_MASK (0xFFC00U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_VOLTAGE_VALUE_SHIFT (10U)
+/*! VSEN_VOLTAGE_VALUE - reading from last sensor sampling available for SW to read out */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_VOLTAGE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_VOLTAGE_VALUE_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_VOLTAGE_VALUE_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERROR_MASK (0x100000U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERROR_SHIFT (20U)
+/*! VSEN_ERROR - Error indication from sensor */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERROR_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSEN_ERROR_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_MASK (0x200000U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_SHIFT (21U)
+/*! SW_ON_DEMAND_VSEN_RD_DONE_STATUS - Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode. */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_2_SW_ON_DEMAND_VSEN_RD_DONE_STATUS_MASK)
+
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSENDC_DEBUG_MASK (0xFFC00000U)
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSENDC_DEBUG_SHIFT (22U)
+/*! VSENDC_DEBUG - Field description: */
+#define SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSENDC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSENDC_DEBUG_SHIFT)) & SENSOR_CTRL_VSEN_CTRL_3_REG_2_VSENDC_DEBUG_MASK)
+/*! @} */
+
+/*! @name VGLITCH_CTRL_REG_1 - Voltage Glitch sensor controller configuration */
+/*! @{ */
+
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_SW_ENABLE_MASK (0x2U)
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_SW_ENABLE_SHIFT (1U)
+/*! VGLITCH_SW_ENABLE - sw enable from CPU for Glitch Sensor */
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_SW_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_SW_ENABLE_SHIFT)) & SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_SW_ENABLE_MASK)
+
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_TESMODE_MASK (0x4U)
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_TESMODE_SHIFT (2U)
+/*! VGLITCH_TESMODE - Testmode enable from CPU for Glitch Sensor */
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_TESMODE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_TESMODE_SHIFT)) & SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_TESMODE_MASK)
+
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_ERROR_MASK (0x10U)
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_ERROR_SHIFT (4U)
+/*! VGLITCH_ERROR - Error indication from Voltage glitch sensor */
+#define SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_ERROR_SHIFT)) & SENSOR_CTRL_VGLITCH_CTRL_REG_1_VGLITCH_ERROR_MASK)
+/*! @} */
+
+/*! @name MISC_CTRL_REG - Miscellaneous controls */
+/*! @{ */
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_ENABLE_MASK (0x1U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_ENABLE_SHIFT (0U)
+/*! TIMER_1_ENABLE - enables the timer for sensor to start counting */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_ENABLE_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_ENABLE_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_PERIOD_MASK (0xEU)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_PERIOD_SHIFT (1U)
+/*! TIMER_1_PERIOD - Pre defined sampling periods for this sensor */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_PERIOD_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_1_PERIOD_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_ENABLE_MASK (0x10U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_ENABLE_SHIFT (4U)
+/*! TIMER_2_ENABLE - enables the timer for sensor to start counting */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_ENABLE_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_ENABLE_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_PERIOD_MASK (0xE0U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_PERIOD_SHIFT (5U)
+/*! TIMER_2_PERIOD - Pre defined sampling periods for this sensor */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_PERIOD_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_2_PERIOD_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_ENABLE_MASK (0x100U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_ENABLE_SHIFT (8U)
+/*! TIMER_3_ENABLE - enables the timer for sensor to start counting */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_ENABLE_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_ENABLE_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_PERIOD_MASK (0xE00U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_PERIOD_SHIFT (9U)
+/*! TIMER_3_PERIOD - Pre defined sampling periods for this sensor */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_PERIOD_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_3_PERIOD_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_ENABLE_MASK (0x1000U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_ENABLE_SHIFT (12U)
+/*! TIMER_4_ENABLE - enables the timer for sensor to start counting */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_ENABLE_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_ENABLE_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_PERIOD_MASK (0xE000U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_PERIOD_SHIFT (13U)
+/*! TIMER_4_PERIOD - Pre defined sampling periods for this sensor */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_PERIOD_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_4_PERIOD_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_ENABLE_MASK (0x10000U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_ENABLE_SHIFT (16U)
+/*! TIMER_5_ENABLE - enables the timer for sensor to start counting */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_ENABLE_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_ENABLE_MASK)
+
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_PERIOD_MASK (0xE0000U)
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_PERIOD_SHIFT (17U)
+/*! TIMER_5_PERIOD - Pre defined sampling periods for this sensor */
+#define SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_PERIOD_SHIFT)) & SENSOR_CTRL_MISC_CTRL_REG_TIMER_5_PERIOD_MASK)
+/*! @} */
+
+/*! @name CFG_ERR_STATUS_REG - CFG ERROR Control */
+/*! @{ */
+
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_TB_SEL_MASK (0x7U)
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_TB_SEL_SHIFT (0U)
+/*! TB_SEL - Select Testbus that can go to GPIO */
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_TB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_CFG_ERR_STATUS_REG_TB_SEL_SHIFT)) & SENSOR_CTRL_CFG_ERR_STATUS_REG_TB_SEL_MASK)
+
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_CFG_ERR_MASK (0x100U)
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_CFG_ERR_SHIFT (8U)
+/*! SEC_CFG_ERR - Indication to SW that Sensor config Registers are has Errors. Original and shadow registers are not same */
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_CFG_ERR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_CFG_ERR_SHIFT)) & SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_CFG_ERR_MASK)
+
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_SEN_ERR_MASK_MASK (0x7F0000U)
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_SEN_ERR_MASK_SHIFT (16U)
+/*! SEC_SEN_ERR_MASK - SW Mask control bit for sensor Error. */
+#define SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_SEN_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_SEN_ERR_MASK_SHIFT)) & SENSOR_CTRL_CFG_ERR_STATUS_REG_SEC_SEN_ERR_MASK_MASK)
+/*! @} */
+
+/*! @name SEN_CLR_REG - CFG ERROR Control */
+/*! @{ */
+
+#define SENSOR_CTRL_SEN_CLR_REG_SEN_ERR_CLR_MASK (0x7FU)
+#define SENSOR_CTRL_SEN_CLR_REG_SEN_ERR_CLR_SHIFT (0U)
+/*! SEN_ERR_CLR - SW control to clear error status of Sensor. */
+#define SENSOR_CTRL_SEN_CLR_REG_SEN_ERR_CLR(x)   (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_SEN_CLR_REG_SEN_ERR_CLR_SHIFT)) & SENSOR_CTRL_SEN_CLR_REG_SEN_ERR_CLR_MASK)
+
+#define SENSOR_CTRL_SEN_CLR_REG_SEN_RD_DONE_CLR_MASK (0x1F00U)
+#define SENSOR_CTRL_SEN_CLR_REG_SEN_RD_DONE_CLR_SHIFT (8U)
+/*! SEN_RD_DONE_CLR - SW control to clear read done status bit of Sensor in case of trigger mode set to on demand. */
+#define SENSOR_CTRL_SEN_CLR_REG_SEN_RD_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_SEN_CLR_REG_SEN_RD_DONE_CLR_SHIFT)) & SENSOR_CTRL_SEN_CLR_REG_SEN_RD_DONE_CLR_MASK)
+/*! @} */
+
+/*! @name SEC_ECO_REG - ECO Bits */
+/*! @{ */
+
+#define SENSOR_CTRL_SEC_ECO_REG_ECO_BITS_MASK    (0xFFFFFFFFU)
+#define SENSOR_CTRL_SEC_ECO_REG_ECO_BITS_SHIFT   (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define SENSOR_CTRL_SEC_ECO_REG_ECO_BITS(x)      (((uint32_t)(((uint32_t)(x)) << SENSOR_CTRL_SEC_ECO_REG_ECO_BITS_SHIFT)) & SENSOR_CTRL_SEC_ECO_REG_ECO_BITS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SENSOR_CTRL_Register_Masks */
+
+
+/* SENSOR_CTRL - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SENSOR_CTRL base address */
+  #define SENSOR_CTRL_BASE                         (0x55004000u)
+  /** Peripheral SENSOR_CTRL base address */
+  #define SENSOR_CTRL_BASE_NS                      (0x45004000u)
+  /** Peripheral SENSOR_CTRL base pointer */
+  #define SENSOR_CTRL                              ((SENSOR_CTRL_Type *)SENSOR_CTRL_BASE)
+  /** Peripheral SENSOR_CTRL base pointer */
+  #define SENSOR_CTRL_NS                           ((SENSOR_CTRL_Type *)SENSOR_CTRL_BASE_NS)
+  /** Array initializer of SENSOR_CTRL peripheral base addresses */
+  #define SENSOR_CTRL_BASE_ADDRS                   { SENSOR_CTRL_BASE }
+  /** Array initializer of SENSOR_CTRL peripheral base pointers */
+  #define SENSOR_CTRL_BASE_PTRS                    { SENSOR_CTRL }
+  /** Array initializer of SENSOR_CTRL peripheral base addresses */
+  #define SENSOR_CTRL_BASE_ADDRS_NS                { SENSOR_CTRL_BASE_NS }
+  /** Array initializer of SENSOR_CTRL peripheral base pointers */
+  #define SENSOR_CTRL_BASE_PTRS_NS                 { SENSOR_CTRL_NS }
+#else
+  /** Peripheral SENSOR_CTRL base address */
+  #define SENSOR_CTRL_BASE                         (0x45004000u)
+  /** Peripheral SENSOR_CTRL base pointer */
+  #define SENSOR_CTRL                              ((SENSOR_CTRL_Type *)SENSOR_CTRL_BASE)
+  /** Array initializer of SENSOR_CTRL peripheral base addresses */
+  #define SENSOR_CTRL_BASE_ADDRS                   { SENSOR_CTRL_BASE }
+  /** Array initializer of SENSOR_CTRL peripheral base pointers */
+  #define SENSOR_CTRL_BASE_PTRS                    { SENSOR_CTRL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SENSOR_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SOCCIU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SOCCIU_Peripheral_Access_Layer SOCCIU Peripheral Access Layer
+ * @{
+ */
+
+/** SOCCIU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PAD_CONFIG0;                       /**< ", offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PAD_PWRDOWN_CTRL0;                 /**< Pad Power-down Control 0, offset: 0x8 */
+  __IO uint32_t PAD_PWRDOWN_CTRL1;                 /**< Pad Power-down Control 1, offset: 0xC */
+  __IO uint32_t PAD_PWRDOWN_CTRL2;                 /**< Pad Power-down Control 2, offset: 0x10 */
+  __IO uint32_t PAD_PWRDOWN_CTRL3;                 /**< Pad Power-down Control 3, offset: 0x14 */
+  __IO uint32_t PAD_PWRDOWN_CTRL4;                 /**< Pad Power-down Control 4, offset: 0x18 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PAD_PWRDOWN_CTRL5;                 /**< Pad Power-down Control 5, offset: 0x2C */
+  __IO uint32_t PAD_RF_SW_SLP_CONFIG;              /**< RF Switch Pad Sleep Mode Configuration, offset: 0x30 */
+  __IO uint32_t PAD_ATEST_SW_SLP_CONFIG;           /**< ATEST Pad Sleep Mode Configuration, offset: 0x34 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t SR_CONFIG0;                        /**< GPIO Slew Rate control, offset: 0x4C */
+  __IO uint32_t SR_CONFIG1;                        /**< GPIO Slew Rate control, offset: 0x50 */
+  __IO uint32_t SR_CONFIG2;                        /**< GPIO Slew Rate control, offset: 0x54 */
+  __IO uint32_t SR_CONFIG3;                        /**< GPIO Slew Rate control, offset: 0x58 */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t SR_CONFIG4;                        /**< GPIO Slew Rate control, offset: 0x64 */
+  __IO uint32_t PAD_WKUP0;                         /**< Pad Wakeup Mode Enable, offset: 0x68 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t PAD_PU_PD_EN0;                     /**< Pad Pull-up Pull-down Enable1, offset: 0x70 */
+  __IO uint32_t PAD_PU_PD_EN1;                     /**< Pad Pull-up Pull-down Enable2, offset: 0x74 */
+  __IO uint32_t PAD_PU_PD_EN2;                     /**< Pad Pull-up Pull-down Enable2, offset: 0x78 */
+  __IO uint32_t PAD_PU_PD_EN3;                     /**< Pad Pull-up Pull-down Enable2, offset: 0x7C */
+       uint8_t RESERVED_5[8];
+  __IO uint32_t PAD_PU_PD_EN4;                     /**< Pad Pull-up Pull-down Enable2, offset: 0x88 */
+  __IO uint32_t PAD_SLP_EN0;                       /**< Pad Sleep Mode Enable, offset: 0x8C */
+  __IO uint32_t PAD_SLP_EN1;                       /**< Pad Sleep Mode Enable, offset: 0x90 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t PAD_SLP_VAL0;                      /**< Pad Sleep Mode Value, offset: 0x98 */
+  __IO uint32_t PAD_SLP_VAL1;                      /**< Pad Sleep Mode Value, offset: 0x9C */
+       uint8_t RESERVED_7[96];
+  __I  uint32_t PSW_VD2_RDY0;                      /**< Power Switch VD2_RDY Status, offset: 0x100 */
+  __IO uint32_t PSW_ECO_CTRL;                      /**< Power Switch ECO Control, offset: 0x104 */
+  __IO uint32_t CLK_SW;                            /**< Clock Controls for SOC_CLK_TOP, offset: 0x108 */
+  __IO uint32_t RST_SW;                            /**< Reset Controls for SOC_RESET_GEN, offset: 0x10C */
+       uint8_t RESERVED_8[4];
+  __I  uint32_t CHIP_INFO;                         /**< Chip Information, offset: 0x114 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t MCI_POWER_MODE_STATUS;             /**< MCI POWER MODE Status, offset: 0x134 */
+  __I  uint32_t PSW_VD2_RDY1;                      /**< Power Switch VD2_RDY Status, offset: 0x138 */
+       uint8_t RESERVED_10[4];
+  __IO uint32_t WLAN_POWER_STATUS;                 /**< WLAN POWER Status, offset: 0x140 */
+  __IO uint32_t BLE_POWER_STATUS;                  /**< BLE POWER Status, offset: 0x144 */
+       uint8_t RESERVED_11[184];
+  __IO uint32_t PAD_VREG_VSENSOR_CTRL;             /**< Vsensor and Vreg Pad Control, offset: 0x200 */
+       uint8_t RESERVED_12[4];
+  __IO uint32_t PAD_RF_VREG_VSENSOR_CTRL;          /**< RF Vsensor and Vreg Pad Control, offset: 0x208 */
+       uint8_t RESERVED_13[16];
+  __IO uint32_t PAD_SD_VREG_VSENSOR_CTRL;          /**< SD Vsensor and Vreg Pad Control, offset: 0x21C */
+       uint8_t RESERVED_14[348];
+  __IO uint32_t PAD_ECO_CTRL;                      /**< Pad ECO Control, offset: 0x37C */
+       uint8_t RESERVED_15[164];
+  __IO uint32_t TST_TSTBUS_CTRL1;                  /**< Testbus Mux Control1, offset: 0x424 */
+  __IO uint32_t TST_TSTBUS_CTRL2;                  /**< Testbus Mux Control2, offset: 0x428 */
+       uint8_t RESERVED_16[4];
+  __I  uint32_t TST_CTRL;                          /**< Test Control, offset: 0x430 */
+       uint8_t RESERVED_17[72];
+  __IO uint32_t TST_ECO_CTRL;                      /**< Test ECO Control, offset: 0x47C */
+       uint8_t RESERVED_18[8];
+  __IO uint32_t DRO_CTRL;                          /**< DRO Control, offset: 0x488 */
+  __I  uint32_t DRO_1_2_CNT;                       /**< DRO1 and DRO2 Counter Read back, offset: 0x48C */
+  __I  uint32_t DRO_3_CNT;                         /**< DRO3 Counter Read back, offset: 0x490 */
+       uint8_t RESERVED_19[4];
+  __IO uint32_t DRO_PAR_SEL;                       /**< DRO Parallel Counter Selection, offset: 0x498 */
+  __IO uint32_t CLK_SOCCLK_CTRL;                   /**< SOC Clock Control, offset: 0x49C */
+       uint8_t RESERVED_20[96];
+  __IO uint32_t PAD_SLP_PU_PD_DIS0;                /**< Pad Sleep Pullup and Pulldown Disable1, offset: 0x500 */
+  __IO uint32_t PAD_SLP_PU_PD_DIS1;                /**< Pad Sleep Pullup and Pulldown Disable2, offset: 0x504 */
+       uint8_t RESERVED_21[8];
+  __IO uint32_t PAD_SLP_PU_PD_DIS2;                /**< Pad Sleep Pullup and Pulldown Disable4, offset: 0x510 */
+  __IO uint32_t PAD_GPIO;                          /**< GPIO Enable, offset: 0x514 */
+       uint8_t RESERVED_22[32];
+  __IO uint32_t MCI_IOMUX_EN0;                     /**< mci_iomux_enable control for GPIO[31:28] and GPIO[21:0], offset: 0x538 */
+  __IO uint32_t MCI_IOMUX_EN1;                     /**< mci_iomux_enable control for GPIO[63:32], offset: 0x53C */
+       uint8_t RESERVED_23[840];
+  __IO uint32_t CAU_CTRL;                          /**< CAU Control, offset: 0x888 */
+       uint8_t RESERVED_24[24];
+  __I  uint32_t SYSPLL_CTRL;                       /**< SYSPLL Control, offset: 0x8A4 */
+} SOCCIU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SOCCIU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SOCCIU_Register_Masks SOCCIU Register Masks
+ * @{
+ */
+
+/*! @name PAD_CONFIG0 - " */
+/*! @{ */
+
+#define SOCCIU_PAD_CONFIG0_ALL_PADS_TRISTATE_EN_MASK (0x1U)
+#define SOCCIU_PAD_CONFIG0_ALL_PADS_TRISTATE_EN_SHIFT (0U)
+/*! ALL_PADS_TRISTATE_EN - Enable/disable Control for Pad Tristate */
+#define SOCCIU_PAD_CONFIG0_ALL_PADS_TRISTATE_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_ALL_PADS_TRISTATE_EN_SHIFT)) & SOCCIU_PAD_CONFIG0_ALL_PADS_TRISTATE_EN_MASK)
+
+#define SOCCIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_MASK (0x2U)
+#define SOCCIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_SHIFT (1U)
+/*! PAD_PWRDOWN_LATCH - Enables the pd_sel latching */
+#define SOCCIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_SHIFT)) & SOCCIU_PAD_CONFIG0_PAD_PWRDOWN_LATCH_MASK)
+
+#define SOCCIU_PAD_CONFIG0_RF_CNTL0_ATEST_EN_MASK (0x8U)
+#define SOCCIU_PAD_CONFIG0_RF_CNTL0_ATEST_EN_SHIFT (3U)
+/*! RF_CNTL0_ATEST_EN - RF_CNTL0 pad ATEST mode Enable */
+#define SOCCIU_PAD_CONFIG0_RF_CNTL0_ATEST_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_RF_CNTL0_ATEST_EN_SHIFT)) & SOCCIU_PAD_CONFIG0_RF_CNTL0_ATEST_EN_MASK)
+
+#define SOCCIU_PAD_CONFIG0_RF_CNTL1_ATEST_EN_MASK (0x10U)
+#define SOCCIU_PAD_CONFIG0_RF_CNTL1_ATEST_EN_SHIFT (4U)
+/*! RF_CNTL1_ATEST_EN - RF_CNTL1 pad ATEST mode Enable */
+#define SOCCIU_PAD_CONFIG0_RF_CNTL1_ATEST_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_RF_CNTL1_ATEST_EN_SHIFT)) & SOCCIU_PAD_CONFIG0_RF_CNTL1_ATEST_EN_MASK)
+
+#define SOCCIU_PAD_CONFIG0_RF_CNTL2_ATEST_EN_MASK (0x20U)
+#define SOCCIU_PAD_CONFIG0_RF_CNTL2_ATEST_EN_SHIFT (5U)
+/*! RF_CNTL2_ATEST_EN - RF_CNTL2 pad ATEST mode Enable */
+#define SOCCIU_PAD_CONFIG0_RF_CNTL2_ATEST_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_RF_CNTL2_ATEST_EN_SHIFT)) & SOCCIU_PAD_CONFIG0_RF_CNTL2_ATEST_EN_MASK)
+
+#define SOCCIU_PAD_CONFIG0_RF_CNTL3_ATEST_EN_MASK (0x40U)
+#define SOCCIU_PAD_CONFIG0_RF_CNTL3_ATEST_EN_SHIFT (6U)
+/*! RF_CNTL3_ATEST_EN - RF_CNTL3 pad ATEST mode Enable */
+#define SOCCIU_PAD_CONFIG0_RF_CNTL3_ATEST_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_RF_CNTL3_ATEST_EN_SHIFT)) & SOCCIU_PAD_CONFIG0_RF_CNTL3_ATEST_EN_MASK)
+
+#define SOCCIU_PAD_CONFIG0_ATEST_EN_3_0_MASK     (0x780U)
+#define SOCCIU_PAD_CONFIG0_ATEST_EN_3_0_SHIFT    (7U)
+/*! ATEST_EN_3_0 - ATEST Pin Force Bits */
+#define SOCCIU_PAD_CONFIG0_ATEST_EN_3_0(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_ATEST_EN_3_0_SHIFT)) & SOCCIU_PAD_CONFIG0_ATEST_EN_3_0_MASK)
+
+#define SOCCIU_PAD_CONFIG0_PAD_XOSC_EN_SEL_MASK  (0x800U)
+#define SOCCIU_PAD_CONFIG0_PAD_XOSC_EN_SEL_SHIFT (11U)
+/*! PAD_XOSC_EN_SEL - PAD XOSC Enable Control */
+#define SOCCIU_PAD_CONFIG0_PAD_XOSC_EN_SEL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_PAD_XOSC_EN_SEL_SHIFT)) & SOCCIU_PAD_CONFIG0_PAD_XOSC_EN_SEL_MASK)
+
+#define SOCCIU_PAD_CONFIG0_ATEST_DIS_STDALONE_MODE_3_0_MASK (0xF000U)
+#define SOCCIU_PAD_CONFIG0_ATEST_DIS_STDALONE_MODE_3_0_SHIFT (12U)
+/*! ATEST_DIS_STDALONE_MODE_3_0 - ATEST Pin Force disable Bits in standalone mode */
+#define SOCCIU_PAD_CONFIG0_ATEST_DIS_STDALONE_MODE_3_0(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_ATEST_DIS_STDALONE_MODE_3_0_SHIFT)) & SOCCIU_PAD_CONFIG0_ATEST_DIS_STDALONE_MODE_3_0_MASK)
+
+#define SOCCIU_PAD_CONFIG0_RFU_STDALONE_MASK     (0x40000U)
+#define SOCCIU_PAD_CONFIG0_RFU_STDALONE_SHIFT    (18U)
+/*! RFU_STDALONE - RFU Standalone */
+#define SOCCIU_PAD_CONFIG0_RFU_STDALONE(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_RFU_STDALONE_SHIFT)) & SOCCIU_PAD_CONFIG0_RFU_STDALONE_MASK)
+
+#define SOCCIU_PAD_CONFIG0_CAU_STDALONE_MASK     (0x80000U)
+#define SOCCIU_PAD_CONFIG0_CAU_STDALONE_SHIFT    (19U)
+/*! CAU_STDALONE - CAU Standalone */
+#define SOCCIU_PAD_CONFIG0_CAU_STDALONE(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_CAU_STDALONE_SHIFT)) & SOCCIU_PAD_CONFIG0_CAU_STDALONE_MASK)
+
+#define SOCCIU_PAD_CONFIG0_BRF_STDALONE_MASK     (0x100000U)
+#define SOCCIU_PAD_CONFIG0_BRF_STDALONE_SHIFT    (20U)
+/*! BRF_STDALONE - BRF Standalone */
+#define SOCCIU_PAD_CONFIG0_BRF_STDALONE(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_BRF_STDALONE_SHIFT)) & SOCCIU_PAD_CONFIG0_BRF_STDALONE_MASK)
+
+#define SOCCIU_PAD_CONFIG0_BRF_W3_SOC_MASTER_SEL_MASK (0x400000U)
+#define SOCCIU_PAD_CONFIG0_BRF_W3_SOC_MASTER_SEL_SHIFT (22U)
+/*! BRF_W3_SOC_MASTER_SEL - BRF 3-Wire SoC Master Select */
+#define SOCCIU_PAD_CONFIG0_BRF_W3_SOC_MASTER_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_BRF_W3_SOC_MASTER_SEL_SHIFT)) & SOCCIU_PAD_CONFIG0_BRF_W3_SOC_MASTER_SEL_MASK)
+
+#define SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_MASK (0x1000000U)
+#define SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_SHIFT (24U)
+/*! BT_DBG_UART_MODE - BT Debug Uart Mode */
+#define SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_SHIFT)) & SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_MASK)
+
+#define SOCCIU_PAD_CONFIG0_WLAN_DBG_UART_MODE_4PIN_MASK (0x2000000U)
+#define SOCCIU_PAD_CONFIG0_WLAN_DBG_UART_MODE_4PIN_SHIFT (25U)
+/*! WLAN_DBG_UART_MODE_4PIN - WLAN 4 Pin Debug Uart Mode */
+#define SOCCIU_PAD_CONFIG0_WLAN_DBG_UART_MODE_4PIN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_WLAN_DBG_UART_MODE_4PIN_SHIFT)) & SOCCIU_PAD_CONFIG0_WLAN_DBG_UART_MODE_4PIN_MASK)
+
+#define SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_4PIN_MASK (0x4000000U)
+#define SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_4PIN_SHIFT (26U)
+/*! BT_DBG_UART_MODE_4PIN - BT 4 pin Debug Uart Mode */
+#define SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_4PIN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_4PIN_SHIFT)) & SOCCIU_PAD_CONFIG0_BT_DBG_UART_MODE_4PIN_MASK)
+
+#define SOCCIU_PAD_CONFIG0_TRACE_PORT_MODE_CPU_MASK (0x10000000U)
+#define SOCCIU_PAD_CONFIG0_TRACE_PORT_MODE_CPU_SHIFT (28U)
+/*! TRACE_PORT_MODE_CPU - Trace port mode enable */
+#define SOCCIU_PAD_CONFIG0_TRACE_PORT_MODE_CPU(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_TRACE_PORT_MODE_CPU_SHIFT)) & SOCCIU_PAD_CONFIG0_TRACE_PORT_MODE_CPU_MASK)
+
+#define SOCCIU_PAD_CONFIG0_LED_MODE_MASK         (0x20000000U)
+#define SOCCIU_PAD_CONFIG0_LED_MODE_SHIFT        (29U)
+/*! LED_MODE - to enable disable led mode */
+#define SOCCIU_PAD_CONFIG0_LED_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_LED_MODE_SHIFT)) & SOCCIU_PAD_CONFIG0_LED_MODE_MASK)
+
+#define SOCCIU_PAD_CONFIG0_SD_D3_PU_CTRL_MASK    (0x40000000U)
+#define SOCCIU_PAD_CONFIG0_SD_D3_PU_CTRL_SHIFT   (30U)
+/*! SD_D3_PU_CTRL - SD D3 PU Control function */
+#define SOCCIU_PAD_CONFIG0_SD_D3_PU_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_CONFIG0_SD_D3_PU_CTRL_SHIFT)) & SOCCIU_PAD_CONFIG0_SD_D3_PU_CTRL_MASK)
+/*! @} */
+
+/*! @name PAD_PWRDOWN_CTRL0 - Pad Power-down Control 0 */
+/*! @{ */
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO0_PD_SEL_MASK (0x7U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO0_PD_SEL_SHIFT (0U)
+/*! GPIO0_PD_SEL - Power down output value for GPIO[0] pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO0_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO0_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO0_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO1_PD_SEL_MASK (0x70U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO1_PD_SEL_SHIFT (4U)
+/*! GPIO1_PD_SEL - Power Down Output Value for GPIO[1] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO1_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO1_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO1_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO2_PD_SEL_MASK (0x700U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO2_PD_SEL_SHIFT (8U)
+/*! GPIO2_PD_SEL - Power Down Output Value for GPIO[2] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO2_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO2_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO2_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO3_PD_SEL_MASK (0x7000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO3_PD_SEL_SHIFT (12U)
+/*! GPIO3_PD_SEL - Power Down Output Value for GPIO[3] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO3_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO3_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO3_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO4_PD_SEL_MASK (0x70000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO4_PD_SEL_SHIFT (16U)
+/*! GPIO4_PD_SEL - Power Down Output Value for GPIO[4] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO4_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO4_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO4_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO5_PD_SEL_MASK (0x700000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO5_PD_SEL_SHIFT (20U)
+/*! GPIO5_PD_SEL - Power Down Output Value for GPIO[5] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO5_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO5_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO5_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO6_PD_SEL_MASK (0x7000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO6_PD_SEL_SHIFT (24U)
+/*! GPIO6_PD_SEL - Power Down Output Value for GPIO[6] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO6_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO6_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO6_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO7_PD_SEL_MASK (0x70000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO7_PD_SEL_SHIFT (28U)
+/*! GPIO7_PD_SEL - Power Down Output Value for GPIO[7] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL0_GPIO7_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL0_GPIO7_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL0_GPIO7_PD_SEL_MASK)
+/*! @} */
+
+/*! @name PAD_PWRDOWN_CTRL1 - Pad Power-down Control 1 */
+/*! @{ */
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO8_PD_SEL_MASK (0x7U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO8_PD_SEL_SHIFT (0U)
+/*! GPIO8_PD_SEL - Power Down Output Value for GPIO[8] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO8_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO8_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO8_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO9_PD_SEL_MASK (0x70U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO9_PD_SEL_SHIFT (4U)
+/*! GPIO9_PD_SEL - Power Down Output Value for GPIO[9] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO9_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO9_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO9_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO10_PD_SEL_MASK (0x700U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO10_PD_SEL_SHIFT (8U)
+/*! GPIO10_PD_SEL - Power Down Output Value for GPIO[10] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO10_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO10_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO10_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO11_PD_SEL_MASK (0x7000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO11_PD_SEL_SHIFT (12U)
+/*! GPIO11_PD_SEL - Power Down Output Value for GPIO[11] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO11_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO11_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO11_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO12_PD_SEL_MASK (0x70000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO12_PD_SEL_SHIFT (16U)
+/*! GPIO12_PD_SEL - Power Down Output Value for GPIO[12] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO12_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO12_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO12_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO13_PD_SEL_MASK (0x700000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO13_PD_SEL_SHIFT (20U)
+/*! GPIO13_PD_SEL - Power Down Output Value for GPIO[13] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO13_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO13_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO13_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO14_PD_SEL_MASK (0x7000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO14_PD_SEL_SHIFT (24U)
+/*! GPIO14_PD_SEL - Power Down Output Value for GPIO[14] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO14_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO14_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO14_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO21_PD_SEL_MASK (0x70000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO21_PD_SEL_SHIFT (28U)
+/*! GPIO21_PD_SEL - Power Down Output Value for GPIO[21] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL1_GPIO21_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL1_GPIO21_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL1_GPIO21_PD_SEL_MASK)
+/*! @} */
+
+/*! @name PAD_PWRDOWN_CTRL2 - Pad Power-down Control 2 */
+/*! @{ */
+
+#define SOCCIU_PAD_PWRDOWN_CTRL2_GPIO42_PD_SEL_MASK (0x7000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL2_GPIO42_PD_SEL_SHIFT (24U)
+/*! GPIO42_PD_SEL - Power Down Output Value for GPIO[42] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL2_GPIO42_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL2_GPIO42_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL2_GPIO42_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL2_GPIO43_PD_SEL_MASK (0x70000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL2_GPIO43_PD_SEL_SHIFT (28U)
+/*! GPIO43_PD_SEL - Power Down Output Value for GPIO[43] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL2_GPIO43_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL2_GPIO43_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL2_GPIO43_PD_SEL_MASK)
+/*! @} */
+
+/*! @name PAD_PWRDOWN_CTRL3 - Pad Power-down Control 3 */
+/*! @{ */
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO44_PD_SEL_MASK (0x7U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO44_PD_SEL_SHIFT (0U)
+/*! GPIO44_PD_SEL - Power Down Output Value for GPIO[44] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO44_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO44_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO44_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO45_PD_SEL_MASK (0x70U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO45_PD_SEL_SHIFT (4U)
+/*! GPIO45_PD_SEL - Power Down Output Value for GPIO[45] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO45_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO45_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO45_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO46_PD_SEL_MASK (0x700U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO46_PD_SEL_SHIFT (8U)
+/*! GPIO46_PD_SEL - Power Down Output Value for GPIO[46] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO46_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO46_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO46_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO47_PD_SEL_MASK (0x7000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO47_PD_SEL_SHIFT (12U)
+/*! GPIO47_PD_SEL - Power Down Output Value for GPIO[47] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO47_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO47_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO47_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO48_PD_SEL_MASK (0x70000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO48_PD_SEL_SHIFT (16U)
+/*! GPIO48_PD_SEL - Power Down Output Value for GPIO[48] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO48_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO48_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO48_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO49_PD_SEL_MASK (0x700000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO49_PD_SEL_SHIFT (20U)
+/*! GPIO49_PD_SEL - Power Down Output Value for GPIO[49] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO49_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO49_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO49_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO50_PD_SEL_MASK (0x7000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO50_PD_SEL_SHIFT (24U)
+/*! GPIO50_PD_SEL - Power Down Output Value for GPIO[50] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO50_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO50_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO50_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO51_PD_SEL_MASK (0x70000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO51_PD_SEL_SHIFT (28U)
+/*! GPIO51_PD_SEL - Power Down Output Value for GPIO[51] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL3_GPIO51_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL3_GPIO51_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL3_GPIO51_PD_SEL_MASK)
+/*! @} */
+
+/*! @name PAD_PWRDOWN_CTRL4 - Pad Power-down Control 4 */
+/*! @{ */
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO52_PD_SEL_MASK (0x7U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO52_PD_SEL_SHIFT (0U)
+/*! GPIO52_PD_SEL - Power Down Output Value for GPIO[52] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO52_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO52_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO52_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO53_PD_SEL_MASK (0x70U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO53_PD_SEL_SHIFT (4U)
+/*! GPIO53_PD_SEL - Power Down Output Value for GPIO[53] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO53_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO53_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO53_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO54_PD_SEL_MASK (0x700U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO54_PD_SEL_SHIFT (8U)
+/*! GPIO54_PD_SEL - Power Down Output Value for GPIO[54] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO54_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO54_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO54_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO55_PD_SEL_MASK (0x7000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO55_PD_SEL_SHIFT (12U)
+/*! GPIO55_PD_SEL - Power Down Output Value for GPIO[55] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO55_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO55_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO55_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO56_PD_SEL_MASK (0x70000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO56_PD_SEL_SHIFT (16U)
+/*! GPIO56_PD_SEL - Power Down Output Value for GPIO[56] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO56_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO56_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO56_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO57_PD_SEL_MASK (0x700000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO57_PD_SEL_SHIFT (20U)
+/*! GPIO57_PD_SEL - Power Down Output Value for GPIO[57] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO57_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO57_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO57_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO58_PD_SEL_MASK (0x7000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO58_PD_SEL_SHIFT (24U)
+/*! GPIO58_PD_SEL - Power Down Output Value for GPIO[58] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO58_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO58_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO58_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO59_PD_SEL_MASK (0x70000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO59_PD_SEL_SHIFT (28U)
+/*! GPIO59_PD_SEL - Power Down Output Value for GPIO[59] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL4_GPIO59_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL4_GPIO59_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL4_GPIO59_PD_SEL_MASK)
+/*! @} */
+
+/*! @name PAD_PWRDOWN_CTRL5 - Pad Power-down Control 5 */
+/*! @{ */
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO60_PD_SEL_MASK (0x7U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO60_PD_SEL_SHIFT (0U)
+/*! GPIO60_PD_SEL - Power Down Output Value for GPIO[60] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO60_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_GPIO60_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_GPIO60_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO61_PD_SEL_MASK (0x70U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO61_PD_SEL_SHIFT (4U)
+/*! GPIO61_PD_SEL - Power Down Output Value for GPIO[61] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO61_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_GPIO61_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_GPIO61_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO62_PD_SEL_MASK (0x700U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO62_PD_SEL_SHIFT (8U)
+/*! GPIO62_PD_SEL - Power Down Output Value for GPIO[62] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO62_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_GPIO62_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_GPIO62_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO63_PD_SEL_MASK (0x7000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO63_PD_SEL_SHIFT (12U)
+/*! GPIO63_PD_SEL - Power Down Output Value for GPIO[63] Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_GPIO63_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_GPIO63_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_GPIO63_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL0_PD_SEL_MASK (0x70000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL0_PD_SEL_SHIFT (16U)
+/*! RF_CNTL0_PD_SEL - Power Down Output Value for rf_cntl0 Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL0_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL0_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL0_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL1_PD_SEL_MASK (0x700000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL1_PD_SEL_SHIFT (20U)
+/*! RF_CNTL1_PD_SEL - Power Down Output Value for rf_cntl1 Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL1_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL1_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL1_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL2_PD_SEL_MASK (0x7000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL2_PD_SEL_SHIFT (24U)
+/*! RF_CNTL2_PD_SEL - Power Down Output Value for rf_cntl2 Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL2_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL2_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL2_PD_SEL_MASK)
+
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL3_PD_SEL_MASK (0x70000000U)
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL3_PD_SEL_SHIFT (28U)
+/*! RF_CNTL3_PD_SEL - Power Down Output Value for rf_cntl3 Pad */
+#define SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL3_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL3_PD_SEL_SHIFT)) & SOCCIU_PAD_PWRDOWN_CTRL5_RF_CNTL3_PD_SEL_MASK)
+/*! @} */
+
+/*! @name PAD_RF_SW_SLP_CONFIG - RF Switch Pad Sleep Mode Configuration */
+/*! @{ */
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_EN_MASK (0x1U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_EN_SHIFT (0U)
+/*! RF_CNTL0_SLP_EN - RF_CNTL0 Sleep Force Enable */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_EN_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_EN_MASK)
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_EN_MASK (0x2U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_EN_SHIFT (1U)
+/*! RF_CNTL1_SLP_EN - RF_CNTL1 Sleep Force Enable */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_EN_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_EN_MASK)
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_EN_MASK (0x4U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_EN_SHIFT (2U)
+/*! RF_CNTL2_SLP_EN - RF_CNTL2 Sleep Force Enable */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_EN_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_EN_MASK)
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_EN_MASK (0x8U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_EN_SHIFT (3U)
+/*! RF_CNTL3_SLP_EN - RF_CNTL3 Sleep Force Enable */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_EN_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_EN_MASK)
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_VAL_MASK (0x10000U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_VAL_SHIFT (16U)
+/*! RF_CNTL0_SLP_VAL - RF_CTRL0 Sleep Value */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_VAL_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL0_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_VAL_MASK (0x20000U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_VAL_SHIFT (17U)
+/*! RF_CNTL1_SLP_VAL - RF_CTRL1 Sleep Value */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_VAL_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL1_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_VAL_MASK (0x40000U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_VAL_SHIFT (18U)
+/*! RF_CNTL2_SLP_VAL - RF_CTRL2 Sleep Value */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_VAL_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL2_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_VAL_MASK (0x80000U)
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_VAL_SHIFT (19U)
+/*! RF_CNTL3_SLP_VAL - RF_CTRL3 Sleep Value */
+#define SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_VAL_SHIFT)) & SOCCIU_PAD_RF_SW_SLP_CONFIG_RF_CNTL3_SLP_VAL_MASK)
+/*! @} */
+
+/*! @name PAD_ATEST_SW_SLP_CONFIG - ATEST Pad Sleep Mode Configuration */
+/*! @{ */
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_EN_MASK (0x1U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_EN_SHIFT (0U)
+/*! ATEST0_SLP_EN - ATEST0 Sleep Force Enable */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_EN_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_EN_MASK)
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_EN_MASK (0x2U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_EN_SHIFT (1U)
+/*! ATEST1_SLP_EN - ATEST1 Sleep Force Enable */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_EN_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_EN_MASK)
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_EN_MASK (0x4U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_EN_SHIFT (2U)
+/*! ATEST2_SLP_EN - ATEST2 Sleep Force Enable */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_EN_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_EN_MASK)
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_EN_MASK (0x8U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_EN_SHIFT (3U)
+/*! ATEST3_SLP_EN - ATEST3 Sleep Force Enable */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_EN_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_EN_MASK)
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_VAL_MASK (0x10000U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_VAL_SHIFT (16U)
+/*! ATEST0_SLP_VAL - ATEST0 Sleep Value */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_VAL_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST0_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_VAL_MASK (0x20000U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_VAL_SHIFT (17U)
+/*! ATEST1_SLP_VAL - ATEST1 Sleep Value */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_VAL_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST1_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_VAL_MASK (0x40000U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_VAL_SHIFT (18U)
+/*! ATEST2_SLP_VAL - ATEST2 Sleep Value */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_VAL_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST2_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_VAL_MASK (0x80000U)
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_VAL_SHIFT (19U)
+/*! ATEST3_SLP_VAL - ATEST3 Sleep Value */
+#define SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_VAL_SHIFT)) & SOCCIU_PAD_ATEST_SW_SLP_CONFIG_ATEST3_SLP_VAL_MASK)
+/*! @} */
+
+/*! @name SR_CONFIG0 - GPIO Slew Rate control */
+/*! @{ */
+
+#define SOCCIU_SR_CONFIG0_GPIO0_SR_MASK          (0x3U)
+#define SOCCIU_SR_CONFIG0_GPIO0_SR_SHIFT         (0U)
+/*! GPIO0_SR - Slew Rate Control for GPIO[0] */
+#define SOCCIU_SR_CONFIG0_GPIO0_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO0_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO0_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO1_SR_MASK          (0xCU)
+#define SOCCIU_SR_CONFIG0_GPIO1_SR_SHIFT         (2U)
+/*! GPIO1_SR - Slew Rate Control for GPIO[1] */
+#define SOCCIU_SR_CONFIG0_GPIO1_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO1_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO1_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO2_SR_MASK          (0x30U)
+#define SOCCIU_SR_CONFIG0_GPIO2_SR_SHIFT         (4U)
+/*! GPIO2_SR - Slew Rate Control for GPIO[2] */
+#define SOCCIU_SR_CONFIG0_GPIO2_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO2_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO2_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO3_SR_MASK          (0xC0U)
+#define SOCCIU_SR_CONFIG0_GPIO3_SR_SHIFT         (6U)
+/*! GPIO3_SR - Slew Rate Control for GPIO[3] */
+#define SOCCIU_SR_CONFIG0_GPIO3_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO3_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO3_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO4_SR_MASK          (0x300U)
+#define SOCCIU_SR_CONFIG0_GPIO4_SR_SHIFT         (8U)
+/*! GPIO4_SR - Slew Rate Control for GPIO[4] */
+#define SOCCIU_SR_CONFIG0_GPIO4_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO4_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO4_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO5_SR_MASK          (0xC00U)
+#define SOCCIU_SR_CONFIG0_GPIO5_SR_SHIFT         (10U)
+/*! GPIO5_SR - Slew Rate Control for GPIO[5] */
+#define SOCCIU_SR_CONFIG0_GPIO5_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO5_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO5_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO6_SR_MASK          (0x3000U)
+#define SOCCIU_SR_CONFIG0_GPIO6_SR_SHIFT         (12U)
+/*! GPIO6_SR - Slew Rate Control for GPIO[6] */
+#define SOCCIU_SR_CONFIG0_GPIO6_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO6_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO6_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO7_SR_MASK          (0xC000U)
+#define SOCCIU_SR_CONFIG0_GPIO7_SR_SHIFT         (14U)
+/*! GPIO7_SR - Slew Rate Control for GPIO[7] */
+#define SOCCIU_SR_CONFIG0_GPIO7_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO7_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO7_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO8_SR_MASK          (0x30000U)
+#define SOCCIU_SR_CONFIG0_GPIO8_SR_SHIFT         (16U)
+/*! GPIO8_SR - Slew Rate Control for GPIO[8] */
+#define SOCCIU_SR_CONFIG0_GPIO8_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO8_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO8_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO9_SR_MASK          (0xC0000U)
+#define SOCCIU_SR_CONFIG0_GPIO9_SR_SHIFT         (18U)
+/*! GPIO9_SR - Slew Rate Control for GPIO[9] */
+#define SOCCIU_SR_CONFIG0_GPIO9_SR(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO9_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO9_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO10_SR_MASK         (0x300000U)
+#define SOCCIU_SR_CONFIG0_GPIO10_SR_SHIFT        (20U)
+/*! GPIO10_SR - Slew Rate Control for GPIO[10] */
+#define SOCCIU_SR_CONFIG0_GPIO10_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO10_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO10_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO11_SR_MASK         (0xC00000U)
+#define SOCCIU_SR_CONFIG0_GPIO11_SR_SHIFT        (22U)
+/*! GPIO11_SR - Slew Rate Control for GPIO[11] */
+#define SOCCIU_SR_CONFIG0_GPIO11_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO11_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO11_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO12_SR_MASK         (0x3000000U)
+#define SOCCIU_SR_CONFIG0_GPIO12_SR_SHIFT        (24U)
+/*! GPIO12_SR - Slew Rate Control for GPIO[12] */
+#define SOCCIU_SR_CONFIG0_GPIO12_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO12_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO12_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO13_SR_MASK         (0xC000000U)
+#define SOCCIU_SR_CONFIG0_GPIO13_SR_SHIFT        (26U)
+/*! GPIO13_SR - Slew Rate Control for GPIO[13] */
+#define SOCCIU_SR_CONFIG0_GPIO13_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO13_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO13_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO14_SR_MASK         (0x30000000U)
+#define SOCCIU_SR_CONFIG0_GPIO14_SR_SHIFT        (28U)
+/*! GPIO14_SR - Slew Rate Control for GPIO[14] */
+#define SOCCIU_SR_CONFIG0_GPIO14_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO14_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO14_SR_MASK)
+
+#define SOCCIU_SR_CONFIG0_GPIO15_SR_MASK         (0xC0000000U)
+#define SOCCIU_SR_CONFIG0_GPIO15_SR_SHIFT        (30U)
+/*! GPIO15_SR - Slew Rate Control for GPIO[15] */
+#define SOCCIU_SR_CONFIG0_GPIO15_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG0_GPIO15_SR_SHIFT)) & SOCCIU_SR_CONFIG0_GPIO15_SR_MASK)
+/*! @} */
+
+/*! @name SR_CONFIG1 - GPIO Slew Rate control */
+/*! @{ */
+
+#define SOCCIU_SR_CONFIG1_GPIO16_SR_MASK         (0x3U)
+#define SOCCIU_SR_CONFIG1_GPIO16_SR_SHIFT        (0U)
+/*! GPIO16_SR - Slew Rate Control for GPIO[16] */
+#define SOCCIU_SR_CONFIG1_GPIO16_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO16_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO16_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO17_SR_MASK         (0xCU)
+#define SOCCIU_SR_CONFIG1_GPIO17_SR_SHIFT        (2U)
+/*! GPIO17_SR - Slew Rate Control for GPIO[17] */
+#define SOCCIU_SR_CONFIG1_GPIO17_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO17_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO17_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO18_SR_MASK         (0x30U)
+#define SOCCIU_SR_CONFIG1_GPIO18_SR_SHIFT        (4U)
+/*! GPIO18_SR - Slew Rate Control for GPIO[18] */
+#define SOCCIU_SR_CONFIG1_GPIO18_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO18_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO18_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO19_SR_MASK         (0xC0U)
+#define SOCCIU_SR_CONFIG1_GPIO19_SR_SHIFT        (6U)
+/*! GPIO19_SR - Slew Rate Control for GPIO[19] */
+#define SOCCIU_SR_CONFIG1_GPIO19_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO19_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO19_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO20_SR_MASK         (0x300U)
+#define SOCCIU_SR_CONFIG1_GPIO20_SR_SHIFT        (8U)
+/*! GPIO20_SR - Slew Rate Control for GPIO[20] */
+#define SOCCIU_SR_CONFIG1_GPIO20_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO20_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO20_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO21_SR_MASK         (0xC00U)
+#define SOCCIU_SR_CONFIG1_GPIO21_SR_SHIFT        (10U)
+/*! GPIO21_SR - Slew Rate Control for GPIO[21] */
+#define SOCCIU_SR_CONFIG1_GPIO21_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO21_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO21_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO28_SR_MASK         (0x3000000U)
+#define SOCCIU_SR_CONFIG1_GPIO28_SR_SHIFT        (24U)
+/*! GPIO28_SR - Slew Rate Control for GPIO[28] */
+#define SOCCIU_SR_CONFIG1_GPIO28_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO28_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO28_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO29_SR_MASK         (0xC000000U)
+#define SOCCIU_SR_CONFIG1_GPIO29_SR_SHIFT        (26U)
+/*! GPIO29_SR - Slew Rate Control for GPIO[29] */
+#define SOCCIU_SR_CONFIG1_GPIO29_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO29_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO29_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO30_SR_MASK         (0x30000000U)
+#define SOCCIU_SR_CONFIG1_GPIO30_SR_SHIFT        (28U)
+/*! GPIO30_SR - Slew Rate Control for GPIO[30] */
+#define SOCCIU_SR_CONFIG1_GPIO30_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO30_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO30_SR_MASK)
+
+#define SOCCIU_SR_CONFIG1_GPIO31_SR_MASK         (0xC0000000U)
+#define SOCCIU_SR_CONFIG1_GPIO31_SR_SHIFT        (30U)
+/*! GPIO31_SR - Slew Rate Control for GPIO[31] */
+#define SOCCIU_SR_CONFIG1_GPIO31_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG1_GPIO31_SR_SHIFT)) & SOCCIU_SR_CONFIG1_GPIO31_SR_MASK)
+/*! @} */
+
+/*! @name SR_CONFIG2 - GPIO Slew Rate control */
+/*! @{ */
+
+#define SOCCIU_SR_CONFIG2_GPIO32_SR_MASK         (0x3U)
+#define SOCCIU_SR_CONFIG2_GPIO32_SR_SHIFT        (0U)
+/*! GPIO32_SR - Slew Rate Control for GPIO[32] */
+#define SOCCIU_SR_CONFIG2_GPIO32_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO32_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO32_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO33_SR_MASK         (0xCU)
+#define SOCCIU_SR_CONFIG2_GPIO33_SR_SHIFT        (2U)
+/*! GPIO33_SR - Slew Rate Control for GPIO[33] */
+#define SOCCIU_SR_CONFIG2_GPIO33_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO33_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO33_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO34_SR_MASK         (0x30U)
+#define SOCCIU_SR_CONFIG2_GPIO34_SR_SHIFT        (4U)
+/*! GPIO34_SR - Slew Rate Control for GPIO[34] */
+#define SOCCIU_SR_CONFIG2_GPIO34_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO34_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO34_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO35_SR_MASK         (0xC0U)
+#define SOCCIU_SR_CONFIG2_GPIO35_SR_SHIFT        (6U)
+/*! GPIO35_SR - Slew Rate Control for GPIO[35] */
+#define SOCCIU_SR_CONFIG2_GPIO35_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO35_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO35_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO36_SR_MASK         (0x300U)
+#define SOCCIU_SR_CONFIG2_GPIO36_SR_SHIFT        (8U)
+/*! GPIO36_SR - Slew Rate Control for GPIO[36] */
+#define SOCCIU_SR_CONFIG2_GPIO36_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO36_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO36_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO37_SR_MASK         (0xC00U)
+#define SOCCIU_SR_CONFIG2_GPIO37_SR_SHIFT        (10U)
+/*! GPIO37_SR - Slew Rate Control for GPIO[37] */
+#define SOCCIU_SR_CONFIG2_GPIO37_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO37_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO37_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO38_SR_MASK         (0x3000U)
+#define SOCCIU_SR_CONFIG2_GPIO38_SR_SHIFT        (12U)
+/*! GPIO38_SR - Slew Rate Control for GPIO[38] */
+#define SOCCIU_SR_CONFIG2_GPIO38_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO38_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO38_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO39_SR_MASK         (0xC000U)
+#define SOCCIU_SR_CONFIG2_GPIO39_SR_SHIFT        (14U)
+/*! GPIO39_SR - Slew Rate Control for GPIO[39] */
+#define SOCCIU_SR_CONFIG2_GPIO39_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO39_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO39_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO40_SR_MASK         (0x30000U)
+#define SOCCIU_SR_CONFIG2_GPIO40_SR_SHIFT        (16U)
+/*! GPIO40_SR - Slew Rate Control for GPIO[40] */
+#define SOCCIU_SR_CONFIG2_GPIO40_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO40_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO40_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO41_SR_MASK         (0xC0000U)
+#define SOCCIU_SR_CONFIG2_GPIO41_SR_SHIFT        (18U)
+/*! GPIO41_SR - Slew Rate Control for GPIO[41] */
+#define SOCCIU_SR_CONFIG2_GPIO41_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO41_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO41_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO42_SR_MASK         (0x300000U)
+#define SOCCIU_SR_CONFIG2_GPIO42_SR_SHIFT        (20U)
+/*! GPIO42_SR - Slew Rate Control for GPIO[42] */
+#define SOCCIU_SR_CONFIG2_GPIO42_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO42_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO42_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO43_SR_MASK         (0xC00000U)
+#define SOCCIU_SR_CONFIG2_GPIO43_SR_SHIFT        (22U)
+/*! GPIO43_SR - Slew Rate Control for GPIO[43] */
+#define SOCCIU_SR_CONFIG2_GPIO43_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO43_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO43_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO44_SR_MASK         (0x3000000U)
+#define SOCCIU_SR_CONFIG2_GPIO44_SR_SHIFT        (24U)
+/*! GPIO44_SR - Slew Rate Control for GPIO[44] */
+#define SOCCIU_SR_CONFIG2_GPIO44_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO44_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO44_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO45_SR_MASK         (0xC000000U)
+#define SOCCIU_SR_CONFIG2_GPIO45_SR_SHIFT        (26U)
+/*! GPIO45_SR - Slew Rate Control for GPIO[45] */
+#define SOCCIU_SR_CONFIG2_GPIO45_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO45_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO45_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO46_SR_MASK         (0x30000000U)
+#define SOCCIU_SR_CONFIG2_GPIO46_SR_SHIFT        (28U)
+/*! GPIO46_SR - Slew Rate Control for GPIO[46] */
+#define SOCCIU_SR_CONFIG2_GPIO46_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO46_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO46_SR_MASK)
+
+#define SOCCIU_SR_CONFIG2_GPIO47_SR_MASK         (0xC0000000U)
+#define SOCCIU_SR_CONFIG2_GPIO47_SR_SHIFT        (30U)
+/*! GPIO47_SR - Slew Rate Control for GPIO[47] */
+#define SOCCIU_SR_CONFIG2_GPIO47_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG2_GPIO47_SR_SHIFT)) & SOCCIU_SR_CONFIG2_GPIO47_SR_MASK)
+/*! @} */
+
+/*! @name SR_CONFIG3 - GPIO Slew Rate control */
+/*! @{ */
+
+#define SOCCIU_SR_CONFIG3_GPIO48_SR_MASK         (0x3U)
+#define SOCCIU_SR_CONFIG3_GPIO48_SR_SHIFT        (0U)
+/*! GPIO48_SR - Slew Rate Control for GPIO[48] */
+#define SOCCIU_SR_CONFIG3_GPIO48_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO48_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO48_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO49_SR_MASK         (0xCU)
+#define SOCCIU_SR_CONFIG3_GPIO49_SR_SHIFT        (2U)
+/*! GPIO49_SR - Slew Rate Control for GPIO[49] */
+#define SOCCIU_SR_CONFIG3_GPIO49_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO49_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO49_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO50_SR_MASK         (0x30U)
+#define SOCCIU_SR_CONFIG3_GPIO50_SR_SHIFT        (4U)
+/*! GPIO50_SR - Slew Rate Control for GPIO[50] */
+#define SOCCIU_SR_CONFIG3_GPIO50_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO50_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO50_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO51_SR_MASK         (0xC0U)
+#define SOCCIU_SR_CONFIG3_GPIO51_SR_SHIFT        (6U)
+/*! GPIO51_SR - Slew Rate Control for GPIO[51] */
+#define SOCCIU_SR_CONFIG3_GPIO51_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO51_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO51_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO52_SR_MASK         (0x300U)
+#define SOCCIU_SR_CONFIG3_GPIO52_SR_SHIFT        (8U)
+/*! GPIO52_SR - Slew Rate Control for GPIO[52] */
+#define SOCCIU_SR_CONFIG3_GPIO52_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO52_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO52_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO53_SR_MASK         (0xC00U)
+#define SOCCIU_SR_CONFIG3_GPIO53_SR_SHIFT        (10U)
+/*! GPIO53_SR - Slew Rate Control for GPIO[53] */
+#define SOCCIU_SR_CONFIG3_GPIO53_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO53_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO53_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO54_SR_MASK         (0x3000U)
+#define SOCCIU_SR_CONFIG3_GPIO54_SR_SHIFT        (12U)
+/*! GPIO54_SR - Slew Rate Control for GPIO[54] */
+#define SOCCIU_SR_CONFIG3_GPIO54_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO54_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO54_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO55_SR_MASK         (0xC000U)
+#define SOCCIU_SR_CONFIG3_GPIO55_SR_SHIFT        (14U)
+/*! GPIO55_SR - Slew Rate Control for GPIO[55] */
+#define SOCCIU_SR_CONFIG3_GPIO55_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO55_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO55_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO56_SR_MASK         (0x30000U)
+#define SOCCIU_SR_CONFIG3_GPIO56_SR_SHIFT        (16U)
+/*! GPIO56_SR - Slew Rate Control for GPIO[56] */
+#define SOCCIU_SR_CONFIG3_GPIO56_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO56_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO56_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO57_SR_MASK         (0xC0000U)
+#define SOCCIU_SR_CONFIG3_GPIO57_SR_SHIFT        (18U)
+/*! GPIO57_SR - Slew Rate Control for GPIO[57] */
+#define SOCCIU_SR_CONFIG3_GPIO57_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO57_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO57_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO58_SR_MASK         (0x300000U)
+#define SOCCIU_SR_CONFIG3_GPIO58_SR_SHIFT        (20U)
+/*! GPIO58_SR - Slew Rate Control for GPIO[58] */
+#define SOCCIU_SR_CONFIG3_GPIO58_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO58_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO58_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO59_SR_MASK         (0xC00000U)
+#define SOCCIU_SR_CONFIG3_GPIO59_SR_SHIFT        (22U)
+/*! GPIO59_SR - Slew Rate Control for GPIO[59] */
+#define SOCCIU_SR_CONFIG3_GPIO59_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO59_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO59_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO60_SR_MASK         (0x3000000U)
+#define SOCCIU_SR_CONFIG3_GPIO60_SR_SHIFT        (24U)
+/*! GPIO60_SR - Slew Rate Control for GPIO[60] */
+#define SOCCIU_SR_CONFIG3_GPIO60_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO60_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO60_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO61_SR_MASK         (0xC000000U)
+#define SOCCIU_SR_CONFIG3_GPIO61_SR_SHIFT        (26U)
+/*! GPIO61_SR - Slew Rate Control for GPIO[61] */
+#define SOCCIU_SR_CONFIG3_GPIO61_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO61_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO61_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO62_SR_MASK         (0x30000000U)
+#define SOCCIU_SR_CONFIG3_GPIO62_SR_SHIFT        (28U)
+/*! GPIO62_SR - Slew Rate Control for GPIO[62] */
+#define SOCCIU_SR_CONFIG3_GPIO62_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO62_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO62_SR_MASK)
+
+#define SOCCIU_SR_CONFIG3_GPIO63_SR_MASK         (0xC0000000U)
+#define SOCCIU_SR_CONFIG3_GPIO63_SR_SHIFT        (30U)
+/*! GPIO63_SR - Slew Rate Control for GPIO[63] */
+#define SOCCIU_SR_CONFIG3_GPIO63_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG3_GPIO63_SR_SHIFT)) & SOCCIU_SR_CONFIG3_GPIO63_SR_MASK)
+/*! @} */
+
+/*! @name SR_CONFIG4 - GPIO Slew Rate control */
+/*! @{ */
+
+#define SOCCIU_SR_CONFIG4_ATEST0_SR_MASK         (0x3U)
+#define SOCCIU_SR_CONFIG4_ATEST0_SR_SHIFT        (0U)
+/*! ATEST0_SR - Slew Rate Control for atest0 */
+#define SOCCIU_SR_CONFIG4_ATEST0_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_ATEST0_SR_SHIFT)) & SOCCIU_SR_CONFIG4_ATEST0_SR_MASK)
+
+#define SOCCIU_SR_CONFIG4_ATEST1_SR_MASK         (0xCU)
+#define SOCCIU_SR_CONFIG4_ATEST1_SR_SHIFT        (2U)
+/*! ATEST1_SR - Slew Rate Control for atest1 */
+#define SOCCIU_SR_CONFIG4_ATEST1_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_ATEST1_SR_SHIFT)) & SOCCIU_SR_CONFIG4_ATEST1_SR_MASK)
+
+#define SOCCIU_SR_CONFIG4_ATEST2_SR_MASK         (0x30U)
+#define SOCCIU_SR_CONFIG4_ATEST2_SR_SHIFT        (4U)
+/*! ATEST2_SR - Slew Rate Control for atest2 */
+#define SOCCIU_SR_CONFIG4_ATEST2_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_ATEST2_SR_SHIFT)) & SOCCIU_SR_CONFIG4_ATEST2_SR_MASK)
+
+#define SOCCIU_SR_CONFIG4_ATEST3_SR_MASK         (0xC0U)
+#define SOCCIU_SR_CONFIG4_ATEST3_SR_SHIFT        (6U)
+/*! ATEST3_SR - Slew Rate Control for atest3 */
+#define SOCCIU_SR_CONFIG4_ATEST3_SR(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_ATEST3_SR_SHIFT)) & SOCCIU_SR_CONFIG4_ATEST3_SR_MASK)
+
+#define SOCCIU_SR_CONFIG4_RF_CNTL0_SR_MASK       (0x300U)
+#define SOCCIU_SR_CONFIG4_RF_CNTL0_SR_SHIFT      (8U)
+/*! RF_CNTL0_SR - Slew Rate Control for rf_cntl0 */
+#define SOCCIU_SR_CONFIG4_RF_CNTL0_SR(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_RF_CNTL0_SR_SHIFT)) & SOCCIU_SR_CONFIG4_RF_CNTL0_SR_MASK)
+
+#define SOCCIU_SR_CONFIG4_RF_CNTL1_SR_MASK       (0xC00U)
+#define SOCCIU_SR_CONFIG4_RF_CNTL1_SR_SHIFT      (10U)
+/*! RF_CNTL1_SR - Slew Rate Control for rf_cntl1 */
+#define SOCCIU_SR_CONFIG4_RF_CNTL1_SR(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_RF_CNTL1_SR_SHIFT)) & SOCCIU_SR_CONFIG4_RF_CNTL1_SR_MASK)
+
+#define SOCCIU_SR_CONFIG4_RF_CNTL2_SR_MASK       (0x3000U)
+#define SOCCIU_SR_CONFIG4_RF_CNTL2_SR_SHIFT      (12U)
+/*! RF_CNTL2_SR - Slew Rate Control for rf_cntl2 */
+#define SOCCIU_SR_CONFIG4_RF_CNTL2_SR(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_RF_CNTL2_SR_SHIFT)) & SOCCIU_SR_CONFIG4_RF_CNTL2_SR_MASK)
+
+#define SOCCIU_SR_CONFIG4_RF_CNTL3_SR_MASK       (0xC000U)
+#define SOCCIU_SR_CONFIG4_RF_CNTL3_SR_SHIFT      (14U)
+/*! RF_CNTL3_SR - Slew Rate Control for rf_cntl3 */
+#define SOCCIU_SR_CONFIG4_RF_CNTL3_SR(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_SR_CONFIG4_RF_CNTL3_SR_SHIFT)) & SOCCIU_SR_CONFIG4_RF_CNTL3_SR_MASK)
+/*! @} */
+
+/*! @name PAD_WKUP0 - Pad Wakeup Mode Enable */
+/*! @{ */
+
+#define SOCCIU_PAD_WKUP0_ENABLE_MASK             (0x3U)
+#define SOCCIU_PAD_WKUP0_ENABLE_SHIFT            (0U)
+/*! ENABLE - Pad Wakeup Mode Enable [1:0] */
+#define SOCCIU_PAD_WKUP0_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_WKUP0_ENABLE_SHIFT)) & SOCCIU_PAD_WKUP0_ENABLE_MASK)
+/*! @} */
+
+/*! @name PAD_PU_PD_EN0 - Pad Pull-up Pull-down Enable1 */
+/*! @{ */
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO0_PU_PD_EN_MASK (0x3U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO0_PU_PD_EN_SHIFT (0U)
+/*! GPIO0_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[0] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO0_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO0_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO0_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO1_PU_PD_EN_MASK (0xCU)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO1_PU_PD_EN_SHIFT (2U)
+/*! GPIO1_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[1] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO1_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO1_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO1_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO2_PU_PD_EN_MASK (0x30U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO2_PU_PD_EN_SHIFT (4U)
+/*! GPIO2_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[2] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO2_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO2_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO2_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO3_PU_PD_EN_MASK (0xC0U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO3_PU_PD_EN_SHIFT (6U)
+/*! GPIO3_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[3] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO3_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO3_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO3_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO4_PU_PD_EN_MASK (0x300U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO4_PU_PD_EN_SHIFT (8U)
+/*! GPIO4_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[4] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO4_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO4_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO4_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO5_PU_PD_EN_MASK (0xC00U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO5_PU_PD_EN_SHIFT (10U)
+/*! GPIO5_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[5] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO5_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO5_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO5_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO6_PU_PD_EN_MASK (0x3000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO6_PU_PD_EN_SHIFT (12U)
+/*! GPIO6_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[6] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO6_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO6_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO6_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO7_PU_PD_EN_MASK (0xC000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO7_PU_PD_EN_SHIFT (14U)
+/*! GPIO7_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[7] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO7_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO7_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO7_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO8_PU_PD_EN_MASK (0x30000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO8_PU_PD_EN_SHIFT (16U)
+/*! GPIO8_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[8] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO8_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO8_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO8_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO9_PU_PD_EN_MASK (0xC0000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO9_PU_PD_EN_SHIFT (18U)
+/*! GPIO9_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[9] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO9_PU_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO9_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO9_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO10_PU_PD_EN_MASK (0x300000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO10_PU_PD_EN_SHIFT (20U)
+/*! GPIO10_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[10] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO10_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO10_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO10_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO11_PU_PD_EN_MASK (0xC00000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO11_PU_PD_EN_SHIFT (22U)
+/*! GPIO11_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[11] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO11_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO11_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO11_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO12_PU_PD_EN_MASK (0x3000000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO12_PU_PD_EN_SHIFT (24U)
+/*! GPIO12_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[12] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO12_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO12_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO12_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO13_PU_PD_EN_MASK (0xC000000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO13_PU_PD_EN_SHIFT (26U)
+/*! GPIO13_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[13] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO13_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO13_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO13_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO14_PU_PD_EN_MASK (0x30000000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO14_PU_PD_EN_SHIFT (28U)
+/*! GPIO14_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[14] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO14_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO14_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO14_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN0_GPIO15_PU_PD_EN_MASK (0xC0000000U)
+#define SOCCIU_PAD_PU_PD_EN0_GPIO15_PU_PD_EN_SHIFT (30U)
+/*! GPIO15_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[15] */
+#define SOCCIU_PAD_PU_PD_EN0_GPIO15_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN0_GPIO15_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN0_GPIO15_PU_PD_EN_MASK)
+/*! @} */
+
+/*! @name PAD_PU_PD_EN1 - Pad Pull-up Pull-down Enable2 */
+/*! @{ */
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO16_PU_PD_EN_MASK (0x3U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO16_PU_PD_EN_SHIFT (0U)
+/*! GPIO16_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[16] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO16_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO16_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO16_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO17_PU_PD_EN_MASK (0xCU)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO17_PU_PD_EN_SHIFT (2U)
+/*! GPIO17_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[17] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO17_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO17_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO17_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO18_PU_PD_EN_MASK (0x30U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO18_PU_PD_EN_SHIFT (4U)
+/*! GPIO18_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[18] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO18_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO18_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO18_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO19_PU_PD_EN_MASK (0xC0U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO19_PU_PD_EN_SHIFT (6U)
+/*! GPIO19_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[19] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO19_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO19_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO19_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO20_PU_PD_EN_MASK (0x300U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO20_PU_PD_EN_SHIFT (8U)
+/*! GPIO20_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[20] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO20_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO20_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO20_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO21_PU_PD_EN_MASK (0xC00U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO21_PU_PD_EN_SHIFT (10U)
+/*! GPIO21_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[21] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO21_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO21_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO21_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO28_PU_PD_EN_MASK (0x3000000U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO28_PU_PD_EN_SHIFT (24U)
+/*! GPIO28_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[28] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO28_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO28_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO28_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO29_PU_PD_EN_MASK (0xC000000U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO29_PU_PD_EN_SHIFT (26U)
+/*! GPIO29_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[29] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO29_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO29_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO29_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO30_PU_PD_EN_MASK (0x30000000U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO30_PU_PD_EN_SHIFT (28U)
+/*! GPIO30_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[30] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO30_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO30_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO30_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN1_GPIO31_PU_PD_EN_MASK (0xC0000000U)
+#define SOCCIU_PAD_PU_PD_EN1_GPIO31_PU_PD_EN_SHIFT (30U)
+/*! GPIO31_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[31] */
+#define SOCCIU_PAD_PU_PD_EN1_GPIO31_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN1_GPIO31_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN1_GPIO31_PU_PD_EN_MASK)
+/*! @} */
+
+/*! @name PAD_PU_PD_EN2 - Pad Pull-up Pull-down Enable2 */
+/*! @{ */
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO32_PU_PD_EN_MASK (0x3U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO32_PU_PD_EN_SHIFT (0U)
+/*! GPIO32_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[32] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO32_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO32_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO32_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO33_PU_PD_EN_MASK (0xCU)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO33_PU_PD_EN_SHIFT (2U)
+/*! GPIO33_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[33] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO33_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO33_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO33_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO34_PU_PD_EN_MASK (0x30U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO34_PU_PD_EN_SHIFT (4U)
+/*! GPIO34_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[34] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO34_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO34_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO34_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO35_PU_PD_EN_MASK (0xC0U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO35_PU_PD_EN_SHIFT (6U)
+/*! GPIO35_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[35] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO35_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO35_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO35_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO36_PU_PD_EN_MASK (0x300U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO36_PU_PD_EN_SHIFT (8U)
+/*! GPIO36_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[36] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO36_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO36_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO36_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO37_PU_PD_EN_MASK (0xC00U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO37_PU_PD_EN_SHIFT (10U)
+/*! GPIO37_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[37] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO37_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO37_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO37_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO38_PU_PD_EN_MASK (0x3000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO38_PU_PD_EN_SHIFT (12U)
+/*! GPIO38_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[38] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO38_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO38_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO38_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO39_PU_PD_EN_MASK (0xC000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO39_PU_PD_EN_SHIFT (14U)
+/*! GPIO39_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[39] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO39_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO39_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO39_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO40_PU_PD_EN_MASK (0x30000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO40_PU_PD_EN_SHIFT (16U)
+/*! GPIO40_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[40] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO40_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO40_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO40_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO41_PU_PD_EN_MASK (0xC0000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO41_PU_PD_EN_SHIFT (18U)
+/*! GPIO41_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[41] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO41_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO41_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO41_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO42_PU_PD_EN_MASK (0x300000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO42_PU_PD_EN_SHIFT (20U)
+/*! GPIO42_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[42] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO42_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO42_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO42_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO43_PU_PD_EN_MASK (0xC00000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO43_PU_PD_EN_SHIFT (22U)
+/*! GPIO43_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[43] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO43_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO43_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO43_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO44_PU_PD_EN_MASK (0x3000000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO44_PU_PD_EN_SHIFT (24U)
+/*! GPIO44_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[44] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO44_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO44_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO44_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO45_PU_PD_EN_MASK (0xC000000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO45_PU_PD_EN_SHIFT (26U)
+/*! GPIO45_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[45] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO45_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO45_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO45_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO46_PU_PD_EN_MASK (0x30000000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO46_PU_PD_EN_SHIFT (28U)
+/*! GPIO46_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[46] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO46_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO46_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO46_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN2_GPIO47_PU_PD_EN_MASK (0xC0000000U)
+#define SOCCIU_PAD_PU_PD_EN2_GPIO47_PU_PD_EN_SHIFT (30U)
+/*! GPIO47_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[47] */
+#define SOCCIU_PAD_PU_PD_EN2_GPIO47_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN2_GPIO47_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN2_GPIO47_PU_PD_EN_MASK)
+/*! @} */
+
+/*! @name PAD_PU_PD_EN3 - Pad Pull-up Pull-down Enable2 */
+/*! @{ */
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO48_PU_PD_EN_MASK (0x3U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO48_PU_PD_EN_SHIFT (0U)
+/*! GPIO48_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[48] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO48_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO48_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO48_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO49_PU_PD_EN_MASK (0xCU)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO49_PU_PD_EN_SHIFT (2U)
+/*! GPIO49_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[49] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO49_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO49_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO49_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO50_PU_PD_EN_MASK (0x30U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO50_PU_PD_EN_SHIFT (4U)
+/*! GPIO50_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[50] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO50_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO50_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO50_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO51_PU_PD_EN_MASK (0xC0U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO51_PU_PD_EN_SHIFT (6U)
+/*! GPIO51_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[51] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO51_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO51_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO51_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO52_PU_PD_EN_MASK (0x300U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO52_PU_PD_EN_SHIFT (8U)
+/*! GPIO52_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[52] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO52_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO52_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO52_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO53_PU_PD_EN_MASK (0xC00U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO53_PU_PD_EN_SHIFT (10U)
+/*! GPIO53_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[53] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO53_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO53_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO53_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO54_PU_PD_EN_MASK (0x3000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO54_PU_PD_EN_SHIFT (12U)
+/*! GPIO54_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[54] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO54_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO54_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO54_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO55_PU_PD_EN_MASK (0xC000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO55_PU_PD_EN_SHIFT (14U)
+/*! GPIO55_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[55] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO55_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO55_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO55_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO56_PU_PD_EN_MASK (0x30000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO56_PU_PD_EN_SHIFT (16U)
+/*! GPIO56_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[56] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO56_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO56_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO56_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO57_PU_PD_EN_MASK (0xC0000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO57_PU_PD_EN_SHIFT (18U)
+/*! GPIO57_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[57] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO57_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO57_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO57_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO58_PU_PD_EN_MASK (0x300000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO58_PU_PD_EN_SHIFT (20U)
+/*! GPIO58_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[58] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO58_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO58_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO58_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO59_PU_PD_EN_MASK (0xC00000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO59_PU_PD_EN_SHIFT (22U)
+/*! GPIO59_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[59] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO59_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO59_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO59_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO60_PU_PD_EN_MASK (0x3000000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO60_PU_PD_EN_SHIFT (24U)
+/*! GPIO60_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[60] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO60_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO60_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO60_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO61_PU_PD_EN_MASK (0xC000000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO61_PU_PD_EN_SHIFT (26U)
+/*! GPIO61_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[61] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO61_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO61_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO61_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO62_PU_PD_EN_MASK (0x30000000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO62_PU_PD_EN_SHIFT (28U)
+/*! GPIO62_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[62] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO62_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO62_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO62_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN3_GPIO63_PU_PD_EN_MASK (0xC0000000U)
+#define SOCCIU_PAD_PU_PD_EN3_GPIO63_PU_PD_EN_SHIFT (30U)
+/*! GPIO63_PU_PD_EN - Internal Pd and Internal Pu Config for GPIO[63] */
+#define SOCCIU_PAD_PU_PD_EN3_GPIO63_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN3_GPIO63_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN3_GPIO63_PU_PD_EN_MASK)
+/*! @} */
+
+/*! @name PAD_PU_PD_EN4 - Pad Pull-up Pull-down Enable2 */
+/*! @{ */
+
+#define SOCCIU_PAD_PU_PD_EN4_ATEST0_PU_PD_EN_MASK (0x3U)
+#define SOCCIU_PAD_PU_PD_EN4_ATEST0_PU_PD_EN_SHIFT (0U)
+/*! ATEST0_PU_PD_EN - Internal Pd and Internal Pu Config for ATEST0 */
+#define SOCCIU_PAD_PU_PD_EN4_ATEST0_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN4_ATEST0_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN4_ATEST0_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN4_ATEST1_PU_PD_EN_MASK (0xCU)
+#define SOCCIU_PAD_PU_PD_EN4_ATEST1_PU_PD_EN_SHIFT (2U)
+/*! ATEST1_PU_PD_EN - Internal Pd and Internal Pu Config for ATEST1 */
+#define SOCCIU_PAD_PU_PD_EN4_ATEST1_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN4_ATEST1_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN4_ATEST1_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN4_ATEST2_PU_PD_EN_MASK (0x30U)
+#define SOCCIU_PAD_PU_PD_EN4_ATEST2_PU_PD_EN_SHIFT (4U)
+/*! ATEST2_PU_PD_EN - Internal Pd and Internal Pu Config for ATEST2 */
+#define SOCCIU_PAD_PU_PD_EN4_ATEST2_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN4_ATEST2_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN4_ATEST2_PU_PD_EN_MASK)
+
+#define SOCCIU_PAD_PU_PD_EN4_ATEST3_PU_PD_EN_MASK (0xC0U)
+#define SOCCIU_PAD_PU_PD_EN4_ATEST3_PU_PD_EN_SHIFT (6U)
+/*! ATEST3_PU_PD_EN - Internal Pd and Internal Pu Config for ATEST3 */
+#define SOCCIU_PAD_PU_PD_EN4_ATEST3_PU_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_PU_PD_EN4_ATEST3_PU_PD_EN_SHIFT)) & SOCCIU_PAD_PU_PD_EN4_ATEST3_PU_PD_EN_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_EN0 - Pad Sleep Mode Enable */
+/*! @{ */
+
+#define SOCCIU_PAD_SLP_EN0_GPIO0_SLP_EN_MASK     (0x1U)
+#define SOCCIU_PAD_SLP_EN0_GPIO0_SLP_EN_SHIFT    (0U)
+/*! GPIO0_SLP_EN - Enable Forcing GPIO[0] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO0_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO0_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO0_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO1_SLP_EN_MASK     (0x2U)
+#define SOCCIU_PAD_SLP_EN0_GPIO1_SLP_EN_SHIFT    (1U)
+/*! GPIO1_SLP_EN - Enable Forcing GPIO[1] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO1_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO1_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO1_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO2_SLP_EN_MASK     (0x4U)
+#define SOCCIU_PAD_SLP_EN0_GPIO2_SLP_EN_SHIFT    (2U)
+/*! GPIO2_SLP_EN - Enable Forcing GPIO[2] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO2_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO2_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO2_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO3_SLP_EN_MASK     (0x8U)
+#define SOCCIU_PAD_SLP_EN0_GPIO3_SLP_EN_SHIFT    (3U)
+/*! GPIO3_SLP_EN - Enable Forcing GPIO[3] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO3_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO3_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO3_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO4_SLP_EN_MASK     (0x10U)
+#define SOCCIU_PAD_SLP_EN0_GPIO4_SLP_EN_SHIFT    (4U)
+/*! GPIO4_SLP_EN - Enable Forcing GPIO[4] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO4_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO4_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO4_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO5_SLP_EN_MASK     (0x20U)
+#define SOCCIU_PAD_SLP_EN0_GPIO5_SLP_EN_SHIFT    (5U)
+/*! GPIO5_SLP_EN - Enable Forcing GPIO[5] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO5_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO5_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO5_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO6_SLP_EN_MASK     (0x40U)
+#define SOCCIU_PAD_SLP_EN0_GPIO6_SLP_EN_SHIFT    (6U)
+/*! GPIO6_SLP_EN - Enable Forcing GPIO[6] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO6_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO6_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO6_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO7_SLP_EN_MASK     (0x80U)
+#define SOCCIU_PAD_SLP_EN0_GPIO7_SLP_EN_SHIFT    (7U)
+/*! GPIO7_SLP_EN - Enable Forcing GPIO[7] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO7_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO7_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO7_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO8_SLP_EN_MASK     (0x100U)
+#define SOCCIU_PAD_SLP_EN0_GPIO8_SLP_EN_SHIFT    (8U)
+/*! GPIO8_SLP_EN - Enable Forcing GPIO[8] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO8_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO8_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO8_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO9_SLP_EN_MASK     (0x200U)
+#define SOCCIU_PAD_SLP_EN0_GPIO9_SLP_EN_SHIFT    (9U)
+/*! GPIO9_SLP_EN - Enable Forcing GPIO[9] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO9_SLP_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO9_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO9_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO10_SLP_EN_MASK    (0x400U)
+#define SOCCIU_PAD_SLP_EN0_GPIO10_SLP_EN_SHIFT   (10U)
+/*! GPIO10_SLP_EN - Enable Forcing GPIO[10] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO10_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO10_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO10_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO11_SLP_EN_MASK    (0x800U)
+#define SOCCIU_PAD_SLP_EN0_GPIO11_SLP_EN_SHIFT   (11U)
+/*! GPIO11_SLP_EN - Enable Forcing GPIO[11] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO11_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO11_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO11_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO12_SLP_EN_MASK    (0x1000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO12_SLP_EN_SHIFT   (12U)
+/*! GPIO12_SLP_EN - Enable Forcing GPIO[12] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO12_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO12_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO12_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO13_SLP_EN_MASK    (0x2000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO13_SLP_EN_SHIFT   (13U)
+/*! GPIO13_SLP_EN - Enable Forcing GPIO[13] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO13_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO13_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO13_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO14_SLP_EN_MASK    (0x4000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO14_SLP_EN_SHIFT   (14U)
+/*! GPIO14_SLP_EN - Enable Forcing GPIO[14] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO14_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO14_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO14_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO15_SLP_EN_MASK    (0x8000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO15_SLP_EN_SHIFT   (15U)
+/*! GPIO15_SLP_EN - Enable Forcing GPIO[15] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO15_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO15_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO15_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO16_SLP_EN_MASK    (0x10000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO16_SLP_EN_SHIFT   (16U)
+/*! GPIO16_SLP_EN - Enable Forcing GPIO[16] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO16_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO16_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO16_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO17_SLP_EN_MASK    (0x20000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO17_SLP_EN_SHIFT   (17U)
+/*! GPIO17_SLP_EN - Enable Forcing GPIO[17] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO17_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO17_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO17_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO18_SLP_EN_MASK    (0x40000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO18_SLP_EN_SHIFT   (18U)
+/*! GPIO18_SLP_EN - Enable Forcing GPIO[18] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO18_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO18_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO18_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO19_SLP_EN_MASK    (0x80000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO19_SLP_EN_SHIFT   (19U)
+/*! GPIO19_SLP_EN - Enable Forcing GPIO[19] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO19_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO19_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO19_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO20_SLP_EN_MASK    (0x100000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO20_SLP_EN_SHIFT   (20U)
+/*! GPIO20_SLP_EN - Enable Forcing GPIO[20] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO20_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO20_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO20_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO21_SLP_EN_MASK    (0x200000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO21_SLP_EN_SHIFT   (21U)
+/*! GPIO21_SLP_EN - Enable Forcing GPIO[21] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO21_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO21_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO21_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO28_SLP_EN_MASK    (0x10000000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO28_SLP_EN_SHIFT   (28U)
+/*! GPIO28_SLP_EN - Enable Forcing GPIO[28] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO28_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO28_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO28_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO29_SLP_EN_MASK    (0x20000000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO29_SLP_EN_SHIFT   (29U)
+/*! GPIO29_SLP_EN - Enable Forcing GPIO[29] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO29_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO29_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO29_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO30_SLP_EN_MASK    (0x40000000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO30_SLP_EN_SHIFT   (30U)
+/*! GPIO30_SLP_EN - Enable Forcing GPIO[30] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO30_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO30_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO30_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN0_GPIO31_SLP_EN_MASK    (0x80000000U)
+#define SOCCIU_PAD_SLP_EN0_GPIO31_SLP_EN_SHIFT   (31U)
+/*! GPIO31_SLP_EN - Enable Forcing GPIO[31] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN0_GPIO31_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN0_GPIO31_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN0_GPIO31_SLP_EN_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_EN1 - Pad Sleep Mode Enable */
+/*! @{ */
+
+#define SOCCIU_PAD_SLP_EN1_GPIO32_SLP_EN_MASK    (0x1U)
+#define SOCCIU_PAD_SLP_EN1_GPIO32_SLP_EN_SHIFT   (0U)
+/*! GPIO32_SLP_EN - Enable Forcing GPIO[32] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO32_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO32_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO32_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO33_SLP_EN_MASK    (0x2U)
+#define SOCCIU_PAD_SLP_EN1_GPIO33_SLP_EN_SHIFT   (1U)
+/*! GPIO33_SLP_EN - Enable Forcing GPIO[33] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO33_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO33_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO33_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO34_SLP_EN_MASK    (0x4U)
+#define SOCCIU_PAD_SLP_EN1_GPIO34_SLP_EN_SHIFT   (2U)
+/*! GPIO34_SLP_EN - Enable Forcing GPIO[34] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO34_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO34_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO34_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO35_SLP_EN_MASK    (0x8U)
+#define SOCCIU_PAD_SLP_EN1_GPIO35_SLP_EN_SHIFT   (3U)
+/*! GPIO35_SLP_EN - Enable Forcing GPIO[35] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO35_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO35_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO35_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO36_SLP_EN_MASK    (0x10U)
+#define SOCCIU_PAD_SLP_EN1_GPIO36_SLP_EN_SHIFT   (4U)
+/*! GPIO36_SLP_EN - Enable Forcing GPIO[36] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO36_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO36_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO36_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO37_SLP_EN_MASK    (0x20U)
+#define SOCCIU_PAD_SLP_EN1_GPIO37_SLP_EN_SHIFT   (5U)
+/*! GPIO37_SLP_EN - Enable Forcing GPIO[37] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO37_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO37_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO37_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO38_SLP_EN_MASK    (0x40U)
+#define SOCCIU_PAD_SLP_EN1_GPIO38_SLP_EN_SHIFT   (6U)
+/*! GPIO38_SLP_EN - Enable Forcing GPIO[38] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO38_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO38_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO38_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO39_SLP_EN_MASK    (0x80U)
+#define SOCCIU_PAD_SLP_EN1_GPIO39_SLP_EN_SHIFT   (7U)
+/*! GPIO39_SLP_EN - Enable Forcing GPIO[39] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO39_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO39_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO39_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO40_SLP_EN_MASK    (0x100U)
+#define SOCCIU_PAD_SLP_EN1_GPIO40_SLP_EN_SHIFT   (8U)
+/*! GPIO40_SLP_EN - Enable Forcing GPIO[40] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO40_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO40_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO40_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO41_SLP_EN_MASK    (0x200U)
+#define SOCCIU_PAD_SLP_EN1_GPIO41_SLP_EN_SHIFT   (9U)
+/*! GPIO41_SLP_EN - Enable Forcing GPIO[41] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO41_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO41_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO41_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO42_SLP_EN_MASK    (0x400U)
+#define SOCCIU_PAD_SLP_EN1_GPIO42_SLP_EN_SHIFT   (10U)
+/*! GPIO42_SLP_EN - Enable Forcing GPIO[42] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO42_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO42_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO42_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO43_SLP_EN_MASK    (0x800U)
+#define SOCCIU_PAD_SLP_EN1_GPIO43_SLP_EN_SHIFT   (11U)
+/*! GPIO43_SLP_EN - Enable Forcing GPIO[43] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO43_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO43_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO43_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO44_SLP_EN_MASK    (0x1000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO44_SLP_EN_SHIFT   (12U)
+/*! GPIO44_SLP_EN - Enable Forcing GPIO[44] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO44_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO44_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO44_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO45_SLP_EN_MASK    (0x2000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO45_SLP_EN_SHIFT   (13U)
+/*! GPIO45_SLP_EN - Enable Forcing GPIO[45] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO45_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO45_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO45_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO46_SLP_EN_MASK    (0x4000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO46_SLP_EN_SHIFT   (14U)
+/*! GPIO46_SLP_EN - Enable Forcing GPIO[46] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO46_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO46_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO46_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO47_SLP_EN_MASK    (0x8000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO47_SLP_EN_SHIFT   (15U)
+/*! GPIO47_SLP_EN - Enable Forcing GPIO[47] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO47_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO47_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO47_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO48_SLP_EN_MASK    (0x10000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO48_SLP_EN_SHIFT   (16U)
+/*! GPIO48_SLP_EN - Enable Forcing GPIO[48] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO48_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO48_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO48_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO49_SLP_EN_MASK    (0x20000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO49_SLP_EN_SHIFT   (17U)
+/*! GPIO49_SLP_EN - Enable Forcing GPIO[49] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO49_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO49_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO49_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO50_SLP_EN_MASK    (0x40000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO50_SLP_EN_SHIFT   (18U)
+/*! GPIO50_SLP_EN - Enable Forcing GPIO[50] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO50_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO50_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO50_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO51_SLP_EN_MASK    (0x80000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO51_SLP_EN_SHIFT   (19U)
+/*! GPIO51_SLP_EN - Enable Forcing GPIO[51] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO51_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO51_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO51_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO52_SLP_EN_MASK    (0x100000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO52_SLP_EN_SHIFT   (20U)
+/*! GPIO52_SLP_EN - Enable Forcing GPIO[52] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO52_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO52_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO52_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO53_SLP_EN_MASK    (0x200000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO53_SLP_EN_SHIFT   (21U)
+/*! GPIO53_SLP_EN - Enable Forcing GPIO[53] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO53_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO53_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO53_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO54_SLP_EN_MASK    (0x400000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO54_SLP_EN_SHIFT   (22U)
+/*! GPIO54_SLP_EN - Enable Forcing GPIO[54] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO54_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO54_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO54_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO55_SLP_EN_MASK    (0x800000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO55_SLP_EN_SHIFT   (23U)
+/*! GPIO55_SLP_EN - Enable Forcing GPIO[55] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO55_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO55_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO55_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO56_SLP_EN_MASK    (0x1000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO56_SLP_EN_SHIFT   (24U)
+/*! GPIO56_SLP_EN - Enable Forcing GPIO[56] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO56_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO56_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO56_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO57_SLP_EN_MASK    (0x2000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO57_SLP_EN_SHIFT   (25U)
+/*! GPIO57_SLP_EN - Enable Forcing GPIO[57] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO57_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO57_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO57_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO58_SLP_EN_MASK    (0x4000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO58_SLP_EN_SHIFT   (26U)
+/*! GPIO58_SLP_EN - Enable Forcing GPIO[58] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO58_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO58_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO58_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO59_SLP_EN_MASK    (0x8000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO59_SLP_EN_SHIFT   (27U)
+/*! GPIO59_SLP_EN - Enable Forcing GPIO[59] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO59_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO59_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO59_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO60_SLP_EN_MASK    (0x10000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO60_SLP_EN_SHIFT   (28U)
+/*! GPIO60_SLP_EN - Enable Forcing GPIO[60] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO60_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO60_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO60_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO61_SLP_EN_MASK    (0x20000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO61_SLP_EN_SHIFT   (29U)
+/*! GPIO61_SLP_EN - Enable Forcing GPIO[61] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO61_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO61_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO61_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO62_SLP_EN_MASK    (0x40000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO62_SLP_EN_SHIFT   (30U)
+/*! GPIO62_SLP_EN - Enable Forcing GPIO[62] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO62_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO62_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO62_SLP_EN_MASK)
+
+#define SOCCIU_PAD_SLP_EN1_GPIO63_SLP_EN_MASK    (0x80000000U)
+#define SOCCIU_PAD_SLP_EN1_GPIO63_SLP_EN_SHIFT   (31U)
+/*! GPIO63_SLP_EN - Enable Forcing GPIO[63] Output During Sleep */
+#define SOCCIU_PAD_SLP_EN1_GPIO63_SLP_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_EN1_GPIO63_SLP_EN_SHIFT)) & SOCCIU_PAD_SLP_EN1_GPIO63_SLP_EN_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_VAL0 - Pad Sleep Mode Value */
+/*! @{ */
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO0_SLP_VAL_MASK   (0x1U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO0_SLP_VAL_SHIFT  (0U)
+/*! GPIO0_SLP_VAL - Force GPIO[0] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO0_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO0_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO0_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO1_SLP_VAL_MASK   (0x2U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO1_SLP_VAL_SHIFT  (1U)
+/*! GPIO1_SLP_VAL - Force GPIO[1] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO1_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO1_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO1_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO2_SLP_VAL_MASK   (0x4U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO2_SLP_VAL_SHIFT  (2U)
+/*! GPIO2_SLP_VAL - Force GPIO[2] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO2_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO2_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO2_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO3_SLP_VAL_MASK   (0x8U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO3_SLP_VAL_SHIFT  (3U)
+/*! GPIO3_SLP_VAL - Force GPIO[3] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO3_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO3_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO3_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO4_SLP_VAL_MASK   (0x10U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO4_SLP_VAL_SHIFT  (4U)
+/*! GPIO4_SLP_VAL - Force GPIO[4] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO4_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO4_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO4_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO5_SLP_VAL_MASK   (0x20U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO5_SLP_VAL_SHIFT  (5U)
+/*! GPIO5_SLP_VAL - Force GPIO[5] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO5_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO5_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO5_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO6_SLP_VAL_MASK   (0x40U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO6_SLP_VAL_SHIFT  (6U)
+/*! GPIO6_SLP_VAL - Force GPIO[6] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO6_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO6_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO6_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO7_SLP_VAL_MASK   (0x80U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO7_SLP_VAL_SHIFT  (7U)
+/*! GPIO7_SLP_VAL - Force GPIO[7] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO7_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO7_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO7_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO8_SLP_VAL_MASK   (0x100U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO8_SLP_VAL_SHIFT  (8U)
+/*! GPIO8_SLP_VAL - Force GPIO[8] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO8_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO8_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO8_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO9_SLP_VAL_MASK   (0x200U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO9_SLP_VAL_SHIFT  (9U)
+/*! GPIO9_SLP_VAL - Force GPIO[9] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO9_SLP_VAL(x)     (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO9_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO9_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO10_SLP_VAL_MASK  (0x400U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO10_SLP_VAL_SHIFT (10U)
+/*! GPIO10_SLP_VAL - Force GPIO[10] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO10_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO10_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO10_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO11_SLP_VAL_MASK  (0x800U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO11_SLP_VAL_SHIFT (11U)
+/*! GPIO11_SLP_VAL - Force GPIO[11] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO11_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO11_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO11_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO12_SLP_VAL_MASK  (0x1000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO12_SLP_VAL_SHIFT (12U)
+/*! GPIO12_SLP_VAL - Force GPIO[12] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO12_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO12_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO12_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO13_SLP_VAL_MASK  (0x2000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO13_SLP_VAL_SHIFT (13U)
+/*! GPIO13_SLP_VAL - Force GPIO[13] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO13_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO13_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO13_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO14_SLP_VAL_MASK  (0x4000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO14_SLP_VAL_SHIFT (14U)
+/*! GPIO14_SLP_VAL - Force GPIO[14] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO14_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO14_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO14_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO15_SLP_VAL_MASK  (0x8000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO15_SLP_VAL_SHIFT (15U)
+/*! GPIO15_SLP_VAL - Force GPIO[15] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO15_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO15_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO15_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO16_SLP_VAL_MASK  (0x10000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO16_SLP_VAL_SHIFT (16U)
+/*! GPIO16_SLP_VAL - Force GPIO[16] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO16_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO16_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO16_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO17_SLP_VAL_MASK  (0x20000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO17_SLP_VAL_SHIFT (17U)
+/*! GPIO17_SLP_VAL - Force GPIO[17] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO17_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO17_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO17_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO18_SLP_VAL_MASK  (0x40000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO18_SLP_VAL_SHIFT (18U)
+/*! GPIO18_SLP_VAL - Force GPIO[18] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO18_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO18_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO18_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO19_SLP_VAL_MASK  (0x80000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO19_SLP_VAL_SHIFT (19U)
+/*! GPIO19_SLP_VAL - Force GPIO[19] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO19_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO19_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO19_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO20_SLP_VAL_MASK  (0x100000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO20_SLP_VAL_SHIFT (20U)
+/*! GPIO20_SLP_VAL - Force GPIO[20] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO20_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO20_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO20_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO21_SLP_VAL_MASK  (0x200000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO21_SLP_VAL_SHIFT (21U)
+/*! GPIO21_SLP_VAL - Force GPIO[21] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO21_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO21_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO21_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO28_SLP_VAL_MASK  (0x10000000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO28_SLP_VAL_SHIFT (28U)
+/*! GPIO28_SLP_VAL - Force GPIO[28] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO28_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO28_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO28_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO29_SLP_VAL_MASK  (0x20000000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO29_SLP_VAL_SHIFT (29U)
+/*! GPIO29_SLP_VAL - Force GPIO[29] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO29_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO29_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO29_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO30_SLP_VAL_MASK  (0x40000000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO30_SLP_VAL_SHIFT (30U)
+/*! GPIO30_SLP_VAL - Force GPIO[30] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO30_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO30_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO30_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL0_GPIO31_SLP_VAL_MASK  (0x80000000U)
+#define SOCCIU_PAD_SLP_VAL0_GPIO31_SLP_VAL_SHIFT (31U)
+/*! GPIO31_SLP_VAL - Force GPIO[31] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL0_GPIO31_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL0_GPIO31_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL0_GPIO31_SLP_VAL_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_VAL1 - Pad Sleep Mode Value */
+/*! @{ */
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO32_SLP_VAL_MASK  (0x1U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO32_SLP_VAL_SHIFT (0U)
+/*! GPIO32_SLP_VAL - Force GPIO[32] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO32_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO32_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO32_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO33_SLP_VAL_MASK  (0x2U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO33_SLP_VAL_SHIFT (1U)
+/*! GPIO33_SLP_VAL - Force GPIO[33] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO33_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO33_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO33_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO34_SLP_VAL_MASK  (0x4U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO34_SLP_VAL_SHIFT (2U)
+/*! GPIO34_SLP_VAL - Force GPIO[34] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO34_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO34_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO34_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO35_SLP_VAL_MASK  (0x8U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO35_SLP_VAL_SHIFT (3U)
+/*! GPIO35_SLP_VAL - Force GPIO[35] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO35_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO35_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO35_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO36_SLP_VAL_MASK  (0x10U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO36_SLP_VAL_SHIFT (4U)
+/*! GPIO36_SLP_VAL - Force GPIO[36] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO36_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO36_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO36_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO37_SLP_VAL_MASK  (0x20U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO37_SLP_VAL_SHIFT (5U)
+/*! GPIO37_SLP_VAL - Force GPIO[37] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO37_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO37_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO37_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO38_SLP_VAL_MASK  (0x40U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO38_SLP_VAL_SHIFT (6U)
+/*! GPIO38_SLP_VAL - Force GPIO[38] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO38_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO38_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO38_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO39_SLP_VAL_MASK  (0x80U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO39_SLP_VAL_SHIFT (7U)
+/*! GPIO39_SLP_VAL - Force GPIO[39] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO39_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO39_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO39_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO40_SLP_VAL_MASK  (0x100U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO40_SLP_VAL_SHIFT (8U)
+/*! GPIO40_SLP_VAL - Force GPIO[40] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO40_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO40_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO40_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO41_SLP_VAL_MASK  (0x200U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO41_SLP_VAL_SHIFT (9U)
+/*! GPIO41_SLP_VAL - Force GPIO[41] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO41_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO41_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO41_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO42_SLP_VAL_MASK  (0x400U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO42_SLP_VAL_SHIFT (10U)
+/*! GPIO42_SLP_VAL - Force GPIO[42] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO42_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO42_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO42_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO43_SLP_VAL_MASK  (0x800U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO43_SLP_VAL_SHIFT (11U)
+/*! GPIO43_SLP_VAL - Force GPIO[43] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO43_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO43_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO43_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO44_SLP_VAL_MASK  (0x1000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO44_SLP_VAL_SHIFT (12U)
+/*! GPIO44_SLP_VAL - Force GPIO[44] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO44_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO44_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO44_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO45_SLP_VAL_MASK  (0x2000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO45_SLP_VAL_SHIFT (13U)
+/*! GPIO45_SLP_VAL - Force GPIO[45] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO45_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO45_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO45_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO46_SLP_VAL_MASK  (0x4000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO46_SLP_VAL_SHIFT (14U)
+/*! GPIO46_SLP_VAL - Force GPIO[46] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO46_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO46_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO46_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO47_SLP_VAL_MASK  (0x8000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO47_SLP_VAL_SHIFT (15U)
+/*! GPIO47_SLP_VAL - Force GPIO[47] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO47_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO47_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO47_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO48_SLP_VAL_MASK  (0x10000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO48_SLP_VAL_SHIFT (16U)
+/*! GPIO48_SLP_VAL - Force GPIO[48] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO48_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO48_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO48_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO49_SLP_VAL_MASK  (0x20000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO49_SLP_VAL_SHIFT (17U)
+/*! GPIO49_SLP_VAL - Force GPIO[49] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO49_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO49_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO49_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO50_SLP_VAL_MASK  (0x40000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO50_SLP_VAL_SHIFT (18U)
+/*! GPIO50_SLP_VAL - Force GPIO[50] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO50_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO50_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO50_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO51_SLP_VAL_MASK  (0x80000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO51_SLP_VAL_SHIFT (19U)
+/*! GPIO51_SLP_VAL - Force GPIO[51] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO51_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO51_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO51_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO52_SLP_VAL_MASK  (0x100000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO52_SLP_VAL_SHIFT (20U)
+/*! GPIO52_SLP_VAL - Force GPIO[52] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO52_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO52_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO52_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO53_SLP_VAL_MASK  (0x200000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO53_SLP_VAL_SHIFT (21U)
+/*! GPIO53_SLP_VAL - Force GPIO[53] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO53_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO53_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO53_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO54_SLP_VAL_MASK  (0x400000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO54_SLP_VAL_SHIFT (22U)
+/*! GPIO54_SLP_VAL - Force GPIO[54] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO54_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO54_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO54_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO55_SLP_VAL_MASK  (0x800000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO55_SLP_VAL_SHIFT (23U)
+/*! GPIO55_SLP_VAL - Force GPIO[55] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO55_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO55_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO55_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO56_SLP_VAL_MASK  (0x1000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO56_SLP_VAL_SHIFT (24U)
+/*! GPIO56_SLP_VAL - Force GPIO[56] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO56_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO56_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO56_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO57_SLP_VAL_MASK  (0x2000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO57_SLP_VAL_SHIFT (25U)
+/*! GPIO57_SLP_VAL - Force GPIO[57] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO57_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO57_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO57_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO58_SLP_VAL_MASK  (0x4000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO58_SLP_VAL_SHIFT (26U)
+/*! GPIO58_SLP_VAL - Force GPIO[58] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO58_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO58_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO58_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO59_SLP_VAL_MASK  (0x8000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO59_SLP_VAL_SHIFT (27U)
+/*! GPIO59_SLP_VAL - Force GPIO[59] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO59_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO59_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO59_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO60_SLP_VAL_MASK  (0x10000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO60_SLP_VAL_SHIFT (28U)
+/*! GPIO60_SLP_VAL - Force GPIO[60] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO60_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO60_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO60_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO61_SLP_VAL_MASK  (0x20000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO61_SLP_VAL_SHIFT (29U)
+/*! GPIO61_SLP_VAL - Force GPIO[61] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO61_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO61_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO61_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO62_SLP_VAL_MASK  (0x40000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO62_SLP_VAL_SHIFT (30U)
+/*! GPIO62_SLP_VAL - Force GPIO[62] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO62_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO62_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO62_SLP_VAL_MASK)
+
+#define SOCCIU_PAD_SLP_VAL1_GPIO63_SLP_VAL_MASK  (0x80000000U)
+#define SOCCIU_PAD_SLP_VAL1_GPIO63_SLP_VAL_SHIFT (31U)
+/*! GPIO63_SLP_VAL - Force GPIO[63] Output During Sleep */
+#define SOCCIU_PAD_SLP_VAL1_GPIO63_SLP_VAL(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_VAL1_GPIO63_SLP_VAL_SHIFT)) & SOCCIU_PAD_SLP_VAL1_GPIO63_SLP_VAL_MASK)
+/*! @} */
+
+/*! @name PSW_VD2_RDY0 - Power Switch VD2_RDY Status */
+/*! @{ */
+
+#define SOCCIU_PSW_VD2_RDY0_PSW_STATUS_MASK      (0xFFFFFFFFU)
+#define SOCCIU_PSW_VD2_RDY0_PSW_STATUS_SHIFT     (0U)
+/*! PSW_STATUS - VD2_RDY Status of following Power Switches: */
+#define SOCCIU_PSW_VD2_RDY0_PSW_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << SOCCIU_PSW_VD2_RDY0_PSW_STATUS_SHIFT)) & SOCCIU_PSW_VD2_RDY0_PSW_STATUS_MASK)
+/*! @} */
+
+/*! @name PSW_ECO_CTRL - Power Switch ECO Control */
+/*! @{ */
+
+#define SOCCIU_PSW_ECO_CTRL_ECO_BITS_MASK        (0xFFFFFFFFU)
+#define SOCCIU_PSW_ECO_CTRL_ECO_BITS_SHIFT       (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define SOCCIU_PSW_ECO_CTRL_ECO_BITS(x)          (((uint32_t)(((uint32_t)(x)) << SOCCIU_PSW_ECO_CTRL_ECO_BITS_SHIFT)) & SOCCIU_PSW_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name CLK_SW - Clock Controls for SOC_CLK_TOP */
+/*! @{ */
+
+#define SOCCIU_CLK_SW_CAU_SIF_AHB_CLK_EN_MASK    (0x1U)
+#define SOCCIU_CLK_SW_CAU_SIF_AHB_CLK_EN_SHIFT   (0U)
+/*! CAU_SIF_AHB_CLK_EN - " */
+#define SOCCIU_CLK_SW_CAU_SIF_AHB_CLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_CAU_SIF_AHB_CLK_EN_SHIFT)) & SOCCIU_CLK_SW_CAU_SIF_AHB_CLK_EN_MASK)
+
+#define SOCCIU_CLK_SW_AHB2APB_CLK_EN_MASK        (0x2U)
+#define SOCCIU_CLK_SW_AHB2APB_CLK_EN_SHIFT       (1U)
+/*! AHB2APB_CLK_EN - " */
+#define SOCCIU_CLK_SW_AHB2APB_CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_AHB2APB_CLK_EN_SHIFT)) & SOCCIU_CLK_SW_AHB2APB_CLK_EN_MASK)
+
+#define SOCCIU_CLK_SW_DAPCLKEN_MASK              (0x20U)
+#define SOCCIU_CLK_SW_DAPCLKEN_SHIFT             (5U)
+/*! DAPCLKEN - clk en for SOC DAP */
+#define SOCCIU_CLK_SW_DAPCLKEN(x)                (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_DAPCLKEN_SHIFT)) & SOCCIU_CLK_SW_DAPCLKEN_MASK)
+
+#define SOCCIU_CLK_SW_WL_CM3_DAPCLKEN_MASK       (0x40U)
+#define SOCCIU_CLK_SW_WL_CM3_DAPCLKEN_SHIFT      (6U)
+/*! WL_CM3_DAPCLKEN - clk en for CPU1 DAP interface */
+#define SOCCIU_CLK_SW_WL_CM3_DAPCLKEN(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_WL_CM3_DAPCLKEN_SHIFT)) & SOCCIU_CLK_SW_WL_CM3_DAPCLKEN_MASK)
+
+#define SOCCIU_CLK_SW_BT_CM3_DAPCLKEN_MASK       (0x80U)
+#define SOCCIU_CLK_SW_BT_CM3_DAPCLKEN_SHIFT      (7U)
+/*! BT_CM3_DAPCLKEN - clk en for CPU2 DAP interface */
+#define SOCCIU_CLK_SW_BT_CM3_DAPCLKEN(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_BT_CM3_DAPCLKEN_SHIFT)) & SOCCIU_CLK_SW_BT_CM3_DAPCLKEN_MASK)
+
+#define SOCCIU_CLK_SW_CSCLKEN_MASK               (0x200U)
+#define SOCCIU_CLK_SW_CSCLKEN_SHIFT              (9U)
+/*! CSCLKEN - clk en for SOC Coresight system (includes CTI, CTM, TPIU, ATB Funnel, ATB upsizer) */
+#define SOCCIU_CLK_SW_CSCLKEN(x)                 (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_CSCLKEN_SHIFT)) & SOCCIU_CLK_SW_CSCLKEN_MASK)
+
+#define SOCCIU_CLK_SW_WL_CM3_CSCLKEN_MASK        (0x400U)
+#define SOCCIU_CLK_SW_WL_CM3_CSCLKEN_SHIFT       (10U)
+/*! WL_CM3_CSCLKEN - clk en for CPU1 ATB (ETM and ITM) and CTI interface */
+#define SOCCIU_CLK_SW_WL_CM3_CSCLKEN(x)          (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_WL_CM3_CSCLKEN_SHIFT)) & SOCCIU_CLK_SW_WL_CM3_CSCLKEN_MASK)
+
+#define SOCCIU_CLK_SW_BT_CM3_CSCLKEN_MASK        (0x800U)
+#define SOCCIU_CLK_SW_BT_CM3_CSCLKEN_SHIFT       (11U)
+/*! BT_CM3_CSCLKEN - clk en for CPU2 ATB (ETM and ITM) and CTI interface */
+#define SOCCIU_CLK_SW_BT_CM3_CSCLKEN(x)          (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_BT_CM3_CSCLKEN_SHIFT)) & SOCCIU_CLK_SW_BT_CM3_CSCLKEN_MASK)
+
+#define SOCCIU_CLK_SW_CAU_SIF_CLK_SEL_MASK       (0x10000U)
+#define SOCCIU_CLK_SW_CAU_SIF_CLK_SEL_SHIFT      (16U)
+/*! CAU_SIF_CLK_SEL - CAU SIF Clock Frequency Select */
+#define SOCCIU_CLK_SW_CAU_SIF_CLK_SEL(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_CAU_SIF_CLK_SEL_SHIFT)) & SOCCIU_CLK_SW_CAU_SIF_CLK_SEL_MASK)
+
+#define SOCCIU_CLK_SW_SOC_AHB_CLK_SEL_MASK       (0x20000U)
+#define SOCCIU_CLK_SW_SOC_AHB_CLK_SEL_SHIFT      (17U)
+/*! SOC_AHB_CLK_SEL - SOC TOP AHB Clock Frequency Select */
+#define SOCCIU_CLK_SW_SOC_AHB_CLK_SEL(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SW_SOC_AHB_CLK_SEL_SHIFT)) & SOCCIU_CLK_SW_SOC_AHB_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name RST_SW - Reset Controls for SOC_RESET_GEN */
+/*! @{ */
+
+#define SOCCIU_RST_SW_CAU_SIF_RSTN_MASK          (0x1U)
+#define SOCCIU_RST_SW_CAU_SIF_RSTN_SHIFT         (0U)
+/*! CAU_SIF_RSTN - " */
+#define SOCCIU_RST_SW_CAU_SIF_RSTN(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_CAU_SIF_RSTN_SHIFT)) & SOCCIU_RST_SW_CAU_SIF_RSTN_MASK)
+
+#define SOCCIU_RST_SW_CAU_SIF_HRESETN_MASK       (0x2U)
+#define SOCCIU_RST_SW_CAU_SIF_HRESETN_SHIFT      (1U)
+/*! CAU_SIF_HRESETN - " */
+#define SOCCIU_RST_SW_CAU_SIF_HRESETN(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_CAU_SIF_HRESETN_SHIFT)) & SOCCIU_RST_SW_CAU_SIF_HRESETN_MASK)
+
+#define SOCCIU_RST_SW_SOC_PERI_HRESETN_MASK      (0x4U)
+#define SOCCIU_RST_SW_SOC_PERI_HRESETN_SHIFT     (2U)
+/*! SOC_PERI_HRESETN - Falling edge detected on this in RTL to reset the ahb bus */
+#define SOCCIU_RST_SW_SOC_PERI_HRESETN(x)        (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_SOC_PERI_HRESETN_SHIFT)) & SOCCIU_RST_SW_SOC_PERI_HRESETN_MASK)
+
+#define SOCCIU_RST_SW_DRO_RSTN_MASK              (0x8U)
+#define SOCCIU_RST_SW_DRO_RSTN_SHIFT             (3U)
+/*! DRO_RSTN - DRO Clock Reset */
+#define SOCCIU_RST_SW_DRO_RSTN(x)                (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_DRO_RSTN_SHIFT)) & SOCCIU_RST_SW_DRO_RSTN_MASK)
+
+#define SOCCIU_RST_SW_AHB2APB_HRESETN_MASK       (0x10U)
+#define SOCCIU_RST_SW_AHB2APB_HRESETN_SHIFT      (4U)
+/*! AHB2APB_HRESETN - " */
+#define SOCCIU_RST_SW_AHB2APB_HRESETN(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_AHB2APB_HRESETN_SHIFT)) & SOCCIU_RST_SW_AHB2APB_HRESETN_MASK)
+
+#define SOCCIU_RST_SW_HCLK__MASK                 (0x20U)
+#define SOCCIU_RST_SW_HCLK__SHIFT                (5U)
+/*! HCLK_ - Auto clear SW reset for socciu */
+#define SOCCIU_RST_SW_HCLK_(x)                   (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_HCLK__SHIFT)) & SOCCIU_RST_SW_HCLK__MASK)
+
+#define SOCCIU_RST_SW_CSSYS_RESETN_MASK          (0x400U)
+#define SOCCIU_RST_SW_CSSYS_RESETN_SHIFT         (10U)
+/*! CSSYS_RESETN - SW reset for the cssys cs resetn */
+#define SOCCIU_RST_SW_CSSYS_RESETN(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_CSSYS_RESETN_SHIFT)) & SOCCIU_RST_SW_CSSYS_RESETN_MASK)
+
+#define SOCCIU_RST_SW_DAP_RESETN_MASK            (0x800U)
+#define SOCCIU_RST_SW_DAP_RESETN_SHIFT           (11U)
+/*! DAP_RESETN - SW reset for the dap_resetn */
+#define SOCCIU_RST_SW_DAP_RESETN(x)              (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_DAP_RESETN_SHIFT)) & SOCCIU_RST_SW_DAP_RESETN_MASK)
+
+#define SOCCIU_RST_SW_WLAN_N_BLE_PORB_DELAY_MASK (0xFF000U)
+#define SOCCIU_RST_SW_WLAN_N_BLE_PORB_DELAY_SHIFT (12U)
+/*! WLAN_N_BLE_PORB_DELAY - PORB delay for wlan and ble, bootrom can use this feature if needed */
+#define SOCCIU_RST_SW_WLAN_N_BLE_PORB_DELAY(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_WLAN_N_BLE_PORB_DELAY_SHIFT)) & SOCCIU_RST_SW_WLAN_N_BLE_PORB_DELAY_MASK)
+
+#define SOCCIU_RST_SW_SOC_ITRC_CHIP_RSTB_EN_MASK (0x100000U)
+#define SOCCIU_RST_SW_SOC_ITRC_CHIP_RSTB_EN_SHIFT (20U)
+/*! SOC_ITRC_CHIP_RSTB_EN - Default the itrc chip reset can reset SOC, SW can disable this if not required */
+#define SOCCIU_RST_SW_SOC_ITRC_CHIP_RSTB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_SOC_ITRC_CHIP_RSTB_EN_SHIFT)) & SOCCIU_RST_SW_SOC_ITRC_CHIP_RSTB_EN_MASK)
+
+#define SOCCIU_RST_SW_WL_ITRC_CHIP_RSTB_EN_MASK  (0x200000U)
+#define SOCCIU_RST_SW_WL_ITRC_CHIP_RSTB_EN_SHIFT (21U)
+/*! WL_ITRC_CHIP_RSTB_EN - Default the itrc chip reset can reset WLAN, SW can disable this if not required */
+#define SOCCIU_RST_SW_WL_ITRC_CHIP_RSTB_EN(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_WL_ITRC_CHIP_RSTB_EN_SHIFT)) & SOCCIU_RST_SW_WL_ITRC_CHIP_RSTB_EN_MASK)
+
+#define SOCCIU_RST_SW_BLE_ITRC_CHIP_RSTB_EN_MASK (0x400000U)
+#define SOCCIU_RST_SW_BLE_ITRC_CHIP_RSTB_EN_SHIFT (22U)
+/*! BLE_ITRC_CHIP_RSTB_EN - Default the itrc chip reset can reset BLE, SW can disable this if not required */
+#define SOCCIU_RST_SW_BLE_ITRC_CHIP_RSTB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_BLE_ITRC_CHIP_RSTB_EN_SHIFT)) & SOCCIU_RST_SW_BLE_ITRC_CHIP_RSTB_EN_MASK)
+
+#define SOCCIU_RST_SW_MSC_ITRC_CHIP_RSTB_EN_MASK (0x800000U)
+#define SOCCIU_RST_SW_MSC_ITRC_CHIP_RSTB_EN_SHIFT (23U)
+/*! MSC_ITRC_CHIP_RSTB_EN - Default the itrc chip reset can reset MSC, SW can disable this if not required */
+#define SOCCIU_RST_SW_MSC_ITRC_CHIP_RSTB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_RST_SW_MSC_ITRC_CHIP_RSTB_EN_SHIFT)) & SOCCIU_RST_SW_MSC_ITRC_CHIP_RSTB_EN_MASK)
+/*! @} */
+
+/*! @name CHIP_INFO - Chip Information */
+/*! @{ */
+
+#define SOCCIU_CHIP_INFO_REV_NUM_MASK            (0xFFU)
+#define SOCCIU_CHIP_INFO_REV_NUM_SHIFT           (0U)
+/*! REV_NUM - Chip Revision Number */
+#define SOCCIU_CHIP_INFO_REV_NUM(x)              (((uint32_t)(((uint32_t)(x)) << SOCCIU_CHIP_INFO_REV_NUM_SHIFT)) & SOCCIU_CHIP_INFO_REV_NUM_MASK)
+
+#define SOCCIU_CHIP_INFO_ID_MASK                 (0xFF00U)
+#define SOCCIU_CHIP_INFO_ID_SHIFT                (8U)
+/*! ID - Chip ID */
+#define SOCCIU_CHIP_INFO_ID(x)                   (((uint32_t)(((uint32_t)(x)) << SOCCIU_CHIP_INFO_ID_SHIFT)) & SOCCIU_CHIP_INFO_ID_MASK)
+/*! @} */
+
+/*! @name MCI_POWER_MODE_STATUS - MCI POWER MODE Status */
+/*! @{ */
+
+#define SOCCIU_MCI_POWER_MODE_STATUS_MCI_SLP_STATE_MASK (0x7U)
+#define SOCCIU_MCI_POWER_MODE_STATUS_MCI_SLP_STATE_SHIFT (0U)
+/*! MCI_SLP_STATE - MCI Power Mode Status */
+#define SOCCIU_MCI_POWER_MODE_STATUS_MCI_SLP_STATE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_MCI_POWER_MODE_STATUS_MCI_SLP_STATE_SHIFT)) & SOCCIU_MCI_POWER_MODE_STATUS_MCI_SLP_STATE_MASK)
+
+#define SOCCIU_MCI_POWER_MODE_STATUS_MCI_BIST_DONE_MASK (0x8U)
+#define SOCCIU_MCI_POWER_MODE_STATUS_MCI_BIST_DONE_SHIFT (3U)
+/*! MCI_BIST_DONE - MCI g2bist done status */
+#define SOCCIU_MCI_POWER_MODE_STATUS_MCI_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_MCI_POWER_MODE_STATUS_MCI_BIST_DONE_SHIFT)) & SOCCIU_MCI_POWER_MODE_STATUS_MCI_BIST_DONE_MASK)
+
+#define SOCCIU_MCI_POWER_MODE_STATUS_CM33_RESET_N_MASK (0x10U)
+#define SOCCIU_MCI_POWER_MODE_STATUS_CM33_RESET_N_SHIFT (4U)
+/*! CM33_RESET_N - CM33 Reset status. Active low. */
+#define SOCCIU_MCI_POWER_MODE_STATUS_CM33_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_MCI_POWER_MODE_STATUS_CM33_RESET_N_SHIFT)) & SOCCIU_MCI_POWER_MODE_STATUS_CM33_RESET_N_MASK)
+
+#define SOCCIU_MCI_POWER_MODE_STATUS_CPU3_FW_READY_MASK (0x20U)
+#define SOCCIU_MCI_POWER_MODE_STATUS_CPU3_FW_READY_SHIFT (5U)
+/*! CPU3_FW_READY - cpu3 FW sets this bit after cpu1 FW initialization is done. */
+#define SOCCIU_MCI_POWER_MODE_STATUS_CPU3_FW_READY(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_MCI_POWER_MODE_STATUS_CPU3_FW_READY_SHIFT)) & SOCCIU_MCI_POWER_MODE_STATUS_CPU3_FW_READY_MASK)
+/*! @} */
+
+/*! @name PSW_VD2_RDY1 - Power Switch VD2_RDY Status */
+/*! @{ */
+
+#define SOCCIU_PSW_VD2_RDY1_PSW_STATUS_MASK      (0xFFFFFFFFU)
+#define SOCCIU_PSW_VD2_RDY1_PSW_STATUS_SHIFT     (0U)
+/*! PSW_STATUS - VD2_RDY Status of following Power Switches: */
+#define SOCCIU_PSW_VD2_RDY1_PSW_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << SOCCIU_PSW_VD2_RDY1_PSW_STATUS_SHIFT)) & SOCCIU_PSW_VD2_RDY1_PSW_STATUS_MASK)
+/*! @} */
+
+/*! @name WLAN_POWER_STATUS - WLAN POWER Status */
+/*! @{ */
+
+#define SOCCIU_WLAN_POWER_STATUS_WLRET_PSW_PD_MASK (0x1U)
+#define SOCCIU_WLAN_POWER_STATUS_WLRET_PSW_PD_SHIFT (0U)
+/*! WLRET_PSW_PD - WLAN-RETENTION domain power-switch control status: */
+#define SOCCIU_WLAN_POWER_STATUS_WLRET_PSW_PD(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_WLAN_POWER_STATUS_WLRET_PSW_PD_SHIFT)) & SOCCIU_WLAN_POWER_STATUS_WLRET_PSW_PD_MASK)
+
+#define SOCCIU_WLAN_POWER_STATUS_WLGATED_PSW_PD_MASK (0x2U)
+#define SOCCIU_WLAN_POWER_STATUS_WLGATED_PSW_PD_SHIFT (1U)
+/*! WLGATED_PSW_PD - WLAN-GATED domain power-switch control status: */
+#define SOCCIU_WLAN_POWER_STATUS_WLGATED_PSW_PD(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_WLAN_POWER_STATUS_WLGATED_PSW_PD_SHIFT)) & SOCCIU_WLAN_POWER_STATUS_WLGATED_PSW_PD_MASK)
+
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_SLEEP_MASK (0x4U)
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_SLEEP_SHIFT (2U)
+/*! CPU1_SLEEP - CPU1 cp15 sleep status */
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_WLAN_POWER_STATUS_CPU1_SLEEP_SHIFT)) & SOCCIU_WLAN_POWER_STATUS_CPU1_SLEEP_MASK)
+
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_BIST_DONE_MASK (0x8U)
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_BIST_DONE_SHIFT (3U)
+/*! CPU1_BIST_DONE - CPU1 memories g2bist done status */
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_WLAN_POWER_STATUS_CPU1_BIST_DONE_SHIFT)) & SOCCIU_WLAN_POWER_STATUS_CPU1_BIST_DONE_MASK)
+
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_RESET_N_MASK (0x10U)
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_RESET_N_SHIFT (4U)
+/*! CPU1_RESET_N - CPU1 Reset status. Active low. */
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_WLAN_POWER_STATUS_CPU1_RESET_N_SHIFT)) & SOCCIU_WLAN_POWER_STATUS_CPU1_RESET_N_MASK)
+
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_FW_READY_MASK (0x20U)
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_FW_READY_SHIFT (5U)
+/*! CPU1_FW_READY - cpu1 FW sets this bit after cpu1 FW initialization is done. */
+#define SOCCIU_WLAN_POWER_STATUS_CPU1_FW_READY(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_WLAN_POWER_STATUS_CPU1_FW_READY_SHIFT)) & SOCCIU_WLAN_POWER_STATUS_CPU1_FW_READY_MASK)
+/*! @} */
+
+/*! @name BLE_POWER_STATUS - BLE POWER Status */
+/*! @{ */
+
+#define SOCCIU_BLE_POWER_STATUS_BLERET_PSW_PD_MASK (0x1U)
+#define SOCCIU_BLE_POWER_STATUS_BLERET_PSW_PD_SHIFT (0U)
+/*! BLERET_PSW_PD - BLE-RETENTION domain power-switch control status: */
+#define SOCCIU_BLE_POWER_STATUS_BLERET_PSW_PD(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_BLE_POWER_STATUS_BLERET_PSW_PD_SHIFT)) & SOCCIU_BLE_POWER_STATUS_BLERET_PSW_PD_MASK)
+
+#define SOCCIU_BLE_POWER_STATUS_BLEGATED_PSW_PD_MASK (0x2U)
+#define SOCCIU_BLE_POWER_STATUS_BLEGATED_PSW_PD_SHIFT (1U)
+/*! BLEGATED_PSW_PD - BLE-GATED domain power-switch control status: */
+#define SOCCIU_BLE_POWER_STATUS_BLEGATED_PSW_PD(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_BLE_POWER_STATUS_BLEGATED_PSW_PD_SHIFT)) & SOCCIU_BLE_POWER_STATUS_BLEGATED_PSW_PD_MASK)
+
+#define SOCCIU_BLE_POWER_STATUS_CPU2_SLEEP_MASK  (0x4U)
+#define SOCCIU_BLE_POWER_STATUS_CPU2_SLEEP_SHIFT (2U)
+/*! CPU2_SLEEP - CPU2 cp15 sleep status */
+#define SOCCIU_BLE_POWER_STATUS_CPU2_SLEEP(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_BLE_POWER_STATUS_CPU2_SLEEP_SHIFT)) & SOCCIU_BLE_POWER_STATUS_CPU2_SLEEP_MASK)
+
+#define SOCCIU_BLE_POWER_STATUS_CPU2_BIST_DONE_MASK (0x8U)
+#define SOCCIU_BLE_POWER_STATUS_CPU2_BIST_DONE_SHIFT (3U)
+/*! CPU2_BIST_DONE - CPU2 memories g2bist done status */
+#define SOCCIU_BLE_POWER_STATUS_CPU2_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_BLE_POWER_STATUS_CPU2_BIST_DONE_SHIFT)) & SOCCIU_BLE_POWER_STATUS_CPU2_BIST_DONE_MASK)
+
+#define SOCCIU_BLE_POWER_STATUS_CPU2_RESET_N_MASK (0x10U)
+#define SOCCIU_BLE_POWER_STATUS_CPU2_RESET_N_SHIFT (4U)
+/*! CPU2_RESET_N - CPU2 Reset status. Active low. */
+#define SOCCIU_BLE_POWER_STATUS_CPU2_RESET_N(x)  (((uint32_t)(((uint32_t)(x)) << SOCCIU_BLE_POWER_STATUS_CPU2_RESET_N_SHIFT)) & SOCCIU_BLE_POWER_STATUS_CPU2_RESET_N_MASK)
+
+#define SOCCIU_BLE_POWER_STATUS_CPU2_FW_READY_MASK (0x20U)
+#define SOCCIU_BLE_POWER_STATUS_CPU2_FW_READY_SHIFT (5U)
+/*! CPU2_FW_READY - cpu2 FW sets this bit after cpu2 FW initialization is done. */
+#define SOCCIU_BLE_POWER_STATUS_CPU2_FW_READY(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_BLE_POWER_STATUS_CPU2_FW_READY_SHIFT)) & SOCCIU_BLE_POWER_STATUS_CPU2_FW_READY_MASK)
+/*! @} */
+
+/*! @name PAD_VREG_VSENSOR_CTRL - Vsensor and Vreg Pad Control */
+/*! @{ */
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_ENB_MASK (0x1U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_ENB_SHIFT (0U)
+/*! VIO_REG1_ENB - VIO_X1 Pad Regulator */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_ENB(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_ENB_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_ENB_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_CTRL_EN_MASK (0x2U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_CTRL_EN_SHIFT (1U)
+/*! VIO_REG1_CTRL_EN - VIO_X1 Pad Regulator control */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_CTRL_EN_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG1_CTRL_EN_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_ENB_MASK (0x4U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_ENB_SHIFT (2U)
+/*! VIO_REG4_ENB - VIO_4 Pad Regulator */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_ENB(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_ENB_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_ENB_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_CTRL_EN_MASK (0x8U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_CTRL_EN_SHIFT (3U)
+/*! VIO_REG4_CTRL_EN - VIO_X4 Pad Regulator control */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_CTRL_EN_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG4_CTRL_EN_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_ENB_MASK (0x10U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_ENB_SHIFT (4U)
+/*! VIO_REG5_ENB - VIO_5 Pad Regulator */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_ENB(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_ENB_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_ENB_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_CTRL_EN_MASK (0x20U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_CTRL_EN_SHIFT (5U)
+/*! VIO_REG5_CTRL_EN - VIO_X5 Pad Regulator control */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_CTRL_EN_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG5_CTRL_EN_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_ENB_MASK (0x40U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_ENB_SHIFT (6U)
+/*! VIO_REG6_ENB - VIO_6 Pad Regulator */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_ENB(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_ENB_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_ENB_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_CTRL_EN_MASK (0x80U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_CTRL_EN_SHIFT (7U)
+/*! VIO_REG6_CTRL_EN - VIO_X6 Pad Regulator control */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_CTRL_EN_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_REG6_CTRL_EN_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK (0x1000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT (12U)
+/*! VSENSOR_BYPASS - Active High Enable Signal for Bypass Mode */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK (0x2000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT (13U)
+/*! VSENSOR_V18EN_12_IN - Bypass Value when Vsensor_Bypass Bit Set */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK (0x4000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT (14U)
+/*! VSENSOR_DISABLE_12 - Vsensor X1 disable */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK (0x8000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT (15U)
+/*! VSENSOR_CLK_12 - Vsensor Clock */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK (0x10000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT (16U)
+/*! VSENSOR_TE - Vsensor Test Enable */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK (0xE0000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT (17U)
+/*! VSENSOR_TEST - Vsensor Test Point Mux Selection */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TEST(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK (0x100000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT (20U)
+/*! VSENSOR_VTHRESH - Vsensor Detection Threshold */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_V25EN_CORE_MASK (0x200000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT (21U)
+/*! V25EN_CORE - V25EN_CORE */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_V25EN_CORE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_V25EN_CORE_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X0_VSENSOR_DETECT_MASK (0x400000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X0_VSENSOR_DETECT_SHIFT (22U)
+/*! VIO_X0_VSENSOR_DETECT - VIO_X0_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X0_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X0_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X0_VSENSOR_DETECT_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X1_VSENSOR_DETECT_MASK (0x800000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X1_VSENSOR_DETECT_SHIFT (23U)
+/*! VIO_X1_VSENSOR_DETECT - VIO_X1_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X1_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X1_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X1_VSENSOR_DETECT_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X2_VSENSOR_DETECT_MASK (0x1000000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X2_VSENSOR_DETECT_SHIFT (24U)
+/*! VIO_X2_VSENSOR_DETECT - VIO_X2_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X2_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X2_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X2_VSENSOR_DETECT_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X3_VSENSOR_DETECT_MASK (0x2000000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X3_VSENSOR_DETECT_SHIFT (25U)
+/*! VIO_X3_VSENSOR_DETECT - VIO_X3_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X3_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X3_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X3_VSENSOR_DETECT_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X4_VSENSOR_DETECT_MASK (0x4000000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X4_VSENSOR_DETECT_SHIFT (26U)
+/*! VIO_X4_VSENSOR_DETECT - VIO_X4_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X4_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X4_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X4_VSENSOR_DETECT_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X5_VSENSOR_DETECT_MASK (0x8000000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X5_VSENSOR_DETECT_SHIFT (27U)
+/*! VIO_X5_VSENSOR_DETECT - VIO_X5_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X5_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X5_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X5_VSENSOR_DETECT_MASK)
+
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X6_VSENSOR_DETECT_MASK (0x10000000U)
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X6_VSENSOR_DETECT_SHIFT (28U)
+/*! VIO_X6_VSENSOR_DETECT - VIO_X6_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X6_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X6_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_VREG_VSENSOR_CTRL_VIO_X6_VSENSOR_DETECT_MASK)
+/*! @} */
+
+/*! @name PAD_RF_VREG_VSENSOR_CTRL - RF Vsensor and Vreg Pad Control */
+/*! @{ */
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG_ENB_MASK (0x1U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG_ENB_SHIFT (0U)
+/*! VIO_REG_ENB - VIO_RF Pad Regulator */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG_ENB(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG_ENB_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG_ENB_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG0_CTRL_EN_MASK (0x2U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG0_CTRL_EN_SHIFT (1U)
+/*! VIO_REG0_CTRL_EN - VIO reg0 control enable Function */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG0_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG0_CTRL_EN_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VIO_REG0_CTRL_EN_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK (0x10U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT (4U)
+/*! VSENSOR_BYPASS - Active High Enable Signal for Bypass Mode */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK (0x20U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT (5U)
+/*! VSENSOR_V18EN_12_IN - Bypass Value when Vsensor_Bypass Bit Set */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK (0x40U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT (6U)
+/*! VSENSOR_DISABLE_12 - Vsensor RF disable */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK (0x80U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT (7U)
+/*! VSENSOR_CLK_12 - Vsensor RF Clock */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_CLK_12(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK (0x100U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT (8U)
+/*! VSENSOR_TE - Vsensor RF Test Enable */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK (0xE00U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT (9U)
+/*! VSENSOR_TEST - Vsensor RF Test Point Mux Selection */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TEST(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK (0x1000U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT (12U)
+/*! VSENSOR_VTHRESH - Vsensor RF Detection Threshold */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_V25EN_CORE_MASK (0x2000U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT (13U)
+/*! V25EN_CORE - V25EN_CORE */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_V25EN_CORE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_V25EN_CORE_MASK)
+
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DETECT_MASK (0x4000U)
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DETECT_SHIFT (14U)
+/*! VSENSOR_DETECT - VIO_RF_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_RF_VREG_VSENSOR_CTRL_VSENSOR_DETECT_MASK)
+/*! @} */
+
+/*! @name PAD_SD_VREG_VSENSOR_CTRL - SD Vsensor and Vreg Pad Control */
+/*! @{ */
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_ENB_MASK (0x1U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_ENB_SHIFT (0U)
+/*! VIO_REG_ENB - VIO_SD Pad Regulator */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_ENB(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_ENB_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_ENB_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_MASK (0x2U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_SHIFT (1U)
+/*! VIO_REG_CTRL_EN - VIO reg control enable function */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VIO_REG_CTRL_EN_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK (0x10U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT (4U)
+/*! VSENSOR_BYPASS - Active High Enable Signal for Bypass Mode */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_BYPASS_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK (0x20U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT (5U)
+/*! VSENSOR_V18EN_12_IN - Bypass Value when Vsensor_Bypass Bit Set */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_V18EN_12_IN_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK (0x40U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT (6U)
+/*! VSENSOR_DISABLE_12 - Vsensor SD disable */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DISABLE_12_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK (0x80U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT (7U)
+/*! VSENSOR_CLK_12 - Vsensor SD Clock */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_CLK_12_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK (0x100U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT (8U)
+/*! VSENSOR_TE - Vsensor SD Test Enable */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TE_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TE_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK (0xE00U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT (9U)
+/*! VSENSOR_TEST - Vsensor SD Test Point Mux Selection */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TEST(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TEST_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_TEST_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK (0x1000U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT (12U)
+/*! VSENSOR_VTHRESH - Vsensor SD Detection Threshold */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_VTHRESH_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_V25EN_CORE_MASK (0x2000U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT (13U)
+/*! V25EN_CORE - V25EN_CORE */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_V25EN_CORE(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_V25EN_CORE_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_V25EN_CORE_MASK)
+
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DETECT_MASK (0x4000U)
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DETECT_SHIFT (14U)
+/*! VSENSOR_DETECT - VIO_SD_Vsensor_Detect_V18 Status */
+#define SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DETECT_SHIFT)) & SOCCIU_PAD_SD_VREG_VSENSOR_CTRL_VSENSOR_DETECT_MASK)
+/*! @} */
+
+/*! @name PAD_ECO_CTRL - Pad ECO Control */
+/*! @{ */
+
+#define SOCCIU_PAD_ECO_CTRL_ECO_BITS_MASK        (0xFFFFFFFFU)
+#define SOCCIU_PAD_ECO_CTRL_ECO_BITS_SHIFT       (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define SOCCIU_PAD_ECO_CTRL_ECO_BITS(x)          (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_ECO_CTRL_ECO_BITS_SHIFT)) & SOCCIU_PAD_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name TST_TSTBUS_CTRL1 - Testbus Mux Control1 */
+/*! @{ */
+
+#define SOCCIU_TST_TSTBUS_CTRL1_SOC_PERI_TB_SEL_MASK (0x70U)
+#define SOCCIU_TST_TSTBUS_CTRL1_SOC_PERI_TB_SEL_SHIFT (4U)
+/*! SOC_PERI_TB_SEL - Select for soc peri testbus: */
+#define SOCCIU_TST_TSTBUS_CTRL1_SOC_PERI_TB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_TSTBUS_CTRL1_SOC_PERI_TB_SEL_SHIFT)) & SOCCIU_TST_TSTBUS_CTRL1_SOC_PERI_TB_SEL_MASK)
+/*! @} */
+
+/*! @name TST_TSTBUS_CTRL2 - Testbus Mux Control2 */
+/*! @{ */
+
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_SEL_MASK (0xF000U)
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_SEL_SHIFT (12U)
+/*! CLK_OUT_SEL - PAGE 0 */
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_SEL_SHIFT)) & SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_SEL_MASK)
+
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_PAGE_SEL_MASK (0x30000U)
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_PAGE_SEL_SHIFT (16U)
+/*! CLK_OUT_PAGE_SEL - Clock out test page sel */
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_PAGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_PAGE_SEL_SHIFT)) & SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_PAGE_SEL_MASK)
+
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_MASK  (0x40000U)
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_SHIFT (18U)
+/*! CLK_OUT_EN - Clock Out Enable */
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN(x)    (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_SHIFT)) & SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_MASK)
+
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_ALT_MASK (0x80000U)
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_ALT_SHIFT (19U)
+/*! CLK_OUT_EN_ALT - Clock Out Enable */
+#define SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_ALT(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_ALT_SHIFT)) & SOCCIU_TST_TSTBUS_CTRL2_CLK_OUT_EN_ALT_MASK)
+
+#define SOCCIU_TST_TSTBUS_CTRL2_POR_MON_SEL_MASK (0x100000U)
+#define SOCCIU_TST_TSTBUS_CTRL2_POR_MON_SEL_SHIFT (20U)
+/*! POR_MON_SEL - POR MON Testbus Select (to support more power domain busses) */
+#define SOCCIU_TST_TSTBUS_CTRL2_POR_MON_SEL(x)   (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_TSTBUS_CTRL2_POR_MON_SEL_SHIFT)) & SOCCIU_TST_TSTBUS_CTRL2_POR_MON_SEL_MASK)
+/*! @} */
+
+/*! @name TST_CTRL - Test Control */
+/*! @{ */
+
+#define SOCCIU_TST_CTRL_RBIST_DONE_MASK          (0xFU)
+#define SOCCIU_TST_CTRL_RBIST_DONE_SHIFT         (0U)
+/*! RBIST_DONE - [3]: HMAC g2bist finish */
+#define SOCCIU_TST_CTRL_RBIST_DONE(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_CTRL_RBIST_DONE_SHIFT)) & SOCCIU_TST_CTRL_RBIST_DONE_MASK)
+/*! @} */
+
+/*! @name TST_ECO_CTRL - Test ECO Control */
+/*! @{ */
+
+#define SOCCIU_TST_ECO_CTRL_ECO_BITS_MASK        (0xFFFFFFFFU)
+#define SOCCIU_TST_ECO_CTRL_ECO_BITS_SHIFT       (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define SOCCIU_TST_ECO_CTRL_ECO_BITS(x)          (((uint32_t)(((uint32_t)(x)) << SOCCIU_TST_ECO_CTRL_ECO_BITS_SHIFT)) & SOCCIU_TST_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name DRO_CTRL - DRO Control */
+/*! @{ */
+
+#define SOCCIU_DRO_CTRL_DRO_EN_MASK              (0x1U)
+#define SOCCIU_DRO_CTRL_DRO_EN_SHIFT             (0U)
+/*! DRO_EN - DRO Counter Enable */
+#define SOCCIU_DRO_CTRL_DRO_EN(x)                (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_CTRL_DRO_EN_SHIFT)) & SOCCIU_DRO_CTRL_DRO_EN_MASK)
+
+#define SOCCIU_DRO_CTRL_DRO_CLK_GATE_EN_MASK     (0x2U)
+#define SOCCIU_DRO_CTRL_DRO_CLK_GATE_EN_SHIFT    (1U)
+/*! DRO_CLK_GATE_EN - DRO Clock Gate Enable */
+#define SOCCIU_DRO_CTRL_DRO_CLK_GATE_EN(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_CTRL_DRO_CLK_GATE_EN_SHIFT)) & SOCCIU_DRO_CTRL_DRO_CLK_GATE_EN_MASK)
+
+#define SOCCIU_DRO_CTRL_DRO_CNT_STATUS_MASK      (0x4U)
+#define SOCCIU_DRO_CTRL_DRO_CNT_STATUS_SHIFT     (2U)
+/*! DRO_CNT_STATUS - 0: dro counter is stopped; 1: dro counter is in process */
+#define SOCCIU_DRO_CTRL_DRO_CNT_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_CTRL_DRO_CNT_STATUS_SHIFT)) & SOCCIU_DRO_CTRL_DRO_CNT_STATUS_MASK)
+
+#define SOCCIU_DRO_CTRL_DRO_COUNT_LIMIT_MASK     (0xFFFFFFF0U)
+#define SOCCIU_DRO_CTRL_DRO_COUNT_LIMIT_SHIFT    (4U)
+/*! DRO_COUNT_LIMIT - DRO Count Value */
+#define SOCCIU_DRO_CTRL_DRO_COUNT_LIMIT(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_CTRL_DRO_COUNT_LIMIT_SHIFT)) & SOCCIU_DRO_CTRL_DRO_COUNT_LIMIT_MASK)
+/*! @} */
+
+/*! @name DRO_1_2_CNT - DRO1 and DRO2 Counter Read back */
+/*! @{ */
+
+#define SOCCIU_DRO_1_2_CNT_DRO2_CNT_MASK         (0xFFFFU)
+#define SOCCIU_DRO_1_2_CNT_DRO2_CNT_SHIFT        (0U)
+/*! DRO2_CNT - DRO2 Count */
+#define SOCCIU_DRO_1_2_CNT_DRO2_CNT(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_1_2_CNT_DRO2_CNT_SHIFT)) & SOCCIU_DRO_1_2_CNT_DRO2_CNT_MASK)
+
+#define SOCCIU_DRO_1_2_CNT_DRO1_CNT_MASK         (0xFFFF0000U)
+#define SOCCIU_DRO_1_2_CNT_DRO1_CNT_SHIFT        (16U)
+/*! DRO1_CNT - DRO1 Count */
+#define SOCCIU_DRO_1_2_CNT_DRO1_CNT(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_1_2_CNT_DRO1_CNT_SHIFT)) & SOCCIU_DRO_1_2_CNT_DRO1_CNT_MASK)
+/*! @} */
+
+/*! @name DRO_3_CNT - DRO3 Counter Read back */
+/*! @{ */
+
+#define SOCCIU_DRO_3_CNT_DRO3_CNT_MASK           (0xFFFFU)
+#define SOCCIU_DRO_3_CNT_DRO3_CNT_SHIFT          (0U)
+/*! DRO3_CNT - DRO3 Count */
+#define SOCCIU_DRO_3_CNT_DRO3_CNT(x)             (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_3_CNT_DRO3_CNT_SHIFT)) & SOCCIU_DRO_3_CNT_DRO3_CNT_MASK)
+/*! @} */
+
+/*! @name DRO_PAR_SEL - DRO Parallel Counter Selection */
+/*! @{ */
+
+#define SOCCIU_DRO_PAR_SEL_DRO1_PAR_SEL_MASK     (0x3U)
+#define SOCCIU_DRO_PAR_SEL_DRO1_PAR_SEL_SHIFT    (0U)
+/*! DRO1_PAR_SEL - DRO1 counter selection */
+#define SOCCIU_DRO_PAR_SEL_DRO1_PAR_SEL(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_PAR_SEL_DRO1_PAR_SEL_SHIFT)) & SOCCIU_DRO_PAR_SEL_DRO1_PAR_SEL_MASK)
+
+#define SOCCIU_DRO_PAR_SEL_DRO2_PAR_SEL_MASK     (0xCU)
+#define SOCCIU_DRO_PAR_SEL_DRO2_PAR_SEL_SHIFT    (2U)
+/*! DRO2_PAR_SEL - DRO2 counter selection */
+#define SOCCIU_DRO_PAR_SEL_DRO2_PAR_SEL(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_PAR_SEL_DRO2_PAR_SEL_SHIFT)) & SOCCIU_DRO_PAR_SEL_DRO2_PAR_SEL_MASK)
+
+#define SOCCIU_DRO_PAR_SEL_DRO3_PAR_SEL_MASK     (0x30U)
+#define SOCCIU_DRO_PAR_SEL_DRO3_PAR_SEL_SHIFT    (4U)
+/*! DRO3_PAR_SEL - DRO3 counter selection */
+#define SOCCIU_DRO_PAR_SEL_DRO3_PAR_SEL(x)       (((uint32_t)(((uint32_t)(x)) << SOCCIU_DRO_PAR_SEL_DRO3_PAR_SEL_SHIFT)) & SOCCIU_DRO_PAR_SEL_DRO3_PAR_SEL_MASK)
+/*! @} */
+
+/*! @name CLK_SOCCLK_CTRL - SOC Clock Control */
+/*! @{ */
+
+#define SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_PCLK_DIV_SEL_MASK (0xFU)
+#define SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_PCLK_DIV_SEL_SHIFT (0U)
+/*! SOC_TOP_AHB2APB_PCLK_DIV_SEL - SOC_TOP AHB2APB PCLK Divider Select */
+#define SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_PCLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_PCLK_DIV_SEL_SHIFT)) & SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_PCLK_DIV_SEL_MASK)
+
+#define SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_WAIT_CYCLES_MASK (0xF0U)
+#define SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_WAIT_CYCLES_SHIFT (4U)
+/*! SOC_TOP_AHB2APB_WAIT_CYCLES - SOC_TOP AHB2APB Wait Cycles between each APB transaction */
+#define SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_WAIT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_WAIT_CYCLES_SHIFT)) & SOCCIU_CLK_SOCCLK_CTRL_SOC_TOP_AHB2APB_WAIT_CYCLES_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_PU_PD_DIS0 - Pad Sleep Pullup and Pulldown Disable1 */
+/*! @{ */
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO0_PU_PD_DIS_MASK (0x1U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO0_PU_PD_DIS_SHIFT (0U)
+/*! GPIO0_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[0] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO0_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO0_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO0_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO1_PU_PD_DIS_MASK (0x2U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO1_PU_PD_DIS_SHIFT (1U)
+/*! GPIO1_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[1] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO1_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO1_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO1_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO2_PU_PD_DIS_MASK (0x4U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO2_PU_PD_DIS_SHIFT (2U)
+/*! GPIO2_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[2] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO2_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO2_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO2_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO3_PU_PD_DIS_MASK (0x8U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO3_PU_PD_DIS_SHIFT (3U)
+/*! GPIO3_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[3] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO3_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO3_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO3_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO4_PU_PD_DIS_MASK (0x10U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO4_PU_PD_DIS_SHIFT (4U)
+/*! GPIO4_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[4] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO4_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO4_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO4_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO5_PU_PD_DIS_MASK (0x20U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO5_PU_PD_DIS_SHIFT (5U)
+/*! GPIO5_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[5] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO5_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO5_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO5_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO6_PU_PD_DIS_MASK (0x40U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO6_PU_PD_DIS_SHIFT (6U)
+/*! GPIO6_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[6] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO6_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO6_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO6_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO7_PU_PD_DIS_MASK (0x80U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO7_PU_PD_DIS_SHIFT (7U)
+/*! GPIO7_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[7] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO7_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO7_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO7_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO8_PU_PD_DIS_MASK (0x100U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO8_PU_PD_DIS_SHIFT (8U)
+/*! GPIO8_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[8] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO8_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO8_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO8_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO9_PU_PD_DIS_MASK (0x200U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO9_PU_PD_DIS_SHIFT (9U)
+/*! GPIO9_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[9] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO9_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO9_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO9_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO10_PU_PD_DIS_MASK (0x400U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO10_PU_PD_DIS_SHIFT (10U)
+/*! GPIO10_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[10] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO10_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO10_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO10_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO11_PU_PD_DIS_MASK (0x800U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO11_PU_PD_DIS_SHIFT (11U)
+/*! GPIO11_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[11] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO11_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO11_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO11_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO12_PU_PD_DIS_MASK (0x1000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO12_PU_PD_DIS_SHIFT (12U)
+/*! GPIO12_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[12] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO12_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO12_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO12_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO13_PU_PD_DIS_MASK (0x2000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO13_PU_PD_DIS_SHIFT (13U)
+/*! GPIO13_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[13] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO13_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO13_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO13_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO14_PU_PD_DIS_MASK (0x4000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO14_PU_PD_DIS_SHIFT (14U)
+/*! GPIO14_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[14] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO14_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO14_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO14_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO15_PU_PD_DIS_MASK (0x8000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO15_PU_PD_DIS_SHIFT (15U)
+/*! GPIO15_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[15] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO15_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO15_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO15_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO16_PU_PD_DIS_MASK (0x10000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO16_PU_PD_DIS_SHIFT (16U)
+/*! GPIO16_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[16] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO16_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO16_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO16_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO17_PU_PD_DIS_MASK (0x20000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO17_PU_PD_DIS_SHIFT (17U)
+/*! GPIO17_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[17] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO17_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO17_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO17_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO18_PU_PD_DIS_MASK (0x40000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO18_PU_PD_DIS_SHIFT (18U)
+/*! GPIO18_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[18] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO18_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO18_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO18_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO19_PU_PD_DIS_MASK (0x80000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO19_PU_PD_DIS_SHIFT (19U)
+/*! GPIO19_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[19] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO19_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO19_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO19_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO20_PU_PD_DIS_MASK (0x100000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO20_PU_PD_DIS_SHIFT (20U)
+/*! GPIO20_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[20] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO20_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO20_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO20_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO21_PU_PD_DIS_MASK (0x200000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO21_PU_PD_DIS_SHIFT (21U)
+/*! GPIO21_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[21] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO21_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO21_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO21_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO28_PU_PD_DIS_MASK (0x10000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO28_PU_PD_DIS_SHIFT (28U)
+/*! GPIO28_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[28] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO28_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO28_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO28_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO29_PU_PD_DIS_MASK (0x20000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO29_PU_PD_DIS_SHIFT (29U)
+/*! GPIO29_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[29] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO29_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO29_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO29_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO30_PU_PD_DIS_MASK (0x40000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO30_PU_PD_DIS_SHIFT (30U)
+/*! GPIO30_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[30] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO30_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO30_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO30_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO31_PU_PD_DIS_MASK (0x80000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO31_PU_PD_DIS_SHIFT (31U)
+/*! GPIO31_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[31] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO31_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO31_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS0_GPIO31_PU_PD_DIS_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_PU_PD_DIS1 - Pad Sleep Pullup and Pulldown Disable2 */
+/*! @{ */
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO32_PU_PD_DIS_MASK (0x1U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO32_PU_PD_DIS_SHIFT (0U)
+/*! GPIO32_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[32] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO32_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO32_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO32_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO33_PU_PD_DIS_MASK (0x2U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO33_PU_PD_DIS_SHIFT (1U)
+/*! GPIO33_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[33] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO33_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO33_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO33_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO34_PU_PD_DIS_MASK (0x4U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO34_PU_PD_DIS_SHIFT (2U)
+/*! GPIO34_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[34] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO34_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO34_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO34_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO35_PU_PD_DIS_MASK (0x8U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO35_PU_PD_DIS_SHIFT (3U)
+/*! GPIO35_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[35] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO35_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO35_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO35_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO36_PU_PD_DIS_MASK (0x10U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO36_PU_PD_DIS_SHIFT (4U)
+/*! GPIO36_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[36] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO36_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO36_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO36_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO37_PU_PD_DIS_MASK (0x20U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO37_PU_PD_DIS_SHIFT (5U)
+/*! GPIO37_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[37] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO37_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO37_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO37_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO38_PU_PD_DIS_MASK (0x40U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO38_PU_PD_DIS_SHIFT (6U)
+/*! GPIO38_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[38] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO38_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO38_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO38_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO39_PU_PD_DIS_MASK (0x80U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO39_PU_PD_DIS_SHIFT (7U)
+/*! GPIO39_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[39] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO39_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO39_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO39_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO40_PU_PD_DIS_MASK (0x100U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO40_PU_PD_DIS_SHIFT (8U)
+/*! GPIO40_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[40] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO40_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO40_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO40_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO41_PU_PD_DIS_MASK (0x200U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO41_PU_PD_DIS_SHIFT (9U)
+/*! GPIO41_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[41] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO41_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO41_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO41_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO42_PU_PD_DIS_MASK (0x400U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO42_PU_PD_DIS_SHIFT (10U)
+/*! GPIO42_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[42] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO42_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO42_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO42_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO43_PU_PD_DIS_MASK (0x800U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO43_PU_PD_DIS_SHIFT (11U)
+/*! GPIO43_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[43] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO43_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO43_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO43_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO44_PU_PD_DIS_MASK (0x1000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO44_PU_PD_DIS_SHIFT (12U)
+/*! GPIO44_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[44] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO44_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO44_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO44_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO45_PU_PD_DIS_MASK (0x2000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO45_PU_PD_DIS_SHIFT (13U)
+/*! GPIO45_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[45] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO45_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO45_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO45_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO46_PU_PD_DIS_MASK (0x4000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO46_PU_PD_DIS_SHIFT (14U)
+/*! GPIO46_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[46] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO46_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO46_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO46_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO47_PU_PD_DIS_MASK (0x8000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO47_PU_PD_DIS_SHIFT (15U)
+/*! GPIO47_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[47] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO47_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO47_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO47_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO48_PU_PD_DIS_MASK (0x10000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO48_PU_PD_DIS_SHIFT (16U)
+/*! GPIO48_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[48] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO48_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO48_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO48_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO49_PU_PD_DIS_MASK (0x20000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO49_PU_PD_DIS_SHIFT (17U)
+/*! GPIO49_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[49] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO49_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO49_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO49_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO50_PU_PD_DIS_MASK (0x40000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO50_PU_PD_DIS_SHIFT (18U)
+/*! GPIO50_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[50] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO50_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO50_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO50_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO51_PU_PD_DIS_MASK (0x80000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO51_PU_PD_DIS_SHIFT (19U)
+/*! GPIO51_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[51] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO51_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO51_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO51_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO52_PU_PD_DIS_MASK (0x100000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO52_PU_PD_DIS_SHIFT (20U)
+/*! GPIO52_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[52] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO52_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO52_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO52_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO53_PU_PD_DIS_MASK (0x200000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO53_PU_PD_DIS_SHIFT (21U)
+/*! GPIO53_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[53] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO53_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO53_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO53_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO54_PU_PD_DIS_MASK (0x400000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO54_PU_PD_DIS_SHIFT (22U)
+/*! GPIO54_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[54] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO54_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO54_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO54_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO55_PU_PD_DIS_MASK (0x800000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO55_PU_PD_DIS_SHIFT (23U)
+/*! GPIO55_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[55] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO55_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO55_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO55_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO56_PU_PD_DIS_MASK (0x1000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO56_PU_PD_DIS_SHIFT (24U)
+/*! GPIO56_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[56] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO56_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO56_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO56_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO57_PU_PD_DIS_MASK (0x2000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO57_PU_PD_DIS_SHIFT (25U)
+/*! GPIO57_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[57] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO57_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO57_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO57_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO58_PU_PD_DIS_MASK (0x4000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO58_PU_PD_DIS_SHIFT (26U)
+/*! GPIO58_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[58] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO58_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO58_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO58_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO59_PU_PD_DIS_MASK (0x8000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO59_PU_PD_DIS_SHIFT (27U)
+/*! GPIO59_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[59] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO59_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO59_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO59_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO60_PU_PD_DIS_MASK (0x10000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO60_PU_PD_DIS_SHIFT (28U)
+/*! GPIO60_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[60] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO60_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO60_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO60_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO61_PU_PD_DIS_MASK (0x20000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO61_PU_PD_DIS_SHIFT (29U)
+/*! GPIO61_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[61] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO61_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO61_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO61_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO62_PU_PD_DIS_MASK (0x40000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO62_PU_PD_DIS_SHIFT (30U)
+/*! GPIO62_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[62] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO62_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO62_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO62_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO63_PU_PD_DIS_MASK (0x80000000U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO63_PU_PD_DIS_SHIFT (31U)
+/*! GPIO63_PU_PD_DIS - Internal Pd and Internal Pu Disable for GPIO[63] During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO63_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO63_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS1_GPIO63_PU_PD_DIS_MASK)
+/*! @} */
+
+/*! @name PAD_SLP_PU_PD_DIS2 - Pad Sleep Pullup and Pulldown Disable4 */
+/*! @{ */
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST0_PU_PD_DIS_MASK (0x1U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST0_PU_PD_DIS_SHIFT (0U)
+/*! ATEST0_PU_PD_DIS - Internal Pd and Internal Pu Disable for ATEST0 During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST0_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST0_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST0_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST1_PU_PD_DIS_MASK (0x2U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST1_PU_PD_DIS_SHIFT (1U)
+/*! ATEST1_PU_PD_DIS - Internal Pd and Internal Pu Disable for ATEST1 During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST1_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST1_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST1_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST2_PU_PD_DIS_MASK (0x4U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST2_PU_PD_DIS_SHIFT (2U)
+/*! ATEST2_PU_PD_DIS - Internal Pd and Internal Pu Disable for ATEST2 During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST2_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST2_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST2_PU_PD_DIS_MASK)
+
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST3_PU_PD_DIS_MASK (0x8U)
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST3_PU_PD_DIS_SHIFT (3U)
+/*! ATEST3_PU_PD_DIS - Internal Pd and Internal Pu Disable for ATEST3 During Sleep Mode */
+#define SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST3_PU_PD_DIS(x) (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST3_PU_PD_DIS_SHIFT)) & SOCCIU_PAD_SLP_PU_PD_DIS2_ATEST3_PU_PD_DIS_MASK)
+/*! @} */
+
+/*! @name PAD_GPIO - GPIO Enable */
+/*! @{ */
+
+#define SOCCIU_PAD_GPIO_ENABLE_MASK              (0xFFFFU)
+#define SOCCIU_PAD_GPIO_ENABLE_SHIFT             (0U)
+/*! ENABLE - GPIO Automatic Forcing for GPIO[15:0] */
+#define SOCCIU_PAD_GPIO_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << SOCCIU_PAD_GPIO_ENABLE_SHIFT)) & SOCCIU_PAD_GPIO_ENABLE_MASK)
+/*! @} */
+
+/*! @name MCI_IOMUX_EN0 - mci_iomux_enable control for GPIO[31:28] and GPIO[21:0] */
+/*! @{ */
+
+#define SOCCIU_MCI_IOMUX_EN0_EN_21_0_MASK        (0x3FFFFFU)
+#define SOCCIU_MCI_IOMUX_EN0_EN_21_0_SHIFT       (0U)
+/*! EN_21_0 - Bitwise enable control for mci_io_mux GPIO[21:0] */
+#define SOCCIU_MCI_IOMUX_EN0_EN_21_0(x)          (((uint32_t)(((uint32_t)(x)) << SOCCIU_MCI_IOMUX_EN0_EN_21_0_SHIFT)) & SOCCIU_MCI_IOMUX_EN0_EN_21_0_MASK)
+
+#define SOCCIU_MCI_IOMUX_EN0_EN_31_28_MASK       (0xF0000000U)
+#define SOCCIU_MCI_IOMUX_EN0_EN_31_28_SHIFT      (28U)
+/*! EN_31_28 - Bitwise enable control for mci_io_mux GPIO[31:28] */
+#define SOCCIU_MCI_IOMUX_EN0_EN_31_28(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_MCI_IOMUX_EN0_EN_31_28_SHIFT)) & SOCCIU_MCI_IOMUX_EN0_EN_31_28_MASK)
+/*! @} */
+
+/*! @name MCI_IOMUX_EN1 - mci_iomux_enable control for GPIO[63:32] */
+/*! @{ */
+
+#define SOCCIU_MCI_IOMUX_EN1_EN_MASK             (0xFFFFFFFFU)
+#define SOCCIU_MCI_IOMUX_EN1_EN_SHIFT            (0U)
+/*! EN - Bitwise enable control for mci_io_mux GPIO[63:32] */
+#define SOCCIU_MCI_IOMUX_EN1_EN(x)               (((uint32_t)(((uint32_t)(x)) << SOCCIU_MCI_IOMUX_EN1_EN_SHIFT)) & SOCCIU_MCI_IOMUX_EN1_EN_MASK)
+/*! @} */
+
+/*! @name CAU_CTRL - CAU Control */
+/*! @{ */
+
+#define SOCCIU_CAU_CTRL_CAU_REFCLK_SEL_MASK      (0x800U)
+#define SOCCIU_CAU_CTRL_CAU_REFCLK_SEL_SHIFT     (11U)
+/*! CAU_REFCLK_SEL - CAU Reference Clock Select */
+#define SOCCIU_CAU_CTRL_CAU_REFCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << SOCCIU_CAU_CTRL_CAU_REFCLK_SEL_SHIFT)) & SOCCIU_CAU_CTRL_CAU_REFCLK_SEL_MASK)
+
+#define SOCCIU_CAU_CTRL_CAU_BG_RDY_MASK          (0x80000U)
+#define SOCCIU_CAU_CTRL_CAU_BG_RDY_SHIFT         (19U)
+/*! CAU_BG_RDY - CAU bandgap Status */
+#define SOCCIU_CAU_CTRL_CAU_BG_RDY(x)            (((uint32_t)(((uint32_t)(x)) << SOCCIU_CAU_CTRL_CAU_BG_RDY_SHIFT)) & SOCCIU_CAU_CTRL_CAU_BG_RDY_MASK)
+
+#define SOCCIU_CAU_CTRL_BUCK_VOUT_RDY_MASK       (0x100000U)
+#define SOCCIU_CAU_CTRL_BUCK_VOUT_RDY_SHIFT      (20U)
+/*! BUCK_VOUT_RDY - Buck power Status */
+#define SOCCIU_CAU_CTRL_BUCK_VOUT_RDY(x)         (((uint32_t)(((uint32_t)(x)) << SOCCIU_CAU_CTRL_BUCK_VOUT_RDY_SHIFT)) & SOCCIU_CAU_CTRL_BUCK_VOUT_RDY_MASK)
+
+#define SOCCIU_CAU_CTRL_REF_CLK_RDY_MASK         (0x200000U)
+#define SOCCIU_CAU_CTRL_REF_CLK_RDY_SHIFT        (21U)
+/*! REF_CLK_RDY - CAU Ref clock Ready Status */
+#define SOCCIU_CAU_CTRL_REF_CLK_RDY(x)           (((uint32_t)(((uint32_t)(x)) << SOCCIU_CAU_CTRL_REF_CLK_RDY_SHIFT)) & SOCCIU_CAU_CTRL_REF_CLK_RDY_MASK)
+/*! @} */
+
+/*! @name SYSPLL_CTRL - SYSPLL Control */
+/*! @{ */
+
+#define SOCCIU_SYSPLL_CTRL_T3_PLL_LOCK_MASK      (0x400U)
+#define SOCCIU_SYSPLL_CTRL_T3_PLL_LOCK_SHIFT     (10U)
+/*! T3_PLL_LOCK - PLL T3 Lock Status */
+#define SOCCIU_SYSPLL_CTRL_T3_PLL_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << SOCCIU_SYSPLL_CTRL_T3_PLL_LOCK_SHIFT)) & SOCCIU_SYSPLL_CTRL_T3_PLL_LOCK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SOCCIU_Register_Masks */
+
+
+/* SOCCIU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SOCCTRL base address */
+  #define SOCCTRL_BASE                             (0x55001000u)
+  /** Peripheral SOCCTRL base address */
+  #define SOCCTRL_BASE_NS                          (0x45001000u)
+  /** Peripheral SOCCTRL base pointer */
+  #define SOCCTRL                                  ((SOCCIU_Type *)SOCCTRL_BASE)
+  /** Peripheral SOCCTRL base pointer */
+  #define SOCCTRL_NS                               ((SOCCIU_Type *)SOCCTRL_BASE_NS)
+  /** Array initializer of SOCCIU peripheral base addresses */
+  #define SOCCIU_BASE_ADDRS                        { SOCCTRL_BASE }
+  /** Array initializer of SOCCIU peripheral base pointers */
+  #define SOCCIU_BASE_PTRS                         { SOCCTRL }
+  /** Array initializer of SOCCIU peripheral base addresses */
+  #define SOCCIU_BASE_ADDRS_NS                     { SOCCTRL_BASE_NS }
+  /** Array initializer of SOCCIU peripheral base pointers */
+  #define SOCCIU_BASE_PTRS_NS                      { SOCCTRL_NS }
+#else
+  /** Peripheral SOCCTRL base address */
+  #define SOCCTRL_BASE                             (0x45001000u)
+  /** Peripheral SOCCTRL base pointer */
+  #define SOCCTRL                                  ((SOCCIU_Type *)SOCCTRL_BASE)
+  /** Array initializer of SOCCIU peripheral base addresses */
+  #define SOCCIU_BASE_ADDRS                        { SOCCTRL_BASE }
+  /** Array initializer of SOCCIU peripheral base pointers */
+  #define SOCCIU_BASE_PTRS                         { SOCCTRL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SOCCIU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SOC_OTP_CTRL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SOC_OTP_CTRL_Peripheral_Access_Layer SOC_OTP_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** SOC_OTP_CTRL - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[512];
+  __IO uint16_t OTP_SPARE0;                        /**< OTP_SPARE0_REG, offset: 0x200 */
+       uint8_t RESERVED_1[2];
+  __IO uint16_t OTP_SPARE1;                        /**< OTP_SPARE1_REG, offset: 0x204 */
+       uint8_t RESERVED_2[2];
+  __O  uint16_t OTP_WDATA0;                        /**< OTP_WDATA0_REG, offset: 0x208 */
+       uint8_t RESERVED_3[2];
+  __IO uint16_t OTP_WDATA1;                        /**< OTP_WDATA1_REG, offset: 0x20C */
+       uint8_t RESERVED_4[2];
+  __IO uint16_t OTP_WDATA2;                        /**< OTP_WDATA2_REG, offset: 0x210 */
+       uint8_t RESERVED_5[2];
+  __IO uint16_t OTP_WDATA3;                        /**< OTP_WDATA3_REG, offset: 0x214 */
+       uint8_t RESERVED_6[2];
+  __I  uint16_t OTP_WDATA4;                        /**< OTP_WDATA4_REG, offset: 0x218 */
+       uint8_t RESERVED_7[2];
+  __IO uint16_t OTP_ADDR;                          /**< OTP_ADDR_REG, offset: 0x21C */
+       uint8_t RESERVED_8[2];
+  __IO uint16_t OTP_CTRL0;                         /**< OTP_CTRL0_REG, offset: 0x220 */
+       uint8_t RESERVED_9[2];
+  __IO uint16_t OTP_CTRL1;                         /**< OTP_CTRL1_REG, offset: 0x224 */
+       uint8_t RESERVED_10[2];
+  __IO uint16_t OTP_CMD_START;                     /**< OTP_CMD_START_REG, offset: 0x228 */
+       uint8_t RESERVED_11[2];
+  __IO uint16_t OTP_PARAM0;                        /**< OTP_PARAM0_REG, offset: 0x22C */
+       uint8_t RESERVED_12[2];
+  __IO uint16_t OTP_PARAM1;                        /**< OTP_PARAM1_REG, offset: 0x230 */
+       uint8_t RESERVED_13[2];
+  __IO uint16_t OTP_PARAM2;                        /**< OTP_PARAM2_REG, offset: 0x234 */
+       uint8_t RESERVED_14[2];
+  __IO uint16_t OTP_BYPASS_MODE0;                  /**< OTP_BYPASS_MODE0_REG, offset: 0x238 */
+       uint8_t RESERVED_15[2];
+  __IO uint16_t OTP_BYPASS_MODE1;                  /**< OTP_BYPASS_MODE1_REG, offset: 0x23C */
+       uint8_t RESERVED_16[2];
+  __IO uint16_t OTP_TESTBUS_SEL;                   /**< OTP_TESTBUS_SEL_REG, offset: 0x240 */
+       uint8_t RESERVED_17[2];
+  __I  uint16_t OTP_TESTBUS;                       /**< OTP_TESTBUS_REG, offset: 0x244 */
+       uint8_t RESERVED_18[2];
+  __IO uint16_t OTP_BYPASS_MODE2;                  /**< OTP_BYPASS_MODE2_REG, offset: 0x248 */
+       uint8_t RESERVED_19[2];
+  __IO uint16_t OTP_RST_B;                         /**< OTP_RST_B_REG, offset: 0x24C */
+       uint8_t RESERVED_20[2];
+  __IO uint16_t OTP_POR_B;                         /**< OTP_POR_B_REG, offset: 0x250 */
+       uint8_t RESERVED_21[10];
+  __IO uint16_t OTP_WRITE_LOCK_REG;                /**< OTP_WRITE_LOCK_REG (Firecrest), offset: 0x25C */
+       uint8_t RESERVED_22[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_15_0;            /**< OTP_WRITE_DIS_REG[15:0] (Firecrest), offset: 0x260 */
+       uint8_t RESERVED_23[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_31_16;           /**< OTP_WRITE_DIS_REG[31:16] (Firecrest), offset: 0x264 */
+       uint8_t RESERVED_24[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_47_32;           /**< OTP_WRITE_DIS_REG[47:32] (Firecrest), offset: 0x268 */
+       uint8_t RESERVED_25[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_63_48;           /**< OTP_WRITE_DIS_REG[63:48] (Firecrest), offset: 0x26C */
+       uint8_t RESERVED_26[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_79_64;           /**< OTP_WRITE_DIS_REG[79:64] (Firecrest), offset: 0x270 */
+       uint8_t RESERVED_27[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_95_80;           /**< OTP_WRITE_DIS_REG[95:80] (Firecrest), offset: 0x274 */
+       uint8_t RESERVED_28[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_111_96;          /**< OTP_WRITE_DIS_REG[111:96] (Firecrest), offset: 0x278 */
+       uint8_t RESERVED_29[2];
+  __IO uint16_t OTP_WRITE_DIS_REG_127_112;         /**< OTP_WRITE_DIS_REG[127:112] (Firecrest), offset: 0x27C */
+} SOC_OTP_CTRL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SOC_OTP_CTRL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SOC_OTP_CTRL_Register_Masks SOC_OTP_CTRL Register Masks
+ * @{
+ */
+
+/*! @name OTP_SPARE0 - OTP_SPARE0_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_SPARE0_OTP_SPARE0_MASK  (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_SPARE0_OTP_SPARE0_SHIFT (0U)
+/*! OTP_SPARE0 - SPARE register for future ECO's, h/w default is 0x0000 */
+#define SOC_OTP_CTRL_OTP_SPARE0_OTP_SPARE0(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_SPARE0_OTP_SPARE0_SHIFT)) & SOC_OTP_CTRL_OTP_SPARE0_OTP_SPARE0_MASK)
+/*! @} */
+
+/*! @name OTP_SPARE1 - OTP_SPARE1_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_SPARE1_OTP_SPARE1_MASK  (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_SPARE1_OTP_SPARE1_SHIFT (0U)
+/*! OTP_SPARE1 - SPARE register for future ECO's, h/w default is 0xFFFF */
+#define SOC_OTP_CTRL_OTP_SPARE1_OTP_SPARE1(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_SPARE1_OTP_SPARE1_SHIFT)) & SOC_OTP_CTRL_OTP_SPARE1_OTP_SPARE1_MASK)
+/*! @} */
+
+/*! @name OTP_WDATA0 - OTP_WDATA0_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WDATA0_OTP_WDATA0_MASK  (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WDATA0_OTP_WDATA0_SHIFT (0U)
+/*! OTP_WDATA0 - Data[15:0] */
+#define SOC_OTP_CTRL_OTP_WDATA0_OTP_WDATA0(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA0_OTP_WDATA0_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA0_OTP_WDATA0_MASK)
+/*! @} */
+
+/*! @name OTP_WDATA1 - OTP_WDATA1_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WDATA1_OTP_WDATA1_MASK  (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WDATA1_OTP_WDATA1_SHIFT (0U)
+/*! OTP_WDATA1 - Data[31:16] */
+#define SOC_OTP_CTRL_OTP_WDATA1_OTP_WDATA1(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA1_OTP_WDATA1_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA1_OTP_WDATA1_MASK)
+/*! @} */
+
+/*! @name OTP_WDATA2 - OTP_WDATA2_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WDATA2_OTP_WDATA2_MASK  (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WDATA2_OTP_WDATA2_SHIFT (0U)
+/*! OTP_WDATA2 - Data[47:32] */
+#define SOC_OTP_CTRL_OTP_WDATA2_OTP_WDATA2(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA2_OTP_WDATA2_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA2_OTP_WDATA2_MASK)
+/*! @} */
+
+/*! @name OTP_WDATA3 - OTP_WDATA3_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WDATA3_OTP_WDATA3_MASK  (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WDATA3_OTP_WDATA3_SHIFT (0U)
+/*! OTP_WDATA3 - Data[63:48] */
+#define SOC_OTP_CTRL_OTP_WDATA3_OTP_WDATA3(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA3_OTP_WDATA3_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA3_OTP_WDATA3_MASK)
+/*! @} */
+
+/*! @name OTP_WDATA4 - OTP_WDATA4_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WDATA4_ATE_TEST_BIT_MASK (0x1U)
+#define SOC_OTP_CTRL_OTP_WDATA4_ATE_TEST_BIT_SHIFT (0U)
+/*! ATE_TEST_BIT - ATE test bit (READ ONLY) */
+#define SOC_OTP_CTRL_OTP_WDATA4_ATE_TEST_BIT(x)  (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA4_ATE_TEST_BIT_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA4_ATE_TEST_BIT_MASK)
+
+#define SOC_OTP_CTRL_OTP_WDATA4_DATA_LINE_VALID_BIT_MASK (0x2U)
+#define SOC_OTP_CTRL_OTP_WDATA4_DATA_LINE_VALID_BIT_SHIFT (1U)
+/*! DATA_LINE_VALID_BIT - Data line valid bit (READ ONLY) */
+#define SOC_OTP_CTRL_OTP_WDATA4_DATA_LINE_VALID_BIT(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA4_DATA_LINE_VALID_BIT_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA4_DATA_LINE_VALID_BIT_MASK)
+
+#define SOC_OTP_CTRL_OTP_WDATA4_SECURITY_BIT_MASK (0x4U)
+#define SOC_OTP_CTRL_OTP_WDATA4_SECURITY_BIT_SHIFT (2U)
+/*! SECURITY_BIT - Security Fuse bit (READ ONLY) */
+#define SOC_OTP_CTRL_OTP_WDATA4_SECURITY_BIT(x)  (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA4_SECURITY_BIT_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA4_SECURITY_BIT_MASK)
+
+#define SOC_OTP_CTRL_OTP_WDATA4_OTP_ALL_BITS_EQ_ZERO_MASK (0x8U)
+#define SOC_OTP_CTRL_OTP_WDATA4_OTP_ALL_BITS_EQ_ZERO_SHIFT (3U)
+/*! OTP_ALL_BITS_EQ_ZERO - All bits equal to zero (READ ONLY) */
+#define SOC_OTP_CTRL_OTP_WDATA4_OTP_ALL_BITS_EQ_ZERO(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WDATA4_OTP_ALL_BITS_EQ_ZERO_SHIFT)) & SOC_OTP_CTRL_OTP_WDATA4_OTP_ALL_BITS_EQ_ZERO_MASK)
+/*! @} */
+
+/*! @name OTP_ADDR - OTP_ADDR_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_ADDR_OTP_ADDR_MASK      (0x3FFU)
+#define SOC_OTP_CTRL_OTP_ADDR_OTP_ADDR_SHIFT     (0U)
+/*! OTP_ADDR - The otp_addr is composed of Bank select[16:13] and row address[12:7], the address
+ *    will select a row or a data line of a bank that contains 64 bits of s/w usable data plus the ATE
+ *    test bit and data line valid bit and the security bit.
+ */
+#define SOC_OTP_CTRL_OTP_ADDR_OTP_ADDR(x)        (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_ADDR_OTP_ADDR_SHIFT)) & SOC_OTP_CTRL_OTP_ADDR_OTP_ADDR_MASK)
+/*! @} */
+
+/*! @name OTP_CTRL0 - OTP_CTRL0_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN25_33B_MASK (0x2U)
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN25_33B_SHIFT (1U)
+/*! REGULATOR_EN25_33B - Stepdown regulator input voltage select */
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN25_33B(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN25_33B_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN25_33B_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_SV_MASK (0xCU)
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_SV_SHIFT (2U)
+/*! REGULATOR_SV - Stepdown regulator Rate Control, default = 2'b10 (2'b10==2.6V for 40nm) */
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_SV(x)   (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_SV_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_SV_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL0_REG_SETULATOR_EN_BYPASS_MASK (0x10U)
+#define SOC_OTP_CTRL_OTP_CTRL0_REG_SETULATOR_EN_BYPASS_SHIFT (4U)
+/*! REG_SETULATOR_EN_BYPASS - Enable/ disable value: */
+#define SOC_OTP_CTRL_OTP_CTRL0_REG_SETULATOR_EN_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_REG_SETULATOR_EN_BYPASS_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_REG_SETULATOR_EN_BYPASS_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN_MASK (0x20U)
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN_SHIFT (5U)
+/*! REGULATOR_EN - Stepdown regulator output enable, only valid if regulator_EN_bypass==1. */
+#define SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN(x)   (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_REGULATOR_EN_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL0_MACRO_RD_DONE_MASK (0x80U)
+#define SOC_OTP_CTRL_OTP_CTRL0_MACRO_RD_DONE_SHIFT (7U)
+/*! MACRO_RD_DONE - RD_DONE is from the OTP bank (selected by otp_addr_reg[9:6]). */
+#define SOC_OTP_CTRL_OTP_CTRL0_MACRO_RD_DONE(x)  (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_MACRO_RD_DONE_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_MACRO_RD_DONE_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL0_MACRO_TEST_MASK   (0xF00U)
+#define SOC_OTP_CTRL_OTP_CTRL0_MACRO_TEST_SHIFT  (8U)
+/*! MACRO_TEST - S/W control bits to TEST[3:0] inputs. */
+#define SOC_OTP_CTRL_OTP_CTRL0_MACRO_TEST(x)     (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_MACRO_TEST_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_MACRO_TEST_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL0_REG_CSTATE_RESET_MASK (0x4000U)
+#define SOC_OTP_CTRL_OTP_CTRL0_REG_CSTATE_RESET_SHIFT (14U)
+/*! REG_CSTATE_RESET - Reset OTP ctrl sm (for debugging purpose). */
+#define SOC_OTP_CTRL_OTP_CTRL0_REG_CSTATE_RESET(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_REG_CSTATE_RESET_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_REG_CSTATE_RESET_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL0_CTRL_CMD_DONE_MASK (0x8000U)
+#define SOC_OTP_CTRL_OTP_CTRL0_CTRL_CMD_DONE_SHIFT (15U)
+/*! CTRL_CMD_DONE - otp access command done. */
+#define SOC_OTP_CTRL_OTP_CTRL0_CTRL_CMD_DONE(x)  (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL0_CTRL_CMD_DONE_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL0_CTRL_CMD_DONE_MASK)
+/*! @} */
+
+/*! @name OTP_CTRL1 - OTP_CTRL1_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_OTPMEM_MASK (0x1U)
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_OTPMEM_SHIFT (0U)
+/*! OTP_PROG_SEQ_CODE_CLK_OTPMEM - Clock input, used to program the match code into all the OTP memories */
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_OTPMEM(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_OTPMEM_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_OTPMEM_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_OTPMEM_MASK (0x2U)
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_OTPMEM_SHIFT (1U)
+/*! OTP_PROG_SEQ_CODE_OTPMEM - Data input, used to program the match code into all the OTP memories. */
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_OTPMEM(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_OTPMEM_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_OTPMEM_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_VTR_MASK (0x4U)
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_VTR_SHIFT (2U)
+/*! OTP_PROG_SEQ_CODE_CLK_VTR - Clock input, used to program the match code into all the VTR (Step Down regulator) */
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_VTR(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_VTR_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_CLK_VTR_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_VTR_MASK (0x8U)
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_VTR_SHIFT (3U)
+/*! OTP_PROG_SEQ_CODE_VTR - Data input, used to program the match code into all the VTR (Step Down regulator) */
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_VTR(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_VTR_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_VTR_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_MUX_SEL_MASK (0x10U)
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_MUX_SEL_SHIFT (4U)
+/*! OTP_PROG_SEQ_CODE_MUX_SEL - SELECT OTP register for the match Code programming. */
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_MUX_SEL(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_MUX_SEL_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_OTP_PROG_SEQ_CODE_MUX_SEL_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_SCLK_MEM_PROG_MASK (0x20U)
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_SCLK_MEM_PROG_SHIFT (5U)
+/*! OTP_FORCE_SCLK_MEM_PROG - Only used for OTP memory programming: Set this bit to allow the match
+ *    code programming, clear this bit after the match code programming before start otp memory
+ *    programming.
+ */
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_SCLK_MEM_PROG(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_SCLK_MEM_PROG_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_SCLK_MEM_PROG_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_STEPDOWN_PROG_MASK (0x40U)
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_STEPDOWN_PROG_SHIFT (6U)
+/*! OTP_FORCE_STEPDOWN_PROG - For OTP memory programming: This bit need to be set before the match
+ *    code programming and clear this bit after the otp memory contents programming is done.
+ */
+#define SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_STEPDOWN_PROG(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_STEPDOWN_PROG_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_OTP_FORCE_STEPDOWN_PROG_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_STEPDOWN_MATCH_MASK (0x80U)
+#define SOC_OTP_CTRL_OTP_CTRL1_STEPDOWN_MATCH_SHIFT (7U)
+/*! STEPDOWN_MATCH - Match value: */
+#define SOC_OTP_CTRL_OTP_CTRL1_STEPDOWN_MATCH(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_STEPDOWN_MATCH_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_STEPDOWN_MATCH_MASK)
+
+#define SOC_OTP_CTRL_OTP_CTRL1_MACRO_MATCH_MASK  (0xFF00U)
+#define SOC_OTP_CTRL_OTP_CTRL1_MACRO_MATCH_SHIFT (8U)
+/*! MACRO_MATCH - 0: match code does not match. */
+#define SOC_OTP_CTRL_OTP_CTRL1_MACRO_MATCH(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CTRL1_MACRO_MATCH_SHIFT)) & SOC_OTP_CTRL_OTP_CTRL1_MACRO_MATCH_MASK)
+/*! @} */
+
+/*! @name OTP_CMD_START - OTP_CMD_START_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_START_MASK (0x1U)
+#define SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_START_SHIFT (0U)
+/*! OTP_CMD_START - Write 1 to start otp access command execution and it clears the ctrl_cmd_done bit. */
+#define SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_START(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_START_SHIFT)) & SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_START_MASK)
+
+#define SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_MASK  (0xF0U)
+#define SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_SHIFT (4U)
+/*! OTP_CMD - OTP access commands (the command execution finishes when the ctrl_cmd_done bit is set): */
+#define SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_SHIFT)) & SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_MASK)
+/*! @} */
+
+/*! @name OTP_PARAM0 - OTP_PARAM0_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_PARAM0_TPGM_2US_MASK    (0x3FFU)
+#define SOC_OTP_CTRL_OTP_PARAM0_TPGM_2US_SHIFT   (0U)
+/*! TPGM_2US - Specify the width of the programming pulse (in number of pclk cycle), the number
+ *    depends on the pclk frequency and the pulse width requirement (OTP macro specifies between 2us up
+ *    to 10us).
+ */
+#define SOC_OTP_CTRL_OTP_PARAM0_TPGM_2US(x)      (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_PARAM0_TPGM_2US_SHIFT)) & SOC_OTP_CTRL_OTP_PARAM0_TPGM_2US_MASK)
+
+#define SOC_OTP_CTRL_OTP_PARAM0_TSQ_MINUS_TRD_MASK (0x3C00U)
+#define SOC_OTP_CTRL_OTP_PARAM0_TSQ_MINUS_TRD_SHIFT (10U)
+/*! TSQ_MINUS_TRD - Read data access time, the value to enter is tSQ(70ns)-tRD. The default value is based on 32MHz LSB clock. */
+#define SOC_OTP_CTRL_OTP_PARAM0_TSQ_MINUS_TRD(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_PARAM0_TSQ_MINUS_TRD_SHIFT)) & SOC_OTP_CTRL_OTP_PARAM0_TSQ_MINUS_TRD_MASK)
+
+#define SOC_OTP_CTRL_OTP_PARAM0_TRD_20NS_LOW_MASK (0xC000U)
+#define SOC_OTP_CTRL_OTP_PARAM0_TRD_20NS_LOW_SHIFT (14U)
+/*! TRD_20NS_LOW - For 28nm. Read pulse width lower two bits(higher two bits are in
+ *    OTP_PARAM2_REG[12:11]). The default value is based on 32MHz LSB clock.
+ */
+#define SOC_OTP_CTRL_OTP_PARAM0_TRD_20NS_LOW(x)  (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_PARAM0_TRD_20NS_LOW_SHIFT)) & SOC_OTP_CTRL_OTP_PARAM0_TRD_20NS_LOW_MASK)
+/*! @} */
+
+/*! @name OTP_PARAM1 - OTP_PARAM1_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_PARAM1_TVHV_OFF_10US_MASK (0x7FFU)
+#define SOC_OTP_CTRL_OTP_PARAM1_TVHV_OFF_10US_SHIFT (0U)
+/*! TVHV_OFF_10US - Specify the VHV turn OFF time before the OTP read access. The default value is based on 32MHz */
+#define SOC_OTP_CTRL_OTP_PARAM1_TVHV_OFF_10US(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_PARAM1_TVHV_OFF_10US_SHIFT)) & SOC_OTP_CTRL_OTP_PARAM1_TVHV_OFF_10US_MASK)
+
+#define SOC_OTP_CTRL_OTP_PARAM1_TSU_300NS_MASK   (0xF800U)
+#define SOC_OTP_CTRL_OTP_PARAM1_TSU_300NS_SHIFT  (11U)
+/*! TSU_300NS - Specify setup time for few of the OTP control signals. The default value is based on 32MHz LSB clock. */
+#define SOC_OTP_CTRL_OTP_PARAM1_TSU_300NS(x)     (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_PARAM1_TSU_300NS_SHIFT)) & SOC_OTP_CTRL_OTP_PARAM1_TSU_300NS_MASK)
+/*! @} */
+
+/*! @name OTP_PARAM2 - OTP_PARAM2_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_PARAM2_TVHV_ON_10US_MASK (0x7FFU)
+#define SOC_OTP_CTRL_OTP_PARAM2_TVHV_ON_10US_SHIFT (0U)
+/*! TVHV_ON_10US - Specify the VHV turn ON time before the OTP programming access. The default value is based on 32MHz LSB clock. */
+#define SOC_OTP_CTRL_OTP_PARAM2_TVHV_ON_10US(x)  (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_PARAM2_TVHV_ON_10US_SHIFT)) & SOC_OTP_CTRL_OTP_PARAM2_TVHV_ON_10US_MASK)
+
+#define SOC_OTP_CTRL_OTP_PARAM2_TRD_20NS_HIGH_MASK (0x1800U)
+#define SOC_OTP_CTRL_OTP_PARAM2_TRD_20NS_HIGH_SHIFT (11U)
+/*! TRD_20NS_HIGH - For 28nm, Read pulse width higher two bits (lower two bits are in
+ *    OTP_PARAM0_REG[15:14]). The default value is based on 32MHz LSB clock.
+ */
+#define SOC_OTP_CTRL_OTP_PARAM2_TRD_20NS_HIGH(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_PARAM2_TRD_20NS_HIGH_SHIFT)) & SOC_OTP_CTRL_OTP_PARAM2_TRD_20NS_HIGH_MASK)
+/*! @} */
+
+/*! @name OTP_BYPASS_MODE0 - OTP_BYPASS_MODE0_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_SET_OTP_BYPASS_MASK (0x1U)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_SET_OTP_BYPASS_SHIFT (0U)
+/*! SET_OTP_BYPASS - SET OTP bypass mode, all the OTP interface control signals are under register control by s/w. */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_SET_OTP_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE0_SET_OTP_BYPASS_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE0_SET_OTP_BYPASS_MASK)
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_SCLK_MASK  (0x40U)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_SCLK_SHIFT (6U)
+/*! SCLK - Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1). */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_SCLK(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE0_SCLK_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE0_SCLK_MASK)
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_PGM_B_MASK (0x80U)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_PGM_B_SHIFT (7U)
+/*! PGM_B - Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1). */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_PGM_B(x)   (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE0_PGM_B_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE0_PGM_B_MASK)
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_LOAD_MASK  (0x100U)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_LOAD_SHIFT (8U)
+/*! LOAD - Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1). */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_LOAD(x)    (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE0_LOAD_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE0_LOAD_MASK)
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_DOUT_MASK (0x4000U)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_DOUT_SHIFT (14U)
+/*! MUX_DOUT - Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1). */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_DOUT(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_DOUT_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_DOUT_MASK)
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_RD_DONE_MASK (0x8000U)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_RD_DONE_SHIFT (15U)
+/*! MUX_RD_DONE - Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1). */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_RD_DONE(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_RD_DONE_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE0_MUX_RD_DONE_MASK)
+/*! @} */
+
+/*! @name OTP_BYPASS_MODE1 - OTP_BYPASS_MODE1_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE1_BIT_ADDRESS_MASK (0x7FU)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE1_BIT_ADDRESS_SHIFT (0U)
+/*! BIT_ADDRESS - Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1). */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE1_BIT_ADDRESS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE1_BIT_ADDRESS_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE1_BIT_ADDRESS_MASK)
+/*! @} */
+
+/*! @name OTP_TESTBUS_SEL - OTP_TESTBUS_SEL_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_TESTBUS_SEL_TESTBUS_MASK (0xFU)
+#define SOC_OTP_CTRL_OTP_TESTBUS_SEL_TESTBUS_SHIFT (0U)
+/*! TESTBUS - OTP Test Bus */
+#define SOC_OTP_CTRL_OTP_TESTBUS_SEL_TESTBUS(x)  (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_TESTBUS_SEL_TESTBUS_SHIFT)) & SOC_OTP_CTRL_OTP_TESTBUS_SEL_TESTBUS_MASK)
+/*! @} */
+
+/*! @name OTP_TESTBUS - OTP_TESTBUS_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_TESTBUS_TESTBUS_MASK    (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_TESTBUS_TESTBUS_SHIFT   (0U)
+/*! TESTBUS - OTP Test Bus */
+#define SOC_OTP_CTRL_OTP_TESTBUS_TESTBUS(x)      (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_TESTBUS_TESTBUS_SHIFT)) & SOC_OTP_CTRL_OTP_TESTBUS_TESTBUS_MASK)
+/*! @} */
+
+/*! @name OTP_BYPASS_MODE2 - OTP_BYPASS_MODE2_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE2_CSB_MASK   (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE2_CSB_SHIFT  (0U)
+/*! CSB - Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1). */
+#define SOC_OTP_CTRL_OTP_BYPASS_MODE2_CSB(x)     (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_BYPASS_MODE2_CSB_SHIFT)) & SOC_OTP_CTRL_OTP_BYPASS_MODE2_CSB_MASK)
+/*! @} */
+
+/*! @name OTP_RST_B - OTP_RST_B_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_RST_B_OTP_RST_B_MASK    (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_RST_B_OTP_RST_B_SHIFT   (0U)
+/*! OTP_RST_B - S/W reset bit to RST_B input of each OTP macro */
+#define SOC_OTP_CTRL_OTP_RST_B_OTP_RST_B(x)      (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_RST_B_OTP_RST_B_SHIFT)) & SOC_OTP_CTRL_OTP_RST_B_OTP_RST_B_MASK)
+/*! @} */
+
+/*! @name OTP_POR_B - OTP_POR_B_REG */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_POR_B_OTP_POR_B_MASK    (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_POR_B_OTP_POR_B_SHIFT   (0U)
+/*! OTP_POR_B - S/W por bit to POR_B input of each OTP macro. */
+#define SOC_OTP_CTRL_OTP_POR_B_OTP_POR_B(x)      (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_POR_B_OTP_POR_B_SHIFT)) & SOC_OTP_CTRL_OTP_POR_B_OTP_POR_B_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_LOCK_REG - OTP_WRITE_LOCK_REG (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_LOCK_REG_OTP_WRITE_LOCK_MASK (0x1U)
+#define SOC_OTP_CTRL_OTP_WRITE_LOCK_REG_OTP_WRITE_LOCK_SHIFT (0U)
+/*! OTP_WRITE_LOCK - "1 sticky bit, once it is set it will stay at set state until POR_ONLY reset to 0. */
+#define SOC_OTP_CTRL_OTP_WRITE_LOCK_REG_OTP_WRITE_LOCK(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_LOCK_REG_OTP_WRITE_LOCK_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_LOCK_REG_OTP_WRITE_LOCK_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_15_0 - OTP_WRITE_DIS_REG[15:0] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_15_0_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_15_0_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[15:0]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_15_0_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_15_0_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_15_0_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_31_16 - OTP_WRITE_DIS_REG[31:16] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_31_16_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_31_16_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[31:16]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_31_16_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_31_16_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_31_16_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_47_32 - OTP_WRITE_DIS_REG[47:32] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_47_32_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_47_32_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[47:32]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_47_32_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_47_32_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_47_32_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_63_48 - OTP_WRITE_DIS_REG[63:48] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_63_48_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_63_48_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[63:48]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_63_48_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_63_48_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_63_48_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_79_64 - OTP_WRITE_DIS_REG[79:64] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_79_64_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_79_64_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[79:64]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_79_64_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_79_64_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_79_64_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_95_80 - OTP_WRITE_DIS_REG[95:80] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_95_80_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_95_80_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[95:80]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_95_80_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_95_80_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_95_80_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_111_96 - OTP_WRITE_DIS_REG[111:96] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_111_96_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_111_96_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[111:96]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_111_96_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_111_96_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_111_96_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DIS_REG_127_112 - OTP_WRITE_DIS_REG[127:112] (Firecrest) */
+/*! @{ */
+
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_127_112_OTP_WRITE_DIS_MASK (0xFFFFU)
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_127_112_OTP_WRITE_DIS_SHIFT (0U)
+/*! OTP_WRITE_DIS - OTP_Write_Disable bitmap for OTP Line[127:112]. */
+#define SOC_OTP_CTRL_OTP_WRITE_DIS_REG_127_112_OTP_WRITE_DIS(x) (((uint16_t)(((uint16_t)(x)) << SOC_OTP_CTRL_OTP_WRITE_DIS_REG_127_112_OTP_WRITE_DIS_SHIFT)) & SOC_OTP_CTRL_OTP_WRITE_DIS_REG_127_112_OTP_WRITE_DIS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SOC_OTP_CTRL_Register_Masks */
+
+
+/* SOC_OTP_CTRL - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SOC_OTP_CTRL base address */
+  #define SOC_OTP_CTRL_BASE                        (0x55003400u)
+  /** Peripheral SOC_OTP_CTRL base address */
+  #define SOC_OTP_CTRL_BASE_NS                     (0x45003400u)
+  /** Peripheral SOC_OTP_CTRL base pointer */
+  #define SOC_OTP_CTRL                             ((SOC_OTP_CTRL_Type *)SOC_OTP_CTRL_BASE)
+  /** Peripheral SOC_OTP_CTRL base pointer */
+  #define SOC_OTP_CTRL_NS                          ((SOC_OTP_CTRL_Type *)SOC_OTP_CTRL_BASE_NS)
+  /** Array initializer of SOC_OTP_CTRL peripheral base addresses */
+  #define SOC_OTP_CTRL_BASE_ADDRS                  { SOC_OTP_CTRL_BASE }
+  /** Array initializer of SOC_OTP_CTRL peripheral base pointers */
+  #define SOC_OTP_CTRL_BASE_PTRS                   { SOC_OTP_CTRL }
+  /** Array initializer of SOC_OTP_CTRL peripheral base addresses */
+  #define SOC_OTP_CTRL_BASE_ADDRS_NS               { SOC_OTP_CTRL_BASE_NS }
+  /** Array initializer of SOC_OTP_CTRL peripheral base pointers */
+  #define SOC_OTP_CTRL_BASE_PTRS_NS                { SOC_OTP_CTRL_NS }
+#else
+  /** Peripheral SOC_OTP_CTRL base address */
+  #define SOC_OTP_CTRL_BASE                        (0x45003400u)
+  /** Peripheral SOC_OTP_CTRL base pointer */
+  #define SOC_OTP_CTRL                             ((SOC_OTP_CTRL_Type *)SOC_OTP_CTRL_BASE)
+  /** Array initializer of SOC_OTP_CTRL peripheral base addresses */
+  #define SOC_OTP_CTRL_BASE_ADDRS                  { SOC_OTP_CTRL_BASE }
+  /** Array initializer of SOC_OTP_CTRL peripheral base pointers */
+  #define SOC_OTP_CTRL_BASE_PTRS                   { SOC_OTP_CTRL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SOC_OTP_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1024];
+  __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x400 */
+  __IO uint32_t DLY;                               /**< Delay Register, offset: 0x404 */
+  __IO uint32_t STAT;                              /**< Status Register, offset: 0x408 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Register, offset: 0x40C */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear Register, offset: 0x410 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< Clock Divider Register, offset: 0x424 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status Register, offset: 0x428 */
+       uint8_t RESERVED_2[2516];
+  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration Register, offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO Status Register, offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Register, offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable Register, offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear Register, offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status Register, offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO Write Data Register, offset: 0xE20 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORD;                            /**< FIFO Read Data Register, offset: 0xE30 */
+       uint8_t RESERVED_6[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with no FIFO Pop Register, offset: 0xE40 */
+       uint8_t RESERVED_7[4];
+  __I  uint32_t FIFOSIZE;                          /**< FIFO Size Register, offset: 0xE48 */
+  struct {                                         /* offset: 0xE4C */
+    __IO uint32_t FIFORXTIMEOUTCFG;                  /**< FIFO Receive Timeout Configuration, offset: 0xE4C */
+    __I  uint32_t FIFORXTIMEOUTCNT;                  /**< FIFO Receive Timeout Counter, offset: 0xE50 */
+  } FIFO_SPI;
+       uint8_t RESERVED_8[424];
+  __I  uint32_t ID;                                /**< Peripheral Identification Register, offset: 0xFFC */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration Register */
+/*! @{ */
+
+#define SPI_CFG_ENABLE_MASK                      (0x1U)
+#define SPI_CFG_ENABLE_SHIFT                     (0U)
+/*! ENABLE - SPI Enable
+ *  0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
+ *  0b1..Enabled. The SPI is enabled for operation.
+ */
+#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+
+#define SPI_CFG_MASTER_MASK                      (0x4U)
+#define SPI_CFG_MASTER_SHIFT                     (2U)
+/*! MASTER - Master Mode Select
+ *  0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs; MISO is an output.
+ *  0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs; MISO is an input.
+ */
+#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+
+#define SPI_CFG_LSBF_MASK                        (0x8U)
+#define SPI_CFG_LSBF_SHIFT                       (3U)
+/*! LSBF - LSB First Mode Enable
+ *  0b0..Standard. Data is transmitted and received in standard MSB-first order.
+ *  0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
+ */
+#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+
+#define SPI_CFG_CPHA_MASK                        (0x10U)
+#define SPI_CFG_CPHA_SHIFT                       (4U)
+/*! CPHA - Clock Phase Select
+ *  0b0..Change
+ *  0b1..Capture
+ */
+#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+
+#define SPI_CFG_CPOL_MASK                        (0x20U)
+#define SPI_CFG_CPOL_SHIFT                       (5U)
+/*! CPOL - Clock Polarity Select
+ *  0b0..Low. The rest state of the clock (between transfers) is low.
+ *  0b1..High. The rest state of the clock (between transfers) is high.
+ */
+#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+
+#define SPI_CFG_LOOP_MASK                        (0x80U)
+#define SPI_CFG_LOOP_SHIFT                       (7U)
+/*! LOOP - Loopback Mode Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+
+#define SPI_CFG_SPOL0_MASK                       (0x100U)
+#define SPI_CFG_SPOL0_SHIFT                      (8U)
+/*! SPOL0 - SSEL0 Polarity Select
+ *  0b0..Low. The SSEL0 pin is active low.
+ *  0b1..High. The SSEL0 pin is active high.
+ */
+#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+
+#define SPI_CFG_SPOL1_MASK                       (0x200U)
+#define SPI_CFG_SPOL1_SHIFT                      (9U)
+/*! SPOL1 - SSEL1 Polarity Select
+ *  0b0..Low. The SSEL1 pin is active low.
+ *  0b1..High. The SSEL1 pin is active high.
+ */
+#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+
+#define SPI_CFG_SPOL2_MASK                       (0x400U)
+#define SPI_CFG_SPOL2_SHIFT                      (10U)
+/*! SPOL2 - SSEL2 Polarity Select
+ *  0b0..Low. The SSEL2 pin is active low.
+ *  0b1..High. The SSEL2 pin is active high.
+ */
+#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+
+#define SPI_CFG_SPOL3_MASK                       (0x800U)
+#define SPI_CFG_SPOL3_SHIFT                      (11U)
+/*! SPOL3 - SSEL3 Polarity Select
+ *  0b0..Low. The SSEL3 pin is active low.
+ *  0b1..High. The SSEL3 pin is active high.
+ */
+#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+/*! @} */
+
+/*! @name DLY - Delay Register */
+/*! @{ */
+
+#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
+/*! PRE_DELAY - Pre-Delay
+ *  0b0000..No additional time is inserted
+ *  0b0001..1 SPI clock time is inserted
+ *  0b0010..2 SPI clock times are inserted
+ *  0b1111..15 SPI clock times are inserted
+ */
+#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+
+#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
+/*! POST_DELAY - Post-Delay
+ *  0b0000..No additional time is inserted
+ *  0b0001..1 SPI clock time is inserted
+ *  0b0010..2 SPI clock times are inserted
+ *  0b1111..15 SPI clock times are inserted
+ */
+#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+
+#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
+/*! FRAME_DELAY - Frame Delay
+ *  0b0000..No additional time is inserted
+ *  0b0001..1 SPI clock time is inserted
+ *  0b0010..2 SPI clock times are inserted
+ *  0b1111..15 SPI clock times are inserted
+ */
+#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+
+#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
+/*! TRANSFER_DELAY - Transfer Delay
+ *  0b0000..The minimum time that SSEL is deasserted is 1 SPI clock time (zero-added time)
+ *  0b0001..The minimum time that SSEL is deasserted is 2 SPI clock times
+ *  0b0010..The minimum time that SSEL is deasserted is 3 SPI clock times
+ *  0b1111..The minimum time that SSEL is deasserted is 16 SPI clock times
+ */
+#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+/*! @} */
+
+/*! @name STAT - Status Register */
+/*! @{ */
+
+#define SPI_STAT_SSA_MASK                        (0x10U)
+#define SPI_STAT_SSA_SHIFT                       (4U)
+/*! SSA - Slave Select Assert */
+#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+
+#define SPI_STAT_SSD_MASK                        (0x20U)
+#define SPI_STAT_SSD_SHIFT                       (5U)
+/*! SSD - Slave Select Deassert */
+#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+
+#define SPI_STAT_STALLED_MASK                    (0x40U)
+#define SPI_STAT_STALLED_SHIFT                   (6U)
+/*! STALLED - Stalled Status Flag */
+#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+
+#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
+/*! ENDTRANSFER - End Transfer Control */
+#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+
+#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
+/*! MSTIDLE - Master Idle Status Flag */
+#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Register */
+/*! @{ */
+
+#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
+/*! SSAEN - Slave Select Assert Interrupt Enable
+ *  0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ *  0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ */
+#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+
+#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
+/*! SSDEN - Slave Select Deassert Interrupt Enable
+ *  0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ *  0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ */
+#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+
+#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
+/*! MSTIDLEEN - Master Idle Interrupt Enable
+ *  0b0..No interrupt will be generated when the SPI master function is idle.
+ *  0b1..An interrupt will be generated when the SPI master function is fully idle.
+ */
+#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear Register */
+/*! @{ */
+
+#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
+/*! SSAEN - Slave Select Assert Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the Slave Select Assert Interrupt Enable bit (INTENSET[SSAEN])
+ */
+#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+
+#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
+/*! SSDEN - Slave Select Deassert Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the Slave Select Deassert Interrupt Enable bit (INTENSET[SSDEN])
+ */
+#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+
+#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
+/*! MSTIDLE - Master Idle Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the Master Idle Interrupt Enable bit (INTENSET[MSTIDLE])
+ */
+#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name DIV - Clock Divider Register */
+/*! @{ */
+
+#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT                     (0U)
+/*! DIVVAL - Rate Divider Value */
+#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status Register */
+/*! @{ */
+
+#define SPI_INTSTAT_SSA_MASK                     (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT                    (4U)
+/*! SSA - Slave Select Assert Interrupt
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+
+#define SPI_INTSTAT_SSD_MASK                     (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT                    (5U)
+/*! SSD - Slave Select Deassert Interrupt
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+
+#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
+/*! MSTIDLE - Master Idle Status Flag Interrupt
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO Configuration Register */
+/*! @{ */
+
+#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
+/*! ENABLETX - Enable the Transmit FIFO
+ *  0b0..The transmit FIFO is not enabled
+ *  0b1..The transmit FIFO is enabled
+ */
+#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+
+#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
+/*! ENABLERX - Enable the Receive FIFO
+ *  0b0..The receive FIFO is not enabled
+ *  0b1..The receive FIFO is enabled
+ */
+#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+
+#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
+/*! SIZE - FIFO Size Configuration
+ *  0b00..FIFO is configured as 16 entries of 8 bits.
+ *  0b01..FIFO is configured as 8 entries of 16 bits.
+ *  0b10..Not used
+ *  0b11..Not used
+ */
+#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+
+#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
+/*! DMATX - DMA Configuration for Transmit
+ *  0b0..DMA is not used for the transmit function
+ *  0b1..Issues DMA request for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+
+#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
+/*! DMARX - DMA Configuration for Receive
+ *  0b0..DMA is not used for the receive function.
+ *  0b1..Issues a DMA request for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+
+#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
+/*! WAKETX - Wake-up for Transmit FIFO Level
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes
+ *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+
+#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
+/*! WAKERX - Wake-up for Receive FIFO Level
+ *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
+ *       FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+
+#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
+/*! EMPTYTX - Empty Command for the Transmit FIFO
+ *  0b0..No effect
+ *  0b1..The TX FIFO is emptied
+ */
+#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+
+#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
+/*! EMPTYRX - Empty Command for the Receive FIFO
+ *  0b0..No effect
+ *  0b1..The RX FIFO is emptied
+ */
+#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+
+#define SPI_FIFOCFG_POPDBG_MASK                  (0x40000U)
+#define SPI_FIFOCFG_POPDBG_SHIFT                 (18U)
+/*! POPDBG - Pop FIFO for Debug Reads
+ *  0b0..Debug reads of the FIFO do not pop the FIFO
+ *  0b1..A debug read will cause the FIFO to pop
+ */
+#define SPI_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO Status Register */
+/*! @{ */
+
+#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
+/*! TXERR - TX FIFO Error
+ *  0b0..A transmit FIFO error has not occurred.
+ *  0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
+ *       FIFO, or by an underflow if the FIFO is empty when data is needed.
+ */
+#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+
+#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
+/*! RXERR - RX FIFO Error
+ *  0b0..A receive FIFO overflow has not occurred
+ *  0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
+ */
+#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+
+#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
+/*! PERINT - Peripheral Interrupt
+ *  0b0..The peripheral function has not asserted an interrupt
+ *  0b1..Indicates that the peripheral function has asserted an interrupt. More information can be found by
+ *       reading the peripheral's status register (STAT).
+ */
+#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+
+#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+/*! TXEMPTY - Transmit FIFO Empty
+ *  0b0..The transmit FIFO is not empty
+ *  0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
+ */
+#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+
+#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+/*! TXNOTFULL - Transmit FIFO is Not Full
+ *  0b0..The transmit FIFO is full and another write would cause it to overflow
+ *  0b1..The transmit FIFO is not full, so more data can be written
+ */
+#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+/*! RXNOTEMPTY - Receive FIFO is Not Empty
+ *  0b0..When 0, the receive FIFO is empty
+ *  0b1..When 1, the receive FIFO is not empty, so data can be read
+ */
+#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+
+#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
+/*! RXFULL - Receive FIFO is Full
+ *  0b0..The receive FIFO is not full
+ *  0b1..The receive FIFO is full. To prevent the peripheral from causing an overflow, data should be read out.
+ */
+#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+
+#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO Current Level */
+#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+
+#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO Current Level */
+#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+
+#define SPI_FIFOSTAT_RXTIMEOUT_MASK              (0x1000000U)
+#define SPI_FIFOSTAT_RXTIMEOUT_SHIFT             (24U)
+/*! RXTIMEOUT - Receive FIFO Timeout
+ *  0b0..RX FIFO on
+ *  0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register.
+ */
+#define SPI_FIFOSTAT_RXTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOSTAT_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO Trigger Register */
+/*! @{ */
+
+#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+/*! TXLVLENA - Transmit FIFO Level Trigger Enable
+ *  0b0..Transmit FIFO level does not generate a FIFO level trigger
+ *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the FIFOTRIG[TXLVL] field.
+ */
+#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+
+#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+/*! RXLVLENA - Receive FIFO Level Trigger Enable
+ *  0b0..Receive FIFO level does not generate a FIFO level trigger
+ *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the FIFOTRIG[RXLVL] field.
+ */
+#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+
+#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
+/*! TXLVL - Transmit FIFO Level Trigger Point
+ *  0b0000..Trigger when the TX FIFO becomes empty
+ *  0b0001..Trigger when the TX FIFO level decreases to 1 entry
+ *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
+ */
+#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+
+#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
+/*! RXLVL - Receive FIFO Level Trigger Point
+ *  0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
+ *  0b0001..Trigger when the RX FIFO has received 2 entries
+ *  0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
+ */
+#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO Interrupt Enable Register */
+/*! @{ */
+
+#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
+/*! TXERR - TX Error Interrupt Enable
+ *  0b0..No interrupt will be generated for a transmit error
+ *  0b1..An interrupt will be generated when a transmit error occurs
+ */
+#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+
+#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ *  0b0..No interrupt will be generated for a receive error
+ *  0b1..An interrupt will be generated when a receive error occurs
+ */
+#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+
+#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ *  0b0..No interrupt will be generated based on the TX FIFO level
+ *  0b1..If FIFOTRIG[TXLVLENA]=1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
+ */
+#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+
+#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ *  0b0..No interrupt will be generated based on the RX FIFO level
+ *  0b1..If FIFOTRIG[RXLVLENA]=1, then an interrupt will be generated when the RX FIFO level increases to the level specified by FIFOTRIG[RXLVL]
+ */
+#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+
+#define SPI_FIFOINTENSET_RXTIMEOUT_MASK          (0x1000000U)
+#define SPI_FIFOINTENSET_RXTIMEOUT_SHIFT         (24U)
+/*! RXTIMEOUT - Receive Timeout
+ *  0b0..No RX interrupt will be generated.
+ *  0b1..Asserts RX interrupt if RX FIFO Timeout event occurs.
+ */
+#define SPI_FIFOINTENSET_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENSET_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear Register */
+/*! @{ */
+
+#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
+/*! TXERR - TX Error Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the TX Error Interrupt Enable bit FIFOINTENSET[TXERR]
+ */
+#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+
+#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the Receive Error Interrupt Enable bit FIFOINTENSET[RXERR]
+ */
+#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+
+#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the Transmit FIFO Level Interrupt Enable bit FIFOINTENSET[TXLVL]
+ */
+#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+
+#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the Receive FIFO Level Interrupt Enable bit FIFOINTENSET[RXLVL]
+ */
+#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+
+#define SPI_FIFOINTENCLR_RXTIMEOUT_MASK          (0x1000000U)
+#define SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT         (24U)
+/*! RXTIMEOUT - Receive Timeout
+ *  0b0..No effect
+ *  0b1..Clear the interrupt
+ */
+#define SPI_FIFOINTENCLR_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENCLR_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO Interrupt Status Register */
+/*! @{ */
+
+#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
+/*! TXERR - TX FIFO Error Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+
+#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
+/*! RXERR - RX FIFO Error Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+
+#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+
+#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+
+#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
+/*! PERINT - Peripheral Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+
+#define SPI_FIFOINTSTAT_RXTIMEOUT_MASK           (0x1000000U)
+#define SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT          (24U)
+/*! RXTIMEOUT - Receive Timeout Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_RXTIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOINTSTAT_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO Write Data Register */
+/*! @{ */
+
+#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
+/*! TXDATA - Transmit Data to the FIFO */
+#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+
+#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
+/*! TXSSEL0_N - Transmit Slave Select 0
+ *  0b0..SSEL0 is asserted
+ *  0b1..SSEL0 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+
+#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
+/*! TXSSEL1_N - Transmit Slave Select 1
+ *  0b0..SSEL1 is asserted
+ *  0b1..SSEL1 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+
+#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
+/*! TXSSEL2_N - Transmit Slave Select 2
+ *  0b0..SSEL2 is asserted
+ *  0b1..SSEL2 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+
+#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
+/*! TXSSEL3_N - Transmit Slave Select 3
+ *  0b0..SSEL3 is asserted
+ *  0b1..SSEL3 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+
+#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT                     (20U)
+/*! EOT - End of Transfer
+ *  0b0..SSEL is not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
+ *  0b1..SSEL is deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
+ */
+#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+
+#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT                     (21U)
+/*! EOF - End of Frame
+ *  0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
+ *  0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
+ *       inserted before subsequent data is transmitted.
+ */
+#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+
+#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
+/*! RXIGNORE - Receive Ignore
+ *  0b0..Read received data. Received data must be read, to allow transmission to proceed. SPI transmit will halt
+ *       when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not
+ *       read before new data is received.
+ *  0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
+ *       data. No receiver flags are generated.
+ */
+#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+
+#define SPI_FIFOWR_TXIGNORE_MASK                 (0x800000U)
+#define SPI_FIFOWR_TXIGNORE_SHIFT                (23U)
+/*! TXIGNORE - Transmit Ignore
+ *  0b0..Write transmit data
+ *  0b1..Ignore transmit data
+ */
+#define SPI_FIFOWR_TXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK)
+
+#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT                     (24U)
+/*! LEN - Data Length
+ *  0b0000..Reserved
+ *  0b0001..Reserved
+ *  0b0010..Reserved
+ *  0b0011..Data transfer is 4 bits in length
+ *  0b0100..Data transfer is 5 bits in length
+ *  0b1111..Data transfer is 16 bits in length
+ */
+#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO Read Data Register */
+/*! @{ */
+
+#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+
+#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
+/*! RXSSEL0_N - Slave Select 0 for Receive
+ *  0b0..Slave Select 0 is active
+ *  0b1..Slave Select 0 is not active
+ */
+#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+
+#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
+/*! RXSSEL1_N - Slave Select 1 for Receive
+ *  0b0..Slave Select 1 is active
+ *  0b1..Slave Select 1 is not active
+ */
+#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+
+#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
+/*! RXSSEL2_N - Slave Select 2 for Receive
+ *  0b0..Slave Select 2 is active
+ *  0b1..Slave Select 2 is not active
+ */
+#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+
+#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
+/*! RXSSEL3_N - Slave Select 3 for Receive
+ *  0b0..Slave Select 3 is active
+ *  0b1..Slave Select 3 is not active
+ */
+#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+
+#define SPI_FIFORD_SOT_MASK                      (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT                     (20U)
+/*! SOT - Start of Transfer Flag
+ *  0b0..This is not the 1st data after the SSELs went from deasserted to asserted
+ *  0b1..This is the 1st data after the SSELs went from deasserted to asserted (i.e., any previous transfer has
+ *       ended). This information can be used to identify the 1st piece of data in cases where the transfer length is
+ *       greater than 16 bits.
+ */
+#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO Data Read with no FIFO Pop Register */
+/*! @{ */
+
+#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
+/*! RXSSEL0_N - Slave Select 0 for Receive
+ *  0b0..Not selected
+ *  0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
+/*! RXSSEL1_N - Slave Select 1 for Receive
+ *  0b0..Not selected
+ *  0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
+/*! RXSSEL2_N - Slave Select 2 for Receive
+ *  0b0..Not selected
+ *  0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
+/*! RXSSEL3_N - Slave Select 3 for Receive
+ *  0b0..Not selected
+ *  0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+
+#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
+/*! SOT - Start of Transfer Flag
+ *  0b0..Not active
+ *  0b1..Active
+ */
+#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+/*! @} */
+
+/*! @name FIFOSIZE - FIFO Size Register */
+/*! @{ */
+
+#define SPI_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
+#define SPI_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
+/*! FIFOSIZE - FIFO Size */
+#define SPI_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK)
+/*! @} */
+
+/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */
+/*! @{ */
+
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU)
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U)
+/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler */
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK)
+
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U)
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U)
+/*! RXTIMEOUT_VALUE - Receive Timeout Value */
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK)
+
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK   (0x1000000U)
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT  (24U)
+/*! RXTIMEOUT_EN - Receive Timeout Enable
+ *  0b0..Disable RX FIFO timeout
+ *  0b1..Enable RX FIFO timeout
+ */
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x)     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK)
+
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK  (0x2000000U)
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U)
+/*! RXTIMEOUT_COW - Receive Timeout Continue On Write
+ *  0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO.
+ *  0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO.
+ */
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x)    (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK)
+
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK  (0x4000000U)
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U)
+/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty
+ *  0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty.
+ *  0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty.
+ */
+#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x)    (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK)
+/*! @} */
+
+/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */
+/*! @{ */
+
+#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK  (0xFFFFU)
+#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U)
+/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value */
+#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x)    (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral Identification Register */
+/*! @{ */
+
+#define SPI_ID_APERTURE_MASK                     (0xFFU)
+#define SPI_ID_APERTURE_SHIFT                    (0U)
+/*! APERTURE - Aperture */
+#define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+
+#define SPI_ID_MINOR_REV_MASK                    (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT                   (8U)
+/*! MINOR_REV - Minor revision of module implementation */
+#define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+
+#define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT                   (12U)
+/*! MAJOR_REV - Major revision of module implementation */
+#define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+
+#define SPI_ID_ID_MASK                           (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT                          (16U)
+/*! ID - Module identifier for the selected function */
+#define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SPI0 base address */
+  #define SPI0_BASE                                (0x50106000u)
+  /** Peripheral SPI0 base address */
+  #define SPI0_BASE_NS                             (0x40106000u)
+  /** Peripheral SPI0 base pointer */
+  #define SPI0                                     ((SPI_Type *)SPI0_BASE)
+  /** Peripheral SPI0 base pointer */
+  #define SPI0_NS                                  ((SPI_Type *)SPI0_BASE_NS)
+  /** Peripheral SPI1 base address */
+  #define SPI1_BASE                                (0x50107000u)
+  /** Peripheral SPI1 base address */
+  #define SPI1_BASE_NS                             (0x40107000u)
+  /** Peripheral SPI1 base pointer */
+  #define SPI1                                     ((SPI_Type *)SPI1_BASE)
+  /** Peripheral SPI1 base pointer */
+  #define SPI1_NS                                  ((SPI_Type *)SPI1_BASE_NS)
+  /** Peripheral SPI2 base address */
+  #define SPI2_BASE                                (0x50108000u)
+  /** Peripheral SPI2 base address */
+  #define SPI2_BASE_NS                             (0x40108000u)
+  /** Peripheral SPI2 base pointer */
+  #define SPI2                                     ((SPI_Type *)SPI2_BASE)
+  /** Peripheral SPI2 base pointer */
+  #define SPI2_NS                                  ((SPI_Type *)SPI2_BASE_NS)
+  /** Peripheral SPI3 base address */
+  #define SPI3_BASE                                (0x50109000u)
+  /** Peripheral SPI3 base address */
+  #define SPI3_BASE_NS                             (0x40109000u)
+  /** Peripheral SPI3 base pointer */
+  #define SPI3                                     ((SPI_Type *)SPI3_BASE)
+  /** Peripheral SPI3 base pointer */
+  #define SPI3_NS                                  ((SPI_Type *)SPI3_BASE_NS)
+  /** Peripheral SPI14 base address */
+  #define SPI14_BASE                               (0x50126000u)
+  /** Peripheral SPI14 base address */
+  #define SPI14_BASE_NS                            (0x40126000u)
+  /** Peripheral SPI14 base pointer */
+  #define SPI14                                    ((SPI_Type *)SPI14_BASE)
+  /** Peripheral SPI14 base pointer */
+  #define SPI14_NS                                 ((SPI_Type *)SPI14_BASE_NS)
+  /** Array initializer of SPI peripheral base addresses */
+  #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI14_BASE }
+  /** Array initializer of SPI peripheral base pointers */
+  #define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI14 }
+  /** Array initializer of SPI peripheral base addresses */
+  #define SPI_BASE_ADDRS_NS                        { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI14_BASE_NS }
+  /** Array initializer of SPI peripheral base pointers */
+  #define SPI_BASE_PTRS_NS                         { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI14_NS }
+#else
+  /** Peripheral SPI0 base address */
+  #define SPI0_BASE                                (0x40106000u)
+  /** Peripheral SPI0 base pointer */
+  #define SPI0                                     ((SPI_Type *)SPI0_BASE)
+  /** Peripheral SPI1 base address */
+  #define SPI1_BASE                                (0x40107000u)
+  /** Peripheral SPI1 base pointer */
+  #define SPI1                                     ((SPI_Type *)SPI1_BASE)
+  /** Peripheral SPI2 base address */
+  #define SPI2_BASE                                (0x40108000u)
+  /** Peripheral SPI2 base pointer */
+  #define SPI2                                     ((SPI_Type *)SPI2_BASE)
+  /** Peripheral SPI3 base address */
+  #define SPI3_BASE                                (0x40109000u)
+  /** Peripheral SPI3 base pointer */
+  #define SPI3                                     ((SPI_Type *)SPI3_BASE)
+  /** Peripheral SPI14 base address */
+  #define SPI14_BASE                               (0x40126000u)
+  /** Peripheral SPI14 base pointer */
+  #define SPI14                                    ((SPI_Type *)SPI14_BASE)
+  /** Array initializer of SPI peripheral base addresses */
+  #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI14_BASE }
+  /** Array initializer of SPI peripheral base pointers */
+  #define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI14 }
+#endif
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM14_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSCTL0 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL0_Peripheral_Access_Layer SYSCTL0 Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCTL0 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t AHBMATRIXPRIOR;                    /**< AHB matrix priority, offset: 0x10 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t M33NMISRCSEL;                      /**< M33 nmi source selection, offset: 0x30 */
+  __IO uint32_t SYSTEM_STICK_CALIB;                /**< system stick calibration, offset: 0x34 */
+  __IO uint32_t SYSTEM_NSTICK_CALIB;               /**< system nstick calibration, offset: 0x38 */
+       uint8_t RESERVED_2[68];
+  __IO uint32_t AUTOCLKGATEOVERRIDE0;              /**< auto clock gating override 0, offset: 0x80 */
+  __IO uint32_t AUTOCLKGATEOVERRIDE1;              /**< auto clock gating override 1, offset: 0x84 */
+       uint8_t RESERVED_3[904];
+  __I  uint32_t USBCLKSTAT;                        /**< USB clock status, offset: 0x410 */
+       uint8_t RESERVED_4[876];
+  __IO uint32_t HWWAKE;                            /**< offset: 0x780 */
+       uint8_t RESERVED_5[1692];
+  __IO uint32_t ROM_HIDING_ADDR_OFFSET;            /**< rom_hiding_addr_offset, offset: 0xE20 */
+  __IO uint32_t ROM_HIDING_ADDR_OFFSET_DP;         /**< rom_hiding_addr_offset_dp, offset: 0xE24 */
+  __IO uint32_t ROM_HIDING_LOCK;                   /**< rom_hiding_lock, offset: 0xE28 */
+} SYSCTL0_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCTL0 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL0_Register_Masks SYSCTL0 Register Masks
+ * @{
+ */
+
+/*! @name AHBMATRIXPRIOR - AHB matrix priority */
+/*! @{ */
+
+#define SYSCTL0_AHBMATRIXPRIOR_M0_MASK           (0x3U)
+#define SYSCTL0_AHBMATRIXPRIOR_M0_SHIFT          (0U)
+/*! M0 - Master 0 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. (0 Low) */
+#define SYSCTL0_AHBMATRIXPRIOR_M0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M0_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M0_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M1_MASK           (0xCU)
+#define SYSCTL0_AHBMATRIXPRIOR_M1_SHIFT          (2U)
+/*! M1 - Master 1 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M1_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M1_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M2_MASK           (0x30U)
+#define SYSCTL0_AHBMATRIXPRIOR_M2_SHIFT          (4U)
+/*! M2 - Master 2 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M2_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M2_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M3_MASK           (0xC0U)
+#define SYSCTL0_AHBMATRIXPRIOR_M3_SHIFT          (6U)
+/*! M3 - Master 3 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M3(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M3_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M3_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M4_MASK           (0x300U)
+#define SYSCTL0_AHBMATRIXPRIOR_M4_SHIFT          (8U)
+/*! M4 - Master 4 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M4(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M4_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M4_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M5_MASK           (0xC00U)
+#define SYSCTL0_AHBMATRIXPRIOR_M5_SHIFT          (10U)
+/*! M5 - Master 5 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M5(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M5_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M5_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M6_MASK           (0x3000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M6_SHIFT          (12U)
+/*! M6 - Master 6 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M6(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M6_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M6_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M7_MASK           (0xC000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M7_SHIFT          (14U)
+/*! M7 - Master 7 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M7(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M7_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M7_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M8_MASK           (0x30000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M8_SHIFT          (16U)
+/*! M8 - Master 8 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M8(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M8_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M8_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M9_MASK           (0xC0000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M9_SHIFT          (18U)
+/*! M9 - Master 9 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M9(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M9_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M9_MASK)
+
+#define SYSCTL0_AHBMATRIXPRIOR_M10_MASK          (0x300000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M10_SHIFT         (20U)
+/*! M10 - Master 10 Priority. . . 0: 0, 1: 1, 2: 2, 3: 3. */
+#define SYSCTL0_AHBMATRIXPRIOR_M10(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M10_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M10_MASK)
+/*! @} */
+
+/*! @name M33NMISRCSEL - M33 nmi source selection */
+/*! @{ */
+
+#define SYSCTL0_M33NMISRCSEL_NMISRCSEL_MASK      (0x7FU)
+#define SYSCTL0_M33NMISRCSEL_NMISRCSEL_SHIFT     (0U)
+/*! NMISRCSEL - Selects one of the M33 interrupt sources as the NMI source. See M33 Interrupt Slot Table for Interrupt Slot Numers. */
+#define SYSCTL0_M33NMISRCSEL_NMISRCSEL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_M33NMISRCSEL_NMISRCSEL_SHIFT)) & SYSCTL0_M33NMISRCSEL_NMISRCSEL_MASK)
+
+#define SYSCTL0_M33NMISRCSEL_NMIEN_MASK          (0x80000000U)
+#define SYSCTL0_M33NMISRCSEL_NMIEN_SHIFT         (31U)
+/*! NMIEN - NMI interrupt enable
+ *  0b0..Disable NMI Interrupt
+ *  0b1..Enable NMI Interrupt.
+ */
+#define SYSCTL0_M33NMISRCSEL_NMIEN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_M33NMISRCSEL_NMIEN_SHIFT)) & SYSCTL0_M33NMISRCSEL_NMIEN_MASK)
+/*! @} */
+
+/*! @name SYSTEM_STICK_CALIB - system stick calibration */
+/*! @{ */
+
+#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_MASK (0x3FFFFFFU)
+#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_SHIFT (0U)
+/*! SYSTEM_STICK_CALIB - Selects the system secure tick calibration value of the M33. */
+#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_SHIFT)) & SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_MASK)
+/*! @} */
+
+/*! @name SYSTEM_NSTICK_CALIB - system nstick calibration */
+/*! @{ */
+
+#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_MASK (0x3FFFFFFU)
+#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_SHIFT (0U)
+/*! SYSTEM_NSTICK_CALIB - Selects the system non-secure tick calibration value of the M33. */
+#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_SHIFT)) & SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_MASK)
+/*! @} */
+
+/*! @name AUTOCLKGATEOVERRIDE0 - auto clock gating override 0 */
+/*! @{ */
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_MASK (0x1U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_SHIFT (0U)
+/*! AHB2APB0 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_MASK (0x2U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_SHIFT (1U)
+/*! AHB2APB1 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINER_MASK (0x4U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINER_SHIFT (2U)
+/*! CRC_ENGINER - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINER_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINER_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_MASK  (0x10U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_SHIFT (4U)
+/*! DMAC0 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_MASK  (0x20U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_SHIFT (5U)
+/*! DMAC1 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_SYSCTL_REGBANK_MASK (0x8000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_SYSCTL_REGBANK_SHIFT (15U)
+/*! SYSCTL_REGBANK - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_SYSCTL_REGBANK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_SYSCTL_REGBANK_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_SYSCTL_REGBANK_MASK)
+/*! @} */
+
+/*! @name AUTOCLKGATEOVERRIDE1 - auto clock gating override 1 */
+/*! @{ */
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF0_MASK (0x1U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF0_SHIFT (0U)
+/*! SRAM_IF0 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF0_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF1_MASK (0x2U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF1_SHIFT (1U)
+/*! SRAM_IF1 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF1_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF2_MASK (0x4U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF2_SHIFT (2U)
+/*! SRAM_IF2 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF2_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF2_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF3_MASK (0x8U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF3_SHIFT (3U)
+/*! SRAM_IF3 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF3_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF3_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF4_MASK (0x10U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF4_SHIFT (4U)
+/*! SRAM_IF4 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF4_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF4_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF5_MASK (0x20U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF5_SHIFT (5U)
+/*! SRAM_IF5 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF5(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF5_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF5_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF6_MASK (0x40U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF6_SHIFT (6U)
+/*! SRAM_IF6 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF6_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF6_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF7_MASK (0x80U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF7_SHIFT (7U)
+/*! SRAM_IF7 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF7_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF7_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF8_MASK (0x100U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF8_SHIFT (8U)
+/*! SRAM_IF8 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF8_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF8_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF9_MASK (0x200U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF9_SHIFT (9U)
+/*! SRAM_IF9 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF9(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF9_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF9_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF10_MASK (0x400U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF10_SHIFT (10U)
+/*! SRAM_IF10 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF10(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF10_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF10_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF11_MASK (0x800U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF11_SHIFT (11U)
+/*! SRAM_IF11 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF11(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF11_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF11_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF12_MASK (0x1000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF12_SHIFT (12U)
+/*! SRAM_IF12 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF12(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF12_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF12_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF13_MASK (0x2000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF13_SHIFT (13U)
+/*! SRAM_IF13 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF13(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF13_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF13_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF14_MASK (0x4000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF14_SHIFT (14U)
+/*! SRAM_IF14 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF14(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF14_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF14_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF15_MASK (0x8000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF15_SHIFT (15U)
+/*! SRAM_IF15 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF15(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF15_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF15_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF16_MASK (0x10000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF16_SHIFT (16U)
+/*! SRAM_IF16 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF16(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF16_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF16_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF17_MASK (0x20000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF17_SHIFT (17U)
+/*! SRAM_IF17 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF17(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF17_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF17_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF18_MASK (0x40000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF18_SHIFT (18U)
+/*! SRAM_IF18 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF18(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF18_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM_IF18_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM0_MASK (0x40000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM0_SHIFT (30U)
+/*! AON_MEM0 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM0_MASK)
+
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM1_MASK (0x80000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM1_SHIFT (31U)
+/*! AON_MEM1 - auto clock gating enable
+ *  0b0..Enable Auto-Clk Gate
+ *  0b1..Disable Auto-Clk Gate (clocks always running)
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_AON_MEM1_MASK)
+/*! @} */
+
+/*! @name USBCLKSTAT - USB clock status */
+/*! @{ */
+
+#define SYSCTL0_USBCLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
+#define SYSCTL0_USBCLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
+/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:
+ *  0b0..low
+ *  0b1..high
+ */
+#define SYSCTL0_USBCLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBCLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCTL0_USBCLKSTAT_DEV_NEED_CLKST_MASK)
+
+#define SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
+#define SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+/*! HOST_NEED_CLKST - USB0 Device Host USB0_NEEDCLK signal status:
+ *  0b0..low
+ *  0b1..high
+ */
+#define SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK)
+/*! @} */
+
+/*! @name HWWAKE -  */
+/*! @{ */
+
+#define SYSCTL0_HWWAKE_FORCEWAKE_MASK            (0x1U)
+#define SYSCTL0_HWWAKE_FORCEWAKE_SHIFT           (0U)
+/*! FORCEWAKE - Force peripheral clocking to stay on during deep-sleep mode. When 1, clocking to
+ *    peripherals is prevented from being shut down when the CPU enters deep-sleep mode. This is
+ *    intended to allow a coprocessor to continue operating while the main CPU(s) are shut down.
+ */
+#define SYSCTL0_HWWAKE_FORCEWAKE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_FORCEWAKE_SHIFT)) & SYSCTL0_HWWAKE_FORCEWAKE_MASK)
+
+#define SYSCTL0_HWWAKE_FCWAKE_MASK               (0x2U)
+#define SYSCTL0_HWWAKE_FCWAKE_SHIFT              (1U)
+/*! FCWAKE - Wake for Flexcomm Interfaces. When 1, any Flexcomm Interface FIFO reaching the level
+ *    specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the
+ *    related status is asserted.
+ */
+#define SYSCTL0_HWWAKE_FCWAKE(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_FCWAKE_SHIFT)) & SYSCTL0_HWWAKE_FCWAKE_MASK)
+
+#define SYSCTL0_HWWAKE_DMICWAKE_MASK             (0x4U)
+#define SYSCTL0_HWWAKE_DMICWAKE_SHIFT            (2U)
+/*! DMICWAKE - Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the
+ *    level specified by TRIGLVL of either channel will cause peripheral clocking to wake up
+ *    temporarily while the related status is asserted.
+ */
+#define SYSCTL0_HWWAKE_DMICWAKE(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMICWAKE_SHIFT)) & SYSCTL0_HWWAKE_DMICWAKE_MASK)
+
+#define SYSCTL0_HWWAKE_DMAC0WAKE_MASK            (0x8U)
+#define SYSCTL0_HWWAKE_DMAC0WAKE_SHIFT           (3U)
+/*! DMAC0WAKE - Wake for DMAC0. When 1, DMAC0 being busy will cause peripheral clocking to remain
+ *    running until DMAC0 completes. This is generally used in conjunction with bit 1 and/or 2 in
+ *    order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is
+ *    cleared, but before DMAC0 has completed its related activity.
+ */
+#define SYSCTL0_HWWAKE_DMAC0WAKE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMAC0WAKE_SHIFT)) & SYSCTL0_HWWAKE_DMAC0WAKE_MASK)
+
+#define SYSCTL0_HWWAKE_DMAC1WAKE_MASK            (0x10U)
+#define SYSCTL0_HWWAKE_DMAC1WAKE_SHIFT           (4U)
+/*! DMAC1WAKE - Wake for DMAC1. When 1, DMAC1 being busy will cause peripheral clocking to remain
+ *    running until DMAC1 completes. This is generally used in conjunction with bit 1 and/or 2 in
+ *    order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is
+ *    cleared, but before DMAC1 has completed its related activity.
+ */
+#define SYSCTL0_HWWAKE_DMAC1WAKE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMAC1WAKE_SHIFT)) & SYSCTL0_HWWAKE_DMAC1WAKE_MASK)
+/*! @} */
+
+/*! @name ROM_HIDING_ADDR_OFFSET - rom_hiding_addr_offset */
+/*! @{ */
+
+#define SYSCTL0_ROM_HIDING_ADDR_OFFSET_ROM_HIDING_ADDR_OFFSET_MASK (0xFFFFU)
+#define SYSCTL0_ROM_HIDING_ADDR_OFFSET_ROM_HIDING_ADDR_OFFSET_SHIFT (0U)
+/*! ROM_HIDING_ADDR_OFFSET - rom_hiding_addr_offset */
+#define SYSCTL0_ROM_HIDING_ADDR_OFFSET_ROM_HIDING_ADDR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_HIDING_ADDR_OFFSET_ROM_HIDING_ADDR_OFFSET_SHIFT)) & SYSCTL0_ROM_HIDING_ADDR_OFFSET_ROM_HIDING_ADDR_OFFSET_MASK)
+/*! @} */
+
+/*! @name ROM_HIDING_ADDR_OFFSET_DP - rom_hiding_addr_offset_dp */
+/*! @{ */
+
+#define SYSCTL0_ROM_HIDING_ADDR_OFFSET_DP_ROM_HIDING_ADDR_OFFSET_DP_MASK (0xFFFFU)
+#define SYSCTL0_ROM_HIDING_ADDR_OFFSET_DP_ROM_HIDING_ADDR_OFFSET_DP_SHIFT (0U)
+/*! ROM_HIDING_ADDR_OFFSET_DP - rom_hiding_addr_offset_dp */
+#define SYSCTL0_ROM_HIDING_ADDR_OFFSET_DP_ROM_HIDING_ADDR_OFFSET_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_HIDING_ADDR_OFFSET_DP_ROM_HIDING_ADDR_OFFSET_DP_SHIFT)) & SYSCTL0_ROM_HIDING_ADDR_OFFSET_DP_ROM_HIDING_ADDR_OFFSET_DP_MASK)
+/*! @} */
+
+/*! @name ROM_HIDING_LOCK - rom_hiding_lock */
+/*! @{ */
+
+#define SYSCTL0_ROM_HIDING_LOCK_ROM_HIDING_LOCK_MASK (0xFFFFFFFFU)
+#define SYSCTL0_ROM_HIDING_LOCK_ROM_HIDING_LOCK_SHIFT (0U)
+/*! ROM_HIDING_LOCK - rom_hiding_addr_offset */
+#define SYSCTL0_ROM_HIDING_LOCK_ROM_HIDING_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_HIDING_LOCK_ROM_HIDING_LOCK_SHIFT)) & SYSCTL0_ROM_HIDING_LOCK_ROM_HIDING_LOCK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCTL0_Register_Masks */
+
+
+/* SYSCTL0 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SYSCTL0 base address */
+  #define SYSCTL0_BASE                             (0x50002000u)
+  /** Peripheral SYSCTL0 base address */
+  #define SYSCTL0_BASE_NS                          (0x40002000u)
+  /** Peripheral SYSCTL0 base pointer */
+  #define SYSCTL0                                  ((SYSCTL0_Type *)SYSCTL0_BASE)
+  /** Peripheral SYSCTL0 base pointer */
+  #define SYSCTL0_NS                               ((SYSCTL0_Type *)SYSCTL0_BASE_NS)
+  /** Array initializer of SYSCTL0 peripheral base addresses */
+  #define SYSCTL0_BASE_ADDRS                       { SYSCTL0_BASE }
+  /** Array initializer of SYSCTL0 peripheral base pointers */
+  #define SYSCTL0_BASE_PTRS                        { SYSCTL0 }
+  /** Array initializer of SYSCTL0 peripheral base addresses */
+  #define SYSCTL0_BASE_ADDRS_NS                    { SYSCTL0_BASE_NS }
+  /** Array initializer of SYSCTL0 peripheral base pointers */
+  #define SYSCTL0_BASE_PTRS_NS                     { SYSCTL0_NS }
+#else
+  /** Peripheral SYSCTL0 base address */
+  #define SYSCTL0_BASE                             (0x40002000u)
+  /** Peripheral SYSCTL0 base pointer */
+  #define SYSCTL0                                  ((SYSCTL0_Type *)SYSCTL0_BASE)
+  /** Array initializer of SYSCTL0 peripheral base addresses */
+  #define SYSCTL0_BASE_ADDRS                       { SYSCTL0_BASE }
+  /** Array initializer of SYSCTL0 peripheral base pointers */
+  #define SYSCTL0_BASE_PTRS                        { SYSCTL0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSCTL0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSCTL1 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL1_Peripheral_Access_Layer SYSCTL1 Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCTL1 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t MCLKPINDIR;                        /**< mclk direction control, offset: 0x10 */
+       uint8_t RESERVED_1[44];
+  __IO uint32_t FCCTRLSEL[4];                      /**< flexcomm control selection N, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[48];
+  __IO uint32_t SHAREDCTRLSET[2];                  /**< shared control set N, array offset: 0x80, array step: 0x4 */
+       uint8_t RESERVED_3[376];
+  __IO uint32_t RXEVPULSEGEN;                      /**< RX Event Pulse Generator, offset: 0x200 */
+} SYSCTL1_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCTL1 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL1_Register_Masks SYSCTL1 Register Masks
+ * @{
+ */
+
+/*! @name MCLKPINDIR - mclk direction control */
+/*! @{ */
+
+#define SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK       (0x1U)
+#define SYSCTL1_MCLKPINDIR_MCLKPINDIR_SHIFT      (0U)
+/*! MCLKPINDIR - mclk direction control
+ *  0b0..MCLK is in input direction.
+ *  0b1..MCLK is in the output direction.
+ */
+#define SYSCTL1_MCLKPINDIR_MCLKPINDIR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL1_MCLKPINDIR_MCLKPINDIR_SHIFT)) & SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK)
+/*! @} */
+
+/*! @name FCCTRLSEL - flexcomm control selection N */
+/*! @{ */
+
+#define SYSCTL1_FCCTRLSEL_SCKINSEL_MASK          (0x3U)
+#define SYSCTL1_FCCTRLSEL_SCKINSEL_SHIFT         (0U)
+/*! SCKINSEL - SCK IN Select. . .
+ *  0b00..Original FLEXCOMM I2S signals
+ *  0b01..Shared Set0 I2S signals.
+ *  0b10..Shared Set1 I2S signals.
+ *  0b11..Reserved.
+ */
+#define SYSCTL1_FCCTRLSEL_SCKINSEL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_SCKINSEL_MASK)
+
+#define SYSCTL1_FCCTRLSEL_WSINSEL_MASK           (0x300U)
+#define SYSCTL1_FCCTRLSEL_WSINSEL_SHIFT          (8U)
+/*! WSINSEL - WS IN Select. . .
+ *  0b00..Original FLEXCOMM I2S signals
+ *  0b01..Shared Set0 I2S signals.
+ *  0b10..Shared Set1 I2S signals.
+ *  0b11..Reserved.
+ */
+#define SYSCTL1_FCCTRLSEL_WSINSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_WSINSEL_MASK)
+
+#define SYSCTL1_FCCTRLSEL_DATAINSEL_MASK         (0x30000U)
+#define SYSCTL1_FCCTRLSEL_DATAINSEL_SHIFT        (16U)
+/*! DATAINSEL - DATA IN Select. . .
+ *  0b00..Original FLEXCOMM I2S signals
+ *  0b01..Shared Set0 I2S signals.
+ *  0b10..Shared Set1 I2S signals.
+ *  0b11..Reserved.
+ */
+#define SYSCTL1_FCCTRLSEL_DATAINSEL(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_DATAINSEL_MASK)
+
+#define SYSCTL1_FCCTRLSEL_DATAOUTSEL_MASK        (0x3000000U)
+#define SYSCTL1_FCCTRLSEL_DATAOUTSEL_SHIFT       (24U)
+/*! DATAOUTSEL - DATA OUT Select. . .
+ *  0b00..Original FLEXCOMM I2S signals
+ *  0b01..Shared Set0 I2S signals.
+ *  0b10..Shared Set1 I2S signals.
+ *  0b11..Reserved.
+ */
+#define SYSCTL1_FCCTRLSEL_DATAOUTSEL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_DATAOUTSEL_MASK)
+/*! @} */
+
+/* The count of SYSCTL1_FCCTRLSEL */
+#define SYSCTL1_FCCTRLSEL_COUNT                  (4U)
+
+/*! @name SHAREDCTRLSET - shared control set N */
+/*! @{ */
+
+#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_MASK  (0x7U)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U)
+/*! SHAREDSCKSEL - Shared SCK Select. . .
+ *  0b000..FLEXCOMM0
+ *  0b001..FLEXCOMM1
+ *  0b010..FLEXCOMM2
+ *  0b011..FLEXCOMM3
+ */
+#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_MASK)
+
+#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_MASK   (0x70U)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_SHIFT  (4U)
+/*! SHAREDWSSEL - Shared WS Select. . .
+ *  0b000..FLEXCOMM0
+ *  0b001..FLEXCOMM1
+ *  0b010..FLEXCOMM2
+ *  0b011..FLEXCOMM3
+ */
+#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_MASK)
+
+#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U)
+/*! SHAREDDATASEL - Shared DATA Select. . .
+ *  0b000..FLEXCOMM0
+ *  0b001..FLEXCOMM1
+ *  0b010..FLEXCOMM2
+ *  0b011..FLEXCOMM3
+ */
+#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_MASK)
+
+#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_MASK  (0x10000U)
+#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U)
+/*! FC0DATAOUTEN - FLEXCOMM0 DATAOUT OUTPUT ENABLE
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_MASK)
+
+#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_MASK  (0x20000U)
+#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U)
+/*! FC1DATAOUTEN - FLEXCOMM1 DATAOUT OUTPUT ENABLE
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_MASK)
+
+#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_MASK  (0x40000U)
+#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U)
+/*! FC2DATAOUTEN - FLEXCOMM2 DATAOUT OUTPUT ENABLE
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_MASK)
+
+#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_MASK  (0x80000U)
+#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U)
+/*! FC3DATAOUTEN - FLEXCOMM3 DATAOUT OUTPUT ENABLE
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_MASK)
+/*! @} */
+
+/* The count of SYSCTL1_SHAREDCTRLSET */
+#define SYSCTL1_SHAREDCTRLSET_COUNT              (2U)
+
+/*! @name RXEVPULSEGEN - RX Event Pulse Generator */
+/*! @{ */
+
+#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_MASK   (0x1U)
+#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT  (0U)
+/*! RXEVPULSEGEN - RX Event Pulse Generator. Writing a '1' to this register will create a one PSCLK
+ *    pulse width of logic '1'. It is automatically cleared.
+ *  0b0..No effect.
+ *  0b1..Pulse RXEV High for one PSCLK cycle.
+ */
+#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT)) & SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCTL1_Register_Masks */
+
+
+/* SYSCTL1 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SYSCTL1 base address */
+  #define SYSCTL1_BASE                             (0x50022000u)
+  /** Peripheral SYSCTL1 base address */
+  #define SYSCTL1_BASE_NS                          (0x40022000u)
+  /** Peripheral SYSCTL1 base pointer */
+  #define SYSCTL1                                  ((SYSCTL1_Type *)SYSCTL1_BASE)
+  /** Peripheral SYSCTL1 base pointer */
+  #define SYSCTL1_NS                               ((SYSCTL1_Type *)SYSCTL1_BASE_NS)
+  /** Array initializer of SYSCTL1 peripheral base addresses */
+  #define SYSCTL1_BASE_ADDRS                       { SYSCTL1_BASE }
+  /** Array initializer of SYSCTL1 peripheral base pointers */
+  #define SYSCTL1_BASE_PTRS                        { SYSCTL1 }
+  /** Array initializer of SYSCTL1 peripheral base addresses */
+  #define SYSCTL1_BASE_ADDRS_NS                    { SYSCTL1_BASE_NS }
+  /** Array initializer of SYSCTL1 peripheral base pointers */
+  #define SYSCTL1_BASE_PTRS_NS                     { SYSCTL1_NS }
+#else
+  /** Peripheral SYSCTL1 base address */
+  #define SYSCTL1_BASE                             (0x40022000u)
+  /** Peripheral SYSCTL1 base pointer */
+  #define SYSCTL1                                  ((SYSCTL1_Type *)SYSCTL1_BASE)
+  /** Array initializer of SYSCTL1 peripheral base addresses */
+  #define SYSCTL1_BASE_ADDRS                       { SYSCTL1_BASE }
+  /** Array initializer of SYSCTL1 peripheral base pointers */
+  #define SYSCTL1_BASE_PTRS                        { SYSCTL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSCTL1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSCTL2 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL2_Peripheral_Access_Layer SYSCTL2 Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCTL2 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t RAM_CTRL0;                         /**< RAM Memory Control Register 0, offset: 0x0 */
+  __IO uint32_t USB_CTRL;                          /**< USB Control Register, offset: 0x4 */
+  __IO uint32_t ANA_GRP_CTRL;                      /**< ANA GRP control register, offset: 0x8 */
+  __IO uint32_t AVPLL_CTRL0;                       /**< Audio PLL Control register0, offset: 0xC */
+  __IO uint32_t AVPLL_CTRL1;                       /**< Audio PLL Control register1, offset: 0x10 */
+  __IO uint32_t AVPLL_CTRL2;                       /**< Audio PLL Control register2, offset: 0x14 */
+  __IO uint32_t AVPLL_CTRL3;                       /**< Audio PLL Control register3, offset: 0x18 */
+  __IO uint32_t AVPLL_CTRL4;                       /**< Audio PLL Control register4, offset: 0x1C */
+  __IO uint32_t AVPLL_CTRL5;                       /**< Audio PLL Control register5, offset: 0x20 */
+  __IO uint32_t AVPLL_CTRL6;                       /**< Audio PLL Control register6, offset: 0x24 */
+  __I  uint32_t AVPLL_CTRL7;                       /**< Audio PLL Control register7, offset: 0x28 */
+  __IO uint32_t AVPLL_CTRL8;                       /**< Audio PLL Control register8, offset: 0x2C */
+  __IO uint32_t AVPLL_CTRL9;                       /**< Audio PLL Control register9, offset: 0x30 */
+  __IO uint32_t AVPLL_CTRL10;                      /**< Audio PLL Control register10, offset: 0x34 */
+  __IO uint32_t AVPLL_CTRL11;                      /**< Audio PLL Control register11, offset: 0x38 */
+  __IO uint32_t AVPLL_CTRL12;                      /**< Audio PLL Control register12, offset: 0x3C */
+  __IO uint32_t GAU_CTRL;                          /**< GAU Control register, offset: 0x40 */
+  __IO uint32_t CTIMER_CTRL;                       /**< CTIMER Control register, offset: 0x44 */
+  __IO uint32_t EXT_H2H_CTRL;                      /**< AHB async bridge Control register, offset: 0x48 */
+  __IO uint32_t RAM_CTRL1;                         /**< RAM Memory Control Register 1, offset: 0x4C */
+  __IO uint32_t ROM_CTRL;                          /**< ROM Control Register, offset: 0x50 */
+  __IO uint32_t MEM_PD_CTRL;                       /**< MEM PD Control enable register when PM2 mode, offset: 0x54 */
+  __IO uint32_t MEM_PD_CFG;                        /**< MEM PD Configure register when PM2 mode, offset: 0x58 */
+  __IO uint32_t ENET_IN_SEL_TIMER;                 /**< Select input source for enet pad0, offset: 0x5C */
+  __IO uint32_t ENET_IPG_STOP;                     /**< Configure ipg_stop, used by enet wakeup sequence, offset: 0x60 */
+  __I  uint32_t ENET_IPG_STOP_ACK;                 /**< Store ipg_stop_ack, used by enet wakeup sequence, offset: 0x64 */
+  __IO uint32_t ROM_BRU_ADDR_MASK_DIS;             /**< Disable dynamic address masking feature, offset: 0x68 */
+  __IO uint32_t ROM_BRU_DYN_CLK_DIS;               /**< Disable dynamic clock gating feature, offset: 0x6C */
+       uint8_t RESERVED_0[12];
+  __I  uint32_t OTP_EARLY_FUSE_VALID;              /**< Early fuse valid from OTP, offset: 0x7C */
+  __I  uint32_t OTP_MEDIUM_FUSE_VALID;             /**< Medium fuse valid from OTP, offset: 0x80 */
+  __I  uint32_t OTP_ALL_FUSE_VALID;                /**< All fuse valid from OTP, offset: 0x84 */
+  __IO uint32_t PLL_CTRL;                          /**< PLL control register, offset: 0x88 */
+  __IO uint32_t ANA_PDWN_PM2;                      /**< ana_pdwn control signal when PM2 mode, offset: 0x8C */
+  __IO uint32_t SOURCE_CLK_GATE;                   /**< source clock gate control, offset: 0x90 */
+  __IO uint32_t TRNG_PWR_MODE;                     /**< TRNG_PWR_MODE, offset: 0x94 */
+  __IO uint32_t TRNG_PIN_CTRL;                     /**< TRNG_PIN_CTRL, offset: 0x98 */
+  __IO uint32_t CAU_CTRL;                          /**< CAU control register, offset: 0x9C */
+  __IO uint32_t SOC_CIU_RDY_MASK;                  /**< SOC_CIU_RDY_MASK, offset: 0xA0 */
+  __IO uint32_t LE_AUDIO_TIMER_ENABLE;             /**< Enable bit for le audio timer, offset: 0xA4 */
+  __IO uint32_t LE_AUDIO_TIMER_CNT_CLR;            /**< Clear bit of internal counter, offset: 0xA8 */
+  __I  uint32_t LE_AUDIO_TIMER_CNT0;               /**< Counter value captured by trigger0, offset: 0xAC */
+  __I  uint32_t LE_AUDIO_TIMER_CNT1;               /**< Counter value captured by trigger1, offset: 0xB0 */
+  __I  uint32_t LE_AUDIO_TIMER_CNT2;               /**< Counter value captured by trigger2, offset: 0xB4 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t AVPLL_CTRL13;                      /**< Audio PLL Control register13, offset: 0xC0 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_STATUS;       /**< CPU Code Bus Access Sram Checker Violation Status, offset: 0xC4 */
+  __IO uint32_t MEM_ACC_CHK_CODE_VIO_CLR;          /**< CPU Code Bus Access Sram Checker Violation Status Clear, offset: 0xC8 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_STATUS;        /**< CPU SYS Bus Access Sram Checker Violation Status, offset: 0xCC */
+  __IO uint32_t MEM_ACC_CHK_SYS_VIO_CLR;           /**< CPU SYS Bus Access Sram Checker Violation Status Clear, offset: 0xD0 */
+       uint8_t RESERVED_2[4];
+  __I  uint32_t SOC_MCI_EXTRA;                     /**< Reserved register, offset: 0xD8 */
+  __IO uint32_t MCI_SOC_EXTRA;                     /**< Reserved register, offset: 0xDC */
+  __IO uint32_t ROM_DYN_CLK_EN;                    /**< To control dynamic clock gating of the rom clock, offset: 0xE0 */
+  __IO uint32_t RESERVED_REG1;                     /**< Reserved register, offset: 0xE4 */
+  __IO uint32_t RESERVED_REG2;                     /**< Reserved register, offset: 0xE8 */
+  __IO uint32_t RESERVED_REG3;                     /**< Reserved register, offset: 0xEC */
+  __IO uint32_t RESERVED_REG4;                     /**< Reserved register, offset: 0xF0 */
+  __IO uint32_t RESERVED_REG5;                     /**< Reserved register, offset: 0xF4 */
+  __IO uint32_t RESERVED_REG6;                     /**< Reserved register, offset: 0xF8 */
+  __IO uint32_t RESERVED_REG7;                     /**< Reserved register, offset: 0xFC */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR0;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x100 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC0;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x104 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR1;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x108 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC1;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x10C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR2;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x110 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC2;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x114 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR3;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x118 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC3;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x11C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR4;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x120 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC4;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x124 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR5;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x128 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC5;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x12C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR6;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x130 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC6;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x134 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR7;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x138 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC7;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x13C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR8;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x140 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC8;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x144 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR9;        /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x148 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC9;        /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x14C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR10;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x150 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC10;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x154 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR11;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x158 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC11;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x15C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR12;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x160 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC12;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x164 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR13;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x168 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC13;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x16C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR14;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x170 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC14;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x174 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR15;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x178 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC15;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x17C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR16;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x180 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC16;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x184 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR17;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x188 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC17;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x18C */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_ADDR18;       /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x190 */
+  __I  uint32_t MEM_ACC_CHK_CODE_VIO_MISC18;       /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x194 */
+       uint8_t RESERVED_3[104];
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR0;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x200 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC0;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x204 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR1;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x208 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC1;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x20C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR2;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x210 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC2;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x214 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR3;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x218 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC3;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x21C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR4;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x220 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC4;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x224 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR5;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x228 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC5;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x22C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR6;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x230 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC6;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x234 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR7;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x238 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC7;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x23C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR8;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x240 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC8;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x244 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR9;         /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x248 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC9;         /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x24C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR10;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x250 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC10;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x254 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR11;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x258 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC11;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x25C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR12;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x260 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC12;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x264 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR13;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x268 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC13;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x26C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR14;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x270 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC14;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x274 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR15;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x278 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC15;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x27C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR16;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x280 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC16;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x284 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR17;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x288 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC17;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x28C */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_ADDR18;        /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x290 */
+  __I  uint32_t MEM_ACC_CHK_SYS_VIO_MISC18;        /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x294 */
+} SYSCTL2_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCTL2 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL2_Register_Masks SYSCTL2 Register Masks
+ * @{
+ */
+
+/*! @name RAM_CTRL0 - RAM Memory Control Register 0 */
+/*! @{ */
+
+#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_MASK      (0x3U)
+#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_SHIFT     (0U)
+/*! AON_MEM_RTC1 - aon_mem_rtc1 */
+#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_MASK)
+
+#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_MASK      (0xCU)
+#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_SHIFT     (2U)
+/*! AON_MEM_WTC1 - aon_mem_wtc1 */
+#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_MASK)
+
+#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_MASK      (0x30U)
+#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_SHIFT     (4U)
+/*! AON_MEM_RTC0 - aon_mem_rtc0 */
+#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_MASK)
+
+#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_MASK      (0xC0U)
+#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_SHIFT     (6U)
+/*! AON_MEM_WTC0 - aon_mem_wtc0 */
+#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_MASK)
+
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_MASK   (0x300U)
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_SHIFT  (8U)
+/*! FLEXSPI_MEM_RTC - flexspi_mem_rtc */
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_MASK   (0xC00U)
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_SHIFT  (10U)
+/*! FLEXSPI_MEM_WTC - flexspi_mem_wtc */
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_MASK (0x3000U)
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_SHIFT (12U)
+/*! FLEXSPI_CACHE_RTC - flexspi_cache_rtc */
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_MASK (0xC000U)
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_SHIFT (14U)
+/*! FLEXSPI_CACHE_WTC - flexspi_cache_wtc */
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_MASK (0x30000U)
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_SHIFT (16U)
+/*! FLEXSPI_CACHE_TAG_RTC - flexspi_cache_tag_rtc */
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_MASK (0xC0000U)
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_SHIFT (18U)
+/*! FLEXSPI_CACHE_TAG_WTC - flexspi_cache_tag_wtc */
+#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_MASK)
+/*! @} */
+
+/*! @name USB_CTRL - USB Control Register */
+/*! @{ */
+
+#define SYSCTL2_USB_CTRL_USB_PU_PLL_MASK         (0x1U)
+#define SYSCTL2_USB_CTRL_USB_PU_PLL_SHIFT        (0U)
+/*! USB_PU_PLL - USB PU PLL */
+#define SYSCTL2_USB_CTRL_USB_PU_PLL(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_PU_PLL_SHIFT)) & SYSCTL2_USB_CTRL_USB_PU_PLL_MASK)
+
+#define SYSCTL2_USB_CTRL_USB_PU_OTG_MASK         (0x2U)
+#define SYSCTL2_USB_CTRL_USB_PU_OTG_SHIFT        (1U)
+/*! USB_PU_OTG - USB PU OTG */
+#define SYSCTL2_USB_CTRL_USB_PU_OTG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_PU_OTG_SHIFT)) & SYSCTL2_USB_CTRL_USB_PU_OTG_MASK)
+
+#define SYSCTL2_USB_CTRL_USB_PU_MASK             (0x4U)
+#define SYSCTL2_USB_CTRL_USB_PU_SHIFT            (2U)
+/*! USB_PU - USB PU */
+#define SYSCTL2_USB_CTRL_USB_PU(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_PU_SHIFT)) & SYSCTL2_USB_CTRL_USB_PU_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_MASK     (0x8U)
+#define SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_SHIFT    (3U)
+/*! REG_RX_PDFVSSM - reg_rx_pdfvssm */
+#define SYSCTL2_USB_CTRL_REG_RX_PDFVSSM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_RX_PDLVMC_MASK      (0x10U)
+#define SYSCTL2_USB_CTRL_REG_RX_PDLVMC_SHIFT     (4U)
+/*! REG_RX_PDLVMC - reg_rx_pdlvmc */
+#define SYSCTL2_USB_CTRL_REG_RX_PDLVMC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_PDLVMC_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_PDLVMC_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_MASK     (0x20U)
+#define SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_SHIFT    (5U)
+/*! REG_TX_PDFVSSM - reg_tx_pdfvssm */
+#define SYSCTL2_USB_CTRL_REG_TX_PDFVSSM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_TX_PDLVMC_MASK      (0x40U)
+#define SYSCTL2_USB_CTRL_REG_TX_PDLVMC_SHIFT     (6U)
+/*! REG_TX_PDLVMC - reg_tx_pdlvmc */
+#define SYSCTL2_USB_CTRL_REG_TX_PDLVMC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_PDLVMC_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_PDLVMC_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_MASK     (0x180U)
+#define SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_SHIFT    (7U)
+/*! REG_RX_BUF_RTC - reg_rx_buf_rtc */
+#define SYSCTL2_USB_CTRL_REG_RX_BUF_RTC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_MASK     (0x600U)
+#define SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_SHIFT    (9U)
+/*! REG_RX_BUF_WTC - reg_rx_buf_wtc */
+#define SYSCTL2_USB_CTRL_REG_RX_BUF_WTC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_MASK     (0x1800U)
+#define SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_SHIFT    (11U)
+/*! REG_TX_BUF_RTC - reg_tx_buf_rtc */
+#define SYSCTL2_USB_CTRL_REG_TX_BUF_RTC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_MASK)
+
+#define SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_MASK     (0x6000U)
+#define SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_SHIFT    (13U)
+/*! REG_TX_BUF_WTC - reg_tx_buf_wtc */
+#define SYSCTL2_USB_CTRL_REG_TX_BUF_WTC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_MASK)
+
+#define SYSCTL2_USB_CTRL_USB_RESUME_MASK         (0x8000U)
+#define SYSCTL2_USB_CTRL_USB_RESUME_SHIFT        (15U)
+/*! USB_RESUME - USB Resume */
+#define SYSCTL2_USB_CTRL_USB_RESUME(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_RESUME_SHIFT)) & SYSCTL2_USB_CTRL_USB_RESUME_MASK)
+
+#define SYSCTL2_USB_CTRL_IDDQ_TEST_MASK          (0x10000U)
+#define SYSCTL2_USB_CTRL_IDDQ_TEST_SHIFT         (16U)
+/*! IDDQ_TEST - iddq Test */
+#define SYSCTL2_USB_CTRL_IDDQ_TEST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_IDDQ_TEST_SHIFT)) & SYSCTL2_USB_CTRL_IDDQ_TEST_MASK)
+
+#define SYSCTL2_USB_CTRL_SOFT_PHY_RESET_MASK     (0x20000U)
+#define SYSCTL2_USB_CTRL_SOFT_PHY_RESET_SHIFT    (17U)
+/*! SOFT_PHY_RESET - Soft PHY Reset */
+#define SYSCTL2_USB_CTRL_SOFT_PHY_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_PHY_RESET_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_PHY_RESET_MASK)
+
+#define SYSCTL2_USB_CTRL_PHY_RESET_SEL_MASK      (0x40000U)
+#define SYSCTL2_USB_CTRL_PHY_RESET_SEL_SHIFT     (18U)
+/*! PHY_RESET_SEL - PHY Reset Select */
+#define SYSCTL2_USB_CTRL_PHY_RESET_SEL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_PHY_RESET_SEL_SHIFT)) & SYSCTL2_USB_CTRL_PHY_RESET_SEL_MASK)
+
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_MASK  (0x80000U)
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_SHIFT (19U)
+/*! SOFT_UTMI_SESSEND - Soft UTMI sessend */
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_MASK)
+
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_MASK   (0x100000U)
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_SHIFT  (20U)
+/*! SOFT_UTMI_XVALID - Soft UTMI xvalid */
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_MASK)
+
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_MASK    (0x200000U)
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_SHIFT   (21U)
+/*! SOFT_UTMI_IDDIG - Soft UTMI iddig */
+#define SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_MASK)
+
+#define SYSCTL2_USB_CTRL_MAC_CTRL_SEL_MASK       (0x400000U)
+#define SYSCTL2_USB_CTRL_MAC_CTRL_SEL_SHIFT      (22U)
+/*! MAC_CTRL_SEL - MAC Control Select */
+#define SYSCTL2_USB_CTRL_MAC_CTRL_SEL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_MAC_CTRL_SEL_SHIFT)) & SYSCTL2_USB_CTRL_MAC_CTRL_SEL_MASK)
+
+#define SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_MASK (0x800000U)
+#define SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_SHIFT (23U)
+/*! USB_TX_BITSTUFF_EN - USM TX BITSTUFF EN */
+#define SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_SHIFT)) & SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_MASK)
+/*! @} */
+
+/*! @name ANA_GRP_CTRL - ANA GRP control register */
+/*! @{ */
+
+#define SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_MASK        (0x3U)
+#define SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_SHIFT       (0U)
+/*! ICC_ADJ - ICC_ADJ Current Select */
+#define SYSCTL2_ANA_GRP_CTRL_ICC_ADJ(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_MASK)
+
+#define SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_MASK        (0xCU)
+#define SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_SHIFT       (2U)
+/*! IPP_ADJ - IPP_ADJ Current Select */
+#define SYSCTL2_ANA_GRP_CTRL_IPP_ADJ(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_MASK)
+
+#define SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_MASK   (0x20U)
+#define SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_SHIFT  (5U)
+/*! AVDD1815_SEL - AVDD Select */
+#define SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_MASK)
+
+#define SYSCTL2_ANA_GRP_CTRL_TEST_ANA_MASK       (0x3C0U)
+#define SYSCTL2_ANA_GRP_CTRL_TEST_ANA_SHIFT      (6U)
+/*! TEST_ANA - TEST ANA */
+#define SYSCTL2_ANA_GRP_CTRL_TEST_ANA(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_TEST_ANA_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_TEST_ANA_MASK)
+
+#define SYSCTL2_ANA_GRP_CTRL_PU_XTL_MASK         (0x400U)
+#define SYSCTL2_ANA_GRP_CTRL_PU_XTL_SHIFT        (10U)
+/*! PU_XTL - PU_XTL power up . Provide the reference voltage , USB need it */
+#define SYSCTL2_ANA_GRP_CTRL_PU_XTL(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_PU_XTL_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_PU_XTL_MASK)
+
+#define SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK          (0x1000U)
+#define SYSCTL2_ANA_GRP_CTRL_PU_AG_SHIFT         (12U)
+/*! PU_AG - Analog Group Power Up.Provide the reference current , AVPLL and USB need it */
+#define SYSCTL2_ANA_GRP_CTRL_PU_AG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_PU_AG_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL0 - Audio PLL Control register0 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_MASK    (0x1U)
+#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_SHIFT   (0U)
+/*! EXT_SPEED_EN - EXT_SPEED Enable */
+#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_MASK       (0x1EU)
+#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_SHIFT      (1U)
+/*! EXT_SPEED - External VCO Speed Control for Different VCO Frequencies. */
+#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SPEED_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SPEED_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_MASK (0x20U)
+#define SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_SHIFT (5U)
+/*! EXT_SP_FBRES_EN - External Speed Enable Pin. */
+#define SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_MASK (0x40U)
+#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_SHIFT (6U)
+/*! EXT_SLLP_DAC_EN - EXT_SLLP_DAC Enable */
+#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_MASK    (0x3F80U)
+#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_SHIFT   (7U)
+/*! EXT_SLLP_DAC - VCON Reference Value Set */
+#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_EN_LP_C1_MASK        (0xC000U)
+#define SYSCTL2_AVPLL_CTRL0_EN_LP_C1_SHIFT       (14U)
+/*! EN_LP_C1 - Channel CX LP Enable. */
+#define SYSCTL2_AVPLL_CTRL0_EN_LP_C1(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EN_LP_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EN_LP_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_MASK      (0x10000U)
+#define SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_SHIFT     (16U)
+/*! EN_DPLL_C1 - Enable/ Disable Channel CX¡¯s DPLL */
+#define SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_MASK   (0x60000U)
+#define SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_SHIFT  (17U)
+/*! DPHER_DLY_SEL - DPHERCK Delay Tune */
+#define SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_MASK   (0x80000U)
+#define SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_SHIFT  (19U)
+/*! CLKOUT_TST_EN - Clock Out Test Output Enable */
+#define SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_MASK      (0x100000U)
+#define SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_SHIFT     (20U)
+/*! CLK_DET_EN - PI Output Clock Enable for Internal Reset Circuit */
+#define SYSCTL2_AVPLL_CTRL0_CLK_DET_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_MASK       (0x3FE00000U)
+#define SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_SHIFT      (21U)
+/*! CAL_FBDIV - FBDIV Calibration */
+#define SYSCTL2_AVPLL_CTRL0_CAL_FBDIV(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_SHIFT)) & SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL1 - Audio PLL Control register1 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_MASK (0x1U)
+#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_SHIFT (0U)
+/*! FREQ_OFFSET_READY_C1 - Indicate Frequency Offset Value Readiness. */
+#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_MASK  (0xFFFFEU)
+#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_SHIFT (1U)
+/*! FREQ_OFFSET_C1 - FREQ_OFFSET_CX[18:0] Set */
+#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL1_FBDIV_MASK           (0x1FF00000U)
+#define SYSCTL2_AVPLL_CTRL1_FBDIV_SHIFT          (20U)
+/*! FBDIV - Feedback Clock Divider Select */
+#define SYSCTL2_AVPLL_CTRL1_FBDIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL1_FBDIV_SHIFT)) & SYSCTL2_AVPLL_CTRL1_FBDIV_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL2 - Audio PLL Control register2 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL2_PW_SLLP_MASK         (0x7U)
+#define SYSCTL2_AVPLL_CTRL2_PW_SLLP_SHIFT        (0U)
+/*! PW_SLLP - PLL in Slow Loop */
+#define SYSCTL2_AVPLL_CTRL2_PW_SLLP(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PW_SLLP_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PW_SLLP_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_MASK (0x8U)
+#define SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_SHIFT (3U)
+/*! PU_OFST_CTRL_C1 - Power Up/Down FREQ_OFFSET Integrator of CX */
+#define SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_PU_C1_MASK           (0x10U)
+#define SYSCTL2_AVPLL_CTRL2_PU_C1_SHIFT          (4U)
+/*! PU_C1 - Power Up/Down Channel CX */
+#define SYSCTL2_AVPLL_CTRL2_PU_C1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PU_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PU_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_PU_MASK              (0x20U)
+#define SYSCTL2_AVPLL_CTRL2_PU_SHIFT             (5U)
+/*! PU - PLL Power-up Signal */
+#define SYSCTL2_AVPLL_CTRL2_PU(x)                (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PU_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PU_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_MASK  (0x40U)
+#define SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_SHIFT (6U)
+/*! POSTDIV_0P5_C1 - Audio Clock Divider Program Set */
+#define SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_MASK   (0x380U)
+#define SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_SHIFT  (7U)
+/*! PLL_VDDRA_SEL - Gate Voltage Select for VDDBUF */
+#define SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_MASK  (0x400U)
+#define SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_SHIFT (10U)
+/*! PLL_LPFC2_LESS - LPF C2 Capacitor Value Select */
+#define SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_MASK  (0xF800U)
+#define SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_SHIFT (11U)
+/*! PLL_CALCLK_DIV - Divider Settings to Generate Calibration Clock. */
+#define SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_MASK   (0x10000U)
+#define SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_SHIFT  (16U)
+/*! PLL_CAL_START - PLL Calibration Start. */
+#define SYSCTL2_AVPLL_CTRL2_PLL_CAL_START(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_MODE_MASK            (0x60000U)
+#define SYSCTL2_AVPLL_CTRL2_MODE_SHIFT           (17U)
+/*! MODE - Feedback Clock for PLL Select */
+#define SYSCTL2_AVPLL_CTRL2_MODE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_MODE_SHIFT)) & SYSCTL2_AVPLL_CTRL2_MODE_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_MASK   (0x80000U)
+#define SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_SHIFT  (19U)
+/*! MASTER_SLAVEB - This signal synchronizes frequencies of the two PLL¡¯s that are being used */
+#define SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_SHIFT)) & SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_INTPR_MASK           (0x700000U)
+#define SYSCTL2_AVPLL_CTRL2_INTPR_SHIFT          (20U)
+/*! INTPR - PI Rload Resistor Select */
+#define SYSCTL2_AVPLL_CTRL2_INTPR(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_INTPR_SHIFT)) & SYSCTL2_AVPLL_CTRL2_INTPR_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_INTPI_MASK           (0x7800000U)
+#define SYSCTL2_AVPLL_CTRL2_INTPI_SHIFT          (23U)
+/*! INTPI - PI Bias Current Select */
+#define SYSCTL2_AVPLL_CTRL2_INTPI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_INTPI_SHIFT)) & SYSCTL2_AVPLL_CTRL2_INTPI_MASK)
+
+#define SYSCTL2_AVPLL_CTRL2_ICP_MASK             (0x78000000U)
+#define SYSCTL2_AVPLL_CTRL2_ICP_SHIFT            (27U)
+/*! ICP - Charge Pump Current Control Bits */
+#define SYSCTL2_AVPLL_CTRL2_ICP(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_ICP_SHIFT)) & SYSCTL2_AVPLL_CTRL2_ICP_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL3 - Audio PLL Control register3 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_MASK (0xFU)
+#define SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_SHIFT (0U)
+/*! REG_SETTLE_LIMIT - Waiting Time Select Before Calibration Start.. */
+#define SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_SHIFT)) & SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_MASK)
+
+#define SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_MASK (0x10U)
+#define SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_SHIFT (4U)
+/*! REG_RING_EXTRA_I_EN - Extra Current Turn On Select. */
+#define SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL3_REFDIV_MASK          (0xFE0U)
+#define SYSCTL2_AVPLL_CTRL3_REFDIV_SHIFT         (5U)
+/*! REFDIV - Reference Clock Divider Select */
+#define SYSCTL2_AVPLL_CTRL3_REFDIV(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_REFDIV_SHIFT)) & SYSCTL2_AVPLL_CTRL3_REFDIV_MASK)
+
+#define SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_MASK      (0xFFFFF000U)
+#define SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_SHIFT     (12U)
+/*! P_SYNC1_C1 - Set DPLL¡¯s Reference Divider */
+#define SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL4 - Audio PLL Control register4 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_MASK     (0x1U)
+#define SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_SHIFT    (0U)
+/*! SLLP_EN_DIS - Slow Loop Select. */
+#define SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_SHIFT)) & SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_MASK)
+
+#define SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_MASK (0x2U)
+#define SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_SHIFT (1U)
+/*! SLLP_CLK_DIV5EN - Slow Loop Clock Enable */
+#define SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_SHIFT)) & SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_MASK  (0x4U)
+#define SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_SHIFT (2U)
+/*! SEL_VTHVCOCONT - Select Threshold Source for Calibrated VDDVCO Voltage */
+#define SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_SHIFT)) & SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_MASK)
+
+#define SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_MASK  (0x1F8U)
+#define SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_SHIFT (3U)
+/*! RESERVE_PLL_IN - Reserved pins */
+#define SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_SHIFT)) & SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_MASK)
+
+#define SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_MASK   (0x600U)
+#define SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_SHIFT  (9U)
+/*! RESERVE_IN_C1 - Reserved pins */
+#define SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_MASK      (0x7FFFF800U)
+#define SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_SHIFT     (11U)
+/*! P_SYNC2_C1 - Set DPLL¡¯s Feedback Divider */
+#define SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL5 - Audio PLL Control register5 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL5_TEST_MON_MASK        (0x3FU)
+#define SYSCTL2_AVPLL_CTRL5_TEST_MON_SHIFT       (0U)
+/*! TEST_MON - DC Test Point Register. For Internal Use Only. */
+#define SYSCTL2_AVPLL_CTRL5_TEST_MON(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_TEST_MON_SHIFT)) & SYSCTL2_AVPLL_CTRL5_TEST_MON_MASK)
+
+#define SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_MASK    (0xFC0U)
+#define SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_SHIFT   (6U)
+/*! SPEED_THRESH - Threshold for VCO Speed Setting Calibration. */
+#define SYSCTL2_AVPLL_CTRL5_SPEED_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_SHIFT)) & SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_MASK)
+
+#define SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_MASK     (0xF000U)
+#define SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_SHIFT    (12U)
+/*! SPEED_FBRES - External feedback resistor (VCO ring) set up bits */
+#define SYSCTL2_AVPLL_CTRL5_SPEED_FBRES(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_SHIFT)) & SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_MASK)
+
+#define SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_MASK  (0x70000U)
+#define SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_SHIFT (16U)
+/*! SLLP_PSF_LEVEL - Slow Loop Current Generate. */
+#define SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_SHIFT)) & SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_MASK      (0xFFF80000U)
+#define SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_SHIFT     (19U)
+/*! POSTDIV_C1 - Audio Clock Divider Program Set */
+#define SYSCTL2_AVPLL_CTRL5_POSTDIV_C1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL6 - Audio PLL Control register6 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_MASK    (0x3U)
+#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_SHIFT   (0U)
+/*! VTH_VCO_PTAT - IPTAT Current to Generate VDDVCO Voltage Select */
+#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_MASK)
+
+#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_MASK     (0xCU)
+#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_SHIFT    (2U)
+/*! VTH_VCO_CAL - VDDVCO Voltage Threshold Select */
+#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL6_VDDL_MASK            (0xF0U)
+#define SYSCTL2_AVPLL_CTRL6_VDDL_SHIFT           (4U)
+/*! VDDL - Internal Regulated VDD Supply Voltage Control */
+#define SYSCTL2_AVPLL_CTRL6_VDDL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VDDL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VDDL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_MASK      (0x700U)
+#define SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_SHIFT     (8U)
+/*! VDDBUF_ADJ - VDDVDOFBUF Voltage Level Adjust */
+#define SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_MASK)
+
+#define SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_MASK (0x1800U)
+#define SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_SHIFT (11U)
+/*! VDDA23_PUMP_SEL - VREF0P96_VDDA23 PUMP Select */
+#define SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL6_VCON_SEL_MASK        (0x6000U)
+#define SYSCTL2_AVPLL_CTRL6_VCON_SEL_SHIFT       (13U)
+/*! VCON_SEL - VCON Value Set. */
+#define SYSCTL2_AVPLL_CTRL6_VCON_SEL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VCON_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VCON_SEL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_MASK (0x18000U)
+#define SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_SHIFT (15U)
+/*! VCO_REF1P45_SEL - VREF1P0V_VCO1P45 Value Select. */
+#define SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_MASK)
+
+#define SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_MASK      (0x20000U)
+#define SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_SHIFT     (17U)
+/*! UPDATE_SEL - PLL Update Rate Select */
+#define SYSCTL2_AVPLL_CTRL6_UPDATE_SEL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL7 - Audio PLL Control register7 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL7_PLL_LOCK_MASK        (0x1000000U)
+#define SYSCTL2_AVPLL_CTRL7_PLL_LOCK_SHIFT       (24U)
+/*! PLL_LOCK - Lock Detect Output */
+#define SYSCTL2_AVPLL_CTRL7_PLL_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL7_PLL_LOCK_SHIFT)) & SYSCTL2_AVPLL_CTRL7_PLL_LOCK_MASK)
+
+#define SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_MASK    (0x2000000U)
+#define SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_SHIFT   (25U)
+/*! PLL_CAL_DONE - Rising edge to indicate the end of PLL calibration */
+#define SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_SHIFT)) & SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL8 - Audio PLL Control register8 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_MASK  (0x1U)
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_SHIFT (0U)
+/*! AVPLL_RESET_C8 - C8 SW Reset . Active high */
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_MASK  (0x2U)
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_SHIFT (1U)
+/*! AVPLL_RESET_C1 - C1 SW Reset . Active high */
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_MASK     (0x4U)
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_SHIFT    (2U)
+/*! AVPLL_RESET - SW Reset . Active high */
+#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_SHIFT)) & SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_MASK   (0x18U)
+#define SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_SHIFT  (3U)
+/*! RESERVE_IN_C8 - Reserved pins */
+#define SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_MASK (0x20U)
+#define SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_SHIFT (5U)
+/*! PU_OFST_CTRL_C8 - Power Up/Down FREQ_OFFSET Integrator of CX */
+#define SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_MASK (0x40U)
+#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_SHIFT (6U)
+/*! FREQ_OFFSET_READY_C8 - Indicate Frequency Offset Value Readiness. */
+#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_MASK  (0x3FFFF80U)
+#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_SHIFT (7U)
+/*! FREQ_OFFSET_C8 - FREQ_OFFSET_CX[18:0] Set */
+#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_EN_LP_C8_MASK        (0xC000000U)
+#define SYSCTL2_AVPLL_CTRL8_EN_LP_C8_SHIFT       (26U)
+/*! EN_LP_C8 - Channel CX LP Enable. */
+#define SYSCTL2_AVPLL_CTRL8_EN_LP_C8(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_EN_LP_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_EN_LP_C8_MASK)
+
+#define SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_MASK      (0x10000000U)
+#define SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_SHIFT     (28U)
+/*! EN_DPLL_C8 - Enable/ Disable Channel CX¡¯s DPLL */
+#define SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL9 - Audio PLL Control register9 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_MASK      (0xFFFFFU)
+#define SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_SHIFT     (0U)
+/*! P_SYNC1_C8 - Set DPLL¡¯s Reference Divider */
+#define SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL10 - Audio PLL Control register10 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_MASK     (0xFFFFFU)
+#define SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_SHIFT    (0U)
+/*! P_SYNC2_C8 - Set DPLL¡¯s Feedback Divider */
+#define SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL11 - Audio PLL Control register11 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_MASK (0x7FFFFU)
+#define SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_SHIFT (0U)
+/*! FREQ_OFFSET_C2 - FREQ_OFFSET_CX[18:0] Set */
+#define SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_MASK     (0xFFF80000U)
+#define SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_SHIFT    (19U)
+/*! POSTDIV_C2 - Audio Clock Divider Program Set */
+#define SYSCTL2_AVPLL_CTRL11_POSTDIV_C2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL12 - Audio PLL Control register12 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_MASK     (0xFFFFFU)
+#define SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_SHIFT    (0U)
+/*! P_SYNC1_C2 - Set DPLL¡¯s Reference Divider */
+#define SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL12_EN_LP_C2_MASK       (0x300000U)
+#define SYSCTL2_AVPLL_CTRL12_EN_LP_C2_SHIFT      (20U)
+/*! EN_LP_C2 - Channel CX LP Enable. */
+#define SYSCTL2_AVPLL_CTRL12_EN_LP_C2(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_EN_LP_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_EN_LP_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_MASK     (0x400000U)
+#define SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_SHIFT    (22U)
+/*! EN_DPLL_C2 - Enable/ Disable Channel CX¡¯s DPLL */
+#define SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_MASK (0x800000U)
+#define SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_SHIFT (23U)
+/*! PU_OFST_CTRL_C2 - Power Up/Down FREQ_OFFSET Integrator of CX */
+#define SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL12_PU_C2_MASK          (0x1000000U)
+#define SYSCTL2_AVPLL_CTRL12_PU_C2_SHIFT         (24U)
+/*! PU_C2 - Power Up/Down Channel CX */
+#define SYSCTL2_AVPLL_CTRL12_PU_C2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_PU_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_PU_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_MASK (0x2000000U)
+#define SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_SHIFT (25U)
+/*! POSTDIV_0P5_C2 - Audio Clock Divider Program Set */
+#define SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_MASK (0x4000000U)
+#define SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_SHIFT (26U)
+/*! FREQ_OFFSET_READY_C2 - Indicate Frequency Offset Value Readiness. */
+#define SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_MASK)
+/*! @} */
+
+/*! @name GAU_CTRL - GAU Control register */
+/*! @{ */
+
+#define SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_MASK  (0x1U)
+#define SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_SHIFT (0U)
+/*! GAU_GPDAC_MCLK_EN - gau gpdac mclk enable */
+#define SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_MASK)
+
+#define SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_MASK     (0x2U)
+#define SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_SHIFT    (1U)
+/*! GAU_BG_MCLK_EN - gau bg mclk enable */
+#define SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_MASK)
+
+#define SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_MASK (0x4U)
+#define SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_SHIFT (2U)
+/*! GAU_GPADC1_MCLK_EN - gau gpadc1 mclk enable */
+#define SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_MASK)
+
+#define SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_MASK (0x8U)
+#define SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_SHIFT (3U)
+/*! GAU_GPADC0_MCLK_EN - gau gpadc0 mclk enable */
+#define SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_MASK)
+
+#define SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_MASK  (0x10U)
+#define SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_SHIFT (4U)
+/*! GAU_ACOMP_MCLK_EN - gau acomp mclk enable */
+#define SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_MASK)
+/*! @} */
+
+/*! @name CTIMER_CTRL - CTIMER Control register */
+/*! @{ */
+
+#define SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_MASK (0x1U)
+#define SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_SHIFT (0U)
+/*! CT0_GLOBAL_ENABLE - ctimer0 global_enable */
+#define SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_MASK)
+
+#define SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_MASK (0x2U)
+#define SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_SHIFT (1U)
+/*! CT0_TRIGGER_ENABLE - ctimer0 trigger_enable */
+#define SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_MASK)
+
+#define SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_MASK (0x4U)
+#define SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_SHIFT (2U)
+/*! CT1_GLOBAL_ENABLE - ctimer1 global_enable */
+#define SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_MASK)
+
+#define SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_MASK (0x8U)
+#define SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_SHIFT (3U)
+/*! CT1_TRIGGER_ENABLE - ctimer1 trigger_enable */
+#define SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_MASK)
+
+#define SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_MASK (0x10U)
+#define SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_SHIFT (4U)
+/*! CT2_GLOBAL_ENABLE - ctimer2 global_enable */
+#define SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_MASK)
+
+#define SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_MASK (0x20U)
+#define SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_SHIFT (5U)
+/*! CT2_TRIGGER_ENABLE - ctimer2 trigger_enable */
+#define SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_MASK)
+
+#define SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_MASK (0x40U)
+#define SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_SHIFT (6U)
+/*! CT3_GLOBAL_ENABLE - ctimer3 global_enable */
+#define SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_MASK)
+
+#define SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_MASK (0x80U)
+#define SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_SHIFT (7U)
+/*! CT3_TRIGGER_ENABLE - ctimer3 trigger_enable */
+#define SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_MASK)
+/*! @} */
+
+/*! @name EXT_H2H_CTRL - AHB async bridge Control register */
+/*! @{ */
+
+#define SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_MASK (0x1U)
+#define SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_SHIFT (0U)
+/*! WLAN_H2H_PREFETCH_EN - wlan_h2h_prefetch_en */
+#define SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_SHIFT)) & SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_MASK)
+
+#define SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_MASK (0x2U)
+#define SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_SHIFT (1U)
+/*! BLE_H2H_PREFETCH_EN - ble_h2h_prefetch_en */
+#define SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_SHIFT)) & SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_MASK)
+/*! @} */
+
+/*! @name RAM_CTRL1 - RAM Memory Control Register 1 */
+/*! @{ */
+
+#define SYSCTL2_RAM_CTRL1_PKC_RTC_MASK           (0x3U)
+#define SYSCTL2_RAM_CTRL1_PKC_RTC_SHIFT          (0U)
+/*! PKC_RTC - pkc_rtc */
+#define SYSCTL2_RAM_CTRL1_PKC_RTC(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PKC_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PKC_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_PKC_WTC_MASK           (0xCU)
+#define SYSCTL2_RAM_CTRL1_PKC_WTC_SHIFT          (2U)
+/*! PKC_WTC - pkc_wtc */
+#define SYSCTL2_RAM_CTRL1_PKC_WTC(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PKC_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PKC_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_PQ_RTC_MASK            (0x30U)
+#define SYSCTL2_RAM_CTRL1_PQ_RTC_SHIFT           (4U)
+/*! PQ_RTC - pq_rtc */
+#define SYSCTL2_RAM_CTRL1_PQ_RTC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PQ_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PQ_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_PQ_WTC_MASK            (0xC0U)
+#define SYSCTL2_RAM_CTRL1_PQ_WTC_SHIFT           (6U)
+/*! PQ_WTC - pq_wtc */
+#define SYSCTL2_RAM_CTRL1_PQ_WTC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PQ_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PQ_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_MASK       (0x300U)
+#define SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_SHIFT      (8U)
+/*! S0_SRAM_RTC - s0_sram_rtc */
+#define SYSCTL2_RAM_CTRL1_S0_SRAM_RTC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_MASK       (0xC00U)
+#define SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_SHIFT      (10U)
+/*! S0_SRAM_WTC - s0_sram_wtc */
+#define SYSCTL2_RAM_CTRL1_S0_SRAM_WTC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_MASK       (0x3000U)
+#define SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_SHIFT      (12U)
+/*! SDU_CIS_RTC - sdu_cis_rtc */
+#define SYSCTL2_RAM_CTRL1_SDU_CIS_RTC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_MASK       (0xC000U)
+#define SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_SHIFT      (14U)
+/*! SDU_CIS_WTC - sdu_cis_wtc */
+#define SYSCTL2_RAM_CTRL1_SDU_CIS_WTC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_SDU_RX_RTC_MASK        (0x30000U)
+#define SYSCTL2_RAM_CTRL1_SDU_RX_RTC_SHIFT       (16U)
+/*! SDU_RX_RTC - sdu_rx_rtc */
+#define SYSCTL2_RAM_CTRL1_SDU_RX_RTC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_RX_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_RX_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_SDU_RX_WTC_MASK        (0xC0000U)
+#define SYSCTL2_RAM_CTRL1_SDU_RX_WTC_SHIFT       (18U)
+/*! SDU_RX_WTC - sdu_rx_wtc */
+#define SYSCTL2_RAM_CTRL1_SDU_RX_WTC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_RX_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_RX_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_SDU_TX_RTC_MASK        (0x300000U)
+#define SYSCTL2_RAM_CTRL1_SDU_TX_RTC_SHIFT       (20U)
+/*! SDU_TX_RTC - sdu_tx_rtc */
+#define SYSCTL2_RAM_CTRL1_SDU_TX_RTC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_TX_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_TX_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_SDU_TX_WTC_MASK        (0xC00000U)
+#define SYSCTL2_RAM_CTRL1_SDU_TX_WTC_SHIFT       (22U)
+/*! SDU_TX_WTC - sdu_tx_wtc */
+#define SYSCTL2_RAM_CTRL1_SDU_TX_WTC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_TX_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_TX_WTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_ENET_RTC_MASK          (0x3000000U)
+#define SYSCTL2_RAM_CTRL1_ENET_RTC_SHIFT         (24U)
+/*! ENET_RTC - enet_rtc */
+#define SYSCTL2_RAM_CTRL1_ENET_RTC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_ENET_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_ENET_RTC_MASK)
+
+#define SYSCTL2_RAM_CTRL1_ENET_WTC_MASK          (0xC000000U)
+#define SYSCTL2_RAM_CTRL1_ENET_WTC_SHIFT         (26U)
+/*! ENET_WTC - enet_wtc */
+#define SYSCTL2_RAM_CTRL1_ENET_WTC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_ENET_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_ENET_WTC_MASK)
+/*! @} */
+
+/*! @name ROM_CTRL - ROM Control Register */
+/*! @{ */
+
+#define SYSCTL2_ROM_CTRL_ELS_RTC_MASK            (0x7U)
+#define SYSCTL2_ROM_CTRL_ELS_RTC_SHIFT           (0U)
+/*! ELS_RTC - els_rtc */
+#define SYSCTL2_ROM_CTRL_ELS_RTC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_ELS_RTC_SHIFT)) & SYSCTL2_ROM_CTRL_ELS_RTC_MASK)
+
+#define SYSCTL2_ROM_CTRL_ELS_RTC_REF_MASK        (0x18U)
+#define SYSCTL2_ROM_CTRL_ELS_RTC_REF_SHIFT       (3U)
+/*! ELS_RTC_REF - els_rtc_ref */
+#define SYSCTL2_ROM_CTRL_ELS_RTC_REF(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_ELS_RTC_REF_SHIFT)) & SYSCTL2_ROM_CTRL_ELS_RTC_REF_MASK)
+
+#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_MASK         (0xE0U)
+#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_SHIFT        (5U)
+/*! S0_ROM_RTC - s0_rom_rtc */
+#define SYSCTL2_ROM_CTRL_S0_ROM_RTC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_S0_ROM_RTC_SHIFT)) & SYSCTL2_ROM_CTRL_S0_ROM_RTC_MASK)
+
+#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_MASK     (0x300U)
+#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_SHIFT    (8U)
+/*! S0_ROM_RTC_REF - s0_rom_rtc_ref */
+#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_SHIFT)) & SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_MASK)
+/*! @} */
+
+/*! @name MEM_PD_CTRL - MEM PD Control enable register when PM2 mode */
+/*! @{ */
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_MASK (0x1U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_SHIFT (0U)
+/*! SRAM0_SW_CTRL_EN - SW control sram0 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_MASK (0x2U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_SHIFT (1U)
+/*! SRAM1_SW_CTRL_EN - SW control sram1 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_MASK (0x4U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_SHIFT (2U)
+/*! SRAM2_SW_CTRL_EN - SW control sram2 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_MASK (0x8U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_SHIFT (3U)
+/*! SRAM3_SW_CTRL_EN - SW control sram3 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_MASK (0x10U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_SHIFT (4U)
+/*! SRAM4_SW_CTRL_EN - SW control sram4 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_MASK (0x20U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_SHIFT (5U)
+/*! SRAM5_SW_CTRL_EN - SW control sram5 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_MASK (0x40U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_SHIFT (6U)
+/*! SRAM6_SW_CTRL_EN - SW control sram6 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_MASK (0x80U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_SHIFT (7U)
+/*! SRAM7_SW_CTRL_EN - SW control sram7 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_MASK (0x100U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_SHIFT (8U)
+/*! SRAM8_SW_CTRL_EN - SW control sram8 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_MASK (0x200U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_SHIFT (9U)
+/*! SRAM9_SW_CTRL_EN - SW control sram9 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_MASK (0x400U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_SHIFT (10U)
+/*! SRAM10_SW_CTRL_EN - SW control sram10 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_MASK (0x800U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_SHIFT (11U)
+/*! SRAM11_SW_CTRL_EN - SW control sram11 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_MASK (0x1000U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_SHIFT (12U)
+/*! SRAM12_SW_CTRL_EN - SW control sram12 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_MASK (0x2000U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_SHIFT (13U)
+/*! SRAM13_SW_CTRL_EN - SW control sram13 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_MASK (0x4000U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_SHIFT (14U)
+/*! SRAM14_SW_CTRL_EN - SW control sram14 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_MASK (0x8000U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_SHIFT (15U)
+/*! SRAM15_SW_CTRL_EN - SW control sram15 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_MASK (0x10000U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_SHIFT (16U)
+/*! SRAM16_SW_CTRL_EN - SW control sram16 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_MASK (0x20000U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_SHIFT (17U)
+/*! SRAM17_SW_CTRL_EN - SW control sram17 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_MASK (0x40000U)
+#define SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_SHIFT (18U)
+/*! SRAM18_SW_CTRL_EN - SW control sram18 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_MASK (0x80000U)
+#define SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_SHIFT (19U)
+/*! AON0_SW_CTRL_EN - SW control aon0 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_MASK (0x100000U)
+#define SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_SHIFT (20U)
+/*! AON1_SW_CTRL_EN - SW control aon1 mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_MASK  (0x200000U)
+#define SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_SHIFT (21U)
+/*! ELS_SW_CTRL_EN - SW control els mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_MASK  (0x400000U)
+#define SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_SHIFT (22U)
+/*! PKC_SW_CTRL_EN - SW control pkc mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_MASK   (0x800000U)
+#define SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_SHIFT  (23U)
+/*! PQ_SW_CTRL_EN - SW control pq mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_MASK (0x1000000U)
+#define SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_SHIFT (24U)
+/*! FLEXSPI_SW_CTRL_EN - SW control flexspi mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_MASK  (0x2000000U)
+#define SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_SHIFT (25U)
+/*! ROM_SW_CTRL_EN - SW control rom mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_MASK  (0x4000000U)
+#define SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_SHIFT (26U)
+/*! OTP_SW_CTRL_EN - SW control otp mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_MASK (0x8000000U)
+#define SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_SHIFT (27U)
+/*! SDIO_SW_CTRL_EN - SW control sdio mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_MASK)
+
+#define SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_MASK (0x10000000U)
+#define SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_SHIFT (28U)
+/*! ENET_SW_CTRL_EN - SW control enet mem_pd signal enable when PM2 mode */
+#define SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_MASK)
+/*! @} */
+
+/*! @name MEM_PD_CFG - MEM PD Configure register when PM2 mode */
+/*! @{ */
+
+#define SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_MASK     (0x1U)
+#define SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_SHIFT    (0U)
+/*! SRAM0_SW_CFG - sw cfg sram0 mem_pdwn signal when PM2 mode; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_MASK     (0x2U)
+#define SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_SHIFT    (1U)
+/*! SRAM1_SW_CFG - sw cfg sram1 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_MASK     (0x4U)
+#define SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_SHIFT    (2U)
+/*! SRAM2_SW_CFG - sw cfg sram2 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_MASK     (0x8U)
+#define SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_SHIFT    (3U)
+/*! SRAM3_SW_CFG - sw cfg sram3 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_MASK     (0x10U)
+#define SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_SHIFT    (4U)
+/*! SRAM4_SW_CFG - sw cfg sram4 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_MASK     (0x20U)
+#define SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_SHIFT    (5U)
+/*! SRAM5_SW_CFG - sw cfg sram5 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_MASK     (0x40U)
+#define SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_SHIFT    (6U)
+/*! SRAM6_SW_CFG - sw cfg sram6 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_MASK     (0x80U)
+#define SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_SHIFT    (7U)
+/*! SRAM7_SW_CFG - sw cfg sram7 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_MASK     (0x100U)
+#define SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_SHIFT    (8U)
+/*! SRAM8_SW_CFG - sw cfg sram8 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_MASK     (0x200U)
+#define SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_SHIFT    (9U)
+/*! SRAM9_SW_CFG - sw cfg sram9 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_MASK    (0x400U)
+#define SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_SHIFT   (10U)
+/*! SRAM10_SW_CFG - sw cfg sram mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_MASK    (0x800U)
+#define SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_SHIFT   (11U)
+/*! SRAM11_SW_CFG - sw cfg sram11 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_MASK    (0x1000U)
+#define SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_SHIFT   (12U)
+/*! SRAM12_SW_CFG - sw cfg sram12 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_MASK    (0x2000U)
+#define SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_SHIFT   (13U)
+/*! SRAM13_SW_CFG - sw cfg sram13 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_MASK    (0x4000U)
+#define SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_SHIFT   (14U)
+/*! SRAM14_SW_CFG - sw cfg sram14 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_MASK    (0x8000U)
+#define SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_SHIFT   (15U)
+/*! SRAM15_SW_CFG - sw cfg sram15 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_MASK    (0x10000U)
+#define SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_SHIFT   (16U)
+/*! SRAM16_SW_CFG - sw cfg sram16 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_MASK    (0x20000U)
+#define SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_SHIFT   (17U)
+/*! SRAM17_SW_CFG - sw cfg sram17 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_MASK    (0x40000U)
+#define SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_SHIFT   (18U)
+/*! SRAM18_SW_CFG - sw cfg sram18 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_MASK      (0x80000U)
+#define SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_SHIFT     (19U)
+/*! AON0_SW_CFG - sw cfg aon0 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_AON0_SW_CFG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_MASK      (0x100000U)
+#define SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_SHIFT     (20U)
+/*! AON1_SW_CFG - sw cfg aon1 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_AON1_SW_CFG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_MASK       (0x200000U)
+#define SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_SHIFT      (21U)
+/*! ELS_SW_CFG - sw cfg els mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_ELS_SW_CFG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_MASK       (0x400000U)
+#define SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_SHIFT      (22U)
+/*! PKC_SW_CFG - sw cfg pkc mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_PKC_SW_CFG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_MASK        (0x800000U)
+#define SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_SHIFT       (23U)
+/*! PQ_SW_CFG - sw cfg pq mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_PQ_SW_CFG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_MASK   (0x1000000U)
+#define SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_SHIFT  (24U)
+/*! FLEXSPI_SW_CFG - sw cfg flexspi mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_MASK       (0x2000000U)
+#define SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_SHIFT      (25U)
+/*! ROM_SW_CFG - sw cfg rom mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_ROM_SW_CFG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_MASK       (0x4000000U)
+#define SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_SHIFT      (26U)
+/*! OTP_SW_CFG - sw cfg otp mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_OTP_SW_CFG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_MASK      (0x8000000U)
+#define SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_SHIFT     (27U)
+/*! SDIO_SW_CFG - sw cfg sdio mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_MASK)
+
+#define SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_MASK      (0x10000000U)
+#define SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_SHIFT     (28U)
+/*! ENET_SW_CFG - sw cfg enet mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
+#define SYSCTL2_MEM_PD_CFG_ENET_SW_CFG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_MASK)
+/*! @} */
+
+/*! @name ENET_IN_SEL_TIMER - Select input source for enet pad0 */
+/*! @{ */
+
+#define SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_MASK (0x1U)
+#define SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_SHIFT (0U)
+/*! ENET_IN_SEL_TIMER - select input source as enet input */
+#define SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_SHIFT)) & SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_MASK)
+/*! @} */
+
+/*! @name ENET_IPG_STOP - Configure ipg_stop, used by enet wakeup sequence */
+/*! @{ */
+
+#define SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_MASK (0x1U)
+#define SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_SHIFT (0U)
+/*! ENET_IPG_STOP - Configure ipg_stop, used by enet wakeup sequence; 0: Drive enet input IPG_STOP low; 1: Drive enet input IPG_STOP high. */
+#define SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_SHIFT)) & SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_MASK)
+/*! @} */
+
+/*! @name ENET_IPG_STOP_ACK - Store ipg_stop_ack, used by enet wakeup sequence */
+/*! @{ */
+
+#define SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_MASK (0x1U)
+#define SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_SHIFT (0U)
+/*! ENET_IPG_STOP_ACK - Store ipg_stop_ack, used by enet wakeup sequence */
+#define SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_SHIFT)) & SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_MASK)
+/*! @} */
+
+/*! @name ROM_BRU_ADDR_MASK_DIS - Disable dynamic address masking feature */
+/*! @{ */
+
+#define SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_MASK (0x1U)
+#define SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_SHIFT (0U)
+/*! ROM_BRU_ADDR_MASK_DIS - Disable dynamic address masking feature */
+#define SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_SHIFT)) & SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_MASK)
+/*! @} */
+
+/*! @name ROM_BRU_DYN_CLK_DIS - Disable dynamic clock gating feature */
+/*! @{ */
+
+#define SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_MASK (0x1U)
+#define SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_SHIFT (0U)
+/*! ROM_BRU_DYN_CLK_DIS - Disable dynamic clock gating feature */
+#define SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_SHIFT)) & SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_MASK)
+/*! @} */
+
+/*! @name OTP_EARLY_FUSE_VALID - Early fuse valid from OTP */
+/*! @{ */
+
+#define SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_MASK (0x1U)
+#define SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_SHIFT (0U)
+/*! OTP_EARLY_FUSE_VALID - Early fuse valid from OTP */
+#define SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_SHIFT)) & SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_MASK)
+/*! @} */
+
+/*! @name OTP_MEDIUM_FUSE_VALID - Medium fuse valid from OTP */
+/*! @{ */
+
+#define SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_MASK (0x1U)
+#define SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_SHIFT (0U)
+/*! OTP_MEDIUM_FUSE_VALID - Medium fuse valid from OTP */
+#define SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_SHIFT)) & SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_MASK)
+/*! @} */
+
+/*! @name OTP_ALL_FUSE_VALID - All fuse valid from OTP */
+/*! @{ */
+
+#define SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_MASK (0x1U)
+#define SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_SHIFT (0U)
+/*! OTP_ALL_FUSE_VALID - All fuse valid from OTP */
+#define SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_SHIFT)) & SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_MASK)
+/*! @} */
+
+/*! @name PLL_CTRL - PLL control register */
+/*! @{ */
+
+#define SYSCTL2_PLL_CTRL_T3_PDB_MASK             (0x1U)
+#define SYSCTL2_PLL_CTRL_T3_PDB_SHIFT            (0U)
+/*! T3_PDB - T3 PLL enable signal from SOC */
+#define SYSCTL2_PLL_CTRL_T3_PDB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_T3_PDB_SHIFT)) & SYSCTL2_PLL_CTRL_T3_PDB_MASK)
+
+#define SYSCTL2_PLL_CTRL_T3_LOCK_MASK            (0x2U)
+#define SYSCTL2_PLL_CTRL_T3_LOCK_SHIFT           (1U)
+/*! T3_LOCK - T3 output clock lock signal */
+#define SYSCTL2_PLL_CTRL_T3_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_T3_LOCK_SHIFT)) & SYSCTL2_PLL_CTRL_T3_LOCK_MASK)
+
+#define SYSCTL2_PLL_CTRL_TDDR_PDB_MASK           (0x8U)
+#define SYSCTL2_PLL_CTRL_TDDR_PDB_SHIFT          (3U)
+/*! TDDR_PDB - TDDR PLL enable signal from SOC */
+#define SYSCTL2_PLL_CTRL_TDDR_PDB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TDDR_PDB_SHIFT)) & SYSCTL2_PLL_CTRL_TDDR_PDB_MASK)
+
+#define SYSCTL2_PLL_CTRL_TDDR_LOCK_MASK          (0x10U)
+#define SYSCTL2_PLL_CTRL_TDDR_LOCK_SHIFT         (4U)
+/*! TDDR_LOCK - TDDR output clock lock signal */
+#define SYSCTL2_PLL_CTRL_TDDR_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TDDR_LOCK_SHIFT)) & SYSCTL2_PLL_CTRL_TDDR_LOCK_MASK)
+
+#define SYSCTL2_PLL_CTRL_TCPU_PDB_MASK           (0x20U)
+#define SYSCTL2_PLL_CTRL_TCPU_PDB_SHIFT          (5U)
+/*! TCPU_PDB - TCPU PLL enable signal from SOC */
+#define SYSCTL2_PLL_CTRL_TCPU_PDB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_PDB_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_PDB_MASK)
+
+#define SYSCTL2_PLL_CTRL_TCPU_LOCK_MASK          (0x40U)
+#define SYSCTL2_PLL_CTRL_TCPU_LOCK_SHIFT         (6U)
+/*! TCPU_LOCK - TCPU output clock lock signal */
+#define SYSCTL2_PLL_CTRL_TCPU_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_LOCK_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_LOCK_MASK)
+
+#define SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK (0x180U)
+#define SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_SHIFT (7U)
+/*! TCPU_FLEXSPI_CLK_SEL - TCPU_PLL DIV selection(00:3120/12; 01:3120/11; 10: 3120/10; 11:3120/9) */
+#define SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK)
+
+#define SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK         (0x1FE00U)
+#define SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIFT        (9U)
+/*! TCPU_FBDIV - TCPU_PLL Feedback Divider Value ( Fxtal 40MHZ: 75 to 96 (decimal); 38.4MHz 78 to 100 (decimal)) */
+#define SYSCTL2_PLL_CTRL_TCPU_FBDIV(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK)
+
+#define SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK (0x60000U)
+#define SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_SHIFT (17U)
+/*! TDDR_FLEXSPI_CLK_SEL - TDDR_PLL Clock selection from SOC for DDR CLOCK (00:3.2GHZ/11; 01: 3.2GHZ/10; 10: 3.2GHz/9;11: 3.2GHz/8) */
+#define SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_SHIFT)) & SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK)
+
+#define SYSCTL2_PLL_CTRL_T3_ITRC_EN_MASK         (0x80000U)
+#define SYSCTL2_PLL_CTRL_T3_ITRC_EN_SHIFT        (19U)
+/*! T3_ITRC_EN - 0-disable the unlock event to ITRC; 1-enable the unlock event to ITRC */
+#define SYSCTL2_PLL_CTRL_T3_ITRC_EN(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_T3_ITRC_EN_SHIFT)) & SYSCTL2_PLL_CTRL_T3_ITRC_EN_MASK)
+
+#define SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_MASK       (0x100000U)
+#define SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_SHIFT      (20U)
+/*! TCPU_ITRC_EN - 0-disable the unlock event to ITRC; 1-enable the unlock event to ITRC */
+#define SYSCTL2_PLL_CTRL_TCPU_ITRC_EN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_MASK)
+/*! @} */
+
+/*! @name ANA_PDWN_PM2 - ana_pdwn control signal when PM2 mode */
+/*! @{ */
+
+#define SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_MASK (0x1U)
+#define SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_SHIFT (0U)
+/*! AVPLL_ANA_PDWN_PM2 - AVPLL ana_pdwn control signal when PM2 mode, 1: AVPLL is low power mode when PM2 0: AVPLL is normal mode when PM2 */
+#define SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_MASK)
+
+#define SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_MASK (0x2U)
+#define SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_SHIFT (1U)
+/*! USB_ANA_PDWN_PM2 - USB ana_pdwn control signal when PM2 mode, 1: USB is low power mode when PM2 0: USB is normal mode when PM2 */
+#define SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_MASK)
+
+#define SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_MASK (0x4U)
+#define SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_SHIFT (2U)
+/*! GAU_ANA_PDWN_PM2 - GAU ana_pdwn control signal when PM2 mode, 1: GAU is low power mode when PM2 0: GAU is normal mode when PM2 */
+#define SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_MASK)
+
+#define SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_MASK (0x8U)
+#define SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_SHIFT (3U)
+/*! ANA_TOP_ANA_PDWN_PM2 - ANA_TOP ana_pdwn control signal when PM2 mode, 1: ANA_TOP is low power mode when PM2 0: ANA_TOP is normal mode when PM2 */
+#define SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_MASK)
+
+#define SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_MASK (0x10U)
+#define SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_SHIFT (4U)
+/*! TDDR_TOP_ANA_PDWN_PM2 - TDDR_TOP ana_pdwn control signal when PM2 mode, 1: TDDR_TOP is low power
+ *    mode when PM2 0: TDDR_TOP is normal mode when PM2
+ */
+#define SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_MASK)
+
+#define SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_MASK (0x20U)
+#define SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_SHIFT (5U)
+/*! TCPU_TOP_ANA_PDWN_PM2 - TCPU_TOP ana_pdwn control signal when PM2 mode, 1: TCPU_TOP is low power
+ *    mode when PM2 0: TCPU_TOP is normal mode when PM2
+ */
+#define SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_MASK)
+
+#define SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_MASK (0x40U)
+#define SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_SHIFT (6U)
+/*! T3_ANA_PDWN_PM2 - T3 ana_pdwn control signal when PM2 mode, 1: T3 is low power mode when PM2 0: T3 is normal mode when PM2 */
+#define SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_MASK)
+/*! @} */
+
+/*! @name SOURCE_CLK_GATE - source clock gate control */
+/*! @{ */
+
+#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_MASK (0x1U)
+#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_SHIFT (0U)
+/*! TCPU_MCI_CLK_CG - gate tcpu_mci_clk */
+#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_MASK (0x2U)
+#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_SHIFT (1U)
+/*! TCPU_MCI_FLEXSPI_CLK_CG - gate tcpu_mci_flexspi_clk */
+#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_MASK (0x4U)
+#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_SHIFT (2U)
+/*! TDDR_MCI_ENET_CLK_CG - gate tddr_mci_enet_clk */
+#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_MASK (0x8U)
+#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_SHIFT (3U)
+/*! TDDR_MCI_FLEXSPI_CLK_CG - gate tddr_mci_flexspi_clk */
+#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_MASK (0x10U)
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_SHIFT (4U)
+/*! T3PLL_MCI_48_60M_IRC_CG - gate t3pll_mci_48_60m_irc */
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_MASK (0x20U)
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_SHIFT (5U)
+/*! T3PLL_MCI_256M_CG - gate t3pll_mci_256m */
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_MASK (0x40U)
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_SHIFT (6U)
+/*! T3PLL_MCI_213P3M_CG - gate t3pll_mci_213p3m */
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_MASK (0x80U)
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_SHIFT (7U)
+/*! T3PLL_MCI_FLEXSPI_CLK_CG - gate t3pll_mci_flexspi_clk */
+#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK (0x200U)
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_SHIFT (9U)
+/*! REFCLK_SYS_CG - gate refclk_sys */
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_MASK  (0x10000U)
+#define SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_SHIFT (16U)
+/*! CPU_CLK_EN - enable cpu clk(c0_fr_hclk) bypass PMU gate_cpu_clk control */
+#define SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_MASK (0x10000000U)
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_SHIFT (28U)
+/*! REFCLK_TCPU_CG - gate CAU_PHY_RECLK_CPR_TCPU request when PM0; 1:request;0:no request */
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_MASK (0x20000000U)
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_SHIFT (29U)
+/*! REFCLK_TDDR_CG - gate CAU_PHY_RECLK_CPR_TDDR request when PM0; MCI request CAU gate reference
+ *    clock for PHY in PM2 mode (when USB/AUD/TCPU/TDDR PLL are all power down); 1:request;0:no request
+ */
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_MASK (0x40000000U)
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_SHIFT (30U)
+/*! REFCLK_AUD_CG - gate CAU_PHY_RECLK_CPR_AUD request when PM0; 1:request;0:no request */
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_MASK)
+
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_MASK (0x80000000U)
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_SHIFT (31U)
+/*! REFCLK_USB_CG - gate CAU_PHY_RECLK_CPR_USB request when PM0;1:request;0:no request */
+#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_MASK)
+/*! @} */
+
+/*! @name TRNG_PWR_MODE - TRNG_PWR_MODE */
+/*! @{ */
+
+#define SYSCTL2_TRNG_PWR_MODE_STOP_REQ_MASK      (0x1U)
+#define SYSCTL2_TRNG_PWR_MODE_STOP_REQ_SHIFT     (0U)
+/*! STOP_REQ - The bit is used as the SoC low-power request. It is generated to tell TRNG that the
+ *    clock to TRNG is going to stop running. This signal will be asserted no less than two clocks
+ *    before TRNG clock is stopped, to allow TRNG to prepare for stop mode.0: No request; 1:Request
+ */
+#define SYSCTL2_TRNG_PWR_MODE_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PWR_MODE_STOP_REQ_SHIFT)) & SYSCTL2_TRNG_PWR_MODE_STOP_REQ_MASK)
+
+#define SYSCTL2_TRNG_PWR_MODE_STOP_ACK_MASK      (0x2U)
+#define SYSCTL2_TRNG_PWR_MODE_STOP_ACK_SHIFT     (1U)
+/*! STOP_ACK - The bit is used as the SoC low-power acknowledge. TRNG will generate this single
+ *    clock cycle pulse one clock cycle after STOP_REQ has been asserted.0:No Acknowledge; 1:Acknowledge
+ */
+#define SYSCTL2_TRNG_PWR_MODE_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PWR_MODE_STOP_ACK_SHIFT)) & SYSCTL2_TRNG_PWR_MODE_STOP_ACK_MASK)
+/*! @} */
+
+/*! @name TRNG_PIN_CTRL - TRNG_PIN_CTRL */
+/*! @{ */
+
+#define SYSCTL2_TRNG_PIN_CTRL_ENABLE_MASK        (0x1U)
+#define SYSCTL2_TRNG_PIN_CTRL_ENABLE_SHIFT       (0U)
+/*! ENABLE - The bit is used to control the interface of TRNG. 0:Disable; 1: Enable */
+#define SYSCTL2_TRNG_PIN_CTRL_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PIN_CTRL_ENABLE_SHIFT)) & SYSCTL2_TRNG_PIN_CTRL_ENABLE_MASK)
+
+#define SYSCTL2_TRNG_PIN_CTRL_BUSY_MASK          (0x2U)
+#define SYSCTL2_TRNG_PIN_CTRL_BUSY_SHIFT         (1U)
+/*! BUSY - The bit indicate that the TRNG is busy. This happens when the TRNG is busy sampling the
+ *    entropy bits and has not issued an entropy valid signal.0: Free; 1: Busy; this bit should be
+ *    zero after ENABLE(bit0 in this register) is set
+ */
+#define SYSCTL2_TRNG_PIN_CTRL_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PIN_CTRL_BUSY_SHIFT)) & SYSCTL2_TRNG_PIN_CTRL_BUSY_MASK)
+
+#define SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_MASK      (0x4U)
+#define SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_SHIFT     (2U)
+/*! HW_ERROR - The bit indicate that the TRNG has generated a hardware error. This could be due to a
+ *    Frequency Count Fail, a run time or power on reset parameter misconfiguration, and /or a
+ *    failure of one or more of the built in internal entropy quality tests. The cause of the error can
+ *    be decoded by checking the bits of the STATUS register of TRNG.0:No Error; 1: Error
+ */
+#define SYSCTL2_TRNG_PIN_CTRL_HW_ERROR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_SHIFT)) & SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_MASK)
+/*! @} */
+
+/*! @name CAU_CTRL - CAU control register */
+/*! @{ */
+
+#define SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_MASK     (0x1U)
+#define SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_SHIFT    (0U)
+/*! SOC_REFCLK_RDY - REFCLK ready signal, if 1, can turn on PLL */
+#define SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_SHIFT)) & SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_MASK)
+
+#define SYSCTL2_CAU_CTRL_MCI_XOSC_EN_MASK        (0x80000000U)
+#define SYSCTL2_CAU_CTRL_MCI_XOSC_EN_SHIFT       (31U)
+/*! MCI_XOSC_EN - mci request control different modes for CAU XTAL (1 for normal mode, 0 for sleep/full PD) */
+#define SYSCTL2_CAU_CTRL_MCI_XOSC_EN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CAU_CTRL_MCI_XOSC_EN_SHIFT)) & SYSCTL2_CAU_CTRL_MCI_XOSC_EN_MASK)
+/*! @} */
+
+/*! @name SOC_CIU_RDY_MASK - SOC_CIU_RDY_MASK */
+/*! @{ */
+
+#define SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_MASK (0x1U)
+#define SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_SHIFT (0U)
+/*! SOC_CIU_RDY_MASK - 1'b1:mask SOC_CIU_RDY, think its value is 1; 1'b0:unmask SOC_CIU_RDY, see its real value */
+#define SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_SHIFT)) & SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_MASK)
+/*! @} */
+
+/*! @name LE_AUDIO_TIMER_ENABLE - Enable bit for le audio timer */
+/*! @{ */
+
+#define SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_MASK (0x1U)
+#define SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_SHIFT (0U)
+/*! ENABLE - 1'b1:Timer is enabled; 1'b0:Timer is disabled */
+#define SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_MASK)
+/*! @} */
+
+/*! @name LE_AUDIO_TIMER_CNT_CLR - Clear bit of internal counter */
+/*! @{ */
+
+#define SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_MASK  (0x1U)
+#define SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_SHIFT (0U)
+/*! CLR - When timer is enabled, write 1 to clear internal counter, write 0 has no effect */
+#define SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_MASK)
+/*! @} */
+
+/*! @name LE_AUDIO_TIMER_CNT0 - Counter value captured by trigger0 */
+/*! @{ */
+
+#define SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_MASK    (0xFFFFFFFFU)
+#define SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_SHIFT   (0U)
+/*! CNT0 - Counter value captured by trigger0 */
+#define SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_MASK)
+/*! @} */
+
+/*! @name LE_AUDIO_TIMER_CNT1 - Counter value captured by trigger1 */
+/*! @{ */
+
+#define SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_MASK    (0xFFFFFFFFU)
+#define SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_SHIFT   (0U)
+/*! CNT1 - Counter value captured by trigger1 */
+#define SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_MASK)
+/*! @} */
+
+/*! @name LE_AUDIO_TIMER_CNT2 - Counter value captured by trigger2 */
+/*! @{ */
+
+#define SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_MASK    (0xFFFFFFFFU)
+#define SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_SHIFT   (0U)
+/*! CNT2 - Counter value captured by trigger2 */
+#define SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_MASK)
+/*! @} */
+
+/*! @name AVPLL_CTRL13 - Audio PLL Control register13 */
+/*! @{ */
+
+#define SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_MASK (0x1U)
+#define SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_SHIFT (0U)
+/*! AVPLL_RESET_C2 - C2 SW Reset . Active high */
+#define SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_MASK  (0x600U)
+#define SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_SHIFT (9U)
+/*! RESERVE_IN_C2 - Reserved pins */
+#define SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_MASK)
+
+#define SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_MASK     (0x7FFFF800U)
+#define SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_SHIFT    (11U)
+/*! P_SYNC2_C2 - Set DPLL¡¯s Feedback Divider */
+#define SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_STATUS - CPU Code Bus Access Sram Checker Violation Status */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_MASK (0x7FFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_SHIFT (0U)
+/*! STATUS - for each of these 19 bits: 0- No violation; 1-violation happened */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_CLR - CPU Code Bus Access Sram Checker Violation Status Clear */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_MASK (0x7FFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_SHIFT (0U)
+/*! STATUS_CLR - Write '1' to clear Violation Status bit; These bits are self-clear */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_STATUS - CPU SYS Bus Access Sram Checker Violation Status */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_MASK (0x7FFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_SHIFT (0U)
+/*! STATUS - for each of these 19 bits: 0- No violation; 1-violation happened */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_CLR - CPU SYS Bus Access Sram Checker Violation Status Clear */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_MASK (0x7FFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_SHIFT (0U)
+/*! STATUS_CLR - Write '1' to clear Violation Status bit; These bits are self-clear */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_MASK)
+/*! @} */
+
+/*! @name SOC_MCI_EXTRA - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_MASK (0xFFFFFFFFU)
+#define SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_SHIFT (0U)
+/*! SOC_MCI_EXTRA - Reserved register */
+#define SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_SHIFT)) & SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_MASK)
+/*! @} */
+
+/*! @name MCI_SOC_EXTRA - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_SHIFT (0U)
+/*! MCI_SOC_EXTRA - Reserved register */
+#define SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_SHIFT)) & SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_MASK)
+/*! @} */
+
+/*! @name ROM_DYN_CLK_EN - To control dynamic clock gating of the rom clock */
+/*! @{ */
+
+#define SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_MASK (0x2U)
+#define SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_SHIFT (1U)
+/*! ROM_DYN_CLK_EN - To control dynamic clock gating of the rom clock
+ *  0b0..Disable the clock gating
+ *  0b1..Enable the clock gating
+ */
+#define SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_SHIFT)) & SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_MASK)
+/*! @} */
+
+/*! @name RESERVED_REG1 - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_RESERVED_REG1_RESERVED_REG_MASK  (0xFFFFFFFFU)
+#define SYSCTL2_RESERVED_REG1_RESERVED_REG_SHIFT (0U)
+/*! RESERVED_REG - Reserved register */
+#define SYSCTL2_RESERVED_REG1_RESERVED_REG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG1_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG1_RESERVED_REG_MASK)
+/*! @} */
+
+/*! @name RESERVED_REG2 - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_RESERVED_REG2_RESERVED_REG_MASK  (0xFFFFFFFFU)
+#define SYSCTL2_RESERVED_REG2_RESERVED_REG_SHIFT (0U)
+/*! RESERVED_REG - Reserved register */
+#define SYSCTL2_RESERVED_REG2_RESERVED_REG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG2_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG2_RESERVED_REG_MASK)
+/*! @} */
+
+/*! @name RESERVED_REG3 - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_RESERVED_REG3_RESERVED_REG_MASK  (0xFFFFFFFFU)
+#define SYSCTL2_RESERVED_REG3_RESERVED_REG_SHIFT (0U)
+/*! RESERVED_REG - Reserved register */
+#define SYSCTL2_RESERVED_REG3_RESERVED_REG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG3_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG3_RESERVED_REG_MASK)
+/*! @} */
+
+/*! @name RESERVED_REG4 - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_RESERVED_REG4_RESERVED_REG_MASK  (0xFFFFFFFFU)
+#define SYSCTL2_RESERVED_REG4_RESERVED_REG_SHIFT (0U)
+/*! RESERVED_REG - Reserved register */
+#define SYSCTL2_RESERVED_REG4_RESERVED_REG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG4_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG4_RESERVED_REG_MASK)
+/*! @} */
+
+/*! @name RESERVED_REG5 - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_RESERVED_REG5_RESERVED_REG_MASK  (0xFFFFFFFFU)
+#define SYSCTL2_RESERVED_REG5_RESERVED_REG_SHIFT (0U)
+/*! RESERVED_REG - Reserved register */
+#define SYSCTL2_RESERVED_REG5_RESERVED_REG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG5_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG5_RESERVED_REG_MASK)
+/*! @} */
+
+/*! @name RESERVED_REG6 - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_RESERVED_REG6_RESERVED_REG_MASK  (0xFFFFFFFFU)
+#define SYSCTL2_RESERVED_REG6_RESERVED_REG_SHIFT (0U)
+/*! RESERVED_REG - Reserved register */
+#define SYSCTL2_RESERVED_REG6_RESERVED_REG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG6_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG6_RESERVED_REG_MASK)
+/*! @} */
+
+/*! @name RESERVED_REG7 - Reserved register */
+/*! @{ */
+
+#define SYSCTL2_RESERVED_REG7_RESERVED_REG_MASK  (0xFFFFFFFFU)
+#define SYSCTL2_RESERVED_REG7_RESERVED_REG_SHIFT (0U)
+/*! RESERVED_REG - Reserved register */
+#define SYSCTL2_RESERVED_REG7_RESERVED_REG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG7_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG7_RESERVED_REG_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR0 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC0 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR1 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC1 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR2 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC2 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR3 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC3 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR4 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC4 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR5 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC5 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR6 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC6 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR7 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC7 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR8 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC8 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR9 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC9 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR10 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC10 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR11 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC11 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR12 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC12 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR13 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC13 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR14 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC14 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR15 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC15 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR16 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC16 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR17 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC17 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_ADDR18 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_CODE_VIO_MISC18 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR0 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC0 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR1 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC1 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR2 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC2 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR3 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC3 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR4 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC4 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR5 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC5 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR6 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC6 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR7 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC7 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR8 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC8 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR9 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC9 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR10 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC10 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR11 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC11 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR12 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC12 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR13 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC13 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR14 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC14 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR15 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC15 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR16 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC16 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR17 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC17 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_ADDR18 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_MASK (0xFFFFFFFFU)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_SHIFT (0U)
+/*! ADDR - Address of Violated Transfer */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_MASK)
+/*! @} */
+
+/*! @name MEM_ACC_CHK_SYS_VIO_MISC18 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
+/*! @{ */
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_MASK (0x1U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_SHIFT (0U)
+/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_MASK (0x2U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_SHIFT (1U)
+/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_MASK)
+
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_MASK (0xF0U)
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_SHIFT (4U)
+/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
+#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCTL2_Register_Masks */
+
+
+/* SYSCTL2 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SYSCTL2 base address */
+  #define SYSCTL2_BASE                             (0x50003000u)
+  /** Peripheral SYSCTL2 base address */
+  #define SYSCTL2_BASE_NS                          (0x40003000u)
+  /** Peripheral SYSCTL2 base pointer */
+  #define SYSCTL2                                  ((SYSCTL2_Type *)SYSCTL2_BASE)
+  /** Peripheral SYSCTL2 base pointer */
+  #define SYSCTL2_NS                               ((SYSCTL2_Type *)SYSCTL2_BASE_NS)
+  /** Array initializer of SYSCTL2 peripheral base addresses */
+  #define SYSCTL2_BASE_ADDRS                       { SYSCTL2_BASE }
+  /** Array initializer of SYSCTL2 peripheral base pointers */
+  #define SYSCTL2_BASE_PTRS                        { SYSCTL2 }
+  /** Array initializer of SYSCTL2 peripheral base addresses */
+  #define SYSCTL2_BASE_ADDRS_NS                    { SYSCTL2_BASE_NS }
+  /** Array initializer of SYSCTL2 peripheral base pointers */
+  #define SYSCTL2_BASE_PTRS_NS                     { SYSCTL2_NS }
+#else
+  /** Peripheral SYSCTL2 base address */
+  #define SYSCTL2_BASE                             (0x40003000u)
+  /** Peripheral SYSCTL2 base pointer */
+  #define SYSCTL2                                  ((SYSCTL2_Type *)SYSCTL2_BASE)
+  /** Array initializer of SYSCTL2 peripheral base addresses */
+  #define SYSCTL2_BASE_ADDRS                       { SYSCTL2_BASE }
+  /** Array initializer of SYSCTL2 peripheral base pointers */
+  #define SYSCTL2_BASE_PTRS                        { SYSCTL2 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSCTL2_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSPLL_T3 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSPLL_T3_Peripheral_Access_Layer SYSPLL_T3 Peripheral Access Layer
+ * @{
+ */
+
+/** SYSPLL_T3 - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[192];
+  __I  uint8_t SYSBYPASS_SOC_CTRL_ONE_RO_REG;      /**< offset: 0xC0 */
+  __I  uint8_t SYSBYPASS_SOC_CTRL_TWO_RO_REG;      /**< offset: 0xC1 */
+  __I  uint8_t SYSBYPASS_SOC_CTRL_THREE_RO_REG;    /**< offset: 0xC2 */
+  __I  uint8_t SYSBYPASS_BBUD_CTRL_ONE_RO_REG;     /**< offset: 0xC3 */
+  __I  uint8_t REG_RO_REG;                         /**< offset: 0xC4 */
+  __IO uint8_t SYS_CTRL_REG;                       /**< offset: 0xC5 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_ONE_RW_REG;      /**< offset: 0xC6 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_TWO_RW_REG;      /**< offset: 0xC7 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_THREE_RW_REG;    /**< offset: 0xC8 */
+  __IO uint8_t SYSBYPASS_BBUD_CTRL_FOUR_RW_REG;    /**< offset: 0xC9 */
+  __IO uint8_t T3_CTRL_ONE_REG;                    /**< offset: 0xCA */
+  __IO uint8_t T3_CTRL_TWO_REG;                    /**< offset: 0xCB */
+  __IO uint8_t T3_CTRL_THREE_REG;                  /**< offset: 0xCC */
+  __IO uint8_t T3_CTRL_FOUR_REG;                   /**< offset: 0xCD */
+  __IO uint8_t T3_CTRL_FIVE_REG;                   /**< offset: 0xCE */
+  __IO uint8_t T3_CTRL_SIX_REG;                    /**< offset: 0xCF */
+  __IO uint8_t T3_CTRL_SEVEN_REG;                  /**< offset: 0xD0 */
+  __IO uint8_t T3_CTRL_EIGHT_REG;                  /**< offset: 0xD1 */
+  __IO uint8_t T3_CTRL_NINE_REG;                   /**< offset: 0xD2 */
+  __IO uint8_t T3_CTRL_TEN_REG;                    /**< offset: 0xD3 */
+  __IO uint8_t CLKTREE_CTRL_ONE_REG;               /**< offset: 0xD4 */
+  __IO uint8_t CLKTREE_CTRL_TWO_REG;               /**< offset: 0xD5 */
+  __IO uint8_t CLKTREE_CTRL_THREE_REG;             /**< offset: 0xD6 */
+  __IO uint8_t CLKTREE_CTRL_FOUR_REG;              /**< offset: 0xD7 */
+  __IO uint8_t CLKTREE_CTRL_FIVE_REG;              /**< offset: 0xD8 */
+  __IO uint8_t CLKTREE_CTRL_SIX_REG;               /**< offset: 0xD9 */
+  __IO uint8_t GPIO_CTRL_REG;                      /**< offset: 0xDA */
+  __IO uint8_t ATEST_CTRL_REG;                     /**< offset: 0xDB */
+  __IO uint8_t RESERVED_LO_ONE_REG;                /**< offset: 0xDC */
+  __IO uint8_t RESERVED_HI_ONE_REG;                /**< offset: 0xDD */
+  __IO uint8_t RESERVED_MIX_ONE_REG;               /**< offset: 0xDE */
+  __IO uint8_t RESERVED_MIX_TWO_REG;               /**< offset: 0xDF */
+} SYSPLL_T3_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSPLL_T3 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSPLL_T3_Register_Masks SYSPLL_T3 Register Masks
+ * @{
+ */
+
+/*! @name SYSBYPASS_SOC_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_ONE_RO - SYSBYPASS_SOC_CTRL_ONE_RO */
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT)) & SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_TWO_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_TWO_RO - SYSBYPASS_SOC_CTRL_TWO_RO */
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT)) & SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_THREE_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_THREE_RO - SYSBYPASS_SOC_CTRL_THREE_RO */
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT)) & SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_BBUD_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_BBUD_CTRL_ONE_RO_REG_SYSBYPASS_BBUD_CTRL_FOUR_RO_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_BBUD_CTRL_ONE_RO_REG_SYSBYPASS_BBUD_CTRL_FOUR_RO_SHIFT (0U)
+/*! SYSBYPASS_BBUD_CTRL_FOUR_RO - SYSBYPASS_BBUD_CTRL_FOUR_RO */
+#define SYSPLL_T3_SYSBYPASS_BBUD_CTRL_ONE_RO_REG_SYSBYPASS_BBUD_CTRL_FOUR_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_BBUD_CTRL_ONE_RO_REG_SYSBYPASS_BBUD_CTRL_FOUR_RO_SHIFT)) & SYSPLL_T3_SYSBYPASS_BBUD_CTRL_ONE_RO_REG_SYSBYPASS_BBUD_CTRL_FOUR_RO_MASK)
+/*! @} */
+
+/*! @name REG_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_REG_RO_REG_REG_RO_MASK         (0xFFU)
+#define SYSPLL_T3_REG_RO_REG_REG_RO_SHIFT        (0U)
+/*! REG_RO - REG_RO */
+#define SYSPLL_T3_REG_RO_REG_REG_RO(x)           (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_REG_RO_REG_REG_RO_SHIFT)) & SYSPLL_T3_REG_RO_REG_REG_RO_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYS_CTRL_REG_SYS_CTRL_MASK     (0xFFU)
+#define SYSPLL_T3_SYS_CTRL_REG_SYS_CTRL_SHIFT    (0U)
+/*! SYS_CTRL - SYS_CTRL */
+#define SYSPLL_T3_SYS_CTRL_REG_SYS_CTRL(x)       (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYS_CTRL_REG_SYS_CTRL_SHIFT)) & SYSPLL_T3_SYS_CTRL_REG_SYS_CTRL_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_ONE_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_ONE_RW - SYSBYPASS_SOC_CTRL_ONE_RW */
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT)) & SYSPLL_T3_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_TWO_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_TWO_RW - SYSBYPASS_SOC_CTRL_TWO_RW */
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT)) & SYSPLL_T3_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_THREE_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_THREE_RW - SYSBYPASS_SOC_CTRL_THREE_RW */
+#define SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT)) & SYSPLL_T3_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_BBUD_CTRL_FOUR_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_SYSBYPASS_BBUD_CTRL_FOUR_RW_REG_SYSBYPASS_BBUD_CTRL_FOUR_RW_MASK (0xFFU)
+#define SYSPLL_T3_SYSBYPASS_BBUD_CTRL_FOUR_RW_REG_SYSBYPASS_BBUD_CTRL_FOUR_RW_SHIFT (0U)
+/*! SYSBYPASS_BBUD_CTRL_FOUR_RW - SYSBYPASS_BBUD_CTRL_FOUR_RW */
+#define SYSPLL_T3_SYSBYPASS_BBUD_CTRL_FOUR_RW_REG_SYSBYPASS_BBUD_CTRL_FOUR_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_SYSBYPASS_BBUD_CTRL_FOUR_RW_REG_SYSBYPASS_BBUD_CTRL_FOUR_RW_SHIFT)) & SYSPLL_T3_SYSBYPASS_BBUD_CTRL_FOUR_RW_REG_SYSBYPASS_BBUD_CTRL_FOUR_RW_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_ONE_REG_T3_CTRL_ONE_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_ONE_REG_T3_CTRL_ONE_SHIFT (0U)
+/*! T3_CTRL_ONE - T3_CTRL_ONE */
+#define SYSPLL_T3_T3_CTRL_ONE_REG_T3_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_ONE_REG_T3_CTRL_ONE_SHIFT)) & SYSPLL_T3_T3_CTRL_ONE_REG_T3_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_TWO_REG_T3_CTRL_TWO_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_TWO_REG_T3_CTRL_TWO_SHIFT (0U)
+/*! T3_CTRL_TWO - T3_CTRL_TWO */
+#define SYSPLL_T3_T3_CTRL_TWO_REG_T3_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_TWO_REG_T3_CTRL_TWO_SHIFT)) & SYSPLL_T3_T3_CTRL_TWO_REG_T3_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_THREE_REG_T3_CTRL_THREE_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_THREE_REG_T3_CTRL_THREE_SHIFT (0U)
+/*! T3_CTRL_THREE - T3_CTRL_THREE */
+#define SYSPLL_T3_T3_CTRL_THREE_REG_T3_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_THREE_REG_T3_CTRL_THREE_SHIFT)) & SYSPLL_T3_T3_CTRL_THREE_REG_T3_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_FOUR_REG_T3_CTRL_FOUR_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_FOUR_REG_T3_CTRL_FOUR_SHIFT (0U)
+/*! T3_CTRL_FOUR - T3_CTRL_FOUR */
+#define SYSPLL_T3_T3_CTRL_FOUR_REG_T3_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_FOUR_REG_T3_CTRL_FOUR_SHIFT)) & SYSPLL_T3_T3_CTRL_FOUR_REG_T3_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_FIVE_REG_T3_CTRL_FIVE_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_FIVE_REG_T3_CTRL_FIVE_SHIFT (0U)
+/*! T3_CTRL_FIVE - T3_CTRL_FIVE */
+#define SYSPLL_T3_T3_CTRL_FIVE_REG_T3_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_FIVE_REG_T3_CTRL_FIVE_SHIFT)) & SYSPLL_T3_T3_CTRL_FIVE_REG_T3_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_SIX_REG_T3_CTRL_SIX_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_SIX_REG_T3_CTRL_SIX_SHIFT (0U)
+/*! T3_CTRL_SIX - T3_CTRL_SIX */
+#define SYSPLL_T3_T3_CTRL_SIX_REG_T3_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_SIX_REG_T3_CTRL_SIX_SHIFT)) & SYSPLL_T3_T3_CTRL_SIX_REG_T3_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_SEVEN_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_SEVEN_REG_T3_CTRL_SEVEN_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_SEVEN_REG_T3_CTRL_SEVEN_SHIFT (0U)
+/*! T3_CTRL_SEVEN - T3_CTRL_SEVEN */
+#define SYSPLL_T3_T3_CTRL_SEVEN_REG_T3_CTRL_SEVEN(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_SEVEN_REG_T3_CTRL_SEVEN_SHIFT)) & SYSPLL_T3_T3_CTRL_SEVEN_REG_T3_CTRL_SEVEN_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_EIGHT_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_EIGHT_REG_T3_CTRL_EIGHT_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_EIGHT_REG_T3_CTRL_EIGHT_SHIFT (0U)
+/*! T3_CTRL_EIGHT - T3_CTRL_EIGHT */
+#define SYSPLL_T3_T3_CTRL_EIGHT_REG_T3_CTRL_EIGHT(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_EIGHT_REG_T3_CTRL_EIGHT_SHIFT)) & SYSPLL_T3_T3_CTRL_EIGHT_REG_T3_CTRL_EIGHT_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_NINE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_NINE_REG_T3_CTRL_NINE_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_NINE_REG_T3_CTRL_NINE_SHIFT (0U)
+/*! T3_CTRL_NINE - T3_CTRL_NINE */
+#define SYSPLL_T3_T3_CTRL_NINE_REG_T3_CTRL_NINE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_NINE_REG_T3_CTRL_NINE_SHIFT)) & SYSPLL_T3_T3_CTRL_NINE_REG_T3_CTRL_NINE_MASK)
+/*! @} */
+
+/*! @name T3_CTRL_TEN_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_T3_CTRL_TEN_REG_T3_CTRL_TEN_MASK (0xFFU)
+#define SYSPLL_T3_T3_CTRL_TEN_REG_T3_CTRL_TEN_SHIFT (0U)
+/*! T3_CTRL_TEN - T3_CTRL_TEN */
+#define SYSPLL_T3_T3_CTRL_TEN_REG_T3_CTRL_TEN(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_T3_CTRL_TEN_REG_T3_CTRL_TEN_SHIFT)) & SYSPLL_T3_T3_CTRL_TEN_REG_T3_CTRL_TEN_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_MASK (0xFFU)
+#define SYSPLL_T3_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_SHIFT (0U)
+/*! CLKTREE_CTRL_ONE - CLKTREE_CTRL_ONE */
+#define SYSPLL_T3_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_SHIFT)) & SYSPLL_T3_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_MASK (0xFFU)
+#define SYSPLL_T3_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_SHIFT (0U)
+/*! CLKTREE_CTRL_TWO - CLKTREE_CTRL_TWO */
+#define SYSPLL_T3_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_SHIFT)) & SYSPLL_T3_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_CLKTREE_CTRL_THREE_REG_CLKTREE_CTRL_THREE_MASK (0xFFU)
+#define SYSPLL_T3_CLKTREE_CTRL_THREE_REG_CLKTREE_CTRL_THREE_SHIFT (0U)
+/*! CLKTREE_CTRL_THREE - CLKTREE_CTRL_THREE */
+#define SYSPLL_T3_CLKTREE_CTRL_THREE_REG_CLKTREE_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_CLKTREE_CTRL_THREE_REG_CLKTREE_CTRL_THREE_SHIFT)) & SYSPLL_T3_CLKTREE_CTRL_THREE_REG_CLKTREE_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_CLKTREE_CTRL_FOUR_REG_CLKTREE_CTRL_FOUR_MASK (0xFFU)
+#define SYSPLL_T3_CLKTREE_CTRL_FOUR_REG_CLKTREE_CTRL_FOUR_SHIFT (0U)
+/*! CLKTREE_CTRL_FOUR - CLKTREE_CTRL_FOUR */
+#define SYSPLL_T3_CLKTREE_CTRL_FOUR_REG_CLKTREE_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_CLKTREE_CTRL_FOUR_REG_CLKTREE_CTRL_FOUR_SHIFT)) & SYSPLL_T3_CLKTREE_CTRL_FOUR_REG_CLKTREE_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_CLKTREE_CTRL_FIVE_REG_CLKTREE_CTRL_FIVE_MASK (0xFFU)
+#define SYSPLL_T3_CLKTREE_CTRL_FIVE_REG_CLKTREE_CTRL_FIVE_SHIFT (0U)
+/*! CLKTREE_CTRL_FIVE - CLKTREE_CTRL_FIVE */
+#define SYSPLL_T3_CLKTREE_CTRL_FIVE_REG_CLKTREE_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_CLKTREE_CTRL_FIVE_REG_CLKTREE_CTRL_FIVE_SHIFT)) & SYSPLL_T3_CLKTREE_CTRL_FIVE_REG_CLKTREE_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_CLKTREE_CTRL_SIX_REG_CLKTREE_CTRL_SIX_MASK (0xFFU)
+#define SYSPLL_T3_CLKTREE_CTRL_SIX_REG_CLKTREE_CTRL_SIX_SHIFT (0U)
+/*! CLKTREE_CTRL_SIX - CLKTREE_CTRL_SIX */
+#define SYSPLL_T3_CLKTREE_CTRL_SIX_REG_CLKTREE_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_CLKTREE_CTRL_SIX_REG_CLKTREE_CTRL_SIX_SHIFT)) & SYSPLL_T3_CLKTREE_CTRL_SIX_REG_CLKTREE_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name GPIO_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_GPIO_CTRL_REG_GPIO_CTRL_MASK   (0xFFU)
+#define SYSPLL_T3_GPIO_CTRL_REG_GPIO_CTRL_SHIFT  (0U)
+/*! GPIO_CTRL - GPIO_CTRL */
+#define SYSPLL_T3_GPIO_CTRL_REG_GPIO_CTRL(x)     (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_GPIO_CTRL_REG_GPIO_CTRL_SHIFT)) & SYSPLL_T3_GPIO_CTRL_REG_GPIO_CTRL_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_ATEST_CTRL_REG_ATEST_CTRL_MASK (0xFFU)
+#define SYSPLL_T3_ATEST_CTRL_REG_ATEST_CTRL_SHIFT (0U)
+/*! ATEST_CTRL - ATEST_CTRL */
+#define SYSPLL_T3_ATEST_CTRL_REG_ATEST_CTRL(x)   (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_ATEST_CTRL_REG_ATEST_CTRL_SHIFT)) & SYSPLL_T3_ATEST_CTRL_REG_ATEST_CTRL_MASK)
+/*! @} */
+
+/*! @name RESERVED_LO_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_MASK (0xFFU)
+#define SYSPLL_T3_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_SHIFT (0U)
+/*! RESERVED_LO_ONE - RESERVED_LO_ONE */
+#define SYSPLL_T3_RESERVED_LO_ONE_REG_RESERVED_LO_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_SHIFT)) & SYSPLL_T3_RESERVED_LO_ONE_REG_RESERVED_LO_ONE_MASK)
+/*! @} */
+
+/*! @name RESERVED_HI_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_MASK (0xFFU)
+#define SYSPLL_T3_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_SHIFT (0U)
+/*! RESERVED_HI_ONE - RESERVED_HI_ONE */
+#define SYSPLL_T3_RESERVED_HI_ONE_REG_RESERVED_HI_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_SHIFT)) & SYSPLL_T3_RESERVED_HI_ONE_REG_RESERVED_HI_ONE_MASK)
+/*! @} */
+
+/*! @name RESERVED_MIX_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_RESERVED_MIX_ONE_REG_RESERVED_MIX_ONE_MASK (0xFFU)
+#define SYSPLL_T3_RESERVED_MIX_ONE_REG_RESERVED_MIX_ONE_SHIFT (0U)
+/*! RESERVED_MIX_ONE - RESERVED_MIX_ONE */
+#define SYSPLL_T3_RESERVED_MIX_ONE_REG_RESERVED_MIX_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_RESERVED_MIX_ONE_REG_RESERVED_MIX_ONE_SHIFT)) & SYSPLL_T3_RESERVED_MIX_ONE_REG_RESERVED_MIX_ONE_MASK)
+/*! @} */
+
+/*! @name RESERVED_MIX_TWO_REG -  */
+/*! @{ */
+
+#define SYSPLL_T3_RESERVED_MIX_TWO_REG_RESERVED_MIX_TWO_MASK (0xFFU)
+#define SYSPLL_T3_RESERVED_MIX_TWO_REG_RESERVED_MIX_TWO_SHIFT (0U)
+/*! RESERVED_MIX_TWO - RESERVED_MIX_TWO */
+#define SYSPLL_T3_RESERVED_MIX_TWO_REG_RESERVED_MIX_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_T3_RESERVED_MIX_TWO_REG_RESERVED_MIX_TWO_SHIFT)) & SYSPLL_T3_RESERVED_MIX_TWO_REG_RESERVED_MIX_TWO_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSPLL_T3_Register_Masks */
+
+
+/* SYSPLL_T3 - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SYSPLL_T3 base address */
+  #define SYSPLL_T3_BASE                           (0x55002000u)
+  /** Peripheral SYSPLL_T3 base address */
+  #define SYSPLL_T3_BASE_NS                        (0x45002000u)
+  /** Peripheral SYSPLL_T3 base pointer */
+  #define SYSPLL_T3                                ((SYSPLL_T3_Type *)SYSPLL_T3_BASE)
+  /** Peripheral SYSPLL_T3 base pointer */
+  #define SYSPLL_T3_NS                             ((SYSPLL_T3_Type *)SYSPLL_T3_BASE_NS)
+  /** Array initializer of SYSPLL_T3 peripheral base addresses */
+  #define SYSPLL_T3_BASE_ADDRS                     { SYSPLL_T3_BASE }
+  /** Array initializer of SYSPLL_T3 peripheral base pointers */
+  #define SYSPLL_T3_BASE_PTRS                      { SYSPLL_T3 }
+  /** Array initializer of SYSPLL_T3 peripheral base addresses */
+  #define SYSPLL_T3_BASE_ADDRS_NS                  { SYSPLL_T3_BASE_NS }
+  /** Array initializer of SYSPLL_T3 peripheral base pointers */
+  #define SYSPLL_T3_BASE_PTRS_NS                   { SYSPLL_T3_NS }
+#else
+  /** Peripheral SYSPLL_T3 base address */
+  #define SYSPLL_T3_BASE                           (0x45002000u)
+  /** Peripheral SYSPLL_T3 base pointer */
+  #define SYSPLL_T3                                ((SYSPLL_T3_Type *)SYSPLL_T3_BASE)
+  /** Array initializer of SYSPLL_T3 peripheral base addresses */
+  #define SYSPLL_T3_BASE_ADDRS                     { SYSPLL_T3_BASE }
+  /** Array initializer of SYSPLL_T3 peripheral base pointers */
+  #define SYSPLL_T3_BASE_PTRS                      { SYSPLL_T3 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSPLL_T3_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSPLL_TCPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSPLL_TCPU_Peripheral_Access_Layer SYSPLL_TCPU Peripheral Access Layer
+ * @{
+ */
+
+/** SYSPLL_TCPU - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[224];
+  __I  uint8_t SYSBYPASS_SOC_CTRL_ONE_RO_REG;      /**< offset: 0xE0 */
+  __I  uint8_t SYSBYPASS_SOC_CTRL_TWO_RO_REG;      /**< offset: 0xE1 */
+  __I  uint8_t SYSBYPASS_SOC_CTRL_THREE_RO_REG;    /**< offset: 0xE2 */
+  __I  uint8_t REG_RO_REG;                         /**< offset: 0xE3 */
+  __IO uint8_t SYS_CTRL_REG;                       /**< offset: 0xE4 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_ONE_RW_REG;      /**< offset: 0xE5 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_TWO_RW_REG;      /**< offset: 0xE6 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_THREE_RW_REG;    /**< offset: 0xE7 */
+  __IO uint8_t TCPU_CTRL_ONE_REG;                  /**< offset: 0xE8 */
+  __IO uint8_t TCPU_CTRL_TWO_REG;                  /**< offset: 0xE9 */
+  __IO uint8_t TCPU_CTRL_THREE_REG;                /**< offset: 0xEA */
+  __IO uint8_t TCPU_CTRL_FOUR_REG;                 /**< offset: 0xEB */
+  __IO uint8_t TCPU_CTRL_FIVE_REG;                 /**< offset: 0xEC */
+  __IO uint8_t TCPU_CTRL_SIX_REG;                  /**< offset: 0xED */
+  __IO uint8_t CLKTREE_CTRL_ONE_REG;               /**< offset: 0xEE */
+  __IO uint8_t CLKTREE_CTRL_TWO_REG;               /**< offset: 0xEF */
+  __IO uint8_t GPIO_CTRL_REG;                      /**< offset: 0xF0 */
+  __IO uint8_t ATEST_CTRL_REG;                     /**< offset: 0xF1 */
+  __IO uint8_t RESERVED_LO_REG;                    /**< offset: 0xF2 */
+  __IO uint8_t RESERVED_HI_REG;                    /**< offset: 0xF3 */
+} SYSPLL_TCPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSPLL_TCPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSPLL_TCPU_Register_Masks SYSPLL_TCPU Register Masks
+ * @{
+ */
+
+/*! @name SYSBYPASS_SOC_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK (0xFFU)
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_ONE_RO - SYSBYPASS_SOC_CTRL_ONE_RO */
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_TWO_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK (0xFFU)
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_TWO_RO - SYSBYPASS_SOC_CTRL_TWO_RO */
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_THREE_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK (0xFFU)
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_THREE_RO - SYSBYPASS_SOC_CTRL_THREE_RO */
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK)
+/*! @} */
+
+/*! @name REG_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_REG_RO_REG_REG_RO_MASK       (0xFFU)
+#define SYSPLL_TCPU_REG_RO_REG_REG_RO_SHIFT      (0U)
+/*! REG_RO - REG_RO */
+#define SYSPLL_TCPU_REG_RO_REG_REG_RO(x)         (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_REG_RO_REG_REG_RO_SHIFT)) & SYSPLL_TCPU_REG_RO_REG_REG_RO_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_MASK   (0xFFU)
+#define SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_SHIFT  (0U)
+/*! SYS_CTRL - SYS_CTRL */
+#define SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL(x)     (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_SHIFT)) & SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_ONE_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK (0xFFU)
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_ONE_RW - SYSBYPASS_SOC_CTRL_ONE_RW */
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_TWO_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK (0xFFU)
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_TWO_RW - SYSBYPASS_SOC_CTRL_TWO_RW */
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_THREE_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK (0xFFU)
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_THREE_RW - SYSBYPASS_SOC_CTRL_THREE_RW */
+#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK)
+/*! @} */
+
+/*! @name TCPU_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_MASK (0xFFU)
+#define SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_SHIFT (0U)
+/*! TCPU_CTRL_ONE - TCPU_CTRL_ONE */
+#define SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name TCPU_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_MASK (0xFFU)
+#define SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_SHIFT (0U)
+/*! TCPU_CTRL_TWO - TCPU_CTRL_TWO */
+#define SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name TCPU_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_MASK (0xFFU)
+#define SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_SHIFT (0U)
+/*! TCPU_CTRL_THREE - TCPU_CTRL_THREE */
+#define SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name TCPU_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_MASK (0xFFU)
+#define SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_SHIFT (0U)
+/*! TCPU_CTRL_FOUR - TCPU_CTRL_FOUR */
+#define SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name TCPU_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_MASK (0xFFU)
+#define SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_SHIFT (0U)
+/*! TCPU_CTRL_FIVE - TCPU_CTRL_FIVE */
+#define SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name TCPU_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_MASK (0xFFU)
+#define SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_SHIFT (0U)
+/*! TCPU_CTRL_SIX - TCPU_CTRL_SIX */
+#define SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_MASK (0xFFU)
+#define SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_SHIFT (0U)
+/*! CLKTREE_CTRL_ONE - CLKTREE_CTRL_ONE */
+#define SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_SHIFT)) & SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_MASK (0xFFU)
+#define SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_SHIFT (0U)
+/*! CLKTREE_CTRL_TWO - CLKTREE_CTRL_TWO */
+#define SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_SHIFT)) & SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name GPIO_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_MASK (0xFFU)
+#define SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_SHIFT (0U)
+/*! GPIO_CTRL - GPIO_CTRL */
+#define SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL(x)   (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_SHIFT)) & SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_MASK (0xFFU)
+#define SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_SHIFT (0U)
+/*! ATEST_CTRL - ATEST_CTRL */
+#define SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_SHIFT)) & SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_MASK)
+/*! @} */
+
+/*! @name RESERVED_LO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_MASK (0xFFU)
+#define SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_SHIFT (0U)
+/*! RESERVED_LO - RESERVED_LO */
+#define SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_SHIFT)) & SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_MASK)
+/*! @} */
+
+/*! @name RESERVED_HI_REG -  */
+/*! @{ */
+
+#define SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_MASK (0xFFU)
+#define SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_SHIFT (0U)
+/*! RESERVED_HI - RESERVED_HI */
+#define SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_SHIFT)) & SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSPLL_TCPU_Register_Masks */
+
+
+/* SYSPLL_TCPU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral SYSPLL_TCPU base address */
+  #define SYSPLL_TCPU_BASE                         (0x55002000u)
+  /** Peripheral SYSPLL_TCPU base address */
+  #define SYSPLL_TCPU_BASE_NS                      (0x45002000u)
+  /** Peripheral SYSPLL_TCPU base pointer */
+  #define SYSPLL_TCPU                              ((SYSPLL_TCPU_Type *)SYSPLL_TCPU_BASE)
+  /** Peripheral SYSPLL_TCPU base pointer */
+  #define SYSPLL_TCPU_NS                           ((SYSPLL_TCPU_Type *)SYSPLL_TCPU_BASE_NS)
+  /** Array initializer of SYSPLL_TCPU peripheral base addresses */
+  #define SYSPLL_TCPU_BASE_ADDRS                   { SYSPLL_TCPU_BASE }
+  /** Array initializer of SYSPLL_TCPU peripheral base pointers */
+  #define SYSPLL_TCPU_BASE_PTRS                    { SYSPLL_TCPU }
+  /** Array initializer of SYSPLL_TCPU peripheral base addresses */
+  #define SYSPLL_TCPU_BASE_ADDRS_NS                { SYSPLL_TCPU_BASE_NS }
+  /** Array initializer of SYSPLL_TCPU peripheral base pointers */
+  #define SYSPLL_TCPU_BASE_PTRS_NS                 { SYSPLL_TCPU_NS }
+#else
+  /** Peripheral SYSPLL_TCPU base address */
+  #define SYSPLL_TCPU_BASE                         (0x45002000u)
+  /** Peripheral SYSPLL_TCPU base pointer */
+  #define SYSPLL_TCPU                              ((SYSPLL_TCPU_Type *)SYSPLL_TCPU_BASE)
+  /** Array initializer of SYSPLL_TCPU peripheral base addresses */
+  #define SYSPLL_TCPU_BASE_ADDRS                   { SYSPLL_TCPU_BASE }
+  /** Array initializer of SYSPLL_TCPU peripheral base pointers */
+  #define SYSPLL_TCPU_BASE_PTRS                    { SYSPLL_TCPU }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSPLL_TCPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSPLL_TDDR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSPLL_TDDR_Peripheral_Access_Layer SYSPLL_TDDR Peripheral Access Layer
+ * @{
+ */
+
+/** SYSPLL_TDDR - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[160];
+  __I  uint8_t SYSBYPASS_SOC_CTRL_ONE_RO_REG;      /**< offset: 0xA0 */
+  __I  uint8_t SYSBYPASS_SOC_CTRL_TWO_RO_REG;      /**< offset: 0xA1 */
+  __I  uint8_t SYSBYPASS_SOC_CTRL_THREE_RO_REG;    /**< offset: 0xA2 */
+  __I  uint8_t REG_RO_REG;                         /**< offset: 0xA3 */
+  __IO uint8_t SYS_CTRL_REG;                       /**< offset: 0xA4 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_ONE_RW_REG;      /**< offset: 0xA5 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_TWO_RW_REG;      /**< offset: 0xA6 */
+  __IO uint8_t SYSBYPASS_SOC_CTRL_THREE_RW_REG;    /**< offset: 0xA7 */
+  __IO uint8_t TDDR_CTRL_ONE_REG;                  /**< offset: 0xA8 */
+  __IO uint8_t TDDR_CTRL_TWO_REG;                  /**< offset: 0xA9 */
+  __IO uint8_t TDDR_CTRL_THREE_REG;                /**< offset: 0xAA */
+  __IO uint8_t TDDR_CTRL_FOUR_REG;                 /**< offset: 0xAB */
+  __IO uint8_t TDDR_CTRL_FIVE_REG;                 /**< offset: 0xAC */
+  __IO uint8_t TDDR_CTRL_SIX_REG;                  /**< offset: 0xAD */
+  __IO uint8_t CLKTREE_CTRL_ONE_REG;               /**< offset: 0xAE */
+  __IO uint8_t CLKTREE_CTRL_TWO_REG;               /**< offset: 0xAF */
+  __IO uint8_t GPIO_CTRL_REG;                      /**< offset: 0xB0 */
+  __IO uint8_t ATEST_CTRL_REG;                     /**< offset: 0xB1 */
+  __IO uint8_t RESERVED_LO_REG;                    /**< offset: 0xB2 */
+  __IO uint8_t RESERVED_HI_REG;                    /**< offset: 0xB3 */
+} SYSPLL_TDDR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSPLL_TDDR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSPLL_TDDR_Register_Masks SYSPLL_TDDR Register Masks
+ * @{
+ */
+
+/*! @name SYSBYPASS_SOC_CTRL_ONE_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK (0xFFU)
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_ONE_RO - SYSBYPASS_SOC_CTRL_ONE_RO */
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT)) & SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_TWO_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK (0xFFU)
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_TWO_RO - SYSBYPASS_SOC_CTRL_TWO_RO */
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT)) & SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_THREE_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK (0xFFU)
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT (0U)
+/*! SYSBYPASS_SOC_CTRL_THREE_RO - SYSBYPASS_SOC_CTRL_THREE_RO */
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT)) & SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK)
+/*! @} */
+
+/*! @name REG_RO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_REG_RO_REG_REG_RO_MASK       (0xFFU)
+#define SYSPLL_TDDR_REG_RO_REG_REG_RO_SHIFT      (0U)
+/*! REG_RO - REG_RO */
+#define SYSPLL_TDDR_REG_RO_REG_REG_RO(x)         (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_REG_RO_REG_REG_RO_SHIFT)) & SYSPLL_TDDR_REG_RO_REG_REG_RO_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_SYS_CTRL_REG_REG_SYS_CTRL_MASK (0xFFU)
+#define SYSPLL_TDDR_SYS_CTRL_REG_REG_SYS_CTRL_SHIFT (0U)
+/*! REG_SYS_CTRL - REG_SYS_CTRL */
+#define SYSPLL_TDDR_SYS_CTRL_REG_REG_SYS_CTRL(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_SYS_CTRL_REG_REG_SYS_CTRL_SHIFT)) & SYSPLL_TDDR_SYS_CTRL_REG_REG_SYS_CTRL_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_ONE_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RW_REG_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK (0xFFU)
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RW_REG_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT (0U)
+/*! REG_SYSBYPASS_SOC_CTRL_ONE_RW - REG_SYSBYPASS_SOC_CTRL_ONE_RW */
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RW_REG_REG_SYSBYPASS_SOC_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RW_REG_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT)) & SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_ONE_RW_REG_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_TWO_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RW_REG_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK (0xFFU)
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RW_REG_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT (0U)
+/*! REG_SYSBYPASS_SOC_CTRL_TWO_RW - REG_SYSBYPASS_SOC_CTRL_TWO_RW */
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RW_REG_REG_SYSBYPASS_SOC_CTRL_TWO_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RW_REG_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT)) & SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_TWO_RW_REG_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK)
+/*! @} */
+
+/*! @name SYSBYPASS_SOC_CTRL_THREE_RW_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RW_REG_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK (0xFFU)
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RW_REG_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT (0U)
+/*! REG_SYSBYPASS_SOC_CTRL_THREE_RW - REG_SYSBYPASS_SOC_CTRL_THREE_RW */
+#define SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RW_REG_REG_SYSBYPASS_SOC_CTRL_THREE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RW_REG_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT)) & SYSPLL_TDDR_SYSBYPASS_SOC_CTRL_THREE_RW_REG_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK)
+/*! @} */
+
+/*! @name TDDR_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_TDDR_CTRL_ONE_REG_REG_TDDR_CTRL_ONE_MASK (0xFFU)
+#define SYSPLL_TDDR_TDDR_CTRL_ONE_REG_REG_TDDR_CTRL_ONE_SHIFT (0U)
+/*! REG_TDDR_CTRL_ONE - REG_TDDR_CTRL_ONE */
+#define SYSPLL_TDDR_TDDR_CTRL_ONE_REG_REG_TDDR_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_TDDR_CTRL_ONE_REG_REG_TDDR_CTRL_ONE_SHIFT)) & SYSPLL_TDDR_TDDR_CTRL_ONE_REG_REG_TDDR_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name TDDR_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_TDDR_CTRL_TWO_REG_REG_TDDR_CTRL_TWO_MASK (0xFFU)
+#define SYSPLL_TDDR_TDDR_CTRL_TWO_REG_REG_TDDR_CTRL_TWO_SHIFT (0U)
+/*! REG_TDDR_CTRL_TWO - REG_TDDR_CTRL_TWO */
+#define SYSPLL_TDDR_TDDR_CTRL_TWO_REG_REG_TDDR_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_TDDR_CTRL_TWO_REG_REG_TDDR_CTRL_TWO_SHIFT)) & SYSPLL_TDDR_TDDR_CTRL_TWO_REG_REG_TDDR_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name TDDR_CTRL_THREE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_TDDR_CTRL_THREE_REG_REG_TDDR_CTRL_THREE_MASK (0xFFU)
+#define SYSPLL_TDDR_TDDR_CTRL_THREE_REG_REG_TDDR_CTRL_THREE_SHIFT (0U)
+/*! REG_TDDR_CTRL_THREE - REG_TDDR_CTRL_THREE */
+#define SYSPLL_TDDR_TDDR_CTRL_THREE_REG_REG_TDDR_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_TDDR_CTRL_THREE_REG_REG_TDDR_CTRL_THREE_SHIFT)) & SYSPLL_TDDR_TDDR_CTRL_THREE_REG_REG_TDDR_CTRL_THREE_MASK)
+/*! @} */
+
+/*! @name TDDR_CTRL_FOUR_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_TDDR_CTRL_FOUR_REG_REG_TDDR_CTRL_FOUR_MASK (0xFFU)
+#define SYSPLL_TDDR_TDDR_CTRL_FOUR_REG_REG_TDDR_CTRL_FOUR_SHIFT (0U)
+/*! REG_TDDR_CTRL_FOUR - REG_TDDR_CTRL_FOUR */
+#define SYSPLL_TDDR_TDDR_CTRL_FOUR_REG_REG_TDDR_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_TDDR_CTRL_FOUR_REG_REG_TDDR_CTRL_FOUR_SHIFT)) & SYSPLL_TDDR_TDDR_CTRL_FOUR_REG_REG_TDDR_CTRL_FOUR_MASK)
+/*! @} */
+
+/*! @name TDDR_CTRL_FIVE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_TDDR_CTRL_FIVE_REG_REG_TDDR_CTRL_FIVE_MASK (0xFFU)
+#define SYSPLL_TDDR_TDDR_CTRL_FIVE_REG_REG_TDDR_CTRL_FIVE_SHIFT (0U)
+/*! REG_TDDR_CTRL_FIVE - REG_TDDR_CTRL_FIVE */
+#define SYSPLL_TDDR_TDDR_CTRL_FIVE_REG_REG_TDDR_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_TDDR_CTRL_FIVE_REG_REG_TDDR_CTRL_FIVE_SHIFT)) & SYSPLL_TDDR_TDDR_CTRL_FIVE_REG_REG_TDDR_CTRL_FIVE_MASK)
+/*! @} */
+
+/*! @name TDDR_CTRL_SIX_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_TDDR_CTRL_SIX_REG_REG_TDDR_CTRL_SIX_MASK (0xFFU)
+#define SYSPLL_TDDR_TDDR_CTRL_SIX_REG_REG_TDDR_CTRL_SIX_SHIFT (0U)
+/*! REG_TDDR_CTRL_SIX - REG_TDDR_CTRL_SIX */
+#define SYSPLL_TDDR_TDDR_CTRL_SIX_REG_REG_TDDR_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_TDDR_CTRL_SIX_REG_REG_TDDR_CTRL_SIX_SHIFT)) & SYSPLL_TDDR_TDDR_CTRL_SIX_REG_REG_TDDR_CTRL_SIX_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_ONE_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_CLKTREE_CTRL_ONE_REG_REG_CLKTREE_CTRL_ONE_MASK (0xFFU)
+#define SYSPLL_TDDR_CLKTREE_CTRL_ONE_REG_REG_CLKTREE_CTRL_ONE_SHIFT (0U)
+/*! REG_CLKTREE_CTRL_ONE - REG_CLKTREE_CTRL_ONE */
+#define SYSPLL_TDDR_CLKTREE_CTRL_ONE_REG_REG_CLKTREE_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_CLKTREE_CTRL_ONE_REG_REG_CLKTREE_CTRL_ONE_SHIFT)) & SYSPLL_TDDR_CLKTREE_CTRL_ONE_REG_REG_CLKTREE_CTRL_ONE_MASK)
+/*! @} */
+
+/*! @name CLKTREE_CTRL_TWO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_CLKTREE_CTRL_TWO_REG_REG_CLKTREE_CTRL_TWO_MASK (0xFFU)
+#define SYSPLL_TDDR_CLKTREE_CTRL_TWO_REG_REG_CLKTREE_CTRL_TWO_SHIFT (0U)
+/*! REG_CLKTREE_CTRL_TWO - REG_CLKTREE_CTRL_TWO */
+#define SYSPLL_TDDR_CLKTREE_CTRL_TWO_REG_REG_CLKTREE_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_CLKTREE_CTRL_TWO_REG_REG_CLKTREE_CTRL_TWO_SHIFT)) & SYSPLL_TDDR_CLKTREE_CTRL_TWO_REG_REG_CLKTREE_CTRL_TWO_MASK)
+/*! @} */
+
+/*! @name GPIO_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_GPIO_CTRL_REG_REG_GPIO_CTRL_MASK (0xFFU)
+#define SYSPLL_TDDR_GPIO_CTRL_REG_REG_GPIO_CTRL_SHIFT (0U)
+/*! REG_GPIO_CTRL - REG_GPIO_CTRL */
+#define SYSPLL_TDDR_GPIO_CTRL_REG_REG_GPIO_CTRL(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_GPIO_CTRL_REG_REG_GPIO_CTRL_SHIFT)) & SYSPLL_TDDR_GPIO_CTRL_REG_REG_GPIO_CTRL_MASK)
+/*! @} */
+
+/*! @name ATEST_CTRL_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_ATEST_CTRL_REG_REG_ATEST_CTRL_MASK (0xFFU)
+#define SYSPLL_TDDR_ATEST_CTRL_REG_REG_ATEST_CTRL_SHIFT (0U)
+/*! REG_ATEST_CTRL - REG_ATEST_CTRL */
+#define SYSPLL_TDDR_ATEST_CTRL_REG_REG_ATEST_CTRL(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_ATEST_CTRL_REG_REG_ATEST_CTRL_SHIFT)) & SYSPLL_TDDR_ATEST_CTRL_REG_REG_ATEST_CTRL_MASK)
+/*! @} */
+
+/*! @name RESERVED_LO_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_RESERVED_LO_REG_REG_RESERVED_LO_MASK (0xFFU)
+#define SYSPLL_TDDR_RESERVED_LO_REG_REG_RESERVED_LO_SHIFT (0U)
+/*! REG_RESERVED_LO - REG_RESERVED_LO */
+#define SYSPLL_TDDR_RESERVED_LO_REG_REG_RESERVED_LO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_RESERVED_LO_REG_REG_RESERVED_LO_SHIFT)) & SYSPLL_TDDR_RESERVED_LO_REG_REG_RESERVED_LO_MASK)
+/*! @} */
+
+/*! @name RESERVED_HI_REG -  */
+/*! @{ */
+
+#define SYSPLL_TDDR_RESERVED_HI_REG_REG_RESERVED_HI_MASK (0xFFU)
+#define SYSPLL_TDDR_RESERVED_HI_REG_REG_RESERVED_HI_SHIFT (0U)
+/*! REG_RESERVED_HI - REG_RESERVED_HI */
+#define SYSPLL_TDDR_RESERVED_HI_REG_REG_RESERVED_HI(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TDDR_RESERVED_HI_REG_REG_RESERVED_HI_SHIFT)) & SYSPLL_TDDR_RESERVED_HI_REG_REG_RESERVED_HI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSPLL_TDDR_Register_Masks */
+
+
+/* SYSPLL_TDDR - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral REG_SYSPLL_TDDR base address */
+  #define REG_SYSPLL_TDDR_BASE                     (0x55002000u)
+  /** Peripheral REG_SYSPLL_TDDR base address */
+  #define REG_SYSPLL_TDDR_BASE_NS                  (0x45002000u)
+  /** Peripheral REG_SYSPLL_TDDR base pointer */
+  #define REG_SYSPLL_TDDR                          ((SYSPLL_TDDR_Type *)REG_SYSPLL_TDDR_BASE)
+  /** Peripheral REG_SYSPLL_TDDR base pointer */
+  #define REG_SYSPLL_TDDR_NS                       ((SYSPLL_TDDR_Type *)REG_SYSPLL_TDDR_BASE_NS)
+  /** Array initializer of SYSPLL_TDDR peripheral base addresses */
+  #define SYSPLL_TDDR_BASE_ADDRS                   { REG_SYSPLL_TDDR_BASE }
+  /** Array initializer of SYSPLL_TDDR peripheral base pointers */
+  #define SYSPLL_TDDR_BASE_PTRS                    { REG_SYSPLL_TDDR }
+  /** Array initializer of SYSPLL_TDDR peripheral base addresses */
+  #define SYSPLL_TDDR_BASE_ADDRS_NS                { REG_SYSPLL_TDDR_BASE_NS }
+  /** Array initializer of SYSPLL_TDDR peripheral base pointers */
+  #define SYSPLL_TDDR_BASE_PTRS_NS                 { REG_SYSPLL_TDDR_NS }
+#else
+  /** Peripheral REG_SYSPLL_TDDR base address */
+  #define REG_SYSPLL_TDDR_BASE                     (0x45002000u)
+  /** Peripheral REG_SYSPLL_TDDR base pointer */
+  #define REG_SYSPLL_TDDR                          ((SYSPLL_TDDR_Type *)REG_SYSPLL_TDDR_BASE)
+  /** Array initializer of SYSPLL_TDDR peripheral base addresses */
+  #define SYSPLL_TDDR_BASE_ADDRS                   { REG_SYSPLL_TDDR_BASE }
+  /** Array initializer of SYSPLL_TDDR peripheral base pointers */
+  #define SYSPLL_TDDR_BASE_PTRS                    { REG_SYSPLL_TDDR }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSPLL_TDDR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
+ * @{
+ */
+
+/** TRNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCTL;                              /**< Miscellaneous Control Register, offset: 0x0 */
+  __IO uint32_t SCMISC;                            /**< Statistical Check Miscellaneous Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t SDCTL;                             /**< Seed Control Register, offset: 0x10 */
+  __I  uint32_t TOTSAM;                            /**< Total Samples Register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t FRQMIN;                            /**< Frequency Count Minimum Limit Register, offset: 0x18 */
+    __I  uint32_t OSC2_FRQCNT;                       /**< Oscillator-2 Frequency Count Register, offset: 0x18 */
+  };
+  union {                                          /* offset: 0x1C */
+    __I  uint32_t FRQCNT;                            /**< Frequency Count Register, offset: 0x1C */
+    __IO uint32_t FRQMAX;                            /**< Frequency Count Maximum Limit Register, offset: 0x1C */
+  };
+  union {                                          /* offset: 0x20 */
+    __I  uint32_t SCMC;                              /**< Statistical Check Monobit Count Register, offset: 0x20 */
+    __IO uint32_t SCML;                              /**< Statistical Check Monobit Limit Register, offset: 0x20 */
+  };
+  union {                                          /* offset: 0x24 */
+    __I  uint32_t SCR1C;                             /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
+    __IO uint32_t SCR1L;                             /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
+  };
+  union {                                          /* offset: 0x28 */
+    __I  uint32_t SCR2C;                             /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
+    __IO uint32_t SCR2L;                             /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
+  };
+  union {                                          /* offset: 0x2C */
+    __I  uint32_t SCR3C;                             /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
+    __IO uint32_t SCR3L;                             /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
+  };
+       uint8_t RESERVED_1[12];
+  __I  uint32_t STATUS;                            /**< Status Register, offset: 0x3C */
+  __I  uint32_t ENT[8];                            /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[64];
+  __IO uint32_t SEC_CFG;                           /**< Security Configuration Register, offset: 0xA0 */
+  __IO uint32_t INT_CTRL;                          /**< Interrupt Control Register, offset: 0xA4 */
+  __IO uint32_t INT_MASK;                          /**< Mask Register, offset: 0xA8 */
+  __I  uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0xAC */
+       uint8_t RESERVED_3[60];
+  __IO uint32_t OSC2_CTL;                          /**< RNG Oscillator 2 Control Register, offset: 0xEC */
+  __I  uint32_t VID1;                              /**< Version ID Register (MS), offset: 0xF0 */
+  __I  uint32_t VID2;                              /**< Version ID Register (LS), offset: 0xF4 */
+} TRNG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Register_Masks TRNG Register Masks
+ * @{
+ */
+
+/*! @name MCTL - Miscellaneous Control Register */
+/*! @{ */
+
+#define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
+#define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
+/*! OSC_DIV
+ *  0b00..use ring oscillator with no divide
+ *  0b01..use ring oscillator divided-by-2
+ *  0b10..use ring oscillator divided-by-4
+ *  0b11..use ring oscillator divided-by-8
+ */
+#define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
+
+#define TRNG_MCTL_UNUSED4_MASK                   (0x10U)
+#define TRNG_MCTL_UNUSED4_SHIFT                  (4U)
+#define TRNG_MCTL_UNUSED4(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
+
+#define TRNG_MCTL_UNUSED5_MASK                   (0x20U)
+#define TRNG_MCTL_UNUSED5_SHIFT                  (5U)
+#define TRNG_MCTL_UNUSED5(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
+
+#define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
+#define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
+#define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
+
+#define TRNG_MCTL_FOR_SCLK_MASK                  (0x80U)
+#define TRNG_MCTL_FOR_SCLK_SHIFT                 (7U)
+#define TRNG_MCTL_FOR_SCLK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
+
+#define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
+#define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
+#define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
+
+#define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
+#define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
+#define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
+
+#define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
+#define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
+#define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
+
+#define TRNG_MCTL_TST_OUT_MASK                   (0x800U)
+#define TRNG_MCTL_TST_OUT_SHIFT                  (11U)
+#define TRNG_MCTL_TST_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
+
+#define TRNG_MCTL_ERR_MASK                       (0x1000U)
+#define TRNG_MCTL_ERR_SHIFT                      (12U)
+#define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
+
+#define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
+#define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
+#define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
+
+#define TRNG_MCTL_LRUN_CONT_MASK                 (0x4000U)
+#define TRNG_MCTL_LRUN_CONT_SHIFT                (14U)
+#define TRNG_MCTL_LRUN_CONT(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
+
+#define TRNG_MCTL_OSC2_FAIL_MASK                 (0x8000U)
+#define TRNG_MCTL_OSC2_FAIL_SHIFT                (15U)
+/*! OSC2_FAIL - Oscillator 2 Failure */
+#define TRNG_MCTL_OSC2_FAIL(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC2_FAIL_SHIFT)) & TRNG_MCTL_OSC2_FAIL_MASK)
+
+#define TRNG_MCTL_PRGM_MASK                      (0x10000U)
+#define TRNG_MCTL_PRGM_SHIFT                     (16U)
+#define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
+/*! @} */
+
+/*! @name SCMISC - Statistical Check Miscellaneous Register */
+/*! @{ */
+
+#define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
+#define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
+#define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
+
+#define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
+#define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
+#define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
+/*! @} */
+
+/*! @name SDCTL - Seed Control Register */
+/*! @{ */
+
+#define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
+#define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
+#define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
+
+#define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
+#define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
+#define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
+/*! @} */
+
+/*! @name TOTSAM - Total Samples Register */
+/*! @{ */
+
+#define TRNG_TOTSAM_TOT_SAM_MASK                 (0xFFFFFU)
+#define TRNG_TOTSAM_TOT_SAM_SHIFT                (0U)
+#define TRNG_TOTSAM_TOT_SAM(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
+/*! @} */
+
+/*! @name FRQMIN - Frequency Count Minimum Limit Register */
+/*! @{ */
+
+#define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
+#define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
+/*! @} */
+
+/*! @name OSC2_FRQCNT - Oscillator-2 Frequency Count Register */
+/*! @{ */
+
+#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK        (0x3FFFFFU)
+#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT       (0U)
+#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT(x)          (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT)) & TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK)
+/*! @} */
+
+/*! @name FRQCNT - Frequency Count Register */
+/*! @{ */
+
+#define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
+#define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
+#define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
+/*! @} */
+
+/*! @name FRQMAX - Frequency Count Maximum Limit Register */
+/*! @{ */
+
+#define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
+#define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
+/*! @} */
+
+/*! @name SCMC - Statistical Check Monobit Count Register */
+/*! @{ */
+
+#define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
+#define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
+#define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
+/*! @} */
+
+/*! @name SCML - Statistical Check Monobit Limit Register */
+/*! @{ */
+
+#define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
+#define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
+#define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
+
+#define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
+#define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
+#define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
+/*! @} */
+
+/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
+/*! @{ */
+
+#define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
+#define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
+#define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
+
+#define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
+#define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
+#define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
+/*! @{ */
+
+#define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
+#define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
+#define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
+
+#define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
+#define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
+#define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
+/*! @} */
+
+/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
+/*! @{ */
+
+#define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
+#define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
+#define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
+
+#define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
+#define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
+#define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
+/*! @{ */
+
+#define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
+#define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
+#define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
+
+#define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
+#define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
+#define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
+/*! @} */
+
+/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
+/*! @{ */
+
+#define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
+#define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
+#define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
+
+#define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
+#define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
+#define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
+/*! @{ */
+
+#define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
+#define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
+#define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
+
+#define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
+#define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
+#define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+
+#define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
+#define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
+#define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
+
+#define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
+#define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
+#define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
+
+#define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
+#define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
+#define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
+
+#define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
+#define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
+#define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
+
+#define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
+#define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
+#define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
+
+#define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
+#define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
+#define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
+
+#define TRNG_STATUS_TFLR_MASK                    (0x2000U)
+#define TRNG_STATUS_TFLR_SHIFT                   (13U)
+#define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
+
+#define TRNG_STATUS_TFMB_MASK                    (0x8000U)
+#define TRNG_STATUS_TFMB_SHIFT                   (15U)
+#define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
+
+#define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
+#define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
+#define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
+/*! @} */
+
+/*! @name ENT - Entropy Read Register */
+/*! @{ */
+
+#define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
+#define TRNG_ENT_ENT_SHIFT                       (0U)
+#define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
+/*! @} */
+
+/* The count of TRNG_ENT */
+#define TRNG_ENT_COUNT                           (8U)
+
+/*! @name SEC_CFG - Security Configuration Register */
+/*! @{ */
+
+#define TRNG_SEC_CFG_UNUSED0_MASK                (0x1U)
+#define TRNG_SEC_CFG_UNUSED0_SHIFT               (0U)
+#define TRNG_SEC_CFG_UNUSED0(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
+
+#define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
+#define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
+/*! NO_PRGM
+ *  0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
+ *  0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
+ */
+#define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
+
+#define TRNG_SEC_CFG_UNUSED2_MASK                (0x4U)
+#define TRNG_SEC_CFG_UNUSED2_SHIFT               (2U)
+#define TRNG_SEC_CFG_UNUSED2(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
+/*! @} */
+
+/*! @name INT_CTRL - Interrupt Control Register */
+/*! @{ */
+
+#define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding bit of INT_STATUS register cleared.
+ *  0b1..Corresponding bit of INT_STATUS register active.
+ */
+#define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
+
+#define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
+
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
+
+#define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
+#define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
+#define TRNG_INT_CTRL_UNUSED(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
+/*! @} */
+
+/*! @name INT_MASK - Mask Register */
+/*! @{ */
+
+#define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding interrupt of INT_STATUS is masked.
+ *  0b1..Corresponding bit of INT_STATUS is active.
+ */
+#define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
+
+#define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
+
+#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status Register */
+/*! @{ */
+
+#define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
+#define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
+/*! HW_ERR
+ *  0b0..no error
+ *  0b1..error detected.
+ */
+#define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
+
+#define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
+#define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
+/*! ENT_VAL
+ *  0b0..Busy generation entropy. Any value read is invalid.
+ *  0b1..TRNG can be stopped and entropy is valid if read.
+ */
+#define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
+
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..No hardware nor self test frequency errors.
+ *  0b1..The frequency counter has detected a failure.
+ */
+#define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name OSC2_CTL - RNG Oscillator 2 Control Register */
+/*! @{ */
+
+#define TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK          (0x3U)
+#define TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT         (0U)
+/*! TRNG_ENT_CTL - TRNG entropy generation control. */
+#define TRNG_OSC2_CTL_TRNG_ENT_CTL(x)            (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT)) & TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK)
+
+#define TRNG_OSC2_CTL_OSC2_DIV_MASK              (0xCU)
+#define TRNG_OSC2_CTL_OSC2_DIV_SHIFT             (2U)
+/*! OSC2_DIV - Oscillator 2 divide control */
+#define TRNG_OSC2_CTL_OSC2_DIV(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_DIV_SHIFT)) & TRNG_OSC2_CTL_OSC2_DIV_MASK)
+
+#define TRNG_OSC2_CTL_OSC2_OUT_EN_MASK           (0x10U)
+#define TRNG_OSC2_CTL_OSC2_OUT_EN_SHIFT          (4U)
+/*! OSC2_OUT_EN - Oscillator 2 Output Enable. */
+#define TRNG_OSC2_CTL_OSC2_OUT_EN(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_OUT_EN_SHIFT)) & TRNG_OSC2_CTL_OSC2_OUT_EN_MASK)
+
+#define TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK          (0x200U)
+#define TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT         (9U)
+/*! OSC2_FCT_VAL - TRNG Oscillator 2 Frequency Count Valid */
+#define TRNG_OSC2_CTL_OSC2_FCT_VAL(x)            (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT)) & TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK)
+
+#define TRNG_OSC2_CTL_OSC2_TST_OUT_MASK          (0x800U)
+#define TRNG_OSC2_CTL_OSC2_TST_OUT_SHIFT         (11U)
+/*! OSC2_TST_OUT - Test point inside ring oscillator 2. */
+#define TRNG_OSC2_CTL_OSC2_TST_OUT(x)            (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_TST_OUT_SHIFT)) & TRNG_OSC2_CTL_OSC2_TST_OUT_MASK)
+
+#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK      (0x3000U)
+#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT     (12U)
+/*! OSC_FAILSAFE_LMT - Test point inside ring oscillator 2. */
+#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT(x)        (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK)
+
+#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK     (0x4000U)
+#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT    (14U)
+/*! OSC_FAILSAFE_TEST - Test point inside ring oscillator 2. */
+#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST(x)       (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK)
+/*! @} */
+
+/*! @name VID1 - Version ID Register (MS) */
+/*! @{ */
+
+#define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
+#define TRNG_VID1_MIN_REV_SHIFT                  (0U)
+/*! MIN_REV
+ *  0b00000100..Minor revision number for TRNG.
+ */
+#define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
+
+#define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
+#define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
+/*! MAJ_REV
+ *  0b00010100..Major revision number for TRNG.
+ */
+#define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
+
+#define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
+#define TRNG_VID1_IP_ID_SHIFT                    (16U)
+/*! IP_ID
+ *  0b0000000000110000..ID for TRNG.
+ */
+#define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
+/*! @} */
+
+/*! @name VID2 - Version ID Register (LS) */
+/*! @{ */
+
+#define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
+#define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
+/*! CONFIG_OPT
+ *  0b00000000..TRNG_CONFIG_OPT for TRNG.
+ */
+#define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
+
+#define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
+#define TRNG_VID2_ECO_REV_SHIFT                  (8U)
+/*! ECO_REV
+ *  0b00000001..TRNG_ECO_REV for TRNG.
+ */
+#define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
+
+#define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
+#define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
+/*! INTG_OPT
+ *  0b00001010..INTG_OPT for TRNG.
+ */
+#define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
+
+#define TRNG_VID2_ERA_MASK                       (0xFF000000U)
+#define TRNG_VID2_ERA_SHIFT                      (24U)
+/*! ERA
+ *  0b00001011..COMPILE_OPT for TRNG.
+ */
+#define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Register_Masks */
+
+
+/* TRNG - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral TRNG base address */
+  #define TRNG_BASE                                (0x50014000u)
+  /** Peripheral TRNG base address */
+  #define TRNG_BASE_NS                             (0x40014000u)
+  /** Peripheral TRNG base pointer */
+  #define TRNG                                     ((TRNG_Type *)TRNG_BASE)
+  /** Peripheral TRNG base pointer */
+  #define TRNG_NS                                  ((TRNG_Type *)TRNG_BASE_NS)
+  /** Array initializer of TRNG peripheral base addresses */
+  #define TRNG_BASE_ADDRS                          { TRNG_BASE }
+  /** Array initializer of TRNG peripheral base pointers */
+  #define TRNG_BASE_PTRS                           { TRNG }
+  /** Array initializer of TRNG peripheral base addresses */
+  #define TRNG_BASE_ADDRS_NS                       { TRNG_BASE_NS }
+  /** Array initializer of TRNG peripheral base pointers */
+  #define TRNG_BASE_PTRS_NS                        { TRNG_NS }
+#else
+  /** Peripheral TRNG base address */
+  #define TRNG_BASE                                (0x40014000u)
+  /** Peripheral TRNG base pointer */
+  #define TRNG                                     ((TRNG_Type *)TRNG_BASE)
+  /** Array initializer of TRNG peripheral base addresses */
+  #define TRNG_BASE_ADDRS                          { TRNG_BASE }
+  /** Array initializer of TRNG peripheral base pointers */
+  #define TRNG_BASE_PTRS                           { TRNG }
+#endif
+
+/*!
+ * @}
+ */ /* end of group TRNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CFG;                               /**< USART Configuration, offset: 0x0 */
+  __IO uint32_t CTL;                               /**< USART Control, offset: 0x4 */
+  __IO uint32_t STAT;                              /**< USART Status, offset: 0x8 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Read and Set for USART (not FIFO) Status, offset: 0xC */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear, offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t BRG;                               /**< Baud Rate Generator, offset: 0x20 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status, offset: 0x24 */
+  __IO uint32_t OSR;                               /**< Oversample Selection Register for Asynchronous Communication, offset: 0x28 */
+  __IO uint32_t ADDR;                              /**< Address Register for Automatic Address Matching, offset: 0x2C */
+       uint8_t RESERVED_1[3536];
+  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration, offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO Status, offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Settings for Interrupt and DMA Request, offset: 0xE08 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable, offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear, offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status, offset: 0xE18 */
+       uint8_t RESERVED_3[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO Write Data, offset: 0xE20 */
+       uint8_t RESERVED_4[12];
+  __I  uint32_t FIFORD;                            /**< FIFO Read Data, offset: 0xE30 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
+       uint8_t RESERVED_6[4];
+  __I  uint32_t FIFOSIZE;                          /**< FIFO Size, offset: 0xE48 */
+  struct {                                         /* offset: 0xE4C */
+    __IO uint32_t FIFORXTIMEOUTCFG;                  /**< FIFO Receive Timeout Configuration, offset: 0xE4C */
+    __I  uint32_t FIFORXTIMEOUTCNT;                  /**< FIFO Receive Timeout Counter, offset: 0xE50 */
+  } FIFO_USART;
+       uint8_t RESERVED_7[424];
+  __I  uint32_t ID;                                /**< Peripheral Identification, offset: 0xFFC */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration */
+/*! @{ */
+
+#define USART_CFG_ENABLE_MASK                    (0x1U)
+#define USART_CFG_ENABLE_SHIFT                   (0U)
+/*! ENABLE - USART Enable
+ *  0b0..Disabled
+ *  0b1..Enabled. The USART is enabled for operation.
+ */
+#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+
+#define USART_CFG_DATALEN_MASK                   (0xCU)
+#define USART_CFG_DATALEN_SHIFT                  (2U)
+/*! DATALEN - Data Length. Selects the data size for the USART.
+ *  0b00..7 bit data length
+ *  0b01..8 bit data length
+ *  0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET[CTL].
+ *  0b11..Reserved
+ */
+#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+
+#define USART_CFG_PARITYSEL_MASK                 (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT                (4U)
+/*! PARITYSEL - Parity Select. Selects what type of parity is used by the USART.
+ *  0b00..No parity
+ *  0b01..Reserved
+ *  0b10..Even parity
+ *  0b11..Odd parity
+ */
+#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+
+#define USART_CFG_STOPLEN_MASK                   (0x40U)
+#define USART_CFG_STOPLEN_SHIFT                  (6U)
+/*! STOPLEN - Stop Length
+ *  0b0..1 stop bit
+ *  0b1..2 stop bits. This setting should be used only for asynchronous communication.
+ */
+#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+
+#define USART_CFG_MODE32K_MASK                   (0x80U)
+#define USART_CFG_MODE32K_SHIFT                  (7U)
+/*! MODE32K - Mode 32 kHz
+ *  0b0..Disabled. USART uses standard clocking.
+ *  0b1..Enabled
+ */
+#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+
+#define USART_CFG_LINMODE_MASK                   (0x100U)
+#define USART_CFG_LINMODE_SHIFT                  (8U)
+/*! LINMODE - LIN Break Mode Enable
+ *  0b0..Disabled. Break detect and generate is configured for normal operation.
+ *  0b1..Enabled. Break detect and generate is configured for LIN bus operation.
+ */
+#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+
+#define USART_CFG_CTSEN_MASK                     (0x200U)
+#define USART_CFG_CTSEN_SHIFT                    (9U)
+/*! CTSEN - CTS Enable
+ *  0b0..No flow control. The transmitter does not receive any automatic flow control signal.
+ *  0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
+ */
+#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+
+#define USART_CFG_SYNCEN_MASK                    (0x800U)
+#define USART_CFG_SYNCEN_SHIFT                   (11U)
+/*! SYNCEN - Synchronous Enable. Selects synchronous or asynchronous operation.
+ *  0b0..Asynchronous mode
+ *  0b1..Synchronous mode
+ */
+#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+
+#define USART_CFG_CLKPOL_MASK                    (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT                   (12U)
+/*! CLKPOL - Clock Polarity
+ *  0b0..Falling edge. RXD is sampled on the falling edge of SCLK.
+ *  0b1..Rising edge. RXD is sampled on the rising edge of SCLK.
+ */
+#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+
+#define USART_CFG_SYNCMST_MASK                   (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT                  (14U)
+/*! SYNCMST - Synchronous mode Master Select
+ *  0b0..Slave. When synchronous mode is enabled, the USART is a slave.
+ *  0b1..Master. When synchronous mode is enabled, the USART is a master.
+ */
+#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+
+#define USART_CFG_LOOP_MASK                      (0x8000U)
+#define USART_CFG_LOOP_SHIFT                     (15U)
+/*! LOOP - Loopback Mode
+ *  0b0..Normal operation
+ *  0b1..Loopback mode
+ */
+#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+
+#define USART_CFG_OETA_MASK                      (0x40000U)
+#define USART_CFG_OETA_SHIFT                     (18U)
+/*! OETA - Output Enable Turnaround Time Enable for RS-485 Operation.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+
+#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT                 (19U)
+/*! AUTOADDR - Automatic Address Matching Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+
+#define USART_CFG_OESEL_MASK                     (0x100000U)
+#define USART_CFG_OESEL_SHIFT                    (20U)
+/*! OESEL - Output Enable Select
+ *  0b0..Standard. The RTS signal is used as the standard flow control function.
+ *  0b1..RS-485. The RTS signal is configured to provide an output enable signal to control an RS-485 transceiver.
+ */
+#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+
+#define USART_CFG_OEPOL_MASK                     (0x200000U)
+#define USART_CFG_OEPOL_SHIFT                    (21U)
+/*! OEPOL - Output Enable Polarity
+ *  0b0..Low. If selected by OESEL, the output enable is active low.
+ *  0b1..High. If selected by OESEL, the output enable is active high.
+ */
+#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+
+#define USART_CFG_RXPOL_MASK                     (0x400000U)
+#define USART_CFG_RXPOL_SHIFT                    (22U)
+/*! RXPOL - Receive Data Polarity
+ *  0b0..Standard
+ *  0b1..Inverted
+ */
+#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+
+#define USART_CFG_TXPOL_MASK                     (0x800000U)
+#define USART_CFG_TXPOL_SHIFT                    (23U)
+/*! TXPOL - Transmit data polarity
+ *  0b0..Standard
+ *  0b1..Inverted
+ */
+#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+/*! @} */
+
+/*! @name CTL - USART Control */
+/*! @{ */
+
+#define USART_CTL_TXBRKEN_MASK                   (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT                  (1U)
+/*! TXBRKEN - Break Enable
+ *  0b0..Normal operation
+ *  0b1..Continuous break
+ */
+#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+
+#define USART_CTL_ADDRDET_MASK                   (0x4U)
+#define USART_CTL_ADDRDET_SHIFT                  (2U)
+/*! ADDRDET - Enable Address Detect Mode
+ *  0b0..Disabled. The USART presents all incoming data.
+ *  0b1..Enabled
+ */
+#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+
+#define USART_CTL_TXDIS_MASK                     (0x40U)
+#define USART_CTL_TXDIS_SHIFT                    (6U)
+/*! TXDIS - Transmit Disable
+ *  0b0..Not disabled. USART transmitter is not disabled.
+ *  0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
+ *       feature can be used to facilitate software flow control.
+ */
+#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+
+#define USART_CTL_CC_MASK                        (0x100U)
+#define USART_CTL_CC_SHIFT                       (8U)
+/*! CC - Continuous Clock Generation
+ *  0b0..Clock on character
+ *  0b1..Continuous clock
+ */
+#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+
+#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT                (9U)
+/*! CLRCCONRX - Clear Continuous Clock
+ *  0b0..No effect. No effect on the CC bit.
+ *  0b1..Auto-clear
+ */
+#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+
+#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
+/*! AUTOBAUD - Autobaud Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+/*! @} */
+
+/*! @name STAT - USART Status */
+/*! @{ */
+
+#define USART_STAT_RXIDLE_MASK                   (0x2U)
+#define USART_STAT_RXIDLE_SHIFT                  (1U)
+/*! RXIDLE - Receiver Idle
+ *  0b0..The receiver is currently receiving data.
+ *  0b1..The receiver is not currently receiving data.
+ */
+#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+
+#define USART_STAT_TXIDLE_MASK                   (0x8U)
+#define USART_STAT_TXIDLE_SHIFT                  (3U)
+/*! TXIDLE - Transmitter Idle
+ *  0b0..The transmitter is currently sending data.
+ *  0b1..The transmitter is not currently sending data.
+ */
+#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+
+#define USART_STAT_CTS_MASK                      (0x10U)
+#define USART_STAT_CTS_SHIFT                     (4U)
+/*! CTS - CTS value */
+#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+
+#define USART_STAT_DELTACTS_MASK                 (0x20U)
+#define USART_STAT_DELTACTS_SHIFT                (5U)
+/*! DELTACTS - Delta CTS */
+#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+
+#define USART_STAT_TXDISSTAT_MASK                (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT               (6U)
+/*! TXDISSTAT - Transmitter Disabled Status Flag
+ *  0b0..Not Idle. Indicates that the USART transmitter is NOT fully idle after being disabled.
+ *  0b1..Idle. Indicates that the USART transmitter is fully idle after being disabled (CTL[TXDIS] = 1).
+ */
+#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+
+#define USART_STAT_RXBRK_MASK                    (0x400U)
+#define USART_STAT_RXBRK_SHIFT                   (10U)
+/*! RXBRK - Received Break */
+#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+
+#define USART_STAT_DELTARXBRK_MASK               (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT              (11U)
+/*! DELTARXBRK - Delta Received Break */
+#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+
+#define USART_STAT_START_MASK                    (0x1000U)
+#define USART_STAT_START_SHIFT                   (12U)
+/*! START - Start */
+#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+
+#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT              (13U)
+/*! FRAMERRINT - Framing Error Interrupt Flag */
+#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+
+#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT            (14U)
+/*! PARITYERRINT - Parity Error Interrupt Flag */
+#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+
+#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT              (15U)
+/*! RXNOISEINT - Received Noise Interrupt Flag */
+#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+
+#define USART_STAT_ABERR_MASK                    (0x10000U)
+#define USART_STAT_ABERR_SHIFT                   (16U)
+/*! ABERR - Auto Baud Error */
+#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Read and Set for USART (not FIFO) Status */
+/*! @{ */
+
+#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
+/*! TXIDLEEN - Transmit Idle Flag
+ *  0b1..Enables an interrupt when the transmitter becomes idle (STAT[TXIDLE] = 1).
+ */
+#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+
+#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
+/*! DELTACTSEN - Delta CTS Input Flag
+ *  0b1..Enables an interrupt when there is a change in the state of the CTS input.
+ */
+#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+
+#define USART_INTENSET_TXDISEN_MASK              (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT             (6U)
+/*! TXDISEN - Transmit Disabled Flag
+ *  0b1..Enables an interrupt when the transmitter is fully disabled as indicated by the STAT[TXDISINT] flag. See
+ *       the description of the STAT[TXDISINT] flag.
+ */
+#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+
+#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
+/*! DELTARXBRKEN - Delta Receive Break Enable
+ *  0b1..Enable
+ */
+#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+
+#define USART_INTENSET_STARTEN_MASK              (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT             (12U)
+/*! STARTEN - Start Enable
+ *  0b1..Enables an interrupt when a received start bit has been detected.
+ */
+#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+
+#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
+/*! FRAMERREN - Frame Error Enable
+ *  0b1..Enables an interrupt when a framing error has been detected.
+ */
+#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+
+#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
+/*! PARITYERREN - Parity Error Enble
+ *  0b1..Enables an interrupt when a parity error has been detected.
+ */
+#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+
+#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
+/*! RXNOISEEN - Receive Noise Enable
+ *  0b1..Enables an interrupt when noise is detected. See the description of the CTL[RXNOISEINT] bit.
+ */
+#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+
+#define USART_INTENSET_ABERREN_MASK              (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT             (16U)
+/*! ABERREN - Auto Baud Error Enable
+ *  0b1..Enables an interrupt when an auto baud error occurs.
+ */
+#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear */
+/*! @{ */
+
+#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
+/*! TXIDLECLR - Transmit Idle Clear */
+#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+
+#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
+/*! DELTACTSCLR - Delta CTS Clear */
+#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+
+#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
+/*! TXDISCLR - Transmit Disable Clear */
+#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+
+#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
+/*! DELTARXBRKCLR - Delta Receive Break Clear */
+#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+
+#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
+/*! STARTCLR - Start Clear */
+#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+
+#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
+/*! FRAMERRCLR - Frame Error Clear */
+#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+
+#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
+/*! PARITYERRCLR - Parity Error Clear */
+#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+
+#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
+/*! RXNOISECLR - Receive Noise Clear */
+#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+
+#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
+/*! ABERRCLR - Auto Baud Error Clear */
+#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+/*! @} */
+
+/*! @name BRG - Baud Rate Generator */
+/*! @{ */
+
+#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT                   (0U)
+/*! BRGVAL - Baud Rate Generator Value
+ *  0b0000000000000000..FCLK is used directly by the USART function.
+ *  0b0000000000000001..FCLK is divided by 2 before use by the USART function.
+ *  0b0000000000000010..FCLK is divided by 3 before use by the USART function.
+ *  0b1111111111111111..FCLK is divided by 65,536 before use by the USART function.
+ */
+#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status */
+/*! @{ */
+
+#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
+/*! TXIDLE - Transmitter Idle Flag */
+#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+
+#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
+/*! DELTACTS - Delta CTS Change Flag */
+#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+
+#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
+/*! TXDISINT - Transmitter Disabled Interrupt Flag */
+#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+
+#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
+/*! DELTARXBRK - Delta Receiver Break Change Flag */
+#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+
+#define USART_INTSTAT_START_MASK                 (0x1000U)
+#define USART_INTSTAT_START_SHIFT                (12U)
+/*! START - Start Detected on Receiver Flag */
+#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+
+#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
+/*! FRAMERRINT - Framing Error Interrupt Flag */
+#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+
+#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
+/*! PARITYERRINT - Parity Error Interrupt Flag */
+#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+
+#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
+/*! RXNOISEINT - Received Noise Interrupt Flag */
+#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+
+#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
+/*! ABERRINT - Auto Baud Error Interrupt Flag */
+#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+/*! @} */
+
+/*! @name OSR - Oversample Selection Register for Asynchronous Communication */
+/*! @{ */
+
+#define USART_OSR_OSRVAL_MASK                    (0xFU)
+#define USART_OSR_OSRVAL_SHIFT                   (0U)
+/*! OSRVAL - Oversample Selection Value
+ *  0b0000..Not supported
+ *  0b0001..Not supported
+ *  0b0010..Not supported
+ *  0b0011..Not supported
+ *  0b0100..5 function clocks are used to transmit and receive each data bit.
+ *  0b0101..6 function clocks are used to transmit and receive each data bit.
+ *  0b1111..16 function clocks are used to transmit and receive each data bit.
+ */
+#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+/*! @} */
+
+/*! @name ADDR - Address Register for Automatic Address Matching */
+/*! @{ */
+
+#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT                 (0U)
+/*! ADDRESS - Address */
+#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO Configuration */
+/*! @{ */
+
+#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
+/*! ENABLETX - Enable the Transmit FIFO.
+ *  0b0..The transmit FIFO is not enabled.
+ *  0b1..The transmit FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+
+#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
+/*! ENABLERX - Enable the Receive FIFO
+ *  0b0..The receive FIFO is not enabled.
+ *  0b1..The receive FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+
+#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
+/*! SIZE - FIFO Size Configuration
+ *  0b00..FIFO is configured as 16 entries of 8 bits.
+ *  0b01..Not used
+ *  0b10..Not used
+ *  0b11..Not used
+ */
+#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+
+#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT                (12U)
+/*! DMATX - DMA Configuration for Transmit
+ *  0b0..DMA is not used for the transmit function.
+ *  0b1..Triggers DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+
+#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT                (13U)
+/*! DMARX - DMA Configuration for Receive
+ *  0b0..DMA is not used for the receive function.
+ *  0b1..Triggers DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+
+#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
+/*! WAKETX - Wake-up for Transmit FIFO Level
+ *  0b0..Only enabled interrupts will wake up the device from low power modes.
+ *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by
+ *       FIFOTRIG[TXLVL], even when the TXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+
+#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
+/*! WAKERX - Wake-up for Receive FIFO Level
+ *  0b0..Only enabled interrupts will wake up the device from low power modes.
+ *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
+ *       FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+
+#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
+/*! EMPTYTX - Empty Command for the Transmit FIFO
+ *  0b0..No effect
+ *  0b1..The TX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+
+#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
+/*! EMPTYRX - Empty Command for the Receive FIFO
+ *  0b0..No effect
+ *  0b1..The RX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+
+#define USART_FIFOCFG_POPDBG_MASK                (0x40000U)
+#define USART_FIFOCFG_POPDBG_SHIFT               (18U)
+/*! POPDBG - Pop FIFO for Debug Reads
+ *  0b0..Debug reads of the FIFO do not pop the FIFO.
+ *  0b1..A debug read will cause the FIFO to pop.
+ */
+#define USART_FIFOCFG_POPDBG(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO Status */
+/*! @{ */
+
+#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
+/*! TXERR - TX FIFO Error
+ *  0b0..A transmit FIFO error has not occurred.
+ *  0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
+ *       FIFO, or by an underflow if the FIFO is empty when data is needed.
+ */
+#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+
+#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
+/*! RXERR - RX FIFO Error
+ *  0b0..A receive FIFO overflow has not occurred
+ *  0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
+ */
+#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+
+#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
+/*! PERINT - Peripheral Interrupt
+ *  0b0..No Peripheral Interrupt
+ *  0b1..Peripheral Interrupt
+ */
+#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+
+#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
+/*! TXEMPTY - Transmit FIFO Empty
+ *  0b0..The transmit FIFO is not empty.
+ *  0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
+ */
+#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+
+#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
+/*! TXNOTFULL - Transmit FIFO is Not Full
+ *  0b0..The transmit FIFO is full and another write would cause it to overflow.
+ *  0b1..The transmit FIFO is not full, so more data can be written.
+ */
+#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
+/*! RXNOTEMPTY - Receive FIFO is Not Empty
+ *  0b0..The receive FIFO is empty.
+ *  0b1..The receive FIFO is not empty, so data can be read.
+ */
+#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+
+#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
+/*! RXFULL - Receive FIFO is Full
+ *  0b0..The receive FIFO is not full.
+ *  0b1..The receive FIFO is full.
+ */
+#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+
+#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
+/*! TXLVL - Transmit FIFO Current Level */
+#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+
+#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
+/*! RXLVL - Receive FIFO Current Level */
+#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+
+#define USART_FIFOSTAT_RXTIMEOUT_MASK            (0x1000000U)
+#define USART_FIFOSTAT_RXTIMEOUT_SHIFT           (24U)
+/*! RXTIMEOUT - Receive FIFO Timeout
+ *  0b0..RX FIFO on
+ *  0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register.
+ */
+#define USART_FIFOSTAT_RXTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOSTAT_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO Trigger Settings for Interrupt and DMA Request */
+/*! @{ */
+
+#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
+/*! TXLVLENA - Transmit FIFO Level Trigger Enable.
+ *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ *  0b1..A trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field.
+ */
+#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+
+#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
+/*! RXLVLENA - Receive FIFO Level Trigger Enable
+ *  0b0..Receive FIFO level does not generate a FIFO level trigger.
+ *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field.
+ */
+#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+
+#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
+/*! TXLVL - Transmit FIFO Level Trigger Point
+ *  0b0000..Trigger when the TX FIFO becomes empty
+ *  0b0001..Trigger when the TX FIFO level decreases to 1 entry
+ *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
+ */
+#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+
+#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
+/*! RXLVL - Receive FIFO Level Trigger Point
+ *  0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
+ *  0b0001..Trigger when the RX FIFO has received 2 entries
+ *  0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
+ */
+#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO Interrupt Enable */
+/*! @{ */
+
+#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
+/*! TXERR - Transmit Error Interrupt Enable
+ *  0b0..No interrupt will be generated for a transmit error.
+ *  0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+
+#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ *  0b0..No interrupt will be generated for a receive error.
+ *  0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+
+#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ *  0b0..No interrupt will be generated based on the TX FIFO level.
+ *  0b1..If FIFOTRIG[TXLVLENA] = 1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
+ */
+#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+
+#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ *  0b0..No interrupt will be generated based on the RX FIFO level.
+ *  0b1..If FIFOTRIG[RXLVLENA] = 1, an interrupt will be generated when the when the RX FIFO level increases to
+ *       the level specified by FIFOTRIG[RXLVL].
+ */
+#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+
+#define USART_FIFOINTENSET_RXTIMEOUT_MASK        (0x1000000U)
+#define USART_FIFOINTENSET_RXTIMEOUT_SHIFT       (24U)
+/*! RXTIMEOUT - Receive Timeout
+ *  0b0..No RX interrupt will be generated.
+ *  0b1..Asserts RX interrupt if RX FIFO Timeout event occurs.
+ */
+#define USART_FIFOINTENSET_RXTIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXTIMEOUT_SHIFT)) & USART_FIFOINTENSET_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear */
+/*! @{ */
+
+#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
+/*! TXERR - Transmit Error Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+
+#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+
+#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+
+#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ *  0b0..No effect
+ *  0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+
+#define USART_FIFOINTENCLR_RXTIMEOUT_MASK        (0x1000000U)
+#define USART_FIFOINTENCLR_RXTIMEOUT_SHIFT       (24U)
+/*! RXTIMEOUT - Receive Timeout
+ *  0b0..No effect
+ *  0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_RXTIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & USART_FIFOINTENCLR_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO Interrupt Status */
+/*! @{ */
+
+#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
+/*! TXERR - TX FIFO Error Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+
+#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
+/*! RXERR - RX FIFO Error Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+
+#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+
+#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+
+#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
+/*! PERINT - Peripheral Interrupt Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+
+#define USART_FIFOINTSTAT_RXTIMEOUT_MASK         (0x1000000U)
+#define USART_FIFOINTSTAT_RXTIMEOUT_SHIFT        (24U)
+/*! RXTIMEOUT - Receive Timeout Status
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define USART_FIFOINTSTAT_RXTIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOINTSTAT_RXTIMEOUT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO Write Data */
+/*! @{ */
+
+#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT                (0U)
+/*! TXDATA - Transmit data to the FIFO */
+#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO Read Data */
+/*! @{ */
+
+#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT                (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+
+#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT               (13U)
+/*! FRAMERR - Framing Error Status Flag */
+#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+
+#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT             (14U)
+/*! PARITYERR - Parity Error Status Flag */
+#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+
+#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT               (15U)
+/*! RXNOISE - Received Noise Flag */
+#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
+/*! @{ */
+
+#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
+/*! RXDATA - Received Data from the FIFO */
+#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+
+#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
+/*! FRAMERR - Framing Error Status Flag */
+#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+
+#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
+/*! PARITYERR - Parity Error Status Flag */
+#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+
+#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
+/*! RXNOISE - Received Noise Flag */
+#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+/*! @} */
+
+/*! @name FIFOSIZE - FIFO Size */
+/*! @{ */
+
+#define USART_FIFOSIZE_FIFOSIZE_MASK             (0x1FU)
+#define USART_FIFOSIZE_FIFOSIZE_SHIFT            (0U)
+/*! FIFOSIZE - FIFO Size */
+#define USART_FIFOSIZE_FIFOSIZE(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK)
+/*! @} */
+
+/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */
+/*! @{ */
+
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU)
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U)
+/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler */
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK)
+
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U)
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U)
+/*! RXTIMEOUT_VALUE - Receive Timeout Value */
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK)
+
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U)
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U)
+/*! RXTIMEOUT_EN - Receive Timeout Enable
+ *  0b0..Disable RX FIFO timeout
+ *  0b1..Enable RX FIFO timeout
+ */
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x)   (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK)
+
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U)
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U)
+/*! RXTIMEOUT_COW - Receive Timeout Continue On Write
+ *  0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO.
+ *  0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO.
+ */
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x)  (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK)
+
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U)
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U)
+/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty
+ *  0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty.
+ *  0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty.
+ */
+#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x)  (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK)
+/*! @} */
+
+/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */
+/*! @{ */
+
+#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU)
+#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U)
+/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value */
+#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x)  (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral Identification */
+/*! @{ */
+
+#define USART_ID_APERTURE_MASK                   (0xFFU)
+#define USART_ID_APERTURE_SHIFT                  (0U)
+/*! APERTURE - Aperture */
+#define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+
+#define USART_ID_MINOR_REV_MASK                  (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT                 (8U)
+/*! MINOR_REV - Minor revision of module implementation */
+#define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+
+#define USART_ID_MAJOR_REV_MASK                  (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT                 (12U)
+/*! MAJOR_REV - Major revision of module implementation */
+#define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+
+#define USART_ID_ID_MASK                         (0xFFFF0000U)
+#define USART_ID_ID_SHIFT                        (16U)
+/*! ID - Module identifier for the selected function */
+#define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral USART0 base address */
+  #define USART0_BASE                              (0x50106000u)
+  /** Peripheral USART0 base address */
+  #define USART0_BASE_NS                           (0x40106000u)
+  /** Peripheral USART0 base pointer */
+  #define USART0                                   ((USART_Type *)USART0_BASE)
+  /** Peripheral USART0 base pointer */
+  #define USART0_NS                                ((USART_Type *)USART0_BASE_NS)
+  /** Peripheral USART1 base address */
+  #define USART1_BASE                              (0x50107000u)
+  /** Peripheral USART1 base address */
+  #define USART1_BASE_NS                           (0x40107000u)
+  /** Peripheral USART1 base pointer */
+  #define USART1                                   ((USART_Type *)USART1_BASE)
+  /** Peripheral USART1 base pointer */
+  #define USART1_NS                                ((USART_Type *)USART1_BASE_NS)
+  /** Peripheral USART2 base address */
+  #define USART2_BASE                              (0x50108000u)
+  /** Peripheral USART2 base address */
+  #define USART2_BASE_NS                           (0x40108000u)
+  /** Peripheral USART2 base pointer */
+  #define USART2                                   ((USART_Type *)USART2_BASE)
+  /** Peripheral USART2 base pointer */
+  #define USART2_NS                                ((USART_Type *)USART2_BASE_NS)
+  /** Peripheral USART3 base address */
+  #define USART3_BASE                              (0x50109000u)
+  /** Peripheral USART3 base address */
+  #define USART3_BASE_NS                           (0x40109000u)
+  /** Peripheral USART3 base pointer */
+  #define USART3                                   ((USART_Type *)USART3_BASE)
+  /** Peripheral USART3 base pointer */
+  #define USART3_NS                                ((USART_Type *)USART3_BASE_NS)
+  /** Peripheral USART14 base address */
+  #define USART14_BASE                             (0x50126000u)
+  /** Peripheral USART14 base address */
+  #define USART14_BASE_NS                          (0x40126000u)
+  /** Peripheral USART14 base pointer */
+  #define USART14                                  ((USART_Type *)USART14_BASE)
+  /** Peripheral USART14 base pointer */
+  #define USART14_NS                               ((USART_Type *)USART14_BASE_NS)
+  /** Array initializer of USART peripheral base addresses */
+  #define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART14_BASE }
+  /** Array initializer of USART peripheral base pointers */
+  #define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART14 }
+  /** Array initializer of USART peripheral base addresses */
+  #define USART_BASE_ADDRS_NS                      { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART14_BASE_NS }
+  /** Array initializer of USART peripheral base pointers */
+  #define USART_BASE_PTRS_NS                       { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART14_NS }
+#else
+  /** Peripheral USART0 base address */
+  #define USART0_BASE                              (0x40106000u)
+  /** Peripheral USART0 base pointer */
+  #define USART0                                   ((USART_Type *)USART0_BASE)
+  /** Peripheral USART1 base address */
+  #define USART1_BASE                              (0x40107000u)
+  /** Peripheral USART1 base pointer */
+  #define USART1                                   ((USART_Type *)USART1_BASE)
+  /** Peripheral USART2 base address */
+  #define USART2_BASE                              (0x40108000u)
+  /** Peripheral USART2 base pointer */
+  #define USART2                                   ((USART_Type *)USART2_BASE)
+  /** Peripheral USART3 base address */
+  #define USART3_BASE                              (0x40109000u)
+  /** Peripheral USART3 base pointer */
+  #define USART3                                   ((USART_Type *)USART3_BASE)
+  /** Peripheral USART14 base address */
+  #define USART14_BASE                             (0x40126000u)
+  /** Peripheral USART14 base pointer */
+  #define USART14                                  ((USART_Type *)USART14_BASE)
+  /** Array initializer of USART peripheral base addresses */
+  #define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART14_BASE }
+  /** Array initializer of USART peripheral base pointers */
+  #define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART14 }
+#endif
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM14_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBC_Peripheral_Access_Layer USBC Peripheral Access Layer
+ * @{
+ */
+
+/** USBC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ID;                                /**< ID, offset: 0x0 */
+  __I  uint32_t HWGENERAL;                         /**< HWGENERAL, offset: 0x4 */
+  __I  uint32_t HWHOST;                            /**< HWHOST, offset: 0x8 */
+  __I  uint32_t HWDEVICE;                          /**< HWDEVICE, offset: 0xC */
+  __I  uint32_t HWTXBUF;                           /**< HWTXBUF, offset: 0x10 */
+  __I  uint32_t HWRXBUF;                           /**< HWRXBUF, offset: 0x14 */
+  __IO uint32_t HWTXBUF0;                          /**< HWTXBUF0, offset: 0x18 */
+  __IO uint32_t HWTXBUF1;                          /**< HWTXBUF1, offset: 0x1C */
+       uint8_t RESERVED_0[96];
+  __IO uint32_t GPTIMER0LD;                        /**< GPTIMER0LD, offset: 0x80 */
+  __IO uint32_t GPTIMER0CTRL;                      /**< GPTIMER0CTRL, offset: 0x84 */
+  __IO uint32_t GPTIMER1LD;                        /**< GPTIMER1LD, offset: 0x88 */
+  __IO uint32_t GPTIMER1CTRL;                      /**< GPTIMER1CTRL, offset: 0x8C */
+  __IO uint32_t SBUSCFG;                           /**< SBUSCFG, offset: 0x90 */
+       uint8_t RESERVED_1[108];
+  __I  uint32_t CAPLENGTH;                         /**< CAPLENGTH, offset: 0x100 */
+  __I  uint32_t HCSPARAMS;                         /**< HCSPARAMS, offset: 0x104 */
+  __I  uint32_t HCCPARAMS;                         /**< HCCPARAMS, offset: 0x108 */
+       uint8_t RESERVED_2[20];
+  __I  uint32_t DCIVERSION;                        /**< DCIVERSION, offset: 0x120 */
+  __I  uint32_t DCCPARAMS;                         /**< DCCPARAMS, offset: 0x124 */
+  __IO uint32_t DEVLPMCSR;                         /**< DevLPMCSR, offset: 0x128 */
+       uint8_t RESERVED_3[20];
+  __IO uint32_t USBCMD;                            /**< USBCMD, offset: 0x140 */
+  __IO uint32_t USBSTS;                            /**< USBSTS, offset: 0x144 */
+  __IO uint32_t USBINTR;                           /**< USBINTR, offset: 0x148 */
+  __IO uint32_t FRINDEX;                           /**< FRINDEX, offset: 0x14C */
+       uint8_t RESERVED_4[4];
+  union {                                          /* offset: 0x154 */
+    __IO uint32_t DEVICEADDR;                        /**< DEVICEADDR, offset: 0x154 */
+    __IO uint32_t PERIODICLISTBASE;                  /**< PERIODICLISTBASE, offset: 0x154 */
+  };
+  union {                                          /* offset: 0x158 */
+    __IO uint32_t ASYNCLISTADDR;                     /**< ASYNCLISTADDR, offset: 0x158 */
+    __IO uint32_t ENDPOINTLISTADDR;                  /**< ENDPOINTLISTADDR, offset: 0x158 */
+  };
+  __IO uint32_t TTCTRL;                            /**< TTCTRL, offset: 0x15C */
+  __IO uint32_t BURSTSIZE;                         /**< BURSTSIZE, offset: 0x160 */
+  __IO uint32_t TXFILLTUNING;                      /**< TXFILLTUNING, offset: 0x164 */
+  __IO uint32_t TXTTFILLTUNING;                    /**< TXTTFILLTUNING, offset: 0x168 */
+  __IO uint32_t IC_USB;                            /**< IC_USB, offset: 0x16C */
+  __I  uint32_t ULPI_VIEWPORT;                     /**< ULPI_VIEWPORT, offset: 0x170 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t ENDPTNAK;                          /**< ENDPTNAK, offset: 0x178 */
+  __IO uint32_t ENDPTNAKEN;                        /**< ENDPTNAKEN, offset: 0x17C */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t PORTSC1;                           /**< PORTSC1, offset: 0x184 */
+  __IO uint32_t PORTSC2;                           /**< PORTSC2, offset: 0x188 */
+  __IO uint32_t PORTSC3;                           /**< PORTSC3, offset: 0x18C */
+  __IO uint32_t PORTSC4;                           /**< PORTSC4, offset: 0x190 */
+  __IO uint32_t PORTSC5;                           /**< PORTSC5, offset: 0x194 */
+  __IO uint32_t PORTSC6;                           /**< PORTSC6, offset: 0x198 */
+  __IO uint32_t PORTSC7;                           /**< PORTSC7, offset: 0x19C */
+  __IO uint32_t PORTSC8;                           /**< PORTSC8, offset: 0x1A0 */
+  __IO uint32_t OTGSC;                             /**< OTGSC, offset: 0x1A4 */
+  __IO uint32_t USBMODE;                           /**< USBMODE, offset: 0x1A8 */
+  __IO uint32_t ENDPTSETUPSTAT;                    /**< ENDPTSETUPSTAT, offset: 0x1AC */
+  __IO uint32_t ENDPTPRIME;                        /**< ENDPTPRIME, offset: 0x1B0 */
+  __IO uint32_t ENDPTFLUSH;                        /**< ENDPTFLUSH, offset: 0x1B4 */
+  __I  uint32_t ENDPTSTAT;                         /**< ENDPTSTAT, offset: 0x1B8 */
+  __IO uint32_t ENDPTCOMPLETE;                     /**< ENDPTCOMPLETE, offset: 0x1BC */
+  __IO uint32_t ENDPTCTRL0;                        /**< ENDPTCTRL0, offset: 0x1C0 */
+  __IO uint32_t ENDPTCTRL[15];                     /**< ENDPTCTRL1..ENDPTCTRL15, array offset: 0x1C4, array step: 0x4 */
+  __IO uint32_t PLL_CONTROL_0;                     /**< PLL_Control_0, offset: 0x200 */
+  __IO uint32_t PLL_CONTROL_1;                     /**< PLL_Control_1, offset: 0x204 */
+  __IO uint32_t CALIBRATION_CONTROL;               /**< CALIBRATION_Control, offset: 0x208 */
+  __IO uint32_t TX_CHANNEL_CONTRL_0;               /**< Tx_Channel_Contrl_0, offset: 0x20C */
+  __I  uint32_t TX_CHANNEL_CONTRL_1;               /**< Tx_Channel_Contrl_1, offset: 0x210 */
+  __IO uint32_t RX_CHANNEL_CONTRL_0;               /**< Rx_Channel_Contrl_0, offset: 0x214 */
+  __IO uint32_t RX_CHANNEL_CONTRL_1;               /**< Rx_Channel_Contrl_1, offset: 0x218 */
+  __IO uint32_t DIGITAL_CONTRL_0;                  /**< Digital_Contrl_0, offset: 0x21C */
+  __IO uint32_t DIGITAL_CONTRL_1;                  /**< Digital_Contrl_1, offset: 0x220 */
+  __IO uint32_t TEST_CONTRL_AND_STATUS_0;          /**< Test_Contrl_and_Status_0, offset: 0x224 */
+  __IO uint32_t TEST_CONTRL_AND_STATUS_1;          /**< Test_Contrl_and_Status_1, offset: 0x228 */
+  __IO uint32_t MONITOR;                           /**< MONITOR, offset: 0x22C */
+  __IO uint32_t RESERVE_ANA;                       /**< PHY_RESERVE, offset: 0x230 */
+  __IO uint32_t PHY_REG_OTG_CONTROL;               /**< PHY_REG_OTG_CONTROL, offset: 0x234 */
+  __IO uint32_t PHY_REG_CHGDTC_CONTRL_1;           /**< PHY_REG_CHGDTC_CONTRL_1, offset: 0x238 */
+       uint8_t RESERVED_7[16];
+  __I  uint32_t RESERVED;                          /**< RESERVED, offset: 0x24C */
+} USBC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBC_Register_Masks USBC Register Masks
+ * @{
+ */
+
+/*! @name ID - ID */
+/*! @{ */
+
+#define USBC_ID_ID_MASK                          (0x3FU)
+#define USBC_ID_ID_SHIFT                         (0U)
+/*! ID - ID */
+#define USBC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << USBC_ID_ID_SHIFT)) & USBC_ID_ID_MASK)
+
+#define USBC_ID_UNUSED_6_MASK                    (0xC0U)
+#define USBC_ID_UNUSED_6_SHIFT                   (6U)
+/*! UNUSED_6 - UNUSED_6 */
+#define USBC_ID_UNUSED_6(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_ID_UNUSED_6_SHIFT)) & USBC_ID_UNUSED_6_MASK)
+
+#define USBC_ID_NID_MASK                         (0x3F00U)
+#define USBC_ID_NID_SHIFT                        (8U)
+/*! NID - NID */
+#define USBC_ID_NID(x)                           (((uint32_t)(((uint32_t)(x)) << USBC_ID_NID_SHIFT)) & USBC_ID_NID_MASK)
+
+#define USBC_ID_UNUSED_14_MASK                   (0xC000U)
+#define USBC_ID_UNUSED_14_SHIFT                  (14U)
+/*! UNUSED_14 - UNUSED_14 */
+#define USBC_ID_UNUSED_14(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_ID_UNUSED_14_SHIFT)) & USBC_ID_UNUSED_14_MASK)
+
+#define USBC_ID_TAG_MASK                         (0x1F0000U)
+#define USBC_ID_TAG_SHIFT                        (16U)
+/*! TAG - TAG */
+#define USBC_ID_TAG(x)                           (((uint32_t)(((uint32_t)(x)) << USBC_ID_TAG_SHIFT)) & USBC_ID_TAG_MASK)
+
+#define USBC_ID_REVISION_MASK                    (0x1E00000U)
+#define USBC_ID_REVISION_SHIFT                   (21U)
+/*! REVISION - REVISION */
+#define USBC_ID_REVISION(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_ID_REVISION_SHIFT)) & USBC_ID_REVISION_MASK)
+
+#define USBC_ID_VERSION_MASK                     (0x1E000000U)
+#define USBC_ID_VERSION_SHIFT                    (25U)
+/*! VERSION - VERSION */
+#define USBC_ID_VERSION(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_ID_VERSION_SHIFT)) & USBC_ID_VERSION_MASK)
+
+#define USBC_ID_CIVERSION_MASK                   (0xE0000000U)
+#define USBC_ID_CIVERSION_SHIFT                  (29U)
+/*! CIVERSION - CIVERSION */
+#define USBC_ID_CIVERSION(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_ID_CIVERSION_SHIFT)) & USBC_ID_CIVERSION_MASK)
+/*! @} */
+
+/*! @name HWGENERAL - HWGENERAL */
+/*! @{ */
+
+#define USBC_HWGENERAL_RT_MASK                   (0x1U)
+#define USBC_HWGENERAL_RT_SHIFT                  (0U)
+/*! RT - RT */
+#define USBC_HWGENERAL_RT(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_RT_SHIFT)) & USBC_HWGENERAL_RT_MASK)
+
+#define USBC_HWGENERAL_CLKC_MASK                 (0x6U)
+#define USBC_HWGENERAL_CLKC_SHIFT                (1U)
+/*! CLKC - CLKC */
+#define USBC_HWGENERAL_CLKC(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_CLKC_SHIFT)) & USBC_HWGENERAL_CLKC_MASK)
+
+#define USBC_HWGENERAL_BWT_MASK                  (0x8U)
+#define USBC_HWGENERAL_BWT_SHIFT                 (3U)
+/*! BWT - BWT */
+#define USBC_HWGENERAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_BWT_SHIFT)) & USBC_HWGENERAL_BWT_MASK)
+
+#define USBC_HWGENERAL_PHYW_MASK                 (0x30U)
+#define USBC_HWGENERAL_PHYW_SHIFT                (4U)
+/*! PHYW - PHYW */
+#define USBC_HWGENERAL_PHYW(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_PHYW_SHIFT)) & USBC_HWGENERAL_PHYW_MASK)
+
+#define USBC_HWGENERAL_PHYM_MASK                 (0x3C0U)
+#define USBC_HWGENERAL_PHYM_SHIFT                (6U)
+/*! PHYM - PHYM */
+#define USBC_HWGENERAL_PHYM(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_PHYM_SHIFT)) & USBC_HWGENERAL_PHYM_MASK)
+
+#define USBC_HWGENERAL_SM_MASK                   (0xC00U)
+#define USBC_HWGENERAL_SM_SHIFT                  (10U)
+/*! SM - SM */
+#define USBC_HWGENERAL_SM(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_SM_SHIFT)) & USBC_HWGENERAL_SM_MASK)
+
+#define USBC_HWGENERAL_UNUSED_12_MASK            (0xFFFFF000U)
+#define USBC_HWGENERAL_UNUSED_12_SHIFT           (12U)
+/*! UNUSED_12 - UNUSED_12 */
+#define USBC_HWGENERAL_UNUSED_12(x)              (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_UNUSED_12_SHIFT)) & USBC_HWGENERAL_UNUSED_12_MASK)
+/*! @} */
+
+/*! @name HWHOST - HWHOST */
+/*! @{ */
+
+#define USBC_HWHOST_HC_MASK                      (0x1U)
+#define USBC_HWHOST_HC_SHIFT                     (0U)
+/*! HC - HC */
+#define USBC_HWHOST_HC(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_HC_SHIFT)) & USBC_HWHOST_HC_MASK)
+
+#define USBC_HWHOST_NPORT_MASK                   (0xEU)
+#define USBC_HWHOST_NPORT_SHIFT                  (1U)
+/*! NPORT - NPORT */
+#define USBC_HWHOST_NPORT(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_NPORT_SHIFT)) & USBC_HWHOST_NPORT_MASK)
+
+#define USBC_HWHOST_UNUSED_4_MASK                (0xFFF0U)
+#define USBC_HWHOST_UNUSED_4_SHIFT               (4U)
+/*! UNUSED_4 - UNUSED_4 */
+#define USBC_HWHOST_UNUSED_4(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_UNUSED_4_SHIFT)) & USBC_HWHOST_UNUSED_4_MASK)
+
+#define USBC_HWHOST_TTASY_MASK                   (0xFF0000U)
+#define USBC_HWHOST_TTASY_SHIFT                  (16U)
+/*! TTASY - TTASY */
+#define USBC_HWHOST_TTASY(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_TTASY_SHIFT)) & USBC_HWHOST_TTASY_MASK)
+
+#define USBC_HWHOST_TTPER_MASK                   (0xFF000000U)
+#define USBC_HWHOST_TTPER_SHIFT                  (24U)
+/*! TTPER - TTPER */
+#define USBC_HWHOST_TTPER(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_TTPER_SHIFT)) & USBC_HWHOST_TTPER_MASK)
+/*! @} */
+
+/*! @name HWDEVICE - HWDEVICE */
+/*! @{ */
+
+#define USBC_HWDEVICE_DC_MASK                    (0x1U)
+#define USBC_HWDEVICE_DC_SHIFT                   (0U)
+/*! DC - DC */
+#define USBC_HWDEVICE_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_HWDEVICE_DC_SHIFT)) & USBC_HWDEVICE_DC_MASK)
+
+#define USBC_HWDEVICE_DEVEP_MASK                 (0x3EU)
+#define USBC_HWDEVICE_DEVEP_SHIFT                (1U)
+/*! DEVEP - DEVEP */
+#define USBC_HWDEVICE_DEVEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_HWDEVICE_DEVEP_SHIFT)) & USBC_HWDEVICE_DEVEP_MASK)
+
+#define USBC_HWDEVICE_UNUSED_6_MASK              (0xFFFFFFC0U)
+#define USBC_HWDEVICE_UNUSED_6_SHIFT             (6U)
+/*! UNUSED_6 - UNUSED_6 */
+#define USBC_HWDEVICE_UNUSED_6(x)                (((uint32_t)(((uint32_t)(x)) << USBC_HWDEVICE_UNUSED_6_SHIFT)) & USBC_HWDEVICE_UNUSED_6_MASK)
+/*! @} */
+
+/*! @name HWTXBUF - HWTXBUF */
+/*! @{ */
+
+#define USBC_HWTXBUF_TXBURST_MASK                (0xFFU)
+#define USBC_HWTXBUF_TXBURST_SHIFT               (0U)
+/*! TXBURST - TXBURST */
+#define USBC_HWTXBUF_TXBURST(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_TXBURST_SHIFT)) & USBC_HWTXBUF_TXBURST_MASK)
+
+#define USBC_HWTXBUF_TXADD_MASK                  (0xFF00U)
+#define USBC_HWTXBUF_TXADD_SHIFT                 (8U)
+/*! TXADD - TXADD */
+#define USBC_HWTXBUF_TXADD(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_TXADD_SHIFT)) & USBC_HWTXBUF_TXADD_MASK)
+
+#define USBC_HWTXBUF_TXCHANADD_MASK              (0xFF0000U)
+#define USBC_HWTXBUF_TXCHANADD_SHIFT             (16U)
+/*! TXCHANADD - TXCHANADD */
+#define USBC_HWTXBUF_TXCHANADD(x)                (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_TXCHANADD_SHIFT)) & USBC_HWTXBUF_TXCHANADD_MASK)
+
+#define USBC_HWTXBUF_UNUSED_24_MASK              (0x7F000000U)
+#define USBC_HWTXBUF_UNUSED_24_SHIFT             (24U)
+/*! UNUSED_24 - UNUSED_24 */
+#define USBC_HWTXBUF_UNUSED_24(x)                (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_UNUSED_24_SHIFT)) & USBC_HWTXBUF_UNUSED_24_MASK)
+
+#define USBC_HWTXBUF_UNUSED_31_MASK              (0x80000000U)
+#define USBC_HWTXBUF_UNUSED_31_SHIFT             (31U)
+/*! UNUSED_31 - UNUSED_31 */
+#define USBC_HWTXBUF_UNUSED_31(x)                (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_UNUSED_31_SHIFT)) & USBC_HWTXBUF_UNUSED_31_MASK)
+/*! @} */
+
+/*! @name HWRXBUF - HWRXBUF */
+/*! @{ */
+
+#define USBC_HWRXBUF_RXBURST_MASK                (0xFFU)
+#define USBC_HWRXBUF_RXBURST_SHIFT               (0U)
+/*! RXBURST - RXBURST */
+#define USBC_HWRXBUF_RXBURST(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_HWRXBUF_RXBURST_SHIFT)) & USBC_HWRXBUF_RXBURST_MASK)
+
+#define USBC_HWRXBUF_RXADD_MASK                  (0xFF00U)
+#define USBC_HWRXBUF_RXADD_SHIFT                 (8U)
+/*! RXADD - RXADD */
+#define USBC_HWRXBUF_RXADD(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HWRXBUF_RXADD_SHIFT)) & USBC_HWRXBUF_RXADD_MASK)
+
+#define USBC_HWRXBUF_UNUSED_16_MASK              (0xFFFF0000U)
+#define USBC_HWRXBUF_UNUSED_16_SHIFT             (16U)
+/*! UNUSED_16 - UNUSED_16 */
+#define USBC_HWRXBUF_UNUSED_16(x)                (((uint32_t)(((uint32_t)(x)) << USBC_HWRXBUF_UNUSED_16_SHIFT)) & USBC_HWRXBUF_UNUSED_16_MASK)
+/*! @} */
+
+/*! @name HWTXBUF0 - HWTXBUF0 */
+/*! @{ */
+
+#define USBC_HWTXBUF0_TXBURST_MASK               (0xFFFFFFFFU)
+#define USBC_HWTXBUF0_TXBURST_SHIFT              (0U)
+/*! TXBURST - TXBURST */
+#define USBC_HWTXBUF0_TXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF0_TXBURST_SHIFT)) & USBC_HWTXBUF0_TXBURST_MASK)
+/*! @} */
+
+/*! @name HWTXBUF1 - HWTXBUF1 */
+/*! @{ */
+
+#define USBC_HWTXBUF1_TXBURST_MASK               (0xFFFFFFFFU)
+#define USBC_HWTXBUF1_TXBURST_SHIFT              (0U)
+/*! TXBURST - TXBURST */
+#define USBC_HWTXBUF1_TXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF1_TXBURST_SHIFT)) & USBC_HWTXBUF1_TXBURST_MASK)
+/*! @} */
+
+/*! @name GPTIMER0LD - GPTIMER0LD */
+/*! @{ */
+
+#define USBC_GPTIMER0LD_GPTLD_MASK               (0xFFFFFFU)
+#define USBC_GPTIMER0LD_GPTLD_SHIFT              (0U)
+/*! GPTLD - GPTLD */
+#define USBC_GPTIMER0LD_GPTLD(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0LD_GPTLD_SHIFT)) & USBC_GPTIMER0LD_GPTLD_MASK)
+
+#define USBC_GPTIMER0LD_UNUSED_24_MASK           (0xFF000000U)
+#define USBC_GPTIMER0LD_UNUSED_24_SHIFT          (24U)
+/*! UNUSED_24 - UNUSED_24 */
+#define USBC_GPTIMER0LD_UNUSED_24(x)             (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0LD_UNUSED_24_SHIFT)) & USBC_GPTIMER0LD_UNUSED_24_MASK)
+/*! @} */
+
+/*! @name GPTIMER0CTRL - GPTIMER0CTRL */
+/*! @{ */
+
+#define USBC_GPTIMER0CTRL_GPTCNT_MASK            (0xFFFFFFU)
+#define USBC_GPTIMER0CTRL_GPTCNT_SHIFT           (0U)
+/*! GPTCNT - GPTCNT */
+#define USBC_GPTIMER0CTRL_GPTCNT(x)              (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBC_GPTIMER0CTRL_GPTCNT_MASK)
+
+#define USBC_GPTIMER0CTRL_GPTMODE_MASK           (0x1000000U)
+#define USBC_GPTIMER0CTRL_GPTMODE_SHIFT          (24U)
+/*! GPTMODE - GPTMODE */
+#define USBC_GPTIMER0CTRL_GPTMODE(x)             (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTMODE_SHIFT)) & USBC_GPTIMER0CTRL_GPTMODE_MASK)
+
+#define USBC_GPTIMER0CTRL_UNUSED_25_MASK         (0x3E000000U)
+#define USBC_GPTIMER0CTRL_UNUSED_25_SHIFT        (25U)
+/*! UNUSED_25 - UNUSED_25 */
+#define USBC_GPTIMER0CTRL_UNUSED_25(x)           (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_UNUSED_25_SHIFT)) & USBC_GPTIMER0CTRL_UNUSED_25_MASK)
+
+#define USBC_GPTIMER0CTRL_GPTRST_MASK            (0x40000000U)
+#define USBC_GPTIMER0CTRL_GPTRST_SHIFT           (30U)
+/*! GPTRST - GPTRST */
+#define USBC_GPTIMER0CTRL_GPTRST(x)              (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTRST_SHIFT)) & USBC_GPTIMER0CTRL_GPTRST_MASK)
+
+#define USBC_GPTIMER0CTRL_GPTRUN_MASK            (0x80000000U)
+#define USBC_GPTIMER0CTRL_GPTRUN_SHIFT           (31U)
+/*! GPTRUN - GPTRUN */
+#define USBC_GPTIMER0CTRL_GPTRUN(x)              (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTRUN_SHIFT)) & USBC_GPTIMER0CTRL_GPTRUN_MASK)
+/*! @} */
+
+/*! @name GPTIMER1LD - GPTIMER1LD */
+/*! @{ */
+
+#define USBC_GPTIMER1LD_GPTLD_MASK               (0xFFFFFFU)
+#define USBC_GPTIMER1LD_GPTLD_SHIFT              (0U)
+/*! GPTLD - GPTLD */
+#define USBC_GPTIMER1LD_GPTLD(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1LD_GPTLD_SHIFT)) & USBC_GPTIMER1LD_GPTLD_MASK)
+
+#define USBC_GPTIMER1LD_UNUSED_24_MASK           (0xFF000000U)
+#define USBC_GPTIMER1LD_UNUSED_24_SHIFT          (24U)
+/*! UNUSED_24 - UNUSED_24 */
+#define USBC_GPTIMER1LD_UNUSED_24(x)             (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1LD_UNUSED_24_SHIFT)) & USBC_GPTIMER1LD_UNUSED_24_MASK)
+/*! @} */
+
+/*! @name GPTIMER1CTRL - GPTIMER1CTRL */
+/*! @{ */
+
+#define USBC_GPTIMER1CTRL_GPTCNT_MASK            (0xFFFFFFU)
+#define USBC_GPTIMER1CTRL_GPTCNT_SHIFT           (0U)
+/*! GPTCNT - GPTCNT */
+#define USBC_GPTIMER1CTRL_GPTCNT(x)              (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBC_GPTIMER1CTRL_GPTCNT_MASK)
+
+#define USBC_GPTIMER1CTRL_GPTMODE_MASK           (0x1000000U)
+#define USBC_GPTIMER1CTRL_GPTMODE_SHIFT          (24U)
+/*! GPTMODE - GPTMODE */
+#define USBC_GPTIMER1CTRL_GPTMODE(x)             (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTMODE_SHIFT)) & USBC_GPTIMER1CTRL_GPTMODE_MASK)
+
+#define USBC_GPTIMER1CTRL_UNUSED_25_MASK         (0x3E000000U)
+#define USBC_GPTIMER1CTRL_UNUSED_25_SHIFT        (25U)
+/*! UNUSED_25 - UNUSED_25 */
+#define USBC_GPTIMER1CTRL_UNUSED_25(x)           (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_UNUSED_25_SHIFT)) & USBC_GPTIMER1CTRL_UNUSED_25_MASK)
+
+#define USBC_GPTIMER1CTRL_GPTRST_MASK            (0x40000000U)
+#define USBC_GPTIMER1CTRL_GPTRST_SHIFT           (30U)
+/*! GPTRST - GPTRST */
+#define USBC_GPTIMER1CTRL_GPTRST(x)              (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTRST_SHIFT)) & USBC_GPTIMER1CTRL_GPTRST_MASK)
+
+#define USBC_GPTIMER1CTRL_GPTRUN_MASK            (0x80000000U)
+#define USBC_GPTIMER1CTRL_GPTRUN_SHIFT           (31U)
+/*! GPTRUN - GPTRUN */
+#define USBC_GPTIMER1CTRL_GPTRUN(x)              (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTRUN_SHIFT)) & USBC_GPTIMER1CTRL_GPTRUN_MASK)
+/*! @} */
+
+/*! @name SBUSCFG - SBUSCFG */
+/*! @{ */
+
+#define USBC_SBUSCFG_AHBBRST_MASK                (0x7U)
+#define USBC_SBUSCFG_AHBBRST_SHIFT               (0U)
+/*! AHBBRST - AHBBRST */
+#define USBC_SBUSCFG_AHBBRST(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_SBUSCFG_AHBBRST_SHIFT)) & USBC_SBUSCFG_AHBBRST_MASK)
+
+#define USBC_SBUSCFG_BARD_MASK                   (0x38U)
+#define USBC_SBUSCFG_BARD_SHIFT                  (3U)
+/*! BARD - BARD */
+#define USBC_SBUSCFG_BARD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_SBUSCFG_BARD_SHIFT)) & USBC_SBUSCFG_BARD_MASK)
+
+#define USBC_SBUSCFG_BAWR_MASK                   (0x1C0U)
+#define USBC_SBUSCFG_BAWR_SHIFT                  (6U)
+/*! BAWR - BAWR */
+#define USBC_SBUSCFG_BAWR(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_SBUSCFG_BAWR_SHIFT)) & USBC_SBUSCFG_BAWR_MASK)
+
+#define USBC_SBUSCFG_UNUSED_9_MASK               (0xFFFFFE00U)
+#define USBC_SBUSCFG_UNUSED_9_SHIFT              (9U)
+/*! UNUSED_9 - UNUSED_9 */
+#define USBC_SBUSCFG_UNUSED_9(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_SBUSCFG_UNUSED_9_SHIFT)) & USBC_SBUSCFG_UNUSED_9_MASK)
+/*! @} */
+
+/*! @name CAPLENGTH - CAPLENGTH */
+/*! @{ */
+
+#define USBC_CAPLENGTH_CAPLENGTH_MASK            (0xFFU)
+#define USBC_CAPLENGTH_CAPLENGTH_SHIFT           (0U)
+/*! CAPLENGTH - CAPLENGTH */
+#define USBC_CAPLENGTH_CAPLENGTH(x)              (((uint32_t)(((uint32_t)(x)) << USBC_CAPLENGTH_CAPLENGTH_SHIFT)) & USBC_CAPLENGTH_CAPLENGTH_MASK)
+
+#define USBC_CAPLENGTH_UNUSED_8_MASK             (0xFF00U)
+#define USBC_CAPLENGTH_UNUSED_8_SHIFT            (8U)
+/*! UNUSED_8 - UNUSED_8 */
+#define USBC_CAPLENGTH_UNUSED_8(x)               (((uint32_t)(((uint32_t)(x)) << USBC_CAPLENGTH_UNUSED_8_SHIFT)) & USBC_CAPLENGTH_UNUSED_8_MASK)
+
+#define USBC_CAPLENGTH_HCIVERSION_MASK           (0xFFFF0000U)
+#define USBC_CAPLENGTH_HCIVERSION_SHIFT          (16U)
+/*! HCIVERSION - HCIVERSION */
+#define USBC_CAPLENGTH_HCIVERSION(x)             (((uint32_t)(((uint32_t)(x)) << USBC_CAPLENGTH_HCIVERSION_SHIFT)) & USBC_CAPLENGTH_HCIVERSION_MASK)
+/*! @} */
+
+/*! @name HCSPARAMS - HCSPARAMS */
+/*! @{ */
+
+#define USBC_HCSPARAMS_N_PORTS_MASK              (0xFU)
+#define USBC_HCSPARAMS_N_PORTS_SHIFT             (0U)
+/*! N_PORTS - N_PORTS */
+#define USBC_HCSPARAMS_N_PORTS(x)                (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_PORTS_SHIFT)) & USBC_HCSPARAMS_N_PORTS_MASK)
+
+#define USBC_HCSPARAMS_PPC_MASK                  (0x10U)
+#define USBC_HCSPARAMS_PPC_SHIFT                 (4U)
+/*! PPC - PPC */
+#define USBC_HCSPARAMS_PPC(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_PPC_SHIFT)) & USBC_HCSPARAMS_PPC_MASK)
+
+#define USBC_HCSPARAMS_UNUSED_5_MASK             (0xE0U)
+#define USBC_HCSPARAMS_UNUSED_5_SHIFT            (5U)
+/*! UNUSED_5 - UNUSED_5 */
+#define USBC_HCSPARAMS_UNUSED_5(x)               (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_UNUSED_5_SHIFT)) & USBC_HCSPARAMS_UNUSED_5_MASK)
+
+#define USBC_HCSPARAMS_N_PCC_MASK                (0xF00U)
+#define USBC_HCSPARAMS_N_PCC_SHIFT               (8U)
+/*! N_PCC - N_PCC */
+#define USBC_HCSPARAMS_N_PCC(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_PCC_SHIFT)) & USBC_HCSPARAMS_N_PCC_MASK)
+
+#define USBC_HCSPARAMS_N_CC_MASK                 (0xF000U)
+#define USBC_HCSPARAMS_N_CC_SHIFT                (12U)
+/*! N_CC - N_CC */
+#define USBC_HCSPARAMS_N_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_CC_SHIFT)) & USBC_HCSPARAMS_N_CC_MASK)
+
+#define USBC_HCSPARAMS_PI_MASK                   (0x10000U)
+#define USBC_HCSPARAMS_PI_SHIFT                  (16U)
+/*! PI - PI */
+#define USBC_HCSPARAMS_PI(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_PI_SHIFT)) & USBC_HCSPARAMS_PI_MASK)
+
+#define USBC_HCSPARAMS_UNUSED_17_MASK            (0xE0000U)
+#define USBC_HCSPARAMS_UNUSED_17_SHIFT           (17U)
+/*! UNUSED_17 - UNUSED_17 */
+#define USBC_HCSPARAMS_UNUSED_17(x)              (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_UNUSED_17_SHIFT)) & USBC_HCSPARAMS_UNUSED_17_MASK)
+
+#define USBC_HCSPARAMS_N_PTT_MASK                (0xF00000U)
+#define USBC_HCSPARAMS_N_PTT_SHIFT               (20U)
+/*! N_PTT - N_PTT */
+#define USBC_HCSPARAMS_N_PTT(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_PTT_SHIFT)) & USBC_HCSPARAMS_N_PTT_MASK)
+
+#define USBC_HCSPARAMS_N_TT_MASK                 (0xF000000U)
+#define USBC_HCSPARAMS_N_TT_SHIFT                (24U)
+/*! N_TT - N_TT */
+#define USBC_HCSPARAMS_N_TT(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_TT_SHIFT)) & USBC_HCSPARAMS_N_TT_MASK)
+
+#define USBC_HCSPARAMS_UNUSED_28_MASK            (0xF0000000U)
+#define USBC_HCSPARAMS_UNUSED_28_SHIFT           (28U)
+/*! UNUSED_28 - UNUSED_28 */
+#define USBC_HCSPARAMS_UNUSED_28(x)              (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_UNUSED_28_SHIFT)) & USBC_HCSPARAMS_UNUSED_28_MASK)
+/*! @} */
+
+/*! @name HCCPARAMS - HCCPARAMS */
+/*! @{ */
+
+#define USBC_HCCPARAMS_ADC_MASK                  (0x1U)
+#define USBC_HCCPARAMS_ADC_SHIFT                 (0U)
+/*! ADC - ADC */
+#define USBC_HCCPARAMS_ADC(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_ADC_SHIFT)) & USBC_HCCPARAMS_ADC_MASK)
+
+#define USBC_HCCPARAMS_PFL_MASK                  (0x2U)
+#define USBC_HCCPARAMS_PFL_SHIFT                 (1U)
+/*! PFL - PFL */
+#define USBC_HCCPARAMS_PFL(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_PFL_SHIFT)) & USBC_HCCPARAMS_PFL_MASK)
+
+#define USBC_HCCPARAMS_ASP_MASK                  (0x4U)
+#define USBC_HCCPARAMS_ASP_SHIFT                 (2U)
+/*! ASP - ASP */
+#define USBC_HCCPARAMS_ASP(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_ASP_SHIFT)) & USBC_HCCPARAMS_ASP_MASK)
+
+#define USBC_HCCPARAMS_UNUSED_3_MASK             (0x8U)
+#define USBC_HCCPARAMS_UNUSED_3_SHIFT            (3U)
+/*! UNUSED_3 - UNUSED_3 */
+#define USBC_HCCPARAMS_UNUSED_3(x)               (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_UNUSED_3_SHIFT)) & USBC_HCCPARAMS_UNUSED_3_MASK)
+
+#define USBC_HCCPARAMS_IST_MASK                  (0xF0U)
+#define USBC_HCCPARAMS_IST_SHIFT                 (4U)
+/*! IST - IST */
+#define USBC_HCCPARAMS_IST(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_IST_SHIFT)) & USBC_HCCPARAMS_IST_MASK)
+
+#define USBC_HCCPARAMS_EECP_MASK                 (0xFF00U)
+#define USBC_HCCPARAMS_EECP_SHIFT                (8U)
+/*! EECP - EECP */
+#define USBC_HCCPARAMS_EECP(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_EECP_SHIFT)) & USBC_HCCPARAMS_EECP_MASK)
+
+#define USBC_HCCPARAMS_UNUSED_16_MASK            (0xFFFF0000U)
+#define USBC_HCCPARAMS_UNUSED_16_SHIFT           (16U)
+/*! UNUSED_16 - UNUSED_16 */
+#define USBC_HCCPARAMS_UNUSED_16(x)              (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_UNUSED_16_SHIFT)) & USBC_HCCPARAMS_UNUSED_16_MASK)
+/*! @} */
+
+/*! @name DCIVERSION - DCIVERSION */
+/*! @{ */
+
+#define USBC_DCIVERSION_DCIVERSION_MASK          (0xFFFFU)
+#define USBC_DCIVERSION_DCIVERSION_SHIFT         (0U)
+/*! DCIVERSION - DCIVERSION */
+#define USBC_DCIVERSION_DCIVERSION(x)            (((uint32_t)(((uint32_t)(x)) << USBC_DCIVERSION_DCIVERSION_SHIFT)) & USBC_DCIVERSION_DCIVERSION_MASK)
+
+#define USBC_DCIVERSION_UNUSED_16_MASK           (0xFFFF0000U)
+#define USBC_DCIVERSION_UNUSED_16_SHIFT          (16U)
+/*! UNUSED_16 - UNUSED_16 */
+#define USBC_DCIVERSION_UNUSED_16(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DCIVERSION_UNUSED_16_SHIFT)) & USBC_DCIVERSION_UNUSED_16_MASK)
+/*! @} */
+
+/*! @name DCCPARAMS - DCCPARAMS */
+/*! @{ */
+
+#define USBC_DCCPARAMS_DEN_MASK                  (0x1FU)
+#define USBC_DCCPARAMS_DEN_SHIFT                 (0U)
+/*! DEN - DEN */
+#define USBC_DCCPARAMS_DEN(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_DEN_SHIFT)) & USBC_DCCPARAMS_DEN_MASK)
+
+#define USBC_DCCPARAMS_UNUSED_5_MASK             (0x60U)
+#define USBC_DCCPARAMS_UNUSED_5_SHIFT            (5U)
+/*! UNUSED_5 - UNUSED_5 */
+#define USBC_DCCPARAMS_UNUSED_5(x)               (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_UNUSED_5_SHIFT)) & USBC_DCCPARAMS_UNUSED_5_MASK)
+
+#define USBC_DCCPARAMS_DC_MASK                   (0x80U)
+#define USBC_DCCPARAMS_DC_SHIFT                  (7U)
+/*! DC - DC */
+#define USBC_DCCPARAMS_DC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_DC_SHIFT)) & USBC_DCCPARAMS_DC_MASK)
+
+#define USBC_DCCPARAMS_HC_MASK                   (0x100U)
+#define USBC_DCCPARAMS_HC_SHIFT                  (8U)
+/*! HC - HC */
+#define USBC_DCCPARAMS_HC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_HC_SHIFT)) & USBC_DCCPARAMS_HC_MASK)
+
+#define USBC_DCCPARAMS_UNUSED_9_MASK             (0x7FFFFE00U)
+#define USBC_DCCPARAMS_UNUSED_9_SHIFT            (9U)
+/*! UNUSED_9 - UNUSED_9 */
+#define USBC_DCCPARAMS_UNUSED_9(x)               (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_UNUSED_9_SHIFT)) & USBC_DCCPARAMS_UNUSED_9_MASK)
+
+#define USBC_DCCPARAMS_LPM_EN_MASK               (0x80000000U)
+#define USBC_DCCPARAMS_LPM_EN_SHIFT              (31U)
+/*! LPM_EN - LPM_EN */
+#define USBC_DCCPARAMS_LPM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_LPM_EN_SHIFT)) & USBC_DCCPARAMS_LPM_EN_MASK)
+/*! @} */
+
+/*! @name DEVLPMCSR - DevLPMCSR */
+/*! @{ */
+
+#define USBC_DEVLPMCSR_INT_L1RSM_MASK            (0x1U)
+#define USBC_DEVLPMCSR_INT_L1RSM_SHIFT           (0U)
+/*! INT_L1RSM - INT_L1RSM */
+#define USBC_DEVLPMCSR_INT_L1RSM(x)              (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_L1RSM_SHIFT)) & USBC_DEVLPMCSR_INT_L1RSM_MASK)
+
+#define USBC_DEVLPMCSR_INT_LPMPKT_MASK           (0x2U)
+#define USBC_DEVLPMCSR_INT_LPMPKT_SHIFT          (1U)
+/*! INT_LPMPKT - INT_LPMPKT */
+#define USBC_DEVLPMCSR_INT_LPMPKT(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_LPMPKT_SHIFT)) & USBC_DEVLPMCSR_INT_LPMPKT_MASK)
+
+#define USBC_DEVLPMCSR_INT_LPMACK_MASK           (0x4U)
+#define USBC_DEVLPMCSR_INT_LPMACK_SHIFT          (2U)
+/*! INT_LPMACK - INT_LPMACK */
+#define USBC_DEVLPMCSR_INT_LPMACK(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_LPMACK_SHIFT)) & USBC_DEVLPMCSR_INT_LPMACK_MASK)
+
+#define USBC_DEVLPMCSR_INT_LPMERR_MASK           (0x8U)
+#define USBC_DEVLPMCSR_INT_LPMERR_SHIFT          (3U)
+/*! INT_LPMERR - INT_LPMERR */
+#define USBC_DEVLPMCSR_INT_LPMERR(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_LPMERR_SHIFT)) & USBC_DEVLPMCSR_INT_LPMERR_MASK)
+
+#define USBC_DEVLPMCSR_IE_L1RSM_MASK             (0x10U)
+#define USBC_DEVLPMCSR_IE_L1RSM_SHIFT            (4U)
+/*! IE_L1RSM - IE_L1RSM */
+#define USBC_DEVLPMCSR_IE_L1RSM(x)               (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_L1RSM_SHIFT)) & USBC_DEVLPMCSR_IE_L1RSM_MASK)
+
+#define USBC_DEVLPMCSR_IE_LPMPKT_MASK            (0x20U)
+#define USBC_DEVLPMCSR_IE_LPMPKT_SHIFT           (5U)
+/*! IE_LPMPKT - IE_LPMPKT */
+#define USBC_DEVLPMCSR_IE_LPMPKT(x)              (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_LPMPKT_SHIFT)) & USBC_DEVLPMCSR_IE_LPMPKT_MASK)
+
+#define USBC_DEVLPMCSR_IE_LPMACK_MASK            (0x40U)
+#define USBC_DEVLPMCSR_IE_LPMACK_SHIFT           (6U)
+/*! IE_LPMACK - IE_LPMACK */
+#define USBC_DEVLPMCSR_IE_LPMACK(x)              (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_LPMACK_SHIFT)) & USBC_DEVLPMCSR_IE_LPMACK_MASK)
+
+#define USBC_DEVLPMCSR_IE_LPMERR_MASK            (0x80U)
+#define USBC_DEVLPMCSR_IE_LPMERR_SHIFT           (7U)
+/*! IE_LPMERR - IE_LPMERR */
+#define USBC_DEVLPMCSR_IE_LPMERR(x)              (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_LPMERR_SHIFT)) & USBC_DEVLPMCSR_IE_LPMERR_MASK)
+
+#define USBC_DEVLPMCSR_RWAKE_EN_MASK             (0x100U)
+#define USBC_DEVLPMCSR_RWAKE_EN_SHIFT            (8U)
+/*! RWAKE_EN - RWAKE_EN */
+#define USBC_DEVLPMCSR_RWAKE_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_RWAKE_EN_SHIFT)) & USBC_DEVLPMCSR_RWAKE_EN_MASK)
+
+#define USBC_DEVLPMCSR_L1STATE_MASK              (0x200U)
+#define USBC_DEVLPMCSR_L1STATE_SHIFT             (9U)
+/*! L1STATE - L1STATE */
+#define USBC_DEVLPMCSR_L1STATE(x)                (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_L1STATE_SHIFT)) & USBC_DEVLPMCSR_L1STATE_MASK)
+
+#define USBC_DEVLPMCSR_IE_L1STATE_MASK           (0x400U)
+#define USBC_DEVLPMCSR_IE_L1STATE_SHIFT          (10U)
+/*! IE_L1STATE - IE_L1STATE */
+#define USBC_DEVLPMCSR_IE_L1STATE(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_L1STATE_SHIFT)) & USBC_DEVLPMCSR_IE_L1STATE_MASK)
+
+#define USBC_DEVLPMCSR_ACK_OK_MASK               (0x800U)
+#define USBC_DEVLPMCSR_ACK_OK_SHIFT              (11U)
+/*! ACK_OK - ACK_OK */
+#define USBC_DEVLPMCSR_ACK_OK(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_ACK_OK_SHIFT)) & USBC_DEVLPMCSR_ACK_OK_MASK)
+
+#define USBC_DEVLPMCSR_STALL_OK_MASK             (0x1000U)
+#define USBC_DEVLPMCSR_STALL_OK_SHIFT            (12U)
+/*! STALL_OK - STALL_OK */
+#define USBC_DEVLPMCSR_STALL_OK(x)               (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_STALL_OK_SHIFT)) & USBC_DEVLPMCSR_STALL_OK_MASK)
+
+#define USBC_DEVLPMCSR_MIN_SLP_EN_MASK           (0x2000U)
+#define USBC_DEVLPMCSR_MIN_SLP_EN_SHIFT          (13U)
+/*! MIN_SLP_EN - MIN_SLP_EN */
+#define USBC_DEVLPMCSR_MIN_SLP_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_MIN_SLP_EN_SHIFT)) & USBC_DEVLPMCSR_MIN_SLP_EN_MASK)
+
+#define USBC_DEVLPMCSR_ALWAYS_LOG_MASK           (0x4000U)
+#define USBC_DEVLPMCSR_ALWAYS_LOG_SHIFT          (14U)
+/*! ALWAYS_LOG - ALWAYS_LOG */
+#define USBC_DEVLPMCSR_ALWAYS_LOG(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_ALWAYS_LOG_SHIFT)) & USBC_DEVLPMCSR_ALWAYS_LOG_MASK)
+
+#define USBC_DEVLPMCSR_LPM_ON_MASK               (0x8000U)
+#define USBC_DEVLPMCSR_LPM_ON_SHIFT              (15U)
+/*! LPM_ON - LPM_ON */
+#define USBC_DEVLPMCSR_LPM_ON(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_ON_SHIFT)) & USBC_DEVLPMCSR_LPM_ON_MASK)
+
+#define USBC_DEVLPMCSR_HST_RSM_EN_MASK           (0x10000U)
+#define USBC_DEVLPMCSR_HST_RSM_EN_SHIFT          (16U)
+/*! HST_RSM_EN - HST_RSM_EN */
+#define USBC_DEVLPMCSR_HST_RSM_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_HST_RSM_EN_SHIFT)) & USBC_DEVLPMCSR_HST_RSM_EN_MASK)
+
+#define USBC_DEVLPMCSR_LPM_ANY_EP_MASK           (0x20000U)
+#define USBC_DEVLPMCSR_LPM_ANY_EP_SHIFT          (17U)
+/*! LPM_ANY_EP - LPM_ANY_EP */
+#define USBC_DEVLPMCSR_LPM_ANY_EP(x)             (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_ANY_EP_SHIFT)) & USBC_DEVLPMCSR_LPM_ANY_EP_MASK)
+
+#define USBC_DEVLPMCSR_UNUSED_18_MASK            (0xC0000U)
+#define USBC_DEVLPMCSR_UNUSED_18_SHIFT           (18U)
+/*! UNUSED_18 - UNUSED_18 */
+#define USBC_DEVLPMCSR_UNUSED_18(x)              (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_UNUSED_18_SHIFT)) & USBC_DEVLPMCSR_UNUSED_18_MASK)
+
+#define USBC_DEVLPMCSR_HIRD_MASK                 (0xF00000U)
+#define USBC_DEVLPMCSR_HIRD_SHIFT                (20U)
+/*! HIRD - HIRD */
+#define USBC_DEVLPMCSR_HIRD(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_HIRD_SHIFT)) & USBC_DEVLPMCSR_HIRD_MASK)
+
+#define USBC_DEVLPMCSR_LINKSTATE_MASK            (0xF000000U)
+#define USBC_DEVLPMCSR_LINKSTATE_SHIFT           (24U)
+/*! LINKSTATE - LINKSTATE */
+#define USBC_DEVLPMCSR_LINKSTATE(x)              (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LINKSTATE_SHIFT)) & USBC_DEVLPMCSR_LINKSTATE_MASK)
+
+#define USBC_DEVLPMCSR_BRMTWAKE_MASK             (0x10000000U)
+#define USBC_DEVLPMCSR_BRMTWAKE_SHIFT            (28U)
+/*! BRMTWAKE - BRMTWAKE */
+#define USBC_DEVLPMCSR_BRMTWAKE(x)               (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_BRMTWAKE_SHIFT)) & USBC_DEVLPMCSR_BRMTWAKE_MASK)
+
+#define USBC_DEVLPMCSR_LPM_PHCD_ONLY_MASK        (0x20000000U)
+#define USBC_DEVLPMCSR_LPM_PHCD_ONLY_SHIFT       (29U)
+/*! LPM_PHCD_ONLY - LPM_PHCD_only */
+#define USBC_DEVLPMCSR_LPM_PHCD_ONLY(x)          (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_PHCD_ONLY_SHIFT)) & USBC_DEVLPMCSR_LPM_PHCD_ONLY_MASK)
+
+#define USBC_DEVLPMCSR_LPM_RSP_MASK              (0xC0000000U)
+#define USBC_DEVLPMCSR_LPM_RSP_SHIFT             (30U)
+/*! LPM_RSP - LPM_RSP */
+#define USBC_DEVLPMCSR_LPM_RSP(x)                (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_RSP_SHIFT)) & USBC_DEVLPMCSR_LPM_RSP_MASK)
+/*! @} */
+
+/*! @name USBCMD - USBCMD */
+/*! @{ */
+
+#define USBC_USBCMD_RS_MASK                      (0x1U)
+#define USBC_USBCMD_RS_SHIFT                     (0U)
+/*! RS - RS */
+#define USBC_USBCMD_RS(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_RS_SHIFT)) & USBC_USBCMD_RS_MASK)
+
+#define USBC_USBCMD_RST_MASK                     (0x2U)
+#define USBC_USBCMD_RST_SHIFT                    (1U)
+/*! RST - RST */
+#define USBC_USBCMD_RST(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_RST_SHIFT)) & USBC_USBCMD_RST_MASK)
+
+#define USBC_USBCMD_FS0_MASK                     (0x4U)
+#define USBC_USBCMD_FS0_SHIFT                    (2U)
+/*! FS0 - HOST only */
+#define USBC_USBCMD_FS0(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_FS0_SHIFT)) & USBC_USBCMD_FS0_MASK)
+
+#define USBC_USBCMD_FS1_MASK                     (0x8U)
+#define USBC_USBCMD_FS1_SHIFT                    (3U)
+/*! FS1 - HOST only */
+#define USBC_USBCMD_FS1(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_FS1_SHIFT)) & USBC_USBCMD_FS1_MASK)
+
+#define USBC_USBCMD_PSE_MASK                     (0x10U)
+#define USBC_USBCMD_PSE_SHIFT                    (4U)
+/*! PSE - HOST only */
+#define USBC_USBCMD_PSE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_PSE_SHIFT)) & USBC_USBCMD_PSE_MASK)
+
+#define USBC_USBCMD_ASE_MASK                     (0x20U)
+#define USBC_USBCMD_ASE_SHIFT                    (5U)
+/*! ASE - HOST only */
+#define USBC_USBCMD_ASE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASE_SHIFT)) & USBC_USBCMD_ASE_MASK)
+
+#define USBC_USBCMD_IAA_MASK                     (0x40U)
+#define USBC_USBCMD_IAA_SHIFT                    (6U)
+/*! IAA - HOST only */
+#define USBC_USBCMD_IAA(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_IAA_SHIFT)) & USBC_USBCMD_IAA_MASK)
+
+#define USBC_USBCMD_LR_MASK                      (0x80U)
+#define USBC_USBCMD_LR_SHIFT                     (7U)
+/*! LR - LR */
+#define USBC_USBCMD_LR(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_LR_SHIFT)) & USBC_USBCMD_LR_MASK)
+
+#define USBC_USBCMD_ASP0_MASK                    (0x100U)
+#define USBC_USBCMD_ASP0_SHIFT                   (8U)
+/*! ASP0 - HOST only */
+#define USBC_USBCMD_ASP0(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASP0_SHIFT)) & USBC_USBCMD_ASP0_MASK)
+
+#define USBC_USBCMD_ASP1_MASK                    (0x200U)
+#define USBC_USBCMD_ASP1_SHIFT                   (9U)
+/*! ASP1 - HOST only */
+#define USBC_USBCMD_ASP1(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASP1_SHIFT)) & USBC_USBCMD_ASP1_MASK)
+
+#define USBC_USBCMD_UNUSED_10_MASK               (0x400U)
+#define USBC_USBCMD_UNUSED_10_SHIFT              (10U)
+/*! UNUSED_10 - UNUSED_10 */
+#define USBC_USBCMD_UNUSED_10(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_UNUSED_10_SHIFT)) & USBC_USBCMD_UNUSED_10_MASK)
+
+#define USBC_USBCMD_ASPE_MASK                    (0x800U)
+#define USBC_USBCMD_ASPE_SHIFT                   (11U)
+/*! ASPE - HOST only */
+#define USBC_USBCMD_ASPE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASPE_SHIFT)) & USBC_USBCMD_ASPE_MASK)
+
+#define USBC_USBCMD_UNUSED_12_MASK               (0x1000U)
+#define USBC_USBCMD_UNUSED_12_SHIFT              (12U)
+/*! UNUSED_12 - UNUSED_12 */
+#define USBC_USBCMD_UNUSED_12(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_UNUSED_12_SHIFT)) & USBC_USBCMD_UNUSED_12_MASK)
+
+#define USBC_USBCMD_SUTW_MASK                    (0x2000U)
+#define USBC_USBCMD_SUTW_SHIFT                   (13U)
+/*! SUTW - SUTW */
+#define USBC_USBCMD_SUTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_SUTW_SHIFT)) & USBC_USBCMD_SUTW_MASK)
+
+#define USBC_USBCMD_ATDTW_MASK                   (0x4000U)
+#define USBC_USBCMD_ATDTW_SHIFT                  (14U)
+/*! ATDTW - ATDTW */
+#define USBC_USBCMD_ATDTW(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ATDTW_SHIFT)) & USBC_USBCMD_ATDTW_MASK)
+
+#define USBC_USBCMD_FS2_MASK                     (0x8000U)
+#define USBC_USBCMD_FS2_SHIFT                    (15U)
+/*! FS2 - HOST only */
+#define USBC_USBCMD_FS2(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_FS2_SHIFT)) & USBC_USBCMD_FS2_MASK)
+
+#define USBC_USBCMD_ITC_MASK                     (0xFF0000U)
+#define USBC_USBCMD_ITC_SHIFT                    (16U)
+/*! ITC - ITC */
+#define USBC_USBCMD_ITC(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ITC_SHIFT)) & USBC_USBCMD_ITC_MASK)
+
+#define USBC_USBCMD_UNUSED_24_MASK               (0xFF000000U)
+#define USBC_USBCMD_UNUSED_24_SHIFT              (24U)
+/*! UNUSED_24 - UNUSED_24 */
+#define USBC_USBCMD_UNUSED_24(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_UNUSED_24_SHIFT)) & USBC_USBCMD_UNUSED_24_MASK)
+/*! @} */
+
+/*! @name USBSTS - USBSTS */
+/*! @{ */
+
+#define USBC_USBSTS_UI_MASK                      (0x1U)
+#define USBC_USBSTS_UI_SHIFT                     (0U)
+/*! UI - rwc */
+#define USBC_USBSTS_UI(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UI_SHIFT)) & USBC_USBSTS_UI_MASK)
+
+#define USBC_USBSTS_UEI_MASK                     (0x2U)
+#define USBC_USBSTS_UEI_SHIFT                    (1U)
+/*! UEI - rwc */
+#define USBC_USBSTS_UEI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UEI_SHIFT)) & USBC_USBSTS_UEI_MASK)
+
+#define USBC_USBSTS_PCI_MASK                     (0x4U)
+#define USBC_USBSTS_PCI_SHIFT                    (2U)
+/*! PCI - rwc */
+#define USBC_USBSTS_PCI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_PCI_SHIFT)) & USBC_USBSTS_PCI_MASK)
+
+#define USBC_USBSTS_FRI_MASK                     (0x8U)
+#define USBC_USBSTS_FRI_SHIFT                    (3U)
+/*! FRI - rwc */
+#define USBC_USBSTS_FRI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_FRI_SHIFT)) & USBC_USBSTS_FRI_MASK)
+
+#define USBC_USBSTS_SEI_MASK                     (0x10U)
+#define USBC_USBSTS_SEI_SHIFT                    (4U)
+/*! SEI - rwc */
+#define USBC_USBSTS_SEI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_SEI_SHIFT)) & USBC_USBSTS_SEI_MASK)
+
+#define USBC_USBSTS_AAI_MASK                     (0x20U)
+#define USBC_USBSTS_AAI_SHIFT                    (5U)
+/*! AAI - rwc */
+#define USBC_USBSTS_AAI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_AAI_SHIFT)) & USBC_USBSTS_AAI_MASK)
+
+#define USBC_USBSTS_URI_MASK                     (0x40U)
+#define USBC_USBSTS_URI_SHIFT                    (6U)
+/*! URI - rwc */
+#define USBC_USBSTS_URI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_URI_SHIFT)) & USBC_USBSTS_URI_MASK)
+
+#define USBC_USBSTS_SRI_MASK                     (0x80U)
+#define USBC_USBSTS_SRI_SHIFT                    (7U)
+/*! SRI - rwc */
+#define USBC_USBSTS_SRI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_SRI_SHIFT)) & USBC_USBSTS_SRI_MASK)
+
+#define USBC_USBSTS_SLI_MASK                     (0x100U)
+#define USBC_USBSTS_SLI_SHIFT                    (8U)
+/*! SLI - rwc */
+#define USBC_USBSTS_SLI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_SLI_SHIFT)) & USBC_USBSTS_SLI_MASK)
+
+#define USBC_USBSTS_UNUSED_9_MASK                (0x200U)
+#define USBC_USBSTS_UNUSED_9_SHIFT               (9U)
+/*! UNUSED_9 - UNUSED_9 */
+#define USBC_USBSTS_UNUSED_9(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UNUSED_9_SHIFT)) & USBC_USBSTS_UNUSED_9_MASK)
+
+#define USBC_USBSTS_ULPII_MASK                   (0x400U)
+#define USBC_USBSTS_ULPII_SHIFT                  (10U)
+/*! ULPII - rwc */
+#define USBC_USBSTS_ULPII(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_ULPII_SHIFT)) & USBC_USBSTS_ULPII_MASK)
+
+#define USBC_USBSTS_UNUSED_11_MASK               (0x800U)
+#define USBC_USBSTS_UNUSED_11_SHIFT              (11U)
+/*! UNUSED_11 - UNUSED_11 */
+#define USBC_USBSTS_UNUSED_11(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UNUSED_11_SHIFT)) & USBC_USBSTS_UNUSED_11_MASK)
+
+#define USBC_USBSTS_HCH_MASK                     (0x1000U)
+#define USBC_USBSTS_HCH_SHIFT                    (12U)
+/*! HCH - HOST only */
+#define USBC_USBSTS_HCH(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_HCH_SHIFT)) & USBC_USBSTS_HCH_MASK)
+
+#define USBC_USBSTS_RCL_MASK                     (0x2000U)
+#define USBC_USBSTS_RCL_SHIFT                    (13U)
+/*! RCL - RCL */
+#define USBC_USBSTS_RCL(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_RCL_SHIFT)) & USBC_USBSTS_RCL_MASK)
+
+#define USBC_USBSTS_PS_MASK                      (0x4000U)
+#define USBC_USBSTS_PS_SHIFT                     (14U)
+/*! PS - PS */
+#define USBC_USBSTS_PS(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_PS_SHIFT)) & USBC_USBSTS_PS_MASK)
+
+#define USBC_USBSTS_AS_MASK                      (0x8000U)
+#define USBC_USBSTS_AS_SHIFT                     (15U)
+/*! AS - AS */
+#define USBC_USBSTS_AS(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_AS_SHIFT)) & USBC_USBSTS_AS_MASK)
+
+#define USBC_USBSTS_NAKI_MASK                    (0x10000U)
+#define USBC_USBSTS_NAKI_SHIFT                   (16U)
+/*! NAKI - NAKI */
+#define USBC_USBSTS_NAKI(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_NAKI_SHIFT)) & USBC_USBSTS_NAKI_MASK)
+
+#define USBC_USBSTS_UNUSED_17_MASK               (0x20000U)
+#define USBC_USBSTS_UNUSED_17_SHIFT              (17U)
+/*! UNUSED_17 - UNUSED_17 */
+#define USBC_USBSTS_UNUSED_17(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UNUSED_17_SHIFT)) & USBC_USBSTS_UNUSED_17_MASK)
+
+#define USBC_USBSTS_UAI_MASK                     (0x40000U)
+#define USBC_USBSTS_UAI_SHIFT                    (18U)
+/*! UAI - rwc */
+#define USBC_USBSTS_UAI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UAI_SHIFT)) & USBC_USBSTS_UAI_MASK)
+
+#define USBC_USBSTS_UPI_MASK                     (0x80000U)
+#define USBC_USBSTS_UPI_SHIFT                    (19U)
+/*! UPI - rwc */
+#define USBC_USBSTS_UPI(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UPI_SHIFT)) & USBC_USBSTS_UPI_MASK)
+
+#define USBC_USBSTS_UNUSED_20_MASK               (0xF00000U)
+#define USBC_USBSTS_UNUSED_20_SHIFT              (20U)
+/*! UNUSED_20 - UNUSED_20 */
+#define USBC_USBSTS_UNUSED_20(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UNUSED_20_SHIFT)) & USBC_USBSTS_UNUSED_20_MASK)
+
+#define USBC_USBSTS_TI0_MASK                     (0x1000000U)
+#define USBC_USBSTS_TI0_SHIFT                    (24U)
+/*! TI0 - rwc */
+#define USBC_USBSTS_TI0(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_TI0_SHIFT)) & USBC_USBSTS_TI0_MASK)
+
+#define USBC_USBSTS_TI1_MASK                     (0x2000000U)
+#define USBC_USBSTS_TI1_SHIFT                    (25U)
+/*! TI1 - rwc */
+#define USBC_USBSTS_TI1(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_TI1_SHIFT)) & USBC_USBSTS_TI1_MASK)
+
+#define USBC_USBSTS_UNUSED_26_MASK               (0xFC000000U)
+#define USBC_USBSTS_UNUSED_26_SHIFT              (26U)
+/*! UNUSED_26 - UNUSED_26 */
+#define USBC_USBSTS_UNUSED_26(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UNUSED_26_SHIFT)) & USBC_USBSTS_UNUSED_26_MASK)
+/*! @} */
+
+/*! @name USBINTR - USBINTR */
+/*! @{ */
+
+#define USBC_USBINTR_UE_MASK                     (0x1U)
+#define USBC_USBINTR_UE_SHIFT                    (0U)
+/*! UE - UE */
+#define USBC_USBINTR_UE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UE_SHIFT)) & USBC_USBINTR_UE_MASK)
+
+#define USBC_USBINTR_UEE_MASK                    (0x2U)
+#define USBC_USBINTR_UEE_SHIFT                   (1U)
+/*! UEE - rwc */
+#define USBC_USBINTR_UEE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UEE_SHIFT)) & USBC_USBINTR_UEE_MASK)
+
+#define USBC_USBINTR_PCE_MASK                    (0x4U)
+#define USBC_USBINTR_PCE_SHIFT                   (2U)
+/*! PCE - PCE */
+#define USBC_USBINTR_PCE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_PCE_SHIFT)) & USBC_USBINTR_PCE_MASK)
+
+#define USBC_USBINTR_FRE_MASK                    (0x8U)
+#define USBC_USBINTR_FRE_SHIFT                   (3U)
+/*! FRE - HOST only */
+#define USBC_USBINTR_FRE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_FRE_SHIFT)) & USBC_USBINTR_FRE_MASK)
+
+#define USBC_USBINTR_SEE_MASK                    (0x10U)
+#define USBC_USBINTR_SEE_SHIFT                   (4U)
+/*! SEE - SEE */
+#define USBC_USBINTR_SEE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_SEE_SHIFT)) & USBC_USBINTR_SEE_MASK)
+
+#define USBC_USBINTR_AAE_MASK                    (0x20U)
+#define USBC_USBINTR_AAE_SHIFT                   (5U)
+/*! AAE - HOST only */
+#define USBC_USBINTR_AAE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_AAE_SHIFT)) & USBC_USBINTR_AAE_MASK)
+
+#define USBC_USBINTR_URE_MASK                    (0x40U)
+#define USBC_USBINTR_URE_SHIFT                   (6U)
+/*! URE - URE */
+#define USBC_USBINTR_URE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_URE_SHIFT)) & USBC_USBINTR_URE_MASK)
+
+#define USBC_USBINTR_SRE_MASK                    (0x80U)
+#define USBC_USBINTR_SRE_SHIFT                   (7U)
+/*! SRE - SRE */
+#define USBC_USBINTR_SRE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_SRE_SHIFT)) & USBC_USBINTR_SRE_MASK)
+
+#define USBC_USBINTR_SLE_MASK                    (0x100U)
+#define USBC_USBINTR_SLE_SHIFT                   (8U)
+/*! SLE - SLE */
+#define USBC_USBINTR_SLE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_SLE_SHIFT)) & USBC_USBINTR_SLE_MASK)
+
+#define USBC_USBINTR_UNUSED_9_MASK               (0x200U)
+#define USBC_USBINTR_UNUSED_9_SHIFT              (9U)
+/*! UNUSED_9 - UNUSED_9 */
+#define USBC_USBINTR_UNUSED_9(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_9_SHIFT)) & USBC_USBINTR_UNUSED_9_MASK)
+
+#define USBC_USBINTR_ULPE_MASK                   (0x400U)
+#define USBC_USBINTR_ULPE_SHIFT                  (10U)
+/*! ULPE - ONLY used VUSB_HS_PHY_ULPI =1 */
+#define USBC_USBINTR_ULPE(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_ULPE_SHIFT)) & USBC_USBINTR_ULPE_MASK)
+
+#define USBC_USBINTR_UNUSED_11_MASK              (0x800U)
+#define USBC_USBINTR_UNUSED_11_SHIFT             (11U)
+/*! UNUSED_11 - UNUSED_11 */
+#define USBC_USBINTR_UNUSED_11(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_11_SHIFT)) & USBC_USBINTR_UNUSED_11_MASK)
+
+#define USBC_USBINTR_UNUSED_12_MASK              (0x1000U)
+#define USBC_USBINTR_UNUSED_12_SHIFT             (12U)
+/*! UNUSED_12 - UNUSED_12 */
+#define USBC_USBINTR_UNUSED_12(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_12_SHIFT)) & USBC_USBINTR_UNUSED_12_MASK)
+
+#define USBC_USBINTR_UNUSED_13_MASK              (0x2000U)
+#define USBC_USBINTR_UNUSED_13_SHIFT             (13U)
+/*! UNUSED_13 - Not define in DUT,RCL */
+#define USBC_USBINTR_UNUSED_13(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_13_SHIFT)) & USBC_USBINTR_UNUSED_13_MASK)
+
+#define USBC_USBINTR_UNUSED_14_MASK              (0x4000U)
+#define USBC_USBINTR_UNUSED_14_SHIFT             (14U)
+/*! UNUSED_14 - Not define in DUT, PS */
+#define USBC_USBINTR_UNUSED_14(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_14_SHIFT)) & USBC_USBINTR_UNUSED_14_MASK)
+
+#define USBC_USBINTR_UNUSED_15_MASK              (0x8000U)
+#define USBC_USBINTR_UNUSED_15_SHIFT             (15U)
+/*! UNUSED_15 - Not define in DUT, AS */
+#define USBC_USBINTR_UNUSED_15(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_15_SHIFT)) & USBC_USBINTR_UNUSED_15_MASK)
+
+#define USBC_USBINTR_NAKE_MASK                   (0x10000U)
+#define USBC_USBINTR_NAKE_SHIFT                  (16U)
+/*! NAKE - NAKE */
+#define USBC_USBINTR_NAKE(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_NAKE_SHIFT)) & USBC_USBINTR_NAKE_MASK)
+
+#define USBC_USBINTR_UNUSED_17_MASK              (0x20000U)
+#define USBC_USBINTR_UNUSED_17_SHIFT             (17U)
+/*! UNUSED_17 - UNUSED_17 */
+#define USBC_USBINTR_UNUSED_17(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_17_SHIFT)) & USBC_USBINTR_UNUSED_17_MASK)
+
+#define USBC_USBINTR_UAE_MASK                    (0x40000U)
+#define USBC_USBINTR_UAE_SHIFT                   (18U)
+/*! UAE - Not use in Device mode */
+#define USBC_USBINTR_UAE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UAE_SHIFT)) & USBC_USBINTR_UAE_MASK)
+
+#define USBC_USBINTR_UPE_MASK                    (0x80000U)
+#define USBC_USBINTR_UPE_SHIFT                   (19U)
+/*! UPE - Not use in Device mode */
+#define USBC_USBINTR_UPE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UPE_SHIFT)) & USBC_USBINTR_UPE_MASK)
+
+#define USBC_USBINTR_UNUSED_20_MASK              (0xF00000U)
+#define USBC_USBINTR_UNUSED_20_SHIFT             (20U)
+/*! UNUSED_20 - UNUSED_20 */
+#define USBC_USBINTR_UNUSED_20(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_20_SHIFT)) & USBC_USBINTR_UNUSED_20_MASK)
+
+#define USBC_USBINTR_TIE0_MASK                   (0x1000000U)
+#define USBC_USBINTR_TIE0_SHIFT                  (24U)
+/*! TIE0 - TIE0 */
+#define USBC_USBINTR_TIE0(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_TIE0_SHIFT)) & USBC_USBINTR_TIE0_MASK)
+
+#define USBC_USBINTR_TIE1_MASK                   (0x2000000U)
+#define USBC_USBINTR_TIE1_SHIFT                  (25U)
+/*! TIE1 - TIE1 */
+#define USBC_USBINTR_TIE1(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_TIE1_SHIFT)) & USBC_USBINTR_TIE1_MASK)
+
+#define USBC_USBINTR_UNUSED_26_MASK              (0xFC000000U)
+#define USBC_USBINTR_UNUSED_26_SHIFT             (26U)
+/*! UNUSED_26 - UNUSED_26 */
+#define USBC_USBINTR_UNUSED_26(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UNUSED_26_SHIFT)) & USBC_USBINTR_UNUSED_26_MASK)
+/*! @} */
+
+/*! @name FRINDEX - FRINDEX */
+/*! @{ */
+
+#define USBC_FRINDEX_FRINDEX_MASK                (0x3FFFU)
+#define USBC_FRINDEX_FRINDEX_SHIFT               (0U)
+/*! FRINDEX - device RO, Host RW */
+#define USBC_FRINDEX_FRINDEX(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_FRINDEX_FRINDEX_SHIFT)) & USBC_FRINDEX_FRINDEX_MASK)
+
+#define USBC_FRINDEX_UNUSED_14_MASK              (0xFFFFC000U)
+#define USBC_FRINDEX_UNUSED_14_SHIFT             (14U)
+/*! UNUSED_14 - UNUSED_14 */
+#define USBC_FRINDEX_UNUSED_14(x)                (((uint32_t)(((uint32_t)(x)) << USBC_FRINDEX_UNUSED_14_SHIFT)) & USBC_FRINDEX_UNUSED_14_MASK)
+/*! @} */
+
+/*! @name DEVICEADDR - DEVICEADDR */
+/*! @{ */
+
+#define USBC_DEVICEADDR_UNUSED_0_MASK            (0xFFFFFFU)
+#define USBC_DEVICEADDR_UNUSED_0_SHIFT           (0U)
+/*! UNUSED_0 - UNUSED_0 */
+#define USBC_DEVICEADDR_UNUSED_0(x)              (((uint32_t)(((uint32_t)(x)) << USBC_DEVICEADDR_UNUSED_0_SHIFT)) & USBC_DEVICEADDR_UNUSED_0_MASK)
+
+#define USBC_DEVICEADDR_USBADRA_MASK             (0x1000000U)
+#define USBC_DEVICEADDR_USBADRA_SHIFT            (24U)
+/*! USBADRA - USBADRA */
+#define USBC_DEVICEADDR_USBADRA(x)               (((uint32_t)(((uint32_t)(x)) << USBC_DEVICEADDR_USBADRA_SHIFT)) & USBC_DEVICEADDR_USBADRA_MASK)
+
+#define USBC_DEVICEADDR_USBADR_MASK              (0xFE000000U)
+#define USBC_DEVICEADDR_USBADR_SHIFT             (25U)
+/*! USBADR - USBADR */
+#define USBC_DEVICEADDR_USBADR(x)                (((uint32_t)(((uint32_t)(x)) << USBC_DEVICEADDR_USBADR_SHIFT)) & USBC_DEVICEADDR_USBADR_MASK)
+/*! @} */
+
+/*! @name PERIODICLISTBASE - PERIODICLISTBASE */
+/*! @{ */
+
+#define USBC_PERIODICLISTBASE_UNUSED_0_MASK      (0xFFFU)
+#define USBC_PERIODICLISTBASE_UNUSED_0_SHIFT     (0U)
+/*! UNUSED_0 - UNUSED_0 */
+#define USBC_PERIODICLISTBASE_UNUSED_0(x)        (((uint32_t)(((uint32_t)(x)) << USBC_PERIODICLISTBASE_UNUSED_0_SHIFT)) & USBC_PERIODICLISTBASE_UNUSED_0_MASK)
+
+#define USBC_PERIODICLISTBASE_PERBASE_MASK       (0xFFFFF000U)
+#define USBC_PERIODICLISTBASE_PERBASE_SHIFT      (12U)
+/*! PERBASE - PERBASE */
+#define USBC_PERIODICLISTBASE_PERBASE(x)         (((uint32_t)(((uint32_t)(x)) << USBC_PERIODICLISTBASE_PERBASE_SHIFT)) & USBC_PERIODICLISTBASE_PERBASE_MASK)
+/*! @} */
+
+/*! @name ASYNCLISTADDR - ASYNCLISTADDR */
+/*! @{ */
+
+#define USBC_ASYNCLISTADDR_UNUSED_0_MASK         (0x1FU)
+#define USBC_ASYNCLISTADDR_UNUSED_0_SHIFT        (0U)
+/*! UNUSED_0 - UNUSED_0 */
+#define USBC_ASYNCLISTADDR_UNUSED_0(x)           (((uint32_t)(((uint32_t)(x)) << USBC_ASYNCLISTADDR_UNUSED_0_SHIFT)) & USBC_ASYNCLISTADDR_UNUSED_0_MASK)
+
+#define USBC_ASYNCLISTADDR_ASYBASE_MASK          (0xFFFFFFE0U)
+#define USBC_ASYNCLISTADDR_ASYBASE_SHIFT         (5U)
+/*! ASYBASE - ASYBASE */
+#define USBC_ASYNCLISTADDR_ASYBASE(x)            (((uint32_t)(((uint32_t)(x)) << USBC_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBC_ASYNCLISTADDR_ASYBASE_MASK)
+/*! @} */
+
+/*! @name ENDPOINTLISTADDR - ENDPOINTLISTADDR */
+/*! @{ */
+
+#define USBC_ENDPOINTLISTADDR_UNUSED_0_MASK      (0x7FFU)
+#define USBC_ENDPOINTLISTADDR_UNUSED_0_SHIFT     (0U)
+/*! UNUSED_0 - UNUSED_0 */
+#define USBC_ENDPOINTLISTADDR_UNUSED_0(x)        (((uint32_t)(((uint32_t)(x)) << USBC_ENDPOINTLISTADDR_UNUSED_0_SHIFT)) & USBC_ENDPOINTLISTADDR_UNUSED_0_MASK)
+
+#define USBC_ENDPOINTLISTADDR_EPBASE_MASK        (0xFFFFF800U)
+#define USBC_ENDPOINTLISTADDR_EPBASE_SHIFT       (11U)
+/*! EPBASE - EPBASE */
+#define USBC_ENDPOINTLISTADDR_EPBASE(x)          (((uint32_t)(((uint32_t)(x)) << USBC_ENDPOINTLISTADDR_EPBASE_SHIFT)) & USBC_ENDPOINTLISTADDR_EPBASE_MASK)
+/*! @} */
+
+/*! @name TTCTRL - TTCTRL */
+/*! @{ */
+
+#define USBC_TTCTRL_TTAS_MASK                    (0x1U)
+#define USBC_TTCTRL_TTAS_SHIFT                   (0U)
+/*! TTAS - TTAS */
+#define USBC_TTCTRL_TTAS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_TTAS_SHIFT)) & USBC_TTCTRL_TTAS_MASK)
+
+#define USBC_TTCTRL_TTAC_MASK                    (0x2U)
+#define USBC_TTCTRL_TTAC_SHIFT                   (1U)
+/*! TTAC - TTAC */
+#define USBC_TTCTRL_TTAC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_TTAC_SHIFT)) & USBC_TTCTRL_TTAC_MASK)
+
+#define USBC_TTCTRL_UNUSED_2_MASK                (0xFFFFFCU)
+#define USBC_TTCTRL_UNUSED_2_SHIFT               (2U)
+/*! UNUSED_2 - UNUSED_2 */
+#define USBC_TTCTRL_UNUSED_2(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_UNUSED_2_SHIFT)) & USBC_TTCTRL_UNUSED_2_MASK)
+
+#define USBC_TTCTRL_TTHA_MASK                    (0x7F000000U)
+#define USBC_TTCTRL_TTHA_SHIFT                   (24U)
+/*! TTHA - TTHA */
+#define USBC_TTCTRL_TTHA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_TTHA_SHIFT)) & USBC_TTCTRL_TTHA_MASK)
+
+#define USBC_TTCTRL_UNUSED_31_MASK               (0x80000000U)
+#define USBC_TTCTRL_UNUSED_31_SHIFT              (31U)
+/*! UNUSED_31 - UNUSED_31 */
+#define USBC_TTCTRL_UNUSED_31(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_UNUSED_31_SHIFT)) & USBC_TTCTRL_UNUSED_31_MASK)
+/*! @} */
+
+/*! @name BURSTSIZE - BURSTSIZE */
+/*! @{ */
+
+#define USBC_BURSTSIZE_RXPBURST_MASK             (0xFFU)
+#define USBC_BURSTSIZE_RXPBURST_SHIFT            (0U)
+/*! RXPBURST - RXPBURST */
+#define USBC_BURSTSIZE_RXPBURST(x)               (((uint32_t)(((uint32_t)(x)) << USBC_BURSTSIZE_RXPBURST_SHIFT)) & USBC_BURSTSIZE_RXPBURST_MASK)
+
+#define USBC_BURSTSIZE_TXPBURST_MASK             (0xFF00U)
+#define USBC_BURSTSIZE_TXPBURST_SHIFT            (8U)
+/*! TXPBURST - TXPBURST */
+#define USBC_BURSTSIZE_TXPBURST(x)               (((uint32_t)(((uint32_t)(x)) << USBC_BURSTSIZE_TXPBURST_SHIFT)) & USBC_BURSTSIZE_TXPBURST_MASK)
+
+#define USBC_BURSTSIZE_UNUSED_16_MASK            (0xFFFF0000U)
+#define USBC_BURSTSIZE_UNUSED_16_SHIFT           (16U)
+/*! UNUSED_16 - UNUSED_16 */
+#define USBC_BURSTSIZE_UNUSED_16(x)              (((uint32_t)(((uint32_t)(x)) << USBC_BURSTSIZE_UNUSED_16_SHIFT)) & USBC_BURSTSIZE_UNUSED_16_MASK)
+/*! @} */
+
+/*! @name TXFILLTUNING - TXFILLTUNING */
+/*! @{ */
+
+#define USBC_TXFILLTUNING_TXSCHOH_MASK           (0x7FU)
+#define USBC_TXFILLTUNING_TXSCHOH_SHIFT          (0U)
+/*! TXSCHOH - Only use in HOST & MPH mode */
+#define USBC_TXFILLTUNING_TXSCHOH(x)             (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_TXSCHOH_SHIFT)) & USBC_TXFILLTUNING_TXSCHOH_MASK)
+
+#define USBC_TXFILLTUNING_UNUSED_7_MASK          (0x80U)
+#define USBC_TXFILLTUNING_UNUSED_7_SHIFT         (7U)
+/*! UNUSED_7 - UNUSED_7 */
+#define USBC_TXFILLTUNING_UNUSED_7(x)            (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_UNUSED_7_SHIFT)) & USBC_TXFILLTUNING_UNUSED_7_MASK)
+
+#define USBC_TXFILLTUNING_TXSCHHEALTH_MASK       (0x1F00U)
+#define USBC_TXFILLTUNING_TXSCHHEALTH_SHIFT      (8U)
+/*! TXSCHHEALTH - Only use in HOST & MPH mode, rwc */
+#define USBC_TXFILLTUNING_TXSCHHEALTH(x)         (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBC_TXFILLTUNING_TXSCHHEALTH_MASK)
+
+#define USBC_TXFILLTUNING_UNUSED_13_MASK         (0xE000U)
+#define USBC_TXFILLTUNING_UNUSED_13_SHIFT        (13U)
+/*! UNUSED_13 - UNUSED_13 */
+#define USBC_TXFILLTUNING_UNUSED_13(x)           (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_UNUSED_13_SHIFT)) & USBC_TXFILLTUNING_UNUSED_13_MASK)
+
+#define USBC_TXFILLTUNING_TXFIFOTHRES_MASK       (0x3F0000U)
+#define USBC_TXFILLTUNING_TXFIFOTHRES_SHIFT      (16U)
+/*! TXFIFOTHRES - Only use in HOST & MPH mode */
+#define USBC_TXFILLTUNING_TXFIFOTHRES(x)         (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBC_TXFILLTUNING_TXFIFOTHRES_MASK)
+
+#define USBC_TXFILLTUNING_UNUSED_22_MASK         (0xFFC00000U)
+#define USBC_TXFILLTUNING_UNUSED_22_SHIFT        (22U)
+/*! UNUSED_22 - UNUSED_22 */
+#define USBC_TXFILLTUNING_UNUSED_22(x)           (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_UNUSED_22_SHIFT)) & USBC_TXFILLTUNING_UNUSED_22_MASK)
+/*! @} */
+
+/*! @name TXTTFILLTUNING - TXTTFILLTUNING */
+/*! @{ */
+
+#define USBC_TXTTFILLTUNING_TXTTSCHOH_MASK       (0x1FU)
+#define USBC_TXTTFILLTUNING_TXTTSCHOH_SHIFT      (0U)
+/*! TXTTSCHOH - Only use in HOST & MPH mode */
+#define USBC_TXTTFILLTUNING_TXTTSCHOH(x)         (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_TXTTSCHOH_SHIFT)) & USBC_TXTTFILLTUNING_TXTTSCHOH_MASK)
+
+#define USBC_TXTTFILLTUNING_UNUSED_5_MASK        (0xE0U)
+#define USBC_TXTTFILLTUNING_UNUSED_5_SHIFT       (5U)
+/*! UNUSED_5 - UNUSED_5 */
+#define USBC_TXTTFILLTUNING_UNUSED_5(x)          (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_UNUSED_5_SHIFT)) & USBC_TXTTFILLTUNING_UNUSED_5_MASK)
+
+#define USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_MASK   (0x1F00U)
+#define USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_SHIFT  (8U)
+/*! TXTTSCHHEALTJ - Only use in HOST & MPH mode, rwc */
+#define USBC_TXTTFILLTUNING_TXTTSCHHEALTJ(x)     (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_SHIFT)) & USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_MASK)
+
+#define USBC_TXTTFILLTUNING_UNUSED_13_MASK       (0xFFFFE000U)
+#define USBC_TXTTFILLTUNING_UNUSED_13_SHIFT      (13U)
+/*! UNUSED_13 - UNUSED_13 */
+#define USBC_TXTTFILLTUNING_UNUSED_13(x)         (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_UNUSED_13_SHIFT)) & USBC_TXTTFILLTUNING_UNUSED_13_MASK)
+/*! @} */
+
+/*! @name IC_USB - IC_USB */
+/*! @{ */
+
+#define USBC_IC_USB_IC_VDD1_MASK                 (0x7U)
+#define USBC_IC_USB_IC_VDD1_SHIFT                (0U)
+/*! IC_VDD1 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD1_SHIFT)) & USBC_IC_USB_IC_VDD1_MASK)
+
+#define USBC_IC_USB_IC1_MASK                     (0x8U)
+#define USBC_IC_USB_IC1_SHIFT                    (3U)
+/*! IC1 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC1(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC1_SHIFT)) & USBC_IC_USB_IC1_MASK)
+
+#define USBC_IC_USB_IC_VDD2_MASK                 (0x70U)
+#define USBC_IC_USB_IC_VDD2_SHIFT                (4U)
+/*! IC_VDD2 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD2_SHIFT)) & USBC_IC_USB_IC_VDD2_MASK)
+
+#define USBC_IC_USB_IC2_MASK                     (0x80U)
+#define USBC_IC_USB_IC2_SHIFT                    (7U)
+/*! IC2 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC2(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC2_SHIFT)) & USBC_IC_USB_IC2_MASK)
+
+#define USBC_IC_USB_IC_VDD3_MASK                 (0x700U)
+#define USBC_IC_USB_IC_VDD3_SHIFT                (8U)
+/*! IC_VDD3 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD3(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD3_SHIFT)) & USBC_IC_USB_IC_VDD3_MASK)
+
+#define USBC_IC_USB_IC3_MASK                     (0x800U)
+#define USBC_IC_USB_IC3_SHIFT                    (11U)
+/*! IC3 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC3(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC3_SHIFT)) & USBC_IC_USB_IC3_MASK)
+
+#define USBC_IC_USB_IC_VDD4_MASK                 (0x7000U)
+#define USBC_IC_USB_IC_VDD4_SHIFT                (12U)
+/*! IC_VDD4 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD4(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD4_SHIFT)) & USBC_IC_USB_IC_VDD4_MASK)
+
+#define USBC_IC_USB_IC4_MASK                     (0x8000U)
+#define USBC_IC_USB_IC4_SHIFT                    (15U)
+/*! IC4 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC4(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC4_SHIFT)) & USBC_IC_USB_IC4_MASK)
+
+#define USBC_IC_USB_IC_VDD5_MASK                 (0x70000U)
+#define USBC_IC_USB_IC_VDD5_SHIFT                (16U)
+/*! IC_VDD5 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD5(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD5_SHIFT)) & USBC_IC_USB_IC_VDD5_MASK)
+
+#define USBC_IC_USB_IC5_MASK                     (0x80000U)
+#define USBC_IC_USB_IC5_SHIFT                    (19U)
+/*! IC5 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC5(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC5_SHIFT)) & USBC_IC_USB_IC5_MASK)
+
+#define USBC_IC_USB_IC_VDD6_MASK                 (0x700000U)
+#define USBC_IC_USB_IC_VDD6_SHIFT                (20U)
+/*! IC_VDD6 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD6(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD6_SHIFT)) & USBC_IC_USB_IC_VDD6_MASK)
+
+#define USBC_IC_USB_IC6_MASK                     (0x800000U)
+#define USBC_IC_USB_IC6_SHIFT                    (23U)
+/*! IC6 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC6(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC6_SHIFT)) & USBC_IC_USB_IC6_MASK)
+
+#define USBC_IC_USB_IC_VDD7_MASK                 (0x7000000U)
+#define USBC_IC_USB_IC_VDD7_SHIFT                (24U)
+/*! IC_VDD7 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD7(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD7_SHIFT)) & USBC_IC_USB_IC_VDD7_MASK)
+
+#define USBC_IC_USB_IC7_MASK                     (0x8000000U)
+#define USBC_IC_USB_IC7_SHIFT                    (27U)
+/*! IC7 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC7(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC7_SHIFT)) & USBC_IC_USB_IC7_MASK)
+
+#define USBC_IC_USB_IC_VDD8_MASK                 (0x70000000U)
+#define USBC_IC_USB_IC_VDD8_SHIFT                (28U)
+/*! IC_VDD8 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC_VDD8(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD8_SHIFT)) & USBC_IC_USB_IC_VDD8_MASK)
+
+#define USBC_IC_USB_IC8_MASK                     (0x80000000U)
+#define USBC_IC_USB_IC8_SHIFT                    (31U)
+/*! IC8 - available in MPH & VUSB_HS_PHY_IC_USB =1 */
+#define USBC_IC_USB_IC8(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC8_SHIFT)) & USBC_IC_USB_IC8_MASK)
+/*! @} */
+
+/*! @name ULPI_VIEWPORT - ULPI_VIEWPORT */
+/*! @{ */
+
+#define USBC_ULPI_VIEWPORT_ULPIDATWR_MASK        (0xFFU)
+#define USBC_ULPI_VIEWPORT_ULPIDATWR_SHIFT       (0U)
+/*! ULPIDATWR - Not available */
+#define USBC_ULPI_VIEWPORT_ULPIDATWR(x)          (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIDATWR_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIDATWR_MASK)
+
+#define USBC_ULPI_VIEWPORT_ULPIDATRD_MASK        (0xFF00U)
+#define USBC_ULPI_VIEWPORT_ULPIDATRD_SHIFT       (8U)
+/*! ULPIDATRD - Not available */
+#define USBC_ULPI_VIEWPORT_ULPIDATRD(x)          (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIDATRD_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIDATRD_MASK)
+
+#define USBC_ULPI_VIEWPORT_ULPIADDR_MASK         (0xFF0000U)
+#define USBC_ULPI_VIEWPORT_ULPIADDR_SHIFT        (16U)
+/*! ULPIADDR - Not available */
+#define USBC_ULPI_VIEWPORT_ULPIADDR(x)           (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIADDR_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIADDR_MASK)
+
+#define USBC_ULPI_VIEWPORT_ULPIPORT_MASK         (0x7000000U)
+#define USBC_ULPI_VIEWPORT_ULPIPORT_SHIFT        (24U)
+/*! ULPIPORT - Not available */
+#define USBC_ULPI_VIEWPORT_ULPIPORT(x)           (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIPORT_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIPORT_MASK)
+
+#define USBC_ULPI_VIEWPORT_ULPISS_MASK           (0x8000000U)
+#define USBC_ULPI_VIEWPORT_ULPISS_SHIFT          (27U)
+/*! ULPISS - Not available */
+#define USBC_ULPI_VIEWPORT_ULPISS(x)             (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPISS_SHIFT)) & USBC_ULPI_VIEWPORT_ULPISS_MASK)
+
+#define USBC_ULPI_VIEWPORT_UNUSED_28_MASK        (0x10000000U)
+#define USBC_ULPI_VIEWPORT_UNUSED_28_SHIFT       (28U)
+/*! UNUSED_28 - Not available */
+#define USBC_ULPI_VIEWPORT_UNUSED_28(x)          (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_UNUSED_28_SHIFT)) & USBC_ULPI_VIEWPORT_UNUSED_28_MASK)
+
+#define USBC_ULPI_VIEWPORT_ULPIRW_MASK           (0x20000000U)
+#define USBC_ULPI_VIEWPORT_ULPIRW_SHIFT          (29U)
+/*! ULPIRW - Not available */
+#define USBC_ULPI_VIEWPORT_ULPIRW(x)             (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIRW_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIRW_MASK)
+
+#define USBC_ULPI_VIEWPORT_ULPIRUN_MASK          (0x40000000U)
+#define USBC_ULPI_VIEWPORT_ULPIRUN_SHIFT         (30U)
+/*! ULPIRUN - Not available */
+#define USBC_ULPI_VIEWPORT_ULPIRUN(x)            (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIRUN_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIRUN_MASK)
+
+#define USBC_ULPI_VIEWPORT_ULPIWU_MASK           (0x80000000U)
+#define USBC_ULPI_VIEWPORT_ULPIWU_SHIFT          (31U)
+/*! ULPIWU - Not available */
+#define USBC_ULPI_VIEWPORT_ULPIWU(x)             (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIWU_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIWU_MASK)
+/*! @} */
+
+/*! @name ENDPTNAK - ENDPTNAK */
+/*! @{ */
+
+#define USBC_ENDPTNAK_EPRN_MASK                  (0xFFFFU)
+#define USBC_ENDPTNAK_EPRN_SHIFT                 (0U)
+/*! EPRN - rwc */
+#define USBC_ENDPTNAK_EPRN(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAK_EPRN_SHIFT)) & USBC_ENDPTNAK_EPRN_MASK)
+
+#define USBC_ENDPTNAK_EPTN_MASK                  (0xFFFF0000U)
+#define USBC_ENDPTNAK_EPTN_SHIFT                 (16U)
+/*! EPTN - rwc */
+#define USBC_ENDPTNAK_EPTN(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAK_EPTN_SHIFT)) & USBC_ENDPTNAK_EPTN_MASK)
+/*! @} */
+
+/*! @name ENDPTNAKEN - ENDPTNAKEN */
+/*! @{ */
+
+#define USBC_ENDPTNAKEN_EPRNE_MASK               (0xFFFFU)
+#define USBC_ENDPTNAKEN_EPRNE_SHIFT              (0U)
+/*! EPRNE - Only 3 PHY max */
+#define USBC_ENDPTNAKEN_EPRNE(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAKEN_EPRNE_SHIFT)) & USBC_ENDPTNAKEN_EPRNE_MASK)
+
+#define USBC_ENDPTNAKEN_EPTNE_MASK               (0xFFFF0000U)
+#define USBC_ENDPTNAKEN_EPTNE_SHIFT              (16U)
+/*! EPTNE - Only 3 PHY max */
+#define USBC_ENDPTNAKEN_EPTNE(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAKEN_EPTNE_SHIFT)) & USBC_ENDPTNAKEN_EPTNE_MASK)
+/*! @} */
+
+/*! @name PORTSC1 - PORTSC1 */
+/*! @{ */
+
+#define USBC_PORTSC1_CCS_MASK                    (0x1U)
+#define USBC_PORTSC1_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC1_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_CCS_SHIFT)) & USBC_PORTSC1_CCS_MASK)
+
+#define USBC_PORTSC1_CSC_MASK                    (0x2U)
+#define USBC_PORTSC1_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC1_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_CSC_SHIFT)) & USBC_PORTSC1_CSC_MASK)
+
+#define USBC_PORTSC1_PE_MASK                     (0x4U)
+#define USBC_PORTSC1_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC1_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PE_SHIFT)) & USBC_PORTSC1_PE_MASK)
+
+#define USBC_PORTSC1_PEC_MASK                    (0x8U)
+#define USBC_PORTSC1_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC1_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PEC_SHIFT)) & USBC_PORTSC1_PEC_MASK)
+
+#define USBC_PORTSC1_OCA_MASK                    (0x10U)
+#define USBC_PORTSC1_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC1_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_OCA_SHIFT)) & USBC_PORTSC1_OCA_MASK)
+
+#define USBC_PORTSC1_OCC_MASK                    (0x20U)
+#define USBC_PORTSC1_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC1_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_OCC_SHIFT)) & USBC_PORTSC1_OCC_MASK)
+
+#define USBC_PORTSC1_FPR_MASK                    (0x40U)
+#define USBC_PORTSC1_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC1_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_FPR_SHIFT)) & USBC_PORTSC1_FPR_MASK)
+
+#define USBC_PORTSC1_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC1_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC1_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_SUSP_SHIFT)) & USBC_PORTSC1_SUSP_MASK)
+
+#define USBC_PORTSC1_PR_MASK                     (0x100U)
+#define USBC_PORTSC1_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC1_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PR_SHIFT)) & USBC_PORTSC1_PR_MASK)
+
+#define USBC_PORTSC1_HSP_MASK                    (0x200U)
+#define USBC_PORTSC1_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC1_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_HSP_SHIFT)) & USBC_PORTSC1_HSP_MASK)
+
+#define USBC_PORTSC1_LS_MASK                     (0xC00U)
+#define USBC_PORTSC1_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC1_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_LS_SHIFT)) & USBC_PORTSC1_LS_MASK)
+
+#define USBC_PORTSC1_PP_MASK                     (0x1000U)
+#define USBC_PORTSC1_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC1_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PP_SHIFT)) & USBC_PORTSC1_PP_MASK)
+
+#define USBC_PORTSC1_PO_MASK                     (0x2000U)
+#define USBC_PORTSC1_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC1_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PO_SHIFT)) & USBC_PORTSC1_PO_MASK)
+
+#define USBC_PORTSC1_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC1_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC1_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PIC_SHIFT)) & USBC_PORTSC1_PIC_MASK)
+
+#define USBC_PORTSC1_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC1_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC1_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTC_SHIFT)) & USBC_PORTSC1_PTC_MASK)
+
+#define USBC_PORTSC1_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC1_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC1_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_WKCN_SHIFT)) & USBC_PORTSC1_WKCN_MASK)
+
+#define USBC_PORTSC1_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC1_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC1_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_WKDS_SHIFT)) & USBC_PORTSC1_WKDS_MASK)
+
+#define USBC_PORTSC1_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC1_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC1_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_WKOC_SHIFT)) & USBC_PORTSC1_WKOC_MASK)
+
+#define USBC_PORTSC1_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC1_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC1_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PHCD_SHIFT)) & USBC_PORTSC1_PHCD_MASK)
+
+#define USBC_PORTSC1_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC1_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC1_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PFSC_SHIFT)) & USBC_PORTSC1_PFSC_MASK)
+
+#define USBC_PORTSC1_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC1_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC1_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTS2_SHIFT)) & USBC_PORTSC1_PTS2_MASK)
+
+#define USBC_PORTSC1_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC1_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC1_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PSPD_SHIFT)) & USBC_PORTSC1_PSPD_MASK)
+
+#define USBC_PORTSC1_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC1_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC1_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTW_SHIFT)) & USBC_PORTSC1_PTW_MASK)
+
+#define USBC_PORTSC1_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC1_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC1_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_STS_SHIFT)) & USBC_PORTSC1_STS_MASK)
+
+#define USBC_PORTSC1_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC1_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC1_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTS_SHIFT)) & USBC_PORTSC1_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC2 - PORTSC2 */
+/*! @{ */
+
+#define USBC_PORTSC2_CCS_MASK                    (0x1U)
+#define USBC_PORTSC2_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC2_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_CCS_SHIFT)) & USBC_PORTSC2_CCS_MASK)
+
+#define USBC_PORTSC2_CSC_MASK                    (0x2U)
+#define USBC_PORTSC2_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC2_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_CSC_SHIFT)) & USBC_PORTSC2_CSC_MASK)
+
+#define USBC_PORTSC2_PE_MASK                     (0x4U)
+#define USBC_PORTSC2_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC2_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PE_SHIFT)) & USBC_PORTSC2_PE_MASK)
+
+#define USBC_PORTSC2_PEC_MASK                    (0x8U)
+#define USBC_PORTSC2_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC2_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PEC_SHIFT)) & USBC_PORTSC2_PEC_MASK)
+
+#define USBC_PORTSC2_OCA_MASK                    (0x10U)
+#define USBC_PORTSC2_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC2_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_OCA_SHIFT)) & USBC_PORTSC2_OCA_MASK)
+
+#define USBC_PORTSC2_OCC_MASK                    (0x20U)
+#define USBC_PORTSC2_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC2_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_OCC_SHIFT)) & USBC_PORTSC2_OCC_MASK)
+
+#define USBC_PORTSC2_FPR_MASK                    (0x40U)
+#define USBC_PORTSC2_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC2_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_FPR_SHIFT)) & USBC_PORTSC2_FPR_MASK)
+
+#define USBC_PORTSC2_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC2_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC2_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_SUSP_SHIFT)) & USBC_PORTSC2_SUSP_MASK)
+
+#define USBC_PORTSC2_PR_MASK                     (0x100U)
+#define USBC_PORTSC2_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC2_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PR_SHIFT)) & USBC_PORTSC2_PR_MASK)
+
+#define USBC_PORTSC2_HSP_MASK                    (0x200U)
+#define USBC_PORTSC2_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC2_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_HSP_SHIFT)) & USBC_PORTSC2_HSP_MASK)
+
+#define USBC_PORTSC2_LS_MASK                     (0xC00U)
+#define USBC_PORTSC2_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC2_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_LS_SHIFT)) & USBC_PORTSC2_LS_MASK)
+
+#define USBC_PORTSC2_PP_MASK                     (0x1000U)
+#define USBC_PORTSC2_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC2_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PP_SHIFT)) & USBC_PORTSC2_PP_MASK)
+
+#define USBC_PORTSC2_PO_MASK                     (0x2000U)
+#define USBC_PORTSC2_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC2_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PO_SHIFT)) & USBC_PORTSC2_PO_MASK)
+
+#define USBC_PORTSC2_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC2_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC2_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PIC_SHIFT)) & USBC_PORTSC2_PIC_MASK)
+
+#define USBC_PORTSC2_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC2_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC2_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTC_SHIFT)) & USBC_PORTSC2_PTC_MASK)
+
+#define USBC_PORTSC2_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC2_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC2_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_WKCN_SHIFT)) & USBC_PORTSC2_WKCN_MASK)
+
+#define USBC_PORTSC2_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC2_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC2_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_WKDS_SHIFT)) & USBC_PORTSC2_WKDS_MASK)
+
+#define USBC_PORTSC2_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC2_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC2_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_WKOC_SHIFT)) & USBC_PORTSC2_WKOC_MASK)
+
+#define USBC_PORTSC2_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC2_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC2_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PHCD_SHIFT)) & USBC_PORTSC2_PHCD_MASK)
+
+#define USBC_PORTSC2_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC2_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC2_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PFSC_SHIFT)) & USBC_PORTSC2_PFSC_MASK)
+
+#define USBC_PORTSC2_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC2_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC2_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTS2_SHIFT)) & USBC_PORTSC2_PTS2_MASK)
+
+#define USBC_PORTSC2_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC2_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC2_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PSPD_SHIFT)) & USBC_PORTSC2_PSPD_MASK)
+
+#define USBC_PORTSC2_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC2_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC2_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTW_SHIFT)) & USBC_PORTSC2_PTW_MASK)
+
+#define USBC_PORTSC2_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC2_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC2_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_STS_SHIFT)) & USBC_PORTSC2_STS_MASK)
+
+#define USBC_PORTSC2_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC2_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC2_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTS_SHIFT)) & USBC_PORTSC2_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC3 - PORTSC3 */
+/*! @{ */
+
+#define USBC_PORTSC3_CCS_MASK                    (0x1U)
+#define USBC_PORTSC3_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC3_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_CCS_SHIFT)) & USBC_PORTSC3_CCS_MASK)
+
+#define USBC_PORTSC3_CSC_MASK                    (0x2U)
+#define USBC_PORTSC3_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC3_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_CSC_SHIFT)) & USBC_PORTSC3_CSC_MASK)
+
+#define USBC_PORTSC3_PE_MASK                     (0x4U)
+#define USBC_PORTSC3_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC3_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PE_SHIFT)) & USBC_PORTSC3_PE_MASK)
+
+#define USBC_PORTSC3_PEC_MASK                    (0x8U)
+#define USBC_PORTSC3_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC3_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PEC_SHIFT)) & USBC_PORTSC3_PEC_MASK)
+
+#define USBC_PORTSC3_OCA_MASK                    (0x10U)
+#define USBC_PORTSC3_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC3_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_OCA_SHIFT)) & USBC_PORTSC3_OCA_MASK)
+
+#define USBC_PORTSC3_OCC_MASK                    (0x20U)
+#define USBC_PORTSC3_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC3_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_OCC_SHIFT)) & USBC_PORTSC3_OCC_MASK)
+
+#define USBC_PORTSC3_FPR_MASK                    (0x40U)
+#define USBC_PORTSC3_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC3_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_FPR_SHIFT)) & USBC_PORTSC3_FPR_MASK)
+
+#define USBC_PORTSC3_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC3_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC3_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_SUSP_SHIFT)) & USBC_PORTSC3_SUSP_MASK)
+
+#define USBC_PORTSC3_PR_MASK                     (0x100U)
+#define USBC_PORTSC3_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC3_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PR_SHIFT)) & USBC_PORTSC3_PR_MASK)
+
+#define USBC_PORTSC3_HSP_MASK                    (0x200U)
+#define USBC_PORTSC3_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC3_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_HSP_SHIFT)) & USBC_PORTSC3_HSP_MASK)
+
+#define USBC_PORTSC3_LS_MASK                     (0xC00U)
+#define USBC_PORTSC3_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC3_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_LS_SHIFT)) & USBC_PORTSC3_LS_MASK)
+
+#define USBC_PORTSC3_PP_MASK                     (0x1000U)
+#define USBC_PORTSC3_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC3_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PP_SHIFT)) & USBC_PORTSC3_PP_MASK)
+
+#define USBC_PORTSC3_PO_MASK                     (0x2000U)
+#define USBC_PORTSC3_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC3_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PO_SHIFT)) & USBC_PORTSC3_PO_MASK)
+
+#define USBC_PORTSC3_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC3_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC3_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PIC_SHIFT)) & USBC_PORTSC3_PIC_MASK)
+
+#define USBC_PORTSC3_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC3_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC3_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTC_SHIFT)) & USBC_PORTSC3_PTC_MASK)
+
+#define USBC_PORTSC3_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC3_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC3_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_WKCN_SHIFT)) & USBC_PORTSC3_WKCN_MASK)
+
+#define USBC_PORTSC3_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC3_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC3_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_WKDS_SHIFT)) & USBC_PORTSC3_WKDS_MASK)
+
+#define USBC_PORTSC3_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC3_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC3_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_WKOC_SHIFT)) & USBC_PORTSC3_WKOC_MASK)
+
+#define USBC_PORTSC3_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC3_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC3_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PHCD_SHIFT)) & USBC_PORTSC3_PHCD_MASK)
+
+#define USBC_PORTSC3_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC3_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC3_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PFSC_SHIFT)) & USBC_PORTSC3_PFSC_MASK)
+
+#define USBC_PORTSC3_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC3_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC3_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTS2_SHIFT)) & USBC_PORTSC3_PTS2_MASK)
+
+#define USBC_PORTSC3_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC3_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC3_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PSPD_SHIFT)) & USBC_PORTSC3_PSPD_MASK)
+
+#define USBC_PORTSC3_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC3_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC3_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTW_SHIFT)) & USBC_PORTSC3_PTW_MASK)
+
+#define USBC_PORTSC3_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC3_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC3_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_STS_SHIFT)) & USBC_PORTSC3_STS_MASK)
+
+#define USBC_PORTSC3_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC3_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC3_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTS_SHIFT)) & USBC_PORTSC3_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC4 - PORTSC4 */
+/*! @{ */
+
+#define USBC_PORTSC4_CCS_MASK                    (0x1U)
+#define USBC_PORTSC4_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC4_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_CCS_SHIFT)) & USBC_PORTSC4_CCS_MASK)
+
+#define USBC_PORTSC4_CSC_MASK                    (0x2U)
+#define USBC_PORTSC4_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC4_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_CSC_SHIFT)) & USBC_PORTSC4_CSC_MASK)
+
+#define USBC_PORTSC4_PE_MASK                     (0x4U)
+#define USBC_PORTSC4_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC4_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PE_SHIFT)) & USBC_PORTSC4_PE_MASK)
+
+#define USBC_PORTSC4_PEC_MASK                    (0x8U)
+#define USBC_PORTSC4_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC4_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PEC_SHIFT)) & USBC_PORTSC4_PEC_MASK)
+
+#define USBC_PORTSC4_OCA_MASK                    (0x10U)
+#define USBC_PORTSC4_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC4_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_OCA_SHIFT)) & USBC_PORTSC4_OCA_MASK)
+
+#define USBC_PORTSC4_OCC_MASK                    (0x20U)
+#define USBC_PORTSC4_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC4_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_OCC_SHIFT)) & USBC_PORTSC4_OCC_MASK)
+
+#define USBC_PORTSC4_FPR_MASK                    (0x40U)
+#define USBC_PORTSC4_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC4_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_FPR_SHIFT)) & USBC_PORTSC4_FPR_MASK)
+
+#define USBC_PORTSC4_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC4_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC4_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_SUSP_SHIFT)) & USBC_PORTSC4_SUSP_MASK)
+
+#define USBC_PORTSC4_PR_MASK                     (0x100U)
+#define USBC_PORTSC4_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC4_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PR_SHIFT)) & USBC_PORTSC4_PR_MASK)
+
+#define USBC_PORTSC4_HSP_MASK                    (0x200U)
+#define USBC_PORTSC4_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC4_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_HSP_SHIFT)) & USBC_PORTSC4_HSP_MASK)
+
+#define USBC_PORTSC4_LS_MASK                     (0xC00U)
+#define USBC_PORTSC4_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC4_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_LS_SHIFT)) & USBC_PORTSC4_LS_MASK)
+
+#define USBC_PORTSC4_PP_MASK                     (0x1000U)
+#define USBC_PORTSC4_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC4_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PP_SHIFT)) & USBC_PORTSC4_PP_MASK)
+
+#define USBC_PORTSC4_PO_MASK                     (0x2000U)
+#define USBC_PORTSC4_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC4_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PO_SHIFT)) & USBC_PORTSC4_PO_MASK)
+
+#define USBC_PORTSC4_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC4_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC4_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PIC_SHIFT)) & USBC_PORTSC4_PIC_MASK)
+
+#define USBC_PORTSC4_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC4_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC4_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTC_SHIFT)) & USBC_PORTSC4_PTC_MASK)
+
+#define USBC_PORTSC4_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC4_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC4_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_WKCN_SHIFT)) & USBC_PORTSC4_WKCN_MASK)
+
+#define USBC_PORTSC4_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC4_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC4_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_WKDS_SHIFT)) & USBC_PORTSC4_WKDS_MASK)
+
+#define USBC_PORTSC4_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC4_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC4_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_WKOC_SHIFT)) & USBC_PORTSC4_WKOC_MASK)
+
+#define USBC_PORTSC4_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC4_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC4_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PHCD_SHIFT)) & USBC_PORTSC4_PHCD_MASK)
+
+#define USBC_PORTSC4_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC4_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC4_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PFSC_SHIFT)) & USBC_PORTSC4_PFSC_MASK)
+
+#define USBC_PORTSC4_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC4_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC4_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTS2_SHIFT)) & USBC_PORTSC4_PTS2_MASK)
+
+#define USBC_PORTSC4_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC4_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC4_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PSPD_SHIFT)) & USBC_PORTSC4_PSPD_MASK)
+
+#define USBC_PORTSC4_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC4_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC4_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTW_SHIFT)) & USBC_PORTSC4_PTW_MASK)
+
+#define USBC_PORTSC4_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC4_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC4_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_STS_SHIFT)) & USBC_PORTSC4_STS_MASK)
+
+#define USBC_PORTSC4_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC4_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC4_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTS_SHIFT)) & USBC_PORTSC4_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC5 - PORTSC5 */
+/*! @{ */
+
+#define USBC_PORTSC5_CCS_MASK                    (0x1U)
+#define USBC_PORTSC5_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC5_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_CCS_SHIFT)) & USBC_PORTSC5_CCS_MASK)
+
+#define USBC_PORTSC5_CSC_MASK                    (0x2U)
+#define USBC_PORTSC5_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC5_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_CSC_SHIFT)) & USBC_PORTSC5_CSC_MASK)
+
+#define USBC_PORTSC5_PE_MASK                     (0x4U)
+#define USBC_PORTSC5_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC5_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PE_SHIFT)) & USBC_PORTSC5_PE_MASK)
+
+#define USBC_PORTSC5_PEC_MASK                    (0x8U)
+#define USBC_PORTSC5_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC5_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PEC_SHIFT)) & USBC_PORTSC5_PEC_MASK)
+
+#define USBC_PORTSC5_OCA_MASK                    (0x10U)
+#define USBC_PORTSC5_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC5_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_OCA_SHIFT)) & USBC_PORTSC5_OCA_MASK)
+
+#define USBC_PORTSC5_OCC_MASK                    (0x20U)
+#define USBC_PORTSC5_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC5_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_OCC_SHIFT)) & USBC_PORTSC5_OCC_MASK)
+
+#define USBC_PORTSC5_FPR_MASK                    (0x40U)
+#define USBC_PORTSC5_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC5_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_FPR_SHIFT)) & USBC_PORTSC5_FPR_MASK)
+
+#define USBC_PORTSC5_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC5_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC5_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_SUSP_SHIFT)) & USBC_PORTSC5_SUSP_MASK)
+
+#define USBC_PORTSC5_PR_MASK                     (0x100U)
+#define USBC_PORTSC5_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC5_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PR_SHIFT)) & USBC_PORTSC5_PR_MASK)
+
+#define USBC_PORTSC5_HSP_MASK                    (0x200U)
+#define USBC_PORTSC5_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC5_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_HSP_SHIFT)) & USBC_PORTSC5_HSP_MASK)
+
+#define USBC_PORTSC5_LS_MASK                     (0xC00U)
+#define USBC_PORTSC5_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC5_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_LS_SHIFT)) & USBC_PORTSC5_LS_MASK)
+
+#define USBC_PORTSC5_PP_MASK                     (0x1000U)
+#define USBC_PORTSC5_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC5_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PP_SHIFT)) & USBC_PORTSC5_PP_MASK)
+
+#define USBC_PORTSC5_PO_MASK                     (0x2000U)
+#define USBC_PORTSC5_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC5_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PO_SHIFT)) & USBC_PORTSC5_PO_MASK)
+
+#define USBC_PORTSC5_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC5_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC5_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PIC_SHIFT)) & USBC_PORTSC5_PIC_MASK)
+
+#define USBC_PORTSC5_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC5_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC5_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTC_SHIFT)) & USBC_PORTSC5_PTC_MASK)
+
+#define USBC_PORTSC5_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC5_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC5_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_WKCN_SHIFT)) & USBC_PORTSC5_WKCN_MASK)
+
+#define USBC_PORTSC5_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC5_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC5_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_WKDS_SHIFT)) & USBC_PORTSC5_WKDS_MASK)
+
+#define USBC_PORTSC5_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC5_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC5_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_WKOC_SHIFT)) & USBC_PORTSC5_WKOC_MASK)
+
+#define USBC_PORTSC5_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC5_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC5_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PHCD_SHIFT)) & USBC_PORTSC5_PHCD_MASK)
+
+#define USBC_PORTSC5_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC5_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC5_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PFSC_SHIFT)) & USBC_PORTSC5_PFSC_MASK)
+
+#define USBC_PORTSC5_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC5_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC5_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTS2_SHIFT)) & USBC_PORTSC5_PTS2_MASK)
+
+#define USBC_PORTSC5_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC5_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC5_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PSPD_SHIFT)) & USBC_PORTSC5_PSPD_MASK)
+
+#define USBC_PORTSC5_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC5_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC5_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTW_SHIFT)) & USBC_PORTSC5_PTW_MASK)
+
+#define USBC_PORTSC5_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC5_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC5_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_STS_SHIFT)) & USBC_PORTSC5_STS_MASK)
+
+#define USBC_PORTSC5_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC5_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC5_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTS_SHIFT)) & USBC_PORTSC5_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC6 - PORTSC6 */
+/*! @{ */
+
+#define USBC_PORTSC6_CCS_MASK                    (0x1U)
+#define USBC_PORTSC6_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC6_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_CCS_SHIFT)) & USBC_PORTSC6_CCS_MASK)
+
+#define USBC_PORTSC6_CSC_MASK                    (0x2U)
+#define USBC_PORTSC6_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC6_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_CSC_SHIFT)) & USBC_PORTSC6_CSC_MASK)
+
+#define USBC_PORTSC6_PE_MASK                     (0x4U)
+#define USBC_PORTSC6_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC6_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PE_SHIFT)) & USBC_PORTSC6_PE_MASK)
+
+#define USBC_PORTSC6_PEC_MASK                    (0x8U)
+#define USBC_PORTSC6_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC6_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PEC_SHIFT)) & USBC_PORTSC6_PEC_MASK)
+
+#define USBC_PORTSC6_OCA_MASK                    (0x10U)
+#define USBC_PORTSC6_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC6_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_OCA_SHIFT)) & USBC_PORTSC6_OCA_MASK)
+
+#define USBC_PORTSC6_OCC_MASK                    (0x20U)
+#define USBC_PORTSC6_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC6_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_OCC_SHIFT)) & USBC_PORTSC6_OCC_MASK)
+
+#define USBC_PORTSC6_FPR_MASK                    (0x40U)
+#define USBC_PORTSC6_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC6_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_FPR_SHIFT)) & USBC_PORTSC6_FPR_MASK)
+
+#define USBC_PORTSC6_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC6_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC6_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_SUSP_SHIFT)) & USBC_PORTSC6_SUSP_MASK)
+
+#define USBC_PORTSC6_PR_MASK                     (0x100U)
+#define USBC_PORTSC6_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC6_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PR_SHIFT)) & USBC_PORTSC6_PR_MASK)
+
+#define USBC_PORTSC6_HSP_MASK                    (0x200U)
+#define USBC_PORTSC6_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC6_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_HSP_SHIFT)) & USBC_PORTSC6_HSP_MASK)
+
+#define USBC_PORTSC6_LS_MASK                     (0xC00U)
+#define USBC_PORTSC6_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC6_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_LS_SHIFT)) & USBC_PORTSC6_LS_MASK)
+
+#define USBC_PORTSC6_PP_MASK                     (0x1000U)
+#define USBC_PORTSC6_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC6_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PP_SHIFT)) & USBC_PORTSC6_PP_MASK)
+
+#define USBC_PORTSC6_PO_MASK                     (0x2000U)
+#define USBC_PORTSC6_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC6_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PO_SHIFT)) & USBC_PORTSC6_PO_MASK)
+
+#define USBC_PORTSC6_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC6_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC6_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PIC_SHIFT)) & USBC_PORTSC6_PIC_MASK)
+
+#define USBC_PORTSC6_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC6_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC6_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTC_SHIFT)) & USBC_PORTSC6_PTC_MASK)
+
+#define USBC_PORTSC6_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC6_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC6_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_WKCN_SHIFT)) & USBC_PORTSC6_WKCN_MASK)
+
+#define USBC_PORTSC6_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC6_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC6_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_WKDS_SHIFT)) & USBC_PORTSC6_WKDS_MASK)
+
+#define USBC_PORTSC6_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC6_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC6_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_WKOC_SHIFT)) & USBC_PORTSC6_WKOC_MASK)
+
+#define USBC_PORTSC6_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC6_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC6_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PHCD_SHIFT)) & USBC_PORTSC6_PHCD_MASK)
+
+#define USBC_PORTSC6_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC6_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC6_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PFSC_SHIFT)) & USBC_PORTSC6_PFSC_MASK)
+
+#define USBC_PORTSC6_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC6_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC6_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTS2_SHIFT)) & USBC_PORTSC6_PTS2_MASK)
+
+#define USBC_PORTSC6_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC6_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC6_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PSPD_SHIFT)) & USBC_PORTSC6_PSPD_MASK)
+
+#define USBC_PORTSC6_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC6_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC6_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTW_SHIFT)) & USBC_PORTSC6_PTW_MASK)
+
+#define USBC_PORTSC6_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC6_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC6_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_STS_SHIFT)) & USBC_PORTSC6_STS_MASK)
+
+#define USBC_PORTSC6_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC6_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC6_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTS_SHIFT)) & USBC_PORTSC6_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC7 - PORTSC7 */
+/*! @{ */
+
+#define USBC_PORTSC7_CCS_MASK                    (0x1U)
+#define USBC_PORTSC7_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC7_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_CCS_SHIFT)) & USBC_PORTSC7_CCS_MASK)
+
+#define USBC_PORTSC7_CSC_MASK                    (0x2U)
+#define USBC_PORTSC7_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC7_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_CSC_SHIFT)) & USBC_PORTSC7_CSC_MASK)
+
+#define USBC_PORTSC7_PE_MASK                     (0x4U)
+#define USBC_PORTSC7_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC7_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PE_SHIFT)) & USBC_PORTSC7_PE_MASK)
+
+#define USBC_PORTSC7_PEC_MASK                    (0x8U)
+#define USBC_PORTSC7_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC7_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PEC_SHIFT)) & USBC_PORTSC7_PEC_MASK)
+
+#define USBC_PORTSC7_OCA_MASK                    (0x10U)
+#define USBC_PORTSC7_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC7_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_OCA_SHIFT)) & USBC_PORTSC7_OCA_MASK)
+
+#define USBC_PORTSC7_OCC_MASK                    (0x20U)
+#define USBC_PORTSC7_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC7_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_OCC_SHIFT)) & USBC_PORTSC7_OCC_MASK)
+
+#define USBC_PORTSC7_FPR_MASK                    (0x40U)
+#define USBC_PORTSC7_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC7_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_FPR_SHIFT)) & USBC_PORTSC7_FPR_MASK)
+
+#define USBC_PORTSC7_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC7_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC7_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_SUSP_SHIFT)) & USBC_PORTSC7_SUSP_MASK)
+
+#define USBC_PORTSC7_PR_MASK                     (0x100U)
+#define USBC_PORTSC7_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC7_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PR_SHIFT)) & USBC_PORTSC7_PR_MASK)
+
+#define USBC_PORTSC7_HSP_MASK                    (0x200U)
+#define USBC_PORTSC7_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC7_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_HSP_SHIFT)) & USBC_PORTSC7_HSP_MASK)
+
+#define USBC_PORTSC7_LS_MASK                     (0xC00U)
+#define USBC_PORTSC7_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC7_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_LS_SHIFT)) & USBC_PORTSC7_LS_MASK)
+
+#define USBC_PORTSC7_PP_MASK                     (0x1000U)
+#define USBC_PORTSC7_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC7_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PP_SHIFT)) & USBC_PORTSC7_PP_MASK)
+
+#define USBC_PORTSC7_PO_MASK                     (0x2000U)
+#define USBC_PORTSC7_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC7_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PO_SHIFT)) & USBC_PORTSC7_PO_MASK)
+
+#define USBC_PORTSC7_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC7_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC7_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PIC_SHIFT)) & USBC_PORTSC7_PIC_MASK)
+
+#define USBC_PORTSC7_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC7_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC7_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTC_SHIFT)) & USBC_PORTSC7_PTC_MASK)
+
+#define USBC_PORTSC7_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC7_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC7_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_WKCN_SHIFT)) & USBC_PORTSC7_WKCN_MASK)
+
+#define USBC_PORTSC7_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC7_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC7_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_WKDS_SHIFT)) & USBC_PORTSC7_WKDS_MASK)
+
+#define USBC_PORTSC7_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC7_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC7_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_WKOC_SHIFT)) & USBC_PORTSC7_WKOC_MASK)
+
+#define USBC_PORTSC7_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC7_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC7_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PHCD_SHIFT)) & USBC_PORTSC7_PHCD_MASK)
+
+#define USBC_PORTSC7_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC7_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC7_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PFSC_SHIFT)) & USBC_PORTSC7_PFSC_MASK)
+
+#define USBC_PORTSC7_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC7_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC7_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTS2_SHIFT)) & USBC_PORTSC7_PTS2_MASK)
+
+#define USBC_PORTSC7_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC7_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC7_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PSPD_SHIFT)) & USBC_PORTSC7_PSPD_MASK)
+
+#define USBC_PORTSC7_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC7_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC7_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTW_SHIFT)) & USBC_PORTSC7_PTW_MASK)
+
+#define USBC_PORTSC7_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC7_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC7_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_STS_SHIFT)) & USBC_PORTSC7_STS_MASK)
+
+#define USBC_PORTSC7_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC7_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC7_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTS_SHIFT)) & USBC_PORTSC7_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC8 - PORTSC8 */
+/*! @{ */
+
+#define USBC_PORTSC8_CCS_MASK                    (0x1U)
+#define USBC_PORTSC8_CCS_SHIFT                   (0U)
+/*! CCS - CCS */
+#define USBC_PORTSC8_CCS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_CCS_SHIFT)) & USBC_PORTSC8_CCS_MASK)
+
+#define USBC_PORTSC8_CSC_MASK                    (0x2U)
+#define USBC_PORTSC8_CSC_SHIFT                   (1U)
+/*! CSC - rwc */
+#define USBC_PORTSC8_CSC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_CSC_SHIFT)) & USBC_PORTSC8_CSC_MASK)
+
+#define USBC_PORTSC8_PE_MASK                     (0x4U)
+#define USBC_PORTSC8_PE_SHIFT                    (2U)
+/*! PE - rwc */
+#define USBC_PORTSC8_PE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PE_SHIFT)) & USBC_PORTSC8_PE_MASK)
+
+#define USBC_PORTSC8_PEC_MASK                    (0x8U)
+#define USBC_PORTSC8_PEC_SHIFT                   (3U)
+/*! PEC - rwc */
+#define USBC_PORTSC8_PEC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PEC_SHIFT)) & USBC_PORTSC8_PEC_MASK)
+
+#define USBC_PORTSC8_OCA_MASK                    (0x10U)
+#define USBC_PORTSC8_OCA_SHIFT                   (4U)
+/*! OCA - OCA */
+#define USBC_PORTSC8_OCA(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_OCA_SHIFT)) & USBC_PORTSC8_OCA_MASK)
+
+#define USBC_PORTSC8_OCC_MASK                    (0x20U)
+#define USBC_PORTSC8_OCC_SHIFT                   (5U)
+/*! OCC - OCC */
+#define USBC_PORTSC8_OCC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_OCC_SHIFT)) & USBC_PORTSC8_OCC_MASK)
+
+#define USBC_PORTSC8_FPR_MASK                    (0x40U)
+#define USBC_PORTSC8_FPR_SHIFT                   (6U)
+/*! FPR - FPR */
+#define USBC_PORTSC8_FPR(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_FPR_SHIFT)) & USBC_PORTSC8_FPR_MASK)
+
+#define USBC_PORTSC8_SUSP_MASK                   (0x80U)
+#define USBC_PORTSC8_SUSP_SHIFT                  (7U)
+/*! SUSP - SUSP */
+#define USBC_PORTSC8_SUSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_SUSP_SHIFT)) & USBC_PORTSC8_SUSP_MASK)
+
+#define USBC_PORTSC8_PR_MASK                     (0x100U)
+#define USBC_PORTSC8_PR_SHIFT                    (8U)
+/*! PR - PR */
+#define USBC_PORTSC8_PR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PR_SHIFT)) & USBC_PORTSC8_PR_MASK)
+
+#define USBC_PORTSC8_HSP_MASK                    (0x200U)
+#define USBC_PORTSC8_HSP_SHIFT                   (9U)
+/*! HSP - HSP */
+#define USBC_PORTSC8_HSP(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_HSP_SHIFT)) & USBC_PORTSC8_HSP_MASK)
+
+#define USBC_PORTSC8_LS_MASK                     (0xC00U)
+#define USBC_PORTSC8_LS_SHIFT                    (10U)
+/*! LS - LS */
+#define USBC_PORTSC8_LS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_LS_SHIFT)) & USBC_PORTSC8_LS_MASK)
+
+#define USBC_PORTSC8_PP_MASK                     (0x1000U)
+#define USBC_PORTSC8_PP_SHIFT                    (12U)
+/*! PP - PP */
+#define USBC_PORTSC8_PP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PP_SHIFT)) & USBC_PORTSC8_PP_MASK)
+
+#define USBC_PORTSC8_PO_MASK                     (0x2000U)
+#define USBC_PORTSC8_PO_SHIFT                    (13U)
+/*! PO - PO */
+#define USBC_PORTSC8_PO(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PO_SHIFT)) & USBC_PORTSC8_PO_MASK)
+
+#define USBC_PORTSC8_PIC_MASK                    (0xC000U)
+#define USBC_PORTSC8_PIC_SHIFT                   (14U)
+/*! PIC - PIC */
+#define USBC_PORTSC8_PIC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PIC_SHIFT)) & USBC_PORTSC8_PIC_MASK)
+
+#define USBC_PORTSC8_PTC_MASK                    (0xF0000U)
+#define USBC_PORTSC8_PTC_SHIFT                   (16U)
+/*! PTC - PTC */
+#define USBC_PORTSC8_PTC(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTC_SHIFT)) & USBC_PORTSC8_PTC_MASK)
+
+#define USBC_PORTSC8_WKCN_MASK                   (0x100000U)
+#define USBC_PORTSC8_WKCN_SHIFT                  (20U)
+/*! WKCN - WKCN */
+#define USBC_PORTSC8_WKCN(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_WKCN_SHIFT)) & USBC_PORTSC8_WKCN_MASK)
+
+#define USBC_PORTSC8_WKDS_MASK                   (0x200000U)
+#define USBC_PORTSC8_WKDS_SHIFT                  (21U)
+/*! WKDS - WKDS */
+#define USBC_PORTSC8_WKDS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_WKDS_SHIFT)) & USBC_PORTSC8_WKDS_MASK)
+
+#define USBC_PORTSC8_WKOC_MASK                   (0x400000U)
+#define USBC_PORTSC8_WKOC_SHIFT                  (22U)
+/*! WKOC - WKOC */
+#define USBC_PORTSC8_WKOC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_WKOC_SHIFT)) & USBC_PORTSC8_WKOC_MASK)
+
+#define USBC_PORTSC8_PHCD_MASK                   (0x800000U)
+#define USBC_PORTSC8_PHCD_SHIFT                  (23U)
+/*! PHCD - PHCD */
+#define USBC_PORTSC8_PHCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PHCD_SHIFT)) & USBC_PORTSC8_PHCD_MASK)
+
+#define USBC_PORTSC8_PFSC_MASK                   (0x1000000U)
+#define USBC_PORTSC8_PFSC_SHIFT                  (24U)
+/*! PFSC - PFSC */
+#define USBC_PORTSC8_PFSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PFSC_SHIFT)) & USBC_PORTSC8_PFSC_MASK)
+
+#define USBC_PORTSC8_PTS2_MASK                   (0x2000000U)
+#define USBC_PORTSC8_PTS2_SHIFT                  (25U)
+/*! PTS2 - PTS2 */
+#define USBC_PORTSC8_PTS2(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTS2_SHIFT)) & USBC_PORTSC8_PTS2_MASK)
+
+#define USBC_PORTSC8_PSPD_MASK                   (0xC000000U)
+#define USBC_PORTSC8_PSPD_SHIFT                  (26U)
+/*! PSPD - PSPD */
+#define USBC_PORTSC8_PSPD(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PSPD_SHIFT)) & USBC_PORTSC8_PSPD_MASK)
+
+#define USBC_PORTSC8_PTW_MASK                    (0x10000000U)
+#define USBC_PORTSC8_PTW_SHIFT                   (28U)
+/*! PTW - PTW */
+#define USBC_PORTSC8_PTW(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTW_SHIFT)) & USBC_PORTSC8_PTW_MASK)
+
+#define USBC_PORTSC8_STS_MASK                    (0x20000000U)
+#define USBC_PORTSC8_STS_SHIFT                   (29U)
+/*! STS - STS */
+#define USBC_PORTSC8_STS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_STS_SHIFT)) & USBC_PORTSC8_STS_MASK)
+
+#define USBC_PORTSC8_PTS_MASK                    (0xC0000000U)
+#define USBC_PORTSC8_PTS_SHIFT                   (30U)
+/*! PTS - PTS */
+#define USBC_PORTSC8_PTS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTS_SHIFT)) & USBC_PORTSC8_PTS_MASK)
+/*! @} */
+
+/*! @name OTGSC - OTGSC */
+/*! @{ */
+
+#define USBC_OTGSC_VD_MASK                       (0x1U)
+#define USBC_OTGSC_VD_SHIFT                      (0U)
+/*! VD - OTG not enable */
+#define USBC_OTGSC_VD(x)                         (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_VD_SHIFT)) & USBC_OTGSC_VD_MASK)
+
+#define USBC_OTGSC_VC_MASK                       (0x2U)
+#define USBC_OTGSC_VC_SHIFT                      (1U)
+/*! VC - OTG not enable */
+#define USBC_OTGSC_VC(x)                         (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_VC_SHIFT)) & USBC_OTGSC_VC_MASK)
+
+#define USBC_OTGSC_HAAR_MASK                     (0x4U)
+#define USBC_OTGSC_HAAR_SHIFT                    (2U)
+/*! HAAR - OTG not enable */
+#define USBC_OTGSC_HAAR(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_HAAR_SHIFT)) & USBC_OTGSC_HAAR_MASK)
+
+#define USBC_OTGSC_OT_MASK                       (0x8U)
+#define USBC_OTGSC_OT_SHIFT                      (3U)
+/*! OT - OTG not enable */
+#define USBC_OTGSC_OT(x)                         (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OT_SHIFT)) & USBC_OTGSC_OT_MASK)
+
+#define USBC_OTGSC_DP_MASK                       (0x10U)
+#define USBC_OTGSC_DP_SHIFT                      (4U)
+/*! DP - OTG not enable */
+#define USBC_OTGSC_DP(x)                         (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DP_SHIFT)) & USBC_OTGSC_DP_MASK)
+
+#define USBC_OTGSC_IDPU_MASK                     (0x20U)
+#define USBC_OTGSC_IDPU_SHIFT                    (5U)
+/*! IDPU - OTG not enable */
+#define USBC_OTGSC_IDPU(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_IDPU_SHIFT)) & USBC_OTGSC_IDPU_MASK)
+
+#define USBC_OTGSC_HADP_MASK                     (0x40U)
+#define USBC_OTGSC_HADP_SHIFT                    (6U)
+/*! HADP - OTG not enable */
+#define USBC_OTGSC_HADP(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_HADP_SHIFT)) & USBC_OTGSC_HADP_MASK)
+
+#define USBC_OTGSC_HABA_MASK                     (0x80U)
+#define USBC_OTGSC_HABA_SHIFT                    (7U)
+/*! HABA - OTG not enable */
+#define USBC_OTGSC_HABA(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_HABA_SHIFT)) & USBC_OTGSC_HABA_MASK)
+
+#define USBC_OTGSC_ID_MASK                       (0x100U)
+#define USBC_OTGSC_ID_SHIFT                      (8U)
+/*! ID - OTG not enable */
+#define USBC_OTGSC_ID(x)                         (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ID_SHIFT)) & USBC_OTGSC_ID_MASK)
+
+#define USBC_OTGSC_AVV_MASK                      (0x200U)
+#define USBC_OTGSC_AVV_SHIFT                     (9U)
+/*! AVV - OTG not enable */
+#define USBC_OTGSC_AVV(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_AVV_SHIFT)) & USBC_OTGSC_AVV_MASK)
+
+#define USBC_OTGSC_ASV_MASK                      (0x400U)
+#define USBC_OTGSC_ASV_SHIFT                     (10U)
+/*! ASV - OTG not enable */
+#define USBC_OTGSC_ASV(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ASV_SHIFT)) & USBC_OTGSC_ASV_MASK)
+
+#define USBC_OTGSC_BSV_MASK                      (0x800U)
+#define USBC_OTGSC_BSV_SHIFT                     (11U)
+/*! BSV - OTG not enable */
+#define USBC_OTGSC_BSV(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSV_SHIFT)) & USBC_OTGSC_BSV_MASK)
+
+#define USBC_OTGSC_BSE_MASK                      (0x1000U)
+#define USBC_OTGSC_BSE_SHIFT                     (12U)
+/*! BSE - OTG not enable */
+#define USBC_OTGSC_BSE(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSE_SHIFT)) & USBC_OTGSC_BSE_MASK)
+
+#define USBC_OTGSC_OTGSC_1MST_MASK               (0x2000U)
+#define USBC_OTGSC_OTGSC_1MST_SHIFT              (13U)
+/*! OTGSC_1MST - OTG not enable */
+#define USBC_OTGSC_OTGSC_1MST(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OTGSC_1MST_SHIFT)) & USBC_OTGSC_OTGSC_1MST_MASK)
+
+#define USBC_OTGSC_DPS_MASK                      (0x4000U)
+#define USBC_OTGSC_DPS_SHIFT                     (14U)
+/*! DPS - OTG not enable */
+#define USBC_OTGSC_DPS(x)                        (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DPS_SHIFT)) & USBC_OTGSC_DPS_MASK)
+
+#define USBC_OTGSC_UNUSED_15_MASK                (0x8000U)
+#define USBC_OTGSC_UNUSED_15_SHIFT               (15U)
+/*! UNUSED_15 - OTG not enable */
+#define USBC_OTGSC_UNUSED_15(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_UNUSED_15_SHIFT)) & USBC_OTGSC_UNUSED_15_MASK)
+
+#define USBC_OTGSC_IDIS_MASK                     (0x10000U)
+#define USBC_OTGSC_IDIS_SHIFT                    (16U)
+/*! IDIS - rwc */
+#define USBC_OTGSC_IDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_IDIS_SHIFT)) & USBC_OTGSC_IDIS_MASK)
+
+#define USBC_OTGSC_AVVIS_MASK                    (0x20000U)
+#define USBC_OTGSC_AVVIS_SHIFT                   (17U)
+/*! AVVIS - rwc */
+#define USBC_OTGSC_AVVIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_AVVIS_SHIFT)) & USBC_OTGSC_AVVIS_MASK)
+
+#define USBC_OTGSC_ASVIS_MASK                    (0x40000U)
+#define USBC_OTGSC_ASVIS_SHIFT                   (18U)
+/*! ASVIS - rwc */
+#define USBC_OTGSC_ASVIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ASVIS_SHIFT)) & USBC_OTGSC_ASVIS_MASK)
+
+#define USBC_OTGSC_BSVIS_MASK                    (0x80000U)
+#define USBC_OTGSC_BSVIS_SHIFT                   (19U)
+/*! BSVIS - rwc */
+#define USBC_OTGSC_BSVIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSVIS_SHIFT)) & USBC_OTGSC_BSVIS_MASK)
+
+#define USBC_OTGSC_BSEIS_MASK                    (0x100000U)
+#define USBC_OTGSC_BSEIS_SHIFT                   (20U)
+/*! BSEIS - rwc */
+#define USBC_OTGSC_BSEIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSEIS_SHIFT)) & USBC_OTGSC_BSEIS_MASK)
+
+#define USBC_OTGSC_OTGSC_1MSS_MASK               (0x200000U)
+#define USBC_OTGSC_OTGSC_1MSS_SHIFT              (21U)
+/*! OTGSC_1MSS - rwc */
+#define USBC_OTGSC_OTGSC_1MSS(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OTGSC_1MSS_SHIFT)) & USBC_OTGSC_OTGSC_1MSS_MASK)
+
+#define USBC_OTGSC_DPIS_MASK                     (0x400000U)
+#define USBC_OTGSC_DPIS_SHIFT                    (22U)
+/*! DPIS - rwc */
+#define USBC_OTGSC_DPIS(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DPIS_SHIFT)) & USBC_OTGSC_DPIS_MASK)
+
+#define USBC_OTGSC_UNUSED_23_MASK                (0x800000U)
+#define USBC_OTGSC_UNUSED_23_SHIFT               (23U)
+/*! UNUSED_23 - OTG not enable */
+#define USBC_OTGSC_UNUSED_23(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_UNUSED_23_SHIFT)) & USBC_OTGSC_UNUSED_23_MASK)
+
+#define USBC_OTGSC_IDIE_MASK                     (0x1000000U)
+#define USBC_OTGSC_IDIE_SHIFT                    (24U)
+/*! IDIE - OTG not enable */
+#define USBC_OTGSC_IDIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_IDIE_SHIFT)) & USBC_OTGSC_IDIE_MASK)
+
+#define USBC_OTGSC_AVVIE_MASK                    (0x2000000U)
+#define USBC_OTGSC_AVVIE_SHIFT                   (25U)
+/*! AVVIE - OTG not enable */
+#define USBC_OTGSC_AVVIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_AVVIE_SHIFT)) & USBC_OTGSC_AVVIE_MASK)
+
+#define USBC_OTGSC_ASVIE_MASK                    (0x4000000U)
+#define USBC_OTGSC_ASVIE_SHIFT                   (26U)
+/*! ASVIE - OTG not enable */
+#define USBC_OTGSC_ASVIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ASVIE_SHIFT)) & USBC_OTGSC_ASVIE_MASK)
+
+#define USBC_OTGSC_BSVIE_MASK                    (0x8000000U)
+#define USBC_OTGSC_BSVIE_SHIFT                   (27U)
+/*! BSVIE - OTG not enable */
+#define USBC_OTGSC_BSVIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSVIE_SHIFT)) & USBC_OTGSC_BSVIE_MASK)
+
+#define USBC_OTGSC_BSEIE_MASK                    (0x10000000U)
+#define USBC_OTGSC_BSEIE_SHIFT                   (28U)
+/*! BSEIE - OTG not enable */
+#define USBC_OTGSC_BSEIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSEIE_SHIFT)) & USBC_OTGSC_BSEIE_MASK)
+
+#define USBC_OTGSC_OTGSC_1MSE_MASK               (0x20000000U)
+#define USBC_OTGSC_OTGSC_1MSE_SHIFT              (29U)
+/*! OTGSC_1MSE - OTG not enable */
+#define USBC_OTGSC_OTGSC_1MSE(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OTGSC_1MSE_SHIFT)) & USBC_OTGSC_OTGSC_1MSE_MASK)
+
+#define USBC_OTGSC_DPIE_MASK                     (0x40000000U)
+#define USBC_OTGSC_DPIE_SHIFT                    (30U)
+/*! DPIE - OTG not enable */
+#define USBC_OTGSC_DPIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DPIE_SHIFT)) & USBC_OTGSC_DPIE_MASK)
+
+#define USBC_OTGSC_UNUSED_31_MASK                (0x80000000U)
+#define USBC_OTGSC_UNUSED_31_SHIFT               (31U)
+/*! UNUSED_31 - OTG not enable */
+#define USBC_OTGSC_UNUSED_31(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_UNUSED_31_SHIFT)) & USBC_OTGSC_UNUSED_31_MASK)
+/*! @} */
+
+/*! @name USBMODE - USBMODE */
+/*! @{ */
+
+#define USBC_USBMODE_CM_MASK                     (0x3U)
+#define USBC_USBMODE_CM_SHIFT                    (0U)
+/*! CM - fix device mode */
+#define USBC_USBMODE_CM(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_CM_SHIFT)) & USBC_USBMODE_CM_MASK)
+
+#define USBC_USBMODE_ES_MASK                     (0x4U)
+#define USBC_USBMODE_ES_SHIFT                    (2U)
+/*! ES - ES */
+#define USBC_USBMODE_ES(x)                       (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_ES_SHIFT)) & USBC_USBMODE_ES_MASK)
+
+#define USBC_USBMODE_SLOM_MASK                   (0x8U)
+#define USBC_USBMODE_SLOM_SHIFT                  (3U)
+/*! SLOM - SLOM */
+#define USBC_USBMODE_SLOM(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_SLOM_SHIFT)) & USBC_USBMODE_SLOM_MASK)
+
+#define USBC_USBMODE_SDIS_MASK                   (0x10U)
+#define USBC_USBMODE_SDIS_SHIFT                  (4U)
+/*! SDIS - SDIS */
+#define USBC_USBMODE_SDIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_SDIS_SHIFT)) & USBC_USBMODE_SDIS_MASK)
+
+#define USBC_USBMODE_VBPS_MASK                   (0x20U)
+#define USBC_USBMODE_VBPS_SHIFT                  (5U)
+/*! VBPS - Only used in Host */
+#define USBC_USBMODE_VBPS(x)                     (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_VBPS_SHIFT)) & USBC_USBMODE_VBPS_MASK)
+
+#define USBC_USBMODE_UNUSED_6_MASK               (0xFC0U)
+#define USBC_USBMODE_UNUSED_6_SHIFT              (6U)
+/*! UNUSED_6 - UNUSED_6 */
+#define USBC_USBMODE_UNUSED_6(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_UNUSED_6_SHIFT)) & USBC_USBMODE_UNUSED_6_MASK)
+
+#define USBC_USBMODE_TXHSD_MASK                  (0x7000U)
+#define USBC_USBMODE_TXHSD_SHIFT                 (12U)
+/*! TXHSD - TXHSD */
+#define USBC_USBMODE_TXHSD(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_TXHSD_SHIFT)) & USBC_USBMODE_TXHSD_MASK)
+
+#define USBC_USBMODE_SRT_MASK                    (0x8000U)
+#define USBC_USBMODE_SRT_SHIFT                   (15U)
+/*! SRT - SRT */
+#define USBC_USBMODE_SRT(x)                      (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_SRT_SHIFT)) & USBC_USBMODE_SRT_MASK)
+
+#define USBC_USBMODE_UNUSED_16_MASK              (0xFFFF0000U)
+#define USBC_USBMODE_UNUSED_16_SHIFT             (16U)
+/*! UNUSED_16 - UNUSED_16 */
+#define USBC_USBMODE_UNUSED_16(x)                (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_UNUSED_16_SHIFT)) & USBC_USBMODE_UNUSED_16_MASK)
+/*! @} */
+
+/*! @name ENDPTSETUPSTAT - ENDPTSETUPSTAT */
+/*! @{ */
+
+#define USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK  (0xFFFFU)
+#define USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
+/*! ENDPTSETUPSTAT - rwc */
+#define USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
+
+#define USBC_ENDPTSETUPSTAT_UNUSED_16_MASK       (0xFFFF0000U)
+#define USBC_ENDPTSETUPSTAT_UNUSED_16_SHIFT      (16U)
+/*! UNUSED_16 - UNUSED_16 */
+#define USBC_ENDPTSETUPSTAT_UNUSED_16(x)         (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSETUPSTAT_UNUSED_16_SHIFT)) & USBC_ENDPTSETUPSTAT_UNUSED_16_MASK)
+/*! @} */
+
+/*! @name ENDPTPRIME - ENDPTPRIME */
+/*! @{ */
+
+#define USBC_ENDPTPRIME_PERB_MASK                (0xFFFFU)
+#define USBC_ENDPTPRIME_PERB_SHIFT               (0U)
+/*! PERB - rws */
+#define USBC_ENDPTPRIME_PERB(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTPRIME_PERB_SHIFT)) & USBC_ENDPTPRIME_PERB_MASK)
+
+#define USBC_ENDPTPRIME_PETB_MASK                (0xFFFF0000U)
+#define USBC_ENDPTPRIME_PETB_SHIFT               (16U)
+/*! PETB - rws */
+#define USBC_ENDPTPRIME_PETB(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTPRIME_PETB_SHIFT)) & USBC_ENDPTPRIME_PETB_MASK)
+/*! @} */
+
+/*! @name ENDPTFLUSH - ENDPTFLUSH */
+/*! @{ */
+
+#define USBC_ENDPTFLUSH_FERB_MASK                (0xFFFFU)
+#define USBC_ENDPTFLUSH_FERB_SHIFT               (0U)
+/*! FERB - rws */
+#define USBC_ENDPTFLUSH_FERB(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTFLUSH_FERB_SHIFT)) & USBC_ENDPTFLUSH_FERB_MASK)
+
+#define USBC_ENDPTFLUSH_FETB_MASK                (0xFFFF0000U)
+#define USBC_ENDPTFLUSH_FETB_SHIFT               (16U)
+/*! FETB - rws */
+#define USBC_ENDPTFLUSH_FETB(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTFLUSH_FETB_SHIFT)) & USBC_ENDPTFLUSH_FETB_MASK)
+/*! @} */
+
+/*! @name ENDPTSTAT - ENDPTSTAT */
+/*! @{ */
+
+#define USBC_ENDPTSTAT_ERBR_MASK                 (0xFFFFU)
+#define USBC_ENDPTSTAT_ERBR_SHIFT                (0U)
+/*! ERBR - ERBR */
+#define USBC_ENDPTSTAT_ERBR(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSTAT_ERBR_SHIFT)) & USBC_ENDPTSTAT_ERBR_MASK)
+
+#define USBC_ENDPTSTAT_ETBR_MASK                 (0xFFFF0000U)
+#define USBC_ENDPTSTAT_ETBR_SHIFT                (16U)
+/*! ETBR - ETBR */
+#define USBC_ENDPTSTAT_ETBR(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSTAT_ETBR_SHIFT)) & USBC_ENDPTSTAT_ETBR_MASK)
+/*! @} */
+
+/*! @name ENDPTCOMPLETE - ENDPTCOMPLETE */
+/*! @{ */
+
+#define USBC_ENDPTCOMPLETE_ERCE_MASK             (0xFFFFU)
+#define USBC_ENDPTCOMPLETE_ERCE_SHIFT            (0U)
+/*! ERCE - rwc */
+#define USBC_ENDPTCOMPLETE_ERCE(x)               (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCOMPLETE_ERCE_SHIFT)) & USBC_ENDPTCOMPLETE_ERCE_MASK)
+
+#define USBC_ENDPTCOMPLETE_ETCE_MASK             (0xFFFF0000U)
+#define USBC_ENDPTCOMPLETE_ETCE_SHIFT            (16U)
+/*! ETCE - rwc */
+#define USBC_ENDPTCOMPLETE_ETCE(x)               (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCOMPLETE_ETCE_SHIFT)) & USBC_ENDPTCOMPLETE_ETCE_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL0 - ENDPTCTRL0 */
+/*! @{ */
+
+#define USBC_ENDPTCTRL0_RXS_MASK                 (0x1U)
+#define USBC_ENDPTCTRL0_RXS_SHIFT                (0U)
+/*! RXS - RXS */
+#define USBC_ENDPTCTRL0_RXS(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RXS_SHIFT)) & USBC_ENDPTCTRL0_RXS_MASK)
+
+#define USBC_ENDPTCTRL0_UNUSED_1_MASK            (0x2U)
+#define USBC_ENDPTCTRL0_UNUSED_1_SHIFT           (1U)
+/*! UNUSED_1 - UNUSED_1 */
+#define USBC_ENDPTCTRL0_UNUSED_1(x)              (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_UNUSED_1_SHIFT)) & USBC_ENDPTCTRL0_UNUSED_1_MASK)
+
+#define USBC_ENDPTCTRL0_RXT_MASK                 (0xCU)
+#define USBC_ENDPTCTRL0_RXT_SHIFT                (2U)
+/*! RXT - RXT */
+#define USBC_ENDPTCTRL0_RXT(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RXT_SHIFT)) & USBC_ENDPTCTRL0_RXT_MASK)
+
+#define USBC_ENDPTCTRL0_UNUSED_4_MASK            (0x70U)
+#define USBC_ENDPTCTRL0_UNUSED_4_SHIFT           (4U)
+/*! UNUSED_4 - UNUSED_4 */
+#define USBC_ENDPTCTRL0_UNUSED_4(x)              (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_UNUSED_4_SHIFT)) & USBC_ENDPTCTRL0_UNUSED_4_MASK)
+
+#define USBC_ENDPTCTRL0_RXE_MASK                 (0x80U)
+#define USBC_ENDPTCTRL0_RXE_SHIFT                (7U)
+/*! RXE - RXE */
+#define USBC_ENDPTCTRL0_RXE(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RXE_SHIFT)) & USBC_ENDPTCTRL0_RXE_MASK)
+
+#define USBC_ENDPTCTRL0_UNUSED_8_MASK            (0xFF00U)
+#define USBC_ENDPTCTRL0_UNUSED_8_SHIFT           (8U)
+/*! UNUSED_8 - UNUSED_8 */
+#define USBC_ENDPTCTRL0_UNUSED_8(x)              (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_UNUSED_8_SHIFT)) & USBC_ENDPTCTRL0_UNUSED_8_MASK)
+
+#define USBC_ENDPTCTRL0_TXS_MASK                 (0x10000U)
+#define USBC_ENDPTCTRL0_TXS_SHIFT                (16U)
+/*! TXS - TXS */
+#define USBC_ENDPTCTRL0_TXS(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_TXS_SHIFT)) & USBC_ENDPTCTRL0_TXS_MASK)
+
+#define USBC_ENDPTCTRL0_UNUSED_17_MASK           (0x20000U)
+#define USBC_ENDPTCTRL0_UNUSED_17_SHIFT          (17U)
+/*! UNUSED_17 - UNUSED_17 */
+#define USBC_ENDPTCTRL0_UNUSED_17(x)             (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_UNUSED_17_SHIFT)) & USBC_ENDPTCTRL0_UNUSED_17_MASK)
+
+#define USBC_ENDPTCTRL0_TXT_MASK                 (0xC0000U)
+#define USBC_ENDPTCTRL0_TXT_SHIFT                (18U)
+/*! TXT - TXT */
+#define USBC_ENDPTCTRL0_TXT(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_TXT_SHIFT)) & USBC_ENDPTCTRL0_TXT_MASK)
+
+#define USBC_ENDPTCTRL0_UNUSED_20_MASK           (0x700000U)
+#define USBC_ENDPTCTRL0_UNUSED_20_SHIFT          (20U)
+/*! UNUSED_20 - UNUSED_20 */
+#define USBC_ENDPTCTRL0_UNUSED_20(x)             (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_UNUSED_20_SHIFT)) & USBC_ENDPTCTRL0_UNUSED_20_MASK)
+
+#define USBC_ENDPTCTRL0_TXE_MASK                 (0x800000U)
+#define USBC_ENDPTCTRL0_TXE_SHIFT                (23U)
+/*! TXE - TXE */
+#define USBC_ENDPTCTRL0_TXE(x)                   (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_TXE_SHIFT)) & USBC_ENDPTCTRL0_TXE_MASK)
+
+#define USBC_ENDPTCTRL0_UNUSED_24_MASK           (0xFF000000U)
+#define USBC_ENDPTCTRL0_UNUSED_24_SHIFT          (24U)
+/*! UNUSED_24 - UNUSED_24 */
+#define USBC_ENDPTCTRL0_UNUSED_24(x)             (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_UNUSED_24_SHIFT)) & USBC_ENDPTCTRL0_UNUSED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL - ENDPTCTRL1..ENDPTCTRL15 */
+/*! @{ */
+
+#define USBC_ENDPTCTRL_RXS_MASK                  (0x1U)
+#define USBC_ENDPTCTRL_RXS_SHIFT                 (0U)
+/*! RXS - RXS */
+#define USBC_ENDPTCTRL_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_RXS_SHIFT)) & USBC_ENDPTCTRL_RXS_MASK)
+
+#define USBC_ENDPTCTRL_RXD_MASK                  (0x2U)
+#define USBC_ENDPTCTRL_RXD_SHIFT                 (1U)
+/*! RXD - RXD */
+#define USBC_ENDPTCTRL_RXD(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_RXD_SHIFT)) & USBC_ENDPTCTRL_RXD_MASK)
+
+#define USBC_ENDPTCTRL_RXT_MASK                  (0xCU)
+#define USBC_ENDPTCTRL_RXT_SHIFT                 (2U)
+/*! RXT - RXT */
+#define USBC_ENDPTCTRL_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_RXT_SHIFT)) & USBC_ENDPTCTRL_RXT_MASK)
+
+#define USBC_ENDPTCTRL_UNUSED_4_MASK             (0x10U)
+#define USBC_ENDPTCTRL_UNUSED_4_SHIFT            (4U)
+/*! UNUSED_4 - UNUSED_4 */
+#define USBC_ENDPTCTRL_UNUSED_4(x)               (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_UNUSED_4_SHIFT)) & USBC_ENDPTCTRL_UNUSED_4_MASK)
+
+#define USBC_ENDPTCTRL_RXI_MASK                  (0x20U)
+#define USBC_ENDPTCTRL_RXI_SHIFT                 (5U)
+/*! RXI - RXI */
+#define USBC_ENDPTCTRL_RXI(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_RXI_SHIFT)) & USBC_ENDPTCTRL_RXI_MASK)
+
+#define USBC_ENDPTCTRL_RXR_MASK                  (0x40U)
+#define USBC_ENDPTCTRL_RXR_SHIFT                 (6U)
+/*! RXR - ws */
+#define USBC_ENDPTCTRL_RXR(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_RXR_SHIFT)) & USBC_ENDPTCTRL_RXR_MASK)
+
+#define USBC_ENDPTCTRL_RXE_MASK                  (0x80U)
+#define USBC_ENDPTCTRL_RXE_SHIFT                 (7U)
+/*! RXE - RXE */
+#define USBC_ENDPTCTRL_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_RXE_SHIFT)) & USBC_ENDPTCTRL_RXE_MASK)
+
+#define USBC_ENDPTCTRL_UNUSED_8_MASK             (0xFF00U)
+#define USBC_ENDPTCTRL_UNUSED_8_SHIFT            (8U)
+/*! UNUSED_8 - UNUSED_8 */
+#define USBC_ENDPTCTRL_UNUSED_8(x)               (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_UNUSED_8_SHIFT)) & USBC_ENDPTCTRL_UNUSED_8_MASK)
+
+#define USBC_ENDPTCTRL_TXS_MASK                  (0x10000U)
+#define USBC_ENDPTCTRL_TXS_SHIFT                 (16U)
+/*! TXS - TXS */
+#define USBC_ENDPTCTRL_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_TXS_SHIFT)) & USBC_ENDPTCTRL_TXS_MASK)
+
+#define USBC_ENDPTCTRL_TXD_MASK                  (0x20000U)
+#define USBC_ENDPTCTRL_TXD_SHIFT                 (17U)
+/*! TXD - TXD */
+#define USBC_ENDPTCTRL_TXD(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_TXD_SHIFT)) & USBC_ENDPTCTRL_TXD_MASK)
+
+#define USBC_ENDPTCTRL_TXT_MASK                  (0xC0000U)
+#define USBC_ENDPTCTRL_TXT_SHIFT                 (18U)
+/*! TXT - TXT */
+#define USBC_ENDPTCTRL_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_TXT_SHIFT)) & USBC_ENDPTCTRL_TXT_MASK)
+
+#define USBC_ENDPTCTRL_UNUSED_20_MASK            (0x100000U)
+#define USBC_ENDPTCTRL_UNUSED_20_SHIFT           (20U)
+/*! UNUSED_20 - UNUSED_20 */
+#define USBC_ENDPTCTRL_UNUSED_20(x)              (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_UNUSED_20_SHIFT)) & USBC_ENDPTCTRL_UNUSED_20_MASK)
+
+#define USBC_ENDPTCTRL_TXI_MASK                  (0x200000U)
+#define USBC_ENDPTCTRL_TXI_SHIFT                 (21U)
+/*! TXI - TXI */
+#define USBC_ENDPTCTRL_TXI(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_TXI_SHIFT)) & USBC_ENDPTCTRL_TXI_MASK)
+
+#define USBC_ENDPTCTRL_TXR_MASK                  (0x400000U)
+#define USBC_ENDPTCTRL_TXR_SHIFT                 (22U)
+/*! TXR - ws */
+#define USBC_ENDPTCTRL_TXR(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_TXR_SHIFT)) & USBC_ENDPTCTRL_TXR_MASK)
+
+#define USBC_ENDPTCTRL_TXE_MASK                  (0x800000U)
+#define USBC_ENDPTCTRL_TXE_SHIFT                 (23U)
+/*! TXE - TXE */
+#define USBC_ENDPTCTRL_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_TXE_SHIFT)) & USBC_ENDPTCTRL_TXE_MASK)
+
+#define USBC_ENDPTCTRL_UNUSED_24_MASK            (0xFF000000U)
+#define USBC_ENDPTCTRL_UNUSED_24_SHIFT           (24U)
+/*! UNUSED_24 - UNUSED_24 */
+#define USBC_ENDPTCTRL_UNUSED_24(x)              (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL_UNUSED_24_SHIFT)) & USBC_ENDPTCTRL_UNUSED_24_MASK)
+/*! @} */
+
+/* The count of USBC_ENDPTCTRL */
+#define USBC_ENDPTCTRL_COUNT                     (15U)
+
+/*! @name PLL_CONTROL_0 - PLL_Control_0 */
+/*! @{ */
+
+#define USBC_PLL_CONTROL_0_REFDIV_MASK           (0x7FU)
+#define USBC_PLL_CONTROL_0_REFDIV_SHIFT          (0U)
+/*! REFDIV - REFDIV */
+#define USBC_PLL_CONTROL_0_REFDIV(x)             (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_REFDIV_SHIFT)) & USBC_PLL_CONTROL_0_REFDIV_MASK)
+
+#define USBC_PLL_CONTROL_0_UNUSED_7_MASK         (0x80U)
+#define USBC_PLL_CONTROL_0_UNUSED_7_SHIFT        (7U)
+/*! UNUSED_7 - Reserved */
+#define USBC_PLL_CONTROL_0_UNUSED_7(x)           (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_UNUSED_7_SHIFT)) & USBC_PLL_CONTROL_0_UNUSED_7_MASK)
+
+#define USBC_PLL_CONTROL_0_ICP_MASK              (0xF00U)
+#define USBC_PLL_CONTROL_0_ICP_SHIFT             (8U)
+/*! ICP - ICP */
+#define USBC_PLL_CONTROL_0_ICP(x)                (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_ICP_SHIFT)) & USBC_PLL_CONTROL_0_ICP_MASK)
+
+#define USBC_PLL_CONTROL_0_VDDM_MASK             (0x3000U)
+#define USBC_PLL_CONTROL_0_VDDM_SHIFT            (12U)
+/*! VDDM - VDDM */
+#define USBC_PLL_CONTROL_0_VDDM(x)               (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_VDDM_SHIFT)) & USBC_PLL_CONTROL_0_VDDM_MASK)
+
+#define USBC_PLL_CONTROL_0_VDDL_MASK             (0xC000U)
+#define USBC_PLL_CONTROL_0_VDDL_SHIFT            (14U)
+/*! VDDL - VDDL */
+#define USBC_PLL_CONTROL_0_VDDL(x)               (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_VDDL_SHIFT)) & USBC_PLL_CONTROL_0_VDDL_MASK)
+
+#define USBC_PLL_CONTROL_0_FBDIV_MASK            (0x1FF0000U)
+#define USBC_PLL_CONTROL_0_FBDIV_SHIFT           (16U)
+/*! FBDIV - FBDIV */
+#define USBC_PLL_CONTROL_0_FBDIV(x)              (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_FBDIV_SHIFT)) & USBC_PLL_CONTROL_0_FBDIV_MASK)
+
+#define USBC_PLL_CONTROL_0_UNUSED_25_MASK        (0xE000000U)
+#define USBC_PLL_CONTROL_0_UNUSED_25_SHIFT       (25U)
+/*! UNUSED_25 - Reserved */
+#define USBC_PLL_CONTROL_0_UNUSED_25(x)          (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_UNUSED_25_SHIFT)) & USBC_PLL_CONTROL_0_UNUSED_25_MASK)
+
+#define USBC_PLL_CONTROL_0_SEL_LPFR_MASK         (0x30000000U)
+#define USBC_PLL_CONTROL_0_SEL_LPFR_SHIFT        (28U)
+/*! SEL_LPFR - SEL_LPFR */
+#define USBC_PLL_CONTROL_0_SEL_LPFR(x)           (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_SEL_LPFR_SHIFT)) & USBC_PLL_CONTROL_0_SEL_LPFR_MASK)
+
+#define USBC_PLL_CONTROL_0_R_ROTATE_MASK         (0x40000000U)
+#define USBC_PLL_CONTROL_0_R_ROTATE_SHIFT        (30U)
+/*! R_ROTATE - R_ROTATE */
+#define USBC_PLL_CONTROL_0_R_ROTATE(x)           (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_R_ROTATE_SHIFT)) & USBC_PLL_CONTROL_0_R_ROTATE_MASK)
+
+#define USBC_PLL_CONTROL_0_PLL_READY_MASK        (0x80000000U)
+#define USBC_PLL_CONTROL_0_PLL_READY_SHIFT       (31U)
+/*! PLL_READY - PLL_READY */
+#define USBC_PLL_CONTROL_0_PLL_READY(x)          (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_PLL_READY_SHIFT)) & USBC_PLL_CONTROL_0_PLL_READY_MASK)
+/*! @} */
+
+/*! @name PLL_CONTROL_1 - PLL_Control_1 */
+/*! @{ */
+
+#define USBC_PLL_CONTROL_1_PU_PLL_MASK           (0x1U)
+#define USBC_PLL_CONTROL_1_PU_PLL_SHIFT          (0U)
+/*! PU_PLL - PU_PLL */
+#define USBC_PLL_CONTROL_1_PU_PLL(x)             (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PU_PLL_SHIFT)) & USBC_PLL_CONTROL_1_PU_PLL_MASK)
+
+#define USBC_PLL_CONTROL_1_PU_PLL_BY_REG_MASK    (0x2U)
+#define USBC_PLL_CONTROL_1_PU_PLL_BY_REG_SHIFT   (1U)
+/*! PU_PLL_BY_REG - PU_PLL_BY_REG */
+#define USBC_PLL_CONTROL_1_PU_PLL_BY_REG(x)      (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PU_PLL_BY_REG_SHIFT)) & USBC_PLL_CONTROL_1_PU_PLL_BY_REG_MASK)
+
+#define USBC_PLL_CONTROL_1_PLL_RESET_MASK        (0x4U)
+#define USBC_PLL_CONTROL_1_PLL_RESET_SHIFT       (2U)
+/*! PLL_RESET - PLL_RESET */
+#define USBC_PLL_CONTROL_1_PLL_RESET(x)          (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PLL_RESET_SHIFT)) & USBC_PLL_CONTROL_1_PLL_RESET_MASK)
+
+#define USBC_PLL_CONTROL_1_PLL_SUSPEND_EN_MASK   (0x8U)
+#define USBC_PLL_CONTROL_1_PLL_SUSPEND_EN_SHIFT  (3U)
+/*! PLL_SUSPEND_EN - PLL_SUSPEND_EN */
+#define USBC_PLL_CONTROL_1_PLL_SUSPEND_EN(x)     (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PLL_SUSPEND_EN_SHIFT)) & USBC_PLL_CONTROL_1_PLL_SUSPEND_EN_MASK)
+
+#define USBC_PLL_CONTROL_1_TESTMON_PLL_MASK      (0xF0U)
+#define USBC_PLL_CONTROL_1_TESTMON_PLL_SHIFT     (4U)
+/*! TESTMON_PLL - TESTMON_PLL */
+#define USBC_PLL_CONTROL_1_TESTMON_PLL(x)        (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_TESTMON_PLL_SHIFT)) & USBC_PLL_CONTROL_1_TESTMON_PLL_MASK)
+
+#define USBC_PLL_CONTROL_1_UNUSED_8_MASK         (0x300U)
+#define USBC_PLL_CONTROL_1_UNUSED_8_SHIFT        (8U)
+/*! UNUSED_8 - Reserved */
+#define USBC_PLL_CONTROL_1_UNUSED_8(x)           (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_UNUSED_8_SHIFT)) & USBC_PLL_CONTROL_1_UNUSED_8_MASK)
+
+#define USBC_PLL_CONTROL_1_TXCLK_EN_MASK         (0x400U)
+#define USBC_PLL_CONTROL_1_TXCLK_EN_SHIFT        (10U)
+/*! TXCLK_EN - TXCLK_EN */
+#define USBC_PLL_CONTROL_1_TXCLK_EN(x)           (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_TXCLK_EN_SHIFT)) & USBC_PLL_CONTROL_1_TXCLK_EN_MASK)
+
+#define USBC_PLL_CONTROL_1_CLK160M_EN_MASK       (0x800U)
+#define USBC_PLL_CONTROL_1_CLK160M_EN_SHIFT      (11U)
+/*! CLK160M_EN - CLK160M_EN */
+#define USBC_PLL_CONTROL_1_CLK160M_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_CLK160M_EN_SHIFT)) & USBC_PLL_CONTROL_1_CLK160M_EN_MASK)
+
+#define USBC_PLL_CONTROL_1_REFCLK_SEL_MASK       (0x1000U)
+#define USBC_PLL_CONTROL_1_REFCLK_SEL_SHIFT      (12U)
+/*! REFCLK_SEL - REFCLK_SEL */
+#define USBC_PLL_CONTROL_1_REFCLK_SEL(x)         (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_REFCLK_SEL_SHIFT)) & USBC_PLL_CONTROL_1_REFCLK_SEL_MASK)
+
+#define USBC_PLL_CONTROL_1_CLK_BLK_EN_MASK       (0x2000U)
+#define USBC_PLL_CONTROL_1_CLK_BLK_EN_SHIFT      (13U)
+/*! CLK_BLK_EN - CLK_BLK_EN */
+#define USBC_PLL_CONTROL_1_CLK_BLK_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_CLK_BLK_EN_SHIFT)) & USBC_PLL_CONTROL_1_CLK_BLK_EN_MASK)
+
+#define USBC_PLL_CONTROL_1_PLL_STRESS_TEST_MASK  (0x4000U)
+#define USBC_PLL_CONTROL_1_PLL_STRESS_TEST_SHIFT (14U)
+/*! PLL_STRESS_TEST - PLL_STRESS_TEST */
+#define USBC_PLL_CONTROL_1_PLL_STRESS_TEST(x)    (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PLL_STRESS_TEST_SHIFT)) & USBC_PLL_CONTROL_1_PLL_STRESS_TEST_MASK)
+
+#define USBC_PLL_CONTROL_1_UNUSED_15_MASK        (0xFFFF8000U)
+#define USBC_PLL_CONTROL_1_UNUSED_15_SHIFT       (15U)
+/*! UNUSED_15 - Reserved */
+#define USBC_PLL_CONTROL_1_UNUSED_15(x)          (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_UNUSED_15_SHIFT)) & USBC_PLL_CONTROL_1_UNUSED_15_MASK)
+/*! @} */
+
+/*! @name CALIBRATION_CONTROL - CALIBRATION_Control */
+/*! @{ */
+
+#define USBC_CALIBRATION_CONTROL_EXT_FS_IMP_MASK (0xFU)
+#define USBC_CALIBRATION_CONTROL_EXT_FS_IMP_SHIFT (0U)
+/*! EXT_FS_IMP - EXT_FS_IMP */
+#define USBC_CALIBRATION_CONTROL_EXT_FS_IMP(x)   (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_EXT_FS_IMP_SHIFT)) & USBC_CALIBRATION_CONTROL_EXT_FS_IMP_MASK)
+
+#define USBC_CALIBRATION_CONTROL_EXT_RCAL_MASK   (0xF0U)
+#define USBC_CALIBRATION_CONTROL_EXT_RCAL_SHIFT  (4U)
+/*! EXT_RCAL - EXT_RCAL */
+#define USBC_CALIBRATION_CONTROL_EXT_RCAL(x)     (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_EXT_RCAL_SHIFT)) & USBC_CALIBRATION_CONTROL_EXT_RCAL_MASK)
+
+#define USBC_CALIBRATION_CONTROL_IMPCAL_VTH_MASK (0x700U)
+#define USBC_CALIBRATION_CONTROL_IMPCAL_VTH_SHIFT (8U)
+/*! IMPCAL_VTH - IMPCAL_VTH */
+#define USBC_CALIBRATION_CONTROL_IMPCAL_VTH(x)   (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_IMPCAL_VTH_SHIFT)) & USBC_CALIBRATION_CONTROL_IMPCAL_VTH_MASK)
+
+#define USBC_CALIBRATION_CONTROL_EXT_FS_IMP_EN_MASK (0x800U)
+#define USBC_CALIBRATION_CONTROL_EXT_FS_IMP_EN_SHIFT (11U)
+/*! EXT_FS_IMP_EN - EXT_FS_IMP_EN */
+#define USBC_CALIBRATION_CONTROL_EXT_FS_IMP_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_EXT_FS_IMP_EN_SHIFT)) & USBC_CALIBRATION_CONTROL_EXT_FS_IMP_EN_MASK)
+
+#define USBC_CALIBRATION_CONTROL_EXT_RCAL_EN_MASK (0x1000U)
+#define USBC_CALIBRATION_CONTROL_EXT_RCAL_EN_SHIFT (12U)
+/*! EXT_RCAL_EN - EXT_RCAL_EN */
+#define USBC_CALIBRATION_CONTROL_EXT_RCAL_EN(x)  (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_EXT_RCAL_EN_SHIFT)) & USBC_CALIBRATION_CONTROL_EXT_RCAL_EN_MASK)
+
+#define USBC_CALIBRATION_CONTROL_IMPCAL_START_MASK (0x2000U)
+#define USBC_CALIBRATION_CONTROL_IMPCAL_START_SHIFT (13U)
+/*! IMPCAL_START - IMPCAL_START */
+#define USBC_CALIBRATION_CONTROL_IMPCAL_START(x) (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_IMPCAL_START_SHIFT)) & USBC_CALIBRATION_CONTROL_IMPCAL_START_MASK)
+
+#define USBC_CALIBRATION_CONTROL_IMPCAL_POL_MASK (0x4000U)
+#define USBC_CALIBRATION_CONTROL_IMPCAL_POL_SHIFT (14U)
+/*! IMPCAL_POL - IMPCAL_POL */
+#define USBC_CALIBRATION_CONTROL_IMPCAL_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_IMPCAL_POL_SHIFT)) & USBC_CALIBRATION_CONTROL_IMPCAL_POL_MASK)
+
+#define USBC_CALIBRATION_CONTROL_VCOCAL_POL_MASK (0x8000U)
+#define USBC_CALIBRATION_CONTROL_VCOCAL_POL_SHIFT (15U)
+/*! VCOCAL_POL - VCOCAL_POL */
+#define USBC_CALIBRATION_CONTROL_VCOCAL_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_VCOCAL_POL_SHIFT)) & USBC_CALIBRATION_CONTROL_VCOCAL_POL_MASK)
+
+#define USBC_CALIBRATION_CONTROL_KVCO_MASK       (0x70000U)
+#define USBC_CALIBRATION_CONTROL_KVCO_SHIFT      (16U)
+/*! KVCO - KVCO */
+#define USBC_CALIBRATION_CONTROL_KVCO(x)         (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_KVCO_SHIFT)) & USBC_CALIBRATION_CONTROL_KVCO_MASK)
+
+#define USBC_CALIBRATION_CONTROL_KVCO_EXT_MASK   (0x80000U)
+#define USBC_CALIBRATION_CONTROL_KVCO_EXT_SHIFT  (19U)
+/*! KVCO_EXT - KVCO_EXT */
+#define USBC_CALIBRATION_CONTROL_KVCO_EXT(x)     (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_KVCO_EXT_SHIFT)) & USBC_CALIBRATION_CONTROL_KVCO_EXT_MASK)
+
+#define USBC_CALIBRATION_CONTROL_PLLCAL_MASK     (0x300000U)
+#define USBC_CALIBRATION_CONTROL_PLLCAL_SHIFT    (20U)
+/*! PLLCAL - PLLCAL */
+#define USBC_CALIBRATION_CONTROL_PLLCAL(x)       (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_PLLCAL_SHIFT)) & USBC_CALIBRATION_CONTROL_PLLCAL_MASK)
+
+#define USBC_CALIBRATION_CONTROL_PLLCAL_START_MASK (0x400000U)
+#define USBC_CALIBRATION_CONTROL_PLLCAL_START_SHIFT (22U)
+/*! PLLCAL_START - PLLCAL_START */
+#define USBC_CALIBRATION_CONTROL_PLLCAL_START(x) (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_PLLCAL_START_SHIFT)) & USBC_CALIBRATION_CONTROL_PLLCAL_START_MASK)
+
+#define USBC_CALIBRATION_CONTROL_IMPCAL_DONE_MASK (0x800000U)
+#define USBC_CALIBRATION_CONTROL_IMPCAL_DONE_SHIFT (23U)
+/*! IMPCAL_DONE - IMPCAL_DONE */
+#define USBC_CALIBRATION_CONTROL_IMPCAL_DONE(x)  (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_IMPCAL_DONE_SHIFT)) & USBC_CALIBRATION_CONTROL_IMPCAL_DONE_MASK)
+
+#define USBC_CALIBRATION_CONTROL_CURRENT_IMP_MASK (0xF000000U)
+#define USBC_CALIBRATION_CONTROL_CURRENT_IMP_SHIFT (24U)
+/*! CURRENT_IMP - CURRENT_IMP */
+#define USBC_CALIBRATION_CONTROL_CURRENT_IMP(x)  (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_CURRENT_IMP_SHIFT)) & USBC_CALIBRATION_CONTROL_CURRENT_IMP_MASK)
+
+#define USBC_CALIBRATION_CONTROL_CURRENT_KVCO_MASK (0x70000000U)
+#define USBC_CALIBRATION_CONTROL_CURRENT_KVCO_SHIFT (28U)
+/*! CURRENT_KVCO - CURRENT_KVCO */
+#define USBC_CALIBRATION_CONTROL_CURRENT_KVCO(x) (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_CURRENT_KVCO_SHIFT)) & USBC_CALIBRATION_CONTROL_CURRENT_KVCO_MASK)
+
+#define USBC_CALIBRATION_CONTROL_PLLCAL_DONE_MASK (0x80000000U)
+#define USBC_CALIBRATION_CONTROL_PLLCAL_DONE_SHIFT (31U)
+/*! PLLCAL_DONE - PLLCAL_DONE */
+#define USBC_CALIBRATION_CONTROL_PLLCAL_DONE(x)  (((uint32_t)(((uint32_t)(x)) << USBC_CALIBRATION_CONTROL_PLLCAL_DONE_SHIFT)) & USBC_CALIBRATION_CONTROL_PLLCAL_DONE_MASK)
+/*! @} */
+
+/*! @name TX_CHANNEL_CONTRL_0 - Tx_Channel_Contrl_0 */
+/*! @{ */
+
+#define USBC_TX_CHANNEL_CONTRL_0_HSDRV_EN_MASK   (0xFU)
+#define USBC_TX_CHANNEL_CONTRL_0_HSDRV_EN_SHIFT  (0U)
+/*! HSDRV_EN - HSDRV_EN */
+#define USBC_TX_CHANNEL_CONTRL_0_HSDRV_EN(x)     (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_HSDRV_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_HSDRV_EN_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_HS_SR_SEL_MASK  (0x30U)
+#define USBC_TX_CHANNEL_CONTRL_0_HS_SR_SEL_SHIFT (4U)
+/*! HS_SR_SEL - HS_SR_SEL */
+#define USBC_TX_CHANNEL_CONTRL_0_HS_SR_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_HS_SR_SEL_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_HS_SR_SEL_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_LOWVDD_EN_MASK  (0x40U)
+#define USBC_TX_CHANNEL_CONTRL_0_LOWVDD_EN_SHIFT (6U)
+/*! LOWVDD_EN - LOWVDD_EN */
+#define USBC_TX_CHANNEL_CONTRL_0_LOWVDD_EN(x)    (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_LOWVDD_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_LOWVDD_EN_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_UNUSED_7_MASK   (0x80U)
+#define USBC_TX_CHANNEL_CONTRL_0_UNUSED_7_SHIFT  (7U)
+/*! UNUSED_7 - Reserved */
+#define USBC_TX_CHANNEL_CONTRL_0_UNUSED_7(x)     (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_UNUSED_7_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_UNUSED_7_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_FSDRV_EN_MASK   (0xF00U)
+#define USBC_TX_CHANNEL_CONTRL_0_FSDRV_EN_SHIFT  (8U)
+/*! FSDRV_EN - FSDRV_EN */
+#define USBC_TX_CHANNEL_CONTRL_0_FSDRV_EN(x)     (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_FSDRV_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_FSDRV_EN_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_DRV_EN_LS_MASK  (0xF000U)
+#define USBC_TX_CHANNEL_CONTRL_0_DRV_EN_LS_SHIFT (12U)
+/*! DRV_EN_LS - DRV_EN_LS */
+#define USBC_TX_CHANNEL_CONTRL_0_DRV_EN_LS(x)    (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_DRV_EN_LS_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_DRV_EN_LS_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_IMP_SEL_LS_MASK (0xF0000U)
+#define USBC_TX_CHANNEL_CONTRL_0_IMP_SEL_LS_SHIFT (16U)
+/*! IMP_SEL_LS - IMP_SEL_LS */
+#define USBC_TX_CHANNEL_CONTRL_0_IMP_SEL_LS(x)   (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_IMP_SEL_LS_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_IMP_SEL_LS_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_AMP_MASK        (0x700000U)
+#define USBC_TX_CHANNEL_CONTRL_0_AMP_SHIFT       (20U)
+/*! AMP - AMP */
+#define USBC_TX_CHANNEL_CONTRL_0_AMP(x)          (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_AMP_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_AMP_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_PU_VDDR18_MASK  (0x800000U)
+#define USBC_TX_CHANNEL_CONTRL_0_PU_VDDR18_SHIFT (23U)
+/*! PU_VDDR18 - PU_VDDR18 */
+#define USBC_TX_CHANNEL_CONTRL_0_PU_VDDR18(x)    (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_PU_VDDR18_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_PU_VDDR18_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_PU_ANA_MASK     (0x1000000U)
+#define USBC_TX_CHANNEL_CONTRL_0_PU_ANA_SHIFT    (24U)
+/*! PU_ANA - PU_ANA */
+#define USBC_TX_CHANNEL_CONTRL_0_PU_ANA(x)       (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_PU_ANA_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_PU_ANA_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_PU_BY_REG_MASK  (0x2000000U)
+#define USBC_TX_CHANNEL_CONTRL_0_PU_BY_REG_SHIFT (25U)
+/*! PU_BY_REG - PU_BY_REG */
+#define USBC_TX_CHANNEL_CONTRL_0_PU_BY_REG(x)    (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_PU_BY_REG_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_PU_BY_REG_MASK)
+
+#define USBC_TX_CHANNEL_CONTRL_0_UNUSED_26_MASK  (0xFC000000U)
+#define USBC_TX_CHANNEL_CONTRL_0_UNUSED_26_SHIFT (26U)
+/*! UNUSED_26 - Reserved */
+#define USBC_TX_CHANNEL_CONTRL_0_UNUSED_26(x)    (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_UNUSED_26_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_UNUSED_26_MASK)
+/*! @} */
+
+/*! @name TX_CHANNEL_CONTRL_1 - Tx_Channel_Contrl_1 */
+/*! @{ */
+
+#define USBC_TX_CHANNEL_CONTRL_1_UNUSED_0_MASK   (0xFFFFFFFFU)
+#define USBC_TX_CHANNEL_CONTRL_1_UNUSED_0_SHIFT  (0U)
+/*! UNUSED_0 - Reserved */
+#define USBC_TX_CHANNEL_CONTRL_1_UNUSED_0(x)     (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_1_UNUSED_0_SHIFT)) & USBC_TX_CHANNEL_CONTRL_1_UNUSED_0_MASK)
+/*! @} */
+
+/*! @name RX_CHANNEL_CONTRL_0 - Rx_Channel_Contrl_0 */
+/*! @{ */
+
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_MASK  (0xFU)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_SHIFT (0U)
+/*! SQ_THRESH - SQ_THRESH */
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH(x)    (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_RXVDD18_MASK    (0x30U)
+#define USBC_RX_CHANNEL_CONTRL_0_RXVDD18_SHIFT   (4U)
+/*! RXVDD18 - RXVDD18 */
+#define USBC_RX_CHANNEL_CONTRL_0_RXVDD18(x)      (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_RXVDD18_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_RXVDD18_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_RXVDDL_MASK     (0xC0U)
+#define USBC_RX_CHANNEL_CONTRL_0_RXVDDL_SHIFT    (6U)
+/*! RXVDDL - RXVDDL */
+#define USBC_RX_CHANNEL_CONTRL_0_RXVDDL(x)       (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_RXVDDL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_RXVDDL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_MASK (0x300U)
+#define USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_SHIFT (8U)
+/*! DISCON_THRESH - DISCON_THRESH */
+#define USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_LINESTATE_EN_MASK (0x400U)
+#define USBC_RX_CHANNEL_CONTRL_0_LINESTATE_EN_SHIFT (10U)
+/*! LINESTATE_EN - LINESTATE_EN */
+#define USBC_RX_CHANNEL_CONTRL_0_LINESTATE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_LINESTATE_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_LINESTATE_EN_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_11_MASK  (0x800U)
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_11_SHIFT (11U)
+/*! UNUSED_11 - Reserved */
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_11(x)    (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_UNUSED_11_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_UNUSED_11_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_DLY_SEL_MASK (0x3000U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_DLY_SEL_SHIFT (12U)
+/*! SQ_DLY_SEL - SQ_DLY_SEL */
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_DLY_SEL(x)   (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_DLY_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_DLY_SEL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_CM_SEL_MASK  (0x4000U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_CM_SEL_SHIFT (14U)
+/*! SQ_CM_SEL - SQ_CM_SEL */
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_CM_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_CM_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_CM_SEL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_DET_EN_MASK  (0x8000U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_DET_EN_SHIFT (15U)
+/*! SQ_DET_EN - SQ_DET_EN */
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_DET_EN(x)    (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_DET_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_DET_EN_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_VHL_SEL_MASK (0x10000U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_VHL_SEL_SHIFT (16U)
+/*! SQ_VHL_SEL - SQ_VHL_SEL */
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_VHL_SEL(x)   (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_VHL_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_VHL_SEL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_17_MASK  (0x60000U)
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_17_SHIFT (17U)
+/*! UNUSED_17 - Reserved */
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_17(x)    (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_UNUSED_17_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_UNUSED_17_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_STRESS_TEST_MODE_MASK (0x80000U)
+#define USBC_RX_CHANNEL_CONTRL_0_STRESS_TEST_MODE_SHIFT (19U)
+/*! STRESS_TEST_MODE - STRESS_TEST_MODE */
+#define USBC_RX_CHANNEL_CONTRL_0_STRESS_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_STRESS_TEST_MODE_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_STRESS_TEST_MODE_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_TESTMON_MASK    (0xF00000U)
+#define USBC_RX_CHANNEL_CONTRL_0_TESTMON_SHIFT   (20U)
+/*! TESTMON - TESTMON */
+#define USBC_RX_CHANNEL_CONTRL_0_TESTMON(x)      (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_TESTMON_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_TESTMON_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_EN_MASK (0x1000000U)
+#define USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_EN_SHIFT (24U)
+/*! RESET_EXT_EN - RESET_EXT_EN */
+#define USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_EN_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_MASK  (0x2000000U)
+#define USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_SHIFT (25U)
+/*! RESET_EXT - RESET_EXT */
+#define USBC_RX_CHANNEL_CONTRL_0_RESET_EXT(x)    (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_RESET_EXT_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_VREF_MASK (0xC000000U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_VREF_SHIFT (26U)
+/*! SQ_ANA_VREF - SQ_ANA_VREF */
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_VREF(x)  (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_VREF_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_VREF_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_DTC_SEL_MASK (0x10000000U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_DTC_SEL_SHIFT (28U)
+/*! SQ_ANA_DTC_SEL - SQ_ANA_DTC_SEL */
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_DTC_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_DTC_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_ANA_DTC_SEL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_CHIRPMODE_SEL_MASK (0x20000000U)
+#define USBC_RX_CHANNEL_CONTRL_0_CHIRPMODE_SEL_SHIFT (29U)
+/*! CHIRPMODE_SEL - CHIRPMODE_SEL */
+#define USBC_RX_CHANNEL_CONTRL_0_CHIRPMODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_CHIRPMODE_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_CHIRPMODE_SEL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_30_MASK  (0xC0000000U)
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_30_SHIFT (30U)
+/*! UNUSED_30 - Reserved */
+#define USBC_RX_CHANNEL_CONTRL_0_UNUSED_30(x)    (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_UNUSED_30_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_UNUSED_30_MASK)
+/*! @} */
+
+/*! @name RX_CHANNEL_CONTRL_1 - Rx_Channel_Contrl_1 */
+/*! @{ */
+
+#define USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_MASK (0x7U)
+#define USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_SHIFT (0U)
+/*! EXT_SQ_AMP_CAL - EXT_SQ_AMP_CAL */
+#define USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_EN_MASK (0x8U)
+#define USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_EN_SHIFT (3U)
+/*! EXT_SQ_AMP_CAL_EN - EXT_SQ_AMP_CAL_EN */
+#define USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_EXT_SQ_AMP_CAL_EN_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_1_REQ_SQCAL_START_MASK (0x10U)
+#define USBC_RX_CHANNEL_CONTRL_1_REQ_SQCAL_START_SHIFT (4U)
+/*! REQ_SQCAL_START - REQ_SQCAL_START */
+#define USBC_RX_CHANNEL_CONTRL_1_REQ_SQCAL_START(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_REQ_SQCAL_START_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_REQ_SQCAL_START_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_1_REG_SQ_UD_SWAP_MASK (0x20U)
+#define USBC_RX_CHANNEL_CONTRL_1_REG_SQ_UD_SWAP_SHIFT (5U)
+/*! REG_SQ_UD_SWAP - REG_SQ_UD_SWAP */
+#define USBC_RX_CHANNEL_CONTRL_1_REG_SQ_UD_SWAP(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_REG_SQ_UD_SWAP_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_REG_SQ_UD_SWAP_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_1_SQ_DPDM_AMP_SEL_MASK (0xC0U)
+#define USBC_RX_CHANNEL_CONTRL_1_SQ_DPDM_AMP_SEL_SHIFT (6U)
+/*! SQ_DPDM_AMP_SEL - SQ_DPDM_AMP_SEL */
+#define USBC_RX_CHANNEL_CONTRL_1_SQ_DPDM_AMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_SQ_DPDM_AMP_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_SQ_DPDM_AMP_SEL_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_1_UNUSED_8_MASK   (0x7FFFFF00U)
+#define USBC_RX_CHANNEL_CONTRL_1_UNUSED_8_SHIFT  (8U)
+/*! UNUSED_8 - Reserved */
+#define USBC_RX_CHANNEL_CONTRL_1_UNUSED_8(x)     (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_UNUSED_8_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_UNUSED_8_MASK)
+
+#define USBC_RX_CHANNEL_CONTRL_1_REG_SQCAL_DONE_MASK (0x80000000U)
+#define USBC_RX_CHANNEL_CONTRL_1_REG_SQCAL_DONE_SHIFT (31U)
+/*! REG_SQCAL_DONE - REG_SQCAL_DONE */
+#define USBC_RX_CHANNEL_CONTRL_1_REG_SQCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_REG_SQCAL_DONE_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_REG_SQCAL_DONE_MASK)
+/*! @} */
+
+/*! @name DIGITAL_CONTRL_0 - Digital_Contrl_0 */
+/*! @{ */
+
+#define USBC_DIGITAL_CONTRL_0_SYNC_NUM_MASK      (0x3U)
+#define USBC_DIGITAL_CONTRL_0_SYNC_NUM_SHIFT     (0U)
+/*! SYNC_NUM - SYNC_NUM */
+#define USBC_DIGITAL_CONTRL_0_SYNC_NUM(x)        (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_SYNC_NUM_SHIFT)) & USBC_DIGITAL_CONTRL_0_SYNC_NUM_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_SYNCDET_WIN32_MASK (0x4U)
+#define USBC_DIGITAL_CONTRL_0_SYNCDET_WIN32_SHIFT (2U)
+/*! SYNCDET_WIN32 - SYNCDET_WIN32 */
+#define USBC_DIGITAL_CONTRL_0_SYNCDET_WIN32(x)   (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_SYNCDET_WIN32_SHIFT)) & USBC_DIGITAL_CONTRL_0_SYNCDET_WIN32_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_SYNCDET_WINDOW_EN_MASK (0x8U)
+#define USBC_DIGITAL_CONTRL_0_SYNCDET_WINDOW_EN_SHIFT (3U)
+/*! SYNCDET_WINDOW_EN - SYNCDET_WINDOW_EN */
+#define USBC_DIGITAL_CONTRL_0_SYNCDET_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_SYNCDET_WINDOW_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_SYNCDET_WINDOW_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL0_MASK (0x10U)
+#define USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL0_SHIFT (4U)
+/*! HOST_DISCON_SEL0 - HOST_DISCON_SEL0 */
+#define USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL0(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL0_SHIFT)) & USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL0_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL1_MASK (0x20U)
+#define USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL1_SHIFT (5U)
+/*! HOST_DISCON_SEL1 - HOST_DISCON_SEL1 */
+#define USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL1(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL1_SHIFT)) & USBC_DIGITAL_CONTRL_0_HOST_DISCON_SEL1_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_UNUSED_6_MASK      (0x40U)
+#define USBC_DIGITAL_CONTRL_0_UNUSED_6_SHIFT     (6U)
+/*! UNUSED_6 - Reserved */
+#define USBC_DIGITAL_CONTRL_0_UNUSED_6(x)        (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_UNUSED_6_SHIFT)) & USBC_DIGITAL_CONTRL_0_UNUSED_6_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_BYPASS_MASK (0x80U)
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_BYPASS_SHIFT (7U)
+/*! PLL_LOCK_BYPASS - PLL_LOCK_BYPASS */
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_PLL_LOCK_BYPASS_SHIFT)) & USBC_DIGITAL_CONTRL_0_PLL_LOCK_BYPASS_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_LONG_EOP_MASK      (0x100U)
+#define USBC_DIGITAL_CONTRL_0_LONG_EOP_SHIFT     (8U)
+/*! LONG_EOP - LONG_EOP */
+#define USBC_DIGITAL_CONTRL_0_LONG_EOP(x)        (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_LONG_EOP_SHIFT)) & USBC_DIGITAL_CONTRL_0_LONG_EOP_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_RXFILT1_EN_MASK    (0x200U)
+#define USBC_DIGITAL_CONTRL_0_RXFILT1_EN_SHIFT   (9U)
+/*! RXFILT1_EN - RXFILT1_EN */
+#define USBC_DIGITAL_CONTRL_0_RXFILT1_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_RXFILT1_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_RXFILT1_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_RXFILT2_EN_MASK    (0x400U)
+#define USBC_DIGITAL_CONTRL_0_RXFILT2_EN_SHIFT   (10U)
+/*! RXFILT2_EN - RXFILT2_EN */
+#define USBC_DIGITAL_CONTRL_0_RXFILT2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_RXFILT2_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_RXFILT2_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_EARLY_TX_ENABLE_MASK (0x800U)
+#define USBC_DIGITAL_CONTRL_0_EARLY_TX_ENABLE_SHIFT (11U)
+/*! EARLY_TX_ENABLE - EARLY_TX_ENABLE */
+#define USBC_DIGITAL_CONTRL_0_EARLY_TX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_EARLY_TX_ENABLE_SHIFT)) & USBC_DIGITAL_CONTRL_0_EARLY_TX_ENABLE_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_SQ_BLK_MASK        (0x7000U)
+#define USBC_DIGITAL_CONTRL_0_SQ_BLK_SHIFT       (12U)
+/*! SQ_BLK - SQ_BLK */
+#define USBC_DIGITAL_CONTRL_0_SQ_BLK(x)          (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_SQ_BLK_SHIFT)) & USBC_DIGITAL_CONTRL_0_SQ_BLK_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_RXFILT3_EN_MASK    (0x8000U)
+#define USBC_DIGITAL_CONTRL_0_RXFILT3_EN_SHIFT   (15U)
+/*! RXFILT3_EN - RXFILT3_EN */
+#define USBC_DIGITAL_CONTRL_0_RXFILT3_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_RXFILT3_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_RXFILT3_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_SQ_FILT_MASK       (0x70000U)
+#define USBC_DIGITAL_CONTRL_0_SQ_FILT_SHIFT      (16U)
+/*! SQ_FILT - SQ_FILT */
+#define USBC_DIGITAL_CONTRL_0_SQ_FILT(x)         (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_SQ_FILT_SHIFT)) & USBC_DIGITAL_CONTRL_0_SQ_FILT_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_FIFOOVF_EN_MASK    (0x80000U)
+#define USBC_DIGITAL_CONTRL_0_FIFOOVF_EN_SHIFT   (19U)
+/*! FIFOOVF_EN - FIFOOVF_EN */
+#define USBC_DIGITAL_CONTRL_0_FIFOOVF_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_FIFOOVF_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_FIFOOVF_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_LOSSOFSYNC_EN_MASK (0x100000U)
+#define USBC_DIGITAL_CONTRL_0_LOSSOFSYNC_EN_SHIFT (20U)
+/*! LOSSOFSYNC_EN - LOSSOFSYNC_EN */
+#define USBC_DIGITAL_CONTRL_0_LOSSOFSYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_LOSSOFSYNC_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_LOSSOFSYNC_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_RX_RUNAWAY_EN_MASK (0x200000U)
+#define USBC_DIGITAL_CONTRL_0_RX_RUNAWAY_EN_SHIFT (21U)
+/*! RX_RUNAWAY_EN - RX_RUNAWAY_EN */
+#define USBC_DIGITAL_CONTRL_0_RX_RUNAWAY_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_RX_RUNAWAY_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_RX_RUNAWAY_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_STOP_AT_RXERR_MASK (0x400000U)
+#define USBC_DIGITAL_CONTRL_0_STOP_AT_RXERR_SHIFT (22U)
+/*! STOP_AT_RXERR - STOP_AT_RXERR */
+#define USBC_DIGITAL_CONTRL_0_STOP_AT_RXERR(x)   (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_STOP_AT_RXERR_SHIFT)) & USBC_DIGITAL_CONTRL_0_STOP_AT_RXERR_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_EDGE_OPT_EN_MASK   (0x800000U)
+#define USBC_DIGITAL_CONTRL_0_EDGE_OPT_EN_SHIFT  (23U)
+/*! EDGE_OPT_EN - EDGE_OPT_EN */
+#define USBC_DIGITAL_CONTRL_0_EDGE_OPT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_EDGE_OPT_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_EDGE_OPT_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_SE0_FILT_SEL_MASK  (0x1000000U)
+#define USBC_DIGITAL_CONTRL_0_SE0_FILT_SEL_SHIFT (24U)
+/*! SE0_FILT_SEL - SE0_FILT_SEL */
+#define USBC_DIGITAL_CONTRL_0_SE0_FILT_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_SE0_FILT_SEL_SHIFT)) & USBC_DIGITAL_CONTRL_0_SE0_FILT_SEL_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_SE1_FILT_SEL_MASK  (0x2000000U)
+#define USBC_DIGITAL_CONTRL_0_SE1_FILT_SEL_SHIFT (25U)
+/*! SE1_FILT_SEL - SE1_FILT_SEL */
+#define USBC_DIGITAL_CONTRL_0_SE1_FILT_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_SE1_FILT_SEL_SHIFT)) & USBC_DIGITAL_CONTRL_0_SE1_FILT_SEL_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_CORE_UTMI_SEL_MASK (0x4000000U)
+#define USBC_DIGITAL_CONTRL_0_CORE_UTMI_SEL_SHIFT (26U)
+/*! CORE_UTMI_SEL - CORE_UTMI_SEL */
+#define USBC_DIGITAL_CONTRL_0_CORE_UTMI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_CORE_UTMI_SEL_SHIFT)) & USBC_DIGITAL_CONTRL_0_CORE_UTMI_SEL_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_VAL_MASK (0x8000000U)
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_VAL_SHIFT (27U)
+/*! PLL_LOCK_FORCE_VAL - PLL_LOCK_FORCE_VAL */
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_VAL_SHIFT)) & USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_VAL_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_EN_MASK (0x10000000U)
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_EN_SHIFT (28U)
+/*! PLL_LOCK_FORCE_EN - PLL_LOCK_FORCE_EN */
+#define USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_EN_SHIFT)) & USBC_DIGITAL_CONTRL_0_PLL_LOCK_FORCE_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_FIFO_OVF_ERROR_MASK (0x20000000U)
+#define USBC_DIGITAL_CONTRL_0_FIFO_OVF_ERROR_SHIFT (29U)
+/*! FIFO_OVF_ERROR - FIFO_OVF_ERROR */
+#define USBC_DIGITAL_CONTRL_0_FIFO_OVF_ERROR(x)  (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_FIFO_OVF_ERROR_SHIFT)) & USBC_DIGITAL_CONTRL_0_FIFO_OVF_ERROR_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_LOSS_OF_SYNC_ERROR_MASK (0x40000000U)
+#define USBC_DIGITAL_CONTRL_0_LOSS_OF_SYNC_ERROR_SHIFT (30U)
+/*! LOSS_OF_SYNC_ERROR - LOSS_OF_SYNC_ERROR */
+#define USBC_DIGITAL_CONTRL_0_LOSS_OF_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_LOSS_OF_SYNC_ERROR_SHIFT)) & USBC_DIGITAL_CONTRL_0_LOSS_OF_SYNC_ERROR_MASK)
+
+#define USBC_DIGITAL_CONTRL_0_BITSTUFFING_ERROR_MASK (0x80000000U)
+#define USBC_DIGITAL_CONTRL_0_BITSTUFFING_ERROR_SHIFT (31U)
+/*! BITSTUFFING_ERROR - BITSTUFFING_ERROR */
+#define USBC_DIGITAL_CONTRL_0_BITSTUFFING_ERROR(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_0_BITSTUFFING_ERROR_SHIFT)) & USBC_DIGITAL_CONTRL_0_BITSTUFFING_ERROR_MASK)
+/*! @} */
+
+/*! @name DIGITAL_CONTRL_1 - Digital_Contrl_1 */
+/*! @{ */
+
+#define USBC_DIGITAL_CONTRL_1_REG_FORCE_END_EN_MASK (0x1U)
+#define USBC_DIGITAL_CONTRL_1_REG_FORCE_END_EN_SHIFT (0U)
+/*! REG_FORCE_END_EN - REG_FORCE_END_EN */
+#define USBC_DIGITAL_CONTRL_1_REG_FORCE_END_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_FORCE_END_EN_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_FORCE_END_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE_MASK (0x2U)
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE_SHIFT (1U)
+/*! REG_FS_RX_ERROR_MODE - REG_FS_RX_ERROR_MODE */
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE1_MASK (0x4U)
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE1_SHIFT (2U)
+/*! REG_FS_RX_ERROR_MODE1 - REG_FS_RX_ERROR_MODE1 */
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE1(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE1_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE1_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE2_MASK (0x8U)
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE2_SHIFT (3U)
+/*! REG_FS_RX_ERROR_MODE2 - REG_FS_RX_ERROR_MODE2 */
+#define USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE2(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE2_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_FS_RX_ERROR_MODE2_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_ARC_DPDM_MODE_MASK (0x10U)
+#define USBC_DIGITAL_CONTRL_1_REG_ARC_DPDM_MODE_SHIFT (4U)
+/*! REG_ARC_DPDM_MODE - REG_ARC_DPDM_MODE */
+#define USBC_DIGITAL_CONTRL_1_REG_ARC_DPDM_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_ARC_DPDM_MODE_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_ARC_DPDM_MODE_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_DM_PULLDOWN_MASK (0x20U)
+#define USBC_DIGITAL_CONTRL_1_REG_DM_PULLDOWN_SHIFT (5U)
+/*! REG_DM_PULLDOWN - REG_DM_PULLDOWN */
+#define USBC_DIGITAL_CONTRL_1_REG_DM_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_DM_PULLDOWN_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_DM_PULLDOWN_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_DP_PULLDOWN_MASK (0x40U)
+#define USBC_DIGITAL_CONTRL_1_REG_DP_PULLDOWN_SHIFT (6U)
+/*! REG_DP_PULLDOWN - REG_DP_PULLDOWN */
+#define USBC_DIGITAL_CONTRL_1_REG_DP_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_DP_PULLDOWN_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_DP_PULLDOWN_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_FS_EOP_MODE_MASK (0x80U)
+#define USBC_DIGITAL_CONTRL_1_REG_FS_EOP_MODE_SHIFT (7U)
+/*! REG_FS_EOP_MODE - REG_FS_EOP_MODE */
+#define USBC_DIGITAL_CONTRL_1_REG_FS_EOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_FS_EOP_MODE_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_FS_EOP_MODE_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_UNUSED_8_MASK      (0x300U)
+#define USBC_DIGITAL_CONTRL_1_UNUSED_8_SHIFT     (8U)
+/*! UNUSED_8 - Reserved */
+#define USBC_DIGITAL_CONTRL_1_UNUSED_8(x)        (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_UNUSED_8_SHIFT)) & USBC_DIGITAL_CONTRL_1_UNUSED_8_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_NOVBUS_DPDM00_MASK (0x400U)
+#define USBC_DIGITAL_CONTRL_1_REG_NOVBUS_DPDM00_SHIFT (10U)
+/*! REG_NOVBUS_DPDM00 - REG_NOVBUS_DPDM00 */
+#define USBC_DIGITAL_CONTRL_1_REG_NOVBUS_DPDM00(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_NOVBUS_DPDM00_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_NOVBUS_DPDM00_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_FREERUNCLK_EN_MASK (0x800U)
+#define USBC_DIGITAL_CONTRL_1_REG_FREERUNCLK_EN_SHIFT (11U)
+/*! REG_FREERUNCLK_EN - REG_FREERUNCLK_EN */
+#define USBC_DIGITAL_CONTRL_1_REG_FREERUNCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_FREERUNCLK_EN_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_FREERUNCLK_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_FLSMODELP_EN_MASK (0x1000U)
+#define USBC_DIGITAL_CONTRL_1_REG_FLSMODELP_EN_SHIFT (12U)
+/*! REG_FLSMODELP_EN - REG_FLSMODELP_EN */
+#define USBC_DIGITAL_CONTRL_1_REG_FLSMODELP_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_FLSMODELP_EN_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_FLSMODELP_EN_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_OPMODE_SEL_MASK (0x2000U)
+#define USBC_DIGITAL_CONTRL_1_REG_OPMODE_SEL_SHIFT (13U)
+/*! REG_OPMODE_SEL - REG_OPMODE_SEL */
+#define USBC_DIGITAL_CONTRL_1_REG_OPMODE_SEL(x)  (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_OPMODE_SEL_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_OPMODE_SEL_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_LAT_UTMI_MASK  (0x4000U)
+#define USBC_DIGITAL_CONTRL_1_REG_LAT_UTMI_SHIFT (14U)
+/*! REG_LAT_UTMI - REG_LAT_UTMI */
+#define USBC_DIGITAL_CONTRL_1_REG_LAT_UTMI(x)    (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_LAT_UTMI_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_LAT_UTMI_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_SWAP_DPDM_MASK (0x8000U)
+#define USBC_DIGITAL_CONTRL_1_REG_SWAP_DPDM_SHIFT (15U)
+/*! REG_SWAP_DPDM - REG_SWAP_DPDM */
+#define USBC_DIGITAL_CONTRL_1_REG_SWAP_DPDM(x)   (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_SWAP_DPDM_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_SWAP_DPDM_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLEROFF_DLY_MASK (0xF0000U)
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLEROFF_DLY_SHIFT (16U)
+/*! REG_SAMPLEROFF_DLY - REG_SAMPLEROFF_DLY */
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLEROFF_DLY(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_SAMPLEROFF_DLY_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_SAMPLEROFF_DLY_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLER_ON_MASK (0x100000U)
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLER_ON_SHIFT (20U)
+/*! REG_SAMPLER_ON - REG_SAMPLER_ON */
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLER_ON(x)  (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_SAMPLER_ON_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_SAMPLER_ON_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLER_PREOFF_MASK (0x200000U)
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLER_PREOFF_SHIFT (21U)
+/*! REG_SAMPLER_PREOFF - REG_SAMPLER_PREOFF */
+#define USBC_DIGITAL_CONTRL_1_REG_SAMPLER_PREOFF(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_SAMPLER_PREOFF_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_SAMPLER_PREOFF_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_CLK_OUT_DLY_MASK (0x3FC00000U)
+#define USBC_DIGITAL_CONTRL_1_REG_CLK_OUT_DLY_SHIFT (22U)
+/*! REG_CLK_OUT_DLY - REG_CLK_OUT_DLY */
+#define USBC_DIGITAL_CONTRL_1_REG_CLK_OUT_DLY(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_CLK_OUT_DLY_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_CLK_OUT_DLY_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_LSIDLE_PRE_MASK (0x40000000U)
+#define USBC_DIGITAL_CONTRL_1_REG_LSIDLE_PRE_SHIFT (30U)
+/*! REG_LSIDLE_PRE - REG_LSIDLE_PRE */
+#define USBC_DIGITAL_CONTRL_1_REG_LSIDLE_PRE(x)  (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_LSIDLE_PRE_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_LSIDLE_PRE_MASK)
+
+#define USBC_DIGITAL_CONTRL_1_REG_VBUSON_SEL_HIGH_MASK (0x80000000U)
+#define USBC_DIGITAL_CONTRL_1_REG_VBUSON_SEL_HIGH_SHIFT (31U)
+/*! REG_VBUSON_SEL_HIGH - REG_VBUSON_SEL_HIGH */
+#define USBC_DIGITAL_CONTRL_1_REG_VBUSON_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTRL_1_REG_VBUSON_SEL_HIGH_SHIFT)) & USBC_DIGITAL_CONTRL_1_REG_VBUSON_SEL_HIGH_MASK)
+/*! @} */
+
+/*! @name TEST_CONTRL_AND_STATUS_0 - Test_Contrl_and_Status_0 */
+/*! @{ */
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_PATTERN_MASK (0xFFU)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_PATTERN_SHIFT (0U)
+/*! REG_TEST_TX_PATTERN - REG_TEST_TX_PATTERN */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_PATTERN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_PATTERN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_MODE_MASK (0x300U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_MODE_SHIFT (8U)
+/*! REG_TEST_MODE - REG_TEST_MODE */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_MODE_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_MODE_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_10_MASK (0xC00U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_10_SHIFT (10U)
+/*! UNUSED_10 - Reserved */
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_10(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_10_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_10_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SKIP_MASK (0x7000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SKIP_SHIFT (12U)
+/*! REG_TEST_SKIP - REG_TEST_SKIP */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SKIP_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SKIP_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_15_MASK (0x8000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_15_SHIFT (15U)
+/*! UNUSED_15 - Reserved */
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_15(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_15_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_15_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_OP_MODE_MASK (0x30000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_OP_MODE_SHIFT (16U)
+/*! REG_TEST_OP_MODE - REG_TEST_OP_MODE */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_OP_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_OP_MODE_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_OP_MODE_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_XVCR_SELECT_MASK (0xC0000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_XVCR_SELECT_SHIFT (18U)
+/*! REG_TEST_XVCR_SELECT - REG_TEST_XVCR_SELECT */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_XVCR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_XVCR_SELECT_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_XVCR_SELECT_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TERM_SELECT_MASK (0x100000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TERM_SELECT_SHIFT (20U)
+/*! REG_TEST_TERM_SELECT - REG_TEST_TERM_SELECT */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TERM_SELECT(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TERM_SELECT_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TERM_SELECT_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_RESET_MASK (0x200000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_RESET_SHIFT (21U)
+/*! REG_TEST_RESET - REG_TEST_RESET */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_RESET(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_RESET_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_RESET_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SUSPENDM_MASK (0x400000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SUSPENDM_SHIFT (22U)
+/*! REG_TEST_SUSPENDM - REG_TEST_SUSPENDM */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SUSPENDM_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_SUSPENDM_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_BITSTUFF_EN_MASK (0x800000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_BITSTUFF_EN_SHIFT (23U)
+/*! REG_TEST_TX_BITSTUFF_EN - REG_TEST_TX_BITSTUFF_EN */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_BITSTUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_BITSTUFF_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_TX_BITSTUFF_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_24_MASK (0x1000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_24_SHIFT (24U)
+/*! UNUSED_24 - Reserved */
+#define USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_24_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_UNUSED_24_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_UTMI_SEL_MASK (0x2000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_UTMI_SEL_SHIFT (25U)
+/*! REG_TEST_UTMI_SEL - REG_TEST_UTMI_SEL */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_UTMI_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_UTMI_SEL_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_UTMI_SEL_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_BYPASS_MASK (0x4000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_BYPASS_SHIFT (26U)
+/*! REG_TEST_BYPASS - REG_TEST_BYPASS */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_BYPASS_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_BYPASS_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_ANA_LPBK_MASK (0x8000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_ANA_LPBK_SHIFT (27U)
+/*! REG_TEST_ANA_LPBK - REG_TEST_ANA_LPBK */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_ANA_LPBK(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_ANA_LPBK_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_ANA_LPBK_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_DIG_LPBK_MASK (0x10000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_DIG_LPBK_SHIFT (28U)
+/*! REG_TEST_DIG_LPBK - REG_TEST_DIG_LPBK */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_DIG_LPBK(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_DIG_LPBK_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_DIG_LPBK_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_EN_MASK (0x20000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_EN_SHIFT (29U)
+/*! REG_TEST_EN - REG_TEST_EN */
+#define USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_REG_TEST_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_DONE_MASK (0x40000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_DONE_SHIFT (30U)
+/*! TEST_DONE - TEST_DONE */
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_DONE_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_DONE_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_FAIL_MASK (0x80000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_FAIL_SHIFT (31U)
+/*! TEST_FAIL - TEST_FAIL */
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_FAIL_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_FAIL_MASK)
+/*! @} */
+
+/*! @name TEST_CONTRL_AND_STATUS_1 - Test_Contrl_and_Status_1 */
+/*! @{ */
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_LEN_MASK (0x7FFU)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_LEN_SHIFT (0U)
+/*! TEST_LEN - TEST_LEN */
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_LEN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_LEN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_UNUSED_11_MASK (0x800U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_UNUSED_11_SHIFT (11U)
+/*! UNUSED_11 - Reserved */
+#define USBC_TEST_CONTRL_AND_STATUS_1_UNUSED_11(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_UNUSED_11_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_UNUSED_11_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_N_MASK (0x1000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_N_SHIFT (12U)
+/*! FLS_RX_N - fls_rx_n */
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_N(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_N_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_N_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_P_MASK (0x2000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_P_SHIFT (13U)
+/*! FLS_RX_P - fls_rx_p */
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_P(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_P_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_P_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_FS_LS_MASK (0x4000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_FS_LS_SHIFT (14U)
+/*! DOUT_FS_LS - dout_fs_ls */
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_FS_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_DOUT_FS_LS_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_DOUT_FS_LS_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_FORCE_EN_MASK (0x8000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_FORCE_EN_SHIFT (15U)
+/*! FLS_RX_FORCE_EN - fls_rx_force_en */
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_FORCE_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_FLS_RX_FORCE_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_VAL_MASK (0x30000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_VAL_SHIFT (16U)
+/*! LINESTATE_FORCE_VAL - linestate_force_val */
+#define USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_VAL_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_VAL_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_EN_MASK (0x40000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_EN_SHIFT (18U)
+/*! LINESTATE_FORCE_EN - linestate_force_en */
+#define USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_LINESTATE_FORCE_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_VAL_MASK (0x80000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_VAL_SHIFT (19U)
+/*! DISCON_FORCE_VAL - discon_force_val */
+#define USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_VAL_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_VAL_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_EN_MASK (0x100000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_EN_SHIFT (20U)
+/*! DISCON_FORCE_EN - discon_force_en */
+#define USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_DISCON_FORCE_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_VAL_MASK (0x200000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_VAL_SHIFT (21U)
+/*! SQ_FORCE_VAL - sq_force_val */
+#define USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_VAL_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_VAL_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_EN_MASK (0x400000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_EN_SHIFT (22U)
+/*! SQ_FORCE_EN - sq_force_en */
+#define USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_SQ_FORCE_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_VAL_MASK (0x800000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_VAL_SHIFT (23U)
+/*! DOUT_HS_FORCE_VAL - dout_hs_force_val */
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_VAL_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_VAL_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_EN_MASK (0x1000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_EN_SHIFT (24U)
+/*! DOUT_HS_FORCE_EN - dout_hs_force_en */
+#define USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_DOUT_HS_FORCE_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_DATA_MASK (0x2000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_DATA_SHIFT (25U)
+/*! HS_TX_DATA - hs_tx_data */
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_DATA_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_DATA_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_ENABLE_MASK (0x4000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_ENABLE_SHIFT (26U)
+/*! HS_TX_ENABLE - hs_tx_enable */
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_ENABLE_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_ENABLE_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_FORCE_EN_MASK (0x8000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_FORCE_EN_SHIFT (27U)
+/*! HS_TX_FORCE_EN - hs_tx_force_en */
+#define USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_FORCE_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_HS_TX_FORCE_EN_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_DAT_MASK (0x10000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_DAT_SHIFT (28U)
+/*! FLS_TX_DAT - fls_tx_dat */
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_DAT(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_DAT_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_DAT_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_SE0_MASK (0x20000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_SE0_SHIFT (29U)
+/*! FLS_TX_SE0 - fls_tx_se0 */
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_SE0_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_SE0_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_ENABLE_MASK (0x40000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_ENABLE_SHIFT (30U)
+/*! FLS_TX_ENABLE - fls_tx_enable */
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_ENABLE_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_ENABLE_MASK)
+
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_FORCE_EN_MASK (0x80000000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_FORCE_EN_SHIFT (31U)
+/*! FLS_TX_FORCE_EN - fls_tx_force_en */
+#define USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_FORCE_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_FLS_TX_FORCE_EN_MASK)
+/*! @} */
+
+/*! @name MONITOR - MONITOR */
+/*! @{ */
+
+#define USBC_MONITOR_REG_MON_SEL_MASK            (0x3FU)
+#define USBC_MONITOR_REG_MON_SEL_SHIFT           (0U)
+/*! REG_MON_SEL - REG_MON_SEL */
+#define USBC_MONITOR_REG_MON_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USBC_MONITOR_REG_MON_SEL_SHIFT)) & USBC_MONITOR_REG_MON_SEL_MASK)
+
+#define USBC_MONITOR_UNUSED_6_MASK               (0xFFC0U)
+#define USBC_MONITOR_UNUSED_6_SHIFT              (6U)
+/*! UNUSED_6 - Reserved */
+#define USBC_MONITOR_UNUSED_6(x)                 (((uint32_t)(((uint32_t)(x)) << USBC_MONITOR_UNUSED_6_SHIFT)) & USBC_MONITOR_UNUSED_6_MASK)
+
+#define USBC_MONITOR_USB_MON_MASK                (0xFFFF0000U)
+#define USBC_MONITOR_USB_MON_SHIFT               (16U)
+/*! USB_MON - USB_MON */
+#define USBC_MONITOR_USB_MON(x)                  (((uint32_t)(((uint32_t)(x)) << USBC_MONITOR_USB_MON_SHIFT)) & USBC_MONITOR_USB_MON_MASK)
+/*! @} */
+
+/*! @name RESERVE_ANA - PHY_RESERVE */
+/*! @{ */
+
+#define USBC_RESERVE_ANA_PHY_RESERVE_MASK        (0xFFFFFFFFU)
+#define USBC_RESERVE_ANA_PHY_RESERVE_SHIFT       (0U)
+/*! PHY_RESERVE - PHY_RESERVE */
+#define USBC_RESERVE_ANA_PHY_RESERVE(x)          (((uint32_t)(((uint32_t)(x)) << USBC_RESERVE_ANA_PHY_RESERVE_SHIFT)) & USBC_RESERVE_ANA_PHY_RESERVE_MASK)
+/*! @} */
+
+/*! @name PHY_REG_OTG_CONTROL - PHY_REG_OTG_CONTROL */
+/*! @{ */
+
+#define USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_MASK (0x7U)
+#define USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_SHIFT (0U)
+/*! TESTMON_OTG - TESTMON_OTG */
+#define USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG(x)  (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_MASK)
+
+#define USBC_PHY_REG_OTG_CONTROL_UNUSED_3_MASK   (0x8U)
+#define USBC_PHY_REG_OTG_CONTROL_UNUSED_3_SHIFT  (3U)
+/*! UNUSED_3 - Reserved */
+#define USBC_PHY_REG_OTG_CONTROL_UNUSED_3(x)     (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_UNUSED_3_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_UNUSED_3_MASK)
+
+#define USBC_PHY_REG_OTG_CONTROL_PU_OTG_MASK     (0x10U)
+#define USBC_PHY_REG_OTG_CONTROL_PU_OTG_SHIFT    (4U)
+/*! PU_OTG - PU_OTG */
+#define USBC_PHY_REG_OTG_CONTROL_PU_OTG(x)       (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_PU_OTG_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_PU_OTG_MASK)
+
+#define USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_MASK (0x20U)
+#define USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_SHIFT (5U)
+/*! OTG_CONTROL_BY_PIN - OTG_CONTROL_BY_PIN */
+#define USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_MASK)
+
+#define USBC_PHY_REG_OTG_CONTROL_UNUSED_7_MASK   (0xFFFFFF80U)
+#define USBC_PHY_REG_OTG_CONTROL_UNUSED_7_SHIFT  (7U)
+/*! UNUSED_7 - Reserved */
+#define USBC_PHY_REG_OTG_CONTROL_UNUSED_7(x)     (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_UNUSED_7_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_UNUSED_7_MASK)
+/*! @} */
+
+/*! @name PHY_REG_CHGDTC_CONTRL_1 - PHY_REG_CHGDTC_CONTRL_1 */
+/*! @{ */
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_TESTMON_CHRGDTC_MASK (0x3U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_TESTMON_CHRGDTC_SHIFT (0U)
+/*! TESTMON_CHRGDTC - TESTMON_CHRGDTC */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_TESTMON_CHRGDTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_TESTMON_CHRGDTC_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_TESTMON_CHRGDTC_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_MASK (0x4U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_SHIFT (2U)
+/*! CDP_EN - CDP_EN */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_MASK (0x8U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_SHIFT (3U)
+/*! DCP_EN - DCP_EN */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_MASK  (0x10U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_SHIFT (4U)
+/*! PD_EN - PD_EN */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN(x)    (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PU_CHRG_DTC_MASK (0x20U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PU_CHRG_DTC_SHIFT (5U)
+/*! PU_CHRG_DTC - PU_CHRG_DTC */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PU_CHRG_DTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_PU_CHRG_DTC_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_PU_CHRG_DTC_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_MASK (0x40U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_SHIFT (6U)
+/*! DP_DM_SWAP_CTRL - DP_DM_SWAP_CTRL */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_MASK (0x80U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_SHIFT (7U)
+/*! CDP_DM_AUTO_SWITCH - CDP_DM_AUTO_SWITCH */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_MASK (0x300U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_SHIFT (8U)
+/*! VDAT_CHARGE - VDAT_CHARGE */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_MASK (0xC00U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_SHIFT (10U)
+/*! VSRC_CHARGE - VSRC_CHARGE */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_MASK (0x1000U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_SHIFT (12U)
+/*! ENABLE_SWITCH_DP - ENABLE_SWITCH_DP */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_MASK (0x2000U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_SHIFT (13U)
+/*! ENABLE_SWITCH_DM - ENABLE_SWITCH_DM */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_MASK)
+
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_UNUSED_14_MASK (0xFFFFC000U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_UNUSED_14_SHIFT (14U)
+/*! UNUSED_14 - Reserved */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_UNUSED_14(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_UNUSED_14_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_UNUSED_14_MASK)
+/*! @} */
+
+/*! @name RESERVED - RESERVED */
+/*! @{ */
+
+#define USBC_RESERVED_RESERVED_MASK              (0xFFFFFFFFU)
+#define USBC_RESERVED_RESERVED_SHIFT             (0U)
+/*! RESERVED - RESERVED */
+#define USBC_RESERVED_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_RESERVED_SHIFT)) & USBC_RESERVED_RESERVED_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBC_Register_Masks */
+
+
+/* USBC - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral USBOTG base address */
+  #define USBOTG_BASE                              (0x50145000u)
+  /** Peripheral USBOTG base address */
+  #define USBOTG_BASE_NS                           (0x40145000u)
+  /** Peripheral USBOTG base pointer */
+  #define USBOTG                                   ((USBC_Type *)USBOTG_BASE)
+  /** Peripheral USBOTG base pointer */
+  #define USBOTG_NS                                ((USBC_Type *)USBOTG_BASE_NS)
+  /** Array initializer of USBC peripheral base addresses */
+  #define USBC_BASE_ADDRS                          { USBOTG_BASE }
+  /** Array initializer of USBC peripheral base pointers */
+  #define USBC_BASE_PTRS                           { USBOTG }
+  /** Array initializer of USBC peripheral base addresses */
+  #define USBC_BASE_ADDRS_NS                       { USBOTG_BASE_NS }
+  /** Array initializer of USBC peripheral base pointers */
+  #define USBC_BASE_PTRS_NS                        { USBOTG_NS }
+#else
+  /** Peripheral USBOTG base address */
+  #define USBOTG_BASE                              (0x40145000u)
+  /** Peripheral USBOTG base pointer */
+  #define USBOTG                                   ((USBC_Type *)USBOTG_BASE)
+  /** Array initializer of USBC peripheral base addresses */
+  #define USBC_BASE_ADDRS                          { USBOTG_BASE }
+  /** Array initializer of USBC peripheral base pointers */
+  #define USBC_BASE_PTRS                           { USBOTG }
+#endif
+/* Backward compatibility */
+#define GPTIMER0CTL                              GPTIMER0CTRL
+#define GPTIMER1CTL                              GPTIMER1CTRL
+#define USBC_SBUSCFG                             SBUSCFG
+#define EPLISTADDR                               ENDPOINTLISTADDR
+#define EPSETUPSR                                ENDPTSETUPSTAT
+#define EPPRIME                                  ENDPTPRIME
+#define EPFLUSH                                  ENDPTFLUSH
+#define EPSR                                     ENDPTSTAT
+#define EPCOMPLETE                               ENDPTCOMPLETE
+#define EPCR                                     ENDPTCTRL
+#define EPCR0                                    ENDPTCTRL0
+#define USBHS_ID_ID_MASK                         USBC_ID_ID_MASK
+#define USBHS_ID_ID_SHIFT                        USBC_ID_ID_SHIFT
+#define USBHS_ID_ID(x)                           USBC_ID_ID(x)
+#define USBHS_ID_NID_MASK                        USBC_ID_NID_MASK
+#define USBHS_ID_NID_SHIFT                       USBC_ID_NID_SHIFT
+#define USBHS_ID_NID(x)                          USBC_ID_NID(x)
+#define USBHS_ID_REVISION_MASK                   USBC_ID_REVISION_MASK
+#define USBHS_ID_REVISION_SHIFT                  USBC_ID_REVISION_SHIFT
+#define USBHS_ID_REVISION(x)                     USBC_ID_REVISION(x)
+#define USBHS_HWGENERAL_PHYW_MASK                USBC_HWGENERAL_PHYW_MASK
+#define USBHS_HWGENERAL_PHYW_SHIFT               USBC_HWGENERAL_PHYW_SHIFT
+#define USBHS_HWGENERAL_PHYW(x)                  USBC_HWGENERAL_PHYW(x)
+#define USBHS_HWGENERAL_PHYM_MASK                USBC_HWGENERAL_PHYM_MASK
+#define USBHS_HWGENERAL_PHYM_SHIFT               USBC_HWGENERAL_PHYM_SHIFT
+#define USBHS_HWGENERAL_PHYM(x)                  USBC_HWGENERAL_PHYM(x)
+#define USBHS_HWGENERAL_SM_MASK                  USBC_HWGENERAL_SM_MASK
+#define USBHS_HWGENERAL_SM_SHIFT                 USBC_HWGENERAL_SM_SHIFT
+#define USBHS_HWGENERAL_SM(x)                    USBC_HWGENERAL_SM(x)
+#define USBHS_HWHOST_HC_MASK                     USBC_HWHOST_HC_MASK
+#define USBHS_HWHOST_HC_SHIFT                    USBC_HWHOST_HC_SHIFT
+#define USBHS_HWHOST_HC(x)                       USBC_HWHOST_HC(x)
+#define USBHS_HWHOST_NPORT_MASK                  USBC_HWHOST_NPORT_MASK
+#define USBHS_HWHOST_NPORT_SHIFT                 USBC_HWHOST_NPORT_SHIFT
+#define USBHS_HWHOST_NPORT(x)                    USBC_HWHOST_NPORT(x)
+#define USBHS_HWDEVICE_DC_MASK                   USBC_HWDEVICE_DC_MASK
+#define USBHS_HWDEVICE_DC_SHIFT                  USBC_HWDEVICE_DC_SHIFT
+#define USBHS_HWDEVICE_DC(x)                     USBC_HWDEVICE_DC(x)
+#define USBHS_HWDEVICE_DEVEP_MASK                USBC_HWDEVICE_DEVEP_MASK
+#define USBHS_HWDEVICE_DEVEP_SHIFT               USBC_HWDEVICE_DEVEP_SHIFT
+#define USBHS_HWDEVICE_DEVEP(x)                  USBC_HWDEVICE_DEVEP(x)
+#define USBHS_HWTXBUF_TXBURST_MASK               USBC_HWTXBUF_TXBURST_MASK
+#define USBHS_HWTXBUF_TXBURST_SHIFT              USBC_HWTXBUF_TXBURST_SHIFT
+#define USBHS_HWTXBUF_TXBURST(x)                 USBC_HWTXBUF_TXBURST(x)
+#define USBHS_HWTXBUF_TXCHANADD_MASK             USBC_HWTXBUF_TXCHANADD_MASK
+#define USBHS_HWTXBUF_TXCHANADD_SHIFT            USBC_HWTXBUF_TXCHANADD_SHIFT
+#define USBHS_HWTXBUF_TXCHANADD(x)               USBC_HWTXBUF_TXCHANADD(x)
+#define USBHS_HWRXBUF_RXBURST_MASK               USBC_HWRXBUF_RXBURST_MASK
+#define USBHS_HWRXBUF_RXBURST_SHIFT              USBC_HWRXBUF_RXBURST_SHIFT
+#define USBHS_HWRXBUF_RXBURST(x)                 USBC_HWRXBUF_RXBURST(x)
+#define USBHS_HWRXBUF_RXADD_MASK                 USBC_HWRXBUF_RXADD_MASK
+#define USBHS_HWRXBUF_RXADD_SHIFT                USBC_HWRXBUF_RXADD_SHIFT
+#define USBHS_HWRXBUF_RXADD(x)                   USBC_HWRXBUF_RXADD(x)
+#define USBHS_GPTIMER0LD_GPTLD_MASK              USBC_GPTIMER0LD_GPTLD_MASK
+#define USBHS_GPTIMER0LD_GPTLD_SHIFT             USBC_GPTIMER0LD_GPTLD_SHIFT
+#define USBHS_GPTIMER0LD_GPTLD(x)                USBC_GPTIMER0LD_GPTLD(x)
+#define USBHS_GPTIMER0CTL_GPTCNT_MASK            USBC_GPTIMER0CTRL_GPTCNT_MASK
+#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           USBC_GPTIMER0CTRL_GPTCNT_SHIFT
+#define USBHS_GPTIMER0CTL_GPTCNT(x)              USBC_GPTIMER0CTRL_GPTCNT(x)
+#define USBHS_GPTIMER0CTL_MODE_MASK              USBC_GPTIMER0CTRL_GPTMODE_MASK
+#define USBHS_GPTIMER0CTL_MODE_SHIFT             USBC_GPTIMER0CTRL_GPTMODE_SHIFT
+#define USBHS_GPTIMER0CTL_MODE(x)                USBC_GPTIMER0CTRL_GPTMODE(x)
+#define USBHS_GPTIMER0CTL_RST_MASK               USBC_GPTIMER0CTRL_GPTRST_MASK
+#define USBHS_GPTIMER0CTL_RST_SHIFT              USBC_GPTIMER0CTRL_GPTRST_SHIFT
+#define USBHS_GPTIMER0CTL_RST(x)                 USBC_GPTIMER0CTRL_GPTRST(x)
+#define USBHS_GPTIMER0CTL_RUN_MASK               USBC_GPTIMER0CTRL_GPTRUN_MASK
+#define USBHS_GPTIMER0CTL_RUN_SHIFT              USBC_GPTIMER0CTRL_GPTRUN_SHIFT
+#define USBHS_GPTIMER0CTL_RUN(x)                 USBC_GPTIMER0CTRL_GPTRUN(x)
+#define USBHS_GPTIMER1LD_GPTLD_MASK              USBC_GPTIMER1LD_GPTLD_MASK
+#define USBHS_GPTIMER1LD_GPTLD_SHIFT             USBC_GPTIMER1LD_GPTLD_SHIFT
+#define USBHS_GPTIMER1LD_GPTLD(x)                USBC_GPTIMER1LD_GPTLD(x)
+#define USBHS_GPTIMER1CTL_GPTCNT_MASK            USBC_GPTIMER1CTRL_GPTCNT_MASK
+#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           USBC_GPTIMER1CTRL_GPTCNT_SHIFT
+#define USBHS_GPTIMER1CTL_GPTCNT(x)              USBC_GPTIMER1CTRL_GPTCNT(x)
+#define USBHS_GPTIMER1CTL_MODE_MASK              USBC_GPTIMER1CTRL_GPTMODE_MASK
+#define USBHS_GPTIMER1CTL_MODE_SHIFT             USBC_GPTIMER1CTRL_GPTMODE_SHIFT
+#define USBHS_GPTIMER1CTL_MODE(x)                USBC_GPTIMER1CTRL_GPTMODE(x)
+#define USBHS_GPTIMER1CTL_RST_MASK               USBC_GPTIMER1CTRL_GPTRST_MASK
+#define USBHS_GPTIMER1CTL_RST_SHIFT              USBC_GPTIMER1CTRL_GPTRST_SHIFT
+#define USBHS_GPTIMER1CTL_RST(x)                 USBC_GPTIMER1CTRL_GPTRST(x)
+#define USBHS_GPTIMER1CTL_RUN_MASK               USBC_GPTIMER1CTRL_GPTRUN_MASK
+#define USBHS_GPTIMER1CTL_RUN_SHIFT              USBC_GPTIMER1CTRL_GPTRUN_SHIFT
+#define USBHS_GPTIMER1CTL_RUN(x)                 USBC_GPTIMER1CTRL_GPTRUN(x)
+#define USBHS_USBC_SBUSCFG_BURSTMODE_MASK        USBC_SBUSCFG_AHBBRST_MASK
+#define USBHS_USBC_SBUSCFG_BURSTMODE_SHIFT       USBC_SBUSCFG_AHBBRST_SHIFT
+#define USBHS_USBC_SBUSCFG_BURSTMODE(x)          USBC_SBUSCFG_AHBBRST(x)
+#define USBHS_CAPLENGTH_CAPLENGTH_MASK           USBC_CAPLENGTH_CAPLENGTH_MASK
+#define USBHS_CAPLENGTH_CAPLENGTH_SHIFT          USBC_CAPLENGTH_CAPLENGTH_SHIFT
+#define USBHS_CAPLENGTH_CAPLENGTH(x)             USBC_CAPLENGTH_CAPLENGTH(x)
+#define USBHS_CAPLENGTH_HCIVERSION_MASK          USBC_CAPLENGTH_HCIVERSION_MASK
+#define USBHS_CAPLENGTH_HCIVERSION_SHIFT         USBC_CAPLENGTH_HCIVERSION_SHIFT
+#define USBHS_CAPLENGTH_HCIVERSION(x)            USBC_CAPLENGTH_HCIVERSION(x)
+#define USBHS_HCSPARAMS_N_PORTS_MASK             USBC_HCSPARAMS_N_PORTS_MASK
+#define USBHS_HCSPARAMS_N_PORTS_SHIFT            USBC_HCSPARAMS_N_PORTS_SHIFT
+#define USBHS_HCSPARAMS_N_PORTS(x)               USBC_HCSPARAMS_N_PORTS(x)
+#define USBHS_HCSPARAMS_PPC_MASK                 USBC_HCSPARAMS_PPC_MASK
+#define USBHS_HCSPARAMS_PPC_SHIFT                USBC_HCSPARAMS_PPC_SHIFT
+#define USBHS_HCSPARAMS_PPC(x)                   USBC_HCSPARAMS_PPC(x)
+#define USBHS_HCSPARAMS_N_PCC_MASK               USBC_HCSPARAMS_N_PCC_MASK
+#define USBHS_HCSPARAMS_N_PCC_SHIFT              USBC_HCSPARAMS_N_PCC_SHIFT
+#define USBHS_HCSPARAMS_N_PCC(x)                 USBC_HCSPARAMS_N_PCC(x)
+#define USBHS_HCSPARAMS_N_CC_MASK                USBC_HCSPARAMS_N_CC_MASK
+#define USBHS_HCSPARAMS_N_CC_SHIFT               USBC_HCSPARAMS_N_CC_SHIFT
+#define USBHS_HCSPARAMS_N_CC(x)                  USBC_HCSPARAMS_N_CC(x)
+#define USBHS_HCSPARAMS_PI_MASK                  USBC_HCSPARAMS_PI_MASK
+#define USBHS_HCSPARAMS_PI_SHIFT                 USBC_HCSPARAMS_PI_SHIFT
+#define USBHS_HCSPARAMS_PI(x)                    USBC_HCSPARAMS_PI(x)
+#define USBHS_HCSPARAMS_N_PTT_MASK               USBC_HCSPARAMS_N_PTT_MASK
+#define USBHS_HCSPARAMS_N_PTT_SHIFT              USBC_HCSPARAMS_N_PTT_SHIFT
+#define USBHS_HCSPARAMS_N_PTT(x)                 USBC_HCSPARAMS_N_PTT(x)
+#define USBHS_HCSPARAMS_N_TT_MASK                USBC_HCSPARAMS_N_TT_MASK
+#define USBHS_HCSPARAMS_N_TT_SHIFT               USBC_HCSPARAMS_N_TT_SHIFT
+#define USBHS_HCSPARAMS_N_TT(x)                  USBC_HCSPARAMS_N_TT(x)
+#define USBHS_HCCPARAMS_ADC_MASK                 USBC_HCCPARAMS_ADC_MASK
+#define USBHS_HCCPARAMS_ADC_SHIFT                USBC_HCCPARAMS_ADC_SHIFT
+#define USBHS_HCCPARAMS_ADC(x)                   USBC_HCCPARAMS_ADC(x)
+#define USBHS_HCCPARAMS_PFL_MASK                 USBC_HCCPARAMS_PFL_MASK
+#define USBHS_HCCPARAMS_PFL_SHIFT                USBC_HCCPARAMS_PFL_SHIFT
+#define USBHS_HCCPARAMS_PFL(x)                   USBC_HCCPARAMS_PFL(x)
+#define USBHS_HCCPARAMS_ASP_MASK                 USBC_HCCPARAMS_ASP_MASK
+#define USBHS_HCCPARAMS_ASP_SHIFT                USBC_HCCPARAMS_ASP_SHIFT
+#define USBHS_HCCPARAMS_ASP(x)                   USBC_HCCPARAMS_ASP(x)
+#define USBHS_HCCPARAMS_IST_MASK                 USBC_HCCPARAMS_IST_MASK
+#define USBHS_HCCPARAMS_IST_SHIFT                USBC_HCCPARAMS_IST_SHIFT
+#define USBHS_HCCPARAMS_IST(x)                   USBC_HCCPARAMS_IST(x)
+#define USBHS_HCCPARAMS_EECP_MASK                USBC_HCCPARAMS_EECP_MASK
+#define USBHS_HCCPARAMS_EECP_SHIFT               USBC_HCCPARAMS_EECP_SHIFT
+#define USBHS_HCCPARAMS_EECP(x)                  USBC_HCCPARAMS_EECP(x)
+#define USBHS_DCIVERSION_DCIVERSION_MASK         USBC_DCIVERSION_DCIVERSION_MASK
+#define USBHS_DCIVERSION_DCIVERSION_SHIFT        USBC_DCIVERSION_DCIVERSION_SHIFT
+#define USBHS_DCIVERSION_DCIVERSION(x)           USBC_DCIVERSION_DCIVERSION(x)
+#define USBHS_DCCPARAMS_DEN_MASK                 USBC_DCCPARAMS_DEN_MASK
+#define USBHS_DCCPARAMS_DEN_SHIFT                USBC_DCCPARAMS_DEN_SHIFT
+#define USBHS_DCCPARAMS_DEN(x)                   USBC_DCCPARAMS_DEN(x)
+#define USBHS_DCCPARAMS_DC_MASK                  USBC_DCCPARAMS_DC_MASK
+#define USBHS_DCCPARAMS_DC_SHIFT                 USBC_DCCPARAMS_DC_SHIFT
+#define USBHS_DCCPARAMS_DC(x)                    USBC_DCCPARAMS_DC(x)
+#define USBHS_DCCPARAMS_HC_MASK                  USBC_DCCPARAMS_HC_MASK
+#define USBHS_DCCPARAMS_HC_SHIFT                 USBC_DCCPARAMS_HC_SHIFT
+#define USBHS_DCCPARAMS_HC(x)                    USBC_DCCPARAMS_HC(x)
+#define USBHS_USBCMD_RS_MASK                     USBC_USBCMD_RS_MASK
+#define USBHS_USBCMD_RS_SHIFT                    USBC_USBCMD_RS_SHIFT
+#define USBHS_USBCMD_RS(x)                       USBC_USBCMD_RS(x)
+#define USBHS_USBCMD_RST_MASK                    USBC_USBCMD_RST_MASK
+#define USBHS_USBCMD_RST_SHIFT                   USBC_USBCMD_RST_SHIFT
+#define USBHS_USBCMD_RST(x)                      USBC_USBCMD_RST(x)
+#define USBHS_USBCMD_FS_MASK                     USBC_USBCMD_FS1_MASK
+#define USBHS_USBCMD_FS_SHIFT                    USBC_USBCMD_FS1_SHIFT
+#define USBHS_USBCMD_FS(x)                       USBC_USBCMD_FS1(x)
+#define USBHS_USBCMD_PSE_MASK                    USBC_USBCMD_PSE_MASK
+#define USBHS_USBCMD_PSE_SHIFT                   USBC_USBCMD_PSE_SHIFT
+#define USBHS_USBCMD_PSE(x)                      USBC_USBCMD_PSE(x)
+#define USBHS_USBCMD_ASE_MASK                    USBC_USBCMD_ASE_MASK
+#define USBHS_USBCMD_ASE_SHIFT                   USBC_USBCMD_ASE_SHIFT
+#define USBHS_USBCMD_ASE(x)                      USBC_USBCMD_ASE(x)
+#define USBHS_USBCMD_IAA_MASK                    USBC_USBCMD_IAA_MASK
+#define USBHS_USBCMD_IAA_SHIFT                   USBC_USBCMD_IAA_SHIFT
+#define USBHS_USBCMD_IAA(x)                      USBC_USBCMD_IAA(x)
+#define USBHS_USBCMD_ASP_MASK                    USBC_USBCMD_ASP_MASK
+#define USBHS_USBCMD_ASP_SHIFT                   USBC_USBCMD_ASP_SHIFT
+#define USBHS_USBCMD_ASP(x)                      USBC_USBCMD_ASP(x)
+#define USBHS_USBCMD_ASPE_MASK                   USBC_USBCMD_ASPE_MASK
+#define USBHS_USBCMD_ASPE_SHIFT                  USBC_USBCMD_ASPE_SHIFT
+#define USBHS_USBCMD_ASPE(x)                     USBC_USBCMD_ASPE(x)
+#define USBHS_USBCMD_ATDTW_MASK                  USBC_USBCMD_ATDTW_MASK
+#define USBHS_USBCMD_ATDTW_SHIFT                 USBC_USBCMD_ATDTW_SHIFT
+#define USBHS_USBCMD_ATDTW(x)                    USBC_USBCMD_ATDTW(x)
+#define USBHS_USBCMD_SUTW_MASK                   USBC_USBCMD_SUTW_MASK
+#define USBHS_USBCMD_SUTW_SHIFT                  USBC_USBCMD_SUTW_SHIFT
+#define USBHS_USBCMD_SUTW(x)                     USBC_USBCMD_SUTW(x)
+#define USBHS_USBCMD_FS2_MASK                    USBC_USBCMD_FS2_MASK
+#define USBHS_USBCMD_FS2_SHIFT                   USBC_USBCMD_FS2_SHIFT
+#define USBHS_USBCMD_FS2(x)                      USBC_USBCMD_FS2(x)
+#define USBHS_USBCMD_ITC_MASK                    USBC_USBCMD_ITC_MASK
+#define USBHS_USBCMD_ITC_SHIFT                   USBC_USBCMD_ITC_SHIFT
+#define USBHS_USBCMD_ITC(x)                      USBC_USBCMD_ITC(x)
+#define USBHS_USBSTS_UI_MASK                     USBC_USBSTS_UI_MASK
+#define USBHS_USBSTS_UI_SHIFT                    USBC_USBSTS_UI_SHIFT
+#define USBHS_USBSTS_UI(x)                       USBC_USBSTS_UI(x)
+#define USBHS_USBSTS_UEI_MASK                    USBC_USBSTS_UEI_MASK
+#define USBHS_USBSTS_UEI_SHIFT                   USBC_USBSTS_UEI_SHIFT
+#define USBHS_USBSTS_UEI(x)                      USBC_USBSTS_UEI(x)
+#define USBHS_USBSTS_PCI_MASK                    USBC_USBSTS_PCI_MASK
+#define USBHS_USBSTS_PCI_SHIFT                   USBC_USBSTS_PCI_SHIFT
+#define USBHS_USBSTS_PCI(x)                      USBC_USBSTS_PCI(x)
+#define USBHS_USBSTS_FRI_MASK                    USBC_USBSTS_FRI_MASK
+#define USBHS_USBSTS_FRI_SHIFT                   USBC_USBSTS_FRI_SHIFT
+#define USBHS_USBSTS_FRI(x)                      USBC_USBSTS_FRI(x)
+#define USBHS_USBSTS_SEI_MASK                    USBC_USBSTS_SEI_MASK
+#define USBHS_USBSTS_SEI_SHIFT                   USBC_USBSTS_SEI_SHIFT
+#define USBHS_USBSTS_SEI(x)                      USBC_USBSTS_SEI(x)
+#define USBHS_USBSTS_AAI_MASK                    USBC_USBSTS_AAI_MASK
+#define USBHS_USBSTS_AAI_SHIFT                   USBC_USBSTS_AAI_SHIFT
+#define USBHS_USBSTS_AAI(x)                      USBC_USBSTS_AAI(x)
+#define USBHS_USBSTS_URI_MASK                    USBC_USBSTS_URI_MASK
+#define USBHS_USBSTS_URI_SHIFT                   USBC_USBSTS_URI_SHIFT
+#define USBHS_USBSTS_URI(x)                      USBC_USBSTS_URI(x)
+#define USBHS_USBSTS_SRI_MASK                    USBC_USBSTS_SRI_MASK
+#define USBHS_USBSTS_SRI_SHIFT                   USBC_USBSTS_SRI_SHIFT
+#define USBHS_USBSTS_SRI(x)                      USBC_USBSTS_SRI(x)
+#define USBHS_USBSTS_SLI_MASK                    USBC_USBSTS_SLI_MASK
+#define USBHS_USBSTS_SLI_SHIFT                   USBC_USBSTS_SLI_SHIFT
+#define USBHS_USBSTS_SLI(x)                      USBC_USBSTS_SLI(x)
+#define USBHS_USBSTS_ULPII_MASK                  USBC_USBSTS_ULPII_MASK
+#define USBHS_USBSTS_ULPII_SHIFT                 USBC_USBSTS_ULPII_SHIFT
+#define USBHS_USBSTS_ULPII(x)                    USBC_USBSTS_ULPII(x)
+#define USBHS_USBSTS_HCH_MASK                    USBC_USBSTS_HCH_MASK
+#define USBHS_USBSTS_HCH_SHIFT                   USBC_USBSTS_HCH_SHIFT
+#define USBHS_USBSTS_HCH(x)                      USBC_USBSTS_HCH(x)
+#define USBHS_USBSTS_RCL_MASK                    USBC_USBSTS_RCL_MASK
+#define USBHS_USBSTS_RCL_SHIFT                   USBC_USBSTS_RCL_SHIFT
+#define USBHS_USBSTS_RCL(x)                      USBC_USBSTS_RCL(x)
+#define USBHS_USBSTS_PS_MASK                     USBC_USBSTS_PS_MASK
+#define USBHS_USBSTS_PS_SHIFT                    USBC_USBSTS_PS_SHIFT
+#define USBHS_USBSTS_PS(x)                       USBC_USBSTS_PS(x)
+#define USBHS_USBSTS_AS_MASK                     USBC_USBSTS_AS_MASK
+#define USBHS_USBSTS_AS_SHIFT                    USBC_USBSTS_AS_SHIFT
+#define USBHS_USBSTS_AS(x)                       USBC_USBSTS_AS(x)
+#define USBHS_USBSTS_NAKI_MASK                   USBC_USBSTS_NAKI_MASK
+#define USBHS_USBSTS_NAKI_SHIFT                  USBC_USBSTS_NAKI_SHIFT
+#define USBHS_USBSTS_NAKI(x)                     USBC_USBSTS_NAKI(x)
+#define USBHS_USBSTS_TI0_MASK                    USBC_USBSTS_TI0_MASK
+#define USBHS_USBSTS_TI0_SHIFT                   USBC_USBSTS_TI0_SHIFT
+#define USBHS_USBSTS_TI0(x)                      USBC_USBSTS_TI0(x)
+#define USBHS_USBSTS_TI1_MASK                    USBC_USBSTS_TI1_MASK
+#define USBHS_USBSTS_TI1_SHIFT                   USBC_USBSTS_TI1_SHIFT
+#define USBHS_USBSTS_TI1(x)                      USBC_USBSTS_TI1(x)
+#define USBHS_USBINTR_UE_MASK                    USBC_USBINTR_UE_MASK
+#define USBHS_USBINTR_UE_SHIFT                   USBC_USBINTR_UE_SHIFT
+#define USBHS_USBINTR_UE(x)                      USBC_USBINTR_UE(x)
+#define USBHS_USBINTR_UEE_MASK                   USBC_USBINTR_UEE_MASK
+#define USBHS_USBINTR_UEE_SHIFT                  USBC_USBINTR_UEE_SHIFT
+#define USBHS_USBINTR_UEE(x)                     USBC_USBINTR_UEE(x)
+#define USBHS_USBINTR_PCE_MASK                   USBC_USBINTR_PCE_MASK
+#define USBHS_USBINTR_PCE_SHIFT                  USBC_USBINTR_PCE_SHIFT
+#define USBHS_USBINTR_PCE(x)                     USBC_USBINTR_PCE(x)
+#define USBHS_USBINTR_FRE_MASK                   USBC_USBINTR_FRE_MASK
+#define USBHS_USBINTR_FRE_SHIFT                  USBC_USBINTR_FRE_SHIFT
+#define USBHS_USBINTR_FRE(x)                     USBC_USBINTR_FRE(x)
+#define USBHS_USBINTR_SEE_MASK                   USBC_USBINTR_SEE_MASK
+#define USBHS_USBINTR_SEE_SHIFT                  USBC_USBINTR_SEE_SHIFT
+#define USBHS_USBINTR_SEE(x)                     USBC_USBINTR_SEE(x)
+#define USBHS_USBINTR_AAE_MASK                   USBC_USBINTR_AAE_MASK
+#define USBHS_USBINTR_AAE_SHIFT                  USBC_USBINTR_AAE_SHIFT
+#define USBHS_USBINTR_AAE(x)                     USBC_USBINTR_AAE(x)
+#define USBHS_USBINTR_URE_MASK                   USBC_USBINTR_URE_MASK
+#define USBHS_USBINTR_URE_SHIFT                  USBC_USBINTR_URE_SHIFT
+#define USBHS_USBINTR_URE(x)                     USBC_USBINTR_URE(x)
+#define USBHS_USBINTR_SRE_MASK                   USBC_USBINTR_SRE_MASK
+#define USBHS_USBINTR_SRE_SHIFT                  USBC_USBINTR_SRE_SHIFT
+#define USBHS_USBINTR_SRE(x)                     USBC_USBINTR_SRE(x)
+#define USBHS_USBINTR_SLE_MASK                   USBC_USBINTR_SLE_MASK
+#define USBHS_USBINTR_SLE_SHIFT                  USBC_USBINTR_SLE_SHIFT
+#define USBHS_USBINTR_SLE(x)                     USBC_USBINTR_SLE(x)
+#define USBHS_USBINTR_ULPIE_MASK                 USBC_USBINTR_ULPIE_MASK
+#define USBHS_USBINTR_ULPIE_SHIFT                USBC_USBINTR_ULPIE_SHIFT
+#define USBHS_USBINTR_ULPIE(x)                   USBC_USBINTR_ULPIE(x)
+#define USBHS_USBINTR_NAKE_MASK                  USBC_USBINTR_NAKE_MASK
+#define USBHS_USBINTR_NAKE_SHIFT                 USBC_USBINTR_NAKE_SHIFT
+#define USBHS_USBINTR_NAKE(x)                    USBC_USBINTR_NAKE(x)
+#define USBHS_USBINTR_UAIE_MASK                  USBC_USBINTR_UAIE_MASK
+#define USBHS_USBINTR_UAIE_SHIFT                 USBC_USBINTR_UAIE_SHIFT
+#define USBHS_USBINTR_UAIE(x)                    USBC_USBINTR_UAIE(x)
+#define USBHS_USBINTR_UPIE_MASK                  USBC_USBINTR_UPIE_MASK
+#define USBHS_USBINTR_UPIE_SHIFT                 USBC_USBINTR_UPIE_SHIFT
+#define USBHS_USBINTR_UPIE(x)                    USBC_USBINTR_UPIE(x)
+#define USBHS_USBINTR_TIE0_MASK                  USBC_USBINTR_TIE0_MASK
+#define USBHS_USBINTR_TIE0_SHIFT                 USBC_USBINTR_TIE0_SHIFT
+#define USBHS_USBINTR_TIE0(x)                    USBC_USBINTR_TIE0(x)
+#define USBHS_USBINTR_TIE1_MASK                  USBC_USBINTR_TIE1_MASK
+#define USBHS_USBINTR_TIE1_SHIFT                 USBC_USBINTR_TIE1_SHIFT
+#define USBHS_USBINTR_TIE1(x)                    USBC_USBINTR_TIE1(x)
+#define USBHS_FRINDEX_FRINDEX_MASK               USBC_FRINDEX_FRINDEX_MASK
+#define USBHS_FRINDEX_FRINDEX_SHIFT              USBC_FRINDEX_FRINDEX_SHIFT
+#define USBHS_FRINDEX_FRINDEX(x)                 USBC_FRINDEX_FRINDEX(x)
+#define USBHS_DEVICEADDR_USBADRA_MASK            USBC_DEVICEADDR_USBADRA_MASK
+#define USBHS_DEVICEADDR_USBADRA_SHIFT           USBC_DEVICEADDR_USBADRA_SHIFT
+#define USBHS_DEVICEADDR_USBADRA(x)              USBC_DEVICEADDR_USBADRA(x)
+#define USBHS_DEVICEADDR_USBADR_MASK             USBC_DEVICEADDR_USBADR_MASK
+#define USBHS_DEVICEADDR_USBADR_SHIFT            USBC_DEVICEADDR_USBADR_SHIFT
+#define USBHS_DEVICEADDR_USBADR(x)               USBC_DEVICEADDR_USBADR(x)
+#define USBHS_PERIODICLISTBASE_PERBASE_MASK      USBC_PERIODICLISTBASE_PERBASE_MASK
+#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     USBC_PERIODICLISTBASE_PERBASE_SHIFT
+#define USBHS_PERIODICLISTBASE_PERBASE(x)        USBC_PERIODICLISTBASE_PERBASE(x)
+#define USBHS_ASYNCLISTADDR_ASYBASE_MASK         USBC_ASYNCLISTADDR_ASYBASE_MASK
+#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        USBC_ASYNCLISTADDR_ASYBASE_SHIFT
+#define USBHS_ASYNCLISTADDR_ASYBASE(x)           USBC_ASYNCLISTADDR_ASYBASE(x)
+#define USBHS_EPLISTADDR_EPBASE_MASK             USBC_ENDPOINTLISTADDR_EPBASE_MASK
+#define USBHS_EPLISTADDR_EPBASE_SHIFT            USBC_ENDPOINTLISTADDR_EPBASE_SHIFT
+#define USBHS_EPLISTADDR_EPBASE(x)               USBC_ENDPOINTLISTADDR_EPBASE(x)
+#define USBHS_BURSTSIZE_RXPBURST_MASK            USBC_BURSTSIZE_RXPBURST_MASK
+#define USBHS_BURSTSIZE_RXPBURST_SHIFT           USBC_BURSTSIZE_RXPBURST_SHIFT
+#define USBHS_BURSTSIZE_RXPBURST(x)              USBC_BURSTSIZE_RXPBURST(x)
+#define USBHS_BURSTSIZE_TXPBURST_MASK            USBC_BURSTSIZE_TXPBURST_MASK
+#define USBHS_BURSTSIZE_TXPBURST_SHIFT           USBC_BURSTSIZE_TXPBURST_SHIFT
+#define USBHS_BURSTSIZE_TXPBURST(x)              USBC_BURSTSIZE_TXPBURST(x)
+#define USBHS_TXFILLTUNING_TXSCHOH_MASK          USBC_TXFILLTUNING_TXSCHOH_MASK
+#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         USBC_TXFILLTUNING_TXSCHOH_SHIFT
+#define USBHS_TXFILLTUNING_TXSCHOH(x)            USBC_TXFILLTUNING_TXSCHOH(x)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      USBC_TXFILLTUNING_TXSCHHEALTH_MASK
+#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     USBC_TXFILLTUNING_TXSCHHEALTH_SHIFT
+#define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        USBC_TXFILLTUNING_TXSCHHEALTH(x)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      USBC_TXFILLTUNING_TXFIFOTHRES_MASK
+#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     USBC_TXFILLTUNING_TXFIFOTHRES_SHIFT
+#define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        USBC_TXFILLTUNING_TXFIFOTHRES(x)
+#define USBHS_ENDPTNAK_EPRN_MASK                 USBC_ENDPTNAK_EPRN_MASK
+#define USBHS_ENDPTNAK_EPRN_SHIFT                USBC_ENDPTNAK_EPRN_SHIFT
+#define USBHS_ENDPTNAK_EPRN(x)                   USBC_ENDPTNAK_EPRN(x)
+#define USBHS_ENDPTNAK_EPTN_MASK                 USBC_ENDPTNAK_EPTN_MASK
+#define USBHS_ENDPTNAK_EPTN_SHIFT                USBC_ENDPTNAK_EPTN_SHIFT
+#define USBHS_ENDPTNAK_EPTN(x)                   USBC_ENDPTNAK_EPTN(x)
+#define USBHS_ENDPTNAKEN_EPRNE_MASK              USBC_ENDPTNAKEN_EPRNE_MASK
+#define USBHS_ENDPTNAKEN_EPRNE_SHIFT             USBC_ENDPTNAKEN_EPRNE_SHIFT
+#define USBHS_ENDPTNAKEN_EPRNE(x)                USBC_ENDPTNAKEN_EPRNE(x)
+#define USBHS_ENDPTNAKEN_EPTNE_MASK              USBC_ENDPTNAKEN_EPTNE_MASK
+#define USBHS_ENDPTNAKEN_EPTNE_SHIFT             USBC_ENDPTNAKEN_EPTNE_SHIFT
+#define USBHS_ENDPTNAKEN_EPTNE(x)                USBC_ENDPTNAKEN_EPTNE(x)
+#define USBHS_CONFIGFLAG_CF_MASK                 USBC_CONFIGFLAG_CF_MASK
+#define USBHS_CONFIGFLAG_CF_SHIFT                USBC_CONFIGFLAG_CF_SHIFT
+#define USBHS_CONFIGFLAG_CF(x)                   USBC_CONFIGFLAG_CF(x)
+#define USBHS_PORTSC1_CCS_MASK                   USBC_PORTSC1_CCS_MASK
+#define USBHS_PORTSC1_CCS_SHIFT                  USBC_PORTSC1_CCS_SHIFT
+#define USBHS_PORTSC1_CCS(x)                     USBC_PORTSC1_CCS(x)
+#define USBHS_PORTSC1_CSC_MASK                   USBC_PORTSC1_CSC_MASK
+#define USBHS_PORTSC1_CSC_SHIFT                  USBC_PORTSC1_CSC_SHIFT
+#define USBHS_PORTSC1_CSC(x)                     USBC_PORTSC1_CSC(x)
+#define USBHS_PORTSC1_PE_MASK                    USBC_PORTSC1_PE_MASK
+#define USBHS_PORTSC1_PE_SHIFT                   USBC_PORTSC1_PE_SHIFT
+#define USBHS_PORTSC1_PE(x)                      USBC_PORTSC1_PE(x)
+#define USBHS_PORTSC1_PEC_MASK                   USBC_PORTSC1_PEC_MASK
+#define USBHS_PORTSC1_PEC_SHIFT                  USBC_PORTSC1_PEC_SHIFT
+#define USBHS_PORTSC1_PEC(x)                     USBC_PORTSC1_PEC(x)
+#define USBHS_PORTSC1_OCA_MASK                   USBC_PORTSC1_OCA_MASK
+#define USBHS_PORTSC1_OCA_SHIFT                  USBC_PORTSC1_OCA_SHIFT
+#define USBHS_PORTSC1_OCA(x)                     USBC_PORTSC1_OCA(x)
+#define USBHS_PORTSC1_OCC_MASK                   USBC_PORTSC1_OCC_MASK
+#define USBHS_PORTSC1_OCC_SHIFT                  USBC_PORTSC1_OCC_SHIFT
+#define USBHS_PORTSC1_OCC(x)                     USBC_PORTSC1_OCC(x)
+#define USBHS_PORTSC1_FPR_MASK                   USBC_PORTSC1_FPR_MASK
+#define USBHS_PORTSC1_FPR_SHIFT                  USBC_PORTSC1_FPR_SHIFT
+#define USBHS_PORTSC1_FPR(x)                     USBC_PORTSC1_FPR(x)
+#define USBHS_PORTSC1_SUSP_MASK                  USBC_PORTSC1_SUSP_MASK
+#define USBHS_PORTSC1_SUSP_SHIFT                 USBC_PORTSC1_SUSP_SHIFT
+#define USBHS_PORTSC1_SUSP(x)                    USBC_PORTSC1_SUSP(x)
+#define USBHS_PORTSC1_PR_MASK                    USBC_PORTSC1_PR_MASK
+#define USBHS_PORTSC1_PR_SHIFT                   USBC_PORTSC1_PR_SHIFT
+#define USBHS_PORTSC1_PR(x)                      USBC_PORTSC1_PR(x)
+#define USBHS_PORTSC1_HSP_MASK                   USBC_PORTSC1_HSP_MASK
+#define USBHS_PORTSC1_HSP_SHIFT                  USBC_PORTSC1_HSP_SHIFT
+#define USBHS_PORTSC1_HSP(x)                     USBC_PORTSC1_HSP(x)
+#define USBHS_PORTSC1_LS_MASK                    USBC_PORTSC1_LS_MASK
+#define USBHS_PORTSC1_LS_SHIFT                   USBC_PORTSC1_LS_SHIFT
+#define USBHS_PORTSC1_LS(x)                      USBC_PORTSC1_LS(x)
+#define USBHS_PORTSC1_PP_MASK                    USBC_PORTSC1_PP_MASK
+#define USBHS_PORTSC1_PP_SHIFT                   USBC_PORTSC1_PP_SHIFT
+#define USBHS_PORTSC1_PP(x)                      USBC_PORTSC1_PP(x)
+#define USBHS_PORTSC1_PO_MASK                    USBC_PORTSC1_PO_MASK
+#define USBHS_PORTSC1_PO_SHIFT                   USBC_PORTSC1_PO_SHIFT
+#define USBHS_PORTSC1_PO(x)                      USBC_PORTSC1_PO(x)
+#define USBHS_PORTSC1_PIC_MASK                   USBC_PORTSC1_PIC_MASK
+#define USBHS_PORTSC1_PIC_SHIFT                  USBC_PORTSC1_PIC_SHIFT
+#define USBHS_PORTSC1_PIC(x)                     USBC_PORTSC1_PIC(x)
+#define USBHS_PORTSC1_PTC_MASK                   USBC_PORTSC1_PTC_MASK
+#define USBHS_PORTSC1_PTC_SHIFT                  USBC_PORTSC1_PTC_SHIFT
+#define USBHS_PORTSC1_PTC(x)                     USBC_PORTSC1_PTC(x)
+#define USBHS_PORTSC1_WKCN_MASK                  USBC_PORTSC1_WKCN_MASK
+#define USBHS_PORTSC1_WKCN_SHIFT                 USBC_PORTSC1_WKCN_SHIFT
+#define USBHS_PORTSC1_WKCN(x)                    USBC_PORTSC1_WKCN(x)
+#define USBHS_PORTSC1_WKDS_MASK                  USBC_PORTSC1_WKDS_MASK
+#define USBHS_PORTSC1_WKDS_SHIFT                 USBC_PORTSC1_WKDS_SHIFT
+#define USBHS_PORTSC1_WKDS(x)                    USBC_PORTSC1_WKDS(x)
+#define USBHS_PORTSC1_WKOC_MASK                  USBC_PORTSC1_WKOC_MASK
+#define USBHS_PORTSC1_WKOC_SHIFT                 USBC_PORTSC1_WKOC_SHIFT
+#define USBHS_PORTSC1_WKOC(x)                    USBC_PORTSC1_WKOC(x)
+#define USBHS_PORTSC1_PHCD_MASK                  USBC_PORTSC1_PHCD_MASK
+#define USBHS_PORTSC1_PHCD_SHIFT                 USBC_PORTSC1_PHCD_SHIFT
+#define USBHS_PORTSC1_PHCD(x)                    USBC_PORTSC1_PHCD(x)
+#define USBHS_PORTSC1_PFSC_MASK                  USBC_PORTSC1_PFSC_MASK
+#define USBHS_PORTSC1_PFSC_SHIFT                 USBC_PORTSC1_PFSC_SHIFT
+#define USBHS_PORTSC1_PFSC(x)                    USBC_PORTSC1_PFSC(x)
+#define USBHS_PORTSC1_PTS2_MASK                  USBC_PORTSC1_PTS_2_MASK
+#define USBHS_PORTSC1_PTS2_SHIFT                 USBC_PORTSC1_PTS_2_SHIFT
+#define USBHS_PORTSC1_PTS2(x)                    USBC_PORTSC1_PTS_2(x)
+#define USBHS_PORTSC1_PSPD_MASK                  USBC_PORTSC1_PSPD_MASK
+#define USBHS_PORTSC1_PSPD_SHIFT                 USBC_PORTSC1_PSPD_SHIFT
+#define USBHS_PORTSC1_PSPD(x)                    USBC_PORTSC1_PSPD(x)
+#define USBHS_PORTSC1_PTW_MASK                   USBC_PORTSC1_PTW_MASK
+#define USBHS_PORTSC1_PTW_SHIFT                  USBC_PORTSC1_PTW_SHIFT
+#define USBHS_PORTSC1_PTW(x)                     USBC_PORTSC1_PTW(x)
+#define USBHS_PORTSC1_STS_MASK                   USBC_PORTSC1_STS_MASK
+#define USBHS_PORTSC1_STS_SHIFT                  USBC_PORTSC1_STS_SHIFT
+#define USBHS_PORTSC1_STS(x)                     USBC_PORTSC1_STS(x)
+#define USBHS_PORTSC1_PTS_MASK                   USBC_PORTSC1_PTS_1_MASK
+#define USBHS_PORTSC1_PTS_SHIFT                  USBC_PORTSC1_PTS_1_SHIFT
+#define USBHS_PORTSC1_PTS(x)                     USBC_PORTSC1_PTS_1(x)
+#define USBHS_OTGSC_VD_MASK                      USBC_OTGSC_VD_MASK
+#define USBHS_OTGSC_VD_SHIFT                     USBC_OTGSC_VD_SHIFT
+#define USBHS_OTGSC_VD(x)                        USBC_OTGSC_VD(x)
+#define USBHS_OTGSC_VC_MASK                      USBC_OTGSC_VC_MASK
+#define USBHS_OTGSC_VC_SHIFT                     USBC_OTGSC_VC_SHIFT
+#define USBHS_OTGSC_VC(x)                        USBC_OTGSC_VC(x)
+#define USBHS_OTGSC_OT_MASK                      USBC_OTGSC_OT_MASK
+#define USBHS_OTGSC_OT_SHIFT                     USBC_OTGSC_OT_SHIFT
+#define USBHS_OTGSC_OT(x)                        USBC_OTGSC_OT(x)
+#define USBHS_OTGSC_DP_MASK                      USBC_OTGSC_DP_MASK
+#define USBHS_OTGSC_DP_SHIFT                     USBC_OTGSC_DP_SHIFT
+#define USBHS_OTGSC_DP(x)                        USBC_OTGSC_DP(x)
+#define USBHS_OTGSC_IDPU_MASK                    USBC_OTGSC_IDPU_MASK
+#define USBHS_OTGSC_IDPU_SHIFT                   USBC_OTGSC_IDPU_SHIFT
+#define USBHS_OTGSC_IDPU(x)                      USBC_OTGSC_IDPU(x)
+#define USBHS_OTGSC_ID_MASK                      USBC_OTGSC_ID_MASK
+#define USBHS_OTGSC_ID_SHIFT                     USBC_OTGSC_ID_SHIFT
+#define USBHS_OTGSC_ID(x)                        USBC_OTGSC_ID(x)
+#define USBHS_OTGSC_AVV_MASK                     USBC_OTGSC_AVV_MASK
+#define USBHS_OTGSC_AVV_SHIFT                    USBC_OTGSC_AVV_SHIFT
+#define USBHS_OTGSC_AVV(x)                       USBC_OTGSC_AVV(x)
+#define USBHS_OTGSC_ASV_MASK                     USBC_OTGSC_ASV_MASK
+#define USBHS_OTGSC_ASV_SHIFT                    USBC_OTGSC_ASV_SHIFT
+#define USBHS_OTGSC_ASV(x)                       USBC_OTGSC_ASV(x)
+#define USBHS_OTGSC_BSV_MASK                     USBC_OTGSC_BSV_MASK
+#define USBHS_OTGSC_BSV_SHIFT                    USBC_OTGSC_BSV_SHIFT
+#define USBHS_OTGSC_BSV(x)                       USBC_OTGSC_BSV(x)
+#define USBHS_OTGSC_BSE_MASK                     USBC_OTGSC_BSE_MASK
+#define USBHS_OTGSC_BSE_SHIFT                    USBC_OTGSC_BSE_SHIFT
+#define USBHS_OTGSC_BSE(x)                       USBC_OTGSC_BSE(x)
+#define USBHS_OTGSC_MST_MASK                     USBC_OTGSC_TOG_1MS_MASK
+#define USBHS_OTGSC_MST_SHIFT                    USBC_OTGSC_TOG_1MS_SHIFT
+#define USBHS_OTGSC_MST(x)                       USBC_OTGSC_TOG_1MS(x)
+#define USBHS_OTGSC_DPS_MASK                     USBC_OTGSC_DPS_MASK
+#define USBHS_OTGSC_DPS_SHIFT                    USBC_OTGSC_DPS_SHIFT
+#define USBHS_OTGSC_DPS(x)                       USBC_OTGSC_DPS(x)
+#define USBHS_OTGSC_IDIS_MASK                    USBC_OTGSC_IDIS_MASK
+#define USBHS_OTGSC_IDIS_SHIFT                   USBC_OTGSC_IDIS_SHIFT
+#define USBHS_OTGSC_IDIS(x)                      USBC_OTGSC_IDIS(x)
+#define USBHS_OTGSC_AVVIS_MASK                   USBC_OTGSC_AVVIS_MASK
+#define USBHS_OTGSC_AVVIS_SHIFT                  USBC_OTGSC_AVVIS_SHIFT
+#define USBHS_OTGSC_AVVIS(x)                     USBC_OTGSC_AVVIS(x)
+#define USBHS_OTGSC_ASVIS_MASK                   USBC_OTGSC_ASVIS_MASK
+#define USBHS_OTGSC_ASVIS_SHIFT                  USBC_OTGSC_ASVIS_SHIFT
+#define USBHS_OTGSC_ASVIS(x)                     USBC_OTGSC_ASVIS(x)
+#define USBHS_OTGSC_BSVIS_MASK                   USBC_OTGSC_BSVIS_MASK
+#define USBHS_OTGSC_BSVIS_SHIFT                  USBC_OTGSC_BSVIS_SHIFT
+#define USBHS_OTGSC_BSVIS(x)                     USBC_OTGSC_BSVIS(x)
+#define USBHS_OTGSC_BSEIS_MASK                   USBC_OTGSC_BSEIS_MASK
+#define USBHS_OTGSC_BSEIS_SHIFT                  USBC_OTGSC_BSEIS_SHIFT
+#define USBHS_OTGSC_BSEIS(x)                     USBC_OTGSC_BSEIS(x)
+#define USBHS_OTGSC_MSS_MASK                     USBC_OTGSC_STATUS_1MS_MASK
+#define USBHS_OTGSC_MSS_SHIFT                    USBC_OTGSC_STATUS_1MS_SHIFT
+#define USBHS_OTGSC_MSS(x)                       USBC_OTGSC_STATUS_1MS(x)
+#define USBHS_OTGSC_DPIS_MASK                    USBC_OTGSC_DPIS_MASK
+#define USBHS_OTGSC_DPIS_SHIFT                   USBC_OTGSC_DPIS_SHIFT
+#define USBHS_OTGSC_DPIS(x)                      USBC_OTGSC_DPIS(x)
+#define USBHS_OTGSC_IDIE_MASK                    USBC_OTGSC_IDIE_MASK
+#define USBHS_OTGSC_IDIE_SHIFT                   USBC_OTGSC_IDIE_SHIFT
+#define USBHS_OTGSC_IDIE(x)                      USBC_OTGSC_IDIE(x)
+#define USBHS_OTGSC_AVVIE_MASK                   USBC_OTGSC_AVVIE_MASK
+#define USBHS_OTGSC_AVVIE_SHIFT                  USBC_OTGSC_AVVIE_SHIFT
+#define USBHS_OTGSC_AVVIE(x)                     USBC_OTGSC_AVVIE(x)
+#define USBHS_OTGSC_ASVIE_MASK                   USBC_OTGSC_ASVIE_MASK
+#define USBHS_OTGSC_ASVIE_SHIFT                  USBC_OTGSC_ASVIE_SHIFT
+#define USBHS_OTGSC_ASVIE(x)                     USBC_OTGSC_ASVIE(x)
+#define USBHS_OTGSC_BSVIE_MASK                   USBC_OTGSC_BSVIE_MASK
+#define USBHS_OTGSC_BSVIE_SHIFT                  USBC_OTGSC_BSVIE_SHIFT
+#define USBHS_OTGSC_BSVIE(x)                     USBC_OTGSC_BSVIE(x)
+#define USBHS_OTGSC_BSEIE_MASK                   USBC_OTGSC_BSEIE_MASK
+#define USBHS_OTGSC_BSEIE_SHIFT                  USBC_OTGSC_BSEIE_SHIFT
+#define USBHS_OTGSC_BSEIE(x)                     USBC_OTGSC_BSEIE(x)
+#define USBHS_OTGSC_MSE_MASK                     USBC_OTGSC_EN_1MS_MASK
+#define USBHS_OTGSC_MSE_SHIFT                    USBC_OTGSC_EN_1MS_SHIFT
+#define USBHS_OTGSC_MSE(x)                       USBC_OTGSC_EN_1MS(x)
+#define USBHS_OTGSC_DPIE_MASK                    USBC_OTGSC_DPIE_MASK
+#define USBHS_OTGSC_DPIE_SHIFT                   USBC_OTGSC_DPIE_SHIFT
+#define USBHS_OTGSC_DPIE(x)                      USBC_OTGSC_DPIE(x)
+#define USBHS_USBMODE_CM_MASK                    USBC_USBMODE_CM_MASK
+#define USBHS_USBMODE_CM_SHIFT                   USBC_USBMODE_CM_SHIFT
+#define USBHS_USBMODE_CM(x)                      USBC_USBMODE_CM(x)
+#define USBHS_USBMODE_ES_MASK                    USBC_USBMODE_ES_MASK
+#define USBHS_USBMODE_ES_SHIFT                   USBC_USBMODE_ES_SHIFT
+#define USBHS_USBMODE_ES(x)                      USBC_USBMODE_ES(x)
+#define USBHS_USBMODE_SLOM_MASK                  USBC_USBMODE_SLOM_MASK
+#define USBHS_USBMODE_SLOM_SHIFT                 USBC_USBMODE_SLOM_SHIFT
+#define USBHS_USBMODE_SLOM(x)                    USBC_USBMODE_SLOM(x)
+#define USBHS_USBMODE_SDIS_MASK                  USBC_USBMODE_SDIS_MASK
+#define USBHS_USBMODE_SDIS_SHIFT                 USBC_USBMODE_SDIS_SHIFT
+#define USBHS_USBMODE_SDIS(x)                    USBC_USBMODE_SDIS(x)
+#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
+#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
+#define USBHS_EPSETUPSR_EPSETUPSTAT(x)           USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
+#define USBHS_EPPRIME_PERB_MASK                  USBC_ENDPTPRIME_PERB_MASK
+#define USBHS_EPPRIME_PERB_SHIFT                 USBC_ENDPTPRIME_PERB_SHIFT
+#define USBHS_EPPRIME_PERB(x)                    USBC_ENDPTPRIME_PERB(x)
+#define USBHS_EPPRIME_PETB_MASK                  USBC_ENDPTPRIME_PETB_MASK
+#define USBHS_EPPRIME_PETB_SHIFT                 USBC_ENDPTPRIME_PETB_SHIFT
+#define USBHS_EPPRIME_PETB(x)                    USBC_ENDPTPRIME_PETB(x)
+#define USBHS_EPFLUSH_FERB_MASK                  USBC_ENDPTFLUSH_FERB_MASK
+#define USBHS_EPFLUSH_FERB_SHIFT                 USBC_ENDPTFLUSH_FERB_SHIFT
+#define USBHS_EPFLUSH_FERB(x)                    USBC_ENDPTFLUSH_FERB(x)
+#define USBHS_EPFLUSH_FETB_MASK                  USBC_ENDPTFLUSH_FETB_MASK
+#define USBHS_EPFLUSH_FETB_SHIFT                 USBC_ENDPTFLUSH_FETB_SHIFT
+#define USBHS_EPFLUSH_FETB(x)                    USBC_ENDPTFLUSH_FETB(x)
+#define USBHS_EPSR_ERBR_MASK                     USBC_ENDPTSTAT_ERBR_MASK
+#define USBHS_EPSR_ERBR_SHIFT                    USBC_ENDPTSTAT_ERBR_SHIFT
+#define USBHS_EPSR_ERBR(x)                       USBC_ENDPTSTAT_ERBR(x)
+#define USBHS_EPSR_ETBR_MASK                     USBC_ENDPTSTAT_ETBR_MASK
+#define USBHS_EPSR_ETBR_SHIFT                    USBC_ENDPTSTAT_ETBR_SHIFT
+#define USBHS_EPSR_ETBR(x)                       USBC_ENDPTSTAT_ETBR(x)
+#define USBHS_EPCOMPLETE_ERCE_MASK               USBC_ENDPTCOMPLETE_ERCE_MASK
+#define USBHS_EPCOMPLETE_ERCE_SHIFT              USBC_ENDPTCOMPLETE_ERCE_SHIFT
+#define USBHS_EPCOMPLETE_ERCE(x)                 USBC_ENDPTCOMPLETE_ERCE(x)
+#define USBHS_EPCOMPLETE_ETCE_MASK               USBC_ENDPTCOMPLETE_ETCE_MASK
+#define USBHS_EPCOMPLETE_ETCE_SHIFT              USBC_ENDPTCOMPLETE_ETCE_SHIFT
+#define USBHS_EPCOMPLETE_ETCE(x)                 USBC_ENDPTCOMPLETE_ETCE(x)
+#define USBHS_EPCR0_RXS_MASK                     USBC_ENDPTCTRL0_RXS_MASK
+#define USBHS_EPCR0_RXS_SHIFT                    USBC_ENDPTCTRL0_RXS_SHIFT
+#define USBHS_EPCR0_RXS(x)                       USBC_ENDPTCTRL0_RXS(x)
+#define USBHS_EPCR0_RXT_MASK                     USBC_ENDPTCTRL0_RXT_MASK
+#define USBHS_EPCR0_RXT_SHIFT                    USBC_ENDPTCTRL0_RXT_SHIFT
+#define USBHS_EPCR0_RXT(x)                       USBC_ENDPTCTRL0_RXT(x)
+#define USBHS_EPCR0_RXE_MASK                     USBC_ENDPTCTRL0_RXE_MASK
+#define USBHS_EPCR0_RXE_SHIFT                    USBC_ENDPTCTRL0_RXE_SHIFT
+#define USBHS_EPCR0_RXE(x)                       USBC_ENDPTCTRL0_RXE(x)
+#define USBHS_EPCR0_TXS_MASK                     USBC_ENDPTCTRL0_TXS_MASK
+#define USBHS_EPCR0_TXS_SHIFT                    USBC_ENDPTCTRL0_TXS_SHIFT
+#define USBHS_EPCR0_TXS(x)                       USBC_ENDPTCTRL0_TXS(x)
+#define USBHS_EPCR0_TXT_MASK                     USBC_ENDPTCTRL0_TXT_MASK
+#define USBHS_EPCR0_TXT_SHIFT                    USBC_ENDPTCTRL0_TXT_SHIFT
+#define USBHS_EPCR0_TXT(x)                       USBC_ENDPTCTRL0_TXT(x)
+#define USBHS_EPCR0_TXE_MASK                     USBC_ENDPTCTRL0_TXE_MASK
+#define USBHS_EPCR0_TXE_SHIFT                    USBC_ENDPTCTRL0_TXE_SHIFT
+#define USBHS_EPCR0_TXE(x)                       USBC_ENDPTCTRL0_TXE(x)
+#define USBHS_EPCR_RXS_MASK                      USBC_ENDPTCTRL_RXS_MASK
+#define USBHS_EPCR_RXS_SHIFT                     USBC_ENDPTCTRL_RXS_SHIFT
+#define USBHS_EPCR_RXS(x)                        USBC_ENDPTCTRL_RXS(x)
+#define USBHS_EPCR_RXD_MASK                      USBC_ENDPTCTRL_RXD_MASK
+#define USBHS_EPCR_RXD_SHIFT                     USBC_ENDPTCTRL_RXD_SHIFT
+#define USBHS_EPCR_RXD(x)                        USBC_ENDPTCTRL_RXD(x)
+#define USBHS_EPCR_RXT_MASK                      USBC_ENDPTCTRL_RXT_MASK
+#define USBHS_EPCR_RXT_SHIFT                     USBC_ENDPTCTRL_RXT_SHIFT
+#define USBHS_EPCR_RXT(x)                        USBC_ENDPTCTRL_RXT(x)
+#define USBHS_EPCR_RXI_MASK                      USBC_ENDPTCTRL_RXI_MASK
+#define USBHS_EPCR_RXI_SHIFT                     USBC_ENDPTCTRL_RXI_SHIFT
+#define USBHS_EPCR_RXI(x)                        USBC_ENDPTCTRL_RXI(x)
+#define USBHS_EPCR_RXR_MASK                      USBC_ENDPTCTRL_RXR_MASK
+#define USBHS_EPCR_RXR_SHIFT                     USBC_ENDPTCTRL_RXR_SHIFT
+#define USBHS_EPCR_RXR(x)                        USBC_ENDPTCTRL_RXR(x)
+#define USBHS_EPCR_RXE_MASK                      USBC_ENDPTCTRL_RXE_MASK
+#define USBHS_EPCR_RXE_SHIFT                     USBC_ENDPTCTRL_RXE_SHIFT
+#define USBHS_EPCR_RXE(x)                        USBC_ENDPTCTRL_RXE(x)
+#define USBHS_EPCR_TXS_MASK                      USBC_ENDPTCTRL_TXS_MASK
+#define USBHS_EPCR_TXS_SHIFT                     USBC_ENDPTCTRL_TXS_SHIFT
+#define USBHS_EPCR_TXS(x)                        USBC_ENDPTCTRL_TXS(x)
+#define USBHS_EPCR_TXD_MASK                      USBC_ENDPTCTRL_TXD_MASK
+#define USBHS_EPCR_TXD_SHIFT                     USBC_ENDPTCTRL_TXD_SHIFT
+#define USBHS_EPCR_TXD(x)                        USBC_ENDPTCTRL_TXD(x)
+#define USBHS_EPCR_TXT_MASK                      USBC_ENDPTCTRL_TXT_MASK
+#define USBHS_EPCR_TXT_SHIFT                     USBC_ENDPTCTRL_TXT_SHIFT
+#define USBHS_EPCR_TXT(x)                        USBC_ENDPTCTRL_TXT(x)
+#define USBHS_EPCR_TXI_MASK                      USBC_ENDPTCTRL_TXI_MASK
+#define USBHS_EPCR_TXI_SHIFT                     USBC_ENDPTCTRL_TXI_SHIFT
+#define USBHS_EPCR_TXI(x)                        USBC_ENDPTCTRL_TXI(x)
+#define USBHS_EPCR_TXR_MASK                      USBC_ENDPTCTRL_TXR_MASK
+#define USBHS_EPCR_TXR_SHIFT                     USBC_ENDPTCTRL_TXR_SHIFT
+#define USBHS_EPCR_TXR(x)                        USBC_ENDPTCTRL_TXR(x)
+#define USBHS_EPCR_TXE_MASK                      USBC_ENDPTCTRL_TXE_MASK
+#define USBHS_EPCR_TXE_SHIFT                     USBC_ENDPTCTRL_TXE_SHIFT
+#define USBHS_EPCR_TXE(x)                        USBC_ENDPTCTRL_TXE(x)
+#define USBHS_EPCR_COUNT                         USBC_ENDPTCTRL_COUNT
+#define USBHS_Type                               USBC_Type
+#define USBHS_BASE_ADDRS                         { USBOTG_BASE }
+#define USBHS_IRQS                               { USB_IRQn }
+#define USBHS_IRQHandler                         USB_IRQHandler
+
+
+/*!
+ * @}
+ */ /* end of group USBC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USIM_Peripheral_Access_Layer USIM Peripheral Access Layer
+ * @{
+ */
+
+/** USIM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t RBR;                               /**< Receive Buffer Register, offset: 0x0 */
+  __O  uint32_t THR;                               /**< Transmit Holding Register, offset: 0x4 */
+  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x8 */
+  __IO uint32_t IIR;                               /**< Interrupt Identification Register, offset: 0xC */
+  __IO uint32_t FCR;                               /**< FIFO Control Register, offset: 0x10 */
+  __I  uint32_t FSR;                               /**< FIFO Status Register, offset: 0x14 */
+  __IO uint32_t ECR;                               /**< Error Control Register, offset: 0x18 */
+  __IO uint32_t LCR;                               /**< Line Control Register, offset: 0x1C */
+  __IO uint32_t USCCR;                             /**< Card Control Register, offset: 0x20 */
+  __I  uint32_t LSR;                               /**< Line Status Register, offset: 0x24 */
+  __IO uint32_t EGTR;                              /**< Extra Guard Time Register, offset: 0x28 */
+  __IO uint32_t BGTR;                              /**< Block Guard Time Register, offset: 0x2C */
+  __IO uint32_t TOR;                               /**< Time Out Register, offset: 0x30 */
+  __IO uint32_t CLKR;                              /**< Clock Register, offset: 0x34 */
+  __IO uint32_t DLR;                               /**< Divisor Latch Register, offset: 0x38 */
+  __IO uint32_t FLR;                               /**< Factor Latch Register, offset: 0x3C */
+  __IO uint32_t CWTR;                              /**< Character Waiting Time Register, offset: 0x40 */
+  __IO uint32_t BWTR;                              /**< Block Waiting Time Register, offset: 0x44 */
+} USIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USIM_Register_Masks USIM Register Masks
+ * @{
+ */
+
+/*! @name RBR - Receive Buffer Register */
+/*! @{ */
+
+#define USIM_RBR_RB_MASK                         (0xFFU)
+#define USIM_RBR_RB_SHIFT                        (0U)
+/*! RB - Data byte received */
+#define USIM_RBR_RB(x)                           (((uint32_t)(((uint32_t)(x)) << USIM_RBR_RB_SHIFT)) & USIM_RBR_RB_MASK)
+
+#define USIM_RBR_PERR_MASK                       (0x100U)
+#define USIM_RBR_PERR_SHIFT                      (8U)
+/*! PERR - parity error bit -When not masked by the PEM bit in the FCR register, the parity error
+ *    indicator will appear in this bit.
+ */
+#define USIM_RBR_PERR(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_RBR_PERR_SHIFT)) & USIM_RBR_PERR_MASK)
+/*! @} */
+
+/*! @name THR - Transmit Holding Register */
+/*! @{ */
+
+#define USIM_THR_TB_MASK                         (0xFFU)
+#define USIM_THR_TB_SHIFT                        (0U)
+/*! TB - Data byte transmitted, leaset significant bit first */
+#define USIM_THR_TB(x)                           (((uint32_t)(((uint32_t)(x)) << USIM_THR_TB_SHIFT)) & USIM_THR_TB_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+
+#define USIM_IER_OVRN_MASK                       (0x1U)
+#define USIM_IER_OVRN_SHIFT                      (0U)
+/*! OVRN - Receiver Dta Overrun Interrupt */
+#define USIM_IER_OVRN(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_IER_OVRN_SHIFT)) & USIM_IER_OVRN_MASK)
+
+#define USIM_IER_PERR_MASK                       (0x2U)
+#define USIM_IER_PERR_SHIFT                      (1U)
+/*! PERR - Parity Error Interrupt */
+#define USIM_IER_PERR(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_IER_PERR_SHIFT)) & USIM_IER_PERR_MASK)
+
+#define USIM_IER_T0ERR_MASK                      (0x4U)
+#define USIM_IER_T0ERR_SHIFT                     (2U)
+/*! T0ERR - T=0 Error Interrupt */
+#define USIM_IER_T0ERR(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_IER_T0ERR_SHIFT)) & USIM_IER_T0ERR_MASK)
+
+#define USIM_IER_FRAMERR_MASK                    (0x8U)
+#define USIM_IER_FRAMERR_SHIFT                   (3U)
+/*! FRAMERR - Framing Error Interrupt */
+#define USIM_IER_FRAMERR(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_IER_FRAMERR_SHIFT)) & USIM_IER_FRAMERR_MASK)
+
+#define USIM_IER_TIMEO_MASK                      (0x10U)
+#define USIM_IER_TIMEO_SHIFT                     (4U)
+/*! TIMEO - Receiver Time Out Interrupt */
+#define USIM_IER_TIMEO(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_IER_TIMEO_SHIFT)) & USIM_IER_TIMEO_MASK)
+
+#define USIM_IER_CWT_MASK                        (0x20U)
+#define USIM_IER_CWT_SHIFT                       (5U)
+/*! CWT - Character Waiting Time Interrupt */
+#define USIM_IER_CWT(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IER_CWT_SHIFT)) & USIM_IER_CWT_MASK)
+
+#define USIM_IER_BWT_MASK                        (0x40U)
+#define USIM_IER_BWT_SHIFT                       (6U)
+/*! BWT - Block Waiting Time Interrupt */
+#define USIM_IER_BWT(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IER_BWT_SHIFT)) & USIM_IER_BWT_MASK)
+
+#define USIM_IER_RDR_MASK                        (0x100U)
+#define USIM_IER_RDR_SHIFT                       (8U)
+/*! RDR - Receiver Data Ready Interrupt */
+#define USIM_IER_RDR(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IER_RDR_SHIFT)) & USIM_IER_RDR_MASK)
+
+#define USIM_IER_TDR_MASK                        (0x200U)
+#define USIM_IER_TDR_SHIFT                       (9U)
+/*! TDR - Transmitter Data Refill Interrupt */
+#define USIM_IER_TDR(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IER_TDR_SHIFT)) & USIM_IER_TDR_MASK)
+
+#define USIM_IER_DMA_TIME_MASK                   (0x2000U)
+#define USIM_IER_DMA_TIME_SHIFT                  (13U)
+/*! DMA_TIME - DMA Receive Request in event of a Time Out situation */
+#define USIM_IER_DMA_TIME(x)                     (((uint32_t)(((uint32_t)(x)) << USIM_IER_DMA_TIME_SHIFT)) & USIM_IER_DMA_TIME_MASK)
+
+#define USIM_IER_DMA_RX_MASK                     (0x4000U)
+#define USIM_IER_DMA_RX_SHIFT                    (14U)
+/*! DMA_RX - DMA Receive Request */
+#define USIM_IER_DMA_RX(x)                       (((uint32_t)(((uint32_t)(x)) << USIM_IER_DMA_RX_SHIFT)) & USIM_IER_DMA_RX_MASK)
+
+#define USIM_IER_DMA_TX_MASK                     (0x8000U)
+#define USIM_IER_DMA_TX_SHIFT                    (15U)
+/*! DMA_TX - DMA Transmit Request */
+#define USIM_IER_DMA_TX(x)                       (((uint32_t)(((uint32_t)(x)) << USIM_IER_DMA_TX_SHIFT)) & USIM_IER_DMA_TX_MASK)
+/*! @} */
+
+/*! @name IIR - Interrupt Identification Register */
+/*! @{ */
+
+#define USIM_IIR_OVRN_MASK                       (0x1U)
+#define USIM_IIR_OVRN_SHIFT                      (0U)
+/*! OVRN - Receiver Data Overrun Interrupt */
+#define USIM_IIR_OVRN(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_IIR_OVRN_SHIFT)) & USIM_IIR_OVRN_MASK)
+
+#define USIM_IIR_PERR_MASK                       (0x2U)
+#define USIM_IIR_PERR_SHIFT                      (1U)
+/*! PERR - Parity Error Interrupt */
+#define USIM_IIR_PERR(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_IIR_PERR_SHIFT)) & USIM_IIR_PERR_MASK)
+
+#define USIM_IIR_T0ERR_MASK                      (0x4U)
+#define USIM_IIR_T0ERR_SHIFT                     (2U)
+/*! T0ERR - T=0 Error Interrupt */
+#define USIM_IIR_T0ERR(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_IIR_T0ERR_SHIFT)) & USIM_IIR_T0ERR_MASK)
+
+#define USIM_IIR_FRAMERR_MASK                    (0x8U)
+#define USIM_IIR_FRAMERR_SHIFT                   (3U)
+/*! FRAMERR - Framing Error Interrupt */
+#define USIM_IIR_FRAMERR(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_IIR_FRAMERR_SHIFT)) & USIM_IIR_FRAMERR_MASK)
+
+#define USIM_IIR_TIMEO_MASK                      (0x10U)
+#define USIM_IIR_TIMEO_SHIFT                     (4U)
+/*! TIMEO - Receiver Time Out Interrupt */
+#define USIM_IIR_TIMEO(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_IIR_TIMEO_SHIFT)) & USIM_IIR_TIMEO_MASK)
+
+#define USIM_IIR_CWT_MASK                        (0x20U)
+#define USIM_IIR_CWT_SHIFT                       (5U)
+/*! CWT - Character Waiting Time Interrupt */
+#define USIM_IIR_CWT(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IIR_CWT_SHIFT)) & USIM_IIR_CWT_MASK)
+
+#define USIM_IIR_BWT_MASK                        (0x40U)
+#define USIM_IIR_BWT_SHIFT                       (6U)
+/*! BWT - Block Waiting Time Interrupt */
+#define USIM_IIR_BWT(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IIR_BWT_SHIFT)) & USIM_IIR_BWT_MASK)
+
+#define USIM_IIR_RDR_MASK                        (0x100U)
+#define USIM_IIR_RDR_SHIFT                       (8U)
+/*! RDR - Receive Data Ready Interrupt */
+#define USIM_IIR_RDR(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IIR_RDR_SHIFT)) & USIM_IIR_RDR_MASK)
+
+#define USIM_IIR_TDR_MASK                        (0x200U)
+#define USIM_IIR_TDR_SHIFT                       (9U)
+/*! TDR - Transmitter Data Refill Interrupt */
+#define USIM_IIR_TDR(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_IIR_TDR_SHIFT)) & USIM_IIR_TDR_MASK)
+/*! @} */
+
+/*! @name FCR - FIFO Control Register */
+/*! @{ */
+
+#define USIM_FCR_RESETRF_MASK                    (0x1U)
+#define USIM_FCR_RESETRF_SHIFT                   (0U)
+/*! RESETRF - Reset Receive FIFO */
+#define USIM_FCR_RESETRF(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_FCR_RESETRF_SHIFT)) & USIM_FCR_RESETRF_MASK)
+
+#define USIM_FCR_RESETTF_MASK                    (0x2U)
+#define USIM_FCR_RESETTF_SHIFT                   (1U)
+/*! RESETTF - Reset Transmit FIFO */
+#define USIM_FCR_RESETTF(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_FCR_RESETTF_SHIFT)) & USIM_FCR_RESETTF_MASK)
+
+#define USIM_FCR_TX_HOLD_MASK                    (0x4U)
+#define USIM_FCR_TX_HOLD_SHIFT                   (2U)
+/*! TX_HOLD - Transmission Hold */
+#define USIM_FCR_TX_HOLD(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_FCR_TX_HOLD_SHIFT)) & USIM_FCR_TX_HOLD_MASK)
+
+#define USIM_FCR_PEM_MASK                        (0x8U)
+#define USIM_FCR_PEM_SHIFT                       (3U)
+/*! PEM - Parity Error Mask */
+#define USIM_FCR_PEM(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_FCR_PEM_SHIFT)) & USIM_FCR_PEM_MASK)
+
+#define USIM_FCR_RX_TL_MASK                      (0xC0U)
+#define USIM_FCR_RX_TL_SHIFT                     (6U)
+/*! RX_TL - Receiver Trigger Level */
+#define USIM_FCR_RX_TL(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_FCR_RX_TL_SHIFT)) & USIM_FCR_RX_TL_MASK)
+
+#define USIM_FCR_TX_TL_MASK                      (0x100U)
+#define USIM_FCR_TX_TL_SHIFT                     (8U)
+/*! TX_TL - Transmitter Trigger Level */
+#define USIM_FCR_TX_TL(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_FCR_TX_TL_SHIFT)) & USIM_FCR_TX_TL_MASK)
+/*! @} */
+
+/*! @name FSR - FIFO Status Register */
+/*! @{ */
+
+#define USIM_FSR_RX_LENGTH_MASK                  (0x1FU)
+#define USIM_FSR_RX_LENGTH_SHIFT                 (0U)
+/*! RX_LENGTH - Receive FIFO length */
+#define USIM_FSR_RX_LENGTH(x)                    (((uint32_t)(((uint32_t)(x)) << USIM_FSR_RX_LENGTH_SHIFT)) & USIM_FSR_RX_LENGTH_MASK)
+
+#define USIM_FSR_TX_LENGTH_MASK                  (0x3E0U)
+#define USIM_FSR_TX_LENGTH_SHIFT                 (5U)
+/*! TX_LENGTH - Transmit FIFO length */
+#define USIM_FSR_TX_LENGTH(x)                    (((uint32_t)(((uint32_t)(x)) << USIM_FSR_TX_LENGTH_SHIFT)) & USIM_FSR_TX_LENGTH_MASK)
+
+#define USIM_FSR_PERR_NUM_MASK                   (0x7C00U)
+#define USIM_FSR_PERR_NUM_SHIFT                  (10U)
+/*! PERR_NUM - Parity Error Number */
+#define USIM_FSR_PERR_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << USIM_FSR_PERR_NUM_SHIFT)) & USIM_FSR_PERR_NUM_MASK)
+/*! @} */
+
+/*! @name ECR - Error Control Register */
+/*! @{ */
+
+#define USIM_ECR_T0ERR_TL_MASK                   (0x3U)
+#define USIM_ECR_T0ERR_TL_SHIFT                  (0U)
+/*! T0ERR_TL - T=0 Error Trigger Level */
+#define USIM_ECR_T0ERR_TL(x)                     (((uint32_t)(((uint32_t)(x)) << USIM_ECR_T0ERR_TL_SHIFT)) & USIM_ECR_T0ERR_TL_MASK)
+
+#define USIM_ECR_PE_TL_MASK                      (0x18U)
+#define USIM_ECR_PE_TL_SHIFT                     (3U)
+/*! PE_TL - Parity Error Trigger Level */
+#define USIM_ECR_PE_TL(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_ECR_PE_TL_SHIFT)) & USIM_ECR_PE_TL_MASK)
+
+#define USIM_ECR_T0_CLR_MASK                     (0x40U)
+#define USIM_ECR_T0_CLR_SHIFT                    (6U)
+/*! T0_CLR - Clear T=0 Error */
+#define USIM_ECR_T0_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << USIM_ECR_T0_CLR_SHIFT)) & USIM_ECR_T0_CLR_MASK)
+
+#define USIM_ECR_T0_REPEAT_MASK                  (0x80U)
+#define USIM_ECR_T0_REPEAT_SHIFT                 (7U)
+/*! T0_REPEAT - Repeat Character Transmission */
+#define USIM_ECR_T0_REPEAT(x)                    (((uint32_t)(((uint32_t)(x)) << USIM_ECR_T0_REPEAT_SHIFT)) & USIM_ECR_T0_REPEAT_MASK)
+/*! @} */
+
+/*! @name LCR - Line Control Register */
+/*! @{ */
+
+#define USIM_LCR_INVERSE_MASK                    (0x1U)
+#define USIM_LCR_INVERSE_SHIFT                   (0U)
+/*! INVERSE - Bit inversion */
+#define USIM_LCR_INVERSE(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_LCR_INVERSE_SHIFT)) & USIM_LCR_INVERSE_MASK)
+
+#define USIM_LCR_ORDER_MASK                      (0x2U)
+#define USIM_LCR_ORDER_SHIFT                     (1U)
+/*! ORDER - Transmit/Receive Bit Order */
+#define USIM_LCR_ORDER(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_LCR_ORDER_SHIFT)) & USIM_LCR_ORDER_MASK)
+
+#define USIM_LCR_EPS_MASK                        (0x4U)
+#define USIM_LCR_EPS_SHIFT                       (2U)
+/*! EPS - Even Parity Select(EPS) - This bit is the even parity select bit. When EPS is a logic 0,
+ *    an odd number of logic ones is transmitted or checked in the data word bits and the parity bit.
+ *    When EPS is a logic 1, an even number of logic ones is transmitted or checked in the data
+ *    word bits and parity bit
+ */
+#define USIM_LCR_EPS(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_LCR_EPS_SHIFT)) & USIM_LCR_EPS_MASK)
+
+#define USIM_LCR_RX_T1_MASK                      (0x8U)
+#define USIM_LCR_RX_T1_SHIFT                     (3U)
+/*! RX_T1 - Receiver Protocol */
+#define USIM_LCR_RX_T1(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_LCR_RX_T1_SHIFT)) & USIM_LCR_RX_T1_MASK)
+
+#define USIM_LCR_TX_T1_MASK                      (0x10U)
+#define USIM_LCR_TX_T1_SHIFT                     (4U)
+/*! TX_T1 - Transmitter Protocol */
+#define USIM_LCR_TX_T1(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_LCR_TX_T1_SHIFT)) & USIM_LCR_TX_T1_MASK)
+/*! @} */
+
+/*! @name USCCR - Card Control Register */
+/*! @{ */
+
+#define USIM_USCCR_RST_CARD_N_MASK               (0x1U)
+#define USIM_USCCR_RST_CARD_N_SHIFT              (0U)
+/*! RST_CARD_N - Card Reset */
+#define USIM_USCCR_RST_CARD_N(x)                 (((uint32_t)(((uint32_t)(x)) << USIM_USCCR_RST_CARD_N_SHIFT)) & USIM_USCCR_RST_CARD_N_MASK)
+
+#define USIM_USCCR_VCC_MASK                      (0x2U)
+#define USIM_USCCR_VCC_SHIFT                     (1U)
+/*! VCC - Card Voltage */
+#define USIM_USCCR_VCC(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_USCCR_VCC_SHIFT)) & USIM_USCCR_VCC_MASK)
+
+#define USIM_USCCR_TXD_FORCE_MASK                (0x10U)
+#define USIM_USCCR_TXD_FORCE_SHIFT               (4U)
+/*! TXD_FORCE - Force TXD - This bit should always remain non-active unless running a deactivation
+ *    process. In deactivation the I/O must be turned low before turning down the card's voltage
+ */
+#define USIM_USCCR_TXD_FORCE(x)                  (((uint32_t)(((uint32_t)(x)) << USIM_USCCR_TXD_FORCE_SHIFT)) & USIM_USCCR_TXD_FORCE_MASK)
+/*! @} */
+
+/*! @name LSR - Line Status Register */
+/*! @{ */
+
+#define USIM_LSR_OVRN_MASK                       (0x1U)
+#define USIM_LSR_OVRN_SHIFT                      (0U)
+/*! OVRN - Receiver Data Overrun Error */
+#define USIM_LSR_OVRN(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_LSR_OVRN_SHIFT)) & USIM_LSR_OVRN_MASK)
+
+#define USIM_LSR_PERR_MASK                       (0x2U)
+#define USIM_LSR_PERR_SHIFT                      (1U)
+/*! PERR - Parity Error */
+#define USIM_LSR_PERR(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_LSR_PERR_SHIFT)) & USIM_LSR_PERR_MASK)
+
+#define USIM_LSR_T0ERR_MASK                      (0x4U)
+#define USIM_LSR_T0ERR_SHIFT                     (2U)
+/*! T0ERR - T=0 Error */
+#define USIM_LSR_T0ERR(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_LSR_T0ERR_SHIFT)) & USIM_LSR_T0ERR_MASK)
+
+#define USIM_LSR_FRAMERR_MASK                    (0x8U)
+#define USIM_LSR_FRAMERR_SHIFT                   (3U)
+/*! FRAMERR - Framing Error */
+#define USIM_LSR_FRAMERR(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_LSR_FRAMERR_SHIFT)) & USIM_LSR_FRAMERR_MASK)
+
+#define USIM_LSR_TIMEO_MASK                      (0x10U)
+#define USIM_LSR_TIMEO_SHIFT                     (4U)
+/*! TIMEO - Receiver Time Out */
+#define USIM_LSR_TIMEO(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_LSR_TIMEO_SHIFT)) & USIM_LSR_TIMEO_MASK)
+
+#define USIM_LSR_CWT_MASK                        (0x20U)
+#define USIM_LSR_CWT_SHIFT                       (5U)
+/*! CWT - Character Waiting Time */
+#define USIM_LSR_CWT(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_LSR_CWT_SHIFT)) & USIM_LSR_CWT_MASK)
+
+#define USIM_LSR_BWT_MASK                        (0x40U)
+#define USIM_LSR_BWT_SHIFT                       (6U)
+/*! BWT - Block Waiting Time */
+#define USIM_LSR_BWT(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_LSR_BWT_SHIFT)) & USIM_LSR_BWT_MASK)
+
+#define USIM_LSR_TDR_MASK                        (0x800U)
+#define USIM_LSR_TDR_SHIFT                       (11U)
+/*! TDR - Transmitter Data Refill */
+#define USIM_LSR_TDR(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_LSR_TDR_SHIFT)) & USIM_LSR_TDR_MASK)
+
+#define USIM_LSR_RX_EMPTY_N_MASK                 (0x1000U)
+#define USIM_LSR_RX_EMPTY_N_SHIFT                (12U)
+/*! RX_EMPTY_N - Receive FIFO Empty */
+#define USIM_LSR_RX_EMPTY_N(x)                   (((uint32_t)(((uint32_t)(x)) << USIM_LSR_RX_EMPTY_N_SHIFT)) & USIM_LSR_RX_EMPTY_N_MASK)
+
+#define USIM_LSR_TX_WORKING_MASK                 (0x2000U)
+#define USIM_LSR_TX_WORKING_SHIFT                (13U)
+/*! TX_WORKING - Transmitter Working */
+#define USIM_LSR_TX_WORKING(x)                   (((uint32_t)(((uint32_t)(x)) << USIM_LSR_TX_WORKING_SHIFT)) & USIM_LSR_TX_WORKING_MASK)
+
+#define USIM_LSR_RX_WORKING_MASK                 (0x4000U)
+#define USIM_LSR_RX_WORKING_SHIFT                (14U)
+/*! RX_WORKING - Receiver Working */
+#define USIM_LSR_RX_WORKING(x)                   (((uint32_t)(((uint32_t)(x)) << USIM_LSR_RX_WORKING_SHIFT)) & USIM_LSR_RX_WORKING_MASK)
+
+#define USIM_LSR_RXD_MASK                        (0x8000U)
+#define USIM_LSR_RXD_SHIFT                       (15U)
+/*! RXD - Reflects serail data from the I/O pad */
+#define USIM_LSR_RXD(x)                          (((uint32_t)(((uint32_t)(x)) << USIM_LSR_RXD_SHIFT)) & USIM_LSR_RXD_MASK)
+/*! @} */
+
+/*! @name EGTR - Extra Guard Time Register */
+/*! @{ */
+
+#define USIM_EGTR_EGTM_MASK                      (0xFFU)
+#define USIM_EGTR_EGTM_SHIFT                     (0U)
+/*! EGTM - Extra Guard Time Moments: Number of total Guard Time moments */
+#define USIM_EGTR_EGTM(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_EGTR_EGTM_SHIFT)) & USIM_EGTR_EGTM_MASK)
+/*! @} */
+
+/*! @name BGTR - Block Guard Time Register */
+/*! @{ */
+
+#define USIM_BGTR_BGT_MASK                       (0xFFU)
+#define USIM_BGTR_BGT_SHIFT                      (0U)
+/*! BGT - Block Guard TIME: Number of total Block Guard Time moments */
+#define USIM_BGTR_BGT(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_BGTR_BGT_SHIFT)) & USIM_BGTR_BGT_MASK)
+/*! @} */
+
+/*! @name TOR - Time Out Register */
+/*! @{ */
+
+#define USIM_TOR_TO_MASK                         (0xFFU)
+#define USIM_TOR_TO_SHIFT                        (0U)
+/*! TO - Time Out: Number of total Time Out moments */
+#define USIM_TOR_TO(x)                           (((uint32_t)(((uint32_t)(x)) << USIM_TOR_TO_SHIFT)) & USIM_TOR_TO_MASK)
+/*! @} */
+
+/*! @name CLKR - Clock Register */
+/*! @{ */
+
+#define USIM_CLKR_DIVISOR_MASK                   (0xFFU)
+#define USIM_CLKR_DIVISOR_SHIFT                  (0U)
+/*! DIVISOR - Clock Divisor */
+#define USIM_CLKR_DIVISOR(x)                     (((uint32_t)(((uint32_t)(x)) << USIM_CLKR_DIVISOR_SHIFT)) & USIM_CLKR_DIVISOR_MASK)
+
+#define USIM_CLKR_RQST_MASK                      (0x1000U)
+#define USIM_CLKR_RQST_SHIFT                     (12U)
+/*! RQST - Clock Change Request */
+#define USIM_CLKR_RQST(x)                        (((uint32_t)(((uint32_t)(x)) << USIM_CLKR_RQST_SHIFT)) & USIM_CLKR_RQST_MASK)
+
+#define USIM_CLKR_STOP_UCLK_MASK                 (0x2000U)
+#define USIM_CLKR_STOP_UCLK_SHIFT                (13U)
+/*! STOP_UCLK - Stop Card Clock */
+#define USIM_CLKR_STOP_UCLK(x)                   (((uint32_t)(((uint32_t)(x)) << USIM_CLKR_STOP_UCLK_SHIFT)) & USIM_CLKR_STOP_UCLK_MASK)
+
+#define USIM_CLKR_STOP_LEVEL_MASK                (0x4000U)
+#define USIM_CLKR_STOP_LEVEL_SHIFT               (14U)
+/*! STOP_LEVEL - Stop Level */
+#define USIM_CLKR_STOP_LEVEL(x)                  (((uint32_t)(((uint32_t)(x)) << USIM_CLKR_STOP_LEVEL_SHIFT)) & USIM_CLKR_STOP_LEVEL_MASK)
+
+#define USIM_CLKR_STOP_CLK_USIM_MASK             (0x8000U)
+#define USIM_CLKR_STOP_CLK_USIM_SHIFT            (15U)
+/*! STOP_CLK_USIM - Stop USIM_IF Clock */
+#define USIM_CLKR_STOP_CLK_USIM(x)               (((uint32_t)(((uint32_t)(x)) << USIM_CLKR_STOP_CLK_USIM_SHIFT)) & USIM_CLKR_STOP_CLK_USIM_MASK)
+/*! @} */
+
+/*! @name DLR - Divisor Latch Register */
+/*! @{ */
+
+#define USIM_DLR_DIVISOR_MASK                    (0xFFFFU)
+#define USIM_DLR_DIVISOR_SHIFT                   (0U)
+/*! DIVISOR - Baud Divisor - Determines the number of USIM clock in between samples, forcing the
+ *    total length of a bit to be DIVISOR*(FACTOR+1)*(USIM_CYCLE). The value zero if forbidden for
+ *    DIVISOR.
+ */
+#define USIM_DLR_DIVISOR(x)                      (((uint32_t)(((uint32_t)(x)) << USIM_DLR_DIVISOR_SHIFT)) & USIM_DLR_DIVISOR_MASK)
+/*! @} */
+
+/*! @name FLR - Factor Latch Register */
+/*! @{ */
+
+#define USIM_FLR_FACTOR_MASK                     (0xFFU)
+#define USIM_FLR_FACTOR_SHIFT                    (0U)
+/*! FACTOR - Baud Factor - Determines the number of samples per bit. Number of samples would be
+ *    (FACTOR+1). ISO standard demands minimum of 6 samples; therefore 5 is the minimum value of FACTOR
+ *    bits
+ */
+#define USIM_FLR_FACTOR(x)                       (((uint32_t)(((uint32_t)(x)) << USIM_FLR_FACTOR_SHIFT)) & USIM_FLR_FACTOR_MASK)
+/*! @} */
+
+/*! @name CWTR - Character Waiting Time Register */
+/*! @{ */
+
+#define USIM_CWTR_CWT_MASK                       (0xFFFFU)
+#define USIM_CWTR_CWT_SHIFT                      (0U)
+/*! CWT - Character Waiting Time - Number of total Character Waiting Time moments */
+#define USIM_CWTR_CWT(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_CWTR_CWT_SHIFT)) & USIM_CWTR_CWT_MASK)
+/*! @} */
+
+/*! @name BWTR - Block Waiting Time Register */
+/*! @{ */
+
+#define USIM_BWTR_BWT_MASK                       (0xFFFFU)
+#define USIM_BWTR_BWT_SHIFT                      (0U)
+/*! BWT - Block Waiting Time - Number of total Block Waiting Time moments */
+#define USIM_BWTR_BWT(x)                         (((uint32_t)(((uint32_t)(x)) << USIM_BWTR_BWT_SHIFT)) & USIM_BWTR_BWT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USIM_Register_Masks */
+
+
+/* USIM - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral USIM base address */
+  #define USIM_BASE                                (0x50008000u)
+  /** Peripheral USIM base address */
+  #define USIM_BASE_NS                             (0x40008000u)
+  /** Peripheral USIM base pointer */
+  #define USIM                                     ((USIM_Type *)USIM_BASE)
+  /** Peripheral USIM base pointer */
+  #define USIM_NS                                  ((USIM_Type *)USIM_BASE_NS)
+  /** Array initializer of USIM peripheral base addresses */
+  #define USIM_BASE_ADDRS                          { USIM_BASE }
+  /** Array initializer of USIM peripheral base pointers */
+  #define USIM_BASE_PTRS                           { USIM }
+  /** Array initializer of USIM peripheral base addresses */
+  #define USIM_BASE_ADDRS_NS                       { USIM_BASE_NS }
+  /** Array initializer of USIM peripheral base pointers */
+  #define USIM_BASE_PTRS_NS                        { USIM_NS }
+#else
+  /** Peripheral USIM base address */
+  #define USIM_BASE                                (0x40008000u)
+  /** Peripheral USIM base pointer */
+  #define USIM                                     ((USIM_Type *)USIM_BASE)
+  /** Array initializer of USIM peripheral base addresses */
+  #define USIM_BASE_ADDRS                          { USIM_BASE }
+  /** Array initializer of USIM peripheral base pointers */
+  #define USIM_BASE_PTRS                           { USIM }
+#endif
+/** Interrupt vectors for the USIM peripheral type */
+#define USIM_IRQS                                { USIM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
+  __IO uint32_t STAT;                              /**< Status, offset: 0x4 */
+  __IO uint32_t CFG;                               /**< Capture Configuration, offset: 0x8 */
+  __O  uint32_t CAPCLR;                            /**< Capture Clear, offset: 0xC */
+  __I  uint32_t CAP[4];                            /**< Capture, array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control */
+/*! @{ */
+
+#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
+/*! DELAYVAL - Tick interval */
+#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+
+#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
+/*! REPEAT - Repeat delay
+ *  0b0..One-time delay
+ *  0b1..Delay repeats continuously
+ */
+#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+/*! @} */
+
+/*! @name STAT - Status */
+/*! @{ */
+
+#define UTICK_STAT_INTR_MASK                     (0x1U)
+#define UTICK_STAT_INTR_SHIFT                    (0U)
+/*! INTR - Interrupt flag
+ *  0b0..No interrupt is pending
+ *  0b1..An interrupt is pending
+ */
+#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+
+#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
+/*! ACTIVE - Timer active flag
+ *  0b0..The Micro-Tick Timer is not active (stopped)
+ *  0b1..The Micro-Tick Timer is currently active
+ */
+#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+/*! @} */
+
+/*! @name CFG - Capture Configuration */
+/*! @{ */
+
+#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
+/*! CAPEN0 - Enable Capture 0
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+
+#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
+/*! CAPEN1 - Enable Capture 1
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+
+#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
+/*! CAPEN2 - Enable Capture 2
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+
+#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
+/*! CAPEN3 - Enable Capture 3
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+
+#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
+/*! CAPPOL0 - Capture Polarity 0
+ *  0b0..Positive edge capture
+ *  0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+
+#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
+/*! CAPPOL1 - Capture Polarity 1
+ *  0b0..Positive edge capture
+ *  0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+
+#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
+/*! CAPPOL2 - Capture Polarity 2
+ *  0b0..Positive edge capture
+ *  0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+
+#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
+/*! CAPPOL3 - Capture Polarity 3
+ *  0b0..Positive edge capture
+ *  0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+/*! @} */
+
+/*! @name CAPCLR - Capture Clear */
+/*! @{ */
+
+#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
+/*! CAPCLR0 - Clear capture 0
+ *  0b0..Does nothing
+ *  0b1..Write 1 to clear the CAP0 register value
+ */
+#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+
+#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
+/*! CAPCLR1 - Clear capture 1
+ *  0b0..Does nothing
+ *  0b1..Write 1 to clear the CAP1 register value
+ */
+#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+
+#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
+/*! CAPCLR2 - Clear capture 2
+ *  0b0..Does nothing
+ *  0b1..Write 1 to clear the CAP2 register value
+ */
+#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+
+#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
+/*! CAPCLR3 - Clear capture 3
+ *  0b0..Does nothing
+ *  0b1..Write 1 to clear the CAP3 register value
+ */
+#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+/*! @} */
+
+/*! @name CAP - Capture */
+/*! @{ */
+
+#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
+/*! CAP_VALUE - Captured value for the related capture event */
+#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+
+#define UTICK_CAP_VALID_MASK                     (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT                    (31U)
+/*! VALID - Captured value is valid
+ *  0b0..A valid value has been not been captured
+ *  0b1..A valid value has been captured, based on a transition of the related UTICK_CAPn pin
+ */
+#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+/*! @} */
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral UTICK base address */
+  #define UTICK_BASE                               (0x5000F000u)
+  /** Peripheral UTICK base address */
+  #define UTICK_BASE_NS                            (0x4000F000u)
+  /** Peripheral UTICK base pointer */
+  #define UTICK                                    ((UTICK_Type *)UTICK_BASE)
+  /** Peripheral UTICK base pointer */
+  #define UTICK_NS                                 ((UTICK_Type *)UTICK_BASE_NS)
+  /** Array initializer of UTICK peripheral base addresses */
+  #define UTICK_BASE_ADDRS                         { UTICK_BASE }
+  /** Array initializer of UTICK peripheral base pointers */
+  #define UTICK_BASE_PTRS                          { UTICK }
+  /** Array initializer of UTICK peripheral base addresses */
+  #define UTICK_BASE_ADDRS_NS                      { UTICK_BASE_NS }
+  /** Array initializer of UTICK peripheral base pointers */
+  #define UTICK_BASE_PTRS_NS                       { UTICK_NS }
+#else
+  /** Peripheral UTICK base address */
+  #define UTICK_BASE                               (0x4000F000u)
+  /** Peripheral UTICK base pointer */
+  #define UTICK                                    ((UTICK_Type *)UTICK_BASE)
+  /** Array initializer of UTICK peripheral base addresses */
+  #define UTICK_BASE_ADDRS                         { UTICK_BASE }
+  /** Array initializer of UTICK peripheral base pointers */
+  #define UTICK_BASE_PTRS                          { UTICK }
+#endif
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS                               { UTICK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WLAPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WLAPU_Peripheral_Access_Layer WLAPU Peripheral Access Layer
+ * @{
+ */
+
+/** WLAPU - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __IO uint32_t SOCWLAPU_APU_BYPASS0;              /**< APU Bypass0, offset: 0x8 */
+  __IO uint32_t SOCWLAPU_APU_PWR_CTRL_BYPASS0;     /**< APU power control Bypass Register 0, offset: 0xC */
+  __IO uint32_t SOCWLAPU_APU_PWR_CTRL_BYPASS1;     /**< APU power control Bypass Register 1, offset: 0x10 */
+  __IO uint32_t SOCWLAPU_APU_PWR_CTRL_BYPASS2;     /**< APU power control Bypass Register 2, offset: 0x14 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOCWLAPU_APU_BYPASS1;              /**< APU Bypass Register 1, offset: 0x1C */
+  __IO uint32_t SOCWLAPU_APU_BYPASS2;              /**< APU Bypass Register 2, offset: 0x20 */
+  __IO uint32_t SOCWLAPU_APU_BYPASS3;              /**< APU Bypass Register 3, offset: 0x24 */
+  __IO uint32_t SOCWLAPU_APU_CTRL;                 /**< APU Control, offset: 0x28 */
+  __I  uint32_t SOCWLAPU_APU_STATUS;               /**< APU Status Register, offset: 0x2C */
+  __IO uint32_t SOCWLAPU_CPU1_LMU_STA_BYPASS0;     /**< LMU static bank control byapss0 Register, offset: 0x30 */
+  __IO uint32_t SOCWLAPU_CPU1_LMU_STA_BYPASS1;     /**< LMU static bank control byapss1 Register, offset: 0x34 */
+  __IO uint32_t SOCWLAPU_CPU1_LMU_STA_BYPASS2;     /**< LMU static bank byapss2 Register, offset: 0x38 */
+  __IO uint32_t SOCWLAPU_LMU_DYN_BYPASS0;          /**< LMU dynamic bank control byapss0 Register, offset: 0x3C */
+  __IO uint32_t SOCWLAPU_LMU_G2BIST_CTRL_BYPASS;   /**< LMU G2Bist control bypass Register, offset: 0x40 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS; /**< LMU G2Bist control bypass Register for CPU1, offset: 0x50 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t SOCWLAPU_APU_PWR_CTRL_BYPASS4;     /**< ", offset: 0x58 */
+  __IO uint32_t SOCWLAPU_APU_PWR_CTRL_BYPASS5;     /**< ", offset: 0x5C */
+  __IO uint32_t SOCWLAPU_APU_PWR_CTRL_BYPASS6;     /**< APU power control Bypass Register 6, offset: 0x60 */
+  __IO uint32_t SOCWLAPU_APU_PWR_CTRL_BYPASS7;     /**< APU power control Bypass Register 7, offset: 0x64 */
+  __IO uint32_t SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0;  /**< LMU static bank control byapss0 Register for smu1 hybrid banks mem, offset: 0x68 */
+  __IO uint32_t SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1;  /**< LMU static bank control byapss1 Register for smu1 hybrid banks mem, offset: 0x6C */
+  __IO uint32_t SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2;  /**< LMU static bank control byapss2 Register for smu1 hybrid banks mem, offset: 0x70 */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t SOCWLAPU_APU_ECO_CTRL;             /**< APU ECO Control, offset: 0x7C */
+  __IO uint32_t SOCWLAPU_GPIO_WKUP_CTRL0;          /**< ", offset: 0x80 */
+  __IO uint32_t SOCWLAPU_GPIO_WKUP_CTRL1;          /**< ", offset: 0x84 */
+  __IO uint32_t SOCWLAPU_GPIO_WKUP_CTRL2;          /**< ", offset: 0x88 */
+  __IO uint32_t SOCWLAPU_GPIO_WKUP_CTRL3;          /**< ", offset: 0x8C */
+  __IO uint32_t SOCWLAPU_HOST_WKUP_MODE;           /**< ", offset: 0x90 */
+  __IO uint32_t SOCWLAPU_T3_CLK_DIV_EN_BYPASS;     /**< ", offset: 0x94 */
+  __IO uint32_t SOCWLAPU_LDO_LV_CTRL2;             /**< LV LDO Control 2, offset: 0x98 */
+  __IO uint32_t SOCWLAPU_CAU_BYPASS;               /**< CAU Bypass, offset: 0x9C */
+  __IO uint32_t SOCWLAPU_MEM_PWDN1;                /**< Memory Powerdown Control, offset: 0xA0 */
+  __IO uint32_t SOCWLAPU_MEM_PWDN2;                /**< Memory Powerdown Control, offset: 0xA4 */
+       uint8_t RESERVED_5[8];
+  __IO uint32_t SOCWLAPU_HOST_WKUP_SOURCE;         /**< Host Wakeup Source Control, offset: 0xB0 */
+       uint8_t RESERVED_6[12];
+  __IO uint32_t SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0; /**< APU IPS power control Bypass Register 0, offset: 0xC0 */
+} WLAPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WLAPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WLAPU_Register_Masks WLAPU Register Masks
+ * @{
+ */
+
+/*! @name SOCWLAPU_APU_BYPASS0 - APU Bypass0 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_MASK (0x1U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_SHIFT (0U)
+/*! C2P_XOSC_EN_BYPASS_EN - C2p_Xosc_En_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_MASK (0x2U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_SHIFT (1U)
+/*! TBG_TCPU_PDB_BYPASS_EN - TCPU_Pdb_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_MASK (0x4U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_SHIFT (2U)
+/*! TBG_BBU1_CLK_EN_BYPASS_EN - TBG512_320_176_BBU1_Clk_En_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_MASK (0x8U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_SHIFT (3U)
+/*! TBG_T2_PDB_BYPASS_EN - tbg t2_Pdb_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_MASK (0x10U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_SHIFT (4U)
+/*! TBG_MAC1_CLK_EN_BYPASS_EN - TBG512_320_176_MAC1_Clk_En_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_MASK (0x20U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_SHIFT (5U)
+/*! TBG_SOC_CLK_EN_BYPASS_EN - TBG512_320_176_SoC_Clk_En_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_MASK (0x40U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_SHIFT (6U)
+/*! TBG_BBU2_CLK_EN_BYPASS_EN - TBG512_320_176_BBU2_Clk_En_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_MASK (0x80U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_SHIFT (7U)
+/*! TBG_MAC2_CLK_EN_BYPASS_EN - TBG512_320_176_MAC2_Clk_En_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_EN_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_EN_SHIFT (10U)
+/*! TX_PE_BYPASS_EN - BBU_Rx_Pe_Bypass Enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_EN_MASK (0x800U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_EN_SHIFT (11U)
+/*! RX_PE_BYPASS_EN - BBU_Rx_Pe_Bypass Enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_SHIFT (12U)
+/*! RFU_PE1_BYPASS_EN - RFU_PE1_Bypass Enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_MASK (0x2000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_SHIFT (13U)
+/*! RFU_PE2_BYPASS_EN - RFU_PE2_Bypass Enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_MASK (0x4000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_SHIFT (14U)
+/*! RFU_PA_PE_A_BYPASS_EN - RFU_PA_PE_A_Bypass Enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_MASK (0x8000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_SHIFT (15U)
+/*! RFU_PA_PE_G_BYPASS_EN - RFU_PA_PE_G_Bypass Enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_MASK (0x10000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_SHIFT (16U)
+/*! C2P_XOSC_EN_BYPASS_VAL - C2p_Xosc_En Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_C2P_XOSC_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_MASK (0x20000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_SHIFT (17U)
+/*! TBG_TCPU_PDB_BYPASS_VAL - TCPU_Pdb Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_TCPU_PDB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_MASK (0x40000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_SHIFT (18U)
+/*! TBG_BBU1_CLK_EN_BYPASS_VAL - TBG512_320_176_BBU1_Clk_En Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU1_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_MASK (0x80000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_SHIFT (19U)
+/*! TBG_T2_PDB_BYPASS_VAL - TBF176_Pdb Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_T2_PDB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_MASK (0x100000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_SHIFT (20U)
+/*! TBG_MAC1_CLK_EN_BYPASS_VAL - TBG512_320_176_MAC1_Clk_En Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC1_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_MASK (0x200000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_SHIFT (21U)
+/*! TBG_SOC_CLK_EN_BYPASS_VAL - TBG512_320_176_SoC_Clk_En Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_SOC_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_MASK (0x400000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_SHIFT (22U)
+/*! TBG_BBU2_CLK_EN_BYPASS_VAL - TBG512_320_176_BBU2_Clk_En Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_BBU2_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_MASK (0x800000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_SHIFT (23U)
+/*! TBG_MAC2_CLK_EN_BYPASS_VAL - TBG512_320_176_MAC2_Clk_En Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TBG_MAC2_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_MASK (0x4000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_SHIFT (26U)
+/*! TX_PE_BYPASS_VAL - Tx_Pe Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_TX_PE_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_MASK (0x8000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_SHIFT (27U)
+/*! RX_PE_BYPASS_VAL - Rx_Pe Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RX_PE_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_MASK (0x10000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_SHIFT (28U)
+/*! RFU_PE1_BYPASS_VAL - RFU PE1 Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE1_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_MASK (0x20000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_SHIFT (29U)
+/*! RFU_PE2_BYPASS_VAL - RFU PE2 Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PE2_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_MASK (0x40000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_SHIFT (30U)
+/*! RFU_PA_PE_A_BYPASS_VAL - RFU PA_PE_A Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_A_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_MASK (0x80000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_SHIFT (31U)
+/*! RFU_PA_PE_G_BYPASS_VAL - RFU PA_PE_G Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS0_RFU_PA_PE_G_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_PWR_CTRL_BYPASS0 - APU power control Bypass Register 0 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_SHIFT (0U)
+/*! SOC_PSW_BYPASS_VAL - SoC Power Switch Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_MASK (0x2U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_SHIFT (1U)
+/*! SOC_PSW_BYPASS_EN - SoC Power Switch Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_PSW_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_MASK (0x4U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_SHIFT (2U)
+/*! SOC_FWBAR_BYPASS_VAL - SoC Firewallbar Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_MASK (0x8U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_SHIFT (3U)
+/*! SOC_FWBAR_BYPASS_EN - SoC Firewallbar Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_FWBAR_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_MASK (0x10U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_SHIFT (4U)
+/*! SOC_ISO_EN_BYPASS_VAL - SoC Isolation Cell Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_MASK (0x20U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_SHIFT (5U)
+/*! SOC_ISO_EN_BYPASS_EN - SoC Isolation Cell Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_ISO_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_MASK (0x40U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_SHIFT (6U)
+/*! SOC_CLK_DIV_RSTB_BYPASS_VAL - Firmware Bypass Value for SoC Dlk_Div_Rstb (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_MASK (0x80U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_SHIFT (7U)
+/*! SOC_CLK_DIV_RSTB_BYPASS_EN - Firmware Bypass SoC Clk_Div_Rstb from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_CLK_DIV_RSTB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_MASK (0x100U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_SHIFT (8U)
+/*! SOC_NON_UDR_RST_BYPASS_VAL - Firmware Bypass Value for SoC non udr rst (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_MASK (0x200U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_SHIFT (9U)
+/*! SOC_NON_UDR_RST_BYPASS_EN - Firmware Bypass SoC non udr rst from APU (used for brf sif only in KF2) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_NON_UDR_RST_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_EN_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_EN_SHIFT (12U)
+/*! APU_WLAN_NON_UDR_RSTB_BYPASS_EN - Firmware Bypass Value for apu_wlan_non_udr_rstb */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_VAL_MASK (0x2000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_VAL_SHIFT (13U)
+/*! APU_WLAN_NON_UDR_RSTB_BYPASS_VAL - Firmware Bypass apu_wlan_non_udr_rstb */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN_NON_UDR_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_VAL_MASK (0x10000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_VAL_SHIFT (16U)
+/*! BBUD_PSW_BYPASS_VAL - BBUD Power Switch Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_EN_MASK (0x20000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_EN_SHIFT (17U)
+/*! BBUD_PSW_BYPASS_EN - BBUD Power Switch Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_PSW_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_VAL_MASK (0x40000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_VAL_SHIFT (18U)
+/*! BBUD_FWBAR_BYPASS_VAL - BBUD Firewallbar Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_EN_MASK (0x80000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_EN_SHIFT (19U)
+/*! BBUD_FWBAR_BYPASS_EN - BBUD Firewallbar Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_FWBAR_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_VAL_MASK (0x100000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_VAL_SHIFT (20U)
+/*! BBUD_ISO_EN_BYPASS_VAL - BBUD Isolation Cell Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_EN_MASK (0x200000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_EN_SHIFT (21U)
+/*! BBUD_ISO_EN_BYPASS_EN - BBUD Isolation Cell Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_ISO_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_VAL_MASK (0x400000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_VAL_SHIFT (22U)
+/*! SOC_BBUD_NON_UDR_RSTB_BYPASS_VAL - Firmware Bypass Value for SoC_BBUD_Non_Udr_Rstb (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_EN_MASK (0x800000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_EN_SHIFT (23U)
+/*! SOC_BBUD_NON_UDR_RSTB_BYPASS_EN - Firmware Bypass SoC_BBUD_Non_Udr_Rstb from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_SOC_BBUD_NON_UDR_RSTB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_VAL_MASK (0x1000000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_VAL_SHIFT (24U)
+/*! BBUD_SRAM_PD_BYPASS_VAL - Firmware Bypass Value for SRAM_PD (active high signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_EN_MASK (0x2000000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_EN_SHIFT (25U)
+/*! BBUD_SRAM_PD_BYPASS_EN - Firmware Bypass SRAM_PD from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_BBUD_SRAM_PD_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_VAL_MASK (0x10000000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_VAL_SHIFT (28U)
+/*! APU_WLAN1_NON_UDR_RSTB_BYPASS_VAL - Firmware Bypass Value for apu_wlan1_non_udr_rst */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_EN_MASK (0x20000000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_EN_SHIFT (29U)
+/*! APU_WLAN1_NON_UDR_RSTB_BYPASS_EN - Firmware Bypass apu_wlan1_non_udr_rst */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS0_APU_WLAN1_NON_UDR_RSTB_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_PWR_CTRL_BYPASS1 - APU power control Bypass Register 1 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_VAL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_VAL_SHIFT (0U)
+/*! RFU_2G_PSW_BYPASS_VAL - RFU 2G Power Switch Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_EN_MASK (0x2U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_EN_SHIFT (1U)
+/*! RFU_2G_PSW_BYPASS_EN - RFU 2G Power Switch Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_PSW_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_VAL_MASK (0x4U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_VAL_SHIFT (2U)
+/*! RFU_2G_FWBAR_BYPASS_VAL - RFU Firewallbar Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_EN_MASK (0x8U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_EN_SHIFT (3U)
+/*! RFU_2G_FWBAR_BYPASS_EN - RFU 2G Firewallbar Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_FWBAR_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_VAL_MASK (0x10U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_VAL_SHIFT (4U)
+/*! RFU_2G_ISO_EN_BYPASS_VAL - RFU 2G Isolation Cell Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_EN_MASK (0x20U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_EN_SHIFT (5U)
+/*! RFU_2G_ISO_EN_BYPASS_EN - RFU 2G Isolation Cell Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_ISO_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_VAL_MASK (0x40U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_VAL_SHIFT (6U)
+/*! RFU_2G_CLK_DIV_RSTB_BYPASS_VAL - Firmware Bypass Value for RFU 2G Clk_Div_Rstb (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_EN_MASK (0x80U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_EN_SHIFT (7U)
+/*! RFU_2G_CLK_DIV_RSTB_BYPASS_EN - Firmware Bypass RFU 2G Clk_Div_Rstb from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_CLK_DIV_RSTB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_VAL_MASK (0x100U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_VAL_SHIFT (8U)
+/*! RFU_2G_SRAM_PD_BYPASS_VAL - Firmware Bypass Value for RFU 2G SRAM_PD (active high signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_EN_MASK (0x200U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_EN_SHIFT (9U)
+/*! RFU_2G_SRAM_PD_BYPASS_EN - Firmware Bypass RFU 2G SRAM_PD from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS1_RFU_2G_SRAM_PD_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_PWR_CTRL_BYPASS2 - APU power control Bypass Register 2 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_VAL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_VAL_SHIFT (0U)
+/*! WLAN_PD_PSW_BYPASS_VAL - wlan_pd Power Switch Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_EN_MASK (0x2U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_EN_SHIFT (1U)
+/*! WLAN_PD_PSW_BYPASS_EN - wlan_pd Power Switch Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_PSW_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_VAL_MASK (0x4U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_VAL_SHIFT (2U)
+/*! WLAN_PD_FWBAR_BYPASS_VAL - wlan_pd Firewallbar Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_EN_MASK (0x8U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_EN_SHIFT (3U)
+/*! WLAN_PD_FWBAR_BYPASS_EN - wlan_pd Firewallbar Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_FWBAR_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_VAL_MASK (0x10U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_VAL_SHIFT (4U)
+/*! WLAN_PD_ISO_EN_BYPASS_VAL - wlan_pd Isolation Cell Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_EN_MASK (0x20U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_EN_SHIFT (5U)
+/*! WLAN_PD_ISO_EN_BYPASS_EN - wlan_pd Isolation Cell Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_ISO_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_VAL_MASK (0x40U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_VAL_SHIFT (6U)
+/*! WLAN_PD_CLK_DIV_RSTB_BYPASS_VAL - Firmware Bypass Value for wlan_pd Clk_Div_Rstb (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_EN_MASK (0x80U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_EN_SHIFT (7U)
+/*! WLAN_PD_CLK_DIV_RSTB_BYPASS_EN - Firmware Bypass wlan_pd Clk_Div_Rstb from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_CLK_DIV_RSTB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_VAL_MASK (0x100U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_VAL_SHIFT (8U)
+/*! WLAN_PD_SRAM_PD_BYPASS_VAL - Firmware Bypass Value for SRAM_PD (active high signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_EN_MASK (0x200U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_EN_SHIFT (9U)
+/*! WLAN_PD_SRAM_PD_BYPASS_EN - Firmware Bypass SRAM_PD from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_PD_SRAM_PD_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_VAL_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_VAL_SHIFT (10U)
+/*! WLAN_RET_PD_PSW_BYPASS_VAL - wlan_ret_pd_psw_bypass_val */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_EN_MASK (0x800U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_EN_SHIFT (11U)
+/*! WLAN_RET_PD_PSW_BYPASS_EN - wlan_ret_pd Power Switch Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS2_WLAN_RET_PD_PSW_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_BYPASS1 - APU Bypass Register 1 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_MASK (0x40U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_SHIFT (6U)
+/*! SOC_CAU_XOSC_EN_BP_EN - Firmware Bypass Xosc_En to CAU and other parts of the chip including pads */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_MASK (0x80U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_SHIFT (7U)
+/*! SOC_CAU_XOSC_EN_BP_VAL - Firmware Bypass Xosc_En Value for SoC_CAU_Xosc_En_Bp_En */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_SOC_CAU_XOSC_EN_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_RXPE_DYN_BYPASS_MASK (0x100U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_RXPE_DYN_BYPASS_SHIFT (8U)
+/*! RXPE_DYN_BYPASS - Rxpe_Dyn_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_RXPE_DYN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_RXPE_DYN_BYPASS_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_RXPE_DYN_BYPASS_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_PE1_DYN_BYPASS_MASK (0x200U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_PE1_DYN_BYPASS_SHIFT (9U)
+/*! PE1_DYN_BYPASS - PE1_Dyn_Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_PE1_DYN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_PE1_DYN_BYPASS_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_PE1_DYN_BYPASS_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_SHIFT (10U)
+/*! PLL_OVERRIDE_BYPASS - PLL Override Bypass */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_PLL_OVERRIDE_BYPASS_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_MASK (0x40000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_SHIFT (18U)
+/*! BCA_CLK_EN_BYPASS_EN - Firmware Bypass BCA_Clk_En */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_MASK (0x80000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_SHIFT (19U)
+/*! BCA_CLK_EN_BYPASS_VAL - Firmware Bypass Value for BCA_Clk_En (active high signal) */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_BCA_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_MASK (0x4000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_SHIFT (26U)
+/*! SLNA_CLK_EN_BYPASS_EN - Firmware Bypass for SLNA_Clk_En */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_MASK (0x8000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_SHIFT (27U)
+/*! SLNA_CLK_EN_BYPASS_VAL - Firmware Bypass Value for SLNA_Clk_En (active high signal) */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_SLNA_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_EN_MASK (0x10000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_EN_SHIFT (28U)
+/*! APU_WL_RF_CLK_EN_BYPASS_EN - Firmware Bypass for APU_WL_RF_Clk_En */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_VAL_MASK (0x20000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_VAL_SHIFT (29U)
+/*! APU_WL_RF_CLK_EN_BYPASS_VAL - Firmware Bypass Value for APU_WL_RF_Clk_En (active high signal) */
+#define WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS1_APU_WL_RF_CLK_EN_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_BYPASS2 - APU Bypass Register 2 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_MASK (0x100U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_SHIFT (8U)
+/*! TBG_T3_PDB_BYPASS_EN - Firmware Bypass for T3_pdb pll */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_MASK (0x200U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_SHIFT (9U)
+/*! TBG_T3_PDB_BYPASS_VAL - T3_Pdb Bypass Value */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T3_PDB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_SHIFT (10U)
+/*! T3_PI1_PDB_BYPASS_EN - Firmware Bypass for TBG256 aiu_pi1 */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_MASK (0x800U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_SHIFT (11U)
+/*! T3_PI1_PDB_BYPASS_VAL - Firmware Bypass Value for TBG256 aiu pi1 */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI1_PDB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_SHIFT (12U)
+/*! T3_PI2_PDB_BYPASS_EN - Firmware Bypass for TBG256 aiu_pi2 */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_MASK (0x2000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_SHIFT (13U)
+/*! T3_PI2_PDB_BYPASS_VAL - Firmware Bypass Value for TBG256 aiu_pi2 */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_T3_PI2_PDB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_MASK (0x2000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_SHIFT (25U)
+/*! TBG_T1_STABLE_BYPASS_EN - Firmware Bypass enable for T1 pll_stable signal from APU */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_MASK (0x4000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_SHIFT (26U)
+/*! TBG_T1_STABLE_BYPASS_VAL - Firmware Bypass value for T1 pll_stable signal from APU */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_TBG_T1_STABLE_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_MASK (0x8000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_SHIFT (27U)
+/*! PMIC_DVSC_CTRL_BYPASS_EN - Firmware Bypass enable for pmic dvsc ctrl from APU */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_MASK (0x30000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_SHIFT (28U)
+/*! PMIC_DVSC_CTRL_BYPASS_VAL - Firmware Bypass value for pmic dvsc ctrl from APU (default high power WLAN ode) */
+#define WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS2_PMIC_DVSC_CTRL_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_BYPASS3 - APU Bypass Register 3 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_MASK (0x10U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_SHIFT (4U)
+/*! SYS_CLK_EN_BYPASS_EN - Firmware Bypass for sys clock domain clock enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_MASK (0x20U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_SHIFT (5U)
+/*! SYS_CLK_EN_BYPASS_VAL - Firmware Bypass Value for sys clock domain clock enable(active high signal) */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_SYS_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_EN_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_EN_SHIFT (10U)
+/*! WLAN1_PD_CLK_EN_BYPASS_EN - Firmware Bypass for WLAN1 PD domain clock enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_VAL_MASK (0x800U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_VAL_SHIFT (11U)
+/*! WLAN1_PD_CLK_EN_BYPASS_VAL - Firmware Bypass Value for WLAN1 PD domain clock enable(active high signal) */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_PD_CLK_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_EN_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_EN_SHIFT (12U)
+/*! WLAN1_CLK_DIV_EN_BYPASS_EN - Firmware Bypass for WLAN1 clocks divider clock enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_VAL_MASK (0x2000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_VAL_SHIFT (13U)
+/*! WLAN1_CLK_DIV_EN_BYPASS_VAL - Firmware Bypass Value for WLAN1 clocks divider enable(active high signal) */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_WLAN1_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_MASK (0x4000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_SHIFT (14U)
+/*! SPSRAM_RST_BYPASS_EN - Firmware Bypass for Single power SRAM reset enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_MASK (0x8000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_SHIFT (15U)
+/*! SPSRAM_RST_BYPASS_VAL - Firmware Bypass Value for single power sram reset(active low signal) */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_SPSRAM_RST_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_MASK (0x10000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_SHIFT (16U)
+/*! SLNA_BBUD_BRF_BYPASS_EN - Firmware Bypass for apu mux control of SLNA gain from bbud/brf */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_MASK (0x20000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_SHIFT (17U)
+/*! SLNA_BBUD_BRF_BYPASS_VAL - Firmware Bypass Value for apu mux control of SLNA gain from bbud/brf */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_SLNA_BBUD_BRF_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_EN_MASK (0x1000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_EN_SHIFT (24U)
+/*! RFU_REF_CLK_EN1_BYPASS_EN - Firmware Bypass Enable for RFU5G reference clk enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_VAL_MASK (0x2000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_VAL_SHIFT (25U)
+/*! RFU_REF_CLK_EN1_BYPASS_VAL - Firmware Bypass Value for RFU5G reference clk enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN1_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_EN_MASK (0x4000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_EN_SHIFT (26U)
+/*! RFU_REF_CLK_EN2_BYPASS_EN - Firmware Bypass Enable for RFU2G reference clk enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_VAL_MASK (0x8000000U)
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_VAL_SHIFT (27U)
+/*! RFU_REF_CLK_EN2_BYPASS_VAL - Firmware Bypass Value for RFU2G reference clk enable */
+#define WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_BYPASS3_RFU_REF_CLK_EN2_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_CTRL - APU Control */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_REFCLK_DIV_SEL_MASK (0xFU)
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_REFCLK_DIV_SEL_SHIFT (0U)
+/*! APU_REFCLK_DIV_SEL - APU Reference Clock Divider Select */
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_REFCLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_APU_REFCLK_DIV_SEL_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_APU_REFCLK_DIV_SEL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_FORCE_BTU_WAKEUP_MASK (0x10U)
+#define WLAPU_SOCWLAPU_APU_CTRL_FORCE_BTU_WAKEUP_SHIFT (4U)
+/*! FORCE_BTU_WAKEUP - Force BTU Wakeup */
+#define WLAPU_SOCWLAPU_APU_CTRL_FORCE_BTU_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_FORCE_BTU_WAKEUP_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_FORCE_BTU_WAKEUP_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_ISU_WKUP_IN_USE_MASK (0x40U)
+#define WLAPU_SOCWLAPU_APU_CTRL_ISU_WKUP_IN_USE_SHIFT (6U)
+/*! ISU_WKUP_IN_USE - APU Wakeup */
+#define WLAPU_SOCWLAPU_APU_CTRL_ISU_WKUP_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_ISU_WKUP_IN_USE_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_ISU_WKUP_IN_USE_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_MASK (0x80U)
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_SHIFT (7U)
+/*! APU_HOST_WKUP - APU Wakeup triggered by CPU2 */
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_BRF_INT_WAKEUP_MASK (0x100U)
+#define WLAPU_SOCWLAPU_APU_CTRL_BRF_INT_WAKEUP_SHIFT (8U)
+/*! BRF_INT_WAKEUP - APU Wakeup */
+#define WLAPU_SOCWLAPU_APU_CTRL_BRF_INT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_BRF_INT_WAKEUP_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_BRF_INT_WAKEUP_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_MASK (0x200U)
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_SHIFT (9U)
+/*! SOC_PA_PE_EN - PA_PE control from SoC to RFU SoC_PA_PE Input */
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN(x)  (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_A_EN_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_A_EN_SHIFT (10U)
+/*! SOC_PA_PE_A_EN - PA_PE_A control from SoC to Pad */
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_A_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_A_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_A_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_G_EN_MASK (0x800U)
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_G_EN_SHIFT (11U)
+/*! SOC_PA_PE_G_EN - PA_PE_G control from SoC to Pad */
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_G_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_G_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_G_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_SHIFT (12U)
+/*! RFU_2G_SRAM_PD_METHOD_SEL - Choose apu signal to use for SRAM PD of RFU 2G memories */
+#define WLAPU_SOCWLAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_RFU_2G_SRAM_PD_METHOD_SEL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_LMU_BYPASS_MASK  (0x8000U)
+#define WLAPU_SOCWLAPU_APU_CTRL_LMU_BYPASS_SHIFT (15U)
+/*! LMU_BYPASS - LMU global bypass bit */
+#define WLAPU_SOCWLAPU_APU_CTRL_LMU_BYPASS(x)    (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_LMU_BYPASS_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_LMU_BYPASS_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_MASK (0x10000U)
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_SHIFT (16U)
+/*! SOC_PA_PE_EN_MAC2 - PA_PE control from MAC2 to RFU SoC_PA_PE Input */
+#define WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_MAC2(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_SOC_PA_PE_EN_MAC2_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU1_MASK (0x40000U)
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU1_SHIFT (18U)
+/*! APU_HOST_WKUP_CPU1 - APU Wakeup triggered by CPU1 */
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU1(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU1_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU1_MASK)
+
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU3_MASK (0x80000U)
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU3_SHIFT (19U)
+/*! APU_HOST_WKUP_CPU3 - APU Wakeup triggered by CPU3 */
+#define WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU3(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU3_SHIFT)) & WLAPU_SOCWLAPU_APU_CTRL_APU_HOST_WKUP_CPU3_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_STATUS - APU Status Register */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_STATUS_BRF_CLK_TBG_SEL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_APU_STATUS_BRF_CLK_TBG_SEL_SHIFT (0U)
+/*! BRF_CLK_TBG_SEL - Monitor BRF_Clk_TBG_Sel */
+#define WLAPU_SOCWLAPU_APU_STATUS_BRF_CLK_TBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_STATUS_BRF_CLK_TBG_SEL_SHIFT)) & WLAPU_SOCWLAPU_APU_STATUS_BRF_CLK_TBG_SEL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_STATUS_BTU_CLK_TBG_SEL_MASK (0x2U)
+#define WLAPU_SOCWLAPU_APU_STATUS_BTU_CLK_TBG_SEL_SHIFT (1U)
+/*! BTU_CLK_TBG_SEL - Monitor BTU_Clk_TBG_Sel */
+#define WLAPU_SOCWLAPU_APU_STATUS_BTU_CLK_TBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_STATUS_BTU_CLK_TBG_SEL_SHIFT)) & WLAPU_SOCWLAPU_APU_STATUS_BTU_CLK_TBG_SEL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_MASK (0x4U)
+#define WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_SHIFT (2U)
+/*! SOC_CLK_T3_REF_SEL - Monitor SoC_Clk_T3_Ref_Sel */
+#define WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_T3_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_SHIFT)) & WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_T3_REF_SEL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_TBG_SEL_MASK (0x8U)
+#define WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_TBG_SEL_SHIFT (3U)
+/*! SOC_CLK_TBG_SEL - Monitor SoC_Clk_TBG_Sel */
+#define WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_TBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_TBG_SEL_SHIFT)) & WLAPU_SOCWLAPU_APU_STATUS_SOC_CLK_TBG_SEL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_CPU1_LMU_STA_BYPASS0 - LMU static bank control byapss0 Register */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK (0xFFU)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_ISO_EN_BP_EN - Firmware Bypass enable for lmu static banks iso_en */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK (0xFF00U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_ISO_EN_BP_VAL - Firmware Bypass value for lmu static banks iso_en */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK (0xFF0000U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT (16U)
+/*! LMU_STA_BANKS_PSW_EN_BP_EN - Firmware Bypass enable for lmu static banks psw_en */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK (0xFF000000U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT (24U)
+/*! LMU_STA_BANKS_PSW_EN_BP_VAL - Firmware Bypass value for lmu static banks psw_en */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_CPU1_LMU_STA_BYPASS1 - LMU static bank control byapss1 Register */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK (0xFFU)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_SRAM_PD_BP_EN - Firmware Bypass enable for lmu static banks sram_pd */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK (0xFF00U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_SRAM_PD_BP_VAL - Firmware Bypass value for lmu static banks sram_pd */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK (0xFF0000U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT (16U)
+/*! LMU_STA_BANKS_FNRST_BP_EN - Firmware Bypass enable for lmu static banks fnrst */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK (0xFF000000U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT (24U)
+/*! LMU_STA_BANKS_FNRST_BP_VAL - Firmware Bypass value for lmu static banks fnrst */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_CPU1_LMU_STA_BYPASS2 - LMU static bank byapss2 Register */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0xFFU)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
+/*! LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN - Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0xFF00U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
+/*! LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL - Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl */
+#define WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_LMU_DYN_BYPASS0 - LMU dynamic bank control byapss0 Register */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0x7U)
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
+/*! LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN - Firmware Bypass enable for lmu dynamic banks vddmc_sw_pd_ctrl */
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0x700U)
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
+/*! LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL - Firmware Bypass value for lmu dynamic banks vddmc_sw_pd_ctrl */
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_MASK (0x70000U)
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_SHIFT (16U)
+/*! LMU_DYN_BANKS_FNRST_BP_EN - Firmware Bypass enable for lmu dynamic banks fnrst */
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_MASK (0x7000000U)
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_SHIFT (24U)
+/*! LMU_DYN_BANKS_FNRST_BP_VAL - Firmware Bypass value for lmu dynamic banks fnrst */
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_FNRST_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_MASK (0x80000000U)
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_SHIFT (31U)
+/*! LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST - 1: By default WLAN_SRAM_FNRST is used for SMU off domain banks */
+#define WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_SHIFT)) & WLAPU_SOCWLAPU_LMU_DYN_BYPASS0_LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_LMU_G2BIST_CTRL_BYPASS - LMU G2Bist control bypass Register */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_MASK (0x1U)
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_SHIFT (0U)
+/*! LMU_G2BIST_MODE_BYPASS_EN - Firmware Bypass enable for lmu g2bist mode */
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_MASK (0x3EU)
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_SHIFT (1U)
+/*! LMU_G2BIST_MODE_BYPASS_VAL - Firmware Bypass value for lmu g2bist mode */
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_MODE_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_MASK (0x1000000U)
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_SHIFT (24U)
+/*! LMU_G2BIST_START_BP_EN - Firmware Bypass enable for lmu g2bist start */
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_MASK (0x2000000U)
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_SHIFT (25U)
+/*! LMU_G2BIST_START_BP_VAL - Firmware Bypass value for lmu g2bist start */
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_START_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_MASK (0x4000000U)
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_SHIFT (26U)
+/*! LMU_G2BIST_CLK_EN_BP_EN - Firmware Bypass enable for lmu g2bist clock en */
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_MASK (0x8000000U)
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_SHIFT (27U)
+/*! LMU_G2BIST_CLK_EN_BP_VAL - Firmware Bypass value for lmu g2bist clock en */
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_LMU_G2BIST_CLK_EN_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_MASK (0xF0000000U)
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_SHIFT (28U)
+/*! G2BIST_STATUS - g2bist status */
+#define WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_SHIFT)) & WLAPU_SOCWLAPU_LMU_G2BIST_CTRL_BYPASS_G2BIST_STATUS_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS - LMU G2Bist control bypass Register for CPU1 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_MASK (0x1U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT (0U)
+/*! LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN - Firmware Bypass enable for CPU1 static banks lmu powerdomain repair request */
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_MASK (0xFFF0U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT (4U)
+/*! LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL - Firmware Bypass value for CPU1 static banks lmu powerdomain repair request */
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_MASK (0x100000U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_SHIFT (20U)
+/*! LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN - Firmware Bypass enable for SMU1 dynamic banks lmu powerdomain repair request */
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_MASK (0xF000000U)
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_SHIFT (24U)
+/*! LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL - Firmware Bypass value for SMU1 dynamic banks lmu powerdomain repair request */
+#define WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS_LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_PWR_CTRL_BYPASS4 - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_VAL_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_VAL_SHIFT (10U)
+/*! RFU_RTDP_WU_RSTB_BYPASS_VAL - Firmware Bypass Value for RFU /RTDP Wakeup reset (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_EN_MASK (0x800U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_EN_SHIFT (11U)
+/*! RFU_RTDP_WU_RSTB_BYPASS_EN - Firmware Bypass RFU /RTDP wakeup reset from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS4_RFU_RTDP_WU_RSTB_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_PWR_CTRL_BYPASS5 - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_SHIFT (12U)
+/*! CPU1_VINITHI_BYPASS_VAL - Firmware Bypass Value for CPU1 Vinithi (default boot from ROM) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_MASK (0x2000U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_SHIFT (13U)
+/*! CPU1_VINITHI_BYPASS_EN - Firmware Bypass enable for CPU1 Vinithi */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS5_CPU1_VINITHI_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_PWR_CTRL_BYPASS6 - APU power control Bypass Register 6 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_VAL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_VAL_SHIFT (0U)
+/*! WLAN1_PD_PSW_BYPASS_VAL - wlan1_pd Power Switch Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_EN_MASK (0x2U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_EN_SHIFT (1U)
+/*! WLAN1_PD_PSW_BYPASS_EN - wlan1_pd Power Switch Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_PSW_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_VAL_MASK (0x4U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_VAL_SHIFT (2U)
+/*! WLAN1_PD_FWBAR_BYPASS_VAL - wlan1_pd Firewallbar Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_EN_MASK (0x8U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_EN_SHIFT (3U)
+/*! WLAN1_PD_FWBAR_BYPASS_EN - wlan1_pd Firewallbar Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_FWBAR_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_VAL_MASK (0x10U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_VAL_SHIFT (4U)
+/*! WLAN1_PD_ISO_EN_BYPASS_VAL - wlan1_pd Isolation Cell Control */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_EN_MASK (0x20U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_EN_SHIFT (5U)
+/*! WLAN1_PD_ISO_EN_BYPASS_EN - wlan1_pd Isolation Cell Control Enable */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_ISO_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_VAL_MASK (0x40U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_VAL_SHIFT (6U)
+/*! WLAN1_PD_CLK_DIV_RSTB_BYPASS_VAL - Firmware Bypass Value for wlan1_pd Clk_Div_Rstb (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_EN_MASK (0x80U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_EN_SHIFT (7U)
+/*! WLAN1_PD_CLK_DIV_RSTB_BYPASS_EN - Firmware Bypass wlan1_pd Clk_Div_Rstb from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_CLK_DIV_RSTB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_VAL_MASK (0x100U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_VAL_SHIFT (8U)
+/*! WLAN1_PD_SRAM_PD_BYPASS_VAL - Firmware Bypass Value for SRAM_PD (active high signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_EN_MASK (0x200U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_EN_SHIFT (9U)
+/*! WLAN1_PD_SRAM_PD_BYPASS_EN - Firmware Bypass SRAM_PD from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS6_WLAN1_PD_SRAM_PD_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_PWR_CTRL_BYPASS7 - APU power control Bypass Register 7 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_VAL_MASK (0x400U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_VAL_SHIFT (10U)
+/*! RFU_RTDP2_WU_RSTB_BYPASS_VAL - Firmware Bypass Value for RFU /rtdp2 Wakeup reset (active low signal) */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_EN_MASK (0x800U)
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_EN_SHIFT (11U)
+/*! RFU_RTDP2_WU_RSTB_BYPASS_EN - Firmware Bypass RFU /rtdp2 wakeup reset from APU */
+#define WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_PWR_CTRL_BYPASS7_RFU_RTDP2_WU_RSTB_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0 - LMU static bank control byapss0 Register for smu1 hybrid banks mem */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_MASK (0xFFU)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_SHIFT (0U)
+/*! LMU_HYBRID_BANKS_ISO_EN_BP_EN - Firmware Bypass enable for lmu static banks iso_en */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_MASK (0xFF00U)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_SHIFT (8U)
+/*! LMU_HYBRID_BANKS_ISO_EN_BP_VAL - Firmware Bypass value for lmu static banks iso_en */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_ISO_EN_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_MASK (0xFF0000U)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_SHIFT (16U)
+/*! LMU_HYBRID_BANKS_PSW_EN_BP_EN - Firmware Bypass enable for lmu static banks psw_en */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_MASK (0xFF000000U)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_SHIFT (24U)
+/*! LMU_HYBRID_BANKS_PSW_EN_BP_VAL - Firmware Bypass value for lmu static banks psw_en */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0_LMU_HYBRID_BANKS_PSW_EN_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1 - LMU static bank control byapss1 Register for smu1 hybrid banks mem */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_MASK (0xFFU)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_SHIFT (0U)
+/*! LMU_HYBRID_BANKS_SRAM_PD_BP_EN - Firmware Bypass enable for lmu static banks sram_pd */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_MASK (0xFF00U)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_SHIFT (8U)
+/*! LMU_HYBRID_BANKS_SRAM_PD_BP_VAL - Firmware Bypass value for lmu static banks sram_pd */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_SRAM_PD_BP_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_MASK (0xFF0000U)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_SHIFT (16U)
+/*! LMU_HYBRID_BANKS_FNRST_BP_EN - Firmware Bypass enable for lmu static banks fnrst */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_MASK (0xFF000000U)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_SHIFT (24U)
+/*! LMU_HYBRID_BANKS_FNRST_BP_VAL - Firmware Bypass value for lmu static banks fnrst */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1_LMU_HYBRID_BANKS_FNRST_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2 - LMU static bank control byapss2 Register for smu1 hybrid banks mem */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0xFFU)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
+/*! LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN - Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)
+
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0xFF00U)
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
+/*! LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL - Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl */
+#define WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & WLAPU_SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2_LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_ECO_CTRL - APU ECO Control */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_ECO_CTRL_ECO_BITS_MASK (0xFFFFFFFFU)
+#define WLAPU_SOCWLAPU_APU_ECO_CTRL_ECO_BITS_SHIFT (0U)
+/*! ECO_BITS - Reserved for ECOs */
+#define WLAPU_SOCWLAPU_APU_ECO_CTRL_ECO_BITS(x)  (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_ECO_CTRL_ECO_BITS_SHIFT)) & WLAPU_SOCWLAPU_APU_ECO_CTRL_ECO_BITS_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_GPIO_WKUP_CTRL0 - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [0] */
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_SHIFT)) & WLAPU_SOCWLAPU_GPIO_WKUP_CTRL0_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_GPIO_WKUP_CTRL1 - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [4] */
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_SHIFT)) & WLAPU_SOCWLAPU_GPIO_WKUP_CTRL1_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_GPIO_WKUP_CTRL2 - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [8] */
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_SHIFT)) & WLAPU_SOCWLAPU_GPIO_WKUP_CTRL2_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_GPIO_WKUP_CTRL3 - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_MASK (0xFFFFFFFFU)
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_SHIFT (0U)
+/*! P2C_WKUP_SELECT - [07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [12] */
+#define WLAPU_SOCWLAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_SHIFT)) & WLAPU_SOCWLAPU_GPIO_WKUP_CTRL3_P2C_WKUP_SELECT_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_HOST_WKUP_MODE - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_HOST_WKUP_MODE_GPIO_SEL_MASK (0xFFFFU)
+#define WLAPU_SOCWLAPU_HOST_WKUP_MODE_GPIO_SEL_SHIFT (0U)
+/*! GPIO_SEL - gpio_sel */
+#define WLAPU_SOCWLAPU_HOST_WKUP_MODE_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_HOST_WKUP_MODE_GPIO_SEL_SHIFT)) & WLAPU_SOCWLAPU_HOST_WKUP_MODE_GPIO_SEL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_T3_CLK_DIV_EN_BYPASS - " */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_MASK (0x1U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_SHIFT (0U)
+/*! T3_SOC_256_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_MASK (0x2U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_SHIFT (1U)
+/*! T3_SOC_256_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_256_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_MASK (0x4U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_SHIFT (2U)
+/*! T3_SOC_320_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_MASK (0x8U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_SHIFT (3U)
+/*! T3_SOC_320_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_320_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_MASK (0x10U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_SHIFT (4U)
+/*! T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_MASK (0x20U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_SHIFT (5U)
+/*! T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_MASK (0x40U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_SHIFT (6U)
+/*! T3_SOC_426_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_MASK (0x80U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_SHIFT (7U)
+/*! T3_SOC_426_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_426_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_MASK (0x100U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_SHIFT (8U)
+/*! T3_SOC_512_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_MASK (0x200U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_SHIFT (9U)
+/*! T3_SOC_512_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_SOC_512_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_MASK (0x400U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_SHIFT (10U)
+/*! T3_213P3_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_MASK (0x800U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_SHIFT (11U)
+/*! T3_213P3_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_213P3_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_SHIFT (12U)
+/*! T3_MAC1_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_MASK (0x2000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_SHIFT (13U)
+/*! T3_MAC1_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC1_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_MASK (0x4000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_SHIFT (14U)
+/*! T3_MAC2_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_MASK (0x8000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_SHIFT (15U)
+/*! T3_MAC2_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_MAC2_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_MASK (0x10000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_SHIFT (16U)
+/*! T3_BBUD_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_MASK (0x20000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_SHIFT (17U)
+/*! T3_BBUD_CLK_DIV_EN_BYPASS_VAL - bypass value */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_T3_BBUD_CLK_DIV_EN_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_MASK (0x40000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_SHIFT (18U)
+/*! TCPU_CPU_CLK_DIV_EN_BYPASS_EN - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_MASK (0x80000U)
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_SHIFT (19U)
+/*! TCPU_CPU_CLK_DIV_EN_BYPASS_VAL - bypass value for tcpu cpu_clk_en */
+#define WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_T3_CLK_DIV_EN_BYPASS_TCPU_CPU_CLK_DIV_EN_BYPASS_VAL_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_LDO_LV_CTRL2 - LV LDO Control 2 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_MASK (0x10U)
+#define WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_SHIFT (4U)
+/*! LDO_GLU_XOSC_VAL - XOSC_EN value for ldo control logic set by FW */
+#define WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_SHIFT)) & WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_MASK (0x20U)
+#define WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_SHIFT (5U)
+/*! LDO_GLU_XOSC_BYPASS_EN - XOSC_EN control bypass for ldo control logic */
+#define WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_LDO_LV_CTRL2_LDO_GLU_XOSC_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_CAU_BYPASS - CAU Bypass */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_SHIFT (0U)
+/*! PHY_REF_CLK_BYPASS_VAL - bypass value for phy ref clk enable */
+#define WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_MASK (0x2U)
+#define WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_SHIFT (1U)
+/*! PHY_REF_CLK_BYPASS_EN - bypass enable for phy ref clk enable */
+#define WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_CAU_BYPASS_PHY_REF_CLK_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_VAL_MASK (0x10U)
+#define WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_VAL_SHIFT (4U)
+/*! WL_CLK_BYPASS_VAL - bypass value for wl clk enable */
+#define WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_EN_MASK (0x20U)
+#define WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_EN_SHIFT (5U)
+/*! WL_CLK_BYPASS_EN - bypass enable for wl clk enable */
+#define WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_CAU_BYPASS_WL_CLK_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_MEM_PWDN1 - Memory Powerdown Control */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_VAL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_VAL_SHIFT (0U)
+/*! CPU1_DTCM_BYPASS_VAL - Firmware Bypass value for cpu1 DTCM Memories Power Down. Not used for KF2 */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_VAL_MASK (0x2U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_VAL_SHIFT (1U)
+/*! CPU1_TCM_BYPASS_VAL - Firmware Bypass value for cpu1 ATCM/BTCM0/BTCM1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_VAL_MASK (0x80U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_VAL_SHIFT (7U)
+/*! CPU1_BPM_BYPASS_VAL - Firmware Bypass value for cpu1 bpm Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_VAL_MASK (0x200U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_VAL_SHIFT (9U)
+/*! SMU1_BYPASS_VAL - Firmware Bypass value for amu1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_VAL_MASK (0x400U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_VAL_SHIFT (10U)
+/*! BCM_BYPASS_VAL - Firmware Bypass value for BCM Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_VAL_MASK (0x800U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_VAL_SHIFT (11U)
+/*! WEU_BYPASS_VAL - Firmware Bypass value for WEU Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_VAL_MASK (0x1000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_VAL_SHIFT (12U)
+/*! SDU_BYPASS_VAL - Firmware Bypass value for cisRAM (SDU) Memory Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_VAL_MASK (0x2000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_VAL_SHIFT (13U)
+/*! MCU1_BYPASS_VAL - Firmware Bypass value for MCU1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_VAL_MASK (0x4000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_VAL_SHIFT (14U)
+/*! SIU_DBG_BYPASS_VAL - Firmware Bypass value for WLAN DBG UART Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_VAL_MASK (0x8000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_VAL_SHIFT (15U)
+/*! ADMA1_BYPASS_VAL - Firmware Bypass value for ADMA1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_EN_MASK (0x10000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_EN_SHIFT (16U)
+/*! CPU1_DTCM_BYPASS_EN - Firmware Bypass Enable for cpu1 DTCM Memories Power Down. */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_DTCM_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_EN_MASK (0x20000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_EN_SHIFT (17U)
+/*! CPU1_TCM_BYPASS_EN - Firmware Bypass Enable for cpu1 ATCM/BTCM0/BTCM1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_TCM_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_EN_MASK (0x800000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_EN_SHIFT (23U)
+/*! CPU1_BPM_BYPASS_EN - Firmware Bypass Enable for cpu1 bpm Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_CPU1_BPM_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_EN_MASK (0x2000000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_EN_SHIFT (25U)
+/*! SMU1_BYPASS_EN - Firmware Bypass Enable for amu1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_SMU1_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_EN_MASK (0x4000000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_EN_SHIFT (26U)
+/*! BCM_BYPASS_EN - Firmware Bypass Enable for BCM Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_BCM_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_EN_MASK (0x8000000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_EN_SHIFT (27U)
+/*! WEU_BYPASS_EN - Firmware Bypass Enable for WEU Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_WEU_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_EN_MASK (0x10000000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_EN_SHIFT (28U)
+/*! SDU_BYPASS_EN - Firmware Bypass Enable for cisRAM (SDU) Memory Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_SDU_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_EN_MASK (0x20000000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_EN_SHIFT (29U)
+/*! MCU1_BYPASS_EN - Firmware Bypass Enable for MCU1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_MCU1_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_EN_MASK (0x40000000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_EN_SHIFT (30U)
+/*! SIU_DBG_BYPASS_EN - Firmware Bypass Enable for WLAN DBG UART Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_SIU_DBG_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_EN_MASK (0x80000000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_EN_SHIFT (31U)
+/*! ADMA1_BYPASS_EN - Firmware Bypass Enable for ADMA1 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN1_ADMA1_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_MEM_PWDN2 - Memory Powerdown Control */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_VAL_MASK (0x2U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_VAL_SHIFT (1U)
+/*! OTP_BYPASS_VAL - Firmware Bypass Value for OTP Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_VAL_MASK (0x8U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_VAL_SHIFT (3U)
+/*! SMU0_BYPASS_VAL - Firmware Bypass value for SMU0 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_VAL_MASK (0x10U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_VAL_SHIFT (4U)
+/*! CPU1_CACHE_BYPASS_VAL - Firmware Bypass value for cpu1 cache Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_VAL_MASK (0x20U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_VAL_SHIFT (5U)
+/*! CPU1_ETB_BYPASS_VAL - Firmware Bypass value for cpu1 ETB Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_VAL_MASK (0x40U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_VAL_SHIFT (6U)
+/*! CPU1_ROM_BYPASS_VAL - Firmware Bypass value for cpu1 ROM Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_VAL_MASK (0x80U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_VAL_SHIFT (7U)
+/*! SSU_BYPASS_VAL - Firmware Bypass Value for SSU Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_EN_MASK (0x20000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_EN_SHIFT (17U)
+/*! OTP_BYPASS_EN - Firmware Bypass Enable for OTP Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_OTP_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_EN_MASK (0x80000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_EN_SHIFT (19U)
+/*! SMU0_BYPASS_EN - Firmware Bypass Enable for SMU0 Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_SMU0_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_EN_MASK (0x100000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_EN_SHIFT (20U)
+/*! CPU1_CACHE_BYPASS_EN - Firmware Bypass Enable for cpu1 cache Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_CACHE_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_EN_MASK (0x200000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_EN_SHIFT (21U)
+/*! CPU1_ETB_BYPASS_EN - Firmware Bypass Enable for cpu1 ETB Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ETB_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_EN_MASK (0x400000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_EN_SHIFT (22U)
+/*! CPU1_ROM_BYPASS_EN - Firmware Bypass Enable for cpu1 ROM Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_CPU1_ROM_BYPASS_EN_MASK)
+
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_EN_MASK (0x800000U)
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_EN_SHIFT (23U)
+/*! SSU_BYPASS_EN - Firmware Bypass Enable for SSU Memories Power Down */
+#define WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_MEM_PWDN2_SSU_BYPASS_EN_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_HOST_WKUP_SOURCE - Host Wakeup Source Control */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_HOST_WKUP_SOURCE_ENABLE_MASK (0xFFFFU)
+#define WLAPU_SOCWLAPU_HOST_WKUP_SOURCE_ENABLE_SHIFT (0U)
+/*! ENABLE - Enable/ disable value: */
+#define WLAPU_SOCWLAPU_HOST_WKUP_SOURCE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_HOST_WKUP_SOURCE_ENABLE_SHIFT)) & WLAPU_SOCWLAPU_HOST_WKUP_SOURCE_ENABLE_MASK)
+/*! @} */
+
+/*! @name SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0 - APU IPS power control Bypass Register 0 */
+/*! @{ */
+
+#define WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_VAL_MASK (0x1U)
+#define WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_VAL_SHIFT (0U)
+/*! IPS_RAM_ROM_PD_BYPASS_VAL - Firmware Bypass value for IPS RAM/ROM PD from APU */
+#define WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_VAL_SHIFT)) & WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_VAL_MASK)
+
+#define WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_EN_MASK (0x2U)
+#define WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_EN_SHIFT (1U)
+/*! IPS_RAM_ROM_PD_BYPASS_EN - Firmware Bypass enable for IPS RAM/ROM PD from APU */
+#define WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_EN_SHIFT)) & WLAPU_SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0_IPS_RAM_ROM_PD_BYPASS_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WLAPU_Register_Masks */
+
+
+/* WLAPU - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral WLAPU base address */
+  #define WLAPU_BASE                               (0x51258000u)
+  /** Peripheral WLAPU base address */
+  #define WLAPU_BASE_NS                            (0x41258000u)
+  /** Peripheral WLAPU base pointer */
+  #define WLAPU                                    ((WLAPU_Type *)WLAPU_BASE)
+  /** Peripheral WLAPU base pointer */
+  #define WLAPU_NS                                 ((WLAPU_Type *)WLAPU_BASE_NS)
+  /** Array initializer of WLAPU peripheral base addresses */
+  #define WLAPU_BASE_ADDRS                         { WLAPU_BASE }
+  /** Array initializer of WLAPU peripheral base pointers */
+  #define WLAPU_BASE_PTRS                          { WLAPU }
+  /** Array initializer of WLAPU peripheral base addresses */
+  #define WLAPU_BASE_ADDRS_NS                      { WLAPU_BASE_NS }
+  /** Array initializer of WLAPU peripheral base pointers */
+  #define WLAPU_BASE_PTRS_NS                       { WLAPU_NS }
+#else
+  /** Peripheral WLAPU base address */
+  #define WLAPU_BASE                               (0x41258000u)
+  /** Peripheral WLAPU base pointer */
+  #define WLAPU                                    ((WLAPU_Type *)WLAPU_BASE)
+  /** Array initializer of WLAPU peripheral base addresses */
+  #define WLAPU_BASE_ADDRS                         { WLAPU_BASE }
+  /** Array initializer of WLAPU peripheral base pointers */
+  #define WLAPU_BASE_PTRS                          { WLAPU }
+#endif
+
+/*!
+ * @}
+ */ /* end of group WLAPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MOD;                               /**< Mode, offset: 0x0 */
+  __IO uint32_t TC;                                /**< Timer Constant, offset: 0x4 */
+  __O  uint32_t FEED;                              /**< Feed Sequence, offset: 0x8 */
+  __I  uint32_t TV;                                /**< Timer Value, offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t WARNINT;                           /**< Warning Interrupt Compare Value, offset: 0x14 */
+  __IO uint32_t WINDOW;                            /**< Window Compare Value, offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Mode */
+/*! @{ */
+
+#define WWDT_MOD_WDEN_MASK                       (0x1U)
+#define WWDT_MOD_WDEN_SHIFT                      (0U)
+/*! WDEN - Watchdog Enable
+ *  0b0..Stop. The Watchdog timer is stopped.
+ *  0b1..Run. The Watchdog timer is running.
+ */
+#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+
+#define WWDT_MOD_WDRESET_MASK                    (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT                   (1U)
+/*! WDRESET - Watchdog Reset Enable
+ *  0b0..Interrupt. A Watchdog timeout will not cause a chip reset.
+ *  0b1..Reset. A Watchdog timeout will cause a chip reset.
+ */
+#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+
+#define WWDT_MOD_WDTOF_MASK                      (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT                     (2U)
+/*! WDTOF - Watchdog Timeout Flag
+ *  0b0..Clear.
+ *  0b1..Reset. Causes a chip reset if WDRESET = 1.
+ */
+#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+
+#define WWDT_MOD_WDINT_MASK                      (0x8U)
+#define WWDT_MOD_WDINT_SHIFT                     (3U)
+/*! WDINT - Warning Interrupt Flag
+ *  0b0..No flag.
+ *  0b1..Flag. The Watchdog interrupt flag is set when the Watchdog counter is no longer greater than the value specified by WARNINT.
+ */
+#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+
+#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
+/*! WDPROTECT - Watchdog Update Mode
+ *  0b0..Flexible
+ *  0b1..Threshold
+ */
+#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+
+#define WWDT_MOD_LOCK_MASK                       (0x20U)
+#define WWDT_MOD_LOCK_SHIFT                      (5U)
+/*! LOCK - Lock
+ *  0b0..No Lock
+ *  0b1..Lock
+ */
+#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+/*! @} */
+
+/*! @name TC - Timer Constant */
+/*! @{ */
+
+#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT                      (0U)
+/*! COUNT - Watchdog Timeout Value */
+#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+/*! @} */
+
+/*! @name FEED - Feed Sequence */
+/*! @{ */
+
+#define WWDT_FEED_FEED_MASK                      (0xFFU)
+#define WWDT_FEED_FEED_SHIFT                     (0U)
+/*! FEED - Feed Value */
+#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+/*! @} */
+
+/*! @name TV - Timer Value */
+/*! @{ */
+
+#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT                      (0U)
+/*! COUNT - Counter Timer Value */
+#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+/*! @} */
+
+/*! @name WARNINT - Warning Interrupt Compare Value */
+/*! @{ */
+
+#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
+/*! WARNINT - Watchdog Warning Interrupt Compare Value */
+#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+/*! @} */
+
+/*! @name WINDOW - Window Compare Value */
+/*! @{ */
+
+#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
+/*! WINDOW - Watchdog Window Value. */
+#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+  /** Peripheral WWDT0 base address */
+  #define WWDT0_BASE                               (0x5000E000u)
+  /** Peripheral WWDT0 base address */
+  #define WWDT0_BASE_NS                            (0x4000E000u)
+  /** Peripheral WWDT0 base pointer */
+  #define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
+  /** Peripheral WWDT0 base pointer */
+  #define WWDT0_NS                                 ((WWDT_Type *)WWDT0_BASE_NS)
+  /** Array initializer of WWDT peripheral base addresses */
+  #define WWDT_BASE_ADDRS                          { WWDT0_BASE }
+  /** Array initializer of WWDT peripheral base pointers */
+  #define WWDT_BASE_PTRS                           { WWDT0 }
+  /** Array initializer of WWDT peripheral base addresses */
+  #define WWDT_BASE_ADDRS_NS                       { WWDT0_BASE_NS }
+  /** Array initializer of WWDT peripheral base pointers */
+  #define WWDT_BASE_PTRS_NS                        { WWDT0_NS }
+#else
+  /** Peripheral WWDT0 base address */
+  #define WWDT0_BASE                               (0x4000E000u)
+  /** Peripheral WWDT0 base pointer */
+  #define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
+  /** Array initializer of WWDT peripheral base addresses */
+  #define WWDT_BASE_ADDRS                          { WWDT0_BASE }
+  /** Array initializer of WWDT peripheral base pointers */
+  #define WWDT_BASE_PTRS                           { WWDT0 }
+#endif
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS                                { WDT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/** Used for get the base address of ROM API */
+#define FSL_ROM_API_BASE_ADDR 0x1303f000U
+/** Used for get the address of OTP INIT API in ROM */
+#define FSL_ROM_OTP_INIT_ADDR 0x13009FF9U
+/** Used for get the address of OTP DEINIT API in ROM */
+#define FSL_ROM_OTP_DEINIT_ADDR 0x1300a047U
+/** Used for get the address of OTP FUSE READ API in ROM */
+#define FSL_ROM_OTP_FUSE_READ_ADDR 0x1300a057U
+
+/*! @brief IMU message link between current CPU and remote peer CPU. */
+typedef enum
+{
+    kIMU_LinkCpu1Cpu3 = 0, /*! Message link between CPU1 and CPU3. */
+    kIMU_LinkCpu2Cpu3,     /*! Message link between CPU2 and CPU3. */
+    kIMU_LinkMax           /*! Message link count used for boundary check. */
+} imu_link_t;
+
+/*! @brief IMU base register for current CPU. */
+#define IMU_CUR_CPU_BASE(link) (((link) == kIMU_LinkCpu1Cpu3) ? (&(WLCTRL->CIU1_IMU_CPU3_WR_MSG_TO_CPU1)) : (&(BLECTRL->CIU2_IMU_CPU3_WR_MSG_TO_CPU2)))
+/*! @brief IMU base register for peer CPU. */
+#define IMU_PEER_CPU_BASE(link) (((link) == kIMU_LinkCpu1Cpu3) ? (&(WLCTRL->CIU1_IMU_CPU1_WR_MSG_TO_CPU3)) : (&(BLECTRL->CIU2_IMU_CPU2_WR_MSG_TO_CPU3)))
+
+/*! @brief IMU CPU index for current CPU. */
+#define IMU_CPU_INDEX (3U)
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* RW612_H_ */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/RW612_features.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/RW612_features.h
new file mode 100644
index 0000000000..e097813354
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/RW612_features.h
@@ -0,0 +1,462 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2021-03-16
+**     Build:               b240723
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2021-03-16)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _RW612_FEATURES_H_
+#define _RW612_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ACOMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACOMP_COUNT (1)
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (2)
+/* @brief AON_SOC_CIU availability on the SoC. */
+#define FSL_FEATURE_SOC_AON_SOC_CIU_COUNT (1)
+/* @brief APU availability on the SoC. */
+#define FSL_FEATURE_SOC_APU_COUNT (2)
+/* @brief BG availability on the SoC. */
+#define FSL_FEATURE_SOC_BG_COUNT (1)
+/* @brief BLEAPU availability on the SoC. */
+#define FSL_FEATURE_SOC_BLEAPU_COUNT (1)
+/* @brief BUCK11 availability on the SoC. */
+#define FSL_FEATURE_SOC_BUCK11_COUNT (1)
+/* @brief BUCK18 availability on the SoC. */
+#define FSL_FEATURE_SOC_BUCK18_COUNT (1)
+/* @brief CACHE64_CTRL availability on the SoC. */
+#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (2)
+/* @brief CACHE64_POLSEL availability on the SoC. */
+#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (2)
+/* @brief CAU availability on the SoC. */
+#define FSL_FEATURE_SOC_CAU_COUNT (1)
+/* @brief CDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_CDOG_COUNT (1)
+/* @brief CIU1 availability on the SoC. */
+#define FSL_FEATURE_SOC_CIU1_COUNT (1)
+/* @brief CIU2 availability on the SoC. */
+#define FSL_FEATURE_SOC_CIU2_COUNT (1)
+/* @brief CLKCTL0 availability on the SoC. */
+#define FSL_FEATURE_SOC_CLKCTL0_COUNT (1)
+/* @brief CLKCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_CLKCTL1_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (4)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (2)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief ELS availability on the SoC. */
+#define FSL_FEATURE_SOC_ELS_COUNT (1)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_ENET_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (5)
+/* @brief FLEXSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
+/* @brief FREQME availability on the SoC. */
+#define FSL_FEATURE_SOC_FREQME_COUNT (1)
+/* @brief GDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_GDMA_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (2)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (5)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (5)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief ITRC availability on the SoC. */
+#define FSL_FEATURE_SOC_ITRC_COUNT (1)
+/* @brief LCDIC availability on the SoC. */
+#define FSL_FEATURE_SOC_LCDIC_COUNT (1)
+/* @brief MCI_IO_MUX availability on the SoC. */
+#define FSL_FEATURE_SOC_MCI_IO_MUX_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (2)
+/* @brief OCOTP availability on the SoC. */
+#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
+/* @brief OSTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PKC availability on the SoC. */
+#define FSL_FEATURE_SOC_PKC_COUNT (1)
+/* @brief POWERQUAD availability on the SoC. */
+#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
+/* @brief PUF availability on the SoC. */
+#define FSL_FEATURE_SOC_PUF_COUNT (1)
+/* @brief RF_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_RF_SYSCON_COUNT (1)
+/* @brief ROMC availability on the SoC. */
+#define FSL_FEATURE_SOC_ROMC_COUNT (1)
+/* @brief RSTCTL0 availability on the SoC. */
+#define FSL_FEATURE_SOC_RSTCTL0_COUNT (1)
+/* @brief RSTCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_RSTCTL1_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (5)
+/* @brief SYSCTL0 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL0_COUNT (1)
+/* @brief SYSCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
+/* @brief SYSCTL2 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL2_COUNT (1)
+/* @brief SYSPLL_T3 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSPLL_T3_COUNT (1)
+/* @brief SYSPLL_TCPU availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSPLL_TCPU_COUNT (1)
+/* @brief SOC_OTP_CTRL availability on the SoC. */
+#define FSL_FEATURE_SOC_SOC_OTP_CTRL_COUNT (1)
+/* @brief SENSOR_CTRL availability on the SoC. */
+#define FSL_FEATURE_SOC_SENSOR_CTRL_COUNT (1)
+/* @brief SDU_FN0_CARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SDU_FN0_CARD_COUNT (1)
+/* @brief SDU_FBR_CARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SDU_FBR_CARD_COUNT (1)
+/* @brief SDU_FN_CARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SDU_FN_CARD_COUNT (1)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (5)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USIM availability on the SoC. */
+#define FSL_FEATURE_SOC_USIM_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WLAPU availability on the SoC. */
+#define FSL_FEATURE_SOC_WLAPU_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* CACHE64_CTRL module features */
+
+/* @brief Cache Line size in byte. */
+#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32)
+
+/* CACHE64_POLSEL module features */
+
+/* No feature definitions */
+
+/* CDOG module features */
+
+/* @brief CDOG Has No Reset */
+#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
+/* @brief CDOG Load default configurations during init function */
+#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (1)
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* CTIMER module features */
+
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
+/* @brief CTIMER has no capture 2 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
+#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
+/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
+/* @brief CTIMER Has register MSR */
+#define FSL_FEATURE_CTIMER_HAS_MSR (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) (33)
+/* @brief Number of all DMA channels */
+#define FSL_FEATURE_DMA_ALL_CHANNELS (66)
+/* @brief Max Number of DMA channels */
+#define FSL_FEATURE_DMA_MAX_CHANNELS (33)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (1024)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+
+/* DMIC module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMIC_CHANNEL_NUM (4)
+/* @brief DMIC channel support stereo data */
+#define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (1)
+/* @brief DMIC does not support bypass channel clock */
+#define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1)
+/* @brief DMIC channel FIFO register support sign extended */
+#define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1)
+/* @brief DMIC has no IOCFG register */
+#define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1)
+/* @brief DMIC has decimator reset function */
+#define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1)
+/* @brief DMIC has global channel synchronization function */
+#define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (0)
+
+/* ENET module features */
+
+/* @brief Support Interrupt Coalesce */
+#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
+/* @brief Queue Size. */
+#define FSL_FEATURE_ENET_QUEUE (1)
+/* @brief Has AVB Support. */
+#define FSL_FEATURE_ENET_HAS_AVB (0)
+/* @brief Has Timer Pulse Width control. */
+#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
+/* @brief Has Extend MDIO Support. */
+#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
+/* @brief Has Additional 1588 Timer Channel Interrupt. */
+#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
+/* @brief Support Interrupt Coalesce for each instance */
+#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0)
+/* @brief Queue Size for each instance. */
+#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1)
+/* @brief Has AVB Support for each instance. */
+#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0)
+/* @brief Has Timer Pulse Width control for each instance. */
+#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (1)
+/* @brief Has Extend MDIO Support for each instance. */
+#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1)
+/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */
+#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0)
+/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
+#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */
+#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0)
+/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */
+#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
+/* @brief ENET Has Extra Clock Gate.(RW610). */
+#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (1)
+/* @brief ENET support reset. */
+#define FSL_FEATURE_ENET_HAS_RSTCTL (1)
+
+/* FLEXCOMM module features */
+
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
+/* @brief FLEXCOMM0 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
+/* @brief FLEXCOMM1 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
+/* @brief FLEXCOMM2 I2S INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
+/* @brief FLEXCOMM3 I2S INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
+/* @brief FLEXCOMM14 USART INDEX 14 */
+#define FSL_FEATURE_FLEXCOMM14_USART_INDEX (14)
+/* @brief FLEXCOMM14 SPI(HS_SPI) INDEX 14 */
+#define FSL_FEATURE_FLEXCOMM14_SPI_INDEX (14)
+/* @brief FLEXCOMM14 I2C INDEX 14 */
+#define FSL_FEATURE_FLEXCOMM14_I2C_INDEX (14)
+/* @brief FLEXCOMM14 I2S INDEX 14 */
+#define FSL_FEATURE_FLEXCOMM14_I2S_INDEX (14)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
+    (((x) == FLEXCOMM0) ? (1) : \
+    (((x) == FLEXCOMM1) ? (0) : \
+    (((x) == FLEXCOMM2) ? (0) : \
+    (((x) == FLEXCOMM3) ? (0) : \
+    (((x) == FLEXCOMM14) ? (0) : (-1))))))
+
+/* FLEXSPI module features */
+
+/* @brief FlexSPI AHB buffer count */
+#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8)
+/* @brief FlexSPI has no MCR0 ARDFEN bit */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0)
+/* @brief FlexSPI has no MCR0 ATDFEN bit */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0)
+/* @brief FlexSPI has no IP parallel mode */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1)
+/* @brief FlexSPI has no AHB parallel mode */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1)
+/* @brief FlexSPI support address shift */
+#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1)
+/* @brief FlexSPI support sample clock source selection */
+#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1)
+/* @brief FlexSPI support sample clock source or source_b selection */
+#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1)
+/* @brief FlexSPI AHB RX buffer size (byte) */
+#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048)
+/* @brief FlexSPI IPED REGION COUNT */
+#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (15)
+
+/* ADC module features */
+
+/* @brief Whether ADC has the single-end mode temp channel */
+#define FSL_FEATURE_ADC_HAS_NO_SINGLEEND_TEMP_CHANNEL (1)
+/* @brief Whether ADC has the differential mode voice channel */
+#define FSL_FEATURE_ADC_HAS_NO_DIFFERENTIAL_VOICE_CHANNEL (1)
+/* @brief Whether ADC has the differential mode temp channel */
+#define FSL_FEATURE_ADC_HAS_NO_DIFFERENTIAL_TEMP_CHANNEL (1)
+
+/* GDMA module features */
+
+/* @brief GDMA Channel Number */
+#define FSL_FEATURE_GDMA_CHANNEL_NUM (4)
+
+/* GPIO module features */
+
+/* @brief GPIO has interrupts */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT (1)
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer. */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+/* @brief I2S has DMIC interconnection. */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1)
+
+/* INPUTMUX module features */
+
+/* @brief Inputmux has DMA Request Enable */
+#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1)
+/* @brief Inputmux has channel mux control */
+#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0)
+
+/* MEMORY module features */
+
+/* @brief Memory map has offset between subsystems. */
+#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+
+/* OSTIMER module features */
+
+/* @brief Has no OS Timer control register in PMC */
+#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* POWERLIB module features */
+
+/* @brief Powerlib API is different with other LPC series devices. */
+#define FSL_FEATURE_POWERLIB_EXTEND (1)
+
+/* RTC module features */
+
+/* @brief RTC has no reset control */
+#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
+/* @brief Has SUBSEC Register (register SUBSEC) */
+#define FSL_FEATURE_RTC_HAS_SUBSEC (1)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SPI module features */
+
+/* @brief SSEL pin count. */
+#define FSL_FEATURE_SPI_SSEL_COUNT (4)
+
+/* TRNG module features */
+
+/* @brief TRNG does not support SCR4L. */
+#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1)
+/* @brief TRNG does not support SCR5L. */
+#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1)
+/* @brief TRNG does not support SCR6L. */
+#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1)
+/* @brief TRNG does not support PKRMAX. */
+#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1)
+/* @brief TRNG does not support SAMP mode. */
+#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1)
+/* @brief TRNG does not support ACC. */
+#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
+/* @brief TRNG does not support SBLIM. */
+#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1)
+/* @brief TRNG supports reset control. */
+#define FSL_FEATURE_TRNG_HAS_RSTCTL (1)
+/* @brief TRNG supports dual oscillator mode. */
+#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1)
+/* @brief TRNG supports control pin. */
+#define FSL_FEATURE_TRNG_HAS_CTRL_PIN (1)
+
+/* USB module features */
+
+/* @brief USBC Atlantic Controller support on the SoC. */
+#define FSL_FEATURE_USB_ATLANTIC_EHCI_SUPPORT (1)
+
+/* USIM module features */
+
+/* @brief USIM Tx/Rx FIFO size in byte. */
+#define FSL_FEATURE_USIM_FIFO_DEPTH (16)
+
+/* UTICK module features */
+
+/* @brief UTICK does not support power down configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+
+/* WWDT module features */
+
+/* @brief WWDT does not support oscillator lock. */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0)
+/* @brief WWDT does not support power down configure. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
+#endif /* _RW612_FEATURES_H_ */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/fsl_device_registers.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/fsl_device_registers.h
new file mode 100644
index 0000000000..ef4ed1aacd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/fsl_device_registers.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2023 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
+
+#define RW612_SERIES
+
+/* CMSIS-style register definitions */
+#include "RW612.h"
+/* CPU specific feature definitions */
+#include "RW612_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/system_RW612.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/system_RW612.c
new file mode 100644
index 0000000000..516c05faaf
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/system_RW612.c
@@ -0,0 +1,250 @@
+/*
+** ###################################################################
+**     Processors:          RW612ETA2I
+**                          RW612HNA2I
+**                          RW612UKA2I
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RW61X User manual Rev. 0.95, June 2022
+**     Version:             rev. 1.0, 2021-03-16
+**     Build:               b231201
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2023 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2021-03-16)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RW612
+ * @version 1.0
+ * @date 2023-12-01
+ * @brief Device specific configuration file for RW612 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define SYSTEM_IS_XIP_FLEXSPI()                                                                               \
+    ((((uint32_t)SystemCoreClockUpdate >= 0x08000000U) && ((uint32_t)SystemCoreClockUpdate < 0x10000000U)) || \
+     (((uint32_t)SystemCoreClockUpdate >= 0x18000000U) && ((uint32_t)SystemCoreClockUpdate < 0x20000000U)))
+
+#define CLOCK_KHZ(freq) ((freq)*1000UL)
+#define CLOCK_MHZ(freq) (CLOCK_KHZ(freq) * 1000UL)
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+__attribute__((weak)) void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */
+#endif                                                    /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif                                                    /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+    SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    SCB_NS->CPACR |=
+        ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
+#endif                                     /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+    SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
+
+    if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* Enable cache to accelerate boot. */
+    {
+        /* set command to invalidate all ways and write GO bit to initiate command */
+        CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
+        CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
+        /* Wait until the command completes */
+        while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
+        {
+        }
+        /* Enable cache, enable write buffer */
+        CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
+
+        /* Set whole FlexSPI0 space to write through. */
+        CACHE64_POLSEL0->REG0_TOP = 0x07FFFC00U;
+        CACHE64_POLSEL0->REG1_TOP = 0x0U;
+        CACHE64_POLSEL0->POLSEL   = 0x1U;
+
+        __ISB();
+        __DSB();
+    }
+
+    SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+static uint32_t getT3PllMciIrcClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    if ((SYSPLL_T3->CLKTREE_CTRL_SIX_REG & 0xFU) == 0x5U)
+    {
+        freq = CLOCK_MHZ(2560UL) / 43UL;
+    }
+    else if ((SYSPLL_T3->CLKTREE_CTRL_SIX_REG & 0xFU) == 0xAU)
+    {
+        freq = CLOCK_MHZ(2560UL) / 53UL;
+    }
+    else
+    {
+        /* Only 48MHz and 60MHz is allowed */
+    }
+
+    return freq;
+}
+
+static uint32_t getTcpuFvcoFreq(void)
+{
+    uint32_t freq = 0UL;
+    uint32_t steps;
+
+    steps = (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIFT;
+
+    if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_40000KHZ) && (steps >= 75UL) && (steps <= 96UL))
+    {
+        /* Fbdiv from 75 to 96, step 40MHz */
+        steps -= 75UL;
+        freq = CLOCK_MHZ(3000UL) + steps * CLOCK_MHZ(40UL);
+    }
+    else if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_38400KHZ) && (steps >= 78UL) && (steps <= 100UL))
+    {
+        /* Fbdiv from 78 to 100, step 38.4MHz */
+        steps -= 78UL;
+        freq = CLOCK_KHZ(2995200UL) + steps * CLOCK_KHZ(38400UL);
+    }
+    else
+    {
+        /* Not valid path */
+    }
+
+    return freq;
+}
+
+static uint32_t getT3PllMci256mClkFreq(void)
+{
+    uint32_t freq = CLOCK_MHZ(256UL);
+    return freq;
+}
+
+static uint32_t getTcpuMciClkFreq(void)
+{
+    uint32_t freq = getTcpuFvcoFreq() / 12UL;
+    return freq;
+}
+
+static uint32_t getSysOscFreq(void)
+{
+    return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT_CLKIN : 0U);
+}
+
+static uint32_t getFFroFreq(void)
+{
+    return getT3PllMciIrcClkFreq();
+}
+
+static uint32_t getLpOscFreq(void)
+{
+    return CLK_XTAL_OSC_CLK / 40U;
+}
+
+static uint32_t getSFroFreq(void)
+{
+    return getT3PllMci256mClkFreq() / 16U;
+}
+
+static uint32_t getMainPllClkFreq(void)
+{
+    return getTcpuMciClkFreq() / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
+}
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
+    {
+        case CLKCTL0_MAINCLKSELB_SEL(0):
+            switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
+            {
+                case CLKCTL0_MAINCLKSELA_SEL(0):
+                    freq = getSysOscFreq();
+                    break;
+                case CLKCTL0_MAINCLKSELA_SEL(1):
+                    freq = getFFroFreq() / 4U;
+                    break;
+                case CLKCTL0_MAINCLKSELA_SEL(2):
+                    freq = getLpOscFreq();
+                    break;
+                case CLKCTL0_MAINCLKSELA_SEL(3):
+                    freq = getFFroFreq();
+                    break;
+                default:
+                    freq = 0U;
+                    break;
+            }
+            break;
+
+        case CLKCTL0_MAINCLKSELB_SEL(1):
+            freq = getSFroFreq();
+            break;
+
+        case CLKCTL0_MAINCLKSELB_SEL(2):
+            freq = getMainPllClkFreq();
+            break;
+
+        case CLKCTL0_MAINCLKSELB_SEL(3):
+            freq = CLK_RTC_32K_CLK;
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__((weak)) void SystemInitHook(void)
+{
+    /* Void implementation of the weak function. */
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/system_RW612.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/system_RW612.h
new file mode 100644
index 0000000000..5121ff1ed0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/device/system_RW612.h
@@ -0,0 +1,112 @@
+/*
+** ###################################################################
+**     Processors:          RW612ETA2I
+**                          RW612HNA2I
+**                          RW612UKA2I
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RW61X User manual Rev. 0.95, June 2022
+**     Version:             rev. 1.0, 2021-03-16
+**     Build:               b231201
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2023 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2021-03-16)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RW612
+ * @version 1.0
+ * @date 2023-12-01
+ * @brief Device specific configuration file for RW612 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+#ifndef _SYSTEM_RW612_H_
+#define _SYSTEM_RW612_H_                    /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define CLK_XTAL_OSC_CLK_38400KHZ 38400000u /* XTAL OSC frequency 38.4MHz */
+#define CLK_XTAL_OSC_CLK_40000KHZ 40000000u /* XTAL OSC frequency 40MHz */
+
+#ifndef CLK_XTAL_OSC_CLK
+#define CLK_XTAL_OSC_CLK \
+    (((AON_SOC_CIU->STRAP_RDBK & 0x20U) == 0U) ? CLK_XTAL_OSC_CLK_38400KHZ : CLK_XTAL_OSC_CLK_40000KHZ)
+#endif
+#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz (32k_clk) */
+#ifndef CLK_EXT_CLKIN
+#define CLK_EXT_CLKIN 0u /* Default external CLKIN pin clock */
+#endif
+#define DEFAULT_SYSTEM_CLOCK 260000000u /* Default System clock value */
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_RW612_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/freertos/fsl_usart_freertos.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/freertos/fsl_usart_freertos.c
new file mode 100644
index 0000000000..f63e301579
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/freertos/fsl_usart_freertos.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_usart_freertos.h"
+#include <FreeRTOS.h>
+#include <event_groups.h>
+#include <semphr.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_freertos"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void USART_RTOS_Callback(USART_Type *base, usart_handle_t *state, status_t status, void *param)
+{
+    usart_rtos_handle_t *handle = (usart_rtos_handle_t *)param;
+    BaseType_t xHigherPriorityTaskWoken, xResult;
+
+    xHigherPriorityTaskWoken = pdFALSE;
+    xResult                  = pdFAIL;
+
+    if (status == kStatus_USART_RxIdle)
+    {
+        xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_USART_COMPLETE, &xHigherPriorityTaskWoken);
+    }
+    else if (status == kStatus_USART_TxIdle)
+    {
+        xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_USART_COMPLETE, &xHigherPriorityTaskWoken);
+    }
+    else if (status == kStatus_USART_RxRingBufferOverrun)
+    {
+        xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_USART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken);
+    }
+    else
+    {
+        xResult = pdFAIL;
+    }
+
+    if (xResult != pdFAIL)
+    {
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : USART_RTOS_Init
+ * Description   : Initializes the USART instance for application
+ *
+ *END**************************************************************************/
+/*!
+ * brief Initializes a USART instance for operation in RTOS.
+ *
+ * param handle The RTOS USART handle, the pointer to allocated space for RTOS context.
+ * param t_handle The pointer to allocated space where to store transactional layer internal state.
+ * param cfg The pointer to the parameters required to configure the USART after initialization.
+ * return kStatus_Success, others fail.
+ */
+int USART_RTOS_Init(usart_rtos_handle_t *handle, usart_handle_t *t_handle, const struct rtos_usart_config *cfg)
+{
+    status_t status;
+    usart_config_t defcfg;
+
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (NULL == t_handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (NULL == cfg)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (NULL == cfg->base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (0U == cfg->srcclk)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (0U == cfg->baudrate)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    handle->base    = cfg->base;
+    handle->t_state = t_handle;
+
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->txSemaphore = xSemaphoreCreateMutexStatic(&handle->txSemaphoreBuffer);
+#else
+    handle->txSemaphore = xSemaphoreCreateMutex();
+#endif
+    if (NULL == handle->txSemaphore)
+    {
+        return kStatus_Fail;
+    }
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->rxSemaphore = xSemaphoreCreateMutexStatic(&handle->rxSemaphoreBuffer);
+#else
+    handle->rxSemaphore = xSemaphoreCreateMutex();
+#endif
+    if (NULL == handle->rxSemaphore)
+    {
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->txEvent = xEventGroupCreateStatic(&handle->txEventBuffer);
+#else
+    handle->txEvent = xEventGroupCreate();
+#endif
+    if (NULL == handle->txEvent)
+    {
+        vSemaphoreDelete(handle->rxSemaphore);
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->rxEvent = xEventGroupCreateStatic(&handle->rxEventBuffer);
+#else
+    handle->rxEvent = xEventGroupCreate();
+#endif
+    if (NULL == handle->rxEvent)
+    {
+        vEventGroupDelete(handle->txEvent);
+        vSemaphoreDelete(handle->rxSemaphore);
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+    USART_GetDefaultConfig(&defcfg);
+
+    defcfg.baudRate_Bps = cfg->baudrate;
+    defcfg.parityMode   = cfg->parity;
+    defcfg.enableTx     = true;
+    defcfg.enableRx     = true;
+    defcfg.enableHardwareFlowControl = cfg->enableHardwareFlowControl;
+
+    status = USART_Init(handle->base, &defcfg, cfg->srcclk);
+    if (status != kStatus_Success)
+    {
+        vEventGroupDelete(handle->rxEvent);
+        vEventGroupDelete(handle->txEvent);
+        vSemaphoreDelete(handle->rxSemaphore);
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+    status = USART_TransferCreateHandle(handle->base, handle->t_state, USART_RTOS_Callback, handle);
+    if (status != kStatus_Success)
+    {
+        vEventGroupDelete(handle->rxEvent);
+        vEventGroupDelete(handle->txEvent);
+        vSemaphoreDelete(handle->rxSemaphore);
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+    USART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size);
+    return kStatus_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : USART_RTOS_Deinit
+ * Description   : Deinitializes the USART instance and frees resources
+ *
+ *END**************************************************************************/
+/*!
+ * brief Deinitializes a USART instance for operation.
+ *
+ * This function deinitializes the USART module, sets all register values to reset value,
+ * and releases the resources.
+ *
+ * param handle The RTOS USART handle.
+ */
+int USART_RTOS_Deinit(usart_rtos_handle_t *handle)
+{
+    USART_Deinit(handle->base);
+
+    vEventGroupDelete(handle->txEvent);
+    vEventGroupDelete(handle->rxEvent);
+
+    /* Give the semaphore. This is for functional safety */
+    (void)xSemaphoreGive(handle->txSemaphore);
+    (void)xSemaphoreGive(handle->rxSemaphore);
+
+    vSemaphoreDelete(handle->txSemaphore);
+    vSemaphoreDelete(handle->rxSemaphore);
+
+    /* Invalidate the handle */
+    handle->base    = NULL;
+    handle->t_state = NULL;
+
+    return kStatus_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : USART_RTOS_Send
+ * Description   : Initializes the USART instance for application
+ *
+ *END**************************************************************************/
+/*!
+ * brief Sends data in the background.
+ *
+ * This function sends data. It is a synchronous API.
+ * If the hardware buffer is full, the task is in the blocked state.
+ *
+ * param handle The RTOS USART handle.
+ * param buffer The pointer to buffer to send.
+ * param length The number of bytes to send.
+ */
+int USART_RTOS_Send(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length)
+{
+    EventBits_t ev;
+    int retval = kStatus_Success;
+    status_t status;
+
+    if (NULL == handle->base)
+    {
+        /* Invalid handle. */
+        return kStatus_Fail;
+    }
+    if (0U == length)
+    {
+        return kStatus_Success;
+    }
+    if (NULL == buffer)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0))
+    {
+        /* We could not take the semaphore, exit with 0 data received */
+        return kStatus_Fail;
+    }
+
+    handle->txTransfer.data     = (uint8_t *)buffer;
+    handle->txTransfer.dataSize = (uint32_t)length;
+
+    /* Non-blocking call */
+    status = USART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+
+    ev = xEventGroupWaitBits(handle->txEvent, RTOS_USART_COMPLETE, pdTRUE, pdFALSE, portMAX_DELAY);
+    if ((ev & RTOS_USART_COMPLETE) == 0U)
+    {
+        retval = kStatus_Fail;
+    }
+
+    if (pdFALSE == xSemaphoreGive(handle->txSemaphore))
+    {
+        /* We could not post the semaphore, exit with error */
+        retval = kStatus_Fail;
+    }
+
+    return retval;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : USART_RTOS_Recv
+ * Description   : Receives chars for the application
+ *
+ *END**************************************************************************/
+/*!
+ * brief Receives data.
+ *
+ * This function receives data from USART. It is a synchronous API. If data is immediately available,
+ * it is returned immediately and the number of bytes received.
+ *
+ * param handle The RTOS USART handle.
+ * param buffer The pointer to buffer where to write received data.
+ * param length The number of bytes to receive.
+ * param received The pointer to a variable of size_t where the number of received data is filled.
+ */
+int USART_RTOS_Receive(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received)
+{
+    EventBits_t ev;
+    size_t n              = 0;
+    int retval            = kStatus_Fail;
+    size_t local_received = 0;
+    status_t status;
+
+    if (NULL == handle->base)
+    {
+        /* Invalid handle. */
+        return kStatus_Fail;
+    }
+    if (0U == length)
+    {
+        if (received != NULL)
+        {
+            *received = n;
+        }
+        return kStatus_Success;
+    }
+    if (NULL == buffer)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* New transfer can be performed only after current one is finished */
+    if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY))
+    {
+        /* We could not take the semaphore, exit with 0 data received */
+        return kStatus_Fail;
+    }
+
+    handle->rxTransfer.data     = buffer;
+    handle->rxTransfer.dataSize = (uint32_t)length;
+
+    /* Non-blocking call */
+    status = USART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->rxSemaphore);
+        return kStatus_Fail;
+    }
+
+    ev = xEventGroupWaitBits(handle->rxEvent, RTOS_USART_COMPLETE | RTOS_USART_RING_BUFFER_OVERRUN, pdTRUE, pdFALSE,
+                             portMAX_DELAY);
+    if ((ev & RTOS_USART_RING_BUFFER_OVERRUN) != 0U)
+    {
+        /* Stop data transfer to application buffer, ring buffer is still active */
+        USART_TransferAbortReceive(handle->base, handle->t_state);
+        /* Prevent false indication of successful transfer in next call of USART_RTOS_Receive.
+           RTOS_USART_COMPLETE flag could be set meanwhile overrun is handled */
+        (void)xEventGroupClearBits(handle->rxEvent, RTOS_USART_COMPLETE);
+        retval         = kStatus_USART_RxRingBufferOverrun;
+        local_received = 0;
+    }
+    else if ((ev & RTOS_USART_COMPLETE) != 0U)
+    {
+        retval         = kStatus_Success;
+        local_received = length;
+    }
+    else
+    {
+        retval         = kStatus_USART_RxError;
+        local_received = 0;
+    }
+
+    /* Prevent repetitive NULL check */
+    if (received != NULL)
+    {
+        *received = local_received;
+    }
+
+    /* Enable next transfer. Current one is finished */
+    if (pdFALSE == xSemaphoreGive(handle->rxSemaphore))
+    {
+        /* We could not post the semaphore, exit with error */
+        retval = kStatus_Fail;
+    }
+    return retval;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/freertos/fsl_usart_freertos.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/freertos/fsl_usart_freertos.h
new file mode 100644
index 0000000000..11057ed82a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/freertos/fsl_usart_freertos.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __FSL_USART_FREERTOS_H__
+#define __FSL_USART_FREERTOS_H__
+
+#include "fsl_usart.h"
+#include <FreeRTOS.h>
+#include <event_groups.h>
+#include <semphr.h>
+
+/*!
+ * @addtogroup usart_freertos_driver
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART FreeRTOS driver version. */
+#define FSL_USART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 7, 0))
+/*@}*/
+
+/*! @brief FLEX USART configuration structure */
+struct rtos_usart_config
+{
+    USART_Type *base;                /*!< USART base address */
+    uint32_t srcclk;                 /*!< USART source clock in Hz*/
+    uint32_t baudrate;               /*!< Desired communication speed */
+    usart_parity_mode_t parity;      /*!< Parity setting */
+    usart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */
+    uint8_t *buffer;                 /*!< Buffer for background reception */
+    uint32_t buffer_size;            /*!< Size of buffer for background reception */
+    bool enableHardwareFlowControl;  /*!< Enable hardware control RTS/CTS */
+};
+
+/*! @brief FLEX USART FreeRTOS handle */
+typedef struct _usart_rtos_handle
+{
+    USART_Type *base;              /*!< USART base address */
+    usart_transfer_t txTransfer;   /*!< TX transfer structure */
+    usart_transfer_t rxTransfer;   /*!< RX transfer structure */
+    SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */
+    SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */
+#define RTOS_USART_COMPLETE                0x1U
+#define RTOS_USART_RING_BUFFER_OVERRUN     0x2U
+#define RTOS_USART_HARDWARE_BUFFER_OVERRUN 0x4U
+    EventGroupHandle_t rxEvent; /*!< RX completion event */
+    EventGroupHandle_t txEvent; /*!< TX completion event */
+    void *t_state;              /*!< Transactional state of the underlying driver */
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */
+    StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */
+    StaticEventGroup_t txEventBuffer;    /*!< Statically allocated memory for txEvent */
+    StaticEventGroup_t rxEventBuffer;    /*!< Statically allocated memory for rxEvent */
+#endif
+} usart_rtos_handle_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name USART RTOS Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance for operation in RTOS.
+ *
+ * @param handle The RTOS USART handle, the pointer to allocated space for RTOS context.
+ * @param t_handle The pointer to allocated space where to store transactional layer internal state.
+ * @param cfg The pointer to the parameters required to configure the USART after initialization.
+ * @return 0 succeed, others fail.
+ */
+int USART_RTOS_Init(usart_rtos_handle_t *handle, usart_handle_t *t_handle, const struct rtos_usart_config *cfg);
+
+/*!
+ * @brief Deinitializes a USART instance for operation.
+ *
+ * This function deinitializes the USART module, sets all register values to reset value,
+ * and releases the resources.
+ *
+ * @param handle The RTOS USART handle.
+ */
+int USART_RTOS_Deinit(usart_rtos_handle_t *handle);
+
+/*!
+ * @name USART transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Sends data in the background.
+ *
+ * This function sends data. It is a synchronous API.
+ * If the hardware buffer is full, the task is in the blocked state.
+ *
+ * @param handle The RTOS USART handle.
+ * @param buffer The pointer to buffer to send.
+ * @param length The number of bytes to send.
+ */
+int USART_RTOS_Send(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length);
+
+/*!
+ * @brief Receives data.
+ *
+ * This function receives data from USART. It is a synchronous API. If data is immediately available,
+ * it is returned immediately and the number of bytes received.
+ *
+ * @param handle The RTOS USART handle.
+ * @param buffer The pointer to buffer where to write received data.
+ * @param length The number of bytes to receive.
+ * @param received The pointer to a variable of size_t where the number of received data is filled.
+ */
+int USART_RTOS_Receive(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_USART_FREERTOS_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_cache.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_cache.c
new file mode 100644
index 0000000000..b58269bf17
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_cache.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright 2016-2021, 2023-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cache.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cache_cache64"
+#endif
+
+#if (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0)
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of CACHE64_CTRL peripheral base address. */
+static CACHE64_CTRL_Type *const s_cache64ctrlBases[] = CACHE64_CTRL_BASE_PTRS;
+
+#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
+/* Array of CACHE64_POLSEL peripheral base address. */
+static CACHE64_POLSEL_Type *const s_cache64polselBases[] = CACHE64_POLSEL_BASE_PTRS;
+#endif
+
+#if (defined(CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT))
+#define CACHE64_PHYMEM_COLUM_COUNT CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT
+/* Array of CACHE64 physical memory base address, 
+  it is a 2D array, the row indicate cache instance,
+  the column indicate the alias of one instance.  */
+static uint32_t const s_cache64PhymemBases[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT] = CACHE64_CTRL_PHYMEM_BASES;
+/* Array of CACHE64 physical size base address, 
+  it is a 2D array, the row indicate cache instance,
+  the column indicate the alias of one instance.  */
+static uint32_t const s_cache64PhymemSizes[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT] = CACHE64_CTRL_PHYMEM_SIZES;
+#else
+#define CACHE64_PHYMEM_COLUM_COUNT 1
+static uint32_t const s_cache64PhymemBases[] = CACHE64_CTRL_PHYMEM_BASES;
+static uint32_t const s_cache64PhymemSizes[] = CACHE64_CTRL_PHYMEM_SIZES;
+#endif
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#ifdef CACHE64_CLOCKS
+/* Array of CACHE64_CTRL clock name. */
+static const clock_ip_name_t s_cache64Clocks[] = CACHE64_CLOCKS;
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+volatile uint8_t g_cache64MemPhyAliasId = 0U;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
+/*!
+ * brief Returns an instance number given periphearl base address.
+ *
+ * param base The peripheral base address.
+ * return CACHE64_POLSEL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base)
+{
+    uint32_t i;
+
+    for (i = 0; i < ARRAY_SIZE(s_cache64polselBases); i++)
+    {
+        if (MSDK_REG_SECURE_ADDR(base) == MSDK_REG_SECURE_ADDR(s_cache64polselBases[i]))
+        {
+            break;
+        }
+    }
+
+    assert(i < ARRAY_SIZE(s_cache64polselBases));
+
+    return i;
+}
+#endif
+
+/*!
+ * brief Returns an instance number given physical memory address.
+ *
+ * param address The physical memory address.
+ * return CACHE64_CTRL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstanceByAddr(uint32_t address)
+{
+    uint32_t i = 0UL;
+    uint32_t phyMemBase[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+    uint32_t phyMemSize[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+    memcpy(phyMemBase, s_cache64PhymemBases, sizeof(s_cache64PhymemBases));
+    memcpy(phyMemSize, s_cache64PhymemSizes, sizeof(s_cache64PhymemSizes));
+
+    while(i < ARRAY_SIZE(s_cache64ctrlBases))
+    {
+        g_cache64MemPhyAliasId = 0U;
+        while(g_cache64MemPhyAliasId < CACHE64_PHYMEM_COLUM_COUNT)
+        {
+            if ((MSDK_REG_SECURE_ADDR(address) >= MSDK_REG_SECURE_ADDR(phyMemBase[i][g_cache64MemPhyAliasId])) && (MSDK_REG_SECURE_ADDR(address) < MSDK_REG_SECURE_ADDR(phyMemBase[i][g_cache64MemPhyAliasId] + phyMemSize[i][g_cache64MemPhyAliasId] - 0x01U)))
+            {
+                return i;
+            }
+            g_cache64MemPhyAliasId++;
+        }
+        i++;
+    }
+		
+    assert(false);
+    return 0xFFFFFFFFUL;
+}
+
+#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
+/*!
+ * @brief Initializes an CACHE64 instance with the user configuration structure.
+ *
+ * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ *
+ * @param base CACHE64_POLSEL peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @retval kStatus_Success CACHE64 initialize succeed
+ */
+status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config)
+{
+    volatile uint32_t *topReg = &base->REG0_TOP;
+    uint32_t i;
+    uint32_t polsel = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#ifdef CACHE64_CLOCKS
+    uint32_t instance = CACHE64_GetInstance(base);
+
+    /* Enable CACHE64 clock */
+    CLOCK_EnableClock(s_cache64Clocks[instance]);
+#endif
+#endif
+
+    for (i = 0; i < CACHE64_REGION_NUM - 1U; i++)
+    {
+        assert((config->boundaryAddr[i] & (CACHE64_REGION_ALIGNMENT - 1U)) == 0U);
+        ((volatile uint32_t *)topReg)[i] = config->boundaryAddr[i] >= CACHE64_REGION_ALIGNMENT ?
+                                               config->boundaryAddr[i] - CACHE64_REGION_ALIGNMENT :
+                                               0U;
+    }
+
+    for (i = 0; i < CACHE64_REGION_NUM; i++)
+    {
+        polsel |= (((uint32_t)config->policy[i]) << (2U * i));
+    }
+    base->POLSEL = polsel;
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the CACHE64 configuration structure to a default value. The default
+ * values are first region covers whole cacheable area, and policy set to write back.
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void CACHE64_GetDefaultConfig(cache64_config_t *config)
+{
+    uint32_t phyMemSize[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+    memcpy(phyMemSize, s_cache64PhymemSizes, sizeof(s_cache64PhymemSizes));
+    (void)memset(config, 0, sizeof(cache64_config_t));
+
+    config->boundaryAddr[0] = phyMemSize[0][g_cache64MemPhyAliasId];
+    config->policy[0]       = kCACHE64_PolicyWriteBack;
+}
+#endif
+
+/*!
+ * brief Enables the cache.
+ *
+ */
+void CACHE64_EnableCache(CACHE64_CTRL_Type *base)
+{
+    /* if CACHE is not enabled */
+    if ((base->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U)
+    {
+        /* First, invalidate the entire cache. */
+        CACHE64_InvalidateCache(base);
+
+        /* Now enable the cache. */
+        base->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK;
+    }
+}
+
+/*!
+ * brief Disables the cache.
+ *
+ */
+void CACHE64_DisableCache(CACHE64_CTRL_Type *base)
+{
+    /* if CACHE is enabled */
+    if ((base->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U)
+    {
+        /* First, push any modified contents. */
+        CACHE64_CleanCache(base);
+
+        /* Now disable the cache. */
+        base->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK;
+    }
+}
+
+/*!
+ * brief Invalidates the cache.
+ *
+ */
+void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
+{
+    /* Invalidate all lines in both ways and initiate the cache command. */
+    base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
+
+    /* Wait until the cache command completes. */
+    while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
+    {
+    }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+    base->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK);
+}
+
+/*!
+ * brief Invalidates cache by range.
+ *
+ * param address The physical address of cache.
+ * param size_byte size of the memory to be invalidated, should be larger than 0.
+ * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
+{
+    if (size_byte > 0UL)
+    {
+        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size_byte - 0x01U);
+        uint32_t pccReg  = 0;
+        /* Align address to cache line size. */
+        uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
+        uint32_t instance  = CACHE64_GetInstanceByAddr(address);
+        uint32_t endLim;
+        CACHE64_CTRL_Type *base;
+        uint32_t phyMemBase[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+        uint32_t phyMemSize[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+        memcpy(phyMemBase, s_cache64PhymemBases, sizeof(s_cache64PhymemBases));
+        memcpy(phyMemSize, s_cache64PhymemSizes, sizeof(s_cache64PhymemSizes));
+
+        if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+        {
+            return;
+        }
+        base    = s_cache64ctrlBases[instance];
+        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
+        endAddr = endAddr > endLim ? endLim : endAddr;
+
+        /* Set the invalidate by line command and use the physical address. */
+        pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+        base->CLCR = pccReg;
+
+        while (startAddr < endAddr)
+        {
+            /* Set the address and initiate the command. */
+            base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+            /* Wait until the cache command completes. */
+            while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+            {
+            }
+            startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
+        }
+    }
+}
+
+/*!
+ * brief Cleans the cache.
+ *
+ */
+void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
+{
+    /* Enable the to push all modified lines. */
+    base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
+
+    /* Wait until the cache command completes. */
+    while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
+    {
+    }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+    base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK);
+}
+
+/*!
+ * brief Cleans cache by range.
+ *
+ * param address The physical address of cache.
+ * param size_byte size of the memory to be cleaned, should be larger than 0.
+ * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
+{
+    if (size_byte > 0UL)
+    {
+        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size_byte - 0x01U);
+        uint32_t pccReg  = 0;
+        /* Align address to cache line size. */
+        uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
+        uint32_t instance  = CACHE64_GetInstanceByAddr(address);
+        uint32_t endLim;
+        CACHE64_CTRL_Type *base;
+        uint32_t phyMemBase[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+        uint32_t phyMemSize[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+        memcpy(phyMemBase, s_cache64PhymemBases, sizeof(s_cache64PhymemBases));
+        memcpy(phyMemSize, s_cache64PhymemSizes, sizeof(s_cache64PhymemSizes));
+
+        if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+        {
+            return;
+        }
+        base    = s_cache64ctrlBases[instance];
+        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
+        endAddr = endAddr > endLim ? endLim : endAddr;
+
+        /* Set the push by line command. */
+        pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+        base->CLCR = pccReg;
+
+        while (startAddr < endAddr)
+        {
+            /* Set the address and initiate the command. */
+            base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+            /* Wait until the cache command completes. */
+            while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+            {
+            }
+            startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
+        }
+    }
+}
+
+/*!
+ * brief Cleans and invalidates the cache.
+ *
+ */
+void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
+{
+    /* Push and invalidate all. */
+    base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK |
+                 CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
+
+    /* Wait until the cache command completes. */
+    while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
+    {
+    }
+
+    /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+    base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK |
+                   CACHE64_CTRL_CCR_INVW1_MASK);
+}
+
+/*!
+ * brief Cleans and invalidate cache by range.
+ *
+ * param address The physical address of cache.
+ * param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
+ * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
+{
+    if (size_byte > 0UL)
+    {
+        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size_byte - 0x01U);
+        uint32_t pccReg  = 0;
+        /* Align address to cache line size. */
+        uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
+        uint32_t instance  = CACHE64_GetInstanceByAddr(address);
+        uint32_t endLim;
+        CACHE64_CTRL_Type *base;
+        uint32_t phyMemBase[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+        uint32_t phyMemSize[FSL_FEATURE_SOC_CACHE64_CTRL_COUNT][CACHE64_PHYMEM_COLUM_COUNT];
+        memcpy(phyMemBase, s_cache64PhymemBases, sizeof(s_cache64PhymemBases));
+        memcpy(phyMemSize, s_cache64PhymemSizes, sizeof(s_cache64PhymemSizes));
+
+        if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+        {
+            return;
+        }
+        base    = s_cache64ctrlBases[instance];
+        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
+        endAddr = endAddr > endLim ? endLim : endAddr;
+
+        /* Set the push by line command. */
+        pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+        base->CLCR = pccReg;
+
+        while (startAddr < endAddr)
+        {
+            /* Set the address and initiate the command. */
+            base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+            /* Wait until the cache command completes. */
+            while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+            {
+            }
+            startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
+        }
+    }
+}
+
+#if !(defined(FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF) && FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF)
+/*!
+ * brief Enable the cache write buffer.
+ *
+ */
+void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CCR |= CACHE64_CTRL_CCR_ENWRBUF_MASK;
+    }
+    else
+    {
+        base->CCR &= ~CACHE64_CTRL_CCR_ENWRBUF_MASK;
+    }
+}
+
+#endif
+
+#endif /* FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0 */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_cache.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_cache.h
new file mode 100644
index 0000000000..726a18ff27
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_cache.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2016-2021, 2023-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_CACHE_H_
+#define FSL_CACHE_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cache64
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief cache driver version. */
+#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 8))
+/*! @} */
+
+/*! @brief cache line size. */
+#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
+
+#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
+/*! @brief cache region number. */
+#define CACHE64_REGION_NUM (3U)
+/*! @brief cache region alignment. */
+#define CACHE64_REGION_ALIGNMENT (0x400U)
+
+/*! @brief Level 2 cache controller way size. */
+typedef enum _cache64_policy
+{
+    kCACHE64_PolicyNonCacheable = 0, /*!< Non-cacheable */
+    kCACHE64_PolicyWriteThrough = 1, /*!< Write through */
+    kCACHE64_PolicyWriteBack    = 2, /*!< Write back */
+} cache64_policy_t;
+
+/*! @brief CACHE64 configuration structure. */
+typedef struct _cache64_config
+{
+    /*!< The cache controller can divide whole memory into 3 regions.
+     * Boundary address is the FlexSPI internal address (start from 0) instead of system
+     * address (start from FlexSPI AMBA base) to split adjacent regions and must be 1KB
+     * aligned. The boundary address itself locates in upper region. */
+    uint32_t boundaryAddr[CACHE64_REGION_NUM - 1];
+    /*!< Cacheable policy for each region. */
+    cache64_policy_t policy[CACHE64_REGION_NUM];
+} cache64_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name cache control for cache64
+ *@{
+ */
+
+#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
+/*!
+ * @brief Returns an instance number given periphearl base address.
+ *
+ * @param base The peripheral base address.
+ * @return CACHE64_POLSEL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base);
+#endif
+
+/*!
+ * brief Returns an instance number given physical memory address.
+ *
+ * param address The physical memory address.
+ * @return CACHE64_CTRL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstanceByAddr(uint32_t address);
+
+#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
+/*!
+ * @brief Initializes an CACHE64 instance with the user configuration structure.
+ *
+ * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ *
+ * @param base CACHE64_POLSEL peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @retval kStatus_Success CACHE64 initialize succeed
+ */
+status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the CACHE64 configuration structure to a default value. The default
+ * values are first region covers whole cacheable area, and policy set to write back.
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void CACHE64_GetDefaultConfig(cache64_config_t *config);
+#endif
+
+/*!
+ * @brief Enables the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_EnableCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Disables the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_DisableCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Invalidates the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Invalidates cache by range.
+ *
+ * @param address The physical address of cache.
+ * @param size_byte size of the memory to be invalidated, should be larger than 0.
+ * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_CleanCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Cleans cache by range.
+ *
+ * @param address The physical address of cache.
+ * @param size_byte size of the memory to be cleaned, should be larger than 0.
+ * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans and invalidates the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Cleans and invalidate cache by range.
+ *
+ * @param address The physical address of cache.
+ * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
+ * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
+
+#if !(defined(FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF) && FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF)
+/*!
+ * @brief Enables/disables the write buffer.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ * @param enable The enable or disable flag.
+ *       true  - enable the write buffer.
+ *       false - disable the write buffer.
+ */
+void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
+#endif
+
+/*! @} */
+
+/*!
+ * @name Unified Cache Control for all caches
+ *@{
+ */
+
+/*!
+ * @brief Invalidates instruction cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be invalidated, should be larger than 0.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    CACHE64_InvalidateCacheByRange(address, size_byte);
+}
+
+/*!
+ * @brief Invalidates data cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be invalidated, should be larger than 0.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    CACHE64_InvalidateCacheByRange(address, size_byte);
+}
+
+/*!
+ * @brief Clean data cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be cleaned, should be larger than 0.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
+{
+    CACHE64_CleanCacheByRange(address, size_byte);
+}
+
+/*!
+ * @brief Cleans and Invalidates data cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    CACHE64_CleanInvalidateCacheByRange(address, size_byte);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_CACHE_H_*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_clock.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_clock.c
new file mode 100644
index 0000000000..4eea9960d5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_clock.c
@@ -0,0 +1,1702 @@
+/*
+ * Copyright 2020-2024, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
+
+/* Each loop costs 3 cpu cycles */
+#define CLOCK_DELAY_LOOPS(cpuFreq, delayFreq, delayCycles) \
+    ((((cpuFreq) + (delayFreq)-1U) / (delayFreq)) * (delayCycles) / 3U)
+
+#define CLOCK_KHZ(freq) ((freq)*1000UL)
+#define CLOCK_MHZ(freq) (CLOCK_KHZ(freq) * 1000UL)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* External CLK_IN pin clock frequency. */
+volatile uint32_t g_clkinFreq = 0U;
+/* External MCLK in (mclk_in) clock frequency. If not used,
+   set this to 0. Otherwise, set it to the exact rate in Hz this pin is
+   being driven at.*/
+volatile uint32_t g_mclkinFreq = 0U;
+
+static const uint32_t s_avpllFreq[] = {
+    0U,
+    CLOCK_KHZ(2048UL),  /*!< AVPLL channel frequency 2.048MHz */
+    CLOCK_KHZ(4096UL),  /*!< AVPLL channel frequency 4.096MHz */
+    CLOCK_KHZ(6144UL),  /*!< AVPLL channel frequency 6.144MHz */
+    CLOCK_KHZ(8192UL),  /*!< AVPLL channel frequency 8.192MHz */
+    11289600UL,         /*!< AVPLL channel frequency 11.2896MHz */
+    CLOCK_MHZ(12UL),    /*!< AVPLL channel frequency 12MHz */
+    CLOCK_KHZ(12288UL), /*!< AVPLL channel frequency 12.288MHz */
+    CLOCK_KHZ(24576UL), /*!< AVPLL channel frequency 24.576MHz */
+    CLOCK_MHZ(64UL),    /*!< AVPLL channel frequency 64MHz */
+    CLOCK_KHZ(98304UL), /*!< AVPLL channel frequency 98.304MHz */
+};
+
+static const uint32_t s_avpllFreqOff[] = {
+    0U,       /*!< AVPLL channel unchanged */
+    0x53U,    /*!< AVPLL channel frequency 2.048MHz */
+    0x1050U,  /*!< AVPLL channel frequency 4.096MHz */
+    0x4145DU, /*!< AVPLL channel frequency 6.144MHz */
+    0x4145DU, /*!< AVPLL channel frequency 8.192MHz */
+    0x38B3U,  /*!< AVPLL channel frequency 11.2896MHz */
+    0U,       /*!< AVPLL channel frequency 12MHz */
+    0x4145DU, /*!< AVPLL channel frequency 12.288MHz */
+    0x4145DU, /*!< AVPLL channel frequency 24.576MHz */
+    0xCCCDU,  /*!< AVPLL channel frequency 64MHz */
+    0x4145DU, /*!< AVPLL channel frequency 98.304MHz */
+};
+
+static const uint32_t s_avpllPostDiv[] = {
+    0U,   /*!< AVPLL channel unchanged */
+    791U, /*!< AVPLL channel frequency 2.048MHz */
+    395U, /*!< AVPLL channel frequency 4.096MHz */
+    264U, /*!< AVPLL channel frequency 6.144MHz */
+    198U, /*!< AVPLL channel frequency 8.192MHz */
+    143U, /*!< AVPLL channel frequency 11.2896MHz */
+    135U, /*!< AVPLL channel frequency 12MHz */
+    132U, /*!< AVPLL channel frequency 12.288MHz */
+    66U,  /*!< AVPLL channel frequency 24.576MHz */
+    25U,  /*!< AVPLL channel frequency 64MHz */
+    16U,  /*!< AVPLL channel frequency 98.304MHz */
+};
+
+static const uint32_t s_avpllPostDiv0p5[] = {
+    0U, /*!< AVPLL channel unchanged */
+    0U, /*!< AVPLL channel frequency 2.048MHz */
+    0U, /*!< AVPLL channel frequency 4.096MHz */
+    0U, /*!< AVPLL channel frequency 6.144MHz */
+    0U, /*!< AVPLL channel frequency 8.192MHz */
+    0U, /*!< AVPLL channel frequency 11.2896MHz */
+    0U, /*!< AVPLL channel frequency 12MHz */
+    0U, /*!< AVPLL channel frequency 12.288MHz */
+    0U, /*!< AVPLL channel frequency 24.576MHz */
+    0U, /*!< AVPLL channel frequency 64MHz */
+    1U, /*!< AVPLL channel frequency 98.304MHz */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Workaround iar/armgcc optimization issue */
+__attribute__((__noinline__))
+static void CLOCK_Delay(uint32_t loop)
+{
+    if (loop > 0U)
+    {
+        __ASM volatile(
+            "1:                             \n"
+            "    SUBS   %0, %0, #1          \n"
+            "    CMP    %0, #0              \n"
+            "    BNE    1b                  \n"
+            :
+            : "r"(loop));
+    }
+}
+
+static void CLOCK_DelayUs(uint32_t us)
+{
+    uint32_t instNum;
+
+    instNum = ((SystemCoreClock + 999999UL) / 1000000UL) * us;
+    CLOCK_Delay((instNum + 2U) / 3U);
+}
+
+/*! @brief  Return Frequency of t3pll_mci_48_60m_irc
+ *  @return Frequency of t3pll_mci_48_60m_irc
+ */
+uint32_t CLOCK_GetT3PllMciIrcClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    if ((SYSPLL_T3->CLKTREE_CTRL_SIX_REG & 0xFU) == 0x5U)
+    {
+        freq = CLOCK_MHZ(2560UL) / 43UL;
+    }
+    else if ((SYSPLL_T3->CLKTREE_CTRL_SIX_REG & 0xFU) == 0xAU)
+    {
+        freq = CLOCK_MHZ(2560UL) / 53UL;
+    }
+    else
+    {
+        /* Only 48MHz and 60MHz is allowed */
+        assert(false);
+    }
+
+    return freq;
+}
+
+/*! @brief  Return Frequency of t3pll_mci_213p3m
+ *  @return Frequency of t3pll_mci_213p3m
+ */
+uint32_t CLOCK_GetT3PllMci213mClkFreq(void)
+{
+    uint32_t freq = CLOCK_KHZ(213300UL);
+    return freq;
+}
+
+/*! @brief  Return Frequency of t3pll_mci_256m
+ *  @return Frequency of t3pll_mci_256m
+ */
+uint32_t CLOCK_GetT3PllMci256mClkFreq(void)
+{
+    uint32_t freq = CLOCK_MHZ(256UL);
+    return freq;
+}
+
+/*! @brief  Return Frequency of t3pll_mci_flexspi_clk
+ *  @return Frequency of t3pll_mci_flexspi_clk
+ */
+uint32_t CLOCK_GetT3PllMciFlexspiClkFreq(void)
+{
+    uint32_t freq = CLOCK_MHZ(365UL);
+    ;
+    return freq;
+}
+
+static uint32_t CLOCK_GetTcpuFvcoFreq(void)
+{
+    uint32_t freq = 0UL;
+    uint32_t steps;
+
+    steps = (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIFT;
+
+    if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_40000KHZ) && (steps >= 75UL) && (steps <= 96UL))
+    {
+        /* Fbdiv from 75 to 96, step 40MHz */
+        steps -= 75UL;
+        freq = CLOCK_MHZ(3000UL) + steps * CLOCK_MHZ(40UL);
+    }
+    else if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_38400KHZ) && (steps >= 78UL) && (steps <= 100UL))
+    {
+        /* Fbdiv from 78 to 100, step 38.4MHz */
+        steps -= 78UL;
+        freq = CLOCK_KHZ(2995200UL) + steps * CLOCK_KHZ(38400UL);
+    }
+    else
+    {
+        assert(false);
+    }
+
+    return freq;
+}
+
+/*! @brief  Return Frequency of tcpu_mci_clk
+ *  return Frequency of tcpu_mci_clk
+ */
+uint32_t CLOCK_GetTcpuMciClkFreq(void)
+{
+    uint32_t freq = CLOCK_GetTcpuFvcoFreq() / 12UL;
+    return freq;
+}
+
+/*! @brief  Return Frequency of tcpu_mci_flexspi_clk
+ *  @return Frequency of tcpu_mci_flexspi_clk
+ */
+uint32_t CLOCK_GetTcpuMciFlexspiClkFreq(void)
+{
+    uint32_t div =
+        (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_SHIFT;
+
+    return CLOCK_GetTcpuFvcoFreq() / (12UL - div);
+}
+
+/*! @brief  Return Frequency of tddr_mci_flexspi_clk
+ *  @return Frequency of tddr_mci_flexspi_clk
+ */
+uint32_t CLOCK_GetTddrMciFlexspiClkFreq(void)
+{
+    uint32_t div =
+        (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK) >> SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_SHIFT;
+    /* TDDR FVCO fixed to 3.2GHz */
+    return CLOCK_MHZ(3200UL) / (11UL - div);
+}
+
+/*! @brief  Return Frequency of tddr_mci_enet_clk
+ *  @return Frequency of tddr_mci_enet_clk
+ */
+uint32_t CLOCK_GetTddrMciEnetClkFreq(void)
+{
+    uint32_t freq = CLOCK_MHZ(50UL);
+    return freq;
+}
+
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param clk  Which clock to enable, see @ref clock_ip_name_t.
+ */
+void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+    uint32_t index;
+
+    if (clk == kCLOCK_RefClkCauSlp)
+    {
+        PMU->CAU_SLP_CTRL &= ~PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG_MASK;
+        while ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U)
+        {
+        }
+    }
+    else if (((uint32_t)clk & SYS_CLK_GATE_FLAG_MASK) != 0U)
+    {
+        SYSCTL2->SOURCE_CLK_GATE &= ~SYS_CLK_GATE_BIT_MASK(clk);
+        /* Delay 2 40MHz cycles to make it ready. */
+        CLOCK_Delay(CLOCK_DELAY_LOOPS(SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY, 40000000UL, 2U));
+    }
+    else
+    {
+        index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+
+        switch (index)
+        {
+            case CLK_CTL0_PSCCTL0:
+                CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL0_PSCCTL1:
+                CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL0_PSCCTL2:
+                CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL1_PSCCTL0:
+                CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL1_PSCCTL1:
+                CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL1_PSCCTL2:
+                CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            default:
+                assert(false);
+                break;
+        }
+
+        if (clk == kCLOCK_Gau)
+        {
+            SYSCTL2->GAU_CTRL = SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_MASK | SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_MASK |
+                                SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_MASK | SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_MASK |
+                                SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_MASK;
+        }
+    }
+}
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param clk  Which clock to disable, see @ref clock_ip_name_t.
+ */
+void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+    uint32_t index;
+
+    if (clk == kCLOCK_RefClkCauSlp)
+    {
+        PMU->CAU_SLP_CTRL |= PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG_MASK;
+    }
+    else if (((uint32_t)clk & SYS_CLK_GATE_FLAG_MASK) != 0U)
+    {
+        SYSCTL2->SOURCE_CLK_GATE |= SYS_CLK_GATE_BIT_MASK(clk);
+    }
+    else
+    {
+        index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+        switch (index)
+        {
+            case CLK_CTL0_PSCCTL0:
+                CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL0_PSCCTL1:
+                CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL0_PSCCTL2:
+                CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL1_PSCCTL0:
+                CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL1_PSCCTL1:
+                CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            case CLK_CTL1_PSCCTL2:
+                CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+                break;
+            default:
+                assert(false);
+                break;
+        }
+
+        if (clk == kCLOCK_Gau)
+        {
+            SYSCTL2->GAU_CTRL = 0U;
+        }
+    }
+}
+
+/**
+ * @brief   Configure the clock selection muxes.
+ * @param   connection  : Clock to be configured.
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+    bool final_descriptor = false;
+    uint32_t i;
+    volatile uint32_t *pClkSel;
+
+    if (((uint32_t)connection & PMU_TUPLE_MUX_AVAIL) != 0U)
+    {
+        *PMU_TUPLE_REG(PMU, connection) = PMU_TUPLE_SEL(connection);
+    }
+    else if (((uint32_t)connection & CLKOUT_TUPLE_MUX_AVAIL) != 0U)
+    {
+        CLKCTL1->CLKOUTSEL0 = CLKCTL1_CLKOUTSEL0_SEL(((uint32_t)connection >> 4U) & 0x7U);
+        CLKCTL1->CLKOUTSEL1 = CLKCTL1_CLKOUTSEL1_SEL(((uint32_t)connection >> 8U) & 0x7U);
+        CLKCTL1->CLKOUTSEL2 = CLKCTL1_CLKOUTSEL2_SEL(((uint32_t)connection >> 12U) & 0x7U);
+    }
+    else
+    {
+        for (i = 0U; (i < 2U) && (!final_descriptor); i++)
+        {
+            connection =
+                (clock_attach_id_t)(uint32_t)(((uint32_t)connection) >> (i * 16U)); /*!<  pick up next descriptor */
+
+            if ((((uint32_t)connection) & CLKCTL1_TUPLE_FLAG_MASK) != 0UL)
+            {
+                pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, connection);
+            }
+            else
+            {
+                pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, connection);
+            }
+
+            if ((((uint32_t)connection) & 0xFFCU) != 0UL)
+            {
+                *pClkSel = CLKCTL_TUPLE_SEL(connection);
+            }
+            else
+            {
+                final_descriptor = true;
+            }
+        }
+    }
+}
+
+/**
+ * @brief   Setup clock dividers.
+ * @param   name        : Clock divider name
+ * @param   divider     : Value to be divided.
+ */
+void CLOCK_SetClkDiv(clock_div_name_t name, uint32_t divider)
+{
+    volatile uint32_t *pClkDiv;
+
+    if ((((uint32_t)name) & CLKCTL1_TUPLE_FLAG_MASK) != 0UL)
+    {
+        pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, name);
+    }
+    else
+    {
+        pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, name);
+    }
+    /* Reset the divider counter */
+    *pClkDiv |= 1UL << 29U;
+
+    if (divider == 0U) /*!<  halt */
+    {
+        *pClkDiv |= 1UL << 30U;
+    }
+    else
+    {
+        *pClkDiv = divider - 1U;
+
+        while (((*pClkDiv) & 0x80000000U) != 0UL)
+        {
+        }
+    }
+}
+
+/*! brief  Return Frequency of selected clock
+ *  return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+    switch (clockName)
+    {
+        case kCLOCK_CoreSysClk:
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_MclkClk:
+            freq = CLOCK_GetMclkClkFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*! @brief  Return Frequency of High-Freq output of FRO
+ *  @return Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFFroFreq(void)
+{
+    return CLOCK_GetT3PllMciIrcClkFreq();
+}
+
+/*! @brief  Return Frequency of SFRO
+ *  @return Frequency of SFRO
+ */
+uint32_t CLOCK_GetSFroFreq(void)
+{
+    return CLOCK_GetT3PllMci256mClkFreq() / 16U;
+}
+
+/*! @brief  Return Frequency of AUDIO PLL (AVPLL CH1)
+ *  @return Frequency of AUDIO PLL
+ */
+uint32_t CLOCK_GetAvPllCh1Freq(void)
+{
+    uint32_t postdiv =
+        (SYSCTL2->AVPLL_CTRL5 & SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_MASK) >> SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_SHIFT;
+    uint32_t i;
+    uint32_t freq = 0U;
+
+    for (i = 1U; i < ARRAY_SIZE(s_avpllPostDiv); i++)
+    {
+        if (s_avpllPostDiv[i] == postdiv)
+        {
+            freq = s_avpllFreq[i];
+            break;
+        }
+    }
+
+    return freq;
+}
+
+/*! @brief  Return Frequency of AVPLL CH2
+ *  @return Frequency of AVPLL CH2
+ */
+uint32_t CLOCK_GetAvPllCh2Freq(void)
+{
+    uint32_t postdiv =
+        (SYSCTL2->AVPLL_CTRL11 & SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_MASK) >> SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_SHIFT;
+    uint32_t i;
+    uint32_t freq = 0U;
+
+    for (i = 1U; i < ARRAY_SIZE(s_avpllPostDiv); i++)
+    {
+        if (s_avpllPostDiv[i] == postdiv)
+        {
+            freq = s_avpllFreq[i];
+            break;
+        }
+    }
+
+    return freq;
+}
+
+static uint32_t CLOCK_GetMainPllClkFreq(void)
+{
+    return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
+}
+
+static uint32_t CLOCK_GetAux0PllClkFreq(void)
+{
+    return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK) + 1U);
+}
+
+static uint32_t CLOCK_GetAux1PllClkFreq(void)
+{
+    return CLOCK_GetT3PllMci213mClkFreq() / ((CLKCTL0->AUX1PLLCLKDIV & CLKCTL0_AUX1PLLCLKDIV_DIV_MASK) + 1U);
+}
+
+static uint32_t CLOCK_GetAudioPllClkFreq(void)
+{
+    return CLOCK_GetAvPllCh1Freq() / ((CLKCTL1->AUDIOPLLCLKDIV & CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK) + 1U);
+}
+
+/* Get MAIN Clk */
+/*! @brief  Return Frequency of main clk
+ *  @return Frequency of main clk
+ */
+uint32_t CLOCK_GetMainClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
+    {
+        case CLKCTL0_MAINCLKSELB_SEL(0):
+            switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
+            {
+                case CLKCTL0_MAINCLKSELA_SEL(0):
+                    freq = CLOCK_GetSysOscFreq();
+                    break;
+                case CLKCTL0_MAINCLKSELA_SEL(1):
+                    freq = CLOCK_GetFFroFreq() / 4U;
+                    break;
+                case CLKCTL0_MAINCLKSELA_SEL(2):
+                    freq = CLOCK_GetLpOscFreq();
+                    break;
+                case CLKCTL0_MAINCLKSELA_SEL(3):
+                    freq = CLOCK_GetFFroFreq();
+                    break;
+                default:
+                    freq = 0U;
+                    break;
+            }
+            break;
+
+        case CLKCTL0_MAINCLKSELB_SEL(1):
+            freq = CLOCK_GetSFroFreq();
+            break;
+
+        case CLKCTL0_MAINCLKSELB_SEL(2):
+            freq = CLOCK_GetMainPllClkFreq();
+            break;
+
+        case CLKCTL0_MAINCLKSELB_SEL(3):
+            freq = CLOCK_GetClk32KFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Get Core/Bus Clk */
+/*! @brief  Return Frequency of core/bus clk
+ *  @return Frequency of core/bus clk
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of systick clk
+ *  @return Frequency of systick clk
+ */
+uint32_t CLOCK_GetSystickClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch (CLKCTL0->SYSTICKFCLKSEL)
+    {
+        case CLKCTL0_SYSTICKFCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSTICKFCLKDIV & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK) + 1U);
+            break;
+
+        case CLKCTL0_SYSTICKFCLKSEL_SEL(1):
+            freq = CLOCK_GetLpOscFreq();
+            break;
+
+        case CLKCTL0_SYSTICKFCLKSEL_SEL(2):
+            freq = CLOCK_GetClk32KFreq();
+            break;
+
+        case CLKCTL0_SYSTICKFCLKSEL_SEL(3):
+            freq = CLOCK_GetSFroFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Get FRG Clk */
+/*! @brief  Return Input frequency for the Fractional baud rate generator
+ *  @return Input Frequency for FRG
+ */
+uint32_t CLOCK_GetFRGClock(uint32_t id)
+{
+    uint32_t freq      = 0U;
+    uint32_t frgPllDiv = 1U;
+    uint32_t clkSel    = 0U;
+    uint32_t frgDiv    = 0U;
+    uint32_t frgMul    = 0U;
+
+    if (id <= 3UL)
+    {
+        clkSel = CLKCTL1->FLEXCOMM[id].FRGCLKSEL & CLKCTL1_FRGCLKSEL_SEL_MASK;
+        frgMul = ((CLKCTL1->FLEXCOMM[id].FRGCTL) & CLKCTL1_FRGCTL_MULT_MASK) >> CLKCTL1_FRGCTL_MULT_SHIFT;
+        frgDiv = ((CLKCTL1->FLEXCOMM[id].FRGCTL) & CLKCTL1_FRGCTL_DIV_MASK) >> CLKCTL1_FRGCTL_DIV_SHIFT;
+    }
+    else if (id == 14UL)
+    {
+        clkSel = CLKCTL1->FRG14CLKSEL & CLKCTL1_FRG14CLKSEL_SEL_MASK;
+        frgMul = ((CLKCTL1->FRG14CTL) & CLKCTL1_FRGCTL_MULT_MASK) >> CLKCTL1_FRGCTL_MULT_SHIFT;
+        frgDiv = ((CLKCTL1->FRG14CTL) & CLKCTL1_FRGCTL_DIV_MASK) >> CLKCTL1_FRGCTL_DIV_SHIFT;
+    }
+    else
+    {
+        assert(false);
+    }
+
+    switch (clkSel)
+    {
+        case CLKCTL1_FRGCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        case CLKCTL1_FRGCLKSEL_SEL(1):
+            frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U;
+            freq      = CLOCK_GetMainPllClkFreq() / frgPllDiv;
+            break;
+
+        case CLKCTL1_FRGCLKSEL_SEL(2):
+            freq = CLOCK_GetSFroFreq();
+            break;
+
+        case CLKCTL1_FRGCLKSEL_SEL(3):
+            freq = CLOCK_GetFFroFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL));
+}
+
+/* Set FRG Clk */
+/*! @brief  Set output of the Fractional baud rate generator
+ * @param   config    : Configuration to set to FRGn clock.
+ */
+void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config)
+{
+    uint32_t i = config->num;
+
+    assert(i <= 14U);
+    assert(config->divider == 255U); /* Always set to 0xFF to use with the fractional baudrate generator.*/
+
+    if (i <= 3UL)
+    {
+        CLKCTL1->FLEXCOMM[i].FRGCLKSEL = (uint32_t)config->sfg_clock_src;
+        CLKCTL1->FLEXCOMM[i].FRGCTL    = (CLKCTL1_FRGCTL_MULT(config->mult) | CLKCTL1_FRGCTL_DIV(config->divider));
+    }
+    else if (i == 14UL)
+    {
+        CLKCTL1->FRG14CLKSEL = (uint32_t)config->sfg_clock_src;
+        CLKCTL1->FRG14CTL    = (CLKCTL1_FRGCTL_MULT(config->mult) | CLKCTL1_FRGCTL_DIV(config->divider));
+    }
+    else
+    {
+        assert(false);
+    }
+}
+
+/*! @brief  Return Frequency of DMIC clk
+ *  @return Frequency of DMIC clk
+ */
+uint32_t CLOCK_GetDmicClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL1->DMIC0FCLKSEL) & CLKCTL1_DMIC0FCLKSEL_SEL_MASK)
+    {
+        case CLKCTL1_DMIC0FCLKSEL_SEL(0):
+            freq = CLOCK_GetSFroFreq();
+            break;
+
+        case CLKCTL1_DMIC0FCLKSEL_SEL(1):
+            freq = CLOCK_GetFFroFreq();
+            break;
+
+        case CLKCTL1_DMIC0FCLKSEL_SEL(2):
+            freq = CLOCK_GetAudioPllClkFreq();
+            break;
+
+        case CLKCTL1_DMIC0FCLKSEL_SEL(3):
+            freq = CLOCK_GetMclkInClkFreq();
+            break;
+
+        case CLKCTL1_DMIC0FCLKSEL_SEL(4):
+            freq = CLOCK_GetLpOscFreq();
+            break;
+
+        case CLKCTL1_DMIC0FCLKSEL_SEL(5):
+            freq = CLOCK_GetClk32KFreq();
+            break;
+
+        case CLKCTL1_DMIC0FCLKSEL_SEL(6):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((CLKCTL1->DMIC0CLKDIV & CLKCTL1_DMIC0CLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of LCD clk
+ *  @return Frequency of LCD clk
+ */
+uint32_t CLOCK_GetLcdClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->LCDFCLKSEL) & CLKCTL0_LCDFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL0_LCDFCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        case CLKCTL0_LCDFCLKSEL_SEL(1):
+            freq = CLOCK_GetT3PllMciFlexspiClkFreq();
+            break;
+
+        case CLKCTL0_LCDFCLKSEL_SEL(2):
+            freq = CLOCK_GetTcpuMciFlexspiClkFreq();
+            break;
+
+        case CLKCTL0_LCDFCLKSEL_SEL(3):
+            freq = CLOCK_GetTddrMciFlexspiClkFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((CLKCTL0->LCDFCLKDIV & CLKCTL0_LCDFCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of WDT clk
+ *  @return Frequency of WDT clk
+ */
+uint32_t CLOCK_GetWdtClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->WDT0FCLKSEL) & CLKCTL0_WDT0FCLKSEL_SEL_MASK)
+    {
+        case CLKCTL0_WDT0FCLKSEL_SEL(0):
+            freq = CLOCK_GetLpOscFreq();
+            break;
+
+        case CLKCTL0_WDT0FCLKSEL_SEL(1):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*! @brief  Return Frequency of mclk
+ *  @return Frequency of mclk clk
+ */
+uint32_t CLOCK_GetMclkClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL1->AUDIOMCLKSEL) & CLKCTL1_AUDIOMCLKSEL_SEL_MASK)
+    {
+        case CLKCTL1_AUDIOMCLKSEL_SEL(0):
+            freq = CLOCK_GetFFroFreq();
+            break;
+        case CLKCTL1_AUDIOMCLKSEL_SEL(1):
+            freq = CLOCK_GetAudioPllClkFreq();
+            break;
+        case CLKCTL1_AUDIOMCLKSEL_SEL(2):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq / ((CLKCTL1->AUDIOMCLKDIV & CLKCTL1_AUDIOMCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of sct
+ *  @return Frequency of sct clk
+ */
+uint32_t CLOCK_GetSctClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->SCTFCLKSEL) & CLKCTL0_SCTFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL0_SCTFCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        case CLKCTL0_SCTFCLKSEL_SEL(1):
+            freq = CLOCK_GetMainPllClkFreq();
+            break;
+
+        case CLKCTL0_SCTFCLKSEL_SEL(2):
+            freq = CLOCK_GetAux0PllClkFreq();
+            break;
+
+        case CLKCTL0_SCTFCLKSEL_SEL(3):
+            freq = CLOCK_GetFFroFreq();
+            break;
+
+        case CLKCTL0_SCTFCLKSEL_SEL(4):
+            freq = CLOCK_GetAux1PllClkFreq();
+            break;
+
+        case CLKCTL0_SCTFCLKSEL_SEL(5):
+            freq = CLOCK_GetAudioPllClkFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((CLKCTL0->SCTFCLKDIV & CLKCTL0_SCTFCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of Flexcomm functional Clock
+ *  @param   id    : flexcomm index to get frequency.
+ *  @return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
+{
+    uint32_t freq   = 0U;
+    uint32_t clkSel = 0U;
+
+    if (id <= 3UL)
+    {
+        clkSel = CLKCTL1->FLEXCOMM[id].FCFCLKSEL;
+    }
+    else if (id == 14UL)
+    {
+        clkSel = CLKCTL1->FC14FCLKSEL;
+    }
+    else
+    {
+        assert(false);
+    }
+
+    switch (clkSel)
+    {
+        case CLKCTL1_FCFCLKSEL_SEL(0):
+            freq = CLOCK_GetSFroFreq();
+            break;
+
+        case CLKCTL1_FCFCLKSEL_SEL(1):
+            freq = CLOCK_GetFFroFreq();
+            break;
+
+        case CLKCTL1_FCFCLKSEL_SEL(2):
+            freq = CLOCK_GetAudioPllClkFreq();
+            break;
+
+        case CLKCTL1_FCFCLKSEL_SEL(3):
+            freq = CLOCK_GetMclkInClkFreq();
+            break;
+
+        case CLKCTL1_FCFCLKSEL_SEL(4):
+            freq = CLOCK_GetFRGClock(id);
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*! @brief  Return Frequency of CTimer Clock
+ *  @param   id    : ctimer index to get frequency.
+ *  @return Frequency of CTimer Clock
+ */
+uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
+{
+    uint32_t freq = 0U;
+
+    assert(id < 4U);
+
+    switch ((CLKCTL1->CT32BITFCLKSEL[id]) & CLKCTL1_CT32BITFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL1_CT32BITFCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        case CLKCTL1_CT32BITFCLKSEL_SEL(1):
+            freq = CLOCK_GetSFroFreq();
+            break;
+
+        case CLKCTL1_CT32BITFCLKSEL_SEL(2):
+            freq = CLOCK_GetFFroFreq();
+            break;
+
+        case CLKCTL1_CT32BITFCLKSEL_SEL(3):
+            freq = CLOCK_GetAudioPllClkFreq();
+            break;
+
+        case CLKCTL1_CT32BITFCLKSEL_SEL(4):
+            freq = CLOCK_GetMclkInClkFreq();
+            break;
+
+        case CLKCTL1_CT32BITFCLKSEL_SEL(5):
+            freq = CLOCK_GetLpOscFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*! @brief  Return Frequency of Utick Clock
+ *  @return Frequency of Utick Clock
+ */
+uint32_t CLOCK_GetUtickClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->UTICKFCLKSEL) & CLKCTL0_UTICKFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL0_UTICKFCLKSEL_SEL(0):
+            freq = CLOCK_GetLpOscFreq();
+            break;
+
+        case CLKCTL1_CT32BITFCLKSEL_SEL(1):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*! @brief  Return Frequency of FLEXSPI Clock
+ *  @return Frequency of FLEXSPI.
+ */
+uint32_t CLOCK_GetFlexspiClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->FLEXSPIFCLKSEL) & CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL0_FLEXSPIFCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        case CLKCTL0_FLEXSPIFCLKSEL_SEL(1):
+            freq = CLOCK_GetT3PllMciFlexspiClkFreq();
+            break;
+
+        case CLKCTL0_FLEXSPIFCLKSEL_SEL(2):
+            freq = CLOCK_GetAux0PllClkFreq();
+            break;
+
+        case CLKCTL0_FLEXSPIFCLKSEL_SEL(3):
+            freq = CLOCK_GetFFroFreq();
+            break;
+
+        case CLKCTL0_FLEXSPIFCLKSEL_SEL(4):
+            freq = CLOCK_GetAux1PllClkFreq();
+            break;
+
+        case CLKCTL0_FLEXSPIFCLKSEL_SEL(5):
+            freq = CLOCK_GetTddrMciFlexspiClkFreq();
+            break;
+
+        case CLKCTL0_FLEXSPIFCLKSEL_SEL(6):
+            freq = CLOCK_GetT3PllMci256mClkFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of USIM Clock
+ *  @return Frequency of USIM.
+ */
+uint32_t CLOCK_GetUsimClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->USIMFCLKSEL) & CLKCTL0_USIMFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL0_USIMFCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        case CLKCTL0_USIMFCLKSEL_SEL(1):
+            freq = CLOCK_GetAudioPllClkFreq();
+            break;
+
+        case CLKCTL0_USIMFCLKSEL_SEL(2):
+            freq = CLOCK_GetFFroFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((CLKCTL0->USIMFCLKDIV & CLKCTL0_USIMFCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of GAU Clock
+ *  @return Frequency of GAU.
+ */
+uint32_t CLOCK_GetGauClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL0->GAUFCLKSEL) & CLKCTL0_GAUFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL0_GAUFCLKSEL_SEL(0):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        case CLKCTL0_GAUFCLKSEL_SEL(1):
+            freq = CLOCK_GetT3PllMci256mClkFreq();
+            break;
+
+        case CLKCTL0_GAUFCLKSEL_SEL(2):
+            freq = CLOCK_GetAvPllCh2Freq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((CLKCTL0->GAUFCLKDIV & CLKCTL0_GAUFCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief  Return Frequency of OSTimer Clock
+ *  @return Frequency of OSTimer.
+ */
+uint32_t CLOCK_GetOSTimerClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((CLKCTL1->OSEVENTFCLKSEL) & CLKCTL1_OSEVENTFCLKSEL_SEL_MASK)
+    {
+        case CLKCTL1_OSEVENTFCLKSEL_SEL(0):
+            freq = CLOCK_GetLpOscFreq();
+            break;
+
+        case CLKCTL1_OSEVENTFCLKSEL_SEL(1):
+            freq = CLOCK_GetClk32KFreq();
+            break;
+
+        case CLKCTL1_OSEVENTFCLKSEL_SEL(2):
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+
+        case CLKCTL1_OSEVENTFCLKSEL_SEL(3):
+            freq = CLOCK_GetMainClkFreq();
+            break;
+
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*! @brief  Enables and disables 32kHz XTAL
+ *  @param  enable : true to enable 32k XTAL clock, false to disable clock
+ */
+void CLOCK_EnableXtal32K(bool enable)
+{
+    if (enable)
+    {
+        AON_SOC_CIU->PAD_PU_PD_EN1 &=
+            ~(AON_SOC_CIU_PAD_PU_PD_EN1_GPIO22_PU_PD_EN_MASK | AON_SOC_CIU_PAD_PU_PD_EN1_GPIO23_PU_PD_EN_MASK);
+        AON_SOC_CIU->MCI_IOMUX_EN0 |= (3UL << 22);
+        PMU->XTAL32K_CTRL |= PMU_XTAL32K_CTRL_X32K_EN_MASK;
+        while ((PMU->XTAL32K_CTRL & PMU_XTAL32K_CTRL_X32K_RDY_MASK) == 0U)
+        {
+        }
+    }
+    else
+    {
+        PMU->XTAL32K_CTRL &= ~PMU_XTAL32K_CTRL_X32K_EN_MASK;
+    }
+}
+
+/*! @brief  Enables and disables RTC 32KHz
+ *  @param  enable : true to enable 32k RTC clock, false to disable clock
+ */
+void CLOCK_EnableRtc32K(bool enable)
+{
+    if (enable)
+    {
+        CLKCTL0->CLK32KHZCTL0 |= CLKCTL0_CLK32KHZCTL0_ENA_32KHZ_MASK;
+    }
+    else
+    {
+        CLKCTL0->CLK32KHZCTL0 &= ~CLKCTL0_CLK32KHZCTL0_ENA_32KHZ_MASK;
+    }
+}
+
+static uint32_t CLOCK_CfgTcpuRefClk(uint32_t targetHz, clock_tcpu_flexspi_div_t div)
+{
+    uint32_t freq  = 0UL;
+    uint32_t steps = 0UL;
+
+    if (CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_40000KHZ)
+    {
+        /* Fbdiv from 75 to 96, step 40MHz */
+        freq = MAX(targetHz, CLOCK_MHZ(3000UL));
+        freq = MIN(freq, CLOCK_MHZ(3840UL));
+        /* Find the closest freq to target */
+        steps = (freq + CLOCK_MHZ(20UL) - CLOCK_MHZ(3000UL)) / CLOCK_MHZ(40UL);
+        freq  = CLOCK_MHZ(3000UL) + steps * CLOCK_MHZ(40UL);
+        /* Get step register value */
+        steps += 75UL;
+    }
+    else if (CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_38400KHZ)
+    {
+        /* Fbdiv from 78 to 100, step 38.4MHz */
+        freq = MAX(targetHz, CLOCK_KHZ(2995200UL));
+        freq = MIN(freq, CLOCK_MHZ(3840UL));
+        /* Find the closest freq to target */
+        steps = (freq + CLOCK_KHZ(19200UL) - CLOCK_KHZ(2995200UL)) / CLOCK_KHZ(38400UL);
+        freq  = CLOCK_KHZ(2995200UL) + steps * CLOCK_KHZ(38400UL);
+        /* Get step register value */
+        steps += 78UL;
+    }
+    else
+    {
+        assert(false);
+    }
+
+    SYSCTL2->PLL_CTRL =
+        (SYSCTL2->PLL_CTRL & ~(SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK | SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK)) |
+        SYSCTL2_PLL_CTRL_TCPU_FBDIV(steps) | SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL(div);
+
+    return freq;
+}
+
+/*! @brief  Initialize TCPU FVCO to target frequency.
+ *          For 40MHz XTAL, FVCO ranges from 3000MHz to 3840MHz.
+            For 38.4MHz XTAL, FVCO ranges from 2995.2MHz to 3840MHz
+ *  @param  targetHz  : Target FVCO frequency in Hz.
+ *  @param  div       : Divider for tcpu_mci_flexspi_clk.
+ *  @return Actual FVCO frequency in Hz.
+ */
+uint32_t CLOCK_InitTcpuRefClk(uint32_t targetHz, clock_tcpu_flexspi_div_t div)
+{
+    uint32_t freq;
+
+    if ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_PDB_MASK) != 0U)
+    {
+        CLOCK_DeinitTcpuRefClk();
+    }
+
+    SYSPLL_TCPU->TCPU_CTRL_ONE_REG = 0x74U;
+    freq                           = CLOCK_CfgTcpuRefClk(targetHz, div);
+
+    /* Set PDB */
+    SYSCTL2->PLL_CTRL |= SYSCTL2_PLL_CTRL_TCPU_PDB_MASK;
+    /* Wait PLL lock */
+    while ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_LOCK_MASK) == 0U)
+    {
+    }
+
+    return freq;
+}
+
+/*! brief  Deinit the TCPU reference clock.
+ *  param  none.
+ */
+void CLOCK_DeinitTcpuRefClk(void)
+{
+    /* Gate all TCPU output clocks */
+    SYSCTL2->SOURCE_CLK_GATE |=
+        SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_MASK | SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_MASK;
+    /* Clear PDB */
+    SYSCTL2->PLL_CTRL &= ~SYSCTL2_PLL_CTRL_TCPU_PDB_MASK;
+    /* Wait PLL lock */
+    /* Ensure SystemCoreClock is up to date for accurate CLOCK_DelayUs() */
+    SystemCoreClockUpdate();
+    CLOCK_DelayUs(1U);
+
+    CLOCK_DisableClock(kCLOCK_RefClkTcpu);
+}
+
+/*! @brief  Initialize the TDDR reference clock.
+ *  @param  div       : Divider for tddr_mci_flexspi_clk.
+ */
+void CLOCK_InitTddrRefClk(clock_tddr_flexspi_div_t div)
+{
+    if ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TDDR_PDB_MASK) != 0U)
+    {
+        CLOCK_DeinitTddrRefClk();
+    }
+
+    REG_SYSPLL_TDDR->TDDR_CTRL_ONE_REG = 0x74U;
+    SYSCTL2->PLL_CTRL =
+        (SYSCTL2->PLL_CTRL & ~SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK) | SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL(div);
+
+    /* Set PDB */
+    SYSCTL2->PLL_CTRL |= SYSCTL2_PLL_CTRL_TDDR_PDB_MASK;
+    /* Wait PLL lock */
+    while ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TDDR_LOCK_MASK) == 0U)
+    {
+    }
+}
+
+/*! brief  Deinit the TDDR reference clock.
+ *  param  none.
+ */
+void CLOCK_DeinitTddrRefClk(void)
+{
+    /* Gate all TDDR output clocks */
+    SYSCTL2->SOURCE_CLK_GATE |=
+        SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_MASK | SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_MASK;
+    /* Clear PDB */
+    SYSCTL2->PLL_CTRL &= ~SYSCTL2_PLL_CTRL_TDDR_PDB_MASK;
+    /* Wait PLL lock */
+    /* Ensure SystemCoreClock is up to date for accurate CLOCK_DelayUs() */
+    SystemCoreClockUpdate();
+    CLOCK_DelayUs(1U);
+
+    CLOCK_DisableClock(kCLOCK_RefClkTddr);
+}
+
+/*! @brief  Initialize the T3 reference clock.
+ *  @param  cnfg       : t3pll_mci_48_60m_irc clock configuration
+ */
+void CLOCK_InitT3RefClk(clock_t3_mci_irc_config_t cnfg)
+{
+    if ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_T3_PDB_MASK) != 0U)
+    {
+        CLOCK_DeinitT3RefClk();
+    }
+
+    if (cnfg == kCLOCK_T3MciIrc60m)
+    {
+        SYSPLL_T3->CLKTREE_CTRL_SIX_REG = 0x5U;
+    }
+    else
+    {
+        SYSPLL_T3->CLKTREE_CTRL_SIX_REG = 0xAU;
+    }
+    /* Set PDB */
+    SYSCTL2->PLL_CTRL |= SYSCTL2_PLL_CTRL_T3_PDB_MASK;
+    /* Wait PLL lock */
+    while ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_T3_LOCK_MASK) == 0U)
+    {
+    }
+}
+
+/*! brief  Deinit the T3 reference clock.
+ *  param  none.
+ */
+void CLOCK_DeinitT3RefClk(void)
+{
+    /* Ensure SystemCoreClock is up to date for accurate CLOCK_DelayUs() */
+    SystemCoreClockUpdate();
+    /* Gate all T3 output clocks */
+    SYSCTL2->SOURCE_CLK_GATE |=
+        SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_MASK | SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_MASK |
+        SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_MASK | SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_MASK;
+    /* Clear PDB */
+    SYSCTL2->PLL_CTRL &= ~SYSCTL2_PLL_CTRL_T3_PDB_MASK;
+
+    /* Wait PLL lock */
+    CLOCK_DelayUs(1U);
+}
+
+static void CLOCK_ConfigAvPll(void)
+{
+    uint32_t fbdiv          = 0x51U;
+    uint32_t freq_offset_c8 = 0x0U;
+    uint32_t pll_calclk_div = 0x14U;
+    uint32_t refdiv         = 0x2U;
+    uint32_t ext_speed      = 0x2U;
+    uint32_t intpi          = 0x3U;
+    uint32_t intpr          = 0x4U;
+    uint32_t icp            = 0x5U;
+
+    if (CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_38400KHZ)
+    {
+        fbdiv          = 0x54U;
+        freq_offset_c8 = 0x4924U;
+        pll_calclk_div = 0x13U;
+    }
+
+    SYSCTL2->AVPLL_CTRL2 =
+        (SYSCTL2->AVPLL_CTRL2 & ~(SYSCTL2_AVPLL_CTRL2_ICP_MASK | SYSCTL2_AVPLL_CTRL2_INTPI_MASK |
+                                  SYSCTL2_AVPLL_CTRL2_INTPR_MASK | SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_MASK)) |
+        SYSCTL2_AVPLL_CTRL2_ICP(icp) | SYSCTL2_AVPLL_CTRL2_INTPI(intpi) | SYSCTL2_AVPLL_CTRL2_INTPR(intpr) |
+        SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV(pll_calclk_div);
+
+    SYSCTL2->AVPLL_CTRL3 =
+        (SYSCTL2->AVPLL_CTRL3 & ~SYSCTL2_AVPLL_CTRL3_REFDIV_MASK) | SYSCTL2_AVPLL_CTRL3_REFDIV(refdiv);
+
+    SYSCTL2->AVPLL_CTRL0 =
+        (SYSCTL2->AVPLL_CTRL0 & ~SYSCTL2_AVPLL_CTRL0_EXT_SPEED_MASK) | SYSCTL2_AVPLL_CTRL0_EXT_SPEED(ext_speed);
+
+    SYSCTL2->AVPLL_CTRL1 = (SYSCTL2->AVPLL_CTRL1 & ~SYSCTL2_AVPLL_CTRL1_FBDIV_MASK) | SYSCTL2_AVPLL_CTRL1_FBDIV(fbdiv);
+
+    SYSCTL2->AVPLL_CTRL8 =
+        (SYSCTL2->AVPLL_CTRL8 & ~(SYSCTL2_AVPLL_CTRL8_EN_LP_C8_MASK | SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_MASK)) |
+        SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8(freq_offset_c8);
+}
+
+static void CLOCK_ConfigAvPllCh1(clock_avpll_ch_freq_t ch1Freq)
+{
+    if (ch1Freq != kCLOCK_AvPllChUnchanged)
+    {
+        SYSCTL2->AVPLL_CTRL2 = (SYSCTL2->AVPLL_CTRL2 & ~SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_MASK) |
+                               SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1(s_avpllPostDiv0p5[(uint32_t)ch1Freq]);
+
+        SYSCTL2->AVPLL_CTRL1 = (SYSCTL2->AVPLL_CTRL1 & ~SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_MASK) |
+                               SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1(s_avpllFreqOff[(uint32_t)ch1Freq]);
+
+        SYSCTL2->AVPLL_CTRL5 = (SYSCTL2->AVPLL_CTRL5 & ~SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_MASK) |
+                               SYSCTL2_AVPLL_CTRL5_POSTDIV_C1(s_avpllPostDiv[(uint32_t)ch1Freq]);
+    }
+}
+
+static void CLOCK_ConfigAvPllCh2(clock_avpll_ch_freq_t ch2Freq)
+{
+    if (ch2Freq != kCLOCK_AvPllChUnchanged)
+    {
+        SYSCTL2->AVPLL_CTRL12 = (SYSCTL2->AVPLL_CTRL12 & ~SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_MASK) |
+                                SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2(s_avpllPostDiv0p5[(uint32_t)ch2Freq]);
+
+        SYSCTL2->AVPLL_CTRL11 = SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2(s_avpllFreqOff[(uint32_t)ch2Freq]) |
+                                SYSCTL2_AVPLL_CTRL11_POSTDIV_C2(s_avpllPostDiv[(uint32_t)ch2Freq]);
+    }
+}
+
+static void CLOCK_PowerUpAnaGrp(void)
+{
+    uint32_t anaGrpPu = SYSCTL2->ANA_GRP_CTRL;
+
+    if ((anaGrpPu & SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK) == 0U)
+    {
+        SYSCTL2->ANA_GRP_CTRL = anaGrpPu | SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK;
+        CLOCK_DelayUs(50U); /* Delay 50us */
+    }
+}
+
+static void CLOCK_PowerDownAnaGrp(void)
+{
+    uint32_t anaGrpPu = SYSCTL2->ANA_GRP_CTRL;
+
+    if ((anaGrpPu & SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK) != 0U)
+    {
+        SYSCTL2->ANA_GRP_CTRL = anaGrpPu & ~SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK;
+    }
+}
+
+/*! @brief  Initialize the AVPLL.
+ *  @param  enableCh1  : Enable AVPLL channel1
+ *  @param  enableCh2  : Enable AVPLL channel2
+ *  @param  enableCali : Enable AVPLL calibration
+ */
+void CLOCK_EnableAvPllCh(bool enableCh1, bool enableCh2, bool enableCali)
+{
+    uint32_t calDoneDelay;
+
+    /* Step 3: Pull up PU_C1 PU_C2 */
+    if (enableCh1)
+    {
+        SYSCTL2->AVPLL_CTRL2 |= SYSCTL2_AVPLL_CTRL2_PU_C1_MASK;
+    }
+    if (enableCh2)
+    {
+        SYSCTL2->AVPLL_CTRL12 |= SYSCTL2_AVPLL_CTRL12_PU_C2_MASK;
+    }
+
+    /* Pull up freq_offset_c8_ready */
+    SYSCTL2->AVPLL_CTRL8 |= SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_MASK;
+    CLOCK_DelayUs(3U); /* Delay 516*FVCO*4, about 3us */
+
+    /* Step 4: Pull low freq_offset_c8_ready */
+    SYSCTL2->AVPLL_CTRL8 &= ~SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_MASK;
+    CLOCK_DelayUs(2U); /* Delay more than 1us, recommended to delay 2us */
+
+    /* Step 5: Pull low RESET_C8 */
+    SYSCTL2->AVPLL_CTRL8 &= ~SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_MASK;
+    CLOCK_DelayUs(5U); /* Delay 5us. */
+
+    if (enableCali)
+    {
+        /* Step 6: Cali start */
+        SYSCTL2->AVPLL_CTRL2 |= SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_MASK;
+    }
+    CLOCK_DelayUs(5U); /* Delay 5us */
+
+    /* Step 7: Pull low RESET_C1 RESET_C2 */
+    if (enableCh1)
+    {
+        SYSCTL2->AVPLL_CTRL8 &= ~SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_MASK;
+    }
+    if (enableCh2)
+    {
+        SYSCTL2->AVPLL_CTRL13 &= ~SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_MASK;
+    }
+    CLOCK_DelayUs(2U); /* Delay 516*FVCO , about 2us */
+
+    /* Step 8: Pull high freq_offset_ready_c1/c2 */
+    if (enableCh1)
+    {
+        SYSCTL2->AVPLL_CTRL1 |= SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_MASK;
+    }
+    if (enableCh2)
+    {
+        SYSCTL2->AVPLL_CTRL12 |= SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_MASK;
+    }
+    CLOCK_DelayUs(2U); /* Delay 516*FVCO , about 2us */
+
+    /* Step 9: pull low freq_offset_ready_c1/2 */
+    if (enableCh1)
+    {
+        SYSCTL2->AVPLL_CTRL1 &= ~SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_MASK;
+    }
+    if (enableCh2)
+    {
+        SYSCTL2->AVPLL_CTRL12 &= ~SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_MASK;
+    }
+    CLOCK_DelayUs(12U); /* Delay more than 10us, recommended 12 us */
+
+    if (enableCali)
+    {
+        /* Step 10: wait cali done */
+        calDoneDelay = 0U;
+        while (
+            ((SYSCTL2->AVPLL_CTRL7 & SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_MASK) != SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_MASK) &&
+            (calDoneDelay < 600U)) /* Wait cali done or 600us */
+        {
+            calDoneDelay += 10U;
+            CLOCK_DelayUs(10U);
+        }
+        CLOCK_DelayUs(10U);
+
+        /* Step 11: clear cali start */
+        SYSCTL2->AVPLL_CTRL2 &= ~SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_MASK;
+    }
+}
+
+/*! @brief  Disable the AVPLL.
+ *  @param  disableCh1  : Disable AVPLL channel1, channel unchanged on false.
+ *  @param  disableCh2  : Disable AVPLL channel2, channel unchanged on false.
+ */
+void CLOCK_DisableAvPllCh(bool disableCh1, bool disableCh2)
+{
+    if (disableCh1)
+    {
+        /* Pull up RESET_C1 */
+        SYSCTL2->AVPLL_CTRL8 |= SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_MASK;
+        /* Pull low PU_C1 */
+        SYSCTL2->AVPLL_CTRL2 &= ~SYSCTL2_AVPLL_CTRL2_PU_C1_MASK;
+    }
+
+    if (disableCh2)
+    {
+        /* Pull up RESET_C2 */
+        SYSCTL2->AVPLL_CTRL13 |= SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_MASK;
+        /* Pull low PU_C2 */
+        SYSCTL2->AVPLL_CTRL12 &= ~SYSCTL2_AVPLL_CTRL12_PU_C2_MASK;
+    }
+}
+
+/*! @brief  Initialize the AVPLL.
+ *  @param  cnfg       : AVPLL clock configuration
+ */
+void CLOCK_InitAvPll(const clock_avpll_config_t *cnfg)
+{
+    assert(cnfg);
+
+    if ((SYSCTL2->AVPLL_CTRL2 & SYSCTL2_AVPLL_CTRL2_PU_MASK) != 0U)
+    {
+        /* Pull down AVPLL power for initialization. */
+        CLOCK_DeinitAvPll();
+    }
+
+    /* Ensure SystemCoreClock is up to date for accurate CLOCK_DelayUs() */
+    SystemCoreClockUpdate();
+
+    /* Ensure ANA_GRP is powered up */
+    CLOCK_PowerUpAnaGrp();
+
+    /* Configure CH1/CH2 frequency */
+    CLOCK_ConfigAvPll();
+    CLOCK_ConfigAvPllCh1(cnfg->ch1Freq);
+    CLOCK_ConfigAvPllCh2(cnfg->ch2Freq);
+
+    /* Step 1: Pull up PU */
+    SYSCTL2->AVPLL_CTRL2 |= SYSCTL2_AVPLL_CTRL2_PU_MASK;
+    CLOCK_DelayUs(15U); /* Wait more than 10us, recommended to delay 15us */
+
+    /* Step 2: Pull low RESET */
+    SYSCTL2->AVPLL_CTRL8 &= ~SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_MASK;
+    CLOCK_DelayUs(15U); /* Wait more than 10us, recommended to delay 15us */
+
+    /* Enable channels */
+    CLOCK_EnableAvPllCh(true, true, cnfg->enableCali);
+}
+
+/*! @brief  Deinit the AVPLL.
+ */
+void CLOCK_DeinitAvPll(void)
+{
+    CLOCK_DisableAvPllCh(true, true);
+
+    /* Pull up RESET */
+    SYSCTL2->AVPLL_CTRL8 |= SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_MASK;
+    /* Pull up RESET_C8 */
+    SYSCTL2->AVPLL_CTRL8 |= SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_MASK;
+    /* Pull low PU */
+    SYSCTL2->AVPLL_CTRL2 &= ~SYSCTL2_AVPLL_CTRL2_PU_MASK;
+
+    /* Disable REFCLK AUD. */
+    CLOCK_DisableClock(kCLOCK_RefClkAud);
+
+    if ((SYSCTL2->USB_CTRL & SYSCTL2_USB_CTRL_USB_PU_MASK) == 0U)
+    {
+        /* USB also not used, ANA_GRP can be powered down. */
+        CLOCK_PowerDownAnaGrp();
+    }
+}
+
+/*! @brief  Update the AVPLL channel configuration. Enable/Disable state keeps unchanged.
+ *  @param  ch1Freq  : Channel 1 frequency to set.
+ *  @param  ch2Freq  : Channel 2 frequency to set.
+ *  @param  enableCali : Enable AVPLL calibration.
+ */
+void CLOCK_ConfigAvPllCh(clock_avpll_ch_freq_t ch1Freq, clock_avpll_ch_freq_t ch2Freq, bool enableCali)
+{
+    bool needRenableCh1, needRenableCh2;
+
+    if ((ch1Freq == kCLOCK_AvPllChUnchanged) && (ch2Freq == kCLOCK_AvPllChUnchanged))
+    {
+        /* Nothing to change. */
+        return;
+    }
+
+    /* If channel enabled and need to update configuration, need to reenable. */
+    needRenableCh1 =
+        ((SYSCTL2->AVPLL_CTRL2 & SYSCTL2_AVPLL_CTRL2_PU_C1_MASK) != 0U) && (ch1Freq != kCLOCK_AvPllChUnchanged);
+    needRenableCh2 =
+        ((SYSCTL2->AVPLL_CTRL12 & SYSCTL2_AVPLL_CTRL12_PU_C2_MASK) != 0U) && (ch2Freq != kCLOCK_AvPllChUnchanged);
+
+    /* Disable channel before update configuration. */
+    CLOCK_DisableAvPllCh(needRenableCh1, needRenableCh2);
+
+    CLOCK_ConfigAvPll();
+
+    if (ch1Freq != kCLOCK_AvPllChUnchanged)
+    {
+        CLOCK_ConfigAvPllCh1(ch1Freq);
+    }
+    if (ch2Freq != kCLOCK_AvPllChUnchanged)
+    {
+        CLOCK_ConfigAvPllCh2(ch2Freq);
+    }
+
+    /* Reenable channel if needed. */
+    CLOCK_EnableAvPllCh(needRenableCh1, needRenableCh2, enableCali);
+}
+
+/*! @brief Enable USB HS PHY PLL clock.
+ *
+ * This function enables USB HS PHY PLL clock.
+ */
+void CLOCK_EnableUsbhsPhyClock(void)
+{
+    uint32_t value;
+    value          = SYSCTL2->USB_CTRL;
+    uint32_t delay = 100000;
+
+    /* Ensure SystemCoreClock is up to date for accurate CLOCK_DelayUs() */
+    SystemCoreClockUpdate();
+
+    /* Ensure ANA_GRP is powered on */
+    SYSCTL2->ANA_GRP_CTRL |= SYSCTL2_ANA_GRP_CTRL_PU_XTL_MASK;
+    CLOCK_PowerUpAnaGrp();
+
+    /* Reset USB PHY */
+    value |=
+        SYSCTL2_USB_CTRL_SOFT_PHY_RESET_MASK | SYSCTL2_USB_CTRL_PHY_RESET_SEL_MASK; /* Use soft reset to reset PHY */
+    SYSCTL2->USB_CTRL =
+        value & ~(SYSCTL2_USB_CTRL_USB_PU_PLL_MASK | SYSCTL2_USB_CTRL_USB_PU_MASK | SYSCTL2_USB_CTRL_USB_PU_OTG_MASK);
+    __NOP();
+    value &= ~(SYSCTL2_USB_CTRL_SOFT_PHY_RESET_MASK |
+               SYSCTL2_USB_CTRL_PHY_RESET_SEL_MASK); /* It is an active high reset; this bit is inverted */
+    SYSCTL2->USB_CTRL = value;
+    /* Power up PHY OTG detection circuit */
+    USBOTG->PHY_REG_OTG_CONTROL |= USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_MASK;
+    /* Analog power up through pin */
+    value |= SYSCTL2_USB_CTRL_USB_PU_MASK | SYSCTL2_USB_CTRL_USB_PU_OTG_MASK;
+    SYSCTL2->USB_CTRL = value;
+    /* Power up PLL via pin; raising edge will auto trigger calibration */
+    value |= SYSCTL2_USB_CTRL_USB_PU_PLL_MASK;
+    SYSCTL2->USB_CTRL = value;
+    while ((delay-- > 0U) && ((USBOTG->PLL_CONTROL_0 & USBC_PLL_CONTROL_0_PLL_READY_MASK) == 0U))
+    {
+    }
+}
+
+/*! @brief Disable USB HS PHY PLL clock.
+ *
+ * This function disables USB HS PHY PLL clock.
+ */
+void CLOCK_DisableUsbhsPhyClock(void)
+{
+    uint32_t value;
+    value = SYSCTL2->USB_CTRL;
+    /* Power down PHY OTG detection circuit */
+    USBOTG->PHY_REG_OTG_CONTROL |= USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_MASK;
+    /* Analog power down through pin */
+    value &= ~SYSCTL2_USB_CTRL_USB_PU_MASK & ~SYSCTL2_USB_CTRL_USB_PU_OTG_MASK;
+    SYSCTL2->USB_CTRL = value;
+    /* Power down PLL via pin */
+    value &= ~SYSCTL2_USB_CTRL_USB_PU_PLL_MASK;
+    SYSCTL2->USB_CTRL = value;
+    if ((SYSCTL2->AVPLL_CTRL2 & SYSCTL2_AVPLL_CTRL2_PU_MASK) == 0U)
+    {
+        /* AVPLL also not used, ANA_GRP can be powered down. */
+        CLOCK_PowerDownAnaGrp();
+    }
+    SYSCTL2->ANA_GRP_CTRL &= ~SYSCTL2_ANA_GRP_CTRL_PU_XTL_MASK;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_clock.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_clock.h
new file mode 100644
index 0000000000..a32eb9fb78
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_clock.h
@@ -0,0 +1,953 @@
+/*
+ * Copyright 2020-2024, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could control the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.3.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
+/*@}*/
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (260000000UL)
+#endif
+
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS                    \
+    {                                  \
+        kCLOCK_HsGpio0, kCLOCK_HsGpio1 \
+    }
+
+/*! @brief Clock ip name array for CACHE64. */
+#define CACHE64_CLOCKS                 \
+    {                                  \
+        kCLOCK_Flexspi, kCLOCK_Flexspi \
+    }
+
+/*! @brief Clock ip name array for FLEXSPI. */
+#define FLEXSPI_CLOCKS \
+    {                  \
+        kCLOCK_Flexspi \
+    }
+
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS                                                                           \
+    {                                                                                             \
+        kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm14 \
+    }
+
+/*! @brief Clock ip name array for LPUART. */
+#define USART_CLOCKS                                                           \
+    {                                                                          \
+        kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
+    }
+
+/*! @brief Clock ip name array for I2C. */
+#define I2C_CLOCKS                                                             \
+    {                                                                          \
+        kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
+    }
+
+/*! @brief Clock ip name array for SPI. */
+#define SPI_CLOCKS                                                                                \
+    {                                                                                             \
+        kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm14 \
+    }
+
+/*! @brief Clock ip name array for ACOMP. */
+#define ACOMP_CLOCKS \
+    {                \
+        kCLOCK_Gau   \
+    }
+
+/*! @brief Clock ip name array for ADC. */
+#define ADC_CLOCKS             \
+    {                          \
+        kCLOCK_Gau, kCLOCK_Gau \
+    }
+
+/*! @brief Clock ip name array for DAC. */
+#define DAC_CLOCKS \
+    {              \
+        kCLOCK_Gau \
+    }
+
+/*! @brief Clock ip name array for LCDIC. */
+#define LCDIC_CLOCKS \
+    {                \
+        kCLOCK_Lcdic \
+    }
+
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS               \
+    {                            \
+        kCLOCK_Dma0, kCLOCK_Dma1 \
+    }
+
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS  \
+    {                \
+        kCLOCK_Dmic0 \
+    }
+
+/*! @brief Clock ip name array for ENET. */
+#define ENET_CLOCKS    \
+    {                  \
+        kCLOCK_EnetIpg \
+    }
+
+/*! @brief Extra clock ip name array for ENET. */
+#define ENET_EXTRA_CLOCKS \
+    {                     \
+        kCLOCK_EnetIpgS   \
+    }
+
+/*! @brief Clock ip name array for Powerquad */
+#define POWERQUAD_CLOCKS \
+    {                    \
+        kCLOCK_PowerQuad \
+    }
+
+/*! @brief Clock ip name array for OSTimer */
+#define OSTIMER_CLOCKS      \
+    {                       \
+        kCLOCK_OsEventTimer \
+    }
+
+/*! @brief Clock ip name array for CT32B. */
+#define CTIMER_CLOCKS                                                             \
+    {                                                                             \
+        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
+    }
+
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS \
+    {                \
+        kCLOCK_Utick \
+    }
+
+/*! @brief Clock ip name array for MRT. */
+#define MRT_CLOCKS                 \
+    {                              \
+        kCLOCK_Mrt, kCLOCK_FreeMrt \
+    }
+
+/*! @brief Clock ip name array for SCT. */
+#define SCT_CLOCKS \
+    {              \
+        kCLOCK_Sct \
+    }
+
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS \
+    {              \
+        kCLOCK_Rtc \
+    }
+
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS  \
+    {                \
+        kCLOCK_Wwdt0 \
+    }
+
+/*! @brief Clock ip name array for TRNG. */
+#define TRNG_CLOCKS \
+    {               \
+        kCLOCK_Trng \
+    }
+
+/*! @brief Clock ip name array for USIM. */
+#define USIM_CLOCKS \
+    {               \
+        kCLOCK_Usim \
+    }
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK  0xFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT  0U
+#define CLK_GATE_BIT_SHIFT_MASK   0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
+    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define CLK_CTL0_PSCCTL0 0
+#define CLK_CTL0_PSCCTL1 1
+#define CLK_CTL0_PSCCTL2 2
+#define CLK_CTL1_PSCCTL0 3
+#define CLK_CTL1_PSCCTL1 4
+#define CLK_CTL1_PSCCTL2 5
+
+#define SYS_CLK_GATE_FLAG_MASK         (0x10000UL)
+#define SYS_CLK_GATE_DEFINE(bit_shift) (((bit_shift)&CLK_GATE_BIT_SHIFT_MASK) | SYS_CLK_GATE_FLAG_MASK)
+#define SYS_CLK_GATE_BIT_MASK(x)       (1UL << (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT))
+
+#define CLKCTL0_TUPLE_MUXA(reg, choice) (((reg)&0xFFCU) | ((choice) << 12U))
+#define CLKCTL0_TUPLE_MUXB(reg, choice) ((((reg)&0xFFCU) << 16) | ((choice) << 28U))
+#define CLKCTL1_TUPLE_FLAG_MASK         (0x8000U)
+#define CLKCTL1_TUPLE_MUXA(reg, choice) (((reg)&0xFFCU) | CLKCTL1_TUPLE_FLAG_MASK | ((choice) << 12U))
+#define CLKCTL1_TUPLE_MUXB(reg, choice) ((((reg)&0xFFCU) | CLKCTL1_TUPLE_FLAG_MASK | ((choice) << 28U)) << 16)
+#define CLKCTL_TUPLE_REG(base, tuple)   ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFCU)))
+#define CLKCTL_TUPLE_SEL(tuple)         (((uint32_t)(tuple) >> 12U) & 0x7U)
+
+#define CLKOUT_TUPLE_MUX_AVAIL          (0x2U)
+#define CLKOUT_TUPLE_MUX(ch0, ch1, ch2) (CLKOUT_TUPLE_MUX_AVAIL | ((ch0) << 4U) | ((ch1) << 8) | ((ch2) << 12))
+
+#define PMU_TUPLE_MUX_AVAIL        (0x1U)
+#define PMU_TUPLE_MUX(reg, choice) (((reg)&0xFFCU) | ((choice) << 12U) | PMU_TUPLE_MUX_AVAIL)
+#define PMU_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFCU)))
+#define PMU_TUPLE_SEL(tuple)       (((uint32_t)(tuple) >> 12U) & 0x3U)
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+    kCLOCK_CoreSysClk,       /*!< Core clock  (aka HCLK)                                 */
+    kCLOCK_BusClk,           /*!< Bus clock (AHB/APB clock, aka HCLK)                    */
+    kCLOCK_MclkClk,          /*!< MCLK, to MCLK pin                                      */
+} clock_name_t;
+
+/*!
+ * @brief Peripheral clock name difinition used for
+ * clock gate.
+ */
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid = 0U,
+
+    kCLOCK_TcpuMciClk         = SYS_CLK_GATE_DEFINE(0),
+    kCLOCK_TcpuMciFlexspiClk  = SYS_CLK_GATE_DEFINE(1),
+    kCLOCK_TddrMciEnetClk     = SYS_CLK_GATE_DEFINE(2),
+    kCLOCK_TddrMciFlexspiClk  = SYS_CLK_GATE_DEFINE(3),
+    kCLOCK_T3PllMciIrcClk     = SYS_CLK_GATE_DEFINE(4),
+    kCLOCK_T3PllMci256mClk    = SYS_CLK_GATE_DEFINE(5),
+    kCLOCK_T3PllMci213mClk    = SYS_CLK_GATE_DEFINE(6),
+    kCLOCK_T3PllMciFlexspiClk = SYS_CLK_GATE_DEFINE(7),
+    kCLOCK_RefClkSys          = SYS_CLK_GATE_DEFINE(9),
+    kCLOCK_RefClkTcpu         = SYS_CLK_GATE_DEFINE(28),
+    kCLOCK_RefClkTddr         = SYS_CLK_GATE_DEFINE(29),
+    kCLOCK_RefClkAud          = SYS_CLK_GATE_DEFINE(30),
+    kCLOCK_RefClkUsb          = SYS_CLK_GATE_DEFINE(31),
+    kCLOCK_RefClkCauSlp       = SYS_CLK_GATE_DEFINE(32),
+
+    kCLOCK_Cpu       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 0),
+    kCLOCK_Matrix    = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1),
+    kCLOCK_Romcp     = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
+    kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
+    kCLOCK_Pkc       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
+    kCLOCK_Els       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
+    kCLOCK_Puf       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
+    kCLOCK_Flexspi   = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
+    kCLOCK_Hpu       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
+    kCLOCK_Usb       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22),
+    kCLOCK_Sct       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24),
+    kCLOCK_AonMem    = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 25),
+    kCLOCK_Gdma      = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 28),
+    kCLOCK_Dma0      = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 29),
+    kCLOCK_Dma1      = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 30),
+    kCLOCK_Sdio      = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 31),
+
+    kCLOCK_ElsApb     = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 0),
+    kCLOCK_SdioSlv    = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2),
+    kCLOCK_Gau        = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16),
+    kCLOCK_Otp        = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 17),
+    kCLOCK_SecureGpio = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24),
+    kCLOCK_EnetIpg    = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 25),
+    kCLOCK_EnetIpgS   = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 26),
+    kCLOCK_Trng       = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 27),
+
+    kCLOCK_Utick   = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
+    kCLOCK_Wwdt0   = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
+    kCLOCK_Usim    = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2),
+    kCLOCK_Itrc    = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3),
+    kCLOCK_FreeMrt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 26),
+    kCLOCK_Lcdic   = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 27),
+
+    kCLOCK_Flexcomm0    = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
+    kCLOCK_Flexcomm1    = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
+    kCLOCK_Flexcomm2    = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
+    kCLOCK_Flexcomm3    = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
+    kCLOCK_Flexcomm14   = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
+    kCLOCK_Dmic0        = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
+    kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
+
+    kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
+    kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
+    kCLOCK_Crc     = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
+    kCLOCK_Freqme  = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
+
+    kCLOCK_Ct32b0   = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
+    kCLOCK_Ct32b1   = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
+    kCLOCK_Ct32b2   = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
+    kCLOCK_Ct32b3   = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
+    kCLOCK_Ct32b4   = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
+    kCLOCK_Pmu      = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 6),
+    kCLOCK_Rtc      = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
+    kCLOCK_Mrt      = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
+    kCLOCK_Pint     = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
+    kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31),
+} clock_ip_name_t;
+
+/*!
+ * @brief Peripheral clock source selection definition.
+ */
+typedef enum _clock_attach_id
+{
+    kXTAL_to_SYSOSC_CLK  = CLKCTL0_TUPLE_MUXA(0x168U, 0),
+    kCLKIN_to_SYSOSC_CLK = CLKCTL0_TUPLE_MUXA(0x168U, 1),
+    kNONE_to_SYSOSC_CLK  = CLKCTL0_TUPLE_MUXA(0x168U, 7),
+
+    kSYSOSC_to_MAIN_CLK    = CLKCTL0_TUPLE_MUXA(0x430U, 0) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
+    kFFRO_DIV4_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 1) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
+    kLPOSC_to_MAIN_CLK     = CLKCTL0_TUPLE_MUXA(0x430U, 2) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
+    kFFRO_to_MAIN_CLK      = CLKCTL0_TUPLE_MUXA(0x430U, 3) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
+    kSFRO_to_MAIN_CLK      = CLKCTL0_TUPLE_MUXA(0x434U, 1),
+    kMAIN_PLL_to_MAIN_CLK  = CLKCTL0_TUPLE_MUXA(0x434U, 2),
+    kCLK32K_to_MAIN_CLK    = CLKCTL0_TUPLE_MUXA(0x434U, 3),
+
+    kMAIN_CLK_to_FLEXSPI_CLK          = CLKCTL0_TUPLE_MUXA(0x620U, 0),
+    kT3PLL_MCI_FLEXSPI_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 1),
+    kAUX0_PLL_to_FLEXSPI_CLK          = CLKCTL0_TUPLE_MUXA(0x620U, 2),
+    kTCPU_MCI_FLEXSPI_to_FLEXSPI_CLK  = CLKCTL0_TUPLE_MUXA(0x620U, 3),
+    kAUX1_PLL_to_FLEXSPI_CLK          = CLKCTL0_TUPLE_MUXA(0x620U, 4),
+    kTDDR_MCI_FLEXSPI_to_FLEXSPI_CLK  = CLKCTL0_TUPLE_MUXA(0x620U, 5),
+    kT3PLL_MCI_256M_to_FLEXSPI_CLK    = CLKCTL0_TUPLE_MUXA(0x620U, 6),
+    kNONE_to_FLEXSPI_CLK              = CLKCTL0_TUPLE_MUXA(0x620U, 7),
+
+    kMAIN_CLK_to_SCT_CLK  = CLKCTL0_TUPLE_MUXA(0x640U, 0),
+    kMAIN_PLL_to_SCT_CLK  = CLKCTL0_TUPLE_MUXA(0x640U, 1),
+    kAUX0_PLL_to_SCT_CLK  = CLKCTL0_TUPLE_MUXA(0x640U, 2),
+    kFFRO_to_SCT_CLK      = CLKCTL0_TUPLE_MUXA(0x640U, 3),
+    kAUX1_PLL_to_SCT_CLK  = CLKCTL0_TUPLE_MUXA(0x640U, 4),
+    kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 5),
+    kNONE_to_SCT_CLK      = CLKCTL0_TUPLE_MUXA(0x640U, 7),
+
+    kLPOSC_to_UTICK_CLK    = CLKCTL0_TUPLE_MUXA(0x700U, 0),
+    kMAIN_CLK_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(0x700U, 1),
+    kNONE_to_UTICK_CLK     = CLKCTL0_TUPLE_MUXA(0x700U, 3),
+
+    kLPOSC_to_WDT0_CLK    = CLKCTL0_TUPLE_MUXA(0x720U, 0),
+    kMAIN_CLK_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(0x720U, 1),
+    kNONE_to_WDT0_CLK     = CLKCTL0_TUPLE_MUXA(0x720U, 3),
+
+    kSYSTICK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 0),
+    kLPOSC_to_SYSTICK_CLK       = CLKCTL0_TUPLE_MUXA(0x760U, 1),
+    kCLK32K_to_SYSTICK_CLK      = CLKCTL0_TUPLE_MUXA(0x760U, 2),
+    kSFRO_to_SYSTICK_CLK        = CLKCTL0_TUPLE_MUXA(0x760U, 3),
+    kNONE_to_SYSTICK_CLK        = CLKCTL0_TUPLE_MUXA(0x760U, 7),
+
+    kMAIN_CLK_to_USIM_CLK  = CLKCTL0_TUPLE_MUXA(0x774U, 0),
+    kAUDIO_PLL_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 1),
+    kFFRO_to_USIM_CLK      = CLKCTL0_TUPLE_MUXA(0x774U, 2),
+    kNONE_to_USIM_CLK      = CLKCTL0_TUPLE_MUXA(0x774U, 3),
+
+    kMAIN_CLK_to_LCD_CLK          = CLKCTL0_TUPLE_MUXA(0x778U, 0),
+    kT3PLL_MCI_FLEXSPI_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 1),
+    kTCPU_MCI_FLEXSPI_to_LCD_CLK  = CLKCTL0_TUPLE_MUXA(0x778U, 2),
+    kTDDR_MCI_FLEXSPI_to_LCD_CLK  = CLKCTL0_TUPLE_MUXA(0x778U, 3),
+    kNONE_to_LCD_CLK              = CLKCTL0_TUPLE_MUXA(0x778U, 7),
+
+    kMAIN_CLK_to_GAU_CLK       = CLKCTL0_TUPLE_MUXA(0x77CU, 0),
+    kT3PLL_MCI_256M_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 1),
+    kAVPLL_CH2_to_GAU_CLK      = CLKCTL0_TUPLE_MUXA(0x77CU, 2),
+    kNONE_to_GAU_CLK           = CLKCTL0_TUPLE_MUXA(0x77CU, 3),
+
+    kT3PLL_MCI_256M_to_ELS_GDET = CLKCTL0_TUPLE_MUXA(0x7A8U, 0),
+    kELS_128M_to_ELS_GDET       = CLKCTL0_TUPLE_MUXA(0x7A8U, 1),
+    kELS_64M_to_ELS_GDET        = CLKCTL0_TUPLE_MUXA(0x7A8U, 2),
+    kOTP_FUSE_32M_to_ELS_GDET   = CLKCTL0_TUPLE_MUXA(0x7A8U, 3),
+    kNONE_to_ELS_GDET           = CLKCTL0_TUPLE_MUXA(0x7A8U, 7),
+
+    kLPOSC_to_OSTIMER_CLK    = CLKCTL1_TUPLE_MUXA(0x480U, 0),
+    kCLK32K_to_OSTIMER_CLK   = CLKCTL1_TUPLE_MUXA(0x480U, 1),
+    kHCLK_to_OSTIMER_CLK     = CLKCTL1_TUPLE_MUXA(0x480U, 2),
+    kMAIN_CLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 3),
+    kNONE_to_OSTIMER_CLK     = CLKCTL1_TUPLE_MUXA(0x480U, 7),
+
+    kSFRO_to_FLEXCOMM0      = CLKCTL1_TUPLE_MUXA(0x508U, 0),
+    kFFRO_to_FLEXCOMM0      = CLKCTL1_TUPLE_MUXA(0x508U, 1),
+    kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 2),
+    kMCLK_IN_to_FLEXCOMM0   = CLKCTL1_TUPLE_MUXA(0x508U, 3),
+    kFRG_to_FLEXCOMM0       = CLKCTL1_TUPLE_MUXA(0x508U, 4),
+    kNONE_to_FLEXCOMM0      = CLKCTL1_TUPLE_MUXA(0x508U, 7),
+
+    kSFRO_to_FLEXCOMM1      = CLKCTL1_TUPLE_MUXA(0x528U, 0),
+    kFFRO_to_FLEXCOMM1      = CLKCTL1_TUPLE_MUXA(0x528U, 1),
+    kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 2),
+    kMCLK_IN_to_FLEXCOMM1   = CLKCTL1_TUPLE_MUXA(0x528U, 3),
+    kFRG_to_FLEXCOMM1       = CLKCTL1_TUPLE_MUXA(0x528U, 4),
+    kNONE_to_FLEXCOMM1      = CLKCTL1_TUPLE_MUXA(0x528U, 7),
+
+    kSFRO_to_FLEXCOMM2      = CLKCTL1_TUPLE_MUXA(0x548U, 0),
+    kFFRO_to_FLEXCOMM2      = CLKCTL1_TUPLE_MUXA(0x548U, 1),
+    kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 2),
+    kMCLK_IN_to_FLEXCOMM2   = CLKCTL1_TUPLE_MUXA(0x548U, 3),
+    kFRG_to_FLEXCOMM2       = CLKCTL1_TUPLE_MUXA(0x548U, 4),
+    kNONE_to_FLEXCOMM2      = CLKCTL1_TUPLE_MUXA(0x548U, 7),
+
+    kSFRO_to_FLEXCOMM3      = CLKCTL1_TUPLE_MUXA(0x568U, 0),
+    kFFRO_to_FLEXCOMM3      = CLKCTL1_TUPLE_MUXA(0x568U, 1),
+    kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 2),
+    kMCLK_IN_to_FLEXCOMM3   = CLKCTL1_TUPLE_MUXA(0x568U, 3),
+    kFRG_to_FLEXCOMM3       = CLKCTL1_TUPLE_MUXA(0x568U, 4),
+    kNONE_to_FLEXCOMM3      = CLKCTL1_TUPLE_MUXA(0x568U, 7),
+
+    kSFRO_to_FLEXCOMM14      = CLKCTL1_TUPLE_MUXA(0x6C8U, 0),
+    kFFRO_to_FLEXCOMM14      = CLKCTL1_TUPLE_MUXA(0x6C8U, 1),
+    kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 2),
+    kMCLK_IN_to_FLEXCOMM14   = CLKCTL1_TUPLE_MUXA(0x6C8U, 3),
+    kFRG_to_FLEXCOMM14       = CLKCTL1_TUPLE_MUXA(0x6C8U, 4),
+    kNONE_to_FLEXCOMM14      = CLKCTL1_TUPLE_MUXA(0x6C8U, 7),
+
+    kSFRO_to_DMIC_CLK      = CLKCTL1_TUPLE_MUXA(0x700U, 0),
+    kFFRO_to_DMIC_CLK      = CLKCTL1_TUPLE_MUXA(0x700U, 1),
+    kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 2),
+    kMCLK_IN_to_DMIC_CLK   = CLKCTL1_TUPLE_MUXA(0x700U, 3),
+    kLPOSC_to_DMIC_CLK     = CLKCTL1_TUPLE_MUXA(0x700U, 4),
+    kCLK32K_to_DMIC_CLK    = CLKCTL1_TUPLE_MUXA(0x700U, 5),
+    kMAIN_CLK_to_DMIC_CLK  = CLKCTL1_TUPLE_MUXA(0x700U, 6),
+    kNONE_to_DMIC_CLK      = CLKCTL1_TUPLE_MUXA(0x700U, 7),
+
+    kMAIN_CLK_to_CTIMER0  = CLKCTL1_TUPLE_MUXA(0x720U, 0),
+    kSFRO_to_CTIMER0      = CLKCTL1_TUPLE_MUXA(0x720U, 1),
+    kFFRO_to_CTIMER0      = CLKCTL1_TUPLE_MUXA(0x720U, 2),
+    kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 3),
+    kMCLK_IN_to_CTIMER0   = CLKCTL1_TUPLE_MUXA(0x720U, 4),
+    kLPOSC_to_CTIMER0     = CLKCTL1_TUPLE_MUXA(0x720U, 5),
+    kNONE_to_CTIMER0      = CLKCTL1_TUPLE_MUXA(0x720U, 7),
+
+    kMAIN_CLK_to_CTIMER1  = CLKCTL1_TUPLE_MUXA(0x724U, 0),
+    kSFRO_to_CTIMER1      = CLKCTL1_TUPLE_MUXA(0x724U, 1),
+    kFFRO_to_CTIMER1      = CLKCTL1_TUPLE_MUXA(0x724U, 2),
+    kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 3),
+    kMCLK_IN_to_CTIMER1   = CLKCTL1_TUPLE_MUXA(0x724U, 4),
+    kLPOSC_to_CTIMER1     = CLKCTL1_TUPLE_MUXA(0x724U, 5),
+    kNONE_to_CTIMER1      = CLKCTL1_TUPLE_MUXA(0x724U, 7),
+
+    kMAIN_CLK_to_CTIMER2  = CLKCTL1_TUPLE_MUXA(0x728U, 0),
+    kSFRO_to_CTIMER2      = CLKCTL1_TUPLE_MUXA(0x728U, 1),
+    kFFRO_to_CTIMER2      = CLKCTL1_TUPLE_MUXA(0x728U, 2),
+    kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 3),
+    kMCLK_IN_to_CTIMER2   = CLKCTL1_TUPLE_MUXA(0x728U, 4),
+    kLPOSC_to_CTIMER2     = CLKCTL1_TUPLE_MUXA(0x728U, 5),
+    kNONE_to_CTIMER2      = CLKCTL1_TUPLE_MUXA(0x728U, 7),
+
+    kMAIN_CLK_to_CTIMER3  = CLKCTL1_TUPLE_MUXA(0x72CU, 0),
+    kSFRO_to_CTIMER3      = CLKCTL1_TUPLE_MUXA(0x72CU, 1),
+    kFFRO_to_CTIMER3      = CLKCTL1_TUPLE_MUXA(0x72CU, 2),
+    kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 3),
+    kMCLK_IN_to_CTIMER3   = CLKCTL1_TUPLE_MUXA(0x72CU, 4),
+    kLPOSC_to_CTIMER3     = CLKCTL1_TUPLE_MUXA(0x72CU, 5),
+    kNONE_to_CTIMER3      = CLKCTL1_TUPLE_MUXA(0x72CU, 7),
+
+    kFFRO_to_MCLK_CLK      = CLKCTL1_TUPLE_MUXA(0x740U, 0),
+    kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 1),
+    kMAIN_CLK_to_MCLK_CLK  = CLKCTL1_TUPLE_MUXA(0x740U, 2),
+    kNONE_to_MCLK_CLK      = CLKCTL1_TUPLE_MUXA(0x740U, 3),
+
+    kSFRO_to_CLKOUT              = CLKOUT_TUPLE_MUX(0U, 0U, 0U),
+    kSYSOSC_to_CLKOUT            = CLKOUT_TUPLE_MUX(1U, 0U, 0U),
+    kLPOSC_to_CLKOUT             = CLKOUT_TUPLE_MUX(2U, 0U, 0U),
+    kFFRO_to_CLKOUT              = CLKOUT_TUPLE_MUX(3U, 0U, 0U),
+    kMAIN_CLK_to_CLKOUT          = CLKOUT_TUPLE_MUX(4U, 0U, 0U),
+    kREFCLK_SYS_to_CLKOUT        = CLKOUT_TUPLE_MUX(5U, 0U, 0U),
+    kAVPLL_CH2_to_CLKOUT         = CLKOUT_TUPLE_MUX(6U, 0U, 0U),
+    kMAIN_PLL_to_CLKOUT          = CLKOUT_TUPLE_MUX(7U, 1U, 0U),
+    kAUX0_PLL_to_CLKOUT          = CLKOUT_TUPLE_MUX(7U, 2U, 0U),
+    kAUX1_PLL_to_CLKOUT          = CLKOUT_TUPLE_MUX(7U, 4U, 0U),
+    kAUDIO_PLL_to_CLKOUT         = CLKOUT_TUPLE_MUX(7U, 5U, 0U),
+    kCLK32K_to_CLKOUT            = CLKOUT_TUPLE_MUX(7U, 6U, 0U),
+    kTCPU_MCI_FLEXSPI_to_CLKOUT  = CLKOUT_TUPLE_MUX(7U, 7U, 1U),
+    kTDDR_MCI_FLEXSPI_to_CLKOUT  = CLKOUT_TUPLE_MUX(7U, 7U, 2U),
+    kT3PLL_MCI_FLEXSPI_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 3U),
+    kT3PLL_MCI_256M_to_CLKOUT    = CLKOUT_TUPLE_MUX(7U, 7U, 4U),
+    kCAU_SLP_REF_CLK_to_CLKOUT   = CLKOUT_TUPLE_MUX(7U, 7U, 5U),
+    kTDDR_MCI_ENET_to_CLKOUT     = CLKOUT_TUPLE_MUX(7U, 7U, 6U),
+    kNONE_to_CLKOUT              = CLKOUT_TUPLE_MUX(7U, 7U, 7U),
+
+    kRC32K_to_CLK32K   = PMU_TUPLE_MUX(0x70U, 0),
+    kXTAL32K_to_CLK32K = PMU_TUPLE_MUX(0x70U, 1),
+    kNCO32K_to_CLK32K  = PMU_TUPLE_MUX(0x70U, 2),
+} clock_attach_id_t;
+
+/*!
+ * @brief Clock divider definition.
+ */
+typedef enum _clock_div_name
+{
+    kCLOCK_DivMainPllClk   = CLKCTL0_TUPLE_MUXA(0x240U, 0),
+    kCLOCK_DivAux0PllClk   = CLKCTL0_TUPLE_MUXA(0x248U, 0),
+    kCLOCK_DivAux1PllClk   = CLKCTL0_TUPLE_MUXA(0x24CU, 0),
+    kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(0x400U, 0),
+    kCLOCK_DivPfc1Clk      = CLKCTL0_TUPLE_MUXA(0x504U, 0),
+    kCLOCK_DivFlexspiClk   = CLKCTL0_TUPLE_MUXA(0x624U, 0),
+    kCLOCK_DivSctClk       = CLKCTL0_TUPLE_MUXA(0x644U, 0),
+    kCLOCK_DivUsbHsFclk    = CLKCTL0_TUPLE_MUXA(0x664U, 0),
+    kCLOCK_DivSystickClk   = CLKCTL0_TUPLE_MUXA(0x764U, 0),
+    kCLOCK_DivLcdClk       = CLKCTL0_TUPLE_MUXA(0x768U, 0),
+    kCLOCK_DivGauClk       = CLKCTL0_TUPLE_MUXA(0x76CU, 0),
+    kCLOCK_DivUsimClk      = CLKCTL0_TUPLE_MUXA(0x770U, 0),
+    kCLOCK_DivPmuFclk      = CLKCTL0_TUPLE_MUXA(0x780U, 0),
+
+    kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(0x240U, 0),
+    kCLOCK_DivPllFrgClk   = CLKCTL1_TUPLE_MUXA(0x6FCU, 0),
+    kCLOCK_DivDmicClk     = CLKCTL1_TUPLE_MUXA(0x704U, 0),
+    kCLOCK_DivMclkClk     = CLKCTL1_TUPLE_MUXA(0x744U, 0),
+    kCLOCK_DivClockOut    = CLKCTL1_TUPLE_MUXA(0x768U, 0),
+} clock_div_name_t;
+
+/*! @brief PLL configuration for FRG */
+typedef struct _clock_frg_clk_config
+{
+    uint8_t num; /*!< FRG clock */
+    enum
+    {
+        kCLOCK_FrgMainClk = 0, /*!< Main System clock */
+        kCLOCK_FrgPllDiv,      /*!< Main pll clock divider*/
+        kCLOCK_FrgSFro,        /*!< 16MHz FRO */
+        kCLOCK_FrgFFro,        /*!< FRO48/60 */
+    } sfg_clock_src;
+    uint8_t divider; /*!< Denominator of the fractional divider. */
+    uint8_t mult;    /*!< Numerator of the fractional divider. */
+} clock_frg_clk_config_t;
+
+/*! @brief TCPU PLL divider for tcpu_mci_flexspi_clk */
+typedef enum
+{
+    kCLOCK_TcpuFlexspiDiv12 = 0, /*!< Divided by 12 */
+    kCLOCK_TcpuFlexspiDiv11,     /*!< Divided by 11 */
+    kCLOCK_TcpuFlexspiDiv10,     /*!< Divided by 10 */
+    kCLOCK_TcpuFlexspiDiv9,      /*!< Divided by 9  */
+} clock_tcpu_flexspi_div_t;
+
+/*! @brief TDDR PLL divider for tddr_mci_flexspi_clk */
+typedef enum
+{
+    kCLOCK_TddrFlexspiDiv11 = 0, /*!< Divided by 11 */
+    kCLOCK_TddrFlexspiDiv10,     /*!< Divided by 10 */
+    kCLOCK_TddrFlexspiDiv9,      /*!< Divided by 9 */
+    kCLOCK_TddrFlexspiDiv8,      /*!< Divided by 8  */
+} clock_tddr_flexspi_div_t;
+
+/*! @brief T3 PLL IRC configuration */
+typedef enum
+{
+    kCLOCK_T3MciIrc60m = 0, /*!< T3 MCI IRC 59.53MHz */
+    kCLOCK_T3MciIrc48m,     /*!< T3 MCI IRC 48.30MHz */
+} clock_t3_mci_irc_config_t;
+
+/*! @brief AVPLL channel1 frequency configuration */
+typedef enum
+{
+    kCLOCK_AvPllChUnchanged = 0, /*!< AVPLL channel frequency unchanged. */
+    kCLOCK_AvPllChFreq2p048m,    /*!< AVPLL channel frequency 2.048MHz */
+    kCLOCK_AvPllChFreq4p096m,    /*!< AVPLL channel frequency 4.096MHz */
+    kCLOCK_AvPllChFreq6p144m,    /*!< AVPLL channel frequency 6.144MHz */
+    kCLOCK_AvPllChFreq8p192m,    /*!< AVPLL channel frequency 8.192MHz */
+    kCLOCK_AvPllChFreq11p2896m,  /*!< AVPLL channel frequency 11.2896MHz */
+    kCLOCK_AvPllChFreq12m,       /*!< AVPLL channel frequency 12MHz */
+    kCLOCK_AvPllChFreq12p288m,   /*!< AVPLL channel frequency 12.288MHz */
+    kCLOCK_AvPllChFreq24p576m,   /*!< AVPLL channel frequency 24.576MHz */
+    kCLOCK_AvPllChFreq64m,       /*!< AVPLL channel frequency 64MHz */
+    kCLOCK_AvPllChFreq98p304m,   /*!< AVPLL channel frequency 98.304MHz */
+} clock_avpll_ch_freq_t;
+
+/*! @brief AVPLL configuration */
+typedef struct
+{
+    clock_avpll_ch_freq_t ch1Freq; /*!< AVPLL channel 1 frequency configuration */
+    clock_avpll_ch_freq_t ch2Freq; /*!< AVPLL channel 2 frequency configuration */
+    bool enableCali;               /*!< Enable calibration */
+} clock_avpll_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
+ *
+ * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
+ * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
+ * if CLK_IN is 16MHz,
+ * @code
+ * CLOCK_SetClkinFreq(16000000);
+ * @endcode
+ */
+extern volatile uint32_t g_clkinFreq;
+/*! @brief External MCLK IN clock frequency.
+ *
+ * The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the
+ * function CLOCK_SetMclkInFreq to set the value in to clock driver. For example,
+ * if mclk_In is 16MHz,
+ * @code
+ * CLOCK_SetMclkInFreq(16000000);
+ * @endcode
+ */
+extern volatile uint32_t g_mclkinFreq;
+
+/*! @brief  Return Frequency of t3pll_mci_48_60m_irc
+ *  @return Frequency of t3pll_mci_48_60m_irc
+ */
+uint32_t CLOCK_GetT3PllMciIrcClkFreq(void);
+
+/*! @brief  Return Frequency of t3pll_mci_213p3m
+ *  @return Frequency of t3pll_mci_213p3m
+ */
+uint32_t CLOCK_GetT3PllMci213mClkFreq(void);
+
+/*! @brief  Return Frequency of t3pll_mci_256m
+ *  @return Frequency of t3pll_mci_256m
+ */
+uint32_t CLOCK_GetT3PllMci256mClkFreq(void);
+
+/*! @brief  Return Frequency of t3pll_mci_flexspi_clk
+ *  @return Frequency of t3pll_mci_flexspi_clk
+ */
+uint32_t CLOCK_GetT3PllMciFlexspiClkFreq(void);
+
+/*! @brief  Return Frequency of tcpu_mci_clk
+ *  @return Frequency of tcpu_mci_clk
+ */
+uint32_t CLOCK_GetTcpuMciClkFreq(void);
+
+/*! @brief  Return Frequency of tcpu_mci_flexspi_clk
+ *  @return Frequency of tcpu_mci_flexspi_clk
+ */
+uint32_t CLOCK_GetTcpuMciFlexspiClkFreq(void);
+
+/*! @brief  Return Frequency of tddr_mci_flexspi_clk
+ *  @return Frequency of tddr_mci_flexspi_clk
+ */
+uint32_t CLOCK_GetTddrMciFlexspiClkFreq(void);
+
+/*! @brief  Return Frequency of tddr_mci_enet_clk
+ *  @return Frequency of tddr_mci_enet_clk
+ */
+uint32_t CLOCK_GetTddrMciEnetClkFreq(void);
+
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param clk  Which clock to enable, see @ref clock_ip_name_t.
+ */
+void CLOCK_EnableClock(clock_ip_name_t clk);
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param clk  Which clock to disable, see @ref clock_ip_name_t.
+ */
+void CLOCK_DisableClock(clock_ip_name_t clk);
+
+/**
+ * @brief   Configure the clock selection muxes.
+ * @param   connection  : Clock to be configured.
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+
+/**
+ * @brief   Setup clock dividers.
+ * @param   name        : Clock divider name
+ * @param   divider     : Value to be divided.
+ */
+void CLOCK_SetClkDiv(clock_div_name_t name, uint32_t divider);
+
+/*! @brief  Return Frequency of selected clock
+ *  @return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*! @brief  Return Input frequency for the Fractional baud rate generator
+ *  @return Input Frequency for FRG
+ */
+uint32_t CLOCK_GetFRGClock(uint32_t id);
+
+/*! @brief  Set output of the Fractional baud rate generator
+ *  @param  config    : Configuration to set to FRGn clock.
+ */
+void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
+
+/*! @brief  Return Frequency of FFRO
+ *  @return Frequency of FFRO
+ */
+uint32_t CLOCK_GetFFroFreq(void);
+
+/*! @brief  Return Frequency of SFRO
+ *  @return Frequency of SFRO
+ */
+uint32_t CLOCK_GetSFroFreq(void);
+
+/*! @brief  Return Frequency of AUDIO PLL (AVPLL CH1)
+ *  @return Frequency of AUDIO PLL
+ */
+uint32_t CLOCK_GetAvPllCh1Freq(void);
+
+/*! @brief  Return Frequency of AVPLL CH2
+ *  @return Frequency of AVPLL CH2
+ */
+uint32_t CLOCK_GetAvPllCh2Freq(void);
+
+/*! @brief  Return Frequency of main clk
+ *  @return Frequency of main clk
+ */
+uint32_t CLOCK_GetMainClkFreq(void);
+
+/*! @brief  Return Frequency of core/bus clk
+ *  @return Frequency of core/bus clk
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+
+/*! @brief  Return Frequency of systick clk
+ *  @return Frequency of systick clk
+ */
+uint32_t CLOCK_GetSystickClkFreq(void);
+
+/*! @brief  Return Frequency of sys osc Clock
+ *  @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
+ */
+static inline uint32_t CLOCK_GetSysOscFreq(void)
+{
+    return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
+}
+
+/*! @brief  Return Frequency of MCLK Input Clock
+ *  @return Frequency of MCLK input Clock.
+ */
+static inline uint32_t CLOCK_GetMclkInClkFreq(void)
+{
+    return g_mclkinFreq;
+}
+
+/*! @brief  Return Frequency of LPOSC
+ *  @return Frequency of LPOSC
+ */
+static inline uint32_t CLOCK_GetLpOscFreq(void)
+{
+    return CLK_XTAL_OSC_CLK / 40U;
+}
+
+/*! @brief  Return Frequency of CLK_32K
+ *  @return Frequency of 32KHz osc
+ */
+static inline uint32_t CLOCK_GetClk32KFreq(void)
+{
+    return CLK_RTC_32K_CLK;
+}
+
+/*! @brief  Enables and disables 32KHz XTAL
+ *  @param  enable : true to enable 32k XTAL clock, false to disable clock
+ */
+void CLOCK_EnableXtal32K(bool enable);
+
+/*! @brief  Enables and disables RTC 32KHz
+ *  @param  enable : true to enable 32k RTC clock, false to disable clock
+ */
+void CLOCK_EnableRtc32K(bool enable);
+
+/*!
+ * @brief Set the CLKIN (CLKIN pin) frequency based on GPIO4 input.
+ *
+ * @param freq : The CLK_IN pin input clock frequency in Hz.
+ */
+static inline void CLOCK_SetClkinFreq(uint32_t freq)
+{
+    g_clkinFreq = freq;
+}
+/*!
+ * @brief Set the MCLK in (mclk_in) clock frequency based on board setting.
+ *
+ * @param freq : The MCLK input clock frequency in Hz.
+ */
+static inline void CLOCK_SetMclkinFreq(uint32_t freq)
+{
+    g_mclkinFreq = freq;
+}
+
+/*! @brief  Return Frequency of DMIC clk
+ *  @return Frequency of DMIC clk
+ */
+uint32_t CLOCK_GetDmicClkFreq(void);
+
+/*! @brief  Return Frequency of LCD clk
+ *  @return Frequency of LCD clk
+ */
+uint32_t CLOCK_GetLcdClkFreq(void);
+
+/*! @brief  Return Frequency of WDT clk
+ *  @return Frequency of WDT clk
+ */
+uint32_t CLOCK_GetWdtClkFreq(void);
+
+/*! @brief  Return Frequency of mclk
+ *  @return Frequency of mclk clk
+ */
+uint32_t CLOCK_GetMclkClkFreq(void);
+
+/*! @brief  Return Frequency of sct
+ *  @return Frequency of sct clk
+ */
+uint32_t CLOCK_GetSctClkFreq(void);
+
+/*! @brief  Return Frequency of Flexcomm functional Clock
+ *  @param   id    : flexcomm index to get frequency.
+ *  @return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of CTimer Clock
+ *  @param   id    : ctimer index to get frequency.
+ *  @return Frequency of CTimer Clock
+ */
+uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of Utick Clock
+ *  @return Frequency of Utick Clock
+ */
+uint32_t CLOCK_GetUtickClkFreq(void);
+
+/*! @brief  Return Frequency of Flexspi Clock
+ *  @return Frequency of Flexspi.
+ */
+uint32_t CLOCK_GetFlexspiClkFreq(void);
+
+/*! @brief  Return Frequency of USIM Clock
+ *  @return Frequency of USIM.
+ */
+uint32_t CLOCK_GetUsimClkFreq(void);
+
+/*! @brief  Return Frequency of GAU Clock
+ *  @return Frequency of GAU.
+ */
+uint32_t CLOCK_GetGauClkFreq(void);
+
+/*! @brief  Return Frequency of OSTimer Clock
+ *  @return Frequency of OSTimer.
+ */
+uint32_t CLOCK_GetOSTimerClkFreq(void);
+
+/*! @brief  Initialize TCPU FVCO to target frequency.
+ *          For 40MHz XTAL, FVCO ranges from 3000MHz to 3840MHz.
+            For 38.4MHz XTAL, FVCO ranges from 2995.2MHz to 3840MHz
+ *  @param  targetHz  : Target FVCO frequency in Hz.
+ *  @param  div       : Divider for tcpu_mci_flexspi_clk.
+ *  @return Actual FVCO frequency in Hz.
+ */
+uint32_t CLOCK_InitTcpuRefClk(uint32_t targetHz, clock_tcpu_flexspi_div_t div);
+
+/*! @brief  Deinit the TCPU reference clock.
+ */
+void CLOCK_DeinitTcpuRefClk(void);
+
+/*! @brief  Initialize the TDDR reference clock.
+ *  @param  div       : Divider for tddr_mci_flexspi_clk.
+ */
+void CLOCK_InitTddrRefClk(clock_tddr_flexspi_div_t div);
+
+/*! @brief  Deinit the TDDR reference clock.
+ */
+void CLOCK_DeinitTddrRefClk(void);
+
+/*! @brief  Initialize the T3 reference clock.
+ *  @param  cnfg       : t3pll_mci_48_60m_irc clock configuration
+ */
+void CLOCK_InitT3RefClk(clock_t3_mci_irc_config_t cnfg);
+
+/*! @brief  Deinit the T3 reference clock. */
+void CLOCK_DeinitT3RefClk(void);
+
+/*! @brief  Initialize the AVPLL. Both channel 1 and 2 are enabled.
+ *  @param  cnfg       : AVPLL clock configuration
+ */
+void CLOCK_InitAvPll(const clock_avpll_config_t *cnfg);
+
+/*! @brief  Deinit the AVPLL. All channels are disabled.
+ */
+void CLOCK_DeinitAvPll(void);
+
+/*! @brief  Update the AVPLL channel configuration. Enable/Disable state keeps unchanged.
+ *  @param  ch1Freq  : Channel 1 frequency to set.
+ *  @param  ch2Freq  : Channel 2 frequency to set.
+ *  @param  enableCali : Enable AVPLL calibration.
+ */
+void CLOCK_ConfigAvPllCh(clock_avpll_ch_freq_t ch1Freq, clock_avpll_ch_freq_t ch2Freq, bool enableCali);
+
+/*! @brief  Enable the AVPLL channel.
+ *  @param  enableCh1  : Enable AVPLL channel1, channel unchanged on false.
+ *  @param  enableCh2  : Enable AVPLL channel2, channel unchanged on false.
+ *  @param  enableCali : Enable AVPLL calibration.
+ */
+void CLOCK_EnableAvPllCh(bool enableCh1, bool enableCh2, bool enableCali);
+
+/*! @brief  Disable the AVPLL.
+ *  @param  disableCh1  : Disable AVPLL channel1, channel unchanged on false.
+ *  @param  disableCh2  : Disable AVPLL channel2, channel unchanged on false.
+ */
+void CLOCK_DisableAvPllCh(bool disableCh1, bool disableCh2);
+
+/*! @brief Enable USB HS PHY PLL clock.
+ *
+ * This function enables USB HS PHY PLL clock.
+ */
+void CLOCK_EnableUsbhsPhyClock(void);
+
+/*! @brief Disable USB HS PHY PLL clock.
+ *
+ * This function disables USB HS PHY PLL clock.
+ */
+void CLOCK_DisableUsbhsPhyClock(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common.c
new file mode 100644
index 0000000000..f7483b9f13
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
+    {
+        return NULL;
+    }
+
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+    {
+        return NULL;
+    }
+
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc((size_t)alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common.h
new file mode 100644
index 0000000000..c697f96a64
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common.h
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_COMMON_H_
+#define FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Macro to use the default weak IRQ handler in drivers. */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
+
+/*! @brief Construct the version number for drivers.
+ *
+ * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
+ * and 16-bit platforms(such as DSC).
+ *
+ * @verbatim
+
+   | Unused    || Major Version || Minor Version ||  Bug Fix    |
+   31        25  24           17  16            9  8            0
+
+   @endverbatim
+ */
+#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief common driver version. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
+/*! @} */
+
+/*! @name Debug console type definition. */
+/*! @{ */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI      3U  /*!< Debug console based on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC     4U  /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U  /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART      6U  /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART     7U  /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */
+/*! @} */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic               = 0,   /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH                 = 1,   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI                 = 4,   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI            = 5,   /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI                  = 6,   /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART           = 7,   /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C            = 8,   /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C                 = 9,   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART                  = 10,  /*!< Group number for UART status codes. */
+    kStatusGroup_I2C                   = 11,  /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI                 = 12,  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART                = 13,  /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI                   = 14,  /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC                  = 15,  /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42                = 16,  /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC                  = 17,  /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC                 = 18,  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI                   = 19,  /*!< Group number for SAI status code */
+    kStatusGroup_MCG                   = 20,  /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG                   = 21,  /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI                 = 22,  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S            = 23,  /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD         = 24,  /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP              = 25,  /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C          = 26,  /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S                   = 27,  /*!< Group number for I2S status codes */
+    kStatusGroup_IUART                 = 28,  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI                   = 29,  /*!< Group number for CSI status codes */
+    kStatusGroup_MIPI_DSI              = 30,  /*!< Group number for MIPI DSI status codes */
+    kStatusGroup_SDRAMC                = 35,  /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER                 = 39,  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET                  = 40,  /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY                   = 41,  /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX                = 42,  /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD             = 43,  /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM                  = 44,  /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI                  = 45,  /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA                   = 50,  /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA                  = 51,  /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR                = 52,  /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN               = 53,  /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC                   = 54,  /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA         = 55,  /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI               = 56,  /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART             = 57,  /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC                  = 58,  /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF                  = 59,  /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI                 = 60,  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP                   = 61,  /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN                  = 62,  /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM                  = 63,  /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI                 = 64,  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC                 = 65,  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C               = 66,  /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_DCP                   = 67,  /*!< Group number for DCP status codes.*/
+    kStatusGroup_MSCAN                 = 68,  /*!< Group number for MSCAN status codes.*/
+    kStatusGroup_ESAI                  = 69,  /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI               = 70,  /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC                  = 71,  /*!< Group number for MMDC status codes. */
+    kStatusGroup_PDM                   = 72,  /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA                  = 73,  /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS                   = 74,  /*!< Group number for ICS status codes. */
+    kStatusGroup_SPDIF                 = 75,  /*!< Group number for SPDIF status codes. */
+    kStatusGroup_LPC_MINISPI           = 76,  /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT             = 77,  /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP           = 78,  /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_I3C                   = 79,  /*!< Group number for I3C status codes */
+    kStatusGroup_LPC_I2C_1             = 97,  /*!< Group number for LPC_I2C_1 status codes. */
+    kStatusGroup_NOTIFIER              = 98,  /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole          = 99,  /*!< Group number for debug console status codes. */
+    kStatusGroup_SEMC                  = 100, /*!< Group number for SEMC status codes. */
+    kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+    kStatusGroup_IAP                   = 102, /*!< Group number for IAP status codes */
+    kStatusGroup_SFA                   = 103, /*!< Group number for SFA status codes*/
+    kStatusGroup_SPC                   = 104, /*!< Group number for SPC status codes. */
+    kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */
+    kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */
+    kStatusGroup_VBAT                  = 107, /*!< Group number for VBAT status codes */
+    kStatusGroup_XSPI                  = 108, /*!< Group number for XSPI status codes */
+    kStatusGroup_PNGDEC                = 109, /*!< Group number for PNGDEC status codes */
+    kStatusGroup_JPEGDEC               = 110, /*!< Group number for JPEGDEC status codes */
+
+    kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER      = 123, /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI        = 124, /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C        = 125, /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH      = 126, /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM        = 127, /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG        = 128, /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_HAL_I2S        = 129, /*!< Group number for HAL I2S status codes. */
+    kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */
+    kStatusGroup_TIMERMANAGER   = 135, /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER  = 136, /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED            = 137, /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON         = 138, /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM  = 139, /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL          = 140, /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER    = 141, /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST           = 142, /*!< Group number for List status codes. */
+    kStatusGroup_OSA            = 143, /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK    = 144, /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG            = 145, /*!< Group number for messaging status codes. */
+    kStatusGroup_SDK_OCOTP      = 146, /*!< Group number for OCOTP status codes. */
+    kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
+    kStatusGroup_CODEC          = 148, /*!< Group number for codec status codes. */
+    kStatusGroup_ASRC           = 149, /*!< Group number for codec status ASRC. */
+    kStatusGroup_OTFAD          = 150, /*!< Group number for codec status codes. */
+    kStatusGroup_SDIOSLV        = 151, /*!< Group number for SDIOSLV status codes. */
+    kStatusGroup_MECC           = 152, /*!< Group number for MECC status codes. */
+    kStatusGroup_ENET_QOS       = 153, /*!< Group number for ENET_QOS status codes. */
+    kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */
+    kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */
+    kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */
+    kStatusGroup_ELEMU          = 157, /*!< Group number for ELEMU status codes. */
+    kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
+    kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
+    kStatusGroup_IPED           = 160, /*!< Group number for IPED status codes. */
+    kStatusGroup_ELS_PKC        = 161, /*!< Group number for ELS PKC status codes. */
+    kStatusGroup_CSS_PKC        = 162, /*!< Group number for CSS PKC status codes. */
+    kStatusGroup_HOSTIF         = 163, /*!< Group number for HOSTIF status codes. */
+    kStatusGroup_CLIF           = 164, /*!< Group number for CLIF status codes. */
+    kStatusGroup_BMA            = 165, /*!< Group number for BMA status codes. */
+    kStatusGroup_NETC           = 166, /*!< Group number for NETC status codes. */
+    kStatusGroup_ELE            = 167, /*!< Group number for ELE status codes. */
+    kStatusGroup_GLIKEY         = 168, /*!< Group number for GLIKEY status codes. */
+};
+
+/*! \public
+ * @brief Generic status return codes.
+ */
+enum
+{
+    kStatus_Success         = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
+    kStatus_Fail            = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
+    kStatus_ReadOnly        = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
+    kStatus_OutOfRange      = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
+    kStatus_Timeout         = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
+    kStatus_NoTransferInProgress =
+        MAKE_STATUS(kStatusGroup_Generic, 6),            /*!< Generic status for no transfer in progress. */
+    kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
+    kStatus_NoData =
+        MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+#ifdef __ZEPHYR__
+#include <zephyr/sys/util.h>
+#else
+/*!
+ * @name Min/max macros
+ * @{
+ */
+#if !defined(MIN)
+/*! Computes the minimum of \a a and \a b. */
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+/*! Computes the maximum of \a a and \a b. */
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+/*! @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+#endif /* __ZEPHYR__ */
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/*! @{ */
+#if !defined(UINT16_MAX)
+/*! Max value of uint16_t type. */
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+/*! Max value of uint32_t type. */
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/*! @} */
+
+/*! Macro to get upper 32 bits of a 64-bit value */
+#if !defined(UINT64_H)
+#define UINT64_H(X)        ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL))
+#endif
+
+/*! Macro to get lower 32 bits of a 64-bit value */
+#if !defined(UINT64_L)
+#define UINT64_L(X)        ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL))
+#endif
+
+/*!
+ * @def SUPPRESS_FALL_THROUGH_WARNING()
+ *
+ * For switch case code block, if case section ends without "break;" statement, there wil be
+ * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ * case section which misses "break;"statement.
+ */
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
+#else
+#define SUPPRESS_FALL_THROUGH_WARNING()
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+/*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+void *SDK_Malloc(size_t size, size_t alignbytes);
+
+/*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+void SDK_Free(void *ptr);
+#endif
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ *  if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#if (defined(__DSC__) && defined(__CW__))
+#include "fsl_common_dsc.h"
+#elif defined(__XTENSA__)
+#include "fsl_common_dsp.h"
+#else
+#include "fsl_common_arm.h"
+#endif
+
+#endif /* FSL_COMMON_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common_arm.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common_arm.c
new file mode 100644
index 0000000000..030a0e7ecd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common_arm.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common_arm"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+#ifdef __VECTOR_TABLE
+#undef __VECTOR_TABLE
+#endif
+
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];
+
+#define __VECTOR_TABLE          Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM            Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[(int32_t)irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+
+/*
+ * When the SYSCON STARTER registers are discontinuous, these functions are
+ * implemented in fsl_power.c.
+ */
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1UL << intNumber;
+    (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERCLR[index] = 1UL << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(DWT)
+/* Use WDT. */
+void MSDK_EnableCpuCycleCounter(void)
+{
+    /* Make sure the DWT trace fucntion is enabled. */
+    if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
+    {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    }
+
+    /* CYCCNT not supported on this device. */
+    assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
+
+    /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
+    if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
+    {
+        DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+}
+
+uint32_t MSDK_GetCpuCycleCount(void)
+{
+    return DWT->CYCCNT;
+}
+#endif /* defined(DWT) */
+
+#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT))
+/* Use software loop. */
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+    SUBS R0, R0, #1
+    CMP  R0, #0
+    BNE  loop
+    BX   LR
+}
+#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    X0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop%=:                        \n"
+        "    SUB    X0, X0, #1          \n"
+        "    CMP    X0, #0              \n"
+
+        "    BNE    loop%=              \n"
+        :
+        :
+        : "r0");
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    R0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop%=:                        \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+        "    SUB    R0, R0, #1          \n"
+#else
+        "    SUBS   R0, R0, #1          \n"
+#endif
+        "    CMP    R0, #0              \n"
+
+        "    BNE    loop%=              \n"
+        :
+        :
+        : "r0");
+}
+#endif /* defined(__CC_ARM) */
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
+ *  effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
+ *  coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
+ *  up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
+{
+    uint64_t count;
+
+    if (delayTime_us > 0U)
+    {
+        count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
+
+        assert(count <= UINT32_MAX);
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
+
+        MSDK_EnableCpuCycleCounter();
+        /* Calculate the count ticks. */
+        count += MSDK_GetCpuCycleCount();
+
+        if (count > UINT32_MAX)
+        {
+            count -= UINT32_MAX;
+            /* Wait for cyccnt overflow. */
+            while (count < MSDK_GetCpuCycleCount())
+            {
+            }
+        }
+
+        /* Wait for cyccnt reach count value. */
+        while (count > MSDK_GetCpuCycleCount())
+        {
+        }
+#else
+#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55))
+        /*
+         * Cortex-A53/A55 execution throughput:
+         *  - SUB/CMP: 2 instructions per cycle
+         *  - BNE:     1 instruction per cycle
+         * So, each loop takes 2 CPU cycles.
+         */
+        count = count / 2U;
+#elif (__CORTEX_M == 7)
+        /* Divide value may be different in various environment to ensure delay is precise.
+         * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+         * two instructions in one period, through test here set divide 1.5. Other M cores use
+         * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
+         * not matter because other instructions outside while loop is enough to fill the time.
+         */
+        count = count / 3U * 2U;
+#else
+        count = count / 4U;
+#endif
+        DelayLoop((uint32_t)count);
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+    }
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common_arm.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common_arm.h
new file mode 100644
index 0000000000..1d76435f33
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_common_arm.h
@@ -0,0 +1,914 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022, 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_COMMON_ARM_H_
+#define FSL_COMMON_ARM_H_
+
+/*
+ * For CMSIS pack RTE.
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
+ * of the related <RTE_Components_h> element for all selected software components.
+ */
+#ifdef _RTE_
+#include "RTE_Components.h"
+#endif
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*! @name Atomic modification
+ *
+ * These macros are used for atomic access, such as read-modify-write
+ * to the peripheral registers.
+ *
+ * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
+ * means the address of the peripheral register or variable you want to modify
+ * atomically, the parameter @c clearBits is the bits to clear, the parameter
+ * @c setBits it the bits to set.
+ * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
+ *
+ * @code
+   volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
+
+   SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
+   @endcode
+ *
+ * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
+ * register bit1:bit0 = 0b10.
+ *
+ * @note For the platforms don't support exclusive load and store, these macros
+ * disable the global interrupt to pretect the modification.
+ *
+ * @note These macros only guarantee the local processor atomic operations. For
+ * the multi-processor devices, use hardware semaphore such as SEMA42 to
+ * guarantee exclusive access if necessary.
+ *
+ * @{
+ */
+
+/*!
+ * @def SDK_ATOMIC_LOCAL_ADD(addr, val)
+ * Add value \a val from the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SUB(addr, val)
+ * Subtract value \a val to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SET(addr, bits)
+ * Set the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits)
+ * Clear the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)
+ * Toggle the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)
+ * For the variable at address \a address, clear the bits specifiled by \a clearBits
+ * and set the bits specifiled by \a setBits.
+ */
+
+/* clang-format off */
+#if ((defined(__ARM_ARCH_7M__     ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined(__ARM_ARCH_7EM__    ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
+/* clang-format on */
+
+/* If the LDREX and STREX are supported, use them. */
+#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXB(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXB((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXH(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXH((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXW(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXW((val), (addr)))
+
+static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                \
+         _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
+                                     _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
+
+#define SDK_ATOMIC_LOCAL_SUB(addr, val)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                \
+         _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
+                                     _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                 \
+         _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+                                     _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                            \
+         _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                       \
+              _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                             \
+         _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                        \
+              _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)                                                                           \
+    ((1UL == sizeof(*(addr))) ?                                                                                                            \
+         _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) :         \
+         ((2UL == sizeof(*(addr))) ?                                                                                                       \
+              _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \
+              _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits))))
+#else
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)      \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) += (val);                    \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_SUB(addr, val)      \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) -= (val);                    \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)     \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) |= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)   \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) &= ~(bits);                  \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)  \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) ^= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
+    do                                                           \
+    {                                                            \
+        uint32_t s_atomicOldInt;                                 \
+        s_atomicOldInt = DisableGlobalIRQ();                     \
+        *(addr)        = (*(addr) & ~(clearBits)) | (setBits);   \
+        EnableGlobalIRQ(s_atomicOldInt);                         \
+    } while (false)
+
+#endif
+/*! @} */
+
+/*! @name Timer utilities */
+/*! @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz))
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
+/*! @} */
+
+/*! @name ISR exit barrier
+ * @{
+ *
+ * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ * exception return operation might vector to incorrect interrupt.
+ * For Cortex-M7, if core speed much faster than peripheral register write speed,
+ * the peripheral interrupt flags may be still set after exiting ISR, this results to
+ * the same error similar with errata 83869.
+ */
+#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
+#define SDK_ISR_EXIT_BARRIER __DSB()
+#else
+#define SDK_ISR_EXIT_BARRIER
+#endif
+
+/*! @} */
+
+/*! @name Alignment variable definition macros */
+/*! @{ */
+#if (defined(__ICCARM__))
+/*
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http:/ /supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+    _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported
+#endif
+
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+/*! @} */
+
+/*!
+ * @name Non-cacheable region definition macros
+ *
+ * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable
+ * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
+ * these zero-inited variables will be initialized to zero in system startup.
+ *
+ * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ *
+ * @{
+ */
+
+/*!
+ * @def AT_NONCACHEABLE_SECTION(var)
+ * Define a variable \a var, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)
+ * Define a variable \a var, and place it in non-cacheable section, the start address
+ * of the variable is aligned to \a alignbytes.
+ *
+ * @def AT_NONCACHEABLE_SECTION_INIT(var)
+ * Define a variable \a var with initial value, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)
+ * Define a variable \a var with initial value, and place it in non-cacheable section,
+ * the start address of the variable is aligned to \a alignbytes.
+ */
+
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
+     defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+
+#if (defined(__ICCARM__))
+#define AT_NONCACHEABLE_SECTION(var)                   var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var)              var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#if (defined(__CC_ARM))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
+#endif
+
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif
+
+#else
+
+#define AT_NONCACHEABLE_SECTION(var)                        var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)      SDK_ALIGN(var, alignbytes)
+#define AT_NONCACHEABLE_SECTION_INIT(var)                   var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
+
+#endif
+
+/*! @} */
+
+/*!
+ * @name Time sensitive region
+ * @{
+ */
+
+/*!
+ * @def AT_QUICKACCESS_SECTION_CODE(func)
+ * Place function in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA(var)
+ * Place data in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)
+ * Place data in a section which can be accessed quickly by core, and the variable
+ * address is set to align with \a alignbytes.
+ */
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(var)  var @"DataQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess"
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/*! @} */
+
+/*!
+ * @name Ram Function
+ * @{
+ *
+ * @def RAMFUNCTION_SECTION_CODE(func)
+ * Place function in ram.
+ */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/*! @} */
+
+/*!
+ * @def MSDK_REG_SECURE_ADDR(x)
+ * Convert the register address to the one used in secure mode.
+ *
+ * @def MSDK_REG_NONSECURE_ADDR(x)
+ * Convert the register address to the one used in non-secure mode.
+ */
+
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+#define MSDK_REG_SECURE_ADDR(x) ((uintptr_t)(x) | (0x1UL << 28))
+#define MSDK_REG_NONSECURE_ADDR(x) ((uintptr_t)(x) & ~(0x1UL << 28))
+#else
+#define MSDK_REG_SECURE_ADDR(x) (x)
+#define MSDK_REG_NONSECURE_ADDR(x) (x)
+#endif
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+        void DefaultISR(void);
+#endif
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+static inline status_t EnableIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+static inline status_t DisableIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
+        NVIC_DisableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Enable the IRQ, and also set the interrupt priority.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ to Enable.
+ * @param priNum Priority number set to interrupt controller register.
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_SetPriority(interrupt, priNum);
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_SetPriority(interrupt, priNum);
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Set the IRQ priority.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ to set.
+ * @param priNum Priority number set to interrupt controller register.
+ *
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_SetPriority(interrupt, priNum);
+#else
+        NVIC_SetPriority(interrupt, priNum);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Clear the pending IRQ flag.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The flag which IRQ to clear.
+ *
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_ClearPendingIRQ(interrupt);
+#else
+        NVIC_ClearPendingIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+    uint32_t mask;
+
+#if defined(CPSR_I_Msk)
+    mask = __get_CPSR() & CPSR_I_Msk;
+#elif defined(DAIF_I_BIT)
+    mask = __get_DAIF() & DAIF_I_BIT;
+#else
+    mask = __get_PRIMASK();
+#endif
+    __disable_irq();
+
+    return mask;
+}
+
+/*!
+ * @brief Enable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#elif defined(DAIF_I_BIT)
+    if (0UL == primask)
+    {
+        __enable_irq();
+    }
+#else
+    __set_PRIMASK(primask);
+#endif
+}
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(DWT)
+/*!
+ * @brief Enable the counter to get CPU cycles.
+ */
+void MSDK_EnableCpuCycleCounter(void);
+
+/*!
+ * @brief Get the current CPU cycle count.
+ *
+ * @return Current CPU cycle count.
+ */
+uint32_t MSDK_GetCpuCycleCount(void);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @} */
+
+#endif /* FSL_COMMON_ARM_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexcomm.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexcomm.c
new file mode 100644
index 0000000000..01f626b4b8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexcomm.c
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*! @brief Set the FLEXCOMM mode . */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);
+
+/*! @brief check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS;
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+/*! @brief Pointers to FLEXCOMM resets for each instance. */
+static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+    if (periph == FLEXCOMM_PERIPH_NONE)
+    {
+        return true;
+    }
+    else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
+    {
+        return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
+    }
+    else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+    {
+        return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+/*! brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+    uint32_t i;
+
+    for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+    {
+        if (MSDK_REG_SECURE_ADDR((uintptr_t)(uint8_t*)base) == MSDK_REG_SECURE_ADDR(s_flexcommBaseAddrs[i]))
+        {
+            break;
+        }
+    }
+
+    assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT);
+    return i;
+}
+
+/* Changes FLEXCOMM mode */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+    /* Check whether peripheral type is present */
+    if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Flexcomm is locked to different peripheral type than expected  */
+    if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
+        ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check if we are asked to lock */
+    if (lock != 0)
+    {
+        base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+    }
+    else
+    {
+        base->PSELID = (uint32_t)periph;
+    }
+
+    return kStatus_Success;
+}
+
+/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+    uint32_t idx = FLEXCOMM_GetInstance(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_flexcommClocks[idx]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+    /* Reset the FLEXCOMM module */
+    RESET_PeripheralReset(s_flexcommResets[idx]);
+#endif
+
+    /* Set the FLEXCOMM to given peripheral */
+    return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(base);
+
+    /* Clear handler first to avoid execution of the handler with wrong handle */
+    s_flexcommIrqHandler[instance] = NULL;
+    s_flexcommHandle[instance]     = flexcommHandle;
+    s_flexcommIrqHandler[instance] = handler;
+    SDK_ISR_EXIT_BARRIER;
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void);
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM0);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void);
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM1);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void);
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM2);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void);
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM3);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void);
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM4);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+#endif
+
+#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void);
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM5);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void);
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM6);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void);
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM7);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void);
+void FLEXCOMM8_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM8);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void);
+void FLEXCOMM9_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM9);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM10)
+void FLEXCOMM10_DriverIRQHandler(void);
+void FLEXCOMM10_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM10);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM11)
+void FLEXCOMM11_DriverIRQHandler(void);
+void FLEXCOMM11_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM11);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM12)
+void FLEXCOMM12_DriverIRQHandler(void);
+void FLEXCOMM12_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM12);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM13)
+void FLEXCOMM13_DriverIRQHandler(void);
+void FLEXCOMM13_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM13);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM14)
+void FLEXCOMM14_DriverIRQHandler(void);
+void FLEXCOMM14_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM14);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM15)
+void FLEXCOMM15_DriverIRQHandler(void);
+void FLEXCOMM15_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM15);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM16)
+void FLEXCOMM16_DriverIRQHandler(void);
+void FLEXCOMM16_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM16);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexcomm.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexcomm.h
new file mode 100644
index 0000000000..67763ad29b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexcomm.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXCOMM_H_
+#define FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*! @} */
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* FSL_FLEXCOMM_H_*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexspi.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexspi.c
new file mode 100644
index 0000000000..c3beebe38d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexspi.c
@@ -0,0 +1,1279 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexspi.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexspi"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define FREQ_1MHz             (1000000UL)
+#define FLEXSPI_DLLCR_DEFAULT (0x100UL)
+#define FLEXSPI_LUT_KEY_VAL   (0x5AF05AF0UL)
+
+enum
+{
+    kFLEXSPI_DelayCellUnitMin = 75,  /* 75ps. */
+    kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */
+};
+
+enum
+{
+    kFLEXSPI_FlashASampleClockSlaveDelayLocked =
+        FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */
+    kFLEXSPI_FlashASampleClockRefDelayLocked =
+        FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
+    kFLEXSPI_FlashBSampleClockSlaveDelayLocked =
+        FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */
+#endif
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK))
+    kFLEXSPI_FlashBSampleClockRefDelayLocked =
+        FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */
+#endif
+};
+
+/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */
+enum
+{
+    /*! IRQ sources enabled by the non-blocking transactional API. */
+    kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmptyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
+                kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag |
+                kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExecutionDoneFlag,
+
+    /*! Errors to check for. */
+    kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag |
+                  kFLEXSPI_IpCommandGrantTimeoutFlag,
+};
+
+/* FLEXSPI transfer state, _flexspi_transfer_state. */
+enum
+{
+    kFLEXSPI_Idle      = 0x0U, /*!< Transfer is done. */
+    kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */
+    kFLEXSPI_BusyRead  = 0x2U, /*!< FLEXSPI is busy write transfer. */
+};
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, flexspi_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void FLEXSPI_Memset(void *src, uint8_t value, size_t length);
+
+/*!
+ * @brief Calculate flash A/B sample clock DLL.
+ *
+ * @param base FLEXSPI base pointer.
+ * @param config Flash configuration parameters.
+ */
+static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to flexspi bases for each instance. */
+static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
+
+/*! @brief Pointers to flexspi IRQ number for each instance. */
+static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Clock name array */
+static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+/*! @brief Pointers to flexspi handles for each instance. */
+static flexspi_handle_t *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)];
+#endif
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET
+/*! @brief Pointers to FLEXSPI resets for each instance. */
+static const reset_ip_name_t s_flexspiResets[] = FLEXSPI_RSTS;
+#endif
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+/*! @brief Pointer to flexspi IRQ handler. */
+static flexspi_isr_t s_flexspiIsr;
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* To avoid compiler opitimizing this API into memset() in library. */
+#if defined(__ICCARM__)
+#pragma optimize = none
+#endif /* defined(__ICCARM__) */
+static void FLEXSPI_Memset(void *src, uint8_t value, size_t length)
+{
+    assert(src != NULL);
+    uint8_t *p = (uint8_t *)src;
+
+    for (uint32_t i = 0U; i < length; i++)
+    {
+        *p = value;
+        p++;
+    }
+}
+
+uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++)
+    {
+        if (MSDK_REG_SECURE_ADDR(s_flexspiBases[instance]) == MSDK_REG_SECURE_ADDR(base))
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_flexspiBases));
+
+    return instance;
+}
+
+static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
+{
+    bool isUnifiedConfig = true;
+    uint32_t flexspiDllValue;
+    uint32_t dllValue;
+    uint32_t temp;
+#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_PS) && FSL_FEATURE_FLEXSPI_DQS_DELAY_PS
+    uint32_t internalDqsDelayPs = FSL_FEATURE_FLEXSPI_DQS_DELAY_PS;
+#endif
+    uint32_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT;
+    switch (rxSampleClock)
+    {
+        case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackInternally:
+        case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromDqsPad:
+        case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromSckPad:
+            isUnifiedConfig = true;
+            break;
+        case (uint32_t)kFLEXSPI_ReadSampleClkExternalInputFromDqsPad:
+            if (config->isSck2Enabled)
+            {
+                isUnifiedConfig = true;
+            }
+            else
+            {
+                isUnifiedConfig = false;
+            }
+            break;
+        default:
+            assert(false);
+            break;
+    }
+
+    if (isUnifiedConfig)
+    {
+        flexspiDllValue = FLEXSPI_DLLCR_DEFAULT; /* 1 fixed delay cells in DLL delay chain) */
+    }
+    else
+    {
+        if (config->flexspiRootClk >= 100U * FREQ_1MHz)
+        {
+#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN) && FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN
+            /* DLLEN = 1, SLVDLYTARGET = 0x0, */
+            flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x00);
+#else
+            /* DLLEN = 1, SLVDLYTARGET = 0xF, */
+            flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F);
+#endif
+#if (defined(FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP) && FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP)
+            flexspiDllValue |= FLEXSPI_DLLCR_REFPHASEGAP(2U);
+#endif /* FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP */
+        }
+        else
+        {
+            temp     = (uint32_t)config->dataValidTime * 1000U; /* Convert data valid time in ns to ps. */
+            dllValue = temp / (uint32_t)kFLEXSPI_DelayCellUnitMin;
+            if (dllValue * (uint32_t)kFLEXSPI_DelayCellUnitMin < temp)
+            {
+                dllValue++;
+            }
+            flexspiDllValue = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue);
+        }
+    }
+    return flexspiDllValue;
+}
+
+status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
+{
+    status_t result = kStatus_Success;
+
+    /* Check for error. */
+    status &= (uint32_t)kErrorFlags;
+    if (0U != status)
+    {
+        /* Select the correct error code.. */
+        if (0U != (status & (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag))
+        {
+            result = kStatus_FLEXSPI_SequenceExecutionTimeout;
+        }
+        else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag))
+        {
+            result = kStatus_FLEXSPI_IpCommandSequenceError;
+        }
+        else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag))
+        {
+            result = kStatus_FLEXSPI_IpCommandGrantTimeout;
+        }
+        else
+        {
+            assert(false);
+        }
+
+        /* Clear the flags. */
+        FLEXSPI_ClearInterruptStatusFlags(base, status);
+    }
+
+    return result;
+}
+
+/*!
+ * brief Initializes the FLEXSPI module and internal state.
+ *
+ * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
+ * input configure parameters. Users should call this function before any FLEXSPI operations.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config FLEXSPI configure structure.
+ */
+void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
+{
+    uint32_t configValue = 0;
+    uint8_t i            = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the flexspi clock */
+    (void)CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET
+    /* Reset the FLEXSPI module */
+    RESET_PeripheralReset(s_flexspiResets[FLEXSPI_GetInstance(base)]);
+#endif
+
+    /* Reset peripheral before configuring it. */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+    FLEXSPI_SoftwareReset(base);
+
+    /* Configure MCR0 configuration items. */
+    configValue = FLEXSPI_MCR0_RXCLKSRC(config->rxSampleClock) | FLEXSPI_MCR0_DOZEEN(config->enableDoze) |
+                  FLEXSPI_MCR0_IPGRANTWAIT(config->ipGrantTimeoutCycle) |
+                  FLEXSPI_MCR0_AHBGRANTWAIT(config->ahbConfig.ahbGrantTimeoutCycle) |
+                  FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) |
+                  FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) |
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+                  FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) |
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
+                  FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) |
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+                  FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) |
+#endif
+                  FLEXSPI_MCR0_MDIS_MASK;
+    base->MCR0 = configValue;
+
+    /* Configure MCR1 configurations. */
+    configValue =
+        FLEXSPI_MCR1_SEQWAIT(config->seqTimeoutCycle) | FLEXSPI_MCR1_AHBBUSWAIT(config->ahbConfig.ahbBusTimeoutCycle);
+    base->MCR1 = configValue;
+
+    /* Configure MCR2 configurations. */
+    configValue = base->MCR2;
+    configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK |
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+                     FLEXSPI_MCR2_SCKBDIFFOPT_MASK |
+#endif
+                     FLEXSPI_MCR2_SAMEDEVICEEN_MASK | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
+    configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) |
+#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB) && FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB
+                   FLEXSPI_MCR2_RXCLKSRC_B(config->rxSampleClockPortB) |
+#endif
+#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF
+                   FLEXSPI_MCR2_RX_CLK_SRC_DIFF(config->rxSampleClockDiff) |
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+                   FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) |
+#endif
+                   FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) |
+                   FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt);
+
+    base->MCR2 = configValue;
+
+    /* Configure AHB control items. */
+    configValue = base->AHBCR;
+    configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK |
+                     FLEXSPI_AHBCR_CACHABLEEN_MASK);
+    configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) |
+                   FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) |
+                   FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) |
+                   FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable);
+    base->AHBCR = configValue;
+
+    /* Configure AHB rx buffers. */
+    for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
+    {
+        configValue = base->AHBRXBUFCR0[i];
+
+        configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK |
+                         FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK);
+        configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) |
+                       FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) |
+                       FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) |
+                       FLEXSPI_AHBRXBUFCR0_BUFSZ((uint32_t)config->ahbConfig.buffer[i].bufferSize / 8U);
+        base->AHBRXBUFCR0[i] = configValue;
+    }
+
+    /* Configure IP Fifo watermarks. */
+    base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK;
+    base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK((uint32_t)config->rxWatermark / 8U - 1U);
+    base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK;
+    base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK((uint32_t)config->txWatermark / 8U - 1U);
+
+    /* Reset flash size on all ports */
+    for (i = 0; i < (uint32_t)kFLEXSPI_PortCount; i++)
+    {
+        base->FLSHCR0[i] = 0;
+    }
+}
+
+/*!
+ * brief Gets default settings for FLEXSPI.
+ *
+ * param config FLEXSPI configuration structure.
+ */
+void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    FLEXSPI_Memset(config, 0, sizeof(*config));
+
+    config->rxSampleClock        = kFLEXSPI_ReadSampleClkLoopbackInternally;
+    config->enableSckFreeRunning = false;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+    config->enableCombination = false;
+#endif
+    config->enableDoze            = true;
+    config->enableHalfSpeedAccess = false;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+    config->enableSckBDiffOpt = false;
+#endif
+    config->enableSameConfigForAll = false;
+    config->seqTimeoutCycle        = 0xFFFFU;
+    config->ipGrantTimeoutCycle    = 0xFFU;
+    config->txWatermark            = 8;
+    config->rxWatermark            = 8;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
+    config->ahbConfig.enableAHBWriteIpTxFifo = false;
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+    config->ahbConfig.enableAHBWriteIpRxFifo = false;
+#endif
+    config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU;
+    config->ahbConfig.ahbBusTimeoutCycle   = 0xFFFFU;
+    config->ahbConfig.resumeWaitCycle      = 0x20U;
+    FLEXSPI_Memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
+    /* Use invalid master ID 0xF and buffer size 0 for the first several buffers. */
+    for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); i++)
+    {
+        config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */
+        config->ahbConfig.buffer[i].masterIndex = 0xFU; /* Invalid master index which is not used, so will never hit. */
+        config->ahbConfig.buffer[i].bufferSize =
+            0; /* Default buffer size 0 for buffer0 to buffer(FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 3U)*/
+    }
+
+    for (uint8_t i = ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U);
+         i < (uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
+    {
+        config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */
+        config->ahbConfig.buffer[i].bufferSize     = 256U; /* Default buffer size 256 bytes. */
+    }
+    config->ahbConfig.enableClearAHBBufferOpt = false;
+    config->ahbConfig.enableReadAddressOpt    = false;
+    config->ahbConfig.enableAHBPrefetch       = false;
+    config->ahbConfig.enableAHBBufferable     = false;
+    config->ahbConfig.enableAHBCachable       = false;
+}
+
+/*!
+ * brief Deinitializes the FLEXSPI module.
+ *
+ * Clears the FLEXSPI state and  FLEXSPI module registers.
+ * param base FLEXSPI peripheral base address.
+ */
+void FLEXSPI_Deinit(FLEXSPI_Type *base)
+{
+    /* Reset peripheral. */
+    FLEXSPI_SoftwareReset(base);
+}
+
+/*!
+ * brief Update FLEXSPI DLL value depending on currently flexspi root clock.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config Flash configuration parameters.
+ * param port FLEXSPI Operation port.
+ */
+void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
+{
+    uint32_t configValue = 0;
+    uint32_t statusValue = 0;
+    uint8_t index        = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */
+
+    /* Wait for bus to be idle before changing flash configuration. */
+    while (!FLEXSPI_GetBusIdleStatus(base))
+    {
+    }
+
+    /* Configure DLL. */
+    configValue        = FLEXSPI_CalculateDll(base, config);
+    base->DLLCR[index] = configValue;
+
+    /* Exit stop mode. */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+    if (index == 0U)
+    {
+        statusValue =
+            ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked);
+    }
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
+    else
+    {
+        statusValue =
+            ((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked);
+    }
+#endif
+    if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK))
+    {
+#if defined(FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426) && (FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426)
+        if (config->isFroClockSource == false)
+#endif
+        {
+            /* Wait slave delay line locked and slave reference delay line locked. */
+            while ((base->STS2 & statusValue) != statusValue)
+            {
+            }
+        }
+
+        /* Wait at least 100 NOPs*/
+        for (uint8_t delay = 100U; delay > 0U; delay--)
+        {
+            __NOP();
+        }
+    }
+}
+
+/*!
+ * brief Configures the connected device parameter.
+ *
+ * This function configures the connected device relevant parameters, such as the size, command, and so on.
+ * The flash configuration value cannot have a default value. The user needs to configure it according to the
+ * connected device.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config Flash configuration parameters.
+ * param port FLEXSPI Operation port.
+ */
+void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
+{
+    uint32_t configValue = 0;
+    uint8_t index        = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */
+
+    /* Wait for bus to be idle before changing flash configuration. */
+    while (!FLEXSPI_GetBusIdleStatus(base))
+    {
+    }
+
+    /* Configure flash size and address shift. */
+#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT) && (FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT)
+    base->FLSHCR0[port] = config->flashSize | FLEXSPI_FLSHCR0_ADDRSHIFT(config->addressShift);
+#else
+    base->FLSHCR0[port] = config->flashSize;
+#endif /* FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT */
+
+    /* Configure flash parameters. */
+    base->FLSHCR1[port] = FLEXSPI_FLSHCR1_CSINTERVAL(config->CSInterval) |
+                          FLEXSPI_FLSHCR1_CSINTERVALUNIT(config->CSIntervalUnit) |
+                          FLEXSPI_FLSHCR1_TCSH(config->CSHoldTime) | FLEXSPI_FLSHCR1_TCSS(config->CSSetupTime) |
+                          FLEXSPI_FLSHCR1_CAS(config->columnspace) | FLEXSPI_FLSHCR1_WA(config->enableWordAddress);
+
+    /* Configure AHB operation items. */
+    configValue = base->FLSHCR2[port];
+
+    configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK |
+                     FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_ARDSEQID_MASK);
+
+    configValue |=
+        FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval);
+
+    if (config->AWRSeqNumber > 0U)
+    {
+        configValue |= FLEXSPI_FLSHCR2_AWRSEQID((uint32_t)config->AWRSeqIndex) |
+                       FLEXSPI_FLSHCR2_AWRSEQNUM((uint32_t)config->AWRSeqNumber - 1U);
+    }
+
+    if (config->ARDSeqNumber > 0U)
+    {
+        configValue |= FLEXSPI_FLSHCR2_ARDSEQID((uint32_t)config->ARDSeqIndex) |
+                       FLEXSPI_FLSHCR2_ARDSEQNUM((uint32_t)config->ARDSeqNumber - 1U);
+    }
+
+    base->FLSHCR2[port] = configValue;
+
+    /* Configure DLL. */
+    FLEXSPI_UpdateDllValue(base, config, port);
+
+    /* Step into stop mode. */
+    base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+
+    /* Configure write mask. */
+    if (config->enableWriteMask)
+    {
+        base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK;
+    }
+    else
+    {
+        base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK;
+    }
+
+    if (index == 0U) /*PortA*/
+    {
+        base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK;
+        base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask);
+    }
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB))
+    else
+    {
+        base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK;
+        base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask);
+    }
+#endif
+
+    /* Exit stop mode. */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    /* Wait for bus to be idle before use it access to external flash. */
+    while (!FLEXSPI_GetBusIdleStatus(base))
+    {
+    }
+}
+
+/*! brief Updates the LUT table.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param index From which index start to update. It could be any index of the LUT table, which
+ * also allows user to update command content inside a command. Each command consists of up to
+ * 8 instructions and occupy 4*32-bit memory.
+ * param cmd Command sequence array.
+ * param count Number of sequences.
+ */
+void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
+{
+    assert(index < 64U);
+
+    uint32_t i = 0;
+    volatile uint32_t *lutBase;
+
+    /* Wait for bus to be idle before changing flash configuration. */
+    while (!FLEXSPI_GetBusIdleStatus(base))
+    {
+    }
+
+    /* Unlock LUT for update. */
+#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
+    base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
+#endif
+    base->LUTCR = 0x02;
+
+    lutBase = &base->LUT[index];
+    for (i = 0; i < count; i++)
+    {
+        *lutBase++ = *cmd++;
+    }
+
+    /* Lock LUT. */
+#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
+    base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
+#endif
+    base->LUTCR = 0x01;
+}
+
+/*! brief Update read sample clock source
+ *
+ * param base FLEXSPI peripheral base address.
+ * param clockSource clockSource of type #flexspi_read_sample_clock_t
+ */
+void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)
+{
+    uint32_t mcr0Val;
+
+    /* Wait for bus to be idle before changing flash configuration. */
+    while (!FLEXSPI_GetBusIdleStatus(base))
+    {
+    }
+
+    mcr0Val = base->MCR0;
+    mcr0Val &= ~FLEXSPI_MCR0_RXCLKSRC_MASK;
+    mcr0Val |= FLEXSPI_MCR0_RXCLKSRC(clockSource);
+    base->MCR0 = mcr0Val;
+
+    /* Reset peripheral. */
+    FLEXSPI_SoftwareReset(base);
+}
+
+/*!
+ * brief Sends a buffer of data bytes using blocking method.
+ * note This function blocks via polling until all bytes have been sent.
+ * param base FLEXSPI peripheral base address
+ * param buffer The data bytes to send
+ * param size The number of data bytes to send
+ * retval kStatus_Success write success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
+{
+    uint32_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U;
+    uint32_t status;
+    status_t result = kStatus_Success;
+    uint32_t i      = 0;
+
+    /* Send data buffer */
+    while (0U != size)
+    {
+        /* Wait until there is room in the fifo. This also checks for errors. */
+        while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag))
+        {
+        }
+
+        result = FLEXSPI_CheckAndClearError(base, status);
+
+        if (kStatus_Success != result)
+        {
+            return result;
+        }
+
+        /* Write watermark level data into tx fifo . */
+        if (size >= 8U * txWatermark)
+        {
+            for (i = 0U; i < 2U * txWatermark; i++)
+            {
+                base->TFDR[i] = *(uint32_t *)(void *)buffer;
+                buffer += 4U;
+            }
+
+            size = size - 8U * txWatermark;
+        }
+        else
+        {
+            /* Write word aligned data into tx fifo. */
+            for (i = 0U; i < (size / 4U); i++)
+            {
+                base->TFDR[i] = *(uint32_t *)(void *)buffer;
+                buffer += 4U;
+            }
+
+            /* Adjust size by the amount processed. */
+            size -= 4U * i;
+
+            /* Write word un-aligned data into tx fifo. */
+            if (0x00U != size)
+            {
+                uint32_t tempVal = 0x00U;
+
+                for (uint32_t j = 0U; j < size; j++)
+                {
+                    tempVal |= ((uint32_t)*buffer++ << (8U * j));
+                }
+
+                base->TFDR[i] = tempVal;
+            }
+
+            size = 0U;
+        }
+
+        /* Push a watermark level data into IP TX FIFO. */
+        base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
+    }
+
+    return result;
+}
+
+/*!
+ * brief Receives a buffer of data bytes using a blocking method.
+ * note This function blocks via polling until all bytes have been sent.
+ * param base FLEXSPI peripheral base address
+ * param buffer The data bytes to send
+ * param size The number of data bytes to receive
+ * retval kStatus_Success read success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
+{
+    uint32_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U;
+    uint32_t status;
+    status_t result = kStatus_Success;
+    uint32_t i      = 0;
+    bool isReturn   = false;
+
+    /* Send data buffer */
+    while (0U != size)
+    {
+        if (size >= 8U * rxWatermark)
+        {
+            /* Wait until there is room in the fifo. This also checks for errors. */
+            while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag))
+            {
+                result = FLEXSPI_CheckAndClearError(base, status);
+
+                if (kStatus_Success != result)
+                {
+                    isReturn = true;
+                    break;
+                }
+            }
+        }
+        else
+        {
+            /* Wait fill level. This also checks for errors. */
+            while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U))
+            {
+                result = FLEXSPI_CheckAndClearError(base, base->INTR);
+
+                if (kStatus_Success != result)
+                {
+                    isReturn = true;
+                    break;
+                }
+            }
+        }
+
+        if (isReturn)
+        {
+            break;
+        }
+
+        result = FLEXSPI_CheckAndClearError(base, base->INTR);
+
+        if (kStatus_Success != result)
+        {
+            break;
+        }
+
+        /* Read watermark level data from rx fifo. */
+        if (size >= 8U * rxWatermark)
+        {
+            for (i = 0U; i < 2U * rxWatermark; i++)
+            {
+                *(uint32_t *)(void *)buffer = base->RFDR[i];
+                buffer += 4U;
+            }
+
+            size = size - 8U * rxWatermark;
+        }
+        else
+        {
+            /* Read word aligned data from rx fifo. */
+            for (i = 0U; i < (size / 4U); i++)
+            {
+                *(uint32_t *)(void *)buffer = base->RFDR[i];
+                buffer += 4U;
+            }
+
+            /* Adjust size by the amount processed. */
+            size -= 4U * i;
+
+            /* Read word un-aligned data from rx fifo. */
+            if (0x00U != size)
+            {
+                uint32_t tempVal = base->RFDR[i];
+
+                for (i = 0U; i < size; i++)
+                {
+                    *buffer++ = ((uint8_t)(tempVal >> (8U * i)) & 0xFFU);
+                }
+            }
+
+            size = 0;
+        }
+
+        /* Pop out a watermark level datas from IP RX FIFO. */
+        base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
+    }
+
+    return result;
+}
+
+/*!
+ * brief Execute command to transfer a buffer data bytes using a blocking method.
+ * param base FLEXSPI peripheral base address
+ * param xfer pointer to the transfer structure.
+ * retval kStatus_Success command transfer success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
+{
+    uint32_t configValue = 0;
+    status_t result      = kStatus_Success;
+
+    /* Clear sequence pointer before sending data to external devices. */
+    base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
+
+    /* Clear former pending status before start this transfer. */
+    base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
+                 FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK;
+
+    /* Configure base address. */
+    base->IPCR0 = xfer->deviceAddress;
+
+    /* Reset fifos. */
+    base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
+    base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
+
+    /* Configure data size. */
+    if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config))
+    {
+        configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize);
+    }
+
+    /* Configure sequence ID. */
+    configValue |=
+        FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U);
+    base->IPCR1 = configValue;
+
+    /* Start Transfer. */
+    base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
+
+    if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config))
+    {
+        result = FLEXSPI_WriteBlocking(base, (uint8_t *)xfer->data, xfer->dataSize);
+    }
+    else if (xfer->cmdType == kFLEXSPI_Read)
+    {
+        result = FLEXSPI_ReadBlocking(base, (uint8_t *)xfer->data, xfer->dataSize);
+    }
+    else
+    {
+        /* Empty else. */
+    }
+
+    /* Wait until the IP command execution finishes */
+    while (0UL == (base->INTR & FLEXSPI_INTR_IPCMDDONE_MASK))
+    {
+    }
+
+    /* Unless there is an error status already set, capture the latest one */
+    if (result == kStatus_Success)
+    {
+        result = FLEXSPI_CheckAndClearError(base, base->INTR);
+    }
+
+    return result;
+}
+
+/*!
+ * brief Initializes the FLEXSPI handle which is used in transactional functions.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure to store the transfer state.
+ * param callback pointer to user callback function.
+ * param userData user parameter passed to the callback function.
+ */
+void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
+                                  flexspi_handle_t *handle,
+                                  flexspi_transfer_callback_t callback,
+                                  void *userData)
+{
+    assert(NULL != handle);
+
+    uint32_t instance = FLEXSPI_GetInstance(base);
+
+    /* Zero handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData           = userData;
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+    /* Save the context in global variables to support the double weak mechanism. */
+    s_flexspiHandle[instance] = handle;
+    s_flexspiIsr              = FLEXSPI_TransferHandleIRQ;
+#endif
+
+    /* Enable NVIC interrupt. */
+    (void)EnableIRQ(s_flexspiIrqs[instance]);
+}
+
+/*!
+ * brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
+ *
+ * note Calling the API returns immediately after transfer initiates. The user needs
+ * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
+ * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
+ * FLEXSPI could not read data properly.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * param xfer pointer to flexspi_transfer_t structure.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
+ */
+status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
+{
+    uint32_t configValue = 0;
+    status_t result      = kStatus_Success;
+
+    assert(NULL != handle);
+    assert(NULL != xfer);
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (handle->state != (uint32_t)kFLEXSPI_Idle)
+    {
+        result = kStatus_FLEXSPI_Busy;
+    }
+    else
+    {
+        handle->data              = (uint8_t *)xfer->data;
+        handle->dataSize          = xfer->dataSize;
+        handle->transferTotalSize = xfer->dataSize;
+        handle->state = (xfer->cmdType == kFLEXSPI_Read) ? (uint32_t)kFLEXSPI_BusyRead : (uint32_t)kFLEXSPI_BusyWrite;
+
+        /* Clear sequence pointer before sending data to external devices. */
+        base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
+
+        /* Clear former pending status before start this transfer. */
+        base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
+                     FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK;
+
+        /* Configure base address. */
+        base->IPCR0 = xfer->deviceAddress;
+
+        /* Reset fifos. */
+        base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
+        base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
+
+        /* Configure data size. */
+        if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write))
+        {
+            configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize);
+        }
+
+        /* Configure sequence ID. */
+        configValue |=
+            FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U);
+        base->IPCR1 = configValue;
+
+        /* Start Transfer. */
+        base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
+
+        if (handle->state == (uint32_t)kFLEXSPI_BusyRead)
+        {
+            FLEXSPI_EnableInterrupts(base, (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
+                                               (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag |
+                                               (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag |
+                                               (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag |
+                                               (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag);
+        }
+        else
+        {
+            FLEXSPI_EnableInterrupts(
+                base, (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag | (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag |
+                          (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag | (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag |
+                          (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag);
+        }
+    }
+
+    return result;
+}
+
+/*!
+ * brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
+{
+    assert(NULL != handle);
+
+    status_t result = kStatus_Success;
+
+    if (handle->state == (uint32_t)kFLEXSPI_Idle)
+    {
+        result = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferTotalSize - handle->dataSize;
+    }
+
+    return result;
+}
+
+/*!
+ * brief Aborts an interrupt non-blocking transfer early.
+ *
+ * note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state
+ */
+void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    FLEXSPI_DisableInterrupts(base, (uint32_t)kIrqFlags);
+    handle->state = (uint32_t)kFLEXSPI_Idle;
+}
+
+/*!
+ * brief Master interrupt handler.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure.
+ */
+void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
+{
+    uint32_t status;
+    status_t result;
+    uint32_t intEnableStatus;
+    uint32_t txWatermark;
+    uint32_t rxWatermark;
+    uint32_t i = 0;
+
+    status          = base->INTR;
+    intEnableStatus = base->INTEN;
+
+    /* Check if interrupt is enabled and status is alerted. */
+    if ((status & intEnableStatus) != 0U)
+    {
+        result = FLEXSPI_CheckAndClearError(base, status);
+
+        if ((result != kStatus_Success) && (handle->completionCallback != NULL))
+        {
+            FLEXSPI_TransferAbort(base, handle);
+            if (NULL != handle->completionCallback)
+            {
+                handle->completionCallback(base, handle, result, handle->userData);
+            }
+        }
+        else
+        {
+            if ((0U != (status & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) &&
+                (handle->state == (uint32_t)kFLEXSPI_BusyRead))
+            {
+                rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U;
+
+                /* Read watermark level data from rx fifo . */
+                if (handle->dataSize >= 8U * rxWatermark)
+                {
+                    /* Read watermark level data from rx fifo . */
+                    for (i = 0U; i < 2U * rxWatermark; i++)
+                    {
+                        *(uint32_t *)(void *)handle->data = base->RFDR[i];
+                        handle->data += 4U;
+                    }
+
+                    handle->dataSize = handle->dataSize - 8U * rxWatermark;
+                }
+                else
+                {
+                    /* Read word aligned data from rx fifo. */
+                    for (i = 0U; i < (handle->dataSize / 4U); i++)
+                    {
+                        *(uint32_t *)(void *)handle->data = base->RFDR[i];
+                        handle->data += 4U;
+                    }
+
+                    /* Adjust size by the amount processed. */
+                    handle->dataSize -= (size_t)4U * i;
+
+                    /* Read word un-aligned data from rx fifo. */
+                    if (0x00U != handle->dataSize)
+                    {
+                        uint32_t tempVal = base->RFDR[i];
+
+                        for (i = 0U; i < handle->dataSize; i++)
+                        {
+                            *handle->data++ = ((uint8_t)(tempVal >> (8U * i)) & 0xFFU);
+                        }
+                    }
+
+                    handle->dataSize = 0;
+                }
+                /* Pop out a watermark level data from IP RX FIFO. */
+                base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
+            }
+
+            if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag))
+            {
+                base->INTR = (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag;
+
+                FLEXSPI_TransferAbort(base, handle);
+
+                if (NULL != handle->completionCallback)
+                {
+                    handle->completionCallback(base, handle, kStatus_Success, handle->userData);
+                }
+            }
+
+            /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */
+            if ((0U != (status & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) &&
+                (handle->state == (uint32_t)kFLEXSPI_BusyWrite))
+            {
+                if (0U != handle->dataSize)
+                {
+                    txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U;
+                    /* Write watermark level data into tx fifo . */
+                    if (handle->dataSize >= 8U * txWatermark)
+                    {
+                        for (i = 0; i < 2U * txWatermark; i++)
+                        {
+                            base->TFDR[i] = *(uint32_t *)(void *)handle->data;
+                            handle->data += 4U;
+                        }
+
+                        handle->dataSize = handle->dataSize - 8U * txWatermark;
+                    }
+                    else
+                    {
+                        /* Write word aligned data into tx fifo. */
+                        for (i = 0U; i < (handle->dataSize / 4U); i++)
+                        {
+                            base->TFDR[i] = *(uint32_t *)(void *)handle->data;
+                            handle->data += 4U;
+                        }
+
+                        /* Adjust size by the amount processed. */
+                        handle->dataSize -= (size_t)4U * i;
+
+                        /* Write word un-aligned data into tx fifo. */
+                        if (0x00U != handle->dataSize)
+                        {
+                            uint32_t tempVal = 0x00U;
+
+                            for (uint32_t j = 0U; j < handle->dataSize; j++)
+                            {
+                                tempVal |= ((uint32_t)*handle->data++ << (8U * j));
+                            }
+
+                            base->TFDR[i] = tempVal;
+                        }
+
+                        handle->dataSize = 0;
+                    }
+
+                    /* Push a watermark level data into IP TX FIFO. */
+                    base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
+                }
+            }
+            else
+            {
+                /* Empty else */
+            }
+        }
+    }
+    else
+    {
+        /* Empty else */
+    }
+}
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#if defined(FLEXSPI)
+void FLEXSPI_DriverIRQHandler(void);
+void FLEXSPI_DriverIRQHandler(void)
+{
+    s_flexspiIsr(FLEXSPI, s_flexspiHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXSPI0)
+void FLEXSPI0_DriverIRQHandler(void);
+void FLEXSPI0_DriverIRQHandler(void)
+{
+    s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#if defined(FLEXSPI1)
+void FLEXSPI1_DriverIRQHandler(void);
+void FLEXSPI1_DriverIRQHandler(void)
+{
+    s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#if defined(FLEXSPI2)
+void FLEXSPI2_DriverIRQHandler(void);
+void FLEXSPI2_DriverIRQHandler(void)
+{
+    s_flexspiIsr(FLEXSPI2, s_flexspiHandle[2]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(LSIO__FLEXSPI0)
+void LSIO_OCTASPI0_INT_DriverIRQHandler(void);
+void LSIO_OCTASPI0_INT_DriverIRQHandler(void)
+{
+    s_flexspiIsr(LSIO__FLEXSPI0, s_flexspiHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#if defined(LSIO__FLEXSPI1)
+void LSIO_OCTASPI1_INT_DriverIRQHandler(void);
+void LSIO_OCTASPI1_INT_DriverIRQHandler(void)
+{
+    s_flexspiIsr(LSIO__FLEXSPI1, s_flexspiHandle[1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1
+
+void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void);
+void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void)
+{
+    /* If handle is registered, treat the transfer function is enabled. */
+    if (NULL != s_flexspiHandle[0])
+    {
+        s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]);
+    }
+    if (NULL != s_flexspiHandle[1])
+    {
+        s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]);
+    }
+}
+#endif
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexspi.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexspi.h
new file mode 100644
index 0000000000..6a36babc9c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_flexspi.h
@@ -0,0 +1,902 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_FLEXSPI_H_
+#define FSL_FLEXSPI_H_
+
+#include <stddef.h>
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexspi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FLEXSPI driver version. */
+#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
+/*! @} */
+
+#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
+
+/*! @brief Formula to form FLEXSPI instructions in LUT table. */
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+/*! @brief Status structure of FLEXSPI.*/
+enum
+{
+    kStatus_FLEXSPI_Busy                     = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */
+    kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout
+                                                                            error occurred during FLEXSPI transfer. */
+    kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2),   /*!< IP command Sequence execution
+                                                                     timeout error occurred during FLEXSPI transfer. */
+    kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3),    /*!< IP command grant timeout error
+                                                                                    occurred during FLEXSPI transfer. */
+};
+
+/*! @brief CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command. */
+enum
+{
+    kFLEXSPI_Command_STOP           = 0x00U, /*!< Stop execution, deassert CS. */
+    kFLEXSPI_Command_SDR            = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
+    kFLEXSPI_Command_RADDR_SDR      = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
+    kFLEXSPI_Command_CADDR_SDR      = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE1_SDR      = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE2_SDR      = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE4_SDR      = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE8_SDR      = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_WRITE_SDR      = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
+    kFLEXSPI_Command_READ_SDR       = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
+    kFLEXSPI_Command_LEARN_SDR      = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
+    kFLEXSPI_Command_DATSZ_SDR      = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
+    kFLEXSPI_Command_DUMMY_SDR      = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
+    kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
+                                                  dummy cycles decided by RWDS. */
+    kFLEXSPI_Command_DDR            = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
+    kFLEXSPI_Command_RADDR_DDR      = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
+    kFLEXSPI_Command_CADDR_DDR      = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE1_DDR      = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE2_DDR      = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE4_DDR      = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE8_DDR      = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_WRITE_DDR      = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
+    kFLEXSPI_Command_READ_DDR       = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
+    kFLEXSPI_Command_LEARN_DDR      = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
+    kFLEXSPI_Command_DATSZ_DDR      = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
+    kFLEXSPI_Command_DUMMY_DDR      = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
+    kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
+                                               dummy cycles decided by RWDS. */
+    kFLEXSPI_Command_JUMP_ON_CS = 0x1FU,     /*!< Stop execution, deassert CS and save operand[7:0] as the
+                                               instruction start pointer for next sequence */
+};
+
+/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */
+typedef enum _flexspi_pad
+{
+    kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */
+    kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */
+    kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */
+    kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */
+} flexspi_pad_t;
+
+/*! @brief FLEXSPI interrupt status flags.*/
+typedef enum _flexspi_flags
+{
+    kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */
+#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN
+    kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */
+#else
+    kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */
+#endif
+    kFLEXSPI_SckStoppedBecauseTxEmptyFlag =
+        FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command
+                                               sequence because Async TX FIFO empty. */
+    kFLEXSPI_SckStoppedBecauseRxFullFlag =
+        FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command
+                                               sequence because Async RX FIFO full. */
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
+    kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */
+#endif
+    kFLEXSPI_IpTxFifoWatermarkEmptyFlag     = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */
+    kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */
+    kFLEXSPI_AhbCommandSequenceErrorFlag =
+        FLEXSPI_INTEN_AHBCMDERREN_MASK,                                  /*!< AHB triggered Command Sequences Error. */
+    kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */
+    kFLEXSPI_AhbCommandGrantTimeoutFlag =
+        FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */
+    kFLEXSPI_IpCommandGrantTimeoutFlag =
+        FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */
+    kFLEXSPI_IpCommandExecutionDoneFlag =
+        FLEXSPI_INTEN_IPCMDDONEEN_MASK,  /*!< IP triggered Command Sequences Execution finished. */
+    kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */
+} flexspi_flags_t;
+
+/*! @brief FLEXSPI sample clock source selection for Flash Reading.*/
+typedef enum _flexspi_read_sample_clock
+{
+    kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U,      /*!< Dummy Read strobe generated by FlexSPI Controller
+                                                               and loopback internally. */
+    kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U,      /*!< Dummy Read strobe generated by FlexSPI Controller
+                                                               and loopback from DQS pad. */
+    kFLEXSPI_ReadSampleClkLoopbackFromSckPad      = 0x2U, /*!< SCK output clock and loopback from SCK pad. */
+    kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */
+} flexspi_read_sample_clock_t;
+
+/*! @brief FLEXSPI interval unit for flash device select.*/
+typedef enum _flexspi_cs_interval_cycle_unit
+{
+    kFLEXSPI_CsIntervalUnit1SckCycle   = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
+    kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */
+} flexspi_cs_interval_cycle_unit_t;
+
+/*! @brief FLEXSPI AHB wait interval unit for writing.*/
+typedef enum _flexspi_ahb_write_wait_unit
+{
+    kFLEXSPI_AhbWriteWaitUnit2AhbCycle     = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit8AhbCycle     = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit32AhbCycle    = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit128AhbCycle   = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit512AhbCycle   = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit2048AhbCycle  = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit8192AhbCycle  = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */
+} flexspi_ahb_write_wait_unit_t;
+
+/*! @brief Error Code when IP command Error detected.*/
+typedef enum _flexspi_ip_error_code
+{
+    kFLEXSPI_IpCmdErrorNoError               = 0x0U,    /*!< No error. */
+    kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd       = 0x2U,    /*!< IP command with JMP_ON_CS instruction used. */
+    kFLEXSPI_IpCmdErrorUnknownOpCode         = 0x3U,    /*!< Unknown instruction opcode in the sequence. */
+    kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U,    /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR
+                                                             used in DDR sequence. */
+    kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U,    /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
+                                                             used in SDR sequence. */
+    kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U,           /*!< Flash access start address exceed the whole
+                                                            flash address range (A1/A2/B1/B2). */
+    kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */
+    kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss     = 0xFU, /*!< Flash boundary crossed. */
+} flexspi_ip_error_code_t;
+
+/*! @brief Error Code when AHB command Error detected.*/
+typedef enum _flexspi_ahb_error_code
+{
+    kFLEXSPI_AhbCmdErrorNoError            = 0x0U,    /*!< No error. */
+    kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U,    /*!< AHB Write command with JMP_ON_CS instruction
+                                                           used in the sequence. */
+    kFLEXSPI_AhbCmdErrorUnknownOpCode         = 0x3U, /*!< Unknown instruction opcode in the sequence. */
+    kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used
+                                                           in DDR sequence. */
+    kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
+                                                           used in SDR sequence. */
+    kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U,   /*!< Sequence execution timeout. */
+} flexspi_ahb_error_code_t;
+
+/*! @brief FLEXSPI operation port select.*/
+typedef enum _flexspi_port
+{
+    kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
+    kFLEXSPI_PortA2,        /*!< Access flash on A2 port. */
+#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB))
+    kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
+    kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
+#endif
+    kFLEXSPI_PortCount
+} flexspi_port_t;
+
+/*! @brief Trigger source of current command sequence granted by arbitrator.*/
+typedef enum _flexspi_arb_command_source
+{
+    kFLEXSPI_AhbReadCommand   = 0x0U,
+    kFLEXSPI_AhbWriteCommand  = 0x1U,
+    kFLEXSPI_IpCommand        = 0x2U,
+    kFLEXSPI_SuspendedCommand = 0x3U,
+} flexspi_arb_command_source_t;
+
+/*! @brief Command type. */
+typedef enum _flexspi_command_type
+{
+    kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */
+    kFLEXSPI_Config,  /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */
+    kFLEXSPI_Read,    /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
+    kFLEXSPI_Write,   /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
+} flexspi_command_type_t;
+
+typedef struct _flexspi_ahbBuffer_config
+{
+    uint8_t priority;    /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */
+    uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */
+    uint16_t bufferSize; /*!< AHB buffer size in byte. */
+    bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows
+                          prefetch disable/enable separately for each master. */
+} flexspi_ahbBuffer_config_t;
+
+/*! @brief FLEXSPI configuration structure. */
+typedef struct _flexspi_config
+{
+    flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */
+    bool enableSckFreeRunning;                 /*!< Enable/disable SCK output free-running. */
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+    bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins
+                            (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */
+#endif
+    bool enableDoze;            /*!< Enable/disable doze mode support. */
+    bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
+                                 speed commands. */
+#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB) && FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB
+    flexspi_read_sample_clock_t rxSampleClockPortB; /*!< Sample Clock source_b selection for Flash Reading. */
+#endif
+#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF
+    bool rxSampleClockDiff; /*!< Sample Clock source or source_b selection for Flash Reading. */
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+    bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
+                             output, when enable, Port B flash access is not available. */
+#endif
+    bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
+                                  when enabled, same configuration in FLASHA1CRx is applied to all. */
+    uint16_t seqTimeoutCycle;    /*!< Timeout wait cycle for command sequence execution,
+                                 timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */
+    uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after
+                                  ipGrantTimeoutCycle*1024 AHB clock cycles. */
+    uint8_t txWatermark;         /*!< FLEXSPI IP transmit watermark value. */
+    uint8_t rxWatermark;         /*!< FLEXSPI receive watermark value. */
+    struct
+    {
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
+        bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+        bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */
+#endif
+        uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant,
+                                       timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */
+        uint16_t ahbBusTimeoutCycle;  /*!< Timeout wait cycle for AHB read/write access,
+                                      timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */
+        uint8_t resumeWaitCycle;      /*!< Wait cycle for idle state before suspended command sequence
+                                       resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */
+        flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
+        bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer
+                                       when FLEXSPI returns STOP mode ACK. */
+        bool enableReadAddressOpt;    /*!< Enable/disable remove AHB read burst start address alignment limitation.
+                                       when enable, there is no AHB read burst start address alignment limitation. */
+        bool enableAHBPrefetch;       /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI
+                                       will fetch more data than current AHB burst. */
+        bool enableAHBBufferable;     /*!< Enable/disable AHB bufferable write access support, when enabled,
+                                       FLEXSPI return before waiting for command execution finished. */
+        bool enableAHBCachable;       /*!< Enable AHB bus cachable read access support. */
+    } ahbConfig;
+} flexspi_config_t;
+
+/*! @brief External device configuration items. */
+typedef struct _flexspi_device_config
+{
+    uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */
+    bool isSck2Enabled;      /*!< FLEXSPI use SCK2. */
+    uint32_t flashSize;      /*!< Flash size in KByte. */
+#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT) && (FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT)
+    bool addressShift;                               /*!< Address shift. */
+#endif                                               /* FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT */
+    flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */
+    uint16_t CSInterval;                             /*!< CS line assert interval, multiply CS interval unit to
+                                                      get the CS line assert interval cycles. */
+    uint8_t CSHoldTime;                              /*!< CS line hold time. */
+    uint8_t CSSetupTime;                             /*!< CS line setup time. */
+    uint8_t dataValidTime;                           /*!< Data valid time for external device. */
+    uint8_t columnspace;                             /*!< Column space size. */
+    bool enableWordAddress;                          /*!< If enable word address.*/
+    uint8_t AWRSeqIndex;                             /*!< Sequence ID for AHB write command. */
+    uint8_t AWRSeqNumber;                            /*!< Sequence number for AHB write command. */
+    uint8_t ARDSeqIndex;                             /*!< Sequence ID for AHB read command. */
+    uint8_t ARDSeqNumber;                            /*!< Sequence number for AHB read command. */
+    flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit;  /*!< AHB write wait unit. */
+    uint16_t AHBWriteWaitInterval;                   /*!< AHB write wait interval, multiply AHB write interval
+                                                      unit to get the AHB write wait cycles. */
+    bool enableWriteMask;                            /*!< Enable/Disable FLEXSPI drive DQS pin as write mask
+                                                      when writing to external device. */
+#if defined(FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426) && (FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426)
+    bool isFroClockSource; /*!< Is FRO clock source or not. */
+#endif
+} flexspi_device_config_t;
+
+/*! @brief Transfer structure for FLEXSPI. */
+typedef struct _flexspi_transfer
+{
+    uint32_t deviceAddress;         /*!< Operation device address. */
+    flexspi_port_t port;            /*!< Operation port. */
+    flexspi_command_type_t cmdType; /*!< Execution command type. */
+    uint8_t seqIndex;               /*!< Sequence ID for command. */
+    uint8_t SeqNumber;              /*!< Sequence number for command. */
+    uint32_t *data;                 /*!< Data buffer. */
+    size_t dataSize;                /*!< Data size in bytes. */
+} flexspi_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexspi_handle flexspi_handle_t;
+
+/*! @brief FLEXSPI transfer callback function. */
+typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base,
+                                            flexspi_handle_t *handle,
+                                            status_t status,
+                                            void *userData);
+
+/*! @brief Transfer handle structure for FLEXSPI. */
+struct _flexspi_handle
+{
+    uint32_t state;                                 /*!< Internal state for FLEXSPI transfer */
+    uint8_t *data;                                  /*!< Data buffer. */
+    size_t dataSize;                                /*!< Remaining Data size in bytes. */
+    size_t transferTotalSize;                       /*!< Total Data size in bytes. */
+    flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */
+    void *userData;                                 /*!< FLEXSPI callback function parameter.*/
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Get the instance number for FLEXSPI.
+ *
+ * @param base FLEXSPI base pointer.
+ */
+uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
+
+/*!
+ * @brief Check and clear IP command execution errors.
+ *
+ * @param base FLEXSPI base pointer.
+ * @param status interrupt status.
+ */
+status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
+
+/*!
+ * @brief Initializes the FLEXSPI module and internal state.
+ *
+ * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
+ * input configure parameters. Users should call this function before any FLEXSPI operations.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param config FLEXSPI configure structure.
+ */
+void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
+
+/*!
+ * @brief Gets default settings for FLEXSPI.
+ *
+ * @param config FLEXSPI configuration structure.
+ */
+void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
+
+/*!
+ * @brief Deinitializes the FLEXSPI module.
+ *
+ * Clears the FLEXSPI state and  FLEXSPI module registers.
+ * @param base FLEXSPI peripheral base address.
+ */
+void FLEXSPI_Deinit(FLEXSPI_Type *base);
+
+/*!
+ * @brief Update FLEXSPI DLL value depending on currently flexspi root clock.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param config Flash configuration parameters.
+ * @param port FLEXSPI Operation port.
+ */
+void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
+
+/*!
+ * @brief Configures the connected device parameter.
+ *
+ * This function configures the connected device relevant parameters, such as the size, command, and so on.
+ * The flash configuration value cannot have a default value. The user needs to configure it according to the
+ * connected device.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param config Flash configuration parameters.
+ * @param port FLEXSPI Operation port.
+ */
+void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
+
+/*!
+ * @brief Software reset for the FLEXSPI logic.
+ *
+ * This function sets the software reset flags for both AHB and buffer domain and
+ * resets both AHB buffer and also IP FIFOs.
+ *
+ * @param base FLEXSPI peripheral base address.
+ */
+static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
+{
+    base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+    while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
+    {
+    }
+}
+
+/*!
+ * @brief Enables or disables the FLEXSPI module.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable True means enable FLEXSPI, false means disable.
+ */
+static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+    }
+    else
+    {
+        base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+/*!
+ * @brief Enables the FLEXSPI interrupts.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param mask FLEXSPI interrupt source.
+ */
+static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+{
+    base->INTEN |= mask;
+}
+
+/*!
+ * @brief Disable the FLEXSPI interrupts.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param mask FLEXSPI interrupt source.
+ */
+static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+{
+    base->INTEN &= ~mask;
+}
+
+/*! @} */
+
+/*! @name DMA control */
+/*! @{ */
+
+/*!
+ * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
+ */
+static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK;
+    }
+    else
+    {
+        base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable.
+ */
+static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK;
+    }
+    else
+    {
+        base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK;
+    }
+}
+
+/*!
+ * @brief Gets FLEXSPI IP tx fifo address for DMA transfer.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval The tx fifo address.
+ */
+static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
+{
+    return (uint32_t)&base->TFDR[0];
+}
+
+/*!
+ * @brief Gets FLEXSPI IP rx fifo address for DMA transfer.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval The rx fifo address.
+ */
+static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
+{
+    return (uint32_t)&base->RFDR[0];
+}
+
+/*! @} */
+
+/*! @name FIFO control */
+/*! @{ */
+
+/*! @brief Clears the FLEXSPI IP FIFO logic.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param txFifo Pass true to reset TX FIFO.
+ * @param rxFifo Pass true to reset RX FIFO.
+ */
+static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
+{
+    if (txFifo)
+    {
+        base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
+    }
+    if (rxFifo)
+    {
+        base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
+    }
+}
+
+/*!
+ * @brief Gets the valid data entries in the FLEXSPI FIFOs.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
+ *      Pass NULL if this value is not required.
+ * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
+ *      Pass NULL if this value is not required.
+ */
+static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
+{
+    if (NULL != txCount)
+    {
+        *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
+    }
+    if (NULL != rxCount)
+    {
+        *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+/*!
+ * @brief Get the FLEXSPI interrupt status flags.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status.
+ */
+static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
+{
+    return base->INTR;
+}
+
+/*!
+ * @brief Get the FLEXSPI interrupt status flags.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param mask FLEXSPI interrupt source.
+ */
+static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
+{
+    base->INTR = mask;
+}
+
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
+/*! @brief Gets the sampling clock phase selection after Data Learning.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA.
+ * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB.
+ */
+static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase)
+{
+    if (portAPhase != NULL)
+    {
+        *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
+    }
+
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB))
+    if (portBPhase != NULL)
+    {
+        *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
+    }
+#endif
+}
+#endif
+
+/*! @brief Gets the trigger source of current command sequence granted by arbitrator.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval trigger source of current command sequence.
+ */
+static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
+{
+    return (flexspi_arb_command_source_t)(
+        (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT));
+}
+
+/*! @brief Gets the error code when IP command error detected.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
+ * @retval error code when IP command error detected.
+ */
+static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+{
+    *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT);
+    return (flexspi_ip_error_code_t)(
+        (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT));
+}
+
+/*! @brief Gets the error code when AHB command error detected.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
+ * @retval error code when AHB command error detected.
+ */
+static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+{
+    *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
+    return (flexspi_ahb_error_code_t)(
+        (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT));
+}
+
+/*! @brief Returns whether the bus is idle.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval true Bus is idle.
+ * @retval false Bus is busy.
+ */
+static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
+{
+    return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
+}
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*! @brief Update read sample clock source
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param clockSource clockSource of type #flexspi_read_sample_clock_t
+ */
+void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
+
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE)
+/*! @brief Enables/disables the FLEXSPI IP command parallel mode.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable True means enable parallel mode, false means disable parallel mode.
+ */
+static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK;
+    }
+    else
+    {
+        base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
+    }
+}
+#endif
+
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE)
+/*! @brief Enables/disables the FLEXSPI AHB command parallel mode.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable True means enable parallel mode, false means disable parallel mode.
+ */
+static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK;
+    }
+    else
+    {
+        base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
+    }
+}
+#endif
+
+#if (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT)
+/*!
+ * @brief Set AHB Memory-Mapped Flash base address.
+ * 
+ * @note The length of base address may be different for differnt instance, please refer to the reference manual.
+ * @note This function should be called when FLEXSPI is in stop mode.
+ * 
+ * @param base FLEXSPI peripheral base address.
+ * @param address AHB Memory-Mapped Flash base address.
+ */
+static inline void FLEXSPI_SetAHBFlashBaseAddress(FLEXSPI_Type *base, uint8_t address)
+{
+    base->AHBCR = (base->AHBCR & (~FLEXSPI_AHBCR_AFLASHBASE_MASK)) | FLEXSPI_AHBCR_AFLASHBASE(address);
+}
+#endif /* (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) */
+
+/*! @brief Updates the LUT table.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param index From which index start to update. It could be any index of the LUT table, which
+ * also allows user to update command content inside a command. Each command consists of up to
+ * 8 instructions and occupy 4*32-bit memory.
+ * @param cmd Command sequence array.
+ * @param count Number of sequences.
+ */
+void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
+
+/*!
+ * @brief Writes data into FIFO.
+ *
+ * @param base FLEXSPI peripheral base address
+ * @param data The data bytes to send
+ * @param fifoIndex Destination fifo index.
+ */
+static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
+{
+    base->TFDR[fifoIndex] = data;
+}
+
+/*!
+ * @brief Receives data from data FIFO.
+ *
+ * @param base FLEXSPI peripheral base address
+ * @param fifoIndex Source fifo index.
+ * @return The data in the FIFO.
+ */
+static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
+{
+    return base->RFDR[fifoIndex];
+}
+
+/*!
+ * @brief Sends a buffer of data bytes using blocking method.
+ * @note This function blocks via polling until all bytes have been sent.
+ * @param base FLEXSPI peripheral base address
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to send
+ * @retval kStatus_Success write success without error
+ * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size);
+
+/*!
+ * @brief Receives a buffer of data bytes using a blocking method.
+ * @note This function blocks via polling until all bytes have been sent.
+ * @param base FLEXSPI peripheral base address
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to receive
+ * @retval kStatus_Success read success without error
+ * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
+ * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size);
+
+/*!
+ * @brief Execute command to transfer a buffer data bytes using a blocking method.
+ * @param base FLEXSPI peripheral base address
+ * @param xfer pointer to the transfer structure.
+ * @retval kStatus_Success command transfer success without error
+ * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXSPI handle which is used in transactional functions.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData user parameter passed to the callback function.
+ */
+void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
+                                  flexspi_handle_t *handle,
+                                  flexspi_transfer_callback_t callback,
+                                  void *userData);
+
+/*!
+ * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
+ *
+ * @note Calling the API returns immediately after transfer initiates. The user needs
+ * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
+ * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
+ * FLEXSPI could not read data properly.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * @param xfer pointer to flexspi_transfer_t structure.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
+ */
+status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an interrupt non-blocking transfer early.
+ *
+ * @note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure which stores the transfer state
+ */
+void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure.
+ */
+void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle);
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*! @} */
+
+#endif /* FSL_FLEXSPI_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gdma.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gdma.c
new file mode 100644
index 0000000000..6d54de0dca
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gdma.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright 2021-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gdma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gdma"
+#endif
+
+/* Is address aligned? */
+#define GDMA_IS_ADDR_ALIGNED(addr, aligned_size) (((uint32_t)(addr) & ((aligned_size)-1UL)) == 0U)
+/* Is the wrap used? */
+#define GDMA_IS_WRAP_BURST(burstsize) (((uint8_t)(burstsize)&0x04U) != 0U)
+/* Get real width from enum gdma_transfer_width_t. */
+#define GDMA_REAL_XFER_WIDTH(width) (s_gdmaRealWidth[(uint8_t)(width)&0x03U])
+/* Get real burst size from gdma_burst_size_t. */
+#define GDMA_REAL_XFER_BUSTSIZE(burstsize) (s_gdmaRealBurstSize[(uint8_t)(burstsize)&0x03U])
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Typedef for interrupt handler. */
+typedef void (*gdma_isr_t)(GDMA_Type *base);
+
+/*!
+ * @brief Verify the configuration.
+ *
+ * Verify the configuration, to make sure the parameters are valid.
+ *
+ * @param config Pointer to the transfer configuration.
+ * @return Return true if the configuration is valid, otherwise return false.
+ */
+static bool GDMA_VerifyTransferConfig(const gdma_channel_xfer_config_t *config);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* @brief Pointers to transfer handle for each GDMA channel. */
+static gdma_handle_t *s_gdmaHandles[FSL_FEATURE_GDMA_CHANNEL_NUM];
+
+static const uint8_t s_gdmaRealBurstSize[] = {1U, 4U, 8U, 16U};
+static const uint8_t s_gdmaRealWidth[]     = {1U, 1U, 2U, 4U};
+
+/* ISR for transactional APIs. */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+static gdma_isr_t s_gdmaIsr = (gdma_isr_t)DefaultISR;
+#else
+static gdma_isr_t s_gdmaIsr;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*
+ * brief Verify the configuration.
+ *
+ * Verify the configuration, to make sure the parameters are valid.
+ *
+ * param config Pointer to the transfer configuration.
+ * return Return true if the configuration is valid, otherwise return false.
+ */
+static bool GDMA_VerifyTransferConfig(const gdma_channel_xfer_config_t *config)
+{
+    bool ret              = false;
+    uint8_t srcWidth      = GDMA_REAL_XFER_WIDTH(config->srcWidth);
+    uint8_t destWidth     = GDMA_REAL_XFER_WIDTH(config->destWidth);
+    uint8_t srcBurstSize  = GDMA_REAL_XFER_BUSTSIZE(config->srcBurstSize);
+    uint8_t destBurstSize = GDMA_REAL_XFER_BUSTSIZE(config->destBurstSize);
+    uint8_t srcAddrAlignSize;
+    uint8_t destAddrAlignSize;
+
+    do
+    {
+        /*  SRCBSIZE * SRCWIDTH == DESTBSIZE * DESTWIDTH */
+        if ((srcWidth * srcBurstSize) != (destWidth * destBurstSize))
+        {
+            break;
+        }
+
+        /*
+         * Address alignment:
+         *
+         * From GDMA's view, the address only need to be aligned with the WIDTH (no matter wrap used or not).
+         * When integrating with AHB and wrap is used, the address should be aligned to WIDTH * BURST_SIZE.
+         */
+        srcAddrAlignSize  = (GDMA_IS_WRAP_BURST(config->srcBurstSize)) ? (srcWidth * srcBurstSize) : srcWidth;
+        destAddrAlignSize = (GDMA_IS_WRAP_BURST(config->destBurstSize)) ? (destWidth * destBurstSize) : destWidth;
+
+        if (!((GDMA_IS_ADDR_ALIGNED(config->srcAddr, srcAddrAlignSize)) &&
+              (GDMA_IS_ADDR_ALIGNED(config->destAddr, destAddrAlignSize))))
+        {
+            break;
+        }
+
+        ret = true;
+
+    } while (false);
+
+    return ret;
+}
+
+/*
+ * brief Initializes GDMA peripheral.
+ *
+ * This function enable the GDMA clock, set descriptor table and
+ * enable GDMA peripheral.
+ *
+ * param base GDMA peripheral base address.
+ */
+void GDMA_Init(GDMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_Gdma);
+#endif
+}
+
+/*
+ * brief Deinitializes GDMA peripheral.
+ *
+ * This function gates the GDMA clock.
+ *
+ * param base GDMA peripheral base address.
+ */
+void GDMA_Deinit(GDMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(kCLOCK_Gdma);
+#endif
+}
+
+/*
+ * brief Set channel transfer configuration..
+ *
+ * This function configures the channel transfer, after configured, GDMA_StartChannel
+ * could be called to start the transfer.
+ *
+ * This function must be called when previous transfer finished. Application can use
+ * GDMA_IsChannelBusy to check whether the channel has finished the previous work.
+ *
+ * param base GDMA base address.
+ * param channel GDMA channel number.
+ * config Pointer to the transfer configuration.
+ * retval kStatus_Fail GDMA is busy with previous transfer.
+ * retval kStatus_Success Configuration set successfully.
+ * retval kStatus_InvalidArgument Configuration wrong.
+ */
+status_t GDMA_SetChannelTransferConfig(GDMA_Type *base, uint8_t channel, const gdma_channel_xfer_config_t *config)
+{
+    assert(NULL != config);
+
+    if (!GDMA_VerifyTransferConfig(config))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (GDMA_IsChannelBusy(base, channel))
+    {
+        return kStatus_Fail;
+    }
+
+    GDMA_ClearChannelInterruptFlags(base, channel, (uint32_t)kGDMA_AllInterruptFlag);
+
+    base->CH[channel].SADR = config->srcAddr;
+    base->CH[channel].DADR = config->destAddr;
+
+    base->CH[channel].CTRL =
+        GDMA_CTRL_PROT(config->ahbProt)                            /* Protection info for AHB master bus */
+        | (config->srcAddrInc ? GDMA_CTRL_SRCADDRINC_MASK : 0UL)   /* Source address increment. */
+        | (config->destAddrInc ? GDMA_CTRL_DESTADDRINC_MASK : 0UL) /* Destination address increment. */
+        | GDMA_CTRL_SRCWIDTH(config->srcWidth)                     /* Source peripheral/memory transfer width. */
+        | GDMA_CTRL_DESTWIDTH(config->destWidth)                   /* Destination peripheral/memory transfer width. */
+        | GDMA_CTRL_SRCBSIZE(config->srcBurstSize)                 /* Source peripheral/memory transfer burst size */
+        | GDMA_CTRL_DESTBSIZE(config->destBurstSize) /* Destination peripheral/memory transfer burst size */
+        | GDMA_CTRL_LEN(config->transferLen);        /* Length of the transfer in bytes */
+
+    if (config->enableLinkList)
+    {
+        base->CH[channel].LLI =
+            (config->linkListAddr & GDMA_LLI_LLI_MASK)                        /* LLI address. */
+            | (config->enableDescInterrupt ? GDMA_LLI_DESC_INT_EN_MASK : 0UL) /* Enable descriptor interrupt. */
+            | (config->stopAfterDescFinished ? GDMA_LLI_STOP_MASK : 0UL);     /* Stop after descriptor finished. */
+        base->CH[channel].CONFIG |= GDMA_CONFIG_LLE_MASK;
+    }
+    else
+    {
+        base->CH[channel].LLI = GDMA_LLI_STOP_MASK;
+        base->CH[channel].CONFIG &= ~GDMA_CONFIG_LLE_MASK;
+    }
+
+    return kStatus_Success;
+}
+
+/*
+ * brief Creates the GDMA handle.
+ *
+ * This function is called if using transaction API for GDMA. This function
+ * initializes the internal state of GDMA handle.
+ *
+ * param handle GDMA handle pointer. It stores callback function and parameters.
+ * param base GDMA peripheral base address.
+ * param channel GDMA channel number.
+ */
+void GDMA_CreateHandle(gdma_handle_t *handle, GDMA_Type *base, uint8_t channel)
+{
+    assert(NULL != handle);
+
+    (void)memset(handle, 0, sizeof(*handle));
+
+    handle->gdma    = base;
+    handle->channel = channel;
+
+    s_gdmaHandles[channel] = handle;
+    s_gdmaIsr              = GDMA_IRQHandle;
+
+    (void)EnableIRQ(GDMA_IRQn);
+}
+
+/*
+ * brief Installs a callback function for the GDMA transfer.
+ *
+ * This callback is called in GDMA IRQ handler to inform user the interrupt status.
+ *
+ * param handle GDMA handle pointer.
+ * param callback GDMA callback function pointer.
+ * param userData Parameter for callback function.
+ */
+void GDMA_SetCallback(gdma_handle_t *handle, gdma_callback_t callback, void *userData)
+{
+    assert(handle != NULL);
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+/*
+ * brief Submits the GDMA channel transfer request.
+ *
+ * After this function, user could call GDMA_StartTransfer to start GDMA transfer.
+ *
+ * This function must be called when previous transfer finished. Application can use
+ * GDMA_IsChannelBusy to check whether the channel has finished the previous work.
+ *
+ * param handle GDMA handle pointer.
+ * param config Pointer to GDMA transfer configuration structure.
+ * retval kStatus_Fail GDMA is busy with previous transfer.
+ * retval kStatus_Success Configuration set successfully.
+ * retval kStatus_InvalidArgument Configuration wrong.
+ */
+status_t GDMA_SubmitTransfer(gdma_handle_t *handle, gdma_channel_xfer_config_t *config)
+{
+    status_t status;
+
+    assert(NULL != handle);
+
+    status = GDMA_SetChannelTransferConfig(handle->gdma, handle->channel, config);
+
+    if (status == kStatus_Success)
+    {
+        GDMA_EnableChannelInterrupts(
+            handle->gdma, handle->channel,
+            (uint32_t)kGDMA_DescriptorTransferDoneInterruptEnable | (uint32_t)kGDMA_AddressErrorInterruptEnable |
+                (uint32_t)kGDMA_BusErrorInterruptEnable | (uint32_t)kGDMA_TransferDoneInterruptEnable);
+    }
+
+    return status;
+}
+
+/*
+ * brief GDMA start transfer.
+ *
+ * User can call this function after GDMA_SubmitTransfer.
+ *
+ * param handle GDMA handle pointer.
+ */
+void GDMA_StartTransfer(gdma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    GDMA_StartChannel(handle->gdma, handle->channel);
+}
+
+/*
+ * brief Abort running transfer by handle.
+ *
+ * This function aborts GDMA transfer specified by handle.
+ *
+ * param handle GDMA handle pointer.
+ */
+void GDMA_AbortTransfer(gdma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    GDMA_StopChannel(handle->gdma, handle->channel);
+
+    GDMA_DisableChannelInterrupts(handle->gdma, handle->channel, (uint32_t)kGDMA_AllInterruptEnable);
+}
+
+/*
+ * brief GDMA IRQ handler.
+ *
+ * This function checks all GDMA channel interrupts and inform application
+ * the interrupt flags through user registered callback.
+ *
+ * param base GDMA peripheral.
+ */
+void GDMA_IRQHandle(GDMA_Type *base)
+{
+    uint8_t channel;
+    uint32_t interrupts;
+    gdma_handle_t *handle;
+
+    for (channel = 0U; channel < (uint8_t)FSL_FEATURE_GDMA_CHANNEL_NUM; channel++)
+    {
+        interrupts = GDMA_GetChannelInterruptFlags(base, channel);
+
+        /*
+         * If channels unmasked interrupt happened. This flag is only assert
+         * only when any unmasked interrupt happened.
+         */
+        if (0U != (interrupts & (uint32_t)kGDMA_ChannelInterruptFlag))
+        {
+            GDMA_ClearChannelInterruptFlags(base, channel, interrupts);
+
+            handle = s_gdmaHandles[channel];
+
+            if (NULL != handle)
+            {
+                /* If error happened or transfer finished successfully. */
+                if (0U != (interrupts & ((uint32_t)kGDMA_AddressErrorFlag | (uint32_t)kGDMA_BusErrorFlag |
+                                         (uint32_t)kGDMA_TransferDoneFlag)))
+                {
+                    GDMA_DisableChannelInterrupts(base, channel, (uint32_t)kGDMA_AllInterruptEnable);
+                }
+
+                if (NULL != handle->callback)
+                {
+                    handle->callback(handle, handle->userData, interrupts);
+                }
+            }
+            else
+            {
+                /*
+                 * If interrupt occurs but handle not created, then disable the interrupts,
+                 * because to use the transactional APIs, user must create handle, then
+                 * setup configuration and enable interrupts for data transfer.
+                 *
+                 * Generally will not reach here.
+                 */
+                GDMA_DisableChannelInterrupts(base, channel, (uint32_t)kGDMA_AllInterruptEnable);
+            }
+        }
+    }
+}
+
+void GDMA_DriverIRQHandler(void);
+void GDMA_DriverIRQHandler(void)
+{
+    s_gdmaIsr(GDMA);
+    SDK_ISR_EXIT_BARRIER;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gdma.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gdma.h
new file mode 100644
index 0000000000..81a5fdc35d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gdma.h
@@ -0,0 +1,535 @@
+/*
+ * Copyright 2021-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_GDMA_H_
+#define FSL_GDMA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gdma
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+#define FSL_GDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
+/*! @} */
+
+/*!
+ * @brief Macro for GDMA link list descriptor LLI.
+ *
+ * This macro constructs @ref gdma_descriptor_t::lli.
+ *
+ * @param linkListAddr Address of next link list descriptor item.
+ * @param stopAfterDescFinished Stop or not after this descriptor transfer done.
+ * @param enableDescInterrupt Generate interrupt after this descriptor transfer done.
+ */
+#define GDMA_DESC_LLI(linkListAddr, stopAfterDescFinished, enableDescInterrupt)                                 \
+    (((uint32_t)(linkListAddr)&GDMA_LLI_LLI_MASK) | ((enableDescInterrupt) ? GDMA_LLI_DESC_INT_EN_MASK : 0UL) | \
+     ((stopAfterDescFinished) ? GDMA_LLI_STOP_MASK : 0UL))
+/*
+ * @brief Macro for GDMA link list descriptor CTRL.
+ *
+ * This macro constructs @ref gdma_descriptor_t::ctrl.
+ *
+ * @param ahbProt GDMA AHB HPROT flags, it could be OR'ed value of @ref _gdma_ahb_prot.
+ * @param srcAddrInc Increase source address on each successive access, use true or false.
+ * @param destAddrInc Increase destination address on each successive access, use true or false.
+ * @param srcWidth  Source transfer width, see @ref gdma_transfer_width_t.
+ * @param destWidth Destination transfer width, see @ref gdma_transfer_width_t.
+ * @param srcBurstSize  Source address burst size, see @ref gdma_burst_size_t.
+ * @param destBurstSize Destination address burst size, see @ref gdma_burst_size_t.
+ * @param len Transfer length in bytes, max value is 8 * 1024 - 1.
+ */
+#define GDMA_DESC_CTRL(ahbProt, srcAddrInc, destAddrInc, srcWidth, destWidth, srcBurstSize, destBurstSize, length) \
+    (GDMA_CTRL_PROT(ahbProt) | ((srcAddrInc) ? GDMA_CTRL_SRCADDRINC_MASK : 0UL) |                                  \
+     ((destAddrInc) ? GDMA_CTRL_DESTADDRINC_MASK : 0UL) | GDMA_CTRL_SRCWIDTH(srcWidth) |                           \
+     GDMA_CTRL_DESTWIDTH(destWidth) | GDMA_CTRL_SRCBSIZE(srcBurstSize) | GDMA_CTRL_DESTBSIZE(destBurstSize) |      \
+     GDMA_CTRL_LEN(length))
+
+/*! @brief GDMA transfer width */
+typedef enum _gdma_transfer_width
+{
+    kGDMA_TransferWidth1Byte = 1U, /*!< 1 byte.  */
+    kGDMA_TransferWidth2Byte = 2U, /*!< 2 bytes. */
+    kGDMA_TransferWidth4Byte = 3U, /*!< 4 bytes. */
+} gdma_transfer_width_t;
+
+/*! @brief GDMA burst size*/
+typedef enum _gdma_burst_size
+{
+    kGDMA_BurstSize1      = 0U, /*!< Burst 1.  */
+    kGDMA_BurstSize4      = 1U, /*!< Burst 4.  */
+    kGDMA_BurstSize8      = 2U, /*!< Burst 8.  */
+    kGDMA_BurstSize16     = 3U, /*!< Burst 16. */
+    kGDMA_BurstSizeWrap4  = 5U, /*!< Wrap 4.   */
+    kGDMA_BurstSizeWrap8  = 6U, /*!< Wrap 8.   */
+    kGDMA_BurstSizeWrap16 = 7U, /*!< Wrap 16.  */
+} gdma_burst_size_t;
+
+/*!
+ * @brief GDMA AHB HPROT flags.
+ * @anchor _gdma_ahb_prot
+ */
+enum _gdma_ahb_prot
+{
+    kGDMA_ProtUserMode       = (0U << 0U), /*!< The access is in user mode. */
+    kGDMA_ProtPrevilegedMode = (1U << 0U), /*!< The access is in previleged mode. */
+    kGDMA_ProtUnbufferable   = (0U << 1U), /*!< The access is not bufferable. */
+    kGDMA_ProtBufferable     = (1U << 1U), /*!< The access is bufferable. */
+    kGDMA_ProtUncacheable    = (0U << 2U), /*!< The access is not cacheable. */
+    kGDMA_ProtCacheable      = (1U << 2U), /*!< The access is cacheable. */
+};
+
+/*! @brief GDMA channel link list descriptor structure */
+typedef struct __ALIGNED(16) _gdma_descriptor
+{
+    uint32_t srcAddr; /*!< Source address. */
+    uint32_t dstAddr; /*!< Destination address. */
+    uint32_t lli;     /*!< Link list item. */
+    uint32_t ctrl;    /*!< Transfer control. */
+} gdma_descriptor_t;
+
+/*! @brief GDMA channel priority */
+typedef enum _gdma_priority
+{
+    kGDMA_ChannelPriority0 = 0, /*!< Lowest channel priority - priority 0   */
+    kGDMA_ChannelPriority1,     /*!< Channel priority 1                     */
+    kGDMA_ChannelPriority2,     /*!< Channel priority 2                     */
+    kGDMA_ChannelPriority3,     /*!< Channel priority 3                     */
+    kGDMA_ChannelPriority4,     /*!< Channel priority 4                     */
+    kGDMA_ChannelPriority5,     /*!< Channel priority 5                     */
+    kGDMA_ChannelPriority6,     /*!< Channel priority 6                     */
+    kGDMA_ChannelPriority7,     /*!< Channel priority 7                     */
+    kGDMA_ChannelPriority8,     /*!< Channel priority 8                     */
+    kGDMA_ChannelPriority9,     /*!< Channel priority 9                     */
+    kGDMA_ChannelPriority10,    /*!< Channel priority 10                    */
+    kGDMA_ChannelPriority11,    /*!< Channel priority 11                    */
+    kGDMA_ChannelPriority12,    /*!< Channel priority 12                    */
+    kGDMA_ChannelPriority13,    /*!< Channel priority 13                    */
+    kGDMA_ChannelPriority14,    /*!< Channel priority 14                    */
+    kGDMA_ChannelPriority15,    /*!< Highest channel priority - priority 15 */
+} gdma_priority_t;
+
+/*!
+ * @brief GDMA interrupts to enable
+ * @anchor _gdma_interrupt_enable
+ */
+enum _gdma_interrupt_enable
+{
+    /*!
+     * Descriptor transfer done interrupt. This happens when the descriptor
+     * is configured to generate interrupt when transfer done.
+     */
+    kGDMA_DescriptorTransferDoneInterruptEnable = GDMA_CHNL_INT_MASK_DESC_TFRINT_MASK,
+
+    /*! Channel source or destination address is not aligned to corresponding transfer width. */
+    kGDMA_AddressErrorInterruptEnable = GDMA_CHNL_INT_MASK_ADDRERRINT_MASK,
+
+    /*! AHB bus interrupt. */
+    kGDMA_BusErrorInterruptEnable = GDMA_CHNL_INT_MASK_BUSERRINT_MASK,
+
+    /*! DMA transfer done interrupt. */
+    kGDMA_TransferDoneInterruptEnable = GDMA_CHNL_INT_MASK_TFRINT_MASK,
+
+    /*! DMA block single/burst transfer done interrupt. */
+    kGDMA_BlockTransferDoneInterruptEnable = GDMA_CHNL_INT_MASK_BLOCKINT_MASK,
+
+    /*! All interrupt enable. */
+    kGDMA_AllInterruptEnable = kGDMA_DescriptorTransferDoneInterruptEnable | kGDMA_AddressErrorInterruptEnable |
+                               kGDMA_BusErrorInterruptEnable | kGDMA_TransferDoneInterruptEnable |
+                               kGDMA_BlockTransferDoneInterruptEnable,
+};
+
+/*!
+ * @brief GDMA interrupt status flags.
+ * @anchor _gdma_interrupt_flags
+ */
+enum _gdma_interrupt_flags
+{
+    /*!
+     * Descriptor transfer done interrupt. This happens when the descriptor
+     * is configured to generate interrupt when transfer done.
+     */
+    kGDMA_DescriptorTransferDoneFlag = GDMA_CHNL_INT_DESC_STATUS_TFRINT_MASK,
+
+    /*! OR of the content of the respective unmasked interrupt of channel. */
+    kGDMA_ChannelInterruptFlag = GDMA_CHNL_INT_STATUS_CHLINT_MASK,
+
+    /*! Channel source or destination address is not aligned to corresponding transfer width. */
+    kGDMA_AddressErrorFlag = GDMA_CHNL_INT_STATUS_ADDRERRINT_MASK,
+
+    /*! AHB bus interrupt. */
+    kGDMA_BusErrorFlag = GDMA_CHNL_INT_STATUS_BUSERRINT_MASK,
+
+    /*! DMA transfer done interrupt. */
+    kGDMA_TransferDoneFlag = GDMA_CHNL_INT_STATUS_TFRINT_MASK,
+
+    /*! DMA block single/burst transfer done interrupt. */
+    kGDMA_BlockTransferDoneFlag = GDMA_CHNL_INT_STATUS_BLOCKINT_MASK,
+
+    /*! All interrupt flags. */
+    kGDMA_AllInterruptFlag = kGDMA_DescriptorTransferDoneFlag | kGDMA_ChannelInterruptFlag | kGDMA_AddressErrorFlag |
+                             kGDMA_BusErrorFlag | kGDMA_TransferDoneFlag | kGDMA_BlockTransferDoneFlag,
+};
+
+/*!
+ * @brief GDMA channel transfer configuration.
+ *
+ * @note The transfer configuration must follow the requirements:
+ *   - SRCBSIZE * SRCWIDTH == DESTBSIZE * DESTWIDTH
+ *   - If wrap not used, the address should align with WIDTH
+ *   - If wrap used, the address should align with WIDTH * BURST_SIZE.
+ */
+typedef struct _gdma_channel_xfer_config
+{
+    uint32_t srcAddr;                /*!< Source data address */
+    uint32_t destAddr;               /*!< Destination data address */
+    uint8_t ahbProt;                 /*!< GDMA AHB HPROT flags, it could be OR'ed value of @ref _gdma_ahb_prot. */
+    gdma_burst_size_t srcBurstSize;  /*!< Source address burst size. */
+    gdma_burst_size_t destBurstSize; /*!< Destination address burst size. */
+    gdma_transfer_width_t srcWidth;  /*!< Source transfer width. */
+    gdma_transfer_width_t destWidth; /*!< Destination transfer width. */
+    bool srcAddrInc;                 /*!< Increase source address on each successive access. */
+    bool destAddrInc;                /*!< Increase destination address on each successive access. */
+    uint16_t transferLen; /*!< Transfer length in bytes, max value is 8 * 1024 - 1, should align with transfer size. */
+    bool enableLinkList;  /*!< Enable link list or not. */
+
+    /*! Generate interrupt when descriptor transfer finished, only used when @ref enableLinkList is true. */
+    bool enableDescInterrupt;
+
+    /*! Stop channel when descriptor transfer finished, only used when @ref enableLinkList is true. */
+    bool stopAfterDescFinished;
+
+    uint32_t linkListAddr; /*!< Link list address, only used when @ref enableLinkList is true. */
+} gdma_channel_xfer_config_t;
+
+/*! @brief Driver handle for GDMA */
+struct _gdma_handle;
+
+/*! @brief Define Callback function for GDMA.
+ *
+ * handle: Pointer to the GDMA driver handle.
+ * userData: The userData registered using @ref GDMA_SetCallback.
+ * interrupts: The interrupts flags of the specific channel.
+ */
+typedef void (*gdma_callback_t)(struct _gdma_handle *handle, void *userData, uint32_t interrupts);
+
+/*! @brief GDMA transfer handle structure */
+typedef struct _gdma_handle
+{
+    GDMA_Type *gdma;          /*!< GDMA peripheral base address */
+    uint8_t channel;          /*!< GDMA channel number */
+    gdma_callback_t callback; /*!< Callback function. Invoked interrupt happens. */
+    void *userData;           /*!< Callback function parameter */
+} gdma_handle_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name GDMA initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes GDMA peripheral.
+ *
+ * It ungates the GDMA access clock, after this function, the GDMA module is
+ * ready to be used.
+ *
+ * @param base GDMA peripheral base address.
+ */
+void GDMA_Init(GDMA_Type *base);
+
+/*!
+ * @brief Deinitializes GDMA peripheral.
+ *
+ * @param base GDMA peripheral base address.
+ */
+void GDMA_Deinit(GDMA_Type *base);
+
+/*! @} */
+
+/*!
+ * @name GDMA Channel Operation
+ * @{
+ */
+
+/*!
+ * @brief Set GDMA channel source address.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @param addr Source address.
+ */
+static inline void GDMA_SetChannelSourceAddress(GDMA_Type *base, uint8_t channel, uint32_t addr)
+{
+    base->CH[channel].SADR = addr;
+}
+
+/*!
+ * @brief Set GDMA channel destination address.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @param addr Destination address.
+ */
+static inline void GDMA_SetChannelDestAddress(GDMA_Type *base, uint8_t channel, uint32_t addr)
+{
+    base->CH[channel].DADR = addr;
+}
+
+/*!
+ * @brief Start GDMA channel to work.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ */
+static inline void GDMA_StartChannel(GDMA_Type *base, uint8_t channel)
+{
+    base->CH[channel].CHL_EN |= GDMA_CHL_EN_CHL_EN_MASK;
+}
+
+/*!
+ * @brief Stop GDMA channel.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ */
+static inline void GDMA_StopChannel(GDMA_Type *base, uint8_t channel)
+{
+    base->CH[channel].CHL_STOP = GDMA_CHL_STOP_CHL_STOP_MASK;
+}
+
+/*!
+ * @brief Return whether GDMA channel is processing transfer
+ *
+ * When @ref GDMA_StopChannel is called, if the channel is on service,
+ * it does not stop immediately, application could call this API to check
+ * whether the channel is stopped.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @return True if the channel is busy, false if not.
+ */
+static inline bool GDMA_IsChannelBusy(GDMA_Type *base, uint8_t channel)
+{
+    return ((base->CH[channel].CHL_EN & GDMA_CHL_EN_CHL_EN_MASK) != 0UL);
+}
+
+/*!
+ * @brief Enables the interrupt for the GDMA transfer.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @param interrupts The interrupts to enable, it is OR'ed value of @ref _gdma_interrupt_enable.
+ */
+static inline void GDMA_EnableChannelInterrupts(GDMA_Type *base, uint8_t channel, uint32_t interrupts)
+{
+    base->CH[channel].CHNL_INT |= interrupts;
+}
+
+/*!
+ * @brief Disables the interrupt for the GDMA transfer.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @param interrupts The interrupts to disable, it is OR'ed value of @ref _gdma_interrupt_enable.
+ */
+static inline void GDMA_DisableChannelInterrupts(GDMA_Type *base, uint8_t channel, uint32_t interrupts)
+{
+    base->CH[channel].CHNL_INT &= ~interrupts;
+}
+
+/*!
+ * @brief Get the GDMA channel interrupt flags.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @return The interrupt flags, it is OR'ed value of @ref _gdma_interrupt_flags.
+ */
+static inline uint32_t GDMA_GetChannelInterruptFlags(GDMA_Type *base, uint8_t channel)
+{
+    return base->CH[channel].CHNL_INT & (uint32_t)kGDMA_AllInterruptFlag;
+}
+
+/*!
+ * @brief Clear the GDMA channel interrupt flags.
+ *
+ * The @ref kGDMA_ChannelInterruptFlag is OR'ed status of all other unmasked interrupt flags,
+ * it could not be clear directly, it should be cleared by clear all other flags.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @param flags The interrupt flags to clear, it is OR'ed value of @ref _gdma_interrupt_flags.
+ */
+static inline void GDMA_ClearChannelInterruptFlags(GDMA_Type *base, uint8_t channel, uint32_t flags)
+{
+    base->CH[channel].CHNL_INT = (base->CH[channel].CHNL_INT & ~(uint32_t)kGDMA_AllInterruptFlag) | flags;
+}
+
+/*!
+ * @brief Get the number of finished descriptor.
+ *
+ * The counter increases when an item of descriptor is done in linklist mode.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @return Number of finished descriptor.
+ */
+static inline uint32_t GDMA_GetChannelFinishedDescriptorNumber(GDMA_Type *base, uint8_t channel)
+{
+    return base->CH[channel].NUM_OF_DESCRIPTOR;
+}
+
+/*!
+ * @brief Clear the number of finished descriptor.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ */
+static inline void GDMA_ClearChannelFinishedDescriptorNumber(GDMA_Type *base, uint8_t channel)
+{
+    base->CH[channel].NUM_OF_DESCRIPTOR = 0UL;
+}
+
+/*!
+ * @brief Set priority of channel.
+ *
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ * @param priority Channel priority value.
+ */
+static inline void GDMA_SetChannelPriority(GDMA_Type *base, uint8_t channel, gdma_priority_t priority)
+{
+    base->CH[channel].CHL_EN =
+        (base->CH[channel].CHL_EN & ~(GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_MASK | GDMA_CHL_EN_CHL_EN_MASK)) |
+        (uint32_t)priority;
+}
+
+/*!
+ * @brief Set channel transfer configuration..
+ *
+ * This function configures the channel transfer, after configured, @ref GDMA_StartChannel
+ * could be called to start the transfer.
+ *
+ * This function must be called when previous transfer finished. Application can use
+ * @ref GDMA_IsChannelBusy to check whether the channel has finished the previous work.
+ *
+ * @note The transfer configuration must follow the requirements:
+ *   - SRCBSIZE * SRCWIDTH == DESTBSIZE * DESTWIDTH
+ *   - If wrap not used, the address should align with WIDTH
+ *   - If wrap used, the address should align with WIDTH * BURST_SIZE.
+ *
+ * @param base GDMA base address.
+ * @param channel GDMA channel number.
+ * @config Pointer to the transfer configuration.
+ * @retval kStatus_Fail GDMA is busy with previous transfer.
+ * @retval kStatus_Success Configuration set successfully.
+ * @retval kStatus_InvalidArgument Configuration wrong.
+ */
+status_t GDMA_SetChannelTransferConfig(GDMA_Type *base, uint8_t channel, const gdma_channel_xfer_config_t *config);
+
+/*! @} */
+
+/*!
+ * @name GDMA Transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Creates the GDMA handle.
+ *
+ * This function is called if using transaction API for GDMA. This function
+ * initializes the internal state of GDMA handle.
+ *
+ * @param handle GDMA handle pointer. It stores callback function and parameters.
+ * @param base GDMA peripheral base address.
+ * @param channel GDMA channel number.
+ */
+void GDMA_CreateHandle(gdma_handle_t *handle, GDMA_Type *base, uint8_t channel);
+
+/*!
+ * @brief Installs a callback function for the GDMA transfer.
+ *
+ * This callback is called in GDMA IRQ handler to inform user the interrupt status.
+ *
+ * @param handle GDMA handle pointer.
+ * @param callback GDMA callback function pointer.
+ * @param userData Parameter for callback function.
+ */
+void GDMA_SetCallback(gdma_handle_t *handle, gdma_callback_t callback, void *userData);
+
+/*!
+ * @brief Submits the GDMA channel transfer request.
+ *
+ * After this function, user could call @ref GDMA_StartTransfer to start GDMA transfer.
+ *
+ * This function must be called when previous transfer finished. Application can use
+ * @ref GDMA_IsChannelBusy to check whether the channel has finished the previous work.
+ *
+ * @note The transfer configuration must follow the requirements:
+ *   - SRCBSIZE * SRCWIDTH == DESTBSIZE * DESTWIDTH
+ *   - If wrap not used, the address should align with WIDTH
+ *   - If wrap used, the address should align with WIDTH * BURST_SIZE.
+ *
+ * @param handle GDMA handle pointer.
+ * @param config Pointer to GDMA transfer configuration structure.
+ * @retval kStatus_Fail GDMA is busy with previous transfer.
+ * @retval kStatus_Success Configuration set successfully.
+ * @retval kStatus_InvalidArgument Configuration wrong.
+ */
+status_t GDMA_SubmitTransfer(gdma_handle_t *handle, gdma_channel_xfer_config_t *config);
+
+/*!
+ * @brief GDMA start transfer.
+ *
+ * User can call this function after @ref GDMA_SubmitTransfer.
+ *
+ * @param handle GDMA handle pointer.
+ */
+void GDMA_StartTransfer(gdma_handle_t *handle);
+
+/*!
+ * @brief Abort running transfer by handle.
+ *
+ * When this function is called, if the channel is on service, it only
+ * stops when service finished.
+ *
+ * @param handle GDMA handle pointer.
+ */
+void GDMA_AbortTransfer(gdma_handle_t *handle);
+
+/*!
+ * @brief GDMA IRQ handler.
+ *
+ * This function checks all GDMA channel interrupts and inform application
+ * the interrupt flags through user registered callback.
+ *
+ * @param base GDMA peripheral.
+ */
+void GDMA_IRQHandle(GDMA_Type *base);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /*FSL_GDMA_H_*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gpio.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gpio.c
new file mode 100644
index 0000000000..3a0cdd3659
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gpio.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+/*! @brief Pointers to GPIO resets for each instance. */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
+#endif
+/*******************************************************************************
+ * Prototypes
+ ************ ******************************************************************/
+/*!
+ * @brief Enable GPIO port clock.
+ *
+ * @param base   GPIO peripheral base pointer.
+ * @param port   GPIO port number.
+ */
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    assert(port < ARRAY_SIZE(s_gpioClockName));
+
+    /* Upgate the GPIO clock */
+    CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * param base   GPIO peripheral base pointer.
+ * param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)
+{
+    GPIO_EnablePortClock(base, port);
+
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+    /* Reset the GPIO module */
+    RESET_PeripheralReset(s_gpioResets[port]);
+#endif
+}
+
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   GPIO peripheral base pointer(Typically GPIO)
+ * param port   GPIO port number
+ * param pin    GPIO pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+    GPIO_EnablePortClock(base, port);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRCLR[port] = 1UL << pin;
+#else
+        base->DIR[port] &= ~(1UL << pin);
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+    }
+    else
+    {
+        /* Set default output value */
+        if (config->outputLogic == 0U)
+        {
+            base->CLR[port] = (1UL << pin);
+        }
+        else
+        {
+            base->SET[port] = (1UL << pin);
+        }
+/* Set pin direction */
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRSET[port] = 1UL << pin;
+#else
+        base->DIR[port] |= 1UL << pin;
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+    }
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Set the configuration of pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
+{
+    base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin);
+
+    base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin);
+}
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] | mask;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] | mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] & ~mask;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] & ~mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Clears multiple pins interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTSTATA[port] = mask;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTSTATB[port] = mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index)
+{
+    uint32_t status = 0U;
+
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        status = base->INTSTATA[port];
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        status = base->INTSTATB[port];
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+    return status;
+}
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] | (1UL << pin);
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] | (1UL << pin);
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] & ~(1UL << pin);
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] & ~(1UL << pin);
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTSTATA[port] = 1UL << pin;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTSTATB[port] = 1UL << pin;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gpio.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gpio.h
new file mode 100644
index 0000000000..27070220ef
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_gpio.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief LPC GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
+/*! @} */
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
+#define GPIO_PIN_INT_LEVEL 0x00U
+#define GPIO_PIN_INT_EDGE  0x01U
+
+#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER  0x01U
+
+/*! @brief GPIO Pin Interrupt enable mode */
+typedef enum _gpio_pin_enable_mode
+{
+    kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
+    kGPIO_PinIntEnableEdge  = GPIO_PIN_INT_EDGE   /*!< Generate Pin Interrupt on edge mode */
+} gpio_pin_enable_mode_t;
+
+/*! @brief GPIO Pin Interrupt enable polarity */
+typedef enum _gpio_pin_enable_polarity
+{
+    kGPIO_PinIntEnableHighOrRise =
+        PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */
+    kGPIO_PinIntEnableLowOrFall =
+        PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */
+} gpio_pin_enable_polarity_t;
+
+/*! @brief LPC GPIO interrupt index definition */
+typedef enum _gpio_interrupt_index
+{
+    kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/
+    kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/
+} gpio_interrupt_index_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef struct _gpio_interrupt_config
+{
+    uint8_t mode;     /* The trigger mode of GPIO interrupts */
+    uint8_t polarity; /* The polarity of GPIO interrupts */
+} gpio_interrupt_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name GPIO Configuration */
+/*! @{ */
+
+/*!
+ * @brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * @param base   GPIO peripheral base pointer.
+ * @param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*! @} */
+
+/*! @name GPIO Output Operations */
+/*! @{ */
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+    base->B[port][pin] = output;
+}
+
+/*! @} */
+/*! @name GPIO Input Operations */
+/*! @{ */
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+    return (uint32_t)base->B[port][pin];
+}
+
+/*! @} */
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->NOT[port] = mask;
+}
+
+/*! @} */
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->PIN[port];
+}
+
+/*! @} */
+/*! @name GPIO Mask Operations */
+/*! @{ */
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param output  GPIO port output value.
+ */
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+    base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @retval       masked GPIO port value
+ */
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->MPIN[port];
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Set the configuration of pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config);
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Clears pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index);
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_imu.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_imu.c
new file mode 100644
index 0000000000..93d89a69e7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_imu.c
@@ -0,0 +1,430 @@
+/*
+ * Copyright 2020-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_imu.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.imu"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/******************************************************************************
+ * Code
+ *****************************************************************************/
+
+/*
+ * Initializes the IMU module.
+ *
+ * This function sets IMU to initialized state, including:
+ *
+ *   - Flush the send FIFO.
+ *   - Unlock the send FIFO.
+ *   - Set the water mark to (IMU_MAX_MSG_FIFO_WATER_MARK)
+ *
+ */
+status_t IMU_Init(imu_link_t link)
+{
+    status_t status;
+
+    if (link >= kIMU_LinkMax)
+    {
+        status = kStatus_InvalidArgument;
+    }
+    else
+    {
+        IMU_FlushSendFifo(link);
+        IMU_LockSendFifo(link, false);
+        IMU_SetSendFifoWaterMark(link, IMU_MAX_MSG_FIFO_WATER_MARK);
+
+        /* Flush RX FIFO. */
+        while (!IMU_RX_FIFO_EMPTY(link))
+        {
+            (void)IMU_RD_MSG(link);
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*
+ * De-initializes the IMU module.
+ *
+ */
+void IMU_Deinit(imu_link_t link)
+{
+}
+
+/*
+ * Blocking to send messages.
+ *
+ * This function blocks until all messages have been filled to TX FIFO.
+ *
+ * - If the TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED.
+ * - If TX FIFO not locked, this function waits the available empty slot in TX FIFO,
+ *   and fills the message to TX FIFO.
+ * - To lock TX FIFO after filling all messages, set  lockSendFifo to true.
+ *
+ * param link IMU link.
+ * param msgs The messages to send.
+ * param msgCount Message count, one message is a 32-bit word.
+ * param lockSendFifo If set to true, the TX FIFO is locked after all messages filled to TX FIFO.
+ * return If TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED,
+ * otherwise, this function returns the actual message count sent out, it equals  msgCount
+ * because this function is blocking function, it returns until all messages have been
+ * filled into TX FIFO.
+ */
+int32_t IMU_SendMsgsBlocking(imu_link_t link, const uint32_t *msgs, int32_t msgCount, bool lockSendFifo)
+{
+    int32_t ret;
+    int32_t curSent;
+    int32_t fifoEmptySpace;
+
+    if (msgCount <= 0)
+    {
+        ret = 0;
+    }
+    else if (IMU_TX_FIFO_LOCKED(link))
+    {
+        ret = IMU_ERR_TX_FIFO_LOCKED;
+    }
+    else
+    {
+        ret = msgCount;
+
+        /* Send the first (msgCount - 1), the last message should
+         * be sent with the lock configuration.
+         */
+        msgCount--;
+
+        while (msgCount > 0)
+        {
+            fifoEmptySpace = (int32_t)IMU_GetSendFifoEmptySpace(link);
+            curSent        = MIN(msgCount, fifoEmptySpace);
+
+            msgCount -= curSent;
+
+            while (0 != (curSent--))
+            {
+                IMU_WR_MSG(link, *msgs);
+                msgs++;
+            }
+        }
+
+        /* To lock TX FIFO, set the lock bit before last message write. */
+        if (lockSendFifo)
+        {
+            IMU_LOCK_TX_FIFO(link);
+        }
+
+        /* Send the last. */
+        while (0UL == IMU_GetSendFifoEmptySpace(link))
+        {
+        }
+        IMU_WR_MSG(link, *msgs);
+    }
+
+    return ret;
+}
+
+/*
+ * Try to send messages.
+ *
+ * This function is similar with @ref IMU_SendMsgsBlocking, the difference is,
+ * this function tries to send as many as possible, if there is not enough
+ * empty slot in TX FIFO, this function fills messages to available empty slots
+ * and returns how many messages have been filled.
+ *
+ * - If the TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED.
+ * - If TX FIFO not locked, this function fills messages to TX FIFO empty slot,
+ *   and returns how many messages have been filled.
+ * - If  lockSendFifo is set to true, TX FIFO is locked after all messages have
+ *   been filled to TX FIFO. In other word, TX FIFO is locked if the function
+ *   return value equals  msgCount, when  lockSendFifo set to true.
+ *
+ * param link IMU link.
+ * param msgs The messages to send.
+ * param msgCount Message count, one message is a 32-bit word.
+ * param lockSendFifo If set to true, the TX FIFO is locked after all messages filled to TX FIFO.
+ * return If TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED,
+ * otherwise, this function returns the actual message count sent out.
+ */
+int32_t IMU_TrySendMsgs(imu_link_t link, const uint32_t *msgs, int32_t msgCount, bool lockSendFifo)
+{
+    int32_t ret;
+    int32_t curSent;
+    int32_t fifoEmptySpace;
+
+    if (msgCount <= 0)
+    {
+        ret = 0;
+    }
+    else if (IMU_TX_FIFO_LOCKED(link))
+    {
+        ret = IMU_ERR_TX_FIFO_LOCKED;
+    }
+    else
+    {
+        ret = 0;
+
+        /* Send the first (msgCount - 1), the last message should
+         * be sent with the lock configuration.
+         */
+        msgCount--;
+
+        while (true)
+        {
+            fifoEmptySpace = (int32_t)IMU_GetSendFifoEmptySpace(link);
+
+            if (fifoEmptySpace == 0)
+            {
+                break;
+            }
+            /* If this is the last and have FIFO space to send. */
+            else if (0 == msgCount)
+            {
+                if (lockSendFifo)
+                {
+                    IMU_LOCK_TX_FIFO(link);
+                }
+
+                /* Send the last. */
+                IMU_WR_MSG(link, *msgs);
+                ret++;
+                break;
+            }
+            else
+            {
+                curSent = MIN(msgCount, fifoEmptySpace);
+
+                /* Send the data. */
+                msgCount -= curSent;
+                ret += curSent;
+                while (0 != (curSent--))
+                {
+                    IMU_WR_MSG(link, *msgs);
+                    msgs++;
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*
+ * Try to receive messages.
+ *
+ * This function tries to read messages from RX FIFO. It reads the messages already
+ * exists in RX FIFO and returns the actual read count.
+ *
+ * - If the RX FIFO has enough messages, this function reads the messages and returns.
+ * - If the RX FIFO does not have enough messages, this function the messages in RX FIFO
+ *   and returns the actual read count.
+ * - During message reading, if RX FIFO is empty and locked, in this case peer CPU will not
+ *   send message until current CPU send lock ack message. Then this function
+ *   returns the message count actually received, and sets  needAckLock to true
+ *   to inform upper layer.
+ *
+ * param link IMU link.
+ * param msgs The buffer to read messages.
+ * param desiredMsgCount Desired read count, one message is a 32-bit word.
+ * param needAckLock Upper layer should always check this value. When this is
+ * set to true by this function, upper layer should send lock ack message to peer CPU.
+ * return Count of messages actually received.
+ */
+int32_t IMU_TryReceiveMsgs(imu_link_t link, uint32_t *msgs, int32_t desiredMsgCount, bool *needAckLock)
+{
+    int32_t receivedCount = 0;
+    int32_t rxFifoMsgCount;
+    int32_t countToRead;
+    uint32_t rxFifoStatus;
+    bool localNeedAckLock = false;
+
+    while (true)
+    {
+        rxFifoStatus = IMU_RX_FIFO_STATUS(link);
+
+        rxFifoMsgCount = (int32_t)(uint32_t)IMU_RX_FIFO_MSG_COUNT_FROM_STATUS(rxFifoStatus);
+
+        if (0 == rxFifoMsgCount)
+        {
+            if (IMU_RX_FIFO_LOCKED_FROM_STATUS(rxFifoStatus))
+            {
+                localNeedAckLock = true;
+            }
+            break;
+        }
+
+        /*
+         * Dont need to check RX FIFO lock status, only notify upper layer
+         * when last message read out.
+         */
+        if (0 == desiredMsgCount)
+        {
+            break;
+        }
+
+        countToRead = MIN(desiredMsgCount, rxFifoMsgCount);
+        receivedCount += countToRead;
+        desiredMsgCount -= countToRead;
+
+        while (0 != (countToRead--))
+        {
+            *msgs++ = IMU_RD_MSG(link);
+        }
+    }
+
+    if (needAckLock != NULL)
+    {
+        *needAckLock = localNeedAckLock;
+    }
+
+    return receivedCount;
+}
+
+/*
+ * Blocking to receive messages.
+ *
+ * This function blocks until all desired messages have been received or the RX FIFO
+ * is locked.
+ *
+ * - If the RX FIFO has enough messages, this function reads the messages and returns.
+ * - If the RX FIFO does not have enough messages, this function waits for the new
+ *   messages.
+ * - During message reading, if RX FIFO is empty and locked, in this case peer CPU will not
+ *   send message until current CPU send lock ack message. Then this function
+ *   returns the message count actually received, and sets  needAckLock to true
+ *   to inform upper layer.
+ *
+ * param link IMU link.
+ * param msgs The buffer to read messages.
+ * param desiredMsgCount Desired read count, one message is a 32-bit word.
+ * param needAckLock Upper layer should always check this value. When this is
+ * set to true by this function, upper layer should send lock ack message to peer CPU.
+ * return Count of messages actually received.
+ */
+int32_t IMU_ReceiveMsgsBlocking(imu_link_t link, uint32_t *msgs, int32_t desiredMsgCount, bool *needAckLock)
+{
+    int32_t receivedCount = 0;
+    int32_t rxFifoMsgCount;
+    int32_t countToRead;
+    uint32_t rxFifoStatus;
+    bool localNeedAckLock;
+
+    while (true)
+    {
+        rxFifoStatus = IMU_RX_FIFO_STATUS(link);
+
+        rxFifoMsgCount = (int32_t)(uint32_t)IMU_RX_FIFO_MSG_COUNT_FROM_STATUS(rxFifoStatus);
+
+        if ((0 == rxFifoMsgCount) && (IMU_RX_FIFO_LOCKED_FROM_STATUS(rxFifoStatus)))
+        {
+            localNeedAckLock = true;
+            break;
+        }
+
+        if (0 == desiredMsgCount)
+        {
+            localNeedAckLock = false;
+            break;
+        }
+
+        countToRead = MIN(desiredMsgCount, rxFifoMsgCount);
+        receivedCount += countToRead;
+        desiredMsgCount -= countToRead;
+
+        while (0 != (countToRead--))
+        {
+            *msgs++ = IMU_RD_MSG(link);
+        }
+    }
+
+    if (NULL != needAckLock)
+    {
+        *needAckLock = localNeedAckLock;
+    }
+
+    return receivedCount;
+}
+
+/*
+ * brief Blocking to send messages pointer.
+ *
+ * Compared with @ref IMU_SendMsgsBlocking, this function fills message pointer
+ * to TX FIFO, but not the message content.
+ *
+ * This function blocks until the message pointer is filled to TX FIFO.
+ *
+ * - If the TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED.
+ * - If TX FIFO not locked, this function waits the available empty slot in TX FIFO,
+ *   and fills the message pointer to TX FIFO.
+ * - To lock TX FIFO after filling the message pointer, set lockSendFifo to true.
+ *
+ * param link IMU link.
+ * param msgPtr The buffer pointer to message to send.
+ * param needAckLock Upper layer should always check this value. When this is
+ * set to true by this function, upper layer should send lock ack message to peer CPU.
+ * retval 0 The message pointer set successfully.
+ * retval IMU_ERR_TX_FIFO_LOCKED The TX FIFO is locked, send failed.
+ */
+int32_t IMU_SendMsgPtrBlocking(imu_link_t link, uint32_t msgPtr, bool lockSendFifo)
+{
+    int32_t ret = 0;
+
+    if (IMU_TX_FIFO_LOCKED(link))
+    {
+        ret = IMU_ERR_TX_FIFO_LOCKED;
+    }
+    else
+    {
+        while (IMU_TX_FIFO_ALMOST_FULL(link))
+        {
+        }
+
+        if (lockSendFifo)
+        {
+            IMU_LOCK_TX_FIFO(link);
+        }
+
+        IMU_WR_MSG(link, msgPtr);
+    }
+
+    return ret;
+}
+
+/*
+ * brief Flush the send FIFO.
+ *
+ * Flush all messages in send FIFO.
+ *
+ * param link IMU link.
+ */
+void IMU_FlushSendFifo(imu_link_t link)
+{
+    IMU_TX_FIFO_CNTL(link) |= IMU_MSG_FIFO_CNTL_FIFO_FLUSH_MASK;
+    IMU_TX_FIFO_CNTL(link) &= ~IMU_MSG_FIFO_CNTL_FIFO_FLUSH_MASK;
+}
+
+/*
+ * Gets the IMU status flags.
+ *
+ * param link IMU link.
+ * return Bit mask of the IMU status flags, see _imu_status_flags.
+ */
+uint32_t IMU_GetStatusFlags(imu_link_t link)
+{
+    uint32_t txFifoStatus = IMU_TX_FIFO_STATUS(link);
+    uint32_t rxFifoStatus = IMU_RX_FIFO_STATUS(link);
+
+    return txFifoStatus | (rxFifoStatus << 8U);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_imu.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_imu.h
new file mode 100644
index 0000000000..f7275d7709
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_imu.h
@@ -0,0 +1,447 @@
+/*
+ * Copyright 2020-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_IMU_H_
+#define FSL_IMU_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup imu
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief IMU driver version. */
+#define FSL_IMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @} */
+
+#define IMU_MSG_FIFO_STATUS_MSG_FIFO_LOCKED_MASK      (1UL)
+#define IMU_MSG_FIFO_STATUS_MSG_FIFO_ALMOST_FULL_MASK (1UL << 1U)
+#define IMU_MSG_FIFO_STATUS_MSG_FIFO_FULL_MASK        (1UL << 2U)
+#define IMU_MSG_FIFO_STATUS_MSG_FIFO_EMPTY_MASK       (1UL << 3U)
+#define IMU_MSG_FIFO_STATUS_MSG_COUNT_MASK            (0x1FUL << 4U)
+#define IMU_MSG_FIFO_STATUS_MSG_COUNT_SHIFT           (4U)
+#define IMU_MSG_FIFO_STATUS_WR_PTR_MASK               (0xFUL << 16U)
+#define IMU_MSG_FIFO_STATUS_WR_PTR_SHIFT              (16U)
+#define IMU_MSG_FIFO_STATUS_RD_PTR_MASK               (0xFUL << 20U)
+#define IMU_MSG_FIFO_STATUS_RD_PTR_SHIFT              (20U)
+
+#define IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK      (1UL << 0U)
+#define IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK        (1UL << 1U)
+#define IMU_MSG_FIFO_CNTL_FIFO_FLUSH_MASK           (1UL << 16U)
+#define IMU_MSG_FIFO_CNTL_WAIT_FOR_ACK_MASK         (1UL << 17U)
+#define IMU_MSG_FIFO_CNTL_FIFO_FULL_WATERMARK_MASK  (0x0FUL << 20U)
+#define IMU_MSG_FIFO_CNTL_FIFO_FULL_WATERMARK_SHIFT (20U)
+#define IMU_MSG_FIFO_CNTL_FIFO_FULL_WATERMARK(x)    (((uint32_t)(x)) << 20U)
+
+/* Write message directly. */
+#define IMU_WR_MSG(link, msg) (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->WR_MSG = (msg))
+
+/* Read message directly. */
+#define IMU_RD_MSG(link) (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->RD_MSG)
+
+/* Check whether RX FIFO is locked. */
+#define IMU_RX_FIFO_LOCKED(link) \
+    (0UL !=                      \
+     (((IMU_Type *)(uintptr_t)IMU_PEER_CPU_BASE(link))->MSG_FIFO_STATUS & IMU_MSG_FIFO_STATUS_MSG_FIFO_LOCKED_MASK))
+
+/* Check whether TX FIFO is locked. */
+#define IMU_TX_FIFO_LOCKED(link) \
+    (0UL !=                      \
+     (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_STATUS & IMU_MSG_FIFO_STATUS_MSG_FIFO_LOCKED_MASK))
+
+/* Check whether TX FIFO is almost full. */
+#define IMU_TX_FIFO_ALMOST_FULL(link)                                           \
+    (0UL != (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_STATUS & \
+             IMU_MSG_FIFO_STATUS_MSG_FIFO_ALMOST_FULL_MASK))
+
+/*! @brief Get Rx FIFO empty status. */
+#define IMU_RX_FIFO_EMPTY(link) \
+    (0UL !=                     \
+     (((IMU_Type *)(uintptr_t)IMU_PEER_CPU_BASE(link))->MSG_FIFO_STATUS & IMU_MSG_FIFO_STATUS_MSG_FIFO_EMPTY_MASK))
+
+/* Lock the TX FIFO. */
+#define IMU_LOCK_TX_FIFO(link) \
+    (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL |= IMU_MSG_FIFO_CNTL_WAIT_FOR_ACK_MASK)
+
+/* Unlock the TX FIFO. */
+#define IMU_UNLOCK_TX_FIFO(link) \
+    (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL &= ~IMU_MSG_FIFO_CNTL_WAIT_FOR_ACK_MASK)
+
+/* Get message count in RX FIFO. */
+#define IMU_RX_FIFO_MSG_COUNT(link)                                                                              \
+    ((((IMU_Type *)(uintptr_t)IMU_PEER_CPU_BASE(link))->MSG_FIFO_STATUS & IMU_MSG_FIFO_STATUS_MSG_COUNT_MASK) >> \
+     IMU_MSG_FIFO_STATUS_MSG_COUNT_SHIFT)
+
+/* Get message count in TX FIFO. */
+#define IMU_TX_FIFO_MSG_COUNT(link)                                                                             \
+    ((((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_STATUS & IMU_MSG_FIFO_STATUS_MSG_COUNT_MASK) >> \
+     IMU_MSG_FIFO_STATUS_MSG_COUNT_SHIFT)
+
+/* Get message count from RX FIFO status register value. */
+#define IMU_RX_FIFO_MSG_COUNT_FROM_STATUS(rxFifoStatus) \
+    (((rxFifoStatus)&IMU_MSG_FIFO_STATUS_MSG_COUNT_MASK) >> IMU_MSG_FIFO_STATUS_MSG_COUNT_SHIFT)
+
+/* Get RX FIFO lock status from RX FIFO status register value. */
+#define IMU_RX_FIFO_LOCKED_FROM_STATUS(rxFifoStatus) (0UL != ((rxFifoStatus)&IMU_MSG_FIFO_STATUS_MSG_FIFO_LOCKED_MASK))
+
+/* TX FIFO status register. */
+#define IMU_TX_FIFO_STATUS(link) (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_STATUS)
+
+/* RX FIFO status register. */
+#define IMU_RX_FIFO_STATUS(link) (((IMU_Type *)(uintptr_t)IMU_PEER_CPU_BASE(link))->MSG_FIFO_STATUS)
+
+/* RX FIFO control register. */
+#define IMU_TX_FIFO_CNTL(link) (((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL)
+
+/*! @brief IMU driver returned error value. */
+#define IMU_ERR_TX_FIFO_LOCKED (-1L)
+
+/*! @brief Maximum message numbers in FIFO. */
+#define IMU_MSG_FIFO_MAX_COUNT 16U
+
+/*! @brief Maximum message FIFO warter mark. */
+#define IMU_MAX_MSG_FIFO_WATER_MARK (IMU_MSG_FIFO_MAX_COUNT - 1U)
+
+/* IMP: ICC_MAX_MSG_CNT should be power of 2 */
+#define IMU_FIFO_SW_WRAPAROUND(ptr) ((ptr) & (IMU_MSG_FIFO_MAX_COUNT - 1U))
+
+#define IMU_WR_PTR(link)                                                                   \
+    IMU_FIFO_SW_WRAPAROUND((IMU_TX_FIFO_STATUS(link) & IMU_MSG_FIFO_STATUS_WR_PTR_MASK) >> \
+                           IMU_MSG_FIFO_STATUS_WR_PTR_SHIFT)
+
+#define IMU_RD_PTR(link)                                                                   \
+    IMU_FIFO_SW_WRAPAROUND((IMU_RX_FIFO_STATUS(link) & IMU_MSG_FIFO_STATUS_RD_PTR_MASK) >> \
+                           IMU_MSG_FIFO_STATUS_RD_PTR_SHIFT)
+
+/*!
+ * @brief IMU status flags.
+ * @anchor _imu_status_flags
+ */
+enum _imu_status_flags
+{
+    kIMU_TxFifoEmpty      = IMU_MSG_FIFO_STATUS_MSG_FIFO_EMPTY_MASK,
+    kIMU_TxFifoFull       = IMU_MSG_FIFO_STATUS_MSG_FIFO_FULL_MASK,
+    kIMU_TxFifoAlmostFull = IMU_MSG_FIFO_STATUS_MSG_FIFO_ALMOST_FULL_MASK,
+    kIMU_TxFifoLocked     = IMU_MSG_FIFO_STATUS_MSG_FIFO_LOCKED_MASK,
+    kIMU_RxFifoEmpty      = IMU_MSG_FIFO_STATUS_MSG_FIFO_EMPTY_MASK << 8U,
+    kIMU_RxFifoFull       = IMU_MSG_FIFO_STATUS_MSG_FIFO_FULL_MASK << 8U,
+    kIMU_RxFifoAlmostFull = IMU_MSG_FIFO_STATUS_MSG_FIFO_ALMOST_FULL_MASK << 8U,
+    kIMU_RxFifoLocked     = IMU_MSG_FIFO_STATUS_MSG_FIFO_LOCKED_MASK << 8U,
+};
+
+/*!
+ * @brief IMU interrupt.
+ * @anchor _imu_interrupts
+ */
+enum _imu_interrupts
+{
+    kIMU_RxMsgReadyInterrupt           = IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK,
+    kIMU_TxFifoSpaceAvailableInterrupt = IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK,
+};
+
+/*! @brief IMU register structure. */
+typedef struct
+{
+    volatile uint32_t WR_MSG;
+    const volatile uint32_t RD_MSG;
+    const volatile uint32_t MSG_FIFO_STATUS;
+    volatile uint32_t MSG_FIFO_CNTL;
+    const volatile uint32_t RD_MSG_DBG;
+} IMU_Type;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name IMU initialization.
+ * @{
+ */
+
+/*!
+ * @brief Initializes the IMU module.
+ *
+ * This function sets IMU to initialized state, including:
+ *
+ *   - Flush the send FIFO.
+ *   - Unlock the send FIFO.
+ *   - Set the water mark to (IMU_MAX_MSG_FIFO_WATER_MARK)
+ *   - Flush the read FIFO.
+ *
+ * @param link IMU link.
+ * @retval kStatus_InvalidArgument The link is invalid.
+ * @retval kStatus_Success Initialized successfully.
+ */
+status_t IMU_Init(imu_link_t link);
+
+/*!
+ * @brief De-initializes the IMU module.
+ *
+ * @param link IMU link.
+ */
+void IMU_Deinit(imu_link_t link);
+
+/*! @} */
+
+/*!
+ * @name IMU Message
+ * @{
+ */
+
+/*!
+ * @brief Write one message to TX FIFO.
+ *
+ * This function writes message to the TX FIFO, user need to make sure
+ * there is empty space in the TX FIFO, and TX FIFO not locked before
+ * calling this function.
+ *
+ * @param link IMU link.
+ * @param msg The message to send.
+ */
+static inline void IMU_WriteMsg(imu_link_t link, uint32_t msg)
+{
+    IMU_WR_MSG(link, msg);
+}
+
+/*!
+ * @brief Read one message from RX FIFO.
+ *
+ * User need to make sure there is available message in the RX FIFO.
+ *
+ * @param link IMU link.
+ * @return The message.
+ */
+static inline uint32_t IMU_ReadMsg(imu_link_t link)
+{
+    return IMU_RD_MSG(link);
+}
+
+/*!
+ * @brief Blocking to send messages.
+ *
+ * This function blocks until all messages have been filled to TX FIFO.
+ *
+ * - If the TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED.
+ * - If TX FIFO not locked, this function waits the available empty slot in TX FIFO,
+ *   and fills the message to TX FIFO.
+ * - To lock TX FIFO after filling all messages, set @p lockSendFifo to true.
+ *
+ * @param link IMU link.
+ * @param msgs The messages to send.
+ * @param msgCount Message count, one message is a 32-bit word.
+ * @param lockSendFifo If set to true, the TX FIFO is locked after all messages filled to TX FIFO.
+ * @return If TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED,
+ * otherwise, this function returns the actual message count sent out, it equals @p msgCount
+ * because this function is blocking function, it returns until all messages have been
+ * filled into TX FIFO.
+ */
+int32_t IMU_SendMsgsBlocking(imu_link_t link, const uint32_t *msgs, int32_t msgCount, bool lockSendFifo);
+
+/*!
+ * @brief Try to send messages.
+ *
+ * This function is similar with @ref IMU_SendMsgsBlocking, the difference is,
+ * this function tries to send as many as possible, if there is not enough
+ * empty slot in TX FIFO, this function fills messages to available empty slots
+ * and returns how many messages have been filled.
+ *
+ * - If the TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED.
+ * - If TX FIFO not locked, this function fills messages to TX FIFO empty slot,
+ *   and returns how many messages have been filled.
+ * - If @p lockSendFifo is set to true, TX FIFO is locked after all messages have
+ *   been filled to TX FIFO. In other word, TX FIFO is locked if the function
+ *   return value equals @p msgCount, when @p lockSendFifo set to true.
+ *
+ * @param link IMU link.
+ * @param msgs The messages to send.
+ * @param msgCount Message count, one message is a 32-bit word.
+ * @param lockSendFifo If set to true, the TX FIFO is locked after all messages filled to TX FIFO.
+ * @return If TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED,
+ * otherwise, this function returns the actual message count sent out.
+ */
+int32_t IMU_TrySendMsgs(imu_link_t link, const uint32_t *msgs, int32_t msgCount, bool lockSendFifo);
+
+/*!
+ * @brief Try to receive messages.
+ *
+ * This function tries to read messages from RX FIFO. It reads the messages already
+ * exists in RX FIFO and returns the actual read count.
+ *
+ * - If the RX FIFO has enough messages, this function reads the messages and returns.
+ * - If the RX FIFO does not have enough messages, this function the messages in RX FIFO
+ *   and returns the actual read count.
+ * - During message reading, if RX FIFO is empty and locked, in this case peer CPU will not
+ *   send message until current CPU send lock ack message. Then this function
+ *   returns the message count actually received, and sets @p needAckLock to true
+ *   to inform upper layer.
+ *
+ * @param link IMU link.
+ * @param msgs The buffer to read messages.
+ * @param desiredMsgCount Desired read count, one message is a 32-bit word.
+ * @param needAckLock Upper layer should always check this value. When this is
+ * set to true by this function, upper layer should send lock ack message to peer CPU.
+ * @return Count of messages actually received.
+ */
+int32_t IMU_TryReceiveMsgs(imu_link_t link, uint32_t *msgs, int32_t desiredMsgCount, bool *needAckLock);
+
+/*!
+ * @brief Blocking to receive messages.
+ *
+ * This function blocks until all desired messages have been received or the RX FIFO
+ * is locked.
+ *
+ * - If the RX FIFO has enough messages, this function reads the messages and returns.
+ * - If the RX FIFO does not have enough messages, this function waits for the new
+ *   messages.
+ * - During message reading, if RX FIFO is empty and locked, in this case peer CPU will not
+ *   send message until current CPU send lock ack message. Then this function
+ *   returns the message count actually received, and sets @p needAckLock to true
+ *   to inform upper layer.
+ *
+ * @param link IMU link.
+ * @param msgs The buffer to read messages.
+ * @param desiredMsgCount Desired read count, one message is a 32-bit word.
+ * @param needAckLock Upper layer should always check this value. When this is
+ * set to true by this function, upper layer should send lock ack message to peer CPU.
+ * @return Count of messages actually received.
+ */
+int32_t IMU_ReceiveMsgsBlocking(imu_link_t link, uint32_t *msgs, int32_t desiredMsgCount, bool *needAckLock);
+
+/*!
+ * @brief Blocking to send messages pointer.
+ *
+ * Compared with @ref IMU_SendMsgsBlocking, this function fills message pointer
+ * to TX FIFO, but not the message content.
+ *
+ * This function blocks until the message pointer is filled to TX FIFO.
+ *
+ * - If the TX FIFO is locked, this function returns IMU_ERR_TX_FIFO_LOCKED.
+ * - If TX FIFO not locked, this function waits the available empty slot in TX FIFO,
+ *   and fills the message pointer to TX FIFO.
+ * - To lock TX FIFO after filling the message pointer, set @p lockSendFifo to true.
+ *
+ * @param link IMU link.
+ * @param msgPtr The buffer pointer to message to send.
+ * @param needAckLock Upper layer should always check this value. When this is
+ * set to true by this function, upper layer should send lock ack message to peer CPU.
+ * @retval 0 The message pointer set successfully.
+ * @retval IMU_ERR_TX_FIFO_LOCKED The TX FIFO is locked, send failed.
+ */
+int32_t IMU_SendMsgPtrBlocking(imu_link_t link, uint32_t msgPtr, bool lockSendFifo);
+
+/*!
+ * @brief Lock or unlock the TX FIFO.
+ *
+ * @param link IMU link.
+ * @param lock Use true to lock the FIFO, use false to unlock.
+ */
+static inline void IMU_LockSendFifo(imu_link_t link, bool lock)
+{
+    if (lock)
+    {
+        ((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL |= IMU_MSG_FIFO_CNTL_WAIT_FOR_ACK_MASK;
+    }
+    else
+    {
+        ((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL &= ~IMU_MSG_FIFO_CNTL_WAIT_FOR_ACK_MASK;
+    }
+}
+
+/*!
+ * @brief Flush the send FIFO.
+ *
+ * Flush all messages in send FIFO.
+ *
+ * @param link IMU link.
+ */
+void IMU_FlushSendFifo(imu_link_t link);
+
+/*!
+ * @brief Set send FIFO warter mark.
+ *
+ * The warter mark must be less than IMU_MAX_MSG_FIFO_WATER_MARK,
+ * i.e. 0 < waterMark <= IMU_MAX_MSG_FIFO_WATER_MARK.
+ *
+ * @param link IMU link.
+ * @param waterMark Send FIFO warter mark.
+ */
+static inline void IMU_SetSendFifoWaterMark(imu_link_t link, uint8_t waterMark)
+{
+    uint32_t reg = ((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL;
+
+    reg &= ~IMU_MSG_FIFO_CNTL_FIFO_FULL_WATERMARK_MASK;
+    reg |= IMU_MSG_FIFO_CNTL_FIFO_FULL_WATERMARK(waterMark);
+
+    ((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL = reg;
+}
+
+/*!
+ * @brief Get the message count in receive FIFO.
+ *
+ * @param link IMU link.
+ * @return The message count in receive FIFO.
+ */
+static inline uint32_t IMU_GetReceivedMsgCount(imu_link_t link)
+{
+    return IMU_RX_FIFO_MSG_COUNT(link);
+}
+
+/*!
+ * @brief Get the empty slot in send FIFO.
+ *
+ * @param link IMU link.
+ * @return The empty slot count in send FIFO.
+ */
+static inline uint32_t IMU_GetSendFifoEmptySpace(imu_link_t link)
+{
+    return IMU_MSG_FIFO_MAX_COUNT - IMU_TX_FIFO_MSG_COUNT(link) - 1U;
+}
+
+/*! @} */
+
+/*!
+ * @name Status and Interrupt.
+ * @{
+ */
+
+/*!
+ * @brief Gets the IMU status flags.
+ *
+ * @param link IMU link.
+ * @return Bit mask of the IMU status flags, see @ref _imu_status_flags.
+ */
+uint32_t IMU_GetStatusFlags(imu_link_t link);
+
+/*!
+ * @brief Clear the IMU IRQ
+ *
+ * @param link IMU link.
+ * @param mask Bit mask of the interrupts to clear, see @ref _imu_interrupts.
+ */
+static inline void IMU_ClearPendingInterrupts(imu_link_t link, uint32_t mask)
+{
+    ((IMU_Type *)(uintptr_t)IMU_CUR_CPU_BASE(link))->MSG_FIFO_CNTL |= mask;
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*! @} */
+
+#endif /* FSL_IMU_H_*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_io_mux.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_io_mux.h
new file mode 100644
index 0000000000..2f78d3075b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_io_mux.h
@@ -0,0 +1,1805 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IO_MUX_H_
+#define _FSL_IO_MUX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup io_mux
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cns_io_mux"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IO_MUX driver version 2.2.0. */
+#define FSL_IO_MUX_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \<GPIO_0_31_Mask GPIO_32_63_Mask GPIO_FC_SetMask GPIO_FC_ClearMask FSEL_SetMask
+ * FSEL_ClearMask CTimer_SetMask CTimer_ClearMask SCTimerSetMask SCTimerClearMask\>
+ *
+ * GPIO_FC_xxxMask:   bit[0:10] maps to FCn[0:10];
+ *                    bit[15:12] is the register offset from FC0;
+ *                    bit[16] indicates GPIO should be operated;
+ *                    bit[17] indicates SGPIO need to be operated.
+ * CTimer_xxxMask:    bit[0:14] maps to C_TIMER_IN[0:14];
+ *                    bit[16:30] maps to C_TIMER_OUT[0:14].
+ * @{
+ */
+#define IO_MUX_GPIO_FC_MASK(gpio, fcIdx, fcMsk) \
+    (((uint32_t)(gpio) << 16) | (((uint32_t)(fcIdx)&0xFUL) << 12) | ((uint32_t)(fcMsk)&0xFFFUL))
+#define IO_MUX_SGPIO_FLAG(mask) (((uint32_t)(mask) >> 17) & 1UL)
+#define IO_MUX_GPIO_FLAG(mask)  (((uint32_t)(mask) >> 16) & 1UL)
+#define IO_MUX_FC_OFFSET(mask)  (((uint32_t)(mask) >> 12) & 0xFUL)
+#define IO_MUX_FC_MASK(mask)    ((uint32_t)(mask)&0x7FFUL)
+
+#define IO_MUX_CTIMER_MASK(inMsk, outMsk) (((uint32_t)(outMsk) << 16) | ((uint32_t)(inMsk)&0xFFFFUL))
+#define IO_MUX_CTIMER_IN_MASK(mask)       ((uint32_t)(mask)&0x7FFFUL)
+#define IO_MUX_CTIMER_OUT_MASK(mask)      (((uint32_t)(mask) >> 16) & 0x7FFFUL)
+
+#define IO_MUX_SCTIMER_MASK(inMsk, outMsk) ((((uint32_t)(outMsk)&0x3FFUL) << 16) | ((uint32_t)(inMsk)&0xFFUL))
+
+#define IO_MUX_FC0_USART_SCK                                                                   \
+    0x00000010U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0x001), IO_MUX_GPIO_FC_MASK(1, 0, 0x02C), /* GPIO&FC mask */ \
+        0x00000000U, 0x00800000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x2, 0x2)            /* SCTimer mask */
+
+#define IO_MUX_FC0_USART_DATA                                                                  \
+    0x0000000CU, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0x200), IO_MUX_GPIO_FC_MASK(1, 0, 0x12E), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x1, 0x1)            /* SCTimer mask */
+
+#define IO_MUX_FC0_USART_CMD                                                                   \
+    0x00000021U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0x400), IO_MUX_GPIO_FC_MASK(1, 0, 0x038), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000040U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x1, 0x1),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC0_I2C_2_3                                                                     \
+    0x0000000CU, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0x002), IO_MUX_GPIO_FC_MASK(1, 0, 0x32C), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x1, 0x1)            /* SCTimer mask */
+
+#define IO_MUX_FC0_I2S                                                                         \
+    0x0000001CU, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0x004), IO_MUX_GPIO_FC_MASK(1, 0, 0x32B), /* GPIO&FC mask */ \
+        0x00000000U, 0x00800000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x3, 0x3)            /* SCTimer mask */
+
+#define IO_MUX_FC0_I2S_DATA                                                                    \
+    0x00000004U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0x100), IO_MUX_GPIO_FC_MASK(1, 0, 0x22E), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC0_SPI_SS0                                                                     \
+    0x0000001DU, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0x008), IO_MUX_GPIO_FC_MASK(1, 0, 0x737), /* GPIO&FC mask */ \
+        0x00000000U, 0x00800000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x1, 0x1),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x3, 0x3)            /* SCTimer mask */
+
+#define IO_MUX_FC1_USART_SCK                                                                   \
+    0x00000080U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 1, 0x001), IO_MUX_GPIO_FC_MASK(1, 1, 0x0EC), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC1_USART_DATA                                                                  \
+    0x00000300U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 1, 0x200), IO_MUX_GPIO_FC_MASK(1, 1, 0x1EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC1_USART_CMD                                                                   \
+    0x00000440U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 1, 0x400), IO_MUX_GPIO_FC_MASK(1, 1, 0x038), /* GPIO&FC mask */ \
+        0x00000000U, 0x01000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC1_I2C_8_9                                                                     \
+    0x00000300U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 1, 0x002), IO_MUX_GPIO_FC_MASK(1, 1, 0x3EC), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC1_I2S                                                                         \
+    0x00000380U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 1, 0x004), IO_MUX_GPIO_FC_MASK(1, 1, 0x3EB), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC1_I2S_DATA                                                                    \
+    0x00000200U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 1, 0x100), IO_MUX_GPIO_FC_MASK(1, 1, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC1_SPI_SS0                                                                     \
+    0x000003C0U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 1, 0x008), IO_MUX_GPIO_FC_MASK(1, 1, 0x7F7), /* GPIO&FC mask */ \
+        0x00000000U, 0x01000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_USART_SCK                                                                   \
+    0x00008000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x001), IO_MUX_GPIO_FC_MASK(1, 2, 0x0EC), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008400U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_USART_DATA                                                                  \
+    0x00006000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x200), IO_MUX_GPIO_FC_MASK(1, 2, 0x1EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x18, 0x18),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_USART_CMD                                                                   \
+    0x00030000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x400), IO_MUX_GPIO_FC_MASK(1, 2, 0x038), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008400U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_I2C_13_14                                                                   \
+    0x00006000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x002), IO_MUX_GPIO_FC_MASK(1, 2, 0x3EC), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x18, 0x18),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_I2C_16_17                                                                   \
+    0x00030000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x010), IO_MUX_GPIO_FC_MASK(1, 2, 0x428), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008400U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_I2S                                                                         \
+    0x0000E000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x004), IO_MUX_GPIO_FC_MASK(1, 2, 0x3EB), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008400U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x18, 0x18),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_I2S_DATA                                                                    \
+    0x00002000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x100), IO_MUX_GPIO_FC_MASK(1, 2, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x18, 0x18),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC2_SPI_SS0                                                                     \
+    0x0001E000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 2, 0x008), IO_MUX_GPIO_FC_MASK(1, 2, 0x7F7), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008400U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x18, 0x18),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC3_USART_SCK                                                                   \
+    0x02000000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x001), IO_MUX_GPIO_FC_MASK(1, 3, 0x0EC), /* GPIO&FC mask */ \
+        0x00000000U, 0x00010000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x80, 0x80),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC3_USART_DATA                                                                  \
+    0x05000000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x200), IO_MUX_GPIO_FC_MASK(1, 3, 0x1EE), /* GPIO&FC mask */ \
+        0x00000000U, 0xC0000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x40, 0x40),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x10, 0x10)          /* SCTimer mask */
+
+#define IO_MUX_FC3_USART_CMD                                                                   \
+    0x00180000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x400), IO_MUX_GPIO_FC_MASK(1, 3, 0x038), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC3_I2C_24_26                                                                   \
+    0x05000000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x002), IO_MUX_GPIO_FC_MASK(1, 3, 0x3EC), /* GPIO&FC mask */ \
+        0x00000000U, 0xC0000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x40, 0x40),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x10, 0x10)          /* SCTimer mask */
+
+#define IO_MUX_FC3_I2C_19_20                                                                   \
+    0x00180000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x010), IO_MUX_GPIO_FC_MASK(1, 3, 0x428), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC3_I2S                                                                         \
+    0x07000000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x004), IO_MUX_GPIO_FC_MASK(1, 3, 0x3EB), /* GPIO&FC mask */ \
+        0x00000000U, 0xC0010000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0xC0, 0xC0),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x10, 0x10)          /* SCTimer mask */
+
+#define IO_MUX_FC3_I2S_DATA                                                                    \
+    0x01000000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x100), IO_MUX_GPIO_FC_MASK(1, 3, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x40000000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x40, 0x40),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC3_SPI_SS0                                                                     \
+    0x07100000U, 0x00000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 3, 0x008), IO_MUX_GPIO_FC_MASK(1, 3, 0x7F7), /* GPIO&FC mask */ \
+        0x00000000U, 0xC0018000U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0xC0, 0xC0),           /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x10, 0x10)          /* SCTimer mask */
+
+#define IO_MUX_FC14_USART_SCK                                                                  \
+    0x00000000U, 0x00400000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 6, 0x001), IO_MUX_GPIO_FC_MASK(3, 6, 0x0EC), /* GPIO&FC mask */ \
+        0x00000000U, 0x00200810U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4000, 0x4000),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC14_USART_DATA                                                                 \
+    0x00000000U, 0x03000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 6, 0x200), IO_MUX_GPIO_FC_MASK(3, 6, 0x1EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x08000800U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC14_USART_CMD                                                                  \
+    0x00000000U, 0x00A00000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 6, 0x400), IO_MUX_GPIO_FC_MASK(3, 6, 0x038), /* GPIO&FC mask */ \
+        0x00000000U, 0x00500810U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x2000, 0x2000),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0x200)            /* SCTimer mask */
+
+#define IO_MUX_FC14_I2C_56_57                                                                  \
+    0x00000000U, 0x03000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 6, 0x002), IO_MUX_GPIO_FC_MASK(3, 6, 0x3EC), /* GPIO&FC mask */ \
+        0x00000000U, 0x08000800U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC14_I2S                                                                        \
+    0x00000000U, 0x03400000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 6, 0x004), IO_MUX_GPIO_FC_MASK(3, 6, 0x3EB), /* GPIO&FC mask */ \
+        0x00000000U, 0x08200810U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4000, 0x4000),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC14_I2S_DATA                                                                   \
+    0x00000000U, 0x02000000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 6, 0x100), IO_MUX_GPIO_FC_MASK(3, 6, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x08000800U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),                 /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_FC14_SPI_SS0                                                                    \
+    0x00000000U, 0x03600000U,                                               /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 6, 0x008), IO_MUX_GPIO_FC_MASK(3, 6, 0x7F7), /* GPIO&FC mask */ \
+        0x00000000U, 0x08300810U,                                           /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x6000, 0x6000),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)                /* SCTimer mask */
+
+#define IO_MUX_QUAD_SPI_FLASH                                                          \
+    0xF0000000U, 0x00000007U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000002U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_QUAD_SPI_PSRAM                                                          \
+    0x00000000U, 0x000003F8U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000008U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x700, 0x700), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0xC0, 0xC0)  /* SCTimer mask */
+
+#define IO_MUX_PDM                                                                         \
+    0x00000000U, 0x00780000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x4FD), /* GPIO&FC mask */ \
+        0x00000010U, 0x003C0800U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x7800, 0x7800),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_USB                                                                         \
+    0x00001000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 1, 0x080), /* GPIO&FC mask */ \
+        0x00000020U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4, 0x4),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_0                                                                   \
+    0x00000008U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x22E), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x1), IO_MUX_SCTIMER_MASK(0x1, 0)        /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_1                                                                   \
+    0x00000010U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x02D), /* GPIO&FC mask */ \
+        0x00000000U, 0x00800000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x2), IO_MUX_SCTIMER_MASK(0x2, 0)        /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_8                                                                   \
+    0x00000800U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 1, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x100), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_4                                                                   \
+    0x04000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x80000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x10), IO_MUX_SCTIMER_MASK(0x10, 0)      /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_5                                                               \
+    0x08000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x10000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x20), IO_MUX_SCTIMER_MASK(0x20, 0)  /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_6                                                               \
+    0x00000000U, 0x00000008U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x40), IO_MUX_SCTIMER_MASK(0x40, 0)  /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_7                                                               \
+    0x00000000U, 0x00000010U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x80), IO_MUX_SCTIMER_MASK(0x80, 0)  /* SCTimer mask */
+
+#define IO_MUX_SCT_OUT_9                                                                   \
+    0x00000000U, 0x00800000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x430), /* GPIO&FC mask */ \
+        0x00000000U, 0x00400000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0x200), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_0                                                                    \
+    0x00000008U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x22E), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x1, 0), IO_MUX_SCTIMER_MASK(0, 0x1)        /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_1                                                                    \
+    0x00000010U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x02D), /* GPIO&FC mask */ \
+        0x00000000U, 0x00800000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x2, 0), IO_MUX_SCTIMER_MASK(0, 0x2)        /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_2                                                                    \
+    0x00400000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x4, 0), IO_MUX_SCTIMER_MASK(0, 0)          /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_3                                                                    \
+    0x00800000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x8, 0), IO_MUX_SCTIMER_MASK(0, 0)          /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_4                                                                    \
+    0x04000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x80000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x10, 0), IO_MUX_SCTIMER_MASK(0, 0x10)      /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_5                                                                \
+    0x08000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x10000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x20, 0), IO_MUX_SCTIMER_MASK(0, 0x20)  /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_6                                                                \
+    0x00000000U, 0x00000008U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x40, 0), IO_MUX_SCTIMER_MASK(0, 0x40)  /* SCTimer mask */
+
+#define IO_MUX_SCT_IN_7                                                                \
+    0x00000000U, 0x00000010U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0x80, 0), IO_MUX_SCTIMER_MASK(0, 0x80)  /* SCTimer mask */
+
+#define IO_MUX_CT0_MAT0_OUT                                                                \
+    0x00000001U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x1), IO_MUX_CTIMER_MASK(0x1, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT0_MAT1_OUT                                                            \
+    0x00000002U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x2), IO_MUX_CTIMER_MASK(0x2, 0),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT0_MAT2_OUT                                                                \
+    0x00001000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 1, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000020U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x4), IO_MUX_CTIMER_MASK(0x4, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT0_MAT3_OUT                                                                \
+    0x00002000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x8), IO_MUX_CTIMER_MASK(0x8, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT1_MAT0_OUT                                                                \
+    0x00004000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x10), IO_MUX_CTIMER_MASK(0x10, 0),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT1_MAT1_OUT                                                                \
+    0x00200000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x20), IO_MUX_CTIMER_MASK(0x20, 0),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT1_MAT2_OUT                                                                \
+    0x01000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x40000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x40), IO_MUX_CTIMER_MASK(0x40, 0),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT1_MAT3_OUT                                                                \
+    0x02000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x0ED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00010000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x80), IO_MUX_CTIMER_MASK(0x80, 0),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT2_MAT0_OUT                                                            \
+    0x00000000U, 0x00000020U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x100), IO_MUX_CTIMER_MASK(0x100, 0), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT2_MAT1_OUT                                                            \
+    0x00000000U, 0x00000040U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x200), IO_MUX_CTIMER_MASK(0x200, 0), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT2_MAT2_OUT                                                            \
+    0x00000000U, 0x00000080U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x400), IO_MUX_CTIMER_MASK(0x400, 0), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT2_MAT3_OUT                                                                \
+    0x00000000U, 0x00080000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00040810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x800), IO_MUX_CTIMER_MASK(0x800, 0),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT3_MAT0_OUT                                                                \
+    0x00000000U, 0x00100000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x00080810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x1000), IO_MUX_CTIMER_MASK(0x1000, 0),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT3_MAT1_OUT                                                                \
+    0x00000000U, 0x00200000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00100810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x2000), IO_MUX_CTIMER_MASK(0x2000, 0),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT3_MAT2_OUT                                                               \
+    0x00000000U, 0x00400000U,                                          /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0xED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00200810U,                                      /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0x4000), IO_MUX_CTIMER_MASK(0x4000, 0),  /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)           /* SCTimer mask */
+
+#define IO_MUX_CT_INP0                                                                     \
+    0x00000001U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x1, 0), IO_MUX_CTIMER_MASK(0, 0x1),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP1                                                                 \
+    0x00000002U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x2, 0), IO_MUX_CTIMER_MASK(0, 0x2),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT_INP2                                                                     \
+    0x00001000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 1, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000020U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x4, 0), IO_MUX_CTIMER_MASK(0, 0x4),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP3                                                                     \
+    0x00002000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x8, 0), IO_MUX_CTIMER_MASK(0, 0x8),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP4                                                                     \
+    0x00004000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x10, 0), IO_MUX_CTIMER_MASK(0, 0x10),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP5                                                                     \
+    0x00200000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x20, 0), IO_MUX_CTIMER_MASK(0, 0x20),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP6                                                                     \
+    0x01000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x40000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x40, 0), IO_MUX_CTIMER_MASK(0, 0x40),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP7                                                                     \
+    0x02000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x0ED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00010000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x80, 0), IO_MUX_CTIMER_MASK(0, 0x80),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP8                                                                 \
+    0x00000000U, 0x00000020U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x100, 0), IO_MUX_CTIMER_MASK(0, 0x100), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT_INP9                                                                 \
+    0x00000000U, 0x00000040U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x200, 0), IO_MUX_CTIMER_MASK(0, 0x200), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT_INP10                                                                \
+    0x00000000U, 0x00000080U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x400, 0), IO_MUX_CTIMER_MASK(0, 0x400), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_CT_INP11                                                                    \
+    0x00000000U, 0x00080000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00040810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x800, 0), IO_MUX_CTIMER_MASK(0, 0x800),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP12                                                                    \
+    0x00000000U, 0x00100000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x00080810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x1000, 0), IO_MUX_CTIMER_MASK(0, 0x1000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP13                                                                    \
+    0x00000000U, 0x00200000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00100810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x2000, 0), IO_MUX_CTIMER_MASK(0, 0x2000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_CT_INP14                                                                   \
+    0x00000000U, 0x00400000U,                                          /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0xED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00200810U,                                      /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0x4000, 0), IO_MUX_CTIMER_MASK(0, 0x4000),  /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)           /* SCTimer mask */
+
+#define IO_MUX_MCLK                                                                        \
+    0x00000020U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x430), /* GPIO&FC mask */ \
+        0x00000040U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_UTICK                                                                       \
+    0x00078000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x4FD), /* GPIO&FC mask */ \
+        0x00000200U, 0x0000C400U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_USIM                                                                        \
+    0x00078000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x4FD), /* GPIO&FC mask */ \
+        0x00000400U, 0x0000C200U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_LCD_8080                                                                    \
+    0x00000000U, 0x037BFC00U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x7FF), /* GPIO&FC mask */ \
+        0x00000800U, 0x083C1010U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x7800, 0x7800),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_LCD_SPI                                                                 \
+    0x00000000U, 0x0003F000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00001000U, 0x00000800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_FREQ_GPIO_CLK                                                           \
+    0x00000000U, 0x00040000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00002000U, 0x00020000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO_INT_BMATCH                                                             \
+    0x00040000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 2, 0x080), /* GPIO&FC mask */ \
+        0x00004000U, 0x00008600U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GAU_TRIGGER0                                                            \
+    0x00000000U, 0x00040000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x00020000U, 0x00002000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_ACOMP0_GPIO_OUT                                                             \
+    0x00000000U, 0x00080000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x040), /* GPIO&FC mask */ \
+        0x00040000U, 0x00000810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x800, 0x800),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_ACOMP0_EDGE_PULSE                                                           \
+    0x00000000U, 0x00100000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x080), /* GPIO&FC mask */ \
+        0x00080000U, 0x00000810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x1000, 0x1000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_ACOMP1_GPIO_OUT                                                             \
+    0x00000000U, 0x00200000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x418), /* GPIO&FC mask */ \
+        0x00100000U, 0x00000810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x2000, 0x2000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_ACOMP1_EDGE_PULSE                                                           \
+    0x00000000U, 0x00400000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x0ED), /* GPIO&FC mask */ \
+        0x00200000U, 0x00000810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4000, 0x4000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GAU_TRIGGER1                                                                \
+    0x00000000U, 0x00800000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x430), /* GPIO&FC mask */ \
+        0x00400000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0x200)        /* SCTimer mask */
+
+#define IO_MUX_SDIO                                                                      \
+    0x001F9000U, 0x00000000U,                                         /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0xF, 0), /* GPIO&FC mask */ \
+        0x00008000U, 0x00004620U,                                     /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4, 0x4),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)          /* SCTimer mask */
+
+#define IO_MUX_ENET_CLK                                                                    \
+    0x02000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x0ED), /* GPIO&FC mask */ \
+        0x00010000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x80, 0x80),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_ENET_RX                                                                     \
+    0x00C00000U, 0xC0000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x0C0), /* GPIO&FC mask */ \
+        0x04000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0xC, 0)          /* SCTimer mask */
+
+#define IO_MUX_ENET_TX                                                                 \
+    0x00000000U, 0x1C000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x02000000U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_ENET_MDIO                                                                   \
+    0x00000000U, 0x03000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 6, 0x3EE), /* GPIO&FC mask */ \
+        0x08000000U, 0x00000800U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_ENET_TIMER0                                                             \
+    0x08000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x10000000U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x20, 0x20)  /* SCTimer mask */
+
+#define IO_MUX_ENET_TIMER1                                                             \
+    0x00000000U, 0x20000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(3, 0, 0), /* GPIO&FC mask */ \
+        0x20000000U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_ENET_TIMER2                                                                 \
+    0x01000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x3EE), /* GPIO&FC mask */ \
+        0x40000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x40, 0x40),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_ENET_TIMER3                                                                 \
+    0x04000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x2EE), /* GPIO&FC mask */ \
+        0x80000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x10, 0x10)      /* SCTimer mask */
+
+#define IO_MUX_CLKIN_FRM_PD                                                                \
+    0x00000010U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0x02D), /* GPIO&FC mask */ \
+        0x00800000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x2, 0x2)        /* SCTimer mask */
+
+#define IO_MUX_GPIO0                                                                       \
+    0x00000001U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x1, 0x1),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO1                                                                   \
+    0x00000002U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x2, 0x2),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO2                                                                       \
+    0x00000004U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0x32E), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO3                                                                       \
+    0x00000008U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0x22E), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x1, 0x1)        /* SCTimer mask */
+
+#define IO_MUX_GPIO4                                                                       \
+    0x00000010U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0x02D), /* GPIO&FC mask */ \
+        0x00000000U, 0x00800000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x2, 0x2)        /* SCTimer mask */
+
+#define IO_MUX_GPIO5                                                                       \
+    0x00000020U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0x430), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO6                                                                       \
+    0x00000040U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 1, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x01000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO7                                                                       \
+    0x00000080U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 1, 0x0ED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO8                                                                       \
+    0x00000100U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 1, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO9                                                                       \
+    0x00000200U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 1, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO10                                                                      \
+    0x00000400U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 1, 0x430), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO11                                                                      \
+    0x00000800U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 1, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0x100)        /* SCTimer mask */
+
+#define IO_MUX_GPIO12                                                                      \
+    0x00001000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 1, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008020U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4, 0x4),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO13                                                                      \
+    0x00002000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 2, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x8, 0x8),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO14                                                                      \
+    0x00004000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 2, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x10, 0x10),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO15                                                                      \
+    0x00008000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 2, 0x0ED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008600U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO16                                                                      \
+    0x00010000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 2, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008600U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO17                                                                      \
+    0x00020000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 2, 0x430), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008600U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO18                                                                      \
+    0x00040000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 2, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x0000C600U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO19                                                                      \
+    0x00080000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 3, 0x430), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO20                                                                      \
+    0x00100000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 3, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00008000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO21                                                                      \
+    0x00200000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 2, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x20, 0x20),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO22                                                                      \
+    0x00400000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 3, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x4, 0)          /* SCTimer mask */
+
+#define IO_MUX_GPIO23                                                                      \
+    0x00800000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 3, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x8, 0)          /* SCTimer mask */
+
+#define IO_MUX_GPIO24                                                                      \
+    0x01000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 3, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x40000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x40, 0x40),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO25                                                                      \
+    0x02000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 3, 0x0ED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00010000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x80, 0x80),       /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO26                                                                      \
+    0x04000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 3, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x80000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x10, 0x10)      /* SCTimer mask */
+
+#define IO_MUX_GPIO27                                                                  \
+    0x08000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x10000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x20, 0x20)  /* SCTimer mask */
+
+#define IO_MUX_GPIO28                                                                  \
+    0x10000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO29                                                                  \
+    0x20000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO30                                                                  \
+    0x40000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO31                                                                  \
+    0x80000000U, 0x00000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(0, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO32                                                                  \
+    0x00000000U, 0x00000001U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO33                                                                  \
+    0x00000000U, 0x00000002U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO34                                                                  \
+    0x00000000U, 0x00000004U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO35                                                                  \
+    0x00000000U, 0x00000008U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x40, 0x40)  /* SCTimer mask */
+
+#define IO_MUX_GPIO36                                                                  \
+    0x00000000U, 0x00000010U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x80, 0x80)  /* SCTimer mask */
+
+#define IO_MUX_GPIO37                                                                  \
+    0x00000000U, 0x00000020U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x100, 0x100), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO38                                                                  \
+    0x00000000U, 0x00000040U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x200, 0x200), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO39                                                                  \
+    0x00000000U, 0x00000080U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x400, 0x400), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO40                                                                  \
+    0x00000000U, 0x00000100U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO41                                                                  \
+    0x00000000U, 0x00000200U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO42                                                                  \
+    0x00000000U, 0x00000400U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO43                                                                  \
+    0x00000000U, 0x00000800U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO44                                                                  \
+    0x00000000U, 0x00001000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO45                                                                  \
+    0x00000000U, 0x00002000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO46                                                                  \
+    0x00000000U, 0x00004000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO47                                                                  \
+    0x00000000U, 0x00008000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO48                                                                  \
+    0x00000000U, 0x00010000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO49                                                                  \
+    0x00000000U, 0x00020000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO50                                                                  \
+    0x00000000U, 0x00040000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00022000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO51                                                                      \
+    0x00000000U, 0x00080000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 6, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00040810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x800, 0x800),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO52                                                                      \
+    0x00000000U, 0x00100000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 6, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x00080810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x1000, 0x1000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO53                                                                      \
+    0x00000000U, 0x00200000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 6, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00100810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x2000, 0x2000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO54                                                                     \
+    0x00000000U, 0x00400000U,                                          /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 6, 0xED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00200810U,                                      /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4000, 0x4000),  /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)           /* SCTimer mask */
+
+#define IO_MUX_GPIO55                                                                      \
+    0x00000000U, 0x00800000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 6, 0x430), /* GPIO&FC mask */ \
+        0x00000000U, 0x00400000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0x200)        /* SCTimer mask */
+
+#define IO_MUX_GPIO56                                                                      \
+    0x00000000U, 0x01000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 6, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x08000800U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO57                                                                      \
+    0x00000000U, 0x02000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 6, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x08000800U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_GPIO58                                                                  \
+    0x00000000U, 0x04000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x02000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO59                                                                  \
+    0x00000000U, 0x08000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x02000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO60                                                                  \
+    0x00000000U, 0x10000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x02000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO61                                                                  \
+    0x00000000U, 0x20000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x20000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO62                                                                  \
+    0x00000000U, 0x40000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_GPIO63                                                                  \
+    0x00000000U, 0x80000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(1, 0, 0), IO_MUX_GPIO_FC_MASK(2, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO0                                                                  \
+    0x00000000U, 0x00000001U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO1                                                                  \
+    0x00000000U, 0x00000002U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO2                                                                  \
+    0x00000000U, 0x00000004U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000002U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO3                                                                  \
+    0x00000000U, 0x00000008U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x40, 0x40)  /* SCTimer mask */
+
+#define IO_MUX_SGPIO4                                                                  \
+    0x00000000U, 0x00000010U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x80, 0x80)  /* SCTimer mask */
+
+#define IO_MUX_SGPIO5                                                                  \
+    0x00000000U, 0x00000020U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x100, 0x100), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO6                                                                  \
+    0x00000000U, 0x00000040U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x200, 0x200), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO7                                                                  \
+    0x00000000U, 0x00000080U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x400, 0x400), /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO8                                                                  \
+    0x00000000U, 0x00000100U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO9                                                                  \
+    0x00000000U, 0x00000200U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000008U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO10                                                                 \
+    0x00000000U, 0x00000400U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO11                                                                 \
+    0x00000000U, 0x00000800U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00000800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO12                                                                 \
+    0x00000000U, 0x00001000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO13                                                                 \
+    0x00000000U, 0x00002000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO14                                                                 \
+    0x00000000U, 0x00004000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO15                                                                 \
+    0x00000000U, 0x00008000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO16                                                                 \
+    0x00000000U, 0x00010000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO17                                                                 \
+    0x00000000U, 0x00020000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00001800U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO18                                                                 \
+    0x00000000U, 0x00040000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x00022000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO19                                                                     \
+    0x00000000U, 0x00080000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 6, 0x040), /* GPIO&FC mask */ \
+        0x00000000U, 0x00040810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x800, 0x800),     /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_SGPIO20                                                                     \
+    0x00000000U, 0x00100000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 6, 0x080), /* GPIO&FC mask */ \
+        0x00000000U, 0x00080810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x1000, 0x1000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_SGPIO21                                                                     \
+    0x00000000U, 0x00200000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 6, 0x418), /* GPIO&FC mask */ \
+        0x00000000U, 0x00100810U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x2000, 0x2000),   /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_SGPIO22                                                                    \
+    0x00000000U, 0x00400000U,                                          /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 6, 0xED), /* GPIO&FC mask */ \
+        0x00000000U, 0x00200810U,                                      /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0x4000, 0x4000),  /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)           /* SCTimer mask */
+
+#define IO_MUX_SGPIO23                                                                     \
+    0x00000000U, 0x00800000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 6, 0x430), /* GPIO&FC mask */ \
+        0x00000000U, 0x00400000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0x200)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO24                                                                     \
+    0x00000000U, 0x01000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 6, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x08000800U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_SGPIO25                                                                     \
+    0x00000000U, 0x02000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 6, 0x3EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x08000800U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)            /* SCTimer mask */
+
+#define IO_MUX_SGPIO26                                                                 \
+    0x00000000U, 0x04000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x02000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO27                                                                 \
+    0x00000000U, 0x08000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x02000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO28                                                                 \
+    0x00000000U, 0x10000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x02000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO29                                                                 \
+    0x00000000U, 0x20000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x20000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO30                                                                 \
+    0x00000000U, 0x40000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_SGPIO31                                                                 \
+    0x00000000U, 0x80000000U,                                       /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(2, 0, 0), IO_MUX_GPIO_FC_MASK(1, 0, 0), /* GPIO&FC mask */ \
+        0x00000000U, 0x04000000U,                                   /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),         /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0, 0)        /* SCTimer mask */
+
+#define IO_MUX_AON_CAPTURE                                                                 \
+    0x04000000U, 0x00000000U,                                           /* Pin mask */     \
+        IO_MUX_GPIO_FC_MASK(0, 0, 0), IO_MUX_GPIO_FC_MASK(1, 3, 0x2EE), /* GPIO&FC mask */ \
+        0x00000000U, 0x80000000U,                                       /* FSEL mask */    \
+        IO_MUX_CTIMER_MASK(0, 0), IO_MUX_CTIMER_MASK(0, 0),             /* CTimer mask */  \
+        IO_MUX_SCTIMER_MASK(0, 0), IO_MUX_SCTIMER_MASK(0x10, 0x10)      /* SCTimer mask */
+
+/*! @brief IO MUX pin configuration.
+      Bit [1:0] for pull configuration
+      Bit [3:2] for drive strength configuration
+ */
+typedef enum
+{
+    IO_MUX_PinConfigNoPullDriveWeakest   = 0x0U,
+    IO_MUX_PinConfigNoPullDriveWeak      = 0x4U,
+    IO_MUX_PinConfigNoPullDriveStrong    = 0x8U,
+    IO_MUX_PinConfigNoPullDriveStrongest = 0xCU,
+
+    IO_MUX_PinConfigPullUpDriveWeakest   = 0x1U,
+    IO_MUX_PinConfigPullUpDriveWeak      = 0x5U,
+    IO_MUX_PinConfigPullUpDriveStrong    = 0x9U,
+    IO_MUX_PinConfigPullUpDriveStrongest = 0xDU,
+
+    IO_MUX_PinConfigPullDownDriveWeakest   = 0x2U,
+    IO_MUX_PinConfigPullDownDriveWeak      = 0x6U,
+    IO_MUX_PinConfigPullDownDriveStrong    = 0xAU,
+    IO_MUX_PinConfigPullDownDriveStrongest = 0xEU,
+
+    IO_MUX_PinConfigNoPull   = IO_MUX_PinConfigNoPullDriveStrongest,
+    IO_MUX_PinConfigPullUp   = IO_MUX_PinConfigPullUpDriveStrongest,
+    IO_MUX_PinConfigPullDown = IO_MUX_PinConfigPullDownDriveStrongest,
+} io_mux_pin_config_t;
+
+/*! @brief IO MUX sleep pin level */
+typedef enum
+{
+    IO_MUX_SleepPinLevelLow       = 0U,
+    IO_MUX_SleepPinLevelHigh      = 1U,
+    IO_MUX_SleepPinLevelUnchanged = 2U,
+} io_mux_sleep_pin_level_t;
+
+/*@}*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IO_MUX pin mux mode.
+ * @note The parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the GPIO2/GPIO3 as the Flexcomm0 UART RX/TX:
+ * @code
+ * IO_MUX_SetPinMux(IO_MUX_FC0_USART_DATA);
+ * @endcode
+ *
+ * This is an example to set the GPIO6/GPIO10 as Flexcomm1 I2C SDA/SCL:
+ * @code
+ * IO_MUX_SetPinMux(IO_MUX_FC1_I2C_6_10);
+ * @endcode
+ *
+ * @param pinLowMask     The GPIO0-31 pins mask.
+ * @param pinHighMask    The GPIO32-63 pins mask.
+ * @param gpioFcSetMask  The GPIO and Flexcomm registers mask to set, defined by IO_MUX_GPIO_FC_MASK()
+ * @param gpioFcClrMask  The GPIO and Flexcomm registers mask to clear, defined by IO_MUX_GPIO_FC_MASK()
+ * @param fselSetMask    The FSEL register mask to set
+ * @param fselClrMask    The FSEL register mask to clear
+ * @param ctimerSetMask  The C_TIMER_IN/C_TIMER_OUT register mask to set, defined by IO_MUX_CTIMER_MASK()
+ * @param ctimerClrMask  The C_TIMER_IN/C_TIMER_OUT register mask to clear, defined by IO_MUX_CTIMER_MASK()
+ * @param sctimerSetMask The SC_TIMER register mask to set
+ * @param sctimerClrMask The SC_TIMER register mask to clear
+ */
+static inline void IO_MUX_SetPinMux(uint32_t pinLowMask,
+                                    uint32_t pinHighMask,
+                                    uint32_t gpioFcSetMask,
+                                    uint32_t gpioFcClrMask,
+                                    uint32_t fselSetMask,
+                                    uint32_t fselClrMask,
+                                    uint32_t ctimerSetMask,
+                                    uint32_t ctimerClrMask,
+                                    uint32_t sctimerSetMask,
+                                    uint32_t sctimerClrMask)
+{
+    volatile uint32_t *fcBase = (volatile uint32_t *)&MCI_IO_MUX->FC0;
+    uint32_t aonMask;
+
+    /* Fist clear all conflicted io_mux function. */
+    if (IO_MUX_SGPIO_FLAG(gpioFcClrMask) != 0U)
+    {
+        MCI_IO_MUX->S_GPIO &= ~pinHighMask;
+    }
+    if (IO_MUX_GPIO_FLAG(gpioFcClrMask) != 0U)
+    {
+        MCI_IO_MUX->GPIO_GRP0 &= ~pinLowMask;
+        MCI_IO_MUX->GPIO_GRP1 &= ~pinHighMask;
+    }
+
+    if (IO_MUX_FC_OFFSET(gpioFcClrMask) == 0xFU) /* Special case for SDIO */
+    {
+        assert(fselSetMask == MCI_IO_MUX_FSEL_SEL_SDIO_MASK);
+        MCI_IO_MUX->FC1 &= ~0x080UL;
+        MCI_IO_MUX->FC2 &= ~0x4FDUL;
+        MCI_IO_MUX->FC3 &= ~0x438UL;
+    }
+    else if (IO_MUX_FC_MASK(gpioFcClrMask) != 0U)
+    {
+        *(fcBase + IO_MUX_FC_OFFSET(gpioFcClrMask)) &= ~IO_MUX_FC_MASK(gpioFcClrMask);
+    }
+    else
+    {
+        /* FC register change not needed. */
+    }
+
+    if (fselClrMask != 0U)
+    {
+        MCI_IO_MUX->FSEL &= ~fselClrMask;
+    }
+    if (IO_MUX_CTIMER_IN_MASK(ctimerClrMask) != 0U)
+    {
+        MCI_IO_MUX->C_TIMER_IN &= ~IO_MUX_CTIMER_IN_MASK(ctimerClrMask);
+    }
+    if (IO_MUX_CTIMER_OUT_MASK(ctimerClrMask) != 0U)
+    {
+        MCI_IO_MUX->C_TIMER_OUT &= ~IO_MUX_CTIMER_OUT_MASK(ctimerClrMask);
+    }
+    if (sctimerClrMask != 0U)
+    {
+        MCI_IO_MUX->SC_TIMER &= ~sctimerClrMask;
+    }
+
+    /* Now set the IO_MUX for the function. */
+    if (IO_MUX_SGPIO_FLAG(gpioFcSetMask) != 0U)
+    {
+        MCI_IO_MUX->S_GPIO |= pinHighMask;
+    }
+    if (IO_MUX_GPIO_FLAG(gpioFcSetMask) != 0U)
+    {
+        MCI_IO_MUX->GPIO_GRP0 |= pinLowMask;
+        MCI_IO_MUX->GPIO_GRP1 |= pinHighMask;
+    }
+
+    if (IO_MUX_FC_MASK(gpioFcSetMask) != 0U)
+    {
+        *(fcBase + IO_MUX_FC_OFFSET(gpioFcSetMask)) |= IO_MUX_FC_MASK(gpioFcSetMask);
+    }
+
+    if (fselSetMask != 0U)
+    {
+        MCI_IO_MUX->FSEL |= fselSetMask;
+    }
+    if (IO_MUX_CTIMER_IN_MASK(ctimerSetMask) != 0U)
+    {
+        MCI_IO_MUX->C_TIMER_IN |= IO_MUX_CTIMER_IN_MASK(ctimerSetMask);
+    }
+    if (IO_MUX_CTIMER_OUT_MASK(ctimerSetMask) != 0U)
+    {
+        MCI_IO_MUX->C_TIMER_OUT |= IO_MUX_CTIMER_OUT_MASK(ctimerSetMask);
+    }
+    if (sctimerSetMask != 0U)
+    {
+        MCI_IO_MUX->SC_TIMER |= sctimerSetMask;
+    }
+
+    /* Last, enable IO function */
+    aonMask = pinLowMask & AON_SOC_CIU_MCI_IOMUX_EN0_EN_27_22_MASK;
+    SOCCTRL->MCI_IOMUX_EN0 |= (pinLowMask & ~aonMask);
+    SOCCTRL->MCI_IOMUX_EN1 |= pinHighMask;
+    AON_SOC_CIU->MCI_IOMUX_EN0 |= aonMask;
+}
+
+/*!
+ * @brief Sets the IO_MUX pin mux pull up/down configuartion.
+ *
+ * This is an example to set the GPIO2 pin to pull down:
+ * @code
+ * IO_MUX_SetPinConfig(2U, IO_MUX_PinConfigPullDown);
+ * @endcode
+ *
+ * @param pin The GPIO pin index to config.
+ * @param config The pull up/down setting for the pin.
+ */
+static inline void IO_MUX_SetPinConfig(uint32_t pin, io_mux_pin_config_t config)
+{
+    __IO uint32_t *pullReg, *driveReg;
+    uint32_t shift;
+    uint32_t pullVal, driveVal;
+
+    assert(pin < 64U);
+
+    shift    = (pin % 16U) * 2U;
+    pullVal  = (uint32_t)config & 0x3U;
+    driveVal = ((uint32_t)config >> 2) & 0x3U;
+    if (pin < 22U || pin > 27U)
+    {
+        pullReg  = &SOCCTRL->PAD_PU_PD_EN0 + pin / 16U;
+        driveReg = &SOCCTRL->SR_CONFIG0 + pin / 16U;
+    }
+    else
+    {
+        pullReg  = &AON_SOC_CIU->PAD_PU_PD_EN1;
+        driveReg = &AON_SOC_CIU->SR_CONFIG1;
+    }
+
+    *pullReg  = (*pullReg & ~(3UL << shift)) | (pullVal << shift);
+    *driveReg = (*driveReg & ~(3UL << shift)) | (driveVal << shift);
+}
+
+/*!
+ * @brief Sets IO output level in sleep mode. If level set to IO_MUX_SleepPinLevelUnchanged,
+ *        the IO configuration is same as the active mode.
+ *
+ * This is an example to set the GPIO2 pin to output high during sleep:
+ * @code
+ * IO_MUX_SetPinOutLevelInSleep(2U, IO_MUX_SleepPinLevelHigh);
+ * @endcode
+ *
+ * @param pin The GPIO pin index to config.
+ * @param level Output level in sleep.
+ */
+static inline void IO_MUX_SetPinOutLevelInSleep(uint32_t pin, io_mux_sleep_pin_level_t level)
+{
+    __IO uint32_t *regEn, *regVal;
+    uint32_t mask, shift;
+
+    assert(pin < 64U);
+
+    shift = pin % 32U;
+    mask  = 1UL << shift;
+
+    if (pin < 22U || pin > 27U)
+    {
+        if (pin < 32U)
+        {
+            regEn  = &SOCCTRL->PAD_SLP_EN0;
+            regVal = &SOCCTRL->PAD_SLP_VAL0;
+        }
+        else
+        {
+            regEn  = &SOCCTRL->PAD_SLP_EN1;
+            regVal = &SOCCTRL->PAD_SLP_VAL1;
+        }
+    }
+    else
+    {
+        regEn  = &AON_SOC_CIU->PAD_SLP_EN0;
+        regVal = &AON_SOC_CIU->PAD_SLP_VAL0;
+    }
+
+    if (level == IO_MUX_SleepPinLevelUnchanged)
+    {
+        *regEn &= ~mask;
+    }
+    else
+    {
+        *regEn |= mask;
+        *regVal = ((*regVal) & ~mask) | (((uint32_t)level) << shift);
+    }
+}
+
+/*!
+ * @brief Sets RF Switch Pin 0-3 output level in sleep mode. If level set to
+ *        IO_MUX_SleepPinLevelUnchanged, the IO configuration is same as the active mode.
+ *
+ * This is an example to set the RF_CNTL0 pin to output low during sleep:
+ * @code
+ * IO_MUX_SetRfPinOutLevelInSleep(0U, IO_MUX_SleepPinLevelLow);
+ * @endcode
+ *
+ * @param pin The RF Switch pin index to config.
+ * @param level Output level in sleep.
+ */
+static inline void IO_MUX_SetRfPinOutLevelInSleep(uint32_t pin, io_mux_sleep_pin_level_t level)
+{
+    uint32_t mask;
+
+    assert(pin < 4U);
+
+    mask = 0x10001UL << pin;
+
+    if (level == IO_MUX_SleepPinLevelUnchanged)
+    {
+        SOCCTRL->PAD_RF_SW_SLP_CONFIG &= ~mask;
+    }
+    else
+    {
+        SOCCTRL->PAD_RF_SW_SLP_CONFIG =
+            (SOCCTRL->PAD_RF_SW_SLP_CONFIG & ~mask) | (1UL << pin) | (((uint32_t)level) << (pin + 16U));
+    }
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IO_MUX_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_ocotp.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_ocotp.c
new file mode 100644
index 0000000000..aa8cfae56e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_ocotp.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2021-2023 NXP
+ *
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_ocotp.h"
+#include "fsl_reset.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.ocotp"
+#endif
+
+/* All error masks in STATUS1 register except for SEC (Single error correction)
+   When new error masks are added this macro needs to be updated */
+#define OTP_STATUS1_ERRORS_MASK                                                                                       \
+    (OCOTP_OTP_NONMASK_STATUS1_NONMASK_PBRICK_ERR_MASK | OCOTP_OTP_NONMASK_STATUS1_NONMASK_OTP_STATE_ERR_MASK |       \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_RELOAD_MASK | OCOTP_OTP_NONMASK_STATUS1_NONMASK_DED_MASK |                 \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_LUT_SEL_ERR_MASK |                                                         \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_ADDRESS_RANGE_ERR_MASK |                                                   \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_WRITE_PROTECT_ERR_MASK |                                                   \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_CRC_SECURTY_PROTECT_ERR_MASK |                                                 \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_ERR_MASK | OCOTP_OTP_NONMASK_STATUS1_NONMASK_LOAD_ERR_MASK |             \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_COUNTER_ERR_MASK | OCOTP_OTP_NONMASK_STATUS1_NONMASK_BITPROTECT_ERR_MASK |     \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_PRNG_O_FAULT_MASK | OCOTP_OTP_NONMASK_STATUS1_NONMASK_ECC_ZEROIZED_ERR_MASK |  \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_ACCESS_ERR_MASK | OCOTP_OTP_NONMASK_STATUS1_NONMASK_RELOAD_REQ_ERR_MASK | \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_WRITE_DURING_RELOAD_ERR_MASK |                                                 \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_READ_ERR_MASK |                                                     \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_HVF_WRITE_ERR_MASK |                                                    \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_READ_ERR_MASK |                                                    \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_SRAM_WRITE_ERR_MASK |                                                   \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_READ_ERR_MASK | OCOTP_OTP_NONMASK_STATUS1_NONMASK_FUSE_PROG_ERR_MASK |    \
+     OCOTP_OTP_NONMASK_STATUS1_NONMASK_SHADOW_NO_ACCESS_MASK)
+
+#define OTP_SEC_NLINES           64U             /* Max. SoC OTP lines */
+#define OTP_SVC_TAG              0x24EU          /* SVC words tag */
+#define OTP_PKG_TAG              0x15DU          /* Package words tag */
+#define SOC_OTP_READ_DELAY_COUNT (0x2AU * 1000U) /* Give 1ms to read the value */
+#define SOC_OTP_CMD_READ         0x00U
+
+/*******************************************************************************
+ * Prototypes
+ *******************************************************************************/
+/* @brief Wait until OTP controller is idle */
+static status_t otp_wait_busy(void);
+
+/* @brief Clear all error status */
+static void otp_clear_status(void);
+
+/* @brief Read nonmask_status1 register and returns precise result*/
+static status_t otp_get_nonmask_status_result(void);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static status_t otp_get_nonmask_status_result(void)
+{
+    uint32_t status_register = OCOTP->OTP_NONMASK_STATUS1;
+    status_t status;
+    int32_t i;
+
+    do
+    {
+        if ((status_register & OTP_STATUS1_ERRORS_MASK) != 0U)
+        {
+            for (i = 0; i < 32; i++)
+            {
+                if (((1UL << (uint32_t)i) & status_register) != 0U)
+                {
+                    status = MAKE_STATUS(kStatusGroup_OtpGroup, i);
+                    break;
+                }
+            }
+        }
+        status = kStatus_Success;
+    } while (false);
+
+    return status;
+}
+
+static status_t otp_wait_busy(void)
+{
+    /*
+     * Assume core clock is 300MHz, the general fuse operation should not exceed 100ms
+     * Maximum allowed ticks is 300MHz / 10
+     * The below loop needs at least 4 CPU cycles, so the timeout rounds for below loop is 300MHz / 10 / 4
+     */
+    uint32_t timeout = 300U * 1000U * 1000U / 10U / 4U;
+    status_t status;
+
+    while (((OCOTP->OTP_STATUS & OCOTP_OTP_STATUS_BUSY_MASK) != 0U) && (timeout > 0U))
+    {
+        timeout--;
+    }
+
+    if (timeout < 1U)
+    {
+        status = kStatus_OTP_Timeout;
+    }
+    else
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+static void otp_clear_status(void)
+{
+    /* Write 1s to clear all error status */
+    OCOTP->OTP_STATUS          = OCOTP_OTP_STATUS_PROGFAIL_MASK;
+    OCOTP->OTP_NONMASK_STATUS1 = OTP_STATUS1_ERRORS_MASK;
+}
+
+status_t OCOTP_OtpInit(void)
+{
+    CLOCK_EnableClock(kCLOCK_Otp);
+    RESET_ClearPeripheralReset(kOTP_RST_SHIFT_RSTn);
+
+    /* Bring SOC OTP out of reset */
+    SOC_OTP_CTRL->OTP_POR_B = SOC_OTP_CTRL_OTP_POR_B_OTP_POR_B_MASK;
+    SOC_OTP_CTRL->OTP_RST_B = SOC_OTP_CTRL_OTP_RST_B_OTP_RST_B_MASK;
+
+    return kStatus_Success;
+}
+
+status_t OCOTP_OtpDeinit(void)
+{
+    status_t status;
+
+    status = otp_wait_busy();
+    if (status == kStatus_Success)
+    {
+        OCOTP->OTP_PDN = OCOTP_OTP_PDN_PDN_MASK;
+        CLOCK_DisableClock(kCLOCK_Otp);
+    }
+
+    SOC_OTP_CTRL->OTP_POR_B = 0U;
+    SOC_OTP_CTRL->OTP_RST_B = 0U;
+
+    return status;
+}
+
+status_t OCOTP_OtpFuseRead(uint32_t addr, uint32_t *data)
+{
+    status_t status = kStatus_InvalidArgument;
+
+    do
+    {
+        if (data == NULL)
+        {
+            break;
+        }
+
+        status = otp_wait_busy();
+        if (status != kStatus_Success)
+        {
+            break;
+        }
+
+        otp_clear_status();
+
+        /* Start reading */
+        OCOTP->OTP_CTRL      = OCOTP_OTP_CTRL_ADDR(addr);
+        OCOTP->OTP_READ_CTRL = OCOTP_OTP_READ_CTRL_READ(1);
+
+        /* Wait until read completes */
+        status = otp_wait_busy();
+        if (status != kStatus_Success)
+        {
+            break;
+        }
+
+        /* Check whether errors happened or not. */
+        status = otp_get_nonmask_status_result();
+        if (status == kStatus_Success)
+        {
+            *data = OCOTP->OTP_READ_DATA;
+        }
+    } while (false);
+
+    return status;
+}
+
+status_t OCOTP_ReadUniqueID(uint8_t *uid, uint32_t *idLen)
+{
+    status_t status = kStatus_InvalidArgument;
+    uint32_t offset = 0U;
+    uint32_t leftByte;
+    uint32_t cpyByte;
+    uint32_t data;
+
+    do
+    {
+        if ((uid == NULL) || (idLen == NULL))
+        {
+            break;
+        }
+
+        (void)OCOTP_OtpInit();
+
+        if ((*idLen) != 0U)
+        {
+            leftByte = *idLen;
+            do
+            {
+                status = OCOTP_OtpFuseRead((offset / 4U) + 46U, &data);
+                if (status != kStatus_Success)
+                {
+                    break;
+                }
+                cpyByte = (leftByte > 4U) ? 4U : leftByte;
+                (void)memcpy((void *)&uid[offset], (void *)(uint8_t *)&data, cpyByte);
+                leftByte -= cpyByte;
+                offset += cpyByte;
+            } while ((leftByte > 0U) && (offset < FSL_OCOTP_UID_LENGTH));
+            *idLen -= leftByte;
+        }
+    } while (false);
+
+    return status;
+}
+
+static uint32_t soc_otp_read(uint32_t addr_line, uint64_t *value)
+{
+    uint32_t dly                   = SOC_OTP_READ_DELAY_COUNT;
+    SOC_OTP_CTRL->OTP_ADDR         = (uint16_t)addr_line;
+    SOC_OTP_CTRL->OTP_BYPASS_MODE1 = 0;
+    SOC_OTP_CTRL->OTP_CMD_START    = SOC_OTP_CMD_READ;
+    SOC_OTP_CTRL->OTP_CMD_START |= SOC_OTP_CTRL_OTP_CMD_START_OTP_CMD_START_MASK;
+    while ((dly > 0U) && ((SOC_OTP_CTRL->OTP_CTRL0 & SOC_OTP_CTRL_OTP_CTRL0_CTRL_CMD_DONE_MASK) == 0U))
+    {
+        dly--; /* If something horrible happens, bail out after a delay */
+    }
+
+    if ((dly > 0U) && ((SOC_OTP_CTRL->OTP_WDATA4 & SOC_OTP_CTRL_OTP_WDATA4_DATA_LINE_VALID_BIT_MASK) != 0U))
+    {
+        *value = ((uint64_t)SOC_OTP_CTRL->OTP_WDATA3 << 48) | ((uint64_t)SOC_OTP_CTRL->OTP_WDATA2 << 32) |
+                 ((uint64_t)SOC_OTP_CTRL->OTP_WDATA1 << 16) | ((uint64_t)SOC_OTP_CTRL->OTP_WDATA0);
+        return 1;
+    }
+
+    return 0;
+}
+
+status_t OCOTP_ReadSocOtp(uint64_t *data, uint32_t tag)
+{
+    status_t status = kStatus_Fail;
+    uint32_t i;
+
+    if (data == NULL)
+    {
+        status = kStatus_InvalidArgument;
+    }
+    else
+    {
+        /* Read SOC_OTP values */
+        for (i = 0U; i < OTP_SEC_NLINES; i++)
+        {
+            if (soc_otp_read(i, data) == 0U)
+            {
+                continue;
+            }
+
+            if ((*data & 0xFFFFU) == tag)
+            {
+                status = kStatus_Success;
+                break;
+            }
+        }
+    }
+
+    return status;
+}
+
+status_t OCOTP_ReadSVC(uint64_t *svc)
+{
+    status_t status = kStatus_Fail;
+
+    assert(svc != NULL);
+
+    status = OCOTP_ReadSocOtp(svc, OTP_SVC_TAG);
+
+    return status;
+}
+
+status_t OCOTP_ReadPackage(uint32_t *pack)
+{
+    status_t status = kStatus_Fail;
+    uint64_t data   = 0ULL;
+
+    assert(pack != NULL);
+
+    status = OCOTP_ReadSocOtp(&data, OTP_PKG_TAG);
+    if (status == kStatus_Success)
+    {
+        *pack = ((uint32_t)data >> 16U) & 0xFFU;
+    }
+
+    return status;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_ocotp.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_ocotp.h
new file mode 100644
index 0000000000..28f6236afc
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_ocotp.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2021-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_OCOTP_H_
+#define __FSL_OCOTP_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup ocotp
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief OCOTP driver version 2.2.1. */
+#define FSL_OCOTP_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
+/*@}*/
+
+/*! @brief OCOTP unique ID length. */
+#define FSL_OCOTP_UID_LENGTH 16U
+
+/*! @brief OTP Status Group */
+enum
+{
+    kStatusGroup_OtpGroup = 0x210,
+};
+
+/*! @brief OTP Error Status definitions */
+enum
+{
+    kStatus_OTP_InvalidAddress = MAKE_STATUS(kStatusGroup_OtpGroup, 1), /*!< Invalid OTP address */
+    kStatus_OTP_Timeout        = MAKE_STATUS(kStatusGroup_OtpGroup, 7), /*!< OTP operation time out */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize OTP controller
+ *
+ * This function enables OTP Controller clock.
+ *
+ * @return kStatus_Success
+ */
+status_t OCOTP_OtpInit(void);
+
+/*!
+ * @brief De-Initialize OTP controller
+ *
+ * This functin disables OTP Controller Clock.
+ * @return kStatus_Success
+ */
+status_t OCOTP_OtpDeinit(void);
+
+/*!
+ * @brief Read Fuse value from OTP Fuse Block
+ *
+ * This function read fuse data from OTP Fuse block to specified data buffer.
+ *
+ * @param addr Fuse address
+ * @param data Buffer to hold the data read from OTP Fuse block
+ * @return kStatus_Success - Data read from OTP Fuse block successfully
+ *         kStatus_OTP_Timeout - OTP read timeout
+ *         kStatus_InvalidArgument - data pointer is invalid
+ */
+status_t OCOTP_OtpFuseRead(uint32_t addr, uint32_t *data);
+
+/*!
+ * @brief Read Fuse line with specific tag value from SoC OTP
+ *
+ * This function read Fuse line with specific tag value from SoC OTP to specified data buffer.
+ *
+ * @param data Buffer to hold the data read from SoC OTP
+ * @param tag  Tag value to match
+ * @return kStatus_Success - Data read from SoC OTP successfully
+ *         kStatus_Fail    - Data read from SoC OTP failed, or cannot find the tag
+ *         kStatus_InvalidArgument - data pointer is invalid
+ */
+status_t OCOTP_ReadSocOtp(uint64_t *data, uint32_t tag);
+
+/*!
+ * @brief Read unique ID from OTP Fuse Block
+ *
+ * This function read unique ID from OTP Fuse block to specified data buffer.
+ *
+ * @param uid The buffer to store unique ID, buffer byte length is FSL_OCOTP_UID_LENGTH.
+ * @param idLen[in/out] The unique ID byte length. Set the length to read, return the length read out.
+ * @return kStatus_Success - Data read from OTP Fuse block successfully
+ *         kStatus_OTP_Timeout - OTP read timeout
+ *         kStatus_InvalidArgument - data pointer is invalid
+ */
+status_t OCOTP_ReadUniqueID(uint8_t *uid, uint32_t *idLen);
+
+/*!
+ * @brief Read Static Voltage Compansation from SOC OTP
+ *
+ * This function read SVC from OTP Fuse block to specified data buffer.
+ *
+ * @param svc The buffer to store SVC.
+ * @return kStatus_Success - Data read from SOC OTP successfully
+ *         kStatus_Fail    - SOC OTP read failure
+ */
+status_t OCOTP_ReadSVC(uint64_t *svc);
+
+/*!
+ * @brief Read package type from SOC OTP
+ *
+ * @param pack The buffer to store package type.
+ * @return kStatus_Success - Data read from SOC OTP successfully
+ *         kStatus_Fail    - SOC OTP read failure
+ */
+status_t OCOTP_ReadPackage(uint32_t *pack);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_OCOTP_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_power.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_power.c
new file mode 100644
index 0000000000..49d06e239d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_power.c
@@ -0,0 +1,1463 @@
+/*
+ * Copyright 2020-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_power.h"
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power"
+#endif
+
+#define IS_XIP_FLEXSPI()                                                                                \
+    ((((uint32_t)POWER_EnableWakeup >= 0x08000000U) && ((uint32_t)POWER_EnableWakeup < 0x10000000U)) || \
+     (((uint32_t)POWER_EnableWakeup >= 0x18000000U) && ((uint32_t)POWER_EnableWakeup < 0x20000000U)))
+
+#define FLEXSPI_DLL_LOCK_RETRY (10U)
+
+/* Wait some PMU cycles */
+#define POWER_WAIT_PMU()              \
+    do                                \
+    {                                 \
+        volatile uint32_t dummy;      \
+        dummy = PMU->PWR_MODE_STATUS; \
+        dummy = PMU->PWR_MODE_STATUS; \
+        dummy = PMU->PWR_MODE_STATUS; \
+        dummy = PMU->PWR_MODE_STATUS; \
+        dummy = PMU->PWR_MODE_STATUS; \
+        (void)dummy;                  \
+    } while (false)
+
+#define POWER_WLAN_POWER_STATUS() (SOCCTRL->WLAN_POWER_STATUS & 0x3U)
+#define POWER_BLE_POWER_STATUS()  (SOCCTRL->BLE_POWER_STATUS & 0x3U)
+#define POWER_WLAN_BLE_POWER_ON   (0U)
+#define POWER_WLAN_BLE_POWER_SLP  (2U)
+#define POWER_WLAN_BLE_POWER_OFF  (3U)
+
+#define ITRC_OUT_SEL_MASK          (0x0C000FF0U)
+#define ITRC_OUT_SEL_DISABLE       (0x08000AA0U)
+#define ITRC_OUT_SEL_EVENT_MASK    (0xFU)
+#define ITRC_OUT_SEL_EVENT_DISABLE (0xAU)
+
+#define POWER_WRITE_MEM32(addr, val)            \
+    do                                          \
+    {                                           \
+        *((volatile uint32_t *)(addr)) = (val); \
+    } while (false)
+
+typedef struct _power_nvic_context
+{
+    uint32_t PriorityGroup;
+    uint32_t ISER[5];
+    uint8_t IPR[160];
+    uint8_t SHPR[12];
+    uint32_t ICSR;
+    uint32_t VTOR;
+    uint32_t AIRCR;
+    uint32_t SCR;
+    uint32_t CCR;
+    uint32_t SHCSR;
+    uint32_t MMFAR;
+    uint32_t BFAR;
+    uint32_t CPACR;
+    uint32_t NSACR;
+} power_nvic_context_t;
+
+typedef struct _power_systick_context
+{
+    uint32_t CTRL;
+    uint32_t LOAD;
+} power_systick_context_t;
+
+typedef struct _power_clock_context
+{
+    uint32_t SOURCE_CLK_GATE;
+} power_clock_context_t;
+
+typedef struct _power_gdet_sensor_context
+{
+    int32_t disableCount;
+    uint32_t VSEN_CTRL_1_REG_1;
+    uint32_t VSEN_CTRL_2_REG_1;
+    uint32_t VSEN_CTRL_3_REG_1;
+    uint32_t ITRC_OUT0_SEL0;
+    uint32_t ITRC_OUT1_SEL0;
+    uint32_t ITRC_OUT0_SEL0_EVENT16_31;
+    uint32_t ITRC_OUT1_SEL0_EVENT16_31;
+    uint32_t ELS_INT_ENABLE;
+    uint32_t ELS_EN;
+} power_gdet_sensor_context_t;
+
+typedef struct _power_threshold_params
+{
+    uint32_t param1;
+    uint32_t param2;
+    uint32_t margin;
+} power_threshold_params_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static power_nvic_context_t s_nvicContext;
+static power_systick_context_t s_systickContext;
+static power_clock_context_t s_clockContext;
+static power_gdet_sensor_context_t s_gdetSensorContext;
+static capt_pulse_timer_callback_t s_captPulseCb;
+static void *s_captPulseCbParam;
+static power_switch_callback_t s_preSwitch;
+static void *s_preSwitchParam;
+static power_switch_callback_t s_postSwitch;
+static void *s_postSwitchParam;
+static const uint8_t s_droTable[19] = {0x40U, 0x43U, 0x46U, 0x48U, 0x4CU, 0x4FU, 0x52U, 0x54U, 0x57U, 0x5AU,
+                                       0x5DU, 0x5FU, 0x62U, 0x65U, 0x67U, 0x69U, 0x69U, 0x69U, 0x69U};
+static power_load_gdet_cfg s_gdetCfgloadFunc;
+static power_gdet_data_t s_gdetCfgData;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+AT_QUICKACCESS_SECTION_CODE(static void POWER_Delay(uint32_t loop))
+{
+    if (loop > 0U)
+    {
+        __ASM volatile(
+            "1:                             \n"
+            "    SUBS   %0, %0, #1          \n"
+            "    CMP    %0, #0              \n"
+            "    BNE    1b                  \n"
+            :
+            : "r"(loop));
+    }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void POWER_DelayUs(uint32_t us))
+{
+    uint32_t instNum;
+
+    instNum = ((SystemCoreClock + 999999UL) / 1000000UL) * us;
+    POWER_Delay((instNum + 2U) / 3U);
+}
+
+static void POWER_GetThresholdParams(uint32_t pack,
+                                     power_threshold_params_t *v11,
+                                     power_threshold_params_t *v18,
+                                     power_threshold_params_t *v33)
+{
+    assert(v11);
+    assert(v18);
+    assert(v33);
+
+    v11->param1 = 38307U;
+    v11->param2 = 514850000U;
+    v11->margin = 750;
+    switch (pack)
+    {
+        case 0: /* QFN */
+            v18->param1 = 22034U;
+            v18->param2 = 507580000U;
+            v18->margin = 500U + 380U;
+            v33->param1 = 12924U;
+            v33->param2 = 503960000U;
+            v33->margin = 1000U + 200U;
+            break;
+        case 1: /* CSP */
+            v18->param1 = 21903U;
+            v18->param2 = 514170000U;
+            v18->margin = 500U + 305U;
+            v33->param1 = 12924U;
+            v33->param2 = 503960000U;
+            v33->margin = 1000U + 200U;
+            break;
+        case 2: /* BGA */
+            v18->param1 = 22156U;
+            v18->param2 = 512500000U;
+            v18->margin = 500U + 305U;
+            v33->param1 = 12917U;
+            v33->param2 = 513300000U;
+            v33->margin = 1000U + 200U;
+            break;
+        default:
+            assert(false);
+            break;
+    }
+}
+
+static void POWER_SaveNvicState(void)
+{
+    uint32_t i;
+    uint32_t irqRegs;
+    uint32_t irqNum;
+
+    irqRegs = (SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) + 1U;
+    irqNum  = irqRegs * 32U;
+
+    assert(irqRegs <= ARRAY_SIZE(s_nvicContext.ISER));
+    assert(irqNum <= ARRAY_SIZE(s_nvicContext.IPR));
+
+    s_nvicContext.PriorityGroup = NVIC_GetPriorityGrouping();
+
+    for (i = 0U; i < irqRegs; i++)
+    {
+        s_nvicContext.ISER[i] = NVIC->ISER[i];
+    }
+
+    for (i = 0U; i < irqNum; i++)
+    {
+        s_nvicContext.IPR[i] = NVIC->IPR[i];
+    }
+
+    /* Save SCB configuration */
+    s_nvicContext.ICSR  = SCB->ICSR;
+    s_nvicContext.VTOR  = SCB->VTOR;
+    s_nvicContext.AIRCR = SCB->AIRCR;
+    s_nvicContext.SCR   = SCB->SCR;
+    s_nvicContext.CCR   = SCB->CCR;
+
+    s_nvicContext.SHCSR = SCB->SHCSR;
+    s_nvicContext.MMFAR = SCB->MMFAR;
+    s_nvicContext.BFAR  = SCB->BFAR;
+    s_nvicContext.CPACR = SCB->CPACR;
+    s_nvicContext.NSACR = SCB->NSACR;
+
+    for (i = 0U; i < ARRAY_SIZE(s_nvicContext.SHPR); i++)
+    {
+        s_nvicContext.SHPR[i] = SCB->SHPR[i];
+    }
+}
+
+static void POWER_RestoreNvicState(void)
+{
+    uint32_t i;
+    uint32_t irqRegs;
+    uint32_t irqNum;
+
+    irqRegs = (SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) + 1U;
+    irqNum  = irqRegs * 32U;
+
+    NVIC_SetPriorityGrouping(s_nvicContext.PriorityGroup);
+
+    for (i = 0U; i < irqRegs; i++)
+    {
+        NVIC->ISER[i] = s_nvicContext.ISER[i];
+    }
+
+    for (i = 0U; i < irqNum; i++)
+    {
+        NVIC->IPR[i] = s_nvicContext.IPR[i];
+    }
+
+    /* Restore SCB configuration */
+    SCB->ICSR  = s_nvicContext.ICSR;
+    SCB->VTOR  = s_nvicContext.VTOR;
+    SCB->AIRCR = s_nvicContext.AIRCR;
+    SCB->SCR   = s_nvicContext.SCR;
+    SCB->CCR   = s_nvicContext.CCR;
+
+    SCB->SHCSR = s_nvicContext.SHCSR;
+    SCB->MMFAR = s_nvicContext.MMFAR;
+    SCB->BFAR  = s_nvicContext.BFAR;
+    SCB->CPACR = s_nvicContext.CPACR;
+    SCB->NSACR = s_nvicContext.NSACR;
+
+    for (i = 0U; i < ARRAY_SIZE(s_nvicContext.SHPR); i++)
+    {
+        SCB->SHPR[i] = s_nvicContext.SHPR[i];
+    }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void POWER_SaveGdetVSensorConfig(void))
+{
+    s_gdetSensorContext.VSEN_CTRL_1_REG_1 =
+        SENSOR_CTRL->VSEN_CTRL_1_REG_1 & SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK;
+    s_gdetSensorContext.VSEN_CTRL_2_REG_1 =
+        SENSOR_CTRL->VSEN_CTRL_2_REG_1 & SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_MASK;
+    s_gdetSensorContext.VSEN_CTRL_3_REG_1 =
+        SENSOR_CTRL->VSEN_CTRL_3_REG_1 & SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_MASK;
+    s_gdetSensorContext.ITRC_OUT0_SEL0            = ITRC->OUT0_SEL0;
+    s_gdetSensorContext.ITRC_OUT1_SEL0            = ITRC->OUT1_SEL0;
+    s_gdetSensorContext.ITRC_OUT0_SEL0_EVENT16_31 = ITRC->OUT0_SEL0_EVENT16_31;
+    s_gdetSensorContext.ITRC_OUT1_SEL0_EVENT16_31 = ITRC->OUT1_SEL0_EVENT16_31;
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void POWER_RestoreGdetVSensorConfig(void))
+{
+    SENSOR_CTRL->VSEN_CTRL_1_REG_1 =
+        (SENSOR_CTRL->VSEN_CTRL_1_REG_1 & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK) |
+        s_gdetSensorContext.VSEN_CTRL_1_REG_1;
+    SENSOR_CTRL->VSEN_CTRL_2_REG_1 =
+        (SENSOR_CTRL->VSEN_CTRL_2_REG_1 & ~SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_MASK) |
+        s_gdetSensorContext.VSEN_CTRL_2_REG_1;
+    SENSOR_CTRL->VSEN_CTRL_3_REG_1 =
+        (SENSOR_CTRL->VSEN_CTRL_3_REG_1 & ~SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_MASK) |
+        s_gdetSensorContext.VSEN_CTRL_3_REG_1;
+    ITRC->OUT0_SEL0            = s_gdetSensorContext.ITRC_OUT0_SEL0;
+    ITRC->OUT1_SEL0            = s_gdetSensorContext.ITRC_OUT1_SEL0;
+    ITRC->OUT0_SEL0_EVENT16_31 = s_gdetSensorContext.ITRC_OUT0_SEL0_EVENT16_31;
+    ITRC->OUT1_SEL0_EVENT16_31 = s_gdetSensorContext.ITRC_OUT1_SEL0_EVENT16_31;
+}
+
+void CAPT_PULSE_DriverIRQHandler(void);
+void CAPT_PULSE_DriverIRQHandler(void)
+{
+    /* Clear IRQ status */
+    PMU->CAPT_PULSE |= PMU_CAPT_PULSE_IRQ_CLR_MASK;
+    /* Call user callback */
+    if (s_captPulseCb != NULL)
+    {
+        s_captPulseCb(s_captPulseCbParam);
+    }
+}
+
+/**
+ * @brief   Check if IRQ is the wakeup source
+ * @param   irq   : IRQ number
+ * @return  true if IRQ is the wakeup source, false otherwise.
+ */
+bool POWER_GetWakeupStatus(IRQn_Type irq)
+{
+    uint32_t status;
+    uint32_t irqNum = (uint32_t)irq;
+
+    assert((int32_t)irq >= 0);
+
+    if (irq <= HWVAD0_IRQn)
+    {
+        status = PMU->WAKEUP_PM2_STATUS0 & (1UL << irqNum);
+    }
+    else if (irq <= POWERQUAD_IRQn)
+    {
+        status = PMU->WAKEUP_PM2_STATUS1 & (1UL << (irqNum - 32U));
+    }
+    else if ((irq <= ITRC_IRQn) && (irq >= GAU_GPDAC_INT_FUNC11_IRQn))
+    {
+        status = PMU->WAKEUP_PM2_STATUS3 & (1UL << (irqNum - 96U));
+    }
+    else
+    {
+        status = 0U;
+    }
+
+    switch (irq)
+    {
+        case PIN0_INT_IRQn:
+            status = PMU->WAKEUP_STATUS & PMU_WAKEUP_STATUS_PIN0_MASK;
+            break;
+        case PIN1_INT_IRQn:
+            status = PMU->WAKEUP_STATUS & PMU_WAKEUP_STATUS_PIN1_MASK;
+            break;
+        case RTC_IRQn:
+            /* PM2 wakeup status is at WAKEUP_PM2_STATUS1, PM3/PM4 wakeup status is at WAKEUP_STATUS */
+            status |= PMU->WAKEUP_STATUS & PMU_WAKEUP_STATUS_RTC_MASK;
+            break;
+        case CAPT_PULSE_IRQn:
+            status = PMU->WAKEUP_STATUS & PMU_WAKEUP_STATUS_CAPT_MASK;
+            break;
+        case WL_MCI_WAKEUP0_IRQn:
+            status = PMU->WAKEUP_STATUS & (1UL << PMU_WAKEUP_STATUS_WL_SHIFT);
+            break;
+        case WL_MCI_WAKEUP1_IRQn:
+            status = PMU->WAKEUP_STATUS & (2UL << PMU_WAKEUP_STATUS_WL_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP0_IRQn:
+            status = PMU->WAKEUP_STATUS & (1UL << PMU_WAKEUP_STATUS_BLE_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP1_IRQn:
+            status = PMU->WAKEUP_STATUS & (2UL << PMU_WAKEUP_STATUS_BLE_SHIFT);
+            break;
+        default:
+            /* Do nothing */
+            break;
+    }
+
+    return (status != 0U);
+}
+
+/**
+ * @brief   Clear wakeup status
+ * @param   irq   : IRQ number
+ */
+void POWER_ClearWakeupStatus(IRQn_Type irq)
+{
+    uint32_t irqNum = (uint32_t)irq;
+
+    assert((int32_t)irq >= 0);
+
+    if (irq <= HWVAD0_IRQn)
+    {
+        PMU->WAKEUP_PM2_SRC_CLR0 = (1UL << irqNum);
+    }
+    else if (irq <= POWERQUAD_IRQn)
+    {
+        PMU->WAKEUP_PM2_SRC_CLR1 = (1UL << (irqNum - 32U));
+    }
+    else if ((irq <= ITRC_IRQn) && (irq >= GAU_GPDAC_INT_FUNC11_IRQn))
+    {
+        PMU->WAKEUP_PM2_SRC_CLR3 = (1UL << (irqNum - 96U));
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    switch (irq)
+    {
+        case PIN0_INT_IRQn:
+            PMU->WAKE_SRC_CLR = PMU_WAKE_SRC_CLR_PIN0_CLR_MASK;
+            break;
+        case PIN1_INT_IRQn:
+            PMU->WAKE_SRC_CLR = PMU_WAKE_SRC_CLR_PIN1_CLR_MASK;
+            break;
+        case RTC_IRQn:
+            PMU->WAKE_SRC_CLR = PMU_WAKE_SRC_CLR_RTC_CLR_MASK;
+            break;
+        case CAPT_PULSE_IRQn:
+            PMU->WAKE_SRC_CLR = PMU_WAKE_SRC_CLR_CAPT_CLR_MASK;
+            break;
+        case WL_MCI_WAKEUP0_IRQn:
+            PMU->WAKE_SRC_CLR = (1UL << PMU_WAKE_SRC_CLR_WL_CLR_SHIFT);
+            break;
+        case WL_MCI_WAKEUP1_IRQn:
+            PMU->WAKE_SRC_CLR = (2UL << PMU_WAKE_SRC_CLR_WL_CLR_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP0_IRQn:
+            PMU->WAKE_SRC_CLR = (1UL << PMU_WAKE_SRC_CLR_BLE_CLR_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP1_IRQn:
+            PMU->WAKE_SRC_CLR = (2UL << PMU_WAKE_SRC_CLR_BLE_CLR_SHIFT);
+            break;
+        default:
+            /* Do nothing */
+            break;
+    }
+}
+
+/**
+ * @brief   Enable the Wakeup interrupt.
+ * @param   irq   : IRQ number
+ */
+void POWER_EnableWakeup(IRQn_Type irq)
+{
+    uint32_t irqNum = (uint32_t)irq;
+
+    assert((int32_t)irq >= 0);
+
+    if (irq <= HWVAD0_IRQn)
+    {
+        PMU->WAKEUP_PM2_MASK0 |= (1UL << irqNum);
+    }
+    else if (irq <= POWERQUAD_IRQn)
+    {
+        PMU->WAKEUP_PM2_MASK1 |= (1UL << (irqNum - 32U));
+    }
+    else if ((irq <= ITRC_IRQn) && (irq >= GAU_GPDAC_INT_FUNC11_IRQn))
+    {
+        PMU->WAKEUP_PM2_MASK3 |= (1UL << (irqNum - 96U));
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    switch (irq)
+    {
+        case PIN0_INT_IRQn:
+            PMU->WAKEUP_MASK |= PMU_WAKEUP_MASK_PIN0_MASK_MASK;
+            break;
+        case PIN1_INT_IRQn:
+            PMU->WAKEUP_MASK |= PMU_WAKEUP_MASK_PIN1_MASK_MASK;
+            break;
+        case RTC_IRQn:
+            PMU->WAKEUP_MASK |= PMU_WAKEUP_MASK_RTC_MASK_MASK;
+            break;
+        case CAPT_PULSE_IRQn:
+            PMU->WAKEUP_MASK |= PMU_WAKEUP_MASK_CAPT_MASK_MASK;
+            break;
+        case WL_MCI_WAKEUP0_IRQn:
+            PMU->WAKEUP_MASK |= (1UL << PMU_WAKEUP_MASK_WL_MASK_SHIFT);
+            break;
+        case WL_MCI_WAKEUP1_IRQn:
+            PMU->WAKEUP_MASK |= (2UL << PMU_WAKEUP_MASK_WL_MASK_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP0_IRQn:
+            PMU->WAKEUP_MASK |= (1UL << PMU_WAKEUP_MASK_BLE_MASK_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP1_IRQn:
+            PMU->WAKEUP_MASK |= (2UL << PMU_WAKEUP_MASK_BLE_MASK_SHIFT);
+            break;
+        default:
+            /* Do nothing */
+            break;
+    }
+}
+
+/**
+ * @brief   Disable the Wakeup interrupts.
+ * @param   irq   : IRQ number
+ */
+void POWER_DisableWakeup(IRQn_Type irq)
+{
+    uint32_t irqNum = (uint32_t)irq;
+
+    assert((int32_t)irq >= 0);
+
+    if (irq <= HWVAD0_IRQn)
+    {
+        PMU->WAKEUP_PM2_MASK0 &= ~(1UL << irqNum);
+    }
+    else if (irq <= POWERQUAD_IRQn)
+    {
+        PMU->WAKEUP_PM2_MASK1 &= ~(1UL << (irqNum - 32U));
+    }
+    else if ((irq <= ITRC_IRQn) && (irq >= GAU_GPDAC_INT_FUNC11_IRQn))
+    {
+        PMU->WAKEUP_PM2_MASK3 &= ~(1UL << (irqNum - 96U));
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    switch (irq)
+    {
+        case PIN0_INT_IRQn:
+            PMU->WAKEUP_MASK &= ~PMU_WAKEUP_MASK_PIN0_MASK_MASK;
+            break;
+        case PIN1_INT_IRQn:
+            PMU->WAKEUP_MASK &= ~PMU_WAKEUP_MASK_PIN1_MASK_MASK;
+            break;
+        case RTC_IRQn:
+            PMU->WAKEUP_MASK &= ~PMU_WAKEUP_MASK_RTC_MASK_MASK;
+            break;
+        case CAPT_PULSE_IRQn:
+            PMU->WAKEUP_MASK &= ~PMU_WAKEUP_MASK_CAPT_MASK_MASK;
+            break;
+        case WL_MCI_WAKEUP0_IRQn:
+            PMU->WAKEUP_MASK &= ~(1UL << PMU_WAKEUP_MASK_WL_MASK_SHIFT);
+            break;
+        case WL_MCI_WAKEUP1_IRQn:
+            PMU->WAKEUP_MASK &= ~(2UL << PMU_WAKEUP_MASK_WL_MASK_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP0_IRQn:
+            PMU->WAKEUP_MASK &= ~(1UL << PMU_WAKEUP_MASK_BLE_MASK_SHIFT);
+            break;
+        case BLE_MCI_WAKEUP1_IRQn:
+            PMU->WAKEUP_MASK &= ~(2UL << PMU_WAKEUP_MASK_BLE_MASK_SHIFT);
+            break;
+        default:
+            /* Do nothing */
+            break;
+    }
+}
+
+/**
+ * @brief   Set sleep mode on idle.
+ * @param   mode : 0 ~ 4 stands for PM0 ~ PM4.
+ */
+void POWER_SetSleepMode(uint32_t mode)
+{
+    assert(mode <= 4U);
+
+    if (mode == 0U)
+    {
+        mode = 1U; /* PM0/PM1 is same */
+    }
+    /* set PMU basic mode */
+    PMU->PWR_MODE = PMU_PWR_MODE_PWR_MODE(mode - 1U);
+
+    /* select deepsleep or not */
+    if (mode == 1U)
+    {
+        SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    }
+    else
+    {
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+    }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void Power_ConfigClkGate(const power_sleep_config_t *config))
+{
+    uint32_t pm2AnaPdCfg = (config->pm2AnaPuCfg ^ (uint32_t)kPOWER_Pm2AnaPuAll) & (uint32_t)kPOWER_Pm2AnaPuAll;
+    uint32_t clkGate     = config->clkGate & (uint32_t)kPOWER_ClkGateAll;
+
+    /* If ENET clock is enabled, TDDR power must be on. */
+    if ((clkGate & SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_MASK) == 0U)
+    {
+        pm2AnaPdCfg &= ~SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_MASK;
+    }
+
+    SYSCTL2->SOURCE_CLK_GATE = (SYSCTL2->SOURCE_CLK_GATE & (~((uint32_t)kPOWER_ClkGateAll))) | clkGate;
+    SYSCTL2->ANA_PDWN_PM2    = pm2AnaPdCfg;
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void deinitXip(void))
+{
+    if (IS_XIP_FLEXSPI())
+    { /* FlexSPI */
+        /* Wait until FLEXSPI is not busy */
+        while (!(((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) &&
+                 ((FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U)))
+        {
+        }
+        /* Disable module. */
+        FLEXSPI->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+        /* Disable clock. */
+        CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK;
+    }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void initFlexSPI(FLEXSPI_Type *base))
+{
+    uint32_t status;
+    uint32_t lastStatus;
+    uint32_t retry;
+    uint32_t mask = 0;
+
+    /* Enable FLEXSPI module */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+    while ((base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) != 0U)
+    {
+    }
+
+    /* Need to wait DLL locked if DLL enabled */
+    if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
+    {
+        lastStatus = base->STS2;
+        retry      = FLEXSPI_DLL_LOCK_RETRY;
+        /* Flash on port A */
+        if (((base->FLSHCR0[0] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0U) ||
+            ((base->FLSHCR0[1] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0U))
+        {
+            mask |= FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK;
+        }
+        /* Flash on port B */
+        if (((base->FLSHCR0[2] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0U) ||
+            ((base->FLSHCR0[3] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0U))
+        {
+            mask |= FLEXSPI_STS2_BREFLOCK_MASK | FLEXSPI_STS2_BSLVLOCK_MASK;
+        }
+        /* Wait slave delay line locked and slave reference delay line locked. */
+        do
+        {
+            status = base->STS2;
+            if ((status & mask) == mask)
+            {
+                /* Locked */
+                retry = 100;
+                break;
+            }
+            else if (status == lastStatus)
+            {
+                /* Same delay cell number in calibration */
+                retry--;
+            }
+            else
+            {
+                retry      = FLEXSPI_DLL_LOCK_RETRY;
+                lastStatus = status;
+            }
+        } while (retry > 0U);
+        /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+        for (; retry > 0U; retry--)
+        {
+            __NOP();
+        }
+    }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void initXip(void))
+{
+    if (IS_XIP_FLEXSPI())
+    { /* FlexSPI */
+        /* Enable FLEXSPI clock again */
+        CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK;
+        /* Re-enable FLEXSPI module */
+        initFlexSPI(FLEXSPI);
+    }
+}
+
+void POWER_ConfigCauInSleep(bool pdCau)
+{
+    if (pdCau) /* xtal / cau full pd */
+    {
+        CAU->PD_CTRL_ONE_REG |= 0x4U;
+        CAU->SLP_CTRL_ONE_REG = 0xCU;
+    }
+    else
+    {
+        CAU->PD_CTRL_ONE_REG &= 0xFBU;
+        CAU->SLP_CTRL_ONE_REG = 0x9EU;
+        CAU->SLP_CTRL_TWO_REG = 0x6AU;
+    }
+}
+
+/* Prepare to go to low power
+ *  Change clock source to RC32M
+ *   Switch off PLLs, XTAL
+ *  Set Deep sleep bit in SRC register
+ *  Initiate state change
+ */
+AT_QUICKACCESS_SECTION_CODE(static void POWER_PrePowerMode(uint32_t mode, const power_sleep_config_t *config))
+{
+    uint32_t wlanPowerStatus, blePowerStatus;
+
+    assert((mode >= 1U) && (mode <= 4U));
+    /* Turn off Systick to avoid interrupt
+     *  when entering low power state
+     */
+    s_systickContext.CTRL = SysTick->CTRL;
+    s_systickContext.LOAD = SysTick->LOAD;
+    SysTick->CTRL         = 0;
+    SysTick->LOAD         = 0;
+
+    POWER_SetSleepMode(mode);
+
+    if ((mode == 2U) || (mode == 3U) || (mode == 4U))
+    {
+        /* To enter PM2/PM3/PM4, GDET sensor must be disabled */
+        assert(s_gdetSensorContext.disableCount > 0);
+    }
+
+    s_clockContext.SOURCE_CLK_GATE = SYSCTL2->SOURCE_CLK_GATE;
+
+    if (mode == 2U)
+    {
+        /* Deinit FlexSPI in case XIP */
+        deinitXip();
+        /* Keep all modules power on in SW controlled CFG */
+        SYSCTL2->MEM_PD_CFG = 0U;
+        /* Enable SW control for modules need be powered on, the others are powered down by HW */
+        SYSCTL2->MEM_PD_CTRL = config->pm2MemPuCfg & (uint32_t)kPOWER_Pm2MemPuAll;
+        Power_ConfigClkGate(config);
+    }
+    else if (mode >= 3U)
+    {
+        /* Turn off the short switch between C18/C11 and V18/V11.
+           In sleep mode, V11 drops to 0.8V */
+        BUCK18->BUCK_CTRL_TWENTY_REG = 0x75U;
+        if (mode == 3U)
+        {
+            POWER_SaveNvicState();
+
+            PMU->MEM_CFG = (PMU->MEM_CFG & ~PMU_MEM_CFG_MEM_RET_MASK) | (config->memPdCfg & PMU_MEM_CFG_MEM_RET_MASK);
+            PMU->PMIP_BUCK_CTRL = (PMU->PMIP_BUCK_CTRL & ~((uint32_t)kPOWER_Pm3BuckAll)) |
+                                  (config->pm3BuckCfg & (uint32_t)kPOWER_Pm3BuckAll);
+            /* Clear reset status */
+            PMU->SYS_RST_CLR = 0x7FU;
+        }
+        else if (mode == 4U)
+        {
+            wlanPowerStatus = POWER_WLAN_POWER_STATUS();
+            blePowerStatus  = POWER_BLE_POWER_STATUS();
+
+            PMU->MEM_CFG =
+                (PMU->MEM_CFG & ~PMU_MEM_CFG_AON_MEM_RET_MASK) | (config->memPdCfg & PMU_MEM_CFG_AON_MEM_RET_MASK);
+            if ((wlanPowerStatus == POWER_WLAN_BLE_POWER_OFF) && (blePowerStatus == POWER_WLAN_BLE_POWER_OFF))
+            {
+                /* pm422, LDO 0.8V, 1.8V */
+                PMU->PMIP_LDO_LVL = PMU_PMIP_LDO_LVL_LDO18_SEL(4) | PMU_PMIP_LDO_LVL_LDO11_SEL(1);
+            }
+            /* Clear reset status */
+            PMU->SYS_RST_CLR = 0x7FU;
+        }
+        else
+        {
+            assert(false);
+        }
+    }
+    else
+    {
+        /* PM1: Do nothing */
+    }
+
+    if (s_preSwitch != NULL)
+    {
+        s_preSwitch(mode, s_preSwitchParam);
+    }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static bool POWER_PostPowerMode(uint32_t mode))
+{
+    assert((mode >= 1U) && (mode <= 4U));
+
+    if (s_postSwitch != NULL)
+    {
+        s_postSwitch(mode, s_postSwitchParam);
+    }
+
+    POWER_SetSleepMode(1U);
+
+    SYSCTL2->SOURCE_CLK_GATE = s_clockContext.SOURCE_CLK_GATE;
+
+    if (mode == 2U)
+    {
+        initXip();
+    }
+    else if (mode == 3U)
+    {
+        SystemInit();
+        POWER_RestoreNvicState();
+        initXip();
+    }
+    else
+    {
+        /* PM1: Do nothing */
+    }
+
+    if ((mode == 3U) && (PMU->PWR_MODE_STATUS == 2U))
+    {
+        /* Successfully resumed from PM3, GDET is enabled by ROM. */
+        assert(s_gdetSensorContext.disableCount > 0);
+        s_gdetSensorContext.disableCount--;
+    }
+
+    SysTick->CTRL = s_systickContext.CTRL;
+    SysTick->LOAD = s_systickContext.LOAD;
+
+    return (mode == 1U) || (PMU->PWR_MODE_STATUS == (mode - 1U)); /* PM1 doesn't update PWR_MODE_STATUS */
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void POWER_EnterPm3Asm(void))
+{
+    uint32_t clk    = CLKCTL0->PSCCTL0;
+    uint32_t rst    = RSTCTL0->PRSTCTL0;
+    uint32_t rtcClk = CLKCTL1->PSCCTL2 & CLKCTL1_PSCCTL2_RTC_LITE_MASK;
+
+    /* Enable AON MEM clock/reset. */
+    CLKCTL0->PSCCTL0_SET  = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK;
+    RSTCTL0->PRSTCTL0_CLR = RSTCTL0_PRSTCTL0_CLR_AON_MEM_MASK;
+
+    /* Address: 0x4015C000 is the address in NVRAM which holds address
+     * where control returns after exit from PM3.
+     * All general purpose registers and special registers
+     * are saved by pushing them on current thread's stack
+     * and finally SP is saved in NVRAM address 0x4015C004. */
+    __ASM volatile(
+        "push {r0-r12, lr}\n"
+        "mrs r1, basepri\n"
+        "push {r1}\n"
+        "mrs r1, primask\n"
+        "push {r1}\n"
+        "mrs r1, faultmask\n"
+        "push {r1}\n"
+        "mrs r1, control\n"
+        "bic r2, r1, #2\n"
+        "msr control, r2\n" /* Use MSP */
+        "push {r1}\n"       /* CONTROL */
+        "mrs r1, psp\n"
+        "push {r1}\n" /* PSP */
+        "mrs r1, psplim\n"
+        "push {r1}\n" /* PSPLIM */
+        "mrs r1, msplim\n"
+        "push {r1}\n" /* MSPLIM */
+        "ldr r0, =0x4015C004\n"
+        "str sp, [r0]\n" /* MSP */
+        "ldr r0, =0x4015C000\n"
+        "mov r1, pc\n"
+        "add r1, r1 , #21\n"
+        "str r1, [r0]\n");
+    /*
+     * Execute WFI to generate a state change
+     * and system is in an unresponsive state
+     * press wakeup key to get it out of standby
+     * If time_to_standby is set to valid value
+     * RTC is programmed and RTC generates
+     * a wakeup signal.
+     */
+    __DSB();
+    __WFI();
+    __ISB();
+
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* When system exits PM3 all registers need to be
+     * restored as they are lost. */
+
+    /*
+     * When MCU enters PM3 all Core registers
+     * r0-r12
+     * lr
+     * basepri
+     * primask
+     * faultmask
+     * control
+     * psp
+     * psplim
+     * msplim
+     * are lost (ZERO) as MCU power is tuned off
+     * On wakeup from PM3, this piece of code restores
+     * these registers which were saved before entry.
+     * The location of saving this register was on stack
+     */
+    __ASM volatile(
+        "ldr r0, =0x4015C004\n"
+        "ldr sp, [r0]\n"
+        "pop {r4}\n"   /* MSPLIM */
+        "pop {r5}\n"   /* PSPLIM */
+        "pop {r1}\n"   /* PSP */
+        "pop {r2}\n"   /* CONTROL */
+        "mov r3, sp\n" /* MSP */
+        "msr msplim, r4\n"
+        "msr psplim, r5\n"
+        "msr msp, r3\n"
+        "msr psp, r1\n"
+        "msr control, r2\n"
+        "pop {r1}\n"
+        "msr faultmask, r1\n"
+        "pop {r1}\n"
+        "msr primask, r1\n"
+        "pop {r1}\n"
+        "msr basepri, r1\n"
+        "pop {r0-r12, lr}\n");
+    /* Restore AON MEM clock/reset */
+    CLKCTL0->PSCCTL0     = clk;
+    RSTCTL0->PRSTCTL0    = rst;
+    CLKCTL1->PSCCTL2_SET = rtcClk;
+}
+
+static void POWER_InitVSensorThreshold(uint8_t volt11, uint32_t pack)
+{
+    uint32_t val;
+    uint32_t svcMv;
+    power_threshold_params_t v11 = {0};
+    power_threshold_params_t v18 = {0};
+    power_threshold_params_t v33 = {0};
+
+    POWER_GetThresholdParams(pack, &v11, &v18, &v33);
+
+    /* Disable V11 sensor */
+    val                            = SENSOR_CTRL->VSEN_CTRL_1_REG_1;
+    SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK;
+    /* Configure threshold */
+    svcMv = (uint32_t)(volt11)*5U + 630U;
+    val   = val & ~(SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR_MASK |
+                  SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR_MASK);
+    val |= SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR(
+        (v11.param1 * (svcMv * 10U + v11.margin) + v11.param2 + 999999U) / 1000000U);
+    val |= SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR((v11.param1 * (svcMv * 10U - v11.margin) + v11.param2) /
+                                                              1000000U);
+    SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK;
+    /* Restore V11 sensor */
+    SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val;
+
+    /* Disable V18 sensor */
+    val                            = SENSOR_CTRL->VSEN_CTRL_2_REG_1;
+    SENSOR_CTRL->VSEN_CTRL_2_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_MASK;
+    /* Configure threshold */
+    val = val & ~(SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MAX_VOLTAGE_THR_MASK |
+                  SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MIN_VOLTAGE_THR_MASK);
+    val |= SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MAX_VOLTAGE_THR(
+        (v18.param1 * (1890U * 10U + v18.margin) + v18.param2 + 999999U) / 1000000U);
+    val |= SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_MIN_VOLTAGE_THR((v18.param1 * (1710U * 10U - v18.margin) + v18.param2) /
+                                                              1000000U);
+    SENSOR_CTRL->VSEN_CTRL_2_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_MASK;
+    /* Restore V18 sensor */
+    SENSOR_CTRL->VSEN_CTRL_2_REG_1 = val;
+
+    /* Disable V33 sensor */
+    val                            = SENSOR_CTRL->VSEN_CTRL_3_REG_1;
+    SENSOR_CTRL->VSEN_CTRL_3_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_MASK;
+    /* Configure threshold */
+    val = val & ~(SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MAX_VOLTAGE_THR_MASK |
+                  SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MIN_VOLTAGE_THR_MASK);
+    val |= SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MAX_VOLTAGE_THR(
+        (v33.param1 * (3630U * 10U + v33.margin) + v33.param2 + 999999U) / 1000000U);
+    val |= SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_MIN_VOLTAGE_THR((v33.param1 * (1850U * 10U - v33.margin) + v33.param2) /
+                                                              1000000U);
+    SENSOR_CTRL->VSEN_CTRL_3_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_MASK;
+    /* Restore V33 sensor */
+    SENSOR_CTRL->VSEN_CTRL_3_REG_1 = val;
+}
+
+void POWER_GetCurrentSleepConfig(power_sleep_config_t *config)
+{
+    assert(config != NULL);
+
+    config->pm2MemPuCfg = (~SYSCTL2->MEM_PD_CFG) & (SYSCTL2->MEM_PD_CTRL);
+    config->pm2AnaPuCfg = (~SYSCTL2->ANA_PDWN_PM2) & (uint32_t)kPOWER_Pm2AnaPuAll;
+    config->clkGate     = SYSCTL2->SOURCE_CLK_GATE;
+    config->memPdCfg    = PMU->MEM_CFG;
+    config->pm3BuckCfg  = PMU->PMIP_BUCK_CTRL & (uint32_t)kPOWER_Pm3BuckAll;
+}
+
+void POWER_InitPowerConfig(const power_init_config_t *config)
+{
+    uint32_t reg;
+    bool iBuck, gateCauRefClk;
+
+    assert(config != NULL);
+
+    iBuck         = config->iBuck;
+    gateCauRefClk = config->gateCauRefClk;
+
+    BUCK11->BUCK_CTRL_THREE_REG  = 0x10U;
+    BUCK18->BUCK_CTRL_THREE_REG  = 0x10U;
+    BUCK18->BUCK_CTRL_TWENTY_REG = 0x55U;
+
+    SYSCTL0->AUTOCLKGATEOVERRIDE0 = 0U;
+    /* Enable RAM dynamic clk gate */
+    SYSCTL0->AUTOCLKGATEOVERRIDE1 = 0U;
+    /* Enable ROM dynamic clk gate */
+    SYSCTL2->ROM_DYN_CLK_EN = SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_MASK;
+
+    PMU->PMIP_LDO_LVL = 0U;
+    if (iBuck)
+    {
+        /* No timeout with internal supply. */
+        PMU->TIME_OUT_CTRL = PMU_TIME_OUT_CTRL_V11_RDY_NO_TMT_MASK | PMU_TIME_OUT_CTRL_V18_RDY_NO_TMT_MASK |
+                             PMU_TIME_OUT_CTRL_PSW_MCI_RDY_NO_TMT_MASK;
+    }
+    else
+    {
+        /* Use timeout mode with external supply for VCORE and AVDD18. */
+        PMU->TIME_OUT_CTRL      = PMU_TIME_OUT_CTRL_PSW_MCI_RDY_NO_TMT_MASK;
+        PMU->TIME_OUT_CFG_VALUE = 0x3FFFFFFFU;
+    }
+
+    PMU->SOC_MEM_PDWN &= ~(PMU_SOC_MEM_PDWN_MSC_MEM_PDWN_CTRL_MASK | PMU_SOC_MEM_PDWN_SOCTOP_OTP_PDWN_CTRL_MASK);
+    PMU->CAU_SLP_CTRL = gateCauRefClk ? PMU_CAU_SLP_CTRL_CAU_SOC_SLP_CG_MASK : 0U;
+
+    /* Open usb clock and release reset */
+    reg                   = CLKCTL0->PSCCTL0;
+    CLKCTL0->PSCCTL0_SET  = CLKCTL0_PSCCTL0_SET_USB_MASK;
+    RSTCTL0->PRSTCTL0_CLR = RSTCTL0_PRSTCTL0_CLR_USB_MASK;
+    POWER_DelayUs(1U);
+    /* Restore usb clk. */
+    CLKCTL0->PSCCTL0 = reg;
+
+    /* Disable G2BIST CLK */
+    CLKCTL0->G2BIST_CLK_EN = 0U;
+}
+
+void POWER_SetPowerSwitchCallback(power_switch_callback_t pre,
+                                  void *preParam,
+                                  power_switch_callback_t post,
+                                  void *postParam)
+{
+    s_preSwitch       = pre;
+    s_preSwitchParam  = preParam;
+    s_postSwitch      = post;
+    s_postSwitchParam = postParam;
+}
+
+bool POWER_EnterPowerMode(uint32_t mode, const power_sleep_config_t *config)
+{
+    uint32_t primask;
+    bool ret = true;
+
+    assert(mode <= 4U);
+
+    /* Needed to make POWER_DelayUs() accurate. */
+    SystemCoreClockUpdate();
+
+    if (mode >= 1U)
+    {
+        primask = DisableGlobalIRQ();
+        POWER_PrePowerMode(mode, config);
+        if (mode == 3U)
+        {
+            POWER_EnterPm3Asm();
+        }
+        else
+        {
+            __DSB();
+            __WFI();
+            __ISB();
+        }
+        ret = POWER_PostPowerMode(mode);
+        EnableGlobalIRQ(primask);
+    }
+
+    return ret;
+}
+
+void POWER_PowerOnWlan(void)
+{
+    if (POWER_WLAN_POWER_STATUS() == POWER_WLAN_BLE_POWER_OFF)
+    {
+        /* Enable SW control */
+        PMU->SW_CTRL_WL |= PMU_SW_CTRL_WL_WL_EN_MASK;
+        /* WLan request buck on, then need wait 5 fast clk_pmu cycles, do psw on, then iso release */
+        PMU->SW_CTRL_WL |= PMU_SW_CTRL_WL_WL_BUCK_ON_REQ_MASK;
+        /* Wait buck on */
+        POWER_WAIT_PMU();
+
+        PMU->SW_CTRL_WL &= ~PMU_SW_CTRL_WL_PSW_WL_PD_MASK;
+        /* Wait PSW ready */
+        SystemCoreClockUpdate();
+        POWER_DelayUs(50U);
+        /* Disable ISO */
+        PMU->SW_CTRL_WL |= PMU_SW_CTRL_WL_MCI_ISO_WL_N_MASK;
+        /* Wait about 125us */
+        POWER_DelayUs(125U);
+        /* Release WLan */
+        PMU->SW_CTRL_WL &= ~PMU_SW_CTRL_WL_MCI_WL_PU_RST_MASK;
+    }
+}
+
+void POWER_PowerOffWlan(void)
+{
+    if (POWER_WLAN_POWER_STATUS() != POWER_WLAN_BLE_POWER_OFF)
+    {
+        /* Enable SW control */
+        PMU->SW_CTRL_WL |= PMU_SW_CTRL_WL_WL_EN_MASK;
+        /* Enable ISO before PSW off */
+        PMU->SW_CTRL_WL &= ~PMU_SW_CTRL_WL_MCI_ISO_WL_N_MASK;
+        POWER_WAIT_PMU();
+        PMU->SW_CTRL_WL |= PMU_SW_CTRL_WL_PSW_WL_PD_MASK;
+        /* Wait PSW off */
+        while ((SOCCTRL->PSW_VD2_RDY0 & (1UL << 1)) == 0U)
+        {
+        }
+        /* Reset WLan */
+        PMU->SW_CTRL_WL |= PMU_SW_CTRL_WL_MCI_WL_PU_RST_MASK;
+        /* Request buck off */
+        PMU->SW_CTRL_WL |= PMU_SW_CTRL_WL_WL_BUCK_OFF_REQ_MASK;
+    }
+}
+
+void POWER_PowerOnBle(void)
+{
+    if (POWER_BLE_POWER_STATUS() == POWER_WLAN_BLE_POWER_OFF)
+    {
+        /* Enable SW control */
+        PMU->SW_CTRL_BLE |= PMU_SW_CTRL_BLE_BLE_EN_MASK;
+        /* BLE request buck on, then need wait 5 fast clk_pmu cycles(about 96ns),do psw on, then iso release */
+        PMU->SW_CTRL_BLE |= PMU_SW_CTRL_BLE_BLE_BUCK_ON_REQ_MASK;
+        /* Wait buck on */
+        POWER_WAIT_PMU();
+        PMU->SW_CTRL_BLE &= ~PMU_SW_CTRL_BLE_PSW_BLE_PD_MASK;
+        /* Wait PSW ready */
+        SystemCoreClockUpdate();
+        POWER_DelayUs(50U);
+        /* Disable ISO */
+        PMU->SW_CTRL_BLE |= PMU_SW_CTRL_BLE_MCI_ISO_BLE_N_MASK;
+        /* Wait about 125us */
+        POWER_DelayUs(125U);
+        /* Release BLE */
+        PMU->SW_CTRL_BLE &= ~PMU_SW_CTRL_BLE_MCI_BLE_PU_RST_MASK;
+    }
+}
+
+void POWER_PowerOffBle(void)
+{
+    if (POWER_BLE_POWER_STATUS() != POWER_WLAN_BLE_POWER_OFF)
+    {
+        /* Enable SW control */
+        PMU->SW_CTRL_BLE |= PMU_SW_CTRL_BLE_BLE_EN_MASK;
+        /* Enable ISO before PSW off */
+        PMU->SW_CTRL_BLE &= ~PMU_SW_CTRL_BLE_MCI_ISO_BLE_N_MASK;
+        POWER_WAIT_PMU();
+        PMU->SW_CTRL_BLE |= PMU_SW_CTRL_BLE_PSW_BLE_PD_MASK;
+        /* Wait PSW off */
+        while ((SOCCTRL->PSW_VD2_RDY0 & (1UL << 9)) == 0U)
+        {
+        }
+        /* Reset BLE */
+        PMU->SW_CTRL_BLE |= PMU_SW_CTRL_BLE_MCI_BLE_PU_RST_MASK;
+        /* Request buck off */
+        PMU->SW_CTRL_BLE |= PMU_SW_CTRL_BLE_BLE_BUCK_OFF_REQ_MASK;
+    }
+}
+
+void POWER_PowerOnGau(void)
+{
+    GAU_BG->CTRL &= ~BG_CTRL_PD_MASK;
+    while ((GAU_BG->STATUS & BG_STATUS_RDY_MASK) == 0U)
+    {
+    }
+}
+
+void POWER_PowerOffGau(void)
+{
+    GAU_BG->CTRL |= BG_CTRL_PD_MASK;
+}
+
+void POWER_EnableCaptSlowPulseTimer(capt_slow_pulse_width_t width,
+                                    capt_slow_pulse_edge_t edge,
+                                    uint32_t timeout,
+                                    capt_pulse_timer_callback_t cb,
+                                    void *param)
+{
+    s_captPulseCb            = cb;
+    s_captPulseCbParam       = param;
+    PMU->CAPT_PULSE          = PMU_CAPT_PULSE_IRQ_CLR_MASK | PMU_CAPT_PULSE_IRQ_MSK_MASK;
+    PMU->CAPT_PULSE_BASE_VAL = timeout;
+    PMU->CAPT_PULSE          = PMU_CAPT_PULSE_IC_WIDTH_CLK_CNT(width) | PMU_CAPT_PULSE_IC_EDGE_CLK_CNT(edge);
+    PMU->CAPT_PULSE |= PMU_CAPT_PULSE_CAPTURE_SLOW_PULSE_CNT_EN_MASK;
+}
+
+void POWER_EnableCaptFastPulseTimer(uint32_t timeout, capt_pulse_timer_callback_t cb, void *param)
+{
+    s_captPulseCb            = cb;
+    s_captPulseCbParam       = param;
+    PMU->CAPT_PULSE          = PMU_CAPT_PULSE_IRQ_CLR_MASK | PMU_CAPT_PULSE_IRQ_MSK_MASK;
+    PMU->CAPT_PULSE_BASE_VAL = timeout;
+    PMU->CAPT_PULSE          = PMU_CAPT_PULSE_CLK_SEL_MASK;
+    PMU->CAPT_PULSE |= PMU_CAPT_PULSE_CAPTURE_FAST_PULSE_CNT_EN_MASK;
+}
+
+void POWER_DisableCaptPulseTimer(void)
+{
+    PMU->CAPT_PULSE = PMU_CAPT_PULSE_IRQ_CLR_MASK | PMU_CAPT_PULSE_IRQ_MSK_MASK;
+}
+
+void Power_InitLoadGdetCfg(power_load_gdet_cfg loadFunc, const power_gdet_data_t *data, uint32_t pack)
+{
+    assert(loadFunc != NULL);
+    assert(data != NULL);
+    assert(pack <= 2U);
+
+    s_gdetCfgloadFunc = loadFunc;
+    (void)memcpy(&s_gdetCfgData, data, sizeof(power_gdet_data_t));
+    s_gdetCfgData.CFG[3] = POWER_TrimSvc(data->CFG[3], pack);
+}
+
+/* Configure voltage threshold */
+void POWER_InitVoltage(uint32_t dro, uint32_t pack)
+{
+    int32_t i;
+    uint8_t val;
+
+    SystemCoreClockUpdate();
+
+    /* LPBG trim */
+    BUCK11->BUCK_CTRL_EIGHTEEN_REG = 0x6U;
+
+    if (dro == 0U)
+    { /* Boot voltage 1.11V */
+        val = 0x60U;
+    }
+    else
+    {
+        /* Change buck level */
+        dro /= 1000U;
+        i = 36 - (int32_t)dro;
+        assert((i >= 0) && ((uint32_t)i < ARRAY_SIZE(s_droTable)));
+        val = s_droTable[i];
+    }
+    PMU->PMIP_BUCK_LVL = PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL(0x60U) |  /* 1.8V */
+                         PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL(0x22U) |  /* 0.8V */
+                         PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL(0x60U) | /* 1.8V */
+                         PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL(val);
+    /* Delay 600us */
+    POWER_DelayUs(600U);
+
+    POWER_InitVSensorThreshold(val, pack);
+}
+
+void POWER_DisableGDetVSensors(void)
+{
+    uint32_t val;
+    uint32_t pscctl0, pscctl1, pscctl2;
+    uint32_t rstctl0, rstctl1;
+
+    if (s_gdetSensorContext.disableCount == 0)
+    {
+        pscctl0 = CLKCTL0->PSCCTL0;
+        pscctl1 = CLKCTL0->PSCCTL1;
+        pscctl2 = CLKCTL0->PSCCTL2;
+        rstctl0 = RSTCTL0->PRSTCTL0;
+        rstctl1 = RSTCTL0->PRSTCTL1;
+
+        /* Enable ELS/ITRC clock */
+        CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_ELS_MASK;
+        CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_ELS_APB_MASK;
+        CLKCTL0->PSCCTL2_SET = CLKCTL0_PSCCTL2_ITRC_MASK;
+        /* Clear ELS reset */
+        RSTCTL0->PRSTCTL0_CLR = RSTCTL0_PRSTCTL0_ELS_MASK;
+        RSTCTL0->PRSTCTL1_CLR = RSTCTL0_PRSTCTL1_ELS_APB_MASK;
+
+        s_gdetSensorContext.ELS_EN = ELS->ELS_CTRL & ELS_ELS_CTRL_ELS_EN_MASK;
+
+        /* Save GDET VSEN config */
+        POWER_SaveGdetVSensorConfig();
+        if (s_gdetSensorContext.ELS_EN != 0U)
+        {
+            s_gdetSensorContext.ELS_INT_ENABLE = ELS->ELS_INT_ENABLE;
+        }
+
+        /* Disable ITRC interrupts, especially security sensors */
+        /* Disable V11 sensor */
+        val = SENSOR_CTRL->VSEN_CTRL_1_REG_1 & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK;
+        SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val;
+
+        /* Disable V18 sensor */
+        val = SENSOR_CTRL->VSEN_CTRL_2_REG_1 & ~SENSOR_CTRL_VSEN_CTRL_2_REG_1_VSEN_SW_ENABLE_MASK;
+        SENSOR_CTRL->VSEN_CTRL_2_REG_1 = val;
+
+        /* Disable V33 sensor */
+        val = SENSOR_CTRL->VSEN_CTRL_3_REG_1 & ~SENSOR_CTRL_VSEN_CTRL_3_REG_1_VSEN_SW_ENABLE_MASK;
+        SENSOR_CTRL->VSEN_CTRL_3_REG_1 = val;
+
+        if (s_gdetSensorContext.ELS_EN != 0U)
+        {
+            /* Disable CSS_INT_ENABLE[GDET_INT_EN] bit field */
+            ELS->ELS_INT_ENABLE &= ~ELS_ELS_INT_ENABLE_GDET_INT_EN_MASK;
+        }
+
+        /* Disable aGDET/LVD/HVD interrupts in ITRC */
+        val             = ITRC->OUT0_SEL0 & ~ITRC_OUT_SEL_MASK;
+        ITRC->OUT0_SEL0 = val | ITRC_OUT_SEL_DISABLE;
+        val             = ITRC->OUT1_SEL0 & ~ITRC_OUT_SEL_MASK;
+        ITRC->OUT1_SEL0 = val | ITRC_OUT_SEL_DISABLE;
+
+        val                        = ITRC->OUT0_SEL0_EVENT16_31 & ~ITRC_OUT_SEL_EVENT_MASK;
+        ITRC->OUT0_SEL0_EVENT16_31 = val | ITRC_OUT_SEL_EVENT_DISABLE;
+        val                        = ITRC->OUT1_SEL0_EVENT16_31 & ~ITRC_OUT_SEL_EVENT_MASK;
+        ITRC->OUT1_SEL0_EVENT16_31 = val | ITRC_OUT_SEL_EVENT_DISABLE;
+
+        /* Restore ELS/ITRC clock */
+        CLKCTL0->PSCCTL0 = pscctl0;
+        CLKCTL0->PSCCTL1 = pscctl1;
+        CLKCTL0->PSCCTL2 = pscctl2;
+        /* Restore ELS reset */
+        RSTCTL0->PRSTCTL0 = rstctl0;
+        RSTCTL0->PRSTCTL1 = rstctl1;
+    }
+
+    s_gdetSensorContext.disableCount++;
+}
+
+bool POWER_EnableGDetVSensors(void)
+{
+    uint32_t pscctl0, pscctl1, pscctl2;
+    uint32_t rstctl0, rstctl1;
+    bool retval = true;
+
+    s_gdetSensorContext.disableCount--;
+
+    if (s_gdetSensorContext.disableCount == 0)
+    {
+        pscctl0 = CLKCTL0->PSCCTL0;
+        pscctl1 = CLKCTL0->PSCCTL1;
+        pscctl2 = CLKCTL0->PSCCTL2;
+        rstctl0 = RSTCTL0->PRSTCTL0;
+        rstctl1 = RSTCTL0->PRSTCTL1;
+
+        /* Enable ELS/ITRC clock */
+        CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_ELS_MASK;
+        CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_ELS_APB_MASK;
+        CLKCTL0->PSCCTL2_SET = CLKCTL0_PSCCTL2_ITRC_MASK;
+        /* Clear ELS reset */
+        RSTCTL0->PRSTCTL0_CLR = RSTCTL0_PRSTCTL0_ELS_MASK;
+        RSTCTL0->PRSTCTL1_CLR = RSTCTL0_PRSTCTL1_ELS_APB_MASK;
+
+        /* Only in the normal flow that GDET_INT_EN is disabled, we will restore GDET config here.
+         * An exception is that we call POWER_DisableGDetVSensors() before PM3 and then wake up
+         * from ROM. In that case, ELS_INT_ENABLE will be set by ROM again and we shouldn't config
+         * GDET here. */
+        if (((ELS->ELS_CTRL & ELS_ELS_CTRL_ELS_EN_MASK) != 0U) &&
+            (ELS->ELS_INT_ENABLE & ELS_ELS_INT_ENABLE_GDET_INT_EN_MASK) == 0U)
+        {
+            POWER_RestoreGdetVSensorConfig();
+            if ((s_gdetSensorContext.ELS_EN != 0U) && (s_gdetSensorContext.ELS_INT_ENABLE != 0U))
+            {
+                /* To enable GDET, load function must be configured. */
+                if (s_gdetCfgloadFunc == NULL)
+                {
+                    retval = false;
+                }
+                else
+                {
+                    /* GDET config must be loaded correctly for GDET working. */
+                    retval = s_gdetCfgloadFunc(&s_gdetCfgData);
+                }
+
+                /* Clear GDET errors */
+                ELS->ELS_INT_STATUS_CLR =
+                    ELS_ELS_INT_STATUS_CLR_INT_CLR_MASK | ELS_ELS_INT_STATUS_CLR_GDET_INT_CLR_MASK;
+                ELS->ELS_ERR_STATUS_CLR  = ELS_ELS_ERR_STATUS_CLR_ERR_CLR_MASK;
+                ELS->ELS_GDET_EVTCNT_CLR = ELS_ELS_GDET_EVTCNT_CLR_GDET_EVTCNT_CLR_MASK;
+                /* Clear Sensor errors */
+                SENSOR_CTRL->SEN_CLR_REG = 0x3CU;
+                /* Clear ITRC status */
+                ITRC->STATUS0 = ITRC->STATUS0;
+                ITRC->STATUS1 = ITRC->STATUS1;
+                if (retval)
+                {
+                    ELS->ELS_INT_ENABLE = s_gdetSensorContext.ELS_INT_ENABLE;
+                }
+            }
+        }
+
+        /* Restore ELS/ITRC clock */
+        CLKCTL0->PSCCTL0 = pscctl0;
+        CLKCTL0->PSCCTL1 = pscctl1;
+        CLKCTL0->PSCCTL2 = pscctl2;
+        /* Restore ELS reset */
+        RSTCTL0->PRSTCTL0 = rstctl0;
+        RSTCTL0->PRSTCTL1 = rstctl1;
+    }
+
+    return retval;
+}
+
+uint32_t POWER_TrimSvc(uint32_t gdetTrim, uint32_t pack)
+{
+    int32_t x;
+    int32_t y1, y3;
+    uint32_t trimSvc = gdetTrim;
+    uint32_t clk;
+    uint32_t rst;
+    uint32_t revision = SOCCTRL->CHIP_INFO & SOCCIU_CHIP_INFO_REV_NUM_MASK;
+
+    if (revision == 2U)
+    {
+        /* A2 */
+        /* Autotrim value at [7:0] */
+        x = (int32_t)(uint32_t)(gdetTrim & 0xFFUL);
+        if (pack == 0U)
+        {
+            /* QFN */
+            y1 = (18 * x * x) + (801 * x) + 437290;
+            y3 = y1 / 10000;
+        }
+        else if (pack == 1U)
+        {
+            /* CSP */
+            y1 = (82 * x * x) - (5171 * x) + 559320;
+            y3 = y1 / 10000;
+        }
+        else
+        {
+            /* BGA */
+            assert(pack == 2U);
+            y1 = (25 * x * x) + (1337 * x) + 381140;
+            y3 = y1 / 10000;
+        }
+
+        trimSvc = ((uint32_t)y3) << 24;
+
+        clk = CLKCTL0->PSCCTL0;
+        rst = RSTCTL0->PRSTCTL0;
+        /* Enable AON MEM clock/reset. */
+        CLKCTL0->PSCCTL0_SET  = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK;
+        RSTCTL0->PRSTCTL0_CLR = RSTCTL0_PRSTCTL0_CLR_AON_MEM_MASK;
+        POWER_WRITE_MEM32(0x4015C00CU, trimSvc);
+        /* Restore AON MEM clock/reset */
+        CLKCTL0->PSCCTL0  = clk;
+        RSTCTL0->PRSTCTL0 = rst;
+    }
+
+    return trimSvc;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_power.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_power.h
new file mode 100644
index 0000000000..a1949bef5a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_power.h
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2020-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup power
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief POWER driver version 2.5.0. */
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*@}*/
+
+/*!
+ * @brief Pin edge for wakeup.
+ */
+typedef enum _power_wakeup_edge
+{
+    kPOWER_WakeupEdgeLow  = 0U, /*!< Wakeup on pin low level. */
+    kPOWER_WakeupEdgeHigh = 1U, /*!< Wakeup on pin high level. */
+} power_wakeup_edge_t;
+
+/*!
+ * @brief Wakeup pin.
+ */
+typedef enum _power_wakeup_pin
+{
+    kPOWER_WakeupPin0 = 0U, /*!< Wakeup0 pin. */
+    kPOWER_WakeupPin1 = 1U, /*!< Wakeup1 pin. */
+} power_wakeup_pin_t;
+
+/*!
+ * @brief Reset cause.
+ */
+typedef enum _power_reset_cause
+{
+    kPOWER_ResetCauseSysResetReq = 1U << 0U, /*!< CM33 system soft reset request. */
+    kPOWER_ResetCauseLockup      = 1U << 1U, /*!< CM33 locked up. */
+    kPOWER_ResetCauseWdt         = 1U << 2U, /*!< Watchdog timer. */
+    kPOWER_ResetCauseApResetReq  = 1U << 3U, /*!< Debug mailbox reset. */
+    kPOWER_ResetCauseCodeWdt     = 1U << 4U, /*!< Code watchdog timer. */
+    kPOWER_ResetCauseItrc        = 1U << 5U, /*!< ITRC_CHIP reset. */
+    kPOWER_ResetCauseResetB      = 1U << 6U, /*!< sw_resetb_scantest reset. */
+    kPOWER_ResetCauseAll         = 0x7FU,    /*!< All reset causes. Used in POWER_ClearResetCause(). */
+} power_reset_cause_t;
+
+/*!
+ * @brief Reset source.
+ */
+typedef enum _power_reset_source
+{
+    kPOWER_ResetSourceSysResetReq = 1U << 0U, /*!< CM33 system soft reset request. */
+    kPOWER_ResetSourceLockup      = 1U << 1U, /*!< CM33 locked up. */
+    kPOWER_ResetSourceWdt         = 1U << 2U, /*!< Watchdog timer. */
+    kPOWER_ResetSourceApResetReq  = 1U << 3U, /*!< Debug mailbox reset. */
+    kPOWER_ResetSourceCodeWdt     = 1U << 4U, /*!< Code watchdog timer. */
+    kPOWER_ResetSourceItrc        = 1U << 5U, /*!< ITRC_CHIP reset. */
+    kPOWER_ResetSourceAll         = 0x3FU,    /*!< All reset sources. */
+} power_reset_source_t;
+
+/*!
+ * @brief PM2 mem power up bits definition
+ */
+enum _pm2_mem_pu_bits
+{
+    kPOWER_Pm2MemPuEnet    = (1UL << 28),
+    kPOWER_Pm2MemPuSdio    = (1UL << 27),
+    kPOWER_Pm2MemPuOtp     = (1UL << 26),
+    kPOWER_Pm2MemPuRom     = (1UL << 25),
+    kPOWER_Pm2MemPuFlexspi = (1UL << 24),
+    kPOWER_Pm2MemPuPq      = (1UL << 23),
+    kPOWER_Pm2MemPuPkc     = (1UL << 22),
+    kPOWER_Pm2MemPuEls     = (1UL << 21),
+    kPOWER_Pm2MemPuAon1    = (1UL << 20),
+    kPOWER_Pm2MemPuAon0    = (1UL << 19),
+    kPOWER_Pm2MemPuSram18  = (1UL << 18),
+    kPOWER_Pm2MemPuSram17  = (1UL << 17),
+    kPOWER_Pm2MemPuSram16  = (1UL << 16),
+    kPOWER_Pm2MemPuSram15  = (1UL << 15),
+    kPOWER_Pm2MemPuSram14  = (1UL << 14),
+    kPOWER_Pm2MemPuSram13  = (1UL << 13),
+    kPOWER_Pm2MemPuSram12  = (1UL << 12),
+    kPOWER_Pm2MemPuSram11  = (1UL << 11),
+    kPOWER_Pm2MemPuSram10  = (1UL << 10),
+    kPOWER_Pm2MemPuSram9   = (1UL << 9),
+    kPOWER_Pm2MemPuSram8   = (1UL << 8),
+    kPOWER_Pm2MemPuSram7   = (1UL << 7),
+    kPOWER_Pm2MemPuSram6   = (1UL << 6),
+    kPOWER_Pm2MemPuSram5   = (1UL << 5),
+    kPOWER_Pm2MemPuSram4   = (1UL << 4),
+    kPOWER_Pm2MemPuSram3   = (1UL << 3),
+    kPOWER_Pm2MemPuSram2   = (1UL << 2),
+    kPOWER_Pm2MemPuSram1   = (1UL << 1),
+    kPOWER_Pm2MemPuSram0   = (1UL << 0),
+    kPOWER_Pm2MemPuAll     = (0x1FFFFFFFUL),
+};
+
+/*!
+ * @brief PM2 ana power up bits definition
+ */
+enum _pm2_ana_pu_bits
+{
+    kPOWER_Pm2AnaPuT3      = (1UL << 6),
+    kPOWER_Pm2AnaPuTcpuTop = (1UL << 5),
+    kPOWER_Pm2AnaPuTddrTop = (1UL << 4),
+    kPOWER_Pm2AnaPuAnaTop  = (1UL << 3),
+    kPOWER_Pm2AnaPuGau     = (1UL << 2),
+    kPOWER_Pm2AnaPuUsb     = (1UL << 1),
+    kPOWER_Pm2AnaPuAvpll   = (1UL << 0),
+    kPOWER_Pm2AnaPuAll     = (0x7FUL),
+};
+
+/*!
+ * @brief clock gate bits definition
+ */
+enum _clk_gate_bits
+{
+    /* Only bit 2 is configuable, others contrlled by HW */
+    kPOWER_ClkGateTddrMciEnet = (1UL << 2),
+    kPOWER_ClkGateAll         = (1UL << 2),
+};
+
+/*!
+ * @brief PM3 buck control bits definition
+ */
+enum _clk_pm3_buck_bits
+{
+    kPOWER_Pm3Buck18  = (1UL << 7), /*!< 1: Use normal buck18 level in PM3. 0: Use sleep buck18 level in PM3 */
+    kPOWER_Pm3Buck11  = (1UL << 6), /*!< 1: Use normal buck11 level in PM3. 0: Use sleep buck11 level in PM3 */
+    kPOWER_Pm3BuckAll = (0xC0UL),
+};
+
+/*!
+ * @brief Capture slow pulse width
+ */
+typedef enum _capt_slow_pulse_width
+{
+    kPOWER_CaptSlowPulseWidth1 = 0U,
+    kPOWER_CaptSlowPulseWidth2 = 1U,
+    kPOWER_CaptSlowPulseWidth3 = 2U,
+    kPOWER_CaptSlowPulseWidth4 = 3U,
+    kPOWER_CaptSlowPulseWidth5 = 4U,
+    kPOWER_CaptSlowPulseWidth6 = 5U,
+    kPOWER_CaptSlowPulseWidth7 = 6U,
+} capt_slow_pulse_width_t;
+
+/*!
+ * @brief Capture slow pulse edge
+ */
+typedef enum _capt_slow_pulse_edge
+{
+    kPOWER_CaptSlowPulseEdgeRising  = 0U,
+    kPOWER_CaptSlowPulseEdgeFalling = 1U,
+    kPOWER_CaptSlowPulseEdgeAny     = 2U,
+} capt_slow_pulse_edge_t;
+
+/*!
+ * @brief Capture timer callback function
+ * @param param : User parameter for callback.
+ */
+typedef void (*capt_pulse_timer_callback_t)(void *param);
+
+/*!
+ * @brief Power mode switch callback function
+ * @param mode : Power mode to switch.
+ * @param param : User parameter for callback.
+ */
+typedef void (*power_switch_callback_t)(uint32_t mode, void *param);
+
+/*!
+ * @brief Init configuration.
+ */
+typedef struct _power_init_config
+{
+    bool iBuck;         /*!< true: VCORE and AVDD18 supplied from iBuck; false: supplied from external DCDC. */
+    bool gateCauRefClk; /*!< true: CAU_SOC_SLP_REF_GEN_CLK gated; false: CAU_SOC_SLP_REF_GEN_CLK on. */
+} power_init_config_t;
+
+/*!
+ * @brief Sleep configuration.
+ */
+typedef struct _power_sleep_config
+{
+    uint32_t
+        pm2MemPuCfg; /*!< Modules to keep powered on in PM2 mode. Logical OR of the enums in @ref _pm2_mem_pu_bits. */
+    uint32_t pm2AnaPuCfg; /*!< Ana to keep powered on in PM2 mode. Logical OR of the enums in @ref _pm2_ana_pu_bits. */
+    uint32_t clkGate;     /*!< Source clock gate control. Logical OR of the enums in @ref _clk_gate_bits. */
+    uint32_t memPdCfg;    /*!< PMU MEM_CFG: Power Down memory configuration. Bit0-5 for PM3, bit8 for PM4.
+                                            bit0: ram0-5 384KB
+                                            bit1: ram6 64KB
+                                            bit2: ram7 64KB
+                                            bit3: ram8-9 128KB
+                                            bit4: ram10-13 256KB
+                                            bit5: ram14-18 320KB.
+                                            bit8: aon mem higher 8KB */
+    uint32_t pm3BuckCfg;  /*!< PMIP BUCK control in PM3 mode. Logical OR of the enums in @ref _clk_pm3_buck_bits. */
+} power_sleep_config_t;
+
+/*!
+ * @brief Glitch detector configuration.
+ */
+typedef struct _power_gdet_data
+{
+    uint32_t CFG[6];
+    uint32_t TRIM0;
+} power_gdet_data_t;
+
+/*!
+ * @brief Glitch detector configuration load function.
+ */
+typedef bool (*power_load_gdet_cfg)(power_gdet_data_t *data);
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief   Enable system reset source
+ * @param   source   : A bitmask of of @ref power_reset_source_t
+ */
+__STATIC_INLINE void POWER_EnableResetSource(uint32_t source)
+{
+    assert((source & ~(uint32_t)kPOWER_ResetSourceAll) == 0U);
+
+    PMU->SYS_RST_EN |= source;
+}
+
+/**
+ * @brief   Disable system reset source
+ * @param   source   : A bitmask of of @ref power_reset_source_t
+ */
+__STATIC_INLINE void POWER_DisableResetSource(uint32_t source)
+{
+    assert((source & ~(uint32_t)kPOWER_ResetSourceAll) == 0U);
+
+    PMU->SYS_RST_EN &= ~source;
+}
+
+/**
+ * @brief   Get last reset cause
+ * @return  Or'ed cause of @ref power_reset_cause_t
+ */
+__STATIC_INLINE uint32_t POWER_GetResetCause(void)
+{
+    /* On reset, PMU->SYS_RST_STATUS is backed up in RF_SYSCON->WO_SCRATCH_REG[3]
+       and cleared by ROM */
+    return RF_SYSCON->WO_SCRATCH_REG[3] & (uint32_t)kPOWER_ResetCauseAll;
+}
+
+/**
+ * @brief   Clear last reset cause
+ * @param   cause   : A bitmask of of @ref power_reset_cause_t
+ */
+__STATIC_INLINE void POWER_ClearResetCause(uint32_t cause)
+{
+    assert((cause & ~(uint32_t)kPOWER_ResetCauseAll) == 0U);
+
+    PMU->SYS_RST_CLR = cause;
+}
+
+/**
+ * @brief   Configure pin edge for wakeup
+ * @param   pin     : Wakeup pin
+ * @param   edge    : Pin level for wakeup
+ */
+__STATIC_INLINE void POWER_ConfigWakeupPin(power_wakeup_pin_t pin, power_wakeup_edge_t edge)
+{
+    PMU->WAKEUP_LEVEL = (PMU->WAKEUP_LEVEL & ~(1UL << (uint8_t)pin)) | ((uint32_t)edge << (uint8_t)pin);
+}
+
+/**
+ * @brief   Check if IRQ is the wakeup source
+ * @param   irq   : IRQ number
+ * @return  true if IRQ is the wakeup source, false otherwise.
+ */
+bool POWER_GetWakeupStatus(IRQn_Type irq);
+
+/**
+ * @brief   Clear wakeup status
+ * @param   irq   : IRQ number
+ */
+void POWER_ClearWakeupStatus(IRQn_Type irq);
+
+/**
+ * @brief   Enable the Wakeup interrupt.
+ * @param   irq   : IRQ number
+ */
+void POWER_EnableWakeup(IRQn_Type irq);
+
+/**
+ * @brief   Disable the Wakeup interrupts.
+ * @param   irq   : IRQ number
+ */
+void POWER_DisableWakeup(IRQn_Type irq);
+
+/**
+ * @brief   Set power mode on idle.
+ * @param   mode : 0 ~ 4 stands for PM0 ~ PM4.
+ */
+AT_QUICKACCESS_SECTION_CODE(void POWER_SetSleepMode(uint32_t mode));
+
+/**
+ * @brief   Get power mode waken up from.
+ * @return  Power mode.
+ */
+__STATIC_INLINE uint32_t POWER_GetWakenMode(void)
+{
+    return (PMU->PWR_MODE_STATUS & PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_MASK) + 1U;
+}
+
+/**
+ * @brief   Get current sleep configuration.
+ * @param   config : Pointer to config structure to save current config.
+ */
+void POWER_GetCurrentSleepConfig(power_sleep_config_t *config);
+
+/**
+ * @brief   Initialize power configuration.
+ * @param   config : Pointer to init config structure.
+ */
+void POWER_InitPowerConfig(const power_init_config_t *config);
+
+/**
+ * @brief   Configure CAU_SOC_SLP_REF_GEN_CLK on/off status in SoC sleep mode.
+ * @param   pdCau : true for clock off; false for clock on.
+ */
+void POWER_ConfigCauInSleep(bool pdCau);
+
+/**
+ * @brief   Set power mode switch callback. The callbacks are called with interrupt disabled.
+ * @param   pre : Function called before power mode switch
+ * @param   preParam : User parameter for pre callback
+ * @param   post : Function called after power mode switch
+ * @param   postParam : User parameter for post callback
+ */
+void POWER_SetPowerSwitchCallback(power_switch_callback_t pre,
+                                  void *preParam,
+                                  power_switch_callback_t post,
+                                  void *postParam);
+
+/**
+ * @brief   Switch system into certain power mode.
+ * @param   mode : 0 ~ 4 stands for PM0 ~ PM4.
+ * @param   config : Sleep configuration on PM2-PM4.
+ * @return  True for success, else failure.
+ */
+AT_QUICKACCESS_SECTION_CODE(bool POWER_EnterPowerMode(uint32_t mode, const power_sleep_config_t *config));
+
+/**
+ * @brief   Power on WLAN.
+ */
+void POWER_PowerOnWlan(void);
+
+/**
+ * @brief   Power off WLAN.
+ */
+void POWER_PowerOffWlan(void);
+
+/**
+ * @brief   Enable MCI wakeup WLAN
+ * @param   wlWakeup : 8 bits wakeup mask
+ */
+__STATIC_INLINE void PMU_EnableWlanWakeup(uint8_t wlWakeup)
+{
+    PMU->WLAN_CTRL |= PMU_WLAN_CTRL_WL_WAKEUP(wlWakeup);
+}
+
+/**
+ * @brief   Disable MCI wakeup WLAN
+ * @param   wlWakeup : 8 bits wakeup mask
+ */
+__STATIC_INLINE void PMU_DisableWlanWakeup(uint8_t wlWakeup)
+{
+    PMU->WLAN_CTRL &= ~PMU_WLAN_CTRL_WL_WAKEUP(wlWakeup);
+}
+
+/**
+ * @brief   Power on BLE.
+ */
+void POWER_PowerOnBle(void);
+
+/**
+ * @brief   Power off BLE.
+ */
+void POWER_PowerOffBle(void);
+
+/**
+ * @brief   Enable MCI wakeup BLE
+ * @param   bleWakeup : 8 bits wakeup mask
+ */
+__STATIC_INLINE void PMU_EnableBleWakeup(uint8_t bleWakeup)
+{
+    PMU->BLE_CTRL |= PMU_BLE_CTRL_BLE_WAKEUP(bleWakeup);
+}
+
+/**
+ * @brief   Disable MCI wakeup BLE
+ * @param   bleWakeup : 8 bits wakeup mask
+ */
+__STATIC_INLINE void PMU_DisableBleWakeup(uint8_t bleWakeup)
+{
+    PMU->BLE_CTRL &= ~PMU_BLE_CTRL_BLE_WAKEUP(bleWakeup);
+}
+
+/**
+ * @brief   Power on GAU.
+ */
+void POWER_PowerOnGau(void);
+
+/**
+ * @brief   Power off GAU.
+ */
+void POWER_PowerOffGau(void);
+
+/**
+ * @brief   Enable capture slow pulse timer with 32768Hz clock source
+ * @param   width    : input capture filter width in cycles
+ * @param   edge     : trigger condition of counter
+ * @param   timeout  : timer expire counter which will trigger callback
+ * @param   callback : callback function on timer expire
+ * @param   param    : callback parameter
+ */
+void POWER_EnableCaptSlowPulseTimer(capt_slow_pulse_width_t width,
+                                    capt_slow_pulse_edge_t edge,
+                                    uint32_t timeout,
+                                    capt_pulse_timer_callback_t cb,
+                                    void *param);
+
+/**
+ * @brief   Enable capture fast pulse timer with 3.84/4MHz clock source
+ * @param   timeout  : timer expire counter which will trigger callback
+ * @param   callback : callback function on timer expire
+ * @param   param    : callback parameter
+ */
+void POWER_EnableCaptFastPulseTimer(uint32_t timeout, capt_pulse_timer_callback_t cb, void *param);
+
+/**
+ * @brief   Disable capture pulse timer
+ */
+void POWER_DisableCaptPulseTimer(void);
+
+/**
+ * @brief   Configure power rail voltage and LVD/HVD threshold.
+ * @param   dro  : trim value from fuse.
+ * @param   pack : Device package type: 0 - QFN, 1 - CSP, 2 - BGA
+ */
+void POWER_InitVoltage(uint32_t dro, uint32_t pack);
+
+/**
+ * @brief   Initialize glitch detector configuration.
+ * @param   loadFunc : function pointer to the GDET load configuration.
+ * @param   data     : GDET config data loaded from fuse.
+ * @param   pack     : Device package type: 0 - QFN, 1 - CSP, 2 - BGA
+ */
+void Power_InitLoadGdetCfg(power_load_gdet_cfg loadFunc, const power_gdet_data_t *data, uint32_t pack);
+
+/**
+ * @brief   Disable GDET and VSensors
+ */
+AT_QUICKACCESS_SECTION_CODE(void POWER_DisableGDetVSensors(void));
+
+/**
+ * @brief   Enable GDET and VSensors
+ * @return  True for success, else failure.
+ */
+AT_QUICKACCESS_SECTION_CODE(bool POWER_EnableGDetVSensors(void));
+
+/**
+ * @brief   Apply SVC GDC equation and get the SVC trim configuration
+ * @param   gdetTrim : GDET trim value from fuse.
+ * @param   pack     : Device package type: 0 - QFN, 1 - CSP, 2 - BGA
+ */
+uint32_t POWER_TrimSvc(uint32_t gdetTrim, uint32_t pack);
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_POWER_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_reset.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_reset.c
new file mode 100644
index 0000000000..9a0c8db329
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_reset.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2021, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0x0000FF00u) >> 8;
+    const uint32_t bitPos   = ((uint32_t)peripheral & 0x000000FFu);
+    const uint32_t bitMask  = 1UL << bitPos;
+
+    assert(bitPos < 32u);
+
+    switch (regIndex)
+    {
+        case RST_CTL0_PSCCTL0:
+            RSTCTL0->PRSTCTL0_SET = bitMask;
+            while (0u == (RSTCTL0->PRSTCTL0 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL0_PSCCTL1:
+            RSTCTL0->PRSTCTL1_SET = bitMask;
+            while (0u == (RSTCTL0->PRSTCTL1 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL0_PSCCTL2:
+            RSTCTL0->PRSTCTL2_SET = bitMask;
+            while (0u == (RSTCTL0->PRSTCTL2 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL1_PSCCTL0:
+            RSTCTL1->PRSTCTL0_SET = bitMask;
+            while (0u == (RSTCTL1->PRSTCTL0 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL1_PSCCTL1:
+            RSTCTL1->PRSTCTL1_SET = bitMask;
+            while (0u == (RSTCTL1->PRSTCTL1 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL1_PSCCTL2:
+            RSTCTL1->PRSTCTL2_SET = bitMask;
+            while (0u == (RSTCTL1->PRSTCTL2 & bitMask))
+            {
+            }
+            break;
+        default:
+            /* Added comments to prevent the violation of MISRA C-2012 rule. */
+            break;
+    }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0x0000FF00u) >> 8;
+    const uint32_t bitPos   = ((uint32_t)peripheral & 0x000000FFu);
+    const uint32_t bitMask  = 1UL << bitPos;
+
+    assert(bitPos < 32u);
+
+    switch (regIndex)
+    {
+        case RST_CTL0_PSCCTL0:
+            RSTCTL0->PRSTCTL0_CLR = bitMask;
+            while (bitMask == (RSTCTL0->PRSTCTL0 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL0_PSCCTL1:
+            RSTCTL0->PRSTCTL1_CLR = bitMask;
+            while (bitMask == (RSTCTL0->PRSTCTL1 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL0_PSCCTL2:
+            RSTCTL0->PRSTCTL2_CLR = bitMask;
+            while (bitMask == (RSTCTL0->PRSTCTL2 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL1_PSCCTL0:
+            RSTCTL1->PRSTCTL0_CLR = bitMask;
+            while (bitMask == (RSTCTL1->PRSTCTL0 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL1_PSCCTL1:
+            RSTCTL1->PRSTCTL1_CLR = bitMask;
+            while (bitMask == (RSTCTL1->PRSTCTL1 & bitMask))
+            {
+            }
+            break;
+        case RST_CTL1_PSCCTL2:
+            RSTCTL1->PRSTCTL2_CLR = bitMask;
+            while (bitMask == (RSTCTL1->PRSTCTL2 & bitMask))
+            {
+            }
+            break;
+        default:
+            /* Added comments to prevent the violation of MISRA C-2012 rule. */
+            break;
+    }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_reset.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_reset.h
new file mode 100644
index 0000000000..b0d6455266
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_reset.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2021, 2023-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup reset
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.1.1. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+/*!
+ * @brief Reset control registers index
+ */
+#define RST_CTL0_PSCCTL0 0
+#define RST_CTL0_PSCCTL1 1
+#define RST_CTL0_PSCCTL2 2
+#define RST_CTL1_PSCCTL0 3
+#define RST_CTL1_PSCCTL1 4
+#define RST_CTL1_PSCCTL2 5
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in RSTCLTx registers
+ */
+typedef enum _RSTCTL_RSTn
+{
+    kPOWERQUAD_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 8U,      /**< POWERQUAD reset control */
+    kPKC_RST_SHIFT_RSTn       = (RST_CTL0_PSCCTL0 << 8) | 9U,      /**< PKC reset control */
+    kELS_RST_SHIFT_RSTn       = (RST_CTL0_PSCCTL0 << 8) | 10U,     /**< ELS reset control */
+    kPUF_RST_SHIFT_RSTn       = (RST_CTL0_PSCCTL0 << 8) | 11U,     /**< Physical unclonable function reset control */
+    kFLEXSPI_RST_SHIFT_RSTn   = (RST_CTL0_PSCCTL0 << 8) | 16U,     /**< FLEXSPI reset control */
+    kHPU_RST_SHIFT_RSTn       = (RST_CTL0_PSCCTL0 << 8) | 20U,     /**< HPU reset control */
+    kUSB_RST_SHIFT_RSTn       = (RST_CTL0_PSCCTL0 << 8) | 22U,     /**< USB reset control */
+    kSCT_RST_SHIFT_RSTn       = (RST_CTL0_PSCCTL0 << 8) | 24U,     /**< Standard ctimers reset control */
+    kAON_MEM_RST_SHIFT_RSTn   = (RST_CTL0_PSCCTL0 << 8) | 25U,     /**< AON MEM reset control */
+    kGDMA_RST_SHIFT_RSTn      = (RST_CTL0_PSCCTL0 << 8) | 28U,     /**< GDMA reset control */
+    kDMA0_RST_SHIFT_RSTn      = (RST_CTL0_PSCCTL0 << 8) | 29U,     /**< DMA0 reset control */
+    kDMA1_RST_SHIFT_RSTn      = (RST_CTL0_PSCCTL0 << 8) | 30U,     /**< DMA1 reset control */
+    kSDIO_RST_SHIFT_RSTn      = (RST_CTL0_PSCCTL0 << 8) | 31U,     /**< SDIO reset control */
+
+    kELS_APB_RST_SHIFT_RSTn      = (RST_CTL0_PSCCTL1 << 8) | 0U,   /**< ELS_APB reset control */
+    kELS_GDET_REF_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 1U,   /**< ELS_GDET_REF_RST reset control */
+    kSDIO_SLV_SHIFT_RSTn         = (RST_CTL0_PSCCTL1 << 8) | 2U,   /**< SDIO_SLV reset control */
+    kGAU_RST_SHIFT_RSTn          = (RST_CTL0_PSCCTL1 << 8) | 16U,  /**< GAU reset control */
+    kOTP_RST_SHIFT_RSTn          = (RST_CTL0_PSCCTL1 << 8) | 17U,  /**< OTP reset control */
+    kSECURE_GPIO_RST_SHIFT_RSTn  = (RST_CTL0_PSCCTL1 << 8) | 24U,  /**< Security GPIO reset control */
+    kENET_IPG_RST_SHIFT_RSTn     = (RST_CTL0_PSCCTL1 << 8) | 25U,  /**< ENET_IPG reset control */
+    kENET_IPG_S_RST_SHIFT_RSTn   = (RST_CTL0_PSCCTL1 << 8) | 26U,  /**< ENET_IPG_S reset control */
+    kTRNG_RST_SHIFT_RSTn         = (RST_CTL0_PSCCTL1 << 8) | 27U,  /**< TRNG reset control */
+
+    kUTICK_RST_SHIFT_RSTn   = (RST_CTL0_PSCCTL2 << 8) | 0U,        /**< Micro-tick timer reset control */
+    kWWDT_RST_SHIFT_RSTn    = (RST_CTL0_PSCCTL2 << 8) | 1U,        /**< Windowed Watchdog timer reset control */
+    kUSIM_RST_SHIFT_RSTn    = (RST_CTL0_PSCCTL2 << 8) | 2U,        /**< USIM reset control */
+    kFREEMRT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 26U,       /**< FREEMRT reset control */
+    kLCDIC_RST_SHIFT_RSTn   = (RST_CTL0_PSCCTL2 << 8) | 27U,       /**< LCDIC reset control */
+
+    kFC0_RST_SHIFT_RSTn           = (RST_CTL1_PSCCTL0 << 8) | 8U,  /**< Flexcomm Interface 0 reset control */
+    kFC1_RST_SHIFT_RSTn           = (RST_CTL1_PSCCTL0 << 8) | 9U,  /**< Flexcomm Interface 1 reset control */
+    kFC2_RST_SHIFT_RSTn           = (RST_CTL1_PSCCTL0 << 8) | 10U, /**< Flexcomm Interface 2 reset control */
+    kFC3_RST_SHIFT_RSTn           = (RST_CTL1_PSCCTL0 << 8) | 11U, /**< Flexcomm Interface 3 reset control */
+    kFC14_RST_SHIFT_RSTn          = (RST_CTL1_PSCCTL0 << 8) | 22U, /**< Flexcomm Interface 14 reset control */
+    kDMIC_RST_SHIFT_RSTn          = (RST_CTL1_PSCCTL0 << 8) | 24U, /**< Digital microphone interface reset control */
+    kOSEVENT_TIMER_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 27U, /**< Osevent Timer reset control */
+
+    kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U,        /**< HSGPIO 0 reset control */
+    kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U,        /**< HSGPIO 1 reset control */
+    kCRC_RST_SHIFT_RSTn     = (RST_CTL1_PSCCTL1 << 8) | 16U,       /**< CRC reset control */
+    kFREQME_RST_SHIFT_RSTn  = (RST_CTL1_PSCCTL1 << 8) | 31U,       /**< Frequency Measure reset control */
+
+    kCT32B0_RST_SHIFT_RSTn   = (RST_CTL1_PSCCTL2 << 8) | 0U,       /**< CT32B0 reset control */
+    kCT32B1_RST_SHIFT_RSTn   = (RST_CTL1_PSCCTL2 << 8) | 1U,       /**< CT32B1 reset control */
+    kCT32B2_RST_SHIFT_RSTn   = (RST_CTL1_PSCCTL2 << 8) | 2U,       /**< CT32B3 reset control */
+    kCT32B3_RST_SHIFT_RSTn   = (RST_CTL1_PSCCTL2 << 8) | 3U,       /**< CT32B4 reset control */
+    kCT32B4_RST_SHIFT_RSTn   = (RST_CTL1_PSCCTL2 << 8) | 4U,       /**< CT32B4 reset control */
+    kMRT_RST_SHIFT_RSTn      = (RST_CTL1_PSCCTL2 << 8) | 8U,       /**< Multi-rate timer (MRT) reset control */
+    kPINT_RST_SHIFT_RSTn     = (RST_CTL1_PSCCTL2 << 8) | 30U,      /**< GPIO_INT reset control */
+    kINPUTMUX_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 31U,      /**< PMUX reset control */
+} RSTCTL_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define CRC_RSTS            \
+    {                       \
+        kCRC_RST_SHIFT_RSTn \
+    } /* Reset bits for CRC peripheral */
+#define DMA_RSTS_N                                 \
+    {                                              \
+        kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
+    } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS            \
+    {                        \
+        kDMIC_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define FLEXCOMM_RSTS                                                                                            \
+    {                                                                                                            \
+        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC14_RST_SHIFT_RSTn \
+    } /* Reset bits for FLEXCOMM peripheral */
+#define GPIO_RSTS_N                                      \
+    {                                                    \
+        kHSGPIO0_RST_SHIFT_RSTn, kHSGPIO1_RST_SHIFT_RSTn \
+    } /* Reset bits for GPIO peripheral */
+#define MRT_RSTS                                     \
+    {                                                \
+        kMRT_RST_SHIFT_RSTn, kFREEMRT_RST_SHIFT_RSTn \
+    } /* Reset bits for MRT peripheral */
+#define PINT_RSTS            \
+    {                        \
+        kPINT_RST_SHIFT_RSTn \
+    } /* Reset bits for PINT peripheral */
+#define SCT_RSTS            \
+    {                       \
+        kSCT_RST_SHIFT_RSTn \
+    } /* Reset bits for SCT peripheral */
+#define CTIMER_RSTS                                                                                     \
+    {                                                                                                   \
+        kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+            kCT32B4_RST_SHIFT_RSTn                                                                      \
+    } /* Reset bits for TIMER peripheral */
+#define USB_RSTS            \
+    {                       \
+        kUSB_RST_SHIFT_RSTn \
+    } /* Reset bits for USB peripheral */
+#define UTICK_RSTS            \
+    {                         \
+        kUTICK_RST_SHIFT_RSTn \
+    } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for WWDT peripheral */
+#define OSTIMER_RSTS                  \
+    {                                 \
+        kOSEVENT_TIMER_RST_SHIFT_RSTn \
+    } /* Reset bits for OSTIMER peripheral */
+#define POWERQUAD_RSTS            \
+    {                             \
+        kPOWERQUAD_RST_SHIFT_RSTn \
+    } /* Reset bits for Powerquad peripheral */
+#define PUF_RSTS            \
+    {                       \
+        kPUF_RST_SHIFT_RSTn \
+    } /* Reset bits for PUF peripheral */
+#define TRNG_RSTS            \
+    {                        \
+        kTRNG_RST_SHIFT_RSTn \
+    } /* Reset bits for TRNG peripheral */
+#define USIM_RSTS            \
+    {                        \
+        kUSIM_RST_SHIFT_RSTn \
+    } /* Reset bits for USIM peripheral */
+#define ENET_RSTS                                            \
+    {                                                        \
+        kENET_IPG_RST_SHIFT_RSTn, kENET_IPG_S_RST_SHIFT_RSTn \
+    } /* Reset bits for ENET peripheral */
+
+/*!
+ * @brief IP reset handle
+ */
+typedef RSTCTL_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Release peripheral module.
+ *
+ * Release peripheral module.
+ *
+ * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_usart.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_usart.c
new file mode 100644
index 0000000000..e92e29e122
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_usart.c
@@ -0,0 +1,1314 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"
+#endif
+
+/*!
+ * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t`
+ */
+typedef union usart_to_flexcomm
+{
+    flexcomm_usart_irq_handler_t usart_master_handler;
+    flexcomm_irq_handler_t flexcomm_handler;
+} usart_to_flexcomm_t;
+
+enum
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+/*! brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+    uint32_t i;
+
+    for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++)
+    {
+        if (MSDK_REG_SECURE_ADDR((uint32_t)base) == MSDK_REG_SECURE_ADDR(s_usartBaseAddrs[i]))
+        {
+            break;
+        }
+    }
+
+    assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT);
+    return i;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle USART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+    size_t size;
+
+    /* Check arguments */
+    assert(NULL != handle);
+    uint16_t rxRingBufferHead = handle->rxRingBufferHead;
+    uint16_t rxRingBufferTail = handle->rxRingBufferTail;
+
+    if (rxRingBufferTail > rxRingBufferHead)
+    {
+        size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;
+    }
+    else
+    {
+        size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;
+    }
+    return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+    bool full;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer     = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+    /* ring buffer is ready we can start receiving data */
+    base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+
+    if (handle->rxState == (uint8_t)kUSART_RxIdle)
+    {
+        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+    }
+    handle->rxRingBuffer     = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param config Pointer to user-defined configuration structure.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_InvalidArgument USART base address is not valid
+ * retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+    int result;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to USART mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (config->enableTx)
+    {
+        /* empty and enable txFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+    }
+
+    /* empty and enable rxFIFO */
+    if (config->enableRx)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+    }
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+    USART_SetRxTimeoutConfig(base, &(config->rxTimeout));
+#endif
+    /* setup configuration and enable USART */
+    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |
+                USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |
+                USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) |
+                USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK;
+
+    /* Setup baudrate */
+    if (config->enableMode32k)
+    {
+        if ((9600U % config->baudRate_Bps) == 0U)
+        {
+            base->BRG = 9600U / config->baudRate_Bps - 1U;
+        }
+        else
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+    }
+    else
+    {
+        result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+        if (kStatus_Success != result)
+        {
+            return result;
+        }
+    }
+    /* Setting continuous Clock configuration. used for synchronous mode. */
+    USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+
+    /* Don't wait for TX idle when peripheral is disabled. */
+    if ((base->CFG & (USART_CFG_ENABLE_MASK)) != 0U)
+    {
+#if UART_RETRY_TIMES
+        uint32_t waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U))
+#else
+        while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+#endif
+        {
+        }
+    }
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+                         USART_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+    base->FIFORXTIMEOUTCFG = 0U;
+#endif
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+    /* Check arguments */
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    /* Set always all members ! */
+    config->baudRate_Bps              = 115200U;
+    config->parityMode                = kUSART_ParityDisabled;
+    config->stopBitCount              = kUSART_OneStopBit;
+    config->bitCountPerChar           = kUSART_8BitsPerChar;
+    config->loopback                  = false;
+    config->enableRx                  = false;
+    config->enableTx                  = false;
+    config->enableMode32k             = false;
+    config->txWatermark               = kUSART_TxFifo0;
+    config->rxWatermark               = kUSART_RxFifo1;
+    config->syncMode                  = kUSART_SyncModeDisabled;
+    config->enableContinuousSCLK      = false;
+    config->clockPolarity             = kUSART_RxSampleOnFallingEdge;
+    config->enableHardwareFlowControl = false;
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+    config->rxTimeout.enable                = false;
+    config->rxTimeout.resetCounterOnEmpty   = true;
+    config->rxTimeout.resetCounterOnReceive = true;
+    config->rxTimeout.counter               = 0U;
+    config->rxTimeout.prescaler             = 0U;
+#endif
+}
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+/*!
+ * brief Calculate the USART instance RX timeout prescaler and counter.
+ *
+ * This function for calculate the USART RXFIFO timeout config. This function is used to calculate
+ * suitable prescaler and counter for target_us.
+ * Example below shows how to use this API to configure USART.
+ * code
+ *   usart_config_t config;
+ *   config.rxWatermark                     = kUSART_RxFifo2;
+ *   config.rxTimeout.enable                = true;
+ *   config.rxTimeout.resetCounterOnEmpty   = true;
+ *   config.rxTimeout.resetCounterOnReceive = true;
+ *   USART_CalcTimeoutConfig(200, &config.rxTimeout.prescaler, &config.rxTimeout.counter,
+ *                                    CLOCK_GetFreq(kCLOCK_BusClk));
+ * endcode
+ * param target_us  Time for rx timeout unit us.
+ * param rxTimeoutPrescaler The prescaler to be setted after function.
+ * param rxTimeoutcounter The counter to be setted after function.
+ * param srcClock_Hz The clockSrc for rx timeout.
+ */
+void USART_CalcTimeoutConfig(uint32_t target_us,
+                             uint8_t *rxTimeoutPrescaler,
+                             uint32_t *rxTimeoutcounter,
+                             uint32_t srcClock_Hz)
+{
+    uint32_t counter   = 0U;
+    uint32_t perscalar = 0U, calculate_us = 0U, us_diff = 0U, min_diff = 0xffffffffUL;
+    /* find the suitable value */
+    for (perscalar = 0U; perscalar < 256U; perscalar++)
+    {
+        counter      =  target_us * (srcClock_Hz / 1000000UL) / (16U * (perscalar + 1U));
+        calculate_us = 16U * (perscalar + 1U) * counter / (srcClock_Hz / 1000000UL);
+        us_diff      = (calculate_us > target_us) ? (calculate_us - target_us) : (target_us - calculate_us);
+        if (us_diff == 0U)
+        {
+            *rxTimeoutPrescaler = (uint8_t)perscalar;
+            *rxTimeoutcounter   = counter;
+            break;
+        }
+        else
+        {
+            if (min_diff > us_diff)
+            {
+                min_diff            = us_diff;
+                *rxTimeoutPrescaler = (uint8_t)perscalar;
+                *rxTimeoutcounter   = counter;
+            }
+        }
+    }
+}
+/*!
+ * brief Sets the USART instance RX timeout config.
+ *
+ * This function configures the USART RXFIFO timeout config. This function is used to config
+ * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init.
+ *
+ * param base USART peripheral base address.
+ * param config pointer to receive timeout configuration structure.
+ */
+void USART_SetRxTimeoutConfig(USART_Type *base, const usart_rx_timeout_config *config)
+{
+    base->FIFORXTIMEOUTCFG = 0U;
+    base->FIFORXTIMEOUTCFG = USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW((config->resetCounterOnReceive) ? 0U : 1U) |
+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE((config->resetCounterOnEmpty) ? 0U : 1U) |
+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(config->enable) |
+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(config->counter) |
+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(config->prescaler);
+}
+#endif
+
+/*!
+ * brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param baudrate_Bps USART baudrate to be set.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+    uint32_t osrval, brgval, diff, baudrate, allowed_error;
+
+    /* check arguments */
+    assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)));
+    if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If synchronous master mode is enabled, only configure the BRG value. */
+    if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U)
+    {
+        if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U)
+        {
+            brgval    = srcClock_Hz / baudrate_Bps;
+            base->BRG = brgval - 1U;
+        }
+    }
+    else
+    {
+        /* Actual baud rate must be within 3% of desired baud rate based on the calculated OSR and BRG value */
+        allowed_error = ((baudrate_Bps / 100U) * 3U);
+
+        for (osrval = best_osrval; osrval >= 4U; osrval--)
+        {
+            /* 
+             * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+             * potentially cause more noise errors or incorrect data.
+             * Break if the best baudrate's diff is in the allowed error range and the osrval is below 8,
+             * only use lower osrval if the baudrate cannot be obtained with an osrval of 8 or above. */
+            if ((osrval <= 8U) && (best_diff <= allowed_error))
+            {
+                break;
+            }
+
+            brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;
+            if (brgval > 0xFFFFU)
+            {
+                continue;
+            }
+            baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));
+            diff     = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
+            if (diff < best_diff)
+            {
+                best_diff   = diff;
+                best_osrval = osrval;
+                best_brgval = brgval;
+            }
+        }
+
+        /* Check to see if actual baud rate is within 3% of desired baud rate
+         * based on the best calculated OSR and BRG value */
+        baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U));
+        diff     = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
+        if (diff > allowed_error)
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+
+        /* value over range */
+        if (best_brgval > 0xFFFFU)
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+
+        base->OSR = best_osrval;
+        base->BRG = best_brgval;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source.
+ *
+ * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator
+ * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting
+ * SYSCON_RTCOSCCTRL_EN bit to 1.
+ * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that
+ * 9600 can evenly divide, eg: 4800, 3200.
+ *
+ * param base USART peripheral base address.
+ * param baudRate_Bps USART baudrate to be set..
+ * param enableMode32k true is 32k mode, false is normal mode.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz)
+{
+    status_t result = kStatus_Success;
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+    if (enableMode32k)
+    {
+        base->CFG |= USART_CFG_MODE32K_MASK;
+        if ((9600U % baudRate_Bps) == 0U)
+        {
+            base->BRG = 9600U / baudRate_Bps - 1U;
+        }
+        else
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+    }
+    else
+    {
+        base->CFG &= ~(USART_CFG_MODE32K_MASK);
+        result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz);
+        if (kStatus_Success != result)
+        {
+            return result;
+        }
+    }
+    base->CFG |= USART_CFG_ENABLE_MASK;
+    return result;
+}
+
+/*!
+ * brief Enable 9-bit data mode for USART.
+ *
+ * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * param base USART peripheral base address.
+ * param enable true to enable, false to disable.
+ */
+void USART_Enable9bitMode(USART_Type *base, bool enable)
+{
+    assert(base != NULL);
+
+    uint32_t temp = 0U;
+
+    if (enable)
+    {
+        /* Set USART 9-bit mode, disable parity. */
+        temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK);
+        temp |= (uint32_t)USART_CFG_DATALEN(0x2U);
+        base->CFG = temp;
+    }
+    else
+    {
+        /* Set USART to 8-bit mode. */
+        base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK);
+        base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U);
+    }
+}
+
+/*!
+ * brief Transmit an address frame in 9-bit data mode.
+ *
+ * param base USART peripheral base address.
+ * param address USART slave address.
+ */
+void USART_SendAddress(USART_Type *base, uint8_t address)
+{
+    assert(base != NULL);
+    base->FIFOWR = ((uint32_t)address | 0x100UL);
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_InvalidArgument Invalid argument.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check whether txFIFO is enabled */
+    if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+    {
+        return kStatus_InvalidArgument;
+    }
+    for (; length > 0U; length--)
+    {
+        /* Loop until txFIFO get some space for new data */
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U))
+#else
+        while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_USART_Timeout;
+        }
+#endif
+        base->FIFOWR = *data;
+        data++;
+    }
+    /* Wait to finish transfer */
+#if UART_RETRY_TIMES
+    waitTimes = UART_RETRY_TIMES;
+    while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U))
+#else
+    while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+#endif
+    {
+    }
+#if UART_RETRY_TIMES
+    if (0U == waitTimes)
+    {
+        return kStatus_USART_Timeout;
+    }
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+    uint32_t statusFlag;
+    status_t status = kStatus_Success;
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check whether rxFIFO is enabled */
+    if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U)
+    {
+        return kStatus_Fail;
+    }
+    for (; length > 0U; length--)
+    {
+        /* loop until rxFIFO have some data to read */
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U))
+#else
+        while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            status = kStatus_USART_Timeout;
+            break;
+        }
+#endif
+        /* check rxFIFO statusFlag */
+        if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+        {
+            base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+            base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+            status = kStatus_USART_RxError;
+            break;
+        }
+        /* check receive statusFlag */
+        statusFlag = base->STAT;
+        /* Clear all status flags */
+        base->STAT |= statusFlag;
+        if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U)
+        {
+            status = kStatus_USART_ParityError;
+        }
+        if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U)
+        {
+            status = kStatus_USART_FramingError;
+        }
+        if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U)
+        {
+            status = kStatus_USART_NoiseError;
+        }
+
+        if (kStatus_Success == status)
+        {
+            *data = (uint8_t)base->FIFORD;
+            data++;
+        }
+        else
+        {
+            break;
+        }
+    }
+    return status;
+}
+
+/*!
+ * brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData)
+{
+    /* Check 'base' */
+    assert(!((NULL == base) || (NULL == handle)));
+
+    uint32_t instance = 0;
+    usart_to_flexcomm_t handler;
+    handler.usart_master_handler = USART_TransferHandleIRQ;
+
+    if ((NULL == base) || (NULL == handle))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    (void)memset(handle, 0, sizeof(*handle));
+    /* Set the TX/RX state. */
+    handle->rxState = (uint8_t)kUSART_RxIdle;
+    handle->txState = (uint8_t)kUSART_TxIdle;
+    /* Set the callback and user data. */
+    handle->callback    = callback;
+    handle->userData    = userData;
+    handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base);
+    handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+    FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);
+
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(s_usartIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure. See #usart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0U == xfer->dataSize) || (NULL == xfer->txData)));
+    if ((0U == xfer->dataSize) || (NULL == xfer->txData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    uint32_t globalMask = DisableGlobalIRQ();
+
+    /* Return error if current TX busy. */
+    if ((uint8_t)kUSART_TxBusy == handle->txState)
+    {
+        EnableGlobalIRQ(globalMask);
+        return kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txState       = (uint8_t)kUSART_TxBusy;
+        uint32_t usartMask = USART_GetEnabledInterrupts(base);
+        USART_DisableInterrupts(base, usartMask);
+        EnableGlobalIRQ(globalMask);
+
+        handle->txData        = xfer->txData;
+        handle->txDataSize    = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        USART_EnableInterrupts(base, usartMask | (uint32_t)kUSART_TxLevelInterruptEnable);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupts */
+    USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable);
+    /* Empty txFIFO */
+    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+    handle->txDataSize = 0U;
+    handle->txState    = (uint8_t)kUSART_TxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by interrupt method.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if ((uint8_t)kUSART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize -
+             ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure, see #usart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes)
+{
+    uint32_t i;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData)));
+    if ((0U == xfer->dataSize) || (NULL == xfer->rxData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Enable address detect when address match is enabled. */
+    if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U)
+    {
+        base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK;
+    }
+
+    uint32_t globalMask = DisableGlobalIRQ();
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+    if ((uint8_t)kUSART_RxBusy == handle->rxState)
+    {
+        EnableGlobalIRQ(globalMask);
+        return kStatus_USART_RxBusy;
+    }
+    else
+    {
+        handle->rxState       = (uint8_t)kUSART_RxBusy;
+        uint32_t usartMask = USART_GetEnabledInterrupts(base);
+        USART_DisableInterrupts(base, usartMask);
+        EnableGlobalIRQ(globalMask);
+
+        bytesToReceive       = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer != NULL)
+        {
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+            if (bytesToCopy != 0U)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+                bytesToReceive -= bytesToCopy;
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive != 0U)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData        = xfer->rxData + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
+                handle->rxDataSizeAll = xfer->dataSize;
+            }
+            else
+            {
+                handle->rxState = (uint8_t)kUSART_RxIdle;
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData        = xfer->rxData + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+
+            /* Enable RX interrupt. */
+            base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK;
+        }
+
+        /* Re-enable USART IRQ. */
+        USART_EnableInterrupts(base, usartMask);
+
+        /* Return the how many bytes have read. */
+        if (receivedBytes != NULL)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+
+        /* When using ring buffer and we received everything, call user callback. */
+        if (handle->rxRingBuffer != NULL && bytesToReceive == 0U)
+        {
+            if (handle->callback != NULL)
+            {
+                handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* Disable interrupts */
+        USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable);
+        /* Empty rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState    = (uint8_t)kUSART_RxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if ((uint8_t)kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert((NULL != base) && (NULL != handle));
+
+    bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+    bool sendEnabled    = (handle->txDataSize != 0U);
+    uint8_t rxdata;
+    size_t tmpsize;
+
+    /* If RX overrun. */
+    if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+    {
+        /* Clear rx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+        }
+    }
+    /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */
+    if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U)
+    {
+        /* Clear tx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_TxError, handle->userData);
+        }
+    }
+    /* If noise error. */
+    if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U)
+    {
+        /* Clear rx error state. */
+        base->STAT |= USART_STAT_RXNOISEINT_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData);
+        }
+    }
+    /* If framing error. */
+    if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U)
+    {
+        /* Clear rx error state. */
+        base->STAT |= USART_STAT_FRAMERRINT_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_FramingError, handle->userData);
+        }
+    }
+    /* If parity error. */
+    if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U)
+    {
+        /* Clear rx error state. */
+        base->STAT |= USART_STAT_PARITYERRINT_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_ParityError, handle->userData);
+        }
+    }
+    while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||
+           (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))
+    {
+        /* Receive data */
+        if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))
+        {
+            /* Clear address detect when RXFIFO has data. */
+            base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK;
+            /* Receive to app bufffer if app buffer is present */
+            if (handle->rxDataSize != 0U)
+            {
+                rxdata          = (uint8_t)base->FIFORD;
+                *handle->rxData = rxdata;
+                handle->rxDataSize--;
+                handle->rxData++;
+                receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+                if (0U == handle->rxDataSize)
+                {
+                    if (NULL == handle->rxRingBuffer)
+                    {
+                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+                    }
+                    handle->rxState = (uint8_t)kUSART_RxIdle;
+                    if (handle->callback != NULL)
+                    {
+                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                    }
+                }
+            }
+            /* Otherwise receive to ring buffer if ring buffer is present */
+            else
+            {
+                if (handle->rxRingBuffer != NULL)
+                {
+                    /* If RX ring buffer is full, trigger callback to notify over run. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        if (handle->callback != NULL)
+                        {
+                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+                        }
+                    }
+                    /* If ring buffer is still full after callback function, the oldest data is overridden. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        /* Increase handle->rxRingBufferTail to make room for new data. */
+                        if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                        {
+                            handle->rxRingBufferTail = 0U;
+                        }
+                        else
+                        {
+                            handle->rxRingBufferTail++;
+                        }
+                    }
+                    /* Read data. */
+                    rxdata                                         = (uint8_t)base->FIFORD;
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata;
+                    /* Increase handle->rxRingBufferHead. */
+                    if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferHead = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferHead++;
+                    }
+                }
+            }
+        }
+        /* Send data */
+        if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))
+        {
+            base->FIFOWR = *handle->txData;
+            handle->txDataSize--;
+            handle->txData++;
+            sendEnabled = handle->txDataSize != 0U;
+            if (!sendEnabled)
+            {
+                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+
+                base->INTENSET = USART_INTENSET_TXIDLEEN_MASK;
+            }
+        }
+    }
+
+    /* Tx idle and the interrupt is enabled. */
+    if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)))
+    {
+        /* Set txState to idle only when all data has been sent out to bus. */
+        handle->txState = (uint8_t)kUSART_TxIdle;
+        /* Disable tx idle interrupt */
+        base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK;
+
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+        }
+    }
+
+    /* ring buffer is not used */
+    if (NULL == handle->rxRingBuffer)
+    {
+        tmpsize = handle->rxDataSize;
+
+        /* restore if rx transfer ends and rxLevel is different from default value */
+        if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+        }
+        /* decrease level if rx transfer is bellow */
+        if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U)))
+        {
+            base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U));
+        }
+    }
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_usart.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_usart.h
new file mode 100644
index 0000000000..c759a83529
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/drivers/fsl_usart.h
@@ -0,0 +1,971 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_USART_H_
+#define FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief USART driver version. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 8, 4))
+/*! @} */
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Retry times for waiting flag.
+ *
+ * Defining to zero means to keep waiting for the flag until it is assert/deassert in blocking transfer,
+ * otherwise the program will wait until the UART_RETRY_TIMES counts down to 0,
+ * if the flag still remains unchanged then program will return kStatus_USART_Timeout.
+ * It is not advised to use this macro in formal application to prevent any hardware error
+ * because the actual wait period is affected by the compiler and optimization.
+ */
+#ifndef UART_RETRY_TIMES
+#define UART_RETRY_TIMES 0U
+#endif
+
+/*! @brief Error codes for the USART driver. */
+enum
+{
+    kStatus_USART_TxBusy              = MAKE_STATUS(kStatusGroup_LPC_USART, 0),  /*!< Transmitter is busy. */
+    kStatus_USART_RxBusy              = MAKE_STATUS(kStatusGroup_LPC_USART, 1),  /*!< Receiver is busy. */
+    kStatus_USART_TxIdle              = MAKE_STATUS(kStatusGroup_LPC_USART, 2),  /*!< USART transmitter is idle. */
+    kStatus_USART_RxIdle              = MAKE_STATUS(kStatusGroup_LPC_USART, 3),  /*!< USART receiver is idle. */
+    kStatus_USART_TxError             = MAKE_STATUS(kStatusGroup_LPC_USART, 7),  /*!< Error happens on txFIFO. */
+    kStatus_USART_RxError             = MAKE_STATUS(kStatusGroup_LPC_USART, 9),  /*!< Error happens on rxFIFO. */
+    kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8),  /*!< Error happens on rx ring buffer */
+    kStatus_USART_NoiseError          = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */
+    kStatus_USART_FramingError        = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */
+    kStatus_USART_ParityError         = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */
+    kStatus_USART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+#if UART_RETRY_TIMES
+    kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */
+#endif
+};
+
+/*! @brief USART synchronous mode. */
+typedef enum _usart_sync_mode
+{
+    kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode.       */
+    kUSART_SyncModeSlave    = 0x2U, /*!< Synchronous slave mode.  */
+    kUSART_SyncModeMaster   = 0x3U, /*!< Synchronous master mode. */
+} usart_sync_mode_t;
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode
+{
+    kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kUSART_ParityEven     = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kUSART_ParityOdd      = 0x3U, /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count
+{
+    kUSART_OneStopBit = 0U, /*!< One stop bit */
+    kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len
+{
+    kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+    kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief USART clock polarity configuration, used in sync mode.*/
+typedef enum _usart_clock_polarity
+{
+    kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */
+    kUSART_RxSampleOnRisingEdge  = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */
+} usart_clock_polarity_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark
+{
+    kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+    kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+    kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+    kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+    kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+    kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+    kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+    kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark
+{
+    kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+    kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+    kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+    kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+    kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+    kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+    kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+    kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+    kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+    kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+    kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+    kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+    kUSART_TxIdleInterruptEnable  = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */
+    kUSART_CtsChangeInterruptEnable =
+        (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */
+    kUSART_RxBreakChangeInterruptEnable =
+        (USART_INTENSET_DELTARXBRKEN_MASK),                              /*!< Break condition asserted or deasserted. */
+    kUSART_RxStartInterruptEnable       = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */
+    kUSART_FramingErrorInterruptEnable  = (USART_INTENSET_FRAMERREN_MASK),   /*!< Framing error detected. */
+    kUSART_ParityErrorInterruptEnable   = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */
+    kUSART_NoiseErrorInterruptEnable    = (USART_INTENSET_RXNOISEEN_MASK),   /*!< Noise error detected. */
+    kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK),     /*!< Auto baudrate error detected. */
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+    kUSART_RxTimeoutInterruptEnable = (USART_FIFOINTENSET_RXTIMEOUT_MASK), /*!< Receive timeout detected. */
+#endif
+    kUSART_AllInterruptEnables =
+        kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable |
+        kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable |
+        kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable |
+        kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable |
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+        kUSART_RxTimeoutInterruptEnable |
+#endif
+        kUSART_AutoBaudErrorInterruptEnable,
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+    kUSART_TxError            = (USART_FIFOSTAT_TXERR_MASK),       /*!< TEERR bit, sets if TX buffer is error */
+    kUSART_RxError            = (USART_FIFOSTAT_RXERR_MASK),       /*!< RXERR bit, sets if RX buffer is error */
+    kUSART_TxFifoEmptyFlag    = (USART_FIFOSTAT_TXEMPTY_MASK),     /*!< TXEMPTY bit, sets if TX buffer is empty */
+    kUSART_TxFifoNotFullFlag  = (USART_FIFOSTAT_TXNOTFULL_MASK),   /*!< TXNOTFULL bit, sets if TX buffer is not full */
+    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK),  /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
+    kUSART_RxFifoFullFlag     = (USART_FIFOSTAT_RXFULL_MASK),      /*!< RXFULL bit, sets if RX buffer is full */
+    kUSART_RxIdleFlag         = (USART_STAT_RXIDLE_MASK << 16U),   /*!< Receiver idle. */
+    kUSART_TxIdleFlag         = (USART_STAT_TXIDLE_MASK << 16U),   /*!< Transmitter idle. */
+    kUSART_CtsAssertFlag      = (USART_STAT_CTS_MASK << 16U),      /*!< CTS signal high. */
+    kUSART_CtsChangeFlag      = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */
+    kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */
+    kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in
+                                                                    the state of receiver break detection. */
+    kUSART_RxStartFlag       = (USART_STAT_START_MASK),          /*!< Rx start bit detected interrupt flag. */
+    kUSART_FramingErrorFlag  = (USART_STAT_FRAMERRINT_MASK),     /*!< Framing error interrupt flag. */
+    kUSART_ParityErrorFlag   = (USART_STAT_PARITYERRINT_MASK),   /*!< parity error interrupt flag. */
+    kUSART_NoiseErrorFlag    = (USART_STAT_RXNOISEINT_MASK),     /*!< Noise error interrupt flag. */
+    kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate
+                                                           counter timeout before the end of start bit. */
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+    kUSART_RxTimeoutFlag = (USART_FIFOSTAT_RXTIMEOUT_MASK), /*!< RXTIMEOUT bit, sets if RX FIFO Timeout. */
+#endif
+    kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag |
+                           kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag |
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+                           kUSART_RxTimeoutFlag |
+#endif
+                           kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag,
+};
+
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+/*! @brief USART receive timeout configuration structure. */
+typedef struct _usart_rx_timeout_config
+{
+    bool enable;                /*!< Enable RX timeout */
+    bool resetCounterOnEmpty;   /*!< Enable RX timeout counter reset when RX FIFO becames empty. */
+    bool resetCounterOnReceive; /*!< Enable RX timeout counter reset when RX FIFO receives data from the transmitter
+                                   side. */
+    uint32_t counter;           /*!< RX timeout counter*/
+    uint8_t prescaler;          /*!< RX timeout prescaler*/
+} usart_rx_timeout_config;
+#endif
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+    uint32_t baudRate_Bps;                /*!< USART baud rate  */
+    usart_parity_mode_t parityMode;       /*!< Parity mode, disabled (default), even, odd */
+    usart_stop_bit_count_t stopBitCount;  /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    usart_data_len_t bitCountPerChar;     /*!< Data length - 7 bit, 8 bit  */
+    bool loopback;                        /*!< Enable peripheral loopback */
+    bool enableRx;                        /*!< Enable RX */
+    bool enableTx;                        /*!< Enable TX */
+    bool enableContinuousSCLK;            /*!< USART continuous Clock generation enable in synchronous master mode. */
+    bool enableMode32k;                   /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */
+    bool enableHardwareFlowControl;       /*!< Enable hardware control RTS/CTS */
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+    usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */
+    usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+    usart_rx_timeout_config rxTimeout; /*!< rx timeout configuration */
+#endif
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+    /*
+     * Use separate TX and RX data pointer, because TX data is const data.
+     * The member data is kept for backward compatibility.
+     */
+    union
+    {
+        uint8_t *data;         /*!< The buffer of data to be transfer.*/
+        uint8_t *rxData;       /*!< The buffer to receive data. */
+        const uint8_t *txData; /*!< The buffer of data to be sent. */
+    };
+    size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+    const uint8_t *volatile txData; /*!< Address of remaining data to send. */
+    volatile size_t txDataSize;     /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;           /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;       /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize;     /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;           /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    usart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                     /*!< USART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+
+    uint8_t txWatermark; /*!< txFIFO watermark */
+    uint8_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*! @brief Typedef for usart interrupt handler. */
+typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*! @brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG
+/*!
+ * @brief Calculate the USART instance RX timeout prescaler and counter.
+ *
+ * This function for calculate the USART RXFIFO timeout config. This function is used to calculate
+ * suitable prescaler and counter for target_us.
+ * @code
+ *   usart_config_t config;
+ *   config.rxWatermark                     = kUSART_RxFifo2;
+ *   config.rxTimeout.enable                = true;
+ *   config.rxTimeout.resetCounterOnEmpty   = true;
+ *   config.rxTimeout.resetCounterOnReceive = true;
+ *   USART_CalcTimeoutConfig(200U, &config.rxTimeout.prescaler, &config.rxTimeout.counter,
+ *                                    CLOCK_GetFreq(kCLOCK_BusClk));
+ * @endcode
+ * @param target_us  Time for rx timeout unit us.
+ * @param rxTimeoutPrescaler The prescaler to be setted after function.
+ * @param rxTimeoutcounter The counter to be setted after function.
+ * @param srcClock_Hz The clockSrc for rx timeout.
+ */
+void USART_CalcTimeoutConfig(uint32_t target_us,
+                             uint8_t *rxTimeoutPrescaler,
+                             uint32_t *rxTimeoutcounter,
+                             uint32_t srcClock_Hz);
+/*!
+ * @brief Sets the USART instance RX timeout config.
+ *
+ * This function configures the USART RXFIFO timeout config. This function is used to config
+ * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init.
+ *
+ * @param base USART peripheral base address.
+ * @param config pointer to receive timeout configuration structure.
+ */
+void USART_SetRxTimeoutConfig(USART_Type *base, const usart_rx_timeout_config *config);
+#endif
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source
+ *
+ * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator
+ * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting
+ * SYSCON_RTCOSCCTRL_EN bit to 1.
+ * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that
+ * 9600 can evenly divide, eg: 4800, 3200.
+ *
+ * @param base USART peripheral base address.
+ * @param baudRate_Bps USART baudrate to be set..
+ * @param enableMode32k true is 32k mode, false is normal mode.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Enable 9-bit data mode for USART.
+ *
+ * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * @param base USART peripheral base address.
+ * @param enable true to enable, false to disable.
+ */
+void USART_Enable9bitMode(USART_Type *base, bool enable);
+
+/*!
+ * @brief Set the USART slave address.
+ *
+ * This function configures the address for USART module that works as slave in 9-bit data mode. When the address
+ * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is
+ * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This
+ * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded.
+ * To un-address a slave, just send an address frame with unmatched address.
+ *
+ * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the
+ * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.
+ *
+ * @param base USART peripheral base address.
+ * @param address USART slave address.
+ */
+static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address)
+{
+    /* Configure match address. */
+    base->ADDR = (uint32_t)address;
+}
+
+/*!
+ * @brief Enable the USART match address feature.
+ *
+ * @param base USART peripheral base address.
+ * @param match true to enable match address, false to disable.
+ */
+static inline void USART_EnableMatchAddress(USART_Type *base, bool match)
+{
+    /* Configure match address enable bit. */
+    if (match)
+    {
+        base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK;
+        base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK;
+    }
+    else
+    {
+        base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK;
+        base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+    return (base->FIFOSTAT & 0xFF0000FFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL);
+}
+
+/*!
+ * @brief Clear USART status flags.
+ *
+ * This function clear supported USART status flags
+ * Flags that can be cleared or set are:
+ *      kUSART_TxError
+ *      kUSART_RxError
+ * For example:
+ * @code
+ *     USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask status flags to be cleared.
+ */
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
+{
+    mask &= (uint32_t)kUSART_AllClearFlags;
+    /* Clear the clearable status in STAT register. */
+    base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U);
+    /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
+    base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+    mask &= (uint32_t)kUSART_AllInterruptEnables;
+    base->INTENSET     = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U);
+    base->FIFOINTENSET = mask & 0xF00000FUL;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+    mask &= (uint32_t)kUSART_AllInterruptEnables;
+    base->INTENCLR     = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U);
+    base->FIFOINTENCLR = mask & 0xFUL;
+}
+
+/*!
+ * @brief Returns enabled USART interrupts.
+ *
+ * This function returns the enabled USART interrupts.
+ *
+ * @param base USART peripheral base address.
+ */
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)
+{
+    return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL);
+}
+
+/*!
+ * @brief Enable DMA for Tx
+ */
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+    }
+}
+
+/*!
+ * @brief Enable DMA for Rx
+ */
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+    }
+}
+
+/*!
+ * @brief Enable CTS.
+ * This function will determine whether CTS is used for flow control.
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable CTS or not, true for enable and false for disable.
+ */
+static inline void USART_EnableCTS(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= USART_CFG_CTSEN_MASK;
+    }
+    else
+    {
+        base->CFG &= ~USART_CFG_CTSEN_MASK;
+    }
+}
+
+/*!
+ * @brief Continuous Clock generation.
+ * By default, SCLK is only output while data is being transmitted in synchronous mode.
+ * Enable this funciton, SCLK will run continuously in synchronous mode, allowing
+ * characters to be received on Un_RxD independently from transmission on Un_TXD).
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable Continuous Clock generation mode or not, true for enable and false for disable.
+ */
+static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= USART_CTL_CC_MASK;
+    }
+    else
+    {
+        base->CTL &= ~USART_CTL_CC_MASK;
+    }
+}
+
+/*!
+ * @brief Enable Continuous Clock generation bit auto clear.
+ * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete
+ * character has been received. This bit is cleared at the same time.
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable auto clear or not, true for enable and false for disable.
+ */
+static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= USART_CTL_CLRCCONRX_MASK;
+    }
+    else
+    {
+        base->CTL &= ~USART_CTL_CLRCCONRX_MASK;
+    }
+}
+
+/*!
+ * @brief Sets the rx FIFO watermark.
+ *
+ * @param base USART peripheral base address.
+ * @param water Rx FIFO watermark.
+ */
+static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water)
+{
+    assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT));
+    base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water);
+}
+
+/*!
+ * @brief Sets the tx FIFO watermark.
+ *
+ * @param base USART peripheral base address.
+ * @param water Tx FIFO watermark.
+ */
+static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water)
+{
+    assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT));
+    base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water);
+}
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+    base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+    return (uint8_t)base->FIFORD;
+}
+
+/*!
+ * @brief Gets the rx FIFO data count.
+ *
+ * @param base USART peripheral base address.
+ * @return rx FIFO data count.
+ */
+static inline uint8_t USART_GetRxFifoCount(USART_Type *base)
+{
+    return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT);
+}
+
+/*!
+ * @brief Gets the tx FIFO data count.
+ *
+ * @param base USART peripheral base address.
+ * @return tx FIFO data count.
+ */
+static inline uint8_t USART_GetTxFifoCount(USART_Type *base)
+{
+    return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT);
+}
+
+/*!
+ * @brief Transmit an address frame in 9-bit data mode.
+ *
+ * @param base USART peripheral base address.
+ * @param address USART slave address.
+ */
+void USART_SendAddress(USART_Type *base, uint8_t address);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See  #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+                                   usart_handle_t *handle,
+                                   uint8_t *ringBuffer,
+                                   size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle USART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_USART_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/frdmrw612/mflash_drv.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/frdmrw612/mflash_drv.c
new file mode 100644
index 0000000000..967753d62a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/frdmrw612/mflash_drv.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright 2017-2022, 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include "mflash_drv.h"
+#include "fsl_flexspi.h"
+#include "fsl_cache.h"
+
+#define FLASH_PORT kFLEXSPI_PortA1
+
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD     0
+#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG     1
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE        2
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR        3
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD   4
+#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP          5
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
+#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL        7
+#define NOR_CMD_LUT_SEQ_IDX_READID             8
+#define NOR_CMD_LUT_SEQ_IDX_WRITE              9
+#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI           10
+#define NOR_CMD_LUT_SEQ_IDX_EXITQPI            11
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG      12
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST          13
+
+#define CUSTOM_LUT_LENGTH        60
+#define FLASH_QUAD_ENABLE        0x2
+#define FLASH_BUSY_STATUS_POL    1
+#define FLASH_BUSY_STATUS_OFFSET 0
+
+static flexspi_device_config_t deviceconfig = {
+    .flexspiRootClk       = 130000000U,
+    .flashSize            = FLASH_SIZE / 1024, /* flash size in KB */
+    .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval           = 2,
+    .CSHoldTime           = 3,
+    .CSSetupTime          = 3,
+    .dataValidTime        = 0,
+    .columnspace          = 0,
+    .enableWordAddress    = 0,
+    .AWRSeqIndex          = NOR_CMD_LUT_SEQ_IDX_WRITE,
+    .AWRSeqNumber         = 1,
+    .ARDSeqIndex          = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
+    .ARDSeqNumber         = 1,
+    .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 0,
+};
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
+    /* Normal read mode -SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x13, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Fast read mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0C, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Fast read quad mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEC, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x20),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_MODE8_SDR, kFLEXSPI_4PAD, 0xF0, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x04),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 2] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+    /* Write Enable */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Erase Sector  */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x21, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
+
+    /* Page Program - single mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x12, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Page Program - quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x34, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read ID */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Enable Quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x31, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x01),
+
+    /*  Dummy write, do nothing when AHB write command is triggered. */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+    /* Read status register */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Erase whole chip */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+};
+
+static status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base)
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    bool busyStatus = (bool)FLASH_BUSY_STATUS_POL;
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port          = FLASH_PORT;
+    flashXfer.cmdType       = kFLEXSPI_Read;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
+    flashXfer.data          = &readValue;
+    flashXfer.dataSize      = 1;
+
+    do
+    {
+        status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        if (busyStatus)
+        {
+            if ((readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) > 0U)
+            {
+                isBusy = true;
+            }
+            else
+            {
+                isBusy = false;
+            }
+        }
+        else
+        {
+            if ((readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) > 0U)
+            {
+                isBusy = false;
+            }
+            else
+            {
+                isBusy = true;
+            }
+        }
+
+    } while (isBusy);
+
+    return status;
+}
+
+static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+
+    /* Write enable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port          = FLASH_PORT;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    return status;
+}
+
+static status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    uint32_t writeValue = FLASH_QUAD_ENABLE;
+
+    /* Write enable */
+    status = flexspi_nor_write_enable(base, 0);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Enable quad mode. */
+    flashXfer.deviceAddress = 0;
+    flashXfer.port          = FLASH_PORT;
+    flashXfer.cmdType       = kFLEXSPI_Write;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
+    flashXfer.data          = &writeValue;
+    flashXfer.dataSize      = 1;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(base);
+
+    return status;
+}
+
+/* Internal - erase single sector */
+static status_t flexspi_nor_flash_sector_erase(FLEXSPI_Type *base, uint32_t address)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* Write enable */
+    flashXfer.deviceAddress = address;
+    flashXfer.port          = FLASH_PORT;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port          = FLASH_PORT;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status                  = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(base);
+
+    return status;
+}
+
+static status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* To make sure external flash be in idle status, added wait for busy before program data for
+        an external flash without RWW(read while write) attribute.*/
+    status = flexspi_nor_wait_bus_busy(base);
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Write enable. */
+    status = flexspi_nor_write_enable(base, dstAddr);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Prepare page program command */
+    flashXfer.deviceAddress = dstAddr;
+    flashXfer.port          = FLASH_PORT;
+    flashXfer.cmdType       = kFLEXSPI_Write;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
+    flashXfer.data          = (uint32_t *)(uintptr_t)src;
+    flashXfer.dataSize      = MFLASH_PAGE_SIZE;
+    status                  = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    /* Do software reset or clear AHB buffer directly. */
+#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) && defined(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) && \
+    defined(FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)
+    base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK;
+    base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK);
+#else
+    FLEXSPI_SoftwareReset(base);
+#endif
+
+    return status;
+}
+
+static status_t flexspi_nor_read_data(FLEXSPI_Type *base, uint32_t startAddress, uint32_t *buffer, uint32_t length)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    uint32_t readAddress = startAddress;
+
+    /* Read page. */
+    flashXfer.deviceAddress = readAddress;
+    flashXfer.port          = FLASH_PORT;
+    flashXfer.cmdType       = kFLEXSPI_Read;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD;
+    flashXfer.data          = buffer;
+    flashXfer.dataSize      = length;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    
+    if(status == kStatus_Success)
+    {
+      status = flexspi_nor_wait_bus_busy(base);
+    }
+
+    return status;
+}
+
+static int32_t mflash_drv_init_internal(void)
+{
+    uint32_t primask = __get_PRIMASK();
+    flexspi_config_t config;
+
+    __asm("cpsid i");
+
+    /*Get FLEXSPI default settings and configure the flexspi. */
+    FLEXSPI_GetDefaultConfig(&config);
+
+    /*Set AHB buffer size for reading data through AHB bus. */
+    config.ahbConfig.enableAHBPrefetch = true;
+    config.rxSampleClock               = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+    config.enableCombination = true;
+#endif
+    config.ahbConfig.enableAHBBufferable = true;
+    config.ahbConfig.enableAHBCachable   = true;
+    FLEXSPI_Init(MFLASH_FLEXSPI, &config);
+
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(MFLASH_FLEXSPI, &deviceconfig, FLASH_PORT);
+
+    /* Update LUT table. */
+    FLEXSPI_UpdateLUT(MFLASH_FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    (void)flexspi_nor_enable_quad_mode(MFLASH_FLEXSPI);
+
+    /* Invalidate cache. */
+    do
+    {
+        CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
+        while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
+        {
+        }
+        CACHE64_CTRL0->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK);
+    } while (false);
+
+    if (primask == 0U)
+    {
+        __asm("cpsie i");
+    }
+
+    return kStatus_Success;
+}
+
+/* API - initialize 'mflash' */
+int32_t mflash_drv_init(void)
+{
+    /* Necessary to have double wrapper call in non_xip memory */
+    return mflash_drv_init_internal();
+}
+
+/* Internal - erase single sector */
+static int32_t mflash_drv_sector_erase_internal(uint32_t sector_addr)
+{
+    status_t status;
+    uint32_t primask = __get_PRIMASK();
+
+    __asm("cpsid i");
+
+    status = flexspi_nor_flash_sector_erase(MFLASH_FLEXSPI, sector_addr);
+
+    DCACHE_InvalidateByRange(MFLASH_BASE_ADDRESS + sector_addr, MFLASH_SECTOR_SIZE);
+
+    if (primask == 0U)
+    {
+        __asm("cpsie i");
+    }
+
+    /* Flush pipeline to allow pending interrupts take place
+     * before starting next loop */
+    __ISB();
+
+    return status;
+}
+
+/* Calling wrapper for 'mflash_drv_sector_erase_internal'.
+ * Erase one sector starting at 'sector_addr' - must be sector aligned.
+ */
+int32_t mflash_drv_sector_erase(uint32_t sector_addr)
+{
+    if (0 == mflash_drv_is_sector_aligned(sector_addr))
+        return kStatus_InvalidArgument;
+
+    return mflash_drv_sector_erase_internal(sector_addr);
+}
+
+/* Internal - write single page */
+static int32_t mflash_drv_page_program_internal(uint32_t page_addr, uint32_t *data)
+{
+    uint32_t primask = __get_PRIMASK();
+
+    __asm("cpsid i");
+
+    status_t status;
+    status = flexspi_nor_flash_page_program(MFLASH_FLEXSPI, page_addr, data);
+
+    /* Do software reset. */
+    // FLEXSPI_SoftwareReset(MFLASH_FLEXSPI);
+
+    DCACHE_InvalidateByRange(MFLASH_BASE_ADDRESS + page_addr, MFLASH_PAGE_SIZE);
+
+    if (primask == 0U)
+    {
+        __asm("cpsie i");
+    }
+
+    /* Flush pipeline to allow pending interrupts take place
+     * before starting next loop */
+    __ISB();
+
+    return status;
+}
+
+/* Internal - read data */
+static int32_t mflash_drv_read_internal(uint32_t addr, uint32_t *buffer, uint32_t len)
+{
+    uint32_t primask = __get_PRIMASK();
+
+    __asm("cpsid i");
+
+    status_t status;
+    status = flexspi_nor_read_data(MFLASH_FLEXSPI, addr, buffer, len);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(MFLASH_FLEXSPI);
+
+    if (primask == 0)
+    {
+        __asm("cpsie i");
+    }
+
+    /* Flush pipeline to allow pending interrupts take place
+     * before starting next loop */
+    __ISB();
+
+    return status;
+}
+
+/* Calling wrapper for 'mflash_drv_page_program_internal'.
+ * Write 'data' to 'page_addr' - must be page aligned.
+ * NOTE: Don't try to store constant data that are located in XIP !!
+ */
+int32_t mflash_drv_page_program(uint32_t page_addr, uint32_t *data)
+{
+    if (0 == mflash_drv_is_page_aligned(page_addr))
+        return kStatus_InvalidArgument;
+
+    return mflash_drv_page_program_internal(page_addr, data);
+}
+
+/* API - Read data */
+int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len)
+{
+    /* Check alignment */
+    if (((uint32_t)buffer % 4) || (len % 4))
+        return kStatus_InvalidArgument;
+
+    return mflash_drv_read_internal(addr, buffer, len);
+}
+
+/* API - Get pointer to FLASH region */
+void *mflash_drv_phys2log(uint32_t addr, uint32_t len)
+{
+    /* FLASH starts at MFLASH_BASE_ADDRESS */
+    return (void *)(addr + MFLASH_BASE_ADDRESS);
+}
+
+/* API - Get pointer to FLASH region */
+uint32_t mflash_drv_log2phys(void *ptr, uint32_t len)
+{
+    if ((uint32_t)ptr < MFLASH_BASE_ADDRESS)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* FLASH starts at MFLASH_BASE_ADDRESS */
+    return ((uint32_t)ptr - MFLASH_BASE_ADDRESS);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/frdmrw612/mflash_drv.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/frdmrw612/mflash_drv.h
new file mode 100644
index 0000000000..61e5866830
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/frdmrw612/mflash_drv.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MFLASH_DRV_H__
+#define __MFLASH_DRV_H__
+
+#include "mflash_common.h"
+
+/* Flash constants */
+#ifndef MFLASH_SECTOR_SIZE
+#define MFLASH_SECTOR_SIZE (4096U)
+#endif
+
+#ifndef MFLASH_PAGE_SIZE
+#define MFLASH_PAGE_SIZE (256U)
+#endif
+
+/* Device specific settings */
+#ifndef MFLASH_FLEXSPI
+#define MFLASH_FLEXSPI FLEXSPI
+#endif
+
+#ifndef MFLASH_BASE_ADDRESS
+#define MFLASH_BASE_ADDRESS (FlexSPI_AMBA_PC_CACHE_BASE)
+#endif
+
+#define FLASH_SIZE 0x04000000U
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_common.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_common.h
new file mode 100644
index 0000000000..7ea84ff5c1
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_common.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MFLASH_COMMON_H__
+#define __MFLASH_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Common definitions
+ ******************************************************************************/
+
+#define MFLASH_INVALID_ADDRESS (UINT32_MAX)
+
+#define mflash_drv_is_page_aligned(x)   (((x) % (MFLASH_PAGE_SIZE)) == 0U)
+#define mflash_drv_is_sector_aligned(x) (((x) % (MFLASH_SECTOR_SIZE)) == 0U)
+
+/*
+ * The addresses of FLASH locations used by APIs below may not correspond with the addresses space, especially when
+ * FLASH remapping is being used. Use mflash_drv_phys2log/log2phys API to obtain actual pointer or physical address.
+ */
+
+/*******************************************************************************
+ * APIs provided by low level driver
+ ******************************************************************************/
+
+/*! @brief Initializes mflash driver */
+int32_t mflash_drv_init(void);
+
+/*! @brief Erases single sector */
+int32_t mflash_drv_sector_erase(uint32_t sector_addr);
+
+/*! @brief Writes single page */
+int32_t mflash_drv_page_program(uint32_t page_addr, uint32_t *data);
+
+/*! @brief Reads data of arbitrary length */
+int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len);
+
+/*! @brief Returns pointer to memory area where the specified region of FLASH is mapped, NULL on failure (could not map
+ * continuous block) */
+void *mflash_drv_phys2log(uint32_t addr, uint32_t len);
+
+/*! @brief Returns address of physical memory where the area accessible by given pointer is actually stored, UINT32_MAX
+ * on failure (could not map as continuous block) */
+uint32_t mflash_drv_log2phys(void *ptr, uint32_t len);
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_file.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_file.c
new file mode 100644
index 0000000000..452727a54a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_file.c
@@ -0,0 +1,719 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#ifdef SDK_OS_FREE_RTOS
+#include "FreeRTOS.h"
+#endif
+
+#include "mflash_file.h"
+#include "mflash_drv.h"
+#include "fsl_common.h"
+
+/* Magic numbers to check for presence of the structures below */
+#define MFLASH_DIR_MAGIC_NO  (0xF17E07ABu)
+#define MFLASH_META_MAGIC_NO (0xABECEDA8u)
+#define MFLASH_FS_VERSION    (0x00010000u)
+#define MFLASH_BLANK_PATTERN (0xFFu)
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+// linker symbols imported as described in https://www.keil.com/support/man/docs/armlink/armlink_pge1362065952432.htm
+extern char Image$$mflash_fs$$Base[];
+#define MFLASH_FS_START ((void *)Image$$mflash_fs$$Base)
+#else
+extern char __MFLASH_FS_START[];
+#define MFLASH_FS_START ((void *)__MFLASH_FS_START)
+#endif
+
+/*
+ * The table header and table record structures have to be aligned
+ * with pages/sectors that are expected to be of 2**n size, hence there is some padding
+ */
+typedef struct
+{
+    uint32_t file_offset;
+    uint32_t alloc_size;
+    uint8_t path[MFLASH_MAX_PATH_LEN];
+} mflash_dir_record_t;
+
+typedef struct
+{
+    uint32_t magic_no;
+    uint32_t version;
+    uint32_t page_size;
+    uint32_t sector_size;
+    uint32_t file_count;
+    uint32_t total_size;
+    uint8_t padding[sizeof(mflash_dir_record_t) - 6 * sizeof(uint32_t)];
+} mflash_fs_header_t;
+
+typedef struct
+{
+    mflash_fs_header_t header;
+    mflash_dir_record_t records[];
+} mflash_fs_t;
+
+/* Metadata prepended to the file itself to identify valid (already written) file and keep actual length of the file */
+typedef struct
+{
+    uint32_t file_size;
+    uint32_t magic_no;
+} mflash_file_meta_t;
+
+/* Pointer to the filesystem */
+static mflash_fs_t *g_mflash_fs = NULL;
+
+/* API - True if mflash is already initialized */
+bool mflash_is_initialized(void)
+{
+    return (g_mflash_fs != NULL);
+}
+
+/* Store path string to directory record structure */
+static bool dir_path_store(mflash_dir_record_t *dr, char *path)
+{
+    assert(dr);
+    assert(path);
+
+    for (int i = 0; i < MFLASH_MAX_PATH_LEN; i++)
+    {
+        dr->path[i] = (uint8_t)(*path);
+
+        /* End of string, exit the loop */
+        if (*path == '\0')
+        {
+            break;
+        }
+
+        path++;
+    }
+
+    /* Check whether the whole given path string was processed */
+    if (*path != '\0')
+    {
+        return false;
+    }
+
+    return true;
+}
+
+/* Match path string against directory record */
+static bool dir_path_match(mflash_dir_record_t *dr, char *path)
+{
+    assert(dr);
+    assert(path);
+
+    for (int i = 0; i < MFLASH_MAX_PATH_LEN; i++)
+    {
+        if (dr->path[i] != (uint8_t)(*path))
+        {
+            return false;
+        }
+
+        /* End of string, there is match */
+        if (*path == '\0')
+        {
+            return true;
+        }
+
+        path++;
+    }
+
+    /* Check whether the whole given path string was processed */
+    if (*path != '\0')
+    {
+        return false;
+    }
+
+    return true;
+}
+
+/* Buffer allocation wrapper */
+static void *mflash_page_buf_get(void)
+{
+    void *page_buf;
+#ifdef SDK_OS_FREE_RTOS
+    page_buf = pvPortMalloc(MFLASH_PAGE_SIZE);
+#else
+    page_buf = malloc(MFLASH_PAGE_SIZE);
+#endif
+    return page_buf;
+}
+
+/* Buffer allocation wrapper */
+static void mflash_page_buf_release(void *page_buf)
+{
+#ifdef SDK_OS_FREE_RTOS
+    vPortFree(page_buf);
+#else
+    free(page_buf);
+#endif
+}
+
+/* Low level abstraction - erase sector of the filesystem */
+static status_t mflash_fs_sector_erase(mflash_fs_t *fs, uint32_t sector_offset)
+{
+    uint32_t phys_addr;
+
+    /* Translate filesystem offset to physical address in FLASH */
+    phys_addr = mflash_drv_log2phys((uint8_t *)fs + sector_offset, MFLASH_SECTOR_SIZE);
+    if (phys_addr == MFLASH_INVALID_ADDRESS)
+    {
+        return kStatus_Fail;
+    }
+
+    return mflash_drv_sector_erase(phys_addr);
+}
+
+/* Low level abstraction - program page of the filesystem */
+static status_t mflash_fs_page_program(mflash_fs_t *fs, uint32_t page_offset, uint32_t *data)
+{
+    uint32_t phys_addr;
+
+    /* Translate filesystem offset to physical address in FLASH */
+    phys_addr = mflash_drv_log2phys((uint8_t *)fs + page_offset, MFLASH_PAGE_SIZE);
+    if (phys_addr == MFLASH_INVALID_ADDRESS)
+    {
+        return kStatus_Fail;
+    }
+
+    return mflash_drv_page_program(phys_addr, data);
+}
+
+/* Low level abstraction - get pointer to filesystem location specified by offset */
+static inline void *mflash_fs_get_ptr(mflash_fs_t *fs, uint32_t offset)
+{
+    return (void *)((uint8_t *)fs + offset);
+}
+
+/*
+ * Check whether give area of FLASH is readable by direct pointer access.
+ * This is necessary on plaforms featuring page checksums as access to page containing invalid data may result in a
+ * hardfault.
+ */
+static status_t mflash_readable_check(void *ptr, uint32_t size)
+{
+#if defined(MFLASH_PAGE_INTEGRITY_CHECKS) && MFLASH_PAGE_INTEGRITY_CHECKS
+    status_t status;
+
+    uintptr_t start_addr = (uintptr_t)ptr - (uintptr_t)ptr % MFLASH_PAGE_SIZE;
+    uintptr_t end_addr   = (uintptr_t)ptr + size;
+
+    for (uintptr_t check_addr = start_addr; check_addr < end_addr; check_addr += MFLASH_PAGE_SIZE)
+    {
+        status = mflash_drv_is_readable(check_addr);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+    }
+
+    return kStatus_Success;
+#else
+    return kStatus_Success;
+#endif
+}
+
+/* Check for filesystem presence and validity */
+static status_t mflash_fs_check(mflash_fs_t *fs)
+{
+    status_t status;
+
+    /* Check params */
+    if (fs == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check readability before accessing filesystem structure by pointer */
+    status = mflash_readable_check(fs, sizeof(mflash_fs_header_t));
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Check magic */
+    if (fs->header.magic_no != MFLASH_DIR_MAGIC_NO)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check major version */
+    if ((fs->header.version & 0xFFFF0000u) != (MFLASH_FS_VERSION & 0xFFFF0000u))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check FLASH memory characteristics */
+    if (fs->header.page_size != MFLASH_PAGE_SIZE || fs->header.sector_size != MFLASH_SECTOR_SIZE)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check readability of the whole directory */
+    status =
+        mflash_readable_check(fs, sizeof(mflash_fs_header_t) + fs->header.file_count * sizeof(mflash_dir_record_t));
+
+    return status;
+}
+
+/* Check for presence of a file data */
+static status_t mflash_file_check(mflash_fs_t *fs, mflash_dir_record_t *dr)
+{
+    status_t status;
+    mflash_file_meta_t *meta;
+
+    /* Check params */
+    if (fs == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (dr == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Get pointer to file meta structure */
+    meta = mflash_fs_get_ptr(fs, dr->file_offset);
+
+    /* Check readability before accessing file meta structure */
+    status = mflash_readable_check(meta, sizeof(mflash_file_meta_t));
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Check magic signature */
+    if (meta->magic_no != MFLASH_META_MAGIC_NO)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check wheter actual file size in meta fits the pre-allocated area */
+    if (meta->file_size + sizeof(mflash_file_meta_t) > dr->alloc_size)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check readability of the whole file */
+    status = mflash_readable_check(meta, sizeof(mflash_file_meta_t) + meta->file_size);
+
+    return kStatus_Success;
+}
+
+/* Searches for directory record with given path and retrieves a copy of it */
+static status_t mflash_dir_lookup(mflash_fs_t *fs, char *path, mflash_dir_record_t *dr_ptr)
+{
+    uint32_t file_count     = fs->header.file_count;
+    mflash_dir_record_t *dr = fs->records;
+
+    for (uint32_t i = 0u; i < file_count; i++)
+    {
+        if (dir_path_match(dr, path))
+        {
+            if (NULL != dr_ptr)
+            {
+                *dr_ptr = *dr;
+            }
+            return kStatus_Success;
+        }
+        dr++;
+    }
+
+    return kStatus_Fail;
+}
+
+/* Create filesystem structure in FLASH according to given directory template */
+static status_t mflash_format_internal(mflash_fs_t *fs,
+                                       void *page_buf,
+                                       uint32_t fs_size_limit,
+                                       const mflash_file_t *dir_template)
+{
+    status_t status;
+
+    uint32_t file_count;
+    uint32_t total_sectors;
+
+    uint32_t dir_size;
+    uint32_t dir_sectors;
+
+    uint32_t file_offset;
+    uint32_t dir_offset;
+
+    mflash_fs_header_t *fsh;
+
+    /* The directory records shall be aligned to page size */
+    assert((MFLASH_PAGE_SIZE % sizeof(mflash_dir_record_t)) == 0u);
+
+    /* Count the files and calculate number of FLASH sectors to be occupied by the filesystem */
+    file_count    = 0;
+    total_sectors = 0;
+    for (const mflash_file_t *dt = dir_template; (NULL != dt->path) && ('\0' != dt->path[0]) && (0 != dt->max_size);
+         dt++)
+    {
+        /* Calculate number of sectors to be occupied by the file */
+        uint32_t file_sectors = (dt->max_size + MFLASH_SECTOR_SIZE - 1) / MFLASH_SECTOR_SIZE;
+        total_sectors += file_sectors;
+        file_count++;
+    }
+
+    dir_size    = file_count * sizeof(mflash_dir_record_t) + sizeof(mflash_fs_header_t);
+    dir_sectors = (dir_size + MFLASH_SECTOR_SIZE - 1) / MFLASH_SECTOR_SIZE;
+    total_sectors += dir_sectors;
+
+    /* Check whether the filestytem fits into the given FLASH area */
+    if ((0u != fs_size_limit) && (fs_size_limit < total_sectors * MFLASH_SECTOR_SIZE))
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Erase the whole FLASH area to be occupied by the filesystem */
+    for (uint32_t i = 0u; i < total_sectors; i++)
+    {
+        status = mflash_fs_sector_erase(fs, i * MFLASH_SECTOR_SIZE);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+    }
+
+    /* Clear the page buffer and set inital values for offsets */
+    (void)memset(page_buf, (int)MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
+    dir_offset  = file_count * sizeof(mflash_dir_record_t) + sizeof(mflash_fs_header_t);
+    file_offset = total_sectors * MFLASH_SECTOR_SIZE;
+
+    /* Create directory entries in reverse order so that programming of the page containing the dir header is the last
+     * step */
+    for (uint32_t fi = file_count; 0u != fi--;)
+    {
+        /* Check for enough space for the directory record */
+        assert(dir_offset >= sizeof(mflash_dir_record_t));
+
+        dir_offset -= sizeof(mflash_dir_record_t);
+
+        mflash_dir_record_t *dr = (mflash_dir_record_t *)((uint8_t *)page_buf + (dir_offset % MFLASH_PAGE_SIZE));
+        const mflash_file_t *dt = &dir_template[fi];
+
+        /* Calculate number of sectors to be occupied by the file */
+        uint32_t file_sectors = (dt->max_size + MFLASH_SECTOR_SIZE - 1) / MFLASH_SECTOR_SIZE;
+
+        /* Fill in directory record */
+        dr->alloc_size  = file_sectors * MFLASH_SECTOR_SIZE;
+        dr->file_offset = (file_offset -= dr->alloc_size);
+        dir_path_store(dr, dt->path);
+
+        if (dir_offset % MFLASH_PAGE_SIZE == 0u)
+        {
+            /* We reached the beginning of a page, program it and start over */
+            status = mflash_fs_page_program(fs, dir_offset, page_buf);
+            if (status != kStatus_Success)
+            {
+                return status;
+            }
+
+            /* Clear the page buffer */
+            (void)memset(page_buf, (int)MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
+        }
+    }
+
+    /* There should be space left exactly for the filesystem header */
+    assert(dir_offset == sizeof(mflash_fs_header_t));
+
+    /* Create filesystem header at the very beginning of the first page */
+    fsh              = (mflash_fs_header_t *)page_buf;
+    fsh->magic_no    = MFLASH_DIR_MAGIC_NO;
+    fsh->version     = MFLASH_FS_VERSION;
+    fsh->page_size   = MFLASH_PAGE_SIZE;
+    fsh->sector_size = MFLASH_SECTOR_SIZE;
+    fsh->total_size  = total_sectors * MFLASH_SECTOR_SIZE;
+    fsh->file_count  = file_count;
+
+    /* Programming of the first page puts header into place marking the filesystem as valid */
+    status = mflash_fs_page_program(fs, 0, page_buf);
+
+    return status;
+}
+
+/* Create filesystem structure in FLASH according to given directory template */
+static status_t mflash_format(mflash_fs_t *fs, uint32_t fs_size_limit, const mflash_file_t *dir_template)
+{
+    status_t status;
+    void *page_buf;
+
+    /* Check parameters */
+    if (dir_template == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Get page buffer for FLASH writes */
+    page_buf = mflash_page_buf_get();
+    if (page_buf == NULL)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Actual formatting of the filesystem */
+    status = mflash_format_internal(fs, page_buf, fs_size_limit, dir_template);
+
+    /* Release page buffer */
+    mflash_page_buf_release(page_buf);
+
+    return status;
+}
+
+/* Match dir against given template. Checks whether all files defined in the template are pre-allocsated in the fs
+ * directory */
+static status_t mflash_template_match(mflash_fs_t *fs, const mflash_file_t *dir_template)
+{
+    status_t status;
+
+    for (const mflash_file_t *dt = dir_template; (NULL != dt->path) && ('\0' != dt->path[0]) && (0u != dt->max_size);
+         dt++)
+    {
+        mflash_dir_record_t dr;
+
+        /* Lookup directory record */
+        status = mflash_dir_lookup(fs, dt->path, &dr);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+
+        /* Check whether pre-allocated size is sufficient */
+        if (dr.alloc_size < dt->max_size)
+        {
+            return kStatus_Fail;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/* Initialize mflash filesystem */
+static status_t mflash_fs_init(mflash_fs_t *fs, uint32_t fs_size_limit, const mflash_file_t *dir_template)
+{
+    status_t status;
+
+    /* Check whether there is a filesystem header and directory already in place */
+    status = mflash_fs_check(fs);
+
+    /* Filesystem is valid, check whether its directory provides records for all required files */
+    if (status == kStatus_Success)
+    {
+        status = mflash_template_match(fs, dir_template);
+    }
+
+    /* The filesystem not present or does not fit the template, create a new one */
+    if (status == kStatus_Fail) /* Error codes other then 'Fail' are not captured here but rather intentinally passed to
+                                   the caller */
+    {
+        status = mflash_format(fs, fs_size_limit, dir_template); /* Format the filestem */
+    }
+
+    if (status == kStatus_Success)
+    {
+        g_mflash_fs = fs; /* If all went ok, keep pointer to the filesytem */
+    }
+
+    return status;
+}
+
+/* API - Initialize mflash driver and filesystem at default address specified by linker symbol */
+status_t mflash_init(const mflash_file_t *dir_template, bool init_drv)
+{
+    status_t status;
+    mflash_fs_t *fs;
+
+    /* Initialize the driver */
+    if (init_drv)
+    {
+        status = mflash_drv_init();
+        if (status == kStatus_Fail)
+        {
+            return status;
+        }
+    }
+
+#ifdef MFLASH_FILE_BASEADDR
+    /* Convert physical address in FLASH to memory pointer */
+    fs = (mflash_fs_t *)mflash_drv_phys2log(MFLASH_FILE_BASEADDR, 0);
+#else
+    /* Otherwise take address from linker file */
+    fs = (mflash_fs_t *)MFLASH_FS_START;
+#endif
+
+    if (fs == NULL)
+    {
+        return kStatus_Fail;
+    }
+
+    return mflash_fs_init(fs, 0, dir_template);
+}
+
+/* Save file */
+static status_t mflash_file_save_internal(
+    mflash_fs_t *fs, void *page_buf, mflash_dir_record_t *dr, uint8_t *data, uint32_t size)
+{
+    status_t status;
+
+    /* Check whether the data + meta fits into the pre-allocated file area */
+    if (size + sizeof(mflash_file_meta_t) > dr->alloc_size)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Erase the whole file area sector by sector */
+    for (uint32_t sector_offset = 0; sector_offset < dr->alloc_size; sector_offset += MFLASH_SECTOR_SIZE)
+    {
+        /* Erase the sector */
+        status = mflash_fs_sector_erase(fs, dr->file_offset + sector_offset);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+    }
+
+    /* Program the file data page by page, skipping the first page containing meta that is going to be programmed in the
+     * last step */
+    for (uint32_t data_offset = MFLASH_PAGE_SIZE - sizeof(mflash_file_meta_t); data_offset < size;
+         data_offset += MFLASH_PAGE_SIZE)
+    {
+        /* Pointer and size of the data portion to be programmed */
+        void *copy_ptr     = data + data_offset;
+        uint32_t copy_size = size - data_offset;
+        if (copy_size > MFLASH_PAGE_SIZE)
+        {
+            copy_size = MFLASH_PAGE_SIZE;
+        }
+
+        (void)memset(page_buf, (int)MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
+        (void)memcpy(page_buf, copy_ptr, copy_size);
+
+        /* Data offset is off by sizeof(mflash_file_meta_t) as this structure occupies the very beginning of the first
+         * page */
+        status = mflash_fs_page_program(fs, dr->file_offset + data_offset + sizeof(mflash_file_meta_t), page_buf);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+    }
+
+    /* Prepare the missing portion of data to be programme to the first page */
+    uint32_t copy_size = size;
+    if (copy_size > MFLASH_PAGE_SIZE - sizeof(mflash_file_meta_t))
+    {
+        copy_size = MFLASH_PAGE_SIZE - sizeof(mflash_file_meta_t);
+    }
+
+    (void)memset(page_buf, (int)MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
+    (void)memcpy((uint8_t *)page_buf + sizeof(mflash_file_meta_t), data, copy_size);
+
+    /* Set file metadata */
+    mflash_file_meta_t *meta = (mflash_file_meta_t *)page_buf;
+    meta->file_size          = size;
+    meta->magic_no           = MFLASH_META_MAGIC_NO;
+
+    /* Program the first page putting the metadata in place which marks the file as valid */
+    status = mflash_fs_page_program(fs, dr->file_offset, page_buf);
+
+    return status;
+}
+
+/* API, save data to file with given path */
+status_t mflash_file_save(char *path, uint8_t *data, uint32_t size)
+{
+    status_t status;
+    mflash_dir_record_t dr;
+    mflash_fs_t *fs = g_mflash_fs;
+    void *page_buf;
+
+    if (path == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if ((data == NULL) && (size != 0u))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Lookup directory record */
+    status = mflash_dir_lookup(fs, path, &dr);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Get page buffer for FLASH writes */
+    page_buf = mflash_page_buf_get();
+    if (page_buf == NULL)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Save the file */
+    status = mflash_file_save_internal(fs, page_buf, &dr, data, size);
+
+    /* Release page buffer */
+    mflash_page_buf_release(page_buf);
+
+    return status;
+}
+
+/* Get direct pointer to file data */
+static status_t mflash_file_mmap_internal(mflash_fs_t *fs, mflash_dir_record_t *dr, uint8_t **pdata, uint32_t *psize)
+{
+    status_t status;
+    mflash_file_meta_t *meta;
+
+    status = mflash_file_check(fs, dr);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    meta = mflash_fs_get_ptr(fs, dr->file_offset);
+
+    *pdata = (uint8_t *)meta + sizeof(*meta);
+    *psize = meta->file_size;
+
+    return kStatus_Success;
+}
+
+/* API, get direct pointer to data of file with given path */
+status_t mflash_file_mmap(char *path, uint8_t **pdata, uint32_t *psize)
+{
+    status_t status;
+    mflash_dir_record_t dr;
+    mflash_fs_t *fs = g_mflash_fs;
+
+    if (path == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (pdata == NULL || psize == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Lookup directory record */
+    status = mflash_dir_lookup(fs, path, &dr);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = mflash_file_mmap_internal(fs, &dr, pdata, psize);
+
+    return status;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_file.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_file.h
new file mode 100644
index 0000000000..428905094c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/mflash_file.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MFLASH_FILE__
+#define __MFLASH_FILE__
+
+#include "fsl_common.h"
+
+#include "mflash_drv.h"
+
+#define MFLASH_MAX_PATH_LEN 56
+
+/*
+ * Template for file record defines file path and size to be pre-allocated for that file.
+ * The actual size of the file shall not exceed the size defined in the template.
+ */
+typedef struct
+{
+    char *path;
+    uint32_t max_size;
+} mflash_file_t;
+
+/*! @brief Initialization status of mflash subsystem */
+bool mflash_is_initialized(void);
+
+/*! @brief Initializes mflash filesystem and driver. Creates new filesystem unless already in place. */
+status_t mflash_init(const mflash_file_t *dir_template, bool init_drv);
+
+/*! @brief Saves data to file with given path. */
+status_t mflash_file_save(char *path, uint8_t *data, uint32_t size);
+
+/*! @brief Returns pointer for direct memory mapped access to file data. */
+status_t mflash_file_mmap(char *path, uint8_t **pdata, uint32_t *psize);
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/readme.txt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/readme.txt
new file mode 100644
index 0000000000..e36927dce8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash/mflash/readme.txt
@@ -0,0 +1,6 @@
+Overview
+========
+
+mflash_file is a simple statically allocated flat filesytem for FLASH memories.
+The storage consists of predefined set of named files with fixed maximal lenght.
+Its main purpose is to provide non-volatile storage for small data like device configuration and provisioning.
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash_config/flash_config.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash_config/flash_config.c
new file mode 100644
index 0000000000..ab9efe00ff
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash_config/flash_config.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2021-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "flash_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flash_config"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1)
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".flash_conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".flash_conf"
+#endif
+const fc_flexspi_nor_config_t flexspi_config = {
+    .memConfig =
+        {
+            .tag                 = FC_BLOCK_TAG,
+            .version             = FC_BLOCK_VERSION,
+            .readSampleClkSrc    = 1,
+            .csHoldTime          = 3,
+            .csSetupTime         = 3,
+            .deviceModeCfgEnable = 1,
+            .deviceModeSeq       = {.seqNum = 1, .seqId = 2},
+            .deviceModeArg       = 0x02,
+            .configCmdEnable     = 0,
+            .deviceType          = 0x1,
+            .sflashPadType       = kSerialFlash_4Pads,
+            .serialClkFreq       = 5,
+            .sflashA1Size        = 0x4000000U,
+            .sflashA2Size        = 0,
+            .sflashB1Size        = 0,
+            .sflashB2Size        = 0,
+            .lookupTable =
+                {
+                    /* Read */
+                    [0] = FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xEC, FC_RADDR_SDR, FC_FLEXSPI_4PAD, 0x20),
+                    [1] = FC_FLEXSPI_LUT_SEQ(FC_MODE8_SDR, FC_FLEXSPI_4PAD, 0xF0, FC_DUMMY_SDR, FC_FLEXSPI_4PAD, 0x04),
+                    [2] = FC_FLEXSPI_LUT_SEQ(FC_READ_SDR, FC_FLEXSPI_4PAD, 0x04, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
+
+                    /* Read Status */
+                    [4 * 1 + 0] =
+                        FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x05, FC_READ_SDR, FC_FLEXSPI_1PAD, 0x04),
+
+                    /* Write Status */
+                    [4 * 2 + 0] =
+                        FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x31, FC_WRITE_SDR, FC_FLEXSPI_1PAD, 0x01),
+
+                    /* Write Enable */
+                    [4 * 3 + 0] =
+                        FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x06, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
+
+                    /* Sector erase */
+                    [4 * 5 + 0] =
+                        FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x21, FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x20),
+
+                    /* Block erase */
+                    [4 * 8 + 0] =
+                        FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xDC, FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x20),
+
+                    /* Page program */
+                    [4 * 9 + 0] =
+                        FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x34, FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x20),
+                    [4 * 9 + 1] =
+                        FC_FLEXSPI_LUT_SEQ(FC_WRITE_SDR, FC_FLEXSPI_4PAD, 0x00, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
+
+                    /* chip erase */
+                    [4 * 11 + 0] =
+                        FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xC7, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
+                },
+        },
+    .pageSize           = 0x100,
+    .sectorSize         = 0x1000,
+    .ipcmdSerialClkFreq = 0,
+    .blockSize          = 0x10000,
+    .fcb_fill[0]        = 0xFFFFFFFF,
+};
+#endif /* BOOT_HEADER_ENABLE */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash_config/flash_config.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash_config/flash_config.h
new file mode 100644
index 0000000000..97b1b6bd7a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/flash_config/flash_config.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright 2021-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FLASH_CONFIG__
+#define __FLASH_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FLASH_CONFIG driver version 2.0.0. */
+#define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*******************************************************************************
+ * Definition
+ ******************************************************************************/
+
+/* FLEXSPI memory config block related defintions */
+#define FC_BLOCK_TAG     (0x42464346)
+#define FC_BLOCK_VERSION (0x00000000)
+
+#define FC_CMD_SDR        0x01
+#define FC_CMD_DDR        0x21
+#define FC_RADDR_SDR      0x02
+#define FC_RADDR_DDR      0x22
+#define FC_CADDR_SDR      0x03
+#define FC_CADDR_DDR      0x23
+#define FC_MODE1_SDR      0x04
+#define FC_MODE1_DDR      0x24
+#define FC_MODE2_SDR      0x05
+#define FC_MODE2_DDR      0x25
+#define FC_MODE4_SDR      0x06
+#define FC_MODE4_DDR      0x26
+#define FC_MODE8_SDR      0x07
+#define FC_MODE8_DDR      0x27
+#define FC_WRITE_SDR      0x08
+#define FC_WRITE_DDR      0x28
+#define FC_READ_SDR       0x09
+#define FC_READ_DDR       0x29
+#define FC_LEARN_SDR      0x0A
+#define FC_LEARN_DDR      0x2A
+#define FC_DATSZ_SDR      0x0B
+#define FC_DATSZ_DDR      0x2B
+#define FC_DUMMY_SDR      0x0C
+#define FC_DUMMY_DDR      0x2C
+#define FC_DUMMY_RWDS_SDR 0x0D
+#define FC_DUMMY_RWDS_DDR 0x2D
+#define FC_JMP_ON_CS      0x1F
+#define FC_STOP_EXE       0
+
+#define FC_FLEXSPI_1PAD 0
+#define FC_FLEXSPI_2PAD 1
+#define FC_FLEXSPI_4PAD 2
+#define FC_FLEXSPI_8PAD 3
+
+#define FC_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                           \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+/* !@brief Data pad used in Read command */
+enum
+{
+    kSerialFlash_1Pads = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+/* !@brief FLEXSPI clock configuration - In High speed boot mode mode */
+enum
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_80MHz  = 4,
+    kFlexSpiSerialClk_100MHz = 5,
+    kFlexSpiSerialClk_120MHz = 6,
+    kFlexSpiSerialClk_133MHz = 7,
+    kFlexSpiSerialClk_166MHz = 8,
+    kFlexSpiSerialClk_200MHz = 9,
+};
+
+/* !@brief FLEXSPI clock configuration - In Normal boot SDR mode */
+enum
+{
+    kFlexSpiSerialClk_SDR_24MHz = 1,
+    kFlexSpiSerialClk_SDR_48MHz = 2,
+};
+
+/* !@brief FLEXSPI clock configuration - In Normal boot DDR mode */
+enum
+{
+    kFlexSpiSerialClk_DDR_48MHz = 1,
+};
+
+/* !@brief Misc feature bit definitions */
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable         = 0, /* !< Bit for Differential clock enable */
+    kFlexSpiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */
+    kFlexSpiMiscOffset_SafeConfigFreqEnable  = 4, /* !< Bit for Safe Configuration Frequency enable */
+    kFlexSpiMiscOffset_DdrModeEnable         = 6, /* !< Bit for DDR clock confiuration indication. */
+};
+
+/* !@brief Flash Configuration Command Type */
+enum
+{
+    kDeviceConfigCmdType_Generic,    /* !< Generic command, for example: configure dummy cycles, drive strength, etc */
+    kDeviceConfigCmdType_QuadEnable, /* !< Quad Enable command */
+    kDeviceConfigCmdType_Spi2Xpi,    /* !< Switch from SPI to DPI/QPI/OPI mode */
+    kDeviceConfigCmdType_Xpi2Spi,    /* !< Switch from DPI/QPI/OPI to SPI mode */
+    kDeviceConfigCmdType_Spi2NoCmd,  /* !< Switch to 0-4-4/0-8-8 mode */
+    kDeviceConfigCmdType_Reset,      /* !< Reset device command */
+};
+
+typedef struct _fc_flexspi_dll_time
+{
+    uint8_t time_100ps;  /* !< Data valid time, in terms of 100ps */
+    uint8_t delay_cells; /* !< Data valid time, in terms of delay cells */
+} fc_flexspi_dll_time_t;
+
+/* !@brief FlexSPI LUT Sequence structure */
+typedef struct _fc_flexspi_lut_seq
+{
+    uint8_t seqNum; /* !< Sequence Number, valid number: 1-16 */
+    uint8_t seqId;  /* !< Sequence Index, valid number: 0-15 */
+    uint16_t reserved;
+} fc_flexspi_lut_seq_t;
+
+/* !@brief FlexSPI Memory Configuration Block */
+typedef struct _fc_flexspi_mem_config
+{
+    uint32_t tag;       /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */
+    uint32_t version;   /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
+    uint32_t reserved0; /* !< [0x008-0x00b] Reserved for future use */
+    uint8_t readSampleClkSrc;    /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
+    uint8_t csHoldTime;          /* !< [0x00d-0x00d] CS hold time, default value: 3 */
+    uint8_t csSetupTime;         /* !< [0x00e-0x00e] CS setup time, default value: 3 */
+    uint8_t columnAddressWidth;  /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+       Serial NAND, need to refer to datasheet */
+    uint8_t deviceModeCfgEnable; /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
+    uint8_t deviceModeType; /* !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+     Generic configuration, etc. */
+    uint16_t waitTimeCfgCommands; /* !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+     DPI/QPI/OPI switch or reset command */
+    fc_flexspi_lut_seq_t deviceModeSeq; /* !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] -
+     LUt sequence number, [31:16] Reserved */
+    uint32_t deviceModeArg;             /* !< [0x018-0x01b] Argument/Parameter for device configuration */
+    uint8_t configCmdEnable;            /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
+    uint8_t configModeType[3];          /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
+    fc_flexspi_lut_seq_t configCmdSeqs[3]; /* !< [0x020-0x02b] Sequence info for Device Configuration command, similar
+                                           as deviceModeSeq */
+    uint32_t reserved1;                    /* !< [0x02c-0x02f] Reserved for future use */
+    uint32_t configCmdArgs[3];             /* !< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
+    uint32_t reserved2;                    /* !< [0x03c-0x03f] Reserved for future use */
+    uint32_t controllerMiscOption; /* !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for
+      more details */
+    uint8_t deviceType;            /* !< [0x044-0x044] Device Type:  See Flash Type Definition for more details */
+    uint8_t sflashPadType; /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
+    uint8_t serialClkFreq; /* !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+     Chapter for more details */
+    uint8_t lutCustomSeqEnable; /* !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+     be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
+    uint32_t reserved3[2];      /* !< [0x048-0x04f] Reserved for future use */
+    uint32_t sflashA1Size;      /* !< [0x050-0x053] Size of Flash connected to A1 */
+    uint32_t sflashA2Size;      /* !< [0x054-0x057] Size of Flash connected to A2 */
+    uint32_t sflashB1Size;      /* !< [0x058-0x05b] Size of Flash connected to B1 */
+    uint32_t sflashB2Size;      /* !< [0x05c-0x05f] Size of Flash connected to B2 */
+    uint32_t csPadSettingOverride;          /* !< [0x060-0x063] CS pad setting override value */
+    uint32_t sclkPadSettingOverride;        /* !< [0x064-0x067] SCK pad setting override value */
+    uint32_t dataPadSettingOverride;        /* !< [0x068-0x06b] data pad setting override value */
+    uint32_t dqsPadSettingOverride;         /* !< [0x06c-0x06f] DQS pad setting override value */
+    uint32_t timeoutInMs;                   /* !< [0x070-0x073] Timeout threshold for read status command */
+    uint32_t commandInterval;               /* !< [0x074-0x077] CS deselect interval between two commands */
+    fc_flexspi_dll_time_t dataValidTime[2]; /* !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
+    uint16_t busyOffset;                    /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */
+    uint16_t busyBitPolarity; /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+     busy flag is 0 when flash device is busy */
+    uint32_t lookupTable[64]; /* !< [0x080-0x17f] Lookup table holds Flash command sequences */
+    fc_flexspi_lut_seq_t lutCustomSeq[12]; /* !< [0x180-0x1af] Customizable LUT Sequences */
+    uint32_t reserved4[4];                 /* !< [0x1b0-0x1bf] Reserved for future use */
+} fc_flexspi_mem_config_t;
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _fc_flexspi_nor_config
+{
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+    uint8_t padding[0x400];            /* !< Padding for MDK and IAR */
+#endif
+    fc_flexspi_mem_config_t memConfig; /* !< Common memory configuration info via FlexSPI */
+    uint32_t pageSize;                 /* !< Page size of Serial NOR */
+    uint32_t sectorSize;               /* !< Sector size of Serial NOR */
+    uint8_t ipcmdSerialClkFreq;        /* !< Clock frequency for IP command */
+    uint8_t isUniformBlockSize;        /* !< Sector/Block size is the same */
+    uint8_t isDataOrderSwapped;        /* !< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
+    uint8_t reserved0[1];              /* !< Reserved for future use */
+    uint8_t serialNorType;             /* !< Serial NOR Flash type: 0/1/2/3 */
+    uint8_t needExitNoCmdMode;         /* !< Need to exit NoCmd mode before other IP command */
+    uint8_t halfClkForNonReadCmd;      /* !< Half the Serial Clock for non-read command: true/false */
+    uint8_t needRestoreNoCmdMode;      /* !< Need to Restore NoCmd mode after IP commmand execution */
+    uint32_t blockSize;                /* !< Block size */
+    uint32_t flashStateCtx;            /* !< Flash State Context */
+    uint32_t reserve2[10];             /* !< Reserved for future use */
+    uint32_t fcb_fill[0x280];          /* !< Fill */
+} fc_flexspi_nor_config_t;
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __FLASH_CONFIG__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/frdm-rw612-xpresso-freertos-builtin JLink Debug.launch b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/frdm-rw612-xpresso-freertos-builtin JLink Debug.launch
new file mode 100644
index 0000000000..60eba216d5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/frdm-rw612-xpresso-freertos-builtin JLink Debug.launch	
@@ -0,0 +1,94 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.nxp.mcuxpresso.core.debug.support.segger.launchConfigurationType">
+    <stringAttribute key="com.crt.ctrlcenter.OFSemuDetails" value="JLink1067289795"/>
+    <booleanAttribute key="com.crt.ctrlcenter.mainBreakIsHardware" value="true"/>
+    <stringAttribute key="com.crt.ctrlcenter.serialNumber" value="USB 1067289795"/>
+    <listAttribute key="com.crt.ctrlcenter.symbolsAndImagesGroupSettings"/>
+    <intAttribute key="com.nxp.mcuxpresso.core.debug.support.segger.launches.JLinkLaunchConfigHandler.version" value="2"/>
+    <booleanAttribute key="com.nxp.mcuxpresso.flash.clear.console" value="true"/>
+    <booleanAttribute key="com.nxp.mcuxpresso.flash.confirm" value="false"/>
+    <stringAttribute key="com.nxp.mcuxpresso.ide.probe.manufacturer" value="SEGGER"/>
+    <stringAttribute key="com.nxp.mcuxpresso.ide.probe.name" value="J-Link MCU-Link"/>
+    <stringAttribute key="com.nxp.mcuxpresso.ide.probe.nickname" value=""/>
+    <stringAttribute key="com.nxp.mcuxpresso.ide.probe.type" value="USB"/>
+    <stringAttribute key="com.nxp.mcuxpresso.jlink.flash.base.address" value="0x8000000"/>
+    <stringAttribute key="com.nxp.mcuxpresso.jlink.flash.executable" value="hex"/>
+    <booleanAttribute key="com.nxp.mcuxpresso.jlink.flash.halt.target" value="true"/>
+    <booleanAttribute key="com.nxp.mcuxpresso.jlink.flash.reset.target" value="true"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.SettingsFile" value="${ProjDirPath}/${ConfigName}/${LaunchConfigName} SettingsFile.jlink"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.auto.startup" value="auto"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.device" value="RW612"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.endian" value="little"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.halt.target" value="-halt"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.if" value="SWD"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.init.register" value="-noir"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.jlinkscriptfile" value=""/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.options" value=""/>
+    <intAttribute key="com.nxp.mcuxpresso.segger.port" value="2331"/>
+    <booleanAttribute key="com.nxp.mcuxpresso.segger.powertarget 50" value="false"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.reset" value="true;"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.rtos" value="true;GDBServer/RTOSPlugin_FreeRTOS"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.select" value="USB=1067289795"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.silent" value="-nosilent"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.singlerun" value="-singlerun"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.speed" value="fixed 4000"/>
+    <intAttribute key="com.nxp.mcuxpresso.segger.swoport" value="2332"/>
+    <intAttribute key="com.nxp.mcuxpresso.segger.telnetport" value="2333"/>
+    <stringAttribute key="com.nxp.mcuxpresso.segger.verify" value="-vd"/>
+    <stringAttribute key="disconnect" value="Run"/>
+    <stringAttribute key="launch.config.handler" value="com.nxp.mcuxpresso.core.debug.support.segger.launches.JLinkLaunchConfigHandler"/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="0"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="monitor reset"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="org.eclipse.cdt.debug.gdbjtag.core.jtagdevice.genericDevice"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.EXTERNAL_CONSOLE" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/frdm-rw612-xpresso-freertos-builtin.axf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="frdm-rw612-xpresso-freertos-builtin"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.252552941"/>
+    <booleanAttribute key="org.eclipse.debug.core.ATTR_FORCE_SYSTEM_CONSOLE_ENCODING" value="false"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/frdm-rw612-xpresso-freertos-builtin"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <mapAttribute key="org.eclipse.debug.core.preferred_launchers">
+        <mapEntry key="[debug]" value="com.nxp.mcuxpresso.core.debug.support.segger.dsfLaunchDelegate"/>
+    </mapAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;"/>
+    <stringAttribute key="process_factory_id" value="com.nxp.mcuxpresso.core.debug.override.MCXProcessFactory"/>
+    <booleanAttribute key="semihost" value="true"/>
+    <stringAttribute key="start.server" value="true"/>
+</launchConfiguration>
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/frdm-rw612-xpresso-freertos-builtin.mex b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/frdm-rw612-xpresso-freertos-builtin.mex
new file mode 100644
index 0000000000..9c8381e294
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/frdm-rw612-xpresso-freertos-builtin.mex
@@ -0,0 +1,227 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="RW612" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="97025c7c-9d28-4956-b425-25e2a6e4a00a" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>RW612</processor>
+      <package>RW612ETA2I</package>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="cm33">
+         <core name="Cortex-M33" id="cm33" description=""/>
+      </cores>
+      <description>Configuration imported from frdm-rw612-xpresso-freertos-builtin</description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="17.0" enabled="false" update_project_code="true">
+         <pins_profile>
+            <processor_version>N/A</processor_version>
+         </pins_profile>
+         <functions_list/>
+      </pins>
+      <clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
+         <clocks_profile>
+            <processor_version>24.12.10</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="CAU.xtal_in" description="&apos;XTALIN&apos; (Pins tool id: CAU.xtal_in, Clocks tool id: CAU.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="CAU.xtal_out" description="&apos;XTALOUT&apos; (Pins tool id: CAU.xtal_out, Clocks tool id: CAU.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="PMU.xtal32k_in" description="&apos;AON_XTAL32K_IN&apos; (Pins tool id: PMU.xtal32k_in, Clocks tool id: PMU.AON_XTAL32K_IN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="PMU.xtal32k_out" description="&apos;AON_XTAL32K_OUT&apos; (Pins tool id: PMU.xtal32k_out, Clocks tool id: PMU.AON_XTAL32K_OUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="CAU.XTAL_OSC.outFreq" value="40 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="audio_pll_clk.outFreq" value="4246732800/345600007 MHz" locked="false" accuracy=""/>
+                  <clock_output id="aux0_pll_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="avpll_ch1_clkout.outFreq" value="4246732800/345600007 MHz" locked="false" accuracy=""/>
+                  <clock_output id="avpll_ch2_clkout.outFreq" value="1415577600/22118401 MHz" locked="false" accuracy=""/>
+                  <clock_output id="cau_slp_clk.outFreq" value="4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="clk_32k.outFreq" value="32 kHz" locked="false" accuracy=""/>
+                  <clock_output id="clk_pmu_sys.outFreq" value="52 MHz" locked="false" accuracy=""/>
+                  <clock_output id="els_128m_clk.outFreq" value="128 MHz" locked="false" accuracy=""/>
+                  <clock_output id="els_256m_clk.outFreq" value="256 MHz" locked="false" accuracy=""/>
+                  <clock_output id="els_64m_clk.outFreq" value="64 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ffro_clk_div4.outFreq" value="640/53 MHz" locked="false" accuracy=""/>
+                  <clock_output id="hclk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="lposc_clk_i.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="main_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="main_pll_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="otp_fuse_32m_clk.outFreq" value="32 MHz" locked="false" accuracy=""/>
+                  <clock_output id="refclk_phy.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="sfro_clk_i.outFreq" value="16 MHz" locked="false" accuracy=""/>
+                  <clock_output id="systick_fclk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="t3pll_mci_256m.outFreq" value="256 MHz" locked="false" accuracy=""/>
+                  <clock_output id="t3pll_mci_48_60m_irc.outFreq" value="2560/53 MHz" locked="false" accuracy=""/>
+                  <clock_output id="tcpu_mci_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="tddr_mci_flexspi_clk.outFreq" value="320 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CLKCTL0.MAINCLKSELB.sel" value="CLKCTL0.MAINPLLCLKDIV" locked="false"/>
+                  <setting id="CLKCTL0.MAINPLLCLKDIV.scale" value="1" locked="true"/>
+                  <setting id="CLKCTL0.PMUFCLKDIV.scale" value="5" locked="true"/>
+                  <setting id="CLKCTL0.SYSCPUAHBCLKDIV.scale" value="1" locked="true"/>
+                  <setting id="CLKCTL0.SYSTICKFCLKSEL.sel" value="CLKCTL0.SYSTICKFCLKDIV" locked="false"/>
+                  <setting id="CLKCTL0.WDT0FCLKSEL.sel" value="NO_CLOCK" locked="false"/>
+                  <setting id="CLKCTL1.FRGPLLCLKDIV.scale" value="13" locked="true"/>
+                  <setting id="CLKCTL1.OSEVENTFCLKSEL.sel" value="NO_CLOCK" locked="false"/>
+                  <setting id="REFCLK_SYS_Config" value="Disabled" locked="false"/>
+                  <setting id="SYSCTL2.CH1_M.scale" value="2621440" locked="true"/>
+                  <setting id="SYSCTL2.CH1_OFFSET_DIV.scale" value="345600007" locked="true"/>
+                  <setting id="SYSCTL2.CH2_M.scale" value="2621440" locked="true"/>
+                  <setting id="SYSCTL2.CH2_OFFSET_DIV.scale" value="66355203" locked="true"/>
+                  <setting id="SYSCTL2.T3_FBDIV.scale" value="64" locked="true"/>
+                  <setting id="SYSCTL2.T3_REFDIV.scale" value="1" locked="true"/>
+                  <setting id="T3PLL_MCI_213P3M_Config" value="Disabled" locked="false"/>
+                  <setting id="T3PLL_MCI_FLEXSPI_Config" value="Disabled" locked="false"/>
+                  <setting id="TCPU_MCI_FLEXSPI_CLK_Config" value="Disabled" locked="false"/>
+                  <setting id="TDDR_MCI_ENET_CLK_Config" value="Disabled" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockLPR" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="CAU.xtal_in" description="&apos;XTALIN&apos; (Pins tool id: CAU.xtal_in, Clocks tool id: CAU.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockLPR">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="CAU.xtal_out" description="&apos;XTALOUT&apos; (Pins tool id: CAU.xtal_out, Clocks tool id: CAU.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockLPR">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="PMU.xtal32k_in" description="&apos;AON_XTAL32K_IN&apos; (Pins tool id: PMU.xtal32k_in, Clocks tool id: PMU.AON_XTAL32K_IN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockLPR">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="PMU.xtal32k_out" description="&apos;AON_XTAL32K_OUT&apos; (Pins tool id: PMU.xtal32k_out, Clocks tool id: PMU.AON_XTAL32K_OUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockLPR">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockLPR">
+                     <feature name="enabled" evaluation="equal" configuration="cm33">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockLPR">
+                     <feature name="enabled" evaluation="equal" configuration="cm33">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockLPR">
+                     <feature name="enabled" evaluation="equal" configuration="cm33">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="CAU.XTAL_OSC.outFreq" value="40 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="aux0_pll_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="clk_32k.outFreq" value="32 kHz" locked="false" accuracy=""/>
+                  <clock_output id="clk_pmu_sys.outFreq" value="52 MHz" locked="false" accuracy=""/>
+                  <clock_output id="els_128m_clk.outFreq" value="128 MHz" locked="false" accuracy=""/>
+                  <clock_output id="els_256m_clk.outFreq" value="256 MHz" locked="false" accuracy=""/>
+                  <clock_output id="els_64m_clk.outFreq" value="64 MHz" locked="false" accuracy=""/>
+                  <clock_output id="hclk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="main_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="main_pll_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="otp_fuse_32m_clk.outFreq" value="32 MHz" locked="false" accuracy=""/>
+                  <clock_output id="refclk_phy.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="refclk_sys.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="sfro_clk_i.outFreq" value="16 MHz" locked="false" accuracy=""/>
+                  <clock_output id="systick_fclk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+                  <clock_output id="t3pll_mci_256m.outFreq" value="256 MHz" locked="false" accuracy=""/>
+                  <clock_output id="tcpu_mci_clk.outFreq" value="260 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="AVPLL_Init_Config" value="Disabled" locked="false"/>
+                  <setting id="CAU_SLP_CLK_Config" value="Disabled" locked="false"/>
+                  <setting id="CLKCTL0.MAINCLKSELB.sel" value="CLKCTL0.MAINPLLCLKDIV" locked="false"/>
+                  <setting id="CLKCTL0.MAINPLLCLKDIV.scale" value="1" locked="true"/>
+                  <setting id="CLKCTL0.SYSOSCBYPASS_SEL.sel" value="NO_CLOCK" locked="false"/>
+                  <setting id="CLKCTL0.SYSTICKFCLKSEL.sel" value="CLKCTL0.SYSTICKFCLKDIV" locked="false"/>
+                  <setting id="CLKCTL1.CLKOUTSEL1.sel" value="CLKCTL1.CLKOUTSEL0" locked="false"/>
+                  <setting id="CLKCTL1.CLKOUTSEL2.sel" value="CLKCTL1.CLKOUTSEL1" locked="false"/>
+                  <setting id="CLKCTL1.FRGPLLCLKDIV.scale" value="13" locked="true"/>
+                  <setting id="SYSCTL2.T3_FBDIV.scale" value="64" locked="false"/>
+                  <setting id="SYSCTL2.TCPU_FBDIV.scale" value="78" locked="true"/>
+                  <setting id="SYSCTL2.TCPU_MCI_FLEXSPI_CLK_DIV.scale" value="10" locked="true"/>
+                  <setting id="SYSCTL2.TCPU_REFDIV.scale" value="1" locked="true"/>
+                  <setting id="T3PLL_MCI_213P3M_Config" value="Disabled" locked="false"/>
+                  <setting id="T3PLL_MCI_48_60M_IRC_Config" value="Disabled" locked="false"/>
+                  <setting id="T3PLL_MCI_FLEXSPI_Config" value="Disabled" locked="false"/>
+                  <setting id="TCPU_MCI_FLEXSPI_CLK_Config" value="Disabled" locked="false"/>
+                  <setting id="TDDR_MCI_ENET_CLK_Config" value="Disabled" locked="false"/>
+                  <setting id="TDDR_MCI_FLEXSPI_CLK_Config" value="Disabled" locked="false"/>
+                  <setting id="TDDR_PLL_Init_Config" value="Disabled" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="4.0" enabled="false" update_project_code="true">
+         <dcdx_profile>
+            <processor_version>N/A</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="15.0" enabled="false" update_project_code="true">
+         <peripherals_profile>
+            <processor_version>N/A</processor_version>
+         </peripherals_profile>
+         <functional_groups/>
+         <components/>
+      </periphs>
+      <tee name="TEE" version="8.0" enabled="false" update_project_code="true">
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/croutine.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/croutine.c
new file mode 100644
index 0000000000..cbef58562b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/croutine.c
@@ -0,0 +1,382 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if ( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+    #ifdef portREMOVE_STATIC_QUALIFIER
+        #define static
+    #endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /**< Prioritised ready co-routines. */
+    static List_t xDelayedCoRoutineList1;                                   /**< Delayed co-routines. */
+    static List_t xDelayedCoRoutineList2;                                   /**< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+    static List_t * pxDelayedCoRoutineList = NULL;                          /**< Points to the delayed co-routine list currently being used. */
+    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /**< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+    static List_t xPendingReadyCoRoutineList;                               /**< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+    CRCB_t * pxCurrentCoRoutine = NULL;
+    static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+    static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+    #define corINITIAL_STATE    ( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority.  It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+    #define prvAddCoRoutineToReadyQueue( pxCRCB )                                                                               \
+    do {                                                                                                                        \
+        if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority )                                                              \
+        {                                                                                                                       \
+            uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority;                                                               \
+        }                                                                                                                       \
+        vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \
+    } while( 0 )
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+    static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+    static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+    static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+    BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex )
+    {
+        BaseType_t xReturn;
+        CRCB_t * pxCoRoutine;
+
+        traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex );
+
+        /* Allocate the memory that will store the co-routine control block. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+
+        if( pxCoRoutine )
+        {
+            /* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+            * be created and the co-routine data structures need initialising. */
+            if( pxCurrentCoRoutine == NULL )
+            {
+                pxCurrentCoRoutine = pxCoRoutine;
+                prvInitialiseCoRoutineLists();
+            }
+
+            /* Check the priority is within limits. */
+            if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+            {
+                uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+            }
+
+            /* Fill out the co-routine control block from the function parameters. */
+            pxCoRoutine->uxState = corINITIAL_STATE;
+            pxCoRoutine->uxPriority = uxPriority;
+            pxCoRoutine->uxIndex = uxIndex;
+            pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+            /* Initialise all the other co-routine control block parameters. */
+            vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+            vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+            /* Set the co-routine control block as a link back from the ListItem_t.
+             * This is so we can get back to the containing CRCB from a generic item
+             * in a list. */
+            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+            /* Event lists are always in priority order. */
+            listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+            /* Now the co-routine has been initialised it can be added to the ready
+             * list at the correct priority. */
+            prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
+
+        traceRETURN_xCoRoutineCreate( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
+                                     List_t * pxEventList )
+    {
+        TickType_t xTimeToWake;
+
+        traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList );
+
+        /* Calculate the time to wake - this may overflow but this is
+         * not a problem. */
+        xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+        /* We must remove ourselves from the ready list before adding
+         * ourselves to the blocked list as the same list item is used for
+         * both lists. */
+        ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+        /* The list item will be inserted in wake time order. */
+        listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+        if( xTimeToWake < xCoRoutineTickCount )
+        {
+            /* Wake time has overflowed.  Place this item in the
+             * overflow list. */
+            vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+        }
+        else
+        {
+            /* The wake time has not overflowed, so we can use the
+             * current block list. */
+            vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+        }
+
+        if( pxEventList )
+        {
+            /* Also add the co-routine to an event list.  If this is done then the
+             * function must be called with interrupts disabled. */
+            vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+        }
+
+        traceRETURN_vCoRoutineAddToDelayedList();
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvCheckPendingReadyList( void )
+    {
+        /* Are there any co-routines waiting to get moved to the ready list?  These
+         * are co-routines that have been readied by an ISR.  The ISR cannot access
+         * the ready lists itself. */
+        while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+        {
+            CRCB_t * pxUnblockedCRCB;
+
+            /* The pending ready list can be accessed by an ISR. */
+            portDISABLE_INTERRUPTS();
+            {
+                pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );
+                ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+            }
+            portENABLE_INTERRUPTS();
+
+            ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+            prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvCheckDelayedList( void )
+    {
+        CRCB_t * pxCRCB;
+
+        xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+
+        while( xPassedTicks )
+        {
+            xCoRoutineTickCount++;
+            xPassedTicks--;
+
+            /* If the tick count has overflowed we need to swap the ready lists. */
+            if( xCoRoutineTickCount == 0 )
+            {
+                List_t * pxTemp;
+
+                /* Tick count has overflowed so we need to swap the delay lists.  If there are
+                 * any items in pxDelayedCoRoutineList here then there is an error! */
+                pxTemp = pxDelayedCoRoutineList;
+                pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+                pxOverflowDelayedCoRoutineList = pxTemp;
+            }
+
+            /* See if this tick has made a timeout expire. */
+            while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+            {
+                pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+                if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+                {
+                    /* Timeout not yet expired. */
+                    break;
+                }
+
+                portDISABLE_INTERRUPTS();
+                {
+                    /* The event could have occurred just before this critical
+                     *  section.  If this is the case then the generic list item will
+                     *  have been moved to the pending ready list and the following
+                     *  line is still valid.  Also the pvContainer parameter will have
+                     *  been set to NULL so the following lines are also valid. */
+                    ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+                    /* Is the co-routine waiting on an event also? */
+                    if( pxCRCB->xEventListItem.pxContainer )
+                    {
+                        ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+                    }
+                }
+                portENABLE_INTERRUPTS();
+
+                prvAddCoRoutineToReadyQueue( pxCRCB );
+            }
+        }
+
+        xLastTickCount = xCoRoutineTickCount;
+    }
+/*-----------------------------------------------------------*/
+
+    void vCoRoutineSchedule( void )
+    {
+        traceENTER_vCoRoutineSchedule();
+
+        /* Only run a co-routine after prvInitialiseCoRoutineLists() has been
+         * called.  prvInitialiseCoRoutineLists() is called automatically when a
+         * co-routine is created. */
+        if( pxDelayedCoRoutineList != NULL )
+        {
+            /* See if any co-routines readied by events need moving to the ready lists. */
+            prvCheckPendingReadyList();
+
+            /* See if any delayed co-routines have timed out. */
+            prvCheckDelayedList();
+
+            /* Find the highest priority queue that contains ready co-routines. */
+            while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+            {
+                if( uxTopCoRoutineReadyPriority == 0 )
+                {
+                    /* No more co-routines to check. */
+                    return;
+                }
+
+                --uxTopCoRoutineReadyPriority;
+            }
+
+            /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+             * of the same priority get an equal share of the processor time. */
+            listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+            /* Call the co-routine. */
+            ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+        }
+
+        traceRETURN_vCoRoutineSchedule();
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvInitialiseCoRoutineLists( void )
+    {
+        UBaseType_t uxPriority;
+
+        for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+        {
+            vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+        }
+
+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+        vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+        /* Start with pxDelayedCoRoutineList using list1 and the
+         * pxOverflowDelayedCoRoutineList using list2. */
+        pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+        pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )
+    {
+        CRCB_t * pxUnblockedCRCB;
+        BaseType_t xReturn;
+
+        traceENTER_xCoRoutineRemoveFromEventList( pxEventList );
+
+        /* This function is called from within an interrupt.  It can only access
+         * event lists and the pending ready list.  This function assumes that a
+         * check has already been made to ensure pxEventList is not empty. */
+        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+        vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+        if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+        {
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+
+        traceRETURN_xCoRoutineRemoveFromEventList( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES == 0 */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/event_groups.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/event_groups.c
new file mode 100644
index 0000000000..91b3b897f9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/event_groups.c
@@ -0,0 +1,870 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+typedef struct EventGroupDef_t
+{
+    EventBits_t uxEventBits;
+    List_t xTasksWaitingForBits; /**< List of tasks waiting for a bit to be set. */
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxEventGroupNumber;
+    #endif
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+    #endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+                                        const EventBits_t uxBitsToWaitFor,
+                                        const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
+    {
+        EventGroup_t * pxEventBits;
+
+        traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer );
+
+        /* A StaticEventGroup_t object must be provided. */
+        configASSERT( pxEventGroupBuffer );
+
+        #if ( configASSERT_DEFINED == 1 )
+        {
+            /* Sanity check that the size of the structure used to declare a
+             * variable of type StaticEventGroup_t equals the size of the real
+             * event group structure. */
+            volatile size_t xSize = sizeof( StaticEventGroup_t );
+            configASSERT( xSize == sizeof( EventGroup_t ) );
+        }
+        #endif /* configASSERT_DEFINED */
+
+        /* The user has provided a statically allocated event group - use it. */
+        /* MISRA Ref 11.3.1 [Misaligned access] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+        /* coverity[misra_c_2012_rule_11_3_violation] */
+        pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer;
+
+        if( pxEventBits != NULL )
+        {
+            pxEventBits->uxEventBits = 0;
+            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+            {
+                /* Both static and dynamic allocation can be used, so note that
+                 * this event group was created statically in case the event group
+                 * is later deleted. */
+                pxEventBits->ucStaticallyAllocated = pdTRUE;
+            }
+            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+            traceEVENT_GROUP_CREATE( pxEventBits );
+        }
+        else
+        {
+            /* xEventGroupCreateStatic should only ever be called with
+             * pxEventGroupBuffer pointing to a pre-allocated (compile time
+             * allocated) StaticEventGroup_t variable. */
+            traceEVENT_GROUP_CREATE_FAILED();
+        }
+
+        traceRETURN_xEventGroupCreateStatic( pxEventBits );
+
+        return pxEventBits;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+    EventGroupHandle_t xEventGroupCreate( void )
+    {
+        EventGroup_t * pxEventBits;
+
+        traceENTER_xEventGroupCreate();
+
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
+
+        if( pxEventBits != NULL )
+        {
+            pxEventBits->uxEventBits = 0;
+            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+            {
+                /* Both static and dynamic allocation can be used, so note this
+                 * event group was allocated statically in case the event group is
+                 * later deleted. */
+                pxEventBits->ucStaticallyAllocated = pdFALSE;
+            }
+            #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+            traceEVENT_GROUP_CREATE( pxEventBits );
+        }
+        else
+        {
+            traceEVENT_GROUP_CREATE_FAILED();
+        }
+
+        traceRETURN_xEventGroupCreate( pxEventBits );
+
+        return pxEventBits;
+    }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+                             const EventBits_t uxBitsToSet,
+                             const EventBits_t uxBitsToWaitFor,
+                             TickType_t xTicksToWait )
+{
+    EventBits_t uxOriginalBitValue, uxReturn;
+    EventGroup_t * pxEventBits = xEventGroup;
+    BaseType_t xAlreadyYielded;
+    BaseType_t xTimeoutOccurred = pdFALSE;
+
+    traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+
+    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+    configASSERT( uxBitsToWaitFor != 0 );
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+    {
+        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+    }
+    #endif
+
+    vTaskSuspendAll();
+    {
+        uxOriginalBitValue = pxEventBits->uxEventBits;
+
+        ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+        if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+        {
+            /* All the rendezvous bits are now set - no need to block. */
+            uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+            /* Rendezvous always clear the bits.  They will have been cleared
+             * already unless this is the only task in the rendezvous. */
+            pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+            xTicksToWait = 0;
+        }
+        else
+        {
+            if( xTicksToWait != ( TickType_t ) 0 )
+            {
+                traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+                /* Store the bits that the calling task is waiting for in the
+                 * task's event list item so the kernel knows when a match is
+                 * found.  Then enter the blocked state. */
+                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+                /* This assignment is obsolete as uxReturn will get set after
+                 * the task unblocks, but some compilers mistakenly generate a
+                 * warning about uxReturn being returned without being set if the
+                 * assignment is omitted. */
+                uxReturn = 0;
+            }
+            else
+            {
+                /* The rendezvous bits were not set, but no block time was
+                 * specified - just return the current event bit value. */
+                uxReturn = pxEventBits->uxEventBits;
+                xTimeoutOccurred = pdTRUE;
+            }
+        }
+    }
+    xAlreadyYielded = xTaskResumeAll();
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        if( xAlreadyYielded == pdFALSE )
+        {
+            taskYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* The task blocked to wait for its required bits to be set - at this
+         * point either the required bits were set or the block time expired.  If
+         * the required bits were set they will have been stored in the task's
+         * event list item, and they should now be retrieved then cleared. */
+        uxReturn = uxTaskResetEventItemValue();
+
+        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+        {
+            /* The task timed out, just return the current event bit value. */
+            taskENTER_CRITICAL();
+            {
+                uxReturn = pxEventBits->uxEventBits;
+
+                /* Although the task got here because it timed out before the
+                 * bits it was waiting for were set, it is possible that since it
+                 * unblocked another task has set the bits.  If this is the case
+                 * then it needs to clear the bits before exiting. */
+                if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+                {
+                    pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            taskEXIT_CRITICAL();
+
+            xTimeoutOccurred = pdTRUE;
+        }
+        else
+        {
+            /* The task unblocked because the bits were set. */
+        }
+
+        /* Control bits might be set as the task had blocked should not be
+         * returned. */
+        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+    }
+
+    traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xTimeoutOccurred;
+
+    traceRETURN_xEventGroupSync( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 const BaseType_t xClearOnExit,
+                                 const BaseType_t xWaitForAllBits,
+                                 TickType_t xTicksToWait )
+{
+    EventGroup_t * pxEventBits = xEventGroup;
+    EventBits_t uxReturn, uxControlBits = 0;
+    BaseType_t xWaitConditionMet, xAlreadyYielded;
+    BaseType_t xTimeoutOccurred = pdFALSE;
+
+    traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+
+    /* Check the user is not attempting to wait on the bits used by the kernel
+     * itself, and that at least one bit is being requested. */
+    configASSERT( xEventGroup );
+    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+    configASSERT( uxBitsToWaitFor != 0 );
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+    {
+        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+    }
+    #endif
+
+    vTaskSuspendAll();
+    {
+        const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+        /* Check to see if the wait condition is already met or not. */
+        xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+        if( xWaitConditionMet != pdFALSE )
+        {
+            /* The wait condition has already been met so there is no need to
+             * block. */
+            uxReturn = uxCurrentEventBits;
+            xTicksToWait = ( TickType_t ) 0;
+
+            /* Clear the wait bits if requested to do so. */
+            if( xClearOnExit != pdFALSE )
+            {
+                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else if( xTicksToWait == ( TickType_t ) 0 )
+        {
+            /* The wait condition has not been met, but no block time was
+             * specified, so just return the current value. */
+            uxReturn = uxCurrentEventBits;
+            xTimeoutOccurred = pdTRUE;
+        }
+        else
+        {
+            /* The task is going to block to wait for its required bits to be
+             * set.  uxControlBits are used to remember the specified behaviour of
+             * this call to xEventGroupWaitBits() - for use when the event bits
+             * unblock the task. */
+            if( xClearOnExit != pdFALSE )
+            {
+                uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            if( xWaitForAllBits != pdFALSE )
+            {
+                uxControlBits |= eventWAIT_FOR_ALL_BITS;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Store the bits that the calling task is waiting for in the
+             * task's event list item so the kernel knows when a match is
+             * found.  Then enter the blocked state. */
+            vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+            /* This is obsolete as it will get set after the task unblocks, but
+             * some compilers mistakenly generate a warning about the variable
+             * being returned without being set if it is not done. */
+            uxReturn = 0;
+
+            traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+        }
+    }
+    xAlreadyYielded = xTaskResumeAll();
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        if( xAlreadyYielded == pdFALSE )
+        {
+            taskYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* The task blocked to wait for its required bits to be set - at this
+         * point either the required bits were set or the block time expired.  If
+         * the required bits were set they will have been stored in the task's
+         * event list item, and they should now be retrieved then cleared. */
+        uxReturn = uxTaskResetEventItemValue();
+
+        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+        {
+            taskENTER_CRITICAL();
+            {
+                /* The task timed out, just return the current event bit value. */
+                uxReturn = pxEventBits->uxEventBits;
+
+                /* It is possible that the event bits were updated between this
+                 * task leaving the Blocked state and running again. */
+                if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+                {
+                    if( xClearOnExit != pdFALSE )
+                    {
+                        pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xTimeoutOccurred = pdTRUE;
+            }
+            taskEXIT_CRITICAL();
+        }
+        else
+        {
+            /* The task unblocked because the bits were set. */
+        }
+
+        /* The task blocked so control bits may have been set. */
+        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+    }
+
+    traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xTimeoutOccurred;
+
+    traceRETURN_xEventGroupWaitBits( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                  const EventBits_t uxBitsToClear )
+{
+    EventGroup_t * pxEventBits = xEventGroup;
+    EventBits_t uxReturn;
+
+    traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear );
+
+    /* Check the user is not attempting to clear the bits used by the kernel
+     * itself. */
+    configASSERT( xEventGroup );
+    configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+    taskENTER_CRITICAL();
+    {
+        traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+        /* The value returned is the event group value prior to the bits being
+         * cleared. */
+        uxReturn = pxEventBits->uxEventBits;
+
+        /* Clear the bits. */
+        pxEventBits->uxEventBits &= ~uxBitsToClear;
+    }
+    taskEXIT_CRITICAL();
+
+    traceRETURN_xEventGroupClearBits( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToClear )
+    {
+        BaseType_t xReturn;
+
+        traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );
+
+        traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+        xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
+
+        traceRETURN_xEventGroupClearBitsFromISR( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+    UBaseType_t uxSavedInterruptStatus;
+    EventGroup_t const * const pxEventBits = xEventGroup;
+    EventBits_t uxReturn;
+
+    traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
+
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        uxReturn = pxEventBits->uxEventBits;
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xEventGroupGetBitsFromISR( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                const EventBits_t uxBitsToSet )
+{
+    ListItem_t * pxListItem;
+    ListItem_t * pxNext;
+    ListItem_t const * pxListEnd;
+    List_t const * pxList;
+    EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+    EventGroup_t * pxEventBits = xEventGroup;
+    BaseType_t xMatchFound = pdFALSE;
+
+    traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+    /* Check the user is not attempting to set the bits used by the kernel
+     * itself. */
+    configASSERT( xEventGroup );
+    configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+    pxList = &( pxEventBits->xTasksWaitingForBits );
+    pxListEnd = listGET_END_MARKER( pxList );
+    vTaskSuspendAll();
+    {
+        traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+        pxListItem = listGET_HEAD_ENTRY( pxList );
+
+        /* Set the bits. */
+        pxEventBits->uxEventBits |= uxBitsToSet;
+
+        /* See if the new bit value should unblock any tasks. */
+        while( pxListItem != pxListEnd )
+        {
+            pxNext = listGET_NEXT( pxListItem );
+            uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+            xMatchFound = pdFALSE;
+
+            /* Split the bits waited for from the control bits. */
+            uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+            uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+            if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+            {
+                /* Just looking for single bit being set. */
+                if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+                {
+                    xMatchFound = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+            {
+                /* All bits are set. */
+                xMatchFound = pdTRUE;
+            }
+            else
+            {
+                /* Need all bits to be set, but not all the bits were set. */
+            }
+
+            if( xMatchFound != pdFALSE )
+            {
+                /* The bits match.  Should the bits be cleared on exit? */
+                if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+                {
+                    uxBitsToClear |= uxBitsWaitedFor;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* Store the actual event flag value in the task's event list
+                 * item before removing the task from the event list.  The
+                 * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+                 * that is was unblocked due to its required bits matching, rather
+                 * than because it timed out. */
+                vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+            }
+
+            /* Move onto the next list item.  Note pxListItem->pxNext is not
+             * used here as the list item may have been removed from the event list
+             * and inserted into the ready/pending reading list. */
+            pxListItem = pxNext;
+        }
+
+        /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+         * bit was set in the control word. */
+        pxEventBits->uxEventBits &= ~uxBitsToClear;
+    }
+    ( void ) xTaskResumeAll();
+
+    traceRETURN_xEventGroupSetBits( pxEventBits->uxEventBits );
+
+    return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+    EventGroup_t * pxEventBits = xEventGroup;
+    const List_t * pxTasksWaitingForBits;
+
+    traceENTER_vEventGroupDelete( xEventGroup );
+
+    configASSERT( pxEventBits );
+
+    pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+    vTaskSuspendAll();
+    {
+        traceEVENT_GROUP_DELETE( xEventGroup );
+
+        while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+        {
+            /* Unblock the task, returning 0 as the event list is being deleted
+             * and cannot therefore have any bits set. */
+            configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+            vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+        }
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+    {
+        /* The event group can only have been allocated dynamically - free
+         * it again. */
+        vPortFree( pxEventBits );
+    }
+    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    {
+        /* The event group could have been allocated statically or
+         * dynamically, so check before attempting to free the memory. */
+        if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+        {
+            vPortFree( pxEventBits );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+    traceRETURN_vEventGroupDelete();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
+                                           StaticEventGroup_t ** ppxEventGroupBuffer )
+    {
+        BaseType_t xReturn;
+        EventGroup_t * pxEventBits = xEventGroup;
+
+        traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer );
+
+        configASSERT( pxEventBits );
+        configASSERT( ppxEventGroupBuffer );
+
+        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+        {
+            /* Check if the event group was statically allocated. */
+            if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
+            {
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
+                *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
+                xReturn = pdTRUE;
+            }
+            else
+            {
+                xReturn = pdFALSE;
+            }
+        }
+        #else /* configSUPPORT_DYNAMIC_ALLOCATION */
+        {
+            /* Event group must have been statically allocated. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
+            xReturn = pdTRUE;
+        }
+        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+        traceRETURN_xEventGroupGetStaticBuffer( xReturn );
+
+        return xReturn;
+    }
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+ * an interrupt. */
+void vEventGroupSetBitsCallback( void * pvEventGroup,
+                                 uint32_t ulBitsToSet )
+{
+    traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );
+
+    /* MISRA Ref 11.5.4 [Callback function parameter] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
+
+    traceRETURN_vEventGroupSetBitsCallback();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+ * an interrupt. */
+void vEventGroupClearBitsCallback( void * pvEventGroup,
+                                   uint32_t ulBitsToClear )
+{
+    traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );
+
+    /* MISRA Ref 11.5.4 [Callback function parameter] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
+
+    traceRETURN_vEventGroupClearBitsCallback();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+                                        const EventBits_t uxBitsToWaitFor,
+                                        const BaseType_t xWaitForAllBits )
+{
+    BaseType_t xWaitConditionMet = pdFALSE;
+
+    if( xWaitForAllBits == pdFALSE )
+    {
+        /* Task only has to wait for one bit within uxBitsToWaitFor to be
+         * set.  Is one already set? */
+        if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+        {
+            xWaitConditionMet = pdTRUE;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+         * Are they set already? */
+        if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+        {
+            xWaitConditionMet = pdTRUE;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToSet,
+                                          BaseType_t * pxHigherPriorityTaskWoken )
+    {
+        BaseType_t xReturn;
+
+        traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );
+
+        traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+        xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
+
+        traceRETURN_xEventGroupSetBitsFromISR( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
+    {
+        UBaseType_t xReturn;
+
+        /* MISRA Ref 11.5.2 [Opaque pointer] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup;
+
+        traceENTER_uxEventGroupGetNumber( xEventGroup );
+
+        if( xEventGroup == NULL )
+        {
+            xReturn = 0;
+        }
+        else
+        {
+            xReturn = pxEventBits->uxEventGroupNumber;
+        }
+
+        traceRETURN_uxEventGroupGetNumber( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vEventGroupSetNumber( void * xEventGroup,
+                               UBaseType_t uxEventGroupNumber )
+    {
+        traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber );
+
+        /* MISRA Ref 11.5.2 [Opaque pointer] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;
+
+        traceRETURN_vEventGroupSetNumber();
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/FreeRTOS.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/FreeRTOS.h
new file mode 100644
index 0000000000..321debf4c3
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/FreeRTOS.h
@@ -0,0 +1,3261 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+/*
+ * Include the generic headers required for the FreeRTOS port being used.
+ */
+#include <stddef.h>
+
+/*
+ * If stdint.h cannot be located then:
+ *   + If using GCC ensure the -nostdint options is *not* being used.
+ *   + Ensure the project's include path includes the directory in which your
+ *     compiler stores stdint.h.
+ *   + Set any compiler options necessary for it to support C99, as technically
+ *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
+ *     other way).
+ *   + The FreeRTOS download includes a simple stdint.h definition that can be
+ *     used in cases where none is provided by the compiler.  The files only
+ *     contains the typedefs required to build FreeRTOS.  Read the instructions
+ *     in FreeRTOS/source/stdint.readme for more information.
+ */
+#include <stdint.h> /* READ COMMENT ABOVE. */
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* Acceptable values for configTICK_TYPE_WIDTH_IN_BITS. */
+#define TICK_TYPE_WIDTH_16_BITS    0
+#define TICK_TYPE_WIDTH_32_BITS    1
+#define TICK_TYPE_WIDTH_64_BITS    2
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+#if !defined( configUSE_16_BIT_TICKS ) && !defined( configTICK_TYPE_WIDTH_IN_BITS )
+    #error Missing definition:  One of configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if defined( configUSE_16_BIT_TICKS ) && defined( configTICK_TYPE_WIDTH_IN_BITS )
+    #error Only one of configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+/* Define configTICK_TYPE_WIDTH_IN_BITS according to the
+ * value of configUSE_16_BIT_TICKS for backward compatibility. */
+#ifndef configTICK_TYPE_WIDTH_IN_BITS
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        #define configTICK_TYPE_WIDTH_IN_BITS    TICK_TYPE_WIDTH_16_BITS
+    #else
+        #define configTICK_TYPE_WIDTH_IN_BITS    TICK_TYPE_WIDTH_32_BITS
+    #endif
+#endif
+
+/* Set configUSE_MPU_WRAPPERS_V1 to 1 to use MPU wrappers v1. */
+#ifndef configUSE_MPU_WRAPPERS_V1
+    #define configUSE_MPU_WRAPPERS_V1    0
+#endif
+
+/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to enable access control list support. */
+#ifndef configENABLE_ACCESS_CONTROL_LIST
+    #define configENABLE_ACCESS_CONTROL_LIST    0
+#endif
+
+/* Set default value of configNUMBER_OF_CORES to 1 to use single core FreeRTOS. */
+#ifndef configNUMBER_OF_CORES
+    #define configNUMBER_OF_CORES    1
+#endif
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
+#ifndef configUSE_NEWLIB_REENTRANT
+    #define configUSE_NEWLIB_REENTRANT    0
+#endif
+
+/* Required if struct _reent is used. */
+#if ( configUSE_NEWLIB_REENTRANT == 1 )
+
+    #include "newlib-freertos.h"
+
+#endif /* if ( configUSE_NEWLIB_REENTRANT == 1 ) */
+
+/* Must be defaulted before configUSE_PICOLIBC_TLS is used below. */
+#ifndef configUSE_PICOLIBC_TLS
+    #define configUSE_PICOLIBC_TLS    0
+#endif
+
+#if ( configUSE_PICOLIBC_TLS == 1 )
+
+    #include "picolibc-freertos.h"
+
+#endif /* if ( configUSE_PICOLIBC_TLS == 1 ) */
+
+#ifndef configUSE_C_RUNTIME_TLS_SUPPORT
+    #define configUSE_C_RUNTIME_TLS_SUPPORT    0
+#endif
+
+#if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+
+    #ifndef configTLS_BLOCK_TYPE
+        #error Missing definition:  configTLS_BLOCK_TYPE must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+    #endif
+
+    #ifndef configINIT_TLS_BLOCK
+        #error Missing definition:  configINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+    #endif
+
+    #ifndef configSET_TLS_BLOCK
+        #error Missing definition:  configSET_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+    #endif
+
+    #ifndef configDEINIT_TLS_BLOCK
+        #error Missing definition:  configDEINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+    #endif
+#endif /* if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) */
+
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+    #error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+    #error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if configMAX_PRIORITIES < 1
+    #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef configUSE_PREEMPTION
+    #error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+    #error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if ( configNUMBER_OF_CORES > 1 )
+    #ifndef configUSE_PASSIVE_IDLE_HOOK
+        #error Missing definition:  configUSE_PASSIVE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+    #endif
+#endif
+
+#ifndef configUSE_TICK_HOOK
+    #error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if ( ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_16_BITS ) && \
+    ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_32_BITS ) &&   \
+    ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_64_BITS ) )
+    #error Macro configTICK_TYPE_WIDTH_IN_BITS is defined to incorrect value.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+    #define configUSE_CO_ROUTINES    0
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+    #define INCLUDE_vTaskPrioritySet    0
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+    #define INCLUDE_uxTaskPriorityGet    0
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+    #define INCLUDE_vTaskDelete    0
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+    #define INCLUDE_vTaskSuspend    0
+#endif
+
+#ifdef INCLUDE_xTaskDelayUntil
+    #ifdef INCLUDE_vTaskDelayUntil
+
+/* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil.  Backward
+ * compatibility is maintained if only one or the other is defined, but
+ * there is a conflict if both are defined. */
+        #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined.  INCLUDE_vTaskDelayUntil is no longer required and should be removed
+    #endif
+#endif
+
+#ifndef INCLUDE_xTaskDelayUntil
+    #ifdef INCLUDE_vTaskDelayUntil
+
+/* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then
+ * the project's FreeRTOSConfig.h probably pre-dates the introduction of
+ * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever
+ * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility.
+ */
+        #define INCLUDE_xTaskDelayUntil    INCLUDE_vTaskDelayUntil
+    #endif
+#endif
+
+#ifndef INCLUDE_xTaskDelayUntil
+    #define INCLUDE_xTaskDelayUntil    0
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+    #define INCLUDE_vTaskDelay    0
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+    #define INCLUDE_xTaskGetIdleTaskHandle    0
+#endif
+
+#ifndef INCLUDE_xTaskAbortDelay
+    #define INCLUDE_xTaskAbortDelay    0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+    #define INCLUDE_xQueueGetMutexHolder    0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+    #define INCLUDE_xSemaphoreGetMutexHolder    INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_xTaskGetHandle
+    #define INCLUDE_xTaskGetHandle    0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+    #define INCLUDE_uxTaskGetStackHighWaterMark    0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+    #define INCLUDE_uxTaskGetStackHighWaterMark2    0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+    #define INCLUDE_eTaskGetState    0
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+    #define INCLUDE_xTaskResumeFromISR    1
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+    #define INCLUDE_xTimerPendFunctionCall    0
+#endif
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+    #define INCLUDE_xTaskGetSchedulerState    0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+    #define INCLUDE_xTaskGetCurrentTaskHandle    1
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+    #ifndef configMAX_CO_ROUTINE_PRIORITIES
+        #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+    #endif
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+    #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+    #define configUSE_APPLICATION_TASK_TAG    0
+#endif
+
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+    #define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+    #define configUSE_RECURSIVE_MUTEXES    0
+#endif
+
+#ifndef configUSE_MUTEXES
+    #define configUSE_MUTEXES    0
+#endif
+
+#ifndef configUSE_TIMERS
+    #define configUSE_TIMERS    0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+    #define configUSE_COUNTING_SEMAPHORES    0
+#endif
+
+#ifndef configUSE_TASK_PREEMPTION_DISABLE
+    #define configUSE_TASK_PREEMPTION_DISABLE    0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+    #define configUSE_ALTERNATIVE_API    0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+    #define portCRITICAL_NESTING_IN_TCB    0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+    #define configMAX_TASK_NAME_LEN    16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+    #define configIDLE_SHOULD_YIELD    1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+    #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef configASSERT
+    #define configASSERT( x )
+    #define configASSERT_DEFINED    0
+#else
+    #define configASSERT_DEFINED    1
+#endif
+
+/* configPRECONDITION should be defined as configASSERT.
+ * The CBMC proofs need a way to track assumptions and assertions.
+ * A configPRECONDITION statement should express an implicit invariant or
+ * assumption made.  A configASSERT statement should express an invariant that must
+ * hold explicit before calling the code. */
+#ifndef configPRECONDITION
+    #define configPRECONDITION( X )    configASSERT( X )
+    #define configPRECONDITION_DEFINED    0
+#else
+    #define configPRECONDITION_DEFINED    1
+#endif
+
+#ifndef configCHECK_HANDLER_INSTALLATION
+    #define configCHECK_HANDLER_INSTALLATION    1
+#else
+
+/* The application has explicitly defined configCHECK_HANDLER_INSTALLATION
+ * to 1. The checks requires configASSERT() to be defined. */
+    #if ( ( configCHECK_HANDLER_INSTALLATION == 1 ) && ( configASSERT_DEFINED == 0 ) )
+        #error You must define configASSERT() when configCHECK_HANDLER_INSTALLATION is 1.
+    #endif
+#endif
+
+#ifndef portMEMORY_BARRIER
+    #define portMEMORY_BARRIER()
+#endif
+
+#ifndef portSOFTWARE_BARRIER
+    #define portSOFTWARE_BARRIER()
+#endif
+
+#ifndef configRUN_MULTIPLE_PRIORITIES
+    #define configRUN_MULTIPLE_PRIORITIES    0
+#endif
+
+#ifndef portGET_CORE_ID
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_CORE_ID()    0
+    #else
+        #error configNUMBER_OF_CORES is set to more than 1 then portGET_CORE_ID must also be defined.
+    #endif /* configNUMBER_OF_CORES */
+
+#endif /* portGET_CORE_ID */
+
+#ifndef portYIELD_CORE
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portYIELD_CORE( x )    portYIELD()
+    #else
+        #error configNUMBER_OF_CORES is set to more than 1 then portYIELD_CORE must also be defined.
+    #endif /* configNUMBER_OF_CORES */
+
+#endif /* portYIELD_CORE */
+
+#ifndef portSET_INTERRUPT_MASK
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portSET_INTERRUPT_MASK is required in SMP
+    #endif
+
+#endif /* portSET_INTERRUPT_MASK */
+
+#ifndef portCLEAR_INTERRUPT_MASK
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portCLEAR_INTERRUPT_MASK is required in SMP
+    #endif
+
+#endif /* portCLEAR_INTERRUPT_MASK */
+
+#ifndef portRELEASE_TASK_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portRELEASE_TASK_LOCK()
+    #else
+        #error portRELEASE_TASK_LOCK is required in SMP
+    #endif
+
+#endif /* portRELEASE_TASK_LOCK */
+
+#ifndef portGET_TASK_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_TASK_LOCK()
+    #else
+        #error portGET_TASK_LOCK is required in SMP
+    #endif
+
+#endif /* portGET_TASK_LOCK */
+
+#ifndef portRELEASE_ISR_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portRELEASE_ISR_LOCK()
+    #else
+        #error portRELEASE_ISR_LOCK is required in SMP
+    #endif
+
+#endif /* portRELEASE_ISR_LOCK */
+
+#ifndef portGET_ISR_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_ISR_LOCK()
+    #else
+        #error portGET_ISR_LOCK is required in SMP
+    #endif
+
+#endif /* portGET_ISR_LOCK */
+
+#ifndef portENTER_CRITICAL_FROM_ISR
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portENTER_CRITICAL_FROM_ISR is required in SMP
+    #endif
+
+#endif
+
+#ifndef portEXIT_CRITICAL_FROM_ISR
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portEXIT_CRITICAL_FROM_ISR is required in SMP
+    #endif
+
+#endif
+
+#ifndef configUSE_CORE_AFFINITY
+    #define configUSE_CORE_AFFINITY    0
+#endif /* configUSE_CORE_AFFINITY */
+
+#ifndef configUSE_PASSIVE_IDLE_HOOK
+    #define configUSE_PASSIVE_IDLE_HOOK    0
+#endif /* configUSE_PASSIVE_IDLE_HOOK */
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+    #ifndef configTIMER_TASK_PRIORITY
+        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+    #endif /* configTIMER_TASK_PRIORITY */
+
+    #ifndef configTIMER_QUEUE_LENGTH
+        #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+    #endif /* configTIMER_QUEUE_LENGTH */
+
+    #ifndef configTIMER_TASK_STACK_DEPTH
+        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+    #endif /* configTIMER_TASK_STACK_DEPTH */
+
+    #ifndef portTIMER_CALLBACK_ATTRIBUTE
+        #define portTIMER_CALLBACK_ATTRIBUTE
+    #endif /* portTIMER_CALLBACK_ATTRIBUTE */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+    #define portSET_INTERRUPT_MASK_FROM_ISR()    0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) ( uxSavedStatusValue )
+#endif
+
+#ifndef portCLEAN_UP_TCB
+    #define portCLEAN_UP_TCB( pxTCB )    ( void ) ( pxTCB )
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+    #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+    #define portSETUP_TCB( pxTCB )    ( void ) ( pxTCB )
+#endif
+
+#ifndef portTASK_SWITCH_HOOK
+    #define portTASK_SWITCH_HOOK( pxTCB )    ( void ) ( pxTCB )
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+    #define configQUEUE_REGISTRY_SIZE    0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+    #define vQueueAddToRegistry( xQueue, pcName )
+    #define vQueueUnregisterQueue( xQueue )
+    #define pcQueueGetName( xQueue )
+#endif
+
+#ifndef configUSE_MINI_LIST_ITEM
+    #define configUSE_MINI_LIST_ITEM    1
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+    #define portPOINTER_SIZE_TYPE    uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+
+/* Used to perform any necessary initialisation - for example, open a file
+ * into which trace is to be written. */
+    #define traceSTART()
+#endif
+
+#ifndef traceEND
+
+/* Use to close a trace, for example close a file into which trace has been
+ * written. */
+    #define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+
+/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
+ * to the task control block of the selected task. */
+    #define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+
+/* Called before stepping the tick count after waking from tickless idle
+ * sleep. */
+    #define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+    /* Called immediately before entering tickless idle. */
+    #define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef traceLOW_POWER_IDLE_END
+    /* Called when returning to the Idle task after a tickless idle. */
+    #define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+
+/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
+ * to the task control block of the task being switched out. */
+    #define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+
+/* Called when a task attempts to take a mutex that is already held by a
+ * lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
+ * that holds the mutex.  uxInheritedPriority is the priority the mutex holder
+ * will inherit (the priority of the task that is attempting to obtain the
+ * muted. */
+    #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+
+/* Called when a task releases a mutex, the holding of which had resulted in
+ * the task inheriting the priority of a higher priority task.
+ * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+ * mutex.  uxOriginalPriority is the task's configured (base) priority. */
+    #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+
+/* Task is about to block because it cannot read from a
+ * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+ * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+ * task that attempted the read. */
+    #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_PEEK
+
+/* Task is about to block because it cannot read from a
+ * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+ * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+ * task that attempted the read. */
+    #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+
+/* Task is about to block because it cannot write to a
+ * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+ * upon which the write was attempted.  pxCurrentTCB points to the TCB of the
+ * task that attempted the write. */
+    #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+    #define configCHECK_FOR_STACK_OVERFLOW    0
+#endif
+
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+    #define configRECORD_STACK_HIGH_ADDRESS    0
+#endif
+
+#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
+    #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H    0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+    #define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
+    #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceMOVED_TASK_TO_DELAYED_LIST
+    #define traceMOVED_TASK_TO_DELAYED_LIST()
+#endif
+
+#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST
+    #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST()
+#endif
+
+#ifndef traceQUEUE_CREATE
+    #define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+    #define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+    #define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+    #define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+    #define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+    #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+    #define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+    #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+    #define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+    #define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SET_SEND
+    #define traceQUEUE_SET_SEND    traceQUEUE_SEND
+#endif
+
+#ifndef traceQUEUE_SEND
+    #define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+    #define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+    #define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+    #define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FAILED
+    #define traceQUEUE_PEEK_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+    #define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+    #define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+    #define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+    #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+    #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+    #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+    #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+    #define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+    #define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+    #define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+    #define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+    #define traceTASK_DELAY_UNTIL( x )
+#endif
+
+#ifndef traceTASK_DELAY
+    #define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+    #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+    #define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+    #define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+    #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+    #define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+    #define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+    #define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+    #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+    #define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+    #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+    #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+    #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+    #define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+    #define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+    #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+    #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) ( xTimeoutOccurred )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+    #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+    #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) ( xTimeoutOccurred )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+    #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+    #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+    #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+    #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+    #define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+    #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret )
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+    #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret )
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+    #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName )
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE_BLOCK
+    #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE
+    #define traceTASK_NOTIFY_TAKE( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT_BLOCK
+    #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT
+    #define traceTASK_NOTIFY_WAIT( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY
+    #define traceTASK_NOTIFY( uxIndexToNotify )
+#endif
+
+#ifndef traceTASK_NOTIFY_FROM_ISR
+    #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify )
+#endif
+
+#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
+    #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify )
+#endif
+
+#ifndef traceISR_EXIT_TO_SCHEDULER
+    #define traceISR_EXIT_TO_SCHEDULER()
+#endif
+
+#ifndef traceISR_EXIT
+    #define traceISR_EXIT()
+#endif
+
+#ifndef traceISR_ENTER
+    #define traceISR_ENTER()
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_FAILED
+    #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
+    #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE
+    #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_DELETE
+    #define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RESET
+    #define traceSTREAM_BUFFER_RESET( xStreamBuffer )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
+    #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND
+    #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FAILED
+    #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
+    #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
+    #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE
+    #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
+    #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
+    #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef traceENTER_xEventGroupCreateStatic
+    #define traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer )
+#endif
+
+#ifndef traceRETURN_xEventGroupCreateStatic
+    #define traceRETURN_xEventGroupCreateStatic( pxEventBits )
+#endif
+
+#ifndef traceENTER_xEventGroupCreate
+    #define traceENTER_xEventGroupCreate()
+#endif
+
+#ifndef traceRETURN_xEventGroupCreate
+    #define traceRETURN_xEventGroupCreate( pxEventBits )
+#endif
+
+#ifndef traceENTER_xEventGroupSync
+    #define traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xEventGroupSync
+    #define traceRETURN_xEventGroupSync( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupWaitBits
+    #define traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xEventGroupWaitBits
+    #define traceRETURN_xEventGroupWaitBits( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupClearBits
+    #define traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceRETURN_xEventGroupClearBits
+    #define traceRETURN_xEventGroupClearBits( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupClearBitsFromISR
+    #define traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceRETURN_xEventGroupClearBitsFromISR
+    #define traceRETURN_xEventGroupClearBitsFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupGetBitsFromISR
+    #define traceENTER_xEventGroupGetBitsFromISR( xEventGroup )
+#endif
+
+#ifndef traceRETURN_xEventGroupGetBitsFromISR
+    #define traceRETURN_xEventGroupGetBitsFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupSetBits
+    #define traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceRETURN_xEventGroupSetBits
+    #define traceRETURN_xEventGroupSetBits( uxEventBits )
+#endif
+
+#ifndef traceENTER_vEventGroupDelete
+    #define traceENTER_vEventGroupDelete( xEventGroup )
+#endif
+
+#ifndef traceRETURN_vEventGroupDelete
+    #define traceRETURN_vEventGroupDelete()
+#endif
+
+#ifndef traceENTER_xEventGroupGetStaticBuffer
+    #define traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer )
+#endif
+
+#ifndef traceRETURN_xEventGroupGetStaticBuffer
+    #define traceRETURN_xEventGroupGetStaticBuffer( xReturn )
+#endif
+
+#ifndef traceENTER_vEventGroupSetBitsCallback
+    #define traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet )
+#endif
+
+#ifndef traceRETURN_vEventGroupSetBitsCallback
+    #define traceRETURN_vEventGroupSetBitsCallback()
+#endif
+
+#ifndef traceENTER_vEventGroupClearBitsCallback
+    #define traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear )
+#endif
+
+#ifndef traceRETURN_vEventGroupClearBitsCallback
+    #define traceRETURN_vEventGroupClearBitsCallback()
+#endif
+
+#ifndef traceENTER_xEventGroupSetBitsFromISR
+    #define traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xEventGroupSetBitsFromISR
+    #define traceRETURN_xEventGroupSetBitsFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxEventGroupGetNumber
+    #define traceENTER_uxEventGroupGetNumber( xEventGroup )
+#endif
+
+#ifndef traceRETURN_uxEventGroupGetNumber
+    #define traceRETURN_uxEventGroupGetNumber( xReturn )
+#endif
+
+#ifndef traceENTER_vEventGroupSetNumber
+    #define traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber )
+#endif
+
+#ifndef traceRETURN_vEventGroupSetNumber
+    #define traceRETURN_vEventGroupSetNumber()
+#endif
+
+#ifndef traceENTER_xQueueGenericReset
+    #define traceENTER_xQueueGenericReset( xQueue, xNewQueue )
+#endif
+
+#ifndef traceRETURN_xQueueGenericReset
+    #define traceRETURN_xQueueGenericReset( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericCreateStatic
+    #define traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueGenericCreateStatic
+    #define traceRETURN_xQueueGenericCreateStatic( pxNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueGenericGetStaticBuffers
+    #define traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueGenericGetStaticBuffers
+    #define traceRETURN_xQueueGenericGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericCreate
+    #define traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueGenericCreate
+    #define traceRETURN_xQueueGenericCreate( pxNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueCreateMutex
+    #define traceENTER_xQueueCreateMutex( ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueCreateMutex
+    #define traceRETURN_xQueueCreateMutex( xNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueCreateMutexStatic
+    #define traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueCreateMutexStatic
+    #define traceRETURN_xQueueCreateMutexStatic( xNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueGetMutexHolder
+    #define traceENTER_xQueueGetMutexHolder( xSemaphore )
+#endif
+
+#ifndef traceRETURN_xQueueGetMutexHolder
+    #define traceRETURN_xQueueGetMutexHolder( pxReturn )
+#endif
+
+#ifndef traceENTER_xQueueGetMutexHolderFromISR
+    #define traceENTER_xQueueGetMutexHolderFromISR( xSemaphore )
+#endif
+
+#ifndef traceRETURN_xQueueGetMutexHolderFromISR
+    #define traceRETURN_xQueueGetMutexHolderFromISR( pxReturn )
+#endif
+
+#ifndef traceENTER_xQueueGiveMutexRecursive
+    #define traceENTER_xQueueGiveMutexRecursive( xMutex )
+#endif
+
+#ifndef traceRETURN_xQueueGiveMutexRecursive
+    #define traceRETURN_xQueueGiveMutexRecursive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueTakeMutexRecursive
+    #define traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueTakeMutexRecursive
+    #define traceRETURN_xQueueTakeMutexRecursive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCreateCountingSemaphoreStatic
+    #define traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueCreateCountingSemaphoreStatic
+    #define traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle )
+#endif
+
+#ifndef traceENTER_xQueueCreateCountingSemaphore
+    #define traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount )
+#endif
+
+#ifndef traceRETURN_xQueueCreateCountingSemaphore
+    #define traceRETURN_xQueueCreateCountingSemaphore( xHandle )
+#endif
+
+#ifndef traceENTER_xQueueGenericSend
+    #define traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition )
+#endif
+
+#ifndef traceRETURN_xQueueGenericSend
+    #define traceRETURN_xQueueGenericSend( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericSendFromISR
+    #define traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition )
+#endif
+
+#ifndef traceRETURN_xQueueGenericSendFromISR
+    #define traceRETURN_xQueueGenericSendFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGiveFromISR
+    #define traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xQueueGiveFromISR
+    #define traceRETURN_xQueueGiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueReceive
+    #define traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueReceive
+    #define traceRETURN_xQueueReceive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSemaphoreTake
+    #define traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueSemaphoreTake
+    #define traceRETURN_xQueueSemaphoreTake( xReturn )
+#endif
+
+#ifndef traceENTER_xQueuePeek
+    #define traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueuePeek
+    #define traceRETURN_xQueuePeek( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueReceiveFromISR
+    #define traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xQueueReceiveFromISR
+    #define traceRETURN_xQueueReceiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueuePeekFromISR
+    #define traceENTER_xQueuePeekFromISR( xQueue, pvBuffer )
+#endif
+
+#ifndef traceRETURN_xQueuePeekFromISR
+    #define traceRETURN_xQueuePeekFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxQueueMessagesWaiting
+    #define traceENTER_uxQueueMessagesWaiting( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueMessagesWaiting
+    #define traceRETURN_uxQueueMessagesWaiting( uxReturn )
+#endif
+
+#ifndef traceENTER_uxQueueSpacesAvailable
+    #define traceENTER_uxQueueSpacesAvailable( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueSpacesAvailable
+    #define traceRETURN_uxQueueSpacesAvailable( uxReturn )
+#endif
+
+#ifndef traceENTER_uxQueueMessagesWaitingFromISR
+    #define traceENTER_uxQueueMessagesWaitingFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueMessagesWaitingFromISR
+    #define traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_vQueueDelete
+    #define traceENTER_vQueueDelete( xQueue )
+#endif
+
+#ifndef traceRETURN_vQueueDelete
+    #define traceRETURN_vQueueDelete()
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueNumber
+    #define traceENTER_uxQueueGetQueueNumber( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueNumber
+    #define traceRETURN_uxQueueGetQueueNumber( uxQueueNumber )
+#endif
+
+#ifndef traceENTER_vQueueSetQueueNumber
+    #define traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber )
+#endif
+
+#ifndef traceRETURN_vQueueSetQueueNumber
+    #define traceRETURN_vQueueSetQueueNumber()
+#endif
+
+#ifndef traceENTER_ucQueueGetQueueType
+    #define traceENTER_ucQueueGetQueueType( xQueue )
+#endif
+
+#ifndef traceRETURN_ucQueueGetQueueType
+    #define traceRETURN_ucQueueGetQueueType( ucQueueType )
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueItemSize
+    #define traceENTER_uxQueueGetQueueItemSize( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueItemSize
+    #define traceRETURN_uxQueueGetQueueItemSize( uxItemSize )
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueLength
+    #define traceENTER_uxQueueGetQueueLength( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueLength
+    #define traceRETURN_uxQueueGetQueueLength( uxLength )
+#endif
+
+#ifndef traceENTER_xQueueIsQueueEmptyFromISR
+    #define traceENTER_xQueueIsQueueEmptyFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_xQueueIsQueueEmptyFromISR
+    #define traceRETURN_xQueueIsQueueEmptyFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueIsQueueFullFromISR
+    #define traceENTER_xQueueIsQueueFullFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_xQueueIsQueueFullFromISR
+    #define traceRETURN_xQueueIsQueueFullFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRSend
+    #define traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueCRSend
+    #define traceRETURN_xQueueCRSend( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRReceive
+    #define traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueCRReceive
+    #define traceRETURN_xQueueCRReceive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRSendFromISR
+    #define traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken )
+#endif
+
+#ifndef traceRETURN_xQueueCRSendFromISR
+    #define traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken )
+#endif
+
+#ifndef traceENTER_xQueueCRReceiveFromISR
+    #define traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken )
+#endif
+
+#ifndef traceRETURN_xQueueCRReceiveFromISR
+    #define traceRETURN_xQueueCRReceiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_vQueueAddToRegistry
+    #define traceENTER_vQueueAddToRegistry( xQueue, pcQueueName )
+#endif
+
+#ifndef traceRETURN_vQueueAddToRegistry
+    #define traceRETURN_vQueueAddToRegistry()
+#endif
+
+#ifndef traceENTER_pcQueueGetName
+    #define traceENTER_pcQueueGetName( xQueue )
+#endif
+
+#ifndef traceRETURN_pcQueueGetName
+    #define traceRETURN_pcQueueGetName( pcReturn )
+#endif
+
+#ifndef traceENTER_vQueueUnregisterQueue
+    #define traceENTER_vQueueUnregisterQueue( xQueue )
+#endif
+
+#ifndef traceRETURN_vQueueUnregisterQueue
+    #define traceRETURN_vQueueUnregisterQueue()
+#endif
+
+#ifndef traceENTER_vQueueWaitForMessageRestricted
+    #define traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely )
+#endif
+
+#ifndef traceRETURN_vQueueWaitForMessageRestricted
+    #define traceRETURN_vQueueWaitForMessageRestricted()
+#endif
+
+#ifndef traceENTER_xQueueCreateSet
+    #define traceENTER_xQueueCreateSet( uxEventQueueLength )
+#endif
+
+#ifndef traceRETURN_xQueueCreateSet
+    #define traceRETURN_xQueueCreateSet( pxQueue )
+#endif
+
+#ifndef traceENTER_xQueueAddToSet
+    #define traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueAddToSet
+    #define traceRETURN_xQueueAddToSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueRemoveFromSet
+    #define traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueRemoveFromSet
+    #define traceRETURN_xQueueRemoveFromSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSelectFromSet
+    #define traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueSelectFromSet
+    #define traceRETURN_xQueueSelectFromSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSelectFromSetFromISR
+    #define traceENTER_xQueueSelectFromSetFromISR( xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueSelectFromSetFromISR
+    #define traceRETURN_xQueueSelectFromSetFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerCreateTimerTask
+    #define traceENTER_xTimerCreateTimerTask()
+#endif
+
+#ifndef traceRETURN_xTimerCreateTimerTask
+    #define traceRETURN_xTimerCreateTimerTask( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerCreate
+    #define traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction )
+#endif
+
+#ifndef traceRETURN_xTimerCreate
+    #define traceRETURN_xTimerCreate( pxNewTimer )
+#endif
+
+#ifndef traceENTER_xTimerCreateStatic
+    #define traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer )
+#endif
+
+#ifndef traceRETURN_xTimerCreateStatic
+    #define traceRETURN_xTimerCreateStatic( pxNewTimer )
+#endif
+
+#ifndef traceENTER_xTimerGenericCommandFromTask
+    #define traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerGenericCommandFromTask
+    #define traceRETURN_xTimerGenericCommandFromTask( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGenericCommandFromISR
+    #define traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerGenericCommandFromISR
+    #define traceRETURN_xTimerGenericCommandFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetTimerDaemonTaskHandle
+    #define traceENTER_xTimerGetTimerDaemonTaskHandle()
+#endif
+
+#ifndef traceRETURN_xTimerGetTimerDaemonTaskHandle
+    #define traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle )
+#endif
+
+#ifndef traceENTER_xTimerGetPeriod
+    #define traceENTER_xTimerGetPeriod( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetPeriod
+    #define traceRETURN_xTimerGetPeriod( xTimerPeriodInTicks )
+#endif
+
+#ifndef traceENTER_vTimerSetReloadMode
+    #define traceENTER_vTimerSetReloadMode( xTimer, xAutoReload )
+#endif
+
+#ifndef traceRETURN_vTimerSetReloadMode
+    #define traceRETURN_vTimerSetReloadMode()
+#endif
+
+#ifndef traceENTER_xTimerGetReloadMode
+    #define traceENTER_xTimerGetReloadMode( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetReloadMode
+    #define traceRETURN_xTimerGetReloadMode( xReturn )
+#endif
+
+#ifndef traceENTER_uxTimerGetReloadMode
+    #define traceENTER_uxTimerGetReloadMode( xTimer )
+#endif
+
+#ifndef traceRETURN_uxTimerGetReloadMode
+    #define traceRETURN_uxTimerGetReloadMode( uxReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetExpiryTime
+    #define traceENTER_xTimerGetExpiryTime( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetExpiryTime
+    #define traceRETURN_xTimerGetExpiryTime( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetStaticBuffer
+    #define traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer )
+#endif
+
+#ifndef traceRETURN_xTimerGetStaticBuffer
+    #define traceRETURN_xTimerGetStaticBuffer( xReturn )
+#endif
+
+#ifndef traceENTER_pcTimerGetName
+    #define traceENTER_pcTimerGetName( xTimer )
+#endif
+
+#ifndef traceRETURN_pcTimerGetName
+    #define traceRETURN_pcTimerGetName( pcTimerName )
+#endif
+
+#ifndef traceENTER_xTimerIsTimerActive
+    #define traceENTER_xTimerIsTimerActive( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerIsTimerActive
+    #define traceRETURN_xTimerIsTimerActive( xReturn )
+#endif
+
+#ifndef traceENTER_pvTimerGetTimerID
+    #define traceENTER_pvTimerGetTimerID( xTimer )
+#endif
+
+#ifndef traceRETURN_pvTimerGetTimerID
+    #define traceRETURN_pvTimerGetTimerID( pvReturn )
+#endif
+
+#ifndef traceENTER_vTimerSetTimerID
+    #define traceENTER_vTimerSetTimerID( xTimer, pvNewID )
+#endif
+
+#ifndef traceRETURN_vTimerSetTimerID
+    #define traceRETURN_vTimerSetTimerID()
+#endif
+
+#ifndef traceENTER_xTimerPendFunctionCallFromISR
+    #define traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xTimerPendFunctionCallFromISR
+    #define traceRETURN_xTimerPendFunctionCallFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerPendFunctionCall
+    #define traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerPendFunctionCall
+    #define traceRETURN_xTimerPendFunctionCall( xReturn )
+#endif
+
+#ifndef traceENTER_uxTimerGetTimerNumber
+    #define traceENTER_uxTimerGetTimerNumber( xTimer )
+#endif
+
+#ifndef traceRETURN_uxTimerGetTimerNumber
+    #define traceRETURN_uxTimerGetTimerNumber( uxTimerNumber )
+#endif
+
+#ifndef traceENTER_vTimerSetTimerNumber
+    #define traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber )
+#endif
+
+#ifndef traceRETURN_vTimerSetTimerNumber
+    #define traceRETURN_vTimerSetTimerNumber()
+#endif
+
+#ifndef traceENTER_xTaskCreateStatic
+    #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer )
+#endif
+
+#ifndef traceRETURN_xTaskCreateStatic
+    #define traceRETURN_xTaskCreateStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateStaticAffinitySet
+    #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateStaticAffinitySet
+    #define traceRETURN_xTaskCreateStaticAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestrictedStatic
+    #define traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedStatic
+    #define traceRETURN_xTaskCreateRestrictedStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestrictedStaticAffinitySet
+    #define traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedStaticAffinitySet
+    #define traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestricted
+    #define traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestricted
+    #define traceRETURN_xTaskCreateRestricted( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestrictedAffinitySet
+    #define traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedAffinitySet
+    #define traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreate
+    #define traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreate
+    #define traceRETURN_xTaskCreate( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateAffinitySet
+    #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateAffinitySet
+    #define traceRETURN_xTaskCreateAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskDelete
+    #define traceENTER_vTaskDelete( xTaskToDelete )
+#endif
+
+#ifndef traceRETURN_vTaskDelete
+    #define traceRETURN_vTaskDelete()
+#endif
+
+#ifndef traceENTER_xTaskDelayUntil
+    #define traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )
+#endif
+
+#ifndef traceRETURN_xTaskDelayUntil
+    #define traceRETURN_xTaskDelayUntil( xShouldDelay )
+#endif
+
+#ifndef traceENTER_vTaskDelay
+    #define traceENTER_vTaskDelay( xTicksToDelay )
+#endif
+
+#ifndef traceRETURN_vTaskDelay
+    #define traceRETURN_vTaskDelay()
+#endif
+
+#ifndef traceENTER_eTaskGetState
+    #define traceENTER_eTaskGetState( xTask )
+#endif
+
+#ifndef traceRETURN_eTaskGetState
+    #define traceRETURN_eTaskGetState( eReturn )
+#endif
+
+#ifndef traceENTER_uxTaskPriorityGet
+    #define traceENTER_uxTaskPriorityGet( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskPriorityGet
+    #define traceRETURN_uxTaskPriorityGet( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskPriorityGetFromISR
+    #define traceENTER_uxTaskPriorityGetFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskPriorityGetFromISR
+    #define traceRETURN_uxTaskPriorityGetFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskBasePriorityGet
+    #define traceENTER_uxTaskBasePriorityGet( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskBasePriorityGet
+    #define traceRETURN_uxTaskBasePriorityGet( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskBasePriorityGetFromISR
+    #define traceENTER_uxTaskBasePriorityGetFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskBasePriorityGetFromISR
+    #define traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_vTaskPrioritySet
+    #define traceENTER_vTaskPrioritySet( xTask, uxNewPriority )
+#endif
+
+#ifndef traceRETURN_vTaskPrioritySet
+    #define traceRETURN_vTaskPrioritySet()
+#endif
+
+#ifndef traceENTER_vTaskCoreAffinitySet
+    #define traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask )
+#endif
+
+#ifndef traceRETURN_vTaskCoreAffinitySet
+    #define traceRETURN_vTaskCoreAffinitySet()
+#endif
+
+#ifndef traceENTER_vTaskCoreAffinityGet
+    #define traceENTER_vTaskCoreAffinityGet( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskCoreAffinityGet
+    #define traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask )
+#endif
+
+#ifndef traceENTER_vTaskPreemptionDisable
+    #define traceENTER_vTaskPreemptionDisable( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskPreemptionDisable
+    #define traceRETURN_vTaskPreemptionDisable()
+#endif
+
+#ifndef traceENTER_vTaskPreemptionEnable
+    #define traceENTER_vTaskPreemptionEnable( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskPreemptionEnable
+    #define traceRETURN_vTaskPreemptionEnable()
+#endif
+
+#ifndef traceENTER_vTaskSuspend
+    #define traceENTER_vTaskSuspend( xTaskToSuspend )
+#endif
+
+#ifndef traceRETURN_vTaskSuspend
+    #define traceRETURN_vTaskSuspend()
+#endif
+
+#ifndef traceENTER_vTaskResume
+    #define traceENTER_vTaskResume( xTaskToResume )
+#endif
+
+#ifndef traceRETURN_vTaskResume
+    #define traceRETURN_vTaskResume()
+#endif
+
+#ifndef traceENTER_xTaskResumeFromISR
+    #define traceENTER_xTaskResumeFromISR( xTaskToResume )
+#endif
+
+#ifndef traceRETURN_xTaskResumeFromISR
+    #define traceRETURN_xTaskResumeFromISR( xYieldRequired )
+#endif
+
+#ifndef traceENTER_vTaskStartScheduler
+    #define traceENTER_vTaskStartScheduler()
+#endif
+
+#ifndef traceRETURN_vTaskStartScheduler
+    #define traceRETURN_vTaskStartScheduler()
+#endif
+
+#ifndef traceENTER_vTaskEndScheduler
+    #define traceENTER_vTaskEndScheduler()
+#endif
+
+#ifndef traceRETURN_vTaskEndScheduler
+    #define traceRETURN_vTaskEndScheduler()
+#endif
+
+#ifndef traceENTER_vTaskSuspendAll
+    #define traceENTER_vTaskSuspendAll()
+#endif
+
+#ifndef traceRETURN_vTaskSuspendAll
+    #define traceRETURN_vTaskSuspendAll()
+#endif
+
+#ifndef traceENTER_xTaskResumeAll
+    #define traceENTER_xTaskResumeAll()
+#endif
+
+#ifndef traceRETURN_xTaskResumeAll
+    #define traceRETURN_xTaskResumeAll( xAlreadyYielded )
+#endif
+
+#ifndef traceENTER_xTaskGetTickCount
+    #define traceENTER_xTaskGetTickCount()
+#endif
+
+#ifndef traceRETURN_xTaskGetTickCount
+    #define traceRETURN_xTaskGetTickCount( xTicks )
+#endif
+
+#ifndef traceENTER_xTaskGetTickCountFromISR
+    #define traceENTER_xTaskGetTickCountFromISR()
+#endif
+
+#ifndef traceRETURN_xTaskGetTickCountFromISR
+    #define traceRETURN_xTaskGetTickCountFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetNumberOfTasks
+    #define traceENTER_uxTaskGetNumberOfTasks()
+#endif
+
+#ifndef traceRETURN_uxTaskGetNumberOfTasks
+    #define traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks )
+#endif
+
+#ifndef traceENTER_pcTaskGetName
+    #define traceENTER_pcTaskGetName( xTaskToQuery )
+#endif
+
+#ifndef traceRETURN_pcTaskGetName
+    #define traceRETURN_pcTaskGetName( pcTaskName )
+#endif
+
+#ifndef traceENTER_xTaskGetHandle
+    #define traceENTER_xTaskGetHandle( pcNameToQuery )
+#endif
+
+#ifndef traceRETURN_xTaskGetHandle
+    #define traceRETURN_xTaskGetHandle( pxTCB )
+#endif
+
+#ifndef traceENTER_xTaskGetStaticBuffers
+    #define traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer )
+#endif
+
+#ifndef traceRETURN_xTaskGetStaticBuffers
+    #define traceRETURN_xTaskGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetSystemState
+    #define traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime )
+#endif
+
+#ifndef traceRETURN_uxTaskGetSystemState
+    #define traceRETURN_uxTaskGetSystemState( uxTask )
+#endif
+
+#if ( configNUMBER_OF_CORES == 1 )
+    #ifndef traceENTER_xTaskGetIdleTaskHandle
+        #define traceENTER_xTaskGetIdleTaskHandle()
+    #endif
+#endif
+
+#if ( configNUMBER_OF_CORES == 1 )
+    #ifndef traceRETURN_xTaskGetIdleTaskHandle
+        #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle )
+    #endif
+#endif
+
+#ifndef traceENTER_xTaskGetIdleTaskHandleForCore
+    #define traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID )
+#endif
+
+#ifndef traceRETURN_xTaskGetIdleTaskHandleForCore
+    #define traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandle )
+#endif
+
+#ifndef traceENTER_vTaskStepTick
+    #define traceENTER_vTaskStepTick( xTicksToJump )
+#endif
+
+#ifndef traceRETURN_vTaskStepTick
+    #define traceRETURN_vTaskStepTick()
+#endif
+
+#ifndef traceENTER_xTaskCatchUpTicks
+    #define traceENTER_xTaskCatchUpTicks( xTicksToCatchUp )
+#endif
+
+#ifndef traceRETURN_xTaskCatchUpTicks
+    #define traceRETURN_xTaskCatchUpTicks( xYieldOccurred )
+#endif
+
+#ifndef traceENTER_xTaskAbortDelay
+    #define traceENTER_xTaskAbortDelay( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskAbortDelay
+    #define traceRETURN_xTaskAbortDelay( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskIncrementTick
+    #define traceENTER_xTaskIncrementTick()
+#endif
+
+#ifndef traceRETURN_xTaskIncrementTick
+    #define traceRETURN_xTaskIncrementTick( xSwitchRequired )
+#endif
+
+#ifndef traceENTER_vTaskSetApplicationTaskTag
+    #define traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction )
+#endif
+
+#ifndef traceRETURN_vTaskSetApplicationTaskTag
+    #define traceRETURN_vTaskSetApplicationTaskTag()
+#endif
+
+#ifndef traceENTER_xTaskGetApplicationTaskTag
+    #define traceENTER_xTaskGetApplicationTaskTag( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetApplicationTaskTag
+    #define traceRETURN_xTaskGetApplicationTaskTag( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetApplicationTaskTagFromISR
+    #define traceENTER_xTaskGetApplicationTaskTagFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetApplicationTaskTagFromISR
+    #define traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCallApplicationTaskHook
+    #define traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter )
+#endif
+
+#ifndef traceRETURN_xTaskCallApplicationTaskHook
+    #define traceRETURN_xTaskCallApplicationTaskHook( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskSwitchContext
+    #define traceENTER_vTaskSwitchContext()
+#endif
+
+#ifndef traceRETURN_vTaskSwitchContext
+    #define traceRETURN_vTaskSwitchContext()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnEventList
+    #define traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnEventList
+    #define traceRETURN_vTaskPlaceOnEventList()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnUnorderedEventList
+    #define traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnUnorderedEventList
+    #define traceRETURN_vTaskPlaceOnUnorderedEventList()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnEventListRestricted
+    #define traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnEventListRestricted
+    #define traceRETURN_vTaskPlaceOnEventListRestricted()
+#endif
+
+#ifndef traceENTER_xTaskRemoveFromEventList
+    #define traceENTER_xTaskRemoveFromEventList( pxEventList )
+#endif
+
+#ifndef traceRETURN_xTaskRemoveFromEventList
+    #define traceRETURN_xTaskRemoveFromEventList( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskRemoveFromUnorderedEventList
+    #define traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue )
+#endif
+
+#ifndef traceRETURN_vTaskRemoveFromUnorderedEventList
+    #define traceRETURN_vTaskRemoveFromUnorderedEventList()
+#endif
+
+#ifndef traceENTER_vTaskSetTimeOutState
+    #define traceENTER_vTaskSetTimeOutState( pxTimeOut )
+#endif
+
+#ifndef traceRETURN_vTaskSetTimeOutState
+    #define traceRETURN_vTaskSetTimeOutState()
+#endif
+
+#ifndef traceENTER_vTaskInternalSetTimeOutState
+    #define traceENTER_vTaskInternalSetTimeOutState( pxTimeOut )
+#endif
+
+#ifndef traceRETURN_vTaskInternalSetTimeOutState
+    #define traceRETURN_vTaskInternalSetTimeOutState()
+#endif
+
+#ifndef traceENTER_xTaskCheckForTimeOut
+    #define traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTaskCheckForTimeOut
+    #define traceRETURN_xTaskCheckForTimeOut( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskMissedYield
+    #define traceENTER_vTaskMissedYield()
+#endif
+
+#ifndef traceRETURN_vTaskMissedYield
+    #define traceRETURN_vTaskMissedYield()
+#endif
+
+#ifndef traceENTER_uxTaskGetTaskNumber
+    #define traceENTER_uxTaskGetTaskNumber( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetTaskNumber
+    #define traceRETURN_uxTaskGetTaskNumber( uxReturn )
+#endif
+
+#ifndef traceENTER_vTaskSetTaskNumber
+    #define traceENTER_vTaskSetTaskNumber( xTask, uxHandle )
+#endif
+
+#ifndef traceRETURN_vTaskSetTaskNumber
+    #define traceRETURN_vTaskSetTaskNumber()
+#endif
+
+#ifndef traceENTER_eTaskConfirmSleepModeStatus
+    #define traceENTER_eTaskConfirmSleepModeStatus()
+#endif
+
+#ifndef traceRETURN_eTaskConfirmSleepModeStatus
+    #define traceRETURN_eTaskConfirmSleepModeStatus( eReturn )
+#endif
+
+#ifndef traceENTER_vTaskSetThreadLocalStoragePointer
+    #define traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue )
+#endif
+
+#ifndef traceRETURN_vTaskSetThreadLocalStoragePointer
+    #define traceRETURN_vTaskSetThreadLocalStoragePointer()
+#endif
+
+#ifndef traceENTER_pvTaskGetThreadLocalStoragePointer
+    #define traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex )
+#endif
+
+#ifndef traceRETURN_pvTaskGetThreadLocalStoragePointer
+    #define traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn )
+#endif
+
+#ifndef traceENTER_vTaskAllocateMPURegions
+    #define traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions )
+#endif
+
+#ifndef traceRETURN_vTaskAllocateMPURegions
+    #define traceRETURN_vTaskAllocateMPURegions()
+#endif
+
+#ifndef traceENTER_vTaskGetInfo
+    #define traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState )
+#endif
+
+#ifndef traceRETURN_vTaskGetInfo
+    #define traceRETURN_vTaskGetInfo()
+#endif
+
+#ifndef traceENTER_uxTaskGetStackHighWaterMark2
+    #define traceENTER_uxTaskGetStackHighWaterMark2( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetStackHighWaterMark2
+    #define traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetStackHighWaterMark
+    #define traceENTER_uxTaskGetStackHighWaterMark( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetStackHighWaterMark
+    #define traceRETURN_uxTaskGetStackHighWaterMark( uxReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetCurrentTaskHandle
+    #define traceENTER_xTaskGetCurrentTaskHandle()
+#endif
+
+#ifndef traceRETURN_xTaskGetCurrentTaskHandle
+    #define traceRETURN_xTaskGetCurrentTaskHandle( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetCurrentTaskHandleForCore
+    #define traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID )
+#endif
+
+#ifndef traceRETURN_xTaskGetCurrentTaskHandleForCore
+    #define traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetSchedulerState
+    #define traceENTER_xTaskGetSchedulerState()
+#endif
+
+#ifndef traceRETURN_xTaskGetSchedulerState
+    #define traceRETURN_xTaskGetSchedulerState( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskPriorityInherit
+    #define traceENTER_xTaskPriorityInherit( pxMutexHolder )
+#endif
+
+#ifndef traceRETURN_xTaskPriorityInherit
+    #define traceRETURN_xTaskPriorityInherit( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskPriorityDisinherit
+    #define traceENTER_xTaskPriorityDisinherit( pxMutexHolder )
+#endif
+
+#ifndef traceRETURN_xTaskPriorityDisinherit
+    #define traceRETURN_xTaskPriorityDisinherit( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskPriorityDisinheritAfterTimeout
+    #define traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask )
+#endif
+
+#ifndef traceRETURN_vTaskPriorityDisinheritAfterTimeout
+    #define traceRETURN_vTaskPriorityDisinheritAfterTimeout()
+#endif
+
+#ifndef traceENTER_vTaskYieldWithinAPI
+    #define traceENTER_vTaskYieldWithinAPI()
+#endif
+
+#ifndef traceRETURN_vTaskYieldWithinAPI
+    #define traceRETURN_vTaskYieldWithinAPI()
+#endif
+
+#ifndef traceENTER_vTaskEnterCritical
+    #define traceENTER_vTaskEnterCritical()
+#endif
+
+#ifndef traceRETURN_vTaskEnterCritical
+    #define traceRETURN_vTaskEnterCritical()
+#endif
+
+#ifndef traceENTER_vTaskEnterCriticalFromISR
+    #define traceENTER_vTaskEnterCriticalFromISR()
+#endif
+
+#ifndef traceRETURN_vTaskEnterCriticalFromISR
+    #define traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus )
+#endif
+
+#ifndef traceENTER_vTaskExitCritical
+    #define traceENTER_vTaskExitCritical()
+#endif
+
+#ifndef traceRETURN_vTaskExitCritical
+    #define traceRETURN_vTaskExitCritical()
+#endif
+
+#ifndef traceENTER_vTaskExitCriticalFromISR
+    #define traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus )
+#endif
+
+#ifndef traceRETURN_vTaskExitCriticalFromISR
+    #define traceRETURN_vTaskExitCriticalFromISR()
+#endif
+
+#ifndef traceENTER_vTaskListTasks
+    #define traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength )
+#endif
+
+#ifndef traceRETURN_vTaskListTasks
+    #define traceRETURN_vTaskListTasks()
+#endif
+
+#ifndef traceENTER_vTaskGetRunTimeStatistics
+    #define traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength )
+#endif
+
+#ifndef traceRETURN_vTaskGetRunTimeStatistics
+    #define traceRETURN_vTaskGetRunTimeStatistics()
+#endif
+
+#ifndef traceENTER_uxTaskResetEventItemValue
+    #define traceENTER_uxTaskResetEventItemValue()
+#endif
+
+#ifndef traceRETURN_uxTaskResetEventItemValue
+    #define traceRETURN_uxTaskResetEventItemValue( uxReturn )
+#endif
+
+#ifndef traceENTER_pvTaskIncrementMutexHeldCount
+    #define traceENTER_pvTaskIncrementMutexHeldCount()
+#endif
+
+#ifndef traceRETURN_pvTaskIncrementMutexHeldCount
+    #define traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB )
+#endif
+
+#ifndef traceENTER_ulTaskGenericNotifyTake
+    #define traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_ulTaskGenericNotifyTake
+    #define traceRETURN_ulTaskGenericNotifyTake( ulReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyWait
+    #define traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyWait
+    #define traceRETURN_xTaskGenericNotifyWait( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotify
+    #define traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotify
+    #define traceRETURN_xTaskGenericNotify( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyFromISR
+    #define traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyFromISR
+    #define traceRETURN_xTaskGenericNotifyFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskGenericNotifyGiveFromISR
+    #define traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_vTaskGenericNotifyGiveFromISR
+    #define traceRETURN_vTaskGenericNotifyGiveFromISR()
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyStateClear
+    #define traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyStateClear
+    #define traceRETURN_xTaskGenericNotifyStateClear( xReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGenericNotifyValueClear
+    #define traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear )
+#endif
+
+#ifndef traceRETURN_ulTaskGenericNotifyValueClear
+    #define traceRETURN_ulTaskGenericNotifyValueClear( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetRunTimeCounter
+    #define traceENTER_ulTaskGetRunTimeCounter( xTask )
+#endif
+
+#ifndef traceRETURN_ulTaskGetRunTimeCounter
+    #define traceRETURN_ulTaskGetRunTimeCounter( ulRunTimeCounter )
+#endif
+
+#ifndef traceENTER_ulTaskGetRunTimePercent
+    #define traceENTER_ulTaskGetRunTimePercent( xTask )
+#endif
+
+#ifndef traceRETURN_ulTaskGetRunTimePercent
+    #define traceRETURN_ulTaskGetRunTimePercent( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetIdleRunTimeCounter
+    #define traceENTER_ulTaskGetIdleRunTimeCounter()
+#endif
+
+#ifndef traceRETURN_ulTaskGetIdleRunTimeCounter
+    #define traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetIdleRunTimePercent
+    #define traceENTER_ulTaskGetIdleRunTimePercent()
+#endif
+
+#ifndef traceRETURN_ulTaskGetIdleRunTimePercent
+    #define traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetMPUSettings
+    #define traceENTER_xTaskGetMPUSettings( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetMPUSettings
+    #define traceRETURN_xTaskGetMPUSettings( xMPUSettings )
+#endif
+
+#ifndef traceENTER_xStreamBufferGenericCreate
+    #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGenericCreate
+    #define traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory )
+#endif
+
+#ifndef traceENTER_xStreamBufferGenericCreateStatic
+    #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGenericCreateStatic
+    #define traceRETURN_xStreamBufferGenericCreateStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferGetStaticBuffers
+    #define traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGetStaticBuffers
+    #define traceRETURN_xStreamBufferGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_vStreamBufferDelete
+    #define traceENTER_vStreamBufferDelete( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_vStreamBufferDelete
+    #define traceRETURN_vStreamBufferDelete()
+#endif
+
+#ifndef traceENTER_xStreamBufferReset
+    #define traceENTER_xStreamBufferReset( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReset
+    #define traceRETURN_xStreamBufferReset( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSetTriggerLevel
+    #define traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSetTriggerLevel
+    #define traceRETURN_xStreamBufferSetTriggerLevel( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSpacesAvailable
+    #define traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSpacesAvailable
+    #define traceRETURN_xStreamBufferSpacesAvailable( xSpace )
+#endif
+
+#ifndef traceENTER_xStreamBufferBytesAvailable
+    #define traceENTER_xStreamBufferBytesAvailable( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferBytesAvailable
+    #define traceRETURN_xStreamBufferBytesAvailable( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSend
+    #define traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSend
+    #define traceRETURN_xStreamBufferSend( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSendFromISR
+    #define traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSendFromISR
+    #define traceRETURN_xStreamBufferSendFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceive
+    #define traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceive
+    #define traceRETURN_xStreamBufferReceive( xReceivedLength )
+#endif
+
+#ifndef traceENTER_xStreamBufferNextMessageLengthBytes
+    #define traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferNextMessageLengthBytes
+    #define traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceiveFromISR
+    #define traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceiveFromISR
+    #define traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength )
+#endif
+
+#ifndef traceENTER_xStreamBufferIsEmpty
+    #define traceENTER_xStreamBufferIsEmpty( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferIsEmpty
+    #define traceRETURN_xStreamBufferIsEmpty( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferIsFull
+    #define traceENTER_xStreamBufferIsFull( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferIsFull
+    #define traceRETURN_xStreamBufferIsFull( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSendCompletedFromISR
+    #define traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSendCompletedFromISR
+    #define traceRETURN_xStreamBufferSendCompletedFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceiveCompletedFromISR
+    #define traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceiveCompletedFromISR
+    #define traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxStreamBufferGetStreamBufferNumber
+    #define traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_uxStreamBufferGetStreamBufferNumber
+    #define traceRETURN_uxStreamBufferGetStreamBufferNumber( uxStreamBufferNumber )
+#endif
+
+#ifndef traceENTER_vStreamBufferSetStreamBufferNumber
+    #define traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber )
+#endif
+
+#ifndef traceRETURN_vStreamBufferSetStreamBufferNumber
+    #define traceRETURN_vStreamBufferSetStreamBufferNumber()
+#endif
+
+#ifndef traceENTER_ucStreamBufferGetStreamBufferType
+    #define traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_ucStreamBufferGetStreamBufferType
+    #define traceRETURN_ucStreamBufferGetStreamBufferType( ucStreamBufferType )
+#endif
+
+#ifndef traceENTER_vListInitialise
+    #define traceENTER_vListInitialise( pxList )
+#endif
+
+#ifndef traceRETURN_vListInitialise
+    #define traceRETURN_vListInitialise()
+#endif
+
+#ifndef traceENTER_vListInitialiseItem
+    #define traceENTER_vListInitialiseItem( pxItem )
+#endif
+
+#ifndef traceRETURN_vListInitialiseItem
+    #define traceRETURN_vListInitialiseItem()
+#endif
+
+#ifndef traceENTER_vListInsertEnd
+    #define traceENTER_vListInsertEnd( pxList, pxNewListItem )
+#endif
+
+#ifndef traceRETURN_vListInsertEnd
+    #define traceRETURN_vListInsertEnd()
+#endif
+
+#ifndef traceENTER_vListInsert
+    #define traceENTER_vListInsert( pxList, pxNewListItem )
+#endif
+
+#ifndef traceRETURN_vListInsert
+    #define traceRETURN_vListInsert()
+#endif
+
+#ifndef traceENTER_uxListRemove
+    #define traceENTER_uxListRemove( pxItemToRemove )
+#endif
+
+#ifndef traceRETURN_uxListRemove
+    #define traceRETURN_uxListRemove( uxNumberOfItems )
+#endif
+
+#ifndef traceENTER_xCoRoutineCreate
+    #define traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex )
+#endif
+
+#ifndef traceRETURN_xCoRoutineCreate
+    #define traceRETURN_xCoRoutineCreate( xReturn )
+#endif
+
+#ifndef traceENTER_vCoRoutineAddToDelayedList
+    #define traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList )
+#endif
+
+#ifndef traceRETURN_vCoRoutineAddToDelayedList
+    #define traceRETURN_vCoRoutineAddToDelayedList()
+#endif
+
+#ifndef traceENTER_vCoRoutineSchedule
+    #define traceENTER_vCoRoutineSchedule()
+#endif
+
+#ifndef traceRETURN_vCoRoutineSchedule
+    #define traceRETURN_vCoRoutineSchedule()
+#endif
+
+#ifndef traceENTER_xCoRoutineRemoveFromEventList
+    #define traceENTER_xCoRoutineRemoveFromEventList( pxEventList )
+#endif
+
+#ifndef traceRETURN_xCoRoutineRemoveFromEventList
+    #define traceRETURN_xCoRoutineRemoveFromEventList( xReturn )
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+    #define configGENERATE_RUN_TIME_STATS    0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+    #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+        #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+    #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+    #ifndef portGET_RUN_TIME_COUNTER_VALUE
+        #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+            #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
+        #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+    #endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+    #define configUSE_MALLOC_FAILED_HOOK    0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+    #define portPRIVILEGE_BIT    ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+    #define portYIELD_WITHIN_API    portYIELD
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+    #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP    2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+    #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+    #define configUSE_TICKLESS_IDLE    0
+#endif
+
+#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
+    #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+    #define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+    #define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+    #define configUSE_QUEUE_SETS    0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+    #define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef portALLOCATE_SECURE_CONTEXT
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portDONT_DISCARD
+    #define portDONT_DISCARD
+#endif
+
+#ifndef configUSE_TIME_SLICING
+    #define configUSE_TIME_SLICING    1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+    #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+    #define configUSE_STATS_FORMATTING_FUNCTIONS    0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+    #define configUSE_TRACE_FACILITY    0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef mtCOVERAGE_TEST_DELAY
+    #define mtCOVERAGE_TEST_DELAY()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+    #define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+#endif
+
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+    #define configAPPLICATION_ALLOCATED_HEAP    0
+#endif
+
+#ifndef configENABLE_HEAP_PROTECTOR
+    #define configENABLE_HEAP_PROTECTOR    0
+#endif
+
+#ifndef configUSE_TASK_NOTIFICATIONS
+    #define configUSE_TASK_NOTIFICATIONS    1
+#endif
+
+#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES
+    #define configTASK_NOTIFICATION_ARRAY_ENTRIES    1
+#endif
+
+#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1
+    #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1
+#endif
+
+#ifndef configUSE_POSIX_ERRNO
+    #define configUSE_POSIX_ERRNO    0
+#endif
+
+#ifndef configUSE_SB_COMPLETED_CALLBACK
+
+/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */
+    #define configUSE_SB_COMPLETED_CALLBACK    0
+#endif
+
+#ifndef portTICK_TYPE_IS_ATOMIC
+    #define portTICK_TYPE_IS_ATOMIC    0
+#endif
+
+#ifndef configSUPPORT_STATIC_ALLOCATION
+    /* Defaults to 0 for backward compatibility. */
+    #define configSUPPORT_STATIC_ALLOCATION    0
+#endif
+
+#ifndef configKERNEL_PROVIDED_STATIC_MEMORY
+    #define configKERNEL_PROVIDED_STATIC_MEMORY    0
+#endif
+
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+    /* Defaults to 1 for backward compatibility. */
+    #define configSUPPORT_DYNAMIC_ALLOCATION    1
+#endif
+
+#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) )
+    #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1.
+#endif
+
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
+    #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) )
+        #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1.  Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h.
+    #endif
+#endif
+
+#ifndef configSTATS_BUFFER_MAX_LENGTH
+    #define configSTATS_BUFFER_MAX_LENGTH    0xFFFF
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+
+/* Defaults to uint16_t for backward compatibility, but can be overridden
+ * in FreeRTOSConfig.h if uint16_t is too restrictive. */
+    #define configSTACK_DEPTH_TYPE    uint16_t
+#endif
+
+#ifndef configRUN_TIME_COUNTER_TYPE
+
+/* Defaults to uint32_t for backward compatibility, but can be overridden in
+ * FreeRTOSConfig.h if uint32_t is too restrictive. */
+
+    #define configRUN_TIME_COUNTER_TYPE    uint32_t
+#endif
+
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+
+/* Defaults to size_t for backward compatibility, but can be overridden
+ * in FreeRTOSConfig.h if lengths will always be less than the number of bytes
+ * in a size_t. */
+    #define configMESSAGE_BUFFER_LENGTH_TYPE    size_t
+#endif
+
+/* Sanity check the configuration. */
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+    #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
+#endif
+
+#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
+    #error configUSE_MUTEXES must be set to 1 to use recursive mutexes
+#endif
+
+#if ( ( configRUN_MULTIPLE_PRIORITIES == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+    #error configRUN_MULTIPLE_PRIORITIES must be set to 1 to use task preemption disable
+#endif
+
+#if ( ( configUSE_PREEMPTION == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+    #error configUSE_PREEMPTION must be set to 1 to use task preemption disable
+#endif
+
+#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+    #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS
+#endif
+
+#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_CORE_AFFINITY != 0 ) )
+    #error configUSE_CORE_AFFINITY is not supported in single core FreeRTOS
+#endif
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PORT_OPTIMISED_TASK_SELECTION != 0 ) )
+    #error configUSE_PORT_OPTIMISED_TASK_SELECTION is not supported in SMP FreeRTOS
+#endif
+
+#ifndef configINITIAL_TICK_COUNT
+    #define configINITIAL_TICK_COUNT    0
+#endif
+
+#if ( portTICK_TYPE_IS_ATOMIC == 0 )
+
+/* Either variables of tick type cannot be read atomically, or
+ * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
+ * the tick count is returned to the standard critical section macros. */
+    #define portTICK_TYPE_ENTER_CRITICAL()                      portENTER_CRITICAL()
+    #define portTICK_TYPE_EXIT_CRITICAL()                       portEXIT_CRITICAL()
+    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         portSET_INTERRUPT_MASK_FROM_ISR()
+    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
+#else
+
+/* The tick type can be read atomically, so critical sections used when the
+ * tick count is returned can be defined away. */
+    #define portTICK_TYPE_ENTER_CRITICAL()
+    #define portTICK_TYPE_EXIT_CRITICAL()
+    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         0
+    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    ( void ) ( x )
+#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+ * V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+    #define configENABLE_BACKWARD_COMPATIBILITY    1
+#endif
+
+#ifndef configPRINTF
+
+/* configPRINTF() was not defined, so define it away to nothing.  To use
+ * configPRINTF() then define it as follows (where MyPrintFunction() is
+ * provided by the application writer):
+ *
+ * void MyPrintFunction(const char *pcFormat, ... );
+ #define configPRINTF( X )   MyPrintFunction X
+ *
+ * Then call like a standard printf() function, but placing brackets around
+ * all parameters so they are passed as a single parameter.  For example:
+ * configPRINTF( ("Value = %d", MyVariable) ); */
+    #define configPRINTF( X )
+#endif
+
+#ifndef configMAX
+
+/* The application writer has not provided their own MAX macro, so define
+ * the following generic implementation. */
+    #define configMAX( a, b )    ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#ifndef configMIN
+
+/* The application writer has not provided their own MIN macro, so define
+ * the following generic implementation. */
+    #define configMIN( a, b )    ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+    #define eTaskStateGet                 eTaskGetState
+    #define portTickType                  TickType_t
+    #define xTaskHandle                   TaskHandle_t
+    #define xQueueHandle                  QueueHandle_t
+    #define xSemaphoreHandle              SemaphoreHandle_t
+    #define xQueueSetHandle               QueueSetHandle_t
+    #define xQueueSetMemberHandle         QueueSetMemberHandle_t
+    #define xTimeOutType                  TimeOut_t
+    #define xMemoryRegion                 MemoryRegion_t
+    #define xTaskParameters               TaskParameters_t
+    #define xTaskStatusType               TaskStatus_t
+    #define xTimerHandle                  TimerHandle_t
+    #define xCoRoutineHandle              CoRoutineHandle_t
+    #define pdTASK_HOOK_CODE              TaskHookFunction_t
+    #define portTICK_RATE_MS              portTICK_PERIOD_MS
+    #define pcTaskGetTaskName             pcTaskGetName
+    #define pcTimerGetTimerName           pcTimerGetName
+    #define pcQueueGetQueueName           pcQueueGetName
+    #define vTaskGetTaskInfo              vTaskGetInfo
+    #define xTaskGetIdleRunTimeCounter    ulTaskGetIdleRunTimeCounter
+
+/* Backward compatibility within the scheduler code only - these definitions
+ * are not really required but are included for completeness. */
+    #define tmrTIMER_CALLBACK             TimerCallbackFunction_t
+    #define pdTASK_CODE                   TaskFunction_t
+    #define xListItem                     ListItem_t
+    #define xList                         List_t
+
+/* For libraries that break the list data hiding, and access list structure
+ * members directly (which is not supposed to be done). */
+    #define pxContainer                   pvContainer
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#if ( configUSE_ALTERNATIVE_API != 0 )
+    #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
+#endif
+
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+ * if floating point hardware is otherwise supported by the FreeRTOS port in use.
+ * This constant is not supported by all FreeRTOS ports that include floating
+ * point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+    #define configUSE_TASK_FPU_SUPPORT    1
+#endif
+
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+ * currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+    #define configENABLE_MPU    0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+ * currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+    #define configENABLE_FPU    1
+#endif
+
+/* Set configENABLE_MVE to 1 to enable MVE support and 0 to disable it. This is
+ * currently used in ARMv8M ports. */
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+ * This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+    #define configENABLE_TRUSTZONE    1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+ * the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+    #define configRUN_FREERTOS_SECURE_ONLY    0
+#endif
+
+#ifndef configRUN_ADDITIONAL_TESTS
+    #define configRUN_ADDITIONAL_TESTS    0
+#endif
+
+/* The following config allows infinite loop control. For example, control the
+ * infinite loop in idle task function when performing unit tests. */
+#ifndef configCONTROL_INFINITE_LOOP
+    #define configCONTROL_INFINITE_LOOP()
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed.  Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM.  Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
+ * |     |         |        |                             |                                   | Static Possible  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE                                                                                     \
+    ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+      ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
+/*
+ * In line with software engineering best practice, FreeRTOS implements a strict
+ * data hiding policy, so the real structures used by FreeRTOS to maintain the
+ * state of tasks, queues, semaphores, etc. are not accessible to the application
+ * code.  However, if the application writer wants to statically allocate such
+ * an object then the size of the object needs to be known.  Dummy structures
+ * that are guaranteed to have the same size and alignment requirements of the
+ * real objects are used for this purpose.  The dummy list and list item
+ * structures below are used for inclusion in such a dummy structure.
+ */
+struct xSTATIC_LIST_ITEM
+{
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    TickType_t xDummy2;
+    void * pvDummy3[ 4 ];
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy4;
+    #endif
+};
+typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
+
+#if ( configUSE_MINI_LIST_ITEM == 1 )
+    /* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+    struct xSTATIC_MINI_LIST_ITEM
+    {
+        #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+            TickType_t xDummy1;
+        #endif
+        TickType_t xDummy2;
+        void * pvDummy3[ 2 ];
+    };
+    typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+#else /* if ( configUSE_MINI_LIST_ITEM == 1 ) */
+    typedef struct xSTATIC_LIST_ITEM      StaticMiniListItem_t;
+#endif /* if ( configUSE_MINI_LIST_ITEM == 1 ) */
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+typedef struct xSTATIC_LIST
+{
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    UBaseType_t uxDummy2;
+    void * pvDummy3;
+    StaticMiniListItem_t xDummy4;
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy5;
+    #endif
+} StaticList_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Task structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a task then
+ * the size of the task object needs to be known.  The StaticTask_t structure
+ * below is provided for this purpose.  Its sizes and alignment requirements are
+ * guaranteed to match those of the genuine structure, no matter which
+ * architecture is being used, and no matter how the values in FreeRTOSConfig.h
+ * are set.  Its contents are somewhat obfuscated in the hope users will
+ * recognise that it would be unwise to make direct use of the structure members.
+ */
+typedef struct xSTATIC_TCB
+{
+    void * pxDummy1;
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        xMPU_SETTINGS xDummy2;
+    #endif
+    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+        UBaseType_t uxDummy26;
+    #endif
+    StaticListItem_t xDummy3[ 2 ];
+    UBaseType_t uxDummy5;
+    void * pxDummy6;
+    #if ( configNUMBER_OF_CORES > 1 )
+        BaseType_t xDummy23;
+        UBaseType_t uxDummy24;
+    #endif
+    uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];
+    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+        BaseType_t xDummy25;
+    #endif
+    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+        void * pxDummy8;
+    #endif
+    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+        UBaseType_t uxDummy9;
+    #endif
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy10[ 2 ];
+    #endif
+    #if ( configUSE_MUTEXES == 1 )
+        UBaseType_t uxDummy12[ 2 ];
+    #endif
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+        void * pxDummy14;
+    #endif
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+        void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+    #endif
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+        configRUN_TIME_COUNTER_TYPE ulDummy16;
+    #endif
+    #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+        configTLS_BLOCK_TYPE xDummy17;
+    #endif
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+        uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+        uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+    #endif
+    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+        uint8_t uxDummy20;
+    #endif
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+        uint8_t ucDummy21;
+    #endif
+    #if ( configUSE_POSIX_ERRNO == 1 )
+        int iDummy22;
+    #endif
+} StaticTask_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Queue structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a queue
+ * then the size of the queue object needs to be known.  The StaticQueue_t
+ * structure below is provided for this purpose.  Its sizes and alignment
+ * requirements are guaranteed to match those of the genuine structure, no
+ * matter which architecture is being used, and no matter how the values in
+ * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
+ * users will recognise that it would be unwise to make direct use of the
+ * structure members.
+ */
+typedef struct xSTATIC_QUEUE
+{
+    void * pvDummy1[ 3 ];
+
+    union
+    {
+        void * pvDummy2;
+        UBaseType_t uxDummy2;
+    } u;
+
+    StaticList_t xDummy3[ 2 ];
+    UBaseType_t uxDummy4[ 3 ];
+    uint8_t ucDummy5[ 2 ];
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucDummy6;
+    #endif
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+        void * pvDummy7;
+    #endif
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy8;
+        uint8_t ucDummy9;
+    #endif
+} StaticQueue_t;
+typedef StaticQueue_t StaticSemaphore_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the event group structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create an event group then the size of the event group object needs to be
+ * know.  The StaticEventGroup_t structure below is provided for this purpose.
+ * Its sizes and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_EVENT_GROUP
+{
+    TickType_t xDummy1;
+    StaticList_t xDummy2;
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy3;
+    #endif
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucDummy4;
+    #endif
+} StaticEventGroup_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the software timer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a software timer then the size of the queue object needs to be known.
+ * The StaticTimer_t structure below is provided for this purpose.  Its sizes
+ * and alignment requirements are guaranteed to match those of the genuine
+ * structure, no matter which architecture is being used, and no matter how the
+ * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
+ * the hope users will recognise that it would be unwise to make direct use of
+ * the structure members.
+ */
+typedef struct xSTATIC_TIMER
+{
+    void * pvDummy1;
+    StaticListItem_t xDummy2;
+    TickType_t xDummy3;
+    void * pvDummy5;
+    TaskFunction_t pvDummy6;
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy7;
+    #endif
+    uint8_t ucDummy8;
+} StaticTimer_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the stream buffer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a stream buffer then the size of the stream buffer object needs to be
+ * known.  The StaticStreamBuffer_t structure below is provided for this
+ * purpose.  Its size and alignment requirements are guaranteed to match those
+ * of the genuine structure, no matter which architecture is being used, and
+ * no matter how the values in FreeRTOSConfig.h are set.  Its contents are
+ * somewhat obfuscated in the hope users will recognise that it would be unwise
+ * to make direct use of the structure members.
+ */
+typedef struct xSTATIC_STREAM_BUFFER
+{
+    size_t uxDummy1[ 4 ];
+    void * pvDummy2[ 3 ];
+    uint8_t ucDummy3;
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy4;
+    #endif
+    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+        void * pvDummy5[ 2 ];
+    #endif
+} StaticStreamBuffer_t;
+
+/* Message buffers are built on stream buffers. */
+typedef StaticStreamBuffer_t StaticMessageBuffer_t;
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* INC_FREERTOS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/StackMacros.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/StackMacros.h
new file mode 100644
index 0000000000..e20d5280ad
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/StackMacros.h
@@ -0,0 +1,34 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
+    #warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in a future release.
+#endif
+
+#include "stack_macros.h"
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/atomic.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/atomic.h
new file mode 100644
index 0000000000..f6ea5d2c66
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/atomic.h
@@ -0,0 +1,419 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/**
+ * @file atomic.h
+ * @brief FreeRTOS atomic operation support.
+ *
+ * This file implements atomic functions by disabling interrupts globally.
+ * Implementations with architecture specific atomic instructions can be
+ * provided under each compiler directory.
+ */
+
+#ifndef ATOMIC_H
+#define ATOMIC_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include atomic.h"
+#endif
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*
+ * Port specific definitions -- entering/exiting critical section.
+ * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
+ *
+ * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
+ * ATOMIC_ENTER_CRITICAL().
+ *
+ */
+#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
+
+/* Nested interrupt scheme is supported in this port. */
+    #define ATOMIC_ENTER_CRITICAL() \
+    UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
+
+    #define ATOMIC_EXIT_CRITICAL() \
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
+
+#else
+
+/* Nested interrupt scheme is NOT supported in this port. */
+    #define ATOMIC_ENTER_CRITICAL()    portENTER_CRITICAL()
+    #define ATOMIC_EXIT_CRITICAL()     portEXIT_CRITICAL()
+
+#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
+
+/*
+ * Port specific definition -- "always inline".
+ * Inline is compiler specific, and may not always get inlined depending on your
+ * optimization level.  Also, inline is considered as performance optimization
+ * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,
+ * instead of resulting error, simply define it away.
+ */
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE
+#endif
+
+#define ATOMIC_COMPARE_AND_SWAP_SUCCESS    0x1U     /**< Compare and swap succeeded, swapped. */
+#define ATOMIC_COMPARE_AND_SWAP_FAILURE    0x0U     /**< Compare and swap failed, did not swap. */
+
+/*----------------------------- Swap && CAS ------------------------------*/
+
+/**
+ * Atomic compare-and-swap
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified values.
+ *
+ * @param[in, out] pulDestination  Pointer to memory location from where value is
+ *                               to be loaded and checked.
+ * @param[in] ulExchange         If condition meets, write this value to memory.
+ * @param[in] ulComparand        Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *pulDestination with ulExchange, if previous
+ *       *pulDestination value equals ulComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
+                                                            uint32_t ulExchange,
+                                                            uint32_t ulComparand )
+{
+    uint32_t ulReturnValue;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        if( *pulDestination == ulComparand )
+        {
+            *pulDestination = ulExchange;
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+        }
+        else
+        {
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+        }
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic swap (pointers)
+ *
+ * @brief Atomically sets the address pointed to by *ppvDestination to the value
+ *        of *pvExchange.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and written back to.
+ * @param[in] pvExchange           Pointer value to be written to *ppvDestination.
+ *
+ * @return The initial value of *ppvDestination.
+ */
+static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
+                                                        void * pvExchange )
+{
+    void * pReturnValue;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        pReturnValue = *ppvDestination;
+        *ppvDestination = pvExchange;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return pReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic compare-and-swap (pointers)
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified pointer
+ *        values.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and checked.
+ * @param[in] pvExchange           If condition meets, write this value to memory.
+ * @param[in] pvComparand          Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *ppvDestination with pvExchange, if previous
+ *       *ppvDestination value equals pvComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
+                                                                    void * pvExchange,
+                                                                    void * pvComparand )
+{
+    uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        if( *ppvDestination == pvComparand )
+        {
+            *ppvDestination = pvExchange;
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+        }
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulReturnValue;
+}
+
+
+/*----------------------------- Arithmetic ------------------------------*/
+
+/**
+ * Atomic add
+ *
+ * @brief Atomically adds count to the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be added to *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
+                                                 uint32_t ulCount )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend += ulCount;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic subtract
+ *
+ * @brief Atomically subtracts count from the value of the specified pointer
+ *        pointers to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be subtract from *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
+                                                      uint32_t ulCount )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend -= ulCount;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic increment
+ *
+ * @brief Atomically increments the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before increment.
+ */
+static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend += 1;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic decrement
+ *
+ * @brief Atomically decrements the value of the specified pointer points to
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before decrement.
+ */
+static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend -= 1;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+
+/*----------------------------- Bitwise Logical ------------------------------*/
+
+/**
+ * Atomic OR
+ *
+ * @brief Performs an atomic OR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
+                                                uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination |= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic AND
+ *
+ * @brief Performs an atomic AND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
+                                                 uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination &= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic NAND
+ *
+ * @brief Performs an atomic NAND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be NANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
+                                                  uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination = ~( ulCurrent & ulValue );
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic XOR
+ *
+ * @brief Performs an atomic XOR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be XORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
+                                                 uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination ^= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* ATOMIC_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/croutine.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/croutine.h
new file mode 100644
index 0000000000..431d303fbe
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/croutine.h
@@ -0,0 +1,755 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* Used to hide the implementation of the co-routine control block.  The
+ * control block structure however has to be included in the header due to
+ * the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t xHandle,
+                                   UBaseType_t uxIndex );
+
+typedef struct corCoRoutineControlBlock
+{
+    crCOROUTINE_CODE pxCoRoutineFunction;
+    ListItem_t xGenericListItem; /**< List item used to place the CRCB in ready and blocked queues. */
+    ListItem_t xEventListItem;   /**< List item used to place the CRCB in event lists. */
+    UBaseType_t uxPriority;      /**< The priority of the co-routine in relation to other co-routines. */
+    UBaseType_t uxIndex;         /**< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+    uint16_t uxState;            /**< Used internally by the co-routine implementation. */
+} CRCB_t;                        /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ * @code{c}
+ * BaseType_t xCoRoutineCreate(
+ *                               crCOROUTINE_CODE pxCoRoutineCode,
+ *                               UBaseType_t uxPriority,
+ *                               UBaseType_t uxIndex
+ *                             );
+ * @endcode
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+ * @code{c}
+ * // Co-routine to be created.
+ * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * static const char cLedToFlash[ 2 ] = { 5, 6 };
+ * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // This co-routine just delays for a fixed period, then toggles
+ *       // an LED.  Two co-routines are created using this function, so
+ *       // the uxIndex parameter is used to tell the co-routine which
+ *       // LED to flash and how int32_t to delay.  This assumes xQueue has
+ *       // already been created.
+ *       vParTestToggleLED( cLedToFlash[ uxIndex ] );
+ *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * // Function that creates two co-routines.
+ * void vOtherFunction( void )
+ * {
+ * uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle;
+ *
+ *   // Create two co-routines at priority 0.  The first is given index 0
+ *   // so (from the code above) toggles LED 5 every 200 ticks.  The second
+ *   // is given index 1 so toggles LED 6 every 400 ticks.
+ *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+ *   {
+ *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+ *   }
+ * }
+ * @endcode
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
+                             UBaseType_t uxPriority,
+                             UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ * @code{c}
+ * void vCoRoutineSchedule( void );
+ * @endcode
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+ * @code{c}
+ * // This idle task hook will schedule a co-routine each time it is called.
+ * // The rest of the idle task will execute between co-routine calls.
+ * void vApplicationIdleHook( void )
+ * {
+ *  vCoRoutineSchedule();
+ * }
+ *
+ * // Alternatively, if you do not require any other part of the idle task to
+ * // execute, the idle task hook can call vCoRoutineSchedule() within an
+ * // infinite loop.
+ * void vApplicationIdleHook( void )
+ * {
+ *  for( ;; )
+ *  {
+ *      vCoRoutineSchedule();
+ *  }
+ * }
+ * @endcode
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * @code{c}
+ * crSTART( CoRoutineHandle_t xHandle );
+ * @endcode
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+ * @code{c}
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * @endcode
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB )                            \
+    switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \
+        case 0:
+
+/**
+ * croutine. h
+ * @code{c}
+ * crEND();
+ * @endcode
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+ * @code{c}
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * @endcode
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND()    }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle )                                       \
+    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \
+    case ( __LINE__ * 2 ):
+#define crSET_STATE1( xHandle )                                               \
+    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \
+    case ( ( __LINE__ * 2 ) + 1 ):
+
+/**
+ * croutine. h
+ * @code{c}
+ * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * @endcode
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for.  The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+ * @code{c}
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * // We are to delay for 200ms.
+ * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *      // Delay for 200ms.
+ *      crDELAY( xHandle, xDelayTime );
+ *
+ *      // Do something here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * @endcode
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )                          \
+    do {                                                           \
+        if( ( xTicksToDelay ) > 0 )                                \
+        {                                                          \
+            vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
+        }                                                          \
+        crSET_STATE0( ( xHandle ) );                               \
+    } while( 0 )
+
+/**
+ * @code{c}
+ * crQUEUE_SEND(
+ *                CoRoutineHandle_t xHandle,
+ *                QueueHandle_t pxQueue,
+ *                void *pvItemToQueue,
+ *                TickType_t xTicksToWait,
+ *                BaseType_t *pxResult
+ *           )
+ * @endcode
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+ * @code{c}
+ * // Co-routine function that blocks for a fixed period then posts a number onto
+ * // a queue.
+ * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xNumberToPost = 0;
+ * static BaseType_t xResult;
+ *
+ *  // Co-routines must begin with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // This assumes the queue has already been created.
+ *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+ *
+ *      if( xResult != pdPASS )
+ *      {
+ *          // The message was not posted!
+ *      }
+ *
+ *      // Increment the number to be posted onto the queue.
+ *      xNumberToPost++;
+ *
+ *      // Delay for 100 ticks.
+ *      crDELAY( xHandle, 100 );
+ *  }
+ *
+ *  // Co-routines must end with a call to crEND().
+ *  crEND();
+ * }
+ * @endcode
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )           \
+    do {                                                                                  \
+        *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \
+        if( *( pxResult ) == errQUEUE_BLOCKED )                                           \
+        {                                                                                 \
+            crSET_STATE0( ( xHandle ) );                                                  \
+            *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );                \
+        }                                                                                 \
+        if( *pxResult == errQUEUE_YIELD )                                                 \
+        {                                                                                 \
+            crSET_STATE1( ( xHandle ) );                                                  \
+            *pxResult = pdPASS;                                                           \
+        }                                                                                 \
+    } while( 0 )
+
+/**
+ * croutine. h
+ * @code{c}
+ * crQUEUE_RECEIVE(
+ *                   CoRoutineHandle_t xHandle,
+ *                   QueueHandle_t pxQueue,
+ *                   void *pvBuffer,
+ *                   TickType_t xTicksToWait,
+ *                   BaseType_t *pxResult
+ *               )
+ * @endcode
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ * @code{c}
+ * // A co-routine receives the number of an LED to flash from a queue.  It
+ * // blocks on the queue until the number is received.
+ * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xResult;
+ * static UBaseType_t uxLEDToFlash;
+ *
+ *  // All co-routines must start with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // Wait for data to become available on the queue.
+ *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // We received the LED to flash - flash it!
+ *          vParTestToggleLED( uxLEDToFlash );
+ *      }
+ *  }
+ *
+ *  crEND();
+ * }
+ * @endcode
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )           \
+    do {                                                                                \
+        *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \
+        if( *( pxResult ) == errQUEUE_BLOCKED )                                         \
+        {                                                                               \
+            crSET_STATE0( ( xHandle ) );                                                \
+            *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 );            \
+        }                                                                               \
+        if( *( pxResult ) == errQUEUE_YIELD )                                           \
+        {                                                                               \
+            crSET_STATE1( ( xHandle ) );                                                \
+            *( pxResult ) = pdPASS;                                                     \
+        }                                                                               \
+    } while( 0 )
+
+/**
+ * croutine. h
+ * @code{c}
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvItemToQueue,
+ *                          BaseType_t xCoRoutinePreviouslyWoken
+ *                     )
+ * @endcode
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ * @code{c}
+ * // A co-routine that blocks on a queue waiting for characters to be received.
+ * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * char cRxedChar;
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Wait for data to become available on the queue.  This assumes the
+ *       // queue xCommsRxQueue has already been created!
+ *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *       // Was a character received?
+ *       if( xResult == pdPASS )
+ *       {
+ *           // Process the character here.
+ *       }
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to send characters received on a serial port to
+ * // a co-routine.
+ * void vUART_ISR( void )
+ * {
+ * char cRxedChar;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   // We loop around reading characters until there are none left in the UART.
+ *   while( UART_RX_REG_NOT_EMPTY() )
+ *   {
+ *       // Obtain the character from the UART.
+ *       cRxedChar = UART_RX_REG;
+ *
+ *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+ *       // the first time around the loop.  If the post causes a co-routine
+ *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+ *       // In this manner we can ensure that if more than one co-routine is
+ *       // blocked on the queue only one is woken by this ISR no matter how
+ *       // many characters are posted to the queue.
+ *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+ *   }
+ * }
+ * @endcode
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \
+    xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * @code{c}
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvBuffer,
+ *                          BaseType_t * pxCoRoutineWoken
+ *                     )
+ * @endcode
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ * @code{c}
+ * // A co-routine that posts a character to a queue then blocks for a fixed
+ * // period.  The character is incremented each time.
+ * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // cChar holds its value while this co-routine is blocked and must therefore
+ * // be declared static.
+ * static char cCharToTx = 'a';
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Send the next character to the queue.
+ *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+ *
+ *       if( xResult == pdPASS )
+ *       {
+ *           // The character was successfully posted to the queue.
+ *       }
+ *       else
+ *       {
+ *          // Could not post the character to the queue.
+ *       }
+ *
+ *       // Enable the UART Tx interrupt to cause an interrupt in this
+ *       // hypothetical UART.  The interrupt will obtain the character
+ *       // from the queue and send it.
+ *       ENABLE_RX_INTERRUPT();
+ *
+ *       // Increment to the next character then block for a fixed period.
+ *       // cCharToTx will maintain its value across the delay as it is
+ *       // declared static.
+ *       cCharToTx++;
+ *       if( cCharToTx > 'x' )
+ *       {
+ *          cCharToTx = 'a';
+ *       }
+ *       crDELAY( 100 );
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to receive characters to send on a UART.
+ * void vUART_ISR( void )
+ * {
+ * char cCharToTx;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   while( UART_TX_REG_EMPTY() )
+ *   {
+ *       // Are there any characters in the queue waiting to be sent?
+ *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+ *       // is woken by the post - ensuring that only a single co-routine is
+ *       // woken no matter how many times we go around this loop.
+ *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+ *       {
+ *           SEND_CHARACTER( cCharToTx );
+ *       }
+ *   }
+ * }
+ * @endcode
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \
+    xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here.  The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
+                                 List_t * pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* CO_ROUTINE_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/deprecated_definitions.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/deprecated_definitions.h
new file mode 100644
index 0000000000..6a9e548650
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/deprecated_definitions.h
@@ -0,0 +1,281 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+ * pre-processor definition was used to ensure the pre-processor found the correct
+ * portmacro.h file for the port being used.  That scheme was deprecated in favour
+ * of setting the compiler's include path such that it found the correct
+ * portmacro.h file - removing the need for the constant and allowing the
+ * portmacro.h file to be located anywhere in relation to the port being used.  The
+ * definitions below remain in the code for backward compatibility only.  New
+ * projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+    #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+    #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+    #include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+    #include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+    #include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+    #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+    #include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+    #include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+    #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+    #include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+    #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+    #include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+    #include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+    #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+    #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+    #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+    #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+    #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+    #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+    #include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+    #include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+    #include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+    #include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+    #include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+    #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+    #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+    #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+    #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+    #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+    #include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+    #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+    #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+    #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+    #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+    #include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+
+/* A short file name has to be used in place of the normal
+ * FreeRTOSConfig.h when using the Borland compiler. */
+    #include "frconfig.h"
+    #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+
+/* A short file name has to be used in place of the normal
+ * FreeRTOSConfig.h when using the Borland compiler. */
+    #include "frconfig.h"
+    #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef __GNUC__
+    #ifdef __AVR32_AVR32A__
+        #include "portmacro.h"
+    #endif
+#endif
+
+#ifdef __ICCAVR32__
+    #ifdef __CORE__
+        #if __CORE__ == __AVR32A__
+            #include "portmacro.h"
+        #endif
+    #endif
+#endif
+
+#ifdef __91467D
+    #include "portmacro.h"
+#endif
+
+#ifdef __96340
+    #include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+    #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+    #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/event_groups.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/event_groups.h
new file mode 100644
index 0000000000..75d6ce5257
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/event_groups.h
@@ -0,0 +1,827 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+/* The following bit fields convey control information in a task's event list
+ * item value.  It is important they don't clash with the
+ * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00U )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000UL )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000UL )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000UL )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000UL )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000ULL )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000ULL )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000ULL )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000ULL )
+#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning.  For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc.  A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active.  To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose.  This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced.  For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+struct EventGroupDef_t;
+typedef struct EventGroupDef_t   * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configTICK_TYPE_WIDTH_IN_BITS (16 bits if set to 0,
+ * 32 bits if set to 1, 64 bits if set to 2.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t               EventBits_t;
+
+/**
+ * event_groups.h
+ * @code{c}
+ * EventGroupHandle_t xEventGroupCreate( void );
+ * @endcode
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGroupCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
+ * using xEventGroupCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configTICK_TYPE_WIDTH_IN_BITS setting in FreeRTOSConfig.h.  If
+ * configTICK_TYPE_WIDTH_IN_BITS is 0 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configTICK_TYPE_WIDTH_IN_BITS is set to 1 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  If configTICK_TYPE_WIDTH_IN_BITS is set to 2 then
+ * each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type
+ * is used to store event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned.  See https://www.FreeRTOS.org/a00111.html
+ *
+ * Example usage:
+ * @code{c}
+ *  // Declare a variable to hold the created event group.
+ *  EventGroupHandle_t xCreatedEventGroup;
+ *
+ *  // Attempt to create the event group.
+ *  xCreatedEventGroup = xEventGroupCreate();
+ *
+ *  // Was the event group created successfully?
+ *  if( xCreatedEventGroup == NULL )
+ *  {
+ *      // The event group was not created because there was insufficient
+ *      // FreeRTOS heap available.
+ *  }
+ *  else
+ *  {
+ *      // The event group was created.
+ *  }
+ * @endcode
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ * @code{c}
+ * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ * @endcode
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGroupCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
+ * using xEventGroupCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configTICK_TYPE_WIDTH_IN_BITS setting in FreeRTOSConfig.h.  If
+ * configTICK_TYPE_WIDTH_IN_BITS is 0 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configTICK_TYPE_WIDTH_IN_BITS is set to 1 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  If configTICK_TYPE_WIDTH_IN_BITS is set to 2 then
+ * each event group has 56 usable bits (bit 0 to bit 53).  The EventBits_t type
+ * is used to store event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @code{c}
+ *  // StaticEventGroup_t is a publicly accessible structure that has the same
+ *  // size and alignment requirements as the real event group structure.  It is
+ *  // provided as a mechanism for applications to know the size of the event
+ *  // group (which is dependent on the architecture and configuration file
+ *  // settings) without breaking the strict data hiding policy by exposing the
+ *  // real event group internals.  This StaticEventGroup_t variable is passed
+ *  // into the xSemaphoreCreateEventGroupStatic() function and is used to store
+ *  // the event group's data structures
+ *  StaticEventGroup_t xEventGroupBuffer;
+ *
+ *  // Create the event group without dynamically allocating any memory.
+ *  xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+ * @endcode
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  EventBits_t xEventGroupWaitBits(    EventGroupHandle_t xEventGroup,
+ *                                      const EventBits_t uxBitsToWaitFor,
+ *                                      const BaseType_t xClearOnExit,
+ *                                      const BaseType_t xWaitForAllBits,
+ *                                      const TickType_t xTicksToWait );
+ * @endcode
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout).  If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires.  If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires.  The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set. A value of portMAX_DELAY can be used to block
+ * indefinitely (provided INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+ * @code{c}
+ * #define BIT_0 ( 1 << 0 )
+ * #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *      // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+ *      // the event group.  Clear the bits before exiting.
+ *      uxBits = xEventGroupWaitBits(
+ *                  xEventGroup,    // The event group being tested.
+ *                  BIT_0 | BIT_4,  // The bits within the event group to wait for.
+ *                  pdTRUE,         // BIT_0 and BIT_4 should be cleared before returning.
+ *                  pdFALSE,        // Don't wait for both bits, either bit will do.
+ *                  xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // xEventGroupWaitBits() returned because both bits were set.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_0 was set.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_4 was set.
+ *      }
+ *      else
+ *      {
+ *          // xEventGroupWaitBits() returned because xTicksToWait ticks passed
+ *          // without either BIT_0 or BIT_4 becoming set.
+ *      }
+ * }
+ * @endcode
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 const BaseType_t xClearOnExit,
+                                 const BaseType_t xWaitForAllBits,
+                                 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ * @endcode
+ *
+ * Clear bits within an event group.  This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+ * @code{c}
+ * #define BIT_0 ( 1 << 0 )
+ * #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupClearBits(
+ *                              xEventGroup,    // The event group being updated.
+ *                              BIT_0 | BIT_4 );// The bits being cleared.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+ *          // called.  Both will now be clear (not set).
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 were set in the first place.
+ *      }
+ * }
+ * @endcode
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                  const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ * @endcode
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts.  As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @note If this function returns pdPASS then the timer task is ready to run
+ * and a portYIELD_FROM_ISR(pdTRUE) should be executed to perform the needed
+ * clear on the event group.  This behavior is different from
+ * xEventGroupSetBitsFromISR because the parameter xHigherPriorityTaskWoken is
+ * not present.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+ * @code{c}
+ * #define BIT_0 ( 1 << 0 )
+ * #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupClearBitsFromISR(
+ *                          xEventGroup,     // The event group being updated.
+ *                          BIT_0 | BIT_4 ); // The bits being set.
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // The message was posted successfully.
+ *          portYIELD_FROM_ISR(pdTRUE);
+ *      }
+ * }
+ * @endcode
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+#else
+    #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
+    xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL )
+#endif
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ * @endcode
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns.  There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+ * @code{c}
+ * #define BIT_0 ( 1 << 0 )
+ * #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupSetBits(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4 );// The bits being set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 remained set when the function returned.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 remained set when the function returned, but bit 4 was
+ *          // cleared.  It might be that bit 4 was cleared automatically as a
+ *          // task that was waiting for bit 4 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 remained set when the function returned, but bit 0 was
+ *          // cleared.  It might be that bit 0 was cleared automatically as a
+ *          // task that was waiting for bit 0 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 remained set.  It might be that a task
+ *          // was waiting for both of the bits to be set, and the bits were
+ *          // cleared as the task left the Blocked state.
+ *      }
+ * }
+ * @endcode
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+ * @code{c}
+ * #define BIT_0 ( 1 << 0 )
+ * #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken, xResult;
+ *
+ *      // xHigherPriorityTaskWoken must be initialised to pdFALSE.
+ *      xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupSetBitsFromISR(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4   // The bits being set.
+ *                          &xHigherPriorityTaskWoken );
+ *
+ *      // Was the message posted successfully?
+ *      if( xResult == pdPASS )
+ *      {
+ *          // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *          // switch should be requested.  The macro used is port specific and
+ *          // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *          // refer to the documentation page for the port being used.
+ *          portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *      }
+ * }
+ * @endcode
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToSet,
+                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+    #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
+    xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) )
+#endif
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,
+ *                                  const EventBits_t uxBitsToSet,
+ *                                  const EventBits_t uxBitsToWaitFor,
+ *                                  TickType_t xTicksToWait );
+ * @endcode
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group.  This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time.  In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ * @code{c}
+ * // Bits used by the three tasks.
+ * #define TASK_0_BIT     ( 1 << 0 )
+ * #define TASK_1_BIT     ( 1 << 1 )
+ * #define TASK_2_BIT     ( 1 << 2 )
+ *
+ * #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+ *
+ * // Use an event group to synchronise three tasks.  It is assumed this event
+ * // group has already been created elsewhere.
+ * EventGroupHandle_t xEventBits;
+ *
+ * void vTask0( void *pvParameters )
+ * {
+ * EventBits_t uxReturn;
+ * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 0 in the event flag to note this task has reached the
+ *      // sync point.  The other two tasks will set the other two bits defined
+ *      // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+ *      // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+ *      // for this to happen.
+ *      uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+ *
+ *      if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+ *      {
+ *          // All three tasks reached the synchronisation point before the call
+ *          // to xEventGroupSync() timed out.
+ *      }
+ *  }
+ * }
+ *
+ * void vTask1( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 1 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *   }
+ * }
+ *
+ * void vTask2( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 2 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *  }
+ * }
+ *
+ * @endcode
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+                             const EventBits_t uxBitsToSet,
+                             const EventBits_t uxBitsToWaitFor,
+                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ * @endcode
+ *
+ * Returns the current value of the bits in an event group.  This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup )    xEventGroupClearBits( ( xEventGroup ), 0 )
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ * @endcode
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ * @endcode
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate().  Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * @code{c}
+ *  BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
+ *                                         StaticEventGroup_t ** ppxEventGroupBuffer );
+ * @endcode
+ *
+ * Retrieve a pointer to a statically created event groups's data structure
+ * buffer. It is the same buffer that is supplied at the time of creation.
+ *
+ * @param xEventGroup The event group for which to retrieve the buffer.
+ *
+ * @param ppxEventGroupBuffer Used to return a pointer to the event groups's
+ * data structure buffer.
+ *
+ * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
+                                           StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void * pvEventGroup,
+                                 uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void * pvEventGroup,
+                                   uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION;
+    void vEventGroupSetNumber( void * xEventGroup,
+                               UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* EVENT_GROUPS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/freertos_tasks_c_additions.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/freertos_tasks_c_additions.h
new file mode 100644
index 0000000000..99fd87a61f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/freertos_tasks_c_additions.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2017-2019, 2024 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* freertos_tasks_c_additions.h Rev. 1.4 */
+#ifndef FREERTOS_TASKS_C_ADDITIONS_H
+#define FREERTOS_TASKS_C_ADDITIONS_H
+
+#include <stdint.h>
+
+#if (configUSE_TRACE_FACILITY == 0)
+#error "configUSE_TRACE_FACILITY must be enabled"
+#endif
+
+#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1
+#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 4
+
+/* NOTE!!
+ * Default to a FreeRTOS version which didn't include these macros. FreeRTOS
+ * v7.5.3 is used here.
+ */
+#ifndef tskKERNEL_VERSION_BUILD
+#define tskKERNEL_VERSION_BUILD 3
+#endif
+#ifndef tskKERNEL_VERSION_MINOR
+#define tskKERNEL_VERSION_MINOR 5
+#endif
+#ifndef tskKERNEL_VERSION_MAJOR
+#define tskKERNEL_VERSION_MAJOR 7
+#endif
+
+/* NOTE!!
+ * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value
+ * 1 - 5 which corresponds to the following schemes:
+ *
+ * heap_1 - the very simplest, does not permit memory to be freed
+ * heap_2 - permits memory to be freed, but not does coalescence adjacent free
+ *          blocks.
+ * heap_3 - simply wraps the standard malloc() and free() for thread safety
+ * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes
+ *          absolute address placement option
+ * heap_5 - as per heap_4, with the ability to span the heap across
+ *          multiple nonOadjacent memory areas
+ */
+#ifndef configFRTOS_MEMORY_SCHEME
+#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */
+#endif
+
+#if ((configFRTOS_MEMORY_SCHEME > 5) || (configFRTOS_MEMORY_SCHEME < 1))
+#error "Invalid configFRTOS_MEMORY_SCHEME setting!"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t FreeRTOSDebugConfig[];
+
+/* NOTES!!
+ * IAR documentation is confusing. It suggests the data must be statically
+ * linked, and the #pragma placed immediately before the symbol definition.
+ * The IAR supplied examples violate both "rules", so this is a best guess.
+ */
+
+#if (tskKERNEL_VERSION_MAJOR >= 11) || ((tskKERNEL_VERSION_MAJOR >= 10) && (tskKERNEL_VERSION_MINOR >= 2))
+#if defined(__GNUC__)
+char *const portArch_Name __attribute__((section(".rodata"))) = portARCH_NAME;
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+char *const portArch_Name __attribute__((used)) = portARCH_NAME;
+#elif defined(__IAR_SYSTEMS_ICC__)
+char *const portArch_Name = portARCH_NAME;
+#pragma required=portArch_Name
+#endif
+#else
+char *const portArch_Name = NULL;
+#endif	// tskKERNEL_VERSION_MAJOR
+
+#if defined(__GNUC__)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((section(".rodata"))) =
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((used)) =
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma required=FreeRTOSDebugConfig
+const uint8_t FreeRTOSDebugConfig[] =
+#endif
+{
+    FREERTOS_DEBUG_CONFIG_MAJOR_VERSION,
+    FREERTOS_DEBUG_CONFIG_MINOR_VERSION,
+    tskKERNEL_VERSION_MAJOR,
+    tskKERNEL_VERSION_MINOR,
+    tskKERNEL_VERSION_BUILD,
+    configFRTOS_MEMORY_SCHEME,
+    (uint8_t)offsetof(struct tskTaskControlBlock, pxTopOfStack),
+#if (tskKERNEL_VERSION_MAJOR > 8)
+    (uint8_t)offsetof(struct tskTaskControlBlock, xStateListItem),
+#else
+    (uint8_t)offsetof(struct tskTaskControlBlock, xGenericListItem),
+#endif
+    (uint8_t)offsetof(struct tskTaskControlBlock, xEventListItem),
+    (uint8_t)offsetof(struct tskTaskControlBlock, pxStack),
+    (uint8_t)offsetof(struct tskTaskControlBlock, pcTaskName),
+    (uint8_t)offsetof(struct tskTaskControlBlock, uxTCBNumber),
+    (uint8_t)offsetof(struct tskTaskControlBlock, uxTaskNumber),
+    configMAX_TASK_NAME_LEN,
+    configMAX_PRIORITIES,
+    configENABLE_MPU,
+    configENABLE_FPU,
+    configENABLE_TRUSTZONE,
+    configRUN_FREERTOS_SECURE_ONLY,
+    configNUMBER_OF_CORES,
+#if (configNUMBER_OF_CORES > 1)
+    (uint8_t)sizeof(struct tskTaskControlBlock),
+    (uint8_t)offsetof(struct tskTaskControlBlock, xTaskRunState),
+    0, 0,       // Padding
+#else
+    0, 0, 0, 0, // Padding
+#endif // configNUMBER_OF_CORES > 1
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FREERTOS_TASKS_C_ADDITIONS_H
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/list.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/list.h
new file mode 100644
index 0000000000..b74a8152c1
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/list.h
@@ -0,0 +1,503 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * ascending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+
+#ifndef LIST_H
+#define LIST_H
+
+#ifndef INC_FREERTOS_H
+    #error "FreeRTOS.h must be included before list.h"
+#endif
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile.  However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour.  The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended.  That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation.  It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler.  If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+    #define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* Macros that can be used to place known values within the list structures,
+ * then check that the known values do not get corrupted during the execution of
+ * the application.   These may catch the list data structures being overwritten in
+ * memory.  They will not catch data errors caused by incorrect configuration or
+ * use of FreeRTOS.*/
+#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+    /* Define the macros to do nothing. */
+    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+    #define listTEST_LIST_INTEGRITY( pxList )
+#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */
+    /* Define macros that add new members into the list structures. */
+    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     TickType_t xListItemIntegrityValue1;
+    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE    TickType_t xListItemIntegrityValue2;
+    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE          TickType_t xListIntegrityValue1;
+    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE         TickType_t xListIntegrityValue2;
+
+/* Define macros that set the new structure members to known values. */
+    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )     ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )    ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )              ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )              ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+/* Define macros that will assert if one of the structure members does not
+ * contain its expected value. */
+    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )                      configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+    #define listTEST_LIST_INTEGRITY( pxList )                           configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST;
+struct xLIST_ITEM
+{
+    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE           /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    configLIST_VOLATILE TickType_t xItemValue;          /**< The value being listed.  In most cases this is used to sort the list in ascending order. */
+    struct xLIST_ITEM * configLIST_VOLATILE pxNext;     /**< Pointer to the next ListItem_t in the list. */
+    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /**< Pointer to the previous ListItem_t in the list. */
+    void * pvOwner;                                     /**< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+    struct xLIST * configLIST_VOLATILE pxContainer;     /**< Pointer to the list in which this list item is placed (if any). */
+    listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE          /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t;
+
+#if ( configUSE_MINI_LIST_ITEM == 1 )
+    struct xMINI_LIST_ITEM
+    {
+        listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+        configLIST_VOLATILE TickType_t xItemValue;
+        struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+        struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+    };
+    typedef struct xMINI_LIST_ITEM MiniListItem_t;
+#else
+    typedef struct xLIST_ITEM      MiniListItem_t;
+#endif
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+    listFIRST_LIST_INTEGRITY_CHECK_VALUE      /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    volatile UBaseType_t uxNumberOfItems;
+    ListItem_t * configLIST_VOLATILE pxIndex; /**< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+    MiniListItem_t xListEnd;                  /**< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+    listSECOND_LIST_INTEGRITY_CHECK_VALUE     /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )    ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem )             ( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in ascending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )     ( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item.  The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )             ( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )        ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList )                      ( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the next list item.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem )                        ( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList )                      ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )                       ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )                 ( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                           \
+    do {                                                                                       \
+        List_t * const pxConstList = ( pxList );                                               \
+        /* Increment the index to the next item and return the item, ensuring */               \
+        /* we don't return the marker used at the end of the list.  */                         \
+        ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                           \
+        if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
+        {                                                                                      \
+            ( pxConstList )->pxIndex = ( pxConstList )->xListEnd.pxNext;                       \
+        }                                                                                      \
+        ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \
+    } while( 0 )
+
+/*
+ * Version of uxListRemove() that does not return a value.  Provided as a slight
+ * optimisation for xTaskIncrementTick() by being inline.
+ *
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page listREMOVE_ITEM listREMOVE_ITEM
+ * \ingroup LinkedList
+ */
+#define listREMOVE_ITEM( pxItemToRemove ) \
+    do {                                  \
+        /* The list item knows which list it is in.  Obtain the list from the list \
+         * item. */                                                              \
+        List_t * const pxList = ( pxItemToRemove )->pxContainer;                 \
+                                                                                 \
+        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \
+        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;     \
+        /* Make sure the index is left pointing to a valid item. */              \
+        if( pxList->pxIndex == ( pxItemToRemove ) )                              \
+        {                                                                        \
+            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                    \
+        }                                                                        \
+                                                                                 \
+        ( pxItemToRemove )->pxContainer = NULL;                                  \
+        ( pxList->uxNumberOfItems )--;                                           \
+    } while( 0 )
+
+/*
+ * Inline version of vListInsertEnd() to provide slight optimisation for
+ * xTaskIncrementTick().
+ *
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page listINSERT_END listINSERT_END
+ * \ingroup LinkedList
+ */
+#define listINSERT_END( pxList, pxNewListItem )           \
+    do {                                                  \
+        ListItem_t * const pxIndex = ( pxList )->pxIndex; \
+                                                          \
+        /* Only effective when configASSERT() is also defined, these tests may catch \
+         * the list data structures being overwritten in memory.  They will not catch \
+         * data errors caused by incorrect configuration or use of FreeRTOS. */ \
+        listTEST_LIST_INTEGRITY( ( pxList ) );                                  \
+        listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) );                      \
+                                                                                \
+        /* Insert a new list item into ( pxList ), but rather than sort the list, \
+         * makes the new list item the last item to be removed by a call to \
+         * listGET_OWNER_OF_NEXT_ENTRY(). */                 \
+        ( pxNewListItem )->pxNext = pxIndex;                 \
+        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \
+                                                             \
+        pxIndex->pxPrevious->pxNext = ( pxNewListItem );     \
+        pxIndex->pxPrevious = ( pxNewListItem );             \
+                                                             \
+        /* Remember which list the item is in. */            \
+        ( pxNewListItem )->pxContainer = ( pxList );         \
+                                                             \
+        ( ( pxList )->uxNumberOfItems )++;                   \
+    } while( 0 )
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )            ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem )    ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem )            ( ( pxListItem )->pxContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList )                ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (ascending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList,
+                  ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList,
+                     ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* ifndef LIST_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/message_buffer.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/message_buffer.h
new file mode 100644
index 0000000000..0c04d41298
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/message_buffer.h
@@ -0,0 +1,887 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*
+ * Message buffers build functionality on top of FreeRTOS stream buffers.
+ * Whereas stream buffers are used to send a continuous stream of data from one
+ * task or interrupt to another, message buffers are used to send variable
+ * length discrete messages from one task or interrupt to another.  Their
+ * implementation is light weight, making them particularly suited for interrupt
+ * to task and core to core communication scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * timeout to 0.
+ *
+ * Message buffers hold variable length messages.  To enable that, when a
+ * message is written to the message buffer an additional sizeof( size_t ) bytes
+ * are also written to store the message's length (that happens internally, with
+ * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so writing a 10 byte message to a message buffer on a 32-bit
+ * architecture will actually reduce the available space in the message buffer
+ * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
+ * of the message).
+ */
+
+#ifndef FREERTOS_MESSAGE_BUFFER_H
+#define FREERTOS_MESSAGE_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include message_buffer.h"
+#endif
+
+/* Message buffers are built onto of stream buffers. */
+#include "stream_buffer.h"
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * Type by which message buffers are referenced.  For example, a call to
+ * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
+ * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
+ * etc. Message buffer is essentially built as a stream buffer hence its handle
+ * is also set to same type as a stream buffer handle.
+ */
+typedef StreamBufferHandle_t MessageBufferHandle_t;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+ * @endcode
+ *
+ * Creates a new message buffer using dynamically allocated memory.  See
+ * xMessageBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes (not messages) the message
+ * buffer will be able to hold at any one time.  When a message is written to
+ * the message buffer an additional sizeof( size_t ) bytes are also written to
+ * store the message's length.  sizeof( size_t ) is typically 4 bytes on a
+ * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
+ * take up 14 bytes of message buffer space.
+ *
+ * @param pxSendCompletedCallback Callback invoked when a send operation to the
+ * message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
+ * is called without the parameter, then it will use the default implementation
+ * provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when a receive operation from
+ * the message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
+ * is called without the parameter, it will use the default implementation provided
+ * by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @return If NULL is returned, then the message buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the message buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the message buffer has been created successfully -
+ * the returned value should be stored as the handle to the created message
+ * buffer.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * void vAFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ * const size_t xMessageBufferSizeBytes = 100;
+ *
+ *  // Create a message buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the message buffer structure and the messages themselves is allocated
+ *  // dynamically.  Each message added to the buffer consumes an additional 4
+ *  // bytes which are used to hold the length of the message.
+ *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+ *
+ *  if( xMessageBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // message buffer.
+ *  }
+ *  else
+ *  {
+ *      // The message buffer was created successfully and can now be used.
+ *  }
+ *
+ * @endcode
+ * \defgroup xMessageBufferCreate xMessageBufferCreate
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreate( xBufferSizeBytes ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                                uint8_t *pucMessageBufferStorageArea,
+ *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
+ * @endcode
+ * Creates a new message buffer using statically allocated memory.  See
+ * xMessageBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucMessageBufferStorageArea parameter.  When a message is written to the
+ * message buffer an additional sizeof( size_t ) bytes are also written to store
+ * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so on most 32-bit architecture a 10 byte message will take up
+ * 14 bytes of message buffer space.  The maximum number of bytes that can be
+ * stored in the message buffer is actually (xBufferSizeBytes - 1).
+ *
+ * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes big.  This is the array to which messages are
+ * copied when they are written to the message buffer.
+ *
+ * @param pxStaticMessageBuffer Must point to a variable of type
+ * StaticMessageBuffer_t, which will be used to hold the message buffer's data
+ * structure.
+ *
+ * @param pxSendCompletedCallback Callback invoked when a new message is sent to the message buffer.
+ * If the parameter is NULL or xMessageBufferCreate() is called without the parameter, then it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when a message is read from a
+ * message buffer. If the parameter is NULL or xMessageBufferCreate() is called without the parameter, it will
+ * use the default implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @return If the message buffer is created successfully then a handle to the
+ * created message buffer is returned. If either pucMessageBufferStorageArea or
+ * pxStaticmessageBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * // Used to dimension the array used to hold the messages.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the messages within the message
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the message buffer structure.
+ * StaticMessageBuffer_t xMessageBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ),
+ *                                               ucStorageBuffer,
+ *                                               &xMessageBufferStruct );
+ *
+ *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+ *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+ *  // reference the created message buffer in other message buffer API calls.
+ *
+ *  // Other code that uses the message buffer can go here.
+ * }
+ *
+ * @endcode
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xMessageBufferGetStaticBuffers( MessageBufferHandle_t xMessageBuffer,
+ *                                            uint8_t ** ppucMessageBufferStorageArea,
+ *                                            StaticMessageBuffer_t ** ppxStaticMessageBuffer );
+ * @endcode
+ *
+ * Retrieve pointers to a statically created message buffer's data structure
+ * buffer and storage area buffer. These are the same buffers that are supplied
+ * at the time of creation.
+ *
+ * @param xMessageBuffer The message buffer for which to retrieve the buffers.
+ *
+ * @param ppucMessageBufferStorageArea Used to return a pointer to the
+ * message buffer's storage area buffer.
+ *
+ * @param ppxStaticMessageBuffer Used to return a pointer to the message
+ * buffer's data structure buffer.
+ *
+ * @return pdTRUE if buffers were retrieved, pdFALSE otherwise..
+ *
+ * \defgroup xMessageBufferGetStaticBuffers xMessageBufferGetStaticBuffers
+ * \ingroup MessageBufferManagement
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xMessageBufferGetStaticBuffers( xMessageBuffer, ppucMessageBufferStorageArea, ppxStaticMessageBuffer ) \
+    xStreamBufferGetStaticBuffers( ( xMessageBuffer ), ( ppucMessageBufferStorageArea ), ( ppxStaticMessageBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+ *                         const void *pvTxData,
+ *                         size_t xDataLengthBytes,
+ *                         TickType_t xTicksToWait );
+ * @endcode
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+ * @code{c}
+ * void vAFunction( MessageBufferHandle_t xMessageBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the message buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the message buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xMessageBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written.
+ *  }
+ *
+ *  // Send the string to the message buffer.  Return immediately if there is
+ *  // not enough space in the buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \
+    xStreamBufferSend( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( xTicksToWait ) )
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                const void *pvTxData,
+ *                                size_t xDataLengthBytes,
+ *                                BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+ * @code{c}
+ * // A message buffer that has already been created.
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the message buffer.
+ *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+ *                                          ( void * ) pcStringToSend,
+ *                                          strlen( pcStringToSend ),
+ *                                          &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \
+    xStreamBufferSendFromISR( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+ *                            void *pvRxData,
+ *                            size_t xBufferLengthBytes,
+ *                            TickType_t xTicksToWait );
+ * @endcode
+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+ * @code{c}
+ * void vAFunction( MessageBuffer_t xMessageBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive the next message from the message buffer.  Wait in the Blocked
+ *  // state (so not using any CPU processing time) for a maximum of 100ms for
+ *  // a message to become available.
+ *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+ *                                          ( void * ) ucRxData,
+ *                                          sizeof( ucRxData ),
+ *                                          xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ * }
+ * @endcode
+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \
+    xStreamBufferReceive( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( xTicksToWait ) )
+
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                   void *pvRxData,
+ *                                   size_t xBufferLengthBytes,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+ * @code{c}
+ * // A message buffer that has already been created.
+ * MessageBuffer_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next message from the message buffer.
+ *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \
+    xStreamBufferReceiveFromISR( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) \
+    vStreamBufferDelete( xMessageBuffer )
+
+/**
+ * message_buffer.h
+ * @code{c}
+ * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) \
+    xStreamBufferIsFull( xMessageBuffer )
+
+/**
+ * message_buffer.h
+ * @code{c}
+ * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) \
+    xStreamBufferIsEmpty( xMessageBuffer )
+
+/**
+ * message_buffer.h
+ * @code{c}
+ * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) \
+    xStreamBufferReset( xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+ * @code{c}
+ * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) \
+    xStreamBufferSpacesAvailable( xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) \
+    xStreamBufferSpacesAvailable( xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ * @code{c}
+ * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
+    xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xMessageBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
+    xStreamBufferSendCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * message_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xMessageBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
+    xStreamBufferReceiveCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    } /* extern "C" */
+#endif
+/* *INDENT-ON* */
+
+#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_prototypes.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_prototypes.h
new file mode 100644
index 0000000000..655ec861c8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_prototypes.h
@@ -0,0 +1,388 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+typedef struct xTaskGenericNotifyParams
+{
+    TaskHandle_t xTaskToNotify;
+    UBaseType_t uxIndexToNotify;
+    uint32_t ulValue;
+    eNotifyAction eAction;
+    uint32_t * pulPreviousNotificationValue;
+} xTaskGenericNotifyParams_t;
+
+typedef struct xTaskGenericNotifyWaitParams
+{
+    UBaseType_t uxIndexToWaitOn;
+    uint32_t ulBitsToClearOnEntry;
+    uint32_t ulBitsToClearOnExit;
+    uint32_t * pulNotificationValue;
+    TickType_t xTicksToWait;
+} xTaskGenericNotifyWaitParams_t;
+
+typedef struct xTimerGenericCommandFromTaskParams
+{
+    TimerHandle_t xTimer;
+    BaseType_t xCommandID;
+    TickType_t xOptionalValue;
+    BaseType_t * pxHigherPriorityTaskWoken;
+    TickType_t xTicksToWait;
+} xTimerGenericCommandFromTaskParams_t;
+
+typedef struct xEventGroupWaitBitsParams
+{
+    EventGroupHandle_t xEventGroup;
+    EventBits_t uxBitsToWaitFor;
+    BaseType_t xClearOnExit;
+    BaseType_t xWaitForAllBits;
+    TickType_t xTicksToWait;
+} xEventGroupWaitBitsParams_t;
+
+/* MPU versions of task.h API functions. */
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                   UBaseType_t uxIndexToNotify,
+                                   uint32_t ulValue,
+                                   eNotifyAction eAction,
+                                   uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                       uint32_t ulBitsToClearOnEntry,
+                                       uint32_t ulBitsToClearOnExit,
+                                       uint32_t * pulNotificationValue,
+                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                      BaseType_t xClearCountOnExit,
+                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                            UBaseType_t uxIndexToClear,
+                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+
+/* Privileged only wrappers for Task APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName,
+                            const uint16_t usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName,
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask,
+                           UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                             void * pvParameter ) PRIVILEGED_FUNCTION;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
+                                      TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask,
+                                      StackType_t ** ppuxStackBuffer,
+                                      StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
+                                          UBaseType_t uxIndexToNotify,
+                                          uint32_t ulValue,
+                                          eNotifyAction eAction,
+                                          uint32_t * pulPreviousNotificationValue,
+                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+void MPU_vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
+                                        UBaseType_t uxIndexToNotify,
+                                        BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                  const void * const pvItemToQueue,
+                                  TickType_t xTicksToWait,
+                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                              void * const pvBuffer,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                           void * const pvBuffer,
+                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                         TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* Privileged only wrappers for Queue APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+void MPU_vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                       const UBaseType_t uxItemSize,
+                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                             const UBaseType_t uxItemSize,
+                                             uint8_t * pucQueueStorage,
+                                             StaticQueue_t * pxStaticQueue,
+                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
+                                   BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
+                                              uint8_t ** ppucQueueStorage,
+                                              StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueGenericSendFromISR( QueueHandle_t xQueue,
+                                         const void * const pvItemToQueue,
+                                         BaseType_t * const pxHigherPriorityTaskWoken,
+                                         const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueGiveFromISR( QueueHandle_t xQueue,
+                                  BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t xQueue,
+                                  void * const pvBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueReceiveFromISR( QueueHandle_t xQueue,
+                                     void * const pvBuffer,
+                                     BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+TaskHandle_t MPU_xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* MPU versions of timers.h API functions. */
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                           void * pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                              const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+/* Privileged only wrappers for Timer APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
+                                const TickType_t xTimerPeriodInTicks,
+                                const UBaseType_t uxAutoReload,
+                                void * const pvTimerID,
+                                TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
+                                      const TickType_t xTimerPeriodInTicks,
+                                      const UBaseType_t uxAutoReload,
+                                      void * const pvTimerID,
+                                      TimerCallbackFunction_t pxCallbackFunction,
+                                      StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer,
+                                      StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                            const BaseType_t xCommandID,
+                                            const TickType_t xOptionalValue,
+                                            BaseType_t * const pxHigherPriorityTaskWoken,
+                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/* MPU versions of event_group.h API functions. */
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     const BaseType_t xClearOnExit,
+                                     const BaseType_t xWaitForAllBits,
+                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToSet,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
+    void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                   UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
+#endif /* ( configUSE_TRACE_FACILITY == 1 )*/
+
+/* Privileged only wrappers for Event Group APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
+                                           StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToSet,
+                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                              const void * pvTxData,
+                              size_t xDataLengthBytes,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                 void * pvRxData,
+                                 size_t xBufferLengthBytes,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+/* Privileged only wrappers for Stream Buffer APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                     size_t xTriggerLevelBytes,
+                                                     BaseType_t xIsMessageBuffer,
+                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xIsMessageBuffer,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers,
+                                              uint8_t * ppucStreamBufferStorageArea,
+                                              StaticStreamBuffer_t * ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                     const void * pvTxData,
+                                     size_t xDataLengthBytes,
+                                     BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                        void * pvRxData,
+                                        size_t xBufferLengthBytes,
+                                        BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                  BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                     BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+#endif /* MPU_PROTOTYPES_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_syscall_numbers.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_syscall_numbers.h
new file mode 100644
index 0000000000..96929f2c34
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_syscall_numbers.h
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef MPU_SYSCALL_NUMBERS_H
+#define MPU_SYSCALL_NUMBERS_H
+
+/* Numbers assigned to various system calls. */
+#define SYSTEM_CALL_xTaskGenericNotify                     0
+#define SYSTEM_CALL_xTaskGenericNotifyWait                 1
+#define SYSTEM_CALL_xTimerGenericCommandFromTask           2
+#define SYSTEM_CALL_xEventGroupWaitBits                    3
+#define SYSTEM_CALL_xTaskDelayUntil                        4
+#define SYSTEM_CALL_xTaskAbortDelay                        5
+#define SYSTEM_CALL_vTaskDelay                             6
+#define SYSTEM_CALL_uxTaskPriorityGet                      7
+#define SYSTEM_CALL_eTaskGetState                          8
+#define SYSTEM_CALL_vTaskGetInfo                           9
+#define SYSTEM_CALL_xTaskGetIdleTaskHandle                 10
+#define SYSTEM_CALL_vTaskSuspend                           11
+#define SYSTEM_CALL_vTaskResume                            12
+#define SYSTEM_CALL_xTaskGetTickCount                      13
+#define SYSTEM_CALL_uxTaskGetNumberOfTasks                 14
+#define SYSTEM_CALL_ulTaskGetRunTimeCounter                15
+#define SYSTEM_CALL_ulTaskGetRunTimePercent                16
+#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent            17
+#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter            18
+#define SYSTEM_CALL_vTaskSetApplicationTaskTag             19
+#define SYSTEM_CALL_xTaskGetApplicationTaskTag             20
+#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer      21
+#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer     22
+#define SYSTEM_CALL_uxTaskGetSystemState                   23
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark            24
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2           25
+#define SYSTEM_CALL_xTaskGetCurrentTaskHandle              26
+#define SYSTEM_CALL_xTaskGetSchedulerState                 27
+#define SYSTEM_CALL_vTaskSetTimeOutState                   28
+#define SYSTEM_CALL_xTaskCheckForTimeOut                   29
+#define SYSTEM_CALL_ulTaskGenericNotifyTake                30
+#define SYSTEM_CALL_xTaskGenericNotifyStateClear           31
+#define SYSTEM_CALL_ulTaskGenericNotifyValueClear          32
+#define SYSTEM_CALL_xQueueGenericSend                      33
+#define SYSTEM_CALL_uxQueueMessagesWaiting                 34
+#define SYSTEM_CALL_uxQueueSpacesAvailable                 35
+#define SYSTEM_CALL_xQueueReceive                          36
+#define SYSTEM_CALL_xQueuePeek                             37
+#define SYSTEM_CALL_xQueueSemaphoreTake                    38
+#define SYSTEM_CALL_xQueueGetMutexHolder                   39
+#define SYSTEM_CALL_xQueueTakeMutexRecursive               40
+#define SYSTEM_CALL_xQueueGiveMutexRecursive               41
+#define SYSTEM_CALL_xQueueSelectFromSet                    42
+#define SYSTEM_CALL_xQueueAddToSet                         43
+#define SYSTEM_CALL_vQueueAddToRegistry                    44
+#define SYSTEM_CALL_vQueueUnregisterQueue                  45
+#define SYSTEM_CALL_pcQueueGetName                         46
+#define SYSTEM_CALL_pvTimerGetTimerID                      47
+#define SYSTEM_CALL_vTimerSetTimerID                       48
+#define SYSTEM_CALL_xTimerIsTimerActive                    49
+#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle         50
+#define SYSTEM_CALL_pcTimerGetName                         51
+#define SYSTEM_CALL_vTimerSetReloadMode                    52
+#define SYSTEM_CALL_xTimerGetReloadMode                    53
+#define SYSTEM_CALL_uxTimerGetReloadMode                   54
+#define SYSTEM_CALL_xTimerGetPeriod                        55
+#define SYSTEM_CALL_xTimerGetExpiryTime                    56
+#define SYSTEM_CALL_xEventGroupClearBits                   57
+#define SYSTEM_CALL_xEventGroupSetBits                     58
+#define SYSTEM_CALL_xEventGroupSync                        59
+#define SYSTEM_CALL_uxEventGroupGetNumber                  60
+#define SYSTEM_CALL_vEventGroupSetNumber                   61
+#define SYSTEM_CALL_xStreamBufferSend                      62
+#define SYSTEM_CALL_xStreamBufferReceive                   63
+#define SYSTEM_CALL_xStreamBufferIsFull                    64
+#define SYSTEM_CALL_xStreamBufferIsEmpty                   65
+#define SYSTEM_CALL_xStreamBufferSpacesAvailable           66
+#define SYSTEM_CALL_xStreamBufferBytesAvailable            67
+#define SYSTEM_CALL_xStreamBufferSetTriggerLevel           68
+#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes    69
+#define NUM_SYSTEM_CALLS                                   70  /* Total number of system calls. */
+
+#endif /* MPU_SYSCALL_NUMBERS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_wrappers.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_wrappers.h
new file mode 100644
index 0000000000..d4f67b749f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/mpu_wrappers.h
@@ -0,0 +1,286 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+ * only for ports that are using the MPU. */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+ * included from queue.c or task.c to prevent it from having an effect within
+ * those files. */
+    #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/*
+ * Map standard (non MPU) API functions to equivalents that start
+ * "MPU_".  This will cause the application code to call the MPU_
+ * version, which wraps the non-MPU version with privilege promoting
+ * then demoting code, so the kernel code always runs will full
+ * privileges.
+ */
+
+/* Map standard task.h API functions to the MPU equivalents. */
+        #define vTaskDelay                            MPU_vTaskDelay
+        #define xTaskDelayUntil                       MPU_xTaskDelayUntil
+        #define xTaskAbortDelay                       MPU_xTaskAbortDelay
+        #define uxTaskPriorityGet                     MPU_uxTaskPriorityGet
+        #define eTaskGetState                         MPU_eTaskGetState
+        #define vTaskGetInfo                          MPU_vTaskGetInfo
+        #define vTaskSuspend                          MPU_vTaskSuspend
+        #define vTaskResume                           MPU_vTaskResume
+        #define xTaskGetTickCount                     MPU_xTaskGetTickCount
+        #define uxTaskGetNumberOfTasks                MPU_uxTaskGetNumberOfTasks
+        #define uxTaskGetStackHighWaterMark           MPU_uxTaskGetStackHighWaterMark
+        #define uxTaskGetStackHighWaterMark2          MPU_uxTaskGetStackHighWaterMark2
+        #define vTaskSetApplicationTaskTag            MPU_vTaskSetApplicationTaskTag
+        #define xTaskGetApplicationTaskTag            MPU_xTaskGetApplicationTaskTag
+        #define vTaskSetThreadLocalStoragePointer     MPU_vTaskSetThreadLocalStoragePointer
+        #define pvTaskGetThreadLocalStoragePointer    MPU_pvTaskGetThreadLocalStoragePointer
+        #define xTaskGetIdleTaskHandle                MPU_xTaskGetIdleTaskHandle
+        #define uxTaskGetSystemState                  MPU_uxTaskGetSystemState
+        #define ulTaskGetIdleRunTimeCounter           MPU_ulTaskGetIdleRunTimeCounter
+        #define ulTaskGetIdleRunTimePercent           MPU_ulTaskGetIdleRunTimePercent
+        #define xTaskGenericNotify                    MPU_xTaskGenericNotify
+        #define xTaskGenericNotifyWait                MPU_xTaskGenericNotifyWait
+        #define ulTaskGenericNotifyTake               MPU_ulTaskGenericNotifyTake
+        #define xTaskGenericNotifyStateClear          MPU_xTaskGenericNotifyStateClear
+        #define ulTaskGenericNotifyValueClear         MPU_ulTaskGenericNotifyValueClear
+        #define vTaskSetTimeOutState                  MPU_vTaskSetTimeOutState
+        #define xTaskCheckForTimeOut                  MPU_xTaskCheckForTimeOut
+        #define xTaskGetCurrentTaskHandle             MPU_xTaskGetCurrentTaskHandle
+        #define xTaskGetSchedulerState                MPU_xTaskGetSchedulerState
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define ulTaskGetRunTimeCounter           MPU_ulTaskGetRunTimeCounter
+            #define ulTaskGetRunTimePercent           MPU_ulTaskGetRunTimePercent
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/* Privileged only wrappers for Task APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+        #define xTaskCreate                              MPU_xTaskCreate
+        #define xTaskCreateStatic                        MPU_xTaskCreateStatic
+        #define vTaskDelete                              MPU_vTaskDelete
+        #define vTaskPrioritySet                         MPU_vTaskPrioritySet
+        #define xTaskGetHandle                           MPU_xTaskGetHandle
+        #define xTaskCallApplicationTaskHook             MPU_xTaskCallApplicationTaskHook
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define pcTaskGetName                        MPU_pcTaskGetName
+            #define xTaskCreateRestricted                MPU_xTaskCreateRestricted
+            #define xTaskCreateRestrictedStatic          MPU_xTaskCreateRestrictedStatic
+            #define vTaskAllocateMPURegions              MPU_vTaskAllocateMPURegions
+            #define xTaskGetStaticBuffers                MPU_xTaskGetStaticBuffers
+            #define uxTaskPriorityGetFromISR             MPU_uxTaskPriorityGetFromISR
+            #define uxTaskBasePriorityGet                MPU_uxTaskBasePriorityGet
+            #define uxTaskBasePriorityGetFromISR         MPU_uxTaskBasePriorityGetFromISR
+            #define xTaskResumeFromISR                   MPU_xTaskResumeFromISR
+            #define xTaskGetApplicationTaskTagFromISR    MPU_xTaskGetApplicationTaskTagFromISR
+            #define xTaskGenericNotifyFromISR            MPU_xTaskGenericNotifyFromISR
+            #define vTaskGenericNotifyGiveFromISR        MPU_vTaskGenericNotifyGiveFromISR
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/* Map standard queue.h API functions to the MPU equivalents. */
+        #define xQueueGenericSend            MPU_xQueueGenericSend
+        #define xQueueReceive                MPU_xQueueReceive
+        #define xQueuePeek                   MPU_xQueuePeek
+        #define xQueueSemaphoreTake          MPU_xQueueSemaphoreTake
+        #define uxQueueMessagesWaiting       MPU_uxQueueMessagesWaiting
+        #define uxQueueSpacesAvailable       MPU_uxQueueSpacesAvailable
+        #define xQueueGetMutexHolder         MPU_xQueueGetMutexHolder
+        #define xQueueTakeMutexRecursive     MPU_xQueueTakeMutexRecursive
+        #define xQueueGiveMutexRecursive     MPU_xQueueGiveMutexRecursive
+        #define xQueueAddToSet               MPU_xQueueAddToSet
+        #define xQueueSelectFromSet          MPU_xQueueSelectFromSet
+
+        #if ( configQUEUE_REGISTRY_SIZE > 0 )
+            #define vQueueAddToRegistry      MPU_vQueueAddToRegistry
+            #define vQueueUnregisterQueue    MPU_vQueueUnregisterQueue
+            #define pcQueueGetName           MPU_pcQueueGetName
+        #endif /* #if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+
+/* Privileged only wrappers for Queue APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+        #define vQueueDelete                           MPU_vQueueDelete
+        #define xQueueCreateMutex                      MPU_xQueueCreateMutex
+        #define xQueueCreateMutexStatic                MPU_xQueueCreateMutexStatic
+        #define xQueueCreateCountingSemaphore          MPU_xQueueCreateCountingSemaphore
+        #define xQueueCreateCountingSemaphoreStatic    MPU_xQueueCreateCountingSemaphoreStatic
+        #define xQueueGenericCreate                    MPU_xQueueGenericCreate
+        #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic
+        #define xQueueGenericReset                     MPU_xQueueGenericReset
+        #define xQueueCreateSet                        MPU_xQueueCreateSet
+        #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define xQueueGenericGetStaticBuffers      MPU_xQueueGenericGetStaticBuffers
+            #define xQueueGenericSendFromISR           MPU_xQueueGenericSendFromISR
+            #define xQueueGiveFromISR                  MPU_xQueueGiveFromISR
+            #define xQueuePeekFromISR                  MPU_xQueuePeekFromISR
+            #define xQueueReceiveFromISR               MPU_xQueueReceiveFromISR
+            #define xQueueIsQueueEmptyFromISR          MPU_xQueueIsQueueEmptyFromISR
+            #define xQueueIsQueueFullFromISR           MPU_xQueueIsQueueFullFromISR
+            #define uxQueueMessagesWaitingFromISR      MPU_uxQueueMessagesWaitingFromISR
+            #define xQueueGetMutexHolderFromISR        MPU_xQueueGetMutexHolderFromISR
+            #define xQueueSelectFromSetFromISR         MPU_xQueueSelectFromSetFromISR
+        #endif /* if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/* Map standard timer.h API functions to the MPU equivalents. */
+        #define pvTimerGetTimerID                 MPU_pvTimerGetTimerID
+        #define vTimerSetTimerID                  MPU_vTimerSetTimerID
+        #define xTimerIsTimerActive               MPU_xTimerIsTimerActive
+        #define xTimerGetTimerDaemonTaskHandle    MPU_xTimerGetTimerDaemonTaskHandle
+        #define xTimerGenericCommandFromTask      MPU_xTimerGenericCommandFromTask
+        #define pcTimerGetName                    MPU_pcTimerGetName
+        #define vTimerSetReloadMode               MPU_vTimerSetReloadMode
+        #define uxTimerGetReloadMode              MPU_uxTimerGetReloadMode
+        #define xTimerGetPeriod                   MPU_xTimerGetPeriod
+        #define xTimerGetExpiryTime               MPU_xTimerGetExpiryTime
+
+/* Privileged only wrappers for Timer APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define xTimerGetReloadMode            MPU_xTimerGetReloadMode
+            #define xTimerCreate                   MPU_xTimerCreate
+            #define xTimerCreateStatic             MPU_xTimerCreateStatic
+            #define xTimerGetStaticBuffer          MPU_xTimerGetStaticBuffer
+            #define xTimerGenericCommandFromISR    MPU_xTimerGenericCommandFromISR
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/* Map standard event_group.h API functions to the MPU equivalents. */
+        #define xEventGroupWaitBits          MPU_xEventGroupWaitBits
+        #define xEventGroupClearBits         MPU_xEventGroupClearBits
+        #define xEventGroupSetBits           MPU_xEventGroupSetBits
+        #define xEventGroupSync              MPU_xEventGroupSync
+
+        #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+            #define uxEventGroupGetNumber    MPU_uxEventGroupGetNumber
+            #define vEventGroupSetNumber     MPU_vEventGroupSetNumber
+        #endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+/* Privileged only wrappers for Event Group APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+        #define xEventGroupCreate                  MPU_xEventGroupCreate
+        #define xEventGroupCreateStatic            MPU_xEventGroupCreateStatic
+        #define vEventGroupDelete                  MPU_vEventGroupDelete
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define xEventGroupGetStaticBuffer     MPU_xEventGroupGetStaticBuffer
+            #define xEventGroupClearBitsFromISR    MPU_xEventGroupClearBitsFromISR
+            #define xEventGroupSetBitsFromISR      MPU_xEventGroupSetBitsFromISR
+            #define xEventGroupGetBitsFromISR      MPU_xEventGroupGetBitsFromISR
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/* Map standard message/stream_buffer.h API functions to the MPU
+ * equivalents. */
+        #define xStreamBufferSend                      MPU_xStreamBufferSend
+        #define xStreamBufferReceive                   MPU_xStreamBufferReceive
+        #define xStreamBufferIsFull                    MPU_xStreamBufferIsFull
+        #define xStreamBufferIsEmpty                   MPU_xStreamBufferIsEmpty
+        #define xStreamBufferSpacesAvailable           MPU_xStreamBufferSpacesAvailable
+        #define xStreamBufferBytesAvailable            MPU_xStreamBufferBytesAvailable
+        #define xStreamBufferSetTriggerLevel           MPU_xStreamBufferSetTriggerLevel
+        #define xStreamBufferNextMessageLengthBytes    MPU_xStreamBufferNextMessageLengthBytes
+
+/* Privileged only wrappers for Stream Buffer APIs. These are needed so that
+ * the application can use opaque handles maintained in mpu_wrappers.c
+ * with all the APIs. */
+
+        #define xStreamBufferGenericCreate                  MPU_xStreamBufferGenericCreate
+        #define xStreamBufferGenericCreateStatic            MPU_xStreamBufferGenericCreateStatic
+        #define vStreamBufferDelete                         MPU_vStreamBufferDelete
+        #define xStreamBufferReset                          MPU_xStreamBufferReset
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define xStreamBufferGetStaticBuffers           MPU_xStreamBufferGetStaticBuffers
+            #define xStreamBufferSendFromISR                MPU_xStreamBufferSendFromISR
+            #define xStreamBufferReceiveFromISR             MPU_xStreamBufferReceiveFromISR
+            #define xStreamBufferSendCompletedFromISR       MPU_xStreamBufferSendCompletedFromISR
+            #define xStreamBufferReceiveCompletedFromISR    MPU_xStreamBufferReceiveCompletedFromISR
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+ * macro so applications can place data in privileged access sections
+ * (useful when using statically allocated objects). */
+        #define PRIVILEGED_FUNCTION
+        #define PRIVILEGED_DATA    __attribute__( ( section( "privileged_data" ) ) )
+        #define FREERTOS_SYSTEM_CALL
+
+
+        #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+            #define vGrantAccessToTask( xTask, xTaskToGrantAccess )                        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToGrantAccess ) )
+            #define vRevokeAccessToTask( xTask, xTaskToRevokeAccess )                      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToRevokeAccess ) )
+
+            #define vGrantAccessToSemaphore( xTask, xSemaphoreToGrantAccess )              vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToGrantAccess ) )
+            #define vRevokeAccessToSemaphore( xTask, xSemaphoreToRevokeAccess )            vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToRevokeAccess ) )
+
+            #define vGrantAccessToQueue( xTask, xQueueToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToGrantAccess ) )
+            #define vRevokeAccessToQueue( xTask, xQueueToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToRevokeAccess ) )
+
+            #define vGrantAccessToQueueSet( xTask, xQueueSetToGrantAccess )                vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToGrantAccess ) )
+            #define vRevokeAccessToQueueSet( xTask, xQueueSetToRevokeAccess )              vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToRevokeAccess ) )
+
+            #define vGrantAccessToEventGroup( xTask, xEventGroupToGrantAccess )            vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToGrantAccess ) )
+            #define vRevokeAccessToEventGroup( xTask, xEventGroupToRevokeAccess )          vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToRevokeAccess ) )
+
+            #define vGrantAccessToStreamBuffer( xTask, xStreamBufferToGrantAccess )        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToGrantAccess ) )
+            #define vRevokeAccessToStreamBuffer( xTask, xStreamBufferToRevokeAccess )      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToRevokeAccess ) )
+
+            #define vGrantAccessToMessageBuffer( xTask, xMessageBufferToGrantAccess )      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToGrantAccess ) )
+            #define vRevokeAccessToMessageBuffer( xTask, xMessageBufferToRevokeAccess )    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToRevokeAccess ) )
+
+            #define vGrantAccessToTimer( xTask, xTimerToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToGrantAccess ) )
+            #define vRevokeAccessToTimer( xTask, xTimerToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToRevokeAccess ) )
+
+        #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
+    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+/* Ensure API functions go in the privileged execution section. */
+        #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
+        #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
+        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
+
+    #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+    #define PRIVILEGED_FUNCTION
+    #define PRIVILEGED_DATA
+    #define FREERTOS_SYSTEM_CALL
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/newlib-freertos.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/newlib-freertos.h
new file mode 100644
index 0000000000..0a8f19b35c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/newlib-freertos.h
@@ -0,0 +1,62 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef INC_NEWLIB_FREERTOS_H
+#define INC_NEWLIB_FREERTOS_H
+
+/* Note Newlib support has been included by popular demand, but is not
+ * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+ * responsible for resulting newlib operation.  User must be familiar with
+ * newlib and must provide system-wide implementations of the necessary
+ * stubs. Be warned that (at the time of writing) the current newlib design
+ * implements a system-wide malloc() that must be provided with locks.
+ *
+ * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+ * for additional information. */
+
+#include <reent.h>
+
+#define configUSE_C_RUNTIME_TLS_SUPPORT    1
+
+#ifndef configTLS_BLOCK_TYPE
+    #define configTLS_BLOCK_TYPE           struct _reent
+#endif
+
+#ifndef configINIT_TLS_BLOCK
+    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )    _REENT_INIT_PTR( &( xTLSBlock ) )
+#endif
+
+#ifndef configSET_TLS_BLOCK
+    #define configSET_TLS_BLOCK( xTLSBlock )    ( _impure_ptr = &( xTLSBlock ) )
+#endif
+
+#ifndef configDEINIT_TLS_BLOCK
+    #define configDEINIT_TLS_BLOCK( xTLSBlock )    _reclaim_reent( &( xTLSBlock ) )
+#endif
+
+#endif /* INC_NEWLIB_FREERTOS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/picolibc-freertos.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/picolibc-freertos.h
new file mode 100644
index 0000000000..9b3eecf449
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/picolibc-freertos.h
@@ -0,0 +1,91 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef INC_PICOLIBC_FREERTOS_H
+#define INC_PICOLIBC_FREERTOS_H
+
+/* Use picolibc TLS support to allocate space for __thread variables,
+ * initialize them at thread creation and set the TLS context at
+ * thread switch time.
+ *
+ * See the picolibc TLS docs:
+ * https://github.com/picolibc/picolibc/blob/main/doc/tls.md
+ * for additional information. */
+
+#include <picotls.h>
+
+#define configUSE_C_RUNTIME_TLS_SUPPORT    1
+
+#define configTLS_BLOCK_TYPE               void *
+
+#define picolibcTLS_SIZE                   ( ( portPOINTER_SIZE_TYPE ) _tls_size() )
+#define picolibcSTACK_ALIGNMENT_MASK       ( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK )
+
+#if __PICOLIBC_MAJOR__ > 1 || __PICOLIBC_MINOR__ >= 8
+
+/* Picolibc 1.8 and newer have explicit alignment values provided
+ * by the _tls_align() inline */
+    #define picolibcTLS_ALIGNMENT_MASK    ( ( portPOINTER_SIZE_TYPE ) ( _tls_align() - 1 ) )
+#else
+
+/* For older Picolibc versions, use the general port alignment value */
+    #define picolibcTLS_ALIGNMENT_MASK    ( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK )
+#endif
+
+/* Allocate thread local storage block off the end of the
+ * stack. The picolibcTLS_SIZE macro returns the size (in
+ * bytes) of the total TLS area used by the application.
+ * Calculate the top of stack address. */
+#if ( portSTACK_GROWTH < 0 )
+
+    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                  \
+    do {                                                                                     \
+        xTLSBlock = ( void * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) -              \
+                                   picolibcTLS_SIZE ) &                                      \
+                                 ~picolibcTLS_ALIGNMENT_MASK );                              \
+        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) - 1 ) & \
+                                           ~picolibcSTACK_ALIGNMENT_MASK );                  \
+        _init_tls( xTLSBlock );                                                              \
+    } while( 0 )
+#else /* portSTACK_GROWTH */
+    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                          \
+    do {                                                                                             \
+        xTLSBlock = ( void * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack +                          \
+                                   picolibcTLS_ALIGNMENT_MASK ) & ~picolibcTLS_ALIGNMENT_MASK );     \
+        pxTopOfStack = ( StackType_t * ) ( ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) +             \
+                                               picolibcTLS_SIZE ) + picolibcSTACK_ALIGNMENT_MASK ) & \
+                                           ~picolibcSTACK_ALIGNMENT_MASK );                          \
+        _init_tls( xTLSBlock );                                                                      \
+    } while( 0 )
+#endif /* portSTACK_GROWTH */
+
+#define configSET_TLS_BLOCK( xTLSBlock )    _set_tls( xTLSBlock )
+
+#define configDEINIT_TLS_BLOCK( xTLSBlock )
+
+#endif /* INC_PICOLIBC_FREERTOS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/portable.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/portable.h
new file mode 100644
index 0000000000..c3b91127a3
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/portable.h
@@ -0,0 +1,271 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Portable layer API.  Each function must be defined for each port.
+*----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+ * pre-processor definition was used to ensure the pre-processor found the correct
+ * portmacro.h file for the port being used.  That scheme was deprecated in favour
+ * of setting the compiler's include path such that it found the correct
+ * portmacro.h file - removing the need for the constant and allowing the
+ * portmacro.h file to be located anywhere in relation to the port being used.
+ * Purely for reasons of backward compatibility the old method is still valid, but
+ * to make it clear that new projects should not use it, support for the port
+ * specific constants has been moved into the deprecated_definitions.h header
+ * file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+ * did not result in a portmacro.h header file being included - and it should be
+ * included here.  In this case the path to the correct portmacro.h header file
+ * must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+    #include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+    #define portBYTE_ALIGNMENT_MASK    ( 0x001f )
+#elif portBYTE_ALIGNMENT == 16
+    #define portBYTE_ALIGNMENT_MASK    ( 0x000f )
+#elif portBYTE_ALIGNMENT == 8
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0007 )
+#elif portBYTE_ALIGNMENT == 4
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0003 )
+#elif portBYTE_ALIGNMENT == 2
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0001 )
+#elif portBYTE_ALIGNMENT == 1
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0000 )
+#else /* if portBYTE_ALIGNMENT == 32 */
+    #error "Invalid portBYTE_ALIGNMENT definition"
+#endif /* if portBYTE_ALIGNMENT == 32 */
+
+#ifndef portUSING_MPU_WRAPPERS
+    #define portUSING_MPU_WRAPPERS    0
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+    #define portNUM_CONFIGURABLE_REGIONS    1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+    #define portHAS_STACK_OVERFLOW_CHECKING    0
+#endif
+
+#ifndef portARCH_NAME
+    #define portARCH_NAME    NULL
+#endif
+
+#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP
+    /* Defaults to 0 for backward compatibility. */
+    #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             StackType_t * pxEndOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters,
+                                             BaseType_t xRunPrivileged,
+                                             xMPU_SETTINGS * xMPUSettings ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters,
+                                             BaseType_t xRunPrivileged,
+                                             xMPU_SETTINGS * xMPUSettings ) PRIVILEGED_FUNCTION;
+    #endif /* if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) */
+#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             StackType_t * pxEndOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters ) PRIVILEGED_FUNCTION;
+    #endif
+#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+
+/* Used by heap_5.c to define the start address and size of each memory region
+ * that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+    uint8_t * pucStartAddress;
+    size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+    size_t xAvailableHeapSpaceInBytes;      /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+    size_t xSizeOfLargestFreeBlockInBytes;  /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xNumberOfFreeBlocks;             /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xMinimumEverFreeBytesRemaining;  /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+    size_t xNumberOfSuccessfulAllocations;  /* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+    size_t xNumberOfSuccessfulFrees;        /* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t * pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void * pvPortCalloc( size_t xNum,
+                     size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 )
+    void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION;
+    void vPortFreeStack( void * pv ) PRIVILEGED_FUNCTION;
+#else
+    #define pvPortMallocStack    pvPortMalloc
+    #define vPortFreeStack       vPortFree
+#endif
+
+#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationMallocFailedHook( void )
+ * @endcode
+ *
+ * This hook function is called when allocation failed.
+ */
+    void vApplicationMallocFailedHook( void );
+#endif
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    struct xMEMORY_REGION;
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * @brief Checks if the calling task is authorized to access the given buffer.
+ *
+ * @param pvBuffer The buffer which the calling task wants to access.
+ * @param ulBufferLength The length of the pvBuffer.
+ * @param ulAccessRequested The permissions that the calling task wants.
+ *
+ * @return pdTRUE if the calling task is authorized to access the buffer,
+ *         pdFALSE otherwise.
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                                uint32_t ulBufferLength,
+                                                uint32_t ulAccessRequested ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * @brief Checks if the calling task is authorized to access the given kernel object.
+ *
+ * @param lInternalIndexOfKernelObject The index of the kernel object in the kernel
+ *                                     object handle pool.
+ *
+ * @return pdTRUE if the calling task is authorized to access the kernel object,
+ *         pdFALSE otherwise.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTABLE_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/projdefs.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/projdefs.h
new file mode 100644
index 0000000000..4d02a5fc12
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/projdefs.h
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (* TaskFunction_t)( void * arg );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+ * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+ * definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInMs ) * ( uint64_t ) configTICK_RATE_HZ ) / ( uint64_t ) 1000U ) )
+#endif
+
+/* Converts a time in ticks to a time in milliseconds.  This macro can be
+ * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+ * definition here is not suitable for your application. */
+#ifndef pdTICKS_TO_MS
+    #define pdTICKS_TO_MS( xTimeInTicks )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInTicks ) * ( uint64_t ) 1000U ) / ( uint64_t ) configTICK_RATE_HZ ) )
+#endif
+
+#define pdFALSE                                  ( ( BaseType_t ) 0 )
+#define pdTRUE                                   ( ( BaseType_t ) 1 )
+#define pdFALSE_SIGNED                           ( ( BaseType_t ) 0 )
+#define pdTRUE_SIGNED                            ( ( BaseType_t ) 1 )
+#define pdFALSE_UNSIGNED                         ( ( UBaseType_t ) 0 )
+#define pdTRUE_UNSIGNED                          ( ( UBaseType_t ) 1 )
+
+#define pdPASS                                   ( pdTRUE )
+#define pdFAIL                                   ( pdFALSE )
+#define errQUEUE_EMPTY                           ( ( BaseType_t ) 0 )
+#define errQUEUE_FULL                            ( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY    ( -1 )
+#define errQUEUE_BLOCKED                         ( -4 )
+#define errQUEUE_YIELD                           ( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+    #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES    0
+#endif
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    #define pdINTEGRITY_CHECK_VALUE    0x5a5a
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5aUL
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5a5a5a5a5aULL
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+ * itself. */
+#define pdFREERTOS_ERRNO_NONE             0   /* No errors */
+#define pdFREERTOS_ERRNO_ENOENT           2   /* No such file or directory */
+#define pdFREERTOS_ERRNO_EINTR            4   /* Interrupted system call */
+#define pdFREERTOS_ERRNO_EIO              5   /* I/O error */
+#define pdFREERTOS_ERRNO_ENXIO            6   /* No such device or address */
+#define pdFREERTOS_ERRNO_EBADF            9   /* Bad file number */
+#define pdFREERTOS_ERRNO_EAGAIN           11  /* No more processes */
+#define pdFREERTOS_ERRNO_EWOULDBLOCK      11  /* Operation would block */
+#define pdFREERTOS_ERRNO_ENOMEM           12  /* Not enough memory */
+#define pdFREERTOS_ERRNO_EACCES           13  /* Permission denied */
+#define pdFREERTOS_ERRNO_EFAULT           14  /* Bad address */
+#define pdFREERTOS_ERRNO_EBUSY            16  /* Mount device busy */
+#define pdFREERTOS_ERRNO_EEXIST           17  /* File exists */
+#define pdFREERTOS_ERRNO_EXDEV            18  /* Cross-device link */
+#define pdFREERTOS_ERRNO_ENODEV           19  /* No such device */
+#define pdFREERTOS_ERRNO_ENOTDIR          20  /* Not a directory */
+#define pdFREERTOS_ERRNO_EISDIR           21  /* Is a directory */
+#define pdFREERTOS_ERRNO_EINVAL           22  /* Invalid argument */
+#define pdFREERTOS_ERRNO_ENOSPC           28  /* No space left on device */
+#define pdFREERTOS_ERRNO_ESPIPE           29  /* Illegal seek */
+#define pdFREERTOS_ERRNO_EROFS            30  /* Read only file system */
+#define pdFREERTOS_ERRNO_EUNATCH          42  /* Protocol driver not attached */
+#define pdFREERTOS_ERRNO_EBADE            50  /* Invalid exchange */
+#define pdFREERTOS_ERRNO_EFTYPE           79  /* Inappropriate file type or format */
+#define pdFREERTOS_ERRNO_ENMFILE          89  /* No more files */
+#define pdFREERTOS_ERRNO_ENOTEMPTY        90  /* Directory not empty */
+#define pdFREERTOS_ERRNO_ENAMETOOLONG     91  /* File or path name too long */
+#define pdFREERTOS_ERRNO_EOPNOTSUPP       95  /* Operation not supported on transport endpoint */
+#define pdFREERTOS_ERRNO_EAFNOSUPPORT     97  /* Address family not supported by protocol */
+#define pdFREERTOS_ERRNO_ENOBUFS          105 /* No buffer space available */
+#define pdFREERTOS_ERRNO_ENOPROTOOPT      109 /* Protocol not available */
+#define pdFREERTOS_ERRNO_EADDRINUSE       112 /* Address already in use */
+#define pdFREERTOS_ERRNO_ETIMEDOUT        116 /* Connection timed out */
+#define pdFREERTOS_ERRNO_EINPROGRESS      119 /* Connection already in progress */
+#define pdFREERTOS_ERRNO_EALREADY         120 /* Socket already connected */
+#define pdFREERTOS_ERRNO_EADDRNOTAVAIL    125 /* Address not available */
+#define pdFREERTOS_ERRNO_EISCONN          127 /* Socket is already connected */
+#define pdFREERTOS_ERRNO_ENOTCONN         128 /* Socket is not connected */
+#define pdFREERTOS_ERRNO_ENOMEDIUM        135 /* No medium inserted */
+#define pdFREERTOS_ERRNO_EILSEQ           138 /* An invalid UTF-16 sequence was encountered. */
+#define pdFREERTOS_ERRNO_ECANCELED        140 /* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+ * itself. */
+#define pdFREERTOS_LITTLE_ENDIAN          0
+#define pdFREERTOS_BIG_ENDIAN             1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN                   pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN                      pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/queue.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/queue.h
new file mode 100644
index 0000000000..23914d58b2
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/queue.h
@@ -0,0 +1,1810 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition   * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition   * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition   * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define queueSEND_TO_BACK                     ( ( BaseType_t ) 0 )
+#define queueSEND_TO_FRONT                    ( ( BaseType_t ) 1 )
+#define queueOVERWRITE                        ( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE                  ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX                 ( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE    ( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE      ( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX       ( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * @code{c}
+ * QueueHandle_t xQueueCreate(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize
+ *                        );
+ * @endcode
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *  if( xQueue1 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue2 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define xQueueCreate( uxQueueLength, uxItemSize )    xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * @code{c}
+ * QueueHandle_t xQueueCreateStatic(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize,
+ *                            uint8_t *pucQueueStorage,
+ *                            StaticQueue_t *pxQueueBuffer
+ *                        );
+ * @endcode
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorage If uxItemSize is not zero then
+ * pucQueueStorage must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorage can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+ *
+ * // xQueueBuffer will hold the queue structure.
+ * StaticQueue_t xQueueBuffer;
+ *
+ * // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ * // [(queue length) * ( queue item size)] bytes long.
+ * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+ *
+ * void vATask( void *pvParameters )
+ * {
+ *  QueueHandle_t xQueue1;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+ *                          ITEM_SIZE     // The size of each item in the queue
+ *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+ *                          &xQueueBuffer ); // The buffer that will hold the queue structure.
+ *
+ *  // The queue is guaranteed to be created successfully as no dynamic memory
+ *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer )    xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueGetStaticBuffers( QueueHandle_t xQueue,
+ *                                    uint8_t ** ppucQueueStorage,
+ *                                    StaticQueue_t ** ppxStaticQueue );
+ * @endcode
+ *
+ * Retrieve pointers to a statically created queue's data structure buffer
+ * and storage area buffer. These are the same buffers that are supplied
+ * at the time of creation.
+ *
+ * @param xQueue The queue for which to retrieve the buffers.
+ *
+ * @param ppucQueueStorage Used to return a pointer to the queue's storage
+ * area buffer.
+ *
+ * @param ppxStaticQueue Used to return a pointer to the queue's data
+ * structure buffer.
+ *
+ * @return pdTRUE if buffers were retrieved, pdFALSE otherwise.
+ *
+ * \defgroup xQueueGetStaticBuffers xQueueGetStaticBuffers
+ * \ingroup QueueManagement
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xQueueGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue )    xQueueGenericGetStaticBuffers( ( xQueue ), ( ppucQueueStorage ), ( ppxStaticQueue ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueSendToFront(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ * @endcode
+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueSendToBack(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ * @endcode
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueSend(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            TickType_t xTicksToWait
+ *                       );
+ * @endcode
+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueOverwrite(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue
+ *                       );
+ * @endcode
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+ * @code{c}
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwrite() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ *
+ *  // Write the value 10 to the queue using xQueueOverwrite().
+ *  ulVarToSend = 10;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // Peeking the queue should now return 10, but leave the value 10 in
+ *  // the queue.  A block time of zero is used as it is known that the
+ *  // queue holds a value.
+ *  ulValReceived = 0;
+ *  xQueuePeek( xQueue, &ulValReceived, 0 );
+ *
+ *  if( ulValReceived != 10 )
+ *  {
+ *      // Error unless the item was removed by a different task.
+ *  }
+ *
+ *  // The queue is still full.  Use xQueueOverwrite() to overwrite the
+ *  // value held in the queue with 100.
+ *  ulVarToSend = 100;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // This time read from the queue, leaving the queue empty once more.
+ *  // A block time of 0 is used again.
+ *  xQueueReceive( xQueue, &ulValReceived, 0 );
+ *
+ *  // The value read should be the last value written, even though the
+ *  // queue was already full when the value was written.
+ *  if( ulValReceived != 100 )
+ *  {
+ *      // Error!
+ *  }
+ *
+ *  // ...
+ * }
+ * @endcode
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueGenericSend(
+ *                                  QueueHandle_t xQueue,
+ *                                  const void * pvItemToQueue,
+ *                                  TickType_t xTicksToWait
+ *                                  BaseType_t xCopyPosition
+ *                              );
+ * @endcode
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
+                              const void * const pvItemToQueue,
+                              TickType_t xTicksToWait,
+                              const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueuePeek(
+ *                           QueueHandle_t xQueue,
+ *                           void * const pvBuffer,
+ *                           TickType_t xTicksToWait
+ *                       );
+ * @endcode
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to peek the data from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Peek a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask, but the item still remains on the queue.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue,
+                       void * const pvBuffer,
+                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueuePeekFromISR(
+ *                                  QueueHandle_t xQueue,
+ *                                  void *pvBuffer,
+ *                              );
+ * @endcode
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
+                              void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueReceive(
+ *                               QueueHandle_t xQueue,
+ *                               void *pvBuffer,
+ *                               TickType_t xTicksToWait
+ *                          );
+ * @endcode
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ * @code{c}
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to receive from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Receive a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * @endcode
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue,
+                          void * const pvBuffer,
+                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+ * @endcode
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+ * @endcode
+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * void vQueueDelete( QueueHandle_t xQueue );
+ * @endcode
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueSendToFrontFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ * @endcode
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFrontFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * @code{c}
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ * @endcode
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueSendToBackFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ * @endcode
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * @code{c}
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ * @endcode
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueOverwriteFromISR(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            BaseType_t *pxHigherPriorityTaskWoken
+ *                       );
+ * @endcode
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+ * @code{c}
+ *
+ * QueueHandle_t xQueue;
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwriteFromISR() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ * }
+ *
+ * void vAnInterruptHandler( void )
+ * {
+ * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Write the value 10 to the queue using xQueueOverwriteFromISR().
+ *  ulVarToSend = 10;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // The queue is full, but calling xQueueOverwriteFromISR() again will still
+ *  // pass because the value held in the queue will be overwritten with the
+ *  // new value.
+ *  ulVarToSend = 100;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // Reading from the queue will now return 100.
+ *
+ *  // ...
+ *
+ *  if( xHigherPrioritytaskWoken == pdTRUE )
+ *  {
+ *      // Writing to the queue caused a task to unblock and the unblocked task
+ *      // has a priority higher than or equal to the priority of the currently
+ *      // executing task (the task this interrupt interrupted). Perform a context
+ *      // switch so this interrupt returns directly to the unblocked task.
+ *      // The macro used is port specific and will be either
+ *      // portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to the documentation
+ *      // page for the port being used.
+ *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *  }
+ * }
+ * @endcode
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueSendFromISR(
+ *                                   QueueHandle_t xQueue,
+ *                                   const void *pvItemToQueue,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken
+ *                              );
+ * @endcode
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * @code{c}
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *       // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *       // switch should be requested. The macro used is port specific and
+ *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *       // refer to the documentation page for the port being used.
+ *       portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *  }
+ * }
+ * @endcode
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueGenericSendFromISR(
+ *                                         QueueHandle_t    xQueue,
+ *                                         const    void    *pvItemToQueue,
+ *                                         BaseType_t  *pxHigherPriorityTaskWoken,
+ *                                         BaseType_t  xCopyPosition
+ *                                     );
+ * @endcode
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * @code{c}
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWokenByPost;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWokenByPost = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post each byte.
+ *      xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWokenByPost )
+ *  {
+ *       // As xHigherPriorityTaskWokenByPost is now set to pdTRUE then a context
+ *       // switch should be requested. The macro used is port specific and
+ *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *       // refer to the documentation page for the port being used.
+ *       portYIELD_FROM_ISR( xHigherPriorityTaskWokenByPost );
+ *  }
+ * }
+ * @endcode
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
+                                     const void * const pvItemToQueue,
+                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                     const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
+                              BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * @code{c}
+ * BaseType_t xQueueReceiveFromISR(
+ *                                     QueueHandle_t    xQueue,
+ *                                     void             *pvBuffer,
+ *                                     BaseType_t       *pxTaskWoken
+ *                                 );
+ * @endcode
+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxHigherPriorityTaskWoken A task may be blocked waiting for space to
+ * become available on the queue.  If xQueueReceiveFromISR causes such a task
+ * to unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ * @code{c}
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Function to create a queue and post some values.
+ * void vAFunction( void *pvParameters )
+ * {
+ * char cValueToPost;
+ * const TickType_t xTicksToWait = ( TickType_t )0xff;
+ *
+ *  // Create a queue capable of containing 10 characters.
+ *  xQueue = xQueueCreate( 10, sizeof( char ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Post some characters that will be used within an ISR.  If the queue
+ *  // is full then this task will block for xTicksToWait ticks.
+ *  cValueToPost = 'a';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *  cValueToPost = 'b';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *
+ *  // ... keep posting characters ... this task may block when the queue
+ *  // becomes full.
+ *
+ *  cValueToPost = 'c';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ * }
+ *
+ * // ISR that outputs all the characters received on the queue.
+ * void vISR_Routine( void )
+ * {
+ * BaseType_t xTaskWokenByReceive = pdFALSE;
+ * char cRxedChar;
+ *
+ *  while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+ *  {
+ *      // A character was received.  Output the character now.
+ *      vOutputCharacter( cRxedChar );
+ *
+ *      // If removing the character from the queue woke the task that was
+ *      // posting onto the queue xTaskWokenByReceive will have been set to
+ *      // pdTRUE.  No matter how many times this loop iterates only one
+ *      // task will be woken.
+ *  }
+ *
+ *  if( xTaskWokenByReceive != ( char ) pdFALSE;
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ * @endcode
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
+                                 void * const pvBuffer,
+                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from within an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
+                                    const void * pvItemToQueue,
+                                    BaseType_t xCoRoutinePreviouslyWoken );
+    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
+                                       void * pvBuffer,
+                                       BaseType_t * pxTaskWoken );
+    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
+                             const void * pvItemToQueue,
+                             TickType_t xTicksToWait );
+    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
+                                void * pvBuffer,
+                                TickType_t xTicksToWait );
+
+#endif /* if ( configUSE_CO_ROUTINES == 1 ) */
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_COUNTING_SEMAPHORES == 1 )
+    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                     TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue )    xQueueGenericReset( ( xQueue ), pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not affect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * If vQueueAddToRegistry is called more than once with the same xQueue
+ * parameter, the registry will store the pcQueueName parameter from the
+ * most recent call to vQueueAddToRegistry.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcQueueName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+    void vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcQueueName ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+    void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to create a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                       const UBaseType_t uxItemSize,
+                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to create a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                             const UBaseType_t uxItemSize,
+                                             uint8_t * pucQueueStorage,
+                                             StaticQueue_t * pxStaticQueue,
+                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to retrieve the buffers of statically
+ * created queues. This is called by other functions and macros that retrieve
+ * the buffers of other statically created RTOS objects that use the queue
+ * structure as their base.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    BaseType_t xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
+                                              uint8_t ** ppucQueueStorage,
+                                              StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+#if ( configUSE_QUEUE_SETS == 1 )
+    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+#if ( configUSE_QUEUE_SETS == 1 )
+    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
+                                     TickType_t xTicksToWait,
+                                     const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
+                               BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* QUEUE_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/semphr.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/semphr.h
new file mode 100644
index 0000000000..c4b927e303
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/semphr.h
@@ -0,0 +1,1215 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH    ( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH      ( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME                  ( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * @code{c}
+ * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore );
+ * @endcode
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+ *  // This is a macro so pass the variable in directly.
+ *  vSemaphoreCreateBinary( xSemaphore );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define vSemaphoreCreateBinary( xSemaphore )                                                                                     \
+    do {                                                                                                                             \
+        ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \
+        if( ( xSemaphore ) != NULL )                                                                                                 \
+        {                                                                                                                            \
+            ( void ) xSemaphoreGive( ( xSemaphore ) );                                                                               \
+        }                                                                                                                            \
+    } while( 0 )
+#endif
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateBinary( void );
+ * @endcode
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateBinary()    xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer );
+ * @endcode
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore = NULL;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // The semaphore's data structures will be placed in the xSemaphoreBuffer
+ *  // variable, the address of which is passed into the function.  The
+ *  // function's parameter is not NULL, so the function will not attempt any
+ *  // dynamic memory allocation, and therefore the function will not return
+ *  // return NULL.
+ *  xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+ *
+ *  // Rest of task code goes here.
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore )    xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, ( pxStaticSemaphore ), queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * @code{c}
+ * xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               );
+ * @endcode
+ *
+ * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // A task that creates a semaphore.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ * }
+ *
+ * // A task that uses the semaphore.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // See if we can obtain the semaphore.  If the semaphore is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the semaphore and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource.  Release the
+ *          // semaphore.
+ *          xSemaphoreGive( xSemaphore );
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the semaphore and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )    xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * @code{c}
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        );
+ * @endcode
+ *
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, but instead buried in a more complex
+ *          // call structure.  This is just for illustrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #define xSemaphoreTakeRecursive( xMutex, xBlockTime )    xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * @code{c}
+ * xSemaphoreGive( SemaphoreHandle_t xSemaphore );
+ * @endcode
+ *
+ * <i>Macro</i> to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = vSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *      {
+ *          // We would expect this call to fail because we cannot give
+ *          // a semaphore without first "taking" it!
+ *      }
+ *
+ *      // Obtain the semaphore - don't block if the semaphore is not
+ *      // immediately available.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+ *      {
+ *          // We now have the semaphore and can access the shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource so can free the
+ *          // semaphore.
+ *          if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *          {
+ *              // We would not expect this call to fail because we must have
+ *              // obtained the semaphore to get here.
+ *          }
+ *      }
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )    xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * @code{c}
+ * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex );
+ * @endcode
+ *
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, it would be more likely that the calls
+ *          // to xSemaphoreGiveRecursive() would be called as a call stack
+ *          // unwound.  This is just for demonstrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #define xSemaphoreGiveRecursive( xMutex )    xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * @code{c}
+ * xSemaphoreGiveFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ * @endcode
+ *
+ * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * @code{c}
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT 10
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // Repetitive task.
+ * void vATask( void * pvParameters )
+ * {
+ *  for( ;; )
+ *  {
+ *      // We want this task to run every 10 ticks of a timer.  The semaphore
+ *      // was created before this task was started.
+ *
+ *      // Block waiting for the semaphore to become available.
+ *      if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+ *      {
+ *          // It is time to execute.
+ *
+ *          // ...
+ *
+ *          // We have finished our task.  Return to the top of the loop where
+ *          // we will block on the semaphore until it is time to execute
+ *          // again.  Note when using the semaphore for synchronisation with an
+ *          // ISR in this manner there is no need to 'give' the semaphore back.
+ *      }
+ *  }
+ * }
+ *
+ * // Timer ISR
+ * void vTimerISR( void * pvParameters )
+ * {
+ * static uint8_t ucLocalTickCount = 0;
+ * static BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // A timer tick has occurred.
+ *
+ *  // ... Do other time functions.
+ *
+ *  // Is it time for vATask () to run?
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *  ucLocalTickCount++;
+ *  if( ucLocalTickCount >= TICKS_TO_WAIT )
+ *  {
+ *      // Unblock the task by releasing the semaphore.
+ *      xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+ *
+ *      // Reset the count so we release the semaphore again in 10 ticks time.
+ *      ucLocalTickCount = 0;
+ *  }
+ *
+ *  if( xHigherPriorityTaskWoken != pdFALSE )
+ *  {
+ *      // We can force a context switch here.  Context switching from an
+ *      // ISR uses port specific syntax.  Check the demo task for your port
+ *      // to find the syntax required.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * @code{c}
+ * xSemaphoreTakeFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ * @endcode
+ *
+ * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateMutex( void );
+ * @endcode
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )
+    #define xSemaphoreCreateMutex()    xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ * @endcode
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A mutex cannot be used before it has been created.  xMutexBuffer is
+ *  // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )
+    #define xSemaphoreCreateMutexStatic( pxMutexBuffer )    xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif
+
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void );
+ * @endcode
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexes use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+    #define xSemaphoreCreateRecursiveMutex()    xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ * @endcode
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexes use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A recursive semaphore cannot be used before it is created.  Here a
+ *  // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+ *  // The address of xMutexBuffer is passed into the function, and will hold
+ *  // the mutexes data structures - so no dynamic memory allocation will be
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+    #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore )    xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, ( pxStaticSemaphore ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount );
+ * @endcode
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+ *  // The max value to which the semaphore can count should be 10, and the
+ *  // initial value assigned to the count should be 0.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount )    xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * @code{c}
+ * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer );
+ * @endcode
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ * @code{c}
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Counting semaphore cannot be used before they have been created.  Create
+ *  // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+ *  // value to which the semaphore can count is 10, and the initial value
+ *  // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+ *  // passed in and will be used to hold the semaphore structure, so no dynamic
+ *  // memory allocation will be used.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+ *
+ *  // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+ *  // is no need to check its value.
+ * }
+ * @endcode
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer )    xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * @code{c}
+ * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
+ * @endcode
+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore )    vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * @code{c}
+ * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
+ * @endcode
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #define xSemaphoreGetMutexHolder( xSemaphore )    xQueueGetMutexHolder( ( xSemaphore ) )
+#endif
+
+/**
+ * semphr.h
+ * @code{c}
+ * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
+ * @endcode
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #define xSemaphoreGetMutexHolderFromISR( xSemaphore )    xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+#endif
+
+/**
+ * semphr.h
+ * @code{c}
+ * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
+ * @endcode
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore )           uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * @code{c}
+ * UBaseType_t uxSemaphoreGetCountFromISR( SemaphoreHandle_t xSemaphore );
+ * @endcode
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCountFromISR() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCountFromISR() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCountFromISR( xSemaphore )    uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * @code{c}
+ * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore,
+ *                                       StaticSemaphore_t ** ppxSemaphoreBuffer );
+ * @endcode
+ *
+ * Retrieve pointer to a statically created binary semaphore, counting semaphore,
+ * or mutex semaphore's data structure buffer. This is the same buffer that is
+ * supplied at the time of creation.
+ *
+ * @param xSemaphore The semaphore for which to retrieve the buffer.
+ *
+ * @param ppxSemaphoreBuffer Used to return a pointer to the semaphore's
+ * data structure buffer.
+ *
+ * @return pdTRUE if buffer was retrieved, pdFALSE otherwise.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xSemaphoreGetStaticBuffer( xSemaphore, ppxSemaphoreBuffer )    xQueueGenericGetStaticBuffers( ( QueueHandle_t ) ( xSemaphore ), NULL, ( ppxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+#endif /* SEMAPHORE_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stack_macros.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stack_macros.h
new file mode 100644
index 0000000000..438d9f14e5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stack_macros.h
@@ -0,0 +1,141 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * portSTACK_LIMIT_PADDING is a number of extra words to consider to be in
+ * use on the stack.
+ */
+#ifndef portSTACK_LIMIT_PADDING
+    #define portSTACK_LIMIT_PADDING    0
+#endif
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+/* Only the current stack state is to be checked. */
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+    do {                                                                                        \
+        /* Is the currently saved stack pointer within the stack limit? */                      \
+        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )     \
+        {                                                                                       \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+        }                                                                                       \
+    } while( 0 )
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+/* Only the current stack state is to be checked. */
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    do {                                                                                         \
+                                                                                                 \
+        /* Is the currently saved stack pointer within the stack limit? */                       \
+        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
+        {                                                                                        \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
+        }                                                                                        \
+    } while( 0 )
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+    do {                                                                                        \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                 \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                 \
+                                                                                                \
+        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                 \
+        {                                                                                       \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+        }                                                                                       \
+    } while( 0 )
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
+    do {                                                                                                                                  \
+        int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
+        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+                                                                                                                                          \
+                                                                                                                                          \
+        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
+                                                                                                                                          \
+        /* Has the extremity of the task stack ever been written over? */                                                                 \
+        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
+        {                                                                                                                                 \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                                                         \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );                                           \
+        }                                                                                                                                 \
+    } while( 0 )
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+    #define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stdint.readme b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stdint.readme
new file mode 100644
index 0000000000..db3229a2c1
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stdint.readme
@@ -0,0 +1,58 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_STDINT
+#define FREERTOS_STDINT
+
+/*******************************************************************************
+ * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions
+ * necessary to build the FreeRTOS code.  It is provided to allow FreeRTOS to be
+ * built using compilers that do not provide their own stdint.h definition.
+ *
+ * To use this file:
+ *
+ *    1) Copy this file into the directory that contains your FreeRTOSConfig.h
+ *       header file, as that directory will already be in the compiler's include
+ *       path.
+ *
+ *    2) Rename the copied file stdint.h.
+ *
+ */
+
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+typedef short int16_t;
+typedef unsigned short uint16_t;
+typedef long int32_t;
+typedef unsigned long uint32_t;
+
+#ifndef SIZE_MAX
+    #define SIZE_MAX    ( ( size_t ) -1 )
+#endif
+
+#endif /* FREERTOS_STDINT */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stream_buffer.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stream_buffer.h
new file mode 100644
index 0000000000..686bc1bbfa
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/stream_buffer.h
@@ -0,0 +1,946 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+/**
+ *  Type used as a stream buffer's optional callback.
+ */
+typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuffer,
+                                                 BaseType_t xIsInsideISR,
+                                                 BaseType_t * const pxHigherPriorityTaskWoken );
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ * @endcode
+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
+ * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
+ * stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the stream buffer structure and the data in the stream buffer is
+ *  // allocated dynamically.
+ *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ *  if( xStreamBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // stream buffer.
+ *  }
+ *  else
+ *  {
+ *      // The stream buffer was created successfully and can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                              size_t xTriggerLevelBytes,
+ *                                              uint8_t *pucStreamBufferStorageArea,
+ *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
+ * @endcode
+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
+ * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
+ * stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * // Used to dimension the array used to hold the streams.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),
+ *                                             xTriggerLevel,
+ *                                             ucStorageBuffer,
+ *                                             &xStreamBufferStruct );
+ *
+ *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+ *  // reference the created stream buffer in other stream buffer API calls.
+ *
+ *  // Other code that uses the stream buffer can go here.
+ * }
+ *
+ * @endcode
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
+ *                                           uint8_t ** ppucStreamBufferStorageArea,
+ *                                           StaticStreamBuffer_t ** ppxStaticStreamBuffer );
+ * @endcode
+ *
+ * Retrieve pointers to a statically created stream buffer's data structure
+ * buffer and storage area buffer. These are the same buffers that are supplied
+ * at the time of creation.
+ *
+ * @param xStreamBuffer The stream buffer for which to retrieve the buffers.
+ *
+ * @param ppucStreamBufferStorageArea Used to return a pointer to the stream
+ * buffer's storage area buffer.
+ *
+ * @param ppxStaticStreamBuffer Used to return a pointer to the stream
+ * buffer's data structure buffer.
+ *
+ * @return pdTRUE if buffers were retrieved, pdFALSE otherwise.
+ *
+ * \defgroup xStreamBufferGetStaticBuffers xStreamBufferGetStaticBuffers
+ * \ingroup StreamBufferManagement
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
+                                              uint8_t ** ppucStreamBufferStorageArea,
+                                              StaticStreamBuffer_t ** ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ *                        const void *pvTxData,
+ *                        size_t xDataLengthBytes,
+ *                        TickType_t xTicksToWait );
+ * @endcode
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+ * @code{c}
+ * void vAFunction( StreamBufferHandle_t xStreamBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the stream buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the stream buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xStreamBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written, but it did
+ *      // successfully write xBytesSent bytes.
+ *  }
+ *
+ *  // Send the string to the stream buffer.  Return immediately if there is not
+ *  // enough space in the buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The entire string could not be added to the stream buffer because
+ *      // there was not enough free space in the buffer, but xBytesSent bytes
+ *      // were sent.  Could try again to send the remaining bytes.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void * pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                               const void *pvTxData,
+ *                               size_t xDataLengthBytes,
+ *                               BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+ * @code{c}
+ * // A stream buffer that has already been created.
+ * StreamBufferHandle_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the stream buffer.
+ *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+ *                                         ( void * ) pcStringToSend,
+ *                                         strlen( pcStringToSend ),
+ *                                         &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // There was not enough free space in the stream buffer for the entire
+ *      // string to be written, ut xBytesSent bytes were written.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void * pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ *                           void *pvRxData,
+ *                           size_t xBufferLengthBytes,
+ *                           TickType_t xTicksToWait );
+ * @endcode
+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+ * @code{c}
+ * void vAFunction( StreamBuffer_t xStreamBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+ *  // Wait in the Blocked state (so not using any CPU processing time) for a
+ *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+ *  // available.
+ *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+ *                                         ( void * ) ucRxData,
+ *                                         sizeof( ucRxData ),
+ *                                         xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains another xReceivedBytes bytes of data, which can
+ *      // be processed here....
+ *  }
+ * }
+ * @endcode
+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void * pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                                  void *pvRxData,
+ *                                  size_t xBufferLengthBytes,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+ * @code{c}
+ * // A stream buffer that has already been created.
+ * StreamBuffer_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next stream from the stream buffer.
+ *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // ucRxData contains xReceivedBytes read from the stream buffer.
+ *      // Process the stream here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void * pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+ * @endcode
+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                         size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                 BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                 size_t xTriggerLevelBytes,
+                                                 BaseType_t xIsMessageBuffer,
+                                                 StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                 StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xIsMessageBuffer,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+#endif
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
+                                             UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* !defined( STREAM_BUFFER_H ) */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/task.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/task.h
new file mode 100644
index 0000000000..3926dfc335
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/task.h
@@ -0,0 +1,3761 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+* MACROS AND DEFINITIONS
+*----------------------------------------------------------*/
+
+/*
+ * If tskKERNEL_VERSION_NUMBER ends with + it represents the version in development
+ * after the numbered release.
+ *
+ * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
+ * values will reflect the last released version number.
+ */
+#define tskKERNEL_VERSION_NUMBER       "V11.0.1"
+#define tskKERNEL_VERSION_MAJOR        11
+#define tskKERNEL_VERSION_MINOR        0
+#define tskKERNEL_VERSION_BUILD        1
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY        ( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE       ( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER    ( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY    ( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY    ( 1UL << 4UL )
+
+/* MPU region permissions stored in MPU settings to
+ * authorize access requests. */
+#define tskMPU_READ_PERMISSION         ( 1UL << 0UL )
+#define tskMPU_WRITE_PERMISSION        ( 1UL << 1UL )
+
+/* The direct to task notification feature used to have only a single notification
+ * per task.  Now there is an array of notifications per task that is dimensioned by
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES.  For backward compatibility, any use of the
+ * original direct to task notification defaults to using the first index in the
+ * array. */
+#define tskDEFAULT_INDEX_TO_NOTIFY     ( 0 )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock         * TaskHandle_t;
+typedef const struct tskTaskControlBlock   * ConstTaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (* TaskHookFunction_t)( void * arg );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+    eRunning = 0, /* A task is querying the state of itself, so must be running. */
+    eReady,       /* The task being queried is in a ready or pending ready list. */
+    eBlocked,     /* The task being queried is in the Blocked state. */
+    eSuspended,   /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+    eDeleted,     /* The task being queried has been deleted, but its TCB has not yet been freed. */
+    eInvalid      /* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+    eNoAction = 0,            /* Notify the task without updating its notify value. */
+    eSetBits,                 /* Set bits in the task's notification value. */
+    eIncrement,               /* Increment the task's notification value. */
+    eSetValueWithOverwrite,   /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+    eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+    BaseType_t xOverflowCount;
+    TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+    void * pvBaseAddress;
+    uint32_t ulLengthInBytes;
+    uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+    TaskFunction_t pvTaskCode;
+    const char * pcName;
+    configSTACK_DEPTH_TYPE usStackDepth;
+    void * pvParameters;
+    UBaseType_t uxPriority;
+    StackType_t * puxStackBuffer;
+    MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+    #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+        StaticTask_t * const pxTaskBuffer;
+    #endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+ * in the system. */
+typedef struct xTASK_STATUS
+{
+    TaskHandle_t xHandle;                         /* The handle of the task to which the rest of the information in the structure relates. */
+    const char * pcTaskName;                      /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */
+    UBaseType_t xTaskNumber;                      /* A number unique to the task. */
+    eTaskState eCurrentState;                     /* The state in which the task existed when the structure was populated. */
+    UBaseType_t uxCurrentPriority;                /* The priority at which the task was running (may be inherited) when the structure was populated. */
+    UBaseType_t uxBasePriority;                   /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+    configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock.  See https://www.FreeRTOS.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+    StackType_t * pxStackBase;                    /* Points to the lowest address of the task's stack area. */
+    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+        StackType_t * pxTopOfStack;               /* Points to the top address of the task's stack area. */
+        StackType_t * pxEndOfStack;               /* Points to the end address of the task's stack area. */
+    #endif
+    configSTACK_DEPTH_TYPE usStackHighWaterMark;  /* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+    #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+        UBaseType_t uxCoreAffinityMask;           /* The core affinity mask for the task */
+    #endif
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+    eAbortSleep = 0,           /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+    eStandardSleep,            /* Enter a sleep mode that will not last any longer than the expected idle time. */
+    #if ( INCLUDE_vTaskSuspend == 1 )
+        eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+    #endif /* INCLUDE_vTaskSuspend */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY    ( ( UBaseType_t ) 0U )
+
+/**
+ * Defines affinity to all available cores.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskNO_AFFINITY      ( ( UBaseType_t ) -1 )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()                          portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()                 portENTER_CRITICAL()
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskENTER_CRITICAL_FROM_ISR()    portSET_INTERRUPT_MASK_FROM_ISR()
+#else
+    #define taskENTER_CRITICAL_FROM_ISR()    portENTER_CRITICAL_FROM_ISR()
+#endif
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()                    portEXIT_CRITICAL()
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskEXIT_CRITICAL_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+#else
+    #define taskEXIT_CRITICAL_FROM_ISR( x )    portEXIT_CRITICAL_FROM_ISR( x )
+#endif
+
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()    portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()     portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+ * 0 to generate more optimal code when configASSERT() is defined as the constant
+ * is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED      ( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED    ( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING        ( ( BaseType_t ) 2 )
+
+/* Checks if core ID is valid. */
+#define taskVALID_CORE_ID( xCoreID )    ( ( ( ( ( BaseType_t ) 0 <= ( xCoreID ) ) && ( ( xCoreID ) < ( BaseType_t ) configNUMBER_OF_CORES ) ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+
+/*-----------------------------------------------------------
+* TASK CREATION API
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskCreate(
+ *                            TaskFunction_t pxTaskCode,
+ *                            const char *pcName,
+ *                            configSTACK_DEPTH_TYPE usStackDepth,
+ *                            void *pvParameters,
+ *                            UBaseType_t uxPriority,
+ *                            TaskHandle_t *pxCreatedTask
+ *                        );
+ * @endcode
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pxTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ * @code{c}
+ * // Task to be created.
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *   }
+ * }
+ *
+ * // Function that creates a task.
+ * void vOtherFunction( void )
+ * {
+ * static uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle = NULL;
+ *
+ *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+ *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+ *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+ *   // the new task attempts to access it.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+ *   configASSERT( xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   if( xHandle != NULL )
+ *   {
+ *      vTaskDelete( xHandle );
+ *   }
+ * }
+ * @endcode
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName,
+                            const configSTACK_DEPTH_TYPE usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
+                                       const char * const pcName,
+                                       const configSTACK_DEPTH_TYPE usStackDepth,
+                                       void * const pvParameters,
+                                       UBaseType_t uxPriority,
+                                       UBaseType_t uxCoreAffinityMask,
+                                       TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+ *                               const char *pcName,
+ *                               uint32_t ulStackDepth,
+ *                               void *pvParameters,
+ *                               UBaseType_t uxPriority,
+ *                               StackType_t *puxStackBuffer,
+ *                               StaticTask_t *pxTaskBuffer );
+ * @endcode
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pxTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param puxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither puxStackBuffer nor pxTaskBuffer are NULL, then the task
+ * will be created and a handle to the created task is returned.  If either
+ * puxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+ * @code{c}
+ *
+ *  // Dimensions of the buffer that the task being created will use as its stack.
+ *  // NOTE:  This is the number of words the stack will hold, not the number of
+ *  // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+ *  // then 400 bytes (100 * 32-bits) will be allocated.
+ #define STACK_SIZE 200
+ *
+ *  // Structure that will hold the TCB of the task being created.
+ *  StaticTask_t xTaskBuffer;
+ *
+ *  // Buffer that the task being created will use as its stack.  Note this is
+ *  // an array of StackType_t variables.  The size of StackType_t is dependent on
+ *  // the RTOS port.
+ *  StackType_t xStack[ STACK_SIZE ];
+ *
+ *  // Function that implements the task being created.
+ *  void vTaskCode( void * pvParameters )
+ *  {
+ *      // The parameter value is expected to be 1 as 1 is passed in the
+ *      // pvParameters value in the call to xTaskCreateStatic().
+ *      configASSERT( ( uint32_t ) pvParameters == 1UL );
+ *
+ *      for( ;; )
+ *      {
+ *          // Task code goes here.
+ *      }
+ *  }
+ *
+ *  // Function that creates a task.
+ *  void vOtherFunction( void )
+ *  {
+ *      TaskHandle_t xHandle = NULL;
+ *
+ *      // Create the task without using any dynamic memory allocation.
+ *      xHandle = xTaskCreateStatic(
+ *                    vTaskCode,       // Function that implements the task.
+ *                    "NAME",          // Text name for the task.
+ *                    STACK_SIZE,      // Stack size in words, not bytes.
+ *                    ( void * ) 1,    // Parameter passed into the task.
+ *                    tskIDLE_PRIORITY,// Priority at which the task is created.
+ *                    xStack,          // Array to use as the task's stack.
+ *                    &xTaskBuffer );  // Variable to hold the task's data structure.
+ *
+ *      // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+ *      // been created, and xHandle will be the task's handle.  Use the handle
+ *      // to suspend the task.
+ *      vTaskSuspend( xHandle );
+ *  }
+ * @endcode
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName,
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
+                                               const char * const pcName,
+                                               const uint32_t ulStackDepth,
+                                               void * const pvParameters,
+                                               UBaseType_t uxPriority,
+                                               StackType_t * const puxStackBuffer,
+                                               StaticTask_t * const pxTaskBuffer,
+                                               UBaseType_t uxCoreAffinityMask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ * @endcode
+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ * @code{c}
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ * @endcode
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
+                                      TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                 UBaseType_t uxCoreAffinityMask,
+                                                 TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ * @endcode
+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ * @code{c}
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * // The StaticTask_t variable is only included in the structure when
+ * // configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+ * // be used to force the variable into the RTOS kernel's privileged data area.
+ * static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ *
+ *  &xTaskBuffer; // Holds the task's data structure.
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestrictedStatic( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ * @endcode
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                       UBaseType_t uxCoreAffinityMask,
+                                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+ * @endcode
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTaskToModify The handle of the task being updated.
+ *
+ * @param[in] pxRegions A pointer to a MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+ * @code{c}
+ * // Define an array of MemoryRegion_t structures that configures an MPU region
+ * // allowing read/write access for 1024 bytes starting at the beginning of the
+ * // ucOneKByte array.  The other two of the maximum 3 definable regions are
+ * // unused so set to zero.
+ * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+ * {
+ *  // Base address     Length      Parameters
+ *  { ucOneKByte,       1024,       portMPU_REGION_READ_WRITE },
+ *  { 0,                0,          0 },
+ *  { 0,                0,          0 }
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ *  // This task was created such that it has access to certain regions of
+ *  // memory as defined by the MPU configuration.  At some point it is
+ *  // desired that these MPU regions are replaced with that defined in the
+ *  // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+ *  // for this purpose.  NULL is used as the task handle to indicate that this
+ *  // function should modify the MPU regions of the calling task.
+ *  vTaskAllocateMPURegions( NULL, xAltRegions );
+ *
+ *  // Now the task can continue its function, but from this point on can only
+ *  // access its stack and the ucOneKByte array (unless any other statically
+ *  // defined or shared regions have been declared elsewhere).
+ * }
+ * @endcode
+ * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions
+ * \ingroup Tasks
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+                                  const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskDelete( TaskHandle_t xTaskToDelete );
+ * @endcode
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTaskToDelete The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+ * @code{c}
+ * void vOtherFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create the task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   vTaskDelete( xHandle );
+ * }
+ * @endcode
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+* TASK CONTROL API
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskDelay( const TickType_t xTicksToDelay );
+ * @endcode
+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will affect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See xTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+ *
+ * void vTaskFunction( void * pvParameters )
+ * {
+ * // Block for 500ms.
+ * const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+ *
+ *   for( ;; )
+ *   {
+ *       // Simply toggle the LED every 500ms, blocking between each toggle.
+ *       vToggleLED();
+ *       vTaskDelay( xDelay );
+ *   }
+ * }
+ *
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
+ * @endcode
+ *
+ * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a
+ * time specified in milliseconds with a resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within xTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling xTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * @return Value which can be used to check whether the task was actually delayed.
+ * Will be pdTRUE if the task way delayed and pdFALSE otherwise.  A task will not
+ * be delayed if the next expected wake time is in the past.
+ *
+ * Example usage:
+ * @code{c}
+ * // Perform an action every 10 ticks.
+ * void vTaskFunction( void * pvParameters )
+ * {
+ * TickType_t xLastWakeTime;
+ * const TickType_t xFrequency = 10;
+ * BaseType_t xWasDelayed;
+ *
+ *     // Initialise the xLastWakeTime variable with the current time.
+ *     xLastWakeTime = xTaskGetTickCount ();
+ *     for( ;; )
+ *     {
+ *         // Wait for the next cycle.
+ *         xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency );
+ *
+ *         // Perform action here. xWasDelayed value can be used to determine
+ *         // whether a deadline was missed if the code here took too long.
+ *     }
+ * }
+ * @endcode
+ * \defgroup xTaskDelayUntil xTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                            const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/*
+ * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not
+ * return a value.
+ */
+#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )                   \
+    do {                                                                        \
+        ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); \
+    } while( 0 )
+
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+    BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+ * @code{c}
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to obtain the priority of the created task.
+ *   // It was created with tskIDLE_PRIORITY, but may have changed
+ *   // it itself.
+ *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+ *   {
+ *       // The task has changed it's priority.
+ *   }
+ *
+ *   // ...
+ *
+ *   // Is our priority higher than the created task?
+ *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+ *   {
+ *       // Our priority (obtained using NULL handle) is higher.
+ *   }
+ * }
+ * @endcode
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_uxTaskPriorityGet and configUSE_MUTEXES must be defined as 1 for this
+ * function to be available. See the configuration section for more information.
+ *
+ * Obtain the base priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the base priority of the calling task being returned.
+ *
+ * @return The base priority of xTask.
+ *
+ * \defgroup uxTaskPriorityGet uxTaskBasePriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * A version of uxTaskBasePriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * eTaskState eTaskGetState( TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+    eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+ * @endcode
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @param xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+ * @code{c}
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * TaskStatus_t xTaskDetails;
+ *
+ *  // Obtain the handle of a task from its name.
+ *  xHandle = xTaskGetHandle( "Task_Name" );
+ *
+ *  // Check the handle is not NULL.
+ *  configASSERT( xHandle );
+ *
+ *  // Use the handle to obtain further information about the task.
+ *  vTaskGetInfo( xHandle,
+ *                &xTaskDetails,
+ *                pdTRUE, // Include the high water mark in xTaskDetails.
+ *                eInvalid ); // Include the task state in xTaskDetails.
+ * }
+ * @endcode
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+ * @endcode
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+ * @code{c}
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to raise the priority of the created task.
+ *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+ *
+ *   // ...
+ *
+ *   // Use a NULL handle to raise our priority to the same value.
+ *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ * }
+ * @endcode
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask,
+                       UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskSuspend( TaskHandle_t xTaskToSuspend );
+ * @endcode
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+ * @code{c}
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Suspend ourselves.
+ *   vTaskSuspend( NULL );
+ *
+ *   // We cannot get here unless another task calls vTaskResume
+ *   // with our handle as the parameter.
+ * }
+ * @endcode
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskResume( TaskHandle_t xTaskToResume );
+ * @endcode
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+ * @code{c}
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Resume the suspended task ourselves.
+ *   vTaskResume( xHandle );
+ *
+ *   // The created task will once again get microcontroller processing
+ *   // time in accordance with its priority within the system.
+ * }
+ * @endcode
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
+ * @endcode
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_CORE_AFFINITY == 1 )
+
+/**
+ * @brief Sets the core affinity mask for a task.
+ *
+ * It sets the cores on which a task can run. configUSE_CORE_AFFINITY must
+ * be defined as 1 for this function to be available.
+ *
+ * @param xTask The handle of the task to set the core affinity mask for.
+ * Passing NULL will set the core affinity mask for the calling task.
+ *
+ * @param uxCoreAffinityMask A bitwise value that indicates the cores on
+ * which the task can run. Cores are numbered from 0 to configNUMBER_OF_CORES - 1.
+ * For example, to ensure that a task can run on core 0 and core 1, set
+ * uxCoreAffinityMask to 0x03.
+ *
+ * Example usage:
+ *
+ * // The function that creates task.
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * UBaseType_t uxCoreAffinityMask;
+ *
+ *      // Create a task, storing the handle.
+ *      xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
+ *
+ *      // Define the core affinity mask such that this task can only run
+ *      // on core 0 and core 2.
+ *      uxCoreAffinityMask = ( ( 1 << 0 ) | ( 1 << 2 ) );
+ *
+ *      //Set the core affinity mask for the task.
+ *      vTaskCoreAffinitySet( xHandle, uxCoreAffinityMask );
+ * }
+ */
+    void vTaskCoreAffinitySet( const TaskHandle_t xTask,
+                               UBaseType_t uxCoreAffinityMask );
+#endif
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+
+/**
+ * @brief Gets the core affinity mask for a task.
+ *
+ * configUSE_CORE_AFFINITY must be defined as 1 for this function to be
+ * available.
+ *
+ * @param xTask The handle of the task to get the core affinity mask for.
+ * Passing NULL will get the core affinity mask for the calling task.
+ *
+ * @return The core affinity mask which is a bitwise value that indicates
+ * the cores on which a task can run. Cores are numbered from 0 to
+ * configNUMBER_OF_CORES - 1. For example, if a task can run on core 0 and core 1,
+ * the core affinity mask is 0x03.
+ *
+ * Example usage:
+ *
+ * // Task handle of the networking task - it is populated elsewhere.
+ * TaskHandle_t xNetworkingTaskHandle;
+ *
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * UBaseType_t uxNetworkingCoreAffinityMask;
+ *
+ *     // Create a task, storing the handle.
+ *     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
+ *
+ *     //Get the core affinity mask for the networking task.
+ *     uxNetworkingCoreAffinityMask = vTaskCoreAffinityGet( xNetworkingTaskHandle );
+ *
+ *     // Here is a hypothetical scenario, just for the example. Assume that we
+ *     // have 2 cores - Core 0 and core 1. We want to pin the application task to
+ *     // the core different than the networking task to ensure that the
+ *     // application task does not interfere with networking.
+ *     if( ( uxNetworkingCoreAffinityMask & ( 1 << 0 ) ) != 0 )
+ *     {
+ *         // The networking task can run on core 0, pin our task to core 1.
+ *         vTaskCoreAffinitySet( xHandle, ( 1 << 1 ) );
+ *     }
+ *     else
+ *     {
+ *         // Otherwise, pin our task to core 0.
+ *         vTaskCoreAffinitySet( xHandle, ( 1 << 0 ) );
+ *     }
+ * }
+ */
+    UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask );
+#endif
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+/**
+ * @brief Disables preemption for a task.
+ *
+ * @param xTask The handle of the task to disable preemption. Passing NULL
+ * disables preemption for the calling task.
+ *
+ * Example usage:
+ *
+ * void vTaskCode( void *pvParameters )
+ * {
+ *     // Silence warnings about unused parameters.
+ *     ( void ) pvParameters;
+ *
+ *     for( ;; )
+ *     {
+ *         // ... Perform some function here.
+ *
+ *         // Disable preemption for this task.
+ *         vTaskPreemptionDisable( NULL );
+ *
+ *         // The task will not be preempted when it is executing in this portion ...
+ *
+ *         // ... until the preemption is enabled again.
+ *         vTaskPreemptionEnable( NULL );
+ *
+ *         // The task can be preempted when it is executing in this portion.
+ *     }
+ * }
+ */
+    void vTaskPreemptionDisable( const TaskHandle_t xTask );
+#endif
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+/**
+ * @brief Enables preemption for a task.
+ *
+ * @param xTask The handle of the task to enable preemption. Passing NULL
+ * enables preemption for the calling task.
+ *
+ * Example usage:
+ *
+ * void vTaskCode( void *pvParameters )
+ * {
+ *     // Silence warnings about unused parameters.
+ *     ( void ) pvParameters;
+ *
+ *     for( ;; )
+ *     {
+ *         // ... Perform some function here.
+ *
+ *         // Disable preemption for this task.
+ *         vTaskPreemptionDisable( NULL );
+ *
+ *         // The task will not be preempted when it is executing in this portion ...
+ *
+ *         // ... until the preemption is enabled again.
+ *         vTaskPreemptionEnable( NULL );
+ *
+ *         // The task can be preempted when it is executing in this portion.
+ *     }
+ * }
+ */
+    void vTaskPreemptionEnable( const TaskHandle_t xTask );
+#endif
+
+/*-----------------------------------------------------------
+* SCHEDULER CONTROL
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskStartScheduler( void );
+ * @endcode
+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+ * @code{c}
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will not get here unless a task calls vTaskEndScheduler ()
+ * }
+ * @endcode
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskEndScheduler( void );
+ * @endcode
+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+ * @code{c}
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // At some point we want to end the real time kernel processing
+ *       // so call ...
+ *       vTaskEndScheduler ();
+ *   }
+ * }
+ *
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will only get here when the vTaskCode () task has called
+ *   // vTaskEndScheduler ().  When we get here we are back to single task
+ *   // execution.
+ * }
+ * @endcode
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskSuspendAll( void );
+ * @endcode
+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+ * @code{c}
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the kernel
+ *       // tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.
+ *       xTaskResumeAll ();
+ *   }
+ * }
+ * @endcode
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskResumeAll( void );
+ * @endcode
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *         returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @code{c}
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the real
+ *       // time kernel tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.  We want to force
+ *       // a context switch - but there is no point if resuming the scheduler
+ *       // caused a context switch already.
+ *       if( !xTaskResumeAll () )
+ *       {
+ *            taskYIELD ();
+ *       }
+ *   }
+ * }
+ * @endcode
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+* TASK UTILITIES
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * @code{c}
+ * TickType_t xTaskGetTickCount( void );
+ * @endcode
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * TickType_t xTaskGetTickCountFromISR( void );
+ * @endcode
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * uint16_t uxTaskGetNumberOfTasks( void );
+ * @endcode
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * char *pcTaskGetName( TaskHandle_t xTaskToQuery );
+ * @endcode
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );
+ * @endcode
+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask,
+ *                                   StackType_t ** ppuxStackBuffer,
+ *                                   StaticTask_t ** ppxTaskBuffer );
+ * @endcode
+ *
+ * Retrieve pointers to a statically created task's data structure
+ * buffer and stack buffer. These are the same buffers that are supplied
+ * at the time of creation.
+ *
+ * @param xTask The task for which to retrieve the buffers.
+ *
+ * @param ppuxStackBuffer Used to return a pointer to the task's stack buffer.
+ *
+ * @param ppxTaskBuffer Used to return a pointer to the task's data structure
+ * buffer.
+ *
+ * @return pdTRUE if buffers were retrieved, pdFALSE otherwise.
+ *
+ * \defgroup xTaskGetStaticBuffers xTaskGetStaticBuffers
+ * \ingroup TaskUtils
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask,
+                                      StackType_t ** ppuxStackBuffer,
+                                      StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task.h
+ * @code{c}
+ * UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task.h
+ * @code{c}
+ * configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/* When using trace macros it is sometimes necessary to include task.h before
+ * FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+ * so the following two prototypes will cause a compilation error.  This can be
+ * fixed by simply guarding against the inclusion of these two prototypes unless
+ * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+ * constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+    #if configUSE_APPLICATION_TASK_TAG == 1
+
+/**
+ * task.h
+ * @code{c}
+ * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+ * @endcode
+ *
+ * Sets pxHookFunction to be the task hook function used by the task xTask.
+ * Passing xTask as NULL has the effect of setting the calling tasks hook
+ * function.
+ */
+        void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                         TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * @code{c}
+ * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+ * @endcode
+ *
+ * Returns the pxHookFunction value assigned to the task xTask.  Do not
+ * call from an interrupt service routine - call
+ * xTaskGetApplicationTaskTagFromISR() instead.
+ */
+        TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * @code{c}
+ * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
+ * @endcode
+ *
+ * Returns the pxHookFunction value assigned to the task xTask.  Can
+ * be called from an interrupt service routine.
+ */
+        TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+    #endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+/* Each task contains an array of pointers that is dimensioned by the
+ * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+ * kernel does not use the pointers itself, so the application writer can use
+ * the pointers for any purpose they wish.  The following two functions are
+ * used to set and query a pointer respectively. */
+    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue ) PRIVILEGED_FUNCTION;
+    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName);
+ * @endcode
+ *
+ * The application stack overflow hook is called when a stack overflow is detected for a task.
+ *
+ * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
+ *
+ * @param xTask the task that just exceeded its stack boundaries.
+ * @param pcTaskName A character string containing the name of the offending task.
+ */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
+    void vApplicationStackOverflowHook( TaskHandle_t xTask,
+                                        char * pcTaskName );
+
+#endif
+
+#if ( configUSE_IDLE_HOOK == 1 )
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationIdleHook( void );
+ * @endcode
+ *
+ * The application idle hook is called by the idle task.
+ * This allows the application designer to add background functionality without
+ * the overhead of a separate task.
+ * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK.
+ */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
+    void vApplicationIdleHook( void );
+
+#endif
+
+
+#if  ( configUSE_TICK_HOOK != 0 )
+
+/**
+ *  task.h
+ * @code{c}
+ * void vApplicationTickHook( void );
+ * @endcode
+ *
+ * This hook function is called in the system tick handler after any OS work is completed.
+ */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
+    void vApplicationTickHook( void );
+
+#endif
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+ * @endcode
+ *
+ * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB.  This function is required when
+ * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
+ *
+ * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
+ * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
+ * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ */
+    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                        StackType_t ** ppxIdleTaskStackBuffer,
+                                        uint32_t * pulIdleTaskStackSize );
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize, BaseType_t xCoreID )
+ * @endcode
+ *
+ * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB.  This function is required when
+ * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
+ *
+ * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
+ *  1. 1 Active idle task which does all the housekeeping.
+ *  2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
+ * These idle tasks are created to ensure that each core has an idle task to run when
+ * no other task is available to run.
+ *
+ * The function vApplicationGetPassiveIdleTaskMemory is called with passive idle
+ * task index 0, 1 ... ( configNUMBER_OF_CORES - 2 ) to get memory for passive idle
+ * tasks.
+ *
+ * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
+ * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
+ * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param xPassiveIdleTaskIndex The passive idle task index of the idle task buffer
+ */
+    #if ( configNUMBER_OF_CORES > 1 )
+        void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                                   StackType_t ** ppxIdleTaskStackBuffer,
+                                                   uint32_t * pulIdleTaskStackSize,
+                                                   BaseType_t xPassiveIdleTaskIndex );
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+/**
+ * task.h
+ * @code{c}
+ * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+ * @endcode
+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                             void * pvParameter ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * In single-core FreeRTOS, this function simply returns the handle of the idle
+ * task. It is not valid to call xTaskGetIdleTaskHandle() before the scheduler
+ * has been started.
+ *
+ * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
+ *  1. 1 Active idle task which does all the housekeeping.
+ *  2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
+ * These idle tasks are created to ensure that each core has an idle task to run when
+ * no other task is available to run. Call xTaskGetIdleTaskHandle() or
+ * xTaskGetIdleTaskHandleForCore() with xCoreID set to 0  to get the Active
+ * idle task handle. Call xTaskGetIdleTaskHandleForCore() with xCoreID set to
+ * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task handles.
+ */
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( configNUMBER_OF_CORES == 1 )
+        TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif /* #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+ * @code{c}
+ *  // This example demonstrates how a human readable table of run time stats
+ *  // information is generated from raw data provided by uxTaskGetSystemState().
+ *  // The human readable table is written to pcWriteBuffer
+ *  void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ *  {
+ *  TaskStatus_t *pxTaskStatusArray;
+ *  volatile UBaseType_t uxArraySize, x;
+ *  configRUN_TIME_COUNTER_TYPE ulTotalRunTime, ulStatsAsPercentage;
+ *
+ *      // Make sure the write buffer does not contain a string.
+ * pcWriteBuffer = 0x00;
+ *
+ *      // Take a snapshot of the number of tasks in case it changes while this
+ *      // function is executing.
+ *      uxArraySize = uxTaskGetNumberOfTasks();
+ *
+ *      // Allocate a TaskStatus_t structure for each task.  An array could be
+ *      // allocated statically at compile time.
+ *      pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+ *
+ *      if( pxTaskStatusArray != NULL )
+ *      {
+ *          // Generate raw status information about each task.
+ *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+ *
+ *          // For percentage calculations.
+ *          ulTotalRunTime /= 100UL;
+ *
+ *          // Avoid divide by zero errors.
+ *          if( ulTotalRunTime > 0 )
+ *          {
+ *              // For each populated position in the pxTaskStatusArray array,
+ *              // format the raw data as human readable ASCII data
+ *              for( x = 0; x < uxArraySize; x++ )
+ *              {
+ *                  // What percentage of the total run time has the task used?
+ *                  // This will always be rounded down to the nearest integer.
+ *                  // ulTotalRunTimeDiv100 has already been divided by 100.
+ *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+ *
+ *                  if( ulStatsAsPercentage > 0UL )
+ *                  {
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ *                  }
+ *                  else
+ *                  {
+ *                      // If the percentage is zero here then the task has
+ *                      // consumed less than 1% of the total run time.
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+ *                  }
+ *
+ *                  pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+ *              }
+ *          }
+ *
+ *          // The array is no longer needed, free the memory it consumes.
+ *          vPortFree( pxTaskStatusArray );
+ *      }
+ *  }
+ *  @endcode
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskListTasks( char *pcWriteBuffer, size_t uxBufferLength );
+ * @endcode
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task:
+ * names, states, priority, stack usage and task number.
+ * Stack usage specified as the number of unused StackType_t words stack can hold
+ * on top of stack - not the number of bytes.
+ *
+ * vTaskListTasks() has a dependency on the snprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskListTasks().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * @param uxBufferLength Length of the pcWriteBuffer.
+ *
+ * \defgroup vTaskListTasks vTaskListTasks
+ * \ingroup TaskUtils
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+    void vTaskListTasks( char * pcWriteBuffer,
+                         size_t uxBufferLength ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskList( char *pcWriteBuffer );
+ * @endcode
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * WARN: This function assumes that the pcWriteBuffer is of length
+ * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
+ * backward compatibility. New applications are recommended to
+ * use vTaskListTasks and supply the length of the pcWriteBuffer explicitly.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task:
+ * names, states, priority, stack usage and task number.
+ * Stack usage specified as the number of unused StackType_t words stack can hold
+ * on top of stack - not the number of bytes.
+ *
+ * vTaskList() has a dependency on the snprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+#define vTaskList( pcWriteBuffer )    vTaskListTasks( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH )
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskGetRunTimeStatistics( char *pcWriteBuffer, size_t uxBufferLength );
+ * @endcode
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStatistics() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part of
+ * the uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStatistics().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * @param uxBufferLength Length of the pcWriteBuffer.
+ *
+ * \defgroup vTaskGetRunTimeStatistics vTaskGetRunTimeStatistics
+ * \ingroup TaskUtils
+ */
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+    void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                    size_t uxBufferLength ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskGetRunTimeStats( char *pcWriteBuffer );
+ * @endcode
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * WARN: This function assumes that the pcWriteBuffer is of length
+ * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
+ * backward compatiblity. New applications are recommended to use
+ * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer
+ * explicitly.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the snprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+#define vTaskGetRunTimeStats( pcWriteBuffer )    vTaskGetRunTimeStatistics( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH )
+
+/**
+ * task. h
+ * @code{c}
+ * configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask );
+ * configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * configGENERATE_RUN_TIME_STATS must be defined as 1 for these functions to be
+ * available.  The application must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+ * portGET_RUN_TIME_COUNTER_VALUE() to configure a peripheral timer/counter and
+ * return the timers current count value respectively.  The counter should be
+ * at least 10 times the frequency of the tick count.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+ * execution time of each task into a buffer, ulTaskGetRunTimeCounter()
+ * returns the total execution time of just one task and
+ * ulTaskGetRunTimePercent() returns the percentage of the CPU time used by
+ * just one task.
+ *
+ * @return The total run time of the given task or the percentage of the total
+ * run time consumed by the given task.  This is the amount of time the task
+ * has actually been executing.  The unit of time is dependent on the frequency
+ * configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+ * portGET_RUN_TIME_COUNTER_VALUE() macros.
+ *
+ * \defgroup ulTaskGetRunTimeCounter ulTaskGetRunTimeCounter
+ * \ingroup TaskUtils
+ */
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void );
+ * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void );
+ * @endcode
+ *
+ * configGENERATE_RUN_TIME_STATS must be defined as 1 for these functions to be
+ * available.  The application must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+ * portGET_RUN_TIME_COUNTER_VALUE() to configure a peripheral timer/counter and
+ * return the timers current count value respectively.  The counter should be
+ * at least 10 times the frequency of the tick count.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+ * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+ * returns the total execution time of just the idle task and
+ * ulTaskGetIdleRunTimePercent() returns the percentage of the CPU time used by
+ * just the idle task.
+ *
+ * Note the amount of idle time is only a good measure of the slack time in a
+ * system if there are no other tasks executing at the idle priority, tickless
+ * idle is not used, and configIDLE_SHOULD_YIELD is set to 0.
+ *
+ * @return The total run time of the idle task or the percentage of the total
+ * run time consumed by the idle task.  This is the amount of time the
+ * idle task has actually been executing.  The unit of time is dependent on the
+ * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+ * portGET_RUN_TIME_COUNTER_VALUE() macros.
+ *
+ * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+ * \ingroup TaskUtils
+ */
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction );
+ * BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
+ * @endcode
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * Sends a direct to task notification to a task, with an optional value and
+ * action.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * A task can use xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() to
+ * [optionally] block to wait for a notification to be pending.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
+ * un-indexed equivalents).  If the task was already in the Blocked state to
+ * wait for a notification when the notification arrives then the task will
+ * automatically be removed from the Blocked state (unblocked) and the
+ * notification cleared.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotify() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed()
+ * with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotify() does
+ * not have this parameter and always sends notifications to index 0.
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The target notification value is bitwise ORed with ulValue.
+ * xTaskNotifyIndexed() always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The target notification value is incremented.  ulValue is not used and
+ * xTaskNotifyIndexed() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The target notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification at the
+ * same array index (the task already had a notification pending at that index).
+ * xTaskNotifyIndexed() always returns pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending at the
+ * same array index then the target notification value is set to ulValue and
+ * xTaskNotifyIndexed() will return pdPASS.  If the task being notified already
+ * had a notification pending at the same array index then no action is
+ * performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification at the specified array index without the
+ * notification value at that index being updated.  ulValue is not used and
+ * xTaskNotifyIndexed() always returns pdPASS in this case.
+ *
+ * pulPreviousNotificationValue -
+ * Can be used to pass out the subject task's notification value before any
+ * bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                               UBaseType_t uxIndexToNotify,
+                               uint32_t ulValue,
+                               eNotifyAction eAction,
+                               uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
+ * BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
+ * @endcode
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * xTaskNotifyAndQueryIndexed() performs the same operation as
+ * xTaskNotifyIndexed() with the addition that it also returns the subject
+ * task's prior notification value (the notification value at the time the
+ * function is called rather than when the function returns) in the additional
+ * pulPreviousNotifyValue parameter.
+ *
+ * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the
+ * addition that it also returns the subject task's prior notification value
+ * (the notification value as it was at the time the function is called, rather
+ * than when the function returns) in the additional pulPreviousNotifyValue
+ * parameter.
+ *
+ * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
+ * BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * A version of xTaskNotifyIndexed() that can be used from an interrupt service
+ * routine (ISR).
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
+ * to wait for a notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
+ * un-indexed equivalents).  If the task was already in the Blocked state to
+ * wait for a notification when the notification arrives then the task will
+ * automatically be removed from the Blocked state (unblocked) and the
+ * notification cleared.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyFromISR() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling xTaskNotifyFromISR() is equivalent to calling
+ * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyFromISR()
+ * does not have this parameter and always sends notifications to index 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNotify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
+                                      UBaseType_t uxIndexToNotify,
+                                      uint32_t ulValue,
+                                      eNotifyAction eAction,
+                                      uint32_t * pulPreviousNotificationValue,
+                                      BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
+ * BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as
+ * xTaskNotifyIndexedFromISR() with the addition that it also returns the
+ * subject task's prior notification value (the notification value at the time
+ * the function is called rather than at the time the function returns) in the
+ * additional pulPreviousNotifyValue parameter.
+ *
+ * xTaskNotifyAndQueryFromISR() performs the same operation as
+ * xTaskNotifyFromISR() with the addition that it also returns the subject
+ * task's prior notification value (the notification value at the time the
+ * function is called rather than at the time the function returns) in the
+ * additional pulPreviousNotifyValue parameter.
+ *
+ * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ *
+ * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ * @endcode
+ *
+ * Waits for a direct to task notification to be pending at a given index within
+ * an array of direct to task notifications.
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
+ * un-indexed equivalents).  If the task was already in the Blocked state to
+ * wait for a notification when the notification arrives then the task will
+ * automatically be removed from the Blocked state (unblocked) and the
+ * notification cleared.
+ *
+ * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
+ * to wait for a notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyWait() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling xTaskNotifyWait() is equivalent to calling
+ * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0.
+ *
+ * @param uxIndexToWaitOn The index within the calling task's array of
+ * notification values on which the calling task will wait for a notification to
+ * be received.  uxIndexToWaitOn must be less than
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyWait() does
+ * not have this parameter and always waits for notifications on index 0.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICKS( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                   uint32_t ulBitsToClearOnEntry,
+                                   uint32_t ulBitsToClearOnExit,
+                                   uint32_t * pulNotificationValue,
+                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
+    xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
+#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
+    xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify );
+ * BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );
+ * @endcode
+ *
+ * Sends a direct to task notification to a particular index in the target
+ * task's notification array in a manner similar to giving a counting semaphore.
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * macros to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGiveIndexed() is a helper macro intended for use when task
+ * notifications are used as light weight and faster binary or counting
+ * semaphore equivalents.  Actual FreeRTOS semaphores are given using the
+ * xSemaphoreGive() API function, the equivalent action that instead uses a task
+ * notification is xTaskNotifyGiveIndexed().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotifyTakeIndexed() API function rather than the
+ * xTaskNotifyWaitIndexed() API function.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyGive() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling xTaskNotifyGive() is equivalent to calling
+ * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyGive()
+ * does not have this parameter and always sends notifications to index 0.
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )
+#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken );
+ * void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
+ *
+ * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt
+ * service routine (ISR).
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveIndexedFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotifyTakeIndexed() API function rather than the
+ * xTaskNotifyWaitIndexed() API function.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyFromISR() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling
+ * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
+ * xTaskNotifyGiveFromISR() does not have this parameter and always sends
+ * notifications to index 0.
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR
+ * \ingroup TaskNotifications
+ */
+void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
+                                    UBaseType_t uxIndexToNotify,
+                                    BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \
+    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) )
+#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \
+    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * @code{c}
+ * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ *
+ * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ * @endcode
+ *
+ * Waits for a direct to task notification on a particular index in the calling
+ * task's notification array in a manner similar to taking a counting semaphore.
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTakeIndexed() is intended for use when a task notification is
+ * used as a faster and lighter weight binary or counting semaphore alternative.
+ * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function,
+ * the equivalent action that instead uses a task notification is
+ * ulTaskNotifyTakeIndexed().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGiveIndexed()
+ * macro, or xTaskNotifyIndex() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTakeIndexed() can either clear the task's notification value at
+ * the array index specified by the uxIndexToWaitOn parameter to zero on exit,
+ * in which case the notification value acts like a binary semaphore, or
+ * decrement the notification value on exit, in which case the notification
+ * value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for
+ * a notification.  The task does not consume any CPU time while it is in the
+ * Blocked state.
+ *
+ * Where as xTaskNotifyWaitIndexed() will return when a notification is pending,
+ * ulTaskNotifyTakeIndexed() will return when the task's notification value is
+ * not zero.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  ulTaskNotifyTake() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling ulTaskNotifyTake() is equivalent to calling
+ * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0.
+ *
+ * @param uxIndexToWaitOn The index within the calling task's array of
+ * notification values on which the calling task will wait for a notification to
+ * be non-zero.  uxIndexToWaitOn must be less than
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyTake() does
+ * not have this parameter and always waits for notifications on index 0.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICKS( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                  BaseType_t xClearCountOnExit,
+                                  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \
+    ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )
+#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \
+    ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) )
+
+/**
+ * task. h
+ * @code{c}
+ * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear );
+ *
+ * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+ * @endcode
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * If a notification is sent to an index within the array of notifications then
+ * the notification at that index is said to be 'pending' until it is read or
+ * explicitly cleared by the receiving task.  xTaskNotifyStateClearIndexed()
+ * is the function that clears a pending notification without reading the
+ * notification value.  The notification value at the same array index is not
+ * altered.  Set xTask to NULL to clear the notification state of the calling
+ * task.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyStateClear() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling xTaskNotifyStateClear() is equivalent to calling
+ * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTask The handle of the RTOS task that will have a notification state
+ * cleared.  Set xTask to NULL to clear a notification state in the calling
+ * task.  To obtain a task's handle create the task using xTaskCreate() and
+ * make use of the pxCreatedTask parameter, or create the task using
+ * xTaskCreateStatic() and store the returned value, or use the task's name in
+ * a call to xTaskGetHandle().
+ *
+ * @param uxIndexToClear The index within the target task's array of
+ * notification values to act upon.  For example, setting uxIndexToClear to 1
+ * will clear the state of the notification at index 1 within the array.
+ * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
+ * ulTaskNotifyStateClear() does not have this parameter and always acts on the
+ * notification at index 0.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ *
+ * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                         UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyStateClear( xTask ) \
+    xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )
+#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \
+    xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )
+
+/**
+ * task. h
+ * @code{c}
+ * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear );
+ *
+ * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
+ * @endcode
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * ulTaskNotifyValueClearIndexed() clears the bits specified by the
+ * ulBitsToClear bit mask in the notification value at array index uxIndexToClear
+ * of the task referenced by xTask.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  ulTaskNotifyValueClear() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling
+ * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0.
+ *
+ * @param xTask The handle of the RTOS task that will have bits in one of its
+ * notification values cleared. Set xTask to NULL to clear bits in a
+ * notification value of the calling task.  To obtain a task's handle create the
+ * task using xTaskCreate() and make use of the pxCreatedTask parameter, or
+ * create the task using xTaskCreateStatic() and store the returned value, or
+ * use the task's name in a call to xTaskGetHandle().
+ *
+ * @param uxIndexToClear The index within the target task's array of
+ * notification values in which to clear the bits.  uxIndexToClear
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
+ * ulTaskNotifyValueClear() does not have this parameter and always clears bits
+ * in the notification value at index 0.
+ *
+ * @param ulBitsToClear Bit mask of the bits to clear in the notification value of
+ * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification
+ * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+ * the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+ * notification value without clearing any bits.
+ *
+ *
+ * @return The value of the target task's notification value before the bits
+ * specified by ulBitsToClear were cleared.
+ * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                        UBaseType_t uxIndexToClear,
+                                        uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \
+    ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )
+#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \
+    ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )
+
+/**
+ * task.h
+ * @code{c}
+ * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+ * @endcode
+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * @code{c}
+ * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+ * @endcode
+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTicksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * @code{c}
+ *  // Driver library function used to receive uxWantedBytes from an Rx buffer
+ *  // that is filled by a UART interrupt. If there are not enough bytes in the
+ *  // Rx buffer then the task enters the Blocked state until it is notified that
+ *  // more data has been placed into the buffer. If there is still not enough
+ *  // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+ *  // is used to re-calculate the Block time to ensure the total amount of time
+ *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+ *  // continues until either the buffer contains at least uxWantedBytes bytes,
+ *  // or the total amount of time spent in the Blocked state reaches
+ *  // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are
+ *  // available up to a maximum of uxWantedBytes.
+ *
+ *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+ *  {
+ *  size_t uxReceived = 0;
+ *  TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+ *  TimeOut_t xTimeOut;
+ *
+ *      // Initialize xTimeOut.  This records the time at which this function
+ *      // was entered.
+ *      vTaskSetTimeOutState( &xTimeOut );
+ *
+ *      // Loop until the buffer contains the wanted number of bytes, or a
+ *      // timeout occurs.
+ *      while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+ *      {
+ *          // The buffer didn't contain enough data so this task is going to
+ *          // enter the Blocked state. Adjusting xTicksToWait to account for
+ *          // any time that has been spent in the Blocked state within this
+ *          // function so far to ensure the total amount of time spent in the
+ *          // Blocked state does not exceed MAX_TIME_TO_WAIT.
+ *          if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+ *          {
+ *              //Timed out before the wanted number of bytes were available,
+ *              // exit the loop.
+ *              break;
+ *          }
+ *
+ *          // Wait for a maximum of xTicksToWait ticks to be notified that the
+ *          // receive interrupt has placed more data into the buffer.
+ *          ulTaskNotifyTake( pdTRUE, xTicksToWait );
+ *      }
+ *
+ *      // Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+ *      // The actual number of bytes read (which might be less than
+ *      // uxWantedBytes) is returned.
+ *      uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+ *                                                  pucBuffer,
+ *                                                  uxWantedBytes );
+ *
+ *      return uxReceived;
+ *  }
+ * @endcode
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                 TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * @code{c}
+ * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp );
+ * @endcode
+ *
+ * This function corrects the tick count value after the application code has held
+ * interrupts disabled for an extended period resulting in tick interrupts having
+ * been missed.
+ *
+ * This function is similar to vTaskStepTick(), however, unlike
+ * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+ * time at which a task should be removed from the blocked state.  That means
+ * tasks may have to be removed from the blocked state as the tick count is
+ * moved.
+ *
+ * @param xTicksToCatchUp The number of tick interrupts that have been missed due to
+ * interrupts being disabled.  Its value is not computed automatically, so must be
+ * computed by the application writer.
+ *
+ * @return pdTRUE if moving the tick count forward resulted in a task leaving the
+ * blocked state and a context switch being performed.  Otherwise pdFALSE.
+ *
+ * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+
+/*-----------------------------------------------------------
+* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+*----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskYIELD_WITHIN_API()    portYIELD_WITHIN_API()
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    #define taskYIELD_WITHIN_API()    vTaskYieldWithinAPI()
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning task's priority) to insert the list item into the event list in task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks, the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList,
+                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
+                                     const TickType_t xItemValue,
+                                     const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
+                                        const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+#if ( configNUMBER_OF_CORES == 1 )
+    portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+#else
+    portDONT_DISCARD void vTaskSwitchContext( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the task running on specified core.
+ */
+#if ( configNUMBER_OF_CORES > 1 )
+    TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
+                                          UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTaskNumber assigned to the task referenced by the xTask parameter.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vTaskSetTaskNumber( TaskHandle_t xTask,
+                             const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+    void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+    eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critical
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only. Same as portYIELD_WITHIN_API() in single core FreeRTOS.
+ * For SMP this is not defined by the port.
+ */
+#if ( configNUMBER_OF_CORES > 1 )
+    void vTaskYieldWithinAPI( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
+ * is greater than 1. This function can be used in the implementation of portENTER_CRITICAL
+ * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
+ * It should be used in the implementation of portENTER_CRITICAL if port is running a
+ * multiple core FreeRTOS.
+ */
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
+    void vTaskEnterCritical( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
+ * is greater than 1. This function can be used in the implementation of portEXIT_CRITICAL
+ * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
+ * It should be used in the implementation of portEXIT_CRITICAL if port is running a
+ * multiple core FreeRTOS.
+ */
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
+    void vTaskExitCritical( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when configNUMBER_OF_CORES is greater than 1. This function
+ * should be used in the implementation of portENTER_CRITICAL_FROM_ISR if port is
+ * running a multiple core FreeRTOS.
+ */
+#if ( configNUMBER_OF_CORES > 1 )
+    UBaseType_t vTaskEnterCriticalFromISR( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when configNUMBER_OF_CORES is greater than 1. This function
+ * should be used in the implementation of portEXIT_CRITICAL_FROM_ISR if port is
+ * running a multiple core FreeRTOS.
+ */
+#if ( configNUMBER_OF_CORES > 1 )
+    void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+#endif
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+/*
+ * For internal use only.  Get MPU settings associated with a task.
+ */
+    xMPU_SETTINGS * xTaskGetMPUSettings( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/*
+ * For internal use only.  Grant/Revoke a task's access to a kernel object.
+ */
+    void vGrantAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
+                                     int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION;
+    void vRevokeAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
+                                      int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Grant/Revoke a task's access to a kernel object.
+ */
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+#endif /* INC_TASK_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/timers.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/timers.h
new file mode 100644
index 0000000000..f771808654
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/include/timers.h
@@ -0,0 +1,1425 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+#include "task.h"
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+* MACROS AND DEFINITIONS
+*----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+ * be used solely through the macros that make up the public software timer API,
+ * as defined below.  The commands that are sent from interrupts must use the
+ * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+ * or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR    ( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK             ( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE             ( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START                        ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET                        ( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP                         ( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD                ( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE                       ( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND               ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR               ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR               ( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR                ( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR       ( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (* PendedFunction_t)( void * arg1,
+                                   uint32_t arg2 );
+
+/**
+ * TimerHandle_t xTimerCreate(  const char * const pcTimerName,
+ *                              TickType_t xTimerPeriodInTicks,
+ *                              BaseType_t xAutoReload,
+ *                              void * pvTimerID,
+ *                              TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  Time timer period must be greater than 0.
+ *
+ * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created because there is
+ * insufficient FreeRTOS heap remaining to allocate the timer
+ * structures then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ *     // Optionally do something if the pxTimer parameter is NULL.
+ *     configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",             // Just a text name, not used by the kernel.
+ *                                         ( 100 * ( x + 1 ) ), // The timer period in ticks.
+ *                                         pdTRUE,              // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,        // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback       // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    TimerHandle_t xTimerCreate( const char * const pcTimerName,
+                                const TickType_t xTimerPeriodInTicks,
+                                const BaseType_t xAutoReload,
+                                void * const pvTimerID,
+                                TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ *                                  TickType_t xTimerPeriodInTicks,
+ *                                  BaseType_t xAutoReload,
+ *                                  void * pvTimerID,
+ *                                  TimerCallbackFunction_t pxCallbackFunction,
+ *                                  StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  The timer period must be greater than 0.
+ *
+ * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
+                                      const TickType_t xTimerPeriodInTicks,
+                                      const BaseType_t xAutoReload,
+                                      void * const pvTimerID,
+                                      TimerCallbackFunction_t pxCallbackFunction,
+                                      StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer,
+                       void * pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod(   TimerHandle_t xTimer,
+ *                                  TickType_t xNewPeriod,
+ *                                  TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR(   TimerHandle_t xTimer,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR(    TimerHandle_t xTimer,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *                                       TickType_t xNewPeriod,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR(   TimerHandle_t xTimer,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *  // The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *  {
+ *      BaseType_t xInterfaceToService;
+ *
+ *      // The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *      xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *      // ...Perform the processing here...
+ *  }
+ *
+ *  // An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *  {
+ *      BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *      // Query the hardware to determine which interface needs processing.
+ *      xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *      // number of the interface that needs processing.  The interface to
+ *      // service is passed in the second parameter.  The first parameter is
+ *      // not used in this case.
+ *      xHigherPriorityTaskWoken = pdFALSE;
+ *      xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *      // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *      // switch should be requested.  The macro used is port specific and will
+ *      // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *      // the documentation page for the port being used.
+ *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *  }
+ * @endverbatim
+ */
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+    BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+                                              void * pvParameter1,
+                                              uint32_t ulParameter2,
+                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+ *                                    void *pvParameter1,
+ *                                    uint32_t ulParameter2,
+ *                                    TickType_t xTicksToWait );
+ *
+ *
+ * Used to defer the execution of a function to the RTOS daemon task (the timer
+ * service task, hence this function is implemented in timers.c and is prefixed
+ * with 'Timer').
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param xTicksToWait Calling this function will result in a message being
+ * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+ * time the calling task should remain in the Blocked state (so not using any
+ * processing time) for space to become available on the timer queue if the
+ * queue is found to be full.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ */
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+    BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                       void * pvParameter1,
+                                       uint32_t ulParameter2,
+                                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer,
+                          const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer );
+ *
+ * Queries a timer to determine if it is an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+ * pdFALSE is returned.
+ */
+BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+ *
+ * Queries a timer to determine if it is an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+ * pdFALSE is returned.
+ */
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+ *
+ * Returns the time in ticks at which the timer will expire.  If this is less
+ * than the current tick count then the expiry time has overflowed from the
+ * current time.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return If the timer is running then the time in ticks at which the timer
+ * will next expire is returned.  If the timer is not running then the return
+ * value is undefined.
+ */
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer,
+ *                                   StaticTimer_t ** ppxTimerBuffer );
+ *
+ * Retrieve pointer to a statically created timer's data structure
+ * buffer. This is the same buffer that is supplied at the time of
+ * creation.
+ *
+ * @param xTimer The timer for which to retrieve the buffer.
+ *
+ * @param ppxTaskBuffer Used to return a pointer to the timers's data
+ * structure buffer.
+ *
+ * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer,
+                                      StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Splitting the xTimerGenericCommand into two sub functions and making it a macro
+ * removes a recursion path when called from ISRs. This is primarily for the XCore
+ * XCC port which detects the recursion path and throws an error during compilation
+ * when this is not split.
+ */
+BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                         const BaseType_t xCommandID,
+                                         const TickType_t xOptionalValue,
+                                         BaseType_t * const pxHigherPriorityTaskWoken,
+                                         const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                        const BaseType_t xCommandID,
+                                        const TickType_t xOptionalValue,
+                                        BaseType_t * const pxHigherPriorityTaskWoken,
+                                        const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#define xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )         \
+    ( ( xCommandID ) < tmrFIRST_FROM_ISR_COMMAND ?                                                                  \
+      xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) : \
+      xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) )
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vTimerSetTimerNumber( TimerHandle_t xTimer,
+                               UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+    UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+ * @endcode
+ *
+ * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB.  This function is required when
+ * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
+ *
+ * @param ppxTimerTaskTCBBuffer   A handle to a statically allocated TCB buffer
+ * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
+ * @param pulTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
+ */
+    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+                                         StackType_t ** ppxTimerTaskStackBuffer,
+                                         uint32_t * pulTimerTaskStackSize );
+
+#endif
+
+#if ( configUSE_DAEMON_TASK_STARTUP_HOOK != 0 )
+
+/**
+ *  timers.h
+ * @code{c}
+ * void vApplicationDaemonTaskStartupHook( void );
+ * @endcode
+ *
+ * This hook function is called form the timer task once when the task starts running.
+ */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
+    void vApplicationDaemonTaskStartupHook( void );
+
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+#endif /* TIMERS_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/list.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/list.c
new file mode 100644
index 0000000000..227b3cbc8d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/list.c
@@ -0,0 +1,247 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "list.h"
+
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
+ * defined for the header files above, but not in this file, in order to
+ * generate the correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/*-----------------------------------------------------------
+* PUBLIC LIST API documented in list.h
+*----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+    traceENTER_vListInitialise( pxList );
+
+    /* The list structure contains a list item which is used to mark the
+     * end of the list.  To initialise the list the list end is inserted
+     * as the only list entry. */
+    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );
+
+    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
+
+    /* The list end value is the highest possible value in the list to
+     * ensure it remains at the end of the list. */
+    pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+    /* The list end next and previous pointers point to itself so we know
+     * when the list is empty. */
+    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );
+    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );
+
+    /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
+    #if ( configUSE_MINI_LIST_ITEM == 0 )
+    {
+        pxList->xListEnd.pvOwner = NULL;
+        pxList->xListEnd.pxContainer = NULL;
+        listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
+    }
+    #endif
+
+    pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+    /* Write known values into the list if
+     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+    listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+
+    traceRETURN_vListInitialise();
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+    traceENTER_vListInitialiseItem( pxItem );
+
+    /* Make sure the list item is not recorded as being on a list. */
+    pxItem->pxContainer = NULL;
+
+    /* Write known values into the list item if
+     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+    listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+
+    traceRETURN_vListInitialiseItem();
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList,
+                     ListItem_t * const pxNewListItem )
+{
+    ListItem_t * const pxIndex = pxList->pxIndex;
+
+    traceENTER_vListInsertEnd( pxList, pxNewListItem );
+
+    /* Only effective when configASSERT() is also defined, these tests may catch
+     * the list data structures being overwritten in memory.  They will not catch
+     * data errors caused by incorrect configuration or use of FreeRTOS. */
+    listTEST_LIST_INTEGRITY( pxList );
+    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+    /* Insert a new list item into pxList, but rather than sort the list,
+     * makes the new list item the last item to be removed by a call to
+     * listGET_OWNER_OF_NEXT_ENTRY(). */
+    pxNewListItem->pxNext = pxIndex;
+    pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+    /* Only used during decision coverage testing. */
+    mtCOVERAGE_TEST_DELAY();
+
+    pxIndex->pxPrevious->pxNext = pxNewListItem;
+    pxIndex->pxPrevious = pxNewListItem;
+
+    /* Remember which list the item is in. */
+    pxNewListItem->pxContainer = pxList;
+
+    ( pxList->uxNumberOfItems )++;
+
+    traceRETURN_vListInsertEnd();
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList,
+                  ListItem_t * const pxNewListItem )
+{
+    ListItem_t * pxIterator;
+    const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+    traceENTER_vListInsert( pxList, pxNewListItem );
+
+    /* Only effective when configASSERT() is also defined, these tests may catch
+     * the list data structures being overwritten in memory.  They will not catch
+     * data errors caused by incorrect configuration or use of FreeRTOS. */
+    listTEST_LIST_INTEGRITY( pxList );
+    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+    /* Insert the new list item into the list, sorted in xItemValue order.
+     *
+     * If the list already contains a list item with the same item value then the
+     * new list item should be placed after it.  This ensures that TCBs which are
+     * stored in ready lists (all of which have the same xItemValue value) get a
+     * share of the CPU.  However, if the xItemValue is the same as the back marker
+     * the iteration loop below will not end.  Therefore the value is checked
+     * first, and the algorithm slightly modified if necessary. */
+    if( xValueOfInsertion == portMAX_DELAY )
+    {
+        pxIterator = pxList->xListEnd.pxPrevious;
+    }
+    else
+    {
+        /* *** NOTE ***********************************************************
+        *  If you find your application is crashing here then likely causes are
+        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for
+        *  more tips, and ensure configASSERT() is defined!
+        *  https://www.FreeRTOS.org/a00110.html#configASSERT
+        *
+        *   1) Stack overflow -
+        *      see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
+        *   2) Incorrect interrupt priority assignment, especially on Cortex-M
+        *      parts where numerically high priority values denote low actual
+        *      interrupt priorities, which can seem counter intuitive.  See
+        *      https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition
+        *      of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+        *      https://www.FreeRTOS.org/a00110.html
+        *   3) Calling an API function from within a critical section or when
+        *      the scheduler is suspended, or calling an API function that does
+        *      not end in "FromISR" from an interrupt.
+        *   4) Using a queue or semaphore before it has been initialised or
+        *      before the scheduler has been started (are interrupts firing
+        *      before vTaskStartScheduler() has been called?).
+        *   5) If the FreeRTOS port supports interrupt nesting then ensure that
+        *      the priority of the tick interrupt is at or below
+        *      configMAX_SYSCALL_INTERRUPT_PRIORITY.
+        **********************************************************************/
+
+        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
+        {
+            /* There is nothing to do here, just iterating to the wanted
+             * insertion position. */
+        }
+    }
+
+    pxNewListItem->pxNext = pxIterator->pxNext;
+    pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+    pxNewListItem->pxPrevious = pxIterator;
+    pxIterator->pxNext = pxNewListItem;
+
+    /* Remember which list the item is in.  This allows fast removal of the
+     * item later. */
+    pxNewListItem->pxContainer = pxList;
+
+    ( pxList->uxNumberOfItems )++;
+
+    traceRETURN_vListInsert();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+    /* The list item knows which list it is in.  Obtain the list from the list
+     * item. */
+    List_t * const pxList = pxItemToRemove->pxContainer;
+
+    traceENTER_uxListRemove( pxItemToRemove );
+
+
+
+    pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+    pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+    /* Only used during decision coverage testing. */
+    mtCOVERAGE_TEST_DELAY();
+
+    /* Make sure the index is left pointing to a valid item. */
+    if( pxList->pxIndex == pxItemToRemove )
+    {
+        pxList->pxIndex = pxItemToRemove->pxPrevious;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    pxItemToRemove->pxContainer = NULL;
+    ( pxList->uxNumberOfItems )--;
+
+    traceRETURN_uxListRemove( pxList->uxNumberOfItems );
+
+    return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
new file mode 100644
index 0000000000..d5db255f03
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -0,0 +1,2077 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
+
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_vTaskDelay == 1 )
+
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_eTaskGetState == 1 )
+
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
+            );
+        }
+
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
+            );
+        }
+
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+/*-----------------------------------------------------------*/
+
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "                                                               \n"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 0000000000..1c62314bb8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,2124 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU includes. */
+#include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG                 ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER    ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16    ( 0xE000E3F0 )
+#define portAIRCR_REG                      ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE                ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS              ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK            ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                 ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used during system call enter and exit.
+ */
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Offsets in the stack to the parameters when inside the SVC handler.
+ */
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+
+/* Extract first address of the MPU region as encoded in the
+ * RBAR (Region Base Address Register) value. */
+#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
+    ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK )
+
+/* Extract last address of the MPU region as encoded in the
+ * RLAR (Region Limit Address Register) value. */
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
+    ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
+
+/* Does addr lies within [start, end] address range? */
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
+    ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
+
+/* Is the access request satisfied by the available permissions? */
+#define portIS_AUTHORIZED( accessRequest, permissions ) \
+    ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX    ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b )    ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 94UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the default SysTick clock rate.  If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( portNVIC_SYSTICK_CLK_BIT )
+#else
+    /* Select the option to clock SysTick not at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )
+#endif
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Extract MPU region's access permissions from the Region Base Address
+ * Register (RBAR) value.
+ *
+ * @param ulRBARValue RBAR value for the MPU region.
+ *
+ * @return uint32_t Access permissions.
+ */
+    static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+/**
+ * @brief Raise SVC for exiting from a system call.
+ */
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Re-enable interrupts - see comments above the cpsid instruction
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+             * is accounted for as best it can be, but using the tickless mode will
+             * inevitably result in some tiny drift of the time maintained by the
+             * kernel with respect to calendar time. */
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+            /* Use the SysTick current-value register to determine the number of
+             * SysTick decrements remaining until the next tick interrupt.  If the
+             * current-value register is zero, then there are actually
+             * ulTimerCountsForOneTick decrements remaining, not zero, because the
+             * SysTick requests the interrupt when decrementing from 1 to 0. */
+            ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            if( ulSysTickDecrementsLeft == 0 )
+            {
+                ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+            }
+
+            /* Calculate the reload value required to wait xExpectedIdleTime
+             * tick periods.  -1 is used because this code normally executes part
+             * way through the first tick period.  But if the SysTick IRQ is now
+             * pending, then clear the IRQ, suppressing the first tick, and correct
+             * the reload value to reflect that the second tick period is already
+             * underway.  The expected idle time is always at least two ticks. */
+            ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+            if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+            {
+                portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+                ulReloadValue -= ulTimerCountsForOneTick;
+            }
+
+            if( ulReloadValue > ulStoppedTimerCompensation )
+            {
+                ulReloadValue -= ulStoppedTimerCompensation;
+            }
+
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine whether the SysTick has already counted to zero. */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt ended the sleep (or is now pending), and
+                 * a new tick period has started.  Reset portNVIC_SYSTICK_LOAD_REG
+                 * with whatever remains of the new tick period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long or because the SysTick current-value register
+                 * is zero. */
+                if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep. */
+
+                /* Use the SysTick current-value register to determine the
+                 * number of SysTick decrements remaining until the expected idle
+                 * time would have ended. */
+                ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+                #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+                {
+                    /* If the SysTick is not using the core clock, the current-
+                     * value register might still be zero here.  In that case, the
+                     * SysTick didn't load from the reload register, and there are
+                     * ulReloadValue decrements remaining in the expected idle
+                     * time, not zero. */
+                    if( ulSysTickDecrementsLeft == 0 )
+                    {
+                        ulSysTickDecrementsLeft = ulReloadValue;
+                    }
+                }
+                #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+                /* Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+             * then set portNVIC_SYSTICK_LOAD_REG back to its standard value.  If
+             * the SysTick is not using the core clock, temporarily configure it to
+             * use the core clock.  This configuration forces the SysTick to load
+             * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+             * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready
+             * to receive the standard value immediately. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+            #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+            {
+                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+            }
+            #else
+            {
+                /* The temporary usage of the core clock has served its purpose,
+                 * as described above.  Resume usage of the other clock. */
+                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+                if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+                {
+                    /* The partial tick period already ended.  Be sure the SysTick
+                     * counts it only once. */
+                    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+                portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+            }
+            #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+            /* Step the tick to account for any tick periods that elapsed. */
+            vTaskStepTick( ulCompleteTickPeriods );
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+    {
+        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+    }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessPermissions = 0;
+
+        if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY )
+        {
+            ulAccessPermissions = tskMPU_READ_PERMISSION;
+        }
+
+        if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE )
+        {
+            ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
+        }
+
+        return ulAccessPermissions;
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* The only permitted number of regions are 8 or 16. */
+        configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            /* Enable non-secure access to the FPU. */
+            SecureInit_EnableNSFPUAccess();
+        }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            traceISR_EXIT_TO_SCHEDULER();
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+        else
+        {
+            traceISR_EXIT();
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0, ulR1;
+        extern TaskHandle_t pxCurrentTCB;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                {
+                    /* Read the CONTROL register value. */
+                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                    /* The task that raised the SVC is privileged if Bit[0]
+                     * in the CONTROL register is 0. */
+                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+                }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                {
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+                }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+
+                /* R0 contains TCB being freed and R1 contains the secure
+                 * context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+                ulR1 = pulCallerStackAddress[ 1 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* De-prioritize the non-secure exceptions so that the
+                 * non-secure pendSV runs at the lowest priority. */
+                SecureInit_DePrioritizeNSExceptions();
+
+                /* Initialize the secure context management system. */
+                SecureContext_Init();
+            }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+            {
+                /* Setup the Floating Point Unit (FPU). */
+                prvSetupFPU();
+            }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
+    {
+        extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+
+        #if defined( __ARMCC_VERSION )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
+        {
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            {
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
+
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
+        }
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    {
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+
+        #if defined( __ARMCC_VERSION )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
+        {
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            {
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+            }
+            else
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+            }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
+        }
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
+    {
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
+    }
+
+#else /* configENABLE_MPU */
+
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+    {
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+    {
+        volatile uint32_t ulImplementedPrioBits = 0;
+        volatile uint8_t ucMaxPriorityValue;
+
+        /* Determine the maximum priority from which ISR safe FreeRTOS API
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+         * ensure interrupt entry is as fast and simple as possible.
+         *
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
+        portNVIC_SHPR2_REG = 0xFF000000;
+
+        /* Read the value back to see how many bits stuck. */
+        ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+        /* Use the same mask on the maximum system call priority. */
+        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+        /* Check that the maximum system call priority is nonzero after
+         * accounting for the number of priority bits supported by the
+         * hardware. A priority of 0 is invalid because setting the BASEPRI
+         * register to 0 unmasks all interrupts, and interrupts with priority 0
+         * cannot be masked using BASEPRI.
+         * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        configASSERT( ucMaxSysCallPriority );
+
+        /* Check that the bits not implemented in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
+
+        /* Calculate the maximum acceptable priority group value for the number
+         * of bits read back. */
+        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+        {
+            ulImplementedPrioBits++;
+            ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+        }
+
+        if( ulImplementedPrioBits == 8 )
+        {
+            /* When the hardware implements 8 priority bits, there is no way for
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
+            configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+            ulMaxPRIGROUPValue = 0;
+        }
+        else
+        {
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+        }
+
+        /* Shift the priority group value back to its position within the AIRCR
+         * register. */
+        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+    }
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
+
+    #if ( configENABLE_MPU == 1 )
+    {
+        /* Setup the Memory Protection Unit (MPU). */
+        prvSetupMPU();
+    }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr0 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                                uint32_t ulBufferLength,
+                                                uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+    {
+        uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+        BaseType_t xAccessGranted = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+            {
+                ulBufferStartAddress = ( uint32_t ) pvBuffer;
+                ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+                for( i = 0; i < portTOTAL_NUM_REGIONS; i++ )
+                {
+                    /* Is the MPU region enabled? */
+                    if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE )
+                    {
+                        if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+                                                         portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+                                                         portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+                            portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+                                                         portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ),
+                                                         portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) &&
+                            portIS_AUTHORIZED( ulAccessRequested,
+                                               prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) )
+                        {
+                            xAccessGranted = pdTRUE;
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+
+        return xAccessGranted;
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that  use the FreeRTOS API must not be left at their
+             * default priority of  zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and  therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings;
+
+            if( xSchedulerRunning == pdFALSE )
+            {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000000..cbfc4ddda4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -0,0 +1,499 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_MPU == 1 )
+
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
+
+#else /* configENABLE_MPU */
+
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "   .syntax unified                                 \n"
+        "                                                   \n"
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   ite ne                                          \n"
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
+        "                                                   \n"
+        "   .align 4                                        \n"
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "   .syntax unified                                 \n"
+        "                                                   \n"
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "   .syntax unified                                 \n"
+        "                                                   \n"
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "   .syntax unified                                 \n"
+        "                                                   \n"
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
+        "   cpsie f                                         \n"
+        "   dsb                                             \n"
+        "   isb                                             \n"
+        "   svc %0                                          \n" /* System call to start the first task. */
+        "   nop                                             \n"
+        "                                                   \n"
+        "   .align 4                                        \n"
+        "xVTORConst: .word 0xe000ed08                       \n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "   .syntax unified                                 \n"
+        "                                                   \n"
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   dsb                                             \n"
+        "   isb                                             \n"
+        "   bx lr                                           \n" /* Return. */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "   .syntax unified                                 \n"
+        "                                                   \n"
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
+        "   dsb                                             \n"
+        "   isb                                             \n"
+        "   bx lr                                           \n" /* Return. */
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
+
+#else /* configENABLE_MPU */
+
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                   \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "blt syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
+
+#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000000..fa3ce35213
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000000..00a1e648ad
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
new file mode 100644
index 0000000000..a7f1cd51df
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -0,0 +1,516 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+    #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+    #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+    #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
+
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH                   ( -1 )
+#define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT                 8
+#define portNOP()
+#define portINLINE                         __inline
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING    1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern BaseType_t xPortIsInsideInterrupt( void );
+
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+    extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configENABLE_MPU == 1 )
+    extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+    extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if ( configENABLE_MPU == 1 )
+    #define portUSING_MPU_WRAPPERS    1
+    #define portPRIVILEGE_BIT         ( 0x80000000UL )
+#else
+    #define portPRIVILEGE_BIT         ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+    /* Define to 8 for backward compatibility. */
+    #define configTOTAL_MPU_REGIONS    ( 8UL )
+#endif
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+#define portPRIVILEGED_RAM_REGION                     ( 3UL )
+#define portSTACK_REGION                              ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+#define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )       /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *              01 --> Device-nGnRE
+ *              10 --> Device-nGRE
+ *              11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )       /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )       /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )       /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )       /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )       /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )       /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+        #ifndef configSYSTEM_CALL_STACK_SIZE
+            #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+        #endif
+
+/**
+ * @brief System call stack.
+ */
+        typedef struct SYSTEM_CALL_STACK_INFO
+        {
+            uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+            uint32_t * pulSystemCallStack;
+            uint32_t * pulSystemCallStackLimit;
+            uint32_t * pulTaskStack;
+            uint32_t ulLinkRegisterAtSystemCallEntry;
+            uint32_t ulStackLimitRegisterAtSystemCallEntry;
+        } xSYSTEM_CALL_STACK_INFO;
+
+    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
+
+        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
+
+        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+    #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
+
+        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
+
+        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+
+    #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
+
+/* Size of an Access Control List (ACL) entry in bits. */
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+        uint32_t ulContext[ MAX_CONTEXT_SIZE ];
+        uint32_t ulTaskFlags;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+            #endif
+        #endif
+    } xMPU_SETTINGS;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+#endif
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+    #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+    #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+    #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+    #define portRESET_PRIVILEGE()    vResetPrivilege()
+#else
+    #define portIS_PRIVILEGED()
+    #define portRAISE_PRIVILEGE()
+    #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    extern BaseType_t xPortIsTaskPrivileged( void );
+
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/ReadMe.url b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/ReadMe.url
new file mode 100644
index 0000000000..4d2d044296
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/ReadMe.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=https://www.FreeRTOS.org/a00111.html
+IDList=
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/heap_3.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/heap_3.c
new file mode 100644
index 0000000000..6405f749bd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/heap_3.c
@@ -0,0 +1,94 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*
+ * Implementation of pvPortMalloc() and vPortFree() that relies on the
+ * compilers own malloc() and free() implementations.
+ *
+ * This file can only be used if the linker is configured to to generate
+ * a heap memory area.
+ *
+ * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
+ * memory management pages of https://www.FreeRTOS.org for more information.
+ */
+
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    void * pvReturn;
+
+    vTaskSuspendAll();
+    {
+        pvReturn = malloc( xWantedSize );
+        traceMALLOC( pvReturn, xWantedSize );
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
+        {
+            vApplicationMallocFailedHook();
+        }
+    }
+    #endif
+
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    if( pv != NULL )
+    {
+        vTaskSuspendAll();
+        {
+            free( pv );
+            traceFREE( pv, 0 );
+        }
+        ( void ) xTaskResumeAll();
+    }
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/heap_4.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/heap_4.c
new file mode 100644
index 0000000000..b8463e29f8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/MemMang/heap_4.c
@@ -0,0 +1,610 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of https://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+#ifndef configHEAP_CLEAR_MEMORY_ON_FREE
+    #define configHEAP_CLEAR_MEMORY_ON_FREE    0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define heapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if multiplying a and b will result in overflow. */
+#define heapMULTIPLY_WILL_OVERFLOW( a, b )     ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+
+/* Check if adding a and b will result in overflow. */
+#define heapADD_WILL_OVERFLOW( a, b )          ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* Check if the subtraction operation ( a - b ) will result in underflow. */
+#define heapSUBTRACT_WILL_UNDERFLOW( a, b )    ( ( a ) < ( b ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define heapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) )
+#define heapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define heapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define heapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )
+#define heapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )
+
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+    PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+ * of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
+} BlockLink_t;
+
+/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers
+ * protection using an application supplied canary value to catch heap
+ * corruption should a heap buffer overflow occur.
+ */
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/**
+ * @brief Application provided function to get a random value to be used as canary.
+ *
+ * @param pxHeapCanary [out] Output parameter to return the canary value.
+ */
+    extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary );
+
+/* Canary value for protecting internal heap pointers. */
+    PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary;
+
+/* Macro to load/store BlockLink_t pointers to memory. By XORing the
+ * pointers with a random canary value, heap overflows will result
+ * in randomly unpredictable pointer values which will be caught by
+ * heapVALIDATE_BLOCK_POINTER assert. */
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
+#else
+
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( pxBlock )
+
+#endif /* configENABLE_HEAP_PROTECTOR */
+
+/* Assert that a heap block pointer is within the heap bounds. */
+#define heapVALIDATE_BLOCK_POINTER( pxBlock )                          \
+    configASSERT( ( ( uint8_t * ) ( pxBlock ) >= &( ucHeap[ 0 ] ) ) && \
+                  ( ( uint8_t * ) ( pxBlock ) <= &( ucHeap[ configTOTAL_HEAP_SIZE - 1 ] ) ) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+ * block must by correctly byte aligned. */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+PRIVILEGED_DATA static BlockLink_t xStart;
+PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+ * number of free bytes remaining, but says nothing about fragmentation. */
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
+PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
+
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock;
+    BlockLink_t * pxPreviousBlock;
+    BlockLink_t * pxNewBlockLink;
+    void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
+
+    if( xWantedSize > 0 )
+    {
+        /* The wanted size must be increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
+            if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
+
+                if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            xWantedSize = 0;
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    vTaskSuspendAll();
+    {
+        /* If this is the first call to malloc then the heap will require
+         * initialisation to setup the list of free blocks. */
+        if( pxEnd == NULL )
+        {
+            prvHeapInit();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* Check the block size we are trying to allocate is not so large that the
+         * top bit is set.  The top bit of the block size member of the BlockLink_t
+         * structure is used to determine who owns the block - the application or
+         * the kernel, so it must be free. */
+        if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+        {
+            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+            {
+                /* Traverse the list from the start (lowest address) block until
+                 * one of adequate size is found. */
+                pxPreviousBlock = &xStart;
+                pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
+                heapVALIDATE_BLOCK_POINTER( pxBlock );
+
+                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) )
+                {
+                    pxPreviousBlock = pxBlock;
+                    pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
+                    heapVALIDATE_BLOCK_POINTER( pxBlock );
+                }
+
+                /* If the end marker was reached then a block of adequate size
+                 * was not found. */
+                if( pxBlock != pxEnd )
+                {
+                    /* Return the memory space pointed to - jumping over the
+                     * BlockLink_t structure at its start. */
+                    pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize );
+                    heapVALIDATE_BLOCK_POINTER( pvReturn );
+
+                    /* This block is being returned for use so must be taken out
+                     * of the list of free blocks. */
+                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                    /* If the block is larger than required it can be split into
+                     * two. */
+                    configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 );
+
+                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+                    {
+                        /* This block is to be split into two.  Create a new
+                         * block following the number of bytes requested. The void
+                         * cast is used to prevent byte alignment warnings from the
+                         * compiler. */
+                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                        configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+                        /* Calculate the sizes of two blocks split from the
+                         * single block. */
+                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                        pxBlock->xBlockSize = xWantedSize;
+
+                        /* Insert the new block into the list of free blocks. */
+                        pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                        pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                    if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                    {
+                        xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* The block is being returned - it is allocated and owned
+                     * by the application and has no "next" block. */
+                    heapALLOCATE_BLOCK( pxBlock );
+                    pxBlock->pxNextFreeBlock = NULL;
+                    xNumberOfSuccessfulAllocations++;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceMALLOC( pvReturn, xWantedSize );
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
+        {
+            vApplicationMallocFailedHook();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        heapVALIDATE_BLOCK_POINTER( pxLink );
+        configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
+        configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                heapFREE_BLOCK( pxLink );
+                #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
+                {
+                    /* Check for underflow as this can occur if xBlockSize is
+                     * overwritten in a heap block. */
+                    if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 )
+                    {
+                        ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+                    }
+                }
+                #endif
+
+                vTaskSuspendAll();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                    xNumberOfSuccessfulFrees++;
+                }
+                ( void ) xTaskResumeAll();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortCalloc( size_t xNum,
+                     size_t xSize )
+{
+    void * pv = NULL;
+
+    if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 )
+    {
+        pv = pvPortMalloc( xNum * xSize );
+
+        if( pv != NULL )
+        {
+            ( void ) memset( pv, 0, xNum * xSize );
+        }
+    }
+
+    return pv;
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
+{
+    BlockLink_t * pxFirstFreeBlock;
+    portPOINTER_SIZE_TYPE uxStartAddress, uxEndAddress;
+    size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxStartAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
+
+    if( ( uxStartAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxStartAddress += ( portBYTE_ALIGNMENT - 1 );
+        uxStartAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= ( size_t ) ( uxStartAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
+    }
+
+    #if ( configENABLE_HEAP_PROTECTOR == 1 )
+    {
+        vApplicationGetRandomHeapCanary( &( xHeapCanary ) );
+    }
+    #endif
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( uxStartAddress );
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxEndAddress = uxStartAddress + ( portPOINTER_SIZE_TYPE ) xTotalHeapSize;
+    uxEndAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
+    uxEndAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+    pxEnd = ( BlockLink_t * ) uxEndAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( BlockLink_t * ) uxStartAddress;
+    pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxEndAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
+    pxFirstFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    if( pxIterator != &xStart )
+    {
+        heapVALIDATE_BLOCK_POINTER( pxIterator );
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
+    {
+        if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t * pxHeapStats )
+{
+    BlockLink_t * pxBlock;
+    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+    vTaskSuspendAll();
+    {
+        pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
+
+        /* pxBlock will be NULL if the heap has not been initialised.  The heap
+         * is initialised automatically when the first allocation is made. */
+        if( pxBlock != NULL )
+        {
+            while( pxBlock != pxEnd )
+            {
+                /* Increment the number of blocks and record the largest block seen
+                 * so far. */
+                xBlocks++;
+
+                if( pxBlock->xBlockSize > xMaxSize )
+                {
+                    xMaxSize = pxBlock->xBlockSize;
+                }
+
+                if( pxBlock->xBlockSize < xMinSize )
+                {
+                    xMinSize = pxBlock->xBlockSize;
+                }
+
+                /* Move to the next block in the chain until the last block is
+                 * reached. */
+                pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
+            }
+        }
+    }
+    ( void ) xTaskResumeAll();
+
+    pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+    pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+    pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+    taskENTER_CRITICAL();
+    {
+        pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+        pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+        pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+        pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+    }
+    taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/readme.txt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/readme.txt
new file mode 100644
index 0000000000..5210a013da
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/portable/readme.txt
@@ -0,0 +1,19 @@
+Each real time kernel port consists of three files that contain the core kernel
+components and are common to every port, and one or more files that are
+specific to a particular microcontroller and/or compiler.
+
+
++ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
+memory allocators as described on the https://www.FreeRTOS.org WEB site.
+
++ The other directories each contain files specific to a particular
+microcontroller or compiler, where the directory name denotes the compiler
+specific files the directory contains.
+
+
+
+For example, if you are interested in the [compiler] port for the [architecture]
+microcontroller, then the port specific files are contained in
+FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
+only port you are interested in then all the other directories can be
+ignored.
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/queue.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/queue.c
new file mode 100644
index 0000000000..0c21982add
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/queue.c
@@ -0,0 +1,3352 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+    #include "croutine.h"
+#endif
+
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED             ( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED    ( ( int8_t ) 0 )
+#define queueINT8_MAX             ( ( int8_t ) 127 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+ * pcTail members are used as pointers into the queue storage area.  When the
+ * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+ * not necessary, and the pcHead pointer is set to NULL to indicate that the
+ * structure instead holds a pointer to the mutex holder (if any).  Map alternative
+ * names to the pcHead and structure member to ensure the readability of the code
+ * is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+ * a union as their usage is mutually exclusive dependent on what the queue is
+ * being used for. */
+#define uxQueueType               pcHead
+#define queueQUEUE_IS_MUTEX       NULL
+
+typedef struct QueuePointers
+{
+    int8_t * pcTail;     /**< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+    int8_t * pcReadFrom; /**< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+    TaskHandle_t xMutexHolder;        /**< The handle of the task that holds the mutex. */
+    UBaseType_t uxRecursiveCallCount; /**< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+ * zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH    ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME          ( ( TickType_t ) 0U )
+
+#if ( configUSE_PREEMPTION == 0 )
+
+/* If the cooperative scheduler is being used then a yield should not be
+ * performed just because a higher priority task has been woken. */
+    #define queueYIELD_IF_USING_PREEMPTION()
+#else
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define queueYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+        #define queueYIELD_IF_USING_PREEMPTION()    vTaskYieldWithinAPI()
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+    int8_t * pcHead;           /**< Points to the beginning of the queue storage area. */
+    int8_t * pcWriteTo;        /**< Points to the free next place in the storage area. */
+
+    union
+    {
+        QueuePointers_t xQueue;     /**< Data required exclusively when this structure is used as a queue. */
+        SemaphoreData_t xSemaphore; /**< Data required exclusively when this structure is used as a semaphore. */
+    } u;
+
+    List_t xTasksWaitingToSend;             /**< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+    List_t xTasksWaitingToReceive;          /**< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+    volatile UBaseType_t uxMessagesWaiting; /**< The number of items currently in the queue. */
+    UBaseType_t uxLength;                   /**< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+    UBaseType_t uxItemSize;                 /**< The size of each items that the queue will hold. */
+
+    volatile int8_t cRxLock;                /**< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+    volatile int8_t cTxLock;                /**< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+    #endif
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+        struct QueueDefinition * pxQueueSetContainer;
+    #endif
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxQueueNumber;
+        uint8_t ucQueueType;
+    #endif
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+ * name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+/* The type stored within the queue registry array.  This allows a name
+ * to be assigned to each queue making kernel aware debugging a little
+ * more user friendly. */
+    typedef struct QUEUE_REGISTRY_ITEM
+    {
+        const char * pcQueueName;
+        QueueHandle_t xHandle;
+    } xQueueRegistryItem;
+
+/* The old xQueueRegistryItem name is maintained above then typedefed to the
+ * new xQueueRegistryItem name below to enable the use of older kernel aware
+ * debuggers. */
+    typedef xQueueRegistryItem QueueRegistryItem_t;
+
+/* The queue registry is simply an array of QueueRegistryItem_t structures.
+ * The pcQueueName member of a structure being NULL is indicative of the
+ * array position being vacant. */
+
+/* MISRA Ref 8.4.2 [Declaration shall be visible] */
+/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+/* coverity[misra_c_2012_rule_8_4_violation] */
+    PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
+                                      const void * pvItemToQueue,
+                                      const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue,
+                                  void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+/*
+ * Checks to see if a queue is a member of a queue set, and if so, notifies
+ * the queue set that the queue contains data.
+ */
+    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
+                                   const UBaseType_t uxItemSize,
+                                   uint8_t * pucQueueStorage,
+                                   const uint8_t ucQueueType,
+                                   Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if ( configUSE_MUTEXES == 1 )
+    static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_MUTEXES == 1 )
+
+/*
+ * If a task waiting for a mutex causes the mutex holder to inherit a
+ * priority, but the waiting task times out, then the holder should
+ * disinherit the priority - but only down to the highest priority of any
+ * other tasks that are waiting for the same mutex.  This function returns
+ * that priority.
+ */
+    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )                            \
+    taskENTER_CRITICAL();                                  \
+    {                                                      \
+        if( ( pxQueue )->cRxLock == queueUNLOCKED )        \
+        {                                                  \
+            ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \
+        }                                                  \
+        if( ( pxQueue )->cTxLock == queueUNLOCKED )        \
+        {                                                  \
+            ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \
+        }                                                  \
+    }                                                      \
+    taskEXIT_CRITICAL()
+
+/*
+ * Macro to increment cTxLock member of the queue data structure. It is
+ * capped at the number of tasks in the system as we cannot unblock more
+ * tasks than the number of tasks in the system.
+ */
+#define prvIncrementQueueTxLock( pxQueue, cTxLock )                           \
+    do {                                                                      \
+        const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks();         \
+        if( ( UBaseType_t ) ( cTxLock ) < uxNumberOfTasks )                   \
+        {                                                                     \
+            configASSERT( ( cTxLock ) != queueINT8_MAX );                     \
+            ( pxQueue )->cTxLock = ( int8_t ) ( ( cTxLock ) + ( int8_t ) 1 ); \
+        }                                                                     \
+    } while( 0 )
+
+/*
+ * Macro to increment cRxLock member of the queue data structure. It is
+ * capped at the number of tasks in the system as we cannot unblock more
+ * tasks than the number of tasks in the system.
+ */
+#define prvIncrementQueueRxLock( pxQueue, cRxLock )                           \
+    do {                                                                      \
+        const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks();         \
+        if( ( UBaseType_t ) ( cRxLock ) < uxNumberOfTasks )                   \
+        {                                                                     \
+            configASSERT( ( cRxLock ) != queueINT8_MAX );                     \
+            ( pxQueue )->cRxLock = ( int8_t ) ( ( cRxLock ) + ( int8_t ) 1 ); \
+        }                                                                     \
+    } while( 0 )
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
+                               BaseType_t xNewQueue )
+{
+    BaseType_t xReturn = pdPASS;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueGenericReset( xQueue, xNewQueue );
+
+    configASSERT( pxQueue );
+
+    if( ( pxQueue != NULL ) &&
+        ( pxQueue->uxLength >= 1U ) &&
+        /* Check for multiplication overflow. */
+        ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) )
+    {
+        taskENTER_CRITICAL();
+        {
+            pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+            pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+            pxQueue->pcWriteTo = pxQueue->pcHead;
+            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize );
+            pxQueue->cRxLock = queueUNLOCKED;
+            pxQueue->cTxLock = queueUNLOCKED;
+
+            if( xNewQueue == pdFALSE )
+            {
+                /* If there are tasks blocked waiting to read from the queue, then
+                 * the tasks will remain blocked as after this function exits the queue
+                 * will still be empty.  If there are tasks blocked waiting to write to
+                 * the queue, then one should be unblocked as after this function exits
+                 * it will be possible to write to it. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* Ensure the event queues start in the correct state. */
+                vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+                vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+    else
+    {
+        xReturn = pdFAIL;
+    }
+
+    configASSERT( xReturn != pdFAIL );
+
+    /* A value is returned for calling semantic consistency with previous
+     * versions. */
+    traceRETURN_xQueueGenericReset( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                             const UBaseType_t uxItemSize,
+                                             uint8_t * pucQueueStorage,
+                                             StaticQueue_t * pxStaticQueue,
+                                             const uint8_t ucQueueType )
+    {
+        Queue_t * pxNewQueue = NULL;
+
+        traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
+
+        /* The StaticQueue_t structure and the queue storage area must be
+         * supplied. */
+        configASSERT( pxStaticQueue );
+
+        if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
+            ( pxStaticQueue != NULL ) &&
+
+            /* A queue storage area should be provided if the item size is not 0, and
+             * should not be provided if the item size is 0. */
+            ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0U ) ) ) &&
+            ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0U ) ) ) )
+        {
+            #if ( configASSERT_DEFINED == 1 )
+            {
+                /* Sanity check that the size of the structure used to declare a
+                 * variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+                 * the real queue and semaphore structures. */
+                volatile size_t xSize = sizeof( StaticQueue_t );
+
+                /* This assertion cannot be branch covered in unit tests */
+                configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
+                ( void ) xSize;                             /* Prevent unused variable warning when configASSERT() is not defined. */
+            }
+            #endif /* configASSERT_DEFINED */
+
+            /* The address of a statically allocated queue was passed in, use it.
+             * The address of a statically allocated storage area was also passed in
+             * but is already set. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            pxNewQueue = ( Queue_t * ) pxStaticQueue;
+
+            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+            {
+                /* Queues can be allocated wither statically or dynamically, so
+                 * note this queue was allocated statically in case the queue is
+                 * later deleted. */
+                pxNewQueue->ucStaticallyAllocated = pdTRUE;
+            }
+            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+            prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+        }
+        else
+        {
+            configASSERT( pxNewQueue );
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xQueueGenericCreateStatic( pxNewQueue );
+
+        return pxNewQueue;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    BaseType_t xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
+                                              uint8_t ** ppucQueueStorage,
+                                              StaticQueue_t ** ppxStaticQueue )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueue = xQueue;
+
+        traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue );
+
+        configASSERT( pxQueue );
+        configASSERT( ppxStaticQueue );
+
+        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+        {
+            /* Check if the queue was statically allocated. */
+            if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
+            {
+                if( ppucQueueStorage != NULL )
+                {
+                    *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead;
+                }
+
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
+                *ppxStaticQueue = ( StaticQueue_t * ) pxQueue;
+                xReturn = pdTRUE;
+            }
+            else
+            {
+                xReturn = pdFALSE;
+            }
+        }
+        #else /* configSUPPORT_DYNAMIC_ALLOCATION */
+        {
+            /* Queue must have been statically allocated. */
+            if( ppucQueueStorage != NULL )
+            {
+                *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead;
+            }
+
+            *ppxStaticQueue = ( StaticQueue_t * ) pxQueue;
+            xReturn = pdTRUE;
+        }
+        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+        traceRETURN_xQueueGenericGetStaticBuffers( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                       const UBaseType_t uxItemSize,
+                                       const uint8_t ucQueueType )
+    {
+        Queue_t * pxNewQueue = NULL;
+        size_t xQueueSizeInBytes;
+        uint8_t * pucQueueStorage;
+
+        traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
+
+        if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
+            /* Check for multiplication overflow. */
+            ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
+            /* Check for addition overflow. */
+            ( ( UBaseType_t ) ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
+        {
+            /* Allocate enough space to hold the maximum number of items that
+             * can be in the queue at any time.  It is valid for uxItemSize to be
+             * zero in the case the queue is used as a semaphore. */
+            xQueueSizeInBytes = ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize );
+
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
+
+            if( pxNewQueue != NULL )
+            {
+                /* Jump past the queue structure to find the location of the queue
+                 * storage area. */
+                pucQueueStorage = ( uint8_t * ) pxNewQueue;
+                pucQueueStorage += sizeof( Queue_t );
+
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    /* Queues can be created either statically or dynamically, so
+                     * note this task was created dynamically in case it is later
+                     * deleted. */
+                    pxNewQueue->ucStaticallyAllocated = pdFALSE;
+                }
+                #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+                prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+            }
+            else
+            {
+                traceQUEUE_CREATE_FAILED( ucQueueType );
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            configASSERT( pxNewQueue );
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xQueueGenericCreate( pxNewQueue );
+
+        return pxNewQueue;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
+                                   const UBaseType_t uxItemSize,
+                                   uint8_t * pucQueueStorage,
+                                   const uint8_t ucQueueType,
+                                   Queue_t * pxNewQueue )
+{
+    /* Remove compiler warnings about unused parameters should
+     * configUSE_TRACE_FACILITY not be set to 1. */
+    ( void ) ucQueueType;
+
+    if( uxItemSize == ( UBaseType_t ) 0 )
+    {
+        /* No RAM was allocated for the queue storage area, but PC head cannot
+         * be set to NULL because NULL is used as a key to say the queue is used as
+         * a mutex.  Therefore just set pcHead to point to the queue as a benign
+         * value that is known to be within the memory map. */
+        pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+    }
+    else
+    {
+        /* Set the head to the start of the queue storage area. */
+        pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+    }
+
+    /* Initialise the queue members as described where the queue type is
+     * defined. */
+    pxNewQueue->uxLength = uxQueueLength;
+    pxNewQueue->uxItemSize = uxItemSize;
+    ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+    {
+        pxNewQueue->ucQueueType = ucQueueType;
+    }
+    #endif /* configUSE_TRACE_FACILITY */
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+    {
+        pxNewQueue->pxQueueSetContainer = NULL;
+    }
+    #endif /* configUSE_QUEUE_SETS */
+
+    traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    static void prvInitialiseMutex( Queue_t * pxNewQueue )
+    {
+        if( pxNewQueue != NULL )
+        {
+            /* The queue create function will set all the queue structure members
+            * correctly for a generic queue, but this function is creating a
+            * mutex.  Overwrite those members that need to be set differently -
+            * in particular the information required for priority inheritance. */
+            pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+            pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+            /* In case this is a recursive mutex. */
+            pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+            traceCREATE_MUTEX( pxNewQueue );
+
+            /* Start with the semaphore in the expected state. */
+            ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+        }
+        else
+        {
+            traceCREATE_MUTEX_FAILED();
+        }
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+    {
+        QueueHandle_t xNewQueue;
+        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+        traceENTER_xQueueCreateMutex( ucQueueType );
+
+        xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+        prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+        traceRETURN_xQueueCreateMutex( xNewQueue );
+
+        return xNewQueue;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue )
+    {
+        QueueHandle_t xNewQueue;
+        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+        traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
+
+        /* Prevent compiler warnings about unused parameters if
+         * configUSE_TRACE_FACILITY does not equal 1. */
+        ( void ) ucQueueType;
+
+        xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+        prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+        traceRETURN_xQueueCreateMutexStatic( xNewQueue );
+
+        return xNewQueue;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+    {
+        TaskHandle_t pxReturn;
+        Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+        traceENTER_xQueueGetMutexHolder( xSemaphore );
+
+        configASSERT( xSemaphore );
+
+        /* This function is called by xSemaphoreGetMutexHolder(), and should not
+         * be called directly.  Note:  This is a good way of determining if the
+         * calling task is the mutex holder, but not a good way of determining the
+         * identity of the mutex holder, as the holder may change between the
+         * following critical section exiting and the function returning. */
+        taskENTER_CRITICAL();
+        {
+            if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+            {
+                pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+            }
+            else
+            {
+                pxReturn = NULL;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xQueueGetMutexHolder( pxReturn );
+
+        return pxReturn;
+    }
+
+#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+    {
+        TaskHandle_t pxReturn;
+
+        traceENTER_xQueueGetMutexHolderFromISR( xSemaphore );
+
+        configASSERT( xSemaphore );
+
+        /* Mutexes cannot be used in interrupt service routines, so the mutex
+         * holder should not change in an ISR, and therefore a critical section is
+         * not required here. */
+        if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+        {
+            pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+        }
+        else
+        {
+            pxReturn = NULL;
+        }
+
+        traceRETURN_xQueueGetMutexHolderFromISR( pxReturn );
+
+        return pxReturn;
+    }
+
+#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+    BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+        traceENTER_xQueueGiveMutexRecursive( xMutex );
+
+        configASSERT( pxMutex );
+
+        /* If this is the task that holds the mutex then xMutexHolder will not
+         * change outside of this task.  If this task does not hold the mutex then
+         * pxMutexHolder can never coincidentally equal the tasks handle, and as
+         * this is the only condition we are interested in it does not matter if
+         * pxMutexHolder is accessed simultaneously by another task.  Therefore no
+         * mutual exclusion is required to test the pxMutexHolder variable. */
+        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+        {
+            traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+            /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+             * the task handle, therefore no underflow check is required.  Also,
+             * uxRecursiveCallCount is only modified by the mutex holder, and as
+             * there can only be one, no mutual exclusion is required to modify the
+             * uxRecursiveCallCount member. */
+            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+            /* Has the recursive call count unwound to 0? */
+            if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+            {
+                /* Return the mutex.  This will automatically unblock any other
+                 * task that might be waiting to access the mutex. */
+                ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            /* The mutex cannot be given because the calling task is not the
+             * holder. */
+            xReturn = pdFAIL;
+
+            traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+        }
+
+        traceRETURN_xQueueGiveMutexRecursive( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+    BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                         TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+        traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait );
+
+        configASSERT( pxMutex );
+
+        /* Comments regarding mutual exclusion as per those within
+         * xQueueGiveMutexRecursive(). */
+
+        traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+        {
+            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+            /* pdPASS will only be returned if the mutex was successfully
+             * obtained.  The calling task may have entered the Blocked state
+             * before reaching here. */
+            if( xReturn != pdFAIL )
+            {
+                ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+            }
+            else
+            {
+                traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+            }
+        }
+
+        traceRETURN_xQueueTakeMutexRecursive( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue )
+    {
+        QueueHandle_t xHandle = NULL;
+
+        traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
+
+        if( ( uxMaxCount != 0U ) &&
+            ( uxInitialCount <= uxMaxCount ) )
+        {
+            xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+            if( xHandle != NULL )
+            {
+                ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+                traceCREATE_COUNTING_SEMAPHORE();
+            }
+            else
+            {
+                traceCREATE_COUNTING_SEMAPHORE_FAILED();
+            }
+        }
+        else
+        {
+            configASSERT( xHandle );
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle );
+
+        return xHandle;
+    }
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount )
+    {
+        QueueHandle_t xHandle = NULL;
+
+        traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount );
+
+        if( ( uxMaxCount != 0U ) &&
+            ( uxInitialCount <= uxMaxCount ) )
+        {
+            xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+            if( xHandle != NULL )
+            {
+                ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+                traceCREATE_COUNTING_SEMAPHORE();
+            }
+            else
+            {
+                traceCREATE_COUNTING_SEMAPHORE_FAILED();
+            }
+        }
+        else
+        {
+            configASSERT( xHandle );
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xQueueCreateCountingSemaphore( xHandle );
+
+        return xHandle;
+    }
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
+                              const void * const pvItemToQueue,
+                              TickType_t xTicksToWait,
+                              const BaseType_t xCopyPosition )
+{
+    BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+    TimeOut_t xTimeOut;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+    {
+        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+    }
+    #endif
+
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            /* Is there room on the queue now?  The running task must be the
+             * highest priority task wanting to access the queue.  If the head item
+             * in the queue is to be overwritten then it does not matter if the
+             * queue is full. */
+            if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+            {
+                traceQUEUE_SEND( pxQueue );
+
+                #if ( configUSE_QUEUE_SETS == 1 )
+                {
+                    const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+                    xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+                    if( pxQueue->pxQueueSetContainer != NULL )
+                    {
+                        if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+                        {
+                            /* Do not notify the queue set as an existing item
+                             * was overwritten in the queue so the number of items
+                             * in the queue has not changed. */
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                        else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                        {
+                            /* The queue is a member of a queue set, and posting
+                             * to the queue set caused a higher priority task to
+                             * unblock. A context switch is required. */
+                            queueYIELD_IF_USING_PREEMPTION();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        /* If there was a task waiting for data to arrive on the
+                         * queue then unblock it now. */
+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                        {
+                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                            {
+                                /* The unblocked task has a priority higher than
+                                 * our own so yield immediately.  Yes it is ok to
+                                 * do this from within the critical section - the
+                                 * kernel takes care of that. */
+                                queueYIELD_IF_USING_PREEMPTION();
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else if( xYieldRequired != pdFALSE )
+                        {
+                            /* This path is a special case that will only get
+                             * executed if the task was holding multiple mutexes
+                             * and the mutexes were given back in an order that is
+                             * different to that in which they were taken. */
+                            queueYIELD_IF_USING_PREEMPTION();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                }
+                #else /* configUSE_QUEUE_SETS */
+                {
+                    xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+                    /* If there was a task waiting for data to arrive on the
+                     * queue then unblock it now. */
+                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                    {
+                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                        {
+                            /* The unblocked task has a priority higher than
+                             * our own so yield immediately.  Yes it is ok to do
+                             * this from within the critical section - the kernel
+                             * takes care of that. */
+                            queueYIELD_IF_USING_PREEMPTION();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else if( xYieldRequired != pdFALSE )
+                    {
+                        /* This path is a special case that will only get
+                         * executed if the task was holding multiple mutexes and
+                         * the mutexes were given back in an order that is
+                         * different to that in which they were taken. */
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                #endif /* configUSE_QUEUE_SETS */
+
+                taskEXIT_CRITICAL();
+
+                traceRETURN_xQueueGenericSend( pdPASS );
+
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* The queue was full and no block time is specified (or
+                     * the block time has expired) so leave now. */
+                    taskEXIT_CRITICAL();
+
+                    /* Return to the original privilege level before exiting
+                     * the function. */
+                    traceQUEUE_SEND_FAILED( pxQueue );
+                    traceRETURN_xQueueGenericSend( errQUEUE_FULL );
+
+                    return errQUEUE_FULL;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The queue was full and a block time was specified so
+                     * configure the timeout structure. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can send to and receive from the queue
+         * now the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            if( prvIsQueueFull( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+                /* Unlocking the queue means queue events can effect the
+                 * event list. It is possible that interrupts occurring now
+                 * remove this task from the event list again - but as the
+                 * scheduler is suspended the task will go onto the pending
+                 * ready list instead of the actual ready list. */
+                prvUnlockQueue( pxQueue );
+
+                /* Resuming the scheduler will move tasks from the pending
+                 * ready list into the ready list - so it is feasible that this
+                 * task is already in the ready list before it yields - in which
+                 * case the yield will not cause a context switch unless there
+                 * is also a higher priority task in the pending ready list. */
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    taskYIELD_WITHIN_API();
+                }
+            }
+            else
+            {
+                /* Try again. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* The timeout has expired. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            traceQUEUE_SEND_FAILED( pxQueue );
+            traceRETURN_xQueueGenericSend( errQUEUE_FULL );
+
+            return errQUEUE_FULL;
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
+                                     const void * const pvItemToQueue,
+                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                     const BaseType_t xCopyPosition )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition );
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    /* Similar to xQueueGenericSend, except without blocking if there is no room
+     * in the queue.  Also don't directly wake a task that was blocked on a queue
+     * read, instead return a flag to say whether a context switch is required or
+     * not (i.e. has a task with a higher priority than us been woken by this
+     * post). */
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+        {
+            const int8_t cTxLock = pxQueue->cTxLock;
+            const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+            traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+            /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+             *  semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+             *  in a task disinheriting a priority and prvCopyDataToQueue() can be
+             *  called here even though the disinherit function does not check if
+             *  the scheduler is suspended before accessing the ready lists. */
+            ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+            /* The event list is not altered if the queue is locked.  This will
+             * be done when the queue is unlocked later. */
+            if( cTxLock == queueUNLOCKED )
+            {
+                #if ( configUSE_QUEUE_SETS == 1 )
+                {
+                    if( pxQueue->pxQueueSetContainer != NULL )
+                    {
+                        if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+                        {
+                            /* Do not notify the queue set as an existing item
+                             * was overwritten in the queue so the number of items
+                             * in the queue has not changed. */
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                        else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                        {
+                            /* The queue is a member of a queue set, and posting
+                             * to the queue set caused a higher priority task to
+                             * unblock.  A context switch is required. */
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                        {
+                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                            {
+                                /* The task waiting has a higher priority so
+                                 *  record that a context switch is required. */
+                                if( pxHigherPriorityTaskWoken != NULL )
+                                {
+                                    *pxHigherPriorityTaskWoken = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                }
+                #else /* configUSE_QUEUE_SETS */
+                {
+                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                    {
+                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                        {
+                            /* The task waiting has a higher priority so record that a
+                             * context switch is required. */
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Not used in this path. */
+                    ( void ) uxPreviousMessagesWaiting;
+                }
+                #endif /* configUSE_QUEUE_SETS */
+            }
+            else
+            {
+                /* Increment the lock count so the task that unlocks the queue
+                 * knows that data was posted while it was locked. */
+                prvIncrementQueueTxLock( pxQueue, cTxLock );
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+            xReturn = errQUEUE_FULL;
+        }
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xQueueGenericSendFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
+                              BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken );
+
+    /* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+     * item size is 0.  Don't directly wake a task that was blocked on a queue
+     * read, instead return a flag to say whether a context switch is required or
+     * not (i.e. has a task with a higher priority than us been woken by this
+     * post). */
+
+    configASSERT( pxQueue );
+
+    /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+     * if the item size is not 0. */
+    configASSERT( pxQueue->uxItemSize == 0 );
+
+    /* Normally a mutex would not be given from an interrupt, especially if
+     * there is a mutex holder, as priority inheritance makes no sense for an
+     * interrupts, only tasks. */
+    configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+        /* When the queue is used to implement a semaphore no data is ever
+         * moved through the queue but it is still valid to see if the queue 'has
+         * space'. */
+        if( uxMessagesWaiting < pxQueue->uxLength )
+        {
+            const int8_t cTxLock = pxQueue->cTxLock;
+
+            traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+            /* A task can only have an inherited priority if it is a mutex
+             * holder - and if there is a mutex holder then the mutex cannot be
+             * given from an ISR.  As this is the ISR version of the function it
+             * can be assumed there is no mutex holder and no need to determine if
+             * priority disinheritance is needed.  Simply increase the count of
+             * messages (semaphores) available. */
+            pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );
+
+            /* The event list is not altered if the queue is locked.  This will
+             * be done when the queue is unlocked later. */
+            if( cTxLock == queueUNLOCKED )
+            {
+                #if ( configUSE_QUEUE_SETS == 1 )
+                {
+                    if( pxQueue->pxQueueSetContainer != NULL )
+                    {
+                        if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                        {
+                            /* The semaphore is a member of a queue set, and
+                             * posting to the queue set caused a higher priority
+                             * task to unblock.  A context switch is required. */
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                        {
+                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                            {
+                                /* The task waiting has a higher priority so
+                                 *  record that a context switch is required. */
+                                if( pxHigherPriorityTaskWoken != NULL )
+                                {
+                                    *pxHigherPriorityTaskWoken = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                }
+                #else /* configUSE_QUEUE_SETS */
+                {
+                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                    {
+                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                        {
+                            /* The task waiting has a higher priority so record that a
+                             * context switch is required. */
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                #endif /* configUSE_QUEUE_SETS */
+            }
+            else
+            {
+                /* Increment the lock count so the task that unlocks the queue
+                 * knows that data was posted while it was locked. */
+                prvIncrementQueueTxLock( pxQueue, cTxLock );
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+            xReturn = errQUEUE_FULL;
+        }
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xQueueGiveFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue,
+                          void * const pvBuffer,
+                          TickType_t xTicksToWait )
+{
+    BaseType_t xEntryTimeSet = pdFALSE;
+    TimeOut_t xTimeOut;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait );
+
+    /* Check the pointer is not NULL. */
+    configASSERT( ( pxQueue ) );
+
+    /* The buffer into which data is received can only be NULL if the data size
+     * is zero (so no data is copied into the buffer). */
+    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+    /* Cannot block if the scheduler is suspended. */
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+    {
+        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+    }
+    #endif
+
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+            /* Is there data in the queue now?  To be running the calling task
+             * must be the highest priority task wanting to access the queue. */
+            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* Data available, remove one item. */
+                prvCopyDataFromQueue( pxQueue, pvBuffer );
+                traceQUEUE_RECEIVE( pxQueue );
+                pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );
+
+                /* There is now space in the queue, were any tasks waiting to
+                 * post to the queue?  If so, unblock the highest priority waiting
+                 * task. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                taskEXIT_CRITICAL();
+
+                traceRETURN_xQueueReceive( pdPASS );
+
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* The queue was empty and no block time is specified (or
+                     * the block time has expired) so leave now. */
+                    taskEXIT_CRITICAL();
+
+                    traceQUEUE_RECEIVE_FAILED( pxQueue );
+                    traceRETURN_xQueueReceive( errQUEUE_EMPTY );
+
+                    return errQUEUE_EMPTY;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The queue was empty and a block time was specified so
+                     * configure the timeout structure. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can send to and receive from the queue
+         * now the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            /* The timeout has not expired.  If the queue is still empty place
+             * the task on the list of tasks waiting to receive from the queue. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+                prvUnlockQueue( pxQueue );
+
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    taskYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* The queue contains data again.  Loop back to try and read the
+                 * data. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* Timed out.  If there is no data in the queue exit, otherwise loop
+             * back and attempt to read the data. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceQUEUE_RECEIVE_FAILED( pxQueue );
+                traceRETURN_xQueueReceive( errQUEUE_EMPTY );
+
+                return errQUEUE_EMPTY;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                TickType_t xTicksToWait )
+{
+    BaseType_t xEntryTimeSet = pdFALSE;
+    TimeOut_t xTimeOut;
+    Queue_t * const pxQueue = xQueue;
+
+    #if ( configUSE_MUTEXES == 1 )
+        BaseType_t xInheritanceOccurred = pdFALSE;
+    #endif
+
+    traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait );
+
+    /* Check the queue pointer is not NULL. */
+    configASSERT( ( pxQueue ) );
+
+    /* Check this really is a semaphore, in which case the item size will be
+     * 0. */
+    configASSERT( pxQueue->uxItemSize == 0 );
+
+    /* Cannot block if the scheduler is suspended. */
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+    {
+        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+    }
+    #endif
+
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            /* Semaphores are queues with an item size of 0, and where the
+             * number of messages in the queue is the semaphore's count value. */
+            const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+            /* Is there data in the queue now?  To be running the calling task
+             * must be the highest priority task wanting to access the queue. */
+            if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+            {
+                traceQUEUE_RECEIVE( pxQueue );
+
+                /* Semaphores are queues with a data size of zero and where the
+                 * messages waiting is the semaphore's count.  Reduce the count. */
+                pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxSemaphoreCount - ( UBaseType_t ) 1 );
+
+                #if ( configUSE_MUTEXES == 1 )
+                {
+                    if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+                    {
+                        /* Record the information required to implement
+                         * priority inheritance should it become necessary. */
+                        pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                #endif /* configUSE_MUTEXES */
+
+                /* Check to see if other tasks are blocked waiting to give the
+                 * semaphore, and if so, unblock the highest priority such task. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                taskEXIT_CRITICAL();
+
+                traceRETURN_xQueueSemaphoreTake( pdPASS );
+
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* The semaphore count was 0 and no block time is specified
+                     * (or the block time has expired) so exit now. */
+                    taskEXIT_CRITICAL();
+
+                    traceQUEUE_RECEIVE_FAILED( pxQueue );
+                    traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );
+
+                    return errQUEUE_EMPTY;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The semaphore count was 0 and a block time was specified
+                     * so configure the timeout structure ready to block. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can give to and take from the semaphore
+         * now the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            /* A block time is specified and not expired.  If the semaphore
+             * count is 0 then enter the Blocked state to wait for a semaphore to
+             * become available.  As semaphores are implemented with queues the
+             * queue being empty is equivalent to the semaphore count being 0. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+                #if ( configUSE_MUTEXES == 1 )
+                {
+                    if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+                    {
+                        taskENTER_CRITICAL();
+                        {
+                            xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+                        }
+                        taskEXIT_CRITICAL();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                #endif /* if ( configUSE_MUTEXES == 1 ) */
+
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+                prvUnlockQueue( pxQueue );
+
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    taskYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* There was no timeout and the semaphore count was not 0, so
+                 * attempt to take the semaphore again. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* Timed out. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            /* If the semaphore count is 0 exit now as the timeout has
+             * expired.  Otherwise return to attempt to take the semaphore that is
+             * known to be available.  As semaphores are implemented by queues the
+             * queue being empty is equivalent to the semaphore count being 0. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                #if ( configUSE_MUTEXES == 1 )
+                {
+                    /* xInheritanceOccurred could only have be set if
+                     * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+                     * test the mutex type again to check it is actually a mutex. */
+                    if( xInheritanceOccurred != pdFALSE )
+                    {
+                        taskENTER_CRITICAL();
+                        {
+                            UBaseType_t uxHighestWaitingPriority;
+
+                            /* This task blocking on the mutex caused another
+                             * task to inherit this task's priority.  Now this task
+                             * has timed out the priority should be disinherited
+                             * again, but only as low as the next highest priority
+                             * task that is waiting for the same mutex. */
+                            uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+
+                            /* vTaskPriorityDisinheritAfterTimeout uses the uxHighestWaitingPriority
+                             * parameter to index pxReadyTasksLists when adding the task holding
+                             * mutex to the ready list for its new priority. Coverity thinks that
+                             * it can result in out-of-bounds access which is not true because
+                             * uxHighestWaitingPriority, as returned by prvGetDisinheritPriorityAfterTimeout,
+                             * is capped at ( configMAX_PRIORITIES - 1 ). */
+                            /* coverity[overrun] */
+                            vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+                        }
+                        taskEXIT_CRITICAL();
+                    }
+                }
+                #endif /* configUSE_MUTEXES */
+
+                traceQUEUE_RECEIVE_FAILED( pxQueue );
+                traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );
+
+                return errQUEUE_EMPTY;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue,
+                       void * const pvBuffer,
+                       TickType_t xTicksToWait )
+{
+    BaseType_t xEntryTimeSet = pdFALSE;
+    TimeOut_t xTimeOut;
+    int8_t * pcOriginalReadPosition;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait );
+
+    /* Check the pointer is not NULL. */
+    configASSERT( ( pxQueue ) );
+
+    /* The buffer into which data is received can only be NULL if the data size
+     * is zero (so no data is copied into the buffer. */
+    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+    /* Cannot block if the scheduler is suspended. */
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+    {
+        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+    }
+    #endif
+
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+            /* Is there data in the queue now?  To be running the calling task
+             * must be the highest priority task wanting to access the queue. */
+            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* Remember the read position so it can be reset after the data
+                 * is read from the queue as this function is only peeking the
+                 * data, not removing it. */
+                pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+                prvCopyDataFromQueue( pxQueue, pvBuffer );
+                traceQUEUE_PEEK( pxQueue );
+
+                /* The data is not being removed, so reset the read pointer. */
+                pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+                /* The data is being left in the queue, so see if there are
+                 * any other tasks waiting for the data. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        /* The task waiting has a higher priority than this task. */
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                taskEXIT_CRITICAL();
+
+                traceRETURN_xQueuePeek( pdPASS );
+
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* The queue was empty and no block time is specified (or
+                     * the block time has expired) so leave now. */
+                    taskEXIT_CRITICAL();
+
+                    traceQUEUE_PEEK_FAILED( pxQueue );
+                    traceRETURN_xQueuePeek( errQUEUE_EMPTY );
+
+                    return errQUEUE_EMPTY;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The queue was empty and a block time was specified so
+                     * configure the timeout structure ready to enter the blocked
+                     * state. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can send to and receive from the queue
+         * now that the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            /* Timeout has not expired yet, check to see if there is data in the
+            * queue now, and if not enter the Blocked state to wait for data. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+                prvUnlockQueue( pxQueue );
+
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    taskYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* There is data in the queue now, so don't enter the blocked
+                 * state, instead return to try and obtain the data. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* The timeout has expired.  If there is still no data in the queue
+             * exit, otherwise go back and try to read the data again. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceQUEUE_PEEK_FAILED( pxQueue );
+                traceRETURN_xQueuePeek( errQUEUE_EMPTY );
+
+                return errQUEUE_EMPTY;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
+                                 void * const pvBuffer,
+                                 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken );
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+        /* Cannot block in an ISR, so check there is data available. */
+        if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+        {
+            const int8_t cRxLock = pxQueue->cRxLock;
+
+            traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+            prvCopyDataFromQueue( pxQueue, pvBuffer );
+            pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );
+
+            /* If the queue is locked the event list will not be modified.
+             * Instead update the lock count so the task that unlocks the queue
+             * will know that an ISR has removed data while the queue was
+             * locked. */
+            if( cRxLock == queueUNLOCKED )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        /* The task waiting has a higher priority than us so
+                         * force a context switch. */
+                        if( pxHigherPriorityTaskWoken != NULL )
+                        {
+                            *pxHigherPriorityTaskWoken = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* Increment the lock count so the task that unlocks the queue
+                 * knows that data was removed while it was locked. */
+                prvIncrementQueueRxLock( pxQueue, cRxLock );
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = pdFAIL;
+            traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+        }
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xQueueReceiveFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
+                              void * const pvBuffer )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    int8_t * pcOriginalReadPosition;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueuePeekFromISR( xQueue, pvBuffer );
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        /* Cannot block in an ISR, so check there is data available. */
+        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+        {
+            traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+            /* Remember the read position so it can be reset as nothing is
+             * actually being removed from the queue. */
+            pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+            prvCopyDataFromQueue( pxQueue, pvBuffer );
+            pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = pdFAIL;
+            traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+        }
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xQueuePeekFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+    UBaseType_t uxReturn;
+
+    traceENTER_uxQueueMessagesWaiting( xQueue );
+
+    configASSERT( xQueue );
+
+    taskENTER_CRITICAL();
+    {
+        uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+    }
+    taskEXIT_CRITICAL();
+
+    traceRETURN_uxQueueMessagesWaiting( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+    UBaseType_t uxReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_uxQueueSpacesAvailable( xQueue );
+
+    configASSERT( pxQueue );
+
+    taskENTER_CRITICAL();
+    {
+        uxReturn = ( UBaseType_t ) ( pxQueue->uxLength - pxQueue->uxMessagesWaiting );
+    }
+    taskEXIT_CRITICAL();
+
+    traceRETURN_uxQueueSpacesAvailable( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+    UBaseType_t uxReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_uxQueueMessagesWaitingFromISR( xQueue );
+
+    configASSERT( pxQueue );
+    uxReturn = pxQueue->uxMessagesWaiting;
+
+    traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_vQueueDelete( xQueue );
+
+    configASSERT( pxQueue );
+    traceQUEUE_DELETE( pxQueue );
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+    {
+        vQueueUnregisterQueue( pxQueue );
+    }
+    #endif
+
+    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+    {
+        /* The queue can only have been allocated dynamically - free it
+         * again. */
+        vPortFree( pxQueue );
+    }
+    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    {
+        /* The queue could have been allocated statically or dynamically, so
+         * check before attempting to free the memory. */
+        if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+        {
+            vPortFree( pxQueue );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */
+    {
+        /* The queue must have been statically allocated, so is not going to be
+         * deleted.  Avoid compiler warnings about the unused parameter. */
+        ( void ) pxQueue;
+    }
+    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+    traceRETURN_vQueueDelete();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+    {
+        traceENTER_uxQueueGetQueueNumber( xQueue );
+
+        traceRETURN_uxQueueGetQueueNumber( ( ( Queue_t * ) xQueue )->uxQueueNumber );
+
+        return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber )
+    {
+        traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber );
+
+        ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+
+        traceRETURN_vQueueSetQueueNumber();
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+    {
+        traceENTER_ucQueueGetQueueType( xQueue );
+
+        traceRETURN_ucQueueGetQueueType( ( ( Queue_t * ) xQueue )->ucQueueType );
+
+        return ( ( Queue_t * ) xQueue )->ucQueueType;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
+{
+    traceENTER_uxQueueGetQueueItemSize( xQueue );
+
+    traceRETURN_uxQueueGetQueueItemSize( ( ( Queue_t * ) xQueue )->uxItemSize );
+
+    return ( ( Queue_t * ) xQueue )->uxItemSize;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
+{
+    traceENTER_uxQueueGetQueueLength( xQueue );
+
+    traceRETURN_uxQueueGetQueueLength( ( ( Queue_t * ) xQueue )->uxLength );
+
+    return ( ( Queue_t * ) xQueue )->uxLength;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+    {
+        UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+        /* If a task waiting for a mutex causes the mutex holder to inherit a
+         * priority, but the waiting task times out, then the holder should
+         * disinherit the priority - but only down to the highest priority of any
+         * other tasks that are waiting for the same mutex.  For this purpose,
+         * return the priority of the highest priority task that is waiting for the
+         * mutex. */
+        if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+        {
+            uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) ( ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ) );
+        }
+        else
+        {
+            uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+        }
+
+        return uxHighestPriorityOfWaitingTasks;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
+                                      const void * pvItemToQueue,
+                                      const BaseType_t xPosition )
+{
+    BaseType_t xReturn = pdFALSE;
+    UBaseType_t uxMessagesWaiting;
+
+    /* This function is called from a critical section. */
+
+    uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+    if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+    {
+        #if ( configUSE_MUTEXES == 1 )
+        {
+            if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+            {
+                /* The mutex is no longer being held. */
+                xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+                pxQueue->u.xSemaphore.xMutexHolder = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #endif /* configUSE_MUTEXES */
+    }
+    else if( xPosition == queueSEND_TO_BACK )
+    {
+        ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
+        pxQueue->pcWriteTo += pxQueue->uxItemSize;
+
+        if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )
+        {
+            pxQueue->pcWriteTo = pxQueue->pcHead;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
+        pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+
+        if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead )
+        {
+            pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( xPosition == queueOVERWRITE )
+        {
+            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* An item is not being added but overwritten, so subtract
+                 * one from the recorded number of items in the queue so when
+                 * one is added again below the number of recorded items remains
+                 * correct. */
+                --uxMessagesWaiting;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue,
+                                  void * const pvBuffer )
+{
+    if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+    {
+        pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+
+        if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+        {
+            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize );
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+    /* The lock counts contains the number of extra data items placed or
+     * removed from the queue while the queue was locked.  When a queue is
+     * locked items can be added or removed, but the event lists cannot be
+     * updated. */
+    taskENTER_CRITICAL();
+    {
+        int8_t cTxLock = pxQueue->cTxLock;
+
+        /* See if data was added to the queue while it was locked. */
+        while( cTxLock > queueLOCKED_UNMODIFIED )
+        {
+            /* Data was posted while the queue was locked.  Are any tasks
+             * blocked waiting for data to become available? */
+            #if ( configUSE_QUEUE_SETS == 1 )
+            {
+                if( pxQueue->pxQueueSetContainer != NULL )
+                {
+                    if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                    {
+                        /* The queue is a member of a queue set, and posting to
+                         * the queue set caused a higher priority task to unblock.
+                         * A context switch is required. */
+                        vTaskMissedYield();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    /* Tasks that are removed from the event list will get
+                     * added to the pending ready list as the scheduler is still
+                     * suspended. */
+                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                    {
+                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                        {
+                            /* The task waiting has a higher priority so record that a
+                             * context switch is required. */
+                            vTaskMissedYield();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        break;
+                    }
+                }
+            }
+            #else /* configUSE_QUEUE_SETS */
+            {
+                /* Tasks that are removed from the event list will get added to
+                 * the pending ready list as the scheduler is still suspended. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        /* The task waiting has a higher priority so record that
+                         * a context switch is required. */
+                        vTaskMissedYield();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    break;
+                }
+            }
+            #endif /* configUSE_QUEUE_SETS */
+
+            --cTxLock;
+        }
+
+        pxQueue->cTxLock = queueUNLOCKED;
+    }
+    taskEXIT_CRITICAL();
+
+    /* Do the same for the Rx lock. */
+    taskENTER_CRITICAL();
+    {
+        int8_t cRxLock = pxQueue->cRxLock;
+
+        while( cRxLock > queueLOCKED_UNMODIFIED )
+        {
+            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+            {
+                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                {
+                    vTaskMissedYield();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                --cRxLock;
+            }
+            else
+            {
+                break;
+            }
+        }
+
+        pxQueue->cRxLock = queueUNLOCKED;
+    }
+    taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue )
+{
+    BaseType_t xReturn;
+
+    taskENTER_CRITICAL();
+    {
+        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+        {
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+    BaseType_t xReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueIsQueueEmptyFromISR( xQueue );
+
+    configASSERT( pxQueue );
+
+    if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    traceRETURN_xQueueIsQueueEmptyFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
+{
+    BaseType_t xReturn;
+
+    taskENTER_CRITICAL();
+    {
+        if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+        {
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+    BaseType_t xReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    traceENTER_xQueueIsQueueFullFromISR( xQueue );
+
+    configASSERT( pxQueue );
+
+    if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    traceRETURN_xQueueIsQueueFullFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
+                             const void * pvItemToQueue,
+                             TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueue = xQueue;
+
+        traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait );
+
+        /* If the queue is already full we may have to block.  A critical section
+         * is required to prevent an interrupt removing something from the queue
+         * between the check to see if the queue is full and blocking on the queue. */
+        portDISABLE_INTERRUPTS();
+        {
+            if( prvIsQueueFull( pxQueue ) != pdFALSE )
+            {
+                /* The queue is full - do we want to block or just leave without
+                 * posting? */
+                if( xTicksToWait > ( TickType_t ) 0 )
+                {
+                    /* As this is called from a coroutine we cannot block directly, but
+                     * return indicating that we need to block. */
+                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_BLOCKED;
+                }
+                else
+                {
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_FULL;
+                }
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        portDISABLE_INTERRUPTS();
+        {
+            if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+            {
+                /* There is room in the queue, copy the data into the queue. */
+                prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+                xReturn = pdPASS;
+
+                /* Were any co-routines waiting for data to become available? */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    /* In this instance the co-routine could be placed directly
+                     * into the ready list as we are within a critical section.
+                     * Instead the same pending ready list mechanism is used as if
+                     * the event were caused from within an interrupt. */
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        /* The co-routine waiting has a higher priority so record
+                         * that a yield might be appropriate. */
+                        xReturn = errQUEUE_YIELD;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                xReturn = errQUEUE_FULL;
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        traceRETURN_xQueueCRSend( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
+                                void * pvBuffer,
+                                TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueue = xQueue;
+
+        traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait );
+
+        /* If the queue is already empty we may have to block.  A critical section
+         * is required to prevent an interrupt adding something to the queue
+         * between the check to see if the queue is empty and blocking on the queue. */
+        portDISABLE_INTERRUPTS();
+        {
+            if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+            {
+                /* There are no messages in the queue, do we want to block or just
+                 * leave with nothing? */
+                if( xTicksToWait > ( TickType_t ) 0 )
+                {
+                    /* As this is a co-routine we cannot block directly, but return
+                     * indicating that we need to block. */
+                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_BLOCKED;
+                }
+                else
+                {
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_FULL;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        portDISABLE_INTERRUPTS();
+        {
+            if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* Data is available from the queue. */
+                pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+
+                if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+                {
+                    pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                --( pxQueue->uxMessagesWaiting );
+                ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+                xReturn = pdPASS;
+
+                /* Were any co-routines waiting for space to become available? */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    /* In this instance the co-routine could be placed directly
+                     * into the ready list as we are within a critical section.
+                     * Instead the same pending ready list mechanism is used as if
+                     * the event were caused from within an interrupt. */
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        xReturn = errQUEUE_YIELD;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        traceRETURN_xQueueCRReceive( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
+                                    const void * pvItemToQueue,
+                                    BaseType_t xCoRoutinePreviouslyWoken )
+    {
+        Queue_t * const pxQueue = xQueue;
+
+        traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken );
+
+        /* Cannot block within an ISR so if there is no space on the queue then
+         * exit without doing anything. */
+        if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+        {
+            prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+            /* We only want to wake one co-routine per ISR, so check that a
+             * co-routine has not already been woken. */
+            if( xCoRoutinePreviouslyWoken == pdFALSE )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        return pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken );
+
+        return xCoRoutinePreviouslyWoken;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
+                                       void * pvBuffer,
+                                       BaseType_t * pxCoRoutineWoken )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueue = xQueue;
+
+        traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken );
+
+        /* We cannot block from an ISR, so check there is data available. If
+         * not then just leave without doing anything. */
+        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+        {
+            /* Copy the data from the queue. */
+            pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+
+            if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+            {
+                pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            --( pxQueue->uxMessagesWaiting );
+            ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+            if( ( *pxCoRoutineWoken ) == pdFALSE )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        *pxCoRoutineWoken = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = pdFAIL;
+        }
+
+        traceRETURN_xQueueCRReceiveFromISR( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+    void vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcQueueName )
+    {
+        UBaseType_t ux;
+        QueueRegistryItem_t * pxEntryToWrite = NULL;
+
+        traceENTER_vQueueAddToRegistry( xQueue, pcQueueName );
+
+        configASSERT( xQueue );
+
+        if( pcQueueName != NULL )
+        {
+            /* See if there is an empty space in the registry.  A NULL name denotes
+             * a free slot. */
+            for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+            {
+                /* Replace an existing entry if the queue is already in the registry. */
+                if( xQueue == xQueueRegistry[ ux ].xHandle )
+                {
+                    pxEntryToWrite = &( xQueueRegistry[ ux ] );
+                    break;
+                }
+                /* Otherwise, store in the next empty location */
+                else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) )
+                {
+                    pxEntryToWrite = &( xQueueRegistry[ ux ] );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+
+        if( pxEntryToWrite != NULL )
+        {
+            /* Store the information on this queue. */
+            pxEntryToWrite->pcQueueName = pcQueueName;
+            pxEntryToWrite->xHandle = xQueue;
+
+            traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+        }
+
+        traceRETURN_vQueueAddToRegistry();
+    }
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+    const char * pcQueueGetName( QueueHandle_t xQueue )
+    {
+        UBaseType_t ux;
+        const char * pcReturn = NULL;
+
+        traceENTER_pcQueueGetName( xQueue );
+
+        configASSERT( xQueue );
+
+        /* Note there is nothing here to protect against another task adding or
+         * removing entries from the registry while it is being searched. */
+
+        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+        {
+            if( xQueueRegistry[ ux ].xHandle == xQueue )
+            {
+                pcReturn = xQueueRegistry[ ux ].pcQueueName;
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        traceRETURN_pcQueueGetName( pcReturn );
+
+        return pcReturn;
+    }
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+    void vQueueUnregisterQueue( QueueHandle_t xQueue )
+    {
+        UBaseType_t ux;
+
+        traceENTER_vQueueUnregisterQueue( xQueue );
+
+        configASSERT( xQueue );
+
+        /* See if the handle of the queue being unregistered in actually in the
+         * registry. */
+        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+        {
+            if( xQueueRegistry[ ux ].xHandle == xQueue )
+            {
+                /* Set the name to NULL to show that this slot if free again. */
+                xQueueRegistry[ ux ].pcQueueName = NULL;
+
+                /* Set the handle to NULL to ensure the same queue handle cannot
+                 * appear in the registry twice if it is added, removed, then
+                 * added again. */
+                xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        traceRETURN_vQueueUnregisterQueue();
+    }
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+    void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
+                                         TickType_t xTicksToWait,
+                                         const BaseType_t xWaitIndefinitely )
+    {
+        Queue_t * const pxQueue = xQueue;
+
+        traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely );
+
+        /* This function should not be called by application code hence the
+         * 'Restricted' in its name.  It is not part of the public API.  It is
+         * designed for use by kernel code, and has special calling requirements.
+         * It can result in vListInsert() being called on a list that can only
+         * possibly ever have one item in it, so the list will be fast, but even
+         * so it should be called with the scheduler locked and not from a critical
+         * section. */
+
+        /* Only do anything if there are no messages in the queue.  This function
+         *  will not actually cause the task to block, just place it on a blocked
+         *  list.  It will not block until the scheduler is unlocked - at which
+         *  time a yield will be performed.  If an item is added to the queue while
+         *  the queue is locked, and the calling task blocks on the queue, then the
+         *  calling task will be immediately unblocked when the queue is unlocked. */
+        prvLockQueue( pxQueue );
+
+        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+        {
+            /* There is nothing in the queue, block for the specified period. */
+            vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        prvUnlockQueue( pxQueue );
+
+        traceRETURN_vQueueWaitForMessageRestricted();
+    }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+    {
+        QueueSetHandle_t pxQueue;
+
+        traceENTER_xQueueCreateSet( uxEventQueueLength );
+
+        pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+        traceRETURN_xQueueCreateSet( pxQueue );
+
+        return pxQueue;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet )
+    {
+        BaseType_t xReturn;
+
+        traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
+
+        taskENTER_CRITICAL();
+        {
+            if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+            {
+                /* Cannot add a queue/semaphore to more than one queue set. */
+                xReturn = pdFAIL;
+            }
+            else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+            {
+                /* Cannot add a queue/semaphore to a queue set if there are already
+                 * items in the queue/semaphore. */
+                xReturn = pdFAIL;
+            }
+            else
+            {
+                ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+                xReturn = pdPASS;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xQueueAddToSet( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+        traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
+
+        if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+        {
+            /* The queue was not a member of the set. */
+            xReturn = pdFAIL;
+        }
+        else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+        {
+            /* It is dangerous to remove a queue from a set when the queue is
+             * not empty because the queue set will still hold pending events for
+             * the queue. */
+            xReturn = pdFAIL;
+        }
+        else
+        {
+            taskENTER_CRITICAL();
+            {
+                /* The queue is no longer contained in the set. */
+                pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+            }
+            taskEXIT_CRITICAL();
+            xReturn = pdPASS;
+        }
+
+        traceRETURN_xQueueRemoveFromSet( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                TickType_t const xTicksToWait )
+    {
+        QueueSetMemberHandle_t xReturn = NULL;
+
+        traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait );
+
+        ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait );
+
+        traceRETURN_xQueueSelectFromSet( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+    {
+        QueueSetMemberHandle_t xReturn = NULL;
+
+        traceENTER_xQueueSelectFromSetFromISR( xQueueSet );
+
+        ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL );
+
+        traceRETURN_xQueueSelectFromSetFromISR( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+    {
+        Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+        BaseType_t xReturn = pdFALSE;
+
+        /* This function must be called form a critical section. */
+
+        /* The following line is not reachable in unit tests because every call
+         * to prvNotifyQueueSetContainer is preceded by a check that
+         * pxQueueSetContainer != NULL */
+        configASSERT( pxQueueSetContainer ); /* LCOV_EXCL_BR_LINE */
+        configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+        if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+        {
+            const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+            traceQUEUE_SET_SEND( pxQueueSetContainer );
+
+            /* The data copied is the handle of the queue that contains data. */
+            xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+            if( cTxLock == queueUNLOCKED )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        /* The task waiting has a higher priority. */
+                        xReturn = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                prvIncrementQueueTxLock( pxQueueSetContainer, cTxLock );
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/stream_buffer.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/stream_buffer.c
new file mode 100644
index 0000000000..e1b10e1907
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/stream_buffer.c
@@ -0,0 +1,1563 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if ( configUSE_TASK_NOTIFICATIONS != 1 )
+    #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+#if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )
+    #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
+#endif
+
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* If the user has not provided application specific Rx notification macros,
+ * or #defined the notification macros away, then provide default implementations
+ * that uses task notifications. */
+#ifndef sbRECEIVE_COMPLETED
+    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                             \
+    do                                                                        \
+    {                                                                         \
+        vTaskSuspendAll();                                                    \
+        {                                                                     \
+            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )              \
+            {                                                                 \
+                ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
+                                      ( uint32_t ) 0,                         \
+                                      eNoAction );                            \
+                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                \
+            }                                                                 \
+        }                                                                     \
+        ( void ) xTaskResumeAll();                                            \
+    } while( 0 )
+#endif /* sbRECEIVE_COMPLETED */
+
+/* If user has provided a per-instance receive complete callback, then
+ * invoke the callback else use the receive complete macro which is provided by default for all instances.
+ */
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define prvRECEIVE_COMPLETED( pxStreamBuffer )                                               \
+    do {                                                                                         \
+        if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                             \
+        {                                                                                        \
+            ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
+        }                                                                                        \
+        else                                                                                     \
+        {                                                                                        \
+            sbRECEIVE_COMPLETED( ( pxStreamBuffer ) );                                           \
+        }                                                                                        \
+    } while( 0 )
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #define prvRECEIVE_COMPLETED( pxStreamBuffer )    sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+    #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                            \
+                                          pxHigherPriorityTaskWoken )                \
+    do {                                                                             \
+        UBaseType_t uxSavedInterruptStatus;                                          \
+                                                                                     \
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                      \
+        {                                                                            \
+            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                     \
+            {                                                                        \
+                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
+                                             ( uint32_t ) 0,                         \
+                                             eNoAction,                              \
+                                             ( pxHigherPriorityTaskWoken ) );        \
+                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                       \
+            }                                                                        \
+        }                                                                            \
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                        \
+    } while( 0 )
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                                               \
+                                           pxHigherPriorityTaskWoken )                                                   \
+    do {                                                                                                                 \
+        if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                                                     \
+        {                                                                                                                \
+            ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \
+        }                                                                                                                \
+        else                                                                                                             \
+        {                                                                                                                \
+            sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                           \
+        }                                                                                                                \
+    } while( 0 )
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+    sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
+/* If the user has not provided an application specific Tx notification macro,
+ * or #defined the notification macro away, then provide a default
+ * implementation that uses task notifications.
+ */
+#ifndef sbSEND_COMPLETED
+    #define sbSEND_COMPLETED( pxStreamBuffer )                               \
+    vTaskSuspendAll();                                                       \
+    {                                                                        \
+        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )              \
+        {                                                                    \
+            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+                                  ( uint32_t ) 0,                            \
+                                  eNoAction );                               \
+            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                \
+        }                                                                    \
+    }                                                                        \
+    ( void ) xTaskResumeAll()
+#endif /* sbSEND_COMPLETED */
+
+/* If user has provided a per-instance send completed callback, then
+ * invoke the callback else use the send complete macro which is provided by default for all instances.
+ */
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define prvSEND_COMPLETED( pxStreamBuffer )                                               \
+    do {                                                                                      \
+        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                             \
+        {                                                                                     \
+            ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
+        }                                                                                     \
+        else                                                                                  \
+        {                                                                                     \
+            sbSEND_COMPLETED( ( pxStreamBuffer ) );                                           \
+        }                                                                                     \
+    } while( 0 )
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #define prvSEND_COMPLETED( pxStreamBuffer )    sbSEND_COMPLETED( ( pxStreamBuffer ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+    #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )       \
+    do {                                                                                \
+        UBaseType_t uxSavedInterruptStatus;                                             \
+                                                                                        \
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                         \
+        {                                                                               \
+            if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
+            {                                                                           \
+                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+                                             ( uint32_t ) 0,                            \
+                                             eNoAction,                                 \
+                                             ( pxHigherPriorityTaskWoken ) );           \
+                ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \
+            }                                                                           \
+        }                                                                               \
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                           \
+    } while( 0 )
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )                                    \
+    do {                                                                                                              \
+        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                                                     \
+        {                                                                                                             \
+            ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \
+        }                                                                                                             \
+        else                                                                                                          \
+        {                                                                                                             \
+            sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                            \
+        }                                                                                                             \
+    } while( 0 )
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+    sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t
+{
+    volatile size_t xTail;                       /* Index to the next item to read within the buffer. */
+    volatile size_t xHead;                       /* Index to the next item to write within the buffer. */
+    size_t xLength;                              /* The length of the buffer pointed to by pucBuffer. */
+    size_t xTriggerLevelBytes;                   /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+    volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+    volatile TaskHandle_t xTaskWaitingToSend;    /* Holds the handle of a task waiting to send data to a message buffer that is full. */
+    uint8_t * pucBuffer;                         /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+    uint8_t ucFlags;
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */
+    #endif
+
+    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+        StreamBufferCallbackFunction_t pxSendCompletedCallback;    /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */
+        StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete.  sbRECEIVE_COMPLETED is called if this is NULL. */
+    #endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer's data storage area.
+ * This function does not update the buffer's xHead pointer, so multiple writes
+ * may be chained together "atomically". This is useful for Message Buffers where
+ * the length and data bytes are written in two separate chunks, and we don't want
+ * the reader to see the buffer as having grown until after all data is copied over.
+ * This function takes a custom xHead value to indicate where to write to (necessary
+ * for chaining) and returns the the resulting xHead position.
+ * To mark the write as complete, manually set the buffer's xHead field with the
+ * returned xHead from this function.
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                     const uint8_t * pucData,
+                                     size_t xCount,
+                                     size_t xHead ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                        void * pvRxData,
+                                        size_t xBufferLengthBytes,
+                                        size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                       const void * pvTxData,
+                                       size_t xDataLengthBytes,
+                                       size_t xSpace,
+                                       size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies xCount bytes from the pxStreamBuffer's data storage area to pucData.
+ * This function does not update the buffer's xTail pointer, so multiple reads
+ * may be chained together "atomically". This is useful for Message Buffers where
+ * the length and data bytes are read in two separate chunks, and we don't want
+ * the writer to see the buffer as having more free space until after all data is
+ * copied over, especially if we have to abort the read due to insufficient receiving space.
+ * This function takes a custom xTail value to indicate where to read from (necessary
+ * for chaining) and returns the the resulting xTail position.
+ * To mark the read as complete, manually set the buffer's xTail field with the
+ * returned xTail from this function.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                      uint8_t * pucData,
+                                      size_t xCount,
+                                      size_t xTail ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                          uint8_t * const pucBuffer,
+                                          size_t xBufferSizeBytes,
+                                          size_t xTriggerLevelBytes,
+                                          uint8_t ucFlags,
+                                          StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                          StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                     size_t xTriggerLevelBytes,
+                                                     BaseType_t xIsMessageBuffer,
+                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
+    {
+        void * pvAllocatedMemory;
+        uint8_t ucFlags;
+
+        traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
+
+        /* In case the stream buffer is going to be used as a message buffer
+         * (that is, it will hold discrete messages with a little meta data that
+         * says how big the next message is) check the buffer will be large enough
+         * to hold at least one message. */
+        if( xIsMessageBuffer == pdTRUE )
+        {
+            /* Is a message buffer but not statically allocated. */
+            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+        }
+        else
+        {
+            /* Not a message buffer and not statically allocated. */
+            ucFlags = 0;
+            configASSERT( xBufferSizeBytes > 0 );
+        }
+
+        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+        /* A trigger level of 0 would cause a waiting task to unblock even when
+         * the buffer was empty. */
+        if( xTriggerLevelBytes == ( size_t ) 0 )
+        {
+            xTriggerLevelBytes = ( size_t ) 1;
+        }
+
+        /* A stream buffer requires a StreamBuffer_t structure and a buffer.
+         * Both are allocated in a single call to pvPortMalloc().  The
+         * StreamBuffer_t structure is placed at the start of the allocated memory
+         * and the buffer follows immediately after.  The requested size is
+         * incremented so the free space is returned as the user would expect -
+         * this is a quirk of the implementation that means otherwise the free
+         * space would be reported as one byte smaller than would be logically
+         * expected. */
+        if( xBufferSizeBytes < ( xBufferSizeBytes + 1U + sizeof( StreamBuffer_t ) ) )
+        {
+            xBufferSizeBytes++;
+            pvAllocatedMemory = pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) );
+        }
+        else
+        {
+            pvAllocatedMemory = NULL;
+        }
+
+        if( pvAllocatedMemory != NULL )
+        {
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory,                         /* Structure at the start of the allocated memory. */
+                                                                                                          /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+                                                                                                          /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                                                                                                          /* coverity[misra_c_2012_rule_11_5_violation] */
+                                          ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */
+                                          xBufferSizeBytes,
+                                          xTriggerLevelBytes,
+                                          ucFlags,
+                                          pxSendCompletedCallback,
+                                          pxReceiveCompletedCallback );
+
+            traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pvAllocatedMemory ), xIsMessageBuffer );
+        }
+        else
+        {
+            traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+        }
+
+        traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory );
+
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        return ( StreamBufferHandle_t ) pvAllocatedMemory;
+    }
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xIsMessageBuffer,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
+    {
+        /* MISRA Ref 11.3.1 [Misaligned access] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+        /* coverity[misra_c_2012_rule_11_3_violation] */
+        StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer;
+        StreamBufferHandle_t xReturn;
+        uint8_t ucFlags;
+
+        traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
+
+        configASSERT( pucStreamBufferStorageArea );
+        configASSERT( pxStaticStreamBuffer );
+        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+        /* A trigger level of 0 would cause a waiting task to unblock even when
+         * the buffer was empty. */
+        if( xTriggerLevelBytes == ( size_t ) 0 )
+        {
+            xTriggerLevelBytes = ( size_t ) 1;
+        }
+
+        /* In case the stream buffer is going to be used as a message buffer
+         * (that is, it will hold discrete messages with a little meta data that
+         * says how big the next message is) check the buffer will be large enough
+         * to hold at least one message. */
+
+        if( xIsMessageBuffer != pdFALSE )
+        {
+            /* Statically allocated message buffer. */
+            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+        }
+        else
+        {
+            /* Statically allocated stream buffer. */
+            ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+        }
+
+        #if ( configASSERT_DEFINED == 1 )
+        {
+            /* Sanity check that the size of the structure used to declare a
+             * variable of type StaticStreamBuffer_t equals the size of the real
+             * message buffer structure. */
+            volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+            configASSERT( xSize == sizeof( StreamBuffer_t ) );
+        }
+        #endif /* configASSERT_DEFINED */
+
+        if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+        {
+            prvInitialiseNewStreamBuffer( pxStreamBuffer,
+                                          pucStreamBufferStorageArea,
+                                          xBufferSizeBytes,
+                                          xTriggerLevelBytes,
+                                          ucFlags,
+                                          pxSendCompletedCallback,
+                                          pxReceiveCompletedCallback );
+
+            /* Remember this was statically allocated in case it is ever deleted
+             * again. */
+            pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+            traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer;
+        }
+        else
+        {
+            xReturn = NULL;
+            traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+        }
+
+        traceRETURN_xStreamBufferGenericCreateStatic( xReturn );
+
+        return xReturn;
+    }
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
+                                              uint8_t ** ppucStreamBufferStorageArea,
+                                              StaticStreamBuffer_t ** ppxStaticStreamBuffer )
+    {
+        BaseType_t xReturn;
+        StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+        traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer );
+
+        configASSERT( pxStreamBuffer );
+        configASSERT( ppucStreamBufferStorageArea );
+        configASSERT( ppxStaticStreamBuffer );
+
+        if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) != ( uint8_t ) 0 )
+        {
+            *ppucStreamBufferStorageArea = pxStreamBuffer->pucBuffer;
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            *ppxStaticStreamBuffer = ( StaticStreamBuffer_t * ) pxStreamBuffer;
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+
+        traceRETURN_xStreamBufferGetStaticBuffers( xReturn );
+
+        return xReturn;
+    }
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+    traceENTER_vStreamBufferDelete( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+    {
+        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+        {
+            /* Both the structure and the buffer were allocated using a single call
+            * to pvPortMalloc(), hence only one call to vPortFree() is required. */
+            vPortFree( ( void * ) pxStreamBuffer );
+        }
+        #else
+        {
+            /* Should not be possible to get here, ucFlags must be corrupt.
+             * Force an assert. */
+            configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+        }
+        #endif
+    }
+    else
+    {
+        /* The structure and buffer were not allocated dynamically and cannot be
+         * freed - just scrub the structure so future use will assert. */
+        ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+    }
+
+    traceRETURN_vStreamBufferDelete();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn = pdFAIL;
+    StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL;
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxStreamBufferNumber;
+    #endif
+
+    traceENTER_xStreamBufferReset( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+    {
+        /* Store the stream buffer number so it can be restored after the
+         * reset. */
+        uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+    }
+    #endif
+
+    /* Can only reset a message buffer if there are no tasks blocked on it. */
+    taskENTER_CRITICAL();
+    {
+        if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
+        {
+            #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+            {
+                pxSendCallback = pxStreamBuffer->pxSendCompletedCallback;
+                pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback;
+            }
+            #endif
+
+            prvInitialiseNewStreamBuffer( pxStreamBuffer,
+                                          pxStreamBuffer->pucBuffer,
+                                          pxStreamBuffer->xLength,
+                                          pxStreamBuffer->xTriggerLevelBytes,
+                                          pxStreamBuffer->ucFlags,
+                                          pxSendCallback,
+                                          pxReceiveCallback );
+
+            #if ( configUSE_TRACE_FACILITY == 1 )
+            {
+                pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+            }
+            #endif
+
+            traceSTREAM_BUFFER_RESET( xStreamBuffer );
+
+            xReturn = pdPASS;
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    traceRETURN_xStreamBufferReset( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                         size_t xTriggerLevel )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+
+    traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+
+    configASSERT( pxStreamBuffer );
+
+    /* It is not valid for the trigger level to be 0. */
+    if( xTriggerLevel == ( size_t ) 0 )
+    {
+        xTriggerLevel = ( size_t ) 1;
+    }
+
+    /* The trigger level is the number of bytes that must be in the stream
+     * buffer before a task that is waiting for data is unblocked. */
+    if( xTriggerLevel < pxStreamBuffer->xLength )
+    {
+        pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+        xReturn = pdPASS;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    traceRETURN_xStreamBufferSetTriggerLevel( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xSpace;
+    size_t xOriginalTail;
+
+    traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    /* The code below reads xTail and then xHead.  This is safe if the stream
+     * buffer is updated once between the two reads - but not if the stream buffer
+     * is updated more than once between the two reads - hence the loop. */
+    do
+    {
+        xOriginalTail = pxStreamBuffer->xTail;
+        xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+        xSpace -= pxStreamBuffer->xHead;
+    } while( xOriginalTail != pxStreamBuffer->xTail );
+
+    xSpace -= ( size_t ) 1;
+
+    if( xSpace >= pxStreamBuffer->xLength )
+    {
+        xSpace -= pxStreamBuffer->xLength;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceRETURN_xStreamBufferSpacesAvailable( xSpace );
+
+    return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn;
+
+    traceENTER_xStreamBufferBytesAvailable( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    xReturn = prvBytesInBuffer( pxStreamBuffer );
+
+    traceRETURN_xStreamBufferBytesAvailable( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void * pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn, xSpace = 0;
+    size_t xRequiredSpace = xDataLengthBytes;
+    TimeOut_t xTimeOut;
+    size_t xMaxReportedSpace = 0;
+
+    traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+
+    configASSERT( pvTxData );
+    configASSERT( pxStreamBuffer );
+
+    /* The maximum amount of space a stream buffer will ever report is its length
+     * minus 1. */
+    xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1;
+
+    /* This send function is used to write to both message buffers and stream
+     * buffers.  If this is a message buffer then the space needed must be
+     * increased by the amount of bytes needed to store the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+        /* Overflow? */
+        configASSERT( xRequiredSpace > xDataLengthBytes );
+
+        /* If this is a message buffer then it must be possible to write the
+         * whole message. */
+        if( xRequiredSpace > xMaxReportedSpace )
+        {
+            /* The message would not fit even if the entire buffer was empty,
+             * so don't wait for space. */
+            xTicksToWait = ( TickType_t ) 0;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        /* If this is a stream buffer then it is acceptable to write only part
+         * of the message to the buffer.  Cap the length to the total length of
+         * the buffer. */
+        if( xRequiredSpace > xMaxReportedSpace )
+        {
+            xRequiredSpace = xMaxReportedSpace;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        vTaskSetTimeOutState( &xTimeOut );
+
+        do
+        {
+            /* Wait until the required number of bytes are free in the message
+             * buffer. */
+            taskENTER_CRITICAL();
+            {
+                xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+                if( xSpace < xRequiredSpace )
+                {
+                    /* Clear notification state as going to wait for space. */
+                    ( void ) xTaskNotifyStateClear( NULL );
+
+                    /* Should only be one writer. */
+                    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+                    pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+                }
+                else
+                {
+                    taskEXIT_CRITICAL();
+                    break;
+                }
+            }
+            taskEXIT_CRITICAL();
+
+            traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+            pxStreamBuffer->xTaskWaitingToSend = NULL;
+        } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    if( xSpace == ( size_t ) 0 )
+    {
+        xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+    if( xReturn > ( size_t ) 0 )
+    {
+        traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+        /* Was a task waiting for the data? */
+        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+        {
+            prvSEND_COMPLETED( pxStreamBuffer );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+        traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+    }
+
+    traceRETURN_xStreamBufferSend( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void * pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn, xSpace;
+    size_t xRequiredSpace = xDataLengthBytes;
+
+    traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken );
+
+    configASSERT( pvTxData );
+    configASSERT( pxStreamBuffer );
+
+    /* This send function is used to write to both message buffers and stream
+     * buffers.  If this is a message buffer then the space needed must be
+     * increased by the amount of bytes needed to store the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+    if( xReturn > ( size_t ) 0 )
+    {
+        /* Was a task waiting for the data? */
+        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+        {
+            prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+    traceRETURN_xStreamBufferSendFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                       const void * pvTxData,
+                                       size_t xDataLengthBytes,
+                                       size_t xSpace,
+                                       size_t xRequiredSpace )
+{
+    size_t xNextHead = pxStreamBuffer->xHead;
+    configMESSAGE_BUFFER_LENGTH_TYPE xMessageLength;
+
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        /* This is a message buffer, as opposed to a stream buffer. */
+
+        /* Convert xDataLengthBytes to the message length type. */
+        xMessageLength = ( configMESSAGE_BUFFER_LENGTH_TYPE ) xDataLengthBytes;
+
+        /* Ensure the data length given fits within configMESSAGE_BUFFER_LENGTH_TYPE. */
+        configASSERT( ( size_t ) xMessageLength == xDataLengthBytes );
+
+        if( xSpace >= xRequiredSpace )
+        {
+            /* There is enough space to write both the message length and the message
+             * itself into the buffer.  Start by writing the length of the data, the data
+             * itself will be written later in this function. */
+            xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xMessageLength ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead );
+        }
+        else
+        {
+            /* Not enough space, so do not write data to the buffer. */
+            xDataLengthBytes = 0;
+        }
+    }
+    else
+    {
+        /* This is a stream buffer, as opposed to a message buffer, so writing a
+         * stream of bytes rather than discrete messages.  Plan to write as many
+         * bytes as possible. */
+        xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+    }
+
+    if( xDataLengthBytes != ( size_t ) 0 )
+    {
+        /* Write the data to the buffer. */
+        /* MISRA Ref 11.5.5 [Void pointer assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead );
+    }
+
+    return xDataLengthBytes;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void * pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+    traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+
+    configASSERT( pvRxData );
+    configASSERT( pxStreamBuffer );
+
+    /* This receive function is used by both message buffers, which store
+     * discrete messages, and stream buffers, which store a continuous stream of
+     * bytes.  Discrete messages include an additional
+     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        xBytesToStoreMessageLength = 0;
+    }
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        /* Checking if there is data and clearing the notification state must be
+         * performed atomically. */
+        taskENTER_CRITICAL();
+        {
+            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+            /* If this function was invoked by a message buffer read then
+             * xBytesToStoreMessageLength holds the number of bytes used to hold
+             * the length of the next discrete message.  If this function was
+             * invoked by a stream buffer read then xBytesToStoreMessageLength will
+             * be 0. */
+            if( xBytesAvailable <= xBytesToStoreMessageLength )
+            {
+                /* Clear notification state as going to wait for data. */
+                ( void ) xTaskNotifyStateClear( NULL );
+
+                /* Should only be one reader. */
+                configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+                pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        if( xBytesAvailable <= xBytesToStoreMessageLength )
+        {
+            /* Wait for data to be available. */
+            traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+            pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+            /* Recheck the data available after blocking. */
+            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+    }
+
+    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
+     * holds the number of bytes used to store the message length) or a stream of
+     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+     * available must be greater than xBytesToStoreMessageLength to be able to
+     * read bytes from the buffer. */
+    if( xBytesAvailable > xBytesToStoreMessageLength )
+    {
+        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable );
+
+        /* Was a task waiting for space in the buffer? */
+        if( xReceivedLength != ( size_t ) 0 )
+        {
+            traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+            prvRECEIVE_COMPLETED( xStreamBuffer );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceRETURN_xStreamBufferReceive( xReceivedLength );
+
+    return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn, xBytesAvailable;
+    configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+    traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    /* Ensure the stream buffer is being used as a message buffer. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+        if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+        {
+            /* The number of bytes available is greater than the number of bytes
+             * required to hold the length of the next message, so another message
+             * is available. */
+            ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, pxStreamBuffer->xTail );
+            xReturn = ( size_t ) xTempReturn;
+        }
+        else
+        {
+            /* The minimum amount of bytes in a message buffer is
+             * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+             * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+             * value is 0. */
+            configASSERT( xBytesAvailable == 0 );
+            xReturn = 0;
+        }
+    }
+    else
+    {
+        xReturn = 0;
+    }
+
+    traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void * pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+    traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken );
+
+    configASSERT( pvRxData );
+    configASSERT( pxStreamBuffer );
+
+    /* This receive function is used by both message buffers, which store
+     * discrete messages, and stream buffers, which store a continuous stream of
+     * bytes.  Discrete messages include an additional
+     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        xBytesToStoreMessageLength = 0;
+    }
+
+    xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
+     * holds the number of bytes used to store the message length) or a stream of
+     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+     * available must be greater than xBytesToStoreMessageLength to be able to
+     * read bytes from the buffer. */
+    if( xBytesAvailable > xBytesToStoreMessageLength )
+    {
+        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable );
+
+        /* Was a task waiting for space in the buffer? */
+        if( xReceivedLength != ( size_t ) 0 )
+        {
+            prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+    traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength );
+
+    return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                        void * pvRxData,
+                                        size_t xBufferLengthBytes,
+                                        size_t xBytesAvailable )
+{
+    size_t xCount, xNextMessageLength;
+    configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+    size_t xNextTail = pxStreamBuffer->xTail;
+
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        /* A discrete message is being received.  First receive the length
+         * of the message. */
+        xNextTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextTail );
+        xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+        /* Reduce the number of bytes available by the number of bytes just
+         * read out. */
+        xBytesAvailable -= sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+        /* Check there is enough space in the buffer provided by the
+         * user. */
+        if( xNextMessageLength > xBufferLengthBytes )
+        {
+            /* The user has provided insufficient space to read the message. */
+            xNextMessageLength = 0;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        /* A stream of bytes is being received (as opposed to a discrete
+         * message), so read as many bytes as possible. */
+        xNextMessageLength = xBufferLengthBytes;
+    }
+
+    /* Use the minimum of the wanted bytes and the available bytes. */
+    xCount = configMIN( xNextMessageLength, xBytesAvailable );
+
+    if( xCount != ( size_t ) 0 )
+    {
+        /* Read the actual data and update the tail to mark the data as officially consumed. */
+        /* MISRA Ref 11.5.5 [Void pointer assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail );
+    }
+
+    return xCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+    size_t xTail;
+
+    traceENTER_xStreamBufferIsEmpty( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    /* True if no bytes are available. */
+    xTail = pxStreamBuffer->xTail;
+
+    if( pxStreamBuffer->xHead == xTail )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    traceRETURN_xStreamBufferIsEmpty( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+    BaseType_t xReturn;
+    size_t xBytesToStoreMessageLength;
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+    traceENTER_xStreamBufferIsFull( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    /* This generic version of the receive function is used by both message
+     * buffers, which store discrete messages, and stream buffers, which store a
+     * continuous stream of bytes.  Discrete messages include an additional
+     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        xBytesToStoreMessageLength = 0;
+    }
+
+    /* True if the available space equals zero. */
+    if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    traceRETURN_xStreamBufferIsFull( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                              BaseType_t * pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+
+    traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );
+
+    configASSERT( pxStreamBuffer );
+
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+        {
+            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+                                         ( uint32_t ) 0,
+                                         eNoAction,
+                                         pxHigherPriorityTaskWoken );
+            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xStreamBufferSendCompletedFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                 BaseType_t * pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+
+    traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );
+
+    configASSERT( pxStreamBuffer );
+
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+        {
+            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+                                         ( uint32_t ) 0,
+                                         eNoAction,
+                                         pxHigherPriorityTaskWoken );
+            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                     const uint8_t * pucData,
+                                     size_t xCount,
+                                     size_t xHead )
+{
+    size_t xFirstLength;
+
+    configASSERT( xCount > ( size_t ) 0 );
+
+    /* Calculate the number of bytes that can be added in the first write -
+     * which may be less than the total number of bytes that need to be added if
+     * the buffer will wrap back to the beginning. */
+    xFirstLength = configMIN( pxStreamBuffer->xLength - xHead, xCount );
+
+    /* Write as many bytes as can be written in the first write. */
+    configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength );
+    ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength );
+
+    /* If the number of bytes written was less than the number that could be
+     * written in the first write... */
+    if( xCount > xFirstLength )
+    {
+        /* ...then write the remaining bytes to the start of the buffer. */
+        configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+        ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    xHead += xCount;
+
+    if( xHead >= pxStreamBuffer->xLength )
+    {
+        xHead -= pxStreamBuffer->xLength;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    return xHead;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                      uint8_t * pucData,
+                                      size_t xCount,
+                                      size_t xTail )
+{
+    size_t xFirstLength;
+
+    configASSERT( xCount != ( size_t ) 0 );
+
+    /* Calculate the number of bytes that can be read - which may be
+     * less than the number wanted if the data wraps around to the start of
+     * the buffer. */
+    xFirstLength = configMIN( pxStreamBuffer->xLength - xTail, xCount );
+
+    /* Obtain the number of bytes it is possible to obtain in the first
+     * read.  Asserts check bounds of read and write. */
+    configASSERT( xFirstLength <= xCount );
+    configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength );
+    ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength );
+
+    /* If the total number of wanted bytes is greater than the number
+     * that could be read in the first read... */
+    if( xCount > xFirstLength )
+    {
+        /* ...then read the remaining bytes from the start of the buffer. */
+        ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Move the tail pointer to effectively remove the data read from the buffer. */
+    xTail += xCount;
+
+    if( xTail >= pxStreamBuffer->xLength )
+    {
+        xTail -= pxStreamBuffer->xLength;
+    }
+
+    return xTail;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+    size_t xCount;
+
+    xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+    xCount -= pxStreamBuffer->xTail;
+
+    if( xCount >= pxStreamBuffer->xLength )
+    {
+        xCount -= pxStreamBuffer->xLength;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                          uint8_t * const pucBuffer,
+                                          size_t xBufferSizeBytes,
+                                          size_t xTriggerLevelBytes,
+                                          uint8_t ucFlags,
+                                          StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                          StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
+{
+    /* Assert here is deliberately writing to the entire buffer to ensure it can
+     * be written to without generating exceptions, and is setting the buffer to a
+     * known value to assist in development/debugging. */
+    #if ( configASSERT_DEFINED == 1 )
+    {
+        /* The value written just has to be identifiable when looking at the
+         * memory.  Don't use 0xA5 as that is the stack fill value and could
+         * result in confusion as to what is actually being observed. */
+    #define STREAM_BUFFER_BUFFER_WRITE_VALUE    ( 0x55 )
+        configASSERT( memset( pucBuffer, ( int ) STREAM_BUFFER_BUFFER_WRITE_VALUE, xBufferSizeBytes ) == pucBuffer );
+    }
+    #endif
+
+    ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+    pxStreamBuffer->pucBuffer = pucBuffer;
+    pxStreamBuffer->xLength = xBufferSizeBytes;
+    pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+    pxStreamBuffer->ucFlags = ucFlags;
+    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    {
+        pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback;
+        pxStreamBuffer->pxReceiveCompletedCallback = pxReceiveCompletedCallback;
+    }
+    #else
+    {
+        /* MISRA Ref 11.1.1 [Object type casting] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
+        /* coverity[misra_c_2012_rule_11_1_violation] */
+        ( void ) pxSendCompletedCallback;
+
+        /* MISRA Ref 11.1.1 [Object type casting] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
+        /* coverity[misra_c_2012_rule_11_1_violation] */
+        ( void ) pxReceiveCompletedCallback;
+    }
+    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+    {
+        traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer );
+
+        traceRETURN_uxStreamBufferGetStreamBufferNumber( xStreamBuffer->uxStreamBufferNumber );
+
+        return xStreamBuffer->uxStreamBufferNumber;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
+                                             UBaseType_t uxStreamBufferNumber )
+    {
+        traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber );
+
+        xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+
+        traceRETURN_vStreamBufferSetStreamBufferNumber();
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+    {
+        traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer );
+
+        traceRETURN_ucStreamBufferGetStreamBufferType( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
+
+        return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/tasks.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/tasks.c
new file mode 100644
index 0000000000..0a9df2abdd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/tasks.c
@@ -0,0 +1,8699 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+ * functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+
+/* At the bottom of this file are two optional functions that can be used
+ * to generate human readable text from the raw data generated by the
+ * uxTaskGetSystemState() function.  Note the formatting functions are provided
+ * for convenience only, and are NOT considered part of the kernel. */
+    #include <stdio.h>
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if ( configUSE_PREEMPTION == 0 )
+
+/* If the cooperative scheduler is being used then a yield should not be
+ * performed just because a higher priority task has been woken. */
+    #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB )
+    #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB )
+#else
+
+    #if ( configNUMBER_OF_CORES == 1 )
+
+/* This macro requests the running task pxTCB to yield. In single core
+ * scheduler, a running task always runs on core 0 and portYIELD_WITHIN_API()
+ * can be used to request the task running on core 0 to yield. Therefore, pxTCB
+ * is not used in this macro. */
+        #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) \
+    do {                                                         \
+        ( void ) ( pxTCB );                                      \
+        portYIELD_WITHIN_API();                                  \
+    } while( 0 )
+
+        #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) \
+    do {                                                        \
+        if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority )  \
+        {                                                       \
+            portYIELD_WITHIN_API();                             \
+        }                                                       \
+        else                                                    \
+        {                                                       \
+            mtCOVERAGE_TEST_MARKER();                           \
+        }                                                       \
+    } while( 0 )
+
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+/* Yield the core on which this task is running. */
+        #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB )    prvYieldCore( ( pxTCB )->xTaskRunState )
+
+/* Yield for the task if a running task has priority lower than this task. */
+        #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB )     prvYieldForTask( pxTCB )
+
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+#endif /* if ( configUSE_PREEMPTION == 0 ) */
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION              ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */
+#define taskWAITING_NOTIFICATION                  ( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED                 ( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE                        ( 0xa5U )
+
+/* Bits used to record how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB    ( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY        ( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB     ( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+ * value so the high water mark can be determined.  If none of the following are
+ * set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    1
+#else
+    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR      ( 'X' )
+#define tskBLOCKED_CHAR      ( 'B' )
+#define tskREADY_CHAR        ( 'R' )
+#define tskDELETED_CHAR      ( 'D' )
+#define tskSUSPENDED_CHAR    ( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to to
+ * be global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+    #define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+ * configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+    #define configIDLE_TASK_NAME    "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+ * performed in a generic way that is not optimised to any particular
+ * microcontroller architecture. */
+
+/* uxTopReadyPriority holds the priority of the highest priority ready
+ * state task. */
+    #define taskRECORD_READY_PRIORITY( uxPriority ) \
+    do {                                            \
+        if( ( uxPriority ) > uxTopReadyPriority )   \
+        {                                           \
+            uxTopReadyPriority = ( uxPriority );    \
+        }                                           \
+    } while( 0 ) /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define taskSELECT_HIGHEST_PRIORITY_TASK()                            \
+    do {                                                                      \
+        UBaseType_t uxTopPriority = uxTopReadyPriority;                       \
+                                                                              \
+        /* Find the highest priority queue that contains ready tasks. */      \
+        while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \
+        {                                                                     \
+            configASSERT( uxTopPriority );                                    \
+            --uxTopPriority;                                                  \
+        }                                                                     \
+                                                                              \
+        /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
+         * the  same priority get an equal share of the processor time. */                    \
+        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
+        uxTopReadyPriority = uxTopPriority;                                                   \
+    } while( 0 ) /* taskSELECT_HIGHEST_PRIORITY_TASK */
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+        #define taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID )    prvSelectHighestPriorityTask( xCoreID )
+
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
+/*-----------------------------------------------------------*/
+
+/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+ * they are only required when a port optimised method of task selection is
+ * being used. */
+    #define taskRESET_READY_PRIORITY( uxPriority )
+    #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+ * performed in a way that is tailored to the particular microcontroller
+ * architecture being used. */
+
+/* A port optimised version is provided.  Call the port defined macros. */
+    #define taskRECORD_READY_PRIORITY( uxPriority )    portRECORD_READY_PRIORITY( ( uxPriority ), uxTopReadyPriority )
+
+/*-----------------------------------------------------------*/
+
+    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                                  \
+    do {                                                                                        \
+        UBaseType_t uxTopPriority;                                                              \
+                                                                                                \
+        /* Find the highest priority list that contains ready tasks. */                         \
+        portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );                          \
+        configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
+        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );   \
+    } while( 0 )
+
+/*-----------------------------------------------------------*/
+
+/* A port optimised version is provided, call it only if the TCB being reset
+ * is being referenced from a ready list.  If it is referenced from a delayed
+ * or suspended list then it won't be in a ready list. */
+    #define taskRESET_READY_PRIORITY( uxPriority )                                                     \
+    do {                                                                                               \
+        if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \
+        {                                                                                              \
+            portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );                        \
+        }                                                                                              \
+    } while( 0 )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+ * count overflows. */
+#define taskSWITCH_DELAYED_LISTS()                                                \
+    do {                                                                          \
+        List_t * pxTemp;                                                          \
+                                                                                  \
+        /* The delayed tasks list should be empty when the lists are switched. */ \
+        configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );               \
+                                                                                  \
+        pxTemp = pxDelayedTaskList;                                               \
+        pxDelayedTaskList = pxOverflowDelayedTaskList;                            \
+        pxOverflowDelayedTaskList = pxTemp;                                       \
+        xNumOfOverflows++;                                                        \
+        prvResetNextTaskUnblockTime();                                            \
+    } while( 0 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )                                                                     \
+    do {                                                                                                   \
+        traceMOVED_TASK_TO_READY_STATE( pxTCB );                                                           \
+        taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );                                                \
+        listINSERT_END( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+        tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB );                                                      \
+    } while( 0 )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take a TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle )    ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+ * of the task to which it belongs (coded to allow it to be held in reverse
+ * priority order).  However, it is occasionally borrowed for other purposes.  It
+ * is important its value is not updated due to a task priority change while it is
+ * being used for another purpose.  The following bit definition is used to inform
+ * the scheduler that the value should not be changed - in which case it is the
+ * responsibility of whichever module is using the value to ensure it gets set back
+ * to its original value when it is released. */
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint16_t ) 0x8000U )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint32_t ) 0x80000000UL )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint64_t ) 0x8000000000000000ULL )
+#endif
+
+/* Indicates that the task is not actively running on any core. */
+#define taskTASK_NOT_RUNNING           ( ( BaseType_t ) ( -1 ) )
+
+/* Indicates that the task is actively running but scheduled to yield. */
+#define taskTASK_SCHEDULED_TO_YIELD    ( ( BaseType_t ) ( -2 ) )
+
+/* Returns pdTRUE if the task is actively running and not scheduled to yield. */
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskTASK_IS_RUNNING( pxTCB )                          ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
+    #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB )    ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
+#else
+    #define taskTASK_IS_RUNNING( pxTCB )                          ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+    #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB )    ( ( ( pxTCB )->xTaskRunState != taskTASK_NOT_RUNNING ) ? ( pdTRUE ) : ( pdFALSE ) )
+#endif
+
+/* Indicates that the task is an Idle task. */
+#define taskATTRIBUTE_IS_IDLE    ( UBaseType_t ) ( 1UL << 0UL )
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) )
+    #define portGET_CRITICAL_NESTING_COUNT()          ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting )
+    #define portSET_CRITICAL_NESTING_COUNT( x )       ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting = ( x ) )
+    #define portINCREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting++ )
+    #define portDECREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting-- )
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */
+
+#define taskBITS_PER_BYTE    ( ( size_t ) 8 )
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* Yields the given core. This must be called from a critical section and xCoreID
+ * must be valid. This macro is not required in single core since there is only
+ * one core to yield. */
+    #define prvYieldCore( xCoreID )                                                          \
+    do {                                                                                     \
+        if( ( xCoreID ) == ( BaseType_t ) portGET_CORE_ID() )                                \
+        {                                                                                    \
+            /* Pending a yield for this core since it is in the critical section. */         \
+            xYieldPendings[ ( xCoreID ) ] = pdTRUE;                                          \
+        }                                                                                    \
+        else                                                                                 \
+        {                                                                                    \
+            /* Request other core to yield if it is not requested before. */                 \
+            if( pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \
+            {                                                                                \
+                portYIELD_CORE( xCoreID );                                                   \
+                pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD;   \
+            }                                                                                \
+        }                                                                                    \
+    } while( 0 )
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+    volatile StackType_t * pxTopOfStack; /**< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        xMPU_SETTINGS xMPUSettings; /**< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+    #endif
+
+    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+        UBaseType_t uxCoreAffinityMask; /**< Used to link the task to certain cores.  UBaseType_t must have greater than or equal to the number of bits as configNUMBER_OF_CORES. */
+    #endif
+
+    ListItem_t xStateListItem;                  /**< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+    ListItem_t xEventListItem;                  /**< Used to reference a task from an event list. */
+    UBaseType_t uxPriority;                     /**< The priority of the task.  0 is the lowest priority. */
+    StackType_t * pxStack;                      /**< Points to the start of the stack. */
+    #if ( configNUMBER_OF_CORES > 1 )
+        volatile BaseType_t xTaskRunState;      /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */
+        UBaseType_t uxTaskAttributes;           /**< Task's attributes - currently used to identify the idle tasks. */
+    #endif
+    char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created.  Facilitates debugging only. */
+
+    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+        BaseType_t xPreemptionDisable; /**< Used to prevent the task from being preempted. */
+    #endif
+
+    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+        StackType_t * pxEndOfStack; /**< Points to the highest valid address for the stack. */
+    #endif
+
+    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+        UBaseType_t uxCriticalNesting; /**< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+    #endif
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxTCBNumber;  /**< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+        UBaseType_t uxTaskNumber; /**< Stores a number specifically for use by third party trace code. */
+    #endif
+
+    #if ( configUSE_MUTEXES == 1 )
+        UBaseType_t uxBasePriority; /**< The priority last assigned to the task - used by the priority inheritance mechanism. */
+        UBaseType_t uxMutexesHeld;
+    #endif
+
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+        TaskHookFunction_t pxTaskTag;
+    #endif
+
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+        void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+    #endif
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+        configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /**< Stores the amount of time the task has spent in the Running state. */
+    #endif
+
+    #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+        configTLS_BLOCK_TYPE xTLSBlock; /**< Memory block used as Thread Local Storage (TLS) Block for the task. */
+    #endif
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+        volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+        volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+    #endif
+
+    /* See the comments in FreeRTOS.h with the definition of
+     * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+        uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+    #endif
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+        uint8_t ucDelayAborted;
+    #endif
+
+    #if ( configUSE_POSIX_ERRNO == 1 )
+        int iTaskErrno;
+    #endif
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+ * below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+#if ( configNUMBER_OF_CORES == 1 )
+    /* MISRA Ref 8.4.1 [Declaration shall be visible] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+    /* coverity[misra_c_2012_rule_8_4_violation] */
+    portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+#else
+    /* MISRA Ref 8.4.1 [Declaration shall be visible] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+    /* coverity[misra_c_2012_rule_8_4_violation] */
+    portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCBs[ configNUMBER_OF_CORES ];
+    #define pxCurrentTCB    xTaskGetCurrentTaskHandle()
+#endif
+
+/* Lists for ready and blocked tasks. --------------------
+ * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but
+ * doing so breaks some kernel aware debuggers and debuggers that rely on removing
+ * the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /**< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;                         /**< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;                         /**< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;              /**< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;      /**< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;                         /**< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    PRIVILEGED_DATA static List_t xTasksWaitingTermination; /**< Tasks that have been deleted - but their memory not yet freed. */
+    PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    PRIVILEGED_DATA static List_t xSuspendedTaskList; /**< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+ * the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+    int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { pdFALSE };
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandles[ configNUMBER_OF_CORES ];       /**< Holds the handles of the idle tasks.  The idle tasks are created automatically when the scheduler is started. */
+
+/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.
+ * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority
+ * to determine the number of priority lists to read back from the remote target. */
+static const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+ * interrupts must not manipulate the xStateListItem of a TCB, or any of the
+ * lists the xStateListItem can be referenced from, if the scheduler is suspended.
+ * If an interrupt needs to unblock a task while the scheduler is suspended then it
+ * moves the task's event list item into the xPendingReadyList, ready for the
+ * kernel to move the task from the pending ready list into the real ready list
+ * when the scheduler is unsuspended.  The pending ready list itself can only be
+ * accessed from a critical section.
+ *
+ * Updates to uxSchedulerSuspended must be protected by both the task lock and the ISR lock
+ * and must not be done from an ISR. Reads must be protected by either lock and may be done
+ * from either an ISR or a task. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) 0U;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+/* Do not move these variables to function scope as doing so prevents the
+ * code working with debuggers that need to remove the static qualifier. */
+PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime[ configNUMBER_OF_CORES ] = { 0U };    /**< Holds the value of a timer/counter the last time a task was switched in. */
+PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* File private functions. --------------------------------*/
+
+/*
+ * Creates the idle tasks during scheduler start.
+ */
+static BaseType_t prvCreateIdleTasks( void );
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Checks to see if another task moved the current task out of the ready
+ * list while it was waiting to enter a critical section and yields, if so.
+ */
+    static void prvCheckForRunStateChange( void );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Yields a core, or cores if multiple priorities are not allowed to run
+ * simultaneously, to allow the task pxTCB to run.
+ */
+    static void prvYieldForTask( const TCB_t * pxTCB );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Selects the highest priority available task for the given core.
+ */
+    static void prvSelectHighestPriorityTask( BaseType_t xCoreID );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks are also
+ * created to ensure that each core has an idle task to run when no other
+ * task is available to run.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for these functions are:
+ *
+ * void prvIdleTask( void *pvParameters );
+ * void prvPassiveIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+#if ( configNUMBER_OF_CORES > 1 )
+    static portTASK_FUNCTION_PROTO( prvPassiveIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
+                                            const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
+                                                     List_t * pxList,
+                                                     eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                     const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
+
+/*
+ * Helper function used to pad task names with spaces when printing out
+ * human readable tables of task information.
+ */
+    static char * prvWriteNameToBuffer( char * pcBuffer,
+                                        const char * pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName,
+                                  const uint32_t ulStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask,
+                                  TCB_t * pxNewTCB,
+                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * Create a task with static buffer for both TCB and stack. Returns a handle to
+ * the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
+                                        const char * const pcName,
+                                        const uint32_t ulStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer,
+                                        TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+/*
+ * Create a restricted task with static buffer for both TCB and stack. Returns
+ * a handle to the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
+                                                  TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+
+/*
+ * Create a restricted task with static buffer for task stack and allocated buffer
+ * for TCB. Returns a handle to the task if it is created successfully. Otherwise,
+ * returns NULL.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+
+/*
+ * Create a task with allocated buffer for both TCB and stack. Returns a handle to
+ * the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName,
+                                  const configSTACK_DEPTH_TYPE usStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+    static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+#if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
+    extern void vApplicationPassiveIdleHook( void );
+#endif /* #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) */
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+/*
+ * Convert the snprintf return value to the number of characters
+ * written. The following are the possible cases:
+ *
+ * 1. The buffer supplied to snprintf is large enough to hold the
+ *    generated string. The return value in this case is the number
+ *    of characters actually written, not counting the terminating
+ *    null character.
+ * 2. The buffer supplied to snprintf is NOT large enough to hold
+ *    the generated string. The return value in this case is the
+ *    number of characters that would have been written if the
+ *    buffer had been sufficiently large, not counting the
+ *    terminating null character.
+ * 3. Encoding error. The return value in this case is a negative
+ *    number.
+ *
+ * From 1 and 2 above ==> Only when the return value is non-negative
+ * and less than the supplied buffer length, the string has been
+ * completely written.
+ */
+    static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
+                                                        size_t n );
+
+#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static void prvCheckForRunStateChange( void )
+    {
+        UBaseType_t uxPrevCriticalNesting;
+        const TCB_t * pxThisTCB;
+
+        /* This must only be called from within a task. */
+        portASSERT_IF_IN_ISR();
+
+        /* This function is always called with interrupts disabled
+         * so this is safe. */
+        pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ];
+
+        while( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD )
+        {
+            /* We are only here if we just entered a critical section
+            * or if we just suspended the scheduler, and another task
+            * has requested that we yield.
+            *
+            * This is slightly complicated since we need to save and restore
+            * the suspension and critical nesting counts, as well as release
+            * and reacquire the correct locks. And then, do it all over again
+            * if our state changed again during the reacquisition. */
+            uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT();
+
+            if( uxPrevCriticalNesting > 0U )
+            {
+                portSET_CRITICAL_NESTING_COUNT( 0U );
+                portRELEASE_ISR_LOCK();
+            }
+            else
+            {
+                /* The scheduler is suspended. uxSchedulerSuspended is updated
+                 * only when the task is not requested to yield. */
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            portRELEASE_TASK_LOCK();
+            portMEMORY_BARRIER();
+            configASSERT( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD );
+
+            portENABLE_INTERRUPTS();
+
+            /* Enabling interrupts should cause this core to immediately
+             * service the pending interrupt and yield. If the run state is still
+             * yielding here then that is a problem. */
+            configASSERT( pxThisTCB->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD );
+
+            portDISABLE_INTERRUPTS();
+            portGET_TASK_LOCK();
+            portGET_ISR_LOCK();
+
+            portSET_CRITICAL_NESTING_COUNT( uxPrevCriticalNesting );
+
+            if( uxPrevCriticalNesting == 0U )
+            {
+                portRELEASE_ISR_LOCK();
+            }
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static void prvYieldForTask( const TCB_t * pxTCB )
+    {
+        BaseType_t xLowestPriorityToPreempt;
+        BaseType_t xCurrentCoreTaskPriority;
+        BaseType_t xLowestPriorityCore = ( BaseType_t ) -1;
+        BaseType_t xCoreID;
+
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+            BaseType_t xYieldCount = 0;
+        #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+        /* This must be called from a critical section. */
+        configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+
+            /* No task should yield for this one if it is a lower priority
+             * than priority level of currently ready tasks. */
+            if( pxTCB->uxPriority >= uxTopReadyPriority )
+        #else
+            /* Yield is not required for a task which is already running. */
+            if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
+        #endif
+        {
+            xLowestPriorityToPreempt = ( BaseType_t ) pxTCB->uxPriority;
+
+            /* xLowestPriorityToPreempt will be decremented to -1 if the priority of pxTCB
+             * is 0. This is ok as we will give system idle tasks a priority of -1 below. */
+            --xLowestPriorityToPreempt;
+
+            for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+            {
+                xCurrentCoreTaskPriority = ( BaseType_t ) pxCurrentTCBs[ xCoreID ]->uxPriority;
+
+                /* System idle tasks are being assigned a priority of tskIDLE_PRIORITY - 1 here. */
+                if( ( pxCurrentTCBs[ xCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                {
+                    xCurrentCoreTaskPriority = xCurrentCoreTaskPriority - 1;
+                }
+
+                if( ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCoreID ] ) != pdFALSE ) && ( xYieldPendings[ xCoreID ] == pdFALSE ) )
+                {
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                        if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
+                    #endif
+                    {
+                        if( xCurrentCoreTaskPriority <= xLowestPriorityToPreempt )
+                        {
+                            #if ( configUSE_CORE_AFFINITY == 1 )
+                                if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                            #endif
+                            {
+                                #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                                    if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
+                                #endif
+                                {
+                                    xLowestPriorityToPreempt = xCurrentCoreTaskPriority;
+                                    xLowestPriorityCore = xCoreID;
+                                }
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                    {
+                        /* Yield all currently running non-idle tasks with a priority lower than
+                         * the task that needs to run. */
+                        if( ( xCurrentCoreTaskPriority > ( ( BaseType_t ) tskIDLE_PRIORITY - 1 ) ) &&
+                            ( xCurrentCoreTaskPriority < ( BaseType_t ) pxTCB->uxPriority ) )
+                        {
+                            prvYieldCore( xCoreID );
+                            xYieldCount++;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                if( ( xYieldCount == 0 ) && ( xLowestPriorityCore >= 0 ) )
+            #else /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+                if( xLowestPriorityCore >= 0 )
+            #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+            {
+                prvYieldCore( xLowestPriorityCore );
+            }
+
+            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                /* Verify that the calling core always yields to higher priority tasks. */
+                if( ( ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) &&
+                    ( pxTCB->uxPriority > pxCurrentTCBs[ portGET_CORE_ID() ]->uxPriority ) )
+                {
+                    configASSERT( ( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) ||
+                                  ( taskTASK_IS_RUNNING( pxCurrentTCBs[ portGET_CORE_ID() ] ) == pdFALSE ) );
+                }
+            #endif
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static void prvSelectHighestPriorityTask( BaseType_t xCoreID )
+    {
+        UBaseType_t uxCurrentPriority = uxTopReadyPriority;
+        BaseType_t xTaskScheduled = pdFALSE;
+        BaseType_t xDecrementTopPriority = pdTRUE;
+
+        #if ( configUSE_CORE_AFFINITY == 1 )
+            const TCB_t * pxPreviousTCB = NULL;
+        #endif
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+            BaseType_t xPriorityDropped = pdFALSE;
+        #endif
+
+        /* This function should be called when scheduler is running. */
+        configASSERT( xSchedulerRunning == pdTRUE );
+
+        /* A new task is created and a running task with the same priority yields
+         * itself to run the new task. When a running task yields itself, it is still
+         * in the ready list. This running task will be selected before the new task
+         * since the new task is always added to the end of the ready list.
+         * The other problem is that the running task still in the same position of
+         * the ready list when it yields itself. It is possible that it will be selected
+         * earlier then other tasks which waits longer than this task.
+         *
+         * To fix these problems, the running task should be put to the end of the
+         * ready list before searching for the ready task in the ready list. */
+        if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
+                                     &pxCurrentTCBs[ xCoreID ]->xStateListItem ) == pdTRUE )
+        {
+            ( void ) uxListRemove( &pxCurrentTCBs[ xCoreID ]->xStateListItem );
+            vListInsertEnd( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
+                            &pxCurrentTCBs[ xCoreID ]->xStateListItem );
+        }
+
+        while( xTaskScheduled == pdFALSE )
+        {
+            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+            {
+                if( uxCurrentPriority < uxTopReadyPriority )
+                {
+                    /* We can't schedule any tasks, other than idle, that have a
+                     * priority lower than the priority of a task currently running
+                     * on another core. */
+                    uxCurrentPriority = tskIDLE_PRIORITY;
+                }
+            }
+            #endif
+
+            if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxCurrentPriority ] ) ) == pdFALSE )
+            {
+                const List_t * const pxReadyList = &( pxReadyTasksLists[ uxCurrentPriority ] );
+                const ListItem_t * pxEndMarker = listGET_END_MARKER( pxReadyList );
+                ListItem_t * pxIterator;
+
+                /* The ready task list for uxCurrentPriority is not empty, so uxTopReadyPriority
+                 * must not be decremented any further. */
+                xDecrementTopPriority = pdFALSE;
+
+                for( pxIterator = listGET_HEAD_ENTRY( pxReadyList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
+                {
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
+                    TCB_t * pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
+
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                    {
+                        /* When falling back to the idle priority because only one priority
+                         * level is allowed to run at a time, we should ONLY schedule the true
+                         * idle tasks, not user tasks at the idle priority. */
+                        if( uxCurrentPriority < uxTopReadyPriority )
+                        {
+                            if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U )
+                            {
+                                continue;
+                            }
+                        }
+                    }
+                    #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+                    if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+                    {
+                        #if ( configUSE_CORE_AFFINITY == 1 )
+                            if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                        #endif
+                        {
+                            /* If the task is not being executed by any core swap it in. */
+                            pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING;
+                            #if ( configUSE_CORE_AFFINITY == 1 )
+                                pxPreviousTCB = pxCurrentTCBs[ xCoreID ];
+                            #endif
+                            pxTCB->xTaskRunState = xCoreID;
+                            pxCurrentTCBs[ xCoreID ] = pxTCB;
+                            xTaskScheduled = pdTRUE;
+                        }
+                    }
+                    else if( pxTCB == pxCurrentTCBs[ xCoreID ] )
+                    {
+                        configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) );
+
+                        #if ( configUSE_CORE_AFFINITY == 1 )
+                            if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                        #endif
+                        {
+                            /* The task is already running on this core, mark it as scheduled. */
+                            pxTCB->xTaskRunState = xCoreID;
+                            xTaskScheduled = pdTRUE;
+                        }
+                    }
+                    else
+                    {
+                        /* This task is running on the core other than xCoreID. */
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    if( xTaskScheduled != pdFALSE )
+                    {
+                        /* A task has been selected to run on this core. */
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                if( xDecrementTopPriority != pdFALSE )
+                {
+                    uxTopReadyPriority--;
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                    {
+                        xPriorityDropped = pdTRUE;
+                    }
+                    #endif
+                }
+            }
+
+            /* There are configNUMBER_OF_CORES Idle tasks created when scheduler started.
+             * The scheduler should be able to select a task to run when uxCurrentPriority
+             * is tskIDLE_PRIORITY. uxCurrentPriority is never decreased to value blow
+             * tskIDLE_PRIORITY. */
+            if( uxCurrentPriority > tskIDLE_PRIORITY )
+            {
+                uxCurrentPriority--;
+            }
+            else
+            {
+                /* This function is called when idle task is not created. Break the
+                 * loop to prevent uxCurrentPriority overrun. */
+                break;
+            }
+        }
+
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+        {
+            if( xTaskScheduled == pdTRUE )
+            {
+                if( xPriorityDropped != pdFALSE )
+                {
+                    /* There may be several ready tasks that were being prevented from running because there was
+                     * a higher priority task running. Now that the last of the higher priority tasks is no longer
+                     * running, make sure all the other idle tasks yield. */
+                    BaseType_t x;
+
+                    for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configNUMBER_OF_CORES; x++ )
+                    {
+                        if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                        {
+                            prvYieldCore( x );
+                        }
+                    }
+                }
+            }
+        }
+        #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+        #if ( configUSE_CORE_AFFINITY == 1 )
+        {
+            if( xTaskScheduled == pdTRUE )
+            {
+                if( ( pxPreviousTCB != NULL ) && ( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxPreviousTCB->uxPriority ] ), &( pxPreviousTCB->xStateListItem ) ) != pdFALSE ) )
+                {
+                    /* A ready task was just evicted from this core. See if it can be
+                     * scheduled on any other core. */
+                    UBaseType_t uxCoreMap = pxPreviousTCB->uxCoreAffinityMask;
+                    BaseType_t xLowestPriority = ( BaseType_t ) pxPreviousTCB->uxPriority;
+                    BaseType_t xLowestPriorityCore = -1;
+                    BaseType_t x;
+
+                    if( ( pxPreviousTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                    {
+                        xLowestPriority = xLowestPriority - 1;
+                    }
+
+                    if( ( uxCoreMap & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                    {
+                        /* pxPreviousTCB was removed from this core and this core is not excluded
+                         * from it's core affinity mask.
+                         *
+                         * pxPreviousTCB is preempted by the new higher priority task
+                         * pxCurrentTCBs[ xCoreID ]. When searching a new core for pxPreviousTCB,
+                         * we do not need to look at the cores on which pxCurrentTCBs[ xCoreID ]
+                         * is allowed to run. The reason is - when more than one cores are
+                         * eligible for an incoming task, we preempt the core with the minimum
+                         * priority task. Because this core (i.e. xCoreID) was preempted for
+                         * pxCurrentTCBs[ xCoreID ], this means that all the others cores
+                         * where pxCurrentTCBs[ xCoreID ] can run, are running tasks with priority
+                         * no lower than pxPreviousTCB's priority. Therefore, the only cores where
+                         * which can be preempted for pxPreviousTCB are the ones where
+                         * pxCurrentTCBs[ xCoreID ] is not allowed to run (and obviously,
+                         * pxPreviousTCB is allowed to run).
+                         *
+                         * This is an optimization which reduces the number of cores needed to be
+                         * searched for pxPreviousTCB to run. */
+                        uxCoreMap &= ~( pxCurrentTCBs[ xCoreID ]->uxCoreAffinityMask );
+                    }
+                    else
+                    {
+                        /* pxPreviousTCB's core affinity mask is changed and it is no longer
+                         * allowed to run on this core. Searching all the cores in pxPreviousTCB's
+                         * new core affinity mask to find a core on which it can run. */
+                    }
+
+                    uxCoreMap &= ( ( 1U << configNUMBER_OF_CORES ) - 1U );
+
+                    for( x = ( ( BaseType_t ) configNUMBER_OF_CORES - 1 ); x >= ( BaseType_t ) 0; x-- )
+                    {
+                        UBaseType_t uxCore = ( UBaseType_t ) x;
+                        BaseType_t xTaskPriority;
+
+                        if( ( uxCoreMap & ( ( UBaseType_t ) 1U << uxCore ) ) != 0U )
+                        {
+                            xTaskPriority = ( BaseType_t ) pxCurrentTCBs[ uxCore ]->uxPriority;
+
+                            if( ( pxCurrentTCBs[ uxCore ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                            {
+                                xTaskPriority = xTaskPriority - ( BaseType_t ) 1;
+                            }
+
+                            uxCoreMap &= ~( ( UBaseType_t ) 1U << uxCore );
+
+                            if( ( xTaskPriority < xLowestPriority ) &&
+                                ( taskTASK_IS_RUNNING( pxCurrentTCBs[ uxCore ] ) != pdFALSE ) &&
+                                ( xYieldPendings[ uxCore ] == pdFALSE ) )
+                            {
+                                #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                                    if( pxCurrentTCBs[ uxCore ]->xPreemptionDisable == pdFALSE )
+                                #endif
+                                {
+                                    xLowestPriority = xTaskPriority;
+                                    xLowestPriorityCore = ( BaseType_t ) uxCore;
+                                }
+                            }
+                        }
+                    }
+
+                    if( xLowestPriorityCore >= 0 )
+                    {
+                        prvYieldCore( xLowestPriorityCore );
+                    }
+                }
+            }
+        }
+        #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) */
+    }
+
+#endif /* ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
+                                        const char * const pcName,
+                                        const uint32_t ulStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer,
+                                        TaskHandle_t * const pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+
+        configASSERT( puxStackBuffer != NULL );
+        configASSERT( pxTaskBuffer != NULL );
+
+        #if ( configASSERT_DEFINED == 1 )
+        {
+            /* Sanity check that the size of the structure used to declare a
+             * variable of type StaticTask_t equals the size of the real task
+             * structure. */
+            volatile size_t xSize = sizeof( StaticTask_t );
+            configASSERT( xSize == sizeof( TCB_t ) );
+            ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not used. */
+        }
+        #endif /* configASSERT_DEFINED */
+
+        if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+        {
+            /* The memory used for the task's TCB and stack are passed into this
+             * function - use them. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            pxNewTCB = ( TCB_t * ) pxTaskBuffer;
+            ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+            pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+            {
+                /* Tasks can be created statically or dynamically, so note this
+                 * task was created statically in case the task is later deleted. */
+                pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+            }
+            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+            prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+        }
+        else
+        {
+            pxNewTCB = NULL;
+        }
+
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName,
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer )
+    {
+        TaskHandle_t xReturn = NULL;
+        TCB_t * pxNewTCB;
+
+        traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+
+        pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+
+        if( pxNewTCB != NULL )
+        {
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+            }
+            #endif
+
+            prvAddNewTaskToReadyList( pxNewTCB );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xTaskCreateStatic( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
+                                                   const char * const pcName,
+                                                   const uint32_t ulStackDepth,
+                                                   void * const pvParameters,
+                                                   UBaseType_t uxPriority,
+                                                   StackType_t * const puxStackBuffer,
+                                                   StaticTask_t * const pxTaskBuffer,
+                                                   UBaseType_t uxCoreAffinityMask )
+        {
+            TaskHandle_t xReturn = NULL;
+            TCB_t * pxNewTCB;
+
+            traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask );
+
+            pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            traceRETURN_xTaskCreateStaticAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
+                                                  TaskHandle_t * const pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+
+        configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+        configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+        if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+        {
+            /* Allocate space for the TCB.  Where the memory comes from depends
+             * on the implementation of the port malloc function and whether or
+             * not static allocation is being used. */
+            pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+            ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+
+            /* Store the stack location in the TCB. */
+            pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+            {
+                /* Tasks can be created statically or dynamically, so note this
+                 * task was created statically in case the task is later deleted. */
+                pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+            }
+            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+            prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
+                                  pxTaskDefinition->pcName,
+                                  ( uint32_t ) pxTaskDefinition->usStackDepth,
+                                  pxTaskDefinition->pvParameters,
+                                  pxTaskDefinition->uxPriority,
+                                  pxCreatedTask, pxNewTCB,
+                                  pxTaskDefinition->xRegions );
+        }
+        else
+        {
+            pxNewTCB = NULL;
+        }
+
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
+
+        configASSERT( pxTaskDefinition != NULL );
+
+        pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );
+
+        if( pxNewTCB != NULL )
+        {
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+            }
+            #endif
+
+            prvAddNewTaskToReadyList( pxNewTCB );
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
+
+        traceRETURN_xTaskCreateRestrictedStatic( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                           UBaseType_t uxCoreAffinityMask,
+                                                           TaskHandle_t * pxCreatedTask )
+        {
+            TCB_t * pxNewTCB;
+            BaseType_t xReturn;
+
+            traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );
+
+            configASSERT( pxTaskDefinition != NULL );
+
+            pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+            }
+
+            traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * const pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+
+        configASSERT( pxTaskDefinition->puxStackBuffer );
+
+        if( pxTaskDefinition->puxStackBuffer != NULL )
+        {
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+            if( pxNewTCB != NULL )
+            {
+                ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+
+                /* Store the stack location in the TCB. */
+                pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+                #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+                {
+                    /* Tasks can be created statically or dynamically, so note
+                     * this task had a statically allocated stack in case it is
+                     * later deleted.  The TCB was allocated dynamically. */
+                    pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+                }
+                #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+                prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
+                                      pxTaskDefinition->pcName,
+                                      ( uint32_t ) pxTaskDefinition->usStackDepth,
+                                      pxTaskDefinition->pvParameters,
+                                      pxTaskDefinition->uxPriority,
+                                      pxCreatedTask, pxNewTCB,
+                                      pxTaskDefinition->xRegions );
+            }
+        }
+        else
+        {
+            pxNewTCB = NULL;
+        }
+
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
+                                      TaskHandle_t * pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
+
+        pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );
+
+        if( pxNewTCB != NULL )
+        {
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+            }
+            #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+            prvAddNewTaskToReadyList( pxNewTCB );
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
+
+        traceRETURN_xTaskCreateRestricted( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                     UBaseType_t uxCoreAffinityMask,
+                                                     TaskHandle_t * pxCreatedTask )
+        {
+            TCB_t * pxNewTCB;
+            BaseType_t xReturn;
+
+            traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );
+
+            pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+            }
+
+            traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName,
+                                  const configSTACK_DEPTH_TYPE usStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+
+        /* If the stack grows down then allocate the stack then the TCB so the stack
+         * does not grow into the TCB.  Likewise if the stack grows up then allocate
+         * the TCB then the stack. */
+        #if ( portSTACK_GROWTH > 0 )
+        {
+            /* Allocate space for the TCB.  Where the memory comes from depends on
+             * the implementation of the port malloc function and whether or not static
+             * allocation is being used. */
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+            if( pxNewTCB != NULL )
+            {
+                ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+
+                /* Allocate space for the stack used by the task being created.
+                 * The base of the stack memory stored in the TCB so the task can
+                 * be deleted later if required. */
+                /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) );
+
+                if( pxNewTCB->pxStack == NULL )
+                {
+                    /* Could not allocate the stack.  Delete the allocated TCB. */
+                    vPortFree( pxNewTCB );
+                    pxNewTCB = NULL;
+                }
+            }
+        }
+        #else /* portSTACK_GROWTH */
+        {
+            StackType_t * pxStack;
+
+            /* Allocate space for the stack used by the task being created. */
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) );
+
+            if( pxStack != NULL )
+            {
+                /* Allocate space for the TCB. */
+                /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+                if( pxNewTCB != NULL )
+                {
+                    ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+
+                    /* Store the stack location in the TCB. */
+                    pxNewTCB->pxStack = pxStack;
+                }
+                else
+                {
+                    /* The stack cannot be used as the TCB was not created.  Free
+                     * it again. */
+                    vPortFreeStack( pxStack );
+                }
+            }
+            else
+            {
+                pxNewTCB = NULL;
+            }
+        }
+        #endif /* portSTACK_GROWTH */
+
+        if( pxNewTCB != NULL )
+        {
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+            {
+                /* Tasks can be created statically or dynamically, so note this
+                 * task was created dynamically in case it is later deleted. */
+                pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+            }
+            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+            prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+        }
+
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName,
+                            const configSTACK_DEPTH_TYPE usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+        pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+        if( pxNewTCB != NULL )
+        {
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+            }
+            #endif
+
+            prvAddNewTaskToReadyList( pxNewTCB );
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
+
+        traceRETURN_xTaskCreate( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
+                                           const char * const pcName,
+                                           const configSTACK_DEPTH_TYPE usStackDepth,
+                                           void * const pvParameters,
+                                           UBaseType_t uxPriority,
+                                           UBaseType_t uxCoreAffinityMask,
+                                           TaskHandle_t * const pxCreatedTask )
+        {
+            TCB_t * pxNewTCB;
+            BaseType_t xReturn;
+
+            traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask );
+
+            pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+            }
+
+            traceRETURN_xTaskCreateAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName,
+                                  const uint32_t ulStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask,
+                                  TCB_t * pxNewTCB,
+                                  const MemoryRegion_t * const xRegions )
+{
+    StackType_t * pxTopOfStack;
+    UBaseType_t x;
+
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        /* Should the task be created in privileged mode? */
+        BaseType_t xRunPrivileged;
+
+        if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+        {
+            xRunPrivileged = pdTRUE;
+        }
+        else
+        {
+            xRunPrivileged = pdFALSE;
+        }
+        uxPriority &= ~portPRIVILEGE_BIT;
+    #endif /* portUSING_MPU_WRAPPERS == 1 */
+
+    /* Avoid dependency on memset() if it is not required. */
+    #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+    {
+        /* Fill the stack with a known value to assist debugging. */
+        ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+    }
+    #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+    /* Calculate the top of stack address.  This depends on whether the stack
+     * grows from high memory to low (as per the 80x86) or vice versa.
+     * portSTACK_GROWTH is used to make the result positive or negative as required
+     * by the port. */
+    #if ( portSTACK_GROWTH < 0 )
+    {
+        pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+        pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+
+        /* Check the alignment of the calculated top of stack is correct. */
+        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+        #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
+        {
+            /* Also record the stack's high address, which may assist
+             * debugging. */
+            pxNewTCB->pxEndOfStack = pxTopOfStack;
+        }
+        #endif /* configRECORD_STACK_HIGH_ADDRESS */
+    }
+    #else /* portSTACK_GROWTH */
+    {
+        pxTopOfStack = pxNewTCB->pxStack;
+        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+
+        /* Check the alignment of the calculated top of stack is correct. */
+        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+        /* The other extreme of the stack space is required if stack checking is
+         * performed. */
+        pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+    }
+    #endif /* portSTACK_GROWTH */
+
+    /* Store the task name in the TCB. */
+    if( pcName != NULL )
+    {
+        for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+        {
+            pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+            /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+             * configMAX_TASK_NAME_LEN characters just in case the memory after the
+             * string is not accessible (extremely unlikely). */
+            if( pcName[ x ] == ( char ) 0x00 )
+            {
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        /* Ensure the name string is terminated in the case that the string length
+         * was greater or equal to configMAX_TASK_NAME_LEN. */
+        pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1U ] = '\0';
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* This is used as an array index so must ensure it's not too large. */
+    configASSERT( uxPriority < configMAX_PRIORITIES );
+
+    if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+    {
+        uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    pxNewTCB->uxPriority = uxPriority;
+    #if ( configUSE_MUTEXES == 1 )
+    {
+        pxNewTCB->uxBasePriority = uxPriority;
+    }
+    #endif /* configUSE_MUTEXES */
+
+    vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+    vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+    /* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+     * back to  the containing TCB from a generic item in a list. */
+    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+    /* Event lists are always in priority order. */
+    listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority );
+    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+    {
+        vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+    }
+    #else
+    {
+        /* Avoid compiler warning about unreferenced parameter. */
+        ( void ) xRegions;
+    }
+    #endif
+
+    #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+    {
+        /* Allocate and initialize memory for the task's TLS Block. */
+        configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock, pxTopOfStack );
+    }
+    #endif
+
+    /* Initialize the TCB stack to look as if the task was already running,
+     * but had been interrupted by the scheduler.  The return address is set
+     * to the start of the task function. Once the stack has been initialised
+     * the top of stack variable is updated. */
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+    {
+        /* If the port has capability to detect stack overflow,
+         * pass the stack end address to the stack initialization
+         * function as well. */
+        #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        {
+            #if ( portSTACK_GROWTH < 0 )
+            {
+                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) );
+            }
+            #else /* portSTACK_GROWTH */
+            {
+                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) );
+            }
+            #endif /* portSTACK_GROWTH */
+        }
+        #else /* portHAS_STACK_OVERFLOW_CHECKING */
+        {
+            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) );
+        }
+        #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+    }
+    #else /* portUSING_MPU_WRAPPERS */
+    {
+        /* If the port has capability to detect stack overflow,
+         * pass the stack end address to the stack initialization
+         * function as well. */
+        #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        {
+            #if ( portSTACK_GROWTH < 0 )
+            {
+                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+            }
+            #else /* portSTACK_GROWTH */
+            {
+                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+            }
+            #endif /* portSTACK_GROWTH */
+        }
+        #else /* portHAS_STACK_OVERFLOW_CHECKING */
+        {
+            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+        }
+        #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+    }
+    #endif /* portUSING_MPU_WRAPPERS */
+
+    /* Initialize task state and task attributes. */
+    #if ( configNUMBER_OF_CORES > 1 )
+    {
+        pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING;
+
+        /* Is this an idle task? */
+        if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvIdleTask ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvPassiveIdleTask ) )
+        {
+            pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE;
+        }
+    }
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+    if( pxCreatedTask != NULL )
+    {
+        /* Pass the handle out in an anonymous way.  The handle can be used to
+         * change the created task's priority, delete the created task, etc.*/
+        *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES == 1 )
+
+    static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
+    {
+        /* Ensure interrupts don't access the task lists while the lists are being
+         * updated. */
+        taskENTER_CRITICAL();
+        {
+            uxCurrentNumberOfTasks++;
+
+            if( pxCurrentTCB == NULL )
+            {
+                /* There are no other tasks, or all the other tasks are in
+                 * the suspended state - make this the current task. */
+                pxCurrentTCB = pxNewTCB;
+
+                if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+                {
+                    /* This is the first task to be created so do the preliminary
+                     * initialisation required.  We will not recover if this call
+                     * fails, but we will report the failure. */
+                    prvInitialiseTaskLists();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* If the scheduler is not already running, make this task the
+                 * current task if it is the highest priority task to be created
+                 * so far. */
+                if( xSchedulerRunning == pdFALSE )
+                {
+                    if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+                    {
+                        pxCurrentTCB = pxNewTCB;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            uxTaskNumber++;
+
+            #if ( configUSE_TRACE_FACILITY == 1 )
+            {
+                /* Add a counter into the TCB for tracing only. */
+                pxNewTCB->uxTCBNumber = uxTaskNumber;
+            }
+            #endif /* configUSE_TRACE_FACILITY */
+            traceTASK_CREATE( pxNewTCB );
+
+            prvAddTaskToReadyList( pxNewTCB );
+
+            portSETUP_TCB( pxNewTCB );
+        }
+        taskEXIT_CRITICAL();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* If the created task is of a higher priority than the current task
+             * then it should run now. */
+            taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
+    {
+        /* Ensure interrupts don't access the task lists while the lists are being
+         * updated. */
+        taskENTER_CRITICAL();
+        {
+            uxCurrentNumberOfTasks++;
+
+            if( xSchedulerRunning == pdFALSE )
+            {
+                if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+                {
+                    /* This is the first task to be created so do the preliminary
+                     * initialisation required.  We will not recover if this call
+                     * fails, but we will report the failure. */
+                    prvInitialiseTaskLists();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                if( ( pxNewTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                {
+                    BaseType_t xCoreID;
+
+                    /* Check if a core is free. */
+                    for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+                    {
+                        if( pxCurrentTCBs[ xCoreID ] == NULL )
+                        {
+                            pxNewTCB->xTaskRunState = xCoreID;
+                            pxCurrentTCBs[ xCoreID ] = pxNewTCB;
+                            break;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            uxTaskNumber++;
+
+            #if ( configUSE_TRACE_FACILITY == 1 )
+            {
+                /* Add a counter into the TCB for tracing only. */
+                pxNewTCB->uxTCBNumber = uxTaskNumber;
+            }
+            #endif /* configUSE_TRACE_FACILITY */
+            traceTASK_CREATE( pxNewTCB );
+
+            prvAddTaskToReadyList( pxNewTCB );
+
+            portSETUP_TCB( pxNewTCB );
+
+            if( xSchedulerRunning != pdFALSE )
+            {
+                /* If the created task is of a higher priority than another
+                 * currently running task and preemption is on then it should
+                 * run now. */
+                taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+    static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
+                                                        size_t n )
+    {
+        size_t uxCharsWritten;
+
+        if( iSnprintfReturnValue < 0 )
+        {
+            /* Encoding error - Return 0 to indicate that nothing
+             * was written to the buffer. */
+            uxCharsWritten = 0;
+        }
+        else if( iSnprintfReturnValue >= ( int ) n )
+        {
+            /* This is the case when the supplied buffer is not
+             * large to hold the generated string. Return the
+             * number of characters actually written without
+             * counting the terminating NULL character. */
+            uxCharsWritten = n - 1U;
+        }
+        else
+        {
+            /* Complete string was written to the buffer. */
+            uxCharsWritten = ( size_t ) iSnprintfReturnValue;
+        }
+
+        return uxCharsWritten;
+    }
+
+#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    void vTaskDelete( TaskHandle_t xTaskToDelete )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_vTaskDelete( xTaskToDelete );
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the calling task that is
+             * being deleted. */
+            pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+            /* Remove task from the ready/delayed list. */
+            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+            {
+                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Is the task waiting on an event also? */
+            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+            {
+                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Increment the uxTaskNumber also so kernel aware debuggers can
+             * detect that the task lists need re-generating.  This is done before
+             * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+             * not return. */
+            uxTaskNumber++;
+
+            /* If the task is running (or yielding), we must add it to the
+             * termination list so that an idle task can delete it when it is
+             * no longer running. */
+            if( taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) != pdFALSE )
+            {
+                /* A running task or a task which is scheduled to yield is being
+                 * deleted. This cannot complete when the task is still running
+                 * on a core, as a context switch to another task is required.
+                 * Place the task in the termination list. The idle task will check
+                 * the termination list and free up any memory allocated by the
+                 * scheduler for the TCB and stack of the deleted task. */
+                vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+                /* Increment the ucTasksDeleted variable so the idle task knows
+                 * there is a task that has been deleted and that it should therefore
+                 * check the xTasksWaitingTermination list. */
+                ++uxDeletedTasksWaitingCleanUp;
+
+                /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+                 * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+                traceTASK_DELETE( pxTCB );
+
+                /* The pre-delete hook is primarily for the Windows simulator,
+                 * in which Windows specific clean up operations are performed,
+                 * after which it is not possible to yield away from this task -
+                 * hence xYieldPending is used to latch that a context switch is
+                 * required. */
+                #if ( configNUMBER_OF_CORES == 1 )
+                    portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ 0 ] ) );
+                #else
+                    portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ pxTCB->xTaskRunState ] ) );
+                #endif
+            }
+            else
+            {
+                --uxCurrentNumberOfTasks;
+                traceTASK_DELETE( pxTCB );
+
+                /* Reset the next expected unblock time in case it referred to
+                 * the task that has just been deleted. */
+                prvResetNextTaskUnblockTime();
+            }
+        }
+
+        #if ( configNUMBER_OF_CORES == 1 )
+        {
+            taskEXIT_CRITICAL();
+
+            /* If the task is not deleting itself, call prvDeleteTCB from outside of
+             * critical section. If a task deletes itself, prvDeleteTCB is called
+             * from prvCheckTasksWaitingTermination which is called from Idle task. */
+            if( pxTCB != pxCurrentTCB )
+            {
+                prvDeleteTCB( pxTCB );
+            }
+
+            /* Force a reschedule if it is the currently running task that has just
+             * been deleted. */
+            if( xSchedulerRunning != pdFALSE )
+            {
+                if( pxTCB == pxCurrentTCB )
+                {
+                    configASSERT( uxSchedulerSuspended == 0 );
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+        {
+            /* If a running task is not deleting itself, call prvDeleteTCB. If a running
+             * task deletes itself, prvDeleteTCB is called from prvCheckTasksWaitingTermination
+             * which is called from Idle task. */
+            if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+            {
+                prvDeleteTCB( pxTCB );
+            }
+
+            /* Force a reschedule if the task that has just been deleted was running. */
+            if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) )
+            {
+                if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+                {
+                    configASSERT( uxSchedulerSuspended == 0 );
+                    vTaskYieldWithinAPI();
+                }
+                else
+                {
+                    prvYieldCore( pxTCB->xTaskRunState );
+                }
+            }
+
+            taskEXIT_CRITICAL();
+        }
+        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+        traceRETURN_vTaskDelete();
+    }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskDelayUntil == 1 )
+
+    BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                const TickType_t xTimeIncrement )
+    {
+        TickType_t xTimeToWake;
+        BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+        traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+
+        configASSERT( pxPreviousWakeTime );
+        configASSERT( ( xTimeIncrement > 0U ) );
+
+        vTaskSuspendAll();
+        {
+            /* Minor optimisation.  The tick count cannot change in this
+             * block. */
+            const TickType_t xConstTickCount = xTickCount;
+
+            configASSERT( uxSchedulerSuspended == 1U );
+
+            /* Generate the tick time at which the task wants to wake. */
+            xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+            if( xConstTickCount < *pxPreviousWakeTime )
+            {
+                /* The tick count has overflowed since this function was
+                 * lasted called.  In this case the only time we should ever
+                 * actually delay is if the wake time has also  overflowed,
+                 * and the wake time is greater than the tick time.  When this
+                 * is the case it is as if neither time had overflowed. */
+                if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+                {
+                    xShouldDelay = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* The tick time has not overflowed.  In this case we will
+                 * delay if either the wake time has overflowed, and/or the
+                 * tick time is less than the wake time. */
+                if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+                {
+                    xShouldDelay = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            /* Update the wake time ready for the next call. */
+            *pxPreviousWakeTime = xTimeToWake;
+
+            if( xShouldDelay != pdFALSE )
+            {
+                traceTASK_DELAY_UNTIL( xTimeToWake );
+
+                /* prvAddCurrentTaskToDelayedList() needs the block time, not
+                 * the time to wake, so subtract the current tick count. */
+                prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        xAlreadyYielded = xTaskResumeAll();
+
+        /* Force a reschedule if xTaskResumeAll has not already done so, we may
+         * have put ourselves to sleep. */
+        if( xAlreadyYielded == pdFALSE )
+        {
+            taskYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xTaskDelayUntil( xShouldDelay );
+
+        return xShouldDelay;
+    }
+
+#endif /* INCLUDE_xTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+    void vTaskDelay( const TickType_t xTicksToDelay )
+    {
+        BaseType_t xAlreadyYielded = pdFALSE;
+
+        traceENTER_vTaskDelay( xTicksToDelay );
+
+        /* A delay time of zero just forces a reschedule. */
+        if( xTicksToDelay > ( TickType_t ) 0U )
+        {
+            vTaskSuspendAll();
+            {
+                configASSERT( uxSchedulerSuspended == 1U );
+
+                traceTASK_DELAY();
+
+                /* A task that is removed from the event list while the
+                 * scheduler is suspended will not get placed in the ready
+                 * list or removed from the blocked list until the scheduler
+                 * is resumed.
+                 *
+                 * This task cannot be in an event list as it is the currently
+                 * executing task. */
+                prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+            }
+            xAlreadyYielded = xTaskResumeAll();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* Force a reschedule if xTaskResumeAll has not already done so, we may
+         * have put ourselves to sleep. */
+        if( xAlreadyYielded == pdFALSE )
+        {
+            taskYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskDelay();
+    }
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+    eTaskState eTaskGetState( TaskHandle_t xTask )
+    {
+        eTaskState eReturn;
+        List_t const * pxStateList;
+        List_t const * pxEventList;
+        List_t const * pxDelayedList;
+        List_t const * pxOverflowedDelayedList;
+        const TCB_t * const pxTCB = xTask;
+
+        traceENTER_eTaskGetState( xTask );
+
+        configASSERT( pxTCB );
+
+        #if ( configNUMBER_OF_CORES == 1 )
+            if( pxTCB == pxCurrentTCB )
+            {
+                /* The task calling this function is querying its own state. */
+                eReturn = eRunning;
+            }
+            else
+        #endif
+        {
+            taskENTER_CRITICAL();
+            {
+                pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+                pxEventList = listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) );
+                pxDelayedList = pxDelayedTaskList;
+                pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+            }
+            taskEXIT_CRITICAL();
+
+            if( pxEventList == &xPendingReadyList )
+            {
+                /* The task has been placed on the pending ready list, so its
+                 * state is eReady regardless of what list the task's state list
+                 * item is currently placed on. */
+                eReturn = eReady;
+            }
+            else if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+            {
+                /* The task being queried is referenced from one of the Blocked
+                 * lists. */
+                eReturn = eBlocked;
+            }
+
+            #if ( INCLUDE_vTaskSuspend == 1 )
+                else if( pxStateList == &xSuspendedTaskList )
+                {
+                    /* The task being queried is referenced from the suspended
+                     * list.  Is it genuinely suspended or is it blocked
+                     * indefinitely? */
+                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+                    {
+                        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+                        {
+                            BaseType_t x;
+
+                            /* The task does not appear on the event list item of
+                             * and of the RTOS objects, but could still be in the
+                             * blocked state if it is waiting on its notification
+                             * rather than waiting on an object.  If not, is
+                             * suspended. */
+                            eReturn = eSuspended;
+
+                            for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                            {
+                                if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                                {
+                                    eReturn = eBlocked;
+                                    break;
+                                }
+                            }
+                        }
+                        #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+                        {
+                            eReturn = eSuspended;
+                        }
+                        #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+                    }
+                    else
+                    {
+                        eReturn = eBlocked;
+                    }
+                }
+            #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+
+            #if ( INCLUDE_vTaskDelete == 1 )
+                else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+                {
+                    /* The task being queried is referenced from the deleted
+                     * tasks list, or it is not referenced from any lists at
+                     * all. */
+                    eReturn = eDeleted;
+                }
+            #endif
+
+            else
+            {
+                #if ( configNUMBER_OF_CORES == 1 )
+                {
+                    /* If the task is not in any other state, it must be in the
+                     * Ready (including pending ready) state. */
+                    eReturn = eReady;
+                }
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                {
+                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                    {
+                        /* Is it actively running on a core? */
+                        eReturn = eRunning;
+                    }
+                    else
+                    {
+                        /* If the task is not in any other state, it must be in the
+                         * Ready (including pending ready) state. */
+                        eReturn = eReady;
+                    }
+                }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+            }
+        }
+
+        traceRETURN_eTaskGetState( eReturn );
+
+        return eReturn;
+    }
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn;
+
+        traceENTER_uxTaskPriorityGet( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the priority of the task
+             * that called uxTaskPriorityGet() that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxPriority;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_uxTaskPriorityGet( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn;
+        UBaseType_t uxSavedInterruptStatus;
+
+        traceENTER_uxTaskPriorityGetFromISR( xTask );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            /* If null is passed in here then it is the priority of the calling
+             * task that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxPriority;
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_uxTaskPriorityGetFromISR( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+    UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn;
+
+        traceENTER_uxTaskBasePriorityGet( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the base priority of the task
+             * that called uxTaskBasePriorityGet() that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxBasePriority;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_uxTaskBasePriorityGet( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+    UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn;
+        UBaseType_t uxSavedInterruptStatus;
+
+        traceENTER_uxTaskBasePriorityGetFromISR( xTask );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            /* If null is passed in here then it is the base priority of the calling
+             * task that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxBasePriority;
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+    void vTaskPrioritySet( TaskHandle_t xTask,
+                           UBaseType_t uxNewPriority )
+    {
+        TCB_t * pxTCB;
+        UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+        BaseType_t xYieldRequired = pdFALSE;
+
+        #if ( configNUMBER_OF_CORES > 1 )
+            BaseType_t xYieldForTask = pdFALSE;
+        #endif
+
+        traceENTER_vTaskPrioritySet( xTask, uxNewPriority );
+
+        configASSERT( uxNewPriority < configMAX_PRIORITIES );
+
+        /* Ensure the new priority is valid. */
+        if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+        {
+            uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the priority of the calling
+             * task that is being changed. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+            #if ( configUSE_MUTEXES == 1 )
+            {
+                uxCurrentBasePriority = pxTCB->uxBasePriority;
+            }
+            #else
+            {
+                uxCurrentBasePriority = pxTCB->uxPriority;
+            }
+            #endif
+
+            if( uxCurrentBasePriority != uxNewPriority )
+            {
+                /* The priority change may have readied a task of higher
+                 * priority than a running task. */
+                if( uxNewPriority > uxCurrentBasePriority )
+                {
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        if( pxTCB != pxCurrentTCB )
+                        {
+                            /* The priority of a task other than the currently
+                             * running task is being raised.  Is the priority being
+                             * raised above that of the running task? */
+                            if( uxNewPriority > pxCurrentTCB->uxPriority )
+                            {
+                                xYieldRequired = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            /* The priority of the running task is being raised,
+                             * but the running task must already be the highest
+                             * priority task able to run so no yield is required. */
+                        }
+                    }
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    {
+                        /* The priority of a task is being raised so
+                         * perform a yield for this task later. */
+                        xYieldForTask = pdTRUE;
+                    }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                }
+                else if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                {
+                    /* Setting the priority of a running task down means
+                     * there may now be another task of higher priority that
+                     * is ready to execute. */
+                    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                        if( pxTCB->xPreemptionDisable == pdFALSE )
+                    #endif
+                    {
+                        xYieldRequired = pdTRUE;
+                    }
+                }
+                else
+                {
+                    /* Setting the priority of any other task down does not
+                     * require a yield as the running task must be above the
+                     * new priority of the task being modified. */
+                }
+
+                /* Remember the ready list the task might be referenced from
+                 * before its uxPriority member is changed so the
+                 * taskRESET_READY_PRIORITY() macro can function correctly. */
+                uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+                #if ( configUSE_MUTEXES == 1 )
+                {
+                    /* Only change the priority being used if the task is not
+                     * currently using an inherited priority or the new priority
+                     * is bigger than the inherited priority. */
+                    if( ( pxTCB->uxBasePriority == pxTCB->uxPriority ) || ( uxNewPriority > pxTCB->uxPriority ) )
+                    {
+                        pxTCB->uxPriority = uxNewPriority;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* The base priority gets set whatever. */
+                    pxTCB->uxBasePriority = uxNewPriority;
+                }
+                #else /* if ( configUSE_MUTEXES == 1 ) */
+                {
+                    pxTCB->uxPriority = uxNewPriority;
+                }
+                #endif /* if ( configUSE_MUTEXES == 1 ) */
+
+                /* Only reset the event list item value if the value is not
+                 * being used for anything else. */
+                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
+                {
+                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* If the task is in the blocked or suspended list we need do
+                 * nothing more than change its priority variable. However, if
+                 * the task is in a ready list it needs to be removed and placed
+                 * in the list appropriate to its new priority. */
+                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+                {
+                    /* The task is currently in its ready list - remove before
+                     * adding it to its new ready list.  As we are in a critical
+                     * section we can do this even if the scheduler is suspended. */
+                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                    {
+                        /* It is known that the task is in its ready list so
+                         * there is no need to check again and the port level
+                         * reset macro can be called directly. */
+                        portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                    #else
+                    {
+                        /* It's possible that xYieldForTask was already set to pdTRUE because
+                         * its priority is being raised. However, since it is not in a ready list
+                         * we don't actually need to yield for it. */
+                        xYieldForTask = pdFALSE;
+                    }
+                    #endif
+                }
+
+                if( xYieldRequired != pdFALSE )
+                {
+                    /* The running task priority is set down. Request the task to yield. */
+                    taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB );
+                }
+                else
+                {
+                    #if ( configNUMBER_OF_CORES > 1 )
+                        if( xYieldForTask != pdFALSE )
+                        {
+                            /* The priority of the task is being raised. If a running
+                             * task has priority lower than this task, it should yield
+                             * for this task. */
+                            taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
+                        }
+                        else
+                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+
+                /* Remove compiler warning about unused variables when the port
+                 * optimised task selection is not being used. */
+                ( void ) uxPriorityUsedOnEntry;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskPrioritySet();
+    }
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    void vTaskCoreAffinitySet( const TaskHandle_t xTask,
+                               UBaseType_t uxCoreAffinityMask )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xCoreID;
+        UBaseType_t uxPrevCoreAffinityMask;
+
+        #if ( configUSE_PREEMPTION == 1 )
+            UBaseType_t uxPrevNotAllowedCores;
+        #endif
+
+        traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask );
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            uxPrevCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+            pxTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+            if( xSchedulerRunning != pdFALSE )
+            {
+                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                {
+                    xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;
+
+                    /* If the task can no longer run on the core it was running,
+                     * request the core to yield. */
+                    if( ( uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) == 0U )
+                    {
+                        prvYieldCore( xCoreID );
+                    }
+                }
+                else
+                {
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        /* Calculate the cores on which this task was not allowed to
+                         * run previously. */
+                        uxPrevNotAllowedCores = ( ~uxPrevCoreAffinityMask ) & ( ( 1U << configNUMBER_OF_CORES ) - 1U );
+
+                        /* Does the new core mask enables this task to run on any of the
+                         * previously not allowed cores? If yes, check if this task can be
+                         * scheduled on any of those cores. */
+                        if( ( uxPrevNotAllowedCores & uxCoreAffinityMask ) != 0U )
+                        {
+                            prvYieldForTask( pxTCB );
+                        }
+                    }
+                    #else /* #if( configUSE_PREEMPTION == 1 ) */
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                    #endif /* #if( configUSE_PREEMPTION == 1 ) */
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskCoreAffinitySet();
+    }
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask )
+    {
+        const TCB_t * pxTCB;
+        UBaseType_t uxCoreAffinityMask;
+
+        traceENTER_vTaskCoreAffinityGet( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask );
+
+        return uxCoreAffinityMask;
+    }
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+    void vTaskPreemptionDisable( const TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_vTaskPreemptionDisable( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            pxTCB->xPreemptionDisable = pdTRUE;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskPreemptionDisable();
+    }
+
+#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+    void vTaskPreemptionEnable( const TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xCoreID;
+
+        traceENTER_vTaskPreemptionEnable( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            pxTCB->xPreemptionDisable = pdFALSE;
+
+            if( xSchedulerRunning != pdFALSE )
+            {
+                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                {
+                    xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;
+                    prvYieldCore( xCoreID );
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskPreemptionEnable();
+    }
+
+#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+    {
+        TCB_t * pxTCB;
+
+        #if ( configNUMBER_OF_CORES > 1 )
+            BaseType_t xTaskRunningOnCore;
+        #endif
+
+        traceENTER_vTaskSuspend( xTaskToSuspend );
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the running task that is
+             * being suspended. */
+            pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+            traceTASK_SUSPEND( pxTCB );
+
+            #if ( configNUMBER_OF_CORES > 1 )
+                xTaskRunningOnCore = pxTCB->xTaskRunState;
+            #endif
+
+            /* Remove task from the ready/delayed list and place in the
+             * suspended list. */
+            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+            {
+                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Is the task waiting on an event also? */
+            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+            {
+                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+            #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+            {
+                BaseType_t x;
+
+                for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                {
+                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                    {
+                        /* The task was blocked to wait for a notification, but is
+                         * now suspended, so no notification was received. */
+                        pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION;
+                    }
+                }
+            }
+            #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+        }
+
+        #if ( configNUMBER_OF_CORES == 1 )
+        {
+            taskEXIT_CRITICAL();
+
+            if( xSchedulerRunning != pdFALSE )
+            {
+                /* Reset the next expected unblock time in case it referred to the
+                 * task that is now in the Suspended state. */
+                taskENTER_CRITICAL();
+                {
+                    prvResetNextTaskUnblockTime();
+                }
+                taskEXIT_CRITICAL();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            if( pxTCB == pxCurrentTCB )
+            {
+                if( xSchedulerRunning != pdFALSE )
+                {
+                    /* The current task has just been suspended. */
+                    configASSERT( uxSchedulerSuspended == 0 );
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    /* The scheduler is not running, but the task that was pointed
+                     * to by pxCurrentTCB has just been suspended and pxCurrentTCB
+                     * must be adjusted to point to a different task. */
+                    if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+                    {
+                        /* No other tasks are ready, so set pxCurrentTCB back to
+                         * NULL so when the next task is created pxCurrentTCB will
+                         * be set to point to it no matter what its relative priority
+                         * is. */
+                        pxCurrentTCB = NULL;
+                    }
+                    else
+                    {
+                        vTaskSwitchContext();
+                    }
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+        {
+            if( xSchedulerRunning != pdFALSE )
+            {
+                /* Reset the next expected unblock time in case it referred to the
+                 * task that is now in the Suspended state. */
+                prvResetNextTaskUnblockTime();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+            {
+                if( xSchedulerRunning != pdFALSE )
+                {
+                    if( xTaskRunningOnCore == ( BaseType_t ) portGET_CORE_ID() )
+                    {
+                        /* The current task has just been suspended. */
+                        configASSERT( uxSchedulerSuspended == 0 );
+                        vTaskYieldWithinAPI();
+                    }
+                    else
+                    {
+                        prvYieldCore( xTaskRunningOnCore );
+                    }
+                }
+                else
+                {
+                    /* This code path is not possible because only Idle tasks are
+                     * assigned a core before the scheduler is started ( i.e.
+                     * taskTASK_IS_RUNNING is only true for idle tasks before
+                     * the scheduler is started ) and idle tasks cannot be
+                     * suspended. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            taskEXIT_CRITICAL();
+        }
+        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+        traceRETURN_vTaskSuspend();
+    }
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+    {
+        BaseType_t xReturn = pdFALSE;
+        const TCB_t * const pxTCB = xTask;
+
+        /* Accesses xPendingReadyList so must be called from a critical
+         * section. */
+
+        /* It does not make sense to check if the calling task is suspended. */
+        configASSERT( xTask );
+
+        /* Is the task being resumed actually in the suspended list? */
+        if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+        {
+            /* Has the task already been resumed from within an ISR? */
+            if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+            {
+                /* Is it in the suspended list because it is in the Suspended
+                 * state, or because it is blocked with no timeout? */
+                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
+                {
+                    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+                    {
+                        BaseType_t x;
+
+                        /* The task does not appear on the event list item of
+                         * and of the RTOS objects, but could still be in the
+                         * blocked state if it is waiting on its notification
+                         * rather than waiting on an object.  If not, is
+                         * suspended. */
+                        xReturn = pdTRUE;
+
+                        for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                        {
+                            if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                            {
+                                xReturn = pdFALSE;
+                                break;
+                            }
+                        }
+                    }
+                    #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+                    {
+                        xReturn = pdTRUE;
+                    }
+                    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    }
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    void vTaskResume( TaskHandle_t xTaskToResume )
+    {
+        TCB_t * const pxTCB = xTaskToResume;
+
+        traceENTER_vTaskResume( xTaskToResume );
+
+        /* It does not make sense to resume the calling task. */
+        configASSERT( xTaskToResume );
+
+        #if ( configNUMBER_OF_CORES == 1 )
+
+            /* The parameter cannot be NULL as it is impossible to resume the
+             * currently executing task. */
+            if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+        #else
+
+            /* The parameter cannot be NULL as it is impossible to resume the
+             * currently executing task. It is also impossible to resume a task
+             * that is actively running on another core but it is not safe
+             * to check their run state here. Therefore, we get into a critical
+             * section and check if the task is actually suspended or not. */
+            if( pxTCB != NULL )
+        #endif
+        {
+            taskENTER_CRITICAL();
+            {
+                if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+                {
+                    traceTASK_RESUME( pxTCB );
+
+                    /* The ready list can be accessed even if the scheduler is
+                     * suspended because this is inside a critical section. */
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+
+                    /* This yield may not cause the task just resumed to run,
+                     * but will leave the lists in the correct state for the
+                     * next yield. */
+                    taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            taskEXIT_CRITICAL();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskResume();
+    }
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+    BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+    {
+        BaseType_t xYieldRequired = pdFALSE;
+        TCB_t * const pxTCB = xTaskToResume;
+        UBaseType_t uxSavedInterruptStatus;
+
+        traceENTER_xTaskResumeFromISR( xTaskToResume );
+
+        configASSERT( xTaskToResume );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+            {
+                traceTASK_RESUME_FROM_ISR( pxTCB );
+
+                /* Check the ready lists can be accessed. */
+                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+                {
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        /* Ready lists can be accessed so move the task from the
+                         * suspended list to the ready list directly. */
+                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                        {
+                            xYieldRequired = pdTRUE;
+
+                            /* Mark that a yield is pending in case the user is not
+                             * using the return value to initiate a context switch
+                             * from the ISR using the port specific portYIELD_FROM_ISR(). */
+                            xYieldPendings[ 0 ] = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    /* The delayed or ready lists cannot be accessed so the task
+                     * is held in the pending ready list until the scheduler is
+                     * unsuspended. */
+                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+                }
+
+                #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) )
+                {
+                    prvYieldForTask( pxTCB );
+
+                    if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
+                    {
+                        xYieldRequired = pdTRUE;
+                    }
+                }
+                #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) */
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_xTaskResumeFromISR( xYieldRequired );
+
+        return xYieldRequired;
+    }
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCreateIdleTasks( void )
+{
+    BaseType_t xReturn = pdPASS;
+    BaseType_t xCoreID;
+    char cIdleName[ configMAX_TASK_NAME_LEN ];
+    TaskFunction_t pxIdleTaskFunction = NULL;
+    BaseType_t xIdleTaskNameIndex;
+
+    for( xIdleTaskNameIndex = ( BaseType_t ) 0; xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN; xIdleTaskNameIndex++ )
+    {
+        cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ];
+
+        /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+         * configMAX_TASK_NAME_LEN characters just in case the memory after the
+         * string is not accessible (extremely unlikely). */
+        if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 )
+        {
+            break;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    /* Add each idle task at the lowest priority. */
+    for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+    {
+        #if ( configNUMBER_OF_CORES == 1 )
+        {
+            pxIdleTaskFunction = prvIdleTask;
+        }
+        #else /* #if (  configNUMBER_OF_CORES == 1 ) */
+        {
+            /* In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks
+             * are also created to ensure that each core has an idle task to
+             * run when no other task is available to run. */
+            if( xCoreID == 0 )
+            {
+                pxIdleTaskFunction = prvIdleTask;
+            }
+            else
+            {
+                pxIdleTaskFunction = prvPassiveIdleTask;
+            }
+        }
+        #endif /* #if (  configNUMBER_OF_CORES == 1 ) */
+
+        /* Update the idle task name with suffix to differentiate the idle tasks.
+         * This function is not required in single core FreeRTOS since there is
+         * only one idle task. */
+        #if ( configNUMBER_OF_CORES > 1 )
+        {
+            /* Append the idle task number to the end of the name if there is space. */
+            if( xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN )
+            {
+                cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );
+
+                /* And append a null character if there is space. */
+                if( ( xIdleTaskNameIndex + 1 ) < ( BaseType_t ) configMAX_TASK_NAME_LEN )
+                {
+                    cIdleName[ xIdleTaskNameIndex + 1 ] = '\0';
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
+        #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+        {
+            StaticTask_t * pxIdleTaskTCBBuffer = NULL;
+            StackType_t * pxIdleTaskStackBuffer = NULL;
+            uint32_t ulIdleTaskStackSize;
+
+            /* The Idle task is created using user provided RAM - obtain the
+             * address of the RAM then create the idle task. */
+            #if ( configNUMBER_OF_CORES == 1 )
+            {
+                vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+            }
+            #else
+            {
+                if( xCoreID == 0 )
+                {
+                    vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+                }
+                else
+                {
+                    vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize, xCoreID - 1 );
+                }
+            }
+            #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+            xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction,
+                                                             cIdleName,
+                                                             ulIdleTaskStackSize,
+                                                             ( void * ) NULL,
+                                                             portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                                             pxIdleTaskStackBuffer,
+                                                             pxIdleTaskTCBBuffer );
+
+            if( xIdleTaskHandles[ xCoreID ] != NULL )
+            {
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+        {
+            /* The Idle task is being created using dynamically allocated RAM. */
+            xReturn = xTaskCreate( pxIdleTaskFunction,
+                                   cIdleName,
+                                   configMINIMAL_STACK_SIZE,
+                                   ( void * ) NULL,
+                                   portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                   &xIdleTaskHandles[ xCoreID ] );
+        }
+        #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+        /* Break the loop if any of the idle task is failed to be created. */
+        if( xReturn == pdFAIL )
+        {
+            break;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+    BaseType_t xReturn;
+
+    traceENTER_vTaskStartScheduler();
+
+    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+    {
+        /* Sanity check that the UBaseType_t must have greater than or equal to
+         * the number of bits as confNUMBER_OF_CORES. */
+        configASSERT( ( sizeof( UBaseType_t ) * taskBITS_PER_BYTE ) >= configNUMBER_OF_CORES );
+    }
+    #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
+
+    xReturn = prvCreateIdleTasks();
+
+    #if ( configUSE_TIMERS == 1 )
+    {
+        if( xReturn == pdPASS )
+        {
+            xReturn = xTimerCreateTimerTask();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #endif /* configUSE_TIMERS */
+
+    if( xReturn == pdPASS )
+    {
+        /* freertos_tasks_c_additions_init() should only be called if the user
+         * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+         * the only macro called by the function. */
+        #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+        {
+            freertos_tasks_c_additions_init();
+        }
+        #endif
+
+        /* Interrupts are turned off here, to ensure a tick does not occur
+         * before or during the call to xPortStartScheduler().  The stacks of
+         * the created tasks contain a status word with interrupts switched on
+         * so interrupts will automatically get re-enabled when the first task
+         * starts to run. */
+        portDISABLE_INTERRUPTS();
+
+        #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+        {
+            /* Switch C-Runtime's TLS Block to point to the TLS
+             * block specific to the task that will run first. */
+            configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+        }
+        #endif
+
+        xNextTaskUnblockTime = portMAX_DELAY;
+        xSchedulerRunning = pdTRUE;
+        xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+        /* If configGENERATE_RUN_TIME_STATS is defined then the following
+         * macro must be defined to configure the timer/counter used to generate
+         * the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+         * is set to 0 and the following line fails to build then ensure you do not
+         * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+         * FreeRTOSConfig.h file. */
+        portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+        traceTASK_SWITCHED_IN();
+
+        /* Setting up the timer tick is hardware specific and thus in the
+         * portable interface. */
+
+        /* The return value for xPortStartScheduler is not required
+         * hence using a void datatype. */
+        ( void ) xPortStartScheduler();
+
+        /* In most cases, xPortStartScheduler() will not return. If it
+         * returns pdTRUE then there was not enough heap memory available
+         * to create either the Idle or the Timer task. If it returned
+         * pdFALSE, then the application called xTaskEndScheduler().
+         * Most ports don't implement xTaskEndScheduler() as there is
+         * nothing to return to. */
+    }
+    else
+    {
+        /* This line will only be reached if the kernel could not be started,
+         * because there was not enough FreeRTOS heap to create the idle task
+         * or the timer task. */
+        configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+    }
+
+    /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+     * meaning xIdleTaskHandles are not used anywhere else. */
+    ( void ) xIdleTaskHandles;
+
+    /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
+     * from getting optimized out as it is no longer used by the kernel. */
+    ( void ) uxTopUsedPriority;
+
+    traceRETURN_vTaskStartScheduler();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+    traceENTER_vTaskEndScheduler();
+
+    /* Stop the scheduler interrupts and call the portable scheduler end
+     * routine so the original ISRs can be restored if necessary.  The port
+     * layer must ensure interrupts enable  bit is left in the correct state. */
+    portDISABLE_INTERRUPTS();
+    xSchedulerRunning = pdFALSE;
+    vPortEndScheduler();
+
+    traceRETURN_vTaskEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+    traceENTER_vTaskSuspendAll();
+
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        /* A critical section is not required as the variable is of type
+         * BaseType_t.  Please read Richard Barry's reply in the following link to a
+         * post in the FreeRTOS support forum before reporting this as a bug! -
+         * https://goo.gl/wu4acr */
+
+        /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
+         * do not otherwise exhibit real time behaviour. */
+        portSOFTWARE_BARRIER();
+
+        /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+         * is used to allow calls to vTaskSuspendAll() to nest. */
+        ++uxSchedulerSuspended;
+
+        /* Enforces ordering for ports and optimised compilers that may otherwise place
+         * the above increment elsewhere. */
+        portMEMORY_BARRIER();
+    }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    {
+        UBaseType_t ulState;
+
+        /* This must only be called from within a task. */
+        portASSERT_IF_IN_ISR();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks.
+             * We must disable interrupts before we grab the locks in the event that this task is
+             * interrupted and switches context before incrementing uxSchedulerSuspended.
+             * It is safe to re-enable interrupts after releasing the ISR lock and incrementing
+             * uxSchedulerSuspended since that will prevent context switches. */
+            ulState = portSET_INTERRUPT_MASK();
+
+            /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+             * do not otherwise exhibit real time behaviour. */
+            portSOFTWARE_BARRIER();
+
+            portGET_TASK_LOCK();
+
+            /* uxSchedulerSuspended is increased after prvCheckForRunStateChange. The
+             * purpose is to prevent altering the variable when fromISR APIs are readying
+             * it. */
+            if( uxSchedulerSuspended == 0U )
+            {
+                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                {
+                    prvCheckForRunStateChange();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            portGET_ISR_LOCK();
+
+            /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
+             * is used to allow calls to vTaskSuspendAll() to nest. */
+            ++uxSchedulerSuspended;
+            portRELEASE_ISR_LOCK();
+
+            portCLEAR_INTERRUPT_MASK( ulState );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    traceRETURN_vTaskSuspendAll();
+}
+
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    static TickType_t prvGetExpectedIdleTime( void )
+    {
+        TickType_t xReturn;
+        UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+        /* uxHigherPriorityReadyTasks takes care of the case where
+         * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+         * task that are in the Ready state, even though the idle task is
+         * running. */
+        #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+        {
+            if( uxTopReadyPriority > tskIDLE_PRIORITY )
+            {
+                uxHigherPriorityReadyTasks = pdTRUE;
+            }
+        }
+        #else
+        {
+            const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+            /* When port optimised task selection is used the uxTopReadyPriority
+             * variable is used as a bit map.  If bits other than the least
+             * significant bit are set then there are tasks that have a priority
+             * above the idle priority that are in the Ready state.  This takes
+             * care of the case where the co-operative scheduler is in use. */
+            if( uxTopReadyPriority > uxLeastSignificantBit )
+            {
+                uxHigherPriorityReadyTasks = pdTRUE;
+            }
+        }
+        #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */
+
+        if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+        {
+            xReturn = 0;
+        }
+        else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1U )
+        {
+            /* There are other idle priority tasks in the ready state.  If
+             * time slicing is used then the very next tick interrupt must be
+             * processed. */
+            xReturn = 0;
+        }
+        else if( uxHigherPriorityReadyTasks != pdFALSE )
+        {
+            /* There are tasks in the Ready state that have a priority above the
+             * idle priority.  This path can only be reached if
+             * configUSE_PREEMPTION is 0. */
+            xReturn = 0;
+        }
+        else
+        {
+            xReturn = xNextTaskUnblockTime;
+            xReturn -= xTickCount;
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+    TCB_t * pxTCB = NULL;
+    BaseType_t xAlreadyYielded = pdFALSE;
+
+    traceENTER_xTaskResumeAll();
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        if( xSchedulerRunning != pdFALSE )
+    #endif
+    {
+        /* It is possible that an ISR caused a task to be removed from an event
+         * list while the scheduler was suspended.  If this was the case then the
+         * removed task will have been added to the xPendingReadyList.  Once the
+         * scheduler has been resumed it is safe to move all the pending ready
+         * tasks from this list into their appropriate ready list. */
+        taskENTER_CRITICAL();
+        {
+            BaseType_t xCoreID;
+            xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+            /* If uxSchedulerSuspended is zero then this function does not match a
+             * previous call to vTaskSuspendAll(). */
+            configASSERT( uxSchedulerSuspended != 0U );
+
+            --uxSchedulerSuspended;
+            portRELEASE_TASK_LOCK();
+
+            if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+            {
+                if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+                {
+                    /* Move any readied tasks from the pending list into the
+                     * appropriate ready list. */
+                    while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+                    {
+                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                        /* coverity[misra_c_2012_rule_11_5_violation] */
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+                        listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
+                        portMEMORY_BARRIER();
+                        listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
+                        prvAddTaskToReadyList( pxTCB );
+
+                        #if ( configNUMBER_OF_CORES == 1 )
+                        {
+                            /* If the moved task has a priority higher than the current
+                             * task then a yield must be performed. */
+                            if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                            {
+                                xYieldPendings[ xCoreID ] = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                        {
+                            /* All appropriate tasks yield at the moment a task is added to xPendingReadyList.
+                             * If the current core yielded then vTaskSwitchContext() has already been called
+                             * which sets xYieldPendings for the current core to pdTRUE. */
+                        }
+                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    }
+
+                    if( pxTCB != NULL )
+                    {
+                        /* A task was unblocked while the scheduler was suspended,
+                         * which may have prevented the next unblock time from being
+                         * re-calculated, in which case re-calculate it now.  Mainly
+                         * important for low power tickless implementations, where
+                         * this can prevent an unnecessary exit from low power
+                         * state. */
+                        prvResetNextTaskUnblockTime();
+                    }
+
+                    /* If any ticks occurred while the scheduler was suspended then
+                     * they should be processed now.  This ensures the tick count does
+                     * not  slip, and that any delayed tasks are resumed at the correct
+                     * time.
+                     *
+                     * It should be safe to call xTaskIncrementTick here from any core
+                     * since we are in a critical section and xTaskIncrementTick itself
+                     * protects itself within a critical section. Suspending the scheduler
+                     * from any core causes xTaskIncrementTick to increment uxPendedCounts. */
+                    {
+                        TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+                        if( xPendedCounts > ( TickType_t ) 0U )
+                        {
+                            do
+                            {
+                                if( xTaskIncrementTick() != pdFALSE )
+                                {
+                                    /* Other cores are interrupted from
+                                     * within xTaskIncrementTick(). */
+                                    xYieldPendings[ xCoreID ] = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+
+                                --xPendedCounts;
+                            } while( xPendedCounts > ( TickType_t ) 0U );
+
+                            xPendedTicks = 0;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+
+                    if( xYieldPendings[ xCoreID ] != pdFALSE )
+                    {
+                        #if ( configUSE_PREEMPTION != 0 )
+                        {
+                            xAlreadyYielded = pdTRUE;
+                        }
+                        #endif /* #if ( configUSE_PREEMPTION != 0 ) */
+
+                        #if ( configNUMBER_OF_CORES == 1 )
+                        {
+                            taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxCurrentTCB );
+                        }
+                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+
+    traceRETURN_xTaskResumeAll( xAlreadyYielded );
+
+    return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+    TickType_t xTicks;
+
+    traceENTER_xTaskGetTickCount();
+
+    /* Critical section required if running on a 16 bit processor. */
+    portTICK_TYPE_ENTER_CRITICAL();
+    {
+        xTicks = xTickCount;
+    }
+    portTICK_TYPE_EXIT_CRITICAL();
+
+    traceRETURN_xTaskGetTickCount( xTicks );
+
+    return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+    TickType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+
+    traceENTER_xTaskGetTickCountFromISR();
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call  interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+    {
+        xReturn = xTickCount;
+    }
+    portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xTaskGetTickCountFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+    traceENTER_uxTaskGetNumberOfTasks();
+
+    /* A critical section is not required because the variables are of type
+     * BaseType_t. */
+    traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks );
+
+    return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char * pcTaskGetName( TaskHandle_t xTaskToQuery )
+{
+    TCB_t * pxTCB;
+
+    traceENTER_pcTaskGetName( xTaskToQuery );
+
+    /* If null is passed in here then the name of the calling task is being
+     * queried. */
+    pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+    configASSERT( pxTCB );
+
+    traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) );
+
+    return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                         const char pcNameToQuery[] )
+        {
+            TCB_t * pxNextTCB;
+            TCB_t * pxFirstTCB;
+            TCB_t * pxReturn = NULL;
+            UBaseType_t x;
+            char cNextChar;
+            BaseType_t xBreakLoop;
+
+            /* This function is called with the scheduler suspended. */
+
+            if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+            {
+                /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+                do
+                {
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
+                    listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+
+                    /* Check each character in the name looking for a match or
+                     * mismatch. */
+                    xBreakLoop = pdFALSE;
+
+                    for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+                    {
+                        cNextChar = pxNextTCB->pcTaskName[ x ];
+
+                        if( cNextChar != pcNameToQuery[ x ] )
+                        {
+                            /* Characters didn't match. */
+                            xBreakLoop = pdTRUE;
+                        }
+                        else if( cNextChar == ( char ) 0x00 )
+                        {
+                            /* Both strings terminated, a match must have been
+                             * found. */
+                            pxReturn = pxNextTCB;
+                            xBreakLoop = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        if( xBreakLoop != pdFALSE )
+                        {
+                            break;
+                        }
+                    }
+
+                    if( pxReturn != NULL )
+                    {
+                        /* The handle has been found. */
+                        break;
+                    }
+                } while( pxNextTCB != pxFirstTCB );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            return pxReturn;
+        }
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+        static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                         const char pcNameToQuery[] )
+        {
+            TCB_t * pxReturn = NULL;
+            UBaseType_t x;
+            char cNextChar;
+            BaseType_t xBreakLoop;
+            const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
+            ListItem_t * pxIterator;
+
+            /* This function is called with the scheduler suspended. */
+
+            if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+            {
+                for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
+                {
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
+                    TCB_t * pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
+
+                    /* Check each character in the name looking for a match or
+                     * mismatch. */
+                    xBreakLoop = pdFALSE;
+
+                    for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+                    {
+                        cNextChar = pxTCB->pcTaskName[ x ];
+
+                        if( cNextChar != pcNameToQuery[ x ] )
+                        {
+                            /* Characters didn't match. */
+                            xBreakLoop = pdTRUE;
+                        }
+                        else if( cNextChar == ( char ) 0x00 )
+                        {
+                            /* Both strings terminated, a match must have been
+                             * found. */
+                            pxReturn = pxTCB;
+                            xBreakLoop = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        if( xBreakLoop != pdFALSE )
+                        {
+                            break;
+                        }
+                    }
+
+                    if( pxReturn != NULL )
+                    {
+                        /* The handle has been found. */
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            return pxReturn;
+        }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery )
+    {
+        UBaseType_t uxQueue = configMAX_PRIORITIES;
+        TCB_t * pxTCB;
+
+        traceENTER_xTaskGetHandle( pcNameToQuery );
+
+        /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+        configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+        vTaskSuspendAll();
+        {
+            /* Search the ready lists. */
+            do
+            {
+                uxQueue--;
+                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+                if( pxTCB != NULL )
+                {
+                    /* Found the handle. */
+                    break;
+                }
+            } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );
+
+            /* Search the delayed lists. */
+            if( pxTCB == NULL )
+            {
+                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+            }
+
+            if( pxTCB == NULL )
+            {
+                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+            }
+
+            #if ( INCLUDE_vTaskSuspend == 1 )
+            {
+                if( pxTCB == NULL )
+                {
+                    /* Search the suspended list. */
+                    pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+                }
+            }
+            #endif
+
+            #if ( INCLUDE_vTaskDelete == 1 )
+            {
+                if( pxTCB == NULL )
+                {
+                    /* Search the deleted list. */
+                    pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+                }
+            }
+            #endif
+        }
+        ( void ) xTaskResumeAll();
+
+        traceRETURN_xTaskGetHandle( pxTCB );
+
+        return pxTCB;
+    }
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask,
+                                      StackType_t ** ppuxStackBuffer,
+                                      StaticTask_t ** ppxTaskBuffer )
+    {
+        BaseType_t xReturn;
+        TCB_t * pxTCB;
+
+        traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer );
+
+        configASSERT( ppuxStackBuffer != NULL );
+        configASSERT( ppxTaskBuffer != NULL );
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 )
+        {
+            if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB )
+            {
+                *ppuxStackBuffer = pxTCB->pxStack;
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
+                *ppxTaskBuffer = ( StaticTask_t * ) pxTCB;
+                xReturn = pdTRUE;
+            }
+            else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+            {
+                *ppuxStackBuffer = pxTCB->pxStack;
+                *ppxTaskBuffer = NULL;
+                xReturn = pdTRUE;
+            }
+            else
+            {
+                xReturn = pdFALSE;
+            }
+        }
+        #else /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */
+        {
+            *ppuxStackBuffer = pxTCB->pxStack;
+            *ppxTaskBuffer = ( StaticTask_t * ) pxTCB;
+            xReturn = pdTRUE;
+        }
+        #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */
+
+        traceRETURN_xTaskGetStaticBuffers( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime )
+    {
+        UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+        traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+
+        vTaskSuspendAll();
+        {
+            /* Is there a space in the array for each task in the system? */
+            if( uxArraySize >= uxCurrentNumberOfTasks )
+            {
+                /* Fill in an TaskStatus_t structure with information on each
+                 * task in the Ready state. */
+                do
+                {
+                    uxQueue--;
+                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ) );
+                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );
+
+                /* Fill in an TaskStatus_t structure with information on each
+                 * task in the Blocked state. */
+                uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ) );
+                uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ) );
+
+                #if ( INCLUDE_vTaskDelete == 1 )
+                {
+                    /* Fill in an TaskStatus_t structure with information on
+                     * each task that has been deleted but not yet cleaned up. */
+                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ) );
+                }
+                #endif
+
+                #if ( INCLUDE_vTaskSuspend == 1 )
+                {
+                    /* Fill in an TaskStatus_t structure with information on
+                     * each task in the Suspended state. */
+                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ) );
+                }
+                #endif
+
+                #if ( configGENERATE_RUN_TIME_STATS == 1 )
+                {
+                    if( pulTotalRunTime != NULL )
+                    {
+                        #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                            portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+                        #else
+                            *pulTotalRunTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+                        #endif
+                    }
+                }
+                #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+                {
+                    if( pulTotalRunTime != NULL )
+                    {
+                        *pulTotalRunTime = 0;
+                    }
+                }
+                #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        ( void ) xTaskResumeAll();
+
+        traceRETURN_uxTaskGetSystemState( uxTask );
+
+        return uxTask;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        TaskHandle_t xTaskGetIdleTaskHandle( void )
+        {
+            traceENTER_xTaskGetIdleTaskHandle();
+
+            /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+             * started, then xIdleTaskHandles will be NULL. */
+            configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) );
+
+            traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] );
+
+            return xIdleTaskHandles[ 0 ];
+        }
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
+    TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID )
+    {
+        traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID );
+
+        /* Ensure the core ID is valid. */
+        configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE );
+
+        /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+         * started, then xIdleTaskHandles will be NULL. */
+        configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) );
+
+        traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandles[ xCoreID ] );
+
+        return xIdleTaskHandles[ xCoreID ];
+    }
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure vTaskStepTick() is available when user defined low power mode
+ * implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+ * 1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    void vTaskStepTick( TickType_t xTicksToJump )
+    {
+        TickType_t xUpdatedTickCount;
+
+        traceENTER_vTaskStepTick( xTicksToJump );
+
+        /* Correct the tick count value after a period during which the tick
+         * was suppressed.  Note this does *not* call the tick hook function for
+         * each stepped tick. */
+        xUpdatedTickCount = xTickCount + xTicksToJump;
+        configASSERT( xUpdatedTickCount <= xNextTaskUnblockTime );
+
+        if( xUpdatedTickCount == xNextTaskUnblockTime )
+        {
+            /* Arrange for xTickCount to reach xNextTaskUnblockTime in
+             * xTaskIncrementTick() when the scheduler resumes.  This ensures
+             * that any delayed tasks are resumed at the correct time. */
+            configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
+            configASSERT( xTicksToJump != ( TickType_t ) 0 );
+
+            /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */
+            taskENTER_CRITICAL();
+            {
+                xPendedTicks++;
+            }
+            taskEXIT_CRITICAL();
+            xTicksToJump--;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        xTickCount += xTicksToJump;
+
+        traceINCREASE_TICK_COUNT( xTicksToJump );
+        traceRETURN_vTaskStepTick();
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+    BaseType_t xYieldOccurred;
+
+    traceENTER_xTaskCatchUpTicks( xTicksToCatchUp );
+
+    /* Must not be called with the scheduler suspended as the implementation
+     * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+    configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
+
+    /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+     * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+    vTaskSuspendAll();
+
+    /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */
+    taskENTER_CRITICAL();
+    {
+        xPendedTicks += xTicksToCatchUp;
+    }
+    taskEXIT_CRITICAL();
+    xYieldOccurred = xTaskResumeAll();
+
+    traceRETURN_xTaskCatchUpTicks( xYieldOccurred );
+
+    return xYieldOccurred;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+    BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB = xTask;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskAbortDelay( xTask );
+
+        configASSERT( pxTCB );
+
+        vTaskSuspendAll();
+        {
+            /* A task can only be prematurely removed from the Blocked state if
+             * it is actually in the Blocked state. */
+            if( eTaskGetState( xTask ) == eBlocked )
+            {
+                xReturn = pdPASS;
+
+                /* Remove the reference to the task from the blocked list.  An
+                 * interrupt won't touch the xStateListItem because the
+                 * scheduler is suspended. */
+                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+                /* Is the task waiting on an event also?  If so remove it from
+                 * the event list too.  Interrupts can touch the event list item,
+                 * even though the scheduler is suspended, so a critical section
+                 * is used. */
+                taskENTER_CRITICAL();
+                {
+                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+                    {
+                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+                        /* This lets the task know it was forcibly removed from the
+                         * blocked state so it should not re-evaluate its block time and
+                         * then block again. */
+                        pxTCB->ucDelayAborted = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                taskEXIT_CRITICAL();
+
+                /* Place the unblocked task into the appropriate ready list. */
+                prvAddTaskToReadyList( pxTCB );
+
+                /* A task being unblocked cannot cause an immediate context
+                 * switch if preemption is turned off. */
+                #if ( configUSE_PREEMPTION == 1 )
+                {
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        /* Preemption is on, but a context switch should only be
+                         * performed if the unblocked task has a priority that is
+                         * higher than the currently executing task. */
+                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                        {
+                            /* Pend the yield to be performed when the scheduler
+                             * is unsuspended. */
+                            xYieldPendings[ 0 ] = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    {
+                        taskENTER_CRITICAL();
+                        {
+                            prvYieldForTask( pxTCB );
+                        }
+                        taskEXIT_CRITICAL();
+                    }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                }
+                #endif /* #if ( configUSE_PREEMPTION == 1 ) */
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        ( void ) xTaskResumeAll();
+
+        traceRETURN_xTaskAbortDelay( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+    TCB_t * pxTCB;
+    TickType_t xItemValue;
+    BaseType_t xSwitchRequired = pdFALSE;
+
+    #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 )
+    BaseType_t xYieldRequiredForCore[ configNUMBER_OF_CORES ] = { pdFALSE };
+    #endif /* #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
+
+    traceENTER_xTaskIncrementTick();
+
+    /* Called by the portable layer each time a tick interrupt occurs.
+     * Increments the tick then checks to see if the new tick value will cause any
+     * tasks to be unblocked. */
+    traceTASK_INCREMENT_TICK( xTickCount );
+
+    /* Tick increment should occur on every kernel timer event. Core 0 has the
+     * responsibility to increment the tick, or increment the pended ticks if the
+     * scheduler is suspended.  If pended ticks is greater than zero, the core that
+     * calls xTaskResumeAll has the responsibility to increment the tick. */
+    if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+    {
+        /* Minor optimisation.  The tick count cannot change in this
+         * block. */
+        const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+        /* Increment the RTOS tick, switching the delayed and overflowed
+         * delayed lists if it wraps to 0. */
+        xTickCount = xConstTickCount;
+
+        if( xConstTickCount == ( TickType_t ) 0U )
+        {
+            taskSWITCH_DELAYED_LISTS();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* See if this tick has made a timeout expire.  Tasks are stored in
+         * the  queue in the order of their wake time - meaning once one task
+         * has been found whose block time has not expired there is no need to
+         * look any further down the list. */
+        if( xConstTickCount >= xNextTaskUnblockTime )
+        {
+            for( ; ; )
+            {
+                if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+                {
+                    /* The delayed list is empty.  Set xNextTaskUnblockTime
+                     * to the maximum possible value so it is extremely
+                     * unlikely that the
+                     * if( xTickCount >= xNextTaskUnblockTime ) test will pass
+                     * next time through. */
+                    xNextTaskUnblockTime = portMAX_DELAY;
+                    break;
+                }
+                else
+                {
+                    /* The delayed list is not empty, get the value of the
+                     * item at the head of the delayed list.  This is the time
+                     * at which the task at the head of the delayed list must
+                     * be removed from the Blocked state. */
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
+                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+                    xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+                    if( xConstTickCount < xItemValue )
+                    {
+                        /* It is not time to unblock this item yet, but the
+                         * item value is the time at which the task at the head
+                         * of the blocked list must be removed from the Blocked
+                         * state -  so record the item value in
+                         * xNextTaskUnblockTime. */
+                        xNextTaskUnblockTime = xItemValue;
+                        break;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* It is time to remove the item from the Blocked state. */
+                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
+
+                    /* Is the task waiting on an event also?  If so remove
+                     * it from the event list. */
+                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+                    {
+                        listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Place the unblocked task into the appropriate ready
+                     * list. */
+                    prvAddTaskToReadyList( pxTCB );
+
+                    /* A task being unblocked cannot cause an immediate
+                     * context switch if preemption is turned off. */
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        #if ( configNUMBER_OF_CORES == 1 )
+                        {
+                            /* Preemption is on, but a context switch should
+                             * only be performed if the unblocked task's
+                             * priority is higher than the currently executing
+                             * task.
+                             * The case of equal priority tasks sharing
+                             * processing time (which happens when both
+                             * preemption and time slicing are on) is
+                             * handled below.*/
+                            if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                            {
+                                xSwitchRequired = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        #else /* #if( configNUMBER_OF_CORES == 1 ) */
+                        {
+                            prvYieldForTask( pxTCB );
+                        }
+                        #endif /* #if( configNUMBER_OF_CORES == 1 ) */
+                    }
+                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
+                }
+            }
+        }
+
+        /* Tasks of equal priority to the currently running task will share
+         * processing time (time slice) if preemption is on, and the application
+         * writer has not explicitly turned time slicing off. */
+        #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+        {
+            #if ( configNUMBER_OF_CORES == 1 )
+            {
+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > 1U )
+                {
+                    xSwitchRequired = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+            {
+                BaseType_t xCoreID;
+
+                for( xCoreID = 0; xCoreID < ( ( BaseType_t ) configNUMBER_OF_CORES ); xCoreID++ )
+                {
+                    if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1U )
+                    {
+                        xYieldRequiredForCore[ xCoreID ] = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+            }
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+        }
+        #endif /* #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+        #if ( configUSE_TICK_HOOK == 1 )
+        {
+            /* Guard against the tick hook being called when the pended tick
+             * count is being unwound (when the scheduler is being unlocked). */
+            if( xPendedTicks == ( TickType_t ) 0 )
+            {
+                vApplicationTickHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #endif /* configUSE_TICK_HOOK */
+
+        #if ( configUSE_PREEMPTION == 1 )
+        {
+            #if ( configNUMBER_OF_CORES == 1 )
+            {
+                /* For single core the core ID is always 0. */
+                if( xYieldPendings[ 0 ] != pdFALSE )
+                {
+                    xSwitchRequired = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+            {
+                BaseType_t xCoreID, xCurrentCoreID;
+                xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+                for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+                {
+                    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                        if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
+                    #endif
+                    {
+                        if( ( xYieldRequiredForCore[ xCoreID ] != pdFALSE ) || ( xYieldPendings[ xCoreID ] != pdFALSE ) )
+                        {
+                            if( xCoreID == xCurrentCoreID )
+                            {
+                                xSwitchRequired = pdTRUE;
+                            }
+                            else
+                            {
+                                prvYieldCore( xCoreID );
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                }
+            }
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+        }
+        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
+    }
+    else
+    {
+        ++xPendedTicks;
+
+        /* The tick hook gets called at regular intervals, even if the
+         * scheduler is locked. */
+        #if ( configUSE_TICK_HOOK == 1 )
+        {
+            vApplicationTickHook();
+        }
+        #endif
+    }
+
+    traceRETURN_xTaskIncrementTick( xSwitchRequired );
+
+    return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                     TaskHookFunction_t pxHookFunction )
+    {
+        TCB_t * xTCB;
+
+        traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction );
+
+        /* If xTask is NULL then it is the task hook of the calling task that is
+         * getting set. */
+        if( xTask == NULL )
+        {
+            xTCB = ( TCB_t * ) pxCurrentTCB;
+        }
+        else
+        {
+            xTCB = xTask;
+        }
+
+        /* Save the hook function in the TCB.  A critical section is required as
+         * the value can be accessed from an interrupt. */
+        taskENTER_CRITICAL();
+        {
+            xTCB->pxTaskTag = pxHookFunction;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskSetApplicationTaskTag();
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        TaskHookFunction_t xReturn;
+
+        traceENTER_xTaskGetApplicationTaskTag( xTask );
+
+        /* If xTask is NULL then set the calling task's hook. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        /* Save the hook function in the TCB.  A critical section is required as
+         * the value can be accessed from an interrupt. */
+        taskENTER_CRITICAL();
+        {
+            xReturn = pxTCB->pxTaskTag;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xTaskGetApplicationTaskTag( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        TaskHookFunction_t xReturn;
+        UBaseType_t uxSavedInterruptStatus;
+
+        traceENTER_xTaskGetApplicationTaskTagFromISR( xTask );
+
+        /* If xTask is NULL then set the calling task's hook. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        /* Save the hook function in the TCB.  A critical section is required as
+         * the value can be accessed from an interrupt. */
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            xReturn = pxTCB->pxTaskTag;
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                             void * pvParameter )
+    {
+        TCB_t * xTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter );
+
+        /* If xTask is NULL then we are calling our own task hook. */
+        if( xTask == NULL )
+        {
+            xTCB = pxCurrentTCB;
+        }
+        else
+        {
+            xTCB = xTask;
+        }
+
+        if( xTCB->pxTaskTag != NULL )
+        {
+            xReturn = xTCB->pxTaskTag( pvParameter );
+        }
+        else
+        {
+            xReturn = pdFAIL;
+        }
+
+        traceRETURN_xTaskCallApplicationTaskHook( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES == 1 )
+    void vTaskSwitchContext( void )
+    {
+        traceENTER_vTaskSwitchContext();
+
+        if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
+        {
+            /* The scheduler is currently suspended - do not allow a context
+             * switch. */
+            xYieldPendings[ 0 ] = pdTRUE;
+        }
+        else
+        {
+            xYieldPendings[ 0 ] = pdFALSE;
+            traceTASK_SWITCHED_OUT();
+
+            #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            {
+                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                    portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ 0 ] );
+                #else
+                    ulTotalRunTime[ 0 ] = portGET_RUN_TIME_COUNTER_VALUE();
+                #endif
+
+                /* Add the amount of time the task has been running to the
+                 * accumulated time so far.  The time the task started running was
+                 * stored in ulTaskSwitchedInTime.  Note that there is no overflow
+                 * protection here so count values are only valid until the timer
+                 * overflows.  The guard against negative values is to protect
+                 * against suspect run time stat counter implementations - which
+                 * are provided by the application, not the kernel. */
+                if( ulTotalRunTime[ 0 ] > ulTaskSwitchedInTime[ 0 ] )
+                {
+                    pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ 0 ] - ulTaskSwitchedInTime[ 0 ] );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                ulTaskSwitchedInTime[ 0 ] = ulTotalRunTime[ 0 ];
+            }
+            #endif /* configGENERATE_RUN_TIME_STATS */
+
+            /* Check for stack overflow, if configured. */
+            taskCHECK_FOR_STACK_OVERFLOW();
+
+            /* Before the currently running task is switched out, save its errno. */
+            #if ( configUSE_POSIX_ERRNO == 1 )
+            {
+                pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+            }
+            #endif
+
+            /* Select a new task to run using either the generic C or port
+             * optimised asm code. */
+            /* MISRA Ref 11.5.3 [Void pointer assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            taskSELECT_HIGHEST_PRIORITY_TASK();
+            traceTASK_SWITCHED_IN();
+
+            /* Macro to inject port specific behaviour immediately after
+             * switching tasks, such as setting an end of stack watchpoint
+             * or reconfiguring the MPU. */
+            portTASK_SWITCH_HOOK( pxCurrentTCB );
+
+            /* After the new task is switched in, update the global errno. */
+            #if ( configUSE_POSIX_ERRNO == 1 )
+            {
+                FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+            }
+            #endif
+
+            #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+            {
+                /* Switch C-Runtime's TLS Block to point to the TLS
+                 * Block specific to this task. */
+                configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+            }
+            #endif
+        }
+
+        traceRETURN_vTaskSwitchContext();
+    }
+#else /* if ( configNUMBER_OF_CORES == 1 ) */
+    void vTaskSwitchContext( BaseType_t xCoreID )
+    {
+        traceENTER_vTaskSwitchContext();
+
+        /* Acquire both locks:
+         * - The ISR lock protects the ready list from simultaneous access by
+         *   both other ISRs and tasks.
+         * - We also take the task lock to pause here in case another core has
+         *   suspended the scheduler. We don't want to simply set xYieldPending
+         *   and move on if another core suspended the scheduler. We should only
+         *   do that if the current core has suspended the scheduler. */
+
+        portGET_TASK_LOCK(); /* Must always acquire the task lock first. */
+        portGET_ISR_LOCK();
+        {
+            /* vTaskSwitchContext() must never be called from within a critical section.
+             * This is not necessarily true for single core FreeRTOS, but it is for this
+             * SMP port. */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
+
+            if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
+            {
+                /* The scheduler is currently suspended - do not allow a context
+                 * switch. */
+                xYieldPendings[ xCoreID ] = pdTRUE;
+            }
+            else
+            {
+                xYieldPendings[ xCoreID ] = pdFALSE;
+                traceTASK_SWITCHED_OUT();
+
+                #if ( configGENERATE_RUN_TIME_STATS == 1 )
+                {
+                    #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                        portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ xCoreID ] );
+                    #else
+                        ulTotalRunTime[ xCoreID ] = portGET_RUN_TIME_COUNTER_VALUE();
+                    #endif
+
+                    /* Add the amount of time the task has been running to the
+                     * accumulated time so far.  The time the task started running was
+                     * stored in ulTaskSwitchedInTime.  Note that there is no overflow
+                     * protection here so count values are only valid until the timer
+                     * overflows.  The guard against negative values is to protect
+                     * against suspect run time stat counter implementations - which
+                     * are provided by the application, not the kernel. */
+                    if( ulTotalRunTime[ xCoreID ] > ulTaskSwitchedInTime[ xCoreID ] )
+                    {
+                        pxCurrentTCBs[ xCoreID ]->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    ulTaskSwitchedInTime[ xCoreID ] = ulTotalRunTime[ xCoreID ];
+                }
+                #endif /* configGENERATE_RUN_TIME_STATS */
+
+                /* Check for stack overflow, if configured. */
+                taskCHECK_FOR_STACK_OVERFLOW();
+
+                /* Before the currently running task is switched out, save its errno. */
+                #if ( configUSE_POSIX_ERRNO == 1 )
+                {
+                    pxCurrentTCBs[ xCoreID ]->iTaskErrno = FreeRTOS_errno;
+                }
+                #endif
+
+                /* Select a new task to run. */
+                taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID );
+                traceTASK_SWITCHED_IN();
+
+                /* Macro to inject port specific behaviour immediately after
+                 * switching tasks, such as setting an end of stack watchpoint
+                 * or reconfiguring the MPU. */
+                portTASK_SWITCH_HOOK( pxCurrentTCBs[ portGET_CORE_ID() ] );
+
+                /* After the new task is switched in, update the global errno. */
+                #if ( configUSE_POSIX_ERRNO == 1 )
+                {
+                    FreeRTOS_errno = pxCurrentTCBs[ xCoreID ]->iTaskErrno;
+                }
+                #endif
+
+                #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+                {
+                    /* Switch C-Runtime's TLS Block to point to the TLS
+                     * Block specific to this task. */
+                    configSET_TLS_BLOCK( pxCurrentTCBs[ xCoreID ]->xTLSBlock );
+                }
+                #endif
+            }
+        }
+        portRELEASE_ISR_LOCK();
+        portRELEASE_TASK_LOCK();
+
+        traceRETURN_vTaskSwitchContext();
+    }
+#endif /* if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList,
+                            const TickType_t xTicksToWait )
+{
+    traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait );
+
+    configASSERT( pxEventList );
+
+    /* THIS FUNCTION MUST BE CALLED WITH THE
+     * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+    /* Place the event list item of the TCB in the appropriate event list.
+     * This is placed in the list in priority order so the highest priority task
+     * is the first to be woken by the event.
+     *
+     * Note: Lists are sorted in ascending order by ListItem_t.xItemValue.
+     * Normally, the xItemValue of a TCB's ListItem_t members is:
+     *      xItemValue = ( configMAX_PRIORITIES - uxPriority )
+     * Therefore, the event list is sorted in descending priority order.
+     *
+     * The queue that contains the event list is locked, preventing
+     * simultaneous access from interrupts. */
+    vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+
+    traceRETURN_vTaskPlaceOnEventList();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
+                                     const TickType_t xItemValue,
+                                     const TickType_t xTicksToWait )
+{
+    traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait );
+
+    configASSERT( pxEventList );
+
+    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+     * the event groups implementation. */
+    configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
+
+    /* Store the item value in the event list item.  It is safe to access the
+     * event list item here as interrupts won't access the event list item of a
+     * task that is not in the Blocked state. */
+    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+    /* Place the event list item of the TCB at the end of the appropriate event
+     * list.  It is safe to access the event list here because it is part of an
+     * event group implementation - and interrupts don't access event groups
+     * directly (instead they access them indirectly by pending function calls to
+     * the task level). */
+    listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+
+    traceRETURN_vTaskPlaceOnUnorderedEventList();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+    void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
+                                          TickType_t xTicksToWait,
+                                          const BaseType_t xWaitIndefinitely )
+    {
+        traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely );
+
+        configASSERT( pxEventList );
+
+        /* This function should not be called by application code hence the
+         * 'Restricted' in its name.  It is not part of the public API.  It is
+         * designed for use by kernel code, and has special calling requirements -
+         * it should be called with the scheduler suspended. */
+
+
+        /* Place the event list item of the TCB in the appropriate event list.
+         * In this case it is assume that this is the only task that is going to
+         * be waiting on this event list, so the faster vListInsertEnd() function
+         * can be used in place of vListInsert. */
+        listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+        /* If the task should block indefinitely then set the block time to a
+         * value that will be recognised as an indefinite delay inside the
+         * prvAddCurrentTaskToDelayedList() function. */
+        if( xWaitIndefinitely != pdFALSE )
+        {
+            xTicksToWait = portMAX_DELAY;
+        }
+
+        traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+        prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+
+        traceRETURN_vTaskPlaceOnEventListRestricted();
+    }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+    TCB_t * pxUnblockedTCB;
+    BaseType_t xReturn;
+
+    traceENTER_xTaskRemoveFromEventList( pxEventList );
+
+    /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+     * called from a critical section within an ISR. */
+
+    /* The event list is sorted in priority order, so the first in the list can
+     * be removed as it is known to be the highest priority.  Remove the TCB from
+     * the delayed list, and add it to the ready list.
+     *
+     * If an event is for a queue that is locked then this function will never
+     * get called - the lock count on the queue will get modified instead.  This
+     * means exclusive access to the event list is guaranteed here.
+     *
+     * This function assumes that a check has already been made to ensure that
+     * pxEventList is not empty. */
+    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+    configASSERT( pxUnblockedTCB );
+    listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) );
+
+    if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+    {
+        listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
+        prvAddTaskToReadyList( pxUnblockedTCB );
+
+        #if ( configUSE_TICKLESS_IDLE != 0 )
+        {
+            /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+             * might be set to the blocked task's time out time.  If the task is
+             * unblocked for a reason other than a timeout xNextTaskUnblockTime is
+             * normally left unchanged, because it is automatically reset to a new
+             * value when the tick count equals xNextTaskUnblockTime.  However if
+             * tickless idling is used it might be more important to enter sleep mode
+             * at the earliest possible time - so reset xNextTaskUnblockTime here to
+             * ensure it is updated at the earliest possible time. */
+            prvResetNextTaskUnblockTime();
+        }
+        #endif
+    }
+    else
+    {
+        /* The delayed and ready lists cannot be accessed, so hold this task
+         * pending until the scheduler is resumed. */
+        listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+    }
+
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+        {
+            /* Return true if the task removed from the event list has a higher
+             * priority than the calling task.  This allows the calling task to know if
+             * it should force a context switch now. */
+            xReturn = pdTRUE;
+
+            /* Mark that a yield is pending in case the user is not using the
+             * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+            xYieldPendings[ 0 ] = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    {
+        xReturn = pdFALSE;
+
+        #if ( configUSE_PREEMPTION == 1 )
+        {
+            prvYieldForTask( pxUnblockedTCB );
+
+            if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
+            {
+                xReturn = pdTRUE;
+            }
+        }
+        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
+    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    traceRETURN_xTaskRemoveFromEventList( xReturn );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
+                                        const TickType_t xItemValue )
+{
+    TCB_t * pxUnblockedTCB;
+
+    traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue );
+
+    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+     * the event flags implementation. */
+    configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
+
+    /* Store the new item value in the event list. */
+    listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+    /* Remove the event list form the event flag.  Interrupts do not access
+     * event flags. */
+    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem );
+    configASSERT( pxUnblockedTCB );
+    listREMOVE_ITEM( pxEventListItem );
+
+    #if ( configUSE_TICKLESS_IDLE != 0 )
+    {
+        /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+         * might be set to the blocked task's time out time.  If the task is
+         * unblocked for a reason other than a timeout xNextTaskUnblockTime is
+         * normally left unchanged, because it is automatically reset to a new
+         * value when the tick count equals xNextTaskUnblockTime.  However if
+         * tickless idling is used it might be more important to enter sleep mode
+         * at the earliest possible time - so reset xNextTaskUnblockTime here to
+         * ensure it is updated at the earliest possible time. */
+        prvResetNextTaskUnblockTime();
+    }
+    #endif
+
+    /* Remove the task from the delayed list and add it to the ready list.  The
+     * scheduler is suspended so interrupts will not be accessing the ready
+     * lists. */
+    listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
+    prvAddTaskToReadyList( pxUnblockedTCB );
+
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+        {
+            /* The unblocked task has a priority above that of the calling task, so
+             * a context switch is required.  This function is called with the
+             * scheduler suspended so xYieldPending is set so the context switch
+             * occurs immediately that the scheduler is resumed (unsuspended). */
+            xYieldPendings[ 0 ] = pdTRUE;
+        }
+    }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    {
+        #if ( configUSE_PREEMPTION == 1 )
+        {
+            taskENTER_CRITICAL();
+            {
+                prvYieldForTask( pxUnblockedTCB );
+            }
+            taskEXIT_CRITICAL();
+        }
+        #endif
+    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    traceRETURN_vTaskRemoveFromUnorderedEventList();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+    traceENTER_vTaskSetTimeOutState( pxTimeOut );
+
+    configASSERT( pxTimeOut );
+    taskENTER_CRITICAL();
+    {
+        pxTimeOut->xOverflowCount = xNumOfOverflows;
+        pxTimeOut->xTimeOnEntering = xTickCount;
+    }
+    taskEXIT_CRITICAL();
+
+    traceRETURN_vTaskSetTimeOutState();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+    traceENTER_vTaskInternalSetTimeOutState( pxTimeOut );
+
+    /* For internal use only as it does not use a critical section. */
+    pxTimeOut->xOverflowCount = xNumOfOverflows;
+    pxTimeOut->xTimeOnEntering = xTickCount;
+
+    traceRETURN_vTaskInternalSetTimeOutState();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                 TickType_t * const pxTicksToWait )
+{
+    BaseType_t xReturn;
+
+    traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+
+    configASSERT( pxTimeOut );
+    configASSERT( pxTicksToWait );
+
+    taskENTER_CRITICAL();
+    {
+        /* Minor optimisation.  The tick count cannot change in this block. */
+        const TickType_t xConstTickCount = xTickCount;
+        const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+        #if ( INCLUDE_xTaskAbortDelay == 1 )
+            if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+            {
+                /* The delay was aborted, which is not the same as a time out,
+                 * but has the same result. */
+                pxCurrentTCB->ucDelayAborted = pdFALSE;
+                xReturn = pdTRUE;
+            }
+            else
+        #endif
+
+        #if ( INCLUDE_vTaskSuspend == 1 )
+            if( *pxTicksToWait == portMAX_DELAY )
+            {
+                /* If INCLUDE_vTaskSuspend is set to 1 and the block time
+                 * specified is the maximum block time then the task should block
+                 * indefinitely, and therefore never time out. */
+                xReturn = pdFALSE;
+            }
+            else
+        #endif
+
+        if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) )
+        {
+            /* The tick count is greater than the time at which
+             * vTaskSetTimeout() was called, but has also overflowed since
+             * vTaskSetTimeOut() was called.  It must have wrapped all the way
+             * around and gone past again. This passed since vTaskSetTimeout()
+             * was called. */
+            xReturn = pdTRUE;
+            *pxTicksToWait = ( TickType_t ) 0;
+        }
+        else if( xElapsedTime < *pxTicksToWait )
+        {
+            /* Not a genuine timeout. Adjust parameters for time remaining. */
+            *pxTicksToWait -= xElapsedTime;
+            vTaskInternalSetTimeOutState( pxTimeOut );
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            *pxTicksToWait = ( TickType_t ) 0;
+            xReturn = pdTRUE;
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    traceRETURN_xTaskCheckForTimeOut( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+    traceENTER_vTaskMissedYield();
+
+    /* Must be called from within a critical section. */
+    xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
+
+    traceRETURN_vTaskMissedYield();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+    {
+        UBaseType_t uxReturn;
+        TCB_t const * pxTCB;
+
+        traceENTER_uxTaskGetTaskNumber( xTask );
+
+        if( xTask != NULL )
+        {
+            pxTCB = xTask;
+            uxReturn = pxTCB->uxTaskNumber;
+        }
+        else
+        {
+            uxReturn = 0U;
+        }
+
+        traceRETURN_uxTaskGetTaskNumber( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vTaskSetTaskNumber( TaskHandle_t xTask,
+                             const UBaseType_t uxHandle )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_vTaskSetTaskNumber( xTask, uxHandle );
+
+        if( xTask != NULL )
+        {
+            pxTCB = xTask;
+            pxTCB->uxTaskNumber = uxHandle;
+        }
+
+        traceRETURN_vTaskSetTaskNumber();
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/*
+ * -----------------------------------------------------------
+ * The passive idle task.
+ * ----------------------------------------------------------
+ *
+ * The passive idle task is used for all the additional cores in a SMP
+ * system. There must be only 1 active idle task and the rest are passive
+ * idle tasks.
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvPassiveIdleTask( void *pvParameters );
+ */
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static portTASK_FUNCTION( prvPassiveIdleTask, pvParameters )
+    {
+        ( void ) pvParameters;
+
+        taskYIELD();
+
+        for( ; configCONTROL_INFINITE_LOOP(); )
+        {
+            #if ( configUSE_PREEMPTION == 0 )
+            {
+                /* If we are not using preemption we keep forcing a task switch to
+                 * see if any other task has become available.  If we are using
+                 * preemption we don't need to do this as any task becoming available
+                 * will automatically get the processor anyway. */
+                taskYIELD();
+            }
+            #endif /* configUSE_PREEMPTION */
+
+            #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+            {
+                /* When using preemption tasks of equal priority will be
+                 * timesliced.  If a task that is sharing the idle priority is ready
+                 * to run then the idle task should yield before the end of the
+                 * timeslice.
+                 *
+                 * A critical region is not required here as we are just reading from
+                 * the list, and an occasional incorrect value will not matter.  If
+                 * the ready list at the idle priority contains one more task than the
+                 * number of idle tasks, which is equal to the configured numbers of cores
+                 * then a task other than the idle task is ready to execute. */
+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
+                {
+                    taskYIELD();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+            #if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
+            {
+                /* Call the user defined function from within the idle task.  This
+                 * allows the application designer to add background functionality
+                 * without the overhead of a separate task.
+                 *
+                 * This hook is intended to manage core activity such as disabling cores that go idle.
+                 *
+                 * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+                 * CALL A FUNCTION THAT MIGHT BLOCK. */
+                vApplicationPassiveIdleHook();
+            }
+            #endif /* configUSE_PASSIVE_IDLE_HOOK */
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*
+ * -----------------------------------------------------------
+ * The idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+    /* Stop warnings. */
+    ( void ) pvParameters;
+
+    /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+     * SCHEDULER IS STARTED. **/
+
+    /* In case a task that has a secure context deletes itself, in which case
+     * the idle task is responsible for deleting the task's secure context, if
+     * any. */
+    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+    #if ( configNUMBER_OF_CORES > 1 )
+    {
+        /* SMP all cores start up in the idle task. This initial yield gets the application
+         * tasks started. */
+        taskYIELD();
+    }
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+    for( ; configCONTROL_INFINITE_LOOP(); )
+    {
+        /* See if any tasks have deleted themselves - if so then the idle task
+         * is responsible for freeing the deleted task's TCB and stack. */
+        prvCheckTasksWaitingTermination();
+
+        #if ( configUSE_PREEMPTION == 0 )
+        {
+            /* If we are not using preemption we keep forcing a task switch to
+             * see if any other task has become available.  If we are using
+             * preemption we don't need to do this as any task becoming available
+             * will automatically get the processor anyway. */
+            taskYIELD();
+        }
+        #endif /* configUSE_PREEMPTION */
+
+        #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+        {
+            /* When using preemption tasks of equal priority will be
+             * timesliced.  If a task that is sharing the idle priority is ready
+             * to run then the idle task should yield before the end of the
+             * timeslice.
+             *
+             * A critical region is not required here as we are just reading from
+             * the list, and an occasional incorrect value will not matter.  If
+             * the ready list at the idle priority contains one more task than the
+             * number of idle tasks, which is equal to the configured numbers of cores
+             * then a task other than the idle task is ready to execute. */
+            if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
+            {
+                taskYIELD();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+        #if ( configUSE_IDLE_HOOK == 1 )
+        {
+            /* Call the user defined function from within the idle task. */
+            vApplicationIdleHook();
+        }
+        #endif /* configUSE_IDLE_HOOK */
+
+        /* This conditional compilation should use inequality to 0, not equality
+         * to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+         * user defined low power mode  implementations require
+         * configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+        #if ( configUSE_TICKLESS_IDLE != 0 )
+        {
+            TickType_t xExpectedIdleTime;
+
+            /* It is not desirable to suspend then resume the scheduler on
+             * each iteration of the idle task.  Therefore, a preliminary
+             * test of the expected idle time is performed without the
+             * scheduler suspended.  The result here is not necessarily
+             * valid. */
+            xExpectedIdleTime = prvGetExpectedIdleTime();
+
+            if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+            {
+                vTaskSuspendAll();
+                {
+                    /* Now the scheduler is suspended, the expected idle
+                     * time can be sampled again, and this time its value can
+                     * be used. */
+                    configASSERT( xNextTaskUnblockTime >= xTickCount );
+                    xExpectedIdleTime = prvGetExpectedIdleTime();
+
+                    /* Define the following macro to set xExpectedIdleTime to 0
+                     * if the application does not want
+                     * portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+                    configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+                    if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+                    {
+                        traceLOW_POWER_IDLE_BEGIN();
+                        portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+                        traceLOW_POWER_IDLE_END();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                ( void ) xTaskResumeAll();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #endif /* configUSE_TICKLESS_IDLE */
+
+        #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) )
+        {
+            /* Call the user defined function from within the idle task.  This
+             * allows the application designer to add background functionality
+             * without the overhead of a separate task.
+             *
+             * This hook is intended to manage core activity such as disabling cores that go idle.
+             *
+             * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+             * CALL A FUNCTION THAT MIGHT BLOCK. */
+            vApplicationPassiveIdleHook();
+        }
+        #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+    {
+        #if ( INCLUDE_vTaskSuspend == 1 )
+            /* The idle task exists in addition to the application tasks. */
+            const UBaseType_t uxNonApplicationTasks = configNUMBER_OF_CORES;
+        #endif /* INCLUDE_vTaskSuspend */
+
+        eSleepModeStatus eReturn = eStandardSleep;
+
+        traceENTER_eTaskConfirmSleepModeStatus();
+
+        /* This function must be called from a critical section. */
+
+        if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0U )
+        {
+            /* A task was made ready while the scheduler was suspended. */
+            eReturn = eAbortSleep;
+        }
+        else if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
+        {
+            /* A yield was pended while the scheduler was suspended. */
+            eReturn = eAbortSleep;
+        }
+        else if( xPendedTicks != 0U )
+        {
+            /* A tick interrupt has already occurred but was held pending
+             * because the scheduler is suspended. */
+            eReturn = eAbortSleep;
+        }
+
+        #if ( INCLUDE_vTaskSuspend == 1 )
+            else if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+            {
+                /* If all the tasks are in the suspended list (which might mean they
+                 * have an infinite block time rather than actually being suspended)
+                 * then it is safe to turn all clocks off and just wait for external
+                 * interrupts. */
+                eReturn = eNoTasksWaitingTimeout;
+            }
+        #endif /* INCLUDE_vTaskSuspend */
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_eTaskConfirmSleepModeStatus( eReturn );
+
+        return eReturn;
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
+
+        if( ( xIndex >= 0 ) &&
+            ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
+        {
+            pxTCB = prvGetTCBFromHandle( xTaskToSet );
+            configASSERT( pxTCB != NULL );
+            pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+        }
+
+        traceRETURN_vTaskSetThreadLocalStoragePointer();
+    }
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex )
+    {
+        void * pvReturn = NULL;
+        TCB_t * pxTCB;
+
+        traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
+
+        if( ( xIndex >= 0 ) &&
+            ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
+        {
+            pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+            pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+        }
+        else
+        {
+            pvReturn = NULL;
+        }
+
+        traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn );
+
+        return pvReturn;
+    }
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+                                  const MemoryRegion_t * const pxRegions )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions );
+
+        /* If null is passed in here then we are modifying the MPU settings of
+         * the calling task. */
+        pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 );
+
+        traceRETURN_vTaskAllocateMPURegions();
+    }
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+    UBaseType_t uxPriority;
+
+    for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+    {
+        vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+    }
+
+    vListInitialise( &xDelayedTaskList1 );
+    vListInitialise( &xDelayedTaskList2 );
+    vListInitialise( &xPendingReadyList );
+
+    #if ( INCLUDE_vTaskDelete == 1 )
+    {
+        vListInitialise( &xTasksWaitingTermination );
+    }
+    #endif /* INCLUDE_vTaskDelete */
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+    {
+        vListInitialise( &xSuspendedTaskList );
+    }
+    #endif /* INCLUDE_vTaskSuspend */
+
+    /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+     * using list2. */
+    pxDelayedTaskList = &xDelayedTaskList1;
+    pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+    /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+    #if ( INCLUDE_vTaskDelete == 1 )
+    {
+        TCB_t * pxTCB;
+
+        /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+         * being called too often in the idle task. */
+        while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+        {
+            #if ( configNUMBER_OF_CORES == 1 )
+            {
+                taskENTER_CRITICAL();
+                {
+                    {
+                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                        /* coverity[misra_c_2012_rule_11_5_violation] */
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+                        ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                        --uxCurrentNumberOfTasks;
+                        --uxDeletedTasksWaitingCleanUp;
+                    }
+                }
+                taskEXIT_CRITICAL();
+
+                prvDeleteTCB( pxTCB );
+            }
+            #else /* #if( configNUMBER_OF_CORES == 1 ) */
+            {
+                pxTCB = NULL;
+
+                taskENTER_CRITICAL();
+                {
+                    /* For SMP, multiple idles can be running simultaneously
+                     * and we need to check that other idles did not cleanup while we were
+                     * waiting to enter the critical section. */
+                    if( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+                    {
+                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                        /* coverity[misra_c_2012_rule_11_5_violation] */
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+
+                        if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+                        {
+                            ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                            --uxCurrentNumberOfTasks;
+                            --uxDeletedTasksWaitingCleanUp;
+                        }
+                        else
+                        {
+                            /* The TCB to be deleted still has not yet been switched out
+                             * by the scheduler, so we will just exit this loop early and
+                             * try again next time. */
+                            taskEXIT_CRITICAL();
+                            break;
+                        }
+                    }
+                }
+                taskEXIT_CRITICAL();
+
+                if( pxTCB != NULL )
+                {
+                    prvDeleteTCB( pxTCB );
+                }
+            }
+            #endif /* #if( configNUMBER_OF_CORES == 1 ) */
+        }
+    }
+    #endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
+
+        /* xTask is NULL then get the state of the calling task. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        pxTaskStatus->xHandle = pxTCB;
+        pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
+        pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+        pxTaskStatus->pxStackBase = pxTCB->pxStack;
+        #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+            pxTaskStatus->pxTopOfStack = ( StackType_t * ) pxTCB->pxTopOfStack;
+            pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack;
+        #endif
+        pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+        #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+        {
+            pxTaskStatus->uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+        }
+        #endif
+
+        #if ( configUSE_MUTEXES == 1 )
+        {
+            pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+        }
+        #else
+        {
+            pxTaskStatus->uxBasePriority = 0;
+        }
+        #endif
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+        {
+            pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+        }
+        #else
+        {
+            pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0;
+        }
+        #endif
+
+        /* Obtaining the task state is a little fiddly, so is only done if the
+         * value of eState passed into this function is eInvalid - otherwise the
+         * state is just set to whatever is passed in. */
+        if( eState != eInvalid )
+        {
+            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+            {
+                pxTaskStatus->eCurrentState = eRunning;
+            }
+            else
+            {
+                pxTaskStatus->eCurrentState = eState;
+
+                #if ( INCLUDE_vTaskSuspend == 1 )
+                {
+                    /* If the task is in the suspended list then there is a
+                     *  chance it is actually just blocked indefinitely - so really
+                     *  it should be reported as being in the Blocked state. */
+                    if( eState == eSuspended )
+                    {
+                        vTaskSuspendAll();
+                        {
+                            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+                            {
+                                pxTaskStatus->eCurrentState = eBlocked;
+                            }
+                            else
+                            {
+                                BaseType_t x;
+
+                                /* The task does not appear on the event list item of
+                                 * and of the RTOS objects, but could still be in the
+                                 * blocked state if it is waiting on its notification
+                                 * rather than waiting on an object.  If not, is
+                                 * suspended. */
+                                for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                                {
+                                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                                    {
+                                        pxTaskStatus->eCurrentState = eBlocked;
+                                        break;
+                                    }
+                                }
+                            }
+                        }
+                        ( void ) xTaskResumeAll();
+                    }
+                }
+                #endif /* INCLUDE_vTaskSuspend */
+
+                /* Tasks can be in pending ready list and other state list at the
+                 * same time. These tasks are in ready state no matter what state
+                 * list the task is in. */
+                taskENTER_CRITICAL();
+                {
+                    if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdFALSE )
+                    {
+                        pxTaskStatus->eCurrentState = eReady;
+                    }
+                }
+                taskEXIT_CRITICAL();
+            }
+        }
+        else
+        {
+            pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+        }
+
+        /* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+         * parameter is provided to allow it to be skipped. */
+        if( xGetFreeStackSpace != pdFALSE )
+        {
+            #if ( portSTACK_GROWTH > 0 )
+            {
+                pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+            }
+            #else
+            {
+                pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+            }
+            #endif
+        }
+        else
+        {
+            pxTaskStatus->usStackHighWaterMark = 0;
+        }
+
+        traceRETURN_vTaskGetInfo();
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
+                                                     List_t * pxList,
+                                                     eTaskState eState )
+    {
+        configLIST_VOLATILE TCB_t * pxNextTCB;
+        configLIST_VOLATILE TCB_t * pxFirstTCB;
+        UBaseType_t uxTask = 0;
+
+        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+        {
+            /* MISRA Ref 11.5.3 [Void pointer assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+            /* Populate an TaskStatus_t structure within the
+             * pxTaskStatusArray array for each task that is referenced from
+             * pxList.  See the definition of TaskStatus_t in task.h for the
+             * meaning of each TaskStatus_t structure member. */
+            do
+            {
+                /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+                vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+                uxTask++;
+            } while( pxNextTCB != pxFirstTCB );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return uxTask;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+    {
+        uint32_t ulCount = 0U;
+
+        while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+        {
+            pucStackByte -= portSTACK_GROWTH;
+            ulCount++;
+        }
+
+        ulCount /= ( uint32_t ) sizeof( StackType_t );
+
+        return ( configSTACK_DEPTH_TYPE ) ulCount;
+    }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type. */
+    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        uint8_t * pucEndOfStack;
+        configSTACK_DEPTH_TYPE uxReturn;
+
+        traceENTER_uxTaskGetStackHighWaterMark2( xTask );
+
+        /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+         * the same except for their return type.  Using configSTACK_DEPTH_TYPE
+         * allows the user to determine the return type.  It gets around the
+         * problem of the value overflowing on 8-bit types without breaking
+         * backward compatibility for applications that expect an 8-bit return
+         * type. */
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        #if portSTACK_GROWTH < 0
+        {
+            pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+        }
+        #else
+        {
+            pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+        }
+        #endif
+
+        uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+        traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        uint8_t * pucEndOfStack;
+        UBaseType_t uxReturn;
+
+        traceENTER_uxTaskGetStackHighWaterMark( xTask );
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        #if portSTACK_GROWTH < 0
+        {
+            pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+        }
+        #else
+        {
+            pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+        }
+        #endif
+
+        uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+        traceRETURN_uxTaskGetStackHighWaterMark( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    static void prvDeleteTCB( TCB_t * pxTCB )
+    {
+        /* This call is required specifically for the TriCore port.  It must be
+         * above the vPortFree() calls.  The call is also used by ports/demos that
+         * want to allocate and clean RAM statically. */
+        portCLEAN_UP_TCB( pxTCB );
+
+        #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+        {
+            /* Free up the memory allocated for the task's TLS Block. */
+            configDEINIT_TLS_BLOCK( pxTCB->xTLSBlock );
+        }
+        #endif
+
+        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+        {
+            /* The task can only have been allocated dynamically - free both
+             * the stack and TCB. */
+            vPortFreeStack( pxTCB->pxStack );
+            vPortFree( pxTCB );
+        }
+        #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+        {
+            /* The task could have been allocated statically or dynamically, so
+             * check what was statically allocated before trying to free the
+             * memory. */
+            if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+            {
+                /* Both the stack and TCB were allocated dynamically, so both
+                 * must be freed. */
+                vPortFreeStack( pxTCB->pxStack );
+                vPortFree( pxTCB );
+            }
+            else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+            {
+                /* Only the stack was statically allocated, so the TCB is the
+                 * only memory that must be freed. */
+                vPortFree( pxTCB );
+            }
+            else
+            {
+                /* Neither the stack nor the TCB were allocated dynamically, so
+                 * nothing needs to be freed. */
+                configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+    }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+    if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+    {
+        /* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+         * the maximum possible value so it is  extremely unlikely that the
+         * if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+         * there is an item in the delayed list. */
+        xNextTaskUnblockTime = portMAX_DELAY;
+    }
+    else
+    {
+        /* The new current delayed list is not empty, get the value of
+         * the item at the head of the delayed list.  This is the time at
+         * which the task at the head of the delayed list should be removed
+         * from the Blocked state. */
+        xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 )
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        TaskHandle_t xTaskGetCurrentTaskHandle( void )
+        {
+            TaskHandle_t xReturn;
+
+            traceENTER_xTaskGetCurrentTaskHandle();
+
+            /* A critical section is not required as this is not called from
+             * an interrupt and the current TCB will always be the same for any
+             * individual execution thread. */
+            xReturn = pxCurrentTCB;
+
+            traceRETURN_xTaskGetCurrentTaskHandle( xReturn );
+
+            return xReturn;
+        }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+        TaskHandle_t xTaskGetCurrentTaskHandle( void )
+        {
+            TaskHandle_t xReturn;
+            UBaseType_t uxSavedInterruptStatus;
+
+            traceENTER_xTaskGetCurrentTaskHandle();
+
+            uxSavedInterruptStatus = portSET_INTERRUPT_MASK();
+            {
+                xReturn = pxCurrentTCBs[ portGET_CORE_ID() ];
+            }
+            portCLEAR_INTERRUPT_MASK( uxSavedInterruptStatus );
+
+            traceRETURN_xTaskGetCurrentTaskHandle( xReturn );
+
+            return xReturn;
+        }
+
+        TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID )
+        {
+            TaskHandle_t xReturn = NULL;
+
+            traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID );
+
+            if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
+            {
+                xReturn = pxCurrentTCBs[ xCoreID ];
+            }
+
+            traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+    BaseType_t xTaskGetSchedulerState( void )
+    {
+        BaseType_t xReturn;
+
+        traceENTER_xTaskGetSchedulerState();
+
+        if( xSchedulerRunning == pdFALSE )
+        {
+            xReturn = taskSCHEDULER_NOT_STARTED;
+        }
+        else
+        {
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskENTER_CRITICAL();
+            #endif
+            {
+                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+                {
+                    xReturn = taskSCHEDULER_RUNNING;
+                }
+                else
+                {
+                    xReturn = taskSCHEDULER_SUSPENDED;
+                }
+            }
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskEXIT_CRITICAL();
+            #endif
+        }
+
+        traceRETURN_xTaskGetSchedulerState( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+    {
+        TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+        BaseType_t xReturn = pdFALSE;
+
+        traceENTER_xTaskPriorityInherit( pxMutexHolder );
+
+        /* If the mutex is taken by an interrupt, the mutex holder is NULL. Priority
+         * inheritance is not applied in this scenario. */
+        if( pxMutexHolder != NULL )
+        {
+            /* If the holder of the mutex has a priority below the priority of
+             * the task attempting to obtain the mutex then it will temporarily
+             * inherit the priority of the task attempting to obtain the mutex. */
+            if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+            {
+                /* Adjust the mutex holder state to account for its new
+                 * priority.  Only reset the event list item value if the value is
+                 * not being used for anything else. */
+                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
+                {
+                    listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* If the task being modified is in the ready state it will need
+                 * to be moved into a new list. */
+                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+                {
+                    if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                    {
+                        /* It is known that the task is in its ready list so
+                         * there is no need to check again and the port level
+                         * reset macro can be called directly. */
+                        portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Inherit the priority before being moved into the new list. */
+                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+                    prvAddTaskToReadyList( pxMutexHolderTCB );
+                    #if ( configNUMBER_OF_CORES > 1 )
+                    {
+                        /* The priority of the task is raised. Yield for this task
+                         * if it is not running. */
+                        if( taskTASK_IS_RUNNING( pxMutexHolderTCB ) != pdTRUE )
+                        {
+                            prvYieldForTask( pxMutexHolderTCB );
+                        }
+                    }
+                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+                }
+                else
+                {
+                    /* Just inherit the priority. */
+                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+                }
+
+                traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+                /* Inheritance occurred. */
+                xReturn = pdTRUE;
+            }
+            else
+            {
+                if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+                {
+                    /* The base priority of the mutex holder is lower than the
+                     * priority of the task attempting to take the mutex, but the
+                     * current priority of the mutex holder is not lower than the
+                     * priority of the task attempting to take the mutex.
+                     * Therefore the mutex holder must have already inherited a
+                     * priority, but inheritance would have occurred if that had
+                     * not been the case. */
+                    xReturn = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xTaskPriorityInherit( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+    {
+        TCB_t * const pxTCB = pxMutexHolder;
+        BaseType_t xReturn = pdFALSE;
+
+        traceENTER_xTaskPriorityDisinherit( pxMutexHolder );
+
+        if( pxMutexHolder != NULL )
+        {
+            /* A task can only have an inherited priority if it holds the mutex.
+             * If the mutex is held by a task then it cannot be given from an
+             * interrupt, and if a mutex is given by the holding task then it must
+             * be the running state task. */
+            configASSERT( pxTCB == pxCurrentTCB );
+            configASSERT( pxTCB->uxMutexesHeld );
+            ( pxTCB->uxMutexesHeld )--;
+
+            /* Has the holder of the mutex inherited the priority of another
+             * task? */
+            if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+            {
+                /* Only disinherit if no other mutexes are held. */
+                if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+                {
+                    /* A task can only have an inherited priority if it holds
+                     * the mutex.  If the mutex is held by a task then it cannot be
+                     * given from an interrupt, and if a mutex is given by the
+                     * holding task then it must be the running state task.  Remove
+                     * the holding task from the ready list. */
+                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                    {
+                        portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Disinherit the priority before adding the task into the
+                     * new  ready list. */
+                    traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+                    pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+                    /* Reset the event list item value.  It cannot be in use for
+                     * any other purpose if this task is running, and it must be
+                     * running to give back the mutex. */
+                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority );
+                    prvAddTaskToReadyList( pxTCB );
+                    #if ( configNUMBER_OF_CORES > 1 )
+                    {
+                        /* The priority of the task is dropped. Yield the core on
+                         * which the task is running. */
+                        if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                        {
+                            prvYieldCore( pxTCB->xTaskRunState );
+                        }
+                    }
+                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
+                    /* Return true to indicate that a context switch is required.
+                     * This is only actually required in the corner case whereby
+                     * multiple mutexes were held and the mutexes were given back
+                     * in an order different to that in which they were taken.
+                     * If a context switch did not occur when the first mutex was
+                     * returned, even if a task was waiting on it, then a context
+                     * switch should occur when the last mutex is returned whether
+                     * a task is waiting on it or not. */
+                    xReturn = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xTaskPriorityDisinherit( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
+                                              UBaseType_t uxHighestPriorityWaitingTask )
+    {
+        TCB_t * const pxTCB = pxMutexHolder;
+        UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+        const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+        traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask );
+
+        if( pxMutexHolder != NULL )
+        {
+            /* If pxMutexHolder is not NULL then the holder must hold at least
+             * one mutex. */
+            configASSERT( pxTCB->uxMutexesHeld );
+
+            /* Determine the priority to which the priority of the task that
+             * holds the mutex should be set.  This will be the greater of the
+             * holding task's base priority and the priority of the highest
+             * priority task that is waiting to obtain the mutex. */
+            if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+            {
+                uxPriorityToUse = uxHighestPriorityWaitingTask;
+            }
+            else
+            {
+                uxPriorityToUse = pxTCB->uxBasePriority;
+            }
+
+            /* Does the priority need to change? */
+            if( pxTCB->uxPriority != uxPriorityToUse )
+            {
+                /* Only disinherit if no other mutexes are held.  This is a
+                 * simplification in the priority inheritance implementation.  If
+                 * the task that holds the mutex is also holding other mutexes then
+                 * the other mutexes may have caused the priority inheritance. */
+                if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+                {
+                    /* If a task has timed out because it already holds the
+                     * mutex it was trying to obtain then it cannot of inherited
+                     * its own priority. */
+                    configASSERT( pxTCB != pxCurrentTCB );
+
+                    /* Disinherit the priority, remembering the previous
+                     * priority to facilitate determining the subject task's
+                     * state. */
+                    traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse );
+                    uxPriorityUsedOnEntry = pxTCB->uxPriority;
+                    pxTCB->uxPriority = uxPriorityToUse;
+
+                    /* Only reset the event list item value if the value is not
+                     * being used for anything else. */
+                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
+                    {
+                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* If the running task is not the task that holds the mutex
+                     * then the task that holds the mutex could be in either the
+                     * Ready, Blocked or Suspended states.  Only remove the task
+                     * from its current state list if it is in the Ready state as
+                     * the task's priority is going to change and there is one
+                     * Ready list per priority. */
+                    if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+                    {
+                        if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                        {
+                            /* It is known that the task is in its ready list so
+                             * there is no need to check again and the port level
+                             * reset macro can be called directly. */
+                            portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        prvAddTaskToReadyList( pxTCB );
+                        #if ( configNUMBER_OF_CORES > 1 )
+                        {
+                            /* The priority of the task is dropped. Yield the core on
+                             * which the task is running. */
+                            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                            {
+                                prvYieldCore( pxTCB->xTaskRunState );
+                            }
+                        }
+                        #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskPriorityDisinheritAfterTimeout();
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* If not in a critical section then yield immediately.
+ * Otherwise set xYieldPendings to true to wait to
+ * yield until exiting the critical section.
+ */
+    void vTaskYieldWithinAPI( void )
+    {
+        traceENTER_vTaskYieldWithinAPI();
+
+        if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+        {
+            portYIELD();
+        }
+        else
+        {
+            xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
+        }
+
+        traceRETURN_vTaskYieldWithinAPI();
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )
+
+    void vTaskEnterCritical( void )
+    {
+        traceENTER_vTaskEnterCritical();
+
+        portDISABLE_INTERRUPTS();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            ( pxCurrentTCB->uxCriticalNesting )++;
+
+            /* This is not the interrupt safe version of the enter critical
+             * function so  assert() if it is being called from an interrupt
+             * context.  Only API functions that end in "FromISR" can be used in an
+             * interrupt.  Only assert if the critical nesting count is 1 to
+             * protect against recursive calls if the assert function also uses a
+             * critical section. */
+            if( pxCurrentTCB->uxCriticalNesting == 1U )
+            {
+                portASSERT_IF_IN_ISR();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskEnterCritical();
+    }
+
+#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    void vTaskEnterCritical( void )
+    {
+        traceENTER_vTaskEnterCritical();
+
+        portDISABLE_INTERRUPTS();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+            {
+                portGET_TASK_LOCK();
+                portGET_ISR_LOCK();
+            }
+
+            portINCREMENT_CRITICAL_NESTING_COUNT();
+
+            /* This is not the interrupt safe version of the enter critical
+             * function so  assert() if it is being called from an interrupt
+             * context.  Only API functions that end in "FromISR" can be used in an
+             * interrupt.  Only assert if the critical nesting count is 1 to
+             * protect against recursive calls if the assert function also uses a
+             * critical section. */
+            if( portGET_CRITICAL_NESTING_COUNT() == 1U )
+            {
+                portASSERT_IF_IN_ISR();
+
+                if( uxSchedulerSuspended == 0U )
+                {
+                    /* The only time there would be a problem is if this is called
+                     * before a context switch and vTaskExitCritical() is called
+                     * after pxCurrentTCB changes. Therefore this should not be
+                     * used within vTaskSwitchContext(). */
+                    prvCheckForRunStateChange();
+                }
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskEnterCritical();
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    UBaseType_t vTaskEnterCriticalFromISR( void )
+    {
+        UBaseType_t uxSavedInterruptStatus = 0;
+
+        traceENTER_vTaskEnterCriticalFromISR();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+            {
+                portGET_ISR_LOCK();
+            }
+
+            portINCREMENT_CRITICAL_NESTING_COUNT();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus );
+
+        return uxSavedInterruptStatus;
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )
+
+    void vTaskExitCritical( void )
+    {
+        traceENTER_vTaskExitCritical();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* If pxCurrentTCB->uxCriticalNesting is zero then this function
+             * does not match a previous call to vTaskEnterCritical(). */
+            configASSERT( pxCurrentTCB->uxCriticalNesting > 0U );
+
+            /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
+             * to exit critical section from ISR. */
+            portASSERT_IF_IN_ISR();
+
+            if( pxCurrentTCB->uxCriticalNesting > 0U )
+            {
+                ( pxCurrentTCB->uxCriticalNesting )--;
+
+                if( pxCurrentTCB->uxCriticalNesting == 0U )
+                {
+                    portENABLE_INTERRUPTS();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskExitCritical();
+    }
+
+#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    void vTaskExitCritical( void )
+    {
+        traceENTER_vTaskExitCritical();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* If critical nesting count is zero then this function
+             * does not match a previous call to vTaskEnterCritical(). */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+
+            /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
+             * to exit critical section from ISR. */
+            portASSERT_IF_IN_ISR();
+
+            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
+            {
+                portDECREMENT_CRITICAL_NESTING_COUNT();
+
+                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                {
+                    BaseType_t xYieldCurrentTask;
+
+                    /* Get the xYieldPending stats inside the critical section. */
+                    xYieldCurrentTask = xYieldPendings[ portGET_CORE_ID() ];
+
+                    portRELEASE_ISR_LOCK();
+                    portRELEASE_TASK_LOCK();
+                    portENABLE_INTERRUPTS();
+
+                    /* When a task yields in a critical section it just sets
+                     * xYieldPending to true. So now that we have exited the
+                     * critical section check if xYieldPending is true, and
+                     * if so yield. */
+                    if( xYieldCurrentTask != pdFALSE )
+                    {
+                        portYIELD();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskExitCritical();
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus )
+    {
+        traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus );
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* If critical nesting count is zero then this function
+             * does not match a previous call to vTaskEnterCritical(). */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+
+            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
+            {
+                portDECREMENT_CRITICAL_NESTING_COUNT();
+
+                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                {
+                    portRELEASE_ISR_LOCK();
+                    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskExitCriticalFromISR();
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
+
+    static char * prvWriteNameToBuffer( char * pcBuffer,
+                                        const char * pcTaskName )
+    {
+        size_t x;
+
+        /* Start by copying the entire string. */
+        ( void ) strcpy( pcBuffer, pcTaskName );
+
+        /* Pad the end of the string with spaces to ensure columns line up when
+         * printed out. */
+        for( x = strlen( pcBuffer ); x < ( size_t ) ( ( size_t ) configMAX_TASK_NAME_LEN - 1U ); x++ )
+        {
+            pcBuffer[ x ] = ' ';
+        }
+
+        /* Terminate. */
+        pcBuffer[ x ] = ( char ) 0x00;
+
+        /* Return the new end of string. */
+        return &( pcBuffer[ x ] );
+    }
+
+#endif /* ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+    void vTaskListTasks( char * pcWriteBuffer,
+                         size_t uxBufferLength )
+    {
+        TaskStatus_t * pxTaskStatusArray;
+        size_t uxConsumedBufferLength = 0;
+        size_t uxCharsWrittenBySnprintf;
+        int iSnprintfReturnValue;
+        BaseType_t xOutputBufferFull = pdFALSE;
+        UBaseType_t uxArraySize, x;
+        char cStatus;
+
+        traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength );
+
+        /*
+         * PLEASE NOTE:
+         *
+         * This function is provided for convenience only, and is used by many
+         * of the demo applications.  Do not consider it to be part of the
+         * scheduler.
+         *
+         * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
+         * uxTaskGetSystemState() output into a human readable table that
+         * displays task: names, states, priority, stack usage and task number.
+         * Stack usage specified as the number of unused StackType_t words stack can hold
+         * on top of stack - not the number of bytes.
+         *
+         * vTaskListTasks() has a dependency on the snprintf() C library function that
+         * might bloat the code size, use a lot of stack, and provide different
+         * results on different platforms.  An alternative, tiny, third party,
+         * and limited functionality implementation of snprintf() is provided in
+         * many of the FreeRTOS/Demo sub-directories in a file called
+         * printf-stdarg.c (note printf-stdarg.c does not provide a full
+         * snprintf() implementation!).
+         *
+         * It is recommended that production systems call uxTaskGetSystemState()
+         * directly to get access to raw stats data, rather than indirectly
+         * through a call to vTaskListTasks().
+         */
+
+
+        /* Make sure the write buffer does not contain a string. */
+        *pcWriteBuffer = ( char ) 0x00;
+
+        /* Take a snapshot of the number of tasks in case it changes while this
+         * function is executing. */
+        uxArraySize = uxCurrentNumberOfTasks;
+
+        /* Allocate an array index for each task.  NOTE!  if
+         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+         * equate to NULL. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+        if( pxTaskStatusArray != NULL )
+        {
+            /* Generate the (binary) data. */
+            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+            /* Create a human readable table from the binary data. */
+            for( x = 0; x < uxArraySize; x++ )
+            {
+                switch( pxTaskStatusArray[ x ].eCurrentState )
+                {
+                    case eRunning:
+                        cStatus = tskRUNNING_CHAR;
+                        break;
+
+                    case eReady:
+                        cStatus = tskREADY_CHAR;
+                        break;
+
+                    case eBlocked:
+                        cStatus = tskBLOCKED_CHAR;
+                        break;
+
+                    case eSuspended:
+                        cStatus = tskSUSPENDED_CHAR;
+                        break;
+
+                    case eDeleted:
+                        cStatus = tskDELETED_CHAR;
+                        break;
+
+                    case eInvalid: /* Fall through. */
+                    default:       /* Should not get here, but it is included
+                                    * to prevent static checking errors. */
+                        cStatus = ( char ) 0x00;
+                        break;
+                }
+
+                /* Is there enough space in the buffer to hold task name? */
+                if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
+                {
+                    /* Write the task name to the string, padding with spaces so it
+                     * can be printed in tabular form more easily. */
+                    pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+                    /* Do not count the terminating null character. */
+                    uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );
+
+                    /* Is there space left in the buffer? -1 is done because snprintf
+                     * writes a terminating null character. So we are essentially
+                     * checking if the buffer has space to write at least one non-null
+                     * character. */
+                    if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
+                    {
+                        /* Write the rest of the string. */
+                        #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+                            /* MISRA Ref 21.6.1 [snprintf for utility] */
+                            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                            /* coverity[misra_c_2012_rule_21_6_violation] */
+                            iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                             uxBufferLength - uxConsumedBufferLength,
+                                                             "\t%c\t%u\t%u\t%u\t0x%x\r\n",
+                                                             cStatus,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask );
+                        #else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
+                            /* MISRA Ref 21.6.1 [snprintf for utility] */
+                            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                            /* coverity[misra_c_2012_rule_21_6_violation] */
+                            iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                             uxBufferLength - uxConsumedBufferLength,
+                                                             "\t%c\t%u\t%u\t%u\r\n",
+                                                             cStatus,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
+                        #endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
+                        uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
+
+                        uxConsumedBufferLength += uxCharsWrittenBySnprintf;
+                        pcWriteBuffer += uxCharsWrittenBySnprintf;
+                    }
+                    else
+                    {
+                        xOutputBufferFull = pdTRUE;
+                    }
+                }
+                else
+                {
+                    xOutputBufferFull = pdTRUE;
+                }
+
+                if( xOutputBufferFull == pdTRUE )
+                {
+                    break;
+                }
+            }
+
+            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+             * is 0 then vPortFree() will be #defined to nothing. */
+            vPortFree( pxTaskStatusArray );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskListTasks();
+    }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+
+    void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                    size_t uxBufferLength )
+    {
+        TaskStatus_t * pxTaskStatusArray;
+        size_t uxConsumedBufferLength = 0;
+        size_t uxCharsWrittenBySnprintf;
+        int iSnprintfReturnValue;
+        BaseType_t xOutputBufferFull = pdFALSE;
+        UBaseType_t uxArraySize, x;
+        configRUN_TIME_COUNTER_TYPE ulTotalTime = 0;
+        configRUN_TIME_COUNTER_TYPE ulStatsAsPercentage;
+
+        traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
+
+        /*
+         * PLEASE NOTE:
+         *
+         * This function is provided for convenience only, and is used by many
+         * of the demo applications.  Do not consider it to be part of the
+         * scheduler.
+         *
+         * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part
+         * of the uxTaskGetSystemState() output into a human readable table that
+         * displays the amount of time each task has spent in the Running state
+         * in both absolute and percentage terms.
+         *
+         * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library
+         * function that might bloat the code size, use a lot of stack, and
+         * provide different results on different platforms.  An alternative,
+         * tiny, third party, and limited functionality implementation of
+         * snprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+         * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+         * a full snprintf() implementation!).
+         *
+         * It is recommended that production systems call uxTaskGetSystemState()
+         * directly to get access to raw stats data, rather than indirectly
+         * through a call to vTaskGetRunTimeStatistics().
+         */
+
+        /* Make sure the write buffer does not contain a string. */
+        *pcWriteBuffer = ( char ) 0x00;
+
+        /* Take a snapshot of the number of tasks in case it changes while this
+         * function is executing. */
+        uxArraySize = uxCurrentNumberOfTasks;
+
+        /* Allocate an array index for each task.  NOTE!  If
+         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+         * equate to NULL. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+        if( pxTaskStatusArray != NULL )
+        {
+            /* Generate the (binary) data. */
+            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+            /* For percentage calculations. */
+            ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100UL );
+
+            /* Avoid divide by zero errors. */
+            if( ulTotalTime > 0UL )
+            {
+                /* Create a human readable table from the binary data. */
+                for( x = 0; x < uxArraySize; x++ )
+                {
+                    /* What percentage of the total run time has the task used?
+                     * This will always be rounded down to the nearest integer.
+                     * ulTotalRunTime has already been divided by 100. */
+                    ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+                    /* Is there enough space in the buffer to hold task name? */
+                    if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
+                    {
+                        /* Write the task name to the string, padding with
+                         * spaces so it can be printed in tabular form more
+                         * easily. */
+                        pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+                        /* Do not count the terminating null character. */
+                        uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );
+
+                        /* Is there space left in the buffer? -1 is done because snprintf
+                         * writes a terminating null character. So we are essentially
+                         * checking if the buffer has space to write at least one non-null
+                         * character. */
+                        if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
+                        {
+                            if( ulStatsAsPercentage > 0UL )
+                            {
+                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+                                {
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%lu\t\t%lu%%\r\n",
+                                                                     pxTaskStatusArray[ x ].ulRunTimeCounter,
+                                                                     ulStatsAsPercentage );
+                                }
+                                #else /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+                                {
+                                    /* sizeof( int ) == sizeof( long ) so a smaller
+                                     * printf() library can be used. */
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%u\t\t%u%%\r\n",
+                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter,
+                                                                     ( unsigned int ) ulStatsAsPercentage );
+                                }
+                                #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+                            }
+                            else
+                            {
+                                /* If the percentage is zero here then the task has
+                                 * consumed less than 1% of the total run time. */
+                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+                                {
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%lu\t\t<1%%\r\n",
+                                                                     pxTaskStatusArray[ x ].ulRunTimeCounter );
+                                }
+                                #else
+                                {
+                                    /* sizeof( int ) == sizeof( long ) so a smaller
+                                     * printf() library can be used. */
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%u\t\t<1%%\r\n",
+                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+                                }
+                                #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+                            }
+
+                            uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
+                            uxConsumedBufferLength += uxCharsWrittenBySnprintf;
+                            pcWriteBuffer += uxCharsWrittenBySnprintf;
+                        }
+                        else
+                        {
+                            xOutputBufferFull = pdTRUE;
+                        }
+                    }
+                    else
+                    {
+                        xOutputBufferFull = pdTRUE;
+                    }
+
+                    if( xOutputBufferFull == pdTRUE )
+                    {
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+             * is 0 then vPortFree() will be #defined to nothing. */
+            vPortFree( pxTaskStatusArray );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_vTaskGetRunTimeStatistics();
+    }
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+    TickType_t uxReturn;
+
+    traceENTER_uxTaskResetEventItemValue();
+
+    uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+    /* Reset the event list item to its normal value - so it can be used with
+     * queues and semaphores. */
+    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) );
+
+    traceRETURN_uxTaskResetEventItemValue( uxReturn );
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_pvTaskIncrementMutexHeldCount();
+
+        pxTCB = pxCurrentTCB;
+
+        /* If xSemaphoreCreateMutex() is called before any tasks have been created
+         * then pxCurrentTCB will be NULL. */
+        if( pxTCB != NULL )
+        {
+            ( pxTCB->uxMutexesHeld )++;
+        }
+
+        traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB );
+
+        return pxTCB;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                      BaseType_t xClearCountOnExit,
+                                      TickType_t xTicksToWait )
+    {
+        uint32_t ulReturn;
+        BaseType_t xAlreadyYielded;
+
+        traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
+
+        configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        taskENTER_CRITICAL();
+
+        /* Only block if the notification count is not already non-zero. */
+        if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL )
+        {
+            /* Mark this task as waiting for a notification. */
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+
+            if( xTicksToWait > ( TickType_t ) 0 )
+            {
+                traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
+
+                /* We MUST suspend the scheduler before exiting the critical
+                 * section (i.e. before enabling interrupts).
+                 *
+                 * If we do not do so, a notification sent from an ISR, which
+                 * happens after exiting the critical section and before
+                 * suspending the scheduler, will get lost. The sequence of
+                 * events will be:
+                 * 1. Exit critical section.
+                 * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the Ready list.
+                 * 3. Suspend scheduler.
+                 * 4. prvAddCurrentTaskToDelayedList moves the task to the
+                 *    delayed or suspended list.
+                 * 5. Resume scheduler does not touch the task (because it is
+                 *    not on the pendingReady list), effectively losing the
+                 *    notification from the ISR.
+                 *
+                 * The same does not happen when we suspend the scheduler before
+                 * exiting the critical section. The sequence of events in this
+                 * case will be:
+                 * 1. Suspend scheduler.
+                 * 2. Exit critical section.
+                 * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the pendingReady list as the scheduler is
+                 *    suspended.
+                 * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or
+                 *    suspended list. Note that this operation does not nullify
+                 *    the add to pendingReady list done in the above step because
+                 *    a different list item, namely xEventListItem, is used for
+                 *    adding the task to the pendingReady list. In other words,
+                 *    the task still remains on the pendingReady list.
+                 * 5. Resume scheduler moves the task from pendingReady list to
+                 *    the Ready list.
+                 */
+                vTaskSuspendAll();
+                {
+                    taskEXIT_CRITICAL();
+
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                }
+                xAlreadyYielded = xTaskResumeAll();
+
+                if( xAlreadyYielded == pdFALSE )
+                {
+                    taskYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                taskEXIT_CRITICAL();
+            }
+        }
+        else
+        {
+            taskEXIT_CRITICAL();
+        }
+
+        taskENTER_CRITICAL();
+        {
+            traceTASK_NOTIFY_TAKE( uxIndexToWaitOn );
+            ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
+
+            if( ulReturn != 0UL )
+            {
+                if( xClearCountOnExit != pdFALSE )
+                {
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0UL;
+                }
+                else
+                {
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ulReturn - ( uint32_t ) 1;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_ulTaskGenericNotifyTake( ulReturn );
+
+        return ulReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                       uint32_t ulBitsToClearOnEntry,
+                                       uint32_t ulBitsToClearOnExit,
+                                       uint32_t * pulNotificationValue,
+                                       TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn, xAlreadyYielded;
+
+        traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+
+        configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        taskENTER_CRITICAL();
+
+        /* Only block if a notification is not already pending. */
+        if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
+        {
+            /* Clear bits in the task's notification value as bits may get
+             * set  by the notifying task or interrupt.  This can be used to
+             * clear the value to zero. */
+            pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
+
+            /* Mark this task as waiting for a notification. */
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+
+            if( xTicksToWait > ( TickType_t ) 0 )
+            {
+                traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
+
+                /* We MUST suspend the scheduler before exiting the critical
+                 * section (i.e. before enabling interrupts).
+                 *
+                 * If we do not do so, a notification sent from an ISR, which
+                 * happens after exiting the critical section and before
+                 * suspending the scheduler, will get lost. The sequence of
+                 * events will be:
+                 * 1. Exit critical section.
+                 * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the Ready list.
+                 * 3. Suspend scheduler.
+                 * 4. prvAddCurrentTaskToDelayedList moves the task to the
+                 *    delayed or suspended list.
+                 * 5. Resume scheduler does not touch the task (because it is
+                 *    not on the pendingReady list), effectively losing the
+                 *    notification from the ISR.
+                 *
+                 * The same does not happen when we suspend the scheduler before
+                 * exiting the critical section. The sequence of events in this
+                 * case will be:
+                 * 1. Suspend scheduler.
+                 * 2. Exit critical section.
+                 * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the pendingReady list as the scheduler is
+                 *    suspended.
+                 * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or
+                 *    suspended list. Note that this operation does not nullify
+                 *    the add to pendingReady list done in the above step because
+                 *    a different list item, namely xEventListItem, is used for
+                 *    adding the task to the pendingReady list. In other words,
+                 *    the task still remains on the pendingReady list.
+                 * 5. Resume scheduler moves the task from pendingReady list to
+                 *    the Ready list.
+                 */
+                vTaskSuspendAll();
+                {
+                    taskEXIT_CRITICAL();
+
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                }
+                xAlreadyYielded = xTaskResumeAll();
+
+                if( xAlreadyYielded == pdFALSE )
+                {
+                    taskYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                taskEXIT_CRITICAL();
+            }
+        }
+        else
+        {
+            taskEXIT_CRITICAL();
+        }
+
+        taskENTER_CRITICAL();
+        {
+            traceTASK_NOTIFY_WAIT( uxIndexToWaitOn );
+
+            if( pulNotificationValue != NULL )
+            {
+                /* Output the current notification value, which may or may not
+                 * have changed. */
+                *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
+            }
+
+            /* If ucNotifyValue is set then either the task never entered the
+             * blocked state (because a notification was already pending) or the
+             * task unblocked because of a notification.  Otherwise the task
+             * unblocked because of a timeout. */
+            if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
+            {
+                /* A notification was not received. */
+                xReturn = pdFALSE;
+            }
+            else
+            {
+                /* A notification was already pending or a notification was
+                 * received while the task was waiting. */
+                pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnExit;
+                xReturn = pdTRUE;
+            }
+
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xTaskGenericNotifyWait( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                   UBaseType_t uxIndexToNotify,
+                                   uint32_t ulValue,
+                                   eNotifyAction eAction,
+                                   uint32_t * pulPreviousNotificationValue )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xReturn = pdPASS;
+        uint8_t ucOriginalNotifyState;
+
+        traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+
+        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+        configASSERT( xTaskToNotify );
+        pxTCB = xTaskToNotify;
+
+        taskENTER_CRITICAL();
+        {
+            if( pulPreviousNotificationValue != NULL )
+            {
+                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
+            }
+
+            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
+
+            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
+
+            switch( eAction )
+            {
+                case eSetBits:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
+                    break;
+
+                case eIncrement:
+                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
+                    break;
+
+                case eSetValueWithOverwrite:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    break;
+
+                case eSetValueWithoutOverwrite:
+
+                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+                    {
+                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    }
+                    else
+                    {
+                        /* The value could not be written to the task. */
+                        xReturn = pdFAIL;
+                    }
+
+                    break;
+
+                case eNoAction:
+
+                    /* The task is being notified without its notify value being
+                     * updated. */
+                    break;
+
+                default:
+
+                    /* Should not get here if all enums are handled.
+                     * Artificially force an assert by testing a value the
+                     * compiler can't assume is const. */
+                    configASSERT( xTickCount == ( TickType_t ) 0 );
+
+                    break;
+            }
+
+            traceTASK_NOTIFY( uxIndexToNotify );
+
+            /* If the task is in the blocked state specifically to wait for a
+             * notification then unblock it now. */
+            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+            {
+                listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
+                prvAddTaskToReadyList( pxTCB );
+
+                /* The task should not have been on an event list. */
+                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+                #if ( configUSE_TICKLESS_IDLE != 0 )
+                {
+                    /* If a task is blocked waiting for a notification then
+                     * xNextTaskUnblockTime might be set to the blocked task's time
+                     * out time.  If the task is unblocked for a reason other than
+                     * a timeout xNextTaskUnblockTime is normally left unchanged,
+                     * because it will automatically get reset to a new value when
+                     * the tick count equals xNextTaskUnblockTime.  However if
+                     * tickless idling is used it might be more important to enter
+                     * sleep mode at the earliest possible time - so reset
+                     * xNextTaskUnblockTime here to ensure it is updated at the
+                     * earliest possible time. */
+                    prvResetNextTaskUnblockTime();
+                }
+                #endif
+
+                /* Check if the notified task has a priority above the currently
+                 * executing task. */
+                taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xTaskGenericNotify( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
+                                          UBaseType_t uxIndexToNotify,
+                                          uint32_t ulValue,
+                                          eNotifyAction eAction,
+                                          uint32_t * pulPreviousNotificationValue,
+                                          BaseType_t * pxHigherPriorityTaskWoken )
+    {
+        TCB_t * pxTCB;
+        uint8_t ucOriginalNotifyState;
+        BaseType_t xReturn = pdPASS;
+        UBaseType_t uxSavedInterruptStatus;
+
+        traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken );
+
+        configASSERT( xTaskToNotify );
+        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        pxTCB = xTaskToNotify;
+
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            if( pulPreviousNotificationValue != NULL )
+            {
+                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
+            }
+
+            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
+            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
+
+            switch( eAction )
+            {
+                case eSetBits:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
+                    break;
+
+                case eIncrement:
+                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
+                    break;
+
+                case eSetValueWithOverwrite:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    break;
+
+                case eSetValueWithoutOverwrite:
+
+                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+                    {
+                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    }
+                    else
+                    {
+                        /* The value could not be written to the task. */
+                        xReturn = pdFAIL;
+                    }
+
+                    break;
+
+                case eNoAction:
+
+                    /* The task is being notified without its notify value being
+                     * updated. */
+                    break;
+
+                default:
+
+                    /* Should not get here if all enums are handled.
+                     * Artificially force an assert by testing a value the
+                     * compiler can't assume is const. */
+                    configASSERT( xTickCount == ( TickType_t ) 0 );
+                    break;
+            }
+
+            traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify );
+
+            /* If the task is in the blocked state specifically to wait for a
+             * notification then unblock it now. */
+            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+            {
+                /* The task should not have been on an event list. */
+                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+                {
+                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    /* The delayed and ready lists cannot be accessed, so hold
+                     * this task pending until the scheduler is resumed. */
+                    listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+                }
+
+                #if ( configNUMBER_OF_CORES == 1 )
+                {
+                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                    {
+                        /* The notified task has a priority above the currently
+                         * executing task so a yield is required. */
+                        if( pxHigherPriorityTaskWoken != NULL )
+                        {
+                            *pxHigherPriorityTaskWoken = pdTRUE;
+                        }
+
+                        /* Mark that a yield is pending in case the user is not
+                         * using the "xHigherPriorityTaskWoken" parameter to an ISR
+                         * safe FreeRTOS function. */
+                        xYieldPendings[ 0 ] = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                {
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        prvYieldForTask( pxTCB );
+
+                        if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
+                        {
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                        }
+                    }
+                    #endif /* if ( configUSE_PREEMPTION == 1 ) */
+                }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+            }
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_xTaskGenericNotifyFromISR( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
+                                        UBaseType_t uxIndexToNotify,
+                                        BaseType_t * pxHigherPriorityTaskWoken )
+    {
+        TCB_t * pxTCB;
+        uint8_t ucOriginalNotifyState;
+        UBaseType_t uxSavedInterruptStatus;
+
+        traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken );
+
+        configASSERT( xTaskToNotify );
+        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        pxTCB = xTaskToNotify;
+
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
+            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
+
+            /* 'Giving' is equivalent to incrementing a count in a counting
+             * semaphore. */
+            ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
+
+            traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify );
+
+            /* If the task is in the blocked state specifically to wait for a
+             * notification then unblock it now. */
+            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+            {
+                /* The task should not have been on an event list. */
+                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+                {
+                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    /* The delayed and ready lists cannot be accessed, so hold
+                     * this task pending until the scheduler is resumed. */
+                    listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+                }
+
+                #if ( configNUMBER_OF_CORES == 1 )
+                {
+                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                    {
+                        /* The notified task has a priority above the currently
+                         * executing task so a yield is required. */
+                        if( pxHigherPriorityTaskWoken != NULL )
+                        {
+                            *pxHigherPriorityTaskWoken = pdTRUE;
+                        }
+
+                        /* Mark that a yield is pending in case the user is not
+                         * using the "xHigherPriorityTaskWoken" parameter in an ISR
+                         * safe FreeRTOS function. */
+                        xYieldPendings[ 0 ] = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                {
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        prvYieldForTask( pxTCB );
+
+                        if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
+                        {
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                        }
+                    }
+                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
+                }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+            }
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_vTaskGenericNotifyGiveFromISR();
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                             UBaseType_t uxIndexToClear )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
+
+        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        /* If null is passed in here then it is the calling task that is having
+         * its notification state cleared. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED )
+            {
+                pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION;
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xTaskGenericNotifyStateClear( xReturn );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                            UBaseType_t uxIndexToClear,
+                                            uint32_t ulBitsToClear )
+    {
+        TCB_t * pxTCB;
+        uint32_t ulReturn;
+
+        traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
+
+        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        /* If null is passed in here then it is the calling task that is having
+         * its notification state cleared. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            /* Return the notification as it was before the bits were cleared,
+             * then clear the bit mask. */
+            ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ];
+            pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_ulTaskGenericNotifyValueClear( ulReturn );
+
+        return ulReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_ulTaskGetRunTimeCounter( xTask );
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        traceRETURN_ulTaskGetRunTimeCounter( pxTCB->ulRunTimeCounter );
+
+        return pxTCB->ulRunTimeCounter;
+    }
+
+#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
+
+        traceENTER_ulTaskGetRunTimePercent( xTask );
+
+        ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+
+        /* For percentage calculations. */
+        ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
+
+        /* Avoid divide by zero errors. */
+        if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+            ulReturn = pxTCB->ulRunTimeCounter / ulTotalTime;
+        }
+        else
+        {
+            ulReturn = 0;
+        }
+
+        traceRETURN_ulTaskGetRunTimePercent( ulReturn );
+
+        return ulReturn;
+    }
+
+#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void )
+    {
+        configRUN_TIME_COUNTER_TYPE ulReturn = 0;
+        BaseType_t i;
+
+        traceENTER_ulTaskGetIdleRunTimeCounter();
+
+        for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
+        {
+            ulReturn += xIdleTaskHandles[ i ]->ulRunTimeCounter;
+        }
+
+        traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn );
+
+        return ulReturn;
+    }
+
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void )
+    {
+        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
+        configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0;
+        BaseType_t i;
+
+        traceENTER_ulTaskGetIdleRunTimePercent();
+
+        ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE() * configNUMBER_OF_CORES;
+
+        /* For percentage calculations. */
+        ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
+
+        /* Avoid divide by zero errors. */
+        if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
+        {
+            for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
+            {
+                ulRunTimeCounter += xIdleTaskHandles[ i ]->ulRunTimeCounter;
+            }
+
+            ulReturn = ulRunTimeCounter / ulTotalTime;
+        }
+        else
+        {
+            ulReturn = 0;
+        }
+
+        traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn );
+
+        return ulReturn;
+    }
+
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
+                                            const BaseType_t xCanBlockIndefinitely )
+{
+    TickType_t xTimeToWake;
+    const TickType_t xConstTickCount = xTickCount;
+    List_t * const pxDelayedList = pxDelayedTaskList;
+    List_t * const pxOverflowDelayedList = pxOverflowDelayedTaskList;
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+    {
+        /* About to enter a delayed list, so ensure the ucDelayAborted flag is
+         * reset to pdFALSE so it can be detected as having been set to pdTRUE
+         * when the task leaves the Blocked state. */
+        pxCurrentTCB->ucDelayAborted = pdFALSE;
+    }
+    #endif
+
+    /* Remove the task from the ready list before adding it to the blocked list
+     * as the same list item is used for both lists. */
+    if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+    {
+        /* The current task must be in a ready list, so there is no need to
+         * check, and the port reset macro can be called directly. */
+        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+    {
+        if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+        {
+            /* Add the task to the suspended task list instead of a delayed task
+             * list to ensure it is not woken by a timing event.  It will block
+             * indefinitely. */
+            listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+        }
+        else
+        {
+            /* Calculate the time at which the task should be woken if the event
+             * does not occur.  This may overflow but this doesn't matter, the
+             * kernel will manage it correctly. */
+            xTimeToWake = xConstTickCount + xTicksToWait;
+
+            /* The list item will be inserted in wake time order. */
+            listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+            if( xTimeToWake < xConstTickCount )
+            {
+                /* Wake time has overflowed.  Place this item in the overflow
+                 * list. */
+                traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
+                vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
+            }
+            else
+            {
+                /* The wake time has not overflowed, so the current block list
+                 * is used. */
+                traceMOVED_TASK_TO_DELAYED_LIST();
+                vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );
+
+                /* If the task entering the blocked state was placed at the
+                 * head of the list of blocked tasks then xNextTaskUnblockTime
+                 * needs to be updated too. */
+                if( xTimeToWake < xNextTaskUnblockTime )
+                {
+                    xNextTaskUnblockTime = xTimeToWake;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+    }
+    #else /* INCLUDE_vTaskSuspend */
+    {
+        /* Calculate the time at which the task should be woken if the event
+         * does not occur.  This may overflow but this doesn't matter, the kernel
+         * will manage it correctly. */
+        xTimeToWake = xConstTickCount + xTicksToWait;
+
+        /* The list item will be inserted in wake time order. */
+        listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+        if( xTimeToWake < xConstTickCount )
+        {
+            traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
+            /* Wake time has overflowed.  Place this item in the overflow list. */
+            vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
+        }
+        else
+        {
+            traceMOVED_TASK_TO_DELAYED_LIST();
+            /* The wake time has not overflowed, so the current block list is used. */
+            vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );
+
+            /* If the task entering the blocked state was placed at the head of the
+             * list of blocked tasks then xNextTaskUnblockTime needs to be updated
+             * too. */
+            if( xTimeToWake < xNextTaskUnblockTime )
+            {
+                xNextTaskUnblockTime = xTimeToWake;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+        ( void ) xCanBlockIndefinitely;
+    }
+    #endif /* INCLUDE_vTaskSuspend */
+}
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+    xMPU_SETTINGS * xTaskGetMPUSettings( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+
+        traceENTER_xTaskGetMPUSettings( xTask );
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) );
+
+        return &( pxTCB->xMPUSettings );
+    }
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+/* Code below here allows additional code to be inserted into this source file,
+ * especially where access to file scope functions and data is needed (for example
+ * when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+    #include "tasks_test_access_functions.h"
+#endif
+
+
+#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+    #include "freertos_tasks_c_additions.h"
+
+    #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+        static void freertos_tasks_c_additions_init( void )
+        {
+            FREERTOS_TASKS_C_ADDITIONS_INIT();
+        }
+    #endif
+
+#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+
+/*
+ * This is the kernel provided implementation of vApplicationGetIdleTaskMemory()
+ * to provide the memory that is used by the Idle task. It is used when
+ * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
+ * it's own implementation of vApplicationGetIdleTaskMemory by setting
+ * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
+ */
+    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                        StackType_t ** ppxIdleTaskStackBuffer,
+                                        uint32_t * pulIdleTaskStackSize )
+    {
+        static StaticTask_t xIdleTaskTCB;
+        static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+        *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
+        *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
+        *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+    }
+
+    #if ( configNUMBER_OF_CORES > 1 )
+
+        void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                                   StackType_t ** ppxIdleTaskStackBuffer,
+                                                   uint32_t * pulIdleTaskStackSize,
+                                                   BaseType_t xPassiveIdleTaskIndex )
+        {
+            static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ];
+            static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ];
+
+            *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xPassiveIdleTaskIndex ] );
+            *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] );
+            *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+        }
+
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+
+/*
+ * This is the kernel provided implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. It is used when
+ * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
+ * it's own implementation of vApplicationGetTimerTaskMemory by setting
+ * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
+ */
+    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+                                         StackType_t ** ppxTimerTaskStackBuffer,
+                                         uint32_t * pulTimerTaskStackSize )
+    {
+        static StaticTask_t xTimerTaskTCB;
+        static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
+
+        *ppxTimerTaskTCBBuffer = &( xTimerTaskTCB );
+        *ppxTimerTaskStackBuffer = &( uxTimerTaskStack[ 0 ] );
+        *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+    }
+
+#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/timers.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/timers.c
new file mode 100644
index 0000000000..46b9871dd4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/freertos/freertos-kernel/timers.c
@@ -0,0 +1,1328 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+    #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+
+/* This entire source file will be skipped if the application is not configured
+ * to include software timer functionality.  This #if is closed at the very bottom
+ * of this file.  If you want to include software timer functionality then ensure
+ * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+    #define tmrNO_DELAY                    ( ( TickType_t ) 0U )
+    #define tmrMAX_TIME_BEFORE_OVERFLOW    ( ( TickType_t ) -1 )
+
+/* The name assigned to the timer service task. This can be overridden by
+ * defining configTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+    #ifndef configTIMER_SERVICE_TASK_NAME
+        #define configTIMER_SERVICE_TASK_NAME    "Tmr Svc"
+    #endif
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+
+/* The core affinity assigned to the timer service task on SMP systems.
+ * This can be overridden by defining configTIMER_SERVICE_TASK_CORE_AFFINITY in FreeRTOSConfig.h. */
+        #ifndef configTIMER_SERVICE_TASK_CORE_AFFINITY
+            #define configTIMER_SERVICE_TASK_CORE_AFFINITY    tskNO_AFFINITY
+        #endif
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+    #define tmrSTATUS_IS_ACTIVE                  ( 0x01U )
+    #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( 0x02U )
+    #define tmrSTATUS_IS_AUTORELOAD              ( 0x04U )
+
+/* The definition of the timers themselves. */
+    typedef struct tmrTimerControl                                               /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+    {
+        const char * pcTimerName;                                                /**< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */
+        ListItem_t xTimerListItem;                                               /**< Standard linked list item as used by all kernel features for event management. */
+        TickType_t xTimerPeriodInTicks;                                          /**< How quickly and often the timer expires. */
+        void * pvTimerID;                                                        /**< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+        portTIMER_CALLBACK_ATTRIBUTE TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            UBaseType_t uxTimerNumber;                                           /**< An ID assigned by trace tools such as FreeRTOS+Trace */
+        #endif
+        uint8_t ucStatus;                                                        /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+    } xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+ * name below to enable the use of older kernel aware debuggers. */
+    typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+ * Two types of message can be queued - messages that manipulate a software timer,
+ * and messages that request the execution of a non-timer related callback.  The
+ * two message types are defined in two separate structures, xTimerParametersType
+ * and xCallbackParametersType respectively. */
+    typedef struct tmrTimerParameters
+    {
+        TickType_t xMessageValue; /**< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+        Timer_t * pxTimer;        /**< The timer to which the command will be applied. */
+    } TimerParameter_t;
+
+
+    typedef struct tmrCallbackParameters
+    {
+        portTIMER_CALLBACK_ATTRIBUTE
+        PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
+        void * pvParameter1;                 /* << The value that will be used as the callback functions first parameter. */
+        uint32_t ulParameter2;               /* << The value that will be used as the callback functions second parameter. */
+    } CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+ * that is used to determine which message type is valid. */
+    typedef struct tmrTimerQueueMessage
+    {
+        BaseType_t xMessageID; /**< The command being sent to the timer service task. */
+        union
+        {
+            TimerParameter_t xTimerParameters;
+
+            /* Don't include xCallbackParameters if it is not going to be used as
+             * it makes the structure (and therefore the timer queue) larger. */
+            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+                CallbackParameters_t xCallbackParameters;
+            #endif /* INCLUDE_xTimerPendFunctionCall */
+        } u;
+    } DaemonTaskMessage_t;
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+ * time order, with the nearest expiry time at the front of the list.  Only the
+ * timer service task is allowed to access these lists.
+ * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+ * breaks some kernel aware debuggers, and debuggers that reply on removing the
+ * static qualifier. */
+    PRIVILEGED_DATA static List_t xActiveTimerList1;
+    PRIVILEGED_DATA static List_t xActiveTimerList2;
+    PRIVILEGED_DATA static List_t * pxCurrentTimerList;
+    PRIVILEGED_DATA static List_t * pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+    PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+    PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+    static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+    static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+    static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
+                                                  const TickType_t xNextExpiryTime,
+                                                  const TickType_t xTimeNow,
+                                                  const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reload the specified auto-reload timer.  If the reloading is backlogged,
+ * clear the backlog, calling the callback for each additional reload.  When
+ * this function returns, the next expiry time is after xTimeNow.
+ */
+    static void prvReloadTimer( Timer_t * const pxTimer,
+                                TickType_t xExpiredTime,
+                                const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
+                                        const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+    static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
+                                            BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+    static void prvInitialiseNewTimer( const char * const pcTimerName,
+                                       const TickType_t xTimerPeriodInTicks,
+                                       const BaseType_t xAutoReload,
+                                       void * const pvTimerID,
+                                       TimerCallbackFunction_t pxCallbackFunction,
+                                       Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerCreateTimerTask( void )
+    {
+        BaseType_t xReturn = pdFAIL;
+
+        traceENTER_xTimerCreateTimerTask();
+
+        /* This function is called when the scheduler is started if
+         * configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+         * timer service task has been created/initialised.  If timers have already
+         * been created then the initialisation will already have been performed. */
+        prvCheckForValidListAndQueue();
+
+        if( xTimerQueue != NULL )
+        {
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+                    StackType_t * pxTimerTaskStackBuffer = NULL;
+                    uint32_t ulTimerTaskStackSize;
+
+                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+                    xTimerTaskHandle = xTaskCreateStaticAffinitySet( prvTimerTask,
+                                                                     configTIMER_SERVICE_TASK_NAME,
+                                                                     ulTimerTaskStackSize,
+                                                                     NULL,
+                                                                     ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                                                     pxTimerTaskStackBuffer,
+                                                                     pxTimerTaskTCBBuffer,
+                                                                     configTIMER_SERVICE_TASK_CORE_AFFINITY );
+
+                    if( xTimerTaskHandle != NULL )
+                    {
+                        xReturn = pdPASS;
+                    }
+                }
+                #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+                {
+                    xReturn = xTaskCreateAffinitySet( prvTimerTask,
+                                                      configTIMER_SERVICE_TASK_NAME,
+                                                      configTIMER_TASK_STACK_DEPTH,
+                                                      NULL,
+                                                      ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                                      configTIMER_SERVICE_TASK_CORE_AFFINITY,
+                                                      &xTimerTaskHandle );
+                }
+                #endif /* configSUPPORT_STATIC_ALLOCATION */
+            }
+            #else /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+            {
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+                    StackType_t * pxTimerTaskStackBuffer = NULL;
+                    uint32_t ulTimerTaskStackSize;
+
+                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+                    xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+                                                          configTIMER_SERVICE_TASK_NAME,
+                                                          ulTimerTaskStackSize,
+                                                          NULL,
+                                                          ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                                          pxTimerTaskStackBuffer,
+                                                          pxTimerTaskTCBBuffer );
+
+                    if( xTimerTaskHandle != NULL )
+                    {
+                        xReturn = pdPASS;
+                    }
+                }
+                #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+                {
+                    xReturn = xTaskCreate( prvTimerTask,
+                                           configTIMER_SERVICE_TASK_NAME,
+                                           configTIMER_TASK_STACK_DEPTH,
+                                           NULL,
+                                           ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                           &xTimerTaskHandle );
+                }
+                #endif /* configSUPPORT_STATIC_ALLOCATION */
+            }
+            #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        configASSERT( xReturn );
+
+        traceRETURN_xTimerCreateTimerTask( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+        TimerHandle_t xTimerCreate( const char * const pcTimerName,
+                                    const TickType_t xTimerPeriodInTicks,
+                                    const BaseType_t xAutoReload,
+                                    void * const pvTimerID,
+                                    TimerCallbackFunction_t pxCallbackFunction )
+        {
+            Timer_t * pxNewTimer;
+
+            traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction );
+
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+
+            if( pxNewTimer != NULL )
+            {
+                /* Status is thus far zero as the timer is not created statically
+                 * and has not been started.  The auto-reload bit may get set in
+                 * prvInitialiseNewTimer. */
+                pxNewTimer->ucStatus = 0x00;
+                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+            }
+
+            traceRETURN_xTimerCreate( pxNewTimer );
+
+            return pxNewTimer;
+        }
+
+    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+        TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
+                                          const TickType_t xTimerPeriodInTicks,
+                                          const BaseType_t xAutoReload,
+                                          void * const pvTimerID,
+                                          TimerCallbackFunction_t pxCallbackFunction,
+                                          StaticTimer_t * pxTimerBuffer )
+        {
+            Timer_t * pxNewTimer;
+
+            traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
+
+            #if ( configASSERT_DEFINED == 1 )
+            {
+                /* Sanity check that the size of the structure used to declare a
+                 * variable of type StaticTimer_t equals the size of the real timer
+                 * structure. */
+                volatile size_t xSize = sizeof( StaticTimer_t );
+                configASSERT( xSize == sizeof( Timer_t ) );
+                ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */
+            }
+            #endif /* configASSERT_DEFINED */
+
+            /* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+            configASSERT( pxTimerBuffer );
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            pxNewTimer = ( Timer_t * ) pxTimerBuffer;
+
+            if( pxNewTimer != NULL )
+            {
+                /* Timers can be created statically or dynamically so note this
+                 * timer was created statically in case it is later deleted.  The
+                 * auto-reload bit may get set in prvInitialiseNewTimer(). */
+                pxNewTimer->ucStatus = ( uint8_t ) tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+            }
+
+            traceRETURN_xTimerCreateStatic( pxNewTimer );
+
+            return pxNewTimer;
+        }
+
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+    static void prvInitialiseNewTimer( const char * const pcTimerName,
+                                       const TickType_t xTimerPeriodInTicks,
+                                       const BaseType_t xAutoReload,
+                                       void * const pvTimerID,
+                                       TimerCallbackFunction_t pxCallbackFunction,
+                                       Timer_t * pxNewTimer )
+    {
+        /* 0 is not a valid value for xTimerPeriodInTicks. */
+        configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+        /* Ensure the infrastructure used by the timer service task has been
+         * created/initialised. */
+        prvCheckForValidListAndQueue();
+
+        /* Initialise the timer structure members using the function
+         * parameters. */
+        pxNewTimer->pcTimerName = pcTimerName;
+        pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+        pxNewTimer->pvTimerID = pvTimerID;
+        pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+        vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+
+        if( xAutoReload != pdFALSE )
+        {
+            pxNewTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
+        }
+
+        traceTIMER_CREATE( pxNewTimer );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn = pdFAIL;
+        DaemonTaskMessage_t xMessage;
+
+        ( void ) pxHigherPriorityTaskWoken;
+
+        traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+
+        configASSERT( xTimer );
+
+        /* Send a message to the timer service task to perform a particular action
+         * on a particular timer definition. */
+        if( xTimerQueue != NULL )
+        {
+            /* Send a command to the timer service task to start the xTimer timer. */
+            xMessage.xMessageID = xCommandID;
+            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+            xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+            configASSERT( xCommandID < tmrFIRST_FROM_ISR_COMMAND );
+
+            if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+            {
+                if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+                {
+                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+                }
+                else
+                {
+                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+                }
+            }
+
+            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xTimerGenericCommandFromTask( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                            const BaseType_t xCommandID,
+                                            const TickType_t xOptionalValue,
+                                            BaseType_t * const pxHigherPriorityTaskWoken,
+                                            const TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn = pdFAIL;
+        DaemonTaskMessage_t xMessage;
+
+        ( void ) xTicksToWait;
+
+        traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+
+        configASSERT( xTimer );
+
+        /* Send a message to the timer service task to perform a particular action
+         * on a particular timer definition. */
+        if( xTimerQueue != NULL )
+        {
+            /* Send a command to the timer service task to start the xTimer timer. */
+            xMessage.xMessageID = xCommandID;
+            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+            xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+            configASSERT( xCommandID >= tmrFIRST_FROM_ISR_COMMAND );
+
+            if( xCommandID >= tmrFIRST_FROM_ISR_COMMAND )
+            {
+                xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+            }
+
+            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceRETURN_xTimerGenericCommandFromISR( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+    {
+        traceENTER_xTimerGetTimerDaemonTaskHandle();
+
+        /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+         * started, then xTimerTaskHandle will be NULL. */
+        configASSERT( ( xTimerTaskHandle != NULL ) );
+
+        traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle );
+
+        return xTimerTaskHandle;
+    }
+/*-----------------------------------------------------------*/
+
+    TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+    {
+        Timer_t * pxTimer = xTimer;
+
+        traceENTER_xTimerGetPeriod( xTimer );
+
+        configASSERT( xTimer );
+
+        traceRETURN_xTimerGetPeriod( pxTimer->xTimerPeriodInTicks );
+
+        return pxTimer->xTimerPeriodInTicks;
+    }
+/*-----------------------------------------------------------*/
+
+    void vTimerSetReloadMode( TimerHandle_t xTimer,
+                              const BaseType_t xAutoReload )
+    {
+        Timer_t * pxTimer = xTimer;
+
+        traceENTER_vTimerSetReloadMode( xTimer, xAutoReload );
+
+        configASSERT( xTimer );
+        taskENTER_CRITICAL();
+        {
+            if( xAutoReload != pdFALSE )
+            {
+                pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
+            }
+            else
+            {
+                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_AUTORELOAD );
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTimerSetReloadMode();
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer )
+    {
+        Timer_t * pxTimer = xTimer;
+        BaseType_t xReturn;
+
+        traceENTER_xTimerGetReloadMode( xTimer );
+
+        configASSERT( xTimer );
+        taskENTER_CRITICAL();
+        {
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0U )
+            {
+                /* Not an auto-reload timer. */
+                xReturn = pdFALSE;
+            }
+            else
+            {
+                /* Is an auto-reload timer. */
+                xReturn = pdTRUE;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xTimerGetReloadMode( xReturn );
+
+        return xReturn;
+    }
+
+    UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+    {
+        UBaseType_t uxReturn;
+
+        traceENTER_uxTimerGetReloadMode( xTimer );
+
+        uxReturn = ( UBaseType_t ) xTimerGetReloadMode( xTimer );
+
+        traceRETURN_uxTimerGetReloadMode( uxReturn );
+
+        return uxReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+    {
+        Timer_t * pxTimer = xTimer;
+        TickType_t xReturn;
+
+        traceENTER_xTimerGetExpiryTime( xTimer );
+
+        configASSERT( xTimer );
+        xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+
+        traceRETURN_xTimerGetExpiryTime( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+        BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer,
+                                          StaticTimer_t ** ppxTimerBuffer )
+        {
+            BaseType_t xReturn;
+            Timer_t * pxTimer = xTimer;
+
+            traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer );
+
+            configASSERT( ppxTimerBuffer != NULL );
+
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0U )
+            {
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
+                *ppxTimerBuffer = ( StaticTimer_t * ) pxTimer;
+                xReturn = pdTRUE;
+            }
+            else
+            {
+                xReturn = pdFALSE;
+            }
+
+            traceRETURN_xTimerGetStaticBuffer( xReturn );
+
+            return xReturn;
+        }
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+    const char * pcTimerGetName( TimerHandle_t xTimer )
+    {
+        Timer_t * pxTimer = xTimer;
+
+        traceENTER_pcTimerGetName( xTimer );
+
+        configASSERT( xTimer );
+
+        traceRETURN_pcTimerGetName( pxTimer->pcTimerName );
+
+        return pxTimer->pcTimerName;
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvReloadTimer( Timer_t * const pxTimer,
+                                TickType_t xExpiredTime,
+                                const TickType_t xTimeNow )
+    {
+        /* Insert the timer into the appropriate list for the next expiry time.
+         * If the next expiry time has already passed, advance the expiry time,
+         * call the callback function, and try again. */
+        while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE )
+        {
+            /* Advance the expiry time. */
+            xExpiredTime += pxTimer->xTimerPeriodInTicks;
+
+            /* Call the timer callback. */
+            traceTIMER_EXPIRED( pxTimer );
+            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
+                                        const TickType_t xTimeNow )
+    {
+        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+        /* Remove the timer from the list of active timers.  A check has already
+         * been performed to ensure the list is not empty. */
+
+        ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+
+        /* If the timer is an auto-reload timer then calculate the next
+         * expiry time and re-insert the timer in the list of active timers. */
+        if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
+        {
+            prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow );
+        }
+        else
+        {
+            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+        }
+
+        /* Call the timer callback. */
+        traceTIMER_EXPIRED( pxTimer );
+        pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+    }
+/*-----------------------------------------------------------*/
+
+    static portTASK_FUNCTION( prvTimerTask, pvParameters )
+    {
+        TickType_t xNextExpireTime;
+        BaseType_t xListWasEmpty;
+
+        /* Just to avoid compiler warnings. */
+        ( void ) pvParameters;
+
+        #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+        {
+            /* Allow the application writer to execute some code in the context of
+             * this task at the point the task starts executing.  This is useful if the
+             * application includes initialisation code that would benefit from
+             * executing after the scheduler has been started. */
+            vApplicationDaemonTaskStartupHook();
+        }
+        #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+        for( ; configCONTROL_INFINITE_LOOP(); )
+        {
+            /* Query the timers list to see if it contains any timers, and if so,
+             * obtain the time at which the next timer will expire. */
+            xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+            /* If a timer has expired, process it.  Otherwise, block this task
+             * until either a timer does expire, or a command is received. */
+            prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+            /* Empty the command queue. */
+            prvProcessReceivedCommands();
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
+                                            BaseType_t xListWasEmpty )
+    {
+        TickType_t xTimeNow;
+        BaseType_t xTimerListsWereSwitched;
+
+        vTaskSuspendAll();
+        {
+            /* Obtain the time now to make an assessment as to whether the timer
+             * has expired or not.  If obtaining the time causes the lists to switch
+             * then don't process this timer as any timers that remained in the list
+             * when the lists were switched will have been processed within the
+             * prvSampleTimeNow() function. */
+            xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+            if( xTimerListsWereSwitched == pdFALSE )
+            {
+                /* The tick count has not overflowed, has the timer expired? */
+                if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+                {
+                    ( void ) xTaskResumeAll();
+                    prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+                }
+                else
+                {
+                    /* The tick count has not overflowed, and the next expire
+                     * time has not been reached yet.  This task should therefore
+                     * block to wait for the next expire time or a command to be
+                     * received - whichever comes first.  The following line cannot
+                     * be reached unless xNextExpireTime > xTimeNow, except in the
+                     * case when the current timer list is empty. */
+                    if( xListWasEmpty != pdFALSE )
+                    {
+                        /* The current timer list is empty - is the overflow list
+                         * also empty? */
+                        xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+                    }
+
+                    vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+                    if( xTaskResumeAll() == pdFALSE )
+                    {
+                        /* Yield to wait for either a command to arrive, or the
+                         * block time to expire.  If a command arrived between the
+                         * critical section being exited and this yield then the yield
+                         * will not cause the task to block. */
+                        taskYIELD_WITHIN_API();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+            }
+            else
+            {
+                ( void ) xTaskResumeAll();
+            }
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+    {
+        TickType_t xNextExpireTime;
+
+        /* Timers are listed in expiry time order, with the head of the list
+         * referencing the task that will expire first.  Obtain the time at which
+         * the timer with the nearest expiry time will expire.  If there are no
+         * active timers then just set the next expire time to 0.  That will cause
+         * this task to unblock when the tick count overflows, at which point the
+         * timer lists will be switched and the next expiry time can be
+         * re-assessed.  */
+        *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+
+        if( *pxListWasEmpty == pdFALSE )
+        {
+            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+        }
+        else
+        {
+            /* Ensure the task unblocks when the tick count rolls over. */
+            xNextExpireTime = ( TickType_t ) 0U;
+        }
+
+        return xNextExpireTime;
+    }
+/*-----------------------------------------------------------*/
+
+    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+    {
+        TickType_t xTimeNow;
+        PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U;
+
+        xTimeNow = xTaskGetTickCount();
+
+        if( xTimeNow < xLastTime )
+        {
+            prvSwitchTimerLists();
+            *pxTimerListsWereSwitched = pdTRUE;
+        }
+        else
+        {
+            *pxTimerListsWereSwitched = pdFALSE;
+        }
+
+        xLastTime = xTimeNow;
+
+        return xTimeNow;
+    }
+/*-----------------------------------------------------------*/
+
+    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
+                                                  const TickType_t xNextExpiryTime,
+                                                  const TickType_t xTimeNow,
+                                                  const TickType_t xCommandTime )
+    {
+        BaseType_t xProcessTimerNow = pdFALSE;
+
+        listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+        listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+        if( xNextExpiryTime <= xTimeNow )
+        {
+            /* Has the expiry time elapsed between the command to start/reset a
+             * timer was issued, and the time the command was processed? */
+            if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks )
+            {
+                /* The time between a command being issued and the command being
+                 * processed actually exceeds the timers period.  */
+                xProcessTimerNow = pdTRUE;
+            }
+            else
+            {
+                vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+            }
+        }
+        else
+        {
+            if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+            {
+                /* If, since the command was issued, the tick count has overflowed
+                 * but the expiry time has not, then the timer must have already passed
+                 * its expiry time and should be processed immediately. */
+                xProcessTimerNow = pdTRUE;
+            }
+            else
+            {
+                vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+            }
+        }
+
+        return xProcessTimerNow;
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvProcessReceivedCommands( void )
+    {
+        DaemonTaskMessage_t xMessage = { 0 };
+        Timer_t * pxTimer;
+        BaseType_t xTimerListsWereSwitched;
+        TickType_t xTimeNow;
+
+        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL )
+        {
+            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+            {
+                /* Negative commands are pended function calls rather than timer
+                 * commands. */
+                if( xMessage.xMessageID < ( BaseType_t ) 0 )
+                {
+                    const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+                    /* The timer uses the xCallbackParameters member to request a
+                     * callback be executed.  Check the callback is not NULL. */
+                    configASSERT( pxCallback );
+
+                    /* Call the function. */
+                    pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            #endif /* INCLUDE_xTimerPendFunctionCall */
+
+            /* Commands that are positive are timer commands rather than pended
+             * function calls. */
+            if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+            {
+                /* The messages uses the xTimerParameters member to work on a
+                 * software timer. */
+                pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
+                {
+                    /* The timer is in a list, remove it. */
+                    ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+                /* In this case the xTimerListsWereSwitched parameter is not used, but
+                 *  it must be present in the function call.  prvSampleTimeNow() must be
+                 *  called after the message is received from xTimerQueue so there is no
+                 *  possibility of a higher priority task adding a message to the message
+                 *  queue with a time that is ahead of the timer daemon task (because it
+                 *  pre-empted the timer daemon task after the xTimeNow value was set). */
+                xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+                switch( xMessage.xMessageID )
+                {
+                    case tmrCOMMAND_START:
+                    case tmrCOMMAND_START_FROM_ISR:
+                    case tmrCOMMAND_RESET:
+                    case tmrCOMMAND_RESET_FROM_ISR:
+                        /* Start or restart a timer. */
+                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
+
+                        if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+                        {
+                            /* The timer expired before it was added to the active
+                             * timer list.  Process it now. */
+                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
+                            {
+                                prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
+                            }
+                            else
+                            {
+                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                            }
+
+                            /* Call the timer callback. */
+                            traceTIMER_EXPIRED( pxTimer );
+                            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        break;
+
+                    case tmrCOMMAND_STOP:
+                    case tmrCOMMAND_STOP_FROM_ISR:
+                        /* The timer has already been removed from the active list. */
+                        pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                        break;
+
+                    case tmrCOMMAND_CHANGE_PERIOD:
+                    case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
+                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
+                        pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+                        configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+                        /* The new period does not really have a reference, and can
+                         * be longer or shorter than the old one.  The command time is
+                         * therefore set to the current time, and as the period cannot
+                         * be zero the next expiry time can only be in the future,
+                         * meaning (unlike for the xTimerStart() case above) there is
+                         * no fail case that needs to be handled here. */
+                        ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+                        break;
+
+                    case tmrCOMMAND_DELETE:
+                        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+                        {
+                            /* The timer has already been removed from the active list,
+                             * just free up the memory if the memory was dynamically
+                             * allocated. */
+                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+                            {
+                                vPortFree( pxTimer );
+                            }
+                            else
+                            {
+                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                            }
+                        }
+                        #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+                        {
+                            /* If dynamic allocation is not enabled, the memory
+                             * could not have been dynamically allocated. So there is
+                             * no need to free the memory - just mark the timer as
+                             * "not active". */
+                            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                        }
+                        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+                        break;
+
+                    default:
+                        /* Don't expect to get here. */
+                        break;
+                }
+            }
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvSwitchTimerLists( void )
+    {
+        TickType_t xNextExpireTime;
+        List_t * pxTemp;
+
+        /* The tick count has overflowed.  The timer lists must be switched.
+         * If there are any timers still referenced from the current timer list
+         * then they must have expired and should be processed before the lists
+         * are switched. */
+        while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+        {
+            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+            /* Process the expired timer.  For auto-reload timers, be careful to
+             * process only expirations that occur on the current list.  Further
+             * expirations must wait until after the lists are switched. */
+            prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW );
+        }
+
+        pxTemp = pxCurrentTimerList;
+        pxCurrentTimerList = pxOverflowTimerList;
+        pxOverflowTimerList = pxTemp;
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvCheckForValidListAndQueue( void )
+    {
+        /* Check that the list from which active timers are referenced, and the
+         * queue used to communicate with the timer service, have been
+         * initialised. */
+        taskENTER_CRITICAL();
+        {
+            if( xTimerQueue == NULL )
+            {
+                vListInitialise( &xActiveTimerList1 );
+                vListInitialise( &xActiveTimerList2 );
+                pxCurrentTimerList = &xActiveTimerList1;
+                pxOverflowTimerList = &xActiveTimerList2;
+
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    /* The timer queue is allocated statically in case
+                     * configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+                    PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;
+                    PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ];
+
+                    xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+                }
+                #else
+                {
+                    xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ) );
+                }
+                #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+                #if ( configQUEUE_REGISTRY_SIZE > 0 )
+                {
+                    if( xTimerQueue != NULL )
+                    {
+                        vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                #endif /* configQUEUE_REGISTRY_SIZE */
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+    {
+        BaseType_t xReturn;
+        Timer_t * pxTimer = xTimer;
+
+        traceENTER_xTimerIsTimerActive( xTimer );
+
+        configASSERT( xTimer );
+
+        /* Is the timer in the list of active timers? */
+        taskENTER_CRITICAL();
+        {
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0U )
+            {
+                xReturn = pdFALSE;
+            }
+            else
+            {
+                xReturn = pdTRUE;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xTimerIsTimerActive( xReturn );
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    void * pvTimerGetTimerID( const TimerHandle_t xTimer )
+    {
+        Timer_t * const pxTimer = xTimer;
+        void * pvReturn;
+
+        traceENTER_pvTimerGetTimerID( xTimer );
+
+        configASSERT( xTimer );
+
+        taskENTER_CRITICAL();
+        {
+            pvReturn = pxTimer->pvTimerID;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_pvTimerGetTimerID( pvReturn );
+
+        return pvReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    void vTimerSetTimerID( TimerHandle_t xTimer,
+                           void * pvNewID )
+    {
+        Timer_t * const pxTimer = xTimer;
+
+        traceENTER_vTimerSetTimerID( xTimer, pvNewID );
+
+        configASSERT( xTimer );
+
+        taskENTER_CRITICAL();
+        {
+            pxTimer->pvTimerID = pvNewID;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_vTimerSetTimerID();
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+
+        BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+                                                  void * pvParameter1,
+                                                  uint32_t ulParameter2,
+                                                  BaseType_t * pxHigherPriorityTaskWoken )
+        {
+            DaemonTaskMessage_t xMessage;
+            BaseType_t xReturn;
+
+            traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken );
+
+            /* Complete the message with the function parameters and post it to the
+             * daemon task. */
+            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+            xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+            tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+            traceRETURN_xTimerPendFunctionCallFromISR( xReturn );
+
+            return xReturn;
+        }
+
+    #endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+
+        BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                           void * pvParameter1,
+                                           uint32_t ulParameter2,
+                                           TickType_t xTicksToWait )
+        {
+            DaemonTaskMessage_t xMessage;
+            BaseType_t xReturn;
+
+            traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
+
+            /* This function can only be called after a timer has been created or
+             * after the scheduler has been started because, until then, the timer
+             * queue does not exist. */
+            configASSERT( xTimerQueue );
+
+            /* Complete the message with the function parameters and post it to the
+             * daemon task. */
+            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+            xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+            tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+            traceRETURN_xTimerPendFunctionCall( xReturn );
+
+            return xReturn;
+        }
+
+    #endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+        {
+            traceENTER_uxTimerGetTimerNumber( xTimer );
+
+            traceRETURN_uxTimerGetTimerNumber( ( ( Timer_t * ) xTimer )->uxTimerNumber );
+
+            return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+        }
+
+    #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        void vTimerSetTimerNumber( TimerHandle_t xTimer,
+                                   UBaseType_t uxTimerNumber )
+        {
+            traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber );
+
+            ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+
+            traceRETURN_vTimerSetTimerNumber();
+        }
+
+    #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+ * to include software timer functionality.  If you want to include software timer
+ * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_data.ldt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_data.ldt
new file mode 100644
index 0000000000..79b78c6119
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_data.ldt
@@ -0,0 +1,3 @@
+       *mflash_drv.o(.text .text* .rodata .rodata*)
+       *fsl_flexspi.o(.text .text* .rodata .rodata*)
+       *(.data*)
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_rodata.ldt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_rodata.ldt
new file mode 100644
index 0000000000..329771d1bf
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_rodata.ldt
@@ -0,0 +1,4 @@
+       *(.rodata)
+       *(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o).rodata.*)
+       *(.constdata .constdata.*)
+       . = ALIGN(${text_align});
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_text.ldt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_text.ldt
new file mode 100644
index 0000000000..3740e219fc
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/main_text.ldt
@@ -0,0 +1 @@
+        *(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/noinit_noload_section.ldt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/noinit_noload_section.ldt
new file mode 100644
index 0000000000..b137ad354b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/linkscripts/noinit_noload_section.ldt
@@ -0,0 +1,44 @@
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        PROVIDE(__start_noinit_RAM = .) ;
+        PROVIDE(__start_noinit_SRAM = .) ;
+        *(.noinit*)
+        . = ALIGN(4) ;
+        _end_noinit = .;
+        PROVIDE(__end_noinit_RAM = .) ;
+        PROVIDE(__end_noinit_SRAM = .) ;
+    } > SRAM AT> SRAM
+
+    .smu_cpu13_mbox (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu13_mbox)
+        KEEP (*(.smu_cpu13_mbox))
+        . = ALIGN(4);
+    } > MBOX1 AT> MBOX1
+
+    .smu_cpu31_txq (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu31_txq)
+        KEEP (*(.smu_cpu31_txq))
+        . = ALIGN(4);
+    } > TXQ1 AT> TXQ1
+
+    .smu_cpu23_mbox (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu23_mbox)
+        KEEP (*(.smu_cpu23_mbox))
+        . = ALIGN(4);
+    } > MBOX2 AT> MBOX2
+
+    .smu_cpu32_txq (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu32_txq)
+        KEEP (*(.smu_cpu32_txq))
+        . = ALIGN(4);
+    } > TXQ32 AT> TXQ32
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/FreeRTOSConfig.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/FreeRTOSConfig.h
new file mode 100644
index 0000000000..4909d4833b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/FreeRTOSConfig.h
@@ -0,0 +1,180 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_TICKLESS_IDLE                 0
+#define configCPU_CLOCK_HZ                      (SystemCoreClock)
+#define configTICK_RATE_HZ                      ((TickType_t)1000)
+#define configMAX_PRIORITIES                    5
+#define configMINIMAL_STACK_SIZE                ((unsigned short)128)
+#define configMAX_TASK_NAME_LEN                 20
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_TASK_NOTIFICATIONS            1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configUSE_ALTERNATIVE_API               0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE               8
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME               3
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+//#define configTOTAL_HEAP_SIZE                   ((size_t)(35 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                     0
+#define configUSE_TICK_HOOK                     0
+#define configCHECK_FOR_STACK_OVERFLOW          0
+#define configUSE_MALLOC_FAILED_HOOK            0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK      0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS         1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES                   0
+#define configMAX_CO_ROUTINE_PRIORITIES         2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                        1
+#define configTIMER_TASK_PRIORITY               (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH                10
+#define configTIMER_TASK_STACK_DEPTH            (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet                1
+#define INCLUDE_uxTaskPriorityGet               1
+#define INCLUDE_vTaskDelete                     1
+#define INCLUDE_vTaskSuspend                    1
+#define INCLUDE_vTaskDelayUntil                 1
+#define INCLUDE_vTaskDelay                      1
+#define INCLUDE_xTaskGetSchedulerState          1
+#define INCLUDE_xTaskGetCurrentTaskHandle       1
+#define INCLUDE_uxTaskGetStackHighWaterMark     0
+#define INCLUDE_xTaskGetIdleTaskHandle          0
+#define INCLUDE_eTaskGetState                   0
+#define INCLUDE_xTimerPendFunctionCall          1
+#define INCLUDE_xTaskAbortDelay                 0
+#define INCLUDE_xTaskGetHandle                  0
+#define INCLUDE_xTaskResumeFromISR              1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+#include "fsl_device_registers.h"
+#endif
+
+
+#ifndef configENABLE_FPU
+  #define configENABLE_FPU                        1
+#endif
+#ifndef configENABLE_MPU
+  #define configENABLE_MPU                        0
+#endif
+#ifndef configENABLE_TRUSTZONE
+  #define configENABLE_TRUSTZONE                  0
+#endif
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+  #define configRUN_FREERTOS_SECURE_ONLY          1
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES                       1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(128 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 3 /* 7 priority levels */
+#endif
+
+#define configSTACK_DEPTH_TYPE uint32_t
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define vPortPendSVHandler PendSV_Handler
+#define vPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/app_config.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/app_config.h
new file mode 100644
index 0000000000..1b8680fa3e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/app_config.h
@@ -0,0 +1,18 @@
+/*
+ *  Copyright 2021 NXP
+ *  All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define RW610
+#define FRDMRW610
+#define WIFI_BT_USE_IMU_INTERFACE
+
+#if CONFIG_MONOLITHIC_WIFI
+#define CONFIG_SOC_SERIES_RW6XX_REVISION_A2 1
+#endif
+
+
+#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW_rw610.h"
+#define CONFIG_BT_SNOOP 1
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/main.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/main.c
new file mode 100644
index 0000000000..0420910632
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/main.c
@@ -0,0 +1,165 @@
+
+#include <stdio.h>
+
+#include "mongoose.h"
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "timers.h"
+
+#include "fsl_debug_console.h"
+
+#include "fsl_power.h"
+
+
+
+//#define WIFI_SSID "YOUR_WIFI_NETWORK_NAME"  // SET THIS!
+//#define WIFI_PASS "YOUR_WIFI_PASSWORD"      // SET THIS!
+#define WIFI_SSID "LinternaVerde"
+#define WIFI_PASS "StanleyJordan69"
+
+
+// mif user states
+enum {AP, SCANNING, STOPPING_AP, CONNECTING, READY};
+static unsigned int state;
+
+
+static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  // TODO(): should we include this inside ifp ? add an fn_data ?
+  if (ev == MG_TCPIP_EV_ST_CHG) {
+    MG_INFO(("State change: %u", *(uint8_t *) ev_data));
+  }
+  switch(state) {
+    case AP: // we are in AP mode, wait for a user connection to trigger a scan or a connection to a network
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
+        MG_INFO(("Access Point READY !"));
+
+        // simulate user request to scan for networks
+        bool res = mg_wifi_scan();
+        MG_INFO(("Starting scan: %s", res ? "OK":"FAIL"));
+        if (res) state = SCANNING;
+      }
+      break;
+    case SCANNING:
+      if (ev == MG_TCPIP_EV_WIFI_SCAN_RESULT) {
+        struct mg_wifi_scan_bss_data *bss = (struct mg_wifi_scan_bss_data *) ev_data;
+        MG_INFO(("BSS: %.*s (%u) (%M) %d dBm %u", bss->SSID.len, bss->SSID.buf, bss->channel, mg_print_mac, bss->BSSID, (int) bss->RSSI, bss->security));
+      } else if (ev == MG_TCPIP_EV_WIFI_SCAN_END) {
+        // struct mg_tcpip_driver_nxp_wifi_data *d = (struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data;
+        MG_INFO(("Wi-Fi scan finished"));
+
+        // simulate user selection of a network (1/2: stop AP)
+        bool res = mg_wifi_ap_stop();
+        MG_INFO(("Manually stopping AP: %s", res ? "OK":"FAIL"));
+        if (res) state = STOPPING_AP;
+        // else we have a hw/fw problem
+      }
+      break;
+    case STOPPING_AP:
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+        wifi->apmode = false;
+
+        // simulate user selection of a network (2/2: actual connect)
+        bool res = mg_wifi_connect(wifi);
+        MG_INFO(("Manually connecting: %s", res ? "OK":"FAIL"));
+        if (res) {
+          state = CONNECTING;
+        } // else manually start AP as below
+      }
+      break;
+    case CONNECTING:
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
+        MG_INFO(("READY!"));
+        state = READY;
+
+        // simulate user code disconnection and go back to AP mode (1/2: disconnect)
+        bool res = mg_wifi_disconnect();
+        MG_INFO(("Manually disconnecting: %s", res ? "OK":"FAIL"));
+      } else if (ev == MG_TCPIP_EV_WIFI_CONNECT_ERR) {
+        MG_ERROR(("Wi-Fi connect failed"));
+        // manually start AP as below
+      }
+      break;
+    case READY:
+      // go back to AP mode after a disconnection (simulation 2/2), you could retry
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+        bool res = mg_wifi_ap_start(wifi);
+        MG_INFO(("Disconnected"));
+        MG_INFO(("Manually starting AP: %s", res ? "OK":"FAIL"));
+        if (res) {
+          state = AP;
+          wifi->apmode = true;
+        }
+      }
+      break;
+  }
+}
+
+
+static void mongoose(void *arg) {
+  struct mg_mgr mgr;        // Initialise Mongoose event manager
+  mg_mgr_init(&mgr);        // and attach it to the interface
+  mg_log_set(MG_LL_DEBUG);
+
+  extern const struct mg_tcpip_driver netif_driver;
+
+  // Initialise WiFi creds
+  struct mg_tcpip_driver_nxp_wifi_data driver_data = {
+    .wifi.ssid = WIFI_SSID,
+    .wifi.pass = WIFI_PASS,
+    .wifi.apssid = "mongoose",
+    .wifi.appass = "mongoose",
+    .wifi.apip = MG_IPV4(192, 168, 169, 1),
+    .wifi.apmask = MG_IPV4(255, 255, 255, 0),
+    .wifi.security = 0,
+    .wifi.apsecurity = 0,
+    .wifi.apchannel = 10,
+    .wifi.apmode = true
+  };
+
+  state = driver_data.wifi.apmode ? AP : CONNECTING;
+
+  // Initialise Mongoose network stack
+  // Either set use_dhcp or enter a static config.
+  // For static configuration, specify IP/mask/GW in network byte order
+  struct mg_tcpip_if mif = {
+      .ip = 0,
+      .driver = (struct mg_tcpip_driver *)&mg_tcpip_driver_nxp_wifi,
+      .driver_data = (struct mg_tcpip_driver_nxp_wifi_data*)&driver_data,
+      .fn = mif_fn,
+//      .recv_queue.size = 8192
+  };
+
+  mg_tcpip_init(&mgr, &mif);
+
+    MG_INFO(("Starting event loop"));
+
+    for (;;) {
+      mg_mgr_poll(&mgr, 10);
+    }
+}
+
+
+int main(void)
+{
+    BOARD_InitBootPins();
+    BOARD_BootClockLPR();
+    CLOCK_EnableClock(kCLOCK_Otp);
+    CLOCK_EnableClock(kCLOCK_Els);
+    CLOCK_EnableClock(kCLOCK_ElsApb);
+    RESET_PeripheralReset(kOTP_RST_SHIFT_RSTn);
+    RESET_PeripheralReset(kELS_APB_RST_SHIFT_RSTn);
+    BOARD_InitDebugConsole();
+    RESET_PeripheralReset(kGDMA_RST_SHIFT_RSTn);
+    POWER_ConfigCauInSleep(false);
+    BOARD_InitSleepPinConfig();
+
+    xTaskCreate(mongoose, "mongoose", 2048, NULL, configMAX_PRIORITIES - 4, NULL);
+
+    vTaskStartScheduler();  // This blocks
+
+    return 0;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose.c
new file mode 120000
index 0000000000..7a2752cb74
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose.c
@@ -0,0 +1 @@
+../../../../mongoose.c
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose.h
new file mode 120000
index 0000000000..daff16334a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose.h
@@ -0,0 +1 @@
+../../../../mongoose.h
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose_config.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose_config.h
new file mode 100644
index 0000000000..7ceeab3f93
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/mongoose_config.h
@@ -0,0 +1,13 @@
+#pragma once
+
+// See https://mongoose.ws/documentation/#build-options
+#define MG_ARCH MG_ARCH_FREERTOS
+
+#define MG_ENABLE_TCPIP 1
+#define MG_ENABLE_DRIVER_NXP_WIFI 1
+#define MG_ENABLE_PACKED_FS 1
+#define MG_ENABLE_TCPIP_DRIVER_INIT 0
+
+
+#define HTTP_URL "http://0.0.0.0:80"
+#define HTTPS_URL "https://0.0.0.0:443"
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/semihost_hardfault.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/semihost_hardfault.c
new file mode 100644
index 0000000000..55f6d9bcaa
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/semihost_hardfault.c
@@ -0,0 +1,98 @@
+// ****************************************************************************
+// semihost_hardfault.c
+//                - Provides hard fault handler to allow semihosting code not
+//                  to hang application when debugger not connected.
+//
+// ****************************************************************************
+// Copyright 2017-2025 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+// ****************************************************************************
+//
+//                       ===== DESCRIPTION =====
+//
+// One of the issues with applications that make use of semihosting operations
+// (such as printf calls) is that the code will not execute correctly when the
+// debugger is not connected. Generally this will show up with the application
+// appearing to just hang. This may include the application running from reset
+// or powering up the board (with the application already in FLASH), and also
+// as the application failing to continue to execute after a debug session is
+// terminated.
+//
+// The problem here is that the "bottom layer" of the semihosted variants of
+// the C library, semihosting is implemented by a "BKPT 0xAB" instruction.
+// When the debug tools are not connected, this instruction triggers a hard
+// fault - and the default hard fault handler within an application will
+// typically just contains an infinite loop - causing the application to
+// appear to have hang when no debugger is connected.
+//
+// The below code provides an example hard fault handler which instead looks
+// to see what the instruction that caused the hard fault was - and if it
+// was a "BKPT 0xAB", then it instead returns back to the user application.
+//
+// In most cases this will allow applications containing semihosting
+// operations to execute (to some degree) when the debugger is not connected.
+//
+// == NOTE ==
+//
+// Correct execution of the application containing semihosted operations
+// which are vectored onto this hard fault handler cannot be guaranteed. This
+// is because the handler may not return data or return codes that the higher
+// level C library code or application code expects. This hard fault handler
+// is meant as a development aid, and it is not recommended to leave
+// semihosted code in a production build of your application!
+//
+// ****************************************************************************
+
+// Allow handler to be removed by setting a define (via command line)
+#if !defined (__SEMIHOST_HARDFAULT_DISABLE)
+
+__attribute__((naked))
+void HardFault_Handler(void){
+    __asm(  ".syntax unified\n"
+        // Check which stack is in use
+            "MOVS   R0, #4           \n"
+            "MOV    R1, LR           \n"
+            "TST    R0, R1           \n"
+            "BEQ    _MSP             \n"
+            "MRS    R0, PSP          \n"
+            "B  _process             \n"
+            "_MSP:                   \n"
+            "MRS    R0, MSP          \n"
+        // Load the instruction that triggered hard fault
+        "_process:                   \n"
+            "LDR    R1,[R0,#24]      \n"
+            "LDRH   R2,[r1]          \n"
+        // Semihosting instruction is "BKPT 0xAB" (0xBEAB)
+            "LDR    R3,=0xBEAB       \n"
+            "CMP    R2,R3            \n"
+            "BEQ    _semihost_return \n"
+        // Wasn't semihosting instruction so enter infinite loop
+            "B .                     \n"
+        // Was semihosting instruction, so adjust location to
+        // return to by 1 instruction (2 bytes), then exit function
+            "_semihost_return:       \n"
+            "ADDS   R1,#2            \n"
+            "STR    R1,[R0,#24]      \n"
+        // Set a return value from semihosting operation.
+        // 0 is slightly arbitrary, but appears to allow most
+        // C Library IO functions sitting on top of semihosting to
+        // continue to operate to some degree
+        // Return a positive value (32) for SYS_OPEN only
+            "LDR    R1,[ R0,#0 ]     \n"  // R0 is at location 0 on stack
+            "CMP    R1, #1           \n"  // 0x01=SYS_OPEN
+            "BEQ    _non_zero_ret    \n"
+            "MOVS   R1,#0            \n"
+            "B      _sys_ret         \n"
+            "_non_zero_ret:          \n"
+            "MOVS   R1,#32           \n"
+            "_sys_ret:               \n"
+            "STR    R1,[ R0,#0 ]     \n" // R0 is at location 0 on stack
+        // Return from hard fault handler to application
+            "BX     LR               \n"
+        ".syntax divided\n") ;
+}
+
+#endif
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/wifi_config.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/wifi_config.h
new file mode 100644
index 0000000000..1617d2dbcc
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/source/wifi_config.h
@@ -0,0 +1,51 @@
+/*
+ *  Copyright 2020-2024 NXP
+ *  All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _WIFI_CONFIG_H_
+#define _WIFI_CONFIG_H_
+
+#include "app_config.h"
+#ifndef RW610
+#include "wifi_bt_module_config.h"
+#endif
+
+#define CONFIG_IPV6 0
+#define CONFIG_MAX_IPV6_ADDRESSES 3
+
+/* WLCMGR debug */
+#define CONFIG_WLCMGR_DEBUG 0
+
+/*
+ * Wifi extra debug options
+ */
+#define CONFIG_WIFI_EXTRA_DEBUG 0
+#define CONFIG_WIFI_EVENTS_DEBUG 0
+#define CONFIG_WIFI_CMD_RESP_DEBUG 0
+#define CONFIG_WIFI_PKT_DEBUG 0
+#define CONFIG_WIFI_SCAN_DEBUG 0
+#define CONFIG_WIFI_IO_INFO_DUMP 0
+#define CONFIG_WIFI_IO_DEBUG 0
+#define CONFIG_WIFI_IO_DUMP 0
+#define CONFIG_WIFI_MEM_DEBUG 0
+#define CONFIG_WIFI_AMPDU_DEBUG 0
+#define CONFIG_WIFI_TIMER_DEBUG 0
+#define CONFIG_WIFI_SDIO_DEBUG 0
+#define CONFIG_WIFI_FW_DEBUG 0
+#define CONFIG_WIFI_UAP_DEBUG 0
+#define CONFIG_WPS_DEBUG 0
+#define CONFIG_FW_VDLL_DEBUG 0
+#define CONFIG_DHCP_SERVER_DEBUG 0
+#define CONFIG_WIFI_SDIO_DEBUG 0
+#define CONFIG_FWDNLD_IO_DEBUG 0
+
+/*
+ * Heap debug options
+ */
+#define CONFIG_HEAP_DEBUG 0
+#define CONFIG_HEAP_STAT 0
+
+#endif /* _WIFI_CONFIG_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/startup/startup_rw612.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/startup/startup_rw612.c
new file mode 100644
index 0000000000..d77c17afae
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/startup/startup_rw612.c
@@ -0,0 +1,1228 @@
+//*****************************************************************************
+// RW612 startup code for use with MCUXpresso IDE
+//
+// Version : 120324
+//*****************************************************************************
+//
+// Copyright 2016-2024 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+     void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SecureFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void WDT0_IRQHandler(void);
+WEAK void DMA0_IRQHandler(void);
+WEAK void GPIO_INTA_IRQHandler(void);
+WEAK void GPIO_INTB_IRQHandler(void);
+WEAK void PIN_INT0_IRQHandler(void);
+WEAK void PIN_INT1_IRQHandler(void);
+WEAK void PIN_INT2_IRQHandler(void);
+WEAK void PIN_INT3_IRQHandler(void);
+WEAK void UTICK_IRQHandler(void);
+WEAK void MRT_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void SCT0_IRQHandler(void);
+WEAK void CTIMER3_IRQHandler(void);
+WEAK void FLEXCOMM0_IRQHandler(void);
+WEAK void FLEXCOMM1_IRQHandler(void);
+WEAK void FLEXCOMM2_IRQHandler(void);
+WEAK void FLEXCOMM3_IRQHandler(void);
+WEAK void Reserved34_IRQHandler(void);
+WEAK void Reserved35_IRQHandler(void);
+WEAK void FLEXCOMM14_IRQHandler(void);
+WEAK void Reserved37_IRQHandler(void);
+WEAK void Reserved38_IRQHandler(void);
+WEAK void GFMRT_IRQHandler(void);
+WEAK void Reserved40_IRQHandler(void);
+WEAK void DMIC_IRQHandler(void);
+WEAK void WKDEEPSLEEP_IRQHandler(void);
+WEAK void HYPERVISOR_IRQHandler(void);
+WEAK void SECUREVIOLATION_IRQHandler(void);
+WEAK void HWVAD_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void Reserved47_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void Reserved49_IRQHandler(void);
+WEAK void Reserved50_IRQHandler(void);
+WEAK void PIN_INT4_IRQHandler(void);
+WEAK void PIN_INT5_IRQHandler(void);
+WEAK void PIN_INT6_IRQHandler(void);
+WEAK void PIN_INT7_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void CTIMER4_IRQHandler(void);
+WEAK void OS_EVENT_TIMER_IRQHandler(void);
+WEAK void FLEXSPI_IRQHandler(void);
+WEAK void Reserved59_IRQHandler(void);
+WEAK void Reserved60_IRQHandler(void);
+WEAK void Reserved61_IRQHandler(void);
+WEAK void SDIO_IRQHandler(void);
+WEAK void SGPIO_INTA_IRQHandler(void);
+WEAK void SGPIO_INTB_IRQHandler(void);
+WEAK void Reserved65_IRQHandler(void);
+WEAK void USB_IRQHandler(void);
+WEAK void Reserved67_IRQHandler(void);
+WEAK void Reserved68_IRQHandler(void);
+WEAK void Reserved69_IRQHandler(void);
+WEAK void DMA1_IRQHandler(void);
+WEAK void PUF_IRQHandler(void);
+WEAK void POWERQUAD_IRQHandler(void);
+WEAK void Reserved73_IRQHandler(void);
+WEAK void Reserved74_IRQHandler(void);
+WEAK void Reserved75_IRQHandler(void);
+WEAK void Reserved76_IRQHandler(void);
+WEAK void LCD_IRQHandler(void);
+WEAK void CAPTIMER_IRQHandler(void);
+WEAK void Reserved79_IRQHandler(void);
+WEAK void W2MWKUP_DONE0_IRQHandler(void);
+WEAK void W2MWKUP_DONE1_IRQHandler(void);
+WEAK void W2MWKUP_DONE2_IRQHandler(void);
+WEAK void W2MWKUP_DONE3_IRQHandler(void);
+WEAK void W2MWKUP_DONE4_IRQHandler(void);
+WEAK void W2MWKUP_DONE5_IRQHandler(void);
+WEAK void W2MWKUP_DONE6_IRQHandler(void);
+WEAK void W2MWKUP_DONE7_IRQHandler(void);
+WEAK void W2MWKUP0_IRQHandler(void);
+WEAK void W2MWKUP1_IRQHandler(void);
+WEAK void WL_MCI_INT0_IRQHandler(void);
+WEAK void WL_MCI_INT1_IRQHandler(void);
+WEAK void WL_MCI_INT2_IRQHandler(void);
+WEAK void WL_MCI_INT3_IRQHandler(void);
+WEAK void WL_MCI_INT4_IRQHandler(void);
+WEAK void WL_MCI_INT5_IRQHandler(void);
+WEAK void WL_MCI_INT6_IRQHandler(void);
+WEAK void WL_MCI_INT7_IRQHandler(void);
+WEAK void B2MWKUP_DONE0_IRQHandler(void);
+WEAK void B2MWKUP_DONE1_IRQHandler(void);
+WEAK void B2MWKUP_DONE2_IRQHandler(void);
+WEAK void B2MWKUP_DONE3_IRQHandler(void);
+WEAK void B2MWKUP_DONE4_IRQHandler(void);
+WEAK void B2MWKUP_DONE5_IRQHandler(void);
+WEAK void B2MWKUP_DONE6_IRQHandler(void);
+WEAK void B2MWKUP_DONE7_IRQHandler(void);
+WEAK void B2MWKUP0_IRQHandler(void);
+WEAK void B2MWKUP1_IRQHandler(void);
+WEAK void BLE_MCI_INT0_IRQHandler(void);
+WEAK void BLE_MCI_INT1_IRQHandler(void);
+WEAK void BLE_MCI_INT2_IRQHandler(void);
+WEAK void BLE_MCI_INT3_IRQHandler(void);
+WEAK void BLE_MCI_INT4_IRQHandler(void);
+WEAK void BLE_MCI_INT5_IRQHandler(void);
+WEAK void BLE_MCI_INT6_IRQHandler(void);
+WEAK void BLE_MCI_INT7_IRQHandler(void);
+WEAK void PIN0_INT_IRQHandler(void);
+WEAK void PIN1_INT_IRQHandler(void);
+WEAK void ELS_IRQHandler(void);
+WEAK void ELS_GDET_IRQHandler(void);
+WEAK void ELS_GDET_UM_IRQHandler(void);
+WEAK void PKC_INT_IRQHandler(void);
+WEAK void PKC_ERR_IRQHandler(void);
+WEAK void CDOG_INT_IRQHandler(void);
+WEAK void GAU_DAC_IRQHandler(void);
+WEAK void GAU_ACOMP_WKUP_IRQHandler(void);
+WEAK void GAU_ACOMP_IRQHandler(void);
+WEAK void GAU_ADC1_IRQHandler(void);
+WEAK void GAU_ADC0_IRQHandler(void);
+WEAK void USIM_IRQHandler(void);
+WEAK void OTP_IRQHandler(void);
+WEAK void ENET_IRQHandler(void);
+WEAK void ENET_TIMER_IRQHandler(void);
+WEAK void PMIP_IRQHandler(void);
+WEAK void PMIP_CHANGE_IRQHandler(void);
+WEAK void ITRC_IRQHandler(void);
+WEAK void Reserved136_IRQHandler(void);
+WEAK void Reserved137_IRQHandler(void);
+WEAK void Reserved138_IRQHandler(void);
+WEAK void TRNG_IRQHandler(void);
+WEAK void ACC_C_INT_IRQHandler(void);
+WEAK void ACC_S_INT_IRQHandler(void);
+WEAK void WACC_IRQHandler(void);
+WEAK void BACC_IRQHandler(void);
+WEAK void GDMA_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void WDT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_INTA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_INTB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved34_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved35_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM14_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved37_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved38_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GFMRT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved40_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WKDEEPSLEEP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HYPERVISOR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SECUREVIOLATION_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HWVAD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved49_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved50_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void OS_EVENT_TIMER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_INTA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_INTB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved65_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved67_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved69_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void POWERQUAD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved73_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved74_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved75_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved76_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAPTIMER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved79_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP_DONE7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void W2MWKUP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WL_MCI_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP_DONE7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void B2MWKUP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_MCI_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN0_INT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN1_INT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ELS_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ELS_GDET_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ELS_GDET_UM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PKC_INT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PKC_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CDOG_INT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GAU_DAC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GAU_ACOMP_WKUP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GAU_ACOMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GAU_ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GAU_ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USIM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void OTP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ENET_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ENET_TIMER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PMIP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PMIP_CHANGE_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ITRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved136_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved137_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved138_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ACC_C_INT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ACC_S_INT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WACC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BACC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GDMA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+extern void _image_size(void);
+//*****************************************************************************
+// External declaration for the pointer to the stack base from the Linker Script
+//*****************************************************************************
+extern void _vStackBase(void);
+//*****************************************************************************
+// External declaration for image type and load address from  Linker Script
+//*****************************************************************************
+WEAK extern void __imghdr_loadaddress();
+WEAK extern void __imghdr_imagetype();
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level - CM33
+    &_vStackTop,                       // The initial stack pointer
+    ResetISR,                          // The reset handler
+    NMI_Handler,                       // NMI Handler
+    HardFault_Handler,                 // Hard Fault Handler
+    MemManage_Handler,                 // MPU Fault Handler
+    BusFault_Handler,                  // Bus Fault Handler
+    UsageFault_Handler,                // Usage Fault Handler
+    SecureFault_Handler,               // Secure Fault Handler
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
+    (void (*)())0x100000,                // Image length
+#else
+    (void (*)())((unsigned)_image_size), // Image length
+#endif
+    __imghdr_imagetype,                // Image type
+    0,                                 // Reserved
+    SVC_Handler,                       // SVCall Handler
+    DebugMon_Handler,                  // Debug Monitor Handler
+    (void (*)())g_pfnVectors,          // Image load address
+    PendSV_Handler,                    // PendSV Handler
+    SysTick_Handler,                   // SysTick Handler
+
+    // Chip Level - RW612
+    WDT0_IRQHandler,             // 16 : Windowed watchdog timer 0 (WDT0)(Cortex-M33 watchdog)
+    DMA0_IRQHandler,             // 17 : Direct memory access (DMA) controller 0 (secure or Cortex-M33 DMA)
+    GPIO_INTA_IRQHandler,        // 18 : GPIO interrupt A
+    GPIO_INTB_IRQHandler,        // 19 : GPIO interrupt B
+    PIN_INT0_IRQHandler,         // 20 : Pin interrupt 0 or pattern match engine slice 0
+    PIN_INT1_IRQHandler,         // 21 : Pin interrupt 1 or pattern match engine slice 1
+    PIN_INT2_IRQHandler,         // 22 : Pin interrupt 2 or pattern match engine slice 2
+    PIN_INT3_IRQHandler,         // 23 : Pin interrupt 3 or pattern match engine slice 3
+    UTICK_IRQHandler,            // 24 : Micro-tick Timer (UTICK)
+    MRT_IRQHandler,              // 25 : Multi-Rate Timer (MRT). Global MRT interrupts
+    CTIMER0_IRQHandler,          // 26 : Standard counter/timer CTIMER0
+    CTIMER1_IRQHandler,          // 27 : Standard counter/timer CTIMER1
+    SCT0_IRQHandler,             // 28 : SCTimer/PWM
+    CTIMER3_IRQHandler,          // 29 : Standard counter/timer CTIMER3
+    FLEXCOMM0_IRQHandler,        // 30 : Flexcomm Interface 0 (USART, SPI, I2C, I2S)
+    FLEXCOMM1_IRQHandler,        // 31 : Flexcomm Interface 1 (USART, SPI, I2C, I2S)
+    FLEXCOMM2_IRQHandler,        // 32 : Flexcomm Interface 2 (USART, SPI, I2C, I2S)
+    FLEXCOMM3_IRQHandler,        // 33 : Flexcomm Interface 3 (USART, SPI, I2C, I2S)
+    Reserved34_IRQHandler,       // 34 : Reserved interrupt
+    Reserved35_IRQHandler,       // 35 : Reserved interrupt
+    FLEXCOMM14_IRQHandler,       // 36 : Flexcomm Interface 14 (USART, SPI, I2C, I2S)
+    Reserved37_IRQHandler,       // 37 : Reserved interrupt
+    Reserved38_IRQHandler,       // 38 : Reserved interrupt
+    GFMRT_IRQHandler,            // 39 : Free Multi-rate timer (GFMRT). Global MRT interrupts
+    Reserved40_IRQHandler,       // 40 : Reserved interrupt
+    DMIC_IRQHandler,             // 41 : Digital microphone (DMIC) and DMIC subsystem
+    WKDEEPSLEEP_IRQHandler,      // 42 : Wake-up from deep sleep
+    HYPERVISOR_IRQHandler,       // 43 : Hypervisor service software interrupt
+    SECUREVIOLATION_IRQHandler,  // 44 : Secure violation
+    HWVAD_IRQHandler,            // 45 : Hardware Voice Activity Detector
+    Reserved46_IRQHandler,       // 46 : Reserved interrupt
+    Reserved47_IRQHandler,       // 47 : Reserved interrupt
+    RTC_IRQHandler,              // 48 : RTC alarm and wake-up
+    Reserved49_IRQHandler,       // 49 : Reserved interrupt
+    Reserved50_IRQHandler,       // 50 : Reserved interrupt
+    PIN_INT4_IRQHandler,         // 51 : Pin interrupt 4 or pattern match engine slice 4
+    PIN_INT5_IRQHandler,         // 52 : Pin interrupt 5 or pattern match engine slice 5
+    PIN_INT6_IRQHandler,         // 53 : Pin interrupt 6 or pattern match engine slice 6
+    PIN_INT7_IRQHandler,         // 54 : Pin interrupt 7 or pattern match engine slice 7
+    CTIMER2_IRQHandler,          // 55 : Standard counter/timer CTIMER2
+    CTIMER4_IRQHandler,          // 56 : Standard counter/timer CTIMER4
+    OS_EVENT_TIMER_IRQHandler,   // 57 : OS event timer 0
+    FLEXSPI_IRQHandler,          // 58 : FLEXSPI interface
+    Reserved59_IRQHandler,       // 59 : Reserved interrupt
+    Reserved60_IRQHandler,       // 60 : Reserved interrupt
+    Reserved61_IRQHandler,       // 61 : Reserved interrupt
+    SDIO_IRQHandler,             // 62 : The secure digital interface
+    SGPIO_INTA_IRQHandler,       // 63 : Secure GPIO interrupt A
+    SGPIO_INTB_IRQHandler,       // 64 : Secure GPIO interrupt B
+    Reserved65_IRQHandler,       // 65 : Reserved interrupt
+    USB_IRQHandler,              // 66 : High-speed USB device/host
+    Reserved67_IRQHandler,       // 67 : Reserved interrupt
+    Reserved68_IRQHandler,       // 68 : Reserved interrupt
+    Reserved69_IRQHandler,       // 69 : Reserved interrupt
+    DMA1_IRQHandler,             // 70 : DMA controller 1 (non-secure or HiFi 4 DMA)
+    PUF_IRQHandler,              // 71 : Physical Unclonable Function
+    POWERQUAD_IRQHandler,        // 72 : PowerQuad math coprocessor
+    Reserved73_IRQHandler,       // 73 : Reserved interrupt
+    Reserved74_IRQHandler,       // 74 : Reserved interrupt
+    Reserved75_IRQHandler,       // 75 : Reserved interrupt
+    Reserved76_IRQHandler,       // 76 : Reserved interrupt
+    LCD_IRQHandler,              // 77 : LCDIC
+    CAPTIMER_IRQHandler,         // 78 : Capture timer
+    Reserved79_IRQHandler,       // 79 : Reserved interrupt
+    W2MWKUP_DONE0_IRQHandler,    // 80 : Wi-Fi to MCU, wakeup done 0
+    W2MWKUP_DONE1_IRQHandler,    // 81 : Wi-Fi to MCU, wakeup done 1
+    W2MWKUP_DONE2_IRQHandler,    // 82 : Wi-Fi to MCU, wakeup done 2
+    W2MWKUP_DONE3_IRQHandler,    // 83 : Wi-Fi to MCU, wakeup done 3
+    W2MWKUP_DONE4_IRQHandler,    // 84 : Wi-Fi to MCU, wakeup done 4
+    W2MWKUP_DONE5_IRQHandler,    // 85 : Wi-Fi to MCU, wakeup done 5
+    W2MWKUP_DONE6_IRQHandler,    // 86 : Wi-Fi to MCU, wakeup done 6
+    W2MWKUP_DONE7_IRQHandler,    // 87 : Wi-Fi to MCU, wakeup done 7
+    W2MWKUP0_IRQHandler,         // 88 : Wi-Fi to MCU, wakeup signal 0
+    W2MWKUP1_IRQHandler,         // 89 : Wi-Fi to MCU, wakueup signal 1
+    WL_MCI_INT0_IRQHandler,      // 90 : Wi-Fi to MCU interrupt 0
+    WL_MCI_INT1_IRQHandler,      // 91 : Reserved for Wi-Fi to MCU
+    WL_MCI_INT2_IRQHandler,      // 92 : Reserved for Wi-Fi to MCU
+    WL_MCI_INT3_IRQHandler,      // 93 : Reserved for Wi-Fi to MCU
+    WL_MCI_INT4_IRQHandler,      // 94 : Reserved for Wi-Fi to MCU
+    WL_MCI_INT5_IRQHandler,      // 95 : Reserved for Wi-Fi to MCU
+    WL_MCI_INT6_IRQHandler,      // 96 : Reserved for Wi-Fi to MCU
+    WL_MCI_INT7_IRQHandler,      // 97 : Reserved for Wi-Fi to MCU
+    B2MWKUP_DONE0_IRQHandler,    // 98 : Bluetooth LE/802.15.4 radio to MCU, wakeup done 0
+    B2MWKUP_DONE1_IRQHandler,    // 99 : Bluetooth LE/802.15.4 radio to MCU, wakeup done 1
+    B2MWKUP_DONE2_IRQHandler,    // 100: Bluetooth LE/802.15.4 radio to MCU, wakeup done 2
+    B2MWKUP_DONE3_IRQHandler,    // 101: Bluetooth LE/802.15.4 radio to MCU, wakeup done 3
+    B2MWKUP_DONE4_IRQHandler,    // 102: Bluetooth LE/802.15.4 radio to MCU, wakeup done 4
+    B2MWKUP_DONE5_IRQHandler,    // 103: Bluetooth LE/802.15.4 radio to MCU, wakeup done 5
+    B2MWKUP_DONE6_IRQHandler,    // 104: Bluetooth LE/802.15.4 radio to MCU, wakeup done 6
+    B2MWKUP_DONE7_IRQHandler,    // 105: Bluetooth LE/802.15.4 radio to MCU, wakeup done 7
+    B2MWKUP0_IRQHandler,         // 106: Bluetooth LE/802.15.4 radio to MCU, wakeup signal 0
+    B2MWKUP1_IRQHandler,         // 107: Bluetooth LE/802.15.4 radio to MCU, wakeup signal 1
+    BLE_MCI_INT0_IRQHandler,     // 108: Bluetooth LE/802.15.4 radio to MCU interrupt 0
+    BLE_MCI_INT1_IRQHandler,     // 109: Reserved for Bluetooth LE/802.15.4 radio to MCU
+    BLE_MCI_INT2_IRQHandler,     // 110: Reserved for Bluetooth LE/802.15.4 radio to MCU
+    BLE_MCI_INT3_IRQHandler,     // 111: Reserved for Bluetooth LE/802.15.4 radio to MCU
+    BLE_MCI_INT4_IRQHandler,     // 112: Reserved for Bluetooth LE/802.15.4 radio to MCU
+    BLE_MCI_INT5_IRQHandler,     // 113: Reserved for Bluetooth LE/802.15.4 radio to MCU
+    BLE_MCI_INT6_IRQHandler,     // 114: Reserved for Bluetooth LE/802.15.4 radio to MCU
+    BLE_MCI_INT7_IRQHandler,     // 115: Reserved for Bluetooth LE/802.15.4 radio to MCU
+    PIN0_INT_IRQHandler,         // 116: From AON GPIO
+    PIN1_INT_IRQHandler,         // 117: From AON GPIO
+    ELS_IRQHandler,              // 118: EdgeLock subsystem (ELS)
+    ELS_GDET_IRQHandler,         // 119: ELS IRQ line for GDET error
+    ELS_GDET_UM_IRQHandler,      // 120: ELS un-gated latched error
+    PKC_INT_IRQHandler,          // 121: Public key crypto-processor (PKC) interrupt
+    PKC_ERR_IRQHandler,          // 122: PKC error
+    CDOG_INT_IRQHandler,         // 123: Code watch dog timmer interrupt
+    GAU_DAC_IRQHandler,          // 124: General analog unit (GAU) digital to analog converter (DAC)
+    GAU_ACOMP_WKUP_IRQHandler,   // 125: GAU analog comparator (ACOMP) wake-up
+    GAU_ACOMP_IRQHandler,        // 126: GAU analog comparator
+    GAU_ADC1_IRQHandler,         // 127: GAU analog to digital converter 1 (ADC1)
+    GAU_ADC0_IRQHandler,         // 128: GAU analog to digital converter 0 (ADC0)
+    USIM_IRQHandler,             // 129: Universal subscriber identity module (USIM) interface
+    OTP_IRQHandler,              // 130: One time programmable (OTP) memory interrupt
+    ENET_IRQHandler,             // 131: Etheret interrupt
+    ENET_TIMER_IRQHandler,       // 132: Ethernet timer interrupt
+    PMIP_IRQHandler,             // 133: Power management IP (PMIP)
+    PMIP_CHANGE_IRQHandler,      // 134: PMIP change from 1 to 0
+    ITRC_IRQHandler,             // 135: Intrusion and tamper response controller (ITRC) interrupt request
+    Reserved136_IRQHandler,      // 136: Reserved interrupt
+    Reserved137_IRQHandler,      // 137: Reserved interrupt
+    Reserved138_IRQHandler,      // 138: Reserved interrupt
+    TRNG_IRQHandler,             // 139: TRNG interrupt request
+    ACC_C_INT_IRQHandler,        // 140: AHB memory access checker - Cortex-M33 code bus
+    ACC_S_INT_IRQHandler,        // 141: AHB memory access checker - Cortex-M33 sys bus
+    WACC_IRQHandler,             // 142: Wi-Fi accessed during power off
+    BACC_IRQHandler,             // 143: Bluetooth LE/802.15.4 radio accessed during power off
+    GDMA_IRQHandler,             // 144: General purpose direct memory access (GDMA) interrupt
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((naked, section(".after_vectors.reset")))
+void ResetISR(void) {
+    // Disable interrupts
+    __asm volatile ("cpsid i");
+    // Config VTOR & MSPLIM register
+    __asm volatile ("LDR R0, =0xE000ED08  \n"
+                    "STR %0, [R0]         \n"
+                    "LDR R1, [%0]         \n"
+                    "MSR MSP, R1          \n"
+                    "MSR MSPLIM, %1       \n"
+                    :
+                    : "r"(g_pfnVectors), "r"(_vStackBase)
+                    : "r0", "r1");
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+    SystemInit();
+
+#endif // (__USE_CMSIS)
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+    // Reenable interrupts
+    __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void HardFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void MemManage_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void BusFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SecureFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SVC_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void PendSV_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void WDT0_IRQHandler(void)
+{   WDT0_DriverIRQHandler();
+}
+
+WEAK void DMA0_IRQHandler(void)
+{   DMA0_DriverIRQHandler();
+}
+
+WEAK void GPIO_INTA_IRQHandler(void)
+{   GPIO_INTA_DriverIRQHandler();
+}
+
+WEAK void GPIO_INTB_IRQHandler(void)
+{   GPIO_INTB_DriverIRQHandler();
+}
+
+WEAK void PIN_INT0_IRQHandler(void)
+{   PIN_INT0_DriverIRQHandler();
+}
+
+WEAK void PIN_INT1_IRQHandler(void)
+{   PIN_INT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT2_IRQHandler(void)
+{   PIN_INT2_DriverIRQHandler();
+}
+
+WEAK void PIN_INT3_IRQHandler(void)
+{   PIN_INT3_DriverIRQHandler();
+}
+
+WEAK void UTICK_IRQHandler(void)
+{   UTICK_DriverIRQHandler();
+}
+
+WEAK void MRT_IRQHandler(void)
+{   MRT_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{   CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{   CTIMER1_DriverIRQHandler();
+}
+
+WEAK void SCT0_IRQHandler(void)
+{   SCT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER3_IRQHandler(void)
+{   CTIMER3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM0_IRQHandler(void)
+{   FLEXCOMM0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM1_IRQHandler(void)
+{   FLEXCOMM1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM2_IRQHandler(void)
+{   FLEXCOMM2_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM3_IRQHandler(void)
+{   FLEXCOMM3_DriverIRQHandler();
+}
+
+WEAK void Reserved34_IRQHandler(void)
+{   Reserved34_DriverIRQHandler();
+}
+
+WEAK void Reserved35_IRQHandler(void)
+{   Reserved35_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM14_IRQHandler(void)
+{   FLEXCOMM14_DriverIRQHandler();
+}
+
+WEAK void Reserved37_IRQHandler(void)
+{   Reserved37_DriverIRQHandler();
+}
+
+WEAK void Reserved38_IRQHandler(void)
+{   Reserved38_DriverIRQHandler();
+}
+
+WEAK void GFMRT_IRQHandler(void)
+{   GFMRT_DriverIRQHandler();
+}
+
+WEAK void Reserved40_IRQHandler(void)
+{   Reserved40_DriverIRQHandler();
+}
+
+WEAK void DMIC_IRQHandler(void)
+{   DMIC_DriverIRQHandler();
+}
+
+WEAK void WKDEEPSLEEP_IRQHandler(void)
+{   WKDEEPSLEEP_DriverIRQHandler();
+}
+
+WEAK void HYPERVISOR_IRQHandler(void)
+{   HYPERVISOR_DriverIRQHandler();
+}
+
+WEAK void SECUREVIOLATION_IRQHandler(void)
+{   SECUREVIOLATION_DriverIRQHandler();
+}
+
+WEAK void HWVAD_IRQHandler(void)
+{   HWVAD_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{   Reserved46_DriverIRQHandler();
+}
+
+WEAK void Reserved47_IRQHandler(void)
+{   Reserved47_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{   RTC_DriverIRQHandler();
+}
+
+WEAK void Reserved49_IRQHandler(void)
+{   Reserved49_DriverIRQHandler();
+}
+
+WEAK void Reserved50_IRQHandler(void)
+{   Reserved50_DriverIRQHandler();
+}
+
+WEAK void PIN_INT4_IRQHandler(void)
+{   PIN_INT4_DriverIRQHandler();
+}
+
+WEAK void PIN_INT5_IRQHandler(void)
+{   PIN_INT5_DriverIRQHandler();
+}
+
+WEAK void PIN_INT6_IRQHandler(void)
+{   PIN_INT6_DriverIRQHandler();
+}
+
+WEAK void PIN_INT7_IRQHandler(void)
+{   PIN_INT7_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{   CTIMER2_DriverIRQHandler();
+}
+
+WEAK void CTIMER4_IRQHandler(void)
+{   CTIMER4_DriverIRQHandler();
+}
+
+WEAK void OS_EVENT_TIMER_IRQHandler(void)
+{   OS_EVENT_TIMER_DriverIRQHandler();
+}
+
+WEAK void FLEXSPI_IRQHandler(void)
+{   FLEXSPI_DriverIRQHandler();
+}
+
+WEAK void Reserved59_IRQHandler(void)
+{   Reserved59_DriverIRQHandler();
+}
+
+WEAK void Reserved60_IRQHandler(void)
+{   Reserved60_DriverIRQHandler();
+}
+
+WEAK void Reserved61_IRQHandler(void)
+{   Reserved61_DriverIRQHandler();
+}
+
+WEAK void SDIO_IRQHandler(void)
+{   SDIO_DriverIRQHandler();
+}
+
+WEAK void SGPIO_INTA_IRQHandler(void)
+{   SGPIO_INTA_DriverIRQHandler();
+}
+
+WEAK void SGPIO_INTB_IRQHandler(void)
+{   SGPIO_INTB_DriverIRQHandler();
+}
+
+WEAK void Reserved65_IRQHandler(void)
+{   Reserved65_DriverIRQHandler();
+}
+
+WEAK void USB_IRQHandler(void)
+{   USB_DriverIRQHandler();
+}
+
+WEAK void Reserved67_IRQHandler(void)
+{   Reserved67_DriverIRQHandler();
+}
+
+WEAK void Reserved68_IRQHandler(void)
+{   Reserved68_DriverIRQHandler();
+}
+
+WEAK void Reserved69_IRQHandler(void)
+{   Reserved69_DriverIRQHandler();
+}
+
+WEAK void DMA1_IRQHandler(void)
+{   DMA1_DriverIRQHandler();
+}
+
+WEAK void PUF_IRQHandler(void)
+{   PUF_DriverIRQHandler();
+}
+
+WEAK void POWERQUAD_IRQHandler(void)
+{   POWERQUAD_DriverIRQHandler();
+}
+
+WEAK void Reserved73_IRQHandler(void)
+{   Reserved73_DriverIRQHandler();
+}
+
+WEAK void Reserved74_IRQHandler(void)
+{   Reserved74_DriverIRQHandler();
+}
+
+WEAK void Reserved75_IRQHandler(void)
+{   Reserved75_DriverIRQHandler();
+}
+
+WEAK void Reserved76_IRQHandler(void)
+{   Reserved76_DriverIRQHandler();
+}
+
+WEAK void LCD_IRQHandler(void)
+{   LCD_DriverIRQHandler();
+}
+
+WEAK void CAPTIMER_IRQHandler(void)
+{   CAPTIMER_DriverIRQHandler();
+}
+
+WEAK void Reserved79_IRQHandler(void)
+{   Reserved79_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE0_IRQHandler(void)
+{   W2MWKUP_DONE0_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE1_IRQHandler(void)
+{   W2MWKUP_DONE1_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE2_IRQHandler(void)
+{   W2MWKUP_DONE2_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE3_IRQHandler(void)
+{   W2MWKUP_DONE3_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE4_IRQHandler(void)
+{   W2MWKUP_DONE4_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE5_IRQHandler(void)
+{   W2MWKUP_DONE5_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE6_IRQHandler(void)
+{   W2MWKUP_DONE6_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP_DONE7_IRQHandler(void)
+{   W2MWKUP_DONE7_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP0_IRQHandler(void)
+{   W2MWKUP0_DriverIRQHandler();
+}
+
+WEAK void W2MWKUP1_IRQHandler(void)
+{   W2MWKUP1_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT0_IRQHandler(void)
+{   WL_MCI_INT0_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT1_IRQHandler(void)
+{   WL_MCI_INT1_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT2_IRQHandler(void)
+{   WL_MCI_INT2_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT3_IRQHandler(void)
+{   WL_MCI_INT3_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT4_IRQHandler(void)
+{   WL_MCI_INT4_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT5_IRQHandler(void)
+{   WL_MCI_INT5_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT6_IRQHandler(void)
+{   WL_MCI_INT6_DriverIRQHandler();
+}
+
+WEAK void WL_MCI_INT7_IRQHandler(void)
+{   WL_MCI_INT7_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE0_IRQHandler(void)
+{   B2MWKUP_DONE0_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE1_IRQHandler(void)
+{   B2MWKUP_DONE1_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE2_IRQHandler(void)
+{   B2MWKUP_DONE2_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE3_IRQHandler(void)
+{   B2MWKUP_DONE3_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE4_IRQHandler(void)
+{   B2MWKUP_DONE4_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE5_IRQHandler(void)
+{   B2MWKUP_DONE5_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE6_IRQHandler(void)
+{   B2MWKUP_DONE6_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP_DONE7_IRQHandler(void)
+{   B2MWKUP_DONE7_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP0_IRQHandler(void)
+{   B2MWKUP0_DriverIRQHandler();
+}
+
+WEAK void B2MWKUP1_IRQHandler(void)
+{   B2MWKUP1_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT0_IRQHandler(void)
+{   BLE_MCI_INT0_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT1_IRQHandler(void)
+{   BLE_MCI_INT1_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT2_IRQHandler(void)
+{   BLE_MCI_INT2_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT3_IRQHandler(void)
+{   BLE_MCI_INT3_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT4_IRQHandler(void)
+{   BLE_MCI_INT4_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT5_IRQHandler(void)
+{   BLE_MCI_INT5_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT6_IRQHandler(void)
+{   BLE_MCI_INT6_DriverIRQHandler();
+}
+
+WEAK void BLE_MCI_INT7_IRQHandler(void)
+{   BLE_MCI_INT7_DriverIRQHandler();
+}
+
+WEAK void PIN0_INT_IRQHandler(void)
+{   PIN0_INT_DriverIRQHandler();
+}
+
+WEAK void PIN1_INT_IRQHandler(void)
+{   PIN1_INT_DriverIRQHandler();
+}
+
+WEAK void ELS_IRQHandler(void)
+{   ELS_DriverIRQHandler();
+}
+
+WEAK void ELS_GDET_IRQHandler(void)
+{   ELS_GDET_DriverIRQHandler();
+}
+
+WEAK void ELS_GDET_UM_IRQHandler(void)
+{   ELS_GDET_UM_DriverIRQHandler();
+}
+
+WEAK void PKC_INT_IRQHandler(void)
+{   PKC_INT_DriverIRQHandler();
+}
+
+WEAK void PKC_ERR_IRQHandler(void)
+{   PKC_ERR_DriverIRQHandler();
+}
+
+WEAK void CDOG_INT_IRQHandler(void)
+{   CDOG_INT_DriverIRQHandler();
+}
+
+WEAK void GAU_DAC_IRQHandler(void)
+{   GAU_DAC_DriverIRQHandler();
+}
+
+WEAK void GAU_ACOMP_WKUP_IRQHandler(void)
+{   GAU_ACOMP_WKUP_DriverIRQHandler();
+}
+
+WEAK void GAU_ACOMP_IRQHandler(void)
+{   GAU_ACOMP_DriverIRQHandler();
+}
+
+WEAK void GAU_ADC1_IRQHandler(void)
+{   GAU_ADC1_DriverIRQHandler();
+}
+
+WEAK void GAU_ADC0_IRQHandler(void)
+{   GAU_ADC0_DriverIRQHandler();
+}
+
+WEAK void USIM_IRQHandler(void)
+{   USIM_DriverIRQHandler();
+}
+
+WEAK void OTP_IRQHandler(void)
+{   OTP_DriverIRQHandler();
+}
+
+WEAK void ENET_IRQHandler(void)
+{   ENET_DriverIRQHandler();
+}
+
+WEAK void ENET_TIMER_IRQHandler(void)
+{   ENET_TIMER_DriverIRQHandler();
+}
+
+WEAK void PMIP_IRQHandler(void)
+{   PMIP_DriverIRQHandler();
+}
+
+WEAK void PMIP_CHANGE_IRQHandler(void)
+{   PMIP_CHANGE_DriverIRQHandler();
+}
+
+WEAK void ITRC_IRQHandler(void)
+{   ITRC_DriverIRQHandler();
+}
+
+WEAK void Reserved136_IRQHandler(void)
+{   Reserved136_DriverIRQHandler();
+}
+
+WEAK void Reserved137_IRQHandler(void)
+{   Reserved137_DriverIRQHandler();
+}
+
+WEAK void Reserved138_IRQHandler(void)
+{   Reserved138_DriverIRQHandler();
+}
+
+WEAK void TRNG_IRQHandler(void)
+{   TRNG_DriverIRQHandler();
+}
+
+WEAK void ACC_C_INT_IRQHandler(void)
+{   ACC_C_INT_DriverIRQHandler();
+}
+
+WEAK void ACC_S_INT_IRQHandler(void)
+{   ACC_S_INT_DriverIRQHandler();
+}
+
+WEAK void WACC_IRQHandler(void)
+{   WACC_DriverIRQHandler();
+}
+
+WEAK void BACC_IRQHandler(void)
+{   BACC_DriverIRQHandler();
+}
+
+WEAK void GDMA_IRQHandler(void)
+{   GDMA_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_assert.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_assert.c
new file mode 100644
index 0000000000..bd2b568ab3
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_assert.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2022-2023 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_assert.h"
+#include "fsl_debug_console.h"
+
+/* User can implement its own asser handler (dump logs, registers, etc) by reimplementing the function fsl_assert_hook() */
+__attribute__ ((weak)) int fsl_assert_hook(const char *failedExpr, const char *file, int line)
+{
+    (void)failedExpr;
+    (void)file;
+    (void)line;
+
+    return 0;
+}
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#else
+    (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#endif
+
+    (void)fsl_assert_hook(failedExpr, file, line);
+
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif (defined(__GNUC__))
+#if defined(__REDLIB__)
+void __assertion_failed(char *failedExpr)
+{
+    const char *file = NULL;
+    int line = -1;
+
+    (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr);
+
+    (void)fsl_assert_hook(failedExpr, file, line);
+
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#else
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line,
+                 func);
+
+    (void)fsl_assert_hook(failedExpr, file, line);
+
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* defined(__REDLIB__) */
+#else  /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+
+#if (defined(__DSC__) && defined(__CW__))
+
+void __msl_assertion_failed(char const *failedExpr, char const *file, char const *func, int line)
+{
+    PRINTF("\r\nASSERT ERROR\r\n");
+    PRINTF("  File      : %s\r\n", file);
+    PRINTF("  Function  : %s\r\n", func); /*compiler not support func name yet*/
+    PRINTF("  Line      : %u\r\n", (uint32_t)line);
+    PRINTF("  failedExpr: %s\r\n", failedExpr);
+    asm(DEBUGHLT);
+}
+
+#endif /* (defined(__DSC__) && defined (__CW__)) */
+
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+#endif /* NDEBUG */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_assert.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_assert.h
new file mode 100644
index 0000000000..ed7f2713e5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_assert.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_ASSERT_H_
+#define _FSL_ASSERT_H_
+
+/*!
+ * @addtogroup assert
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+
+/*!
+ * @brief Assert hook that can be redifined
+ *
+ * @param failedExpr  Expression that caused the assert
+ * @param file  File where the exception occured.
+ * @param line  Line on the file where the exception occured.
+ */
+int fsl_assert_hook(const char *failedExpr, const char *file, int line);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console.c
new file mode 100644
index 0000000000..2413a242ed
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console.c
@@ -0,0 +1,1426 @@
+/*
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ *      1999-2000 MOTOROLA, INC. All Rights Reserved.
+ *  You are hereby granted a copyright license to use, modify, and
+ *  distribute the SOFTWARE so long as this entire notice is
+ *  retained without alteration in any modified and/or redistributed
+ *  versions, and that such modified versions are clearly identified
+ *  as such. No licenses are granted by implication, estoppel or
+ *  otherwise under any patents or trademarks of Motorola, Inc. This
+ *  software is provided on an "AS IS" basis and without warranty.
+ *
+ *  To the maximum extent permitted by applicable law, MOTOROLA
+ *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ *  ACCOMPANYING WRITTEN MATERIALS.
+ *
+ *  To the maximum extent permitted by applicable law, IN NO EVENT
+ *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ *  Motorola assumes no responsibility for the maintenance and support
+ *  of this software
+
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, 2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#include <stdio.h>
+#endif
+
+#include "fsl_debug_console_conf.h"
+#include "fsl_str.h"
+
+#include "fsl_common.h"
+#include "fsl_component_serial_manager.h"
+
+#include "fsl_debug_console.h"
+
+#ifdef SDK_OS_FREE_RTOS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#else
+/* MISRA C-2012 Rule 17.2 */
+#undef assert
+#define assert(n) \
+    while (!(n))  \
+    {             \
+        ;         \
+    }
+#endif
+#endif
+
+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))
+#define DEBUG_CONSOLE_FUNCTION_PREFIX
+#else
+#define DEBUG_CONSOLE_FUNCTION_PREFIX static
+#endif
+
+/*! @brief character backspace ASCII value */
+#define DEBUG_CONSOLE_BACKSPACE 127U
+
+/* lock definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+static SemaphoreHandle_t s_debugConsoleReadSemaphore;
+#if configSUPPORT_STATIC_ALLOCATION
+static StaticSemaphore_t s_debugConsoleReadSemaphoreStatic;
+#endif
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;
+#if configSUPPORT_STATIC_ALLOCATION
+static StaticSemaphore_t s_debugConsoleReadWaitSemaphoreStatic;
+#endif
+#endif
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static volatile bool s_debugConsoleReadWaitSemaphore;
+#endif
+
+#else
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+/*! @brief get current runing environment is ISR or not */
+#ifdef __CA7_REV
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
+#else
+#define IS_RUNNING_IN_ISR() __get_IPSR()
+#endif /* __CA7_REV */
+
+/* semaphore definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+/* mutex semaphore */
+/* clang-format off */
+#if configSUPPORT_STATIC_ALLOCATION
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex, stack) ((mutex) = xSemaphoreCreateMutexStatic(stack))
+#else
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())
+#endif
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)   \
+        do                                             \
+        {                                              \
+            if(NULL != (mutex))                        \
+            {                                          \
+                vSemaphoreDelete(mutex);               \
+                (mutex) = NULL;                          \
+            }                                          \
+        } while(false)
+
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \
+{                                                 \
+        if (IS_RUNNING_IN_ISR() == 0U)            \
+        {                                         \
+            (void)xSemaphoreGive(mutex);          \
+        }                                         \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \
+{                                                          \
+        if (IS_RUNNING_IN_ISR() == 0U)                     \
+        {                                                  \
+            (void)xSemaphoreTake(mutex, portMAX_DELAY);    \
+        }                                                  \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
+{                                                                     \
+        if (IS_RUNNING_IN_ISR() == 0U)                                \
+        {                                                             \
+            result = xSemaphoreTake(mutex, 0U);                       \
+        }                                                             \
+        else                                                          \
+        {                                                             \
+            result = 1U;                                              \
+        }                                                             \
+}
+
+/* Binary semaphore */
+#if configSUPPORT_STATIC_ALLOCATION
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary,stack) ((binary) = xSemaphoreCreateBinaryStatic(stack))
+#else
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())
+#endif
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \
+        do                                             \
+        {                                              \
+            if(NULL != (binary))                       \
+            {                                          \
+                vSemaphoreDelete((binary));              \
+                (binary) = NULL;                         \
+            }                                          \
+        } while(false)
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake((binary), portMAX_DELAY))
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR((binary), NULL))
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)
+
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)         (void)(mutex)
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)        (void)(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)  (void)(mutex)
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)           (void)(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)       (void)(binary)
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary)      (void)(binary)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
+    {                                                        \
+        while (!(binary))                                    \
+        {                                                    \
+        }                                                    \
+        (binary) = false;                                      \
+    }
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) \
+    do                                                       \
+    {                                                        \
+        (binary) = true;                                       \
+    } while(false)
+#else
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)  (void)(binary)
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)  (void)(binary)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+/* clang-format on */
+
+/* add other implementation here
+ *such as :
+ * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)
+ */
+
+#else
+
+#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/* receive state structure */
+typedef struct _debug_console_write_ring_buffer
+{
+    uint32_t ringBufferSize;
+    volatile uint32_t ringHead;
+    volatile uint32_t ringTail;
+    uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];
+} debug_console_write_ring_buffer_t;
+#endif
+
+typedef struct _debug_console_state_struct
+{
+    serial_handle_t serialHandle; /*!< serial manager handle */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    SERIAL_MANAGER_HANDLE_DEFINE(serialHandleBuffer);
+    debug_console_write_ring_buffer_t writeRingBuffer;
+    uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];
+    SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer);
+    SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer2);
+    SERIAL_MANAGER_READ_HANDLE_DEFINE(serialReadHandleBuffer);
+#else
+    SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(serialHandleBuffer);
+    SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(serialWriteHandleBuffer);
+    SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(serialReadHandleBuffer);
+#endif
+} debug_console_state_struct_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Debug console state information. */
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0))
+AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState);
+#else
+static debug_console_state_struct_t s_debugConsoleState;
+#endif
+serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief This is a printf call back function which is used to relocate the log to buffer
+ * or print the log immediately when the local buffer is full.
+ *
+ * @param[in] buf   Buffer to store log.
+ * @param[in] indicator Buffer index.
+ * @param[in] val Target character to store.
+ * @param[in] len length of the character
+ *
+ */
+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len);
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch);
+int DbgConsole_SendData(uint8_t *ch, size_t size);
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size);
+int DbgConsole_ReadLine(uint8_t *buf, size_t size);
+int DbgConsole_ReadCharacter(uint8_t *ch);
+
+#if ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+     (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+static status_t DbgConsole_SerialManagerPerformTransfer(debug_console_state_struct_t *ioState)
+{
+    serial_manager_status_t ret = kStatus_SerialManager_Error;
+    uint32_t sendDataLength;
+    uint32_t startIndex;
+    uint32_t regPrimask;
+
+    regPrimask = DisableGlobalIRQ();
+    if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)
+    {
+        if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)
+        {
+            sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;
+            startIndex     = ioState->writeRingBuffer.ringTail;
+        }
+        else
+        {
+            sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;
+            startIndex     = ioState->writeRingBuffer.ringTail;
+            if (0U != ioState->writeRingBuffer.ringHead)
+            {
+                ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer2[0]),
+                                                     &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength);
+                sendDataLength = ioState->writeRingBuffer.ringHead - 0U;
+                startIndex     = 0U;
+            }
+        }
+        ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),
+                                             &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength);
+    }
+    EnableGlobalIRQ(regPrimask);
+    return (status_t)ret;
+}
+
+static void DbgConsole_SerialManagerTxCallback(void *callbackParam,
+                                               serial_manager_callback_message_t *message,
+                                               serial_manager_status_t serialManagerStatus)
+{
+    debug_console_state_struct_t *ioState;
+
+    if ((NULL == callbackParam) || (NULL == message))
+    {
+        return;
+    }
+
+    ioState = (debug_console_state_struct_t *)callbackParam;
+
+    ioState->writeRingBuffer.ringTail += message->length;
+    if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)
+    {
+        ioState->writeRingBuffer.ringTail = 0U;
+    }
+
+    if (kStatus_SerialManager_Success == serialManagerStatus)
+    {
+        (void)DbgConsole_SerialManagerPerformTransfer(ioState);
+    }
+    else if (kStatus_SerialManager_Canceled == serialManagerStatus)
+    {
+        ioState->writeRingBuffer.ringTail = 0U;
+        ioState->writeRingBuffer.ringHead = 0U;
+    }
+    else
+    {
+        /*MISRA rule 16.4*/
+    }
+}
+
+static void DbgConsole_SerialManagerTx2Callback(void *callbackParam,
+                                                serial_manager_callback_message_t *message,
+                                                serial_manager_status_t serialManagerStatus)
+{
+    debug_console_state_struct_t *ioState;
+
+    if ((NULL == callbackParam) || (NULL == message))
+    {
+        return;
+    }
+
+    ioState = (debug_console_state_struct_t *)callbackParam;
+
+    ioState->writeRingBuffer.ringTail += message->length;
+    if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)
+    {
+        ioState->writeRingBuffer.ringTail = 0U;
+    }
+
+    if (kStatus_SerialManager_Success == serialManagerStatus)
+    {
+        /* Empty block*/
+    }
+    else if (kStatus_SerialManager_Canceled == serialManagerStatus)
+    {
+        /* Empty block*/
+    }
+    else
+    {
+        /*MISRA rule 16.4*/
+    }
+}
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+static void DbgConsole_SerialManagerRxCallback(void *callbackParam,
+                                               serial_manager_callback_message_t *message,
+                                               serial_manager_status_t serialManagerStatus)
+{
+    if ((NULL == callbackParam) || (NULL == message))
+    {
+        return;
+    }
+
+    if (kStatus_SerialManager_Notify == serialManagerStatus)
+    {
+    }
+    else if (kStatus_SerialManager_Success == serialManagerStatus)
+    {
+        /* release s_debugConsoleReadWaitSemaphore from RX callback */
+        DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);
+    }
+    else
+    {
+        /*MISRA rule 16.4*/
+    }
+}
+#endif
+
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+    (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+    return (status_t)kStatus_Fail;
+#else  /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \
+          DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Error;
+
+/* recieve one char every time */
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    serialManagerStatus =
+        SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#else  /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/
+    serialManagerStatus =
+        SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/
+    if (kStatus_SerialManager_Success != serialManagerStatus)
+    {
+        serialManagerStatus = (serial_manager_status_t)kStatus_Fail;
+    }
+    else
+    {
+        /* wait s_debugConsoleReadWaitSemaphore from RX callback */
+        DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);
+        serialManagerStatus = (serial_manager_status_t)kStatus_Success;
+    }
+    return (status_t)serialManagerStatus;
+#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \
+          DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/
+
+#else  /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/
+
+    return (status_t)kStatus_Fail;
+
+#endif /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/
+}
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+{
+    /* Due to scanf take \n and \r as end of string,should not echo */
+    if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar))
+    {
+        /* recieve one char every time */
+        if (1 != DbgConsole_SendDataReliable(ch, 1U))
+        {
+            return (status_t)kStatus_Fail;
+        }
+    }
+
+    if ((!isGetChar) && (index != NULL))
+    {
+        if (DEBUG_CONSOLE_BACKSPACE == *ch)
+        {
+            if ((*index >= 2))
+            {
+                *index -= 2;
+            }
+            else
+            {
+                *index = 0;
+            }
+        }
+    }
+
+    return (status_t)kStatus_Success;
+}
+#endif
+
+int DbgConsole_SendData(uint8_t *ch, size_t size)
+{
+    status_t dbgConsoleStatus;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    uint32_t sendDataLength;
+    int txBusy = 0;
+#endif
+    assert(NULL != ch);
+    assert(0U != size);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    uint32_t regPrimask = DisableGlobalIRQ();
+    if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+    {
+        txBusy = 1;
+        sendDataLength =
+            (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+             s_debugConsoleState.writeRingBuffer.ringTail) %
+            s_debugConsoleState.writeRingBuffer.ringBufferSize;
+    }
+    else
+    {
+        sendDataLength = 0U;
+    }
+    sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
+    if (sendDataLength < size)
+    {
+        EnableGlobalIRQ(regPrimask);
+        return -1;
+    }
+    for (int i = 0; i < (int)size; i++)
+    {
+        s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];
+        if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)
+        {
+            s_debugConsoleState.writeRingBuffer.ringHead = 0U;
+        }
+    }
+
+    dbgConsoleStatus = (status_t)kStatus_SerialManager_Success;
+
+    if (txBusy == 0)
+    {
+        dbgConsoleStatus = DbgConsole_SerialManagerPerformTransfer(&s_debugConsoleState);
+    }
+    EnableGlobalIRQ(regPrimask);
+#else
+    dbgConsoleStatus = (status_t)SerialManager_WriteBlocking(
+        ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+#endif
+    return (((status_t)kStatus_Success == dbgConsoleStatus) ? (int)size : -1);
+}
+
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Error;
+    uint32_t sendDataLength;
+    uint32_t totalLength = size;
+    int sentLength;
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+#else  /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+    serial_manager_status_t serialManagerStatus;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+    assert(NULL != ch);
+
+    if (0U == size)
+    {
+        return 0;
+    }
+
+    if (NULL == g_serialHandle)
+    {
+        return 0;
+    }
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+    do
+    {
+        uint32_t regPrimask = DisableGlobalIRQ();
+        if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+        {
+            sendDataLength =
+                (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+                 s_debugConsoleState.writeRingBuffer.ringTail) %
+                s_debugConsoleState.writeRingBuffer.ringBufferSize;
+        }
+        else
+        {
+            sendDataLength = 0U;
+        }
+        sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
+
+        if ((sendDataLength > 0U) && ((sendDataLength >= totalLength) ||
+                                      (totalLength >= (s_debugConsoleState.writeRingBuffer.ringBufferSize - 1U))))
+        {
+            if (sendDataLength > totalLength)
+            {
+                sendDataLength = totalLength;
+            }
+
+            sentLength = DbgConsole_SendData(&ch[size - totalLength], (size_t)sendDataLength);
+            if (sentLength > 0)
+            {
+                totalLength = totalLength - (uint32_t)sentLength;
+            }
+        }
+        EnableGlobalIRQ(regPrimask);
+
+        if (totalLength != 0U)
+        {
+            serialManagerStatus = (serial_manager_status_t)DbgConsole_Flush();
+            if (kStatus_SerialManager_Success != serialManagerStatus)
+            {
+                break;
+            }
+        }
+    } while (totalLength != 0U);
+    return ((int)size - (int)totalLength);
+#else  /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+    return DbgConsole_SendData(ch, size);
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else  /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+    serialManagerStatus =
+        SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+    return ((kStatus_SerialManager_Success == serialManagerStatus) ? (int)size : -1);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+}
+
+int DbgConsole_ReadLine(uint8_t *buf, size_t size)
+{
+    int i = 0;
+
+    assert(buf != NULL);
+
+    if (NULL == g_serialHandle)
+    {
+        return -1;
+    }
+
+    /* take mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+#endif
+
+    do
+    {
+        /* recieve one char every time */
+        if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))
+        {
+            /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+            DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+            i = -1;
+            break;
+        }
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        (void)DbgConsole_EchoCharacter(&buf[i], false, &i);
+#endif
+        /* analysis data */
+        if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i]))
+        {
+            /* End of Line. */
+            if (0 == i)
+            {
+                buf[i] = (uint8_t)'\0';
+                continue;
+            }
+            else
+            {
+                break;
+            }
+        }
+        i++;
+    } while (i < (int)size);
+
+    /* get char should not add '\0'*/
+    if (i == (int)size)
+    {
+        buf[i] = (uint8_t)'\0';
+    }
+    else
+    {
+        buf[i + 1] = (uint8_t)'\0';
+    }
+
+    /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+
+    return i;
+}
+
+int DbgConsole_ReadCharacter(uint8_t *ch)
+{
+    int ret;
+
+    assert(ch);
+
+    if (NULL == g_serialHandle)
+    {
+        return -1;
+    }
+
+    /* take mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+#endif
+    /* read one character */
+    if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))
+    {
+        ret = 1;
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        (void)DbgConsole_EchoCharacter(ch, true, NULL);
+#endif
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+
+    return ret;
+}
+
+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len)
+{
+    int i = 0;
+
+    for (i = 0; i < len; i++)
+    {
+        if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+        {
+            (void)DbgConsole_SendDataReliable((uint8_t *)buf, (size_t)(*indicator));
+            *indicator = 0;
+        }
+
+        buf[*indicator] = dbgVal;
+        (*indicator)++;
+    }
+}
+#endif
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U))
+#include "board.h"
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+static const serial_port_uart_config_t uartConfig = {.instance     = BOARD_DEBUG_UART_INSTANCE,
+                                                     .clockRate    = BOARD_DEBUG_UART_CLK_FREQ,
+                                                     .baudRate     = BOARD_DEBUG_UART_BAUDRATE,
+                                                     .parityMode   = kSerialManager_UartParityDisabled,
+                                                     .stopBitCount = kSerialManager_UartOneStopBit,
+                                                     .enableRx     = 1U,
+                                                     .enableTx     = 1U,
+                                                     .enableRxRTS  = 0U,
+                                                     .enableTxCTS  = 0U,
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+                                                     .txFifoWatermark = 0U,
+                                                     .rxFifoWatermark = 0U
+#endif
+};
+#endif
+#endif
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
+{
+    serial_manager_config_t serialConfig;
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
+
+#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U))
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+    serial_port_uart_config_t uartConfig = {
+        .instance     = instance,
+        .clockRate    = clkSrcFreq,
+        .baudRate     = baudRate,
+        .parityMode   = kSerialManager_UartParityDisabled,
+        .stopBitCount = kSerialManager_UartOneStopBit,
+        .enableRx     = 1,
+        .enableTx     = 1,
+        .enableRxRTS  = 0U,
+        .enableTxCTS  = 0U,
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+        .txFifoWatermark = 0U,
+        .rxFifoWatermark = 0U
+#endif
+    };
+#endif
+#endif
+    (void)memset(&serialConfig, 0x0, sizeof(serial_manager_config_t));
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+    serial_port_usb_cdc_config_t usbCdcConfig = {
+        .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,
+    };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+    serial_port_swo_config_t swoConfig = {
+        .clockRate = clkSrcFreq,
+        .baudRate  = baudRate,
+        .port      = instance,
+        .protocol  = kSerialManager_SwoProtocolNrz,
+    };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+    serial_port_virtual_config_t serialPortVirtualConfig = {
+        .controllerIndex = (serial_port_virtual_controller_index_t)instance,
+    };
+#endif
+
+    serialConfig.type = device;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    serialConfig.ringBuffer     = &s_debugConsoleState.readRingBuffer[0];
+    serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;
+    serialConfig.blockType      = kSerialManager_NonBlocking;
+#else
+    serialConfig.blockType = kSerialManager_Blocking;
+#endif
+
+    if (kSerialPort_Uart == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U))
+        serialConfig.portConfig = (void *)&uartConfig;
+#else
+        serialConfig.portConfig = &uartConfig;
+#endif
+#else
+        serialManagerStatus = kStatus_SerialManager_Error;
+#endif
+    }
+    else if (kSerialPort_UsbCdc == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        serialConfig.portConfig = &usbCdcConfig;
+#else
+        serialManagerStatus = kStatus_SerialManager_Error;
+#endif
+    }
+    else if (kSerialPort_Swo == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        serialConfig.portConfig = &swoConfig;
+#else
+        serialManagerStatus = kStatus_SerialManager_Error;
+#endif
+    }
+    else if (kSerialPort_Virtual == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        serialConfig.portConfig = &serialPortVirtualConfig;
+#else
+        serialManagerStatus = kStatus_SerialManager_Error;
+#endif
+    }
+    else if (kSerialPort_BleWu == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
+        serialConfig.portConfig = NULL;
+#else
+        serialManagerStatus = kStatus_SerialManager_Error;
+#endif
+    }
+    else
+    {
+        serialManagerStatus = kStatus_SerialManager_Error;
+    }
+
+    if (kStatus_SerialManager_Error != serialManagerStatus)
+    {
+        (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState));
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+        s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;
+#endif
+
+        s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];
+        serialManagerStatus              = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);
+
+        assert(kStatus_SerialManager_Success == serialManagerStatus);
+
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+#if configSUPPORT_STATIC_ALLOCATION
+        DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore, &s_debugConsoleReadSemaphoreStatic);
+#else
+        DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+#endif
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) && configSUPPORT_STATIC_ALLOCATION
+        DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore, &s_debugConsoleReadWaitSemaphoreStatic);
+#else
+        DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+#endif
+
+        {
+            serialManagerStatus =
+                SerialManager_OpenWriteHandle(s_debugConsoleState.serialHandle,
+                                              ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+            assert(kStatus_SerialManager_Success == serialManagerStatus);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+            (void)SerialManager_InstallTxCallback(
+                ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+                DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);
+            serialManagerStatus = SerialManager_OpenWriteHandle(
+                s_debugConsoleState.serialHandle,
+                ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0]));
+            assert(kStatus_SerialManager_Success == serialManagerStatus);
+            (void)SerialManager_InstallTxCallback(
+                ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0]),
+                DbgConsole_SerialManagerTx2Callback, &s_debugConsoleState);
+#endif
+        }
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+        {
+            serialManagerStatus =
+                SerialManager_OpenReadHandle(s_debugConsoleState.serialHandle,
+                                             ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+            assert(kStatus_SerialManager_Success == serialManagerStatus);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+            (void)SerialManager_InstallRxCallback(
+                ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),
+                DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);
+#endif
+        }
+#endif
+
+        g_serialHandle = s_debugConsoleState.serialHandle;
+    }
+    return (status_t)serialManagerStatus;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_EnterLowpower(void)
+{
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Error;
+    if (s_debugConsoleState.serialHandle != NULL)
+    {
+        serialManagerStatus = SerialManager_EnterLowpower(s_debugConsoleState.serialHandle);
+    }
+    return (status_t)serialManagerStatus;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_ExitLowpower(void)
+{
+    serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Error;
+
+    if (s_debugConsoleState.serialHandle != NULL)
+    {
+        serialManagerStatus = SerialManager_ExitLowpower(s_debugConsoleState.serialHandle);
+    }
+    return (status_t)serialManagerStatus;
+}
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+    {
+        if (s_debugConsoleState.serialHandle != NULL)
+        {
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+            (void)SerialManager_CloseWriteHandle(
+                ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0]));
+#endif
+            (void)SerialManager_CloseWriteHandle(
+                ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+        }
+    }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+    {
+        if (s_debugConsoleState.serialHandle != NULL)
+        {
+            (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+        }
+    }
+#endif
+    if (NULL != s_debugConsoleState.serialHandle)
+    {
+        if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle))
+        {
+            s_debugConsoleState.serialHandle = NULL;
+            g_serialHandle                   = NULL;
+        }
+    }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+    DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+
+    return (status_t)kStatus_Success;
+}
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))) ||                 \
+     ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+      (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+
+    if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+    {
+        return (status_t)kStatus_Fail;
+    }
+
+#else
+
+    while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+    {
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+        if (0U == IS_RUNNING_IN_ISR())
+        {
+            if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState())
+            {
+                vTaskDelay(1);
+            }
+        }
+        else
+        {
+            return (status_t)kStatus_Fail;
+        }
+#endif
+    }
+
+#endif
+
+#endif
+    return (status_t)kStatus_Success;
+}
+#endif
+
+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *fmt_s, ...)
+{
+    va_list ap;
+    int result = 0;
+
+    va_start(ap, fmt_s);
+    result = DbgConsole_Vprintf(fmt_s, ap);
+    va_end(ap);
+
+    return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg)
+{
+    int logLength = 0, result = 0;
+    char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+    if (NULL != g_serialHandle)
+    {
+        /* format print log first */
+        logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback);
+        /* print log */
+        result = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);
+    }
+    return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+    /* print char */
+    return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *fmt_s, ...)
+{
+    va_list ap;
+    int formatResult;
+    char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'};
+
+    /* scanf log */
+    (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
+    /* get va_list */
+    va_start(ap, fmt_s);
+    /* format scanf log */
+    formatResult = StrFormatScanf(scanfBuf, fmt_s, ap);
+
+    va_end(ap);
+
+    return formatResult;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_BlockingPrintf(const char *fmt_s, ...)
+{
+    va_list ap;
+    int result = 0;
+
+    va_start(ap, fmt_s);
+    result = DbgConsole_BlockingVprintf(fmt_s, ap);
+    va_end(ap);
+
+    return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg)
+{
+    status_t dbgConsoleStatus;
+    int logLength = 0, result = 0;
+    char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+    if (NULL == g_serialHandle)
+    {
+        return 0;
+    }
+
+    /* format print log first */
+    logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    (void)SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+#endif
+    /* print log */
+    dbgConsoleStatus =
+        (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+                                              (uint8_t *)printBuf, (size_t)logLength);
+    result = (((status_t)kStatus_Success == dbgConsoleStatus) ? (int)logLength : -1);
+
+    return result;
+}
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+status_t DbgConsole_TryGetchar(char *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+    uint32_t length           = 0;
+    status_t dbgConsoleStatus = (status_t)kStatus_Fail;
+
+    assert(ch);
+
+    if (NULL == g_serialHandle)
+    {
+        return kStatus_Fail;
+    }
+
+    /* take mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+#endif
+
+    if (kStatus_SerialManager_Success ==
+        SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,
+                              &length))
+    {
+        if (length != 0U)
+        {
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+            (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL);
+#endif
+            dbgConsoleStatus = (status_t)kStatus_Success;
+        }
+    }
+    /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+    return dbgConsoleStatus;
+#else
+    return (status_t)kStatus_Fail;
+#endif
+}
+#endif
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+    int ret    = -1;
+    uint8_t ch = 0U;
+
+    /* Get char */
+    if (DbgConsole_ReadCharacter(&ch) > 0)
+    {
+        ret = (int)ch;
+    }
+
+    return ret;
+}
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#if defined(SDK_DEBUGCONSOLE_UART)
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size);
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+    size_t ret;
+    if (NULL == buffer)
+    {
+        /*
+         * This means that we should flush internal buffers.  Since we don't we just return.
+         * (Remember, "handle" == -1 means that all handles should be flushed.)
+         */
+        ret = 0U;
+    }
+    else if ((handle != 1) && (handle != 2))
+    {
+        /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure.
+         */
+        ret = (size_t)-1;
+    }
+    else
+    {
+        /* Send data. */
+        uint8_t buff[512];
+        (void)memcpy(buff, buffer, size);
+        (void)DbgConsole_SendDataReliable((uint8_t *)buff, size);
+
+        ret = size;
+    }
+    return ret;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size);
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+    uint8_t ch     = 0U;
+    int actualSize = 0;
+
+    /* This function only reads from "standard in", for all other file  handles it returns failure. */
+    if (0 != handle)
+    {
+        actualSize = -1;
+    }
+    else
+    {
+        /* Receive data.*/
+        for (; size > 0U; size--)
+        {
+            (void)DbgConsole_ReadCharacter(&ch);
+            if (0U == ch)
+            {
+                break;
+            }
+
+            *buffer++ = ch;
+            actualSize++;
+        }
+    }
+    return (size_t)actualSize;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* support LPC Xpresso with RedLib */
+#elif (defined(__REDLIB__))
+
+#if (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+    if (NULL == buffer)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+    return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+    char tmp;
+
+    /* Receive data. */
+    DbgConsole_ReadCharacter((uint8_t *)&tmp);
+
+    return tmp;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#if defined(SDK_DEBUGCONSOLE_UART)
+#if defined(__CC_ARM)
+struct __FILE
+{
+    int handle;
+    /*
+     * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+     * no file handling is required.
+     */
+};
+#endif
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+    /* Send data. */
+    return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1);
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+    char ch;
+
+    /* Receive data. */
+    DbgConsole_ReadCharacter((uint8_t *)&ch);
+
+    return ch;
+}
+
+/*
+ * Terminate the program, passing a return code back to the user.
+ * This function may not return.
+ */
+void _sys_exit(int returncode)
+{
+    while (1)
+    {
+    }
+}
+
+/*
+ * Writes a character to the output channel. This function is used
+ * for last-resort error message output.
+ */
+void _ttywrch(int ch)
+{
+    char ench = ch;
+    DbgConsole_SendDataReliable((uint8_t *)(&ench), 1);
+}
+
+char *_sys_command_string(char *cmd, int len)
+{
+    return (cmd);
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif (defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \
+     (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART))))
+int __attribute__((weak)) _write(int handle, char *buffer, int size);
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+    if (NULL == buffer)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size);
+
+    return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size);
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+    uint8_t ch     = 0U;
+    int actualSize = 0;
+
+    /* This function only reads from "standard in", for all other file handles it returns failure. */
+    if (handle != 0)
+    {
+        return -1;
+    }
+
+    /* Receive data. */
+    for (; size > 0; size--)
+    {
+        if (DbgConsole_ReadCharacter(&ch) < 0)
+        {
+            break;
+        }
+
+        *buffer++ = (char)ch;
+        actualSize++;
+
+        if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r'))
+        {
+            break;
+        }
+    }
+
+    return (actualSize > 0) ? actualSize : -1;
+}
+#endif
+
+#endif /* __ICCARM__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console.h
new file mode 100644
index 0000000000..596179e5d3
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console.h
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ *   - [flags] :'-', '+', '#', ' ', '0'
+ *   - [width]:  number (0,1...)
+ *   - [.precision]: number (0,1...)
+ *   - [length]: do not support
+ *   - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ *   - [*]: is supported.
+ *   - [width]: number (0,1...)
+ *   - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ *   - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+#include "fsl_component_serial_manager.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+extern serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK       1U /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE               2U /*!< Disable debugconsole function. */
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
+ * to be redefined in project setting.
+ */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#else
+#include <stdarg.h>
+#endif
+
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
+ *
+ *  if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
+ *  if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
+ *  if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
+ */
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+static inline int DbgConsole_Disabled(void)
+{
+    return -1;
+}
+#define PRINTF(...)  DbgConsole_Disabled()
+#define SCANF(...)   DbgConsole_Disabled()
+#define PUTCHAR(...) DbgConsole_Disabled()
+#define GETCHAR()    DbgConsole_Disabled()
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF  DbgConsole_Printf
+#define SCANF   DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
+                                                              */
+#define PRINTF  printf
+#define SCANF   scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/*!
+ * @brief Initializes the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param instance      The instance of the module.If the device is kSerialPort_Uart,
+ *                      the instance is UART peripheral instance. The UART hardware peripheral
+ *                      type is determined by UART adapter. For example, if the instance is 1,
+ *                      if the lpuart_adapter.c is added to the current project, the UART periheral
+ *                      is LPUART1.
+ *                      If the uart_adapter.c is added to the current project, the UART periheral
+ *                      is UART1.
+ * @param baudRate      The desired baud rate in bits per second.
+ * @param device        Low level device type for the debug console, can be one of the following.
+ *                      @arg kSerialPort_Uart,
+ *                      @arg kSerialPort_UsbCdc
+ * @param clkSrcFreq    Frequency of peripheral source clock.
+ *
+ * @return              Indicates whether initialization was successful or not.
+ * @retval kStatus_Success          Execution successfully
+ */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_EnterLowpower(void);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_ExitLowpower(void);
+
+#else
+/*!
+ * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Init(uint8_t instance,
+                                       uint32_t baudRate,
+                                       serial_port_type_t device,
+                                       uint32_t clkSrcFreq)
+{
+    (void)instance;
+    (void)baudRate;
+    (void)device;
+    (void)clkSrcFreq;
+    return (status_t)kStatus_Fail;
+}
+/*!
+ * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Deinit(void)
+{
+    return (status_t)kStatus_Fail;
+}
+
+/*!
+ * Use an error to replace the DbgConsole_EnterLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_EnterLowpower(void)
+{
+    return (status_t)kStatus_Fail;
+}
+
+/*!
+ * Use an error to replace the DbgConsole_ExitLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_ExitLowpower(void)
+{
+    return (status_t)kStatus_Fail;
+}
+
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param   fmt_s Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *fmt_s, ...);
+
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param   fmt_s Format control string.
+ * @param   formatStringArg Format arguments.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param   ch Character to be written.
+ * @return  Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @param   fmt_s Format control string.
+ * @return  Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *fmt_s, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+/*!
+ * @brief Writes formatted output to the standard output stream with the blocking mode.
+ *
+ * Call this function to write a formatted output to the standard output stream with the blocking mode.
+ * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
+ * or not.
+ * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
+ *
+ * @param   fmt_s Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_BlockingPrintf(const char *fmt_s, ...);
+
+/*!
+ * @brief Writes formatted output to the standard output stream with the blocking mode.
+ *
+ * Call this function to write a formatted output to the standard output stream with the blocking mode.
+ * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
+ * or not.
+ * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
+ *
+ * @param   fmt_s Format control string.
+ * @param   formatStringArg Format arguments.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg);
+
+/*!
+ * @brief Debug console flush.
+ *
+ * Call this function to wait the tx buffer empty.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief Debug console try to get char
+ * This function provides a API which will not block current task, if character is
+ * available return it, otherwise return fail.
+ * @param ch the address of char to receive
+ * @return Indicates get char was successful or not.
+ */
+status_t DbgConsole_TryGetchar(char *ch);
+#endif
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console_conf.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console_conf.h
new file mode 100644
index 0000000000..5568e02471
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_debug_console_conf.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2017 - 2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debug_console_config
+ * @ingroup debugconsole
+ * @{ 
+ */
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+ * otherwise blocking mode is the default transfer mode.
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding
+ * IO interrupt is enable, otherwise there is no output.
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.
+ * Below shows how to configure in your project if you want to use non-blocking mode.
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
+ * For ARMGCC, open CmakeLists.txt and add the following lines,
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
+ * Complier->Preprocessor".
+ *
+ */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+ * when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed , because the log will not be
+ * buffered if the buffer is full, and the print will return immediately with -1.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+/*!@brief Whether enable the reliable TX function
+ * If the macro is zero, the reliable TX function of the debug console is disabled.
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
+ */
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@brief Whether enable the RX function
+ * If the macro is zero, the receive function of the debug console is disabled.
+ */
+#ifndef DEBUG_CONSOLE_RX_ENABLE
+#define DEBUG_CONSOLE_RX_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+/*!@brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+ * length can not bigger than this value.
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+ * the buffer is too big and current task stack size not big enough.
+ */
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+ * length can not bigger than this value.
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+ */
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+ * User should not change these macro for synchronization mode, but add the
+ * corresponding synchronization mechanism per different software environment.
+ * Such as, if another RTOS is used,
+ * add:
+ *  \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+ * in this configuration file and implement the synchronization in fsl.log.c.
+ */
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+ * If not defined, default is enable, to avoid multitask log print mess.
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+ * If synchronization is disabled, log maybe messed on terminal.
+ */
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef SDK_OS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* SDK_OS_FREE_RTOS */
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+ * at your project setting.
+ */
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
+#ifndef BOARD_USE_VIRTUALCOM
+#define BOARD_USE_VIRTUALCOM 0U
+#endif
+/*******************************************************************/
+
+/*! @} */
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_memcpy.S b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_memcpy.S
new file mode 100644
index 0000000000..987d3de1a8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_memcpy.S
@@ -0,0 +1,279 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+    .syntax unified
+
+    .text
+    .thumb
+
+    .align 2
+
+#ifndef MSDK_MISC_OVERRIDE_MEMCPY
+#define MSDK_MISC_OVERRIDE_MEMCPY 1
+#endif
+
+/*
+   This mempcy function is used to replace the GCC newlib function for these purposes:
+   1. The newlib nano memcpy function use byte by byte copy, it is slow.
+   2. The newlib memcpy function for CM4, CM7, CM33 does't check address alignment,
+      so it may run to fault when the address is unaligned, and the memory region
+      is device memory, which does not support unaligned access.
+
+   This function is manually optimized base on assembly result of the c function.
+   The workflow is:
+   1. Return directly if length is 0.
+   2. If the source address is not 4-byte aligned, copy the unaligned part first byte by byte.
+   3. If the destination address is 4-byte aligned, then copy the 16-byte aligned part first,
+      copy 16-byte each loop, and then copy 8-byte, 4-byte, 2-byte and 1-byte.
+   4. If the destination address is not 4-byte aligned, load source data into register word
+      by word first, then store to memory based on alignement requirement. For the left part,
+      copy them byte by byte.
+
+   The source code of the c function is:
+
+   #define __CPY_WORD(dst, src) \
+       *(uint32_t *)(dst) = *(uint32_t *)(src); \
+       (dst) = ((uint32_t *)dst) + 1; \
+       (src) = ((uint32_t *)src) + 1
+
+   #define __CPY_HWORD(dst, src) \
+       *(uint16_t *)(dst) = *(uint16_t *)(src); \
+       (dst) = ((uint16_t *)dst) + 1; \
+       (src) = ((uint16_t *)src) + 1
+
+   #define __CPY_BYTE(dst, src) \
+       *(uint8_t *)(dst) = *(uint8_t *)(src); \
+       (dst) = ((uint8_t *)dst) + 1; \
+       (src) = ((uint8_t *)src) + 1
+
+   void * memcpy(void *restrict  dst, const void * restrict src, size_t n)
+   {
+       void *ret = dst;
+       uint32_t tmp;
+
+       if (0 == n) return ret;
+
+       while (((uintptr_t)src & 0x03UL) != 0UL)
+       {
+           __CPY_BYTE(dst, src);
+           n--;
+
+           if (0 == n) return ret;
+       }
+
+       if (((uintptr_t)dst & 0x03UL) == 0UL)
+       {
+           while (n >= 16UL)
+           {
+               __CPY_WORD(dst, src);
+               __CPY_WORD(dst, src);
+               __CPY_WORD(dst, src);
+               __CPY_WORD(dst, src);
+               n-= 16UL;
+           }
+
+           if ((n & 0x08UL) != 0UL)
+           {
+               __CPY_WORD(dst, src);
+               __CPY_WORD(dst, src);
+           }
+
+           if ((n & 0x04UL) != 0UL)
+           {
+               __CPY_WORD(dst, src);
+           }
+
+           if ((n & 0x02UL) != 0UL)
+           {
+               __CPY_HWORD(dst, src);
+           }
+
+           if ((n & 0x01UL) != 0UL)
+           {
+               __CPY_BYTE(dst, src);
+           }
+       }
+       else
+       {
+           if (((uintptr_t)dst & 1UL) == 0UL)
+           {
+               while (n >= 4)
+               {
+                   tmp = *(uint32_t *)src;
+                   src = ((uint32_t *)src) + 1;
+
+                   *(volatile uint16_t *)dst = (uint16_t)tmp;
+                   dst = ((uint16_t *)dst) + 1;
+                   *(volatile uint16_t *)dst = (uint16_t)(tmp>>16U);
+                   dst = ((uint16_t *)dst) + 1;
+
+                   n-=4;
+               }
+           }
+           else
+           {
+               while (n >= 4)
+               {
+                   tmp = *(uint32_t *)src;
+                   src = ((uint32_t *)src) + 1;
+
+                   *(volatile uint8_t *)dst  = (uint8_t)tmp;
+                   dst = ((uint8_t *)dst) + 1;
+                   *(volatile uint16_t *)dst = (uint16_t)(tmp>>8U);
+                   dst = ((uint16_t *)dst) + 1;
+                   *(volatile uint8_t *)dst = (uint8_t)(tmp>>24U);
+                   dst = ((uint8_t *)dst) + 1;
+                   n-=4;
+               }
+           }
+
+           while (n > 0)
+           {
+               __CPY_BYTE(dst, src);
+               n--;
+           }
+       }
+
+       return ret;
+   }
+
+   The test function is:
+
+   void test_memcpy(uint8_t *dst, const uint8_t * src, size_t n)
+   {
+       uint8_t * ds;
+       uint8_t * de;
+       const uint8_t *ss;
+       const uint8_t *se;
+       uint8_t * ret;
+
+       for (ss = src; ss < src+n; ss++)
+       {
+           for (se = ss; se < src + n; se ++)
+           {
+               size_t nn = (uintptr_t)se - (uintptr_t)ss;
+
+               for (ds = dst; ds + nn < dst+n; ds++)
+               {
+                   de = ds + nn;
+
+                   memset(dst, 0, n);
+
+                   ret = memcpy(ds, ss, nn);
+
+                   assert(ret == ds);
+
+                   for (const uint8_t *data = dst; data < ds; data++)
+                   {
+                       assert(0 == *data);
+                   }
+
+                   for (const uint8_t *data = de; data < dst+n; data++)
+                   {
+                       assert(0 == *data);
+                   }
+
+                   assert(memcmp(ds, ss, nn) == 0);
+               }
+           }
+       }
+   }
+
+   test_memcpy((uint8_t *)0x20240000, (const uint8_t *)0x202C0000, 48);
+
+ */
+
+#if MSDK_MISC_OVERRIDE_MEMCPY
+
+    .thumb_func
+    .align 2
+    .global  memcpy
+    .type    memcpy, %function
+
+memcpy:
+    push    {r0, r4, r5, r6, r7, lr}
+    cmp     r2, #0
+    beq     ret                    /* If copy size is 0, return. */
+
+src_word_unaligned:
+    ands    r3, r1, #3             /* Make src 4-byte align. */
+    beq.n   src_word_aligned       /* src is 4-byte aligned, jump. */
+    ldrb    r4, [r1], #1
+    subs    r2, r2, #1             /* n-- */
+    strb    r4, [r0], #1
+    beq.n   ret                    /* n=0, return. */
+    b.n     src_word_unaligned
+
+src_word_aligned:
+    ands    r3, r0, #3             /* Check dest 4-byte align. */
+    bne.n   dst_word_unaligned
+
+dst_word_aligned:
+    cmp     r2, #16
+    blt.n   size_ge_8
+size_ge_16:                         /* size greater or equal than 16, use ldm and stm. */
+    subs    r2, r2, #16             /* n -= 16 */
+    ldmia   r1!, { r4, r5, r6, r7 }
+    cmp     r2, #16
+    stmia   r0!, { r4, r5, r6, r7 }
+    bcs.n   size_ge_16
+size_ge_8:                         /* size greater or equal than 8 */
+    lsls    r3, r2, #28
+    itt     mi
+    ldmiami r1!, { r4, r5 }
+    stmiami r0!, { r4, r5 }
+size_ge_4:                         /* size greater or equal than 4 */
+    lsls    r3, r2, #29
+    itt     mi
+    ldrmi   r4, [r1], #4
+    strmi   r4, [r0], #4
+size_ge_2:                         /* size greater or equal than 2 */
+    lsls    r3, r2, #30
+    itt     mi
+    ldrhmi  r4, [r1], #2
+    strhmi  r4, [r0], #2
+size_ge_1:                         /* size greater or equal than 1 */
+    lsls    r3, r2, #31
+    itt     mi
+    ldrbmi  r4, [r1]
+    strbmi  r4, [r0]
+    b.n     ret
+
+dst_word_unaligned:
+    lsls    r3, r0, #31
+    bmi.n   dst_half_word_unaligned
+dst_half_word_aligned:
+    cmp     r2, #4
+    bcc.n   size_lt_4
+    ldr     r4, [r1], #4
+    subs    r2, r2, #4
+    strh    r4, [r0], #2
+    lsrs    r5, r4, #16
+    strh    r5, [r0], #2
+    b  dst_half_word_aligned
+dst_half_word_unaligned:
+    cmp     r2, #4
+    bcc.n   size_lt_4
+    ldr     r4, [r1], #4
+    subs    r2, r2, #4
+    strb    r4, [r0], #1
+    lsrs    r5, r4, #8
+    strh    r5, [r0], #2
+    lsrs    r6, r4, #24
+    strb    r6, [r0], #1
+    b  dst_half_word_unaligned
+size_lt_4:                             /* size less than 4. */
+    cmp     r2, #0
+    ittt    ne
+    ldrbne  r4, [r1], #1
+    strbne  r4, [r0], #1
+    subne   r2, r2, #1
+    bne     size_lt_4
+ret:
+    pop    {r0, r4, r5, r6, r7, pc}
+
+#endif /* MSDK_MISC_OVERRIDE_MEMCPY */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_str.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_str.c
new file mode 100644
index 0000000000..3ca1e4194a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_str.c
@@ -0,0 +1,1707 @@
+/*
+ * Copyright 2017, 2020, 2022-2023 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <math.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <errno.h> /* MISRA C-2012 Rule 22.9 */
+#include "fsl_str.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+#ifndef MAX_FIELD_WIDTH
+#define MAX_FIELD_WIDTH 99U
+#endif
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned long long int
+#define STR_FORMAT_PRINTF_IVAL_TYPE long long int
+#else
+#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned int
+#define STR_FORMAT_PRINTF_IVAL_TYPE int
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in]   s The address of the string pointer to update.
+ * @return      String without white spaces.
+ */
+static uint32_t ScanIgnoreWhiteSpace(const char **s);
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr    Converted string of the number.
+ * @param[in] nump      Pointer to the number.
+ * @param[in] neg       Polarity of the number.
+ * @param[in] radix     The radix to be converted to.
+ * @param[in] use_caps  Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps);
+
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U))
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr            Converted string of the number.
+ * @param[in] nump              Pointer to the number.
+ * @param[in] radix             The radix to be converted to.
+ * @param[in] precision_width   Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*************Code for process formatted data*******************************/
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+static uint8_t PrintGetSignChar(long long int ival, uint32_t flags_used, char *schar)
+{
+    uint8_t len = 1U;
+    if (ival < 0)
+    {
+        *schar = '-';
+    }
+    else
+    {
+        if (0U != (flags_used & (uint32_t)kPRINTF_Plus))
+        {
+            *schar = '+';
+        }
+        else if (0U != (flags_used & (uint32_t)kPRINTF_Space))
+        {
+            *schar = ' ';
+        }
+        else
+        {
+            *schar = '\0';
+            len    = 0U;
+        }
+    }
+    return len;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+static uint32_t PrintGetWidth(const char **p, va_list *ap)
+{
+    uint32_t field_width = 0;
+    uint8_t done         = 0U;
+    char c;
+
+    while (0U == done)
+    {
+        c = *(++(*p));
+        if ((c >= '0') && (c <= '9'))
+        {
+            (field_width) = ((field_width)*10U) + ((uint32_t)c - (uint32_t)'0');
+        }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+        else if (c == '*')
+        {
+            (field_width) = (uint32_t)va_arg(*ap, uint32_t);
+        }
+#endif /* PRINTF_ADVANCED_ENABLE */
+        else
+        {
+            /* We've gone one char too far. */
+            --(*p);
+            done = 1U;
+        }
+    }
+    return field_width;
+}
+
+static uint32_t PrintGetPrecision(const char **s, va_list *ap, bool *valid_precision_width)
+{
+    const char *p            = *s;
+    uint32_t precision_width = 6U;
+    uint8_t done             = 0U;
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (NULL != valid_precision_width)
+    {
+        *valid_precision_width = false;
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+    if (*++p == '.')
+    {
+        /* Must get precision field width, if present. */
+        precision_width = 0U;
+        done            = 0U;
+        while (0U == done)
+        {
+            char c = *++p;
+            if ((c >= '0') && (c <= '9'))
+            {
+                precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0');
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                if (NULL != valid_precision_width)
+                {
+                    *valid_precision_width = true;
+                }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+            else if (c == '*')
+            {
+                precision_width = (uint32_t)va_arg(*ap, uint32_t);
+                if (NULL != valid_precision_width)
+                {
+                    *valid_precision_width = true;
+                }
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                /* We've gone one char too far. */
+                --p;
+                done = 1U;
+            }
+        }
+    }
+    else
+    {
+        /* We've gone one char too far. */
+        --p;
+    }
+    *s = p;
+    return precision_width;
+}
+
+static uint32_t PrintIsobpu(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t PrintIsdi(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'd') || (c == 'i'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static void PrintOutputdifFobpu(uint32_t flags_used,
+                                uint32_t field_width,
+                                uint32_t vlen,
+                                char schar,
+                                char *vstrp,
+                                printfCb cb,
+                                char *buf,
+                                int32_t *count)
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    /* Do the ZERO pad. */
+    if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+    {
+        if ('\0' != schar)
+        {
+            cb(buf, count, schar, 1);
+            schar = '\0';
+        }
+        cb(buf, count, '0', (int)field_width - (int)vlen);
+        vlen = field_width;
+    }
+    else
+    {
+        if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+        {
+            cb(buf, count, ' ', (int)field_width - (int)vlen);
+            if ('\0' != schar)
+            {
+                cb(buf, count, schar, 1);
+                schar = '\0';
+            }
+        }
+    }
+    /* The string was built in reverse order, now display in correct order. */
+    if ('\0' != schar)
+    {
+        cb(buf, count, schar, 1);
+    }
+#else
+    cb(buf, count, ' ', (int)field_width - (int)vlen);
+#endif /* PRINTF_ADVANCED_ENABLE */
+    while ('\0' != (*vstrp))
+    {
+        cb(buf, count, *vstrp--, 1);
+    }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+    {
+        cb(buf, count, ' ', (int)field_width - (int)vlen);
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+}
+
+static void PrintOutputxX(uint32_t flags_used,
+                          uint32_t field_width,
+                          uint32_t vlen,
+                          bool use_caps,
+                          char *vstrp,
+                          printfCb cb,
+                          char *buf,
+                          int32_t *count)
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    uint8_t dschar = 0;
+    if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+    {
+        if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+        {
+            cb(buf, count, '0', 1);
+            cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+            dschar = 1U;
+        }
+        cb(buf, count, '0', (int)field_width - (int)vlen);
+        vlen = field_width;
+    }
+    else
+    {
+        if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+        {
+            if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+            {
+                vlen += 2U;
+            }
+            cb(buf, count, ' ', (int)field_width - (int)vlen);
+            if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+            {
+                cb(buf, count, '0', 1);
+                cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+                dschar = 1U;
+            }
+        }
+    }
+
+    if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (0U == dschar))
+    {
+        cb(buf, count, '0', 1);
+        cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+        vlen += 2U;
+    }
+#else
+    cb(buf, count, ' ', (int)field_width - (int)vlen);
+#endif /* PRINTF_ADVANCED_ENABLE */
+    while ('\0' != (*vstrp))
+    {
+        cb(buf, count, *vstrp--, 1);
+    }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+    {
+        cb(buf, count, ' ', (int)field_width - (int)vlen);
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+}
+
+static uint32_t PrintIsfF(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'f') || (c == 'F'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t PrintIsxX(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'x') || (c == 'X'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+static uint32_t PrintCheckFlags(const char **s)
+{
+    const char *p = *s;
+    /* First check for specification modifier flags. */
+    uint32_t flags_used = 0U;
+    bool done           = false;
+    while (false == done)
+    {
+        switch (*++p)
+        {
+            case '-':
+                flags_used |= (uint32_t)kPRINTF_Minus;
+                break;
+            case '+':
+                flags_used |= (uint32_t)kPRINTF_Plus;
+                break;
+            case ' ':
+                flags_used |= (uint32_t)kPRINTF_Space;
+                break;
+            case '0':
+                flags_used |= (uint32_t)kPRINTF_Zero;
+                break;
+            case '#':
+                flags_used |= (uint32_t)kPRINTF_Pound;
+                break;
+            default:
+                /* We've gone one char too far. */
+                --p;
+                done = true;
+                break;
+        }
+    }
+    *s = p;
+    return flags_used;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+/*
+ * Check for the length modifier.
+ */
+static uint32_t PrintGetLengthFlag(const char **s)
+{
+    const char *p = *s;
+    /* First check for specification modifier flags. */
+    uint32_t flags_used = 0U;
+
+    switch (/* c = */ *++p)
+    {
+        case 'h':
+            if (*++p != 'h')
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthShortInt;
+                --p;
+            }
+            else
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthChar;
+            }
+            break;
+        case 'l':
+            if (*++p != 'l')
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongInt;
+                --p;
+            }
+            else
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;
+            }
+            break;
+        case 'z':
+            if (sizeof(size_t) == sizeof(uint32_t))
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongInt;
+            }
+            else if (sizeof(size_t) == (2U * sizeof(uint32_t)))
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;
+            }
+            else if (sizeof(size_t) == sizeof(uint16_t))
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthShortInt;
+            }
+            else
+            {
+                /* MISRA C-2012 Rule 15.7 */
+            }
+            break;
+        default:
+            /* we've gone one char too far */
+            --p;
+            break;
+    }
+    *s = p;
+    return flags_used;
+}
+#else
+static void PrintFilterLengthFlag(const char **s)
+{
+    const char *p = *s;
+    char strCh;
+
+    do
+    {
+        strCh = *++p;
+    } while ((strCh == 'h') || (strCh == 'l'));
+
+    *s = --p;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+static uint8_t PrintGetRadixFromobpu(const char c)
+{
+    uint8_t radix;
+
+    if (c == 'o')
+    {
+        radix = 8U;
+    }
+    else if (c == 'b')
+    {
+        radix = 2U;
+    }
+    else if (c == 'p')
+    {
+        radix = 16U;
+    }
+    else
+    {
+        radix = 10U;
+    }
+    return radix;
+}
+
+static uint32_t ScanIsWhiteSpace(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t ScanIgnoreWhiteSpace(const char **s)
+{
+    uint32_t count = 0U;
+    char c;
+
+    c = **s;
+    while (1U == ScanIsWhiteSpace(c))
+    {
+        count++;
+        (*s)++;
+        c = **s;
+    }
+    return count;
+}
+
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps)
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    long long int a;
+    long long int b;
+    long long int c;
+
+    unsigned long long int ua;
+    unsigned long long int ub;
+    unsigned long long int uc;
+    unsigned long long int uc_param;
+#else
+    int a;
+    int b;
+    int c;
+
+    unsigned int ua;
+    unsigned int ub;
+    unsigned int uc;
+    unsigned int uc_param;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+    int32_t nlen;
+    char *nstrp;
+
+    nlen     = 0;
+    nstrp    = numstr;
+    *nstrp++ = '\0';
+
+#if !(defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0u))
+    neg = 0U;
+#endif
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    a        = 0;
+    b        = 0;
+    c        = 0;
+    ua       = 0ULL;
+    ub       = 0ULL;
+    uc       = 0ULL;
+    uc_param = 0ULL;
+#else
+    a        = 0;
+    b        = 0;
+    c        = 0;
+    ua       = 0U;
+    ub       = 0U;
+    uc       = 0U;
+    uc_param = 0U;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+    (void)a;
+    (void)b;
+    (void)c;
+    (void)ua;
+    (void)ub;
+    (void)uc;
+    (void)uc_param;
+    (void)neg;
+    /*
+     * Fix MISRA issue: CID 15972928 (#15 of 15): MISRA C-2012 Control Flow Expressions (MISRA C-2012 Rule 14.3)
+     * misra_c_2012_rule_14_3_violation: Execution cannot reach this statement: a = *((int *)nump);
+     */
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (0U != neg)
+    {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+        a = *(long long int *)nump;
+#else
+        a = *(int *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (a == 0)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (a != 0)
+        {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+            b = (long long int)a / (long long int)radix;
+            c = (long long int)a - ((long long int)b * (long long int)radix);
+            if (c < 0)
+            {
+                uc       = (unsigned long long int)c;
+                uc_param = ~uc;
+                c        = (long long int)uc_param + 1 + (long long int)'0';
+            }
+#else
+            b = (int)a / (int)radix;
+            c = (int)a - ((int)b * (int)radix);
+            if (c < 0)
+            {
+                uc       = (unsigned int)c;
+                uc_param = ~uc;
+                c        = (int)uc_param + 1 + (int)'0';
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                c = c + (int)'0';
+            }
+            a        = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+    {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+        ua = *(unsigned long long int *)nump;
+#else
+        ua = *(unsigned int *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (ua == 0U)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (ua != 0U)
+        {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+            ub = (unsigned long long int)ua / (unsigned long long int)radix;
+            uc = (unsigned long long int)ua - ((unsigned long long int)ub * (unsigned long long int)radix);
+#else
+            ub = ua / (unsigned int)radix;
+            uc = ua - (ub * (unsigned int)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+            if (uc < 10U)
+            {
+                uc = uc + (unsigned int)'0';
+            }
+            else
+            {
+                uc = uc - 10U + (unsigned int)(use_caps ? 'A' : 'a');
+            }
+            ua       = ub;
+            *nstrp++ = (char)uc;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U))
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+    int32_t a;
+    int32_t b;
+    int32_t c;
+    int32_t i;
+    uint32_t uc;
+    double fa;
+    double dc;
+    double fb;
+    double r;
+    double fractpart;
+    double intpart;
+
+    int32_t nlen;
+    char *nstrp;
+    nlen     = 0;
+    nstrp    = numstr;
+    *nstrp++ = '\0';
+    r        = *(double *)nump;
+    if (0.0 == r)
+    {
+        *nstrp = '0';
+        ++nlen;
+        return nlen;
+    }
+    fractpart = modf((double)r, (double *)&intpart);
+    /* Process fractional part. */
+    for (i = 0; i < (int32_t)precision_width; i++)
+    {
+        fractpart *= (double)radix;
+    }
+    if (r >= (double)0.0)
+    {
+        fa = fractpart + (double)0.5;
+        if (fa >= pow((double)10, (double)precision_width))
+        {
+            intpart++;
+        }
+    }
+    else
+    {
+        fa = fractpart - (double)0.5;
+        if (fa <= -pow((double)10, (double)precision_width))
+        {
+            intpart--;
+        }
+    }
+    for (i = 0; i < (int32_t)precision_width; i++)
+    {
+        fb = fa / (double)radix;
+        dc = (fa - (double)(long long int)fb * (double)radix);
+        c  = (int32_t)dc;
+        if (c < 0)
+        {
+            uc = (uint32_t)c;
+            uc = ~uc;
+            c  = (int32_t)uc;
+            c += (int32_t)1;
+            c += (int32_t)'0';
+        }
+        else
+        {
+            c = c + '0';
+        }
+        fa       = fb;
+        *nstrp++ = (char)c;
+        ++nlen;
+    }
+    *nstrp++ = (char)'.';
+    ++nlen;
+    a = (int32_t)intpart;
+    if (a == 0)
+    {
+        *nstrp++ = '0';
+        ++nlen;
+    }
+    else
+    {
+        while (a != 0)
+        {
+            b = (int32_t)a / (int32_t)radix;
+            c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+            if (c < 0)
+            {
+                uc = (uint32_t)c;
+                uc = ~uc;
+                c  = (int32_t)uc;
+                c += (int32_t)1;
+                c += (int32_t)'0';
+            }
+            else
+            {
+                c = c + '0';
+            }
+            a        = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+static void StrFormatExaminedi(uint32_t *flags_used, long long int *ival, va_list *ap)
+#else
+static void StrFormatExaminedi(int *ival, va_list *ap)
+#endif
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (0U != (*flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+    {
+        *ival = (long long int)va_arg(*ap, long long int);
+    }
+    else if (0U != (*flags_used & (uint32_t)kPRINTF_LengthLongInt))
+    {
+        *ival = (long long int)va_arg(*ap, long int);
+    }
+    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+    {
+        *ival = (STR_FORMAT_PRINTF_IVAL_TYPE)va_arg(*ap, int);
+    }
+}
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+static void StrFormatExaminexX(uint32_t *flags_used, unsigned long long int *uval, va_list *ap)
+#else
+static void StrFormatExaminexX(unsigned int *uval, va_list *ap)
+#endif
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongLongInt))
+    {
+        *uval = (unsigned long long int)va_arg(*ap, unsigned long long int);
+    }
+    else if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongInt))
+    {
+        *uval = (unsigned long long int)va_arg(*ap, unsigned long int);
+    }
+    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+    {
+        *uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(*ap, unsigned int);
+    }
+}
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+static void StrFormatExamineobpu(uint32_t *flags_used, unsigned long long int *uval, va_list *ap)
+#else
+static void StrFormatExamineobpu(unsigned int *uval, va_list *ap)
+#endif
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongLongInt))
+    {
+        *uval = (unsigned long long int)va_arg(*ap, unsigned long long int);
+    }
+    else if (0U != (*flags_used & (unsigned int)kPRINTF_LengthLongInt))
+    {
+        *uval = (unsigned long long int)va_arg(*ap, unsigned long int);
+    }
+    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+    {
+        *uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(*ap, unsigned int);
+    }
+}
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+static int32_t ConvertPrecisionWidthToLength(bool valid_precision_width, uint32_t precision_width, char *sval)
+#else
+static int32_t ConvertPrecisionWidthToLength(char *sval)
+#endif
+{
+    int32_t vlen = 0;
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    if (valid_precision_width)
+    {
+        vlen = (int)precision_width;
+    }
+    else
+    {
+        vlen = (int)strlen(sval);
+    }
+#else
+    vlen = (int32_t)strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+    return vlen;
+}
+
+/*!
+ * brief This function outputs its parameters according to a formatted string.
+ *
+ * note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * param[in] fmt   Format string for printf.
+ * param[in] ap    Arguments to printf.
+ * param[in] buf  pointer to the buffer
+ * param cb print callback function pointer
+ *
+ * return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
+{
+    /* va_list ap; */
+    const char *p;
+    char c;
+
+    char vstr[33];
+    char *vstrp  = NULL;
+    int32_t vlen = 0;
+
+    int32_t count = 0;
+
+    uint32_t field_width;
+    uint32_t precision_width;
+    char *sval;
+    int32_t cval;
+    bool use_caps;
+    unsigned int radix = 0;
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+    uint32_t flags_used;
+    char schar;
+    long long int ival;
+    unsigned long long int uval = 0;
+    bool valid_precision_width;
+#else
+    int ival;
+    unsigned int uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U))
+    double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+    /* Start parsing apart the format string and display appropriate formats and data. */
+    p = fmt;
+    while (true)
+    {
+        if ('\0' == *p)
+        {
+            break;
+        }
+        c = *p;
+        /*
+         * All formats begin with a '%' marker.  Special chars like
+         * '\n' or '\t' are normally converted to the appropriate
+         * character by the __compiler__.  Thus, no need for this
+         * routine to account for the '\' character.
+         */
+        if (c != '%')
+        {
+            cb(buf, &count, c, 1);
+            p++;
+            /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+            continue;
+        }
+
+        use_caps = true;
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+        /* First check for specification modifier flags. */
+        flags_used = PrintCheckFlags(&p);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+        /* Next check for minimum field width. */
+        field_width = PrintGetWidth(&p, &ap);
+
+        /* Next check for the width and precision field separator. */
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+        precision_width = PrintGetPrecision(&p, &ap, &valid_precision_width);
+#else
+        precision_width = PrintGetPrecision(&p, &ap, NULL);
+        (void)precision_width;
+#endif
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+        /* Check for the length modifier. */
+        flags_used |= PrintGetLengthFlag(&p);
+#else
+        /* Filter length modifier. */
+        PrintFilterLengthFlag(&p);
+#endif
+
+        /* Now we're ready to examine the format. */
+        c = *++p;
+        {
+            if (1U == PrintIsdi(c))
+            {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                StrFormatExaminedi(&flags_used, &ival, &ap);
+#else
+                StrFormatExaminedi(&ival, &ap);
+#endif
+
+                vlen  = ConvertRadixNumToString((char *)vstr, (void *)&ival, 1, 10, use_caps);
+                vstrp = &vstr[vlen];
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                vlen += (int)PrintGetSignChar(ival, flags_used, &schar);
+                PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0U, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+            }
+            else if (1U == PrintIsfF(c))
+            {
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U))
+                fval  = (double)va_arg(ap, double);
+                vlen  = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+                vstrp = &vstr[vlen];
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                vlen += (int32_t)PrintGetSignChar(((fval < 0.0) ? ((long long int)-1) : ((long long int)fval)),
+                                                  flags_used, &schar);
+                PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+
+#else
+                (void)va_arg(ap, double);
+#endif /* PRINTF_FLOAT_ENABLE */
+            }
+            else if (1U == PrintIsxX(c))
+            {
+                if (c == 'x')
+                {
+                    use_caps = false;
+                }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                StrFormatExaminexX(&flags_used, &uval, &ap);
+#else
+                StrFormatExaminexX(&uval, &ap);
+#endif
+
+                vlen  = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, 16, use_caps);
+                vstrp = &vstr[vlen];
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                PrintOutputxX(flags_used, field_width, (unsigned int)vlen, use_caps, vstrp, cb, buf, &count);
+#else
+                PrintOutputxX(0U, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count);
+#endif
+            }
+            else if (1U == PrintIsobpu(c))
+            {
+                if ('p' == c)
+                {
+                    /*
+                     * Fix MISRA issue: CID 17205581 (#15 of 15): MISRA C-2012 Pointer Type Conversions (MISRA C-2012
+                     * Rule 11.6) 1.misra_c_2012_rule_11_6_violation: The expression va_arg (ap, void *) of type void *
+                     * is cast to type uint32_t.
+                     *
+                     * Orignal code: uval = (STR_FORMAT_PRINTF_UVAL_TYPE)(uint32_t)va_arg(ap, void *);
+                     */
+                    void *pval;
+                    pval = (void *)va_arg(ap, void *);
+                    (void)memcpy((void *)&uval, (void *)&pval, sizeof(void *));
+                }
+                else
+                {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                    StrFormatExamineobpu(&flags_used, &uval, &ap);
+#else
+                    StrFormatExamineobpu(&uval, &ap);
+#endif
+                }
+
+                radix = PrintGetRadixFromobpu(c);
+
+                vlen  = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, radix, use_caps);
+                vstrp = &vstr[vlen];
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+            }
+            else if (c == 'c')
+            {
+                cval = (int32_t)va_arg(ap, int);
+                cb(buf, &count, cval, 1);
+            }
+            else if (c == 's')
+            {
+                sval = (char *)va_arg(ap, char *);
+                if (NULL != sval)
+                {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                    vlen = ConvertPrecisionWidthToLength(valid_precision_width, precision_width, sval);
+#else
+                    vlen = ConvertPrecisionWidthToLength(sval);
+#endif
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                    if (0U == (flags_used & (unsigned int)kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+                    {
+                        cb(buf, &count, ' ', (int)field_width - (int)vlen);
+                    }
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                    if (valid_precision_width)
+                    {
+                        while (('\0' != *sval) && (vlen > 0))
+                        {
+                            cb(buf, &count, *sval++, 1);
+                            vlen--;
+                        }
+                        /* In case that vlen sval is shorter than vlen */
+                        vlen = (int)precision_width - vlen;
+                    }
+                    else
+                    {
+#endif /* PRINTF_ADVANCED_ENABLE */
+                        while ('\0' != (*sval))
+                        {
+                            cb(buf, &count, *sval++, 1);
+                        }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+                    if (0U != (flags_used & (unsigned int)kPRINTF_Minus))
+                    {
+                        cb(buf, &count, ' ', (int)field_width - vlen);
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+            }
+            else
+            {
+                cb(buf, &count, c, 1);
+            }
+        }
+        p++;
+    }
+
+    return (int)count;
+}
+
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+static uint8_t StrFormatScanIsFloat(char *c)
+{
+    uint8_t ret = 0U;
+    if (('a' == (*c)) || ('A' == (*c)) || ('e' == (*c)) || ('E' == (*c)) || ('f' == (*c)) || ('F' == (*c)) ||
+        ('g' == (*c)) || ('G' == (*c)))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+#endif
+
+static uint8_t StrFormatScanIsFormatStarting(char *c)
+{
+    uint8_t ret = 1U;
+    if ((*c != '%'))
+    {
+        ret = 0U;
+    }
+    else if (*(c + 1) == '%')
+    {
+        ret = 0U;
+    }
+    else
+    {
+        /*MISRA rule 15.7*/
+    }
+
+    return ret;
+}
+
+static uint8_t StrFormatScanGetBase(uint8_t base, const char *s)
+{
+    if (base == 0U)
+    {
+        if (s[0] == '0')
+        {
+            if ((s[1] == 'x') || (s[1] == 'X'))
+            {
+                base = 16;
+            }
+            else
+            {
+                base = 8;
+            }
+        }
+        else
+        {
+            base = 10;
+        }
+    }
+    return base;
+}
+
+static uint8_t StrFormatScanCheckSymbol(const char *p, int8_t *neg)
+{
+    uint8_t len;
+    switch (*p)
+    {
+        case '-':
+            *neg = -1;
+            len  = 1;
+            break;
+        case '+':
+            *neg = 1;
+            len  = 1;
+            break;
+        default:
+            *neg = 1;
+            len  = 0;
+            break;
+    }
+    return len;
+}
+
+static uint8_t StrFormatScanFillInteger(uint32_t flag, va_list *args_ptr, int32_t val)
+{
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+    {
+        return 0u;
+    }
+
+    switch (flag & (uint32_t)kSCANF_LengthMask)
+    {
+        case (uint32_t)kSCANF_LengthChar:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed char *) = (signed char)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned char *) = (unsigned char)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthShortInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed short *) = (signed short)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned short *) = (unsigned short)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthLongInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed long int *) = (signed long int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned long int *) = (unsigned long int)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthLongLongInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed long long int *) = (signed long long int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned long long int *) = (unsigned long long int)val;
+            }
+            break;
+        default:
+            /* The default type is the type int. */
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed int *) = (signed int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned int *) = (unsigned int)val;
+            }
+            break;
+    }
+#else
+    /* The default type is the type int. */
+    if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+    {
+        *va_arg(*args_ptr, signed int *) = (signed int)val;
+    }
+    else
+    {
+        *va_arg(*args_ptr, unsigned int *) = (unsigned int)val;
+    }
+#endif /* SCANF_ADVANCED_ENABLE */
+
+    return 1U;
+}
+
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+static uint8_t StrFormatScanFillFloat(uint32_t flag, va_list *args_ptr, double fnum)
+{
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+    {
+        return 0U;
+    }
+    else
+#endif /* SCANF_ADVANCED_ENABLE */
+    {
+        if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble))
+        {
+            *va_arg(*args_ptr, double *) = fnum;
+        }
+        else
+        {
+            *va_arg(*args_ptr, float *) = (float)fnum;
+        }
+        return 1U;
+    }
+}
+#endif /* SCANF_FLOAT_ENABLE */
+
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+static uint8_t strFormatScanfHandleh(uint8_t exitPending, char **c, uint32_t *flag)
+{
+    if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+    {
+        /* Match failure. */
+        exitPending = 1U;
+    }
+    else
+    {
+        if ((*c)[1] == 'h')
+        {
+            (*flag) |= (uint32_t)kSCANF_LengthChar;
+            *c = *c + 1U;
+        }
+        else
+        {
+            (*flag) |= (uint32_t)kSCANF_LengthShortInt;
+        }
+    }
+
+    return exitPending;
+}
+
+static uint8_t strFormatScanfHandlel(uint8_t exitPending, char **c, uint32_t *flag)
+{
+    if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+    {
+        /* Match failure. */
+        exitPending = 1U;
+    }
+    else
+    {
+        if ((*c)[1] == 'l')
+        {
+            (*flag) |= (uint32_t)kSCANF_LengthLongLongInt;
+            *c = *c + 1U;
+        }
+        else
+        {
+            (*flag) |= (uint32_t)kSCANF_LengthLongInt;
+        }
+    }
+
+    return exitPending;
+}
+#endif
+
+static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t *field_width, uint8_t *base)
+{
+    uint8_t exitPending = 0U;
+    char *c             = *str;
+
+    /* Loop to get full conversion specification. */
+    while (('\0' != (*c)) && (0U == (*flag & (uint32_t)kSCANF_DestMask)))
+    {
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+        if ('*' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_Suppress))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                (*flag) |= (uint32_t)kSCANF_Suppress;
+            }
+        }
+        else if ('h' == (*c))
+        {
+            exitPending = strFormatScanfHandleh(exitPending, &c, flag);
+        }
+        else if ('l' == (*c))
+        {
+            exitPending = strFormatScanfHandlel(exitPending, &c, flag);
+        }
+        else
+#endif /* SCANF_ADVANCED_ENABLE */
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+            if ('L' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                (*flag) |= (uint32_t)kSCANF_LengthLongLongDouble;
+            }
+        }
+        else
+#endif /* SCANF_FLOAT_ENABLE */
+            if (((*c) >= '0') && ((*c) <= '9'))
+            {
+                {
+                    char *p;
+                    errno          = 0;
+                    (*field_width) = strtoul(c, &p, 10);
+                    if (0 != errno)
+                    {
+                        *field_width = 0U;
+                    }
+                    c = p - 1;
+                }
+            }
+            else if ('d' == (*c))
+            {
+                (*base) = 10U;
+                (*flag) |= (uint32_t)kSCANF_TypeSinged;
+                (*flag) |= (uint32_t)kSCANF_DestInt;
+            }
+            else if ('u' == (*c))
+            {
+                (*base) = 10U;
+                (*flag) |= (uint32_t)kSCANF_DestInt;
+            }
+            else if ('o' == (*c))
+            {
+                (*base) = 8U;
+                (*flag) |= (uint32_t)kSCANF_DestInt;
+            }
+            else if (('x' == (*c)))
+            {
+                (*base) = 16U;
+                (*flag) |= (uint32_t)kSCANF_DestInt;
+            }
+            else if ('X' == (*c))
+            {
+                (*base) = 16U;
+                (*flag) |= (uint32_t)kSCANF_DestInt;
+            }
+            else if ('i' == (*c))
+            {
+                (*base) = 0U;
+                (*flag) |= (uint32_t)kSCANF_DestInt;
+            }
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+            else if (1U == StrFormatScanIsFloat(c))
+            {
+                (*flag) |= (uint32_t)kSCANF_DestFloat;
+            }
+#endif /* SCANF_FLOAT_ENABLE */
+            else if ('c' == (*c))
+            {
+                (*flag) |= (uint32_t)kSCANF_DestChar;
+                if (MAX_FIELD_WIDTH == (*field_width))
+                {
+                    (*field_width) = 1;
+                }
+            }
+            else if ('s' == (*c))
+            {
+                (*flag) |= (uint32_t)kSCANF_DestString;
+            }
+            else
+            {
+                exitPending = 1U;
+            }
+
+        if (1U == exitPending)
+        {
+            break;
+        }
+        else
+        {
+            c++;
+        }
+    }
+    *str = c;
+    return exitPending;
+}
+
+static void StrFormatScanfHandleChar(
+    const char **Cp, uint32_t *field_width, char **buf, uint32_t flag, uint32_t *n_decode, uint32_t *nassigned)
+{
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+    uint8_t added = 0;
+#endif
+    while ((0U != ((*field_width)--))
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+           && ('\0' != (**Cp))
+#endif
+    )
+    {
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+        if (0U != (flag & (uint32_t)kSCANF_Suppress))
+        {
+            (*Cp) = (*Cp) + 1U;
+        }
+        else
+#endif
+        {
+            **buf  = **Cp;
+            (*Cp)  = (*Cp) + 1U;
+            (*buf) = (*buf) + 1U;
+
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+            added = 1u;
+#endif
+        }
+        *n_decode = *n_decode + 1U;
+    }
+
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+    if (1u == added)
+#endif
+    {
+        *nassigned = *nassigned + 1U;
+    }
+}
+
+static void StrFormatScanfHandleString(
+    const char **Sp, uint32_t *field_width, char **buf, uint32_t flag, uint32_t *n_decode, uint32_t *nassigned)
+{
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+    uint8_t added = 0;
+#endif
+    while ((0U != ((*field_width)--)) && (**Sp != '\0') && (0U == ScanIsWhiteSpace(**Sp)))
+    {
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+        if (0U != (flag & (uint32_t)kSCANF_Suppress))
+        {
+            (*Sp) = (*Sp) + 1U;
+        }
+        else
+#endif
+        {
+            **buf  = **Sp;
+            (*buf) = (*buf) + 1U;
+            (*Sp)  = (*Sp) + 1U;
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+            added = 1u;
+#endif
+        }
+        *n_decode = *n_decode + 1U;
+    }
+
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+    if (1u == added)
+#endif
+    {
+        /* Add NULL to end of string. */
+        **buf      = '\0';
+        *nassigned = *nassigned + 1U;
+    }
+}
+
+/*!
+ * brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * param[in] line_ptr The input line of ASCII data.
+ * param[in] format   Format first points to the format string.
+ * param[in] args_ptr The list of parameters.
+ *
+ * return Number of input items converted and assigned.
+ * retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
+{
+    uint8_t base;
+    int8_t neg;
+    /* Identifier for the format string. */
+    char *c = format;
+    char *buf;
+    /* Flag telling the conversion specification. */
+    uint32_t flag = 0;
+    /* Filed width for the matching input streams. */
+    uint32_t field_width;
+    /* How many arguments are assigned except the suppress. */
+    uint32_t nassigned = 0;
+    /* How many characters are read from the input streams. */
+    uint32_t n_decode = 0;
+
+    int32_t val;
+
+    uint8_t added = 0U;
+
+    uint8_t exitPending = 0;
+
+    const char *s;
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+    char *s_temp; /* MISRA C-2012 Rule 11.3 */
+#endif
+
+    /* Identifier for the input string. */
+    const char *p = line_ptr;
+
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+    double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+    /* Return EOF error before any conversion. */
+    if (*p == '\0')
+    {
+        return -1;
+    }
+
+    /* Decode directives. */
+    while (('\0' != (*c)) && ('\0' != (*p)))
+    {
+        /* Ignore all white-spaces in the format strings. */
+        if (0U != ScanIgnoreWhiteSpace((const char **)((void *)&c)))
+        {
+            n_decode += ScanIgnoreWhiteSpace(&p);
+        }
+        else if (0U == StrFormatScanIsFormatStarting(c))
+        {
+            /* Ordinary characters. */
+            c++;
+            if (*p == *c)
+            {
+                n_decode++;
+                p++;
+                c++;
+            }
+            else
+            {
+                /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+                 * However, it is deserted now. */
+                break;
+            }
+        }
+        else
+        {
+            /* convernsion specification */
+            c++;
+            /* Reset. */
+            flag        = 0;
+            field_width = MAX_FIELD_WIDTH;
+            base        = 0;
+
+            exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base);
+
+            if (1U == exitPending)
+            {
+                /* Format strings are exhausted. */
+                break;
+            }
+
+            /* Matching strings in input streams and assign to argument. */
+            if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestChar)
+            {
+                s   = (const char *)p;
+                buf = va_arg(args_ptr, char *);
+                StrFormatScanfHandleChar(&p, &field_width, &buf, flag, &n_decode, &nassigned);
+            }
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestString)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                buf = va_arg(args_ptr, char *);
+                StrFormatScanfHandleString(&p, &field_width, &buf, flag, &n_decode, &nassigned);
+            }
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestInt)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                s    = p;
+                val  = 0;
+                base = StrFormatScanGetBase(base, s);
+
+                added = StrFormatScanCheckSymbol(p, &neg);
+                n_decode += added;
+                p += added;
+                field_width -= added;
+
+                s = p;
+                if (strlen(p) > field_width)
+                {
+                    char temp[12];
+                    char *tempEnd;
+                    (void)memcpy(temp, p, sizeof(temp) - 1U);
+                    temp[sizeof(temp) - 1U] = '\0';
+                    errno                   = 0;
+                    val                     = (int32_t)strtoul(temp, &tempEnd, (int)base);
+                    if (0 != errno)
+                    {
+                        break;
+                    }
+                    p = p + (tempEnd - temp);
+                }
+                else
+                {
+                    char *tempEnd;
+                    errno = 0;
+                    val   = (int32_t)strtoul(p, &tempEnd, (int)base);
+                    if (0 != errno)
+                    {
+                        break;
+                    }
+                    p = tempEnd;
+                }
+                n_decode += (uintptr_t)p - (uintptr_t)s;
+
+                val *= neg;
+
+                nassigned += StrFormatScanFillInteger(flag, &args_ptr, val);
+            }
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                errno = 0;
+
+                fnum = strtod(p, (char **)&s_temp);
+                s    = s_temp; /* MISRA C-2012 Rule 11.3 */
+
+                /* MISRA C-2012 Rule 22.9 */
+                if (0 != errno)
+                {
+                    break;
+                }
+
+                if ((fnum < HUGE_VAL) && (fnum > -HUGE_VAL))
+                {
+                    n_decode = (uint32_t)n_decode + (uint32_t)s - (uint32_t)p;
+                    p        = s;
+                    nassigned += StrFormatScanFillFloat(flag, &args_ptr, fnum);
+                }
+            }
+#endif /* SCANF_FLOAT_ENABLE */
+            else
+            {
+                break;
+            }
+        }
+    }
+    return (int)nassigned;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_str.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_str.h
new file mode 100644
index 0000000000..32382faec2
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/utilities/fsl_str.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+    kPRINTF_Minus             = 0x01U,  /*!< Minus FLag. */
+    kPRINTF_Plus              = 0x02U,  /*!< Plus Flag. */
+    kPRINTF_Space             = 0x04U,  /*!< Space Flag. */
+    kPRINTF_Zero              = 0x08U,  /*!< Zero Flag. */
+    kPRINTF_Pound             = 0x10U,  /*!< Pound Flag. */
+    kPRINTF_LengthChar        = 0x20U,  /*!< Length: Char Flag. */
+    kPRINTF_LengthShortInt    = 0x40U,  /*!< Length: Short Int Flag. */
+    kPRINTF_LengthLongInt     = 0x80U,  /*!< Length: Long Int Flag. */
+    kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+    kSCANF_Suppress   = 0x2U,    /*!< Suppress Flag. */
+    kSCANF_DestMask   = 0x7cU,   /*!< Destination Mask. */
+    kSCANF_DestChar   = 0x4U,    /*!< Destination Char Flag. */
+    kSCANF_DestString = 0x8U,    /*!< Destination String FLag. */
+    kSCANF_DestSet    = 0x10U,   /*!< Destination Set Flag. */
+    kSCANF_DestInt    = 0x20U,   /*!< Destination Int Flag. */
+    kSCANF_DestFloat  = 0x30U,   /*!< Destination Float Flag. */
+    kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+    kSCANF_LengthChar        = 0x100U, /*!< Length Char Flag. */
+    kSCANF_LengthShortInt    = 0x200U, /*!< Length ShortInt Flag. */
+    kSCANF_LengthLongInt     = 0x400U, /*!< Length LongInt Flag. */
+    kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif                                 /* SCANF_ADVANCED_ENABLE */
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+    kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif                                     /*PRINTF_FLOAT_ENABLE */
+    kSCANF_TypeSinged = 0x2000U,           /*!< TypeSinged Flag. */
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt   Format string for printf.
+ * @param[in] ap  Arguments to printf.
+ * @param[in] buf  pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/CMakeLists.txt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/CMakeLists.txt
new file mode 100644
index 0000000000..bfe24c385f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/CMakeLists.txt
@@ -0,0 +1,339 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright 2022 NXP
+
+# define part number for this driver
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8987
+    SD8987
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW416
+    SD8978
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW61X
+    SD9177
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8801
+    SD8801
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_RW610
+    RW610
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW_rw610.h"
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8987_AW_CM358_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x09
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8987_AW_CM358MA_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x09
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8987_MURATA_1ZM_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_1ZM_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x06
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x06
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8987_MURATA_1ZM_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_1ZM_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x06
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x06
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW416_AW_AM457_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x09
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW416_AW_AM457MA_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x09
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW416_AW_AM510_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x09
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW416_AW_AM510MA_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_1XK_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x09
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW416_MURATA_1XK_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_1XK_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x00
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW416_MURATA_1XK_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_1XK_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x00
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0C
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW612_MURATA_2EL_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_2EL_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x0A
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0A
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW612_MURATA_2EL_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_2EL_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x0A
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0A
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW611_MURATA_2DL_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_2EL_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x0A
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0A
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_IW611_MURATA_2DL_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_2EL_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x0A
+    CONFIG_NXP_WIFI_ED_OFFSET_5G=0x0A
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8801_AW_NM191_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x1B
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8801_AW_NM191MA_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x1B
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8801_MURATA_2DS_USD
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_2DS_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x0E
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_88W8801_MURATA_2DS_M2
+    WIFI_BT_TX_PWR_LIMITS="wlan_txpwrlimit_cfg_murata_2DS_WW.h"
+    CONFIG_NXP_WIFI_ED_OFFSET_2G=0x0E
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_NXP_WIFI_BT_USE_USD_INTERFACE
+    WIFI_BT_USE_USD_INTERFACE
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_NXP_WIFI_BT_USE_M2_INTERFACE
+    WIFI_BT_USE_M2_INTERFACE
+)
+
+zephyr_library_compile_definitions(
+    FSL_OSA_TASK_ENABLE=1
+)
+
+zephyr_library_sources(${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/utilities/misc_utilities/fsl_memcpy.S)
+
+zephyr_library_sources(${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/lists/fsl_component_generic_list.c)
+
+zephyr_library_sources(${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/osa/fsl_os_abstraction_zephyr.c)
+
+zephyr_include_directories(
+    incl
+    incl/wifidriver
+    incl/wlcmgr
+    incl/port/net
+    incl/port/osa
+    incl/port/net/zephyr
+    port/osa
+    port/net/zephyr
+    sdio_nxp_abs/incl
+    firmware_dnld
+    fwdnld_intf_abs
+    wifidriver
+    wifidriver/incl
+    wifi_bt_firmware
+    wifi_bt_firmware/8987
+    wifi_bt_firmware/IW416
+    wifi_bt_firmware/nw61x
+    wifi_bt_firmware/8801
+    cli
+    ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/osa/
+    ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/lists/
+    ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/wifi_bt_module/AzureWave/tx_pwr_limits/
+    ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/wifi_bt_module/Murata/tx_pwr_limits/
+)
+
+# OS abstraction layer source
+zephyr_library_sources(
+    port/osa/osa.c
+    port/osa/osa_zephyr.c
+)
+# net stack abstraction layer source
+zephyr_library_sources(port/net/zephyr/net.c)
+
+file(GLOB WIFI_SRC ./wifidriver/*.c)
+list(FILTER WIFI_SRC EXCLUDE REGEX ".*imu.c$")
+list(FILTER WIFI_SRC EXCLUDE REGEX ".*sdio.c$")
+list(FILTER WIFI_SRC EXCLUDE REGEX ".*firmware_dnld.c$")
+
+zephyr_library_sources_ifdef(CONFIG_RW610
+    wifidriver/wifi-imu.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_SDIO_STACK
+    wifidriver/sdio.c
+    sdio_nxp_abs/fwdnld_sdio.c
+    sdio_nxp_abs/mlan_sdio.c
+    wifidriver/wifi-sdio.c
+    firmware_dnld/firmware_dnld.c
+    fwdnld_intf_abs/fwdnld_intf_abs.c
+)
+
+zephyr_library_sources(${WIFI_SRC})
+
+file(GLOB WLCMGR_SRC ./wlcmgr/*.c)
+#list(FILTER WLCMGR_SRC EXCLUDE REGEX ".*tests*")
+#list(FILTER WLCMGR_SRC EXCLUDE REGEX ".*cli*")
+
+zephyr_library_sources(${WLCMGR_SRC})
+
+zephyr_library_sources_ifdef(CONFIG_NXP_WIFI_SMOKE_TESTS
+    nw_utils/init_enet.c
+)
+
+zephyr_include_directories_ifdef(CONFIG_NXP_WIFI_SMOKE_TESTS
+    nw_utils
+)
+
+if(CONFIG_NXP_WIFI_SIGMA_AGENT)
+zephyr_library_sources(
+    nw_utils/wifi_ping.c
+    sigma_agent/sigma_agent.c
+    sigma_agent/dut/wfa_dut.c
+    sigma_agent/dut/wfa_dut_init.c
+)
+
+file(GLOB SIGMA_SRC ./sigma_agent/lib/*.c)
+list(FILTER SIGMA_SRC EXCLUDE REGEX ".*cmdproc*")
+list(FILTER SIGMA_SRC EXCLUDE REGEX ".*ca_resp*")
+zephyr_library_sources(${SIGMA_SRC})
+endif()
+
+zephyr_library_include_directories_ifdef(CONFIG_NXP_WIFI_SIGMA_AGENT
+    PRIVATE ${ZEPHYR_BASE}/subsys/net/ip)
+
+zephyr_library_include_directories_ifdef(CONFIG_NXP_WIFI_SIGMA_AGENT
+    sigma_agent/inc
+    sigma_agent/dut
+)
+
+file(GLOB DHCPD_SRC ./dhcpd/*.c)
+list(FILTER DHCPD_SRC EXCLUDE REGEX ".*cli*")
+
+zephyr_library_sources(${DHCPD_SRC})
+zephyr_library_include_directories(dhcpd)
+
+# nxp wifi shell
+zephyr_library_sources(cli/wifi_shell.c)
+zephyr_library_sources(cli/cli_utils.c)
+
+# macros for wpa_supplicant
+if(CONFIG_WPA_SUPP)
+zephyr_include_directories(certs)
+
+zephyr_library_include_directories(wifidriver/wpa_supp_if wifidriver/wpa_supp_if/incl)
+file(GLOB WIFI_SUPP_SRC ./wifidriver/wpa_supp_if/*.c)
+zephyr_library_sources(${WIFI_SUPP_SRC})
+endif()
+
+if(CONFIG_SPEED_OPTIMIZATIONS OR CONFIG_SIZE_OPTIMIZATIONS)
+# critical path code relocated to SRAM
+zephyr_code_relocate(FILES
+                     port/net/net.c
+                     port/osa/osa.c
+                     port/osa/osa_zephyr.c
+                     port/net/zephyr/net.c
+                     sdio_nxp_abs/mlan_sdio_zephyr.c
+                     wifidriver/mlan_11n.c
+                     wifidriver/mlan_11n_aggr.c
+                     wifidriver/mlan_11n_rxreorder.c
+                     wifidriver/mlan_wmm.c
+                     wifidriver/wifi.c
+                     LOCATION RAM_TEXT)
+
+if(CONFIG_SDIO_STACK)
+zephyr_code_relocate(FILES
+                     sdio_nxp_abs/mlan_sdio.c
+                     wifidriver/wifi-sdio.c
+                     LOCATION RAM_TEXT)
+endif()
+
+if(CONFIG_RW610)
+zephyr_code_relocate(FILES
+                     # fsl_cache.c
+                     # ${ZEPHYR_BASE}/modules/hal_nxp/fsl_memcpy.S
+                     wifidriver/wifi-imu.c
+                     ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/osa/fsl_os_abstraction_zephyr.c
+                     ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/drivers/imu/fsl_imu.c
+                     ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/rpmsg/fsl_adapter_rfimu.c
+                     LOCATION RAM_TEXT)
+endif()
+
+zephyr_code_relocate(FILES
+                     # fsl_cache.c
+                     # ${ZEPHYR_BASE}/modules/hal_nxp/fsl_memcpy.S
+                     ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/components/osa/fsl_os_abstraction_zephyr.c
+                     ${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/utilities/misc_utilities/fsl_memcpy.S
+                     LOCATION RAM_TEXT)
+
+file(GLOB ZPERF_SRC ${ZEPHYR_BASE}/subsys/net/lib/zperf/*.c)
+zephyr_code_relocate(FILES ${ZPERF_SRC} LOCATION RAM_TEXT)
+
+file(GLOB SOCKET_SRC ${ZEPHYR_BASE}/subsys/net/lib/sockets/*.c)
+zephyr_code_relocate(FILES ${SOCKET_SRC} LOCATION RAM_TEXT)
+
+file(GLOB NET_SRC ${ZEPHYR_BASE}/subsys/net/ip/*.c)
+zephyr_code_relocate(FILES ${NET_SRC} LOCATION RAM_TEXT)
+
+file(GLOB ETH_SRC ${ZEPHYR_BASE}/subsys/net/l2/ethernet/*.c)
+zephyr_code_relocate(FILES ${ETH_SRC} LOCATION RAM_TEXT)
+
+zephyr_code_relocate(FILES ${ZEPHYR_BASE}/subsys/net/buf.c LOCATION RAM_TEXT)
+
+zephyr_code_relocate(FILES
+                     ${ZEPHYR_BASE}/kernel/mem_slab.c
+                     ${ZEPHYR_BASE}/kernel/mempool.c
+                     ${ZEPHYR_BASE}/kernel/msg_q.c
+                     ${ZEPHYR_BASE}/kernel/mutex.c
+                     ${ZEPHYR_BASE}/kernel/queue.c
+                     ${ZEPHYR_BASE}/kernel/sched.c
+                     ${ZEPHYR_BASE}/kernel/sem.c
+                     ${ZEPHYR_BASE}/kernel/thread.c
+                     ${ZEPHYR_BASE}/kernel/work.c
+                     LOCATION RAM_TEXT)
+endif()
+
+zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/ChangeLogKSDK.txt b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/ChangeLogKSDK.txt
new file mode 100644
index 0000000000..c6685ff066
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/ChangeLogKSDK.txt
@@ -0,0 +1,1061 @@
+/*!
+@page middleware_log Middleware Change Log
+
+@section wifi NXP WiFi
+
+Version 1.3.r47.p16
+ - Updates:
+  - Updated FC's f/w version to 2.p66.155.
+  - Updated CA2 and RB3+ f/w version to 21.p124.
+  - Fine tuning of GTK rekey offload feature.
+
+Version 1.3.r47.p15
+ - Bug Fix:
+  - DUT fails to connect to Ex-AP configured with wpa2 Enterprise security (Auth method Fast-mschapv2).
+  - Incorrect AKM types PSK(2), PSK(SHA-256) are seen in beacon after configuring APUT in wpa2-psk security mode.
+  - Link lost seen after wlan-scan when DUT is connected in wpa2 ft-psk security in 2.4Ghz band.
+
+Version 1.3.r47.p12
+ - Bug Fix:
+  - Throughput numbers for TCP-Rx traffic on APUT are dropping to 0mbps in HE20/VHT20 mode.
+
+Version 1.3.r47.p11
+ - Bug Fix:
+  - Failed to connect STAUT configured in WPA2+PMF required security to Ex-AP configured in WPA2/WPA3 mixed mode+PMF capable security.
+  - STAUT is waking up with Broadcast traffic while running MEF AUTO PING ALLOW and WAKE HOST & MEF AUTO PING DISCARD and WAKE HOST.
+  - Cannot connec to AP with security wpa3_sb_192_eap_tls.
+  - Cannot out band independent reset successfully.
+
+Version 1.3.r47.p10
+ - Bug Fix:
+  - Auto reconnect - link lost reported when ap shut down.
+  - STAUT failed to roam from Ex-AP1 to Ex-AP2 with WPA3 security mode while running UDP-Tx traffic.
+  - STAUT is not waking up from suspend state while running Host-sleep test even after running Unicast/Broadcast traffic from Ex-AP to STAUT.
+  - STAUT is waking up with Unicast data and without unicast data as well before running Broadcast data traffic from AP backend to STAUT.
+  - While running WPS connection with Ex-AP, DUT gets deauthenticated after M4 packet, WPS_NACK is recvd. M1 packet does not have WPS PBC or keypad specific bit set
+  - "Network not found" is seen on the STAUT after disconnection and reconnection of the same profile in UNII4 channels (169,173,177).
+  - When Dut reported Link lost, After configured time interval, DUT reconnects to AP but fails to ping to AP_BACKEND after reconnection.
+  - Coverity Fixes.
+
+Version 1.3.r47.p9
+ - Bug Fix:
+  - APUT is advertising channel width information for 40Mhz in HE-phy capabilities instead of 20Mhz bandwidth in Assoc response frame.
+  - STAUT failed to roam from Ex-AP1 to Ex-AP2 with WPA3 security mode with same channel same band and different channel same band scenario.
+  - 15-20% Throughput degradation observed in TCP-TX and UDP-TX of HE[40Mhz/80MHz], VHT[40Mhz/80Mhz] compared to previous release[R45.p12].
+  - "WLAN: Network not found" is observed while connecting STAUT configured in wpa2 security PMF capable to Ex-AP in wpa2 security with PMF required.
+  - Coverity Fixes.
+
+Version 1.3.r47.p8
+ - Bug Fix:
+  - "WLAN: network not found & Warn: Scan temporary failure" is observed after disconnecting from one network and Re-connecting to same network after renaming SSID of Ex-AP.
+  - "Network not found" is seen on the STAUT after disconnection and reconnection of the same profile in UNII4 channels (169,173,177).
+  - Beacons not stopping in the older channel, after uAP switching the channel according to the Ex-AP in simultaneous mode.
+  - Incorrect return value on error.
+
+Version 1.3.r47.p7
+ - Bug Fix:
+  - STA STRESS | Independent Reset, DUT went to hang state after 134 iterations of independent reset with status "ASSERT: wlan_process_hang: 982 Assert failed: Panic"!
+  - Error message "'is_mef' undeclared(first use in this function)" is observed while the time of compilation of binary after enabling macro for the host-sleep.
+  - DUT not able to roam from AP1 to AP2 in different channel (DFS) and same Band on reducing the RSSI of AP1.
+  - STAUT failed to roam from Ex-AP1 to Ex-AP2 with WPA3 security mode while running UDP-Tx traffic.
+  - MEF, DUT fails to wakeup with mef conditions ping 1,3 and arp 1 & 3.
+
+Version 1.3.r47.p6
+ - Features
+  - Add GTK rekey offload support.
+  - Independent Reset via In-band
+  - Independent Reset via Out-of-Band
+ - Updates:
+  - Updated FC's f/w version to 2.p66.14.
+ - Bug Fix:
+  - Power save/host sleep support improvements.
+  - Messy log output after in band independent reset(17 in 31)
+  - Association_Req content corrupted when Dut config as WPA/WPA2 mix mode and connecting to AP WPA+TKIP
+  - Cannot connect to AP with security wpa3_sb_192_eap_tls.
+  - Command "wlan-add-packet-filter 1" is not available for setting MEF filter configuration in Host-sleep.
+  - WPA3 Enterprise support (Host based - Remaining set of authentication methods)
+  - STAUT failed to roam from Ex-AP1 to Ex-AP2 with WPA3 security mode while running UDP-Tx traffic.
+  - No Link lost is observed while switching from 11n[2.4G | 20Mhz] to legacy[2.4G] mode.
+  - The introduction of new features does not follow the scope limitations of modules and apps
+  - STAUT 11r, DUT unable to roam to particular BSSID after 10 to 15 iterations of roam, showing "Roaming already in progress Started FT roaming"
+  - STAUT | After DUT wake up from Hostsleep condition 0x10 (WAKE_ON_ARP_BROADCAST) Ping failed from AP_Backend to DUT and Delayed ping from DUT to AP_Backend
+  - Error: ignoring scan request in invalid state
+  - Fix COVERITY Issue for midware_wifi
+
+Version 1.3.r47.p5
+ - Updates:
+  - Updated FC's f/w version to 2.p66.11.
+ - Bug Fix:
+  - AKM checks are wrong for UAP PMF MANDATORY WPA2 PSK STA PMF MANDATORY WPA2 PSK for 11AN[20Mhz] as well as BGN[20Mhz] mode.
+  - STAUT is not waking up in any scenarios after giving Host-sleep commands with default power save enabled mode.
+
+Version 1.3.r47.p4
+ - Features
+  - Added support for Doxygen.
+ - Bug Fix:
+  - AKM checks are wrong for UAP PMF MANDATORY WPA2 PSK STA PMF MANDATORY WPA2 PSK for 11AN[20Mhz] as well as BGN[20Mhz] mode.
+  - On DUT manually configured parameters of 11axcfg, not getting reset to default after "wlan-reset" command execution.
+  - 2G to 5G and 5G to 2G FTOA roaming fails , link lost observed with permanent disconnect
+  - Change of bandwidth from 80Mhz to 40 MHz is observed after uAP (APUT) is stopped and started again, in HE/VHT band.
+  - STAUT unable to scan Ex-AP in UNII4 channels (169,173,177) with any Band/security.
+  - "Command response timed out. command 0x107" observed after 945 iterations in Scan-Connect-Disconnect Test without any traffic [Idle Test].
+  - RT Console hangs after enabling WLAN/BT Independent Download.
+  - Cannot get full iperf summary.
+  - While running UDP Bi-directional traffic, QOS data packets are not going from APUT/STAUT.
+
+Version 1.3.r47.p3
+ - Updates:
+  - Updated FC's f/w version to 2.p66.6.
+  - Updated CA2 and RB3+ f/w version to 21.221.
+ - Features
+  - Added FW (Parallel) Download support.
+ - Bug Fix:
+  - WiFi hang up with memory alloc buffer error during perform WiFi-scan along with WiFi independent reset loop test(OT already form the NTW)
+  - TCP-Keep-Alive packets are not seen in sniffer after successfully setting configuration commands for cloud keep alive and STAUT is not waking up after putting in suspend state.
+  - STAUT is not waking up from suspend state while running Host-sleep test even after running Unicast/Broadcast traffic from Ex-AP to STAUT.
+  - AKM checks are wrong for UAP PMF MANDATORY WPA2 PSK STA PMF MANDATORY WPA2 PSK for 11AN[20Mhz] as well as BGN[20Mhz] mode.
+  - Ex-STA (Kestrel, Firecrest RT1060-EVKC) Failed to associate in WPA2 PMF disabled mode to APUT configured in WPA2/WPA3 mixed security mode.
+  - STAUT, failed to Associate in WPA2 security with PMF disabled to Ex-AP configured in WPA2/WPA3 mixed security mode.
+
+Version 1.3.r47.p2
+ - Bug Fix:
+  - Fail to disable IEEE Power save mode, while giving command to disable it.
+  - NXP devices Kestrel/KF2-RD(STA) unable to connect to DUT as MMH-AP but connecting with Mobile, Four way Handshake Timeout is observed with NXP Devices
+  - Ex-STA(Kestrel, KF2) Assoc-reject is observed with uAP configured in OWE security mode.
+  - Cannot connect to 5g external AP.
+
+Version 1.3.r47.p1
+ - Updates:
+  - Updated CA2 and RB3+ f/w version to 21.p109
+  - Updated 8801 f/w version to 36_186
+  - Updated Firecrest firmware version to p66.5.
+ - Features
+  - Added EVKC board support for all SoCs.
+  - Added WPA2/3 Enterprise support for EAP-SIM/EAP-AKA/EAP-AKA-PRIME for STA and uAP.
+  - Added CSI support.
+  - Added Auto Reconnect support.
+  - Added CA2 and RB3+ Parallel FW Download support.
+  - Added CA2 and RB3+ Independent Reset via In-band support.
+  - Added CA2 and RB3+ Independent Reset via Out-of-Band support.
+  - Added CA2 and RB3+ Boot sleep patch support.
+
+Version 1.3.r46.p7
+ - Updates:
+  - Updated Falcon to p185, CA2 and RB3+ f/w version to 21.p91.5
+ - Bug Fix:
+  - uAP reassociation not working
+  - Traffic stops wen moving from auto rate to mcs0
+  - DUT not sending TCP-KEEP-ALIVE in suspend state
+  - DUT not able to roam from WPA-R1 enabled AP to WPA3-R3 enabled AP
+  - Ex-AP1 to Ex-AP2 roaming not working in wpa3
+  - STAUT is nto following BSS transition correctly
+  - RF test mode commands crash issue
+  - Ping is not working when uAP configured with wpa3-sb-192 bit EAP-TLS/EAP-TTLS/EAP-PEAP enterprise security.
+  - DUT shows network not found, even when connected to Ex-AP
+  - Stress test fixes
+
+Version 1.3.r46.p5
+ - Updates:
+  - Updated CA2 and RB3+ f/w version to 21.p91.5
+ - Bug Fix:
+  - Wifi random crash issue when DUT set to sleep
+  - Enable 11D for uAP by default
+  - STA doesnt get IP address when ieee-ps and deep sleep are enabled
+  - Coverity fixes
+  - BT/BLE fix for PTS test case
+
+Version 1.3.r46.p4
+ - Updates:
+  - Updated CA2 and RB3+ f/w version to 21.p91.4
+ - Bug Fix:
+  - Fixed: pre-cert: 20/40 BSS coexistence management is not supported in association request.
+  - Fixed: pre-cert: STAUT is not correctly following the MU EDCA parameters advertised by the AP.
+  - Fixed: Fail to connect to external AP with security wpa3.
+  - Fixed: uAP with wpa3 security is not connectable.
+  - Fixed: DUT not able to connect to Ex-AP in WPA2 security when PMF required is set.
+  - Fixed: Remove BAND_B rates from Supported rates for 5G channels during scan.
+  - Fixed: pre-cert STAUT is not including operating class 81 and 115 under Alternate Operating Classes in assoc request.
+  - Fixed: Cannot connect to external AP successfully.
+  - Fixed: 5Ghz channel are configured acceptable in 2.4Ghz band
+  - Fixed: wlan_set_rf_tx_power is not consistent with tx-frame power output
+  - Fixed: Getting compilation errors while compiling the binary after defining "CONFIG_UNII4_BAND_SUPPORT" macro in wifi_config.h file.
+  - Fixed: uAP Beacons advertise 3 AKM suites (PSK & PSK SHA256 & SAE SHA256) in RSNIE when WPA2+WPA3 mixed mode is set on AP with mfpc 1 and mfpr 0.
+  - Fixed: STAUT configured with WPA3-SAE associates to WPA2 configured AP.
+  - Fixed: DUT unable to roam from Ex-AP1 to Ex-AP2 on lowering the RSSI of Ex-AP1.
+  - Fixed: pre-cert STAUT is not correctly following the MU EDCA parameters advertised by the AP.
+  - Fixed: DUT-STA is unable to associate with WPA/WPA2 Mixed mode AP when DUT-STA is configure WPA security.
+  - Fixed: pre-cert STAUT fails to roam from WPA3 configured AP1 to WPA2-PSK configured AP2.
+  - Removed IEEE_MGMT_ACTION_CATEGORY_PUBLIC enum.
+  - Fixed logic for consecutive connect for both embedded and wpa supplicant.
+  - Fixed all compilation errors and warnings seen on dapeng.
+  - Resolved MISRA and coverity defects.
+
+Version 1.3.r46.p3
+ - Updates:
+  - Updated CA2 and RB3+ f/w version to 21.p91.2
+ - Bug Fix:
+  - Fixed: TCP and UDP TX traffic stream not working with ex-sta
+  - Fixed: pre-cert: STAUT is not following BSS transition correctly
+  - Fixed: Extend wlan-get-antcfg to print current antenna
+  - Fixed: DUT able to configure MFPR 0 in WPA3 security.
+  - Fixed: DUT MCS rates are not updating to default after stopping/removing previous profile with MCS set to fixed number via fixed rate command.
+  - Fixed: DUT-uAP unable to start with ACS configuration.
+  - Fixed: While running WPS connection with Ex-AP, DUT gets deauthenticated after M4 packet, WPS_NACK is recvd. M1 packet does not have WPS PBC or keypad specific bit set.
+  - Fixed: Fail to create ipv6 iperf client.
+  - Fixed: uAP beacons contain incorrect bit, UAPSD bit is set in WME QoS Info even though it is not supported.
+  - Fixed: uAP beacons contain incorrect bits, SU/MU Beamformer bits are set in HE Phy capabilities and UAPSD bit is set in WME QoS Info even though it is not supported.
+  - Fixed: Data path blocks once we initiate wlan-scan on DUT and change Ex-AP channel at the same time.
+  - Fixed: MISRA defects.
+
+Version 1.3.r46.p2
+ - Updates:
+  - Updated CA2 and RB3+ f/w version to 21.p91
+ - Bug Fix:
+  - Fixed BT connection issue on RB3+
+
+Version 1.3.r46.p1
+ - Updates:
+  - Updated CA2 and RB3+ f/w version to 21.p90
+  - Updated 8801 f/w version to 36_181
+  - CA2 Fixed FIPS GCMP support
+  - Added all changes as part of r45.p3 as applicable for CA2 and RB3+
+  - Added information for BSD3 license.
+  - Updated WLCMGR and Wi-Fi driver to support WPA supplicant and hostapd.
+  - Deepsleep feature in BLE peripheral role
+  - Deep Sleep and wakeup feature is enabled for CA2 and RB3+
+
+ - Features
+  - Added WPA supplicant and hostapd support.
+  - Added WPS 2.0 support for STA and uAP.
+  - Added WPA2 enterprise support for STA and uAP.
+  - Added WPA3 enterprise support with suite b and suite b 192 bit mode for STA and uAP.
+
+ - Bug Fixes:
+  - Fixed: APUT goes into hang state after every disassociation of STA.
+  - Fixed: (pre-cert)AMSDU Rx test fails as STAUT returns the throughput received as 0.
+  - Fixed: Country Information IE with default country code (WW) is seen in beacon even after changing the regions from WW to US/EU/CA/CN.
+  - Fixed: DUT should show "Network not found" message in cli, when Configure SSID is not present in network area.
+  - Fixed: DUT not able to connect to Ex-AP in WPA3R3 security.
+  - Fixed: DUT not able to roam from Ex-AP1 to Ex-AP2.
+  - Fixed: Hostsleep/MEF test condition failures are seen.
+  - Fixed: uAP not coming up in WPA2/WPA3 mixed mode security., getting "WPA initialization failed" on DUT console.
+  - Fixed: DUT shows wrong channel number in wlan-scan-opt and wlan-info command results.
+  - Fixed: DUT sending QoS data packets with LDPC coding when LDPC coding is disabled on Ex-STA.
+  - Fixed: Country Information IE is not seen in uAP Beacon.
+  - Fixed: DUT is going into hang state while running Connect/Disconnect Stress Test
+  - Fixed: Supported MCS and NSS rates are not properly set under HE capabilities IE in beacon frame when CAPA enabled binary is flashed on DUT.
+  - Fixed: Channel Bandwidth is setting to 80Mhz when uAP is configured in 11AX-40Mhz/20Mhz.
+  - Fixed: Beacon frame includes HE IE when uAP is configured in 11AC using Capa command.
+  - Fixed: DUT is not connecting in WPA2/WPA3 Enterprise security.
+  - Fixed: DUT is not getting ipv4 address after Roaming to Ex-AP2.
+  - Fixed: DUT is not roaming from AP1 to Ex-AP2 after running wlan-ft-roam command in 5Ghz.
+  - Fixed: DUT is not following BSS transition Correctly.
+  - Fixed: DUT is not responding Beacon Report Action frame after sending the Beacon request from Ex-AP to DUT.
+  - Fixed: Automatic Channel Selection is not working when DUT configured in MMH mode.
+  - Fixed: DUT is going for Reassociation with the same Ex-AP after running "wlan-host-11k-neighbour-req" command.
+  - Fixed: uAP Beacons does not include SHA256 in RSNIE when PMF mandatory is set on AP in WPA2-PSK security.
+  - Fixed: Low Throughput seen in 11AX, 11AC, 11N (80MHz, 40MHz & 20MHz) TCP-RX/TX, UDP-TX/RX in 2.4Ghz & 5Ghz.
+  - Fixed: DUT is not using "FT using PSK" AKM suite when 802.11R is enabled.
+  - Fixed: DUT not able to connect to Ex-AP in WPA2 security when PMF required is set.
+  - Fixed: Need to reset DUT every time for every new connection to happen.
+  - Fixed: Incorrect VHT IE "RX/TX MCS Map" is seen in uAP beacons.
+  - Fixed: uAP Beacons is advertising 4 Pairwise Cipher Suites [CCMP (256), GCMP (256), AES (CCM), GCMP (128)] in RSNIE with WPA2/WPA3 security.
+  - Fixed: uAP not coming up in 2.4GHz channel 11, getting "uAP start failed, giving up" on DUT console.
+  - Fixed: DUT is going in hang state after Stop/Remove/Start network in wpa2 and wpa3 security, when configured in MMH mode.
+  - Fixed: HE IE is not reflecting in beacons, when DUT is configured in default mode without capa in MMH.
+  - Fixed: DUT is not connecting in WPA3 security, shows "Error: Init of random number generator failed."
+
+Version 1.3.r45.p12
+ - Updates:
+  - Uodated tx pwr limit files for murata 2el module.
+  - Added config macro for RU Tx power.
+  - Updated WPA2/3 Enterprise support to handle pre-cert tests.
+
+ - Bug Fixes:
+  - Fixed: uAP not starting up in channel 14 showing start failed when uAP country code is set to JP.
+
+Version 1.3.r45.p11
+ - Updates:
+  - Added integrate tx pwr limit files for murata 2el module.
+  - Added support for legacy mode of RU Tx power.
+  - Updated WPA2/3 Enterprise support to handle pre-cert tests.
+
+ - Bug Fixes:
+  - Fixed: Bi-directional traffic converts to uni-directional traffic.
+  - Fixed: The support for "wlan-multi-mef" command to configure MEF
+  parameters on cli is not available.
+  - Fixed: Country Information IE with default country code (WW) is seen in
+  uAP beacon even after changing the regions from WW to US/EU/CA/CN.
+  - Fixed: Failed to wakeup card after turned on IEEE Power Save mode.
+  - Fixed: Bi-directional iperf traffic is not running getting dropped to
+  0.000 bits/sec.
+  - Fixed: Macbook not connecting with DUT-AP in channel 48 and BW 80MHz.
+  - Fixed: [pre-cert] DUT fails to connect to Ex-AP configured with wpa/wpa2
+  enterprise security (AES Encryption) and the radius server configured with
+  hostapd, unsupported certificate error.
+  - Fixed: Not connecting to AP in WPA-TKIP and WPA-AES, M2 is not being
+  initiated by STA.
+
+Version 1.3.r45.p10
+ - Updates:
+  - Updated firmware version to 2.p7.19 and added TP signed FW(with VDLL) too.
+  - Changed the init and command flow for uart_wifi_bridge app.
+
+ - Bug Fixes:
+  - Fixed: [pre-cert] DUT not correctly receiving AMPDU+AMSDU , AMSDU bit is not set to 1 in QOS data frame.
+  - Fixed: uAP not starting up in channel 14 showing start failed when uAP country code is set to JP.
+  - Fixed: Data path blocks once we initiate wlan-scan on DUT and change Ex-AP channel at the same time.
+  - Fixed: App will block/output error log when trying to set rf tx frame.
+
+Version 1.3.r45.p9
+ - Updates:
+  - Updated firmware version to 2.p7.17 and added TP signed FW(with VDLL) too.
+  - Added support for channel based RU Tx power.
+  - Added support of reassociate command on STAUT to test reassociate feature.
+
+ - Bug Fixes:
+  - Fixed: Ex-STA(Kestrel) not able to connect to uAP with "reassociate" command in first attempt, getting deauthentication and again connection is initiated with Association Request and connection happens, in wpa3 security.
+  - Fixed: [pre-cert] STAUT is sending incomplete beacon report response to AP's beacon report request.
+  - Fixed: Messy log output when trying to turn off deep sleep mode.
+  - Fixed: Unable to set TX-OMI on uAP using command "wlan-set-tx-omi".
+  - Fixed: DUT is not re-connecting when bandwidth/mode changed on Ex-AP.
+
+Version 1.3.r45.p7
+ - Updates:
+  - Updated firmware version to 2.p7.15 and added TP signed FW(with VDLL) too.
+ - Bug Fixes:
+  - Fixed: STAUT is not following BSS transition correctly.
+  - Fixed: DUT is not sending TCP-KEEP-ALIVE packets in suspend state, when TCP connection is established via Cloud keep alive command.
+  - Fixed: DUT not able to roam from Ex-AP1 to Ex-AP2 on lowering the RSSI of Ex-AP1 in wpa3 security.
+  - Fixed: STAUT's probe request does not contain MBO-OCE IE
+  - Fixed: Ping is not working when uAP configured with wpa3-sb-192 bit EAP-TLS/EAP-TTLS/EAP-PEAP enterprise security.
+  - Fixed: STAUT's probe request does not contain MBO-OCE IE.
+  - Fixed: Throughput enhancement for STA and uAP mode for various TCP/UDP and Tx-Rx modes for embedded and wpa supplicant.
+  - Fixed: "TCP_ABORTED_LOCAL" message seen on DUT console instead of "TCP_DONE" when running iperf traffic
+  - Fixed: [pre-cert] STAUT is not dropping TP when AP is increasing MPDU spacing factor from 0 to 3.
+
+Version 1.3.r45.p6
+ - Updates:
+  - Updated firmware version to 2.p7.11 and added TP signed FW(with VDLL) too.
+  - uart_wifi_bridge added and errors fixed for RT1170-EVKB.
+ - Bug Fixes:
+  - Fixed: Traffic stops after moving from auto rate to fixed mcs0. Command is triggered on the fly.
+  - Fixed: DUT not able to roam from WPA3R1 enabled AP to WPA3R3 enabled AP showing network not found.
+
+Version 1.3.r45.p5
+ - Updates:
+  - Updated firmware version to 2.p7.10 and added TP signed FW(with VDLL) too.
+
+ - Bug Fixes:
+  - Fixed: Data path blocks once we initiate wlan-scan on DUT and change Ex-AP channel at the same time.
+  - Fixed: uAP beacons contain incorrect bits, SU/MU Beamformer bits are set in HE Phy capabilities and UAPSD bit is set in WME QoS Info even though it is not supported.
+  - Fixed: uAP beacons contain incorrect bit, UAPSD bit is set in WME QoS Info even though it is not supported.
+  - Fixed: [pre-cert] STAUT is not correctly following the MU EDCA parameters advertised by the AP
+  - Fixed: [pre-cert] 20/40 BSS coexistence management is not supported in association request.
+  - Fixed: Fail to connect to external AP with security wpa3.
+  - Fixed: uAP with wpa3 security is not connectable.
+  - Fixed: DUT not able to connect to Ex-AP in WPA2 security when PMF required is set.
+  - Fixed: Remove BAND_B rates from Supported rates for 5G channels during scan.
+  - Fixed: Fix wifi_cli_prov example hang when connect if enable ieee power save and deep sleep.
+  - Fixed: RFTM: 5Ghz channel are configured acceptable in 2.4Ghz band.
+  - Fixed: RFTM: wlan_set_rf_tx_power is not consistent with tx-frame power output.
+  - Fixed: DUT not able to roam from AP1 to AP2 in different channel (DFS) and same Band on reducing the RSSI of AP1.
+  - Fixed: uAP Beacons advertise 3 AKM suites (PSK & PSK SHA256 & SAE SHA256) in RSNIE when WPA2+WPA3 mixed mode is set on AP with mfpc 1 and mfpr 0.
+  - Fixed: DUT unable to roam from Ex-AP1 to Ex-AP2 on lowering the RSSI of Ex-AP1.
+  - Fixed: Fixed build errors and warnings for matter, MISRA, coverity and other compilers.
+
+Version 1.3.r45.p4
+ - Updates:
+  - Updated firmware version to 2.p7.4 and added TP signed FW(with VDLL) too.
+
+ - Bug Fixes:
+  - Fixed: Fail to create ipv6 iperf client.
+  - Fixed: DUT MCS rates are not updating to default after stopping/removing previous profile with MCS set to fixed number via fixed rate command.
+  - Fixed: MISRA Defect fixed.
+  - Fixed: IEEE PS event not getting triggered.
+  - Fixed: While running WPS connection with Ex-AP, DUT gets deauthenticated after M4 packet, WPS_NACK is recvd. M1 packet does not have WPS PBC or keypad specific bit set.
+  - Fixed: Fail to create ipv6 iperf client.
+  - Fixed: Hang issue seen when assoc reject event received.
+
+Version 1.3.r45.p3
+ - Updates:
+  - Enabled h/w acceleration APIs via mbedtls.
+  - VDLL support added.
+
+ - Bug Fixes:
+  - Fixed: (pre-cert)Need support to set UL MU Disable/Data Disable element through TX-OMI command.
+  - Fixed: iTCP and UDP TX traffic stream not working with ex-sta.
+  - Fixed: STA not able to connect to APUT when APUT is configured in OWE security.
+  - Fixed: DUT is going on hang state after running "wlan-reset" command.
+  - Fixed: "TCP_ABORTED_REMOTE" message seen on DUT console when running UDP traffic.
+  - Fixed: (pre-cert)STAUT is not scanning Non Transmitted SSID in MBSSID test.
+  - Fixed: 6+ ms of traffic burst is seen which is failing cert criteria of max cot as 6ms.
+  - Fixed: DUT not getting IP address(DHCP) when "WMM_ENH" Macro is defined in "wifi_config.h" file for TWT feature.
+  - Fixed: For Tx Frame & tx-continuous, the Measured tx-power value is 2dBm irrespective of configured Tx-power(10/12/15/20dBm)
+  - Fixed: Data path blocks once we initiate wlan-scan on DUT and change Ex-AP channel at the same time.
+  - Fixed: DUT not able to scan and connect to DFS channels when Broadcast SSID is disabled.
+  - Fixed: Aggregation is broken when TCP/UDP TX Data is going with TID 6-7 (Voice), and TID 3 (Best Effort).
+  - Fixed: uAP not beaconing in 40MHz when uAP configured in channel 12/13-40MHz in MMH mode
+  - Fixed: STA Ping is not working once it roams to Ex-AP2.
+  - Fixed: Wi-Fi lwip port does not protect correctly concurrent accesses to lwip stack.
+  - Fixed: Beacon frame does not include RSN XE IE when uAP configured in WPA3R3 security.
+  - Fixed: Beacon frame includes HT IE when uAP configured in 11A mode using capa legacy command.
+  - Fixed: DUT not connecting to Ex-AP when PMF is configured using "wlan-set-pmfcfg" command.
+  - Resolved IAR, MCUX and MDK build errors.
+
+Version 1.3.r45.p2
+ - Updates:
+  - Updated firmware version to 2.p7.1 and added TP signed FW too.
+  - Added RFTM commands missing CLI commands related to OFDMA feature.
+  - Added support for EVKB board.
+
+ - Bug Fixes:
+  - Fixed: uAP not coming up in channel 14 when country code is set to JP.
+  - Fixed: DUT not able to connect with 32-character SSID when Ex-AP configured in open/wpa2/wpa3 security.
+  - Fixed: QoS Data packets not seen on air when we run "wlan-set-tx-omi 0x48 0xff 16" command on DUT.
+  - Fixed: [pre-cert] Not able to set non-preferred channel in MBO through wpa_cli on RTOS.
+  - Fixed: Automatic Channel Selection is not working when DUT configured in MMH mode.
+  - Fixed: STA not able to connect to APUT when APUT is configured in OWE security.
+  - Fixed: Wi-Fi lwip port does not protect correctly concurrent accesses to lwip stack.
+  - Fixed: DUT is going on hang state after running "wlan-reset" command.
+  - Resolved IAR, MCUX and MDK build errors.
+
+Version 1.3.r43.p9
+ - Updates:
+  - Added support for RF test mode.
+
+ - Bug Fixes:
+  - Fixed: (pre-cert)Updated help message for TX-OMI command.
+  - Fixed: (pre-cert)STAUT is not scanning Non Transmitted SSID in MBSSID test.
+  - Fixed: (pre-cert)STAUT is not governing OBSS Narrow Bandwidth RU in UL OFDMA Tolerance Support.
+  - Fixed compilation errors and warnings after branch merge.
+
+Version 1.3.r44.p3
+ - Bug fixes:
+  - Added RSNX IE for WPA3-R3 for uAP
+
+Version 1.3.r44.p2
+ - Updates:
+  - Updated CA2, RB3+ firmware to p82
+  - Bug fixes:
+   - Fixes for 11KR
+   - Fixes for WPA3-R3 STA
+   - Added extra event for Connected notification in case of uAP
+
+Version 1.3.r44.p1
+ - Updates:
+  - Updated CA2, RB3+ firmware to p79
+  - Updated 8801 firmware to p180
+
+ - Features:
+  - Added 11KVR support for CA2 and RB3+
+
+ - Bug fixes:
+  - Fixed: Association Request does not include Group Management Cipher Suite IE in RSNIE when PMF mandatory is set on STA in WPA2-PSK/WPA3/OWE security.
+  - Fixed: Sending of deauth codes in all scenarios
+  - Fixed: Command timeout issues for wlan-eu-crypto
+  - Added Coverity fixes
+  - Fixed command timeout seen during simultaneous AP + STA mode, with high
+  traffic on 8801
+  - Set proper value for Edmac value updated to support Murata 2DS Module
+  - Fixed Channel switch announcement is not seen in beacon in AP+STA mode,
+  when AP changes channel on 8801
+  - Added few BT Sig qualification fixes
+
+Version 1.3.r43.p8
+ - Updates:
+  - Updated firmware version to p182.1 and added TP signed secure FW too.
+
+ - Bug Fixes:
+  - Fixed: (pre-cert)APUT beacons does not have RSNXE when configured in H2E mode.
+
+Version 1.3.r43.p7
+ - Updates:
+  - Updated firmware version to p182.
+  - Added TP signed secure FW.
+  - Added support for 2EL M2 module for Firecrest.
+  - Added wifi capability configuration support.
+  - Added FIPS validation feature.
+  - Added wifi rf test mode example.
+  - Unified all wifi examples in wifi_cli.
+  - 11R is not surrpoted for FC.
+
+ - Bug Fixes:
+  - Modified the method to load RU tx power limit with RT.
+  - Modified txrate config design for 11AC and 11AX features.
+  - Added support for roaming and neighbor request processing.
+  - Fixed: "Error in sending Background traffic" messages seen on DUT while running Background TX-Traffic.
+  - Fixed: STAUT is not associating in WPA3 Hash-to-Element only mode.
+  - Fixed: Not able to change HE MAC Capabilities or HE PHY Capabilities in Association Request using 11axcfg command.
+  - Fixed: DUT not waking up from suspend state when we start multicast traffic after 30sec-1 minute.
+  - Fixed: STAUT hangs after scanning AP in scenario K of SI-5.2.2 test case.
+  - Fixed: STAUT is not including operating class 81 and 115 under Alternate Operating Classes in assoc request.
+  - Fixed: STAUT fails to roam from WPA3 cionfigured AP1 to WPA2-PSK configured AP2.
+  - Fixed: DUT goes for DHCP DORA Process after roaming to AP2 from AP1.
+  - Fixed build errors and warnings.
+  - Corrected description related to num_dat_pkts parameter of tx-omi command.
+
+Version 1.3.r43.p6
+ - Updates:
+  - Updated firmware version to p174 and added latest signed FW bins as well.
+
+ - Bug Fixes:
+  - Fixed: Command timeout issues observed for various offload commands.
+  - Fixed: TWT requester bit not set in Extended Capabilities IE (127) in Association Request and Probe Request of STAUT.
+  - Fixed: Not able to scan and connect Firecrest-STA to Firecrest-uAP configured in UNII-4 band channels 173 and 177.
+  - Fixed: Multiple error messages are seen on DUT while running the stress "RX ping on STA, Start-stop uAP" in loop.
+  - Added 11AX macro so that nss settings can be available for 11AC as well as 11AX based configurations.
+  - Fixed various warning for IAR, MDK, armgcc and mcuXpresso compilers.
+
+Version 1.3.r43.p5
+ - Updates:
+  - Updated firmware version to p168(however signed firmware is not updated in this release and has version p164).
+
+ - Bug Fixes:
+  - Fixed: DUT not able to connect to AP configured in WPA2/WPA3 mixed mode security.
+  - Fixed: Association Request does not include Group Management Cipher Suite IE in RSNIE when PMF mandatory is set on STA in WPA2-PSK/WPA3/OWE security.
+  - Fixed: uAP Beacons does not include SHA256 in RSNIE when PMF mandatory is set on AP in WPA2-PSK security.
+  - Fixed: Device getting hanged while setting txpwrlimit by CMD 'wlan-set-txpwrlimit'.
+  - Fixed: Not able to load RU tx power limit with RT.
+  - Fixed: Not able to change HE parameters in HE MAC Capabilities or HE PHY Capabilities using 11axcfg command.
+
+Version 1.3.r43.p4
+ - Updates:
+  - None.
+
+ - Bug Fixes:
+  - Updated helper message for owe_only cli.
+  - Fixed: Observed bi-directional data traffic on air while running uni-directional TCP-RX traffic.
+  - Fixed: UDP-TX traffic going without using aggregation.
+  - Throughput values will now be displayed on DUT while running iperf Tx and Rx traffic.
+
+Version 1.3.r43.p3
+ - Updates:
+  - Updated firmware version to p164.
+
+ - Bug Fixes:
+  - Added ed mac config support for uAP.
+  - Modified process_rsn_ie function on driver side to provide support for Group Management Cipher suite.
+  - Added conditional logic related to handling of region code.
+
+Version 1.3.r43.p2
+ - Bug Fixes:
+  - Added delay in uart_wifi_bridge application to correctly read calibration data for RB3P board.
+
+Version 1.3.r43.p1
+ - Updates:
+  - Updated firmware version to p162.
+  - Added MBO feature support.
+  - Added OWE feature support.
+
+ - Bug Fixes:
+  - uAP Beacons contains MFPC & MFPR bits set to 1 in WPA2-PSK security after removing the previous WPA3 security profile.
+  - Added new cli parameters for wlan-set-tx-omi command to send OMI using QoS Null Packet or QoS Data Packet according to input provided.
+  - Corrected 11R configuration macro in allMacros_iw61x.txt file and removed the same from ignoreMacros_iw61x.txt file.
+  - Coverity fix: Changed all WM_FAIL to -WM_FAIL.
+
+Version 1.3.r42.p4
+  -New Additions:
+   - CA2 and RB3+ f/w updated to v16_xx.21.p64.1
+
+Version 1.3.r42.p3
+  -New Additions:
+   - 8801 f/w update
+  -Bug Fixes:
+   - Fixed Misra issues.
+
+Version 1.3.r42.p2
+  -Bug Fixes:
+   - Fixed Misra issues.
+
+Version 1.3.r42.p1
+  -New Additions:
+   - RTOS abstraction improvement
+   - Added support for FIPS for CA2 and RB3+
+   - Added uAP 11AC support
+   - Deprecated support for 88W8977 Wi-Fi SoC
+   - Added 8978 SoC firmware p64.
+   - Added 8987 SoC firmware p64.
+   - Added mlanutl equivalent utility on RT to create wifi fw compatible command arrays.
+
+  -Bug Fixes:
+   - Fixed Misra issues.
+
+Version 1.3.r41.p2
+  -New Additions:
+   - Updated license header as a github friendly license.
+   - Added 8801 SoC firmware p177 with get Coex Statistics support.
+   - Added 8987 SoC firmware p32.2 with Bluetooth related fixes. Added fix for automatic ble disconnect issue.
+
+  -Bug Fixes:
+   - Fixed Unable to start/stop 11n rx reorder timer(50%).
+   - Fixed Getting Improper Channel Number in "wlan-get-uap-channel" command.
+   - Fixed DUT fails to start DHCP intermittently.
+   - Fixed wrong wlan-list output.
+   - Fixed station connect issue after host sleep is enabled and disabled.
+   - Fixed Misra and coverity issues.
+   - Fixed automatic ble disconnect issue after 30 seconds of connection establishment.
+
+Version 1.3.r41.p1
+  -Bug Fixes:
+   - Updated 8801 SoC firmware to toggle GRANT Pin with WLAN/BT time on HIGH Request with Low Priority.
+   - Added coverity fixes.
+
+Version 1.3.r40.p5
+  -Bug Fixes:
+   - Fixed issue of DUT not entering Powersave mode on all SoCs.
+
+Version 1.3.r40.p4
+  -Bug Fixes:
+   - Default bandwidth set to 20 MHz for uAP on 8977.
+   - Fixed an issue in static IPv4 address assignment.
+   - Fixed warning and errors for IAR, MDK and gn + ninja + armgcc toolchains.
+
+Version 1.3.r40.p3
+  -Bug Fixes:
+   - Added wlan_uap_set_httxcfg API to set 40 MHz support in 2.4 GHz.
+   - Fix for build issue seen for wifi_setup 1020
+
+Version 1.3.r40.p2
+  -Bug Fixes:
+   - Fixed IPv6 address and state updates as per the networking stack configuration.
+   - Removed errors shown in channel validation and in setting custom CFP tables
+   - Added API to support selection of 20 and 40 MHz bandwidth
+   - Added -b(bandwidth) option in wifi_cli iperf command
+   - DHCP client doesn't report the failure of obtaining IP address
+   - Remove dependency for wifi_config_internal.h
+   - Remove warnings reported for channel list variables
+   - Fix STA not sending data in 40M bandwidth for BGN 40 in 2.4G
+
+
+Version 1.3.r38.p2
+  - New Additions:
+   - Added Support for IPv6.
+   - Added support for Hostsleep and packet filters.
+   - Updated Firecrest Firmware version to p50.5.
+   - Updated CA2 Firmware version to p21.22.
+
+  -Bug Fixes:
+   - Fixed an issue where DUT not able to start UAP Network in 2G MMH Mode.
+   - Fixed an issue where Command 0xb2 timeout is seen when stopped uAP while running DL traffic.
+
+Version 1.3.r37.p4
+  - New Additions:
+   - Added support for new API for HostCmd in RT Platform.
+   - Added provision to set tx rates for HE mode in wlan_set_txratecfg API.
+   - Added support for new command to set tx OMI.
+   - Added WPA3 R3 support for 8801, RB3, RB3+ and CA2.
+   - Updated Firecrest firmware version to p50.2.
+   - Updated CA2 firmware version to p235.2
+   - Updated RB3+ firmware version to p11.3.
+   - Updated 8801 firmware version to p191.2
+   - Updated RB3 firmware version to p186.2.
+
+  - Bug Fixes:
+   - Fixed an issue where default netif was not set to STA after closing uAP.
+   - Fixed an issue where 30% low RX throughput was seen with 11AN 40Mhz.
+   - Fixed wlan_start and wlan_stop API working.
+   - Fixed High ping latency when DUT is put in IEEEPS mode.
+   - Fixed an issue where wlan_get_dtim_period API was not returning any value.
+   - Fixed SVD vulnerability issue on RB3+.
+   - Fixed MISRA/Coverity issues.
+   - Fixed SVD vulnerability issue on 8977, 8801 and CA2.
+   - Fixed an issue in Firecrest where STAUT is disconnecting immediately after ieeeps command is fired.
+   - Fixed an issue where UDP traffic was not working on uAP mode.
+   - Country code not being displayed in 11d is being fixed
+
+Version 1.3.r35.p2
+  - New Additions:
+   - Added support for 11ax for Firecrest.
+   - Updated Firecrest firmware version to p27.
+
+  - Bug Fixes:
+   - Fixed an issue for CA2 where tcp/udp Rx traffic was not seen with Linksys AP.
+   - Fixed tx power limit issue for Firecrest.
+   - Fixed an issue for Firecrest where Ping stops working after TCP traffic is started from DUT.
+   - Changed WLAN_PSK_MAX_LENGTH to 64 from 65.
+   - Fixed an issue where mfpc was not set properly.
+
+Version 1.3.r34.p2
+  - New Additions:
+   - Updated CA2(8987) SoC firmware to p235.1.
+
+  - Bug Fixes:
+   - Fixed WPA3 Authentication failure for CA2.
+   - Fixed SPP connection issue.
+
+version 1.3.r34.p1
+  - New Additions:
+   - Updated CA2(8987) SoC firmware to p235.
+   - Added Separation of fw download from Wi-Fi initialization.
+   - Added support for Multicast group creation
+   - Updated license content in the wlan src for Murata or Generic customer.
+   - Added support for new firmware version display.
+   - Added config Macro for disabling Rx SDIO aggregation. This is enabled by default.
+
+  - Bug Fixes:
+   - Fixed CH 144 connection issue.
+
+version 1.3.r33.p2
+  - New Additions:
+   - Updated RB3+(8978) SoC firmware to p214.
+   - Updated CA2(8987) SoC firmware to p200.
+
+  - Bug Fixes:
+  - Fixed an issue where, wifi connection was failing during BLE activity.
+  - Fixed an issue where a2dp profile app could not find a2dp sink device.
+
+
+version 1.3.r32.p5
+  - New Additions:
+   - Updated RB3+(8978) SoC firmware to p198.
+   - Updated CA2(8987) SoC firmware to p199.
+
+  - Bug Fixes:
+   - Fixed an issue where BT pairing auth failure was observed between two 8987
+   or two IW416 devices due to same DH Public Key being generated.
+
+version 1.3.r32.p4
+  - New Additions:
+   - Updated RB3+(8978) SoC firmware to p197.
+
+  - Bug Fixes:
+   - Fixed an issue where, in presence of WLAN, BT A2DP SNK scenario can observe continuous glitches because
+   of BT utilizing the WLAN overlapping channels.
+   - Fixed an issue where, in presence of BT A2DP SRC scenario and WLAN traffic, both will share air-time.
+   WLAN Rx TP can drop to 15-20% of its baseline because of A2DP occupying more air-time duty cycle.
+
+version 1.3.r32.p3
+  - New Additions:
+   - Updated RB3+(8978) SoC firmware to p196.
+   - Updated CA2(8987) SoC firmware to p162.
+   - Updated RB3(8977) SoC firmware to p186.
+   - Updated Falcon(8801) SoC firmware to p191.
+
+  - Bug Fixes:
+   - Fixed an issue where STAUT was not advertising extended capabilities in assoc request
+   - Fixed an issue where cal data download API is not setting the cal data
+   correctly.
+   - Fixed an issue where Ping of 10000 bytes is not workingfor WMM case with 11n/11ac pre-cert WFA testbed AP's.
+   - VU FFD(vulnerability) fixes have been made for CA2(8987)/RB3+(8978)/RB3(8977)/Falcon(8801).
+
+version 1.3.r31.p1
+  - New Additions:
+   - Updated RB3+(8978) SoC firmware to p152.
+   - Updated CA2(8987) SoC firmware to p152.
+   - Added WMM feature for 8987 SoC
+  -Updates
+   - Enabled wifi deep sleep and IEEEPS modes as part of CLI initialisation.
+   - Updated module macro for CA2 from WIFI_BOARD_AW_CM358MA to WIFI_BOARD_AW_CM358.
+  - Bug Fixes:
+   - Fixed deepsleep error when called immediately after disconnection
+   - Fixed an issue where uAP was not turned on when country is specified using wlan_set_country API.
+
+version 1.3.r30.p2
+  - New Additions:
+   - Updated 8978 SoC firmware to p185.
+   - Updated 8987 SoC firmware to p185.
+  - Bug Fixes:
+   - Fixed a regression issue in WiFi FW where Ex-client is not able to associate with uAP on 8978 and 8987 SoC.
+
+version 1.3.r30.p1
+  - New Additions:
+   - Updated RB3+(8978) SoC firmware to p145.
+   - Updated CA2(8987) SoC firmware to p145.
+  - Bug Fixes:
+   - Fixed MISRA C-2012 Rule 14.4 issues.
+   - Updated TX Power configuration table for uAP.
+   - Fixed an issue where in MFG mode measured TX power value for 2.4GHz is 10.97dBm
+     and for 5GHz is 12.03dBm always irrespective of TX-power values configured in CA2.
+   - Fixed an issue where in control frames measured TX power is less than configured
+     Tx power by 3dBm for 5Ghz 40Mhz BW and ~7dBm for 5Ghz 80Mhz BW in CA2.
+
+version 1.3.r29.p2
+  - New Additions:
+   - Updated 8987 SoC firmware to p142.
+   - Updated 8978 SoC firmware to p142.
+  - Bug Fixes:
+   - Fixed MISRA C-2012 Directive 4.7, Directive 4.10, Rule 15.7 and Rule 14.4 issues
+   - Fixed wlan_get_sta_tx_power() API implementation for retrieving station tx power level.
+   - Fixed wlan-set/get-txpwrlimit CLI command for setting/getting TX power
+   limit for 11AC modulation groups in 8987.
+   - Fixed an issue where in MFG mode(rf_test_mode=1) after disabling
+   wlan_set_rf_cont_mode(CMD18_CW=1) command response timeout is seen in 8987.
+
+version 1.3.r29.p1
+  - New Additions:
+   - Added support for 8987 SoC with p141 firmware version.
+   - Updated 8978 SoC firmware to p141.
+  - Bug Fixes:
+   - Fixed Misra C-2012 required category issues for Rule 17.7.
+   - Fixes for BCA-TDM in Co-Ex for 8978 SoC.
+   - Fixed A2DP glitches in BT when WLAN connected for 8978 SoC.
+
+version 1.3.r27.p2
+  - New Additions:
+   - Updated FW versions to p130 for 8978.
+
+version 1.3.r27.p1
+
+  - Bug Fixes:
+   - Fixed PMF pre-cert issue where STAUT is not associating to PSK-SHA-256 enabled AP.
+   - Fixed 11N pre-cert issue where 11N-5.2.47 STAUT AMPDU TX test case is failing.
+
+version 1.3.r26.p2
+
+  - New Additions:
+   - Updated FW versions to p184 for 8977 and p122 FW for 8978.
+   - Added wifi_cert application under wifi_examples.
+
+  - Bug Fixes:
+   - Fixed an issue where connection problem is seen with uAP in wifi_webconfig after removing stored credentials.
+   - Fixed RF Test Mode issue for setting data rate in uAP mode.
+   - Fixed Coverity and MISRA issues in WiFi Driver.
+   - Fixed WPA3 SAE pre-cert requirement where there was requirement of Auth confirm to be initiated by either STA or Ex-AP.
+   - Removed following API's from WiFi driver as they were not supported:
+     - wifi_auto_reconnect_enable()
+     - wifi_auto_reconnect_disable()
+     - wifi_get_auto_reconnect_config()
+     - wifi_get_tbtt_offset()
+     - wifi_set_packet_filters()
+     - wifi_set_auto_arp()
+     - wifi_tcp_keep_alive()
+     - wifi_nat_keep_alive()
+
+version 1.3.r23.p2
+
+  - New Additions:
+   - Minor update to wifi_test_mode CLIs for better usability.
+   - Added bug fixes in WiFi FW and updated FW versions to p155 for 8801, p182 for 8977 and p106 for 8978.
+   - Added new wlan_uap_set_htcapinfo() API for setting HT Capability field for uAP.
+
+  - Bug Fixes:
+   - Fixed RF Test Mode issues for SD8801 and SD8977 reported by QA.
+   - Fixed WiFi 802.11n WPA3 SAE pre-cert test failures for SD8978.
+   - Fixed stack overflow issue with WLCMGR thread during wlan-connect.
+   - Fixed memory corruption issue cause by scan list overflow when using 11D.
+
+version 1.3.r21.p1
+
+  - New Additions:
+   - Added support for SD8978.
+   - Added Test Mode support for 8801, 8977 and 8978.
+   - Added new FW binaries for 8801, 8977 and 8978.
+   - Added OTP Force Region support in WiFi Driver.
+   - Added support for DHCP Server CLI to print IP addresses of connected clients to uAP.
+   - Added support to set HT Capability field for uAP.
+   - Added wlan_get_chanlist API and CLI.
+   - Added WiFi Driver task priority configurability option.
+   - Reduced WiFi Driver SRAM footprint.
+   - Added support in Wi-Fi driver to print debug events from WLAN FW.
+   - Added support for FW Dump generation using a micro-USB mass storage device.
+
+  - Bug Fixes:
+   - Fixed an issue where a redundant Link Loss disconnect timer was defined in the wifi_iperf app.
+   - Fixed an issue where sometimes the wlan_disconnect call did not abort an ongoing re-association.
+   - Fixed an issue where station connection to an Open security Ext-AP fails after connection to a WPA3-SAE Ext-AP.
+   - Fixed an issue where uAP did not start with WPA3-SAE security type.
+
+  - Known Issues
+   - Wi-Fi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r20.p1
+
+  - New Additions:
+   - Added new FW for 8801.
+
+  - Bug Fixes:
+   - Fixed an issue where STAUT went to hang state when doing a disconnect in the wifi_iperf app.
+   - Fixed an issue where STAUT failed to reassociate with an Ext-AP after band switch.
+   - Fixed an issue where Scan command timeout was observed after changing the ssid of Ext-AP to which STAUT is connected.
+
+  - Known Issues
+   - Wi-Fi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r19.p1
+
+  - New Additions:
+   - Added new FW for 8801.
+   - Updated WiFi API reference manual.
+
+  - Bug Fixes:
+   - Fixed an issue where STAUT attempted to connect with Ext-AP continuously even when an Auth Failure occured due to incorect passphrase.
+   - Fixed an issue where SDIO write error occured sometimes for some packet sizes during Tx.
+   - Fixed an issue where packet leakage was noticed on SD8801 when noise was applied.
+   - Fixed an issue to supress Association Failed warning generated during a connection attempt.
+
+  - Known Issues
+   - Wi-Fi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r18.p1
+
+  - New Additions:
+   - Added new FW for 8977.
+
+  - Bug Fixes:
+   - Fixed an issue where STAUT fails to scan after Channel Switch and STAUT moves to new channel after eCSA IE.
+   - Fixed IAR, MDK build compilation warnings.
+
+  - Known Issues
+   - Wi-Fi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r17.p1
+
+  - New Additions:
+   - Added new FW for 8977.
+   - Added CLI command to get a list of stations connected to uAP.
+
+  - Bug Fixes:
+   - Fixed an issue where Scan was temporarily aborted due to noise but correct status was not being returned to the host.
+   - Fixed an issue where STAUT failed to connect with an AP with hidden SSID.
+   - Fixed IAR, MDK build compilation warnings.
+   - Fixed an issue where TCP bi-directional throughput stops abruptly for SD8801 and STAUT is disconnected.
+   - Fixed an issue where UDP Dual Mode throughput stops abruptly and disconnection is seen.
+   - Fixed an issue where Tx got stuck after removal of interference noise.
+
+  - Known Issues
+   - Wi-Fi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r16.p1
+
+  - New Additions:
+   - Added PMF Configuration for uAP.
+   - Updated WLAN Versioning.
+   - Updated WLAN CLIs.
+
+  - Bug Fixes:
+   - Fixed an issue where the STAUT sometimes did not send aggregated packets during Tx.
+   - Fixed an issue External Client could not associate with the UAP in WPA3-SAE mode.
+   - Fixed IAR build compilation warnings.
+   - Fixed an issue where the STAUT failed to associate with an AP with hidden SSID.
+   - Fixed an issue where active scan probe requests were sent for DFS channels.
+   - Fixed an issue where 2.4GHz-HT40 power values were exposed via CLI configuration.
+   - Fixed an issue where the STAUT will be continuously in re-association mode after link-loss.
+
+  - Known Issues
+   - Wi-Fi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r15.p1
+
+  - New Additions
+   - Added support for Tx Power Limit configuration.
+   - Added support for Channel List configuration.
+   - Added support for CW MODE.
+   - Added support for sysinfo CLI to get threads information, network stats, wlan stats and heap stats.
+   - Added -d and -r options to iperf CLI for dual and trade-off mode.
+   - Added support for antenna configuration for 8801.
+   - Added support for band configuration.
+   - Added new FW for 8977
+
+  - Bug Fixes:
+   - Fixed an issue where UDP Rx data rate was low in iperf dual mode operation.
+   - Fixed an issue where STAUT traffic was getting halted when there is traffic in overlapping BSS on the extension channel.
+   - Fixed an issue where STAUT was not able to transmit above MCS 4.
+   - Fixed an issue where association with uAP failed with WPA2 security mode.
+   - Fixed an issue where STAUT failed to connect to WPA3 AP due to PMF config mismatch.
+   - Fixed an issue where ping loss was observed for packets of size greater than 10000 bytes.
+   - Fixed an issue in CLI where CR and LF characters where not handled properly.
+   - Fixed an issue where TCP-Tx traffic abruptly stops when parallel traffic is ongoing on another device using the same AP.
+   - Fixed an issue where DUT goes into hang state when iperf run is aborted.
+   - Fixed an issue where the STATU was not sending aggregated packets to the AP.
+   - Fixed an issue where UAP did not start with WPA2 security mode when ACS is configured.
+   - Fixed an issue where ED MAC was not enabled by default.
+
+  - Known Issues
+   - WiFi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r14.p1
+
+  - New Additions
+   - Added support for Panasonic PAN9026 module.
+   - Added -t option in iperf CLI for setting traffic running time.
+   - Added -B option for supporting Tx/Rx Multicast packets during iperf runs.
+   - Added World Wide Safe Mode configurability to the WiFi Driver.
+   - Added ED MAC support for 8977.
+   - Added support for PMF APIs and CLIs.
+   - Added new FW for 8977 and 8801.
+
+  - Bug Fixes:
+   - Fixed Coverity and mandatory MISRA issues reported on v1.3.r13.p1 release.
+   - Fixed an isuue where DUT console was getting stuck after intiating connection with an AP which has different RSN values than expected.
+   - Fixed an issue where DUT was not able to roam from SAE-PSK to PSK configured AP.
+   - Fixed an issue where the app became unresponsive after Soft AP is stopped.
+   - Removed unnecessary files after Blackduck scan.
+
+  - Known Issues
+   - WiFi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r1r3.p1
+
+  - New Additions
+    - Updated WiFi Driver to be independednt of the LwIP stack. Only the WLAN Connection Manager now uses LwIP.
+    - Added WiFi Roaming feature.
+    - Added CLI support for iperf in wifi_cli app.
+    - Added support for CSA handling from wlan station side.
+    - Added WLAN APIs for wlan-set-txratecfg, wlan-get-txratecfg, wlan-get-data-rate, wlan-set-reg and wlan-get-reg.
+    - Updated External AP SSID required for wifi_iperf app.
+  - Bug Fixes:
+    - Fixed Coverity issues reported on v1.3.r12.p1 release.
+    - Added a fix for ping loss observed during ping test.
+    - Added a fix where the console became unresponsive after wlan-start-network+wlan-stop-network commands are executed in loop.
+    - Added a fix for HT IE missing from beacon for both 2.4GHz and 5GHZ bands.
+    - Fixed warnings reported for IAR.
+    - Added a fix for increasing DHCP leave time to 24 hrs for long duration stress tests.
+  - Known Issues
+    - WiFi sample apps do not work with Rev-C (2018) version of RT685 board
+
+version 1.3.r12.p1
+
+  - New Additions
+    - Added support for ping utility.
+  - Bug Fixes
+    - Restart of SoftAP fails once SoftAP is stopped.
+    - HT IE is missing from beacon for both 2.4GHz and 5GHZ bands.
+    - Low TCP-Rx and UDP-Rx throughput observed for 5GHz-HT40 band.
+    - uAP couldn't be started after STA is associated to Ex-AP.
+    - Stopping SoftAP results in disconnection of In-STA from Ex-AP.
+    - DHCP server is not started for BSS created using "wlan-add" command.
+  - Known Issues
+    - N.A
+
+version 1.3.r11.p2
+
+  - New Additions
+    - Updated SDK version for RT1060 to 2.7.1 RFP RC2.
+    - Added FP91 based WiFi FW for SD8801, SD8977, SD8978, and SD8987.
+    - SD8801, SD8977, SD8978 and SD8987 WiFi Fw have embedded WPA3 SAE support
+      from version v1.3.r11.p1 onwards.
+    - Added WLAN CLI support. Added new wifi_cli for CLI demo.
+  - Enhancements
+    - License and Copyright Updates.
+    - Formated code base with clang-format 10.0.0 standards.
+    - Integrated PICK utility for WiFi Driver code scrubbing.
+  - Bug Fixes
+    - Removed unnecessary prints LwIP stats display.
+    - Fixed an issue where uAP did not start on 5GHz band.
+    - Fixed an issue where loww TCP/UDP-Rx throughput was observed for 5GHz-HT40Mhz.
+  - Known Issues
+    - N.A
+
+version 1.3.r10.p1
+
+  - New Additions
+    - Moved to using LwIP provided IPerf App.
+    - Added SDIO Rx Aggregation support to improve throughput.
+    - Added support for 11ac configuration API.
+    - Updated License and Copyright information on all WiFi driver files and sample apps.
+    - Moved MCUXpresso SDK base for RT1060 platform from 2.6.2 to 2.7.0 rc3.
+  - Known Issues
+    - N.A
+
+version 1.3.r9.p1
+
+  - New Additions
+    - Achieved additional TP improvements by updating LwIP parameters.
+  - Bug Fixes
+    - Fixed the issue of low throughput for both TCP and UDP (Tx/Rx) by updating LwIP parameters.
+    - TCP Throughput was observed to be lower than UDP throughput by 70%-80%. Fixed this issue by updating TCP related LwIP configurations.
+  - Known Issues
+    - N.A
+
+*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/ca-cert.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/ca-cert.h
new file mode 100644
index 0000000000..43423424a0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/ca-cert.h
@@ -0,0 +1,65 @@
+const unsigned char ca_der[] = {
+    0x30, 0x82, 0x04, 0xa1, 0x30, 0x82, 0x03, 0x09, 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x14, 0x39, 0x27, 0xf3, 0x9b,
+    0x20, 0x1e, 0xa5, 0xe3, 0xda, 0xdb, 0x44, 0x64, 0x0d, 0x71, 0x24, 0xb6, 0x8a, 0x94, 0x33, 0x64, 0x30, 0x0d, 0x06,
+    0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30, 0x5f, 0x31, 0x0b, 0x30, 0x09, 0x06,
+    0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x49, 0x4e, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02,
+    0x4d, 0x48, 0x31, 0x0d, 0x30, 0x0b, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0c, 0x04, 0x50, 0x55, 0x4e, 0x45, 0x31, 0x0c,
+    0x30, 0x0a, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x03, 0x4e, 0x58, 0x50, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55,
+    0x04, 0x03, 0x0c, 0x02, 0x43, 0x41, 0x31, 0x19, 0x30, 0x17, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01,
+    0x09, 0x01, 0x16, 0x0a, 0x63, 0x61, 0x40, 0x6e, 0x78, 0x70, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x20, 0x17, 0x0d, 0x32,
+    0x33, 0x30, 0x33, 0x31, 0x35, 0x31, 0x34, 0x32, 0x33, 0x31, 0x33, 0x5a, 0x18, 0x0f, 0x33, 0x30, 0x32, 0x32, 0x30,
+    0x37, 0x31, 0x36, 0x31, 0x34, 0x32, 0x33, 0x31, 0x33, 0x5a, 0x30, 0x5f, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55,
+    0x04, 0x06, 0x13, 0x02, 0x49, 0x4e, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02, 0x4d, 0x48,
+    0x31, 0x0d, 0x30, 0x0b, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0c, 0x04, 0x50, 0x55, 0x4e, 0x45, 0x31, 0x0c, 0x30, 0x0a,
+    0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x03, 0x4e, 0x58, 0x50, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x03,
+    0x0c, 0x02, 0x43, 0x41, 0x31, 0x19, 0x30, 0x17, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x09, 0x01,
+    0x16, 0x0a, 0x63, 0x61, 0x40, 0x6e, 0x78, 0x70, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x82, 0x01, 0xa2, 0x30, 0x0d, 0x06,
+    0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x01, 0x05, 0x00, 0x03, 0x82, 0x01, 0x8f, 0x00, 0x30, 0x82,
+    0x01, 0x8a, 0x02, 0x82, 0x01, 0x81, 0x00, 0xdd, 0x70, 0x03, 0x4e, 0xb4, 0x53, 0xdf, 0x45, 0xfb, 0xf2, 0x9f, 0x74,
+    0x0b, 0x1e, 0x53, 0x0e, 0x98, 0x30, 0x5b, 0x68, 0x26, 0x8f, 0x59, 0xba, 0xfc, 0x3c, 0xd6, 0x80, 0x33, 0xd4, 0xf1,
+    0x16, 0x44, 0x42, 0xc7, 0x7e, 0x77, 0xfe, 0x0b, 0xae, 0x92, 0x50, 0x4c, 0x3b, 0xeb, 0x3f, 0x28, 0x53, 0x4d, 0xa0,
+    0x58, 0xad, 0xd9, 0x88, 0x4a, 0xd8, 0xac, 0x52, 0xfb, 0x35, 0x5a, 0x34, 0x07, 0xb9, 0x14, 0xd4, 0x0f, 0x3d, 0xa5,
+    0x7a, 0xa8, 0x44, 0x17, 0x9c, 0x97, 0xb6, 0x7f, 0x0e, 0x7a, 0x05, 0x33, 0x65, 0x58, 0x42, 0xf0, 0x61, 0xd8, 0x20,
+    0x1f, 0xaa, 0xc6, 0xdc, 0xcf, 0x6b, 0x50, 0xb5, 0x13, 0x55, 0x19, 0x3f, 0x57, 0x6d, 0x15, 0x8f, 0x33, 0xe9, 0x86,
+    0x98, 0x85, 0xdf, 0xb3, 0x72, 0x4b, 0x8b, 0xa1, 0xe3, 0xa9, 0xa5, 0x43, 0x84, 0xcd, 0x61, 0x6a, 0x61, 0xbc, 0x1a,
+    0xb9, 0xd6, 0x57, 0xaa, 0x53, 0x4e, 0xa3, 0x1c, 0x8a, 0xab, 0x81, 0x40, 0x84, 0xaa, 0x11, 0x55, 0xcf, 0x37, 0xb4,
+    0x69, 0xe5, 0x65, 0x59, 0x27, 0x74, 0x78, 0xfb, 0xa3, 0xf0, 0x1a, 0xa1, 0xdd, 0xaf, 0xd7, 0x5e, 0x65, 0x72, 0x99,
+    0x1b, 0x40, 0x44, 0x99, 0x9f, 0x67, 0x30, 0x5f, 0x12, 0x3c, 0xb7, 0x6a, 0x03, 0xe3, 0x35, 0x10, 0xc2, 0x02, 0x80,
+    0x66, 0x80, 0xc2, 0xa6, 0x50, 0x9a, 0x9a, 0xa1, 0xa1, 0xf3, 0xc4, 0x06, 0x3b, 0x87, 0x3f, 0xb3, 0x0a, 0x52, 0x4d,
+    0xb7, 0x3c, 0x8b, 0x8d, 0x17, 0x23, 0x4f, 0x4c, 0x27, 0x7d, 0x1c, 0xb2, 0xb2, 0x6c, 0x19, 0x0c, 0xef, 0x6c, 0xf2,
+    0x2a, 0xfc, 0x6a, 0x98, 0xb4, 0x7f, 0x46, 0xa2, 0xf2, 0xf1, 0x36, 0x46, 0xbf, 0x40, 0x06, 0x47, 0xf3, 0xdd, 0xa7,
+    0xe7, 0xe4, 0xef, 0xd3, 0x1e, 0xc5, 0x01, 0xb1, 0xb0, 0x1a, 0x8b, 0x86, 0x06, 0x5f, 0x66, 0xc4, 0x3a, 0xa5, 0x49,
+    0x09, 0xaa, 0xf6, 0x64, 0x51, 0x41, 0x14, 0x8a, 0x7b, 0x9c, 0x06, 0xfa, 0xff, 0x06, 0xa0, 0xf2, 0x12, 0xa9, 0xef,
+    0x14, 0x2d, 0xd3, 0x6e, 0xee, 0x0f, 0x35, 0x10, 0xb0, 0x7a, 0x1b, 0xbb, 0x58, 0x44, 0xe8, 0x18, 0x5c, 0xc0, 0x26,
+    0x1c, 0xfb, 0xc3, 0x80, 0x97, 0xc1, 0xae, 0x56, 0x44, 0xd1, 0x5e, 0xd8, 0xe1, 0x66, 0xfd, 0x43, 0xea, 0x3e, 0x1f,
+    0x88, 0x00, 0x73, 0xb1, 0x05, 0xd5, 0xbb, 0x70, 0xe6, 0xea, 0xab, 0x6a, 0x63, 0xe7, 0xa2, 0x3b, 0xad, 0x50, 0xe0,
+    0xc8, 0x79, 0x22, 0x71, 0x8d, 0x31, 0x5c, 0x7d, 0xf6, 0xea, 0x0b, 0x92, 0x7a, 0x1d, 0x46, 0xde, 0xf7, 0x33, 0x4d,
+    0xca, 0xb0, 0xa4, 0x81, 0x1b, 0xd8, 0xd3, 0xf1, 0x8d, 0xa7, 0xc1, 0xe2, 0x84, 0x24, 0x31, 0x19, 0x71, 0x8c, 0xe6,
+    0xfe, 0x5d, 0xdb, 0xcd, 0x8b, 0xae, 0xa3, 0x25, 0xdd, 0x2d, 0x07, 0x02, 0x03, 0x01, 0x00, 0x01, 0xa3, 0x53, 0x30,
+    0x51, 0x30, 0x1d, 0x06, 0x03, 0x55, 0x1d, 0x0e, 0x04, 0x16, 0x04, 0x14, 0xc5, 0x31, 0x78, 0x1d, 0x4a, 0xde, 0xf0,
+    0x95, 0x0c, 0xdd, 0xd2, 0x21, 0x41, 0x2c, 0x8c, 0xfa, 0xc8, 0x20, 0x2d, 0xb1, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d,
+    0x23, 0x04, 0x18, 0x30, 0x16, 0x80, 0x14, 0xc5, 0x31, 0x78, 0x1d, 0x4a, 0xde, 0xf0, 0x95, 0x0c, 0xdd, 0xd2, 0x21,
+    0x41, 0x2c, 0x8c, 0xfa, 0xc8, 0x20, 0x2d, 0xb1, 0x30, 0x0f, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x01, 0x01, 0xff, 0x04,
+    0x05, 0x30, 0x03, 0x01, 0x01, 0xff, 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b,
+    0x05, 0x00, 0x03, 0x82, 0x01, 0x81, 0x00, 0xb1, 0x1b, 0x2b, 0xdc, 0xf0, 0x60, 0x19, 0xa8, 0x83, 0xb9, 0x10, 0xc3,
+    0x69, 0x40, 0x52, 0x09, 0x14, 0x41, 0x85, 0x5c, 0x07, 0x73, 0xbc, 0x0f, 0x19, 0xae, 0xcd, 0x40, 0xb2, 0x88, 0x60,
+    0x12, 0x15, 0x49, 0x8a, 0x37, 0x82, 0xb5, 0x66, 0xa6, 0xea, 0x3e, 0x94, 0xe0, 0x17, 0x64, 0x1d, 0x9f, 0x40, 0x49,
+    0x03, 0x8e, 0x0b, 0x0d, 0x4e, 0x16, 0xdf, 0x3d, 0x0d, 0x1d, 0x79, 0xe5, 0xaf, 0xd0, 0x20, 0x48, 0xe2, 0x4b, 0x07,
+    0xc1, 0x3a, 0x23, 0x10, 0x21, 0xc2, 0x72, 0xe1, 0xb4, 0xd6, 0x78, 0xd8, 0xe5, 0xa9, 0xa8, 0x34, 0x2c, 0x74, 0x70,
+    0x09, 0x30, 0xb7, 0xbe, 0xde, 0x3e, 0x25, 0x02, 0x74, 0xfc, 0xe4, 0x1c, 0xfa, 0xb9, 0xa7, 0x70, 0x94, 0xfa, 0x52,
+    0x5f, 0x32, 0x73, 0x93, 0x1b, 0x1c, 0x11, 0xb4, 0xc6, 0x7a, 0xd9, 0x72, 0x18, 0xf5, 0x74, 0x06, 0xce, 0xb6, 0xb1,
+    0x0f, 0x5c, 0x45, 0x21, 0xca, 0x52, 0xda, 0x14, 0x50, 0x8a, 0x1a, 0x30, 0xbd, 0xd3, 0xed, 0x13, 0x10, 0x5c, 0x94,
+    0x93, 0xb0, 0x45, 0x46, 0x31, 0xbb, 0xb1, 0x61, 0xc8, 0xa9, 0xad, 0x91, 0xee, 0xe1, 0xea, 0xeb, 0x1f, 0x8e, 0x67,
+    0x22, 0xc4, 0x3a, 0x54, 0xd8, 0x52, 0xeb, 0xde, 0xcf, 0x6d, 0x72, 0x31, 0xaf, 0x75, 0x8c, 0xd2, 0x2c, 0xa8, 0x72,
+    0x8d, 0x1a, 0x35, 0x53, 0x4b, 0x10, 0x98, 0xc7, 0xd8, 0x3d, 0x59, 0x18, 0x24, 0xdf, 0x57, 0xe6, 0x31, 0x91, 0x55,
+    0x17, 0x2e, 0x40, 0x1d, 0x82, 0x34, 0xa6, 0x2d, 0x99, 0x23, 0x73, 0xd6, 0x1c, 0x2b, 0x66, 0xe2, 0x50, 0x18, 0xc2,
+    0x9d, 0x85, 0x32, 0x12, 0xac, 0x7e, 0x41, 0x76, 0x33, 0x39, 0x5b, 0x6d, 0x22, 0xd4, 0x0b, 0xb0, 0xc2, 0x26, 0x53,
+    0x72, 0x2c, 0x18, 0xbf, 0x45, 0x13, 0x8f, 0xce, 0xc8, 0x28, 0x3c, 0x6d, 0x13, 0x83, 0x02, 0x79, 0xe0, 0x38, 0xb7,
+    0x14, 0x74, 0x1e, 0xab, 0xc8, 0x9d, 0xad, 0xe2, 0x64, 0xae, 0x4f, 0x16, 0xd6, 0x60, 0xa1, 0x0d, 0x90, 0x11, 0xce,
+    0x9b, 0x9b, 0x51, 0xe0, 0xba, 0x7c, 0xa2, 0xb5, 0xfd, 0xa4, 0x40, 0x7f, 0xee, 0xaa, 0x5f, 0xf1, 0xbd, 0xf8, 0x04,
+    0x8f, 0x5a, 0x82, 0x50, 0x80, 0xf5, 0x27, 0x18, 0x8d, 0x37, 0x86, 0x35, 0xb5, 0xf2, 0xfa, 0x18, 0x71, 0x82, 0x24,
+    0x9a, 0xdd, 0x37, 0x1e, 0xf1, 0xee, 0xd8, 0xd2, 0x16, 0xf4, 0x93, 0xa7, 0x35, 0x46, 0xa0, 0x54, 0x1c, 0x3b, 0x7d,
+    0x77, 0x48, 0x4e, 0x76, 0x46, 0x27, 0x2d, 0x83, 0x40, 0x76, 0x66, 0x1b, 0x3c, 0x7b, 0x57, 0x68, 0x2d, 0x9d, 0x21,
+    0xa4, 0x70, 0xf5, 0xff, 0x58, 0xce, 0x3c, 0xf3, 0xc9, 0x67, 0x8c, 0x9d, 0x5a, 0x9c, 0xa0, 0x02, 0xf3, 0x0c, 0x44,
+    0x65, 0x1b, 0xe3, 0x51, 0x79, 0xcd, 0xf7, 0xb6, 0x66, 0xb3, 0x9d};
+unsigned int ca_der_len = 1189;
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/client-cert.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/client-cert.h
new file mode 100644
index 0000000000..9b93dadd23
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/client-cert.h
@@ -0,0 +1,60 @@
+const unsigned char client_der[] = {
+    0x30, 0x82, 0x04, 0x3c, 0x30, 0x82, 0x02, 0xa4, 0x02, 0x01, 0x01, 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86,
+    0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30, 0x5f, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13,
+    0x02, 0x49, 0x4e, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02, 0x4d, 0x48, 0x31, 0x0d, 0x30,
+    0x0b, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0c, 0x04, 0x50, 0x55, 0x4e, 0x45, 0x31, 0x0c, 0x30, 0x0a, 0x06, 0x03, 0x55,
+    0x04, 0x0a, 0x0c, 0x03, 0x4e, 0x58, 0x50, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x02, 0x43,
+    0x41, 0x31, 0x19, 0x30, 0x17, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x09, 0x01, 0x16, 0x0a, 0x63,
+    0x61, 0x40, 0x6e, 0x78, 0x70, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x20, 0x17, 0x0d, 0x32, 0x33, 0x30, 0x33, 0x31, 0x35,
+    0x31, 0x34, 0x32, 0x36, 0x32, 0x31, 0x5a, 0x18, 0x0f, 0x33, 0x30, 0x32, 0x32, 0x30, 0x37, 0x31, 0x36, 0x31, 0x34,
+    0x32, 0x36, 0x32, 0x31, 0x5a, 0x30, 0x67, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x49,
+    0x4e, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02, 0x4d, 0x48, 0x31, 0x0d, 0x30, 0x0b, 0x06,
+    0x03, 0x55, 0x04, 0x07, 0x0c, 0x04, 0x50, 0x55, 0x4e, 0x45, 0x31, 0x0c, 0x30, 0x0a, 0x06, 0x03, 0x55, 0x04, 0x0a,
+    0x0c, 0x03, 0x4e, 0x58, 0x50, 0x31, 0x0f, 0x30, 0x0d, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x06, 0x43, 0x6c, 0x69,
+    0x65, 0x6e, 0x74, 0x31, 0x1d, 0x30, 0x1b, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x09, 0x01, 0x16,
+    0x0e, 0x63, 0x6c, 0x69, 0x65, 0x6e, 0x74, 0x40, 0x6e, 0x78, 0x70, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x82, 0x01, 0xa2,
+    0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x01, 0x05, 0x00, 0x03, 0x82, 0x01, 0x8f,
+    0x00, 0x30, 0x82, 0x01, 0x8a, 0x02, 0x82, 0x01, 0x81, 0x00, 0xd6, 0xd8, 0x4e, 0x1a, 0xc7, 0x51, 0x89, 0x3c, 0x6e,
+    0xd5, 0xf7, 0xc2, 0x44, 0xbd, 0x8d, 0x53, 0x6a, 0x01, 0xc4, 0x6b, 0x1d, 0xe3, 0xae, 0xbd, 0x83, 0x34, 0x92, 0x31,
+    0x89, 0xe3, 0x65, 0x63, 0x25, 0xf3, 0xe8, 0x38, 0x37, 0xcd, 0xae, 0x13, 0xac, 0xe3, 0x61, 0xa8, 0x4f, 0x1a, 0xa0,
+    0x61, 0xb0, 0x54, 0x19, 0x39, 0x4c, 0xd5, 0xb2, 0x99, 0xaa, 0x2c, 0x15, 0xe5, 0x7e, 0x61, 0xec, 0xe9, 0x2f, 0x1e,
+    0xd1, 0x89, 0x91, 0x90, 0x08, 0x08, 0x51, 0xc7, 0x8a, 0x9f, 0xa2, 0xf0, 0xa8, 0x69, 0x8e, 0xf7, 0xda, 0x7e, 0x69,
+    0xb4, 0x28, 0xf8, 0x83, 0x81, 0x6d, 0x96, 0x6d, 0xb2, 0x88, 0x98, 0xa3, 0x1f, 0x2f, 0xe3, 0x09, 0x3a, 0x5e, 0xe1,
+    0x0a, 0xfc, 0xba, 0xd5, 0x98, 0x0a, 0x1d, 0x66, 0x1f, 0xeb, 0x8d, 0x9b, 0x6a, 0x7a, 0xd9, 0x43, 0x29, 0x8c, 0xd9,
+    0xbd, 0x6e, 0x97, 0xde, 0x84, 0x8b, 0xe0, 0x9c, 0x36, 0x21, 0xd8, 0x22, 0xa1, 0xbf, 0xcc, 0x01, 0x53, 0x53, 0x31,
+    0x36, 0x97, 0xaa, 0xfe, 0x53, 0x88, 0x14, 0xc9, 0xac, 0xbb, 0x03, 0x4d, 0x74, 0x48, 0x8d, 0x47, 0x5b, 0xbe, 0x41,
+    0xc0, 0xd2, 0x70, 0x2a, 0xc0, 0x41, 0x2d, 0xa8, 0x1a, 0xd8, 0xa5, 0x88, 0xd1, 0x5e, 0x07, 0x33, 0x40, 0x00, 0xaa,
+    0xe4, 0xc3, 0xd1, 0xb5, 0x57, 0x22, 0x1c, 0xfc, 0xc8, 0x84, 0x23, 0xab, 0xe2, 0x27, 0x2d, 0x40, 0xa8, 0x1e, 0x39,
+    0xf3, 0x58, 0xd3, 0x6a, 0x62, 0x55, 0x6d, 0x46, 0x53, 0xf9, 0xad, 0x5a, 0xa4, 0xf5, 0xba, 0x5c, 0xb8, 0x95, 0xc8,
+    0x32, 0xef, 0x8e, 0x77, 0x50, 0x58, 0x71, 0xc8, 0xaf, 0x5b, 0xc2, 0x8c, 0x37, 0x46, 0xeb, 0x75, 0xbc, 0x96, 0x89,
+    0x12, 0x86, 0xe8, 0x5c, 0x9e, 0x34, 0x42, 0xed, 0xbc, 0xf6, 0x72, 0x69, 0x28, 0xa5, 0xbd, 0x36, 0x9c, 0xe2, 0x67,
+    0xf1, 0x09, 0x4f, 0xcb, 0x49, 0x96, 0x45, 0x16, 0xe4, 0xe8, 0x6a, 0x03, 0x91, 0xab, 0x77, 0x5a, 0x52, 0x49, 0x9c,
+    0xa6, 0x6a, 0x84, 0xc1, 0x7c, 0x7b, 0x68, 0x71, 0x23, 0x3d, 0x82, 0x13, 0x58, 0x1c, 0xd7, 0x75, 0x37, 0x81, 0x86,
+    0x2e, 0xfb, 0x74, 0x66, 0xfb, 0xcf, 0xfe, 0xab, 0x57, 0x1c, 0xe0, 0x02, 0x95, 0x4c, 0x54, 0x7d, 0x31, 0xf7, 0xb7,
+    0x3f, 0xe2, 0xb8, 0xf0, 0xe6, 0x90, 0x68, 0x8d, 0x81, 0x9b, 0xdd, 0xad, 0x25, 0x8d, 0x53, 0x5b, 0x6e, 0xbe, 0x87,
+    0x61, 0x62, 0x10, 0xe6, 0x2b, 0x2e, 0x14, 0xa6, 0x1b, 0x0c, 0x5a, 0xca, 0xe1, 0x32, 0xb1, 0xf9, 0xd6, 0x0b, 0xb2,
+    0xfb, 0xc4, 0xf4, 0xe8, 0xf9, 0x86, 0xae, 0x9c, 0x8c, 0x37, 0x07, 0x96, 0x59, 0x87, 0xdf, 0x2d, 0xd4, 0x05, 0x97,
+    0x7d, 0xc2, 0x59, 0xef, 0xa9, 0x8c, 0xcd, 0x7c, 0xb6, 0xab, 0x14, 0xc7, 0x7d, 0xe3, 0x02, 0x03, 0x01, 0x00, 0x01,
+    0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x03, 0x82, 0x01, 0x81,
+    0x00, 0xc4, 0xce, 0x37, 0x39, 0x3f, 0x3e, 0x78, 0xdb, 0x9e, 0x37, 0x9c, 0x42, 0x49, 0x30, 0x65, 0xe7, 0x59, 0xd1,
+    0xd8, 0x83, 0x55, 0xf4, 0x1b, 0xb0, 0x8e, 0x43, 0xc4, 0x5c, 0x6c, 0xca, 0x95, 0x5a, 0xd9, 0x89, 0xd3, 0x4b, 0x73,
+    0x78, 0x8a, 0x3a, 0xc6, 0xe3, 0xdc, 0x67, 0x1d, 0xb6, 0xe9, 0x8e, 0x67, 0x71, 0x0a, 0xa4, 0x00, 0x79, 0x82, 0x40,
+    0x11, 0x64, 0x86, 0x4a, 0x8a, 0x8f, 0x98, 0xce, 0x2c, 0x74, 0xb5, 0x56, 0xeb, 0xfa, 0xe8, 0x83, 0x27, 0x0f, 0xec,
+    0x12, 0xcb, 0x85, 0x30, 0x9a, 0x16, 0xcc, 0x15, 0x91, 0xb5, 0x66, 0xd0, 0x58, 0xec, 0x1f, 0x55, 0x2c, 0xde, 0x17,
+    0xc1, 0x83, 0x5c, 0x50, 0x53, 0x8f, 0x64, 0x62, 0xab, 0xec, 0x2b, 0x04, 0x06, 0xeb, 0x29, 0x7e, 0x18, 0x53, 0xfa,
+    0xfd, 0x0b, 0x79, 0x73, 0x65, 0x02, 0x5b, 0x85, 0x8f, 0x8b, 0xb3, 0xd3, 0xa1, 0x1b, 0x3e, 0x4c, 0x90, 0x55, 0xd1,
+    0x38, 0x01, 0x0c, 0x76, 0xca, 0x06, 0xe3, 0xaa, 0x3e, 0x7b, 0xfc, 0x3c, 0xbe, 0x8c, 0x25, 0x5a, 0x06, 0x5f, 0x1f,
+    0x61, 0x8b, 0xab, 0x2c, 0xa4, 0xc3, 0xc7, 0x2b, 0xfa, 0x07, 0x63, 0x1c, 0xda, 0xea, 0x3f, 0x09, 0x92, 0x67, 0x40,
+    0xbb, 0x5d, 0xd5, 0xc8, 0x3d, 0xf0, 0x6b, 0xdc, 0x7d, 0x88, 0x6a, 0x42, 0xb2, 0xe4, 0xd0, 0x82, 0x69, 0xb5, 0x00,
+    0x18, 0x40, 0x3c, 0xd1, 0x2c, 0x22, 0x8d, 0xda, 0x9a, 0xdf, 0xb6, 0x79, 0x51, 0xf9, 0x73, 0xe8, 0xfd, 0xb1, 0xb4,
+    0x24, 0x3c, 0x2f, 0xfe, 0xeb, 0xb3, 0xd2, 0x0c, 0x14, 0x64, 0x9b, 0x63, 0xe9, 0xc4, 0x71, 0x8e, 0x6b, 0xac, 0x5a,
+    0xa2, 0x16, 0x18, 0xe9, 0x12, 0xec, 0xa1, 0x8c, 0x4c, 0x81, 0xd1, 0x26, 0xb3, 0xa5, 0x3d, 0x5a, 0x0f, 0xf1, 0x81,
+    0xe4, 0x2b, 0xb5, 0x9a, 0xc6, 0x83, 0x28, 0x64, 0x92, 0xfe, 0x36, 0x88, 0xab, 0x16, 0x29, 0x5a, 0x03, 0xef, 0x96,
+    0x2c, 0xb0, 0xd8, 0x16, 0x02, 0x3b, 0x5d, 0x38, 0xff, 0xed, 0xcb, 0x59, 0xdf, 0xb0, 0x9a, 0x5f, 0xae, 0xf9, 0xff,
+    0xaa, 0xd3, 0xaf, 0x7c, 0xce, 0xa2, 0xeb, 0xd0, 0xeb, 0xb4, 0x2e, 0xb8, 0x60, 0xea, 0x7f, 0xb5, 0x79, 0xb5, 0x93,
+    0x39, 0x83, 0x04, 0x2b, 0xfe, 0xab, 0xd3, 0x9b, 0x8c, 0xee, 0x32, 0x13, 0x76, 0xaa, 0xed, 0x67, 0x87, 0x0d, 0xa9,
+    0x7b, 0xe8, 0x96, 0xb3, 0x22, 0x3e, 0xf4, 0xac, 0xf8, 0xd4, 0x1e, 0xce, 0x1c, 0x73, 0x9a, 0xf4, 0x13, 0x33, 0xe6,
+    0x0f, 0x43, 0xc3, 0xe5, 0x23, 0x78, 0xeb, 0xc3, 0xe4, 0x98, 0x82, 0x46, 0x0f, 0x93, 0xb0, 0xda, 0xa5, 0xa4, 0xb8,
+    0x9b, 0x81, 0x65, 0x68, 0xf5, 0xf1, 0xae, 0xd0, 0x5c, 0x9e, 0x9d, 0x9b, 0xa8, 0x88, 0x2f, 0xdd, 0x25, 0x2b, 0xf3,
+    0xbb, 0xe0, 0xfe, 0xf8, 0xeb};
+unsigned int client_der_len = 1088;
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/client-key.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/client-key.h
new file mode 100644
index 0000000000..2c8c0b9006
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/client-key.h
@@ -0,0 +1,95 @@
+const unsigned char client_key_der[] = {
+    0x30, 0x82, 0x06, 0xe3, 0x02, 0x01, 0x00, 0x02, 0x82, 0x01, 0x81, 0x00, 0xd6, 0xd8, 0x4e, 0x1a, 0xc7, 0x51, 0x89,
+    0x3c, 0x6e, 0xd5, 0xf7, 0xc2, 0x44, 0xbd, 0x8d, 0x53, 0x6a, 0x01, 0xc4, 0x6b, 0x1d, 0xe3, 0xae, 0xbd, 0x83, 0x34,
+    0x92, 0x31, 0x89, 0xe3, 0x65, 0x63, 0x25, 0xf3, 0xe8, 0x38, 0x37, 0xcd, 0xae, 0x13, 0xac, 0xe3, 0x61, 0xa8, 0x4f,
+    0x1a, 0xa0, 0x61, 0xb0, 0x54, 0x19, 0x39, 0x4c, 0xd5, 0xb2, 0x99, 0xaa, 0x2c, 0x15, 0xe5, 0x7e, 0x61, 0xec, 0xe9,
+    0x2f, 0x1e, 0xd1, 0x89, 0x91, 0x90, 0x08, 0x08, 0x51, 0xc7, 0x8a, 0x9f, 0xa2, 0xf0, 0xa8, 0x69, 0x8e, 0xf7, 0xda,
+    0x7e, 0x69, 0xb4, 0x28, 0xf8, 0x83, 0x81, 0x6d, 0x96, 0x6d, 0xb2, 0x88, 0x98, 0xa3, 0x1f, 0x2f, 0xe3, 0x09, 0x3a,
+    0x5e, 0xe1, 0x0a, 0xfc, 0xba, 0xd5, 0x98, 0x0a, 0x1d, 0x66, 0x1f, 0xeb, 0x8d, 0x9b, 0x6a, 0x7a, 0xd9, 0x43, 0x29,
+    0x8c, 0xd9, 0xbd, 0x6e, 0x97, 0xde, 0x84, 0x8b, 0xe0, 0x9c, 0x36, 0x21, 0xd8, 0x22, 0xa1, 0xbf, 0xcc, 0x01, 0x53,
+    0x53, 0x31, 0x36, 0x97, 0xaa, 0xfe, 0x53, 0x88, 0x14, 0xc9, 0xac, 0xbb, 0x03, 0x4d, 0x74, 0x48, 0x8d, 0x47, 0x5b,
+    0xbe, 0x41, 0xc0, 0xd2, 0x70, 0x2a, 0xc0, 0x41, 0x2d, 0xa8, 0x1a, 0xd8, 0xa5, 0x88, 0xd1, 0x5e, 0x07, 0x33, 0x40,
+    0x00, 0xaa, 0xe4, 0xc3, 0xd1, 0xb5, 0x57, 0x22, 0x1c, 0xfc, 0xc8, 0x84, 0x23, 0xab, 0xe2, 0x27, 0x2d, 0x40, 0xa8,
+    0x1e, 0x39, 0xf3, 0x58, 0xd3, 0x6a, 0x62, 0x55, 0x6d, 0x46, 0x53, 0xf9, 0xad, 0x5a, 0xa4, 0xf5, 0xba, 0x5c, 0xb8,
+    0x95, 0xc8, 0x32, 0xef, 0x8e, 0x77, 0x50, 0x58, 0x71, 0xc8, 0xaf, 0x5b, 0xc2, 0x8c, 0x37, 0x46, 0xeb, 0x75, 0xbc,
+    0x96, 0x89, 0x12, 0x86, 0xe8, 0x5c, 0x9e, 0x34, 0x42, 0xed, 0xbc, 0xf6, 0x72, 0x69, 0x28, 0xa5, 0xbd, 0x36, 0x9c,
+    0xe2, 0x67, 0xf1, 0x09, 0x4f, 0xcb, 0x49, 0x96, 0x45, 0x16, 0xe4, 0xe8, 0x6a, 0x03, 0x91, 0xab, 0x77, 0x5a, 0x52,
+    0x49, 0x9c, 0xa6, 0x6a, 0x84, 0xc1, 0x7c, 0x7b, 0x68, 0x71, 0x23, 0x3d, 0x82, 0x13, 0x58, 0x1c, 0xd7, 0x75, 0x37,
+    0x81, 0x86, 0x2e, 0xfb, 0x74, 0x66, 0xfb, 0xcf, 0xfe, 0xab, 0x57, 0x1c, 0xe0, 0x02, 0x95, 0x4c, 0x54, 0x7d, 0x31,
+    0xf7, 0xb7, 0x3f, 0xe2, 0xb8, 0xf0, 0xe6, 0x90, 0x68, 0x8d, 0x81, 0x9b, 0xdd, 0xad, 0x25, 0x8d, 0x53, 0x5b, 0x6e,
+    0xbe, 0x87, 0x61, 0x62, 0x10, 0xe6, 0x2b, 0x2e, 0x14, 0xa6, 0x1b, 0x0c, 0x5a, 0xca, 0xe1, 0x32, 0xb1, 0xf9, 0xd6,
+    0x0b, 0xb2, 0xfb, 0xc4, 0xf4, 0xe8, 0xf9, 0x86, 0xae, 0x9c, 0x8c, 0x37, 0x07, 0x96, 0x59, 0x87, 0xdf, 0x2d, 0xd4,
+    0x05, 0x97, 0x7d, 0xc2, 0x59, 0xef, 0xa9, 0x8c, 0xcd, 0x7c, 0xb6, 0xab, 0x14, 0xc7, 0x7d, 0xe3, 0x02, 0x03, 0x01,
+    0x00, 0x01, 0x02, 0x82, 0x01, 0x80, 0x04, 0x89, 0x7c, 0xdc, 0xc3, 0xe8, 0xcc, 0xe5, 0x21, 0xd2, 0x12, 0xf1, 0x5f,
+    0x52, 0x41, 0x71, 0xc9, 0x83, 0x50, 0x0a, 0x93, 0x0f, 0x03, 0xd9, 0xac, 0xb3, 0xa7, 0x82, 0xb4, 0x4e, 0xc1, 0x0d,
+    0x5e, 0xf7, 0xcf, 0xa7, 0xa0, 0x46, 0x0f, 0xaf, 0x0a, 0xaf, 0xa2, 0x98, 0x53, 0x53, 0x54, 0x9f, 0xbb, 0x81, 0x8b,
+    0x26, 0xd2, 0xa0, 0x90, 0xac, 0xfe, 0x13, 0x00, 0x43, 0x60, 0x6f, 0xe0, 0xf8, 0xeb, 0xad, 0xd2, 0xee, 0xfc, 0xcb,
+    0xf5, 0xdf, 0x77, 0x1a, 0xa7, 0xaa, 0xc7, 0x5e, 0x1d, 0xb0, 0x5c, 0xfc, 0x8e, 0xf8, 0xac, 0x72, 0xc9, 0x8a, 0xb5,
+    0xfc, 0x3d, 0xbc, 0x37, 0x84, 0xd5, 0xad, 0xa3, 0x84, 0x3d, 0x16, 0xa6, 0x53, 0x3d, 0x3d, 0xb3, 0x65, 0xb2, 0xec,
+    0x5f, 0xd1, 0x96, 0xdd, 0x59, 0x3f, 0x38, 0x36, 0x58, 0x01, 0x50, 0x25, 0x42, 0xf3, 0x5e, 0x85, 0xc9, 0x98, 0x1b,
+    0x72, 0xe1, 0x21, 0x55, 0x2b, 0x2f, 0x7b, 0xc8, 0xff, 0x71, 0x75, 0x75, 0x71, 0xb5, 0x08, 0x0d, 0x07, 0x16, 0xed,
+    0x58, 0x06, 0x3f, 0xaa, 0x22, 0xa3, 0xb0, 0x66, 0x2a, 0x56, 0x7d, 0xe5, 0x4b, 0xe2, 0xb0, 0xb0, 0xc9, 0xc0, 0xe4,
+    0xa6, 0x3a, 0xba, 0x24, 0x1a, 0xad, 0x08, 0x91, 0xe3, 0x1a, 0x01, 0x3c, 0xeb, 0xd5, 0x17, 0xc6, 0xcc, 0xfb, 0xd8,
+    0xc0, 0x86, 0x4f, 0xe6, 0x66, 0xb5, 0xa3, 0xab, 0x2b, 0xa5, 0x11, 0xff, 0xcb, 0x56, 0x5f, 0x88, 0xef, 0x64, 0x45,
+    0x73, 0x09, 0x68, 0x86, 0x5a, 0x7c, 0xb4, 0x3c, 0xb8, 0x1f, 0x4b, 0x40, 0xd3, 0x05, 0xe2, 0xbb, 0x2c, 0x05, 0x8e,
+    0xda, 0x81, 0x9f, 0x37, 0x25, 0xfa, 0x7d, 0x7d, 0x94, 0x5f, 0x11, 0xc9, 0x47, 0x24, 0x72, 0x0e, 0x17, 0x08, 0xb6,
+    0xa7, 0xf0, 0x13, 0x2d, 0x76, 0xfe, 0x97, 0xed, 0x0c, 0xe6, 0x3b, 0xc0, 0x04, 0xe8, 0xf9, 0x0e, 0x70, 0xd7, 0x63,
+    0xa8, 0x32, 0xf1, 0x63, 0xd1, 0xca, 0xc7, 0xe2, 0x81, 0xf5, 0x72, 0x97, 0x22, 0x43, 0x52, 0x0a, 0x6b, 0x22, 0xdd,
+    0xe6, 0xf3, 0x9d, 0xed, 0x3a, 0xeb, 0x3b, 0x52, 0x7c, 0x38, 0xca, 0x14, 0xbc, 0x95, 0x9c, 0x9c, 0x0b, 0x14, 0x4b,
+    0x2c, 0x99, 0x45, 0xd1, 0x4e, 0x02, 0xaa, 0xf4, 0x57, 0x60, 0xba, 0xaf, 0x92, 0x03, 0x22, 0x03, 0x6d, 0x5e, 0x36,
+    0xfa, 0x14, 0x92, 0x26, 0x09, 0x61, 0x40, 0xe2, 0x9d, 0x75, 0x01, 0xb6, 0x0e, 0x89, 0xfc, 0x44, 0xc4, 0xf1, 0x4f,
+    0xb0, 0xe9, 0x50, 0xfe, 0xdf, 0xcd, 0xec, 0xe7, 0xda, 0x41, 0x75, 0x73, 0x4f, 0x46, 0x63, 0xf9, 0xa1, 0x28, 0xf4,
+    0xcb, 0xf6, 0x19, 0x15, 0x1c, 0xea, 0x0b, 0xde, 0x9a, 0x7d, 0xe8, 0x4c, 0x22, 0xd2, 0x0b, 0x4e, 0x5b, 0xa5, 0x0c,
+    0xe0, 0x34, 0x05, 0x97, 0x83, 0xa6, 0x5f, 0x74, 0xba, 0x81, 0x02, 0x81, 0xc1, 0x00, 0xfc, 0x1c, 0xe8, 0x40, 0x0f,
+    0x52, 0x89, 0x0b, 0x71, 0x02, 0x91, 0x64, 0xf1, 0x40, 0xfb, 0x55, 0x52, 0x44, 0x43, 0x9d, 0x85, 0x3e, 0x74, 0x86,
+    0xfc, 0xbb, 0x16, 0x3e, 0x3f, 0xa5, 0x6a, 0xb5, 0x04, 0xec, 0x4b, 0x5e, 0x06, 0x43, 0xd0, 0xa5, 0xf2, 0x48, 0xdb,
+    0x0c, 0xea, 0x4d, 0xf7, 0xfd, 0x8c, 0xcc, 0xb9, 0xe6, 0xe7, 0xa4, 0xb7, 0x2b, 0xbc, 0x80, 0xd0, 0x67, 0xa6, 0x41,
+    0xf4, 0x97, 0x5f, 0x86, 0x82, 0x42, 0xe3, 0xf4, 0xfd, 0x68, 0xc2, 0xcc, 0xe2, 0x60, 0x75, 0x9c, 0x55, 0x42, 0x06,
+    0x6c, 0xf3, 0x58, 0xa2, 0xdb, 0x3c, 0x63, 0x16, 0x21, 0x99, 0xde, 0x96, 0x46, 0x39, 0x36, 0x12, 0xc0, 0x7a, 0x69,
+    0x4c, 0x92, 0x3b, 0x69, 0xd6, 0xc9, 0xc6, 0x01, 0x0f, 0x77, 0x58, 0xc2, 0xba, 0xb4, 0xe1, 0x86, 0x90, 0x92, 0xa8,
+    0xba, 0x04, 0x76, 0xd7, 0xb4, 0x2b, 0x24, 0x6e, 0x7c, 0xca, 0x14, 0x3d, 0xe8, 0xb4, 0xcb, 0xf0, 0x2c, 0x00, 0xf9,
+    0x21, 0x8c, 0x6f, 0x37, 0x8c, 0x30, 0x69, 0x7a, 0xd2, 0x0e, 0x0a, 0xa1, 0xd5, 0x41, 0x7b, 0x75, 0xe7, 0xa9, 0x41,
+    0xe4, 0xeb, 0xbf, 0x7a, 0x89, 0xc4, 0x77, 0x0e, 0x78, 0x80, 0x28, 0x55, 0x97, 0x52, 0x4f, 0x88, 0xc6, 0x96, 0x72,
+    0x4c, 0x27, 0x56, 0x73, 0xc7, 0x76, 0x4c, 0x40, 0xf1, 0x3f, 0xf2, 0x6e, 0xc6, 0xc9, 0x08, 0x29, 0x02, 0x81, 0xc1,
+    0x00, 0xda, 0x28, 0x4c, 0xfb, 0x2b, 0xa1, 0xb9, 0xe9, 0x95, 0x77, 0x2a, 0x81, 0x4d, 0x51, 0x54, 0xcb, 0xc6, 0xb8,
+    0xbb, 0xf4, 0xf0, 0x99, 0x7b, 0x02, 0x7b, 0xdf, 0x0b, 0x2a, 0x83, 0x8f, 0x4b, 0xa7, 0x8b, 0xcb, 0x27, 0x04, 0x7e,
+    0x1e, 0x9f, 0x7a, 0xd7, 0x13, 0x8d, 0x9c, 0xa2, 0xbc, 0xf5, 0x3e, 0x1b, 0x2a, 0x7f, 0xb3, 0xc9, 0x05, 0xbd, 0x41,
+    0x8f, 0xa5, 0xbf, 0x04, 0x7f, 0xf4, 0xa4, 0x33, 0xd2, 0x45, 0x0d, 0xcf, 0x80, 0x86, 0x59, 0xaa, 0x95, 0xc9, 0xd5,
+    0x16, 0x30, 0xc8, 0xbe, 0x1a, 0x5b, 0xaf, 0x78, 0xe3, 0xc2, 0x3e, 0xc8, 0xd5, 0x0b, 0x96, 0x97, 0x7b, 0x51, 0xbb,
+    0x88, 0xd4, 0x7c, 0x58, 0x8c, 0x11, 0xd7, 0x81, 0xb3, 0xff, 0x0e, 0x66, 0x4b, 0x2e, 0xac, 0x23, 0x02, 0x0e, 0x7f,
+    0xc0, 0xb1, 0x5a, 0xd7, 0x19, 0x05, 0x0a, 0xa4, 0x41, 0x04, 0xcb, 0xbc, 0xd3, 0x3b, 0xc6, 0x49, 0x6e, 0xfa, 0x64,
+    0xb7, 0x8b, 0xfe, 0xf8, 0xe9, 0xf3, 0x62, 0xbf, 0xfc, 0x4c, 0xe8, 0x7a, 0x27, 0x9e, 0x30, 0xcd, 0x30, 0x15, 0x4d,
+    0xb7, 0x6c, 0xe4, 0xcc, 0x64, 0x6b, 0xe2, 0x1b, 0x94, 0x20, 0x81, 0xb7, 0x93, 0xb0, 0xfd, 0x49, 0x27, 0x5d, 0x98,
+    0x19, 0x6d, 0xc9, 0x4e, 0xf6, 0xfd, 0x6f, 0xcb, 0xd3, 0x27, 0x77, 0xbd, 0xf1, 0x1b, 0x6f, 0x8f, 0x67, 0x66, 0xa4,
+    0xba, 0x07, 0x2b, 0x02, 0x81, 0xc1, 0x00, 0x93, 0x91, 0xf4, 0x1c, 0x33, 0x1b, 0xd3, 0x9d, 0xff, 0xdb, 0x49, 0xf1,
+    0xb5, 0x09, 0x9d, 0x54, 0x16, 0xe0, 0x60, 0x57, 0x9e, 0xbb, 0xad, 0x07, 0xaa, 0x7d, 0x74, 0x0a, 0xa1, 0xc4, 0x98,
+    0x8e, 0x36, 0xc0, 0x7d, 0x69, 0x1e, 0xef, 0xa8, 0xfc, 0xc9, 0xb1, 0xfd, 0x8e, 0x34, 0xc3, 0xc8, 0xaa, 0x00, 0x35,
+    0x81, 0x87, 0x78, 0x05, 0xc1, 0x35, 0xf7, 0x93, 0xca, 0xe9, 0x30, 0xb7, 0x20, 0x8d, 0x4e, 0x5b, 0xf4, 0x79, 0x64,
+    0xe7, 0x6d, 0x41, 0x59, 0xed, 0x05, 0x81, 0x02, 0xb6, 0xac, 0x6d, 0x06, 0x47, 0xd5, 0xb5, 0x07, 0x36, 0x9e, 0xc5,
+    0x3d, 0x1a, 0x13, 0xef, 0xe7, 0x34, 0x59, 0x9e, 0x9e, 0x21, 0x4e, 0x45, 0xbe, 0x8d, 0x45, 0xfb, 0xb0, 0xbe, 0xd0,
+    0x88, 0xa4, 0x5d, 0xee, 0x75, 0xa5, 0x45, 0xe5, 0x50, 0x97, 0xe5, 0x50, 0x9f, 0xf9, 0xa6, 0xfa, 0xa1, 0xba, 0x33,
+    0x0b, 0xfd, 0x3d, 0x67, 0xd5, 0xc9, 0x15, 0xb2, 0xdd, 0xf5, 0x53, 0xe8, 0x7f, 0xcb, 0xac, 0xf9, 0xed, 0xb4, 0x14,
+    0xb9, 0xd0, 0xa4, 0x69, 0x72, 0xca, 0xda, 0x16, 0x83, 0x30, 0x43, 0xb1, 0x8f, 0x66, 0xb2, 0xe0, 0xee, 0x2d, 0x32,
+    0xa7, 0x24, 0xbf, 0x97, 0x5c, 0x6a, 0x43, 0xc2, 0xcc, 0x43, 0xb9, 0xa2, 0x53, 0x93, 0x1f, 0x16, 0x8c, 0x25, 0x61,
+    0x83, 0x0d, 0xf3, 0xa9, 0x5b, 0x50, 0x3e, 0x31, 0xe9, 0x02, 0x81, 0xc0, 0x43, 0x5e, 0x1a, 0x97, 0x9d, 0x9b, 0xad,
+    0x9b, 0x92, 0x4a, 0x60, 0x57, 0xd9, 0x96, 0x7a, 0x07, 0x0b, 0x70, 0xd4, 0xaa, 0x08, 0xfa, 0x7c, 0x60, 0x01, 0xfc,
+    0x98, 0xa8, 0x22, 0x44, 0x47, 0xea, 0x8f, 0x62, 0xc6, 0xc3, 0xbe, 0x66, 0x9a, 0x7d, 0x06, 0x99, 0xc5, 0x2b, 0x4f,
+    0x9d, 0xe6, 0x65, 0xad, 0x61, 0xec, 0x59, 0x8a, 0x84, 0x39, 0x33, 0x5b, 0xb6, 0xa5, 0x4c, 0x30, 0x6f, 0x4d, 0x9d,
+    0xab, 0x1b, 0x23, 0xee, 0xa6, 0x13, 0xd6, 0xf0, 0xb4, 0x9c, 0xc5, 0x2e, 0xbb, 0x15, 0xe2, 0x8e, 0xa5, 0x2d, 0x84,
+    0xb9, 0x60, 0xac, 0x9e, 0xbc, 0x1b, 0x7d, 0xff, 0x7d, 0x57, 0x7a, 0x00, 0x01, 0x0d, 0xfd, 0x12, 0x14, 0x18, 0x66,
+    0xb7, 0x3c, 0xd6, 0x27, 0x84, 0xa3, 0xff, 0x08, 0x38, 0x84, 0x5d, 0xb3, 0x15, 0x91, 0xa5, 0xc6, 0xd6, 0x25, 0xb9,
+    0x1f, 0x52, 0xe9, 0xcf, 0x7f, 0xb3, 0x7f, 0xc2, 0x01, 0x81, 0x55, 0x44, 0xd0, 0xf8, 0x85, 0xc9, 0x49, 0x1d, 0x7f,
+    0x87, 0xdc, 0x00, 0x16, 0x68, 0xd1, 0x92, 0xe4, 0x6a, 0x2a, 0xc9, 0xfb, 0x10, 0xa7, 0x7e, 0xee, 0xab, 0xda, 0x01,
+    0x06, 0x37, 0x1b, 0x97, 0xa3, 0x06, 0x0e, 0xd1, 0x5e, 0x54, 0xaa, 0xb9, 0x7f, 0x8b, 0xa0, 0xd4, 0xe8, 0xe2, 0x73,
+    0x20, 0xdb, 0x99, 0x40, 0x90, 0x8a, 0x16, 0x63, 0x44, 0x5d, 0x10, 0x15, 0x5a, 0x4d, 0x02, 0x81, 0xc0, 0x5a, 0x64,
+    0x55, 0x96, 0x85, 0x29, 0xf3, 0x13, 0xe5, 0x67, 0xf4, 0xb8, 0xfa, 0x43, 0xae, 0x75, 0xce, 0xae, 0x01, 0xc7, 0x51,
+    0xac, 0xc4, 0x95, 0x81, 0x36, 0x2c, 0x4d, 0x31, 0x92, 0x3d, 0xa4, 0x1e, 0x42, 0x2e, 0x66, 0xe0, 0xd9, 0x04, 0xfd,
+    0xb7, 0xc1, 0x88, 0xdc, 0xc7, 0xee, 0x01, 0x0d, 0xfa, 0x2a, 0x4a, 0x04, 0x85, 0x51, 0xa9, 0x52, 0x35, 0xe7, 0xe6,
+    0x4a, 0xac, 0x6d, 0x0f, 0x1c, 0xa5, 0x28, 0x66, 0xd5, 0x55, 0xf9, 0x0e, 0x13, 0x7e, 0xfa, 0x26, 0x28, 0xad, 0xbe,
+    0xf9, 0xe8, 0xfd, 0x37, 0xdf, 0x9b, 0x8d, 0x9b, 0x7c, 0xe1, 0x28, 0xd2, 0x21, 0xb0, 0x47, 0xba, 0xdc, 0xbb, 0xf9,
+    0x69, 0xcc, 0x0f, 0x3b, 0x98, 0x6c, 0xdb, 0xc1, 0x66, 0x0f, 0x97, 0x06, 0xbe, 0xcb, 0xe2, 0x65, 0xae, 0x23, 0x75,
+    0x7c, 0x5c, 0xbf, 0x26, 0x75, 0xae, 0xf6, 0x0d, 0xad, 0x16, 0xb5, 0x14, 0x9e, 0x0f, 0xd3, 0x66, 0x62, 0x48, 0xd4,
+    0x35, 0x09, 0x63, 0xc4, 0xed, 0x13, 0xa2, 0x09, 0x11, 0x4a, 0x20, 0x52, 0x6b, 0x39, 0x74, 0xc4, 0xff, 0x6a, 0xb3,
+    0xc5, 0xbf, 0x72, 0xf7, 0xae, 0x6c, 0x60, 0xba, 0x8f, 0xb9, 0xe0, 0xc3, 0x04, 0xe0, 0x47, 0xbc, 0xb3, 0x70, 0x49,
+    0x89, 0xbc, 0x4c, 0x4f, 0x51, 0xcb, 0x5a, 0x7f, 0xc1, 0xbc, 0x92, 0xc9, 0x90, 0x66, 0x58, 0x94, 0x63, 0x2a, 0xcd};
+unsigned int client_key_der_len = 1767;
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/dh-param.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/dh-param.h
new file mode 100644
index 0000000000..1a81d73449
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/dh-param.h
@@ -0,0 +1,17 @@
+unsigned char dh_der[] = {
+    0x30, 0x82, 0x01, 0x08, 0x02, 0x82, 0x01, 0x01, 0x00, 0xf5, 0x39, 0x89, 0x48, 0xe9, 0x02, 0xfc, 0xd5, 0x13,
+    0x31, 0xa5, 0x83, 0x8c, 0xeb, 0xdf, 0x6f, 0xb5, 0xd2, 0x94, 0x35, 0x17, 0x60, 0xec, 0xb5, 0x1f, 0x43, 0xd0,
+    0x90, 0xbd, 0xc8, 0x77, 0xa7, 0x1e, 0xd3, 0x0a, 0x2b, 0x2a, 0xd4, 0xea, 0xa8, 0xbb, 0x19, 0xa9, 0x01, 0x11,
+    0xde, 0x35, 0xaf, 0xd1, 0x95, 0x55, 0x05, 0x17, 0x9d, 0xf9, 0xc9, 0x73, 0x63, 0xdf, 0x10, 0x97, 0x4d, 0x55,
+    0xa2, 0x25, 0xa1, 0x90, 0xf0, 0x16, 0xe2, 0x23, 0xd0, 0x87, 0x7b, 0xc9, 0x03, 0xdb, 0x13, 0xdf, 0xf9, 0xe2,
+    0xb3, 0xe7, 0xf0, 0xff, 0x53, 0xf8, 0xbb, 0xd0, 0x5b, 0xe2, 0x97, 0x17, 0xeb, 0x6b, 0x20, 0x72, 0x96, 0x1f,
+    0xec, 0x18, 0x60, 0xd0, 0x1f, 0xe8, 0xf1, 0x6f, 0xa1, 0x82, 0x16, 0xca, 0xdc, 0x03, 0xde, 0xcd, 0x8b, 0xbc,
+    0xc8, 0xd3, 0xca, 0x30, 0x16, 0x52, 0x7f, 0x42, 0xfa, 0xbc, 0xb5, 0xae, 0xb1, 0x64, 0x4a, 0x00, 0x28, 0x0b,
+    0xcc, 0xfa, 0x7a, 0x59, 0xe9, 0x67, 0x84, 0xb1, 0x5e, 0x95, 0x86, 0x9a, 0xc7, 0xc5, 0xb3, 0xc0, 0x5a, 0x9c,
+    0x35, 0xa2, 0x33, 0x6e, 0xbd, 0xbf, 0x4a, 0x59, 0x07, 0x76, 0x7c, 0xdd, 0x3e, 0xe2, 0x70, 0x2b, 0x12, 0x75,
+    0x60, 0xfc, 0x89, 0xc3, 0x0b, 0xe7, 0xb0, 0x08, 0x01, 0x91, 0x68, 0x6e, 0x19, 0xe5, 0x3f, 0xdf, 0xc7, 0xdf,
+    0x57, 0x86, 0x83, 0xfa, 0x50, 0x46, 0x07, 0x5f, 0xe0, 0x59, 0x2c, 0x98, 0x79, 0x01, 0xb0, 0x8b, 0xad, 0xb5,
+    0x40, 0x36, 0x5b, 0xcf, 0x01, 0x59, 0x79, 0xfd, 0xb1, 0x4f, 0x69, 0x2b, 0x1c, 0xec, 0x97, 0x04, 0xd2, 0xdb,
+    0x7c, 0x0e, 0x5f, 0xa4, 0xd6, 0x16, 0x4a, 0x6c, 0x78, 0x8b, 0xa7, 0x23, 0xff, 0x14, 0x6e, 0x88, 0x37, 0xbf,
+    0x77, 0xc3, 0x11, 0xac, 0x87, 0xe9, 0xab, 0x0e, 0x4f, 0x95, 0xa0, 0x37, 0x2b, 0x02, 0x01, 0x02};
+unsigned int dh_der_len = 268;
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/server-cert.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/server-cert.h
new file mode 100644
index 0000000000..a97ae88ea4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/server-cert.h
@@ -0,0 +1,60 @@
+const unsigned char server_der[] = {
+    0x30, 0x82, 0x04, 0x3c, 0x30, 0x82, 0x02, 0xa4, 0x02, 0x01, 0x01, 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86,
+    0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30, 0x5f, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13,
+    0x02, 0x49, 0x4e, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02, 0x4d, 0x48, 0x31, 0x0d, 0x30,
+    0x0b, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0c, 0x04, 0x50, 0x55, 0x4e, 0x45, 0x31, 0x0c, 0x30, 0x0a, 0x06, 0x03, 0x55,
+    0x04, 0x0a, 0x0c, 0x03, 0x4e, 0x58, 0x50, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x02, 0x43,
+    0x41, 0x31, 0x19, 0x30, 0x17, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x09, 0x01, 0x16, 0x0a, 0x63,
+    0x61, 0x40, 0x6e, 0x78, 0x70, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x20, 0x17, 0x0d, 0x32, 0x33, 0x30, 0x33, 0x31, 0x35,
+    0x31, 0x34, 0x32, 0x34, 0x33, 0x37, 0x5a, 0x18, 0x0f, 0x33, 0x30, 0x32, 0x32, 0x30, 0x37, 0x31, 0x36, 0x31, 0x34,
+    0x32, 0x34, 0x33, 0x37, 0x5a, 0x30, 0x67, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x49,
+    0x4e, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02, 0x4d, 0x48, 0x31, 0x0d, 0x30, 0x0b, 0x06,
+    0x03, 0x55, 0x04, 0x07, 0x0c, 0x04, 0x50, 0x55, 0x4e, 0x45, 0x31, 0x0c, 0x30, 0x0a, 0x06, 0x03, 0x55, 0x04, 0x0a,
+    0x0c, 0x03, 0x4e, 0x58, 0x50, 0x31, 0x0f, 0x30, 0x0d, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x06, 0x53, 0x45, 0x52,
+    0x56, 0x45, 0x52, 0x31, 0x1d, 0x30, 0x1b, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x09, 0x01, 0x16,
+    0x0e, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, 0x40, 0x6e, 0x78, 0x70, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x82, 0x01, 0xa2,
+    0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x01, 0x05, 0x00, 0x03, 0x82, 0x01, 0x8f,
+    0x00, 0x30, 0x82, 0x01, 0x8a, 0x02, 0x82, 0x01, 0x81, 0x00, 0xce, 0x19, 0xcb, 0x0e, 0x8d, 0x82, 0xc1, 0x22, 0xe1,
+    0xed, 0xa2, 0x88, 0xd0, 0x46, 0xb6, 0x3c, 0x70, 0xcf, 0x30, 0x9c, 0x83, 0x55, 0x7d, 0xd6, 0xac, 0xb3, 0x2f, 0x02,
+    0xb3, 0x86, 0x8c, 0x8e, 0xcc, 0xcc, 0x9a, 0x6b, 0x1c, 0xf4, 0x12, 0x6e, 0x3a, 0x97, 0xb5, 0x6f, 0x0a, 0xf7, 0x0f,
+    0x7d, 0x61, 0x1f, 0xf4, 0xf1, 0xef, 0x27, 0xa8, 0x8d, 0xde, 0xcf, 0x77, 0xfa, 0x8c, 0x0c, 0xe3, 0x9b, 0x06, 0xfe,
+    0x70, 0x54, 0xd2, 0xb5, 0x4b, 0xd8, 0xac, 0x96, 0x6b, 0xef, 0x45, 0xe5, 0x33, 0xe4, 0xd4, 0xec, 0x37, 0xae, 0xfc,
+    0xe9, 0xbf, 0x4d, 0x97, 0x22, 0x85, 0xde, 0xbf, 0xfe, 0x58, 0x31, 0x01, 0xfd, 0x7c, 0xc1, 0x10, 0x8b, 0x06, 0xdd,
+    0x78, 0x6f, 0xad, 0x93, 0x6f, 0x1a, 0xf4, 0xf7, 0xab, 0x72, 0x63, 0xd3, 0x24, 0xcc, 0x47, 0xc4, 0xd2, 0x38, 0xfd,
+    0x69, 0x6a, 0x20, 0x72, 0x65, 0xa9, 0xe2, 0xe3, 0x14, 0xb3, 0xe1, 0x99, 0xc2, 0x70, 0xed, 0x4f, 0xd8, 0xf9, 0x71,
+    0x5a, 0x08, 0x2e, 0x90, 0x99, 0x87, 0x4c, 0x8d, 0x5b, 0xf2, 0x25, 0x82, 0xe1, 0xfe, 0x50, 0x38, 0xf3, 0x91, 0xd2,
+    0x86, 0xe6, 0xc9, 0xdc, 0x14, 0xef, 0xaf, 0x75, 0x48, 0x92, 0x65, 0xb3, 0x1a, 0x27, 0x21, 0x56, 0xa9, 0xa0, 0xfd,
+    0x99, 0xc6, 0xfe, 0x13, 0x3f, 0x65, 0xe2, 0x5a, 0x21, 0x1c, 0xac, 0xce, 0xea, 0x8d, 0x21, 0xae, 0x04, 0xeb, 0x0e,
+    0x1e, 0x90, 0x2b, 0x4b, 0x63, 0x11, 0xd4, 0x27, 0x3f, 0x72, 0xd3, 0x6a, 0x7c, 0xae, 0x41, 0x47, 0xd4, 0xdb, 0x7b,
+    0xf3, 0xbf, 0x31, 0x4d, 0x3a, 0x40, 0x02, 0x65, 0xfd, 0x1d, 0x0a, 0x35, 0x8b, 0xf3, 0x2e, 0x38, 0x56, 0xc2, 0xb3,
+    0x88, 0xc1, 0x36, 0xa0, 0x02, 0x09, 0xe7, 0x2d, 0xc2, 0xbe, 0x68, 0xcd, 0x42, 0xc3, 0xda, 0x4d, 0xdd, 0xfa, 0x69,
+    0x39, 0x49, 0x93, 0x3c, 0x6c, 0x00, 0x6f, 0x8b, 0x30, 0x88, 0x23, 0x8c, 0x0f, 0xef, 0x9e, 0x65, 0xd2, 0x45, 0x00,
+    0xd9, 0x80, 0x59, 0x1f, 0xcb, 0x65, 0x35, 0xdc, 0x85, 0xf7, 0xc2, 0x00, 0x9b, 0xc0, 0x2e, 0x4c, 0xb0, 0x90, 0xcd,
+    0x72, 0xbd, 0x8d, 0x61, 0x4f, 0x26, 0x12, 0x4c, 0x10, 0x32, 0xeb, 0x03, 0x42, 0x1f, 0xb6, 0x9a, 0xc2, 0xab, 0x31,
+    0x54, 0xb8, 0x80, 0xe2, 0x05, 0x40, 0xdd, 0x36, 0xed, 0x62, 0x84, 0xee, 0xb3, 0x0e, 0x0e, 0x74, 0x48, 0xad, 0xad,
+    0x6b, 0xd6, 0x99, 0x09, 0xc0, 0xa6, 0x61, 0x24, 0x19, 0x12, 0xcc, 0xca, 0x47, 0x12, 0x4a, 0xf3, 0x65, 0xef, 0xed,
+    0x97, 0x1a, 0x74, 0xa5, 0x4a, 0xbb, 0xdf, 0x02, 0x49, 0x1b, 0xb0, 0x4d, 0xa1, 0x95, 0x25, 0xda, 0x63, 0xe5, 0x44,
+    0xb2, 0xf2, 0x35, 0x5e, 0x80, 0x72, 0x7b, 0x50, 0x45, 0x5f, 0xc4, 0xc6, 0xcd, 0x85, 0x02, 0x03, 0x01, 0x00, 0x01,
+    0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x03, 0x82, 0x01, 0x81,
+    0x00, 0xaa, 0x6d, 0x4f, 0x75, 0x97, 0x2d, 0x69, 0xa6, 0x13, 0xc0, 0xde, 0xe1, 0x2f, 0x91, 0xeb, 0x63, 0x2a, 0x16,
+    0x8a, 0x56, 0x75, 0xce, 0xcb, 0x6f, 0xfa, 0xfa, 0x96, 0xa2, 0xf4, 0x87, 0xcd, 0xea, 0xc5, 0x9c, 0x79, 0x63, 0x56,
+    0x3b, 0x20, 0x02, 0xc2, 0xb4, 0xc8, 0x6c, 0x03, 0x0a, 0x19, 0xa0, 0xd6, 0x2d, 0xb4, 0x9a, 0x70, 0xe8, 0x86, 0x09,
+    0xcd, 0xf7, 0x38, 0xf7, 0x9a, 0x6c, 0xce, 0xeb, 0x1f, 0xff, 0x34, 0x1f, 0x20, 0xbd, 0x64, 0x93, 0xef, 0x95, 0xc4,
+    0x60, 0x68, 0x23, 0xe6, 0x5f, 0x20, 0xdd, 0xcd, 0xbf, 0xe2, 0x31, 0x66, 0xa5, 0x8a, 0x50, 0x88, 0xcc, 0x5a, 0x8d,
+    0x6d, 0x81, 0x00, 0x8b, 0xba, 0xf7, 0x2b, 0x0d, 0xe6, 0x02, 0x0e, 0x43, 0x96, 0x49, 0x78, 0x0f, 0xbf, 0x2a, 0x26,
+    0x2e, 0xde, 0xa0, 0xc4, 0x99, 0x71, 0x70, 0xfd, 0x31, 0xdc, 0xa4, 0x98, 0x80, 0x14, 0xaf, 0xe9, 0x86, 0x4e, 0x00,
+    0x52, 0x42, 0x9e, 0x22, 0x63, 0xbc, 0x25, 0x4d, 0xd0, 0xf4, 0xa9, 0x08, 0x9c, 0x82, 0xbb, 0x72, 0xce, 0xee, 0x08,
+    0x13, 0x33, 0xe4, 0xa8, 0x9c, 0x74, 0x8d, 0x3b, 0x79, 0x99, 0x17, 0x18, 0x28, 0x9c, 0x18, 0x6b, 0xd7, 0x36, 0x94,
+    0x2c, 0xf4, 0x0e, 0x0c, 0x6f, 0x27, 0x57, 0xdc, 0x23, 0x18, 0xee, 0xb7, 0xc2, 0x65, 0x5e, 0xd1, 0x6a, 0x59, 0x7e,
+    0x2a, 0xe8, 0xeb, 0xb4, 0xf8, 0xb7, 0xa5, 0xbc, 0xc5, 0x7c, 0x0f, 0x7b, 0x6f, 0x60, 0x32, 0x24, 0x8a, 0xf6, 0x60,
+    0xb2, 0x6d, 0x96, 0xb9, 0x27, 0x11, 0x58, 0x94, 0x75, 0x30, 0xe2, 0x34, 0x8d, 0x88, 0x90, 0xa7, 0xb4, 0x36, 0x55,
+    0x30, 0x7f, 0x10, 0x30, 0x48, 0x8c, 0x60, 0x6a, 0x7e, 0x2f, 0x16, 0xc8, 0x72, 0x9e, 0xb8, 0xe8, 0xb8, 0x05, 0xf7,
+    0x48, 0xe9, 0x22, 0x4d, 0x9c, 0x2a, 0xd7, 0xba, 0x4b, 0xf7, 0x63, 0xf9, 0x08, 0x6b, 0xd3, 0x88, 0x8f, 0x54, 0xce,
+    0xc3, 0x23, 0xed, 0x57, 0xb8, 0xa2, 0x44, 0x2c, 0x36, 0xe6, 0x96, 0xcb, 0xf7, 0xed, 0x8b, 0xfb, 0xf6, 0x6d, 0x6e,
+    0xa1, 0xd5, 0x43, 0x6d, 0xbd, 0x4c, 0xe7, 0xc6, 0x30, 0x03, 0x1f, 0x1f, 0x48, 0xbd, 0xc6, 0x1b, 0x5d, 0xc7, 0x60,
+    0xb3, 0x42, 0xbf, 0x0f, 0x8c, 0x1f, 0xd3, 0xea, 0x8b, 0x1c, 0x91, 0x89, 0x7c, 0x88, 0xbe, 0x93, 0xc9, 0xf1, 0x1c,
+    0x5c, 0xc6, 0x56, 0x10, 0x6e, 0xae, 0x55, 0x3e, 0x19, 0xa2, 0xab, 0x05, 0x4c, 0x62, 0xa9, 0x25, 0x3f, 0x54, 0x9e,
+    0xac, 0x47, 0x22, 0x7e, 0x03, 0xf0, 0xfb, 0x36, 0x8c, 0x89, 0x5c, 0x5f, 0xfd, 0xcf, 0xf3, 0x92, 0xc6, 0x13, 0xed,
+    0x4e, 0x28, 0x63, 0xa0, 0xfa, 0xae, 0x19, 0x53, 0x95, 0x80, 0x0f, 0xa8, 0x82, 0x52, 0xde, 0x89, 0xb5, 0xa7, 0xc5,
+    0xf9, 0x80, 0x0a, 0x3c, 0x2a};
+unsigned int server_der_len = 1088;
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/server-key.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/server-key.h
new file mode 100644
index 0000000000..a3bfec1ab0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/certs/server-key.h
@@ -0,0 +1,95 @@
+const unsigned char server_key_der[] = {
+    0x30, 0x82, 0x06, 0xe3, 0x02, 0x01, 0x00, 0x02, 0x82, 0x01, 0x81, 0x00, 0xce, 0x19, 0xcb, 0x0e, 0x8d, 0x82, 0xc1,
+    0x22, 0xe1, 0xed, 0xa2, 0x88, 0xd0, 0x46, 0xb6, 0x3c, 0x70, 0xcf, 0x30, 0x9c, 0x83, 0x55, 0x7d, 0xd6, 0xac, 0xb3,
+    0x2f, 0x02, 0xb3, 0x86, 0x8c, 0x8e, 0xcc, 0xcc, 0x9a, 0x6b, 0x1c, 0xf4, 0x12, 0x6e, 0x3a, 0x97, 0xb5, 0x6f, 0x0a,
+    0xf7, 0x0f, 0x7d, 0x61, 0x1f, 0xf4, 0xf1, 0xef, 0x27, 0xa8, 0x8d, 0xde, 0xcf, 0x77, 0xfa, 0x8c, 0x0c, 0xe3, 0x9b,
+    0x06, 0xfe, 0x70, 0x54, 0xd2, 0xb5, 0x4b, 0xd8, 0xac, 0x96, 0x6b, 0xef, 0x45, 0xe5, 0x33, 0xe4, 0xd4, 0xec, 0x37,
+    0xae, 0xfc, 0xe9, 0xbf, 0x4d, 0x97, 0x22, 0x85, 0xde, 0xbf, 0xfe, 0x58, 0x31, 0x01, 0xfd, 0x7c, 0xc1, 0x10, 0x8b,
+    0x06, 0xdd, 0x78, 0x6f, 0xad, 0x93, 0x6f, 0x1a, 0xf4, 0xf7, 0xab, 0x72, 0x63, 0xd3, 0x24, 0xcc, 0x47, 0xc4, 0xd2,
+    0x38, 0xfd, 0x69, 0x6a, 0x20, 0x72, 0x65, 0xa9, 0xe2, 0xe3, 0x14, 0xb3, 0xe1, 0x99, 0xc2, 0x70, 0xed, 0x4f, 0xd8,
+    0xf9, 0x71, 0x5a, 0x08, 0x2e, 0x90, 0x99, 0x87, 0x4c, 0x8d, 0x5b, 0xf2, 0x25, 0x82, 0xe1, 0xfe, 0x50, 0x38, 0xf3,
+    0x91, 0xd2, 0x86, 0xe6, 0xc9, 0xdc, 0x14, 0xef, 0xaf, 0x75, 0x48, 0x92, 0x65, 0xb3, 0x1a, 0x27, 0x21, 0x56, 0xa9,
+    0xa0, 0xfd, 0x99, 0xc6, 0xfe, 0x13, 0x3f, 0x65, 0xe2, 0x5a, 0x21, 0x1c, 0xac, 0xce, 0xea, 0x8d, 0x21, 0xae, 0x04,
+    0xeb, 0x0e, 0x1e, 0x90, 0x2b, 0x4b, 0x63, 0x11, 0xd4, 0x27, 0x3f, 0x72, 0xd3, 0x6a, 0x7c, 0xae, 0x41, 0x47, 0xd4,
+    0xdb, 0x7b, 0xf3, 0xbf, 0x31, 0x4d, 0x3a, 0x40, 0x02, 0x65, 0xfd, 0x1d, 0x0a, 0x35, 0x8b, 0xf3, 0x2e, 0x38, 0x56,
+    0xc2, 0xb3, 0x88, 0xc1, 0x36, 0xa0, 0x02, 0x09, 0xe7, 0x2d, 0xc2, 0xbe, 0x68, 0xcd, 0x42, 0xc3, 0xda, 0x4d, 0xdd,
+    0xfa, 0x69, 0x39, 0x49, 0x93, 0x3c, 0x6c, 0x00, 0x6f, 0x8b, 0x30, 0x88, 0x23, 0x8c, 0x0f, 0xef, 0x9e, 0x65, 0xd2,
+    0x45, 0x00, 0xd9, 0x80, 0x59, 0x1f, 0xcb, 0x65, 0x35, 0xdc, 0x85, 0xf7, 0xc2, 0x00, 0x9b, 0xc0, 0x2e, 0x4c, 0xb0,
+    0x90, 0xcd, 0x72, 0xbd, 0x8d, 0x61, 0x4f, 0x26, 0x12, 0x4c, 0x10, 0x32, 0xeb, 0x03, 0x42, 0x1f, 0xb6, 0x9a, 0xc2,
+    0xab, 0x31, 0x54, 0xb8, 0x80, 0xe2, 0x05, 0x40, 0xdd, 0x36, 0xed, 0x62, 0x84, 0xee, 0xb3, 0x0e, 0x0e, 0x74, 0x48,
+    0xad, 0xad, 0x6b, 0xd6, 0x99, 0x09, 0xc0, 0xa6, 0x61, 0x24, 0x19, 0x12, 0xcc, 0xca, 0x47, 0x12, 0x4a, 0xf3, 0x65,
+    0xef, 0xed, 0x97, 0x1a, 0x74, 0xa5, 0x4a, 0xbb, 0xdf, 0x02, 0x49, 0x1b, 0xb0, 0x4d, 0xa1, 0x95, 0x25, 0xda, 0x63,
+    0xe5, 0x44, 0xb2, 0xf2, 0x35, 0x5e, 0x80, 0x72, 0x7b, 0x50, 0x45, 0x5f, 0xc4, 0xc6, 0xcd, 0x85, 0x02, 0x03, 0x01,
+    0x00, 0x01, 0x02, 0x82, 0x01, 0x81, 0x00, 0xc3, 0x41, 0x1c, 0x66, 0x85, 0x1a, 0x42, 0xef, 0x51, 0x2b, 0x58, 0xb8,
+    0x54, 0xd9, 0x28, 0xfc, 0xc9, 0xc3, 0x00, 0x42, 0xc7, 0x09, 0xcf, 0x55, 0xf9, 0xf7, 0x27, 0xaa, 0x5f, 0x7a, 0x30,
+    0xdf, 0x78, 0x96, 0xbe, 0x14, 0x8c, 0x31, 0x8e, 0xe4, 0x6f, 0x0e, 0x1b, 0x0d, 0x40, 0x4e, 0x1f, 0x96, 0xa0, 0xd5,
+    0x2d, 0xb1, 0xa6, 0xe8, 0xe3, 0x7e, 0xc4, 0x7f, 0xb9, 0x22, 0xdc, 0x5b, 0xb9, 0xa5, 0xbd, 0x52, 0x80, 0x09, 0x5c,
+    0x35, 0xf5, 0xcd, 0x28, 0x74, 0xb9, 0x7c, 0xcd, 0xb2, 0xff, 0x1e, 0xe3, 0xb9, 0x86, 0x67, 0x79, 0xa3, 0xd9, 0x61,
+    0x20, 0xb5, 0xcc, 0x2d, 0xe3, 0xa6, 0x8a, 0xd6, 0xa3, 0x14, 0x0b, 0x84, 0xbc, 0xaf, 0x79, 0xa9, 0x87, 0xd8, 0x05,
+    0x91, 0x8f, 0xc8, 0xf2, 0x1b, 0x51, 0x89, 0xe5, 0x98, 0xbb, 0x5b, 0xed, 0x02, 0x42, 0x47, 0x4b, 0x8c, 0xfa, 0xc6,
+    0x12, 0x9a, 0xcd, 0xff, 0xed, 0x32, 0x47, 0xd8, 0x8b, 0x5a, 0xf2, 0xb1, 0x60, 0xdc, 0x26, 0x35, 0x85, 0x1e, 0x0b,
+    0x3f, 0x62, 0xb4, 0x13, 0x8a, 0x38, 0x79, 0x87, 0xa0, 0x1f, 0x8a, 0x57, 0x66, 0x1d, 0x1b, 0x21, 0x60, 0x3c, 0x75,
+    0x30, 0xd3, 0x84, 0xdf, 0xad, 0x35, 0x3b, 0xbc, 0xad, 0x99, 0x31, 0x49, 0x1c, 0x59, 0x47, 0xf3, 0xfa, 0x23, 0xd3,
+    0xc1, 0x58, 0x66, 0xa5, 0xb2, 0xcd, 0x7b, 0xe5, 0x19, 0xcc, 0xe6, 0x2f, 0x1f, 0x16, 0xd0, 0xad, 0xa1, 0xaf, 0xdf,
+    0x16, 0x70, 0xe8, 0x1d, 0x77, 0xe2, 0x15, 0x48, 0x4b, 0x2c, 0xf6, 0xb6, 0x31, 0x50, 0x69, 0x99, 0x66, 0xb0, 0xc2,
+    0x58, 0x3b, 0x80, 0xc2, 0x59, 0x68, 0x77, 0x8a, 0x40, 0xec, 0x15, 0x26, 0x9c, 0x2b, 0x58, 0xdf, 0x75, 0xe9, 0x52,
+    0xa3, 0x41, 0x43, 0x77, 0xa7, 0xc7, 0x1f, 0x62, 0x76, 0x75, 0xd1, 0x13, 0x72, 0xcd, 0x47, 0x46, 0x28, 0xd1, 0x41,
+    0xac, 0x4d, 0x1b, 0x56, 0x58, 0x0b, 0xf8, 0x37, 0x0f, 0xae, 0x0b, 0xd4, 0x75, 0x05, 0xb6, 0x66, 0x0d, 0x06, 0x3e,
+    0xa9, 0xb6, 0x66, 0xe2, 0x69, 0x60, 0x6d, 0x0b, 0x3f, 0x07, 0x62, 0xd6, 0x5a, 0xb3, 0x66, 0x83, 0x9c, 0x14, 0xd4,
+    0x86, 0xb5, 0xa6, 0x81, 0x90, 0x23, 0x77, 0xa8, 0x26, 0x51, 0x82, 0xad, 0xae, 0x43, 0x31, 0x0d, 0xf2, 0xb9, 0xc8,
+    0xbd, 0x3d, 0x11, 0xa9, 0x5c, 0x83, 0x11, 0x98, 0xe3, 0x0d, 0x2e, 0x29, 0x59, 0xe3, 0x2b, 0xd4, 0x8f, 0x69, 0xe7,
+    0xd3, 0x23, 0x74, 0x64, 0x13, 0x86, 0x8b, 0x44, 0x85, 0x03, 0xd0, 0xc0, 0x04, 0x0c, 0xe0, 0xbb, 0x2e, 0x1c, 0xb1,
+    0x4e, 0x20, 0xb0, 0xf1, 0x23, 0x84, 0xda, 0x03, 0xcf, 0xb8, 0x4d, 0x9f, 0x34, 0x8a, 0x92, 0x5d, 0x84, 0x08, 0x87,
+    0x86, 0x04, 0x6a, 0x19, 0x5f, 0xcb, 0xc5, 0x93, 0x82, 0xe7, 0x01, 0x02, 0x81, 0xc1, 0x00, 0xff, 0x3b, 0x7a, 0xe2,
+    0xdb, 0x66, 0x15, 0x4f, 0x21, 0x66, 0xee, 0x47, 0x84, 0x41, 0x5f, 0x75, 0x4f, 0x44, 0xf0, 0xc5, 0x93, 0xc0, 0x4e,
+    0xdf, 0x36, 0x47, 0x07, 0xe7, 0x45, 0x31, 0x57, 0x44, 0x5b, 0x23, 0x49, 0xd1, 0x5f, 0x7e, 0x0e, 0x2d, 0xd5, 0x93,
+    0xa1, 0xb5, 0x8c, 0xba, 0xf6, 0x77, 0x33, 0xc0, 0xb3, 0x4f, 0x6e, 0x1d, 0x02, 0x61, 0xfd, 0xb2, 0xfc, 0x78, 0x28,
+    0x89, 0x8f, 0xf4, 0x8a, 0xc6, 0x69, 0xdb, 0xc3, 0xe2, 0xc4, 0x54, 0x2e, 0xd1, 0xd9, 0x87, 0x7f, 0x35, 0x88, 0x4e,
+    0xcf, 0x16, 0x78, 0x57, 0x00, 0x3d, 0xe7, 0x02, 0x72, 0x22, 0xbe, 0x0d, 0x39, 0x1c, 0xfa, 0x7f, 0x41, 0xda, 0x65,
+    0x1a, 0xf9, 0xd5, 0xb7, 0x0c, 0xfc, 0x25, 0x86, 0xb4, 0xd5, 0xe7, 0x81, 0x01, 0x2f, 0x56, 0x17, 0xb5, 0x0b, 0x6b,
+    0x2c, 0xa5, 0xcb, 0x7c, 0xa2, 0x2f, 0xaf, 0x4b, 0xf7, 0x15, 0xe8, 0x15, 0x9f, 0xa6, 0x68, 0xab, 0x12, 0x5c, 0x11,
+    0xc6, 0xb1, 0x8c, 0x1f, 0x02, 0x31, 0x8d, 0x0c, 0x8f, 0x87, 0x88, 0x2a, 0xf6, 0x4d, 0x6b, 0x87, 0x75, 0x06, 0xa7,
+    0x5c, 0xf4, 0xb4, 0xf2, 0x2c, 0x48, 0xbb, 0x67, 0x44, 0x37, 0x14, 0xff, 0x7b, 0xc5, 0x0d, 0xa8, 0xcb, 0x3f, 0x62,
+    0x5e, 0x7d, 0x5c, 0x52, 0x63, 0x66, 0x8b, 0x6e, 0xc7, 0xb6, 0x52, 0xd3, 0x0b, 0x43, 0x60, 0xde, 0x89, 0x02, 0x81,
+    0xc1, 0x00, 0xce, 0xb8, 0x7b, 0xca, 0xb5, 0x7a, 0x44, 0x2c, 0x19, 0x5d, 0x52, 0xfb, 0x2a, 0xd2, 0x57, 0xe7, 0xa3,
+    0xba, 0x69, 0x00, 0xc0, 0x92, 0x8d, 0xba, 0xc9, 0x8c, 0x98, 0x6a, 0x13, 0x96, 0xa2, 0x64, 0xb8, 0x89, 0x36, 0x2d,
+    0x8a, 0x39, 0x65, 0x12, 0x9e, 0xbb, 0x64, 0xa5, 0x23, 0x0c, 0x6d, 0x98, 0x37, 0xa0, 0x9b, 0x00, 0x33, 0x3b, 0xc1,
+    0x76, 0x71, 0x41, 0x4e, 0xf2, 0xc5, 0x5f, 0x42, 0x6e, 0x26, 0x73, 0x27, 0x46, 0xcd, 0x18, 0x14, 0x7d, 0x8d, 0x91,
+    0xba, 0x90, 0x88, 0xd4, 0x33, 0x4f, 0xbd, 0x0a, 0x66, 0x0f, 0x11, 0x0f, 0xe8, 0x71, 0xcc, 0xad, 0x20, 0x81, 0x4b,
+    0x60, 0xdb, 0xf1, 0xef, 0x3f, 0x08, 0xf5, 0x57, 0x68, 0xaa, 0x23, 0xbf, 0xfe, 0x06, 0x77, 0x68, 0x4d, 0x51, 0x1d,
+    0xd3, 0xf6, 0x49, 0x9d, 0xe5, 0xfe, 0xbb, 0x21, 0xec, 0xef, 0xd6, 0x79, 0xdf, 0x8b, 0x25, 0x66, 0xee, 0x9b, 0x24,
+    0x4a, 0xba, 0xc8, 0x6a, 0x4d, 0x94, 0xc2, 0x48, 0x6d, 0x2f, 0xad, 0x49, 0x62, 0x33, 0xe0, 0x75, 0x7f, 0xa6, 0x9a,
+    0x96, 0x97, 0x37, 0xda, 0xff, 0xee, 0x6f, 0x6a, 0x15, 0xc8, 0x8e, 0x1e, 0xce, 0x89, 0x0e, 0xe2, 0xfc, 0x45, 0x72,
+    0x19, 0x74, 0x91, 0x0f, 0x77, 0xf5, 0x6c, 0xa7, 0xa2, 0x9e, 0x9c, 0x8c, 0x54, 0xf3, 0x0e, 0x5c, 0x95, 0x52, 0xc6,
+    0x1c, 0x3a, 0xd8, 0x1d, 0x02, 0x81, 0xc0, 0x0f, 0x31, 0x3e, 0x2e, 0x54, 0xba, 0xed, 0xd7, 0xc8, 0xf8, 0x34, 0x84,
+    0xc3, 0x45, 0x94, 0xe6, 0x09, 0xb2, 0xe3, 0xd6, 0x0e, 0xe6, 0x6a, 0x8b, 0x74, 0xd2, 0xa3, 0x90, 0xcb, 0x98, 0x95,
+    0x46, 0x37, 0x5a, 0x91, 0x61, 0x4a, 0x1a, 0xd9, 0xc3, 0x36, 0xac, 0x53, 0xfa, 0xd7, 0x86, 0xa5, 0x77, 0x10, 0xf8,
+    0x8e, 0x73, 0xd2, 0xed, 0x1d, 0x20, 0x32, 0x16, 0xbe, 0x5a, 0x74, 0xa7, 0x43, 0x8f, 0x5d, 0xd7, 0x53, 0xa3, 0xc6,
+    0x34, 0x30, 0x55, 0x86, 0x77, 0xed, 0x47, 0xd8, 0x75, 0x9a, 0x48, 0x7e, 0xa1, 0x2a, 0xc6, 0x9a, 0xf8, 0x14, 0x51,
+    0x1b, 0xf4, 0x1f, 0x75, 0xf0, 0x09, 0x5e, 0x8b, 0xc6, 0xa2, 0xb6, 0x53, 0xf5, 0xbd, 0x17, 0xe9, 0x48, 0xf4, 0xfe,
+    0xe0, 0xb2, 0xbe, 0xd5, 0xf9, 0xf9, 0x14, 0x59, 0xd2, 0xe7, 0xfc, 0x18, 0x2b, 0x42, 0x42, 0x87, 0xf0, 0xe8, 0xb1,
+    0x4f, 0xe2, 0xd8, 0xee, 0xb8, 0x93, 0x12, 0x35, 0xe4, 0xa0, 0xe0, 0x5a, 0x00, 0x65, 0x83, 0xcf, 0x00, 0x9e, 0x11,
+    0xba, 0x55, 0x69, 0xf0, 0x8c, 0xba, 0xad, 0x04, 0xe2, 0x1d, 0x64, 0x46, 0xef, 0x35, 0xfa, 0x18, 0x52, 0xb7, 0xfc,
+    0xfc, 0x9d, 0x7e, 0xbd, 0x7a, 0x63, 0x8f, 0x5d, 0x95, 0xc3, 0x8f, 0x1a, 0x6a, 0xc1, 0xdd, 0x11, 0x97, 0xa0, 0x03,
+    0x17, 0x16, 0x2e, 0x35, 0xeb, 0xbc, 0xb5, 0xfe, 0x69, 0x02, 0x81, 0xc0, 0x77, 0xc3, 0x98, 0x2c, 0xc3, 0xe1, 0x57,
+    0x37, 0xb9, 0x66, 0x41, 0x1a, 0x35, 0x1f, 0xf2, 0x3f, 0xc8, 0xb2, 0xc9, 0xfc, 0xde, 0x94, 0xc9, 0xba, 0x0a, 0xe5,
+    0x02, 0xb4, 0x8a, 0x2e, 0xbe, 0x5c, 0xde, 0x30, 0xd8, 0x8b, 0x9f, 0xc6, 0x4a, 0xd1, 0x73, 0xd7, 0x1b, 0xa3, 0x34,
+    0xe0, 0x11, 0x6a, 0x9b, 0xe7, 0xd7, 0x85, 0x51, 0x29, 0x70, 0x97, 0x3f, 0x5c, 0x57, 0xf1, 0xfc, 0xf9, 0x88, 0x92,
+    0x2a, 0x82, 0x92, 0xa1, 0xc9, 0x57, 0x07, 0x20, 0x0a, 0x72, 0x00, 0x85, 0x96, 0x50, 0x62, 0x7d, 0xf3, 0x06, 0xe0,
+    0x44, 0x20, 0x5d, 0x78, 0x0c, 0xde, 0x48, 0xfb, 0x49, 0x0d, 0x33, 0xcb, 0x99, 0xaa, 0x43, 0x79, 0xdc, 0x32, 0x4c,
+    0xf8, 0x2d, 0x88, 0x21, 0x12, 0xfc, 0x01, 0x18, 0xb2, 0x43, 0x36, 0xb7, 0x3c, 0xc5, 0x57, 0x27, 0xb2, 0xa1, 0x20,
+    0x15, 0x7f, 0xcb, 0xd2, 0x00, 0x5a, 0xa5, 0xfc, 0xdd, 0x33, 0x34, 0x7c, 0x6c, 0x7a, 0x72, 0x02, 0x1a, 0x61, 0x3d,
+    0xa8, 0xde, 0x9b, 0x62, 0x62, 0xad, 0xcb, 0x45, 0x2e, 0x6f, 0xe7, 0x89, 0x2a, 0x9a, 0x1d, 0xa6, 0xb5, 0x33, 0xdf,
+    0xf4, 0xf6, 0xa9, 0xd0, 0x7c, 0xc5, 0x7c, 0x2a, 0x2d, 0xcd, 0xc2, 0x03, 0xaf, 0xbb, 0x27, 0x83, 0xaf, 0xf4, 0x9b,
+    0x19, 0x8b, 0x97, 0x1d, 0xec, 0x47, 0x48, 0xca, 0x56, 0x4f, 0x62, 0xb1, 0x90, 0xdd, 0x02, 0x81, 0xc0, 0x26, 0x80,
+    0xdf, 0xf2, 0x8b, 0x17, 0x31, 0x72, 0x38, 0x4a, 0x05, 0x90, 0x92, 0xc5, 0x26, 0x71, 0xb2, 0xeb, 0x1e, 0x5e, 0x30,
+    0x56, 0x5a, 0x42, 0x60, 0x3c, 0x91, 0xf9, 0x29, 0xbe, 0x09, 0x89, 0xbe, 0xd1, 0x23, 0x3d, 0x52, 0xfd, 0x35, 0xf7,
+    0xab, 0x1a, 0xb5, 0x00, 0xae, 0x02, 0xc5, 0x68, 0x76, 0x5b, 0x6f, 0x6b, 0x95, 0xd5, 0x1f, 0x12, 0x05, 0x02, 0x42,
+    0x40, 0xd5, 0xa3, 0xc2, 0x7c, 0xd5, 0x04, 0xa8, 0x81, 0xa2, 0x79, 0xfc, 0x27, 0xe7, 0x11, 0x02, 0x84, 0x50, 0x90,
+    0x55, 0x1c, 0x96, 0x2f, 0x0d, 0xa8, 0xf6, 0x14, 0xdb, 0x33, 0xca, 0x1c, 0x4f, 0x99, 0x55, 0x11, 0x20, 0x19, 0xab,
+    0x97, 0xb3, 0xd1, 0x25, 0x56, 0xb9, 0x6e, 0x71, 0xec, 0x53, 0xfe, 0x58, 0xa6, 0xe5, 0x0a, 0x5f, 0x29, 0x2e, 0xfe,
+    0x20, 0xd0, 0x3b, 0xfc, 0x2c, 0x3d, 0x6e, 0x4b, 0x48, 0x05, 0x78, 0x9b, 0xf2, 0xd4, 0xc6, 0x58, 0xc8, 0x07, 0x22,
+    0x95, 0x51, 0x71, 0x6a, 0xb0, 0x20, 0x48, 0x91, 0x94, 0x67, 0x71, 0xb3, 0x6b, 0x09, 0x10, 0x09, 0x17, 0x32, 0x4c,
+    0xbf, 0x70, 0xe5, 0xce, 0x9b, 0x64, 0xfe, 0x04, 0x5e, 0x0c, 0xd9, 0xfb, 0xa7, 0x4e, 0xf7, 0xcb, 0x03, 0xb9, 0xcc,
+    0x17, 0x58, 0xff, 0x42, 0x3d, 0x1c, 0x09, 0x09, 0x9c, 0x4e, 0x7b, 0x1e, 0x0d, 0x08, 0x2d, 0x21, 0xd9, 0xd0, 0xf1};
+unsigned int server_key_der_len = 1767;
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/dhcp-server.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/dhcp-server.h
new file mode 100644
index 0000000000..0ba1e259a3
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/dhcp-server.h
@@ -0,0 +1,168 @@
+/*
+ *  Copyright 2008-2022, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*!\file dhcp-server.h
+ *\brief The file provides DHCP server configuration interfaces.
+ *
+ * The DHCP Server is required in the provisioning mode of the application to
+ * assign IP Address to Wireless Clients that connect to the WM.
+ */
+
+#ifndef __DHCP_SERVER_H__
+#define __DHCP_SERVER_H__
+
+#include <wmerrno.h>
+
+/** DHCPD Error Codes
+ */
+
+enum wm_dhcpd_errno
+{
+    WM_E_DHCPD_ERRNO_BASE = MOD_ERROR_START(MOD_DHCPD),
+    /** Dhcp server is already running */
+    WM_E_DHCPD_SERVER_RUNNING,
+    /** Failed to create dhcp thread */
+    WM_E_DHCPD_THREAD_CREATE,
+    /** Failed to create dhcp mutex */
+    WM_E_DHCPD_MUTEX_CREATE,
+    /** Failed to register dhcp commands */
+    WM_E_DHCPD_REGISTER_CMDS,
+    /** Failed to send dhcp response */
+    WM_E_DHCPD_RESP_SEND,
+    /** Ignore as msg is not a valid dns query */
+    WM_E_DHCPD_DNS_IGNORE,
+    /** Buffer overflow occurred */
+    WM_E_DHCPD_BUFFER_FULL,
+    /** The input message is NULL or has incorrect length */
+    WM_E_DHCPD_INVALID_INPUT,
+    /** Invalid opcode in the dhcp message */
+    WM_E_DHCPD_INVALID_OPCODE,
+    /** Invalid header type or incorrect header length */
+    WM_E_DHCPD_INCORRECT_HEADER,
+    /** Spoof length is either NULL or it exceeds max length */
+    WM_E_DHCPD_SPOOF_NAME,
+    /** Failed to get broadcast address */
+    WM_E_DHCPD_BCAST_ADDR,
+    /** Failed to look up requested IP address from the interface */
+    WM_E_DHCPD_IP_ADDR,
+    /** Failed to look up requested netmask from the interface */
+    WM_E_DHCPD_NETMASK,
+    /** Failed to create the socket */
+    WM_E_DHCPD_SOCKET,
+    /** Failed to send Gratuitous ARP */
+    WM_E_DHCPD_ARP_SEND,
+    /** Error in ioctl call */
+    WM_E_DHCPD_IOCTL_CALL,
+    /** Failed to init dhcp server */
+    WM_E_DHCPD_INIT,
+
+};
+
+/* Maximum length of the name_to_spoof for the DNS spoofer (see
+ * dhcp_server_start below)
+ */
+#define MAX_QNAME_SIZE 32
+
+/** Register DHCP server commands
+ *
+ * This function registers the CLI dhcp-stat for the DHCP server.
+ * dhcp-stat command displays ip to associated client mac mapping.
+ *
+ * @return -WM_E_DHCPD_REGISTER_CMDS if cli init operation failed.
+ * @return WM_SUCCESS if cli init operation success.
+ */
+int dhcpd_cli_init(void);
+
+/** Unrgister DHCP server commands
+ *
+ * This function unregisters the CLI dhcp-stat for the DHCP server.
+ * dhcp-stat command displays ip to associated client mac mapping.
+ *
+ * @return -WM_E_DHCPD_REGISTER_CMDS if cli init operation failed.
+ * @return WM_SUCCESS if cli init operation success.
+ */
+int dhcpd_cli_deinit(void);
+
+/** Start DHCP server
+ *
+ * This starts the DHCP server on the interface specified. Typically DHCP server
+ * should be running on the micro-AP interface but it can also run on wifi
+ * direct interface if configured as group owner. Use net_get_uap_handle() to
+ * get micro-AP interface handle.
+ *
+ * \param[in] intrfc_handle The interface handle on which DHCP server will start
+ *
+ * \return WM_SUCCESS on success or error code
+ */
+int dhcp_server_start(void *intrfc_handle);
+
+/** Start DNS server
+ *
+ * This starts the DNS server on the interface specified for dhcp server. This
+ * function needs to be used before dhcp_server_start() function and can be
+ * invoked on receiving \ref WLAN_REASON_INITIALIZED event in the application
+ * before starting micro-AP.
+ *
+ * The application needs to define its own list of domain names with the last
+ * entry as NULL. The dns server handles dns queries and if domain name match is
+ * found then resolves it to device ip address. Currently the maximum length for
+ * each domain name is set to 32 bytes.
+ *
+ * Eg.
+ * char *domain_names[] = {"nxpprov.net", "www.nxpprov.net", NULL};
+ *
+ * dhcp_enable_dns_server(domain_names);
+ *
+ * However, application can also start dns server without any domain names
+ * specified to solve following issue.
+ * Some of the client devices do not show Wi-Fi signal strength symbol when
+ * connected to micro-AP in open mode, if dns queries are not resolved.
+ * With dns server support enabled, dns server responds with ERROR_REFUSED
+ * indicating that the DNS server refuses to provide whatever data client is
+ * asking for.
+ *
+ * \param[in] domain_names Pointer to the list of domain names or NULL.
+ *
+ */
+void dhcp_enable_dns_server(char **domain_names);
+
+/** Stop DHCP server
+ */
+void dhcp_server_stop(void);
+
+/** Configure the DHCP dynamic IP lease time
+ *
+ * This API configures the dynamic IP lease time, which
+ * should be invoked before DHCP server initialization
+ *
+ * \param[in] val Number of seconds, use (60U*60U*number of hours)
+ *             for clarity. Max value is (60U*60U*24U*49700U)
+ *
+ * \return Error status code
+ */
+int dhcp_server_lease_timeout(uint32_t val);
+
+/** Get IP address corresponding to MAC address from dhcpd ip-mac mapping
+ *
+ * This API returns IP address mapping to the MAC address present in cache.
+ * IP-MAC cache stores MAC to IP mapping of previously or currently connected
+ * clients.
+ *
+ * \param[in] client_mac Pointer to a six byte array containing the MAC address
+ * of the client
+ * \param[out] client_ip Pointer to IP address of the client
+ *
+ * \return WM_SUCCESS on success or -WM_FAIL.
+ */
+int dhcp_get_ip_from_mac(uint8_t *client_mac, uint32_t *client_ip);
+
+/** Print DHCP stats on the console
+ *
+ * This API prints DHCP stats on the console
+ */
+void dhcp_stat(void);
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/nxp_wifi.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/nxp_wifi.h
new file mode 100644
index 0000000000..da2934a6f6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/nxp_wifi.h
@@ -0,0 +1,488 @@
+/*  Copyright 2023-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file nxp_wifi.h
+ *\brief This file provides macros mapping between zephyr Kconfig and Wi-Fi driver.
+ */
+
+#ifndef __NXP_WIFI_H__
+#define __NXP_WIFI_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if CONFIG_NXP_WIFI_SHELL
+#define CONFIG_WIFI_SHELL CONFIG_NXP_WIFI_SHELL
+#endif
+
+#if CONFIG_NXP_WIFI_MAX_AP_ENTRIES
+#define CONFIG_MAX_AP_ENTRIES CONFIG_NXP_WIFI_MAX_AP_ENTRIES
+#endif
+
+#if CONFIG_NXP_WIFI_WLAN_KNOWN_NETWORKS
+#define CONFIG_WLAN_KNOWN_NETWORKS CONFIG_NXP_WIFI_WLAN_KNOWN_NETWORKS
+#endif
+
+#if CONFIG_NXP_WIFI_SDIO_MULTI_PORT_RX_AGGR
+#define CONFIG_SDIO_MULTI_PORT_RX_AGGR CONFIG_NXP_WIFI_SDIO_MULTI_PORT_RX_AGGR
+#endif
+
+#if CONFIG_NXP_WIFI_SDIO_MULTI_PORT_TX_AGGR
+#define CONFIG_SDIO_MULTI_PORT_TX_AGGR CONFIG_NXP_WIFI_SDIO_MULTI_PORT_TX_AGGR
+#endif
+
+#if CONFIG_NXP_WIFI_AUTO_POWER_SAVE
+#define CONFIG_WIFI_AUTO_POWER_SAVE CONFIG_NXP_WIFI_AUTO_POWER_SAVE
+#endif
+
+#if CONFIG_NXP_WIFI_TX_RX_ZERO_COPY
+#define CONFIG_TX_RX_ZERO_COPY CONFIG_NXP_WIFI_TX_RX_ZERO_COPY
+#endif
+
+#if CONFIG_NXP_WIFI_RF_TEST_MODE
+#define CONFIG_WIFI_RF_TEST_MODE CONFIG_NXP_WIFI_RF_TEST_MODE
+#endif
+
+#if CONFIG_NXP_WIFI_OFFLOAD
+#define CONFIG_OFFLOAD CONFIG_NXP_WIFI_OFFLOAD
+#endif
+
+#if CONFIG_NXP_WIFI_STA_AUTO_DHCPV4
+#define CONFIG_STA_AUTO_DHCPV4 CONFIG_NXP_WIFI_STA_AUTO_DHCPV4
+#endif
+
+#if CONFIG_NXP_WIFI_STA_RECONNECT
+#define CONFIG_WIFI_STA_RECONNECT CONFIG_NXP_WIFI_STA_RECONNECT
+#endif
+
+#if CONFIG_NXP_WIFI_MON_THREAD_STACK_SIZE
+#define CONFIG_MON_THREAD_STACK_SIZE CONFIG_NXP_WIFI_MON_THREAD_STACK_SIZE
+#endif
+
+#if CONFIG_NXP_WIFI_WLCMGR_STACK_SIZE
+#define CONFIG_WLCMGR_STACK_SIZE CONFIG_NXP_WIFI_WLCMGR_STACK_SIZE
+#endif
+
+#if CONFIG_NXP_WIFI_WPS_STACK_SIZE
+#define CONFIG_WPS_STACK_SIZE CONFIG_NXP_WIFI_WPS_STACK_SIZE
+#endif
+
+#if CONFIG_NXP_WIFI_POWERSAVE_STACK_SIZE
+#define CONFIG_POWERSAVE_STACK_SIZE CONFIG_NXP_WIFI_POWERSAVE_STACK_SIZE
+#endif
+
+#if CONFIG_NXP_WIFI_TX_STACK_SIZE
+#define CONFIG_TX_STACK_SIZE CONFIG_NXP_WIFI_TX_STACK_SIZE
+#endif
+
+#if CONFIG_NXP_WIFI_DRIVER_STACK_SIZE
+#define CONFIG_DRIVER_STACK_SIZE CONFIG_NXP_WIFI_DRIVER_STACK_SIZE
+#endif
+
+#if CONFIG_NXP_WIFI_DHCP_SERVER_STACK_SIZE
+#define CONFIG_DHCP_SERVER_STACK_SIZE CONFIG_NXP_WIFI_DHCP_SERVER_STACK_SIZE
+#endif
+
+#if CONFIG_NXP_WIFI_11AX
+#define CONFIG_11AX CONFIG_NXP_WIFI_11AX
+#endif
+
+#if CONFIG_NXP_WIFI_11AC
+#define CONFIG_11AC CONFIG_NXP_WIFI_11AC
+#endif
+
+#if CONFIG_NXP_WIFI_ENABLE_HTTPSERVER
+#define CONFIG_ENABLE_HTTPSERVER CONFIG_NXP_WIFI_ENABLE_HTTPSERVER
+#endif
+
+#if CONFIG_NXP_WIFI_TX_RX_ZERO_COPY
+#define CONFIG_TX_RX_ZERO_COPY CONFIG_NXP_WIFI_TX_RX_ZERO_COPY
+#endif
+
+#if CONFIG_NXP_WIFI_CAPA
+#define CONFIG_WIFI_CAPA CONFIG_NXP_WIFI_CAPA
+#endif
+
+#if CONFIG_NXP_WIFI_WMM_UAPSD
+#define CONFIG_WMM_UAPSD CONFIG_NXP_WIFI_WMM_UAPSD
+#endif
+
+#if CONFIG_NXP_WIFI_GET_LOG
+#define CONFIG_WIFI_GET_LOG CONFIG_NXP_WIFI_GET_LOG
+#endif
+
+#if CONFIG_NXP_WIFI_TX_PER_TRACK
+#define CONFIG_WIFI_TX_PER_TRACK CONFIG_NXP_WIFI_TX_PER_TRACK
+#endif
+
+#if CONFIG_NXP_WIFI_CSI
+#define CONFIG_CSI CONFIG_NXP_WIFI_CSI
+#endif
+
+#if CONFIG_NXP_WIFI_RESET
+#define CONFIG_WIFI_RESET CONFIG_NXP_WIFI_RESET
+#endif
+
+#if CONFIG_NXP_WIFI_NET_MONITOR
+#define CONFIG_NET_MONITOR CONFIG_NXP_WIFI_NET_MONITOR
+#endif
+
+#if CONFIG_NXP_WIFI_ECSA
+#define CONFIG_ECSA CONFIG_NXP_WIFI_ECSA
+#endif
+
+#if CONFIG_NXP_WIFI_UNII4_BAND_SUPPORT
+#define CONFIG_UNII4_BAND_SUPPORT CONFIG_NXP_WIFI_UNII4_BAND_SUPPORT
+#endif
+
+#if CONFIG_NXP_WIFI_TSP
+#define CONFIG_TSP CONFIG_NXP_WIFI_TSP
+#endif
+
+#if CONFIG_NXP_WIFI_11AX_TWT
+#define CONFIG_11AX_TWT CONFIG_NXP_WIFI_11AX_TWT
+#endif
+
+#if CONFIG_NXP_WIFI_COMPRESS_TX_PWTBL
+#define CONFIG_COMPRESS_TX_PWTBL CONFIG_NXP_WIFI_COMPRESS_TX_PWTBL
+#endif
+
+#if CONFIG_NXP_WIFI_COMPRESS_RU_TX_PWTBL
+#define CONFIG_COMPRESS_RU_TX_PWTBL CONFIG_NXP_WIFI_COMPRESS_RU_TX_PWTBL
+#endif
+
+#if CONFIG_NXP_WIFI_MAX_PRIO
+#define CONFIG_WIFI_MAX_PRIO CONFIG_NXP_WIFI_MAX_PRIO
+#endif
+
+#if CONFIG_NXP_WIFI_IPS
+#define CONFIG_IPS CONFIG_NXP_WIFI_IPS
+#endif
+
+#if CONFIG_NXP_WIFI_EXT_SCAN_SUPPORT
+#define CONFIG_EXT_SCAN_SUPPORT CONFIG_NXP_WIFI_EXT_SCAN_SUPPORT
+#endif
+
+#if CONFIG_NXP_WIFI_SCAN_WITH_RSSIFILTER
+#define CONFIG_SCAN_WITH_RSSIFILTER CONFIG_NXP_WIFI_SCAN_WITH_RSSIFILTER
+#endif
+
+#if CONFIG_NXP_WIFI_DTIM_PERIOD
+#define CONFIG_WIFI_DTIM_PERIOD CONFIG_NXP_WIFI_DTIM_PERIOD
+#endif
+
+#if CONFIG_NXP_WIFI_RX_ABORT_CFG
+#define CONFIG_RX_ABORT_CFG CONFIG_NXP_WIFI_RX_ABORT_CFG
+#endif
+
+#if CONFIG_NXP_WIFI_RX_ABORT_CFG_EXT
+#define CONFIG_RX_ABORT_CFG_EXT CONFIG_NXP_WIFI_RX_ABORT_CFG_EXT
+#endif
+
+#if CONFIG_NXP_WIFI_CCK_DESENSE_CFG
+#define CONFIG_CCK_DESENSE_CFG CONFIG_NXP_WIFI_CCK_DESENSE_CFG
+#endif
+
+#if CONFIG_NXP_WIFI_MEM_ACCESS
+#define CONFIG_WIFI_MEM_ACCESS CONFIG_NXP_WIFI_MEM_ACCESS
+#endif
+
+#if CONFIG_NXP_WIFI_REG_ACCESS
+#define CONFIG_WIFI_REG_ACCESS CONFIG_NXP_WIFI_REG_ACCESS
+#endif
+
+#if CONFIG_NXP_WIFI_SUBSCRIBE_EVENT_SUPPORT
+#define CONFIG_SUBSCRIBE_EVENT_SUPPORT CONFIG_NXP_WIFI_SUBSCRIBE_EVENT_SUPPORT
+#endif
+
+#if CONFIG_NXP_WIFI_TX_RX_HISTOGRAM
+#define CONFIG_TX_RX_HISTOGRAM CONFIG_NXP_WIFI_TX_RX_HISTOGRAM
+#endif
+
+#if CONFIG_NXP_WIFI_COEX_DUTY_CYCLE
+#define CONFIG_COEX_DUTY_CYCLE CONFIG_NXP_WIFI_COEX_DUTY_CYCLE
+#endif
+
+#if CONFIG_NXP_WIFI_MMSF
+#define CONFIG_MMSF CONFIG_NXP_WIFI_MMSF
+#endif
+
+#if CONFIG_NXP_WIFI_USB_FILE_ACCESS
+#define CONFIG_USB_FILE_ACCESS CONFIG_NXP_WIFI_USB_FILE_ACCESS
+#endif
+
+#if CONFIG_NXP_WIFI_SCAN_CHANNEL_GAP_TIME
+#define CONFIG_SCAN_CHANNEL_GAP_TIME CONFIG_NXP_WIFI_SCAN_CHANNEL_GAP_TIME
+#endif
+
+#if CONFIG_NXP_WIFI_INACTIVITY_TIMEOUT_EXT
+#define CONFIG_INACTIVITY_TIMEOUT_EXT CONFIG_NXP_WIFI_INACTIVITY_TIMEOUT_EXT
+#endif
+
+#if CONFIG_NXP_WIFI_RF_TEST_MODE
+#define CONFIG_RF_TEST_MODE CONFIG_NXP_WIFI_RF_TEST_MODE
+#endif
+
+#if CONFIG_NXP_WIFI_IMD3_CFG
+#define CONFIG_IMD3_CFG CONFIG_NXP_WIFI_IMD3_CFG
+#endif
+
+#if CONFIG_NXP_WIFI_ANT_DETECT
+#define CONFIG_ANT_DETECT CONFIG_NXP_WIFI_ANT_DETECT
+#endif
+
+#if CONFIG_NXP_WIFI_WLAN_CALDATA_1ANT
+#define CONFIG_WLAN_CALDATA_1ANT CONFIG_NXP_WIFI_WLAN_CALDATA_1ANT
+#endif
+
+#if CONFIG_NXP_WIFI_WLAN_CALDATA_1ANT_WITH_DIVERSITY
+#define CONFIG_WLAN_CALDATA_1ANT_WITH_DIVERSITY CONFIG_NXP_WIFI_WLAN_CALDATA_1ANT_WITH_DIVERSITY
+#endif
+
+#if CONFIG_NXP_WIFI_WLAN_CALDATA_3ANT_DIVERSITY
+#define CONFIG_WLAN_CALDATA_3ANT_DIVERSITY CONFIG_NXP_WIFI_WLAN_CALDATA_3ANT_DIVERSITY
+#endif
+
+#if CONFIG_NXP_WIFI_CLOCKSYNC
+#define CONFIG_CLOCKSYNC CONFIG_NXP_WIFI_CLOCKSYNC
+#endif
+
+#if CONFIG_NXP_WIFI_WMM
+#define CONFIG_WMM CONFIG_NXP_WIFI_WMM
+#endif
+
+#if CONFIG_NXP_WIFI_IPV6
+#define CONFIG_IPV6 CONFIG_NXP_WIFI_IPV6
+#endif
+
+#if CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT
+#define CONFIG_MAX_IPV6_ADDRESSES CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT
+#endif
+
+#if CONFIG_NXP_WIFI_5GHz_SUPPORT
+#define CONFIG_5GHz_SUPPORT CONFIG_NXP_WIFI_5GHz_SUPPORT
+#endif
+
+#if CONFIG_NXP_WIFI_HOST_SLEEP
+#define CONFIG_HOST_SLEEP CONFIG_NXP_WIFI_HOST_SLEEP
+#endif
+
+#if CONFIG_PM
+#define CONFIG_POWER_MANAGER CONFIG_PM
+#endif
+
+#if CONFIG_NXP_WIFI_ROAMING
+#define CONFIG_ROAMING CONFIG_NXP_WIFI_ROAMING
+#endif
+
+#if CONFIG_NXP_WIFI_CLOUD_KEEP_ALIVE
+#define CONFIG_CLOUD_KEEP_ALIVE CONFIG_NXP_WIFI_CLOUD_KEEP_ALIVE
+#endif
+
+#if CONFIG_NXP_WIFI_MEF_CFG
+#define CONFIG_MEF_CFG CONFIG_NXP_WIFI_MEF_CFG
+#endif
+
+#if CONFIG_NXP_WIFI_TURBO_MODE
+#define CONFIG_TURBO_MODE CONFIG_NXP_WIFI_TURBO_MODE
+#endif
+
+#if CONFIG_NXP_WIFI_EU_CRYPTO
+#define CONFIG_EU_CRYPTO CONFIG_NXP_WIFI_EU_CRYPTO
+#endif
+
+#if CONFIG_NXP_WIFI_FIPS
+#define CONFIG_FIPS CONFIG_NXP_WIFI_FIPS
+#endif
+
+#if CONFIG_NXP_WIFI_OWE
+#define CONFIG_OWE CONFIG_NXP_WIFI_OWE
+#endif
+
+#if CONFIG_NXP_WIFI_11K
+#define CONFIG_11K CONFIG_NXP_WIFI_11K
+#endif
+
+#if CONFIG_NXP_WIFI_11V
+#define CONFIG_11V CONFIG_NXP_WIFI_11V
+#endif
+
+#if CONFIG_NXP_WIFI_11R
+#define CONFIG_11R CONFIG_NXP_WIFI_11R
+#endif
+
+#if CONFIG_NXP_WIFI_EU_CRYPTO
+#define CONFIG_WIFI_EU_CRYPTO CONFIG_NXP_WIFI_EU_CRYPTO
+#endif
+
+#if CONFIG_NXP_WIFI_CLOCKSYNC
+#define CONFIG_WIFI_CLOCKSYNC CONFIG_NXP_WIFI_CLOCKSYNC
+#endif
+
+#if CONFIG_NXP_WIFI_RTS_THRESHOLD
+#define CONFIG_WIFI_RTS_THRESHOLD 1
+#endif
+
+#if CONFIG_NXP_WIFI_UAP_WORKAROUND_STICKY_TIM
+#define CONFIG_UAP_WORKAROUND_STICKY_TIM CONFIG_NXP_WIFI_UAP_WORKAROUND_STICKY_TIM
+#endif
+
+#if CONFIG_NXP_WIFI_AUTO_NULL_TX
+#define CONFIG_AUTO_NULL_TX CONFIG_NXP_WIFI_AUTO_NULL_TX
+#endif
+
+#if CONFIG_NXP_WIFI_ENABLE_ERROR_LOGS
+#define CONFIG_ENABLE_ERROR_LOGS CONFIG_NXP_WIFI_ENABLE_ERROR_LOGS
+#endif
+
+#if CONFIG_NXP_WIFI_ENABLE_WARNING_LOGS
+#define CONFIG_ENABLE_WARNING_LOGS CONFIG_NXP_WIFI_ENABLE_WARNING_LOGS
+#endif
+
+#if CONFIG_NXP_WIFI_DEBUG_BUILD
+#define CONFIG_DEBUG_BUILD CONFIG_NXP_WIFI_DEBUG_BUILD
+#endif
+
+#if CONFIG_NXP_WIFI_OS_DEBUG
+#define CONFIG_OS_DEBUG CONFIG_NXP_WIFI_OS_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_NET_DEBUG
+#define CONFIG_NET_DEBUG CONFIG_NXP_WIFI_NET_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_WLCMGR_DEBUG
+#define CONFIG_WLCMGR_DEBUG CONFIG_NXP_WIFI_WLCMGR_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_EXTRA_DEBUG
+#define CONFIG_WIFI_EXTRA_DEBUG CONFIG_NXP_WIFI_EXTRA_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_UAP_DEBUG
+#define CONFIG_WIFI_UAP_DEBUG CONFIG_NXP_WIFI_UAP_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_EVENTS_DEBUG
+#define CONFIG_WIFI_EVENTS_DEBUG CONFIG_NXP_WIFI_EVENTS_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_CMD_RESP_DEBUG
+#define CONFIG_WIFI_CMD_RESP_DEBUG CONFIG_NXP_WIFI_CMD_RESP_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_PS_DEBUG
+#define CONFIG_WIFI_PS_DEBUG CONFIG_NXP_WIFI_PS_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_SCAN_DEBUG
+#define CONFIG_WIFI_SCAN_DEBUG CONFIG_NXP_WIFI_SCAN_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_PKT_DEBUG
+#define CONFIG_WIFI_PKT_DEBUG CONFIG_NXP_WIFI_PKT_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_IO_INFO_DUMP
+#define CONFIG_WIFI_IO_INFO_DUMP CONFIG_NXP_WIFI_IO_INFO_DUMP
+#endif
+
+#if CONFIG_NXP_WIFI_IO_DEBUG
+#define CONFIG_WIFI_IO_DEBUG CONFIG_NXP_WIFI_IO_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_IO_DUMP
+#define CONFIG_WIFI_IO_DUMP CONFIG_NXP_WIFI_IO_DUMP
+#endif
+
+#if CONFIG_NXP_WIFI_MEM_DEBUG
+#define CONFIG_WIFI_MEM_DEBUG CONFIG_NXP_WIFI_MEM_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_AMPDU_DEBUG
+#define CONFIG_WIFI_AMPDU_DEBUG CONFIG_NXP_WIFI_AMPDU_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_TIMER_DEBUG
+#define CONFIG_WIFI_TIMER_DEBUG CONFIG_NXP_WIFI_TIMER_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_SDIO_DEBUG
+#define CONFIG_WIFI_SDIO_DEBUG CONFIG_NXP_WIFI_SDIO_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_SDIO_IO_DEBUG
+#define CONFIG_SDIO_IO_DEBUG CONFIG_NXP_WIFI_SDIO_IO_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_FWDNLD_IO_DEBUG
+#define CONFIG_FWDNLD_IO_DEBUG CONFIG_NXP_WIFI_FWDNLD_IO_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_FW_DEBUG
+#define CONFIG_WIFI_FW_DEBUG CONFIG_NXP_WIFI_FW_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_FW_VDLL_DEBUG
+#define CONFIG_FW_VDLL_DEBUG CONFIG_NXP_WIFI_FW_VDLL_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_DHCP_SERVER_DEBUG
+#define CONFIG_DHCP_SERVER_DEBUG CONFIG_NXP_WIFI_DHCP_SERVER_DEBUG
+#endif
+
+#if CONFIG_NXP_WIFI_SMOKE_TESTS
+#define CONFIG_WIFI_SMOKE_TESTS CONFIG_NXP_WIFI_SMOKE_TESTS
+#endif
+
+#if CONFIG_NXP_WIFI_SM_IP_DHCP
+#define IP_USE_DHCP CONFIG_NXP_WIFI_SM_IP_DHCP
+#endif
+
+#if CONFIG_NXP_WIFI_SIGMA_AGENT
+#define CONFIG_SIGMA_AGENT CONFIG_NXP_WIFI_SIGMA_AGENT
+#endif
+
+#if CONFIG_NXP_WIFI_CUSTOM_CALDATA
+#define CONFIG_CUSTOM_CALDATA CONFIG_NXP_WIFI_CUSTOM_CALDATA
+#endif
+
+#if (CONFIG_NXP_WIFI_8978) || (CONFIG_NXP_WIFI_8987) || (CONFIG_NXP_WIFI_9177)
+
+#define CONFIG_GTK_REKEY_OFFLOAD 0
+
+#define CONFIG_FW_VDLL 1
+
+#endif
+
+#if (CONFIG_NXP_WIFI_9177)
+#define CONFIG_TCP_ACK_ENH 1
+#endif
+
+#if CONFIG_11AX
+
+#if !CONFIG_11K
+#define CONFIG_11K 1
+#endif
+
+#if !CONFIG_11V
+#define CONFIG_11V 1
+#endif
+
+#if !CONFIG_WPA_SUPP
+#define CONFIG_DRIVER_MBO 1
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NXP_WIFI_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/net/wm_net.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/net/wm_net.h
new file mode 100644
index 0000000000..d1f0dd94cf
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/net/wm_net.h
@@ -0,0 +1,334 @@
+/*
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ */
+/*
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*!\file wm_net.h
+ *\brief This file provides interface for network abstraction layer.
+ *
+ * This provides the calls related to the network layer.
+ */
+
+// Modified to work with Mongoose built-in TCP/IP by Cesanta Software Ltd.
+
+#ifndef _WM_NET_H_
+#define _WM_NET_H_
+
+#include <string.h>
+
+#include <osa.h>
+#include <wmtypes.h>
+#include <wmerrno.h>
+
+// need this dependency due to assumptions satisfied below
+#include "mongoose.h"
+// vendor libs have strong lwIP dependencies
+#define htonl(x) mg_htonl(x)
+#define ipaddr_addr(x) 0    // A Mongoose environment does not need this nor works this way
+
+// instead of exposing wlan.h, libs cast to "the same" structure and enums we must replicate here and expose to them
+enum net_address_types
+{
+    /** static IP address */
+    NET_ADDR_TYPE_STATIC = 0,
+    /** Dynamic  IP address*/
+    NET_ADDR_TYPE_DHCP = 1,
+    /** Link level address */
+    NET_ADDR_TYPE_LLA = 2,
+};
+
+/** This data structure represents an IPv4 address */
+struct net_ipv4_config
+{
+    /** Set to \ref ADDR_TYPE_DHCP to use DHCP to obtain the IP address or
+     *  \ref ADDR_TYPE_STATIC to use a static IP. In case of static IP
+     *  address ip, gw, netmask and dns members must be specified.  When
+     *  using DHCP, the ip, gw, netmask and dns are overwritten by the
+     *  values obtained from the DHCP server. They should be zeroed out if
+     *  not used. */
+    enum net_address_types addr_type;
+    /** The system's IP address in network order. */
+    unsigned address;
+    /** The system's default gateway in network order. */
+    unsigned gw;
+    /** The system's subnet mask in network order. */
+    unsigned netmask;
+    /** The system's primary dns server in network order. */
+    unsigned dns1;
+    /** The system's secondary dns server in network order. */
+    unsigned dns2;
+};
+
+#if CONFIG_IPV6
+/** This data structure represents an IPv6 address */
+struct net_ipv6_config
+{
+    /** The system's IPv6 address in network order. */
+    unsigned address[4];
+    /** The address type: linklocal, site-local or global. */
+    unsigned char addr_type;
+    /** The state of IPv6 address (Tentative, Preferred, etc). */
+    unsigned char addr_state;
+};
+#endif
+
+/** Network IP configuration.
+ *
+ *  This data structure represents the network IP configuration
+ *  for IPv4 as well as IPv6 addresses
+ */
+struct net_ip_config
+{
+#if CONFIG_IPV6
+    /** The network IPv6 address configuration that should be
+     * associated with this interface. */
+    struct net_ipv6_config ipv6[CONFIG_MAX_IPV6_ADDRESSES];
+    /** The network IPv6 valid addresses count */
+    size_t ipv6_count;
+#endif
+    /** The network IPv4 address configuration that should be
+     * associated with this interface. */
+    struct net_ipv4_config ipv4;
+};
+
+// libs only handle one private var, so we need to craft a "packet buffer" structure to be able to hold data length
+#pragma pack(push, 1)
+struct pb {
+  uint16_t len;
+  uint8_t data[1];
+};
+#pragma pack(pop)
+
+
+
+/** Deactivate the dhcp timer
+ *
+ */
+void net_stop_dhcp_timer(void);
+
+/** set MAC hardware address to lwip network interface
+ *
+ * \param[in] stamac sta MAC address.
+ * \param[in] uapmac uap MAC address.
+ *
+ */
+void net_wlan_set_mac_address(unsigned char *stamac, unsigned char *uapmac);
+
+/** Skip a number of bytes at the start of a stack buffer
+ *
+ * \param[in] buf input stack buffer.
+ * \param[in] in_offset offset to skip.
+ *
+ * \return the payload pointer after skip a number of bytes
+ */
+static inline uint8_t *net_stack_buffer_skip(void *buf, uint16_t in_offset)
+{
+	return ((struct pb *)buf)->data + in_offset;
+}
+
+/** Free a buffer allocated from stack memory
+ *
+ * \param[in] buf stack buffer pointer.
+ *
+ */
+static inline void net_stack_buffer_free(void *buf)
+{
+    free(buf);
+}
+
+/** Copy (part of) the contents of a packet buffer to an application supplied buffer
+ *
+ * \param[in] stack_buffer the stack buffer from which to copy data.
+ * \param[in] dst the destination buffer.
+ * \param[in] len length of data to copy.
+ * \param[in] offset offset into the stack buffer from where to begin copying
+ * \return copy status based on stack definition.
+ */
+static inline int net_stack_buffer_copy_partial(void *stack_buffer, void *dst, uint16_t len, uint16_t offset)
+{
+    memcpy(dst, ((struct pb *)stack_buffer)->data + offset, len);
+	return 1;
+}
+
+/** Get the data payload inside the stack buffer.
+ *
+ * \param[in] buf input stack buffer.
+ *
+ * \return the payload pointer of the stack buffer.
+ */
+static inline void *net_stack_buffer_get_payload(void *buf)
+{
+	return ((struct pb *)buf)->data;
+}
+
+/** Converts Internet host address in network byte order to a string in IPv4
+ * dotted-decimal notation
+ *
+ * \param[in] addr IP address in network byte order.
+ * \param[out] cp buffer in which IPv4 dotted-decimal string is returned.
+ *
+ */
+static inline void net_inet_ntoa(unsigned long addr, char *cp)
+{
+	// This is only called by WPL, we don't need to call this function so we don't serve this
+}
+
+/** Check whether buffer is IPv4 or IPV6 packet type
+ *
+ * \param[in] buffer pointer to buffer where packet to be checked located.
+ *
+ * \return true if buffer packet type matches with IPv4 or IPv6, false otherwise.
+ *
+ */
+static inline bool net_is_ip_or_ipv6(const uint8_t *b)
+{
+	// this does not account for 802.1Q-tagged traffic, no need to, this is called
+    // when sending and we don't send that.
+    return (b[12]==0x08 && b[13]== 0x00) || (b[12]==0x86 && b[13]== 0xdd);
+}
+
+/** Initialize TCP/IP networking stack
+ *
+ * \return WM_SUCCESS on success
+ * \return -WM_FAIL otherwise
+ */
+int net_wlan_init(void);
+
+/** DeInitialize TCP/IP networking stack
+ *
+ * \return WM_SUCCESS on success
+ * \return -WM_FAIL otherwise
+ */
+int net_wlan_deinit(void);
+
+/** Get STA interface netif structure pointer
+ *
+ * \return A pointer to STA interface netif structure
+ */
+struct netif *net_get_sta_interface(void);
+
+/** Get uAP interface netif structure pointer
+ *
+ * \return A pointer to uAP interface netif structure
+ *
+ */
+struct netif *net_get_uap_interface(void);
+
+/** Get interface name for given netif
+ *
+ * \param[out] pif_name Buffer to store interface name
+ * \param[in] iface Interface to get the name
+ *
+ * \return WM_SUCCESS on success
+ * \return -WM_FAIL otherwise
+ *
+ */
+int net_get_if_name_netif(char *pif_name, struct netif *iface);
+
+/** Get client data index for storing private data in * netif.
+ *
+ * \return allocated client data index, -1 if error or
+ *         not supported.
+ */
+int net_alloc_client_data_id();
+
+/** Get station interface handle
+ *
+ * Some APIs require the interface handle to be passed to them. The handle can
+ * be retrieved using this API.
+ *
+ * \return station interface handle
+ */
+void *net_get_sta_handle(void);
+#define net_get_mlan_handle() net_get_sta_handle()
+
+/** Get micro-AP interface handle
+ *
+ * Some APIs require the interface handle to be passed to them. The handle can
+ * be retrieved using this API.
+ *
+ * \return micro-AP interface handle
+ */
+void *net_get_uap_handle(void);
+
+/** Take interface up
+ *
+ * Change interface state to up. Use net_get_sta_handle(),
+ * net_get_uap_handle() to get interface handle.
+ *
+ * \param[in] intrfc_handle interface handle
+ *
+ * \return void
+ */
+void net_interface_up(void *intrfc_handle);
+
+/** Take interface down
+ *
+ * Change interface state to down. Use net_get_sta_handle(),
+ * net_get_uap_handle() to get interface handle.
+ *
+ * \param[in] intrfc_handle interface handle
+ *
+ * \return void
+ */
+void net_interface_down(void *intrfc_handle);
+
+/** Stop DHCP client on given interface
+ *
+ * Stop the DHCP client on given interface state. Use net_get_sta_handle(),
+ * net_get_uap_handle() to get interface handle.
+ *
+ * \param[in] intrfc_handle interface handle
+ *
+ * \return void
+ */
+void net_interface_dhcp_stop(void *intrfc_handle);
+
+/** Cleanup DHCP client on given interface
+ *
+ * Cleanup the DHCP client on given interface state. Use net_get_sta_handle(),
+ * net_get_uap_handle() to get interface handle.
+ *
+ * \param[in] intrfc_handle interface handle
+ *
+ */
+void net_interface_dhcp_cleanup(void *intrfc_handle);
+
+/** Configure IP address for interface
+ *
+ * \param[in] addr Address that needs to be configured.
+ * \param[in] intrfc_handle Handle for network interface to be configured.
+ *
+ * \return WM_SUCCESS on success or an error code.
+ */
+int net_configure_address(struct net_ip_config *addr, void *intrfc_handle);
+
+/** Configure DNS server address
+ *
+ * \param[in] ip IP address of the DNS server to set
+ * \param[in] role Network wireless BSS Role
+ *
+ */
+void net_configure_dns(struct net_ip_config *ip, unsigned int role);
+
+/** Get interface IP Address in \ref net_ip_config
+ *
+ * This function will get the IP address of a given interface. Use
+ * net_get_sta_handle(), net_get_uap_handle() to get
+ * interface handle.
+ *
+ * \param[out] addr \ref net_ip_config
+ * \param[in] intrfc_handle interface handle
+ *
+ * \return WM_SUCCESS on success or error code.
+ */
+int net_get_if_addr(struct net_ip_config *addr, void *intrfc_handle);
+
+
+#endif /* _WM_NET_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/mem_pool.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/mem_pool.h
new file mode 100644
index 0000000000..cf91cdbe59
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/mem_pool.h
@@ -0,0 +1,97 @@
+/*
+ *  Copyright 2023-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file mem_pool.h
+ *\brief This file provides OSA memory pool interfaces for Wi-Fi driver static memory operation.
+ */
+
+#ifndef MEM_POOL_H_
+#define MEM_POOL_H_
+
+#include <osa.h>
+
+/**
+ * @brief Amount of memory reserved for overhead
+ */
+#define POOL_OVERHEAD (sizeof(uint32_t))
+
+#if defined(SDK_OS_FREE_RTOS)
+
+#include "stack_simple.h"
+
+/**
+ *  The actual Memory Pool data structure.
+ *
+ *  This is a variable length data structure.
+ */
+typedef struct MemPool_t_
+{
+    /**
+     *  We need a lock to make this thread safe.
+     */
+    OSA_MUTEX_HANDLE_DEFINE(Lock);
+
+    /**
+     *  Memory blocks are stored on a stack.
+     */
+    Stack_t Stack;
+
+    /**
+     *  Save the item size for additions.
+     */
+    int ItemSize;
+
+    /**
+     *  The overall alignment of an item.
+     */
+    int Alignment;
+
+    /**
+     *  The begining of the actual memory pool itself.
+     */
+    unsigned char Buffer[1];
+
+} MemPool_t;
+
+#elif defined(FSL_RTOS_THREADX)
+
+typedef TX_BLOCK_POOL MemPool_t;
+
+#endif
+
+/** Create a MemoryPool
+ *\param[in,out] MemPool the created memory pool.
+ *\param[in] ItemSize How big is an allocation.
+ *\param[in] PreallocatedMemory Pointer to the preallocated memory
+ *           you are dedicating to this pool.
+ *\param[in] PreallocatedMemorySize How big is the buffer you are
+ *           passing in.
+ *\param[in] Alignment Power of 2 value denoting on which address boundary the
+ *           memory will be aligned to. Must be at least sizeof(unsigned char *).
+ *\return A Handle to the pool, or NULL on failure.
+ */
+MemoryPool_t OSA_MemoryPoolCreate(
+    MemPool_t *MemPool, int ItemSize, void *PreallocatedMemory, int PreallocatedMemorySize, int Alignment);
+
+/**Get a memory buffer from the pool.
+ * Note that this can block, and cannnot be used from ISR context.
+ *
+ *\param[in] pool A handle to a MemoryPool.
+ *\return A pointer or NULL on failure.
+ */
+void *OSA_MemoryPoolAllocate(MemoryPool_t pool);
+
+/**free a memory buffer to the pool.
+ *
+ *  note This can block, and cannnot be used from ISR context.
+ *  note There is no check that the memory passed in is valid.
+ *
+ *\param[in] pool A handle to a MemoryPool.
+ *\param[in] memory memory obtained from OSA_MemoryPoolAllocate().
+ */
+void OSA_MemoryPoolFree(MemoryPool_t pool, void *memory);
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/mem_pool_config.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/mem_pool_config.h
new file mode 100644
index 0000000000..ce166483ba
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/mem_pool_config.h
@@ -0,0 +1,48 @@
+/*  Copyright 2023-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file mem_pool_config.h
+ *\brief This file declares interface for memeory pool.
+ */
+
+#ifndef _MEM_POOL_CONFIG_H_
+#define _MEM_POOL_CONFIG_H_
+
+#include <mem_pool.h>
+
+#include <wmlog.h>
+#define mpool_e(...) wmlog_e("mpool", ##__VA_ARGS__)
+#define mpool_w(...) wmlog_w("mpool", ##__VA_ARGS__)
+
+#if CONFIG_MEM_POOL_DEBUG
+#define mpool_d(...) wmlog("mpool", ##__VA_ARGS__)
+#else
+#define mpool_d(...)
+#endif /* ! CONFIG_MEM_POOL_DEBUG */
+
+/**
+ *  Handle for memory pools.
+ *
+ *  These are fixed allocation size memory areas.
+ */
+extern MemoryPool_t pmAdapterMemoryPool;
+extern MemoryPool_t pmPrivateMemoryPool;
+extern MemoryPool_t buf_32_MemoryPool;
+extern MemoryPool_t buf_128_MemoryPool;
+extern MemoryPool_t buf_256_MemoryPool;
+extern MemoryPool_t buf_512_MemoryPool;
+extern MemoryPool_t buf_768_MemoryPool;
+extern MemoryPool_t buf_1024_MemoryPool;
+extern MemoryPool_t buf_1280_MemoryPool;
+extern MemoryPool_t buf_1536_MemoryPool;
+extern MemoryPool_t buf_1792_MemoryPool;
+extern MemoryPool_t buf_2048_MemoryPool;
+extern MemoryPool_t buf_2560_MemoryPool;
+extern MemoryPool_t buf_3072_MemoryPool;
+extern MemoryPool_t buf_4096_MemoryPool;
+
+int mem_pool_init();
+
+#endif // _MEM_POOL_CONFIG_H_
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/osa.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/osa.h
new file mode 100644
index 0000000000..f1f9f4ad52
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/osa.h
@@ -0,0 +1,387 @@
+/*
+ *  Copyright 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file osa.h
+ *\brief This file contains OSA wrapper declarations for timer, read/write lock and idle hook.
+*/
+
+
+#ifndef _OSA_H_
+#define _OSA_H_
+
+#include <wifi_config_default.h>
+
+#include "fsl_os_abstraction.h"
+
+#if defined(SDK_OS_FREE_RTOS)
+#include <osa_freertos.h>
+#elif defined(FSL_RTOS_THREADX)
+#include "app_config.h"
+#include <osa_threadx.h>
+#elif (CONFIG_ZEPHYR)
+#include <osa_zephyr.h>
+#else
+#error "Please define OS type"
+#endif
+
+#include <wmerrno.h>
+#include <wm_utils.h>
+
+/*** Timer Management ***/
+/** Create timer
+ *
+ * This function creates a timer.
+ *
+ * @param[in] timerHandle Pointer to the timer handle
+ * @param[in] ticks Period in ticks
+ * @param[in] call_back Timer expire callback function
+ * @param[in] cb_arg Timer callback data
+ * @param[in] reload Reload Options, valid values include \ref KOSA_TimerOnce
+ * or \ref KOSA_TimerPeriodic.
+ * @param[in] activate Activate Options, valid values include \ref
+ * OSA_TIMER_AUTO_ACTIVATE or \ref OSA_TIMER_NO_ACTIVATE
+ *
+ * @return KOSA_StatusSuccess if timer created successfully
+ * @return KOSA_StatusError if timer creation fails
+ */
+osa_status_t OSA_TimerCreate(osa_timer_handle_t timerHandle,
+                             osa_timer_tick ticks,
+                             void (*call_back)(osa_timer_arg_t),
+                             void *cb_arg,
+                             osa_timer_t reload,
+                             osa_timer_activate_t activate);
+
+/** Activate timer
+ *
+ * This function activates (or starts) a timer that was previously created using
+ * OSA_TimerCreate(). If the timer had already started and was already in the
+ * active state, then this call is equivalent to OSA_TimerReset().
+ *
+ * @param[in] timerHandle Pointer to a timer handle
+ *
+ * @return KOSA_StatusSuccess if timer activated successfully
+ * @return KOSA_StatusError if timer activation fails
+ *
+ */
+osa_status_t OSA_TimerActivate(osa_timer_handle_t timerHandle);
+
+/** Change timer period
+ *
+ * This function changes the period of a timer that was previously created using
+ * OSA_TimerCreate(). This function changes the period of an active or dormant
+ * state timer.
+ *
+ * @param[in] timerHandle Pointer to a timer handle
+ * @param[in] ntime Time in ticks after which the timer will expire
+ * @param[in] block_time  This option is currently not supported
+ *
+ * @return KOSA_StatusSuccess if timer change successfully
+ * @return KOSA_StatusError if timer change fails
+ */
+osa_status_t OSA_TimerChange(osa_timer_handle_t timerHandle, osa_timer_tick ntime, osa_timer_tick block_time);
+
+/** Check the timer active state
+ *
+ * This function checks if the timer is in the active or dormant state. A timer
+ * is in the dormant state if (a) it has been created but not started, or (b) it
+ * has expired and a one-shot timer.
+ *
+ * @param [in] timerHandle Pointer to a timer handle
+ *
+ * @return true if timer is active
+ * @return false if time is not active
+ */
+bool OSA_TimerIsRunning(osa_timer_handle_t timerHandle);
+
+/**
+ * Get the timer context
+ *
+ * This function helps to retrieve the timer context i.e. 'cb_arg' passed
+ * to OSA_TimerCreate().
+ *
+ * @param[in] timer_t Pointer to timer handle. The timer handle is received
+ * in the timer callback.
+ *
+ * @return The timer context i.e. the callback argument passed to
+ * OSA_TimerCreate().
+ */
+void *OSA_TimerGetContext(osa_timer_handle_t timerHandle);
+
+/** Reset timer
+ *
+ * This function resets a timer that was previously created using using
+ * OSA_TimerCreate(). If the timer had already been started and was already in
+ * the active state, then this call will cause the timer to re-evaluate its
+ * expiry time so that it is relative to when OSA_TimerReset() was called. If
+ * the timer was in the dormant state then this call behaves in the same way as
+ * OSA_TimerActivate().
+ *
+ * @param[in] timerHandle Pointer to a timer handle
+ *
+ * @return KOSA_StatusSuccess if timer reset successfully
+ * @return KOSA_StatusError if timer reset fails
+ */
+osa_status_t OSA_TimerReset(osa_timer_handle_t timerHandle);
+
+/** Deactivate timer
+ *
+ * This function deactivates (or stops) a timer that was previously started.
+ *
+ * @param [in] timerHandle handle populated by OSA_TimerCreate().
+ *
+ * @return KOSA_StatusSuccess if timer deactivate successfully
+ * @return KOSA_StatusError if timer deactivate fails
+ */
+osa_status_t OSA_TimerDeactivate(osa_timer_handle_t timerHandle);
+
+/** Destroy timer
+ *
+ * This function deletes a timer.
+ *
+ * @param[in] timerHandle Pointer to a timer handle
+ *
+ * @return KOSA_StatusSuccess if timer destroy successfully
+ * @return KOSA_StatusError if timer destroy fails
+ */
+osa_status_t OSA_TimerDestroy(osa_timer_handle_t timerHandle);
+
+/*
+ * Reader Writer Locks
+ * This is a generic implementation of reader writer locks
+ * which is reader priority.
+ * Not only it provides mutual exclusion but also synchronization.
+ * Six APIs are exposed to user which include.
+ * -# Create a reader writer lock
+ * -# Delete a reader writer lock
+ * -# Reader lock
+ * -# Reader unlock
+ * -# Writer lock
+ * -# Writer unlock
+ * The locking operation is timeout based.
+ * Caller can give a timeout from 0 (no wait) to
+ * infinite (wait forever)
+ */
+
+typedef struct _rw_lock osa_rw_lock_t;
+/** This is prototype of reader callback */
+typedef int (*cb_fn)(osa_rw_lock_t *plock, unsigned int wait_time);
+
+struct _rw_lock
+{
+    /** Mutex for reader mutual exclusion */
+    OSA_MUTEX_HANDLE_DEFINE(reader_mutex);
+    /** Mutex for write mutual exclusion */
+    OSA_MUTEX_HANDLE_DEFINE(write_mutex);
+    /** Lock which when held by reader,
+     *  writer cannot enter critical section
+     */
+    OSA_SEMAPHORE_HANDLE_DEFINE(rw_lock);
+    /** Function being called when first reader gets
+     *  the lock
+     */
+    cb_fn reader_cb;
+    /** Counter to maintain number of readers
+     *  in critical section
+     */
+    unsigned int reader_count;
+};
+
+int OSA_RWLockCreateWithCB(osa_rw_lock_t *plock, const char *mutex_name, const char *lock_name, cb_fn r_fn);
+
+/** Create reader-writer lock
+ *
+ * This function creates a reader-writer lock.
+ *
+ * @param[in] lock Pointer to a reader-writer lock handle
+ * @param[in] mutex_name Name of the mutex
+ * @param[in] lock_name Name of the lock
+ *
+ * @return WM_SUCCESS on success
+ * @return -WM_FAIL on error
+ */
+int OSA_RWLockCreate(osa_rw_lock_t *plock, const char *mutex_name, const char *lock_name);
+
+/** Delete a reader-write lock
+ *
+ * This function deletes a reader-writer lock.
+ *
+ * @param[in] lock Pointer to the reader-writer lock handle
+ *
+ */
+void OSA_RWLockDestroy(osa_rw_lock_t *lock);
+
+/** Acquire writer lock
+ *
+ * This function acquires a writer lock. While readers can acquire the lock on a
+ * sharing basis, writers acquire the lock in an exclusive manner.
+ *
+ * @param[in] lock Pointer to the reader-writer lock handle
+ * @param[in] wait_time The maximum amount of time, in OS ticks, the task should
+ * block waiting for the lock to be acquired. The special values \ref
+ * osaWaitForever_c and \ref osaWaitNone_c are provided to respectively wait
+ * infinitely or return immediately.
+ *
+ * @return  WM_SUCCESS on success
+ * @return  -WM_FAIL on error
+ *
+ */
+int OSA_RWLockWriteLock(osa_rw_lock_t *lock, unsigned int wait_time);
+
+/** Release writer lock
+ *
+ * This function releases a writer lock previously acquired using
+ * OSA_RWLockWriteLock().
+ *
+ * @param[in] lock Pointer to the reader-writer lock handle
+ */
+void OSA_RWLockWriteUnlock(osa_rw_lock_t *lock);
+
+/** Acquire reader lock
+ *
+ * This function acquires a reader lock. While readers can acquire the lock on a
+ * sharing basis, writers acquire the lock in an exclusive manner.
+ *
+ * @param[in] lock pointer to the reader-writer lock handle
+ * @param[in] wait_time The maximum amount of time, in OS ticks, the task should
+ * block waiting for the lock to be acquired. The special values \ref
+ * osaWaitForever_c and \ref osaWaitNone_c are provided to respectively wait
+ * infinitely or return immediately.
+ *
+ * @return  WM_SUCCESS on success
+ * @return  -WM_FAIL on error
+ *
+ */
+int OSA_RWLockReadLock(osa_rw_lock_t *lock, unsigned int wait_time);
+
+/** Release reader lock
+ *
+ * This function releases a reader lock previously acquired using
+ * OSA_RWLockReadLock().
+ *
+ * @param[in] lock pointer to the reader-writer lock handle
+ *
+ * @return WM_SUCCESS if unlock operation successful.
+ * @return -WM_FAIL if unlock operation failed.
+ */
+int OSA_RWLockReadUnlock(osa_rw_lock_t *lock);
+
+/*** Tick function */
+#define MAX_CUSTOM_HOOKS 4U
+
+extern void (*g_osa_tick_hooks[MAX_CUSTOM_HOOKS])(void);
+extern void (*g_osa_idle_hooks[MAX_CUSTOM_HOOKS])(void);
+
+/** Setup idle function
+ *
+ * This function sets up a callback function which will be called whenever the
+ * system enters the idle thread context.
+ *
+ *  @param[in] func The callback function
+ *
+ *  @return WM_SUCCESS on success
+ *  @return -WM_FAIL on error
+ */
+int OSA_SetupIdleFunction(void (*func)(void));
+
+/** Setup tick function
+ *
+ * This function sets up a callback function which will be called on every
+ * SysTick interrupt.
+ *
+ *  @param[in] func The callback function
+ *
+ *  @return WM_SUCCESS on success
+ *  @return -WM_FAIL on error
+ */
+int OSA_SetupTickFunction(void (*func)(void));
+
+/** Remove idle function
+ *
+ *  This function removes an idle callback function that was registered
+ *  previously using OSA_SetupIdleFunction().
+ *
+ *  @param[in] func The callback function
+ *
+ *  @return WM_SUCCESS on success
+ *  @return -WM_FAIL on error
+ */
+int OSA_RemoveIdleFunction(void (*func)(void));
+
+/** Remove tick function
+ *
+ *  This function removes a tick callback function that was registered
+ *  previously using OSA_SetupTickFunction().
+ *
+ *  @param[in] func Callback function
+ *  @return WM_SUCCESS on success
+ *  @return -WM_FAIL on error
+ */
+int OSA_RemoveTickFunction(void (*func)(void));
+
+/* Init value for rand generator seed */
+extern uint32_t wm_rand_seed;
+
+/** This function initialize the seed for rand generator
+ *  @return a uint32_t random numer
+ */
+static inline void OSA_Srand(uint32_t seed)
+{
+    wm_rand_seed = seed;
+}
+
+/** This function generate a random number
+ *  @return a uint32_t random numer
+ */
+static inline uint32_t OSA_Rand()
+{
+    if (wm_rand_seed == 0xFFFFFFFFU)
+        OSA_Srand(OSA_TimeGetMsec());
+    wm_rand_seed = (uint32_t)((((uint64_t)wm_rand_seed * 279470273UL) % 4294967291UL) & 0xFFFFFFFFUL);
+    return wm_rand_seed;
+}
+
+/** This function generate a random number in a range
+ *  @param [in] low  range low
+ *  @param [in] high range high
+ *  @return a uint32_t random numer
+ */
+static inline uint32_t OSA_RandRange(uint32_t low, uint32_t high)
+{
+    uint32_t tmp;
+    if (low == high)
+        return low;
+    if (low > high)
+    {
+        tmp  = low;
+        low  = high;
+        high = tmp;
+    }
+    return (low + OSA_Rand() % (high - low));
+}
+
+void OSA_DumpThreadInfo(char *name);
+
+/** Suspend the given thread
+ *
+ * - The function OSA_ThreadSelfComplete() will \b permanently suspend the
+ * given thread. Passing NULL will suspend the current thread. This
+ * function never returns.
+ * - The thread continues to consume system resources. To delete the thread
+ * the function OSA_TaskDestroy() needs to be called separately.
+ *
+ * @param[in] taskHandle Pointer to thread handle
+ */
+void OSA_ThreadSelfComplete(osa_task_handle_t taskHandle);
+
+/** Return the number of messages stored in queue.
+ *
+ * @param[in] msgqHandle Pointer to handle of the queue to be queried.
+ *
+ * @returns Number of items in the queue
+ */
+uint32_t OSA_MsgQWaiting(osa_msgq_handle_t msgqHandle);
+
+#endif /* ! _OSA_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/slist.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/slist.h
new file mode 100644
index 0000000000..65e6914a0f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/slist.h
@@ -0,0 +1,174 @@
+ /* Copyright (c) 2023, Michael Becker (michael.f.becker@gmail.com)
+ *  Copyright 2023-2024 NXP
+ *  Source Code:
+ *  https://github.com/michaelbecker/freertos-addons
+ *
+ *  Project Page:
+ *  http://michaelbecker.github.io/freertos-addons/
+ *
+ *  On-line Documentation:
+ *  http://michaelbecker.github.io/freertos-addons/docs/html/index.html
+ *
+ *  MIT License
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files
+ *  (the "Software"), to deal in the Software without restriction, including
+ *  without limitation the rights to use, copy, modify, merge, publish,
+ *  distribute, sublicense, and/or sell copies of the Software, and to
+ *  permit persons to whom the Software is furnished to do so,subject to the
+ *  following conditions:
+ *
+ *  + The above copyright notice and this permission notice shall be included
+ *    in all copies or substantial portions of the Software.
+ *  + Credit is appreciated, but not required, if you find this project
+ *    useful enough to include in your application, product, device, etc.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ *  OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ *  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ *  CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ *  TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ *  SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+/*!\file slist.h
+ *\brief This file is a part of the FreeRTOS Add-ons project.
+ */
+
+#ifndef SLIST_H_
+#define SLIST_H_
+
+/**
+ *  The singly linked list structure.
+ *
+ *  This is designed to be embedded within your data
+ *  structure(s).
+ *
+ *  These lists offer the smallest storage overhead (one pointer per item),
+ *  but many operations may take O(n) time.
+ */
+typedef struct SlNode_t_
+{
+    /**
+     *  A pointer to ourselves.
+     */
+    struct SlNode_t_ *Next;
+
+} SlNode_t;
+
+/**
+ *  Macro to initialize a list head.
+ *
+ *  @param _head A pointer to the list head.
+ */
+#define SlInitHead(_head) (_head)->Next = NULL;
+
+/**
+ *  Add a node to the list head.
+ *  Runs in O(1) time.
+ *
+ *  @param _head A pointer to the existing list head.
+ *  @param _node A pointer to the node you are adding.
+ */
+#define SlAddNodeToHead(_head, _node) SlInsertNodeAfter(_head, _node)
+
+/**
+ *  Add a node to the list tail.
+ *  Runs in O(n) time.
+ *
+ *  @param Head A pointer to the existing list head.
+ *  @param Node A pointer to the node you are adding.
+ */
+void SlAddNodeToTail(SlNode_t *Head, SlNode_t *Node);
+
+/**
+ *  Removes the node from the list head.
+ *  Runs in O(1) time.
+ *
+ *  @param Head A pointer to the existing list head.
+ *  @return The node removed, or NULL for an empty list.
+ */
+SlNode_t *SlRemoveNodeFromHead(SlNode_t *Head);
+
+/**
+ *  Removes the node from the list tail.
+ *  Runs in O(n) time.
+ *
+ *  @param Head A pointer to the existing list head.
+ *  @return The node removed, or NULL for an empty list.
+ */
+SlNode_t *SlRemoveNodeFromTail(SlNode_t *Head);
+
+/**
+ *  Check if the list is empty.
+ *
+ *  @param _head A pointer to the existing list head.
+ *  @return true if the list is empty, false otherwise.
+ */
+#define SlIsListEmpty(_head) ((_head)->Next == NULL)
+
+/**
+ *  Inserts a new node into the list right after the marker element.
+ *  Runs in O(1) time.
+ *
+ *  @param Marker The node you are inserting after. Cannot be NULL.
+ *  @param Node The node you are inserting. Cannot be NULL.
+ */
+void SlInsertNodeAfter(SlNode_t *Marker, SlNode_t *Node);
+
+/**
+ *  Inserts a new node into the list right before the marker element.
+ *  Runs in O(n) time.
+ *
+ *  @param Head Pointer to the list head.
+ *  @param Marker Node you are inserting before. Cannot be NULL.
+ *  @param Node The node you are inserting. Cannot be NULL.
+ */
+void SlInsertNodeBefore(SlNode_t *Head, SlNode_t *Marker, SlNode_t *Node);
+
+/**
+ *  Removes a node from the list.
+ *  Runs in O(n) time worst case.
+ *
+ *  @param Head Pointer to the list head.
+ *  @param Node The node you are removing.
+ */
+void SlRemoveNode(SlNode_t *Head, SlNode_t *Node);
+
+/**
+ *  Given here in case you do not have an equivalent macro.
+ *  @param _type The structure type.
+ *  @param _field The name of the field you want the offset to.
+ *  @returns The offset into _type where _field starts, in bytes.
+ */
+#ifndef OFFSET_OF
+#define OFFSET_OF(_type, _field) ((size_t) & ((_type *)0)->_field)
+#endif
+
+/**
+ *  Given here in case you do not have an equivalent macro.
+ *  @param _address The real address of the _field you have.
+ *  @param _type The structure type.
+ *  @param _field The name of the field you want the offset to.
+ *  @returns A typed pointer to the structure containing the _field
+ *  at _address.
+ */
+#ifndef CONTAINING_RECORD
+#define CONTAINING_RECORD(_address, _type, _field) ((_type *)((unsigned char *)(_address)-OFFSET_OF(_type, _field)))
+#endif
+
+/**
+ *  Macro to ease walking through all of the nodes in a list.
+ *  Runs in O(n) time.
+ *
+ *  This will work for an empty list.
+ *
+ *  @param _head A pointer to the list head. Cannot be NULL.
+ *  @param _node An SlNode_t pointer that you need to define before calling
+ *                  this macro.
+ */
+#define SlForEachNode(_head, _node) for ((_node) = (_head)->Next; (_node) != NULL; (_node) = (_node)->Next)
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/stack_simple.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/stack_simple.h
new file mode 100644
index 0000000000..08ac59c305
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/port/osa/stack_simple.h
@@ -0,0 +1,100 @@
+/*
+ *  Copyright (c) 2023, Michael Becker (michael.f.becker@gmail.com)
+ *  Copyright 2023-2024 NXP
+ */
+/*!\file stack_simple.h
+ *\brief This file is part of the FreeRTOS Add-ons project.
+ */
+
+/*
+ *  Source Code:
+ *  https://github.com/michaelbecker/freertos-addons
+ *
+ *  Project Page:
+ *  http://michaelbecker.github.io/freertos-addons/
+ *
+ *  On-line Documentation:
+ *  http://michaelbecker.github.io/freertos-addons/docs/html/index.html
+ *
+ *  MIT License
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files
+ *  (the "Software"), to deal in the Software without restriction, including
+ *  without limitation the rights to use, copy, modify, merge, publish,
+ *  distribute, sublicense, and/or sell copies of the Software, and to
+ *  permit persons to whom the Software is furnished to do so,subject to the
+ *  following conditions:
+ *
+ *  + The above copyright notice and this permission notice shall be included
+ *    in all copies or substantial portions of the Software.
+ *  + Credit is appreciated, but not required, if you find this project
+ *    useful enough to include in your application, product, device, etc.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ *  OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ *  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ *  CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ *  TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ *  SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef STACK_H_
+#define STACK_H_
+
+#include "slist.h"
+
+/**
+ *  The stack structure, we leverage low overhead singly linked lists here.
+ */
+typedef struct Stack_t_
+{
+    /**
+     *  How many items are in the stack.
+     */
+    int Count;
+
+    /**
+     *  The head of the stack.
+     */
+    SlNode_t Head;
+
+} Stack_t;
+
+/**
+ *  Initialize a Stack structure you provide.
+ *
+ *  @param Stack Pointer to your stack structure.
+ */
+void InitStack(Stack_t *Stack);
+
+/**
+ *  Push an item onto the stack.
+ *
+ *  Note that you have to have embedded an SListNode inside your data
+ *  structure.
+ *
+ *  @param Stack Pointer to your stack structure.
+ *  @param Node The SListNode you want on the stack.
+ */
+void PushOnStack(Stack_t *Stack, SlNode_t *Node);
+
+/**
+ *  Pop an item off the stack.
+ *
+ *  Note that you have to have embedded an SListNode inside your data
+ *  structure.
+ *
+ *  @param Stack Pointer to your stack structure.
+ *  @return An SListNode from the stack, or NULL if it's empty.
+ */
+SlNode_t *PopOffStack(Stack_t *Stack);
+
+/**
+ *  @return True if the stack is empty, false otherwise.
+ */
+#define IsStackEmpty(_stack) ((_stack)->Count == 0)
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifi_cal_data_ext.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifi_cal_data_ext.h
new file mode 100644
index 0000000000..4938049364
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifi_cal_data_ext.h
@@ -0,0 +1,257 @@
+/** @file wifi_cal_data_ext.h
+ *
+ *  @brief  This file contains the cal data
+ */
+/*
+ *  Copyright 2021, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _WIFI_CAL_DATA_H_
+#define _WIFI_CAL_DATA_H_
+
+#if defined(SD8978)
+/* Following cal data is specific to IW416 QFN A1 chips */
+#if CONFIG_WLAN_CALDATA_1ANT
+const uint8_t int_cal_data[] = {
+    0x01, 0x00, 0x0E, 0x00, 0x64, 0x01, 0x00, 0x20, 0x77, 0x0E, 0x00, 0x00, 0x00, 0x20, 0x01, 0x01, 0x20, 0x00, 0xA0,
+    0x02, 0xBE, 0x19, 0x00, 0x3F, 0x00, 0x10, 0x00, 0x02, 0x58, 0x81, 0x02, 0x00, 0x00, 0x3E, 0x01, 0x00, 0x00, 0x36,
+    0x00, 0x3C, 0x22, 0x4B, 0x00, 0x00, 0x00, 0x5C, 0xFF, 0xFF, 0x06, 0x00, 0x05, 0x11, 0x62, 0x03, 0xFF, 0xFF, 0x6B,
+    0x6B, 0x05, 0x17, 0x5F, 0x43, 0xFF, 0xFF, 0x76, 0x76, 0x05, 0x14, 0x57, 0x47, 0xFF, 0xFF, 0x54, 0x54, 0x05, 0x16,
+    0x5B, 0x4B, 0xFF, 0xFF, 0x6E, 0x6E, 0x05, 0x15, 0x62, 0x4F, 0xFF, 0xFF, 0x72, 0x72, 0x05, 0x13, 0x4B, 0x53, 0xFF,
+    0xFF, 0x54, 0x54, 0x00, 0x6C, 0x92, 0x4D, 0x00, 0x00, 0x00, 0xC8, 0xFF, 0xF1, 0x0C, 0x00, 0x01, 0xA5, 0xFF, 0xFF,
+    0x00, 0x06, 0x10, 0x5F, 0x01, 0x93, 0xFF, 0xFF, 0x40, 0x10, 0x10, 0x5F, 0x01, 0x9F, 0xFF, 0xFF, 0x44, 0x30, 0x10,
+    0x5F, 0x01, 0x97, 0xFF, 0xFF, 0x48, 0x78, 0x10, 0x5F, 0x01, 0x92, 0xFF, 0xFF, 0x4C, 0x9D, 0x10, 0x5F, 0x01, 0x92,
+    0xFF, 0xFF, 0x50, 0x50, 0x10, 0x5F, 0x40, 0x0A, 0xFF, 0xFF, 0x00, 0x06, 0x10, 0x5F, 0x40, 0x1C, 0xFF, 0xFF, 0x40,
+    0x10, 0x10, 0x5F, 0x40, 0x1C, 0xFF, 0xFF, 0x44, 0x30, 0x10, 0x5F, 0x40, 0x1C, 0xFF, 0xFF, 0x48, 0x78, 0x10, 0x5F,
+    0x40, 0x1E, 0xFF, 0xFF, 0x4C, 0x9D, 0x10, 0x5F, 0x40, 0x1C, 0xFF, 0xFF, 0x50, 0x50, 0x10, 0x5F, 0x00, 0x24, 0xDE,
+    0x49, 0x00, 0x00, 0x00, 0xEC, 0xFF, 0xFF, 0x06, 0x00, 0x03, 0xFF, 0x04, 0x05, 0x43, 0xFF, 0x08, 0x09, 0x47, 0xFF,
+    0x08, 0x09, 0x4B, 0xFF, 0x06, 0x07, 0x4F, 0xFF, 0x06, 0x07, 0x53, 0xFF, 0x06, 0x07, 0x00, 0x44, 0x06, 0x5A, 0x00,
+    0x00, 0x01, 0x30, 0x00, 0x07, 0x01, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
+    0xFF, 0xFF, 0x00, 0x22, 0x00, 0x08, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00,
+    0x08, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
+    0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x18, 0x8C, 0x53, 0x00, 0x00, 0x01, 0x48, 0x39, 0x54, 0xDC, 0x66, 0xBC,
+    0x58, 0x44, 0xD0, 0xBE, 0x5D, 0x2F, 0x1B, 0x41, 0x1A, 0xB8, 0x52, 0x00, 0x1C, 0x9B, 0x37, 0xFF, 0xFF, 0xFF, 0xFF,
+    0x02, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x2D, 0xC6, 0xC0, 0x33, 0x44, 0x55, 0x66, 0x00, 0xF0, 0x11,
+    0x22};
+#else
+const uint8_t int_cal_data[] = {0x00};
+#endif
+#endif
+
+#if defined(SD8987)
+const uint8_t int_cal_data[] = {0x00};
+#endif
+
+#if defined(SD8801)
+const uint8_t int_cal_data[] = {0x00};
+#endif
+
+#if defined(SD9177)
+#if CONFIG_WLAN_CALDATA_2ANT_DIVERSITY
+/*Antenna Diversity*/
+const uint8_t int_cal_data[] = {
+    0x01, 0x00, 0x0F, 0x00, 0x6C, 0x01, 0x00, 0x20, 0x99, 0x0F, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF, 0x40, 0x00, 0x77,
+    0x00, 0x27, 0x07, 0x00, 0x00, 0x00, 0x10, 0x00, 0x03, 0xE8, 0x88, 0x02, 0x00, 0x00, 0x3F, 0x01, 0x00, 0x00, 0x71,
+    0x00, 0x2C, 0x9A, 0x4B, 0x00, 0x00, 0x00, 0x4C, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0xC6, 0xC6, 0x03, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0xDB, 0xDB, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0xE1, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDD,
+    0xDD, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8C, 0xE4, 0x61, 0x00, 0x00, 0x00, 0xD8, 0xFF, 0xF1, 0x08, 0x00, 0x00,
+    0x05, 0x01, 0x25, 0xFB, 0x6E, 0x20, 0x21, 0xC4, 0x40, 0x5B, 0xE8, 0xCB, 0x22, 0x78, 0x6F, 0x00, 0x0B, 0x01, 0x27,
+    0xFB, 0xDE, 0x3C, 0x22, 0xC4, 0xB0, 0x7B, 0xF0, 0xCB, 0x32, 0x8C, 0x77, 0x44, 0x28, 0x01, 0x10, 0xFB, 0x3E, 0x30,
+    0x24, 0xC3, 0xF0, 0x4B, 0xE4, 0xCA, 0xE2, 0x30, 0x67, 0x44, 0x38, 0x01, 0x0F, 0xFC, 0x1E, 0x68, 0x25, 0xC4, 0xB0,
+    0x7F, 0xF2, 0xCB, 0x32, 0x54, 0x70, 0x48, 0x6C, 0x01, 0x37, 0xFB, 0x6E, 0x38, 0x25, 0xC3, 0xF0, 0x4F, 0xE6, 0xCA,
+    0xB2, 0x34, 0x68, 0x48, 0x84, 0x01, 0x36, 0xFC, 0x6E, 0x7C, 0x26, 0xC4, 0xF0, 0x93, 0xF7, 0xCB, 0x02, 0x68, 0x75,
+    0x4C, 0x99, 0x01, 0x3B, 0xFE, 0x1E, 0xE8, 0x26, 0xC6, 0x80, 0xF8, 0x12, 0xCA, 0xE2, 0x90, 0x89, 0x4C, 0xA5, 0x01,
+    0x3F, 0xFE, 0x4E, 0xF4, 0x27, 0xC6, 0x50, 0xFC, 0x15, 0xCA, 0x92, 0x78, 0x83, 0x00, 0x1C, 0xFD, 0x62, 0x00, 0x00,
+    0x00, 0xF4, 0xFF, 0xFF, 0x04, 0x00, 0x03, 0xF0, 0xFC, 0x3F, 0x47, 0xF0, 0xFC, 0x3F, 0x4B, 0xF0, 0xFC, 0x3F, 0x4F,
+    0xF0, 0xFC, 0x3F, 0x00, 0x18, 0x5C, 0x53, 0x00, 0x00, 0x01, 0x0C, 0x39, 0x06, 0x75, 0x0D, 0xBC, 0x55, 0x1F, 0x97,
+    0x3D, 0x16, 0x3D, 0x21, 0x41, 0x49, 0xAE, 0xBC, 0x00, 0x44, 0xCE, 0x5A, 0x00, 0x00, 0x01, 0x50, 0x00, 0x07, 0x01,
+    0x04, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0xFF, 0xFF, 0x00, 0x22, 0x00, 0x01,
+    0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00,
+    0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01,
+    0x00, 0x1C, 0x00, 0x37, 0xFF, 0xFF, 0xFF, 0xFF, 0x04, 0x04, 0x77, 0x01, 0x00, 0x00, 0x00, 0x09, 0x00, 0x2D, 0xC6,
+    0xC0, 0xDA, 0x21, 0x12, 0x14, 0x00, 0x00, 0xC0, 0x95,
+};
+
+#else
+const uint8_t int_cal_data[] = {
+    0x01, 0x00, 0x0F, 0x00, 0xD0, 0x01, 0x00, 0x20, 0x98, 0x0F, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF, 0x40, 0x00, 0x77,
+    0x00, 0x28, 0x07, 0x00, 0x00, 0x00, 0x10, 0x00, 0x03, 0xE8, 0x88, 0x02, 0x00, 0x00, 0x3F, 0x01, 0x00, 0x00, 0x71,
+    0x00, 0x2C, 0x9A, 0x4B, 0x00, 0x00, 0x00, 0x4C, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0xC6, 0xC6, 0x03, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0xDB, 0xDB, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0xE1, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDD,
+    0xDD, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8C, 0x7D, 0x61, 0x00, 0x00, 0x00, 0xD8, 0xFF, 0xF1, 0x08, 0x00, 0x00,
+    0x05, 0x01, 0x00, 0x39, 0x7D, 0x9C, 0x23, 0x02, 0x6F, 0xE3, 0xC8, 0x0A, 0xC2, 0x0C, 0x55, 0x00, 0x0B, 0x01, 0x0E,
+    0x39, 0x5D, 0x9C, 0x25, 0x02, 0x6F, 0xDF, 0xC8, 0x0A, 0xB2, 0x0C, 0x55, 0x44, 0x28, 0x01, 0xCE, 0x3A, 0x7D, 0xF0,
+    0x27, 0x03, 0x40, 0x1B, 0xD7, 0x0A, 0xF2, 0x1C, 0x60, 0x44, 0x38, 0x01, 0xD4, 0x3A, 0xBE, 0x10, 0x29, 0x03, 0x70,
+    0x27, 0xDB, 0x0A, 0xB2, 0x1C, 0x61, 0x48, 0x6C, 0x01, 0xD1, 0x3A, 0x4E, 0x00, 0x29, 0x03, 0x00, 0x07, 0xD3, 0x0B,
+    0x12, 0x10, 0x5F, 0x48, 0x84, 0x01, 0xD2, 0x3A, 0x8E, 0x00, 0x2A, 0x03, 0x20, 0x0F, 0xD6, 0x0A, 0xB2, 0x0C, 0x5E,
+    0x4C, 0x99, 0x01, 0xD6, 0x3A, 0x2D, 0xE0, 0x2A, 0x02, 0xCF, 0xFB, 0xD0, 0x0A, 0x51, 0xF4, 0x58, 0x4C, 0xA5, 0x01,
+    0xD3, 0x3A, 0x0D, 0xE0, 0x2B, 0x02, 0x9F, 0xEF, 0xCF, 0x09, 0xF1, 0xE4, 0x54, 0x00, 0x1C, 0x55, 0x62, 0x00, 0x00,
+    0x00, 0xF4, 0xFF, 0xFF, 0x04, 0x00, 0x03, 0xF0, 0x84, 0x21, 0x47, 0xF0, 0x84, 0x21, 0x4B, 0xF0, 0x84, 0x21, 0x4F,
+    0xF0, 0x84, 0x21, 0x00, 0x18, 0x2D, 0x53, 0x00, 0x00, 0x01, 0x0C, 0x39, 0x1B, 0x30, 0x73, 0xBC, 0x15, 0x18, 0x2B,
+    0xBE, 0x82, 0x8F, 0x5C, 0x41, 0x4C, 0xCC, 0xCD, 0x00, 0x70, 0xDD, 0x5A, 0x00, 0x00, 0x01, 0x7C, 0x00, 0x07, 0x02,
+    0x04, 0x00, 0x07, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x02, 0x00, 0x03,
+    0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x05, 0x00, 0x03, 0x00, 0x03, 0x00,
+    0x03, 0x00, 0x05, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03,
+    0xFF, 0xFF, 0x00, 0x20, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00,
+    0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05,
+    0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x10, 0xE4, 0x63, 0x00, 0x00, 0x01, 0x8C, 0xF1, 0x11, 0x00, 0x01, 0x00,
+    0x00, 0x0D, 0x0D, 0x00, 0x1C, 0x07, 0x37, 0x00, 0x00, 0x01, 0xA8, 0x07, 0x0D, 0x77, 0x01, 0x00, 0x00, 0x00, 0x28,
+    0x00, 0x01, 0xC2, 0x00, 0x23, 0xBB, 0x5E, 0x71, 0x00, 0x00, 0xDC, 0xFE, 0x00, 0x18, 0x60, 0x68, 0x00, 0x00, 0x01,
+    0xC0, 0x00, 0x74, 0x00, 0x01, 0xFE, 0xBB, 0x5E, 0x70, 0xDC, 0xFE, 0x23, 0xFF, 0x00, 0x00, 0x00, 0x68, 0x00, 0x10,
+    0x87, 0x64, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x04, 0x00, 0x01, 0x00, 0x04, 0x00, 0x01};
+#endif
+#endif
+
+#ifdef RW610
+#ifdef FRDMRW610
+#define CONFIG_WLAN_CALDATA_1ANT 1
+#endif
+#if CONFIG_WLAN_CALDATA_1ANT
+#ifdef FRDMRW610
+/*one ANT*/
+const uint8_t cal_data_rw610[] = {
+    0x01, 0x00, 0x0F, 0x00, 0xB8, 0x01, 0x00, 0x20, 0xDD, 0x0F, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF,
+    0x40, 0x00, 0x7C, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x26, 0x79, 0x02, 0x00,
+    0x00, 0x3F, 0x01, 0x00, 0x00, 0x12, 0x00, 0x8C, 0x74, 0x61, 0x00, 0x00, 0x00, 0xAC, 0x23, 0xF0,
+    0x08, 0x00, 0x00, 0x05, 0x01, 0x10, 0x3B, 0x6E, 0x20, 0x23, 0x04, 0x70, 0x63, 0xE8, 0x0C, 0x42,
+    0x88, 0x74, 0x00, 0x0B, 0x01, 0x1A, 0x3B, 0x4E, 0x18, 0x25, 0x04, 0x40, 0x57, 0xE5, 0x0C, 0x12,
+    0x80, 0x71, 0x44, 0x28, 0x01, 0x10, 0x3A, 0x7E, 0x00, 0x27, 0x03, 0x60, 0x1F, 0xD7, 0x0A, 0xC2,
+    0x14, 0x61, 0x44, 0x38, 0x01, 0x23, 0x3A, 0x7E, 0x00, 0x29, 0x03, 0x50, 0x1F, 0xD8, 0x0A, 0xA2,
+    0x10, 0x5F, 0x48, 0x6C, 0x01, 0x14, 0x3A, 0x8E, 0x04, 0x2A, 0x03, 0x60, 0x23, 0xD9, 0x0A, 0xD2,
+    0x14, 0x61, 0x48, 0x84, 0x01, 0xF7, 0x3A, 0x6E, 0x00, 0x2C, 0x03, 0x40, 0x1B, 0xD7, 0x0A, 0x82,
+    0x0C, 0x5F, 0x4C, 0x99, 0x01, 0xFF, 0x3B, 0x3E, 0x30, 0x2C, 0x03, 0xE0, 0x47, 0xE3, 0x0A, 0xC2,
+    0x28, 0x66, 0x4C, 0xA5, 0x01, 0x00, 0x3B, 0x3E, 0x30, 0x2D, 0x03, 0xE0, 0x4B, 0xE3, 0x0A, 0xB2,
+    0x28, 0x66, 0x00, 0x70, 0xF2, 0x5A, 0x00, 0x00, 0x01, 0x1C, 0x00, 0x07, 0x02, 0x04, 0x00, 0x0F,
+    0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x02, 0x00, 0x06,
+    0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x06, 0x00, 0x05,
+    0x00, 0x05, 0x00, 0x05, 0x00, 0x06, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05,
+    0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0xFF, 0xFF, 0x00, 0x20, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+    0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+    0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+    0x00, 0x06, 0x00, 0x10, 0x49, 0x63, 0x00, 0x00, 0x01, 0x2C, 0xF1, 0x11, 0x00, 0x01, 0x00, 0x00,
+    0x0D, 0x08, 0x00, 0x2C, 0x85, 0x4B, 0x00, 0x00, 0x01, 0x58, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0xD6,
+    0xDA, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDB, 0xDD, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6,
+    0xD9, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6, 0xD9, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C,
+    0x56, 0x62, 0x00, 0x00, 0x01, 0x74, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0x01, 0x8C, 0x63, 0x44, 0x02,
+    0x94, 0xA5, 0x48, 0x03, 0x9C, 0xE7, 0x4C, 0x04, 0x21, 0x08, 0x00, 0x1C, 0xD2, 0x37, 0x00, 0x00,
+    0x01, 0x90, 0x05, 0x04, 0x7C, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x2D, 0xC6, 0xC0, 0xFF, 0xFF,
+    0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x18, 0xDF, 0x68, 0x00, 0x00, 0x01, 0xA8, 0x00, 0x00,
+    0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+    0x8D, 0x64, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00};
+#else
+/*one ANT*/
+const uint8_t cal_data_rw610[] = {
+    0x01, 0x00, 0x0F, 0x00, 0xB8, 0x01, 0x00, 0x20, 0xDF, 0x0F, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF,
+    0x40, 0x00, 0x7C, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x26, 0x79, 0x02, 0x00,
+    0x00, 0x3F, 0x01, 0x00, 0x00, 0x12, 0x00, 0x8C, 0xCF, 0x61, 0x00, 0x00, 0x00, 0xAC, 0x23, 0xF0,
+    0x08, 0x00, 0x00, 0x05, 0x01, 0x0E, 0x3C, 0x1E, 0x4C, 0x1E, 0x05, 0x00, 0x8B, 0xF2, 0x0C, 0x72,
+    0xAC, 0x7D, 0x00, 0x0B, 0x01, 0x0B, 0x3B, 0xCE, 0x38, 0x20, 0x04, 0xC0, 0x77, 0xEE, 0x0C, 0x52,
+    0x9C, 0x79, 0x44, 0x28, 0x01, 0x04, 0x3A, 0xBE, 0x10, 0x22, 0x03, 0xB0, 0x33, 0xDC, 0x0B, 0x32,
+    0x2C, 0x66, 0x44, 0x38, 0x01, 0x00, 0x3A, 0x7E, 0x00, 0x24, 0x03, 0x50, 0x1F, 0xD8, 0x0A, 0xB2,
+    0x14, 0x61, 0x48, 0x6C, 0x01, 0x1E, 0x3B, 0xBE, 0x50, 0x25, 0x04, 0x80, 0x6F, 0xEC, 0x0B, 0xB2,
+    0x58, 0x72, 0x48, 0x84, 0x01, 0x0D, 0x3B, 0x4E, 0x34, 0x26, 0x04, 0x30, 0x57, 0xE6, 0x0B, 0x72,
+    0x48, 0x6D, 0x4C, 0x99, 0x01, 0x09, 0x3B, 0xCE, 0x54, 0x27, 0x04, 0x80, 0x73, 0xEE, 0x0B, 0x52,
+    0x4C, 0x6F, 0x4C, 0xA5, 0x01, 0x01, 0x3B, 0x2E, 0x28, 0x28, 0x03, 0xD0, 0x47, 0xE3, 0x0A, 0xB2,
+    0x28, 0x65, 0x00, 0x70, 0x92, 0x5A, 0x00, 0x00, 0x01, 0x1C, 0x00, 0x07, 0x02, 0x04, 0x00, 0x0F,
+    0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x02, 0x00, 0x02,
+    0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01,
+    0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01,
+    0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0xFF, 0xFF, 0x00, 0x20, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02,
+    0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02,
+    0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02,
+    0x00, 0x02, 0x00, 0x10, 0x49, 0x63, 0x00, 0x00, 0x01, 0x2C, 0xF1, 0x11, 0x00, 0x01, 0x00, 0x00,
+    0x0D, 0x08, 0x00, 0x2C, 0x85, 0x4B, 0x00, 0x00, 0x01, 0x58, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0xD6,
+    0xDA, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDB, 0xDD, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6,
+    0xD9, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6, 0xD9, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C,
+    0x93, 0x62, 0x00, 0x00, 0x01, 0x74, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0x01, 0x8C, 0x63, 0x44, 0x01,
+    0x8C, 0x63, 0x48, 0x02, 0x94, 0xA5, 0x4C, 0x03, 0x9C, 0xE7, 0x00, 0x1C, 0xD3, 0x37, 0x00, 0x00,
+    0x01, 0x90, 0x04, 0x04, 0x7C, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x2D, 0xC6, 0xC0, 0xFF, 0xFF,
+    0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x18, 0xDF, 0x68, 0x00, 0x00, 0x01, 0xA8, 0x00, 0x00,
+    0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+    0x8D, 0x64, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00};
+#endif /*FRDMRW610*/
+#else
+#if CONFIG_WLAN_CALDATA_3ANT_DIVERSITY
+const uint8_t cal_data_rw610[] = {
+    0x01, 0x00, 0x0F, 0x00, 0xA8, 0x01, 0x00, 0x20, 0x46, 0x0F, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF, 0x40, 0x00, 0x72,
+    0x00, 0x22, 0x00, 0x00, 0xA3, 0x00, 0x00, 0x00, 0x04, 0x26, 0x79, 0x02, 0x00, 0x00, 0x3F, 0x01, 0x00, 0x00, 0x12,
+    0x00, 0x8C, 0x93, 0x61, 0x00, 0x00, 0x00, 0xAC, 0xFF, 0xF0, 0x08, 0x00, 0x00, 0x05, 0x01, 0x15, 0x3B, 0xAE, 0x30,
+    0x20, 0x04, 0xC0, 0x73, 0xED, 0x0C, 0x12, 0x84, 0x7B, 0x00, 0x0B, 0x01, 0x18, 0x3B, 0xCE, 0x38, 0x21, 0x04, 0xE0,
+    0x7B, 0xEE, 0x0C, 0x12, 0x88, 0x7A, 0x44, 0x28, 0x01, 0x1E, 0x3B, 0x8E, 0x40, 0x21, 0x04, 0x30, 0x5B, 0xE8, 0x0B,
+    0x82, 0x50, 0x6B, 0x44, 0x38, 0x01, 0x2D, 0x3B, 0xAE, 0x4C, 0x23, 0x04, 0xB0, 0x6F, 0xEC, 0x0B, 0x72, 0x9C, 0x79,
+    0x48, 0x6C, 0x01, 0x15, 0x3C, 0x1E, 0x68, 0x24, 0x04, 0xC0, 0x7F, 0xF0, 0x0B, 0xA2, 0x60, 0x75, 0x48, 0x84, 0x01,
+    0x2D, 0x3B, 0x8E, 0x44, 0x24, 0x04, 0x80, 0x67, 0xE9, 0x0B, 0x52, 0x7C, 0x77, 0x4C, 0x99, 0x01, 0x22, 0x3B, 0xFE,
+    0x60, 0x24, 0x04, 0xA0, 0x7B, 0xF0, 0x0A, 0xD2, 0x50, 0x72, 0x4C, 0xA5, 0x01, 0x0F, 0x3B, 0x4E, 0x30, 0x25, 0x03,
+    0xE0, 0x47, 0xE4, 0x0A, 0x92, 0x28, 0x68, 0x00, 0x70, 0x7A, 0x5A, 0x00, 0x00, 0x01, 0x1C, 0x00, 0x07, 0x02, 0x04,
+    0x00, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x0C, 0xFF, 0xFF, 0x00, 0x02, 0x00, 0x02, 0x00,
+    0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01,
+    0x00, 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0xFF,
+    0xFF, 0x00, 0x20, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02,
+    0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00,
+    0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x10, 0x49, 0x63, 0x00, 0x00, 0x01, 0x2C, 0xF1, 0x11, 0x00, 0x01, 0x00, 0x00,
+    0x0D, 0x08, 0x00, 0x2C, 0x49, 0x4B, 0x00, 0x00, 0x01, 0x58, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0xE4, 0xEA, 0x03, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0xE0, 0xE2, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDD, 0xE0, 0x4B, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0xDB, 0xDA, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xF3, 0x62, 0x00, 0x00, 0x01, 0x74, 0xFF, 0xFF, 0x04,
+    0x00, 0x00, 0x02, 0x90, 0xA4, 0x44, 0x04, 0xA5, 0x29, 0x48, 0x04, 0x20, 0xE8, 0x4C, 0x04, 0x21, 0x08, 0x00, 0x1C,
+    0x0A, 0x37, 0x00, 0x00, 0x01, 0x90, 0x03, 0x04, 0x72, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x2D, 0xC6, 0xC0, 0xDA,
+    0x01, 0x07, 0x97, 0x00, 0xF0, 0xC0, 0x95, 0x00, 0x18, 0x27, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, 0x65, 0x00, 0x00, 0x01,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00};
+#elif (CONFIG_WLAN_CALDATA_1ANT_WITH_DIVERSITY)
+const uint8_t cal_data_rw610[] = {
+    0x01, 0x00, 0x0F, 0x00, 0xB8, 0x01, 0x00, 0x20, 0xE1, 0x0F, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF,
+    0x40, 0x00, 0x7B, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x26, 0x79, 0x02, 0x00,
+    0x00, 0x3F, 0x01, 0x00, 0x00, 0x12, 0x00, 0x8C, 0x29, 0x61, 0x00, 0x00, 0x00, 0xAC, 0x23, 0xF0,
+    0x08, 0x00, 0x00, 0x05, 0x01, 0x09, 0x3B, 0x5E, 0x1C, 0x1F, 0x04, 0x50, 0x5B, 0xE6, 0x0C, 0x32,
+    0x80, 0x72, 0x00, 0x0B, 0x01, 0x0C, 0x3B, 0x5E, 0x1C, 0x21, 0x04, 0x50, 0x5B, 0xE7, 0x0C, 0x32,
+    0x84, 0x72, 0x44, 0x28, 0x01, 0x09, 0x3A, 0x1D, 0xE8, 0x23, 0x03, 0x00, 0x0B, 0xD2, 0x0A, 0x82,
+    0x04, 0x5C, 0x44, 0x38, 0x01, 0x12, 0x3A, 0x2D, 0xEC, 0x25, 0x03, 0x10, 0x0F, 0xD3, 0x0A, 0x62,
+    0x04, 0x5C, 0x48, 0x6C, 0x01, 0x0D, 0x3A, 0x9E, 0x08, 0x26, 0x03, 0x60, 0x23, 0xDA, 0x0A, 0xD2,
+    0x18, 0x61, 0x48, 0x84, 0x01, 0x2A, 0x3B, 0x5E, 0x38, 0x27, 0x04, 0x20, 0x57, 0xE6, 0x0B, 0x42,
+    0x40, 0x6B, 0x4C, 0x99, 0x01, 0x2A, 0x3C, 0x2E, 0x68, 0x28, 0x04, 0xD0, 0x87, 0xF3, 0x0B, 0x52,
+    0x5C, 0x73, 0x4C, 0xA5, 0x01, 0x33, 0x3B, 0xCE, 0x50, 0x29, 0x04, 0x60, 0x6F, 0xED, 0x0A, 0xF2,
+    0x40, 0x6C, 0x00, 0x70, 0xDA, 0x5A, 0x00, 0x00, 0x01, 0x1C, 0x00, 0x07, 0x02, 0x04, 0x00, 0x0F,
+    0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x0C, 0xFF, 0xFF, 0x00, 0x02, 0x00, 0x06,
+    0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x06, 0x00, 0x05,
+    0x00, 0x05, 0x00, 0x05, 0x00, 0x06, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x05,
+    0x00, 0x05, 0x00, 0x05, 0x00, 0x05, 0xFF, 0xFF, 0x00, 0x20, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+    0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+    0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+    0x00, 0x06, 0x00, 0x10, 0x49, 0x63, 0x00, 0x00, 0x01, 0x2C, 0xF1, 0x11, 0x00, 0x01, 0x00, 0x00,
+    0x0D, 0x08, 0x00, 0x2C, 0x85, 0x4B, 0x00, 0x00, 0x01, 0x58, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0xD6,
+    0xDA, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDB, 0xDD, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6,
+    0xD9, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6, 0xD9, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C,
+    0xB0, 0x62, 0x00, 0x00, 0x01, 0x74, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0x02, 0x10, 0x84, 0x44, 0x02,
+    0x94, 0xA5, 0x48, 0x03, 0x9C, 0xE7, 0x4C, 0x04, 0x21, 0x08, 0x00, 0x1C, 0xD3, 0x37, 0x00, 0x00,
+    0x01, 0x90, 0x05, 0x04, 0x7B, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x2D, 0xC6, 0xC0, 0xFF, 0xFF,
+    0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x18, 0xDF, 0x68, 0x00, 0x00, 0x01, 0xA8, 0x00, 0x00,
+    0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+    0x7D, 0x64, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00,};
+#else /*TWO ANT*/
+const uint8_t cal_data_rw610[] = {
+    0x01, 0x00, 0x0F, 0x00, 0x38, 0x01, 0x00, 0x20, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF,
+    0x40, 0x00, 0x7B, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x26, 0x79, 0x02, 0x00,
+    0x00, 0x3F, 0x01, 0x00, 0x00, 0x12, 0x00, 0x8C, 0xA2, 0x61, 0x00, 0x00, 0x00, 0xAC, 0x23, 0xF0,
+    0x08, 0x00, 0x00, 0x05, 0x01, 0x1B, 0x3C, 0x6E, 0x60, 0x1F, 0x05, 0x50, 0x9F, 0xF8, 0x0C, 0x72,
+    0xC0, 0x81, 0x00, 0x0B, 0x01, 0x17, 0x3C, 0x3E, 0x54, 0x21, 0x05, 0x30, 0x97, 0xF5, 0x0C, 0x62,
+    0xB4, 0x7F, 0x44, 0x28, 0x01, 0x03, 0x3A, 0xAE, 0x08, 0x23, 0x03, 0x90, 0x2B, 0xDB, 0x0B, 0x12,
+    0x28, 0x65, 0x44, 0x38, 0x01, 0x02, 0x3A, 0x5D, 0xFC, 0x25, 0x03, 0x40, 0x1B, 0xD6, 0x0A, 0x92,
+    0x10, 0x5F, 0x48, 0x6C, 0x01, 0x1D, 0x3B, 0xBE, 0x50, 0x26, 0x04, 0x80, 0x6F, 0xEC, 0x0B, 0xC2,
+    0x5C, 0x72, 0x48, 0x84, 0x01, 0x0E, 0x3B, 0x2E, 0x2C, 0x27, 0x04, 0x10, 0x4B, 0xE3, 0x0B, 0x62,
+    0x40, 0x6B, 0x4C, 0x99, 0x01, 0x05, 0x3B, 0xCE, 0x54, 0x28, 0x04, 0x80, 0x6F, 0xEE, 0x0B, 0x62,
+    0x50, 0x70, 0x4C, 0xA5, 0x01, 0xFF, 0x3B, 0x1E, 0x28, 0x28, 0x03, 0xD0, 0x47, 0xE3, 0x0A, 0xB2,
+    0x24, 0x65, 0x00, 0x10, 0xBF, 0x63, 0x00, 0x00, 0x00, 0xBC, 0xF1, 0x11, 0x00, 0x01, 0x00, 0x00,
+    0x08, 0x08, 0x00, 0x2C, 0xF6, 0x4B, 0x00, 0x00, 0x00, 0xE8, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0xD6,
+    0xDA, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDB, 0xDD, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6,
+    0xD9, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD6, 0xD9, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C,
+    0x03, 0x62, 0x00, 0x00, 0x01, 0x04, 0xFF, 0xFF, 0x04, 0x00, 0x00, 0x01, 0x8C, 0x63, 0x44, 0x01,
+    0x8C, 0x63, 0x48, 0x02, 0x94, 0xA5, 0x4C, 0x03, 0x9C, 0xE7, 0x00, 0x1C, 0x46, 0x37, 0x00, 0x00,
+    0x01, 0x20, 0x02, 0x04, 0x7B, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x2D, 0xC6, 0xC0, 0xFF, 0xFF,
+    0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x18, 0x8C, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+    0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,};
+#endif
+#endif
+#endif
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifi_config_default.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifi_config_default.h
new file mode 100644
index 0000000000..35764465c0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifi_config_default.h
@@ -0,0 +1,1339 @@
+ /*
+ *  Copyright 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file wifi_config_default.h
+ *\brief This file provides default macros for Wi-Fi.
+ */
+
+#if !defined WIFI_HDR_CONFIG_H
+#define WIFI_HDR_CONFIG_H
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you don't like!
+ */
+
+#include "wifi_config.h"
+
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+
+#if !defined CONFIG_WIFI_AUTO_POWER_SAVE
+#define CONFIG_WIFI_AUTO_POWER_SAVE 1
+#endif
+
+#if !defined CONFIG_WIFI_MAX_PRIO
+#define CONFIG_WIFI_MAX_PRIO (configMAX_PRIORITIES - 1)
+#endif
+
+#if !defined CONFIG_MAX_AP_ENTRIES
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_MAX_AP_ENTRIES 10
+#else
+#define CONFIG_MAX_AP_ENTRIES 30
+#endif
+#endif
+
+#if !defined CONFIG_5GHz_SUPPORT
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD9177)
+#define CONFIG_5GHz_SUPPORT 1
+#endif
+#endif
+
+#if defined(SD8801)
+#undef CONFIG_5GHz_SUPPORT
+#define CONFIG_5GHz_SUPPORT 0
+#endif
+
+#if !defined CONFIG_11AC
+#if defined(RW610) || defined(SD8987) || defined(SD9177)
+#define CONFIG_11AC 1
+#endif
+#endif
+
+#if CONFIG_11AC
+#if defined(SD8801) || defined(SD8978)
+#undef CONFIG_11AC
+#define CONFIG_11AC 0
+#endif
+#endif
+
+#if !defined CONFIG_11AX
+#if defined(RW610) || defined(SD9177)
+#define CONFIG_11AX CONFIG_11AC
+#endif
+#endif
+
+#if !CONFIG_11AC
+#undef CONFIG_11AX
+#define CONFIG_11AX 0
+#endif
+
+
+
+#if !defined CONFIG_11AX_TWT
+#if defined(RW610) || defined(SD9177)
+#define CONFIG_11AX_TWT CONFIG_11AX
+#endif
+#endif
+
+#if !CONFIG_11AX
+#undef CONFIG_11AX_TWT
+#define CONFIG_11AX_TWT 0
+#endif
+
+
+#if !CONFIG_11AX
+#undef CONFIG_SET_SU
+#define CONFIG_SET_SU 0
+#endif
+
+/* WMM options */
+#if !defined CONFIG_WMM
+#if defined(RW610)
+#define CONFIG_WMM 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WMM 0
+#endif
+#endif
+
+#if !defined CONFIG_SDIO_MULTI_PORT_RX_AGGR
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_SDIO_MULTI_PORT_RX_AGGR 1
+#endif
+#endif
+
+#if CONFIG_SDIO_MULTI_PORT_RX_AGGR
+#if defined(RW610)
+#undef CONFIG_SDIO_MULTI_PORT_RX_AGGR
+#define CONFIG_SDIO_MULTI_PORT_RX_AGGR 0
+#endif
+#endif
+
+#if !defined CONFIG_SDIO_MULTI_PORT_TX_AGGR
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_SDIO_MULTI_PORT_TX_AGGR CONFIG_WMM
+#endif
+#endif
+
+#if defined(RW610)
+#undef CONFIG_SDIO_MULTI_PORT_TX_AGGR
+#define CONFIG_SDIO_MULTI_PORT_TX_AGGR 0
+#endif
+
+#if !CONFIG_WMM
+#undef CONFIG_SDIO_MULTI_PORT_TX_AGGR
+#define CONFIG_SDIO_MULTI_PORT_TX_AGGR 0
+#endif
+
+/** Multi port aggregation packet limit */
+#if !defined CONFIG_SDIO_MP_AGGR_DEF_PKT_LIMIT
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_SDIO_MP_AGGR_DEF_PKT_LIMIT (4 + (CONFIG_WMM * 4))
+#endif
+#endif
+
+#if CONFIG_SDIO_MP_AGGR_DEF_PKT_LIMIT > 8
+#undef CONFIG_SDIO_MP_AGGR_DEF_PKT_LIMIT
+#if CONFIG_WMM && CONFIG_SDIO_MULTI_PORT_TX_AGGR
+#define CONFIG_SDIO_MP_AGGR_DEF_PKT_LIMIT 8
+#else
+#define CONFIG_SDIO_MP_AGGR_DEF_PKT_LIMIT 4
+#endif
+#endif
+
+
+#if !defined CONFIG_RF_TEST_MODE
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_RF_TEST_MODE 0
+#endif
+#endif
+
+#if !defined CONFIG_UNII4_BAND_SUPPORT
+#if defined(RW610)
+#define CONFIG_UNII4_BAND_SUPPORT 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD9177)
+#define CONFIG_UNII4_BAND_SUPPORT 0
+#endif
+#endif
+
+#if !CONFIG_5GHz_SUPPORT
+#undef CONFIG_UNII4_BAND_SUPPORT
+#define CONFIG_UNII4_BAND_SUPPORT 0
+#endif
+
+#if !defined CONFIG_COMPRESS_TX_PWTBL
+#if defined(RW610) || defined(SD9177)
+#define CONFIG_COMPRESS_TX_PWTBL 1
+#endif
+#endif
+
+#if CONFIG_COMPRESS_TX_PWTBL
+#if defined(SD8978) || defined(SD8987) || defined(SD8801)
+#undef CONFIG_COMPRESS_TX_PWTBL
+#define CONFIG_COMPRESS_TX_PWTBL 0
+#endif
+#endif
+
+#if !defined CONFIG_COMPRESS_RU_TX_PWTBL
+#if defined(SD9177) || defined(RW610)
+#define CONFIG_COMPRESS_RU_TX_PWTBL 1
+#endif
+#endif
+
+#if CONFIG_COMPRESS_RU_TX_PWTBL
+#if defined(SD8978) || defined(SD8987) || defined(SD8801)
+#undef CONFIG_COMPRESS_RU_TX_PWTBL
+#define CONFIG_COMPRESS_RU_TX_PWTBL 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_FEATURES
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_FEATURES 0
+#endif
+#endif
+
+#if CONFIG_WIFI_FEATURES
+#if defined(SD8801)
+#undef CONFIG_WIFI_FEATURES
+#define CONFIG_WIFI_FEATURES 0
+#endif
+#endif
+
+#if !defined CONFIG_OFFLOAD
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_OFFLOAD CONFIG_WIFI_FEATURES
+#endif
+#endif
+
+#if !CONFIG_WIFI_FEATURES
+#undef CONFIG_OFFLOAD
+#define CONFIG_OFFLOAD 0
+#endif
+
+#if !defined CONFIG_RW610_A1
+#if defined(RW610)
+#define CONFIG_RW610_A1 1
+#endif
+#endif
+
+#if !defined PRINTF_FLOAT_ENABLE
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define PRINTF_FLOAT_ENABLE 0
+#endif
+#endif
+
+#if !defined CONFIG_IMU_GDMA
+#if defined(RW610)
+#define CONFIG_IMU_GDMA 0
+#endif
+#endif
+
+#if !defined CONFIG_AMSDU_IN_AMPDU
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_AMSDU_IN_AMPDU 0
+#endif
+#endif
+
+#if !defined CONFIG_SCAN_WITH_RSSIFILTER
+#if defined(RW610)
+#define CONFIG_SCAN_WITH_RSSIFILTER 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_SCAN_WITH_RSSIFILTER 0
+#endif
+#endif
+
+/* WLAN white/black list opt */
+#if !defined CONFIG_UAP_STA_MAC_ADDR_FILTER
+#if defined(RW610)
+#define CONFIG_UAP_STA_MAC_ADDR_FILTER 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_UAP_STA_MAC_ADDR_FILTER 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_DTIM_PERIOD
+#if defined(RW610)
+#define CONFIG_WIFI_DTIM_PERIOD 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_DTIM_PERIOD 0
+#endif
+#endif
+
+#if !defined CONFIG_UART_INTERRUPT
+#if defined(RW610)
+#define CONFIG_UART_INTERRUPT 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_UART_INTERRUPT 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_MAX_CLIENTS_CNT
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_MAX_CLIENTS_CNT 1
+#endif
+#endif
+
+
+#if !defined CONFIG_WIFI_FRAG_THRESHOLD
+#if defined(RW610)
+#define CONFIG_WIFI_FRAG_THRESHOLD 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_FRAG_THRESHOLD 0
+#endif
+#endif
+
+#if !defined CONFIG_WMM_UAPSD
+#if defined(RW610)
+#define CONFIG_WMM_UAPSD 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WMM_UAPSD 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_GET_LOG
+#if defined(RW610)
+#define CONFIG_WIFI_GET_LOG 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_GET_LOG 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_TX_PER_TRACK
+#if defined(RW610)
+#define CONFIG_WIFI_TX_PER_TRACK 0
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_TX_PER_TRACK 0
+#endif
+#endif
+
+#if CONFIG_WIFI_TX_PER_TRACK
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#undef CONFIG_WIFI_TX_PER_TRACK
+#define CONFIG_WIFI_TX_PER_TRACK 0
+#endif
+#endif
+
+#if !defined CONFIG_POWER_MANAGER
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_POWER_MANAGER 0
+#endif
+#endif
+
+#if CONFIG_POWER_MANAGER
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#undef CONFIG_POWER_MANAGER
+#define CONFIG_POWER_MANAGER 0
+#endif
+#endif
+
+#if !defined CONFIG_CSI
+#if defined(RW610)
+#define CONFIG_CSI 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_CSI 0
+#endif
+#endif
+
+#if CONFIG_CSI
+#if defined(SD8801)
+#undef CONFIG_CSI
+#define CONFIG_CSI 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_RESET
+#if defined(RW610)
+#define CONFIG_WIFI_RESET 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_RESET 0
+#endif
+#endif
+
+#if CONFIG_WIFI_RESET
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#undef CONFIG_WIFI_RESET
+#define CONFIG_WIFI_RESET 0
+#endif
+#endif
+
+#if !defined CONFIG_NET_MONITOR
+#if defined(RW610)
+#define CONFIG_NET_MONITOR 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_NET_MONITOR 0
+#endif
+#endif
+
+#if CONFIG_NET_MONITOR
+#if defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#undef CONFIG_NET_MONITOR
+#define CONFIG_NET_MONITOR 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_MEM_ACCESS
+#if defined(RW610)
+#define CONFIG_WIFI_MEM_ACCESS 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_MEM_ACCESS 0
+#endif
+#endif
+
+#if CONFIG_WIFI_MEM_ACCESS
+#if defined(SD8801)
+#undef CONFIG_WIFI_MEM_ACCESS
+#define CONFIG_WIFI_MEM_ACCESS 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_REG_ACCESS
+#if defined(RW610)
+#define CONFIG_WIFI_REG_ACCESS 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_REG_ACCESS 0
+#endif
+#endif
+
+#if CONFIG_WIFI_REG_ACCESS
+#if defined(SD8801)
+#undef CONFIG_WIFI_REG_ACCESS
+#define CONFIG_WIFI_REG_ACCESS 0
+#endif
+#endif
+
+#if !defined CONFIG_ECSA
+#if defined(RW610)
+#define CONFIG_ECSA 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_ECSA 0
+#endif
+#endif
+
+#if !defined CONFIG_RX_ABORT_CFG
+#if defined(RW610)
+#define CONFIG_RX_ABORT_CFG 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_RX_ABORT_CFG 0
+#endif
+#endif
+
+#if !defined CONFIG_RX_ABORT_CFG_EXT
+#if defined(RW610)
+#define CONFIG_RX_ABORT_CFG_EXT 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_RX_ABORT_CFG_EXT 0
+#endif
+#endif
+
+#if !defined CONFIG_CCK_DESENSE_CFG
+#if defined(RW610)
+#define CONFIG_CCK_DESENSE_CFG 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_CCK_DESENSE_CFG 0
+#endif
+#endif
+
+#if !defined CONFIG_IPS
+#if defined(RW610)
+#define CONFIG_IPS 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_IPS 0
+#endif
+#endif
+
+#if !defined CONFIG_SUBSCRIBE_EVENT_SUPPORT
+#if defined(RW610)
+#define CONFIG_SUBSCRIBE_EVENT_SUPPORT 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_SUBSCRIBE_EVENT_SUPPORT 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_FORCE_RTS
+#if defined(RW610)
+#define CONFIG_WIFI_FORCE_RTS 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_FORCE_RTS 0
+#endif
+#endif
+
+#if !defined CONFIG_TX_AMPDU_PROT_MODE
+#if defined(RW610)
+#define CONFIG_TX_AMPDU_PROT_MODE 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_TX_AMPDU_PROT_MODE 0
+#endif
+#endif
+
+#if !defined CONFIG_TSP
+#if defined(RW610)
+#define CONFIG_TSP 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_TSP 0
+#endif
+#endif
+
+#if !defined CONFIG_TX_RX_HISTOGRAM
+#if defined(RW610)
+#define CONFIG_TX_RX_HISTOGRAM 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_TX_RX_HISTOGRAM 0
+#endif
+#endif
+
+#if !defined CONFIG_IPV6
+#define CONFIG_IPV6 0
+#endif
+
+#if !defined CONFIG_MAX_IPV6_ADDRESSES
+#define CONFIG_MAX_IPV6_ADDRESSES 0
+#endif
+
+#if !defined CONFIG_WIFI_CAPA
+#if defined(RW610)
+#define CONFIG_WIFI_CAPA 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_CAPA 0
+#endif
+#endif
+
+#if !defined CONFIG_ROAMING
+#if defined(RW610)
+#define CONFIG_ROAMING 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_ROAMING 0
+#endif
+#endif
+
+#if !defined CONFIG_CLOUD_KEEP_ALIVE
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_CLOUD_KEEP_ALIVE 0
+#endif
+#endif
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+#if defined(SD8801)
+#undef CONFIG_CLOUD_KEEP_ALIVE
+#define CONFIG_CLOUD_KEEP_ALIVE 0
+#endif
+#endif
+
+#if !defined CONFIG_TURBO_MODE
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_TURBO_MODE CONFIG_WMM
+#endif
+#endif
+
+#if CONFIG_TURBO_MODE
+#undef CONFIG_TURBO_MODE
+#define CONFIG_TURBO_MODE CONFIG_WMM
+#endif
+
+#if !defined CONFIG_AUTO_RECONNECT
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_AUTO_RECONNECT 0
+#endif
+#endif
+
+#if CONFIG_AUTO_RECONNECT
+#if defined(SD8801)
+#undef CONFIG_AUTO_RECONNECT
+#define CONFIG_AUTO_RECONNECT 0
+#endif
+#endif
+
+#if !defined CONFIG_EXT_SCAN_SUPPORT
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD9177)
+#define CONFIG_EXT_SCAN_SUPPORT 1
+#endif
+#endif
+
+#if CONFIG_EXT_SCAN_SUPPORT
+#if defined(SD8801)
+#undef CONFIG_EXT_SCAN_SUPPORT
+#define CONFIG_EXT_SCAN_SUPPORT 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_EU_CRYPTO
+#if defined(RW610)
+#define CONFIG_WIFI_EU_CRYPTO 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_EU_CRYPTO 0
+#endif
+#endif
+
+#if CONFIG_WIFI_EU_CRYPTO
+#if defined(SD8801)
+#undef CONFIG_WIFI_EU_CRYPTO
+#define CONFIG_WIFI_EU_CRYPTO 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_IND_DNLD
+#if defined(SD8978) || defined(SD8987) || defined(SD9177)
+#define CONFIG_WIFI_IND_DNLD 0
+#endif
+#endif
+
+#if CONFIG_WIFI_IND_DNLD
+#if defined(RW610) || defined(SD8801)
+#undef CONFIG_WIFI_IND_DNLD
+#define CONFIG_WIFI_IND_DNLD 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_IND_RESET
+#if defined(SD8978) || defined(SD8987) || defined(SD9177)
+#define CONFIG_WIFI_IND_RESET 0
+#endif
+#endif
+
+#if CONFIG_WIFI_IND_RESET
+#if defined(RW610) || defined(SD8801)
+#undef CONFIG_WIFI_IND_RESET
+#define CONFIG_WIFI_IND_RESET 0
+#endif
+#endif
+
+#if !defined CONFIG_HOST_SLEEP
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_HOST_SLEEP 0
+#endif
+#endif
+
+#if !defined CONFIG_DRIVER_FIPS
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_DRIVER_FIPS 0
+#endif
+#endif
+
+#if CONFIG_DRIVER_FIPS
+#define CONFIG_FIPS
+#endif
+
+#if !CONFIG_DRIVER_FIPS
+#undef CONFIG_FIPS
+#endif
+
+#if !defined CONFIG_11K
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_11K 0
+#endif
+#endif
+
+#if CONFIG_11AX
+#undef CONFIG_11K
+#define CONFIG_11K CONFIG_11AX
+#endif
+
+#if !defined CONFIG_11V
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_11V 0
+#endif
+#endif
+
+#if CONFIG_11AX
+#undef CONFIG_11V
+#define CONFIG_11V CONFIG_11AX
+#endif
+
+#if !defined CONFIG_TCP_ACK_ENH
+#if defined(SD9177)
+#define CONFIG_TCP_ACK_ENH 1
+#endif
+#endif
+
+#if CONFIG_TCP_ACK_ENH
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801)
+#undef CONFIG_TCP_ACK_ENH
+#define CONFIG_TCP_ACK_ENH
+#endif
+#endif
+
+#if !defined CONFIG_FW_VDLL
+#if defined(SD9177)
+#define CONFIG_FW_VDLL 1
+#endif
+#endif
+
+#if !CONFIG_FW_VDLL
+#if defined(SD9177)
+#undef CONFIG_FW_VDLL
+#define CONFIG_FW_VDLL 1
+#endif
+#endif
+
+/*
+ * Config options for wpa supplicant
+ */
+#if !defined CONFIG_WPA_SUPP
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP 0
+#endif
+#endif
+
+#if !defined CONFIG_DRIVER_MBO
+#if defined(RW610) || defined(SD9177)
+#define CONFIG_DRIVER_MBO (CONFIG_11AX && !CONFIG_WPA_SUPP)
+#endif
+#endif
+
+#if CONFIG_DRIVER_MBO
+#if !CONFIG_11AX || CONFIG_WPA_SUPP
+#undef CONFIG_DRIVER_MBO
+#define CONFIG_DRIVER_MBO 0
+#endif
+#endif
+
+#if CONFIG_DRIVER_MBO
+#undef CONFIG_MBO
+#endif
+
+#if !CONFIG_DRIVER_MBO
+#define CONFIG_MBO
+#endif
+
+#if !defined CONFIG_DRIVER_OWE
+#if defined(RW610)
+#define CONFIG_DRIVER_OWE 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_DRIVER_OWE 0
+#endif
+#endif
+
+#if CONFIG_DRIVER_OWE
+#if defined(RW610) || defined(SD8801)
+#undef CONFIG_DRIVER_OWE
+#define CONFIG_DRIVER_OWE CONFIG_WPA_SUPP
+#endif
+#endif
+
+#if CONFIG_DRIVER_OWE
+#define CONFIG_OWE
+#endif
+
+#if !CONFIG_DRIVER_OWE
+#undef CONFIG_OWE
+#endif
+
+#if !defined CONFIG_11R
+#if defined(RW610)
+#define CONFIG_11R 1
+#elif defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_11R 0
+#endif
+#endif
+
+#if CONFIG_11R
+#if defined(RW610) || defined(SD8801) || defined(SD9177)
+#undef CONFIG_11R
+#define CONFIG_11R CONFIG_WPA_SUPP
+#endif
+#endif
+
+#if !defined CONFIG_WPA_SUPP_WPS
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP_WPS 0
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP_WPS
+#undef CONFIG_WPA_SUPP_WPS
+#define CONFIG_WPA_SUPP_WPS CONFIG_WPA_SUPP
+#endif
+
+#if !defined CONFIG_WPA_SUPP_WPA3
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP_WPA3 CONFIG_WPA_SUPP
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP_WPA3
+#undef CONFIG_WPA_SUPP_WPA3
+#define CONFIG_WPA_SUPP_WPA3 CONFIG_WPA_SUPP
+#endif
+
+#if !defined CONFIG_WPA_SUPP_DPP
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP_DPP 0
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP_DPP
+#if defined(SD8978) || defined(SD8987) || defined(SD8801)
+#undef CONFIG_WPA_SUPP_DPP
+#define CONFIG_WPA_SUPP_DPP 0
+#endif
+#endif
+
+#if !defined CONFIG_WPA_SUPP_DPP2
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP_DPP2 0
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP_DPP2
+#if defined(SD8978) || defined(SD8987) || defined(SD8801)
+#undef CONFIG_WPA_SUPP_DPP2
+#define CONFIG_WPA_SUPP_DPP2 CONFIG_WPA_SUPP_DPP
+#endif
+#endif
+
+#if !defined CONFIG_WPA_SUPP_DPP3
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP_DPP3 0
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP_DPP3
+#if defined(SD8978) || defined(SD8987) || defined(SD8801)
+#undef CONFIG_WPA_SUPP_DPP3
+#define CONFIG_WPA_SUPP_DPP3 (CONFIG_WPA_SUPP_DPP && CONFIG_WPA_SUPP_DPP2)
+#endif
+#endif
+
+
+
+#if !CONFIG_WPA_SUPP_DPP
+#undef CONFIG_RX_CHAN_INFO
+#define CONFIG_RX_CHAN_INFO 0
+#endif
+
+
+
+#if !CONFIG_WPA_SUPP_DPP
+#undef CONFIG_TXPD_RXPD_V3
+#define CONFIG_TXPD_RXPD_V3 0
+#endif
+
+#if !defined CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE 0
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#undef CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#define CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE CONFIG_WPA_SUPP
+#endif
+
+#if !defined CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE 0
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+#undef CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+#define CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#endif
+
+#if !defined CONFIG_EAP_TLS
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_TLS 0
+#endif
+#endif
+
+#if !CONFIG_WPA2_ENTP
+#if CONFIG_EAP_TLS
+#undef CONFIG_EAP_TLS
+#define CONFIG_EAP_TLS (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#endif
+#endif
+
+#if !defined CONFIG_EAP_PEAP
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_PEAP 0
+#endif
+#endif
+
+#if CONFIG_EAP_PEAP
+#undef CONFIG_EAP_PEAP
+#define CONFIG_EAP_PEAP (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#endif
+
+#if !defined CONFIG_EAP_TTLS
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_TTLS 0
+#endif
+#endif
+
+#if CONFIG_EAP_TTLS
+#undef CONFIG_EAP_TTLS
+#define CONFIG_EAP_TTLS (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#endif
+
+#if !defined CONFIG_EAP_FAST
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_FAST 0
+#endif
+#endif
+
+#if CONFIG_EAP_FAST
+#undef CONFIG_EAP_FAST
+#define CONFIG_EAP_FAST (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#endif
+
+#if !defined CONFIG_EAP_SIM
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_SIM 0
+#endif
+#endif
+
+#if CONFIG_EAP_SIM
+#undef CONFIG_EAP_SIM
+#define CONFIG_EAP_SIM (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#endif
+
+#if !defined CONFIG_EAP_AKA
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_AKA 0
+#endif
+#endif
+
+#if CONFIG_EAP_AKA
+#undef CONFIG_EAP_AKA
+#define CONFIG_EAP_AKA (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#endif
+
+#if !defined CONFIG_EAP_AKA_PRIME
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_AKA_PRIME 0
+#endif
+#endif
+
+#if CONFIG_EAP_AKA_PRIME
+#undef CONFIG_EAP_AKA_PRIME
+#define CONFIG_EAP_AKA_PRIME (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE && CONFIG_EAP_AKA)
+#endif
+
+#if !defined CONFIG_EAP_MSCHAPV2
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_MSCHAPV2 (CONFIG_EAP_PEAP || CONFIG_EAP_TTLS || CONFIG_EAP_FAST)
+#endif
+#endif
+
+#if CONFIG_EAP_MSCHAPV2
+#undef CONFIG_EAP_MSCHAPV2
+#define CONFIG_EAP_MSCHAPV2 \
+    (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE && (CONFIG_EAP_PEAP || CONFIG_EAP_TTLS || CONFIG_EAP_FAST))
+#endif
+
+#if !defined CONFIG_EAP_GTC
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_EAP_GTC (CONFIG_EAP_PEAP || CONFIG_EAP_TTLS || CONFIG_EAP_FAST)
+#endif
+#endif
+
+#if CONFIG_EAP_GTC
+#undef CONFIG_EAP_GTC
+#define CONFIG_EAP_GTC \
+    (CONFIG_WPA_SUPP && CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE && (CONFIG_EAP_PEAP || CONFIG_EAP_TTLS || CONFIG_EAP_FAST))
+#endif
+
+#if !defined CONFIG_WPS2
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPS2 0
+#endif
+#endif
+
+#if CONFIG_WPS2
+#undef CONFIG_WPS2
+#define CONFIG_WPS2 !CONFIG_WPA_SUPP
+#endif
+
+#if !defined CONFIG_WPA2_ENTP
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WPA2_ENTP 0
+#endif
+#endif
+
+#if CONFIG_WPA2_ENTP
+#undef CONFIG_WPA2_ENTP
+#define CONFIG_WPA2_ENTP !CONFIG_WPA_SUPP
+#endif
+
+#if !defined CONFIG_PEAP_MSCHAPV2
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_PEAP_MSCHAPV2 0
+#endif
+#endif
+
+#if CONFIG_PEAP_MSCHAPV2
+#undef CONFIG_PEAP_MSCHAPV2
+#define CONFIG_PEAP_MSCHAPV2 !CONFIG_WPA_SUPP
+#endif
+
+#if !defined CONFIG_WIFI_USB_FILE_ACCESS
+#if defined(RW610) || defined(SD8978) || defined(SD8987) || defined(SD8801) || defined(SD9177)
+#define CONFIG_WIFI_USB_FILE_ACCESS 0
+#endif
+#endif
+
+#if !defined CONFIG_MMSF
+#if defined(RW610)
+#define CONFIG_MMSF 1
+#endif
+#endif
+
+#if !defined CONFIG_COEX_DUTY_CYCLE
+#if defined(RW610)
+#define CONFIG_COEX_DUTY_CYCLE 1
+#endif
+#endif
+
+/** If define CONFIG_TX_RX_ZERO_COPY 1, please make sure
+ *  #define PBUF_POOL_BUFSIZE 1752
+ *  in lwipopts.h
+ */
+#if !defined CONFIG_TX_RX_ZERO_COPY
+#if defined(RW610)
+#define CONFIG_TX_RX_ZERO_COPY 0
+#endif
+#endif
+
+#if !defined CONFIG_WIFI_CLOCKSYNC
+#if defined(RW610)
+#define CONFIG_WIFI_CLOCKSYNC 1
+#endif
+#endif
+
+#if !defined CONFIG_INACTIVITY_TIMEOUT_EXT
+#if defined(RW610)
+#define CONFIG_INACTIVITY_TIMEOUT_EXT 1
+#endif
+#endif
+
+#if !defined CONFIG_AUTO_NULL_TX
+#if defined(RW610)
+#define CONFIG_AUTO_NULL_TX 1
+#endif
+#endif
+
+#if !defined CONFIG_EXTERNAL_COEX_PTA
+#if defined(RW610)
+#define CONFIG_EXTERNAL_COEX_PTA 1
+#endif
+#endif
+
+#if !defined CONFIG_FW_VDLLV2
+#if defined(RW610)
+#define CONFIG_FW_VDLLV2 1
+#endif
+#endif
+
+/** Wi-Fi NXP internal macros */
+#define LWIPERF_REVERSE_MODE      1
+#define CONFIG_MLAN_WMSDK         1
+#define CONFIG_11N                1
+#define STA_SUPPORT               1
+#define UAP_SUPPORT               1
+#define WPA                       1
+#define KEY_MATERIAL_WEP          1
+#define KEY_PARAM_SET_V2          1
+#define ENABLE_802_11W            1
+#define ENABLE_GCMP_SUPPORT       1
+#define CONFIG_STA_AMPDU_RX       1
+#define CONFIG_STA_AMPDU_TX       1
+#define CONFIG_ENABLE_AMSDU_RX    1
+#define CONFIG_UAP_AMPDU_TX       1
+#define CONFIG_UAP_AMPDU_RX       1
+#define CONFIG_WIFIDRIVER_PS_LOCK 1
+#define CONFIG_WNM_PS             1
+#define CONFIG_SCAN_CHANNEL_GAP   1
+#define CONFIG_COMBO_SCAN         1
+#define CONFIG_BG_SCAN            1
+#define CONFIG_HOST_MLME          1
+#define UAP_HOST_MLME             1
+
+#if CONFIG_WNM_PS
+#if defined(RW610)
+#undef CONFIG_WNM_PS
+#define CONFIG_WNM_PS 0
+#endif
+#endif
+
+#if !defined CONFIG_SEND_HOSTCMD
+#define CONFIG_SEND_HOSTCMD 1
+#endif
+
+/* Logs */
+#if !defined CONFIG_ENABLE_ERROR_LOGS
+#define CONFIG_ENABLE_ERROR_LOGS 1
+#endif
+
+#if !defined CONFIG_ENABLE_WARNING_LOGS
+#define CONFIG_ENABLE_WARNING_LOGS 1
+#endif
+
+/* WLCMGR debug */
+#if !defined CONFIG_WLCMGR_DEBUG
+#define CONFIG_WLCMGR_DEBUG 0
+#endif
+
+/*
+ * Wifi extra debug options
+ */
+#if !defined CONFIG_WIFI_EXTRA_DEBUG
+#define CONFIG_WIFI_EXTRA_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_EVENTS_DEBUG
+#define CONFIG_WIFI_EVENTS_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_CMD_RESP_DEBUG
+#define CONFIG_WIFI_CMD_RESP_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_PKT_DEBUG
+#define CONFIG_WIFI_PKT_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_SCAN_DEBUG
+#define CONFIG_WIFI_SCAN_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_IO_INFO_DUMP
+#define CONFIG_WIFI_IO_INFO_DUMP 0
+#endif
+
+#if !defined CONFIG_WIFI_IO_DEBUG
+#define CONFIG_WIFI_IO_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_IO_DUMP
+#define CONFIG_WIFI_IO_DUMP 0
+#endif
+
+#if !defined CONFIG_WIFI_MEM_DEBUG
+#define CONFIG_WIFI_MEM_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_AMPDU_DEBUG
+#define CONFIG_WIFI_AMPDU_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_TIMER_DEBUG
+#define CONFIG_WIFI_TIMER_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_SDIO_DEBUG
+#define CONFIG_WIFI_SDIO_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_FW_DEBUG
+#define CONFIG_WIFI_FW_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_UAP_DEBUG
+#define CONFIG_WIFI_UAP_DEBUG 0
+#endif
+
+#if !defined CONFIG_WPS_DEBUG
+#define CONFIG_WPS_DEBUG 0
+#endif
+
+#if !defined CONFIG_FW_VDLL_DEBUG
+#define CONFIG_FW_VDLL_DEBUG 0
+#endif
+
+#if !defined CONFIG_DHCP_SERVER_DEBUG
+#define CONFIG_DHCP_SERVER_DEBUG 0
+#endif
+
+#if !defined CONFIG_WIFI_SDIO_DEBUG
+#define CONFIG_WIFI_SDIO_DEBUG 0
+#endif
+
+#if !defined CONFIG_FWDNLD_IO_DEBUG
+#define CONFIG_FWDNLD_IO_DEBUG 0
+#endif
+
+/*
+ * Heap debug options
+ */
+#if !defined CONFIG_HEAP_DEBUG
+#define CONFIG_HEAP_DEBUG 0
+#endif
+
+#if !defined CONFIG_HEAP_STAT
+#define CONFIG_HEAP_STAT 0
+#endif
+
+/*
+ * wpa supplicant debug options
+ */
+#if !defined CONFIG_WPA_SUPP_DEBUG_LEVEL
+#define CONFIG_WPA_SUPP_DEBUG_LEVEL 6
+#endif
+
+#if !defined CONFIG_SUPP_DEBUG
+#define CONFIG_SUPP_DEBUG 0
+#endif
+
+/*
+* Wi-Fi SLIM feature options
+*/
+
+#ifndef CONFIG_WIFI_SLIM_ROAM
+#define CONFIG_WIFI_SLIM_ROAM 0
+#endif
+
+#ifndef CONFIG_WIFI_SLIM_STA
+#define CONFIG_WIFI_SLIM_STA 0
+#endif
+
+#ifndef CONFIG_WIFI_SLIM_UAP
+#define CONFIG_WIFI_SLIM_UAP 0
+#endif
+
+#ifndef CONFIG_WIFI_SLIM_DBG
+#define CONFIG_WIFI_SLIM_DBG 0
+#endif
+
+#if CONFIG_WIFI_SLIM_ROAM
+
+#if CONFIG_ROAMING
+#undef CONFIG_ROAMING
+#define CONFIG_ROAMING 0
+#endif
+
+#if CONFIG_11K
+#undef CONFIG_11K
+#define CONFIG_11K 0
+#endif
+
+#if CONFIG_11V
+#undef CONFIG_11V
+#define CONFIG_11V 0
+#endif
+
+#if CONFIG_11R
+#undef CONFIG_11R
+#define CONFIG_11R 0
+#endif
+
+#endif /* CONFIG_WIFI_SLIM_ROAM */
+
+#if CONFIG_WIFI_SLIM_STA
+
+#if CONFIG_5GHz_SUPPORT
+#undef CONFIG_5GHz_SUPPORT
+#define CONFIG_5GHz_SUPPORT 0
+#endif
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+#undef CONFIG_CLOUD_KEEP_ALIVE
+#define CONFIG_CLOUD_KEEP_ALIVE 0
+#endif
+
+#if CONFIG_WIFI_EU_CRYPTO
+#undef CONFIG_WIFI_EU_CRYPTO
+#define CONFIG_WIFI_EU_CRYPTO 0
+#endif
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+#undef CONFIG_TX_AMPDU_PROT_MODE
+#define CONFIG_TX_AMPDU_PROT_MODE 0
+#endif
+
+#if CONFIG_WNM_PS
+#undef CONFIG_WNM_PS
+#define CONFIG_WNM_PS 0
+#endif
+
+#if CONFIG_TURBO_MODE
+#undef CONFIG_TURBO_MODE
+#define CONFIG_TURBO_MODE 0
+#endif
+
+#if CONFIG_AUTO_RECONNECT
+#undef CONFIG_AUTO_RECONNECT
+#define CONFIG_AUTO_RECONNECT 0
+#endif
+
+#if CONFIG_DRIVER_OWE
+#undef CONFIG_DRIVER_OWE
+#define CONFIG_DRIVER_OWE 0
+#endif
+
+#ifdef CONFIG_OWE
+#undef CONFIG_OWE
+#endif
+
+#if CONFIG_WIFI_FORCE_RTS
+#undef CONFIG_WIFI_FORCE_RTS
+#define CONFIG_WIFI_FORCE_RTS 0
+#endif
+
+#if CONFIG_WIFI_FRAG_THRESHOLD
+#undef CONFIG_WIFI_FRAG_THRESHOLD
+#define CONFIG_WIFI_FRAG_THRESHOLD 0
+#endif
+
+#if CONFIG_COMBO_SCAN
+#undef CONFIG_COMBO_SCAN
+#define CONFIG_COMBO_SCAN 0
+#endif
+
+#if CONFIG_SCAN_CHANNEL_GAP
+#undef CONFIG_SCAN_CHANNEL_GAP
+#define CONFIG_SCAN_CHANNEL_GAP 0
+#endif
+
+#if CONFIG_MAX_AP_ENTRIES
+#undef CONFIG_MAX_AP_ENTRIES
+#define CONFIG_MAX_AP_ENTRIES 5
+#endif
+
+#endif /* CONFIG_WIFI_SLIM_ROAM */
+
+#if CONFIG_WIFI_SLIM_UAP
+
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+#undef CONFIG_UAP_STA_MAC_ADDR_FILTER
+#define CONFIG_UAP_STA_MAC_ADDR_FILTER 0
+#endif
+
+#if CONFIG_WIFI_MAX_CLIENTS_CNT
+#undef CONFIG_WIFI_MAX_CLIENTS_CNT
+#define CONFIG_WIFI_MAX_CLIENTS_CNT 0
+#endif
+
+#if CONFIG_WIFI_CAPA
+#undef CONFIG_WIFI_CAPA
+#define CONFIG_WIFI_CAPA 0
+#endif
+
+#endif /* CONFIG_WIFI_SLIM_ROAM */
+
+#if CONFIG_WIFI_SLIM_DBG
+
+#if CONFIG_ENABLE_ERROR_LOGS
+#undef CONFIG_ENABLE_ERROR_LOGS
+#define CONFIG_ENABLE_ERROR_LOGS 0
+#endif
+
+#if CONFIG_ENABLE_WARNING_LOGS
+#undef CONFIG_ENABLE_WARNING_LOGS
+#define CONFIG_ENABLE_WARNING_LOGS 0
+#endif
+
+#if CONFIG_SEND_HOSTCMD
+#undef CONFIG_SEND_HOSTCMD
+#define CONFIG_SEND_HOSTCMD 0
+#endif
+
+#endif /* CONFIG_WIFI_SLIM_ROAM */
+
+#else
+#error "Please define supported Wi-Fi module"
+#endif
+
+#endif /* WIFI_HDR_CONFIG_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi-decl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi-decl.h
new file mode 100644
index 0000000000..11b3494858
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi-decl.h
@@ -0,0 +1,1905 @@
+/*
+ *  Copyright 2008-2022, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file wifi-decl.h
+ *\brief This file provieds Wi-Fi structure declarations
+ */
+#ifndef __WIFI_DECL_H__
+#define __WIFI_DECL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <wm_utils.h>
+#include <mlan_decl.h>
+#include <mlan_ioctl.h>
+#include <wifi_events.h>
+
+/* fixme: remove these after complete integration with mlan */
+#define MLAN_MAC_ADDR_LENGTH (6U)
+/** Version string buffer length */
+#define MLAN_MAX_VER_STR_LEN 128
+
+#define WIFI_MAX_CHANNEL_NUM 42
+
+#define PMK_BIN_LEN 32
+#define PMK_HEX_LEN 64
+
+#define MOD_GROUPS 7
+
+#if CONFIG_DRIVER_OWE
+/** The open AP in OWE transmition Mode */
+#define OWE_TRANS_MODE_OPEN 1U
+/** The security AP in OWE trsnsition Mode */
+#define OWE_TRANS_MODE_OWE 2U
+#endif
+
+#if CONFIG_WIFI_CAPA
+#define WIFI_SUPPORT_11AX   (1 << 3)
+#define WIFI_SUPPORT_11AC   (1 << 2)
+#define WIFI_SUPPORT_11N    (1 << 1)
+#define WIFI_SUPPORT_LEGACY (1 << 0)
+#endif
+
+#if 0
+/** channel_field.flags */
+#define CHANNEL_FLAGS_TURBO                   0x0010
+#define CHANNEL_FLAGS_CCK                     0x0020
+#define CHANNEL_FLAGS_OFDM                    0x0040
+#define CHANNEL_FLAGS_2GHZ                    0x0080
+#define CHANNEL_FLAGS_5GHZ                    0x0100
+#define CHANNEL_FLAGS_ONLY_PASSIVSCAN_ALLOW   0x0200
+#define CHANNEL_FLAGS_DYNAMIC_CCK_OFDM        0x0400
+#define CHANNEL_FLAGS_GFSK                    0x0800
+PACK_START struct channel_field {
+    t_u16 frequency;
+    t_u16 flags;
+} PACK_END;
+
+/** mcs_field.known */
+#define MCS_KNOWN_BANDWIDTH                   0x01
+#define MCS_KNOWN_MCS_INDEX_KNOWN             0x02
+#define MCS_KNOWN_GUARD_INTERVAL              0x04
+#define MCS_KNOWN_HT_FORMAT                   0x08
+#define MCS_KNOWN_FEC_TYPE                    0x10
+#define MCS_KNOWN_STBC_KNOWN                  0x20
+#define MCS_KNOWN_NESS_KNOWN                  0x40
+#define MCS_KNOWN_NESS_DATA                   0x80
+/** bandwidth */
+#define RX_BW_20                              0
+#define RX_BW_40                              1
+#define RX_BW_20L                             2
+#define RX_BW_20U                             3
+/** mcs_field.flags
+The flags field is any combination of the following:
+0x03    bandwidth - 0: 20, 1: 40, 2: 20L, 3: 20U
+0x04    guard interval - 0: long GI, 1: short GI
+0x08    HT format - 0: mixed, 1: greenfield
+0x10    FEC type - 0: BCC, 1: LDPC
+0x60    Number of STBC streams
+0x80    Ness - bit 0 (LSB) of Number of extension spatial streams */
+PACK_START struct mcs_field {
+    t_u8 known;
+    t_u8 flags;
+    t_u8 mcs;
+} PACK_END;
+
+/** radiotap_body.flags */
+#define RADIOTAP_FLAGS_DURING_CFG             0x01
+#define RADIOTAP_FLAGS_SHORT_PREAMBLE         0x02
+#define RADIOTAP_FLAGS_WEP_ENCRYPTION         0x04
+#define RADIOTAP_FLAGS_WITH_FRAGMENT          0x08
+#define RADIOTAP_FLAGS_INCLUDE_FCS            0x10
+#define RADIOTAP_FLAGS_PAD_BTW_HEADER_PAYLOAD 0x20
+#define RADIOTAP_FLAGS_FAILED_FCS_CHECK       0x40
+#define RADIOTAP_FLAGS_USE_SGI_HT             0x80
+PACK_START struct radiotap_body {
+    t_u64 timestamp;
+    t_u8 flags;
+    t_u8 rate;
+    struct channel_field channel;
+    t_s8 antenna_signal;
+    t_s8 antenna_noise;
+    t_u8 antenna;
+    struct mcs_field mcs;
+} PACK_END;
+
+typedef PACK_START struct _radiotap_header {
+    struct ieee80211_radiotap_header hdr;
+    struct radiotap_body body;
+} PACK_END radiotap_header_t;
+#endif
+
+/** Station information structure */
+typedef struct
+{
+    /** MAC address buffer */
+    t_u8 mac[MLAN_MAC_ADDR_LENGTH];
+    /**
+     * Power management status
+     * 0 = active (not in power save)
+     * 1 = in power save status
+     */
+    t_u8 power_mgmt_status;
+    /** RSSI: dBm */
+    t_s8 rssi;
+} wifi_sta_info_t;
+
+/** Channel list structure */
+typedef PACK_START struct _wifi_scan_chan_list_t
+{
+    /** Number of channels */
+    uint8_t num_of_chan;
+    /** Channel number */
+    uint8_t chan_number[MLAN_MAX_CHANNEL];
+} PACK_END wifi_scan_chan_list_t;
+
+/**
+ *  Note: This is variable length structure. The size of array mac_list is
+ *  equal to count. The caller of the API which returns this structure does
+ *  not need to separately free the array mac_list. It only needs to free
+ *  the sta_list_t object after use.
+ */
+typedef struct
+{
+    /** Count */
+    int count;
+    /*
+     * Variable length array. Max size is MAX_NUM_CLIENTS.
+     */
+    /* wifi_sta_info_t *list; */
+} wifi_sta_list_t;
+
+/** BSS type : STA */
+#define BSS_TYPE_STA 0U
+/** BSS type : UAP */
+#define BSS_TYPE_UAP 1U
+
+#define UAP_DEFAULT_CHANNEL       0
+#define UAP_DEFAULT_BANDWIDTH     2
+#define UAP_DEFAULT_BEACON_PERIOD 100
+#define UAP_DEFAULT_HIDDEN_SSID   0
+
+enum wifi_bss_security
+{
+    WIFI_SECURITY_NONE = 0,
+    WIFI_SECURITY_WEP_STATIC,
+    WIFI_SECURITY_WEP_DYNAMIC,
+    WIFI_SECURITY_WPA,
+    WIFI_SECURITY_WPA2,
+};
+
+enum wifi_bss_features
+{
+    WIFI_BSS_FEATURE_WMM = 0,
+    WIFI_BSS_FEATURE_WPS = 1,
+};
+
+struct wifi_message
+{
+    uint16_t event;
+    enum wifi_event_reason reason;
+    void *data;
+};
+
+
+/* Wlan Cipher structure */
+typedef struct
+{
+    /** 1 bit value can be set for none */
+    uint16_t none : 1;
+    /** 1 bit value can be set for wep40 */
+    uint16_t wep40 : 1;
+    /** 1 bit value can be set for wep104 */
+    uint16_t wep104 : 1;
+    /** 1 bit value can be set for tkip */
+    uint16_t tkip : 1;
+    /** 1 bit valuecan be set for ccmp */
+    uint16_t ccmp : 1;
+    /**  1 bit valuecan be set for aes 128 cmac */
+    uint16_t aes_128_cmac : 1;
+    /** 1 bit value can be set for gcmp */
+    uint16_t gcmp : 1;
+    /** 1 bit value can be set for sms4 */
+    uint16_t sms4 : 1;
+    /** 1 bit value can be set for gcmp 256 */
+    uint16_t gcmp_256 : 1;
+    /** 1 bit valuecan be set for ccmp 256 */
+    uint16_t ccmp_256 : 1;
+    /** 1 bit is reserved */
+    uint16_t rsvd : 1;
+    /** 1 bit value can be set for bip gmac 128 */
+    uint16_t bip_gmac_128 : 1;
+    /** 1 bit value can be set for bip gmac 256 */
+    uint16_t bip_gmac_256 : 1;
+    /** 1 bit value can be set for bip cmac 256 */
+    uint16_t bip_cmac_256 : 1;
+    /** 1 bit valuecan be set for gtk not used */
+    uint16_t gtk_not_used : 1;
+    /** 4 bits are reserved */
+    uint16_t rsvd2 : 2;
+} _Cipher_t;
+
+/* Security mode structure */
+typedef struct
+{
+    /** No security */
+    uint32_t noRsn : 1;
+    /** WEP static */
+    uint32_t wepStatic : 1;
+    /** WEP dynamic */
+    uint32_t wepDynamic : 1;
+    /** WPA */
+    uint32_t wpa : 1;
+    /** WPA none */
+    uint32_t wpaNone : 1;
+    /** WPA 2 */
+    uint32_t wpa2 : 1;
+    /** WPA 2 sha256 */
+    uint32_t wpa2_sha256 : 1;
+    /** OWE */
+    uint32_t owe : 1;
+    /** WPA3 SAE */
+    uint32_t wpa3_sae : 1;
+    /** 802.1x */
+    uint32_t wpa2_entp : 1;
+    /** 802.1x sha256 */
+    uint32_t wpa2_entp_sha256 : 1;
+    /** FT 802.1x */
+    uint32_t ft_1x : 1;
+    /** FT 802.1x sha384 */
+    uint32_t ft_1x_sha384 : 1;
+    /** FT PSK  */
+    uint32_t ft_psk : 1;
+    /** FT SAE */
+    uint32_t ft_sae : 1;
+    /** WPA3 802.1x sha256 */
+    uint32_t wpa3_1x_sha256 : 1;
+    /** WPA3 802.1x sha384 */
+    uint32_t wpa3_1x_sha384 : 1;
+    /** Reserved 16 bits */
+    uint32_t rsvd : 16;
+} _SecurityMode_t;
+
+/* TODO: clean up the parts brought over from the Host SME BSSDescriptor_t,
+ * remove ifdefs, consolidate security info */
+
+/** MLAN Maximum SSID Length */
+#define MLAN_MAX_SSID_LENGTH (32U)
+/** MLAN Maximum PASSPHRASE Length */
+#define MLAN_MAX_PASS_LENGTH (64)
+
+/** Scan result information */
+struct wifi_scan_result2
+{
+    uint8_t bssid[MLAN_MAC_ADDR_LENGTH]; /*!< BSSID array */
+    bool is_ibss_bit_set;                /*!< Is bssid set? */
+
+    uint8_t ssid[MLAN_MAX_SSID_LENGTH];  /*!< ssid array */
+    int ssid_len;                        /*!< SSID length */
+    uint8_t Channel;                     /*!< Channel associated to the BSSID */
+    uint8_t RSSI;                        /*!< Received signal strength */
+    uint16_t beacon_period;              /*!< Beacon period */
+    uint16_t dtim_period;                /*!< DTIM period */
+    _SecurityMode_t WPA_WPA2_WEP;        /*!< Security mode info */
+    _Cipher_t wpa_mcstCipher;            /*!< WPA multicast cipher */
+    _Cipher_t wpa_ucstCipher;            /*!< WPA unicast cipher */
+    _Cipher_t rsn_mcstCipher;            /*!< No security multicast cipher */
+    _Cipher_t rsn_ucstCipher;            /*!< No security unicast cipher */
+    bool is_pmf_required;                /*!< Is pmf required flag */
+    t_u8 ap_mfpc;                        /*!< MFPC bit of AP */
+    t_u8 ap_mfpr;                        /*!< MFPR bit of AP */
+    t_u8 ap_pwe;                         /*!< PWE bit of AP */
+
+    /*!<
+     **  WPA_WPA2 = 0 => Security not enabled
+     **  = 1 => WPA mode
+     **  = 2 => WPA2 mode
+     **  = 3 => WEP mode
+     */
+    bool phtcap_ie_present;  /*!< PHT CAP IE present info */
+    bool phtinfo_ie_present; /*!< PHT INFO IE present info */
+#if CONFIG_11AC
+    /** 11AC VHT capab support */
+    bool pvhtcap_ie_present;
+#endif
+#if CONFIG_11AX
+    /** 11AX HE capab support */
+    bool phecap_ie_present;
+#endif
+
+    bool wmm_ie_present;                       /*!< WMM IE present info */
+    uint16_t band;                             /*!< Band info */
+
+    bool wps_IE_exist;                         /*!< WPS IE exist info */
+    uint16_t wps_session;                      /*!< WPS session */
+    bool wpa2_entp_IE_exist;                   /*!< WPA2 enterprise IE exist info */
+    uint8_t trans_mode;                        /*!< Trans mode */
+    uint8_t trans_bssid[MLAN_MAC_ADDR_LENGTH]; /*!< Trans bssid array */
+    uint8_t trans_ssid[MLAN_MAX_SSID_LENGTH];  /*!< Trans ssid array */
+    int trans_ssid_len;                        /*!< Trans bssid length */
+#if CONFIG_DRIVER_MBO
+    bool mbo_assoc_disallowed;                 /*!< MBO disallowed */
+#endif
+#if CONFIG_11R
+    /** Mobility domain identifier */
+    uint16_t mdid;
+#endif
+#if CONFIG_11K
+    /** Neigbort report support */
+    bool neighbor_report_supported;
+#endif
+#if CONFIG_11V
+    /** bss transition support */
+    bool bss_transition_supported;
+#endif
+};
+
+/** MAC address */
+typedef struct
+{
+    /** Mac address array */
+    char mac[MLAN_MAC_ADDR_LENGTH];
+} wifi_mac_addr_t;
+
+/** Firmware version */
+typedef struct
+{
+    /** Firmware version string */
+    char version_str[MLAN_MAX_VER_STR_LEN];
+} wifi_fw_version_t;
+
+/** Extended Firmware version */
+typedef struct
+{
+    /** ID for extended version select */
+    uint8_t version_str_sel;
+    /** Firmware version string */
+    char version_str[MLAN_MAX_VER_STR_LEN];
+} wifi_fw_version_ext_t;
+
+enum wlan_type
+{
+    WLAN_TYPE_NORMAL = 0,
+    WLAN_TYPE_WIFI_CALIB,
+    WLAN_TYPE_FCC_CERTIFICATION,
+};
+
+/** Tx power levels */
+typedef struct
+{
+    /** Current power level */
+    uint16_t current_level;
+    /** Maximum power level */
+    uint8_t max_power;
+    /** Minimum power level */
+    uint8_t min_power;
+
+} wifi_tx_power_t;
+
+/** Rf channel */
+typedef struct
+{
+    /** Current channel */
+    uint16_t current_channel;
+    /** RF Type */
+    uint16_t rf_type;
+} wifi_rf_channel_t;
+
+/** Remain on channel info structure */
+typedef struct
+{
+    /** Remove */
+    uint16_t remove;
+    /** Current status */
+    uint8_t status;
+    /** band configuration */
+    uint8_t bandcfg;
+    /** Channel */
+    uint8_t channel;
+    /** Remain on channel period */
+    uint32_t remain_period;
+} wifi_remain_on_channel_t;
+
+#if CONFIG_11AX
+/** TX Rate Setting */
+typedef PACK_START struct _txrate_setting
+{
+    /** Preamble */
+    t_u16 preamble : 2; /*BIT1-BIT0:
+                         *  For legacy 11b: preamble type
+                         *    00    = long
+                         *    01    = short
+                         *    10/11  = reserved
+                         *  For legacy 11g: reserved
+                         *  For 11n: Green field PPDU indicator
+                         *    00 = HT-mix
+                         *    01 = HT-GF
+                         *    10/11 = reserved.
+                         *  For 11ac: reserved.
+                         *  For 11ax:
+                         *    00 = HE-SU
+                         *    01 = HE-EXT-SU
+                         *    10 = HE-MU
+                         *    11 = HE trigger based
+                         */
+    /** Bandwidth */
+    t_u16 bandwidth : 3; /* BIT2- BIT4
+                          * For 11n and 11ac traffic: Bandwidth
+                          *    0 = 20Mhz
+                          *    1 = 40Mhz
+                          *    2 = 80 Mhz
+                          *    3 = 160 Mhz
+                          *    4-7 = reserved
+                          *  For legacy rate : BW>0 implies non-HT duplicates.
+                          *  For HE SU PPDU:
+                          *    0 = 20Mhz
+                          *    1 = 40Mhz
+                          *    2 = 80 Mhz
+                          *    3 = 160 Mhz
+                          *    4-7 = reserved
+                          *  For HE ER SU PPDU:
+                          *    0 = 242-tone RU
+                          *    1 = upper frequency 106 tone RU within the primary 20 Mhz.
+                          *  For HE MU PPDU:
+                          *    0 = 20Mhz.
+                          *    1 = 40Mhz.
+                          *    2 = 80Mhz non-preamble puncturing mode
+                          *    3 = 160Mhz and 80+80 Mhz non-preamble.
+                          *    4 = for preemble puncturing in 80 Mhz ,
+                          *        where in the preamble only the secondary 20Mhz is punctured.
+                          *    5 = for preemble puncturing in 80 Mhz ,
+                          *        where in the preamble only one of the two 20Mhz subchannels in the secondary 40Mhz is
+                          * punctured.  6 = for preemble puncturing in 160 Mhz or 80 Mhz + 80 Mhz,  where in the primary
+                          * 80 Mhz of the preamble only the secondary 20 Mhz is punctured.  7 = for preemble puncturing
+                          * in 160 Mhz or 80 Mhz + 80 Mhz,  where in the primary 80 Mhz of the preamble the primary 40
+                          * Mhz is present.
+                          */
+    /** Short GI */
+    t_u16 shortGI : 2; /*BIT5- BIT6
+                        *  For legacy: not used
+                        *  For 11n: 00 = normal, 01 =shortGI, 10/11 = reserved
+                        *  For 11ac: SGI map to VHT-SIG-A2[0]
+                        *           VHT-SIG-A2[1] is set to 1 if short guard interval is used
+                        *           and NSYM mod 10 = 9, otherwise set to 0.
+                        *  For 11ax:
+                        *           00 = 1xHELTF+GI0.8usec
+                        *           01 = 2xHELTF+GI0.8usec
+                        *           10 = 2xHELTF+GI1.6usec
+                        *           11 = 4xHELTF+GI0.8 usec if both DCM and STBC are 1
+                        *                4xHELTF+GI3.2 usec otherwise
+                        */
+    /** STBC */
+    t_u16 stbc : 1; // BIT7, 0: no STBC; 1: STBC
+    /** DCM */
+    t_u16 dcm : 1; // BIT8, 0: no DCM; 1: DCM used.
+    /** Adv coding */
+    t_u16 adv_coding : 1; // BIT9, 0: BCC; 1: LDPC.
+    /** Doppler */
+    t_u16 doppler : 2; /* BIT11-BIT10,
+                          00: Doppler0
+                          01: Doppler 1 with Mma =10
+                          10: Doppler 1 with Mma =20
+                       */
+    /** Max PK text */
+    t_u16 max_pktext : 2; /*BIT12-BIT13:
+                           * Max packet extension
+                           *  0 - 0 usec
+                           *  1 - 8 usec
+                           *  2 - 16 usec.
+                           */
+    /** Reserved */
+    t_u16 reserverd : 2; // BIT14-BIT15
+} PACK_END txrate_setting;
+
+#if CONFIG_MMSF
+typedef struct
+{
+    t_u8 *enable;
+    t_u8 *Density;
+    t_u8 *MMSF;
+} wifi_mmsf_cfg_t;
+#endif
+#endif
+
+/** Data structure for cmd txratecfg */
+typedef PACK_START struct _wifi_rate_cfg_t
+{
+    /** LG rate: 0, HT rate: 1, VHT rate: 2 */
+    mlan_rate_format rate_format;
+    /** Rate/MCS index (0xFF: auto) */
+    t_u32 rate_index;
+    /** Rate rate */
+    t_u32 rate;
+#if (CONFIG_11AC) || (CONFIG_11AX)
+    /** NSS */
+    t_u32 nss;
+#endif
+    /** Rate Setting */
+    t_u16 rate_setting;
+} PACK_END wifi_rate_cfg_t;
+
+/** Data structure for cmd get data rate */
+typedef PACK_START struct _wifi_data_rate_t
+{
+    /** Tx data rate */
+    t_u32 tx_data_rate;
+    /** Rx data rate */
+    t_u32 rx_data_rate;
+
+    /** Tx channel bandwidth */
+    t_u32 tx_bw;
+    /** Tx guard interval */
+    t_u32 tx_gi;
+    /** Rx channel bandwidth */
+    t_u32 rx_bw;
+    /** Rx guard interval */
+    t_u32 rx_gi;
+
+#ifndef SD8801
+    /** MCS index */
+    t_u32 tx_mcs_index;
+    /** MCS index */
+    t_u32 rx_mcs_index;
+#if (CONFIG_11AC) || (CONFIG_11AX)
+    /** NSS */
+    t_u32 tx_nss;
+    /** NSS */
+    t_u32 rx_nss;
+#endif
+    /** LG rate: 0, HT rate: 1, VHT rate: 2 */
+    mlan_rate_format tx_rate_format;
+    /** LG rate: 0, HT rate: 1, VHT rate: 2 */
+    mlan_rate_format rx_rate_format;
+#endif
+} PACK_END wifi_data_rate_t;
+
+enum wifi_ds_command_type
+{
+    WIFI_DS_RATE_CFG      = 0,
+    WIFI_DS_GET_DATA_RATE = 1,
+};
+
+/** Type definition of wifi_ds_rate */
+typedef PACK_START struct _wifi_ds_rate
+{
+    /** Sub-command */
+    enum wifi_ds_command_type sub_command;
+#if CONFIG_AUTO_NULL_TX
+    /** Only set auto tx fix rate */
+    t_u16 auto_null_fixrate_enable;
+#endif
+    /** Rate configuration parameter */
+    union
+    {
+        /** Rate configuration for MLAN_OID_RATE_CFG */
+        wifi_rate_cfg_t rate_cfg;
+        /** Data rate for MLAN_OID_GET_DATA_RATE */
+        wifi_data_rate_t data_rate;
+    } param;
+} PACK_END wifi_ds_rate;
+
+/** Type definition of wifi_ed_mac_ctrl_t */
+typedef PACK_START struct _wifi_ed_mac_ctrl_t
+{
+    /** ED CTRL 2G */
+    t_u16 ed_ctrl_2g;
+    /** ED Offset 2G */
+    t_s16 ed_offset_2g;
+    /** ED CTRL 5G */
+    t_u16 ed_ctrl_5g;
+    /** ED Offset 5G */
+    t_s16 ed_offset_5g;
+} PACK_END wifi_ed_mac_ctrl_t;
+
+/** Type definition of wifi_bandcfg_t */
+typedef PACK_START struct _wifi_bandcfg_t
+{
+    /** Infra band */
+    t_u16 config_bands;
+    /** fw supported band */
+    t_u16 fw_bands;
+} PACK_END wifi_bandcfg_t;
+
+#ifdef SD8801
+/** Type definition of wifi_ext_coex_config_t */
+typedef PACK_START struct _wifi_ext_coex_config_t
+{
+    /** Enable or disable external coexistence */
+    t_u8 Enabled;
+    /** Ignore the priority of the external radio request */
+    t_u8 IgnorePriority;
+    /** Default priority when the priority of the external radio
+request is ignored */
+    t_u8 DefaultPriority;
+    /** Input request GPIO pin for EXT_RADIO_REQ signal */
+    t_u8 EXT_RADIO_REQ_ip_gpio_num;
+    /** Input request GPIO polarity for EXT_RADIO_REQ signal */
+    t_u8 EXT_RADIO_REQ_ip_gpio_polarity;
+    /** Input priority GPIO pin for EXT_RADIO_PRI signal */
+    t_u8 EXT_RADIO_PRI_ip_gpio_num;
+    /** Input priority GPIO polarity for EXT_RADIO_PRI signal */
+    t_u8 EXT_RADIO_PRI_ip_gpio_polarity;
+    /** Output grant GPIO pin for WLAN_GRANT signal */
+    t_u8 WLAN_GRANT_op_gpio_num;
+    /** Output grant GPIO polarity of WLAN_GRANT */
+    t_u8 WLAN_GRANT_op_gpio_polarity;
+    /** Reserved Bytes */
+    t_u16 reserved_1;
+    /** Reserved Bytes */
+    t_u16 reserved_2;
+} PACK_END wifi_ext_coex_config_t;
+
+/** Type definition of wifi_ext_coex_stats_t */
+typedef PACK_START struct _wifi_ext_coex_stats_t
+{
+    /** External Radio Request count */
+    t_u16 ext_radio_req_count;
+    /** External Radio Priority count */
+    t_u16 ext_radio_pri_count;
+    /** WLAN GRANT count */
+    t_u16 wlan_grant_count;
+} PACK_END wifi_ext_coex_stats_t;
+#endif
+
+/** Type definition of wifi_antcfg_t */
+typedef PACK_START struct _wifi_antcfg_t
+{
+    /** Antenna Mode */
+    t_u32 *ant_mode;
+    /** Evaluate Time */
+    t_u16 *evaluate_time;
+    /** Current antenna*/
+    t_u16 *current_antenna;
+#ifdef RW610
+    /** Evaluate mode */
+    t_u8 *evaluate_mode;
+#endif
+} PACK_END wifi_antcfg_t;
+
+/** CW_MODE_CTRL structure */
+typedef PACK_START struct _wifi_cw_mode_ctrl_t
+{
+    /** Mode of Operation 0:Disable 1: Tx Continuous Packet 2 : Tx
+ Continuous Wave */
+    t_u8 mode;
+    /** channel */
+    t_u8 channel;
+    /** channel info */
+    t_u8 chanInfo;
+    /** Tx Power level in dBm */
+    t_u16 txPower;
+    /** Packet Length */
+    t_u16 pktLength;
+    /** bit rate info */
+    t_u32 rateInfo;
+} PACK_END wifi_cw_mode_ctrl_t;
+
+/** TBTT offset structure */
+typedef struct
+{
+    /** Min TBTT offset */
+    t_u32 min_tbtt_offset;
+    /** Max TBTT offset */
+    t_u32 max_tbtt_offset;
+    /** AVG TBTT offset */
+    t_u32 avg_tbtt_offset;
+} wifi_tbtt_offset_t;
+
+#ifndef BIT
+#define BIT(n) (1U << (n))
+#endif
+#define WOWLAN_MAX_PATTERN_LEN           20
+#define WOWLAN_MAX_OFFSET_LEN            50
+#define MAX_NUM_FILTERS                  10
+#define MEF_MODE_HOST_SLEEP              (1 << 0)
+#define MEF_MODE_NON_HOST_SLEEP          (1 << 1)
+#define MEF_ACTION_WAKE                  (1 << 0)
+#define MEF_ACTION_ALLOW                 (1 << 1)
+#define MEF_ACTION_ALLOW_AND_WAKEUP_HOST 3
+#define MEF_AUTO_ARP                     0x10
+#define MEF_AUTO_PING                    0x20
+#define MEF_NS_RESP                      0x40
+#define MEF_MAGIC_PKT                    0x80
+#define CRITERIA_BROADCAST               MBIT(0)
+#define CRITERIA_UNICAST                 MBIT(1)
+#define CRITERIA_MULTICAST               MBIT(3)
+
+#define MAX_NUM_ENTRIES  8
+#define MAX_NUM_BYTE_SEQ 6
+#define MAX_NUM_MASK_SEQ 6
+
+#define OPERAND_DNUM     1
+#define OPERAND_BYTE_SEQ 2
+
+#define MAX_OPERAND  0x40
+#define TYPE_BYTE_EQ (MAX_OPERAND + 1)
+#define TYPE_DNUM_EQ (MAX_OPERAND + 2)
+#define TYPE_BIT_EQ  (MAX_OPERAND + 3)
+
+#define RPN_TYPE_AND (MAX_OPERAND + 4)
+#define RPN_TYPE_OR  (MAX_OPERAND + 5)
+
+#define ICMP_OF_IP_PROTOCOL 0x01
+#define TCP_OF_IP_PROTOCOL  0x06
+#define UDP_OF_IP_PROTOCOL  0x11
+
+#define IPV4_PKT_OFFSET      20
+#define IP_PROTOCOL_OFFSET   31
+#define PORT_PROTOCOL_OFFSET 44
+
+#define FILLING_TYPE      MBIT(0)
+#define FILLING_PATTERN   MBIT(1)
+#define FILLING_OFFSET    MBIT(2)
+#define FILLING_NUM_BYTES MBIT(3)
+#define FILLING_REPEAT    MBIT(4)
+#define FILLING_BYTE_SEQ  MBIT(5)
+#define FILLING_MASK_SEQ  MBIT(6)
+
+/** Type definition of filter_item
+ *  support three match methods:
+ *  <1>Byte comparison type=0x41
+ *  <2>Decimal comparison type=0x42
+ *  <3>Bit comparison type=0x43
+ */
+typedef struct _wifi_mef_filter_t
+{
+    /** flag*/
+    t_u32 fill_flag;
+    /** BYTE 0X41; Decimal 0X42; Bit 0x43*/
+    t_u16 type;
+    /** value*/
+    t_u32 pattern;
+    /** offset*/
+    t_u16 offset;
+    /** number of bytes*/
+    t_u16 num_bytes;
+    /** repeat*/
+    t_u16 repeat;
+    /** byte number*/
+    t_u8 num_byte_seq;
+    /** array*/
+    t_u8 byte_seq[MAX_NUM_BYTE_SEQ];
+    /** mask numbers*/
+    t_u8 num_mask_seq;
+    /** array*/
+    t_u8 mask_seq[MAX_NUM_MASK_SEQ];
+} wifi_mef_filter_t;
+
+/** MEF entry struct */
+typedef struct _wifi_mef_entry_t
+{
+    /** mode: bit0--hostsleep mode; bit1--non hostsleep mode */
+    t_u8 mode;
+    /** action: 0--discard and not wake host;
+                1--discard and wake host;
+                3--allow and wake host;*/
+    t_u8 action;
+    /** filter number */
+    t_u8 filter_num;
+    /** filter array*/
+    wifi_mef_filter_t filter_item[MAX_NUM_FILTERS];
+    /** rpn array*/
+    t_u8 rpn[MAX_NUM_FILTERS];
+} wifi_mef_entry_t;
+
+/** Wifi filter config struct */
+typedef struct _wifi_flt_cfg
+{
+    /** Filter Criteria */
+    t_u32 criteria;
+    /** Number of entries */
+    t_u16 nentries;
+    /** MEF entry*/
+    wifi_mef_entry_t mef_entry[MAX_NUM_ENTRIES];
+} wifi_flt_cfg_t;
+
+/* User defined pattern struct */
+typedef struct
+{
+    /** pattern offset of received pattern */
+    t_u8 pkt_offset;
+    /** pattern length */
+    t_u8 pattern_len;
+    /** wowlan pattern */
+    t_u8 pattern[WOWLAN_MAX_PATTERN_LEN];
+    /** mask */
+    t_u8 mask[6];
+} wifi_wowlan_pattern_t;
+
+/** Wowlan Pattern config struct */
+typedef struct
+{
+    /** Enable user defined pattern*/
+    t_u8 enable;
+    /** number of patterns******/
+    t_u8 n_patterns;
+    /** user define pattern*/
+    wifi_wowlan_pattern_t patterns[MAX_NUM_FILTERS];
+} wifi_wowlan_ptn_cfg_t;
+
+/** TCP keep alive information */
+typedef struct
+{
+    /** Enable keep alive */
+    t_u8 enable;
+    /** Reset */
+    t_u8 reset;
+    /** Keep alive timeout */
+    t_u32 timeout;
+    /** Keep alive interval */
+    t_u16 interval;
+    /** Maximum keep alives */
+    t_u16 max_keep_alives;
+    /** Destination MAC address */
+    t_u8 dst_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Destination IP */
+    t_u32 dst_ip;
+    /** Destination TCP port */
+    t_u16 dst_tcp_port;
+    /** Source TCP port */
+    t_u16 src_tcp_port;
+    /** Sequence number */
+    t_u32 seq_no;
+} wifi_tcp_keep_alive_t;
+
+/** TCP nat keep alive information */
+typedef struct
+{
+    /** Keep alive interval */
+    t_u16 interval;
+    /** Destination MAC address */
+    t_u8 dst_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Destination IP */
+    t_u32 dst_ip;
+    /** Destination port */
+    t_u16 dst_port;
+} wifi_nat_keep_alive_t;
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+#define MKEEP_ALIVE_IP_PKT_MAX 256
+/** Cloud keep alive information */
+typedef struct
+{
+    /** Keep alive id */
+    t_u8 mkeep_alive_id;
+    /** Enable keep alive */
+    t_u8 enable;
+    /** Enable/Disable tcp reset */
+    t_u8 reset;
+    /** Saved in driver */
+    t_u8 cached;
+    /** Period to send keep alive packet(The unit is milliseconds) */
+    t_u32 send_interval;
+    /** Period to send retry packet(The unit is milliseconds) */
+    t_u16 retry_interval;
+    /** Count to send retry packet */
+    t_u16 retry_count;
+    /** Source MAC address */
+    t_u8 src_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Destination MAC address */
+    t_u8 dst_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Source IP */
+    t_u32 src_ip;
+    /** Destination IP */
+    t_u32 dst_ip;
+    /** Source Port */
+    t_u16 src_port;
+    /** Destination Port */
+    t_u16 dst_port;
+    /** Packet length */
+    t_u16 pkt_len;
+    /** Packet buffer */
+    t_u8 packet[MKEEP_ALIVE_IP_PKT_MAX];
+} wifi_cloud_keep_alive_t;
+#endif
+
+/** RSSI information */
+typedef struct
+{
+    /** Data RSSI last */
+    int16_t data_rssi_last;
+    /** Data nf last */
+    int16_t data_nf_last;
+    /** Data RSSI average */
+    int16_t data_rssi_avg;
+    /** Data nf average */
+    int16_t data_nf_avg;
+    /** BCN SNR */
+    int16_t bcn_snr_last;
+    /** BCN SNR average */
+    int16_t bcn_snr_avg;
+    /** Data SNR last */
+    int16_t data_snr_last;
+    /** Data SNR average */
+    int16_t data_snr_avg;
+    /** BCN RSSI */
+    int16_t bcn_rssi_last;
+    /** BCN nf */
+    int16_t bcn_nf_last;
+    /** BCN RSSI average */
+    int16_t bcn_rssi_avg;
+    /** BCN nf average */
+    int16_t bcn_nf_avg;
+} wifi_rssi_info_t;
+
+/**
+ * Data structure for subband set
+ *
+ * For uAP 11d support
+ */
+typedef struct
+{
+    /** First channel */
+    t_u8 first_chan;
+    /** Number of channels */
+    t_u8 no_of_chan;
+    /** Maximum Tx power in dBm */
+    t_u8 max_tx_pwr;
+
+} wifi_sub_band_set_t;
+
+/**
+ * Data structure for Channel attributes
+ *
+ */
+typedef PACK_START struct
+{
+    /** Channel Number */
+    t_u8 chan_num;
+    /** Channel frequency for this channel */
+    t_u16 chan_freq;
+    /** Passice Scan or RADAR Detect*/
+    bool passive_scan_or_radar_detect;
+} PACK_END wifi_chan_info_t;
+
+/**
+ * Data structure for Channel List Config
+ *
+ */
+typedef PACK_START struct
+{
+    /** Number of Channels */
+    t_u8 num_chans;
+    /** Channel Info */
+    wifi_chan_info_t chan_info[54];
+} PACK_END wifi_chanlist_t;
+
+/** Wifi subband enum */
+typedef enum
+{
+    /** Subband 2.4 GHz */
+    SubBand_2_4_GHz = 0x00,
+    /** Subband 5 GHz 0 */
+    SubBand_5_GHz_0 = 0x10,
+    /** Subband 5 GHz 1 */
+    SubBand_5_GHz_1 = 0x11,
+    /** Subband 5 GHz 2 */
+    SubBand_5_GHz_2 = 0x12,
+    /** Subband 5 GHz 3 */
+    SubBand_5_GHz_3 = 0x13,
+} wifi_SubBand_t;
+
+/**
+ * Data structure for Channel descriptor
+ *
+ * Set CFG data for Tx power limitation
+ *
+ * start_freq: Starting Frequency of the band for this channel\n
+ *                  2407, 2414 or 2400 for 2.4 GHz\n
+ *                  5000\n
+ *                  4000\n
+ * chan_width: Channel Width\n
+ *                  20\n
+ * chan_num  : Channel Number\n
+ *
+ */
+typedef PACK_START struct
+{
+    /** Starting frequency of the band for this channel */
+    t_u16 start_freq;
+    /** Channel width */
+    t_u8 chan_width;
+    /** Channel Number */
+    t_u8 chan_num;
+} PACK_END wifi_channel_desc_t;
+
+/**
+ * Data structure for Modulation Group
+ *
+ * mod_group : ModulationGroup\n
+ *                  0: CCK (1,2,5.5,11 Mbps)\n
+ *                  1: OFDM (6,9,12,18 Mbps)\n
+ *                  2: OFDM (24,36 Mbps)\n
+ *                  3: OFDM (48,54 Mbps)\n
+ *                  4: HT20 (0,1,2)\n
+ *                  5: HT20 (3,4)\n
+ *                  6: HT20 (5,6,7)\n
+ *                  7: HT40 (0,1,2)\n
+ *                  8: HT40 (3,4)\n
+ *                  9: HT40 (5,6,7)\n
+ *                  10: HT2_20 (8,9,10)\n
+ *                  11: HT2_20 (11,12)\n
+ *                  12: HT2_20 (13,14,15)\n
+ *tx_power   : Power Limit in dBm\n
+ *
+ */
+typedef PACK_START struct
+{
+    /** Modulation group */
+    t_u8 mod_group;
+    /** Tx Power */
+    t_u8 tx_power;
+} PACK_END wifi_txpwrlimit_entry_t;
+
+/**
+ * Data structure for TRPC config
+ *
+ * For TRPC support
+ */
+typedef PACK_START struct
+{
+    /** Number of modulation groups */
+    t_u8 num_mod_grps;
+    /** Chnannel descriptor */
+    wifi_channel_desc_t chan_desc;
+    /** Channel Modulation groups */
+#if CONFIG_11AX
+    wifi_txpwrlimit_entry_t txpwrlimit_entry[20];
+#elif (CONFIG_11AC)
+    wifi_txpwrlimit_entry_t txpwrlimit_entry[16];
+#else
+    wifi_txpwrlimit_entry_t txpwrlimit_entry[10];
+#endif /* CONFIG_11AX */
+} PACK_END wifi_txpwrlimit_config_t;
+
+/**
+ * Data structure for Channel TRPC config
+ *
+ * For TRPC support
+ */
+typedef PACK_START struct
+{
+    /** SubBand */
+    wifi_SubBand_t subband;
+    /** Number of Channels */
+    t_u8 num_chans;
+    /** TRPC config */
+#if defined(SD9177)
+    wifi_txpwrlimit_config_t txpwrlimit_config[43];
+#else
+    wifi_txpwrlimit_config_t txpwrlimit_config[40];
+#endif
+} PACK_END wifi_txpwrlimit_t;
+
+#if CONFIG_11AX
+typedef PACK_START struct _wifi_rupwrlimit_config_t
+{
+    /** start freq */
+    t_u16 start_freq;
+    /* channel width */
+    t_u8 width;
+    /** channel number */
+    t_u8 chan_num;
+    /** chan ru Power */
+    t_s16 ruPower[MAX_RU_COUNT];
+} PACK_END wifi_rupwrlimit_config_t;
+
+/**
+ * Data structure for Channel RU PWR config
+ *
+ * For RU PWR support
+ */
+typedef PACK_START struct
+{
+    /** Number of Channels */
+    t_u8 num_chans;
+    /** RU PWR config */
+    wifi_rupwrlimit_config_t rupwrlimit_config[MAX_RUTXPWR_NUM];
+} PACK_END wifi_rutxpwrlimit_t;
+
+/** Wi-Fi 11AX Configuration */
+typedef PACK_START struct
+{
+    /** Band */
+    t_u8 band;
+    /** tlv id of he capability */
+    t_u16 id;
+    /** length of the payload */
+    t_u16 len;
+    /** extension id */
+    t_u8 ext_id;
+    /** he mac capability info */
+    t_u8 he_mac_cap[6];
+    /** he phy capability info */
+    t_u8 he_phy_cap[11];
+    /** he txrx mcs support for 80MHz */
+    t_u8 he_txrx_mcs_support[4];
+    /** val for PE thresholds */
+    t_u8 val[4];
+} PACK_END wifi_11ax_config_t;
+
+#if CONFIG_11AX_TWT
+/** Wi-Fi TWT setup configuration */
+typedef PACK_START struct
+{
+    /** Implicit, 0: TWT session is explicit, 1: Session is implicit */
+    t_u8 implicit;
+    /** Announced, 0: Unannounced, 1: Announced TWT */
+    t_u8 announced;
+    /** Trigger Enabled, 0: Non-Trigger enabled, 1: Trigger enabled TWT */
+    t_u8 trigger_enabled;
+    /** TWT Information Disabled, 0: TWT info enabled, 1: TWT info disabled */
+    t_u8 twt_info_disabled;
+    /** Negotiation Type, 0: Future Individual TWT SP start time, 1: Next
+     * Wake TBTT time */
+    t_u8 negotiation_type;
+    /** TWT Wakeup Duration, time after which the TWT requesting STA can
+     * transition to doze state */
+    t_u8 twt_wakeup_duration;
+    /** Flow Identifier. Range: [0-7]*/
+    t_u8 flow_identifier;
+    /** Hard Constraint, 0: FW can tweak the TWT setup parameters if it is
+     *rejected by AP.
+     ** 1: Firmware should not tweak any parameters. */
+    t_u8 hard_constraint;
+    /** TWT Exponent, Range: [0-63] */
+    t_u8 twt_exponent;
+    /** TWT Mantissa Range: [0-sizeof(UINT16)] */
+    t_u16 twt_mantissa;
+    /** TWT Request Type, 0: REQUEST_TWT, 1: SUGGEST_TWT*/
+    t_u8 twt_request;
+} PACK_END wifi_twt_setup_config_t;
+
+/** Wi-Fi Teardown Configuration */
+typedef PACK_START struct
+{
+    /** TWT Flow Identifier. Range: [0-7] */
+    t_u8 flow_identifier;
+    /** Negotiation Type. 0: Future Individual TWT SP start time, 1: Next
+     * Wake TBTT time */
+    t_u8 negotiation_type;
+    /** Tear down all TWT. 1: To teardown all TWT, 0 otherwise */
+    t_u8 teardown_all_twt;
+} PACK_END wifi_twt_teardown_config_t;
+
+/** Wi-Fi BTWT Configuration */
+typedef PACK_START struct
+{
+    /** Only support 1: Set*/
+    t_u16 action;
+    /** Broadcast TWT AP config */
+    t_u16 sub_id;
+    /** Range 64-255 */
+    t_u8 nominal_wake;
+    /** Max STA Support */
+    t_u8 max_sta_support;
+    /** TWT Mantissa */
+    t_u16 twt_mantissa;
+    /** TWT Offset */
+    t_u16 twt_offset;
+    /** TWT Exponent */
+    t_u8 twt_exponent;
+    /** SP Gap */
+    t_u8 sp_gap;
+} PACK_END wifi_btwt_config_t;
+
+#define WLAN_BTWT_REPORT_LEN     9
+#define WLAN_BTWT_REPORT_MAX_NUM 4
+/** Wi-Fi TWT Report Configuration */
+typedef PACK_START struct
+{
+    /** TWT report type, 0: BTWT id */
+    t_u8 type;
+    /** TWT report length of value in data */
+    t_u8 length;
+    /** Reserved 2 */
+    t_u8 reserve[2];
+    /** TWT report buffer */
+    t_u8 data[WLAN_BTWT_REPORT_LEN * WLAN_BTWT_REPORT_MAX_NUM];
+} PACK_END wifi_twt_report_t;
+
+#endif /* CONFIG_11AX_TWT */
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+/** Wi-Fi Clock sync configuration */
+typedef PACK_START struct
+{
+    /**clock sync Mode */
+    t_u8 clock_sync_mode;
+    /**clock sync Role */
+    t_u8 clock_sync_Role;
+    /**clock sync GPIO Pin Number */
+    t_u8 clock_sync_gpio_pin_number;
+    /**clock sync GPIO Level or Toggle */
+    t_u8 clock_sync_gpio_level_toggle;
+    /**clock sync GPIO Pulse Width */
+    t_u16 clock_sync_gpio_pulse_width;
+} PACK_END wifi_clock_sync_gpio_tsf_t;
+
+/** Wi-Fi TSF information */
+typedef PACK_START struct
+{
+    /**get tsf info format */
+    t_u16 tsf_format;
+    /**tsf info */
+    t_u16 tsf_info;
+    /**tsf */
+    t_u64 tsf;
+    /**Positive or negative offset in microsecond from Beacon TSF to GPIO toggle TSF  */
+    t_s32 tsf_offset;
+} PACK_END wifi_tsf_info_t;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+#if CONFIG_NET_MONITOR
+typedef t_u8 wifi_802_11_mac_addr[MLAN_MAC_ADDR_LENGTH];
+
+/** Network monitor structure */
+typedef PACK_START struct
+{
+    /** Action */
+    t_u16 action;
+    /** Monitor activity */
+    t_u16 monitor_activity;
+    /** Filter flags */
+    t_u16 filter_flags;
+    /** Channel scan parameter : Radio type */
+    t_u8 radio_type;
+    /** Channel number */
+    t_u8 chan_number;
+    /** mac num of filter*/
+    t_u8 filter_num;
+    /** Source address of the packet to receive */
+    wifi_802_11_mac_addr mac_addr[MAX_MONIT_MAC_FILTER_NUM];
+} PACK_END wifi_net_monitor_t;
+
+/** Beacon information structure */
+typedef PACK_START struct
+{
+    /** Frame control flags */
+    uint8_t frame_ctrl_flags;
+	/** time interval */
+    uint16_t duration;
+    /** Destination MAC address */
+    char dest[MLAN_MAC_ADDR_LENGTH];
+    /** Source MAC address */
+    char src[MLAN_MAC_ADDR_LENGTH];
+    /** BSSID */
+    char bssid[MLAN_MAC_ADDR_LENGTH];
+	/** Fragment number of frame fragments */
+    uint16_t seq_frag_num;
+    /** Beacon timestamp */
+    uint8_t timestamp[8];
+	/** Beacon interval, Send periodically at Beacon time intervals, typically abbreviated as TU, representing 1024 microseconds */
+    uint16_t beacon_interval;
+	/** capability info, when sending beacon signals, it is used to notify all parties of the performance of the network */
+    uint16_t cap_info;
+	/** element identification code */
+    uint8_t ssid_element_id;
+    /** SSID Length */
+    uint8_t ssid_len;
+    /** SSID string */
+    char ssid[MLAN_MAX_SSID_LENGTH];
+} PACK_END wifi_beacon_info_t;
+
+/** Wifi data information */
+typedef PACK_START struct
+{
+    /** Frame control flags */
+    uint8_t frame_ctrl_flags;
+	/** data time interval */
+    uint16_t duration;
+	/** basic service set identifier */
+    char bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Source MAC address */
+    char src[MLAN_MAC_ADDR_LENGTH];
+    /** Destination MAC address */
+    char dest[MLAN_MAC_ADDR_LENGTH];
+	/** sequence frage number */
+    uint16_t seq_frag_num;
+    /** QOS control */
+    uint16_t qos_ctrl;
+} PACK_END wifi_data_info_t;
+#endif
+/** Wifi frame types */
+typedef enum
+{
+    /** Assoc request frame */
+    ASSOC_REQ_FRAME = 0x00,
+    /** Assoc response frame */
+    ASSOC_RESP_FRAME = 0x10,
+    /** ReAssoc request frame */
+    REASSOC_REQ_FRAME = 0x20,
+    /** ReAssoc response frame */
+    REASSOC_RESP_FRAME = 0x30,
+    /** Probe request frame */
+    PROBE_REQ_FRAME = 0x40,
+    /** Probe response frame */
+    PROBE_RESP_FRAME = 0x50,
+    /** BEACON frame */
+    BEACON_FRAME = 0x80,
+    /** Dis assoc frame */
+    DISASSOC_FRAME = 0xA0,
+    /** Auth frame */
+    AUTH_FRAME = 0xB0,
+    /** Deauth frame */
+    DEAUTH_FRAME = 0xC0,
+    /** Action frame */
+    ACTION_FRAME = 0xD0,
+    /** Data frame */
+    DATA_FRAME = 0x08,
+    /** QOS frame */
+    QOS_DATA_FRAME = 0x88,
+} wifi_frame_type_t;
+
+typedef PACK_START struct
+{
+    wifi_frame_type_t frame_type;
+#if CONFIG_NET_MONITOR
+    union
+    {
+        wifi_beacon_info_t beacon_info;
+        wifi_data_info_t data_info;
+    } frame_data;
+#endif
+} PACK_END wifi_frame_t;
+
+typedef struct
+{
+    uint8_t mfpc;
+    uint8_t mfpr;
+} wifi_pmf_params_t;
+
+/** Channel scan parameters */
+typedef struct
+{
+    /** channel number */
+    t_u8 chan_number;
+    /** minimum scan time */
+    t_u16 min_scan_time;
+    /** maximum scan time */
+    t_u16 max_scan_time;
+} wifi_chan_scan_param_set_t;
+
+/** Channel list parameter set */
+typedef struct
+{
+    /** number of channels */
+    t_u8 no_of_channels;
+    /** channel scan array */
+    wifi_chan_scan_param_set_t chan_scan_param[1];
+} wifi_chan_list_param_set_t;
+
+/** 802_11_header packet */
+typedef PACK_START struct _wifi_mgmt_frame_t
+{
+    /** Packet Length */
+    t_u16 frm_len;
+    /** Frame Type */
+    wifi_frame_type_t frame_type;
+    /** Frame Control flags */
+    t_u8 frame_ctrl_flags;
+    /** Duration ID */
+    t_u16 duration_id;
+    /** Address 1 */
+    t_u8 addr1[MLAN_MAC_ADDR_LENGTH];
+    /** Address 2 */
+    t_u8 addr2[MLAN_MAC_ADDR_LENGTH];
+    /** Address 3 */
+    t_u8 addr3[MLAN_MAC_ADDR_LENGTH];
+    /** Sequence Control */
+    t_u16 seq_ctl;
+    /** Address 4 */
+    t_u8 addr4[MLAN_MAC_ADDR_LENGTH];
+    /** Frame payload */
+    t_u8 payload[1];
+} PACK_END wifi_mgmt_frame_t;
+
+/** Calibration Data */
+typedef PACK_START struct _wifi_cal_data_t
+{
+    /** Calibration data length */
+    t_u16 data_len;
+    /** Calibration data */
+    t_u8 *data;
+} PACK_END wifi_cal_data_t;
+
+/** Auto reconnect structure */
+typedef PACK_START struct _wifi_auto_reconnect_config_t
+{
+    /** Reconnect counter */
+    t_u8 reconnect_counter;
+    /** Reconnect interval */
+    t_u8 reconnect_interval;
+    /** Flags */
+    t_u16 flags;
+} PACK_END wifi_auto_reconnect_config_t;
+
+/** Scan all the channels in specified band */
+#define BAND_SPECIFIED 0x80U
+
+/** Scan channel list */
+typedef PACK_START struct _wifi_scan_channel_list_t
+{
+    /** Channel scan parameter : Radio type */
+    t_u8 radio_type;
+    /** Channel numder */
+    t_u8 chan_number;
+    /** Scan type Active = 1, Passive = 2 */
+    mlan_scan_type scan_type;
+    /** Scan time */
+    t_u16 scan_time;
+} PACK_END wifi_scan_channel_list_t;
+
+/* Configuration for wireless scanning */
+#if defined(RW610) && (CONFIG_ANT_DETECT)
+#define ANT_DETECT_MAX_CHANNEL_LIST 50U
+#endif
+#define MAX_CHANNEL_LIST 6
+#if CONFIG_COMBO_SCAN
+#define MAX_NUM_SSID 2
+#endif
+/** V2 scan parameters */
+typedef PACK_START struct _wifi_scan_params_v2_t
+{
+#if CONFIG_WPA_SUPP
+    /** Scan Only */
+    t_u8 scan_only;
+    /** BSSID present */
+    t_u8 is_bssid;
+    /** SSID present */
+    t_u8 is_ssid;
+#endif
+    /** BSSID to scan */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** SSID to scan */
+#if CONFIG_COMBO_SCAN
+    char ssid[MAX_NUM_SSID][MLAN_MAX_SSID_LENGTH + 1];
+#else
+    char ssid[MLAN_MAX_SSID_LENGTH + 1];
+#endif
+    /** Number of channels */
+    t_u8 num_channels;
+    /** Channel list with channel information */
+#if defined(RW610) && (CONFIG_ANT_DETECT)
+    wifi_scan_channel_list_t chan_list[ANT_DETECT_MAX_CHANNEL_LIST];
+#else
+    wifi_scan_channel_list_t chan_list[MAX_CHANNEL_LIST];
+#endif
+    /** Number of probes */
+    t_u8 num_probes;
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    /** Threshold of rssi */
+    t_s16 rssi_threshold;
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** scan channel gap */
+    t_u16 scan_chan_gap;
+#endif
+    /** Callback to be called when scan is completed */
+    int (*cb)(unsigned int count);
+} PACK_END wifi_scan_params_v2_t;
+
+#if CONFIG_RF_TEST_MODE
+/** Configuration for Manufacturing generic command */
+typedef PACK_START struct _wifi_mfg_cmd_generic_cfg
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** value 1 */
+    t_u32 data1;
+    /** value 2 */
+    t_u32 data2;
+    /** value 3 */
+    t_u32 data3;
+} PACK_END wifi_mfg_cmd_generic_cfg_t;
+
+/** Configuration for Manufacturing command Tx Frame */
+typedef PACK_START struct _wifi_mfg_cmd_tx_frame
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable */
+    t_u32 enable;
+    /** data_rate */
+    t_u32 data_rate;
+    /** frame pattern */
+    t_u32 frame_pattern;
+    /** frame length */
+    t_u32 frame_length;
+    /** BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Adjust burst sifs */
+    t_u16 adjust_burst_sifs;
+    /** Burst sifs in us*/
+    t_u32 burst_sifs_in_us;
+    /** short preamble */
+    t_u32 short_preamble;
+    /** active sub channel */
+    t_u32 act_sub_ch;
+    /** short GI */
+    t_u32 short_gi;
+    /** Adv coding */
+    t_u32 adv_coding;
+    /** Tx beamforming */
+    t_u32 tx_bf;
+    /** HT Greenfield Mode*/
+    t_u32 gf_mode;
+    /** STBC */
+    t_u32 stbc;
+    /** power id */
+    t_u32 rsvd[1];
+    /**signal bw*/
+    t_u32 signal_bw;
+    /** NumPkt */
+    t_u32 NumPkt;
+    /** MaxPE */
+    t_u32 MaxPE;
+    /** BeamChange */
+    t_u32 BeamChange;
+    /** Dcm */
+    t_u32 Dcm;
+    /** Doppler */
+    t_u32 Doppler;
+    /** MidP */
+    t_u32 MidP;
+    /** QNum */
+    t_u32 QNum;
+} PACK_END wifi_mfg_cmd_tx_frame_t;
+
+/** Configuration for Manufacturing command Tx Continuous */
+typedef PACK_START struct _wifi_mfg_cmd_tx_cont
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable Tx*/
+    t_u32 enable_tx;
+    /** Continuous Wave mode */
+    t_u32 cw_mode;
+    /** payload pattern */
+    t_u32 payload_pattern;
+    /** CS Mode */
+    t_u32 cs_mode;
+    /** active sub channel */
+    t_u32 act_sub_ch;
+    /** Tx rate */
+    t_u32 tx_rate;
+    /** power id */
+    t_u32 rsvd;
+} PACK_END wifi_mfg_cmd_tx_cont_t;
+
+typedef PACK_START struct wifi_mfg_cmd_he_tb_tx
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** Enable Tx */
+    t_u16 enable;
+    /** Q num */
+    t_u16 qnum;
+    /** AID */
+    t_u16 aid;
+    /** AXQ Mu Timer */
+    t_u16 axq_mu_timer;
+    /** Tx Power */
+    t_s16 tx_power;
+} PACK_END wifi_mfg_cmd_he_tb_tx_t;
+
+typedef PACK_START struct wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable Tx*/
+    t_u32 enable_tx;
+    /** enable Stand Alone HE TB */
+    t_u32 standalone_hetb;
+    /** Frame Control */
+    mfg_cmd_IEEEtypes_FrameCtrl_t frmCtl;
+    /** Duration */
+    t_u16 duration;
+    /** Destination MAC Address */
+    t_u8 dest_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Source MAC Address */
+    t_u8 src_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Common Info Field **/
+    mfg_cmd_IEEEtypes_HETrigComInfo_t trig_common_field;
+    /** User Info Field **/
+    mfg_cmd_IEEEtypes_HETrigUserInfo_t trig_user_info_field;
+    /** Trigger Dependent User Info Field **/
+    mfg_cmd_IEEETypes_BasicHETrigUserInfo_t basic_trig_user_info;
+} PACK_END wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr_t;
+
+typedef PACK_START struct wifi_mfg_cmd_otp_mac_addr_rd_wr
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** Destination MAC Address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+} PACK_END wifi_mfg_cmd_otp_mac_addr_rd_wr_t;
+
+typedef PACK_START struct wifi_mfg_cmd_otp_cal_data_rd_wr
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** CAL Data write status */
+    t_u32 cal_data_status;
+    /** CAL Data Length*/
+    t_u32 cal_data_len;
+    /** Destination MAC Address */
+    t_u8 cal_data[CAL_DATA_LEN];
+} PACK_END wifi_mfg_cmd_otp_cal_data_rd_wr_t;
+#endif
+
+#if CONFIG_HEAP_DEBUG
+#define MAX_FUNC_SYMBOL_LEN    64
+#define OS_MEM_STAT_TABLE_SIZE 128
+
+typedef struct
+{
+    char name[MAX_FUNC_SYMBOL_LEN];
+    t_u32 size;
+    t_u32 line_num;
+
+    t_u32 alloc_cnt;
+    t_u32 free_cnt;
+} wifi_os_mem_info;
+#endif
+
+#if CONFIG_MULTI_CHAN
+typedef PACK_START struct
+{
+    /** Channel Index*/
+    t_u16 chan_idx;
+    /** Channel time (in TU) for chan_idx */
+    t_u8 chantime;
+    /** Channel switch time (in TU) for chan_idx */
+    t_u8 switchtime;
+    /** Undoze time (in TU) for chan_idx */
+    t_u8 undozetime;
+    /** Rx traffic control scheme when channel switch*/
+    /** only valid for GC/STA interface*/
+    t_u8 mode;
+} PACK_END wifi_drcs_cfg_t;
+#endif
+
+
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+/** Type definition of mlan_ds_subscribe_evt for subscribe events */
+typedef struct _wifi_ds_subscribe_evt
+{
+    /** bitmap for subscribe event */
+    t_u16 evt_bitmap;
+    /** Absolute value of RSSI threshold value (dBm) */
+    t_u8 low_rssi;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 low_rssi_freq;
+    /** SNR threshold value (dB) */
+    t_u8 low_snr;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 low_snr_freq;
+    /** Failure count threshold */
+    t_u8 failure_count;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 failure_count_freq;
+    /** num of missed beacons */
+    t_u8 beacon_miss;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 beacon_miss_freq;
+    /** Absolute value of RSSI threshold value (dBm) */
+    t_u8 high_rssi;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 high_rssi_freq;
+    /** SNR threshold value (dB) */
+    t_u8 high_snr;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 high_snr_freq;
+    /** Absolute value of data RSSI threshold value (dBm) */
+    t_u8 data_low_rssi;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 data_low_rssi_freq;
+    /** Absolute value of data SNR threshold value (dBm) */
+    t_u8 data_low_snr;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 data_low_snr_freq;
+    /** Absolute value of data RSSI threshold value (dBm) */
+    t_u8 data_high_rssi;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 data_high_rssi_freq;
+    /** Absolute value of data SNR threshold value (dBm) */
+    t_u8 data_high_snr;
+    /** 0--report once, 1--report everytime happend, N -- report only happend > N consecutive times */
+    t_u8 data_high_snr_freq;
+    /* Link SNR threshold (dB) */
+    t_u16 link_snr;
+    /* Link SNR frequency */
+    t_u16 link_snr_freq;
+    /* Second minimum rate value as per the rate table below */
+    t_u16 link_rate;
+    /* Second minimum rate frequency */
+    t_u16 link_rate_freq;
+    /* Tx latency value (us) */
+    t_u16 link_tx_latency;
+    /* Tx latency frequency */
+    t_u16 link_tx_lantency_freq;
+    /* Number of pre missed beacons */
+    t_u8 pre_beacon_miss;
+} wifi_ds_subscribe_evt;
+#endif
+
+#if CONFIG_CSI
+#define CSI_FILTER_MAX 16
+/** Structure of CSI filters */
+typedef PACK_START struct _wifi_csi_filter_t
+{
+    /** Source address of the packet to receive */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Pakcet type of the interested CSI */
+    t_u8 pkt_type;
+    /** Packet subtype of the interested CSI */
+    t_u8 subtype;
+    /** Other filter flags */
+    t_u8 flags;
+} PACK_END wifi_csi_filter_t;
+/** Structure of CSI parameters */
+typedef PACK_START struct _wifi_csi_config_params_t
+{
+    /** 0: station; 1: uap */
+	t_u8 bss_type;
+    /** CSI enable flag. 1: enable, 2: disable */
+    t_u16 csi_enable;
+    /** Header ID*/
+    t_u32 head_id;
+    /** Tail ID */
+    t_u32 tail_id;
+    /** Number of CSI filters */
+    t_u8 csi_filter_cnt;
+    /** Chip ID */
+    t_u8 chip_id;
+    /** band config */
+    t_u8 band_config;
+    /** Channel num */
+    t_u8 channel;
+    /** Enable getting CSI data on special channel */
+    t_u8 csi_monitor_enable;
+    /** CSI data received in cfg channel with mac addr filter, not only RA is us or other*/
+    t_u8 ra4us;
+    /** CSI filters */
+    wifi_csi_filter_t csi_filter[CSI_FILTER_MAX];
+} PACK_END wifi_csi_config_params_t;
+#endif /* CSI_SUPPORT */
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+/** Wi-Fi independent reset config */
+typedef PACK_START struct
+{
+    /** reset mode enable/ disable */
+    t_u8 ir_mode;
+    /** gpio pin */
+    t_u8 gpio_pin;
+} PACK_END wifi_indrst_cfg_t;
+#endif
+
+#if CONFIG_INACTIVITY_TIMEOUT_EXT
+/** Type definition of wifi_inactivity_to
+ *  for MLAN_OID_PM_CFG_INACTIVITY_TO
+ */
+typedef PACK_START struct
+{
+    /** Timeout unit in microsecond, 0 means 1000us (1ms) */
+    t_u32 timeout_unit;
+    /** Inactivity timeout for unicast data */
+    t_u32 unicast_timeout;
+    /** Inactivity timeout for multicast data */
+    t_u32 mcast_timeout;
+    /** Timeout for additional Rx traffic after Null PM1 packet exchange */
+    t_u32 ps_entry_timeout;
+    /** Inactivity timeout for cmd */
+    t_u32 ps_cmd_timeout;
+} PACK_END wifi_inactivity_to_t;
+#endif
+
+#if CONFIG_AUTO_NULL_TX
+/** auto null tx information */
+typedef struct
+{
+    /** 1-start 0-stop */
+    t_u8 start;
+    /** bit15:14 unit: 00-s 01-us 10-ms 11-one_shot  bit13-0: interval */
+    t_u16 interval;
+    /** bit7-4: bandwidth. bit3-0: priority, ignored if non-WMM */
+    t_u8 priority;
+    /** Destination MAC address */
+    t_u8 dst_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Source MAC address */
+    t_u8 src_mac[MLAN_MAC_ADDR_LENGTH];
+} wifi_auto_null_tx_t;
+#endif
+
+#if defined(RW610) && (CONFIG_ANT_DETECT)
+#define NORMAL_DETECT_MODE                 0
+#define QUICK_DETECT_MODE                  1
+#define PCB_DETECT_MODE                    2
+#define PCB_DETECT_MODE_CHECK_DEVICE_COUNT 2
+#define ANT_DETECT_MAX_SCAN_ENTRY          5
+#define MAX_ANTENNA_PORT_NUM               4
+typedef PACK_START struct _scan_result_entry_t
+{
+    char ssid[33];
+    unsigned int ssid_len;
+    char bssid[6];
+    unsigned int channel;
+    unsigned char rssi;
+} PACK_END scan_result_entry_t;
+
+typedef PACK_START struct _wlan_ant_info_t
+{
+    uint8_t scan_done;
+    unsigned char avg_rssi;
+    uint8_t entry_idx;
+    scan_result_entry_t scan_entry[ANT_DETECT_MAX_SCAN_ENTRY];
+} PACK_END wlan_ant_scan_info_t;
+
+typedef PACK_START struct _cfg_scan_channel_list_t
+{
+    uint8_t num_channels;
+    uint8_t chan_number[ANT_DETECT_MAX_CHANNEL_LIST];
+} PACK_END cfg_scan_channel_list_t;
+
+typedef PACK_START struct _wlan_ant_detect_data_t
+{
+    uint8_t detect_mode;
+    int detect_done;
+    uint16_t current_ant;
+    uint8_t ant_port_count;
+    uint16_t best_ant;
+    uint16_t next_best_ant;
+    cfg_scan_channel_list_t *channel_list;
+    wlan_ant_scan_info_t scan_info[MAX_ANTENNA_PORT_NUM];
+} PACK_END wlan_ant_detect_data_t;
+#endif
+
+#endif /* __WIFI_DECL_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi.h
new file mode 100644
index 0000000000..77f1fd9df0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi.h
@@ -0,0 +1,1891 @@
+/*
+ * Copyright 2008-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file  wifi.h
+ *\brief This file provides interface for Wi-Fi driver
+ */
+
+#ifndef __WIFI_H__
+#define __WIFI_H__
+
+#include <wifi_config_default.h>
+
+#ifdef __ZEPHYR__
+#include "nxp_wifi.h"
+#endif
+
+#ifndef __ZEPHYR__
+#if !CONFIG_STA_AUTO_DHCPV4
+#define CONFIG_STA_AUTO_DHCPV4 1
+#endif
+#endif
+
+#ifndef __ZEPHYR__
+#if !CONFIG_WIFI_STA_RECONNECT
+#define CONFIG_WIFI_STA_RECONNECT 1
+#endif
+#endif
+
+#define CONFIG_GTK_REKEY_OFFLOAD 0
+
+
+#if defined(SD9177)
+#define CONFIG_TCP_ACK_ENH 1
+#define CONFIG_FW_VDLL     1
+#if !CONFIG_WIFI_CAPA
+#undef CONFIG_WIFI_CAPA
+#define CONFIG_WIFI_CAPA 1
+#endif
+
+#if CONFIG_11AX
+#if !CONFIG_11K
+#define CONFIG_11K 1
+#endif
+#if !CONFIG_11V
+#define CONFIG_11V 1
+#endif
+#endif
+#endif
+
+#include <wifi-decl.h>
+#include <wifi_events.h>
+#include <osa.h>
+#include <wmerrno.h>
+
+#define WIFI_REG8(x)  (*(volatile unsigned char *)(x))
+#define WIFI_REG16(x) (*(volatile unsigned short *)(x))
+#define WIFI_REG32(x) (*(volatile unsigned int *)(x))
+
+#define WIFI_WRITE_REG8(reg, val)  (WIFI_REG8(reg) = (val))
+#define WIFI_WRITE_REG16(reg, val) (WIFI_REG16(reg) = (val))
+#define WIFI_WRITE_REG32(reg, val) (WIFI_REG32(reg) = (val))
+
+#ifdef RW610
+#define WLAN_CAU_ENABLE_ADDR         (0x45004008U)
+#define WLAN_CAU_TEMPERATURE_ADDR    (0x4500400CU)
+#define WLAN_CAU_TEMPERATURE_FW_ADDR (0x41382490U)
+#define WLAN_FW_WAKE_STATUS_ADDR     (0x40031068U)
+#endif
+
+#ifdef RW610
+#define RW610_PACKAGE_TYPE_QFN 0
+#define RW610_PACKAGE_TYPE_CSP 1
+#define RW610_PACKAGE_TYPE_BGA 2
+#endif
+
+#define WIFI_COMMAND_RESPONSE_WAIT_MS 20000
+
+#define BANDWIDTH_20MHZ 1U
+#define BANDWIDTH_40MHZ 2U
+#if CONFIG_11AC
+#define BANDWIDTH_80MHZ 3U
+#endif
+
+#define MAX_NUM_CHANS_IN_NBOR_RPT 6U
+
+/** BIT value */
+#ifndef MBIT
+#define MBIT(x) (((t_u32)1) << (x))
+#endif
+
+#define WIFI_MGMT_DIASSOC MBIT(10)
+#define WIFI_MGMT_AUTH    MBIT(11)
+#define WIFI_MGMT_DEAUTH  MBIT(12)
+/** BITMAP for Action frame */
+#define WIFI_MGMT_ACTION MBIT(13)
+
+extern t_u8 wifi_tx_status;
+extern t_u8 wifi_tx_block_cnt;
+extern t_u8 wifi_rx_status;
+extern t_u8 wifi_rx_block_cnt;
+
+extern int16_t g_bcn_nf_last;
+extern uint8_t g_rssi;
+extern uint16_t g_data_nf_last;
+extern uint16_t g_data_snr_last;
+
+#if CONFIG_WIFI_RECOVERY
+extern bool wifi_recovery_enable;
+extern t_u16 wifi_recovery_cnt;
+#endif
+extern bool wifi_shutdown_enable;
+
+/** Wi-Fi Error Code */
+enum
+{
+    WM_E_WIFI_ERRNO_START = MOD_ERROR_START(MOD_WIFI),
+    /** The Firmware download operation failed. */
+    WIFI_ERROR_FW_DNLD_FAILED,
+    /** The Firmware ready register not set. */
+    WIFI_ERROR_FW_NOT_READY,
+    /** The Wi-Fi card not found. */
+    WIFI_ERROR_CARD_NOT_DETECTED,
+    /** The Wi-Fi Firmware not found. */
+    WIFI_ERROR_FW_NOT_DETECTED,
+};
+
+/** Wi-Fi driver TX/RX data status */
+enum
+{
+    /** Data in running status */
+    WIFI_DATA_RUNNING = 0,
+    /** Data in block status */
+    WIFI_DATA_BLOCK = 1,
+};
+
+typedef enum
+{
+    MGMT_RSN_IE = 48,
+#if CONFIG_11K
+    MGMT_RRM_ENABLED_CAP = 70,
+#endif
+    MGMT_VENDOR_SPECIFIC_221 = 221,
+    MGMT_WPA_IE              = MGMT_VENDOR_SPECIFIC_221,
+    MGMT_WPS_IE              = MGMT_VENDOR_SPECIFIC_221,
+    MGMT_MBO_IE              = MGMT_VENDOR_SPECIFIC_221,
+} IEEEtypes_ElementId_t;
+
+typedef struct wifi_uap_client_disassoc
+{
+    int reason_code;
+    t_u8 sta_addr[MLAN_MAC_ADDR_LENGTH];
+} wifi_uap_client_disassoc_t;
+
+/**
+ * Initialize Wi-Fi driver module.
+ *
+ * Performs SDIO init, downloads Wi-Fi Firmware, creates Wi-Fi Driver
+ * and command response processor thread.
+ *
+ * Also creates mutex, and semaphores used in command and data synchronizations.
+ *
+ * \param[in] fw_start_addr address of stored Wi-Fi Firmware.
+ * \param[in] size Size of Wi-Fi Firmware.
+ *
+ * \return WM_SUCCESS on success or -WM_FAIL on error.
+ *
+ */
+int wifi_init(const uint8_t *fw_start_addr, const size_t size);
+
+/**
+ * Initialize Wi-Fi driver module for FCC Certification.
+ *
+ * Performs SDIO init, downloads Wi-Fi Firmware, creates Wi-Fi Driver
+ * and command response processor thread.
+ *
+ * Also creates mutex, and semaphores used in command and data synchronizations.
+ *
+ * \param[in] fw_start_addr address of stored Manufacturing Wi-Fi Firmware.
+ * \param[in] size Size of Manufacturing Wi-Fi Firmware.
+ *
+ * \return WM_SUCCESS on success or -WM_FAIL on error.
+ *
+ */
+int wifi_init_fcc(const uint8_t *fw_start_addr, const size_t size);
+
+/**
+ * Deinitialize Wi-Fi driver module.
+ *
+ * Performs SDIO deinit, send shutdown command to Wi-Fi Firmware, deletes
+ * Wi-Fi Driver and command processor thread.
+ *
+ * Also deletes mutex and semaphores used in command and data synchronizations.
+ *
+ */
+void wifi_deinit(void);
+#ifdef RW610
+/**
+ * This API can be used to destroy all Wi-Fi driver tasks.
+ */
+void wifi_destroy_wifidriver_tasks(void);
+/**
+ * This API can be used to get IMU task lock.
+ */
+int wifi_imu_get_task_lock(void);
+/**
+ * This API can be used to put IMU task lock.
+ */
+int wifi_imu_put_task_lock(void);
+/**
+ * This API can be used to judge if Wi-Fi firmware is hang.
+ */
+bool wifi_fw_is_hang(void);
+/**
+ * This API can be used to send shutdown command to FW.
+ */
+int wifi_send_shutdown_cmd(void);
+#endif
+/**
+ * This API can be used to set Wi-Fi driver tx status.
+ *
+ * @param[in] status Status to set for TX
+ */
+void wifi_set_tx_status(t_u8 status);
+
+/**
+ * This API can be used to set Wi-Fi driver rx status.
+ *
+ * @param[in] status Status to set for RX
+ *
+ */
+void wifi_set_rx_status(t_u8 status);
+
+/**
+ * This API can be used to reset mgmt_ie_index_bitmap.
+ */
+void reset_ie_index();
+
+/**
+ * Register Data callback function with Wi-Fi Driver to receive
+ * DATA from SDIO.
+ *
+ * This callback function is used to send data received from Wi-Fi
+ * firmware to the networking stack.
+ *
+ * @param[in] data_input_callback Function that needs to be called
+ *
+ * @return WM_SUCCESS
+ */
+int wifi_register_data_input_callback(void (*data_input_callback)(const uint8_t interface,
+                                                                  const uint8_t *buffer,
+                                                                  const uint16_t len));
+
+/** Deregister Data callback function from Wi-Fi Driver */
+void wifi_deregister_data_input_callback(void);
+
+#if FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER
+
+int wifi_register_get_rxbuf_desc_callback(void *(*wifi_get_rxbuf_desc)(t_u16 rx_len));
+
+void wifi_deregister_get_rxbuf_desc_callback(void);
+
+#endif
+
+/**
+ * Register Data callback function with Wi-Fi Driver to receive
+ * processed AMSDU DATA from Wi-Fi driver.
+ *
+ * This callback function is used to send data received from Wi-Fi
+ * firmware to the networking stack.
+ *
+ * @param[in] amsdu_data_input_callback Function that needs to be called
+ *
+ * @return WM_SUCESS
+ *
+ */
+int wifi_register_amsdu_data_input_callback(void (*amsdu_data_input_callback)(uint8_t interface,
+                                                                              uint8_t *buffer,
+                                                                              uint16_t len));
+
+/** Deregister Data callback function from Wi-Fi Driver */
+void wifi_deregister_amsdu_data_input_callback(void);
+
+int wifi_register_deliver_packet_above_callback(void (*deliver_packet_above_callback)(void *rxpd,
+                                                                                      uint8_t interface,
+                                                                                      void *lwip_pbuf));
+
+void wifi_deregister_deliver_packet_above_callback(void);
+
+int wifi_register_wrapper_net_is_ip_or_ipv6_callback(bool (*wrapper_net_is_ip_or_ipv6_callback)(const t_u8 *buffer));
+
+void wifi_deregister_wrapper_net_is_ip_or_ipv6_callback(void);
+
+#if CONFIG_WMM
+int wifi_add_to_bypassq(const t_u8 interface, void *pkt, t_u32 len);
+#endif
+
+/**
+ * Wi-Fi Driver low level output function.
+ *
+ * Data received from upper layer is passed to Wi-Fi Driver for transmission.
+ *
+ * \param[in] interface Interface on which DATA frame will be transmitted.
+ *  0 for Station interface, 1 for uAP interface and 2 for Wi-Fi
+ *  Direct interface.
+ * \param[in] buffer A pointer pointing to DATA frame.
+ * \param[in] len Length of DATA frame.
+ * \param[in] pkt_prio Priority for.sending packet.
+ * \param[in] tid TID for tx.
+ *
+ * \return WM_SUCCESS on success or -WM_E_NOMEM if memory is not available
+ *  or -WM_E_BUSY if SDIO is busy.
+ *
+ */
+int wifi_low_level_output(const uint8_t interface,
+                          const uint8_t *buffer,
+                          const uint16_t len
+#if CONFIG_WMM
+                          ,
+                          uint8_t pkt_prio,
+                          uint8_t tid
+#endif
+);
+
+/**
+ * API to enable packet retries at Wi-Fi driver level.
+ *
+ * This API sets retry count which will be used by Wi-Fi driver to retry packet
+ * transmission in case there was failure in earlier attempt. Failure may
+ * happen due to SDIO write port un-availability or other failures in SDIO
+ * write operation.
+ *
+ * \note Default value of retry count is zero.
+ *
+ * \param[in] count No of retry attempts.
+ *
+ */
+void wifi_set_packet_retry_count(const int count);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when station is a transmitter.
+ */
+void wifi_sta_ampdu_tx_enable(void);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when station is a transmitter.
+ */
+void wifi_sta_ampdu_tx_disable(void);
+
+/**
+ * This API can be used to set tid to enable AMPDU support on the go
+ * when station is a transmitter.
+ * @param[in] tid tid value
+ */
+void wifi_sta_ampdu_tx_enable_per_tid(t_u8 tid);
+
+/**
+ * This API can be used to check if tid to enable AMPDU is allowed
+ * when station is a transmitter.
+ * @param[in] tid tid value
+ * @return MTRUE or MFALSE
+ */
+t_u8 wifi_sta_ampdu_tx_enable_per_tid_is_allowed(t_u8 tid);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when station is a receiver.
+ */
+void wifi_sta_ampdu_rx_enable(void);
+
+/**
+ * This API can be used to set tid to enable AMPDU support on the go
+ * when station is a receiver.
+ * @param[in] tid tid value
+ */
+void wifi_sta_ampdu_rx_enable_per_tid(t_u8 tid);
+
+/**
+ * This API can be used to check if tid to enable AMPDU is allowed
+ * when station is a receiver.
+ * @param[in] tid tid value
+ * @return MTRUE or MFALSE
+ */
+t_u8 wifi_sta_ampdu_rx_enable_per_tid_is_allowed(t_u8 tid);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when uap is a receiver.
+ */
+void wifi_uap_ampdu_rx_enable(void);
+
+/**
+ * This API can be used to set tid to enable AMPDU support on the go
+ * when uap is a receiver.
+ * @param[in] tid tid value
+ */
+void wifi_uap_ampdu_rx_enable_per_tid(t_u8 tid);
+
+/**
+ * This API can be used to check if tid to enable AMPDU is allowed
+ * when uap is a receiver.
+ * @param[in] tid tid value
+ * @return MTRUE or MFALSE
+ */
+t_u8 wifi_uap_ampdu_rx_enable_per_tid_is_allowed(t_u8 tid);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when uap is a receiver.
+ */
+void wifi_uap_ampdu_rx_disable(void);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when uap is a transmitter.
+ */
+void wifi_uap_ampdu_tx_enable(void);
+
+/**
+ * This API can be used to set tid to enable AMPDU support on the go
+ * when uap is a transmitter.
+ * @param[in] tid tid value
+ */
+void wifi_uap_ampdu_tx_enable_per_tid(t_u8 tid);
+
+/**
+ * This API can be used to check if tid to enable AMPDU is allowed
+ * when uap is a transmitter.
+ * @param[in] tid tid value
+ * @return MTRUE or MFALSE
+ */
+t_u8 wifi_uap_ampdu_tx_enable_per_tid_is_allowed(t_u8 tid);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when uap is a transmitter.
+ */
+void wifi_uap_ampdu_tx_disable(void);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when station is a receiver.
+ */
+void wifi_sta_ampdu_rx_disable(void);
+
+/**
+ * Get the device sta MAC address
+ *
+ * @param[out] mac_addr Mac address
+ *
+ * @return WM_SUCESS
+ */
+int wifi_get_device_mac_addr(wifi_mac_addr_t *mac_addr);
+
+/**
+ * Get the device uap MAC address
+ *
+ * @param[out] mac_addr_uap Mac address
+ *
+ * @return WM_SUCESS
+ */
+int wifi_get_device_uap_mac_addr(wifi_mac_addr_t *mac_addr_uap);
+
+/**
+ * Get the cached string representation of the wlan firmware extended version.
+ *
+ * @param[in] fw_ver_ext Firmware Version Extended
+ *
+ * @return WM_SUCCESS
+ */
+int wifi_get_device_firmware_version_ext(wifi_fw_version_ext_t *fw_ver_ext);
+
+/**
+ * Get the timestamp of the last command sent to the firmware
+ *
+ * @return Timestamp in millisec of the last command sent
+ */
+unsigned wifi_get_last_cmd_sent_ms(void);
+
+uint32_t wifi_get_value1(void);
+
+uint8_t *wifi_get_outbuf(uint32_t *outbuf_len);
+
+#if CONFIG_WIFI_TX_PER_TRACK
+int wifi_set_tx_pert(void *cfg, mlan_bss_type bss_type);
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+int wifi_set_txrx_histogram(void *cfg, t_u8 *data);
+#endif
+
+#if CONFIG_ROAMING
+int wifi_config_roaming(const int enable, uint8_t *rssi_low);
+#endif
+int wifi_config_bgscan_and_rssi(const char *ssid);
+mlan_status wifi_stop_bgscan();
+
+/**
+ * This will update the last command sent variable value to current
+ * time. This is used for power management.
+ */
+void wifi_update_last_cmd_sent_ms(void);
+
+/**
+ * Register an event queue with the Wi-Fi driver to receive events
+ *
+ * The list of events which can be received from the Wi-Fi driver are
+ * enumerated in the file wifi_events.h
+ *
+ * @param[in] event_queue The queue to which Wi-Fi driver will post events.
+ *
+ * @note Only one queue can be registered. If the registered queue needs to
+ * be changed unregister the earlier queue first.
+ *
+ * @return Standard SDK return codes
+ */
+int wifi_register_event_queue(osa_msgq_handle_t event_queue);
+
+/**
+ * Unregister an event queue from the Wi-Fi driver.
+ *
+ * @param[in] event_queue The queue to which was registered earlier with
+ * the Wi-Fi driver.
+ *
+ * @return Standard SDK return codes
+ */
+int wifi_unregister_event_queue(osa_msgq_handle_t event_queue);
+
+/** Get scan list
+ *
+ * @param[in] index Index
+ * @param[out] desc Descriptor of type \ref wifi_scan_result2
+ *
+ * @return WM_SUCCESS on success or error code.
+ *
+ */
+int wifi_get_scan_result(unsigned int index, struct wifi_scan_result2 **desc);
+
+/**
+ * Get the count of elements in the scan list
+ *
+ * @param[in,out] count Pointer to a variable which will hold the count after
+ * this call returns
+ *
+ * @warning The count returned by this function is the current count of the
+ * elements. A scan command given to the driver or some other background
+ * event may change this count in the Wi-Fi driver. Thus when the API
+ * \ref wifi_get_scan_result is used to get individual elements of the scan
+ * list, do not assume that it will return exactly 'count' number of
+ * elements. Your application should not consider such situations as a
+ * major event.
+ *
+ * @return Standard SDK return codes.
+ */
+int wifi_get_scan_result_count(unsigned *count);
+
+/**
+ * Returns the current STA list connected to our uAP
+ *
+ * This function gets its information after querying the firmware. It will
+ * block till the response is received from firmware or a timeout.
+ *
+ * @param[in, out] list After this call returns this points to the
+ * structure \ref wifi_sta_list_t allocated by the callee. This is variable
+ * length structure and depends on count variable inside it. <b> The caller
+ * needs to free this buffer after use.</b>. If this function is unable to
+ * get the sta list, the value of list parameter will be NULL
+ *
+ * \note The caller needs to explicitly free the buffer returned by this
+ * function.
+ *
+ * @return void
+ */
+int wifi_uap_bss_sta_list(wifi_sta_list_t **list);
+
+/**
+ * Dsiconnect ex-sta which is connected to in-uap.
+ *
+ * \param[in] mac_addr Mac address of external station.
+ * \param[in] reason_code Deauth reason code.
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_sta_deauth(uint8_t *mac_addr, uint16_t reason_code);
+
+#if CONFIG_RX_ABORT_CFG
+/**
+ * Set/Get Rx abort config
+ *
+ * \param[in] cfg User configurations.
+ * \param[in] action Set/Get
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_get_rx_abort_cfg(void *cfg, t_u16 action);
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+/**
+ * Set/Get Rx abort config ext
+ *
+ * \param[in] cfg User configurations.
+ * \param[in] action Set/Get
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_get_rx_abort_cfg_ext(void *cfg, t_u16 action);
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+/**
+ * Set/Get CCK Desense config
+ *
+ * \param[in] cfg User configurations.
+ * \param[in] action Set/Get
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_get_cck_desense_cfg(void *cfg, t_u16 action);
+#endif
+
+#ifdef WLAN_LOW_POWER_ENABLE
+void wifi_enable_low_pwr_mode();
+#endif
+
+/** Set Wi-Fi calibration data in firmware.
+ *
+ * This function may be used to set Wi-Fi calibration data in firmware.
+ *
+ * @param[in] cdata The calibration data
+ * @param[in] clen Length of calibration data
+ *
+ */
+void wifi_set_cal_data(const uint8_t *cdata, const unsigned int clen);
+
+/** Set Wi-Fi MAC address in firmware at load time.
+ *
+ * This function may be used to set Wi-Fi MAC address in firmware.
+ *
+ * @param[in] mac The new MAC Address
+ *
+ */
+void wifi_set_mac_addr(uint8_t *mac);
+
+/** Set Wi-Fi MAC address in firmware at run time.
+ *
+ * This function may be used to set Wi-Fi MAC address in firmware as per passed bss type.
+ *
+ * @param[in] mac The new MAC Address
+ * @param[in] bss_type BSS Type
+ *
+ */
+void _wifi_set_mac_addr(const uint8_t *mac, mlan_bss_type bss_type);
+
+#if CONFIG_WMM_UAPSD
+int wifi_wmm_qos_cfg(t_u8 *qos_cfg, t_u8 action);
+int wifi_sleep_period(unsigned int *sleep_period, int action);
+#endif
+
+#if CONFIG_WIFI_TX_BUFF
+/**
+ * Check whether the tx buffer size setting is reasonable.
+ *
+ * \param[in]   buf_size The tx buffer size
+ *
+ */
+bool wifi_calibrate_tx_buf_size(uint16_t buf_size);
+void wifi_recfg_tx_buf_size(uint16_t buf_size);
+void _wifi_recfg_tx_buf_size(uint16_t buf_size, mlan_bss_type bss_type);
+#endif
+
+int wifi_get_wpa_ie_in_assoc(uint8_t *wpa_ie);
+
+/** Add Multicast Filter by MAC Address
+ *
+ * Multicast filters should be registered with the Wi-Fi driver for IP-level
+ * multicast addresses to work. This API allows for registration of such filters
+ * with the Wi-Fi driver.
+ *
+ * If multicast-mapped MAC address is 00:12:23:34:45:56 then pass mac_addr as
+ * below:
+ * mac_add[0] = 0x00
+ * mac_add[1] = 0x12
+ * mac_add[2] = 0x23
+ * mac_add[3] = 0x34
+ * mac_add[4] = 0x45
+ * mac_add[5] = 0x56
+ *
+ * \param[in] mac_addr multicast mapped MAC address
+ *
+ * \return 0 on Success or else Error
+ */
+int wifi_add_mcast_filter(uint8_t *mac_addr);
+
+/** Remove Multicast Filter by MAC Address
+ *
+ * This function removes multicast filters for the given multicast-mapped
+ * MAC address. If multicast-mapped MAC address is 00:12:23:34:45:56
+ * then pass mac_addr as below:
+ * mac_add[0] = 0x00
+ * mac_add[1] = 0x12
+ * mac_add[2] = 0x23
+ * mac_add[3] = 0x34
+ * mac_add[4] = 0x45
+ * mac_add[5] = 0x56
+ *
+ * \param[in] mac_addr multicast mapped MAC address
+ *
+ * \return  0 on Success or else Error
+ */
+int wifi_remove_mcast_filter(uint8_t *mac_addr);
+
+/** Get Multicast Mapped Mac address from IPv4
+ *
+ * This function will generate Multicast Mapped MAC address from IPv4
+ * Multicast Mapped MAC address will be in following format:
+ * 1) Higher 24-bits filled with IANA Multicast OUI (01-00-5E)
+ * 2) 24th bit set as Zero
+ * 3) Lower 23-bits filled with IP address (ignoring higher 9bits).
+ *
+ * \param[in] ipaddr ipaddress(input)
+ * \param[in] mac_addr multicast mapped MAC address(output)
+ *
+ */
+void wifi_get_ipv4_multicast_mac(uint32_t ipaddr, uint8_t *mac_addr);
+
+#if CONFIG_IPV6
+/** Get Multicast Mapped Mac address from IPv6 address
+ *
+ * This function will generate Multicast Mapped MAC address from IPv6 address.
+ * Multicast Mapped MAC address will be in following format:
+ * 1) Higher 16-bits filled with IANA Multicast OUI (33-33)
+ * 2) Lower 32-bits filled with last 4 bytes of IPv6 address
+ *
+ * \param[in] ipaddr last 4 bytes of IPv6 address
+ * \param[in] mac_addr multicast mapped MAC address
+ *
+ */
+void wifi_get_ipv6_multicast_mac(uint32_t ipaddr, uint8_t *mac_addr);
+#endif /* CONFIG_IPV6 */
+
+
+#ifndef RW610
+int wifi_set_antenna(t_u32 ant_mode, t_u16 evaluate_time);
+int wifi_get_antenna(t_u32 *ant_mode, t_u16 *evaluate_time, t_u16 *current_antenna);
+#else
+int wifi_set_antenna(t_u32 ant_mode, t_u16 evaluate_time, t_u8 evaluate_mode);
+int wifi_get_antenna(t_u32 *ant_mode, t_u16 *evaluate_time, t_u8 *evaluate_mode, t_u16 *current_antenna);
+#endif
+
+void wifi_process_hs_cfg_resp(t_u8 *cmd_res_buffer);
+enum wifi_event_reason wifi_process_ps_enh_response(t_u8 *cmd_res_buffer, t_u16 *ps_event, t_u16 *action);
+
+int wifi_uap_rates_getset(uint8_t action, char *rates, uint8_t num_rates);
+int wifi_uap_sta_ageout_timer_getset(uint8_t action, uint32_t *sta_ageout_timer);
+int wifi_uap_ps_sta_ageout_timer_getset(uint8_t action, uint32_t *ps_sta_ageout_timer);
+typedef enum
+{
+    REG_MAC = 1,
+    REG_BBP,
+    REG_RF,
+    REG_CAU
+} wifi_reg_t;
+
+int wifi_mem_access(uint16_t action, uint32_t addr, uint32_t *value);
+/*
+ * This function is supposed to be called after scan is complete from wlc
+ * manager.
+ */
+void wifi_scan_process_results(void);
+
+/**
+ * Get the Wi-Fi region code
+ *
+ * This function will return one of the following values in the region_code
+ * variable.\n
+ * 0x10 : US FCC\n
+ * 0x20 : CANADA\n
+ * 0x30 : EU\n
+ * 0x32 : FRANCE\n
+ * 0x40 : JAPAN\n
+ * 0x41 : JAPAN\n
+ * 0x50 : China\n
+ * 0xfe : JAPAN\n
+ * 0xff : Special\n
+ *
+ * @param[out] region_code Region Code
+ *
+ * @return Standard WMSDK return codes.
+ */
+int wifi_get_region_code(t_u32 *region_code);
+
+/**
+ * Set the Wi-Fi region code.
+ *
+ * This function takes one of the values from the following array.\n
+ * 0x10 : US FCC\n
+ * 0x20 : CANADA\n
+ * 0x30 : EU\n
+ * 0x32 : FRANCE\n
+ * 0x40 : JAPAN\n
+ * 0x41 : JAPAN\n
+ * 0x50 : China\n
+ * 0xfe : JAPAN\n
+ * 0xff : Special\n
+ *
+ * @param[in] region_code Region Code
+ *
+ * @return Standard WMSDK return codes.
+ */
+int wifi_set_region_code(t_u32 region_code);
+
+/**
+ * Set/Get country code
+ * \param[in] alpha2 country code in 3bytes string, 2bytes country code and 1byte 0
+ *            WW : World Wide Safe
+ *            US : US FCC
+ *            CA : IC Canada
+ *            SG : Singapore
+ *            EU : ETSI
+ *            AU : Australia
+ *            KR : Republic Of Korea
+ *            FR : France
+ *            JP : Japan
+ *            CN : China
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_country_code(const char *alpha2);
+int wifi_get_country_code(char *alpha2);
+int wifi_set_country_ie_ignore(uint8_t *ignore);
+
+/**
+ * Get the uAP channel number
+ *
+ *
+ * @param[in] channel Pointer to channel number. Will be initialized by
+ * callee
+ * @return Standard WMSDK return code
+ */
+int wifi_get_uap_channel(int *channel);
+
+/**
+ * Get/Set the uAP mfpc and mfpr
+ *
+ * @param[in] action
+ *
+ * \param[in, out] mfpc Management Frame Protection Capable (MFPC)
+ *                       1: Management Frame Protection Capable
+ *                       0: Management Frame Protection not Capable
+ * \param[in, out] mfpr Management Frame Protection Required (MFPR)
+ *                       1: Management Frame Protection Required
+ *                       0: Management Frame Protection Optional
+ *
+ * @return cmd response status
+ */
+int wifi_uap_pmf_getset(uint8_t action, uint8_t *mfpc, uint8_t *mfpr);
+
+/**
+ * enable/disable 80211d domain feature for the uAP.
+ *
+ * @note This API only set 80211d domain feature.
+ * The actual application will happen only during
+ * starting phase of uAP. So, if the uAP is already started then the
+ * configuration will not apply till uAP re-start.
+ *
+ * @return WM_SUCCESS on success or error code.
+ *
+ */
+int wifi_uap_enable_11d_support();
+bool wifi_11d_is_channel_allowed(int channel);
+wifi_sub_band_set_t *get_sub_band_from_region_code(int region_code, t_u8 *nr_sb);
+#if CONFIG_5GHz_SUPPORT
+wifi_sub_band_set_t *get_sub_band_from_region_code_5ghz(int region_code, t_u8 *nr_sb);
+#endif
+
+int wifi_enable_11d_support();
+int wifi_enable_uap_11d_support();
+int wifi_disable_11d_support();
+int wifi_disable_uap_11d_support();
+
+#ifdef OTP_CHANINFO
+int wifi_get_fw_region_and_cfp_tables(void);
+void wifi_free_fw_region_and_cfp_tables(void);
+#endif
+#if CONFIG_COMPRESS_TX_PWTBL
+int wifi_set_region_power_cfg(const t_u8 *data, t_u16 len);
+#endif
+int wifi_set_txbfcap(unsigned int tx_bf_cap);
+int wifi_set_htcapinfo(unsigned int htcapinfo);
+int wifi_set_httxcfg(unsigned short httxcfg);
+void wifi_uap_set_httxcfg(const t_u16 ht_tx_cfg);
+int wifi_uap_set_httxcfg_int(unsigned short httxcfg);
+int wifi_get_tx_power(t_u32 *power_level);
+int wifi_set_tx_power(t_u32 power_level);
+int wrapper_wlan_cmd_get_hw_spec(void);
+/* fixme: These need to be removed later after complete mlan integration */
+void set_event_chanswann(void);
+void clear_event_chanswann(void);
+void wifi_set_ps_cfg(t_u16 multiple_dtims,
+                     t_u16 bcn_miss_timeout,
+                     t_u16 local_listen_interval,
+                     t_u16 adhoc_wake_period,
+                     t_u16 mode,
+                     t_u16 delay_to_ps);
+int wifi_send_hs_cfg_cmd(mlan_bss_type interface, t_u32 ipv4_addr, t_u16 action, t_u32 conditions);
+#if CONFIG_HOST_SLEEP
+int wifi_cancel_host_sleep(mlan_bss_type interface);
+#endif
+bool wrapper_wlan_11d_support_is_enabled(void);
+void wrapper_wlan_11d_clear_parsedtable(void);
+void wrapper_clear_media_connected_event(void);
+int wifi_uap_ps_inactivity_sleep_exit(mlan_bss_type type);
+int wifi_uap_ps_inactivity_sleep_enter(mlan_bss_type type,
+                                       unsigned int ctrl_bitmap,
+                                       unsigned int min_sleep,
+                                       unsigned int max_sleep,
+                                       unsigned int inactivity_to,
+                                       unsigned int min_awake,
+                                       unsigned int max_awake);
+int wifi_enter_ieee_power_save(void);
+int wifi_exit_ieee_power_save(void);
+#if (CONFIG_WNM_PS)
+int wifi_enter_wnm_power_save(t_u16 wnm_sleep_time);
+int wifi_exit_wnm_power_save(void);
+#endif
+int wifi_enter_deepsleep_power_save(void);
+int wifi_exit_deepsleep_power_save(void);
+int wifi_set_power_save_mode(void);
+int wifi_get_wakeup_reason(t_u16 *hs_wakeup_reason);
+void send_sleep_confirm_command(mlan_bss_type interface);
+void wifi_configure_listen_interval(int listen_interval);
+void wifi_configure_delay_to_ps(unsigned int timeout_ms);
+unsigned short wifi_get_listen_interval();
+unsigned int wifi_get_delay_to_ps();
+void wifi_configure_null_pkt_interval(unsigned int null_pkt_interval);
+int wrapper_wifi_assoc(
+    const unsigned char *bssid, int wlan_security, bool is_wpa_tkip, unsigned int owe_trans_mode, bool is_ft);
+#if CONFIG_WIFI_UAP_WORKAROUND_STICKY_TIM
+void wifi_uap_enable_sticky_bit(const uint8_t *mac_addr);
+#endif /* CONFIG_WIFI_UAP_WORKAROUND_STICKY_TIM */
+bool wifi_get_xfer_pending(void);
+void wifi_set_xfer_pending(bool xfer_val);
+int wrapper_wlan_cmd_11n_ba_stream_timeout(void *saved_event_buff);
+
+int wifi_set_txratecfg(wifi_ds_rate ds_rate, mlan_bss_type bss_type);
+int wifi_get_txratecfg(wifi_ds_rate *ds_rate, mlan_bss_type bss_type);
+void wifi_wake_up_card(uint32_t *resp);
+void wifi_tx_card_awake_lock(void);
+void wifi_tx_card_awake_unlock(void);
+#ifdef RW610
+uint32_t wifi_get_board_type();
+#endif
+#if CONFIG_WPA2_ENTP
+void wifi_scan_enable_wpa2_enterprise_ap_only();
+#endif
+
+
+int wrapper_wlan_11d_enable(t_u32 state);
+int wrapper_wlan_uap_11d_enable(t_u32 state);
+
+int wifi_11h_enable(void);
+
+int wrapper_wlan_cmd_11n_addba_rspgen(void *saved_event_buff);
+
+int wrapper_wlan_cmd_11n_delba_rspgen(void *saved_event_buff);
+
+int wrapper_wlan_ecsa_enable(void);
+
+int wifi_uap_start(mlan_bss_type type,
+                   char *ssid,
+                   uint8_t *mac_addr,
+                   int security,
+                   int key_mgmt,
+                   char *passphrase,
+                   char *password,
+                   int channel,
+                   wifi_scan_chan_list_t scan_chan_list,
+                   uint8_t pwe_derivation,
+                   uint8_t transition_disable,
+                   bool mfpc,
+#if CONFIG_WIFI_DTIM_PERIOD
+                   bool mfpr,
+                   uint8_t dtim
+#else
+                   bool mfpr
+#endif
+);
+
+int wrapper_wlan_sta_ampdu_enable(
+#if CONFIG_WMM
+    t_u8 tid
+#endif
+);
+
+int wrapper_wlan_uap_ampdu_enable(uint8_t *addr
+#if CONFIG_WMM
+                                  ,
+                                  t_u8 tid
+#endif
+);
+
+
+#if CONFIG_WIFI_GET_LOG
+/** Wi-Fi Statistics counter */
+typedef PACK_START struct
+{
+    /** Multicast transmitted frame count */
+    t_u32 mcast_tx_frame;
+    /** Failure count */
+    t_u32 failed;
+    /** Retry count */
+    t_u32 retry;
+    /** Multi entry count */
+    t_u32 multi_retry;
+    /** Duplicate frame count */
+    t_u32 frame_dup;
+    /** RTS success count */
+    t_u32 rts_success;
+    /** RTS failure count */
+    t_u32 rts_failure;
+    /** Ack failure count */
+    t_u32 ack_failure;
+    /** Rx fragmentation count */
+    t_u32 rx_frag;
+    /** Multicast Tx frame count */
+    t_u32 mcast_rx_frame;
+    /** FCS error count */
+    t_u32 fcs_error;
+    /** Tx frame count */
+    t_u32 tx_frame;
+    /** WEP ICV error count */
+    t_u32 wep_icv_error[4];
+    /** beacon recv count */
+    t_u32 bcn_rcv_cnt;
+    /** beacon miss count */
+    t_u32 bcn_miss_cnt;
+    /** received amsdu count*/
+    t_u32 amsdu_rx_cnt;
+    /** received msdu count in amsdu*/
+    t_u32 msdu_in_rx_amsdu_cnt;
+    /** tx amsdu count*/
+    t_u32 amsdu_tx_cnt;
+    /** tx msdu count in amsdu*/
+    t_u32 msdu_in_tx_amsdu_cnt;
+    /** Tx frag count */
+    t_u32 tx_frag_cnt;
+    /** Qos Tx frag count */
+    t_u32 qos_tx_frag_cnt[8];
+    /** Qos failed count */
+    t_u32 qos_failed_cnt[8];
+    /** Qos retry count */
+    t_u32 qos_retry_cnt[8];
+    /** Qos multi retry count */
+    t_u32 qos_multi_retry_cnt[8];
+    /** Qos frame dup count */
+    t_u32 qos_frm_dup_cnt[8];
+    /** Qos rts success count */
+    t_u32 qos_rts_suc_cnt[8];
+    /** Qos rts failure count */
+    t_u32 qos_rts_failure_cnt[8];
+    /** Qos ack failure count */
+    t_u32 qos_ack_failure_cnt[8];
+    /** Qos Rx frag count */
+    t_u32 qos_rx_frag_cnt[8];
+    /** Qos Tx frame count */
+    t_u32 qos_tx_frm_cnt[8];
+    /** Qos discarded frame count */
+    t_u32 qos_discarded_frm_cnt[8];
+    /** Qos mpdus Rx count */
+    t_u32 qos_mpdus_rx_cnt[8];
+    /** Qos retry rx count */
+    t_u32 qos_retries_rx_cnt[8];
+    /** CMACICV errors count */
+    t_u32 cmacicv_errors;
+    /** CMAC replays count */
+    t_u32 cmac_replays;
+    /** mgmt CCMP replays count */
+    t_u32 mgmt_ccmp_replays;
+    /** TKIP ICV errors count */
+    t_u32 tkipicv_errors;
+    /** TKIP replays count */
+    t_u32 tkip_replays;
+    /** CCMP decrypt errors count */
+    t_u32 ccmp_decrypt_errors;
+    /** CCMP replays count */
+    t_u32 ccmp_replays;
+    /** Tx amsdu count */
+    t_u32 tx_amsdu_cnt;
+    /** failed amsdu count */
+    t_u32 failed_amsdu_cnt;
+    /** retry amsdu count */
+    t_u32 retry_amsdu_cnt;
+    /** multi-retry amsdu count */
+    t_u32 multi_retry_amsdu_cnt;
+    /** Tx octets in amsdu count */
+    t_u64 tx_octets_in_amsdu_cnt;
+    /** amsdu ack failure count */
+    t_u32 amsdu_ack_failure_cnt;
+    /** Rx amsdu count */
+    t_u32 rx_amsdu_cnt;
+    /** Rx octets in amsdu count */
+    t_u64 rx_octets_in_amsdu_cnt;
+    /** Tx ampdu count */
+    t_u32 tx_ampdu_cnt;
+    /** tx mpdus in ampdu count */
+    t_u32 tx_mpdus_in_ampdu_cnt;
+    /** tx octets in ampdu count */
+    t_u64 tx_octets_in_ampdu_cnt;
+    /** ampdu Rx count */
+    t_u32 ampdu_rx_cnt;
+    /** mpdu in Rx ampdu count */
+    t_u32 mpdu_in_rx_ampdu_cnt;
+    /** Rx octets ampdu count */
+    t_u64 rx_octets_in_ampdu_cnt;
+    /** ampdu delimiter CRC error count */
+    t_u32 ampdu_delimiter_crc_error_cnt;
+    /** Rx Stuck Related Info*/
+    /** Rx Stuck Issue count */
+    t_u32 rx_stuck_issue_cnt[2];
+    /** Rx Stuck Recovery count */
+    t_u32 rx_stuck_recovery_cnt;
+    /** Rx Stuck TSF */
+    t_u64 rx_stuck_tsf[2];
+    /** Tx Watchdog Recovery Related Info */
+    /** Tx Watchdog Recovery count */
+    t_u32 tx_watchdog_recovery_cnt;
+    /** Tx Watchdog TSF */
+    t_u64 tx_watchdog_tsf[2];
+    /** Channel Switch Related Info */
+    /** Channel Switch Announcement Sent */
+    t_u32 channel_switch_ann_sent;
+    /** Channel Switch State */
+    t_u32 channel_switch_state;
+    /** Register Class */
+    t_u32 reg_class;
+    /** Channel Number */
+    t_u32 channel_number;
+    /** Channel Switch Mode */
+    t_u32 channel_switch_mode;
+    /** Reset Rx Mac Recovery Count */
+    t_u32 rx_reset_mac_recovery_cnt;
+    /** ISR2 Not Done Count*/
+    t_u32 rx_Isr2_NotDone_Cnt;
+    /** GDMA Abort Count */
+    t_u32 gdma_abort_cnt;
+    /** Rx Reset MAC Count */
+    t_u32 g_reset_rx_mac_cnt;
+    // Ownership error counters
+    /** Error Ownership error count*/
+    t_u32 dwCtlErrCnt;
+    /** Control Ownership error count*/
+    t_u32 dwBcnErrCnt;
+    /** Control Ownership error count*/
+    t_u32 dwMgtErrCnt;
+    /** Control Ownership error count*/
+    t_u32 dwDatErrCnt;
+    /** BIGTK MME good count*/
+    t_u32 bigtk_mmeGoodCnt;
+    /** BIGTK Replay error count*/
+    t_u32 bigtk_replayErrCnt;
+    /** BIGTK MIC error count*/
+    t_u32 bigtk_micErrCnt;
+    /** BIGTK MME not included count*/
+    t_u32 bigtk_mmeNotFoundCnt;
+    /** RX unicast count */
+    t_u32 rx_unicast_cnt;
+    /** TX Buffer Overrun Dropped Count */
+    t_u32 tx_overrun_cnt;
+    /** RX Buffer Overrun Dropped Count */
+    t_u32 rx_overrun_cnt;
+} PACK_END wifi_pkt_stats_t;
+
+int wifi_get_log(wifi_pkt_stats_t *stats, mlan_bss_type bss_type);
+#endif
+
+int wifi_set_packet_filters(wifi_flt_cfg_t *flt_cfg);
+
+int wifi_uap_stop();
+#if CONFIG_WPA_SUPP_AP
+int wifi_uap_do_acs(const int *freq_list);
+#else
+int wifi_uap_do_acs(const int *freq_list, const t_u16 acs_band);
+#endif
+
+#if CONFIG_WIFI_CAPA
+/**
+ * Set uAP capability
+ *
+ * User can set uAP capability of 11ax/11ac/11n/legacy. Default is 11ax.
+ *
+ * @param[in] wlan_capa uAP capability bitmap.
+ *                      1111 - 11AX
+ *                      0111 - 11AC
+ *                      0011 - 11N
+ *                      0001 - legacy
+ *
+ */
+void wifi_uap_config_wifi_capa(uint8_t wlan_capa);
+void wifi_get_fw_info(mlan_bss_type type, t_u16 *fw_bands);
+#endif
+int wifi_get_data_rate(wifi_ds_rate *ds_rate, mlan_bss_type bss_type);
+
+int wifi_uap_set_bandwidth(const t_u8 bandwidth);
+
+t_u8 wifi_uap_get_bandwidth();
+
+int wifi_uap_get_pmfcfg(t_u8 *mfpc, t_u8 *mfpr);
+
+int wifi_uap_get_pmfcfg(t_u8 *mfpc, t_u8 *mfpr);
+
+
+int wifi_set_rts(int rts, mlan_bss_type bss_type);
+
+#if CONFIG_WIFI_FRAG_THRESHOLD
+int wifi_set_frag(int frag, mlan_bss_type bss_type);
+#endif
+
+#if CONFIG_11R
+bool wifi_same_ess_ft();
+#endif
+
+
+#if CONFIG_11K
+#define BEACON_REPORT_BUF_SIZE 1400
+
+/* Reporting Detail values */
+enum wlan_rrm_beacon_reporting_detail
+{
+    WLAN_RRM_REPORTING_DETAIL_NONE                    = 0,
+    WLAN_RRM_REPORTING_DETAIL_AS_REQUEST              = 1,
+    WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS = 2,
+};
+
+typedef struct _wlan_rrm_beacon_report_data
+{
+    t_u8 token;
+    t_u8 ssid[MLAN_MAX_SSID_LENGTH];
+    t_u8 ssid_length;
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    t_u8 channel[MAX_CHANNEL_LIST];
+    t_u8 channel_num;
+    t_u8 last_ind;
+    t_u16 duration;
+    enum wlan_rrm_beacon_reporting_detail report_detail;
+    t_u8 bits_field[32];
+} wlan_rrm_beacon_report_data;
+
+typedef struct _wlan_rrm_scan_cb_param
+{
+    wlan_rrm_beacon_report_data rep_data;
+    t_u8 dialog_tok;
+    t_u8 dst_addr[MLAN_MAC_ADDR_LENGTH];
+    t_u8 protect;
+} wlan_rrm_scan_cb_param;
+
+int wifi_host_11k_cfg(int enable_11k);
+
+int wifi_host_11k_neighbor_req(const char *ssid);
+#endif
+
+#if CONFIG_11V
+int wifi_host_11v_bss_trans_query(t_u8 query_reason);
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V)
+/* Neighbor List Mode values */
+enum wlan_nlist_mode
+{
+#if (CONFIG_11K)
+    WLAN_NLIST_11K = 1,
+#endif
+#if (CONFIG_11V)
+    WLAN_NLIST_11V           = 2,
+    WLAN_NLIST_11V_PREFERRED = 3,
+#endif
+};
+
+#define MAX_NEIGHBOR_AP_LIMIT 6U
+
+typedef struct _wlan_rrm_neighbor_ap_t
+{
+    char ssid[MLAN_MAX_SSID_LENGTH];
+    t_u8 bssid[MLAN_MAX_SSID_LENGTH];
+    t_u8 bssidInfo[32];
+    int op_class;
+    int channel;
+    int phy_type;
+    int freq;
+} wlan_rrm_neighbor_ap_t;
+
+typedef struct _wlan_neighbor_report_t
+{
+    wlan_rrm_neighbor_ap_t neighbor_ap[MAX_NEIGHBOR_AP_LIMIT];
+    int neighbor_cnt;
+} wlan_rrm_neighbor_report_t;
+
+typedef struct _wlan_nlist_report_param
+{
+    enum wlan_nlist_mode nlist_mode;
+    t_u8 num_channels;
+    t_u8 channels[MAX_NUM_CHANS_IN_NBOR_RPT];
+#if (CONFIG_11V)
+    t_u8 btm_mode;
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    t_u8 dialog_token;
+    t_u8 dst_addr[MLAN_MAC_ADDR_LENGTH];
+    t_u8 protect;
+#endif
+} wlan_nlist_report_param;
+#endif
+
+int wifi_clear_mgmt_ie(mlan_bss_type bss_type, IEEEtypes_ElementId_t index, int mgmt_bitmap_index);
+
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+int wifi_set_sta_mac_filter(int filter_mode, int mac_count, unsigned char *mac_addr);
+#endif
+
+int wifi_set_auto_arp(t_u32 *ipv4_addr);
+
+int wifi_tcp_keep_alive(wifi_tcp_keep_alive_t *keep_alive, t_u8 *src_mac, t_u32 src_ip);
+
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+int wifi_cloud_keep_alive(wifi_cloud_keep_alive_t *keep_alive, t_u16 action, t_u8 *enable);
+#endif
+
+#if CONFIG_HOST_SLEEP
+int wifi_set_packet_filters(wifi_flt_cfg_t *flt_cfg);
+int wakelock_get(void);
+int wakelock_put(void);
+int wakelock_isheld(void);
+void wifi_print_wakeup_reason(t_u16 hs_wakeup_reason);
+void wifi_clear_wakeup_reason(void);
+#endif
+
+int wifi_raw_packet_send(const t_u8 *packet, t_u32 length);
+
+int wifi_raw_packet_recv(t_u8 **data, t_u32 *pkt_type);
+
+#if CONFIG_11AX
+int wifi_set_11ax_tx_omi(const mlan_bss_type bss_type,
+                         const t_u16 tx_omi,
+                         const t_u8 tx_option,
+                         const t_u8 num_data_pkts);
+int wifi_set_11ax_tol_time(const t_u32 tol_time);
+int wifi_set_11ax_rutxpowerlimit(const void *rutx_pwr_cfg, uint32_t rutx_pwr_cfg_len);
+int wifi_set_11ax_rutxpowerlimit_legacy(const wifi_rutxpwrlimit_t *ru_pwr_cfg);
+int wifi_get_11ax_rutxpowerlimit_legacy(wifi_rutxpwrlimit_t *ru_pwr_cfg);
+/** Set 11ax config params
+ *
+ * \param[in, out] ax_config 11AX config parameters to be sent to Firmware
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_11ax_cfg(wifi_11ax_config_t *ax_config);
+
+#if CONFIG_11AX_TWT
+/** Set btwt config params
+ *
+ * \param[in] btwt_config Broadcast TWT setup parameters to be sent to Firmware
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_btwt_cfg(const wifi_btwt_config_t *btwt_config);
+
+/** Set twt setup config params
+ *
+ * \param[in] twt_setup TWT Setup parameters to be sent to Firmware
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_twt_setup_cfg(const wifi_twt_setup_config_t *twt_setup);
+
+/** Set twt teardown config params
+ *
+ * \param[in] teardown_config TWT Teardown parameters to be sent to Firmware
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_twt_teardown_cfg(const wifi_twt_teardown_config_t *teardown_config);
+
+/** Get twt report
+ *
+ * \param[out] twt_report TWT Report parameters to be sent to Firmware
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_get_twt_report(wifi_twt_report_t *twt_report);
+
+#endif /* CONFIG_11AX_TWT */
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+int wifi_set_clocksync_cfg(const wifi_clock_sync_gpio_tsf_t *tsf_latch, mlan_bss_type bss_type);
+int wifi_get_tsf_info(wifi_tsf_info_t *tsf_info);
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+#if CONFIG_RF_TEST_MODE
+
+int wifi_set_rf_test_mode(void);
+
+int wifi_unset_rf_test_mode(void);
+
+int wifi_set_rf_channel(const uint8_t channel);
+
+int wifi_set_rf_radio_mode(const uint8_t mode);
+
+int wifi_get_rf_channel(uint8_t *channel);
+
+int wifi_get_rf_radio_mode(uint8_t *mode);
+
+int wifi_set_rf_band(const uint8_t band);
+
+int wifi_get_rf_band(uint8_t *band);
+
+int wifi_set_rf_bandwidth(const uint8_t bandwidth);
+
+int wifi_get_rf_bandwidth(uint8_t *bandwidth);
+
+int wifi_get_rf_per(uint32_t *rx_tot_pkt_count, uint32_t *rx_mcast_bcast_count, uint32_t *rx_pkt_fcs_error);
+
+int wifi_set_rf_tx_cont_mode(const uint32_t enable_tx,
+                             const uint32_t cw_mode,
+                             const uint32_t payload_pattern,
+                             const uint32_t cs_mode,
+                             const uint32_t act_sub_ch,
+                             const uint32_t tx_rate);
+
+int wifi_set_rf_tx_antenna(const uint8_t antenna);
+
+int wifi_get_rf_tx_antenna(uint8_t *antenna);
+
+int wifi_set_rf_rx_antenna(const uint8_t antenna);
+
+int wifi_get_rf_rx_antenna(uint8_t *antenna);
+
+int wifi_set_rf_tx_power(const uint32_t power, const uint8_t mod, const uint8_t path_id);
+
+int wifi_cfg_rf_he_tb_tx(uint16_t enable, uint16_t qnum, uint16_t aid, uint16_t axq_mu_timer, int16_t tx_power);
+
+int wifi_rf_trigger_frame_cfg(uint32_t Enable_tx,
+                              uint32_t Standalone_hetb,
+                              uint8_t FRAME_CTRL_TYPE,
+                              uint8_t FRAME_CTRL_SUBTYPE,
+                              uint16_t FRAME_DURATION,
+                              uint64_t TriggerType,
+                              uint64_t UlLen,
+                              uint64_t MoreTF,
+                              uint64_t CSRequired,
+                              uint64_t UlBw,
+                              uint64_t LTFType,
+                              uint64_t LTFMode,
+                              uint64_t LTFSymbol,
+                              uint64_t UlSTBC,
+                              uint64_t LdpcESS,
+                              uint64_t ApTxPwr,
+                              uint64_t PreFecPadFct,
+                              uint64_t PeDisambig,
+                              uint64_t SpatialReuse,
+                              uint64_t Doppler,
+                              uint64_t HeSig2,
+                              uint32_t AID12,
+                              uint32_t RUAllocReg,
+                              uint32_t RUAlloc,
+                              uint32_t UlCodingType,
+                              uint32_t UlMCS,
+                              uint32_t UlDCM,
+                              uint32_t SSAlloc,
+                              uint8_t UlTargetRSSI,
+                              uint8_t MPDU_MU_SF,
+                              uint8_t TID_AL,
+                              uint8_t AC_PL,
+                              uint8_t Pref_AC);
+
+int wifi_set_rf_tx_frame(const uint32_t enable,
+                         const uint32_t data_rate,
+                         const uint32_t frame_pattern,
+                         const uint32_t frame_length,
+                         const uint16_t adjust_burst_sifs,
+                         const uint32_t burst_sifs_in_us,
+                         const uint32_t short_preamble,
+                         const uint32_t act_sub_ch,
+                         const uint32_t short_gi,
+                         const uint32_t adv_coding,
+                         const uint32_t tx_bf,
+                         const uint32_t gf_mode,
+                         const uint32_t stbc,
+                         const uint8_t *bssid);
+
+int wifi_set_rf_otp_mac_addr(uint8_t *mac);
+
+int wifi_get_rf_otp_mac_addr(uint8_t *mac);
+
+int wifi_set_rf_otp_cal_data(const uint8_t *cal_data, uint32_t cal_data_len);
+
+int wifi_get_rf_otp_cal_data(uint8_t *cal_data);
+#endif
+#if CONFIG_WIFI_FW_DEBUG
+/** This function registers callbacks which are used to generate FW Dump on USB
+ * device.
+ *
+ * \param[in] wifi_usb_mount_cb Callback to mount usb device.
+ * \param[in] wifi_usb_file_open_cb Callback to open file on usb device for FW dump.
+ * \param[in] wifi_usb_file_write_cb Callback to write FW dump data to opened file.
+ * \param[in] wifi_usb_file_close_cb Callback to close FW dump file.
+ *
+ */
+void wifi_register_fw_dump_cb(int (*wifi_usb_mount_cb)(),
+                              int (*wifi_usb_file_open_cb)(char *test_file_name),
+                              int (*wifi_usb_file_write_cb)(uint8_t *data, size_t data_len),
+                              int (*wifi_usb_file_close_cb)());
+#endif
+
+#if CONFIG_WMM
+void wifi_wmm_init();
+t_u32 wifi_wmm_get_pkt_prio(void *buf, t_u8 *tid);
+t_u8 wifi_wmm_get_packet_cnt(void);
+/* handle EVENT_TX_DATA_PAUSE */
+void wifi_handle_event_data_pause(void *data);
+void wifi_wmm_tx_stats_dump(int bss_type);
+#endif /* CONFIG_WMM */
+
+int wifi_set_rssi_low_threshold(uint8_t *low_rssi);
+
+#if CONFIG_HEAP_DEBUG
+/**
+ * Show os mem alloc and free info.
+ *
+ */
+void wifi_show_os_mem_stat();
+#endif
+
+#if CONFIG_WPS2
+/**
+ * enable/disable WPS session
+ *
+ * \param[in] option -- 1 is WPS session START, 0 is WPS session END
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_send_wps_cfg_cmd(int option);
+
+int wps_low_level_output(const uint8_t interface, const uint8_t *buf, const uint16_t len);
+
+#endif /* CONFIG_WPS2 */
+
+
+#if CONFIG_MULTI_CHAN
+/**
+ * Set multi-channel stayed time in us.
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_mc_cfg(uint32_t channel_time);
+
+/**
+ * Get multi-channel stayed time in us.
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_get_mc_cfg(uint32_t *channel_time);
+
+/**
+ * Set multi-channel status disable/enable.
+ * \param[in]      status       status disable/enable
+ * 0-disable, 1-enable
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_mc_policy(const int status);
+/**
+ * Get multi-channel status disable/enable.
+ *
+ * \return status 0-disable, 1-enable.
+ */
+int wifi_get_mc_policy(void);
+
+/**
+ * Set multi-channel config.
+ * \param[in]      num       array length of drcs_cfg[]
+ * \param[in] 	   drcs      multi-channel config, maybe an array
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_mc_cfg_ext(const wifi_drcs_cfg_t *drcs, const int num);
+
+/**
+ * Get multi-channel config.
+ * \param[in]      num       array length of drcs_cfg[]
+ * \param[out]     drcs      multi-channel config, maybe an array
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_get_mc_cfg_ext(wifi_drcs_cfg_t *drcs, int num);
+#endif
+
+/**
+ *Frame Tx - Injecting Wireless frames from Host
+ *
+ * This function is used to Inject Wireless frames from application
+ * directly.
+ *
+ * \note All injected frames will be sent on station interface. Application
+ * needs minimum of 2 KBytes stack for successful operation.
+ * Also application have to take care of allocating buffer for 802.11 Wireless
+ * frame (Header + Data) and freeing allocated buffer. Also this
+ * API may not work when Power Save is enabled on station interface.
+ *
+ * \param[in] bss_type The interface on which management frame needs to be send.
+ * \param[in] buff Buffer holding 802.11 Wireless frame (Header + Data).
+ * \param[in] len Length of the 802.11 Wireless frame.
+ *
+ * \return WM_SUCCESS on success or error code.
+ *
+ **/
+
+int wifi_inject_frame(const enum wlan_bss_type bss_type, const uint8_t *buff, const size_t len);
+
+int wifi_supp_inject_frame(const unsigned int bss_type, const uint8_t *buff, const size_t len);
+#if CONFIG_WPA_SUPP
+void wifi_is_wpa_supplicant_input(const uint8_t interface, const uint8_t *buffer, const uint16_t len);
+void wifi_wpa_supplicant_eapol_input(const uint8_t interface,
+                                     const uint8_t *src_addr,
+                                     const uint8_t *buffer,
+                                     const uint16_t len);
+
+t_u8 wifi_get_sec_channel_offset(unsigned int chan);
+int wifi_nxp_scan_res_get(void);
+int wifi_nxp_survey_res_get(void);
+int wifi_nxp_set_default_scan_ies(const u8 *ies, size_t ies_len);
+void wifi_nxp_reset_scan_flag();
+#endif
+
+#if CONFIG_DRIVER_MBO
+int wifi_host_mbo_cfg(int enable_mbo);
+int wifi_mbo_preferch_cfg(t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1);
+int wifi_mbo_send_preferch_wnm(t_u8 *src_addr, t_u8 *target_bssid, t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1);
+#endif
+
+#if CONFIG_ECSA
+
+/**
+ * Send the ecsa config parameter to FW by TLV.
+ *
+ *\param[in] block_tx 0 -- no need to block traffic,1 -- need block traffic.
+ *\param[in] oper_class Operating class according to IEEE std802.11 spec, when 0 is used, only CSA IE will be used.
+ *\param[in] channel The channel will switch to.
+ *\param[in] switch_count Channel switch time to send ECSA ie.
+ *\param[in] band_width Channel width switch to(optional),only for 5G channels.
+ *\param[in] ecsa True need to get operclass by band_width and channel, Otherwise, no need
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_ecsa_cfg(t_u8 block_tx, t_u8 oper_class, t_u8 channel, t_u8 switch_count, t_u8 band_width, t_u8 ecsa);
+
+/**
+ * Send the ecsa config parameter to FW by action.
+ *
+ *\param[in] block_tx 0 -- no need to block traffic,1 -- need block traffic.
+ *\param[in] oper_class Operating class according to IEEE std802.11 spec, when 0 is used, only CSA IE will be used.
+ *\param[in] channel The channel will switch to.
+ *\param[in] switch_count Channel switch time to send ECSA ie.
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_set_action_ecsa_cfg(t_u8 block_tx, t_u8 oper_class, t_u8 channel, t_u8 switch_count);
+
+/**
+ * Record the ECSA blcok tx time.
+ *
+ *\param[in] switch_count FW expire at switch_count*beacon_period,and then switch to new_channel.
+ *
+ * \return void.
+ */
+void set_ecsa_block_tx_time(t_u8 switch_count);
+
+/**
+ * Get the blcok tx time when need to block traffic.
+ *
+ * \return blcok tx time.
+ */
+t_u8 get_ecsa_block_tx_time();
+
+/**
+ * Record whether block tx is required.
+ *
+ *\param[in] block_tx if block tx is required, block_tx is true. otherwise, flag is false.
+ *
+ * \return void.
+ */
+void set_ecsa_block_tx_flag(bool block_tx);
+
+/**
+ * Get the block tx status.
+ *
+ * \return true block tx is required, false not required.
+ */
+bool get_ecsa_block_tx_flag();
+
+/**
+ * put the ecsa semaphore .
+ *
+ * \return void.
+ */
+void wifi_put_ecsa_sem(void);
+
+/** wifi_ecsa_status_control */
+typedef struct _wifi_ecsa_status_control
+{
+    /** block tx required*/
+    bool required;
+    /** block time of one detect period*/
+    t_u8 block_time;
+    /** Semaphore to wait ECSA complete */
+    OSA_SEMAPHORE_HANDLE_DEFINE(ecsa_sem);
+} wifi_ecsa_status_control;
+#endif
+
+typedef struct _wifi_ecsa_info
+{
+    t_u8 bss_type;
+    t_u8 band_config;
+    /** channel */
+    t_u8 channel;
+} wifi_ecsa_info;
+
+#ifdef RW610
+#if CONFIG_HOST_SLEEP
+extern int wakeup_by;
+#define WAKEUP_BY_WLAN 0x1
+#define WAKEUP_BY_RTC  0x2
+#define WAKEUP_BY_PIN1 0x4
+#endif
+#endif
+
+#if CONFIG_CSI
+/**
+ * Send the csi config parameter to FW.
+ *
+ *\param[in] csi_params Csi config parameter
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_csi_cfg(wifi_csi_config_params_t *csi_params);
+int register_csi_user_callback(int (*csi_data_recv_callback)(void *buffer, size_t len));
+int unregister_csi_user_callback(void);
+void csi_local_buff_init();
+void csi_save_data_to_local_buff(void *data);
+void csi_deliver_data_to_user();
+
+typedef struct _csi_local_buff_statu
+{
+    t_u8 write_index;
+    t_u8 read_index;
+    t_u8 valid_data_cnt;
+    /** Semaphore to protect data parameters */
+    OSA_SEMAPHORE_HANDLE_DEFINE(csi_data_sem);
+} csi_local_buff_statu;
+
+extern int csi_event_cnt;
+extern t_u64 csi_event_data_len;
+#endif
+#if CONFIG_NET_MONITOR
+/**
+ * Send the net monitor config parameter to FW.
+ *
+ *\param[in] monitor Monitor config parameter.
+ *
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wifi_net_monitor_cfg(wifi_net_monitor_t *monitor);
+
+/**
+ * Register user callback to receive monitor data.
+ *
+ *\param[in] monitor_cb User callback function.
+ *
+ * \return void.
+ */
+void register_monitor_user_callback(int (*monitor_cb)(void *frame, t_u16 len));
+
+/**
+ * Deregister user callback for monitor feature.
+ *
+ * \return void.
+ */
+void deregister_monitor_user_callback();
+
+/**
+ * Record the status when start monitor.
+ *
+ *\param[in] flag Flag is true, when in monitor mode,otherwise, flag is false.
+ *
+ * \return void.
+ */
+void set_monitor_flag(bool flag);
+
+/**
+ * Get the monitor status to determine if it is in monitor mode.
+ *
+ * \return true in monitor mode, false in other modes.
+ */
+bool get_monitor_flag();
+
+#endif
+
+int wifi_send_mgmt_auth_request(const t_u8 channel,
+                                const t_u8 auth_alg,
+                                const t_u8 *auth_seq_num,
+                                const t_u8 *status_code,
+                                const t_u8 *dest,
+                                const t_u8 *sae_data,
+                                const t_u16 sae_data_len);
+int wifi_send_scan_cmd(t_u8 bss_mode,
+                       const t_u8 *specific_bssid,
+                       const char *ssid,
+                       uint8_t ssid_num,
+                       const t_u8 num_channels,
+                       const wifi_scan_channel_list_t *chan_list,
+                       const t_u8 num_probes,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                       const t_s16 rssi_threshold,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                       const t_u16 scan_chan_gap,
+#endif
+                       const bool keep_previous_scan,
+                       const bool active_scan_triggered);
+int wifi_deauthenticate(uint8_t *bssid);
+
+#if CONFIG_TURBO_MODE
+int wifi_get_turbo_mode(t_u8 *mode);
+int wifi_get_uap_turbo_mode(t_u8 *mode);
+int wifi_set_turbo_mode(t_u8 mode);
+int wifi_set_uap_turbo_mode(t_u8 mode);
+#endif
+
+#if CONFIG_WPA_SUPP_AP
+t_u16 wifi_get_default_ht_capab();
+t_u32 wifi_get_default_vht_capab();
+
+void wifi_uap_client_assoc(t_u8 *sta_addr, unsigned char is_11n_enabled);
+void wifi_uap_client_deauth(t_u8 *sta_addr);
+
+#endif
+/**
+ *  @brief This function converts region string to region code
+ *
+ *  @param region_string    Region string
+ *
+ *  @return                 Region code
+ */
+t_u8 region_string_2_region_code(t_u8 *region_string);
+
+#if CONFIG_COEX_DUTY_CYCLE
+int wifi_single_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime);
+int wifi_dual_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime, t_u16 wlanBlockTime);
+#endif
+
+#ifdef RW610
+/* get CAU module temperature and write to firmware */
+void wifi_cau_temperature_enable(void);
+int wifi_cau_temperature_write_to_firmware(void);
+int32_t wifi_get_temperature(void);
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+int wifi_set_indrst_cfg(const wifi_indrst_cfg_t *indrst_cfg, mlan_bss_type bss_type);
+int wifi_get_indrst_cfg(wifi_indrst_cfg_t *indrst_cfg, mlan_bss_type bss_type);
+int wifi_test_independent_reset();
+int wifi_trigger_oob_indrst();
+#endif
+
+#if CONFIG_WIFI_BOOT_SLEEP
+int wifi_boot_sleep(uint16_t action, uint16_t *enable);
+#endif
+
+#if CONFIG_AUTO_NULL_TX
+int wifi_auto_null_tx(wifi_auto_null_tx_t *auto_null_tx, mlan_bss_type bss_type);
+#endif
+
+#if CONFIG_WPA_SUPP
+void hostapd_connected_sta_list(wifi_sta_info_t *si, wifi_sta_list_t *sl);
+#endif
+bool wifi_is_remain_on_channel(void);
+
+#endif /* __WIFI_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi_events.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi_events.h
new file mode 100644
index 0000000000..a463fd3a42
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi_events.h
@@ -0,0 +1,240 @@
+/*
+ *  Copyright 2008-2020, 2023-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*! \file wifi_events.h
+ * \brief This file provides Wi-Fi driver event enum.
+ */
+
+#ifndef __WIFI_EVENTS_H__
+#define __WIFI_EVENTS_H__
+
+#include <osa.h>
+
+#if CONFIG_WPA_SUPP
+#define CONFIG_WPA_SUPP_AP 1
+#endif
+
+/** Wi-Fi events */
+enum wifi_event
+{
+    /** uAP Started */
+    WIFI_EVENT_UAP_STARTED = 0,
+    /** uAP Client Assoc */
+    WIFI_EVENT_UAP_CLIENT_ASSOC,
+    /** uAP Client connected */
+    WIFI_EVENT_UAP_CLIENT_CONN,
+    /** uAP Client De-authentication */
+    WIFI_EVENT_UAP_CLIENT_DEAUTH,
+    /** uAP Network Address Configuration */
+    WIFI_EVENT_UAP_NET_ADDR_CONFIG,
+    /** uAP Stopped */
+    WIFI_EVENT_UAP_STOPPED,
+    /** uAP Last */
+    WIFI_EVENT_UAP_LAST,
+    /* All the uAP related events need to be above and STA related events
+     * below */
+    /** Scan start event when scan is started */
+    WIFI_EVENT_SCAN_START,
+    /** Scan Result */
+    WIFI_EVENT_SCAN_RESULT,
+    /** Survey Result Get */
+    WIFI_EVENT_SURVEY_RESULT_GET,
+    /** Get hardware spec */
+    WIFI_EVENT_GET_HW_SPEC,
+    /** Association */
+    WIFI_EVENT_ASSOCIATION,
+#if CONFIG_WPA_SUPP
+#if CONFIG_AUTO_RECONNECT
+    /** Association Notify */
+    WIFI_EVENT_ASSOCIATION_NOTIFY,
+#endif
+#if CONFIG_WPA_SUPP_AP
+    WIFI_EVENT_ACS_COMPLETE,
+#endif
+#endif
+    /** PMK */
+    WIFI_EVENT_PMK,
+    /** Authentication */
+    WIFI_EVENT_AUTHENTICATION,
+    /** Disassociation */
+    WIFI_EVENT_DISASSOCIATION,
+    /** De-authentication */
+    WIFI_EVENT_DEAUTHENTICATION,
+    /** Link Loss */
+    WIFI_EVENT_LINK_LOSS,
+    /* Wi-Fi RSSI Low Event */
+    WIFI_EVENT_RSSI_LOW,
+    /** Firmware Hang event */
+    WIFI_EVENT_FW_HANG,
+    /** Firmware Reset event */
+    WIFI_EVENT_FW_RESET,
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+    /* Wi-Fi RSSI High Event */
+    WIFI_EVENT_RSSI_HIGH,
+    /* Wi-Fi SRN Low Event */
+    WIFI_EVENT_SNR_LOW,
+    /* Wi-Fi SNR High Event */
+    WIFI_EVENT_SNR_HIGH,
+    /* Wi-Fi Max Fail Event */
+    WIFI_EVENT_MAX_FAIL,
+    /* Wi-Fi Beacon miised Event */
+    WIFI_EVENT_BEACON_MISSED,
+    /* Wi-Fi Data RSSI Low Event */
+    WIFI_EVENT_DATA_RSSI_LOW,
+    /* Wi-Fi Data RSSI High Event */
+    WIFI_EVENT_DATA_RSSI_HIGH,
+    /* Wi-Fi Data SNR Low Event */
+    WIFI_EVENT_DATA_SNR_LOW,
+    /* Wi-Fi Data SNR High Event */
+    WIFI_EVENT_DATA_SNR_HIGH,
+    /* Wi-Fi Link Quality Event */
+    WIFI_EVENT_FW_LINK_QUALITY,
+    /* Wi-Fi Pre Beacon Lost Event */
+    WIFI_EVENT_FW_PRE_BCN_LOST,
+#endif
+#if CONFIG_HOST_SLEEP
+    /* Host sleep activated */
+    WIFI_EVENT_HS_ACTIVATED,
+    /** HS configuration */
+    WIFI_EVENT_HS_CONFIG,
+    /* Sleep confirm done */
+    WIFI_EVENT_SLEEP_CONFIRM_DONE,
+#endif
+    /** Network station address configuration */
+    WIFI_EVENT_NET_STA_ADDR_CONFIG,
+    /** Network interface configuration */
+    WIFI_EVENT_NET_INTERFACE_CONFIG,
+    /** WEP configuration */
+    WIFI_EVENT_WEP_CONFIG,
+    /** STA MAC address configuration */
+    WIFI_EVENT_STA_MAC_ADDR_CONFIG,
+    /** UAP MAC address configuration */
+    WIFI_EVENT_UAP_MAC_ADDR_CONFIG,
+    /** Network DHCP configuration */
+    WIFI_EVENT_NET_DHCP_CONFIG,
+    /** Supplicant PMK */
+    WIFI_EVENT_SUPPLICANT_PMK,
+    /** Sleep */
+    WIFI_EVENT_SLEEP,
+    /** IEEE PS */
+    WIFI_EVENT_IEEE_PS,
+    /** Deep Sleep */
+    WIFI_EVENT_DEEP_SLEEP,
+    /** WNM ps */
+    WIFI_EVENT_WNM_PS,
+    /** IEEE and Deep Sleep */
+    WIFI_EVENT_IEEE_DEEP_SLEEP,
+    /** WNM and Deep Sleep */
+    WIFI_EVENT_WNM_DEEP_SLEEP,
+    /** PS Invalid */
+    WIFI_EVENT_PS_INVALID,
+    /** Error Multicast */
+    WIFI_EVENT_ERR_MULTICAST,
+    /** error Unicast */
+    WIFI_EVENT_ERR_UNICAST,
+    /** 802.11K/11V neighbor report */
+    WIFI_EVENT_NLIST_REPORT,
+    /* Add Block Ack */
+    /** 802.11N add block ack */
+    WIFI_EVENT_11N_ADDBA,
+    /** 802.11N block Ack stream timeout */
+    WIFI_EVENT_11N_BA_STREAM_TIMEOUT,
+    /** 802.11n Delete block add */
+    WIFI_EVENT_11N_DELBA,
+    /** 802.11n aggregation control */
+    WIFI_EVENT_11N_AGGR_CTRL,
+    /** Channel Switch Announcement */
+    WIFI_EVENT_CHAN_SWITCH_ANN,
+    /** Channel Switch */
+    WIFI_EVENT_CHAN_SWITCH,
+#if CONFIG_IPV6
+    /** IPv6 address state change */
+    WIFI_EVENT_NET_IPV6_CONFIG,
+#endif
+    /* Background Scan Report */
+    WIFI_EVENT_BG_SCAN_REPORT,
+    /* Background Scan Stop */
+    WIFI_EVENT_BG_SCAN_STOPPED,
+    /* Event to indicate RX Management Frame */
+    WIFI_EVENT_MGMT_FRAME,
+    /* Event to indicate remain on channel started */
+    WIFI_EVENT_REMAIN_ON_CHANNEL,
+    /* Event to indicate Management tx status */
+    WIFI_EVENT_MGMT_TX_STATUS,
+#if CONFIG_CSI
+    /* Recv csi data */
+    WIFI_EVENT_CSI,
+#endif
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+    /* Event to trigger or stop ftm*/
+    WIFI_EVENT_FTM_COMPLETE,
+#if CONFIG_WLS_CSI_PROC
+    WIFI_EVENT_WLS_CSI,
+#endif
+#endif
+    /** Event to set region power*/
+    WIFI_EVENT_REGION_POWER_CFG,
+    /** Event to indicate end of Wi-Fi events */
+    WIFI_EVENT_LAST,
+    /* other events can be added after this, however this must
+       be the last event in the Wi-Fi module */
+};
+
+/** Wi-Fi Event Reason */
+enum wifi_event_reason
+{
+    /** Success */
+    WIFI_EVENT_REASON_SUCCESS,
+    /** Timeout */
+    WIFI_EVENT_REASON_TIMEOUT,
+    /** Failure */
+    WIFI_EVENT_REASON_FAILURE,
+};
+
+/** Network wireless BSS Type */
+enum wlan_bss_type
+{
+    /** Station */
+    WLAN_BSS_TYPE_STA = 0,
+    /** uAP */
+    WLAN_BSS_TYPE_UAP = 1,
+    /** Any */
+    WLAN_BSS_TYPE_ANY = 0xff,
+};
+
+/** Network wireless BSS Role */
+enum wlan_bss_role
+{
+    /** Infrastructure network. The system will act as a station connected
+     *  to an Access Point. */
+    WLAN_BSS_ROLE_STA = 0,
+    /** uAP (micro-AP) network.  The system will act as an uAP node to
+     * which other Wireless clients can connect. */
+    WLAN_BSS_ROLE_UAP = 1,
+    /** Either Infrastructure network or micro-AP network */
+    WLAN_BSS_ROLE_ANY = 0xff,
+};
+
+/** This enum defines various wakeup events
+ * for which wakeup will occur */
+enum wifi_wakeup_event_t
+{
+    /** Wakeup on broadcast  */
+    WIFI_WAKE_ON_ALL_BROADCAST = 1,
+    /** Wakeup on unicast  */
+    WIFI_WAKE_ON_UNICAST = 1 << 1,
+    /** Wakeup on MAC event  */
+    WIFI_WAKE_ON_MAC_EVENT = 1 << 2,
+    /** Wakeup on multicast  */
+    WIFI_WAKE_ON_MULTICAST = 1 << 3,
+    /** Wakeup on ARP broadcast  */
+    WIFI_WAKE_ON_ARP_BROADCAST = 1 << 4,
+    /** Wakeup on receiving a management frame  */
+    WIFI_WAKE_ON_MGMT_FRAME = 1 << 6,
+};
+
+#endif /*__WIFI_EVENTS_H__*/
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi_nxp.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi_nxp.h
new file mode 100644
index 0000000000..68fd549d18
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wifidriver/wifi_nxp.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2008-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file  wifi_nxp.h
+ *\brief This file provides core Wi-Fi function definition for wpa supplicant RTOS driver port layer.
+ */
+
+#ifndef __WIFI_NXP_H__
+#define __WIFI_NXP_H__
+
+#include <stdio.h>
+#include <wm_net.h>
+#if CONFIG_WPA_SUPP
+
+#include <drivers/driver_freertos.h>
+
+typedef struct freertos_wpa_supp_dev_callbk_fns rtos_wpa_supp_dev_callbk_fns;
+
+#if CONFIG_WPA_SUPP_AP
+typedef struct freertos_hostapd_dev_callbk_fns rtos_hostapd_dev_callbk_fns;
+#endif
+
+typedef struct freertos_wpa_supp_dev_ops rtos_wpa_supp_dev_ops;
+
+#if 0
+/* current zephyr implement uses freertos structures */
+#include <drivers/driver_zephyr.h>
+
+typedef struct zep_wpa_supp_dev_callbk_fns rtos_wpa_supp_dev_callbk_fns;
+
+#if CONFIG_WPA_SUPP_AP
+typedef struct zep_hostapd_dev_callbk_fns rtos_hostapd_dev_callbk_fns;
+#endif
+
+typedef struct zep_wpa_supp_dev_ops rtos_wpa_supp_dev_ops;
+#error "Define WPA Supplicant driver interface structs for your RTOS here"
+#endif
+
+struct wifi_nxp_ctx_rtos
+{
+    const struct netif *iface_ctx;
+    void *supp_drv_if_ctx;
+
+    void *hapd_drv_if_ctx;
+    unsigned int bss_type;
+
+    bool scan_in_progress;
+    uint64_t scan_start_tsf;
+    uint8_t scan_start_tsf_bssid[ETH_ALEN];
+
+    unsigned int assoc_freq;
+    uint8_t attempt_bssid[ETH_ALEN];
+    uint8_t assoc_bssid[ETH_ALEN];
+    bool associated;
+    bool uap_started;
+    bool hostapd;
+    rtos_wpa_supp_dev_callbk_fns supp_callbk_fns;
+    bool supp_called_remain_on_chan;
+    unsigned int remain_on_channel_freq;
+    unsigned int remain_on_channel_duration;
+    bool remain_on_chan_is_canceled;
+#if CONFIG_WPA_SUPP_AP
+    rtos_hostapd_dev_callbk_fns hostapd_callbk_fns;
+    int mgmt_tx_status;
+    uint8_t *last_mgmt_tx_data;
+    size_t last_mgmt_tx_data_len;
+#endif
+};
+
+int wifi_supp_init(void);
+void wifi_supp_deinit(void);
+int monitor_start(void);
+void monitor_stop(void);
+void wifi_scan_start(struct wifi_message *msg);
+void wifi_scan_done(struct wifi_message *msg);
+void wifi_process_remain_on_channel(struct wifi_message *msg);
+void wifi_process_mgmt_tx_status(struct wifi_message *msg);
+void wifi_scan_result_get(struct wifi_message *msg);
+void wifi_survey_result_get(struct wifi_message *msg);
+
+#endif /* CONFIG_WPA_SUPP */
+
+#endif /* __WIFI_NXP_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wlcmgr/wlan.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wlcmgr/wlan.h
new file mode 100644
index 0000000000..7cbb301db4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wlcmgr/wlan.h
@@ -0,0 +1,7197 @@
+/*
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*!\file wlan.h
+ *\brief This file provides Wi-Fi APIs for the application.
+ */
+
+#ifndef __WLAN_H__
+#define __WLAN_H__
+
+#ifdef __ZEPHYR__
+#include <nxp_wifi.h>
+#endif
+
+#include <wmtypes.h>
+#include <wmerrno.h>
+#include <stdint.h>
+#include <wifi_events.h>
+#include <wifi.h>
+
+#define WLAN_DRV_VERSION "v1.3.r48.p25"
+
+#if CONFIG_WPA2_ENTP
+#include <wm_mbedtls_helper_api.h>
+#endif
+
+#define ARG_UNUSED(x) (void)(x)
+/* Configuration */
+
+#if !CONFIG_WLAN_KNOWN_NETWORKS
+#define CONFIG_WLAN_KNOWN_NETWORKS 5U
+#endif
+
+#include <wmlog.h>
+#define wlcm_e(...) wmlog_e("wlcm", ##__VA_ARGS__)
+#define wlcm_w(...) wmlog_w("wlcm", ##__VA_ARGS__)
+
+#if CONFIG_WLCMGR_DEBUG
+#define wlcm_d(...) wmlog("wlcm", ##__VA_ARGS__)
+#else
+#define wlcm_d(...)
+#endif /* ! CONFIG_WLCMGR_DEBUG */
+
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION == 1U)))
+
+#if CONFIG_WPA_SUPP
+#error "Static memory allocation is not supported for wpa supplicant "
+#endif
+
+#endif
+
+/** Action GET */
+#define ACTION_GET (0U)
+/** Action SET */
+#define ACTION_SET (1)
+
+/** Maximum SSID length */
+#ifndef IEEEtypes_SSID_SIZE
+#define IEEEtypes_SSID_SIZE 32U
+#endif /* IEEEtypes_SSID_SIZE */
+
+/** MAC Address length */
+#ifndef IEEEtypes_ADDRESS_SIZE
+#define IEEEtypes_ADDRESS_SIZE 6
+#endif /* IEEEtypes_ADDRESS_SIZE */
+
+#if CONFIG_HOST_SLEEP
+#if CONFIG_POWER_MANAGER
+extern osa_msg_handle_t mon_thread_event_queue;
+#endif
+#endif
+
+#define WLAN_REASON_CODE_PREV_AUTH_NOT_VALID 2U
+
+typedef enum
+{
+    BSS_INFRASTRUCTURE = 1,
+    BSS_INDEPENDENT,
+    BSS_ANY
+} IEEEtypes_Bss_t;
+
+/* The possible types of basic service sets */
+
+/** The number of times that the Wi-Fi connection manager look for a
+ *  network before giving up. */
+#if CONFIG_MAX_RESCAN_LIMIT
+#define WLAN_RESCAN_LIMIT CONFIG_MAX_RESCAN_LIMIT
+#else
+#if CONFIG_WPA_SUPP
+#define WLAN_RESCAN_LIMIT 30U
+#else
+#define WLAN_RESCAN_LIMIT 5U
+#endif /* CONFIG_WPA_SUPP */
+#endif /* CONFIG_MAX_RESCAN_LIMIT */
+
+#define WLAN_11D_SCAN_LIMIT 3U
+/** The number of times that the Wi-Fi connection manager attempts a
+ * reconnection with the network before giving up. */
+#ifndef WLAN_RECONNECT_LIMIT
+#define WLAN_RECONNECT_LIMIT 5U
+#endif
+/** The minimum length for network names, see \ref wlan_network. This should
+ *  be between 1 and \ref WLAN_NETWORK_NAME_MAX_LENGTH */
+#define WLAN_NETWORK_NAME_MIN_LENGTH 1U
+/** The space reserved for storing network names, \ref wlan_network */
+#define WLAN_NETWORK_NAME_MAX_LENGTH 32U
+/** The space reserved for storing PSK (password) phrases. */
+/* Min WPA2 passphrase can be upto 8 ASCII chars */
+#define WLAN_PSK_MIN_LENGTH 8U
+/** Max WPA2 passphrase can be upto 63 ASCII chars or 64 hexadecimal digits*/
+#define WLAN_PSK_MAX_LENGTH 65U
+/** Min WPA3 password can be upto 8 ASCII chars */
+#define WLAN_PASSWORD_MIN_LENGTH 8U
+/** Max WPA3 password can be upto 255 ASCII chars */
+#define WLAN_PASSWORD_MAX_LENGTH 255U
+/** Max WPA2 Enterprise identity can be upto 256 characters */
+#define IDENTITY_MAX_LENGTH 64U
+/** Max WPA2 Enterprise password can be upto 256 unicode characters */
+#define PASSWORD_MAX_LENGTH 128U
+/** Max identities for EAP server users */
+#define MAX_USERS 8U
+/** Encryption key for EAP-FAST PAC-Opaque values. This key is a secret, random value. It is configured as a
+ * 16-octet value in hex format. */
+#define PAC_OPAQUE_ENCR_KEY_MAX_LENGTH 33U
+/** A-ID indicates the identity of the authority that issues PACs. The A-ID should be unique across all issuing servers.
+ * A-ID to be 16 octets in length */
+#define A_ID_MAX_LENGTH 33U
+/** MAX CA Cert hash len */
+#define HASH_MAX_LENGTH 40U
+/** MAX domain len */
+#define DOMAIN_MATCH_MAX_LENGTH 64U
+
+#if CONFIG_WLAN_KNOWN_NETWORKS
+/** The size of the list of known networks maintained by the Wi-Fi connection manager */
+#define WLAN_MAX_KNOWN_NETWORKS CONFIG_WLAN_KNOWN_NETWORKS
+#else
+#error "CONFIG_WLAN_KNOWN_NETWORKS is not defined"
+#endif /* CONFIG_WLAN_KNOWN_NETWORKS */
+/** Length of a pairwise master key (PMK).  It's always 256 bits (32 Bytes) */
+#define WLAN_PMK_LENGTH 32
+
+#if CONFIG_WMM_UAPSD
+#define WMM_UAPSD_QOS_INFO     0x0F
+#define WMM_UAPSD_SLEEP_PERIOD 20
+#endif
+
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+
+/* Maximum number of STA filter list can be upto 16 */
+#define WLAN_MAX_STA_FILTER_NUM 16
+
+/* The length of Wi-Fi MAC address */
+#define WLAN_MAC_ADDR_LENGTH 6
+#endif
+
+/** Error codes */
+/** The operation was successful. */
+#define WLAN_ERROR_NONE 0
+/** The operation failed due to an error with one or more parameters. */
+#define WLAN_ERROR_PARAM 1
+/** The operation could not be performed because there is not enough memory. */
+#define WLAN_ERROR_NOMEM 2
+/** The operation could not be performed in the current system state. */
+#define WLAN_ERROR_STATE 3
+/** The operation failed due to an internal error. */
+#define WLAN_ERROR_ACTION 4
+/** The operation to change power state could not be performed*/
+#define WLAN_ERROR_PS_ACTION 5
+/** The requested feature is not supported*/
+#define WLAN_ERROR_NOT_SUPPORTED 6
+
+/*
+ * HOST_WAKEUP_GPIO_PIN / CARD_WAKEUP_GPIO_PIN
+ *
+ *   Default GPIO pin number. This is chip
+ *   specific, and a compile time setting depending on the system
+ *   board level build!
+ */
+#if defined(SD8997) || defined(SD9098) || defined(SD9064) || defined(RW610)
+#define HOST_WAKEUP_GPIO_PIN 12
+#define CARD_WAKEUP_GPIO_PIN 13
+#elif defined(SD9177)
+#define HOST_WAKEUP_GPIO_PIN 17
+#define CARD_WAKEUP_GPIO_PIN 16
+#elif defined(WIFI_88W8987_BOARD_MURATA_1ZM_M2)
+#define HOST_WAKEUP_GPIO_PIN 13
+#define CARD_WAKEUP_GPIO_PIN 16
+#elif defined(WIFI_IW416_BOARD_MURATA_1XK_M2)
+#define HOST_WAKEUP_GPIO_PIN 2
+#define CARD_WAKEUP_GPIO_PIN 16
+#else
+#define HOST_WAKEUP_GPIO_PIN 1
+#define CARD_WAKEUP_GPIO_PIN 16
+#endif
+
+#define WLAN_MGMT_DIASSOC MBIT(10)
+#define WLAN_MGMT_AUTH    MBIT(11)
+#define WLAN_MGMT_DEAUTH  MBIT(12)
+/** BITMAP for Action frame */
+#define WLAN_MGMT_ACTION MBIT(13)
+
+#if CONFIG_WMM_UAPSD
+#define WMM_UAPSD_QOS_INFO     0x0F
+#define WMM_UAPSD_SLEEP_PERIOD 20
+#endif
+
+#define WLAN_KEY_MGMT_IEEE8021X             MBIT(0)
+#define WLAN_KEY_MGMT_PSK                   MBIT(1)
+#define WLAN_KEY_MGMT_NONE                  MBIT(2)
+#define WLAN_KEY_MGMT_IEEE8021X_NO_WPA      MBIT(3)
+#define WLAN_KEY_MGMT_WPA_NONE              MBIT(4)
+#define WLAN_KEY_MGMT_FT_IEEE8021X          MBIT(5)
+#define WLAN_KEY_MGMT_FT_PSK                MBIT(6)
+#define WLAN_KEY_MGMT_IEEE8021X_SHA256      MBIT(7)
+#define WLAN_KEY_MGMT_PSK_SHA256            MBIT(8)
+#define WLAN_KEY_MGMT_WPS                   MBIT(9)
+#define WLAN_KEY_MGMT_SAE                   MBIT(10)
+#define WLAN_KEY_MGMT_FT_SAE                MBIT(11)
+#define WLAN_KEY_MGMT_WAPI_PSK              MBIT(12)
+#define WLAN_KEY_MGMT_WAPI_CERT             MBIT(13)
+#define WLAN_KEY_MGMT_CCKM                  MBIT(14)
+#define WLAN_KEY_MGMT_OSEN                  MBIT(15)
+#define WLAN_KEY_MGMT_IEEE8021X_SUITE_B     MBIT(16)
+#define WLAN_KEY_MGMT_IEEE8021X_SUITE_B_192 MBIT(17)
+#define WLAN_KEY_MGMT_FILS_SHA256           MBIT(18)
+#define WLAN_KEY_MGMT_FILS_SHA384           MBIT(19)
+#define WLAN_KEY_MGMT_FT_FILS_SHA256        MBIT(20)
+#define WLAN_KEY_MGMT_FT_FILS_SHA384        MBIT(21)
+#define WLAN_KEY_MGMT_OWE                   MBIT(22)
+#define WLAN_KEY_MGMT_DPP                   MBIT(23)
+#define WLAN_KEY_MGMT_FT_IEEE8021X_SHA384   MBIT(24)
+#define WLAN_KEY_MGMT_PASN                  MBIT(25)
+#define WLAN_KEY_MGMT_SAE_EXT_KEY           MBIT(26)
+
+#define WLAN_KEY_MGMT_FT                                                                                            \
+    (WLAN_KEY_MGMT_FT_PSK | WLAN_KEY_MGMT_FT_IEEE8021X | WLAN_KEY_MGMT_FT_IEEE8021X_SHA384 | WLAN_KEY_MGMT_FT_SAE | \
+     WLAN_KEY_MGMT_FT_FILS_SHA256 | WLAN_KEY_MGMT_FT_FILS_SHA384)
+
+#if CONFIG_WPA_SUPP
+
+#define WLAN_CIPHER_NONE         MBIT(0)
+#define WLAN_CIPHER_WEP40        MBIT(1)
+#define WLAN_CIPHER_WEP104       MBIT(2)
+#define WLAN_CIPHER_TKIP         MBIT(3)
+#define WLAN_CIPHER_CCMP         MBIT(4)
+#define WLAN_CIPHER_AES_128_CMAC MBIT(5)
+#define WLAN_CIPHER_GCMP         MBIT(6)
+#define WLAN_CIPHER_SMS4         MBIT(7)
+#define WLAN_CIPHER_GCMP_256     MBIT(8)
+#define WLAN_CIPHER_CCMP_256     MBIT(9)
+#define WLAN_CIPHER_BIP_GMAC_128 MBIT(11)
+#define WLAN_CIPHER_BIP_GMAC_256 MBIT(12)
+#define WLAN_CIPHER_BIP_CMAC_256 MBIT(13)
+#define WLAN_CIPHER_GTK_NOT_USED MBIT(14)
+
+#endif
+
+/** Enum for Wi-Fi errors */
+enum wm_wlan_errno
+{
+    WM_E_WLAN_ERRNO_BASE = MOD_ERROR_START(MOD_WLAN),
+    /** The firmware download operation failed. */
+    WLAN_ERROR_FW_DNLD_FAILED,
+    /** The firmware ready register not set. */
+    WLAN_ERROR_FW_NOT_READY,
+    /** The Wi-Fi card not found. */
+    WLAN_ERROR_CARD_NOT_DETECTED,
+    /** The Wi-Fi Firmware not found. */
+    WLAN_ERROR_FW_NOT_DETECTED,
+    /** BSSID not found in scan list */
+    WLAN_BSSID_NOT_FOUND_IN_SCAN_LIST,
+};
+
+/* Events and states */
+
+/** Wi-Fi connection manager event reason */
+enum wlan_event_reason
+{
+    /** The Wi-Fi connection manager has successfully connected to a network and
+     *  is now in the \ref WLAN_CONNECTED state. */
+    WLAN_REASON_SUCCESS,
+    /** The Wi-Fi connection manager has successfully authenticated to a network and
+     *  is now in the \ref WLAN_ASSOCIATED state. */
+    WLAN_REASON_AUTH_SUCCESS,
+    /** The Wi-Fi connection manager failed to connect before actual
+     * connection attempt with AP due to incorrect Wi-Fi network profile.
+     * or the Wi-Fi connection manager failed to reconnect to previously connected
+     * network and it is now in the \ref WLAN_DISCONNECTED state.*/
+    WLAN_REASON_CONNECT_FAILED,
+    /** The Wi-Fi connection manager could not find the network that it was
+     *  connecting to and it is now in the \ref WLAN_DISCONNECTED state. */
+    WLAN_REASON_NETWORK_NOT_FOUND,
+    /** The Wi-Fi connection manager could not find the network in background scan during roam attempt that it was
+     *  connecting to and it is now in the \ref WLAN_CONNECTED state with previous AP. */
+    WLAN_REASON_BGSCAN_NETWORK_NOT_FOUND,
+    /** The Wi-Fi connection manager failed to authenticate with the network
+     *  and is now in the \ref WLAN_DISCONNECTED state. */
+    WLAN_REASON_NETWORK_AUTH_FAILED,
+    /** DHCP lease has been renewed.*/
+    WLAN_REASON_ADDRESS_SUCCESS,
+    /** The Wi-Fi connection manager failed to obtain an IP address
+     *  or TCP stack configuration has failed or the IP address
+     *  configuration was lost due to a DHCP error.  The system is
+     *  now in the \ref WLAN_DISCONNECTED state. */
+    WLAN_REASON_ADDRESS_FAILED,
+    /** The Wi-Fi connection manager has lost the link to the current network. */
+    WLAN_REASON_LINK_LOST,
+    /** The Wi-Fi connection manager has received the channel switch
+     * announcement from the current network. */
+    WLAN_REASON_CHAN_SWITCH,
+    /** The Wi-Fi connection manager has disconnected from the WPS network
+     *  (or has canceled a connection attempt) by request and is now in the
+     *  WLAN_DISCONNECTED state. */
+    WLAN_REASON_WPS_DISCONNECT,
+    /** The Wi-Fi connection manager has disconnected from the current network
+     *  (or has canceled a connection attempt) by request and is now in the
+     *  WLAN_DISCONNECTED state. */
+    WLAN_REASON_USER_DISCONNECT,
+    /** The Wi-Fi connection manager is initialized and is ready for use.
+     *  That is, it's now possible to scan or to connect to a network. */
+    WLAN_REASON_INITIALIZED,
+    /** The Wi-Fi connection manager has failed to initialize and is therefore
+     *  not running. It is not possible to scan or to connect to a network.  The
+     *  Wi-Fi connection manager should be stopped and started again via
+     *  wlan_stop() and wlan_start() respectively. */
+    WLAN_REASON_INITIALIZATION_FAILED,
+#if (CONFIG_WIFI_IND_DNLD)
+    /** The Wi-Fi connection manager has entered in hang mode. */
+    WLAN_REASON_FW_HANG,
+    /** The Wi-Fi connection manager has reset fw successfully. */
+    WLAN_REASON_FW_RESET,
+#endif
+    /** The Wi-Fi connection manager has entered power save mode. */
+    WLAN_REASON_PS_ENTER,
+    /** The Wi-Fi connection manager has exited from power save mode. */
+    WLAN_REASON_PS_EXIT,
+    /** The Wi-Fi connection manager has started UAP */
+    WLAN_REASON_UAP_SUCCESS,
+    /** A Wi-Fi client has joined UAP's BSS network */
+    WLAN_REASON_UAP_CLIENT_ASSOC,
+    /** A Wi-Fi client has auhtenticated and connected to UAP's BSS network */
+    WLAN_REASON_UAP_CLIENT_CONN,
+    /** A Wi-Fi client has left UAP's BSS network */
+    WLAN_REASON_UAP_CLIENT_DISSOC,
+    /** The Wi-Fi connection manager has failed to start UAP */
+    WLAN_REASON_UAP_START_FAILED,
+    /** The Wi-Fi connection manager has failed to stop UAP */
+    WLAN_REASON_UAP_STOP_FAILED,
+    /** The Wi-Fi connection manager has stopped UAP */
+    WLAN_REASON_UAP_STOPPED,
+    /** The Wi-Fi connection manager has received subscribed RSSI low event on station interface as per configured
+       threshold and frequency. If CONFIG_11K, CONFIG_11V, CONFIG_11R or CONFIG_ROAMING enabled then RSSI low event is
+       processed internally.*/
+    WLAN_REASON_RSSI_LOW,
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+    /** The Wi-Fi connection manager has received subscribed RSSI high event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_RSSI_HIGH,
+    /** The Wi-Fi connection manager has received subscribed SNR low event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_SNR_LOW,
+    /** The Wi-Fi connection manager has received subscribed SNR high event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_SNR_HIGH,
+    /** The Wi-Fi connection manager has received subscribed maximum fail event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_MAX_FAIL,
+    /** The Wi-Fi connection manager has received subscribed beacon missed fail event on station interface as per
+       configured threshold and frequency. */
+    WLAN_REASON_BEACON_MISSED,
+    /** The Wi-Fi connection manager has received subscribed data RSSI low event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_DATA_RSSI_LOW,
+    /** The Wi-Fi connection manager has received subscribed data RSSI high event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_DATA_RSSI_HIGH,
+    /** The Wi-Fi connection manager has received subscribed data SNR low event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_DATA_SNR_LOW,
+    /** The Wi-Fi connection manager has received subscribed data SNR high event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_DATA_SNR_HIGH,
+    /** The Wi-Fi connection manager has received subscribed link quality event on station interface as per configured
+    link_snr threshold and frequency, link_rate threshold and frequency, link_tx_latency threshold and frequency*/
+    WLAN_REASON_LINK_QUALITY,
+    /** The Wi-Fi connection manager has received subscribed pre beacon lost event on station interface as per configured
+       threshold and frequency. */
+    WLAN_REASON_PRE_BEACON_LOST,
+#endif
+#if CONFIG_NCP
+    /** Scan is done */
+    WLAN_REASON_SCAN_DONE,
+    /** WPS session is done */
+    WLAN_REASON_WPS_SESSION_DONE,
+#endif
+};
+
+/** Wakeup event bitmap */
+enum wlan_wakeup_event_t
+{
+    /** Wakeup on broadcast  */
+    WAKE_ON_ALL_BROADCAST = 1,
+    /** Wakeup on unicast  */
+    WAKE_ON_UNICAST = 1 << 1,
+    /** Wakeup on MAC event  */
+    WAKE_ON_MAC_EVENT = 1 << 2,
+    /** Wakeup on multicast  */
+    WAKE_ON_MULTICAST = 1 << 3,
+    /** Wakeup on ARP broadcast  */
+    WAKE_ON_ARP_BROADCAST = 1 << 4,
+    /** Wakeup on receiving a management frame  */
+    WAKE_ON_MGMT_FRAME = 1 << 6,
+};
+
+/** Wi-Fi station/UAP/Wi-Fi direct connection/status state */
+enum wlan_connection_state
+{
+    /** The Wi-Fi connection manager is not connected and no connection attempt
+     *  is in progress. It is possible to connect to a network or scan. */
+    WLAN_DISCONNECTED,
+    /** The Wi-Fi connection manager is not connected but it is currently
+     *  attempting to connect to a network.  It is not possible to scan at this
+     *  time.  It is possible to connect to a different network. */
+    WLAN_CONNECTING,
+    /** The Wi-Fi connection manager is not connected but associated. */
+    WLAN_ASSOCIATED,
+    /** The Wi-Fi connection manager is not connected but authenticated. */
+    WLAN_AUTHENTICATED,
+    /** The Wi-Fi connection manager is connected. It is possible to scan and
+     *  connect to another network at this time. Information about the current
+     *  network configuration is available. */
+    WLAN_CONNECTED,
+    /** The Wi-Fi connection manager has started UAP */
+    WLAN_UAP_STARTED,
+    /** The Wi-Fi connection manager has stopped UAP */
+    WLAN_UAP_STOPPED,
+    /** The Wi-Fi connection manager is not connected and network scan
+     * is in progress. */
+    WLAN_SCANNING,
+    /** The Wi-Fi connection manager is not connected and network association
+     * is in progress. */
+    WLAN_ASSOCIATING,
+};
+
+/* Data Structures */
+
+/** Station power save mode */
+typedef enum wlan_ps_mode
+{
+    /** Active mode */
+    WLAN_ACTIVE = 0,
+    /** IEEE power save mode */
+    WLAN_IEEE,
+    /** Deep sleep power save mode */
+    WLAN_DEEP_SLEEP,
+    /** IEEE and deep sleep power save mode */
+    WLAN_IEEE_DEEP_SLEEP,
+#if CONFIG_WNM_PS
+    /** WNM power save mode */
+    WLAN_WNM,
+    /** WNM and Deep sleep power save mode */
+    WLAN_WNM_DEEP_SLEEP,
+#endif
+} wlan_ps_mode;
+
+enum wlan_ps_state
+{
+    PS_STATE_AWAKE = 0,
+    PS_STATE_PRE_SLEEP,
+    PS_STATE_SLEEP_CFM,
+    PS_STATE_SLEEP
+};
+
+typedef enum _ENH_PS_MODES
+{
+    GET_PS        = 0,
+    SLEEP_CONFIRM = 5,
+    EXT_PS_PARAM  = 6,
+#if (CONFIG_WNM_PS)
+    DIS_WNM_PS = 0xfc,
+    EN_WNM_PS  = 0xfd,
+#endif
+    DIS_AUTO_PS = 0xfe,
+    EN_AUTO_PS  = 0xff,
+} ENH_PS_MODES;
+
+typedef enum _Host_Sleep_Action
+{
+    HS_CONFIGURE = 0x0001,
+    HS_ACTIVATE  = 0x0002,
+} Host_Sleep_Action;
+
+#if (CONFIG_WNM_PS)
+typedef PACK_START struct
+{
+    uint8_t action;
+    uint8_t result;
+} PACK_END wnm_sleep_result_t;
+#endif
+
+#if CONFIG_CSI
+enum wlan_csi_opt
+{
+    CSI_FILTER_OPT_ADD = 0,
+    CSI_FILTER_OPT_DELETE,
+    CSI_FILTER_OPT_CLEAR,
+    CSI_FILTER_OPT_DUMP,
+};
+#endif
+
+enum wlan_monitor_opt
+{
+    MONITOR_FILTER_OPT_ADD_MAC = 0,
+    MONITOR_FILTER_OPT_DELETE_MAC,
+    MONITOR_FILTER_OPT_CLEAR_MAC,
+    MONITOR_FILTER_OPT_DUMP,
+};
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+#define FTM_ACTION_START 1
+#define FTM_ACTION_STOP  2
+
+#define PROTO_DOT11AZ_NTB 1
+#define PROTO_DOT11AZ_TB  2
+#define PROTO_DOT11MC     0
+
+/* DOT11MC CFG */
+/* Burst duration
+ 0 - 1: Reserved
+ 2: 250 micro seconds
+ 3: 500 micro seconds
+ 4: 1 ms
+ 5: 2 ms
+ 6: 4 ms
+ 7: 8 ms
+ 8: 16 ms
+ 9: 32 ms
+ 10: 64 ms
+ 11: 128 ms
+ 12-14 reserved*/
+#define BURST_DURATION 11
+/* Burst period in units of 100 milli seconds */
+#define BURST_PERIOD 10
+/* FTM frames per burst */
+#define FTM_PER_BURST 5
+/* Indicates minimum time between consecutive FTM (fine timing measurement) frames. It is specified in in units of 100 micro
+ * seconds. */
+#define MIN_DELTA 60
+/* ASAP */
+#define IS_ASAP 1
+/* Bandwidth
+ 9  - HT20
+ 10 - VHT20
+ 11 - HT40
+ 12 - VHT40
+ 13 - VHT80 */
+#define BW 13 /* RW610 only allows 20M bandwidth */
+/*Indicates how many burst instances are requested for the FTM session */
+#define BURST_EXP 3
+
+/* LCI */
+#define LCI_REQUEST                1
+#define LCI_LATITIUDE              -33.8570095
+#define LCI_LONGITUDE              151.2152005
+#define LCI_LATITUDE_UNCERTAINITY  18
+#define LCI_LONGITUDE_UNCERTAINITY 18
+#define LCI_ALTITUDE               11.2
+#define LCI_ALTITUDE_UNCERTAINITY  15
+#define Z_INFO                     0
+
+/* CIVIC */
+#define CIVIC_REQUEST       1
+#define CIVIC_LOCATION      1
+#define CIVIC_LOCATION_TYPE 1
+#define CIVIC_COUNTRY_CODE  0 /* US */
+#define CIVIC_ADDRESS_TYPE  22
+#define CIVIC_ADDRESS       "#123"
+
+/* DOT11AZ CFG */
+#define FORMAT_BW 2 /* RW610 only allows 20M bandwidth */
+/*Maximum number of space-time streams to be used in DL/UL NDP frames in the session upto 80MHz*/
+#define MAX_I2R_STS_UPTO80 0 /* RW610 only allows to send 1 N_STS*/
+#define MAX_R2I_STS_UPTO80 0
+/* Measurement freq in Hz to calculate measurement interval*/
+#define AZ_MEASUREMENT_FREQ       4 /* in 0.1 Hz increments */
+#define AZ_NUMBER_OF_MEASUREMENTS 6
+#define I2R_LMR_FEEDBACK          0 /* allow RSTA to request I2R reporting */
+
+#define FOR_RANGING 0
+
+/** Structure of FTM_SESSION_CFG_NTB_RANGING / FTM_SESSION_CFG_TB_RANGING TLV data */
+typedef struct _ranging_11az_cfg
+{
+    /** Indicates the channel BW for session*/
+    /*0: HE20, 1: HE40, 2: HE80, 3: HE80+80, 4: HE160, 5:HE160_SRF*/
+    t_u8 format_bw;
+    /** indicates for bandwidths less than or equal to 80 MHz the maximum number of space-time streams to be used in
+     * DL/UL NDP frames in the session*/
+    t_u8 max_i2r_sts_upto80;
+    /**indicates for bandwidths less than or equal to 80 MHz the maximum number of space-time streams to be used in
+     * DL/UL NDP frames in the session*/
+    t_u8 max_r2i_sts_upto80;
+    /**Specify measurement freq in Hz to calculate measurement interval*/
+    t_u8 az_measurement_freq;
+    /**Indicates the number of measurements to be done for session*/
+    t_u8 az_number_of_measurements;
+    /** Initator lmr feedback */
+    t_u8 i2r_lmr_feedback;
+    /**Include location civic request (Expect location civic from responder)*/
+    t_u8 civic_req;
+    /**Include LCI request (Expect LCI info from responder)*/
+    t_u8 lci_req;
+} ranging_11az_cfg_t;
+
+typedef struct _location_cfg_info
+{
+    /** known latitude uncertainty */
+    t_u8 lat_unc;
+    /** known longitude uncertainty */
+    t_u8 long_unc;
+    /** Known altitude uncertainty */
+    t_u8 alt_unc;
+    /**Include LCI request (expect LCI infomation from responder) */
+    t_u8 lci_req;
+    /** known longitude */
+    double longitude;
+    /** known latitude */
+    double latitude;
+    /** known altitude */
+    double altitude;
+} location_cfg_info_t;
+
+typedef struct _location_civic_rep
+{
+    /** Civic location type */
+    t_u8 civic_location_type;
+    /**Civic address type*/
+    t_u8 civic_address_type;
+    /**Civic address length*/
+    t_u8 civic_address_length;
+    /**Include LCI request (Expect LCI info from responder)*/
+    t_u8 civic_req;
+    /**Country code*/
+    t_u16 country_code;
+} location_civic_rep_t;
+
+/** Structure of FTM_SESSION_CFG TLV data */
+typedef struct _ftm_11mc_nego_cfg
+{
+    /** Indicates how many burst instances are requested for the FTM session*/
+    t_u8 burst_exponent;
+    /** Indicates the duration of a burst instance*/
+    t_u8 burst_duration;
+    /**Minimum time between consecutive FTM frames*/
+    t_u8 min_delta_FTM;
+    /**ASAP/non-ASAP casel*/
+    t_u8 is_ASAP;
+    /**Number of FTMs per burst*/
+    t_u8 per_burst_FTM;
+    /**FTM channel spacing: HT20/HT40/VHT80/... */
+    t_u8 channel_spacing;
+    /**Indicates the interval between two consecutive burst instances*/
+    t_u16 burst_period;
+} ftm_11mc_nego_cfg_t;
+#endif
+
+/** Scan result */
+struct wlan_scan_result
+{
+    /** The network SSID, represented as a NULL-terminated C string of 0 to 32
+     *  characters. If the network has a hidden SSID, this can be the empty
+     *  string.
+     */
+    char ssid[33];
+    /** SSID length */
+    unsigned int ssid_len;
+    /** The network BSSID, represented as a 6-byte array. */
+    char bssid[6];
+    /** The network channel. */
+    unsigned int channel;
+    /** The Wi-Fi network type. */
+    enum wlan_bss_type type;
+    /** The Wi-Fi network mode. */
+    enum wlan_bss_role role;
+
+    /* network features */
+    /** The network supports 802.11N.  This is set to 0 if the network does not
+     *  support 802.11N or if the system does not have 802.11N support enabled. */
+    unsigned dot11n : 1;
+#if CONFIG_11AC
+    /** The network supports 802.11AC.  This is set to 0 if the network does not
+     *  support 802.11AC or if the system does not have 802.11AC support enabled. */
+    unsigned dot11ac : 1;
+#endif
+#if CONFIG_11AX
+    /** The network supports 802.11AX.  This is set to 0 if the network does not
+     *  support 802.11AX or if the system does not have 802.11AX support enabled. */
+    unsigned dot11ax : 1;
+#endif
+
+    /** The network supports WMM.  This is set to 0 if the network does not
+     *  support WMM or if the system does not have WMM support enabled. */
+    unsigned wmm : 1;
+#if (CONFIG_WPA_SUPP_WPS) || (CONFIG_WPS2)
+    /** The network supports WPS.  This is set to 0 if the network does not
+     *  support WPS or if the system does not have WPS support enabled. */
+    unsigned wps : 1;
+    /** WPS Type PBC/PIN */
+    unsigned int wps_session;
+#endif
+    /** The network uses WEP security. */
+    unsigned wep : 1;
+    /** The network uses WPA security. */
+    unsigned wpa : 1;
+    /** The network uses WPA2 security */
+    unsigned wpa2 : 1;
+    /** The network uses WPA2 SHA256 security */
+    unsigned wpa2_sha256 : 1;
+#if CONFIG_DRIVER_OWE
+    /** The network uses OWE security */
+    unsigned owe : 1;
+#endif
+    /** The network uses WPA3 SAE security */
+    unsigned wpa3_sae : 1;
+    /** The network uses WPA2 Enterprise security */
+    unsigned wpa2_entp : 1;
+    /** The network uses WPA2 Enterprise SHA256 security */
+    unsigned wpa2_entp_sha256 : 1;
+    /** The network uses WPA3 Enterprise SHA256 security */
+    unsigned wpa3_1x_sha256 : 1;
+    /** The network uses WPA3 Enterprise SHA384 security */
+    unsigned wpa3_1x_sha384 : 1;
+#if CONFIG_11R
+    /** The network uses FT 802.1x security (For internal use only)*/
+    unsigned ft_1x : 1;
+    /** The network uses FT 892.1x SHA384 security */
+    unsigned ft_1x_sha384 : 1;
+    /** The network uses FT PSK security (For internal use only)*/
+    unsigned ft_psk : 1;
+    /** The network uses FT SAE security (For internal use only)*/
+    unsigned ft_sae : 1;
+#endif
+    /** The signal strength of the beacon */
+    unsigned char rssi;
+    /** The network SSID, represented as a NULL-terminated C string of 0 to 32
+     *  characters. If the network has a hidden SSID, this should be the empty
+     *  string.
+     */
+    char trans_ssid[33];
+    /** SSID length */
+    unsigned int trans_ssid_len;
+    /** The network BSSID, represented as a 6-byte array. */
+    char trans_bssid[6];
+
+    /** Beacon Period */
+    uint16_t beacon_period;
+
+    /** DTIM Period */
+    uint8_t dtim_period;
+
+    /** MFPC bit of AP*/
+    t_u8 ap_mfpc;
+    /** MFPR bit of AP*/
+    t_u8 ap_mfpr;
+    /** PWE bit of AP*/
+    t_u8 ap_pwe;
+
+#if CONFIG_11K
+    /** Neigbort report support (For internal use only)*/
+    bool neighbor_report_supported;
+#endif
+#if CONFIG_11V
+    /** bss transition support (For internal use only)*/
+    bool bss_transition_supported;
+#endif
+};
+
+typedef enum
+{
+    Band_2_4_GHz = 0,
+    Band_5_GHz   = 1,
+    Band_4_GHz   = 2,
+
+} ChanBand_e;
+
+#define NUM_CHAN_BAND_ENUMS 3
+
+typedef enum
+{
+    ChanWidth_20_MHz = 0,
+    ChanWidth_10_MHz = 1,
+    ChanWidth_40_MHz = 2,
+    ChanWidth_80_MHz = 3,
+} ChanWidth_e;
+
+typedef enum
+{
+    SECONDARY_CHAN_NONE  = 0,
+    SECONDARY_CHAN_ABOVE = 1,
+    SECONDARY_CHAN_BELOW = 3,
+    // reserved 2, 4~255
+} Chan2Offset_e;
+
+typedef enum
+{
+    MANUAL_MODE = 0,
+    ACS_MODE    = 1,
+} ScanMode_e;
+
+typedef PACK_START struct
+{
+    ChanBand_e chanBand : 2;
+    ChanWidth_e chanWidth : 2;
+    Chan2Offset_e chan2Offset : 2;
+    ScanMode_e scanMode : 2;
+} PACK_END BandConfig_t;
+
+typedef PACK_START struct
+{
+    BandConfig_t bandConfig;
+    uint8_t chanNum;
+
+} PACK_END ChanBandInfo_t;
+
+
+#if CONFIG_5GHz_SUPPORT
+#define DFS_REC_HDR_LEN (8)
+#define DFS_REC_HDR_NUM (10)
+#define BIN_COUNTER_LEN (7)
+
+typedef PACK_START struct _Event_Radar_Detected_Info
+{
+    t_u32 detect_count;
+    t_u8 reg_domain;    /*1=fcc, 2=etsi, 3=mic*/
+    t_u8 main_det_type; /*0=none, 1=pw(chirp), 2=pri(radar)*/
+    t_u16 pw_chirp_type;
+    t_u8 pw_chirp_idx;
+    t_u8 pw_value;
+    t_u8 pri_radar_type;
+    t_u8 pri_binCnt;
+    t_u8 binCounter[BIN_COUNTER_LEN];
+    t_u8 numDfsRecords;
+    t_u8 dfsRecordHdrs[DFS_REC_HDR_NUM][DFS_REC_HDR_LEN];
+    t_u32 reallyPassed;
+} PACK_END Event_Radar_Detected_Info;
+#endif
+
+/** Network security types */
+enum wlan_security_type
+{
+    /** The network does not use security. */
+    WLAN_SECURITY_NONE,
+    /** The network uses WEP security with open key. */
+    WLAN_SECURITY_WEP_OPEN,
+    /** The network uses WEP security with shared key. */
+    WLAN_SECURITY_WEP_SHARED,
+    /** The network uses WPA security with PSK. */
+    WLAN_SECURITY_WPA,
+    /** The network uses WPA2 security with PSK. */
+    WLAN_SECURITY_WPA2,
+    /** The network uses WPA/WPA2 mixed security with PSK */
+    WLAN_SECURITY_WPA_WPA2_MIXED,
+#if CONFIG_11R
+    /** The network uses WPA2 security with PSK FT. */
+    WLAN_SECURITY_WPA2_FT,
+#endif
+    /** The network uses WPA3 security with SAE. */
+    WLAN_SECURITY_WPA3_SAE,
+#if CONFIG_WPA_SUPP
+#if CONFIG_11R
+    /** The network uses WPA3 security with SAE FT. */
+    WLAN_SECURITY_WPA3_FT_SAE,
+#endif
+#endif
+    /** The network uses WPA3 security with SAE EXT KEY. */
+    WLAN_SECURITY_WPA3_SAE_EXT_KEY,
+    /** The network uses WPA2/WPA3 SAE mixed security with PSK. */
+    WLAN_SECURITY_WPA2_WPA3_SAE_MIXED,
+#if CONFIG_DRIVER_OWE
+    /** The network uses OWE only security without Transition mode support. */
+    WLAN_SECURITY_OWE_ONLY,
+#endif
+#if (CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE) || (CONFIG_WPA2_ENTP)
+    /** The network uses WPA2 Enterprise EAP-TLS security
+     * The identity field in \ref wlan_network structure is used */
+    WLAN_SECURITY_EAP_TLS,
+#endif
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if CONFIG_EAP_TLS
+    /** The network uses WPA2 Enterprise EAP-TLS SHA256 security.
+     * The identity field in \ref wlan_network structure is used */
+    WLAN_SECURITY_EAP_TLS_SHA256,
+#if CONFIG_11R
+    /** The network uses WPA2 Enterprise EAP-TLS FT security.
+     * The identity field in \ref wlan_network structure is used */
+    WLAN_SECURITY_EAP_TLS_FT,
+    /** The network uses WPA2 Enterprise EAP-TLS FT SHA384 security
+     * The identity field in \ref wlan_network structure is used */
+    WLAN_SECURITY_EAP_TLS_FT_SHA384,
+#endif
+#endif
+#if CONFIG_EAP_TTLS
+    /** The network uses WPA2 Enterprise EAP-TTLS security.
+     * The identity field in \ref wlan_network structure is used */
+    WLAN_SECURITY_EAP_TTLS,
+#endif
+#if CONFIG_EAP_MSCHAPV2
+    /** The network uses WPA2 Enterprise EAP-TTLS-MSCHAPV2 security.
+     * The anonymous identity, identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_TTLS_MSCHAPV2,
+#endif
+#endif
+#if (CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE) || (CONFIG_PEAP_MSCHAPV2) || (CONFIG_WPA2_ENTP)
+    /** The network uses WPA2 Enterprise EAP-PEAP-MSCHAPV2 security.
+     * The anonymous identity, identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_PEAP_MSCHAPV2,
+#endif
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if CONFIG_EAP_PEAP
+#if CONFIG_EAP_TLS
+    /** The network uses WPA2 Enterprise EAP-PEAP-TLS security.
+     * The anonymous identity, identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_PEAP_TLS,
+#endif
+#if CONFIG_EAP_GTC
+    /** The network uses WPA2 Enterprise EAP-PEAP-GTC security.
+     * The anonymous identity, identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_PEAP_GTC,
+#endif
+#endif
+#if CONFIG_EAP_FAST
+#if CONFIG_EAP_MSCHAPV2
+    /** The network uses WPA2 Enterprise EAP-FAST-MSCHAPV2 security.
+     * The anonymous identity, identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_FAST_MSCHAPV2,
+#endif
+#if CONFIG_EAP_GTC
+    /** The network uses WPA2 Enterprise EAP-FAST-GTC security
+     * The anonymous identity, identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_FAST_GTC,
+#endif
+#endif
+#if CONFIG_EAP_SIM
+    /** The network uses WPA2 Enterprise EAP-SIM security
+     * The identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_SIM,
+#endif
+#if CONFIG_EAP_AKA
+    /** The network uses WPA2 Enterprise EAP-AKA security
+     * The identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_AKA,
+#endif
+#if CONFIG_EAP_AKA_PRIME
+    /** The network uses WPA2 Enterprise EAP-AKA-PRIME security
+     * The identity and password fields in
+     * \ref wlan_network structure are used */
+    WLAN_SECURITY_EAP_AKA_PRIME,
+#endif
+#endif
+#if CONFIG_WPA_SUPP_DPP
+    /** The network uses DPP security with NAK(Net Access Key) */
+    WLAN_SECURITY_DPP,
+#endif
+    /** The network can use any security method. This is often used when
+     * the user only knows the name and passphrase but not the security
+     * type.  */
+    WLAN_SECURITY_WILDCARD,
+};
+
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if CONFIG_EAP_TLS
+/** EAP TLS Cipher types*/
+enum eap_tls_cipher_type
+{
+    EAP_TLS_NONE,
+    /** EAP TLS with ECDH & ECDSA with p384 */
+    EAP_TLS_ECC_P384,
+    /** EAP TLS with ECDH & RSA with > 3K */
+    EAP_TLS_RSA_3K,
+};
+#endif
+#endif
+
+/** Wi-Fi cipher structure */
+struct wlan_cipher
+{
+    /** 1 bit value can be set for none */
+    uint16_t none : 1;
+    /** 1 bit value can be set for wep40 */
+    uint16_t wep40 : 1;
+    /** 1 bit value can be set for wep104 */
+    uint16_t wep104 : 1;
+    /** 1 bit value can be set for tkip */
+    uint16_t tkip : 1;
+    /** 1 bit value can be set for ccmp */
+    uint16_t ccmp : 1;
+    /**  1 bit value can be set for aes 128 cmac */
+    uint16_t aes_128_cmac : 1;
+    /** 1 bit value can be set for gcmp */
+    uint16_t gcmp : 1;
+    /** 1 bit value can be set for sms4 */
+    uint16_t sms4 : 1;
+    /** 1 bit value can be set for gcmp 256 */
+    uint16_t gcmp_256 : 1;
+    /** 1 bit value can be set for ccmp 256 */
+    uint16_t ccmp_256 : 1;
+    /** 1 bit is reserved */
+    uint16_t rsvd : 1;
+    /** 1 bit value can be set for bip gmac 128 */
+    uint16_t bip_gmac_128 : 1;
+    /** 1 bit value can be set for bip gmac 256 */
+    uint16_t bip_gmac_256 : 1;
+    /** 1 bit value can be set for bip cmac 256 */
+    uint16_t bip_cmac_256 : 1;
+    /** 1 bit value can be set for gtk not used */
+    uint16_t gtk_not_used : 1;
+    /** 4 bits are reserved */
+    uint16_t rsvd2 : 2;
+};
+
+static inline int is_valid_security(int security)
+{
+    /*Currently only these modes are supported */
+    if ((security == WLAN_SECURITY_NONE) || (security == WLAN_SECURITY_WEP_OPEN) || (security == WLAN_SECURITY_WPA) ||
+        (security == WLAN_SECURITY_WPA2) ||
+#if CONFIG_11R
+        (security == WLAN_SECURITY_WPA2_FT) ||
+#endif
+        (security == WLAN_SECURITY_WPA_WPA2_MIXED) ||
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if CONFIG_EAP_TLS
+        (security == WLAN_SECURITY_EAP_TLS) || (security == WLAN_SECURITY_EAP_TLS_SHA256) ||
+#if CONFIG_11R
+        (security == WLAN_SECURITY_EAP_TLS_FT) || (security == WLAN_SECURITY_EAP_TLS_FT_SHA384) ||
+#endif
+#endif
+#if CONFIG_EAP_TTLS
+        (security == WLAN_SECURITY_EAP_TTLS) ||
+#if CONFIG_EAP_MSCHAPV2
+        (security == WLAN_SECURITY_EAP_TTLS_MSCHAPV2) ||
+#endif
+#endif
+#if CONFIG_EAP_PEAP
+#if CONFIG_EAP_MSCHAPV2
+        (security == WLAN_SECURITY_EAP_PEAP_MSCHAPV2) ||
+#endif
+#if CONFIG_EAP_TLS
+        (security == WLAN_SECURITY_EAP_PEAP_TLS) ||
+#endif
+#if CONFIG_EAP_GTC
+        (security == WLAN_SECURITY_EAP_PEAP_GTC) ||
+#endif
+#endif
+#if CONFIG_EAP_FAST
+#if CONFIG_EAP_MSCHAPV2
+        (security == WLAN_SECURITY_EAP_FAST_MSCHAPV2) ||
+#endif
+#if CONFIG_EAP_GTC
+        (security == WLAN_SECURITY_EAP_FAST_GTC) ||
+#endif
+#endif
+#if CONFIG_EAP_SIM
+        (security == WLAN_SECURITY_EAP_SIM) ||
+#endif
+#if CONFIG_EAP_AKA
+        (security == WLAN_SECURITY_EAP_AKA) ||
+#endif
+#if CONFIG_EAP_AKA_PRIME
+        (security == WLAN_SECURITY_EAP_AKA_PRIME) ||
+#endif
+#else
+#if CONFIG_WPA2_ENTP
+        (security == WLAN_SECURITY_EAP_TLS) ||
+#endif
+#if CONFIG_PEAP_MSCHAPV2
+        (security == WLAN_SECURITY_EAP_PEAP_MSCHAPV2) ||
+#endif
+#endif /* CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE */
+#if CONFIG_DRIVER_OWE
+        (security == WLAN_SECURITY_OWE_ONLY) ||
+#endif
+        (security == WLAN_SECURITY_WPA3_SAE) || (security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED) ||
+#if CONFIG_WPA_SUPP
+#if CONFIG_11R
+        (security == WLAN_SECURITY_WPA3_FT_SAE) ||
+#endif
+#endif
+        (security == WLAN_SECURITY_WPA3_SAE_EXT_KEY) || (security == WLAN_SECURITY_WILDCARD))
+    {
+        return 1;
+    }
+    return 0;
+}
+
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+static inline int is_ep_valid_security(int security)
+{
+    /*Currently only these modes are supported */
+    if (
+#if CONFIG_EAP_TLS
+        (security == WLAN_SECURITY_EAP_TLS) || (security == WLAN_SECURITY_EAP_TLS_SHA256) ||
+#if CONFIG_11R
+        (security == WLAN_SECURITY_EAP_TLS_FT) || (security == WLAN_SECURITY_EAP_TLS_FT_SHA384) ||
+#endif
+#endif
+#if CONFIG_EAP_TTLS
+        (security == WLAN_SECURITY_EAP_TTLS) ||
+#if CONFIG_EAP_MSCHAPV2
+        (security == WLAN_SECURITY_EAP_TTLS_MSCHAPV2) ||
+#endif
+#endif
+#if CONFIG_EAP_PEAP
+#if CONFIG_EAP_MSCHAPV2
+        (security == WLAN_SECURITY_EAP_PEAP_MSCHAPV2) ||
+#endif
+#if CONFIG_EAP_TLS
+        (security == WLAN_SECURITY_EAP_PEAP_TLS) ||
+#endif
+#if CONFIG_EAP_GTC
+        (security == WLAN_SECURITY_EAP_PEAP_GTC) ||
+#endif
+#endif
+#if CONFIG_EAP_FAST
+#if CONFIG_EAP_MSCHAPV2
+        (security == WLAN_SECURITY_EAP_FAST_MSCHAPV2) ||
+#endif
+#if CONFIG_EAP_GTC
+        (security == WLAN_SECURITY_EAP_FAST_GTC) ||
+#endif
+#endif
+#if CONFIG_EAP_SIM
+        (security == WLAN_SECURITY_EAP_SIM) ||
+#endif
+#if CONFIG_EAP_AKA
+        (security == WLAN_SECURITY_EAP_AKA) ||
+#endif
+#if CONFIG_EAP_AKA_PRIME
+        (security == WLAN_SECURITY_EAP_AKA_PRIME) ||
+#endif
+        false)
+    {
+        return 1;
+    }
+    return 0;
+}
+#endif
+
+/** Network security configuration */
+struct wlan_network_security
+{
+    /** Type of network security to use specified by enum
+     * wlan_security_type. */
+    enum wlan_security_type type;
+    /** Key management type */
+    int key_mgmt;
+    /** Type of network security Group Cipher suite used internally*/
+    struct wlan_cipher mcstCipher;
+    /** Type of network security Pairwise Cipher suite used internally*/
+    struct wlan_cipher ucstCipher;
+#if CONFIG_WPA_SUPP
+    /** Proactive key caching */
+    unsigned pkc : 1;
+    /** Type of network security Group Cipher suite */
+    int group_cipher;
+    /** Type of network security Pairwise Cipher suite */
+    int pairwise_cipher;
+    /** Type of network security Pairwise Cipher suite */
+    int group_mgmt_cipher;
+#endif
+    /** Is PMF (protected management frame) required */
+    bool is_pmf_required;
+    /** Pre-shared key (network password).  For WEP networks this is a hex byte
+     * sequence of length psk_len, for WPA and WPA2 networks this is an ASCII
+     * pass-phrase of length psk_len.  This field is ignored for networks with no
+     * security. */
+    char psk[WLAN_PSK_MAX_LENGTH];
+    /** Length of the WEP key or WPA/WPA2 pass phrase, \ref WLAN_PSK_MIN_LENGTH to \ref
+     * WLAN_PSK_MAX_LENGTH.  Ignored for networks with no security. */
+    uint8_t psk_len;
+    /** WPA3 SAE password, for WPA3 SAE networks this is an ASCII
+     * password of length password_len.  This field is ignored for networks with no
+     * security. */
+    char password[WLAN_PASSWORD_MAX_LENGTH + 1];
+    /** Length of the WPA3 SAE Password, \ref WLAN_PASSWORD_MIN_LENGTH to \ref
+     * WLAN_PASSWORD_MAX_LENGTH.  Ignored for networks with no security. */
+    size_t password_len;
+    /** SAE Groups */
+    char *sae_groups;
+    /** PWE derivation */
+    uint8_t pwe_derivation;
+    /** transition disable */
+    uint8_t transition_disable;
+#if CONFIG_DRIVER_OWE
+    /** OWE Groups */
+    char *owe_groups;
+#endif
+    /** PMK (pairwise master key). When pmk_valid is set, this is the PMK calculated
+     * from the PSK for WPA/PSK networks. If pmk_valid is not set, this field
+     * is not valid. When adding networks with \ref wlan_add_network, users
+     * can initialize PMK and set pmk_valid in lieu of setting the psk. After
+     * successfully connecting to a WPA/PSK network, users can call \ref
+     * wlan_get_current_network to inspect pmk_valid and pmk. Thus, the pmk
+     * value can be populated in subsequent calls to \ref wlan_add_network.
+     * This saves the CPU time required to otherwise calculate the PMK.
+     */
+    char pmk[WLAN_PMK_LENGTH];
+
+    /** Flag reporting whether PMK is valid or not. */
+    bool pmk_valid;
+    /** Management frame protection capable (MFPC) */
+    int8_t mfpc;
+    /** Management frame protection required (MFPR) */
+    int8_t mfpr;
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+    /** WPA3 Enterprise mode */
+    unsigned wpa3_sb : 1;
+    /** WPA3 Enterprise Suite B 192 mode */
+    unsigned wpa3_sb_192 : 1;
+    /** PEAP version */
+    unsigned eap_ver : 1;
+#if CONFIG_EAP_PEAP
+    /** PEAP label */
+    unsigned peap_label : 1;
+    /** crypto_binding option can be used to control \ref WLAN_SECURITY_EAP_PEAP_MSCHAPV2, \ref
+     * WLAN_SECURITY_EAP_PEAP_TLS and \ref WLAN_SECURITY_EAP_PEAP_GTC version 0 cryptobinding behavior: 0 = do not use
+     * cryptobinding (default) 1 = use cryptobinding if server supports it 2 = require cryptobinding */
+    uint8_t eap_crypto_binding;
+#endif
+#if (CONFIG_EAP_SIM) || (CONFIG_EAP_AKA) || (CONFIG_EAP_AKA_PRIME)
+    /** eap_result_ind=1 can be used to enable \ref WLAN_SECURITY_EAP_SIM, \ref WLAN_SECURITY_EAP_AKA and \ref
+     * WLAN_SECURITY_EAP_AKA_PRIME to use protected result indication.*/
+    unsigned eap_result_ind : 1;
+#endif
+#if CONFIG_EAP_TLS
+    /** Cipher for EAP TLS */
+    unsigned char tls_cipher;
+#endif
+    /** Identity string for EAP */
+    char identity[IDENTITY_MAX_LENGTH];
+    /** Anonymous identity string for EAP */
+    char anonymous_identity[IDENTITY_MAX_LENGTH];
+    /** Password string for EAP. This field can include
+     * either the plaintext password (using ASCII or
+     * hex string) */
+    char eap_password[PASSWORD_MAX_LENGTH];
+    /** CA cert blob in PEM/DER format */
+    unsigned char *ca_cert_data;
+    /** CA cert blob len */
+    size_t ca_cert_len;
+    /** Client cert blob in PEM/DER format */
+    unsigned char *client_cert_data;
+    /** Client cert blob len */
+    size_t client_cert_len;
+    /** Client key blob */
+    unsigned char *client_key_data;
+    /** Client key blob len */
+    size_t client_key_len;
+    /** Client key password */
+    char client_key_passwd[PASSWORD_MAX_LENGTH];
+    /** CA cert HASH */
+    char ca_cert_hash[HASH_MAX_LENGTH];
+    /** Domain */
+    char domain_match[DOMAIN_MATCH_MAX_LENGTH];
+    /** Domain Suffix */
+    char domain_suffix_match[DOMAIN_MATCH_MAX_LENGTH]; /*suffix max length same as full domain name length*/
+    /** CA cert2 blob in PEM/DER format */
+    unsigned char *ca_cert2_data;
+    /** CA cert2 blob len */
+    size_t ca_cert2_len;
+    /** Client cert2 blob in PEM/DER format */
+    unsigned char *client_cert2_data;
+    /** Client cert2 blob len */
+    size_t client_cert2_len;
+    /** Client key2 blob */
+    unsigned char *client_key2_data;
+    /** Client key2 blob len */
+    size_t client_key2_len;
+    /** Client key2 password */
+    char client_key2_passwd[PASSWORD_MAX_LENGTH];
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    /** DH params blob */
+    unsigned char *dh_data;
+    /** DH params blob len */
+    size_t dh_len;
+    /** Server cert blob in PEM/DER format */
+    unsigned char *server_cert_data;
+    /** Server cert blob len */
+    size_t server_cert_len;
+    /** Server key blob */
+    unsigned char *server_key_data;
+    /** Server key blob len */
+    size_t server_key_len;
+    /** Server key password */
+    char server_key_passwd[PASSWORD_MAX_LENGTH];
+    /** Number of EAP users */
+    size_t nusers;
+    /** User Identities */
+    char identities[MAX_USERS][IDENTITY_MAX_LENGTH];
+    /** User Passwords */
+    char passwords[MAX_USERS][PASSWORD_MAX_LENGTH];
+#if CONFIG_EAP_FAST
+    /** Encryption key for EAP-FAST PAC-Opaque values */
+    char pac_opaque_encr_key[PAC_OPAQUE_ENCR_KEY_MAX_LENGTH];
+    /** EAP-FAST authority identity (A-ID) */
+    char a_id[A_ID_MAX_LENGTH];
+    /** EAP-FAST provisioning modes:
+     * 0 = provisioning disabled
+     * 1 = only anonymous provisioning allowed
+     * 2 = only authenticated provisioning allowed
+     * 3 = both provisioning modes allowed (default)
+     */
+    uint8_t fast_prov;
+#endif
+#endif
+#endif
+#elif (CONFIG_WPA2_ENTP)
+    /** TLS client cert configuration */
+    wm_mbedtls_cert_t tls_cert;
+    /** mbedtls_ssl_config handle */
+    mbedtls_ssl_config *wlan_ctx;
+    /** mbedtls_ssl_context handle */
+    mbedtls_ssl_context *wlan_ssl;
+#endif
+#if CONFIG_WPA_SUPP_DPP
+    unsigned char *dpp_connector;
+    unsigned char *dpp_c_sign_key;
+    unsigned char *dpp_net_access_key;
+#endif
+};
+
+/** Configuration for Wi-Fi scan */
+#define MAX_CHANNEL_LIST 6
+/** This structure is used to configure Wi-Fi scan parameters */
+struct wifi_scan_params_t
+{
+    /** BSSID (basic servivce set ID) */
+    uint8_t *bssid;
+    /** SSID (service set ID) */
+    char *ssid;
+    /** Channel list */
+    int channel[MAX_CHANNEL_LIST];
+    /** BSS (basic service set) type.
+    1: Infrastructure BSS,
+    2: Indenpent BSS.
+    */
+    IEEEtypes_Bss_t bss_type;
+    /** Time for scan duration */
+    int scan_duration;
+    /** split scan delay */
+    int split_scan_delay;
+};
+
+#if CONFIG_WIFI_GET_LOG
+/** Wi-Fi firmware stat from \ref wifi_pkt_stats_t
+ */
+typedef wifi_pkt_stats_t wlan_pkt_stats_t;
+#endif
+
+/** Configuration for Wi-Fi scan channel list from
+ * \ref wifi_scan_channel_list_t
+ */
+typedef wifi_scan_channel_list_t wlan_scan_channel_list_t;
+/** Configuration for Wi-Fi scan parameters v2 from
+ * \ref wifi_scan_params_v2_t
+ */
+typedef wifi_scan_params_v2_t wlan_scan_params_v2_t;
+
+
+/** Configuration for Wi-Fi calibration data from
+ * \ref wifi_cal_data_t
+ */
+typedef wifi_cal_data_t wlan_cal_data_t;
+
+#if CONFIG_AUTO_RECONNECT
+/** Configuration for auto reconnect configuration from
+ * \ref wifi_auto_reconnect_config_t
+ */
+typedef wifi_auto_reconnect_config_t wlan_auto_reconnect_config_t;
+#endif
+
+/** Configuration for memory efficient filters in Wi-Fi firmware from
+ * \ref wifi_flt_cfg_t
+ */
+typedef wifi_flt_cfg_t wlan_flt_cfg_t;
+
+/** Configuration for wowlan pattern parameters from
+ * \ref wifi_wowlan_ptn_cfg_t
+ */
+typedef wifi_wowlan_ptn_cfg_t wlan_wowlan_ptn_cfg_t;
+/** Configuration for TCP keep alive parameters from
+ * \ref wifi_tcp_keep_alive_t
+ */
+typedef wifi_tcp_keep_alive_t wlan_tcp_keep_alive_t;
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+/** Configuration for cloud keep alive parameters from
+ * \ref wifi_cloud_keep_alive_t
+ */
+typedef wifi_cloud_keep_alive_t wlan_cloud_keep_alive_t;
+#endif
+
+/** Configuration for TX rate and get data rate from
+ * \ref wifi_ds_rate
+ */
+typedef wifi_ds_rate wlan_ds_rate;
+/** Configuration for ED MAC Control parameters from
+ * \ref wifi_ed_mac_ctrl_t
+ */
+typedef wifi_ed_mac_ctrl_t wlan_ed_mac_ctrl_t;
+/** Configuration for band from
+ * \ref wifi_bandcfg_t
+ */
+typedef wifi_bandcfg_t wlan_bandcfg_t;
+/** Configuration for CW mode parameters from
+ * \ref wifi_cw_mode_ctrl_t
+ */
+typedef wifi_cw_mode_ctrl_t wlan_cw_mode_ctrl_t;
+/** Configuration for channel list from
+ * \ref wifi_chanlist_t
+ */
+typedef wifi_chanlist_t wlan_chanlist_t;
+/** Configuration for TX power Limit from
+ * \ref wifi_txpwrlimit_t
+ */
+typedef wifi_txpwrlimit_t wlan_txpwrlimit_t;
+#ifdef SD8801
+/** Statistic of External Coex from
+ * \ref wifi_ext_coex_config_t
+ */
+typedef wifi_ext_coex_stats_t wlan_ext_coex_stats_t;
+/** Configuration for external Coex from
+ * \ref wifi_ext_coex_config_t
+ */
+typedef wifi_ext_coex_config_t wlan_ext_coex_config_t;
+#endif
+
+#if CONFIG_11AX
+/** Configuration for RU TX power limit from
+ * \ref wifi_rutxpwrlimit_t
+ */
+typedef wifi_rutxpwrlimit_t wlan_rutxpwrlimit_t;
+/** Configuration for 802.11ax capabilities
+ * \ref wifi_11ax_config_t
+ */
+typedef wifi_11ax_config_t wlan_11ax_config_t;
+#if CONFIG_11AX_TWT
+/** Configuration for TWT setup
+ * \ref wifi_twt_setup_config_t
+ */
+typedef wifi_twt_setup_config_t wlan_twt_setup_config_t;
+/** Configuration for TWT teardown
+ * \ref wifi_twt_teardown_config_t
+ */
+typedef wifi_twt_teardown_config_t wlan_twt_teardown_config_t;
+/** Configuration for Broadcast TWT setup
+ * \ref wifi_btwt_config_t
+ */
+typedef wifi_btwt_config_t wlan_btwt_config_t;
+/** Configuration for TWT report
+ * \ref wifi_twt_report_t
+ */
+typedef wifi_twt_report_t wlan_twt_report_t;
+#endif /* CONFIG_11AX_TWT */
+#if CONFIG_MMSF
+#define WLAN_AMPDU_DENSITY 0x30
+#define WLAN_AMPDU_MMSF    0x6
+#endif
+#endif
+#if CONFIG_WIFI_CLOCKSYNC
+/** Configuration for clock sync GPIO TSF latch
+ * \ref wifi_clock_sync_gpio_tsf_t
+ */
+typedef wifi_clock_sync_gpio_tsf_t wlan_clock_sync_gpio_tsf_t;
+/** Configuration for TSF info
+ * \ref wifi_tsf_info_t
+ */
+typedef wifi_tsf_info_t wlan_tsf_info_t;
+#endif
+
+#if CONFIG_MULTI_CHAN
+/** Configuration for multi-channel switch
+ * \ref wifi_drcs_cfg_t
+ */
+typedef wifi_drcs_cfg_t wlan_drcs_cfg_t;
+#endif
+
+typedef wifi_mgmt_frame_t wlan_mgmt_frame_t;
+
+
+#if CONFIG_CSI
+/** Configuration for CSI config params from
+ * \ref wifi_csi_config_params_t
+ */
+typedef wifi_csi_config_params_t wlan_csi_config_params_t;
+#endif
+
+#if CONFIG_NET_MONITOR
+/** Configuration for net monitor from
+ * \ref wifi_net_monitor_t
+ */
+typedef wifi_net_monitor_t wlan_net_monitor_t;
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+/** Configuration for GPIO independent reset
+ * \ref wifi_indrst_cfg_t
+ */
+typedef wifi_indrst_cfg_t wlan_indrst_cfg_t;
+#endif
+
+#if CONFIG_11AX
+/** Configuration for TX rate setting from
+ * \ref txrate_setting
+ */
+typedef txrate_setting wlan_txrate_setting;
+#endif
+
+/** Configuration for RSSI information
+ * \ref wifi_rssi_info_t
+ */
+typedef wifi_rssi_info_t wlan_rssi_info_t;
+
+#if CONFIG_EXTERNAL_COEX_PTA
+#define MIN_SAMP_TIMING              20
+#define MAX_SAMP_TIMING              200
+#define COEX_PTA_FEATURE_ENABLE      1
+#define COEX_PTA_FEATURE_DISABLE     0
+#define POL_GRANT_PIN_HIGH           0
+#define POL_GRANT_PIN_LOW            1
+#define STATE_INPUT_DISABLE          0
+#define STATE_PTA_PIN                1
+#define STATE_PRIORITY_PIN           2
+#define SAMPLE_TIMING_VALUE          100
+#define EXT_COEX_PTA_INTERFACE       5
+#define EXT_COEX_WCI2_INTERFACE      6
+#define EXT_COEX_WCI2_GPIO_INTERFACE 7
+
+typedef struct _external_coex_pta_cfg
+{
+    /** Enable: 0x01, Disable: 0x00 */
+    t_u8 enabled;
+    /** Enable extended Wi-Fi and Bluetooth LE arbitration: 0x01, disable : 0x00 */
+    t_u8 ext_WifiBtArb;
+    /** Active high: 0x00, Active low: 0x01 */
+    t_u8 polGrantPin;
+    /**  Enable PriPtaInt: 0x01, Disable PriPtaInt: 0x00 */
+    t_u8 enable_PriPtaInt;
+    /** State input disable: 0x00, State info is from state pin: 0x01, State info is sampled on priority pin: 0x02 */
+    t_u8 enable_StatusFromPta;
+    /** Timing to sample Priority bit */
+    t_u16 setPriSampTiming;
+    /** Timing to sample TX/RX info */
+    t_u16 setStateInfoSampTiming;
+    /** Enable external traffic TX/RX Priority: 0x01, Disable external traffic TX/RX Priority: 0x00 */
+    t_u8 extRadioTrafficPrio;
+    /** Enable wci-2 interface: 0x01, Disable wci-2 interface: 0x00 */
+    t_u8 extCoexHwIntWci2;
+} ext_coex_pta_cfg;
+#endif
+
+/**
+* Check whether the scan duration is valid.
+*
+* \param[in] scan duration time
+*
+* \return 0 if the time is valid, else return -1.
+*/
+int verify_scan_duration_value(int scan_duration);
+
+/**
+* Check whether the scan channel is valid.
+*
+* \param[in] channel
+*
+* \return 0 if the channel is valid, else return -1.
+*/
+int verify_scan_channel_value(int channel);
+
+/**
+* Check whether the scan delay time is valid.
+*
+* \param[in] delay, the scan delay time.
+*
+* \return 0 if the time is valid, else return -1.
+*/
+int verify_split_scan_delay(int delay);
+
+/**
+* Set scan parameters.
+*
+* \param[in] wifi_scan_params Wi-Fi scan parameter structure pointer.
+*
+* \return WM_SUCCESS.
+*/
+int set_scan_params(struct wifi_scan_params_t *wifi_scan_params);
+
+/**
+* Get scan parameters.
+*
+* \param[out] wifi_scan_params Wi-Fi scan parameter structure pointer.
+*
+* \return WM_SUCCESS.
+*/
+int get_scan_params(struct wifi_scan_params_t *wifi_scan_params);
+
+/**
+* Get current RSSI value.
+*
+* \param[out] rssi, RSSI pointer.
+*
+* \return WM_SUCCESS.
+*/
+int wlan_get_current_rssi(short *rssi);
+
+/**
+* Get current noise floor.
+*
+* \return noise floor value .
+*/
+int wlan_get_current_nf(void);
+
+/** Address types to be used by the element wlan_ip_config.addr_type below
+ */
+enum address_types
+{
+    /** static IP address */
+    ADDR_TYPE_STATIC = 0,
+    /** Dynamic  IP address*/
+    ADDR_TYPE_DHCP = 1,
+    /** Link level address */
+    ADDR_TYPE_LLA = 2,
+};
+
+/** This data structure represents an IPv4 address */
+struct ipv4_config
+{
+    /** Set to \ref ADDR_TYPE_DHCP to use DHCP to obtain the IP address or
+     *  \ref ADDR_TYPE_STATIC to use a static IP. In case of static IP
+     *  address ip, gw, netmask and dns members should be specified. When
+     *  using DHCP, the ip, gw, netmask and dns are overwritten by the
+     *  values obtained from the DHCP server. They should be zeroed out if
+     *  not used. */
+    enum address_types addr_type;
+    /** The system's IP address in network order. */
+    unsigned address;
+    /** The system's default gateway in network order. */
+    unsigned gw;
+    /** The system's subnet mask in network order. */
+    unsigned netmask;
+    /** The system's primary dns server in network order. */
+    unsigned dns1;
+    /** The system's secondary dns server in network order. */
+    unsigned dns2;
+};
+
+#if CONFIG_IPV6
+/** This data structure represents an IPv6 address */
+struct ipv6_config
+{
+    /** The system's IPv6 address in network order. */
+    unsigned address[4];
+    /** The address type: linklocal, site-local or global. */
+    unsigned char addr_type;
+    /** The state of IPv6 address (Tentative, Preferred, etc). */
+    unsigned char addr_state;
+};
+#endif
+
+/** Network IP configuration.
+ *
+ *  This data structure represents the network IP configuration
+ *  for IPv4 as well as IPv6 addresses
+ */
+struct wlan_ip_config
+{
+#if CONFIG_IPV6
+    /** The network IPv6 address configuration that should be
+     * associated with this interface. */
+    struct ipv6_config ipv6[CONFIG_MAX_IPV6_ADDRESSES];
+    /** The network IPv6 valid addresses count */
+    size_t ipv6_count;
+#endif
+    /** The network IPv4 address configuration that should be
+     * associated with this interface. */
+    struct ipv4_config ipv4;
+};
+
+/** Wi-Fi network profile
+ *
+ *  This data structure represents a Wi-Fi network profile. It consists of an
+ *  arbitrary name, Wi-Fi configuration, and IP address configuration.
+ *
+ *  Every network profile is associated with one of the two interfaces. The
+ *  network profile can be used for the station interface (i.e. to connect to an
+ *  Access Point) by setting the role field to \ref
+ *  WLAN_BSS_ROLE_STA. The network profile can be used for the UAP
+ *  interface (i.e. to start a network of our own.) by setting the mode field to
+ *  \ref WLAN_BSS_ROLE_UAP.
+ *
+ *  If the mode field is \ref WLAN_BSS_ROLE_STA, either of the SSID or
+ *  BSSID fields are used to identify the network, while the other members like
+ *  channel and security settings characterize the network.
+ *
+ *  If the mode field is \ref WLAN_BSS_ROLE_UAP, the SSID, channel and security
+ *  fields are used to define the network to be started.
+ *
+ *  In both the above cases, the address field is used to determine the type of
+ *  address assignment to be used for this interface.
+ */
+struct wlan_network
+{
+#if CONFIG_WPA_SUPP
+    /** Identifier for network profile */
+    int id;
+    /** WPS netwrok flag. */
+    int wps_network;
+#endif
+    /** The name of this network profile. Each network profile that is
+     *  added to the Wi-Fi connection manager should have a unique name. */
+    char name[WLAN_NETWORK_NAME_MAX_LENGTH + 1];
+    /** The network SSID, represented as a C string of up to 32 characters
+     *  in length.
+     *  If this profile is used in the UAP mode, this field is
+     *  used as the SSID of the network.
+     *  If this profile is used in the station mode, this field is
+     *  used to identify the network. Set the first byte of the SSID to NULL
+     *  (a 0-length string) to use only the BSSID to find the network.
+     */
+    char ssid[IEEEtypes_SSID_SIZE + 1];
+    /** The network BSSID, represented as a 6-byte array.
+     *  If this profile is used in the UAP mode, this field is
+     *  ignored.
+     *  If this profile is used in the station mode, this field is
+     *  used to identify the network. Set all 6 bytes to 0 to use any BSSID,
+     *  in which case only the SSID is used to find the network.
+     */
+    char bssid[IEEEtypes_ADDRESS_SIZE];
+    /** The channel for this network.
+     *
+     *  If this profile is used in UAP mode, this field
+     *  specifies the channel to start the UAP interface on. Set this
+     *  to 0 for auto channel selection.
+     *
+     *  If this profile is used in the station mode, this constrains the
+     *  channel on which the network to connect should be present. Set this
+     *  to 0 to allow the network to be found on any channel. */
+    unsigned int channel;
+    /** The secondary channel offset **/
+    uint8_t sec_channel_offset;
+    /** The ACS (auto channel selection) band if set channel to 0. */
+    uint16_t acs_band;
+    /** RSSI (received signal strength indicator) value. */
+    int rssi;
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    /** RSSI threshold */
+    short rssi_threshold;
+#endif
+#if CONFIG_WPA_SUPP
+    /** HT capabilities */
+    unsigned short ht_capab;
+#if CONFIG_11AC
+    /** VHT capabilities */
+    unsigned int vht_capab;
+    /** VHT bandwidth */
+    unsigned char vht_oper_chwidth;
+#endif
+#if CONFIG_11AX
+    /** HE bandwidth */
+    unsigned char he_oper_chwidth;
+#endif
+#endif
+    /** BSS type */
+    enum wlan_bss_type type;
+    /** The network Wi-Fi mode enum wlan_bss_role. Set this
+     *  to specify what type of Wi-Fi network mode to use.
+     *  This can either be \ref WLAN_BSS_ROLE_STA for use in
+     *  the station mode, or it can be \ref WLAN_BSS_ROLE_UAP
+     *  for use in the UAP mode. */
+    enum wlan_bss_role role;
+    /** The network security configuration specified by struct
+     * wlan_network_security for the network. */
+    struct wlan_network_security security;
+    /** The network IP address configuration specified by struct
+     * wlan_ip_config that should be associated with this interface. */
+    struct wlan_ip_config ip;
+#if CONFIG_WPA2_ENTP
+    /** WPA2 Enterprise identity, the max can be upto 256 characters */
+    char identity[IDENTITY_MAX_LENGTH];
+#if CONFIG_PEAP_MSCHAPV2
+    char anonymous_identity[IDENTITY_MAX_LENGTH];
+    /** password string */
+    char password[PASSWORD_MAX_LENGTH];
+#endif
+#endif
+
+    /* Private Fields */
+
+    /**
+     * If set to 1, the ssid field contains the specific SSID for this
+     * network.
+     * the Wi-Fi connection manager can only connect to networks whose SSID
+     * matches.  If set to 0, the ssid field contents are not used when
+     * deciding whether to connect to a network, the BSSID field is used
+     * instead and any network whose BSSID matches is accepted.
+     *
+     * This field can be set to 1 if the network is added with the SSID
+     * specified (not an empty string), otherwise it is set to 0.
+     */
+    unsigned ssid_specific : 1;
+#if CONFIG_DRIVER_OWE
+    /**
+     * If set to 1, the ssid field contains the transitional SSID for this
+     * network.
+     */
+    unsigned trans_ssid_specific : 1;
+#endif
+    /** If set to 1, the bssid field contains the specific BSSID for this
+     *  network. The Wi-Fi connection manager can not connect to any other
+     *  network with the same SSID unless the BSSID matches.  If set to 0, the
+     *  Wi-Fi connection manager can connect to any network whose SSID matches.
+     *
+     *  This field set to 1 if the network is added with the BSSID
+     *  specified (not set to all zeroes), otherwise it is set to 0. */
+    unsigned bssid_specific : 1;
+    /**
+     * If set to 1, the channel field contains the specific channel for this
+     * network. The Wi-Fi connection manager can not look for this network on
+     * any other channel. If set to 0, the Wi-Fi connection manager can look
+     * for this network on any available channel.
+     *
+     * This field set to 1 if the network is added with the channel
+     * specified (not set to 0), otherwise it is set to 0. */
+    unsigned channel_specific : 1;
+    /**
+     * If set to 0, any security that matches is used. This field is
+     * internally set when the security type parameter above is set to
+     * WLAN_SECURITY_WILDCARD.
+     */
+    unsigned security_specific : 1;
+#if CONFIG_WPS2
+    /** This indicates this network is used as an internal network for
+     * WPS */
+    unsigned wps_specific : 1;
+#endif
+
+    /** The network supports 802.11N. (For internal use only) */
+    unsigned dot11n : 1;
+#if CONFIG_11AC
+    /** The network supports 802.11AC. (For internal use only) */
+    unsigned dot11ac : 1;
+#endif
+#if CONFIG_11AX
+    /** The network supports 802.11AX. (For internal use only) */
+    unsigned dot11ax : 1;
+#endif
+
+#if CONFIG_11R
+    /** Mobility Domain ID */
+    uint16_t mdid;
+    /** The network uses FT 802.1x security (For internal use only)*/
+    unsigned ft_1x : 1;
+    /** The network uses FT PSK security (For internal use only)*/
+    unsigned ft_psk : 1;
+    /** The network uses FT SAE security (For internal use only)*/
+    unsigned ft_sae : 1;
+#endif
+#if CONFIG_DRIVER_OWE
+    /** OWE Transition mode */
+    unsigned int owe_trans_mode;
+    /** The network transitional SSID, represented as a C string of up to 32 characters
+     *  in length.
+     *
+     * This field is used internally.
+     */
+    char trans_ssid[IEEEtypes_SSID_SIZE + 1];
+    /** Transitional SSID length
+     *
+     * This field is used internally.
+     */
+    unsigned int trans_ssid_len;
+#endif
+    /** Beacon period of associated BSS */
+    uint16_t beacon_period;
+    /** DTIM period of associated BSS */
+    uint8_t dtim_period;
+#if CONFIG_WIFI_CAPA
+    /** Wi-Fi capabilities of UAP network 802.11n, 802.11ac or/and 802.11ax */
+    uint8_t wlan_capa;
+#endif
+#if CONFIG_11V
+    /** BTM mode */
+    uint8_t btm_mode;
+    /** BSS transition support (For internal use only) */
+    bool bss_transition_supported;
+#endif
+#if CONFIG_11K
+    /** Neighbor report support (For internal use only) */
+    bool neighbor_report_supported;
+#endif
+};
+
+/** This structure is for IEEE PS (power save) configuration */
+struct wlan_ieeeps_config
+{
+    /** PS null interval in seconds */
+    t_u32 ps_null_interval;
+    /** Multiple DTIM interval */
+    t_u32 multiple_dtim_interval;
+    /** Listen interval */
+    t_u32 listen_interval;
+    /** Adhoc awake period */
+    t_u32 adhoc_awake_period;
+    /** Beacon miss timeout in milliseconds */
+    t_u32 bcn_miss_timeout;
+    /** Delay to PS in milliseconds */
+    t_s32 delay_to_ps;
+    /** Power save mode,
+    0: Active mode,
+    1: IEEE power save mode,
+    2: Deep sleep power save mode,
+    3: IEEE and deep sleep power save mode,
+    4: WNM power save mode,
+    5: WNM and deep sleep power save mode. */
+    t_u32 ps_mode;
+};
+
+#if CONFIG_WIFI_TX_PER_TRACK
+/** TX per tracking structure
+ * Driver sets TX per tracking statistic to FW.
+ * FW can check TX packet error rate periodically and
+ * report per to host if per is high.
+ */
+struct wlan_tx_pert_info
+{
+    /** Enable/Disable TX per tracking */
+    t_u8 tx_pert_check;
+    /** Check period (unit sec) */
+    t_u8 tx_pert_check_peroid;
+    /** (Fail TX packet)/(Total TX packet) ratio (unit 10%)
+     * default: 5
+     */
+    t_u8 tx_pert_check_ratio;
+    /** A watermark of check number (default 5) */
+    t_u16 tx_pert_check_num;
+};
+#endif
+#if defined(RW610)
+typedef enum
+{
+    CLI_DISABLE_WIFI,
+    CLI_ENABLE_WIFI,
+    CLI_RESET_WIFI,
+} cli_reset_option;
+#endif
+
+enum wlan_mon_task_event
+{
+    HOST_SLEEP_HANDSHAKE = 1,
+    HOST_SLEEP_EXIT,
+    WIFI_RECOVERY_REQ,
+};
+
+#if CONFIG_HOST_SLEEP
+enum wlan_hostsleep_state
+{
+    HOST_SLEEP_DISABLE,
+    HOST_SLEEP_ONESHOT,
+    HOST_SLEEP_PERIODIC,
+};
+
+#define WLAN_HOSTSLEEP_SUCCESS    1
+#define WLAN_HOSTSLEEP_IN_PROCESS 2
+#define WLAN_HOSTSLEEP_FAIL       3
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+struct wlan_txrx_histogram_info
+{
+    /**  Enable or disable  */
+    t_u8 enable;
+    /** Choose to get TX, RX or both */
+    t_u16 action;
+};
+
+#define FLAG_TX_HISTOGRAM       0x01
+#define FLAG_RX_HISTOGRAM       0x02
+#define DISABLE_TX_RX_HISTOGRAM 0x00
+#define ENABLE_TX_RX_HISTOGRAM  0x01
+#define GET_TX_RX_HISTOGRAM     0x02
+
+/** Sum of TX packets for HT (802.11n high throughput) rate. */
+typedef struct _tx_pkt_ht_rate_info
+{
+    /** Sum of TX packets for HT rate. Array index represents MSC0~MCS15,
+    the following array indexs have the same effect. */
+    t_u32 htmcs_txcnt[16];
+    /** Sum of TX short GI (guard interval) packets for HT rate. */
+    t_u32 htsgi_txcnt[16];
+    /** Sum of TX STBC (space time block code) packets for HT rate. */
+    t_u32 htstbcrate_txcnt[16];
+} tx_pkt_ht_rate_info;
+
+/** Sum of TX packets for VHT (802.11ac very high throughput) rate. */
+typedef struct _tx_pkt_vht_rate_info
+{
+	/** Sum of TX packets for VHT rate. Array index represents MSC0~MCS9,
+	the following array indexs have the same effect. */
+    t_u32 vhtmcs_txcnt[10];
+	/** Sum of TX short GI packets for HT mode. */
+    t_u32 vhtsgi_txcnt[10];
+	/** Sum of TX STBC (space time block code) packets for VHT mode. */
+    t_u32 vhtstbcrate_txcnt[10];
+} tx_pkt_vht_rate_info;
+
+/** Sum of TX packets for HE (802.11ax high efficiency) rate. */
+typedef struct _tx_pkt_he_rate_info
+{
+    /** Sum of TX packets for HE rate. Array index represents MSC0~MCS11,
+	the following array indexs have the same effect. */
+    t_u32 hemcs_txcnt[12];
+    /** Sum of TX STBC (space time block code) packets for HE rate. */
+    t_u32 hestbcrate_txcnt[12];
+} tx_pkt_he_rate_info;
+
+/** Sum of TX packets. */
+typedef struct _tx_pkt_rate_info
+{
+    /** Sum of TX NSS (N*N MIMO spatial stream) packets.
+    nss_txcnt[0] is for NSS 1,
+    nss_txcnt[1] is for NSS 2.
+    */
+    t_u32 nss_txcnt[2];
+    /** Sum of TX packets for 3 bandwidths.
+    bandwidth_txcnt[0] is for 20MHz,
+    bandwidth_txcnt[1] is for 40MHz,
+    bandwidth_txcnt[2] is for 80MHz.
+    */
+    t_u32 bandwidth_txcnt[3];
+    /** Sum of RX packets for 4 preamble format types.
+    preamble_txcnt[0] is for preamble format 0,
+    preamble_txcnt[1] is for preamble format 1,
+    preamble_txcnt[2] is for preamble format 2,
+    preamble_txcnt[3] is for preamble format 3,
+    */
+    t_u32 preamble_txcnt[4];
+	/** Sum of TX LDPC (low density parity check) packets. */
+    t_u32 ldpc_txcnt;
+    /** Sum of TX RTS (require to send) packets */
+    t_u32 rts_txcnt;
+    /** RSSI of ACK packet */
+    t_s32 ack_RSSI;
+} tx_pkt_rate_info;
+
+/** Sum of RX packets for HT (802.11n high throughput) rate. */
+typedef struct _rx_pkt_ht_rate_info
+{
+    /** Sum of RX packets for HT rate. Array index represents MSC0~MCS15,
+    the following array indexs have the same effect.
+    */
+    t_u32 htmcs_rxcnt[16];
+	/** Sum of TX short GI (guard interval) packets for HT rate. */
+    t_u32 htsgi_rxcnt[16];
+	/** Sum of TX STBC (space time block code) packets for HT rate. */
+    t_u32 htstbcrate_rxcnt[16];
+} rx_pkt_ht_rate_info;
+
+/** Sum of RX packets for VHT (802.11ac very high throughput) rate. */
+typedef struct _rx_pkt_vht_rate_info
+{
+	/** Sum of RX packets for VHT rate. Array index represents MSC0~MCS9,
+	the following array indexs have the same effect. */
+    t_u32 vhtmcs_rxcnt[10];
+    /** Sum of RX short GI (guard interval) packets for VHT rate. */
+    t_u32 vhtsgi_rxcnt[10];
+	/** Sum of RX STBC (space time block code) packets for VHT rate. */
+    t_u32 vhtstbcrate_rxcnt[10];
+} rx_pkt_vht_rate_info;
+
+/** Sum of RX packets for HE (802.11ax high efficiency) rate. */
+typedef struct _rx_pkt_he_rate_info
+{
+    /** Sum of TX packets for HE rate. Array index represents MSC0~MCS11,
+	the following array indexs have the same effect. */
+    t_u32 hemcs_rxcnt[12];
+    /** Sum of TX STBC (space time block code) packets for HE rate. */
+    t_u32 hestbcrate_rxcnt[12];
+} rx_pkt_he_rate_info;
+
+/** Sum of RX packets. */
+typedef struct _rx_pkt_rate_info
+{
+    /** Sum of RX NSS (N*N MIMO spatial stream) packets.
+    nss_txcnt[0] is for NSS 1,
+    nss_txcnt[1] is for NSS 2.
+    */
+    t_u32 nss_rxcnt[2];
+    /** Sum of received packets for all STBC rates. */
+    t_u32 nsts_rxcnt;
+    /** Sum of received packets for 3 bandwith types.
+    bandwidth_rxcnt[0] is for 20MHz,
+    bandwidth_rxcnt[1] is for 40MHz,
+    bandwidth_rxcnt[2] is for 80MHz.
+    */
+    t_u32 bandwidth_rxcnt[3];
+    /** Sum of received packets for 4 preamble format types.
+    preamble_txcnt[0] is for preamble format 0,
+    preamble_txcnt[1] is for preamble format 1,
+    preamble_txcnt[2] is for preamble format 2,
+    preamble_txcnt[3] is for preamble format 3,
+    preamble_txcnt[4] and preamble_txcnt[5] are as reserved.
+    */
+    t_u32 preamble_rxcnt[6];
+    /** Sum of packets for TX LDPC packets. */
+    t_u32 ldpc_txbfcnt[2];
+    /** Average RSSI */
+    t_s32 rssi_value[2];
+    /** RSSI value of path A */
+    t_s32 rssi_chain0[4];
+    /** RSSI value of path B */
+    t_s32 rssi_chain1[4];
+} rx_pkt_rate_info;
+#endif
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+#define TX_AMPDU_RTS_CTS            0
+#define TX_AMPDU_CTS_2_SELF         1
+#define TX_AMPDU_DISABLE_PROTECTION 2
+#define TX_AMPDU_DYNAMIC_RTS_CTS    3
+
+/** Set protection mode for the transmit AMPDU packet */
+typedef struct _tx_ampdu_prot_mode_para
+{
+    /**
+    mode,
+    0: set RTS/CTS mode,
+    1: set CTS to self mode,
+    2: disable protection mode,
+    3: set dynamic RTS/CTS mode.
+    */
+    int mode;
+} tx_ampdu_prot_mode_para;
+#endif
+
+typedef wifi_uap_client_disassoc_t wlan_uap_client_disassoc_t;
+
+#if CONFIG_INACTIVITY_TIMEOUT_EXT
+typedef wifi_inactivity_to_t wlan_inactivity_to_t;
+#endif
+
+/* Wi-Fi connection manager API */
+/** Initialize Wi-Fi driver and create the Wi-Fi driver thread.
+ *
+ * \param[in]  fw_start_addr Start address of the Wi-Fi firmware.
+ * \param[in]  size Size of the Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if the Wi-Fi connection manager service has
+ *         initialized successfully.
+ * \return Negative value if initialization failed.
+ */
+int wlan_init(const uint8_t *fw_start_addr, const size_t size);
+
+/** Start the Wi-Fi connection manager service.
+ *
+ * This function starts the Wi-Fi connection manager.
+ *
+ * \note The status of the Wi-Fi connection manager is notified asynchronously
+ * through the callback, \a cb, with a WLAN_REASON_INITIALIZED event
+ * (if initialization succeeded) or WLAN_REASON_INITIALIZATION_FAILED
+ * (if initialization failed).
+ * If the Wi-Fi connection manager fails to initialize, the caller should
+ * stop Wi-Fi connection manager via wlan_stop() and try wlan_start() again.
+ *
+ * \param[in] cb A pointer to a callback function that handles Wi-Fi events. All
+ * further WLCMGR events can be notified in this callback. Refer to enum
+ * \ref wlan_event_reason for the various events for which this callback is called.
+ *
+ * \return WM_SUCCESS if the Wi-Fi connection manager service has started
+ *         successfully.
+ * \return -WM_E_INVAL if the \a cb pointer is NULL.
+ * \return -WM_FAIL if an internal error occurred.
+ * \return WLAN_ERROR_STATE if the Wi-Fi connection manager is already running.
+ */
+int wlan_start(int (*cb)(enum wlan_event_reason reason, void *data));
+
+/** Stop the Wi-Fi connection manager service.
+ *
+ *  This function stops the Wi-Fi connection manager, causing station interface
+ *  to disconnect from the currently connected network and stop the
+ * UAP interface.
+ *
+ *  \return WM_SUCCESS if the Wi-Fi connection manager service has been
+ *          stopped successfully.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not
+ *          running.
+ */
+int wlan_stop(void);
+
+/** Deinitialize Wi-Fi driver, send shutdown command to Wi-Fi firmware
+ *  and delete the Wi-Fi driver thread.
+ *  \param action Additional action to be taken with deinit
+ *			WLAN_ACTIVE: no action to be taken
+ */
+void wlan_deinit(int action);
+
+#if CONFIG_WPS2
+/** Generate valid pin code for WPS session.
+ *
+ *  This function generate pin for WPS pin session.
+ *
+ * \param[out]  pin A pointer to WPS pin to be generated.
+ */
+void wlan_wps_generate_pin(uint32_t *pin);
+
+/** Start WPS pin session.
+ *
+ *  This function starts WPS pin session.
+ *
+ * \param[in]  pin Pin for WPS session.
+ *
+ * \return WM_SUCCESS if the pin entered is valid.
+ * \return -WM_FAIL if invalid pin entered.
+ */
+int wlan_start_wps_pin(uint32_t pin);
+
+/** Start WPS PBC session.
+ *
+ *  This function starts WPS PBC session.
+ *
+ * \return  WM_SUCCESS if successful
+ */
+int wlan_start_wps_pbc(void);
+/**
+ * Set None/WPS/802.1x session.
+ *
+ *\param[in] session       0 -- PROV_NON_SESSION_ATTEMPT, 1 -- PROV_WPS_SESSION_ATTEMPT, 2 -- PROV_ENTP_SESSION_ATTEMPT.
+ */
+void wlan_set_prov_session(int session);
+
+/**
+ * Get connect session type.
+ *
+ * \return 0 -- PROV_NON_SESSION_ATTEMPT, 1 -- PROV_WPS_SESSION_ATTEMPT, 2 -- PROV_ENTP_SESSION_ATTEMPT.
+ */
+int wlan_get_prov_session(void);
+#endif
+
+/** Stop and remove all Wi-Fi network profiles.
+ *
+ *  \return WM_SUCCESS if successful otherwise return -WM_E_INVAL.
+ */
+int wlan_remove_all_network_profiles(void);
+
+#if defined(RW610)
+/** Reset driver.
+ *  \param[in] ResetOption Option including enable, disable or reset Wi-Fi driver
+ *  can be chosen.
+ */
+void wlan_reset(cli_reset_option ResetOption);
+/** Stop and remove all Wi-Fi network (access point).
+ *
+ *  \return WM_SUCCESS if successful.
+ */
+int wlan_remove_all_networks(void);
+
+/**
+ * This API destroy all tasks.
+ */
+void wlan_destroy_all_tasks(void);
+/** Retrieve the status information of if Wi-Fi started.
+ *
+ *  \return TRUE if Wi-Fi network is started.
+ *  \return FALSE if not started.
+ */
+int wlan_is_started(void);
+
+#endif // RW610
+
+#if CONFIG_NCP
+/** UAP provisioning deinit callback function */
+void wlan_register_uap_prov_deinit_cb(int (*cb)(void));
+/** UAP provisioning cleanup callback function */
+void wlan_register_uap_prov_cleanup_cb(void (*cb)(void));
+/** Stop all Wi-Fi network.
+ *
+ *  \return WM_SUCCESS if successful.
+ */
+int wlan_stop_all_networks(void);
+#endif
+
+#if CONFIG_RX_ABORT_CFG
+struct wlan_rx_abort_cfg
+{
+    /** Enable/Disable RX abort configuration */
+    t_u8 enable;
+    /** RX weak RSSI threshold */
+    int rssi_threshold;
+};
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+struct wlan_rx_abort_cfg_ext
+{
+    /** Enable/Disable dyn RX abort on weak packet RSSI */
+    int enable;
+    /** Specify RSSI margin */
+    int rssi_margin;
+    /** Specify ceil RSSI threshold */
+    int ceil_rssi_threshold;
+    /** Specify floor RSSI threshold */
+    int floor_rssi_threshold;
+    /** Current dynamic RSSI threshold */
+    int current_dynamic_rssi_threshold;
+    /** RSSI config: default or user configured */
+    int rssi_default_config;
+    /** EDMAC status */
+    int edmac_enable;
+};
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+#define CCK_DESENSE_MODE_DISABLED 0
+#define CCK_DESENSE_MODE_DYNAMIC  1
+#define CCK_DESENSE_MODE_DYN_ENH  2
+
+struct wlan_cck_desense_cfg
+{
+    /** CCK (complementary code keying) desense mode: 0:disable 1:normal 2:dynamic */
+    t_u16 mode;
+    /** Specify RSSI margin */
+    int margin;
+    /** Specify ceil RSSI threshold */
+    int ceil_thresh;
+    /** CCK (complementary code keying) desense "on" interval count */
+    int num_on_intervals;
+    /** CCK desense "off" interval count */
+    int num_off_intervals;
+};
+#endif
+#if CONFIG_RX_ABORT_CFG
+/**
+ * Set/Get RX abort configure to/from firmware.
+ *
+ * \param[in,out] cfg A pointer to information buffer
+ * \param[in] action Command action: get or set
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_get_rx_abort_cfg(struct wlan_rx_abort_cfg *cfg, t_u16 action);
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+/**
+ * Set dynamic RX abort config to firmware.
+ *
+ * \param[in] cfg A pointer to information buffer
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_rx_abort_cfg_ext(const struct wlan_rx_abort_cfg_ext *cfg);
+
+/**
+ * Get dynamic RX abort config from firmware.
+ *
+ * \param[in,out] cfg A pointer to information buffer
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_rx_abort_cfg_ext(struct wlan_rx_abort_cfg_ext *cfg);
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+/**
+ * Set/Get CCK (complementary code keying) desense configure to/from firmware.
+ *
+ * \param[in,out] cfg A pointer to information buffer
+ * \param[in] action get or set.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_get_cck_desense_cfg(struct wlan_cck_desense_cfg *cfg, t_u16 action);
+#endif
+
+/** Wi-Fi initialize UAP network information
+ *
+ * This API intializes a default UAP network. The network ssid, passphrase
+ * is initialized to NULL. Channel is set to auto. The IP Address of the
+ * UAP interface is 192.168.10.1/255.255.255.0. Network name is set to
+ * 'uap-network'.
+ *
+ * \param[out] net Pointer to the initialized UAP network
+ */
+void wlan_initialize_uap_network(struct wlan_network *net);
+
+/** Wi-Fi initialize station network information
+ *
+ * This API intializes a default station network. The network ssid, passphrase
+ * is initialized to NULL. Channel is set to auto.
+ *
+ * \param[out] net Pointer to the initialized UAP network
+ */
+void wlan_initialize_sta_network(struct wlan_network *net);
+
+/** Add a network profile to the list of known networks.
+ *
+ *  This function copies the contents of \a network to the list of known
+ *  networks in the Wi-Fi connection manager. The network's 'name' field is
+ *  unique and between \ref WLAN_NETWORK_NAME_MIN_LENGTH and \ref
+ *  WLAN_NETWORK_NAME_MAX_LENGTH characters.  The network must specify at least
+ *  an SSID or BSSID.  the Wi-Fi connection manager may store up to
+ *  WLAN_MAX_KNOWN_NETWORKS networks.
+ *
+ *  \note Profiles for the station interface may be added only when the station
+ *  interface is in the \ref WLAN_DISCONNECTED or \ref WLAN_CONNECTED state.
+ *
+ *  \note This API can be used to add profiles for station or
+ *  UAP interfaces.
+ *
+ *  \note Set mfpc and mfpr to -1 for default configurations.
+ *
+ *  \param[in] network A pointer to the \ref wlan_network that can be copied
+ *             to the list of known networks in the Wi-Fi connection manager
+ *             successfully.
+ *
+ *  \return WM_SUCCESS if the contents pointed to by \a network have been
+ *          added to the Wi-Fi connection manager.
+ *  \return -WM_E_INVAL if \a network is NULL or the network name
+ *          is not unique or the network name length is not valid
+ *          or network security is \ref WLAN_SECURITY_WPA3_SAE but
+ *          Management Frame Protection Capable is not enabled.
+ *          in \ref wlan_network_security field. if network security type is
+ *          \ref WLAN_SECURITY_WPA or \ref WLAN_SECURITY_WPA2 or \ref
+ *          WLAN_SECURITY_WPA_WPA2_MIXED, but the passphrase length is less
+ *          than 8 or greater than 63, or the psk length equal to 64 but not
+ *          hexadecimal digits. if network security type is \ref WLAN_SECURITY_WPA3_SAE,
+ *          but the password length is less than 8 or greater than 255.
+ *          if network security type is \ref WLAN_SECURITY_WEP_OPEN or
+ *          \ref WLAN_SECURITY_WEP_SHARED.
+ *  \return -WM_E_NOMEM if there was no room to add the network.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager
+ *          was running and not in the \ref WLAN_DISCONNECTED,
+ *          \ref WLAN_ASSOCIATED or \ref WLAN_CONNECTED state.
+ */
+int wlan_add_network(struct wlan_network *network);
+
+/** Remove a network profile from the list of known networks.
+ *
+ *  This function removes a network (identified by its name) from the WLAN
+ *  Connection Manager, disconnecting from that network if connected.
+ *
+ *  \note This function is asynchronous if it is called while the WLAN
+ *  Connection Manager is running and connected to the network to be removed.
+ *  In that case, the Wi-Fi connection manager can disconnect from the network
+ *  and generate an event with reason \ref WLAN_REASON_USER_DISCONNECT. This
+ *  function is synchronous otherwise.
+ *
+ *  \note This API can be used to remove profiles for station or
+ *  UAP interfaces. Station network can not be removed if it is
+ *  in \ref WLAN_CONNECTED state and UAP network can not be removed
+ *  if it is in \ref WLAN_UAP_STARTED state.
+ *
+ *  \param[in] name A pointer to the string representing the name of the
+ *             network to remove.
+ *
+ *  \return WM_SUCCESS if the network named \a name was removed from the
+ *          Wi-Fi connection manager successfully. Otherwise,
+ *          the network is not removed.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *          running and the station interface was not in the \ref
+ *          WLAN_DISCONNECTED state.
+ *  \return -WM_E_INVAL if \a name is NULL or the network was not found in
+ *          the list of known networks.
+ *  \return -WM_FAIL if an internal error occurred
+ *          while trying to disconnect from the network specified for
+ *          removal.
+ */
+int wlan_remove_network(const char *name);
+
+/** Connect to a Wi-Fi network (access point).
+ *
+ *  When this function is called, Wi-Fi connection manager starts connection attempts
+ *  to the network specified by \a name. The connection result can be notified
+ *  asynchronously to the WLCMGR callback when the connection process has
+ *  completed.
+ *
+ *  When connecting to a network, the event refers to the connection
+ *  attempt to that network.
+ *
+ *  Calling this function when the station interface is in the \ref
+ *  WLAN_DISCONNECTED state should, if successful, cause the interface to
+ *  transition into the \ref WLAN_CONNECTING state. If the connection attempt
+ *  succeeds, the station interface should transition to the \ref WLAN_CONNECTED state,
+ *  otherwise it should return to the \ref WLAN_DISCONNECTED state.  If this
+ *  function is called while the station interface is in the \ref
+ *  WLAN_CONNECTING or \ref WLAN_CONNECTED state, the Wi-Fi connection manager
+ *  should first cancel its connection attempt or disconnect from the network,
+ *  respectively, and generate an event with reason \ref
+ *  WLAN_REASON_USER_DISCONNECT. This should be followed by a second event that
+ *  reports the result of the new connection attempt.
+ *
+ *  If the connection attempt was successful the WLCMGR callback is notified
+ *  with the event \ref WLAN_REASON_SUCCESS, while if the connection attempt
+ *  fails then either of the events, \ref WLAN_REASON_NETWORK_NOT_FOUND, \ref
+ *  WLAN_REASON_NETWORK_AUTH_FAILED, \ref WLAN_REASON_CONNECT_FAILED
+ *  or \ref WLAN_REASON_ADDRESS_FAILED are reported as appropriate.
+ *
+ *  \param[in] name A pointer to a string representing the name of the network
+ *              to connect to.
+ *
+ *  \return WM_SUCCESS if a connection attempt was started successfully
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not running.
+ *  \return -WM_E_INVAL if there are no known networks to connect to
+ *          or the network specified by \a name is not in the list
+ *          of known networks or network \a name is NULL.
+ *  \return -WM_FAIL if an internal error has occurred.
+ */
+int wlan_connect(char *name);
+
+/** Connect to a Wi-Fi network (access point) with options.
+ *
+ *  When this function is called, Wi-Fi connection manager starts connection attempts
+ *  to the network specified by \a name. The connection result should be notified
+ *  asynchronously to the WLCMGR callback when the connection process has
+ *  completed.
+ *
+ *  When connecting to a network, the event refers to the connection
+ *  attempt to that network.
+ *
+ *  Calling this function when the station interface is in the \ref
+ *  WLAN_DISCONNECTED state should, if successful, cause the interface to
+ *  transition into the \ref WLAN_CONNECTING state.  If the connection attempt
+ *  succeeds, the station interface should transition to the \ref WLAN_CONNECTED state,
+ *  otherwise it should return to the \ref WLAN_DISCONNECTED state.  If this
+ *  function is called while the station interface is in the \ref
+ *  WLAN_CONNECTING or \ref WLAN_CONNECTED state, the Wi-Fi connection manager
+ *  should first cancel its connection attempt or disconnect from the network,
+ *  respectively, and generate an event with reason \ref
+ *  WLAN_REASON_USER_DISCONNECT. This should be followed by a second event that
+ *  reports the result of the new connection attempt.
+ *
+ *  If the connection attempt was successful the WLCMGR callback is notified
+ *  with the event \ref WLAN_REASON_SUCCESS, while if the connection attempt
+ *  fails then either of the events, \ref WLAN_REASON_NETWORK_NOT_FOUND, \ref
+ *  WLAN_REASON_NETWORK_AUTH_FAILED, \ref WLAN_REASON_CONNECT_FAILED
+ *  or \ref WLAN_REASON_ADDRESS_FAILED are reported as appropriate.
+ *
+ *  \param[in] name A pointer to a string representing the name of the network
+ *              to connect to.
+ *  \param[in] skip_dfs Option to skip DFS channel when doing scan.
+ *
+ *  \return WM_SUCCESS if a connection attempt was started successfully
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not running.
+ *  \return -WM_E_INVAL if there are no known networks to connect to
+ *          or the network specified by \a name is not in the list
+ *          of known networks or network \a name is NULL.
+ *  \return -WM_FAIL if an internal error has occurred.
+ */
+int wlan_connect_opt(char *name, bool skip_dfs);
+
+/** Reassociate to a Wi-Fi network (access point).
+ *
+ *  When this function is called, Wi-Fi connection manager starts reassociation
+ *  attempts using same SSID as currently connected network .
+ *  The connection result should be notified asynchronously to the WLCMGR
+ *  callback when the connection process has completed.
+ *
+ *  When connecting to a network, the event refers to the connection
+ *  attempt to that network.
+ *
+ *  Calling this function when the station interface is in the \ref
+ *  WLAN_DISCONNECTED state should have no effect.
+ *
+ *  Calling this function when the station interface is in the \ref
+ *  WLAN_CONNECTED state should, if successful, cause the interface to
+ *  reassociate to another network (access point).
+ *
+ *  If the connection attempt was successful the WLCMGR (Wi-Fi command manager) callback is notified
+ *  with the event \ref WLAN_REASON_SUCCESS, while if the connection attempt
+ *  fails then either of the events, \ref WLAN_REASON_NETWORK_AUTH_FAILED,
+ *  \ref WLAN_REASON_CONNECT_FAILED or \ref WLAN_REASON_ADDRESS_FAILED
+ *  are reported as appropriate.
+ *
+ *  \return WM_SUCCESS if a reassociation attempt was started successfully
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not running.
+ *          or Wi-Fi connection manager was not in \ref WLAN_CONNECTED state.
+ *  \return -WM_E_INVAL if there are no known networks to connect to
+ *  \return -WM_FAIL if an internal error has occurred.
+ */
+int wlan_reassociate(void);
+
+/** Disconnect from the current Wi-Fi network (access point).
+ *
+ *  When this function is called, the Wi-Fi connection manager attempts to disconnect
+ *  the station interface from its currently connected network (or cancel an in-progress
+ *  connection attempt) and return to the \ref WLAN_DISCONNECTED state. Calling
+ *  this function has no effect if the station interface is already
+ *  disconnected.
+ *
+ *  \note This is an asynchronous function and successful disconnection should be
+ *  notified using the \ref WLAN_REASON_USER_DISCONNECT.
+ *
+ * \return  WM_SUCCESS if successful
+ * \return  WLAN_ERROR_STATE otherwise
+ */
+int wlan_disconnect(void);
+
+/** Start a Wi-Fi network (access point).
+ *
+ *  When this function is called, the Wi-Fi connection manager starts the network
+ *  specified by \a name. The network with the specified \a name is
+ *  first added using \ref wlan_add_network and is a UAP network with
+ *  a valid SSID.
+ *
+ *  \note The WLCMGR callback is asynchronously notified of the status. On
+ *  success, the event \ref WLAN_REASON_UAP_SUCCESS is reported, while on
+ *  failure, the event \ref WLAN_REASON_UAP_START_FAILED is reported.
+ *
+ *  \param[in] name A pointer to string representing the name of the network
+ *             to connect to.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return WLAN_ERROR_STATE if in power save state or UAP already running.
+ *  \return -WM_E_INVAL if \a name was NULL or the network \a
+ *          name was not found or it not have a specified SSID.
+ */
+int wlan_start_network(const char *name);
+
+/** Stop a Wi-Fi network (access point).
+ *
+ *  When this function is called, the Wi-Fi connection manager stops the network
+ *  specified by \a name. The specified network is a valid UAP
+ *  network that has already been started.
+ *
+ *  \note The WLCMGR callback is asynchronously notified of the status. On
+ *  success, the event \ref WLAN_REASON_UAP_STOPPED is reported, while on
+ *  failure, the event \ref WLAN_REASON_UAP_STOP_FAILED is reported.
+ *
+ *  \param[in] name A pointer to a string representing the name of the network
+ *             to stop.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return WLAN_ERROR_STATE if UAP is in power save state.
+ *  \return -WM_E_INVAL if \a name was NULL or the network \a
+ *          name was not found or that the network \a name is not a UAP
+ *          network or it is a UAP network but does not have a specified
+ *          SSID.
+ */
+int wlan_stop_network(const char *name);
+
+/** Retrieve the Wi-Fi MAC address of station interface.
+ *
+ *  This function copies the MAC address of the station interface to STA MAC address and UAP interface to UAP mac
+ * address.
+ *
+ *  \param[out] dest A pointer to a 6-byte array where the MAC address should be
+ *              copied.
+ *
+ *  \return WM_SUCCESS if the MAC address was copied.
+ *  \return -WM_E_INVAL if \a sta_mac or UAP_mac is NULL.
+ */
+int wlan_get_mac_address(uint8_t *dest);
+
+/** Retrieve the Wi-Fi MAC address of UAP interface.
+ *
+ *  This function copies the MAC address of the Wi-Fi interface to
+ *  the 6-byte array pointed to by \a dest. In the event of an error, nothing
+ *  is copied to \a dest.
+ *
+ *  \param[out] dest A pointer to a 6-byte array where the MAC address can be
+ *              copied.
+ *
+ *  \return WM_SUCCESS if the MAC address was copied.
+ *  \return -WM_E_INVAL if \a dest is NULL.
+ */
+int wlan_get_mac_address_uap(uint8_t *dest);
+
+/** Retrieve the IP address configuration of the station interface.
+ *
+ *  This function retrieves the IP address configuration
+ *  of the station interface and copies it to the memory
+ *  location pointed to by \a addr.
+ *
+ *  \note This function may only be called when the station interface is in the
+ *  \ref WLAN_CONNECTED state.
+ *
+ *  \param[out] addr A pointer to the \ref wlan_ip_config.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a addr is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not running or was
+ *          not in the \ref WLAN_CONNECTED state.
+ *  \return -WM_FAIL if an internal error
+ *          occurred when retrieving IP address information from the
+ *          TCP stack.
+ */
+int wlan_get_address(struct wlan_ip_config *addr);
+
+/** Retrieve the IP address of UAP interface.
+ *
+ *  This function retrieves the current IP address configuration of UAP
+ *  and copies it to the memory location pointed to by \a addr.
+ *
+ *  \note This function may only be called when the UAP interface is in the
+ *  \ref WLAN_UAP_STARTED state.
+ *
+ *  \param[out] addr A pointer to the \ref wlan_ip_config.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a addr is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not running or
+ *          the UAP interface was not in the \ref WLAN_UAP_STARTED state.
+ *  \return -WM_FAIL if an internal error
+ *          occurred when retrieving IP address information from the
+ *          TCP stack.
+ */
+int wlan_get_uap_address(struct wlan_ip_config *addr);
+
+/** Retrieve the channel of UAP interface.
+ *
+ *  This function retrieves the channel number of UAP
+ *  and copies it to the memory location pointed to by \a channel.
+ *
+ *  \note This function may only be called when the UAP interface is in the
+ *  \ref WLAN_UAP_STARTED state.
+ *
+ *  \param[out] channel A pointer to variable that stores channel number.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a channel is NULL.
+ *  \return -WM_FAIL if an internal error has occurred.
+ */
+int wlan_get_uap_channel(int *channel);
+
+/** Retrieve the current network configuration of station interface.
+ *
+ *  This function retrieves the current network configuration of station
+ *  interface when the station interface is in the \ref WLAN_CONNECTED
+ *  state.
+ *
+ *  \param[out] network A pointer to the \ref wlan_network.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a network is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *          not running or not in the \ref WLAN_CONNECTED state.
+ */
+int wlan_get_current_network(struct wlan_network *network);
+
+/** Retrieve the current network ssid of station interface.
+ *
+ *  This function retrieves the current network ssid of station
+ *  interface when the station interface is in the \ref WLAN_CONNECTED
+ *  state.
+ *
+ *  \param[out] ssid A pointer to the ssid.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a network is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *          not running or not in the \ref WLAN_CONNECTED state.
+ */
+int wlan_get_current_network_ssid(char *ssid);
+
+/** Retrieve the current network bssid of station interface.
+ *
+ *  This function retrieves the current network bssid of station
+ *  interface when the station interface is in the \ref WLAN_CONNECTED
+ *  state.
+ *
+ *  \param[out] bssid A pointer to the bssid.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a network is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *          not running or not in the \ref WLAN_CONNECTED state.
+ */
+int wlan_get_current_network_bssid(char *bssid);
+
+/** Retrieve the current network configuration of UAP interface.
+ *
+ *  This function retrieves the current network configuration of UAP
+ *  interface when the UAP interface is in the \ref WLAN_UAP_STARTED state.
+ *
+ *  \param[out] network A pointer to the \ref wlan_network.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a network is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *           not running or not in the \ref WLAN_UAP_STARTED state.
+ */
+int wlan_get_current_uap_network(struct wlan_network *network);
+
+/** Retrieve the current network ssid of UAP interface.
+ *
+ *  This function retrieves the current network ssid of UAP
+ *  interface when the UAP interface is in the \ref WLAN_UAP_STARTED state.
+ *
+ *  \param[out] ssid A pointer to the ssid.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a network is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *           not running or not in the \ref WLAN_UAP_STARTED state.
+ */
+int wlan_get_current_uap_network_ssid(char *ssid);
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+int wlan_set_rssi_threshold(int rssithr);
+#endif
+
+/** Retrieve the status information of the UAP interface.
+ *
+ *  \return TRUE if UAP interface is in \ref WLAN_UAP_STARTED state.
+ *  \return FALSE otherwise.
+ */
+bool is_uap_started(void);
+
+/** Retrieve the status information of the station interface.
+ *
+ *  \return TRUE if station interface is in \ref WLAN_CONNECTED state.
+ *  \return FALSE otherwise.
+ */
+bool is_sta_connected(void);
+
+/** Retrieve the status information of the ipv4 network of station interface.
+ *
+ *  \return TRUE if ipv4 network of station interface is in \ref WLAN_CONNECTED
+ *  state.
+ *  \return FALSE otherwise.
+ */
+bool is_sta_ipv4_connected(void);
+
+#if CONFIG_IPV6
+/** Retrieve the status information of the ipv6 network of station interface.
+ *
+ *  \return TRUE if ipv6 network of station interface is in \ref WLAN_CONNECTED
+ *  state.
+ *  \return FALSE otherwise.
+ */
+bool is_sta_ipv6_connected(void);
+#endif
+
+/** Retrieve the information about a known network using \a index.
+ *
+ *  This function retrieves the contents of a network at \a index in the
+ *  list of known networks maintained by the Wi-Fi connection manager and
+ *  copies it to the location pointed to by \a network.
+ *
+ *  \note \ref wlan_get_network_count() may be used to retrieve the number
+ *  of known networks. \ref wlan_get_network() may be used to retrieve
+ *  information about networks at \a index 0 to one minus the number of networks.
+ *
+ *  \note This function may be called regardless of whether the Wi-Fi connection
+ *  manager is running. Calls to this function are synchronous.
+ *
+ *  \param[in] index The index of the network to retrieve.
+ *  \param[out] network A pointer to the \ref wlan_network where the network
+ *              configuration for the network at \a index can be copied.
+ *
+ *  \returns WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a network is NULL or \a index is out of range.
+ */
+int wlan_get_network(unsigned int index, struct wlan_network *network);
+
+/** Retrieve information about a known network using \a name.
+ *
+ *  This function retrieves the contents of a named network in the
+ *  list of known networks maintained by the Wi-Fi connection manager and
+ *  copies it to the location pointed to by \a network.
+ *
+ *  \note This function may be called regardless of whether the Wi-Fi Connection
+ *  Manager is running. Calls to this function are synchronous.
+ *
+ *  \param[in] name The name of the network to retrieve.
+ *  \param[out] network A pointer to the \ref wlan_network where the network
+ *              configuration for the network having name as \a name should be copied.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a network is NULL or \a name is NULL.
+ */
+int wlan_get_network_byname(char *name, struct wlan_network *network);
+
+/** Retrieve the number of networks known to the Wi-Fi connection manager.
+ *
+ *  This function retrieves the number of known networks in the list maintained
+ *  by the Wi-Fi connection manager and copies it to \a count.
+ *
+ *  \note This function may be called regardless of whether the Wi-Fi Connection
+ *  Manager is running. Calls to this function are synchronous.
+ *
+ *  \param[out] count A pointer to the memory location where the number of
+ *              networks should be copied.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a count is NULL.
+ */
+int wlan_get_network_count(unsigned int *count);
+
+/** Retrieve the connection state of station interface.
+ *
+ *  This function retrieves the connection state of station interface, which is
+ *  one of \ref WLAN_DISCONNECTED, \ref WLAN_CONNECTING, \ref WLAN_ASSOCIATED
+ *  or \ref WLAN_CONNECTED.
+ *
+ *  \param[out] state A pointer to the \ref wlan_connection_state where the
+ *         current connection state should be copied.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a state is NULL
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not running.
+ */
+int wlan_get_connection_state(enum wlan_connection_state *state);
+
+/** Retrieve the connection state of UAP interface.
+ *
+ *  This function retrieves the connection state of UAP interface, which is
+ *  one of \ref WLAN_UAP_STARTED, or \ref WLAN_UAP_STOPPED.
+ *
+ *  \param[out] state A pointer to the \ref wlan_connection_state where the
+ *         current connection state should be copied.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a state is NULL
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was not running.
+ */
+int wlan_get_uap_connection_state(enum wlan_connection_state *state);
+
+/** Scan for Wi-Fi networks.
+ *
+ *  When this function is called, the Wi-Fi connection manager starts scan
+ *  for Wi-Fi networks. On completion of the scan the Wi-Fi connection manager
+ *  can call the specified callback function \a cb. The callback function should then
+ *  retrieve the scan results by using the \ref wlan_get_scan_result() function.
+ *
+ *  \note This function may only be called when the station interface is in the
+ *  \ref WLAN_DISCONNECTED or \ref WLAN_CONNECTED state. scan is disabled
+ *  in the \ref WLAN_CONNECTING state.
+ *
+ *  \note This function should block until it can issue a scan request if called
+ *  while another scan is in progress.
+ *
+ *  \param[in] cb A pointer to the function that should be called to handle scan
+ *         results when they are available.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_NOMEM if failed to allocated memory for \ref
+ *	     wlan_scan_params_v2_t structure.
+ *  \return -WM_E_INVAL if \a cb scan result callack functio pointer is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *           not running or not in the \ref WLAN_DISCONNECTED or \ref
+ *           WLAN_CONNECTED states.
+ *  \return -WM_FAIL if an internal error has occurred and
+ *           the system is unable to scan.
+ */
+int wlan_scan(int (*cb)(unsigned int count));
+
+/** Scan for Wi-Fi networks using options provided.
+ *
+ *  When this function is called, the Wi-Fi connection manager starts scan
+ *  for Wi-Fi networks. On completion of the scan the Wi-Fi connection manager
+ *  should call the specified callback function \a cb. The callback function
+ *  should then retrieve the scan results by using the \ref wlan_get_scan_result()
+ *  function.
+ *
+ *  \note This function may only be called when the station interface is in the
+ *  \ref WLAN_DISCONNECTED or \ref WLAN_CONNECTED state. scan is disabled
+ *  in the \ref WLAN_CONNECTING state.
+ *
+ *  \note This function can block until it issue a scan request if called
+ *  while another scan is in progress.
+ *
+ *  \param[in] t_wlan_scan_param  A \ref wlan_scan_params_v2_t structure holding
+ *	       a pointer to function that should be called
+ *	       to handle scan results when they are available,
+ *	       SSID of a Wi-Fi network, BSSID of a Wi-Fi network,
+ *	       number of channels with scan type information and number of
+ *	       probes.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_NOMEM if failed to allocated memory for \ref
+ *	     wlan_scan_params_v2_t structure.
+ *  \return -WM_E_INVAL if \a cb scan result callack function pointer is NULL.
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager was
+ *           not running or not in the \ref WLAN_DISCONNECTED or \ref
+ *           WLAN_CONNECTED states.
+ *  \return -WM_FAIL if an internal error has occurred and
+ *           the system is unable to scan.
+ */
+int wlan_scan_with_opt(wlan_scan_params_v2_t t_wlan_scan_param);
+
+/** Retrieve a scan result.
+ *
+ *  This function may be called to retrieve scan results when the Wi-Fi
+ *  connection manager has finished scanning. It is called from within the
+ *  scan result callback (see \ref wlan_scan()) as scan results are valid
+ *  only in that context. The callback argument 'count' provides the number
+ *  of scan results that may be retrieved and \ref wlan_get_scan_result() may
+ *  be used to retrieve scan results at \a index 0 through that number.
+ *
+ *  \note This function may only be called in the context of the scan results
+ *  callback.
+ *
+ *  \note Calls to this function are synchronous.
+ *
+ *  \param[in] index The scan result to retrieve.
+ *  \param[out] res A pointer to the \ref wlan_scan_result where the scan
+ *              result information should be copied.
+ *
+ *  \return WM_SUCCESS if successful.
+ *  \return -WM_E_INVAL if \a res is NULL
+ *  \return WLAN_ERROR_STATE if the Wi-Fi connection manager
+ *          was not running
+ *  \return -WM_FAIL if the scan result at \a
+ *          index could not be retrieved (that is, \a index
+ *          is out of range).
+ */
+int wlan_get_scan_result(unsigned int index, struct wlan_scan_result *res);
+
+#ifdef WLAN_LOW_POWER_ENABLE
+/**
+ * Enable low power mode in Wi-Fi Firmware.
+ *
+ * \note When low power mode is enabled, the output power should be clipped at
+ * ~+10dBm and the expected PA current is expected to be in the 80-90 mA
+ * range for b/g/n modes.
+ *
+ * This function may be called to enable low power mode in firmware.
+ * This should be called before \ref wlan_init() function.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ *
+ */
+int wlan_enable_low_pwr_mode(void);
+#endif
+
+/**
+ * Configure ED MAC mode for station in Wi-Fi Firmware.
+ *
+ * \note When ED MAC mode is enabled,
+ * Wi-Fi Firmware can behave following way:
+ *
+ * when background noise had reached -70dB or above,
+ * Wi-Fi chipset/module should hold data transmitting
+ * until condition is removed.
+ * It is applicable for both 5GHz and 2.4GHz bands.
+ *
+ * \param[in] wlan_ed_mac_ctrl  Struct with following parameters
+ *	 ed_ctrl_2g	     0  - disable EU adaptivity for 2.4GHz band
+ *                           1  - enable EU adaptivity for 2.4GHz band
+ *
+ *       ed_offset_2g        0  - Default Energy Detect threshold (Default: 0x9)
+ *                           offset value range: 0x80 to 0x7F
+ *
+ * \note If 5GH enabled then add following parameters
+ *
+ *       ed_ctrl_5g          0  - disable EU adaptivity for 5GHz band
+ *                           1  - enable EU adaptivity for 5GHz band
+ *
+ *       ed_offset_5g        0  - Default Energy Detect threshold(Default: 0xC)
+ *                           offset value range: 0x80 to 0x7F
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ *
+ */
+int wlan_set_ed_mac_mode(wlan_ed_mac_ctrl_t wlan_ed_mac_ctrl);
+
+/**
+ * Configure ED MAC mode for UAP in Wi-Fi firmware.
+ *
+ * \note When ED MAC mode is enabled,
+ * Wi-Fi Firmware can behave following way:
+ *
+ * when background noise had reached -70dB or above,
+ * Wi-Fi chipset/module should hold data transmitting
+ * until condition is removed.
+ * It is applicable for both 5GHz and 2.4GHz bands.
+ *
+ * \param[in] wlan_ed_mac_ctrl  Struct with following parameters
+ *	 ed_ctrl_2g	     0  - disable EU adaptivity for 2.4GHz band
+ *                           1  - enable EU adaptivity for 2.4GHz band
+ *
+ *       ed_offset_2g        0  - Default energy detect threshold (Default: 0x9)
+ *                           offset value range: 0x80 to 0x7F
+ *
+ * \note If 5GH enabled then add following parameters
+ *
+ *       ed_ctrl_5g          0  - disable EU adaptivity for 5GHz band
+ *                           1  - enable EU adaptivity for 5GHz band
+ *
+ *       ed_offset_5g        0  - Default energy detect threshold(Default: 0xC)
+ *                           offset value range: 0x80 to 0x7F
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ *
+ */
+int wlan_set_uap_ed_mac_mode(wlan_ed_mac_ctrl_t wlan_ed_mac_ctrl);
+
+/**
+ * This API can be used to get current ED MAC MODE configuration for station.
+ *
+ * \param[out] wlan_ed_mac_ctrl A pointer to \ref wlan_ed_mac_ctrl_t
+ * 			with parameters mentioned in above set API.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ *
+ */
+int wlan_get_ed_mac_mode(wlan_ed_mac_ctrl_t *wlan_ed_mac_ctrl);
+
+/**
+ * This API can be used to get current ED MAC MODE configuration for UAP.
+ *
+ * \param[out] wlan_ed_mac_ctrl A pointer to \ref wlan_ed_mac_ctrl_t
+ * 			with parameters mentioned in above set API.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ *
+ */
+int wlan_get_uap_ed_mac_mode(wlan_ed_mac_ctrl_t *wlan_ed_mac_ctrl);
+
+/** Set Wi-Fi calibration data in Wi-Fi firmware.
+ *
+ * This function may be called to set Wi-Fi calibration data in firmware.
+ * This should be call before \ref wlan_init() function.
+ *
+ * \param[in] cal_data The calibration data buffer
+ * \param[in] cal_data_size Size of calibration data buffer.
+ *
+ */
+void wlan_set_cal_data(const uint8_t *cal_data, const unsigned int cal_data_size);
+
+/** Set Wi-Fi MAC Address in Wi-Fi firmware.
+ *
+ * This function may be called to set Wi-Fi MAC Address in firmware.
+ * This should be call before \ref wlan_init() function.
+ * When called after Wi-Fi init done, the incoming MAC is treated as the STA MAC address directly. And mac[4] plus 1 the
+ * modifed MAC as the UAP MAC address.
+ *
+ * \param[in] MAC The MAC Address in 6 byte array format like
+ *                uint8_t mac[] = { 0x00, 0x50, 0x43, 0x21, 0x19, 0x6E};
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_set_mac_addr(uint8_t *mac);
+
+/** Set Wi-Fi MAC address for STA in Wi-Fi firmware.
+ *
+ * This function may be called to set Wi-Fi MAC address in firmware.
+ * This should be call before \ref wlan_init() function.
+ * When called after Wi-Fi init done, it can set only STA MAC adderess.
+ *
+ * \param[in] MAC The MAC Address in 6 byte array format like
+ *                uint8_t mac[] = { 0x00, 0x50, 0x43, 0x21, 0x19, 0x6E};
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_set_sta_mac_addr(uint8_t *mac);
+
+/** Set Wi-Fi MAC address for UAP in Wi-Fi firmware.
+ *
+ * This function may be called to set Wi-Fi MAC address in firmware.
+ * This should be call before \ref wlan_init() function.
+ * When called after Wi-Fi init done, it can set only UAP MAC address.
+ *
+ * \param[in] MAC The MAC Address in 6 byte array format like
+ *                uint8_t mac[] = { 0x00, 0x50, 0x43, 0x21, 0x19, 0x6E};
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_set_uap_mac_addr(uint8_t *mac);
+
+#if CONFIG_WMM_UAPSD
+/** Set QOS info in Wi-Fi firmware.
+ *
+ * \param[in] qos_info UAPSD (unscheduled automatic power save delivery) QOS info.
+ * \param[in] action Set/get action.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_wmm_uapsd_qosinfo(t_u8 *qos_info, t_u8 action);
+/** Enable/Disable UAPSD in Wi-Fi firmware.
+ *
+ * \param[in] UAPsd_enable Enable/Disable UAPSD.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_set_wmm_uapsd(t_u8 UAPsd_enable);
+/** Set/get UAPSD sleep period in Wi-Fi firmware.
+ *
+ * \param[in] sleep_period UAPSD sleep period.
+ * \param[in] action Set/get action.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_sleep_period(unsigned int *sleep_period, t_u8 action);
+/** Check whether UAPSD is enabled or not.
+ *
+ * \return true if UAPSD is enabled.
+ * \return false if UAPSD is disabled.
+ */
+t_u8 wlan_is_wmm_uapsd_enabled(void);
+#endif
+
+#if CONFIG_WIFI_TX_BUFF
+/** Reconfigure Wi-Fi TX buffer size in Wi-Fi firmware.
+ *
+ * This function may be called to reconfigure Wi-Fi TX buffer size in firmware.
+ * This should be call before \ref wlan_init() function.
+ *
+ * \param[in] buf_size The new buffer size
+ *
+ * \param[in] bss_type 0: STA, 1: UAP
+ *
+ */
+void wlan_recfg_tx_buf_size(uint16_t buf_size, mlan_bss_type bss_type);
+#endif
+
+#if CONFIG_WIFI_TX_PER_TRACK
+/** Set TX per tracking config.
+ * This function may be called to set TX per tracking in firmware.
+ *
+ * \param[in] tx_pert User configured parameters of TX per tracking
+ *            period, ratio and number of TX packets.
+ *
+ * \param[in] bss_type BSS type for STA or UAP.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+void wlan_set_tx_pert(struct wlan_tx_pert_info *tx_pert, mlan_bss_type bss_type);
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+/** Set TX RX histogram config.
+ * This function may be called to set TX RX histogram config.
+ *
+ * \param[in] txrx_histogram User configured parameters of TX RX histogram.
+ *            including enable and action.
+ * \param[out] data TX RX histogram data from FW.
+ */
+void wlan_set_txrx_histogram(struct wlan_txrx_histogram_info *txrx_histogram, t_u8 *data);
+#endif
+
+#if CONFIG_ROAMING
+/** Set soft roaming config.
+ *
+ * This function may be called to enable/disable soft roaming
+ * by specifying the RSSI threshold.
+ *
+ * \note <b>RSSI Threshold setting for soft roaming</b>:
+ * The provided RSSI low threshold value is used to subscribe
+ * RSSI low event from firmware, on reception of this event
+ * background scan is started in firmware with same RSSI
+ * threshold to find out APs with better signal strength than
+ * RSSI threshold.
+ *
+ * If AP is found then roam attempt is initiated, otherwise
+ * background scan started again till limit reaches to
+ * BG_SCAN_LIMIT.
+ *
+ * If still AP is not found then Wi-Fi connection manager sends
+ * \ref WLAN_REASON_BGSCAN_NETWORK_NOT_FOUND event to
+ * application. In this case,
+ * if application again wants to use soft roaming then it
+ * can call this API again or use
+ * \ref wlan_set_rssi_low_threshold API to set RSSI low
+ * threshold again.
+ *
+ * \param[in] enable Enable/Disable roaming.
+ * \param[in] rssi_low_threshold RSSI low threshold value
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_set_roaming(const int enable, const uint8_t rssi_low_threshold);
+
+/** Get roaming status.
+ *
+ * \return 1 if roaming is enabled.
+ * \return 0 if roaming is disbled.
+ */
+int wlan_get_roaming_status(void);
+#endif
+
+#if CONFIG_HOST_SLEEP
+#ifdef RW610
+/** Wowlan (wake on wireless LAN) configure.
+ * This function may be called to config host sleep in firmware.
+ *
+ * \param[in] is_mef Flag to indicate use MEF (memory efficient filtering) condition or not.
+ * \param[in] wake_up_conds Bit map of default condition.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_wowlan_config(uint8_t is_mef, t_u32 wake_up_conds);
+
+/** Host sleep configure.
+ * This function may be called to config host sleep in firmware.
+ *
+ * \param[in] is_manual Flag to indicate host enter low power mode with power manager or by command.
+ * \param[in] is_periodic Flag to indicate host enter low power periodically or once with power manager.
+ */
+void wlan_config_host_sleep(bool is_manual, t_u8 is_periodic);
+
+/** This function sent host sleep events to mon_thread
+ * \param[in] id Event ID.
+ * \param[in] data Pointer to event msg.
+ * \return kStatus_Success if successful else return -WM_FAIL.
+ */
+status_t wlan_hs_send_event(int id, void *data);
+#endif /*RW610*/
+
+/** Cancel host sleep.
+ * This function may be called to cancel host sleep in firmware.
+ */
+void wlan_cancel_host_sleep(void);
+
+/** Clear host sleep configurations in driver.
+ * This function clears all the host sleep related configures in driver.
+ */
+void wlan_clear_host_sleep_config(void);
+
+/** This function set multicast MEF (memory efficient filtering) entry
+ *
+ * \param[in] mef_action To be 0--discard and not wake host, 1--discard and wake host 3--allow and wake host.
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_set_multicast(t_u8 mef_action);
+#endif
+
+/** Set configuration parameters of IEEE power save mode.
+ *
+ * \param [in] ps_cfg Power save configuratiuon includes multiple parameters.
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_set_ieeeps_cfg(struct wlan_ieeeps_config *ps_cfg);
+
+/** Configure listen interval of IEEE power save mode.
+ *
+ * \note <b>Delivery traffic indication message (DTIM)</b>:
+ * It is a concept in 802.11
+ * It is a time duration after which AP can send out buffered
+ * BROADCAST / MULTICAST data and stations connected to the AP
+ * should wakeup to take this broadcast / multicast data.
+
+ * \note <b>Traffic Indication Map (TIM)</b>:
+ * It is a bitmap which the AP sends with each beacon.
+ * The bitmap has one bit each for a station connected to AP.
+ *
+ * \note Each station is recognized by an association ID (AID).
+ * If AID is say 1 bit number 1 is set in the bitmap if
+ * unicast data is present with AP in its buffer for station with AID = 1
+ * Ideally AP does not buffer any unicast data it just sends
+ * unicast data to the station on every beacon when station
+ * is not sleeping.\n
+ * When broadcast data / multicast data is to be send AP sets bit 0
+ * of TIM indicating broadcast / multicast.\n
+ * The occurrence of DTIM is defined by AP.\n
+ * Each beacon has a number indicating period at which DTIM occurs.\n
+ * The number is expressed in terms of number of beacons.\n
+ * This period is called DTIM Period / DTIM interval.\n
+ * For example:\n
+ *     If AP has DTIM period = 3 the stations connected to AP
+ *     have to wake up (if they are sleeping) to receive
+ *     broadcast /multicast data on every third beacon.\n
+ * Generic:\n
+ *     When DTIM period is X
+ *     AP buffers broadcast data / multicast data for X beacons.
+ *     Then it transmits the data no matter whether station is awake or not.\n
+ * Listen interval:\n
+ * This is time interval on station side which indicates when station
+ * can be awake to listen i.e. accept data.\n
+ * Long listen interval:\n
+ * It comes into picture when station sleeps (IEEEPS) and it does
+ * not want to wake up on every DTIM
+ * So station is not worried about broadcast data/multicast data
+ * in this case.\n
+ * This should be a design decision what should be chosen
+ * Firmware suggests values which are about 3 times DTIM
+ * at the max to gain optimal usage and reliability.\n
+ * In the IEEEPS power save mode, the Wi-Fi firmware goes to sleep and
+ * periodically wakes up to check if the AP has any pending packets for it. A
+ * longer listen interval implies that the Wi-Fi card stays in power save for a
+ * longer duration at the cost of additional delays while receiving data.
+ * Note that choosing incorrect value for listen interval
+ * causes poor response from device during data transfer.
+ * Actual listen interval selected by firmware is equal to closest DTIM.\n
+ * For e.g.:-\n
+ *            AP beacon period : 100 ms\n
+ *            AP DTIM period : 2\n
+ *            Application request value: 500ms\n
+ *            Actual listen interval = 400ms (This is the closest DTIM).
+ * Actual listen interval set should be a multiple of DTIM closest to but
+ * lower than the value provided by the application.\n
+ *
+ *  \note This API can be called before/after association.
+ *  The configured listen interval can be used in subsequent association
+ *  attempt.
+ *
+ *  \param [in]  listen_interval Listen interval as below\n
+ *               0 : Unchanged,\n
+ *              -1 : Disable,\n
+ *             1-49: Value in beacon intervals,\n
+ *            >= 50: Value in TUs\n
+ */
+void wlan_configure_listen_interval(int listen_interval);
+
+/** Set timeout configuration before Wi-Fi power save mode.
+ *
+ * \param [in] timeout_ms timout time, in milliseconds.
+ *
+ */
+void wlan_configure_delay_to_ps(unsigned int timeout_ms);
+
+/** Get listen interval .
+ *
+ * \return listen interval value.
+ *
+ */
+unsigned short wlan_get_listen_interval(void);
+
+/** Get delay time for Wi-Fi power save mode.
+ *
+ * \return delay time value.
+ *
+ */
+unsigned int wlan_get_delay_to_ps(void);
+
+/** Check whether Wi-Fi power save is enabled.
+ *
+ * \return TRUE if Wi-Fi power save is enable, else return FALSE.
+ *
+ */
+bool wlan_is_power_save_enabled(void);
+
+/** Configure NULL packet interval of IEEE power save mode.
+ *
+ *  \note In IEEE PS (power save) station sends a NULL packet to AP to indicate that
+ *  the station is alive and AP should not kick it off.
+ *  If null packet is not send some APs may disconnect station
+ *  which might lead to a loss of connectivity.
+ *  The time is specified in seconds.
+ *  Default value is 30 seconds.
+ *
+ *  \note This API should be called before configuring IEEE Power save.
+ *
+ *  \param [in] time_in_secs : -1 Disables null packet transmission,
+ *                              0  Null packet interval is unchanged,
+ *                              n  Null packet interval in seconds.
+ */
+void wlan_configure_null_pkt_interval(int time_in_secs);
+
+#ifndef RW610
+/** This API can be used to set the mode of TX/RX antenna.
+ * If SAD (slow antenna diversity) is enabled, this API can also used to set SAD antenna
+ * evaluate time interval(antenna mode is antenna diversity
+ * when set SAD evaluate time interval).
+ *
+ * \param[in] ant Antenna valid values are 1, 2 and 65535
+ *                1 : TX/RX antenna 1
+ *                2 : TX/RX antenna 2
+ *	          0xFFFF: TX/RX antenna diversity
+ * \param[in] evaluate_time
+ *	      SAD (slow antenna diversity) evaluate time interval, default value is 6s(0x1770).
+ *
+ * \return WM_SUCCESS if successful.
+ * \return WLAN_ERROR_STATE if unsuccessful.
+ *
+ */
+int wlan_set_antcfg(uint32_t ant, uint16_t evaluate_time);
+
+/** This API can be used to get the mode of TX/RX antenna.
+ * If SAD (slow antenna diversity) is enabled, this API can also used to get SAD antenna
+ * evaluate time interval(antenna mode is antenna diversity
+ * when set SAD evaluate time interval).
+ *
+ * \param[out] ant pointer to antenna variable.
+ * \param[out] evaluate_time pointer to evaluate_time variable for SAD.
+ * \param[out] current_antenna pointer to current antenna.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return WLAN_ERROR_STATE if unsuccessful.
+ */
+int wlan_get_antcfg(uint32_t *ant, uint16_t *evaluate_time, uint16_t *current_antenna);
+#else
+/** This API can be used to set the mode of TX/RX antenna.
+ * If SAD is enabled, this API can also used to set SAD antenna
+ * evaluate time interval(antenna mode is antenna diversity
+ * when set SAD evaluate time interval).
+ *
+ * \param[in] ant Antenna valid values are 1, 2 and 65535
+ *                1 : TX/RX antenna 1
+ *                2 : TX/RX antenna 2
+ *	          0xFFFF: TX/RX antenna diversity
+ * \param[in] evaluate_time
+ *	      SAD evaluate time interval, default value is 6s(0x1770).
+ *  \param[in] evaluate_mode
+ *	            0: PCB Ant  + Ext Ant0
+ *              1: Ext Ant0 + Ext Ant1
+ *              2: PCB Ant  + Ext Ant1
+ *           0xFF: Default divisity mode.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return WLAN_ERROR_STATE if unsuccessful.
+ *
+ */
+int wlan_set_antcfg(uint32_t ant, uint16_t evaluate_time, uint8_t evaluate_mode);
+
+/** This API can be used to get the mode of TX/RX antenna.
+ * If SAD is enabled, this API can also used to get SAD antenna
+ * evaluate time interval(antenna mode is antenna diversity
+ * when set SAD evaluate time interval).
+ *
+ * \param[out] ant pointer to antenna variable.
+ * \param[out] evaluate_time pointer to evaluate_time variable for SAD.
+ * \param[out] current_mode pointer to evaluate_mode.
+ * \param[out] current_antenna pointer to current antenna.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return WLAN_ERROR_STATE if unsuccessful.
+ */
+int wlan_get_antcfg(uint32_t *ant, uint16_t *evaluate_time, uint8_t *evaluate_mode, uint16_t *current_antenna);
+#endif /*RW610*/
+
+/** Get the Wi-Fi firmware version extension string.
+ *
+ * \note This API does not allocate memory for pointer.
+ *       It just returns pointer of WLCMGR internal static
+ *       buffer. So no need to free the pointer by caller.
+ *
+ * \return Wi-Fi firmware version extension string pointer stored in
+ *         WLCMGR
+ */
+char *wlan_get_firmware_version_ext(void);
+
+/** Use this API to print Wi-Fi driver and firmware extended version.
+ */
+void wlan_version_extended(void);
+
+/**
+ * Use this API to get the TSF (timing synchronization function) from Wi-Fi firmware.
+ *
+ * \param[in] tsf_high Pointer to store TSF higher 32bits.
+ * \param[in] tsf_low Pointer to store TSF lower 32bits.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ *
+ */
+int wlan_get_tsf(uint32_t *tsf_high, uint32_t *tsf_low);
+
+/** Enable IEEE power save with host sleep configuration
+ *
+ * When enabled, it opportunistically puts the Wi-Fi card into IEEE power save mode.
+ * Before putting the Wi-Fi card in power
+ * save this also sets the hostsleep configuration on the card as
+ * specified. This makes the card generate a wakeup for the processor if
+ * any of the wakeup conditions are met.
+ *
+ * \param[in] wakeup_conditions conditions to wake the host. This should
+ *            be a logical OR of the conditions in \ref wlan_wakeup_event_t.
+ *            Typically devices would want to wake up on
+ *            \ref WAKE_ON_ALL_BROADCAST,
+ *            \ref WAKE_ON_UNICAST,
+ *            \ref WAKE_ON_MAC_EVENT.
+ *            \ref WAKE_ON_MULTICAST,
+ *            \ref WAKE_ON_ARP_BROADCAST,
+ *            \ref WAKE_ON_MGMT_FRAME
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL otherwise.
+ *
+ */
+int wlan_ieeeps_on(unsigned int wakeup_conditions);
+
+/** Turn off IEEE power save mode.
+ *
+ * \note This call is asynchronous. The system exits the power save mode
+ *       only when all requisite conditions are met.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL otherwise.
+ *
+ */
+int wlan_ieeeps_off(void);
+
+#if !CONFIG_WPA_SUPP
+#if (CONFIG_WNM_PS)
+/** Enable WNM with host sleep configuration
+ *
+ * When enabled, it opportunistically puts the Wi-Fi card into IEEE PS (power save) mode.
+ * Before putting the Wi-Fi card in power
+ * save this also sets the hostsleep configuration on the card as
+ * specified. This makes the card generate a wakeup for the processor if
+ * any of the wakeup conditions are met.
+ *
+ * \param[in] wakeup_conditions conditions to wake the host. This should
+ *            be a logical OR of the conditions in \ref wlan_wakeup_event_t.
+ *            Typically devices would want to wake up on
+ *            \ref WAKE_ON_ALL_BROADCAST,
+ *            \ref WAKE_ON_UNICAST,
+ *            \ref WAKE_ON_MAC_EVENT.
+ *            \ref WAKE_ON_MULTICAST,
+ *            \ref WAKE_ON_ARP_BROADCAST,
+ *            \ref WAKE_ON_MGMT_FRAME
+ * \param[in] wnm_sleep_time wnm sleep interval.(number of dtims)
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL otherwise.
+ *
+ */
+int wlan_wnmps_on(unsigned int wakeup_conditions, t_u16 wnm_sleep_time);
+
+/** Turn off WNM power save mode.
+ *
+ * \note This call is asynchronous. The system exits the power save mode
+ *       only when all requisite conditions are met.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL otherwise.
+ *
+ */
+int wlan_wnmps_off(void);
+#endif
+#endif
+
+/** Turn on deep sleep power save mode.
+ *
+ * \note This call is asynchronous. The system enters the power save mode
+ * only when all requisite conditions are meet. For example, Wi-Fi should be
+ * disconnected for this to work.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL otherwise.
+ *
+ */
+int wlan_deepsleepps_on(void);
+
+/** Turn off deep sleep power save mode.
+ *
+ * \note This call is asynchronous. The system exits the power save mode
+ *       only when all requisite conditions are met.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL otherwise.
+ *
+ */
+int wlan_deepsleepps_off(void);
+
+/**
+ * Use this API to configure the TCP keep alive parameters in Wi-Fi firmware.
+ * \ref wlan_tcp_keep_alive_t provides the parameters which are available
+ * for configuration.
+ *
+ * \note To reset current TCP keep alive configuration just pass the reset with
+ * value 1, all other parameters are ignored in this case.
+ *
+ * \note Note that this API is called after successful connection
+ * and before putting Wi-Fi card in IEEE power save mode.
+ *
+ * \param[in] keep_alive A pointer to \ref wlan_tcp_keep_alive_t
+ * 		with following parameters.
+ * 	         enable Enable keep alive
+ *               reset  Reset keep alive
+ *   	         timeout Keep alive timeout
+ *   	         interval Keep alive interval
+ *               max_keep_alives Maximum keep alives
+ *   		 dst_mac Destination MAC address
+ *   		 dst_ip Destination IP
+ *   		 dst_tcp_port Destination TCP port
+ *   		 src_tcp_port Source TCP port
+ *   		 seq_no Sequence number
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_tcp_keep_alive(wlan_tcp_keep_alive_t *keep_alive);
+
+
+/**
+ * Use this API to get the beacon period of associated BSS.
+ *
+ * \return beacon_period if operation is successful.
+ * \return 0 if command fails.
+ */
+uint16_t wlan_get_beacon_period(void);
+
+/**
+ * Use this API to get the dtim period of associated BSS.
+ *
+ * \return dtim_period if operation is successful.
+ * \return 0 if DTIM IE Is not found in AP's Probe response.
+ * \note This API should not be called from Wi-Fi event handler
+ *        registered by application during \ref wlan_start.
+ */
+uint8_t wlan_get_dtim_period(void);
+
+/**
+ * Use this API to get the current TX and RX rates along with
+ * bandwidth and guard interval information if rate is 802.11n.
+ *
+ * \param[in] ds_rate A pointer to structure which has
+ *            tx, RX rate information along with bandwidth and guard
+ *	      interval information.
+ *
+ * \param[in] bss_type 0: STA, 1: UAP
+ *
+ * \note If rate is greater than 11 then it is 802.11n rate and from 12
+ *       MCS0 rate starts. The bandwidth mapping is like value 0 is for
+ *	 20MHz, 1 is 40MHz, 2 is for 80MHz.
+ *	 The guard interval value zero means Long otherwise Short.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_get_data_rate(wlan_ds_rate *ds_rate, mlan_bss_type bss_type);
+
+/**
+ * Use this API to get the set management frame protection parameters for sta.
+ *
+ * \param[out] mfpc: Management frame protection capable (MFPC)
+ *                       1: Management frame protection capable
+ *                       0: Management frame protection not capable
+ * \param[out] mfpr: Management frame protection required (MFPR)
+ *                       1: Management frame protection required
+ *                       0: Management frame protection optional
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_get_pmfcfg(uint8_t *mfpc, uint8_t *mfpr);
+
+/**
+ * Use this API to get the set management frame protection parameters for UAP.
+ *
+ * \param[out] mfpc: Management frame protection capable (MFPC)
+ *                       1: management frame protection capable.
+ *                       0: management frame protection not capable.
+ * \param[out] mfpr: Management frame protection required (MFPR)
+ *                       1: management frame protection required.
+ *                       0: management frame protection optional.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_uap_get_pmfcfg(uint8_t *mfpc, uint8_t *mfpr);
+
+
+/**
+ * Use this API to set packet filters in Wi-Fi firmware.
+ *
+ * \param[in] flt_cfg A pointer to structure which holds the
+ *	      the packet filters in same way as given below.\n
+ *
+ * MEF Configuration command\n
+ * mefcfg={\n
+ * Criteria: bit0-broadcast, bit1-unicast, bit3-multicast\n
+ * Criteria=2 		Unicast frames are received during hostsleepmode\n
+ * NumEntries=1		Number of activated MEF entries\n
+ * mef_entry_0: example filters to match TCP destination port 80 send by 192.168.0.88 pkt or magic pkt.\n
+ * mef_entry_0={\n
+ *  mode: bit0--hostsleep mode, bit1--non hostsleep mode\n
+ *  mode=1		HostSleep mode\n
+ *  action: 0--discard and not wake host, 1--discard and wake host 3--allow and wake host\n
+ *  action=3	Allow and Wake host\n
+ *  filter_num=3    Number of filter\n
+ *   RPN only support "&&" and "||" operator,space can not be removed between operator.\n
+ *   RPN=Filter_0 && Filter_1 || Filter_2\n
+ *   Byte comparison filter's type is 0x41,Decimal comparison filter's type is 0x42,\n
+ *   Bit comparison filter's type is  0x43\n
+ *  Filter_0 is decimal comparison filter, it always with type=0x42\n
+ *  Decimal filter always has type, pattern, offset, numbyte 4 field\n
+ *  Filter_0 matchs RX packet with TCP destination port 80\n
+ *  Filter_0={\n
+ *    type=0x42	      decimal comparison filter\n
+ *    pattern=80      80 is the decimal constant to be compared\n
+ *    offset=44	      44 is the byte offset of the field in RX pkt to be compare\n
+ *    numbyte=2       2 is the number of bytes of the field\n
+ *  }\n
+ *  Filter_1 is Byte comparison filter, it always with type=0x41\n
+ *  Byte filter always has type, byte, repeat, offset 4 filed\n
+ *  Filter_1 matchs RX packet send by IP address 192.168.0.88\n
+ *  Filter_1={\n
+ *   type=0x41         Byte comparison filter\n
+ *   repeat=1          1 copies of 'c0:a8:00:58'\n
+ *   byte=c0:a8:00:58  'c0:a8:00:58' is the byte sequence constant with each byte\n
+ *   in hex format, with ':' as delimiter between two byte.\n
+ *   offset=34         34 is the byte offset of the equal length field of rx'd pkt.\n
+ *  }\n
+ *  Filter_2 is Magic packet, it can looking for 16 contiguous copies of '00:50:43:20:01:02' from\n
+ *  the RX pkt's offset 14\n
+ *  Filter_2={\n
+ *   type=0x41	       Byte comparison filter\n
+ *   repeat=16         16 copies of '00:50:43:20:01:02'\n
+ *   byte=00:50:43:20:01:02  # '00:50:43:20:01:02' is the byte sequence constant\n
+ *   offset=14	       14 is the byte offset of the equal length field of rx'd pkt.\n
+ *  }\n
+ * }\n
+ * }\n
+ * Above filters can be set by filling values in following way in \ref wlan_flt_cfg_t structure.\n
+ * wlan_flt_cfg_t flt_cfg;\n
+ * uint8_t byte_seq1[] = {0xc0, 0xa8, 0x00, 0x58};\n
+ * uint8_t byte_seq2[] = {0x00, 0x50, 0x43, 0x20, 0x01, 0x02};\n
+ *\n
+ * memset(&flt_cfg, 0, sizeof(wlan_flt_cfg_t));\n
+ *\n
+ * flt_cfg.criteria = 2;\n
+ * flt_cfg.nentries = 1;\n
+ *\n
+ * flt_cfg.mef_entry.mode = 1;\n
+ * flt_cfg.mef_entry.action = 3;\n
+ *\n
+ * flt_cfg.mef_entry.filter_num = 3;\n
+ *\n
+ * flt_cfg.mef_entry.filter_item[0].type = TYPE_DNUM_EQ;\n
+ * flt_cfg.mef_entry.filter_item[0].pattern = 80;\n
+ * flt_cfg.mef_entry.filter_item[0].offset = 44;\n
+ * flt_cfg.mef_entry.filter_item[0].num_bytes = 2;\n
+ *\n
+ * flt_cfg.mef_entry.filter_item[1].type = TYPE_BYTE_EQ;\n
+ * flt_cfg.mef_entry.filter_item[1].repeat = 1;\n
+ * flt_cfg.mef_entry.filter_item[1].offset = 34;\n
+ * flt_cfg.mef_entry.filter_item[1].num_byte_seq = 4;\n
+ * memcpy(flt_cfg.mef_entry.filter_item[1].byte_seq, byte_seq1, 4);\n
+ * flt_cfg.mef_entry.rpn[1] = RPN_TYPE_AND;\n
+ *\n
+ * flt_cfg.mef_entry.filter_item[2].type = TYPE_BYTE_EQ;\n
+ * flt_cfg.mef_entry.filter_item[2].repeat = 16;\n
+ * flt_cfg.mef_entry.filter_item[2].offset = 14;\n
+ * flt_cfg.mef_entry.filter_item[2].num_byte_seq = 6;\n
+ * memcpy(flt_cfg.mef_entry.filter_item[2].byte_seq, byte_seq2, 6);\n
+ * flt_cfg.mef_entry.rpn[2] = RPN_TYPE_OR;\n
+ *
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_set_packet_filters(wlan_flt_cfg_t *flt_cfg);
+
+/**
+ * Use this API to enable ARP (address resolution protocol) offload in Wi-Fi firmware
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_set_auto_arp(void);
+
+
+/**
+ * Use this API to enable WOWLAN (wake-on-wireless-LAN) on magic packet RX in Wi-Fi firmware
+ *
+ * \param[in] ptn_cfg A pointer to \ref wlan_wowlan_ptn_cfg_t containing wake on Wi-Fi pattern configuration
+ *
+ *\return WM_SUCCESS if operation is successful.
+ *\return -WM_FAIL if command fails
+ */
+int wlan_wowlan_cfg_ptn_match(wlan_wowlan_ptn_cfg_t *ptn_cfg);
+/**
+ * Use this API to enable NS offload in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_set_ipv6_ns_offload(void);
+
+#if CONFIG_HOST_SLEEP
+
+/** WLCMGR host sleep pre configuration */
+void wlan_hs_pre_cfg(void);
+
+/** WLCMGR host sleep post configuration */
+void wlan_hs_post_cfg(void);
+
+/**
+ * Use this API to configure host sleep params in Wi-Fi firmware.
+ *
+ * \param[in] wakeup_condition  bit 0: WAKE_ON_ALL_BROADCAST
+ *                              bit 1: WAKE_ON_UNICAST
+ *                              bit 2: WAKE_ON_MAC_EVENT
+ *                              bit 3: WAKE_ON_MULTICAST
+ *                              bit 4: WAKE_ON_ARP_BROADCAST
+ *                              bit 6: WAKE_ON_MGMT_FRAME
+ *                              All bit 0 discard and not wakeup host
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_send_host_sleep(uint32_t wakeup_condition);
+
+/**
+ * Use this API to get host sleep wakeup reason from Wi-Fi firmware.
+ *
+ * \param[out] hs_wakeup_reason wakeupReason:
+ *                              0: unknown
+ *                              1: Broadcast data matched
+ *                              2: Multicast data matched
+ *                              3: Unicast data matched
+ *                              4: Maskable event matched
+ *                              5. Non-maskable event matched
+ *                              6: Non-maskable condition matched (EAPoL rekey)
+ *                              7: Magic pattern matched
+ *                              Others: reserved. (set to 0)
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_get_wakeup_reason(uint16_t *hs_wakeup_reason);
+#endif
+
+/**
+ * Use this API to get the BSSID of associated BSS.
+ *
+ * \param[in] bssid A pointer to array to store the BSSID.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_get_current_bssid(uint8_t *bssid);
+
+/**
+ * Use this API to get the channel number of associated BSS.
+ *
+ * \return channel number if operation is successful.
+ * \return 0 if command fails.
+ */
+uint8_t wlan_get_current_channel(void);
+
+#if CONFIG_WIFI_GET_LOG
+/**
+ * Use this API to get the various statistics of STA from Wi-Fi firmware like
+ * number of beacons received, missed and so on.
+ *
+ * \param[in] stats A pointer to structure where stats collected from Wi-Fi firmware
+ *	      can be copied.
+ * \note Explore the elements of the \ref wlan_pkt_stats_t strucutre for
+ * 	 more information on stats.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_get_log(wlan_pkt_stats_t *stats);
+
+/**
+ * Use this API to get the various statistics of UAP from Wi-Fi firmware like
+ * number of beacons received, missed and so on.
+ *
+ * \param[in] stats A pointer to structure where stats collected from Wi-Fi firmware
+ *	      can be copied.
+ * \note  explore the elements of the \ref wlan_pkt_stats_t strucutre for
+ * 	 more information on stats.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_uap_get_log(wlan_pkt_stats_t *stats);
+#endif
+
+/** Get station interface power save mode.
+ *
+ * \param[out] ps_mode A pointer to \ref wlan_ps_mode where station interface
+ * 	      power save mode should be stored.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_INVAL if \a ps_mode was NULL.
+ */
+int wlan_get_ps_mode(enum wlan_ps_mode *ps_mode);
+
+/** Send message to Wi-Fi connection manager thread.
+ *
+ * \param[in] event An event from \ref wifi_event.
+ * \param[in] reason A reason code.
+ * \param[in] data A pointer to data buffer associated with event.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_wlcmgr_send_msg(enum wifi_event event, enum wifi_event_reason reason, void *data);
+
+/** Register WFA basic Wi-Fi CLI (command line input) commands
+ *
+ * This function registers basic Wi-Fi CLI commands like showing
+ * version information, MAC address.
+ *
+ * \note This function can only be called by the application after
+ * \ref wlan_init() called.
+ *
+ * \return WLAN_ERROR_NONE if the CLI commands were registered or
+ * \return WLAN_ERROR_ACTION if they were not registered (for example
+ *   if this function was called while the CLI commands were already
+ *   registered).
+ */
+int wlan_wfa_basic_cli_init(void);
+
+/** Unregister WFA basic Wi-Fi CLI (command line input) commands
+ *
+ * This function unregisters basic Wi-Fi CLI commands like showing
+ * version information, MAC address.
+ *
+ * \note This function can only be called by the application after
+ * \ref wlan_init() called.
+ *
+ * \return WLAN_ERROR_NONE if the CLI commands were unregistered or
+ * \return WLAN_ERROR_ACTION if they were not unregistered
+ */
+int wlan_wfa_basic_cli_deinit(void);
+
+/** Register basic Wi-Fi CLI (command line input) commands
+ *
+ * This function registers basic Wi-Fi CLI commands like showing
+ * version information, MAC address.
+ *
+ * \note This function can only be called by the application after
+ * \ref wlan_init() called.
+ *
+ * \note This function gets called by \ref wlan_cli_init(), hence
+ * only one function out of these two functions should be called in
+ * the application.
+ *
+ * \return WLAN_ERROR_NONE if the CLI commands were registered or
+ * \return WLAN_ERROR_ACTION if they were not registered (for example
+ *   if this function was called while the CLI commands were already
+ *   registered).
+ */
+int wlan_basic_cli_init(void);
+
+/** Unregister basic Wi-Fi CLI commands
+ *
+ * This function unregisters basic Wi-Fi CLI commands like showing
+ * version information, MAC address.
+ *
+ * \note This function can only be called by the application after
+ * \ref wlan_init() called.
+ *
+ * \note This function gets called by \ref wlan_cli_init(), hence
+ * only one function out of these two functions should be called in
+ * the application.
+ *
+ * \return WLAN_ERROR_NONE if the CLI commands were unregistered or
+ * \return WLAN_ERROR_ACTION if they were not unregistered (for example
+ *   if this function was called while the CLI commands were already
+ *   registered).
+ */
+int wlan_basic_cli_deinit(void);
+
+/** Register Wi-Fi CLI (command line input) commands.
+ *
+ *  Try to register the Wi-Fi CLI commands with the CLI subsystem. This
+ *  function is available for the application for use.
+ *
+ *  \note This function can only be called by the application after \ref wlan_init()
+ *  called.
+ *
+ *  \note This function internally calls \ref wlan_basic_cli_init(), hence
+ *  only one function out of these two functions should be called in
+ *  the application.
+ *
+ *  \return WM_SUCCESS if the CLI commands were registered or
+ *  \return -WM_FAIL if they were not (for example if this function
+ *          was called while the CLI commands were already registered).
+ */
+int wlan_cli_init(void);
+
+/** Unregister Wi-Fi CLI commands.
+ *
+ *  Try to unregister the Wi-Fi CLI commands with the CLI subsystem. This
+ *  function is available for the application for use.
+ *
+ *  \note This function can only be called by the application after \ref wlan_init()
+ *  called.
+ *
+ *  \note This function internally calls \ref wlan_basic_cli_deinit(), hence
+ *  only one function out of these two functions should be called in
+ *  the application.
+ *
+ *  \return WM_SUCCESS if the CLI commands were unregistered or
+ *  \return -WM_FAIL if they were not (for example if this function
+ *          was called while the CLI commands were already unregistered).
+ */
+int wlan_cli_deinit(void);
+
+/** Register Wi-Fi enhanced CLI commands.
+ *
+ *  Register the Wi-Fi enhanced CLI commands like set or get tx-power,
+ *  tx-datarate, tx-modulation etc with the CLI subsystem.
+ *
+ *  \note This function can only be called by the application after \ref wlan_init()
+ *  called.
+ *
+ *  \return WM_SUCCESS if the CLI commands were registered or
+ *  \return -WM_FAIL if they were not (for example if this function
+ *           was called while the CLI commands were already registered).
+ */
+int wlan_enhanced_cli_init(void);
+
+/** Unregister Wi-Fi enhanced CLI commands.
+ *
+ *  Unregister the Wi-Fi enhanced CLI commands like set or get tx-power,
+ *  tx-datarate, tx-modulation etc with the CLI subsystem.
+ *
+ *  \note This function can only be called by the application after \ref wlan_init()
+ *  called.
+ *
+ *  \return WM_SUCCESS if the CLI commands were unregistered or
+ *  \return -WM_FAIL if they were not unregistered.
+ */
+
+int wlan_enhanced_cli_deinit(void);
+
+#if CONFIG_RF_TEST_MODE
+/** Register Wi-Fi test mode CLI commands.
+ *
+ *  Register the Wi-Fi test mode CLI commands like set or get channel,
+ *  band, bandwidth, per and more with the CLI subsystem.
+ *
+ *  \note This function can only be called by the application after \ref wlan_init()
+ *  called.
+ *
+ *  \return WM_SUCCESS if the CLI commands were registered or
+ *  \return -WM_FAIL if they were not (for example if this function
+ *           was called while the CLI commands were already registered).
+ */
+int wlan_test_mode_cli_init(void);
+
+/** Unregister Wi-Fi test mode CLI commands.
+ *
+ *  Unregister the Wi-Fi test mode CLI commands like set or get channel,
+ *  band, bandwidth, PER and more with the CLI subsystem.
+ *
+ *  \note This function can only be called by the application after \ref wlan_init()
+ *  called.
+ *
+ *  \return WM_SUCCESS if the CLI commands were unregistered or
+ *  \return -WM_FAIL if they were not unregistered
+ */
+int wlan_test_mode_cli_deinit(void);
+#endif
+
+/**
+ * Get maximum number of Wi-Fi firmware supported stations that
+ * can be allowed to connect to the UAP.
+ *
+ * \return Maximum number of Wi-Fi firmware supported stations.
+ *
+ * \note Get operation is allowed in any UAP state.
+ */
+unsigned int wlan_get_uap_supported_max_clients(void);
+
+/**
+ * Get current maximum number of stations that
+ * can be allowed to connect to the UAP.
+ *
+ * \param[out] max_sta_num A pointer to variable where current maximum
+ *             number of stations of UAP interface can be stored.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ * \note Get operation is allowed in any UAP state.
+ */
+int wlan_get_uap_max_clients(unsigned int *max_sta_num);
+
+/**
+ * Set maximum number of stations that can be allowed to connect to the UAP.
+ *
+ * \param[in] max_sta_num Number of maximum stations for UAP.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ * \note Set operation in not allowed in \ref WLAN_UAP_STARTED state.
+ */
+int wlan_set_uap_max_clients(unsigned int max_sta_num);
+
+/**
+ * This API can be used to configure some of parameters in HT capability infomation IE
+ *       (such as short GI, channel bandwidth, and green field support)
+ *
+ * \param[in] htcapinfo This is a bitmap and should be used as following\n
+ *               Bit 29: Green field Enable/Disable\n
+ *               Bit 26: RX STBC Support Enable/Disable. (As we support\n
+ *                       single spatial stream only 1 bit is used for RX STBC)\n
+ *               Bit 25: TX STBC support Enable/Disable.\n
+ *               Bit 24: Short GI in 40 Mhz Enable/Disable\n
+ *               Bit 23: Short GI in 20 Mhz Enable/Disable\n
+ *               Bit 22: RX LDPC Enable/Disable\n
+ *               Bit 17: 20/40 Mhz enable disable.\n
+ *               Bit  8: Enable/Disable 40Mhz Intolarent bit in HT capinfo.\n
+ *                       0 can reset this bit and 1 can set this bit in\n
+ *                       htcapinfo attached in assoc request.\n
+ *               All others are reserved and should be set to 0.\n
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_set_htcapinfo(unsigned int htcapinfo);
+
+/**
+ * This API can be used to configure various 802.11n specific configuration
+ *       for transmit (such as short GI, channel bandwidth and green field support)
+ *
+ * \param[in] httxcfg This is a bitmap and should be used as following\n
+ *               Bit 15-10: Reserved set to 0\n
+ *               Bit 9-8: RX STBC set to 0x01\n
+ *               BIT9 BIT8  Description\n
+ *               0    0     No spatial streams\n
+ *               0    1     One spatial streams supported\n
+ *               1    0     Reserved\n
+ *               1    1     Reserved\n
+ *               Bit 7: STBC Enable/Disable\n
+ *               Bit 6: Short GI in 40 Mhz Enable/Disable\n
+ *               Bit 5: Short GI in 20 Mhz Enable/Disable\n
+ *               Bit 4: Green field Enable/Disable\n
+ *               Bit 3-2: Reserved set to 1\n
+ *               Bit 1: 20/40 Mhz enable disable.\n
+ *               Bit 0: LDPC Enable/Disable\n
+ *
+ *       When Bit 1 is set then firmware could transmit in 20Mhz or 40Mhz based\n
+ *       on rate adaptation. When this bit is reset then firmware can only\n
+ *       transmit in 20Mhz.\n
+ *
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_set_httxcfg(unsigned short httxcfg);
+
+/**
+ * This API can be used to set the transmit data rate.
+ *
+ * \note The data rate can be set only after association.
+ *
+ * \param[in] ds_rate struct contains following fields
+ *             sub_command It should be WIFI_DS_RATE_CFG
+ *             and rate_cfg should have following parameters.\n
+ *              rate_format - This parameter specifies
+ *                              the data rate format used
+ *                              in this command\n
+ *               0:    LG\n
+ *               1:    HT\n
+ *               2:    VHT\n
+ *               0xff: Auto\n
+ *
+ *              index - This parameter specifies the rate or MCS index\n
+ *              If  rate_format is 0 (LG),\n
+ *               0       1 Mbps\n
+ *               1       2 Mbps\n
+ *               2       5.5 Mbps\n
+ *               3       11 Mbps\n
+ *               4       6 Mbps\n
+ *               5       9 Mbps\n
+ *               6       12 Mbps\n
+ *               7       18 Mbps\n
+ *               8       24 Mbps\n
+ *               9       36 Mbps\n
+ *               10      48 Mbps\n
+ *               11      54 Mbps\n
+ *              If  rate_format is 1 (HT),\n
+ *               0       MCS0\n
+ *               1       MCS1\n
+ *               2       MCS2\n
+ *               3       MCS3\n
+ *               4       MCS4\n
+ *               5       MCS5\n
+ *               6       MCS6\n
+ *               7       MCS7\n
+ *	        If STREAM_2X2\n
+ *               8       MCS8\n
+ *               9       MCS9\n
+ *               10      MCS10\n
+ *               11      MCS11\n
+ *               12      MCS12\n
+ *               13      MCS13\n
+ *               14      MCS14\n
+ *               15      MCS15\n
+ *              If  rate_format is 2 (VHT),\n
+ *               0       MCS0\n
+ *               1       MCS1\n
+ *               2       MCS2\n
+ *               3       MCS3\n
+ *               4       MCS4\n
+ *               5       MCS5\n
+ *               6       MCS6\n
+ *               7       MCS7\n
+ *               8       MCS8\n
+ *               9       MCS9\n
+ *              nss - This parameter specifies the NSS.\n
+ *			It is valid only for VHT\n
+ *              If  rate_format is 2 (VHT),\n
+ *               1       NSS1\n
+ *               2       NSS2\n
+ *
+ * \param[in] bss_type 0: STA, 1: UAP
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_set_txratecfg(wlan_ds_rate ds_rate, mlan_bss_type bss_type);
+
+/**
+ * This API can be used to get the transmit data rate.
+ *
+ * \param[in] ds_rate A pointer to \ref wlan_ds_rate where TX Rate
+ * 		configuration can be stored.
+ * \param[in] bss_type 0: STA, 1: UAP
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_get_txratecfg(wlan_ds_rate *ds_rate, mlan_bss_type bss_type);
+
+/**
+ * Get station transmit power
+ *
+ * \param[out] power_level Transmit power level.
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_get_sta_tx_power(t_u32 *power_level);
+
+/**
+ * Set station transmit power
+ *
+ * \param[in] power_level Transmit power level.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_set_sta_tx_power(t_u32 power_level);
+
+/**
+ * Set world wide safe mode TX power limits
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_set_wwsm_txpwrlimit(void);
+
+#ifndef RW610
+/**
+ * Get Wi-Fi region code from TX power config
+ *
+ * \return Wi-Fi region code in string format.
+ *
+ */
+const char *wlan_get_wlan_region_code(void);
+#endif
+
+/**
+ * Get Management IE for given BSS type (interface) and index.
+ *
+ * \param[in] bss_type 0: STA, 1: UAP
+ * \param[in] index IE index.
+ *
+ * \param[out] buf Buffer to store requested IE data.
+ * \param[out] buf_len To store length of IE data.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_get_mgmt_ie(enum wlan_bss_type bss_type, IEEEtypes_ElementId_t index, void *buf, unsigned int *buf_len);
+
+/**
+ * Set management IE for given BSS type (interface) and index.
+ *
+ * \param[in] bss_type 0: STA, 1: UAP
+ * \param[in] id Type/ID of Management IE.
+ * \param[in] buf Buffer containing IE data.
+ * \param[in] buf_len Length of IE data.
+ *
+ * \return IE index if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_set_mgmt_ie(enum wlan_bss_type bss_type, IEEEtypes_ElementId_t id, void *buf, unsigned int buf_len);
+
+#ifdef SD8801
+/**
+ * Get external radio coex statistics.
+ *
+ * \param[out] ext_coex_stats A pointer to structure to get coex statistics.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_get_ext_coex_stats(wlan_ext_coex_stats_t *ext_coex_stats);
+
+/**
+ * Set external radio coex configuration.
+ *
+ * \param[in] ext_coex_config to apply coex configuration.
+ *
+ * \return IE index if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_set_ext_coex_config(const wlan_ext_coex_config_t ext_coex_config);
+#endif
+
+/**
+ * Clear management IE for given BSS type (interface) and index.
+ *
+ * \param[in] bss_type 0: STA, 1: UAP
+ * \param[in] index IE index.
+ * \param[in] mgmt_bitmap_index management bitmap index.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_FAIL if unsuccessful.
+ *
+ */
+int wlan_clear_mgmt_ie(enum wlan_bss_type bss_type, IEEEtypes_ElementId_t index, int mgmt_bitmap_index);
+
+/**
+ * Get current status of 802.11d support.
+ *
+ * \return true if 802.11d support is enabled by application.
+ * \return false if not enabled.
+ *
+ */
+bool wlan_get_11d_enable_status(void);
+
+/**
+ * Get current RSSI and signal to noise ratio from Wi-Fi firmware.
+ *
+ * \param[in] RSSI A pointer to variable to store current RSSI
+ * \param[in] snr A pointer to variable to store current SNR.
+ *
+ * \return WM_SUCCESS if successful.
+ */
+int wlan_get_current_signal_strength(short *rssi, int *snr);
+
+/**
+ * Get average RSSI and signal to noise ratio from Wi-Fi firmware.
+ *
+ * \param[in] RSSI A pointer to variable to store current RSSI
+ * \param[in] snr A pointer to variable to store current SNR.
+ *
+ * \return WM_SUCCESS if successful.
+ */
+int wlan_get_average_signal_strength(short *rssi, int *snr);
+
+/**
+ * This API is used to set/cancel the remain on channel configuration.
+ *
+ * \note When status is false, channel and duration parameters are
+ * ignored.
+ *
+ * \param[in] bss_type The interface to set channel  bss_type 0: STA, 1: UAP
+ * \param[in] status false : Cancel the remain on channel configuration
+ *                   true : Set the remain on channel configuration
+ * \param[in] channel The channel to configure
+ * \param[in] duration The duration for which to
+ *	      remain on channel in milliseconds.
+ *
+ * \return WM_SUCCESS on success or error code.
+ *
+ */
+int wlan_remain_on_channel(const enum wlan_bss_type bss_type,
+                           const bool status,
+                           const uint8_t channel,
+                           const uint32_t duration);
+
+/**
+ * Get user data from OTP (one-time pramming) memory
+ *
+ * \param[in] buf Pointer to buffer where data should be stored
+ * \param[in] len Number of bytes to read
+ *
+ * \return WM_SUCCESS if user data read operation is successful.
+ * \return -WM_E_INVAL if buf is not valid or of insufficient size.
+ * \return -WM_FAIL if user data field is not present or command fails.
+ */
+int wlan_get_otp_user_data(uint8_t *buf, uint16_t len);
+
+/**
+ * Get calibration data from Wi-Fi firmware.
+ *
+ * \param[out] cal_data Pointer to calibration data structure where
+ *	      calibration data and it's length should be stored.
+ *
+ * \return WM_SUCCESS if calibration data read operation is successful.
+ * \return -WM_E_INVAL if cal_data is not valid.
+ * \return -WM_FAIL if command fails.
+ *
+ * \note The user of this API should free the allocated buffer for
+ *	 calibration data.
+ */
+int wlan_get_cal_data(wlan_cal_data_t *cal_data);
+
+#if CONFIG_COMPRESS_TX_PWTBL
+/**
+ * Set the compressed TX power limit configuration.
+ *
+ * \param[in] data A pointer to TX power limit configuration.
+ * \param[in] len Length of TX power limit configuration.
+ *
+ * \return WM_SUCCESS on success, error otherwise.
+ *
+ */
+int wlan_set_region_power_cfg(const t_u8 *data, t_u16 len);
+#endif
+
+/**
+ * Set the TRPC (transient receptor potential canonical) channel list and TX power limit configuration.
+ *
+ * \param[in] chanlist A poiner to \ref wlan_chanlist_t channel List configuration.
+ * \param[in] txpwrlimit A pointer to \ref wlan_txpwrlimit_t TX power limit configuration.
+ *
+ * \return WM_SUCCESS on success, error otherwise.
+ *
+ */
+int wlan_set_chanlist_and_txpwrlimit(wlan_chanlist_t *chanlist, wlan_txpwrlimit_t *txpwrlimit);
+
+/**
+ * Set the channel list configuration.
+ *
+ * \param[in] chanlist A pointer to wlan_chanlist_t channel list configuration.
+ *
+ * \return WM_SUCCESS on success, error otherwise.
+ *
+ * \note If region enforcement flag is enabled in the OTP then this API should
+ * not take effect.
+ */
+int wlan_set_chanlist(wlan_chanlist_t *chanlist);
+
+/**
+ * Get the channel list configuration.
+ *
+ * \param[out] chanlist A pointer to wlan_chanlist_t channel list configuration.
+ *
+ * \return WM_SUCCESS on success, error otherwise.
+ *
+ * \note The \ref wlan_chanlist_t struct allocates memory for a maximum of 54.
+ * channels.
+ *
+ */
+int wlan_get_chanlist(wlan_chanlist_t *chanlist);
+
+/**
+ * Set the TRPC (transient receptor potential canonical) channel configuration.
+ *
+ * \param[in] txpwrlimit A pointer to \ref wlan_txpwrlimit_t TX power limit configuration.
+ *
+ * \return WM_SUCCESS on success, error otherwise.
+ *
+ */
+int wlan_set_txpwrlimit(wlan_txpwrlimit_t *txpwrlimit);
+
+/**
+ * Get the TRPC (transient receptor potential canonical) channel configuration.
+ *
+ * \param[in] subband  Where subband is:\n
+ *              0x00 2G subband  (2.4G: channel 1-14)\n
+ *              0x10 5G subband0 (5G: channel 36,40,44,48,\n
+ *                                            52,56,60,64)\n
+ *              0x11 5G subband1 (5G: channel 100,104,108,112,\n
+ *                                            116,120,124,128,\n
+ *                                            132,136,140,144)\n
+ *              0x12 5G subband2 (5G: channel 149,153,157,161,165,172)\n
+ *              0x13 5G subband3 (5G: channel 183,184,185,187,188,\n
+ *                                            189, 192,196;\n
+ *                                5G: channel 7,8,11,12,16,34)\n
+ *
+ * \param[out] txpwrlimit A pointer to \ref wlan_txpwrlimit_t TX power
+ * 		Limit configuration structure where Wi-Fi firmware
+ * 		configuration can get copied.
+ *
+ * \return WM_SUCCESS on success, error otherwise.
+ *
+ * \note application can use print_txpwrlimit API to print the
+ *	 content of the txpwrlimit structure.
+ */
+int wlan_get_txpwrlimit(wifi_SubBand_t subband, wifi_txpwrlimit_t *txpwrlimit);
+
+#if CONFIG_AUTO_RECONNECT
+/**
+ * Enable auto reconnect feature in Wi-Fi firmware.
+ *
+ * \param[in] auto_reconnect_config auto reconnect configuration
+ *	      structure holding following parameters:
+ *	      1. reconnect counter(0x1-0xff) - The number of times the Wi-Fi
+ *		 firmware retries connection attempt with AP.
+ *				The value 0xff means retry forever.
+ *				(default 0xff).
+ *	      2. reconnect interval(0x0-0xff) - Time gap in seconds between
+ *				each connection attempt (default 10).
+ *	      3. flags - Bit 0:
+ *			 Set to 1: Firmware should report link-loss to host
+ *				if AP rejects authentication/association
+ *				while reconnecting.
+ *			 Set to 0: Default behaviour: Firmware does not report
+ *				link-loss to host on AP rejection and
+ *				continues internally.
+ *			 Bit 1-15: Reserved.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ *
+ */
+int wlan_auto_reconnect_enable(wlan_auto_reconnect_config_t auto_reconnect_config);
+
+/**
+ * Disable auto reconnect feature in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ *
+ */
+int wlan_auto_reconnect_disable(void);
+
+/**
+ * Get auto reconnect configuration from Wi-Fi firmware.
+ *
+ * \param[out] auto_reconnect_config auto reconnect configuration
+ *	       structure where response from Wi-Fi firmware
+ *	       gets stored.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_E_INVAL if auto_reconnect_config is not valid.
+ * \return -WM_FAIL if command fails.
+ *
+ */
+int wlan_get_auto_reconnect_config(wlan_auto_reconnect_config_t *auto_reconnect_config);
+#endif
+/**
+ * Set reassociation control in Wi-Fi connection manager.
+ * \note Reassociation is enabled by default in the Wi-Fi connection manager.
+ *
+ * \param[in] reassoc_control Reassociation enable/disable
+ *
+ */
+void wlan_set_reassoc_control(bool reassoc_control);
+
+/** API to set the beacon period of UAP
+ *
+ *\param[in] beacon_period Beacon period in TU (1 TU = 1024 micro seconds)
+ *
+ *\note  Call this API before calling UAP start API.
+ *
+ */
+void wlan_uap_set_beacon_period(const uint16_t beacon_period);
+
+/** API to set the bandwidth of UAP
+ *
+ *\param[in] bandwidth Wi-Fi AP bandwidth (20MHz/40MHz)
+    1: 20 MHz 2: 40 MHz 3: 80 MHz
+ *
+ *\return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *\return -WM_FAIL if command fails.
+ *
+ *\note  call this API before calling UAP start API.
+ *\note Default bandwidth setting is 40 MHz.
+ *
+ */
+int wlan_uap_set_bandwidth(const uint8_t bandwidth);
+
+/** API to get the bandwidth of UAP
+ *
+ *\param[out] bandwidth Wi-Fi AP bandwidth (20MHz/40MHz)
+    1: 20 MHz 2: 40 MHz 3: 80 MHz
+ *
+ *\return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *\return -WM_FAIL if command fails.
+ *
+ *\note  call this API before calling UAP start API.
+ *
+ */
+int wlan_uap_get_bandwidth(uint8_t *bandwidth);
+
+/** API to control SSID broadcast capability of UAP
+ *
+ * This API enables/disables the SSID broadcast feature
+ * (also known as the hidden SSID feature). When broadcast SSID
+ * is enabled, the AP responds to probe requests from client stations
+ * that contain null SSID. When broadcast SSID is disabled, the AP
+ * does not respond to probe requests that contain null SSID and
+ * generates beacons that contain null SSID.
+ *
+ *\param[in] hidden_ssid Hidden SSID control
+ *           hidden_ssid=0: broadcast SSID in beacons.
+ *           hidden_ssid=1: send empty SSID (length=0) in beacon.
+ *           hidden_ssid=2: clear SSID (ACSII 0), but keep the original length
+ *
+ *\return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *\return -WM_FAIL if command fails.
+ *
+ *\note  call this API before calling UAP start API.
+ *
+ */
+int wlan_uap_set_hidden_ssid(const t_u8 hidden_ssid);
+
+/** API to control the deauth during UAP channel switch.
+ *
+ *\param[in] enable 0 -- Wi-Fi firmware can use default behaviour.
+ *		    1 -- Wi-Fi firmware can not send deauth packet
+ *		         when UAP move to another channel.
+ *
+ *\note  call this API before calling UAP start API.
+ *
+ */
+void wlan_uap_ctrl_deauth(const bool enable);
+
+/** API to enable channel switch announcement functionality on UAP.
+ *
+ *\note  call this API before calling UAP start API. Also
+ *	note that 802.11n should be enabled on UAP. The channel switch announcement IE
+ *	is transmitted in 7 beacons before the channel switch, during a station
+ *	connection attempt on a different channel with Ex-AP.
+ *
+ */
+void wlan_uap_set_ecsa(void);
+
+/** API to set the HT capability information of UAP.
+ *
+ *\param[in] ht_cap_info - This is a bitmap and should be used as following\n
+ *             Bit 15: L Sig TxOP protection - reserved, set to 0 \n
+ *             Bit 14: 40 MHz intolerant - reserved, set to 0 \n
+ *             Bit 13: PSMP - reserved, set to 0 \n
+ *             Bit 12: DSSS Cck40MHz mode\n
+ *             Bit 11: Maximal A-MSDU size - reserved, set to 0 \n
+ *             Bit 10: Delayed BA - reserved, set to 0 \n
+ *             Bits 9:8: RX STBC - reserved, set to 0 \n
+ *             Bit 7: TX STBC - reserved, set to 0 \n
+ *             Bit 6: Short GI 40 MHz\n
+ *             Bit 5: Short GI 20 MHz\n
+ *             Bit 4: GF preamble\n
+ *             Bits 3:2: MIMO power save - reserved, set to 0 \n
+ *             Bit 1: SuppChanWidth - set to 0 for 2.4 GHz band \n
+ *             Bit 0: LDPC coding - reserved, set to 0 \n
+ *
+ *\note  call this API before calling UAP start API.
+ *
+ */
+void wlan_uap_set_htcapinfo(const uint16_t ht_cap_info);
+
+/**
+ * This API can be used to configure various 802.11n specific configuration
+ *       for transmit (such as short GI, channel bandwidth and green field support)
+ *       for UAP interface.
+ *
+ * \param[in] httxcfg This is a bitmap and should be used as following\n
+ *               Bit 15-8: Reserved set to 0\n
+ *               Bit 7: STBC Enable/Disable\n
+ *               Bit 6: Short GI in 40 Mhz Enable/Disable\n
+ *               Bit 5: Short GI in 20 Mhz Enable/Disable\n
+ *               Bit 4: Green field Enable/Disable\n
+ *               Bit 3-2: Reserved set to 1\n
+ *               Bit 1: 20/40 Mhz enable disable.\n
+ *               Bit 0: LDPC Enable/Disable\n
+ *
+ *       When Bit 1 is set then firmware could transmit in 20Mhz or 40Mhz based\n
+ *       on rate adaptation. When this bit is reset then firmware can only\n
+ *       transmit in 20Mhz.\n
+ *
+ *\note  Call this API before calling UAP start API.
+ *
+ */
+void wlan_uap_set_httxcfg(unsigned short httxcfg);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when station is a transmitter.
+ *
+ * \note By default the station AMPDU TX support is on if
+ * configuration option is enabled in defconfig.
+ */
+void wlan_sta_ampdu_tx_enable(void);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when station is a transmitter.
+ *
+ *\note By default the station AMPDU RX support is on if
+ * configuration option is enabled in defconfig.
+ *
+ */
+void wlan_sta_ampdu_tx_disable(void);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when station is a receiver.
+ */
+void wlan_sta_ampdu_rx_enable(void);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when station is a receiver.
+ */
+void wlan_sta_ampdu_rx_disable(void);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when UAP is a transmitter.
+ *
+ * \note By default the UAP AMPDU TX support is on if
+ * configuration option is enabled in defconfig.
+ */
+void wlan_uap_ampdu_tx_enable(void);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when UAP is a transmitter.
+ *
+ *\note By default the UAP AMPDU RX support is on if
+ * configuration option is enabled in defconfig.
+ *
+ */
+void wlan_uap_ampdu_tx_disable(void);
+
+/**
+ * This API can be used to enable AMPDU support on the go
+ * when UAP is a receiver.
+ */
+void wlan_uap_ampdu_rx_enable(void);
+
+/**
+ * This API can be used to disable AMPDU support on the go
+ * when UAP is a receiver.
+ */
+void wlan_uap_ampdu_rx_disable(void);
+
+
+/**
+ * Set number of channels and channel number used during automatic
+ * channel selection of UAP.
+ *
+ *\param[in] scan_chan_list A structure holding the number of channels and
+ *	     channel numbers.
+ *
+ *\note  call this API before UAP start API in order to set the user
+ *      defined channels, otherwise it can have no effect. There is no need
+ *      to call this API every time before UAP start, if once set same channel
+ *      configuration can get used in all upcoming UAP start call. If user
+ *      wish to change the channels at run time then it make sense to call
+ *      this API before every UAP start API.
+ */
+void wlan_uap_set_scan_chan_list(wifi_scan_chan_list_t scan_chan_list);
+
+#if CONFIG_WPA2_ENTP
+
+/**
+ * Use this API if application want to allow station
+ * connection to WPA2 Enterprise ap profiles only.
+ *
+ * If called the in scan result only the WPA2 Enterprise AP
+ * can be listed and station network profile only with WPA2
+ * Enterprise security can be allowed to add to network profile
+ * list.
+ */
+void wlan_enable_wpa2_enterprise_ap_only(void);
+#endif
+
+/**
+ * Set the rts threshold of STA in Wi-Fi firmware.
+ *
+ * \param[in] rts the value of rts threshold configuration.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_rts(int rts);
+
+/**
+ * Set the rts threshold of UAP in Wi-Fi firmware.
+ *
+ * \param[in] rts the value of rts threshold configuration.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_uap_rts(int rts);
+
+#if CONFIG_WIFI_FRAG_THRESHOLD
+/**
+ * Set the fragment threshold of STA in Wi-Fi firmware.
+ *
+ * \param[in] frag The value of fragment threshold configuration.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_frag(int frag);
+
+/**
+ * Set the fragment threshold of UAP in Wi-Fi firmware.
+ *
+ * \param[in] frag the value of fragment threshold configuration.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_uap_frag(int frag);
+#endif
+
+
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+/**
+ * Set the STA MAC filter in Wi-Fi firmware.
+ *
+ * \param[in] filter_mode Channel filter mode (disable/white/black list)
+ * \param[in] mac_count The ount of MAC list
+ * \param[in] mac_addr The pointer to MAC address list
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_sta_mac_filter(int filter_mode, int mac_count, unsigned char *mac_addr);
+#endif
+
+static inline void print_mac(const char *mac)
+{
+    (void)PRINTF("%02X:%02X:%02X:%02X:%02X:%02X ", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+}
+
+#if CONFIG_RF_TEST_MODE
+
+/**
+ * Set the RF test mode in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_rf_test_mode(void);
+
+/**
+ * Unset the RF test mode in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful.
+ */
+int wlan_unset_rf_test_mode(void);
+
+/**
+ * Set the RF channel in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] channel The channel number to be set in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_channel(const uint8_t channel);
+
+/**
+ * Set the RF radio mode in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] mode The radio mode number to be set in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_radio_mode(const uint8_t mode);
+
+/**
+ * Get the RF channel from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] channel A pointer to a variable where channel number to get.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_channel(uint8_t *channel);
+
+/**
+ * Get the RF radio mode from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] mode A pointer to a variable where radio mode number to get.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_radio_mode(uint8_t *mode);
+
+/**
+ * Set the RF band in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] band The bandwidth to be set in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_band(const uint8_t band);
+
+/**
+ * Get the RF band from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] band A Pointer to a variable where RF band is to be stored.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_band(uint8_t *band);
+
+/**
+ * Set the RF bandwidth in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] bandwidth The bandwidth to be set in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_bandwidth(const uint8_t bandwidth);
+
+/**
+ * Get the RF bandwidth from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] bandwidth A Pointer to a variable where bandwidth to get.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_bandwidth(uint8_t *bandwidth);
+
+/**
+ * Get the RF RX total packet and multicast/broadcast packet count.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] rx_tot_pkt_count A Pointer to a variable where RX total packet count to get.
+ * \param[out] rx_mcast_bcast_count A Pointer to a variable where RX total multicast/broadcast packet count to get.
+ * \param[out] rx_pkt_fcs_error A Pointer to a variable where RX total packet count with FCS (frame check sequence) error to get.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_per(uint32_t *rx_tot_pkt_count, uint32_t *rx_mcast_bcast_count, uint32_t *rx_pkt_fcs_error);
+
+/**
+ * Set the RF TX continuous mode in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] enable_tx Enable TX.
+ * \param[in] cw_mode Set CW (continuous wave) mode.
+ * \param[in] payload_pattern Set payload pattern.
+ * \param[in] cs_mode Set CS mode.
+ * \param[in] act_sub_ch Active subchannel.
+ * \param[in] tx_rate Set TX rate.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL..
+ *
+ */
+int wlan_set_rf_tx_cont_mode(const uint32_t enable_tx,
+                             const uint32_t cw_mode,
+                             const uint32_t payload_pattern,
+                             const uint32_t cs_mode,
+                             const uint32_t act_sub_ch,
+                             const uint32_t tx_rate);
+
+/**
+ * Set the RF HE TB TX in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] enable Enable/Disable trigger response mode
+ * \param[in] qnum AXQ to be used for the trigger response frame
+ * \param[in] aid AID of the peer to which response is to be generated
+ * \param[in] axq_mu_timer MU timer for the AXQ on which response is sent
+ * \param[in] tx_power TxPwr to be configured for the response
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_cfg_rf_he_tb_tx(uint16_t enable, uint16_t qnum, uint16_t aid, uint16_t axq_mu_timer, int16_t tx_power);
+
+/**
+ * Set the RF Trigger Frame Config in Wi-Fi firmware.
+ *
+ * \note call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] Enable_tx Enable or Disable trigger frame transmission.
+ * \param[in] Standalone_hetb Enable or Disable Standalone HE TB support.
+ * \param[in] FRAME_CTRL_TYPE Frame control type.
+ * \param[in] FRAME_CTRL_SUBTYPE Frame control subtype.
+ * \param[in] FRAME_DURATION Max Duration time.
+ * \param[in] TriggerType Identifies the Trigger frame variant and its encoding.
+ * \param[in] UlLen Indicates the value of the L-SIG LENGTH field of the solicited HE TB PPDU.
+ * \param[in] MoreTF Indicates whether a subsequent Trigger frame is scheduled for transmission.
+ * \param[in] CSRequired Required to use ED to sense the medium and to consider the medium state and the NAV in
+ * determining whether to respond. \param[in] UlBw Indicates the bandwidth in the HE-SIG-A field of the HE TB PPDU.
+ * \param[in] LTFType Indicates the LTF type of the HE TB PPDU response.
+ * \param[in] LTFMode Indicates the LTF mode for an HE TB PPDU.
+ * \param[in] LTFSymbol Indicates the number of LTF symbols present in the HE TB PPDU.
+ * \param[in] UlSTBC Indicates the status of STBC encoding for the solicited HE TB PPDUs.
+ * \param[in] LdpcESS Indicates the status of the LDPC extra symbol segment.
+ * \param[in] ApTxPwr Indicates the AP’s combined transmit power at the transmit antenna connector of all the antennas
+ * used to transmit the triggering PPDU. \param[in] PreFecPadFct Indicates the pre-FEC padding factor. \param[in]
+ * PeDisambig Indicates PE disambiguity. \param[in] SpatialReuse Carries the values to be included in the Spatial Reuse
+ * fields in the HE-SIG-A field of the solicited HE TB PPDUs. \param[in] Doppler Indicate that a midamble is present in
+ * the HE TB PPDU. \param[in] HeSig2 Carries the value to be included in the Reserved field in the HE-SIG-A2 subfield of
+ * the solicited HE TB PPDUs. \param[in] AID12 If set to 0 allocates one or more contiguous RA-RUs for associated STAs.
+ * \param[in] RUAllocReg RUAllocReg.
+ * \param[in] RUAlloc Identifies the size and the location of the RU.
+ * \param[in] UlCodingType Indicates the code type of the solicited HE TB PPDU.
+ * \param[in] UlMCS Indicates the HE-MCS of the solicited HE TB PPDU.
+ * \param[in] UlDCM Indicates DCM of the solicited HE TB PPDU.
+ * \param[in] SSAlloc Indicates the spatial streams of the solicited HE TB PPDU.
+ * \param[in] UlTargetRSSI Indicates the expected receive signal power.
+ * \param[in] MPDU_MU_SF Used for calculating the value by which the minimum MPDU start spacing is multiplied.
+ * \param[in] TID_AL Indicates the MPDUs allowed in an A-MPDU carried in the HE TB PPDU and the maximum number of TIDs
+ * that can be aggregated by the STA in the A-MPDU. \param[in] AC_PL Reserved. \param[in] Pref_AC Indicates the lowest
+ * AC that is recommended for aggregation of MPDUs in the A-MPDU contained in the HE TB PPDU sent as a response to the
+ * Trigger frame.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_rf_trigger_frame_cfg(uint32_t Enable_tx,
+                              uint32_t Standalone_hetb,
+                              uint8_t FRAME_CTRL_TYPE,
+                              uint8_t FRAME_CTRL_SUBTYPE,
+                              uint16_t FRAME_DURATION,
+                              uint64_t TriggerType,
+                              uint64_t UlLen,
+                              uint64_t MoreTF,
+                              uint64_t CSRequired,
+                              uint64_t UlBw,
+                              uint64_t LTFType,
+                              uint64_t LTFMode,
+                              uint64_t LTFSymbol,
+                              uint64_t UlSTBC,
+                              uint64_t LdpcESS,
+                              uint64_t ApTxPwr,
+                              uint64_t PreFecPadFct,
+                              uint64_t PeDisambig,
+                              uint64_t SpatialReuse,
+                              uint64_t Doppler,
+                              uint64_t HeSig2,
+                              uint32_t AID12,
+                              uint32_t RUAllocReg,
+                              uint32_t RUAlloc,
+                              uint32_t UlCodingType,
+                              uint32_t UlMCS,
+                              uint32_t UlDCM,
+                              uint32_t SSAlloc,
+                              uint8_t UlTargetRSSI,
+                              uint8_t MPDU_MU_SF,
+                              uint8_t TID_AL,
+                              uint8_t AC_PL,
+                              uint8_t Pref_AC);
+
+/**
+ * Set the RF TX antenna in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] antenna The TX antenna to be set in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_tx_antenna(const uint8_t antenna);
+
+/**
+ * Get the RF TX antenna from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] antenna A Pointer to a variable where TX antenna is to be stored.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_tx_antenna(uint8_t *antenna);
+
+/**
+ * Set RF RX antenna in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] antenna The RX antenna to be set in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_rx_antenna(const uint8_t antenna);
+
+/**
+ * Get RF RX antenna from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] antenna A Pointer to a variable where RX antenna is to be stored.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_rx_antenna(uint8_t *antenna);
+
+/**
+ * Set RF RX power in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] power The RF RX power to be set in Wi-Fi firmware.
+ *                  For RW610, 20M bandwidth max linear output power is 20db per data sheet.
+ * \param[in] mod The modulation to be set in Wi-Fi firmware.
+ * \param[in] path_id The Path ID to be set in Wi-Fi firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_tx_power(const uint32_t power, const uint8_t mod, const uint8_t path_id);
+
+/**
+ * Set the RF TX Frame in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] enable Enable/Disable RF TX Frame
+ * \param[in] data_rate Rate index corresponding to legacy/HT/VHT rates
+ * \param[in] frame_pattern Payload pattern
+ * \param[in] frame_length Payload length
+ * \param[in] adjust_burst_sifs Enabl/Disable adjust burst SIFS3 Gap
+ * \param[in] burst_sifs_in_us Burst SIFS in us
+ * \param[in] short_preamble Enable/Disable short preamble
+ * \param[in] act_sub_ch Enable/Disable active subChannel
+ * \param[in] short_gi Short guard interval
+ * \param[in] adv_coding Enable/Disable adv Coding
+ * \param[in] tx_bf Enable/Disable beamforming
+ * \param[in] gf_mode Enable/Disable green field mode
+ * \param[in] stbc Enable/Disable STBC
+ * \param[in] bssid BSSID
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_tx_frame(const uint32_t enable,
+                         const uint32_t data_rate,
+                         const uint32_t frame_pattern,
+                         const uint32_t frame_length,
+                         const uint16_t adjust_burst_sifs,
+                         const uint32_t burst_sifs_in_us,
+                         const uint32_t short_preamble,
+                         const uint32_t act_sub_ch,
+                         const uint32_t short_gi,
+                         const uint32_t adv_coding,
+                         const uint32_t tx_bf,
+                         const uint32_t gf_mode,
+                         const uint32_t stbc,
+                         const uint8_t *bssid);
+
+/**
+ * Set the RF OTP (one-time password) MAC address in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] MAC A pointer to a variable where OTP MAC address is to be stored.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_otp_mac_addr(uint8_t *mac);
+
+/**
+ * Get the RF OTP MAC address from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] MAC A Pointer to a variable where OTP MAC address is to be stored.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_otp_mac_addr(uint8_t *mac);
+
+/**
+ * Set the RF OTP calculate data in Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[in] cal_data A Pointer to a variable where OTP calculate data is to be stored.
+ * \param[in] cal_data_len The length of OTP calculate data.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_set_rf_otp_cal_data(const uint8_t *cal_data, uint32_t cal_data_len);
+
+/**
+ * Get the RF OTP calculate data from Wi-Fi firmware.
+ *
+ * \note  call \ref wlan_set_rf_test_mode API before using this API.
+ *
+ * \param[out] cal_data A pointer to a variable where OTP calculate data is to be stored.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_get_rf_otp_cal_data(uint8_t *cal_data);
+#endif
+#if CONFIG_WIFI_FW_DEBUG
+/** This function registers callbacks which are used to generate firmware dump on USB
+ * device.
+ *
+ * \param[in] wlan_usb_init_cb Callback to initialize usb device.
+ * \param[in] wlan_usb_mount_cb Callback to mount usb device.
+ * \param[in] wlan_usb_file_open_cb Callback to open file on usb device for firmware dump.
+ * \param[in] wlan_usb_file_write_cb Callback to write firmware dump data to opened file.
+ * \param[in] wlan_usb_file_close_cb Callback to close firmware dump file.
+ *
+ */
+void wlan_register_fw_dump_cb(void (*wlan_usb_init_cb)(void),
+                              int (*wlan_usb_mount_cb)(),
+                              int (*wlan_usb_file_open_cb)(char *test_file_name),
+                              int (*wlan_usb_file_write_cb)(uint8_t *data, size_t data_len),
+                              int (*wlan_usb_file_close_cb)());
+
+#endif
+
+#if CONFIG_WIFI_EU_CRYPTO
+#define EU_CRYPTO_DATA_MAX_LENGTH  1300U
+#define EU_CRYPTO_KEY_MAX_LENGTH   32U
+#define EU_CRYPTO_KEYIV_MAX_LENGTH 32U
+#define EU_CRYPTO_NONCE_MAX_LENGTH 14U
+#define EU_CRYPTO_AAD_MAX_LENGTH   32U
+
+/** Set crypto RC4 (rivest cipher 4) algorithm encrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The KeyLength + KeyIVLength valid range [1,256].
+ * \param[in] KeyIV KeyIV
+ * \param[in] KeyIVLength The KeyLength + KeyIVLength valid range [1,256].
+ * \param[in] Data Data
+ * \param[in] DataLength The maximum data length is 1200.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the encrypted
+ * data. The value of DataLength is updated to the encrypted data length. The length of the encrypted data is the same
+ * as the origin DataLength.
+ */
+int wlan_set_crypto_RC4_encrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength);
+
+/** Set crypto RC4 (rivest cipher 4) algorithm decrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The KeyLength + KeyIVLength valid range [1,256].
+ * \param[in] KeyIV KeyIV
+ * \param[in] KeyIVLength The KeyLength + KeyIVLength valid range [1,256].
+ * \param[in] Data Data
+ * \param[in] DataLength The maximum data length is 1200.
+ *
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the decrypted
+ * data. The value of DataLength is updated to the decrypted data length. The length of the decrypted data is the same
+ * as the origin DataLength.
+ */
+int wlan_set_crypto_RC4_decrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength);
+
+/** Set crypto AES_ECB (advanced encryption standard, electronic codebook) algorithm encrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/24/32.
+ * \param[in] KeyIV KeyIV should point to a 8 bytes array with any value in the array.
+ * \param[in] KeyIVLength The keyIV length is 8.
+ * \param[in] Data Data
+ * \param[in] DataLength The data length is 16.
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the encrypted
+ * data. The value of DataLength is updated to the encrypted data length. The length of the encrypted data is the same
+ * as the origin DataLength.
+ */
+int wlan_set_crypto_AES_ECB_encrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength);
+
+/** Set crypto AES_ECB (advanced encryption standard, electronic codebook) algorithm decrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/24/32.
+ * \param[in] KeyIV KeyIV should point to a 8 bytes array with any value in the array.
+ * \param[in] KeyIVLength The keyIV length is 8.
+ * \param[in] Data Data
+ * \param[in] DataLength The data length is 16.
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the decrypted
+ * data. The value of DataLength is updated to the decrypted data length. The length of the decrypted data is the same
+ * as the origin DataLength.
+ */
+int wlan_set_crypto_AES_ECB_decrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength);
+
+/** Set crypto AES_WRAP (advanced encryption standard wrap) algorithm encrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/24/32.
+ * \param[in] KeyIV KeyIV
+ * \param[in] KeyIVLength The keyIV length is 8.
+ * \param[in] Data Data
+ * \param[in] DataLength The data length valid range [8,1016].
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the encrypted
+ * data. The value of DataLength is updated to the encrypted data length. The encrypted data is 8 bytes more than the
+ * original data. Therefore, the address pointed to by Data needs to reserve enough space.
+ */
+int wlan_set_crypto_AES_WRAP_encrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength);
+
+/** Set crypto AES_WRAP algorithm decrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/24/32.
+ * \param[in] KeyIV KeyIV
+ * \param[in] KeyIVLength The keyIV length is 8.
+ * \param[in] Data Data
+ * \param[in] DataLength The data length valid range [8,1016].
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the decrypted
+ * data. The value of DataLength is updated to the decrypted data length. The decrypted data is 8 bytes less than the
+ * original data.
+ */
+int wlan_set_crypto_AES_WRAP_decrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength);
+
+/** Set crypto AES_CCMP (counter mode with cipher block chaining message authentication code protocol)
+ * algorithm encrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/32.
+ * \param[in] AAD AAD
+ * \param[in] AADLength The maximum AAD length is 30.
+ * \param[in] Nonce Nonce
+ * \param[in] NonceLength The nonce length valid range [7,13].
+ * \param[in] Data Data
+ * \param[in] DataLength The maximum data length is 80.
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the encrypted
+ * data. The value of DataLength is updated to the encrypted data length. The encrypted data is 8 or 16 bytes more than
+ * the original data. Therefore, the address pointed to by Data needs to reserve enough space.
+ */
+int wlan_set_crypto_AES_CCMP_encrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength);
+
+/** Set crypto AES_CCMP algorithm decrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/32.
+ * \param[in] AAD AAD
+ * \param[in] AADLength The maximum AAD length is 30.
+ * \param[in] Nonce Nonce
+ * \param[in] NonceLength The nonce length valid range [7,13].
+ * \param[in] Data Data
+ * \param[in] DataLength The maximum data length is 80.
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the decrypted
+ * data. The value of DataLength is updated to the decrypted data length. The decrypted data is 8 or 16 bytes less than
+ * the original data.
+ */
+int wlan_set_crypto_AES_CCMP_decrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength);
+
+/** Set crypto AES_GCMP (galois/counter mode with AES-GMAC) algorithm encrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/32.
+ * \param[in] AAD AAD
+ * \param[in] AADLength The maximum AAD length is 30.
+ * \param[in] Nonce Nonce
+ * \param[in] NonceLength The nonce length valid range [7,13].
+ * \param[in] Data Data
+ * \param[in] DataLength The maximum data length is 80.
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the encrypted
+ * data. The value of DataLength is updated to the encrypted data length. The encrypted data is 16 bytes more than the
+ * original data. Therefore, the address pointed to by Data needs to reserve enough space.
+ */
+int wlan_set_crypto_AES_GCMP_encrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength);
+
+/** Set crypto AES_CCMP algorithm decrypt command param.
+ *
+ * \param[in] Key key
+ * \param[in] KeyLength The key length is 16/32.
+ * \param[in] AAD AAD
+ * \param[in] AADLength The maximum AAD length is 30.
+ * \param[in] Nonce Nonce
+ * \param[in] NonceLength The nonce length valid range [7,13].
+ * \param[in] Data Data
+ * \param[in] DataLength The maximum data length is 80.
+ * \return WM_SUCCESS if successful.
+ * \return -WM_E_PERM if not supported.
+ * \return -WM_FAIL if failure.
+ *
+ * \note If the function returns WM_SUCCESS, the data in the memory pointed to by data is overwritten by the decrypted
+ * data. The value of DataLength is updated to the decrypted data length. The decrypted data is 16 bytes less than the
+ * original data.
+ */
+int wlan_set_crypto_AES_GCMP_decrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength);
+#endif
+
+#if CONFIG_WIFI_MEM_ACCESS
+/** This function reads/writes adapter memory location value.
+ *
+ *\param[in]        action      0 -- read, 1 -- write
+ *\param[in]        addr        Specifies the memory address that is to be read/write.
+ *\param[in,out]    value       Value if specified, stand for write action, then that value can be written to that
+ *offset in the specified register. Value should be specified in hexadecimal. Otherwise, it stands for read action, the
+ *value is updated with read value.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_mem_access(uint16_t action, uint32_t addr, uint32_t *value);
+#endif
+
+#if CONFIG_WIFI_BOOT_SLEEP
+/** This function get/set Wi-Fi boot sleep enable status.
+ *
+ *\param[in]        action      0 -- get, 1 -- set
+ *\param[in,out]    enable      If action is get then enable value is used to store firmware returned value otherwise it
+ *is set in firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_boot_sleep(uint16_t action, uint16_t *enable);
+#endif
+
+/**
+ * This function sends the host command to firmware and copies back response to caller provided buffer in case of
+ * success response from firmware is not parsed by this function but just copied back to the caller buffer.
+ *
+ *  \param[in]    cmd_buf         Buffer containing the host command with header
+ *  \param[in]    cmd_buf_len     length of valid bytes in cmd_buf
+ *  \param[out]   host_resp_buf   Caller provided buffer, in case of success command response is copied to this
+ * buffer can be same as cmd_buf \param[in]    resp_buf_len    resp_buf's allocated length \param[out]   reqd_resp_len
+ * length of valid bytes in response buffer if successful otherwise invalid. \return                       WM_SUCCESS in
+ * case of success. \return                       WM_E_INBIG in case cmd_buf_len is bigger than the commands that can be
+ * handled by driver. \return                       WM_E_INSMALL in case cmd_buf_len is smaller than the minimum length.
+ * Minimum length is atleast the length of command header.  see Note for same. \return WM_E_OUTBIG in case the
+ * resp_buf_len is not sufficient to copy response from firmware. reqd_resp_len is updated with the response size.
+ *  \return                       WM_E_INVAL in case cmd_buf_len and resp_buf_len have invalid values.
+ *  \return                       WM_E_NOMEM in case cmd_buf, resp_buf and reqd_resp_len are NULL
+ *  \note                         Brief on the command Header: Start 8 bytes of cmd_buf should have these values set.
+ *                                Firmware would update resp_buf with these 8 bytes at the start.\n
+ *                                2 bytes : Command.\n
+ *                                2 bytes : Size.\n
+ *                                2 bytes : Sequence number.\n
+ *                                2 bytes : Result.\n
+ *                                Rest of buffer length is Command/Response Body.
+ */
+
+int wlan_send_hostcmd(
+    const void *cmd_buf, uint32_t cmd_buf_len, void *host_resp_buf, uint32_t resp_buf_len, uint32_t *reqd_resp_len);
+
+#if CONFIG_11AX
+/**
+ * This function is used to set HTC (high throughput control) parameter.
+ *
+ *  \param[in]    count
+ *  \param[in]    vht
+ *  \param[in]    he
+ *  \param[in]    rxNss
+ *  \param[in]    channelWidth
+ *  \param[in]    ulMuDisable
+ *  \param[in]    txNSTS
+ *  \param[in]    erSuDisable
+ *  \param[in]    dlResoundRecomm
+ *  \param[in]    ulMuDataDisable
+ *
+ * \return WM_SUCCESS if operation is successful, otherwise return -WM_FAIL
+ */
+int wlan_send_debug_htc(const uint8_t count,
+                        const uint8_t vht,
+                        const uint8_t he,
+                        const uint8_t rxNss,
+                        const uint8_t channelWidth,
+                        const uint8_t ulMuDisable,
+                        const uint8_t txNSTS,
+                        const uint8_t erSuDisable,
+                        const uint8_t dlResoundRecomm,
+                        const uint8_t ulMuDataDisable);
+
+/**
+ * This function is used to enable/disable HTC (high throughput control).
+ *
+ *  \param[in]    option         1 => Enable; 0 => Disable
+ *
+ * \return WM_SUCCESS if operation is successful, otherwise return -WM_FAIL
+ */
+int wlan_enable_disable_htc(uint8_t option);
+#endif
+
+#if CONFIG_11AX
+/**
+ * Use this API to set the set 802.11ax TX OMI (operating mode inication).
+ *
+ * \param[in] interface Interface type STAor UAP.
+ * \param[in] tx_omi value to be sent to firmware
+ * \param[in] tx_option value to be sent to firmware
+ *            1: send OMI (operating mode indication) in QoS (quality of service) data.
+ * \param[in] num_data_pkts value to be sent to firmware
+ *            num_data_pkts is applied only if OMI is sent in QoS data frame.
+ *            It specifies the number of consecutive data frames containing the OMI.
+ *            Minimum value is 1
+ *            Maximum value is 16
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_set_11ax_tx_omi(const t_u8 interface, const t_u16 tx_omi, const t_u8 tx_option, const t_u8 num_data_pkts);
+/**
+ * Set 802.11ax OBSS (overlapping basic service set) narrow bandwidth RU (resource unit) tolerance time
+ * In uplink transmission, AP sends a trigger frame to all the stations that can be involved in the upcoming
+ *transmission, and then these stations transmit Trigger-based(TB) PPDU in response to the trigger frame. If STA
+ *connects to AP which channel is set to 100,STA doesn't support 26 tones RU. The API should be called when station is
+ *in disconnected state.
+ *
+ *
+ * \param[in] tol_time     Valid range [1...3600]
+ *          tolerance time is in unit of seconds.
+ *			STA periodically check AP's beacon for ext cap bit79 (OBSS Narrow bandwidth RU in ofdma tolerance support)
+ * 			and set 20 tone RU tolerance time if ext cap bit79 is not set
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_11ax_tol_time(const t_u32 tol_time);
+/**
+ * Use this API to set the RU TX power limit.
+ *
+ * \param[in] rutx_pwr_cfg       802.11ax rutxpwr of sub-bands to be sent to firmware.
+ * \param[in] rutx_pwr_cfg_len   Size of rutx_pwr_cfg buffer.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_set_11ax_rutxpowerlimit(const void *rutx_pwr_cfg, uint32_t rutx_pwr_cfg_len);
+
+/**
+ * Use this API to set the RU TX power limit by channel based approach.
+ *
+ * \param[in] ru_pwr_cfg 802.11ax rutxpwr of channels to be sent to firmware.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_set_11ax_rutxpowerlimit_legacy(const wlan_rutxpwrlimit_t *ru_pwr_cfg);
+
+/**
+ * Use this API to get the RU TX power limit by channel based approach.
+ *
+ * \param[in] ru_pwr_cfg 802.11ax rutxpwr of channels to be get from firmware.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_get_11ax_rutxpowerlimit_legacy(wlan_rutxpwrlimit_t *ru_pwr_cfg);
+
+/** Set 802.11ax config params
+ *
+ * \param[in, out] ax_config 802.11ax config parameters to be sent to firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_11ax_cfg(wlan_11ax_config_t *ax_config);
+
+/** Get default 802.11ax config params
+ *
+ * \return 802.11ax config parameters default array.
+ */
+uint8_t *wlan_get_11ax_cfg(void);
+
+#if CONFIG_11AX_TWT
+/** Set broadcast TWT (target wake time) config params
+ *
+ * \param[in] btwt_config Broadcast TWT setup parameters to be sent to firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_btwt_cfg(const wlan_btwt_config_t *btwt_config);
+
+/** Get broadcast TWT config params
+ *
+ * \return Broadcast TWT setup parameters default config array.
+ */
+uint8_t *wlan_get_btwt_cfg(void);
+
+/** Set TWT setup config params
+ *
+ * \param[in] twt_setup TWT setup parameters to be sent to firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_twt_setup_cfg(const wlan_twt_setup_config_t *twt_setup);
+
+/** Get TWT setup config params
+ *
+ * \return TWT setup parameters default array.
+ */
+uint8_t *wlan_get_twt_setup_cfg(void);
+
+/** Set TWT teardown config params
+ *
+ * \param[in] teardown_config TWT teardown parameters sent to firmware.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_twt_teardown_cfg(const wlan_twt_teardown_config_t *teardown_config);
+
+/** Get TWT teardown config params
+ *
+ * \return TWT Teardown parameters default array
+ */
+uint8_t *wlan_get_twt_teardown_cfg(void);
+
+/** Get TWT report
+ *
+ * \param[out] twt_report TWT report parameter.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_twt_report(wlan_twt_report_t *twt_report);
+
+#endif /* CONFIG_11AX_TWT */
+
+#if CONFIG_MMSF
+/**
+ * Set 802.11ax AMPDU (aggregate medium access control (MAC) protocol data unit) density config.
+ * \param[in] enable     0 - Disbale MMSF;  1 - Enable MMSF
+ * \param[in] Density    AMPDU density value. Default value is 0x30.
+ * \param[in] MMSF       AMPDU MMSF value. Default value is 0x6.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_mmsf(const t_u8 enable, const t_u8 Density, const t_u8 MMSF);
+
+/**
+ * Get 802.11ax AMPDU density config.
+ * \param[out] enable     0 - Disbale MMSF;  1 - Enable MMSF
+ * \param[out] Density    AMPDU Density value. Default value is 0x30.
+ * \param[out] MMSF       AMPDU MMSF value. Default value is 0x6.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_mmsf(t_u8 *enable, t_u8 *Density, t_u8 *MMSF);
+#endif
+#endif /* CONFIG_11AX */
+
+#if CONFIG_WIFI_RECOVERY
+int wlan_recovery_test(void);
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+/** Set clock sync GPIO based TSF (time synchronization function).
+ *
+ * \param[in] tsf_latch Clock sync TSF latch parameters to be sent to firmware
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_clocksync_cfg(const wlan_clock_sync_gpio_tsf_t *tsf_latch);
+/** Get TSF info from firmware using GPIO latch.
+ *
+ * \param[out] tsf_info TSF info parameter received from firmware
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_tsf_info(wlan_tsf_info_t *tsf_info);
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+#if CONFIG_HEAP_DEBUG
+/**
+ * Show os mem alloc and free info.
+ *
+ */
+void wlan_show_os_mem_stat(void);
+#endif
+
+#if CONFIG_MULTI_CHAN
+/**
+ * Set multi-channel status disable/enable.
+ * \param[in]      status   multi channel status
+ * 0-disable, 1-enable
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_multi_chan_status(const int status);
+
+/**
+ * Get dynamic rapid channel switch status disable/enable.
+ * \param[out]      status  multi channel status
+ * 0-disable, 1-enable
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_multi_chan_status(int *status);
+
+/**
+ * Set dynamic rapid channel switch config.
+ * \param[in]      num       array length of drcs_cfg[]
+ * \param[in]     drcs_cfg   multi-channel config, maybe an array
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_drcs_cfg(const wlan_drcs_cfg_t *drcs_cfg, const int num);
+
+/**
+ * Get dynamic rapid channel switch config.
+ * \param[in]      num       array length of drcs_cfg[]
+ * \param[out] drcs_cfg  multi-channel config, maybe an array
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_drcs_cfg(wlan_drcs_cfg_t *drcs_cfg, int num);
+#endif
+
+#if CONFIG_11R
+/**
+ * Start FT roaming : This API is used to initiate fast BSS transition based
+ * roaming.
+ *
+ * \param[in] bssid       BSSID of AP to roam
+ * \param[in] channel     Channel of AP to roam
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_ft_roam(const t_u8 *bssid, const t_u8 channel);
+#endif
+
+/**
+ * This API can be used to start/stop the management frame forwards
+ * to host through datapath.
+ *
+ * \param[in] bss_type The interface from which management frame needs to be
+ *            collected 0: STA, 1: UAP
+
+ * \param[in] mgmt_subtype_mask     Management Subtype Mask
+ *            If Bit X is set in mask, it means that IEEE Management Frame
+ *            SubTyoe X is to be filtered and passed through to host.
+ *            Bit                   Description
+ *            [31:14]               Reserved
+ *            [13]                  Action frame
+ *            [12:9]                Reserved
+ *            [8]                   Beacon
+ *            [7:6]                 Reserved
+ *            [5]                   Probe response
+ *            [4]                   Probe request
+ *            [3]                   Reassociation response
+ *            [2]                   Reassociation request
+ *            [1]                   Association response
+ *            [0]                   Association request
+ *            Support multiple bits set.
+ *            0 = stop forward frame
+ *            1 = start forward frame
+ *\param[in] rx_mgmt_callback The receive callback where the received management
+ *           frames are passed.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ *
+ * \note Pass management subtype mask all zero to disable all the management
+ *       frame forward to host.
+ */
+int wlan_rx_mgmt_indication(const enum wlan_bss_type bss_type,
+                            const uint32_t mgmt_subtype_mask,
+                            int (*rx_mgmt_callback)(const enum wlan_bss_type bss_type,
+                                                    const wlan_mgmt_frame_t *frame,
+                                                    const size_t len));
+
+#if CONFIG_WMM
+void wlan_wmm_tx_stats_dump(int bss_type);
+#endif
+
+#if CONFIG_SCAN_CHANNEL_GAP
+/**
+ * Set scan channel gap.
+ * \param[in] scan_chan_gap      Time gap to be used between two consecutive channels scan.
+ *
+ */
+void wlan_set_scan_channel_gap(unsigned scan_chan_gap);
+#endif
+
+#if CONFIG_11K
+/**
+ * Enable/Disable host 802.11k feature.
+ *
+ * \param[in] enable_11k the value of 802.11k configuration.
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_host_11k_cfg(int enable_11k);
+
+/**
+ * Get enable/disable host 802.11k feature flag.
+ *
+ * \return TRUE if 802.11k is enabled, return FALSE if 802.11k is disabled.
+ *
+ */
+bool wlan_get_host_11k_status(void);
+
+/**
+ * Host send neighbor report request.
+ *
+ * \param[in] ssid The SSID for neighbor report
+ * \note ssid parameter is optional
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_host_11k_neighbor_req(const char *ssid);
+#endif
+
+#if CONFIG_11V
+/**
+ * Host send BSS transition management query.
+ *
+ * \param[in] query_reason BTM (BSS transition management) request query reason code.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_host_11v_bss_trans_query(t_u8 query_reason);
+#endif
+
+#if !CONFIG_WPA_SUPP
+#if CONFIG_DRIVER_MBO
+/**
+ * Enable/Disable MBO (multi band operation) feature.
+ *
+ * \param[in] enable_mbo The value of MBO configuration.
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_host_mbo_cfg(int enable_mbo);
+
+/**
+ * MBO channel operation preference configuration
+ *
+ * \param[in] ch0 Channel number.
+ * \param[in] prefer0 Operation preference for ch0.
+ * \param[in] ch1 Channel number.
+ * \param[in] prefer1 Operation preference for ch1.
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_mbo_peferch_cfg(t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1);
+#endif
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+int wlan_unassoc_ftm_cfg(const t_u16 action, const t_u16 config);
+
+/**
+ * Start or stop FTM (Wi-Fi fine time measurement) based on the command from CLI.
+ * \param[in] action 1: start FTM  2: stop FTM.
+ * \param[in] loop_cnt         number of FTM sessions to run repeatedly (default:1,  0: non-stop, n>1: n times).
+ * \param[in] MAC              MAC address of the peer with whom FTM session is required.
+ * \param[in] channel          Channel on which FTM is started.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_ftm_start_stop(const t_u16 action, const t_u8 loop_cnt, const t_u8 *mac, const t_u8 channel);
+
+/**
+ * Config FTM protocol.
+ * \param[in] protocol 0: Dot11mc, 1: Dot11az_ntb, 2: Dot11az_tb
+ * \param[in] ftm_ranging_cfg  FTM ranging config.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_ftm_cfg(const t_u8 protocol, ranging_11az_cfg_t *ftm_ranging_cfg);
+
+int wlan_ftm_11mc_cfg(ftm_11mc_nego_cfg_t *ftm_11mc_nego_cfg);
+
+int wlan_ftm_location_cfg(location_cfg_info_t *ftm_location_cfg);
+
+int wlan_ftm_civic_cfg(location_civic_rep_t *ftm_civic_cfg);
+
+extern location_cfg_info_t g_ftm_location_cfg;
+extern location_civic_rep_t g_ftm_civic_cfg;
+
+#endif
+
+#if CONFIG_WPA_SUPP
+#if (CONFIG_11AX && defined(CONFIG_MBO))
+/**
+ * Multi band pperation (MBO) non-preferred channels
+ *
+ * A space delimited list of non-preferred channels where each channel is a colon delimited list of values.
+ *
+ * Format:
+ *
+ * non_pref_chan=oper_class:chan:preference:reason
+ * Example:
+ *
+ * non_pref_chan=81:5:10:2 81:1:0:2 81:9:0:2
+ *
+ * \param[in] non_pref_chan list of non-preferred channels.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_mbo_peferch_cfg(const char *non_pref_chan);
+
+/**
+ * MBO set cellular data capabilities
+ *
+ * \param[in] cell_capa 1 = Cellular data connection available
+ * 2 = Cellular data connection not available
+ * 3 = Not cellular capable (default)
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_mbo_set_cell_capa(t_u8 cell_capa);
+
+/**
+ * Optimized connectivity experience (OCE)
+ *
+ * \param[in] oce Enable OCE features
+ * 1 = Enable OCE in non-AP STA mode (default; disabled if the driver
+ * does not indicate support for OCE in STA mode).
+ * 2 = Enable OCE in STA-CFON mode.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_mbo_set_oce(t_u8 oce);
+#endif
+
+/**
+ * Opportunistic key caching (also known as proactive key caching) default
+ * This parameter can be used to set the default behavior for the
+ * proactive_key_caching parameter. By default, OKC is disabled unless enabled
+ * with the global okc=1 parameter or with the per-network
+ * pkc(proactive_key_caching)=1 parameter. With okc=1, OKC is enabled by default, but
+ * can be disabled with per-network pkc(proactive_key_caching)=0 parameter.
+ *
+ * \param[in] okc Enable opportunistic key caching
+ *
+ * 0 = Disable OKC (default)
+ * 1 = Enable OKC
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_okc(t_u8 okc);
+
+/**
+ * Dump text list of entries in PMKSA (pairwise master key security association) cache.
+ *
+ * \param[out] buf Buffer to save PMKSA cache text list
+ * \param[in] buflen length of the buffer
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_pmksa_list(char *buf, size_t buflen);
+
+/**
+ * Flush PTKSA cache entries
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_pmksa_flush(void);
+
+/**
+ * Set wpa supplicant scan interval in seconds
+ *
+ * \param[in] scan_int Scan interval in seconds
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_scan_interval(int scan_int);
+#endif
+
+
+#if CONFIG_ECSA
+/**
+ * Send the ecsa config parameter to FW.
+ *
+ *\param[in] block_tx      0 -- no need to block traffic,1 -- need block traffic.
+ *\param[in] oper_class    Operating class according to IEEE std802.11 spec, refer to Annex E,
+ *                         when 0 is used, automatically get operclass through band_width and channel.
+ *\param[in] channel       The channel can switch to.
+ *\param[in] switch_count  Channel switch time to send ECSA ie, unit is 110ms.
+ *\param[in] band_width    Channel width switch to(optional), only for 5G channels.
+ *                         Depends on the hardware capabilities, when the hardware does not support, it can
+ *automatically downgrade. Redfinch support 20M. 0 -- 20MHZ, 1 -- 40M above, 3 -- 40M below, 4 -- 80M, 5 -- 160M
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_uap_set_ecsa_cfg(t_u8 block_tx, t_u8 oper_class, t_u8 channel, t_u8 switch_count, t_u8 band_width);
+#endif
+
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+
+/** Type enum definition of subscribe event */
+typedef enum
+{
+    /** Event Id for subscribe event RSSI low */
+    EVENT_SUB_RSSI_LOW = 0,
+    /** Event Id for subscribe event RSSI high */
+    EVENT_SUB_RSSI_HIGH,
+    /** Event Id for subscribe event snr low */
+    EVENT_SUB_SNR_LOW,
+    /** Event Id for subscribe event snr high */
+    EVENT_SUB_SNR_HIGH,
+    /** Event Id for subscribe event max fail */
+    EVENT_SUB_MAX_FAIL,
+    /** Event Id for subscribe event beacon missed */
+    EVENT_SUB_BEACON_MISSED,
+    /** Event Id for subscribe event data RSSI low */
+    EVENT_SUB_DATA_RSSI_LOW,
+    /** Event Id for subscribe event data RSSI high */
+    EVENT_SUB_DATA_RSSI_HIGH,
+    /** Event Id for subscribe event data snr low */
+    EVENT_SUB_DATA_SNR_LOW,
+    /** Event Id for subscribe event data snr high */
+    EVENT_SUB_DATA_SNR_HIGH,
+    /** Event Id for subscribe event link quality */
+    EVENT_SUB_LINK_QUALITY,
+    /** Event Id for subscribe event pre_beacon_lost */
+    EVENT_SUB_PRE_BEACON_LOST,
+    /** Fail event id */
+    MAX_EVENT_ID,
+} sub_event_id;
+
+/** Type definition of wlan_ds_subscribe_evt for subscribe events */
+typedef wifi_ds_subscribe_evt wlan_ds_subscribe_evt;
+
+/**
+ * Subscribe specified event from the Wi-Fi firmware. Wi-Fi firmware report the registered event to driver upon
+ * configured report conditions are met.
+ * \param[in] event_id event to register as per \ref sub_event_id
+ * \param[in] thresh_value the RSSI threshold value (dBm)
+ * \param[in] freq     event frequency 0--report once, 1--report everytime happened, N --
+ *                     report only happened > N consecutive times.
+ * \return WM_SUCCESS if set successfully, otherwise return failure.
+ */
+int wlan_set_subscribe_event(unsigned int event_id, unsigned int thresh_value, unsigned int freq);
+/**
+ * Get all subscribed events from Wi-Fi firmware along with threshold value and report frequency.
+ * \param[in] sub_evt A pointer to \ref wlan_ds_subscribe_evt to store the events data.
+ */
+int wlan_get_subscribe_event(wlan_ds_subscribe_evt *sub_evt);
+/**
+ * cancel the subscribe event to firmware
+ * \param[in] event_id event id to clear as per \ref sub_event_id
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_clear_subscribe_event(unsigned int event_id);
+/**
+ * subscibe link quality event
+ * \param[in] event_id event id to clear as per \ref sub_event_id
+ * \param[in] link_snr link quality snr value
+ * \param[in] link_snr_freq link quality snr freq
+ * \param[in] link_rate link quality rate
+ * \param[in] link_rate_freq link quality rate freq
+ * \param[in] link_tx_latency link quality write lantency
+ * \param[in] link_tx_lantency_freq link quality write lantency freq
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_threshold_link_quality(unsigned int evend_id,
+                                    unsigned int link_snr,
+                                    unsigned int link_snr_freq,
+                                    unsigned int link_rate,
+                                    unsigned int link_rate_freq,
+                                    unsigned int link_tx_latency,
+                                    unsigned int link_tx_lantency_freq);
+#endif
+
+#if CONFIG_TSP
+/**
+ * get TSP (thermal safeguard protection) configuration.
+ * TSP algorithm moniters PA Tj and primarily backs off data throughput.
+ * \param[out] enable            Enable/Disable TSP algothrim
+ * \param[out] back_off          Power back off   [0...20]dB
+ * \param[out] highThreshold     High threshold  [0...300]°C
+ * \param[out] lowThreshold      Low threshold   [0...300]°C
+ *             High Threshold is Greater than low threshold.
+ * \param[out] dutycycstep       Duty cycle step(percentage)
+ * \param[out] dutycycmin        Duty cycle min(percentage)
+ * \param[out] highthrtemp       High throttle threshold temperature(celsius)
+ * \param[out] lowthrtemp        Low throttle threshold temperature(celsius)
+ * \param[out] currCAUTemp       CAU TSEN temperature
+ * \param[out] currRFUTemp       RFU temperature
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_tsp_cfg(t_u16 *enable,
+                     t_u32 *back_off,
+                     t_u32 *highThreshold,
+                     t_u32 *lowThreshold,
+                     t_u32 *dutycycstep,
+                     t_u32 *dutycycmin,
+                     int *highthrtemp,
+                     int *lowthrtemp,
+                     int *currCAUTemp,
+                     int *currRFUTemp);
+
+/**
+ * Set TSP (thermal safeguard protection) configuration.
+ * TSP algorithm moniters and primarily backs off data throughput.
+ * \param[in] enable            Enable/Disable tsp algothrim
+ * \param[in] back_off          Power back off   [0...20]dB
+ * \param[in] highThreshold     High threshold  [0...300]°C
+ * \param[in] lowThreshold      Low threshold   [0...300]°C
+ *                              High threshold is greater than low threshold.
+ * \param[in] dutycycstep       Duty cycle step(percentage)
+ * \param[in] dutycycmin        Duty cycle min(percentage)
+ * \param[out] highthrtemp      High throttle threshold temperature (celsius)
+ * \param[out] lowthrtemp       Low throttle threshold temperature (celsius)
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_tsp_cfg(t_u16 enable,
+                     t_u32 back_off,
+                     t_u32 highThreshold,
+                     t_u32 lowThreshold,
+                     t_u32 dutycycstep,
+                     t_u32 dutycycmin,
+                     int highthrtemp,
+                     int lowthrtemp);
+#endif
+
+#if CONFIG_WIFI_REG_ACCESS
+/** This function reads/writes adapter registers value.
+ *
+ *\param[in]        type        Register type: 1 -- MAC, 2 -- BBP, 3 -- RF.
+ *\param[in]        action      0 -- read, 1 -- write
+ *\param[in]        offset      Specifies the offset location that is to be read/write.
+ *\param[in,out]    value       Value if specified, stand for write action, then that value can be written to that
+ *                              offset in the specified register. Value should be specified in hexadecimal. Otherwise,
+ *                              it stands for read action, the
+ *value is updated with read value.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_reg_access(wifi_reg_t type, uint16_t action, uint32_t offset, uint32_t *value);
+#endif
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+/**
+ * Set/Get TX AMPDU protect mode.
+ *
+ * \param[in,out] prot_mode    TX AMPDU protect mode
+ * \param[in]     action       Command action
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_tx_ampdu_prot_mode(tx_ampdu_prot_mode_para *prot_mode, t_u16 action);
+#endif
+
+struct wlan_message
+{
+    t_u16 id;
+    void *data;
+};
+
+enum wlan_mef_type
+{
+    MEF_TYPE_DELETE = 0,
+    MEF_TYPE_PING,
+    MEF_TYPE_ARP,
+    MEF_TYPE_MULTICAST,
+    MEF_TYPE_IPV6_NS,
+    MEF_TYPE_END,
+};
+/** This function set auto ARP configuration.
+ *
+ * \param[in] mef_action  To be 0--discard and not wake host, 1--discard and wake host 3--allow and wake host.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_mef_set_auto_arp(t_u8 mef_action);
+/** This function set auto ping configuration.
+ *
+ * \param[in] mef_action  To be 0--discard and not wake host, 1--discard and wake host 3--allow and wake host.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ *
+ */
+int wlan_mef_set_auto_ping(t_u8 mef_action);
+/** This function set/delete MEF entries configuration.
+ *
+ * \param[in] type        MEF type: MEF_TYPE_DELETE, MEF_TYPE_AUTO_PING, MEF_TYPE_AUTO_ARP
+ * \param[in] mef_action  To be 0--discard and not wake host, 1--discard and wake host 3--allow and wake host.
+ *
+ * \return WM_SUCCESS if the call was successful.
+ * \return -WM_FAIL if failed.
+ */
+int wlan_config_mef(int type, t_u8 mef_action);
+/**
+ * Use this API to enable IPv6 neighbor solicitation offload in Wi-Fi firmware.
+ *
+ * \param[in] mef_action  0--discard and not wake host, 1--discard and wake host 3--allow and wake host.
+ *
+ * \return WM_SUCCESS if operation is successful.
+ * \return -WM_FAIL if command fails.
+ */
+int wlan_set_ipv6_ns_mef(t_u8 mef_action);
+
+#if CONFIG_CSI
+/**
+ * Send the CSI config parameter to firmware.
+ *
+ *\param[in] csi_params CSI config parameter
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_csi_cfg(wlan_csi_config_params_t *csi_params);
+
+/** This function registers callback which are used to deliver CSI (channel state information) data to user.
+ *
+ * \param[in] csi_data_recv_callback Callback to deliver CSI data and max data length is 768 bytes.
+ * Pls save data as soon as possible in callback
+ * Type of callback return vale is int.
+ *
+ *          Memory layout of buffer:
+ *          size(byte)                         items
+ *          2                                  buffer len[bit 0:12]
+ *          2                                  CSI signature, 0xABCD fixed
+ *          4                                  User defined HeaderID
+ *          2                                  Packet info
+ *          2                                  Frame control field for the received packet
+ *          8                                  Timestamp when packet received
+ *          6                                  Received packet destination MAC Address
+ *          6                                  Received packet source MAC address
+ *          1                                  RSSI for antenna A
+ *          1                                  RSSI for antenna B
+ *          1                                  Noise floor for antenna A
+ *          1                                  Noise floor for antenna B
+ *          1                                  RX signal strength above noise floor
+ *          1                                  Channel
+ *          2                                  user defined chip ID
+ *          4                                  Reserved
+ *          4                                  CSI data length in DWORDs
+ *                                             CSI data
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_register_csi_user_callback(int (*csi_data_recv_callback)(void *buffer, size_t len));
+
+/** This function unregisters callback which are used to deliver CSI data to user.
+ *
+ * \return  WM_SUCCESS if successful
+ */
+int wlan_unregister_csi_user_callback(void);
+/** This function get CSI default configuration data.
+ *
+ * \return CSI data pointer.
+ */
+wlan_csi_config_params_t *wlan_get_csi_cfg_param_default(void);
+/** This function set CSI default configuration data.
+ *
+ * \param[in] in_csi_cfg CSI default configuration data to be set.
+ *
+ * \return if successful return 1 else return 0.
+ */
+int wlan_set_csi_cfg_param_default(wlan_csi_config_params_t *in_csi_cfg);
+
+/**
+ * This function reset Wi-Fi CSI filter data.
+ */
+void wlan_reset_csi_filter_data(void);
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_11R) || (CONFIG_ROAMING)
+/**
+ * Use this API to set the RSSI threshold value for low RSSI event subscription.
+ * When RSSI falls below this threshold firmware can generate the low RSSI event to driver.
+ * This low RSSI event is used when either of CONFIG_11R, CONFIG_11K, CONFIG_11V or CONFIG_ROAMING is enabled.
+ * NOTE: By default RSSI low threshold is set at -70 dbm
+ *
+ * \param[in]     threshold      Threshold RSSI value to be set
+ *
+ */
+void wlan_set_rssi_low_threshold(uint8_t threshold);
+#endif
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+/**
+ *  This function generate pin for WPS pin session.
+ *
+ * \param[in]  pin A pointer to WPS pin to be generated.
+ */
+void wlan_wps_generate_pin(uint32_t *pin);
+
+/** Start WPS pin session.
+ *
+ *  This function starts WPS pin session.
+ *
+ * \param[in]  pin Pin for WPS session.
+ *
+ * \return WM_SUCCESS if the pin entered is valid.
+ * \return -WM_FAIL if invalid pin entered.
+ */
+int wlan_start_wps_pin(const char *pin);
+
+/** Start WPS PBC (push button configuration) session.
+ *
+ *  This function starts WPS PBC (push button configuration) session.
+ *
+ * \return  WM_SUCCESS if successful
+ * \return -WM_FAIL if invalid pin entered.
+ *
+ */
+int wlan_start_wps_pbc(void);
+
+/** Cancel WPS session.
+ *
+ *  This function cancels ongoing WPS session.
+ *
+ * \return  WM_SUCCESS if successful
+ * \return -WM_FAIL if invalid pin entered.
+ *
+ */
+int wlan_wps_cancel(void);
+
+#if CONFIG_WPA_SUPP_AP
+/** Start WPS pin session.
+ *
+ *  This function starts AP WPS pin session.
+ *
+ * \param[in] pin Pin for WPS session.
+ *
+ * \return WM_SUCCESS if the pin entered is valid.
+ * \return -WM_FAIL if invalid pin entered.
+ */
+int wlan_start_ap_wps_pin(const char *pin);
+
+/** Start WPS PBC session.
+ *
+ *  This function starts AP WPS PBC session.
+ *
+ * \return  WM_SUCCESS if successful
+ * \return -WM_FAIL if invalid pin entered.
+ *
+ */
+int wlan_start_ap_wps_pbc(void);
+
+/** Cancel AP's WPS session.
+ *
+ *  This function cancels ongoing WPS session.
+ *
+ * \return  WM_SUCCESS if successful
+ * \return -WM_FAIL if invalid pin entered.
+ *
+ */
+int wlan_wps_ap_cancel(void);
+#endif
+#endif
+#endif
+
+#if (CONFIG_WPA2_ENTP) || (CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#define FILE_TYPE_NONE              0
+#define FILE_TYPE_ENTP_CA_CERT      1
+#define FILE_TYPE_ENTP_CLIENT_CERT  2
+#define FILE_TYPE_ENTP_CLIENT_KEY   3
+#define FILE_TYPE_ENTP_CA_CERT2     4
+#define FILE_TYPE_ENTP_CLIENT_CERT2 5
+#define FILE_TYPE_ENTP_CLIENT_KEY2  6
+
+#if CONFIG_HOSTAPD
+#define FILE_TYPE_ENTP_SERVER_CERT 8
+#define FILE_TYPE_ENTP_SERVER_KEY  9
+#define FILE_TYPE_ENTP_DH_PARAMS   10
+#endif
+
+/** This function specifies the enterprise certificate file
+ *  This function is used before adding network profile. It can store certificate data
+ *  in "wlan" global structure. When adding new network profile, it can be get by
+ *  wlan_get_entp_cert_files(), and put into profile security structure after mbedtls parse.
+ *
+ * \param[in]        cert_type   certificate file type:
+ * 1 -- FILE_TYPE_ENTP_CA_CERT,
+ * 2 -- FILE_TYPE_ENTP_CLIENT_CERT,
+ * 3 -- FILE_TYPE_ENTP_CLIENT_KEY.
+ * \param[in]        data        raw data
+ * \param[in]        data_len    size of raw data
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_entp_cert_files(int cert_type, t_u8 *data, t_u32 data_len);
+
+/** This function get enterprise certificate data from "wlan" global structure           *
+ * \param[in]        cert_type   certificate file type:
+ * 1 -- FILE_TYPE_ENTP_CA_CERT,
+ * 2 -- FILE_TYPE_ENTP_CLIENT_CERT,
+ * 3 -- FILE_TYPE_ENTP_CLIENT_KEY.
+ * \param[in]        data        raw data
+ *
+ * \return size of raw data
+ */
+t_u32 wlan_get_entp_cert_files(int cert_type, t_u8 **data);
+
+/** This function free the temporary memory of enterprise certificate data
+ *  After add new enterprise network profile, the certificate data has been parsed by mbedtls into another data, which
+ * can be freed.
+ *
+ */
+void wlan_free_entp_cert_files(void);
+#endif
+
+#if CONFIG_NET_MONITOR
+/**
+ * Send the net monitor config parameter to firmware.
+ *
+ *\param[in] monitor Monitor config parameter
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_net_monitor_cfg(wlan_net_monitor_t *monitor);
+
+/** This function registers callback which are used to deliver monitor data to user.
+ *
+ * \param[in] monitor_data_recv_callback Callback to deliver monitor data and data length to user.
+ *          Memory layout of buffer:
+ *          offset(byte)                        items
+ *          0                                   rssi
+ *          1                                   802.11 MAC header
+ *          1 + 'size of 802.11 MAC header'     frame body
+ *
+ * \return void
+ */
+void wlan_register_monitor_user_callback(int (*monitor_data_recv_callback)(void *buffer, t_u16 data_len));
+
+/** This function deregisters monitor callback.
+ *
+ * \return void
+ */
+void wlan_deregister_net_monitor_user_callback(void);
+#endif
+
+#if CONFIG_WIFI_CAPA
+/** Check if 802.11n (2G or 5G) is supported by hardware or not.
+ *
+ * \param[in] channel Channel number.
+ *
+ * \return true if 802.11n is supported or false if not.
+ */
+uint8_t wlan_check_11n_capa(unsigned int channel);
+
+/** Check if 802.11ac (2G or 5G) is supported by hardware or not.
+ *
+ * \param[in] channel Channel number.
+ *
+ * \return true if 802.11ac is supported or false if not.
+ */
+uint8_t wlan_check_11ac_capa(unsigned int channel);
+
+/** Check if 11ax(2G or 5G) is supported by hardware or not.
+ *
+ * \param[in] channel Channel number.
+ *
+ * \return true if 802.11ax is supported or false if not.
+ */
+uint8_t wlan_check_11ax_capa(unsigned int channel);
+#endif
+
+#if (CONFIG_IPS)
+/**
+ * Config IEEE power save mode (IPS). If the option is 1, the IPS hardware listens to beacon frames after Wi-Fi CPU enters
+ * power save mode. When there is work needed to done by Wi-Fi CPU, Wi-Fi CPU can be woken up by ips hardware. \param[in]
+ * option    0/1  disable/enable ips
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_ips(int option);
+#endif
+
+/**
+ * Get RSSI information.
+ * \param[out] signal    RSSI infomation get report buffer
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_signal_info(wlan_rssi_info_t *signal);
+
+/**
+ * Set band configuration.
+ * \param[in] bandcfg    band configureation
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_bandcfg(wlan_bandcfg_t *bandcfg);
+
+/**
+ * Get band configuration.
+ * \param[out] bandcfg    band configureation
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_bandcfg(wlan_bandcfg_t *bandcfg);
+
+#if CONFIG_COMPRESS_TX_PWTBL
+/**
+ * set region power table
+ * \param[in] region_code region code
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_rg_power_cfg(t_u16 region_code);
+#endif
+
+#if (CONFIG_COMPRESS_RU_TX_PWTBL) && (CONFIG_11AX)
+/**
+ * set ru tx power table
+ * \param[in] region_code region code
+ * \return WM_SUCCESS if successful otherwise failure.
+ */
+int wlan_set_ru_power_cfg(t_u16 region_code);
+#endif
+
+#if CONFIG_TURBO_MODE
+/**
+ * Get Turbo mode.
+ * \param[out] mode    turbo mode
+ *                          0: disable turbo mode
+ *                          1: turbo mode 1
+ *                          2: turbo mode 2
+ *                          3: turbo mode 3
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_turbo_mode(t_u8 *mode);
+
+/**
+ * Get UAP turbo mode.
+ * \param[out] mode    turbo mode
+ *                          0: disable turbo mode
+ *                          1: turbo mode 1
+ *                          2: turbo mode 2
+ *                          3: turbo mode 3
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_uap_turbo_mode(t_u8 *mode);
+
+/**
+ * Set turbo mode.
+ * \param[in] mode    turbo mode
+ *                          0: disable turbo mode
+ *                          1: turbo mode 1
+ *                          2: turbo mode 2
+ *                          3: turbo mode 3
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_turbo_mode(t_u8 mode);
+
+/**
+ * Set UAP turbo mode.
+ * \param[in] mode    turbo mode
+ *                          0: disable turbo mode
+ *                          1: turbo mode 1
+ *                          2: turbo mode 2
+ *                          3: turbo mode 3
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_uap_turbo_mode(t_u8 mode);
+#endif
+
+/**
+ * set ps configuration.
+ * Currently only used to modify multiple dtim.
+ * \param[in] multiple_dtims        num dtims, range [1,20]
+ * \param[in] bcn_miss_timeout      becaon miss interval
+ * \param[in] local_listen_interval local listen interval
+ * \param[in] adhoc_wake_period     adhoc awake period
+ * \param[in] mode                  mode - (0x01 - firmware to automatically choose PS_POLL or NULL mode,
+ *                                          0x02 - PS_POLL,
+ *                                          0x03 - NULL mode )
+ * \param[in] delay_to_ps           Delay to PS in milliseconds
+ */
+void wlan_set_ps_cfg(t_u16 multiple_dtims,
+                     t_u16 bcn_miss_timeout,
+                     t_u16 local_listen_interval,
+                     t_u16 adhoc_wake_period,
+                     t_u16 mode,
+                     t_u16 delay_to_ps);
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+/**
+ * Save start cloud keep alive parameters
+ *
+ * \param[in] cloud_keep_alive    cloud keep alive information
+ * \param[in] src_port Source port
+ * \param[in] dst_port Destination port
+ * \param[in] seq_number Sequence number
+ * \param[in] ack_number Acknowledgement number
+ * \param[in] enable Enable
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_save_cloud_keep_alive_params(wlan_cloud_keep_alive_t *cloud_keep_alive,
+                                      t_u16 src_port,
+                                      t_u16 dst_port,
+                                      t_u32 seq_number,
+                                      t_u32 ack_number,
+                                      t_u8 enable);
+
+/**
+ * Get cloud keep alive status for given destination ip and port
+ *
+ * \param[in] dst_ip Destination ip address
+ * \param[in] dst_port Destination port
+ *
+ * \return 1 if enabled otherwise 0.
+ */
+int wlan_cloud_keep_alive_enabled(t_u32 dst_ip, t_u16 dst_port);
+
+/**
+ * Start cloud keep alive
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_start_cloud_keep_alive(void);
+/**
+ * Stop cloud keep alive
+ * \param[in] cloud_keep_alive    cloud keep alive information
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_stop_cloud_keep_alive(wlan_cloud_keep_alive_t *cloud_keep_alive);
+#endif
+
+/**
+ * Set country code
+ *
+ * \note This API should be called after Wi-Fi is initialized
+ * but before starting UAP interface.
+ *
+ * \param[in] alpha2 country code in 3 octets string, 2 octets country code and 1 octet environment
+ *            2 octets country code supported:
+ *            WW : World Wide Safe
+ *            US : US FCC
+ *            CA : IC Canada
+ *            SG : Singapore
+ *            EU : ETSI
+ *            AU : Australia
+ *            KR : Republic Of Korea
+ *            FR : France
+ *            JP : Japan
+ *            CN : China
+ *
+ * For the third octet, STA is always 0.
+ * for UAP environment:
+ * All environments of the current frequency band and country (default)
+ * alpha2[2]=0x20
+ * Outdoor environment only
+ * alpha2[2]=0x4f
+ * Indoor environment only
+ * alpha2[2]=0x49
+ * Noncountry entity (country_code=XX)
+ * alpha[2]=0x58
+ * IEEE 802.11 standard Annex E table indication: 0x01 .. 0x1f
+ * Annex E, Table E-4 (Global operating classes)
+ * alpha[2]=0x04
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_country_code(const char *alpha2);
+
+/** Set ignore region code.
+ *
+ * \param[in] ignore     0: don't ignore, 1: ignore
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_country_ie_ignore(uint8_t *ignore);
+
+/** Set region code.
+ *
+ * \param[in] region_code region code to be set.
+ * \return WM_SUCCESS if successful otherwise fail.
+ */
+int wlan_set_region_code(unsigned int region_code);
+
+/** Get region code.
+ *
+ * \param[out] region_code pointer
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_region_code(unsigned int *region_code);
+
+/** Set STA/UAP 802.11d feature Enable/Disable.
+ *
+ * \param[in] bss_type 0: STA, 1: UAP
+ * \param[in] state    0: disable, 1: enable
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_11d_state(int bss_type, int state);
+
+#if CONFIG_COEX_DUTY_CYCLE
+/**
+ * Set single ant duty cycle.
+ * \param[in] enable
+ * \param[in] nbTime
+ * \param[in] wlanTime
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_single_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime);
+
+/**
+ * Set dual ant duty cycle.
+ * \param[in] enable
+ * \param[in] nbTime
+ * \param[in] wlanTime
+ * \param[in] wlanBlockTime
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dual_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime, t_u16 wlanBlockTime);
+#endif
+
+#if CONFIG_EXTERNAL_COEX_PTA
+/**
+ * Set external coex PTA (packet traffic arbitration) parameters.
+ * \param[in] coex_pta_config
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_external_coex_pta_cfg(ext_coex_pta_cfg coex_pta_config);
+#endif
+
+#if CONFIG_WPA_SUPP_DPP
+/** Add a DPP (device provisioning protocol) configurator.
+ *
+ *  If this device is DPP configurator, add it to get configurator ID.
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      "curve=P-256"
+ *
+ * \return configurator ID if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_configurator_add(int is_ap, const char *cmd);
+
+/** Set DPP (device provisioning protocol) configurator parameter
+ *
+ *  set DPP configurator params.
+ *  for example:" conf=<sta-dpp/ap-dpp> ssid=<hex ssid> configurator=conf_id"
+ *  #space character exists between " & conf word.
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      " conf=<sta-dpp/ap-dpp/sta-psk> ssid=<hex ssid> configurator=conf_id..."
+ *
+ * \return void
+ */
+void wlan_dpp_configurator_params(int is_ap, const char *cmd);
+
+/** MUD URL for enrollee's DPP configuration request (optional)
+ *
+ *  Wi-Fi_CERTIFIED_Easy_Connect_Test_Plan_v3.0.pdf
+ *  5.1.23 STAUT sends the MUD URL
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      "https://example.com/mud"
+ *
+ * \return void
+ */
+void wlan_dpp_mud_url(int is_ap, const char *cmd);
+
+/** Generate QR code.
+ *
+ *  This function generates QR code and return bootstrap-id
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      "type=qrcode mac=<mac-address-of-device> chan=<operating-class/channel>..."
+ *
+ * \return bootstrap-id if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_bootstrap_gen(int is_ap, const char *cmd);
+
+/** Get QR code by bootstrap-id.
+ *
+ *  This function get QR code string by bootstrap-id
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  id       bootstrap-id
+ *
+ * \return QR code string if successful otherwise NULL.
+ */
+const char *wlan_dpp_bootstrap_get_uri(int is_ap, unsigned int id);
+
+/** Enter the QR code in the DPP device.
+ *
+ *  This function set the QR code and return qr-code-id.
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP
+ * \param[in]  uri      QR code provided by other device.
+ *
+ * \return qr-code-id if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_qr_code(int is_ap, char *uri);
+
+/** Send provisioning auth request to responder.
+ *
+ *  This function send Auth request to responder by qr-code-id.
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      " peer=<qr-code-id> conf=<sta-dpp/ap-dpp/sta-psk> ...."
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_auth_init(int is_ap, const char *cmd);
+
+/** Make device listen to DPP request.
+ *
+ *  Responder generates QR code and listening on its operating channel to wait Auth request.
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      "<frequency>"
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_listen(int is_ap, const char *cmd);
+
+/** DPP stop listen.
+ *
+ *  Stop dpp listen and clear listen frequency
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_stop_listen(int is_ap);
+
+/** Set bootstrapping through PKEX (Public Key Exchange).
+ *
+ *  Support in-band bootstrapping through PKEX
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      "own=<bootstrap_id> identifier=<string> code=<string>"
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_pkex_add(int is_ap, const char *cmd);
+
+/** sends DPP presence announcement.
+ *
+ *  Send DPP presence announcement from responder.
+ *  After the Initiator enters the QRcode URI provided by the Responder,
+ *  the Responder sends the presence announcement to trigger Auth Request from Initiator.
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP.
+ * \param[in]  cmd      "own=<bootstrap id> listen=<freq> ..."
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_chirp(int is_ap, const char *cmd);
+
+/** DPP reconfig.
+ *
+ *  DPP reconfig and make a new DPP connection.
+ *
+ * \param[in]  cmd      "<network id> ..."
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_reconfig(const char *cmd);
+
+/** Configurator configures itself as an Enrollee AP/STA.
+ *
+ *  Wi-Fi_CERTIFIED_Easy_Connect_Test_Plan_v3.0.pdf
+ *  5.3.8 & 5.3.9 Configurator configures itself as an Enrollee AP/STA
+ *
+ *  for example:" conf=<sta-dpp/ap-dpp> ssid=<hex ssid> configurator=conf_id"
+ *  #space character exists between " & conf word.
+ *
+ * \param[in]  is_ap    0 is STA, 1 is UAP
+ * \param[in]  cmd      " conf=<sta-dpp/ap-dpp/sta-psk> ssid=<hex ssid> configurator=conf_id..."
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_dpp_configurator_sign(int is_ap, const char *cmd);
+#endif
+
+#if CONFIG_IMD3_CFG
+/**
+ * Set imd validation parameters.
+ * \param[in] imd3_value   disable imd3: imd3_value = 0;
+ *                         enable imd3: low 4 bits: enable, high 4 bits: isolation index.
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_imd3_cfg(t_u8 imd3_value);
+#endif
+
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+int wlan_host_set_sta_mac_filter(int filter_mode, int mac_count, unsigned char *mac_addr);
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+/**
+ * Set GPIO independent reset configuration
+ *
+ * \param[in] indrst_cfg GPIO independent reset config to be sent to firmware
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_set_indrst_cfg(const wifi_indrst_cfg_t *indrst_cfg);
+
+/* Get GPIO independent reset configuration
+ *
+ * \param[out] indrst_cfg GPIO independent reset config set in Firmware
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_get_indrst_cfg(wifi_indrst_cfg_t *indrst_cfg);
+
+/** Test independent firmware reset
+ *
+ * This function can either send cmd that can cause timeout in firmware or
+ * send GPIO pulse that can cause out of band reset in firmware as per configuration
+ * int earlier \ref wlan_set_indrst_cfg API.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_independent_reset(void);
+
+#endif
+
+int wlan_set_network_ip_byname(char *name, struct wlan_ip_config *ip);
+
+#if CONFIG_INACTIVITY_TIMEOUT_EXT
+/**
+ * Get/Set inactivity timeout extend
+ * \param[in] inac_to
+ * \param[in] action
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_sta_inactivityto(wlan_inactivity_to_t *inac_to, t_u16 action);
+#endif
+
+/**
+ * Get 802.11 Status Code.
+ *
+ * \param[in] reason wlcmgr event reason
+ *
+ * \return status code defined in IEEE 802.11-2020 standard.
+ */
+t_u16 wlan_get_status_code(enum wlan_event_reason reason);
+
+#ifdef RW610
+/**
+ * Get board temperature.
+ * \return board temperature.
+ */
+int32_t wlan_get_temperature(void);
+#endif
+
+#if CONFIG_CPU_LOADING
+/**
+ * Set parameters for cpu loading test.
+ *
+ * \param[in]  start    0 stop test, 1 start test.
+ * \param[in]  number   The number of cpu loading test.
+ * \param[in]  period   The period of cpu loading test.
+ *
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_cpu_loading(uint8_t start, uint32_t number, uint8_t period);
+#endif
+
+#if CONFIG_AUTO_NULL_TX
+/** Configuration for auto null TX parameters from
+ * \ref wifi_auto_null_tx_t
+ */
+typedef wifi_auto_null_tx_t wlan_auto_null_tx_t;
+
+/**
+ * Start/Stop auto TX null.
+ *
+ * \param[in]  auto_null_tx  auto null RX information
+ * \param[in]  bss_type      0: station; 1: UAP
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_auto_null_tx(wlan_auto_null_tx_t *auto_null_tx, mlan_bss_type bss_type);
+#endif
+
+/**
+ * allocate a copy of a string
+ *
+ * \param[in,out] s the source/target string
+ * \return new string if successful, otherwise return -WM_FAIL.
+ */
+char *wlan_string_dup(const char *s);
+
+/**
+ * Get board type.
+ *
+ * \return board type.
+ */
+uint32_t wlan_get_board_type(void);
+
+/**
+ * Disconnect to STA which is connected with internal UAP.
+ *
+ * \param[in]  sta_addr    STA MAC address
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_uap_disconnect_sta(uint8_t *sta_addr);
+
+/**
+ * Check if 802.11n is allowed in capability.
+ *
+ * \param[in]  network    A pointer to the \ref wlan_network
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_11n_allowed(struct wlan_network *network);
+
+#if CONFIG_11AC
+/**
+ * Check if 802.11ac is allowed in capability.
+ *
+ * \param[in]  network    A pointer to the \ref wlan_network
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_11ac_allowed(struct wlan_network *network);
+#endif
+
+#if CONFIG_11AX
+/**
+ * Check if 802.11ax is allowed in capability.
+ *
+ * \param[in]  network    A pointer to the \ref wlan_network
+ * \return WM_SUCCESS if successful otherwise return -WM_FAIL.
+ */
+int wlan_11ax_allowed(struct wlan_network *network);
+#endif
+#endif /* __WLAN_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wlcmgr/wlan_11d.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wlcmgr/wlan_11d.h
new file mode 100644
index 0000000000..e431f0d42d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wlcmgr/wlan_11d.h
@@ -0,0 +1,55 @@
+/*
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*! \file wlan_11d.h
+ * \brief This file provides 802.11d interfaces.
+ */
+
+#ifndef __WLAN_11D_H__
+#define __WLAN_11D_H__
+
+#include <wifi.h>
+
+/** Enable 11D support in WLAN Driver.
+ *
+ * \note This API should be called after WLAN is initialized
+ * but before starting uAP or making any connection attempts on station
+ * interface.
+ *
+ * \param[in] state 1: enable, 0: disable
+ *
+ * \return -WM_FAIL if operation was failed.
+ * \return WM_SUCCESS if operation was successful.
+ */
+static inline int wlan_enable_11d(int state)
+{
+    if (state)
+        return wifi_enable_11d_support();
+    else
+        return wifi_disable_11d_support();
+}
+
+/** Enable 11D support in WLAN Driver for uap interface.
+ *
+ * \note This API should be called after WLAN is initialized
+ * but before starting uAP or making any connection attempts on station
+ * interface.
+ *
+ * \param[in] state 1: enable, 0: disable
+ *
+ * \return -WM_FAIL if operation was failed.
+ * \return WM_SUCCESS if operation was successful.
+ */
+static inline int wlan_enable_uap_11d(int state)
+{
+    if (state)
+        return wifi_enable_uap_11d_support();
+    else
+        return wifi_disable_uap_11d_support();
+}
+
+#endif /* __WLAN_11D_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wm_utils.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wm_utils.h
new file mode 100644
index 0000000000..2df975118d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wm_utils.h
@@ -0,0 +1,437 @@
+/*
+ *  Copyright 2008-2022, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*!\file wm_utils.h
+ *\brief This file provides utility functions for Wi-Fi connection manager.
+ *
+ * Utility functions
+ */
+
+#ifndef _UTIL_H_
+#define _UTIL_H_
+
+#include <wifi_config_default.h>
+#include <wmtypes.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <ctype.h>
+#ifdef __ZEPHYR__
+#include <zephyr/kernel.h>
+#include <strings.h>
+#else
+#include "fsl_debug_console.h"
+#endif
+
+#if CONFIG_WIFI_SMOKE_TESTS
+#if defined(SDK_OS_FREE_RTOS)
+
+#undef PRINTF
+extern void sm_printf(const char *fmt, ...);
+
+#define PRINTF sm_printf
+#elif __ZEPHYR__
+#endif
+#endif
+
+#ifdef __ZEPHYR__
+#ifndef PRINTF
+#define PRINTF printk
+#endif
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE CONFIG_WIFI_EXTRA_DEBUG
+#endif
+#endif
+
+#define ffs __builtin_ffs
+
+#ifdef __GNUC__
+#define WARN_UNUSED_RET __attribute__((warn_unused_result))
+
+#ifndef PACK_START
+#define PACK_START
+#endif
+#ifndef PACK_END
+#define PACK_END __attribute__((packed))
+#endif
+#define NORETURN __attribute__((noreturn))
+
+/* alignment value should be a power of 2 */
+#define ALIGN_X(num, align) WM_MASK(num, (typeof(num))align - 1)
+
+#define ALIGN_2(num)  ALIGN_X(num, 2)
+#define ALIGN_4(num)  ALIGN_X(num, 4)
+#define ALIGN_8(num)  ALIGN_X(num, 8)
+#define ALIGN_16(num) ALIGN_X(num, 16)
+#define ALIGN_32(num) ALIGN_X(num, 32)
+
+#else /* __GNUC__ */
+
+#define WARN_UNUSED_RET
+
+#define PACK_START __packed
+#define PACK_END
+#define NORETURN
+
+#endif /* __GNUC__ */
+
+/* Weak function. */
+#if defined(__GNUC__)
+#define WEAK __attribute__((weak))
+#elif defined(__ICCARM__)
+#define WEAK __weak
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define WEAK __attribute__((weak))
+#endif
+
+/* alignment value should be a power of 2 */
+#define __WM_ALIGN__(num, num_type, align) WM_MASK(num, (num_type)align - 1)
+#define WM_MASK(num, mask)                 ((num + mask) & ~(mask))
+
+NORETURN void wmpanic(void);
+
+/**
+ * Convert a given hex string to a equivalent binary representation.
+ *
+ * E.g. If your input string of 4 bytes is {'F', 'F', 'F', 'F'} the output
+ * string will be of 2 bytes {255, 255} or to put the same in other way
+ * {0xFF, 0xFF}
+ *
+ * Note that hex2bin is not the same as strtoul as the latter will properly
+ * return the integer in the correct machine binary format viz. little
+ * endian. hex2bin however does only in-place like replacement of two ASCII
+ * characters to one binary number taking 1 byte in memory.
+ *
+ * @param[in] ibuf input buffer
+ * @param[out] obuf output buffer
+ * @param[in]  max_olen Maximum output buffer length
+ *
+ * @return length of the binary string
+ */
+static inline unsigned int wm_hex2bin(const uint8_t *ibuf, uint8_t *obuf, unsigned max_olen)
+{
+#ifndef __ZEPHYR__
+    unsigned int i;      /* loop iteration variable */
+    unsigned int j  = 0; /* current character */
+    unsigned int by = 0; /* byte value for conversion */
+    unsigned char ch;    /* current character */
+    unsigned int len = strlen((const char *)ibuf);
+    /* process the list of characters */
+    for (i = 0; i < len; i++)
+    {
+        if (i == (2U * max_olen))
+        {
+            (void)PRINTF("hexbin",
+                         "Destination full. "
+                         "Truncating to avoid overflow.\r\n");
+            return j + 1U;
+        }
+        ch = (unsigned char)toupper(*ibuf++); /* get next uppercase character */
+
+        /* do the conversion */
+        if (ch >= '0' && ch <= '9')
+        {
+            by = (by << 4) + ch - '0';
+        }
+        else if (ch >= 'A' && ch <= 'F')
+        {
+            by = (by << 4) + ch - 'A' + 10U;
+        }
+        else
+        { /* error if not hexadecimal */
+            return 0;
+        }
+
+        /* store a byte for each pair of hexadecimal digits */
+        if ((i & 1) == 1U)
+        {
+            j       = ((i + 1U) / 2U) - 1U;
+            obuf[j] = (uint8_t)(by & 0xffU);
+        }
+    }
+    return j + 1U;
+#else
+    return hex2bin(ibuf, strlen(ibuf), obuf, max_olen);
+#endif
+}
+
+#ifndef __ZEPHYR__
+/**
+ * Convert given binary array to equivalent hex representation.
+ *
+ * @param[in] src Input buffer
+ * @param[out]  dest Output buffer
+ * @param[in] src_len Length of the input buffer
+ * @param[in] dest_len Length of the output buffer
+ *
+ */
+void wm_bin2hex(uint8_t *src, char *dest, unsigned int src_len, unsigned int dest_len);
+#endif /* ! __ZEPHYR__ */
+
+/** Function prototype for a random entropy/seed generator
+ *
+ * \return a 32bit random number
+ */
+typedef uint32_t (*random_hdlr_t)(void);
+
+/** Register a random entropy generator handler
+ *
+ * This API allows applications to register their own random entropy
+ * generator handlers that will be internally used by get_random_sequence()
+ * to add even more randomization to the byte stream generated by it.
+ *
+ * \param[in] func Function pointer of type \ref random_hdlr_t
+ *
+ * \return WM_SUCCESS if successful
+ * \return -WM_E_NOSPC if there is no space available for additional handlers
+ */
+int random_register_handler(random_hdlr_t func);
+
+/** Un-register a random entropy generator handler
+ *
+ * This API can be used to un-register a handler registered using
+ * random_register_handler()
+ *
+ * \param[in] func Function pointer of type \ref random_hdlr_t used during
+ * registering
+ *
+ * \return WM_SUCCESS if successful
+ * \return -WM_E_INVAL if the passed pointer is invalid
+ */
+int random_unregister_handler(random_hdlr_t func);
+
+/** Register a random seed generator handler
+ *
+ * For getting better random numbers, the initial seed (ideally required only
+ * once on every boot) should also be random. This API allows applications to
+ * register their own seed generators. Applications can use any logic such
+ * that a different seed is generated every time. A sample seed generator which
+ * uses a combination of DAC (generating random noise) and ADC (that internally
+ * samples the random noise) along with the flash id has already been provided.
+ * Please have a look at sample_initialise_random_seed().
+ *
+ * The seed generator handler is called only once by the get_random_sequence()
+ * function. Applications can also explicitly initialize the seed by calling
+ * random_initialize_seed() after registering a handler.
+ *
+ * \param[in] func Function pointer of type \ref random_hdlr_t
+ *
+ * \return WM_SUCCESS if successful
+ * \return -WM_E_NOSPC if there is no space available for additional handlers
+ */
+int random_register_seed_handler(random_hdlr_t func);
+
+/** Un-register a random seed generator handler
+ *
+ * This API can be used to un-register a handler registered using
+ * random_register_seed_handler()
+ *
+ * \param[in] func Function pointer of type \ref random_hdlr_t used during
+ * registering
+ *
+ * \return WM_SUCCESS if successful
+ * \return -WM_E_INVAL if the passed pointer is invalid
+ */
+int random_unregister_seed_handler(random_hdlr_t func);
+
+/** Initialize the random number generator's seed
+ *
+ * The get_random_sequence() uses a random number generator that is
+ * initialized with a seed when get_random_sequence() is called for the first
+ * time. The handlers registered using random_register_seed_handler() are
+ * used to generate the seed. If an application wants to explicitly initialize
+ * the seed, this API can be used. The seed will then not be re-initialized
+ * in get_random_sequence().
+ */
+void random_initialize_seed(void);
+
+/** Sample random seed generator
+ *
+ * This is a sample random seed generator handler that can be registered using
+ * random_register_seed_handler() to generate a random seed. This uses a
+ * combination of DAC (generating random noise) and ADC (that internally
+ * samples the random noise) along with the flash id to generate a seed.
+ * It is recommended to register this handler and immediately call
+ * random_initialize_seed() before executing any other application code,
+ * especially if the application is going to use ADC/DAC for its own purpose.
+ *
+ * \return Random seed
+ */
+uint32_t sample_initialise_random_seed(void);
+
+/** Generate random sequence of bytes
+ *
+ * This function generates random sequence of bytes in the user provided buffer.
+ *
+ * @param[out] buf The buffer to be populated with random data
+ * @param[in] size The number of bytes of the random sequence required
+ *
+ */
+void get_random_sequence(void *buf, unsigned int size);
+
+#if (SDK_DEBUGCONSOLE != DEBUGCONSOLE_DISABLE) || defined(__ZEPHYR__)
+#define DUMP_WRAPAROUND 16U
+
+/** Dump buffer in hex format on console
+ *
+ * This function prints the received buffer in HEX format on the console
+ *
+ * \param[in] data Pointer to the data buffer
+ * \param[in] len Length of the data
+ */
+static inline void dump_hex(const void *data, unsigned len)
+{
+    (void)PRINTF("**** Dump @ %p Len: %d ****\n\r", data, len);
+
+    unsigned int i    = 0;
+    const char *data8 = (const char *)data;
+    while (i < len)
+    {
+        (void)PRINTF("%02x ", data8[i++]);
+        if (!(i % DUMP_WRAPAROUND))
+        {
+            (void)PRINTF("\n\r");
+        }
+    }
+
+    (void)PRINTF("\n\r******** End Dump *******\n\r");
+}
+/** Dump buffer in hex and ascii format on console
+ *
+ * This function prints the received buffer in HEX as well as ASCII
+ * format on the console
+ *
+ * \param[in] data Pointer to the data buffer
+ * \param[in] len Length of the data
+ */
+void dump_hex_ascii(const void *data, unsigned len);
+void dump_ascii(const void *data, unsigned len);
+void print_ascii(const void *data, unsigned len);
+void dump_json(const void *buffer, unsigned len);
+#else
+#define dump_hex(...) \
+    do                \
+    {                 \
+    } while (0)
+#define dump_hex_ascii(...) \
+    do                      \
+    {                       \
+    } while (0)
+#define dump_ascii(...) \
+    do                  \
+    {                   \
+    } while (0)
+#define print_ascii(...) \
+    do                   \
+    {                    \
+    } while (0)
+#define dump_json(...) \
+    do                 \
+    {                  \
+    } while (0)
+#endif
+
+/* Helper functions to print a float value. Some compilers have a problem
+ * interpreting %f
+ */
+
+#define wm_int_part_of(x) ((int)(x))
+static inline int wm_frac_part_of(float x, short precision)
+{
+    int scale = 1;
+
+    while ((precision--) != (short)0U)
+    {
+        scale *= 10;
+    }
+
+    return (x < 0 ? (int)(((int)x - x) * scale) : (int)((x - (int)x) * scale));
+}
+
+#if CONFIG_SIGMA_AGENT
+#if defined(SDK_OS_FREE_RTOS)
+#if (defined(__MCUXPRESSO) || defined(__GNUC__)) && !defined(__ARMCC_VERSION)
+static inline int strcasecmp(const char *a, const char *b)
+{
+    int ca, cb;
+    do
+    {
+        ca = *(unsigned char *)a;
+        cb = *(unsigned char *)b;
+        ca = tolower(toupper(ca));
+        cb = tolower(toupper(cb));
+        a++;
+        b++;
+    } while (ca == cb && ca != '\0');
+    return ca - cb;
+}
+#endif
+#endif
+#endif
+
+#ifndef __linux__
+/** Returns a pointer to a new string which is a duplicate of the
+ *  input string s.
+ *  Memory for the new string is obtained allocated by the function.
+ *
+ *  It is caller's responsibility to free the memory after its use.
+ *
+ *  \param[in] s Pointer to string to be duplicated
+ *
+ *  \return Pointer to newly allocated string which is duplicate of
+ *  input string
+ *  \return NULL on error
+ */
+char *strdup(const char *s);
+#endif /* ! __linux__ */
+
+/** Calculate CRC32 using software algorithm
+ *
+ * @pre soft_crc32_init()
+ *
+ * soft_crc32() allows the user to calculate CRC32 values of arbitrary
+ * sized buffers across multiple calls.
+ *
+ * @param[in] data__ Input buffer over which CRC32 is calculated.
+ * @param[in] data_size Length of the input buffer.
+ * @param[in] crc Previous CRC32 value used as starting point for given
+ * buffer calculation.
+ *
+ * @return Calculated CRC32 value
+ */
+uint32_t soft_crc32(const void *data__, int data_size, uint32_t crc);
+float wm_strtof(const char *str, char **endptr);
+
+/**
+ * Fill the given buffer with a sequential pattern starting from
+ * given byte.
+ *
+ * For example, if the 'first_byte' is 0x45 and buffer size of 5 then
+ * buffer will be set to {0x45, 0x46, 0x47, 0x48, 0x49}
+ * @param[in] buffer The pattern will be set to this buffer.
+ * @param[in] size Number of pattern bytes to the be written to the buffer.
+ * @param[in] first_byte This is the value of first byte in the sequential
+ * pattern.
+ *
+ */
+void fill_sequential_pattern(void *buffer, int size, uint8_t first_byte);
+
+/**
+ * Verify if the the given buffer has a sequential pattern starting from
+ * given byte.
+ *
+ * For example, if the 'first_byte' is 0x45 and buffer size of 5 then
+ * buffer will be verified for presence of {0x45, 0x46, 0x47, 0x48, 0x49}
+ * @param[in] buffer The pattern will be verified from this buffer.
+ * @param[in] size Number of pattern bytes to the be verified from the buffer.
+ * @param[in] first_byte This is the value of first byte in the sequential
+ * pattern.
+ *
+ * @return 'true' If verification successful.
+ * @return 'false' If verification fails.
+ */
+bool verify_sequential_pattern(const void *buffer, int size, uint8_t first_byte);
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmerrno.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmerrno.h
new file mode 100644
index 0000000000..f49a7d3fcd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmerrno.h
@@ -0,0 +1,143 @@
+/*
+ *  Copyright 2008-2020, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*!\file wmerrno.h
+ *\brief This file provides error codes definition.
+ */
+#ifndef WM_ERRNO_H
+#define WM_ERRNO_H
+
+#include <wifi_config_default.h>
+
+#if defined(FSL_RTOS_THREADX)
+#include <errno.h>
+#endif
+
+/* Get the module index number from error code (4th byte from LSB)*/
+#define get_module_base(code) ((code & 0xF000) >> 12)
+
+/* Get notifier message type i.e Error, Warning or Info (3rd byte from LSB)*/
+#define get_notifier_msg_type(code) ((code & 0x0F00) >> 8)
+
+/* Get module notifier code (2nd and 1st byte from LSB)*/
+#define get_code(code) (code & 0xFF)
+
+#define MOD_ERROR_START(x) ((x) << 12 | 0)
+#define MOD_WARN_START(x)  ((x) << 12 | 1)
+#define MOD_INFO_START(x)  ((x) << 12 | 2)
+
+/* Create Module index */
+#define MOD_GENERIC 0
+/** Unused */
+#define MOD_UNUSED_3 2
+/** HTTPD module index */
+#define MOD_HTTPD 3
+/** Application framework module index */
+#define MOD_AF 4
+/** FTFS module index */
+#define MOD_FTFS 5
+/** RFGET module index */
+#define MOD_RFGET 6
+/** JSON module index  */
+#define MOD_JSON 7
+/** TELNETD module index */
+#define MOD_TELNETD 8
+/** SIMPLE MDNS module index */
+#define MOD_SMDNS 9
+/** EXML module index */
+#define MOD_EXML 10
+/** DHCPD module index */
+#define MOD_DHCPD 11
+/** MDNS module index */
+#define MOD_MDNS 12
+/** SYSINFO module index */
+#define MOD_SYSINFO 13
+/** Unused module index */
+#define MOD_UNUSED_1 14
+/** CRYPTO module index */
+#define MOD_CRYPTO 15
+/** HTTP-CLIENT module index */
+#define MOD_HTTPC 16
+/** PROVISIONING module index */
+#define MOD_PROV 17
+/** SPI module index */
+#define MOD_SPI 18
+/** PSM module index */
+#define MOD_PSM 19
+/** TTCP module index */
+#define MOD_TTCP 20
+/** DIAGNOSTICS module index */
+#define MOD_DIAG 21
+/** Unused module index */
+#define MOD_UNUSED_2 22
+/** WPS module index */
+#define MOD_WPS 23
+/** WLAN module index */
+#define MOD_WLAN 24
+/** USB module index */
+#define MOD_USB 25
+/** WIFI driver module index */
+#define MOD_WIFI 26
+/** Critical error module index */
+#define MOD_CRIT_ERR 27
+/** Last module index .Applications can define their own modules beyond this */
+#define MOD_ERR_LAST 50
+
+/* Globally unique success code */
+#define WM_SUCCESS 0
+
+/* First Generic Error codes */
+#define WM_GEN_E_BASE MOD_ERROR_START(MOD_GENERIC)
+#define WM_FAIL       1
+#define WM_E_PERM     2  /*Operation not permitted */
+#define WM_E_NOENT    3  /*No such file or directory */
+#define WM_E_SRCH     4  /*No such process */
+#define WM_E_INTR     5  /*Interrupted system call */
+#define WM_E_IO       6  /*I/O error */
+#define WM_E_NXIO     7  /*No such device or address */
+#define WM_E_2BIG     8  /*Argument list too long */
+#define WM_E_NOEXEC   9  /*Exec format error */
+#define WM_E_BADF     10 /* Bad file number */
+#define WM_E_CHILD    11 /* No child processes */
+#define WM_E_AGAIN    12 /* Try again */
+#define WM_E_NOMEM    13 /* Out of memory */
+#define WM_E_ACCES    14 /* Permission denied */
+#define WM_E_FAULT    15 /* Bad address */
+#define WM_E_NOTBLK   16 /* Block device required */
+#define WM_E_BUSY     17 /* Device or resource busy */
+#define WM_E_EXIST    18 /* File exists */
+#define WM_E_XDEV     19 /* Cross-device link */
+#define WM_E_NODEV    20 /* No such device */
+#define WM_E_NOTDIR   21 /* Not a directory */
+#define WM_E_ISDIR    22 /* Is a directory */
+#define WM_E_INVAL    23 /* Invalid argument */
+#define WM_E_NFILE    24 /* File table overflow */
+#define WM_E_MFILE    25 /* Too many open files */
+#define WM_E_NOTTY    26 /* Not a typewriter */
+#define WM_E_TXTBSY   27 /* Text file busy */
+#define WM_E_FBIG     28 /* File too large */
+#define WM_E_NOSPC    29 /* No space left on device */
+#define WM_E_SPIPE    30 /* Illegal seek */
+#define WM_E_ROFS     31 /* Read-only file system */
+#define WM_E_MLINK    32 /* Too many links */
+#define WM_E_PIPE     33 /* Broken pipe */
+#define WM_E_DOM      34 /* Math argument out of domain of func */
+#define WM_E_RANGE    35 /* Math result not representable */
+
+/* WMSDK generic error codes */
+#define WM_E_CRC     36 /* Error in CRC check */
+#define WM_E_UNINIT  37 /* Module is not yet initialized */
+#define WM_E_TIMEOUT 38 /* Timeout occurred during operation */
+
+/* Defined for Hostcmd specific API*/
+#define WM_E_INBIG 39 /* Input buffer too big */
+#define WM_E_INSMALL                                                                                         \
+    40 /* A finer version for WM_E_INVAL, where it clearly specifies that input is much smaller than minimum \
+          requirement */
+#define WM_E_OUTBIG 41 /* Data output exceeds the size provided */
+
+#endif                 /* ! WM_ERRNO_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmlog.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmlog.h
new file mode 100644
index 0000000000..13e88d6e22
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmlog.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright 2008-2020, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file wmlog.h
+ *\brief This file contains macros to print logs.
+ */
+
+#ifndef __WMLOG_H__
+#define __WMLOG_H__
+
+#include <osa.h>
+
+#ifdef __ZEPHYR__
+#include "nxp_wifi.h"
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#ifndef PRINTF
+#define PRINTF printk
+#endif
+#else
+#include "fsl_debug_console.h"
+#endif
+
+#if CONFIG_ENABLE_ERROR_LOGS
+#define wmlog_e(_mod_name_, _fmt_, ...) (void)PRINTF("[%s]%s" _fmt_ "\n\r", _mod_name_, " Error: ", ##__VA_ARGS__)
+#else
+#define wmlog_e(...)
+#endif /* CONFIG_ENABLE_ERROR_LOGS */
+
+#if CONFIG_ENABLE_WARNING_LOGS
+#define wmlog_w(_mod_name_, _fmt_, ...) (void)PRINTF("[%s]%s" _fmt_ "\n\r", _mod_name_, " Warn: ", ##__VA_ARGS__)
+#else
+#define wmlog_w(...)
+#endif /* CONFIG_ENABLE_WARNING_LOGS */
+
+/* General debug function. User can map his own debug functions to this
+ne */
+#define wmlog(_mod_name_, _fmt_, ...) (void)PRINTF("[%s] " _fmt_ "\n\r", _mod_name_, ##__VA_ARGS__)
+
+/* Function entry */
+#define wmlog_entry(_fmt_, ...) (void)PRINTF("> %s (" _fmt_ ")\n\r", __func__, ##__VA_ARGS__)
+
+/* function exit */
+#define wmlog_exit(_fmt_, ...) (void)PRINTF("< %s" _fmt_ "\n\r", __func__, ##__VA_ARGS__)
+
+#endif /* __WMLOG_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmstats.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmstats.h
new file mode 100644
index 0000000000..8d8f1683fe
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmstats.h
@@ -0,0 +1,105 @@
+/*
+ *  Copyright 2008-2020, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*!\file wmstats.h
+ *\brief This file provides state statistics for Wi-Fi connection manager.
+ */
+
+#ifndef _WMSTATS_H_
+#define _WMSTATS_H_
+
+typedef enum
+{
+    CONN_STATS,
+    DHCP_STATS,
+    HTTP_CLIENT_STATS,
+    CLOUD_CUMUL_STATS,
+    CLOUD_STATS,
+    HTTPD_STATS,
+    NET_STATS,
+    IP_ADDR,
+    TIME,
+    PROV_TYPE,
+    WD_STATUS,
+} wm_stat_type_t;
+
+/*! Define return values */
+typedef enum
+{
+    /** */
+    REASON_ADV_SETTINGS_DONE,
+    /** */
+    REASON_NW_ADD_FAIL,
+    /** */
+    REASON_NW_FAILURE,
+    /** */
+    REASON_SWITCH_TO_PROV,
+    /** */
+    REASON_AUTH_FAILURES,
+    /** */
+    REASON_USER_REBOOT,
+    /** */
+    REASON_CLOUD_WATCHDOG,
+    /** */
+    REASON_CLOUD_FW_UPDATE,
+    /** */
+    REASON_WLAN_FW_UNRESPONSIVE,
+} wm_reboot_reason_t;
+
+struct wm_stats
+{
+    unsigned short wm_lloss;
+    /** The number of connection attempts.
+     * wm_conn_att == wm_conn_succ + wm_conn_fail
+     */
+    unsigned short wm_conn_att;
+    /** The connection success indicates successful association+authentication
+        attempt. This does NOT include the address configuration step */
+    unsigned short wm_conn_succ;
+    /** This should be split up into multiple types of failures
+     * wm_conn_fail = wm_auth_fail + wm_nwnt_found + others
+     */
+    unsigned short wm_conn_fail;
+    unsigned short wm_auth_fail;
+    unsigned short wm_nwnt_found;
+    /** DHCP Address assignment */
+    unsigned short wm_dhcp_succ;
+    unsigned short wm_dhcp_fail;
+    /** DHCP Lease renewal */
+    unsigned short wm_leas_succ;
+    unsigned short wm_leas_fail;
+    /** 1 if DHCP */
+    char wm_addr_type;
+    unsigned int wm_dhcp_req_cnt;
+    /** HTTP Client */
+    unsigned short wm_ht_dns_fail;
+    unsigned short wm_ht_sock_fail;
+    unsigned short wm_ht_conn_no_route;
+    unsigned short wm_ht_conn_timeout;
+    unsigned short wm_ht_conn_reset;
+    unsigned short wm_ht_conn_other;
+    /** Cloud Stats */
+    unsigned long wm_cl_post_succ;
+    unsigned long wm_cl_post_fail;
+    unsigned long wm_cl_total;
+    unsigned int wm_cl_cum_total;
+    /** Provisioning type */
+    /* Tells whether the module was in NORMAL mode, PROVISIONING mode or
+     * TIMED PROVISIONING mode immediately after rebooting*/
+    unsigned short wm_prov_type;
+
+    /** Reboot reason of the device */
+    wm_reboot_reason_t reboot_reason;
+};
+
+extern struct wm_stats g_wm_stats;
+
+/** Note: This should be in sync with definition in firmware file
+ * tcpip_custom.h.
+ * */
+
+#endif /* ! _WMSTATS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmtypes.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmtypes.h
new file mode 100644
index 0000000000..2cccc6e406
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/incl/wmtypes.h
@@ -0,0 +1,24 @@
+/*
+ *  Copyright 2008-2020, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+/*!\file wmtypes.h
+ *\brief This file provides consolidated header for data types
+ */
+
+
+#ifndef _WMTYPES_H_
+#define _WMTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <wifi_config_default.h>
+
+#ifdef __ZEPHYR__
+#include "nxp_wifi.h"
+#endif
+
+#endif /* ! _WMTYPES_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/net.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/net.c
new file mode 100644
index 0000000000..8d421be880
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/net.c
@@ -0,0 +1,155 @@
+/** @file net.c
+ *
+ *  @brief  This file provides network porting code
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+// Modified to work with Mongoose built-in TCP/IP by Cesanta Software Ltd.
+
+#include <inttypes.h>
+#include <osa.h>
+#include <wlan.h>
+#include <wm_net.h>
+#include "netif_decl.h"
+#include "wifi.h"
+
+#include <wmlog.h>
+#define net_e(...) wmlog_e("net", ##__VA_ARGS__)
+
+#if CONFIG_NET_DEBUG
+#define net_d(...) wmlog("net", ##__VA_ARGS__)
+#else
+#define net_d(...)
+#endif /* ! CONFIG_NET_DEBUG */
+
+typedef struct {
+  struct netif netif;
+} interface_t;
+
+static interface_t s_sta;
+static interface_t s_ap;
+
+static bool net_wlan_init_done;
+
+// in netif-specific netif_mongoose.c
+extern void handle_data_packet(const t_u8 interface, const t_u8 *rcvdata, const t_u16 datalen);
+extern void handle_amsdu_data_packet(t_u8 interface, t_u8 *rcvdata, t_u16 datalen);
+extern void handle_deliver_packet_above(t_void *rxpd, t_u8 interface, t_void *lwip_pbuf);
+extern bool wrapper_net_is_ip_or_ipv6(const t_u8 *buffer);
+
+void net_wlan_set_mac_address(unsigned char *stamac, unsigned char *uapmac) {
+  if (stamac != NULL) memcpy(s_sta.netif.mac, stamac, sizeof(s_sta.netif.mac));
+  if (uapmac != NULL) memcpy(s_ap.netif.mac, uapmac, sizeof(s_sta.netif.mac));
+}
+
+int net_wlan_init(void) {
+#ifdef RW610
+  (void) wifi_register_data_input_callback(&handle_data_packet);
+  (void) wifi_register_amsdu_data_input_callback(&handle_amsdu_data_packet);
+  (void) wifi_register_deliver_packet_above_callback(
+      &handle_deliver_packet_above);
+  (void) wifi_register_wrapper_net_is_ip_or_ipv6_callback(
+      &wrapper_net_is_ip_or_ipv6);
+#endif
+  if (!net_wlan_init_done) {
+
+#ifndef RW610
+    (void) wifi_register_data_input_callback(&handle_data_packet);
+    (void) wifi_register_amsdu_data_input_callback(&handle_amsdu_data_packet);
+    (void) wifi_register_deliver_packet_above_callback(
+        &handle_deliver_packet_above);
+    (void) wifi_register_wrapper_net_is_ip_or_ipv6_callback(
+        &wrapper_net_is_ip_or_ipv6);
+#endif
+    net_wlan_init_done = 1;
+  }
+
+  (void) wlan_wlcmgr_send_msg(WIFI_EVENT_NET_INTERFACE_CONFIG, WIFI_EVENT_REASON_SUCCESS, NULL);
+  return WM_SUCCESS;
+}
+
+struct netif *net_get_sta_interface(void) {
+  return &s_sta.netif;
+}
+
+struct netif *net_get_uap_interface(void) {
+  return &s_ap.netif;
+}
+
+int net_get_if_name_netif(char *pif_name, struct netif *iface) {
+  if (iface == &s_sta.netif) strcpy(pif_name, "STA");
+  if (iface == &s_ap.netif) strcpy(pif_name, "AP");
+  return WM_SUCCESS;
+}
+
+int net_wlan_deinit(void) {
+  return WM_SUCCESS;
+}
+
+void net_stop_dhcp_timer(void) {
+}
+
+void *net_get_sta_handle(void) {
+  return &s_sta;
+}
+
+void *net_get_uap_handle(void) {
+  return &s_ap;
+}
+
+int net_alloc_client_data_id() {
+  return -1;
+}
+
+void net_interface_up(void *intrfc_handle) {
+(void) intrfc_handle;
+}
+
+void net_interface_down(void *intrfc_handle) {
+(void) intrfc_handle;
+}
+
+void net_interface_dhcp_stop(void *intrfc_handle) {
+(void) intrfc_handle;
+}
+
+void net_interface_dhcp_cleanup(void *intrfc_handle) {
+(void) intrfc_handle;
+}
+
+int net_configure_address(struct net_ip_config *addr, void *intrfc_handle) {
+  interface_t *if_handle = (interface_t *)intrfc_handle;
+  // A Mongoose environment does not need this nor works this way
+  net_d("Deliberately ignoring request to configure interface %s (with %s)",
+        (if_handle == &s_sta) ? "STA" : "AP", (addr->ipv4.addr_type == NET_ADDR_TYPE_DHCP) ? "DHCP client" : "Static IP");
+  if (if_handle == &s_sta) {
+    wlan_wlcmgr_send_msg(WIFI_EVENT_NET_STA_ADDR_CONFIG, WIFI_EVENT_REASON_SUCCESS, NULL);
+    // Keep wlan in its realm and fool it to return we are connected
+    if (addr->ipv4.addr_type == NET_ADDR_TYPE_DHCP)
+      wlan_wlcmgr_send_msg(WIFI_EVENT_NET_DHCP_CONFIG, WIFI_EVENT_REASON_SUCCESS, NULL);
+  } else if (if_handle == &s_ap) {
+    (void) wlan_wlcmgr_send_msg(WIFI_EVENT_UAP_NET_ADDR_CONFIG, WIFI_EVENT_REASON_SUCCESS, NULL);
+  } else {
+    // Do nothing
+  }
+  return WM_SUCCESS;
+}
+
+int net_get_if_addr(struct net_ip_config *addr, void *intrfc_handle) {
+  interface_t *if_handle = (interface_t *)intrfc_handle;
+  extern void netif_fillstaddr(unsigned *, unsigned *, unsigned *, unsigned *); // type is NXP's struct type
+  extern void netif_fillapaddr(unsigned *, unsigned *, unsigned *, unsigned *); // type is NXP's struct type
+  if (if_handle == &s_sta) netif_fillstaddr(&addr->ipv4.address, &addr->ipv4.netmask, &addr->ipv4.gw, &addr->ipv4.dns1);
+  if (if_handle == &s_ap)  netif_fillapaddr(&addr->ipv4.address, &addr->ipv4.netmask, &addr->ipv4.gw, &addr->ipv4.dns1);
+  addr->ipv4.dns2 = addr->ipv4.dns1;
+  return WM_SUCCESS;
+}
+
+void net_configure_dns(struct net_ip_config *ip, unsigned int role) {
+  // A Mongoose environment does not need this nor works this way
+  net_d("Deliberately ignoring request to configure DNS for role %u", role);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/netif_decl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/netif_decl.h
new file mode 100644
index 0000000000..11b09785b7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/netif_decl.h
@@ -0,0 +1,56 @@
+/*
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+// Modified to work with Mongoose built-in TCP/IP by Cesanta Software Ltd.
+
+#include <mlan_api.h>
+#include <wm_net.h>
+#include <wmlog.h>
+#ifdef RW610
+#include <wifi-imu.h>
+#else
+#include <wifi-sdio.h>
+#endif
+#include <wifi-internal.h>
+
+#define NETIF_NAMESIZE 4
+
+struct netif {
+  uint8_t mac[6];
+};
+
+/*
+ * It was observed that Wi-Fi card does not wakeup
+ * immediately after call to wlan_wakeup_card.
+ * The code tries to wakeup the card by writing
+ * in SDIO register.
+ * It waits for 20 ms for AWAKE event from Wi-Fi card,
+ * if AWAKE event is not generated or received  by MCU code
+ * it returns error and does not send a packet out.
+ * This is observed with  8801 Wi-Fi card.
+ * So for 8801 based platforms the wait time is now 35 ms.
+ */
+#define MAX_WAIT_TIME 35
+
+extern int wlan_get_mac_address(uint8_t *dest);
+extern void wlan_wake_up_card(void);
+
+#if CONFIG_WPA_SUPP
+// void (*l2_packet_rx_callback)(const struct pbuf *p);
+#endif /* CONFIG_HOST_SUPP */
+
+void wrapper_wlan_update_uap_rxrate_info(RxPD *rxpd);
+
+int wrapper_wlan_handle_rx_packet(t_u16 datalen, RxPD *rxpd, void *p,
+                                  void *payload);
+
+int wrapper_wlan_handle_amsdu_rx_packet(const t_u8 *rcvdata,
+                                        const t_u16 datalen);
+
+#if CONFIG_NET_MONITOR
+void user_recv_monitor_data(const t_u8 *rcvdata);
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/netif_mongoose.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/netif_mongoose.c
new file mode 100644
index 0000000000..3ee70977f6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/net/netif_mongoose.c
@@ -0,0 +1,566 @@
+// Portions of this taken from NXP examples, copyright 2008-2023 NXP,
+// BSD-3-Clause licensed
+
+#include <netif_decl.h>
+#include "mongoose.h"
+#include "wlan_bt_fw.h"
+#define STA_NWKLBL "wifi"  // wlan ids interfaces with text labels...
+#define AP_NWKLBL "uap-network" // hardcoded in wlan.c, do NOT change
+
+#if CONFIG_IPV6
+#error "CONFIG_IPV6 is not supported, disable it"
+#endif
+
+#if FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER
+#error FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER is not supported, disable it
+#endif
+
+#if CONFIG_TX_RX_ZERO_COPY
+#error CONFIG_TX_RX_ZERO_COPY is not supported, disable it
+#endif
+
+uint16_t g_data_nf_last;
+uint16_t g_data_snr_last;
+
+#if CONFIG_WPS2
+static void (*wps_rx_callback)(const t_u8 *buf, size_t len);
+#endif
+
+void handle_data_packet(const t_u8 ifc, const t_u8 *data, const t_u16 len);
+void handle_amsdu_data_packet(t_u8 ifc, t_u8 *data, t_u16 len);
+void handle_deliver_packet_above(t_void *rxpd, t_u8 ifc, t_void *priv_pbuf);
+bool wrapper_net_is_ip_or_ipv6(const t_u8 *buffer);
+
+#if MGMT_RX
+static int (*rx_mgmt_callback)(const enum wlan_bss_type bss_type,
+                               const wifi_mgmt_frame_t *frame,
+                               const size_t len);
+void rx_mgmt_register_callback(
+    int (*rx_mgmt_cb_fn)(const enum wlan_bss_type bss_type,
+                         const wifi_mgmt_frame_t *frame, const size_t len)) {
+  rx_mgmt_callback = rx_mgmt_cb_fn;
+}
+void rx_mgmt_deregister_callback() {
+  rx_mgmt_callback = NULL;
+}
+#endif
+
+#define ETH_PKT_SIZE 1540  // Max frame size
+
+// Receive path
+// - net.c registers these handlers:
+//   - Received data --> handle_data_packet()
+//   - AMSDU data --> handle_amsdu_data_packet()
+//   - deliver_packet_above_callback --> handle_deliver_packet_above
+// - This generates the following receive data flow:
+//   - Rx Frame --> handle_data_packet() --> process_data_packet() --> wifi libs
+//   internal processing -->
+//     --> handle_deliver_packet_above() --> deliver_packet_above()
+//     --> handle_amsdu_data_packet() --> deliver_packet_above()
+// - Wifi libs internal processing assumes some kind of lwip_pbuf-like packet
+// buffer scheme; so, it calls back some functions to operate on that, and
+// returns that to the two handlers shown above
+// - process_data_packet() is expected to filter and respond to some management
+// frames, store Rx Frame data on that buffering scheme, and handle it to
+// another section of the vendor libs.
+// - deliver_packet_above() finally delivers to Mongoose TCP/IP stack or back to
+// the vendor stack for final EAPOL/WPS2 processing.
+
+// THESE FUNCTIONS GET CALLED FROM HAL_ImuMainCpu13 TASK CONTEXT
+
+static void process_data_packet(const uint8_t *data, const uint16_t len);
+static void deliver_packet_above(struct pb *buf, int ifc);
+static struct pb *topb(uint8_t *data, uint16_t len);
+
+void handle_data_packet(const t_u8 ifc, const t_u8 *data, const t_u16 len) {
+  if (ifc < 2)
+    process_data_packet((const uint8_t *) data, (const uint16_t) len);
+}
+
+void handle_amsdu_data_packet(t_u8 ifc, t_u8 *data, t_u16 len) {
+  if (ifc >= 2) return;
+  // handled data will be destroyed when we return + libs use FreeRTOS tasks
+  struct pb *buf = topb((uint8_t *) data, (uint16_t) len);
+  if (buf != NULL) deliver_packet_above(buf, ifc);
+}
+
+void handle_deliver_packet_above(t_void *rxpd, t_u8 ifc, t_void *priv_pbuf) {
+  if (ifc >= 2) return;
+  deliver_packet_above((struct pb *) priv_pbuf, ifc);
+  (void) rxpd;
+}
+
+// This one gets called from wifi_low_level_output(), in Mongoose context
+bool wrapper_net_is_ip_or_ipv6(const t_u8 *buffer) {
+  return net_is_ip_or_ipv6(buffer);
+}
+
+#pragma pack(push, 1)
+// in network order
+struct eth_hdr {  // TODO(scaprile) reuse 'eth' in net_builtin.c
+  uint8_t dest[6];
+  uint8_t src[6];
+  uint16_t type;
+};
+
+struct llc_hdr {
+  uint8_t dsap, ssap, ctrl, oui[3];
+  uint16_t proto;
+};
+#pragma pack(pop)
+
+// Entry point for data frames, wrap or put in a custom buffer is necessary,
+// then handle back to wifi libs for processing
+//  ------------- ------ ----------
+// | INTF_HEADER | RxPD | Rx frame |
+//  ------------- ------ ----------
+// Take into account the possibility that the code is being compiled with the
+// wpa_supplicant library and support for mobile wireless extensions
+static void process_data_packet(const uint8_t *data, const uint16_t len) {
+  RxPD *rxpd = (RxPD *) (data + INTF_HEADER_LEN);
+  mlan_bss_type ifc = (mlan_bss_type) (rxpd->bss_type);
+  uint16_t header_type;
+#if !CONFIG_WPA_SUPP
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_1AS)
+  wlan_mgmt_pkt *pmgmt_pkt_hdr = MNULL;
+  wlan_802_11_header *pieee_pkt_hdr = MNULL;
+  t_u16 sub_type = 0;
+  t_u8 category = 0;
+#endif
+#endif
+  uint8_t *payload;
+  uint16_t payload_len = 0;
+  struct pb *buf = NULL;
+
+  if (rxpd->rx_pkt_type == PKT_TYPE_AMSDU) {
+    Eth803Hdr_t *h = (Eth803Hdr_t *) ((t_u8 *) rxpd + rxpd->rx_pkt_offset);
+    if (memcmp(mlan_adap->priv[ifc]->curr_addr, h->dest_addr,
+               MLAN_MAC_ADDR_LENGTH) != 0 &&
+        ((h->dest_addr[0] & 0x01) == 0))
+      return;  // If the AMSDU frame is unicast and is not for us, drop it
+  }
+
+  if (ifc == MLAN_BSS_TYPE_STA || ifc == MLAN_BSS_TYPE_UAP) {
+    g_data_nf_last = rxpd->nf;
+    g_data_snr_last = rxpd->snr;
+  }
+
+#if !CONFIG_WPA_SUPP
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_1AS)
+  if (rxpd->rx_pkt_type == PKT_TYPE_MGMT_FRAME && ifc == MLAN_BSS_TYPE_STA) {
+    pmgmt_pkt_hdr =
+        (wlan_mgmt_pkt *) (void *) ((t_u8 *) rxpd + rxpd->rx_pkt_offset);
+    pieee_pkt_hdr = (wlan_802_11_header *) (void *) &pmgmt_pkt_hdr->wlan_header;
+    sub_type = IEEE80211_GET_FC_MGMT_FRAME_SUBTYPE(pieee_pkt_hdr->frm_ctl);
+    category = *((t_u8 *) pieee_pkt_hdr + sizeof(wlan_802_11_header));
+    if (sub_type == (t_u16) SUBTYPE_ACTION &&
+        (category != (t_u8) IEEE_MGMT_ACTION_CATEGORY_RADIO_RSRC &&
+         category != (t_u8) IEEE_MGMT_ACTION_CATEGORY_WNM &&
+         category != (t_u8) IEEE_MGMT_ACTION_CATEGORY_UNPROTECT_WNM))
+      return;
+    payload = (uint8_t *) rxpd;
+    payload_len = len - INTF_HEADER_LEN;
+  } else
+#endif
+#endif
+  {
+    payload = (uint8_t *) rxpd + rxpd->rx_pkt_offset;
+    payload_len = rxpd->rx_pkt_length;
+  }
+
+  // handled data will be destroyed when we return + libs use FreeRTOS tasks
+  buf = topb(payload, payload_len);
+  if (buf == NULL) return;
+
+#if !CONFIG_WPA_SUPP
+  if (rxpd->rx_pkt_type == PKT_TYPE_MGMT_FRAME) {
+    // Bypass management frames about Add Block Ack Request or Add Block Ack
+    // Response
+    if (wlan_bypass_802dot11_mgmt_pkt(buf->data) == WM_SUCCESS) {
+      free(buf);
+      return;
+    }
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_1AS)
+    if (sub_type == (t_u16) SUBTYPE_ACTION && ifc == MLAN_BSS_TYPE_STA) {
+      if (wifi_event_completion(WIFI_EVENT_MGMT_FRAME,
+                                WIFI_EVENT_REASON_SUCCESS, buf) != WM_SUCCESS)
+        free(buf);
+      return;
+    }
+#endif
+    // MGMT_RX: rx_mgmt_callback() is never called in the examples; dropped
+  }
+#endif
+
+  struct eth_hdr *ethhdr = (struct eth_hdr *) buf->data;
+  header_type = mg_ntohs(ethhdr->type);
+
+  uint8_t llcoui[6] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};  // 802.3 frame ?
+  if (memcmp(buf->data + sizeof(Eth803Hdr_t), llcoui, 6) == 0) {
+    struct llc_hdr *h = (struct llc_hdr *) (buf->data + sizeof(Eth803Hdr_t));
+    header_type = mg_ntohs(h->proto);
+    if (rxpd->rx_pkt_type != PKT_TYPE_AMSDU) {  // convert to Ethernet
+      ethhdr->type = h->proto;  // Rest of Eth header = 802.3 header
+      buf->len -= sizeof(*h);
+      (void) memmove(buf->data + sizeof(*ethhdr),
+                     buf->data + sizeof(*ethhdr) + sizeof(*h),
+                     buf->len - sizeof(*ethhdr));
+    }
+  }
+  switch (header_type) {
+    case 0x0800:  // IPv4
+#if CONFIG_IPV6
+    case 0x86dd:  // IPv6
+#endif
+    case 0x0806:  // Unicast ARP also needs to be reordered
+      if (ifc == MLAN_BSS_TYPE_STA || ifc == MLAN_BSS_TYPE_UAP) {
+        if (wrapper_wlan_handle_rx_packet(len, rxpd, buf, payload) !=
+            WM_SUCCESS)
+          free(buf);
+      } else {
+        wrapper_wlan_update_uap_rxrate_info(rxpd);
+        deliver_packet_above(buf, ifc);
+      }
+      break;
+    case 0x888E:  // EAPOL
+      deliver_packet_above(buf, ifc);
+      break;
+    default:
+#if CONFIG_NET_MONITOR
+      if (rxpd->rx_pkt_type == PKT_TYPE_802DOT11 && get_monitor_flag()) {
+        wifi_frame_t *frame = (wifi_frame_t *) buf->data;
+        if (frame->frame_type == BEACON_FRAME ||
+            frame->frame_type == DATA_FRAME ||
+            frame->frame_type == AUTH_FRAME ||
+            frame->frame_type == PROBE_REQ_FRAME ||
+            frame->frame_type == QOS_DATA_FRAME) {
+          user_recv_monitor_data(data);
+        }
+      }
+#endif
+      free(buf);
+      break;
+  }
+}
+
+static struct mg_tcpip_if *s_ifp;
+
+// Final processing stage, deliver to TCP/IP stack or to wlan libs
+static void deliver_packet_above(struct pb *buf, int ifc) {
+  struct eth_hdr *ethhdr = (struct eth_hdr *) buf->data;
+  w_pkt_d("Data RX: Driver=>Kernel, if %d, len %d", ifc, buf->len);
+  if (mg_ntohs(ethhdr->type == 0x888E)) {
+#if CONFIG_WPS2
+    if (wps_rx_callback != NULL) wps_rx_callback(buf->data, buf->len);
+#endif
+  } else if (ifc < 2) {
+    mg_tcpip_qwrite(buf->data, buf->len, s_ifp);
+  }
+  free(buf);
+}
+
+#if CONFIG_WPS2
+void wps_register_rx_callback(void (*h)(const t_u8 *buf, const size_t len)) {
+  wps_rx_callback = h;
+}
+
+void wps_deregister_rx_callback() {
+  wps_rx_callback = NULL;
+}
+#endif
+
+static struct pb *topb(uint8_t *data, uint16_t len) {
+  struct pb *buf = (struct pb *) malloc(ETH_PKT_SIZE + sizeof(buf->len));
+  if (buf == NULL) {
+    MG_ERROR(("OOM"));
+    return buf;
+  }
+  memcpy(buf->data, data, len);
+  buf->len = len;
+  return buf;
+}
+
+// Utility and link status functions, CALLED FROM (yet) ANOTHER TASK CONTEXT
+
+// need to make sure Mongoose will not write to these vars
+void netif_fillstaddr(unsigned *addr, unsigned *mask, unsigned *gw,
+                      unsigned *dns) {  // type is NXP's struct type
+}
+void netif_fillapaddr(unsigned *addr, unsigned *mask, unsigned *gw,
+                      unsigned *dns) {  // type is NXP's struct type
+}
+
+// Transmit path
+// - Mongoose calls netif_tx(), which tries to make it to the wlan libs
+//   - If what seems to be a priority queuing scheme (WMM) is in place, it then
+//   tries calling wifi_add_to_bypassq(). This function expects a networking
+//   stack proprietary buffer, so it will call back those functions mentioned at
+//   the receive path docs above. If that fails, it tries several times to get a
+//   vendor proprietary packet buffer, crafts data into it, and handles it to
+//   wifi_low_level_output().
+//   - Otherwise (no WMM), it tries several times to get another type of vendor
+//   proprietary packet buffer, crafts data into it, and handles it to
+//   wifi_low_level_output().
+
+// These functions are called by Mongoose task (except when noted)
+
+size_t netif_tx(const void *bfr, size_t len, struct mg_tcpip_if *ifp) {
+  struct mg_tcpip_driver_nxp_wifi_data *d = (struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data;
+  t_u8 ifc = (d->wifi.apmode) ? MLAN_BSS_TYPE_UAP : MLAN_BSS_TYPE_STA;
+  int ret;
+  t_u8 *buf = NULL;
+  t_u16 pktlen;
+  uint32_t buflen;
+
+#if CONFIG_WMM
+  t_u8 tid = 0;
+  int retry = 0;
+  t_u8 ra[MLAN_MAC_ADDR_LENGTH] = {0};
+  bool is_tx_pause = false;
+  extern int retry_attempts;
+
+  t_u32 pkt_prio = wifi_wmm_get_pkt_prio((void *) bfr, &tid);
+  if (pkt_prio == -WM_FAIL) return 0;
+
+  if (wifi_tx_status == WIFI_DATA_BLOCK) {
+    wifi_tx_block_cnt++;
+    return len;
+  }
+
+  if (wifi_add_to_bypassq(ifc, (void *) bfr, len) == WM_SUCCESS) return len;
+
+  wifi_wmm_da_to_ra((void *) bfr, ra);
+  retry = retry_attempts;
+  while (retry--) {
+    buf = wifi_wmm_get_outbuf_enh(&buflen, (mlan_wmm_ac_e) pkt_prio, ifc, ra,
+                                  &is_tx_pause);
+    if (buf != NULL) break;
+    if (buf == NULL && retry <= 0) {
+      wifi_wmm_drop_retried_drop(ifc);
+      mlan_adap->priv[ifc]->tx_overrun_cnt++;
+      return 0;
+    }
+    if (is_tx_pause) OSA_TimeDelay(1);
+    send_wifi_driver_tx_data_event(ifc);
+  }
+  pktlen = sizeof(TxPD) + INTF_HEADER_LEN + sizeof(mlan_linked_list);
+  memset(buf, 0x00, pktlen);
+  memcpy(buf + pktlen, bfr, len);
+  pktlen += len;
+  ret = wifi_low_level_output(ifc, buf, pktlen, pkt_prio, tid);
+#else
+  buf = wifi_get_outbuf(&buflen);
+  if (buf == NULL) {
+    mlan_adap->priv[ifc]->tx_overrun_cnt++;
+    return 0;
+  }
+  pktlen = sizeof(TxPD) + INTF_HEADER_LEN;
+  memset(buf, 0x00, pktlen);
+  memcpy(buf + pktlen, bfr, len);
+  pktlen += len;
+  ret = wifi_low_level_output(ifc, buf, pktlen);
+#endif
+
+  if (ret != WM_SUCCESS) {
+    if (ret == -WM_E_NOMEM) mlan_adap->priv[ifc]->tx_overrun_cnt++;
+    return 0;
+  }
+  return len;
+}
+
+
+static volatile bool s_stalink = false, s_aplink = false, s_ok = false,
+                     s_fail = false;
+static bool s_scanning = false, s_connecting = false;
+
+
+// THIS FUNCTION GETS CALLED FROM wlcmgr_task TASK CONTEXT
+// - even though a callback is passed to the init function, other parts of the libs rely on an external with this name... so we reuse the same function
+int wlan_event_callback(enum wlan_event_reason reason, void *data) {
+  (void) data;
+  switch (reason) {
+    case WLAN_REASON_INITIALIZED:
+      s_ok = true;
+      break;
+    case WLAN_REASON_INITIALIZATION_FAILED:
+      s_fail = true;
+      break;
+    case WLAN_REASON_SUCCESS:
+      s_ok = true;
+      s_stalink = true;
+      break;
+    case WLAN_REASON_CONNECT_FAILED:
+    case WLAN_REASON_NETWORK_NOT_FOUND:
+    case WLAN_REASON_NETWORK_AUTH_FAILED:
+      s_fail = true;
+      s_stalink = false;
+      break;
+    case WLAN_REASON_USER_DISCONNECT:
+    case WLAN_REASON_LINK_LOST:
+      s_stalink = false;
+      break;
+    case WLAN_REASON_UAP_SUCCESS:
+      s_ok = true;
+      s_aplink = true;
+      break;
+    case WLAN_REASON_UAP_START_FAILED:
+    case WLAN_REASON_UAP_STOP_FAILED:
+      s_fail = true;
+      break;
+    case WLAN_REASON_UAP_STOPPED:
+      s_ok = true;
+      s_aplink = false;
+      break;
+    default:
+      break;
+  }
+  return WM_SUCCESS;
+}
+
+
+bool netif_init(struct mg_tcpip_if *ifp) {
+  s_ifp = ifp;
+  s_stalink = false;
+  s_aplink = false;
+  if (wlan_init(wlan_fw_bin, wlan_fw_bin_len) != WM_SUCCESS) return false;
+  if (wlan_start(&wlan_event_callback) != WM_SUCCESS) return false;
+  while (!s_ok) {
+    if (s_fail) return false;
+    OSA_TimeDelay(1);
+  }
+  wlan_get_mac_address(ifp->mac);  // same for STA and AP
+  wlan_config_mef(MEF_TYPE_MULTICAST, 3);
+  return true;
+}
+
+
+static volatile uint8_t s_scan_results = 0;
+
+static void handle_scan_result(unsigned int, mg_tcpip_event_handler_t);
+
+bool netif_poll(struct mg_tcpip_if *ifp, bool s1, mg_tcpip_event_handler_t evcb) {
+  if (s_scanning && s_scan_results > 0) {
+    // serve scan results one by one, to be fair to other connections; result
+    // table should stay valid until next scan
+    handle_scan_result((unsigned int) --s_scan_results, evcb);
+    if (s_scan_results == 0) {
+      MG_VERBOSE(("scan complete"));
+      s_scanning = false;
+      evcb(ifp, MG_TCPIP_EV_WIFI_SCAN_END, NULL);
+    }
+  }
+  if (!s1) return false;
+  struct mg_tcpip_driver_nxp_wifi_data *d = (struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data;
+  if (d->wifi.apmode) return s_aplink;
+  MG_VERBOSE(("conn: %c ok/fail: %c/%c", s_connecting ? '1' : '0',
+              s_ok ? '1' : '0', s_fail ? '1' : '0'));
+  if (s_connecting && (s_ok || s_fail)) {
+    if (s_fail) evcb(ifp, MG_TCPIP_EV_WIFI_CONNECT_ERR, NULL);
+    s_connecting = false;
+  }
+  return s_stalink;
+}
+
+
+static void handle_scan_result(unsigned int i, mg_tcpip_event_handler_t evcb) {
+  struct wlan_scan_result r;
+  if (wlan_get_scan_result((uint32_t) i, &r) != WM_SUCCESS) return;
+  struct mg_wifi_scan_bss_data bss;
+  unsigned char bssid[6];
+  bss.SSID = mg_str_n(r.ssid, r.ssid_len);
+  mg_mprintf(bssid, "%M", print_mac, r.bssid);
+  bss.BSSID = bssid;
+  bss.RSSI = (int8_t) -r.rssi;
+  bss.has_n = r.dot11n;  // TODO(scaprile): add 11ac, 11ax, etc
+  bss.channel = r.channel;
+  bss.band = r.channel <= MAX_CHANNELS_BG ? MG_WIFI_BAND_2G : MG_WIFI_BAND_5G;
+  bss.security = r.wep ? MG_WIFI_SECURITY_WEP : MG_WIFI_SECURITY_OPEN;
+  if (r.wpa) bss.security |= MG_WIFI_SECURITY_WPA;
+  if (r.wpa2) bss.security |= MG_WIFI_SECURITY_WPA2;
+  // TODO(scaprile): add WPA3, enterprise
+  MG_VERBOSE(("BSS: %.*s (%u) (%M) %d dBm %u", bss.SSID.len, bss.SSID.buf,
+              bss.channel, mg_print_mac, bss.BSSID, (int) bss.RSSI,
+              bss.security));
+  evcb(s_ifp, MG_TCPIP_EV_WIFI_SCAN_RESULT, &bss);
+}
+
+// THIS FUNCTION GETS CALLED FROM wlcmgr_task TASK CONTEXT
+static int get_scan(unsigned int count) {
+  s_scan_results = (uint8_t) count;
+  return WM_SUCCESS;
+}
+
+bool mg_wifi_scan(void) {
+  s_scan_results = 0;
+  s_scanning = (wlan_scan(&get_scan) == WM_SUCCESS);
+  return s_scanning;
+}
+
+
+bool netif_connect(struct mg_wifi_data *wifi) {
+  struct wlan_network sta;
+  MG_DEBUG(("Connecting to '%s'", wifi->ssid));
+  memset(&sta, 0, sizeof(sta));
+  sta.security.type = WLAN_SECURITY_WILDCARD;
+  sta.security.mfpc = true;
+  sta.security.mfpr = true;
+  sta.security.password_len = strlen(wifi->pass);
+  strcpy(sta.security.password, wifi->pass);
+  sta.security.psk_len = sta.security.password_len;
+  strcpy(sta.security.psk, wifi->pass);
+  strcpy(sta.name, STA_NWKLBL);
+  strcpy(sta.ssid, wifi->ssid);
+  sta.ip.ipv4.addr_type = ADDR_TYPE_DHCP;
+  sta.ssid_specific = 1;
+  if (wlan_add_network(&sta) != WM_SUCCESS) return false;
+  s_connecting = false;
+  s_ok = s_fail = false;
+  if (wlan_connect(STA_NWKLBL) == WM_SUCCESS) {
+    s_connecting = true;
+  } else {
+    enum wlan_connection_state s = WLAN_DISCONNECTED;
+    if (wlan_get_connection_state(&s) == WM_SUCCESS && s != WLAN_DISCONNECTED)
+      wlan_disconnect();
+    wlan_remove_network(STA_NWKLBL);
+  }
+  return s_connecting;
+}
+
+bool mg_wifi_disconnect(void) {
+  enum wlan_connection_state s = WLAN_DISCONNECTED;
+  return (wlan_get_connection_state(&s) == WM_SUCCESS &&
+          s != WLAN_DISCONNECTED && wlan_disconnect() == WM_SUCCESS &&
+          wlan_remove_network(STA_NWKLBL) == WM_SUCCESS);
+}
+
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  struct wlan_network ap;
+  MG_DEBUG(("Starting AP '%s' (%u)", wifi->apssid, wifi->apchannel));
+  wlan_initialize_uap_network(&ap);
+  strcpy(ap.ssid, wifi->apssid);
+  ap.channel = wifi->apchannel;
+  ap.security.type = WLAN_SECURITY_WPA2;
+  ap.security.psk_len = strlen(wifi->appass);
+  strcpy(ap.security.psk, wifi->appass);
+  wlan_add_network(&ap); // error return values won't help, more resilient
+  s_ok = s_fail = false;
+  if (wlan_start_network(ap.name) == WM_SUCCESS) {
+    while (!s_fail) {
+      if (s_ok) return true;
+      OSA_TimeDelay(1);
+    }
+  }
+  wlan_remove_network(AP_NWKLBL); // error return values won't help
+  return false;
+}
+
+bool mg_wifi_ap_stop(void) {
+  s_ok = s_fail = false;
+  if (wlan_stop_network(AP_NWKLBL) != WM_SUCCESS) return false;
+  while (!s_ok) {
+    if (s_fail) return false;
+    OSA_TimeDelay(1);
+  }
+  wlan_remove_network(AP_NWKLBL); // error return values won't help
+  return true;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/mem_pool.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/mem_pool.c
new file mode 100644
index 0000000000..000fdf0228
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/mem_pool.c
@@ -0,0 +1,215 @@
+/*
+ *  Copyright 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdlib.h>
+#include "mem_pool.h"
+
+#if CONFIG_MEM_POOLS
+
+#if defined(SDK_OS_FREE_RTOS)
+
+static int CalculateAndVerifyAlignment(int Alignment)
+{
+    /*********************************/
+    int i;
+    int alignmentBit = 0x1;
+    /*********************************/
+
+    /**
+     *  Guarantee that the alignment is the size of a pointer.
+     */
+    if (Alignment < (int)sizeof(unsigned char *))
+    {
+        Alignment = (int)sizeof(unsigned char *);
+    }
+
+    for (i = 0; i < 31; i++)
+    {
+        if (Alignment == alignmentBit)
+        {
+            break;
+        }
+        alignmentBit <<= 1;
+    }
+
+    if (i >= 31)
+    {
+        return 0;
+    }
+    else
+    {
+        return Alignment;
+    }
+}
+
+static int CalculateItemSize(int ItemSize, int Alignment)
+{
+    /*********************************/
+    int alignmentCount;
+    /*********************************/
+
+    if (ItemSize <= Alignment)
+    {
+        /**
+         *  The 2* accounts for the SList struct inside each memory block.
+         */
+        ItemSize = 2 * Alignment;
+    }
+    else
+    {
+        alignmentCount = ItemSize / Alignment;
+        if (ItemSize % Alignment != 0)
+        {
+            alignmentCount++;
+        }
+        /**
+         *  The +1 accounts for the SList struct inside each memory block.
+         */
+        ItemSize = ((alignmentCount + 1) * Alignment);
+    }
+
+    return ItemSize;
+}
+
+MemoryPool_t OSA_MemoryPoolCreate(
+    MemPool_t *MemPool, int ItemSize, void *PreallocatedMemory, int PreallocatedMemorySize, int Alignment)
+{
+    /*********************************/
+    unsigned char *ptr;
+    SlNode_t *Node;
+    osa_status_t status;
+    /*********************************/
+
+    Alignment = CalculateAndVerifyAlignment(Alignment);
+
+    if (Alignment == 0)
+    {
+        return NULL;
+    }
+
+    ItemSize = CalculateItemSize(ItemSize, Alignment);
+
+    status = OSA_MutexCreate((osa_mutex_handle_t)MemPool->Lock);
+    if (status != KOSA_StatusSuccess)
+    {
+        return NULL;
+    }
+
+    InitStack(&MemPool->Stack);
+    MemPool->ItemSize  = ItemSize;
+    MemPool->Alignment = Alignment;
+
+    ptr = (unsigned char *)PreallocatedMemory;
+
+    while (PreallocatedMemorySize >= ItemSize)
+    {
+        Node = (SlNode_t *)ptr;
+
+        PushOnStack(&MemPool->Stack, Node);
+        ptr += MemPool->ItemSize;
+        PreallocatedMemorySize -= MemPool->ItemSize;
+    }
+
+    return (MemoryPool_t)MemPool;
+}
+
+void *OSA_MemoryPoolAllocate(MemoryPool_t pool)
+{
+    /*********************************/
+    MemPool_t *MemPool;
+    SlNode_t *Node;
+    unsigned char *ptr = NULL;
+    /*********************************/
+
+    MemPool = (MemPool_t *)pool;
+
+    OSA_MutexLock((osa_mutex_handle_t)MemPool->Lock, osaWaitForever_c);
+
+    if (MemPool->Stack.Count == 0)
+    {
+        OSA_MutexUnlock((osa_mutex_handle_t)MemPool->Lock);
+        return NULL;
+    }
+
+    Node = PopOffStack(&MemPool->Stack);
+
+    OSA_MutexUnlock((osa_mutex_handle_t)MemPool->Lock);
+
+    if (Node == NULL)
+    {
+        return NULL;
+    }
+
+    ptr = ((unsigned char *)Node) + MemPool->Alignment;
+
+    return (void *)ptr;
+}
+
+void OSA_MemoryPoolFree(MemoryPool_t pool, void *memory)
+{
+    /*********************************/
+    MemPool_t *MemPool;
+    SlNode_t *Node;
+    unsigned char *ptr;
+    /*********************************/
+
+    if(memory != NULL)
+    {
+        MemPool = (MemPool_t *)pool;
+
+        ptr = ((unsigned char *)memory) - MemPool->Alignment;
+
+        Node = (SlNode_t *)ptr;
+
+        OSA_MutexLock((osa_mutex_handle_t)MemPool->Lock, osaWaitForever_c);
+
+        PushOnStack(&MemPool->Stack, Node);
+
+        OSA_MutexUnlock((osa_mutex_handle_t)MemPool->Lock);
+    }
+}
+
+#elif defined(FSL_RTOS_THREADX)
+
+MemoryPool_t OSA_MemoryPoolCreate(
+    MemPool_t *MemPool, int ItemSize, void *PreallocatedMemory, int PreallocatedMemorySize, int Alignment)
+{
+    int ret;
+
+    ret = tx_block_pool_create(MemPool, "BlkPool", ItemSize, PreallocatedMemory, PreallocatedMemorySize);
+
+    if (ret != TX_SUCCESS)
+    {
+        return NULL;
+    }
+
+    return (MemoryPool_t)MemPool;
+}
+
+void *OSA_MemoryPoolAllocate(MemoryPool_t pool)
+{
+    int ret;
+    void *memory;
+
+    ret = tx_block_allocate(pool, &memory, osaWaitNone_c);
+
+    if (ret != TX_SUCCESS)
+    {
+        return NULL;
+    }
+
+    return memory;
+}
+
+void OSA_MemoryPoolFree(MemoryPool_t pool, void *memory)
+{
+    tx_block_release(memory);
+}
+
+#endif
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/mem_pool_config.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/mem_pool_config.c
new file mode 100644
index 0000000000..9307f156fd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/mem_pool_config.c
@@ -0,0 +1,495 @@
+/*
+ *  Copyright 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "mem_pool_config.h"
+
+#if CONFIG_MEM_POOLS
+
+#define ALIGNED_START(x)
+
+/******************************** Pool ID 0 ********************************/
+// Pool 0 buffer pool sizes and buffer counts
+#define POOL_ID0_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID0_BUF0_CNT 1
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID0_BUF0_SZ 1500
+
+// Pool 0 total buffer size calculation
+#define POOL_ID0_SZ (POOL_ID0_BUF0_SZ * POOL_ID0_BUF0_CNT)
+
+// Pool 0 block pool pointer overhead calculation
+#define POOL_ID0_OVERHEAD ((POOL_ID0_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 0 total pool size calculation
+#define POOL_ID0_POOL_SZ (POOL_ID0_SZ + POOL_ID0_OVERHEAD)
+
+/******************************** Pool ID 1 ********************************/
+// Pool 1 buffer pool sizes and buffer counts
+#define POOL_ID1_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID1_BUF0_CNT 2
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID1_BUF0_SZ 5200
+
+// Pool 1 total buffer size calculation
+#define POOL_ID1_SZ (POOL_ID1_BUF0_SZ * POOL_ID1_BUF0_CNT)
+
+// Pool 1 block pool pointer overhead calculation
+#define POOL_ID1_OVERHEAD ((POOL_ID1_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 1 total pool size calculation
+#define POOL_ID1_POOL_SZ (POOL_ID1_SZ + POOL_ID1_OVERHEAD)
+
+/******************************** Pool ID 2 ********************************/
+// Pool 2 buffer pool sizes and buffer counts
+#define POOL_ID2_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID2_BUF0_CNT 128
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID2_BUF0_SZ 32
+
+// Pool 2 total buffer size calculation
+#define POOL_ID2_SZ (POOL_ID2_BUF0_SZ * POOL_ID2_BUF0_CNT)
+
+// Pool 2 block pool pointer overhead calculation
+#define POOL_ID2_OVERHEAD ((POOL_ID2_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 2 total pool size calculation
+#define POOL_ID2_POOL_SZ (POOL_ID2_SZ + POOL_ID2_OVERHEAD)
+
+/******************************** Pool ID 3 ********************************/
+// Pool 3 buffer pool sizes and buffer counts
+#define POOL_ID3_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID3_BUF0_CNT 256
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID3_BUF0_SZ 128
+
+// Pool 3 total buffer size calculation
+#define POOL_ID3_SZ (POOL_ID3_BUF0_SZ * POOL_ID3_BUF0_CNT)
+
+// Pool 3 block pool pointer overhead calculation
+#define POOL_ID3_OVERHEAD ((POOL_ID3_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 3 total pool size calculation
+#define POOL_ID3_POOL_SZ (POOL_ID3_SZ + POOL_ID3_OVERHEAD)
+
+/******************************** Pool ID 4 ********************************/
+// Pool 4 buffer pool sizes and buffer counts
+#define POOL_ID4_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID4_BUF0_CNT 8
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID4_BUF0_SZ 256
+
+// Pool 4 total buffer size calculation
+#define POOL_ID4_SZ (POOL_ID4_BUF0_SZ * POOL_ID4_BUF0_CNT)
+
+// Pool 4 block pool pointer overhead calculation
+#define POOL_ID4_OVERHEAD ((POOL_ID4_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 4 total pool size calculation
+#define POOL_ID4_POOL_SZ (POOL_ID4_SZ + POOL_ID4_OVERHEAD)
+
+/******************************** Pool ID 5 ********************************/
+// Pool 5 buffer pool sizes and buffer counts
+#define POOL_ID5_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID5_BUF0_CNT 4
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID5_BUF0_SZ 512
+
+// Pool 5 total buffer size calculation
+#define POOL_ID5_SZ (POOL_ID5_BUF0_SZ * POOL_ID5_BUF0_CNT)
+
+// Pool 5 block pool pointer overhead calculation
+#define POOL_ID5_OVERHEAD ((POOL_ID5_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 5 total pool size calculation
+#define POOL_ID5_POOL_SZ (POOL_ID5_SZ + POOL_ID5_OVERHEAD)
+
+/******************************** Pool ID 6 ********************************/
+// Pool 6 buffer pool sizes and buffer counts
+#define POOL_ID6_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID6_BUF0_CNT 4
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID6_BUF0_SZ 768
+
+// Pool 6 total buffer size calculation
+#define POOL_ID6_SZ (POOL_ID6_BUF0_SZ * POOL_ID6_BUF0_CNT)
+
+// Pool 6 block pool pointer overhead calculation
+#define POOL_ID6_OVERHEAD ((POOL_ID6_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 6 total pool size calculation
+#define POOL_ID6_POOL_SZ (POOL_ID6_SZ + POOL_ID6_OVERHEAD)
+
+/******************************** Pool ID 7 ********************************/
+// Pool 7 buffer pool sizes and buffer counts
+#define POOL_ID7_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID7_BUF0_CNT 4
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID7_BUF0_SZ 1024
+
+// Pool 7 total buffer size calculation
+#define POOL_ID7_SZ (POOL_ID7_BUF0_SZ * POOL_ID7_BUF0_CNT)
+
+// Pool 7 block pool pointer overhead calculation
+#define POOL_ID7_OVERHEAD ((POOL_ID7_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 7 total pool size calculation
+#define POOL_ID7_POOL_SZ (POOL_ID7_SZ + POOL_ID7_OVERHEAD)
+
+/******************************** Pool ID 8 ********************************/
+// Pool 8 buffer pool sizes and buffer counts
+#define POOL_ID8_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID8_BUF0_CNT 4
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID8_BUF0_SZ 1280
+
+// Pool 8 total buffer size calculation
+#define POOL_ID8_SZ (POOL_ID8_BUF0_SZ * POOL_ID8_BUF0_CNT)
+
+// Pool 8 block pool pointer overhead calculation
+#define POOL_ID8_OVERHEAD ((POOL_ID8_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 8 total pool size calculation
+#define POOL_ID8_POOL_SZ (POOL_ID8_SZ + POOL_ID8_OVERHEAD)
+
+/******************************** Pool ID 9 ********************************/
+// Pool 9 buffer pool sizes and buffer counts
+#define POOL_ID9_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID9_BUF0_CNT 4
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID9_BUF0_SZ 1536
+
+// Pool 9 total buffer size calculation
+#define POOL_ID9_SZ (POOL_ID9_BUF0_SZ * POOL_ID9_BUF0_CNT)
+
+// Pool 9 block pool pointer overhead calculation
+#define POOL_ID9_OVERHEAD ((POOL_ID9_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 9 total pool size calculation
+#define POOL_ID9_POOL_SZ (POOL_ID9_SZ + POOL_ID9_OVERHEAD)
+
+/******************************** Pool ID 10 ********************************/
+// Pool 10 buffer pool sizes and buffer counts
+#define POOL_ID10_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID10_BUF0_CNT 1
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID10_BUF0_SZ 1792
+
+// Pool 10 total buffer size calculation
+#define POOL_ID10_SZ (POOL_ID10_BUF0_SZ * POOL_ID10_BUF0_CNT)
+
+// Pool 10 block pool pointer overhead calculation
+#define POOL_ID10_OVERHEAD ((POOL_ID10_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 10 total pool size calculation
+#define POOL_ID10_POOL_SZ (POOL_ID10_SZ + POOL_ID10_OVERHEAD)
+
+/******************************** Pool ID 11 ********************************/
+// Pool 11 buffer pool sizes and buffer counts
+#define POOL_ID11_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID11_BUF0_CNT 4
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID11_BUF0_SZ 2048
+
+// Pool 11 total buffer size calculation
+#define POOL_ID11_SZ (POOL_ID11_BUF0_SZ * POOL_ID11_BUF0_CNT)
+
+// Pool 11 block pool pointer overhead calculation
+#define POOL_ID11_OVERHEAD ((POOL_ID11_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 11 total pool size calculation
+#define POOL_ID11_POOL_SZ (POOL_ID11_SZ + POOL_ID11_OVERHEAD)
+
+/******************************** Pool ID 12 ********************************/
+// Pool 12 buffer pool sizes and buffer counts
+#define POOL_ID12_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID12_BUF0_CNT 1
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID12_BUF0_SZ 2560
+
+// Pool 12 total buffer size calculation
+#define POOL_ID12_SZ (POOL_ID12_BUF0_SZ * POOL_ID12_BUF0_CNT)
+
+// Pool 12 block pool pointer overhead calculation
+#define POOL_ID12_OVERHEAD ((POOL_ID12_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 12 total pool size calculation
+#define POOL_ID12_POOL_SZ (POOL_ID12_SZ + POOL_ID12_OVERHEAD)
+
+/******************************** Pool ID 13 ********************************/
+// Pool 13 buffer pool sizes and buffer counts
+#define POOL_ID13_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID13_BUF0_CNT 1
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID13_BUF0_SZ 3072
+
+// Pool 13 total buffer size calculation
+#define POOL_ID13_SZ (POOL_ID13_BUF0_SZ * POOL_ID13_BUF0_CNT)
+
+// Pool 13 block pool pointer overhead calculation
+#define POOL_ID13_OVERHEAD ((POOL_ID13_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 13 total pool size calculation
+#define POOL_ID13_POOL_SZ (POOL_ID13_SZ + POOL_ID13_OVERHEAD)
+
+/******************************** Pool ID 14 ********************************/
+// Pool 14 buffer pool sizes and buffer counts
+#define POOL_ID14_BLOCK_POOL_CNT 1
+
+// Buffer 0
+
+#define POOL_ID14_BUF0_CNT 1
+
+/* Buffer descriptor size already part of TX size so don't add again */
+#define POOL_ID14_BUF0_SZ 4096
+
+// Pool 14 total buffer size calculation
+#define POOL_ID14_SZ (POOL_ID14_BUF0_SZ * POOL_ID14_BUF0_CNT)
+
+// Pool 14 block pool pointer overhead calculation
+#define POOL_ID14_OVERHEAD ((POOL_ID14_BUF0_CNT)*POOL_OVERHEAD)
+
+// Pool 14 total pool size calculation
+#define POOL_ID14_POOL_SZ (POOL_ID14_SZ + POOL_ID14_OVERHEAD)
+
+MemoryPool_t pmAdapterMemoryPool;
+MemoryPool_t pmPrivateMemoryPool;
+MemoryPool_t buf_32_MemoryPool;
+MemoryPool_t buf_128_MemoryPool;
+MemoryPool_t buf_256_MemoryPool;
+MemoryPool_t buf_512_MemoryPool;
+MemoryPool_t buf_768_MemoryPool;
+MemoryPool_t buf_1024_MemoryPool;
+MemoryPool_t buf_1280_MemoryPool;
+MemoryPool_t buf_1536_MemoryPool;
+MemoryPool_t buf_1792_MemoryPool;
+MemoryPool_t buf_2048_MemoryPool;
+MemoryPool_t buf_2560_MemoryPool;
+MemoryPool_t buf_3072_MemoryPool;
+MemoryPool_t buf_4096_MemoryPool;
+
+static MemPool_t pmAdapterMemPool;
+static MemPool_t pmPrivateMemPool;
+static MemPool_t buf_32_MemPool;
+static MemPool_t buf_128_MemPool;
+static MemPool_t buf_256_MemPool;
+static MemPool_t buf_512_MemPool;
+static MemPool_t buf_768_MemPool;
+static MemPool_t buf_1024_MemPool;
+static MemPool_t buf_1280_MemPool;
+static MemPool_t buf_1536_MemPool;
+static MemPool_t buf_1792_MemPool;
+static MemPool_t buf_2048_MemPool;
+static MemPool_t buf_2560_MemPool;
+static MemPool_t buf_3072_MemPool;
+static MemPool_t buf_4096_MemPool;
+
+/***************** Preallocated pmAdapter pool memory ************************/
+SDK_ALIGN(uint8_t pmAdapterBufferPool[POOL_ID0_POOL_SZ], 32);
+
+/***************** Preallocated pmPrivate pool memory ************************/
+SDK_ALIGN(uint8_t pmPrivateBufferPool[POOL_ID1_POOL_SZ], 32);
+
+/***************** Preallocated buffer 32 pool memory ************************/
+SDK_ALIGN(uint8_t buf_32_BufferPool[POOL_ID2_POOL_SZ], 32);
+
+SDK_ALIGN(uint8_t buf_128_BufferPool[POOL_ID3_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_256_BufferPool[POOL_ID4_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_512_BufferPool[POOL_ID5_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_768_BufferPool[POOL_ID6_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_1024_BufferPool[POOL_ID7_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_1280_BufferPool[POOL_ID8_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_1536_BufferPool[POOL_ID9_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_1792_BufferPool[POOL_ID10_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_2048_BufferPool[POOL_ID11_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_2560_BufferPool[POOL_ID12_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_3072_BufferPool[POOL_ID13_POOL_SZ], 32);
+SDK_ALIGN(uint8_t buf_4096_BufferPool[POOL_ID14_POOL_SZ], 32);
+
+int mem_pool_init()
+{
+    int ret = -1;
+
+    pmAdapterMemoryPool =
+        OSA_MemoryPoolCreate(&pmAdapterMemPool, POOL_ID0_BUF0_SZ, (void *)pmAdapterBufferPool, POOL_ID0_POOL_SZ, 0);
+    if (pmAdapterMemoryPool == NULL)
+    {
+        mpool_e("Failed to init pmAdapter Buffer Pool");
+        return ret;
+    }
+
+    pmPrivateMemoryPool =
+        OSA_MemoryPoolCreate(&pmPrivateMemPool, POOL_ID1_BUF0_SZ, (void *)pmPrivateBufferPool, POOL_ID1_POOL_SZ, 0);
+    if (pmPrivateMemoryPool == NULL)
+    {
+        mpool_e("Failed to init pmAdapter Buffer Pool");
+        return ret;
+    }
+
+    buf_32_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_32_MemPool, POOL_ID2_BUF0_SZ, (void *)buf_32_BufferPool, POOL_ID2_POOL_SZ, 0);
+    if (buf_32_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 32 Buffer Pool");
+        return ret;
+    }
+
+    buf_128_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_128_MemPool, POOL_ID3_BUF0_SZ, (void *)buf_128_BufferPool, POOL_ID3_POOL_SZ, 0);
+    if (buf_128_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 128 Buffer Pool");
+        return ret;
+    }
+
+    buf_256_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_256_MemPool, POOL_ID4_BUF0_SZ, (void *)buf_256_BufferPool, POOL_ID4_POOL_SZ, 0);
+    if (buf_256_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 256 Buffer Pool");
+        return ret;
+    }
+
+    buf_512_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_512_MemPool, POOL_ID5_BUF0_SZ, (void *)buf_512_BufferPool, POOL_ID5_POOL_SZ, 0);
+    if (buf_512_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 512 Buffer Pool");
+        return ret;
+    }
+
+    buf_768_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_768_MemPool, POOL_ID6_BUF0_SZ, (void *)buf_768_BufferPool, POOL_ID6_POOL_SZ, 0);
+    if (buf_768_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 768 Buffer Pool");
+        return ret;
+    }
+
+    buf_1024_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_1024_MemPool, POOL_ID7_BUF0_SZ, (void *)buf_1024_BufferPool, POOL_ID7_POOL_SZ, 0);
+    if (buf_1024_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 1024 Buffer Pool");
+        return ret;
+    }
+
+    buf_1280_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_1280_MemPool, POOL_ID8_BUF0_SZ, (void *)buf_1280_BufferPool, POOL_ID8_POOL_SZ, 0);
+    if (buf_1280_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 1280 Buffer Pool");
+        return ret;
+    }
+
+    buf_1536_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_1536_MemPool, POOL_ID9_BUF0_SZ, (void *)buf_1536_BufferPool, POOL_ID9_POOL_SZ, 0);
+    if (buf_1536_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 1536 Buffer Pool");
+        return ret;
+    }
+
+    buf_1792_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_1792_MemPool, POOL_ID10_BUF0_SZ, (void *)buf_1792_BufferPool, POOL_ID10_POOL_SZ, 0);
+    if (buf_1792_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 1792 Buffer Pool");
+        return ret;
+    }
+
+    buf_2048_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_2048_MemPool, POOL_ID11_BUF0_SZ, (void *)buf_2048_BufferPool, POOL_ID11_POOL_SZ, 0);
+    if (buf_2048_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 2048 Buffer Pool");
+        return ret;
+    }
+
+    buf_2560_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_2560_MemPool, POOL_ID12_BUF0_SZ, (void *)buf_2560_BufferPool, POOL_ID12_POOL_SZ, 0);
+    if (buf_2560_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 2560 Buffer Pool");
+        return ret;
+    }
+
+    buf_3072_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_3072_MemPool, POOL_ID13_BUF0_SZ, (void *)buf_3072_BufferPool, POOL_ID13_POOL_SZ, 0);
+    if (buf_3072_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 3072 Buffer Pool");
+        return ret;
+    }
+
+    buf_4096_MemoryPool =
+        OSA_MemoryPoolCreate(&buf_4096_MemPool, POOL_ID14_BUF0_SZ, (void *)buf_4096_BufferPool, POOL_ID14_POOL_SZ, 0);
+    if (buf_4096_MemoryPool == NULL)
+    {
+        mpool_e("Failed to init buf 4096 Buffer Pool");
+        return ret;
+    }
+
+    return 0;
+}
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa.c
new file mode 100644
index 0000000000..dc0e30abc3
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa.c
@@ -0,0 +1,145 @@
+/** @file osa.c
+ *
+ *  @brief OS Abstraction API
+ *
+ *  Copyright 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <inttypes.h>
+#include <stdio.h>
+#include <osa.h>
+#include <wmlog.h>
+
+/** Check if cpu is in isr context
+ *
+ * \return bool value - true if cpu is in isr context
+ */
+bool is_isr_context(void)
+{
+#ifdef __CA7_REV
+    return (0U != if (SystemGetIRQNestingLevel()))
+#else /* __CA7_REV */
+    return (0U != __get_IPSR());
+#endif
+}
+
+/*** OS Reader Writer Locks ***/
+int OSA_RWLockCreate(osa_rw_lock_t *plock, const char *mutex_name, const char *lock_name)
+{
+    return OSA_RWLockCreateWithCB(plock, mutex_name, lock_name, NULL);
+}
+
+int OSA_RWLockCreateWithCB(osa_rw_lock_t *plock, const char *mutex_name, const char *lock_name, cb_fn r_fn)
+{
+    osa_status_t status;
+
+    status = OSA_MutexCreate((osa_mutex_handle_t)plock->reader_mutex);
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+    status = OSA_MutexCreate((osa_mutex_handle_t)plock->write_mutex);
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)plock->rw_lock);
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+    OSA_SemaphorePost((osa_semaphore_handle_t)plock->rw_lock);
+    plock->reader_count = 0;
+    plock->reader_cb    = r_fn;
+    return WM_SUCCESS;
+}
+
+int OSA_RWLockReadLock(osa_rw_lock_t *lock, unsigned int wait_time)
+{
+    int ret;
+    osa_status_t status = OSA_MutexLock((osa_mutex_handle_t)lock->reader_mutex, osaWaitForever_c);
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+    lock->reader_count++;
+    if (lock->reader_count == 1U)
+    {
+        if (lock->reader_cb != NULL)
+        {
+            ret = lock->reader_cb(lock, wait_time);
+            if (ret != WM_SUCCESS)
+            {
+                lock->reader_count--;
+                (void)OSA_MutexUnlock((osa_mutex_handle_t)lock->reader_mutex);
+                return ret;
+            }
+        }
+        else
+        {
+            /* If  1 it is the first reader and
+             * if writer is not active, reader will get access
+             * else reader will block.
+             */
+            status = OSA_SemaphoreWait((osa_semaphore_handle_t)lock->rw_lock, wait_time);
+            if (status != KOSA_StatusSuccess)
+            {
+                lock->reader_count--;
+                (void)OSA_MutexUnlock((osa_mutex_handle_t)lock->reader_mutex);
+                return -WM_FAIL;
+            }
+        }
+    }
+    (void)OSA_MutexUnlock((osa_mutex_handle_t)lock->reader_mutex);
+    return WM_SUCCESS;
+}
+
+int OSA_RWLockReadUnlock(osa_rw_lock_t *lock)
+{
+    osa_status_t status = OSA_MutexLock((osa_mutex_handle_t)lock->reader_mutex, osaWaitForever_c);
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+    lock->reader_count--;
+    if (lock->reader_count == 0U)
+    {
+        /* This is last reader so
+         * give a chance to writer now
+         */
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)lock->rw_lock);
+    }
+    (void)OSA_MutexUnlock((osa_mutex_handle_t)lock->reader_mutex);
+    return WM_SUCCESS;
+}
+
+int OSA_RWLockWriteLock(osa_rw_lock_t *lock, unsigned int wait_time)
+{
+    osa_status_t status = OSA_SemaphoreWait((osa_semaphore_handle_t)lock->rw_lock, wait_time);
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+void OSA_RWLockWriteUnlock(osa_rw_lock_t *lock)
+{
+    (void)OSA_SemaphorePost((osa_semaphore_handle_t)lock->rw_lock);
+}
+
+void OSA_RWLockDestroy(osa_rw_lock_t *lock)
+{
+    lock->reader_cb = NULL;
+
+    (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)lock->rw_lock);
+
+    (void)OSA_MutexDestroy((osa_mutex_handle_t)lock->reader_mutex);
+
+    (void)OSA_MutexDestroy((osa_mutex_handle_t)lock->write_mutex);
+
+    lock->reader_count = 0;
+}
\ No newline at end of file
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa_freertos.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa_freertos.c
new file mode 100644
index 0000000000..94b70be013
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa_freertos.c
@@ -0,0 +1,558 @@
+/*
+ * FreeRTOS Kernel V11.0.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/** @file osa_freertos.c
+ *
+ *  @brief OS FreeRTOS interaction APIs
+ *
+ */
+#include <inttypes.h>
+#include <stdio.h>
+#include <osa.h>
+#include <wmlog.h>
+
+#if defined(SDK_OS_FREE_RTOS)
+
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+
+/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+used by the Idle task. */
+void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer,
+                                   StackType_t **ppxIdleTaskStackBuffer,
+                                   uint32_t *pulIdleTaskStackSize)
+{
+    /* If the buffers to be provided to the Idle task are declared inside this
+    function then they must be declared static - otherwise they will be allocated on
+    the stack and so not exists after this function exits. */
+    static StaticTask_t xIdleTaskTCB;
+    static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE];
+
+    /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+    state will be stored. */
+    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+    /* Pass out the array that will be used as the Idle task's stack. */
+    *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+    /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+    *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+/*-----------------------------------------------------------*/
+
+/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+application must provide an implementation of vApplicationGetTimerTaskMemory()
+to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer,
+                                    StackType_t **ppxTimerTaskStackBuffer,
+                                    uint32_t *pulTimerTaskStackSize)
+{
+    /* If the buffers to be provided to the Timer task are declared inside this
+    function then they must be declared static - otherwise they will be allocated on
+    the stack and so not exists after this function exits. */
+    static StaticTask_t xTimerTaskTCB;
+    static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH];
+
+    /* Pass out a pointer to the StaticTask_t structure in which the Timer
+    task's state will be stored. */
+    *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+    /* Pass out the array that will be used as the Timer task's stack. */
+    *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+    /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
+    *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+#endif
+
+osa_status_t OSA_TimerCreate(osa_timer_handle_t timerHandle,
+                             osa_timer_tick ticks,
+                             void (*call_back)(osa_timer_arg_t),
+                             void *cb_arg,
+                             osa_timer_t reload,
+                             osa_timer_activate_t activate)
+{
+    int auto_reload = (reload == KOSA_TimerOnce) ? pdFALSE : pdTRUE;
+
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    assert((sizeof(osa_timer_handle_t) + sizeof(StaticTimer_t)) == OSA_TIMER_HANDLE_SIZE);
+#else
+    assert(sizeof(osa_timer_handle_t) == OSA_TIMER_HANDLE_SIZE);
+#endif
+    assert(NULL != timerHandle);
+
+    union
+    {
+        TimerHandle_t tm;
+        uint32_t timerhandle;
+    } xTimerHandle;
+
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+    xTimerHandle.tm =
+        xTimerCreateStatic(NULL, ticks, (UBaseType_t)auto_reload, cb_arg, call_back,
+                           (StaticTimer_t *)(void *)((uint8_t *)timerHandle + sizeof(osa_timer_handle_t)));
+#else
+    xTimerHandle.tm = xTimerCreate(NULL, ticks, (UBaseType_t)auto_reload, cb_arg, call_back);
+#endif
+    if (NULL != xTimerHandle.tm)
+    {
+        *(uint32_t *)timerHandle = xTimerHandle.timerhandle;
+
+        if (activate == OSA_TIMER_AUTO_ACTIVATE)
+        {
+            return OSA_TimerActivate(timerHandle);
+        }
+
+        return KOSA_StatusSuccess;
+    }
+
+    return KOSA_StatusError;
+}
+
+osa_status_t OSA_TimerActivate(osa_timer_handle_t timerHandle)
+{
+    assert(NULL != timerHandle);
+    osa_status_t status = KOSA_StatusError;
+    TimerHandle_t tm    = (TimerHandle_t)(void *)(uint32_t *)(*(uint32_t *)timerHandle);
+
+    if (0U != __get_IPSR())
+    {
+        portBASE_TYPE taskToWake = (portBASE_TYPE)pdFALSE;
+
+        if (((BaseType_t)1) == (BaseType_t)xTimerStartFromISR(tm, &taskToWake))
+        {
+            portYIELD_FROM_ISR(((bool)(taskToWake)));
+            status = KOSA_StatusSuccess;
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+    else
+    {
+        if (((BaseType_t)1) == (BaseType_t)xTimerStart(tm, 0))
+        {
+            status = KOSA_StatusSuccess; /* sync object given */
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+
+    return status;
+}
+
+osa_status_t OSA_TimerChange(osa_timer_handle_t timerHandle, osa_timer_tick ntime, osa_timer_tick block_time)
+{
+    assert(NULL != timerHandle);
+    osa_status_t status = KOSA_StatusError;
+    TimerHandle_t tm    = (TimerHandle_t)(void *)(uint32_t *)(*(uint32_t *)timerHandle);
+
+    if (0U != __get_IPSR())
+    {
+        portBASE_TYPE taskToWake = (portBASE_TYPE)pdFALSE;
+
+        if (((BaseType_t)1) == (BaseType_t)xTimerChangePeriodFromISR(tm, ntime, &taskToWake))
+        {
+            portYIELD_FROM_ISR(((bool)(taskToWake)));
+            status = KOSA_StatusSuccess;
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+    else
+    {
+        if (((BaseType_t)1) == (BaseType_t)xTimerChangePeriod(tm, ntime, 100))
+        {
+            status = KOSA_StatusSuccess; /* sync object given */
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+
+    return status;
+}
+
+bool OSA_TimerIsRunning(osa_timer_handle_t timerHandle)
+{
+    assert(NULL != timerHandle);
+    TimerHandle_t tm = (TimerHandle_t)(void *)(uint32_t *)(*(uint32_t *)timerHandle);
+
+    if (((BaseType_t)0) == (BaseType_t)xTimerIsTimerActive(tm))
+    {
+        return false; /* Timer not active */
+    }
+    else
+    {
+        return true; /* Timer active */
+    }
+}
+
+void *OSA_TimerGetContext(osa_timer_handle_t timerHandle)
+{
+    assert(NULL != timerHandle);
+    TimerHandle_t tm = (TimerHandle_t)(void *)(uint32_t *)(*(uint32_t *)timerHandle);
+
+    return pvTimerGetTimerID(tm);
+}
+
+osa_status_t OSA_TimerReset(osa_timer_handle_t timerHandle)
+{
+    assert(NULL != timerHandle);
+    osa_status_t status = KOSA_StatusError;
+    TimerHandle_t tm    = (TimerHandle_t)(void *)(uint32_t *)(*(uint32_t *)timerHandle);
+
+    if (0U != __get_IPSR())
+    {
+        portBASE_TYPE taskToWake = (portBASE_TYPE)pdFALSE;
+
+        if (((BaseType_t)1) == (BaseType_t)xTimerResetFromISR(tm, &taskToWake))
+        {
+            portYIELD_FROM_ISR(((bool)(taskToWake)));
+            status = KOSA_StatusSuccess;
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+    else
+    {
+        if (((BaseType_t)1) == (BaseType_t)xTimerReset(tm, 0))
+        {
+            status = KOSA_StatusSuccess; /* sync object given */
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+
+    return status;
+}
+
+osa_status_t OSA_TimerDeactivate(osa_timer_handle_t timerHandle)
+{
+    assert(NULL != timerHandle);
+    osa_status_t status = KOSA_StatusError;
+    TimerHandle_t tm    = (TimerHandle_t)(void *)(uint32_t *)(*(uint32_t *)timerHandle);
+
+    if (0U != __get_IPSR())
+    {
+        portBASE_TYPE taskToWake = (portBASE_TYPE)pdFALSE;
+
+        if (((BaseType_t)1) == (BaseType_t)xTimerStopFromISR(tm, &taskToWake))
+        {
+            portYIELD_FROM_ISR(((bool)(taskToWake)));
+            status = KOSA_StatusSuccess;
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+    else
+    {
+        if (((BaseType_t)1) == (BaseType_t)xTimerStop(tm, 0))
+        {
+            status = KOSA_StatusSuccess; /* sync object given */
+        }
+        else
+        {
+            status = KOSA_StatusError;
+        }
+    }
+
+    return status;
+}
+
+osa_status_t OSA_TimerDestroy(osa_timer_handle_t timerHandle)
+{
+    assert(NULL != timerHandle);
+    TimerHandle_t tm = (TimerHandle_t)(void *)(uint32_t *)(*(uint32_t *)timerHandle);
+    int ret;
+
+    /* Below timer handle invalidation needs to be protected as a context
+     * switch may create issues if same handle is used before
+     * invalidation.
+     */
+    OSA_SR_ALLOC();
+
+    OSA_ENTER_CRITICAL();
+    /* Note: Block time is set as 0, thus signifying non-blocking
+       API. Can be changed later if required. */
+    ret = xTimerDelete(tm, 0);
+
+    OSA_EXIT_CRITICAL();
+
+    return ret == pdPASS ? KOSA_StatusSuccess : KOSA_StatusError;
+}
+
+void (*g_os_tick_hooks[MAX_CUSTOM_HOOKS])(void) = {NULL};
+void (*g_os_idle_hooks[MAX_CUSTOM_HOOKS])(void) = {NULL};
+
+/** The FreeRTOS Tick hook function. */
+void vApplicationTickHook(void)
+{
+    int i;
+
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_tick_hooks[i] != NULL)
+        {
+            g_os_tick_hooks[i]();
+        }
+    }
+}
+
+void vApplicationIdleHook(void)
+{
+    int i;
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_idle_hooks[i] != NULL)
+        {
+            g_os_idle_hooks[i]();
+        }
+    }
+}
+
+int OSA_SetupIdleFunction(void (*func)(void))
+{
+    unsigned int i;
+
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_idle_hooks[i] != NULL && g_os_idle_hooks[i] == func)
+        {
+            return WM_SUCCESS;
+        }
+    }
+
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_idle_hooks[i] == NULL)
+        {
+            g_os_idle_hooks[i] = func;
+            break;
+        }
+    }
+
+    if (i == MAX_CUSTOM_HOOKS)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int OSA_SetupTickFunction(void (*func)(void))
+{
+    unsigned int i;
+
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_tick_hooks[i] != NULL && g_os_tick_hooks[i] == func)
+        {
+            return WM_SUCCESS;
+        }
+    }
+
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_tick_hooks[i] == NULL)
+        {
+            g_os_tick_hooks[i] = func;
+            break;
+        }
+    }
+
+    if (i == MAX_CUSTOM_HOOKS)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int OSA_RemoveIdleFunction(void (*func)(void))
+{
+    unsigned int i;
+
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_idle_hooks[i] == func)
+        {
+            g_os_idle_hooks[i] = NULL;
+            break;
+        }
+    }
+
+    if (i == MAX_CUSTOM_HOOKS)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int OSA_RemoveTickFunction(void (*func)(void))
+{
+    unsigned int i;
+
+    for (i = 0; i < MAX_CUSTOM_HOOKS; i++)
+    {
+        if (g_os_tick_hooks[i] == func)
+        {
+            g_os_tick_hooks[i] = NULL;
+            break;
+        }
+    }
+
+    if (i == MAX_CUSTOM_HOOKS)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_HEAP_STAT
+/** This function dumps complete statistics
+ *  of the heap memory.
+ */
+void OSA_DumpMemStats(void)
+{
+    OSA_SR_ALLOC()
+    OSA_ENTER_CRITICAL();
+
+    HeapStats_t HS;
+
+    HS.xAvailableHeapSpaceInBytes      = 0;
+    HS.xSizeOfLargestFreeBlockInBytes  = 0;
+    HS.xSizeOfSmallestFreeBlockInBytes = 0;
+    HS.xNumberOfFreeBlocks             = 0;
+    HS.xNumberOfSuccessfulAllocations  = 0;
+    HS.xNumberOfSuccessfulFrees        = 0;
+    HS.xMinimumEverFreeBytesRemaining  = 0;
+
+    vPortGetHeapStats(&HS);
+
+    (void)PRINTF("\n\r");
+    (void)PRINTF("Heap size ---------------------- : %d\n\r", HS.xAvailableHeapSpaceInBytes);
+    (void)PRINTF("Largest Free Block size -------- : %d\n\r", HS.xSizeOfLargestFreeBlockInBytes);
+    (void)PRINTF("Smallest Free Block size ------- : %d\n\r", HS.xSizeOfSmallestFreeBlockInBytes);
+    (void)PRINTF("Number of Free Blocks ---------- : %d\n\r", HS.xNumberOfFreeBlocks);
+    (void)PRINTF("Total successful allocations --- : %d\n\r", HS.xNumberOfSuccessfulAllocations);
+    (void)PRINTF("Total successful frees --------- : %d\n\r", HS.xNumberOfSuccessfulFrees);
+    (void)PRINTF("Min Free since system boot ----- : %d\n\r", HS.xMinimumEverFreeBytesRemaining);
+
+    OSA_EXIT_CRITICAL()
+}
+#endif
+void OSA_ThreadSelfComplete(osa_task_handle_t taskHandle)
+{
+    /* Suspend self until someone calls delete. This is required because in
+     * freeRTOS, main functions of a thread cannot return.
+     */
+    if (taskHandle != NULL)
+    {
+        PRINTF("OSA: Thread Complete: %p\r\n", taskHandle);
+        vTaskSuspend(taskHandle);
+    }
+    else
+    {
+        PRINTF("OSA: Thread Complete: SELF\r\n");
+        vTaskSuspend(NULL);
+    }
+
+    /*
+     * We do not want this function to return ever.
+     */
+    while (true)
+    {
+        OSA_TimeDelay(60000);
+    }
+}
+
+/* the OS timer register is loaded with CNTMAX */
+#define CNTMAX                 ((SystemCoreClock / configTICK_RATE_HZ) - 1UL)
+#define CPU_CLOCK_TICKSPERUSEC (SystemCoreClock / 1000000U)
+#define USECSPERTICK           (1000000U / configTICK_RATE_HZ)
+
+/* returns time in micro-secs since time began */
+unsigned int OSA_GetTimestamp(void)
+{
+    uint32_t nticks;
+    uint32_t counter;
+
+    vPortEnterCritical();
+    nticks  = xTaskGetTickCount();
+    counter = SysTick->VAL;
+
+    /*
+     * If this is called after SysTick counter
+     * expired but before SysTick Handler got a
+     * chance to run, then set the return value
+     * to the start of next tick.
+     */
+    if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U)
+    {
+        nticks++;
+        counter = CNTMAX;
+    }
+
+    vPortExitCritical();
+    return ((CNTMAX - counter) / CPU_CLOCK_TICKSPERUSEC) + (nticks * USECSPERTICK);
+}
+
+uint32_t OSA_MsgQWaiting(osa_msgq_handle_t msgqHandle)
+{
+    uint32_t nmsg = 0;
+    assert(NULL != msgqHandle);
+    QueueHandle_t handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+    nmsg = (uint32_t)uxQueueMessagesWaiting(handler);
+
+    return nmsg;
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa_freertos.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa_freertos.h
new file mode 100644
index 0000000000..b180c032ad
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/osa_freertos.h
@@ -0,0 +1,153 @@
+/*
+ *  Copyright 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _OSA_FREERTOS_H_
+#define _OSA_FREERTOS_H_
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+#include "timers.h"
+#include "portmacro.h"
+
+#ifndef configMAX_PRIORITIES
+#error Define configMAX_PRIORITIES in FreeRTOSConfig.h
+#elif configMAX_PRIORITIES < 5
+#error configMAX_PRIORITIES must be defined to be greater than or equal to 5
+#endif
+/*** Priority setting ***/
+#define OSA_PRIORITY(x) (PRIORITY_RTOS_TO_OSA((configMAX_PRIORITIES - x)))
+#define WLAN_TASK_PRI_HIGHEST (OSA_PRIORITY(1))
+#define WLAN_TASK_PRI_HIGH    (OSA_PRIORITY(2))
+#define WLAN_TASK_PRI_NORMAL  (OSA_PRIORITY(3))
+#define WLAN_TASK_PRI_LOW     (OSA_PRIORITY(4))
+#define WLAN_TASK_PRI_IDLE    (OSA_PRIORITY(5))
+
+/**
+ *  Handle for memory pools.
+ *
+ *  These are fixed allocation size memory areas.
+ */
+typedef void * MemoryPool_t;
+
+#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \
+    !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U)))
+
+#define CONFIG_MEM_POOLS 1
+
+#include <mem_pool_config.h>
+
+#endif
+
+/*** Timer Management ***/
+/**
+ * OS Timer Activate Options
+ */
+typedef enum osa_timer_activation
+{
+    /** Start the timer on creation. */
+    OSA_TIMER_AUTO_ACTIVATE,
+    /** Do not start the timer on creation. */
+    OSA_TIMER_NO_ACTIVATE,
+} osa_timer_activate_t;
+
+typedef TimerHandle_t osa_timer_arg_t;
+typedef TickType_t osa_timer_tick;
+
+#if CONFIG_HEAP_STAT
+/** This function dumps complete statistics
+ *  of the heap memory.
+ */
+void OSA_DumpMemStats(void);
+#endif
+
+/**
+ * \def os_get_runtime_stats(__buff__)
+ *
+ * Get ASCII formatted run time statistics
+ *
+ * Please ensure that your buffer is big enough for the formatted data to
+ * fit. Failing to do this may cause memory data corruption.
+ */
+#define OSA_GetRuntimeStats(__buff__) vTaskGetRunTimeStats(__buff__)
+
+/**
+ * \def os_get_task_list(__buff__)
+ *
+ * Get ASCII formatted task list
+ *
+ * Please ensure that your buffer is big enough for the formatted data to
+ * fit. Failing to do this may cause memory data corruption.
+ */
+
+#define OSA_GetTaskList(__buff__) vTaskList(__buff__)
+
+bool is_isr_context(void);
+/** Get current OS tick counter value
+ *
+ * \return 32 bit value of ticks since boot-up
+ */
+static inline unsigned OSA_TicksGet(void)
+{
+    if (is_isr_context())
+    {
+        return xTaskGetTickCountFromISR();
+    }
+    else
+    {
+        return xTaskGetTickCount();
+    }
+}
+
+static inline uint32_t OSA_MsecToTicks(uint32_t msecs)
+{
+    return (msecs) / (portTICK_PERIOD_MS);
+}
+
+static inline unsigned long OSA_TicksToMsec(unsigned long ticks)
+{
+    return (ticks) * (portTICK_PERIOD_MS);
+}
+
+/** Disable all tasks schedule */
+static inline void OSA_LockSchedule(void)
+{
+    vTaskSuspendAll();
+}
+
+/** Enable all tasks schedule */
+static inline void OSA_UnlockSchedule(void)
+{
+    xTaskResumeAll();
+}
+
+/**
+ * Returns time in micro-secs since bootup
+ *
+ * @note The value returned will wrap around after sometime and caller is
+ * expected to guard itself against this.
+ *
+ * @return Time in micro-secs since bootup
+ */
+unsigned int OSA_GetTimestamp(void);
+
+/** Structure used for queue definition */
+typedef struct osa_queue_pool
+{
+    /** Size of the queue */
+    int size;
+} osa_queue_pool_t;
+
+/** Define OS Queue pool
+ *
+ * This macro helps define the name and size of the queue to be created
+ * using the function os_queue_create().
+ */
+#define OSA_QueuePoolDefine(poolname, poolsize) osa_queue_pool_t poolname = {poolsize};
+
+#endif /* ! _OSA_FREERTOS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/slist.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/slist.c
new file mode 100644
index 0000000000..aeba68d1e9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/slist.c
@@ -0,0 +1,210 @@
+/****************************************************************************
+ *
+ *  Copyright (c) 2023, Michael Becker (michael.f.becker@gmail.com)
+ *
+ *  This file is part of the FreeRTOS Add-ons project.
+ *
+ *  Source Code:
+ *  https://github.com/michaelbecker/freertos-addons
+ *
+ *  Project Page:
+ *  http://michaelbecker.github.io/freertos-addons/
+ *
+ *  On-line Documentation:
+ *  http://michaelbecker.github.io/freertos-addons/docs/html/index.html
+ *
+ *  MIT License
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files
+ *  (the "Software"), to deal in the Software without restriction, including
+ *  without limitation the rights to use, copy, modify, merge, publish,
+ *  distribute, sublicense, and/or sell copies of the Software, and to
+ *  permit persons to whom the Software is furnished to do so,subject to the
+ *  following conditions:
+ *
+ *  + The above copyright notice and this permission notice shall be included
+ *    in all copies or substantial portions of the Software.
+ *  + Credit is appreciated, but not required, if you find this project
+ *    useful enough to include in your application, product, device, etc.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ *  OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ *  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ *  CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ *  TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ *  SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ***************************************************************************/
+/*
+ *  Copyright 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdlib.h>
+#include "slist.h"
+
+void SlAddNodeToTail(SlNode_t *Head, SlNode_t *Node)
+{
+    /********************/
+    SlNode_t *Current;
+    /********************/
+
+    if (Head == NULL)
+        return;
+
+    if (Node == NULL)
+        return;
+
+    Current = Head;
+
+    while (Current->Next != NULL)
+    {
+        Current = Current->Next;
+    }
+
+    Current->Next = Node;
+    Node->Next    = NULL;
+}
+
+void SlInsertNodeAfter(SlNode_t *Marker, SlNode_t *Node)
+{
+    /********************/
+    SlNode_t *Temp;
+    /********************/
+
+    if (Marker == NULL)
+        return;
+
+    if (Node == NULL)
+        return;
+
+    Temp         = Marker->Next;
+    Marker->Next = Node;
+    Node->Next   = Temp;
+}
+
+void SlInsertNodeBefore(SlNode_t *Head, SlNode_t *Marker, SlNode_t *Node)
+{
+    /********************/
+    SlNode_t *Current;
+    SlNode_t *Prior;
+    int Found = 0;
+    /********************/
+
+    if (Marker == NULL)
+        return;
+
+    if (Node == NULL)
+        return;
+
+    if (Head == NULL)
+        return;
+
+    Current = Head->Next;
+    Prior   = Head;
+
+    while (Current != NULL)
+    {
+        if (Current == Marker)
+        {
+            Found = 1;
+            break;
+        }
+
+        Prior   = Current;
+        Current = Current->Next;
+    }
+
+    if (Found)
+    {
+        Prior->Next = Node;
+        Node->Next  = Current;
+    }
+}
+
+void SlRemoveNode(SlNode_t *Head, SlNode_t *Node)
+{
+    /********************/
+    SlNode_t *Current;
+    SlNode_t *Prior;
+    int Found = 0;
+    /********************/
+
+    if (Head == NULL)
+        return;
+
+    if (Node == NULL)
+        return;
+
+    Current = Head->Next;
+    Prior   = Head;
+
+    while (Current != NULL)
+    {
+        if (Current == Node)
+        {
+            Found = 1;
+            break;
+        }
+
+        Prior   = Current;
+        Current = Current->Next;
+    }
+
+    if (Found)
+    {
+        Prior->Next = Current->Next;
+    }
+}
+
+SlNode_t *SlRemoveNodeFromHead(SlNode_t *Head)
+{
+    /********************/
+    SlNode_t *Node;
+    /********************/
+
+    if (Head == NULL)
+        return NULL;
+
+    Node = Head->Next;
+
+    if (Node != NULL)
+    {
+        Head->Next = Node->Next;
+    }
+
+    return Node;
+}
+
+SlNode_t *SlRemoveNodeFromTail(SlNode_t *Head)
+{
+    /********************/
+    SlNode_t *Current;
+    SlNode_t *Prior;
+    /********************/
+
+    if (Head == NULL)
+        return NULL;
+
+    Current = Head->Next;
+    Prior   = Head;
+
+    if (SlIsListEmpty(Head))
+    {
+        return NULL;
+    }
+
+    while (Current->Next != NULL)
+    {
+        Prior   = Current;
+        Current = Current->Next;
+    }
+
+    Prior->Next = NULL;
+
+    return Current;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/stack_simple.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/stack_simple.c
new file mode 100644
index 0000000000..d3484123f7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/port/osa/stack_simple.c
@@ -0,0 +1,87 @@
+/****************************************************************************
+ *
+ *  Copyright (c) 2023, Michael Becker (michael.f.becker@gmail.com)
+ *
+ *  This file is part of the FreeRTOS Add-ons project.
+ *
+ *  Source Code:
+ *  https://github.com/michaelbecker/freertos-addons
+ *
+ *  Project Page:
+ *  http://michaelbecker.github.io/freertos-addons/
+ *
+ *  On-line Documentation:
+ *  http://michaelbecker.github.io/freertos-addons/docs/html/index.html
+ *
+ *  MIT License
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files
+ *  (the "Software"), to deal in the Software without restriction, including
+ *  without limitation the rights to use, copy, modify, merge, publish,
+ *  distribute, sublicense, and/or sell copies of the Software, and to
+ *  permit persons to whom the Software is furnished to do so,subject to the
+ *  following conditions:
+ *
+ *  + The above copyright notice and this permission notice shall be included
+ *    in all copies or substantial portions of the Software.
+ *  + Credit is appreciated, but not required, if you find this project
+ *    useful enough to include in your application, product, device, etc.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ *  OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ *  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ *  CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ *  TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ *  SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ***************************************************************************/
+/*
+ *  Copyright 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdlib.h>
+#include "stack_simple.h"
+
+void InitStack(Stack_t *Stack)
+{
+    Stack->Count = 0;
+    SlInitHead(&Stack->Head);
+}
+
+void PushOnStack(Stack_t *Stack, SlNode_t *Node)
+{
+    if (!Stack)
+        return;
+
+    if (!Node)
+        return;
+
+    SlAddNodeToHead(&Stack->Head, Node);
+    Stack->Count++;
+}
+
+SlNode_t *PopOffStack(Stack_t *Stack)
+{
+    SlNode_t *Node;
+
+    if (!Stack)
+        return NULL;
+
+    if (Stack->Count == 0)
+    {
+        return NULL;
+    }
+    else
+    {
+        Stack->Count--;
+    }
+
+    Node = SlRemoveNodeFromHead(&Stack->Head);
+
+    return Node;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifi_bt_firmware/wlan_bt_fw.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifi_bt_firmware/wlan_bt_fw.h
new file mode 100644
index 0000000000..8566797437
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifi_bt_firmware/wlan_bt_fw.h
@@ -0,0 +1,43 @@
+/*
+ *  Copyright 2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __WLAN_BT_FW_H__
+#define __WLAN_BT_FW_H__
+
+#include <osa.h>
+
+#if defined(SD8801)
+#include "sd8801_wlan.h"
+#elif defined(SD8978)
+#if !(CONFIG_WIFI_IND_DNLD) && !defined(CONFIG_BT_IND_DNLD)
+#include "sduartIW416_wlan_bt.h"
+#else
+#include "sdIW416_wlan.h"
+#include "uartIW416_bt.h"
+#endif
+#elif defined(SD8987)
+#if !(CONFIG_WIFI_IND_DNLD) && !defined(CONFIG_BT_IND_DNLD)
+#include "sduart8987_wlan_bt.h"
+#else
+#include "sd8987_wlan.h"
+#include "uart8987_bt.h"
+#endif
+#elif defined(SD9177)
+#if !(CONFIG_WIFI_IND_DNLD) && !defined(CONFIG_BT_IND_DNLD)
+#include "sduart_nw61x_se.h"
+#else
+#include "sd_nw61x_se.h"
+#include "uart_nw61x_se.h"
+#endif
+#elif defined(RW610)
+extern const unsigned char *wlan_fw_bin;
+extern const unsigned int wlan_fw_bin_len;
+#else
+#error "Please define Wi-Fi Module"
+#endif
+
+#endif /* __WLAN_BT_FW_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan.h
new file mode 100644
index 0000000000..ba5180794f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan.h
@@ -0,0 +1,67 @@
+/** @file mlan.h
+ *
+ *  @brief This file declares all APIs that will be called from MOAL module.
+ *  It also defines the data structures used for APIs between MLAN and MOAL.
+ *
+ *  Copyright 2008-2021, 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/13/2008: initial version
+    11/07/2008: split mlan.h into mlan_decl.h & mlan_ioctl.h
+******************************************************/
+
+#ifndef _MLAN_H_
+#define _MLAN_H_
+
+#include <wifi_config_default.h>
+
+#ifdef __ZEPHYR__
+#include "nxp_wifi.h"
+#endif
+
+
+
+#ifndef __ZEPHYR__
+#if !CONFIG_STA_AUTO_DHCPV4
+#define CONFIG_STA_AUTO_DHCPV4 1
+#endif
+#endif
+
+#ifndef __ZEPHYR__
+#if !CONFIG_WIFI_STA_RECONNECT
+#define CONFIG_WIFI_STA_RECONNECT 1
+#endif
+#endif
+
+#define CONFIG_GTK_REKEY_OFFLOAD 0
+
+
+#if defined(SD9177)
+#define CONFIG_TCP_ACK_ENH 1
+#define CONFIG_FW_VDLL     1
+#if !CONFIG_WIFI_CAPA
+#define CONFIG_WIFI_CAPA 1
+#endif
+
+#if CONFIG_11AX
+#if !CONFIG_11K
+#define CONFIG_11K 1
+#endif
+#if !CONFIG_11V
+#define CONFIG_11V 1
+#endif
+#endif
+#endif
+
+#include <osa.h>
+
+#include "mlan_decl.h"
+#include "mlan_ioctl.h"
+#include "mlan_ieee.h"
+
+#endif /* !_MLAN_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11ac.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11ac.h
new file mode 100644
index 0000000000..0a2bbdfa49
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11ac.h
@@ -0,0 +1,49 @@
+/** @file mlan_11ac.h
+ *
+ *  @brief This file defines the private and adapter data
+ *  structures and declares global function prototypes used
+ *  in MLAN module.
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _MLAN_11AC_H_
+#define _MLAN_11AC_H_
+
+#include "mlan_11n_aggr.h"
+#include "mlan_11n_rxreorder.h"
+#include "mlan_wmm.h"
+#if 0
+void wlan_show_dot11acdevcap(pmlan_adapter pmadapter, t_u32 cap);
+void wlan_show_dot11acmcssupport(pmlan_adapter pmadapter, t_u32 support);
+#endif
+t_u16 wlan_convert_mcsmap_to_maxrate(mlan_private *priv, t_u8 bands, t_u16 mcs_map);
+void wlan_fill_vht_cap_tlv(mlan_private *priv, MrvlIETypes_VHTCap_t *pvht_cap, t_u16 bands, t_u8 flag);
+#if 0
+void wlan_fill_vht_cap_ie(mlan_private *priv, IEEEtypes_VHTCap_t *pvht_cap, t_u16 bands);
+#endif
+int wlan_cmd_append_11ac_tlv(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc, t_u8 **ppbuffer);
+#if 0
+mlan_status wlan_11ac_cfg_ioctl(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req);
+void wlan_update_11ac_cap(mlan_private *pmpriv);
+#endif
+#if CONFIG_11AC
+
+t_u8 wlan_get_center_freq_idx(mlan_private *pmpriv, t_u8 band, t_u32 pri_chan, t_u8 chan_bw);
+
+#endif /*CONFIG_11AC*/
+t_u8 wlan_11ac_bandconfig_allowed(mlan_private *pmpriv, t_u16 bss_band);
+
+mlan_status wlan_cmd_11ac_cfg(IN pmlan_private pmpriv,
+                              IN HostCmd_DS_COMMAND *cmd,
+                              IN t_u16 cmd_action,
+                              IN t_void *pdata_buf);
+#if 0
+mlan_status wlan_ret_11ac_cfg(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN mlan_ioctl_req *pioctl_buf);
+#endif
+mlan_status wlan_11ac_ioctl_vhtcfg(IN mlan_private *pmpriv, IN t_u8 action, IN mlan_ds_11ac_vht_cfg *vht_cfg);
+
+#endif /* _MLAN_11AC_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11ax.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11ax.h
new file mode 100644
index 0000000000..cd6cd3a7ea
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11ax.h
@@ -0,0 +1,54 @@
+#if CONFIG_11AX
+/** @file mlan_11ax.h
+ *
+ *  @brief This file defines the private and adapter data
+ *  structures and declares global function prototypes used
+ *  in MLAN module.
+ *
+ *  Copyright 2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _MLAN_11AX_H_
+#define _MLAN_11AX_H_
+
+/** device support 2.4G 40MHZ */
+#define AX_2G_40MHZ_SUPPORT MBIT(1)
+/** device support 2.4G 242 tone RUs */
+#define AX_2G_20MHZ_SUPPORT MBIT(5)
+
+#ifdef RW610
+/**
+ *  firmware 11ax tlv sequence number, for judging 2.4G or 5G tlv
+ *  firmware add 11ax tlv as 0-5G 1-2.4G to stack
+ *  so driver need to parse 11ax tlv as 0-2.4G 1-5G in converse
+ */
+#define AX_2G_TLV_INDEX 0
+#define AX_5G_TLV_INDEX 1
+#endif
+
+t_u8 wlan_check_ap_11ax_twt_supported(BSSDescriptor_t *pbss_desc);
+t_u8 wlan_check_11ax_twt_supported(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc);
+t_u16 wlan_fill_he_cap_tlv(mlan_private *pmpriv, t_u16 band, MrvlIEtypes_Extension_t *phe_cap, t_u8 flag);
+int wlan_cmd_append_11ax_tlv(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc, t_u8 **ppbuffer);
+void wlan_update_11ax_cap(mlan_adapter *pmadapter,
+                          MrvlIEtypes_Extension_t *hw_he_cap
+#ifdef RW610
+                          ,
+                          int tlv_idx
+#endif
+);
+t_u16 wlan_11ax_bandconfig_allowed(mlan_private *pmpriv, t_u16 bss_band);
+mlan_status wlan_11ax_cfg_ioctl(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req);
+mlan_status wlan_11ax_ioctl_cmd(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req);
+int wlan_cmd_11ax_cfg(mlan_private *pmpriv, t_u16 action, mlan_ds_11ax_he_cfg *he_cfg);
+mlan_status wlan_ret_11ax_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ds_11ax_he_cfg *hecfg);
+mlan_status wlan_cmd_11ax_cmd(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+mlan_status wlan_ret_11ax_cmd(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+#if CONFIG_11AX_TWT
+mlan_status wlan_cmd_twt_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+#endif /* CONFIG_11AX_TWT */
+#endif /* _MLAN_11AX_H_ */
+#endif /* CONFIG_11AX */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11h.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11h.h
new file mode 100644
index 0000000000..5142bf0952
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11h.h
@@ -0,0 +1,50 @@
+/** @file mlan_11h.h
+ *
+ *  @brief This header file contains data structures and
+ *  function declarations of 802.11h
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*************************************************************
+Change Log:
+    03/26/2009: initial creation
+*************************************************************/
+
+#ifndef _MLAN_11H_
+#define _MLAN_11H_
+
+/** 11H OID bitmasks */
+#define ENABLE_11H_MASK       MBIT(0)
+#define MASTER_RADAR_DET_MASK MBIT(1)
+#define SLAVE_RADAR_DET_MASK  MBIT(2)
+
+/** DFS Master Radar Detect global enable */
+#define DFS_MASTER_RADAR_DETECT_EN (MTRUE)
+/** DFS Slave Radar Detect global enable */
+#define DFS_SLAVE_RADAR_DETECT_EN (MFALSE)
+
+/**
+ *  11H APIs
+ */
+
+
+/** Initialize the 11h device structure */
+extern void wlan_11h_init(mlan_adapter *adapter);
+
+/** Initialize the 11h interface structure */
+extern void wlan_11h_priv_init(mlan_private *pmpriv);
+
+
+/** Check if radar detection is required on the specified channel */
+extern t_bool wlan_11h_radar_detect_required(mlan_private *priv, t_u8 channel);
+
+
+
+/** Get non-DFS channel */
+extern mlan_status wlan_get_non_dfs_chan(mlan_private *priv, t_u8 *chan);
+
+#endif /*_MLAN_11H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11k.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11k.h
new file mode 100644
index 0000000000..95a24bed54
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11k.h
@@ -0,0 +1,194 @@
+/** @file mlan_11k.h
+ *
+ *  @brief Interface for the BTM module implemented in mlan_11k.c
+ *
+ *  Driver interface functions and type declarations for the process RRM data
+ *    module implemented in mlan_11k.c.
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    08/24/2022: initial version
+********************************************************/
+
+#ifndef _MLAN_11K_H_
+#define _MLAN_11K_H_
+
+#if CONFIG_11K
+/* Link Measurement Request frame */
+typedef MLAN_PACK_START struct _mgmt_rrm_link_meas_request
+{
+    t_u8 dialog_tok;
+    /* Transmit power used to transmit the frame containing the Link Measurement Request */
+    t_s8 tx_power;
+    /* The upper limit on the transmit power */
+    t_s8 max_tx_power;
+    t_u8 variable[1];
+} MLAN_PACK_END mgmt_rrm_link_meas_request;
+
+/* Link Measurement Report frame */
+typedef MLAN_PACK_START struct _mgmt_rrm_link_meas_report
+{
+    t_u8 dialog_tok;
+    /* Transmit power and link margin information */
+    IEEEtypes_TPCReport_t tpc_report;
+    /* Receive Antenna ID */
+    t_u8 rx_ant_id;
+    /* Transmit Antenna ID */
+    t_u8 tx_ant_id;
+    /* Received channel power indicator in a dBm scale */
+    t_u8 rcpi;
+    /* Received signal to noise indicator in a dBm scale */
+    t_u8 rsni;
+    t_u8 variable[1];
+} MLAN_PACK_END mgmt_rrm_link_meas_report;
+
+/* Measurement Request element */
+typedef MLAN_PACK_START struct _mgmt_rrm_radio_meas_request
+{
+    /* Element ID */
+    t_u8 ele_id;
+    /* Length */
+    t_u8 length;
+    /* Measurement Token */
+    t_u8 token;
+    /* Measurement Request Mode */
+    t_u8 mode;
+    /* Measurement Type */
+    t_u8 type;
+    /* Measurement Request */
+    t_u8 variable[1];
+} MLAN_PACK_END mgmt_rrm_radio_meas_request;
+
+/* Beacon request */
+typedef MLAN_PACK_START struct _mgmt_rrm_meas_beacon_request
+{
+    /* Operating Class */
+    t_u8 oper_class;
+    /* Channel Number */
+    t_u8 channel;
+    /* Randomization Interval (in TUs) */
+    t_u16 rand_intv;
+    /* Measurement Duration (in TUs) */
+    t_u16 duration;
+    /* Measurement Mode */
+    t_u8 mode;
+    /* BSSID */
+    t_u8 bssid[IEEEtypes_ADDRESS_SIZE];
+    /* Optional Subelements */
+    t_u8 variable[1];
+} MLAN_PACK_END mgmt_rrm_meas_beacon_request;
+
+/* Beacon report */
+typedef MLAN_PACK_START struct _mgmt_rrm_meas_beacon_report
+{
+    /* Operating Class */
+    t_u8 op_class;
+    /* Channel Number */
+    t_u8 channel;
+    /* Actual Measurement Start Time (in TSF of the BSS requesting the measurement) */
+    t_u64 m_start_time;
+    /* in TUs */
+    t_u16 duration;
+    /* Reported Frame Information */
+    t_u8 report_info;
+    /* Received channel power indicator in a dBm scale */
+    t_u8 rcpi;
+    /* Received signal to noise indicator in a dBm scale */
+    t_u8 rsni;
+    /* BSSID */
+    t_u8 bssid[IEEEtypes_ADDRESS_SIZE];
+    /* Antenna ID */
+    t_u8 ant_id;
+    /* Parent TSF */
+    t_u32 parent_tsf;
+    /* Optional Subelements */
+    t_u8 variable[1];
+} MLAN_PACK_END mgmt_rrm_meas_beacon_report;
+
+/* Measurement requests type */
+#define WLAN_RRM_MEASURE_TYPE_BEACON 5
+
+#ifndef BIT
+#define BIT(x) (1 << (x))
+#endif
+
+/* dot11PHYType */
+enum wlan_phy_type
+{
+    WLAN_PHY_TYPE_UNSPECIFIED = 0,
+    WLAN_PHY_TYPE_FHSS        = 1,
+    WLAN_PHY_TYPE_DSSS        = 2,
+    WLAN_PHY_TYPE_IRBASEBAND  = 3,
+    WLAN_PHY_TYPE_OFDM        = 4,
+    WLAN_PHY_TYPE_HRDSSS      = 5,
+    WLAN_PHY_TYPE_ERP         = 6,
+    WLAN_PHY_TYPE_HT          = 7,
+    WLAN_PHY_TYPE_DMG         = 8,
+    WLAN_PHY_TYPE_VHT         = 9,
+};
+
+/* Measurement Mode of Beacon request */
+enum wlan_rrm_beacon_report_mode
+{
+    WLAN_RRM_MEASUREMENT_MODE_PASSIVE = 0,
+    WLAN_RRM_MEASUREMENT_MODE_ACTIVE  = 1,
+    WLAN_RRM_MEASUREMENT_MODE_TABLE   = 2,
+};
+
+/* Beacon Request subelement IDs */
+#define WLAN_RRM_BEACON_REQUEST_SUBELEMENT_SSID             0
+#define WLAN_RRM_BEACON_REQUEST_SUBELEMENT_REPORTING_INFO   1
+#define WLAN_RRM_BEACON_REQUEST_SUBELEMENT_REPORTING_DETAIL 2
+#define WLAN_RRM_BEACON_REQUEST_SUBELEMENT_REQUEST          10
+#define WLAN_RRM_BEACON_REQUEST_SUBELEMENT_AP_CHANNEL       51
+#define WLAN_RRM_BEACON_REQUEST_SUBELEMENT_LAST_INDICATION  164
+#define WLAN_RRM_BEACON_REQUEST_SUBELEMENT_VENDOR           221
+
+/* Measurement Report Mode field */
+#define WLAN_RRM_REPORT_MODE_ACCEPT           0
+#define WLAN_RRM_REPORT_MODE_REJECT_LATE      BIT(0)
+#define WLAN_RRM_REPORT_MODE_REJECT_INCAPABLE BIT(1)
+#define WLAN_RRM_REPORT_MODE_REJECT_REFUSED   BIT(2)
+
+/* Beacon report Subelement IDs */
+#define WLAN_RRM_BEACON_REP_SUBELEM_FRAME_BODY             1
+#define WLAN_RRM_BEACON_REP_SUBELEM_FRAME_BODY_FRAGMENT_ID 2
+#define WLAN_RRM_BEACON_REP_SUBELEM_LAST_INDICATION        164
+
+#define WLAN_RRM_BEACON_REP_FRAME_BODY_FRAGMENT_SUB_LEN 4
+#define WLAN_RRM_BEACON_REP_LAST_INDICATION_SUB_LEN     3
+
+/* Measurement Request Mode field */
+#define WLAN_RRM_MEAS_REQUEST_MODE_PARALLEL           BIT(0)
+#define WLAN_RRM_MEAS_REQUEST_MODE_ENABLE             BIT(1)
+#define WLAN_RRM_MEAS_REQUEST_MODE_REQUEST            BIT(2)
+#define WLAN_RRM_MEAS_REQUEST_MODE_REPORT             BIT(3)
+#define WLAN_RRM_MEAS_REQUEST_MODE_DURATION_MANDATORY BIT(4)
+
+void wlan_process_radio_measurement_request(t_u8 *frame, t_u32 len, t_u8 *dest_addr, t_u8 *src_addr, bool protect);
+void wlan_process_neighbor_report_response(t_u8 *frame, t_u32 len, t_u8 *dest_addr, t_u8 *src_addr, bool protect);
+void wlan_process_link_measurement_request(
+    t_u8 *frame, t_u32 len, t_u8 *dest_addr, t_u8 *src_addr, bool protect, RxPD *rxpd);
+void wlan_send_mgmt_rm_beacon_report(
+    t_u8 dialog_tok, t_u8 *src_addr, t_u8 *dst_addr, t_u8 *rep, t_u32 rep_len, bool protect);
+void wlan_add_rm_beacon_report(wlan_rrm_beacon_report_data *rep_data,
+                               BSSDescriptor_t *bss_entry,
+                               t_u8 **buf_pos,
+                               t_s32 remained_len,
+                               t_u32 *pos_last_indication);
+bool wlan_rrm_matched_ap_found(wlan_rrm_beacon_report_data *rep_data, BSSDescriptor_t *bss_entry);
+
+/** Add RRM Capabilities */
+void wlan_dot11k_formatRrmCapabilities(IEEEtypes_RrmEnabledCapabilities_t *pRrmCapIe, t_u16 bcnInterval);
+
+/* send mgmt neighbor report request frame */
+int wlan_send_mgmt_rm_neighbor_request(mlan_private *pmpriv, t_u8 *ssid, t_u8 ssid_len);
+#endif /* CONFIG_11K */
+
+#endif /* !_MLAN_11K_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n.h
new file mode 100644
index 0000000000..f4abbfc769
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n.h
@@ -0,0 +1,356 @@
+/** @file mlan_11n.h
+ *
+ *  @brief Interface for the 802.11n mlan_11n module implemented in mlan_11n.c
+ *
+ *  Driver interface functions and type declarations for the 11n module
+ *    implemented in mlan_11n.c.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    12/01/2008: initial version
+********************************************************/
+
+#ifndef _MLAN_11N_H_
+#define _MLAN_11N_H_
+
+#include "mlan_11n_aggr.h"
+#include "mlan_11n_rxreorder.h"
+#include "mlan_wmm.h"
+
+/** Print the 802.11n device capability */
+void wlan_show_dot11ndevcap(pmlan_adapter pmadapter, t_u32 cap);
+/** Print the 802.11n device MCS */
+void wlan_show_devmcssupport(pmlan_adapter pmadapter, t_u8 support);
+/** Handle the command response of a delete block ack request */
+mlan_status wlan_ret_11n_delba(mlan_private *priv, HostCmd_DS_COMMAND *resp);
+/** Handle the command response of an add block ack request */
+mlan_status wlan_ret_11n_addba_req(mlan_private *priv, HostCmd_DS_COMMAND *resp);
+/** Handle the command response of 11ncfg command */
+mlan_status wlan_ret_11n_cfg(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN mlan_ioctl_req *pioctl_buf);
+/** Prepare 11ncfg command */
+mlan_status wlan_cmd_11n_cfg(IN pmlan_private pmpriv,
+                             IN HostCmd_DS_COMMAND *cmd,
+                             IN t_u16 cmd_action,
+                             IN t_void *pdata_buf);
+/** Prepare TX BF configuration command */
+mlan_status wlan_cmd_tx_bf_cfg(IN pmlan_private pmpriv,
+                               IN HostCmd_DS_COMMAND *cmd,
+                               IN t_u16 cmd_action,
+                               IN t_void *pdata_buf);
+/** Handle the command response TX BF configuration */
+mlan_status wlan_ret_tx_bf_cfg(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN mlan_ioctl_req *pioctl_buf);
+/** Append the 802_11N tlv */
+t_u32 wlan_cmd_append_11n_tlv(IN mlan_private *pmpriv, IN BSSDescriptor_t *pbss_desc, OUT t_u8 **ppbuffer);
+/** wlan fill HT cap tlv */
+void wlan_fill_ht_cap_tlv(mlan_private *priv, MrvlIETypes_HTCap_t *pht_cap, t_u16 bands);
+/** Miscellaneous configuration handler */
+mlan_status wlan_11n_cfg_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+/** Delete Tx BA stream table entry */
+void wlan_11n_delete_txbastream_tbl_entry(mlan_private *priv, t_u8 *ra);
+/** Delete all Tx BA stream table entries */
+void wlan_11n_deleteall_txbastream_tbl(mlan_private *priv);
+/** Get Tx BA stream table */
+TxBAStreamTbl *wlan_11n_get_txbastream_tbl(mlan_private *priv, t_u8 *ra);
+/** update Tx ampud_stat */
+void wlan_11n_update_txbastream_tbl_ampdu_stat(mlan_private *priv, t_u8 *ra, t_u8 status, t_u8 tid);
+/** update Tx ampdu_supported */
+void wlan_11n_update_txbastream_tbl_ampdu_supported(mlan_private *priv, t_u8 *ra, t_u8 supported);
+/** update Tx threshold */
+void wlan_11n_update_txbastream_tbl_tx_thresh(mlan_private *priv, t_u8 *ra, t_u8 tx_thresh);
+/** update Tx ampdu_tx cnt */
+void wlan_11n_update_txbastream_tbl_tx_cnt(mlan_private *priv, t_u8 *ra);
+/** get sta peer amsdu */
+int wlan_11n_get_sta_peer_amsdu(mlan_private *priv);
+/** Create Tx BA stream table */
+void wlan_11n_create_txbastream_tbl(mlan_private *priv, t_u8 *ra, baStatus_e ba_status);
+/** Send ADD BA request */
+int wlan_send_addba(mlan_private *priv, int tid, const t_u8 *peer_mac);
+/** Send DEL BA request */
+mlan_status wlan_send_delba(mlan_private *priv, pmlan_ioctl_req pioctl_req, int tid, t_u8 *peer_mac, int initiator);
+/** This function handles the command response of delete a block ack request*/
+void wlan_11n_delete_bastream(mlan_private *priv, t_u8 *del_ba);
+/** get rx reorder table */
+int wlan_get_rxreorder_tbl(mlan_private *priv, rx_reorder_tbl *buf);
+/** get tx ba stream table */
+int wlan_get_txbastream_tbl(mlan_private *priv, tx_ba_stream_tbl *buf);
+#if CONFIG_AMSDU_IN_AMPDU
+/** Minimum number of AMSDU */
+#define MIN_NUM_AMSDU 2
+/** AMSDU Aggr control cmd resp */
+mlan_status wlan_ret_amsdu_aggr_ctrl(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+#endif
+/** reconfigure tx buf size */
+mlan_status wlan_cmd_recfg_tx_buf(mlan_private *priv, HostCmd_DS_COMMAND *cmd, int cmd_action, void *pdata_buf);
+/** AMSDU aggr control cmd */
+mlan_status wlan_cmd_amsdu_aggr_ctrl(mlan_private *priv, HostCmd_DS_COMMAND *cmd, int cmd_action, void *pdata_buf);
+
+/** clean up txbastream_tbl */
+void wlan_11n_cleanup_txbastream_tbl(mlan_private *priv, t_u8 *ra);
+/**
+ *  @brief This function checks whether a station has 11N enabled or not
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param mac      station mac address
+ *  @return 	    MTRUE or MFALSE
+ */
+INLINE
+static t_u8 is_station_11n_enabled(mlan_private *priv, t_u8 *mac)
+{
+    sta_node *sta_ptr = MNULL;
+    sta_ptr           = wlan_get_station_entry(priv, mac);
+    if (sta_ptr != MNULL)
+    {
+        return (sta_ptr->is_11n_enabled) ? MTRUE : MFALSE;
+    }
+    return MFALSE;
+}
+
+/**
+ *  @brief This function get station max amsdu size
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param mac      station mac address
+ *  @return 	    max amsdu size statio supported
+ */
+INLINE
+static t_u16 get_station_max_amsdu_size(mlan_private *priv, t_u8 *mac)
+{
+    sta_node *sta_ptr = MNULL;
+    sta_ptr           = wlan_get_station_entry(priv, mac);
+    if (sta_ptr != MNULL)
+    {
+        return sta_ptr->max_amsdu;
+    }
+    return 0;
+}
+
+/**
+ *  @brief This function checks whether a station allows AMPDU or not
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ptr      A pointer to RA list table
+ *  @param tid      TID value for ptr
+ *  @return 	    MTRUE or MFALSE
+ */
+#if 0
+INLINE
+static t_u8
+is_station_ampdu_allowed(mlan_private * priv, raListTbl * ptr, int tid)
+{
+    sta_node *sta_ptr = MNULL;
+    if ((sta_ptr = wlan_get_station_entry(priv, ptr->ra))) {
+        if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP) {
+            if (priv->sec_info.wapi_enabled && !sta_ptr->wapi_key_on)
+                return MFALSE;
+        }
+        return ((sta_ptr->ampdu_sta[tid] != BA_STREAM_NOT_ALLOWED)
+                ? MTRUE : MFALSE);
+    }
+    return MFALSE;
+}
+#endif /* 0 */
+
+/**
+ *  @brief This function disable station ampdu for specific tid
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param tid     tid index
+ *  @param ra      station mac address
+ *  @return 	   N/A
+ */
+INLINE
+static void disable_station_ampdu(mlan_private *priv, t_u8 tid, t_u8 *ra)
+{
+    sta_node *sta_ptr = MNULL;
+    sta_ptr           = wlan_get_station_entry(priv, ra);
+    if (sta_ptr != MNULL)
+    {
+        sta_ptr->ampdu_sta[tid] = BA_STREAM_NOT_ALLOWED;
+    }
+    return;
+}
+
+
+/**
+ *  @brief This function checks whether AMPDU is allowed or not
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ptr      A pointer to RA list table
+ *  @param tid      TID value for ptr
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+#if 0
+INLINE
+static t_u8
+wlan_is_ampdu_allowed(mlan_private * priv, raListTbl * ptr, int tid)
+{
+    if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP)
+        return is_station_ampdu_allowed(priv, ptr, tid);
+    if (priv->sec_info.wapi_enabled && !priv->sec_info.wapi_key_on)
+        return MFALSE;
+
+    return ((priv->aggr_prio_tbl[tid].ampdu_ap != BA_STREAM_NOT_ALLOWED)
+            ? MTRUE : MFALSE);
+}
+#endif /* 0 */
+
+/**
+ *  @brief This function checks whether AMSDU is allowed for BA stream
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ptr      A pointer to RA list table
+ *  @param tid	    TID value for ptr
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+INLINE
+static int wlan_is_amsdu_in_ampdu_allowed(mlan_private *priv, raListTbl *ptr, int tid)
+{
+    TxBAStreamTbl *ptx_tbl;
+    ENTER();
+    ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ptr->ra);
+    if (ptx_tbl != MNULL)
+    {
+        LEAVE();
+        return (int)(ptx_tbl->amsdu);
+    }
+    LEAVE();
+    return MFALSE;
+}
+
+/**
+ *  @brief This function checks whether AMSDU is allowed or not
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ptr      A pointer to RA list table
+ *  @param tid      TID value for ptr
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+#if 0
+INLINE
+static t_u8
+wlan_is_amsdu_allowed(mlan_private * priv, raListTbl * ptr, int tid)
+{
+    sta_node *sta_ptr = MNULL;
+    if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP) {
+        if ((sta_ptr = wlan_get_station_entry(priv, ptr->ra))) {
+            if (priv->sec_info.wapi_enabled && !sta_ptr->wapi_key_on)
+                return MFALSE;
+        }
+    }
+#define TXRATE_BITMAP_INDEX_MCS0_7 2
+    return (((priv->aggr_prio_tbl[tid].amsdu != BA_STREAM_NOT_ALLOWED)
+             && ((priv->is_data_rate_auto)
+                 || !((priv->bitmap_rates[TXRATE_BITMAP_INDEX_MCS0_7]) & 0x03)))
+            ? MTRUE : MFALSE);
+}
+#endif /* 0 */
+
+/**
+ *  @brief This function checks whether a BA stream is available or not
+ *
+ *  @param priv     A pointer to mlan_private
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+INLINE
+static t_u8 wlan_is_bastream_avail(mlan_private *priv)
+{
+    mlan_private *pmpriv = MNULL;
+    t_u8 i               = 0;
+    t_u32 bastream_num   = 0;
+    for (i = 0; i < priv->adapter->priv_num; i++)
+    {
+        pmpriv = priv->adapter->priv[i];
+        if (pmpriv != MNULL)
+        {
+            bastream_num += wlan_wmm_list_len(priv->adapter, (pmlan_list_head)&pmpriv->tx_ba_stream_tbl_ptr);
+        }
+    }
+    return ((bastream_num < MLAN_MAX_TX_BASTREAM_SUPPORTED) ? MTRUE : MFALSE);
+}
+
+
+/**
+ *  @brief This function checks whether BA stream is setup
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ptr      A pointer to RA list table
+ *  @param tid	    TID value for ptr
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+INLINE
+static int wlan_is_bastream_setup(mlan_private *priv, raListTbl *ptr, int tid)
+{
+    TxBAStreamTbl *ptx_tbl;
+
+    ENTER();
+    ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ptr->ra);
+    if (ptx_tbl != MNULL)
+    {
+        LEAVE();
+        return IS_BASTREAM_SETUP(ptx_tbl) ? MTRUE : MFALSE;
+    }
+
+    LEAVE();
+    return MFALSE;
+}
+
+/**
+ *  @brief This function checks whether 11n is supported
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ra       Address of the receiver STA
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+INLINE
+static int wlan_is_11n_enabled(mlan_private *priv, t_u8 *ra)
+{
+    int ret = MFALSE;
+    ENTER();
+    if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP)
+    {
+        if ((!(ra[0] & 0x01U)) && (priv->is_11n_enabled))
+        {
+            ret = (int)is_station_11n_enabled(priv, ra);
+        }
+    }
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function checks whether amsdu is allowed
+ *
+ *  @param interface     interface to indicate uap or STA
+ *  @param pkt_cnt       current packets conuter in the queue
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+#if CONFIG_AMSDU_IN_AMPDU
+INLINE
+static bool wlan_is_amsdu_allowed(mlan_private *priv, t_u8 interface, t_u8 pkt_cnt, t_u8 tid)
+{
+    // First stage, only consider tx amsdu on STA side
+    if (interface == MLAN_BSS_TYPE_STA && pkt_cnt >= MIN_NUM_AMSDU && priv->is_amsdu_enabled && priv->max_amsdu &&
+        wlan_11n_get_sta_peer_amsdu(priv))
+    {
+        return MTRUE;
+    }
+    else
+    {
+        return MFALSE;
+    }
+}
+#endif
+#endif /* !_MLAN_11N_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n_aggr.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n_aggr.h
new file mode 100644
index 0000000000..de001bbb83
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n_aggr.h
@@ -0,0 +1,28 @@
+/** @file mlan_11n_aggr.h
+ *
+ *  @brief This file contains related macros, enum, and struct
+ *  of 11n aggregation functionalities
+ *
+ *  Copyright 2008-2021, 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    11/10/2008: initial version
+********************************************************/
+
+#ifndef _MLAN_11N_AGGR_H_
+#define _MLAN_11N_AGGR_H_
+
+/** Aggregate 11N packets */
+mlan_status wlan_11n_deaggregate_pkt(mlan_private *priv, pmlan_buffer pmbuf);
+/** Deaggregate 11N packets */
+int wlan_11n_aggregate_pkt(mlan_private *priv, raListTbl *ptr, int headroom, int ptrindex);
+#if CONFIG_AMSDU_IN_AMPDU
+/** Form A-MSDU packets */
+int wlan_11n_form_amsdu_pkt(t_u8 *amsdu_buf, t_u8 *data, int pkt_len, int *pad);
+#endif
+#endif /* !_MLAN_11N_AGGR_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n_rxreorder.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n_rxreorder.h
new file mode 100644
index 0000000000..f8d1a2174e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11n_rxreorder.h
@@ -0,0 +1,86 @@
+/** @file mlan_11n_rxreorder.h
+ *
+ *  @brief This file contains related macros, enum, and struct
+ *  of 11n RxReordering functionalities
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    11/10/2008: initial version
+********************************************************/
+
+#ifndef _MLAN_11N_RXREORDER_H_
+#define _MLAN_11N_RXREORDER_H_
+
+/** Max value a TID can take = 2^12 = 4096 */
+#define MAX_TID_VALUE 4096U
+/** 2^11 = 2048 */
+#define TWOPOW11 2048U
+
+/** Tid Mask used for extracting TID from BlockAckParamSet */
+#define BLOCKACKPARAM_TID_MASK 0x3CU
+/** Tid position in BlockAckParamSet */
+#define BLOCKACKPARAM_TID_POS 2U
+/** WinSize Mask used for extracting WinSize from BlockAckParamSet */
+#define BLOCKACKPARAM_WINSIZE_MASK 0xffc0U
+/** WinSize Mask used for extracting WinSize from BlockAckParamSet */
+#define BLOCKACKPARAM_AMSDU_SUPP_MASK 0x1U
+/** WinSize position in BlockAckParamSet */
+#define BLOCKACKPARAM_WINSIZE_POS 6U
+/** Position of TID in DelBA Param set */
+#define DELBA_TID_POS 12
+/** Position of INITIATOR in DelBA Param set */
+#define DELBA_INITIATOR_POS 11
+/** Reason code: Requested from peer STA as it does not want to use the mechanism */
+#define REASON_CODE_STA_DONT_WANT 37
+/** Reason code: Requested from peer STA due to timeout*/
+#define REASON_CODE_STA_TIMEOUT 39
+/** Type: send delba command */
+#define TYPE_DELBA_SENT 1
+/** Type: recieve delba command */
+#define TYPE_DELBA_RECEIVE 2U
+/** Set Initiator Bit */
+#define DELBA_INITIATOR(paramset) ((paramset) = ((paramset) | (1U << 11)))
+/** Reset Initiator Bit for recipient */
+#define DELBA_RECIPIENT(paramset) ((paramset) = ((paramset) & ~(1U << 11)))
+/** Immediate block ack */
+#define IMMEDIATE_BLOCK_ACK 0x2U
+
+/** The request has been declined */
+#define ADDBA_RSP_STATUS_DECLINED 37U
+/** ADDBA response status : Reject */
+#define ADDBA_RSP_STATUS_REJECT 1U
+/** ADDBA response status : Accept */
+#define ADDBA_RSP_STATUS_ACCEPT 0U
+
+/** DEFAULT SEQ NUM */
+#define DEFAULT_SEQ_NUM 0xffffU
+
+/** Indicate packet has been dropped in FW */
+#define RX_PKT_DROPPED_IN_FW 0xffffffffU
+
+
+mlan_status mlan_11n_rxreorder_pkt(void *priv, t_u16 seq_num, t_u16 tid, t_u8 *ta, t_u8 pkt_type, void *payload);
+void mlan_11n_update_bastream_tbl(mlan_private *priv, int Tid, t_u8 *PeerMACAddr, t_u8 type, int initiator);
+void wlan_11n_ba_stream_timeout(mlan_private *priv, HostCmd_DS_11N_BATIMEOUT *event);
+mlan_status wlan_ret_11n_addba_resp(mlan_private *priv, HostCmd_DS_COMMAND *resp);
+mlan_status wlan_cmd_11n_delba(mlan_private *priv, HostCmd_DS_COMMAND *cmd, void *pdata_buf);
+mlan_status wlan_cmd_11n_addba_rspgen(mlan_private *priv, HostCmd_DS_COMMAND *cmd, void *pdata_buf);
+mlan_status wlan_cmd_11n_uap_addba_rspgen(mlan_private *priv, HostCmd_DS_COMMAND *cmd, void *pdata_buf);
+mlan_status wlan_cmd_11n_addba_req(mlan_private *priv, HostCmd_DS_COMMAND *cmd, t_void *pdata_buf);
+void wlan_11n_cleanup_reorder_tbl(mlan_private *priv);
+RxReorderTbl *wlan_11n_get_rxreorder_tbl(mlan_private *priv, int tid, t_u8 *ta);
+void wlan_11n_rxba_sync_event(mlan_private *priv, t_u8 *event_buf, t_u16 len);
+
+/** send delba for all entries in reorder_tbl */
+t_void wlan_send_delba_to_all_in_reorder_tbl(pmlan_private priv);
+void wlan_update_rxreorder_tbl(pmlan_adapter pmadapter, bool flag);
+
+/** clean up reorder_tbl */
+void wlan_cleanup_reorder_tbl(mlan_private *priv, t_u8 *ta);
+#endif /* _MLAN_11N_RXREORDER_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11v.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11v.h
new file mode 100644
index 0000000000..f29b110dae
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_11v.h
@@ -0,0 +1,69 @@
+/** @file mlan_11v.h
+ *
+ *  @brief Interface for the BTM module implemented in mlan_11v.c
+ *
+ *  Driver interface functions and type declarations for the process BTM frame
+ *    module implemented in mlan_11v.c.
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    08/11/2022: initial version
+********************************************************/
+
+#ifndef _MLAN_11V_H_
+#define _MLAN_11V_H_
+
+#if CONFIG_11V
+
+#define WLAN_WNM_MAX_NEIGHBOR_REPORT               6
+#define MGMT_WNM_NEIGHBOR_BSS_TRANSITION_CANDIDATE 3
+
+struct wnm_neighbor_report
+{
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    t_u32 bssid_info;
+    t_u8 reg_class;
+    t_u8 channel;
+    t_u8 PhyType;
+    t_u8 prefer;
+    t_u8 prefer_select;
+};
+
+/* IEEE Std 802.11-2016 - Table 9-357 BTM status code definitions */
+enum wnm_btm_status_code
+{
+    WNM_BTM_ACCEPT                                 = 0,
+    WNM_BTM_REJECT_UNSPECIFIED                     = 1,
+    WNM_BTM_REJECT_INSUFFICIENT_BEACON_PROBE_RESP  = 2,
+    WNM_BTM_REJECT_INSUFFICIENT_AVAILABLE_CAPABITY = 3,
+    WNM_BTM_REJECT_TERMINATION_UNDESIRED           = 4,
+    WNM_BTM_REJECT_TERMINATION_DELAY_REQUEST       = 5,
+    WNM_BTM_REJECT_STA_CANDIDATE_LIST_PROVIDED     = 6,
+    WNM_BTM_REJECT_NO_SUITABLE_CANDIDATES          = 7,
+    WNM_BTM_REJECT_LEAVING_ESS                     = 8
+};
+
+/** process rx action frame */
+void wlan_process_mgmt_wnm_btm_req(t_u8 *pos, t_u8 *end, t_u8 *src_addr, t_u8 *dest_addr, bool protect);
+
+/* send mgmt bss transition query frame */
+int wlan_send_mgmt_bss_trans_query(mlan_private *pmpriv, t_u8 query_reason);
+
+/* send mgmt bss transition mgmt response */
+void wlan_send_mgmt_wnm_btm_resp(t_u8 dialog_token,
+                                 enum wnm_btm_status_code status,
+                                 t_u8 *dst_addr,
+                                 t_u8 *src_addr,
+                                 t_u8 *target_bssid,
+                                 t_u8 *tag_nr,
+                                 t_u8 tag_len,
+                                 bool protect);
+#endif /* CONFIG_11V */
+
+#endif /* !_MLAN_11V_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_action.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_action.h
new file mode 100644
index 0000000000..ee6ca2bdef
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_action.h
@@ -0,0 +1,27 @@
+/** @file mlan_action.h
+ *
+ *  @brief Interface for the mlan_action module implemented in mlan_action.c
+ *
+ *  Driver interface functions and type declarations for the process action frame
+ *    module implemented in mlan_action.c.
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    08/11/2022: initial version
+********************************************************/
+
+#ifndef _MLAN_ACTION_H_
+#define _MLAN_ACTION_H_
+
+#include "mlan_fw.h"
+
+/** process rx action frame */
+mlan_status wlan_process_mgmt_action(t_u8 *payload, t_u32 payload_len, RxPD *rxpd);
+
+#endif /* !_MLAN_ACTION_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_api.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_api.h
new file mode 100644
index 0000000000..d270233e9f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_api.h
@@ -0,0 +1,619 @@
+/** @file mlan_api.h
+ *
+ *  @brief MLAN Interface
+ *
+ *  Copyright 2008-2022, 2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __MLAN_API_H__
+#define __MLAN_API_H__
+#include <string.h>
+#include <wmtypes.h>
+#include <wlan.h>
+
+#ifndef __ZEPHYR__
+#include "fsl_debug_console.h"
+#endif
+
+#define MLAN_WMSDK_MAX_WPA_IE_LEN 64U
+#define MLAN_MAX_MDIE_LEN         10U
+#define MLAN_MAX_VENDOR_IE_LEN    100U
+
+#include "mlan.h"
+#include "mlan_join.h"
+#include "mlan_util.h"
+#include "mlan_fw.h"
+#include "mlan_main.h"
+#ifndef RW610
+#include "mlan_main_defs.h"
+#endif
+#include "mlan_wmm.h"
+#include "mlan_11n.h"
+#include "mlan_11h.h"
+#include "mlan_11ac.h"
+#if CONFIG_11AX
+#include "mlan_11ax.h"
+#endif
+#include "mlan_11n_aggr.h"
+#ifndef RW610
+#include "mlan_sdio.h"
+#endif
+#include "mlan_11n_rxreorder.h"
+#include "mlan_meas.h"
+#include "mlan_uap.h"
+#include <wifi-debug.h>
+#ifndef RW610
+#include <wifi-sdio.h>
+#endif
+#include "wifi-internal.h"
+#include "mlan_action.h"
+#if CONFIG_11V
+#include "mlan_11v.h"
+#endif
+#if CONFIG_11K
+#include "mlan_11k.h"
+#endif
+/* #define CONFIG_WIFI_DEBUG */
+
+static inline void panic(const char *msg)
+{
+    PRINTF("%s\r\n", msg);
+    assert(0);
+}
+
+/** Wait until a condition becomes true */
+#define ASSERT(cond)                                          \
+    do                                                        \
+    {                                                         \
+        if (!(cond))                                          \
+        {                                                     \
+            PRINTF("ASSERT: %s: %d\r\n", __func__, __LINE__); \
+            panic("Assert failed: Panic!");                   \
+        }                                                     \
+    } while (0)
+
+#if CONFIG_WIFI_DEBUG
+/* #define DEBUG_11N_ASSOC */
+/* #define DEBUG_11N_AGGR */
+/* #define DEBUG_11N_REORDERING */
+#define DEBUG_MLAN
+/* #define DEBUG_DEVELOPMENT */
+/* #define DUMP_PACKET_MAC */
+#endif /* CONFIG_WIFI_DEBUG */
+
+#ifdef EXIT
+#undef EXIT
+#define EXIT(...)
+#endif /* EXIT */
+
+#ifdef DEBUG_MLAN
+
+#ifdef PRINTM
+#undef PRINTM
+#define PRINTM(level, ...)                   \
+    do                                       \
+    {                                        \
+        (void)PRINTF("[mlan] " __VA_ARGS__); \
+        (void)PRINTF("\n\r");                \
+    } while (0)
+#else
+#define PRINTM(...)
+#endif /* PRINTM */
+
+#ifdef DBG_HEXDUMP
+#undef DBG_HEXDUMP
+#define DBG_HEXDUMP(level, x, y, z)       \
+    do                                    \
+    {                                     \
+        (void)PRINTF("[mlan] %s\r\n", x); \
+        dump_hex(y, z);                   \
+        (void)PRINTF("\r\n");             \
+    } while (0)
+#else
+#define DBG_HEXDUMP(...)
+#endif /* DBG_HEXDUMP */
+
+#ifdef HEXDUMP
+#undef HEXDUMP
+#define HEXDUMP(x, y, z)                  \
+    do                                    \
+    {                                     \
+        (void)PRINTF("[mlan] %s\r\n", x); \
+        dump_hex(y, z);                   \
+        (void)PRINTF("\r\n");             \
+    } while (0)
+#else
+#define HEXDUMP(...)
+#endif /* HEXDUMP */
+#endif /* DEBUG_MLAN */
+
+#define DOT11N_CFG_ENABLE_RIFS            0x08
+#define DOT11N_CFG_ENABLE_GREENFIELD_XMIT (1U << 4)
+#define DOT11N_CFG_ENABLE_SHORT_GI_20MHZ  (1U << 5)
+#define DOT11N_CFG_ENABLE_SHORT_GI_40MHZ  (1U << 6)
+
+#define CLOSEST_DTIM_TO_LISTEN_INTERVAL 65534
+
+#define SDIO_DMA_ALIGNMENT 4
+
+#define MAX_WAIT_WAKEUP_TIME 3000
+
+/*
+ * Bit 0 : Assoc Req
+ * Bit 1 : Assoc Resp
+ * Bit 2 : ReAssoc Req
+ * Bit 3 : ReAssoc Resp
+ * Bit 4 : Probe Req
+ * Bit 5 : Probe Resp
+ * Bit 8 : Beacon
+ */
+/** Mask for Assoc request frame */
+#define MGMT_MASK_ASSOC_REQ 0x01
+/** Mask for ReAssoc request frame */
+#define MGMT_MASK_REASSOC_REQ 0x04
+/** Mask for Assoc response frame */
+#define MGMT_MASK_ASSOC_RESP 0x02
+/** Mask for ReAssoc response frame */
+#define MGMT_MASK_REASSOC_RESP 0x08
+/** Mask for probe request frame */
+#define MGMT_MASK_PROBE_REQ 0x10
+/** Mask for probe response frame */
+#define MGMT_MASK_PROBE_RESP 0x20
+/** Mask for beacon frame */
+#define MGMT_MASK_BEACON 0x100
+/** Mask for action frame */
+#define MGMT_MASK_ACTION 0x2000
+/** Mask to clear previous settings */
+#define MGMT_MASK_CLEAR 0x000
+
+/* Following is allocated in mlan_register */
+extern mlan_adapter *mlan_adap;
+
+#if CONFIG_WPS2
+extern int wps_session_attempt;
+#endif
+
+extern osa_rw_lock_t sleep_rwlock;
+
+#if CONFIG_WMM_UAPSD
+extern OSA_SEMAPHORE_HANDLE_DEFINE(uapsd_sem);
+#endif
+
+#if CONFIG_WMM
+extern OSA_SEMAPHORE_HANDLE_DEFINE(txbuf_sem);
+#endif
+
+extern bool sta_ampdu_rx_enable;
+#ifdef DUMP_PACKET_MAC
+void dump_mac_addr(const char *msg, unsigned char *addr);
+#endif /* DUMP_PACKET_MAC */
+mlan_status wifi_prepare_and_send_cmd(IN mlan_private *pmpriv,
+                                      IN t_u16 cmd_no,
+                                      IN t_u16 cmd_action,
+                                      IN t_u32 cmd_oid,
+                                      IN t_void *pioctl_buf,
+                                      IN t_void *pdata_buf,
+                                      mlan_bss_type bss_type,
+                                      void *priv);
+int wifi_uap_prepare_and_send_cmd(mlan_private *pmpriv,
+                                  t_u16 cmd_no,
+                                  t_u16 cmd_action,
+                                  t_u32 cmd_oid,
+                                  t_void *pioctl_buf,
+                                  t_void *pdata_buf,
+                                  mlan_bss_type bss_type,
+                                  void *priv);
+
+bool wmsdk_is_11N_enabled(void);
+
+/**
+ * Abort the split scan if it is in progress.
+ *
+ * After this call returns this scan function will abort the current split
+ * scan and return back to the caller. The scan list may be incomplete at
+ * this moment. There are no other side effects on the scan function apart
+ * from this. The next call to scan function should proceed as normal.
+ */
+void wlan_abort_split_scan(void);
+
+void wlan_scan_process_results(IN mlan_private *pmpriv);
+bool wlan_use_non_default_ht_vht_cap(IN BSSDescriptor_t *pbss_desc);
+bool check_for_wpa2_entp_ie(bool *wpa2_entp_IE_exist, const void *element_data, unsigned element_len);
+
+#if CONFIG_WPA2_ENTP
+bool wifi_get_scan_enable_wpa2_enterprise_ap_only();
+
+static inline mlan_status wifi_check_bss_entry_wpa2_entp_only(BSSDescriptor_t *pbss_entry, t_u8 element_id)
+{
+    if (element_id == RSN_IE)
+    {
+        if ((wifi_get_scan_enable_wpa2_enterprise_ap_only()) &&
+            (!check_for_wpa2_entp_ie(&pbss_entry->wpa2_entp_IE_exist, pbss_entry->rsn_ie_buff + 8,
+                                     pbss_entry->rsn_ie_buff_len - 10)))
+        {
+            return MLAN_STATUS_RESOURCE;
+        }
+        else
+        {
+            check_for_wpa2_entp_ie(&pbss_entry->wpa2_entp_IE_exist, pbss_entry->rsn_ie_buff + 8,
+                                   pbss_entry->rsn_ie_buff_len - 10);
+        }
+    }
+    else if (element_id == VENDOR_SPECIFIC_221)
+    {
+        if (wifi_get_scan_enable_wpa2_enterprise_ap_only())
+            return MLAN_STATUS_RESOURCE;
+    }
+    else if (!element_id)
+    {
+        if ((wifi_get_scan_enable_wpa2_enterprise_ap_only()) && (pbss_entry->privacy != Wlan802_11PrivFilter8021xWEP) &&
+            (!pbss_entry->pwpa_ie) && (!pbss_entry->prsn_ie))
+            return MLAN_STATUS_RESOURCE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+#else
+static inline mlan_status wifi_check_bss_entry_wpa2_entp_only(BSSDescriptor_t *pbss_entry,
+                                                              IEEEtypes_ElementId_e element_id)
+{
+    if (element_id == RSN_IE)
+    {
+        (void)check_for_wpa2_entp_ie(&pbss_entry->wpa2_entp_IE_exist, pbss_entry->rsn_ie_buff + 8,
+                                     pbss_entry->rsn_ie_buff_len - 10);
+    }
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+int wifi_request_bgscan_query(mlan_private *pmpriv);
+int wifi_send_scan_query(void);
+void wifi_get_band(mlan_private *pmpriv, int *band);
+
+int wifi_send_hostcmd(
+    const void *cmd_buf, uint32_t cmd_buf_len, void *resp_buf, uint32_t resp_buf_len, uint32_t *reqd_resp_len);
+
+int wifi_send_get_wpa_pmk(int mode, char *ssid);
+int wifi_deauthenticate(uint8_t *bssid);
+#if CONFIG_WPA_SUPP
+int wifi_nxp_deauthenticate(unsigned int bss_type, const uint8_t *bssid, uint16_t reason_code);
+void wifi_get_scan_table(mlan_private *pmpriv, mlan_scan_resp *pscan_resp);
+#endif
+int wifi_get_eeprom_data(uint32_t offset, uint32_t byte_count, uint8_t *buf);
+int wifi_get_mgmt_ie(mlan_bss_type bss_type, IEEEtypes_ElementId_t index, void *buf, unsigned int *buf_len);
+int wifi_send_remain_on_channel_cmd(unsigned int bss_type, wifi_remain_on_channel_t *remain_on_channel);
+int wifi_set_smart_mode_cfg(char *ssid,
+                            int beacon_period,
+                            wifi_chan_list_param_set_t *chan_list,
+                            uint8_t *smc_start_addr,
+                            uint8_t *smc_end_addr,
+                            uint16_t filter_type,
+                            int smc_frame_filter_len,
+                            uint8_t *smc_frame_filter,
+                            int custom_ie_len,
+                            uint8_t *custom_ie);
+int wifi_set_mgmt_ie(mlan_bss_type bss_type, IEEEtypes_ElementId_t id, void *buf, unsigned int buf_len);
+#ifdef SD8801
+int wifi_get_ext_coex_stats(wifi_ext_coex_stats_t *ext_coex_stats);
+int wifi_set_ext_coex_config(const wifi_ext_coex_config_t *ext_coex_config);
+#endif
+int wifi_send_enable_supplicant(int mode, const char *ssid);
+int wifi_send_clear_wpa_psk(int mode, const char *ssid);
+int wifi_send_add_wpa_psk(int mode, char *ssid, char *passphrase, unsigned int len);
+int wifi_send_add_wpa3_password(int mode, char *ssid, char *password, unsigned int len);
+int wifi_send_add_wpa_pmk(int mode, char *ssid, char *bssid, char *pmk, unsigned int len);
+bool wifi_11d_is_channel_allowed(int channel);
+
+#if CONFIG_11AX
+void wifi_request_get_fw_info(mlan_private *priv, mlan_fw_info *fw_info);
+
+#if CONFIG_MMSF
+int wifi_mmsf_cfg(const t_u16 action, t_u8 *enable, t_u8 *Density, t_u8 *MMSF);
+#endif
+#endif
+
+#if CONFIG_WIFI_RECOVERY
+int wifi_recovery_test(void);
+#endif
+
+/**
+ * Get the string representation of the wlan firmware extended version.
+ *
+ * @param[out] version_ext Extended Version
+ *
+ * @return WM_SUCCESS on success or error code.
+ */
+int wifi_get_firmware_version_ext(wifi_fw_version_ext_t *version_ext);
+/**
+ * Get the string representation of the wlan firmware version.
+ *
+ * @param[out] ver Version
+ *
+ * @return WM_SUCCESS on success or error code.
+ */
+int wifi_get_firmware_version(wifi_fw_version_t *ver);
+int wifi_get_smart_mode_cfg(void);
+int wifi_start_smart_mode(void);
+/**
+ * Get Calibration data from WLAN firmware
+ *
+ * \param[out] cal_data Pointer to calibration data structure where
+ *	      calibration data and it's length will be stored.
+ *
+ * \return WM_SUCCESS if cal data read operation is successful.
+ * \return -WM_FAIL if cal data field is not present or command fails.
+ *
+ * \note The user of this API should free the allocated buffer for
+ *	 calibration data.
+ *
+ */
+int wifi_get_cal_data(wifi_cal_data_t *cal_data);
+int wifi_set_key(int bss_index,
+                 bool is_pairwise,
+                 const uint8_t key_index,
+                 const uint8_t *key,
+                 unsigned key_len,
+                 const uint8_t *seq,
+                 unsigned seq_len,
+                 const uint8_t *mac_addr,
+                 unsigned int flags);
+int wifi_set_rekey_info(
+    int bss_index, const t_u8 *kek, size_t kek_len, const t_u8 *kck, size_t kck_len, const t_u8 *replay_ctr);
+
+/**
+ * Get User Data from OTP Memory
+ *
+ * \param[in] buf Pointer to buffer where data will be stored
+ * \param[in] len Number of bytes to read
+ *
+ * \return WM_SUCCESS if user data read operation is successful.
+ * \return -WM_FAIL if user data field is not present or command fails.
+ */
+int wifi_get_otp_user_data(uint8_t *buf, uint16_t len);
+int wifi_reg_access(wifi_reg_t reg_type, uint16_t action, uint32_t offset, uint32_t *value);
+int wifi_enable_11d_support_APIs(void);
+int wifi_get_tsf(uint32_t *tsf_high, uint32_t *tsf_low);
+int wifi_set_igtk_key(int bss_index, const uint8_t *pn, const uint16_t key_index, const uint8_t *key, unsigned key_len);
+int wifi_send_scan_cmd(t_u8 bss_mode,
+                       const t_u8 *specific_bssid,
+                       const char *ssid,
+                       uint8_t ssid_num,
+                       const t_u8 num_channels,
+                       const wifi_scan_channel_list_t *chan_list,
+                       const t_u8 num_probes,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                       const t_s16 rssi_threshold,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                       const t_u16 scan_chan_gap,
+#endif
+                       const bool keep_previous_scan,
+                       const bool active_scan_triggered);
+int wifi_stop_smart_mode(void);
+int wifi_remove_key(int bss_index, bool is_pairwise, const uint8_t key_index, const uint8_t *mac_addr);
+int wifi_enable_ecsa_support(void);
+int wifi_set_ed_mac_mode(wifi_ed_mac_ctrl_t *wifi_ed_mac_ctrl, int bss_type);
+int wifi_get_pmfcfg(t_u8 *mfpc, t_u8 *mfpr);
+int wifi_get_ed_mac_mode(wifi_ed_mac_ctrl_t *wifi_ed_mac_ctrl, int bss_type);
+int wifi_set_pmfcfg(t_u8 mfpc, t_u8 mfpr);
+int wifi_set_chanlist(wifi_chanlist_t *chanlist);
+int wifi_get_txpwrlimit(wifi_SubBand_t subband, wifi_txpwrlimit_t *txpwrlimit);
+int wifi_get_data_rate(wifi_ds_rate *ds_rate, mlan_bss_type bss_type);
+void wifi_get_active_channel_list(t_u8 *chan_list, t_u8 *num_chans, t_u16 acs_band);
+bool wifi_is_ecsa_enabled(void);
+int wifi_set_txpwrlimit(wifi_txpwrlimit_t *txpwrlimit);
+int wifi_send_rssi_info_cmd(wifi_rssi_info_t *rssi_info);
+void wifi_set_curr_bss_channel(uint8_t channel);
+int wifi_get_chanlist(wifi_chanlist_t *chanlist);
+int wifi_get_set_bandcfg(wifi_bandcfg_t *bandcfg, mlan_act_ioctl action);
+#if (CONFIG_IPS)
+int wifi_set_ips_config(mlan_bss_type interface, int option);
+#endif
+#if CONFIG_WIFI_EU_CRYPTO
+int wifi_set_eu_crypto(EU_Crypto *Crypto_Data, enum _crypto_algorithm Algorithm, t_u16 EncDec);
+#endif
+int wifi_set_rx_mgmt_indication(unsigned int bss_type, unsigned int mgmt_subtype_mask);
+mlan_status wlan_cmd_rx_mgmt_indication(IN pmlan_private pmpriv,
+                                        IN HostCmd_DS_COMMAND *cmd,
+                                        IN t_u16 cmd_action,
+                                        IN t_void *pdata_buf);
+wlan_mgmt_pkt *wifi_PrepDefaultMgtMsg(t_u8 sub_type,
+                                      mlan_802_11_mac_addr *DestAddr,
+                                      mlan_802_11_mac_addr *SrcAddr,
+                                      mlan_802_11_mac_addr *Bssid,
+                                      t_u16 pkt_len);
+
+#if CONFIG_11MC
+void wlan_location_ftm_cfg(location_cfg_info_t *ftm_location_cfg);
+void wlan_civic_ftm_cfg(location_civic_rep_t *ftm_civic_cfg);
+void wlan_dot11mc_ftm_cfg(void *cmd, ftm_11mc_nego_cfg_t *ftm_11mc_nego_cfg);
+#endif
+#if CONFIG_11AZ
+void wlan_dto11az_ranging_cfg(void *cmd, const t_u8 protocl, HostCmd_FTM_SESSION_CFG *ftm_session_cfg);
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+/* ftm ctrl params */
+typedef struct
+{
+    int loop_cnt;
+    t_u8 channel;
+    t_u8 peer_mac[MLAN_MAC_ADDR_LENGTH];
+    t_u8 status;
+} ftm_start_param;
+
+int wifi_unassoc_ftm_cfg(const t_u16 action, const t_u16 config);
+int wifi_ftm_start_stop(const t_u16 action, const t_u8 loop_cnt, const t_u8 *mac, const t_u8 channel);
+int wifi_ftm_start(const t_u16 action, const t_u8 *mac, const t_u8 channel);
+int wifi_ftm_stop(const t_u16 action, const t_u8 *mac, const t_u8 channel);
+int wifi_ftm_cfg(const t_u8 protocol, ranging_11az_cfg_t *ftm_ranging_cfg);
+int wifi_ftm_11mc_cfg(ftm_11mc_nego_cfg_t *ftm_11mc_nego_cfg);
+int wifi_ftm_location_cfg(location_cfg_info_t *ftm_location_cfg);
+int wifi_ftm_civic_cfg(location_civic_rep_t *ftm_civic_cfg);
+int wifi_process_wlc_ftm_event();
+void wifi_ftm_process_cfg_resp(void *resp_buff);
+void wifi_ftm_process_ctrl_resp(void *resp_buff);
+void wifi_ftm_process_event(void *p_data);
+#if CONFIG_WLS_CSI_PROC
+int wifi_process_wls_csi_event(void *p_data);
+void wls_csi_process_event(void *p_data);
+extern t_u8 g_csi_event_for_wls;
+#endif
+#endif
+
+int wifi_set_custom_ie(custom_ie *beacon_ies_data,
+                       custom_ie *beacon_wps_ies_data,
+                       custom_ie *proberesp_ies_data,
+                       custom_ie *assocresp_ies_data);
+
+#if CONFIG_11K
+/**
+ * rrm scan callback function to process scan results
+ *
+ * \param[in] count the count of available scan results
+ * \return WM_SUCCESS if successful otherwise failure.
+ *
+ */
+int _wlan_rrm_scan_cb(unsigned int count);
+
+/**
+ * rrm scan request
+ *
+ * \param[in] wlan_scan_param the scan parameters
+ * \param[in] scan_cb_param the rm scan parameters
+ *
+ */
+void wlan_rrm_request_scan(wlan_scan_params_v2_t *wlan_scan_param, wlan_rrm_scan_cb_param *scan_cb_param);
+#endif
+
+int wrapper_bssdesc_first_set(int bss_index,
+                              uint8_t *BssId,
+                              bool *is_ibss_bit_set,
+                              int *ssid_len,
+                              uint8_t *ssid,
+                              uint8_t *Channel,
+                              uint8_t *RSSI,
+                              uint16_t *beacon_period,
+                              uint16_t *dtim_period,
+                              _SecurityMode_t *WPA_WPA2_WEP,
+                              _Cipher_t *wpa_mcstCipher,
+                              _Cipher_t *wpa_ucstCipher,
+                              _Cipher_t *rsn_mcstCipher,
+                              _Cipher_t *rsn_ucstCipher,
+                              t_u8 *ap_mfpc,
+                              t_u8 *ap_mfpr,
+                              t_u8 *ap_pwe);
+
+int wrapper_bssdesc_second_set(int bss_index,
+                               bool *phtcap_ie_present,
+                               bool *phtinfo_ie_present,
+#if CONFIG_11AC
+                               bool *pvhtcap_ie_present,
+#endif
+#if CONFIG_11AX
+                               bool *phecap_ie_present,
+#endif
+                               bool *wmm_ie_present,
+                               uint16_t *band,
+                               bool *wps_IE_exist,
+                               uint16_t *wps_session,
+                               bool *wpa2_entp_IE_exist,
+#if CONFIG_11R
+                               uint16_t *mdid,
+#endif
+#if CONFIG_11K
+                               bool *neighbor_report_supported,
+#endif
+#if CONFIG_11V
+                               bool *bss_transition_supported,
+#endif
+                               uint8_t *trans_mode,
+                               uint8_t *trans_bssid,
+                               int *trans_ssid_len,
+                               uint8_t *trans_ssid
+#if CONFIG_DRIVER_MBO
+                               ,
+                               bool *mbo_assoc_disallowed
+#endif
+);
+
+int wifi_get_mgmt_ie2(mlan_bss_type bss_type, void *buf, unsigned int *buf_len);
+int wifi_set_mgmt_ie2(mlan_bss_type bss_type, unsigned short mask, void *buf, unsigned int buf_len);
+int wifi_clear_mgmt_ie2(mlan_bss_type bss_type, int mgmt_bitmap_index);
+
+int wifi_request_bgscan(mlan_private *pmpriv);
+
+#if CONFIG_WPA_SUPP
+int wifi_send_sched_scan_cmd(nxp_wifi_trigger_sched_scan_t *params);
+int wifi_send_stop_sched_scan_cmd(void);
+#endif
+
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+/*submit subscribe event cmd to firmware*/
+int wifi_subscribe_event_submit(mlan_private *pmpriv, mlan_ds_subscribe_evt *sub_evt);
+
+/*get subscribe event*/
+int wifi_get_subscribe_event(mlan_private *pmpriv, mlan_ds_subscribe_evt *sub_evt);
+
+/*disable specific subscribe event*/
+int wifi_clear_subscribe_event(mlan_private *pmpriv, int evt_bitmap);
+
+/*set subscribe event thresh_value and freq*/
+int wifi_set_threshold_rssi_low(mlan_private *pmpriv, unsigned int rssi_low, unsigned int freq);
+int wifi_set_threshold_rssi_high(mlan_private *pmpriv, unsigned int rssi_high, unsigned int freq);
+int wifi_set_threshold_snr_low(mlan_private *pmpriv, unsigned int snr_low, unsigned int freq);
+int wifi_set_threshold_snr_high(mlan_private *pmpriv, unsigned int snr_high, unsigned int freq);
+int wifi_set_threshold_max_fail(mlan_private *pmpriv, unsigned int max_fail, unsigned int freq);
+int wifi_set_threshold_beacon_miss(mlan_private *pmpriv, unsigned int beacon_miss, unsigned int freq);
+int wifi_set_threshold_data_rssi_low(mlan_private *pmpriv, unsigned int data_rssi_low, unsigned int freq);
+int wifi_set_threshold_data_rssi_high(mlan_private *pmpriv, unsigned int data_rssi_high, unsigned int freq);
+int wifi_set_threshold_data_snr_low(mlan_private *pmpriv, unsigned int data_snr_low, unsigned int freq);
+int wifi_set_threshold_data_snr_high(mlan_private *pmpriv, unsigned int data_snr_high, unsigned int freq);
+int wifi_set_threshold_link_quality(mlan_private *pmpriv,
+                                    unsigned int link_snr,
+                                    unsigned int link_snr_freq,
+                                    unsigned int link_rate,
+                                    unsigned int link_rate_freq,
+                                    unsigned int link_tx_latency,
+                                    unsigned int link_tx_lantency_freq);
+int wifi_set_threshold_pre_beacon_lost(mlan_private *pmpriv, unsigned int pre_beacon_lost, unsigned int freq);
+#endif
+
+#if CONFIG_TSP
+int wifi_tsp_cfg(const t_u16 action,
+                 t_u16 *enable,
+                 t_u32 *back_off,
+                 t_u32 *highThreshold,
+                 t_u32 *lowThreshold,
+                 t_u32 *dutycycstep,
+                 t_u32 *dutycycmin,
+                 int *highthrtemp,
+                 int *lowthrtemp,
+                 int *currCAUTemp,
+                 int *currRFUTemp);
+#endif
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+int wifi_tx_ampdu_prot_mode(tx_ampdu_prot_mode_para *prot_mode, t_u16 action);
+#endif
+
+#if CONFIG_EXTERNAL_COEX_PTA
+int wifi_external_coex_pta_cfg(ext_coex_pta_cfg coex_pta_config);
+#endif
+
+#if CONFIG_IMD3_CFG
+int wifi_imd3_cfg(t_u8 imd3_value);
+#endif
+
+#if CONFIG_AUTO_RECONNECT
+int wifi_auto_reconnect_enable(wifi_auto_reconnect_config_t auto_reconnect_config);
+int wifi_auto_reconnect_disable(void);
+int wifi_get_auto_reconnect_config(wifi_auto_reconnect_config_t *auto_reconnect_config);
+#endif
+
+#if CONFIG_INACTIVITY_TIMEOUT_EXT
+int wifi_sta_inactivityto(wifi_inactivity_to_t *inac_to, t_u16 cmd_action);
+#endif
+#endif /* __MLAN_API_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_decl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_decl.h
new file mode 100644
index 0000000000..bc66150d18
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_decl.h
@@ -0,0 +1,1035 @@
+/** @file mlan_decl.h
+ *
+ *  @brief This file declares the generic data structures and APIs.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    11/07/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_DECL_H_
+#define _MLAN_DECL_H_
+
+#include "type_decls.h"
+#include <osa.h>
+#if CONFIG_WPA_SUPP
+#include <ieee802_11_defs.h>
+#endif
+
+/** MLAN release version */
+#define MLAN_RELEASE_VERSION "310"
+
+/** Constants below */
+
+#ifdef __GNUC__
+/** Structure packing begins */
+#define MLAN_PACK_START
+/** Structure packeing end */
+#define MLAN_PACK_END __attribute__((packed))
+#else /* !__GNUC__ */
+#ifdef PRAGMA_PACK
+/** Structure packing begins */
+#define MLAN_PACK_START
+/** Structure packeing end */
+#define MLAN_PACK_END
+#else /* !PRAGMA_PACK */
+/** Structure packing begins */
+#define MLAN_PACK_START __packed
+/** Structure packing end */
+#define MLAN_PACK_END
+#endif /* PRAGMA_PACK */
+#endif /* __GNUC__ */
+
+#ifndef INLINE
+#ifdef __GNUC__
+/** inline directive */
+#define INLINE inline
+#else
+/** inline directive */
+#define INLINE __inline
+#endif
+#endif
+
+/** MLAN TRUE */
+#define MTRUE (1)
+/** MLAN FALSE */
+#define MFALSE (0)
+
+/** Macros for Data Alignment : size */
+#define ALIGN_SZ(p, a) (((p) + ((a)-1U)) & ~((a)-1U))
+
+/** Macros for Data Alignment : address */
+#define ALIGN_ADDR(p, a) ((((t_ptr)(p)) + (((t_ptr)(a)) - 1U)) & ~(((t_ptr)(a)) - 1U))
+
+#ifndef MACSTR
+/** MAC address security format */
+#define MACSTR "%02x:XX:XX:XX:%02x:%02x"
+#endif
+
+#ifndef MAC2STR
+/** MAC address security print arguments */
+#define MAC2STR(a) (a)[0], (a)[4], (a)[5]
+#endif
+
+/** Return the byte offset of a field in the given structure */
+#define MLAN_FIELD_OFFSET(type, field) ((t_u32)(t_ptr) & (((type *)0)->field))
+/** Return aligned offset */
+#define OFFSET_ALIGN_ADDR(p, a) (t_u32)(ALIGN_ADDR(p, a) - (t_ptr)p)
+
+/** Maximum BSS numbers */
+/* fixme: We have reduced this from 16 to 2. Ensure that this is Ok */
+#define MLAN_MAX_BSS_NUM 2U
+
+/** NET IP alignment */
+#define MLAN_NET_IP_ALIGN 0
+
+/** DMA alignment */
+#define DMA_ALIGNMENT 32U
+/** max size of TxPD */
+#define MAX_TXPD_SIZE 32
+
+/** Minimum data header length */
+#define MLAN_MIN_DATA_HEADER_LEN (DMA_ALIGNMENT + MAX_TXPD_SIZE)
+
+/** rx data header length */
+#define MLAN_RX_HEADER_LEN MLAN_MIN_DATA_HEADER_LEN
+
+/** This is current limit on Maximum Tx AMPDU allowed */
+#define MLAN_MAX_TX_BASTREAM_SUPPORTED 2U
+/** This is current limit on Maximum Rx AMPDU allowed */
+#define MLAN_MAX_RX_BASTREAM_SUPPORTED 16
+
+/** US country code */
+#define COUNTRY_CODE_US 0x10
+
+/** Default Win size attached during ADDBA request */
+#ifndef MLAN_STA_AMPDU_DEF_TXWINSIZE
+#if defined(SD9177) && defined(COEX_APP_SUPPORT)
+#define MLAN_STA_AMPDU_DEF_TXWINSIZE 32
+#else
+#define MLAN_STA_AMPDU_DEF_TXWINSIZE 64
+#endif
+#endif
+
+/** Default Win size attached during ADDBA response */
+#ifndef MLAN_STA_AMPDU_DEF_RXWINSIZE
+#if defined(SD9177) && !defined(COEX_APP_SUPPORT)
+#define MLAN_STA_AMPDU_DEF_RXWINSIZE 64
+#else
+#define MLAN_STA_AMPDU_DEF_RXWINSIZE 32
+#endif
+#endif
+
+/** Default Win size attached during ADDBA request */
+#ifndef MLAN_UAP_AMPDU_DEF_TXWINSIZE
+#if defined(SD9177) && defined(COEX_APP_SUPPORT)
+#define MLAN_UAP_AMPDU_DEF_TXWINSIZE 32
+#else
+#define MLAN_UAP_AMPDU_DEF_TXWINSIZE 64
+#endif
+#endif
+
+/** Default Win size attached during ADDBA response */
+#ifndef MLAN_UAP_AMPDU_DEF_RXWINSIZE
+#if defined(SD9177) && !defined(COEX_APP_SUPPORT)
+#define MLAN_UAP_AMPDU_DEF_RXWINSIZE 64
+#else
+#define MLAN_UAP_AMPDU_DEF_RXWINSIZE 32
+#endif
+#endif
+
+
+/** Block ack timeout value */
+#define MLAN_DEFAULT_BLOCK_ACK_TIMEOUT 0U
+/** Maximum Tx Win size configured for ADDBA request [10 bits] */
+#define MLAN_AMPDU_MAX_TXWINSIZE 0x3ff
+/** Maximum Rx Win size configured for ADDBA request [10 bits] */
+#define MLAN_AMPDU_MAX_RXWINSIZE 0x3ff
+
+/** Rate index for HR/DSSS 0 */
+#define MLAN_RATE_INDEX_HRDSSS0 0
+/** Rate index for HR/DSSS 3 */
+#define MLAN_RATE_INDEX_HRDSSS3 3
+/** Rate index for OFDM 0 */
+#define MLAN_RATE_INDEX_OFDM0 4U
+/** Rate index for OFDM 7 */
+#define MLAN_RATE_INDEX_OFDM7 11
+/** Rate index for MCS 0 */
+#define MLAN_RATE_INDEX_MCS0 0U
+/** Rate index for MCS 2 */
+#define MLAN_RATE_INDEX_MCS2 2U
+/** Rate index for MCS 4 */
+#define MLAN_RATE_INDEX_MCS4 4U
+/** Rate index for MCS 7 */
+#define MLAN_RATE_INDEX_MCS7 7U
+/** Rate index for MCS 8 */
+#define MLAN_RATE_INDEX_MCS8 8U
+/** Rate index for MCS 9 */
+#define MLAN_RATE_INDEX_MCS9 9U
+#if CONFIG_11AX
+/** Rate index for MCS11 */
+#define MLAN_RATE_INDEX_MCS11 11U
+#endif
+/** Rate index for MCS 32 */
+#define MLAN_RATE_INDEX_MCS32 32U
+/** Rate index for MCS 127 */
+#define MLAN_RATE_INDEX_MCS127 127U
+#if (CONFIG_11AC) || (CONFIG_11AX)
+#define MLAN_RATE_NSS1 1
+#define MLAN_RATE_NSS2 2
+#endif
+
+/** Rate bitmap for OFDM 0 */
+#define MLAN_RATE_BITMAP_OFDM0 16
+/** Rate bitmap for OFDM 7 */
+#define MLAN_RATE_BITMAP_OFDM7 23
+/** Rate bitmap for MCS 0 */
+#define MLAN_RATE_BITMAP_MCS0 32U
+/** Rate bitmap for MCS 127 */
+#define MLAN_RATE_BITMAP_MCS127 159
+#if CONFIG_11AC
+#define MLAN_RATE_BITMAP_NSS1_MCS0 160
+#define MLAN_RATE_BITMAP_NSS1_MCS9 169
+#define MLAN_RATE_BITMAP_NSS2_MCS0 176
+#define MLAN_RATE_BITMAP_NSS2_MCS9 185
+#endif
+
+/** MU beamformer */
+#define DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK (MBIT(19))
+#ifdef RW610
+/** Short GI for 80MHz/TVHT_MODE_4C */
+#define DEFALUT_11AC_CAP_SHORTGI_80MHZ_RESET_MASK (MBIT(5))
+/** HE Phy Cap Info(40MHz in 2.4GHz band) */
+#define DEFAULT_11AX_CAP_40MHZIH2_4GHZBAND_RESET_MASK (MBIT(1))
+#endif
+
+/** Size of rx data buffer */
+#define MLAN_RX_DATA_BUF_SIZE (4 * 1024)
+/** Size of rx command buffer */
+#define MLAN_RX_CMD_BUF_SIZE (2 * 1024)
+
+/** MLAN MAC Address Length */
+#define MLAN_MAC_ADDR_LENGTH (6U)
+/** MLAN 802.11 MAC Address */
+typedef t_u8 mlan_802_11_mac_addr[MLAN_MAC_ADDR_LENGTH];
+
+/** MLAN Maximum SSID Length */
+#define MLAN_MAX_SSID_LENGTH (32U)
+
+/** RTS/FRAG related defines */
+/** Minimum RTS value */
+#define MLAN_RTS_MIN_VALUE (0)
+/** Maximum RTS value */
+#define MLAN_RTS_MAX_VALUE (2347)
+/** Minimum FRAG value */
+#define MLAN_FRAG_MIN_VALUE (256)
+/** Maximum FRAG value */
+#define MLAN_FRAG_MAX_VALUE (2346)
+
+/** Minimum tx retry count */
+#define MLAN_TX_RETRY_MIN (0)
+/** Maximum tx retry count */
+#define MLAN_TX_RETRY_MAX (14)
+
+/** define SDIO block size for data Tx/Rx */
+/* We support up to 480-byte block size due to FW buffer limitation. */
+#define MLAN_SDIO_BLOCK_SIZE 256U
+
+/** define SDIO block size for firmware download */
+#define MLAN_SDIO_BLOCK_SIZE_FW_DNLD MLAN_SDIO_BLOCK_SIZE
+
+/** define allocated buffer size */
+#define ALLOC_BUF_SIZE (4 * 1024)
+
+/** SDIO IO Port mask */
+#define MLAN_SDIO_IO_PORT_MASK 0xfffff
+/** SDIO Block/Byte mode mask */
+#define MLAN_SDIO_BYTE_MODE_MASK 0x80000000U
+
+/** Max retry number of IO write */
+#define MAX_READ_IOMEM_RETRY 2
+
+/** IN parameter */
+#define IN
+/** OUT parameter */
+#define OUT
+
+/** BIT value */
+#define MBIT(x) (((t_u32)1) << (x))
+
+#define MRVL_PKT_TYPE_MGMT_FRAME 0xE5
+
+/** Buffer flag for requeued packet */
+#define MLAN_BUF_FLAG_REQUEUED_PKT MBIT(0)
+/** Buffer flag for transmit buf from moal */
+#define MLAN_BUF_FLAG_MOAL_TX_BUF MBIT(1)
+/** Buffer flag for malloc mlan_buffer */
+#define MLAN_BUF_FLAG_MALLOC_BUF MBIT(2)
+
+/** Buffer flag for bridge packet */
+#define MLAN_BUF_FLAG_BRIDGE_BUF MBIT(3)
+
+/** Buffer flag for TX_STATUS */
+#define MLAN_BUF_FLAG_TX_STATUS MBIT(10)
+
+#ifdef DEBUG_LEVEL1
+/** Debug level bit definition */
+#define MMSG   MBIT(0)
+#define MFATAL MBIT(1)
+#define MERROR MBIT(2)
+#define MDATA  MBIT(3)
+#define MCMND  MBIT(4)
+#define MEVENT MBIT(5)
+#define MINTR  MBIT(6)
+#define MIOCTL MBIT(7)
+
+#define MDAT_D MBIT(16)
+#define MCMD_D MBIT(17)
+#define MEVT_D MBIT(18)
+#define MFW_D  MBIT(19)
+#define MIF_D  MBIT(20)
+
+#define MENTRY    MBIT(28)
+#define MWARN     MBIT(29)
+#define MINFO     MBIT(30)
+#define MHEX_DUMP MBIT(31)
+#endif /* DEBUG_LEVEL1 */
+
+/** Memory allocation type: DMA */
+#define MLAN_MEM_DMA MBIT(0U)
+
+/** Default memory allocation flag */
+#define MLAN_MEM_DEF 0U
+
+#if CONFIG_WIFI_IND_DNLD
+/** driver initial the fw reset */
+#define FW_RELOAD_SDIO_INBAND_RESET 1
+/** out band reset trigger reset, no interface re-emulation */
+#define FW_RELOAD_NO_EMULATION 2
+/** out band reset with interface re-emulation */
+#define FW_RELOAD_WITH_EMULATION 3
+/** sdio hw reset */
+#define FW_RELOAD_SDIO_HW_RESET 5
+#endif
+
+/** MrvlExtIEtypesHeader_t */
+typedef MLAN_PACK_START struct _MrvlExtIEtypesHeader
+{
+    /** Header type */
+    t_u16 type;
+    /** Header length */
+    t_u16 len;
+    /** ext id */
+    t_u8 ext_id;
+} MLAN_PACK_END MrvlExtIEtypesHeader_t;
+
+/** MrvlIEtypes_Data_t */
+typedef MLAN_PACK_START struct _MrvlExtIEtypes_Data_t
+{
+    /** Header */
+    MrvlExtIEtypesHeader_t header;
+    /** Data */
+    t_u8 data[];
+} MLAN_PACK_END MrvlExtIEtypes_Data_t;
+
+/** mlan_status */
+typedef enum _mlan_status
+{
+    MLAN_STATUS_FAILURE = 0xffffffff,
+    MLAN_STATUS_SUCCESS = 0,
+    MLAN_STATUS_PENDING,
+    MLAN_STATUS_RESOURCE,
+} mlan_status;
+
+/** mlan_error_code */
+typedef enum _mlan_error_code
+{
+    /** No error */
+    MLAN_ERROR_NO_ERROR = 0,
+    /** Firmware/device errors below (MSB=0) */
+    MLAN_ERROR_FW_NOT_READY = 0x00000001,
+    MLAN_ERROR_FW_BUSY,
+    MLAN_ERROR_FW_CMDRESP,
+    MLAN_ERROR_DATA_TX_FAIL,
+    MLAN_ERROR_DATA_RX_FAIL,
+    /** Driver errors below (MSB=1) */
+    MLAN_ERROR_PKT_SIZE_INVALID = 0x80000001,
+    MLAN_ERROR_PKT_TIMEOUT,
+    MLAN_ERROR_PKT_INVALID,
+    MLAN_ERROR_CMD_INVALID,
+    MLAN_ERROR_CMD_TIMEOUT,
+    MLAN_ERROR_CMD_DNLD_FAIL,
+    MLAN_ERROR_CMD_CANCEL,
+    MLAN_ERROR_CMD_RESP_FAIL,
+    MLAN_ERROR_CMD_ASSOC_FAIL,
+    MLAN_ERROR_CMD_SCAN_FAIL,
+    MLAN_ERROR_IOCTL_INVALID,
+    MLAN_ERROR_IOCTL_FAIL,
+    MLAN_ERROR_EVENT_UNKNOWN,
+    MLAN_ERROR_INVALID_PARAMETER,
+    MLAN_ERROR_NO_MEM,
+    /** More to add */
+} mlan_error_code;
+
+/** mlan_buf_type */
+typedef enum _mlan_buf_type
+{
+    MLAN_BUF_TYPE_CMD = 1,
+    MLAN_BUF_TYPE_DATA,
+    MLAN_BUF_TYPE_EVENT,
+    MLAN_BUF_TYPE_RAW_DATA,
+} mlan_buf_type;
+
+/** MLAN BSS type */
+typedef enum _mlan_bss_type
+{
+    MLAN_BSS_TYPE_STA = 0,
+    MLAN_BSS_TYPE_UAP = 1,
+    /* fixme: This macro will be enabled when
+     * mlan is completely integrated with wlan
+     */
+    /* #ifdef WIFI_DIRECT_SUPPORT*/
+    MLAN_BSS_TYPE_WIFIDIRECT = 2,
+    /*#endif*/
+    MLAN_BSS_TYPE_ANY = 0xff,
+} mlan_bss_type;
+
+/** MLAN BSS role */
+typedef enum _mlan_bss_role
+{
+    MLAN_BSS_ROLE_STA = 0,
+    MLAN_BSS_ROLE_UAP = 1,
+    MLAN_BSS_ROLE_ANY = 0xff,
+} mlan_bss_role;
+
+/** BSS role bit mask */
+#define BSS_ROLE_BIT_MASK MBIT(0)
+
+/** Get BSS role */
+#define GET_BSS_ROLE(priv) ((unsigned)(priv)->bss_role & (BSS_ROLE_BIT_MASK))
+
+/** mlan_data_frame_type */
+typedef enum _mlan_data_frame_type
+{
+    MLAN_DATA_FRAME_TYPE_ETH_II = 0,
+    MLAN_DATA_FRAME_TYPE_802_11,
+} mlan_data_frame_type;
+
+/** mlan_event_id */
+typedef enum _mlan_event_id
+{
+    /* Event generated by firmware (MSB=0) */
+    MLAN_EVENT_ID_FW_UNKNOWN = 0x00000001,
+    MLAN_EVENT_ID_FW_ADHOC_LINK_SENSED,
+    MLAN_EVENT_ID_FW_ADHOC_LINK_LOST,
+    MLAN_EVENT_ID_FW_DISCONNECTED,
+    MLAN_EVENT_ID_FW_MIC_ERR_UNI,
+    MLAN_EVENT_ID_FW_MIC_ERR_MUL,
+    MLAN_EVENT_ID_FW_BCN_RSSI_LOW,
+    MLAN_EVENT_ID_FW_BCN_RSSI_HIGH,
+    MLAN_EVENT_ID_FW_BCN_SNR_LOW,
+    MLAN_EVENT_ID_FW_BCN_SNR_HIGH,
+    MLAN_EVENT_ID_FW_MAX_FAIL,
+    MLAN_EVENT_ID_FW_DATA_RSSI_LOW,
+    MLAN_EVENT_ID_FW_DATA_RSSI_HIGH,
+    MLAN_EVENT_ID_FW_DATA_SNR_LOW,
+    MLAN_EVENT_ID_FW_DATA_SNR_HIGH,
+    MLAN_EVENT_ID_FW_LINK_QUALITY,
+    MLAN_EVENT_ID_FW_PORT_RELEASE,
+    MLAN_EVENT_ID_FW_PRE_BCN_LOST,
+    MLAN_EVENT_ID_FW_WMM_CONFIG_CHANGE,
+    MLAN_EVENT_ID_FW_HS_WAKEUP,
+    MLAN_EVENT_ID_FW_BG_SCAN,
+    MLAN_EVENT_ID_FW_WEP_ICV_ERR,
+    MLAN_EVENT_ID_FW_STOP_TX,
+    MLAN_EVENT_ID_FW_START_TX,
+    MLAN_EVENT_ID_FW_CHANNEL_SWITCH_ANN,
+    MLAN_EVENT_ID_FW_RADAR_DETECTED,
+    MLAN_EVENT_ID_FW_CHANNEL_REPORT_RDY,
+    MLAN_EVENT_ID_FW_BW_CHANGED,
+    MLAN_EVENT_ID_UAP_FW_BSS_START,
+    MLAN_EVENT_ID_UAP_FW_BSS_ACTIVE,
+    MLAN_EVENT_ID_UAP_FW_BSS_IDLE,
+    MLAN_EVENT_ID_UAP_FW_STA_CONNECT,
+    MLAN_EVENT_ID_UAP_FW_STA_DISCONNECT,
+
+    /* Event generated by MLAN driver (MSB=1) */
+    MLAN_EVENT_ID_DRV_CONNECTED = 0x80000001,
+    MLAN_EVENT_ID_DRV_DEFER_HANDLING,
+    MLAN_EVENT_ID_DRV_HS_ACTIVATED,
+    MLAN_EVENT_ID_DRV_HS_DEACTIVATED,
+    MLAN_EVENT_ID_DRV_MGMT_FRAME,
+    MLAN_EVENT_ID_DRV_OBSS_SCAN_PARAM,
+    MLAN_EVENT_ID_DRV_PASSTHRU,
+    MLAN_EVENT_ID_DRV_SCAN_REPORT,
+    MLAN_EVENT_ID_DRV_MEAS_REPORT,
+    MLAN_EVENT_ID_DRV_ASSOC_FAILURE_REPORT,
+    MLAN_EVENT_ID_DRV_REPORT_STRING,
+    MLAN_EVENT_ID_DRV_DBG_DUMP,
+} mlan_event_id;
+
+/** Data Structures */
+/** mlan_image data structure */
+typedef struct _mlan_fw_image
+{
+    /** Helper image buffer pointer */
+    t_u8 *phelper_buf;
+    /** Helper image length */
+    t_u32 helper_len;
+    /** Firmware image buffer pointer */
+    t_u8 *pfw_buf;
+    /** Firmware image length */
+    t_u32 fw_len;
+#if CONFIG_WIFI_IND_DNLD
+    /** Firmware reload flag */
+    t_u8 fw_reload;
+#endif
+} mlan_fw_image, *pmlan_fw_image;
+
+/** Custom data structure */
+typedef struct _mlan_init_param
+{
+    /** Cal data buffer pointer */
+    t_u8 *pcal_data_buf;
+    /** Cal data length */
+    t_u32 cal_data_len;
+    /** Other custom data */
+} mlan_init_param, *pmlan_init_param;
+
+/** Channel usability flags */
+#define NXP_CHANNEL_NO_OFDM  MBIT(9)
+#define NXP_CHANNEL_NO_CCK   MBIT(8)
+#define NXP_CHANNEL_DISABLED MBIT(7)
+/* BIT 5/6 resevered for FW */
+#define NXP_CHANNEL_NOHT160 MBIT(4)
+#define NXP_CHANNEL_NOHT80  MBIT(3)
+#define NXP_CHANNEL_NOHT40  MBIT(2)
+#define NXP_CHANNEL_DFS     MBIT(1)
+#define NXP_CHANNEL_PASSIVE MBIT(0)
+
+/** CFP dynamic (non-const) elements */
+typedef struct _cfp_dyn_t
+{
+    /** extra flags to specify channel usability
+     *  bit 9 : if set, channel is non-OFDM
+     *  bit 8 : if set, channel is non-CCK
+     *  bit 7 : if set, channel is disabled
+     *  bit  5/6 resevered for FW
+     *  bit 4 : if set, 160MHz on channel is disabled
+     *  bit 3 : if set, 80MHz on channel is disabled
+     *  bit 2 : if set, 40MHz on channel is disabled
+     *  bit 1 : if set, channel is DFS channel
+     *  bit 0 : if set, channel is passive
+     */
+    t_u16 flags;
+    /** TRUE: Channel is blacklisted (do not use) */
+    t_bool blacklist;
+} cfp_dyn_t;
+
+/** Chan-Freq-TxPower mapping table*/
+typedef struct _chan_freq_power_t
+{
+    /** Channel Number */
+    t_u16 channel;
+    /** Frequency of this Channel */
+    t_u32 freq;
+    /** Max allowed Tx power level */
+    t_u16 max_tx_power;
+    /** TRUE:radar detect required for BAND A or passive scan for BAND B/G;
+     * FALSE:radar detect not required for BAND A or active scan for BAND B/G*/
+    t_bool passive_scan_or_radar_detect;
+    /** Elements associated to cfp that change at run-time */
+    cfp_dyn_t dynamic;
+} chan_freq_power_t;
+
+/** mlan_event data structure */
+typedef struct _mlan_event
+{
+    /** BSS index number for multiple BSS support */
+    t_u32 bss_index;
+    /** Event ID */
+    mlan_event_id event_id;
+    /** Event length */
+    t_u32 event_len;
+    /** Event buffer */
+    t_u8 event_buf[1];
+} mlan_event, *pmlan_event;
+
+
+#if CONFIG_EXT_SCAN_SUPPORT
+/** mlan_event_scan_result data structure */
+typedef MLAN_PACK_START struct _mlan_event_scan_result
+{
+    /** Event ID */
+    t_u16 event_id;
+    /** BSS index number for multiple BSS support */
+    t_u8 bss_index;
+    /** BSS type */
+    t_u8 bss_type;
+    /** More event available or not */
+    t_u8 more_event;
+    /** Reserved */
+    t_u8 reserved[3];
+    /** Size of the response buffer */
+    t_u16 buf_size;
+    /** Number of BSS in scan response */
+    t_u8 num_of_set;
+} MLAN_PACK_END mlan_event_scan_result, *pmlan_event_scan_result;
+#endif
+
+/** mlan_buffer data structure */
+typedef struct _mlan_buffer
+{
+    /** Pointer to previous mlan_buffer */
+    // struct _mlan_buffer *pprev;
+    /** Pointer to next mlan_buffer */
+    // struct _mlan_buffer *pnext;
+    /** Status code from firmware/driver */
+    t_u32 status_code;
+    /** Flags for this buffer */
+    t_u32 flags;
+    /** BSS index number for multiple BSS support */
+    t_u32 bss_index;
+    /** Buffer descriptor, e.g. skb in Linux */
+    t_void *pdesc;
+    /** Private member added for WMSDK. This is used to store the lwip pbuf
+ pointer */
+    t_void *lwip_pbuf;
+    /** Pointer to buffer */
+    t_u8 *pbuf;
+    /** Offset to data */
+    t_u32 data_offset;
+    /** Data length */
+    t_u32 data_len;
+    /** Buffer type: data, cmd, event etc. */
+    mlan_buf_type buf_type;
+
+    /** Fields below are valid for data packet only */
+    /** QoS priority */
+    t_u32 priority;
+    /** Time stamp when packet is received (seconds) */
+    // t_u32 in_ts_sec;
+    /** Time stamp when packet is received (micro seconds) */
+    // t_u32 in_ts_usec;
+    /** Time stamp when packet is processed (seconds) */
+    // t_u32 out_ts_sec;
+    /** Time stamp when packet is processed (micro seconds) */
+    // t_u32 out_ts_usec;
+
+    /** Fields below are valid for MLAN module only */
+    /** Pointer to parent mlan_buffer */
+    // struct _mlan_buffer *pparent;
+    /** Use count for this buffer */
+    t_u32 use_count;
+} mlan_buffer, *pmlan_buffer;
+
+/** mlan_bss_attr data structure */
+typedef struct _mlan_bss_attr
+{
+    /** BSS type */
+    mlan_bss_type bss_type;
+    /** Data frame type: Ethernet II, 802.11, etc. */
+    t_u32 frame_type;
+    /** The BSS is active (non-0) or not (0). */
+    t_u32 active;
+    /** BSS Priority */
+    t_u32 bss_priority;
+    /** BSS number */
+    t_u32 bss_num;
+} mlan_bss_attr, *pmlan_bss_attr;
+
+#ifdef PRAGMA_PACK
+#pragma pack(push, 1)
+#endif
+
+/** Type enumeration for the command result */
+typedef MLAN_PACK_START enum _mlan_cmd_result_e {
+    MLAN_CMD_RESULT_SUCCESS      = 0,
+    MLAN_CMD_RESULT_FAILURE      = 1,
+    MLAN_CMD_RESULT_TIMEOUT      = 2,
+    MLAN_CMD_RESULT_INVALID_DATA = 3
+} MLAN_PACK_END mlan_cmd_result_e;
+
+#define WMM_AC_BK 0
+#define WMM_AC_BE 1
+#define WMM_AC_VI 2
+#define WMM_AC_VO 3
+
+typedef t_u8 mlan_wmm_ac_e;
+
+/** Type enumeration for the action field in the Queue Config command */
+typedef MLAN_PACK_START enum _mlan_wmm_queue_config_action_e {
+    MLAN_WMM_QUEUE_CONFIG_ACTION_GET     = 0,
+    MLAN_WMM_QUEUE_CONFIG_ACTION_SET     = 1,
+    MLAN_WMM_QUEUE_CONFIG_ACTION_DEFAULT = 2,
+    MLAN_WMM_QUEUE_CONFIG_ACTION_MAX
+} MLAN_PACK_END mlan_wmm_queue_config_action_e;
+
+/** Type enumeration for the action field in the queue stats command */
+typedef MLAN_PACK_START enum _mlan_wmm_queue_stats_action_e {
+    MLAN_WMM_STATS_ACTION_START   = 0,
+    MLAN_WMM_STATS_ACTION_STOP    = 1,
+    MLAN_WMM_STATS_ACTION_GET_CLR = 2,
+    MLAN_WMM_STATS_ACTION_SET_CFG = 3, /* Not currently used */
+    MLAN_WMM_STATS_ACTION_GET_CFG = 4, /* Not currently used */
+    MLAN_WMM_STATS_ACTION_MAX
+} MLAN_PACK_END mlan_wmm_queue_stats_action_e;
+
+/**
+ *  @brief IOCTL structure for a Traffic stream status.
+ *
+ */
+typedef MLAN_PACK_START struct
+{
+    /** TSID: Range: 0->7 */
+    t_u8 tid;
+    /** TSID specified is valid */
+    t_u8 valid;
+    /** AC TSID is active on */
+    t_u8 access_category;
+    /** UP specified for the TSID */
+    t_u8 user_priority;
+    /** Power save mode for TSID: 0 (legacy), 1 (UAPSD) */
+    t_u8 psb;
+    /** Upstream(0), Downlink(1), Bidirectional(3) */
+    t_u8 flow_dir;
+    /** Medium time granted for the TSID */
+    t_u16 medium_time;
+} MLAN_PACK_END wlan_ioctl_wmm_ts_status_t,
+    /** Type definition of mlan_ds_wmm_ts_status for MLAN_OID_WMM_CFG_TS_STATUS */
+    mlan_ds_wmm_ts_status, *pmlan_ds_wmm_ts_status;
+
+/** Max Ie length */
+#define MAX_IE_SIZE 256U
+
+/** custom IE */
+typedef MLAN_PACK_START struct _custom_ie
+{
+    /** IE Index */
+    t_u16 ie_index;
+    /** Mgmt Subtype Mask */
+    t_u16 mgmt_subtype_mask;
+    /** IE Length */
+    t_u16 ie_length;
+    /** IE buffer */
+    t_u8 ie_buffer[MAX_IE_SIZE];
+} MLAN_PACK_END custom_ie;
+
+/** TLV buffer : custom IE */
+typedef MLAN_PACK_START struct _tlvbuf_custom_ie
+{
+    /** Tag */
+    t_u16 type;
+    /** Length */
+    t_u16 length;
+    /** custom IE data */
+    custom_ie ie_data[0];
+} MLAN_PACK_END tlvbuf_custom_ie;
+
+/** Max IE index to FW */
+#define MAX_MGMT_IE_INDEX_TO_FW 4U
+/** Max IE index per BSS */
+#define MAX_MGMT_IE_INDEX 16
+
+/** custom IE info */
+typedef MLAN_PACK_START struct _custom_ie_info
+{
+    /** size of buffer */
+    t_u16 buf_size;
+    /** no of buffers of buf_size */
+    t_u16 buf_count;
+} MLAN_PACK_END custom_ie_info;
+
+/** TLV buffer : Max Mgmt IE */
+typedef MLAN_PACK_START struct _tlvbuf_max_mgmt_ie
+{
+    /** Type */
+    t_u16 type;
+    /** Length */
+    t_u16 len;
+    /** No of tuples */
+    t_u16 count;
+    /** custom IE info tuples */
+    custom_ie_info info[MAX_MGMT_IE_INDEX];
+} MLAN_PACK_END tlvbuf_max_mgmt_ie;
+
+/** TLV buffer : custom IE */
+typedef MLAN_PACK_START struct _mlan_ds_misc_custom_ie
+{
+    /** Type */
+    t_u16 type;
+    /** Length */
+    t_u16 len;
+    /** IE data */
+    custom_ie ie_data_list[MAX_MGMT_IE_INDEX_TO_FW];
+    /** Max mgmt IE TLV */
+    tlvbuf_max_mgmt_ie max_mgmt_ie;
+} MLAN_PACK_END mlan_ds_misc_custom_ie;
+
+/** channel type */
+enum mlan_channel_type
+{
+    CHAN_NO_HT,
+    CHAN_HT20,
+    CHAN_HT40MINUS,
+    CHAN_HT40PLUS,
+    CHAN_VHT80
+};
+
+/** channel band */
+enum
+{
+    BAND_2GHZ = 0,
+    BAND_5GHZ = 1,
+    BAND_6GHZ = 2,
+    BAND_4GHZ = 3,
+};
+
+/** Band_Config_t */
+typedef MLAN_PACK_START struct _Band_Config_t
+{
+    /** Band Info - (00)=2.4GHz, (01)=5GHz */
+    t_u8 chanBand : 2;
+    /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */
+    t_u8 chanWidth : 2;
+    /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */
+    t_u8 chan2Offset : 2;
+    /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=Adoption mode*/
+    t_u8 scanMode : 2;
+} MLAN_PACK_END Band_Config_t;
+
+/** channel_band_t */
+typedef MLAN_PACK_START struct _chan_band_info
+{
+    /** Band Configuration */
+    Band_Config_t bandcfg;
+    /** channel */
+    t_u8 channel;
+    /** 11n flag */
+    t_u8 is_11n_enabled;
+    /** center channel */
+    t_u8 center_chan;
+#if defined(ENABLE_802_11H) && defined(DFS_SUPPORT)
+    /** dfs channel flag */
+    t_u8 is_dfs_chan;
+#endif
+} MLAN_PACK_END chan_band_info;
+
+/** csi event data structure */
+#if CONFIG_CSI
+typedef MLAN_PACK_START struct _csi_record_ds
+{
+    /** Length in DWORDS, including header */
+    t_u16 Len;
+    /** CSI signature. 0xABCD fixed */
+    t_u16 CSI_Sign;
+    /** User defined HeaderID  */
+    t_u32 CSI_HeaderID;
+    /** Packet info field */
+    t_u16 PKT_info;
+    /** Frame control field for the received packet*/
+    t_u16 FCF;
+    /** Timestamp when packet received */
+    t_u64 TSF;
+    /** Received Packet Destination MAC Address */
+    t_u8 Dst_MAC[6];
+    /** Received Packet Source MAC Address */
+    t_u8 Src_MAC[6];
+    /** RSSI for antenna A */
+    t_u8 Rx_RSSI_A;
+    /** RSSI for antenna B */
+    t_u8 Rx_RSSI_B;
+    /** Noise floor for antenna A */
+    t_u8 Rx_NF_A;
+    /** Noise floor for antenna A */
+    t_u8 Rx_NF_B;
+    /** Rx signal strength above noise floor */
+    t_u8 Rx_SINR;
+    /** Channel */
+    t_u8 channel;
+    /** user defined Chip ID */
+    t_u16 chip_id;
+    /** Reserved */
+    t_u32 rsvd;
+    /** CSI data length in DWORDs */
+    t_u32 CSI_Data_Length;
+    /** Start of CSI data */
+    t_u8 CSI_Data[0];
+    /** At the end of CSI raw data, user defined TailID of 4 bytes*/
+} MLAN_PACK_END csi_record_ds, *pcsi_record_ds;
+#endif
+
+#ifdef PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+/** mlan_callbacks data structure */
+typedef struct _mlan_callbacks
+{
+#if 0
+    /** moal_get_fw_data */
+    mlan_status(*moal_get_fw_data) (IN t_void * pmoal_handle,
+                                    IN t_u32 offset,
+                                    IN t_u32 len, OUT t_u8 * pbuf);
+    /** moal_init_fw_complete */
+    mlan_status(*moal_init_fw_complete) (IN t_void * pmoal_handle,
+                                         IN mlan_status status);
+    /** moal_shutdown_fw_complete */
+    mlan_status(*moal_shutdown_fw_complete) (IN t_void * pmoal_handle,
+                                             IN mlan_status status);
+    /** moal_send_packet_complete */
+    mlan_status(*moal_send_packet_complete) (IN t_void * pmoal_handle,
+                                             IN pmlan_buffer pmbuf,
+                                             IN mlan_status status);
+    /** moal_recv_complete */
+    mlan_status(*moal_recv_complete) (IN t_void * pmoal_handle,
+                                      IN pmlan_buffer pmbuf,
+                                      IN t_u32 port, IN mlan_status status);
+#endif /* 0 */
+    /** moal_recv_packet */
+    mlan_status (*moal_recv_packet)(IN t_void *pmoal_handle, IN pmlan_buffer pmbuf);
+#if 0
+    /** moal_recv_event */
+    mlan_status(*moal_recv_event) (IN t_void * pmoal_handle,
+                                   IN pmlan_event pmevent);
+    /** moal_ioctl_complete */
+    mlan_status(*moal_ioctl_complete) (IN t_void * pmoal_handle,
+                                       IN pmlan_ioctl_req pioctl_req,
+                                       IN mlan_status status);
+    /** moal_alloc_mlan_buffer */
+    mlan_status(*moal_alloc_mlan_buffer) (IN t_void * pmoal_handle,
+                                          IN t_u32 size,
+                                          OUT pmlan_buffer * pmbuf);
+    /** moal_free_mlan_buffer */
+    mlan_status(*moal_free_mlan_buffer) (IN t_void * pmoal_handle,
+                                         IN pmlan_buffer pmbuf);
+    /** moal_write_reg */
+    mlan_status(*moal_write_reg) (IN t_void * pmoal_handle,
+                                  IN t_u32 reg, IN t_u32 data);
+    /** moal_read_reg */
+    mlan_status(*moal_read_reg) (IN t_void * pmoal_handle,
+                                 IN t_u32 reg, OUT t_u32 * data);
+    /** moal_write_data_sync */
+    mlan_status(*moal_write_data_sync) (IN t_void * pmoal_handle,
+                                        IN pmlan_buffer pmbuf,
+                                        IN t_u32 port, IN t_u32 timeout);
+    /** moal_read_data_sync */
+    mlan_status(*moal_read_data_sync) (IN t_void * pmoal_handle,
+                                       IN OUT pmlan_buffer pmbuf,
+                                       IN t_u32 port, IN t_u32 timeout);
+#endif /* 0 */
+    /** moal_malloc */
+    mlan_status (*moal_malloc)(IN t_void *pmoal_handle, IN t_u32 size, IN t_u32 flag, OUT t_u8 **ppbuf);
+    /** moal_mfree */
+    mlan_status (*moal_mfree)(IN t_void *pmoal_handle, IN t_u8 *pbuf);
+#if 0
+    /** moal_memset */
+    t_void *(*moal_memset) (IN t_void * pmoal_handle,
+                            IN t_void * pmem, IN t_u8 byte, IN t_u32 num);
+    /** moal_memcpy */
+    t_void *(*moal_memcpy) (IN t_void * pmoal_handle,
+                            IN t_void * pdest,
+                            IN const t_void * psrc, IN t_u32 num);
+    /** moal_memmove */
+    t_void *(*moal_memmove) (IN t_void * pmoal_handle,
+                             IN t_void * pdest,
+                             IN const t_void * psrc, IN t_u32 num);
+    /** moal_memcmp */
+      t_s32(*moal_memcmp) (IN t_void * pmoal_handle,
+                           IN const t_void * pmem1,
+                           IN const t_void * pmem2, IN t_u32 num);
+    /** moal_udelay */
+      t_void(*moal_udelay) (IN t_void * pmoal_handle, IN t_u32 udelay);
+    /** moal_get_system_time */
+      mlan_status(*moal_get_system_time) (IN t_void * pmoal_handle,
+                                          OUT t_u32 * psec, OUT t_u32 * pusec);
+#endif /* 0 */
+
+    /** moal_memcpy_ext */
+    t_void *(*moal_memcpy_ext)(t_void *pmoal, t_void *pdest, const t_void *psrc, t_u32 num, t_u32 dest_size);
+
+    /** moal_init_timer*/
+    mlan_status (*moal_init_timer)(IN t_void *pmoal_handle,
+                                   OUT t_void *ptimer,
+                                   IN t_void (*callback)(osa_timer_arg_t arg),
+                                   IN t_void *pcontext);
+    /** moal_free_timer */
+    mlan_status (*moal_free_timer)(IN t_void *pmoal_handle, IN t_void *ptimer);
+    /** moal_start_timer*/
+    mlan_status (*moal_start_timer)(IN t_void *pmoal_handle, IN t_void *ptimer, IN bool periodic, IN t_u32 msec);
+    /** moal_reset_timer*/
+    mlan_status (*moal_reset_timer)(IN t_void *pmoal_handle, IN t_void *ptimer);
+    /** moal_stop_timer*/
+    mlan_status (*moal_stop_timer)(IN t_void *pmoal_handle, IN t_void *ptimer);
+    /** moal_init_lock */
+    mlan_status (*moal_init_lock)(IN t_void *pmoal_handle, OUT t_void *plock);
+    /** moal_free_lock */
+    mlan_status (*moal_free_lock)(IN t_void *pmoal_handle, IN t_void *plock);
+    /** moal_spin_lock */
+    mlan_status (*moal_spin_lock)(IN t_void *pmoal_handle, IN t_void *plock);
+    /** moal_spin_unlock */
+    mlan_status (*moal_spin_unlock)(IN t_void *pmoal_handle, IN t_void *plock);
+#if CONFIG_WMM
+    /** moal_init_semaphore */
+    mlan_status (*moal_init_semaphore)(IN t_void *pmoal_handle, IN const char *name, OUT t_void *plock);
+    /** moal_free_semaphore */
+    mlan_status (*moal_free_semaphore)(IN t_void *pmoal_handle, IN t_void *plock);
+    /** moal_semaphore_get */
+    mlan_status (*moal_semaphore_get)(IN t_void *pmoal_handle, IN t_void *plock);
+    /** moal_semaphore_put */
+    mlan_status (*moal_semaphore_put)(IN t_void *pmoal_handle, IN t_void *plock);
+#endif
+#if 0
+    /** moal_print */
+      t_void(*moal_print) (IN t_void * pmoal_handle,
+                           IN t_u32 level, IN t_s8 * pformat, IN ...);
+    /** moal_print_netintf */
+      t_void(*moal_print_netintf) (IN t_void * pmoal_handle,
+                                   IN t_u32 bss_index, IN t_u32 level);
+    /** moal_assert */
+      t_void(*moal_assert) (IN t_void * pmoal_handle, IN t_u32 cond);
+#endif /* 0 */
+} mlan_callbacks, *pmlan_callbacks;
+
+/** Interrupt Mode SDIO */
+#define INT_MODE_SDIO 0
+/** Interrupt Mode GPIO */
+#define INT_MODE_GPIO 1
+
+/** Parameter unchanged, use MLAN default setting */
+#define MLAN_INIT_PARA_UNCHANGED 0
+/** Parameter enabled, override MLAN default setting */
+#define MLAN_INIT_PARA_ENABLED 1
+/** Parameter disabled, override MLAN default setting */
+#define MLAN_INIT_PARA_DISABLED 2U
+
+/** mlan_device data structure */
+typedef struct _mlan_device
+{
+    /** BSS Attributes */
+    mlan_bss_attr bss_attr[MLAN_MAX_BSS_NUM];
+    /** Callbacks */
+    mlan_callbacks callbacks;
+} mlan_device, *pmlan_device;
+
+/** MLAN API function prototype */
+#define MLAN_API
+
+/** Registration */
+MLAN_API mlan_status mlan_register(IN pmlan_device pmdevice, OUT t_void **ppmlan_adapter);
+
+/** Un-registration */
+MLAN_API mlan_status mlan_unregister(IN t_void *pmlan_adapter);
+
+
+/** Firmware Initialization */
+MLAN_API mlan_status mlan_init_fw(IN t_void *pmlan_adapter);
+
+
+#endif /* !_MLAN_DECL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_fw.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_fw.h
new file mode 100644
index 0000000000..30460279e5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_fw.h
@@ -0,0 +1,7855 @@
+/** @file mlan_fw.h
+ *
+ *  @brief This file contains firmware specific defines.
+ *  structures and declares global function prototypes used
+ *  in MLAN module.
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/27/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_FW_H_
+#define _MLAN_FW_H_
+
+/** Interface header length */
+#define INTF_HEADER_LEN                4U
+#define WIFI_HOST_CMD_FIXED_HEADER_LEN 8U
+
+/** Ethernet header */
+typedef struct
+{
+    /** Ethernet header destination address */
+    t_u8 dest_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Ethernet header source address */
+    t_u8 src_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Ethernet header length */
+    t_u16 h803_len;
+
+} Eth803Hdr_t;
+
+/** RFC 1042 header */
+typedef struct
+{
+    /** LLC DSAP */
+    t_u8 llc_dsap;
+    /** LLC SSAP */
+    t_u8 llc_ssap;
+    /** LLC CTRL */
+    t_u8 llc_ctrl;
+    /** SNAP OUI */
+    t_u8 snap_oui[3];
+    /** SNAP type */
+    t_u16 snap_type;
+
+} Rfc1042Hdr_t;
+
+#ifdef PRAGMA_PACK
+#pragma pack(push, 1)
+#endif
+
+/** Rx packet header */
+typedef MLAN_PACK_START struct
+{
+    /** Etherner header */
+    Eth803Hdr_t eth803_hdr;
+    /** RFC 1042 header */
+    Rfc1042Hdr_t rfc1042_hdr;
+
+} MLAN_PACK_END RxPacketHdr_t;
+
+/** Enable Rate ctrl in TxPD */
+#define TXPD_TXRATE_ENABLE MBIT(15)
+
+/** Rates supported in band B */
+#define B_SUPPORTED_RATES 5
+/** Rates supported in band G */
+#define G_SUPPORTED_RATES 9
+/** Rates supported in band BG */
+#define BG_SUPPORTED_RATES 13
+
+/** Setup the number of rates passed in the driver/firmware API */
+#define A_SUPPORTED_RATES 9
+
+/** CapInfo Short Slot Time Disabled */
+// #define SHORT_SLOT_TIME_DISABLED(CapInfo) ((IEEEtypes_CapInfo_t)(CapInfo).short_slot_time = 0)
+#define SHORT_SLOT_TIME_DISABLED(CapInfo) ((CapInfo) &= ~MBIT(10))
+/** CapInfo Short Slot Time Enabled */
+#define SHORT_SLOT_TIME_ENABLED(CapInfo) ((CapInfo) |= MBIT(10))
+
+/** CapInfo Spectrum Mgmt Enabled */
+#define SPECTRUM_MGMT_ENABLED(CapInfo) ((CapInfo) |= MBIT(8))
+/** CapInfo Radio Measurement Disabled */
+#define RADIO_MEASUREMENT_DISABLED(CapInfo) ((CapInfo) &= ~MBIT(12))
+/** CapInfo Radio Measurement Enabled */
+#define RADIO_MEASUREMENT_ENABLED(CapInfo) ((CapInfo) |= MBIT(12))
+
+/** Setup the number of rates passed in the driver/firmware API */
+#define HOSTCMD_SUPPORTED_RATES 14
+
+/** Rates supported in band N */
+#define N_SUPPORTED_RATES 3
+#if CONFIG_5GHz_SUPPORT
+/** All bands (B, G, N) */
+#define ALL_802_11_BANDS (BAND_A | BAND_B | BAND_G | BAND_GN | BAND_AAC | BAND_GAC)
+#else
+#define ALL_802_11_BANDS (BAND_B | BAND_G | BAND_GN | BAND_GAC)
+#endif
+
+/** Firmware multiple bands support */
+#define FW_MULTI_BANDS_SUPPORT (MBIT(8) | MBIT(9) | MBIT(10) | MBIT(11) | MBIT(12) | MBIT(13))
+/** Check if multiple bands support is enabled in firmware */
+#define IS_SUPPORT_MULTI_BANDS(_adapter) ((_adapter)->fw_cap_info & FW_MULTI_BANDS_SUPPORT)
+/** Get default bands of the firmware */
+#define GET_FW_DEFAULT_BANDS(_adapter) \
+    ((((((_adapter)->fw_cap_info & 0x3000) << 1) | ((_adapter)->fw_cap_info & ~0xF000)) >> 8) & ALL_802_11_BANDS)
+
+extern t_u8 SupportedRates_B[B_SUPPORTED_RATES];
+extern t_u8 SupportedRates_G[G_SUPPORTED_RATES];
+extern t_u8 SupportedRates_BG[BG_SUPPORTED_RATES];
+extern t_u8 SupportedRates_A[A_SUPPORTED_RATES];
+extern t_u8 SupportedRates_N[N_SUPPORTED_RATES];
+extern t_u8 AdhocRates_G[G_SUPPORTED_RATES];
+extern t_u8 AdhocRates_B[B_SUPPORTED_RATES];
+extern t_u8 AdhocRates_BG[BG_SUPPORTED_RATES];
+extern t_u8 AdhocRates_A[A_SUPPORTED_RATES];
+
+/** Default auto deep sleep mode */
+#define DEFAULT_AUTO_DS_MODE MTRUE
+/** Default power save mode */
+#define DEFAULT_PS_MODE Wlan802_11PowerModePSP
+
+/** WEP Key index mask */
+#define HostCmd_WEP_KEY_INDEX_MASK 0x3fff
+/** Length of WEP 40 bit key */
+#define WEP_40_BIT_LEN 5U
+/** Length of WEP 104 bit key */
+#define WEP_104_BIT_LEN 13U
+
+/** Key information enabled */
+#define KEY_INFO_ENABLED 0x01
+/** KEY_TYPE_ID */
+typedef enum _KEY_TYPE_ID
+{
+    /** Key type : WEP */
+    KEY_TYPE_ID_WEP = 0,
+    /** Key type : TKIP */
+    KEY_TYPE_ID_TKIP = 1,
+    /** Key type : AES */
+    KEY_TYPE_ID_AES      = 2,
+    KEY_TYPE_ID_WAPI     = 3,
+    KEY_TYPE_ID_AES_CMAC = 4,
+    /** Key type : GCMP */
+    KEY_TYPE_ID_GCMP = 5,
+    /** Key type : GCMP_256 */
+    KEY_TYPE_ID_GCMP_256 = 6,
+    /** Key type : CCMP_256 */
+    KEY_TYPE_ID_CCMP_256 = 7,
+    /** Key type : GMAC_128 */
+    KEY_TYPE_ID_BIP_GMAC_128 = 8,
+    /** Key type : GMAC_256 */
+    KEY_TYPE_ID_BIP_GMAC_256 = 9,
+} KEY_TYPE_ID;
+
+/** KEY_INFO_WEP*/
+typedef enum _KEY_INFO_WEP
+{
+    KEY_INFO_WEP_MCAST   = 0x01,
+    KEY_INFO_WEP_UNICAST = 0x02,
+    KEY_INFO_WEP_ENABLED = 0x04
+} KEY_INFO_WEP;
+
+/** KEY_INFO_TKIP */
+typedef enum _KEY_INFO_TKIP
+{
+    KEY_INFO_TKIP_MCAST   = 0x01,
+    KEY_INFO_TKIP_UNICAST = 0x02,
+    KEY_INFO_TKIP_ENABLED = 0x04
+} KEY_INFO_TKIP;
+
+/** KEY_INFO_AES*/
+typedef enum _KEY_INFO_AES
+{
+    KEY_INFO_AES_MCAST      = 0x01,
+    KEY_INFO_AES_UNICAST    = 0x02,
+    KEY_INFO_AES_ENABLED    = 0x04,
+    KEY_INFO_AES_MCAST_IGTK = 0x400,
+} KEY_INFO_AES;
+
+/** WPA AES key length */
+#define WPA_AES_KEY_LEN 16
+/** WPA TKIP key length */
+#define WPA_TKIP_KEY_LEN 32
+/** WPA AES IGTK key length */
+#define CMAC_AES_KEY_LEN 16
+/** IGTK key length */
+#define WPA_IGTK_KEY_LEN     16
+#define WPA_IGTK_256_KEY_LEN 32
+#define WPA_GCMP_KEY_LEN     32
+#define WPA_CCMP_256_KEY_LEN 32
+
+
+/** Maximum ethernet frame length sans FCS */
+#define MV_ETH_FRAME_LEN 1514
+
+/** Length of SNAP header */
+#define MRVDRV_SNAP_HEADER_LEN 8
+
+/** The number of times to try when waiting for downloaded firmware to
+     become active when multiple interface is present */
+#define MAX_MULTI_INTERFACE_POLL_TRIES 1000
+
+/** The number of times to try when waiting for downloaded firmware to
+     become active. (polling the scratch register). */
+#define MAX_FIRMWARE_POLL_TRIES 100
+
+/** This is for firmware specific length */
+#define EXTRA_LEN 36
+
+/** Buffer size for ethernet Tx packets */
+#define MRVDRV_ETH_TX_PACKET_BUFFER_SIZE (MV_ETH_FRAME_LEN + sizeof(TxPD) + EXTRA_LEN)
+
+/** Buffer size for ethernet Rx packets */
+#define MRVDRV_ETH_RX_PACKET_BUFFER_SIZE (MV_ETH_FRAME_LEN + sizeof(RxPD) + MRVDRV_SNAP_HEADER_LEN + EXTRA_LEN)
+
+/* Macros in interface module */
+
+/** Number of firmware blocks to transfer */
+#define FIRMWARE_TRANSFER_NBLOCK 2
+
+/** Enumeration definition*/
+/** WLAN_802_11_PRIVACY_FILTER */
+typedef enum _WLAN_802_11_PRIVACY_FILTER
+{
+    Wlan802_11PrivFilterAcceptAll,
+    Wlan802_11PrivFilter8021xWEP
+} WLAN_802_11_PRIVACY_FILTER;
+
+/** WLAN_802_11_WEP_STATUS */
+typedef enum _WLAN_802_11_WEP_STATUS
+{
+    Wlan802_11WEPEnabled,
+    Wlan802_11WEPDisabled,
+    Wlan802_11WEPKeyAbsent,
+    Wlan802_11WEPNotSupported
+} WLAN_802_11_WEP_STATUS;
+
+#define RXPD_FLAG_EXTRA_HEADER (1 << 1)
+
+
+/** SNR calculation */
+#define CAL_SNR(RSSI, NF) ((t_s16)((t_s16)(RSSI) - (t_s16)(NF)))
+
+/** 2K buf size */
+#define MLAN_TX_DATA_BUF_SIZE_2K 2048
+
+/** TLV  type ID definition */
+#define PROPRIETARY_TLV_BASE_ID 0x0100U
+
+/** Terminating TLV Type */
+#define MRVL_TERMINATE_TLV_ID 0xffff
+
+/** TLV type : SSID */
+#define TLV_TYPE_SSID 0x0000
+/** TLV type : Rates */
+#define TLV_TYPE_RATES 0x0001
+/** TLV type : PHY FH */
+#define TLV_TYPE_PHY_FH 0x0002
+/** TLV type : PHY DS */
+#define TLV_TYPE_PHY_DS 0x0003
+/** TLV type : CF */
+#define TLV_TYPE_CF 0x0004
+/** TLV type : IBSS */
+#define TLV_TYPE_IBSS 0x0006
+
+/** TLV type : Domain */
+#define TLV_TYPE_DOMAIN 0x0007
+
+/** TLV type : Power constraint */
+#define TLV_TYPE_POWER_CONSTRAINT 0x0020
+
+/** TLV type : Power capability */
+#define TLV_TYPE_POWER_CAPABILITY 0x0021
+
+/** TLV type : Vendor Specific IE */
+#define TLV_TYPE_VENDOR_SPECIFIC_IE 0xdd
+
+/** TLV type : Key material */
+#define TLV_TYPE_KEY_MATERIAL (PROPRIETARY_TLV_BASE_ID + 0x00) // 0x0100
+/** TLV type : Channel list */
+#define TLV_TYPE_CHANLIST (PROPRIETARY_TLV_BASE_ID + 0x01U) // 0x0101
+/** TLV type : Number of probes */
+#define TLV_TYPE_NUMPROBES (PROPRIETARY_TLV_BASE_ID + 0x02) // 0x0102
+/** TLV type : Beacon RSSI low */
+#define TLV_TYPE_RSSI_LOW (PROPRIETARY_TLV_BASE_ID + 0x04U) // 0x0104
+/** TLV type : Beacon SNR low */
+#define TLV_TYPE_SNR_LOW (PROPRIETARY_TLV_BASE_ID + 0x05U) // 0x0105
+/** TLV type : Fail count */
+#define TLV_TYPE_FAILCOUNT (PROPRIETARY_TLV_BASE_ID + 0x06U) // 0x0106
+/** TLV type : BCN miss */
+#define TLV_TYPE_BCNMISS (PROPRIETARY_TLV_BASE_ID + 0x07U) // 0x0107
+/** TLV type : LED behavior */
+#define TLV_TYPE_LEDBEHAVIOR (PROPRIETARY_TLV_BASE_ID + 0x09) // 0x0109
+/** TLV type : Passthrough */
+#define TLV_TYPE_PASSTHROUGH (PROPRIETARY_TLV_BASE_ID + 0x0aU) // 0x010a
+/** TLV type : Power TBL 2.4 Ghz */
+#define TLV_TYPE_POWER_TBL_2_4GHZ (PROPRIETARY_TLV_BASE_ID + 0x0c) // 0x010c
+/** TLV type : Power TBL 5 GHz */
+#define TLV_TYPE_POWER_TBL_5GHZ (PROPRIETARY_TLV_BASE_ID + 0x0d) // 0x010d
+/** TLV type : WMM queue status */
+#define TLV_TYPE_WMMQSTATUS (PROPRIETARY_TLV_BASE_ID + 0x10) // 0x0110
+/** TLV type : Wildcard SSID */
+#define TLV_TYPE_WILDCARDSSID (PROPRIETARY_TLV_BASE_ID + 0x12) // 0x0112
+/** TLV type : TSF timestamp */
+#define TLV_TYPE_TSFTIMESTAMP (PROPRIETARY_TLV_BASE_ID + 0x13) // 0x0113
+/** TLV type : ARP filter */
+#define TLV_TYPE_ARP_FILTER (PROPRIETARY_TLV_BASE_ID + 0x15U) // 0x0115
+/** TLV type : Beacon RSSI high */
+#define TLV_TYPE_RSSI_HIGH (PROPRIETARY_TLV_BASE_ID + 0x16U) // 0x0116
+/** TLV type : Beacon SNR high */
+#define TLV_TYPE_SNR_HIGH (PROPRIETARY_TLV_BASE_ID + 0x17U) // 0x0117
+/** TLV type : Start BG scan later */
+#define TLV_TYPE_STARTBGSCANLATER (PROPRIETARY_TLV_BASE_ID + 0x1e) // 0x011e
+/** TLV type: BG scan repeat count */
+#define TLV_TYPE_REPEAT_COUNT (PROPRIETARY_TLV_BASE_ID + 0xb0) // 0x01b0
+/** TLV type : Authentication type */
+#define TLV_TYPE_AUTH_TYPE (PROPRIETARY_TLV_BASE_ID + 0x1fU) // 0x011f
+/** TLV type : BSSID */
+#define TLV_TYPE_BSSID (PROPRIETARY_TLV_BASE_ID + 0x23U) // 0x0123
+#if CONFIG_SCAN_WITH_RSSIFILTER
+/** TLV type : RSSI Threshold */
+#define TLV_TYPE_RSSI_THRESHOLD (PROPRIETARY_TLV_BASE_ID + 0x151)
+#endif
+
+/** TLV type : Link Quality */
+#define TLV_TYPE_LINK_QUALITY (PROPRIETARY_TLV_BASE_ID + 0x24U) // 0x0124
+
+/** TLV type : Data RSSI low */
+#define TLV_TYPE_RSSI_LOW_DATA (PROPRIETARY_TLV_BASE_ID + 0x26U) // 0x0126
+/** TLV type : Data SNR low */
+#define TLV_TYPE_SNR_LOW_DATA (PROPRIETARY_TLV_BASE_ID + 0x27U) // 0x0127
+/** TLV type : Data RSSI high */
+#define TLV_TYPE_RSSI_HIGH_DATA (PROPRIETARY_TLV_BASE_ID + 0x28U) // 0x0128
+/** TLV type : Data SNR high */
+#define TLV_TYPE_SNR_HIGH_DATA (PROPRIETARY_TLV_BASE_ID + 0x29U) // 0x0129
+
+/** TLV type : Channel band list */
+#define TLV_TYPE_CHANNELBANDLIST (PROPRIETARY_TLV_BASE_ID + 0x2a) // 0x012a
+
+/** TLV type : Passphrase */
+#define TLV_TYPE_PASSPHRASE (PROPRIETARY_TLV_BASE_ID + 0x3cU) // 0x013c
+
+/** TLV type : WPA3 SAE Password */
+#define TLV_TYPE_WPA3_SAE_PASSWORD (PROPRIETARY_TLV_BASE_ID + 0x141U) // 0x0241
+
+/** TLV type : SAE PWE Derivation Mode */
+#define TLV_TYPE_WPA3_SAE_PWE_DERIVATION_MODE (PROPRIETARY_TLV_BASE_ID + 339) /* 0x0100 + 0x153 */
+
+/** TLV type: fw cap info */
+#define TLV_TYPE_FW_CAP_INFO (PROPRIETARY_TLV_BASE_ID + 318)
+
+/** TLV type : Encryption Protocol TLV */
+#define TLV_TYPE_ENCRYPTION_PROTO (PROPRIETARY_TLV_BASE_ID + 0x40) // 0x0140
+/** TLV type : Cipher TLV */
+#define TLV_TYPE_CIPHER (PROPRIETARY_TLV_BASE_ID + 0x42) // 0x0142
+/** TLV type : PMK */
+#define TLV_TYPE_PMK (PROPRIETARY_TLV_BASE_ID + 0x44U) // 0x0144
+
+/** TLV type : BCN miss */
+#define TLV_TYPE_PRE_BCNMISS (PROPRIETARY_TLV_BASE_ID + 0x49U) // 0x0149
+
+/** TLV type: WAPI IE */
+#define TLV_TYPE_WAPI_IE (PROPRIETARY_TLV_BASE_ID + 0x5e) // 0x015e
+
+/** TLV type: MGMT IE */
+#define TLV_TYPE_MGMT_IE (PROPRIETARY_TLV_BASE_ID + 0x69) // 0x0169
+/** TLV type: MAX_MGMT_IE */
+#define TLV_TYPE_MAX_MGMT_IE (PROPRIETARY_TLV_BASE_ID + 0xaa) // 0x01aa
+
+/** TLV type : HT Capabilities */
+#define TLV_TYPE_HT_CAP (PROPRIETARY_TLV_BASE_ID + 0x4a) // 0x014a
+/** TLV type : HT Information */
+#define TLV_TYPE_HT_INFO (PROPRIETARY_TLV_BASE_ID + 0x4b) // 0x014b
+/** TLV type : Secondary Channel Offset */
+#define TLV_SECONDARY_CHANNEL_OFFSET (PROPRIETARY_TLV_BASE_ID + 0x4c) // 0x014c
+/** TLV type : 20/40 BSS Coexistence */
+#define TLV_TYPE_2040BSS_COEXISTENCE (PROPRIETARY_TLV_BASE_ID + 0x4d) // 0x014d
+/** TLV type : Overlapping BSS Scan Parameters */
+#define TLV_TYPE_OVERLAP_BSS_SCAN_PARAM (PROPRIETARY_TLV_BASE_ID + 0x4e) // 0x014e
+/** TLV type : Extended capabilities */
+#define TLV_TYPE_EXTCAP (PROPRIETARY_TLV_BASE_ID + 0x4f) // 0x014f
+/** TLV type : Set of MCS values that STA desires to use within the BSS */
+#define TLV_TYPE_HT_OPERATIONAL_MCS_SET (PROPRIETARY_TLV_BASE_ID + 0x50) // 0x0150
+/** TLV type : Channel TRPC Config */
+#define TLV_TYPE_CHANNEL_TRPC_CONFIG (PROPRIETARY_TLV_BASE_ID + 0x89U) // 0x0189
+/** TLV type : Channel RU PWR Config */
+#define TLV_TYPE_CHANNEL_RU_PWR_CONFIG (PROPRIETARY_TLV_BASE_ID + 0x144U) // 0x0244
+/** TLV type : RXBA_SYNC */
+#define TLV_TYPE_RXBA_SYNC (PROPRIETARY_TLV_BASE_ID + 0x99) // 0x0199
+/** TLV type: key param v2 */
+#define TLV_TYPE_KEY_PARAM_V2 (PROPRIETARY_TLV_BASE_ID + 0x9CU) /* 0x019C */
+#if CONFIG_EXT_SCAN_SUPPORT
+/** TLV type : SCAN channel gap */
+#define TLV_TYPE_SCAN_CHANNEL_GAP (PROPRIETARY_TLV_BASE_ID + 0xc5) /* 0x01c5 */
+#endif
+/** TLV type : BridgeParamSet */
+#define TLV_TYPE_BRIDGE_PARAM (PROPRIETARY_TLV_BASE_ID + 0xe0)
+/** TLV type : AutoLinkParamSet */
+#define TLV_TYPE_AUTOLINK_PARAM (PROPRIETARY_TLV_BASE_ID + 0xe8) /*0x01e8*/
+/** TLV type : Coex parameter config */
+#define TLV_TYPE_EXT_BLE_COEX_CFG (PROPRIETARY_TLV_BASE_ID + 0x12F)
+#if CONFIG_WIFI_CLOCKSYNC
+/** TLV type : GPIO TSF LATCH CONFIG */
+#define TLV_TYPE_GPIO_TSF_LATCH_CONFIG (PROPRIETARY_TLV_BASE_ID + 0x154U)
+/** TLV type : GPIO TSF LATCH REPORT*/
+#define TLV_TYPE_GPIO_TSF_LATCH_REPORT (PROPRIETARY_TLV_BASE_ID + 0x155U)
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+/** TLV ID : Management Frame */
+#define TLV_TYPE_MGMT_FRAME (PROPRIETARY_TLV_BASE_ID + 0x68) /* 0x0168 */
+/** TLV type: management filter  */
+#define TLV_TYPE_MGMT_FRAME_WAKEUP (PROPRIETARY_TLV_BASE_ID + 0x116) /* 0x0216 */
+
+#define TLV_TYPE_PREV_BSSID (PROPRIETARY_TLV_BASE_ID + 330)
+
+#define TLV_TYPE_CSI_MONITOR_CFG (PROPRIETARY_TLV_BASE_ID + 354) /*0x0262*/
+
+/** ADDBA TID mask */
+#define ADDBA_TID_MASK (MBIT(2) | MBIT(3) | MBIT(4) | MBIT(5))
+/** DELBA TID mask */
+#define DELBA_TID_MASK (MBIT(12) | MBIT(13) | MBIT(14) | MBIT(15))
+/** ADDBA Starting Sequence Number Mask */
+#define SSN_MASK 0xfff0
+
+/** Block Ack result status */
+/** Block Ack Result : Success */
+#define BA_RESULT_SUCCESS 0x0U
+/** Block Ack Result : Execution failure */
+#define BA_RESULT_FAILURE 0x1
+/** Block Ack Result : Timeout */
+#define BA_RESULT_TIMEOUT 0x2U
+/** Block Ack Result : Data invalid */
+#define BA_RESULT_DATA_INVALID 0x3
+
+/** Get the baStatus (NOT_SETUP, COMPLETE, IN_PROGRESS)
+ *  in Tx BA stream table */
+#define IS_BASTREAM_SETUP(ptr) ((ptr)->ba_status)
+
+/** An AMPDU/AMSDU could be disallowed for certain TID. 0xff means
+ *  no aggregation is enabled for the assigned TID */
+#define BA_STREAM_NOT_ALLOWED 0xffU
+
+/** Test if 11n is enabled by checking the HTCap IE */
+#define IS_11N_ENABLED(priv)                                               \
+    (((priv)->config_bands & BAND_GN || (priv)->config_bands & BAND_AN) && \
+     ((priv)->curr_bss_params.bss_descriptor.pht_cap != MNULL))
+/** Find out if we are the initiator or not */
+#define INITIATOR_BIT(DelBAParamSet) (((DelBAParamSet)&MBIT(DELBA_INITIATOR_POS)) >> DELBA_INITIATOR_POS)
+
+/** 4K buf size */
+#define MLAN_TX_DATA_BUF_SIZE_4K 4096
+/** 8K buf size */
+#define MLAN_TX_DATA_BUF_SIZE_8K 8192
+#if CONFIG_11AC
+/** 12K buf size */
+#define MLAN_TX_DATA_BUF_SIZE_12K 12288
+#endif
+/** Max Rx AMPDU Size */
+#define MAX_RX_AMPDU_SIZE_64K 0x03
+/** Non green field station */
+#define NON_GREENFIELD_STAS 0x04
+#if CONFIG_AMSDU_IN_AMPDU
+/** Supported A-MSDU size */
+#define MAX_SUPPORT_AMSDU_SIZE 4096
+#endif
+
+/** Max AMSDU size support */
+#define HWSPEC_MAX_AMSDU_SUPP MBIT(31)
+/** Greenfield support */
+#define HWSPEC_GREENFIELD_SUPP MBIT(29)
+/** SM Power Save enable */
+#define CAPINFO_SMPS_ENABLE MBIT(27)
+/** RX STBC support */
+#define HWSPEC_RXSTBC_SUPP MBIT(26)
+/** ShortGI @ 40Mhz support */
+#define HWSPEC_SHORTGI40_SUPP MBIT(24)
+/** ShortGI @ 20Mhz support */
+#define HWSPEC_SHORTGI20_SUPP MBIT(23)
+/** RX LDPC support */
+#define HWSPEC_LDPC_SUPP MBIT(22)
+/** Channel width 40Mhz support */
+#define HWSPEC_CHANBW40_SUPP MBIT(17)
+/** SM Power Save mode */
+#define CAPINFO_SMPS_MODE MBIT(9)
+/** 40Mhz intolarent enable */
+#define CAPINFO_40MHZ_INTOLARENT MBIT(8)
+
+/** Default 11n capability mask for 2.4GHz */
+#if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177)
+#define DEFAULT_11N_CAP_MASK_BG \
+    (HWSPEC_SHORTGI20_SUPP | HWSPEC_RXSTBC_SUPP | HWSPEC_SHORTGI40_SUPP | HWSPEC_CHANBW40_SUPP | HWSPEC_LDPC_SUPP)
+#elif defined(SD8801) || defined(RW610)
+#define DEFAULT_11N_CAP_MASK_BG (HWSPEC_SHORTGI20_SUPP | HWSPEC_RXSTBC_SUPP | HWSPEC_LDPC_SUPP)
+#endif
+/** Default 11n capability mask for 5GHz */
+#define DEFAULT_11N_CAP_MASK_A                                                                      \
+    (HWSPEC_CHANBW40_SUPP | HWSPEC_SHORTGI20_SUPP | HWSPEC_MAX_AMSDU_SUPP | HWSPEC_SHORTGI40_SUPP | \
+     HWSPEC_RXSTBC_SUPP | HWSPEC_LDPC_SUPP)
+
+/** Bits to ignore in hw_dev_cap as these bits are set in get_hw_spec */
+#define IGN_HW_DEV_CAP (CAPINFO_40MHZ_INTOLARENT | (CAPINFO_SMPS_ENABLE | CAPINFO_SMPS_MODE))
+
+/** HW_SPEC FwCapInfo : If FW support RSN Replay Detection */
+#define ISSUPP_RSN_REPLAY_DETECTION(FwCapInfo) (FwCapInfo & MBIT(28))
+
+/** HW_SPEC FwCapInfo */
+#define ISSUPP_11NENABLED(FwCapInfo) ((FwCapInfo)&MBIT(11))
+
+/** HW_SPEC Dot11nDevCap : MAX AMSDU supported */
+#define ISSUPP_MAXAMSDU(Dot11nDevCap) ((Dot11nDevCap)&MBIT(31))
+/** HW_SPEC Dot11nDevCap : Beamforming support */
+#define ISSUPP_BEAMFORMING(Dot11nDevCap) ((Dot11nDevCap)&MBIT(30))
+/** HW_SPEC Dot11nDevCap : Green field support */
+#define ISSUPP_GREENFIELD(Dot11nDevCap) ((Dot11nDevCap)&MBIT(29))
+/** HW_SPEC Dot11nDevCap : AMPDU support */
+#define ISSUPP_AMPDU(Dot11nDevCap) ((Dot11nDevCap)&MBIT(28))
+/** HW_SPEC Dot11nDevCap : MIMO PS support  */
+#define ISSUPP_MIMOPS(Dot11nDevCap) ((Dot11nDevCap)&MBIT(27))
+/** HW_SPEC Dot11nDevCap : Rx STBC support */
+#define ISSUPP_RXSTBC(Dot11nDevCap) ((Dot11nDevCap)&MBIT(26))
+/** HW_SPEC Dot11nDevCap : Tx STBC support */
+#define ISSUPP_TXSTBC(Dot11nDevCap) ((Dot11nDevCap)&MBIT(25))
+/** HW_SPEC Dot11nDevCap : Short GI @ 40Mhz support */
+#define ISSUPP_SHORTGI40(Dot11nDevCap) ((Dot11nDevCap)&MBIT(24))
+/** HW_SPEC Dot11nDevCap : Short GI @ 20Mhz support */
+#define ISSUPP_SHORTGI20(Dot11nDevCap) ((Dot11nDevCap)&MBIT(23))
+/** HW_SPEC Dot11nDevCap : Rx LDPC support */
+#define ISSUPP_RXLDPC(Dot11nDevCap) ((Dot11nDevCap)&MBIT(22))
+/** HW_SPEC Dot11nDevCap : Number of TX BA streams supported */
+#define ISSUPP_GETTXBASTREAM(Dot11nDevCap) ((Dot11nDevCap >> 18) & 0xF)
+/** HW_SPEC Dot11nDevCap : Channel BW support @ 40Mhz  support */
+#define ISSUPP_CHANWIDTH40(Dot11nDevCap) ((Dot11nDevCap)&MBIT(17))
+/** HW_SPEC Dot11nDevCap : Channel BW support @ 20Mhz  support */
+#define ISSUPP_CHANWIDTH20(Dot11nDevCap) ((Dot11nDevCap)&MBIT(16))
+/** HW_SPEC Dot11nDevCap : Channel BW support @ 10Mhz  support */
+#define ISSUPP_CHANWIDTH10(Dot11nDevCap) ((Dot11nDevCap)&MBIT(15))
+/** Dot11nUsrCap : 40Mhz intolarance enabled */
+#define ISENABLED_40MHZ_INTOLARENT(Dot11nDevCap) ((Dot11nDevCap)&MBIT(8))
+/** HW_SPEC Dot11nDevCap : Rx AntennaD support */
+#define ISSUPP_RXANTENNAD(Dot11nDevCap) ((Dot11nDevCap)&MBIT(7))
+/** HW_SPEC Dot11nDevCap : Rx AntennaC support */
+#define ISSUPP_RXANTENNAC(Dot11nDevCap) ((Dot11nDevCap)&MBIT(6))
+/** HW_SPEC Dot11nDevCap : Rx AntennaB support */
+#define ISSUPP_RXANTENNAB(Dot11nDevCap) ((Dot11nDevCap)&MBIT(5))
+/** HW_SPEC Dot11nDevCap : Rx AntennaA support */
+#define ISSUPP_RXANTENNAA(Dot11nDevCap) ((Dot11nDevCap)&MBIT(4))
+/** HW_SPEC Dot11nDevCap : Tx AntennaD support */
+#define ISSUPP_TXANTENNAD(Dot11nDevCap) ((Dot11nDevCap)&MBIT(3))
+/** HW_SPEC Dot11nDevCap : Tx AntennaC support */
+#define ISSUPP_TXANTENNAC(Dot11nDevCap) ((Dot11nDevCap)&MBIT(2))
+/** HW_SPEC Dot11nDevCap : Tx AntennaB support */
+#define ISSUPP_TXANTENNAB(Dot11nDevCap) ((Dot11nDevCap)&MBIT(1))
+/** HW_SPEC Dot11nDevCap : Tx AntennaA support */
+#define ISSUPP_TXANTENNAA(Dot11nDevCap) ((Dot11nDevCap)&MBIT(0))
+
+/** HW_SPEC Dot11nDevCap : Set support of channel bw @ 40Mhz */
+#define SETSUPP_CHANWIDTH40(Dot11nDevCap) ((Dot11nDevCap) |= MBIT(17))
+/** HW_SPEC Dot11nDevCap : Reset support of channel bw @ 40Mhz */
+#define RESETSUPP_CHANWIDTH40(Dot11nDevCap) ((Dot11nDevCap) &= ~MBIT(17))
+
+/** Dot11nUsrCap : Reset 40Mhz intolarance enabled */
+#define RESET_40MHZ_INTOLARENT(Dot11nDevCap) ((Dot11nDevCap) &= ~MBIT(8))
+/** HW_SPEC Dot11nDevCap : Reset Short GI @ 40Mhz support */
+#define RESETSUPP_SHORTGI40(Dot11nDevCap) ((Dot11nDevCap) &= ~MBIT(24))
+
+/** DevMCSSupported : Tx MCS supported */
+#define GET_TXMCSSUPP(DevMCSSupported) ((DevMCSSupported) >> 4)
+/** DevMCSSupported : Rx MCS supported */
+#define GET_RXMCSSUPP(DevMCSSupported) ((DevMCSSupported)&0x0fU)
+/** hw_dev_cap : MPDU DENSITY */
+#define GET_MPDU_DENSITY(hw_dev_cap) (hw_dev_cap & 0x7)
+
+/** GET HTCapInfo : Supported Channel BW */
+#define GETHT_SUPPCHANWIDTH(HTCapInfo) ((HTCapInfo)&MBIT(1))
+/** GET HTCapInfo : Support for Greenfield */
+#define GETHT_GREENFIELD(HTCapInfo) ((HTCapInfo)&MBIT(4))
+/** GET HTCapInfo : Support for Short GI @ 20Mhz */
+#define GETHT_SHORTGI20(HTCapInfo) ((HTCapInfo)&MBIT(5))
+/** GET HTCapInfo : Support for Short GI @ 40Mhz */
+#define GETHT_SHORTGI40(HTCapInfo) ((HTCapInfo)&MBIT(6))
+/** GET HTCapInfo : Support for Tx STBC */
+#define GETHT_TXSTBC(HTCapInfo) ((HTCapInfo)&MBIT(7))
+
+/** GET HTCapInfo : Support for Rx STBC */
+#define GETHT_RXSTBC(HTCapInfo) (((HTCapInfo) >> 8) & 0x03)
+/** GET HTCapInfo : Support for Delayed ACK */
+#define GETHT_DELAYEDBACK(HTCapInfo) ((HTCapInfo)&MBIT(10))
+/** GET HTCapInfo : Support for Max AMSDU */
+#define GETHT_MAXAMSDU(HTCapInfo) ((HTCapInfo)&MBIT(11))
+/** GET HTCapInfo : Support 40Mhz Intolarence */
+#define GETHT_40MHZ_INTOLARANT(HTCapInfo) (HTCapInfo & MBIT(14))
+
+/** SET HTCapInfo : Set support for LDPC coding capability */
+#define SETHT_LDPCCODINGCAP(HTCapInfo) ((HTCapInfo) |= MBIT(0))
+/** SET HTCapInfo : Set support for Channel BW */
+#define SETHT_SUPPCHANWIDTH(HTCapInfo) ((HTCapInfo) |= MBIT(1))
+/** SET HTCapInfo : Set support for Greenfield */
+#define SETHT_GREENFIELD(HTCapInfo) ((HTCapInfo) |= MBIT(4))
+/** SET HTCapInfo : Set support for Short GI @ 20Mhz */
+#define SETHT_SHORTGI20(HTCapInfo) ((HTCapInfo) |= MBIT(5))
+/** SET HTCapInfo : Set support for Short GI @ 40Mhz */
+#define SETHT_SHORTGI40(HTCapInfo) ((HTCapInfo) |= MBIT(6))
+/** SET HTCapInfo : Set support for Tx STBC */
+#define SETHT_TXSTBC(HTCapInfo) ((HTCapInfo) |= MBIT(7))
+/** SET HTCapInfo : Set support for Rx STBC */
+#define SETHT_RXSTBC(HTCapInfo, value) ((HTCapInfo) |= ((value) << 8))
+/** SET HTCapInfo : Set support for delayed block ack */
+#define SETHT_DELAYEDBACK(HTCapInfo) ((HTCapInfo) |= MBIT(10))
+/** SET HTCapInfo : Set support for Max size AMSDU */
+#define SETHT_MAXAMSDU(HTCapInfo) ((HTCapInfo) |= MBIT(11))
+/** SET HTCapInfo : Set support for DSSS/CCK Rates @ 40Mhz */
+#define SETHT_DSSSCCK40(HTCapInfo) ((HTCapInfo) |= MBIT(12))
+/** SET HTCapInfo : Enable 40Mhz Intolarence */
+#define SETHT_40MHZ_INTOLARANT(HTCapInfo) ((HTCapInfo) |= MBIT(14))
+/** SET HTCapInfo : Disable Static SM power save */
+#define SETHT_STATIC_SMPS(HTCapInfo) ((HTCapInfo) |= (MBIT(2) | MBIT(3)))
+
+/** RESET HTCapInfo : Set support for LDPC coding capability */
+#define RESETHT_LDPCCODINGCAP(HTCapInfo) ((HTCapInfo) &= ~MBIT(0))
+/** RESET HTCapInfo : Set support for Channel BW */
+#define RESETHT_SUPPCHANWIDTH(HTCapInfo) ((HTCapInfo) &= ~MBIT(1))
+/** RESET HTCapInfo : Set support for Greenfield */
+#define RESETHT_GREENFIELD(HTCapInfo) ((HTCapInfo) &= ~MBIT(4))
+/** RESET HTCapInfo : Set support for Short GI @ 20Mhz */
+#define RESETHT_SHORTGI20(HTCapInfo) ((HTCapInfo) &= ~MBIT(5))
+/** RESET HTCapInfo : Set support for Short GI @ 40Mhz */
+#define RESETHT_SHORTGI40(HTCapInfo) ((HTCapInfo) &= ~MBIT(6))
+/** RESET HTCapInfo : Set support for Tx STBC */
+#define RESETHT_TXSTBC(HTCapInfo) ((HTCapInfo) &= ~MBIT(7))
+/** RESET HTCapInfo : Set support for Rx STBC */
+#define RESETHT_RXSTBC(HTCapInfo) ((HTCapInfo) &= ~(0x03 << 8))
+/** RESET HTCapInfo : Set support for delayed block ack */
+#define RESETHT_DELAYEDBACK(HTCapInfo) ((HTCapInfo) &= ~MBIT(10))
+/** RESET HTCapInfo : Set support for Max size AMSDU */
+#define RESETHT_MAXAMSDU(HTCapInfo) ((HTCapInfo) &= ~MBIT(11))
+/** RESET HTCapInfo : Set support for Channel BW */
+#define RESETHT_DSSSCCK40(HTCapInfo) ((HTCapInfo) &= ~MBIT(12))
+/** RESET HTCapInfo : Disable 40Mhz Intolarence */
+#define RESETHT_40MHZ_INTOLARANT(HTCapInfo) ((HTCapInfo) &= ~MBIT(14))
+/** RESET HTCapInfo: Enable SM power save */
+#define RESETHT_SM_POWERSAVE(HTCapInfo) ((HTCapInfo) &= ~(MBIT(2) | MBIT(3)))
+/** RESET HTExtCap : Clear RD Responder bit */
+#define RESETHT_EXTCAP_RDG(HTExtCap) ((HTExtCap) &= ~MBIT(11))
+/** SET MCS32 */
+#define SETHT_MCS32(x) (x[4] |= 1U)
+/** Set mcs set defined bit */
+#define SETHT_MCS_SET_DEFINED(x) (x[12] |= 1)
+/** Set the highest Rx data rate */
+#define SETHT_RX_HIGHEST_DT_SUPP(x, y) ((*(t_u16 *)(x + 10)) = y)
+/** AMPDU factor size */
+#define AMPDU_FACTOR_64K 0x03U
+/** Set AMPDU size in A-MPDU paramter field */
+#define SETAMPDU_SIZE(x, y) \
+    do                      \
+    {                       \
+        (x) = (x) & ~0x03U; \
+        (x) |= (y)&0x03U;   \
+    } while (false) /** Set AMPDU spacing in A-MPDU paramter field */
+#define SETAMPDU_SPACING(x, y)    \
+    do                            \
+    {                             \
+        (x) = (x) & ~0x1cU;       \
+        (x) |= ((y)&0x07U) << 2U; \
+    } while (false)
+
+/** RadioType : Support for Band A */
+#define ISSUPP_BANDA(FwCapInfo) (FwCapInfo & MBIT(10))
+/** RadioType : Support for 40Mhz channel BW */
+#define ISALLOWED_CHANWIDTH40(Field2) ((Field2)&MBIT(2))
+/** RadioType : Set support 40Mhz channel */
+#define SET_CHANWIDTH40(Field2) ((Field2) |= MBIT(2))
+/** RadioType : Reset support 40Mhz channel */
+#define RESET_CHANWIDTH40(Field2) ((Field2) &= ~(MBIT(0) | MBIT(1) | MBIT(2)))
+/** RadioType : Get secondary channel */
+#define GET_SECONDARYCHAN(Field2) ((Field2) & (MBIT(0) | MBIT(1)))
+/** RadioType : Set secondary channel */
+#define SET_SECONDARYCHAN(RadioType, SECCHAN) ((RadioType) |= ((SECCHAN) << 4))
+
+/** Locally administered address */
+#define ISLOCALLY_ADMINISTERED_ADDR(mac) (mac & MBIT(1))
+
+/* fw_cap_info bit18 for ecsa support*/
+#define FW_CAPINFO_ECSA MBIT(18)
+
+#if CONFIG_DRIVER_OWE
+/** fw_cap_info bit30 for Embedded OWE Support*/
+#define FW_CAPINFO_EMBEDDED_OWE_SUPPORT MBIT(30)
+/** Check if Embedded OWE is supported by firmware */
+#define IS_FW_SUPPORT_EMBEDDED_OWE(_adapter) (_adapter->fw_cap_info & FW_CAPINFO_EMBEDDED_OWE_SUPPORT)
+#endif
+
+/** FW cap info bit 9: Multi BSSID Support */
+#define FW_CAPINFO_EXT_MULTI_BSSID MBIT(9)
+/** Check if Multi BSSID supported by firmware */
+#define IS_FW_SUPPORT_MULTIBSSID(_adapter) (_adapter->fw_cap_ext & FW_CAPINFO_EXT_MULTI_BSSID)
+
+/** FW cap info bit 16: Tx mgmt pkt with command*/
+#if defined(SD8987)
+#define FW_CAPINFO_EXT_CMD_TX_DATA          MBIT(29)
+#define IS_FW_SUPPORT_CMD_TX_DATA(_adapter) (_adapter->fw_cap_info & FW_CAPINFO_EXT_CMD_TX_DATA)
+#elif defined(SD9177)
+#define FW_CAPINFO_EXT_CMD_TX_DATA          MBIT(16)
+/** Check if transmit mgmt pkt through command supported by firmware */
+#define IS_FW_SUPPORT_CMD_TX_DATA(_adapter) (_adapter->fw_cap_ext & FW_CAPINFO_EXT_CMD_TX_DATA)
+#endif
+
+/** LLC/SNAP header len   */
+#define LLC_SNAP_LEN 8
+/** Ethernet header len */
+#define ETH_HDR_LEN 14
+
+/** bandwidth following HTCAP */
+#define BW_FOLLOW_HTCAP 0
+/** bandwidth following VHTCAP */
+#define BW_FOLLOW_VHTCAP 1U
+
+/** HW_SPEC FwCapInfo */
+#define HWSPEC_11ACSGI80_SUPP  MBIT(5)
+#define HWSPEC_11ACRXSTBC_SUPP MBIT(8)
+
+#define ISSUPP_11ACENABLED(FwCapInfo) ((FwCapInfo) & (MBIT(12) | MBIT(13)))
+
+#define ISSUPP_11AC2GENABLED(FwCapInfo) ((FwCapInfo)&MBIT(12))
+#define ISSUPP_11AC5GENABLED(FwCapInfo) ((FwCapInfo)&MBIT(13))
+
+/** HW_SPEC FwCapExt: no 5G enabled */
+#define ISSUPP_NO5G(FwCapExt) (FwCapExt & MBIT(17))
+
+/** HW_SPEC Dot11acDevCap : HTC-VHT supported */
+#define ISSUPP_11ACVHTHTCVHT(Dot11acDevCap) (Dot11acDevCap & MBIT(22))
+/** HW_SPEC Dot11acDevCap : VHT TXOP PS support */
+#define ISSUPP_11ACVHTTXOPPS(Dot11acDevCap) (Dot11acDevCap & MBIT(21))
+/** HW_SPEC Dot11acDevCap : MU RX beamformee support */
+#define ISSUPP_11ACMURXBEAMFORMEE(Dot11acDevCap) (Dot11acDevCap & MBIT(20))
+/** HW_SPEC Dot11acDevCap : MU TX beamformee support */
+#define ISSUPP_11ACMUTXBEAMFORMEE(Dot11acDevCap) (Dot11acDevCap & MBIT(19))
+/** HW_SPEC Dot11acDevCap : SU Beamformee support */
+#define ISSUPP_11ACSUBEAMFORMEE(Dot11acDevCap) (Dot11acDevCap & MBIT(12))
+/** HW_SPEC Dot11acDevCap : SU Beamformer support */
+#define ISSUPP_11ACSUBEAMFORMER(Dot11acDevCap) (Dot11acDevCap & MBIT(11))
+/** HW_SPEC Dot11acDevCap : Rx STBC support */
+#define ISSUPP_11ACRXSTBC(Dot11acDevCap) (Dot11acDevCap & MBIT(8))
+/** HW_SPEC Dot11acDevCap : Tx STBC support */
+#define ISSUPP_11ACTXSTBC(Dot11acDevCap) (Dot11acDevCap & MBIT(7))
+/** HW_SPEC Dot11acDevCap : Short GI support for 160MHz BW */
+#define ISSUPP_11ACSGI160(Dot11acDevCap) (Dot11acDevCap & MBIT(6))
+/** HW_SPEC Dot11acDevCap : Short GI support for 80MHz BW */
+#define ISSUPP_11ACSGI80(Dot11acDevCap) (Dot11acDevCap & MBIT(5))
+/** HW_SPEC Dot11acDevCap : LDPC coding support */
+#define ISSUPP_11ACLDPC(Dot11acDevCap) (Dot11acDevCap & MBIT(4))
+/** HW_SPEC Dot11acDevCap : Channel BW 20/40/80/160/80+80 MHz support */
+#define ISSUPP_11ACBW8080(Dot11acDevCap) (Dot11acDevCap & MBIT(3))
+/** HW_SPEC Dot11acDevCap : Channel BW 20/40/80/160 MHz support */
+#define ISSUPP_11ACBW160(Dot11acDevCap) (Dot11acDevCap & MBIT(2))
+
+/** Set VHT Cap Info: Max MPDU length */
+#define SET_VHTCAP_MAXMPDULEN(VHTCapInfo, value) ((VHTCapInfo) |= (value & 0x03U))
+/** SET VHT CapInfo:  Supported Channel Width SET (2 bits)*/
+#define SET_VHTCAP_CHWDSET(VHTCapInfo, value) ((VHTCapInfo) |= ((value & 0x3U) << 2))
+/** SET VHT CapInfo:  Rx STBC (3 bits) */
+#define SET_VHTCAP_RXSTBC(VHTCapInfo, value) ((VHTCapInfo) |= ((value & 0x7U) << 8))
+/** SET VHT CapInfo:  Commpressed Steering Num of BFer Ant Supported (3 bits) */
+#define SET_VHTCAP_SNBFERANT(VHTCapInfo, value) ((VHTCapInfo) |= ((value & 0x7U) << 13))
+/** SET VHT CapInfo:  Num of Sounding Dimensions (3 bits) */
+#define SET_VHTCAP_NUMSNDDM(VHTCapInfo, value) ((VHTCapInfo) |= ((value & 0x7U) << 16))
+/** SET VHT CapInfo:  Max AMPDU Length Exponent (3 bits) */
+#define SET_VHTCAP_MAXAMPDULENEXP(VHTCapInfo, value) ((VHTCapInfo) |= ((value & 0x7U) << 23))
+/** SET VHT CapInfo:  VHT Link Adaptation Capable (2 bits) */
+#define SET_VHTCAP_LINKADPCAP(VHTCapInfo, value) ((VHTCapInfo) |= ((value & 0x3U) << 26))
+
+/** HW_SPEC Dot11acDevCap : ReSet VHT Link Adapation Capable */
+#define RESET_11ACVHTLINKCAPA(Dot11acDevCap, value) ((Dot11acDevCap) &= ~(0x03))
+/** HW_SPEC Dot11acDevCap : ReSet Maximum AMPDU Length Exponent */
+#define RESET_11ACAMPDULENEXP(Dot11acDevCap, value) ((Dot11acDevCap) &= ~(0x07))
+/** HW_SPEC Dot11acDevCap : ReSet support of HTC-VHT */
+#define RESET_11ACVHTHTCVHT(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(22))
+/** HW_SPEC Dot11acDevCap : ReSet support of VHT TXOP PS */
+#define RESET_11ACVHTTXOPPS(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(21))
+/** HW_SPEC Dot11acDevCap : ReSet support of MU RX beamformee */
+#define RESET_11ACMURXBEAMFORMEE(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(20))
+/** HW_SPEC Dot11acDevCap : ReSet support of MU TX beamformee */
+#define RESET_11ACMUTXBEAMFORMEE(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(19))
+/** HW_SPEC Dot11acDevCap : ReSet Number of Sounding Dimensions */
+#define RESET_11ACSOUNDINGNUM(Dot11acDevCap) ((Dot11acDevCap) &= ~((0x07) << 16))
+/** HW_SPEC Dot11acDevCap : ReSet Compressed Steering Number
+ * of Beamformer Antenna */
+#define RESET_11ACBFANTNUM(Dot11acDevCap) ((Dot11acDevCap) &= ~((0x07) << 13))
+/** HW_SPEC Dot11acDevCap : ReSet support of SU Beamformee */
+#define RESET_11ACSUBEAMFORMEE(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(12))
+/** HW_SPEC Dot11acDevCap : ReSet support of SU Beamformer */
+#define RESET_11ACSUBEAMFORMER(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(11))
+/** HW_SPEC Dot11acDevCap : ReSet support of Rx STBC */
+#define RESET_11ACRXSTBC(Dot11acDevCap) ((Dot11acDevCap) &= ~((0x07) << 8))
+/** HW_SPEC Dot11acDevCap : ReSet support of Tx STBC */
+#define RESET_11ACTXSTBC(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(7))
+/** HW_SPEC Dot11acDevCap : ReSet support of Short GI support for 160MHz BW */
+#define RESET_11ACSGI160(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(6))
+/** HW_SPEC Dot11acDevCap : ReSet support of Short GI support for 80MHz BW */
+#define RESET_11ACSGI80(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(5))
+/** HW_SPEC Dot11acDevCap : ReSet support of LDPC coding */
+#define RESET_11ACLDPC(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(4))
+/** HW_SPEC Dot11acDevCap : ReSet support of
+ * Channel BW 20/40/80/160/80+80 MHz */
+#define RESET_11ACBW8080(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(3))
+/** HW_SPEC Dot11acDevCap : ReSet support of
+ * Channel BW 20/40/80/160 MHz */
+#define RESET_11ACBW160(Dot11acDevCap) ((Dot11acDevCap) &= ~MBIT(2))
+/** HW_SPEC Dot11acDevCap : ReSet Max MPDU length */
+#define RESET_11ACMAXMPDULEN(Dot11acDevCap) ((Dot11acDevCap) &= ~(0x03))
+
+/** Default 11ac capability mask for 2.4GHz */
+#define DEFAULT_11AC_CAP_MASK_BG (HWSPEC_11ACSGI80_SUPP | HWSPEC_11ACRXSTBC_SUPP)
+/** Default 11ac capability mask for 5GHz */
+#define DEFAULT_11AC_CAP_MASK_A (HWSPEC_11ACSGI80_SUPP | HWSPEC_11ACRXSTBC_SUPP)
+/** GET VHT CapInfo : MAX MPDU Length */
+#define GET_VHTCAP_MAXMPDULEN(VHTCapInfo) ((VHTCapInfo)&0x3U)
+/** GET VHT CapInfo:  Supported Channel Width SET (2 bits)*/
+#define GET_VHTCAP_CHWDSET(VHTCapInfo) (((VHTCapInfo) >> 2) & 0x3U)
+/** GET VHT CapInfo:  Rx STBC (3 bits) */
+#define GET_VHTCAP_RXSTBC(VHTCapInfo) (((VHTCapInfo) >> 8) & 0x7U)
+/** GET VHT CapInfo:  Compressed Steering Num of BFer Ant Supported (3 bits) */
+#define GET_VHTCAP_SNBFERANT(VHTCapInfo) (((VHTCapInfo) >> 13) & 0x7U)
+/** GET VHT CapInfo:  Num of Sounding Dimensions (3 bits) */
+#define GET_VHTCAP_NUMSNDDM(VHTCapInfo) (((VHTCapInfo) >> 16) & 0x7U)
+/** GET VHT CapInfo:  Max AMPDU Length Exponent (3 bits) */
+#define GET_VHTCAP_MAXAMPDULENEXP(VHTCapInfo) (((VHTCapInfo) >> 23) & 0x7U)
+/** GET VHT CapInfo:  VHT Link Adaptation Capable (2 bits) */
+#define GET_VHTCAP_LINKADPCAP(VHTCapInfo) (((VHTCapInfo) >> 26) & 0x3U)
+/**SET OPERATING MODE:Channel Width:80M*/
+#define SET_OPER_MODE_80M(oper_mode) ((oper_mode) = (t_u8)((oper_mode) & ~MBIT(0)) | MBIT(1))
+/**SET OPERATING MODE:Channel Width:40M*/
+#define SET_OPER_MODE_40M(oper_mode) ((oper_mode) = (t_u8)((oper_mode) & ~MBIT(1)) | MBIT(0))
+/**SET OPERATING MODE:Channel Width:20M*/
+#define SET_OPER_MODE_20M(oper_mode) ((oper_mode) &= (t_u8)(~(0x03U)))
+#define IS_OPER_MODE_20M(oper_mode)  (((oper_mode) & (MBIT(0) | MBIT(1))) == 0U)
+/**SET OPERATING MODE:Rx NSS:2*/
+#define SET_OPER_MODE_2NSS(oper_mode) ((oper_mode) = ((oper_mode) & ~(MBIT(5) | MBIT(6))) | MBIT(4))
+/**SET OPERATING MODE:Rx NSS:1*/
+#define SET_OPER_MODE_1NSS(oper_mode) ((oper_mode) &= ~(MBIT(4) | MBIT(5) | MBIT(6)))
+
+#define NO_NSS_SUPPORT                0x03U
+#define GET_VHTMCS(MCSMapSet)         ((MCSMapSet)&0xFFFFU)
+#define GET_VHTNSSMCS(MCSMapSet, nss) (((MCSMapSet) >> (2U * ((nss)-1U))) & 0x3U)
+#define RET_VHTNSSMCS(MCSMapSet, nss) (((MCSMapSet) >> (2U * ((nss)-1))) & 0x3)
+#define SET_VHTNSSMCS(MCSMapSet, nss, value) \
+    ((MCSMapSet) |= (t_u32)(((t_u32)(value)&0x0003U) << (t_u32)(2U * ((t_u32)(nss)-1U))))
+
+/** DevMCSSupported : Tx MCS supported */
+#define GET_DEVTXMCSMAP(DevMCSMap)             ((DevMCSMap) >> 16)
+#define GET_DEVNSSTXMCS(DevMCSMap, nss)        (((DevMCSMap) >> (2U * ((nss)-1U) + 16U)) & 0x3U)
+#define SET_DEVNSSTXMCS(DevMCSMap, nss, value) ((DevMCSMap) |= ((value)&0x3) << (2 * ((nss)-1) + 16))
+#define RESET_DEVTXMCSMAP(DevMCSMap)           ((DevMCSMap) &= 0xFFFFU)
+/** DevMCSSupported : Rx MCS supported */
+#define GET_DEVRXMCSMAP(DevMCSMap)             ((DevMCSMap)&0xFFFFU)
+#define GET_DEVNSSRXMCS(DevMCSMap, nss)        (((DevMCSMap) >> (2U * ((nss)-1U))) & 0x3U)
+#define SET_DEVNSSRXMCS(DevMCSMap, nss, value) ((DevMCSMap) |= ((value)&0x3) << (2 * ((nss)-1)))
+#define RESET_DEVRXMCSMAP(DevMCSMap)           ((DevMCSMap) &= 0xFFFF0000U)
+
+
+/** ExtCap : Set support Multi BSSID */
+#define SET_EXTCAP_MULTI_BSSID(ext_cap) (ext_cap.MultipleBSSID = 1)
+
+#if CONFIG_11AX
+/** FW cap info bit 7 11AX */
+#define FW_CAPINFO_EXT_802_11AX MBIT(7)
+
+/* HE MAC Capabilities Information field BIT 1 for TWT Req */
+#define HE_MAC_CAP_TWT_REQ_SUPPORT MBIT(1)
+/* HE MAC Capabilities Information field BIT 2 for TWT Resp*/
+#define HE_MAC_CAP_TWT_RESP_SUPPORT MBIT(2)
+/** Check if 11AX is supported by firmware */
+#define IS_FW_SUPPORT_11AX(_adapter) (_adapter->fw_cap_ext & FW_CAPINFO_EXT_802_11AX)
+/** ExtCap : Support for TWT RESP */
+#define ISSUPP_EXTCAP_EXT_TWT_RESP(ext_cap) (ext_cap.TWTResp)
+/** ExtCap : Set support Ext TWT_REQ */
+#define SET_EXTCAP_TWT_REQ(ext_cap) (ext_cap.TWTReq = 1)
+/** ExtCap : ReSet support Ext TWT REQ */
+#define RESET_EXTCAP_TWT_REQ(ext_cap) (ext_cap.TWTReq = 0)
+
+typedef MLAN_PACK_START struct _MrvlIEtypes_He_cap_t
+{
+    /** Header type */
+    t_u16 type;
+    /** Header length */
+    t_u16 len;
+    /** Element id extension */
+    t_u8 ext_id;
+    /** he mac capability info */
+    t_u8 he_mac_cap[6];
+    /** he phy capability info */
+    t_u8 he_phy_cap[11];
+    /** he txrx mcs support , size would be 4 or 8 or 12 */
+    t_u8 he_txrx_mcs_support[4];
+    /** 160Mhz tx rx mcs support*/
+    t_u8 he160_txrx_mcs_support[4];
+    /** 80+80 Mhz tx rx mcs suport */
+    t_u8 he8080_txrx_mcs_support[4];
+    /** PPE Thresholds (optional) */
+    t_u8 val[20];
+} MLAN_PACK_END MrvlIEtypes_He_cap_t, *pMrvlIEtypes_he_cap_t;
+
+typedef MLAN_PACK_START struct _MrvlIEtypes_Extension_t
+{
+    /** Header type */
+    t_u16 type;
+    /** Header length */
+    t_u16 len;
+    /** Element id extension */
+    t_u8 ext_id;
+    /** payload */
+    t_u8 data[];
+} MLAN_PACK_END MrvlIEtypes_Extension_t, *pMrvlIEtypes_Extension_t;
+#endif
+
+/** FW cap info TLV */
+typedef MLAN_PACK_START struct _MrvlIEtypes_fw_cap_info_t
+{
+    /** Header type */
+    t_u16 type;
+    /** Header length */
+    t_u16 len;
+    /** Fw cap info bitmap */
+    t_u32 fw_cap_info;
+    /** Extended fw cap info bitmap */
+    t_u32 fw_cap_ext;
+} MLAN_PACK_END MrvlIEtypes_fw_cap_info_t, *pMrvlIEtypes_fw_cap_info_t;
+
+/** TLV type : Rate scope */
+#define TLV_TYPE_RATE_DROP_PATTERN (PROPRIETARY_TLV_BASE_ID + 0x51U) // 0x0151
+/** TLV type : Rate drop pattern */
+#define TLV_TYPE_RATE_DROP_CONTROL (PROPRIETARY_TLV_BASE_ID + 0x52) // 0x0152
+/** TLV type : Rate scope */
+#define TLV_TYPE_RATE_SCOPE (PROPRIETARY_TLV_BASE_ID + 0x53U) // 0x0153
+
+/** TLV type : Power group */
+#define TLV_TYPE_POWER_GROUP (PROPRIETARY_TLV_BASE_ID + 0x54U) // 0x0154
+
+/** Modulation class for DSSS Rates */
+#define MOD_CLASS_HR_DSSS 0x03
+/** Modulation class for OFDM Rates */
+#define MOD_CLASS_OFDM 0x07U
+/** Modulation class for HT Rates */
+#define MOD_CLASS_HT 0x08
+/** HT bandwidth 20 MHz */
+#define HT_BW_20 0
+/** HT bandwidth 40 MHz */
+#define HT_BW_40 1U
+/** TLV type : TX RATE CFG, rename from TLV_TYPE_GI_LTF_SIZE to include CMD and
+ * HE ER SU settings to this tlv */
+#define TLV_TYPE_TX_RATE_CFG (PROPRIETARY_TLV_BASE_ID + 319) /* 0x023f */
+
+#if (CONFIG_EXT_SCAN_SUPPORT)
+/** TLV type : Scan Response */
+#define TLV_TYPE_BSS_SCAN_RSP (PROPRIETARY_TLV_BASE_ID + 0x56) // 0x0156
+/** TLV type : Scan Response Stats */
+#define TLV_TYPE_BSS_SCAN_INFO (PROPRIETARY_TLV_BASE_ID + 0x57) // 0x0157
+#endif
+
+/** TLV type : 11h Basic Rpt */
+#define TLV_TYPE_CHANRPT_11H_BASIC (PROPRIETARY_TLV_BASE_ID + 0x5b) // 0x015b
+
+/** TLV type : Action frame */
+#define TLV_TYPE_IEEE_ACTION_FRAME (PROPRIETARY_TLV_BASE_ID + 0x8c) // 0x018c
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+#define FTM_SESSION_CFG_LCI_TLV_ID            (PROPRIETARY_TLV_BASE_ID + 270) /* 0x20e */
+#define FTM_SESSION_CFG_LOCATION_CIVIC_TLV_ID (PROPRIETARY_TLV_BASE_ID + 271) /* 0x20f */
+#define FTM_SESSION_CFG_INITATOR_TLV_ID       (PROPRIETARY_TLV_BASE_ID + 273) /* 0x211 */
+#define FTM_NTB_RANGING_CFG_TLV_ID            (PROPRIETARY_TLV_BASE_ID + 343) /* 0x257 */
+#define FTM_TB_RANGING_CFG_TLV_ID             (PROPRIETARY_TLV_BASE_ID + 344) /* 0x258 */
+
+#if CONFIG_WLS_CSI_PROC
+#define WLS_CSI_DATA_LEN_DW 181
+#define WLS_CSI_DATA_LEN    (WLS_CSI_DATA_LEN_DW * sizeof(uint32_t))
+#endif
+
+#endif
+
+#if CONFIG_SCAN_CHANNEL_GAP
+/** TLV type : SCAN channel gap */
+#define TLV_TYPE_SCAN_CHANNEL_GAP              \
+    (PROPRIETARY_TLV_BASE_ID + 0xc5) /* 0x01c5 \
+                                      */
+/** TLV type : Channel statistics */
+#define TLV_TYPE_CHANNEL_STATS (PROPRIETARY_TLV_BASE_ID + 0xc6) /* 0x01c6 */
+#endif
+
+/** Firmware Host Command ID Constants */
+/** Host Command ID : Get hardware specifications */
+#define HostCmd_CMD_GET_HW_SPEC 0x0003
+/** Host Command ID : 802.11 scan */
+#define HostCmd_CMD_802_11_SCAN 0x0006
+/** Host Command ID : 802.11 get log */
+#define HostCmd_CMD_802_11_GET_LOG 0x000b
+/** Host Command ID : MAC multicast address */
+#define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010
+/** Host Command ID : 802.11 EEPROM access */
+#define HostCmd_CMD_802_11_EEPROM_ACCESS 0x0059
+/** Host Command ID : 802.11 associate */
+#define HostCmd_CMD_802_11_ASSOCIATE 0x0012
+
+/** Host Command ID : 802.11 SNMP MIB */
+#define HostCmd_CMD_802_11_SNMP_MIB 0x0016
+/** Host Command ID : MAC register access */
+#define HostCmd_CMD_MAC_REG_ACCESS 0x0019
+/** Host Command ID : BBP register access */
+#define HostCmd_CMD_BBP_REG_ACCESS 0x001a
+/** Host Command ID : RF register access */
+#define HostCmd_CMD_RF_REG_ACCESS 0x001b
+
+/** Host Command ID : 802.11 radio control */
+#define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c
+/** Host Command ID : 802.11 RF channel */
+#define HostCmd_CMD_802_11_RF_CHANNEL 0x001d
+/** Host Command ID : 802.11 RF Tx power */
+#define HostCmd_CMD_802_11_RF_TX_POWER 0x001e
+
+/** Host Command ID : 802.11 RF antenna */
+#define HostCmd_CMD_802_11_RF_ANTENNA 0x0020
+
+/** Host Command ID : 802.11 deauthenticate */
+#define HostCmd_CMD_802_11_DEAUTHENTICATE 0x0024
+/** Host Command ID : MAC control */
+#define HostCmd_CMD_MAC_CONTROL 0x0028
+/** Host Command ID : 802.11 Ad-Hoc start */
+#define HostCmd_CMD_802_11_AD_HOC_START 0x002b
+/** Host Command ID : 802.11 Ad-Hoc join */
+#define HostCmd_CMD_802_11_AD_HOC_JOIN 0x002c
+
+/** Host Command ID : 802.11 key material */
+#define HostCmd_CMD_802_11_KEY_MATERIAL 0x005e
+
+/** Host Command ID : 802.11 Ad-Hoc stop */
+#define HostCmd_CMD_802_11_AD_HOC_STOP 0x0040
+
+/** Host Command ID : 802.22 MAC address */
+#define HostCmd_CMD_802_11_MAC_ADDRESS 0x004D
+
+/** Host Command ID : WMM Traffic Stream Status */
+#define HostCmd_CMD_WMM_TS_STATUS 0x005d
+
+/** Host Command ID : 802.11 D domain information */
+#define HostCmd_CMD_802_11D_DOMAIN_INFO 0x005b
+
+/** Host Command ID : 802.11 TPC information */
+#define HostCmd_CMD_802_11_TPC_INFO 0x005f
+/** Host Command ID : 802.11 TPC adapt req */
+#define HostCmd_CMD_802_11_TPC_ADAPT_REQ 0x0060
+/** Host Command ID : 802.11 channel SW ann */
+#define HostCmd_CMD_802_11_CHAN_SW_ANN 0x0061
+
+/** Host Command ID : Measurement request */
+#define HostCmd_CMD_MEASUREMENT_REQUEST 0x0062
+/** Host Command ID : Measurement report */
+#define HostCmd_CMD_MEASUREMENT_REPORT 0x0063
+
+/** Host Command ID : 802.11 sleep parameters */
+#define HostCmd_CMD_802_11_SLEEP_PARAMS 0x0066
+
+/** Host Command ID : 802.11 sleep period */
+#define HostCmd_CMD_802_11_SLEEP_PERIOD 0x0068
+
+/** Host Command ID: 802.11 BG scan config */
+#define HostCmd_CMD_802_11_BG_SCAN_CONFIG 0x006b
+/** Host Command ID : 802.11 BG scan query */
+#define HostCmd_CMD_802_11_BG_SCAN_QUERY 0x006cU
+
+/** Host Command ID : WMM ADDTS req */
+#define HostCmd_CMD_WMM_ADDTS_REQ 0x006E
+/** Host Command ID : WMM DELTS req */
+#define HostCmd_CMD_WMM_DELTS_REQ 0x006F
+/** Host Command ID : WMM queue configuration */
+#define HostCmd_CMD_WMM_QUEUE_CONFIG 0x0070
+/** Host Command ID : 802.11 get status */
+#define HostCmd_CMD_WMM_GET_STATUS 0x0071
+
+/** Host Command ID : 802.11 subscribe event */
+#define HostCmd_CMD_802_11_SUBSCRIBE_EVENT 0x0075
+
+#if CONFIG_WIFI_EU_CRYPTO
+/** Host Command ID : EU Test */
+#define HostCmd_CMD_EU_CRYPTO 0x0078
+#endif
+
+/** Host Command ID : 802.11 NET MONITOR*/
+#define HostCmd_CMD_802_11_NET_MONITOR 0x0102
+
+/** Host Command ID : 802.11 Tx rate query */
+#define HostCmd_CMD_802_11_TX_RATE_QUERY 0x007f
+
+/** Host Command ID :Get timestamp value */
+#define HostCmd_CMD_GET_TSF 0x0080
+
+/** Host Command ID : WMM queue stats */
+#define HostCmd_CMD_WMM_QUEUE_STATS 0x0081
+
+/** Host Command ID : KEEP ALIVE command */
+#define HostCmd_CMD_AUTO_TX 0x0082
+
+/** Host Command ID : 802.11 IBSS coalescing status */
+#define HostCmd_CMD_802_11_IBSS_COALESCING_STATUS 0x0083
+
+/** Host Command ID : Memory access */
+#define HostCmd_CMD_MEM_ACCESS 0x0086
+
+/** Host Command ID : SDIO GPIO interrupt configuration */
+#define HostCmd_CMD_SDIO_GPIO_INT_CONFIG 0x0088
+
+#if CONFIG_RF_TEST_MODE
+/** Host Command ID : Mfg command */
+#define HostCmd_CMD_MFG_COMMAND 0x0089
+#endif
+
+/** Host Command ID : Inactivity timeout ext */
+#define HostCmd_CMD_INACTIVITY_TIMEOUT_EXT 0x008a
+
+/** Host Command ID : DBGS configuration */
+#define HostCmd_CMD_DBGS_CFG 0x008b
+/** Host Command ID : Get memory */
+#define HostCmd_CMD_GET_MEM 0x008c
+
+#if (CONFIG_WIFI_TX_PER_TRACK) || (CONFIG_TX_RX_HISTOGRAM)
+/** Host Command ID: TX_RX_PKT_STATS */
+#define HostCmd_CMD_TX_RX_PKT_STATS 0x008d
+#endif
+
+/** Host Command ID : Cal data dnld */
+#define HostCmd_CMD_CFG_DATA 0x008f
+
+/** Host Command ID : SDIO pull control */
+#define HostCmd_CMD_SDIO_PULL_CTRL 0x0093
+
+/** Host Command ID : ECL system clock configuration */
+#define HostCmd_CMD_ECL_SYSTEM_CLOCK_CONFIG 0x0094
+
+/** Host Command ID : Extended version */
+#define HostCmd_CMD_VERSION_EXT 0x0097
+
+/** Host Command ID : MEF configuration */
+#define HostCmd_CMD_MEF_CFG 0x009a
+
+/** Host Command ID : 802.11 RSSI INFO*/
+#define HostCmd_CMD_RSSI_INFO 0x00a4
+
+/** Host Command ID : Function initialization */
+#define HostCmd_CMD_FUNC_INIT 0x00a9U
+/** Host Command ID : Function shutdown */
+#define HostCmd_CMD_FUNC_SHUTDOWN 0x00aa
+
+/** Host Command ID : Channel report request */
+#define HostCmd_CMD_CHAN_REPORT_REQUEST 0x00dd
+
+/** Host Command ID: SUPPLICANT_PMK */
+#define HostCmd_CMD_SUPPLICANT_PMK 0x00c4
+/** Host Command ID: SUPPLICANT_PROFILE */
+#define HostCmd_CMD_SUPPLICANT_PROFILE 0x00c5
+
+/** Host Command ID : Add Block Ack Request */
+#define HostCmd_CMD_11N_ADDBA_REQ 0x00ce
+/** Host Command ID : Delete a Block Ack Request */
+#define HostCmd_CMD_11N_CFG 0x00cd
+/** Host Command ID : Add Block Ack Response */
+#define HostCmd_CMD_11N_ADDBA_RSP 0x00cf
+/** Host Command ID : Delete a Block Ack Request */
+#define HostCmd_CMD_11N_DELBA 0x00d0
+/** Host Command ID: Configure Tx Buf size */
+#define HostCmd_CMD_RECONFIGURE_TX_BUFF 0x00d9
+/** Host Command ID: AMSDU Aggr Ctrl */
+#define HostCmd_CMD_AMSDU_AGGR_CTRL 0x00df
+
+/** Host Command ID : 802.11 TX power configuration */
+#define HostCmd_CMD_TXPWR_CFG 0x00d1
+
+/** Host Command ID : Soft Reset */
+#define HostCmd_CMD_SOFT_RESET 0x00d5
+
+/** Host Command ID : 802.11 b/g/n rate configration */
+#define HostCmd_CMD_TX_RATE_CFG 0x00d6
+
+/** Host Command ID : Coexistence mode config */
+#define HostCmd_CMD_ROBUST_COEX 0x00e0
+
+/** Host Command ID : Enhanced PS mode */
+#define HostCmd_CMD_802_11_PS_MODE_ENH 0x00e4
+
+/** Host command action : Host sleep configuration */
+#define HostCmd_CMD_802_11_HS_CFG_ENH 0x00e5
+
+/** Host Command ID : CAU register access */
+#define HostCmd_CMD_CAU_REG_ACCESS 0x00ed
+
+/** Host Command ID : mgmt IE list */
+#define HostCmd_CMD_MGMT_IE_LIST 0x00f2
+
+#if CONFIG_EXT_SCAN_SUPPORT
+/** Host Command ID : Extended scan support */
+#define HostCmd_CMD_802_11_SCAN_EXT 0x0107
+#endif
+
+/** Host Command ID : Forward mgmt frame */
+#define HostCmd_CMD_RX_MGMT_IND 0x010c
+
+/** Host Command ID : Set BSS_MODE */
+#define HostCmd_CMD_SET_BSS_MODE 0x00f7
+
+/** TLV OF CHAN_TRPC_CONFIG */
+#define TLV_TYPE_CHAN_TRPC_CONFIG (PROPRIETARY_TLV_BASE_ID + 137U)
+
+/** Host Command ID: Channel TRPC Config */
+#define HostCmd_CMD_CHANNEL_TRPC_CONFIG 0x00fb
+
+/**  Host Command id: SYS_INFO */
+#define HOST_CMD_APCMD_SYS_INFO 0x00ae
+/** Host Command id: sys_reset */
+#define HOST_CMD_APCMD_SYS_RESET 0x00af
+/** Host Command id: SYS_CONFIGURE  */
+#define HOST_CMD_APCMD_SYS_CONFIGURE 0x00b0
+/** Host Command id: BSS_START */
+#define HOST_CMD_APCMD_BSS_START 0x00b1
+/** Host Command id: BSS_STOP  */
+#define HOST_CMD_APCMD_BSS_STOP 0x00b2
+/** Host Command id: sta_list */
+#define HOST_CMD_APCMD_STA_LIST 0x00b3
+/** Host Command id: STA_DEAUTH */
+#define HOST_CMD_APCMD_STA_DEAUTH 0x00b5
+
+
+/** Host Command ID: Tx data pause */
+#define HostCmd_CMD_CFG_TX_DATA_PAUSE 0x0103
+
+#if CONFIG_GTK_REKEY_OFFLOAD
+/** Host Command ID: GTK REKEY OFFLOAD CFG */
+#define HostCmd_CMD_CONFIG_GTK_REKEY_OFFLOAD_CFG 0x010f
+#endif
+
+/** Host Command ID: Remain On Channel */
+#define HostCmd_CMD_802_11_REMAIN_ON_CHANNEL 0x010d
+
+/** Host Command ID: 11AC config */
+#define HostCmd_CMD_11AC_CFG 0x0112
+
+/** Host Command ID : OTP user data */
+#define HostCmd_CMD_OTP_READ_USER_DATA 0x0114
+
+
+#ifdef SD8801
+#define HostCmd_CMD_ED_MAC_MODE 0x0124
+#else
+#define HostCmd_CMD_ED_MAC_MODE 0x0130
+#endif
+
+#ifdef WLAN_LOW_POWER_ENABLE
+#define HostCmd_CMD_LOW_POWER_MODE 0x0128
+#endif /* WLAN_LOW_POWER_ENABLE */
+
+#define HOST_CMD_SMART_MODE_CFG 0x012d
+
+#define HostCmd_CMD_AUTO_RECONNECT 0x0115
+
+/** Host Command ID : PMF_PARAMS */
+#define HostCmd_CMD_PMF_PARAMS 0x0131
+
+/** Host Command ID: ACS scan */
+#define HostCMD_APCMD_ACS_SCAN 0x0224
+
+/** Host Command ID : Bridge Mode */
+#define HostCmd_CMD_BRIDGE_MODE 0x022e
+
+/** Host Command ID: CW Mode */
+#define HostCmd_CMD_CW_MODE_CTRL 0x0239
+
+#if CONFIG_WMM
+/** Host Command ID: WMM Param Config */
+#define HostCmd_CMD_WMM_PARAM_CONFIG 0x023a
+#endif
+
+#if CONFIG_FW_VDLL
+#define HostCmd_CMD_VDLL 0x0240
+#endif
+
+#define HostCmd_CMD_BOOT_SLEEP 0x0258
+
+#ifdef SD8801
+#define HostCmd_MMH_ACS_CFG 0x025a
+#endif
+
+/** Host Command ID : GET TBTT Offset stats */
+#define HostCmd_CMD_TBTT_OFFSET 0x0268
+
+#if (CONFIG_IPS)
+/** Host Command ID : IPS Config */
+#define HostCmd_CMD_IPS_CONFIG 0x0279
+#endif
+
+#if CONFIG_RX_ABORT_CFG
+#define HostCmd_CMD_RX_ABORT_CFG 0x0261
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+#define HostCmd_CMD_RX_ABORT_CFG_EXT 0x0262
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+#define HostCmd_CMD_CCK_DESENSE_CFG 0x0265
+#endif
+
+/** Host Command ID: Tx Frame */
+#define HostCmd_CMD_802_11_TX_FRAME 0x0283
+
+#if 0
+/** Enhanced PS modes */
+typedef enum _ENH_PS_MODES
+{
+    GET_PS = 0,
+    SLEEP_CONFIRM = 5,
+    DIS_AUTO_PS = 0xfe,
+    EN_AUTO_PS = 0xff,
+} ENH_PS_MODES;
+#endif
+
+/** Command RET code, MSB is set to 1 */
+#define HostCmd_RET_BIT 0x8000
+
+/** General purpose action : Get */
+#define HostCmd_ACT_GEN_GET 0x0000U
+/** General purpose action : Set */
+#define HostCmd_ACT_GEN_SET 0x0001U
+/** Special purpose action : Set */
+#define HostCmd_ACT_SPC_SET 0x8001
+
+#if CONFIG_AUTO_NULL_TX
+/** Special purpose action : Set */
+#define HostCmd_ACT_SPC_AUTO_SET 0x8002
+/** Special purpose action : Set */
+#define HostCmd_ACT_SPC_AUTO_NOSET 0x8003
+#endif
+/** General purpose action : Get_Current */
+#define HostCmd_ACT_GEN_GET_CURRENT 0x0003
+/** General purpose action : Remove */
+#define HostCmd_ACT_GEN_REMOVE 0x0004
+/** General purpose action : Reset */
+#define HostCmd_ACT_GEN_RESET 0x0005
+
+#define HostCmd_ACT_GEN_START 0x0002
+#define HostCmd_ACT_GEN_STOP  0x0003
+
+/** Host command action : Set Rx */
+#define HostCmd_ACT_SET_RX 0x0001
+/** Host command action : Set Tx */
+#define HostCmd_ACT_SET_TX 0x0002
+/** Host command action : Set both Rx and Tx */
+#define HostCmd_ACT_SET_BOTH 0x0003
+/** Host command action : Get Rx */
+#define HostCmd_ACT_GET_RX 0x0004
+/** Host command action : Get Tx */
+#define HostCmd_ACT_GET_TX 0x0008
+/** Host command action : Get both Rx and Tx */
+#define HostCmd_ACT_GET_BOTH 0x000cU
+
+#if (CONFIG_WIFI_TX_PER_TRACK) || (CONFIG_TX_RX_HISTOGRAM)
+/** Host command action: Get Tx statics */
+#define HostCmd_ACT_GET_TX_STATICS 0x0001
+/** Host command action: Get Rx statics */
+#define HostCmd_ACT_GET_RX_STATICS 0x0002
+/** Host command action: Get both Tx and Rx statics */
+#define HostCmd_ACT_GET_BOTH_TX_AND_RX 0x0003
+/** Host command action: Set Tx PER tracking */
+#define HostCmd_ACT_SET_TX_PER_TRACKING 0x0004
+#endif
+
+/** General Result Code*/
+/** General result code OK */
+#define HostCmd_RESULT_OK 0x0000U
+/** Genenral error */
+#define HostCmd_RESULT_ERROR 0x0001
+/** Command is not valid */
+#define HostCmd_RESULT_NOT_SUPPORT 0x0002
+/** Command is pending */
+#define HostCmd_RESULT_PENDING 0x0003
+/** System is busy (command ignored) */
+#define HostCmd_RESULT_BUSY 0x0004U
+/** Data buffer is not big enough */
+#define HostCmd_RESULT_PARTIAL_DATA 0x0005
+
+/* Define action or option for HostCmd_CMD_MAC_CONTROL */
+/** MAC action : Rx on */
+#define HostCmd_ACT_MAC_RX_ON 0x0001U
+/** MAC action : Tx on */
+#define HostCmd_ACT_MAC_TX_ON 0x0002U
+/** MAC action : WEP enable */
+#define HostCmd_ACT_MAC_WEP_ENABLE 0x0008U
+/** MAC action : EthernetII enable */
+#define HostCmd_ACT_MAC_ETHERNETII_ENABLE 0x0010U
+/** MAC action : Promiscous mode enable */
+#define HostCmd_ACT_MAC_PROMISCUOUS_ENABLE 0x0080U
+/** MAC action : All multicast enable */
+#define HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE 0x0100
+/** MAC action : RTS/CTS enable */
+#define HostCmd_ACT_MAC_RTS_CTS_ENABLE 0x0200
+/** MAC action : Strict protection enable */
+#define HostCmd_ACT_MAC_STRICT_PROTECTION_ENABLE 0x0400
+/** MAC action : Force 11n protection disable */
+#define HostCmd_ACT_MAC_FORCE_11N_PROTECTION_OFF 0x0800
+/** MAC action : Ad-Hoc G protection on */
+#define HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON 0x2000
+#if CONFIG_11AC
+/** MAC action : Static-Dynamic BW enable */
+#define HostCmd_ACT_MAC_STATIC_DYNAMIC_BW_ENABLE MBIT(16)
+/** MAC action : Dynamic BW */
+#define HostCmd_ACT_MAC_DYNAMIC_BW MBIT(17)
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+/** Host Command ID : FTM session config and control */
+#define HostCmd_CMD_FTM_SESSION_CFG         0x024d
+#define HostCmd_CMD_FTM_SESSION_CTRL        0x024e
+#define HostCmd_CMD_DOT11MC_UNASSOC_FTM_CFG 0x0275
+#endif
+
+/* Define action or option for HostCmd_CMD_802_11_SCAN */
+/** Scan type : BSS */
+#define HostCmd_BSS_MODE_BSS 0x0001
+/** Scan type : IBSS */
+#define HostCmd_BSS_MODE_IBSS 0x0002
+/** Scan type : Any */
+#define HostCmd_BSS_MODE_ANY 0x0003
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+#define HostCmd_CMD_TX_AMPDU_PROT_MODE 0x0263
+#endif
+
+#if CONFIG_CSI
+#define HostCmd_CMD_CSI 0x025b
+#define CSI_CMD_ENABLE  0x0001
+#define CSI_CMD_DISABLE 0x0002
+#endif
+
+#if CONFIG_11AX
+/** Host Command ID: 11AX config */
+#define HostCmd_CMD_11AX_CFG 0x0266
+
+/** Host Command ID: 11AX command */
+#define HostCmd_CMD_11AX_CMD 0x026d
+
+#if CONFIG_11AX_TWT
+/** Host Command ID: TWT cfg command */
+#define HostCmd_CMD_TWT_CFG 0x0270
+#endif /* CONFIG_11AX_TWT */
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+/** Host Command ID: GPIO TSF LATCH */
+#define HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG 0x0278
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+/** Host Command ID: HS Wakeup Reason */
+#define HostCmd_CMD_HS_WAKEUP_REASON 0x0116
+
+#if CONFIG_MULTI_CHAN
+/** Host Command ID: Multi chan config */
+#define HostCmd_CMD_MULTI_CHAN_CONFIG 0x011e
+/** Host Command ID: Multi chan policy */
+#define HostCmd_CMD_MULTI_CHAN_POLICY 0x0121
+/** TLV ID for multi chan info */
+#define TLV_TYPE_MULTI_CHAN_INFO (PROPRIETARY_TLV_BASE_ID + 0xb7)
+/** TLV ID for multi chan group info */
+#define TLV_TYPE_MULTI_CHAN_GROUP_INFO_TLV_ID (PROPRIETARY_TLV_BASE_ID + 0xb8)
+/** TLV ID for DRCS TimeSlice */
+#define MRVL_DRCS_TIME_SLICE_TLV_ID (PROPRIETARY_TLV_BASE_ID + 263U)
+/** Host Command ID: DRCS config */
+#define HostCmd_CMD_DRCS_CONFIG 0x024a
+
+#endif
+
+
+/* Radio type definitions for the channel TLV */
+/** Radio type BG */
+#define HostCmd_SCAN_RADIO_TYPE_BG 0U
+/** Radio type A */
+#define HostCmd_SCAN_RADIO_TYPE_A 1U
+
+/** Pairwise Cipher Suite length */
+#define PAIRWISE_CIPHER_SUITE_LEN 4
+/** AKM Suite length */
+#define AKM_SUITE_LEN 4
+/** PMKID length */
+#define PMKID_LEN 16
+/** Group mgmt Cipher Suite length */
+#define GROUP_MGMT_CIPHER_SUITE_LEN 4
+/** MFPC bit in RSN capability */
+#define MFPC_BIT 7
+/** MFPR bit in RSN capability */
+#define MFPR_BIT 6
+/** PMF ORing mask */
+#define PMF_MASK 0x00c0
+
+/** Bit mask for TxPD flags field for Tx status report */
+#define MRVDRV_TxPD_FLAGS_TX_PACKET_STATUS MBIT(5)
+
+/** Define bitmap conditions for HOST_SLEEP_CFG : GPIO FF */
+#define HOST_SLEEP_CFG_GPIO_FF 0xff
+/** Define bitmap conditions for HOST_SLEEP_CFG : GAP FF */
+#define HOST_SLEEP_CFG_GAP_FF 0xff
+
+/** Buffer Constants */
+/** Number of command buffers */
+#define MRVDRV_NUM_OF_CMD_BUFFER 20
+/** Size of command buffer */
+#define MRVDRV_SIZE_OF_CMD_BUFFER 2048U
+
+/** Maximum number of BSS Descriptors */
+/* wmsdk: Count taken from kconfig */
+#if CONFIG_MAX_AP_ENTRIES
+#define MRVDRV_MAX_BSSID_LIST CONFIG_MAX_AP_ENTRIES
+#else
+#define MRVDRV_MAX_BSSID_LIST 20U
+#endif /* CONFIG_MAX_AP_ENTRIES */
+
+/** Host command flag in command */
+#define CMD_F_HOSTCMD (1 << 0)
+/** command cancel flag in command */
+#define CMD_F_CANCELED (1 << 1)
+
+/** Host Command ID bit mask (bit 11:0) */
+#define HostCmd_CMD_ID_MASK 0x0fffU
+
+/** Host Command Sequence number mask (bit 7:0) */
+#define HostCmd_SEQ_NUM_MASK 0x00ff
+
+/** Host Command BSS number mask (bit 11:8) */
+#define HostCmd_BSS_NUM_MASK 0x0f00
+
+/** Host Command BSS type mask (bit 15:12) */
+#define HostCmd_BSS_TYPE_MASK 0xf000U
+
+/** Set BSS information to Host Command */
+#define HostCmd_SET_SEQ_NO_BSS_INFO(seq, num, type) \
+    (((seq)&0x00ffU) | (((num)&0x000fU) << 8U)) | (((type)&0x000fU) << 12U)
+
+/** Get Sequence Number from Host Command (bit 7:0) */
+#define HostCmd_GET_SEQ_NO(seq) ((seq)&HostCmd_SEQ_NUM_MASK)
+
+/** Get BSS number from Host Command (bit 11:8) */
+#define HostCmd_GET_BSS_NO(seq) (((seq)&HostCmd_BSS_NUM_MASK) >> 8)
+
+/** Get BSS type from Host Command (bit 15:12) */
+#define HostCmd_GET_BSS_TYPE(seq) (((seq)&HostCmd_BSS_TYPE_MASK) >> 12)
+
+/** Card Event definition : Dummy host wakeup signal */
+#define EVENT_DUMMY_HOST_WAKEUP_SIGNAL 0x00000001
+/** Card Event definition : Link lost */
+#define EVENT_LINK_LOST 0x00000003
+/** Card Event definition : Link sensed */
+#define EVENT_LINK_SENSED 0x00000004
+/** Card Event definition : MIB changed */
+#define EVENT_MIB_CHANGED 0x00000006
+/** Card Event definition : Init done */
+#define EVENT_INIT_DONE 0x00000007
+/** Card Event definition : Deauthenticated */
+#define EVENT_DEAUTHENTICATED 0x00000008
+/** Card Event definition : Disassociated */
+#define EVENT_DISASSOCIATED 0x00000009
+/** Card Event definition : Power save awake */
+#define EVENT_PS_AWAKE 0x0000000a
+/** Card Event definition : Power save sleep */
+#define EVENT_PS_SLEEP 0x0000000b
+#if (CONFIG_WNM_PS)
+/** Card Event definition : WNM power save */
+#define EVENT_WNM_PS 0x00000097
+#endif
+/** Card Event definition : MIC error multicast */
+#define EVENT_MIC_ERR_MULTICAST 0x0000000d
+/** Card Event definition : MIC error unicast */
+#define EVENT_MIC_ERR_UNICAST 0x0000000e
+
+/** Card Event definition : Ad-Hoc BCN lost */
+#define EVENT_ADHOC_BCN_LOST 0x00000011
+
+/** Card Event definition : Stop Tx */
+#define EVENT_STOP_TX 0x00000013
+/** Card Event definition : Start Tx */
+#define EVENT_START_TX 0x00000014
+/** Card Event definition : Channel switch */
+#define EVENT_CHANNEL_SWITCH 0x00000015
+
+/** Card Event definition : MEAS report ready */
+#define EVENT_MEAS_REPORT_RDY 0x00000016
+
+/** Card Event definition : WMM status change */
+#define EVENT_WMM_STATUS_CHANGE 0x00000017
+
+/** Card Event definition : BG scan report */
+#define EVENT_BG_SCAN_REPORT 0x00000018
+/** Card Event definition : BG scan stopped */
+#define EVENT_BG_SCAN_STOPPED 0x00000065
+/** Card Event definition : Beacon RSSI low */
+#define EVENT_RSSI_LOW 0x00000019
+/** Card Event definition : Beacon SNR low */
+#define EVENT_SNR_LOW 0x0000001a
+/** Card Event definition : Maximum fail */
+#define EVENT_MAX_FAIL 0x0000001b
+/** Card Event definition : Beacon RSSI high */
+#define EVENT_RSSI_HIGH 0x0000001c
+/** Card Event definition : Beacon SNR high */
+#define EVENT_SNR_HIGH 0x0000001d
+
+/** Card Event definition : IBSS coalsced */
+#define EVENT_IBSS_COALESCED 0x0000001e
+
+/** Card Event definition : Data RSSI low */
+#define EVENT_DATA_RSSI_LOW 0x00000024
+/** Card Event definition : Data SNR low */
+#define EVENT_DATA_SNR_LOW 0x00000025
+/** Card Event definition : Data RSSI high */
+#define EVENT_DATA_RSSI_HIGH 0x00000026
+/** Card Event definition : Data SNR high */
+#define EVENT_DATA_SNR_HIGH 0x00000027
+
+/** Card Event definition : Link Quality */
+#define EVENT_LINK_QUALITY 0x00000028
+
+/** Card Event definition : Port release event */
+#define EVENT_PORT_RELEASE 0x0000002b
+
+/** Card Event definition : Pre-Beacon Lost */
+#define EVENT_PRE_BEACON_LOST 0x00000031
+
+/** Card Event definition : Add BA event */
+#define EVENT_ADDBA 0x00000033
+/** Card Event definition : Del BA event */
+#define EVENT_DELBA 0x00000034
+/** Card Event definition: BA stream timeout*/
+#define EVENT_BA_STREAM_TIMEOUT 0x00000037
+
+/** Card Event definition : AMSDU aggr control */
+#define EVENT_AMSDU_AGGR_CTRL 0x00000042
+
+/** Card Event definition: WEP ICV error */
+#define EVENT_WEP_ICV_ERR 0x00000046
+
+/** Card Event definition : Host sleep enable */
+#define EVENT_HS_ACT_REQ 0x00000047
+
+/** Card Event definition : BW changed */
+#define EVENT_BW_CHANGE 0x00000048
+
+/* fixme: enable this macro check after it is enabled systemically */
+/*  #ifdef WIFI_DIRECT_SUPPORT */
+/** WIFIDIRECT generic event */
+#define EVENT_WIFIDIRECT_GENERIC_EVENT 0x00000049
+/** WIFIDIRECT service discovery event */
+#define EVENT_WIFIDIRECT_SERVICE_DISCOVERY 0x0000004a
+/** Remain on Channel expired event */
+#define EVENT_REMAIN_ON_CHANNEL_EXPIRED 0x0000005f
+/* #endif */
+
+/** Card Event definition: Channel switch pending announcment */
+#define EVENT_CHANNEL_SWITCH_ANN 0x00000050
+
+/** Event definition:  Radar Detected by card */
+#define EVENT_RADAR_DETECTED 0x00000053
+
+/** Event definition:  Radar Detected by card */
+#define EVENT_CHANNEL_REPORT_RDY 0x00000054
+
+/** Event definition:  wake-up indication to host by card */
+#define EVENT_MEF_HOST_WAKEUP 0x0000004f
+#if CONFIG_EXT_SCAN_SUPPORT
+/** Event definition:  Scan results through event */
+#define EVENT_EXT_SCAN_REPORT 0x00000058
+#endif
+
+/** Event definition: RXBA_SYNC */
+#define EVENT_RXBA_SYNC 0x00000059
+
+#ifdef SD9177
+#define EVENT_IMD3_CAL_START 0x000000A0
+#define EVENT_IMD3_CAL_END   0x000000A1
+#endif
+
+#if CONFIG_WIFI_FW_DEBUG
+/** Event definition : FW debug information */
+#define EVENT_FW_DEBUG_INFO 0x00000063
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+#define EVENT_WLS_FTM_COMPLETE 0x00000086
+
+#define WLS_SUB_EVENT_FTM_COMPLETE       0
+#define WLS_SUB_EVENT_RADIO_RECEIVED     1
+#define WLS_SUB_EVENT_RADIO_RPT_RECEIVED 2
+#define WLS_SUB_EVENT_ANQP_RESP_RECEIVED 3
+#define WLS_SUB_EVENT_RTT_RESULTS        4
+#define WLS_SUB_EVENT_FTM_FAIL           5
+
+#endif
+
+#if CONFIG_11K
+#define EVENT_NLIST_REPORT          0x00000079
+#define MRVL_NEIGHBOR_REPORT_TLV_ID 0x1de
+#endif
+
+#if (CONFIG_FW_VDLL) || (CONFIG_FW_VDLLV2)
+#define EVENT_VDLL_IND 0x00000081
+#endif
+
+
+/** Event ID: STA deauth */
+#define EVENT_MICRO_AP_STA_DEAUTH 0x0000002c
+/** Event ID: STA assoicated */
+#define EVENT_MICRO_AP_STA_ASSOC 0x0000002d
+/** Event ID: BSS started */
+#define EVENT_MICRO_AP_BSS_START 0x0000002e
+/** Event ID: BSS idle event */
+#define EVENT_MICRO_AP_BSS_IDLE 0x00000043
+/** Event ID: BSS active event */
+#define EVENT_MICRO_AP_BSS_ACTIVE 0x00000044
+/** Event ID: uAP in connected state for non-Open Auth*/
+#define EVENT_MICRO_AP_RSN_CONNECT 0x00000051
+
+
+/** Event ID: TX data pause event */
+#define EVENT_TX_DATA_PAUSE 0x00000055
+
+#if CONFIG_MULTI_CHAN
+/** Event ID: Multi Chan Info*/
+#define EVENT_MULTI_CHAN_INFO 0x0000006a
+#endif
+
+#define EVENT_TX_STATUS_REPORT 0x00000074
+
+#if (CONFIG_CSI) || (CONFIG_11MC) || (CONFIG_11AZ)
+#define EVENT_CSI 0x0000008D
+#endif
+
+/** Event ID: EV_SMC_GENERIC */
+#define EVENT_EV_SMC_GENERIC 0x00000077
+
+#if CONFIG_CSI
+#define EVENT_CSI 0x0000008D
+#endif
+
+/** Card Event definition : RESET PN */
+
+#define EVENT_BLOCKEDSTA_AUTH_REPORT 0x00000093
+
+/** Event ID: Assoc Req IE*/
+#define EVENT_ASSOC_REQ_IE 0x00000095
+
+#define EVENT_ACCESS_BY_HOST 0x00000098
+
+/** Event ID mask */
+#define EVENT_ID_MASK 0xffff
+
+/** BSS number mask */
+#define BSS_NUM_MASK 0xfU
+
+/** Get BSS number from event cause (bit 23:16) */
+#define EVENT_GET_BSS_NUM(event_cause) (((event_cause) >> 16) & BSS_NUM_MASK)
+
+/** Get BSS type from event cause (bit 31:24) */
+#define EVENT_GET_BSS_TYPE(event_cause) (((event_cause) >> 24) & 0x00ff)
+
+#if CONFIG_TSP
+#define HostCmd_CMD_TSP_CFG 0x0280
+#endif
+
+#ifdef OTP_CHANINFO
+#define HostCmd_CMD_CHAN_REGION_CFG 0x0242
+/* mod_grp */
+typedef enum _mod_grp
+{
+    MOD_CCK,          // 0
+    MOD_OFDM_PSK,     // 1
+    MOD_OFDM_QAM16,   // 2
+    MOD_OFDM_QAM64,   // 3
+    MOD_HT_20_PSK,    // 4
+    MOD_HT_20_QAM16,  // 5
+    MOD_HT_20_QAM64,  // 6
+    MOD_HT_40_PSK,    // 7
+    MOD_HT_40_QAM16,  // 8
+    MOD_HT_40_QAM64,  // 9
+#ifdef STREAM_2x2
+    MOD_HT2_20_PSK,   // 10
+    MOD_HT2_20_QAM16, // 11
+    MOD_HT2_20_QAM64, // 12
+    MOD_HT2_40_PSK,   // 13
+    MOD_HT2_40_QAM16, // 14
+    MOD_HT2_40_QAM64, // 15
+#endif
+
+#if CONFIG_11AC
+    MOD_VHT_20_QAM256,  // 16
+    MOD_VHT_40_QAM256,  // 17
+    MOD_VHT_80_PSK,     // 18
+    MOD_VHT_80_QAM16,   // 19
+    MOD_VHT_80_QAM64,   // 20
+    MOD_VHT_80_QAM256,  // 21
+#ifdef STREAM_2x2
+    MOD_VHT2_20_QAM256, // 22
+    MOD_VHT2_40_QAM256, // 23
+    MOD_VHT2_80_PSK,    // 24
+    MOD_VHT2_80_QAM16,  // 25
+    MOD_VHT2_80_QAM64,  // 26
+    MOD_VHT2_80_QAM256, // 27
+#endif
+#endif
+} mod_grp;
+
+typedef MLAN_PACK_START struct _power_table_attr
+{
+    t_u8 rows_2g;
+    t_u8 cols_2g;
+    t_u8 rows_5g;
+    t_u8 cols_5g;
+} MLAN_PACK_END power_table_attr_t;
+
+#define FW_CFP_TABLE_MAX_ROWS_BG 14
+#define FW_CFP_TABLE_MAX_COLS_BG 11
+
+#if CONFIG_5GHz_SUPPORT
+#define FW_CFP_TABLE_MAX_ROWS_A 42
+#define FW_CFP_TABLE_MAX_COLS_A 17
+#endif /* CONFIG_5GHz_SUPPORT */
+#endif /* OTP_CHANINFO */
+
+/** Host Command ID : GPIO independent reset configure */
+#define HostCmd_CMD_INDEPENDENT_RESET_CFG 0x0243
+
+#if CONFIG_COMPRESS_TX_PWTBL
+/** used in hostcmd to download region power cfg setting to firmware */
+#define HostCmd_CMD_REGION_POWER_CFG 0x0249
+#endif
+
+/** Event_WEP_ICV_ERR structure */
+typedef MLAN_PACK_START struct _Event_WEP_ICV_ERR
+{
+    /** Reason code */
+    t_u16 reason_code;
+    /** Source MAC address */
+    t_u8 src_mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** WEP decryption used key */
+    t_u8 wep_key_index;
+    /** WEP key length */
+    t_u8 wep_key_length;
+    /** WEP key */
+    t_u8 key[MAX_WEP_KEY_SIZE];
+} MLAN_PACK_END Event_WEP_ICV_ERR;
+
+/** WLAN_802_11_FIXED_IEs */
+typedef MLAN_PACK_START struct _WLAN_802_11_FIXED_IEs
+{
+    /** Timestamp */
+    t_u8 time_stamp[8];
+    /** Beacon interval */
+    t_u16 beacon_interval;
+    /** Capabilities*/
+    t_u16 capabilities;
+} MLAN_PACK_END WLAN_802_11_FIXED_IEs;
+
+/** WLAN_802_11_VARIABLE_IEs */
+typedef MLAN_PACK_START struct _WLAN_802_11_VARIABLE_IEs
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 length;
+    /** IE data */
+    t_u8 data[1];
+} MLAN_PACK_END WLAN_802_11_VARIABLE_IEs;
+
+/** TLV related data structures*/
+/** MrvlIEtypesHeader_t */
+typedef MLAN_PACK_START struct _MrvlIEtypesHeader
+{
+    /** Header type */
+    t_u16 type;
+    /** Header length */
+    t_u16 len;
+} MLAN_PACK_END MrvlIEtypesHeader_t;
+
+/** MrvlIEtypes_Data_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Data_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Data */
+    t_u8 data[1];
+} MLAN_PACK_END MrvlIEtypes_Data_t;
+
+/** MrvlIEtypes_PrevBssid_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_PrevBssid_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** prev_bssid **/
+    t_u8 prev_bssid[6];
+} MLAN_PACK_END MrvlIEtypes_PrevBssid_t;
+
+/** MrvlIETypes_ActionFrame_t */
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypesHeader_t header; /**< Header */
+
+    t_u8 smcstartAddr[MLAN_MAC_ADDR_LENGTH];
+    t_u8 smcendAddr[MLAN_MAC_ADDR_LENGTH];
+    t_u16 filter_type;
+
+} MLAN_PACK_END MrvlIETypes_SmcAddrRange_t;
+
+#if CONFIG_HOST_SLEEP
+#define MAX_MGMT_FRAME_FILTER         2
+#define EVENT_MANAGEMENT_FRAME_WAKEUP 0x00000088
+
+typedef MLAN_PACK_START struct _mgmt_frame_filter
+{
+    /** action - bitmap
+     ** On matching rx'd pkt and filter during NON_HOSTSLEEP mode:
+     **   Action[1]=0  Discard
+     **   Action[1]=1  Allow
+     ** Note that default action on non-match is "Allow".
+     **
+     ** On matching rx'd pkt and filter during HOSTSLEEP mode:
+     **   Action[1:0]=00  Discard and Not Wake host
+     **   Action[1:0]=01  Discard and Wake host
+     **   Action[1:0]=10  Invalid
+     ** Note that default action on non-match is "Discard and Not Wake
+     *host".
+     **/
+    t_u8 action;
+    /** Frame type(p2p...)
+     ** type=0: invalid
+     ** type=1: p2p
+     ** type=0xff: management frames(assoc req/rsp, probe req/rsp,...)
+     ** type=others: reserved
+     **/
+    t_u8 type;
+    /** Frame mask according to each type
+     ** When type=1 for p2p, frame-mask have following define:
+     **    Bit      Frame
+     **     0       GO Negotiation Request
+     **     1       GO Negotiation Response
+     **     2       GO Negotiation Confirmation
+     **     3       P2P Invitation Request
+     **     4       P2P Invitation Response
+     **     5       Device Discoverability Request
+     **     6       Device Discoverability Response
+     **     7       Provision Discovery Request
+     **     8       Provision Discovery Response
+     **     9       Notice of Absence
+     **     10      P2P Presence Request
+     **     11      P2P Presence Response
+     **     12      GO Discoverability Request
+     **     13-31   Reserved
+     **
+     ** When type=others, frame-mask is reserved.
+     **/
+    t_u32 frame_mask;
+} MLAN_PACK_END mgmt_frame_filter;
+
+/** MrvlIEtypes_MgmtFrameFilter_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_MgmtFrameFilter_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** management frame filters */
+    mgmt_frame_filter filter[MAX_MGMT_FRAME_FILTER];
+} MLAN_PACK_END MrvlIEtypes_MgmtFrameFilter_t;
+#endif
+
+/** MrvlIETypes_SMCFrameFilter_t */
+
+#define MAX_FILTER_LENGTH 10
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypesHeader_t header; /**< Header */
+    uint8_t frame_filter[MAX_FILTER_LENGTH];
+
+} MLAN_PACK_END MrvlIETypes_SmcFrameFilter_t;
+
+/** Bit mask for TxPD status field for null packet */
+#define MRVDRV_TxPD_POWER_MGMT_NULL_PACKET 0x01
+/** Bit mask for TxPD status field for last packet */
+#define MRVDRV_TxPD_POWER_MGMT_LAST_PACKET 0x08
+
+/** Packet type: 802.11 */
+#define PKT_TYPE_802DOT11   0x05
+#define PKT_TYPE_MGMT_FRAME 0xE5U
+/** Packet type: AMSDU */
+#define PKT_TYPE_AMSDU 0xE6U
+/** Packet type: BAR */
+#define PKT_TYPE_BAR 0xE7U
+/** Packet type: debugging */
+#define PKT_TYPE_DEBUG 0xEF
+
+/** TxPD descriptor */
+typedef MLAN_PACK_START struct _TxPD
+{
+    /** BSS type */
+    t_u8 bss_type;
+    /** BSS number */
+    t_u8 bss_num;
+    /** Tx packet length */
+    t_u16 tx_pkt_length;
+    /** Tx packet offset */
+    t_u16 tx_pkt_offset;
+    /** Tx packet type */
+    t_u16 tx_pkt_type;
+    /** Tx Control */
+    t_u32 tx_control;
+    /** Pkt Priority */
+    t_u8 priority;
+    /** Transmit Pkt Flags*/
+    t_u8 flags;
+    /** Amount of time the packet has been queued in the driver (units = 2ms)*/
+    t_u8 pkt_delay_2ms;
+    /** Reserved */
+    t_u8 reserved1[2];
+    /** Trasnit Pkt Token Id*/
+    t_u8 tx_token_id;
+    /** reserverd */
+    t_u8 reserved[4];
+} MLAN_PACK_END TxPD, *PTxPD;
+
+/** RxPD Descriptor */
+typedef MLAN_PACK_START struct _RxPD
+{
+    /** BSS type */
+    t_u8 bss_type;
+    /** BSS number */
+    t_u8 bss_num;
+    /** Rx Packet Length */
+    t_u16 rx_pkt_length;
+    /** Rx Pkt offset */
+    t_u16 rx_pkt_offset;
+    /** Rx packet type */
+    t_u16 rx_pkt_type;
+    /** Sequence number */
+    t_u16 seq_num;
+    /** Packet Priority */
+    t_u8 priority;
+    /** Rx Packet Rate */
+    t_u8 rx_rate;
+    /** SNR */
+    t_s8 snr;
+    /** Noise Floor */
+    t_s8 nf;
+#ifdef SD8801
+    /** Ht Info [Bit 0] RxRate format: LG=0, HT=1
+     * [Bit 1]  HT Bandwidth: BW20 = 0, BW40 = 1
+     * [Bit 2]  HT Guard Interval: LGI = 0, SGI = 1 */
+    t_u8 ht_info;
+#else
+    /** [Bit 1] [Bit 0] RxRate format: legacy rate = 00 HT = 01 VHT = 10
+     *  [Bit 3] [Bit 2] HT/VHT Bandwidth BW20 = 00 BW40 = 01 BW80 = 10 BW160 = 11
+     *  [Bit 4] HT/VHT Guard interval LGI = 0 SGI = 1
+     *  [Bit 5] STBC support Enabled = 1
+     *  [Bit 6] LDPC support Enabled = 1
+     *  [Bit 7] Reserved */
+    t_u8 rate_info;
+#endif
+    /** Reserved */
+    t_u8 reserved[3];
+    /** TDLS flags, bit 0: 0=InfraLink, 1=DirectLink */
+    t_u8 flags;
+    /**For SD8887 antenna info: 0 = 2.4G antenna a; 1 = 2.4G antenna b; 3 = 5G antenna; 0xff = invalid value */
+    t_u8 antenna;
+    /** Reserved */
+    t_u64 reserved1;
+    t_u32 rx_info;
+    /** Reserved */
+    t_u8 reserved3[8];
+} MLAN_PACK_END RxPD, *PRxPD;
+
+/** TxPD descriptor */
+typedef MLAN_PACK_START struct _UapTxPD
+{
+    /** BSS type */
+    t_u8 bss_type;
+    /** BSS number */
+    t_u8 bss_num;
+    /** Tx packet length */
+    t_u16 tx_pkt_length;
+    /** Tx packet offset */
+    t_u16 tx_pkt_offset;
+    /** Tx packet type */
+    t_u16 tx_pkt_type;
+    /** Tx Control */
+    t_u32 tx_control;
+    /** Pkt Priority */
+    t_u8 priority;
+    /** Transmit Pkt Flags*/
+    t_u8 flags;
+    /** Amount of time the packet has been queued in the driver (units = 2ms)*/
+    t_u8 pkt_delay_2ms;
+    /** Reserved */
+    t_u8 reserved1;
+    /** Reserved */
+    t_u32 reserved;
+} MLAN_PACK_END UapTxPD, *PUapTxPD;
+
+/** RxPD Descriptor */
+typedef MLAN_PACK_START struct _UapRxPD
+{
+    /** BSS Type */
+    t_u8 bss_type;
+    /** BSS number*/
+    t_u8 bss_num;
+    /** Rx packet length */
+    t_u16 rx_pkt_length;
+    /** Rx packet offset */
+    t_u16 rx_pkt_offset;
+    /** Rx packet type */
+    t_u16 rx_pkt_type;
+    /** Sequence number */
+    t_u16 seq_num;
+    /** Packet Priority */
+    t_u8 priority;
+    /** reserved */
+    t_u8 reserved1;
+} MLAN_PACK_END UapRxPD, *PUapRxPD;
+
+/** Fixed size of station association event */
+#define ASSOC_EVENT_FIX_SIZE 12U
+
+/** IEEEtypes_FrameCtl_t*/
+typedef MLAN_PACK_START struct _IEEEtypes_FrameCtl_t
+{
+    /** Protocol Version */
+    t_u8 protocol_version : 2;
+    /** Type */
+    t_u8 type : 2;
+    /** Sub Type */
+    t_u8 sub_type : 4;
+    /** To DS */
+    t_u8 to_ds : 1;
+    /** From DS */
+    t_u8 from_ds : 1;
+    /** More Frag */
+    t_u8 more_frag : 1;
+    /** Retry */
+    t_u8 retry : 1;
+    /** Power Mgmt */
+    t_u8 pwr_mgmt : 1;
+    /** More Data */
+    t_u8 more_data : 1;
+    /** Wep */
+    t_u8 wep : 1;
+    /** Order */
+    t_u8 order : 1;
+} MLAN_PACK_END IEEEtypes_FrameCtl_t;
+
+/** action add station */
+#define HostCmd_ACT_ADD_STA 0x1
+/** remove station */
+#define HostCmd_ACT_REMOVE_STA 0x0
+/** HostCmd_DS_ADD_STATION */
+typedef MLAN_PACK_START struct _HostCmd_DS_ADD_STATION
+{
+    /** 1 -add, 0 --delete */
+    t_u16 action;
+    /** aid */
+    t_u16 aid;
+    /** peer_mac */
+    t_u8 peer_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Listen Interval */
+    int listen_interval;
+    /** Capability Info */
+    t_u16 cap_info;
+    /** tlv start */
+    t_u8 tlv[];
+} MLAN_PACK_END HostCmd_DS_ADD_STATION;
+
+/** Host Command ID : Add New Station */
+#define HostCmd_CMD_ADD_NEW_STATION 0x025f
+/** TLV id: station flag */
+#define TLV_TYPE_UAP_STA_FLAGS (PROPRIETARY_TLV_BASE_ID + 313)
+/**MrvlIEtypes_Sta_Flag_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_StaFlag_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** station flag     */
+    t_u32 sta_flags;
+} MLAN_PACK_END MrvlIEtypes_StaFlag_t;
+
+/** MrvlIETypes_MgmtFrameSet_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_MgmtFrameSet_t
+{
+    /** Type */
+    t_u16 type;
+    /** Length */
+    t_u16 len;
+    /** Frame Control */
+    IEEEtypes_FrameCtl_t frame_control;
+    /* t_u8 frame_contents[0]; */
+} MLAN_PACK_END MrvlIETypes_MgmtFrameSet_t;
+
+/** IEEEtypes_AssocRqst_t */
+typedef MLAN_PACK_START struct _IEEEtypes_AssocRqst_t
+{
+    /** Capability Info */
+    t_u16 cap_info;
+    /** Listen Interval */
+    t_u16 listen_interval;
+    /* t_u8 ie_buffer[0]; */
+} MLAN_PACK_END IEEEtypes_AssocRqst_t;
+
+/** IEEEtypes_ReAssocRqst_t */
+typedef MLAN_PACK_START struct _IEEEtypes_ReAssocRqst_t
+{
+    /** Capability Info */
+    t_u16 cap_info;
+    /** Listen Interval */
+    t_u16 listen_interval;
+    /** Current AP Address */
+    t_u8 current_ap_addr[MLAN_MAC_ADDR_LENGTH];
+    /* t_u8 ie_buffer[0]; */
+} MLAN_PACK_END IEEEtypes_ReAssocRqst_t;
+
+/** wlan_802_11_header */
+typedef MLAN_PACK_START struct _wlan_802_11_header
+{
+    /** Frame Control */
+    t_u16 frm_ctl;
+    /** Duration ID */
+    t_u16 duration_id;
+    /** Address1 */
+    mlan_802_11_mac_addr addr1;
+    /** Address2 */
+    mlan_802_11_mac_addr addr2;
+    /** Address3 */
+    mlan_802_11_mac_addr addr3;
+    /** Sequence Control */
+    t_u16 seq_ctl;
+    /** Address4 */
+    mlan_802_11_mac_addr addr4;
+} MLAN_PACK_END wlan_802_11_header;
+
+
+/** wlan_802_11_header packet from FW with length */
+typedef MLAN_PACK_START struct _wlan_mgmt_pkt
+{
+    /** Packet Length */
+    t_u16 frm_len;
+    /** wlan_802_11_header */
+    wlan_802_11_header wlan_header;
+} MLAN_PACK_END wlan_mgmt_pkt;
+
+/** (Beaconsize(256)-5(IEId,len,contrystr(3))/3(FirstChan,NoOfChan,MaxPwr) */
+#define MAX_NO_OF_CHAN 40U
+
+/** Channel-power table entries */
+typedef MLAN_PACK_START struct _chan_power_11d
+{
+    /** 11D channel */
+    t_u8 chan;
+    /** Band for channel */
+    t_u8 band;
+    /** 11D channel power */
+    t_u8 pwr;
+    /** AP seen on channel */
+    t_u8 ap_seen;
+} MLAN_PACK_END chan_power_11d_t;
+
+/** Region channel info */
+typedef MLAN_PACK_START struct _parsed_region_chan_11d
+{
+    /** 11D channel power per channel */
+    chan_power_11d_t chan_pwr[MAX_NO_OF_CHAN];
+    /** 11D number of channels */
+    t_u8 no_of_chan;
+} MLAN_PACK_END parsed_region_chan_11d_t;
+
+/** ChanScanMode_t */
+typedef MLAN_PACK_START struct _ChanScanMode_t
+{
+    /** Channel scan mode passive flag */
+    t_u8 passive_scan : 1;
+    /** Disble channel filtering flag */
+    t_u8 disable_chan_filt : 1;
+    /** Multidomain scan mode */
+    t_u8 multidomain_scan : 1;
+    /** Enable probe response timeout */
+    t_u8 rsp_timeout_en : 1;
+    /** Enable hidden ssid report */
+    t_u8 hidden_ssid_report : 1;
+    /** First channel in scan */
+    t_u8 first_chan : 1;
+    /** First passive scan then active scan */
+    t_u8 passive_to_active_scan : 1;
+    /** Reserved */
+    t_u8 reserved_7 : 1;
+} MLAN_PACK_END ChanScanMode_t;
+
+/** secondary channel is below */
+#define SECOND_CHANNEL_BELOW 0x30
+/** secondary channel is above */
+#define SECOND_CHANNEL_ABOVE 0x10
+/** channel offset */
+enum
+{
+    SEC_CHAN_NONE  = 0,
+    SEC_CHAN_ABOVE = 1,
+    SEC_CHAN_BELOW = 3
+};
+/** channel bandwidth */
+enum
+{
+    CHAN_BW_20MHZ = 0,
+    CHAN_BW_10MHZ,
+    CHAN_BW_40MHZ,
+    CHAN_BW_80MHZ,
+};
+/** ChanScanParamSet_t */
+typedef MLAN_PACK_START struct _ChanScanParamSet_t
+{
+    /** Channel scan parameter : Radio type */
+    t_u8 radio_type;
+    /** Channel scan parameter : Channel number */
+    t_u8 chan_number;
+    /** Channel scan parameter : Channel scan mode */
+    ChanScanMode_t chan_scan_mode;
+    /** Channel scan parameter : Minimum scan time */
+    t_u16 min_scan_time;
+    /** Channel scan parameter : Maximum scan time */
+    t_u16 max_scan_time;
+} MLAN_PACK_END ChanScanParamSet_t;
+
+/** MrvlIEtypes_ChanListParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ChanListParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Channel scan parameters */
+    ChanScanParamSet_t chan_scan_param[1];
+} MLAN_PACK_END MrvlIEtypes_ChanListParamSet_t;
+
+/** ChanBandParamSet_t */
+typedef struct _ChanBandParamSet_t
+{
+    /** Channel scan parameter : Radio type */
+    t_u8 radio_type;
+    /** Channel number */
+    t_u8 chan_number;
+} ChanBandParamSet_t;
+
+/** MrvlIEtypes_ChanBandListParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ChanBandListParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Channel Band parameters */
+    ChanBandParamSet_t chan_band_param[1];
+} MLAN_PACK_END MrvlIEtypes_ChanBandListParamSet_t;
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+typedef MLAN_PACK_START struct _MrvlIEtypes_RssiThresholdParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Enable or disable the TLV */
+    t_u8 enable;
+    /** Threshold of RSSI */
+    t_s16 rssi_threshold;
+    /** Reserved */
+    t_u8 reserved;
+} MLAN_PACK_END MrvlIEtypes_RssiThresholdParamSet_t;
+#endif
+
+/** MrvlIEtypes_RatesParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_RatesParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Rates */
+    t_u8 rates[MAX_DATA_RATES];
+} MLAN_PACK_END MrvlIEtypes_RatesParamSet_t;
+
+#if CONFIG_EXT_SCAN_SUPPORT
+/** _MrvlIEtypes_Bssid_List_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Bssid_List_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END MrvlIEtypes_Bssid_List_t;
+#endif
+
+/** MrvlIEtypes_SsIdParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_SsIdParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** SSID */
+    t_u8 ssid[1];
+} MLAN_PACK_END MrvlIEtypes_SsIdParamSet_t;
+
+/**MrvlIEtypes_AssocType_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_HostMlme_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Authentication type */
+    t_u8 host_mlme;
+} MLAN_PACK_END MrvlIEtypes_HostMlme_t;
+
+/** MrvlIEtypes_NumProbes_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_NumProbes_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Number of probes */
+    t_u16 num_probes;
+} MLAN_PACK_END MrvlIEtypes_NumProbes_t;
+
+/** MrvlIEtypes_WildCardSsIdParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_WildCardSsIdParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Maximum SSID length */
+    t_u8 max_ssid_length;
+    /** SSID */
+    t_u8 ssid[1];
+} MLAN_PACK_END MrvlIEtypes_WildCardSsIdParamSet_t;
+
+/**TSF data size */
+#define TSF_DATA_SIZE 8U
+/** Table of TSF values returned in the scan result */
+typedef MLAN_PACK_START struct _MrvlIEtypes_TsfTimestamp_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** the length of each TSF data is 8 bytes, could be multiple TSF here */
+    t_u8 tsf_data[1];
+} MLAN_PACK_END MrvlIEtypes_TsfTimestamp_t;
+
+/** CfParamSet_t */
+typedef MLAN_PACK_START struct _CfParamSet_t
+{
+    /** CF parameter : Count */
+    t_u8 cfp_cnt;
+    /** CF parameter : Period */
+    t_u8 cfp_period;
+    /** CF parameter : Duration */
+    t_u16 cfp_max_duration;
+    /** CF parameter : Duration remaining */
+    t_u16 cfp_duration_remaining;
+} MLAN_PACK_END CfParamSet_t;
+
+/** IbssParamSet_t */
+typedef MLAN_PACK_START struct _IbssParamSet_t
+{
+    /** ATIM window value */
+    t_u16 atim_window;
+} MLAN_PACK_END IbssParamSet_t;
+
+/** MrvlIEtypes_SsParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_SsParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** CF/IBSS parameters sets */
+    union
+    {
+        /** CF parameter set */
+        CfParamSet_t cf_param_set[1];
+        /** IBSS parameter set */
+        IbssParamSet_t ibss_param_set[1];
+    } cf_ibss;
+} MLAN_PACK_END MrvlIEtypes_SsParamSet_t;
+
+/** FhParamSet_t */
+typedef MLAN_PACK_START struct _FhParamSet_t
+{
+    /** FH parameter : Dwell time */
+    t_u16 dwell_time;
+    /** FH parameter : Hop set */
+    t_u8 hop_set;
+    /** FH parameter : Hop pattern */
+    t_u8 hop_pattern;
+    /** FH parameter : Hop index */
+    t_u8 hop_index;
+} MLAN_PACK_END FhParamSet_t;
+
+/** DsParamSet_t */
+typedef MLAN_PACK_START struct _DsParamSet_t
+{
+    /** Current channel number */
+    t_u8 current_chan;
+} MLAN_PACK_END DsParamSet_t;
+
+/** MrvlIEtypes_PhyParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_PhyParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** FH/DS parameters */
+    union
+    {
+        /** FH parameter set */
+        FhParamSet_t fh_param_set[1];
+        /** DS parameter set */
+        DsParamSet_t ds_param_set[1];
+    } fh_ds;
+} MLAN_PACK_END MrvlIEtypes_PhyParamSet_t;
+
+/* Auth type to be used in the Authentication portion of an Assoc seq */
+/** MrvlIEtypes_AuthType_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_AuthType_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Authentication type */
+    t_u16 auth_type;
+} MLAN_PACK_END MrvlIEtypes_AuthType_t;
+
+#if CONFIG_SCAN_CHANNEL_GAP
+/** MrvlIEtypes_ScanChanGap_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ScanChanGap_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Time gap in units to TUs to be used between
+     * two consecutive channels scan */
+    t_u16 gap;
+} MLAN_PACK_END MrvlIEtypes_ScanChanGap_t;
+
+/** channel statictics */
+typedef MLAN_PACK_START struct _chan_statistics_t
+{
+    /** channle number */
+    t_u8 chan_num;
+    /** band info */
+    Band_Config_t bandcfg;
+    /** flags */
+    t_u8 flags;
+    /** noise */
+    t_s8 noise;
+    /** total network */
+    t_u16 total_networks;
+    /** scan duration */
+    t_u16 cca_scan_duration;
+    /** busy duration */
+    t_u16 cca_busy_duration;
+} MLAN_PACK_END chan_statistics_t;
+
+/** channel statictics tlv */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ChannelStats_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** channel statictics */
+    chan_statistics_t chanStat[];
+} MLAN_PACK_END MrvlIEtypes_ChannelStats_t;
+#endif
+
+/** MrvlIETypes_ActionFrame_t */
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypesHeader_t header; /**< Header */
+
+    t_u8 srcAddr[MLAN_MAC_ADDR_LENGTH];
+    t_u8 dstAddr[MLAN_MAC_ADDR_LENGTH];
+
+    IEEEtypes_ActionFrame_t actionFrame;
+
+} MLAN_PACK_END MrvlIETypes_ActionFrame_t;
+
+/** MrvlIEtypes_RxBaSync_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_RxBaSync_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** mac address */
+    t_u8 mac[MLAN_MAC_ADDR_LENGTH];
+    /** tid */
+    t_u8 tid;
+    /** reserved field */
+    t_u8 reserved;
+    /** start seq num */
+    t_u16 seq_num;
+    /** bitmap len */
+    t_u16 bitmap_len;
+    /** bitmap */
+    t_u8 bitmap[1];
+} MLAN_PACK_END MrvlIEtypes_RxBaSync_t;
+
+/** MrvlIEtypes_RsnParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_RsnParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** RSN IE */
+    t_u8 rsn_ie[1];
+} MLAN_PACK_END MrvlIEtypes_RsnParamSet_t;
+
+/** Key Info flag for multicast key */
+#define KEY_INFO_MCAST_KEY 0x01U
+/** Key Info flag for unicast key */
+#define KEY_INFO_UCAST_KEY 0x02U
+/** Key Info flag for enable key */
+#define KEY_INFO_ENABLE_KEY 0x04
+/** Key Info flag for default key */
+#define KEY_INFO_DEFAULT_KEY 0x08U
+/** Key Info flag for TX key */
+#define KEY_INFO_TX_KEY 0x10U
+/** Key Info flag for RX key */
+#define KEY_INFO_RX_KEY       0x20U
+#define KEY_INFO_CMAC_AES_KEY 0x400
+/** PN size for WPA/WPA2 */
+#define WPA_PN_SIZE 8
+/** PN size for PMF IGTK */
+#define IGTK_PN_SIZE 8
+/** WAPI KEY size */
+#define WAPI_KEY_SIZE 32
+/** key params fix size */
+#define KEY_PARAMS_FIXED_LEN 10U
+/** key index mask */
+#define KEY_INDEX_MASK 0xfU
+
+/** wep_param */
+typedef MLAN_PACK_START struct _wep_param_t
+{
+    /** key_len */
+    t_u16 key_len;
+    /** wep key */
+    t_u8 key[MAX_WEP_KEY_SIZE];
+} MLAN_PACK_END wep_param_t;
+
+/** tkip_param */
+typedef MLAN_PACK_START struct _tkip_param
+{
+    /** Rx packet num */
+    t_u8 pn[WPA_PN_SIZE];
+    /** key_len */
+    t_u16 key_len;
+    /** tkip key */
+    t_u8 key[WPA_TKIP_KEY_LEN];
+} MLAN_PACK_END tkip_param;
+
+/** aes_param */
+typedef MLAN_PACK_START struct _aes_param
+{
+    /** Rx packet num */
+    t_u8 pn[WPA_PN_SIZE];
+    /** key_len */
+    t_u16 key_len;
+    /** aes key */
+    t_u8 key[WPA_AES_KEY_LEN];
+} MLAN_PACK_END aes_param;
+
+/** wapi_param */
+typedef MLAN_PACK_START struct _wapi_param
+{
+    /** Rx packet num */
+    t_u8 pn[PN_SIZE];
+    /** key_len */
+    t_u16 key_len;
+    /** wapi key */
+    t_u8 key[WAPI_KEY_SIZE];
+} MLAN_PACK_END wapi_param;
+
+/** cmac_aes_param */
+typedef MLAN_PACK_START struct _cmac_aes_param
+{
+    /** IGTK pn */
+    t_u8 ipn[IGTK_PN_SIZE];
+    /** key_len */
+    t_u16 key_len;
+    /** aes key */
+    t_u8 key[CMAC_AES_KEY_LEN];
+} MLAN_PACK_END cmac_aes_param;
+
+/** gmac_aes_256_param */
+typedef MLAN_PACK_START struct _gmac_aes_256_param
+{
+    /** IGTK pn */
+    t_u8 ipn[IGTK_PN_SIZE];
+    /** key_len */
+    t_u16 key_len;
+    /** aes key */
+    t_u8 key[WPA_IGTK_256_KEY_LEN];
+} MLAN_PACK_END gmac_aes_256_param;
+
+/** gmac_param */
+typedef MLAN_PACK_START struct _gcmp_param
+{
+    /** GCMP pn */
+    t_u8 pn[WPA_PN_SIZE];
+    /** key_len */
+    t_u16 key_len; /** aes key */
+    t_u8 key[WPA_GCMP_KEY_LEN];
+} MLAN_PACK_END gcmp_param;
+
+/** ccmp256_param */
+typedef MLAN_PACK_START struct _ccmp256_param
+{
+    /** CCMP pn */
+    t_u8 pn[WPA_PN_SIZE];
+    /** key_len */
+    t_u16 key_len;
+    /** ccmp256 key */
+    t_u8 key[WPA_CCMP_256_KEY_LEN];
+} MLAN_PACK_END ccmp_256_param;
+
+/** MrvlIEtype_KeyParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtype_KeyParamSetV2_t
+{
+    /** Type ID */
+    t_u16 type;
+    /** Length of Payload */
+    t_u16 length;
+    /** mac address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** key index */
+    t_u8 key_idx;
+    /** Type of Key: WEP=0, TKIP=1, AES=2, WAPI=3 AES_CMAC=4 */
+    t_u8 key_type;
+    /** Key Control Info specific to a key_type_id */
+    t_u16 key_info;
+    union
+    {
+        /** wep key param */
+        wep_param_t wep;
+        /** tkip key param */
+        tkip_param tkip;
+        /** aes key param */
+        aes_param aes;
+        /** wapi key param */
+        wapi_param wapi;
+        /** IGTK key param */
+        cmac_aes_param cmac_aes;
+        /** IGTK key param */
+        gmac_aes_256_param gmac_aes;
+        /** gcmp key param */
+        gcmp_param gcmp;
+        /** ccmp 256 key parameters */
+        ccmp_256_param ccmp256;
+    } key_params;
+} MLAN_PACK_END MrvlIEtype_KeyParamSetV2_t;
+
+/** HostCmd_DS_802_11_KEY_MATERIAL */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_KEY_MATERIAL
+{
+    /** Action */
+    t_u16 action;
+    /** Key parameter set */
+    MrvlIEtype_KeyParamSetV2_t key_param_set;
+} MLAN_PACK_END HostCmd_DS_802_11_KEY_MATERIAL;
+
+#if CONFIG_GTK_REKEY_OFFLOAD
+/** HostCmd_DS_GTK_REKEY_PARAMS */
+typedef MLAN_PACK_START struct _HostCmd_DS_GTK_REKEY_PARAMS
+{
+    /** Action */
+    t_u16 action;
+    /** Key confirmation key */
+    t_u8 kck[MLAN_KCK_LEN];
+    /** Key encryption key */
+    t_u8 kek[MLAN_KEK_LEN];
+    /** Replay counter low 32 bit */
+    t_u32 replay_ctr_low;
+    /** Replay counter high 32 bit */
+    t_u32 replay_ctr_high;
+} MLAN_PACK_END HostCmd_DS_GTK_REKEY_PARAMS;
+#endif
+
+/** Data structure of WMM QoS information */
+typedef MLAN_PACK_START struct _WmmQosInfo_t
+{
+    /** Parameter set count */
+    t_u8 para_set_count : 4;
+    /** Reserved */
+    t_u8 reserved : 3;
+    /** QoS UAPSD */
+    t_u8 qos_uapsd : 1;
+} MLAN_PACK_END WmmQosInfo_t, *pWmmQosInfo_t;
+
+/** Data structure of WMM ECW */
+typedef MLAN_PACK_START struct _WmmEcw_t
+{
+    /** Minimum Ecw */
+    t_u8 ecw_min : 4;
+    /** Maximum Ecw */
+    t_u8 ecw_max : 4;
+} MLAN_PACK_END WmmEcw_t, *pWmmEcw_t;
+
+/** Data structure of WMM Aci/Aifsn */
+typedef MLAN_PACK_START struct _WmmAciAifsn_t
+{
+    /** Aifsn */
+    t_u8 aifsn : 4;
+    /** Acm */
+    t_u8 acm : 1;
+    /** Aci */
+    t_u8 aci : 2;
+    /** Reserved */
+    t_u8 reserved : 1;
+} MLAN_PACK_END WmmAciAifsn_t, *pWmmAciAifsn_t;
+
+/** Data structure of WMM AC parameters  */
+typedef MLAN_PACK_START struct _WmmAcParameters_t
+{
+    WmmAciAifsn_t aci_aifsn; /**< AciAifSn */
+    WmmEcw_t ecw;            /**< Ecw */
+    t_u16 tx_op_limit;       /**< Tx op limit */
+} MLAN_PACK_END WmmAcParameters_t, *pWmmAcParameters_t;
+
+/** Data structure of WMM parameter  */
+typedef MLAN_PACK_START struct _WmmParameter_t
+{
+    /** OuiType:  00:50:f2:02 */
+    t_u8 ouitype[4];
+    /** Oui subtype: 01 */
+    t_u8 ouisubtype;
+    /** version: 01 */
+    t_u8 version;
+    /** QoS information */
+    t_u8 qos_info;
+    /** Reserved */
+    t_u8 reserved;
+    /** AC Parameters Record WMM_AC_BE, WMM_AC_BK, WMM_AC_VI, WMM_AC_VO */
+    WmmAcParameters_t ac_params[MAX_AC_QUEUES];
+} MLAN_PACK_END WmmParameter_t, *pWmmParameter_t;
+
+/** Data structure of Host command WMM_PARAM_CFG  */
+typedef MLAN_PACK_START struct _HostCmd_DS_WMM_PARAM_CONFIG
+{
+    /** action */
+    t_u16 action;
+    /** AC Parameters Record WMM_AC_BE, WMM_AC_BK, WMM_AC_VI, WMM_AC_VO */
+    WmmAcParameters_t ac_params[MAX_AC_QUEUES];
+} MLAN_PACK_END HostCmd_DS_WMM_PARAM_CONFIG;
+
+/* Definition of firmware host command */
+/** HostCmd_DS_GEN */
+typedef MLAN_PACK_START struct _HostCmd_DS_GEN
+{
+    /** Command */
+    t_u16 command;
+    /** Size */
+    t_u16 size;
+    /** Sequence number */
+    t_u16 seq_num;
+    /** Result */
+    t_u16 result;
+} MLAN_PACK_END HostCmd_DS_GEN;
+
+/** Size of HostCmd_DS_GEN */
+#define S_DS_GEN sizeof(HostCmd_DS_GEN)
+
+#define MAX_MOD_GROUP 35
+/** modulation setting */
+typedef MLAN_PACK_START struct _mod_group_setting
+{
+    /** modulation group */
+    t_u8 mod_group;
+    /** power */
+    t_u8 power;
+} MLAN_PACK_END mod_group_setting;
+
+/** chan trpc config */
+typedef MLAN_PACK_START struct _ChanTRPCConfig_t
+{
+    /** start freq */
+    t_u16 start_freq;
+    /* channel width */
+    t_u8 width;
+    /** channel number */
+    t_u8 chan_num;
+    mod_group_setting mod_group[MAX_MOD_GROUP];
+} MLAN_PACK_END ChanTRPCConfig_t;
+
+/** MrvlIETypes_ChanTRPCConfig_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_ChanTRPCConfig_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** start freq */
+    t_u16 start_freq;
+    /* channel width */
+    t_u8 width;
+    /** channel number */
+    t_u8 chan_num;
+    mod_group_setting mod_group[0];
+} MLAN_PACK_END MrvlIETypes_ChanTRPCConfig_t;
+
+/** Address type: broadcast */
+#define ADDR_TYPE_BROADCAST 1
+/* Address type: unicast */
+#define ADDR_TYPE_UNICAST 2
+/* Address type: multicast */
+#define ADDR_TYPE_MULTICAST 3
+
+/** Ether type: any */
+#define ETHER_TYPE_ANY 0xffff
+/** Ether type: ARP */
+#define ETHER_TYPE_ARP 0x0608
+
+/** IPv4 address any */
+#define IPV4_ADDR_ANY 0xffffffffU
+
+/** Header structure for ARP filter */
+typedef MLAN_PACK_START struct _arpfilter_header
+{
+    /** Type */
+    t_u16 type;
+    /** TLV length */
+    t_u16 len;
+} MLAN_PACK_END arpfilter_header;
+
+/** Filter entry structure */
+typedef MLAN_PACK_START struct _filter_entry
+{
+    /** Address type */
+    t_u16 addr_type;
+    /** Ether type */
+    t_u16 eth_type;
+    /** IPv4 address */
+    t_u32 ipv4_addr;
+} MLAN_PACK_END filter_entry;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_MEF_CFG
+{
+    /** Criteria */
+    t_u32 criteria;
+    /** Number of entries */
+    t_u16 nentries;
+} MLAN_PACK_END HostCmd_DS_MEF_CFG;
+
+/** mef entry struct */
+typedef MLAN_PACK_START struct _mef_entry_header
+{
+    /**mode:1->hostsleep;2->non hostsleep mode*/
+    t_u8 mode;
+    /**action=0->discard and not wake host
+     * action=1->discard and wake host
+     * action=3->allow and wake host*/
+    t_u8 action;
+    /* Len */
+    t_u16 len;
+} MLAN_PACK_END mef_entry_header;
+
+/** mef op struct is to help to generate mef data*/
+typedef MLAN_PACK_START struct _mef_op
+{
+    /** operand_type*/
+    t_u8 operand_type;
+    /** reserved*/
+    t_u8 rsvd[3];
+    /** data */
+    t_u8 val[MAX_NUM_BYTE_SEQ + 1];
+} MLAN_PACK_END mef_op;
+
+/* HostCmd_DS_802_11_SLEEP_PERIOD */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SLEEP_PERIOD
+{
+    /** ACT_GET/ACT_SET */
+    t_u16 action;
+
+    /** Sleep Period in msec */
+    t_u16 sleep_pd;
+} MLAN_PACK_END HostCmd_DS_802_11_SLEEP_PERIOD;
+
+/* HostCmd_DS_802_11_SLEEP_PARAMS */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SLEEP_PARAMS
+{
+    /** ACT_GET/ACT_SET */
+    t_u16 action;
+    /** Sleep clock error in ppm */
+    t_u16 error;
+    /** Wakeup offset in usec */
+    t_u16 offset;
+    /** Clock stabilization time in usec */
+    t_u16 stable_time;
+    /** Control periodic calibration */
+    t_u8 cal_control;
+    /** Control the use of external sleep clock */
+    t_u8 external_sleep_clk;
+    /** Reserved field, should be set to zero */
+    t_u16 reserved;
+} MLAN_PACK_END HostCmd_DS_802_11_SLEEP_PARAMS;
+
+/** Sleep response control */
+typedef enum _sleep_resp_ctrl
+{
+    RESP_NOT_NEEDED = 0,
+    RESP_NEEDED,
+} sleep_resp_ctrl;
+
+/** Structure definition for the new ieee power save parameters*/
+typedef MLAN_PACK_START struct __ps_param
+{
+    /** Null packet interval */
+    t_u16 null_pkt_interval;
+    /** Num dtims */
+    t_u16 multiple_dtims;
+    /** becaon miss interval */
+    t_u16 bcn_miss_timeout;
+    /** local listen interval */
+    t_u16 local_listen_interval;
+    /** Adhoc awake period */
+    t_u16 adhoc_wake_period;
+    /** mode - (0x01 - firmware to automatically choose PS_POLL or NULL mode, 0x02 - PS_POLL, 0x03 - NULL mode ) */
+    t_u16 mode;
+    /** Delay to PS in milliseconds */
+    t_u16 delay_to_ps;
+} MLAN_PACK_END ps_param;
+
+/** Structure definition for the new auto deep sleep command */
+typedef MLAN_PACK_START struct __auto_ds_param
+{
+    /** Deep sleep inactivity timeout */
+    t_u16 deep_sleep_timeout;
+} MLAN_PACK_END auto_ds_param;
+
+#if (CONFIG_WNM_PS)
+/** Structure definition for the wnm power save command */
+typedef MLAN_PACK_START struct __wnm_ps_param
+{
+    /** 0: enable WNM Sleep Mode, 1: disable WNM Sleep Mode */
+    t_u8 action;
+    /** Null packet interval */
+    t_u16 null_pkt_interval;
+    /** becaon miss interval */
+    t_u16 bcn_miss_timeout;
+    /** local listen interval */
+    t_u16 local_listen_interval;
+    /** mode - (0x01 - firmware to automatically choose PS_POLL or NULL mode, 0x02 - PS_POLL, 0x03 - NULL mode ) */
+    t_u16 ps_mode;
+    /** Delay to PS in milliseconds */
+    t_u16 delay_to_ps;
+    /** WNM sleep interval */
+    t_u16 wnm_sleep_interval;
+} MLAN_PACK_END wnm_ps_param;
+
+/** Structure definition for the wnm power save result */
+typedef MLAN_PACK_START struct __wnm_ps_result
+{
+    /** 0: enable WNM Sleep Mode, 1: disable WNM Sleep Mode */
+    t_u8 action;
+    /** 0: successful; 1: fail */
+    t_u8 result;
+} MLAN_PACK_END wnm_ps_result;
+#endif
+
+/** Structure definition for sleep confirmation in the new ps command */
+typedef struct __sleep_confirm_param
+{
+    /** response control 0x00 - response not needed, 0x01 - response needed */
+    t_u16 resp_ctrl;
+} sleep_confirm_param;
+
+/* bit define for pre_asleep*/
+#define BLOCK_CMD_IN_PRE_ASLEEP MBIT(0)
+/** MrvlIEtypes_ext_ps_param_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ext_ps_param_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** mode: bit0:BLOCK_CMD_IN_PRE_ASLEEP */
+    t_u32 mode;
+} MLAN_PACK_END MrvlIEtypes_ext_ps_param_t;
+
+/** ext_ps_param_t */
+typedef MLAN_PACK_START struct _ext_ps_param
+{
+    /** reserved */
+    t_u16 reserved;
+    /** ext_ps_param tlv */
+    MrvlIEtypes_ext_ps_param_t param;
+} MLAN_PACK_END ext_ps_param;
+
+/** bitmap for get auto deepsleep */
+#define BITMAP_AUTO_DS 0x01U
+/** bitmap for sta power save */
+#define BITMAP_STA_PS 0x10U
+/** bitmap for uap inactivity based PS */
+#define BITMAP_UAP_INACT_PS 0x100U
+/** bitmap for uap DTIM PS */
+#define BITMAP_UAP_DTIM_PS 0x200U
+/** Structure definition for the new ieee power save parameters*/
+typedef struct _auto_ps_param
+{
+    /** bitmap for enable power save mode */
+    t_u16 ps_bitmap;
+    /* auto deep sleep parameter, sta power save parameter uap inactivity
+       parameter uap DTIM parameter */
+} auto_ps_param;
+
+/** fix size for auto ps */
+#define AUTO_PS_FIX_SIZE 4U
+
+/** TLV type : auto ds param */
+#define TLV_TYPE_AUTO_DS_PARAM (PROPRIETARY_TLV_BASE_ID + 0x71U) // 0x0171
+/** TLV type : ps param */
+#define TLV_TYPE_PS_PARAM (PROPRIETARY_TLV_BASE_ID + 0x72U) // 0x0172
+
+#if (CONFIG_WNM_PS)
+/** TLV type : wnm param */
+#define TLV_TYPE_WNM_PARAM (PROPRIETARY_TLV_BASE_ID + 0x158) // 0x0258
+#endif
+/** TLV type: ps_ext_param */
+#define TLV_TYPE_PS_EXT_PARAM (PROPRIETARY_TLV_BASE_ID + 0x15F) /* 0x25F */
+
+/** MrvlIEtypes_auto_ds_param_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_auto_ds_param_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** auto ds param */
+    auto_ds_param param;
+} MLAN_PACK_END MrvlIEtypes_auto_ds_param_t;
+
+/** MrvlIEtypes_ps_param_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ps_param_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** ps param */
+    ps_param param;
+} MLAN_PACK_END MrvlIEtypes_ps_param_t;
+
+#if (CONFIG_WNM_PS)
+/** MrvlIEtypes_wnm_ps_param_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_wnm_ps_param_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** wnm ps param */
+    wnm_ps_param param;
+} MLAN_PACK_END MrvlIEtypes_wnm_ps_param_t;
+#endif
+
+/** Structure definition for new power save command */
+typedef MLAN_PACK_START struct _HostCmd_DS_PS_MODE_ENH
+{
+    /** Action */
+    uint16_t action;
+    /** Data speciifc to action */
+    /* For IEEE power save data will be as UINT16 mode (0x01 - firmware to
+       automatically choose PS_POLL or NULL mode, 0x02 - PS_POLL, 0x03 - NULL
+       mode ) UINT16 NullpacketInterval UINT16 NumDtims UINT16
+       BeaconMissInterval UINT16 locallisteninterval UINT16 adhocawakeperiod */
+
+    /* For auto deep sleep */
+    /* UINT16 Deep sleep inactivity timeout */
+
+    /* For PS sleep confirm UINT16 responeCtrl - 0x00 - reponse from fw not
+       needed, 0x01 - response from fw is needed */
+
+    union
+    {
+        /** PS param definition */
+        ps_param opt_ps;
+        /** Auto ds param definition */
+        auto_ds_param auto_ds;
+        /** Sleep comfirm param definition */
+        sleep_confirm_param sleep_cfm;
+        /** bitmap for get PS info and Disable PS mode */
+        t_u16 ps_bitmap;
+        /** auto ps param */
+        auto_ps_param auto_ps;
+#if (CONFIG_WNM_PS)
+        /** wnm ps param */
+        wnm_ps_param param;
+#endif
+        /** ext ps param */
+        ext_ps_param ext_param;
+    } params;
+} MLAN_PACK_END HostCmd_DS_802_11_PS_MODE_ENH;
+
+/** UAP FW version 2 */
+#define UAP_FW_VERSION_2 0x2
+
+/** HostCMD_DS_APCMD_ACS_SCAN */
+typedef MLAN_PACK_START struct _HostCMD_DS_APCMD_ACS_SCAN
+{
+    /** band */
+    Band_Config_t bandcfg;
+    /** channel */
+    t_u8 chan;
+} MLAN_PACK_END HostCMD_DS_APCMD_ACS_SCAN;
+
+/** HostCmd_DS_GET_HW_SPEC */
+typedef MLAN_PACK_START struct _HostCmd_DS_GET_HW_SPEC
+{
+    /** HW Interface version number */
+    t_u16 hw_if_version;
+    /** HW version number */
+    t_u16 version;
+    /** Reserved field */
+    t_u16 reserved;
+    /** Max no of Multicast address  */
+    t_u16 num_of_mcast_adr;
+    /** MAC address */
+    t_u8 permanent_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Region Code */
+    t_u16 region_code;
+    /** Number of antenna used */
+    t_u16 number_of_antenna;
+    /** FW release number, example 0x1234=1.2.3.4 */
+    t_u32 fw_release_number;
+    /** hw dev cap */
+    t_u32 hw_dev_cap;
+    /** Reserved field */
+    t_u32 reserved_2;
+    /** Reserved field */
+    t_u32 reserved_3;
+    /** FW/HW Capability */
+    t_u32 fw_cap_info;
+    /** 802.11n Device Capabilities */
+    t_u32 dot_11n_dev_cap;
+    /** MIMO abstraction of MCSs supported by device */
+    t_u8 dev_mcs_support;
+    /** Valid end port at init */
+    t_u16 mp_end_port;
+    /** mgmt IE buffer count */
+    t_u16 mgmt_buf_count;
+    /** Reserved */
+    t_u32 reserved_8;
+    /** Reserved */
+    t_u32 reserved_9;
+    /** 802.11ac Device Capabilities */
+    t_u32 Dot11acDevCap;
+    /** MCSs supported by 802.11ac device */
+    t_u32 Dot11acMcsSupport;
+} MLAN_PACK_END HostCmd_DS_GET_HW_SPEC;
+
+/**  HostCmd_DS_802_11_CFG_DATA */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_CFG_DATA
+{
+    /** Action */
+    t_u16 action;
+    /** Type */
+    t_u16 type;
+    /** Data length */
+    t_u16 data_len;
+    /** Data */
+    t_u8 data[1];
+} MLAN_PACK_END HostCmd_DS_802_11_CFG_DATA;
+
+/**  HostCmd_DS_CMD_802_11_RSSI_INFO */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_RSSI_INFO
+{
+    /** Action */
+    t_u16 action;
+    /** Parameter used for exponential averaging for Data */
+    t_u16 ndata;
+    /** Parameter used for exponential averaging for Beacon */
+    t_u16 nbcn;
+    /** Reserved field 0 */
+    t_u16 reserved[9];
+    /** Reserved field 1 */
+    t_u64 reserved_1;
+} MLAN_PACK_END HostCmd_DS_802_11_RSSI_INFO;
+
+/** HostCmd_DS_802_11_RSSI_INFO_RSP */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_RSSI_INFO_RSP
+{
+    /** Action */
+    t_u16 action;
+    /** Parameter used for exponential averaging for Data */
+    t_u16 ndata;
+    /** Parameter used for exponential averaging for beacon */
+    t_u16 nbcn;
+    /** Last Data RSSI in dBm */
+    t_s16 data_rssi_last;
+    /** Last Data NF in dBm */
+    t_s16 data_nf_last;
+    /** AVG DATA RSSI in dBm */
+    t_s16 data_rssi_avg;
+    /** AVG DATA NF in dBm */
+    t_s16 data_nf_avg;
+    /** Last BEACON RSSI in dBm */
+    t_s16 bcn_rssi_last;
+    /** Last BEACON NF in dBm */
+    t_s16 bcn_nf_last;
+    /** AVG BEACON RSSI in dBm */
+    t_s16 bcn_rssi_avg;
+    /** AVG BEACON NF in dBm */
+    t_s16 bcn_nf_avg;
+    /** Last RSSI Beacon TSF */
+    t_u64 tsf_bcn;
+} MLAN_PACK_END HostCmd_DS_802_11_RSSI_INFO_RSP;
+
+/** HostCmd_DS_802_11_MAC_ADDRESS */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_MAC_ADDRESS
+{
+    /** Action */
+    t_u16 action;
+    /** MAC address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END HostCmd_DS_802_11_MAC_ADDRESS;
+
+/** HostCmd_DS_MAC_CONTROL */
+typedef MLAN_PACK_START struct _HostCmd_DS_MAC_CONTROL
+{
+    /** Action */
+    t_u32 action;
+} MLAN_PACK_END HostCmd_DS_MAC_CONTROL;
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+/** HostCmd_DS_IND_RST */
+typedef MLAN_PACK_START struct _HostCmd_DS_IND_RST
+{
+    /** Action */
+    t_u16 action;
+    /** CMD_SUBID */
+    t_u16 sub_id;
+} MLAN_PACK_END HostCmd_DS_IND_RST;
+
+/** HostCmd_DS_INDEPENDENT_RESET_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_INDEPENDENT_RESET_CFG
+{
+    /** ACT_GET/ACT_SET */
+    t_u16 action;
+    /** out band independent reset */
+    t_u8 ir_mode;
+    /** gpio pin */
+    t_u8 gpio_pin;
+} MLAN_PACK_END HostCmd_DS_INDEPENDENT_RESET_CFG;
+#endif
+
+/** HostCmd_DS_CMD_TX_DATA_PAUSE */
+typedef MLAN_PACK_START struct _HostCmd_DS_CMD_TX_DATA_PAUSE
+{
+    /** Action */
+    t_u16 action;
+    /** Enable/disable Tx data pause */
+    t_u8 enable_tx_pause;
+    /** Max number of TX buffers allowed for all PS clients*/
+    t_u8 pause_tx_count;
+} MLAN_PACK_END HostCmd_DS_CMD_TX_DATA_PAUSE;
+
+/** TLV type : TX pause TLV */
+#define TLV_TYPE_TX_PAUSE (PROPRIETARY_TLV_BASE_ID + 0x94) // 0x0194
+/** MrvlIEtypes_SsIdParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_tx_pause_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** peer mac address */
+    t_u8 peermac[MLAN_MAC_ADDR_LENGTH];
+    /** Tx pause state, 1--pause, 0--free flowing */
+    t_u8 tx_pause;
+    /** total packets queued for the client */
+    t_u8 pkt_cnt;
+} MLAN_PACK_END MrvlIEtypes_tx_pause_t;
+
+/**  HostCmd_CMD_MAC_MULTICAST_ADR */
+typedef MLAN_PACK_START struct _HostCmd_DS_MAC_MULTICAST_ADR
+{
+    /** Action */
+    t_u16 action;
+    /** Number of addresses */
+    t_u16 num_of_adrs;
+    /** List of MAC */
+    t_u8 mac_list[MLAN_MAC_ADDR_LENGTH * MLAN_MAX_MULTICAST_LIST_SIZE];
+} MLAN_PACK_END HostCmd_DS_MAC_MULTICAST_ADR;
+
+/**  HostCmd_CMD_802_11_DEAUTHENTICATE */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_DEAUTHENTICATE
+{
+    /** MAC address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Deauthentication resaon code */
+    t_u16 reason_code;
+} MLAN_PACK_END HostCmd_DS_802_11_DEAUTHENTICATE;
+
+/** HostCmd_DS_802_11_ASSOCIATE */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_ASSOCIATE
+{
+    /** Peer STA address */
+    t_u8 peer_sta_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Capability information */
+    IEEEtypes_CapInfo_t cap_info;
+    /** Listen interval */
+    t_u16 listen_interval;
+    /** Beacon period */
+    t_u16 beacon_period;
+    /** DTIM period */
+    t_u8 dtim_period;
+
+    /**
+     *  MrvlIEtypes_SsIdParamSet_t  SsIdParamSet;
+     *  MrvlIEtypes_PhyParamSet_t   PhyParamSet;
+     *  MrvlIEtypes_SsParamSet_t    SsParamSet;
+     *  MrvlIEtypes_RatesParamSet_t RatesParamSet;
+     */
+} MLAN_PACK_END HostCmd_DS_802_11_ASSOCIATE;
+
+/** HostCmd_CMD_802_11_ASSOCIATE response */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_ASSOCIATE_RSP
+{
+    /** Association response structure */
+    IEEEtypes_AssocRsp_t assoc_rsp;
+} MLAN_PACK_END HostCmd_DS_802_11_ASSOCIATE_RSP;
+
+/** HostCmd_DS_802_11_AD_HOC_START*/
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_AD_HOC_START
+{
+    /** AdHoc SSID */
+    t_u8 ssid[MLAN_MAX_SSID_LENGTH];
+    /** BSS mode */
+    mlan_bss_mode bss_mode;
+    /** Beacon period */
+    t_u16 beacon_period;
+    /** DTIM period */
+    t_u8 dtim_period;
+    /** SS parameter set */
+    IEEEtypes_SsParamSet_t ss_param_set;
+    /** PHY parameter set */
+    IEEEtypes_PhyParamSet_t phy_param_set;
+    /** Reserved field */
+    t_u16 reserved1;
+    /** Capability information */
+    IEEEtypes_CapInfo_t cap;
+    /** Supported data rates */
+    t_u8 DataRate[HOSTCMD_SUPPORTED_RATES];
+} MLAN_PACK_END HostCmd_DS_802_11_AD_HOC_START;
+
+/**  HostCmd_CMD_802_11_AD_HOC_START response */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_AD_HOC_START_RESULT
+{
+    /** Padding */
+    t_u8 pad[3];
+    /** AdHoc BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Padding to sync with FW structure*/
+    t_u8 pad2[2];
+    /** Result */
+    t_u8 result;
+} MLAN_PACK_END HostCmd_DS_802_11_AD_HOC_START_RESULT;
+
+/**  HostCmd_CMD_802_11_AD_HOC_START response */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_AD_HOC_JOIN_RESULT
+{
+    /** Result */
+    t_u8 result;
+} MLAN_PACK_END HostCmd_DS_802_11_AD_HOC_JOIN_RESULT;
+
+/** AdHoc_BssDesc_t */
+typedef MLAN_PACK_START struct _AdHoc_BssDesc_t
+{
+    /** BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** SSID */
+    t_u8 ssid[MLAN_MAX_SSID_LENGTH];
+    /** BSS mode */
+    mlan_bss_mode bss_mode;
+    /** Beacon period */
+    t_u16 beacon_period;
+    /** DTIM period */
+    t_u8 dtim_period;
+    /** Timestamp */
+    t_u8 time_stamp[8];
+    /** Local time */
+    t_u8 local_time[8];
+    /** PHY parameter set */
+    IEEEtypes_PhyParamSet_t phy_param_set;
+    /** SS parameter set */
+    IEEEtypes_SsParamSet_t ss_param_set;
+    /** Capability information */
+    IEEEtypes_CapInfo_t cap;
+    /** Supported data rates */
+    t_u8 data_rates[HOSTCMD_SUPPORTED_RATES];
+
+    /*
+     *  DO NOT ADD ANY FIELDS TO THIS STRUCTURE.
+     *  It is used in the Adhoc join command and will cause a
+     *  binary layout mismatch with the firmware
+     */
+} MLAN_PACK_END AdHoc_BssDesc_t;
+
+/** HostCmd_DS_802_11_AD_HOC_JOIN */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_AD_HOC_JOIN
+{
+    /** AdHoc BSS descriptor */
+    AdHoc_BssDesc_t bss_descriptor;
+    /** Reserved field */
+    t_u16 reserved1;
+    /** Reserved field */
+    t_u16 reserved2;
+} MLAN_PACK_END HostCmd_DS_802_11_AD_HOC_JOIN;
+
+#if CONFIG_NET_MONITOR
+/** MrvlIEtypes_Monitor_filter_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Monitor_filter_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** mac num of filter*/
+    t_u8 filter_num;
+    /** mac address */
+    mlan_802_11_mac_addr mac_list[MAX_MONIT_MAC_FILTER_NUM];
+} MLAN_PACK_END MrvlIEtypes_Monitor_filter_t;
+
+/**  HostCmd_CMD_802_11_NET_MONITOR */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_NET_MONITOR
+{
+    t_u16 action;
+    t_u16 monitor_activity;
+    t_u16 filter_flags;
+    MrvlIEtypes_ChanBandListParamSet_t monitor_channel;
+    MrvlIEtypes_Monitor_filter_t monitor_filter;
+} MLAN_PACK_END HostCmd_DS_802_11_NET_MONITOR;
+#endif
+
+/** Interrupt Raising Edge */
+#define INT_RASING_EDGE 0
+/** Interrupt Falling Edge */
+#define INT_FALLING_EDGE 1
+
+/** Delay 1 usec */
+#define DELAY_1_US 1
+
+typedef MLAN_PACK_START struct _HostCmd_DS_SDIO_GPIO_INT_CONFIG
+{
+    /** Action */
+    t_u16 action;
+    /** GPIO interrupt pin */
+    t_u16 gpio_pin;
+    /** GPIO interrupt edge, 1: failing edge; 0: raising edge */
+    t_u16 gpio_int_edge;
+    /** GPIO interrupt pulse widthin usec units */
+    t_u16 gpio_pulse_width;
+} MLAN_PACK_END HostCmd_DS_SDIO_GPIO_INT_CONFIG;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_SDIO_PULL_CTRL
+{
+    /** Action */
+    t_u16 action;
+    /** The delay of pulling up in us */
+    t_u16 pull_up;
+    /** The delay of pulling down in us */
+    t_u16 pull_down;
+} MLAN_PACK_END HostCmd_DS_SDIO_PULL_CTRL;
+
+/** HostCmd_DS_802_11_GET_LOG */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_GET_LOG
+{
+    /** Number of multicast transmitted frames */
+    t_u32 mcast_tx_frame;
+    /** Number of failures */
+    t_u32 failed;
+    /** Number of retries */
+    t_u32 retry;
+    /** Number of multiretries */
+    t_u32 multiretry;
+    /** Number of duplicate frames */
+    t_u32 frame_dup;
+    /** Number of RTS success */
+    t_u32 rts_success;
+    /** Number of RTS failure */
+    t_u32 rts_failure;
+    /** Number of acknowledgement failure */
+    t_u32 ack_failure;
+    /** Number of fragmented packets received */
+    t_u32 rx_frag;
+    /** Number of multicast frames received */
+    t_u32 mcast_rx_frame;
+    /** FCS error */
+    t_u32 fcs_error;
+    /** Number of transmitted frames */
+    t_u32 tx_frame;
+    /** Reserved field */
+    t_u32 reserved;
+    /** Number of WEP icv error for each key */
+    t_u32 wep_icv_err_cnt[4];
+    /** Beacon received count */
+    t_u32 bcn_rcv_cnt;
+    /** Beacon missed count */
+    t_u32 bcn_miss_cnt;
+    /** Tx frag count */
+    t_u32 tx_frag_cnt;
+    /** Qos Tx frag count */
+    t_u32 qos_tx_frag_cnt[8];
+    /** Qos failed count */
+    t_u32 qos_failed_cnt[8];
+    /** Qos retry count */
+    t_u32 qos_retry_cnt[8];
+    /** Qos multi retry count */
+    t_u32 qos_multi_retry_cnt[8];
+    /** Qos frame dup count */
+    t_u32 qos_frm_dup_cnt[8];
+    /** Qos rts success count */
+    t_u32 qos_rts_suc_cnt[8];
+    /** Qos rts failure count */
+    t_u32 qos_rts_failure_cnt[8];
+    /** Qos ack failure count */
+    t_u32 qos_ack_failure_cnt[8];
+    /** Qos Rx frag count */
+    t_u32 qos_rx_frag_cnt[8];
+    /** Qos Tx frame count */
+    t_u32 qos_tx_frm_cnt[8];
+    /** Qos discarded frame count */
+    t_u32 qos_discarded_frm_cnt[8];
+    /** Qos mpdus Rx count */
+    t_u32 qos_mpdus_rx_cnt[8];
+    /** Qos retry rx count */
+    t_u32 qos_retries_rx_cnt[8];
+    /** CMAC ICV errors count */
+    t_u32 cmacicv_errors;
+    /** CMAC replays count */
+    t_u32 cmac_replays;
+    /** mgmt CCMP replays count */
+    t_u32 mgmt_ccmp_replays;
+    /** TKIP ICV errors count */
+    t_u32 tkipicv_errors;
+    /** TKIP replays count */
+    t_u32 tkip_replays;
+    /** CCMP decrypt errors count */
+    t_u32 ccmp_decrypt_errors;
+    /** CCMP replays count */
+    t_u32 ccmp_replays;
+    /** Tx amsdu count */
+    t_u32 tx_amsdu_cnt;
+    /** failed amsdu count */
+    t_u32 failed_amsdu_cnt;
+    /** retry amsdu count */
+    t_u32 retry_amsdu_cnt;
+    /** multi-retry amsdu count */
+    t_u32 multi_retry_amsdu_cnt;
+    /** Tx octets in amsdu count */
+    t_u64 tx_octets_in_amsdu_cnt;
+    /** amsdu ack failure count */
+    t_u32 amsdu_ack_failure_cnt;
+    /** Rx amsdu count */
+    t_u32 rx_amsdu_cnt;
+    /** Rx octets in amsdu count */
+    t_u64 rx_octets_in_amsdu_cnt;
+    /** Tx ampdu count */
+    t_u32 tx_ampdu_cnt;
+    /** tx mpdus in ampdu count */
+    t_u32 tx_mpdus_in_ampdu_cnt;
+    /** tx octets in ampdu count */
+    t_u64 tx_octets_in_ampdu_cnt;
+    /** ampdu Rx count */
+    t_u32 ampdu_rx_cnt;
+    /** mpdu in Rx ampdu count */
+    t_u32 mpdu_in_rx_ampdu_cnt;
+    /** Rx octets ampdu count */
+    t_u64 rx_octets_in_ampdu_cnt;
+    /** ampdu delimiter CRC error count */
+    t_u32 ampdu_delimiter_crc_error_cnt;
+    /** Rx Stuck Related Info*/
+    /** Rx Stuck Issue count */
+    t_u32 rx_stuck_issue_cnt[2];
+    /** Rx Stuck Recovery count */
+    t_u32 rx_stuck_recovery_cnt;
+    /** Rx Stuck TSF */
+    t_u64 rx_stuck_tsf[2];
+    /** Tx Watchdog Recovery Related Info */
+    /** Tx Watchdog Recovery count */
+    t_u32 tx_watchdog_recovery_cnt;
+    /** Tx Watchdog TSF */
+    t_u64 tx_watchdog_tsf[2];
+    /** Channel Switch Related Info */
+    /** Channel Switch Announcement Sent */
+    t_u32 channel_switch_ann_sent;
+    /** Channel Switch State */
+    t_u32 channel_switch_state;
+    /** Register Class */
+    t_u32 reg_class;
+    /** Channel Number */
+    t_u32 channel_number;
+    /** Channel Switch Mode */
+    t_u32 channel_switch_mode;
+    /** Reset Rx Mac Count */
+    t_u32 rx_reset_mac_recovery_cnt;
+    /** ISR2 Not Done Count*/
+    t_u32 rx_Isr2_NotDone_Cnt;
+    /** GDMA Abort Count */
+    t_u32 gdma_abort_cnt;
+    /** Rx Reset MAC Count */
+    t_u32 g_reset_rx_mac_cnt;
+    // Ownership error counters
+    /*Error Ownership error count*/
+    t_u32 dwCtlErrCnt;
+    /*Control Ownership error count*/
+    t_u32 dwBcnErrCnt;
+    /*Control Ownership error count*/
+    t_u32 dwMgtErrCnt;
+    /*Control Ownership error count*/
+    t_u32 dwDatErrCnt;
+    /*BIGTK MME good count*/
+    t_u32 bigtk_mmeGoodCnt;
+    /*BIGTK Replay error count*/
+    t_u32 bigtk_replayErrCnt;
+    /*BIGTK MIC error count*/
+    t_u32 bigtk_micErrCnt;
+    /*BIGTK MME not included count*/
+    t_u32 bigtk_mmeNotFoundCnt;
+} MLAN_PACK_END HostCmd_DS_802_11_GET_LOG;
+
+/**_HostCmd_TX_RATE_QUERY */
+typedef MLAN_PACK_START struct _HostCmd_TX_RATE_QUERY
+{
+    /** Tx rate */
+    t_u8 tx_rate;
+#ifdef SD8801
+    /** Ht Info [Bit 0] RxRate format: LG=0, HT=1
+     * [Bit 1]  HT Bandwidth: BW20 = 0, BW40 = 1
+     * [Bit 2]  HT Guard Interval: LGI = 0, SGI = 1 */
+    t_u8 ht_info;
+#else
+    /** Tx Rate Info:
+     * [Bit 0-1] tx rate format: LG = 0, HT = 1, VHT = 2, HE = 3
+     * [Bit 2-3] HT/VHT Bandwidth: BW20 = 0, BW40 = 1, BW80 = 2, BW160 = 3
+     * [Bit 4]   HT/VHT Guard Interval: LGI = 0, SGI = 1
+     * [Bit 5]   STBC support
+     * [Bit 6]   LDPC support
+     * [Bit 7] [Bit 4] 11ax GI, 00, 01, 10, 11 */
+    t_u8 tx_rate_info;
+#endif
+#if CONFIG_11AX
+    /**
+     * BIT0: DCM
+     * BIT3-BIT1: tone mode
+     **  000: 26  tone
+     **  001: 52  tone
+     **  010: 106 tone
+     **  011: 242 tone
+     **  100: 484 tone
+     **  101: 996 tone
+     * BIT7-BIT4: resvd
+     **/
+    t_u8 ext_tx_rate_info;
+#endif
+} MLAN_PACK_END HostCmd_TX_RATE_QUERY;
+
+typedef MLAN_PACK_START struct _hs_config_param
+{
+    /** bit0=1: broadcast data
+     * bit1=1: unicast data
+     * bit2=1: mac events
+     * bit3=1: multicast data
+     */
+    t_u32 conditions;
+    /** GPIO pin or 0xff for interface */
+    t_u8 gpio;
+    /** gap in milliseconds or or 0xff for special setting when GPIO is used to wakeup host */
+    t_u8 gap;
+} MLAN_PACK_END hs_config_param;
+
+#if 0
+/** HS Action 0x0001 - Configure enhanced host sleep mode, 0x0002 - Activate enhanced host sleep mode */
+typedef enum _Host_Sleep_Action
+{
+    HS_CONFIGURE = 0x0001,
+    HS_ACTIVATE = 0x0002,
+} Host_Sleep_Action;
+#endif
+
+/** Structure definition for activating enhanced hs */
+typedef MLAN_PACK_START struct __hs_activate_param
+{
+    /** response control 0x00 - response not needed, 0x01 - response needed */
+    t_u16 resp_ctrl;
+} MLAN_PACK_END hs_activate_param;
+
+/** HostCmd_DS_802_11_HS_CFG_ENH */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_HS_CFG_ENH
+{
+    /** Action 0x0001 - Configure enhanced host sleep mode, 0x0002 - Activate enhanced host sleep mode */
+    t_u16 action;
+
+    union
+    {
+        /** Configure enhanced hs */
+        hs_config_param hs_config;
+        /** Activate enhanced hs */
+        hs_activate_param hs_activate;
+    } params;
+} MLAN_PACK_END HostCmd_DS_802_11_HS_CFG_ENH;
+
+/** SNMP_MIB_INDEX */
+typedef enum _SNMP_MIB_INDEX
+{
+    OpRateSet_i     = 1,
+    DtimPeriod_i    = 3,
+    RtsThresh_i     = 5,
+    ShortRetryLim_i = 6,
+    LongRetryLim_i  = 7,
+    FragThresh_i    = 8,
+    Dot11D_i        = 9,
+    Dot11H_i        = 10,
+    WwsMode_i       = 17,
+    Thermal_i       = 34,
+    ECSAEnable_i    = 42,
+    StopDeauth_i    = 44,
+} SNMP_MIB_INDEX;
+
+#if CONFIG_TURBO_MODE
+/** Used just for Turbo mode */
+#define OID_WMM_TURBO_MODE 0x27
+/** turbo_mode parameters */
+typedef MLAN_PACK_START struct _turbo_mode_para
+{
+    t_u16 action;
+    t_u16 oid;
+    t_u16 size;
+    /** set prot mode */
+    t_u8 mode;
+} MLAN_PACK_END turbo_mode_para;
+#endif
+
+/** max SNMP buf size */
+#define MAX_SNMP_BUF_SIZE 128U
+
+/**  HostCmd_CMD_802_11_SNMP_MIB */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SNMP_MIB
+{
+    /** SNMP query type */
+    t_u16 query_type;
+    /** SNMP object ID */
+    t_u16 oid;
+    /** SNMP buffer size */
+    t_u16 buf_size;
+    /** Value */
+    t_u8 value[1];
+} MLAN_PACK_END HostCmd_DS_802_11_SNMP_MIB;
+
+/** HostCmd_DS_AUTO_TX structure */
+typedef MLAN_PACK_START struct _HostCmd_DS_AUTO_TX
+{
+    /** Action Set or get */
+    t_u16 action;
+    /** Tlv buffer */
+    t_u8 tlv_buffer[0];
+} MLAN_PACK_END HostCmd_DS_AUTO_TX;
+
+#define OID_CLOUD_KEEP_ALIVE              0
+#define EVENT_CLOUD_KEEP_ALIVE_RETRY_FAIL 133
+/** TLV for cloud keep alive control info */
+#define TLV_TYPE_CLOUD_KEEP_ALIVE (PROPRIETARY_TLV_BASE_ID + 0x102) /* 0x0100 + 258 */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Cloud_Keep_Alive_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** ID for cloud keep alive */
+    t_u8 keep_alive_id;
+    /** Enable/disable for this ID */
+    t_u8 enable;
+    /** TLV buffer */
+    t_u8 tlv[0];
+} MLAN_PACK_END MrvlIEtypes_Cloud_Keep_Alive_t;
+
+/** TLV for cloud keep alive control info */
+#define TLV_TYPE_KEEP_ALIVE_CTRL (PROPRIETARY_TLV_BASE_ID + 0x103) /* 0x0100 + 259 */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Keep_Alive_Ctrl_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** period to send keep alive packet */
+    t_u32 snd_interval;
+    /** period to send retry packet */
+    t_u16 retry_interval;
+    /** count to send retry packet */
+    t_u16 retry_count;
+} MLAN_PACK_END MrvlIEtypes_Keep_Alive_Ctrl_t;
+
+/** TLV for cloud keep alive packet */
+#define TLV_TYPE_KEEP_ALIVE_PKT (PROPRIETARY_TLV_BASE_ID + 0x104) /* 0x0100 + 260 */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Keep_Alive_Pkt_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Ethernet Header */
+    Eth803Hdr_t eth_header;
+    /** packet buffer*/
+    t_u8 ip_packet[];
+} MLAN_PACK_END MrvlIEtypes_Keep_Alive_Pkt_t;
+
+#define TLV_TYPE_AUTO_TX (PROPRIETARY_TLV_BASE_ID + 0x18) // 0x0118
+/** AutoTx_MacFrame_t */
+typedef MLAN_PACK_START struct AutoTx_MacFrame
+{
+    t_u16 interval;                           /**< in seconds */
+    t_u8 priority;                            /**< User Priority: 0~7, ignored if non-WMM */
+    t_u8 reserved;                            /**< set to 0 */
+    t_u16 frame_len;                          /**< Length of MAC frame payload */
+    t_u8 dest_mac_addr[MLAN_MAC_ADDR_LENGTH]; /**< Destination MAC address */
+    t_u8 src_mac_addr[MLAN_MAC_ADDR_LENGTH];  /**< Source MAC address */
+    t_u8 payload[];                           /**< Payload */
+} MLAN_PACK_END AutoTx_MacFrame_t;
+
+/** MrvlIEtypes_AutoTx_t */
+typedef MLAN_PACK_START struct MrvlIEtypes_AutoTx
+{
+    MrvlIEtypesHeader_t header;          /**< Header */
+    AutoTx_MacFrame_t auto_tx_mac_frame; /**< Auto Tx MAC frame */
+} MLAN_PACK_END MrvlIEtypes_AutoTx_t;
+
+/** HostCmd_DS_802_11_AUTO_TX */
+typedef MLAN_PACK_START struct MAPP_HostCmd_DS_802_11_AUTO_TX
+{
+    /** Action */
+    t_u16 action;                 /* 0 = ACT_GET; 1 = ACT_SET; */
+    MrvlIEtypes_AutoTx_t auto_tx; /**< Auto Tx */
+} MLAN_PACK_END HostCmd_DS_802_11_AUTO_TX;
+
+/** MrvlIEtypes_Auto_Null_Tx_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Auto_Null_Tx_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** bit15:14 unit: 00-s 01-us 10-ms 11-one_shot  bit13-0: interval */
+    t_u16 interval;
+    /** bit7-4: bandwidth. bit3-0: priority, ignored if non-WMM */
+    t_u8 priority;
+    /** Packet index, set to 0 */
+    t_u8 index;
+    /** Set to 0 for auto null tx */
+    t_u8 getTodToAForPkts;
+    /** Length of MAC frame payload */
+    t_u16 frame_len;
+    /** Destination MAC address */
+    t_u8 dest_mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Source MAC address */
+    t_u8 src_mac_addr[MLAN_MAC_ADDR_LENGTH]; /**< Source MAC address */
+    /** '0x00,0x00' for auto null tx */
+    t_u16 frame_body_len;
+} MLAN_PACK_END MrvlIEtypes_Auto_Null_Tx_t;
+
+/** Radio on */
+#define RADIO_ON 0x01
+/** Radio off */
+#define RADIO_OFF 0x00
+
+/** HostCmd_CMD_802_11_RADIO_CONTROL */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_RADIO_CONTROL
+{
+    /** Action */
+    t_u16 action;
+    /** Control */
+    t_u16 control;
+} MLAN_PACK_END HostCmd_DS_802_11_RADIO_CONTROL;
+
+/** MrvlRateScope_t */
+typedef MLAN_PACK_START struct _MrvlRateScope_t
+{
+    /** Header Type */
+    t_u16 type;
+    /** Header Length */
+    t_u16 length;
+    /** Bitmap of HR/DSSS rates */
+    t_u16 hr_dsss_rate_bitmap;
+    /** Bitmap of OFDM rates */
+    t_u16 ofdm_rate_bitmap;
+    /** Bitmap of HT-MCSs allowed for initial rate */
+    t_u16 ht_mcs_rate_bitmap[8];
+    /** VHT MCS rate bitmap */
+    t_u16 vht_mcs_rate_bitmap[8];
+#if CONFIG_11AX
+    /** HE MCS rate bitmap */
+    t_u16 he_mcs_rate_bitmap[8];
+#endif
+} MLAN_PACK_END MrvlRateScope_t;
+
+/** MrvlRateDropControl_t */
+typedef MLAN_PACK_START struct _MrvlRateDropControl_t
+{
+    /** Header Length */
+    t_u16 length;
+    /** Rate Information */
+    t_u32 rate_info[1];
+} MLAN_PACK_END MrvlRateDropControl_t;
+
+/** MrvlRateDropPattern_t */
+typedef MLAN_PACK_START struct _MrvlRateDropPattern_t
+{
+    /** Header Type */
+    t_u16 type;
+    /** Header Length */
+    t_u16 length;
+    /** Rate Drop Mode */
+    t_u32 rate_drop_mode;
+    /* MrvlRateDropControl_t RateDropControl[0]; */
+} MLAN_PACK_END MrvlRateDropPattern_t;
+
+/** MrvlIETypes_rate_setting_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_rate_setting_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Rate Setting */
+    t_u16 rate_setting;
+} MLAN_PACK_END MrvlIETypes_rate_setting_t;
+
+/** HostCmd_DS_TX_RATE_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_TX_RATE_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** Tx Rate Configuration Index */
+    t_u16 cfg_index;
+    /* MrvlRateScope_t RateScope; MrvlRateDropPattern_t RateDrop; */
+} MLAN_PACK_END HostCmd_DS_TX_RATE_CFG;
+
+#if CONFIG_WIFI_TX_PER_TRACK
+#define TLV_TYPE_TX_PER_TRACK   (PROPRIETARY_TLV_BASE_ID + 338)
+#define EVENT_PER_STATUS_REPORT 0x94
+typedef MLAN_PACK_START struct _HostCmd_DS_TX_RX_PKT_STATS
+{
+    /** Enable or disable */
+    t_u8 enable;
+    /** Action */
+    t_u16 action;
+} MLAN_PACK_END HostCmd_DS_TX_RX_PKT_STATS;
+
+typedef MLAN_PACK_START struct _MrvlTxPerTrackInfo_t
+{
+    /** Header Type */
+    t_u16 type;
+    /** Header Length */
+    t_u16 length;
+    /** Tx stat check period */
+    t_u8 tx_stat_check_period;
+    /** Tx stat check ratio */
+    t_u8 tx_stat_check_ratio;
+    /** Tx stat check packet number */
+    t_u16 tx_stat_check_num;
+} MLAN_PACK_END MrvlTxPerTrackInfo_t;
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+/** TX and RX histogram statistic parameters*/
+typedef MLAN_PACK_START struct _HostCmd_DS_TX_RX_HISTOGRAM
+{
+    /** Enable or disable get tx/rx histogram statistic */
+    t_u8 enable;
+    /** Choose to get TX, RX or both histogram statistic */
+    t_u16 action;
+} MLAN_PACK_END HostCmd_DS_TX_RX_HISTOGRAM;
+#endif
+
+#if CONFIG_RX_ABORT_CFG
+typedef MLAN_PACK_START struct _HostCmd_DS_RX_ABORT_CFG
+{
+    t_u16 action;
+    /** Enable or disable */
+    t_u8 enable;
+    /** RSSI threshold */
+    t_s8 rssi_threshold;
+} MLAN_PACK_END HostCmd_DS_RX_ABORT_CFG;
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+typedef MLAN_PACK_START struct _HostCmd_DS_RX_ABORT_CFG_EXT
+{
+    /** Action */
+    t_u16 action;
+    /** Enable/disable dyn rx abort on weak pkt rssi */
+    t_u8 enable;
+    /** specify rssi margin */
+    t_s8 rssi_margin;
+    /** specify ceil rssi threshold */
+    t_s8 ceil_rssi_threshold;
+    /** specify floor rssi threshold */
+    t_s8 floor_rssi_threshold;
+    /** current dynamic rssi threshold */
+    t_s8 current_dynamic_rssi_threshold;
+    /** rssi config: default or user configured */
+    t_u8 rssi_default_config;
+    /** EDMAC status */
+    t_u8 edmac_enable;
+} MLAN_PACK_END HostCmd_DS_RX_ABORT_CFG_EXT;
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+typedef MLAN_PACK_START struct _HostCmd_DS_CCK_DESENSE_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** cck desense mode: 0:disable 1:normal 2:dynamic */
+    t_u16 mode;
+    /** specify rssi margin */
+    t_s8 margin;
+    /** specify ceil rssi threshold */
+    t_s8 ceil_thresh;
+    /** cck desense "on" interval count */
+    t_u8 num_on_intervals;
+    /** cck desense "off" interval count */
+    t_u8 num_off_intervals;
+} MLAN_PACK_END HostCmd_DS_CCK_DESENSE_CFG;
+#endif
+
+/** Power_Group_t */
+typedef MLAN_PACK_START struct _Power_Group_t
+{
+    /** Modulation Class */
+    t_u8 modulation_class;
+    /** MCS Code or Legacy RateID */
+    t_u8 first_rate_code;
+    /** MCS Code or Legacy RateID */
+    t_u8 last_rate_code;
+    /** Power Adjustment Step */
+    t_s8 power_step;
+    /** Minimal Tx Power Level [dBm] */
+    t_s8 power_min;
+    /** Maximal Tx Power Level [dBm] */
+    t_s8 power_max;
+    /** 0: HTBW20, 1: HTBW40 */
+    t_u8 ht_bandwidth;
+    /** Reserved */
+    t_u8 reserved;
+} MLAN_PACK_END Power_Group_t;
+
+/** MrvlTypes_Power_Group_t */
+typedef MLAN_PACK_START struct _MrvlTypes_Power_Group_t
+{
+    /** Header Type */
+    t_u16 type;
+    /** Header Length */
+    t_u16 length;
+    /* Power_Group_t PowerGroups */
+} MLAN_PACK_END MrvlTypes_Power_Group_t;
+
+/** HostCmd_CMD_TXPWR_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_TXPWR_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** Power group configuration index */
+    t_u16 cfg_index;
+    /** Power group configuration mode */
+    t_u32 mode;
+    /* MrvlTypes_Power_Group_t PowerGrpCfg[0] */
+} MLAN_PACK_END HostCmd_DS_TXPWR_CFG;
+
+/** HostCmd_CMD_802_11_RF_TX_POWER */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_RF_TX_POWER
+{
+    /** Action */
+    t_u16 action;
+    /** Current power level */
+    t_u16 current_level;
+    /** Maximum power */
+    t_u8 max_power;
+    /** Minimum power */
+    t_u8 min_power;
+} MLAN_PACK_END HostCmd_DS_802_11_RF_TX_POWER;
+
+/** Connection type infra */
+#define CONNECTION_TYPE_INFRA 0
+/** Connection type adhoc */
+#define CONNECTION_TYPE_ADHOC 1
+/** HostCmd_DS_SET_BSS_MODE */
+typedef MLAN_PACK_START struct _HostCmd_DS_SET_BSS_MODE
+{
+    /** connection type */
+    t_u8 con_type;
+} MLAN_PACK_END HostCmd_DS_SET_BSS_MODE;
+
+/** HostCmd_DS_REMAIN_ON_CHANNEL */
+typedef MLAN_PACK_START struct _HostCmd_DS_REMAIN_ON_CHANNEL
+{
+    /** Action 0-GET, 1-SET, 4 CLEAR*/
+    t_u16 action;
+    /** Not used set to zero */
+    t_u8 status;
+    /** Not used set to zero */
+    t_u8 reserved;
+    /** Band cfg */
+    t_u8 bandcfg;
+    /** channel */
+    t_u8 channel;
+    /** remain time: Unit ms*/
+    t_u32 remain_period;
+} MLAN_PACK_END HostCmd_DS_REMAIN_ON_CHANNEL;
+
+
+
+/**
+ * @brief Structure used internally in the wlan driver to configure a scan.
+ *
+ * Sent to the command process module to configure the firmware
+ *   scan command prepared by wlan_cmd_802_11_scan.
+ *
+ * @sa wlan_scan_networks
+ *
+ */
+typedef MLAN_PACK_START struct _wlan_scan_cmd_config
+{
+    /**
+     *  BSS Type to be sent in the firmware command
+     *
+     *  Field can be used to restrict the types of networks returned in the
+     *    scan.  Valid settings are:
+     *
+     *   - MLAN_SCAN_MODE_BSS  (infrastructure)
+     *   - MLAN_SCAN_MODE_IBSS (adhoc)
+     *   - MLAN_SCAN_MODE_ANY  (unrestricted, adhoc and infrastructure)
+     */
+    t_u8 bss_mode;
+
+    /**
+     *  Specific BSSID used to filter scan results in the firmware
+     */
+    t_u8 specific_bssid[MLAN_MAC_ADDR_LENGTH];
+
+    /**
+     *  Length of TLVs sent in command starting at tlvBuffer
+     */
+    t_u32 tlv_buf_len;
+
+    /**
+     *  SSID TLV(s) and ChanList TLVs to be sent in the firmware command
+     *
+     *  TLV_TYPE_CHANLIST, MrvlIEtypes_ChanListParamSet_t
+     *  TLV_TYPE_SSID, MrvlIEtypes_SsIdParamSet_t
+     */
+    t_u8 tlv_buf[1]; /* SSID TLV(s) and ChanList TLVs are stored
+                        here */
+} MLAN_PACK_END wlan_scan_cmd_config;
+
+/**
+ *  Sructure to retrieve the scan table
+ */
+typedef MLAN_PACK_START struct
+{
+    /**
+     *  - Zero based scan entry to start retrieval in command request
+     *  - Number of scans entries returned in command response
+     */
+    t_u32 scan_number;
+    /**
+     * Buffer marker for multiple wlan_ioctl_get_scan_table_entry structures.
+     *   Each struct is padded to the nearest 32 bit boundary.
+     */
+    t_u8 scan_table_entry_buf[1];
+} MLAN_PACK_END wlan_get_scan_table_info;
+
+/** Generic structure defined for parsing WPA/RSN IEs for GTK/PTK OUIs */
+typedef MLAN_PACK_START struct
+{
+    /** Group key oui */
+    t_u8 GrpKeyOui[4];
+    /** Number of PTKs */
+    t_u8 PtkCnt[2];
+    /** Ptk body starts here */
+    t_u8 PtkBody[4];
+} MLAN_PACK_END IEBody;
+
+/*
+ * This scan handle Country Information IE(802.11d compliant)
+ * Define data structure for HostCmd_CMD_802_11_SCAN
+ */
+/** HostCmd_DS_802_11_SCAN */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SCAN
+{
+    /** BSS mode */
+    t_u8 bss_mode;
+    /** BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** TLV buffer */
+    t_u8 tlv_buffer[1];
+    /** MrvlIEtypes_SsIdParamSet_t      SsIdParamSet;
+     *  MrvlIEtypes_ChanListParamSet_t  ChanListParamSet;
+     *  MrvlIEtypes_RatesParamSet_t     OpRateSet;
+     */
+} MLAN_PACK_END HostCmd_DS_802_11_SCAN;
+
+#if CONFIG_EXT_SCAN_SUPPORT
+/*
+ * This scan handle Country Information IE(802.11d compliant)
+ * Define data structure for HostCmd_CMD_802_11_SCAN_EXT
+ */
+/** HostCmd_DS_802_11_SCAN_EXT */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SCAN_EXT
+{
+    /** Reserved */
+    t_u32 reserved;
+    /** TLV buffer */
+    t_u8 tlv_buffer[1];
+    /** MrvlIEtypes_Bssid_List_t            BssIdList;
+     *  MrvlIEtypes_SsIdParamSet_t          SSIDParamSet;
+     *  MrvlIEtypes_ChanListParamSet_t      ChanListParamSet;
+     *  MrvlIEtypes_RatesParamSet_t         OpRateSet;
+     *  MrvlIEtypes_NumProbes_t             NumProbes;
+     *  MrvlIEtypes_WildCardSsIdParamSet_t  WildCardSSIDParamSet;
+     */
+} MLAN_PACK_END HostCmd_DS_802_11_SCAN_EXT;
+
+typedef MLAN_PACK_START struct _MrvlIEtypes_Bss_Scan_Rsp_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** BSSID of the BSS descriptor */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Beacon/Probe response buffer */
+    t_u8 frame_body[1];
+} MLAN_PACK_END MrvlIEtypes_Bss_Scan_Rsp_t;
+
+typedef MLAN_PACK_START struct _MrvlIEtypes_Bss_Scan_Info_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** RSSI for scan entry */
+    t_s16 rssi;
+    /** Channel ANPI */
+    t_s16 anpi;
+    /** Channel load (parts per 255) */
+    t_u8 cca_busy_fraction;
+    /** Band */
+    t_u8 band;
+    /** Channel */
+    t_u8 channel;
+    /** Reserved */
+    t_u8 reserved;
+    /** TSF data */
+    t_u64 tsf;
+} MLAN_PACK_END MrvlIEtypes_Bss_Scan_Info_t;
+#endif /* CONFIG_EXT_SCAN_SUPPORT */
+
+/** HostCmd_DS_RX_MGMT_IND */
+typedef MLAN_PACK_START struct _HostCmd_DS_RX_MGMT_IND
+{
+    /** Action */
+    t_u16 action;
+    /** Mgmt frame subtype mask */
+    t_u32 mgmt_subtype_mask;
+    /** Data frame subtype mask */
+    t_u32 data_subtype_mask;
+} MLAN_PACK_END HostCmd_DS_RX_MGMT_IND;
+
+/** HostCmd_DS_802_11_SCAN_RSP */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SCAN_RSP
+{
+    /** Size of BSS descriptor */
+    t_u16 bss_descript_size;
+    /** Numner of sets */
+    t_u8 number_of_sets;
+    /** BSS descriptor and TLV buffer */
+    t_u8 bss_desc_and_tlv_buffer[1];
+} MLAN_PACK_END HostCmd_DS_802_11_SCAN_RSP;
+
+/** HostCmd_DS_802_11_BG_SCAN_CONFIG */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_BG_SCAN_CONFIG
+{
+    /** action */
+    t_u16 action;
+    /** 0: disable, 1: enable */
+    t_u8 enable;
+    /** bss type */
+    t_u8 bss_type;
+    /** num of channel per scan */
+    t_u8 chan_per_scan;
+    /** reserved field */
+    t_u8 reserved;
+    /** reserved field */
+    t_u16 reserved1;
+    /** interval between consecutive scans */
+    t_u32 scan_interval;
+    /** reserved field */
+    t_u32 reserved2;
+    /** condition to trigger report to host */
+    t_u32 report_condition;
+    /** reserved field */
+    t_u16 reserved3;
+} MLAN_PACK_END HostCmd_DS_802_11_BG_SCAN_CONFIG;
+
+/** HostCmd_DS_802_11_BG_SCAN_QUERY */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_BG_SCAN_QUERY
+{
+    /** Flush */
+    t_u8 flush;
+} MLAN_PACK_END HostCmd_DS_802_11_BG_SCAN_QUERY;
+
+/** HostCmd_DS_802_11_BG_SCAN_QUERY_RSP */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_BG_SCAN_QUERY_RSP
+{
+    /** Report condition */
+    t_u32 report_condition;
+    /** Scan response */
+    HostCmd_DS_802_11_SCAN_RSP scan_resp;
+} MLAN_PACK_END HostCmd_DS_802_11_BG_SCAN_QUERY_RSP;
+
+/** MrvlIEtypes_StartLater_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_StartLater_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /* 0 - BGScan start immediately, 1 - BGScan will start later after "Scan
+       Interval" */
+    t_u16 value;
+} MLAN_PACK_END MrvlIEtypes_StartLater_t;
+
+/** MrvlIEtypes_RepeatCount_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_RepeatCount_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /* Repeat count */
+    t_u16 repeat_count;
+} MLAN_PACK_END MrvlIEtypes_RepeatCount_t;
+
+/** MrvlIEtypes_DomainParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_DomainParamSet
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Country code */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /** Set of subbands */
+    IEEEtypes_SubbandSet_t sub_band[1];
+} MLAN_PACK_END MrvlIEtypes_DomainParamSet_t;
+
+/** HostCmd_DS_802_11D_DOMAIN_INFO */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11D_DOMAIN_INFO
+{
+    /** Action */
+    t_u16 action;
+    /** Domain parameter set */
+    MrvlIEtypes_DomainParamSet_t domain;
+} MLAN_PACK_END HostCmd_DS_802_11D_DOMAIN_INFO;
+
+/** HostCmd_DS_802_11D_DOMAIN_INFO_RSP */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11D_DOMAIN_INFO_RSP
+{
+    /** Action */
+    t_u16 action;
+    /** Domain parameter set */
+    MrvlIEtypes_DomainParamSet_t domain;
+} MLAN_PACK_END HostCmd_DS_802_11D_DOMAIN_INFO_RSP;
+
+/** HostCmd_DS_11N_ADDBA_REQ */
+typedef MLAN_PACK_START struct _HostCmd_DS_11N_ADDBA_REQ
+{
+    /** Result of the ADDBA Request Operation */
+    t_u8 add_req_result;
+    /** Peer MAC address */
+    t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Dialog Token */
+    t_u8 dialog_token;
+    /** Block Ack Parameter Set */
+    t_u16 block_ack_param_set;
+    /** Block Act Timeout Value */
+    t_u16 block_ack_tmo;
+    /** Starting Sequence Number */
+    t_u16 ssn;
+} MLAN_PACK_END HostCmd_DS_11N_ADDBA_REQ;
+
+/** HostCmd_DS_11N_ADDBA_RSP */
+typedef MLAN_PACK_START struct _HostCmd_DS_11N_ADDBA_RSP
+{
+    /** Result of the ADDBA Response Operation */
+    t_u8 add_rsp_result;
+    /** Peer MAC address */
+    t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Dialog Token */
+    t_u8 dialog_token;
+    /** Status Code */
+    t_u16 status_code;
+    /** Block Ack Parameter Set */
+    t_u16 block_ack_param_set;
+    /** Block Act Timeout Value */
+    t_u16 block_ack_tmo;
+    /** Starting Sequence Number */
+    t_u16 ssn;
+} MLAN_PACK_END HostCmd_DS_11N_ADDBA_RSP;
+
+/** HostCmd_DS_11N_DELBA */
+typedef MLAN_PACK_START struct _HostCmd_DS_11N_DELBA
+{
+    /** Result of the ADDBA Request Operation */
+    t_u8 del_result;
+    /** Peer MAC address */
+    t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Delete Block Ack Parameter Set */
+    t_u16 del_ba_param_set;
+    /** Reason Code sent for DELBA */
+    t_u16 reason_code;
+    /** Reserved */
+    t_u8 reserved;
+} MLAN_PACK_END HostCmd_DS_11N_DELBA;
+
+/** HostCmd_DS_11N_BATIMEOUT */
+typedef MLAN_PACK_START struct _HostCmd_DS_11N_BATIMEOUT
+{
+    /** TID */
+    t_u8 tid;
+    /** Peer MAC address */
+    t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Delete Block Ack Parameter Set */
+    t_u8 origninator;
+} MLAN_PACK_END HostCmd_DS_11N_BATIMEOUT;
+
+/** HostCmd_DS_11N_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_11N_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** HTTxCap */
+    t_u16 ht_tx_cap;
+    /** HTTxInfo */
+    t_u16 ht_tx_info;
+    /** Misc configuration */
+    t_u16 misc_config;
+} MLAN_PACK_END HostCmd_DS_11N_CFG;
+
+#define VHT_MCS_SET_LEN 8
+
+/** HostCmd_DS_11AC_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_11AC_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** BandConfig */
+    t_u8 band_config;
+    /** Misc Configuration */
+    t_u8 misc_config;
+    /** VHT Capability Info */
+    t_u32 vht_cap_info;
+    /** VHT Support MCS Set */
+    t_u8 vht_supp_mcs_set[VHT_MCS_SET_LEN];
+} MLAN_PACK_END HostCmd_DS_11AC_CFG;
+
+#if CONFIG_11AX
+/** HostCmd_DS_11AX_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_11AX_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** BandConfig */
+    t_u8 band_config;
+    /** TLV for HE capability or HE operation */
+    t_u8 val[];
+} MLAN_PACK_END HostCmd_DS_11AX_CFG;
+
+/** HostCmd_DS_11AX_CMD_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_11AX_CMD_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** CMD_SUBID */
+    t_u16 sub_id;
+    /** TLV or value for cmd */
+    t_u8 val[];
+} MLAN_PACK_END HostCmd_DS_11AX_CMD_CFG;
+
+#if CONFIG_11AX_TWT
+/** Type definition of hostcmd_twt_setup */
+typedef MLAN_PACK_START struct _hostcmd_twt_setup
+{
+    /** Implicit, 0: TWT session is explicit, 1: Session is implicit */
+    t_u8 implicit;
+    /** Announced, 0: Unannounced, 1: Announced TWT */
+    t_u8 announced;
+    /** Trigger Enabled, 0: Non-Trigger enabled, 1: Trigger enabled TWT */
+    t_u8 trigger_enabled;
+    /** TWT Information Disabled, 0: TWT info enabled, 1: TWT info disabled */
+    t_u8 twt_info_disabled;
+    /** Negotiation Type, 0: Future Individual TWT SP start time, 1: Next
+     * Wake TBTT time */
+    t_u8 negotiation_type;
+    /** TWT Wakeup Duration, time after which the TWT requesting STA can
+     * transition to doze state */
+    t_u8 twt_wakeup_duration;
+    /** Flow Identifier. Range: [0-7]*/
+    t_u8 flow_identifier;
+    /** Hard Constraint, 0: FW can tweak the TWT setup parameters if it is
+     *rejected by AP.
+     ** 1: Firmware should not tweak any parameters. */
+    t_u8 hard_constraint;
+    /** TWT Exponent, Range: [0-63] */
+    t_u8 twt_exponent;
+    /** TWT Mantissa Range: [0-sizeof(UINT16)] */
+    t_u16 twt_mantissa;
+    /** TWT Request Type, 0: REQUEST_TWT, 1: SUGGEST_TWT*/
+    t_u8 twt_request;
+    /** TWT Setup State. Set to 0 by driver, filled by FW in response*/
+    t_u8 twt_setup_state;
+    /** Reserved, set to 0. */
+    t_u8 reserved[2];
+} MLAN_PACK_END hostcmd_twt_setup, *phostcmd_twt_setup;
+
+/** Type definition of hostcmd_twt_teardown */
+typedef MLAN_PACK_START struct _hostcmd_twt_teardown
+{
+    /** TWT Flow Identifier. Range: [0-7] */
+    t_u8 flow_identifier;
+    /** Negotiation Type. 0: Future Individual TWT SP start time, 1: Next
+     * Wake TBTT time */
+    t_u8 negotiation_type;
+    /** Tear down all TWT. 1: To teardown all TWT, 0 otherwise */
+    t_u8 teardown_all_twt;
+    /** TWT Teardown State. Set to 0 by driver, filled by FW in response */
+    t_u8 twt_teardown_state;
+    /** Reserved, set to 0. */
+    t_u8 reserved[3];
+} MLAN_PACK_END hostcmd_twt_teardown, *phostcmd_twt_teardown;
+
+/** Type definition of hostcmd_twt_report */
+typedef MLAN_PACK_START struct _hostcmd_twt_report
+{
+    /** TWT report type, 0: BTWT id */
+    t_u8 type;
+    /** TWT report length of value in data */
+    t_u8 length;
+    t_u8 reserve[2];
+    /** TWT report payload for FW response to fill */
+    t_u8 data[36];
+} MLAN_PACK_END hostcmd_twt_report, *phostcmd_twt_report;
+
+/** HostCmd_DS_TWT_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_TWT_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** CMD_SUBID */
+    t_u16 sub_id;
+    /** TWT Setup/Teardown configuration parameters */
+    union
+    {
+        /** TWT Setup config for Sub ID: MLAN_11AX_TWT_SETUP_SUBID */
+        hostcmd_twt_setup twt_setup;
+        /** TWT Teardown config for Sub ID: MLAN_11AX_TWT_TEARDOWN_SUBID */
+        hostcmd_twt_teardown twt_teardown;
+        /** TWT report for Sub ID: MLAN_11AX_TWT_REPORT_SUBID */
+        hostcmd_twt_report twt_report;
+    } param;
+} MLAN_PACK_END HostCmd_DS_TWT_CFG;
+#endif /* CONFIG_11AX_TWT */
+
+#if CONFIG_MMSF
+/** Type definition of hostcmd_mmsf_cfg*/
+typedef MLAN_PACK_START struct _HostCmd_DS_MMSF_CFG
+{
+    /** 1 - set; 0 - get*/
+    t_u16 action;
+    /** sub-command id*/
+    t_u16 sub_id;
+    /** 1 - enable MMSF; 0 - disable MMSF */
+    t_u8 enableMMSF;
+    /** Density value */
+    t_u8 ampduDensity;
+    /** MMSF value */
+    t_u8 ampduMMSF;
+} MLAN_PACK_END HostCmd_DS_MMSF_CFG;
+#endif
+#endif
+
+#if CONFIG_WIFI_RECOVERY
+/** Type definition of HostCmd_DS_TMRC_CFG*/
+typedef MLAN_PACK_START struct _HostCmd_DS_TMRC_CFG
+{
+    /** 1 - set; 0 - get*/
+    t_u16 action;
+    /** sub-command id*/
+    t_u16 sub_id;
+} MLAN_PACK_END HostCmd_DS_TMRC_CFG;
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+/** MrvlIEtypes_GPIO_TSF_LATCH_CONFIG*/
+typedef MLAN_PACK_START struct _MrvlIEtypes_GPIO_TSF_LATCH_CONFIG
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /**clock sync Mode */
+    t_u8 clock_sync_mode;
+    /**clock sync Role */
+    t_u8 clock_sync_Role;
+    /**clock sync GPIO Pin Number */
+    t_u8 clock_sync_gpio_pin_number;
+    /**clock sync GPIO Level or Toggle */
+    t_u8 clock_sync_gpio_level_toggle;
+    /**clock sync GPIO Pulse Width */
+    t_u16 clock_sync_gpio_pulse_width;
+} MLAN_PACK_END MrvlIEtypes_GPIO_TSF_LATCH_CONFIG;
+
+/** MrvlIEtypes_GPIO_TSF_LATCH_REPORT */
+typedef MLAN_PACK_START struct _MrvlIEtypes_GPIO_TSF_LATCH_REPORT
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /**get tsf info format */
+    t_u16 tsf_format;
+    /**tsf info */
+    t_u16 tsf_info;
+    /**tsf */
+    t_u64 tsf;
+    /**Positive or negative offset in microsecond from Beacon TSF to GPIO toggle TSF  */
+    t_s32 tsf_offset;
+} MLAN_PACK_END MrvlIEtypes_GPIO_TSF_LATCH_REPORT;
+
+/** HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG */
+typedef MLAN_PACK_START struct _HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG
+{
+    /** Action 0-GET, 1-SET */
+    t_u16 action;
+    /** MrvlIEtypes_GPIO_TSF_LATCH_CONFIG
+     *  MrvlIEtypes_GPIO_TSF_LATCH_REPORT
+     */
+    t_u8 tlv_buf[];
+} MLAN_PACK_END HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+/** HostCmd_DS_TXBUF_CFG*/
+typedef MLAN_PACK_START struct _HostCmd_DS_TXBUF_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** Buffer Size */
+    t_u16 buff_size;
+    /** End Port_for Multiport */
+    t_u16 mp_end_port;
+    /** Reserved */
+    t_u16 reserved3;
+} MLAN_PACK_END HostCmd_DS_TXBUF_CFG;
+
+/** HostCmd_DS_AMSDU_AGGR_CTRL */
+typedef MLAN_PACK_START struct _HostCmd_DS_AMSDU_AGGR_CTRL
+{
+    /** Action */
+    t_u16 action;
+    /** Enable */
+    t_u16 enable;
+    /** Get the current Buffer Size valid */
+    t_u16 curr_buf_size;
+} MLAN_PACK_END HostCmd_DS_AMSDU_AGGR_CTRL;
+
+/** HostCmd_DS_ECL_SYSTEM_CLOCK_CONFIG */
+typedef MLAN_PACK_START struct _HostCmd_DS_ECL_SYSTEM_CLOCK_CONFIG
+{
+    /** Action */
+    t_u16 action;
+    /** Current system clock */
+    t_u16 cur_sys_clk;
+    /** Clock type */
+    t_u16 sys_clk_type;
+    /** Length of clocks */
+    t_u16 sys_clk_len;
+    /** System clocks */
+    t_u16 sys_clk[16];
+} MLAN_PACK_END HostCmd_DS_ECL_SYSTEM_CLOCK_CONFIG;
+
+/** MrvlIEtypes_WmmParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_WmmParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** WMM IE */
+    t_u8 wmm_ie[1];
+} MLAN_PACK_END MrvlIEtypes_WmmParamSet_t;
+
+/** MrvlIEtypes_WmmQueueStatus_t */
+typedef MLAN_PACK_START struct
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Queue index */
+    t_u8 queue_index;
+    /** Disabled flag */
+    t_u8 disabled;
+    /** Medium time allocation in 32us units*/
+    t_u16 medium_time;
+    /** Flow required flag */
+    t_u8 flow_required;
+    /** Flow created flag */
+    t_u8 flow_created;
+    /** Reserved */
+    t_u32 reserved;
+} MLAN_PACK_END MrvlIEtypes_WmmQueueStatus_t;
+
+/** Size of a TSPEC.  Used to allocate necessary buffer space in commands */
+#define WMM_TSPEC_SIZE 63
+
+/** Maximum number of AC QOS queues available in the driver/firmware */
+#define MAX_AC_QUEUES 4
+
+/** Extra IE bytes allocated in messages for appended IEs after a TSPEC */
+#define WMM_ADDTS_EXTRA_IE_BYTES 256
+
+/** Extra TLV bytes allocated in messages for configuring WMM Queues */
+#define WMM_QUEUE_CONFIG_EXTRA_TLV_BYTES 64
+
+/** Number of bins in the histogram for the HostCmd_DS_WMM_QUEUE_STATS */
+#define WMM_STATS_PKTS_HIST_BINS 7
+
+/**
+ *  @brief Firmware command structure to retrieve the firmware WMM status.
+ *
+ *  Used to retrieve the status of each WMM AC Queue in TLV
+ *    format (MrvlIEtypes_WmmQueueStatus_t) as well as the current WMM
+ *    parameter IE advertised by the AP.
+ *
+ *  Used in response to a EVENT_WMM_STATUS_CHANGE event signaling
+ *    a QOS change on one of the ACs or a change in the WMM Parameter in
+ *    the Beacon.
+ *
+ *  TLV based command, byte arrays used for max sizing purpose. There are no
+ *    arguments sent in the command, the TLVs are returned by the firmware.
+ */
+typedef MLAN_PACK_START struct
+{
+    /** Queue status TLV */
+    t_u8 queue_status_tlv[sizeof(MrvlIEtypes_WmmQueueStatus_t) * MAX_AC_QUEUES];
+    /** WMM parameter TLV */
+    t_u8 wmm_param_tlv[sizeof(IEEEtypes_WmmParameter_t) + 2];
+} MLAN_PACK_END HostCmd_DS_WMM_GET_STATUS;
+
+/**
+ *  @brief Command structure for the HostCmd_CMD_WMM_ADDTS_REQ firmware command
+ */
+typedef MLAN_PACK_START struct
+{
+    mlan_cmd_result_e command_result;                  /**< Command result */
+    t_u32 timeout_ms;                                  /**< Timeout value in milliseconds */
+    t_u8 dialog_token;                                 /**< Dialog token */
+    t_u8 ieee_status_code;                             /**< IEEE status code */
+    t_u8 tspec_data[WMM_TSPEC_SIZE];                   /**< TSPEC data */
+    t_u8 addts_extra_ie_buf[WMM_ADDTS_EXTRA_IE_BYTES]; /**< Extra IE buffer */
+} MLAN_PACK_END HostCmd_DS_WMM_ADDTS_REQ;
+
+/**
+ *  @brief Command structure for the HostCmd_CMD_WMM_DELTS_REQ firmware command
+ */
+typedef MLAN_PACK_START struct
+{
+    mlan_cmd_result_e command_result; /**< Command result */
+    t_u8 dialog_token;                /**< Dialog token */
+    t_u8 ieee_reason_code;            /**< IEEE reason code */
+    t_u8 tspec_data[WMM_TSPEC_SIZE];  /**< TSPEC data */
+} MLAN_PACK_END HostCmd_DS_WMM_DELTS_REQ;
+
+/**
+ *  @brief Command structure for the HostCmd_CMD_WMM_QUEUE_CONFIG firmware cmd
+ *
+ *  Set/Get/Default the Queue parameters for a specific AC in the firmware.
+ */
+typedef MLAN_PACK_START struct
+{
+    mlan_wmm_queue_config_action_e action; /**< Set, Get, or Default */
+    mlan_wmm_ac_e access_category;         /**< WMM_AC_BK(0) to WMM_AC_VO(3) */
+    /** @brief MSDU lifetime expiry per 802.11e
+     *
+     *   - Ignored if 0 on a set command
+     *   - Set to the 802.11e specified 500 TUs when defaulted
+     */
+    t_u16 msdu_lifetime_expiry;
+    t_u8 tlv_buffer[WMM_QUEUE_CONFIG_EXTRA_TLV_BYTES]; /**< Not supported */
+} MLAN_PACK_END HostCmd_DS_WMM_QUEUE_CONFIG;
+
+/**
+ *  @brief Command structure for the HostCmd_CMD_WMM_QUEUE_STATS firmware cmd
+ *
+ *  Turn statistical collection on/off for a given AC or retrieve the
+ *    accumulated stats for an AC and clear them in the firmware.
+ */
+typedef MLAN_PACK_START struct
+{
+    mlan_wmm_queue_stats_action_e action; /**< Start, Stop, or Get */
+    t_u8 select_is_userpri : 1; /**< Set if select_bin is UP, Clear for AC */
+    t_u8 select_bin : 7;        /**< WMM_AC_BK(0) to WMM_AC_VO(3), or TID */
+    t_u16 pkt_count;       /**< Number of successful packets transmitted */
+    t_u16 pkt_loss;        /**< Packets lost; not included in pktCount */
+    t_u32 avg_queue_delay; /**< Average Queue delay in microsec */
+    t_u32 avg_tx_delay;    /**< Average Transmission delay in microsec */
+    t_u16 used_time;       /**< Calc used time - units of 32 microsec */
+    t_u16 policed_time;    /**< Calc policed time - units of 32 microsec */
+    /** @brief Queue Delay Histogram; number of packets per queue delay range
+     *
+     *  [0] -  0ms <= delay < 5ms
+     *  [1] -  5ms <= delay < 10ms
+     *  [2] - 10ms <= delay < 20ms
+     *  [3] - 20ms <= delay < 30ms
+     *  [4] - 30ms <= delay < 40ms
+     *  [5] - 40ms <= delay < 50ms
+     *  [6] - 50ms <= delay < msduLifetime (TUs)
+     */
+    t_u16 delay_histogram[WMM_STATS_PKTS_HIST_BINS];
+    /** Reserved */
+    t_u16 reserved_1;
+} MLAN_PACK_END HostCmd_DS_WMM_QUEUE_STATS;
+
+/**
+ *  @brief Command structure for the HostCmd_CMD_WMM_TS_STATUS firmware cmd
+ *
+ *  Query the firmware to get the status of the WMM Traffic Streams
+ */
+typedef MLAN_PACK_START struct
+{
+    /** TSID: Range: 0->7 */
+    t_u8 tid;
+    /** TSID specified is valid */
+    t_u8 valid;
+    /** AC TSID is active on */
+    t_u8 access_category;
+    /** UP specified for the TSID */
+    t_u8 user_priority;
+    /** Power save mode for TSID: 0 (legacy), 1 (UAPSD) */
+    t_u8 psb;
+    /** Uplink(1), Downlink(2), Bidirectional(3) */
+    t_u8 flow_dir;
+    /** Medium time granted for the TSID */
+    t_u16 medium_time;
+} MLAN_PACK_END HostCmd_DS_WMM_TS_STATUS;
+
+/** Firmware status for a specific AC */
+typedef MLAN_PACK_START struct
+{
+    /** Disabled flag */
+    t_u8 disabled;
+    /** Flow required flag */
+    t_u8 flow_required;
+    /** Flow created flag */
+    t_u8 flow_created;
+} MLAN_PACK_END WmmAcStatus_t;
+
+/**  Local Power Capability */
+typedef MLAN_PACK_START struct _MrvlIEtypes_PowerCapability_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Minmum power */
+    t_s8 min_power;
+    /** Maximum power */
+    t_s8 max_power;
+} MLAN_PACK_END MrvlIEtypes_PowerCapability_t;
+
+/** HT Capabilities element */
+typedef MLAN_PACK_START struct _MrvlIETypes_HTCap_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** HTCap struct */
+    HTCap_t ht_cap;
+} MLAN_PACK_END MrvlIETypes_HTCap_t;
+
+/** HT Information element */
+typedef MLAN_PACK_START struct _MrvlIETypes_HTInfo_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** HTInfo struct */
+    HTInfo_t ht_info;
+} MLAN_PACK_END MrvlIETypes_HTInfo_t;
+
+/** 20/40 BSS Coexistence element */
+typedef MLAN_PACK_START struct _MrvlIETypes_2040BSSCo_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** BSSCo2040_t struct */
+    BSSCo2040_t bss_co_2040;
+} MLAN_PACK_END MrvlIETypes_2040BSSCo_t;
+
+/** Extended Capabilities element */
+typedef MLAN_PACK_START struct _MrvlIETypes_ExtCap_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** ExtCap_t struct */
+    ExtCap_t ext_cap;
+} MLAN_PACK_END MrvlIETypes_ExtCap_t;
+
+/** Overlapping BSS Scan Parameters element */
+typedef MLAN_PACK_START struct _MrvlIETypes_OverlapBSSScanParam_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** OBSSScanParam_t struct */
+    OBSSScanParam_t obss_scan_param;
+} MLAN_PACK_END MrvlIETypes_OverlapBSSScanParam_t;
+
+/** Set of MCS values that STA desires to use within the BSS */
+typedef MLAN_PACK_START struct _MrvlIETypes_HTOperationalMCSSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** Bitmap indicating MCSs that STA desires to use within the BSS */
+    t_u8 ht_operational_mcs_bitmap[16];
+} MLAN_PACK_END MrvlIETypes_HTOperationalMCSSet_t;
+
+/** VHT Capabilities element */
+typedef MLAN_PACK_START struct _MrvlIETypes_VHTCap_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** VHTCap struct */
+    VHT_capa_t vht_cap;
+} MLAN_PACK_END MrvlIETypes_VHTCap_t;
+
+/** VHT Operations IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_VHTOprat_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** Channel width */
+    t_u8 chan_width;
+    /** Channel center frequency 1 */
+    t_u8 chan_center_freq_1;
+    /** Channel center frequency 2 */
+    t_u8 chan_center_freq_2;
+    /** Basic MCS set map, each 2 bits stands for a Nss */
+    t_u16 basic_MCS_map;
+} MLAN_PACK_END MrvlIETypes_VHTOprat_t;
+
+/** VHT Transmit Power Envelope IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_VHTtxpower_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** Maximum tx power */
+    t_u8 max_tx_power;
+    /** Channel center frequency */
+    t_u8 chan_center_freq;
+    /** Channel width */
+    t_u8 chan_width;
+} MLAN_PACK_END MrvlIETypes_VHTtxpower_t;
+
+/** Extended Power Constraint IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_ExtPwerCons_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** channel width */
+    t_u8 chan_width;
+    /** local power constraint */
+    t_u8 local_power_cons;
+} MLAN_PACK_END MrvlIETypes_ExtPwerCons_t;
+
+/** Extended BSS Load IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_ExtBSSload_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** MIMO Capability count */
+    t_u8 MU_MIMO_capa_count;
+    /** Stream under utilization */
+    t_u8 stream_underutilization;
+    /** VHT40 util */
+    t_u8 VHT40_util;
+    /** VHT80 util */
+    t_u8 VHT80_util;
+    /** VHT160 util */
+    t_u8 VHT160_util;
+} MLAN_PACK_END MrvlIETypes_ExtBSSload_t;
+
+/** Quiet Channel IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_QuietChan_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** AP quiet mode */
+    t_u8 AP_quiet_mode;
+    /** Quiet count */
+    t_u8 quiet_count;
+    /** Quiet period */
+    t_u8 quiet_period;
+    /** Quiet duration */
+    t_u16 quiet_dur;
+    /** Quiet offset */
+    t_u16 quiet_offset;
+} MLAN_PACK_END MrvlIETypes_QuietChan_t;
+
+/** Wide Bandwidth Channel Switch IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_BWSwitch_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** New Channel width */
+    t_u8 new_chan_width;
+    /** New Channel center frequency 1 */
+    t_u8 new_chan_center_freq_1;
+    /** New channel center frequency 2 */
+    t_u8 new_chan_center_freq_2;
+} MLAN_PACK_END MrvlIETypes_BWSwitch_t;
+
+/** AID IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_AID_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** AID number */
+    t_u16 AID;
+} MLAN_PACK_END MrvlIETypes_AID_t;
+
+/** Operating Mode Notification IE */
+typedef MLAN_PACK_START struct _MrvlIETypes_OperModeNtf_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+
+    /** operating mdoe */
+    t_u8 oper_mode;
+} MLAN_PACK_END MrvlIETypes_OperModeNtf_t;
+
+
+/** MrvlIEtypes_PMK_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_PMK_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** PMK */
+    t_u8 pmk[1];
+} MLAN_PACK_END MrvlIEtypes_PMK_t;
+
+/** MrvlIEtypes_Passphrase_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Passphrase_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Passphrase */
+    char passphrase[1];
+} MLAN_PACK_END MrvlIEtypes_Passphrase_t;
+
+/** MrvlIEtypes_Passphrase_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Password_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Passphrase */
+    char password[1];
+} MLAN_PACK_END MrvlIEtypes_Password_t;
+
+/** MrvlIEtypes_SAE_PWE_Mode_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_SAE_PWE_Mode_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** WPA3 SAE mechanism for PWE derivation */
+    char pwe[1];
+} MLAN_PACK_END MrvlIEtypes_SAE_PWE_Mode_t;
+
+/** SAE H2E capability bit in RSNX */
+#define SAE_H2E_BIT 5
+
+/* unicastCipher -
+ *      Bit 0   : RFU
+ *      Bit 1   : RFU
+ *      Bit 2   : TKIP
+ *      Bit 3   : AES CCKM
+ *      Bit 2-7 : RFU
+ * multicastCipher -
+ *      Bit 0   : WEP40
+ *      Bit 1   : WEP104
+ *      Bit 2   : TKIP
+ *      Bit 3   : AES
+ *      Bit 4-7 : Reserved for now
+ */
+/** MrvlIEtypes_Cipher_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Cipher_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** PairCipher */
+    t_u8 pair_cipher;
+    /** GroupCipher */
+    t_u8 group_cipher;
+} MLAN_PACK_END MrvlIEtypes_Cipher_t;
+
+/* rsnMode -
+ *      Bit 0    : No RSN
+ *      Bit 1-2  : RFU
+ *      Bit 3    : WPA
+ *      Bit 4    : WPA-NONE
+ *      Bit 5    : WPA2
+ *      Bit 6    : AES CCKM
+ *      Bit 7-15 : RFU
+ */
+/** MrvlIEtypes_EncrProto_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_EncrProto_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** EncrProto */
+    t_u16 rsn_mode;
+} MLAN_PACK_END MrvlIEtypes_EncrProto_t;
+
+/** MrvlIEtypes_Bssid_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_Bssid_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Bssid */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END MrvlIEtypes_Bssid_t;
+
+/*
+ * This struct will handle GET,SET,CLEAR function for embedded
+ * supplicant.
+ * Define data structure for HostCmd_CMD_802_11_SUPPLICANT_PMK
+ */
+/** HostCmd_DS_802_11_SUPPLICANT_PMK */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SUPPLICANT_PMK
+{
+    /** CMD Action GET/SET/CLEAR */
+    t_u16 action;
+    /** CacheResult initialized to 0 */
+    t_u16 cache_result;
+    /** TLV Buffer */
+    t_u8 tlv_buffer[1];
+    /** MrvlIEtypes_SsidParamSet_t  SsidParamSet;
+     * MrvlIEtypes_PMK_t           Pmk;
+     * MrvlIEtypes_Passphrase_t    Passphrase;
+     * MrvlIEtypes_Bssid_t         Bssid;
+     **/
+} MLAN_PACK_END HostCmd_DS_802_11_SUPPLICANT_PMK;
+
+/*
+ * This struct will GET the Supplicant supported bitmaps
+ * The GET_CURRENT action will get the network profile used
+ * for the current assocation.
+ * Define data structure for HostCmd_CMD_802_11_SUPPLICANT_PROFILE
+ */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_SUPPLICANT_PROFILE
+{
+    /** GET/SET/GET_CURRENT */
+    t_u16 action;
+    /** Reserved */
+    t_u16 reserved;
+    /** TLVBuffer */
+    t_u8 tlv_buf[1];
+    /* MrvlIEtypes_EncrProto_t */
+} MLAN_PACK_END HostCmd_DS_802_11_SUPPLICANT_PROFILE;
+
+/** HostCmd_CMD_802_11_RF_CHANNEL */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_RF_CHANNEL
+{
+    /** Action */
+    t_u16 action;
+    /** Current channel */
+    t_u16 current_channel;
+    /** RF type */
+    t_u16 rf_type;
+    /** Reserved field */
+    t_u16 reserved;
+    /** Reserved */
+    t_u8 reserved_1[32];
+} MLAN_PACK_END HostCmd_DS_802_11_RF_CHANNEL;
+
+/** HostCmd_DS_VERSION_EXT */
+typedef MLAN_PACK_START struct _HostCmd_DS_VERSION_EXT
+{
+    /** Selected version string */
+    t_u8 version_str_sel;
+    /** Version string */
+    char version_str[128];
+} MLAN_PACK_END HostCmd_DS_VERSION_EXT;
+
+/** HostCmd_CMD_CW_MODE_CTRL */
+typedef MLAN_PACK_START struct _HostCmd_DS_CW_MODE_CTRL
+{
+    /** Action for CW Tone Control */
+    t_u16 action;
+    /** Mode of Operation 0: Disbale 1: Tx Continuous Packet 2: Tx Continuous Wave */
+    t_u8 mode;
+    /** channel */
+    t_u8 channel;
+    /** channel info*/
+    t_u8 chanInfo;
+    /** Tx Power level in dBm */
+    t_u16 txPower;
+    /** Packet Length */
+    t_u16 pktLength;
+    /** bit rate Info */
+    t_u32 rateInfo;
+} MLAN_PACK_END HostCmd_DS_CW_MODE_CTRL;
+
+/** HostCmd_CMD_802_11_RF_ANTENNA */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_RF_ANTENNA
+{
+    /** Action */
+    t_u16 action;
+    /**  Antenna or 0xffff (diversity) */
+    t_u16 antenna_mode;
+    /** Evaluate time */
+    t_u16 evaluate_time;
+    /** Current antenna */
+    t_u16 current_antenna;
+#ifdef RW610
+    /** Evaluate mode */
+    t_u8 evaluate_mode;
+#endif
+} MLAN_PACK_END HostCmd_DS_802_11_RF_ANTENNA;
+
+/** HostCmd_DS_802_11_IBSS_STATUS */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_IBSS_STATUS
+{
+    /** Action */
+    t_u16 action;
+    /** Enable */
+    t_u16 enable;
+    /** BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Beacon interval */
+    t_u16 beacon_interval;
+    /** ATIM window interval */
+    t_u16 atim_window;
+    /** User G rate protection */
+    t_u16 use_g_rate_protect;
+} MLAN_PACK_END HostCmd_DS_802_11_IBSS_STATUS;
+
+/** HostCmd_DS_MGMT_IE_LIST_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_MGMT_IE_LIST
+{
+    /** Action */
+    t_u16 action;
+    /** Get/Set mgmt IE */
+    mlan_ds_misc_custom_ie ds_mgmt_ie;
+} MLAN_PACK_END HostCmd_DS_MGMT_IE_LIST_CFG;
+
+/** HostCmd_CMD_MAC_REG_ACCESS */
+typedef MLAN_PACK_START struct _HostCmd_DS_MAC_REG_ACCESS
+{
+    /** Action */
+    t_u16 action;
+    /** MAC register offset */
+    t_u16 offset;
+    /** MAC register value */
+    t_u32 value;
+} MLAN_PACK_END HostCmd_DS_MAC_REG_ACCESS;
+
+/** HostCmd_CMD_BBP_REG_ACCESS */
+typedef MLAN_PACK_START struct _HostCmd_DS_BBP_REG_ACCESS
+{
+    /** Acion */
+    t_u16 action;
+    /** BBP register offset */
+    t_u16 offset;
+    /** BBP register value */
+    t_u8 value;
+    /** Reserved field */
+    t_u8 reserved[3];
+} MLAN_PACK_END HostCmd_DS_BBP_REG_ACCESS;
+
+/**  HostCmd_CMD_RF_REG_ACCESS */
+typedef MLAN_PACK_START struct _HostCmd_DS_RF_REG_ACCESS
+{
+    /** Action */
+    t_u16 action;
+    /** RF register offset */
+    t_u16 offset;
+    /** RF register value */
+    t_u8 value;
+    /** Reserved field */
+    t_u8 reserved[3];
+} MLAN_PACK_END HostCmd_DS_RF_REG_ACCESS;
+
+/** HostCmd_DS_802_11_EEPROM_ACCESS */
+typedef MLAN_PACK_START struct _HostCmd_DS_802_11_EEPROM_ACCESS
+{
+    /** Action */
+    t_u16 action;
+
+    /** multiple 4 */
+    t_u16 offset;
+    /** Number of bytes */
+    t_u16 byte_count;
+    /** Value */
+    t_u8 value;
+} MLAN_PACK_END HostCmd_DS_802_11_EEPROM_ACCESS;
+
+/** HostCmd_DS_MEM_ACCESS */
+typedef MLAN_PACK_START struct _HostCmd_DS_MEM_ACCESS
+{
+    /** Action */
+    t_u16 action;
+    /** Reserved field */
+    t_u16 reserved;
+    /** Address */
+    t_u32 addr;
+    /** Value */
+    t_u32 value;
+} MLAN_PACK_END HostCmd_DS_MEM_ACCESS;
+
+/** HostCmd_DS_AUTO_RECONNECT */
+typedef MLAN_PACK_START struct _HostCmd_DS_AUTO_RECONNECT
+{
+    /** Action */
+    t_u16 action;
+    /** Reconnect Counter */
+    t_u8 reconnect_counter;
+    /** Reconnect Interval */
+    t_u8 reconnect_interval;
+    /** Flags */
+    t_u16 flags;
+} MLAN_PACK_END HostCmd_DS_AUTO_RECONNECT;
+
+/** HostCmd_CMD_HS_WAKEUP_REASON */
+typedef MLAN_PACK_START struct _HostCmd_DS_HS_WAKEUP_REASON
+{
+    /** wakeupReason:
+     * 0: unknown
+     * 1: Broadcast data matched
+     * 2: Multicast data matched
+     * 3: Unicast data matched
+     * 4: Maskable event matched
+     * 5. Non-maskable event matched
+     * 6: Non-maskable condition matched (EAPoL rekey)
+     * 7: Magic pattern matched
+     * Others: reserved. (set to 0) */
+    t_u16 wakeup_reason;
+} MLAN_PACK_END HostCmd_DS_HS_WAKEUP_REASON;
+
+/** HostCmd_BRIDGE_MODE */
+typedef MLAN_PACK_START struct _HostCmd_BRIDGE_MODE
+{
+    /** Action */
+    t_u16 action;
+    /** Enable */
+    t_u8 enable;
+} MLAN_PACK_END HostCmd_BRIDGE_MODE;
+
+/** HostCmd_DS_SUBSCRIBE_EVENT */
+typedef MLAN_PACK_START struct _HostCmd_DS_SUBSCRIBE_EVENT
+{
+    /** Action */
+    t_u16 action;
+    /** Bitmap of subscribed events */
+    t_u16 event_bitmap;
+} MLAN_PACK_END HostCmd_DS_SUBSCRIBE_EVENT;
+
+/** HostCmd_DS_OTP_USER_DATA */
+typedef MLAN_PACK_START struct _HostCmd_DS_OTP_USER_DATA
+{
+    /** Action */
+    t_u16 action;
+    /** Reserved field */
+    t_u16 reserved;
+    /** User data length */
+    t_u16 user_data_length;
+    /** User data */
+    t_u8 user_data[1];
+} MLAN_PACK_END HostCmd_DS_OTP_USER_DATA;
+
+/** HostCmd_DS_INACTIVITY_TIMEOUT_EXT */
+typedef MLAN_PACK_START struct _HostCmd_DS_INACTIVITY_TIMEOUT_EXT
+{
+    /** ACT_GET/ACT_SET */
+    t_u16 action;
+    /** uS, 0 means 1000uS(1ms) */
+    t_u16 timeout_unit;
+    /** Inactivity timeout for unicast data */
+    t_u16 unicast_timeout;
+    /** Inactivity timeout for multicast data */
+    t_u16 mcast_timeout;
+    /** Timeout for additional RX traffic after Null PM1 packet exchange */
+    t_u16 ps_entry_timeout;
+    /** Inactivity timeout for cmd */
+    t_u16 ps_cmd_timeout;
+} MLAN_PACK_END HostCmd_DS_INACTIVITY_TIMEOUT_EXT;
+
+/** HostCmd_DS_CMD_TX_AMPDU_PROT_MODE */
+typedef MLAN_PACK_START struct _HostCmd_DS_CMD_TX_AMPDU_PROT_MODE
+{
+    /** Action */
+    t_u16 action;
+    /** Prot mode */
+    t_u16 mode;
+} MLAN_PACK_END HostCmd_DS_CMD_TX_AMPDU_PROT_MODE;
+
+/** TLV type : STA Mac address */
+#define TLV_TYPE_STA_MAC_ADDRESS (PROPRIETARY_TLV_BASE_ID + 0x20) // 0x0120
+
+/** MrvlIEtypes_MacAddr_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_MacAddr_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** mac address */
+    t_u8 mac[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END MrvlIEtypes_MacAddr_t;
+
+#ifdef SD8801
+typedef MLAN_PACK_START struct _MrvlIETypes_ExtBLECoex_Config_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Enable or disable external coexistence */
+    t_u8 Enabled;
+    /** Ignore the priority of the external radio request */
+    t_u8 IgnorePriority;
+    /** Default priority when the priority of the external radio
+request is ignored */
+    t_u8 DefaultPriority;
+    /** Input request GPIO pin for EXT_RADIO_REQ signal */
+    t_u8 EXT_RADIO_REQ_ip_gpio_num;
+    /** Input request GPIO polarity for EXT_RADIO_REQ signal */
+    t_u8 EXT_RADIO_REQ_ip_gpio_polarity;
+    /** Input priority GPIO pin for EXT_RADIO_PRI signal */
+    t_u8 EXT_RADIO_PRI_ip_gpio_num;
+    /** Input priority GPIO polarity for EXT_RADIO_PRI signal */
+    t_u8 EXT_RADIO_PRI_ip_gpio_polarity;
+    /** Output grant GPIO pin for WLAN_GRANT signal */
+    t_u8 WLAN_GRANT_op_gpio_num;
+    /** Output grant GPIO polarity of WLAN_GRANT */
+    t_u8 WLAN_GRANT_op_gpio_polarity;
+    /** Reserved Bytes */
+    t_u16 reserved_1;
+    /** Reserved Bytes */
+    t_u16 reserved_2;
+    /** External Radio Request count */
+    t_u16 EXT_RADIO_REQ_count;
+    /** External Radio Priority count */
+    t_u16 EXT_RADIO_PRI_count;
+    /** WLAN GRANT count */
+    t_u16 WLAN_GRANT_count;
+} MLAN_PACK_END MrvlIETypes_ExtBLECoex_Config_t;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_ExtBLECoex_Config_t
+{
+    /** Action */
+    t_u16 action;
+    /** Reserved field */
+    t_u16 reserved;
+    /** External Coex Configuration Data */
+    MrvlIETypes_ExtBLECoex_Config_t coex_cfg_data;
+} MLAN_PACK_END HostCmd_DS_ExtBLECoex_Config_t;
+#endif
+
+/** Assoc Request */
+#define SUBTYPE_ASSOC_REQUEST 0U
+/** Assoc Response */
+#define SUBTYPE_ASSOC_RESP 1U
+/** ReAssoc Request */
+#define SUBTYPE_REASSOC_REQUEST 2U
+/** ReAssoc Response */
+#define SUBTYPE_REASSOC_RESP 3U
+/** Probe Request */
+#define SUBTYPE_PROBE_REQUEST 4U
+/** Probe Response */
+#define SUBTYPE_PROBE_RESP 5U
+/** Disassoc Request */
+#define SUBTYPE_DISASSOC 10
+/** Auth Request */
+#define SUBTYPE_AUTH 11
+/** Deauth Request */
+#define SUBTYPE_DEAUTH 12
+/** Action frame */
+#define SUBTYPE_ACTION 13
+
+/** TLV type : AP Channel band Config */
+#define TLV_TYPE_UAP_CHAN_BAND_CONFIG (PROPRIETARY_TLV_BASE_ID + 0x2aU) // 0x012a
+/** TLV type : AP Mac address */
+#define TLV_TYPE_UAP_MAC_ADDRESS (PROPRIETARY_TLV_BASE_ID + 0x2b) // 0x012b
+/** TLV type : AP Beacon period */
+#define TLV_TYPE_UAP_BEACON_PERIOD (PROPRIETARY_TLV_BASE_ID + 0x2c) // 0x012c
+/** TLV type : AP DTIM period */
+#define TLV_TYPE_UAP_DTIM_PERIOD (PROPRIETARY_TLV_BASE_ID + 0x2d) // 0x012d
+/** TLV type : AP Tx power */
+#define TLV_TYPE_UAP_TX_POWER (PROPRIETARY_TLV_BASE_ID + 0x2fU) // 0x012f
+/** TLV type : AP SSID broadcast control */
+#define TLV_TYPE_UAP_BCAST_SSID_CTL (PROPRIETARY_TLV_BASE_ID + 0x30) // 0x0130
+/** TLV type : AP Preamble control */
+#define TLV_TYPE_UAP_PREAMBLE_CTL (PROPRIETARY_TLV_BASE_ID + 0x31) // 0x0131
+/** TLV type : AP Antenna control */
+#define TLV_TYPE_UAP_ANTENNA_CTL (PROPRIETARY_TLV_BASE_ID + 0x32) // 0x0132
+/** TLV type : AP RTS threshold */
+#define TLV_TYPE_UAP_RTS_THRESHOLD (PROPRIETARY_TLV_BASE_ID + 0x33) // 0x0133
+/** TLV type : AP Tx data rate */
+#define TLV_TYPE_UAP_TX_DATA_RATE (PROPRIETARY_TLV_BASE_ID + 0x35) // 0x0135
+/** TLV type: AP Packet forwarding control */
+#define TLV_TYPE_UAP_PKT_FWD_CTL (PROPRIETARY_TLV_BASE_ID + 0x36U) // 0x0136
+/** TLV type: STA information */
+#define TLV_TYPE_UAP_STA_INFO (PROPRIETARY_TLV_BASE_ID + 0x37) // 0x0137
+/** TLV type: AP STA MAC address filter */
+#define TLV_TYPE_UAP_STA_MAC_ADDR_FILTER (PROPRIETARY_TLV_BASE_ID + 0x38) // 0x0138
+/** TLV type: AP STA ageout timer */
+#define TLV_TYPE_UAP_STA_AGEOUT_TIMER (PROPRIETARY_TLV_BASE_ID + 0x39) // 0x0139
+/** TLV type: AP WEP keys */
+#define TLV_TYPE_UAP_WEP_KEY (PROPRIETARY_TLV_BASE_ID + 0x3b) // 0x013b
+/** TLV type: AP WPA passphrase */
+#define TLV_TYPE_UAP_WPA_PASSPHRASE (PROPRIETARY_TLV_BASE_ID + 0x3c) // 0x013c
+/** TLV type: AP protocol */
+#define TLV_TYPE_UAP_ENCRYPT_PROTOCOL (PROPRIETARY_TLV_BASE_ID + 0x40) // 0x0140
+/** TLV type: AP AKMP */
+#define TLV_TYPE_UAP_AKMP (PROPRIETARY_TLV_BASE_ID + 0x41) // 0x0141
+/** TLV type: AP Fragment threshold */
+#define TLV_TYPE_UAP_FRAG_THRESHOLD (PROPRIETARY_TLV_BASE_ID + 0x46) // 0x0146
+/** TLV type: AP Group rekey timer */
+#define TLV_TYPE_UAP_GRP_REKEY_TIME (PROPRIETARY_TLV_BASE_ID + 0x47) // 0x0147
+/**TLV type : AP Max Station number */
+#define TLV_TYPE_UAP_MAX_STA_CNT (PROPRIETARY_TLV_BASE_ID + 0x55U) // 0x0155
+/**TLV type : AP Retry limit */
+#define TLV_TYPE_UAP_RETRY_LIMIT (PROPRIETARY_TLV_BASE_ID + 0x5d) // 0x015d
+/** TLV type : AP MCBC data rate */
+#define TLV_TYPE_UAP_MCBC_DATA_RATE (PROPRIETARY_TLV_BASE_ID + 0x62) // 0x0162
+/**TLV type: AP RSN replay protection */
+#define TLV_TYPE_UAP_RSN_REPLAY_PROTECT (PROPRIETARY_TLV_BASE_ID + 0x64) // 0x0164
+/** TLV ID : Management Frame */
+#define TLV_TYPE_UAP_MGMT_FRAME (PROPRIETARY_TLV_BASE_ID + 0x68U) // 0x0168
+/** TLV: Management IE list */
+#define MRVL_MGMT_IE_LIST_TLV_ID (PROPRIETARY_TLV_BASE_ID + 0x69U)
+/**TLV type: AP mgmt IE passthru mask */
+#define TLV_TYPE_UAP_MGMT_IE_PASSTHRU_MASK (PROPRIETARY_TLV_BASE_ID + 0x70U) // 0x0170
+/** TLV type : AP ECSA CONFIG TLV */
+#define TLV_TYPE_UAP_ECSA_CONFIG (PROPRIETARY_TLV_BASE_ID + 289)
+
+#if CONFIG_IMD3_CFG
+#define TLV_TYPE_IMD_VALIDATION (PROPRIETARY_TLV_BASE_ID + 0x60) // 0x0160
+#endif
+
+/** TLV : 20/40 coex config */
+#define TLV_TYPE_2040_BSS_COEX_CONTROL (PROPRIETARY_TLV_BASE_ID + 0x98) // 0x0198
+/**TLV type: AP pairwise handshake timeout */
+#define TLV_TYPE_UAP_EAPOL_PWK_HSK_TIMEOUT (PROPRIETARY_TLV_BASE_ID + 0x75) // 0x0175
+/**TLV type: AP pairwise handshake retries */
+#define TLV_TYPE_UAP_EAPOL_PWK_HSK_RETRIES (PROPRIETARY_TLV_BASE_ID + 0x76) // 0x0176
+/**TLV type: AP groupwise handshake timeout */
+#define TLV_TYPE_UAP_EAPOL_GWK_HSK_TIMEOUT (PROPRIETARY_TLV_BASE_ID + 0x77) // 0x0177
+/**TLV type: AP groupwise handshake retries */
+#define TLV_TYPE_UAP_EAPOL_GWK_HSK_RETRIES (PROPRIETARY_TLV_BASE_ID + 0x78) // 0x0178
+/** TLV type: AP PS STA ageout timer */
+#define TLV_TYPE_UAP_PS_STA_AGEOUT_TIMER (PROPRIETARY_TLV_BASE_ID + 0x7b) // 0x017b
+/** TLV type : Pairwise Cipher */
+#define TLV_TYPE_PWK_CIPHER (PROPRIETARY_TLV_BASE_ID + 0x91) // 0x0191
+/** TLV type : Group Cipher */
+#define TLV_TYPE_GWK_CIPHER (PROPRIETARY_TLV_BASE_ID + 0x92) // 0x0192
+/** TLV type : BSS Status */
+#define TLV_TYPE_BSS_STATUS (PROPRIETARY_TLV_BASE_ID + 0x93) // 0x0193
+
+#if CONFIG_11AX
+/** TLV type: Extension ID for 11AX Capability */
+#define TLV_TYPE_EXTENSION_ID 0x00ff
+#endif
+
+/**TLV type : Host MLME Flag*/
+#define TLV_TYPE_HOST_MLME (PROPRIETARY_TLV_BASE_ID + 307)
+
+#if CONFIG_EXTERNAL_COEX_PTA
+/** TLV type : Robust Coex */
+#define TLV_TYPE_ROBUST_COEX (PROPRIETARY_TLV_BASE_ID + 0x138) // 0x0238
+#endif
+
+/** TLV type : WPA3 SAE Passowrd */
+#define TLV_TYPE_UAP_WPA3_SAE_PASSWORD (PROPRIETARY_TLV_BASE_ID + 0x141) // 0x0241
+
+
+/** MrvlIEtypes_AutoLinkParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_AutoLinkParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Auto Link Periodical scan interval */
+    uint32_t scan_timer_interval;
+    /** The condition triggers Auto Link periodical scan
+    0:trigger scan when current link is not good
+    1:trigger scan by host setting(always periodical scan)
+    */
+    uint8_t scan_timer_condition;
+    /** Auto Link periodical scan channel list:
+    0:only scan with previous In-STA associated channel
+    1: 2.4G all channels
+    */
+    uint8_t scan_channel_list;
+} MLAN_PACK_END MrvlIEtypes_AutoLinkParamSet_t;
+
+/** MrvlIEtypes_BridgeParamSet_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_BridgeParamSet_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** SSID of External AP */
+    MrvlIEtypes_SsIdParamSet_t SSID_ExAP;
+    /** Passphrase of External AP */
+    MrvlIEtypes_Passphrase_t pass_ExAP;
+    /** SSID of External AP */
+    MrvlIEtypes_SsIdParamSet_t SSID_bridge;
+    /** Passphrase of External AP */
+    MrvlIEtypes_Passphrase_t pass_bridge;
+} MLAN_PACK_END MrvlIEtypes_BridgeParamSet_t;
+
+/** MrvlIEtypes_beacon_period_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_beacon_period_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** beacon period */
+    t_u16 beacon_period;
+} MLAN_PACK_END MrvlIEtypes_beacon_period_t;
+
+/** MrvlIEtypes_ecsa_config_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ecsa_config_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** enable */
+    t_u16 enable;
+    /** data traffic mode */
+    t_u8 ChannelSwitchMode;
+    /** channel switch count */
+    t_u8 ChannelSwitchCount;
+} MLAN_PACK_END MrvlIEtypes_ecsa_config_t;
+
+/** MrvlIEtypes_dtim_period_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_dtim_period_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** DTIM period */
+    t_u8 dtim_period;
+} MLAN_PACK_END MrvlIEtypes_dtim_period_t;
+
+/** MrvlIEtypes_tx_rate_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_tx_rate_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** tx data rate */
+    t_u16 tx_data_rate;
+} MLAN_PACK_END MrvlIEtypes_tx_rate_t;
+
+/** MrvlIEtypes_mcbc_rate_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_mcbc_rate_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** mcbc data rate */
+    t_u16 mcbc_data_rate;
+} MLAN_PACK_END MrvlIEtypes_mcbc_rate_t;
+
+/** MrvlIEtypes_tx_power_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_tx_power_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** tx power */
+    t_u8 tx_power;
+} MLAN_PACK_END MrvlIEtypes_tx_power_t;
+
+/** MrvlIEtypes_bcast_ssid_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_bcast_ssid_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** bcast ssid control*/
+    t_u8 bcast_ssid_ctl;
+} MLAN_PACK_END MrvlIEtypes_bcast_ssid_t;
+
+/** MrvlIEtypes_antenna_mode_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_antenna_mode_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** which antenna */
+    t_u8 which_antenna;
+    /** antenna mode*/
+    t_u8 antenna_mode;
+} MLAN_PACK_END MrvlIEtypes_antenna_mode_t;
+
+/** MrvlIEtypes_pkt_forward_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_pkt_forward_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** pkt foward control */
+    t_u8 pkt_forward_ctl;
+} MLAN_PACK_END MrvlIEtypes_pkt_forward_t;
+
+/** MrvlIEtypes_max_sta_count_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_max_sta_count_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** max station count */
+    t_u16 max_sta_count;
+} MLAN_PACK_END MrvlIEtypes_max_sta_count_t;
+
+/** MrvlIEtypes_sta_ageout_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_sta_ageout_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** station age out timer */
+    t_u32 sta_ageout_timer;
+} MLAN_PACK_END MrvlIEtypes_sta_ageout_t;
+
+/** MrvlIEtypes_rts_threshold_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_rts_threshold_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** rts threshold */
+    t_u16 rts_threshold;
+} MLAN_PACK_END MrvlIEtypes_rts_threshold_t;
+
+/** MrvlIEtypes_frag_threshold_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_frag_threshold_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** frag threshold */
+    t_u16 frag_threshold;
+} MLAN_PACK_END MrvlIEtypes_frag_threshold_t;
+
+/** MrvlIEtypes_retry_limit_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_retry_limit_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** retry limit */
+    t_u8 retry_limit;
+} MLAN_PACK_END MrvlIEtypes_retry_limit_t;
+
+/** MrvlIEtypes_eapol_pwk_hsk_timeout_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_eapol_pwk_hsk_timeout_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** pairwise update timeout in milliseconds */
+    t_u32 pairwise_update_timeout;
+} MLAN_PACK_END MrvlIEtypes_eapol_pwk_hsk_timeout_t;
+
+/** MrvlIEtypes_eapol_pwk_hsk_retries_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_eapol_pwk_hsk_retries_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** pairwise handshake retries */
+    t_u32 pwk_retries;
+} MLAN_PACK_END MrvlIEtypes_eapol_pwk_hsk_retries_t;
+
+/** MrvlIEtypes_eapol_gwk_hsk_timeout_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_eapol_gwk_hsk_timeout_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** groupwise update timeout in milliseconds */
+    t_u32 groupwise_update_timeout;
+} MLAN_PACK_END MrvlIEtypes_eapol_gwk_hsk_timeout_t;
+
+/** MrvlIEtypes_eapol_gwk_hsk_retries_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_eapol_gwk_hsk_retries_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** groupwise handshake retries */
+    t_u32 gwk_retries;
+} MLAN_PACK_END MrvlIEtypes_eapol_gwk_hsk_retries_t;
+
+/** MrvlIEtypes_mgmt_ie_passthru_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_mgmt_ie_passthru_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** mgmt IE mask value */
+    t_u32 mgmt_ie_mask;
+} MLAN_PACK_END MrvlIEtypes_mgmt_ie_passthru_t;
+
+/** TLV buffer : 2040 coex config */
+typedef MLAN_PACK_START struct _MrvlIEtypes_2040_coex_enable_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Enable */
+    t_u8 enable_2040coex;
+} MLAN_PACK_END MrvlIEtypes_2040_coex_enable_t;
+
+/** MrvlIEtypes_mac_filter_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_mac_filter_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Filter mode */
+    t_u8 filter_mode;
+    /** Number of STA MACs */
+    t_u8 count;
+    /** STA MAC addresses buffer */
+    t_u8 mac_address[1];
+} MLAN_PACK_END MrvlIEtypes_mac_filter_t;
+
+/** setting for band_config - band=5GHZ */
+#define BAND_CONFIG_5GHZ 0x01U
+
+#if CONFIG_UNII4_BAND_SUPPORT
+/** TODO: Temporary work around until firmware fix is available */
+/** setting for band_config - channel 173 */
+#define BAND_CONFIG_CH_173 0x11U
+/** setting for band_config - channel 169 and channel 177 */
+#define BAND_CONFIG_CH_169_177 0x31U
+#endif
+
+/** MrvlIEtypes_retry_limit_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_channel_band_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Band Configuration
+     *
+     * [7-6] Channel Selection Mode; 00 manual, 01 ACS
+     * [3-2] Channel Width; 00 20 MHz
+     * [1-0] Band Info; 00 2.4 GHz
+     */
+    t_u8 band_config;
+    /** channel */
+    t_u8 channel;
+} MLAN_PACK_END MrvlIEtypes_channel_band_t;
+
+/** MrvlIEtypes_auth_type_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_auth_type_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Authentication type */
+    t_u8 auth_type;
+    /** PWE derivation */
+    t_u8 PWE_derivation;
+    /** transition disable */
+    t_u8 transition_disable;
+} MLAN_PACK_END MrvlIEtypes_auth_type_t;
+
+/** MrvlIEtypes_encrypt_protocol_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_encrypt_protocol_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** encryption protocol */
+    t_u16 protocol;
+} MLAN_PACK_END MrvlIEtypes_encrypt_protocol_t;
+
+/** MrvlIEtypes_pwk_cipher_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_pwk_cipher_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** protocol */
+    t_u16 protocol;
+    /** pairwise cipher */
+    t_u8 pairwise_cipher;
+    /** reserved */
+    t_u8 reserved;
+} MLAN_PACK_END MrvlIEtypes_pwk_cipher_t;
+
+/** MrvlIEtypes_gwk_cipher_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_gwk_cipher_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** group cipher */
+    t_u8 group_cipher;
+    /** reserved */
+    t_u8 reserved;
+} MLAN_PACK_END MrvlIEtypes_gwk_cipher_t;
+
+/** MrvlIEtypes_akmp_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_akmp_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** key management */
+    t_u16 key_mgmt;
+    /** key management operation */
+    t_u16 key_mgmt_operation;
+} MLAN_PACK_END MrvlIEtypes_akmp_t;
+
+/** MrvlIEtypes_passphrase_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_passphrase_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** passphrase */
+    t_u8 passphrase[1];
+} MLAN_PACK_END MrvlIEtypes_passphrase_t;
+
+/** MrvlIEtypes_passphrase_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_password_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** passphrase */
+    t_u8 password[1];
+} MLAN_PACK_END MrvlIEtypes_password_t;
+
+/** MrvlIEtypes_rsn_replay_prot_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_rsn_replay_prot_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** rsn replay proection */
+    t_u8 rsn_replay_prot;
+} MLAN_PACK_END MrvlIEtypes_rsn_replay_prot_t;
+
+/** MrvlIEtypes_group_rekey_time_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_group_rekey_time_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** group key rekey time */
+    t_u32 gk_rekey_time;
+} MLAN_PACK_END MrvlIEtypes_group_rekey_time_t;
+
+/** MrvlIEtypes_wep_key_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_wep_key_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** key index */
+    t_u8 key_index;
+    /** is default */
+    t_u8 is_default;
+    /** key data */
+    t_u8 key[1];
+} MLAN_PACK_END MrvlIEtypes_wep_key_t;
+
+/** MrvlIEtypes_bss_status_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_bss_status_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** BSS status, READ only */
+    t_u16 bss_status;
+} MLAN_PACK_END MrvlIEtypes_bss_status_t;
+
+/** MrvlIEtypes_preamble_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_preamble_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** preamble type, READ only */
+    t_u8 preamble_type;
+} MLAN_PACK_END MrvlIEtypes_preamble_t;
+
+/** MrvlIEtypes_wmm_parameter_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_wmm_parameter_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** WMM parameter */
+    WmmParameter_t wmm_para;
+} MLAN_PACK_END MrvlIEtypes_wmm_parameter_t;
+
+/** SNMP_MIB_UAP_INDEX */
+typedef enum _SNMP_MIB_UAP_INDEX
+{
+    tkip_mic_failures             = 0x0b,
+    ccmp_decrypt_errors           = 0x0c,
+    wep_undecryptable_count       = 0x0d,
+    wep_icv_error_count           = 0x0e,
+    decrypt_failure_count         = 0xf,
+    dot11_failed_count            = 0x12,
+    dot11_retry_count             = 0x13,
+    dot11_multi_retry_count       = 0x14,
+    dot11_frame_dup_count         = 0x15,
+    dot11_rts_success_count       = 0x16,
+    dot11_rts_failure_count       = 0x17,
+    dot11_ack_failure_count       = 0x18,
+    dot11_rx_fragment_count       = 0x19,
+    dot11_mcast_rx_frame_count    = 0x1a,
+    dot11_fcs_error_count         = 0x1b,
+    dot11_tx_frame_count          = 0x1c,
+    dot11_rsna_tkip_cm_invoked    = 0x1d,
+    dot11_rsna_4way_hshk_failures = 0x1e,
+    dot11_mcast_tx_count          = 0x1f,
+} SNMP_MIB_UAP_INDEX;
+
+/** MrvlIEtypes_snmp_oid_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_snmp_oid_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** data */
+    t_u32 data;
+} MLAN_PACK_END MrvlIEtypes_snmp_oid_t;
+
+/** HostCmd_SYS_CONFIG */
+typedef MLAN_PACK_START struct _HostCmd_DS_SYS_CONFIG
+{
+    /** CMD Action GET/SET*/
+    t_u16 action;
+    /** Tlv buffer */
+    t_u8 tlv_buffer[1];
+} MLAN_PACK_END HostCmd_DS_SYS_CONFIG;
+
+#ifdef SD8801
+/** HostCmd_ACS_CONFIG */
+typedef MLAN_PACK_START struct _HostCmd_DS_ACS_CONFIG
+{
+    /** channel */
+    t_u8 chan;
+    /** Tlv buffer */
+    t_u8 tlv_buffer[1];
+} MLAN_PACK_END HostCmd_DS_ACS_CONFIG;
+#endif
+
+/** HostCmd_SYS_CONFIG */
+typedef MLAN_PACK_START struct _HostCmd_DS_SYS_INFO
+{
+    /** sys info */
+    t_u8 sys_info[64];
+} MLAN_PACK_END HostCmd_DS_SYS_INFO;
+
+/** HostCmd_DS_STA_DEAUTH */
+typedef MLAN_PACK_START struct _HostCmd_DS_STA_DEAUTH
+{
+    /** mac address */
+    t_u8 mac[MLAN_MAC_ADDR_LENGTH];
+    /** reason code */
+    t_u16 reason;
+} MLAN_PACK_END HostCmd_DS_STA_DEAUTH;
+
+/** HostCmd_DS_REPORT_MIC */
+typedef MLAN_PACK_START struct _HostCmd_DS_REPORT_MIC
+{
+    /** mac address */
+    t_u8 mac[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END HostCmd_DS_REPORT_MIC;
+
+/** HostCmd_PMF_CONFIG */
+typedef MLAN_PACK_START struct _HostCmd_DS_PMF_PARAMS
+{
+    /** CMD Action GET/SET*/
+    t_u16 action;
+    /** Params */
+    MLAN_PACK_START struct
+    {
+        t_u8 mfpc : 1; /* capable bit */
+        t_u8 mfpr : 1; /* required bit */
+        t_u8 rsvd : 6;
+    } MLAN_PACK_END params;
+} MLAN_PACK_END HostCmd_DS_PMF_PARAMS;
+
+/** Host Command id: POWER_MGMT  */
+#define HOST_CMD_POWER_MGMT_EXT 0x00ef
+/** TLV type: AP Sleep param */
+#define TLV_TYPE_AP_SLEEP_PARAM (PROPRIETARY_TLV_BASE_ID + 0x6aU) // 0x016a
+/** TLV type: AP Inactivity Sleep param */
+#define TLV_TYPE_AP_INACT_SLEEP_PARAM (PROPRIETARY_TLV_BASE_ID + 0x6bU) // 0x016b
+
+/** MrvlIEtypes_sleep_param_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_sleep_param_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** control bitmap */
+    t_u32 ctrl_bitmap;
+    /** min_sleep */
+    t_u32 min_sleep;
+    /** max_sleep */
+    t_u32 max_sleep;
+} MLAN_PACK_END MrvlIEtypes_sleep_param_t;
+
+/** MrvlIEtypes_inact_sleep_param_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_inact_sleep_param_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** inactivity timeout */
+    t_u32 inactivity_to;
+
+    /** min_awake */
+    t_u32 min_awake;
+    /** max_awake */
+    t_u32 max_awake;
+} MLAN_PACK_END MrvlIEtypes_inact_sleep_param_t;
+
+/** HostCmd_DS_POWER_MGMT */
+typedef MLAN_PACK_START struct _HostCmd_DS_POWER_MGMT_EXT
+{
+    /** CMD Action Get/Set*/
+    t_u16 action;
+    /** power mode */
+    t_u16 power_mode;
+} MLAN_PACK_END HostCmd_DS_POWER_MGMT_EXT;
+
+/** MrvlIEtypes_ps_sta_ageout_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_ps_sta_ageout_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** station age out timer */
+    t_u32 ps_sta_ageout_timer;
+} MLAN_PACK_END MrvlIEtypes_ps_sta_ageout_t;
+
+/** MrvlIEtypes_sta_info_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_sta_info_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** STA MAC address */
+    t_u8 mac_address[MLAN_MAC_ADDR_LENGTH];
+    /** Power mfg status */
+    t_u8 power_mfg_status;
+    /** RSSI */
+    t_s8 rssi;
+} MLAN_PACK_END MrvlIEtypes_sta_info_t;
+
+/** HostCmd_DS_STA_LIST */
+typedef MLAN_PACK_START struct _HostCmd_DS_STA_LIST
+{
+    /** Number of STAs */
+    t_u16 sta_count;
+    /* MrvlIEtypes_sta_info_t sta_info[0]; */
+} MLAN_PACK_END HostCmd_DS_STA_LIST;
+
+/** TLV ID : WAPI Information */
+#define TLV_TYPE_AP_WAPI_INFO (PROPRIETARY_TLV_BASE_ID + 0x67) // 0x0167
+
+/** MrvlIEtypes_sta_info_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_wapi_info_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Multicast PN */
+    t_u8 multicast_PN[16];
+} MLAN_PACK_END MrvlIEtypes_wapi_info_t;
+
+#ifdef WLAN_LOW_POWER_ENABLE
+/** HostCmd_CONFIG_LOW_PWR_MODE */
+typedef MLAN_PACK_START struct _HostCmd_CONFIG_LOW_PWR_MODE
+{
+    /** Enable LPM */
+    t_u8 enable;
+} MLAN_PACK_END HostCmd_CONFIG_LOW_PWR_MODE;
+#endif /* WLAN_LOW_POWER_ENABLE */
+
+/** HostCmd_CMD_GET_TSF */
+typedef MLAN_PACK_START struct _HostCmd_DS_TSF
+{
+    /** tsf value*/
+    t_u64 tsf;
+} MLAN_PACK_END HostCmd_DS_TSF;
+/* WLAN_GET_TSF*/
+
+/** HostCmd_CMD_TBTT_OFFSET */
+typedef MLAN_PACK_START struct _HostCmd_DS_TBTT_OFFSET
+{
+    /** Action */
+    t_u16 action;
+    /** Min TBTT offset */
+    t_u32 min_tbtt_offset;
+    /** Max TBTT offset */
+    t_u32 max_tbtt_offset;
+    /** Avg TBTT offset */
+    t_u32 avg_tbtt_offset;
+} MLAN_PACK_END HostCmd_DS_TBTT_OFFSET;
+
+/** HostCmd_CONFIG_ED_MAC_MODE */
+typedef MLAN_PACK_START struct _HostCmd_CONFIG_ED_MAC_MODE
+{
+    /** Enable/Disable ED CTRL 2G */
+    t_u16 ed_ctrl_2g;
+    /** Offset of default threshold */
+    t_s16 ed_offset_2g;
+#if CONFIG_5GHz_SUPPORT
+    /** Enable/Disable ED MAC mode */
+    t_u16 ed_ctrl_5g;
+    /** Offset of default threshold */
+    t_s16 ed_offset_5g;
+    /** Enable/Disable ED MAC mode */
+    t_u32 ed_bitmap_txq_lock;
+#endif
+} MLAN_PACK_END HostCmd_CONFIG_ED_MAC_MODE;
+
+#if CONFIG_ECSA
+#define MRVL_ACTION_CHAN_SWITCH_ANNOUNCE (PROPRIETARY_TLV_BASE_ID + 0x341)
+
+/** MrvlIEtypes_uap_chan_switch */
+typedef MLAN_PACK_START struct _MrvlIEtypes_action_chan_switch_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /* 0 send broadcast CSA action frame, 1 send unicast CSA action frame */
+    t_u32 mode;
+    /**ie buf*/
+    t_u8 ie_buf[];
+} MLAN_PACK_END MrvlIEtypes_action_chan_switch_t;
+#endif
+
+#if CONFIG_RF_TEST_MODE
+
+#define MFG_CMD_SET_TEST_MODE        1
+#define MFG_CMD_UNSET_TEST_MODE      0
+#define MFG_CMD_TX_ANT               0x1004
+#define MFG_CMD_RX_ANT               0x1005
+#define MFG_CMD_TX_CONT              0x1009
+#define MFG_CMD_RF_CHAN              0x100A
+#define MFG_CMD_CLR_RX_ERR           0x1010
+#define MFG_CMD_TX_FRAME             0x1021
+#define MFG_CMD_RFPWR                0x1033
+#define MFG_CMD_RF_BAND_AG           0x1034
+#define MFG_CMD_RF_CHANNELBW         0x1044
+#define MFG_CMD_RADIO_MODE_CFG       0x1211
+#define MFG_CMD_CONFIG_MAC_HE_TB_TX  0x110A
+#define MFG_CMD_CONFIG_TRIGGER_FRAME 0x110C
+#define MFG_CMD_OTP_MAC_ADD          0x108C
+#define MFG_CMD_OTP_CAL_DATA         0x121A
+
+typedef MLAN_PACK_START struct _HostCmd_DS_MFG_CMD_GENERIC_CFG
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** value 1 */
+    t_u32 data1;
+    /** value 2 */
+    t_u32 data2;
+    /** value 3 */
+    t_u32 data3;
+} MLAN_PACK_END HostCmd_DS_MFG_CMD_GENERIC_CFG;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_MFG_CMD_TX_FRAME2
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable */
+    t_u32 enable;
+    /** data_rate */
+    t_u32 data_rate;
+    /** frame pattern */
+    t_u32 frame_pattern;
+    /** frame length */
+    t_u32 frame_length;
+    /** BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Adjust burst sifs */
+    t_u16 adjust_burst_sifs;
+    /** Burst sifs in us*/
+    t_u32 burst_sifs_in_us;
+    /** short preamble */
+    t_u32 short_preamble;
+    /** active sub channel */
+    t_u32 act_sub_ch;
+    /** short GI */
+    t_u32 short_gi;
+    /** Adv coding */
+    t_u32 adv_coding;
+    /** Tx beamforming */
+    t_u32 tx_bf;
+    /** HT Greenfield Mode*/
+    t_u32 gf_mode;
+    /** STBC */
+    t_u32 stbc;
+    /** power id */
+    t_u32 rsvd[1];
+    /**signal bw*/
+    t_u32 signal_bw;
+    /** NumPkt */
+    t_u32 NumPkt;
+    /** MaxPE */
+    t_u32 MaxPE;
+    /** BeamChange */
+    t_u32 BeamChange;
+    /** Dcm */
+    t_u32 Dcm;
+    /** Doppler */
+    t_u32 Doppler;
+    /** MidP */
+    t_u32 MidP;
+    /** QNum */
+    t_u32 QNum;
+} MLAN_PACK_END HostCmd_DS_MFG_CMD_TX_FRAME2;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_MFG_CMD_TX_CONT
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable Tx*/
+    t_u32 enable_tx;
+    /** Continuous Wave mode */
+    t_u32 cw_mode;
+    /** payload pattern */
+    t_u32 payload_pattern;
+    /** CS Mode */
+    t_u32 cs_mode;
+    /** active sub channel */
+    t_u32 act_sub_ch;
+    /** Tx rate */
+    t_u32 tx_rate;
+    /** power id */
+    t_u32 rsvd;
+} MLAN_PACK_END HostCmd_DS_MFG_CMD_TX_CONT;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_MFG_CMD_HE_TBTX_T
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** Enable Tx */
+    t_u16 enable;
+    /** Q num */
+    t_u16 qnum;
+    /** AID */
+    t_u16 aid;
+    /** AXQ Mu Timer */
+    t_u16 axq_mu_timer;
+    /** Tx Power */
+    t_s16 tx_power;
+} MLAN_PACK_END HostCmd_DS_MFG_CMD_HE_TBTX_T;
+
+typedef MLAN_PACK_START struct _HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable Tx*/
+    t_u32 enable_tx;
+    /** enable Stand Alone HE TB */
+    t_u32 standalone_hetb;
+    /** Frame Control */
+    mfg_cmd_IEEEtypes_FrameCtrl_t frmCtl;
+    /** Duration */
+    t_u16 duration;
+    /** Destination MAC Address */
+    t_u8 dest_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Source MAC Address */
+    t_u8 src_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Common Info Field **/
+    mfg_cmd_IEEEtypes_HETrigComInfo_t trig_common_field;
+    /** User Info Field **/
+    mfg_cmd_IEEEtypes_HETrigUserInfo_t trig_user_info_field;
+    /** Trigger Dependent User Info Field **/
+    mfg_cmd_IEEETypes_BasicHETrigUserInfo_t basic_trig_user_info;
+} MLAN_PACK_END HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** Destination MAC Address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T;
+
+#define CAL_DATA_LEN 2800
+typedef MLAN_PACK_START struct _HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** CAL Data write status */
+    t_u32 cal_data_status;
+    /** CAL Data Length*/
+    t_u32 cal_data_len;
+    /** Destination MAC Address */
+    t_u8 cal_data[CAL_DATA_LEN];
+} MLAN_PACK_END HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T;
+#endif
+
+#ifdef OTP_CHANINFO
+#define TLV_TYPE_CHAN_ATTR_CFG    (PROPRIETARY_TLV_BASE_ID + 237U)
+#define TLV_TYPE_REGION_INFO      (PROPRIETARY_TLV_BASE_ID + 238U)
+#define TLV_TYPE_POWER_TABLE      (PROPRIETARY_TLV_BASE_ID + 262U)
+#define TLV_TYPE_POWER_TABLE_ATTR (PROPRIETARY_TLV_BASE_ID + 317U)
+/** HostCmd_DS_CHAN_REGION_CFG */
+typedef MLAN_PACK_START struct _HostCmd_DS_CHAN_REGION_CFG
+{
+    /** Action */
+    t_u16 action;
+} MLAN_PACK_END HostCmd_DS_CHAN_REGION_CFG;
+#endif
+
+/**
+ * @brief 802.11h Local Power Constraint NXP extended TLV
+ */
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypesHeader_t header; /**< NXP TLV header: ID/Len */
+    t_u8 chan;                  /**< Channel local constraint applies to */
+
+    /** Power constraint included in beacons and used by fw to offset 11d info */
+    t_u8 constraint;
+
+} MLAN_PACK_END MrvlIEtypes_LocalPowerConstraint_t;
+
+/*
+ *
+ * Data structures for driver/firmware command processing
+ *
+ */
+
+/**  TPC Info structure sent in CMD_802_11_TPC_INFO command to firmware */
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypes_LocalPowerConstraint_t local_constraint; /**< Local constraint */
+    MrvlIEtypes_PowerCapability_t power_cap;             /**< Power Capability */
+
+} MLAN_PACK_END HostCmd_DS_802_11_TPC_INFO;
+
+/**  TPC Request structure sent in CMD_802_11_TPC_ADAPT_REQ command to firmware */
+typedef MLAN_PACK_START struct
+{
+    t_u8 dest_mac[MLAN_MAC_ADDR_LENGTH]; /**< Destination STA address  */
+    t_u16 timeout;                       /**< Response timeout in ms */
+    t_u8 rate_index;                     /**< IEEE Rate index to send request */
+
+} MLAN_PACK_END HostCmd_TpcRequest;
+
+/**  TPC Response structure received from the CMD_802_11_TPC_ADAPT_REQ command */
+typedef MLAN_PACK_START struct
+{
+    t_u8 tpc_ret_code; /**< Firmware command result status code */
+    t_s8 tx_power;     /**< Reported TX Power from the TPC Report element */
+    t_s8 link_margin;  /**< Reported link margin from the TPC Report element */
+    t_s8 rssi;         /**< RSSI of the received TPC Report frame */
+
+} MLAN_PACK_END HostCmd_TpcResponse;
+
+/**  CMD_802_11_TPC_ADAPT_REQ substruct. Union of the TPC request and response */
+typedef MLAN_PACK_START union
+{
+    HostCmd_TpcRequest req;   /**< Request struct sent to firmware */
+    HostCmd_TpcResponse resp; /**< Response struct received from firmware */
+
+} MLAN_PACK_END HostCmd_DS_802_11_TPC_ADAPT_REQ;
+
+/**  CMD_802_11_CHAN_SW_ANN firmware command substructure */
+typedef MLAN_PACK_START struct
+{
+    t_u8 switch_mode;  /**< Set to 1 for a quiet switch request, no STA tx */
+    t_u8 new_chan;     /**< Requested new channel */
+    t_u8 switch_count; /**< Number of TBTTs until the switch is to occur */
+} MLAN_PACK_END HostCmd_DS_802_11_CHAN_SW_ANN;
+
+/**
+ * @brief Enumeration of measurement types, including max supported
+ *        enum for 11h/11k
+ */
+typedef MLAN_PACK_START enum _MeasType_t {
+    WLAN_MEAS_BASIC = 0,                      /**< 11h: Basic */
+    WLAN_MEAS_NUM_TYPES,                      /**< Number of enumerated measurements */
+    WLAN_MEAS_11H_MAX_TYPE = WLAN_MEAS_BASIC, /**< Max 11h measurement */
+
+} MLAN_PACK_END MeasType_t;
+
+/**
+ * @brief Mode octet of the measurement request element (7.3.2.21)
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 parallel : 1;           /**< 11k: series or parallel with previous meas */
+    t_u8 enable : 1;             /**< 11h: enable report/request bits */
+    t_u8 request : 1;            /**< 11h: en/disable requests of specified type */
+    t_u8 report : 1;             /**< 11h: en/disable report rcpt. of spec. type */
+    t_u8 duration_mandatory : 1; /**< 11k: duration spec. for meas. is mandatory */
+    t_u8 rsvd5_7 : 3;            /**< Reserved */
+
+} MLAN_PACK_END MeasReqMode_t;
+
+/**
+ * @brief Common measurement request structure (7.3.2.21.1 to 7.3.2.21.3)
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 channel;     /**< Channel to measure */
+    t_u64 start_time; /**< TSF Start time of measurement (0 for immediate) */
+    t_u16 duration;   /**< TU duration of the measurement */
+
+} MLAN_PACK_END MeasReqCommonFormat_t;
+
+/**
+ * @brief Basic measurement request structure (7.3.2.21.1)
+ */
+typedef MeasReqCommonFormat_t MeasReqBasic_t;
+
+/**
+ * @brief CCA measurement request structure (7.3.2.21.2)
+ */
+typedef MeasReqCommonFormat_t MeasReqCCA_t;
+
+/**
+ * @brief RPI measurement request structure (7.3.2.21.3)
+ */
+typedef MeasReqCommonFormat_t MeasReqRPI_t;
+
+/**
+ * @brief Union of the availble measurement request types.  Passed in the
+ *        driver/firmware interface.
+ */
+typedef union
+{
+    MeasReqBasic_t basic; /**< Basic measurement request */
+    MeasReqCCA_t cca;     /**< CCA measurement request */
+    MeasReqRPI_t rpi;     /**< RPI measurement request */
+
+} MeasRequest_t;
+
+/**
+ * @brief Mode octet of the measurement report element (7.3.2.22)
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 late : 1;               /**< Start TSF time missed for measurement */
+    t_u8 incapable : 1;          /**< Incapable of performing measurement */
+    t_u8 refused : 1;            /**< Measurement refused */
+    t_u8 rsvd3_7 : 5;            /**< Reserved */
+
+} MLAN_PACK_END MeasRptMode_t;
+
+/**
+ * @brief Basic measurement report (7.3.2.22.1)
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 channel;          /**< Channel to measured */
+    t_u64 start_time;      /**< Start time (TSF) of measurement */
+    t_u16 duration;        /**< Duration of measurement in TUs */
+    MeasRptBasicMap_t map; /**< Basic measurement report */
+
+} MLAN_PACK_END MeasRptBasic_t;
+
+/**
+ * @brief CCA measurement report (7.3.2.22.2)
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 channel;       /**< Channel to measured */
+    t_u64 start_time;   /**< Start time (TSF) of measurement */
+    t_u16 duration;     /**< Duration of measurement in TUs  */
+    t_u8 busy_fraction; /**< Fractional duration CCA indicated chan busy */
+
+} MLAN_PACK_END MeasRptCCA_t;
+
+/**
+ * @brief RPI measurement report (7.3.2.22.3)
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 channel;     /**< Channel to measured  */
+    t_u64 start_time; /**< Start time (TSF) of measurement */
+    t_u16 duration;   /**< Duration of measurement in TUs  */
+    t_u8 density[8];  /**< RPI Density histogram report */
+
+} MLAN_PACK_END MeasRptRPI_t;
+
+/**
+ * @brief Union of the availble measurement report types.  Passed in the
+ *        driver/firmware interface.
+ */
+typedef union
+{
+    MeasRptBasic_t basic; /**< Basic measurement report */
+    MeasRptCCA_t cca;     /**< CCA measurement report */
+    MeasRptRPI_t rpi;     /**< RPI measurement report */
+
+} MeasReport_t;
+
+/**
+ * @brief Structure passed to firmware to perform a measurement
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH]; /**< Reporting STA address */
+    t_u8 dialog_token;                   /**< Measurement dialog toke */
+    MeasReqMode_t req_mode;              /**< Report mode  */
+    MeasType_t meas_type;                /**< Measurement type */
+    MeasRequest_t req;                   /**< Measurement request data */
+
+} MLAN_PACK_END HostCmd_DS_MEASUREMENT_REQUEST;
+
+/**
+ * @brief Structure passed back from firmware with a measurement report,
+ *        also can be to send a measurement report to another STA
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH]; /**< Reporting STA address */
+    t_u8 dialog_token;                   /**< Measurement dialog token */
+    MeasRptMode_t rpt_mode;              /**< Report mode */
+    MeasType_t meas_type;                /**< Measurement type */
+    MeasReport_t rpt;                    /**< Measurement report data */
+
+} MLAN_PACK_END HostCmd_DS_MEASUREMENT_REPORT;
+
+typedef MLAN_PACK_START struct
+{
+    t_u16 startFreq;
+    t_u8 chanWidth;
+    t_u8 chanNum;
+
+} MLAN_PACK_END MrvlChannelDesc_t;
+
+typedef MLAN_PACK_START struct
+{
+    t_u8 modGroup;
+    t_u8 txPower;
+
+} MLAN_PACK_END MrvlChanTrpcEntry_t;
+
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypesHeader_t header; /**< Header */
+
+    MrvlChannelDesc_t chanDesc;
+    MrvlChanTrpcEntry_t chanTrpcEntry[10];
+
+} MLAN_PACK_END MrvlIEtypes_ChanTrpcCfg_t;
+
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypes_ChanTrpcCfg_t ChanTrpc[26];
+
+} MLAN_PACK_END MrvlIEtypes_ChanTrpc_t;
+
+typedef MLAN_PACK_START struct
+{
+    t_u16 action;
+    t_u16 reserved;
+    // MrvlIEtypes_ChanTrpc_t ChanTrpcG;
+    t_u8 tlv_buffer[1]; /** MrvlIEtypes_ChanTrpcCfg_t TLVs */
+} MLAN_PACK_END HostCmd_DS_CHAN_TRPC_CONFIG;
+
+typedef MLAN_PACK_START struct
+{
+    MrvlIEtypesHeader_t Header; /**< Header */
+
+    MeasRptBasicMap_t map;      /**< IEEE 802.11h basic meas report */
+} MLAN_PACK_END MrvlIEtypes_ChanRpt11hBasic_t;
+
+typedef MLAN_PACK_START struct
+{
+    MrvlChannelDesc_t chan_desc; /**< Channel band, number */
+    t_u32 millisec_dwell_time;   /**< Channel dwell time in milliseconds */
+} MLAN_PACK_END HostCmd_DS_CHAN_RPT_REQ;
+
+typedef MLAN_PACK_START struct
+{
+    t_u32 cmd_result;   /**< Rpt request command result (0 == SUCCESS) */
+    t_u64 start_tsf;    /**< TSF Measurement started */
+    t_u32 duration;     /**< Duration of measurement in microsecs */
+    t_u8 tlv_buffer[1]; /**< TLV Buffer */
+} MLAN_PACK_END HostCmd_DS_CHAN_RPT_RSP;
+
+#if CONFIG_WIFI_EU_CRYPTO
+typedef MLAN_PACK_START struct
+{
+    /* EncDec: 0-Decrypt, 1-Encrypt */
+    t_u16 EncDec;
+    /* Algorithm: 1-RC4, 2-AES, 3-AES_KEY_WRAP,4-AES-CCM */
+    t_u16 Algorithm;
+    /* KeyLength: Length of Key (bytes) */
+    t_u16 KeyLength;
+    /* Key: Key */
+    t_u8 Key[32];
+    /* NonceLength: Length of Nonce (bytes) */
+    t_u16 NonceLength;
+    /* Nonce: Nonce */
+    t_u8 Nonce[14];
+    /* AADLength: Length of AAD (bytes) */
+    t_u16 AADLength;
+    /* AAD: AAD */
+    t_u8 AAD[32];
+    /* DataType: DataType */
+    t_u16 DataType;
+    /* DataLength: Data Length */
+    t_u16 DataLength;
+    /* Data: Data */
+    t_u8 Data[1];
+} MLAN_PACK_END HostCmd_DS_EU_AES_CRYPTO;
+
+typedef MLAN_PACK_START struct
+{
+    /* EncDec: 0-Decrypt, 1-Encrypt */
+    t_u16 EncDec;
+    /* Algorithm: 1-RC4, 2-AES, 3-AES_KEY_WRAP, 4-AES-CCMP, 6-AES-GCMP */
+    t_u16 Algorithm;
+    /* KeyLength: Length of KeyIV (bytes) */
+    t_u16 KeyIVLength;
+    /* KeyIV: KeyIV */
+    t_u8 KeyIV[32];
+    /* KeyLength: Length of Key (bytes) */
+    t_u16 KeyLength;
+    /* Key: Key */
+    t_u8 Key[32];
+    /* DataType: DataType */
+    t_u16 DataType;
+    /* DataLength: Data Length */
+    t_u16 DataLength;
+    /* Data: Data */
+    t_u8 Data[1];
+} MLAN_PACK_END HostCmd_DS_EU_CRYPTO;
+
+typedef enum _crypto_algorithm
+{
+    CRYPTO_RC4      = 1,
+    CRYPTO_AES_ECB  = 2,
+    CRYPTO_AES_WRAP = 3,
+    CRYPTO_AES_CCMP = 4,
+    CRYPTO_AES_GCMP = 6,
+} crypto_algorithm;
+
+typedef MLAN_PACK_START struct
+{
+    /* KeyLength: Length of KeyIV (bytes) */
+    t_u16 KeyIVLength;
+    /* KeyIV: KeyIV */
+    t_u8 KeyIV[32];
+    /* NonceLength: Length of Nonce (bytes) */
+    t_u16 NonceLength;
+    /* Nonce: Nonce */
+    t_u8 Nonce[14];
+    /* AADLength: Length of AAD (bytes) */
+    t_u16 AADLength;
+    /* AAD: AAD */
+    t_u8 AAD[32];
+    /* KeyLength: Length of Key (bytes) */
+    t_u16 KeyLength;
+    /* Key: Key */
+    t_u8 Key[32];
+    /* DataLength: Length of Data (bytes) */
+    t_u16 *DataLength;
+    /* Data: Data */
+    t_u8 *Data;
+} MLAN_PACK_END EU_Crypto;
+#endif
+
+#if (CONFIG_IPS)
+typedef MLAN_PACK_START struct
+{
+    t_u32 enable;
+} MLAN_PACK_END HostCmd_DS_IPS_CONFIG;
+#endif
+
+/** statistics threshold */
+typedef MLAN_PACK_START struct
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** value */
+    t_u8 value;
+    /** reporting frequency */
+    t_u8 frequency;
+} MLAN_PACK_END MrvlIEtypes_BeaconHighRssiThreshold_t, MrvlIEtypes_BeaconLowRssiThreshold_t,
+    MrvlIEtypes_BeaconHighSnrThreshold_t, MrvlIEtypes_BeaconLowSnrThreshold_t, MrvlIEtypes_FailureCount_t,
+    MrvlIEtypes_DataLowRssiThreshold_t, MrvlIEtypes_DataHighRssiThreshold_t, MrvlIEtypes_DataLowSnrThreshold_t,
+    MrvlIEtypes_DataHighSnrThreshold_t, MrvlIETypes_PreBeaconMissed_t, MrvlIEtypes_BeaconsMissed_t;
+
+/** statistics threshold for LinkQuality */
+typedef MLAN_PACK_START struct
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Link SNR threshold (dB) */
+    t_u16 link_snr;
+    /** Link SNR frequency */
+    t_u16 link_snr_freq;
+    /* Second minimum rate value as per the rate table below */
+    t_u16 link_rate;
+    /* Second minimum rate frequency */
+    t_u16 link_rate_freq;
+    /* Tx latency value (us) */
+    t_u16 link_tx_latency;
+    /* Tx latency frequency */
+    t_u16 link_tx_lantency_freq;
+} MLAN_PACK_END MrvlIEtypes_LinkQualityThreshold_t;
+
+/** Supported operating classes element */
+typedef MLAN_PACK_START struct _MrvlIETypes_SuppOperClass_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Current operationg class **/
+    t_u8 current_oper_class;
+    /** Operating class list */
+    t_u8 oper_class[1];
+} MLAN_PACK_END MrvlIETypes_SuppOperClass_t;
+
+#if CONFIG_MULTI_CHAN
+typedef MLAN_PACK_START struct _MrvlTypes_DrcsTimeSlice_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Channel Index*/
+    t_u16 chan_idx;
+    /** Channel time (in TU) for chan_idx*/
+    t_u8 chantime;
+    /** Channel swith time (in TU) for chan_idx*/
+    t_u8 switchtime;
+    /** Undoze time (in TU) for chan_idx*/
+    t_u8 undozetime;
+    /** Rx traffic control scheme when channel switch*/
+    /** only valid for GC/STA interface*/
+    t_u8 mode;
+} MLAN_PACK_END MrvlTypes_DrcsTimeSlice_t;
+typedef MLAN_PACK_START struct _HostCmd_DS_MULTI_CHAN_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** Channel time */
+    t_u32 channel_time;
+    /** Buffer weight */
+    t_u8 buffer_weight;
+    /** TLV buffer */
+    t_u8 tlv_buf[];
+    /* t_u8 *tlv_buf; */
+} MLAN_PACK_END HostCmd_DS_MULTI_CHAN_CFG;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_DRCS_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** TLV buffer */
+    MrvlTypes_DrcsTimeSlice_t time_slicing;
+    /** TLV buffer */
+    MrvlTypes_DrcsTimeSlice_t drcs_buf[];
+    /* t_u8 *tlv_buf; */
+} MLAN_PACK_END HostCmd_DS_DRCS_CFG;
+
+typedef MLAN_PACK_START struct _HostCmd_DS_MULTI_CHAN_POLICY
+{
+    /** Action */
+    t_u16 action;
+    /** Multi-channel Policy */
+    t_u16 policy;
+} MLAN_PACK_END HostCmd_DS_MULTI_CHAN_POLICY;
+
+/** MrvlIEtypes_multi_chan_info_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_mutli_chan_info_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** multi channel operation status */
+    t_u16 status;
+    /** Tlv buffer */
+    t_u8 tlv_buffer[];
+} MLAN_PACK_END MrvlIEtypes_multi_chan_info_t;
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+/**Structure for FTM complete subevent*/
+typedef MLAN_PACK_START struct _wls_subevent_ftm_complete
+{
+    /** BSS Number */
+    t_u8 bssNum;
+    /** BSS Type */
+    t_u8 bssType;
+    /** MAC address of the responder */
+    t_u8 mac[MLAN_MAC_ADDR_LENGTH];
+    /** Average RTT */
+    t_u32 avg_rtt;
+    /** Average Clock offset */
+    t_u32 avg_clk_offset;
+    /** Measure start timestamp */
+    t_u32 meas_start_tsf;
+} MLAN_PACK_END wls_subevent_ftm_complete_t;
+
+/** Structure for FTM events*/
+typedef MLAN_PACK_START struct _wls_event_t
+{
+    /* No of bytes in packet including this field */
+    t_u16 length;
+    /* Type: Event (3) */
+    t_u16 type;
+    /** Event ID */
+    t_u16 event_id;
+    /** BSS index number for multiple BSS support */
+    t_u8 bss_index;
+    /** BSS type */
+    t_u8 bss_type;
+    /** sub event id */
+    t_u8 sub_event_id;
+    union
+    {
+        /** FTM Complete Sub event*/
+        wls_subevent_ftm_complete_t ftm_complete;
+    } e;
+} MLAN_PACK_END wls_event_t;
+
+/** Structure of FTM_SESSION_CFG_NTB_RANGING / FTM_SESSION_CFG_TB_RANGING TLV data*/
+typedef MLAN_PACK_START struct _ranging_cfg
+{
+    /** Indicates the channel BW for session*/
+    /*0: HE20, 1: HE40, 2: HE80, 3: HE80+80, 4: HE160, 5:HE160_SRF*/
+    t_u8 format_bw;
+    /** indicates for bandwidths less than or equal to 80 MHz the maximum number of space-time streams to be used in
+     * DL/UL NDP frames in the session*/
+    t_u8 max_i2r_sts_upto80;
+    /**indicates for bandwidths less than or equal to 80 MHz the maximum number of space-time streams to be used in
+     * DL/UL NDP frames in the session*/
+    t_u8 max_r2i_sts_upto80;
+    /**Specify measurement freq in Hz to calculate measurement interval*/
+    t_u8 az_measurement_freq;
+    /**Indicates the number of measurements to be done for session*/
+    t_u8 az_number_of_measurements;
+    /** Initator lmr feedback */
+    t_u8 i2r_lmr_feedback;
+    /**Include location civic request (Expect location civic from responder)*/
+    t_u8 civic_req;
+    /**Include LCI request (Expect LCI info from responder)*/
+    t_u8 lci_req;
+} MLAN_PACK_END ranging_cfg_t;
+
+/** Structure of FTM_SESSION_CFG TLV data*/
+typedef MLAN_PACK_START struct _ftm_session_cfg
+{
+    /** Indicates how many burst instances are requested for the FTM session*/
+    t_u8 burst_exponent;
+    /** Indicates the duration of a burst instance*/
+    t_u8 burst_duration;
+    /**Minimum time between consecutive FTM frames*/
+    t_u8 min_delta_FTM;
+    /**ASAP/non-ASAP casel*/
+    t_u8 is_ASAP;
+    /**Number of FTMs per burst*/
+    t_u8 per_burst_FTM;
+    /**FTM channel spacing: HT20/HT40/VHT80/... */
+    t_u8 channel_spacing;
+    /**Indicates the interval between two consecutive burst instances*/
+    t_u16 burst_period;
+} MLAN_PACK_END ftm_session_cfg_t;
+
+/** Structure for FTM_SESSION_CFG_LOCATION_CIVIC TLV data*/
+typedef MLAN_PACK_START struct _civic_loc_cfg
+{
+    /**Civic location type*/
+    t_u8 civic_location_type;
+    /**Country code*/
+    t_u16 country_code;
+    /**Civic address type*/
+    t_u8 civic_address_type;
+    /**Civic address length*/
+    t_u8 civic_address_length;
+    /**Civic Address*/
+    t_u8 civic_address[256];
+} MLAN_PACK_END civic_loc_cfg_t;
+
+/** Structure for FTM_SESSION_CFG_LCI TLV data*/
+typedef MLAN_PACK_START struct _lci_cfg
+{
+    /** known longitude*/
+    double longitude;
+    /** known Latitude*/
+    double latitude;
+    /** known altitude*/
+    double altitude;
+    /** known Latitude uncertainty*/
+    t_u8 lat_unc;
+    /** known Longitude uncertainty*/
+    t_u8 long_unc;
+    /** Known Altitude uncertainty*/
+    t_u8 alt_unc;
+    /** 1 word for additional Z information */
+    t_u32 z_info;
+} MLAN_PACK_END lci_cfg_t;
+
+/** Structure for FTM_SESSION_CFG_NTB_RANGING TLV*/
+typedef MLAN_PACK_START struct _ranging_cfg_tlv
+{
+    /** Type*/
+    t_u16 type;
+    /** Length*/
+    t_u16 len;
+    /** Value*/
+    ranging_cfg_t val;
+} MLAN_PACK_END ranging_cfg_tlv_t;
+
+/** Structure for FTM_SESSION_CFG  TLV*/
+typedef MLAN_PACK_START struct _ftm_session_cfg_tlv
+{
+    /** Type*/
+    t_u16 type;
+    /** Length*/
+    t_u16 len;
+    /** Value*/
+    ftm_session_cfg_t val;
+    t_u8 civic_req;
+    t_u8 lci_req;
+} MLAN_PACK_END ftm_session_cfg_tlv_t;
+
+/** Structure for FTM_SESSION_CFG_LOCATION_CIVIC TLV*/
+typedef MLAN_PACK_START struct _civic_loc_tlv
+{
+    /** Type*/
+    t_u16 type;
+    /** Length*/
+    t_u16 len;
+    /** Value*/
+    civic_loc_cfg_t val;
+} MLAN_PACK_END civic_loc_tlv_t;
+
+/** Structure for FTM_SESSION_CFG_LCI TLV*/
+typedef MLAN_PACK_START struct _lci_tlv
+{
+    /** Type*/
+    t_u16 type;
+    /** Length*/
+    t_u16 len;
+    /** Value*/
+    lci_cfg_t val;
+} MLAN_PACK_END lci_tlv_t;
+
+/** Structure for DOT11MC FTM_SESSION_CFG */
+typedef MLAN_PACK_START struct _dot11mc_ftm_cfg
+{
+    /** FTM session cfg*/
+    ftm_session_cfg_tlv_t sess_tlv;
+    /** Location Request cfg*/
+    lci_tlv_t lci_tlv;
+    /** Civic location cfg*/
+    civic_loc_tlv_t civic_tlv;
+
+} MLAN_PACK_END dot11mc_ftm_cfg_t;
+
+/** Structure for DOT11AZ FTM_SESSION_CFG */
+typedef MLAN_PACK_START struct _dot11az_ftmcfg_ntb_t
+{
+    /** NTB session cfg */
+    ranging_cfg_tlv_t range_tlv;
+} MLAN_PACK_END dot11az_ftm_cfg_t;
+
+/** Type definition for hostcmd_ftm_session_cfg */
+typedef MLAN_PACK_START struct _HostCmd_FTM_SESSION_CFG
+{
+    /** 0:Get, 1:Set */
+    t_u16 action;
+    /** FTM_SESSION_CFG_TLVs*/
+    union
+    {
+        /**11az cfg*/
+        dot11az_ftm_cfg_t cfg_11az;
+        /** 11mc cfg*/
+        dot11mc_ftm_cfg_t cfg_11mc;
+    } tlv;
+} MLAN_PACK_END HostCmd_FTM_SESSION_CFG;
+
+/** Type definition for hostcmd_unassoc_ftm_cfg */
+typedef MLAN_PACK_START struct _Hostcmd_DOT11MC_UNASSOC_FTM_CFG
+{
+    /** 0: Get, 1: Set */
+    t_u16 action;
+    /** 0: Disable, 1: Enable */
+    t_u16 config;
+} MLAN_PACK_END HostCmd_DOT11MC_UNASSOC_FTM_CFG;
+
+/** Type definition for hostcmd_ftm_session_ctrl */
+typedef MLAN_PACK_START struct _Hostcmd_FTM_SESSION_CTRL
+{
+    /** 0: Not used, 1: Start, 2: Stop*/
+    t_u16 action;
+    /*FTM for ranging*/
+    t_u8 for_ranging;
+    /** Mac address of the peer with whom FTM session is required*/
+    t_u8 peer_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Channel on which FTM must be started */
+    t_u8 chan;
+    /** Band on which FTM must be started */
+    t_u8 chanBand;
+} MLAN_PACK_END HostCmd_FTM_SESSION_CTRL;
+
+#if CONFIG_WLS_CSI_PROC
+typedef MLAN_PACK_START struct _CSI_EVENT_HEADER_t
+{
+    /** No of bytes in packet including this field */
+    t_u16 length;
+    /** Type: Event (3) */
+    t_u16 type;
+    /** Event ID */
+    t_u16 event_id;
+    /** BSS index number for multiple BSS support */
+    t_u8 bss_index;
+    /** BSS type */
+    t_u8 bss_type;
+} MLAN_PACK_END csi_event_t;
+
+typedef MLAN_PACK_START struct _Hostcmd_WLS_CSI_ACK
+{
+    t_u16 action;
+    t_u16 sub_id;
+    t_u32 ack;
+    t_u32 phase_roll;
+    t_u32 firstpath_delay;
+    t_u32 fft_size_pointer;
+    t_u32 csi_tsf;
+} MLAN_PACK_END HostCmd_WLS_CSI_ACK;
+#endif
+
+#endif
+
+
+#if CONFIG_CSI
+/** MrvlIEtypes_channel_bandcfg_t */
+typedef MLAN_PACK_START struct _MrvlIEtypes_channel_bandcfg_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Enable getting CSI data on special channel */
+    t_u8 csi_monitor_enable;
+    /** CSI data received in cfg channel with mac addr filter, not only RA is us or other*/
+    t_u8 ra4us;
+    /** bandconfig*/
+    t_u8 bandconfig;
+    /** channel num */
+    t_u8 channel;
+} MLAN_PACK_END MrvlIEtypes_channel_bandcfg_t;
+
+/**
+ * @brief Structure passed to firmware to config csi info
+ */
+typedef MLAN_PACK_START struct _HostCmd_DS_CSI_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** Header ID*/
+    t_u32 head_id;
+    /** Tail ID */
+    t_u32 tail_id;
+    /** Number of CSI filters */
+    t_u8 csi_filter_cnt;
+    /** Chip ID */
+    t_u8 chip_id;
+    /** CSI filters */
+    wifi_csi_filter_t csi_filter[CSI_FILTER_MAX];
+    /**channel and bandconfig*/
+    MrvlIEtypes_channel_bandcfg_t channel_bandconfig;
+} MLAN_PACK_END HostCmd_DS_CSI_CFG;
+#endif
+
+/** HostCmd_DS_BOOT_SLEEP */
+typedef MLAN_PACK_START struct _HostCmd_DS_BOOT_SLEEP
+{
+    /** Set or Get */
+    t_u16 action;
+    /** 1 on or 0 off */
+    t_u16 enable;
+} MLAN_PACK_END HostCmd_DS_BOOT_SLEEP;
+
+#if CONFIG_TSP
+typedef MLAN_PACK_START struct _HostCmd_DS_TSP_CFG
+{
+    /** Action */
+    t_u16 action;
+    /** enable/disabel tsp algothrim*/
+    t_u16 thermalPowerMgmtenable;
+    /** backoff*/
+    t_u32 powerMgmtBackoff;
+    /** high Threshold*/
+    t_u32 highPwrBOThrshld;
+    /** low Threshold*/
+    t_u32 lowPwrBOThrshld;
+    /** DUTY_CYC_STEP */
+    t_u32 dutycycstep;
+    /** DUTY_CYC_MIN */
+    t_u32 dutycycmin;
+    /** HIGH_THRESHOLD_TEMP*/
+    int highthrtemp;
+    /** LOW_THRESHOLD_TEMP*/
+    int lowthrtemp;
+    /** CAU TSEN temperature */
+    int currCAUTemp;
+    /** RFU temperature */
+    int currRFUTemp;
+} MLAN_PACK_END HostCmd_DS_TSP_CFG;
+
+typedef MLAN_PACK_START struct _TSP_CFG
+{
+    /** enable/disabel tsp algothrim*/
+    t_u16 *thermalPowerMgmtenable;
+    /** backoff*/
+    t_u32 *powerMgmtBackoff;
+    /** high Threshold*/
+    t_u32 *highPwrBOThrshld;
+    /** low Threshold*/
+    t_u32 *lowPwrBOThrshld;
+    /** DUTY_CYC_STEP */
+    t_u32 *dutycycstep;
+    /** DUTY_CYC_MIN */
+    t_u32 *dutycycmin;
+    /** HIGH_THRESHOLD_TEMP*/
+    int *highthrtemp;
+    /** LOW_THRESHOLD_TEMP*/
+    int *lowthrtemp;
+    /** CAU TSEN temperature */
+    int *currCAUTemp;
+    /** RFU temperature */
+    int *currRFUTemp;
+} MLAN_PACK_END TSP_CFG;
+#endif
+
+#if CONFIG_COEX_DUTY_CYCLE
+/** TLV type : Coex duty cycle */
+#define TLV_TYPE_COEX_DUTY_CYCLE (PROPRIETARY_TLV_BASE_ID + 0x290)
+
+/** MrvlIETypes_SingleAntDutyCycle_Config_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_SingleAntDutyCycle_Config_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Enable: 0x1 generic time, 0x2 Enable Dutycycle */
+    t_u16 enabled;
+    /** Enter value in Units (1Unit = 1ms), should be no more than wlanTime */
+    t_u16 nbTime;
+    /** Enter value in Units (1Unit = 1ms) */
+    t_u16 wlanTime;
+} MLAN_PACK_END MrvlIETypes_SingleAntDutyCycle_Config_t;
+
+/** HostCmd_SIGNLE_ANT_DUTY_CYCLE structure */
+typedef MLAN_PACK_START struct _HostCmd_SIGNLE_ANT_DUTY_CYCLE
+{
+    /** Action */
+    t_u16 action;
+    /** Reserved field */
+    t_u16 reserved;
+    /** Single Ant Duty Cycle Configuration Data */
+    MrvlIETypes_SingleAntDutyCycle_Config_t single_ant_cfg_data;
+} MLAN_PACK_END HostCmd_SIGNLE_ANT_DUTY_CYCLE;
+
+/** MrvlIETypes_DualAntDutyCycle_Config_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_DualAntDutyCycle_Config_t
+{
+    /** Header */
+    MrvlIEtypesHeader_t header;
+    /** Enable: 0x1 generic time, 0x2 Enable Dutycycle */
+    t_u16 enabled;
+    /** Enter value in Units (1Unit = 1ms), should be no more than TotalTime */
+    t_u16 nbTime;
+    /** Enter value in Units (1Unit = 1ms) */
+    t_u16 wlanTime;
+    /** Enter value in Units (1Unit = 1ms) */
+    t_u16 wlanBlockTime;
+} MLAN_PACK_END MrvlIETypes_DualAntDutyCycle_Config_t;
+
+/** HostCmd_DUAL_ANT_DUTY_CYCLE structure */
+typedef MLAN_PACK_START struct _HostCmd_DUAL_ANT_DUTY_CYCLE
+{
+    t_u16 action;
+    t_u16 reserved;
+    /** Dual Ant Duty Cycle Configuration Data */
+    MrvlIETypes_DualAntDutyCycle_Config_t dual_ant_cfg_data;
+} MLAN_PACK_END HostCmd_DUAL_ANT_DUTY_CYCLE;
+#endif
+
+#if (CONFIG_EXTERNAL_COEX_PTA) || (CONFIG_IMD3_CFG)
+
+/** HostCmd_EXTERNAL_COEX_PTA structure */
+typedef MLAN_PACK_START struct _MrvlIETypes_Coex_params_t
+{
+    /** External coex pta type */
+    t_u16 tlv_type;
+    /** Externel coex pta tlv length */
+    t_u16 tlv_length;
+} MLAN_PACK_END MrvlIETypes_Coex_params_t;
+#endif
+
+#if CONFIG_EXTERNAL_COEX_PTA
+/** MrvlIETypes_DualAntDutyCycle_Config_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_ExternalCoexPta_Config_t
+{
+    MrvlIETypes_Coex_params_t param;
+    /** Enable: 0x01, Disable: 0x00 */
+    t_u8 enabled;
+    /** Enable ExtWifiBtArb: 0x01, Disable ExWifiBtArb: 0x00 */
+    t_u8 ext_WifiBtArb;
+    /** Active high: 0x00, Active low: 0x01 */
+    t_u8 polGrantPin;
+    /**  Enable PriPtaInt: 0x01, Disable PriPtaInt: 0x00 */
+    t_u8 enable_PriPtaInt;
+    /** State input disable: 0x00, State info is from state pin: 0x01, State info is sampled on priority pin: 0x02 */
+    t_u8 enable_StatusFromPta;
+    /** Timing to sample Priority bit */
+    t_u16 setPriSampTiming;
+    /** Timing to sample Tx/Rx info */
+    t_u16 setStateInfoSampTiming;
+    /** Enable external traffic Tx/Rx Priority: 0x01, Disable external traffic Tx/Rx Priority: 0x00 */
+    t_u8 extRadioTrafficPrio;
+    /** Enable wci-2 interface: 0x01, Disable wci-2 interface: 0x00 */
+    t_u8 extCoexHwIntWci2;
+} MLAN_PACK_END MrvlIETypes_ExternalCoexPta_Config_t;
+
+/** HostCmd_EXTERNAL_COEX_PTA structure */
+typedef MLAN_PACK_START struct _HostCmd_EXTERNAL_COEX_PTA
+{
+    /** Get: 0x00, Set: 0x01 */
+    t_u16 action;
+    /** Reserved filed */
+    t_u16 reserved;
+    /** External Coex Pta Configuration Data */
+    MrvlIETypes_ExternalCoexPta_Config_t coex_pta_cfg_data;
+} MLAN_PACK_END HostCmd_EXTERNAL_COEX_PTA;
+#endif
+
+#if CONFIG_IMD3_CFG
+/** MrvlIETypes_IMD_Config_t */
+typedef MLAN_PACK_START struct _MrvlIETypes_IMD_Config_t
+{
+    /** Tlv param*/
+    MrvlIETypes_Coex_params_t param;
+    /** Rbc mode*/
+    t_u8 rbc_mode;
+    /** Reserved filed*/
+    t_u8 reserved;
+    /** Dynamic Mode */
+    t_u16 DynamicMode;
+} MLAN_PACK_END MrvlIETypes_IMD_Config_t;
+/** HostCmd_IMD3_CFG structure */
+typedef MLAN_PACK_START struct _HostCmd_IMD3_CFG
+{
+    /** Get: 0x00, Set: 0x01 */
+    t_u16 action;
+    /** Reserved filed */
+    t_u16 reserved;
+    /** Imd config */
+    MrvlIETypes_IMD_Config_t imd_cfg;
+} MLAN_PACK_END HostCmd_IMD3_CFG;
+#endif
+
+/** HostCmd_DS_80211_TX_FRAME */
+typedef MLAN_PACK_START struct _HostCmd_DS_80211_TX_FRAME
+{
+    /** Action Set or get */
+    t_u16 action;
+    /** status */
+    t_u16 status;
+    /** BandConfig */
+    t_u8 band_config;
+    /** channel */
+    t_u8 channel;
+    /** reserved */
+    t_u32 reserved;
+    /** buffer include TxPD and full Tx packet */
+    t_u8 buffer[];
+} MLAN_PACK_END HostCmd_DS_80211_TX_FRAME;
+
+/** HostCmd_DS_COMMAND */
+/* Note in case the fixed header of 8 bytes is modified please modify WIFI_HOST_CMD_FIXED_HEADER_LEN too */
+typedef MLAN_PACK_START struct _HostCmd_DS_COMMAND
+{
+    /** Command Header : Command */
+    t_u16 command;
+    /** Command Header : Size */
+    t_u16 size;
+    /** Command Header : Sequence number */
+    t_u16 seq_num;
+    /** Command Header : Result */
+    t_u16 result;
+    /** Command Body */
+    union
+    {
+        /** Hardware specifications */
+        HostCmd_DS_GET_HW_SPEC hw_spec;
+        /** Cfg data */
+        HostCmd_DS_802_11_CFG_DATA cfg_data;
+        /** MAC control */
+        HostCmd_DS_MAC_CONTROL mac_ctrl;
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+        /** Test Independent reset */
+        HostCmd_DS_IND_RST ind_rst;
+        /** GPIO Independent reset configure */
+        HostCmd_DS_INDEPENDENT_RESET_CFG ind_rst_cfg;
+#endif
+        /** MAC address */
+        HostCmd_DS_802_11_MAC_ADDRESS mac_addr;
+        /** MAC muticast address */
+        HostCmd_DS_MAC_MULTICAST_ADR mc_addr;
+        /** Get log */
+        HostCmd_DS_802_11_GET_LOG get_log;
+        /** RSSI information */
+        HostCmd_DS_802_11_RSSI_INFO rssi_info;
+        /** RSSI information response */
+        HostCmd_DS_802_11_RSSI_INFO_RSP rssi_info_rsp;
+        /** SNMP MIB */
+        HostCmd_DS_802_11_SNMP_MIB smib;
+        /** Radio control */
+        HostCmd_DS_802_11_RADIO_CONTROL radio;
+        /** RF channel */
+        HostCmd_DS_802_11_RF_CHANNEL rf_channel;
+        /** Tx rate query */
+        HostCmd_TX_RATE_QUERY tx_rate;
+        /** Tx rate configuration */
+        HostCmd_DS_TX_RATE_CFG tx_rate_cfg;
+        /** Tx power configuration */
+        HostCmd_DS_TXPWR_CFG txp_cfg;
+        /** RF Tx power configuration */
+        HostCmd_DS_802_11_RF_TX_POWER txp;
+        /** CW Mode: Tx CW Level control */
+        HostCmd_DS_CW_MODE_CTRL cwmode;
+        /** RF antenna */
+        HostCmd_DS_802_11_RF_ANTENNA antenna;
+#if CONFIG_NET_MONITOR
+        /** Net Monitor Mode command */
+        HostCmd_DS_802_11_NET_MONITOR net_mon;
+#endif
+        /** Enhanced power save command */
+        HostCmd_DS_802_11_PS_MODE_ENH psmode_enh;
+        HostCmd_DS_802_11_HS_CFG_ENH opt_hs_cfg;
+        /** Scan */
+        HostCmd_DS_802_11_SCAN scan;
+#if CONFIG_EXT_SCAN_SUPPORT
+        /** Extended Scan */
+        HostCmd_DS_802_11_SCAN_EXT ext_scan;
+#endif
+
+        /** Mgmt frame subtype mask */
+        HostCmd_DS_RX_MGMT_IND rx_mgmt_ind;
+        /** Scan response */
+        HostCmd_DS_802_11_SCAN_RSP scan_resp;
+
+        HostCmd_DS_802_11_BG_SCAN_CONFIG bg_scan_config;
+        HostCmd_DS_802_11_BG_SCAN_QUERY bg_scan_query;
+        HostCmd_DS_802_11_BG_SCAN_QUERY_RSP bg_scan_query_resp;
+        HostCmd_DS_SUBSCRIBE_EVENT subscribe_event;
+        HostCmd_DS_OTP_USER_DATA otp_user_data;
+        /** Associate */
+        HostCmd_DS_802_11_ASSOCIATE associate;
+
+        /** Associate response */
+        HostCmd_DS_802_11_ASSOCIATE_RSP associate_rsp;
+        /** Deauthenticate */
+        HostCmd_DS_802_11_DEAUTHENTICATE deauth;
+        /** Ad-Hoc start */
+        HostCmd_DS_802_11_AD_HOC_START adhoc_start;
+        /** Ad-Hoc start result */
+        HostCmd_DS_802_11_AD_HOC_START_RESULT adhoc_start_result;
+        /** Ad-Hoc join result */
+        HostCmd_DS_802_11_AD_HOC_JOIN_RESULT adhoc_join_result;
+        /** Ad-Hoc join */
+        HostCmd_DS_802_11_AD_HOC_JOIN adhoc_join;
+        /** Domain information */
+        HostCmd_DS_802_11D_DOMAIN_INFO domain_info;
+        /** Domain information response */
+        HostCmd_DS_802_11D_DOMAIN_INFO_RSP domain_info_resp;
+        HostCmd_DS_802_11_TPC_ADAPT_REQ tpc_req;
+        HostCmd_DS_802_11_TPC_INFO tpc_info;
+        HostCmd_DS_802_11_CHAN_SW_ANN chan_sw_ann;
+        HostCmd_DS_CHAN_RPT_REQ chan_rpt_req;
+        HostCmd_DS_MEASUREMENT_REQUEST meas_req;
+        HostCmd_DS_MEASUREMENT_REPORT meas_rpt;
+        /** Add BA request */
+        HostCmd_DS_11N_ADDBA_REQ add_ba_req;
+        /** Add BA response */
+        HostCmd_DS_11N_ADDBA_RSP add_ba_rsp;
+        /** Delete BA entry */
+        HostCmd_DS_11N_DELBA del_ba;
+        /** Tx buffer configuration */
+        HostCmd_DS_TXBUF_CFG tx_buf;
+        /** AMSDU Aggr Ctrl configuration */
+        HostCmd_DS_AMSDU_AGGR_CTRL amsdu_aggr_ctrl;
+        /** 11n configuration */
+        HostCmd_DS_11N_CFG htcfg;
+        /** HostCmd_DS_11AC_CFG */
+        HostCmd_DS_11AC_CFG vhtcfg;
+#if CONFIG_11AX
+        /** HostCmd_DS_11AX_CFG */
+        HostCmd_DS_11AX_CFG axcfg;
+#if CONFIG_11AX_TWT
+        /** HostCmd_DS_TWT_CFG */
+        HostCmd_DS_TWT_CFG twtcfg;
+#endif /* CONFIG_11AX_TWT  */
+#if CONFIG_MMSF
+        /* HostCmd_DS_MMSF_CFG*/
+        HostCmd_DS_MMSF_CFG mmsf_cfg;
+#endif
+#endif /* CONFIG_11AX */
+#if CONFIG_WIFI_RECOVERY
+        /* HostCmd_DS_TMRC_CFG*/
+        HostCmd_DS_TMRC_CFG tmrc_cfg;
+#endif
+        /** WMM status get */
+        HostCmd_DS_WMM_GET_STATUS get_wmm_status;
+        /** WMM ADDTS */
+        HostCmd_DS_WMM_ADDTS_REQ add_ts;
+        /** WMM DELTS */
+        HostCmd_DS_WMM_DELTS_REQ del_ts;
+        /** WMM set/get queue config */
+        HostCmd_DS_WMM_QUEUE_CONFIG queue_config;
+        /** WMM on/of/get queue statistics */
+        HostCmd_DS_WMM_QUEUE_STATS queue_stats;
+        /** WMM get traffic stream status */
+        HostCmd_DS_WMM_TS_STATUS ts_status;
+        /** WMM param config*/
+        HostCmd_DS_WMM_PARAM_CONFIG param_config;
+        /** Key material */
+        HostCmd_DS_802_11_KEY_MATERIAL key_material;
+#if CONFIG_GTK_REKEY_OFFLOAD
+        /** GTK Rekey parameters */
+        HostCmd_DS_GTK_REKEY_PARAMS gtk_rekey;
+#endif
+        /** E-Supplicant PSK */
+        HostCmd_DS_802_11_SUPPLICANT_PMK esupplicant_psk;
+        /** E-Supplicant profile */
+        HostCmd_DS_802_11_SUPPLICANT_PROFILE esupplicant_profile;
+        /** Extended version */
+        HostCmd_DS_VERSION_EXT verext;
+        /** Adhoc Coalescing */
+        HostCmd_DS_802_11_IBSS_STATUS ibss_coalescing;
+        /** Mgmt IE list configuration */
+        HostCmd_DS_MGMT_IE_LIST_CFG mgmt_ie_list;
+        /** System clock configuration */
+        HostCmd_DS_ECL_SYSTEM_CLOCK_CONFIG sys_clock_cfg;
+        /** MAC register access */
+        HostCmd_DS_MAC_REG_ACCESS mac_reg;
+        /** BBP register access */
+        HostCmd_DS_BBP_REG_ACCESS bbp_reg;
+        /** RF register access */
+        HostCmd_DS_RF_REG_ACCESS rf_reg;
+        /** EEPROM register access */
+        HostCmd_DS_802_11_EEPROM_ACCESS eeprom;
+        /** Memory access */
+        HostCmd_DS_MEM_ACCESS mem;
+        /** Bridge mode */
+        HostCmd_BRIDGE_MODE bridge_mode;
+        /** Auto Reconnect */
+        HostCmd_DS_AUTO_RECONNECT auto_reconnect;
+        /** HS Wakeup Reason */
+        HostCmd_DS_HS_WAKEUP_REASON hs_wakeup_reason;
+        /** Inactivity timeout extend */
+        HostCmd_DS_INACTIVITY_TIMEOUT_EXT inactivity_to;
+        HostCmd_DS_SYS_CONFIG sys_config;
+        HostCmd_DS_SYS_INFO sys_info;
+        HostCmd_DS_STA_DEAUTH sta_deauth;
+        HostCmd_DS_STA_LIST sta_list;
+        HostCmd_DS_POWER_MGMT_EXT pm_cfg;
+        HostCmd_DS_REPORT_MIC report_mic;
+        HostCmd_DS_PMF_PARAMS pmf_params;
+#ifdef SD8801
+        HostCmd_DS_ACS_CONFIG acs_scan;
+#else
+        HostCMD_DS_APCMD_ACS_SCAN acs_scan;
+#endif
+        HostCmd_DS_ADD_STATION sta_info;
+        /** Sleep period command */
+        HostCmd_DS_802_11_SLEEP_PERIOD sleep_pd;
+        /** Sleep params command */
+        HostCmd_DS_802_11_SLEEP_PARAMS sleep_param;
+
+        /** SDIO GPIO interrupt config command */
+        HostCmd_DS_SDIO_GPIO_INT_CONFIG sdio_gpio_int;
+        HostCmd_DS_SDIO_PULL_CTRL sdio_pull_ctl;
+        HostCmd_DS_SET_BSS_MODE bss_mode;
+        HostCmd_DS_CMD_TX_DATA_PAUSE tx_data_pause;
+        HostCmd_DS_REMAIN_ON_CHANNEL remain_on_chan;
+#ifdef WLAN_LOW_POWER_ENABLE
+        HostCmd_CONFIG_LOW_PWR_MODE low_pwr_mode_cfg;
+#endif /* WLAN_LOW_POWER_ENABLE */
+        HostCmd_CONFIG_ED_MAC_MODE ed_mac_mode_cfg;
+        HostCmd_DS_CHAN_TRPC_CONFIG chan_trpc_cfg;
+        HostCmd_DS_TSF tsf_cfg;
+#if CONFIG_WIFI_CLOCKSYNC
+        HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG gpio_tsf_latch;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+        HostCmd_DS_TBTT_OFFSET tbtt_offset;
+#if CONFIG_RF_TEST_MODE
+        HostCmd_DS_MFG_CMD_GENERIC_CFG mfg_generic_cfg;
+        HostCmd_DS_MFG_CMD_TX_FRAME2 mfg_tx_frame2;
+        HostCmd_DS_MFG_CMD_TX_CONT mfg_tx_cont;
+        HostCmd_DS_MFG_CMD_HE_TBTX_T mfg_he_power;
+        HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T mfg_tx_trigger_config;
+        HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T mfg_otp_mac_addr_rd_wr;
+        HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T mfg_otp_cal_data_rd_wr;
+#endif
+#if CONFIG_WIFI_TX_PER_TRACK
+        HostCmd_DS_TX_RX_PKT_STATS pkt_stats;
+#endif
+#if CONFIG_TX_RX_HISTOGRAM
+        HostCmd_DS_TX_RX_HISTOGRAM histogram;
+#endif
+#ifdef OTP_CHANINFO
+        HostCmd_DS_CHAN_REGION_CFG reg_cfg;
+#endif
+#if CONFIG_WIFI_EU_CRYPTO
+        HostCmd_DS_EU_AES_CRYPTO eu_aes_crypto;
+        HostCmd_DS_EU_CRYPTO eu_crypto;
+#endif
+
+#if CONFIG_11AX
+        HostCmd_DS_11AX_CMD_CFG axcmd;
+#endif
+#ifdef SD8801
+        HostCmd_DS_ExtBLECoex_Config_t ext_ble_coex_cfg;
+#endif
+#if CONFIG_MULTI_CHAN
+        HostCmd_DS_MULTI_CHAN_CFG multi_chan_cfg;
+        HostCmd_DS_MULTI_CHAN_POLICY multi_chan_policy;
+        HostCmd_DS_DRCS_CFG drcs_cfg;
+#endif
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+        /** hostcmd for unassociated FTM configuration user command */
+        HostCmd_DOT11MC_UNASSOC_FTM_CFG unassoc_ftm_cfg;
+        /** hostcmd for session_ctrl user command */
+        HostCmd_FTM_SESSION_CTRL ftm_session_ctrl;
+        /** hostcmd for session_cfg user command */
+        HostCmd_FTM_SESSION_CFG ftm_session_cfg;
+#if CONFIG_WLS_CSI_PROC
+        HostCmd_WLS_CSI_ACK wls_csi_ack;
+#endif
+#endif
+#if CONFIG_TX_AMPDU_PROT_MODE
+        HostCmd_DS_CMD_TX_AMPDU_PROT_MODE tx_ampdu_prot_mode;
+#endif
+#if (CONFIG_IPS)
+        HostCmd_DS_IPS_CONFIG ips_config;
+#endif
+#if CONFIG_CSI
+        HostCmd_DS_CSI_CFG csi_params;
+#endif
+
+        /** boot sleep configure */
+        HostCmd_DS_BOOT_SLEEP boot_sleep;
+
+#if CONFIG_RX_ABORT_CFG
+        HostCmd_DS_RX_ABORT_CFG rx_abort_cfg;
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+        HostCmd_DS_RX_ABORT_CFG_EXT rx_abort_cfg_ext;
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+        HostCmd_DS_CCK_DESENSE_CFG cck_desense_cfg;
+#endif
+
+#if CONFIG_FW_VDLL
+        uint8_t *vdll_cmd_mem;
+#endif
+#if CONFIG_TSP
+        HostCmd_DS_TSP_CFG tsp_cfg;
+#endif
+#if CONFIG_CLOUD_KEEP_ALIVE
+        HostCmd_DS_AUTO_TX auto_tx;
+#endif
+#if CONFIG_COEX_DUTY_CYCLE
+        HostCmd_SIGNLE_ANT_DUTY_CYCLE single_ant_duty_cycle;
+        HostCmd_DUAL_ANT_DUTY_CYCLE dual_ant_duty_cycle;
+#endif
+#if CONFIG_EXTERNAL_COEX_PTA
+        HostCmd_EXTERNAL_COEX_PTA external_coex_pta;
+#endif
+#if CONFIG_IMD3_CFG
+        HostCmd_IMD3_CFG imd3_cfg;
+#endif
+        HostCmd_DS_80211_TX_FRAME tx_frame;
+    } params;
+} MLAN_PACK_END HostCmd_DS_COMMAND;
+
+/** PS_CMD_ConfirmSleep */
+typedef MLAN_PACK_START struct _OPT_Confirm_Sleep
+{
+    /** Command */
+    t_u16 command;
+    /** Size */
+    t_u16 size;
+    /** Sequence number */
+    t_u16 seq_num;
+    /** Result */
+    t_u16 result;
+    /** Action */
+    t_u16 action;
+    /** Sleep comfirm param definition */
+    sleep_confirm_param sleep_cfm;
+} MLAN_PACK_END OPT_Confirm_Sleep;
+
+typedef MLAN_PACK_START struct _opt_sleep_confirm_buffer
+{
+    /** Header for interface */
+    t_u8 hdr[4];
+    /** New power save command used to send sleep confirmation to the firmware */
+    OPT_Confirm_Sleep ps_cfm_sleep;
+} MLAN_PACK_END opt_sleep_confirm_buffer;
+
+#if (CONFIG_FW_VDLL) || (CONFIG_FW_VDLLV2)
+/** req host side download vdll block */
+#define VDLL_IND_TYPE_REQ 0
+/** notify vdll start offset in firmware image */
+#define VDLL_IND_TYPE_OFFSET 1
+/** notify vdll download error: signature error */
+#define VDLL_IND_TYPE_ERR_SIG 2
+/** notify vdll download error: ID error */
+#define VDLL_IND_TYPE_ERR_ID 3
+#if defined(SD9177)
+/** notify vdll download error: Secure error */
+#define VDLL_IND_TYPE_ERR_SECURE 4
+/** notify vdll download vdll complete */
+#define VDLL_IND_TYPE_COMPLETE 5
+#elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(RW610)
+/** notify VDLL_V2 interface reset */
+#define VDLL_IND_TYPE_INTF_RESET 5
+#endif
+
+/** vdll indicate event structure */
+typedef MLAN_PACK_START struct _vdll_ind
+{
+    /*VDLL ind type*/
+    t_u16 type;
+    /*reserved*/
+    t_u16 reserved;
+    /*indicate the offset downloaded so far*/
+    t_u32 offset;
+    /*VDLL block size*/
+    t_u16 block_len;
+} MLAN_PACK_END vdll_ind, *pvdll_ind;
+
+/** mlan_event_vdllv2_indication data structure */
+typedef MLAN_PACK_START struct _mlan_event_vdll_indication
+{
+    /** Event ID */
+    t_u16 event_id;
+    /** BSS index number for multiple BSS support */
+    t_u8 bss_index;
+    /** BSS type */
+    t_u8 bss_type;
+    /** vdll indicate event */
+    vdll_ind vdllInd;
+} MLAN_PACK_END mlan_event_vdll_indication, *pmlan_event_vdll_indication;
+
+#endif /* CONFIG_FW_VDLL || CONFIG_FW_VDLLV2*/
+
+
+#ifdef PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* !_MLAN_FW_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_ieee.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_ieee.h
new file mode 100644
index 0000000000..2a8fb56655
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_ieee.h
@@ -0,0 +1,2333 @@
+/** @file mlan_ieee.h
+ *
+ *  @brief This file contains IEEE information element related
+ *  definitions used in MLAN and MOAL module.
+ *
+ *  Copyright 2008-2021, 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    11/03/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_IEEE_H_
+#define _MLAN_IEEE_H_
+
+/** FIX IES size in beacon buffer */
+#define WLAN_802_11_FIXED_IE_SIZE 12
+/** WLAN supported rates */
+#define WLAN_SUPPORTED_RATES 14U
+
+/** WLAN supported rates extension*/
+#define WLAN_SUPPORTED_RATES_EXT 60U
+
+enum wifi_nxp_wpa_versions
+{
+    WIFI_NXP_WPA_VERSION_1 = 1 << 0,
+    WIFI_NXP_WPA_VERSION_2 = 1 << 1,
+};
+
+/** Enumeration definition*/
+/** WLAN_802_11_NETWORK_TYPE */
+typedef enum _WLAN_802_11_NETWORK_TYPE
+{
+    Wlan802_11FH,
+    Wlan802_11DS,
+    /* Defined as upper bound */
+    Wlan802_11NetworkTypeMax
+} WLAN_802_11_NETWORK_TYPE;
+
+/** Maximum size of IEEE Information Elements */
+#define IEEE_MAX_IE_SIZE 500
+
+/** Frame control: Type Mgmt frame */
+#define IEEE80211_FC_MGMT_FRAME_TYPE_MASK       0x000C
+/** Frame control: SubType Mgmt frame */
+#define IEEE80211_GET_FC_MGMT_FRAME_SUBTYPE(fc) (((fc)&0x00F0U) >> 4)
+
+#ifdef PRAGMA_PACK
+#pragma pack(push, 1)
+#endif
+
+/*
+*****************************************************************************
+**
+**
+**                         802.11 Message Types
+**
+**
+*****************************************************************************
+*/
+typedef enum
+{
+    IEEE_TYPE_MANAGEMENT = 0,
+    IEEE_TYPE_CONTROL,
+    IEEE_TYPE_DATA
+} IEEEtypes_MsgType_e;
+
+#if CONFIG_11AX
+typedef enum _IEEEtypes_Ext_ElementId_e
+{
+    HE_CAPABILITY = 35,
+    HE_OPERATION  = 36
+} IEEEtypes_Ext_ElementId_e;
+#endif
+
+/** IEEE Type definitions  */
+typedef MLAN_PACK_START enum _IEEEtypes_ElementId_e {
+    SSID            = 0,
+    SUPPORTED_RATES = 1,
+
+    FH_PARAM_SET   = 2,
+    DS_PARAM_SET   = 3,
+    CF_PARAM_SET   = 4,
+    DTIM_PARAM_SET = 5,
+    IBSS_PARAM_SET = 6,
+
+    COUNTRY_INFO = 7,
+
+    POWER_CONSTRAINT   = 32,
+    POWER_CAPABILITY   = 33,
+    TPC_REQUEST        = 34,
+    TPC_REPORT         = 35,
+    SUPPORTED_CHANNELS = 36,
+    CHANNEL_SWITCH_ANN = 37,
+#if CONFIG_11K
+    MEASURE_REQUEST = 38,
+    MEASURE_REPORT  = 39,
+#endif
+    QUIET         = 40,
+    IBSS_DFS      = 41,
+    HT_CAPABILITY = 45,
+    QOS_INFO      = 46,
+
+#if (CONFIG_11K) || (CONFIG_11V)
+    NEIGHBOR_REPORT = 52,
+#endif
+#if (CONFIG_11R) || (CONFIG_11K)
+    /*IEEE802.11r*/
+    MOBILITY_DOMAIN     = 54,
+    FAST_BSS_TRANSITION = 55,
+    TIMEOUT_INTERVAL    = 56,
+    RIC                 = 57,
+#endif
+
+    REGULATORY_CLASS = 59,
+#if CONFIG_ECSA
+    EXTEND_CHANNEL_SWITCH_ANN = 60,
+#endif
+    HT_OPERATION = 61,
+#if CONFIG_11K
+    RRM_ENABLED_CAP = 70,
+#endif
+    MULTI_BSSID = 71,
+    BSSCO_2040          = 72,
+    OVERLAPBSSSCANPARAM = 74,
+    NONTX_BSSID_CAP = 83,
+
+    MBSSID_INDEX = 85,
+    EXT_CAPABILITY = 127,
+
+    /* ERP_INFO = 42, */
+
+    EXTENDED_SUPPORTED_RATES = 50,
+
+    VHT_CAPABILITY = 191,
+    VHT_OPERATION  = 192,
+/*EXT_BSS_LOAD        = 193,*/
+#if CONFIG_ECSA
+    BW_CHANNEL_SWITCH = 194,
+#endif
+    VHT_TX_POWER_ENV = 195,
+#if CONFIG_ECSA
+    EXT_POWER_CONSTR = 196,
+#endif
+    /*AID_INFO            = 197,
+    QUIET_CHAN          = 198,*/
+    OPER_MODE_NTF = 199,
+
+    VENDOR_SPECIFIC_221 = 221,
+    WMM_IE              = VENDOR_SPECIFIC_221,
+
+    WPS_IE = VENDOR_SPECIFIC_221,
+
+    WPA_IE    = VENDOR_SPECIFIC_221,
+    RSN_IE    = 48,
+    VS_IE     = VENDOR_SPECIFIC_221,
+    WAPI_IE   = 68,
+    FRAGMENT  = 242,
+    RSNX_IE   = 244,
+    EXTENSION = 255,
+
+} MLAN_PACK_END IEEEtypes_ElementId_e;
+
+/** IEEE IE header */
+typedef MLAN_PACK_START struct _IEEEtypes_Header_t
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 len;
+} MLAN_PACK_END IEEEtypes_Header_t, *pIEEEtypes_Header_t;
+
+/** Vendor specific IE header */
+typedef MLAN_PACK_START struct _IEEEtypes_VendorHeader_t
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 len;
+    /** OUI */
+    t_u8 oui[3];
+    /** OUI type */
+    t_u8 oui_type;
+    /** OUI subtype */
+    t_u8 oui_subtype;
+    /** Version */
+    t_u8 version;
+} MLAN_PACK_END IEEEtypes_VendorHeader_t, *pIEEEtypes_VendorHeader_t;
+
+/** Vendor specific IE */
+typedef MLAN_PACK_START struct _IEEEtypes_VendorSpecific_t
+{
+    /** Vendor specific IE header */
+    IEEEtypes_VendorHeader_t vend_hdr;
+    /** IE Max - size of previous fields */
+    t_u8 data[IEEE_MAX_IE_SIZE - sizeof(IEEEtypes_VendorHeader_t)];
+} MLAN_PACK_END IEEEtypes_VendorSpecific_t, *pIEEEtypes_VendorSpecific_t;
+
+/** IEEE IE */
+typedef MLAN_PACK_START struct _IEEEtypes_Generic_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** IE Max - size of previous fields */
+    t_u8 data[IEEE_MAX_IE_SIZE - sizeof(IEEEtypes_Header_t)];
+} MLAN_PACK_END IEEEtypes_Generic_t, *pIEEEtypes_Generic_t;
+
+#ifdef ENABLE_802_11R
+/**ft capability policy*/
+typedef MLAN_PACK_START struct _IEEEtypes_FtCapPolicy_t
+{
+    /** FT over the DS capable */
+    t_u8 ft_over_ds : 1;
+    /** RIC support */
+    t_u8 ric : 1;
+    /** Reserved */
+    t_u8 reserved : 6;
+} MLAN_PACK_END IEEEtypes_FtCapPolicy_t;
+
+/** Mobility domain IE */
+typedef MLAN_PACK_START struct _IEEEtypes_MobilityDomain_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Mobility Domain ID */
+    t_u16 mdid;
+    /** FT Capability policy */
+    t_u8 ft_cap;
+} MLAN_PACK_END IEEEtypes_MobilityDomain_t;
+
+/**FT MIC Control*/
+typedef MLAN_PACK_START struct _IEEEtypes_FT_MICControl_t
+{
+    /** reserved */
+    t_u8 reserved;
+    /** element count */
+    t_u8 element_count;
+} MLAN_PACK_END IEEEtypes_FT_MICControl_t;
+
+/** FTIE MIC LEN */
+#define FTIE_MIC_LEN 16
+
+/**FT IE*/
+typedef MLAN_PACK_START struct _IEEEtypes_FastBssTransElement_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** mic control */
+    IEEEtypes_FT_MICControl_t mic_control;
+    /** mic */
+    t_u8 mic[FTIE_MIC_LEN];
+    /** ANonce */
+    t_u8 a_nonce[32];
+    /** SNonce */
+    t_u8 s_nonce[32];
+    /** sub element */
+    t_u8 sub_element[1];
+} MLAN_PACK_END IEEEtypes_FastBssTransElement_t;
+
+/*Category for FT*/
+#define FT_CATEGORY 6
+/** FT ACTION request */
+#define FT_ACTION_REQUEST 1
+/** FT ACTION response */
+#define FT_ACTION_RESPONSE 2
+
+/*FT response and FT ack*/
+typedef MLAN_PACK_START struct
+{
+    /** category */
+    t_u8 category;
+    /** action */
+    t_u8 action;
+    /** sta address */
+    t_u8 sta_addr[MLAN_MAC_ADDR_LENGTH];
+    /** target ap address */
+    t_u8 target_ap_addr[MLAN_MAC_ADDR_LENGTH];
+    /** status code */
+    t_u16 status_code;
+    /** varible */
+    t_u8 variable[];
+} MLAN_PACK_END IEEEtypes_Ft_action_response;
+
+/**FT request */
+typedef MLAN_PACK_START struct
+{
+    /** category */
+    t_u8 category;
+    /** action */
+    t_u8 action;
+    /** sta address */
+    t_u8 sta_addr[MLAN_MAC_ADDR_LENGTH];
+    /** target ap address */
+    t_u8 target_ap_addr[MLAN_MAC_ADDR_LENGTH];
+    /** varible */
+    t_u8 variable[];
+} MLAN_PACK_END IEEEtypes_Ft_action_request;
+#endif
+
+/** auth frame body*/
+typedef MLAN_PACK_START struct
+{
+    /** auth alg */
+    t_u16 auth_alg;
+    /** auth transaction */
+    t_u16 auth_transaction;
+    /** status code */
+    t_u16 status_code;
+    /** variable */
+    t_u8 variable[];
+} MLAN_PACK_END IEEEtypes_Auth_framebody;
+
+/** associate request frame */
+typedef MLAN_PACK_START struct
+{
+    t_u16 capab_info;
+    t_u16 listen_interval;
+    /** followed by SSID and Supported rates */
+    t_u8 variablep[];
+} MLAN_PACK_END IEEEtypes_assoc_req;
+
+/** deauth request frame */
+typedef MLAN_PACK_START struct
+{
+    t_u16 reason_code;
+    t_u8 variablep[];
+} MLAN_PACK_END IEEEtypes_deauth_req;
+
+/*Mgmt frame*/
+typedef MLAN_PACK_START struct
+{
+    /** frame control */
+    t_u16 frame_control;
+    /** duration */
+    t_u16 duration;
+    /** dest address */
+    t_u8 da[MLAN_MAC_ADDR_LENGTH];
+    /** source address */
+    t_u8 sa[MLAN_MAC_ADDR_LENGTH];
+    /** bssid */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** seq control */
+    t_u16 seq_ctrl;
+    union
+    {
+        IEEEtypes_Auth_framebody auth;
+        IEEEtypes_assoc_req assoc_req;
+        IEEEtypes_deauth_req deauth_req;
+#ifdef ENABLE_802_11R
+        IEEEtypes_Ft_action_response ft_resp;
+        IEEEtypes_Ft_action_request ft_req;
+#endif
+    } u;
+} MLAN_PACK_END IEEE80211_MGMT;
+
+/** Capability information mask */
+#define CAPINFO_MASK (~(MBIT(15) | MBIT(14) | MBIT(11) | MBIT(9)))
+
+/** Capability Bit Map*/
+typedef MLAN_PACK_START struct _IEEEtypes_CapInfo_t
+{
+    /** Capability Bit Map : ESS */
+    t_u8 ess : 1;
+    /** Capability Bit Map : IBSS */
+    t_u8 ibss : 1;
+    /** Capability Bit Map : CF pollable */
+    t_u8 cf_pollable : 1;
+    /** Capability Bit Map : CF poll request */
+    t_u8 cf_poll_rqst : 1;
+    /** Capability Bit Map : privacy */
+    t_u8 privacy : 1;
+    /** Capability Bit Map : Short preamble */
+    t_u8 short_preamble : 1;
+    /** Capability Bit Map : PBCC */
+    t_u8 pbcc : 1;
+    /** Capability Bit Map : Channel agility */
+    t_u8 chan_agility : 1;
+    /** Capability Bit Map : Spectrum management */
+    t_u8 spectrum_mgmt : 1;
+    /** Capability Bit Map : Qos */
+    t_u8 qos : 1;
+    /** Capability Bit Map : Short slot time */
+    t_u8 short_slot_time : 1;
+    /** Capability Bit Map : APSD */
+    t_u8 Apsd : 1;
+    /** Capability Bit Map : Radio Rsrc Measurement */
+    t_u8 radio_measurement : 1;
+    /** Capability Bit Map : DSS OFDM */
+    t_u8 dsss_ofdm : 1;
+    /** Capability Bit Map : Delayed Block Ack */
+    t_u8 delayed_block_ack : 1;
+    /** Capability Bit Map : Immediate Block Ack */
+    t_u8 immediate_block_ack : 1;
+} MLAN_PACK_END IEEEtypes_CapInfo_t, *pIEEEtypes_CapInfo_t;
+
+/** IEEEtypes_Ssid_t */
+typedef MLAN_PACK_START struct _IEEEtypes_Ssid_t
+{
+    /** SSID: Element ID */
+    t_u8 element_id;
+    /** SSID : Length */
+    t_u8 len;
+    /** ssid */
+    t_u8 ssid[MLAN_MAX_SSID_LENGTH];
+} MLAN_PACK_END IEEEtypes_Ssid_t, *pIEEEtypes_Ssid_t;
+
+/** IEEEtypes_CfParamSet_t */
+typedef MLAN_PACK_START struct _IEEEtypes_CfParamSet_t
+{
+    /** CF peremeter : Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** CF peremeter : Length */
+    t_u8 len;
+    /** CF peremeter : Count */
+    t_u8 cfp_cnt;
+    /** CF peremeter : Period */
+    t_u8 cfp_period;
+    /** CF peremeter : Maximum duration */
+    t_u16 cfp_max_duration;
+    /** CF peremeter : Remaining duration */
+    t_u16 cfp_duration_remaining;
+} MLAN_PACK_END IEEEtypes_CfParamSet_t, *pIEEEtypes_CfParamSet_t;
+
+/** IEEEtypes_IbssParamSet_t */
+typedef MLAN_PACK_START struct _IEEEtypes_IbssParamSet_t
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 len;
+    /** ATIM window value in milliseconds */
+    t_u16 atim_window;
+} MLAN_PACK_END IEEEtypes_IbssParamSet_t, *pIEEEtypes_IbssParamSet_t;
+
+/** IEEEtypes_SsParamSet_t */
+typedef MLAN_PACK_START union _IEEEtypes_SsParamSet_t
+{
+    /** SS parameter : CF parameter set */
+    IEEEtypes_CfParamSet_t cf_param_set;
+    /** SS parameter : IBSS parameter set */
+    IEEEtypes_IbssParamSet_t ibss_param_set;
+} MLAN_PACK_END IEEEtypes_SsParamSet_t, *pIEEEtypes_SsParamSet_t;
+
+/** IEEEtypes_FhParamSet_t */
+typedef MLAN_PACK_START struct _IEEEtypes_FhParamSet_t
+{
+    /** FH parameter : Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** FH parameter : Length */
+    t_u8 len;
+    /** FH parameter : Dwell time in milliseconds */
+    t_u16 dwell_time;
+    /** FH parameter : Hop set */
+    t_u8 hop_set;
+    /** FH parameter : Hop pattern */
+    t_u8 hop_pattern;
+    /** FH parameter : Hop index */
+    t_u8 hop_index;
+} MLAN_PACK_END IEEEtypes_FhParamSet_t, *pIEEEtypes_FhParamSet_t;
+
+/** IEEEtypes_DsParamSet_t */
+typedef MLAN_PACK_START struct _IEEEtypes_DsParamSet_t
+{
+    /** DS parameter : Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** DS parameter : Length */
+    t_u8 len;
+    /** DS parameter : Current channel */
+    t_u8 current_chan;
+} MLAN_PACK_END IEEEtypes_DsParamSet_t, *pIEEEtypes_DsParamSet_t;
+
+/** IEEEtypes_DTIMParamSet_t */
+typedef MLAN_PACK_START struct _IEEEtypes_DtimParamSet_t
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 len;
+    /** DTIM Count */
+    t_u8 dtim_count;
+    /** DTIM Period */
+    t_u8 dtim_period;
+    /** Bitmap Control */
+    t_u8 bitmap_control;
+    /** Partial Virtual Bitmap */
+    t_u8 partial_virtual_bitmap;
+} MLAN_PACK_END IEEEtypes_DtimParamSet_t, *pIEEEtypes_DtimParamSet_t;
+
+/** IEEEtypes_PhyParamSet_t */
+typedef MLAN_PACK_START union _IEEEtypes_PhyParamSet_t
+{
+    /** FH parameter set */
+    IEEEtypes_FhParamSet_t fh_param_set;
+    /** DS parameter set */
+    IEEEtypes_DsParamSet_t ds_param_set;
+} MLAN_PACK_END IEEEtypes_PhyParamSet_t, *pIEEEtypes_PhyParamSet_t;
+
+/** IEEEtypes_ERPInfo_t */
+typedef MLAN_PACK_START struct _IEEEtypes_ERPInfo_t
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 len;
+    /** ERP flags */
+    t_u8 erp_flags;
+} MLAN_PACK_END IEEEtypes_ERPInfo_t, *pIEEEtypes_ERPInfo_t;
+
+/** IEEEtypes_AId_t */
+typedef t_u16 IEEEtypes_AId_t;
+
+/** IEEEtypes_StatusCode_t */
+typedef t_u16 IEEEtypes_StatusCode_t;
+
+/** IEEEtypes_StatusCode_e */
+typedef MLAN_PACK_START enum _IEEEtypes_StatusCode_e
+{
+    IEEE_STATUS_CODE_SUCCESS                   = 0,
+    IEEE_STATUS_CODE_REASON_UNSPECIFIED        = 1,
+    IEEE_STATUS_CODE_DENIED_OTHER_REASON       = 12,
+    IEEE_STATUS_CODE_POOR_CHANNEL_CONDITIONS   = 34,
+    IEEE_STATUS_CODE_REQUEST_DECLINED          = 37,
+    IEEE_STATUS_CODE_INVALID_PARAMETERS        = 38,
+    IEEE_STATUS_CODE_INVALID_RSNE_CAPABILITIES = 45,
+    IEEE_STATUS_CODE_TRANSMISSION_FAILURE      = 79,
+}MLAN_PACK_END IEEEtypes_StatusCode_e;
+
+/** IEEEtypes_SeqCtl_t */
+typedef MLAN_PACK_START struct _IEEEtypes_SeqCtl_t
+{
+    /** Fragment Number */
+    t_u16 FragNum : 4;
+    /** Sequence Number */
+    t_u16 SeqNum : 12;
+} MLAN_PACK_END IEEEtypes_SeqCtl_t;
+
+/** IEEEtypes_MgmtHdr_t */
+typedef MLAN_PACK_START struct _IEEEtypes_MgmtHdr_t
+{
+    /** FrmCtl*/
+    t_u16 FrmCtl;
+    /** Duration*/
+    t_u16 Duration;
+    /** Destination Addr*/
+    t_u8 DestAddr[6];
+    /** Source Addr*/
+    t_u8 SrcAddr[6];
+    /** BSSID */
+    t_u8 BssId[6];
+    /** IEEEtypes_SeqCtl_t */
+    IEEEtypes_SeqCtl_t SeqCtl;
+} MLAN_PACK_END IEEEtypes_MgmtHdr_t;
+
+/** IEEEtypes_AssocRsp_t */
+typedef MLAN_PACK_START struct _IEEEtypes_AssocRsp_t
+{
+    /** Capability information */
+    IEEEtypes_CapInfo_t capability;
+    /** Association response status code */
+    IEEEtypes_StatusCode_t status_code;
+    /** Association ID */
+    IEEEtypes_AId_t a_id;
+    /** IE data buffer */
+    t_u8 ie_buffer[1];
+} MLAN_PACK_END IEEEtypes_AssocRsp_t, *pIEEEtypes_AssocRsp_t;
+
+/** 802.11 supported rates */
+typedef t_u8 WLAN_802_11_RATES[WLAN_SUPPORTED_RATES];
+
+/** cipher TKIP */
+#define WPA_CIPHER_TKIP2 2
+/** cipher AES CCMP 128 */
+#define WPA_CIPHER_AES_CCM 4
+/** cipher AES GCMP 128 */
+#define WPA_CIPHER_AES_GCM 8
+/** cipher AES CCMP 256 */
+#define WPA_CIPHER_AES_CCM_256 10
+/** cipher AES GCMP 256 */
+#define WPA_CIPHER_AES_GCM_256 9
+
+/** AKM: 8021x */
+#define RSN_AKM_8021X 1
+/** AKM: FT 8021x */
+#define RSN_AKM_FT_8021X 3
+/** AKM: 8021x SUITE B*/
+#define RSN_AKM_8021X_SUITEB 0xb
+/** AKM: 8021x SUITE B 192*/
+#define RSN_AKM_8021X_SUITEB_192 0xc
+/** AKM: FT 8021x SHA384 */
+#define RSN_AKM_FT_8021X_SHA384 0xd
+/** AKM: PSK */
+#define RSN_AKM_PSK 2
+/** AKM: FT PSK */
+#define RSN_AKM_FT_PSK 4
+/** AKM: 8021x_SHA256 */
+#define RSN_AKM_8021X_SHA256 5
+/** AKM: PSK SHA256 */
+#define RSN_AKM_PSK_SHA256 6
+
+/** AKM: SAE SHA256 */
+#define RSN_AKM_SAE 8
+/** AKM: FT SAE SHA256 */
+#define RSN_AKM_FT_SAE 9
+/** AKM: OWE SHA256 */
+#define RSN_AKM_OWE 18
+
+#if defined(STA_SUPPORT) && defined(ENABLE_802_11W) && defined(EMBEDDED_SUPPLICANT)
+/** Pairwise Cipher Suite length */
+#define PAIRWISE_CIPHER_SUITE_LEN 4
+/** AKM Suite length */
+#define AKM_SUITE_LEN 4
+/** MFPC bit in RSN capability */
+#define MFPC_BIT 7
+/** MFPR bit in RSN capability */
+#define MFPR_BIT 6
+/** PMF ORing mask */
+#define PMF_MASK 0x00c0
+#endif
+
+/** wpa_suite_t */
+typedef MLAN_PACK_START struct _wpa_suite_t
+{
+    /** OUI */
+    t_u8 oui[3];
+    /** tyep */
+    t_u8 type;
+} MLAN_PACK_END wpa_suite, wpa_suite_mcast_t;
+
+/** wpa_suite_ucast_t */
+typedef MLAN_PACK_START struct
+{
+    /* count */
+    t_u16 count;
+    /** wpa_suite list */
+    wpa_suite list[1];
+} MLAN_PACK_END wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
+
+/** IEEEtypes_Rsn_t */
+typedef MLAN_PACK_START struct _IEEEtypes_Rsn_t
+{
+    /** Rsn : Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Rsn : Length */
+    t_u8 len;
+    /** Rsn : version */
+    t_u16 version;
+    /** Rsn : group cipher */
+    wpa_suite_mcast_t group_cipher;
+    /** Rsn : pairwise cipher */
+    wpa_suite_ucast_t pairwise_cipher;
+    /** Rsn : AuthKey Mgmt */
+    // wpa_suite_auth_key_mgmt_t auth_key_mgmt;
+} MLAN_PACK_END IEEEtypes_Rsn_t, *pIEEEtypes_Rsn_t;
+
+/** IEEEtypes_Rsnx_t */
+typedef MLAN_PACK_START struct _IEEEtypes_Rsnx_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Rsnx : data */
+    t_u8 data[1];
+} MLAN_PACK_END IEEEtypes_Rsnx_t, *pIEEEtypes_Rsnx_t;
+
+/** IEEEtypes_Wpa_t */
+typedef MLAN_PACK_START struct _IEEEtypes_Wpa_t
+{
+    /** Wpa : Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Wpa : Length */
+    t_u8 len;
+    /** Wpa : oui */
+    t_u8 oui[4];
+    /** version */
+    t_u16 version;
+    /** Wpa : group cipher */
+    wpa_suite_mcast_t group_cipher;
+    /** Wpa : pairwise cipher */
+    wpa_suite_ucast_t pairwise_cipher;
+    /** Wpa : AuthKey Mgmt */
+    // wpa_suite_auth_key_mgmt_t auth_key_mgmt;
+} MLAN_PACK_END IEEEtypes_Wpa_t, *pIEEEtypes_Wpa_t;
+
+/** Maximum number of AC QOS queues available in the driver/firmware */
+#define MAX_AC_QUEUES 4
+
+/** Data structure of WMM QoS information */
+typedef MLAN_PACK_START struct _IEEEtypes_WmmQosInfo_t
+{
+    /** Parameter set count */
+    t_u8 para_set_count : 4;
+    /** Reserved */
+    t_u8 reserved : 3;
+    /** QoS UAPSD */
+    t_u8 qos_uapsd : 1;
+} MLAN_PACK_END IEEEtypes_WmmQosInfo_t, *pIEEEtypes_WmmQosInfo_t;
+
+/** Data structure of WMM Aci/Aifsn */
+typedef MLAN_PACK_START struct _IEEEtypes_WmmAciAifsn_t
+{
+    /** Aifsn */
+    t_u8 aifsn : 4;
+    /** Acm */
+    t_u8 acm : 1;
+    /** Aci */
+    t_u8 aci : 2;
+    /** Reserved */
+    t_u8 reserved : 1;
+} MLAN_PACK_END IEEEtypes_WmmAciAifsn_t, *pIEEEtypes_WmmAciAifsn_t;
+
+/** Data structure of WMM ECW */
+typedef MLAN_PACK_START struct _IEEEtypes_WmmEcw_t
+{
+    /** Minimum Ecw */
+    t_u8 ecw_min : 4;
+    /** Maximum Ecw */
+    t_u8 ecw_max : 4;
+} MLAN_PACK_END IEEEtypes_WmmEcw_t, *pIEEEtypes_WmmEcw_t;
+
+/** Data structure of WMM AC parameters  */
+typedef MLAN_PACK_START struct _IEEEtypes_WmmAcParameters_t
+{
+    IEEEtypes_WmmAciAifsn_t aci_aifsn; /**< AciAifSn */
+    IEEEtypes_WmmEcw_t ecw;            /**< Ecw */
+    t_u16 tx_op_limit;                 /**< Tx op limit */
+} MLAN_PACK_END IEEEtypes_WmmAcParameters_t, *pIEEEtypes_WmmAcParameters_t;
+
+/** Data structure of WMM Info IE  */
+typedef MLAN_PACK_START struct _IEEEtypes_WmmInfo_t
+{
+    /**
+     * WMM Info IE - Vendor Specific Header:
+     *   element_id  [221/0xdd]
+     *   Len         [7]
+     *   Oui         [00:50:f2]
+     *   OuiType     [2]
+     *   OuiSubType  [0]
+     *   Version     [1]
+     */
+    IEEEtypes_VendorHeader_t vend_hdr;
+
+    /** QoS information */
+    IEEEtypes_WmmQosInfo_t qos_info;
+
+} MLAN_PACK_END IEEEtypes_WmmInfo_t, *pIEEEtypes_WmmInfo_t;
+
+/** Data structure of WMM parameter IE  */
+typedef MLAN_PACK_START struct _IEEEtypes_WmmParameter_t
+{
+    /**
+     * WMM Parameter IE - Vendor Specific Header:
+     *   element_id  [221/0xdd]
+     *   Len         [24]
+     *   Oui         [00:50:f2]
+     *   OuiType     [2]
+     *   OuiSubType  [1]
+     *   Version     [1]
+     */
+    IEEEtypes_VendorHeader_t vend_hdr;
+
+    /** QoS information */
+    IEEEtypes_WmmQosInfo_t qos_info;
+    /** Reserved */
+    t_u8 reserved;
+
+    /** AC Parameters Record WMM_AC_BE, WMM_AC_BK, WMM_AC_VI, WMM_AC_VO */
+    IEEEtypes_WmmAcParameters_t ac_params[MAX_AC_QUEUES];
+} MLAN_PACK_END IEEEtypes_WmmParameter_t, *pIEEEtypes_WmmParameter_t;
+
+/** Enumerator for TSPEC direction */
+typedef MLAN_PACK_START enum _IEEEtypes_WMM_TSPEC_TS_Info_Direction_e {
+
+    TSPEC_DIR_UPLINK   = 0,
+    TSPEC_DIR_DOWNLINK = 1,
+    /* 2 is a reserved value */
+    TSPEC_DIR_BIDIRECT = 3,
+
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_TS_Info_Direction_e;
+
+/** Enumerator for TSPEC PSB */
+typedef MLAN_PACK_START enum _IEEEtypes_WMM_TSPEC_TS_Info_PSB_e {
+
+    TSPEC_PSB_LEGACY = 0,
+    TSPEC_PSB_TRIG   = 1,
+
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_TS_Info_PSB_e;
+
+/** Enumerator for TSPEC Ack Policy */
+typedef MLAN_PACK_START enum _IEEEtypes_WMM_TSPEC_TS_Info_AckPolicy_e {
+
+    TSPEC_ACKPOLICY_NORMAL = 0,
+    TSPEC_ACKPOLICY_NOACK  = 1,
+    /* 2 is reserved */
+    TSPEC_ACKPOLICY_BLOCKACK = 3,
+
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_TS_Info_AckPolicy_e;
+
+/** Enumerator for TSPEC Trafffice type */
+typedef MLAN_PACK_START enum _IEEEtypes_WMM_TSPEC_TS_TRAFFIC_TYPE_e {
+
+    TSPEC_TRAFFIC_APERIODIC = 0,
+    TSPEC_TRAFFIC_PERIODIC  = 1,
+
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_TS_TRAFFIC_TYPE_e;
+
+/** Data structure of WMM TSPEC information */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_WMM_TSPEC_TS_TRAFFIC_TYPE_e TrafficType : 1;
+    t_u8 TID : 4;                                            // ! Unique identifier
+    IEEEtypes_WMM_TSPEC_TS_Info_Direction_e Direction : 2;
+    t_u8 AccessPolicy1 : 1;                                  // !
+    t_u8 AccessPolicy2 : 1;                                  // !
+    t_u8 Aggregation : 1;                                    // ! Reserved
+    IEEEtypes_WMM_TSPEC_TS_Info_PSB_e PowerSaveBehavior : 1; // !
+                                                             // Legacy/Trigg
+    t_u8 UserPri : 3;                                        // ! 802.1d User Priority
+    IEEEtypes_WMM_TSPEC_TS_Info_AckPolicy_e AckPolicy : 2;
+    t_u8 Schedule : 1;
+    t_u8 Reserved17_23 : 7; // ! Reserved
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_TS_Info_t;
+
+/** Data structure of WMM TSPEC Nominal Size */
+typedef MLAN_PACK_START struct
+{
+    t_u16 Size : 15;        // ! Nominal size in octets
+    t_u16 Fixed : 1;        // ! 1: Fixed size given in Size, 0: Var, size
+                            // is nominal
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_NomMSDUSize_t;
+
+/** Data structure of WMM TSPEC SBWA */
+typedef MLAN_PACK_START struct
+{
+    t_u16 Fractional : 13;  // ! Fractional portion
+    t_u16 Whole : 3;        // ! Whole portion
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_SBWA;
+
+/** Data structure of WMM TSPEC Body */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_WMM_TSPEC_TS_Info_t TSInfo;
+    IEEEtypes_WMM_TSPEC_NomMSDUSize_t NomMSDUSize;
+    t_u16 MaximumMSDUSize;
+    t_u32 MinServiceInterval;
+    t_u32 MaxServiceInterval;
+    t_u32 InactivityInterval;
+    t_u32 SuspensionInterval;
+    t_u32 ServiceStartTime;
+    t_u32 MinimumDataRate;
+    t_u32 MeanDataRate;
+    t_u32 PeakDataRate;
+    t_u32 MaxBurstSize;
+    t_u32 DelayBound;
+    t_u32 MinPHYRate;
+    IEEEtypes_WMM_TSPEC_SBWA SurplusBWAllowance;
+    t_u16 MediumTime;
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_Body_t;
+
+/** Data structure of WMM TSPEC all elements */
+typedef MLAN_PACK_START struct
+{
+    t_u8 ElementId;
+    t_u8 Len;
+    t_u8 OuiType[4]; /* 00:50:f2:02 */
+    t_u8 OuiSubType; /* 01 */
+    t_u8 Version;
+
+    IEEEtypes_WMM_TSPEC_Body_t TspecBody;
+
+} MLAN_PACK_END IEEEtypes_WMM_TSPEC_t;
+
+/** WMM Action Category values */
+typedef MLAN_PACK_START enum _IEEEtypes_ActionCategory_e {
+    IEEE_MGMT_ACTION_CATEGORY_SPECTRUM_MGMT  = 0,
+    IEEE_MGMT_ACTION_CATEGORY_QOS            = 1,
+    IEEE_MGMT_ACTION_CATEGORY_DLS            = 2,
+    IEEE_MGMT_ACTION_CATEGORY_BLOCK_ACK      = 3,
+    IEEE_MGMT_ACTION_CATEGORY_PUBLIC         = 4,
+    IEEE_MGMT_ACTION_CATEGORY_RADIO_RSRC     = 5,
+    IEEE_MGMT_ACTION_CATEGORY_FAST_BSS_TRANS = 6,
+    IEEE_MGMT_ACTION_CATEGORY_HT             = 7,
+    IEEE_MGMT_ACTION_CATEGORY_SA_QUERY       = 8,
+    IEEE_MGMT_ACTION_CATEGORY_PROTECTED_DUAL = 9,
+    IEEE_MGMT_ACTION_CATEGORY_WNM            = 10,
+    IEEE_MGMT_ACTION_CATEGORY_UNPROTECT_WNM  = 11,
+    IEEE_MGMT_ACTION_CATEGORY_WMM_TSPEC      = 17,
+    IEEE_MGMT_ACTION_CATEGORY_FST            = 18,
+    IEEE_MGMT_ACTION_CATEGORY_AV_STREAMING   = 19,
+    IEEE_MGMT_ACTION_CATEGORY_VENDOR_SPEC    = 127
+} MLAN_PACK_END IEEEtypes_ActionCategory_e;
+
+/** IEEE Std 802.11-2016 - Table 9-354 WNM Action field values */
+typedef MLAN_PACK_START enum _IEEEtypes_WNM_ActionFieldType_e {
+
+    IEEE_MGMT_WNM_EVENT_REQUEST                   = 0,
+    IEEE_MGMT_WNM_EVENT_REPORT                    = 1,
+    IEEE_MGMT_WNM_DIAGNOSTIC_REQUEST              = 2,
+    IEEE_MGMT_WNM_DIAGNOSTIC_REPORT               = 3,
+    IEEE_MGMT_WNM_LOCATION_CFG_REQUEST            = 4,
+    IEEE_MGMT_WNM_LOCATION_CFG_RESPONSE           = 5,
+    IEEE_MGMT_WNM_BTM_QUERY                       = 6,
+    IEEE_MGMT_WNM_BTM_REQUEST                     = 7,
+    IEEE_MGMT_WNM_BTM_RESPONSE                    = 8,
+    IEEE_MGMT_WNM_FMS_REQUEST                     = 9,
+    IEEE_MGMT_WNM_FMS_RESPONSE                    = 10,
+    IEEE_MGMT_WNM_COLLOCATED_INTERFERENCE_REQUEST = 11,
+    IEEE_MGMT_WNM_COLLOCATED_INTERFERENCE_REPORT  = 12,
+    IEEE_MGMT_WNM_TFS_REQUEST                     = 13,
+    IEEE_MGMT_WNM_TFS_RESPONSE                    = 14,
+    IEEE_MGMT_WNM_TFS_NOTIFY                      = 15,
+    IEEE_MGMT_WNM_SLEEP_MODE_REQUEST              = 16,
+    IEEE_MGMT_WNM_SLEEP_MODE_RESPONSE             = 17,
+    IEEE_MGMT_WNM_TIM_BROADCAST_REQUEST           = 18,
+    IEEE_MGMT_WNM_TIM_BROADCAST_RESPONSE          = 19,
+    IEEE_MGMT_WNM_QOS_TRAFFIC_CAPABILITY_UPDATE   = 20,
+    IEEE_MGMT_WNM_CHANNEL_USAGE_REQUEST           = 21,
+    IEEE_MGMT_WNM_CHANNEL_USAGE_RESPONSE          = 22,
+    IEEE_MGMT_WNM_DMS_REQUEST                     = 23,
+    IEEE_MGMT_WNM_DMS_RESPONSE                    = 24,
+    IEEE_MGMT_WNM_TIMING_MEASUREMENT_REQUEST      = 25,
+    IEEE_MGMT_WNM_NOTIFICATION_REQUEST            = 26,
+    IEEE_MGMT_WNM_NOTIFICATION_RESPONSE           = 27,
+    IEEE_MGMT_WNM_NOTIFY_RESPONSE                 = 28
+} MLAN_PACK_END IEEEtypes_WNM_ActionFieldType_e;
+
+#if CONFIG_11V
+/* IEEE Std 802.11-2016 - Figure 9-702 Request Mode field */
+#define IEEE_WNM_BTM_REQUEST_PREFERENCE_CAND_LIST_INCLUDED MBIT(0)
+#define IEEE_WNM_BTM_REQUEST_ABRIDGED                      MBIT(1)
+#define IEEE_WNM_BTM_REQUEST_DISASSOC_IMMINENT             MBIT(2)
+#define IEEE_WNM_BTM_REQUEST_BSS_TERMINATION_INCLUDED      MBIT(3)
+#define IEEE_WNM_BTM_REQUEST_ESS_DISASSOC_IMMINENT         MBIT(4)
+#endif
+
+/** WMM TSPEC operations */
+typedef MLAN_PACK_START enum _IEEEtypes_WMM_Tspec_Action_e {
+
+    TSPEC_ACTION_CODE_ADDTS_REQ = 0,
+    TSPEC_ACTION_CODE_ADDTS_RSP = 1,
+    TSPEC_ACTION_CODE_DELTS     = 2,
+
+} MLAN_PACK_END IEEEtypes_WMM_Tspec_Action_e;
+
+/** WMM TSPEC Category Action Base */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ActionCategory_e category;
+    IEEEtypes_WMM_Tspec_Action_e action;
+    t_u8 dialogToken;
+
+} MLAN_PACK_END IEEEtypes_WMM_Tspec_Action_Base_Tspec_t;
+
+/** WMM TSPEC AddTS request structure */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_WMM_Tspec_Action_Base_Tspec_t tspecAct;
+    t_u8 statusCode;
+    IEEEtypes_WMM_TSPEC_t tspecIE;
+
+    /* Place holder for additional elements after the TSPEC */
+    t_u8 subElem[256];
+
+} MLAN_PACK_END IEEEtypes_Action_WMM_AddTsReq_t;
+
+/** WMM TSPEC AddTS response structure */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_WMM_Tspec_Action_Base_Tspec_t tspecAct;
+    t_u8 statusCode;
+    IEEEtypes_WMM_TSPEC_t tspecIE;
+
+    /* Place holder for additional elements after the TSPEC */
+    t_u8 subElem[256];
+
+} MLAN_PACK_END IEEEtypes_Action_WMM_AddTsRsp_t;
+
+/** WMM TSPEC DelTS structure */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_WMM_Tspec_Action_Base_Tspec_t tspecAct;
+    t_u8 reasonCode;
+    IEEEtypes_WMM_TSPEC_t tspecIE;
+
+} MLAN_PACK_END IEEEtypes_Action_WMM_DelTs_t;
+
+/** union of WMM TSPEC structures */
+typedef MLAN_PACK_START union
+{
+    IEEEtypes_WMM_Tspec_Action_Base_Tspec_t tspecAct;
+
+    IEEEtypes_Action_WMM_AddTsReq_t addTsReq;
+    IEEEtypes_Action_WMM_AddTsRsp_t addTsRsp;
+    IEEEtypes_Action_WMM_DelTs_t delTs;
+
+} MLAN_PACK_END IEEEtypes_Action_WMMAC_t;
+
+/** union of WMM TSPEC & Action category */
+typedef MLAN_PACK_START union
+{
+    IEEEtypes_ActionCategory_e category;
+
+    IEEEtypes_Action_WMMAC_t wmmAc;
+
+} MLAN_PACK_END IEEEtypes_ActionFrame_t;
+
+/** action code for 20/40 BSS Coexsitence Management frame */
+#define BSS_20_40_COEX 0
+/** action code for FILS Discovery Management frame */
+#define FILS_DISCOVERY 34
+
+/** Data structure for subband set */
+typedef MLAN_PACK_START struct _IEEEtypes_SubbandSet_t
+{
+    /** First channel */
+    t_u8 first_chan;
+    /** Number of channels */
+    t_u8 no_of_chan;
+    /** Maximum Tx power in dBm */
+    t_u8 max_tx_pwr;
+} MLAN_PACK_END IEEEtypes_SubbandSet_t, *pIEEEtypes_SubbandSet_t;
+
+/** Data structure for Country IE */
+typedef MLAN_PACK_START struct _IEEEtypes_CountryInfoSet_t
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 len;
+    /** Country code */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /** Set of subbands */
+    IEEEtypes_SubbandSet_t sub_band[1];
+} MLAN_PACK_END IEEEtypes_CountryInfoSet_t, *pIEEEtypes_CountryInfoSet_t;
+
+/** Data structure for Country IE full set */
+typedef MLAN_PACK_START struct _IEEEtypes_CountryInfoFullSet_t
+{
+    /** Element ID */
+    IEEEtypes_ElementId_e element_id;
+    /** Length */
+    t_u8 len;
+    /** Country code */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /** Set of subbands */
+    IEEEtypes_SubbandSet_t sub_band[MRVDRV_MAX_SUBBAND_802_11D];
+} MLAN_PACK_END IEEEtypes_CountryInfoFullSet_t, *pIEEEtypes_CountryInfoFullSet_t;
+
+
+/** HT Capabilities Data */
+typedef MLAN_PACK_START struct _HTCap_t
+{
+    /** HT Capabilities Info field */
+    t_u16 ht_cap_info;
+    /** A-MPDU Parameters field */
+    t_u8 ampdu_param;
+    /** Supported MCS Set field */
+    t_u8 supported_mcs_set[16];
+    /** HT Extended Capabilities field */
+    t_u16 ht_ext_cap;
+    /** Transmit Beamforming Capabilities field */
+    t_u32 tx_bf_cap;
+    /** Antenna Selection Capability field */
+    t_u8 asel;
+} MLAN_PACK_END HTCap_t, *pHTCap_t;
+
+/** HT Information Data */
+typedef MLAN_PACK_START struct _HTInfo_t
+{
+    /** Primary channel */
+    t_u8 pri_chan;
+    /** Field 2 */
+    t_u8 field2;
+    /** Field 3 */
+    t_u16 field3;
+    /** Field 4 */
+    t_u16 field4;
+    /** Bitmap indicating MCSs supported by all HT STAs in the BSS */
+    t_u8 basic_mcs_set[16];
+} MLAN_PACK_END HTInfo_t, *pHTInfo_t;
+
+/** 20/40 BSS Coexistence Data */
+typedef MLAN_PACK_START struct _BSSCo2040_t
+{
+    /** 20/40 BSS Coexistence value */
+    t_u8 bss_co_2040_value;
+} MLAN_PACK_END BSSCo2040_t, *pBSSCo2040_t;
+
+/** Extended Capabilities Data */
+typedef MLAN_PACK_START struct _ExtCap_t
+{
+    /** Extended Capabilities value */
+    t_u8 BSS_CoexistSupport : 1;   /* bit 0 */
+    t_u8 Reserved1 : 1;            /* bit 1 */
+    t_u8 ExtChanSwitching : 1;     /* bit 2 */
+    t_u8 RejectUnadmFrame : 1;     /* bit 3 */
+    t_u8 PSMP_Capable : 1;         /* bit 4 */
+    t_u8 Reserved5 : 1;            /* bit 5 */
+    t_u8 SPSMP_Support : 1;        /* bit 6 */
+    t_u8 Event : 1;                /* bit 7 */
+    t_u8 Diagnostics : 1;          /* bit 8 */
+    t_u8 MulticastDiagnostics : 1; /* bit 9 */
+    t_u8 LocationTracking : 1;     /* bit 10 */
+    t_u8 FMS : 1;                  /* bit 11 */
+    t_u8 ProxyARPService : 1;      /* bit 12 */
+    t_u8 CollocatedIntf : 1;       /* bit 13 */
+    t_u8 CivicLocation : 1;        /* bit 14 */
+    t_u8 GeospatialLocation : 1;   /* bit 15 */
+    t_u8 TFS : 1;                  /* bit 16 */
+    t_u8 WNM_Sleep : 1;            /* bit 17 */
+    t_u8 TIM_Broadcast : 1;        /* bit 18 */
+    t_u8 BSS_Transition : 1;       /* bit 19 */
+    t_u8 QoSTrafficCap : 1;        /* bit 20 */
+    t_u8 AC_StationCount : 1;      /* bit 21 */
+    t_u8 MultipleBSSID : 1;        /* bit 22 */
+    t_u8 TimingMeasurement : 1;    /* bit 23 */
+    t_u8 ChannelUsage : 1;         /* bit 24 */
+    t_u8 SSID_List : 1;            /* bit 25 */
+    t_u8 DMS : 1;                  /* bit 26 */
+    t_u8 UTC : 1;                  /* bit 27 */
+    t_u8 TDLSPeerUAPSDSupport : 1; /* bit 28 */
+    t_u8 TDLSPeerPSMSupport : 1;   /* bit 29 */
+    t_u8 TDLSChannelSwitching : 1; /* bit 30 */
+    t_u8 Interworking : 1;         /* bit 31 */
+    t_u8 Qos_Map : 1;              /* bit 32 */
+    t_u8 EBR : 1;                  /* bit 33 */
+    t_u8 SSPN_Interface : 1;       /* bit 34 */
+    t_u8 Reserved35 : 1;           /* bit 35 */
+    t_u8 MSGCF_Capa : 1;           /* bit 36 */
+    t_u8 TDLSSupport : 1;          /* bit 37 */
+    t_u8 TDLSProhibited : 1;       /* bit 38 */
+    t_u8 TDLSChlSwitchProhib : 1;  /* bit 39 */
+    t_u8 rsvdBit40 : 1;            /* bit 40 */
+    t_u8 rsvdBit41 : 1;            /* bit 41 */
+    t_u8 rsvdBit42 : 1;            /* bit 42 */
+    t_u8 rsvdBit43 : 1;            /* bit 43 */
+    t_u8 rsvdBit44 : 1;            /* bit 44 */
+    t_u8 rsvdBit45 : 1;            /* bit 45 */
+    t_u8 rsvdBit46 : 1;            /* bit 46 */
+    t_u8 rsvdBit47 : 1;            /* bit 47 */
+    t_u8 rsvdBit48 : 1;            /* bit 48 */
+    t_u8 rsvdBit49 : 1;            /* bit 49 */
+    t_u8 rsvdBit50 : 1;            /* bit 50 */
+    t_u8 rsvdBit51 : 1;            /* bit 51 */
+    t_u8 rsvdBit52 : 1;            /* bit 52 */
+    t_u8 rsvdBit53 : 1;            /* bit 53 */
+    t_u8 rsvdBit54 : 1;            /* bit 54 */
+    t_u8 rsvdBit55 : 1;            /* bit 55 */
+    t_u8 rsvdBit56 : 1;            /* bit 56 */
+    t_u8 rsvdBit57 : 1;            /* bit 57 */
+    t_u8 rsvdBit58 : 1;            /* bit 58 */
+    t_u8 rsvdBit59 : 1;            /* bit 59 */
+    t_u8 rsvdBit60 : 1;            /* bit 60 */
+    t_u8 TDLSWildBandwidth : 1;    /* bit 61 */
+    t_u8 OperModeNtf : 1;          /* bit 62 */
+    t_u8 MaxAMSDU0 : 1;            /* bit 63 */
+    t_u8 MaxAMSDU1 : 1;            /* bit 64 */
+    t_u8 chanSchedMgnt : 1;        /* bit 65 */
+    t_u8 rsvdBit66 : 1;            /* bit 66 */
+    t_u8 NCC : 1;                  /* bit 67 */
+    t_u8 rsvdBit68 : 1;            /* bit 68 */
+    t_u8 CAQ : 1;                  /* bit 69 */
+    t_u8 FTMR : 1;                 /* bit 70 */
+    t_u8 FTMI : 1;                 /* bit 71 */
+    t_u8 FILS : 1;                 /* bit 72 */
+    t_u8 rsvdBit73 : 1;            /* bit 73 */
+    t_u8 rsvdBit74 : 1;            /* bit 74 */
+    t_u8 rsvdBit75 : 1;            /* bit 75 */
+    t_u8 rsvdBit76 : 1;            /* bit 76 */
+#if CONFIG_11AX
+    t_u8 TWTReq : 1;               /* bit 77 */
+    t_u8 TWTResp : 1;              /* bit 78 */
+#else
+    t_u8 rsvdBit77 : 1; /* bit 77 */
+    t_u8 rsvdBit78 : 1; /* bit 78 */
+#endif
+    t_u8 rsvdBit79 : 1;            /* bit 79 */
+
+} MLAN_PACK_END ExtCap_t, *pExtCap_t;
+
+/** Overlapping BSS Scan Parameters Data */
+typedef MLAN_PACK_START struct _OverlapBSSScanParam_t
+{
+    /** OBSS Scan Passive Dwell in milliseconds */
+    t_u16 obss_scan_passive_dwell;
+    /** OBSS Scan Active Dwell in milliseconds */
+    t_u16 obss_scan_active_dwell;
+    /** BSS Channel Width Trigger Scan Interval in seconds */
+    t_u16 bss_chan_width_trigger_scan_int;
+    /** OBSS Scan Passive Total Per Channel */
+    t_u16 obss_scan_passive_total;
+    /** OBSS Scan Active Total Per Channel */
+    t_u16 obss_scan_active_total;
+    /** BSS Width Channel Transition Delay Factor */
+    t_u16 bss_width_chan_trans_delay;
+    /** OBSS Scan Activity Threshold */
+    t_u16 obss_scan_active_threshold;
+} MLAN_PACK_END OBSSScanParam_t, *pOBSSScanParam_t;
+
+/** HT Capabilities IE */
+typedef MLAN_PACK_START struct _IEEEtypes_HTCap_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** HTCap struct */
+    HTCap_t ht_cap;
+} MLAN_PACK_END IEEEtypes_HTCap_t, *pIEEEtypes_HTCap_t;
+
+/** HT Information IE */
+typedef MLAN_PACK_START struct _IEEEtypes_HTInfo_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** HTInfo struct */
+    HTInfo_t ht_info;
+} MLAN_PACK_END IEEEtypes_HTInfo_t, *pIEEEtypes_HTInfo_t;
+
+/** the AP which send the multi_bssid IE */
+#define MULTI_BSSID_AP 1
+/** the AP which don't send beacon */
+#define MULTI_BSSID_SUB_AP 2
+/** IEEEtypes_NotxBssCap_t */
+typedef MLAN_PACK_START struct _IEEEtypes_NotxBssCap_t
+{
+    /** Nontransmitted BSSID Capability: Element ID */
+    t_u8 element_id;
+    /** Nontransmitted BSSID Capability : Length */
+    t_u8 len;
+    /** capability */
+    t_u16 cap;
+} MLAN_PACK_END IEEEtypes_NotxBssCap_t, *pIEEEtypes_NotxBssCap_t;
+
+/** Multi BSSID IE */
+typedef MLAN_PACK_START struct _IEEEtypes_MultiBSSIDIndex_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** BSSID Index */
+    t_u8 bssid_index;
+    /** DTIM Period (Optional, not Present in ProbeRsp) */
+    t_u8 dtim_period;
+    /** DTIM Count (Optional, not Present in ProbeRsp) */
+    t_u8 dtim_count;
+} MLAN_PACK_END IEEEtypes_MultiBSSIDIndex_t, *pIEEEtypes_MultiBSSIDIndex_t;
+
+/** NonTransmitted BSSID Profile Subelement IE */
+/** SUBID for IEEEtypes_NonTransBSSIDCap_t */
+#define NONTRANS_BSSID_PROFILE_SUBELEM_ID 0
+
+/** NonTransmitted BSSID Capability IE */
+typedef MLAN_PACK_START struct _IEEEtypes_NonTransBSSIDProfile_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    t_u8 profile_data[];
+} MLAN_PACK_END IEEEtypes_NonTransBSSIDProfile_t, *pIEEEtypes_NonTransBSSIDProfile_t;
+
+/** Multi BSSID IE */
+typedef MLAN_PACK_START struct _IEEEtypes_MultiBSSID_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Max BSSID Indicator */
+    t_u8 max_bssid_indicator;
+    /** Optional Subelement data*/
+    t_u8 sub_elem_data[];
+} MLAN_PACK_END IEEEtypes_MultiBSSID_t, *pIEEEtypes_MultiBSSID_t;
+
+/** 20/40 BSS Coexistence IE */
+typedef MLAN_PACK_START struct _IEEEtypes_2040BSSCo_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** BSSCo2040_t struct */
+    BSSCo2040_t bss_co_2040;
+} MLAN_PACK_END IEEEtypes_2040BSSCo_t, *pIEEEtypes_2040BSSCo_t;
+
+/** Extended Capabilities IE */
+typedef MLAN_PACK_START struct _IEEEtypes_ExtCap_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** ExtCap_t struct */
+    ExtCap_t ext_cap;
+} MLAN_PACK_END IEEEtypes_ExtCap_t, *pIEEEtypes_ExtCap_t;
+
+/** Overlapping BSS Scan Parameters IE */
+typedef MLAN_PACK_START struct _IEEEtypes_OverlapBSSScanParam_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** OBSSScanParam_t struct */
+    OBSSScanParam_t obss_scan_param;
+} MLAN_PACK_END IEEEtypes_OverlapBSSScanParam_t, *pIEEEtypes_OverlapBSSScanParam_t;
+
+/** VHT MCS rate set field, refer to 802.11ac */
+typedef MLAN_PACK_START struct _VHT_MCS_set
+{
+    t_u16 rx_mcs_map;
+    t_u16 rx_max_rate; /* bit 29-31 reserved */
+    t_u16 tx_mcs_map;
+    t_u16 tx_max_rate; /* bit 61-63 reserved */
+} MLAN_PACK_END VHT_MCS_set_t, *pVHT_MCS_set_t;
+
+/** VHT Capabilities info field, reference 802.11ac D1.4 p89 */
+typedef MLAN_PACK_START struct _VHT_capa
+{
+#if 0
+    t_u8 reserved_1:4;
+    t_u8 link_apapt_capa:2;
+    t_u8 max_ampdu_len:3;
+    t_u8 HTC_VHT_capa:1;
+    t_u8 VHT_TXOP_ps:1;
+    t_u8 MU_beamformee_capa:1;
+    t_u8 MU_beamformer_capa:1;
+    t_u8 sounding_dim_num:3;
+    t_u8 beamformer_ante_num:3;
+    t_u8 SU_beamformee_capa:1;
+    t_u8 SU_beamformer_capa:1;
+    t_u8 rx_STBC:3;
+    t_u8 tx_STBC:1;
+    t_u8 sgi_160:1;
+    t_u8 sgi_80:1;
+    t_u8 rx_LDPC:1;
+    t_u8 chan_width:2;
+    t_u8 mpdu_max_len:2;
+#endif
+    t_u32 vht_cap_info;
+    VHT_MCS_set_t mcs_sets;
+} MLAN_PACK_END VHT_capa_t, *pVHT_capa_t;
+
+/** VHT Capabilities IE */
+typedef MLAN_PACK_START struct _IEEEtypes_VHTCap_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    VHT_capa_t vht_cap;
+} MLAN_PACK_END IEEEtypes_VHTCap_t, *pIEEEtypes_VHTCap_t;
+
+#define VHT_CAP_CHWD_80MHZ    0
+#define VHT_CAP_CHWD_160MHZ   1
+#define VHT_CAP_CHWD_80_80MHZ 2
+
+/** VHT Operations IE */
+typedef MLAN_PACK_START struct _IEEEtypes_VHTOprat_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Channel width */
+    t_u8 chan_width;
+    /** Channel center frequency 1 */
+    t_u8 chan_center_freq_1;
+    /** Channel center frequency 2 */
+    t_u8 chan_center_freq_2;
+    /** Basic MCS set map, each 2 bits stands for a Nss */
+    t_u16 basic_MCS_map;
+} MLAN_PACK_END IEEEtypes_VHTOprat_t, *pIEEEtypes_VHTOprat_t;
+
+#define VHT_OPER_CHWD_20_40MHZ 0
+#define VHT_OPER_CHWD_80MHZ    1U
+#define VHT_OPER_CHWD_160MHZ   2
+#define VHT_OPER_CHWD_80_80MHZ 3
+
+/** VHT Transmit Power Envelope IE */
+typedef MLAN_PACK_START struct _IEEEtypes_VHTtxpower_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** maximum tx power */
+    t_u8 max_tx_power;
+    /** channel center frequency */
+    t_u8 chan_center_freq;
+    /** channel width */
+    t_u8 chan_width;
+} MLAN_PACK_END IEEEtypes_VHTtxpower_t, *pIEEEtypes_VHTtxpower_t;
+
+/** Extended Power Constraint IE */
+typedef MLAN_PACK_START struct _IEEEtypes_ExtPwerCons_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** channel width */
+    t_u8 chan_width;
+    /** local power constraint */
+    t_u8 local_power_cons;
+} MLAN_PACK_END IEEEtypes_ExtPwerCons_t, *pIEEEtypes_ExtPwerCons_t;
+
+#if (CONFIG_11AC) || (CONFIG_ECSA)
+/*  IEEE Wide Bandwidth Channel Switch Element */
+/**
+ *  Provided in beacons and probe responses.  Used to advertise when
+ *    and to which channel it is changing to.  Only starting STAs in
+ *    an IBSS and APs are allowed to originate a wide bandwidth chan
+ *    switch element.
+ */
+typedef MLAN_PACK_START struct
+{
+    /** Generic IE header IEEE Element ID = 194*/
+    IEEEtypes_Header_t ieee_hdr;
+    t_u8 new_channel_width;
+    t_u8 new_channel_center_freq0;
+    t_u8 new_channel_center_freq1;
+} MLAN_PACK_END IEEEtypes_WideBWChanSwitch_t;
+
+/*  IEEE VHT Transmit Power Envelope Element */
+/**
+ *  Provided in beacons and probe responses.  Used to advertise the max
+ *    TX power in sepeate bandwidth and as a sub element of Channel Switch
+ *    Wrapper IE.
+ */
+typedef MLAN_PACK_START struct
+{
+    /** Generic IE header IEEE Element ID = 195*/
+    IEEEtypes_Header_t ieee_hdr;
+    t_u8 tpc_info;                     /**< Transmit Power Information>*/
+    t_u8 local_max_tp_20mhz;           /**< Local Maximum Transmit Power for 20 MHZ>*/
+    t_u8 local_max_tp_40mhz;           /**< Local Maximum Transmit Power for 40 MHZ>*/
+    t_u8 local_max_tp_80mhz;           /**< Local Maximum Transmit Power for 80 MHZ>*/
+    t_u8 local_max_tp_160mhz_80_80mhz; /**< Local Maximum Transmit Power for 160/80+80 MHZ>*/
+} MLAN_PACK_END IEEEtypes_VhtTpcEnvelope_t;
+#endif
+
+#if CONFIG_ECSA
+/** data structure for extended channel switch */
+typedef MLAN_PACK_START struct
+{
+    /** IEEE element ID = 60 */
+    t_u8 element_id;
+    /** Element length after id and len, set to 4 */
+    t_u8 len;
+    /** STA should not transmit any frames if 1 */
+    t_u8 chan_switch_mode;
+    /** Operate class # that AP/IBSS is moving to */
+    t_u8 new_oper_class;
+    /** Channel # that AP/IBSS is moving to */
+    t_u8 new_channel_num;
+    /** of TBTTs before channel switch */
+    t_u8 chan_switch_count;
+} MLAN_PACK_END IEEEtypes_ExtChanSwitchAnn_t;
+#endif
+
+/** Extended BSS Load IE */
+typedef MLAN_PACK_START struct _IEEEtypes_ExtBSSload_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** MIMO capability count */
+    t_u8 MU_MIMO_capa_count;
+    /** stream under utilization */
+    t_u8 stream_underutilization;
+    /** VHT 40 util */
+    t_u8 VHT40_util;
+    /** VHT 80 util */
+    t_u8 VHT80_util;
+    /** VHT 160 util */
+    t_u8 VHT160_util;
+} MLAN_PACK_END IEEEtypes_ExtBSSload_t, *pIEEEtypes_ExtBSSload_t;
+
+/** Quiet Channel IE */
+typedef MLAN_PACK_START struct _IEEEtypes_QuietChan_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** AP quiet mode */
+    t_u8 AP_quiet_mode;
+    /** Quiet count */
+    t_u8 quiet_count;
+    /** Quiet period */
+    t_u8 quiet_period;
+    /** Quiet duration */
+    t_u16 quiet_dur;
+    /** Quiet offset */
+    t_u16 quiet_offset;
+} MLAN_PACK_END IEEEtypes_QuietChan_t, *pIEEEtypes_QuietChan_t;
+
+/** Wide Bandwidth Channel Switch IE */
+typedef MLAN_PACK_START struct _IEEEtypes_BWSwitch_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** New channel width */
+    t_u8 new_chan_width;
+    /** New channel center frequency 1 */
+    t_u8 new_chan_center_freq_1;
+    /** New channel center frequency 2 */
+    t_u8 new_chan_center_freq_2;
+} MLAN_PACK_END IEEEtypes_BWSwitch_t, *pIEEEtypes_BWSwitch_t;
+
+/** AID IE */
+typedef MLAN_PACK_START struct _IEEEtypes_AID_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** AID number */
+    t_u16 AID;
+} MLAN_PACK_END IEEEtypes_AID_t, *pIEEEtypes_AID_t;
+
+/** Operating Mode Notificaton IE */
+typedef MLAN_PACK_START struct _IEEEtypes_OperModeNtf_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Operating Mode */
+    t_u8 oper_mode;
+} MLAN_PACK_END IEEEtypes_OperModeNtf_t, *pIEEEtypes_OperModeNtf_t;
+
+/** Maximum number of subbands in the IEEEtypes_SupportedChannels_t structure */
+#define WLAN_11H_MAX_SUBBANDS 5
+
+/** Maximum number of DFS channels configured in IEEEtypes_IBSS_DFS_t */
+#define WLAN_11H_MAX_IBSS_DFS_CHANNELS 25
+
+/**  IEEE Power Constraint element (7.3.2.15) */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ElementId_e element_id; /**< IEEE Element ID = 32 */
+    t_u8 len;                         /**< Element length after id and len */
+    t_u8 local_constraint;            /**< Local power constraint applied to 11d chan info */
+} MLAN_PACK_END IEEEtypes_PowerConstraint_t;
+
+/**  IEEE Power Capability element (7.3.2.16) */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ElementId_e element_id; /**< IEEE Element ID = 33 */
+    t_u8 len;                         /**< Element length after id and len */
+    t_s8 min_tx_power_capability;     /**< Minimum Transmit power (dBm) */
+    t_s8 max_tx_power_capability;     /**< Maximum Transmit power (dBm) */
+} MLAN_PACK_END IEEEtypes_PowerCapability_t;
+
+/**  IEEE TPC Report element (7.3.2.18) */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ElementId_e element_id; /**< IEEE Element ID = 35 */
+    t_u8 len;                         /**< Element length after id and len */
+    t_s8 tx_power;                    /**< Max power used to transmit the TPC Report frame (dBm) */
+    t_s8 link_margin;                 /**< Link margin when TPC Request received (dB) */
+} MLAN_PACK_END IEEEtypes_TPCReport_t;
+
+/*  IEEE Supported Channel sub-band description (7.3.2.19) */
+/**
+ *  Sub-band description used in the supported channels element.
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 start_chan; /**< Starting channel in the subband */
+    t_u8 num_chans;  /**< Number of channels in the subband */
+
+} MLAN_PACK_END IEEEtypes_SupportChan_Subband_t;
+
+/*  IEEE Supported Channel element (7.3.2.19) */
+/**
+ *  Sent in association requests. Details the sub-bands and number
+ *    of channels supported in each subband
+ */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ElementId_e element_id; /**< IEEE Element ID = 36 */
+    t_u8 len;                         /**< Element length after id and len */
+
+    /** Configured sub-bands information in the element */
+    IEEEtypes_SupportChan_Subband_t subband[WLAN_11H_MAX_SUBBANDS];
+
+} MLAN_PACK_END IEEEtypes_SupportedChannels_t;
+
+/*  IEEE Channel Switch Announcement Element (7.3.2.20) */
+/**
+ *  Provided in beacons and probe responses.  Used to advertise when
+ *    and to which channel it is changing to.  Only starting STAs in
+ *    an IBSS and APs are allowed to originate a chan switch element.
+ */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ElementId_e element_id; /**< IEEE Element ID = 37 */
+    t_u8 len;                         /**< Element length after id and len */
+    t_u8 chan_switch_mode;            /**< STA should not transmit any frames if 1 */
+    t_u8 new_channel_num;             /**< Channel # that AP/IBSS is moving to */
+    t_u8 chan_switch_count;           /**< # of TBTTs before channel switch */
+
+} MLAN_PACK_END IEEEtypes_ChanSwitchAnn_t;
+
+/*  IEEE Quiet Period Element (7.3.2.23) */
+/**
+ *  Provided in beacons and probe responses.  Indicates times during
+ *    which the STA should not be transmitting data.  Only starting STAs in
+ *    an IBSS and APs are allowed to originate a quiet element.
+ */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ElementId_e element_id; /**< IEEE Element ID = 40 */
+    t_u8 len;                         /**< Element length after id and len */
+    t_u8 quiet_count;                 /**< Number of TBTTs until beacon with the quiet period */
+    t_u8 quiet_period;                /**< Regular quiet period, # of TBTTS between periods */
+    t_u16 quiet_duration;             /**< Duration of the quiet period in TUs */
+    t_u16 quiet_offset;               /**< Offset in TUs from the TBTT for the quiet period */
+
+} MLAN_PACK_END IEEEtypes_Quiet_t;
+
+/**
+***  @brief Map octet of the basic measurement report (7.3.2.22.1)
+**/
+typedef MLAN_PACK_START struct
+{
+    t_u8 bss : 1;              /**< At least one valid MPDU received on channel */
+    t_u8 ofdm_preamble : 1;    /**< OFDM preamble detected on channel */
+    t_u8 unidentified_sig : 1; /**< Unidentified signal found on channel */
+    t_u8 radar : 1;            /**< Radar detected on channel */
+    t_u8 unmeasured : 1;       /**< Channel is unmeasured */
+    t_u8 rsvd5_7 : 3;          /**< Reserved */
+
+} MLAN_PACK_END MeasRptBasicMap_t;
+
+/*  IEEE DFS Channel Map field (7.3.2.24) */
+/**
+ *  Used to list supported channels and provide a octet "map" field which
+ *    contains a basic measurement report for that channel in the
+ *    IEEEtypes_IBSS_DFS_t element
+ */
+typedef MLAN_PACK_START struct
+{
+    t_u8 channel_number;       /**< Channel number */
+    MeasRptBasicMap_t rpt_map; /**< Basic measurement report for the channel */
+
+} MLAN_PACK_END IEEEtypes_ChannelMap_t;
+
+/*  IEEE IBSS DFS Element (7.3.2.24) */
+/**
+ *  IBSS DFS element included in ad hoc beacons and probe responses.
+ *    Provides information regarding the IBSS DFS Owner as well as the
+ *    originating STAs supported channels and basic measurement results.
+ */
+typedef MLAN_PACK_START struct
+{
+    IEEEtypes_ElementId_e element_id;     /**< IEEE Element ID = 41 */
+    t_u8 len;                             /**< Element length after id and len */
+    t_u8 dfs_owner[MLAN_MAC_ADDR_LENGTH]; /**< DFS Owner STA Address */
+    t_u8 dfs_recovery_interval;           /**< DFS Recovery time in TBTTs */
+
+    /** Variable length map field, one Map entry for each supported channel */
+    IEEEtypes_ChannelMap_t channel_map[WLAN_11H_MAX_IBSS_DFS_CHANNELS];
+
+} MLAN_PACK_END IEEEtypes_IBSS_DFS_t;
+
+/* 802.11h BSS information kept for each BSSID received in scan results */
+/**
+ * IEEE BSS information needed from scan results for later processing in
+ *    join commands
+ */
+typedef struct
+{
+    t_u8 sensed_11h;                              /**< Capability bit set or 11h IE found in this BSS */
+
+    IEEEtypes_PowerConstraint_t power_constraint; /**< Power Constraint IE */
+    IEEEtypes_PowerCapability_t power_capability; /**< Power Capability IE */
+    IEEEtypes_TPCReport_t tpc_report;             /**< TPC Report IE */
+    IEEEtypes_ChanSwitchAnn_t chan_switch_ann;    /**< Channel Switch Announcement IE */
+    IEEEtypes_Quiet_t quiet;                      /**< Quiet IE */
+    IEEEtypes_IBSS_DFS_t ibss_dfs;                /**< IBSS DFS Element IE */
+
+} wlan_11h_bss_info_t;
+
+/** Macro for maximum size of scan response buffer */
+#define MAX_SCAN_RSP_BUF (16 * 1024)
+
+/** Maximum number of channels that can be sent in user scan config */
+#define WLAN_USER_SCAN_CHAN_MAX 50U
+
+/** Maximum length of SSID list */
+#define MRVDRV_MAX_SSID_LIST_LENGTH 10
+
+/** Scan all the channels in specified band */
+#define BAND_SPECIFIED 0x80U
+
+/**
+ *  IOCTL SSID List sub-structure sent in wlan_ioctl_user_scan_cfg
+ *
+ *  Used to specify SSID specific filters as well as SSID pattern matching
+ *    filters for scan result processing in firmware.
+ */
+typedef MLAN_PACK_START struct _wlan_user_scan_ssid
+{
+    /** SSID */
+    t_u8 ssid[MLAN_MAX_SSID_LENGTH + 1];
+    /** Maximum length of SSID */
+    t_u8 max_len;
+} MLAN_PACK_END wlan_user_scan_ssid;
+
+/**
+ *  @brief IOCTL channel sub-structure sent in wlan_ioctl_user_scan_cfg
+ *
+ *  Multiple instances of this structure are included in the IOCTL command
+ *   to configure a instance of a scan on the specific channel.
+ */
+typedef MLAN_PACK_START struct _wlan_user_scan_chan
+{
+    /** Channel Number to scan */
+    t_u8 chan_number;
+    /** Radio type: 'B/G' Band = 0, 'A' Band = 1 */
+    t_u8 radio_type;
+    /** Scan type: Active = 1, Passive = 2 */
+    mlan_scan_type scan_type;
+    /** Reserved */
+    t_u8 reserved;
+    /** Scan duration in milliseconds; if 0 default used */
+    t_u32 scan_time;
+} MLAN_PACK_END wlan_user_scan_chan;
+
+#if CONFIG_SCAN_CHANNEL_GAP
+/** channel statictics */
+typedef MLAN_PACK_START struct _ChanStatistics_t
+{
+    /** channle number */
+    t_u8 chan_num;
+    /** band info */
+    Band_Config_t bandcfg;
+    /** flags */
+    t_u8 flags;
+    /** noise */
+    t_s8 noise;
+    /** total network */
+    t_u16 total_networks;
+    /** scan duration */
+    t_u16 cca_scan_duration;
+    /** busy duration */
+    t_u16 cca_busy_duration;
+    /** min rss */
+    t_u8 min_rss;
+    /** max rssi */
+    t_u8 max_rss;
+} MLAN_PACK_END ChanStatistics_t;
+#endif
+
+/**
+ *  Input structure to configure an immediate scan cmd to firmware
+ *
+ *  Specifies a number of parameters to be used in general for the scan
+ *    as well as a channel list (wlan_user_scan_chan) for each scan period
+ *    desired.
+ */
+typedef MLAN_PACK_START struct
+{
+    /**
+     *  Flag set to keep the previous scan table intact
+     *
+     *  If set, the scan results will accumulate, replacing any previous
+     *   matched entries for a BSS with the new scan data
+     */
+    t_u8 keep_previous_scan;
+    /**
+     *  BSS mode to be sent in the firmware command
+     *
+     *  Field can be used to restrict the types of networks returned in the
+     *    scan.  Valid settings are:
+     *
+     *   - MLAN_SCAN_MODE_BSS  (infrastructure)
+     *   - MLAN_SCAN_MODE_IBSS (adhoc)
+     *   - MLAN_SCAN_MODE_ANY  (unrestricted, adhoc and infrastructure)
+     */
+    t_u8 bss_mode;
+    /**
+     *  Configure the number of probe requests for active chan scans
+     */
+    t_u8 num_probes;
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    /**
+     *  Threshold of RSSI
+     */
+    t_s16 rssi_threshold;
+#endif
+    /**
+     *  @brief Reserved
+     */
+    t_u8 reserved;
+    /**
+     *  @brief BSSID filter sent in the firmware command to limit the results
+     */
+    t_u8 specific_bssid[MLAN_MAC_ADDR_LENGTH];
+    /**
+     *  SSID filter list used in the to limit the scan results
+     */
+    wlan_user_scan_ssid ssid_list[MRVDRV_MAX_SSID_LIST_LENGTH];
+    /**
+     *  Variable number (fixed maximum) of channels to scan up
+     */
+    wlan_user_scan_chan chan_list[WLAN_USER_SCAN_CHAN_MAX];
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** scan channel gap */
+    t_u16 scan_chan_gap;
+#endif
+} MLAN_PACK_END wlan_user_scan_cfg;
+/** Default scan interval in millisecond*/
+#define DEFAULT_BGSCAN_INTERVAL 30000
+
+/** action get all, except pps/uapsd config */
+#define BG_SCAN_ACT_GET 0x0000
+/** action set all, except pps/uapsd config */
+#define BG_SCAN_ACT_SET 0x0001
+#if CONFIG_WMM_UAPSD
+/** action get pps/uapsd config */
+#define BG_SCAN_ACT_GET_PPS_UAPSD 0x0100
+/** action set pps/uapsd config */
+#define BG_SCAN_ACT_SET_PPS_UAPSD 0x0101
+#endif
+/** action set all */
+#define BG_SCAN_ACT_SET_ALL 0xff01
+/** ssid match */
+#define BG_SCAN_SSID_MATCH 0x0001
+/** ssid match and RSSI exceeded */
+#define BG_SCAN_SSID_RSSI_MATCH 0x0004
+/**wait for all channel scan to complete to report scan result*/
+#define BG_SCAN_WAIT_ALL_CHAN_DONE 0x80000000
+/** Maximum number of channels that can be sent in bg scan config */
+#define WLAN_BG_SCAN_CHAN_MAX 38
+#if CONFIG_UNII4_BAND_SUPPORT
+/** max bgscan chan number, include UNII_4 channel */
+#define WLAN_BG_SCAN_CHAN_MAX_UNII_4 41
+#endif
+/** Min BGSCAN interval 30 second */
+#define MIN_BGSCAN_INTERVAL 30000
+/** default repeat count */
+#define DEF_REPEAT_COUNT 6
+
+/** default rssi low threshold */
+#define DEFAULT_RSSI_LOW_THRESHOLD 70
+/** RSSI HYSTERSIS */
+#define RSSI_HYSTERESIS 4
+/** lowest rssi threshold */
+#define LOWEST_RSSI_THRESHOLD 82
+/** delta rssi */
+#define DELTA_RSSI 10
+#if CONFIG_SCAN_CHANNEL_GAP
+/** Scan channel gap */
+#define SCAN_CHANNEL_GAP_VALUE 50U
+#endif
+#if CONFIG_11AX
+typedef MLAN_PACK_START struct _IEEEtypes_Extension_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Element id extension */
+    t_u8 ext_id;
+    /** payload */
+    t_u8 data[];
+} MLAN_PACK_END IEEEtypes_Extension_t, *pIEEEtypes_Extension_t;
+
+typedef MLAN_PACK_START struct _IEEEtypes_HeMcsNss_t
+{
+    /** HE Rx MCS and NSS Set */
+    t_u16 rx_mcs;
+    /** HE Tx MCS and NSS Set*/
+    t_u16 tx_mcs;
+} MLAN_PACK_END IEEEtypes_HeMcsNss_t, *pIEEEtypes_HeMcsNss_t;
+
+typedef MLAN_PACK_START struct _IEEEtypes_HECap_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Element id extension */
+    t_u8 ext_id;
+    /** he mac capability info */
+    t_u8 he_mac_cap[6];
+    /** he phy capability info */
+    t_u8 he_phy_cap[11];
+    /** he txrx mcs support , size would be 4 or 8 or 12 */
+    t_u8 he_txrx_mcs_support[4];
+    /** PPE Thresholds (optional) */
+} MLAN_PACK_END IEEEtypes_HECap_t, *pIEEEtypes_HECap_t;
+
+typedef MLAN_PACK_START struct _IEEEtypes_HeOpParam_t {
+    /** Default PE Duration */
+    t_u16 default_pe_dur : 3;                       /* bit 0-2 */
+    /** TWT Required */
+    t_u16 twt_req : 1;                              /* bit 3 */
+    /** TXOP Duration RTS Threshold */
+    t_u16 txop_dur_rts_threshold : 10;              /* bit 4-13 */
+    /** VHT Operation Info Present */
+    t_u16 vht_op_info_present : 1;                  /* bit 14 */
+    /** Co-Hosted BSS */
+    t_u16 co_located_bss : 1;                       /* bit 15 */
+    /** ER SU Disable */
+    t_u8  er_su_disable : 1;                        /* bit 16 */
+    /* 6g operation info present */
+    t_u8  he_6g_op_info_present :1;                 /* bit 17 */
+    /** Reserved bit 18-23 */
+    t_u8  reserved : 6;                             /* bit 18-23 */
+} MLAN_PACK_END IEEEtypes_HeOpParam_t;
+
+typedef MLAN_PACK_START struct _IEEEtypes_HeBssColorInfo_t {
+    /** BSS Color */
+    t_u8 bss_color : 6;                             /* bit 0-5 */
+    /** Partial BSS Color */
+    t_u8 partial_bss_color : 1;                     /* bit 6 */
+    /** BSS Color Disabled */
+    t_u8 bss_color_disabled : 1;                    /* bit 7 */
+} MLAN_PACK_END IEEEtypes_HeBssColorInfo_t;
+
+typedef MLAN_PACK_START struct _IEEEtypes_HeMcsMap_t {
+    /** Max HE-MAC for 1 SS */
+    t_u8 max_mcs_1ss: 2;
+    /** Max HE-MAC for 2 SS */
+    t_u8 max_mcs_2ss: 2;
+    /** Max HE-MAC for 3 SS */
+    t_u8 max_mcs_3ss: 2;
+    /** Max HE-MAC for 4 SS */
+    t_u8 max_mcs_4ss: 2;
+    /** Max HE-MAC for 5 SS */
+    t_u8 max_mcs_5ss: 2;
+    /** Max HE-MAC for 6 SS */
+    t_u8 max_mcs_6ss: 2;
+    /** Max HE-MAC for 7 SS */
+    t_u8 max_mcs_7ss: 2;
+    /** Max HE-MAC for 8 SS */
+    t_u8 max_mcs_8ss: 2;
+} MLAN_PACK_END IEEEtypes_HeMcsMap_t, *pIEEEtypes_HeMcsMap_t;
+
+typedef MLAN_PACK_START struct _IEEEtypes_HeOp_t {
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Element id extension */
+    t_u8 ext_id;
+    /** HE Operation Parameters */
+    IEEEtypes_HeOpParam_t           he_op_param;
+    /** BSS Color Info */
+    IEEEtypes_HeBssColorInfo_t      bss_color_info;
+    /** Basic HE-MCS and NSS Set */
+    IEEEtypes_HeMcsMap_t            basic_he_mcs_nss;
+    /** Optional Field, including VHT Operation Info Max Co-Hosted BSSID Indicator, and 6Ghz Operation Info  */
+    t_u8 option[9];
+} MLAN_PACK_END IEEEtypes_HeOp_t;
+#endif
+
+/** MBO IE header */
+#define MBO_IE_HEADER_LEN 6U
+
+/** MBO attribute header */
+#define MBO_ATTR_HEADER_LEN 2
+
+/*
+*****************************************************************************
+**
+**
+**                     802.11k RRM definitions
+**
+**
+*****************************************************************************
+*/
+#if CONFIG_11K
+typedef MLAN_PACK_START struct _IEEEtypes_RrmEnabledCapabilities_t
+{
+    /* First byte */
+    t_u8 LinkMeas : 1;
+    t_u8 NborRpt : 1;
+    t_u8 ParallelMeas : 1;
+    t_u8 RepeatMeas : 1;
+    t_u8 BcnPassiveMeas : 1;
+    t_u8 BcnActiveMeas : 1;
+    t_u8 BcnTableMeas : 1;
+    t_u8 BcnMeasRptCond : 1;
+
+    /* Second byte */
+    t_u8 FrameMeas : 1;
+    t_u8 ChanLoadMeas : 1;
+    t_u8 NoiseHistMeas : 1;
+    t_u8 StatsMeas : 1;
+    t_u8 LciMeas : 1;
+    t_u8 LciAzimuth : 1;
+    t_u8 TxStreamMeas : 1;
+    t_u8 TrigTxStreamMeas : 1;
+
+    /* Third byte */
+    t_u8 ApChanRpt : 1;
+    t_u8 RrmMib : 1;
+    t_u8 OpChanMaxMeas : 3;
+    t_u8 NonOpChanMaxMeas : 3;
+
+    /* Fourth byte */
+    t_u8 MeasPilot : 3;
+    t_u8 MeasPilotTxInfo : 1;
+    t_u8 NborRptTsfOffset : 1;
+    t_u8 RcpiMeas : 1;
+    t_u8 RsniMeas : 1;
+    t_u8 BssAvgAccessDelay : 1;
+
+    /* Fifth byte */
+    t_u8 BssAvailAdmCap : 1;
+    t_u8 AntennaInfo : 1;
+    t_u8 FtmRangeReport : 1;
+    t_u8 CivicLocation : 1;
+    t_u8 Reserved : 4;
+} MLAN_PACK_END IEEEtypes_RrmEnabledCapabilities_t, *pIEEEtypes_RrmEnabledCapabilities_t;
+
+typedef MLAN_PACK_START struct _IEEEtypes_RrmElement_t
+{
+    /** Element ID */
+    t_u8 element_id;
+    /** Length */
+    t_u8 len;
+
+    IEEEtypes_RrmEnabledCapabilities_t RrmEnabledCapabilities;
+} MLAN_PACK_END IEEEtypes_RrmElement_t, *pIEEEtypes_RrmElement_t;
+
+/** Mobility Domain element */
+typedef MLAN_PACK_START struct _MrvlIETypes_MobDomain_t
+{
+    /** Header */
+    IEEEtypes_Header_t header;
+    /** Mobility Domain Identifier */
+    t_u16 mob_domain_id;
+    /** FT Capability and Policy */
+    t_u8 ft_cap_policy;
+} MLAN_PACK_END MrvlIETypes_MobDomain_t;
+
+typedef MLAN_PACK_START enum _IEEEtypes_RRM_ActionFieldType_e {
+    IEEE_MGMT_RRM_RADIO_MEASUREMENT_REQUEST = 0,
+    IEEE_MGMT_RRM_RADIO_MEASUREMENT_REPORT  = 1,
+    IEEE_MGMT_RRM_LINK_MEASUREMENT_REQUEST  = 2,
+    IEEE_MGMT_RRM_LINK_MEASUREMENT_REPORT   = 3,
+    IEEE_MGMT_RRM_NEIGHBOR_REPORT_REQUEST   = 4,
+    IEEE_MGMT_RRM_NEIGHBOR_REPORT_RESPONSE  = 5
+} MLAN_PACK_END IEEEtypes_RRM_ActionFieldType_e;
+#endif
+
+/**
+ *  Input structure to configure bs scan cmd to firmware
+ */
+typedef MLAN_PACK_START struct
+{
+    /** action */
+    t_u16 action;
+    /** enable/disable */
+    t_u8 enable;
+    /**  BSS type:
+     *   MLAN_SCAN_MODE_BSS  (infrastructure)
+     *   MLAN_SCAN_MODE_IBSS (adhoc)
+     *   MLAN_SCAN_MODE_ANY  (unrestricted, adhoc and infrastructure)
+     */
+    t_u8 bss_type;
+    /** number of channel scanned during each scan */
+    t_u8 chan_per_scan;
+    /** interval between consecutive scan */
+    t_u32 scan_interval;
+    /** bit 0: ssid match bit 1: ssid match and SNR exceeded
+     *  bit 2: ssid match and RSSI exceeded
+     *  bit 31: wait for all channel scan to complete to report scan result
+     */
+    t_u32 report_condition;
+    /* Configure the number of probe requests for active chan scans */
+    t_u8 num_probes;
+    /** RSSI threshold */
+    t_u8 rssi_threshold;
+    /** SNR threshold */
+    t_u8 snr_threshold;
+    /** repeat count */
+    t_u16 repeat_count;
+    /** start later flag */
+    t_u16 start_later;
+    /** SSID filter list used in the to limit the scan results */
+    wlan_user_scan_ssid ssid_list[MRVDRV_MAX_SSID_LIST_LENGTH];
+    /** Variable number (fixed maximum) of channels to scan up */
+    wlan_user_scan_chan chan_list[WLAN_BG_SCAN_CHAN_MAX];
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** scan channel gap */
+    t_u16 scan_chan_gap;
+#endif
+} MLAN_PACK_END wlan_bgscan_cfg;
+
+#ifdef PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#if (CONFIG_11R) || (CONFIG_11K)
+/** Mobility domain IE */
+typedef MLAN_PACK_START struct _IEEEtypes_MobilityDomain_t
+{
+    /** Generic IE header */
+    IEEEtypes_Header_t ieee_hdr;
+    /** Mobility Domain ID */
+    t_u16 mdid;
+    /** FT Capability policy */
+    t_u8 ft_cap;
+} MLAN_PACK_END IEEEtypes_MobilityDomain_t;
+#endif
+
+/** BSSDescriptor_t
+ *    Structure used to store information for beacon/probe response
+ */
+typedef struct _BSSDescriptor_t
+{
+    /** MAC address */
+    mlan_802_11_mac_addr mac_address;
+
+    /** SSID */
+    mlan_802_11_ssid ssid;
+
+    /** Transition MAC address */
+    mlan_802_11_mac_addr trans_mac_address;
+
+    /** Transition SSID */
+    mlan_802_11_ssid trans_ssid;
+
+#if CONFIG_DRIVER_OWE
+    /** OWE Transition mode */
+    t_u8 owe_transition_mode;
+#endif
+
+    /** WEP encryption requirement */
+    t_u32 privacy;
+
+    /** Receive signal strength in dBm */
+    t_s32 rssi;
+
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** channel load */
+    t_u16 chan_load;
+    /** channel load */
+    t_u16 chan_noise;
+#endif
+
+    /** Channel */
+    t_u8 channel;
+
+    /** Freq */
+    t_u32 freq;
+
+    /** Beacon period */
+    t_u16 beacon_period;
+
+    /** DTIM period */
+    t_u16 dtim_period;
+
+    /** ATIM window */
+    t_u32 atim_window;
+
+    /** ERP flags */
+    t_u8 erp_flags;
+
+    /** Type of network in use */
+    WLAN_802_11_NETWORK_TYPE network_type_use;
+
+    /** Network infrastructure mode */
+    mlan_bss_mode bss_mode;
+
+    /** Network supported rates */
+    WLAN_802_11_RATES supported_rates;
+
+    /** Supported data rates */
+    t_u8 data_rates[WLAN_SUPPORTED_RATES];
+
+    /** Current channel bandwidth
+     *  0 : 20MHZ
+     *  1 : 40MHZ
+     *  2 : 80MHZ
+     *  3 : 160MHZ
+     */
+    t_u8 curr_bandwidth;
+
+    /** Network band.
+     * BAND_B(0x01): 'b' band
+     * BAND_G(0x02): 'g' band
+     * BAND_A(0X04): 'a' band
+     */
+    t_u16 bss_band;
+
+    /** TSF record at driver receive the scan result from FW (in us) */
+    unsigned int scan_result_tsf;
+
+    /** TSF timestamp from the current firmware TSF */
+    t_u64 network_tsf;
+
+    /** TSF value included in the beacon/probe response */
+    t_u8 time_stamp[8];
+
+    /** PHY parameter set */
+    IEEEtypes_PhyParamSet_t phy_param_set;
+
+    /** SS parameter set */
+    IEEEtypes_SsParamSet_t ss_param_set;
+
+    /** Capability information */
+    IEEEtypes_CapInfo_t cap_info;
+
+    /** WMM IE */
+    IEEEtypes_WmmParameter_t wmm_ie;
+
+    /** 802.11h BSS information */
+
+    /** Indicate disabling 11n when associate with AP */
+    t_u8 disable_11n;
+    /** 802.11n BSS information */
+    /** HT Capabilities IE */
+    IEEEtypes_HTCap_t *pht_cap;
+    /** HT Capabilities Offset */
+    /* t_u16 ht_cap_offset; */
+    /** HT Information IE */
+    IEEEtypes_HTInfo_t *pht_info;
+    /** HT Information Offset */
+    /* t_u16 ht_info_offset; */
+    /** Flag to indicate this is multi_bssid_ap */
+    t_u8 multi_bssid_ap;
+    /** the mac address of multi-bssid AP */
+    mlan_802_11_mac_addr multi_bssid_ap_addr;
+    /** 20/40 BSS Coexistence IE */
+    IEEEtypes_2040BSSCo_t *pbss_co_2040;
+    /** VHT Capabilities IE */
+    IEEEtypes_VHTCap_t *pvht_cap;
+    /** VHT Capabilities IE offset */
+    /** VHT Operations IE */
+    IEEEtypes_VHTOprat_t *pvht_oprat;
+    /** VHT Operations IE offset */
+    /** VHT Transmit Power Envelope IE */
+    IEEEtypes_VHTtxpower_t *pvht_txpower;
+    /** Operating Mode Notification IE */
+    IEEEtypes_OperModeNtf_t *ppoper_mode;
+    /** 20/40 BSS Coexistence Offset */
+    t_u16 bss_co_2040_offset;
+    /** Extended Capabilities IE */
+    IEEEtypes_ExtCap_t *pext_cap;
+    /** Extended Capabilities Offset */
+    t_u16 ext_cap_offset;
+    /** Overlapping BSS Scan Parameters IE */
+    IEEEtypes_OverlapBSSScanParam_t *poverlap_bss_scan_param;
+    /** Overlapping BSS Scan Parameters Offset */
+    t_u16 overlap_bss_offset;
+
+    /** Country information set */
+    IEEEtypes_CountryInfoFullSet_t country_info;
+
+    /** WPA IE */
+    IEEEtypes_VendorSpecific_t *pwpa_ie;
+    /** WPA IE offset in the beacon buffer */
+    t_u16 wpa_offset;
+    /** RSN IE */
+    IEEEtypes_Generic_t *prsn_ie;
+    /** RSN IE offset in the beacon buffer */
+    t_u16 rsn_offset;
+    /** WAPI IE */
+    IEEEtypes_Generic_t *pwapi_ie;
+    /** WAPI IE offset in the beacon buffer */
+    t_u16 wapi_offset;
+
+    /** Pointer to the returned scan response */
+    t_u8 *pbeacon_buf;
+    /** Length of the stored scan response */
+    t_u32 beacon_buf_size;
+    /** Max allocated size for updated scan response */
+    t_u32 beacon_buf_size_max;
+
+#if CONFIG_WPA_SUPP
+    /** Pointer to the returned scan response */
+    t_u8 *ies;
+    /** Length of the stored scan response */
+    t_u32 ies_len;
+#endif
+
+    /* Added for WMSDK */
+
+    /*
+     * Since we do not save the beacon buffer because it is too huge
+     * for us we need to save selected data structures for later
+     * perusal.
+     */
+    IEEEtypes_HTCap_t ht_cap_saved;
+    IEEEtypes_HTInfo_t ht_info_saved;
+    IEEEtypes_2040BSSCo_t bss_co_2040_saved;
+
+#if CONFIG_11AC
+    IEEEtypes_VHTCap_t vht_cap_saved;
+    IEEEtypes_VHTOprat_t vht_oprat_saved;
+    IEEEtypes_VHTtxpower_t vht_txpower_saved;
+    IEEEtypes_OperModeNtf_t poper_mode_saved;
+#endif
+    IEEEtypes_ExtCap_t ext_cap_saved;
+    bool ext_cap_exist;
+#if CONFIG_11AX
+    /** HE Capability IE */
+    IEEEtypes_HECap_t *phe_cap;
+    /** HE Capability IE offset */
+    t_u16 he_cap_offset;
+    /** HE operation IE */
+    IEEEtypes_HeOp_t *phe_oprat;
+    /** HE operation IE offset */
+    t_u16 he_oprat_offset;
+    IEEEtypes_HECap_t he_cap_saved;
+    IEEEtypes_HeOp_t he_oprat_saved;
+#endif
+    /*
+      fixme: The legacy code used IEEEtypes_RSN_IE_t which is of 24
+      bytes. There seems to be confusion about the exact structure to
+      use in this situation. Seems that 256 bytes are used by
+      mlan_private (wpa_ie). We cannot use that much here. Lets take a
+      reasonable amount.
+    */
+    unsigned char wpa_ie_buff[MLAN_WMSDK_MAX_WPA_IE_LEN];
+    size_t wpa_ie_buff_len;
+    unsigned char rsn_ie_buff[MLAN_WMSDK_MAX_WPA_IE_LEN];
+    size_t rsn_ie_buff_len;
+
+    bool wps_IE_exist;
+    t_u16 wps_session;
+
+    bool wpa2_entp_IE_exist;
+    /** RSNX IE */
+    IEEEtypes_Rsnx_t *prsnx_ie;
+    IEEEtypes_Rsnx_t rsnx_ie_saved;
+    /** RSNX IE offset in the beacon buffer */
+    t_u16 rsnx_offset;
+
+    bool brcm_ie_exist;
+    bool epigram_ie_exist;
+#if (CONFIG_11R) || (CONFIG_11K)
+    unsigned char md_ie_buff[MLAN_MAX_MDIE_LEN];
+    size_t md_ie_buff_len;
+    /* Mobility domain IE */
+    IEEEtypes_MobilityDomain_t *pmd_ie;
+    bool mob_domain_exist;
+#endif
+#if CONFIG_11K
+    bool rm_cap_exist;
+    IEEEtypes_RrmElement_t rm_cap_saved;
+    unsigned char vendor_ie_buff[MLAN_MAX_VENDOR_IE_LEN];
+    t_u8 vendor_ie_len;
+    bool neighbor_report_supported;
+#endif
+#if CONFIG_11V
+    bool bss_transition_supported;
+#endif
+#if CONFIG_DRIVER_MBO
+    bool mbo_assoc_disallowed;
+#endif
+} BSSDescriptor_t, *pBSSDescriptor_t;
+
+#endif /* !_MLAN_IEEE_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_init.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_init.h
new file mode 100644
index 0000000000..88bcd823d8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_init.h
@@ -0,0 +1,69 @@
+/** @file mlan_init.h
+ *
+ *  @brief This file defines the FW initialization data
+ *  structures.
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/13/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_INIT_H_
+#define _MLAN_INIT_H_
+
+/** Tx buffer size for firmware download*/
+#define FW_DNLD_TX_BUF_SIZE 620
+/** Rx buffer size for firmware download*/
+#define FW_DNLD_RX_BUF_SIZE 2048
+/** Max firmware retry */
+#define MAX_FW_RETRY 3
+
+/** Firmware has last block */
+#define FW_HAS_LAST_BLOCK 0x00000004
+
+/** Firmware data transmit size */
+#define FW_DATA_XMIT_SIZE sizeof(FWHeader) + DataLength + sizeof(t_u32)
+
+/** FWHeader */
+typedef struct _FWHeader
+{
+    /** FW download command */
+    t_u32 dnld_cmd;
+    /** FW base address */
+    t_u32 base_addr;
+    /** FW data length */
+    t_u32 data_length;
+    /** FW CRC */
+    t_u32 crc;
+} FWHeader;
+
+/** FWData */
+typedef struct _FWData
+{
+    /** FW data header */
+    FWHeader fw_header;
+    /** FW data sequence number */
+    t_u32 seq_num;
+    /** FW data buffer */
+    t_u8 data[1];
+} FWData;
+
+/** FWSyncHeader */
+typedef struct _FWSyncHeader
+{
+    /** FW sync header command */
+    t_u32 cmd;
+    /** FW sync header sequence number */
+    t_u32 seq_num;
+} FWSyncHeader;
+
+/** Convert sequence number and command fields of fwheader to correct endian format */
+#define endian_convert_syncfwheader(x)
+
+#endif /* _MLAN_INIT_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_ioctl.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_ioctl.h
new file mode 100644
index 0000000000..9036406c19
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_ioctl.h
@@ -0,0 +1,4033 @@
+/** @file mlan_ioctl.h
+ *
+ *  @brief This file declares the IOCTL data structures and APIs.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    11/07/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_IOCTL_H_
+#define _MLAN_IOCTL_H_
+
+/** Enumeration for IOCTL request ID */
+typedef enum _mlan_ioctl_req_id
+{
+    /* Scan Group */
+    MLAN_IOCTL_SCAN = 0x00010000,
+    MLAN_OID_SCAN_NORMAL,
+    MLAN_OID_SCAN_SPECIFIC_SSID,
+    MLAN_OID_SCAN_USER_CONFIG,
+    MLAN_OID_SCAN_CONFIG,
+    MLAN_OID_SCAN_GET_CURRENT_BSS,
+    MLAN_OID_SCAN_CANCEL,
+    MLAN_OID_SCAN_TABLE_FLUSH,
+    MLAN_OID_SCAN_BGSCAN_CONFIG,
+    /* BSS Configuration Group */
+    MLAN_IOCTL_BSS = 0x00020000,
+    MLAN_OID_BSS_START,
+    MLAN_OID_BSS_STOP,
+    MLAN_OID_BSS_MODE,
+    MLAN_OID_BSS_CHANNEL,
+    MLAN_OID_BSS_CHANNEL_LIST,
+    MLAN_OID_BSS_MAC_ADDR,
+    MLAN_OID_BSS_MULTICAST_LIST,
+    MLAN_OID_BSS_FIND_BSS,
+    MLAN_OID_IBSS_BCN_INTERVAL,
+    MLAN_OID_IBSS_ATIM_WINDOW,
+    MLAN_OID_IBSS_CHANNEL,
+    MLAN_OID_UAP_BSS_CONFIG,
+    MLAN_OID_UAP_DEAUTH_STA,
+    MLAN_OID_UAP_BSS_RESET,
+    MLAN_OID_BSS_ROLE,
+    MLAN_OID_UAP_ADD_STATION = 0x0002001C,
+#if CONFIG_ECSA
+    MLAN_OID_ACTION_CHAN_SWITCH = 0x0002001E,
+#endif
+
+    /* Radio Configuration Group */
+    MLAN_IOCTL_RADIO_CFG = 0x00030000,
+    MLAN_OID_RADIO_CTRL,
+    MLAN_OID_BAND_CFG,
+    MLAN_OID_ANT_CFG,
+
+    /* SNMP MIB Group */
+    MLAN_IOCTL_SNMP_MIB = 0x00040000,
+    MLAN_OID_SNMP_MIB_RTS_THRESHOLD,
+    MLAN_OID_SNMP_MIB_FRAG_THRESHOLD,
+    MLAN_OID_SNMP_MIB_RETRY_COUNT,
+    MLAN_OID_SNMP_MIB_DOT11D,
+    MLAN_OID_SNMP_MIB_DOT11H,
+    MLAN_OID_SNMP_MIB_DTIM_PERIOD,
+    MLAN_OID_SNMP_MIB_CTRL_DEAUTH,
+
+    /* Status Information Group */
+    MLAN_IOCTL_GET_INFO = 0x00050000,
+    MLAN_OID_GET_STATS,
+    MLAN_OID_GET_SIGNAL,
+    MLAN_OID_GET_FW_INFO,
+    MLAN_OID_GET_VER_EXT,
+    MLAN_OID_GET_BSS_INFO,
+    MLAN_OID_GET_DEBUG_INFO,
+    MLAN_OID_UAP_STA_LIST,
+
+    /* Security Configuration Group */
+    MLAN_IOCTL_SEC_CFG = 0x00060000,
+    MLAN_OID_SEC_CFG_AUTH_MODE,
+    MLAN_OID_SEC_CFG_ENCRYPT_MODE,
+    MLAN_OID_SEC_CFG_WPA_ENABLED,
+    MLAN_OID_SEC_CFG_ENCRYPT_KEY,
+    MLAN_OID_SEC_CFG_PASSPHRASE,
+    MLAN_OID_SEC_CFG_PASSWORD,
+    MLAN_OID_SEC_CFG_EWPA_ENABLED,
+    MLAN_OID_SEC_CFG_ESUPP_MODE,
+    MLAN_OID_SEC_CFG_WAPI_ENABLED,
+    MLAN_OID_SEC_CFG_PORT_CTRL_ENABLED,
+    MLAN_OID_SEC_CFG_REPORT_MIC_ERR,
+    MLAN_OID_SEC_QUERY_KEY,
+
+    /* Rate Group */
+    MLAN_IOCTL_RATE = 0x00070000,
+    MLAN_OID_RATE_CFG,
+    MLAN_OID_GET_DATA_RATE,
+    MLAN_OID_SUPPORTED_RATES,
+
+    /* Power Configuration Group */
+    MLAN_IOCTL_POWER_CFG = 0x00080000,
+    MLAN_OID_POWER_CFG,
+    MLAN_OID_POWER_CFG_EXT,
+
+    /* Power Management Configuration Group */
+    MLAN_IOCTL_PM_CFG = 0x00090000,
+    MLAN_OID_PM_CFG_IEEE_PS,
+    MLAN_OID_PM_CFG_HS_CFG,
+    MLAN_OID_PM_CFG_INACTIVITY_TO,
+    MLAN_OID_PM_CFG_DEEP_SLEEP,
+    MLAN_OID_PM_CFG_SLEEP_PD,
+    MLAN_OID_PM_CFG_PS_CFG,
+    MLAN_OID_PM_CFG_SLEEP_PARAMS,
+    MLAN_OID_PM_CFG_PS_MODE,
+    MLAN_OID_PM_INFO,
+    MLAN_OID_PM_HS_WAKEUP_REASON = 0x0009000B,
+
+    /* WMM Configuration Group */
+    MLAN_IOCTL_WMM_CFG = 0x000A0000,
+    MLAN_OID_WMM_CFG_ENABLE,
+    MLAN_OID_WMM_CFG_QOS,
+    MLAN_OID_WMM_CFG_ADDTS,
+    MLAN_OID_WMM_CFG_DELTS,
+    MLAN_OID_WMM_CFG_QUEUE_CONFIG,
+    MLAN_OID_WMM_CFG_QUEUE_STATS,
+    MLAN_OID_WMM_CFG_QUEUE_STATUS,
+    MLAN_OID_WMM_CFG_TS_STATUS,
+
+    /* WPS Configuration Group */
+    MLAN_IOCTL_WPS_CFG = 0x000B0000,
+    MLAN_OID_WPS_CFG_SESSION,
+
+    /* 802.11n Configuration Group */
+    MLAN_IOCTL_11N_CFG = 0x000C0000,
+    MLAN_OID_11N_CFG_TX,
+    MLAN_OID_11N_HTCAP_CFG,
+    MLAN_OID_11N_CFG_ADDBA_REJECT,
+    MLAN_OID_11N_CFG_AGGR_PRIO_TBL,
+    MLAN_OID_11N_CFG_ADDBA_PARAM,
+    MLAN_OID_11N_CFG_MAX_TX_BUF_SIZE,
+    MLAN_OID_11N_CFG_AMSDU_AGGR_CTRL,
+    MLAN_OID_11N_CFG_SUPPORTED_MCS_SET,
+    MLAN_OID_11N_CFG_TX_BF_CAP,
+
+    MLAN_OID_11N_CFG_DELBA            = 0x000C000C,
+    MLAN_OID_11N_CFG_REJECT_ADDBA_REQ = 0x000C000D,
+
+    /* 802.11d Configuration Group */
+    MLAN_IOCTL_11D_CFG = 0x000D0000,
+    MLAN_OID_11D_CFG_ENABLE,
+    MLAN_OID_11D_CLR_CHAN_TABLE,
+    MLAN_OID_11D_DOMAIN_INFO,
+
+    /* Register Memory Access Group */
+    MLAN_IOCTL_REG_MEM = 0x000E0000,
+    MLAN_OID_REG_RW,
+    MLAN_OID_EEPROM_RD,
+    MLAN_OID_MEM_RW,
+
+    /* Multi-Radio Configuration Group */
+    MLAN_IOCTL_MFR_CFG = 0x00100000,
+
+    /* 802.11h Configuration Group */
+    MLAN_IOCTL_11H_CFG = 0x00110000,
+    MLAN_OID_11H_CHANNEL_CHECK,
+    MLAN_OID_11H_LOCAL_POWER_CONSTRAINT,
+
+
+#if CONFIG_11AX
+    /* 802.11ax Configuration Group  */
+    MLAN_IOCTL_11AX_CFG   = 0x00170000,
+    MLAN_OID_11AX_HE_CFG  = 0x00170001,
+    MLAN_OID_11AX_CMD_CFG = 0x00170002,
+#endif /* ENABLE_802_11AX */
+
+    /* Miscellaneous Configuration Group */
+    MLAN_IOCTL_MISC_CFG = 0x00200000,
+    MLAN_OID_MISC_GEN_IE,
+    MLAN_OID_MISC_REGION,
+    MLAN_OID_MISC_WARM_RESET,
+    MLAN_OID_MISC_HOST_CMD,
+    MLAN_OID_MISC_SYS_CLOCK,
+    MLAN_OID_MISC_SOFT_RESET,
+    MLAN_OID_MISC_WWS,
+    MLAN_OID_MISC_INIT_SHUTDOWN,
+    MLAN_OID_MISC_CUSTOM_IE,
+    MLAN_OID_MISC_TX_DATAPAUSE,
+    MLAN_OID_MISC_IP_ADDR,
+    MLAN_OID_MISC_MAC_CONTROL,
+    MLAN_OID_MISC_MEF_CFG,
+    MLAN_OID_MISC_CFP_CODE,
+    MLAN_OID_MISC_COUNTRY_CODE,
+    MLAN_OID_MISC_THERMAL,
+    MLAN_OID_MISC_RX_MGMT_IND,
+    MLAN_OID_MISC_SUBSCRIBE_EVENT,
+#ifdef DEBUG_LEVEL1
+    MLAN_OID_MISC_DRVDBG,
+#endif
+    MLAN_OID_MISC_HOTSPOT_CFG,
+    MLAN_OID_MISC_OTP_USER_DATA,
+#ifdef WLAN_LOW_POWER_ENABLE
+    MLAN_OID_MISC_LOW_PWR_MODE,
+#endif // WLAN_LOW_POWER_ENABLE
+#if CONFIG_GTK_REKEY_OFFLOAD
+    MLAN_OID_MISC_CONFIG_GTK_REKEY_OFFLOAD = 0x00200037,
+#endif
+#if CONFIG_ECSA
+    MLAN_OID_MISC_OPER_CLASS = 0x00200038,
+#endif
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+    MLAN_OID_MISC_IND_RST_CFG = 0x00200040,
+#endif
+#if CONFIG_ECSA
+    MLAN_OID_MISC_OPER_CLASS_CHECK = 0x00200049,
+#endif
+    MLAN_OID_MISC_GET_REGIONPWR_CFG,
+#if CONFIG_WIFI_CLOCKSYNC
+    MLAN_OID_MISC_GPIO_TSF_LATCH = 0x00200082,
+    MLAN_OID_MISC_GET_TSF_INFO   = 0x00200083
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+} mlan_ioctl_req_id;
+
+/** Sub command size */
+#define MLAN_SUB_COMMAND_SIZE 4U
+
+/** Enumeration for the action of IOCTL request */
+typedef enum _mlan_act_ioctl
+{
+    MLAN_ACT_SET = 1,
+    MLAN_ACT_GET,
+    MLAN_ACT_CANCEL,
+    MLAN_ACT_CLEAR,
+    MLAN_ACT_RESET,
+    MLAN_ACT_DEFAULT
+} mlan_act_ioctl;
+
+/** Enumeration for generic enable/disable */
+enum _mlan_act_generic
+{
+    MLAN_ACT_DISABLE = 0,
+    MLAN_ACT_ENABLE  = 1
+};
+
+/** Enumeration for scan mode */
+enum _mlan_scan_mode
+{
+    MLAN_SCAN_MODE_UNCHANGED = 0,
+    MLAN_SCAN_MODE_BSS,
+    MLAN_SCAN_MODE_IBSS,
+    MLAN_SCAN_MODE_ANY
+};
+
+/** Enumeration for scan type */
+typedef enum _mlan_scan_type
+{
+    MLAN_SCAN_TYPE_UNCHANGED = 0,
+    MLAN_SCAN_TYPE_ACTIVE,
+    MLAN_SCAN_TYPE_PASSIVE,
+#if defined(RW610) || defined(SD9177)
+    MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE,
+#endif
+} mlan_scan_type;
+
+/** mlan_ioctl_req data structure */
+typedef struct _mlan_ioctl_req
+{
+    /** Status code from firmware/driver */
+    mlan_error_code status_code;
+    /** BSS index number for multiple BSS support */
+    t_u32 bss_index;
+    /** Request id */
+    t_u32 req_id;
+    /** Action: set or get */
+    mlan_act_ioctl action;
+
+    /** Pointer to buffer */
+    t_u8 *pbuf;
+    /** Length of buffer */
+    t_u32 buf_len;
+    /** Length of the data read/written in buffer */
+    t_u32 data_read_written;
+    /** Length of buffer needed */
+    t_u32 buf_len_needed;
+    /** Reserved for MOAL module */
+    t_ptr reserved_1;
+} mlan_ioctl_req, *pmlan_ioctl_req;
+
+/** Max number of supported rates */
+#define MLAN_SUPPORTED_RATES 32
+
+/** RSSI scan */
+#define SCAN_RSSI(RSSI) (0x100U - ((t_u8)(RSSI)))
+
+/** Max passive scan time for each channel in milliseconds */
+#define MRVDRV_MAX_PASSIVE_SCAN_CHAN_TIME 2000
+
+/** Max active scan time for each channel in milliseconds  */
+#define MRVDRV_MAX_ACTIVE_SCAN_CHAN_TIME 500
+
+#if CONFIG_SCAN_CHANNEL_GAP
+/** Max gap time between 2 scan in milliseconds  */
+#define MRVDRV_MAX_SCAN_CHAN_GAP_TIME 500
+#endif
+
+/** Maximum number of probes to send on each channel */
+#define MAX_PROBES 4U
+
+/** Default number of probes to send on each channel */
+#define DEFAULT_PROBES 2
+
+/**
+ *  @brief Sub-structure passed in wlan_ioctl_get_scan_table_entry for each BSS
+ *
+ *  Fixed field information returned for the scan response in the IOCTL
+ *    response.
+ */
+typedef struct _wlan_get_scan_table_fixed
+{
+    /** BSSID of this network */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Channel this beacon/probe response was detected */
+    t_u8 channel;
+    /** RSSI for the received packet */
+    t_u8 rssi;
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** channel load */
+    t_u8 chan_load;
+#endif
+    /** TSF value in microseconds from the firmware at packet reception */
+    t_u64 network_tsf;
+} wlan_get_scan_table_fixed;
+
+/** mlan_802_11_ssid data structure */
+typedef struct _mlan_802_11_ssid
+{
+    /** SSID Length */
+    t_u32 ssid_len;
+    /** SSID information field */
+    t_u8 ssid[MLAN_MAX_SSID_LENGTH];
+} mlan_802_11_ssid, *pmlan_802_11_ssid;
+
+typedef MLAN_PACK_START struct _tx_status_event
+{
+    /** packet type */
+    t_u8 packet_type;
+    /** tx_token_id */
+    t_u8 tx_token_id;
+    /** 0--success, 1--fail, 2--watchdogtimeout */
+    t_u8 status;
+} MLAN_PACK_END tx_status_event;
+
+/**
+ *  Sructure to retrieve the scan table
+ */
+typedef struct
+{
+    /**
+     *  - Zero based scan entry to start retrieval in command request
+     *  - Number of scans entries returned in command response
+     */
+    t_u32 scan_number;
+    /**
+     * Buffer marker for multiple wlan_ioctl_get_scan_table_entry structures.
+     *   Each struct is padded to the nearest 32 bit boundary.
+     */
+    t_u8 scan_table_entry_buf[1];
+} wlan_ioctl_get_scan_table_info;
+
+/**
+ *  Structure passed in the wlan_ioctl_get_scan_table_info for each
+ *    BSS returned in the WLAN_GET_SCAN_RESP IOCTL
+ */
+typedef struct _wlan_ioctl_get_scan_table_entry
+{
+    /**
+     *  Fixed field length included in the response.
+     *
+     *  Length value is included so future fixed fields can be added to the
+     *   response without breaking backwards compatibility.  Use the length
+     *   to find the offset for the bssInfoLength field, not a sizeof() calc.
+     */
+    t_u32 fixed_field_length;
+
+    /**
+     *  Length of the BSS Information (probe resp or beacon) that
+     *    follows after the fixed_field_length
+     */
+    t_u32 bss_info_length;
+
+    /**
+     *  Always present, fixed length data fields for the BSS
+     */
+    wlan_get_scan_table_fixed fixed_fields;
+
+    /*
+     *  Probe response or beacon scanned for the BSS.
+     *
+     *  Field layout:
+     *   - TSF              8 octets
+     *   - Beacon Interval  2 octets
+     *   - Capability Info  2 octets
+     *
+     *   - IEEE Infomation Elements; variable number & length per 802.11 spec
+     */
+    /* t_u8 bss_info_buffer[0]; */
+} wlan_ioctl_get_scan_table_entry;
+
+/** Type definition of mlan_scan_time_params */
+typedef struct _mlan_scan_time_params
+{
+    /** Scan channel time for specific scan in milliseconds */
+    t_u32 specific_scan_time;
+    /** Scan channel time for active scan in milliseconds */
+    t_u32 active_scan_time;
+    /** Scan channel time for passive scan in milliseconds */
+    t_u32 passive_scan_time;
+} mlan_scan_time_params, *pmlan_scan_time_params;
+
+/** Type definition of mlan_user_scan */
+typedef struct _mlan_user_scan
+{
+    /** Length of scan_cfg_buf */
+    t_u32 scan_cfg_len;
+    /** Buffer of scan config */
+    t_u8 scan_cfg_buf[1];
+} mlan_user_scan, *pmlan_user_scan;
+
+/** Type definition of mlan_scan_req */
+typedef struct _mlan_scan_req
+{
+    /** BSS mode for scanning */
+    t_u32 scan_mode;
+    /** Scan type */
+    mlan_scan_type scan_type;
+    /** SSID */
+    mlan_802_11_ssid scan_ssid;
+    /** Scan time parameters */
+    mlan_scan_time_params scan_time;
+    /** Scan config parameters in user scan */
+    mlan_user_scan user_scan;
+} mlan_scan_req, *pmlan_scan_req;
+
+/** Type definition of mlan_ds_misc_tx_frame for MLAN_OID_MISC_TX_FRAME */
+typedef struct _mlan_ds_misc_tx_frame
+{
+    /** Band Configuration */
+    Band_Config_t bandcfg;
+    /** channel */
+    t_u8 channel;
+    /** Buffer type: data, cmd, event etc. */
+    mlan_buf_type buf_type;
+    /** QoS priority */
+    t_u32 priority;
+    /** Flags for this buffer */
+    t_u32 flags;
+    /** tx_seq_num */
+    t_u32 tx_seq_num;
+    /** tx_buf length */
+    t_u16 data_len;
+    /** Tx buffer */
+    t_u8 tx_buf[512];
+} mlan_ds_misc_tx_frame;
+
+/** Type defnition of mlan_scan_resp */
+typedef struct _mlan_scan_resp
+{
+    /** Number of scan result */
+    t_u32 num_in_scan_table;
+    /** Scan table */
+    t_u8 *pscan_table;
+    /* Age in seconds */
+    t_u32 age_in_secs;
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** channel statstics */
+    t_u8 *pchan_stats;
+    /** Number of records in the chan_stats */
+    t_u32 num_in_chan_stats;
+#endif
+} mlan_scan_resp, *pmlan_scan_resp;
+
+/** Type definition of mlan_scan_cfg */
+typedef struct _mlan_scan_cfg
+{
+    /** Scan type */
+    mlan_scan_type scan_type;
+    /** BSS mode for scanning */
+    t_u32 scan_mode;
+    /** Scan probe */
+    t_u32 scan_probe;
+    /** Scan time parameters */
+    mlan_scan_time_params scan_time;
+#if CONFIG_EXT_SCAN_SUPPORT
+    /** Extended Scan */
+    t_u32 ext_scan;
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** scan channel gap */
+    t_u32 scan_chan_gap;
+#endif
+#endif
+} mlan_scan_cfg, *pmlan_scan_cfg;
+
+/** Type defnition of mlan_ds_scan for MLAN_IOCTL_SCAN */
+typedef struct _mlan_ds_scan
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Scan request/response */
+    union
+    {
+        /** Scan request */
+        mlan_scan_req scan_req;
+        /** Scan response */
+        mlan_scan_resp scan_resp;
+        /** Scan config parameters in user scan */
+        mlan_user_scan user_scan;
+        /** Scan config parameters */
+        mlan_scan_cfg scan_cfg;
+    } param;
+} mlan_ds_scan, *pmlan_ds_scan;
+
+/*-----------------------------------------------------------------*/
+/** BSS Configuration Group */
+/*-----------------------------------------------------------------*/
+/** Enumeration for BSS mode */
+typedef enum _mlan_bss_mode
+{
+    MLAN_BSS_MODE_NEGATIVE = -1,
+    MLAN_BSS_MODE_INFRA    = 1,
+    MLAN_BSS_MODE_IBSS,
+    MLAN_BSS_MODE_AUTO
+} mlan_bss_mode;
+
+/** Maximum key length */
+#define MLAN_MAX_KEY_LENGTH 32U
+
+/** max Wmm AC queues */
+#define MAX_AC_QUEUES 4
+
+/** Maximum atim window in milliseconds */
+#define MLAN_MAX_ATIM_WINDOW 50
+
+/** Minimum beacon interval */
+#define MLAN_MIN_BEACON_INTERVAL 20
+/** Maximum beacon interval */
+#define MLAN_MAX_BEACON_INTERVAL 1000
+/** Default beacon interval */
+#define MLAN_BEACON_INTERVAL 100
+
+/** Receive all packets */
+#define MLAN_PROMISC_MODE 1
+/** Receive multicast packets in multicast list */
+#define MLAN_MULTICAST_MODE 2
+/** Receive all multicast packets */
+#define MLAN_ALL_MULTI_MODE 4
+
+/** Maximum size of multicast list */
+#define MLAN_MAX_MULTICAST_LIST_SIZE 32U
+
+/** mlan_multicast_list data structure for MLAN_OID_BSS_MULTICAST_LIST */
+typedef struct _mlan_multicast_list
+{
+    /** Multicast mode */
+    t_u32 mode;
+    /** Number of multicast addresses in the list */
+    t_u32 num_multicast_addr;
+    /** Multicast address list */
+    mlan_802_11_mac_addr mac_list[MLAN_MAX_MULTICAST_LIST_SIZE];
+} mlan_multicast_list, *pmlan_multicast_list;
+
+/** World Wide Safe Mode Max channel */
+#if CONFIG_5GHz_SUPPORT
+#define MLAN_WWSM_MAX_CHANNEL 15
+#else
+#define MLAN_WWSM_MAX_CHANNEL 11
+#endif
+
+/** Max channel */
+#if CONFIG_5GHz_SUPPORT
+#if (CONFIG_UNII4_BAND_SUPPORT)
+#define MLAN_MAX_CHANNEL 177U
+#else
+#define MLAN_MAX_CHANNEL 165U
+#endif
+#else
+#define MLAN_MAX_CHANNEL 14U
+#endif
+
+/** Maximum number of channels in table */
+#define MLAN_MAX_CHANNEL_NUM 128
+
+/** Channel/frequence for MLAN_OID_BSS_CHANNEL */
+typedef struct _chan_freq
+{
+    /** Channel Number */
+    t_u32 channel;
+    /** Frequency of this Channel */
+    t_u32 freq;
+} chan_freq_t;
+
+/** mlan_chan_list data structure for MLAN_OID_BSS_CHANNEL_LIST */
+typedef struct _mlan_chan_list
+{
+    /** Number of channel */
+    t_u32 num_of_chan;
+    /** Channel-Frequency table */
+    chan_freq_t cf[MLAN_MAX_CHANNEL_NUM];
+} mlan_chan_list;
+
+/** mlan_ssid_bssid  data structure for MLAN_OID_BSS_START and MLAN_OID_BSS_FIND_BSS */
+typedef struct _mlan_ssid_bssid
+{
+    /** SSID */
+    mlan_802_11_ssid ssid;
+    /** BSSID */
+    mlan_802_11_mac_addr bssid;
+    /** index in BSSID list, start from 1 */
+    t_u32 idx;
+} mlan_ssid_bssid;
+
+/** UAP FLAG: Host based */
+#define UAP_FLAG_HOST_BASED MBIT(0)
+/** UAP FLAG: Host mlme */
+#define UAP_FLAG_HOST_MLME MBIT(1)
+
+#if CONFIG_11AX
+#define MLAN_11AXCMD_SR_SUBID           0x102
+#define MLAN_11AXCMD_BEAM_SUBID         0x103
+#define MLAN_11AXCMD_HTC_SUBID          0x104
+#define MLAN_11AXCMD_TXOMI_SUBID        0x105
+#define MLAN_11AXCMD_OBSS_TOLTIME_SUBID 0x106
+#define MLAN_11AXCMD_TXOPRTS_SUBID      0x108
+#define MLAN_11AXCMD_RUPOWER_SUBID      0x117
+
+#if CONFIG_11AX_TWT
+#define MLAN_11AX_TWT_SETUP_SUBID       0x114
+#define MLAN_11AX_TWT_TEARDOWN_SUBID    0x115
+#define MLAN_11AX_TWT_REPORT_SUBID      0x116
+#endif /* CONFIG_11AX_TWT */
+
+#if CONFIG_MMSF
+#define MLAN_11AX_DEBUG_MMSF_SUBID 0x12d
+#endif
+#endif /* CONFIG_11AX */
+
+#if CONFIG_WIFI_RECOVERY
+#define MLAN_RECOVERY_TEST_SUBID 0x117
+#endif
+
+/** Maximum packet forward control value */
+#define MAX_PKT_FWD_CTRL 15
+/** Maximum BEACON period */
+#define MAX_BEACON_PERIOD 4000U
+/** Minimum BEACON period */
+#define MIN_BEACON_PERIOD 50U
+/** Maximum Channel Switch count */
+#define MAX_CHSW_COUNT 15U
+/** Minimum Channel Switch count */
+#define MIN_CHSW_COUNT 5U
+/** Maximum DTIM period */
+#define MAX_DTIM_PERIOD 100U
+/** Minimum DTIM period */
+#define MIN_DTIM_PERIOD 1U
+/** Maximum TX Power Limit */
+#define MAX_TX_POWER 20
+/** Minimum TX Power Limit */
+#define MIN_TX_POWER 0
+/** MAX station count */
+#define MAX_UAP_STA_COUNT 10
+/** Maximum RTS threshold */
+#define MAX_RTS_THRESHOLD 2347
+/** Maximum fragmentation threshold */
+#define MAX_FRAG_THRESHOLD 2346
+/** Minimum fragmentation threshold */
+#define MIN_FRAG_THRESHOLD 256
+/** data rate 54 M */
+#define DATA_RATE_54M 108
+/** Maximum value of bcast_ssid_ctl */
+#define MAX_BCAST_SSID_CTL 2
+/** antenna A */
+#define ANTENNA_MODE_A 0
+/** antenna B */
+#define ANTENNA_MODE_B 1
+/** transmit antenna */
+#define TX_ANTENNA 1
+/** receive antenna */
+#define RX_ANTENNA 0
+/** Maximum stage out time */
+#define MAX_STAGE_OUT_TIME 864000
+/** Minimum stage out time */
+#define MIN_STAGE_OUT_TIME 300
+/** Maximum Retry Limit */
+#define MAX_RETRY_LIMIT 14
+
+/** Maximum group key timer in seconds */
+#define MAX_GRP_TIMER 86400
+
+/** Maximum value of 4 byte configuration */
+#define MAX_VALID_DWORD 0x7FFFFFFF /* (1 << 31) - 1 */
+
+/** Band config ACS mode */
+#define BAND_CONFIG_ACS_MODE 0x40U
+/** Band config manual */
+#define BAND_CONFIG_MANUAL 0x00
+
+/** Maximum channel number in bg mode */
+#define MAX_CHANNELS_BG 14U
+
+/** Maximum data rates */
+#define MAX_DATA_RATES 14U
+
+/** auto data rate */
+#define DATA_RATE_AUTO 0
+
+/**filter mode: disable */
+#define MAC_FILTER_MODE_DISABLE 0
+/**filter mode: block mac address */
+#define MAC_FILTER_MODE_ALLOW_MAC 1
+/**filter mode: block mac address */
+#define MAC_FILTER_MODE_BLOCK_MAC 2
+/** Maximum mac filter num */
+#define MAX_MAC_FILTER_NUM 16
+
+/* Bitmap for protocol to use */
+/** No security */
+#define PROTOCOL_NO_SECURITY 0x01
+/** Static WEP */
+#define PROTOCOL_STATIC_WEP 0x02
+/** WPA */
+#define PROTOCOL_WPA 0x08U
+/** WPA2 */
+#define PROTOCOL_WPA2 0x20U
+/** WP2 Mixed */
+#define PROTOCOL_WPA2_MIXED 0x28U
+/** EAP */
+#define PROTOCOL_EAP 0x40U
+/** WAPI */
+#define PROTOCOL_WAPI 0x80U
+/** WPA3 SAE */
+#define PROTOCOL_WPA3_SAE 256U
+#if CONFIG_DRIVER_OWE
+/** OWE */
+#define PROTOCOL_OWE 512U
+#endif
+
+/** Key_mgmt_psk_sha256 */
+#define KEY_MGMT_PSK_SHA256 0x100
+/** Key_mgmt_sae */
+#define KEY_MGMT_SAE 0x400
+#if CONFIG_DRIVER_OWE
+/** Key_mgmt_owe */
+#define KEY_MGMT_OWE 0x200
+#endif
+/** Key_mgmt_none */
+#define KEY_MGMT_NONE 0x04
+/** Key_mgmt_psk */
+#define KEY_MGMT_PSK 0x02
+/** Key_mgmt_psk_sha256 */
+#define KEY_MGMT_PSK_SHA256 0x100
+/** Key_mgmt_eap  */
+#define KEY_MGMT_EAP 0x01
+/** Key_mgmt_psk sha256 */
+#define KEY_MGMT_PSK_SHA256 0x100
+
+/** TKIP */
+#define CIPHER_TKIP 0x04
+/** AES CCMP */
+#define CIPHER_AES_CCMP 0x08
+
+/** Valid cipher bitmap */
+#define VALID_CIPHER_BITMAP 0x0cU
+
+#if CONFIG_NET_MONITOR
+/** Maximum monior mac filter num */
+#define MAX_MONIT_MAC_FILTER_NUM 3
+#endif
+
+/** Channel List Entry */
+typedef struct _channel_list
+{
+    /** Channel Number */
+    t_u8 chan_number;
+    /** Band Config */
+    t_u8 band_config_type;
+} scan_chan_list;
+
+/** mac_filter data structure */
+typedef struct _mac_filter
+{
+    /** mac filter mode */
+    t_u16 filter_mode;
+    /** mac adress count */
+    t_u16 mac_count;
+    /** mac address list */
+    mlan_802_11_mac_addr mac_list[MAX_MAC_FILTER_NUM];
+} mac_filter;
+
+/** wpa parameter */
+typedef struct _wpa_param
+{
+    /** Pairwise cipher WPA */
+    t_u8 pairwise_cipher_wpa;
+    /** Pairwise cipher WPA2 */
+    t_u8 pairwise_cipher_wpa2;
+    /** group cipher */
+    t_u8 group_cipher;
+    /** RSN replay protection */
+    t_u8 rsn_protection;
+    /** passphrase length */
+    t_u32 length;
+    /** passphrase */
+    t_u8 passphrase[64];
+    /** password length */
+    t_u32 password_length;
+    /** wpa3 sae password */
+    t_u8 password[255];
+    /**group key rekey time in seconds */
+    t_u32 gk_rekey_time;
+} wpa_param;
+
+/** wep key */
+typedef struct _wep_key
+{
+    /** key index 0-3 */
+    t_u8 key_index;
+    /** is default */
+    t_u8 is_default;
+    /** length */
+    t_u16 length;
+    /** key data */
+    t_u8 key[26];
+} wep_key;
+
+/** wep param */
+typedef struct _wep_param
+{
+    /** key 0 */
+    wep_key key0;
+    /** key 1 */
+    wep_key key1;
+    /** key 2 */
+    wep_key key2;
+    /** key 3 */
+    wep_key key3;
+} wep_param;
+
+/** Data structure of WMM QoS information */
+typedef struct _wmm_qos_info_t
+{
+    /** Parameter set count */
+    t_u8 para_set_count : 4;
+    /** Reserved */
+    t_u8 reserved : 3;
+    /** QoS UAPSD */
+    t_u8 qos_uapsd : 1;
+} wmm_qos_info_t, *pwmm_qos_info_t;
+
+/** Data structure of WMM ECW */
+typedef struct _wmm_ecw_t
+{
+    /** Minimum Ecw */
+    t_u8 ecw_min : 4;
+    /** Maximum Ecw */
+    t_u8 ecw_max : 4;
+} wmm_ecw_t, *pwmm_ecw_t;
+
+/** Data structure of WMM Aci/Aifsn */
+typedef struct _wmm_aci_aifsn_t
+{
+    /** Aifsn */
+    t_u8 aifsn : 4;
+    /** Acm */
+    t_u8 acm : 1;
+    /** Aci */
+    t_u8 aci : 2;
+    /** Reserved */
+    t_u8 reserved : 1;
+} wmm_aci_aifsn_t, *pwmm_aci_aifsn_t;
+
+/** Data structure of WMM AC parameters  */
+typedef struct _wmm_ac_parameters_t
+{
+    wmm_aci_aifsn_t aci_aifsn; /**< AciAifSn */
+    wmm_ecw_t ecw;             /**< Ecw */
+    t_u16 tx_op_limit;         /**< Tx op limit */
+} wmm_ac_parameters_t, *pwmm_ac_parameters_t;
+
+/** Data structure of WMM parameter IE  */
+typedef struct _wmm_parameter_t
+{
+    /** OuiType:  00:50:f2:02 */
+    t_u8 ouitype[4];
+    /** Oui subtype: 01 */
+    t_u8 ouisubtype;
+    /** version: 01 */
+    t_u8 version;
+    /** QoS information */
+    t_u8 qos_info;
+    /** Reserved */
+    t_u8 reserved;
+    /** AC Parameters Record WMM_AC_BE, WMM_AC_BK, WMM_AC_VI, WMM_AC_VO */
+    wmm_ac_parameters_t ac_params[MAX_AC_QUEUES];
+} wmm_parameter_t, *pwmm_parameter_t;
+
+/** mlan_bss_param
+ * Note: For each entry you must enter an invalid value
+ * in the MOAL function woal_set_sys_config_invalid_data().
+ * Otherwise for a valid data an unwanted TLV will be
+ * added to that command.
+ */
+typedef struct _mlan_uap_bss_param
+{
+    /** AP mac addr */
+    mlan_802_11_mac_addr mac_addr;
+    /** SSID */
+    mlan_802_11_ssid ssid;
+    /** Broadcast ssid control */
+    t_u8 bcast_ssid_ctl;
+    /** Radio control: on/off */
+    t_u8 radio_ctl;
+    /** dtim period */
+    t_u8 dtim_period;
+    /** beacon period */
+    t_u16 beacon_period;
+    /** channel switch time to send ECSA */
+    t_u8 chan_sw_count;
+    /** rates */
+    t_u8 rates[MAX_DATA_RATES];
+    /** Tx data rate */
+    t_u16 tx_data_rate;
+    /** multicast/broadcast data rate */
+    t_u16 mcbc_data_rate;
+    /** Tx power level in dBm */
+    t_u8 tx_power_level;
+    /** Tx antenna */
+    t_u8 tx_antenna;
+    /** Rx antenna */
+    t_u8 rx_antenna;
+    /** packet forward control */
+    t_u8 pkt_forward_ctl;
+    /** max station count */
+    t_u16 max_sta_count;
+    /** mac filter */
+    mac_filter filter;
+    /** station ageout timer in unit of 100ms  */
+    t_u32 sta_ageout_timer;
+    /** PS station ageout timer in unit of 100ms  */
+    t_u32 ps_sta_ageout_timer;
+    /** RTS threshold */
+    t_u16 rts_threshold;
+    /** fragmentation threshold */
+    t_u16 frag_threshold;
+    /**  retry_limit */
+    t_u16 retry_limit;
+    /**  pairwise update timeout in milliseconds */
+    t_u32 pairwise_update_timeout;
+    /** pairwise handshake retries */
+    t_u32 pwk_retries;
+    /**  groupwise update timeout in milliseconds */
+    t_u32 groupwise_update_timeout;
+    /** groupwise handshake retries */
+    t_u32 gwk_retries;
+    /** preamble type */
+    t_u8 preamble_type;
+    /** band cfg */
+    t_u8 band_cfg;
+    /** channel */
+    t_u8 channel;
+    /** auth mode */
+    t_u16 auth_mode;
+    /** PWE derivation */
+    t_u8 pwe_derivation;
+    /** transition disable */
+    t_u8 transition_disable;
+    /** encryption protocol */
+    t_u16 protocol;
+    /** key managment type */
+    t_u16 key_mgmt;
+    /** wep param */
+    wep_param wep_cfg;
+    /** wpa param */
+    wpa_param wpa_cfg;
+    /** Mgmt IE passthru mask */
+    t_u32 mgmt_ie_passthru_mask;
+    /*
+     * 11n HT Cap  HTCap_t  ht_cap
+     */
+    /** HT Capabilities Info field */
+    t_u16 ht_cap_info;
+    /** A-MPDU Parameters field */
+    t_u8 ampdu_param;
+    /** Supported MCS Set field */
+    t_u8 supported_mcs_set[16];
+    /** HT Extended Capabilities field */
+    t_u16 ht_ext_cap;
+    /** Transmit Beamforming Capabilities field */
+    t_u32 tx_bf_cap;
+    /** Antenna Selection Capability field */
+    t_u8 asel;
+    /** Enable 2040 Coex */
+    t_u8 enable_2040coex;
+    /** key management operation */
+    t_u16 key_mgmt_operation;
+    /** BSS status */
+    t_u16 bss_status;
+    /** Number of channels in scan_channel_list */
+    t_u32 num_of_chan;
+    /** scan channel list in ACS mode */
+    scan_chan_list chan_list[MLAN_MAX_CHANNEL];
+    /** Wmm parameters */
+    wmm_parameter_t wmm_para;
+    /** uap host based config */
+    t_u32 uap_host_based_config;
+} mlan_uap_bss_param;
+
+/** mlan_deauth_param */
+typedef struct _mlan_deauth_param
+{
+    /** STA mac addr */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** deauth reason */
+    t_u16 reason_code;
+} mlan_deauth_param;
+
+
+#if CONFIG_ECSA
+/** mlan_chan_switch_param */
+typedef struct _mlan_action_chan_switch
+{
+    /** mode*/
+    t_u8 mode;
+    /** switch mode*/
+    t_u8 chan_switch_mode;
+    /** oper class*/
+    t_u8 new_oper_class;
+    /** new channel */
+    t_u8 new_channel_num;
+    /** chan_switch_count */
+    t_u8 chan_switch_count;
+} mlan_action_chan_switch;
+
+typedef struct _mlan_ds_bw_chan_oper
+{
+    /* bandwidth 20:20M 40:40M 80:80M*/
+    t_u8 bandwidth;
+    /* channel number */
+    t_u8 channel;
+    /* Non-global operating class */
+    t_u8 oper_class;
+} mlan_ds_bw_chan_oper;
+#endif
+
+/** mlan_uap_acs_scan */
+typedef struct _mlan_uap_acs_scan
+{
+    /** band */
+    Band_Config_t bandcfg;
+    /** channel */
+    t_u8 chan;
+} mlan_uap_acs_scan;
+
+/** station is authorized (802.1X) */
+#define STA_FLAG_AUTHORIZED MBIT(1)
+/** Station is capable of receiving frames with short barker preamble */
+#define STA_FLAG_SHORT_PREAMBLE MBIT(2)
+/** station is WME/QoS capable */
+#define STA_FLAG_WME MBIT(3)
+/** station uses management frame protection */
+#define STA_FLAG_MFP MBIT(4)
+/** station is authenticated */
+#define STA_FLAG_AUTHENTICATED MBIT(5)
+/** station is a TDLS peer */
+#define STA_FLAG_TDLS_PEER MBIT(6)
+/** station is associated */
+#define STA_FLAG_ASSOCIATED MBIT(7)
+/** mlan_ds_sta_info */
+typedef struct _mlan_ds_sta_info
+{
+    /** aid */
+    t_u16 aid;
+    /** peer_mac */
+    t_u8 peer_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Listen Interval */
+    int listen_interval;
+    /** Capability Info */
+    t_u16 cap_info;
+    /** station flag */
+    t_u32 sta_flags;
+    /** tlv len */
+    t_u16 tlv_len;
+    /** tlv start */
+    t_u8 tlv[];
+} mlan_ds_sta_info;
+
+/** Type definition of mlan_embedded_dhcp_config */
+typedef MLAN_PACK_START struct _mlan_embedded_dhcp_config
+{
+    /** Host IP address */
+    t_u32 host_ip_addr;
+    /** Start IP address */
+    t_u32 start_ip_addr;
+    /** Sub mask */
+    t_u32 subnet_mask;
+    /** Lease time */
+    t_u32 lease_time;
+    /** Limit count */
+    t_u8 limit_count;
+    /** Enabled/disbaled */
+    t_u8 is_enabled;
+    /** Get / Set action*/
+    t_u16 action;
+} MLAN_PACK_END mlan_embedded_dhcp_config, *pmlan_embedded_dhcp_config;
+
+/** Type definition of mlan_ds_bss for MLAN_IOCTL_BSS */
+typedef struct _mlan_ds_bss
+{
+    /** Sub-command */
+    mlan_ioctl_req_id sub_command;
+    /** BSS parameter */
+    union
+    {
+        /** SSID-BSSID for MLAN_OID_BSS_START */
+        mlan_ssid_bssid ssid_bssid;
+#if 0
+        /** BSSID for MLAN_OID_BSS_STOP */
+        mlan_802_11_mac_addr bssid;
+        /** BSS mode for MLAN_OID_BSS_MODE */
+        t_u32 bss_mode;
+        /** BSS channel/frequency for MLAN_OID_BSS_CHANNEL */
+        chan_freq bss_chan;
+        /** BSS channel list for MLAN_OID_BSS_CHANNEL_LIST */
+        mlan_chan_list chanlist;
+        /** MAC address for MLAN_OID_BSS_MAC_ADDR */
+        mlan_802_11_mac_addr mac_addr;
+        /** Multicast list for MLAN_OID_BSS_MULTICAST_LIST */
+        mlan_multicast_list multicast_list;
+        /** Beacon interval for MLAN_OID_IBSS_BCN_INTERVAL */
+        t_u32 bcn_interval;
+        /** ATIM window for MLAN_OID_IBSS_ATIM_WINDOW */
+        t_u32 atim_window;
+#endif
+        /** BSS param for AP mode */
+        mlan_uap_bss_param bss_config;
+#if CONFIG_ECSA
+        /** channel switch for MLAN_OID_UAP_CHAN_SWITCH */
+        mlan_action_chan_switch chanswitch;
+#endif
+#if 0
+        /** deauth param for MLAN_OID_UAP_DEAUTH_STA */
+        mlan_deauth_param deauth_param;
+#endif
+        /** BSS role */
+        mlan_bss_role bss_role;
+        /** AP acs scan MLAN_OID_UAP_ACS_SCAN */
+        mlan_uap_acs_scan ap_acs_scan;
+        /** host based flag for MLAN_OID_BSS_START */
+        t_u8 host_based;
+        /** STA info for MLAN_OID_UAP_ADD_STATION */
+        mlan_ds_sta_info sta_info;
+    } param;
+} mlan_ds_bss, *pmlan_ds_bss;
+
+#ifdef OTP_CHANINFO
+/* OTP Region info */
+typedef MLAN_PACK_START struct _otp_region_info
+{
+    t_u8 country_code[2];
+    t_u8 region_code;
+    t_u8 environment;
+    t_u16 force_reg : 1;
+    t_u16 reserved : 15;
+} MLAN_PACK_END otp_region_info_t;
+
+/** Type definition of mlan_ds_custom_reg_domain */
+typedef struct _mlan_ds_custom_reg_domain
+{
+    otp_region_info_t region;
+    /** num of 2g channels in custom_reg_domain */
+    t_u8 num_bg_chan;
+#if CONFIG_5GHz_SUPPORT
+    /** num of 5g channels in custom_reg_domain */
+    t_u8 num_a_chan;
+#endif
+    /** cfp table */
+    chan_freq_power_t cfp_tbl[0];
+} mlan_ds_custom_reg_domain;
+#endif
+
+/*-----------------------------------------------------------------*/
+/** Radio Control Group */
+/*-----------------------------------------------------------------*/
+/** Enumeration for band */
+#define BAND_B   1U
+#define BAND_G   2U
+#define BAND_A   4U
+#define BAND_GN  8U
+#define BAND_AN  16U
+#define BAND_GAC 32U
+#define BAND_AAC 64U
+#if CONFIG_11AX
+#define BAND_GAX 256U
+#define BAND_AAX 512U
+#endif
+
+/** band AUTO */
+#define WIFI_FREQUENCY_BAND_AUTO 0
+/** band 5G */
+#define WIFI_FREQUENCY_BAND_5GHZ 1
+/** band 2G */
+#define WIFI_FREQUENCY_BAND_2GHZ 2
+/** All band */
+#define WIFI_FREQUENCY_ALL_BAND 3
+
+/** NO secondary channel */
+#define NO_SEC_CHANNEL 0
+/** secondary channel is above primary channel */
+#define SEC_CHANNEL_ABOVE 1
+/** secondary channel is below primary channel */
+#define SEC_CHANNEL_BELOW 3
+/** secondary channel is 80Mhz bandwidth for 11ac */
+#define CHANNEL_BW_80MHZ  4
+#define CHANNEL_BW_160MHZ 5
+/** Channel bandwidth */
+#define CHANNEL_BW_20MHZ       0
+#define CHANNEL_BW_40MHZ_ABOVE 1
+#define CHANNEL_BW_40MHZ_BELOW 3
+
+/** Type definition of mlan_ds_band_cfg for MLAN_OID_BAND_CFG */
+typedef struct _mlan_ds_band_cfg
+{
+    /** Infra band */
+    t_u16 config_bands;
+    /** Ad-hoc start band */
+    t_u16 adhoc_start_band;
+    /** Ad-hoc start channel */
+    t_u32 adhoc_channel;
+    /** Ad-hoc channel bandwidth */
+    t_u32 sec_chan_offset;
+    /** fw supported band */
+    t_u16 fw_bands;
+} mlan_ds_band_cfg;
+
+/** Type definition of mlan_ds_remain_chan for MLAN_OID_REMAIN_CHAN_CFG */
+typedef struct _mlan_ds_remain_chan
+{
+    /** remove flag */
+    t_u16 remove;
+    /** status */
+    t_u8 status;
+    /** Band cfg */
+    t_u8 bandcfg;
+    /** channel */
+    t_u8 channel;
+    /** remain time: Unit ms*/
+    t_u32 remain_period;
+} mlan_ds_remain_chan, *pmlan_ds_remain_chan;
+
+/** Type definition of mlan_ds_radio_cfg for MLAN_IOCTL_RADIO_CFG */
+typedef struct _mlan_ds_radio_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Radio control parameter */
+    union
+    {
+        /** Radio on/off for MLAN_OID_RADIO_CTRL */
+        t_u32 radio_on_off;
+        /** Band info for MLAN_OID_BAND_CFG */
+        mlan_ds_band_cfg band_cfg;
+        /** Antenna info for MLAN_OID_ANT_CFG */
+        t_u32 antenna;
+    } param;
+} mlan_ds_radio_cfg, *pmlan_ds_radio_cfg;
+
+/** Type definition of mlan_ds_ant_cfg_1x1 for MLAN_OID_ANT_CFG */
+typedef struct _mlan_ds_ant_cfg_1x1
+{
+    /** Antenna mode */
+    t_u32 antenna;
+    /** Evaluate time */
+    t_u16 evaluate_time;
+    /** Current antenna */
+    t_u16 current_antenna;
+#ifdef RW610
+    /** Evaluate time */
+    t_u8 evaluate_mode;
+#endif
+} mlan_ds_ant_cfg_1x1, *pmlan_ds_ant_cfg_1x1;
+
+
+/*-----------------------------------------------------------------*/
+/** SNMP MIB Group */
+/*-----------------------------------------------------------------*/
+/** Type definition of mlan_ds_snmp_mib for MLAN_IOCTL_SNMP_MIB */
+typedef struct _mlan_ds_snmp_mib
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** SNMP MIB parameter */
+    union
+    {
+        /** RTS threshold for MLAN_OID_SNMP_MIB_RTS_THRESHOLD */
+        t_u32 rts_threshold;
+        /** Fragment threshold for MLAN_OID_SNMP_MIB_FRAG_THRESHOLD */
+        t_u32 frag_threshold;
+        /** Retry count for MLAN_OID_SNMP_MIB_RETRY_COUNT */
+        t_u32 retry_count;
+        /** OID value for MLAN_OID_SNMP_MIB_DOT11D/H */
+        t_u32 oid_value;
+        /** DTIM period for MLAN_OID_SNMP_MIB_DTIM_PERIOD */
+        t_u32 dtim_period;
+        /** Control deauth when uap switch channel */
+        t_u8 deauthctrl;
+    } param;
+} mlan_ds_snmp_mib, *pmlan_ds_snmp_mib;
+
+/*-----------------------------------------------------------------*/
+/** Status Information Group */
+/*-----------------------------------------------------------------*/
+/** Enumeration for ad-hoc status */
+enum _mlan_adhoc_status
+{
+    ADHOC_IDLE,
+    ADHOC_STARTED,
+    ADHOC_JOINED,
+    ADHOC_COALESCED,
+    ADHOC_STARTING
+};
+
+/** Type definition of mlan_ds_get_stats for MLAN_OID_GET_STATS */
+typedef struct _mlan_ds_get_stats
+{
+    /** Statistics counter */
+    /** Multicast transmitted frame count */
+    t_u32 mcast_tx_frame;
+    /** Failure count */
+    t_u32 failed;
+    /** Retry count */
+    t_u32 retry;
+    /** Multi entry count */
+    t_u32 multi_retry;
+    /** Duplicate frame count */
+    t_u32 frame_dup;
+    /** RTS success count */
+    t_u32 rts_success;
+    /** RTS failure count */
+    t_u32 rts_failure;
+    /** Ack failure count */
+    t_u32 ack_failure;
+    /** Rx fragmentation count */
+    t_u32 rx_frag;
+    /** Multicast Tx frame count */
+    t_u32 mcast_rx_frame;
+    /** FCS error count */
+    t_u32 fcs_error;
+    /** Tx frame count */
+    t_u32 tx_frame;
+    /** WEP ICV error count */
+    t_u32 wep_icv_error[4];
+} mlan_ds_get_stats, *pmlan_ds_get_stats;
+
+/** Type definition of mlan_ds_uap_stats for MLAN_OID_GET_STATS */
+typedef struct _mlan_ds_uap_stats
+{
+    /** tkip mic failures */
+    t_u32 tkip_mic_failures;
+    /** ccmp decrypt errors */
+    t_u32 ccmp_decrypt_errors;
+    /** wep undecryptable count */
+    t_u32 wep_undecryptable_count;
+    /** wep icv error count */
+    t_u32 wep_icv_error_count;
+    /** decrypt failure count */
+    t_u32 decrypt_failure_count;
+    /** dot11 multicast tx count */
+    t_u32 mcast_tx_count;
+    /** dot11 failed count */
+    t_u32 failed_count;
+    /** dot11 retry count */
+    t_u32 retry_count;
+    /** dot11 multi retry count */
+    t_u32 multi_retry_count;
+    /** dot11 frame duplicate count */
+    t_u32 frame_dup_count;
+    /** dot11 rts success count */
+    t_u32 rts_success_count;
+    /** dot11 rts failure count */
+    t_u32 rts_failure_count;
+    /** dot11 ack failure count */
+    t_u32 ack_failure_count;
+    /** dot11 rx ragment count */
+    t_u32 rx_fragment_count;
+    /** dot11 mcast rx frame count */
+    t_u32 mcast_rx_frame_count;
+    /** dot11 fcs error count */
+    t_u32 fcs_error_count;
+    /** dot11 tx frame count */
+    t_u32 tx_frame_count;
+    /** dot11 rsna tkip cm invoked */
+    t_u32 rsna_tkip_cm_invoked;
+    /** dot11 rsna 4way handshake failures */
+    t_u32 rsna_4way_hshk_failures;
+} mlan_ds_uap_stats, *pmlan_ds_uap_stats;
+
+/** Mask of last beacon RSSI */
+#define BCN_RSSI_LAST_MASK 0x00000001
+/** Mask of average beacon RSSI */
+#define BCN_RSSI_AVG_MASK 0x00000002
+/** Mask of last data RSSI */
+#define DATA_RSSI_LAST_MASK 0x00000004
+/** Mask of average data RSSI */
+#define DATA_RSSI_AVG_MASK 0x00000008
+/** Mask of last beacon SNR */
+#define BCN_SNR_LAST_MASK 0x00000010
+/** Mask of average beacon SNR */
+#define BCN_SNR_AVG_MASK 0x00000020
+/** Mask of last data SNR */
+#define DATA_SNR_LAST_MASK 0x00000040
+/** Mask of average data SNR */
+#define DATA_SNR_AVG_MASK 0x00000080
+/** Mask of last beacon NF */
+#define BCN_NF_LAST_MASK 0x00000100
+/** Mask of average beacon NF */
+#define BCN_NF_AVG_MASK 0x00000200
+/** Mask of last data NF */
+#define DATA_NF_LAST_MASK 0x00000400
+/** Mask of average data NF */
+#define DATA_NF_AVG_MASK 0x00000800
+/** Mask of all RSSI_INFO */
+#define ALL_RSSI_INFO_MASK 0x00000fff
+
+/** Type definition of mlan_ds_get_signal for MLAN_OID_GET_SIGNAL */
+typedef struct _mlan_ds_get_signal
+{
+    /** Selector of get operation */
+    /*
+     * Bit0:  Last Beacon RSSI,  Bit1:  Average Beacon RSSI,
+     * Bit2:  Last Data RSSI,    Bit3:  Average Data RSSI,
+     * Bit4:  Last Beacon SNR,   Bit5:  Average Beacon SNR,
+     * Bit6:  Last Data SNR,     Bit7:  Average Data SNR,
+     * Bit8:  Last Beacon NF,    Bit9:  Average Beacon NF,
+     * Bit10: Last Data NF,      Bit11: Average Data NF
+     */
+    t_u16 selector;
+
+    /** RSSI */
+    /** RSSI of last beacon */
+    t_s16 bcn_rssi_last;
+    /** RSSI of beacon average */
+    t_s16 bcn_rssi_avg;
+    /** RSSI of last data packet */
+    t_s16 data_rssi_last;
+    /** RSSI of data packet average */
+    t_s16 data_rssi_avg;
+
+    /** SNR */
+    /** SNR of last beacon */
+    t_s16 bcn_snr_last;
+    /** SNR of beacon average */
+    t_s16 bcn_snr_avg;
+    /** SNR of last data packet */
+    t_s16 data_snr_last;
+    /** SNR of data packet average */
+    t_s16 data_snr_avg;
+
+    /** NF */
+    /** NF of last beacon */
+    t_s16 bcn_nf_last;
+    /** NF of beacon average */
+    t_s16 bcn_nf_avg;
+    /** NF of last data packet */
+    t_s16 data_nf_last;
+    /** NF of data packet average */
+    t_s16 data_nf_avg;
+} mlan_ds_get_signal, *pmlan_ds_get_signal;
+
+
+/** mlan_fw_info data structure for MLAN_OID_GET_FW_INFO */
+typedef struct _mlan_fw_info
+{
+    /** Firmware version */
+    t_u32 fw_ver;
+    /** MAC address */
+    mlan_802_11_mac_addr mac_addr;
+    /** Device support for MIMO abstraction of MCSs */
+    t_u8 hw_dev_mcs_support;
+    /** fw supported band */
+    t_u16 fw_bands;
+#if CONFIG_11AX
+    /** length of hw he capability */
+    t_u8 hw_hecap_len;
+    /** 802.11ax HE capability */
+    t_u8 hw_he_cap[54];
+    /** length of hw 2.4G he capability */
+    t_u8 hw_2g_hecap_len;
+    /** 802.11ax 2.4G HE capability */
+    t_u8 hw_2g_he_cap[54];
+#ifdef ENABLE_802_116E
+    /** 802.11ax 6G HE capability */
+    t_u16 hw_he_6g_cap;
+#endif
+#endif
+} mlan_fw_info, *pmlan_fw_info;
+
+/** Version string buffer length */
+#define MLAN_MAX_VER_STR_LEN 128
+
+/** mlan_ver_ext data structure for MLAN_OID_GET_VER_EXT */
+typedef struct _mlan_ver_ext
+{
+    /** Selected version string */
+    t_u32 version_str_sel;
+    /** Version string */
+    char version_str[MLAN_MAX_VER_STR_LEN];
+} mlan_ver_ext, *pmlan_ver_ext;
+
+/** mlan_bss_info data structure for MLAN_OID_GET_BSS_INFO */
+typedef struct _mlan_bss_info
+{
+    /** BSS mode */
+    mlan_bss_mode bss_mode;
+    /** SSID */
+    mlan_802_11_ssid ssid;
+    /** Table index */
+    t_u32 scan_table_idx;
+    /** Channel */
+    t_u32 bss_chan;
+    /** Band */
+    t_u8 bss_band;
+    /** Region code */
+    t_u32 region_code;
+    /** Connection status */
+    t_u32 media_connected;
+    /** Radio on */
+    t_u32 radio_on;
+    /** Max power level in dBm */
+    t_u32 max_power_level;
+    /** Min power level in dBm */
+    t_u32 min_power_level;
+    /** Adhoc state */
+    t_u32 adhoc_state;
+    /** NF of last beacon */
+    t_s32 bcn_nf_last;
+    /** wep status */
+    t_u32 wep_status;
+    /** Host Sleep configured flag */
+    t_u32 is_hs_configured;
+    /** Deep Sleep flag */
+    t_u32 is_deep_sleep;
+    /** BSSID */
+    mlan_802_11_mac_addr bssid;
+    /** Capability Info */
+    t_u16 capability_info;
+    /** Beacon Interval */
+    t_u16 beacon_interval;
+    /** Listen Interval */
+    t_u16 listen_interval;
+    /** Association Id  */
+    t_u16 assoc_id;
+    /** AP/Peer supported rates */
+    t_u8 peer_supp_rates[MLAN_SUPPORTED_RATES];
+} mlan_bss_info, *pmlan_bss_info;
+
+/** MAXIMUM number of TID */
+#define MAX_NUM_TID 8U
+
+/** Max RX Win size */
+#define MAX_RX_WINSIZE 64
+
+/** rx_reorder_tbl */
+typedef struct
+{
+    /** TID */
+    t_u16 tid;
+    /** TA */
+    t_u8 ta[MLAN_MAC_ADDR_LENGTH];
+    /** Start window */
+    t_u32 start_win;
+    /** Window size */
+    t_u32 win_size;
+    /** amsdu flag */
+    t_u8 amsdu;
+    /** buffer status */
+    t_u32 buffer[MAX_RX_WINSIZE];
+} rx_reorder_tbl;
+
+/** tx_ba_stream_tbl */
+typedef struct
+{
+    /** TID */
+    t_u16 tid;
+    /** RA */
+    t_u8 ra[MLAN_MAC_ADDR_LENGTH];
+    /** amsdu flag */
+    t_u8 amsdu;
+} tx_ba_stream_tbl;
+
+/** Debug command number */
+#define DBG_CMD_NUM 5
+
+/** mlan_debug_info data structure for MLAN_OID_GET_DEBUG_INFO */
+typedef struct _mlan_debug_info
+{
+    /* WMM AC_BK count */
+    t_u32 wmm_ac_bk;
+    /* WMM AC_BE count */
+    t_u32 wmm_ac_be;
+    /* WMM AC_VI count */
+    t_u32 wmm_ac_vi;
+    /* WMM AC_VO count */
+    t_u32 wmm_ac_vo;
+    /** Corresponds to max_tx_buf_size member of mlan_adapter*/
+    t_u32 max_tx_buf_size;
+    /** Corresponds to tx_buf_size member of mlan_adapter*/
+    t_u32 tx_buf_size;
+    /** Corresponds to curr_tx_buf_size member of mlan_adapter*/
+    t_u32 curr_tx_buf_size;
+    /** Tx table num */
+    t_u32 tx_tbl_num;
+    /** Tx ba stream table */
+    tx_ba_stream_tbl tx_tbl[MLAN_MAX_TX_BASTREAM_SUPPORTED];
+    /** Rx table num */
+    t_u32 rx_tbl_num;
+    /** Rx reorder table*/
+    rx_reorder_tbl rx_tbl[MLAN_MAX_RX_BASTREAM_SUPPORTED];
+    /** Corresponds to ps_mode member of mlan_adapter */
+    t_u16 ps_mode;
+    /** Corresponds to ps_state member of mlan_adapter */
+    t_u32 ps_state;
+    /** Corresponds to is_deep_sleep member of mlan_adapter */
+    t_u8 is_deep_sleep;
+    /** Corresponds to pm_wakeup_card_req member of mlan_adapter */
+    t_u8 pm_wakeup_card_req;
+    /** Corresponds to pm_wakeup_fw_try member of mlan_adapter */
+    t_u32 pm_wakeup_fw_try;
+    /** Corresponds to is_hs_configured member of mlan_adapter */
+    t_u8 is_hs_configured;
+    /** Corresponds to hs_activated member of mlan_adapter */
+    t_u8 hs_activated;
+    /** Corresponds to pps_uapsd_mode member of mlan_adapter */
+    t_u16 pps_uapsd_mode;
+    /** Corresponds to sleep_period.period member of mlan_adapter */
+    t_u16 sleep_pd;
+    /** Corresponds to wmm_qosinfo member of mlan_private */
+    t_u8 qos_cfg;
+    /** Corresponds to tx_lock_flag member of mlan_adapter */
+    t_u8 tx_lock_flag;
+    /** Corresponds to port_open member of mlan_private */
+    t_u8 port_open;
+    /** Corresponds to scan_processing member of mlan_adapter */
+    t_u32 scan_processing;
+    /** Number of host to card command failures */
+    t_u32 num_cmd_host_to_card_failure;
+    /** Number of host to card sleep confirm failures */
+    t_u32 num_cmd_sleep_cfm_host_to_card_failure;
+    /** Number of host to card Tx failures */
+    t_u32 num_tx_host_to_card_failure;
+    /** Number of card to host command/event failures */
+    t_u32 num_cmdevt_card_to_host_failure;
+    /** Number of card to host Rx failures */
+    t_u32 num_rx_card_to_host_failure;
+    /** Number of interrupt read failures */
+    t_u32 num_int_read_failure;
+    /** Last interrupt status */
+    t_u32 last_int_status;
+    /** Number of deauthentication events */
+    t_u32 num_event_deauth;
+    /** Number of disassosiation events */
+    t_u32 num_event_disassoc;
+    /** Number of link lost events */
+    t_u32 num_event_link_lost;
+    /** Number of deauthentication commands */
+    t_u32 num_cmd_deauth;
+    /** Number of association comamnd successes */
+    t_u32 num_cmd_assoc_success;
+    /** Number of association command failures */
+    t_u32 num_cmd_assoc_failure;
+    /** Number of Tx timeouts */
+    t_u32 num_tx_timeout;
+    /** Number of command timeouts */
+    t_u32 num_cmd_timeout;
+    /** Timeout command ID */
+    t_u16 timeout_cmd_id;
+    /** Timeout command action */
+    t_u16 timeout_cmd_act;
+    /** List of last command IDs */
+    t_u16 last_cmd_id[DBG_CMD_NUM];
+    /** List of last command actions */
+    t_u16 last_cmd_act[DBG_CMD_NUM];
+    /** Last command index */
+    t_u16 last_cmd_index;
+    /** List of last command response IDs */
+    t_u16 last_cmd_resp_id[DBG_CMD_NUM];
+    /** Last command response index */
+    t_u16 last_cmd_resp_index;
+    /** List of last events */
+    t_u16 last_event[DBG_CMD_NUM];
+    /** Last event index */
+    t_u16 last_event_index;
+
+    /** Corresponds to data_sent member of mlan_adapter */
+    t_u8 data_sent;
+    /** Corresponds to cmd_sent member of mlan_adapter */
+    t_u8 cmd_sent;
+    /** SDIO multiple port read bitmap */
+    t_u32 mp_rd_bitmap;
+    /** SDIO multiple port write bitmap */
+    t_u32 mp_wr_bitmap;
+    /** Current available port for read */
+    t_u8 curr_rd_port;
+    /** Current available port for write */
+    t_u8 curr_wr_port;
+    /** Corresponds to cmdresp_received member of mlan_adapter */
+    t_u8 cmd_resp_received;
+    /** Corresponds to event_received member of mlan_adapter */
+    t_u8 event_received;
+    /**  pendig tx pkts */
+    t_u32 tx_pkts_queued;
+    /**  pending bridge pkts */
+    t_u16 num_bridge_pkts;
+    /**  dropped pkts */
+    t_u32 num_drop_pkts;
+} mlan_debug_info, *pmlan_debug_info;
+
+/** Maximum number of clients supported by AP */
+#define MAX_NUM_CLIENTS 16U
+
+/** station info */
+typedef struct _sta_info
+{
+    /** STA MAC address */
+    t_u8 mac_address[MLAN_MAC_ADDR_LENGTH];
+    /** Power mfg status */
+    t_u8 power_mfg_status;
+    /** RSSI */
+    t_s8 rssi;
+} sta_info;
+
+/** mlan_ds_sta_list structure for MLAN_OID_UAP_STA_LIST */
+typedef struct _mlan_ds_sta_list
+{
+    /** station count */
+    t_u16 sta_count;
+    /** station list */
+    sta_info info[MAX_NUM_CLIENTS];
+} mlan_ds_sta_list, *pmlan_ds_sta_list;
+
+/** Type definition of mlan_ds_get_info for MLAN_IOCTL_GET_INFO */
+typedef struct _mlan_ds_get_info
+{
+    /** Sub-command */
+    t_u32 sub_command;
+
+    /** Status information parameter */
+    union
+    {
+        /** Signal information for MLAN_OID_GET_SIGNAL */
+        mlan_ds_get_signal signal;
+        /** Statistics information for MLAN_OID_GET_STATS */
+        mlan_ds_get_stats stats;
+        /** Firmware information for MLAN_OID_GET_FW_INFO */
+        mlan_fw_info fw_info;
+        /** Extended version information for MLAN_OID_GET_VER_EXT */
+        mlan_ver_ext ver_ext;
+        /** BSS information for MLAN_OID_GET_BSS_INFO */
+        mlan_bss_info bss_info;
+        /** Debug information for MLAN_OID_GET_DEBUG_INFO */
+        mlan_debug_info debug_info;
+        /** UAP Statistics information for MLAN_OID_GET_STATS */
+        mlan_ds_uap_stats ustats;
+        /** UAP station list for MLAN_OID_UAP_STA_LIST */
+        mlan_ds_sta_list sta_list;
+    } param;
+} mlan_ds_get_info, *pmlan_ds_get_info;
+
+/*-----------------------------------------------------------------*/
+/** Security Configuration Group */
+/*-----------------------------------------------------------------*/
+/** Enumeration for authentication mode */
+typedef enum _mlan_auth_mode
+{
+    MLAN_AUTH_MODE_OPEN   = 0x00,
+    MLAN_AUTH_MODE_SHARED = 0x01,
+    MLAN_AUTH_MODE_FT     = 0x02,
+    MLAN_AUTH_MODE_SAE    = 0x03,
+#if CONFIG_DRIVER_OWE
+    MLAN_AUTH_MODE_OWE = 0x04,
+#endif
+    MLAN_AUTH_MODE_NETWORKEAP = 0x80,
+    MLAN_AUTH_MODE_AUTO       = 0xFF,
+} mlan_auth_mode;
+
+/**Enumeration for AssocAgent authentication mode, sync from FW.*/
+typedef enum
+{
+    AssocAgentAuth_Open,
+    AssocAgentAuth_Shared,
+    AssocAgentAuth_FastBss,
+    AssocAgentAuth_FastBss_Skip,
+    AssocAgentAuth_FastBss_SAE,
+    AssocAgentAuth_Wpa3Sae = 6,
+#if CONFIG_DRIVER_OWE
+    AssocAgentAuth_Owe = 7,
+#endif
+    AssocAgentAuth_Auto,
+} AssocAgentAuthType_e;
+
+/** Enumeration for encryption mode */
+typedef enum _mlan_encryption_mode
+{
+    MLAN_ENCRYPTION_MODE_NONE   = 0,
+    MLAN_ENCRYPTION_MODE_WEP40  = 1,
+    MLAN_ENCRYPTION_MODE_TKIP   = 2,
+    MLAN_ENCRYPTION_MODE_CCMP   = 3,
+    MLAN_ENCRYPTION_MODE_WEP104 = 4,
+} mlan_encryption_mode;
+
+/** Enumeration for PSK */
+typedef enum _mlan_psk_type
+{
+    MLAN_PSK_PASSPHRASE = 1,
+    MLAN_PSK_PMK,
+    MLAN_PSK_CLEAR,
+    MLAN_PSK_QUERY,
+    MLAN_PSK_PASSWORD,
+} mlan_psk_type;
+
+/** The bit to indicate the key is for unicast */
+#define MLAN_KEY_INDEX_UNICAST 0x40000000
+/** The key index to indicate default key */
+#define MLAN_KEY_INDEX_DEFAULT 0x000000ffU
+/** Maximum key length */
+// #define MLAN_MAX_KEY_LENGTH        32
+/** Minimum passphrase length */
+#define MLAN_MIN_PASSPHRASE_LENGTH 8U
+/** Maximum passphrase length */
+/** FIXME: This macro is used for both passphrase and PSK length
+ * As per standards maximum passphrase length is 63 and
+ * maximum PSK length is 64.
+ *
+ * For now setting it to 64 to avoid 4 way Handshake timeout issue
+ * if connection attempt is with PSK.
+ */
+#define MLAN_MAX_PASSPHRASE_LENGTH 64U
+/** PMK length */
+#define MLAN_PMK_HEXSTR_LENGTH 64
+/* A few details needed for WEP (Wireless Equivalent Privacy) */
+/** Minimum password length */
+#define MLAN_MIN_PASSWORD_LENGTH 1U
+/** Maximum passphrase length */
+#define MLAN_MAX_PASSWORD_LENGTH 255U
+/** 104 bits */
+#define MAX_WEP_KEY_SIZE 13U
+/** 40 bits RC4 - WEP */
+#define MIN_WEP_KEY_SIZE 5
+/** packet number size */
+#define PN_SIZE 16
+/** max seq size of wpa/wpa2 key */
+#define SEQ_MAX_SIZE 8
+
+/** key flag for tx_seq */
+#define KEY_FLAG_TX_SEQ_VALID 0x00000001
+/** key flag for rx_seq */
+#define KEY_FLAG_RX_SEQ_VALID 0x00000002
+/** key flag for group key */
+#define KEY_FLAG_GROUP_KEY 0x00000004U
+/** key flag for tx and rx */
+#define KEY_FLAG_SET_TX_KEY 0x00000008U
+/** key flag for mcast IGTK */
+#define KEY_FLAG_AES_MCAST_IGTK 0x00000010U
+#ifdef MAC80211_SUPPORT_MESH
+/** key flag for mesh group Rx key */
+#define KEY_FLAG_SET_GRP_TX_KEY 0x00000100
+#endif
+/** key flag for remove key */
+#define KEY_FLAG_REMOVE_KEY 0x80000000
+/** key flag for GCMP */
+#define KEY_FLAG_GCMP 0x00000020
+/** key flag for GCMP_256 */
+#define KEY_FLAG_GCMP_256 0x00000040
+/** key flag for ccmp 256 */
+#define KEY_FLAG_CCMP_256 0x00000080
+/** key flag for GMAC_128 */
+#define KEY_FLAG_GMAC_128 0x00000100
+/** key flag for GMAC_256 */
+#define KEY_FLAG_GMAC_256 0x00000200
+
+/* Clear all key indexes */
+#define KEY_INDEX_CLEAR_ALL 0x0000000F
+
+/** Type definition of mlan_ds_encrypt_key for MLAN_OID_SEC_CFG_ENCRYPT_KEY */
+typedef struct _mlan_ds_encrypt_key
+{
+    /** Key disabled, all other fields will be ignore when this flag set to MTRUE */
+    t_u32 key_disable;
+    /** key removed flag, when this flag is set to MTRUE, only key_index will be check */
+    t_u32 key_remove;
+    /** Key index, used as current tx key index when is_current_wep_key is set to MTRUE */
+    t_u32 key_index;
+    /** Current Tx key flag */
+    bool is_current_wep_key;
+    /** Key length */
+    t_u32 key_len;
+    /** Key */
+    t_u8 key_material[MLAN_MAX_KEY_LENGTH];
+    /** mac address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** wapi key flag */
+    t_u32 is_wapi_key;
+    /** Initial packet number */
+    t_u8 pn[PN_SIZE];
+    /** key flags */
+    t_u32 key_flags;
+} mlan_ds_encrypt_key, *pmlan_ds_encrypt_key;
+
+/** Type definition of mlan_passphrase_t */
+typedef struct _mlan_passphrase_t
+{
+    /** Length of passphrase */
+    t_u32 passphrase_len;
+    /** Passphrase */
+    t_u8 passphrase[MLAN_MAX_PASSPHRASE_LENGTH];
+} mlan_passphrase_t;
+
+/** Type defnition of mlan_pmk_t */
+typedef struct _mlan_pmk_t
+{
+    /** PMK */
+    t_u8 pmk[MLAN_MAX_KEY_LENGTH];
+} mlan_pmk_t;
+
+/** Type definition of mlan_passphrase_t */
+typedef struct _mlan_password_t
+{
+    /** Length of passphrase */
+    t_u32 password_len;
+    /** Passphrase */
+    t_u8 password[MLAN_MAX_PASSWORD_LENGTH];
+} mlan_password_t;
+
+/** Embedded supplicant RSN type: No RSN */
+#define RSN_TYPE_NO_RSN MBIT(0)
+/** Embedded supplicant RSN type: WPA */
+#define RSN_TYPE_WPA MBIT(3)
+/** Embedded supplicant RSN type: WPA-NONE */
+#define RSN_TYPE_WPANONE MBIT(4)
+/** Embedded supplicant RSN type: WPA2 */
+#define RSN_TYPE_WPA2 MBIT(5)
+/** Embedded supplicant RSN type: RFU */
+#define RSN_TYPE_VALID_BITS (RSN_TYPE_NO_RSN | RSN_TYPE_WPA | RSN_TYPE_WPANONE | RSN_TYPE_WPA2)
+
+/** Embedded supplicant cipher type: TKIP */
+#define EMBED_CIPHER_TKIP MBIT(2)
+/** Embedded supplicant cipher type: AES */
+#define EMBED_CIPHER_AES MBIT(3)
+/** Embedded supplicant cipher type: RFU */
+#define EMBED_CIPHER_VALID_BITS (EMBED_CIPHER_TKIP | EMBED_CIPHER_AES)
+
+/** Type definition of mlan_ds_passphrase for MLAN_OID_SEC_CFG_PASSPHRASE */
+typedef struct _mlan_ds_passphrase
+{
+    /** SSID may be used */
+    mlan_802_11_ssid ssid;
+    /** BSSID may be used */
+    mlan_802_11_mac_addr bssid;
+    /** Flag for passphrase or pmk used */
+    mlan_psk_type psk_type;
+    /** Passphrase or PMK */
+    union
+    {
+        /** Passphrase */
+        mlan_passphrase_t passphrase;
+        /** PMK */
+        mlan_pmk_t pmk;
+    } psk;
+    /** Password */
+    mlan_password_t password;
+} mlan_ds_passphrase, *pmlan_ds_passphrase;
+
+/** Type definition of mlan_ds_esupp_mode for MLAN_OID_SEC_CFG_ESUPP_MODE */
+typedef struct _mlan_ds_ewpa_mode
+{
+    /** RSN mode */
+    t_u32 rsn_mode;
+    /** Active pairwise cipher */
+    t_u32 act_paircipher;
+    /** Active pairwise cipher */
+    t_u32 act_groupcipher;
+} mlan_ds_esupp_mode, *pmlan_ds_esupp_mode;
+
+/** Type definition of mlan_ds_sec_cfg for MLAN_IOCTL_SEC_CFG */
+typedef struct _mlan_ds_sec_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Security configuration parameter */
+    union
+    {
+        /** Authentication mode for MLAN_OID_SEC_CFG_AUTH_MODE */
+        t_u32 auth_mode;
+        /** Encryption mode for MLAN_OID_SEC_CFG_ENCRYPT_MODE */
+        t_u32 encrypt_mode;
+        /** WPA enabled flag for MLAN_OID_SEC_CFG_WPA_ENABLED */
+        t_u32 wpa_enabled;
+        /** WAPI enabled flag for MLAN_OID_SEC_CFG_WAPI_ENABLED */
+        t_u32 wapi_enabled;
+        /** Port Control enabled flag for MLAN_OID_SEC_CFG_PORT_CTRL */
+        t_u32 port_ctrl_enabled;
+        /** Encryption key for MLAN_OID_SEC_CFG_ENCRYPT_KEY */
+        mlan_ds_encrypt_key encrypt_key;
+        /** Passphrase for MLAN_OID_SEC_CFG_PASSPHRASE */
+        mlan_ds_passphrase passphrase;
+        /** Embedded supplicant WPA enabled flag for MLAN_OID_SEC_CFG_EWPA_ENABLED */
+        t_u32 ewpa_enabled;
+        /** Embedded supplicant mode for MLAN_OID_SEC_CFG_ESUPP_MODE */
+        mlan_ds_esupp_mode esupp_mode;
+    } param;
+} mlan_ds_sec_cfg, *pmlan_ds_sec_cfg;
+
+/*-----------------------------------------------------------------*/
+/** Rate Configuration Group */
+/*-----------------------------------------------------------------*/
+/** Enumeration for rate type */
+enum _mlan_rate_type
+{
+    MLAN_RATE_INDEX,
+    MLAN_RATE_VALUE,
+    MLAN_RATE_BITMAP
+};
+
+/** Enumeration for rate format */
+typedef enum _mlan_rate_format
+{
+    MLAN_RATE_FORMAT_LG = 0,
+    MLAN_RATE_FORMAT_HT,
+#if CONFIG_11AC
+    MLAN_RATE_FORMAT_VHT,
+#endif
+#if CONFIG_11AX
+    MLAN_RATE_FORMAT_HE,
+#endif
+    MLAN_RATE_FORMAT_AUTO = 0xFF,
+} mlan_rate_format;
+
+#if CONFIG_11AX
+#define MAX_BITMAP_RATES_SIZE 26
+#else
+/** Max bitmap rates size */
+#define MAX_BITMAP_RATES_SIZE 18
+#endif
+
+/** Type definition of mlan_rate_cfg_t for MLAN_OID_RATE_CFG */
+typedef struct _mlan_rate_cfg_t
+{
+    /** Fixed rate: 0, auto rate: 1 */
+    bool is_rate_auto;
+    /** Rate type. 0: index; 1: value; 2: bitmap */
+    t_u32 rate_type;
+    /** Rate/MCS index or rate value if fixed rate */
+    t_u32 rate;
+    /** Rate Bitmap */
+    t_u16 bitmap_rates[MAX_BITMAP_RATES_SIZE];
+#if (CONFIG_11AC) || (CONFIG_11AX)
+    /** NSS */
+    t_u32 nss;
+#endif
+    /* LG rate: 0, HT rate: 1, VHT rate: 2 */
+    mlan_rate_format rate_format;
+    /** Rate Setting */
+    t_u16 rate_setting;
+} mlan_rate_cfg_t;
+
+/** HT channel bandwidth */
+typedef enum _mlan_ht_bw
+{
+    MLAN_HT_BW20,
+    MLAN_HT_BW40,
+#if CONFIG_11AC
+    MLAN_VHT_BW80,
+    MLAN_VHT_BW160,
+#endif
+} mlan_ht_bw;
+
+/** HT guard interval */
+typedef enum _mlan_ht_gi
+{
+    MLAN_HT_LGI,
+    MLAN_HT_SGI,
+} mlan_ht_gi;
+
+#if CONFIG_11AC
+typedef enum _mlan_vht_stbc
+{
+    MLAN_VHT_STBC,
+    MLAN_VHT_NO_STBC,
+} mlan_vht_stbc;
+
+typedef enum _mlan_vht_ldpc
+{
+    MLAN_VHT_LDPC,
+    MLAN_VHT_NO_LDPC,
+} mlan_vht_ldpc;
+#endif
+
+/** Band and BSS mode */
+typedef struct _mlan_band_data_rate
+{
+    /** Band configuration */
+    t_u16 config_bands;
+    /** BSS mode (Infra or IBSS) */
+    mlan_bss_mode bss_mode;
+} mlan_band_data_rate;
+
+/** Type definition of mlan_data_rate for MLAN_OID_GET_DATA_RATE */
+typedef struct _mlan_data_rate
+{
+    /** Tx data rate */
+    t_u32 tx_data_rate;
+    /** Rx data rate */
+    t_u32 rx_data_rate;
+
+    /** Tx channel bandwidth */
+    t_u32 tx_ht_bw;
+    /** Tx guard interval */
+    t_u32 tx_ht_gi;
+    /** Rx channel bandwidth */
+    t_u32 rx_ht_bw;
+    /** Rx guard interval */
+    t_u32 rx_ht_gi;
+
+#ifndef SD8801
+    /** MCS index */
+    t_u32 tx_mcs_index;
+    t_u32 rx_mcs_index;
+
+#if (CONFIG_11AC) || (CONFIG_11AX)
+    /** NSS */
+    t_u32 tx_nss;
+    t_u32 rx_nss;
+#endif
+
+    /* LG rate: 0, HT rate: 1, VHT rate: 2 */
+    mlan_rate_format tx_rate_format;
+    mlan_rate_format rx_rate_format;
+#endif
+} mlan_data_rate;
+
+/** Type definition of mlan_ds_rate for MLAN_IOCTL_RATE */
+typedef struct _mlan_ds_rate
+{
+    /** Sub-command */
+    mlan_ioctl_req_id sub_command;
+#if CONFIG_AUTO_NULL_TX
+    /** Only set auto tx fix rate */
+    t_u16 auto_null_fixrate_enable;
+#endif
+    /** Rate configuration parameter */
+    union
+    {
+        /** Rate configuration for MLAN_OID_RATE_CFG */
+        mlan_rate_cfg_t rate_cfg;
+        /** Data rate for MLAN_OID_GET_DATA_RATE */
+        mlan_data_rate data_rate;
+        /** Supported rates for MLAN_OID_SUPPORTED_RATES */
+        t_u8 rates[MLAN_SUPPORTED_RATES];
+        /** Band/BSS mode for getting supported rates */
+        mlan_band_data_rate rate_band_cfg;
+    } param;
+} mlan_ds_rate, *pmlan_ds_rate;
+
+/*-----------------------------------------------------------------*/
+/** Power Configuration Group */
+/*-----------------------------------------------------------------*/
+
+/** Type definition of mlan_power_cfg_t for MLAN_OID_POWER_CFG */
+typedef struct _mlan_power_cfg_t
+{
+    /** Is power auto */
+    bool is_power_auto;
+    /** Power level in dBm */
+    t_u32 power_level;
+} mlan_power_cfg_t;
+
+/** max power table size */
+#define MAX_POWER_TABLE_SIZE 128
+
+/** The HT BW40 bit in Tx rate index */
+#define TX_RATE_HT_BW40_BIT MBIT(7)
+
+/** Type definition of mlan_power_cfg_ext for MLAN_OID_POWER_CFG_EXT */
+typedef struct _mlan_power_cfg_ext
+{
+    /** Length of power_data */
+    t_u32 len;
+    /** Buffer of power configuration data */
+    t_u32 power_data[MAX_POWER_TABLE_SIZE];
+} mlan_power_cfg_ext;
+
+/** Type definition of mlan_ds_power_cfg for MLAN_IOCTL_POWER_CFG */
+typedef struct _mlan_ds_power_cfg
+{
+    /** Sub-command */
+    mlan_ioctl_req_id sub_command;
+    /** Power configuration parameter */
+    union
+    {
+        /** Power configuration for MLAN_OID_POWER_CFG */
+        mlan_power_cfg_t power_cfg;
+        /** Extended power configuration for MLAN_OID_POWER_CFG_EXT */
+        mlan_power_cfg_ext power_ext;
+    } param;
+} mlan_ds_power_cfg, *pmlan_ds_power_cfg;
+
+/*-----------------------------------------------------------------*/
+/** Power Management Configuration Group */
+/*-----------------------------------------------------------------*/
+#if CONFIG_HOST_SLEEP
+/** Host sleep config conditions : Cancel */
+#define HOST_SLEEP_CFG_CANCEL 0xffffffffU
+/** Host sleep config conditions : NULL (used for offload features) */
+#define HOST_SLEEP_NO_COND 0
+
+/** Host sleep config condition: broadcast data */
+#define HOST_SLEEP_COND_BROADCAST_DATA MBIT(0)
+/** Host sleep config condition: unicast data */
+#define HOST_SLEEP_COND_UNICAST_DATA MBIT(1)
+/** Host sleep config condition: mac event */
+#define HOST_SLEEP_COND_MAC_EVENT MBIT(2)
+/** Host sleep config condition: multicast data */
+#define HOST_SLEEP_COND_MULTICAST_DATA MBIT(3)
+
+/** Host sleep config conditions: Default */
+#define HOST_SLEEP_DEF_COND (HOST_SLEEP_COND_BROADCAST_DATA | HOST_SLEEP_COND_UNICAST_DATA | HOST_SLEEP_COND_MAC_EVENT)
+/** Host sleep config GPIO : Default */
+#define HOST_SLEEP_DEF_GPIO 0xff
+/** Host sleep config gap : Default */
+#define HOST_SLEEP_DEF_GAP 200
+
+/** Type definition of mlan_ds_hs_cfg for MLAN_OID_PM_CFG_HS_CFG */
+typedef struct _mlan_ds_hs_cfg
+{
+    /** MTRUE to invoke the HostCmd, MFALSE otherwise */
+    t_u32 is_invoke_hostcmd;
+    /** Host sleep config condition */
+    /** Bit0: broadcast data
+     *  Bit1: unicast data
+     *  Bit2: mac event
+     *  Bit3: multicast data
+     */
+    t_u32 conditions;
+    /** GPIO pin or 0xff for interface */
+    t_u32 gpio;
+    /** Gap in milliseconds or or 0xff for special setting when GPIO is used to wakeup host */
+    t_u32 gap;
+} mlan_ds_hs_cfg, *pmlan_ds_hs_cfg;
+#endif
+
+/** Enable deep sleep mode */
+#define DEEP_SLEEP_ON 1
+/** Disable deep sleep mode */
+#define DEEP_SLEEP_OFF 0
+
+/** Default idle time in milliseconds for auto deep sleep */
+#define DEEP_SLEEP_IDLE_TIME 100
+
+typedef struct _mlan_ds_auto_ds
+{
+    /** auto ds mode, 0 - disable, 1 - enable */
+    t_u16 auto_ds;
+    /** auto ds idle time in milliseconds */
+    t_u16 idletime;
+} mlan_ds_auto_ds;
+
+/** Type definition of mlan_ds_inactivity_to for MLAN_OID_PM_CFG_INACTIVITY_TO */
+typedef struct _mlan_ds_inactivity_to
+{
+    /** Timeout unit in microsecond, 0 means 1000us (1ms) */
+    t_u32 timeout_unit;
+    /** Inactivity timeout for unicast data */
+    t_u32 unicast_timeout;
+    /** Inactivity timeout for multicast data */
+    t_u32 mcast_timeout;
+    /** Timeout for additional Rx traffic after Null PM1 packet exchange */
+    t_u32 ps_entry_timeout;
+} mlan_ds_inactivity_to, *pmlan_ds_inactivity_to;
+
+/** Minimum sleep period in milliseconds */
+#define MIN_SLEEP_PERIOD 10
+/** Maximum sleep period in milliseconds */
+#define MAX_SLEEP_PERIOD 60
+/** Special setting for UPSD certification tests */
+#define SLEEP_PERIOD_RESERVED_FF 0xFF
+
+/** PS null interval disable */
+#define PS_NULL_DISABLE (-1)
+
+/** Local listen interval disable */
+#define MRVDRV_LISTEN_INTERVAL_DISABLE (-1)
+/** Minimum listen interval */
+#define MRVDRV_MIN_LISTEN_INTERVAL 0
+
+/** Minimum multiple DTIM */
+#define MRVDRV_MIN_MULTIPLE_DTIM 0
+/** Maximum multiple DTIM */
+#define MRVDRV_MAX_MULTIPLE_DTIM 5
+/** Ignore multiple DTIM */
+#define MRVDRV_IGNORE_MULTIPLE_DTIM 0xfffe
+/** Match listen interval to closest DTIM */
+#define MRVDRV_MATCH_CLOSEST_DTIM 0xfffd
+
+/** Minimum adhoc awake period */
+#define MIN_ADHOC_AWAKE_PD 0
+/** Maximum adhoc awake period */
+#define MAX_ADHOC_AWAKE_PD 31
+/** Special adhoc awake period */
+#define SPECIAL_ADHOC_AWAKE_PD 255
+
+/** Minimum beacon miss timeout in milliseconds */
+#define MIN_BCN_MISS_TO 0
+/** Maximum beacon miss timeout in milliseconds */
+#define MAX_BCN_MISS_TO 50
+/** Disable beacon miss timeout */
+#define DISABLE_BCN_MISS_TO 65535
+
+/** Minimum delay to PS in milliseconds */
+#define MIN_DELAY_TO_PS 0
+/** Maximum delay to PS in milliseconds */
+#define MAX_DELAY_TO_PS 65535
+/** Delay to PS unchanged */
+#define DELAY_TO_PS_UNCHANGED (-1)
+/** Default delay to PS in milliseconds */
+#define DELAY_TO_PS_DEFAULT 1000
+/** Delay for WNM retry request in milliseconds */
+#define DELAY_TO_PS_WNM 500
+
+/** PS mode: Unchanged */
+#define PS_MODE_UNCHANGED 0
+/** PS mode: Auto */
+#define PS_MODE_AUTO 1
+/** PS mode: Poll */
+#define PS_MODE_POLL 2
+/** PS mode: Null */
+#define PS_MODE_NULL 3
+
+/** Type definition of mlan_ds_ps_cfg for MLAN_OID_PM_CFG_PS_CFG */
+typedef struct _mlan_ds_ps_cfg
+{
+    /** PS null interval in seconds */
+    t_u32 ps_null_interval;
+    /** Multiple DTIM interval */
+    t_u32 multiple_dtim_interval;
+    /** Listen interval */
+    t_u32 listen_interval;
+    /** Adhoc awake period */
+    t_u32 adhoc_awake_period;
+    /** Beacon miss timeout in milliseconds */
+    t_u32 bcn_miss_timeout;
+    /** Delay to PS in milliseconds */
+    t_s32 delay_to_ps;
+    /** PS mode */
+    t_u32 ps_mode;
+} mlan_ds_ps_cfg, *pmlan_ds_ps_cfg;
+
+/** Type definition of mlan_ds_sleep_params for MLAN_OID_PM_CFG_SLEEP_PARAMS */
+typedef struct _mlan_ds_sleep_params
+{
+    /** Error */
+    t_u32 error;
+    /** Offset in microseconds */
+    t_u32 offset;
+    /** Stable time in microseconds */
+    t_u32 stable_time;
+    /** Calibration control */
+    t_u32 cal_control;
+    /** External sleep clock */
+    t_u32 ext_sleep_clk;
+    /** Reserved */
+    t_u32 reserved;
+} mlan_ds_sleep_params, *pmlan_ds_sleep_params;
+
+/** sleep_param */
+typedef struct _ps_sleep_param
+{
+    /** control bitmap */
+    t_u32 ctrl_bitmap;
+    /** minimum sleep period (micro second) */
+    t_u32 min_sleep;
+    /** maximum sleep period (micro second) */
+    t_u32 max_sleep;
+} ps_sleep_param;
+
+/** inactivity sleep_param */
+typedef struct _inact_sleep_param
+{
+    /** inactivity timeout (micro second) */
+    t_u32 inactivity_to;
+    /** miniumu awake period (micro second) */
+    t_u32 min_awake;
+    /** maximum awake period (micro second) */
+    t_u32 max_awake;
+} inact_sleep_param;
+
+/** flag for ps mode */
+#define PS_FLAG_PS_MODE 1U
+/** flag for sleep param */
+#define PS_FLAG_SLEEP_PARAM 2U
+/** flag for inactivity sleep param */
+#define PS_FLAG_INACT_SLEEP_PARAM 4U
+
+/** Disable power mode */
+#define PS_MODE_DISABLE 0
+/** Enable periodic dtim ps */
+#define PS_MODE_PERIODIC_DTIM 1
+/** Enable inactivity ps */
+#define PS_MODE_INACTIVITY 2
+
+/** mlan_ds_ps_mgmt */
+typedef struct _mlan_ds_ps_mgmt
+{
+    /** flags for valid field */
+    t_u16 flags;
+    /** power mode */
+    t_u16 ps_mode;
+    /** sleep param */
+    ps_sleep_param sleep_param;
+    /** inactivity sleep param */
+    inact_sleep_param inact_param;
+} mlan_ds_ps_mgmt;
+
+/** mlan_ds_ps_info */
+typedef struct _mlan_ds_ps_info
+{
+    /** suspend allowed flag */
+    t_u32 is_suspend_allowed;
+} mlan_ds_ps_info;
+
+/** Type definition of mlan_ds_wakeup_reason for MLAN_OID_PM_HS_WAKEUP_REASON */
+typedef struct _mlan_ds_hs_wakeup_reason
+{
+    t_u16 hs_wakeup_reason;
+} mlan_ds_hs_wakeup_reason;
+
+/** Type definition of mlan_ds_pm_cfg for MLAN_IOCTL_PM_CFG */
+typedef struct _mlan_ds_pm_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Power management parameter */
+    union
+    {
+        /** Power saving mode for MLAN_OID_PM_CFG_IEEE_PS */
+        t_u32 ps_mode;
+#if CONFIG_HOST_SLEEP
+        /** Host Sleep configuration for MLAN_OID_PM_CFG_HS_CFG */
+        mlan_ds_hs_cfg hs_cfg;
+#endif
+        /** Deep sleep mode for MLAN_OID_PM_CFG_DEEP_SLEEP */
+        mlan_ds_auto_ds auto_deep_sleep;
+        /** Inactivity timeout for MLAN_OID_PM_CFG_INACTIVITY_TO */
+        mlan_ds_inactivity_to inactivity_to;
+        /** Sleep period for MLAN_OID_PM_CFG_SLEEP_PD */
+        t_u32 sleep_period;
+        /** PS configuration parameters for MLAN_OID_PM_CFG_PS_CFG */
+        mlan_ds_ps_cfg ps_cfg;
+        /** PS configuration parameters for MLAN_OID_PM_CFG_SLEEP_PARAMS */
+        mlan_ds_sleep_params sleep_params;
+        /** PS configuration parameters for MLAN_OID_PM_CFG_PS_MODE */
+        mlan_ds_ps_mgmt ps_mgmt;
+        /** power info for MLAN_OID_PM_INFO */
+        mlan_ds_ps_info ps_info;
+        /** hs wakeup reason for MLAN_OID_PM_HS_WAKEUP_REASON */
+        mlan_ds_hs_wakeup_reason wakeup_reason;
+    } param;
+} mlan_ds_pm_cfg, *pmlan_ds_pm_cfg;
+
+/*-----------------------------------------------------------------*/
+/** WMM Configuration Group */
+/*-----------------------------------------------------------------*/
+
+/** WMM TSpec size */
+#define MLAN_WMM_TSPEC_SIZE 63
+/** WMM Add TS extra IE bytes */
+#define MLAN_WMM_ADDTS_EXTRA_IE_BYTES 256
+/** WMM statistics for packets hist bins */
+#define MLAN_WMM_STATS_PKTS_HIST_BINS 7
+/** Maximum number of AC QOS queues available */
+#define MLAN_WMM_MAX_AC_QUEUES 4
+
+/**
+ *  @brief IOCTL structure to send an ADDTS request and retrieve the response.
+ *
+ *  IOCTL structure from the application layer relayed to firmware to
+ *    instigate an ADDTS management frame with an appropriate TSPEC IE as well
+ *    as any additional IEs appended in the ADDTS Action frame.
+ *
+ *  @sa woal_wmm_addts_req_ioctl
+ */
+typedef struct
+{
+    mlan_cmd_result_e cmd_result;                  /**< Firmware execution result */
+
+    t_u32 timeout_ms;                              /**< Timeout value in milliseconds */
+    t_u8 ieee_status_code;                         /**< IEEE status code */
+
+    t_u32 ie_data_len;                             /**< Length of ie block in ie_data */
+    t_u8 ie_data[MLAN_WMM_TSPEC_SIZE               /**< TSPEC to send in the ADDTS */
+                 + MLAN_WMM_ADDTS_EXTRA_IE_BYTES]; /**< Extra IE buf*/
+} wlan_ioctl_wmm_addts_req_t;
+
+/**
+ *  @brief IOCTL structure to send a DELTS request.
+ *
+ *  IOCTL structure from the application layer relayed to firmware to
+ *    instigate an DELTS management frame with an appropriate TSPEC IE.
+ *
+ *  @sa woal_wmm_delts_req_ioctl
+ */
+typedef struct
+{
+    mlan_cmd_result_e cmd_result;      /**< Firmware execution result */
+    t_u8 ieee_reason_code;             /**< IEEE reason code sent, unused for WMM */
+    t_u32 ie_data_len;                 /**< Length of ie block in ie_data */
+    t_u8 ie_data[MLAN_WMM_TSPEC_SIZE]; /**< TSPEC to send in the DELTS */
+} wlan_ioctl_wmm_delts_req_t;
+
+/**
+ *  @brief IOCTL structure to configure a specific AC Queue's parameters
+ *
+ *  IOCTL structure from the application layer relayed to firmware to
+ *    get, set, or default the WMM AC queue parameters.
+ *
+ *  - msdu_lifetime_expiry is ignored if set to 0 on a set command
+ *
+ *  @sa woal_wmm_queue_config_ioctl
+ */
+typedef struct
+{
+    mlan_wmm_queue_config_action_e action; /**< Set, Get, or Default */
+    mlan_wmm_ac_e access_category;         /**< WMM_AC_BK(0) to WMM_AC_VO(3) */
+    t_u16 msdu_lifetime_expiry;            /**< lifetime expiry in TUs */
+    t_u8 supported_rates[10];              /**< Not supported yet */
+} wlan_ioctl_wmm_queue_config_t;
+
+/**
+ *  @brief IOCTL structure to start, stop, and get statistics for a WMM AC
+ *
+ *  IOCTL structure from the application layer relayed to firmware to
+ *    start or stop statistical collection for a given AC.  Also used to
+ *    retrieve and clear the collected stats on a given AC.
+ *
+ *  @sa woal_wmm_queue_stats_ioctl
+ */
+typedef struct
+{
+    /** Action of Queue Config : Start, Stop, or Get */
+    mlan_wmm_queue_stats_action_e action;
+    /** User Priority */
+    t_u8 user_priority;
+    /** Number of successful packets transmitted */
+    t_u16 pkt_count;
+    /** Packets lost; not included in pkt_count */
+    t_u16 pkt_loss;
+    /** Average Queue delay in microseconds */
+    t_u32 avg_queue_delay;
+    /** Average Transmission delay in microseconds */
+    t_u32 avg_tx_delay;
+    /** Calculated used time in units of 32 microseconds */
+    t_u16 used_time;
+    /** Calculated policed time in units of 32 microseconds */
+    t_u16 policed_time;
+    /** Queue Delay Histogram; number of packets per queue delay range
+     *
+     *  [0] -  0ms <= delay < 5ms
+     *  [1] -  5ms <= delay < 10ms
+     *  [2] - 10ms <= delay < 20ms
+     *  [3] - 20ms <= delay < 30ms
+     *  [4] - 30ms <= delay < 40ms
+     *  [5] - 40ms <= delay < 50ms
+     *  [6] - 50ms <= delay < msduLifetime (TUs)
+     */
+    t_u16 delay_histogram[MLAN_WMM_STATS_PKTS_HIST_BINS];
+} wlan_ioctl_wmm_queue_stats_t,
+    /** Type definition of mlan_ds_wmm_queue_stats for MLAN_OID_WMM_CFG_QUEUE_STATS */
+    mlan_ds_wmm_queue_stats, *pmlan_ds_wmm_queue_stats;
+
+/**
+ *  @brief IOCTL sub structure for a specific WMM AC Status
+ */
+typedef struct
+{
+    /** WMM Acm */
+    t_u8 wmm_acm;
+    /** Flow required flag */
+    t_u8 flow_required;
+    /** Flow created flag */
+    t_u8 flow_created;
+    /** Disabled flag */
+    t_u8 disabled;
+} wlan_ioctl_wmm_queue_status_ac_t;
+
+/**
+ *  @brief IOCTL structure to retrieve the WMM AC Queue status
+ *
+ *  IOCTL structure from the application layer to retrieve:
+ *     - ACM bit setting for the AC
+ *     - Firmware status (flow required, flow created, flow disabled)
+ *
+ *  @sa woal_wmm_queue_status_ioctl
+ */
+typedef struct
+{
+    /** WMM AC queue status */
+    wlan_ioctl_wmm_queue_status_ac_t ac_status[MLAN_WMM_MAX_AC_QUEUES];
+} wlan_ioctl_wmm_queue_status_t,
+    /** Type definition of mlan_ds_wmm_queue_status for MLAN_OID_WMM_CFG_QUEUE_STATUS */
+    mlan_ds_wmm_queue_status, *pmlan_ds_wmm_queue_status;
+
+/** Type definition of mlan_ds_wmm_addts for MLAN_OID_WMM_CFG_ADDTS */
+typedef struct _mlan_ds_wmm_addts
+{
+    /** Result of ADDTS request */
+    mlan_cmd_result_e result;
+    /** Timeout value in milliseconds */
+    t_u32 timeout;
+    /** IEEE status code */
+    t_u32 status_code;
+    /** Dialog token */
+    t_u8 dialog_tok;
+    /** TSPEC data length */
+    t_u8 ie_data_len;
+    /** TSPEC to send in the ADDTS + buffering for any extra IEs */
+    t_u8 ie_data[MLAN_WMM_TSPEC_SIZE + MLAN_WMM_ADDTS_EXTRA_IE_BYTES];
+} mlan_ds_wmm_addts, *pmlan_ds_wmm_addts;
+
+/** Type definition of mlan_ds_wmm_delts for MLAN_OID_WMM_CFG_DELTS */
+typedef struct _mlan_ds_wmm_delts
+{
+    /** Result of DELTS request */
+    mlan_cmd_result_e result;
+    /** IEEE status code */
+    t_u32 status_code;
+    /** TSPEC data length */
+    t_u8 ie_data_len;
+    /** TSPEC to send in the DELTS */
+    t_u8 ie_data[MLAN_WMM_TSPEC_SIZE];
+} mlan_ds_wmm_delts, *pmlan_ds_wmm_delts;
+
+/** Type definition of mlan_ds_wmm_queue_config for MLAN_OID_WMM_CFG_QUEUE_CONFIG */
+typedef struct _mlan_ds_wmm_queue_config
+{
+    /** Action of Queue Config : Set, Get, or Default */
+    mlan_wmm_queue_config_action_e action;
+    /** WMM Access Category: WMM_AC_BK(0) to WMM_AC_VO(3) */
+    mlan_wmm_ac_e access_category;
+    /** Lifetime expiry in TUs */
+    t_u16 msdu_lifetime_expiry;
+    /** Reserve for future use */
+    t_u8 reserved[10];
+} mlan_ds_wmm_queue_config, *pmlan_ds_wmm_queue_config;
+
+/** Type definition of mlan_ds_wmm_cfg for MLAN_IOCTL_WMM_CFG */
+typedef struct _mlan_ds_wmm_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** WMM configuration parameter */
+    union
+    {
+        /** WMM enable for MLAN_OID_WMM_CFG_ENABLE */
+        t_u32 wmm_enable;
+        /** QoS configuration for MLAN_OID_WMM_CFG_QOS */
+        t_u8 qos_cfg;
+        /** WMM add TS for MLAN_OID_WMM_CFG_ADDTS */
+        mlan_ds_wmm_addts addts;
+        /** WMM delete TS for MLAN_OID_WMM_CFG_DELTS */
+        mlan_ds_wmm_delts delts;
+        /** WMM queue configuration for MLAN_OID_WMM_CFG_QUEUE_CONFIG */
+        mlan_ds_wmm_queue_config q_cfg;
+        /** AC Parameters Record WMM_AC_BE, WMM_AC_BK, WMM_AC_VI,
+         * WMM_AC_VO */
+        wmm_ac_parameters_t ac_params[MAX_AC_QUEUES];
+        /** WMM queue status for MLAN_OID_WMM_CFG_QUEUE_STATS */
+        mlan_ds_wmm_queue_stats q_stats;
+        /** WMM queue status for MLAN_OID_WMM_CFG_QUEUE_STATUS */
+        mlan_ds_wmm_queue_status q_status;
+        /** WMM TS status for MLAN_OID_WMM_CFG_TS_STATUS */
+        mlan_ds_wmm_ts_status ts_status;
+    } param;
+} mlan_ds_wmm_cfg, *pmlan_ds_wmm_cfg;
+
+/*-----------------------------------------------------------------*/
+/** WPS Configuration Group */
+/*-----------------------------------------------------------------*/
+/** Enumeration for WPS session */
+enum _mlan_wps_status
+{
+    MLAN_WPS_CFG_SESSION_START = 1,
+    MLAN_WPS_CFG_SESSION_END   = 0
+};
+
+/** Type definition of mlan_ds_wps_cfg for MLAN_IOCTL_WPS_CFG */
+typedef struct _mlan_ds_wps_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** WPS configuration parameter */
+    union
+    {
+        /** WPS session for MLAN_OID_WPS_CFG_SESSION */
+        t_u32 wps_session;
+    } param;
+} mlan_ds_wps_cfg, *pmlan_ds_wps_cfg;
+
+/*-----------------------------------------------------------------*/
+/** 802.11n Configuration Group */
+/*-----------------------------------------------------------------*/
+/** Maximum MCS */
+#define NUM_MCS_FIELD 16
+
+/* Both 2.4G and 5G band selected */
+#define BAND_SELECT_BOTH 0U
+/* Band 2.4G selected */
+#define BAND_SELECT_BG 1U
+/* Band 5G selected */
+#define BAND_SELECT_A 2U
+
+/** Type definition of mlan_ds_11n_htcap_cfg for MLAN_OID_11N_HTCAP_CFG */
+typedef struct _mlan_ds_11n_htcap_cfg
+{
+    /** HT Capability information */
+    t_u32 htcap;
+    /** Band selection */
+    t_u32 misc_cfg;
+    /** Hardware HT cap information required */
+    t_u32 hw_cap_req;
+} mlan_ds_11n_htcap_cfg, *pmlan_ds_11n_htcap_cfg;
+
+/** Type definition of mlan_ds_11n_addba_param for MLAN_OID_11N_CFG_ADDBA_PARAM */
+typedef struct _mlan_ds_11n_addba_param
+{
+    /** Timeout */
+    t_u32 timeout;
+    /** Buffer size for ADDBA request */
+    t_u32 txwinsize;
+    /** Buffer size for ADDBA response */
+    t_u32 rxwinsize;
+    /** amsdu for ADDBA request */
+    t_u8 txamsdu;
+    /** amsdu for ADDBA response */
+    t_u8 rxamsdu;
+} mlan_ds_11n_addba_param, *pmlan_ds_11n_addba_param;
+
+/** Type definition of mlan_ds_11n_tx_cfg for MLAN_OID_11N_CFG_TX */
+typedef struct _mlan_ds_11n_tx_cfg
+{
+    /** HTTxCap */
+    t_u16 httxcap;
+    /** HTTxInfo */
+    t_u16 httxinfo;
+    /** Band selection */
+    t_u32 misc_cfg;
+} mlan_ds_11n_tx_cfg, *pmlan_ds_11n_tx_cfg;
+
+/** Tx */
+#define MLAN_RADIO_TX MBIT(0)
+/** Rx */
+#define MLAN_RADIO_RX MBIT(1)
+/** Tx & Rx */
+#define MLAN_RADIO_TXRX (MLAN_RADIO_TX | MLAN_RADIO_RX)
+
+/** Type definition of mlan_ds_11ac_tx_cfg for MLAN_OID_11AC_CFG */
+typedef struct _mlan_ds_11ac_vht_cfg
+{
+    /** Band selection (1: 2.4G, 2: 5 G, 3: both 2.4G and 5G) */
+    t_u32 band;
+    /** TxRx (1: Tx, 2: Rx, 3: both Tx and Rx) */
+    t_u32 txrx;
+    /** BW CFG (0: 11N CFG, 1: vhtcap) */
+    t_u32 bwcfg;
+    /** VHT capabilities. */
+    t_u32 vht_cap_info;
+    /** VHT Tx mcs */
+    t_u32 vht_tx_mcs;
+    /** VHT Rx mcs */
+    t_u32 vht_rx_mcs;
+    /** VHT rx max rate */
+    t_u16 vht_rx_max_rate;
+    /** VHT max tx rate */
+    t_u16 vht_tx_max_rate;
+    /** Skip usr 11ac mcs cfg */
+    t_bool skip_usr_11ac_mcs_cfg;
+} mlan_ds_11ac_vht_cfg, *pmlan_ds_11ac_vht_cfg;
+
+#if CONFIG_11AX
+#define MAX_RU_COUNT    6
+#define MAX_RUTXPWR_NUM 140
+typedef MLAN_PACK_START struct _mlan_rupwrlimit_config_t
+{
+    /** start freq */
+    t_u16 start_freq;
+    /* channel width */
+    t_u8 width;
+    /** channel number */
+    t_u8 chan_num;
+    /** chan ru Power */
+    t_s8 ruPower[MAX_RU_COUNT];
+} MLAN_PACK_END mlan_rupwrlimit_config_t;
+
+typedef MLAN_PACK_START struct _mlan_11axcmdcfg_obss_pd_offset
+{
+    /** <NON_SRG_OffSET, SRG_OFFSET> */
+    t_u8 offset[2];
+} MLAN_PACK_END mlan_11axcmdcfg_obss_pd_offset;
+
+/** Type definition of mlan_11axcmdcfg_sr_control for MLAN_OID_11AX_CMD_CFG */
+typedef MLAN_PACK_START struct _mlan_11axcmdcfg_sr_control
+{
+    /** 1 enable, 0 disable */
+    t_u8 control;
+} MLAN_PACK_END mlan_11axcmdcfg_sr_control;
+
+/** Type definition of mlan_ds_11ax_he_capa for MLAN_OID_11AX_HE_CFG */
+typedef MLAN_PACK_START struct _mlan_ds_11ax_he_capa
+{
+    /** tlv id of he capability */
+    t_u16 id;
+    /** length of the payload */
+    t_u16 len;
+    /** extension id */
+    t_u8 ext_id;
+    /** he mac capability info */
+    t_u8 he_mac_cap[6];
+    /** he phy capability info */
+    t_u8 he_phy_cap[11];
+    /** he txrx mcs support for 80MHz */
+    t_u8 he_txrx_mcs_support[4];
+    /** val for txrx mcs 160Mhz or 80+80, and PPE thresholds */
+    t_u8 val[28];
+} MLAN_PACK_END mlan_ds_11ax_he_capa, *pmlan_ds_11ax_he_capa;
+
+/** Type definition of mlan_ds_11ax_he_cfg for MLAN_OID_11AX_HE_CFG */
+typedef struct _mlan_ds_11ax_he_cfg
+{
+    /** band, BIT0:2.4G, BIT1:5G*/
+    t_u8 band;
+    /** mlan_ds_11ax_he_capa */
+    mlan_ds_11ax_he_capa he_cap;
+} mlan_ds_11ax_he_cfg, *pmlan_ds_11ax_he_cfg;
+
+/** Type definition of mlan_ds_11ax_sr_cmd for MLAN_OID_11AX_CMD_CFG */
+typedef MLAN_PACK_START struct _mlan_ds_11ax_sr_cmd
+{
+    /** type*/
+    t_u16 type;
+    /** length of TLV */
+    t_u16 len;
+    /** value */
+    union
+    {
+        mlan_11axcmdcfg_obss_pd_offset obss_pd_offset;
+        mlan_11axcmdcfg_sr_control sr_control;
+    } param;
+} MLAN_PACK_END mlan_ds_11ax_sr_cmd, *pmlan_ds_11ax_sr_cmd;
+
+/** Type definition of mlan_ds_11ax_beam_cmd for MLAN_OID_11AX_CMD_CFG */
+typedef struct _mlan_ds_11ax_beam_cmd
+{
+    /** command value: 1 is disable, 0 is enable*/
+    t_u8 value;
+} mlan_ds_11ax_beam_cmd, *pmlan_ds_11ax_beam_cmd;
+
+/** Type definition of mlan_ds_11ax_htc_cmd for MLAN_OID_11AX_CMD_CFG */
+typedef struct _mlan_ds_11ax_htc_cmd
+{
+    /** command value: 1 is enable, 0 is disable*/
+    t_u8 value;
+} mlan_ds_11ax_htc_cmd, *pmlan_ds_11ax_htc_cmd;
+
+/** Type definition of mlan_ds_11ax_htc_cmd for MLAN_OID_11AX_CMD_CFG */
+typedef struct _mlan_ds_11ax_txop_cmd
+{
+    /** Two byte rts threshold value of which only 10 bits, bit 0 to bit 9
+     * are valid */
+    t_u16 rts_thres;
+} mlan_ds_11ax_txop_cmd, *pmlan_ds_11ax_txop_cmd;
+
+/** Type definition of mlan_ds_11ax_htc_cmd for MLAN_OID_11AX_CMD_CFG */
+typedef MLAN_PACK_START struct _mlan_ds_11ax_txomi_cmd
+{
+    /* 11ax spec 9.2.4.6a.2 OM Control 12 bits. Bit 0 to bit 11 */
+    t_u16 omi;
+    /* tx option
+     * 0: send OMI in QoS NULL; 1: send OMI in QoS data;
+     * 0xFF: OMI is transmitted in both QoS NULL and QoS data frame.
+     */
+    t_u8 tx_option;
+    /* num_data_pkts is applied only if OMI is sent in QoS data frame.
+     * It specifies the number of consecutive data frames containing the OMI.
+     * Minimum number of data packets should be 1 and maximum should be 16.
+     */
+    t_u8 num_data_pkts;
+} MLAN_PACK_END mlan_ds_11ax_txomi_cmd, *pmlan_ds_11ax_txomi_cmd;
+
+/** Type definition of mlan_ds_11ax_toltime_cmd for MLAN_OID_11AX_CMD_CFG */
+typedef struct _mlan_ds_11ax_toltime_cmd
+{
+    /* OBSS Narrow Bandwidth RU Tolerance Time */
+    t_u32 tol_time;
+} mlan_ds_11ax_toltime_cmd, *pmlan_ds_11ax_toltime_cmd;
+
+/** Type definition of mlan_ds_11ax_chanlrupwrcft_cmd for MLAN_OID_11AX_CMD_CFG */
+typedef struct _mlan_ds_11ax_chanlrupwrcft_cmd
+{
+    /** type*/
+    t_u16 type;
+    /** length of TLV */
+    t_u16 len;
+    /* Channel RU TX power limit Config */
+    mlan_rupwrlimit_config_t rupwrlimit_config;
+} mlan_ds_11ax_chanlrupwrcft_cmd, *pmlan_ds_11ax_chanlrupwrcft_cmd;
+
+/** Type definition of mlan_ds_11ax_cmd_cfg for MLAN_OID_11AX_CMD_CFG */
+typedef struct _mlan_ds_11ax_cmd_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Sub-id */
+    t_u32 sub_id;
+    /** 802.11n configuration parameter */
+    union
+    {
+        /** SR configuration for MLAN_11AXCMD_SR_SUBID */
+        mlan_ds_11ax_sr_cmd sr_cfg;
+        /** Beam configuration for MLAN_11AXCMD_BEAM_SUBID */
+        mlan_ds_11ax_beam_cmd beam_cfg;
+        /** HTC configuration for MLAN_11AXCMD_HTC_SUBID */
+        mlan_ds_11ax_htc_cmd htc_cfg;
+        /** txop RTS configuration for MLAN_11AXCMD_TXOPRTS_SUBID */
+        mlan_ds_11ax_txop_cmd txop_cfg;
+        /** tx omi configuration for MLAN_11AXCMD_TXOMI_SUBID */
+        mlan_ds_11ax_txomi_cmd txomi_cfg;
+        /** OBSS tolerance time configuration for
+         * MLAN_11AXCMD_TOLTIME_SUBID */
+        mlan_ds_11ax_toltime_cmd toltime_cfg;
+        /** Channel RU TX power limit Config for
+         * MLAN_11AXCMD_RUPOWER_SUBID */
+        mlan_ds_11ax_chanlrupwrcft_cmd rupwr_cfg;
+    } param;
+} mlan_ds_11ax_cmd_cfg, *pmlan_ds_11ax_cmd_cfg;
+
+#if CONFIG_11AX_TWT
+/** Type definition of mlan_ds_twt_setup for MLAN_OID_11AX_TWT_CFG */
+typedef MLAN_PACK_START struct _mlan_ds_twt_setup
+{
+    /** Implicit, 0: TWT session is explicit, 1: Session is implicit */
+    t_u8 implicit;
+    /** Announced, 0: Unannounced, 1: Announced TWT */
+    t_u8 announced;
+    /** Trigger Enabled, 0: Non-Trigger enabled, 1: Trigger enabled TWT */
+    t_u8 trigger_enabled;
+    /** TWT Information Disabled, 0: TWT info enabled, 1: TWT info disabled */
+    t_u8 twt_info_disabled;
+    /** Negotiation Type, 0: Future Individual TWT SP start time, 1: Next
+     * Wake TBTT time */
+    t_u8 negotiation_type;
+    /** TWT Wakeup Duration, time after which the TWT requesting STA can
+     * transition to doze state */
+    t_u8 twt_wakeup_duration;
+    /** Flow Identifier. Range: [0-7]*/
+    t_u8 flow_identifier;
+    /** Hard Constraint, 0: FW can tweak the TWT setup parameters if it is
+     *rejected by AP.
+     ** 1: Firmware should not tweak any parameters. */
+    t_u8 hard_constraint;
+    /** TWT Exponent, Range: [0-63] */
+    t_u8 twt_exponent;
+    /** TWT Mantissa Range: [0-sizeof(UINT16)] */
+    t_u16 twt_mantissa;
+    /** TWT Request Type, 0: REQUEST_TWT, 1: SUGGEST_TWT*/
+    t_u8 twt_request;
+} MLAN_PACK_END mlan_ds_twt_setup, *pmlan_ds_twt_setup;
+
+/** Type definition of mlan_ds_twt_teardown for MLAN_OID_11AX_TWT_CFG */
+typedef MLAN_PACK_START struct _mlan_ds_twt_teardown
+{
+    /** TWT Flow Identifier. Range: [0-7] */
+    t_u8 flow_identifier;
+    /** Negotiation Type. 0: Future Individual TWT SP start time, 1: Next
+     * Wake TBTT time */
+    t_u8 negotiation_type;
+    /** Tear down all TWT. 1: To teardown all TWT, 0 otherwise */
+    t_u8 teardown_all_twt;
+} MLAN_PACK_END mlan_ds_twt_teardown, *pmlan_ds_twt_teardown;
+
+/** Type definition of mlan_ds_twt_report for MLAN_OID_11AX_TWT_CFG */
+typedef MLAN_PACK_START struct _mlan_ds_twt_report
+{
+    /** TWT report type, 0: BTWT id */
+    t_u8 type;
+    /** TWT report length of value in data */
+    t_u8 length;
+    t_u8 reserve[2];
+    /** TWT report payload for FW response to fill, 4 * 9bytes */
+    t_u8 data[36];
+} MLAN_PACK_END mlan_ds_twt_report, *pmlan_ds_twt_report;
+
+/** Type definition of mlan_ds_twtcfg for MLAN_OID_11AX_TWT_CFG */
+typedef MLAN_PACK_START struct _mlan_ds_twtcfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Sub-id */
+    t_u32 sub_id;
+    /** TWT Setup/Teardown configuration parameter */
+    union
+    {
+        /** TWT Setup config for Sub ID: MLAN_11AX_TWT_SETUP_SUBID */
+        mlan_ds_twt_setup twt_setup;
+        /** TWT Teardown config for Sub ID: MLAN_11AX_TWT_TEARDOWN_SUBID */
+        mlan_ds_twt_teardown twt_teardown;
+        /** TWT report for Sub ID: MLAN_11AX_TWT_REPORT_SUBID */
+        mlan_ds_twt_report twt_report;
+    } param;
+} MLAN_PACK_END mlan_ds_twtcfg, *pmlan_ds_twtcfg;
+#endif /* CONFIG_11AX_TWT */
+
+/** Type definition of mlan_ds_11as_cfg for MLAN_IOCTL_11AX_CFG */
+typedef struct _mlan_ds_11ax_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** 802.11n configuration parameter */
+    union
+    {
+        /** HE configuration for MLAN_OID_11AX_HE_CFG */
+        mlan_ds_11ax_he_cfg he_cfg;
+    } param;
+} mlan_ds_11ax_cfg, *pmlan_ds_11ax_cfg;
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+/** Type definition of mlan_ds_gpio_tsf_latch */
+typedef MLAN_PACK_START struct _mlan_ds_gpio_tsf_latch
+{
+    /**clock sync Mode */
+    t_u8 clock_sync_mode;
+    /**clock sync Role */
+    t_u8 clock_sync_Role;
+    /**clock sync GPIO Pin Number */
+    t_u8 clock_sync_gpio_pin_number;
+    /**clock sync GPIO Level or Toggle */
+    t_u8 clock_sync_gpio_level_toggle;
+    /**clock sync GPIO Pulse Width */
+    t_u16 clock_sync_gpio_pulse_width;
+} MLAN_PACK_END mlan_ds_gpio_tsf_latch, *pmlan_ds_gpio_tsf_latch;
+
+/** Type definition of mlan_ds_tsf_info */
+typedef MLAN_PACK_START struct _mlan_ds_tsf_info
+{
+    /**get tsf info format */
+    t_u16 tsf_format;
+    /**tsf info */
+    t_u16 tsf_info;
+    /**tsf */
+    t_u64 tsf;
+    /**Positive or negative offset in microsecond from Beacon TSF to GPIO toggle TSF  */
+    t_s32 tsf_offset;
+} MLAN_PACK_END mlan_ds_tsf_info, *pmlan_ds_tsf_info;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+/** Type definition of mlan_ds_11n_amsdu_aggr_ctrl for
+ * MLAN_OID_11N_AMSDU_AGGR_CTRL*/
+typedef struct _mlan_ds_11n_amsdu_aggr_ctrl
+{
+    /** Enable/Disable */
+    t_u16 enable;
+    /** Current AMSDU size valid */
+    t_u16 curr_buf_size;
+} mlan_ds_11n_amsdu_aggr_ctrl, *pmlan_ds_11n_amsdu_aggr_ctrl;
+
+/** Type definition of mlan_ds_11n_aggr_prio_tbl for MLAN_OID_11N_CFG_AGGR_PRIO_TBL */
+typedef struct _mlan_ds_11n_aggr_prio_tbl
+{
+    /** ampdu priority table */
+    t_u8 ampdu[MAX_NUM_TID];
+    /** amsdu priority table */
+    t_u8 amsdu[MAX_NUM_TID];
+} mlan_ds_11n_aggr_prio_tbl, *pmlan_ds_11n_aggr_prio_tbl;
+
+/** DelBA All TIDs */
+#define DELBA_ALL_TIDS 0xff
+/** DelBA Tx */
+#define DELBA_TX MBIT(0)
+/** DelBA Rx */
+#define DELBA_RX MBIT(1)
+
+/** Type definition of mlan_ds_11n_delba for MLAN_OID_11N_CFG_DELBA */
+typedef struct _mlan_ds_11n_delba
+{
+    /** TID */
+    t_u8 tid;
+    /** Peer MAC address */
+    t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Direction (Tx: bit 0, Rx: bit 1) */
+    t_u8 direction;
+} mlan_ds_11n_delba, *pmlan_ds_11n_delba;
+
+/** Type definition of mlan_ds_11n_cfg for MLAN_IOCTL_11N_CFG */
+typedef struct _mlan_ds_11n_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** 802.11n configuration parameter */
+    union
+    {
+        /** Tx param for 11n for MLAN_OID_11N_CFG_TX */
+        mlan_ds_11n_tx_cfg tx_cfg;
+        /** Aggr priority table for MLAN_OID_11N_CFG_AGGR_PRIO_TBL */
+        mlan_ds_11n_aggr_prio_tbl aggr_prio_tbl;
+        /** Add BA param for MLAN_OID_11N_CFG_ADDBA_PARAM */
+        mlan_ds_11n_addba_param addba_param;
+        /** Add BA Reject paramters for MLAN_OID_11N_CFG_ADDBA_REJECT */
+        t_u8 addba_reject[MAX_NUM_TID];
+        /** Tx buf size for MLAN_OID_11N_CFG_MAX_TX_BUF_SIZE */
+        t_u32 tx_buf_size;
+        /** HT cap info configuration for MLAN_OID_11N_HTCAP_CFG */
+        mlan_ds_11n_htcap_cfg htcap_cfg;
+        /** Tx param for 11n for MLAN_OID_11N_AMSDU_AGGR_CTRL */
+        mlan_ds_11n_amsdu_aggr_ctrl amsdu_aggr_ctrl;
+        /** Supported MCS Set field */
+        t_u8 supported_mcs_set[NUM_MCS_FIELD];
+        /** Transmit Beamforming Capabilities field */
+        t_u32 tx_bf_cap;
+        /** DelBA for MLAN_OID_11N_CFG_DELBA */
+        mlan_ds_11n_delba del_ba;
+    } param;
+} mlan_ds_11n_cfg, *pmlan_ds_11n_cfg;
+
+/** Country code length */
+#define COUNTRY_CODE_LEN 3U
+
+/*-----------------------------------------------------------------*/
+/** 802.11d Configuration Group */
+/*-----------------------------------------------------------------*/
+/** Maximum subbands for 11d */
+#if CONFIG_5GHz_SUPPORT
+#define MRVDRV_MAX_SUBBAND_802_11D 83U
+#else
+#define MRVDRV_MAX_SUBBAND_802_11D 14
+#endif /* CONFIG_5GHz_SUPPORT */
+
+/** Data structure for subband set */
+typedef struct _mlan_ds_subband_set_t
+{
+    /** First channel */
+    t_u8 first_chan;
+    /** Number of channels */
+    t_u8 no_of_chan;
+    /** Maximum Tx power in dBm */
+    t_u8 max_tx_pwr;
+} mlan_ds_subband_set_t;
+
+/** Domain regulatory information */
+typedef struct _mlan_ds_11d_domain_info
+{
+    /** Country Code */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /** Band that channels in sub_band belong to */
+    t_u16 band;
+    /** No. of subband in below */
+    t_u8 no_of_sub_band;
+    /** Subband data to send/last sent */
+    mlan_ds_subband_set_t sub_band[MRVDRV_MAX_SUBBAND_802_11D];
+} mlan_ds_11d_domain_info;
+
+/** Type definition of mlan_ds_11d_cfg for MLAN_IOCTL_11D_CFG */
+typedef struct _mlan_ds_11d_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** 802.11d configuration parameter */
+    union
+    {
+        /** Enable for MLAN_OID_11D_CFG_ENABLE */
+        t_u32 enable_11d;
+        /** Domain info for MLAN_OID_11D_DOMAIN_INFO */
+        mlan_ds_11d_domain_info domain_info;
+        /** tlv data for MLAN_OID_11D_DOMAIN_INFO */
+        t_u8 domain_tlv[MAX_IE_SIZE];
+    } param;
+} mlan_ds_11d_cfg, *pmlan_ds_11d_cfg;
+
+/*-----------------------------------------------------------------*/
+/** Register Memory Access Group */
+/*-----------------------------------------------------------------*/
+/** Enumeration for register type */
+enum _mlan_reg_type
+{
+    MLAN_REG_MAC = 1,
+    MLAN_REG_BBP,
+    MLAN_REG_RF,
+    MLAN_REG_CAU = 5,
+};
+
+/** Type definition of mlan_ds_reg_rw for MLAN_OID_REG_RW */
+typedef struct _mlan_ds_reg_rw
+{
+    /** Register type */
+    t_u32 type;
+    /** Offset */
+    t_u32 offset;
+    /** Value */
+    t_u32 value;
+} mlan_ds_reg_rw;
+
+/** Maximum EEPROM data */
+/* wmsdk: The value of MAX_EEPROM_DATA has been changed from 256 to 1. This is
+ * done as this structure is used to set only the offset and byte_count. The
+ * command (iwpriv mlan rdeeprom <offset> <length>) being GET command, its value
+ * parameter is always sent as 0 */
+#define MAX_EEPROM_DATA 1
+
+/** Type definition of mlan_ds_read_eeprom for MLAN_OID_EEPROM_RD */
+typedef struct _mlan_ds_read_eeprom
+{
+    /** Multiples of 4 */
+    t_u16 offset;
+    /** Number of bytes */
+    t_u16 byte_count;
+    /** Value */
+    t_u8 value[MAX_EEPROM_DATA];
+} mlan_ds_read_eeprom;
+
+/** Type definition of mlan_ds_mem_rw for MLAN_OID_MEM_RW */
+typedef struct _mlan_ds_mem_rw
+{
+    /** Address */
+    t_u32 addr;
+    /** Value */
+    t_u32 value;
+} mlan_ds_mem_rw;
+
+/** Type definition of mlan_ds_reg_mem for MLAN_IOCTL_REG_MEM */
+typedef struct _mlan_ds_reg_mem
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Register memory access parameter */
+    union
+    {
+        /** Register access for MLAN_OID_REG_RW */
+        mlan_ds_reg_rw reg_rw;
+        /** EEPROM access for MLAN_OID_EEPROM_RD */
+        mlan_ds_read_eeprom rd_eeprom;
+        /** Memory access for MLAN_OID_MEM_RW */
+        mlan_ds_mem_rw mem_rw;
+    } param;
+} mlan_ds_reg_mem, *pmlan_ds_reg_mem;
+
+/** Type definition of mlan_ds_auto_reconnect */
+typedef struct _mlan_ds_auto_reconnect
+{
+    /** Reconnect Counter */
+    t_u8 reconnect_counter;
+    /** Reconnect Interval */
+    t_u8 reconnect_interval;
+    /** Flags */
+    t_u16 flags;
+} mlan_ds_auto_reconnect;
+
+/** Type definition of mlan_ds_rx_mgmt_indication */
+typedef struct _mlan_ds_rx_mgmt_indication
+{
+    /** Mgmt subtype mask for MLAN_OID_MISC_RX_MGMT_IND */
+    t_u32 mgmt_subtype_mask;
+} mlan_ds_rx_mgmt_indication;
+
+/** Type definition of mlan_bridge_mode */
+typedef struct _mlan_bridge_mode
+{
+    /** Value */
+    t_u8 enable;
+} mlan_bridge_mode;
+
+/*-----------------------------------------------------------------*/
+/** Multi-Radio Configuration Group */
+/*-----------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------*/
+/** 802.11h Configuration Group */
+/*-----------------------------------------------------------------*/
+
+/** Type definition of mlan_ds_11h_cfg for MLAN_IOCTL_11H_CFG */
+typedef struct _mlan_ds_11h_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    union
+    {
+        /** Local power constraint for MLAN_OID_11H_LOCAL_POWER_CONSTRAINT */
+        t_s8 usr_local_power_constraint;
+    } param;
+} mlan_ds_11h_cfg, *pmlan_ds_11h_cfg;
+
+/*-----------------------------------------------------------------*/
+/** Miscellaneous Configuration Group */
+/*-----------------------------------------------------------------*/
+
+/** CMD buffer size */
+#define MLAN_SIZE_OF_CMD_BUFFER 2048
+
+/** LDO Internal */
+#define LDO_INTERNAL 0
+/** LDO External */
+#define LDO_EXTERNAL 1
+
+/** Enumeration for IE type */
+enum _mlan_ie_type
+{
+    MLAN_IE_TYPE_GEN_IE = 0,
+    MLAN_IE_TYPE_ARP_FILTER,
+};
+
+/** Type definition of mlan_ds_misc_gen_ie for MLAN_OID_MISC_GEN_IE */
+typedef struct _mlan_ds_misc_gen_ie
+{
+    /** IE type */
+    t_u32 type;
+    /** IE length */
+    t_u32 len;
+    /** IE buffer */
+    t_u8 ie_data[MAX_IE_SIZE];
+} mlan_ds_misc_gen_ie;
+
+
+/** Type definition of mlan_ds_misc_cmd for MLAN_OID_MISC_HOST_CMD */
+typedef struct _mlan_ds_misc_cmd
+{
+    /** Command length */
+    t_u32 len;
+    /** Command buffer */
+    t_u8 cmd[MLAN_SIZE_OF_CMD_BUFFER];
+} mlan_ds_misc_cmd;
+
+/** Maximum number of system clocks */
+#define MLAN_MAX_CLK_NUM 16
+
+/** Clock type : Configurable */
+#define MLAN_CLK_CONFIGURABLE 0
+/** Clock type : Supported */
+#define MLAN_CLK_SUPPORTED 1
+
+/** Type definition of mlan_ds_misc_sys_clock for MLAN_OID_MISC_SYS_CLOCK */
+typedef struct _mlan_ds_misc_sys_clock
+{
+    /** Current system clock */
+    t_u16 cur_sys_clk;
+    /** Clock type */
+    t_u16 sys_clk_type;
+    /** Number of clocks */
+    t_u16 sys_clk_num;
+    /** System clocks */
+    t_u16 sys_clk[MLAN_MAX_CLK_NUM];
+} mlan_ds_misc_sys_clock;
+
+/** Enumeration for function init/shutdown */
+enum _mlan_func_cmd
+{
+    MLAN_FUNC_INIT = 1,
+    MLAN_FUNC_SHUTDOWN,
+};
+
+/** Type definition of mlan_ds_misc_tx_datapause for MLAN_OID_MISC_TX_DATAPAUSE */
+typedef struct _mlan_ds_misc_tx_datapause
+{
+    /** Tx data pause flag */
+    t_u16 tx_pause;
+    /** Max number of Tx buffers for all PS clients */
+    t_u16 tx_buf_cnt;
+} mlan_ds_misc_tx_datapause;
+
+/** IP address length */
+#define IPADDR_LEN (16)
+/** Max number of ip */
+#define MAX_IPADDR (4)
+/** IP address type - IPv4*/
+#define IPADDR_TYPE_IPV4 (1)
+/** IP operation remove */
+#define MLAN_IPADDR_OP_IP_REMOVE (0)
+/** IP operation ARP filter */
+#define MLAN_IPADDR_OP_ARP_FILTER MBIT(0)
+/** IP operation ARP response */
+#define MLAN_IPADDR_OP_AUTO_ARP_RESP MBIT(1)
+
+/** Type definition of mlan_ds_misc_ipaddr_cfg for MLAN_OID_MISC_IP_ADDR */
+typedef struct _mlan_ds_misc_ipaddr_cfg
+{
+    /** Operation code */
+    t_u32 op_code;
+    /** IP address type */
+    t_u32 ip_addr_type;
+    /** Number of IP */
+    t_u32 ip_addr_num;
+    /** IP address */
+    t_u8 ip_addr[MAX_IPADDR][IPADDR_LEN];
+} mlan_ds_misc_ipaddr_cfg;
+
+/* MEF configuration disable */
+#define MEF_CFG_DISABLE 0
+/* MEF configuration Rx filter enable */
+#define MEF_CFG_RX_FILTER_ENABLE 1
+/* MEF configuration auto ARP response */
+#define MEF_CFG_AUTO_ARP_RESP 2
+/* MEF configuration host command */
+#define MEF_CFG_HOSTCMD 0xFFFF
+
+/** Type definition of mlan_ds_misc_mef_cfg for MLAN_OID_MISC_MEF_CFG */
+typedef struct _mlan_ds_misc_mef_cfg
+{
+    /** Sub-ID for operation */
+    t_u32 sub_id;
+    /** Parameter according to sub-ID */
+    union
+    {
+        /** MEF command buffer for MEF_CFG_HOSTCMD */
+        mlan_ds_misc_cmd cmd_buf;
+    } param;
+} mlan_ds_misc_mef_cfg;
+
+/** Type definition of mlan_ds_misc_cfp_code for MLAN_OID_MISC_CFP_CODE */
+typedef struct _mlan_ds_misc_cfp_code
+{
+    /** CFP table code for 2.4GHz */
+    t_u32 cfp_code_bg;
+    /** CFP table code for 5GHz */
+    t_u32 cfp_code_a;
+} mlan_ds_misc_cfp_code;
+
+/** Type definition of mlan_ds_misc_country_code for MLAN_OID_MISC_COUNTRY_CODE */
+typedef struct _mlan_ds_misc_country_code
+{
+    /** Country Code */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+} mlan_ds_misc_country_code;
+
+/** action for set */
+#define SUBSCRIBE_EVT_ACT_BITWISE_SET 0x0002
+/** action for clear */
+#define SUBSCRIBE_EVT_ACT_BITWISE_CLR 0x0003
+/** BITMAP for subscribe event rssi low */
+#define SUBSCRIBE_EVT_RSSI_LOW MBIT(0)
+/** BITMAP for subscribe event snr low */
+#define SUBSCRIBE_EVT_SNR_LOW MBIT(1)
+/** BITMAP for subscribe event max fail */
+#define SUBSCRIBE_EVT_MAX_FAIL MBIT(2)
+/** BITMAP for subscribe event beacon missed */
+#define SUBSCRIBE_EVT_BEACON_MISSED MBIT(3)
+/** BITMAP for subscribe event rssi high */
+#define SUBSCRIBE_EVT_RSSI_HIGH MBIT(4)
+/** BITMAP for subscribe event snr high */
+#define SUBSCRIBE_EVT_SNR_HIGH MBIT(5)
+/** BITMAP for subscribe event data rssi low */
+#define SUBSCRIBE_EVT_DATA_RSSI_LOW MBIT(6)
+/** BITMAP for subscribe event data snr low */
+#define SUBSCRIBE_EVT_DATA_SNR_LOW MBIT(7)
+/** BITMAP for subscribe event data rssi high */
+#define SUBSCRIBE_EVT_DATA_RSSI_HIGH MBIT(8)
+/** BITMAP for subscribe event data snr high */
+#define SUBSCRIBE_EVT_DATA_SNR_HIGH MBIT(9)
+/** BITMAP for subscribe event link quality */
+#define SUBSCRIBE_EVT_LINK_QUALITY MBIT(10)
+/** BITMAP for subscribe event pre_beacon_lost */
+#define SUBSCRIBE_EVT_PRE_BEACON_LOST MBIT(11)
+/** default PRE_BEACON_MISS_COUNT */
+#define DEFAULT_PRE_BEACON_MISS 30
+
+/** Type definition of mlan_ds_subscribe_evt for MLAN_OID_MISC_CFP_CODE */
+typedef struct _mlan_ds_subscribe_evt
+{
+    /** evt action */
+    t_u16 evt_action;
+    /** bitmap for subscribe event */
+    t_u16 evt_bitmap;
+    /** Absolute value of RSSI threshold value (dBm) */
+    t_u8 low_rssi;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 low_rssi_freq;
+    /** SNR threshold value (dB) */
+    t_u8 low_snr;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 low_snr_freq;
+    /** Failure count threshold */
+    t_u8 failure_count;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 failure_count_freq;
+    /** num of missed beacons */
+    t_u8 beacon_miss;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 beacon_miss_freq;
+    /** Absolute value of RSSI threshold value (dBm) */
+    t_u8 high_rssi;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 high_rssi_freq;
+    /** SNR threshold value (dB) */
+    t_u8 high_snr;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 high_snr_freq;
+    /** Absolute value of data RSSI threshold value (dBm) */
+    t_u8 data_low_rssi;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 data_low_rssi_freq;
+    /** Absolute value of data SNR threshold value (dBm) */
+    t_u8 data_low_snr;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 data_low_snr_freq;
+    /** Absolute value of data RSSI threshold value (dBm) */
+    t_u8 data_high_rssi;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 data_high_rssi_freq;
+    /** Absolute value of data SNR threshold value (dBm) */
+    t_u8 data_high_snr;
+    /** 0--report once, 1--report everytime happen, N -- report only happend > N consecutive times */
+    t_u8 data_high_snr_freq;
+    /* Link SNR threshold (dB) */
+    t_u16 link_snr;
+    /* Link SNR frequency */
+    t_u16 link_snr_freq;
+    /* Second minimum rate value as per the rate table below */
+    t_u16 link_rate;
+    /* Second minimum rate frequency */
+    t_u16 link_rate_freq;
+    /* Tx latency value (us) */
+    t_u16 link_tx_latency;
+    /* Tx latency frequency */
+    t_u16 link_tx_lantency_freq;
+    /* Number of pre missed beacons */
+    t_u8 pre_beacon_miss;
+} mlan_ds_subscribe_evt;
+/** Max OTP user data length */
+#define MAX_OTP_USER_DATA_LEN 252U
+
+/** Type definition of mlan_ds_misc_otp_user_data for MLAN_OID_MISC_OTP_USER_DATA */
+typedef struct _mlan_ds_misc_otp_user_data
+{
+    /** Reserved */
+    t_u16 reserved;
+    /** OTP user data length */
+    t_u16 user_data_length;
+    /** User data buffer */
+    t_u8 user_data[MAX_OTP_USER_DATA_LEN];
+} mlan_ds_misc_otp_user_data;
+
+/** mlan_ds_misc_pmfcfg structure */
+typedef struct _mlan_ds_misc_pmfcfg
+{
+    /** Management Frame Protection Capable */
+    t_u8 mfpc;
+    /** Management Frame Protection Required */
+    t_u8 mfpr;
+} mlan_ds_misc_pmfcfg;
+
+/** mlan_ds_misc_ed_mac_mode structure */
+typedef struct _mlan_ds_ed_mac_mode
+{
+    /** ED CTRL 2G */
+    t_u16 ed_ctrl_2g;
+    /** ED Offset 2G */
+    t_s16 ed_offset_2g;
+#if CONFIG_5GHz_SUPPORT
+    /** ED CTRL 5G */
+    t_u16 ed_ctrl_5g;
+    /** ED Offset 5G */
+    t_s16 ed_offset_5g;
+#endif
+} mlan_ds_misc_ed_mac_mode;
+
+#ifdef OTP_CHANINFO
+typedef struct _mlan_ds_misc_chnrgpwr_cfg
+{
+    /** length */
+    t_u16 length;
+    /** chnrgpwr buf */
+    t_u8 chnrgpwr_buf[2048];
+} mlan_ds_misc_chnrgpwr_cfg;
+#endif
+
+#if CONFIG_RF_TEST_MODE
+
+typedef enum _mlan_rf_test_mode
+{
+    MLAN_OID_MISC_RF_TEST_GENERIC              = 0x00200075,
+    MLAN_OID_MISC_RF_TEST_TX_CONT              = 0x00200076,
+    MLAN_OID_MISC_RF_TEST_TX_FRAME             = 0x00200077,
+    MLAN_OID_MISC_RF_TEST_HE_POWER             = 0X0020007F,
+    MLAN_OID_MISC_RF_TEST_CONFIG_TRIGGER_FRAME = 0x0020008C,
+} mlan_rf_test_mode;
+
+#define MFG_CMD_SET_TEST_MODE        1
+#define MFG_CMD_UNSET_TEST_MODE      0
+#define MFG_CMD_TX_ANT               0x1004
+#define MFG_CMD_RX_ANT               0x1005
+#define MFG_CMD_TX_CONT              0x1009
+#define MFG_CMD_RF_CHAN              0x100A
+#define MFG_CMD_CLR_RX_ERR           0x1010
+#define MFG_CMD_TX_FRAME             0x1021
+#define MFG_CMD_RFPWR                0x1033
+#define MFG_CMD_RF_BAND_AG           0x1034
+#define MFG_CMD_RF_CHANNELBW         0x1044
+#define MFG_CMD_RADIO_MODE_CFG       0x1211
+#define MFG_CMD_CONFIG_MAC_HE_TB_TX  0x110A
+#define MFG_CMD_CONFIG_TRIGGER_FRAME 0x110C
+#define MFG_CMD_OTP_MAC_ADD          0x108C
+#define MFG_CMD_OTP_CAL_DATA         0x121A
+
+/** Configuration for Manufacturing generic command */
+typedef MLAN_PACK_START struct _mlan_ds_mfg_cmd_generic_cfg
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** value 1 */
+    t_u32 data1;
+    /** value 2 */
+    t_u32 data2;
+    /** value 3 */
+    t_u32 data3;
+} MLAN_PACK_END mlan_ds_mfg_cmd_generic_cfg;
+
+/** Configuration for Manufacturing command Tx Frame */
+typedef MLAN_PACK_START struct _mlan_ds_mfg_cmd_tx_frame2
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable */
+    t_u32 enable;
+    /** data_rate */
+    t_u32 data_rate;
+    /** frame pattern */
+    t_u32 frame_pattern;
+    /** frame length */
+    t_u32 frame_length;
+    /** BSSID */
+    t_u8 bssid[MLAN_MAC_ADDR_LENGTH];
+    /** Adjust burst sifs */
+    t_u16 adjust_burst_sifs;
+    /** Burst sifs in us*/
+    t_u32 burst_sifs_in_us;
+    /** short preamble */
+    t_u32 short_preamble;
+    /** active sub channel */
+    t_u32 act_sub_ch;
+    /** short GI */
+    t_u32 short_gi;
+    /** Adv coding */
+    t_u32 adv_coding;
+    /** Tx beamforming */
+    t_u32 tx_bf;
+    /** HT Greenfield Mode*/
+    t_u32 gf_mode;
+    /** STBC */
+    t_u32 stbc;
+    /** power id */
+    t_u32 rsvd[1];
+    /**signal bw*/
+    t_u32 signal_bw;
+    /** NumPkt */
+    t_u32 NumPkt;
+    /** MaxPE */
+    t_u32 MaxPE;
+    /** BeamChange */
+    t_u32 BeamChange;
+    /** Dcm */
+    t_u32 Dcm;
+    /** Doppler */
+    t_u32 Doppler;
+    /** MidP */
+    t_u32 MidP;
+    /** QNum */
+    t_u32 QNum;
+} MLAN_PACK_END mlan_ds_mfg_cmd_tx_frame2;
+
+/** Configuration for Manufacturing command Tx Continuous */
+typedef MLAN_PACK_START struct _mlan_ds_mfg_cmd_tx_cont
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable Tx*/
+    t_u32 enable_tx;
+    /** Continuous Wave mode */
+    t_u32 cw_mode;
+    /** payload pattern */
+    t_u32 payload_pattern;
+    /** CS Mode */
+    t_u32 cs_mode;
+    /** active sub channel */
+    t_u32 act_sub_ch;
+    /** Tx rate */
+    t_u32 tx_rate;
+    /** power id */
+    t_u32 rsvd;
+} MLAN_PACK_END mlan_ds_mfg_cmd_tx_cont;
+
+typedef PACK_START struct _mlan_ds_mfg_Cmd_HE_TBTx_t
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** Enable Tx */
+    t_u16 enable;
+    /** Q num */
+    t_u16 qnum;
+    /** AID */
+    t_u16 aid;
+    /** AXQ Mu Timer */
+    t_u16 axq_mu_timer;
+    /** Tx Power */
+    t_s16 tx_power;
+} PACK_END mlan_ds_mfg_Cmd_HE_TBTx_t;
+
+typedef MLAN_PACK_START struct _mlan_ds_mfg_cmd_otp_mac_addr_rd_wr_t
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** Destination MAC Address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END mlan_ds_mfg_cmd_otp_mac_addr_rd_wr_t;
+
+#define CAL_DATA_LEN 2800
+typedef MLAN_PACK_START struct _mlan_ds_mfg_cmd_otp_cal_data_rd_wr_t
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** CAL Data write status */
+    t_u32 cal_data_status;
+    /** CAL Data Length*/
+    t_u32 cal_data_len;
+    /** Destination MAC Address */
+    t_u8 cal_data[CAL_DATA_LEN];
+} MLAN_PACK_END mlan_ds_mfg_cmd_otp_cal_data_rd_wr_t;
+
+typedef MLAN_PACK_START struct _mfg_cmd_IEEEtypes_HETrigComInfo_t
+{
+    t_u64 trigger_type : 4;
+    t_u64 ul_len : 12;
+    t_u64 more_tf : 1;
+    t_u64 cs_required : 1;
+    t_u64 ul_bw : 2;
+
+    t_u64 ltf_type : 2;
+    t_u64 ltf_mode : 1;
+    t_u64 ltf_symbol : 3;
+    t_u64 ul_stbc : 1;
+    t_u64 ldpc_ess : 1;
+
+    t_u64 ap_tx_pwr : 6;
+    t_u64 pre_fec_pad_fct : 2;
+    t_u64 pe_disambig : 1;
+    t_u64 spatial_reuse : 16;
+    t_u64 doppler : 1;
+    t_u64 he_sig2 : 9;
+    t_u64 reserved : 1;
+
+} MLAN_PACK_END mfg_cmd_IEEEtypes_HETrigComInfo_t;
+
+typedef MLAN_PACK_START struct _mfg_cmd_IEEEtypes_HETrigUserInfo_t
+{
+    t_u32 aid12 : 12;
+    t_u32 ru_alloc_reg : 1;
+    t_u32 ru_alloc : 7;
+    t_u32 ul_coding_type : 1;
+    t_u32 ul_mcs : 4;
+    t_u32 ul_dcm : 1;
+    t_u32 ss_alloc : 6;
+    t_u8 ul_target_rssi : 7;
+    t_u8 reserved : 1;
+} MLAN_PACK_END mfg_cmd_IEEEtypes_HETrigUserInfo_t;
+
+typedef MLAN_PACK_START struct _mfg_cmd_IEEETypes_BasicHETrigUserInfo_t
+{
+    t_u8 mpdu_mu_sf : 2;
+    t_u8 tid_al : 3;
+    t_u8 ac_pl : 1;
+    t_u8 pref_ac : 2;
+} MLAN_PACK_END mfg_cmd_IEEETypes_BasicHETrigUserInfo_t;
+
+typedef MLAN_PACK_START struct _mfg_cmd_IEEEtypes_FrameCtrl_t
+{
+    /** Protocol Version */
+    t_u8 protocol_version : 2;
+    /** Type */
+    t_u8 type : 2;
+    /** Sub Type */
+    t_u8 sub_type : 4;
+    /** To DS */
+    t_u8 to_ds : 1;
+    /** From DS */
+    t_u8 from_ds : 1;
+    /** More Frag */
+    t_u8 more_frag : 1;
+    /** Retry */
+    t_u8 retry : 1;
+    /** Power Mgmt */
+    t_u8 pwr_mgmt : 1;
+    /** More Data */
+    t_u8 more_data : 1;
+    /** Wep */
+    t_u8 wep : 1;
+    /** Order */
+    t_u8 order : 1;
+} MLAN_PACK_END mfg_cmd_IEEEtypes_FrameCtrl_t;
+
+typedef MLAN_PACK_START struct _mfg_Cmd_IEEEtypes_CtlBasicTrigHdr_t
+{
+    /** MFG command code */
+    t_u32 mfg_cmd;
+    /** Action */
+    t_u16 action;
+    /** Device ID */
+    t_u16 device_id;
+    /** MFG Error code */
+    t_u32 error;
+    /** enable Tx*/
+    t_u32 enable_tx;
+    /** enable Stand Alone HE TB */
+    t_u32 standalone_hetb;
+    /** Frame Control */
+    mfg_cmd_IEEEtypes_FrameCtrl_t frmCtl;
+    /** Duration */
+    t_u16 duration;
+    /** Destination MAC Address */
+    t_u8 dest_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Source MAC Address */
+    t_u8 src_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Common Info Field **/
+    mfg_cmd_IEEEtypes_HETrigComInfo_t trig_common_field;
+    /** User Info Field **/
+    mfg_cmd_IEEEtypes_HETrigUserInfo_t trig_user_info_field;
+    /** Trigger Dependent User Info Field **/
+    mfg_cmd_IEEETypes_BasicHETrigUserInfo_t basic_trig_user_info;
+} MLAN_PACK_END mfg_Cmd_IEEEtypes_CtlBasicTrigHdr_t;
+#endif
+
+#if CONFIG_MULTI_CHAN
+typedef MLAN_PACK_START struct _mlan_ds_multi_chan_cfg
+{
+    /** Channel Time */
+    t_u32 channel_time;
+    /** Buffer Weight */
+    t_u8 buffer_weight;
+    /** tlv len */
+    t_u16 tlv_len;
+    /** TLV buffer */
+    t_u8 tlv_buf[];
+} MLAN_PACK_END mlan_ds_multi_chan_cfg;
+
+typedef MLAN_PACK_START struct _mlan_ds_drcs_cfg
+{
+    /** Channel Index*/
+    t_u16 chan_idx;
+    /** Channel time (in TU) for chan_idx */
+    t_u8 chantime;
+    /** Channel swith time (in TU) for chan_idx */
+    t_u8 switchtime;
+    /** Undoze time (in TU) for chan_idx */
+    t_u8 undozetime;
+    /** Rx traffic control scheme when channel switch*/
+    /** only valid for GC/STA interface*/
+    t_u8 mode;
+} MLAN_PACK_END mlan_ds_drcs_cfg;
+#endif
+
+
+#if (CONFIG_GTK_REKEY_OFFLOAD)
+#define MLAN_KCK_LEN        16
+#define MLAN_KEK_LEN        16
+#define MLAN_REPLAY_CTR_LEN 8
+/** mlan_ds_misc_gtk_rekey_data */
+typedef struct _mlan_ds_misc_gtk_rekey_data
+{
+    /** key encryption key */
+    t_u8 kek[MLAN_KEK_LEN];
+    /** key confirmation key */
+    t_u8 kck[MLAN_KCK_LEN];
+    /** replay counter */
+    t_u8 replay_ctr[MLAN_REPLAY_CTR_LEN];
+} mlan_ds_misc_gtk_rekey_data;
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+typedef struct _mlan_ds_ind_rst_cfg
+{
+    /** Set or Get */
+    t_u16 action;
+    /** oob mode enable/ disable */
+    t_u8 ir_mode;
+    /** gpio pin */
+    t_u8 gpio_pin;
+} mlan_ds_ind_rst_cfg;
+#endif
+
+/** Type definition of mlan_ds_misc_cfg for MLAN_IOCTL_MISC_CFG */
+typedef struct _mlan_ds_misc_cfg
+{
+    /** Sub-command */
+    t_u32 sub_command;
+    /** Miscellaneous configuration parameter */
+    union
+    {
+        /** Generic IE for MLAN_OID_MISC_GEN_IE */
+        mlan_ds_misc_gen_ie gen_ie;
+        /** Region code for MLAN_OID_MISC_REGION */
+        t_u32 region_code;
+        /** Hostcmd for MLAN_OID_MISC_HOST_CMD */
+        mlan_ds_misc_cmd hostcmd;
+        /** System clock for MLAN_OID_MISC_SYS_CLOCK */
+        mlan_ds_misc_sys_clock sys_clock;
+#if CONFIG_WIFI_CLOCKSYNC
+        mlan_ds_gpio_tsf_latch gpio_tsf_latch_config;
+        mlan_ds_tsf_info tsf_info;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+        /** WWS set/get for MLAN_OID_MISC_WWS */
+        t_u32 wws_cfg;
+        /** Function init/shutdown for MLAN_OID_MISC_INIT_SHUTDOWN */
+        t_u32 func_init_shutdown;
+        /** Custom IE for MLAN_OID_MISC_CUSTOM_IE */
+        mlan_ds_misc_custom_ie cust_ie;
+        /** Tx data pause for MLAN_OID_MISC_TX_DATAPAUSE */
+        mlan_ds_misc_tx_datapause tx_datapause;
+        /** IP address configuration */
+        mlan_ds_misc_ipaddr_cfg ipaddr_cfg;
+        /** MAC control for MLAN_OID_MISC_MAC_CONTROL */
+        t_u32 mac_ctrl;
+        /** MEF configuration for MLAN_OID_MISC_MEF_CFG */
+        mlan_ds_misc_mef_cfg mef_cfg;
+        /** CFP code for MLAN_OID_MISC_CFP_CODE */
+        mlan_ds_misc_cfp_code cfp_code;
+        /** Country code for MLAN_OID_MISC_COUNTRY_CODE */
+        mlan_ds_misc_country_code country_code;
+        /** Thermal reading for MLAN_OID_MISC_THERMAL */
+        t_u32 thermal;
+        /** Mgmt subtype mask for MLAN_OID_MISC_RX_MGMT_IND */
+        t_u32 mgmt_subtype_mask;
+        /** subscribe event for MLAN_OID_MISC_SUBSCRIBE_EVENT */
+        mlan_ds_subscribe_evt subscribe_event;
+#ifdef DEBUG_LEVEL1
+        /** Driver debug bit masks */
+        t_u32 drvdbg;
+#endif
+
+        /** boot sleep enable or disable */
+        t_u16 boot_sleep;
+
+        /** Hotspot config param set */
+        t_u32 hotspot_cfg;
+        mlan_ds_misc_otp_user_data otp_user_data;
+#ifdef WLAN_LOW_POWER_ENABLE
+        t_u8 low_pwr_mode;
+#endif // WLAN_LOW_POWER_ENABLE
+#ifdef OTP_CHANINFO
+        /** Custom regulatory domain */
+        mlan_ds_custom_reg_domain custom_reg_domain;
+        mlan_ds_misc_chnrgpwr_cfg rgchnpwr_cfg;
+#endif
+#if CONFIG_RF_TEST_MODE
+        mlan_ds_mfg_cmd_generic_cfg mfg_generic_cfg;
+        mlan_ds_mfg_cmd_tx_frame2 mfg_tx_frame2;
+        mlan_ds_mfg_cmd_tx_cont mfg_tx_cont;
+        mlan_ds_mfg_Cmd_HE_TBTx_t mfg_he_power;
+        mfg_Cmd_IEEEtypes_CtlBasicTrigHdr_t mfg_tx_trigger_config;
+        mlan_ds_mfg_cmd_otp_mac_addr_rd_wr_t mfg_otp_mac_addr_rd_wr;
+        mlan_ds_mfg_cmd_otp_cal_data_rd_wr_t mfg_otp_cal_data_rd_wr;
+#endif
+#if CONFIG_MULTI_CHAN
+        /** Multi-channel config for MLAN_OID_MISC_MULTI_CHAN_CFG */
+        mlan_ds_multi_chan_cfg multi_chan_cfg;
+        /** Multi-channel policy for MLAN_OID_MISC_MULTI_CHAN_POLICY */
+        t_u16 multi_chan_policy;
+        /** channel drcs time slicing config for MLAN_OID_MISC_DRCS_CFG
+         */
+        mlan_ds_drcs_cfg drcs_cfg[2];
+#endif
+#if CONFIG_ECSA
+        mlan_ds_bw_chan_oper bw_chan_oper;
+#endif
+        mlan_embedded_dhcp_config embedded_dhcp_config;
+#if CONFIG_GTK_REKEY_OFFLOAD
+        /** GTK rekey data */
+        mlan_ds_misc_gtk_rekey_data gtk_rekey;
+#endif
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+        mlan_ds_ind_rst_cfg ind_rst_cfg;
+#endif
+    } param;
+} mlan_ds_misc_cfg, *pmlan_ds_misc_cfg;
+
+/** mlan ioctl */
+MLAN_API mlan_status mlan_ioctl(IN t_void *pmlan_adapter, IN pmlan_ioctl_req pioctl_req);
+
+#endif /* !_MLAN_IOCTL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_join.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_join.h
new file mode 100644
index 0000000000..8f3fa76ba9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_join.h
@@ -0,0 +1,30 @@
+/** @file mlan_join.h
+ *
+ *  @brief This file defines the interface for the WLAN infrastructure
+ *  and adhoc join routines.
+ *
+ *  Driver interface functions and type declarations for the join module
+ *  implemented in mlan_join.c.  Process all start/join requests for
+ *  both adhoc and infrastructure networks
+ *
+ *  Copyright 2008-2021, 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/13/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_JOIN_H_
+#define _MLAN_JOIN_H_
+
+/** Size of buffer allocated to store the association response from firmware */
+#define MRVDRV_ASSOC_RSP_BUF_SIZE 500
+
+/** Size of buffer allocated to store IEs passed to firmware in the assoc req */
+#define MRVDRV_GENIE_BUF_SIZE 256
+
+#endif /* _MLAN_JOIN_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_main.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_main.h
new file mode 100644
index 0000000000..1b489216d8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_main.h
@@ -0,0 +1,3177 @@
+/** @file mlan_main.h
+ *
+ *  @brief This file defines the private and adapter data
+ *  structures and declares global function prototypes used
+ *  in MLAN module.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/13/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_MAIN_H_
+#define _MLAN_MAIN_H_
+#ifndef RW610
+#include "mlan_main_defs.h"
+#endif
+#ifdef DEBUG_LEVEL1
+extern t_void (*print_callback)(IN t_void *pmoal_handle, IN t_u32 level, IN t_s8 *pformat, IN...);
+
+extern mlan_status (*get_sys_time_callback)(IN t_void *pmoal_handle, OUT t_u32 *psec, OUT t_u32 *pusec);
+
+extern t_u32 drvdbg;
+
+#ifdef DEBUG_LEVEL2
+#define PRINTM_MINFO(msg...)                      \
+    do                                            \
+    {                                             \
+        if ((drvdbg & MINFO) && (print_callback)) \
+            print_callback(MNULL, MINFO, msg);    \
+    } while (false)
+#define PRINTM_MWARN(msg...)                      \
+    do                                            \
+    {                                             \
+        if ((drvdbg & MWARN) && (print_callback)) \
+            print_callback(MNULL, MWARN, msg);    \
+    } while (false)
+#define PRINTM_MENTRY(msg...)                      \
+    do                                             \
+    {                                              \
+        if ((drvdbg & MENTRY) && (print_callback)) \
+            print_callback(MNULL, MENTRY, msg);    \
+    } while (false)
+#define PRINTM_GET_SYS_TIME(level, psec, pusec)          \
+    do                                                   \
+    {                                                    \
+        if ((level & drvdbg) && (get_sys_time_callback)) \
+            get_sys_time_callback(MNULL, psec, pusec);   \
+    } while (false)
+
+/** Hexdump for level-2 debugging */
+#define HEXDUMP(x, y, z)                                        \
+    do                                                          \
+    {                                                           \
+        if ((drvdbg & (MHEX_DUMP | MINFO)) && (print_callback)) \
+            print_callback(MNULL, MHEX_DUMP | MINFO, x, y, z);  \
+    } while (false)
+
+#else
+
+#define PRINTM_MINFO(msg...) \
+    do                       \
+    {                        \
+    } while (false)
+#define PRINTM_MWARN(msg...) \
+    do                       \
+    {                        \
+    } while (false)
+#define PRINTM_MENTRY(msg...) \
+    do                        \
+    {                         \
+    } while (false)
+
+#define PRINTM_GET_SYS_TIME(level, psec, pusec)                                                  \
+    do                                                                                           \
+    {                                                                                            \
+        if ((level & drvdbg) && (get_sys_time_callback) && (level != MINFO) && (level != MWARN)) \
+            get_sys_time_callback(MNULL, psec, pusec);                                           \
+    } while (false)
+
+/** Hexdump for debugging */
+#define HEXDUMP(x, y, z) \
+    do                   \
+    {                    \
+    } while (false)
+
+#endif /* DEBUG_LEVEL2 */
+
+#define PRINTM_MFW_D(msg...)                      \
+    do                                            \
+    {                                             \
+        if ((drvdbg & MFW_D) && (print_callback)) \
+            print_callback(MNULL, MFW_D, msg);    \
+    } while (false)
+#define PRINTM_MCMD_D(msg...)                      \
+    do                                             \
+    {                                              \
+        if ((drvdbg & MCMD_D) && (print_callback)) \
+            print_callback(MNULL, MCMD_D, msg);    \
+    } while (false)
+#define PRINTM_MDAT_D(msg...)                      \
+    do                                             \
+    {                                              \
+        if ((drvdbg & MDAT_D) && (print_callback)) \
+            print_callback(MNULL, MDAT_D, msg);    \
+    } while (false)
+#define PRINTM_MIF_D(msg...)                      \
+    do                                            \
+    {                                             \
+        if ((drvdbg & MIF_D) && (print_callback)) \
+            print_callback(MNULL, MIF_D, msg);    \
+    } while (false)
+
+#define PRINTM_MIOCTL(msg...)                      \
+    do                                             \
+    {                                              \
+        if ((drvdbg & MIOCTL) && (print_callback)) \
+            print_callback(MNULL, MIOCTL, msg);    \
+    } while (false)
+#define PRINTM_MINTR(msg...)                      \
+    do                                            \
+    {                                             \
+        if ((drvdbg & MINTR) && (print_callback)) \
+            print_callback(MNULL, MINTR, msg);    \
+    } while (false)
+#define PRINTM_MEVENT(msg...)                      \
+    do                                             \
+    {                                              \
+        if ((drvdbg & MEVENT) && (print_callback)) \
+            print_callback(MNULL, MEVENT, msg);    \
+    } while (false)
+#define PRINTM_MCMND(msg...)                      \
+    do                                            \
+    {                                             \
+        if ((drvdbg & MCMND) && (print_callback)) \
+            print_callback(MNULL, MCMND, msg);    \
+    } while (false)
+#define PRINTM_MDATA(msg...)                      \
+    do                                            \
+    {                                             \
+        if ((drvdbg & MDATA) && (print_callback)) \
+            print_callback(MNULL, MDATA, msg);    \
+    } while (false)
+#define PRINTM_MERROR(msg...)                      \
+    do                                             \
+    {                                              \
+        if ((drvdbg & MERROR) && (print_callback)) \
+            print_callback(MNULL, MERROR, msg);    \
+    } while (false)
+#define PRINTM_MFATAL(msg...)                      \
+    do                                             \
+    {                                              \
+        if ((drvdbg & MFATAL) && (print_callback)) \
+            print_callback(MNULL, MFATAL, msg);    \
+    } while (false)
+#define PRINTM_MMSG(msg...)                      \
+    do                                           \
+    {                                            \
+        if ((drvdbg & MMSG) && (print_callback)) \
+            print_callback(MNULL, MMSG, msg);    \
+    } while (false)
+
+#define PRINTM(level, msg...) PRINTM_##level(msg)
+
+/** Log debug message */
+#ifdef __GNUC__
+#define PRINTM_NETINTF(level, pmpriv)                                                                               \
+    do                                                                                                              \
+    {                                                                                                               \
+        if ((drvdbg & level) && pmpriv && pmpriv->adapter->callbacks.moal_print_netintf)                            \
+            pmpriv->adapter->callbacks.moal_print_netintf(pmpriv->adapter->pmoal_handle, pmpriv->bss_index, level); \
+    } while (false)
+#endif /* __GNUC__ */
+
+/** Max hex dump data length */
+#define MAX_DATA_DUMP_LEN 64
+
+/** Debug hexdump for level-1 debugging */
+#define DBG_HEXDUMP(level, x, y, z)                            \
+    do                                                         \
+    {                                                          \
+        if ((drvdbg & level) && print_callback)                \
+            print_callback(MNULL, MHEX_DUMP | level, x, y, z); \
+    } while (false)
+
+#else /* DEBUG_LEVEL1 */
+
+#define PRINTM(level, msg...) \
+    do                        \
+    {                         \
+    } while ((bool)false)
+
+#define PRINTM_NETINTF(level, pmpriv) \
+    do                                \
+    {                                 \
+    } while ((bool)false)
+
+/** Debug hexdump for level-1 debugging */
+#define DBG_HEXDUMP(level, x, y, z) \
+    do                              \
+    {                               \
+    } while ((bool)false)
+
+/** Hexdump for debugging */
+#define HEXDUMP(x, y, z) \
+    do                   \
+    {                    \
+    } while ((bool)false)
+
+#define PRINTM_GET_SYS_TIME(level, psec, pusec) \
+    do                                          \
+    {                                           \
+    } while ((bool)false)
+
+#endif /* DEBUG_LEVEL1 */
+
+/** Log entry point for debugging */
+#define ENTER()                                      \
+    do                                               \
+    {                                                \
+        PRINTM(MENTRY, "Enter: %s\n", __FUNCTION__); \
+    } while ((bool)false)
+
+/** Log exit point for debugging */
+#define LEAVE()                                      \
+    do                                               \
+    {                                                \
+        PRINTM(MENTRY, "Leave: %s\n", __FUNCTION__); \
+    } while ((bool)false)
+
+/** Find minimum */
+#ifndef MIN
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+/** Find maximum */
+#ifndef MAX
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+
+#if 0
+#ifdef memset
+#undef memset
+#endif
+/** Memset routine */
+#define memset(adapter, s, c, len) adapter->callbacks.moal_memset(adapter->pmoal_handle, s, c, len)
+
+#ifdef memmove
+#undef memmove
+#endif
+/** Memmove routine */
+#define memmove(adapter, dest, src, len) adapter->callbacks.moal_memmove(adapter->pmoal_handle, dest, src, len)
+
+#ifdef memcpy
+#undef memcpy
+#endif
+/** Memcpy routine */
+#define memcpy(adapter, to, from, len) adapter->callbacks.moal_memcpy(adapter->pmoal_handle, to, from, len)
+
+#ifdef memcmp
+#undef memcmp
+#endif
+/** Memcmp routine */
+#define memcmp(adapter, s1, s2, len) adapter->callbacks.moal_memcmp(adapter->pmoal_handle, s1, s2, len)
+#endif /* 0 */
+
+/* memcpy_ext rountine */
+#define memcpy_ext(adapter, to, from, len, size) \
+    (adapter->callbacks.moal_memcpy_ext(adapter->pmoal_handle, to, from, len, size))
+
+/** Find number of elements */
+#ifndef NELEMENTS
+#define NELEMENTS(x) (sizeof(x) / sizeof(x[0]))
+#endif
+
+/** SWAP: swap t_u8 */
+#define SWAP_U8(a, b) \
+    {                 \
+        t_u8 t;       \
+        t = a;        \
+        a = b;        \
+        b = t;        \
+    }
+
+/** SWAP: swap t_u8 */
+#define SWAP_U16(a, b) \
+    {                  \
+        t_u16 t;       \
+        t = a;         \
+        a = b;         \
+        b = t;         \
+    }
+
+/** MLAN MNULL pointer */
+#ifndef MNULL
+#define MNULL ((void *)0)
+#endif
+
+/** 16 bits byte swap */
+#define swap_byte_16(x) ((t_u16)((((t_u16)(x)&0x00ffU) << 8) | (((t_u16)(x)&0xff00U) >> 8)))
+
+/** 32 bits byte swap */
+#define swap_byte_32(x)                                                                                                \
+    ((t_u32)((((t_u32)(x)&0x000000ffUL) << 24) | (((t_u32)(x)&0x0000ff00UL) << 8) | (((t_u32)(x)&0x00ff0000UL) >> 8) | \
+             (((t_u32)(x)&0xff000000UL) >> 24)))
+
+/** 64 bits byte swap */
+#define swap_byte_64(x)                                                                                              \
+    ((t_u64)((t_u64)(((t_u64)(x)&0x00000000000000ffULL) << 56) | (t_u64)(((t_u64)(x)&0x000000000000ff00ULL) << 40) | \
+             (t_u64)(((t_u64)(x)&0x0000000000ff0000ULL) << 24) | (t_u64)(((t_u64)(x)&0x00000000ff000000ULL) << 8) |  \
+             (t_u64)(((t_u64)(x)&0x000000ff00000000ULL) >> 8) | (t_u64)(((t_u64)(x)&0x0000ff0000000000ULL) >> 24) |  \
+             (t_u64)(((t_u64)(x)&0x00ff000000000000ULL) >> 40) | (t_u64)(((t_u64)(x)&0xff00000000000000ULL) >> 56)))
+
+/** Convert ulong n/w to host */
+#define mlan_ntohl(x)       swap_byte_32(x)
+/** Convert host ulong to n/w */
+#define mlan_htonl(x)       swap_byte_32(x)
+/** Convert n/w to host */
+#define mlan_ntohs(x)       swap_byte_16(x)
+/** Convert host to n/w */
+#define mlan_htons(x)       swap_byte_16(x)
+/** Do nothing */
+#define wlan_le16_to_cpu(x) x
+/** Do nothing */
+#define wlan_le32_to_cpu(x) x
+/** Do nothing */
+#define wlan_le64_to_cpu(x) x
+/** Do nothing */
+#define wlan_cpu_to_le16(x) x
+/** Do nothing */
+#define wlan_cpu_to_le32(x) x
+/** Do nothing */
+#define wlan_cpu_to_le64(x) x
+
+/** Convert TxPD to little endian format from CPU format */
+#define endian_convert_TxPD(x) \
+    do                         \
+    {                          \
+    } while (false)
+/** Convert RxPD from little endian format to CPU format */
+#define endian_convert_RxPD(x) \
+    do                         \
+    {                          \
+    } while (false)
+
+/** Global moal_assert_callback */
+extern t_void (*assert_callback)(IN t_void *pmoal_handle, IN t_u32 cond);
+
+/** Assertion */
+#define MASSERT(cond)                                                   \
+    do                                                                  \
+    {                                                                   \
+        if (!(cond))                                                    \
+        {                                                               \
+            PRINTM(MFATAL, "ASSERT: %s: %i\n", __FUNCTION__, __LINE__); \
+            if (assert_callback != NULL)                                \
+            {                                                           \
+                assert_callback(MNULL, (t_ptr)(cond));                  \
+            }                                                           \
+            else                                                        \
+            {                                                           \
+                do                                                      \
+                {                                                       \
+                } while (true);                                         \
+            }                                                           \
+        }                                                               \
+    } while (false)
+
+/** Upload size */
+#define WLAN_UPLD_SIZE (2312)
+
+/** Maximum event buffer size */
+#define MAX_EVENT_SIZE 1024
+
+/** Maximum event buffer size */
+#define MAX_P2P_EVENT_SIZE 512
+
+/** Maximum buffer size for ARP filter */
+#define ARP_FILTER_MAX_BUF_SIZE 68
+
+/** 60 seconds */
+#define MRVDRV_TIMER_60S 60000
+/** 10 seconds */
+#define MRVDRV_TIMER_10S 10000U
+/** 5 seconds */
+#define MRVDRV_TIMER_5S 5000
+/** 1 second */
+#define MRVDRV_TIMER_1S 1000U
+
+/** Maximum size of multicast list */
+#define MRVDRV_MAX_MULTICAST_LIST_SIZE 32
+/** Maximum size of channel */
+#define MRVDRV_MAX_CHANNEL_SIZE 14
+/** Maximum length of SSID */
+#define MRVDRV_MAX_SSID_LENGTH 32U
+/** WEP list macros & data structures */
+/** Size of key buffer in bytes */
+#define MRVL_KEY_BUFFER_SIZE_IN_BYTE 16
+/** Maximum length of WPA key */
+#define MRVL_MAX_KEY_WPA_KEY_LENGTH 32
+
+/** Default listen interval */
+/* wmsdk: Changed to keep same as was in legacy */
+#define MLAN_DEFAULT_LISTEN_INTERVAL 10
+
+/** Maximum number of region codes */
+#define MRVDRV_MAX_REGION_CODE 10U
+
+/** Maximum number of CFP codes for BG */
+#define MRVDRV_MAX_CFP_CODE_BG 0
+/** Maximum number of CFP codes for A */
+#define MRVDRV_MAX_CFP_CODE_A 5
+
+#ifdef RW610
+/** Default region code */
+#define MRVDRV_DEFAULT_REGION_CODE 0x10
+#else
+/** Default region code */
+#define MRVDRV_DEFAULT_REGION_CODE 0x00
+#endif
+
+#ifdef RW610
+/** Default country code */
+#define MRVDRV_DEFAULT_COUNTRY_CODE "US"
+#else
+/** Default country code */
+#define MRVDRV_DEFAULT_COUNTRY_CODE "WW"
+#endif
+
+/** Japan country code */
+#define COUNTRY_CODE_JP_40 0x40
+/** Japan special country code */
+#define COUNTRY_CODE_JP_FF 0xFF
+
+/** Default factor for calculating beacon average */
+#define DEFAULT_BCN_AVG_FACTOR 8
+/** Default factor for calculating data average */
+#define DEFAULT_DATA_AVG_FACTOR 8
+
+/** The first valid channel for use */
+#define FIRST_VALID_CHANNEL 0xffU
+/** Default Ad-Hoc channel */
+#define DEFAULT_AD_HOC_CHANNEL 6
+/** Default Ad-Hoc channel A */
+#define DEFAULT_AD_HOC_CHANNEL_A 36
+
+/** Number of WEP keys */
+/* fixme: This param has been set to 1 as it is seen in legacy code */
+/* that only one set is used. If needed could be increased upto 4 */
+#define MRVL_NUM_WEP_KEY (1U) /* 4 */
+
+/** Default multiple DTIM */
+#define MRVDRV_DEFAULT_MULTIPLE_DTIM 1
+
+/** Default beacon missing timeout */
+#define DEFAULT_BCN_MISS_TIMEOUT 5
+
+#if CONFIG_EXT_SCAN_SUPPORT
+/** Maximum buffer space for beacons retrieved from scan responses */
+#define MAX_SCAN_BEACON_BUFFER 49152
+#else
+#define MAX_SCAN_BEACON_BUFFER 16384
+#endif
+/** Default buffer space for beacons retrieved from scan responses */
+#define DEFAULT_SCAN_BEACON_BUFFER 4096
+
+#ifdef RW610
+#define DEFAULT_11N_TX_BF_CAP 0x19870408
+#endif
+
+/**
+ * @brief Buffer pad space for newly allocated beacons/probe responses
+ *
+ * Beacons are typically 6 bytes longer than an equivalent probe response.
+ *  For each scan response stored, allocate an extra byte pad at the end to
+ *  allow easy expansion to store a beacon in the same memory a probe response
+ *  previously contained
+ */
+#define SCAN_BEACON_ENTRY_PAD 6
+
+/** Scan time specified in the channel TLV for each channel for passive scans */
+/* wmsdk: Changed this so that UAP connectivity is not lost
+   for more than acceptable value to all known clients.
+   The downside is that some clients whose beacon interval
+   is more than 100mS and does not coincide with uAP
+   passive scan duration will not be listed in the scan */
+#define MRVDRV_PASSIVE_SCAN_CHAN_TIME 100 /* 200 */
+
+/** Scan time specified in the channel TLV for each channel for active scans */
+/* wmsdk: Note: Modified this to keep same as what was in legacy code. */
+#define MRVDRV_ACTIVE_SCAN_CHAN_TIME 100 /* 200 */
+
+/** Scan time specified in the channel TLV for each channel for specific scans */
+#define MRVDRV_SPECIFIC_SCAN_CHAN_TIME 110
+
+/**
+ * Max total scan time in milliseconds
+ * The total scan time should be less than scan command timeout value (20s)
+ */
+#define MRVDRV_MAX_TOTAL_SCAN_TIME (MRVDRV_TIMER_10S * 3U)
+
+/** Offset for GTK as it has version to skip past for GTK */
+#define RSN_GTK_OUI_OFFSET 2
+
+/** If OUI is not found */
+#define MLAN_OUI_NOT_PRESENT 0
+/** If OUI is found */
+#define MLAN_OUI_PRESENT 1
+
+/** RF antenna selection */
+#define RF_ANTENNA_MASK(n) ((1 << (n)) - 1)
+/** RF antenna auto select */
+#define RF_ANTENNA_AUTO 0xFFFF
+
+/** Is cmd_resp, event or data packet received? */
+#define IS_CARD_RX_RCVD(adapter) (adapter->cmd_resp_received || adapter->event_received || adapter->data_received)
+
+/** Type command */
+#define MLAN_TYPE_CMD 1U
+/** Type data */
+#define MLAN_TYPE_DATA 0U
+/** Type event */
+#define MLAN_TYPE_EVENT 3U
+#if CONFIG_FW_VDLL
+/** Type vdll */
+#define MLAN_TYPE_VDLL 4U
+#endif
+/** Type null data */
+#define MLAN_TYPE_NULL_DATA 4
+
+/** Type bypass data */
+#define MLAN_TYPE_BYPASS_DATA 5
+
+#if CONFIG_RX_ABORT_CFG
+/** Data structure of Rx abort configuration */
+typedef struct
+{
+    /** Enable/Disable Rx abort config */
+    t_u8 enable;
+    /** Rx weak RSSI pkt threshold */
+    int rssi_threshold;
+} rx_abort_cfg_t;
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+/** Data structure of Rx abort configuration */
+typedef struct
+{
+    /** Enable/disable dyn rx abort on weak pkt rssi */
+    int enable;
+    /** specify rssi margin */
+    int rssi_margin;
+    /** specify ceil rssi threshold */
+    int ceil_rssi_threshold;
+    /** specify floor rssi threshold */
+    int floor_rssi_threshold;
+    /** current dynamic rssi threshold */
+    int current_dynamic_rssi_threshold;
+    /** rssi config: default or user configured */
+    int rssi_default_config;
+    /** EDMAC status */
+    int edmac_enable;
+} rx_abort_cfg_ext_t;
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+typedef struct
+{
+    /** cck desense mode: 0:disable 1:normal 2:dynamic */
+    t_u16 mode;
+    /** specify rssi margin */
+    int margin;
+    /** specify ceil rssi threshold */
+    int ceil_thresh;
+    /** cck desense "on" interval count */
+    int num_on_intervals;
+    /** cck desense "off" interval count */
+    int num_off_intervals;
+} cck_desense_cfg_t;
+#endif
+
+
+
+/** High threshold at which to start drop packets */
+#define RX_HIGH_THRESHOLD 1024
+/** Medium threshold at which to disable Rx BA */
+#define RX_MED_THRESHOLD 256
+/** Low threshold to allow Rx BA */
+#define RX_LOW_THRESHOLD 128
+
+/** Debug command number */
+#define DBG_CMD_NUM 5
+
+/** Hotspot status enable */
+#define HOTSPOT_ENABLED MTRUE
+/** Hotspot status disable */
+#define HOTSPOT_DISABLED MFALSE
+/** inteworking indication in extended capa IE */
+#define HOTSPOT_ENABLE_INTERWORKING_IND MBIT(0)
+/** TDLS indication in extended capa IE */
+#define HOTSPOT_ENABLE_TDLS_IND MBIT(1)
+
+#define MLAN_SET_BIT_U64(x, val)   ((x) |= (1ULL << (val)))
+#define MLAN_SET_BIT(x, val)       ((x) |= (1U << (val)))
+#define MLAN_CLEAR_BIT_U64(x, val) ((x) &= ~(1ULL << (val)))
+
+/** scan GAP value is optional */
+#define GAP_FLAG_OPTIONAL MBIT(15)
+
+/** Info for debug purpose */
+typedef struct _wlan_dbg
+{
+    /** Number of host to card command failures */
+    t_u32 num_cmd_host_to_card_failure;
+    /** Number of host to card sleep confirm failures */
+    t_u32 num_cmd_sleep_cfm_host_to_card_failure;
+    /** Number of host to card Tx failures */
+    t_u32 num_tx_host_to_card_failure;
+    /** Number of card to host command/event failures */
+    t_u32 num_cmdevt_card_to_host_failure;
+    /** Number of card to host Rx failures */
+    t_u32 num_rx_card_to_host_failure;
+    /** Number of interrupt read failures */
+    t_u32 num_int_read_failure;
+    /** Last interrupt status */
+    t_u32 last_int_status;
+    /** Number of deauthentication events */
+    t_u32 num_event_deauth;
+    /** Number of disassosiation events */
+    t_u32 num_event_disassoc;
+    /** Number of link lost events */
+    t_u32 num_event_link_lost;
+    /** Number of deauthentication commands */
+    t_u32 num_cmd_deauth;
+    /** Number of association comamnd successes */
+    t_u32 num_cmd_assoc_success;
+    /** Number of association command failures */
+    t_u32 num_cmd_assoc_failure;
+    /** Number of Tx timeouts */
+    t_u32 num_tx_timeout;
+    /** Number of command timeouts */
+    t_u32 num_cmd_timeout;
+    /** Timeout command ID */
+    t_u16 timeout_cmd_id;
+    /** Timeout command action */
+    t_u16 timeout_cmd_act;
+    /** List of last command IDs */
+    t_u16 last_cmd_id[DBG_CMD_NUM];
+    /** List of last command actions */
+    t_u16 last_cmd_act[DBG_CMD_NUM];
+    /** Last command index */
+    t_u16 last_cmd_index;
+    /** List of last command response IDs */
+    t_u16 last_cmd_resp_id[DBG_CMD_NUM];
+    /** Last command response index */
+    t_u16 last_cmd_resp_index;
+    /** List of last events */
+    t_u16 last_event[DBG_CMD_NUM];
+    /** Last event index */
+    t_u16 last_event_index;
+} wlan_dbg;
+
+#if CONFIG_RF_TEST_MODE
+#define MFG_CMD_SET_TEST_MODE        1
+#define MFG_CMD_UNSET_TEST_MODE      0
+#define MFG_CMD_TX_ANT               0x1004
+#define MFG_CMD_RX_ANT               0x1005
+#define MFG_CMD_TX_CONT              0x1009
+#define MFG_CMD_RF_CHAN              0x100A
+#define MFG_CMD_CLR_RX_ERR           0x1010
+#define MFG_CMD_TX_FRAME             0x1021
+#define MFG_CMD_RF_BAND_AG           0x1034
+#define MFG_CMD_RF_CHANNELBW         0x1044
+#define MFG_CMD_RADIO_MODE_CFG       0x1211
+#define MFG_CMD_CONFIG_MAC_HE_TB_TX  0x110A
+#define MFG_CMD_CONFIG_TRIGGER_FRAME 0x110C
+#define MFG_CMD_OTP_MAC_ADD          0x108C
+#define MFG_CMD_OTP_CAL_DATA         0x121A
+#endif
+
+/** Hardware status codes */
+typedef enum _WLAN_HARDWARE_STATUS
+{
+    WlanHardwareStatusReady,
+    WlanHardwareStatusInitializing,
+    WlanHardwareStatusInitdone,
+    WlanHardwareStatusReset,
+    WlanHardwareStatusClosing,
+    WlanHardwareStatusNotReady
+} WLAN_HARDWARE_STATUS;
+
+/** WLAN_802_11_POWER_MODE */
+typedef enum _WLAN_802_11_POWER_MODE
+{
+    Wlan802_11PowerModeCAM,
+    Wlan802_11PowerModePSP
+} WLAN_802_11_POWER_MODE;
+
+/** Ethernet frame header */
+typedef MLAN_PACK_START struct _eth_hdr
+{
+    /** destination eth addr */
+    t_u8 dest_addr[MLAN_MAC_ADDR_LENGTH];
+    /** source ether addr */
+    t_u8 src_addr[MLAN_MAC_ADDR_LENGTH];
+    /** packet type ID field */
+    t_u16 h_proto;
+} MLAN_PACK_END eth_hdr;
+
+/** Ethernet LLC frame header */
+typedef MLAN_PACK_START struct _eth_llc_hdr
+{
+    /* destination SAP */
+    t_u8 dsap;
+    /* source SAP */
+    t_u8 ssap;
+    /* LLC control field */
+    t_u8 llc;
+    /* protocol id */
+    t_u8 protid[3];
+    /* ether type field */
+    t_u16 type;
+} MLAN_PACK_END eth_llc_hdr;
+
+/* The IPv4 header */
+typedef MLAN_PACK_START struct _ip_hdr
+{
+    /* header length */
+    t_u8 ihl : 4;
+    /* version */
+    t_u8 _version : 4;
+    /* type of service */
+    t_u8 _tos;
+    /* total length */
+    t_u16 tot_len;
+    /* identification */
+    t_u16 _id;
+    /* fragment offset field */
+    t_u16 doff;
+    /* time to live */
+    t_u8 _ttl;
+    /* protocol*/
+    t_u8 protocol;
+    /* checksum */
+    t_u16 _chksum;
+    /* source and destination IP addresses */
+    t_u32 src;
+    t_u32 dest;
+} MLAN_PACK_END ip_hdr;
+
+/** TCP HDR flags */
+typedef MLAN_PACK_START struct _tcp_hdr_flags_t
+{
+    t_u16 res1 : 4;
+    t_u16 doff : 4;
+    t_u16 fin : 1;
+    t_u16 syn : 1;
+    t_u16 rst : 1;
+    t_u16 psh : 1;
+    t_u16 ack : 1;
+    t_u16 urg : 1;
+    t_u16 ece : 1;
+    t_u16 cwr : 1;
+} MLAN_PACK_END tcp_hdr_flags_t;
+
+typedef MLAN_PACK_START struct _tcp_hdr
+{
+    t_u16 src;
+    t_u16 dest;
+    t_u32 seqno;
+    t_u32 ackno;
+    tcp_hdr_flags_t _hdrlen_rsvd_flags;
+    t_u16 wnd;
+    t_u16 chksum;
+    t_u16 urgp;
+} MLAN_PACK_END tcp_hdr;
+
+/** tx param */
+typedef struct _mlan_tx_param
+{
+    /** next packet length */
+    t_u32 next_pkt_len;
+} mlan_tx_param;
+
+#if 0
+/** PS_STATE */
+typedef enum _PS_STATE
+{
+    PS_STATE_AWAKE,
+    PS_STATE_PRE_SLEEP,
+    PS_STATE_SLEEP_CFM,
+    PS_STATE_SLEEP
+} PS_STATE;
+#endif
+
+/** Minimum flush timer for win size of 1 is 50 ms */
+#define MIN_FLUSH_TIMER_MS 50U
+/** Tx BA stream table */
+typedef struct _TxBAStreamTbl TxBAStreamTbl;
+
+/** Add BA parameter data structure */
+typedef struct
+{
+    /** Window size for initiator */
+    t_u32 tx_win_size;
+    /** Window size for receiver */
+    t_u32 rx_win_size;
+    /** Block ack timeout */
+    t_u32 timeout;
+    /** amsdu support for ADDBA request */
+    t_u8 tx_amsdu;
+    /** amsdu support for ADDBA response */
+    t_u8 rx_amsdu;
+} add_ba_param_t;
+
+/** Tx aggregation data structure */
+typedef struct _txAggr_t
+{
+    /** AMPDU user */
+    t_u8 ampdu_user;
+    /** AMPDU AP */
+    t_u8 ampdu_ap;
+    /** AMSDU */
+    t_u8 amsdu;
+#if CONFIG_AMSDU_IN_AMPDU
+    /** peer AMSDU */
+    t_u8 amsdu_peer;
+#endif
+    /** TX packet cnt */
+    t_u32 txpkt_cnt;
+    /** TX BA threshold */
+    t_u32 txba_thresh;
+} tx_aggr_t;
+
+/** RA list table */
+typedef struct _raListTbl raListTbl;
+
+/** RA list table */
+struct _raListTbl
+{
+    /** Pointer to previous node */
+    raListTbl *pprev;
+    /** Pointer to next node */
+    raListTbl *pnext;
+    /** Buffer list head */
+    mlan_list_head buf_head;
+    /** RA list buffer */
+    t_u8 ra[MLAN_MAC_ADDR_LENGTH];
+    /** total packets in RA list */
+    t_u16 total_pkts;
+    /** packets received */
+    t_u16 packet_count;
+    /** packet count threshold to setup BA */
+    t_u8 ba_packet_threshold;
+    /** is 11n enabled */
+    t_u8 is_11n_enabled;
+    /** max amsdu size */
+    t_u16 max_amsdu;
+    /** tx_pause flag */
+    t_u8 tx_pause;
+#if CONFIG_WMM
+    /** drop packet count  */
+    t_u16 drop_count;
+#endif
+};
+
+/** TID table */
+typedef struct _tidTbl
+{
+    /** RA list head */
+    mlan_list_head ra_list;
+    /** Current RA list */
+    raListTbl *ra_list_curr;
+} tid_tbl_t;
+
+/** Highest priority setting for a packet (uses voice AC) */
+#define WMM_HIGHEST_PRIORITY 7
+/** Highest priority TID  */
+#define HIGH_PRIO_TID 7
+/** Lowest priority TID  */
+#define LOW_PRIO_TID 0
+/** No packet priority (< lowest) */
+#define NO_PKT_PRIO_TID -1
+
+/** Struct of WMM DESC */
+typedef struct _wmm_desc
+{
+    /** TID table */
+    tid_tbl_t tid_tbl_ptr[MAX_NUM_TID];
+    /** Packets out */
+    t_u32 packets_out[MAX_NUM_TID];
+    /** Packets queued */
+    t_u32 pkts_queued[MAX_NUM_TID];
+    /** Spin lock to protect ra_list */
+    t_void *ra_list_spinlock;
+
+    /** AC status */
+    WmmAcStatus_t ac_status[MAX_AC_QUEUES];
+    /** AC downgraded values */
+    mlan_wmm_ac_e ac_down_graded_vals[MAX_AC_QUEUES];
+
+    /** Max driver packet delay sent to the firmware for expiry eval */
+    t_u32 drv_pkt_delay_max;
+
+    /** WMM queue priority table */
+    t_u8 queue_priority[MAX_AC_QUEUES];
+    /** User priority packet transmission control */
+    t_u32 user_pri_pkt_tx_ctrl[WMM_HIGHEST_PRIORITY + 1]; /* UP: 0 to 7 */
+
+    /** Number of transmit packets queued */
+    mlan_scalar tx_pkts_queued;
+    /** Tracks highest priority with a packet queued */
+    mlan_scalar highest_queued_prio;
+#if (CONFIG_WMM) && (CONFIG_WMM_DEBUG)
+    /** Restored historical ralists for debug */
+    mlan_list_head hist_ra[MAX_AC_QUEUES];
+    /** Restored historical ralists count */
+    t_u8 hist_ra_count[MAX_AC_QUEUES];
+#endif
+} wmm_desc_t;
+
+/** Security structure */
+typedef struct _wlan_802_11_security_t
+{
+    /** WPA enabled flag */
+    t_u8 wpa_enabled;
+    /** WPA TKIP flag */
+    bool is_wpa_tkip;
+#if CONFIG_11R
+    /** FT attempt flag */
+    bool is_ft;
+#endif
+    /** E-Supplicant enabled flag */
+    t_u8 ewpa_enabled;
+    /** WPA2 enabled flag */
+    t_u8 wpa2_enabled;
+    /** WAPI enabled flag */
+    t_u8 wapi_enabled;
+    /** WAPI key on flag */
+    t_u8 wapi_key_on;
+    /** WEP status */
+    WLAN_802_11_WEP_STATUS wep_status;
+    /** Authentication mode */
+    mlan_auth_mode authentication_mode;
+    /** Encryption mode */
+    mlan_encryption_mode encryption_mode;
+} wlan_802_11_security_t;
+
+/** Current Basic Service Set State Structure */
+typedef struct
+{
+    /** BSS descriptor */
+    BSSDescriptor_t bss_descriptor;
+    /** WMM enable? */
+    t_u8 wmm_enabled;
+    /** Uapsd enable?*/
+    t_u8 wmm_uapsd_enabled;
+    /** Band */
+    t_u8 band;
+    /** Number of rates supported */
+    t_u32 num_of_rates;
+    /** Supported rates*/
+    t_u8 data_rates[WLAN_SUPPORTED_RATES];
+    /** Host MLME flag*/
+    t_u8 host_mlme;
+    /** prev_bssid */
+    mlan_802_11_mac_addr prev_bssid;
+    /** attemp_bssid */
+    mlan_802_11_mac_addr attemp_bssid;
+    t_u8 use_mfp;
+} current_bss_params_t;
+
+/** Sleep_params */
+typedef struct _sleep_params_t
+{
+    /** Sleep parameter error */
+    t_u16 sp_error;
+    /** Sleep parameter offset */
+    t_u16 sp_offset;
+    /** Sleep parameter stable time */
+    t_u16 sp_stable_time;
+    /** Sleep parameter calibration control */
+    t_u8 sp_cal_control;
+    /** Sleep parameter external sleep clock */
+    t_u8 sp_ext_sleep_clk;
+    /** Sleep parameter reserved */
+    t_u16 sp_reserved;
+} sleep_params_t;
+
+/** Sleep_period */
+typedef struct sleep_period_t
+{
+    /** Sleep period */
+    t_u16 period;
+    /** Reserved */
+    t_u16 reserved;
+} sleep_period_t;
+
+/** mrvl_wep_key_t */
+typedef struct _mrvl_wep_key_t
+{
+    /** Length */
+    t_u32 length;
+    /** WEP key index */
+    t_u32 key_index;
+    /** WEP key length */
+    t_u32 key_length;
+    /** WEP keys */
+    t_u8 key_material[MRVL_KEY_BUFFER_SIZE_IN_BYTE];
+} mrvl_wep_key_t;
+
+/** Maximum number of region channel */
+#define MAX_REGION_CHANNEL_NUM 2U
+
+/** Region-band mapping table */
+typedef struct _region_chan_t
+{
+    /** TRUE if this entry is valid */
+    t_u8 valid;
+    /** Region code for US, Japan ... */
+    t_u8 region;
+    /** Band B/G/A, used for BAND_CONFIG cmd */
+    t_u16 band;
+    /** Actual No. of elements in the array below */
+    t_u8 num_cfp;
+    /** chan-freq-txpower mapping table */
+    const chan_freq_power_t *pcfp;
+} region_chan_t;
+
+/** State of 11d */
+typedef enum _state_11d_t
+{
+    DISABLE_11D = 0UL,
+    ENABLE_11D  = 1UL,
+} state_11d_t;
+
+/** State of 11h */
+typedef enum _state_11h_t
+{
+    DISABLE_11H = 0UL,
+    ENABLE_11H  = 1UL,
+} state_11h_t;
+
+#define DEFAULT_11D_STATE DISABLE_11D
+
+/** Domain regulatory information */
+typedef struct _wlan_802_11d_domain_reg
+{
+    /** Country Code */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /** band that channels in sub_band belong to */
+    t_u16 band;
+    /** No. of subband in below */
+    t_u8 no_of_sub_band;
+    /** Subband data to send/last sent */
+    IEEEtypes_SubbandSet_t sub_band[MRVDRV_MAX_SUBBAND_802_11D];
+} wlan_802_11d_domain_reg_t;
+
+/** Data for state machine */
+typedef struct _wlan_802_11d_state
+{
+    /** True for enabling 11D */
+    state_11d_t enable_11d;
+    /** True for user enabling 11D */
+    state_11d_t user_enable_11d;
+    /** True for user enabling 11D support*/
+    state_11d_t user_enable_11d_support;
+} wlan_802_11d_state_t;
+
+/** 802.11h State information kept in the 'mlan_private' driver structure */
+typedef struct
+{
+    /** Indicates whether 11h is enabled in the driver */
+    t_bool is_11h_enabled;
+    /** Indicates whether 11h is active in the firmware */
+    t_bool is_11h_active;
+    /** Master device using automatic channel select */
+    t_bool adhoc_auto_sel_chan;
+    /** Set when driver receives a STOP TX event from fw */
+    t_bool tx_disabled;
+} wlan_11h_interface_state_t;
+
+/** UAP get info callback state kept in the 'mlan_private' driver structure */
+typedef struct
+{
+    /** UAP internal callback after wlan_uap_get_channel */
+    /**  (parameter is really pointer to mlan_private)   */
+    mlan_status (*get_chan_callback)(t_void *);
+    /** current ioctl_req (to be completed in callback) */
+    pmlan_ioctl_req pioctl_req_curr;
+    /** band_cfg from MrvlIEtypes_channel_band_t */
+    t_u8 band_config;
+    /** channel from MrvlIEtypes_channel_band_t */
+    t_u8 channel;
+    /** beacon period (in msec) from MrvlIEtypes_beacon_period_t */
+    t_u16 beacon_period;
+    /** dtim period (no unit) from MrvlIEtypes_dtim_period_t */
+    t_u8 dtim_period;
+    /** Maximum number of stations that will be allowed to connect to the uAP.
+     */
+    t_u16 max_sta_count;
+} wlan_uap_get_info_cb_t;
+
+/** Data structure for WPS information */
+typedef struct
+{
+    /** WPS IE */
+    IEEEtypes_VendorSpecific_t wps_ie;
+    int wps_mgmt_bitmap_index;
+    /** Session enable flag */
+    t_u8 session_enable;
+} wps_t;
+
+typedef struct _mlan_private mlan_private;
+typedef struct _mlan_private *pmlan_private;
+
+/* 802.11D related structs */
+typedef struct
+{
+    mlan_status (*wlan_11d_prepare_dnld_domain_info_cmd_p)(mlan_private *pmpriv);
+    mlan_status (*wlan_11d_create_dnld_countryinfo_p)(mlan_private *pmpriv, t_u16 band);
+    mlan_status (*wlan_11d_parse_dnld_countryinfo_p)(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc);
+} wlan_11d_fn_t;
+
+typedef struct _mlan_adapter *pmlan_adapter;
+typedef struct _mlan_adapter mlan_adapter;
+
+typedef struct
+{
+    mlan_status (*wlan_11d_cfg_ioctl_p)(IN mlan_private *pmpriv, IN pmlan_ioctl_req pioctl_req);
+    mlan_status (*wlan_11d_cfg_domain_info_p)(IN pmlan_adapter pmadapter, IN mlan_ioctl_req *pioctl_req);
+    mlan_status (*wlan_cmd_802_11d_domain_info_p)(mlan_private *pmpriv, HostCmd_DS_COMMAND *pcmd, t_u16 cmd_action);
+    mlan_status (*wlan_11d_handle_uap_domain_info_p)(mlan_private *pmpriv,
+                                                     t_u16 band,
+                                                     t_u8 *domain_tlv,
+                                                     t_void *pioctl_buf);
+} wlan_11d_apis_t;
+
+#if CONFIG_WMM
+typedef struct
+{
+    mlan_list_head free_list;
+    int free_cnt;
+} outbuf_pool_t;
+
+typedef struct
+{
+    t_u16 tx_no_media;
+    t_u16 tx_err_mem;
+    t_u16 tx_wmm_retried_drop;
+    t_u16 tx_wmm_pause_drop;
+    t_u16 tx_wmm_pause_replaced;
+    t_u16 rx_reorder_drop;
+} wlan_pkt_stat_t;
+#endif
+
+/** mlan_operations data structure */
+typedef struct _mlan_operations
+{
+    /** cmd handler */
+    mlan_status (*prepare_cmd)(IN t_void *priv,
+                               IN t_u16 cmd_no,
+                               IN t_u16 cmd_action,
+                               IN t_u32 cmd_oid,
+                               IN t_void *pioctl_buf,
+                               IN t_void *pdata_buf,
+                               IN t_void *pcmd_buf);
+    /** rx handler */
+    mlan_status (*process_rx_packet)(IN t_void *adapter, IN pmlan_buffer pmbuf);
+    /** BSS role */
+    mlan_bss_role bss_role;
+} mlan_operations;
+
+typedef MLAN_PACK_START struct _mlan_chan_info
+{
+    unsigned int mode;
+    int freq;
+    int channel;
+    int sec_channel_offset;
+    int bandwidth;
+    int ht_enabled;
+    int vht_enabled;
+    int he_enabled;
+    int center_freq1;
+    int center_freq2;
+} MLAN_PACK_END mlan_chan_info;
+
+
+#define WLAN_AUTH_SAE 3
+
+/** AUTH pending flag */
+#define HOST_MLME_AUTH_PENDING MBIT(0)
+/** AUTH complete flag */
+#define HOST_MLME_AUTH_DONE     MBIT(1)
+#define HOST_MLME_ASSOC_PENDING MBIT(2)
+#define HOST_MLME_ASSOC_DONE    MBIT(3)
+
+#ifdef RW610
+/**Adapter_operations data structure*/
+typedef struct _bus_operations
+{
+    /** interface to check if fw is hang */
+    bool (*fw_is_hang)(void);
+    /**Interface header length*/
+    t_u32 intf_header_len;
+} bus_operations;
+#endif
+
+/** Private structure for MLAN */
+struct _mlan_private
+{
+    /** Pointer to mlan_adapter */
+    struct _mlan_adapter *adapter;
+    /** BSS index */
+    t_u8 bss_index;
+    /** BSS type */
+    mlan_bss_type bss_type;
+    /** BSS role */
+    mlan_bss_role bss_role;
+    /** BSS Priority */
+    t_u8 bss_priority;
+    /** BSS number */
+    t_u8 bss_num;
+    /** Frame type */
+    t_u8 frame_type;
+    /** MAC address information */
+    t_u8 curr_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Media connection status */
+    t_bool media_connected;
+
+    /** Current packet filter */
+    t_u32 curr_pkt_filter;
+    /** Infrastructure mode */
+    mlan_bss_mode bss_mode;
+
+    /** Channel info */
+    mlan_chan_info chan;
+
+    /** Tx packet control */
+    t_u32 pkt_tx_ctrl;
+
+    /** Tx power level */
+    t_u16 tx_power_level;
+    /** Maximum Tx power level */
+    t_u8 max_tx_power_level;
+    /** Minimum Tx power level */
+    t_u8 min_tx_power_level;
+    /** Tx rate */
+    t_u8 tx_rate;
+#ifdef SD8801
+    /** tx ht_info */
+    t_u8 tx_htinfo;
+    /** rxpd_htinfo */
+    t_u8 rxpd_htinfo;
+#else
+    t_u8 tx_rate_info;
+#if CONFIG_11AX
+    /*HE tx tone mode and DCM info*/
+    t_u8 ext_tx_rate_info;
+#endif
+    /** rxpd_htinfo */
+    t_u8 rxpd_rate_info;
+#endif
+
+#if CONFIG_11AX
+    /** UAP 11ax flag */
+    t_u8 is_11ax_enabled;
+    /** length of hw he capability */
+    t_u8 user_hecap_len;
+    /** user configured 802.11ax HE capability */
+    t_u8 user_he_cap[54];
+    /** length of hw he capability */
+    t_u8 user_2g_hecap_len;
+    /** user configured 802.11ax HE capability */
+    t_u8 user_2g_he_cap[54];
+#endif
+
+    t_u8 ssid_filter;
+
+    /** Filter SSID */
+    mlan_802_11_ssid filter_ssid[MRVDRV_MAX_SSID_LIST_LENGTH];
+    /** max amsdu size */
+    t_u16 max_amsdu;
+#if CONFIG_AMSDU_IN_AMPDU
+    /** amsdu enabled */
+    t_bool is_amsdu_enabled;
+#endif
+    /** UAP 11n flag */
+    bool is_11n_enabled;
+    /** UAP 11ac flag */
+    bool is_11ac_enabled;
+    /** packet forward control */
+    t_u8 pkt_fwd;
+    /**  dropped pkts */
+    t_u32 num_drop_pkts;
+    /** TX beamforming capability */
+    t_u32 tx_bf_cap;
+    /** Rx PD rate */
+    t_u8 rxpd_rate;
+    /** Rate bitmap */
+    t_u16 rate_bitmap;
+    /** Bitmap rates */
+    t_u16 bitmap_rates[MAX_BITMAP_RATES_SIZE];
+    /** Data rate */
+    t_u32 data_rate;
+    /** Data rate index */
+    t_s8 data_rate_index;
+    /** Automatic data rate flag */
+    bool is_data_rate_auto;
+    /** Factor for calculating beacon average */
+    t_u16 bcn_avg_factor;
+    /** Factor for calculating data average */
+    t_u16 data_avg_factor;
+    /** Last data RSSI */
+    t_s16 data_rssi_last;
+    /** Last data Noise Floor */
+    t_s16 data_nf_last;
+    /** Average data RSSI */
+    t_s16 data_rssi_avg;
+    /** Averag data Noise Floor */
+    t_s16 data_nf_avg;
+    /** Last beacon RSSI */
+    t_s16 bcn_rssi_last;
+    /** Last beacon Noise Floor */
+    t_s16 bcn_nf_last;
+    /** Average beacon RSSI */
+    t_s16 bcn_rssi_avg;
+    /** Average beacon Noise Floor */
+    t_s16 bcn_nf_avg;
+
+    /** Attempted BSS descriptor */
+    BSSDescriptor_t *pattempted_bss_desc;
+#if CONFIG_GTK_REKEY_OFFLOAD
+    /** GTK rekey data*/
+    mlan_ds_misc_gtk_rekey_data gtk_rekey;
+#endif
+
+    /** Current SSID/BSSID related parameters*/
+    current_bss_params_t curr_bss_params;
+
+    /** flag for auth */
+    t_u8 auth_flag;
+    /** flag for auth algorithm */
+    t_u16 auth_alg;
+#if CONFIG_11R
+    /** flag for ft roam */
+    t_u8 ft_roam;
+#endif
+
+    /** User selected bands */
+    t_u16 config_bands;
+
+    /** Beacon period */
+    t_u16 beacon_period;
+    /** Listen interval */
+    t_u16 listen_interval;
+    /** ATIM window */
+    t_u16 atim_window;
+
+    /** AdHoc channel */
+    t_u8 adhoc_channel;
+    /** AdHoc link sensed flag */
+    t_u8 adhoc_is_link_sensed;
+    /** AdHoc operating state */
+    t_u8 adhoc_state;
+    /** AdHoc operating state backup */
+    t_u8 adhoc_state_prev;
+    /** AdHoc previous ssid used for Start */
+    mlan_802_11_ssid adhoc_last_start_ssid;
+    /** FSM variable for 11d support */
+    wlan_802_11d_state_t state_11d;
+    /** 11d function pointer */
+    wlan_11d_fn_t *support_11d;
+    /** 11d Driver function pointer */
+    wlan_11d_apis_t *support_11d_APIs;
+    /** FSM variable for 11h support */
+    wlan_11h_interface_state_t intf_state_11h;
+    /** Whether UAP interface has started */
+    t_bool uap_bss_started;
+    /** state variable for UAP Get Info callback */
+    wlan_uap_get_info_cb_t uap_state_chan_cb;
+    /** Security related */
+    /** Encryption parameter */
+    wlan_802_11_security_t sec_info;
+    /** WEP keys */
+    mrvl_wep_key_t wep_key[MRVL_NUM_WEP_KEY];
+    /** Current WEP key index */
+    t_u16 wep_key_curr_index;
+    /** EWPA query 0: disable, 1: enable */
+    bool ewpa_query;
+    /** Encryption Key*/
+    t_u8 wpa_ie[MLAN_WMSDK_MAX_WPA_IE_LEN];
+    /** WPA IE length */
+    t_u8 wpa_ie_len;
+#if CONFIG_11R
+    /** MD IE */
+    t_u8 md_ie[5];
+    /** MD IE length */
+    size_t md_ie_len;
+#endif
+    /** GTK set flag */
+    t_u8 wpa_is_gtk_set;
+    /** Pointer to the station table */
+    mlan_list_head sta_list;
+    /** mgmt frame passthru mask */
+    t_u32 mgmt_frame_passthru_mask;
+    /** Advanced Encryption Standard */
+    bool adhoc_aes_enabled;
+    /** WMM required */
+    bool wmm_required;
+    /** WMM enabled */
+    bool wmm_enabled;
+    /** WMM qos info */
+    t_u8 wmm_qosinfo;
+    /** WMM related variable*/
+    wmm_desc_t wmm;
+#if CONFIG_WMM
+    /** Bypass TX queue*/
+    mlan_list_head bypass_txq;
+    /** Bypass TX queue cnt*/
+    t_u8 bypass_txq_cnt;
+#endif
+    /* Mgmt Frame Protection config */
+    mlan_ds_misc_pmfcfg pmfcfg;
+
+    /* ED MAC MODE config */
+    mlan_ds_misc_ed_mac_mode ed_mac_mode;
+
+    /** Pointer to the Transmit BA stream table*/
+    mlan_list_head tx_ba_stream_tbl_ptr;
+    /** Semaphore to the Transmit BA stream table */
+    OSA_MUTEX_HANDLE_DEFINE(tx_ba_stream_tbl_lock);
+    /** Pointer to the priorities for AMSDU/AMPDU table*/
+    tx_aggr_t aggr_prio_tbl[MAX_NUM_TID];
+    /** Pointer to the priorities for AMSDU/AMPDU table*/
+    t_u8 addba_reject[MAX_NUM_TID];
+    /** Struct to store ADDBA parameters */
+    add_ba_param_t add_ba_param;
+    /** last rx_seq */
+    t_u16 rx_seq[MAX_NUM_TID];
+    /** Lock to the Receive Reordering table */
+    OSA_SEMAPHORE_HANDLE_DEFINE(rx_reorder_tbl_lock);
+    /** Pointer to the Receive Reordering table*/
+    mlan_list_head rx_reorder_tbl_ptr;
+    /** Lock for Rx packets */
+    t_void *rx_pkt_lock;
+
+
+    /** Generic IEEE IEs passed from the application to be inserted into the
+     *    association request to firmware
+     */
+    t_u8 gen_ie_buf[MRVDRV_GENIE_BUF_SIZE];
+    /** Length of the data stored in gen_ie_buf */
+    t_u8 gen_ie_buf_len;
+
+#if CONFIG_WPA_SUPP
+    /**
+     * Default scan ies buffer
+     */
+    t_u8 default_scan_ies[MRVDRV_GENIE_BUF_SIZE];
+    /** Length of the data stored in gen_ie_buf */
+    t_u8 default_scan_ies_len;
+#endif
+
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    /** WPS */
+    wps_t wps;
+#endif
+#elif (CONFIG_WPS2)
+    /** WPS */
+    wps_t wps;
+#endif
+    /** Buffer to store the association req IEs */
+    t_u8 assoc_req_buf[MRVDRV_ASSOC_RSP_BUF_SIZE];
+    /** Length of the data stored in assoc_rsp_buf */
+    t_u32 assoc_req_size;
+
+    /** function table */
+    mlan_operations ops;
+
+#if CONFIG_11K
+    t_u8 enable_host_11k;
+    int rrm_mgmt_bitmap_index;
+    t_u8 neighbor_rep_token;
+#endif
+#if CONFIG_11V
+    t_u8 bss_trans_query_token;
+#endif
+
+    /** Port Control mode */
+    bool port_ctrl_mode;
+
+    /** Port open flag */
+    bool port_open;
+
+    /** Port open flag state at time of association attempt */
+    bool prior_port_status;
+
+    /** Scan block flag */
+    bool scan_block;
+    /** IP address operation */
+    t_u32 op_code;
+    /** IP address */
+    t_u8 ip_addr[IPADDR_LEN];
+    t_u32 hotspot_cfg;
+    ExtCap_t ext_cap;
+#if (CONFIG_WNM_PS)
+    /** WNM power save mode */
+    bool wnm_set;
+#endif
+    t_u8 rssi_low;
+    t_u8 roaming_enabled;
+    t_u8 roaming_configured;
+    /** bg_scan_start */
+    t_u8 bg_scan_start;
+    /** bg_scan reported */
+    t_u8 bg_scan_reported;
+    /** bg_scan config */
+    wlan_bgscan_cfg scan_cfg;
+    /** sched scaning flag */
+    t_u8 sched_scanning;
+    /** bgscan request id */
+    t_u64 bg_scan_reqid;
+    /* interface pause status */
+    t_u8 tx_pause;
+#if CONFIG_WMM
+    wlan_pkt_stat_t driver_error_cnt;
+#endif
+#if CONFIG_DRIVER_MBO
+    t_u8 enable_mbo;
+    int mbo_mgmt_bitmap_index;
+#endif
+    /** tx_seq_num */
+    t_u32 tx_seq_num;
+#if CONFIG_WPA_SUPP
+    int probe_req_index;
+#if CONFIG_WPA_SUPP_AP
+    int beacon_vendor_index;
+    int beacon_index;
+    int proberesp_index;
+    int assocresp_index;
+    int beacon_wps_index;
+#endif
+#endif
+    /** uAP started or not */
+    bool bss_started;
+    /** host based uap flag */
+    bool uap_host_based;
+    /**UAP operating channel*/
+    t_u8 uap_channel;
+    /** uAP MAX STAs */
+    t_u8 uap_max_sta;
+#if CONFIG_TCP_ACK_ENH
+    bool enable_tcp_ack_enh;
+#endif
+#if CONFIG_WPA_SUPP_DPP
+    /** configured by DPP */
+    bool is_dpp_connect;
+#endif
+    t_u32 tx_overrun_cnt;
+    t_u32 rx_overrun_cnt;
+};
+
+/** BA stream status */
+typedef enum _baStatus_e
+{
+    BA_STREAM_NOT_SETUP = 0,
+    BA_STREAM_SETUP_INPROGRESS,
+    BA_STREAM_SETUP_COMPLETE
+} baStatus_e;
+
+/** Tx BA stream table */
+struct _TxBAStreamTbl
+{
+    /** TxBAStreamTbl previous node */
+    TxBAStreamTbl *pprev;
+    /** TxBAStreamTbl next node */
+    TxBAStreamTbl *pnext;
+    /** TID */
+    int ampdu_stat[MAX_NUM_TID];
+    /** RA */
+    t_u8 ra[MLAN_MAC_ADDR_LENGTH];
+    /** BA stream status */
+    baStatus_e ba_status;
+    t_u8 amsdu;
+    t_u32 txpkt_cnt;
+    t_u32 txba_thresh;
+    t_u8 ampdu_supported[MAX_NUM_TID];
+    /** last rx_seq */
+    t_u16 rx_seq[MAX_NUM_TID];
+};
+
+/** RX reorder table */
+typedef struct _RxReorderTbl RxReorderTbl;
+
+typedef struct
+{
+    /** Timer for flushing */
+    OSA_TIMER_HANDLE_DEFINE(timer);
+    /** Timer set flag */
+    bool timer_is_set;
+    /** RxReorderTbl ptr */
+    RxReorderTbl *ptr;
+    /** Priv pointer */
+    mlan_private *priv;
+} reorder_tmr_cnxt_t;
+
+/** RX reorder table */
+struct _RxReorderTbl
+{
+    /** RxReorderTbl previous node */
+    RxReorderTbl *pprev;
+    /** RxReorderTbl next node */
+    RxReorderTbl *pnext;
+    /** TID */
+    int tid;
+    /** TA */
+    t_u8 ta[MLAN_MAC_ADDR_LENGTH];
+    /** Start window */
+    t_u16 start_win;
+    /** last_seq */
+    t_u16 last_seq;
+    /** Window size */
+    t_u16 win_size;
+    /** Pointer to pointer to RxReorderTbl */
+    t_void **rx_reorder_ptr;
+    /** Timer context */
+    reorder_tmr_cnxt_t timer_context;
+    /** BA stream status */
+    baStatus_e ba_status;
+    t_u8 amsdu;
+    /** no packet drop flag for rx_reorder_tbl */
+    bool force_no_drop;
+    /** flag for check start win */
+    bool check_start_win;
+    /** pkt receive after BA setup */
+    t_u8 pkt_count;
+    /** BA window bitmap */
+    t_u64 bitmap;
+};
+
+/** BSS priority node */
+typedef struct _mlan_bssprio_node mlan_bssprio_node;
+
+/** BSS priority node */
+struct _mlan_bssprio_node
+{
+    /** Pointer to previous node */
+    mlan_bssprio_node *pprev;
+    /** Pointer to next node */
+    mlan_bssprio_node *pnext;
+    /** Pointer to priv */
+    pmlan_private priv;
+};
+
+/** BSS priority table */
+typedef struct _mlan_bssprio_tbl mlan_bssprio_tbl;
+
+/** BSS priority table */
+struct _mlan_bssprio_tbl
+{
+    /** BSS priority list head */
+    mlan_list_head bssprio_head;
+    /** Current priority node */
+    mlan_bssprio_node *bssprio_cur;
+};
+
+/** cmd_ctrl_node */
+typedef struct _cmd_ctrl_node cmd_ctrl_node;
+
+/** _cmd_ctrl_node */
+struct _cmd_ctrl_node
+{
+    /** Pointer to previous node */
+    cmd_ctrl_node *pprev;
+    /** Pointer to next node */
+    cmd_ctrl_node *pnext;
+    /** Pointer to priv */
+    pmlan_private priv;
+    /** Command OID for sub-command use */
+    t_u32 cmd_oid;
+    /** Command flag */
+    t_u32 cmd_flag;
+    /** Pointer to mlan_buffer */
+    mlan_buffer *cmdbuf;
+    /** Pointer to mlan_buffer */
+    mlan_buffer *respbuf;
+    /** Command parameter */
+    t_void *pdata_buf;
+    /** Pointer to mlan_ioctl_req if command is from IOCTL */
+    t_void *pioctl_buf;
+    /** pre_allocated mlan_buffer for cmd */
+    mlan_buffer *pmbuf;
+};
+
+/** station node */
+typedef struct _sta_node sta_node;
+
+/** station node*/
+struct _sta_node
+{
+    /** previous node */
+    sta_node *pprev;
+    /** next node */
+    sta_node *pnext;
+    /** station mac address */
+    t_u8 mac_addr[MLAN_MAC_ADDR_LENGTH];
+    /** wmm flag */
+    t_u8 is_wmm_enabled;
+    /** 11n flag */
+    bool is_11n_enabled;
+#if CONFIG_11AC
+    /** 11ac flag */
+    bool is_11ac_enabled;
+#endif
+#if CONFIG_11AX
+    t_u8 is_11ax_enabled;
+    IEEEtypes_HECap_t he_cap;
+#endif
+    /** AMPDU STA */
+    t_u8 ampdu_sta[MAX_NUM_TID];
+    /** last rx_seq */
+    t_u16 rx_seq[MAX_NUM_TID];
+    /** max amsdu size */
+    t_u16 max_amsdu;
+    /** HT cap */
+    IEEEtypes_HTCap_t HTcap;
+    /** peer capability */
+    t_u16 capability;
+    /** station band mode */
+    t_u16 bandmode;
+    /** wapi key on off flag */
+    t_u8 wapi_key_on;
+    /** tx pause status */
+    t_u8 tx_pause;
+};
+
+/** 802.11h State information kept in the 'mlan_adapter' driver structure */
+typedef struct
+{
+    /** Min TX Power capability sent to FW for 11h use and fw power control */
+    t_s8 min_tx_power_capability;
+    /** Max TX Power capability sent to FW for 11h use and fw power control */
+    t_s8 max_tx_power_capability;
+    /** User provisioned local power constraint sent in association requests */
+    t_s8 usr_def_power_constraint;
+    /** Received CHANNEL_SWITCH_ANN event */
+    t_bool recvd_chanswann_event;
+    /** Indicates an interface wants to enable master radar detection */
+    t_bool master_radar_det_enable_pending;
+    /** Indicates an interface wants to enable slave radar detection */
+    t_bool slave_radar_det_enable_pending;
+    /** Indicates whether master radar detection active in the firmware */
+    t_bool is_master_radar_det_active;
+    /** Indicates whether slave radar detection active in the firmware */
+    t_bool is_slave_radar_det_active;
+    /** Quiet IE */
+    IEEEtypes_Quiet_t quiet_ie;
+} wlan_11h_device_state_t;
+
+/** Enumeration for DFS Timestamp represents field */
+enum _dfs_timestamp_repr_e
+{
+    /** Ignore entry */
+    DFS_TS_REPR_NOT_IN_USE = 0,
+    /** NOP (Non-Occupancy Period) start time */
+    DFS_TS_REPR_NOP_START = 1,
+    /** CAC (Channel Availability Check) completion time */
+    DFS_TS_REPR_CAC_COMPLETION
+};
+
+/** DFS Timestamp type used for marking NOP/CAC events */
+typedef struct _wlan_dfs_timestamp_t wlan_dfs_timestamp_t;
+
+/** DFS Timestamp type used for marking NOP/CAC events */
+struct _wlan_dfs_timestamp_t
+{
+    /** Pointer to previous node */
+    wlan_dfs_timestamp_t *pprev;
+    /** Pointer to next node */
+    wlan_dfs_timestamp_t *pnext;
+    /** WLAN Channel number */
+    t_u8 channel;
+    /** What this timestamp represents */
+    t_u8 represents;
+    /** reserved field */
+    t_u16 reserved;
+    /** timestamp - seconds */
+    t_u32 ts_sec;
+    /** timestamp - microseconds */
+    t_u32 ts_usec;
+};
+
+/** DFS State information kept in the 'mlan_adapter' driver structure */
+typedef struct
+{
+    /** Indicates whether DFS channel check is occurring in firmware */
+    t_bool dfs_check_pending;
+    /** Indicates whether DFS channel check found radar */
+    t_bool dfs_radar_found;
+    /** Channel radar is being checked on.  BAND_A is assumed. */
+    t_u8 dfs_check_channel;
+    /** Timestamp when we got last report, to determine if data is old or not. */
+    t_u32 dfs_report_time_sec;
+    /** List for holding dfs_timestamps for NOP/CAC events */
+    mlan_list_head dfs_ts_head;
+} wlan_dfs_device_state_t;
+
+/** Enumeration for mlan_ds_11h_radar_det_hndlg stages */
+enum _mlan_ds_11h_rdh_stages
+{
+    RDH_OFF       = 0,
+    RDH_CHK_INTFS = 1,
+    RDH_STOP_TRAFFIC,
+    RDH_GET_INFO_CHANNEL,
+    RDH_GET_INFO_BEACON_DTIM,
+    RDH_SET_CUSTOM_IE,
+    RDH_REM_CUSTOM_IE,
+    RDH_STOP_INTFS,
+    RDH_SET_NEW_CHANNEL,
+    RDH_RESTART_INTFS,
+    RDH_RESTART_TRAFFIC
+};
+
+/** State info for Radar Detected Handling kept in 'mlan_adapter' */
+typedef struct
+{
+    /** Stage (of Operation) */
+    t_u8 stage;
+    /** Number of interfaces to handle */
+    t_u8 priv_list_count;
+    /** Index of interface in process (used by some stages) */
+    t_u8 priv_curr_idx;
+    /** Current Channel (to leave) */
+    t_u8 curr_channel;
+    /** New Channel (to switch to) */
+    t_u8 new_channel;
+    /** UAP band_config */
+    t_u8 uap_band_cfg;
+    /** BEACON*DTIM period (in msec; max of STA/UAP) */
+    t_u16 max_bcn_dtim_ms;
+    /** List of interfaces to handle */
+    mlan_private *priv_list[MLAN_MAX_BSS_NUM];
+} wlan_radar_det_hndlg_state_t;
+
+
+/**
+ * @brief Driver measurement state held in 'mlan_adapter' structure
+ *
+ *  Used to record a measurement request that the driver is pending on
+ *    the result (received measurement report).
+ */
+typedef struct
+{
+    /**
+     * Dialog token of a pending measurement request/report.  Used to
+     *   block execution while waiting for the specific dialog token
+     */
+    t_u8 meas_rpt_pend_on;
+
+    /**
+     * Measurement report received from the firmware that we were pending on
+     */
+    HostCmd_DS_MEASUREMENT_REPORT meas_rpt_returned;
+
+} wlan_meas_state_t;
+
+#if CONFIG_WIFI_TX_PER_TRACK
+/** Tx Per Tracking Structure
+ * Driver sets tx per tracking statistic to fw.
+ * Fw will check tx packet error rate periodically and
+ * report PER to host if per is high.
+ */
+typedef struct
+{
+    /** Enable/Disable tx per tracking */
+    t_u8 tx_pert_check;
+    /** Check period(unit sec) */
+    t_u8 tx_pert_check_peroid;
+    /** (Fail TX packet)/(Total TX packet) ratio(unit 10%)
+     * default: 5
+     */
+    t_u8 tx_pert_check_ratio;
+    /** A watermark of check number(default 5) */
+    t_u16 tx_pert_check_num;
+} tx_pert_info;
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+typedef struct
+{
+    /**  Enable or disable  */
+    t_u8 enable;
+    /** Choose to get TX, RX or both */
+    t_u16 action;
+} txrx_histogram_info;
+#endif
+
+
+
+/** mlan_init_para structure */
+typedef struct _mlan_init_para
+{
+    /** SDIO interrupt mode (0: INT_MODE_SDIO, 1: INT_MODE_GPIO) */
+    t_u32 int_mode;
+    /** GPIO interrupt pin number */
+    t_u32 gpio_pin;
+    /** Auto deep sleep */
+    t_u32 auto_ds;
+    /** IEEE PS mode */
+    t_u32 ps_mode;
+    /** Max Tx buffer size */
+    t_u32 max_tx_buf;
+    /** 802.11d configuration */
+    t_u32 cfg_11d;
+    /** 802.11H DFS Master Radar Detect */
+    t_u32 dfs_master_radar_det_en;
+    /** 802.11H DFS Slave Radar Detect */
+    t_u32 dfs_slave_radar_det_en;
+    /** FW download CRC check flag */
+    t_u32 fw_crc_check;
+} mlan_init_para, *pmlan_init_para;
+
+#define MLAN_MAX_BLACKLIST_BSSID 16
+
+/* BSSID blacklist */
+typedef struct
+{
+    /** Number of blacklisted BSSIDs */
+    int num_bssid;
+    /** Blacklisted BSSIDs */
+    mlan_802_11_mac_addr bssids[MLAN_MAX_BLACKLIST_BSSID];
+} mlan_blacklisted_bssid_params;
+
+#if CONFIG_FW_VDLL
+/** vdll_dnld_ctrl structure */
+typedef struct _vdll_dnld_ctrl
+{
+    /**  pending  VDLL block */
+    t_u8 *pending_block;
+    /* pending VDLL block len */
+    t_u16 pending_block_len;
+    /** memory for VDLL fw image */
+    t_u8 *vdll_mem;
+    /**  VDLL fw image len */
+    t_u32 vdll_len;
+    /** cmd buffer for VDLL download */
+    t_u8 *cmd_buf;
+} vdll_dnld_ctrl, *pvdll_dnld_ctrl;
+#endif
+
+#if CONFIG_HOST_SLEEP
+/* WLAN wakeup reason in detail */
+typedef struct
+{
+    /* Rx IMU msg type */
+    uint8_t type;
+    /* IMU msg subtype for ctrl msg */
+    uint8_t subtype;
+    /* cmdresp or event id */
+    uint16_t id;
+} wlan_wakeup_reason;
+#endif
+
+/** Adapter data structure for MLAN */
+struct _mlan_adapter
+{
+    /** MOAL handle structure */
+    t_void *pmoal_handle;
+    /** Private pointer */
+    pmlan_private priv[MLAN_MAX_BSS_NUM];
+    /** Total number of Priv number */
+    t_u8 priv_num;
+    /** Firmware start addr */
+    const t_u8 *fw_start_addr;
+    mlan_callbacks callbacks;
+    /** Init parameters */
+    mlan_init_para init_para;
+#ifdef RW610
+    /** bus operations*/
+    bus_operations bus_ops;
+#endif
+    /** Country ie ignore */
+    t_u8 country_ie_ignore;
+    /** In reset status now */
+    t_u8 in_reset;
+    /** IO port */
+    t_u32 ioport;
+    /** STATUS variables */
+    WLAN_HARDWARE_STATUS hw_status;
+    /** Firmware release number */
+    t_u32 fw_release_number;
+
+    /** Number of antenna used */
+    t_u16 number_of_antenna;
+
+    /** Firmware capability information */
+    t_u32 fw_cap_info;
+    /** Extended firmware capability information */
+    t_u32 fw_cap_ext;
+#if CONFIG_FW_VDLL
+    /** vdll ctrl */
+    vdll_dnld_ctrl vdll_ctrl;
+    /** VDLL operation in progress */
+    volatile t_bool vdll_in_progress;
+    /** Timer for vdll */
+    OSA_TIMER_HANDLE_DEFINE(vdll_timer);
+#endif
+    /** pint_lock for interrupt handling */
+    t_void *pint_lock;
+    /** Interrupt status */
+    t_u8 sdio_ireg;
+    /** SDIO multiple port read bitmap */
+    t_u32 mp_rd_bitmap;
+    /** SDIO multiple port write bitmap */
+    t_u32 mp_wr_bitmap;
+    /** SDIO end port from txbufcfg */
+    t_u16 mp_end_port;
+    /** SDIO port mask calculated based on txbufcfg end port */
+    t_u32 mp_data_port_mask;
+    /** Current available port for read */
+    t_u8 curr_rd_port;
+    /** Current available port for write */
+    t_u8 curr_wr_port;
+    /** Array to store values of SDIO multiple port group registers */
+    t_u8 *mp_regs;
+    /** allocated buf to read SDIO multiple port group registers */
+    t_u8 *mp_regs_buf;
+
+    /** ECSA support */
+    bool ecsa_enable;
+    /* Firmware support cmd_tx_data */
+    t_u8 cmd_tx_data;
+
+    /** CMD sent:
+     *       TRUE - CMD is sent to fw, no CMD Done received
+     *       FALSE - CMD done received for previous CMD
+     */
+    t_u8 cmd_sent;
+    /** Region code */
+    t_u16 region_code;
+    /** Region code from HW*/
+    t_u16 hw_region_code;
+    /** Region Channel data */
+    region_chan_t region_channel[MAX_REGION_CHANNEL_NUM];
+    /** CFP table code for 2.4GHz */
+    t_u8 cfp_code_bg;
+    /** CFP table code for 5GHz */
+    t_u8 cfp_code_a;
+    /** WMM AC params */
+    wmm_ac_parameters_t ac_params[MAX_AC_QUEUES];
+    /** Minimum BA Threshold */
+    t_u8 min_ba_threshold;
+    /** Universal Channel data */
+    region_chan_t universal_channel[MAX_REGION_CHANNEL_NUM];
+    /** Parsed region channel */
+    parsed_region_chan_11d_t parsed_region_chan;
+    /** 11D and Domain Regulatory Data */
+    wlan_802_11d_domain_reg_t domain_reg;
+    /** Country Code */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /** FSM variable for 11h support */
+    wlan_11h_device_state_t state_11h;
+    /** FSM variable for DFS support */
+    wlan_dfs_device_state_t state_dfs;
+    /** FSM variable for RDH support */
+    wlan_radar_det_hndlg_state_t state_rdh;
+    /** FSM variable for MEAS support */
+    wlan_meas_state_t state_meas;
+    /** Scan table */
+    BSSDescriptor_t *pscan_table;
+    /** BSS blacklist */
+    mlan_blacklisted_bssid_params blacklist_bss;
+    /** scan age in secs */
+    t_u32 age_in_secs;
+    /** Active scan for hidden ssid triggered */
+    t_u8 active_scan_triggered;
+#if CONFIG_WPA_SUPP
+    /** WPA supplicant scan triggered */
+    t_u8 wpa_supp_scan_triggered;
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+    /** channel statstics */
+    ChanStatistics_t *pchan_stats;
+    /** Number of records in the chan_stats */
+    t_u32 num_in_chan_stats;
+    /** index of chan stats */
+    t_u32 idx_chan_stats;
+    /** scan channel gap time */
+    t_u16 scan_chan_gap;
+#endif
+    /** Number of records in the scan table */
+    t_u32 num_in_scan_table;
+    /** Scan probes */
+    t_u16 scan_probes;
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    /** Rssi threshold */
+    t_s16 rssi_threshold;
+#endif
+
+    /** Scan type */
+    mlan_scan_type scan_type;
+    /** Scan mode */
+    t_u32 scan_mode;
+    /** Specific scan time */
+    t_u16 specific_scan_time;
+    /** Active scan time */
+    t_u16 active_scan_time;
+    /** Passive scan time */
+    t_u16 passive_scan_time;
+#if CONFIG_EXT_SCAN_SUPPORT
+    /** Extended scan or legacy scan */
+    t_u8 ext_scan;
+#endif
+    /** F/W supported bands */
+    t_u16 fw_bands;
+    /** User selected band to start adhoc network */
+    t_u16 adhoc_start_band;
+    /** User selected bands */
+    t_u16 config_bands;
+    /** Pointer to channel list last sent to the firmware for scanning */
+    ChanScanParamSet_t *pscan_channels;
+#if CONFIG_WMM_UAPSD
+    /** Tx lock flag */
+    t_u8 tx_lock_flag;
+
+    /** sleep_params_t */
+    sleep_params_t sleep_params;
+    /** sleep_period_t (Enhanced Power Save) */
+    sleep_period_t sleep_period;
+#endif
+    /** Power Save state */
+    enum wlan_ps_state ps_state;
+    /** keep_wakeup */
+    t_u8 keep_wakeup;
+    /** Multiple DTIM */
+    t_u16 multiple_dtim;
+    /** Local listen interval */
+    t_u16 local_listen_interval;
+    /** Null packet interval */
+    t_u16 null_pkt_interval;
+
+    /** Beacon miss timeout */
+    t_u16 bcn_miss_time_out;
+
+    /** AdHoc awake period */
+    t_u16 adhoc_awake_period;
+
+    /** Delay to PS in milliseconds */
+    t_u16 delay_to_ps;
+    /** Enhanced PS mode */
+    t_u16 enhanced_ps_mode;
+#if CONFIG_WMM_UAPSD
+    /** Gen NULL pkg */
+    t_u16 gen_null_pkt;
+
+    /** PPS/UAPSD mode flag */
+    t_u16 pps_uapsd_mode;
+#endif
+#if CONFIG_HOST_SLEEP
+    /** Host Sleep configured flag */
+    t_u8 is_hs_configured;
+    /** management frame wakeup filter config */
+    mgmt_frame_filter mgmt_filter[MAX_MGMT_FRAME_FILTER];
+#endif
+    /** 802.11n device capabilities */
+    t_u32 hw_dot_11n_dev_cap;
+    /** Device support for MIMO abstraction of MCSs */
+    t_u8 hw_dev_mcs_support;
+    /** mpdu density */
+    t_u8 hw_mpdu_density;
+    /** 802.11n Device Capabilities for 2.4GHz */
+    t_u32 usr_dot_11n_dev_cap_bg;
+    /** 802.11n Device Capabilities for 5GHz */
+    t_u32 usr_dot_11n_dev_cap_a;
+    /** MIMO abstraction of MCSs supported by device */
+    t_u8 usr_dev_mcs_support;
+#if CONFIG_WIFI_CAPA
+    /** user configured 11n enable/disable */
+    t_u8 usr_dot_11n_enable;
+#endif
+    /** Enable 11n support for adhoc start */
+    bool adhoc_11n_enabled;
+    /** Adhoc Secondary Channel Bandwidth */
+    t_u8 chan_bandwidth;
+
+    /** 802.11ac device capabilities */
+    t_u32 hw_dot_11ac_dev_cap;
+    /** 802.11ac device support for MIMO abstraction of MCSs */
+    t_u32 hw_dot_11ac_mcs_support;
+    /** tx vht_info */
+    t_u8 tx_vhtinfo;
+    /** rxpd_vhtinfo */
+    t_u8 rxpd_vhtinfo;
+#if CONFIG_WIFI_CAPA
+    /** user configured 11ac enable/disable */
+    t_u8 usr_dot_11ac_enable;
+#endif
+    /** 802.11ac Device Capabilities for 2.4GHz */
+    t_u32 usr_dot_11ac_dev_cap_bg;
+    /** 802.11ac Device Capabilities for 5GHz */
+    t_u32 usr_dot_11ac_dev_cap_a;
+    /** MIMO abstraction of MCSs supported by device */
+    t_u32 usr_dot_11ac_mcs_support;
+    /** user dot 11ac_BW */
+    t_u8 usr_dot_11ac_bw;
+    /** user dot 11ac_opermode_BW */
+    t_u8 usr_dot_11ac_opermode_bw;
+    /** user dot 11ac_opermode_nss */
+    t_u8 usr_dot_11ac_opermode_nss;
+
+#if CONFIG_11AX
+    /** length of hw he capability */
+    t_u8 hw_hecap_len;
+    /** 802.11ax HE capability */
+    t_u8 hw_he_cap[54];
+    /** length of hw 2.4G he capability */
+    t_u8 hw_2g_hecap_len;
+    /** 802.11ax 2.4G HE capability */
+    t_u8 hw_2g_he_cap[54];
+#if CONFIG_WIFI_CAPA
+    /** user configured 11ax enable/disable */
+    t_u8 usr_dot_11ax_enable;
+#endif
+#endif
+    /** max mgmt IE index in device */
+    t_u16 max_mgmt_ie_index;
+#ifdef OTP_CHANINFO
+    otp_region_info_t *otp_region;
+    chan_freq_power_t *cfp_otp_bg;
+    t_u8 *tx_power_table_bg;
+    t_u32 tx_power_table_bg_size;
+    t_u8 tx_power_table_bg_rows;
+    t_u8 tx_power_table_bg_cols;
+#if CONFIG_5GHz_SUPPORT
+    chan_freq_power_t *cfp_otp_a;
+    t_u8 *tx_power_table_a;
+    t_u32 tx_power_table_a_size;
+    t_u8 tx_power_table_a_rows;
+    t_u8 tx_power_table_a_cols;
+#endif
+#endif
+#if CONFIG_WIFI_TX_BUFF
+    /** Tx buffer size */
+    t_u16 tx_buffer_size;
+#endif
+#if CONFIG_WIFI_TX_PER_TRACK
+    tx_pert_info tx_pert;
+#endif
+    t_u8 bgscan_reported;
+#if CONFIG_MULTI_CHAN
+    t_bool mc_policy;
+#endif
+#if CONFIG_WMM
+    /* wmm buffer pool */
+    outbuf_pool_t outbuf_pool;
+    bool wait_txbuf;
+#endif
+#if CONFIG_HOST_SLEEP
+    wlan_wakeup_reason wlan_wakeup;
+#endif
+    bool skip_dfs;
+    /* remain on channel flag */
+    t_u8 remain_on_channel;
+    t_u8 remain_bss_index;
+};
+
+/** Ethernet packet type for EAPOL */
+#define MLAN_ETHER_PKT_TYPE_EAPOL (0x888E)
+/** Ethernet packet type for WAPI */
+#define MLAN_ETHER_PKT_TYPE_WAPI (0x88B4)
+/** Ethernet packet type for ARP */
+#define MLAN_ETHER_PKT_TYPE_ARP (0x0806)
+/** Ethernet packet type for ARP */
+#define MLAN_ETHER_PKT_TYPE_IPV6 (0x86dd)
+/** Ethernet packet type offset */
+#define MLAN_ETHER_PKT_TYPE_OFFSET (12)
+
+#define MLAN_ETHER_PKT_DHCP_MAGIC_COOKIE        0x63825363UL
+#define MLAN_ETHER_PKT_DHCP_MAGIC_COOKIE_OFFSET 278
+
+mlan_status wlan_cmd_get_tsf(pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action);
+
+#if (CONFIG_WIFI_TX_PER_TRACK) || (CONFIG_TX_RX_HISTOGRAM)
+mlan_status wlan_cmd_txrx_pkt_stats(pmlan_private pmpriv,
+                                    IN HostCmd_DS_COMMAND *cmd,
+                                    IN t_u16 cmd_action,
+                                    IN t_void *pdata_buf);
+#endif
+
+#if CONFIG_WIFI_TX_PER_TRACK
+mlan_status wlan_cmd_tx_pert(pmlan_private pmpriv,
+                             IN HostCmd_DS_COMMAND *cmd,
+                             IN t_u16 cmd_action,
+                             IN t_void *pdata_buf);
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+mlan_status wlan_cmd_txrx_histogram(pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+#endif
+
+mlan_status wlan_init_lock_list(IN pmlan_adapter pmadapter);
+
+/** Initialize firmware */
+mlan_status wlan_init_fw(IN pmlan_adapter pmadapter);
+
+
+
+
+/** Initialize mlan_adapter structure */
+t_void wlan_init_adapter(IN pmlan_adapter pmadapter);
+
+/** Initialize mlan_private structure */
+mlan_status wlan_init_priv(IN pmlan_private priv);
+
+
+/** Prepare command */
+mlan_status wlan_prepare_cmd(IN mlan_private *pmpriv,
+                             IN t_u16 cmd_no,
+                             IN t_u16 cmd_action,
+                             IN t_u32 cmd_oid,
+                             IN t_void *pioctl_buf,
+                             IN t_void *pdata_buf);
+
+void wlan_clear_scan_bss(void);
+/** Allocate memory for adapter structure members */
+mlan_status wlan_allocate_adapter(pmlan_adapter pmadapter);
+/** Free adapter */
+t_void wlan_free_adapter(pmlan_adapter pmadapter);
+/** Handle received packet, has extra handling for aggregate packets */
+mlan_status wlan_handle_rx_packet(pmlan_adapter pmadapter, pmlan_buffer pmbuf);
+/** Transmit a null data packet */
+mlan_status wlan_send_null_packet(pmlan_private priv, t_u8 flags);
+
+
+/** Clean Tx Rx queues */
+t_void wlan_clean_txrx(pmlan_private priv);
+
+/** function to allocate a mlan_buffer */
+pmlan_buffer wlan_alloc_mlan_buffer(mlan_adapter *pmadapter, t_u32 data_len, t_u32 head_room, t_u32 malloc_flag);
+/** function to free a mlan_buffer */
+t_void wlan_free_mlan_buffer(mlan_adapter *pmadapter, pmlan_buffer pmbuf);
+
+
+/** handle command for enhanced power save mode */
+mlan_status wlan_cmd_enh_power_mode(pmlan_private pmpriv,
+                                    IN HostCmd_DS_COMMAND *cmd,
+                                    IN ENH_PS_MODES cmd_action,
+                                    IN t_u16 ps_bitmap,
+                                    IN t_void *pdata_buf);
+
+mlan_status wlan_process_802dot11_mgmt_pkt(mlan_private *priv, t_u8 *payload, t_u32 payload_len, RxPD *rxpd);
+
+mlan_status wlan_bypass_802dot11_mgmt_pkt(void *data);
+
+
+mlan_status wlan_cmd_remain_on_channel(IN pmlan_private pmpriv,
+                                       IN HostCmd_DS_COMMAND *cmd,
+                                       IN t_u16 cmd_action,
+                                       IN t_void *pdata_buf);
+
+
+
+mlan_status wlan_radio_ioctl_radio_ctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+
+
+mlan_status wlan_cmd_tx_rate_cfg(IN pmlan_private pmpriv,
+                                 IN HostCmd_DS_COMMAND *cmd,
+                                 IN t_u16 cmd_action,
+                                 IN t_void *pdata_buf,
+                                 IN mlan_ioctl_req *pioctl_buf);
+mlan_status wlan_ret_tx_rate_cfg(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN void *pioctl);
+
+mlan_status wlan_rate_ioctl_cfg(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+mlan_status wlan_ret_802_11_tx_rate_query(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN void *pioctl);
+/** Handler for bgscan query commands */
+mlan_status wlan_cmd_802_11_bg_scan_query(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action);
+/** Handler for bgscan config command */
+mlan_status wlan_cmd_bgscan_config(IN mlan_private *pmpriv,
+                                   IN HostCmd_DS_COMMAND *cmd,
+                                   IN t_u16 cmd_action,
+                                   IN t_void *pdata_buf);
+/** Hander for bgscan config command response */
+mlan_status wlan_ret_bgscan_config(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *resp, IN mlan_ioctl_req *pioctl_buf);
+
+#if (CONFIG_ROAMING) || (CONFIG_SUBSCRIBE_EVENT_SUPPORT)
+/** Handler for subscribe event command */
+mlan_status wlan_cmd_subscribe_event(IN mlan_private *pmpriv,
+                                     IN HostCmd_DS_COMMAND *cmd,
+                                     IN t_u16 cmd_action,
+                                     IN t_void *pioctl_buf);
+int wlan_parse_getdata(HostCmd_DS_COMMAND *resp, mlan_ds_subscribe_evt *sub_evt);
+#endif
+
+/** Handler to get current operating class */
+/* For several features, such as DPP and MBO, we need the global operating class. */
+mlan_status wlan_get_global_nonglobal_oper_class(
+    mlan_private *pmpriv, t_u8 channel, t_u8 bw, t_u8 *oper_class, t_u8 *global_op_class);
+
+#define wlan_get_curr_oper_class(pmpriv, channel, bw, oper_class) \
+    wlan_get_global_nonglobal_oper_class(pmpriv, channel, bw, oper_class, MNULL)
+#define wlan_get_curr_global_oper_class(pmpriv, channel, bw, oper_class) \
+    wlan_get_global_nonglobal_oper_class(pmpriv, channel, bw, MNULL, oper_class)
+
+/** Handler to add supported operating class IE */
+int wlan_add_supported_oper_class_ie(mlan_private *pmpriv, t_u8 **pptlv_out, t_u8 curr_oper_class);
+
+/** rx handler for station/uap mode */
+mlan_status wlan_ops_process_rx_packet(IN t_void *adapter, IN pmlan_buffer pmbuf);
+/** Process received packet */
+mlan_status wlan_process_rx_packet(pmlan_adapter pmadapter, pmlan_buffer pmbuf);
+/** ioctl handler for station mode */
+mlan_status wlan_ops_sta_ioctl(t_void *adapter, pmlan_ioctl_req pioctl_req);
+
+/** cmd handler for station mode */
+mlan_status wlan_ops_sta_prepare_cmd(IN t_void *priv,
+                                     IN t_u16 cmd_no,
+                                     IN t_u16 cmd_action,
+                                     IN t_u32 cmd_oid,
+                                     IN t_void *pioctl_buf,
+                                     IN t_void *pdata_buf,
+                                     IN t_void *pcmd_buf);
+
+/** cmdresp handler for station mode */
+mlan_status wlan_ops_sta_process_cmdresp(IN t_void *priv, IN t_u16 cmdresp_no, IN t_void *pcmd_buf, IN t_void *pioctl);
+
+/** Scan for networks */
+mlan_status wlan_scan_networks(IN mlan_private *pmpriv,
+                               IN t_void *pioctl_buf,
+                               IN const wlan_user_scan_cfg *puser_scan_in);
+
+bool wlan_active_scan_req_for_passive_chan(IN mlan_private *pmpriv, IN wlan_user_scan_cfg *puser_scan_in);
+
+/** Scan command handler */
+mlan_status wlan_cmd_802_11_scan(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *pcmd, IN t_void *pdata_buf);
+
+/** Handler for scan command response */
+mlan_status wlan_ret_802_11_scan(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf);
+
+#if CONFIG_EXT_SCAN_SUPPORT
+/** Extended scan command handler */
+mlan_status wlan_cmd_802_11_scan_ext(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *pcmd, IN t_void *pdata_buf);
+/** Handler for extended scan command response */
+mlan_status wlan_ret_802_11_scan_ext(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf);
+/** Handler event for extended scan report */
+mlan_status wlan_handle_event_ext_scan_report(IN mlan_private *pmpriv, IN t_u8 *pmbuf);
+#endif
+
+/** check network compatibility */
+t_s32 wlan_is_network_compatible(IN mlan_private *pmpriv, IN t_u32 index, IN mlan_bss_mode mode);
+
+/** Find an SSID in a list */
+t_s32 wlan_find_ssid_in_list(IN pmlan_private pmpriv, IN mlan_802_11_ssid *ssid, IN t_u8 *bssid, IN mlan_bss_mode mode);
+
+/** Find a BSSID in a list */
+t_s32 wlan_find_bssid_in_list(IN mlan_private *pmpriv, IN const t_u8 *bssid, IN mlan_bss_mode mode);
+
+/** Compare two SSIDs */
+t_s32 wlan_ssid_cmp(IN pmlan_adapter pmadapter, IN mlan_802_11_ssid *ssid1, IN mlan_802_11_ssid *ssid2);
+
+/** Associate */
+mlan_status wlan_associate(IN mlan_private *pmpriv, IN t_void *pioctl_buf, IN BSSDescriptor_t *pbss_desc);
+
+/** Associate command handler */
+mlan_status wlan_cmd_802_11_associate(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+
+/** Handler for association command response */
+mlan_status wlan_ret_802_11_associate(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf);
+
+/** Reset connected state */
+t_void wlan_reset_connect_state(IN pmlan_private priv, IN t_u8 drv_disconnect);
+
+t_void wlan_handle_disconnect_event(pmlan_private pmpriv);
+
+mlan_status wlan_ret_802_11_deauthenticate(IN pmlan_private pmpriv,
+                                           IN HostCmd_DS_COMMAND *resp,
+                                           IN mlan_ioctl_req *pioctl_buf);
+
+/** convert band to radio type */
+t_u8 wlan_band_to_radio_type(IN t_u8 band);
+
+/** Disconnect */
+/* Temporary disable prototype. Same name function present in wmsdk */
+/* mlan_status wlan_disconnect(IN mlan_private * pmpriv, */
+/*                             IN mlan_ioctl_req * pioctl_req, */
+/*                             IN mlan_802_11_mac_addr * mac); */
+
+/** Get Channel-Frequency-Power by band and channel */
+const chan_freq_power_t *wlan_get_cfp_by_band_and_channel(pmlan_adapter pmadapter,
+                                                          t_u16 band,
+                                                          t_u16 channel,
+                                                          region_chan_t *region_channel);
+/** Find Channel-Frequency-Power by band and channel */
+const chan_freq_power_t *wlan_find_cfp_by_band_and_channel(mlan_adapter *pmadapter, t_u16 band, t_u16 channel);
+/** Find Channel-Frequency-Power by band and frequency */
+const chan_freq_power_t *wlan_find_cfp_by_band_and_freq(mlan_adapter *pmadapter, t_u16 band, t_u32 freq);
+/** Get Tx power of channel from Channel-Frequency-Power */
+t_u8 wlan_get_txpwr_of_chan_from_cfp(mlan_private *pmpriv, t_u8 channel);
+
+
+/* Rate related functions */
+/** Convert index into data rate */
+#ifdef SD8801
+t_u32 wlan_index_to_data_rate(pmlan_adapter pmadapter, t_u8 index, t_u8 ht_info);
+#else
+t_u32 wlan_index_to_data_rate(pmlan_adapter pmadapter,
+                              t_u8 index,
+                              t_u8 tx_rate_info
+#if CONFIG_11AX
+                              ,
+                              t_u8 ext_rate_info
+#endif
+);
+#endif
+/** Get active data rates */
+t_u32 wlan_get_active_data_rates(mlan_private *pmpriv,
+                                 mlan_bss_mode bss_mode,
+                                 t_u16 config_bands,
+                                 WLAN_802_11_RATES rates);
+/** Get supported data rates */
+t_u32 wlan_get_supported_rates(mlan_private *pmpriv,
+                               mlan_bss_mode bss_mode,
+                               t_u16 config_bands,
+                               WLAN_802_11_RATES rates);
+/** Check if rate is auto */
+bool wlan_is_rate_auto(mlan_private *pmpriv);
+/** Get rate index */
+int wlan_get_rate_index(pmlan_adapter pmadapter, t_u16 *rate_bitmap, int size);
+
+/* CFP related functions */
+/** Region code index table */
+extern t_u16 region_code_index[MRVDRV_MAX_REGION_CODE];
+
+
+/** The table to keep CFP code for A */
+extern t_u16 cfp_code_index_a[MRVDRV_MAX_CFP_CODE_A];
+/** Set region table */
+mlan_status wlan_set_regiontable(mlan_private *pmpriv, t_u8 region, t_u16 band);
+/** Get radar detection requirements*/
+t_bool wlan_get_cfp_radar_detect(mlan_private *priv, t_u8 chnl);
+/** check if scan type is passive for b/g band*/
+t_bool wlan_bg_scan_type_is_passive(mlan_private *priv, t_u8 chnl);
+t_u8 wlan_convert_v14_rate_ht_info(t_u8 ht_info);
+/** Check if channel number is valid */
+t_bool wlan_is_channel_valid(t_u8 chan_num);
+/** Check if radio mode number is valid */
+t_bool wlan_is_radio_mode_valid(t_u8 mode);
+/** Check if channel number and its frequency is valid */
+t_bool wlan_is_channel_and_freq_valid(mlan_adapter *pmadapter, t_u8 chan_num, t_u16 chan_freq);
+/** Set Custom CFP Table */
+#if CONFIG_5GHz_SUPPORT
+mlan_status wlan_set_custom_cfp_table(wifi_chanlist_t *chanlist, t_u8 *cfp_no_bg, t_u8 *cfp_no_a);
+void wlan_set_custom_regiontable(mlan_private *pmpriv, t_u8 cfp_no_bg, t_u8 cfp_no_a);
+#else
+mlan_status wlan_set_custom_cfp_table(wifi_chanlist_t *chanlist, t_u8 *cfp_no_bg);
+void wlan_set_custom_regiontable(mlan_private *pmpriv, t_u8 cfp_no_bg);
+#endif
+/** Get the list of active channels */
+void wlan_get_active_channel_list(mlan_private *pmpriv, t_u8 *chan_list, t_u8 *num_chans, t_u16 acs_band);
+
+/* 802.11D related functions */
+/** Initialize 11D */
+t_void wlan_11d_priv_init(mlan_private *pmpriv);
+/** Initialize 11D */
+t_void wlan_11d_init(mlan_adapter *pmadapter);
+/** Enable 11D support */
+t_u16 wlan_enable_11d_support(mlan_private *pmpriv);
+t_u16 wlan_11d_support_APIs(mlan_private *pmpriv);
+/** Get if 11D support is enabled */
+t_bool wlan_11d_support_is_enabled(mlan_private *pmpriv);
+/** Get if 11D is enabled */
+t_bool wlan_11d_is_enabled(mlan_private *pmpriv);
+/** 11D Region code to country code string */
+const t_u8 *wlan_11d_code_2_region(pmlan_adapter pmadapter, t_u8 code);
+/**converts region string to integer code*/
+mlan_status wlan_11d_region_2_code(pmlan_adapter pmadapter, t_u8 *region, OUT t_u8 *code);
+/** Store 11D domain info */
+mlan_status wlan_11d_set_domain_info(mlan_private *pmpriv,
+                                     t_u16 band,
+                                     const t_u8 country_code[COUNTRY_CODE_LEN],
+                                     t_u8 num_sub_band,
+                                     IEEEtypes_SubbandSet_t *sub_band_list);
+
+/** Get if priv is station */
+t_bool wlan_is_station(mlan_private *pmpriv);
+/** Command handler for 11D country info */
+mlan_status wlan_cmd_802_11d_domain_info(mlan_private *pmpriv, HostCmd_DS_COMMAND *pcmd, t_u16 cmd_action);
+/** Convert channel to frequency */
+t_u32 wlan_11d_chan_2_freq(pmlan_adapter pmadapter, t_u8 chan, t_u16 band);
+/** Set 11D universal table */
+mlan_status wlan_11d_set_universaltable(mlan_private *pmpriv, t_u16 band);
+/** Clear 11D region table */
+mlan_status wlan_11d_clear_parsedtable(mlan_private *pmpriv);
+/** Create 11D country information for downloading */
+mlan_status wlan_11d_create_dnld_countryinfo(mlan_private *pmpriv, t_u16 band);
+/** Get scan type from 11D info */
+mlan_scan_type wlan_11d_get_scan_type(mlan_private *pmpriv,
+                                      t_u16 band,
+                                      t_u8 chan,
+                                      parsed_region_chan_11d_t *parsed_region_chan);
+/** Parse 11D country info */
+mlan_status wlan_11d_parse_dnld_countryinfo(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc);
+/** Prepare 11D domain information for download */
+mlan_status wlan_11d_prepare_dnld_domain_info_cmd(mlan_private *pmpriv);
+/** Parse 11D country information into domain info */
+mlan_status wlan_11d_parse_domain_info(pmlan_adapter pmadapter,
+                                       IEEEtypes_CountryInfoFullSet_t *country_info,
+                                       t_u16 band,
+                                       parsed_region_chan_11d_t *parsed_region_chan);
+/** Configure 11D domain info command */
+mlan_status wlan_11d_cfg_domain_info(IN pmlan_adapter pmadapter, IN mlan_ioctl_req *pioctl_req);
+
+mlan_status wlan_11d_cfg_ioctl(IN mlan_private *pmpriv, IN pmlan_ioctl_req pioctl_req);
+/** Handle 11D domain information from UAP */
+mlan_status wlan_11d_handle_uap_domain_info(mlan_private *pmpriv, t_u16 band, t_u8 *domain_tlv, t_void *pioctl_buf);
+
+/** This function converts region string to CFP table code */
+mlan_status wlan_misc_country_2_cfp_table_code(IN pmlan_adapter pmadapter,
+                                               IN t_u8 *country_code,
+                                               OUT t_u8 *cfp_bg,
+                                               OUT t_u8 *cfp_a);
+/** check if station list is empty */
+t_u8 wlan_is_station_list_empty(mlan_private *priv);
+/** get station node */
+sta_node *wlan_get_station_entry(mlan_private *priv, t_u8 *mac);
+/** delete station list */
+t_void wlan_delete_station_list(pmlan_private priv);
+/** delete station entry */
+t_void wlan_delete_station_entry(mlan_private *priv, t_u8 *mac);
+/** add station entry */
+sta_node *wlan_add_station_entry(mlan_private *priv, t_u8 *mac);
+/** process uap rx packet */
+
+void wlan_check_sta_capability(pmlan_private priv, pmlan_buffer pevent, sta_node *sta_ptr);
+
+#if CONFIG_RF_TEST_MODE
+mlan_status wlan_ret_mfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, void *pioctl_buf);
+mlan_status wlan_misc_ioctl_rf_test_cfg(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req);
+#endif
+
+#if CONFIG_11R
+t_u8 wlan_ft_akm_is_used(mlan_private *pmpriv, t_u8 *rsn_ie);
+#endif
+
+/** find specific ie */
+t_u8 *wlan_get_specific_ie(pmlan_private priv, t_u8 *ie_buf, t_u8 ie_len, IEEEtypes_ElementId_e id, t_u8 ext_id);
+
+/**
+ *  @brief This function checks tx_pause flag for peer
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ra       Address of the receiver STA
+ *
+ *  @return 	    MTRUE or MFALSE
+ */
+INLINE
+static int wlan_is_tx_pause(mlan_private *priv, t_u8 *ra)
+{
+    sta_node *sta_ptr = MNULL;
+    sta_ptr           = wlan_get_station_entry(priv, ra);
+    if (sta_ptr != MNULL)
+    {
+        return sta_ptr->tx_pause;
+    }
+    return MFALSE;
+}
+
+
+t_bool wlan_check_channel_by_region_table(mlan_private *pmpriv, t_u8 chan_num);
+
+
+mlan_status wlan_cmd_get_hw_spec(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *pcmd);
+mlan_status wlan_ret_get_hw_spec(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf);
+
+
+mlan_status wlan_cmd_802_11_rf_antenna(IN pmlan_private pmpriv,
+                                       IN HostCmd_DS_COMMAND *cmd,
+                                       IN t_u16 cmd_action,
+                                       IN t_void *pdata_buf);
+#if CONFIG_NET_MONITOR
+mlan_status wlan_cmd_802_11_net_monitor(IN pmlan_private pmpriv,
+                                        IN HostCmd_DS_COMMAND *cmd,
+                                        IN t_u16 cmd_action,
+                                        IN t_void *pdata_buf);
+#endif
+
+#ifdef DEBUG_LEVEL1
+mlan_status wlan_set_drvdbg(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+#endif
+
+void wlan_add_ext_capa_info_ie(IN mlan_private *pmpriv, IN BSSDescriptor_t *pbss_desc, OUT t_u8 **pptlv_out);
+
+
+#ifdef WLAN_LOW_POWER_ENABLE
+mlan_status wlan_misc_ioctl_low_pwr_mode(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+#endif // WLAN_LOW_POWER_ENABLE
+
+#ifdef OTP_CHANINFO
+mlan_status wlan_ret_chan_region_cfg(IN pmlan_private pmpriv,
+                                     IN HostCmd_DS_COMMAND *resp,
+                                     IN mlan_ioctl_req *pioctl_buf);
+
+void wlan_add_fw_cfp_tables(pmlan_private pmpriv, t_u8 *buf, t_u16 buf_left);
+
+void wlan_free_fw_cfp_tables(mlan_adapter *pmadapter);
+
+// mlan_status wlan_misc_chan_reg_cfg(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+#endif
+
+#if CONFIG_COMPRESS_TX_PWTBL
+mlan_status wlan_cmd_region_power_cfg(pmlan_private pmpriv,
+                                      HostCmd_DS_COMMAND *cmd,
+                                      t_u16 cmd_action,
+                                      t_void *pdata_buf);
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+mlan_status wlan_cmd_gpio_tsf_latch(
+    pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, mlan_ioctl_req *pioctl_buf, t_void *pdata_buf);
+mlan_status wlan_ret_gpio_tsf_latch(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+mlan_status wlan_misc_gpio_tsf_latch_config(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req);
+mlan_status wlan_misc_get_tsf_info(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req);
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+#if CONFIG_MULTI_CHAN
+mlan_status wlan_cmd_multi_chan_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+
+mlan_status wlan_ret_multi_chan_cfg(pmlan_private pmpriv, const HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+
+mlan_status wlan_cmd_multi_chan_policy(pmlan_private pmpriv,
+                                       HostCmd_DS_COMMAND *cmd,
+                                       t_u16 cmd_action,
+                                       t_void *pdata_buf);
+
+mlan_status wlan_ret_multi_chan_policy(pmlan_private pmpriv,
+                                       const HostCmd_DS_COMMAND *resp,
+                                       mlan_ioctl_req *pioctl_buf);
+
+mlan_status wlan_cmd_drcs_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+
+mlan_status wlan_ret_drcs_cfg(pmlan_private pmpriv, const HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+
+#endif
+
+mlan_status wlan_cmd_tx_frame(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+
+#if CONFIG_ECSA
+mlan_status wlan_misc_ioctl_operclass_validation(pmlan_adapter pmadapter, mlan_ioctl_req *pioctl_req);
+mlan_status wlan_misc_ioctl_oper_class(pmlan_adapter pmadapter, mlan_ioctl_req *pioctl_req);
+mlan_status wlan_check_operclass_validation(mlan_private *pmpriv, t_u8 channel, t_u8 oper_class);
+#endif
+
+#if CONFIG_RX_ABORT_CFG
+mlan_status wlan_cmd_rx_abort_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+mlan_status wlan_cmd_rx_abort_cfg_ext(pmlan_private pmpriv,
+                                      HostCmd_DS_COMMAND *cmd,
+                                      t_u16 cmd_action,
+                                      t_void *pdata_buf);
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+mlan_status wlan_cmd_cck_desense_cfg(pmlan_private pmpriv,
+                                     HostCmd_DS_COMMAND *cmd,
+                                     t_u16 cmd_action,
+                                     t_void *pdata_buf);
+#endif
+
+#define BW_20MHZ 0
+#define BW_40MHZ 1
+#define BW_80MHZ 2
+
+#if CONFIG_TURBO_MODE
+int wlan_get_set_turbo_mode(t_u16 action, t_u8 *mode, mlan_bss_type bss_type);
+#endif
+
+
+/**
+ *  @brief RA based queueing
+ *
+ *  @param priv                 A pointer to mlan_private structure
+ *
+ *  @return 	   	        MTRUE or MFALSE
+ */
+INLINE
+static t_u8 queuing_ra_based(pmlan_private priv)
+{
+    /*
+     * Currently we assume if we are in Infra, then DA=RA. This might not be
+     * true in the future
+     */
+    if ((priv->bss_mode == MLAN_BSS_MODE_INFRA) && (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_STA))
+    {
+        return MFALSE;
+    }
+
+    return MTRUE;
+}
+
+/**
+ *  @brief Copy Rates
+ *
+ *  @param dest                 A pointer to Dest Buf
+ *  @param pos		        The position for copy
+ *  @param src		        A pointer to Src Buf
+ *  @param len                  The len of Src Buf
+ *
+ *  @return 	   	        Number of Rates copied
+ */
+INLINE
+static t_u32 wlan_copy_rates(t_u8 *dest, t_u32 pos, t_u8 *src, int len)
+{
+    int i;
+
+    for (i = 0; i < len && src[i]; i++)
+    {
+        if (pos >= sizeof(WLAN_802_11_RATES))
+        {
+            break;
+        }
+        dest[pos] = src[i];
+        pos++;
+    }
+
+    return pos;
+}
+
+/**
+ *  @brief strlen
+ *
+ *  @param str		        A pointer to string
+ *
+ *  @return 	   	        Length of string
+ */
+INLINE
+static t_u32 wlan_strlen(const t_s8 *str)
+{
+    t_u32 i;
+
+    for (i = 0; str[i] != '\0'; i++)
+    {
+    }
+    return i;
+}
+
+/**
+ *  @brief iscdigit
+ *
+ *  @param chr                  A char
+ *
+ *  @return                     Non zero if chr is a hex, else 0
+ */
+INLINE
+static t_u32 wlan_isxdigit(t_u8 chr)
+{
+    return ((chr <= 'f' && chr >= 'a') || (chr <= 'F' && chr >= 'A') || (chr <= '9' && chr >= '0'));
+}
+
+/**
+ *  @brief isspace
+ *
+ *  @param                       A chr
+ *
+ *  @return                      Non zero if chr is space etc, else 0
+ */
+INLINE
+static t_u32 wlan_isspace(t_u8 chr)
+{
+    return (chr <= ' ' && (chr == ' ' || (chr <= 13 && chr >= 9)));
+}
+
+/** delay unit */
+typedef enum _delay_unit
+{
+    USEC,
+    MSEC,
+    SEC,
+} t_delay_unit;
+
+
+/** delay function wrapper */
+#define wlan_delay(p, n) wlan_delay_func(p, n, SEC)
+/** delay function wrapper */
+#define wlan_mdelay(p, n) wlan_delay_func(p, n, MSEC)
+/** delay function wrapper */
+#define wlan_udelay(p, n) wlan_delay_func(p, n, USEC)
+
+/** Function to check if any command is pending in the queue */
+#define IS_COMMAND_PENDING(pmadapter)                                                    \
+    ((cmd_ctrl_node *)util_peek_list(pmadapter->pmoal_handle, &pmadapter->cmd_pending_q, \
+                                     pmadapter->callbacks.moal_spin_lock, pmadapter->callbacks.moal_spin_unlock))
+
+/** Get BSS number from priv */
+#define GET_BSS_NUM(priv) (priv)->bss_num
+/**
+ *  @brief This function returns priv based on the BSS num and BSS type
+ *
+ *  @param pmadapter A pointer to mlan_adapter
+ *  @param bss_num   BSS number
+ *  @param bss_type  BSS type
+ *
+ *  @return          Pointer to mlan_private
+ */
+INLINE
+static mlan_private *wlan_get_priv_by_id(mlan_adapter *pmadapter, t_u32 bss_num, t_u32 bss_type)
+{
+    int i;
+
+    for (i = 0; i < MIN(pmadapter->priv_num, MLAN_MAX_BSS_NUM); i++)
+    {
+        if (pmadapter->priv[i] != MNULL)
+        {
+            if ((pmadapter->priv[i]->bss_num == bss_num) && (pmadapter->priv[i]->bss_type == bss_type))
+            {
+                return (pmadapter->priv[i]);
+            }
+        }
+    }
+    return MNULL;
+}
+
+/**
+ *  @brief This function returns first available priv
+ *  based on the BSS role
+ *
+ *  @param pmadapter A pointer to mlan_adapter
+ *  @param bss_role  BSS role or MLAN_BSS_ROLE_ANY
+ *
+ *  @return          Pointer to mlan_private
+ */
+INLINE
+static mlan_private *wlan_get_priv(mlan_adapter *pmadapter, mlan_bss_role bss_role)
+{
+    int i;
+
+    for (i = 0; i < MIN(pmadapter->priv_num, MLAN_MAX_BSS_NUM); i++)
+    {
+        if (pmadapter->priv[i] != MNULL)
+        {
+            if (bss_role == MLAN_BSS_ROLE_ANY || GET_BSS_ROLE(pmadapter->priv[i]) == bss_role)
+            {
+                return (pmadapter->priv[i]);
+            }
+        }
+    }
+    return MNULL;
+}
+
+/**
+ *  @brief This function counts the number of occurences for a certain
+ *  condition among privs.  Which privs are checked can be configured
+ *  via a second condition.
+ *
+ *  @param pmadapter  A pointer to mlan_adapter
+ *  @param count_cond Function pointer to condition to count on privs
+ *  @param check_cond Function pointer to condition to decide whether priv
+ *                    should be counted or not.  Use MNULL to check all privs.
+ *
+ *  @return          Count of privs where count_cond returned MTRUE.
+ */
+INLINE
+static int wlan_count_priv_cond(mlan_adapter *pmadapter,
+                                t_bool (*count_cond)(IN pmlan_private pmpriv),
+                                t_bool (*check_cond)(IN pmlan_private pmpriv))
+{
+    pmlan_private pmpriv;
+    int count = 0;
+    t_u8 i;
+
+    if (pmadapter == MNULL || count_cond == MNULL)
+    {
+        return 0;
+    }
+
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        pmpriv = pmadapter->priv[i];
+        if (pmpriv != MNULL)
+        {
+            if ((check_cond == MNULL) || check_cond(pmpriv))
+            {
+                if (count_cond(pmpriv))
+                {
+                    count++;
+                }
+            }
+        }
+    }
+
+    return count;
+}
+
+/**
+ *  @brief This function runs a procedure on each priv.
+ *  Which privs it is run on can be configured via a condition.
+ *
+ *  @param pmadapter  A pointer to mlan_adapter
+ *  @param operation  Function pointer to produedure to operate on priv
+ *  @param check_cond Function pointer to condition to decide whether priv
+ *                    operated on or not.  Use MNULL to run on all privs.
+ *
+ *  @return           Number of privs that operation was run on.
+ */
+INLINE
+static int wlan_do_task_on_privs(mlan_adapter *pmadapter,
+                                 t_void (*operation)(IN pmlan_private pmpriv),
+                                 t_bool (*check_cond)(IN pmlan_private pmpriv))
+{
+    pmlan_private pmpriv;
+    int count = 0;
+    t_u8 i;
+
+    if (pmadapter == MNULL || operation == MNULL)
+    {
+        return 0;
+    }
+
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        pmpriv = pmadapter->priv[i];
+        if (pmpriv != MNULL)
+        {
+            if ((check_cond == MNULL) || check_cond(pmpriv))
+            {
+                operation(pmpriv);
+                count++;
+            }
+        }
+    }
+
+    return count;
+}
+
+/**
+ *  @brief This function builds a list of privs that test for a condition
+ *  This is useful if you need to do a number of operations on the same set
+ *  of privs.  For one-off tasks, the above two functions might be better.
+ *
+ *  @param pmadapter  A pointer to mlan_adapter
+ *  @param check_cond Function pointer to condition to decide whether priv
+ *                    should be placed in the list.
+ *  @param ppriv_list Output param.  Externally supplied array of mlan_private*
+ *                    to hold priv's that test positive with check_cond.
+ *                    Array size should be at least pmadapter->priv_num.
+ *
+ *  @return          Number of privs in ppriv_list
+ *
+ *  @sa              wlan_count_priv_cond
+ */
+INLINE
+static int wlan_get_privs_by_cond(mlan_adapter *pmadapter,
+                                  t_bool (*check_cond)(IN pmlan_private pmpriv),
+                                  mlan_private **ppriv_list)
+{
+    pmlan_private pmpriv;
+    int count = 0;
+    t_u8 i;
+
+    if (pmadapter == MNULL || check_cond == MNULL || ppriv_list == MNULL)
+    {
+        return 0;
+    }
+
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        pmpriv = pmadapter->priv[i];
+        if (pmpriv != MNULL)
+        {
+            if (check_cond(pmpriv))
+            {
+                ppriv_list[count++] = pmpriv;
+            }
+        }
+    }
+
+    return count;
+}
+
+/**
+ *  @brief This function builds a list of privs that test against two conditions
+ *  This is useful if you need to do a number of operations on the same set
+ *  of privs.  Can choose whether both conditions (AND) or either condition (OR)
+ *  is required.
+ *
+ *  @param pmadapter      A pointer to mlan_adapter
+ *  @param check_cond     Function pointer to condition to decide whether priv
+ *                        should be placed in the list.
+ *  @param check_cond_2   Function pointer to second condition to check.
+ *  @param and_conditions If MTRUE, both conditions must be met (AND),
+ *                        else either condition can be met (OR).
+ *  @param ppriv_list     Output param.  Externally supplied array of mlan_private*
+ *                        to hold priv's that test positive with check_cond.
+ *                        Array size should be at least pmadapter->priv_num.
+ *
+ *  @return          Number of privs in ppriv_list
+ *
+ *  @sa              wlan_count_priv_cond, wlan_get_privs_by_cond
+ */
+INLINE
+static int wlan_get_privs_by_two_cond(mlan_adapter *pmadapter,
+                                      t_bool (*check_cond)(IN pmlan_private pmpriv),
+                                      t_bool (*check_cond_2)(IN pmlan_private pmpriv),
+                                      t_bool and_conditions,
+                                      mlan_private **ppriv_list)
+{
+    pmlan_private pmpriv;
+    int count = 0;
+    t_u8 i;
+
+    if (pmadapter == MNULL || check_cond == MNULL || check_cond_2 == MNULL || ppriv_list == MNULL)
+    {
+        return 0;
+    }
+
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        pmpriv = pmadapter->priv[i];
+        if (pmpriv != MNULL)
+        {
+            if (and_conditions)
+            {
+                if (check_cond(pmpriv) && check_cond_2(pmpriv))
+                {
+                    ppriv_list[count++] = pmpriv;
+                }
+            }
+            else
+            {
+                if (check_cond(pmpriv) || check_cond_2(pmpriv))
+                {
+                    ppriv_list[count++] = pmpriv;
+                }
+            }
+        }
+    }
+
+    return count;
+}
+
+#if CONFIG_WMM_UAPSD
+/** Check if there is no packet */
+t_u8 wifi_check_no_packet_indication(mlan_private *priv);
+/** Check if this is the last packet */
+t_u8 wifi_check_last_packet_indication(mlan_private *priv);
+#endif
+
+mlan_status wlan_cmd_hs_wakeup_reason(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_void *pdata_buf);
+
+mlan_status wlan_ret_hs_wakeup_reason(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+
+#if CONFIG_FW_VDLL
+mlan_status wlan_download_vdll_block(mlan_adapter *pmadapter, t_u8 *block, t_u16 block_len);
+mlan_status wlan_process_vdll_event(pmlan_private pmpriv, t_u8 *pevent);
+#endif
+
+#if CONFIG_WIFI_IND_RESET
+mlan_status wlan_misc_ioctl_ind_rst_cfg(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req);
+mlan_status wlan_cmd_ind_rst_cfg(HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+
+mlan_status wlan_ret_ind_rst_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+#endif
+
+mlan_status wlan_cmd_boot_sleep(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf);
+
+mlan_status wlan_ret_boot_sleep(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+
+t_bool wlan_is_etsi_country(pmlan_adapter pmadapter, t_u8 *country_code);
+
+#endif /* !_MLAN_MAIN_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_mbo.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_mbo.h
new file mode 100644
index 0000000000..7aeac18b50
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_mbo.h
@@ -0,0 +1,45 @@
+/** @file mlan_mbo.h
+ *
+ *  @brief Interface for the MBO feature implemented in mlan_mbo.c
+ *
+ *  Driver interface functions and type declarations for the process MBO
+ *    module implemented in mlan_mbo.c.
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    8/SEP/2022: initial version
+********************************************************/
+#ifndef _MLAN_MBO_H
+#define _MLAN_MBO_H
+
+#if CONFIG_DRIVER_MBO
+/** MBO attributes ID */
+enum MBO_ATTRIB_ID
+{
+    MBO_AP_CAP_IND = 1,
+    MBO_NON_PERFER_CH_REPORT,
+    MBO_CELLULAR_DATA_CAP,
+    MBO_ASSOC_DISALLOWED,
+    MBO_CELLULAR_DATA_CONNECT_PREFER,
+    MBO_TRANSIT_REASON,
+    MBO_TRANSIT_REJECCT_REASON,
+    MBO_ASSOC_RETRY_DELAY,
+};
+
+extern const t_u8 mbo_oui[];
+
+t_u8 *wlan_add_mbo_oui(t_u8 *oui);
+t_u8 *wlan_add_mbo_oui_type(t_u8 *oui_type);
+t_u8 *wlan_add_mbo_attr_id(t_u8 *attr_id);
+t_u8 *wlan_add_mbo_cellular_cap(t_u8 *attrib);
+t_u8 *wlan_add_mbo_prefer_ch(t_u8 *attrib, t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1);
+void wlan_send_mgmt_wnm_notification(
+    t_u8 *src_addr, t_u8 *dst_addr, t_u8 *target_bssid, t_u8 *tag_nr, t_u8 tag_len, bool protect);
+#endif
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_meas.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_meas.h
new file mode 100644
index 0000000000..4de23be982
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_meas.h
@@ -0,0 +1,40 @@
+/**
+ *  @file mlan_meas.h
+ *
+ *  @brief Interface for the measurement module implemented in mlan_meas.c
+ *
+ *  Driver interface functions and type declarations for the measurement module
+ *    implemented in mlan_meas.c
+ *
+ *  @sa mlan_meas.c
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*************************************************************
+Change Log:
+    03/25/2009: initial version
+************************************************************/
+
+#ifndef _MLAN_MEAS_H_
+#define _MLAN_MEAS_H_
+
+#include "mlan_fw.h"
+
+/* Send a given measurement request to the firmware, report back the result */
+extern int wlan_meas_util_send_req(mlan_private *pmpriv,
+                                   HostCmd_DS_MEASUREMENT_REQUEST *pmeas_req,
+                                   t_u32 wait_for_resp_timeout,
+                                   pmlan_ioctl_req pioctl_req,
+                                   HostCmd_DS_MEASUREMENT_REPORT *pmeas_rpt);
+
+/* Setup a measurement command before it is sent to the firmware */
+extern int wlan_meas_cmd_process(mlan_private *pmpriv, HostCmd_DS_COMMAND *pcmd_ptr, const t_void *pinfo_buf);
+
+/* Handle a given measurement command response from the firmware */
+extern int wlan_meas_cmdresp_process(mlan_private *pmpriv, const HostCmd_DS_COMMAND *resp);
+
+#endif /* _MLAN_MEAS_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_remap_mem_operations.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_remap_mem_operations.h
new file mode 100644
index 0000000000..895da3b885
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_remap_mem_operations.h
@@ -0,0 +1,46 @@
+/** @file mlan_remap_mem_operations.h
+ *
+ *  @brief This file contains redefinition of memory routines
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*
+ * File added for wmsdk. Not present in original mlan release.
+ *
+ * Purpose: The mlan release source files contain non-standard (libc)
+ * prototypes for memcpy, memmove, memcmp, etc. This causes problems when
+ * mlan header files are included by the remaining code. We work around
+ * this problem by remapping these operations to standard functions.
+ *
+ * IMPORTANT: Ensure that this file is included in every mlan source file
+ * which used mem* operations. ENSURE that this is the last file included
+ * in the include header list.
+ */
+
+#ifdef __memset
+#undef __memset
+#endif
+/** Memset routine */
+#define __memset(adapter, s, c, len) memset((void *)(s), (int)(c), (size_t)(len))
+
+#ifdef __memmove
+#undef __memmove
+#endif
+/** Memmove routine */
+#define __memmove(adapter, dest, src, len) memmove((void *)(dest), (const void *)(src), (size_t)(len))
+
+#ifdef __memcpy
+#undef __memcpy
+#endif
+/** Memcpy routine */
+#define __memcpy(adapter, to, from, len) memcpy((void *)(to), (const void *)(from), (size_t)(len))
+
+#ifdef __memcmp
+#undef __memcmp
+#endif
+/** Memcmp routine */
+#define __memcmp(adapter, s1, s2, len) memcmp((const void *)(s1), (const void *)(s2), (size_t)(len))
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_uap.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_uap.h
new file mode 100644
index 0000000000..856e1c7558
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_uap.h
@@ -0,0 +1,84 @@
+/** @file mlan_uap.h
+ *
+ *  @brief This file contains related macros, enum, and struct
+ *  of uap functionalities
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    02/05/2009: initial version
+********************************************************/
+
+#ifndef _MLAN_UAP_H_
+#define _MLAN_UAP_H_
+
+/** Convert TxPD to little endian format from CPU format */
+#define uap_endian_convert_TxPD(x) \
+    do                             \
+    {                              \
+    } while (0)
+/** Convert RxPD from little endian format to CPU format */
+#define uap_endian_convert_RxPD(x) \
+    do                             \
+    {                              \
+    } while (0)
+
+/** Band config 5GHz */
+#define UAP_BAND_CONFIG_5GHZ 0x01
+
+/** Packet forwarding to be done by FW or host */
+#define PKT_FWD_FW_BIT 0x01U
+/** Intra-BSS broadcast packet forwarding allow bit */
+#define PKT_FWD_INTRA_BCAST 0x02
+/** Intra-BSS unicast packet forwarding allow bit */
+#define PKT_FWD_INTRA_UCAST 0x04
+/** Inter-BSS unicast packet forwarding allow bit */
+#define PKT_FWD_INTER_UCAST 0x08
+/** Intra-BSS unicast packet */
+#define PKT_INTRA_UCAST 0x01
+/** Inter-BSS unicast packet */
+#define PKT_INTER_UCAST 0x02
+/** Enable Host PKT forwarding */
+#define PKT_FWD_ENABLE_BIT 0x01U
+
+
+
+mlan_status wlan_ops_uap_ioctl(t_void *adapter, pmlan_ioctl_req pioctl_req);
+
+mlan_status wlan_ops_uap_prepare_cmd(IN t_void *priv,
+                                     IN t_u16 cmd_no,
+                                     IN t_u16 cmd_action,
+                                     IN t_u32 cmd_oid,
+                                     IN t_void *pioctl_buf,
+                                     IN t_void *pdata_buf,
+                                     IN t_void *pcmd_buf);
+
+
+
+int wifi_uap_enable_11d_support(void);
+
+int wifi_uap_group_rekey_timer_getset(uint8_t action, uint32_t *group_rekey_timer);
+
+int wifi_uap_mcbc_rate_getset(uint8_t action, uint16_t *mcbc_rate);
+
+int wifi_uap_tx_power_getset(uint8_t action, uint8_t *tx_power_dbm);
+
+int wifi_set_uap_max_clients(unsigned int *max_sta_num);
+
+int wifi_get_uap_max_clients(unsigned int *max_sta_num);
+
+void wifi_uap_set_ecsa(void);
+
+int wifi_uap_ctrl_deauth(bool enable);
+
+void wifi_uap_set_hidden_ssid(const t_u8 bcast_ssid_ctl);
+
+void wifi_uap_set_htcapinfo(const t_u16 ht_cap_info);
+
+void wifi_uap_set_beacon_period(const t_u16 beacon_period);
+#endif /* _MLAN_UAP_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_util.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_util.h
new file mode 100644
index 0000000000..be3089274e
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_util.h
@@ -0,0 +1,542 @@
+/** @file mlan_util.h
+ *
+ *  @brief This file contains wrappers for linked-list,
+ *  spinlock and timer defines.
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/28/2008: initial version
+******************************************************/
+
+#ifndef _MLAN_UTIL_H_
+#define _MLAN_UTIL_H_
+
+#ifndef MNULL
+#define MNULL ((void *)0)
+#endif
+
+/** Circular doubly linked list */
+typedef struct _mlan_linked_list
+{
+    /** Pointer to previous node */
+    struct _mlan_linked_list *pprev;
+    /** Pointer to next node */
+    struct _mlan_linked_list *pnext;
+} mlan_linked_list, *pmlan_linked_list;
+
+/** List head */
+typedef struct _mlan_list_head
+{
+    /** Pointer to previous node */
+    struct _mlan_linked_list *pprev;
+    /** Pointer to next node */
+    struct _mlan_linked_list *pnext;
+    /** Pointer to lock */
+    OSA_SEMAPHORE_HANDLE_DEFINE(plock);
+} mlan_list_head, *pmlan_list_head;
+
+/**
+ *  @brief This function initializes a list without locking
+ *
+ *  @param phead		List head
+ *
+ *  @return			N/A
+ */
+static INLINE t_void util_init_list(pmlan_linked_list phead)
+{
+    /* Both next and prev point to self */
+    phead->pnext = phead->pprev = (pmlan_linked_list)phead;
+}
+
+/**
+ *  @brief This function initializes a list
+ *
+ *  @param phead		List head
+ *  @param lock_required	A flag for spinlock requirement
+ *  @param moal_init_lock	A pointer to init lock handler
+ *
+ *  @return			N/A
+ */
+static INLINE t_void util_init_list_head(t_void *pmoal_handle,
+                                         pmlan_list_head phead,
+                                         bool lock_required,
+                                         mlan_status (*moal_init_lock)(t_void *handle, t_void *plock))
+{
+    /* Both next and prev point to self */
+    util_init_list((pmlan_linked_list)(void *)phead);
+    if (lock_required != 0U)
+    {
+        (void)moal_init_lock(pmoal_handle, &phead->plock);
+    }
+}
+
+/**
+ *  @brief This function frees a list
+ *
+ *  @param phead		List head
+ *  @param moal_free_lock	A pointer to free lock handler
+ *
+ *  @return			N/A
+ */
+static INLINE t_void util_free_list_head(t_void *pmoal_handle,
+                                         pmlan_list_head phead,
+                                         mlan_status (*moal_free_lock)(t_void *handle, t_void *plock))
+{
+    phead->pprev = phead->pnext = MNULL;
+
+    if (moal_free_lock != MNULL)
+    {
+        (void)moal_free_lock(pmoal_handle, phead->plock);
+    }
+}
+
+/**
+ *  @brief This function peeks into a list
+ *
+ *  @param phead		List head
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return			List node
+ */
+static INLINE pmlan_linked_list util_peek_list(t_void *pmoal_handle,
+                                               pmlan_list_head phead,
+                                               mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                               mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    pmlan_linked_list pnode = MNULL;
+
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, phead->plock);
+    }
+    if (phead->pnext != (pmlan_linked_list)(void *)phead)
+    {
+        pnode = phead->pnext;
+    }
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, phead->plock);
+    }
+    return pnode;
+}
+
+/**
+ *  @brief This function queues a node at the list tail
+ *
+ *  @param phead		List head
+ *  @param pnode		List node to queue
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return			N/A
+ */
+static INLINE t_void util_enqueue_list_tail(t_void *pmoal_handle,
+                                            pmlan_list_head phead,
+                                            pmlan_linked_list pnode,
+                                            mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                            mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    pmlan_linked_list pold_last;
+
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, phead->plock);
+    }
+    pold_last    = phead->pprev;
+    pnode->pprev = pold_last;
+    pnode->pnext = (pmlan_linked_list)(void *)phead;
+
+    phead->pprev = pold_last->pnext = pnode;
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, phead->plock);
+    }
+}
+
+/**
+ *  @brief This function adds a node at the list head
+ *
+ *  @param phead		List head
+ *  @param pnode		List node to add
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return			N/A
+ */
+static INLINE t_void util_enqueue_list_head(t_void *pmoal_handle,
+                                            pmlan_list_head phead,
+                                            pmlan_linked_list pnode,
+                                            mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                            mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    pmlan_linked_list pold_first;
+
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, phead->plock);
+    }
+    pold_first   = phead->pnext;
+    pnode->pprev = (pmlan_linked_list)(void *)phead;
+    pnode->pnext = pold_first;
+
+    phead->pnext = pold_first->pprev = pnode;
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, phead->plock);
+    }
+}
+
+/**
+ *  @brief This function removes a node from the list
+ *
+ *  @param phead		List head
+ *  @param pnode		List node to remove
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return			N/A
+ */
+static INLINE t_void util_unlink_list(t_void *pmoal_handle,
+                                      pmlan_list_head phead,
+                                      pmlan_linked_list pnode,
+                                      mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                      mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    pmlan_linked_list pmy_prev;
+    pmlan_linked_list pmy_next;
+
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, phead->plock);
+    }
+    pmy_prev        = pnode->pprev;
+    pmy_next        = pnode->pnext;
+    pmy_next->pprev = pmy_prev;
+    pmy_prev->pnext = pmy_next;
+
+    pnode->pnext = pnode->pprev = MNULL;
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, phead->plock);
+    }
+}
+
+/**
+ *  @brief This function dequeues a node from the list
+ *
+ *  @param phead		List head
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return			List node
+ */
+static INLINE pmlan_linked_list util_dequeue_list(t_void *pmoal_handle,
+                                                  pmlan_list_head phead,
+                                                  mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                                  mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    pmlan_linked_list pnode;
+
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, phead->plock);
+    }
+    pnode = phead->pnext;
+    if (pnode != MNULL && (pnode != (pmlan_linked_list)(void *)phead))
+    {
+        util_unlink_list(pmoal_handle, phead, pnode, 0, 0);
+    }
+    else
+    {
+        pnode = 0;
+    }
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, phead->plock);
+    }
+    return pnode;
+}
+
+/** Access controlled scalar variable */
+typedef struct _mlan_scalar
+{
+    /** Value */
+    t_s32 value;
+    /** Pointer to lock */
+    t_void *plock;
+    /** Control flags */
+    t_u32 flags;
+} mlan_scalar, *pmlan_scalar;
+
+/** Flag to scalar lock acquired */
+#define MLAN_SCALAR_FLAG_UNIQUE_LOCK MBIT(16)
+
+/** scalar conditional value list */
+typedef enum _MLAN_SCALAR_CONDITIONAL
+{
+    MLAN_SCALAR_COND_EQUAL,
+    MLAN_SCALAR_COND_NOT_EQUAL,
+    MLAN_SCALAR_COND_GREATER_THAN,
+    MLAN_SCALAR_COND_GREATER_OR_EQUAL,
+    MLAN_SCALAR_COND_LESS_THAN,
+    MLAN_SCALAR_COND_LESS_OR_EQUAL
+} MLAN_SCALAR_CONDITIONAL;
+
+/**
+ *  @brief This function initializes a scalar
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param val				Initial scalar value
+ *  @param plock_to_use		A new lock is created if NULL, else lock to use
+ *  @param moal_init_lock	A pointer to init lock handler
+ *
+ *  @return					N/A
+ */
+static INLINE t_void util_scalar_init(t_void *pmoal_handle,
+                                      pmlan_scalar pscalar,
+                                      t_s32 val,
+                                      t_void *plock_to_use,
+                                      mlan_status (*moal_init_lock)(t_void *handle, t_void *plock))
+{
+    pscalar->value = val;
+    pscalar->flags = 0;
+    if (plock_to_use != MNULL)
+    {
+        pscalar->flags &= ~MLAN_SCALAR_FLAG_UNIQUE_LOCK;
+        pscalar->plock = plock_to_use;
+    }
+    else
+    {
+        pscalar->flags |= MLAN_SCALAR_FLAG_UNIQUE_LOCK;
+        (void)moal_init_lock(pmoal_handle, &pscalar->plock);
+    }
+}
+
+/**
+ *  @brief This function frees a scalar
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param moal_free_lock	A pointer to free lock handler
+ *
+ *  @return			N/A
+ */
+static INLINE t_void util_scalar_free(t_void *pmoal_handle,
+                                      pmlan_scalar pscalar,
+                                      mlan_status (*moal_free_lock)(t_void *handle, t_void *plock))
+{
+    if ((pscalar->flags & MLAN_SCALAR_FLAG_UNIQUE_LOCK) > 0U)
+    {
+        (void)moal_free_lock(pmoal_handle, &pscalar->plock);
+    }
+}
+
+/**
+ *  @brief This function reads value from scalar
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return					Stored value
+ */
+static INLINE t_s32 util_scalar_read(t_void *pmoal_handle,
+                                     pmlan_scalar pscalar,
+                                     mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                     mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    t_s32 val;
+
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, pscalar->plock);
+    }
+    val = pscalar->value;
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, pscalar->plock);
+    }
+
+    return val;
+}
+
+/**
+ *  @brief This function writes value to scalar
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param val				Value to write
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return					N/A
+ */
+static INLINE t_void util_scalar_write(t_void *pmoal_handle,
+                                       pmlan_scalar pscalar,
+                                       t_s32 val,
+                                       mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                       mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, pscalar->plock);
+    }
+    pscalar->value = val;
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, pscalar->plock);
+    }
+}
+
+/**
+ *  @brief This function increments the value in scalar
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return					N/A
+ */
+static INLINE t_void util_scalar_increment(t_void *pmoal_handle,
+                                           pmlan_scalar pscalar,
+                                           mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                           mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, pscalar->plock);
+    }
+    pscalar->value++;
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, pscalar->plock);
+    }
+}
+
+/**
+ *  @brief This function decrements the value in scalar
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return					N/A
+ */
+static INLINE t_void util_scalar_decrement(t_void *pmoal_handle,
+                                           pmlan_scalar pscalar,
+                                           mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                           mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, pscalar->plock);
+    }
+    pscalar->value--;
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, pscalar->plock);
+    }
+}
+
+/**
+ *  @brief This function adds an offset to the value in scalar,
+ *         and returns the new value
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param offset			Offset value (can be negative)
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return					Value after offset
+ */
+static INLINE t_s32 util_scalar_offset(t_void *pmoal_handle,
+                                       pmlan_scalar pscalar,
+                                       t_s32 offset,
+                                       mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                       mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    t_s32 newval;
+
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, pscalar->plock);
+    }
+    newval = (pscalar->value += offset);
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, pscalar->plock);
+    }
+
+    return newval;
+}
+
+/**
+ *  @brief This function writes the value to the scalar
+ *         if existing value compared with other value is true.
+ *
+ *  @param pscalar			Pointer to scalar
+ *  @param condition		Condition to check
+ *  @param val_compare		Value to compare against current value
+ *  						((A X B), where B = val_compare)
+ *  @param val_to_set		Value to set if comparison is true
+ *  @param moal_spin_lock	A pointer to spin lock handler
+ *  @param moal_spin_unlock	A pointer to spin unlock handler
+ *
+ *  @return					Comparison result (MTRUE or MFALSE)
+ */
+static INLINE t_u8 util_scalar_conditional_write(t_void *pmoal_handle,
+                                                 pmlan_scalar pscalar,
+                                                 MLAN_SCALAR_CONDITIONAL condition,
+                                                 t_s32 val_compare,
+                                                 t_s32 val_to_set,
+                                                 mlan_status (*moal_spin_lock)(t_void *handle, t_void *plock),
+                                                 mlan_status (*moal_spin_unlock)(t_void *handle, t_void *plock))
+{
+    t_u8 update;
+    if (moal_spin_lock != MNULL)
+    {
+        (void)moal_spin_lock(pmoal_handle, pscalar->plock);
+    }
+
+    switch (condition)
+    {
+        case MLAN_SCALAR_COND_EQUAL:
+            update = (pscalar->value == val_compare);
+            break;
+        case MLAN_SCALAR_COND_NOT_EQUAL:
+            update = (pscalar->value != val_compare);
+            break;
+        case MLAN_SCALAR_COND_GREATER_THAN:
+            update = (pscalar->value > val_compare);
+            break;
+        case MLAN_SCALAR_COND_GREATER_OR_EQUAL:
+            update = (pscalar->value >= val_compare);
+            break;
+        case MLAN_SCALAR_COND_LESS_THAN:
+            update = (pscalar->value < val_compare);
+            break;
+        case MLAN_SCALAR_COND_LESS_OR_EQUAL:
+            update = (pscalar->value <= val_compare);
+            break;
+        default:
+            update = MFALSE;
+            break;
+    }
+    if (update != 0U)
+    {
+        pscalar->value = val_to_set;
+    }
+
+    if (moal_spin_unlock != MNULL)
+    {
+        (void)moal_spin_unlock(pmoal_handle, pscalar->plock);
+    }
+    return (update) ? MTRUE : MFALSE;
+}
+
+#endif /* !_MLAN_UTIL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_wmm.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_wmm.h
new file mode 100644
index 0000000000..4e2243e6cb
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/mlan_wmm.h
@@ -0,0 +1,269 @@
+/** @file mlan_wmm.h
+ *
+ *  @brief This file contains related macros, enum, and struct
+ *  of wmm functionalities
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/****************************************************
+Change log:
+    10/24/2008: initial version
+****************************************************/
+
+#ifndef _MLAN_WMM_H_
+#define _MLAN_WMM_H_
+
+/**
+ *  @brief This function gets the TID
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param ptr          A pointer to RA list table
+ *
+ *  @return 	    TID
+ */
+static INLINE int wlan_get_tid(pmlan_adapter pmadapter, raListTbl *ptr)
+{
+    pmlan_buffer mbuf;
+
+    ENTER();
+    mbuf = (pmlan_buffer)(void *)util_peek_list(pmadapter->pmoal_handle, &ptr->buf_head, MNULL, MNULL);
+    LEAVE();
+
+    return mbuf->priority;
+}
+
+/**
+ *  @brief This function gets the length of a list
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param head         A pointer to mlan_list_head
+ *
+ *  @return 	    Length of list
+ */
+static INLINE int wlan_wmm_list_len(pmlan_adapter pmadapter, pmlan_list_head head)
+{
+    pmlan_linked_list pos;
+    int count = 0;
+
+    ENTER();
+
+    pos = head->pnext;
+
+    while (pos != (pmlan_linked_list)(void *)head)
+    {
+        ++count;
+        pos = pos->pnext;
+    }
+
+    LEAVE();
+    return count;
+}
+
+/**
+ *  @brief This function requests a ralist lock
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *
+ *  @return             N/A
+ */
+static INLINE t_void wlan_request_ralist_lock(pmlan_private priv)
+{
+
+    ENTER();
+
+    OSA_MutexLock((osa_mutex_handle_t)priv->tx_ba_stream_tbl_lock, osaWaitForever_c);
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function releases a lock on ralist
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *
+ *  @return             N/A
+ */
+static INLINE t_void wlan_release_ralist_lock(pmlan_private priv)
+{
+
+    ENTER();
+
+    OSA_MutexUnlock((osa_mutex_handle_t)priv->tx_ba_stream_tbl_lock);
+
+
+    LEAVE();
+    return;
+}
+
+/** Add buffer to WMM Tx queue */
+void wlan_wmm_add_buf_txqueue(pmlan_adapter pmadapter, pmlan_buffer pmbuf);
+/** Add to RA list */
+void wlan_ralist_add(mlan_private *priv, t_u8 *ra);
+/** Update the RA list */
+int wlan_ralist_update(mlan_private *priv, t_u8 *old_ra, t_u8 *new_ra);
+/** WMM status change command handler */
+mlan_status wlan_cmd_wmm_status_change(pmlan_private priv);
+/** Check if WMM lists are empty */
+int wlan_wmm_lists_empty(pmlan_adapter pmadapter);
+/** Process WMM transmission */
+t_void wlan_wmm_process_tx(pmlan_adapter pmadapter);
+/** Test to see if the ralist ptr is valid */
+int wlan_is_ralist_valid(mlan_private *priv, raListTbl *ra_list, int tid);
+raListTbl *wlan_wmm_get_ralist_node(pmlan_private priv, t_u8 tid, t_u8 *ra_addr);
+t_u8 wlan_get_random_ba_threshold(pmlan_adapter pmadapter);
+
+/** Compute driver packet delay */
+t_u8 wlan_wmm_compute_driver_packet_delay(pmlan_private priv, const pmlan_buffer pmbuf);
+/** Initialize WMM */
+t_void wlan_wmm_init(pmlan_adapter pmadapter);
+/** Initialize WMM paramter */
+t_void wlan_init_wmm_param(pmlan_adapter pmadapter);
+/** Setup WMM queues */
+extern void wlan_wmm_setup_queues(pmlan_private priv);
+/* Setup default queues */
+void wlan_wmm_default_queue_priorities(pmlan_private priv);
+
+/** Process WMM association request */
+extern t_u32 wlan_wmm_process_association_req(pmlan_private priv,
+                                              t_u8 **ppAssocBuf,
+                                              IEEEtypes_WmmParameter_t *pWmmIE,
+                                              IEEEtypes_HTCap_t *pHTCap);
+
+/** setup wmm queue priorities */
+void wlan_wmm_setup_queue_priorities(pmlan_private priv, IEEEtypes_WmmParameter_t *wmm_ie);
+
+/** Downgrade WMM priority queue */
+void wlan_wmm_setup_ac_downgrade(pmlan_private priv);
+/** select WMM queue */
+t_u8 wlan_wmm_select_queue(mlan_private *pmpriv, t_u8 tid);
+t_void wlan_wmm_delete_peer_ralist(pmlan_private priv, t_u8 *mac);
+
+/** WMM TS_STATUS command handler */
+extern mlan_status wlan_cmd_wmm_ts_status(IN pmlan_private pmpriv, OUT HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+/** WMM ADDTS request command response handler */
+extern mlan_status wlan_ret_wmm_addts_req(IN pmlan_private pmpriv,
+                                          const IN HostCmd_DS_COMMAND *resp,
+                                          OUT mlan_ioctl_req *pioctl_buf);
+/** WMM DELTS request command response handler */
+extern mlan_status wlan_ret_wmm_delts_req(IN pmlan_private pmpriv,
+                                          const IN HostCmd_DS_COMMAND *resp,
+                                          OUT mlan_ioctl_req *pioctl_buf);
+/*
+ *  Functions used in the cmd handling routine
+ */
+/** WMM ADDTS request command handler */
+extern mlan_status wlan_cmd_wmm_addts_req(IN pmlan_private pmpriv, OUT HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+/** WMM QUEUE_STATS command handler */
+extern mlan_status wlan_cmd_wmm_queue_stats(IN pmlan_private pmpriv, OUT HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+/** WMM QUEUE_CONFIG command handler */
+extern mlan_status wlan_cmd_wmm_queue_config(IN pmlan_private pmpriv,
+                                             OUT HostCmd_DS_COMMAND *cmd,
+                                             IN t_void *pdata_buf);
+/** WMM get status command response handler */
+extern mlan_status wlan_ret_wmm_get_status(IN pmlan_private priv, IN t_u8 *ptlv, IN int resp_len);
+/** WMM TS_STATUS command response handler */
+extern mlan_status wlan_ret_wmm_ts_status(IN pmlan_private pmpriv,
+                                          IN HostCmd_DS_COMMAND *resp,
+                                          OUT mlan_ioctl_req *pioctl_buf);
+/** WMM QUEUE_CONFIG command response handler */
+extern mlan_status wlan_ret_wmm_queue_config(IN pmlan_private pmpriv,
+                                             const IN HostCmd_DS_COMMAND *resp,
+                                             OUT mlan_ioctl_req *pioctl_buf);
+/** WMM QUEUE_STATS command response handler */
+extern mlan_status wlan_ret_wmm_queue_stats(IN pmlan_private pmpriv,
+                                            const IN HostCmd_DS_COMMAND *resp,
+                                            OUT mlan_ioctl_req *pioctl_buf);
+/** WMM DELTS request command handler */
+extern mlan_status wlan_cmd_wmm_delts_req(IN pmlan_private pmpriv, OUT HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+
+
+t_void wlan_wmm_delete_peer_ralist(pmlan_private priv, t_u8 *mac);
+
+/* process wmm_param_config command */
+mlan_status wlan_cmd_wmm_param_config(pmlan_private pmpriv,
+                                      HostCmd_DS_COMMAND *cmd,
+                                      t_u8 cmd_action,
+                                      t_void *pdata_buf);
+
+/* process wmm_param_config command response */
+mlan_status wlan_ret_wmm_param_config(pmlan_private pmpriv, const HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf);
+
+#if CONFIG_WMM
+/* wmm enhance buffer pool */
+#define MAX_WMM_BUF_NUM 16
+#define WMM_DATA_LEN    1580
+#define OUTBUF_WMM_LEN  (sizeof(outbuf_t))
+
+typedef struct
+{
+    mlan_linked_list entry;
+    t_u8 intf_header[INTF_HEADER_LEN];
+    TxPD tx_pd;
+#if CONFIG_TX_RX_ZERO_COPY
+    t_u8 eth_header[ETH_HDR_LEN];
+#if CONFIG_AMSDU_IN_AMPDU
+    t_u8 llc_header[LLC_SNAP_LEN];
+#endif
+    /* Data payload pointer */
+    t_u8 *payload;
+    /* Packet buffer structure pointer */
+    void *buffer;
+#else
+    t_u8 data[WMM_DATA_LEN];
+#endif
+} outbuf_t;
+
+typedef struct
+{
+    mlan_linked_list entry;
+    t_u8 intf_header[INTF_HEADER_LEN];
+    TxPD tx_pd;
+    t_u8 data[1];
+} bypass_outbuf_t;
+
+/* transfer destination address to receive address */
+void wifi_wmm_da_to_ra(uint8_t *da, uint8_t *ra);
+
+/* wmm enhance get free buffer */
+uint8_t *wifi_wmm_get_outbuf_enh(
+    uint32_t *outbuf_len, mlan_wmm_ac_e queue, const uint8_t interface, uint8_t *ra, bool *is_tx_pause);
+
+/* wmm enhance enqueue tx buffer */
+int wlan_wmm_add_buf_txqueue_enh(const uint8_t interface, const uint8_t *buffer, const uint16_t len, uint8_t pkt_prio);
+
+/* wmm enhance buffer pool management */
+outbuf_t *wifi_wmm_buf_get(void);
+void wifi_wmm_buf_put(outbuf_t *buf);
+int wifi_wmm_buf_pool_init(uint8_t *pool);
+void wifi_wmm_buf_pool_deinit(void);
+
+/* wmm enhance ralist operation */
+void wlan_ralist_add_enh(mlan_private *priv, t_u8 *ra);
+int wlan_ralist_update_enh(mlan_private *priv, t_u8 *old_ra, t_u8 *new_ra);
+void wlan_ralist_pkts_free_enh(mlan_private *priv, raListTbl *ra_list, t_u8 ac);
+void wlan_ralist_del_enh(mlan_private *priv, t_u8 *ra);
+void wlan_ralist_del_all_enh(mlan_private *priv);
+void wlan_ralist_deinit_enh(mlan_private *priv);
+
+/* debug statistics */
+void wifi_wmm_drop_err_mem(const uint8_t interface);
+void wifi_wmm_drop_no_media(const uint8_t interface);
+void wifi_wmm_drop_retried_drop(const uint8_t interface);
+void wifi_wmm_drop_pause_drop(const uint8_t interface);
+void wifi_wmm_drop_pause_replaced(const uint8_t interface);
+
+int wifi_bypass_txq_init(void);
+void wifi_bypass_txq_deinit(void);
+void wlan_get_bypass_lock(uint8_t interface);
+void wlan_put_bypass_lock(uint8_t interface);
+void wlan_add_buf_bypass_txq(const uint8_t *buffer, const uint8_t interface);
+t_u8 wlan_bypass_txq_empty(uint8_t interface);
+void wlan_cleanup_bypass_txq(uint8_t interface);
+#endif
+
+#endif /* !_MLAN_WMM_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/type_decls.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/type_decls.h
new file mode 100644
index 0000000000..6ce6851947
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/incl/type_decls.h
@@ -0,0 +1,61 @@
+/** @file type_decls.h
+ *
+ *  @brief This file declares the generic data structures and APIs.
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    20/01/2022: initial version
+******************************************************/
+
+#ifndef _TYPE_DECL_H_
+#define _TYPE_DECL_H_
+
+
+/** Re-define generic data types for firmware downloader */
+/** Signed char (1-byte) */
+typedef char t_s8;
+/** Unsigned char (1-byte) */
+typedef unsigned char t_u8;
+/** Signed short (2-bytes) */
+typedef short t_s16;
+/** Unsigned short (2-bytes) */
+typedef unsigned short t_u16;
+/** Signed long (4-bytes) */
+typedef int t_s32;
+/** Unsigned long (4-bytes) */
+typedef unsigned int t_u32;
+/** Signed long long 8-bytes) */
+typedef long long t_s64;
+/** Unsigned long long 8-bytes) */
+typedef unsigned long long t_u64;
+/** Void pointer (4-bytes) */
+typedef void t_void;
+/** Size type */
+typedef t_u32 t_size;
+/** Boolean type */
+typedef t_u8 t_bool;
+
+#ifdef MLAN_64BIT
+/** Pointer type (64-bit) */
+typedef t_u64 t_ptr;
+/** Signed value (64-bit) */
+typedef t_s64 t_sval;
+#else
+/** Pointer type (32-bit) */
+typedef t_u32 t_ptr;
+/** Signed value (32-bit) */
+typedef t_s32 t_sval;
+#endif
+
+/** MLAN TRUE */
+#define MTRUE (1)
+/** MLAN FALSE */
+#define MFALSE (0)
+
+#endif /* !_TYPE_DECL_H_ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11ac.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11ac.c
new file mode 100644
index 0000000000..fb8517c78b
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11ac.c
@@ -0,0 +1,1196 @@
+/** @file mlan_11ac.c
+ *
+ *  @brief This file defines the private and adapter data
+ *  structures and declares global function prototypes used
+ *  in MLAN module.
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+/********************************************************
+   Local Variables
+********************************************************/
+
+/********************************************************
+   Global Variables
+********************************************************/
+
+/********************************************************
+   Local Functions
+********************************************************/
+#if CONFIG_11AC
+/**
+ *  @brief determine the center frquency center index for bandwidth
+ *         of 80 MHz and 160 MHz
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param band         band
+ *  @param pri_chan     primary channel
+ *  @param chan_bw      channel bandwidth
+ *
+ *  @return             channel center frequency center, if found; O, otherwise
+ */
+
+t_u8 wlan_get_center_freq_idx(IN mlan_private *pmpriv, IN t_u8 band, IN t_u32 pri_chan, IN t_u8 chan_bw)
+{
+    t_u8 center_freq_idx = 0;
+
+    if ((band & BAND_AAC) != 0U)
+    {
+        switch (pri_chan)
+        {
+            case 36:
+            case 40:
+            case 44:
+            case 48:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 42;
+                }
+                break;
+            case 52:
+            case 56:
+            case 60:
+            case 64:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 58;
+                }
+                else if (chan_bw == (t_u8)CHANNEL_BW_160MHZ)
+                {
+                    center_freq_idx = 50;
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+                break;
+            case 100:
+            case 104:
+            case 108:
+            case 112:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 106;
+                }
+                break;
+            case 116:
+            case 120:
+            case 124:
+            case 128:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 122;
+                }
+                else if (chan_bw == (t_u8)CHANNEL_BW_160MHZ)
+                {
+                    center_freq_idx = 114;
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+                break;
+            case 132:
+            case 136:
+            case 140:
+            case 144:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 138;
+                }
+                break;
+            case 149:
+            case 153:
+            case 157:
+            case 161:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 155;
+                }
+                break;
+            case 165:
+            case 169:
+            case 173:
+            case 177:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 171;
+                }
+                break;
+            case 184:
+            case 188:
+            case 192:
+            case 196:
+                if (chan_bw == (t_u8)CHANNEL_BW_80MHZ)
+                {
+                    center_freq_idx = 190;
+                }
+                break;
+            default: /* error. go to the default */
+                center_freq_idx = 42;
+                break;
+        }
+    }
+    return center_freq_idx;
+}
+#endif
+
+/**
+ *  @brief This function gets the bitmap of nss which supports VHT mcs
+ *
+ *  @param mcs_map_set  VHT mcs map
+ *
+ *  @return             The bitmap of supported nss
+ */
+static t_u8 wlan_get_nss_vht_mcs(t_u16 mcs_map_set)
+{
+    t_u8 nss, nss_map = 0;
+    for (nss = 1; nss <= 8U; nss++)
+    {
+        if (GET_VHTNSSMCS(mcs_map_set, nss) != NO_NSS_SUPPORT)
+        {
+            nss_map |= 1U << (nss - 1U);
+        }
+    }
+    PRINTM(MCMND, "Supported nss bit map:0x%02x\n", nss_map);
+    return nss_map;
+}
+
+/**
+ *  @brief This function gets the number of nss which supports VHT mcs
+ *
+ *  @param mcs_map_set  VHT mcs map
+ *
+ *  @return             Number of supported nss
+ */
+static t_u8 wlan_get_nss_num_vht_mcs(t_u16 mcs_map_set)
+{
+    t_u8 nss, nss_num = 0;
+    for (nss = 1; nss <= 8U; nss++)
+    {
+        if (GET_VHTNSSMCS(mcs_map_set, nss) != NO_NSS_SUPPORT)
+        {
+            nss_num++;
+        }
+    }
+    PRINTM(MCMND, "Supported nss:%d\n", nss_num);
+    return nss_num;
+}
+
+/**
+ *  @brief This function fills the cap info
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param pht_cap      A pointer to MrvlIETypes_HTCap_t structure
+ *  @param bands        Band configuration
+ *
+ *  @return             N/A
+ */
+static void wlan_fill_cap_info(mlan_private *priv, VHT_capa_t *vht_cap, t_u16 bands)
+{
+    mlan_adapter *pmadapter = priv->adapter;
+    t_u32 usr_dot_11ac_dev_cap;
+
+    ENTER();
+
+#if CONFIG_5GHz_SUPPORT
+    if ((bands & BAND_A) != 0U)
+    {
+        usr_dot_11ac_dev_cap = pmadapter->usr_dot_11ac_dev_cap_a;
+    }
+    else
+#endif
+    {
+        usr_dot_11ac_dev_cap = pmadapter->usr_dot_11ac_dev_cap_bg;
+    }
+
+    vht_cap->vht_cap_info = usr_dot_11ac_dev_cap;
+#ifdef RW610
+    if (GET_VHTCAP_MAXMPDULEN(vht_cap->vht_cap_info) != 0U)
+        RESET_11ACMAXMPDULEN(vht_cap->vht_cap_info);
+#endif
+
+    LEAVE();
+}
+
+#if CONFIG_11AC
+/**
+ *  @brief Set/get 11ac configuration
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return     MLAN_STATUS_PENDING --success, otherwise fail
+ */
+
+mlan_status wlan_11ac_ioctl_vhtcfg(IN mlan_private *pmpriv, IN t_u8 action, IN mlan_ds_11ac_vht_cfg *vht_cfg)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u16 cmd_action        = 0;
+    t_u32 usr_vht_cap_info  = 0;
+    t_u32 cfg_value         = 0;
+    t_u32 hw_value          = 0;
+    t_u8 nss                = 0;
+    t_u16 no_nss_support    = NO_NSS_SUPPORT;
+
+    ENTER();
+
+#define VHT_CAP_INFO_BIT_FIELDS                                                                                \
+    (MBIT(4) | MBIT(5) | MBIT(6) | MBIT(7) | MBIT(11) | MBIT(12) | MBIT(19) | MBIT(20) | MBIT(21) | MBIT(22) | \
+     MBIT(28) | MBIT(29))
+
+    if (action == (t_u8)MLAN_ACT_SET)
+    {
+        /** SET operation */
+        /** validate the user input and correct it if necessary */
+        if (pmpriv->bss_role == MLAN_BSS_ROLE_STA)
+        {
+            if (vht_cfg->txrx == 3U)
+            {
+                PRINTM(MERROR, "Configuration of VHT capabilities for TX/RX 3 is not supported in STA mode!\n");
+                return MLAN_STATUS_FAILURE;
+            }
+        }
+        if (pmpriv->bss_role == MLAN_BSS_ROLE_UAP)
+        {
+            if (vht_cfg->txrx != 3U)
+            {
+                PRINTM(MERROR, "Configuration of VHT capabilities for TX/RX %d is not supported in UAP mode!\n",
+                       vht_cfg->txrx);
+
+                return MLAN_STATUS_FAILURE;
+            }
+        }
+        /** set bit fileds */
+        usr_vht_cap_info = VHT_CAP_INFO_BIT_FIELDS & vht_cfg->vht_cap_info & pmadapter->hw_dot_11ac_dev_cap;
+        /** set MAX MPDU LEN field (bit 0 - bit 1) */
+        cfg_value = GET_VHTCAP_MAXMPDULEN(vht_cfg->vht_cap_info);
+        hw_value  = GET_VHTCAP_MAXMPDULEN(pmadapter->hw_dot_11ac_dev_cap);
+        SET_VHTCAP_MAXMPDULEN(usr_vht_cap_info, MIN(cfg_value, hw_value));
+        /** set CHAN Width Set field (bit 2 - bit 3) */
+        cfg_value = GET_VHTCAP_CHWDSET(vht_cfg->vht_cap_info);
+        hw_value  = GET_VHTCAP_CHWDSET(pmadapter->hw_dot_11ac_dev_cap);
+        SET_VHTCAP_CHWDSET(usr_vht_cap_info, MIN(cfg_value, hw_value));
+        /** set Rx STBC field (bit 8 - bit 10) */
+        cfg_value = GET_VHTCAP_RXSTBC(vht_cfg->vht_cap_info);
+        hw_value  = GET_VHTCAP_RXSTBC(pmadapter->hw_dot_11ac_dev_cap);
+        SET_VHTCAP_RXSTBC(usr_vht_cap_info, MIN(cfg_value, hw_value));
+        /** set Steering Number of BFer Ant (bit 13 - bit 15) */
+        cfg_value = GET_VHTCAP_SNBFERANT(vht_cfg->vht_cap_info);
+        hw_value  = GET_VHTCAP_SNBFERANT(pmadapter->hw_dot_11ac_dev_cap);
+        SET_VHTCAP_SNBFERANT(usr_vht_cap_info, MIN(cfg_value, hw_value));
+        /** set Number of Sounding Dimension (bit 16 - bit 18) */
+        cfg_value = GET_VHTCAP_NUMSNDDM(vht_cfg->vht_cap_info);
+        hw_value  = GET_VHTCAP_NUMSNDDM(pmadapter->hw_dot_11ac_dev_cap);
+        SET_VHTCAP_NUMSNDDM(usr_vht_cap_info, MIN(cfg_value, hw_value));
+        /** set Number of Max AMPDU Length Exponent (bit 23 - bit 25) */
+        cfg_value = GET_VHTCAP_MAXAMPDULENEXP(vht_cfg->vht_cap_info);
+        hw_value  = GET_VHTCAP_MAXAMPDULENEXP(pmadapter->hw_dot_11ac_dev_cap);
+        SET_VHTCAP_MAXAMPDULENEXP(usr_vht_cap_info, MIN(cfg_value, hw_value));
+        /** set VHT Link Adaptation Capable (bit 26 - bit 27) */
+        cfg_value = GET_VHTCAP_LINKADPCAP(vht_cfg->vht_cap_info);
+        hw_value  = GET_VHTCAP_LINKADPCAP(pmadapter->hw_dot_11ac_dev_cap);
+        SET_VHTCAP_LINKADPCAP(usr_vht_cap_info, MIN(cfg_value, hw_value));
+        /** update the user setting if it is beyond the hw capabiliteis */
+        vht_cfg->vht_cap_info = usr_vht_cap_info;
+        PRINTM(MINFO, "Set: vht cap info  0x%x\n", usr_vht_cap_info);
+
+        /** update the RX MCS map */
+        if ((vht_cfg->txrx & MLAN_RADIO_RX) != 0U)
+        {
+            /* use the previous user value */
+            if (vht_cfg->vht_rx_mcs == 0xffffffffU)
+            {
+                vht_cfg->vht_rx_mcs = GET_VHTMCS(pmadapter->usr_dot_11ac_mcs_support);
+            }
+            for (nss = 1; nss <= 8U; nss++)
+            {
+                cfg_value = GET_VHTNSSMCS(vht_cfg->vht_rx_mcs, nss);
+                hw_value  = GET_DEVNSSRXMCS(pmadapter->hw_dot_11ac_mcs_support, nss);
+                if ((hw_value == NO_NSS_SUPPORT) || (cfg_value == NO_NSS_SUPPORT))
+                {
+                    SET_VHTNSSMCS(vht_cfg->vht_rx_mcs, nss, no_nss_support);
+                }
+                else
+                {
+                    SET_VHTNSSMCS(vht_cfg->vht_rx_mcs, nss, MIN(cfg_value, hw_value));
+                }
+            }
+            PRINTM(MINFO, "Set: vht rx mcs set 0x%08x\n", vht_cfg->vht_rx_mcs);
+            /* use the previous user value */
+            if (vht_cfg->vht_tx_mcs == 0xffffffffU)
+            {
+                vht_cfg->vht_tx_mcs = GET_VHTMCS(pmadapter->usr_dot_11ac_mcs_support >> 16);
+            }
+            for (nss = 1; nss <= 8U; nss++)
+            {
+                cfg_value = GET_VHTNSSMCS(vht_cfg->vht_tx_mcs, nss);
+                hw_value  = GET_DEVNSSTXMCS(pmadapter->hw_dot_11ac_mcs_support, nss);
+                if ((hw_value == NO_NSS_SUPPORT) || (cfg_value == NO_NSS_SUPPORT))
+                {
+                    SET_VHTNSSMCS(vht_cfg->vht_tx_mcs, nss, no_nss_support);
+                }
+                else
+                {
+                    SET_VHTNSSMCS(vht_cfg->vht_tx_mcs, nss, MIN(cfg_value, hw_value));
+                }
+            }
+
+            PRINTM(MINFO, "Set: vht tx mcs set 0x%08x\n", vht_cfg->vht_tx_mcs);
+            if (!vht_cfg->skip_usr_11ac_mcs_cfg)
+            {
+                RESET_DEVRXMCSMAP(pmadapter->usr_dot_11ac_mcs_support);
+                pmadapter->usr_dot_11ac_mcs_support |= GET_VHTMCS(vht_cfg->vht_rx_mcs);
+                RESET_DEVTXMCSMAP(pmadapter->usr_dot_11ac_mcs_support);
+                pmadapter->usr_dot_11ac_mcs_support |= (GET_VHTMCS(vht_cfg->vht_tx_mcs) << 16);
+                PRINTM(MINFO, "Set: vht mcs set 0x%08x\n", pmadapter->usr_dot_11ac_mcs_support);
+            }
+            else
+            {
+                PRINTM(MINFO, "Skipped user 11ac mcs configuration\n");
+                vht_cfg->skip_usr_11ac_mcs_cfg = MFALSE;
+            }
+        }
+    }
+
+    if (pmpriv->bss_role == MLAN_BSS_ROLE_STA)
+    {
+        if ((vht_cfg->txrx & MLAN_RADIO_RX) != 0U)
+        {
+            /* maximum VHT configuration used in association */
+
+            if (action == (t_u8)MLAN_ACT_SET)
+            {
+                if (vht_cfg->band == BAND_SELECT_BG)
+                {
+                    pmadapter->usr_dot_11ac_dev_cap_bg = usr_vht_cap_info;
+                }
+#if CONFIG_5GHz_SUPPORT
+                else if (vht_cfg->band == BAND_SELECT_A)
+                {
+                    pmadapter->usr_dot_11ac_dev_cap_a = usr_vht_cap_info;
+                }
+#endif
+                else
+                {
+                    pmadapter->usr_dot_11ac_dev_cap_bg = usr_vht_cap_info;
+#if CONFIG_5GHz_SUPPORT
+                    pmadapter->usr_dot_11ac_dev_cap_a = usr_vht_cap_info;
+#endif
+                }
+                pmadapter->usr_dot_11ac_bw = (t_u8)vht_cfg->bwcfg;
+            }
+            else
+            {
+                /** GET operation */
+                if (vht_cfg->band == BAND_SELECT_BG)
+                {
+                    vht_cfg->vht_cap_info = pmadapter->usr_dot_11ac_dev_cap_bg;
+                    PRINTM(MINFO, "Get: vht cap info for 2.4GHz 0x%x\n", pmadapter->usr_dot_11ac_dev_cap_bg);
+                }
+#if CONFIG_5GHz_SUPPORT
+                else if (vht_cfg->band == BAND_SELECT_A)
+                {
+                    vht_cfg->vht_cap_info = pmadapter->usr_dot_11ac_dev_cap_a;
+                    PRINTM(MINFO, "Get: vht cap info for 5GHz 0x%x\n", pmadapter->usr_dot_11ac_dev_cap_a);
+                }
+#endif
+                else
+                {
+                    PRINTM(MINFO, "Get: invalid band selection for vht cap info\n");
+                    ret = MLAN_STATUS_FAILURE;
+                }
+                vht_cfg->bwcfg      = pmadapter->usr_dot_11ac_bw;
+                vht_cfg->vht_rx_mcs = GET_DEVRXMCSMAP(pmadapter->usr_dot_11ac_mcs_support);
+                vht_cfg->vht_tx_mcs = GET_DEVTXMCSMAP(pmadapter->usr_dot_11ac_mcs_support);
+                vht_cfg->vht_rx_max_rate =
+                    wlan_convert_mcsmap_to_maxrate(pmpriv, (t_u8)vht_cfg->band, (t_u16)vht_cfg->vht_rx_mcs);
+                vht_cfg->vht_tx_max_rate =
+                    wlan_convert_mcsmap_to_maxrate(pmpriv, (t_u8)vht_cfg->band, (t_u16)vht_cfg->vht_tx_mcs);
+            }
+            LEAVE();
+            return ret;
+        }
+    }
+
+    if (action == (t_u8)MLAN_ACT_SET)
+    {
+        cmd_action = HostCmd_ACT_GEN_SET;
+    }
+    else
+    {
+        cmd_action = HostCmd_ACT_GEN_GET;
+    }
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_11AC_CFG, cmd_action, 0, NULL, (t_void *)vht_cfg);
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    LEAVE();
+    return ret;
+}
+#endif
+
+#if 0
+/**
+ *  @brief Get/Set Operating Mode Notification cfg
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return     MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_11ac_ioctl_opermodecfg(
+    IN pmlan_adapter    pmadapter,
+    IN pmlan_ioctl_req  pioctl_req)
+{
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    t_u8 hw_bw_160or8080 = 0;
+    t_u8 hw_rx_nss = 0;
+
+    ENTER();
+
+    cfg = (mlan_ds_11ac_cfg *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_GET) {
+        cfg->param.opermode_cfg.bw = pmpriv->usr_dot_11ac_opermode_bw;
+        cfg->param.opermode_cfg.nss = pmpriv->usr_dot_11ac_opermode_nss;
+    } else if (pioctl_req->action == MLAN_ACT_SET) {
+        hw_bw_160or8080 = GET_VHTCAP_CHWDSET(pmadapter->hw_dot_11ac_dev_cap);
+        hw_rx_nss = wlan_get_nss_num_vht_mcs(GET_DEVRXMCSMAP(pmadapter->hw_dot_11ac_mcs_support));
+        if ((((cfg->param.opermode_cfg.bw - 1) > BW_80MHZ) && !hw_bw_160or8080) ||
+            (cfg->param.opermode_cfg.nss > hw_rx_nss)) {
+            PRINTM(MERROR, "bw or nss NOT supported. HW support bw_160or8080=%d rx_nss=%d.\n",
+                hw_bw_160or8080, hw_rx_nss);
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        pmpriv->usr_dot_11ac_opermode_bw = cfg->param.opermode_cfg.bw;
+        pmpriv->usr_dot_11ac_opermode_nss = cfg->param.opermode_cfg.nss;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Get supported MCS set
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return     MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_11ac_ioctl_supported_mcs_set(
+    IN pmlan_adapter    pmadapter,
+    IN pmlan_ioctl_req  pioctl_req)
+{
+    /*mlan_ds_11ac_cfg *cfg= MNULL;*/
+    /*int rx_mcs_supp;*/
+    /*t_u8 mcs_set[NUM_MCS_SUPP];*/
+
+    ENTER();
+#if 0
+    if (pioctl_req->action == MLAN_ACT_SET) {
+        PRINTM(MERROR, "Set operation is not supported\n");
+        pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    rx_mcs_supp = GET_11ACRXMCSSUPP(pmadapter->usr_dot_11ac_mcs_support);
+    /* Set MCS */
+    (void)__memset(pmadapter, (t_u8 *) mcs_set, 0xff, rx_mcs_supp);
+    /* Clear all the other values */
+    (void)__memset(pmadapter, (t_u8 *) &mcs_set[rx_mcs_supp], 0,
+                 NUM_MCS_FIELD - rx_mcs_supp);
+    /* Set MCS32 with 40MHz support */
+    if (ISSUPP_CHANWIDTH80(pmadapter->usr_dot_11ac_dev_cap_bg)
+#if CONFIG_5GHz_SUPPORT
+        || ISSUPP_CHANWIDTH80(pmadapter->usr_dot_11ac_dev_cap_a)
+#endif
+        )
+        SETHT_MCS32(mcs_set);
+
+    cfg = (mlan_ds_11ac_cfg *)pioctl_req->pbuf;
+    (void)__memcpy(pmadapter, cfg->param.supported_mcs_set, mcs_set, NUM_MCS_SUPP);
+
+#endif
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/********************************************************
+			Global Functions
+********************************************************/
+
+/**
+ *  @brief This function prints the 802.11ac device capability
+ *
+ *  @param pmadapter     A pointer to mlan_adapter structure
+ *  @param cap           Capability value
+ *
+ *  @return        N/A
+ */
+void wlan_show_dot11acdevcap(pmlan_adapter pmadapter, t_u32 cap)
+{
+    ENTER();
+
+    switch (GET_VHTCAP_MAXMPDULEN(cap)) {
+        case 0x0:
+            PRINTM(MINFO, "GET_HW_SPEC: Maximum MSDU length = 3895 octets\n");
+            break;
+        case 0x1:
+            PRINTM(MINFO, "GET_HW_SPEC: Maximum MSDU length = 7991 octets\n");
+            break;
+        case 0x2:
+            PRINTM(MINFO, "GET_HW_SPEC: Maximum MSDU length = 11454 octets\n");
+            break;
+        default:
+            PRINTM(MINFO, "Unsupport value\n");
+            break;
+    }
+
+    PRINTM(MINFO, "GET_HW_SPEC: HTC-VHT %s\n",
+           (ISSUPP_11ACVHTHTCVHT(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: VHT TXOP PS %s\n",
+           (ISSUPP_11ACVHTTXOPPS(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: MU RX beamformee %s\n",
+           (ISSUPP_11ACMURXBEAMFORMEE(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: MU TX beamformee %s\n",
+           (ISSUPP_11ACMUTXBEAMFORMEE(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: SU RX Beamformee %s\n",
+           (ISSUPP_11ACSUBEAMFORMEE(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: SU TX Beamformer %s\n",
+           (ISSUPP_11ACSUBEAMFORMER(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Rx STBC %s\n",
+           (ISSUPP_11ACRXSTBC(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Tx STBC %s\n",
+           (ISSUPP_11ACTXSTBC(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Short GI %s for 160MHz BW\n",
+           (ISSUPP_11ACSGI160(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Short GI %s for 80MHz BW\n",
+           (ISSUPP_11ACSGI80(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: LDPC coding %s\n",
+           (ISSUPP_11ACLDPC(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Channel BW 20/40/80/160/80+80 MHz %s\n",
+           (ISSUPP_11ACBW8080(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Channel BW 20/40/80/160 MHz %s\n",
+           (ISSUPP_11ACBW160(cap) ? "supported" : "not supported"));
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function prints the 802.11ac device MCS
+ *
+ *  @param pmadapter A pointer to mlan_adapter structure
+ *  @param support   Support value
+ *
+ *  @return        N/A
+ */
+void wlan_show_dot11acmcssupport(pmlan_adapter pmadapter, t_u32 support)
+{
+    ENTER();
+
+    PRINTM(MINFO, "GET_HW_SPEC: MCSs for %2dx%2d MIMO\n", GET_DEVRXMCSMAP(support),
+                        GET_DEVTXMCSMAP(support));
+
+    LEAVE();
+    return;
+}
+
+#endif
+
+/**
+ *  @brief This function converts the 2-bit MCS map to the highest long GI
+ *  VHT PPDU data rate
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param bands        Supported bands
+ *  @param mcs_map      2-bit MCS map
+ *
+ *  @return             the max data rate for long GI
+ */
+t_u16 wlan_convert_mcsmap_to_maxrate(mlan_private *priv, t_u8 bands, t_u16 mcs_map)
+{
+    mlan_adapter *pmadapter = priv->adapter;
+    t_u8 i;
+    t_u8 nss;
+    t_u8 max_mcs;
+    t_u16 max_rate         = 0;
+    t_u32 usr_vht_cap_info = 0;
+    t_u32 usr_dot_11n_dev_cap;
+
+    /* tables of the MCS map to the highest data rate (in Mbps)
+     * supported for long GI */
+    t_u16 max_rate_lgi_20MHZ[8][3] = {
+        {0x41, 0x4E, 0x0},     /* NSS = 1 */
+        {0x82, 0x9C, 0x0},     /* NSS = 2 */
+        {0xC3, 0xEA, 0x104},   /* NSS = 3 */
+        {0x104, 0x138, 0x0},   /* NSS = 4 */
+        {0x145, 0x186, 0x0},   /* NSS = 5 */
+        {0x186, 0x1D4, 0x208}, /* NSS = 6 */
+        {0x1C7, 0x222, 0x0},   /* NSS = 7 */
+        {0x208, 0x270, 0x0}    /* NSS = 8 */
+    };
+
+    t_u16 max_rate_lgi_40MHZ[8][3] = {
+        {0x87, 0xA2, 0xB4},    /* NSS = 1 */
+        {0x10E, 0x144, 0x168}, /* NSS = 2 */
+        {0x195, 0x1E6, 0x21C}, /* NSS = 3 */
+        {0x21C, 0x288, 0x2D0}, /* NSS = 4 */
+        {0x2A3, 0x32A, 0x384}, /* NSS = 5 */
+        {0x32A, 0x3CC, 0x438}, /* NSS = 6 */
+        {0x3B1, 0x46E, 0x4EC}, /* NSS = 7 */
+        {0x438, 0x510, 0x5A0}  /* NSS = 8 */
+    };
+
+    t_u16 max_rate_lgi_80MHZ[8][3] = {
+        {0x124, 0x15F, 0x186}, /* NSS = 1 */
+        {0x249, 0x2BE, 0x30C}, /* NSS = 2 */
+        {0x36D, 0x41D, 0x492}, /* NSS = 3 */
+        {0x492, 0x57C, 0x618}, /* NSS = 4 */
+        {0x5B6, 0x6DB, 0x79E}, /* NSS = 5 */
+        {0x6DB, 0x83A, 0x0},   /* NSS = 6 */
+        {0x7FF, 0x999, 0xAAA}, /* NSS = 7 */
+        {0x924, 0xAF8, 0xC30}  /* NSS = 8 */
+    };
+    t_u16 max_rate_lgi_160MHZ[8][3] = {
+        {0x249, 0x2BE, 0x30C},   /* NSS = 1 */
+        {0x492, 0x57C, 0x618},   /* NSS = 2 */
+        {0x6DB, 0x83A, 0x0},     /* NSS = 3 */
+        {0x924, 0xAF8, 0xC30},   /* NSS = 4 */
+        {0xB6D, 0xDB6, 0xF3C},   /* NSS = 5 */
+        {0xDB6, 0x1074, 0x1248}, /* NSS = 6 */
+        {0xFFF, 0x1332, 0x1554}, /* NSS = 7 */
+        {0x1248, 0x15F0, 0x1860} /* NSS = 8 */
+    };
+
+#if CONFIG_5GHz_SUPPORT
+    if ((bands & BAND_AAC) != 0U)
+    {
+        usr_vht_cap_info    = pmadapter->usr_dot_11ac_dev_cap_a;
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_a;
+    }
+    else
+    {
+#endif
+        usr_vht_cap_info    = pmadapter->usr_dot_11ac_dev_cap_bg;
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_bg;
+#if CONFIG_5GHz_SUPPORT
+    }
+#endif
+
+    /* find the max NSS supported */
+    nss = 0;
+    for (i = 0; i < 8U; i++)
+    {
+        max_mcs = (t_u8)((mcs_map >> (2U * i)) & 0x3U);
+        if (max_mcs < 3U)
+        {
+            nss = i;
+        }
+    }
+
+    max_mcs = (t_u8)((mcs_map >> (2U * nss)) & 0x3U);
+    /* if max_mcs is 3, nss must be 0 (SS = 1). Thus, max mcs is MCS 9*/
+    if (max_mcs >= 3U)
+    {
+        max_mcs = (t_u8)2U;
+    }
+
+    if (GET_VHTCAP_CHWDSET(usr_vht_cap_info) != 0U)
+    {
+        /* support 160 MHz */
+        max_rate = max_rate_lgi_160MHZ[nss][max_mcs];
+        if (max_mcs >= 1U && max_rate == 0U)
+        {
+            /* MCS9 is not supported in NSS6 */
+            max_rate = max_rate_lgi_160MHZ[nss][max_mcs - 1U];
+        }
+    }
+    else
+    {
+        if (pmadapter->usr_dot_11ac_bw == BW_FOLLOW_VHTCAP)
+        {
+            max_rate = max_rate_lgi_80MHZ[nss][max_mcs];
+            if (max_mcs >= 1U && max_rate == 0U)
+            {
+                /* MCS9 is not supported in NSS3 */
+                max_rate = max_rate_lgi_80MHZ[nss][max_mcs - 1U];
+            }
+        }
+        else
+        {
+            if (ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap) != 0U)
+            {
+                max_rate = max_rate_lgi_40MHZ[nss][max_mcs];
+            }
+            else
+            {
+                max_rate = max_rate_lgi_20MHZ[nss][max_mcs];
+                /* MCS9 is not supported in NSS1/2/4/5/7/8 */
+                if (max_mcs >= 1U && max_rate == 0U)
+                {
+                    max_rate = max_rate_lgi_20MHZ[nss][max_mcs - 1U];
+                }
+            }
+        }
+    }
+    PRINTM(MCMND, "max_rate=%dM\n", max_rate);
+    return max_rate;
+}
+
+/**
+ *  @brief This function fills the VHT cap tlv out put format is LE, not CPU
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param pvht_cap      A pointer to MrvlIETypes_HTCap_t structure
+ *  @param bands        Band configuration
+ *  @param flag         TREU--pvht_cap has the setting for resp
+ *                      MFALSE -- pvht_cap is clean
+ *  @return             N/A
+ */
+void wlan_fill_vht_cap_tlv(mlan_private *priv, MrvlIETypes_VHTCap_t *pvht_cap, t_u16 bands, t_u8 flag)
+{
+    mlan_adapter *pmadapter = priv->adapter;
+    t_u16 mcs_map_user      = 0;
+    t_u16 mcs_map_resp      = 0;
+    t_u32 mcs_map_result    = 0U;
+    t_u16 mcs_user          = 0;
+    t_u16 mcs_resp          = 0;
+    t_u16 nss;
+    t_u16 no_nss_support = NO_NSS_SUPPORT;
+
+    ENTER();
+
+    /* Fill VHT cap info */
+    wlan_fill_cap_info(priv, &pvht_cap->vht_cap, bands);
+    pvht_cap->vht_cap.vht_cap_info = wlan_cpu_to_le32(pvht_cap->vht_cap.vht_cap_info);
+
+    /* Fill VHT MCS Set */
+    /* rx MCS Set, find the minimum of the user rx mcs and ap rx mcs*/
+    mcs_map_resp = mcs_map_user = (t_u16)GET_DEVRXMCSMAP(pmadapter->usr_dot_11ac_mcs_support);
+    if (flag != 0U)
+    {
+        mcs_map_resp = wlan_le16_to_cpu(pvht_cap->vht_cap.mcs_sets.rx_mcs_map);
+    }
+    mcs_map_result = 0U;
+    for (nss = 1; nss <= 8U; nss++)
+    {
+        mcs_user = GET_VHTNSSMCS(mcs_map_user, nss);
+        mcs_resp = GET_VHTNSSMCS(mcs_map_resp, nss);
+        if ((mcs_user == NO_NSS_SUPPORT) || (mcs_resp == NO_NSS_SUPPORT))
+        {
+            SET_VHTNSSMCS(mcs_map_result, nss, no_nss_support);
+        }
+        else
+        {
+            SET_VHTNSSMCS(mcs_map_result, nss, MIN(mcs_user, mcs_resp));
+        }
+    }
+    /* rx MCS map */
+    pvht_cap->vht_cap.mcs_sets.rx_mcs_map = wlan_cpu_to_le16(mcs_map_result);
+
+    /* rx highest rate */
+    pvht_cap->vht_cap.mcs_sets.rx_max_rate = wlan_convert_mcsmap_to_maxrate(priv, (t_u8)bands, (t_u16)mcs_map_result);
+    pvht_cap->vht_cap.mcs_sets.rx_max_rate = wlan_cpu_to_le16(pvht_cap->vht_cap.mcs_sets.rx_max_rate);
+
+    /* tx MCS Set find the minimum of the user tx mcs and ap tx mcs */
+    mcs_map_resp = mcs_map_user = (t_u16)GET_DEVTXMCSMAP(pmadapter->usr_dot_11ac_mcs_support);
+    if (flag != 0U)
+    {
+        mcs_map_resp = wlan_le16_to_cpu(pvht_cap->vht_cap.mcs_sets.tx_mcs_map);
+    }
+    mcs_map_result = 0U;
+    for (nss = 1; nss <= 8U; nss++)
+    {
+        mcs_user = GET_VHTNSSMCS(mcs_map_user, nss);
+        mcs_resp = GET_VHTNSSMCS(mcs_map_resp, nss);
+        if ((mcs_user == NO_NSS_SUPPORT) || (mcs_resp == NO_NSS_SUPPORT))
+        {
+            SET_VHTNSSMCS(mcs_map_result, nss, no_nss_support);
+        }
+        else
+        {
+            SET_VHTNSSMCS(mcs_map_result, nss, MIN(mcs_user, mcs_resp));
+        }
+    }
+
+    /* tx MCS map */
+    pvht_cap->vht_cap.mcs_sets.tx_mcs_map = wlan_cpu_to_le16(mcs_map_result);
+    /* tx highest rate */
+    pvht_cap->vht_cap.mcs_sets.tx_max_rate = wlan_convert_mcsmap_to_maxrate(priv, (t_u8)bands, (t_u16)mcs_map_result);
+    pvht_cap->vht_cap.mcs_sets.tx_max_rate = wlan_cpu_to_le16(pvht_cap->vht_cap.mcs_sets.tx_max_rate);
+
+    LEAVE();
+    return;
+}
+
+#if 0
+/**
+ *  @brief This function fills the VHT cap tlv out put format is CPU
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param pvht_cap      A pointer to MrvlIETypes_HTCap_t structure
+ *  @param bands        Band configuration
+ *
+ *  @return             N/A
+ */
+void wlan_fill_vht_cap_ie(mlan_private *priv,
+        IEEEtypes_VHTCap_t *pvht_cap, t_u16 bands)
+{
+    ENTER();
+
+    pvht_cap->ieee_hdr.element_id = VHT_CAPABILITY;
+    pvht_cap->ieee_hdr.len = sizeof(VHT_capa_t);
+
+    /* Fill VHT cap info */
+    wlan_fill_cap_info(priv, &pvht_cap->vht_cap, bands);
+
+    /* rx MCS map */
+    pvht_cap->vht_cap.mcs_sets.rx_mcs_map =
+        GET_DEVRXMCSMAP(priv->usr_dot_11ac_mcs_support);
+
+    /* rx highest rate */
+    pvht_cap->vht_cap.mcs_sets.rx_max_rate =
+        wlan_convert_mcsmap_to_maxrate(priv, bands, pvht_cap->vht_cap.mcs_sets.rx_mcs_map);
+
+    /* tx MCS map */
+    pvht_cap->vht_cap.mcs_sets.tx_mcs_map = GET_DEVTXMCSMAP(priv->usr_dot_11ac_mcs_support);
+    /* tx highest rate */
+    pvht_cap->vht_cap.mcs_sets.tx_max_rate =
+        wlan_convert_mcsmap_to_maxrate(priv, bands,pvht_cap->vht_cap.mcs_sets.tx_mcs_map);
+
+    LEAVE();
+    return;
+}
+
+#endif
+
+/**
+ *  @brief This function append the 802_11AC tlv
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc    A pointer to BSSDescriptor_t structure
+ *  @param ppbuffer     A Pointer to command buffer pointer
+ *
+ *  @return bytes added to the buffer
+ */
+int wlan_cmd_append_11ac_tlv(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc, t_u8 **ppbuffer)
+{
+    pmlan_adapter pmadapter = pmpriv->adapter;
+    MrvlIETypes_VHTCap_t *pvht_cap;
+    MrvlIETypes_OperModeNtf_t *pmrvl_oper_mode;
+    t_u16 mcs_map_user = 0;
+    t_u16 nss;
+    int ret_len = 0;
+
+    ENTER();
+
+    /* Null Checks */
+    if (ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    if (*ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    /* VHT Capabilities IE */
+    if (pbss_desc->pvht_cap != MNULL && wlan_get_nss_vht_mcs(pbss_desc->pvht_cap->vht_cap.mcs_sets.rx_mcs_map) != 0U)
+    {
+        pvht_cap = (MrvlIETypes_VHTCap_t *)(void *)*ppbuffer;
+        (void)__memset(pmadapter, pvht_cap, 0, sizeof(MrvlIETypes_VHTCap_t));
+        pvht_cap->header.type = wlan_cpu_to_le16(VHT_CAPABILITY);
+        pvht_cap->header.len  = (t_u16)sizeof(VHT_capa_t);
+        (void)__memcpy(pmadapter, (t_u8 *)pvht_cap + sizeof(MrvlIEtypesHeader_t),
+                       (t_u8 *)pbss_desc->pvht_cap + sizeof(IEEEtypes_Header_t), pvht_cap->header.len);
+
+        wlan_fill_vht_cap_tlv(pmpriv, pvht_cap, pbss_desc->bss_band, (t_u8)MTRUE);
+        if (wlan_use_non_default_ht_vht_cap(pbss_desc))
+        {
+            /* Indicate 3 STS in VHT cap info */
+            pvht_cap->vht_cap.vht_cap_info = ((pvht_cap->vht_cap.vht_cap_info & (~(0x7 << 13))) | (0x2 << 13));
+        }
+
+        HEXDUMP("VHT_CAPABILITIES IE", (t_u8 *)pvht_cap, sizeof(MrvlIETypes_VHTCap_t));
+        *ppbuffer += sizeof(MrvlIETypes_VHTCap_t);
+        ret_len += (int)sizeof(MrvlIETypes_VHTCap_t);
+        pvht_cap->header.len = wlan_cpu_to_le16(pvht_cap->header.len);
+    }
+    else
+    {
+        LEAVE();
+        return 0;
+    }
+
+    /* Operating Mode Notification IE */
+    pmrvl_oper_mode = (MrvlIETypes_OperModeNtf_t *)(void *)*ppbuffer;
+    (void)__memset(pmadapter, pmrvl_oper_mode, 0, sizeof(MrvlIETypes_OperModeNtf_t));
+    pmrvl_oper_mode->header.type = wlan_cpu_to_le16(OPER_MODE_NTF);
+    pmrvl_oper_mode->header.len  = (t_u16)sizeof(t_u8);
+
+    if (pmadapter->usr_dot_11ac_opermode_bw != 0U || pmadapter->usr_dot_11ac_opermode_nss != 0U)
+    {
+        pmrvl_oper_mode->oper_mode |= (pmadapter->usr_dot_11ac_opermode_nss - 1U) << 4U;
+        pmrvl_oper_mode->oper_mode |= pmadapter->usr_dot_11ac_opermode_bw - 1U;
+        if ((pbss_desc->bss_band & BAND_G) != 0U)
+        {
+            if (!(IS_OPER_MODE_20M(pmrvl_oper_mode->oper_mode)))
+            {
+                if ((pbss_desc->pht_cap->ht_cap.ht_cap_info & MBIT(1)) != 0U)
+                {
+                    SET_OPER_MODE_40M(pmrvl_oper_mode->oper_mode);
+                }
+                else
+                {
+                    SET_OPER_MODE_20M(pmrvl_oper_mode->oper_mode);
+                }
+            }
+        }
+    }
+    else
+    {
+        /** set default bandwidth:80M*/
+        SET_OPER_MODE_80M(pmrvl_oper_mode->oper_mode);
+
+        mcs_map_user = (t_u16)GET_DEVRXMCSMAP(pmadapter->usr_dot_11ac_mcs_support);
+        nss          = wlan_get_nss_num_vht_mcs(mcs_map_user);
+        pmrvl_oper_mode->oper_mode |= (t_u8)(nss - 1U) << 4U;
+
+        switch (pbss_desc->curr_bandwidth)
+        {
+            case BW_20MHZ:
+                SET_OPER_MODE_20M(pmrvl_oper_mode->oper_mode);
+                break;
+            case BW_40MHZ:
+                SET_OPER_MODE_40M(pmrvl_oper_mode->oper_mode);
+                break;
+            case BW_80MHZ:
+            default:
+                PRINTM(MINFO, "Unexpected bandwidth.\n");
+                break;
+        }
+    }
+    HEXDUMP("OPER MODE NTF IE", (t_u8 *)pmrvl_oper_mode, sizeof(MrvlIETypes_OperModeNtf_t));
+    *ppbuffer += sizeof(MrvlIETypes_OperModeNtf_t);
+    ret_len += (int)sizeof(MrvlIETypes_OperModeNtf_t);
+    pmrvl_oper_mode->header.len = wlan_cpu_to_le16(pmrvl_oper_mode->header.len);
+
+    LEAVE();
+    return ret_len;
+}
+
+#if 0
+/**
+ *  @brief 11ac configuration handler
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return     MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+mlan_status wlan_11ac_cfg_ioctl(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status = MLAN_STATUS_SUCCESS;
+    mlan_ds_11ac_cfg *cfg = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_11ac_cfg)) {
+        PRINTM(MINFO, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed = sizeof(mlan_ds_11ac_cfg);
+        pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    cfg = (mlan_ds_11ac_cfg *)pioctl_req->pbuf;
+    switch (cfg->sub_command) {
+        case MLAN_OID_11AC_VHT_CFG:
+            status = wlan_11ac_ioctl_vhtcfg(pmadapter, pioctl_req);
+            break;
+        case MLAN_OID_11AC_CFG_SUPPORTED_MCS_SET:
+            status = wlan_11ac_ioctl_supported_mcs_set(pmadapter, pioctl_req);
+            break;
+        case MLAN_OID_11AC_OPERMODE_CFG:
+            status = wlan_11ac_ioctl_opermodecfg(pmadapter, pioctl_req);
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+#endif
+
+/**
+ *  @brief This function prepares 11ac cfg command
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd      A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_11ac_cfg(IN pmlan_private pmpriv,
+                              IN HostCmd_DS_COMMAND *cmd,
+                              IN t_u16 cmd_action,
+                              IN t_void *pdata_buf)
+{
+    HostCmd_DS_11AC_CFG *vhtcfg   = &cmd->params.vhtcfg;
+    mlan_ds_11ac_vht_cfg *vht_cfg = (mlan_ds_11ac_vht_cfg *)pdata_buf;
+
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_11AC_CFG);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_11AC_CFG) + S_DS_GEN);
+    if (pmpriv->bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        cmd->seq_num = (t_u16)(0x01U) << 12;
+    }
+    vhtcfg->action      = wlan_cpu_to_le16(cmd_action);
+    vhtcfg->band_config = (t_u8)(vht_cfg->band & 0xFFU);
+    vhtcfg->misc_config = (t_u8)(vht_cfg->txrx & 0x3U);
+    if (vhtcfg->misc_config != 2U)
+    {
+        vhtcfg->misc_config |= (t_u8)(vht_cfg->bwcfg << 2);
+    }
+
+    vhtcfg->vht_cap_info = wlan_cpu_to_le32(vht_cfg->vht_cap_info);
+    vht_cfg->vht_rx_mcs  = wlan_cpu_to_le32(vht_cfg->vht_rx_mcs);
+    (void)__memcpy(pmpriv->adapter, &vhtcfg->vht_supp_mcs_set[0], &vht_cfg->vht_rx_mcs, sizeof(t_u32));
+    vht_cfg->vht_tx_mcs = wlan_cpu_to_le32(vht_cfg->vht_tx_mcs);
+    (void)__memcpy(pmpriv->adapter, &vhtcfg->vht_supp_mcs_set[4], &vht_cfg->vht_tx_mcs, sizeof(t_u32));
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if 0
+/**
+ *  @brief This function handles the command response of 11ac cfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_11ac_cfg(
+    IN  pmlan_private        pmpriv,
+    IN  HostCmd_DS_COMMAND   *resp,
+    IN  mlan_ioctl_req       *pioctl_buf)
+{
+    pmlan_adapter        pmadapter = pmpriv->adapter;
+    mlan_ds_11ac_cfg    *cfg = MNULL;
+    HostCmd_DS_11AC_CFG *vhtcfg = &resp->params.vhtcfg;
+
+    ENTER();
+    if (pioctl_buf && (wlan_le16_to_cpu(vhtcfg->action) == HostCmd_ACT_GEN_GET)) {
+        cfg = (mlan_ds_11ac_cfg *)pioctl_buf->pbuf;
+        cfg->param.vht_cfg.band = vhtcfg->band_config;
+        cfg->param.vht_cfg.txrx = vhtcfg->misc_config & 0x03;
+        if (cfg->param.vht_cfg.txrx & 0x1)
+            cfg->param.vht_cfg.bwcfg = (vhtcfg->misc_config & 0x04) >> 2;
+        else
+            cfg->param.vht_cfg.bwcfg = 0;
+
+        cfg->param.vht_cfg.vht_cap_info = wlan_le32_to_cpu(vhtcfg->vht_cap_info);
+        (void)__memcpy(pmadapter, &cfg->param.vht_cfg.vht_rx_mcs,
+                          &vhtcfg->vht_supp_mcs_set[0], sizeof(t_u32));
+        cfg->param.vht_cfg.vht_rx_mcs =
+            wlan_le32_to_cpu(cfg->param.vht_cfg.vht_rx_mcs);
+        (void)__memcpy(pmadapter, &cfg->param.vht_cfg.vht_tx_mcs,
+                          &vhtcfg->vht_supp_mcs_set[4], sizeof(t_u32));
+        cfg->param.vht_cfg.vht_tx_mcs =
+            wlan_le32_to_cpu(cfg->param.vht_cfg.vht_tx_mcs);
+        cfg->param.vht_cfg.vht_rx_max_rate =
+			wlan_convert_mcsmap_to_maxrate(pmpriv,cfg->param.vht_cfg.band,cfg->param.vht_cfg.vht_rx_mcs);
+        cfg->param.vht_cfg.vht_tx_max_rate =
+			wlan_convert_mcsmap_to_maxrate(pmpriv, cfg->param.vht_cfg.band,cfg->param.vht_cfg.vht_tx_mcs);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+void wlan_update_11ac_cap(mlan_private * pmpriv){
+
+    mlan_adapter* pmadapter = pmpriv->adapter;
+
+    pmpriv->usr_dot_11ac_mcs_support = pmadapter->hw_dot_11ac_mcs_support;
+    pmpriv->usr_dot_11ac_dev_cap_bg =
+		pmadapter->hw_dot_11ac_dev_cap & ~DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK;
+#if CONFIG_5GHz_SUPPORT
+    pmpriv->usr_dot_11ac_dev_cap_a =
+		pmadapter->hw_dot_11ac_dev_cap & ~DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK;
+#endif
+    pmpriv->usr_dot_11ac_bw = BW_FOLLOW_VHTCAP;
+}
+#endif
+
+/**
+ *  @brief This function check if 11AC is allowed in bandcfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param bss_band     bss band
+ *
+ *  @return 0--not allowed, other value allowed
+ */
+t_u8 wlan_11ac_bandconfig_allowed(mlan_private *pmpriv, t_u16 bss_band)
+{
+    if (pmpriv->bss_mode == MLAN_BSS_MODE_IBSS)
+    {
+        if ((bss_band & BAND_G) != 0U)
+        {
+            return (t_u8)(pmpriv->adapter->adhoc_start_band & BAND_GAC);
+        }
+#if CONFIG_5GHz_SUPPORT
+        else if ((bss_band & BAND_A) != 0U)
+        {
+            return (t_u8)(pmpriv->adapter->adhoc_start_band & BAND_AAC);
+        }
+        else
+        { /* Do Nothing */
+        }
+#endif
+    }
+    else
+    {
+        if ((bss_band & BAND_G) != 0U)
+        {
+            return (t_u8)(pmpriv->config_bands & BAND_GAC);
+        }
+#if CONFIG_5GHz_SUPPORT
+        else if ((bss_band & BAND_A) != 0U)
+        {
+            return (t_u8)(pmpriv->config_bands & BAND_AAC);
+        }
+        else
+        { /* Do Nothing */
+        }
+#endif
+    }
+    return 0;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11ax.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11ax.c
new file mode 100644
index 0000000000..4843e16192
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11ax.c
@@ -0,0 +1,730 @@
+/** @file mlan_11ax.c
+ *
+ *  @brief This file defines the private and adapter data
+ *  structures and declares global function prototypes used
+ *  in MLAN module.
+ *
+ *  Copyright 2021-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+#if CONFIG_11AX
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+#if defined(RW610)
+#include "wifi-imu.h"
+#else
+#include "wifi-sdio.h"
+#endif
+/********************************************************
+ *    Local Variables
+ *    ********************************************************/
+
+static t_u8 user_he_cap_band;
+/********************************************************
+ *    Global Variables
+ *    ********************************************************/
+
+/********************************************************
+ *    Local Functions
+ *    *******************************************************/
+
+/**
+ *  @brief This function check if AP support TWT Response.
+ *
+ *  @param pbss_desc    A pointer to BSSDescriptor_t structure
+ *
+ *  @return        MTRUE/MFALSE
+ */
+t_u8 wlan_check_ap_11ax_twt_supported(BSSDescriptor_t *pbss_desc)
+{
+    if (!pbss_desc->phe_cap)
+        return MFALSE;
+    if (!(pbss_desc->phe_cap->he_mac_cap[0] & HE_MAC_CAP_TWT_RESP_SUPPORT))
+        return MFALSE;
+    if (!pbss_desc->pext_cap)
+        return MFALSE;
+    if (!ISSUPP_EXTCAP_EXT_TWT_RESP(pbss_desc->pext_cap->ext_cap))
+        return MFALSE;
+    return MTRUE;
+}
+
+/**
+ *  @brief This function check if we should enable TWT support
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc    A pointer to BSSDescriptor_t structure
+ *
+ *  @return        MTRUE/MFALSE
+ */
+t_u8 wlan_check_11ax_twt_supported(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+#if CONFIG_5GHz_SUPPORT
+    MrvlIEtypes_He_cap_t *phecap    = (MrvlIEtypes_He_cap_t *)&pmpriv->user_he_cap;
+    MrvlIEtypes_He_cap_t *hw_he_cap = (MrvlIEtypes_He_cap_t *)&pmadapter->hw_he_cap;
+#else
+    MrvlIEtypes_He_cap_t *phecap    = (MrvlIEtypes_He_cap_t *)&pmpriv->user_2g_he_cap;
+    MrvlIEtypes_He_cap_t *hw_he_cap = (MrvlIEtypes_He_cap_t *)&pmadapter->hw_2g_he_cap;
+#endif
+
+    if (pbss_desc && !wlan_check_ap_11ax_twt_supported(pbss_desc))
+    {
+        PRINTM(MINFO, "AP don't support twt feature\n");
+        return MFALSE;
+    }
+    if (pbss_desc)
+    {
+        if (pbss_desc->bss_band & BAND_A)
+        {
+            hw_he_cap = (MrvlIEtypes_He_cap_t *)&pmadapter->hw_he_cap;
+            phecap    = (MrvlIEtypes_He_cap_t *)&pmpriv->user_he_cap;
+        }
+        else
+        {
+            hw_he_cap = (MrvlIEtypes_He_cap_t *)&pmadapter->hw_2g_he_cap;
+            phecap    = (MrvlIEtypes_He_cap_t *)&pmpriv->user_2g_he_cap;
+        }
+    }
+    if (!(hw_he_cap->he_mac_cap[0] & HE_MAC_CAP_TWT_REQ_SUPPORT))
+    {
+        PRINTM(MINFO, "FW don't support TWT\n");
+        return MFALSE;
+    }
+    if (phecap->he_mac_cap[0] & HE_MAC_CAP_TWT_REQ_SUPPORT)
+        return MTRUE;
+    PRINTM(MINFO, "USER HE_MAC_CAP don't support TWT\n");
+    return MFALSE;
+}
+
+/**
+ *  @brief This function fills the HE cap tlv out put format is LE, not CPU
+ *
+ *  @param pmpriv         A pointer to mlan_private structure
+ *  @param band           5G or 2.4 G
+ *  @param phe_cap        A pointer to MrvlIEtypes_Data_t structure
+ *  @param flag           MTRUE -- phe_cap has the setting for resp
+ *                                 MFALSE -- phe_cap is clean
+ *
+ *  @return bytes added to the phe_cap
+ */
+
+t_u16 wlan_fill_he_cap_tlv(mlan_private *pmpriv, t_u16 band, MrvlIEtypes_Extension_t *phe_cap, t_u8 flag)
+{
+    t_u16 len = 0;
+
+    if (!phe_cap)
+        return 0;
+
+    if (user_he_cap_band)
+    {
+        if (user_he_cap_band & MBIT(1))
+        {
+            (void)__memcpy(pmpriv->adapter, (t_u8 *)phe_cap, pmpriv->user_he_cap, pmpriv->user_hecap_len);
+            len = pmpriv->user_hecap_len;
+        }
+        else
+        {
+            (void)__memcpy(pmpriv->adapter, (t_u8 *)phe_cap, pmpriv->user_2g_he_cap, pmpriv->user_2g_hecap_len);
+            len = pmpriv->user_2g_hecap_len;
+        }
+    }
+    else
+    {
+        if (band & (t_u16)BAND_AAX)
+        {
+            (void)__memcpy(pmpriv->adapter, (t_u8 *)phe_cap, pmpriv->user_he_cap, pmpriv->user_hecap_len);
+            len = pmpriv->user_hecap_len;
+        }
+        else
+        {
+            (void)__memcpy(pmpriv->adapter, (t_u8 *)phe_cap, pmpriv->user_2g_he_cap, pmpriv->user_2g_hecap_len);
+            len = pmpriv->user_2g_hecap_len;
+        }
+    }
+    phe_cap->type = wlan_cpu_to_le16(phe_cap->type);
+    phe_cap->len  = wlan_cpu_to_le16(phe_cap->len);
+
+    return len;
+}
+
+/**
+ *  @brief This function append the 802_11ax HE capability  tlv
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc    A pointer to BSSDescriptor_t structure
+ *  @param ppbuffer     A Pointer to command buffer pointer
+ *
+ *  @return bytes added to the buffer
+ */
+int wlan_cmd_append_11ax_tlv(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc, t_u8 **ppbuffer)
+{
+    MrvlIEtypes_He_cap_t *phecap = MNULL;
+    int len                      = 0;
+
+    ENTER();
+    /* Null Checks */
+    if (ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    if (*ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    /** check if AP support HE, if not return right away */
+    if (!pbss_desc->phe_cap)
+    {
+        LEAVE();
+        return 0;
+    }
+    phecap = (MrvlIEtypes_He_cap_t *)*ppbuffer;
+    if (pbss_desc->bss_band & BAND_A)
+    {
+        (void)__memcpy(pmpriv->adapter, *ppbuffer, pmpriv->user_he_cap, pmpriv->user_hecap_len);
+        *ppbuffer += pmpriv->user_hecap_len;
+        len = pmpriv->user_hecap_len;
+    }
+    else
+    {
+        (void)__memcpy(pmpriv->adapter, *ppbuffer, pmpriv->user_2g_he_cap, pmpriv->user_2g_hecap_len);
+        *ppbuffer += pmpriv->user_2g_hecap_len;
+        len = pmpriv->user_2g_hecap_len;
+    }
+    phecap->type = wlan_cpu_to_le16(phecap->type);
+    phecap->len  = wlan_cpu_to_le16(phecap->len);
+    phecap->he_phy_cap[0] &= ~(MBIT(3) | MBIT(4));
+    LEAVE();
+    return len;
+}
+
+/**
+ *  @brief This function save the 11ax cap from FW.
+ *
+ *  @param pmadapater   A pointer to mlan_adapter
+ *  @param hw_he_cap    A pointer to MrvlIEtypes_Extension_t
+ *  @param tlv_idx      0 for 2.4G, 1 for 5G
+ *
+ *  @return N/A
+ */
+void wlan_update_11ax_cap(mlan_adapter *pmadapter,
+                          MrvlIEtypes_Extension_t *hw_he_cap
+#ifdef RW610
+                          ,
+                          int tlv_idx
+#endif
+)
+{
+#ifndef RW610
+    MrvlIEtypes_He_cap_t *phe_cap = MNULL;
+#endif
+    t_u8 i         = 0;
+    t_u8 he_cap_2g = 0;
+#if CONFIG_11AX_TWT
+    MrvlIEtypes_He_cap_t *user_he_cap_tlv = MNULL;
+#endif
+
+    ENTER();
+    if ((hw_he_cap->len + sizeof(MrvlIEtypesHeader_t)) > sizeof(pmadapter->hw_he_cap))
+    {
+        PRINTM(MERROR, "hw_he_cap too big, len=%d\n", hw_he_cap->len);
+        LEAVE();
+        return;
+    }
+#ifndef RW610
+    phe_cap = (MrvlIEtypes_He_cap_t *)hw_he_cap;
+    if (phe_cap->he_phy_cap[0] & (AX_2G_20MHZ_SUPPORT | AX_2G_40MHZ_SUPPORT))
+#else
+    if (tlv_idx == AX_2G_TLV_INDEX)
+#endif
+    {
+        pmadapter->hw_2g_hecap_len = hw_he_cap->len + sizeof(MrvlIEtypesHeader_t);
+        (void)__memcpy(pmadapter, pmadapter->hw_2g_he_cap, (t_u8 *)hw_he_cap,
+                       hw_he_cap->len + sizeof(MrvlIEtypesHeader_t));
+        pmadapter->fw_bands |= BAND_GAX;
+        pmadapter->config_bands |= BAND_GAX;
+        he_cap_2g = MTRUE;
+        DBG_HEXDUMP(MCMD_D, "2.4G HE capability IE ", (t_u8 *)pmadapter->hw_2g_he_cap, pmadapter->hw_2g_hecap_len);
+    }
+    else
+    {
+        pmadapter->fw_bands |= BAND_AAX;
+        pmadapter->config_bands |= BAND_AAX;
+        pmadapter->hw_hecap_len = hw_he_cap->len + sizeof(MrvlIEtypesHeader_t);
+        (void)__memcpy(pmadapter, pmadapter->hw_he_cap, (t_u8 *)hw_he_cap,
+                       hw_he_cap->len + sizeof(MrvlIEtypesHeader_t));
+        DBG_HEXDUMP(MCMD_D, "5G HE capability IE ", (t_u8 *)pmadapter->hw_he_cap, pmadapter->hw_hecap_len);
+    }
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        if (pmadapter->priv[i])
+        {
+            pmadapter->priv[i]->config_bands = pmadapter->config_bands;
+            if (he_cap_2g)
+            {
+                pmadapter->priv[i]->user_2g_hecap_len = pmadapter->hw_2g_hecap_len;
+                (void)__memcpy(pmadapter, pmadapter->priv[i]->user_2g_he_cap, pmadapter->hw_2g_he_cap,
+                               pmadapter->hw_2g_hecap_len);
+            }
+            else
+            {
+                pmadapter->priv[i]->user_hecap_len = pmadapter->hw_hecap_len;
+                (void)__memcpy(pmadapter, pmadapter->priv[i]->user_he_cap, pmadapter->hw_he_cap,
+                               pmadapter->hw_hecap_len);
+            }
+#if CONFIG_11AX_TWT
+            /**
+             *  Clear TWT bits in he_mac_cap by bss role
+             *  STA mode should clear TWT responder bit
+             *  UAP mode should clear TWT request bit
+             */
+            if (he_cap_2g)
+                user_he_cap_tlv = (MrvlIEtypes_He_cap_t *)&pmadapter->priv[i]->user_2g_he_cap;
+            else
+                user_he_cap_tlv = (MrvlIEtypes_He_cap_t *)&pmadapter->priv[i]->user_he_cap;
+
+            if (pmadapter->priv[i]->bss_role == MLAN_BSS_ROLE_STA)
+                user_he_cap_tlv->he_mac_cap[0] &= ~HE_MAC_CAP_TWT_RESP_SUPPORT;
+            else
+                user_he_cap_tlv->he_mac_cap[0] &= ~HE_MAC_CAP_TWT_REQ_SUPPORT;
+#endif
+        }
+    }
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function check if 11AX is allowed in bandcfg
+ *
+ *  @param pmpriv	A pointer to mlan_private structure
+ *  @param bss_band 	bss band
+ *
+ *  @return 0--not allowed, other value allowed
+ */
+t_u16 wlan_11ax_bandconfig_allowed(mlan_private *pmpriv, t_u16 bss_band)
+{
+    if (!IS_FW_SUPPORT_11AX(pmpriv->adapter))
+        return MFALSE;
+    if (pmpriv->bss_mode == MLAN_BSS_MODE_IBSS)
+    {
+        if (bss_band & BAND_G)
+            return (pmpriv->adapter->adhoc_start_band & BAND_GAX);
+#if CONFIG_5GHz_SUPPORT
+        else if (bss_band & BAND_A)
+            return (pmpriv->adapter->adhoc_start_band & BAND_AAX);
+#endif
+    }
+    else
+    {
+        if (bss_band & BAND_G)
+            return (pmpriv->config_bands & BAND_GAX);
+#if CONFIG_5GHz_SUPPORT
+        else if (bss_band & BAND_A)
+            return (pmpriv->config_bands & BAND_AAX);
+#endif
+    }
+    return MFALSE;
+}
+
+mlan_status wlan_11ax_ioctl_cmd(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status        = MLAN_STATUS_SUCCESS;
+    mlan_ds_11ax_cmd_cfg *cfg = MNULL;
+    mlan_private *pmpriv      = pmadapter->priv[pioctl_req->bss_index];
+    t_u16 cmd_action          = 0;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_11ax_cmd_cfg))
+    {
+        PRINTM(MINFO, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_11ax_cmd_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    cfg = (mlan_ds_11ax_cmd_cfg *)pioctl_req->pbuf;
+
+    if (pioctl_req->action == MLAN_ACT_SET)
+        cmd_action = HostCmd_ACT_GEN_SET;
+    else
+        cmd_action = HostCmd_ACT_GEN_GET;
+
+    /* Send request to firmware */
+    status = wifi_prepare_and_send_cmd(pmpriv, HostCmd_CMD_11AX_CMD, cmd_action, 0, (t_void *)pioctl_req, (t_void *)cfg,
+                                       pmpriv->bss_type, NULL);
+    if (status == MLAN_STATUS_SUCCESS)
+        status = MLAN_STATUS_PENDING;
+
+    LEAVE();
+    return status;
+}
+
+/**
+ *  @brief 11ax configuration handler
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return     MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+mlan_status wlan_11ax_cfg_ioctl(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status    = MLAN_STATUS_SUCCESS;
+    mlan_ds_11ax_cfg *cfg = MNULL;
+
+    ENTER();
+
+    cfg = (mlan_ds_11ax_cfg *)pioctl_req->pbuf;
+    switch (cfg->sub_command)
+    {
+        case MLAN_OID_11AX_CMD_CFG:
+            status = wlan_11ax_ioctl_cmd(pmadapter, pioctl_req);
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+
+/**
+ *  @brief This function prepares and sends 11ax cfg command
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param action       the action: GET or SET
+ *  @param he_cfg       A pointer to mlan_ds_11ax_he_cfg structure
+ *
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+int wlan_cmd_11ax_cfg(mlan_private *pmpriv, t_u16 action, mlan_ds_11ax_he_cfg *he_cfg)
+{
+    HostCmd_DS_11AX_CFG *axcfg   = MNULL;
+    t_u8 *pos                    = MNULL;
+    MrvlIEtypes_Extension_t *tlv = MNULL;
+
+    ENTER();
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    cmd->command            = wlan_cpu_to_le16(HostCmd_CMD_11AX_CFG);
+    cmd->size               = S_DS_GEN + sizeof(HostCmd_DS_11AX_CFG);
+    axcfg                   = (HostCmd_DS_11AX_CFG *)((t_u32)cmd + S_DS_GEN);
+    axcfg->action           = action;
+    axcfg->band_config      = he_cfg->band & 0xFF;
+    pos                     = (t_u8 *)axcfg->val;
+    /** HE Capability */
+    if (he_cfg->he_cap.len && (he_cfg->he_cap.ext_id == HE_CAPABILITY))
+    {
+        tlv       = (MrvlIEtypes_Extension_t *)pos;
+        tlv->type = wlan_cpu_to_le16(he_cfg->he_cap.id);
+        tlv->len  = wlan_cpu_to_le16(he_cfg->he_cap.len);
+        (void)__memcpy(pmpriv->adapter, &tlv->ext_id, &he_cfg->he_cap.ext_id, he_cfg->he_cap.len);
+        cmd->size += he_cfg->he_cap.len + sizeof(MrvlIEtypesHeader_t);
+        pos += he_cfg->he_cap.len + sizeof(MrvlIEtypesHeader_t);
+    }
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, pmpriv->bss_index);
+    cmd->result  = 0x00;
+
+    wifi_wait_for_cmdresp(he_cfg);
+    LEAVE();
+    return wm_wifi.cmd_resp_status;
+}
+
+/**
+ *  @brief This function handles the command response of 11axcfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param hecfg        A pointer to mlan_ds_11ax_he_cfg structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_11ax_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ds_11ax_he_cfg *hecfg)
+{
+    HostCmd_DS_11AX_CFG *axcfg   = (HostCmd_DS_11AX_CFG *)&resp->params.axcfg;
+    mlan_ds_11ax_he_capa *hecap  = MNULL;
+    MrvlIEtypes_Extension_t *tlv = MNULL;
+    t_u16 left_len = 0, tlv_type = 0, tlv_len = 0;
+
+    ENTER();
+
+    if (hecfg == MNULL)
+        goto done;
+
+    hecfg->band = axcfg->band_config;
+    hecap       = (mlan_ds_11ax_he_capa *)&hecfg->he_cap;
+
+    /* TLV parse */
+    left_len = resp->size - sizeof(HostCmd_DS_11AX_CFG) - S_DS_GEN;
+    tlv      = (MrvlIEtypes_Extension_t *)axcfg->val;
+
+    while (left_len > sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+        if (tlv_type == EXTENSION)
+        {
+            switch (tlv->ext_id)
+            {
+                case HE_CAPABILITY:
+                    hecap->id  = tlv_type;
+                    hecap->len = tlv_len;
+                    (void)__memcpy(pmpriv->adapter, (t_u8 *)&hecap->ext_id, (t_u8 *)&tlv->ext_id, tlv_len);
+                    user_he_cap_band = hecfg->band;
+                    if (hecfg->band & MBIT(1))
+                    {
+                        (void)__memcpy(pmpriv->adapter, (t_u8 *)&pmpriv->user_he_cap, (t_u8 *)tlv,
+                                       tlv_len + sizeof(MrvlIEtypesHeader_t));
+                        pmpriv->user_hecap_len =
+                            MIN(tlv_len + sizeof(MrvlIEtypesHeader_t), sizeof(pmpriv->user_he_cap));
+                        PRINTM(MCMND, "user_hecap_len=%d\n", pmpriv->user_hecap_len);
+                        wcmdr_d("user_hecap_len=%d\n", pmpriv->user_hecap_len);
+                    }
+                    else
+                    {
+                        (void)__memcpy(pmpriv->adapter, (t_u8 *)&pmpriv->user_2g_he_cap, (t_u8 *)tlv,
+                                       tlv_len + sizeof(MrvlIEtypesHeader_t));
+                        pmpriv->user_2g_hecap_len =
+                            MIN(tlv_len + sizeof(MrvlIEtypesHeader_t), sizeof(pmpriv->user_2g_he_cap));
+                        PRINTM(MCMND, "user_2g_hecap_len=%d\n", pmpriv->user_2g_hecap_len);
+                        wcmdr_d("user_2g_hecap_len=%d\n", pmpriv->user_2g_hecap_len);
+                    }
+                    break;
+                default:
+                    PRINTM(MINFO, "Unexpected extentsion \n");
+                    break;
+            }
+        }
+
+        left_len -= (sizeof(MrvlIEtypesHeader_t) + tlv_len);
+        tlv = (MrvlIEtypes_Extension_t *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+done:
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if CONFIG_11AX_TWT
+/**
+ *  @brief              This function prepares TWT cfg command to configure setup/teardown
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             Status returned
+ */
+mlan_status wlan_cmd_twt_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    HostCmd_DS_TWT_CFG *hostcmd_twtcfg              = (HostCmd_DS_TWT_CFG *)&cmd->params.twtcfg;
+    mlan_ds_twtcfg *ds_twtcfg                       = (mlan_ds_twtcfg *)pdata_buf;
+    hostcmd_twt_setup *twt_setup_params             = MNULL;
+    hostcmd_twt_teardown *twt_teardown_params       = MNULL;
+    hostcmd_twt_report *twt_report_params           = MNULL;
+    mlan_status ret                                 = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_TWT_CFG);
+
+    hostcmd_twtcfg->action = wlan_cpu_to_le16(cmd_action);
+    hostcmd_twtcfg->sub_id = wlan_cpu_to_le16(ds_twtcfg->sub_id);
+
+    cmd->size = S_DS_GEN + sizeof(hostcmd_twtcfg->action) + sizeof(hostcmd_twtcfg->sub_id);
+    switch (hostcmd_twtcfg->sub_id)
+    {
+        case MLAN_11AX_TWT_SETUP_SUBID:
+            twt_setup_params = &hostcmd_twtcfg->param.twt_setup;
+            __memset(pmpriv->adapter, twt_setup_params, 0x00, sizeof(hostcmd_twtcfg->param.twt_setup));
+            twt_setup_params->implicit            = ds_twtcfg->param.twt_setup.implicit;
+            twt_setup_params->announced           = ds_twtcfg->param.twt_setup.announced;
+            twt_setup_params->trigger_enabled     = ds_twtcfg->param.twt_setup.trigger_enabled;
+            twt_setup_params->twt_info_disabled   = ds_twtcfg->param.twt_setup.twt_info_disabled;
+            twt_setup_params->negotiation_type    = ds_twtcfg->param.twt_setup.negotiation_type;
+            twt_setup_params->twt_wakeup_duration = ds_twtcfg->param.twt_setup.twt_wakeup_duration;
+            twt_setup_params->flow_identifier     = ds_twtcfg->param.twt_setup.flow_identifier;
+            twt_setup_params->hard_constraint     = ds_twtcfg->param.twt_setup.hard_constraint;
+            twt_setup_params->twt_exponent        = ds_twtcfg->param.twt_setup.twt_exponent;
+            twt_setup_params->twt_mantissa        = wlan_cpu_to_le16(ds_twtcfg->param.twt_setup.twt_mantissa);
+            twt_setup_params->twt_request         = ds_twtcfg->param.twt_setup.twt_request;
+            cmd->size += sizeof(hostcmd_twtcfg->param.twt_setup);
+            break;
+        case MLAN_11AX_TWT_TEARDOWN_SUBID:
+            twt_teardown_params = &hostcmd_twtcfg->param.twt_teardown;
+            __memset(pmpriv->adapter, twt_teardown_params, 0x00, sizeof(hostcmd_twtcfg->param.twt_teardown));
+            twt_teardown_params->flow_identifier  = ds_twtcfg->param.twt_teardown.flow_identifier;
+            twt_teardown_params->negotiation_type = ds_twtcfg->param.twt_teardown.negotiation_type;
+            twt_teardown_params->teardown_all_twt = ds_twtcfg->param.twt_teardown.teardown_all_twt;
+            cmd->size += sizeof(hostcmd_twtcfg->param.twt_teardown);
+            break;
+        case MLAN_11AX_TWT_REPORT_SUBID:
+
+            twt_report_params = &hostcmd_twtcfg->param.twt_report;
+            __memset(pmpriv->adapter, twt_report_params, 0x00, sizeof(hostcmd_twtcfg->param.twt_report));
+            twt_report_params->type = ds_twtcfg->param.twt_report.type;
+            cmd->size += sizeof(hostcmd_twtcfg->param.twt_report);
+            break;
+        default:
+            PRINTM(MERROR, "Unknown subcmd %x\n", ds_twtcfg->sub_id);
+            ret = MLAN_STATUS_FAILURE;
+            break;
+    }
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    LEAVE();
+    return ret;
+}
+#endif /* CONFIG_11AX_TWT */
+
+/**
+ *  @brief This function prepares 11ax command
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd      A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_11ax_cmd(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    HostCmd_DS_11AX_CMD_CFG *axcmd        = &cmd->params.axcmd;
+    mlan_ds_11ax_cmd_cfg *ds_11ax_cmd     = (mlan_ds_11ax_cmd_cfg *)pdata_buf;
+    mlan_ds_11ax_txomi_cmd *txomi_cmd     = (mlan_ds_11ax_txomi_cmd *)&ds_11ax_cmd->param;
+    mlan_ds_11ax_toltime_cmd *toltime_cmd = (mlan_ds_11ax_toltime_cmd *)&ds_11ax_cmd->param;
+
+
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_11AX_CMD);
+    cmd->size    = sizeof(HostCmd_DS_11AX_CMD_CFG) + S_DS_GEN;
+
+    axcmd->action = wlan_cpu_to_le16(cmd_action);
+    axcmd->sub_id = wlan_cpu_to_le16(ds_11ax_cmd->sub_id);
+    switch (ds_11ax_cmd->sub_id)
+    {
+        case MLAN_11AXCMD_TXOMI_SUBID:
+            (void)__memcpy(pmpriv->adapter, axcmd->val, txomi_cmd, sizeof(mlan_ds_11ax_txomi_cmd));
+            cmd->size += sizeof(mlan_ds_11ax_txomi_cmd);
+            break;
+        case MLAN_11AXCMD_OBSS_TOLTIME_SUBID:
+            (void)__memcpy(pmpriv->adapter, axcmd->val, &toltime_cmd->tol_time, sizeof(t_u32));
+            cmd->size += sizeof(t_u32);
+            break;
+        default:
+            PRINTM(MERROR, "Unknown subcmd %x\n", ds_11ax_cmd->sub_id);
+            break;
+    }
+
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of 11axcmd
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_11ax_cmd(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_11ax_cmd_cfg *cfg      = MNULL;
+    HostCmd_DS_11AX_CMD_CFG *axcmd = &resp->params.axcmd;
+    MrvlIEtypes_Data_t *tlv        = MNULL;
+    t_s16 left_len                 = 0;
+    t_u16 tlv_len                  = 0;
+
+    ENTER();
+    if (axcmd->action != HostCmd_ACT_GEN_GET)
+    {
+        goto done;
+    }
+    cfg = (mlan_ds_11ax_cmd_cfg *)pioctl_buf->pbuf;
+    switch (axcmd->sub_id)
+    {
+        case MLAN_11AXCMD_SR_SUBID:
+            /* TLV parse */
+            left_len = resp->size - sizeof(HostCmd_DS_11AX_CMD_CFG) - S_DS_GEN;
+            tlv      = (MrvlIEtypes_Data_t *)axcmd->val;
+            while (left_len > (t_s16)sizeof(MrvlIEtypesHeader_t))
+            {
+                tlv_len = wlan_le16_to_cpu(tlv->header.len);
+                (void)__memcpy(pmpriv->adapter, cfg->param.sr_cfg.param.obss_pd_offset.offset, tlv->data, tlv_len);
+                left_len -= (sizeof(MrvlIEtypesHeader_t) + tlv_len);
+                tlv = (MrvlIEtypes_Data_t *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+            }
+            break;
+        case MLAN_11AXCMD_BEAM_SUBID:
+            cfg->param.beam_cfg.value = *axcmd->val;
+            break;
+        case MLAN_11AXCMD_HTC_SUBID:
+            cfg->param.htc_cfg.value = *axcmd->val;
+            break;
+        case MLAN_11AXCMD_TXOPRTS_SUBID:
+            (void)__memcpy(pmpriv->adapter, &cfg->param.txop_cfg.rts_thres, axcmd->val, sizeof(t_u16));
+            break;
+        case MLAN_11AXCMD_TXOMI_SUBID:
+            (void)__memcpy(pmpriv->adapter, &cfg->param.txomi_cfg, axcmd->val, sizeof(mlan_ds_11ax_txomi_cmd));
+            break;
+        case MLAN_11AXCMD_RUPOWER_SUBID:
+        {
+            wifi_rutxpwrlimit_t *ru_pwr_cfg = (wifi_rutxpwrlimit_t *)wm_wifi.cmd_resp_priv;
+            mlan_ds_11ax_chanlrupwrcft_cmd *rupwr_tlv;
+            t_u8 *pByte;
+            pByte    = axcmd->val;
+            left_len = resp->size - sizeof(HostCmd_DS_11AX_CMD_CFG) - S_DS_GEN;
+            while (left_len >= sizeof(MrvlIEtypesHeader_t))
+            {
+                rupwr_tlv = (mlan_ds_11ax_chanlrupwrcft_cmd *)pByte;
+                if (rupwr_tlv->type == TLV_TYPE_CHANNEL_RU_PWR_CONFIG)
+                {
+                    t_u8 i;
+                    ru_pwr_cfg->rupwrlimit_config[ru_pwr_cfg->num_chans].start_freq =
+                        rupwr_tlv->rupwrlimit_config.start_freq;
+                    ru_pwr_cfg->rupwrlimit_config[ru_pwr_cfg->num_chans].width = rupwr_tlv->rupwrlimit_config.width;
+                    ru_pwr_cfg->rupwrlimit_config[ru_pwr_cfg->num_chans].chan_num =
+                        rupwr_tlv->rupwrlimit_config.chan_num;
+                    for (i = 0; i < MAX_RU_COUNT; i++)
+                    {
+                        ru_pwr_cfg->rupwrlimit_config[ru_pwr_cfg->num_chans].ruPower[i] =
+                            rupwr_tlv->rupwrlimit_config.ruPower[i];
+                    }
+                    ru_pwr_cfg->num_chans++;
+                }
+                left_len -= (rupwr_tlv->len + sizeof(MrvlIEtypesHeader_t));
+                pByte += (rupwr_tlv->len + sizeof(MrvlIEtypesHeader_t));
+            }
+        }
+        break;
+        case MLAN_11AXCMD_OBSS_TOLTIME_SUBID:
+            (void)__memcpy(pmpriv->adapter, &cfg->param.toltime_cfg.tol_time, axcmd->val, sizeof(t_u32));
+            break;
+        default:
+            PRINTM(MERROR, "Unknown subcmd %x\n", axcmd->sub_id);
+            break;
+    }
+
+done:
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif /* CONFIG_11AX */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11d.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11d.c
new file mode 100644
index 0000000000..c9af0c1dc7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11d.c
@@ -0,0 +1,1625 @@
+/** @file mlan_11d.c
+ *
+ *  @brief  This file provides functions for 802.11D
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    10/21/2008: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+                Local Variables
+********************************************************/
+
+/** Region code mapping */
+typedef struct _region_code_mapping
+{
+    /** Region */
+    t_u8 region[COUNTRY_CODE_LEN];
+    /** Code */
+    t_u8 code;
+} region_code_mapping_t;
+
+/** Region code mapping table */
+static const region_code_mapping_t region_code_mapping[] = {
+    {"WW ", 0x00}, /* World Wide Safe */
+    {"US ", 0x10}, /* US FCC */
+    {"CA ", 0x20}, /* IC Canada */
+    {"SG ", 0x10}, /* Singapore */
+    {"EU ", 0x30}, /* ETSI */
+    {"AU ", 0x30}, /* Australia */
+    {"KR ", 0x30}, /* Republic Of Korea */
+    {"FR ", 0x32}, /* France */
+    {"JP ", 0xFF}, /* Japan */
+    {"CN ", 0x50}, /* China */
+};
+
+/** Default Tx power */
+#define TX_PWR_DEFAULT 10
+
+/** Universal region code */
+#define UNIVERSAL_REGION_CODE 0xff
+
+#define EU_REGION_CODE 0x30
+
+/* Following two structures define the supported channels */
+/** Channels for 802.11b/g */
+static const chan_freq_power_t channel_freq_power_UN_BG[] = {
+    {1, 2412, TX_PWR_DEFAULT},  {2, 2417, TX_PWR_DEFAULT},  {3, 2422, TX_PWR_DEFAULT},  {4, 2427, TX_PWR_DEFAULT},
+    {5, 2432, TX_PWR_DEFAULT},  {6, 2437, TX_PWR_DEFAULT},  {7, 2442, TX_PWR_DEFAULT},  {8, 2447, TX_PWR_DEFAULT},
+    {9, 2452, TX_PWR_DEFAULT},  {10, 2457, TX_PWR_DEFAULT}, {11, 2462, TX_PWR_DEFAULT}, {12, 2467, TX_PWR_DEFAULT},
+    {13, 2472, TX_PWR_DEFAULT}, {14, 2484, TX_PWR_DEFAULT}};
+
+#if CONFIG_5GHz_SUPPORT
+/** Channels for 802.11a/j */
+static chan_freq_power_t channel_freq_power_UN_AJ[] = {
+    {8, 5040, TX_PWR_DEFAULT},   {12, 5060, TX_PWR_DEFAULT},  {16, 5080, TX_PWR_DEFAULT},  {34, 5170, TX_PWR_DEFAULT},
+    {38, 5190, TX_PWR_DEFAULT},  {42, 5210, TX_PWR_DEFAULT},  {46, 5230, TX_PWR_DEFAULT},  {36, 5180, TX_PWR_DEFAULT},
+    {40, 5200, TX_PWR_DEFAULT},  {44, 5220, TX_PWR_DEFAULT},  {48, 5240, TX_PWR_DEFAULT},  {52, 5260, TX_PWR_DEFAULT},
+    {56, 5280, TX_PWR_DEFAULT},  {60, 5300, TX_PWR_DEFAULT},  {64, 5320, TX_PWR_DEFAULT},  {100, 5500, TX_PWR_DEFAULT},
+    {104, 5520, TX_PWR_DEFAULT}, {108, 5540, TX_PWR_DEFAULT}, {112, 5560, TX_PWR_DEFAULT}, {116, 5580, TX_PWR_DEFAULT},
+    {120, 5600, TX_PWR_DEFAULT}, {124, 5620, TX_PWR_DEFAULT}, {128, 5640, TX_PWR_DEFAULT}, {132, 5660, TX_PWR_DEFAULT},
+    {136, 5680, TX_PWR_DEFAULT}, {140, 5700, TX_PWR_DEFAULT}, {144, 5720, TX_PWR_DEFAULT}, {149, 5745, TX_PWR_DEFAULT},
+    {153, 5765, TX_PWR_DEFAULT}, {157, 5785, TX_PWR_DEFAULT}, {161, 5805, TX_PWR_DEFAULT},
+#if CONFIG_UNII4_BAND_SUPPORT
+    {165, 5825, TX_PWR_DEFAULT}, {169, 5845, TX_PWR_DEFAULT}, {173, 5865, TX_PWR_DEFAULT}, {177, 5885, TX_PWR_DEFAULT},
+#else
+    {165, 5825, TX_PWR_DEFAULT}
+#endif
+    /*  {240, 4920, TX_PWR_DEFAULT},
+        {244, 4940, TX_PWR_DEFAULT},
+        {248, 4960, TX_PWR_DEFAULT},
+        {252, 4980, TX_PWR_DEFAULT},
+    channels for 11J JP 10M channel gap */
+};
+#endif /* CONFIG_5GHz_SUPPORT */
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+
+/**
+ *  @brief This function converts region string to region code
+ *
+ *  @param region_string    Region string
+ *
+ *  @return                 Region code
+ */
+t_u8 region_string_2_region_code(t_u8 *region_string)
+{
+    t_u8 i;
+
+    ENTER();
+
+    for (i = 0; i < ARRAY_SIZE(region_code_mapping); i++)
+    {
+        if (memcmp(region_string, region_code_mapping[i].region, COUNTRY_CODE_LEN - 1) == 0)
+        {
+            LEAVE();
+            return region_code_mapping[i].code;
+        }
+    }
+
+    if (wlan_is_etsi_country(NULL, region_string))
+    {
+        LEAVE();
+        return EU_REGION_CODE;
+    }
+
+    /* Default is WW */
+    LEAVE();
+    return region_code_mapping[0].code;
+}
+
+/**
+ *  @brief This function converts region string to integer code
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param region       Region string
+ *  @param code         [output] Region code
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_region_2_code(pmlan_adapter pmadapter, t_u8 *region, OUT t_u8 *code)
+{
+    t_u8 i;
+    t_u8 size = sizeof(region_code_mapping) / sizeof(region_code_mapping_t);
+
+    ENTER();
+
+    if (wlan_is_etsi_country(pmadapter, region))
+    {
+        *code = EU_REGION_CODE;
+        LEAVE();
+        return MLAN_STATUS_SUCCESS;
+    }
+
+    /* Look for code in mapping table */
+    for (i = 0; i < size; i++)
+    {
+        if (!__memcmp(pmadapter, region_code_mapping[i].region, region, COUNTRY_CODE_LEN))
+        {
+            *code = region_code_mapping[i].code;
+            LEAVE();
+            return MLAN_STATUS_SUCCESS;
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_FAILURE;
+}
+
+/**
+ *  @brief This function converts country index to country string
+ *
+ *  @param code         Country index
+ *
+ *  @return             Country string
+ */
+const uint8_t *wlan_11d_country_index_2_string(int country)
+{
+    if (country < 1 || country > 9)
+    {
+        return ((const uint8_t *)region_code_mapping[0].region);
+    }
+    return ((const uint8_t *)region_code_mapping[country - 1].region);
+}
+
+/**
+ *  @brief This function converts integer code to region string
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param code         Region code
+ *
+ *  @return             Region string
+ */
+const t_u8 *wlan_11d_code_2_region(pmlan_adapter pmadapter, t_u8 code)
+{
+    t_u8 i;
+    t_u8 size = sizeof(region_code_mapping) / sizeof(region_code_mapping_t);
+
+    ENTER();
+
+    /* Look for code in mapping table */
+    for (i = 0; i < size; i++)
+    {
+        if (region_code_mapping[i].code == code)
+        {
+            LEAVE();
+            return ((const t_u8 *)region_code_mapping[i].region);
+        }
+    }
+
+    LEAVE();
+    /* Default is WW */
+    return ((const t_u8 *)region_code_mapping[0].region);
+}
+
+/**
+ *  @brief This function Checks if channel txpwr is learned from AP/IBSS
+ *
+ *  @param pmadapter            A pointer to mlan_adapter structure
+ *  @param band                 Band number
+ *  @param chan                 Channel number
+ *  @param parsed_region_chan   Pointer to parsed_region_chan_11d_t
+ *
+ *  @return                     MTRUE or MFALSE
+ */
+static t_u8 wlan_11d_channel_known(pmlan_adapter pmadapter,
+                                   t_u16 band,
+                                   t_u8 chan,
+                                   parsed_region_chan_11d_t *parsed_region_chan)
+{
+    chan_power_11d_t *pchan_pwr = parsed_region_chan->chan_pwr;
+    t_u8 no_of_chan             = parsed_region_chan->no_of_chan;
+    t_u8 i                      = 0;
+    t_u8 ret                    = MFALSE;
+    mlan_private *pmpriv;
+
+    ENTER();
+
+    HEXDUMP("11D: parsed_region_chan", (t_u8 *)pchan_pwr, sizeof(chan_power_11d_t) * no_of_chan);
+
+    /* Search channel */
+    for (i = 0; i < no_of_chan; i++)
+    {
+        if (chan == pchan_pwr[i].chan && band == pchan_pwr[i].band)
+        {
+            PRINTM(MINFO, "11D: Found channel:%d (band:%d)\n", chan, band);
+            ret = MTRUE;
+
+            if ((band & BAND_A) != 0U)
+            {
+                /* If chan is a DFS channel, we need to see an AP on it */
+                pmpriv = wlan_get_priv(pmadapter, MLAN_BSS_ROLE_STA);
+                if (pmpriv != MNULL && wlan_11h_radar_detect_required(pmpriv, chan))
+                {
+                    PRINTM(MINFO, "11H: DFS channel %d, and ap_seen=%d\n", chan, pchan_pwr[i].ap_seen);
+                    ret = pchan_pwr[i].ap_seen;
+                }
+            }
+
+            LEAVE();
+            return ret;
+        }
+    }
+
+    PRINTM(MINFO, "11D: Could not find channel:%d (band:%d)\n", chan, band);
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function generates parsed_region_chan from Domain Info
+ *           learned from AP/IBSS
+ *
+ *  @param pmadapter            Pointer to mlan_adapter structure
+ *  @param region_chan          Pointer to region_chan_t
+ *  @param parsed_region_chan   Pointer to parsed_region_chan_11d_t
+ *
+ *  @return                     N/A
+ */
+static t_void wlan_11d_generate_parsed_region_chan(pmlan_adapter pmadapter,
+                                                   region_chan_t *region_chan,
+                                                   parsed_region_chan_11d_t *parsed_region_chan)
+{
+    const chan_freq_power_t *cfp;
+    t_u8 i;
+
+    ENTER();
+
+    /* Region channel must be provided */
+    if (region_chan == MNULL)
+    {
+        PRINTM(MWARN, "11D: region_chan is MNULL\n");
+        LEAVE();
+        return;
+    }
+
+    /* Get channel-frequency-power trio */
+    cfp = region_chan->pcfp;
+    if (cfp == MNULL)
+    {
+        PRINTM(MWARN, "11D: cfp equal MNULL\n");
+        LEAVE();
+        return;
+    }
+
+    /* Set channel, band and power */
+    for (i = 0; i < region_chan->num_cfp; i++)
+    {
+        parsed_region_chan->chan_pwr[i].chan = (t_u8)cfp->channel;
+        parsed_region_chan->chan_pwr[i].band = (t_u8)region_chan->band;
+        parsed_region_chan->chan_pwr[i].pwr  = (t_u8)cfp->max_tx_power;
+        PRINTM(MINFO, "11D: Chan[%d] Band[%d] Pwr[%d]\n", parsed_region_chan->chan_pwr[i].chan,
+               parsed_region_chan->chan_pwr[i].band, parsed_region_chan->chan_pwr[i].pwr);
+        cfp++;
+    }
+    parsed_region_chan->no_of_chan = region_chan->num_cfp;
+
+    PRINTM(MINFO, "11D: no_of_chan[%d]\n", parsed_region_chan->no_of_chan);
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function generates domain_info from parsed_region_chan
+ *
+ *  @param pmadapter            Pointer to mlan_adapter structure
+ *  @param parsed_region_chan   Pointer to parsed_region_chan_11d_t
+ *
+ *  @return                     MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_11d_generate_domain_info(pmlan_adapter pmadapter, parsed_region_chan_11d_t *parsed_region_chan)
+{
+    t_u8 no_of_sub_band    = 0;
+    t_u8 no_of_chan        = parsed_region_chan->no_of_chan;
+    t_u8 no_of_parsed_chan = 0;
+    t_u8 first_chan = 0, next_chan = 0, max_pwr = 0;
+    t_u8 i, flag = MFALSE;
+    wlan_802_11d_domain_reg_t *domain_info = &pmadapter->domain_reg;
+
+    ENTER();
+
+    /* Should be only place that clear domain_reg (besides init) */
+    (void)__memset(pmadapter, domain_info, 0, sizeof(wlan_802_11d_domain_reg_t));
+
+    /* Set country code */
+    (void)__memcpy(pmadapter, domain_info->country_code,
+                   wlan_11d_code_2_region(pmadapter, (t_u8)pmadapter->region_code), COUNTRY_CODE_LEN);
+
+    PRINTM(MINFO, "11D: Number of channel = %d\n", no_of_chan);
+    HEXDUMP("11D: parsed_region_chan", (t_u8 *)parsed_region_chan, sizeof(parsed_region_chan_11d_t));
+
+    /* Set channel and power */
+    for (i = 0; i < no_of_chan; i++)
+    {
+        if (!flag)
+        {
+            flag      = MTRUE;
+            next_chan = first_chan = parsed_region_chan->chan_pwr[i].chan;
+            max_pwr                = parsed_region_chan->chan_pwr[i].pwr;
+            no_of_parsed_chan      = 1;
+            continue;
+        }
+
+        if (parsed_region_chan->chan_pwr[i].chan == next_chan + 1U && parsed_region_chan->chan_pwr[i].pwr == max_pwr)
+        {
+            next_chan++;
+            no_of_parsed_chan++;
+        }
+        else
+        {
+            domain_info->sub_band[no_of_sub_band].first_chan = first_chan;
+            domain_info->sub_band[no_of_sub_band].no_of_chan = no_of_parsed_chan;
+            domain_info->sub_band[no_of_sub_band].max_tx_pwr = max_pwr;
+            no_of_sub_band++;
+            no_of_parsed_chan = 1;
+            next_chan = first_chan = parsed_region_chan->chan_pwr[i].chan;
+            max_pwr                = parsed_region_chan->chan_pwr[i].pwr;
+        }
+    }
+
+    if (flag != 0U)
+    {
+        domain_info->sub_band[no_of_sub_band].first_chan = first_chan;
+        domain_info->sub_band[no_of_sub_band].no_of_chan = no_of_parsed_chan;
+        domain_info->sub_band[no_of_sub_band].max_tx_pwr = max_pwr;
+        no_of_sub_band++;
+    }
+    domain_info->no_of_sub_band = no_of_sub_band;
+
+    PRINTM(MINFO, "11D: Number of sub-band =0x%x\n", domain_info->no_of_sub_band);
+    HEXDUMP("11D: domain_info", (t_u8 *)domain_info,
+            COUNTRY_CODE_LEN + 1 + sizeof(IEEEtypes_SubbandSet_t) * no_of_sub_band);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function updates the channel power table with the channel
+ *            present in BSSDescriptor.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc    A pointer to BSSDescriptor_t
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_11d_update_chan_pwr_table(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc)
+{
+    mlan_adapter *pmadapter                      = pmpriv->adapter;
+    parsed_region_chan_11d_t *parsed_region_chan = &pmadapter->parsed_region_chan;
+    t_u16 i;
+    t_u8 tx_power = 0;
+    t_u8 chan;
+
+    ENTER();
+
+    chan = pbss_desc->phy_param_set.ds_param_set.current_chan;
+
+    tx_power = wlan_get_txpwr_of_chan_from_cfp(pmpriv, chan);
+
+    if (!tx_power)
+    {
+        PRINTM(MMSG, "11D: Invalid channel\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    /* Check whether the channel already exists in channel power table of
+       parsed region */
+    for (i = 0; ((i < parsed_region_chan->no_of_chan) && (i < MAX_NO_OF_CHAN)); i++)
+    {
+        if (parsed_region_chan->chan_pwr[i].chan == chan && parsed_region_chan->chan_pwr[i].band == pbss_desc->bss_band)
+        {
+            /* Channel already exists, use minimum of existing and tx_power */
+            parsed_region_chan->chan_pwr[i].pwr     = MIN(parsed_region_chan->chan_pwr[i].pwr, tx_power);
+            parsed_region_chan->chan_pwr[i].ap_seen = MTRUE;
+            break;
+        }
+    }
+
+    if (i == parsed_region_chan->no_of_chan && i < MAX_NO_OF_CHAN)
+    {
+        /* Channel not found. Update the channel in the channel-power table */
+        parsed_region_chan->chan_pwr[i].chan    = chan;
+        parsed_region_chan->chan_pwr[i].band    = (t_u8)pbss_desc->bss_band;
+        parsed_region_chan->chan_pwr[i].pwr     = tx_power;
+        parsed_region_chan->chan_pwr[i].ap_seen = MTRUE;
+        parsed_region_chan->no_of_chan++;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function finds the no_of_chan-th chan after the first_chan
+ *
+ *  @param pmadapter  A pointer to mlan_adapter structure
+ *  @param band       Band
+ *  @param first_chan First channel number
+ *  @param no_of_chan Number of channels
+ *  @param chan       Pointer to the returned no_of_chan-th chan number
+ *
+ *  @return           MTRUE or MFALSE
+ */
+static t_u8 wlan_11d_get_chan(pmlan_adapter pmadapter, t_u16 band, t_u8 first_chan, t_u8 no_of_chan, t_u8 *chan)
+{
+    const chan_freq_power_t *cfp = MNULL;
+    t_u8 i;
+    t_u8 cfp_no = 0;
+
+    ENTER();
+    if ((band & (BAND_B | BAND_G | BAND_GN)) != 0U)
+    {
+        cfp    = (const chan_freq_power_t *)channel_freq_power_UN_BG;
+        cfp_no = sizeof(channel_freq_power_UN_BG) / sizeof(chan_freq_power_t);
+    }
+#if CONFIG_5GHz_SUPPORT
+    else if ((band & (BAND_A | BAND_AN)) != 0U)
+    {
+        cfp    = channel_freq_power_UN_AJ;
+        cfp_no = sizeof(channel_freq_power_UN_AJ) / sizeof(chan_freq_power_t);
+    }
+#endif /* CONFIG_5GHz_SUPPORT */
+    else
+    {
+        PRINTM(MERROR, "11D: Wrong Band[%d]\n", band);
+        LEAVE();
+        return MFALSE;
+    }
+    /* Locate the first_chan */
+    for (i = 0; i < cfp_no; i++)
+    {
+        if ((cfp + i)->channel == first_chan)
+        {
+            PRINTM(MINFO, "11D: first_chan found\n");
+            break;
+        }
+    }
+
+    if (i < cfp_no)
+    {
+        /* Check if beyond the boundary */
+        if (i + no_of_chan < cfp_no)
+        {
+            /* Get first_chan + no_of_chan */
+            *chan = (t_u8)(cfp + i + no_of_chan)->channel;
+            LEAVE();
+            return MTRUE;
+        }
+    }
+
+    LEAVE();
+    return MFALSE;
+}
+
+/**
+ *  @brief This function processes the country info present in BSSDescriptor.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc     A pointer to BSSDescriptor_t
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_11d_process_country_info(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    parsed_region_chan_11d_t region_chan;
+    parsed_region_chan_11d_t *parsed_region_chan = &pmadapter->parsed_region_chan;
+    t_u16 i, j, num_chan_added = 0;
+
+    ENTER();
+
+    (void)__memset(pmadapter, &region_chan, 0, sizeof(parsed_region_chan_11d_t));
+
+    /* Parse 11D country info */
+    if (wlan_11d_parse_domain_info(pmadapter, &pbss_desc->country_info, pbss_desc->bss_band, &region_chan) !=
+        MLAN_STATUS_SUCCESS)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    if (parsed_region_chan->no_of_chan != 0U)
+    {
+        /*
+         * Check if the channel number already exists in the
+         * chan-power table of parsed_region_chan
+         */
+        for (i = 0; (i < region_chan.no_of_chan && i < MAX_NO_OF_CHAN); i++)
+        {
+            for (j = 0; (j < parsed_region_chan->no_of_chan && j < MAX_NO_OF_CHAN); j++)
+            {
+                /*
+                 * Channel already exists, update the tx power with new tx
+                 * power, since country IE is valid here.
+                 */
+                if (region_chan.chan_pwr[i].chan == parsed_region_chan->chan_pwr[j].chan &&
+                    region_chan.chan_pwr[i].band == parsed_region_chan->chan_pwr[j].band)
+                {
+                    parsed_region_chan->chan_pwr[j].pwr = region_chan.chan_pwr[i].pwr;
+                    break;
+                }
+            }
+
+            if (j == parsed_region_chan->no_of_chan && j < MAX_NO_OF_CHAN)
+            {
+                if (parsed_region_chan->no_of_chan + num_chan_added >= MAX_NO_OF_CHAN)
+                {
+                    break;
+                }
+                /*
+                 * Channel does not exist in the channel power table,
+                 * update this new chan and tx_power to the channel power table
+                 */
+                parsed_region_chan->chan_pwr[parsed_region_chan->no_of_chan + num_chan_added].chan =
+                    region_chan.chan_pwr[i].chan;
+                parsed_region_chan->chan_pwr[parsed_region_chan->no_of_chan + num_chan_added].band =
+                    region_chan.chan_pwr[i].band;
+                parsed_region_chan->chan_pwr[parsed_region_chan->no_of_chan + num_chan_added].pwr =
+                    region_chan.chan_pwr[i].pwr;
+                parsed_region_chan->chan_pwr[parsed_region_chan->no_of_chan + num_chan_added].ap_seen = MFALSE;
+                num_chan_added++;
+            }
+        }
+        parsed_region_chan->no_of_chan += (t_u8)num_chan_added;
+        if (parsed_region_chan->no_of_chan > MAX_NO_OF_CHAN)
+        {
+            parsed_region_chan->no_of_chan = MAX_NO_OF_CHAN;
+        }
+    }
+    else
+    {
+        /* Parsed region is empty, copy the first one */
+        (void)__memcpy(pmadapter, parsed_region_chan, &region_chan, sizeof(parsed_region_chan_11d_t));
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This helper function copies chan_power_11d_t element
+ *
+ *  @param chan_dst   Pointer to destination of chan_power
+ *  @param chan_src   Pointer to source of chan_power
+ *
+ *  @return           N/A
+ */
+static t_void wlan_11d_copy_chan_power(chan_power_11d_t *chan_dst, chan_power_11d_t *chan_src)
+{
+    ENTER();
+
+    chan_dst->chan    = chan_src->chan;
+    chan_dst->band    = chan_src->band;
+    chan_dst->pwr     = chan_src->pwr;
+    chan_dst->ap_seen = chan_src->ap_seen;
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function sorts parsed_region_chan in ascending
+ *  channel number.
+ *
+ *  @param parsed_region_chan   Pointer to parsed_region_chan_11d_t
+ *
+ *  @return                     N/A
+ */
+static t_void wlan_11d_sort_parsed_region_chan(parsed_region_chan_11d_t *parsed_region_chan)
+{
+    t_u8 i, j;
+    chan_power_11d_t temp;
+    chan_power_11d_t *pchan_power = parsed_region_chan->chan_pwr;
+
+    ENTER();
+
+    PRINTM(MINFO, "11D: Number of channel = %d\n", parsed_region_chan->no_of_chan);
+
+    // Use insertion sort method
+    for (i = 1; i < parsed_region_chan->no_of_chan; i++)
+    {
+        wlan_11d_copy_chan_power(&temp, pchan_power + i);
+        for (j = i; j > 0 && (pchan_power + j - 1)->chan > temp.chan; j--)
+        {
+            wlan_11d_copy_chan_power(pchan_power + j, pchan_power + j - 1);
+        }
+        wlan_11d_copy_chan_power(pchan_power + j, &temp);
+    }
+
+    HEXDUMP("11D: parsed_region_chan", (t_u8 *)parsed_region_chan, sizeof(parsed_region_chan_11d_t));
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function sends domain info to FW
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pioctl_buf   A pointer to MLAN IOCTL Request buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_11d_send_domain_info(mlan_private *pmpriv, t_void *pioctl_buf, t_bool is_op_special_set)
+{
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    /* Send cmd to FW to set domain info */
+    if (is_op_special_set)
+    {
+        ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_802_11D_DOMAIN_INFO, HostCmd_ACT_SPC_SET, 0, (t_void *)pioctl_buf,
+                               MNULL);
+    }
+    else
+    {
+        ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_802_11D_DOMAIN_INFO, HostCmd_ACT_GEN_SET, 0, (t_void *)pioctl_buf,
+                               MNULL);
+    }
+    if (ret != MLAN_STATUS_SUCCESS)
+    {
+        PRINTM(MERROR, "11D: Failed to download domain Info\n");
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function overwrites domain_info
+ *
+ *  @param pmadapter        Pointer to mlan_adapter structure
+ *  @param band             Intended operating band
+ *  @param country_code     Intended country code
+ *  @param num_sub_band     Count of tuples in list below
+ *  @param sub_band_list    List of sub_band tuples
+ *
+ *  @return                 MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_11d_set_domain_info(mlan_private *pmpriv,
+                                     t_u16 band,
+                                     const t_u8 country_code[COUNTRY_CODE_LEN],
+                                     t_u8 num_sub_band,
+                                     IEEEtypes_SubbandSet_t *sub_band_list)
+{
+    mlan_adapter *pmadapter            = pmpriv->adapter;
+    wlan_802_11d_domain_reg_t *pdomain = &pmadapter->domain_reg;
+    mlan_status ret                    = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    (void)__memset(pmadapter, pdomain, 0, sizeof(wlan_802_11d_domain_reg_t));
+    (void)__memcpy(pmadapter, pdomain->country_code, country_code, COUNTRY_CODE_LEN);
+    pdomain->band           = band;
+    pdomain->no_of_sub_band = num_sub_band;
+    (void)__memcpy(pmadapter, pdomain->sub_band, sub_band_list,
+                   MIN(MRVDRV_MAX_SUBBAND_802_11D, num_sub_band) * sizeof(IEEEtypes_SubbandSet_t));
+
+    LEAVE();
+    return ret;
+}
+
+/********************************************************
+                Global functions
+********************************************************/
+
+/**
+ *  @brief This function gets if priv is a station (STA)
+ *
+ *  @param pmpriv       Pointer to mlan_private structure
+ *
+ *  @return             MTRUE or MFALSE
+ */
+t_bool wlan_is_station(mlan_private *pmpriv)
+{
+    ENTER();
+    LEAVE();
+    return (GET_BSS_ROLE(pmpriv) == MLAN_BSS_ROLE_STA) ? MTRUE : MFALSE;
+}
+
+/**
+ *  @brief This function gets if 11D is enabled
+ *
+ *  @param pmpriv       Pointer to mlan_private structure
+ *
+ *  @return             MTRUE or MFALSE
+ */
+t_bool wlan_11d_support_is_enabled(mlan_private *pmpriv)
+{
+    ENTER();
+    LEAVE();
+    return (pmpriv->state_11d.user_enable_11d_support == ENABLE_11D) ? MTRUE : MFALSE;
+}
+
+/**
+ *  @brief This function gets if 11D is enabled
+ *
+ *  @param pmpriv       Pointer to mlan_private structure
+ *
+ *  @return             MTRUE or MFALSE
+ */
+t_bool wlan_11d_is_enabled(mlan_private *pmpriv)
+{
+    ENTER();
+    LEAVE();
+    return (pmpriv->state_11d.enable_11d == ENABLE_11D) ? MTRUE : MFALSE;
+}
+
+static wlan_11d_fn_t wlan_11d_fn = {
+    .wlan_11d_prepare_dnld_domain_info_cmd_p = wlan_11d_prepare_dnld_domain_info_cmd,
+    .wlan_11d_create_dnld_countryinfo_p      = wlan_11d_create_dnld_countryinfo,
+    .wlan_11d_parse_dnld_countryinfo_p       = wlan_11d_parse_dnld_countryinfo,
+};
+
+static void *wlan_11d_enable_support = (wlan_11d_fn_t *)&wlan_11d_fn;
+
+/**
+ *  @brief This function sets 11D support
+ *
+ *  @param pmpriv       Pointer to mlan_private structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+t_u16 wlan_enable_11d_support(mlan_private *pmpriv)
+{
+    ENTER();
+    LEAVE();
+
+    pmpriv->state_11d.user_enable_11d_support = ENABLE_11D;
+
+    pmpriv->support_11d = wlan_11d_enable_support;
+
+    return (t_u16)MLAN_STATUS_SUCCESS;
+}
+
+static wlan_11d_apis_t wlan_11d_apis = {
+    .wlan_11d_cfg_ioctl_p              = wlan_11d_cfg_ioctl,
+    .wlan_11d_cfg_domain_info_p        = wlan_11d_cfg_domain_info,
+    .wlan_cmd_802_11d_domain_info_p    = wlan_cmd_802_11d_domain_info,
+    .wlan_11d_handle_uap_domain_info_p = wlan_11d_handle_uap_domain_info,
+};
+
+static void *wlan_11d_support_apis = (wlan_11d_apis_t *)&wlan_11d_apis;
+
+/**
+ *  @brief This function enables 11D driver APIs
+ *
+ *  @param pmpriv       Pointer to mlan_private structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+t_u16 wlan_11d_support_APIs(mlan_private *pmpriv)
+{
+    ENTER();
+    LEAVE();
+
+    pmpriv->support_11d_APIs = wlan_11d_support_apis;
+
+    return (t_u16)MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Initialize interface variable for 11D
+ *
+ *  @param pmpriv       Pointer to mlan_private structure
+ *
+ *  @return             N/A
+ */
+t_void wlan_11d_priv_init(mlan_private *pmpriv)
+{
+    wlan_802_11d_state_t *state = &pmpriv->state_11d;
+
+    ENTER();
+
+    /* Start in disabled mode */
+    state->enable_11d = DISABLE_11D;
+    if (!pmpriv->adapter->init_para.cfg_11d)
+    {
+        state->user_enable_11d = DEFAULT_11D_STATE;
+    }
+    else
+    {
+        state->user_enable_11d =
+            (pmpriv->adapter->init_para.cfg_11d == MLAN_INIT_PARA_DISABLED) ? DISABLE_11D : ENABLE_11D;
+    }
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief Initialize device variable for 11D
+ *
+ *  @param pmadapter    Pointer to mlan_adapter structure
+ *
+ *  @return             N/A
+ */
+t_void wlan_11d_init(mlan_adapter *pmadapter)
+{
+    ENTER();
+
+    (void)__memset(pmadapter, &(pmadapter->parsed_region_chan), 0, sizeof(parsed_region_chan_11d_t));
+    (void)__memset(pmadapter, &(pmadapter->universal_channel), 0, sizeof(region_chan_t));
+    (void)__memset(pmadapter, &(pmadapter->domain_reg), 0, sizeof(wlan_802_11d_domain_reg_t));
+
+    LEAVE();
+    return;
+}
+
+
+/**
+ *  @brief This function implements command CMD_802_11D_DOMAIN_INFO
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pcmd         A pointer to HostCmd_DS_COMMAND structure of
+ *                        command buffer
+ *  @param cmd_action   Command action
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_802_11d_domain_info(mlan_private *pmpriv, HostCmd_DS_COMMAND *pcmd, t_u16 cmd_action)
+{
+    mlan_adapter *pmadapter                      = pmpriv->adapter;
+    HostCmd_DS_802_11D_DOMAIN_INFO *pdomain_info = &pcmd->params.domain_info;
+    MrvlIEtypes_DomainParamSet_t *domain         = &pdomain_info->domain;
+    t_u8 no_of_sub_band                          = pmadapter->domain_reg.no_of_sub_band;
+
+    ENTER();
+
+    PRINTM(MINFO, "11D: number of sub-band=0x%x\n", no_of_sub_band);
+
+    pcmd->command        = wlan_cpu_to_le16(HostCmd_CMD_802_11D_DOMAIN_INFO);
+    pdomain_info->action = wlan_cpu_to_le16(cmd_action);
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        /* Dump domain info */
+        pcmd->size = wlan_cpu_to_le16(sizeof(pdomain_info->action) + S_DS_GEN);
+        HEXDUMP("11D: 802_11D_DOMAIN_INFO", (t_u8 *)pcmd, wlan_le16_to_cpu(pcmd->size));
+        LEAVE();
+        return MLAN_STATUS_SUCCESS;
+    }
+
+    /* Set domain info fields */
+    domain->header.type = wlan_cpu_to_le16(TLV_TYPE_DOMAIN);
+    (void)__memcpy(pmadapter, domain->country_code, pmadapter->domain_reg.country_code, sizeof(domain->country_code));
+
+    domain->header.len = (t_u16)(((no_of_sub_band * sizeof(IEEEtypes_SubbandSet_t)) + sizeof(domain->country_code)));
+
+    if (no_of_sub_band != 0U)
+    {
+        (void)__memcpy(pmadapter, domain->sub_band, pmadapter->domain_reg.sub_band,
+                       MIN(MRVDRV_MAX_SUBBAND_802_11D, no_of_sub_band) * sizeof(IEEEtypes_SubbandSet_t));
+
+        pcmd->size = wlan_cpu_to_le16(sizeof(pdomain_info->action) + domain->header.len + sizeof(MrvlIEtypesHeader_t) +
+                                      S_DS_GEN);
+    }
+    else
+    {
+        pcmd->size = wlan_cpu_to_le16(sizeof(pdomain_info->action) + S_DS_GEN);
+    }
+    domain->header.len = wlan_cpu_to_le16(domain->header.len);
+
+    HEXDUMP("11D: 802_11D_DOMAIN_INFO", (t_u8 *)pcmd, wlan_le16_to_cpu(pcmd->size));
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+
+/** Region code mapping */
+typedef struct _region_code_t
+{
+    /** Region */
+    t_u8 region[COUNTRY_CODE_LEN];
+} region_code_t;
+
+/**
+ *  @brief This function check cfg80211 special region code.
+ *
+ *  @param region_string         Region string
+ *
+ *  @return     MTRUE/MFALSE
+ */
+t_u8 is_special_region_code(t_u8 *region_string)
+{
+    t_u8 i;
+    region_code_t special_region_code[] = {{"00 "}, {"99 "}, {"98 "}, {"97 "}};
+
+    for (i = 0; i < COUNTRY_CODE_LEN && region_string[i]; i++)
+        region_string[i] = toupper(region_string[i]);
+
+    for (i = 0; i < ARRAY_SIZE(special_region_code); i++)
+    {
+        if (!memcmp(region_string, special_region_code[i].region, COUNTRY_CODE_LEN))
+        {
+            PRINTM(MINFO, "special region code=%s\n", region_string);
+            return MTRUE;
+        }
+    }
+    return MFALSE;
+}
+
+/**
+ *  @brief This function parses country information for region channel
+ *
+ *  @param pmadapter            Pointer to mlan_adapter structure
+ *  @param country_info         Country information
+ *  @param band                 Chan band
+ *  @param parsed_region_chan   Pointer to parsed_region_chan_11d_t
+ *
+ *  @return                     MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_parse_domain_info(pmlan_adapter pmadapter,
+                                       IEEEtypes_CountryInfoFullSet_t *country_info,
+                                       t_u16 band,
+                                       parsed_region_chan_11d_t *parsed_region_chan)
+{
+    t_u8 no_of_sub_band, no_of_chan;
+    t_u8 last_chan, first_chan, cur_chan = 0;
+    t_u8 idx = 0;
+    t_u8 j, i;
+
+    ENTER();
+
+    /*
+     * Validation Rules:
+     *    1. Valid Region Code
+     *    2. First Chan increment
+     *    3. Channel range no overlap
+     *    4. Channel is valid?
+     *    5. Channel is supported by Region?
+     *    6. Others
+     */
+
+    HEXDUMP("country_info", (t_u8 *)country_info, 30);
+    /* Step 1: Check region_code */
+    if (!(*(country_info->country_code)) || (country_info->len <= COUNTRY_CODE_LEN))
+    {
+        /* No region info or wrong region info: treat as no 11D info */
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    no_of_sub_band = (t_u8)((country_info->len - COUNTRY_CODE_LEN) / sizeof(IEEEtypes_SubbandSet_t));
+
+    last_chan = 0;
+    for (j = 0; j < no_of_sub_band; j++)
+    {
+        if (country_info->sub_band[j].first_chan <= last_chan)
+        {
+            /* Step2&3: Check First Chan Num increment and no overlap */
+            PRINTM(MINFO, "11D: Chan[%d>%d] Overlap\n", country_info->sub_band[j].first_chan, last_chan);
+            continue;
+        }
+
+        first_chan = country_info->sub_band[j].first_chan;
+        no_of_chan = country_info->sub_band[j].no_of_chan;
+
+        i = 0;
+        while (idx < MAX_NO_OF_CHAN && i < no_of_chan)
+        {
+            /* Step 4 : Channel is supported? */
+            if (wlan_11d_get_chan(pmadapter, band, first_chan, i, &cur_chan) == MFALSE)
+            {
+                /* Chan is not found in UN table */
+                PRINTM(MWARN, "11D: channel is not supported: %d\n", i);
+                break;
+            }
+
+            last_chan = cur_chan;
+
+            /* Step 5: We don't need to check if cur_chan is supported by mrvl
+               in region */
+            parsed_region_chan->chan_pwr[idx].chan = cur_chan;
+            parsed_region_chan->chan_pwr[idx].band = (t_u8)band;
+            parsed_region_chan->chan_pwr[idx].pwr  = country_info->sub_band[j].max_tx_pwr;
+            idx++;
+            i++;
+        }
+
+        /* Step 6: Add other checking if any */
+    }
+
+    parsed_region_chan->no_of_chan = idx;
+
+    PRINTM(MINFO, "11D: number of channel=0x%x\n", parsed_region_chan->no_of_chan);
+    HEXDUMP("11D: parsed_region_chan", (t_u8 *)parsed_region_chan->chan_pwr, sizeof(chan_power_11d_t) * idx);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function converts channel to frequency
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param chan         Channel number
+ *  @param band         Band
+ *
+ *  @return             Channel frequency
+ */
+t_u32 wlan_11d_chan_2_freq(pmlan_adapter pmadapter, t_u8 chan, t_u16 band)
+{
+    const chan_freq_power_t *cf;
+    t_u16 cnt;
+    t_u16 i;
+    t_u32 freq = 0;
+
+    ENTER();
+
+#if CONFIG_5GHz_SUPPORT
+    /* Get channel-frequency-power trios */
+    if ((band & (BAND_A | BAND_AN)) != 0)
+    {
+        cf  = channel_freq_power_UN_AJ;
+        cnt = sizeof(channel_freq_power_UN_AJ) / sizeof(chan_freq_power_t);
+    }
+    else
+    {
+#endif /* CONFIG_5GHz_SUPPORT */
+        cf  = (const chan_freq_power_t *)channel_freq_power_UN_BG;
+        cnt = sizeof(channel_freq_power_UN_BG) / sizeof(chan_freq_power_t);
+#if CONFIG_5GHz_SUPPORT
+    }
+#endif /* CONFIG_5GHz_SUPPORT */
+
+    /* Locate channel and return corresponding frequency */
+    for (i = 0; i < cnt; i++)
+    {
+        if (chan == cf[i].channel)
+        {
+            freq = cf[i].freq;
+        }
+    }
+
+    LEAVE();
+    return freq;
+}
+
+/**
+ *  @brief This function setups scan channels
+ *
+ *  @param pmpriv       Pointer to mlan_private structure
+ *  @param band         Band
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_11d_set_universaltable(mlan_private *pmpriv, t_u16 band)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u16 size              = (t_u16)sizeof(chan_freq_power_t);
+    t_u16 i                 = 0;
+
+    ENTER();
+
+    (void)__memset(pmadapter, pmadapter->universal_channel, 0, sizeof(pmadapter->universal_channel));
+
+    if ((band & (BAND_B | BAND_G | BAND_GN)) != 0U)
+    /* If band B, G or N */
+    {
+        /* Set channel-frequency-power */
+        pmadapter->universal_channel[i].num_cfp = (t_u8)(sizeof(channel_freq_power_UN_BG) / size);
+        PRINTM(MINFO, "11D: BG-band num_cfp=%d\n", pmadapter->universal_channel[i].num_cfp);
+
+        pmadapter->universal_channel[i].pcfp  = (const chan_freq_power_t *)channel_freq_power_UN_BG;
+        pmadapter->universal_channel[i].valid = MTRUE;
+
+        /* Set region code */
+        pmadapter->universal_channel[i].region = UNIVERSAL_REGION_CODE;
+
+        /* Set band */
+        if ((band & BAND_GN) != 0U)
+        {
+            pmadapter->universal_channel[i].band = BAND_G;
+        }
+        else
+        {
+            pmadapter->universal_channel[i].band = (band & BAND_G) ? BAND_G : BAND_B;
+        }
+        i++;
+    }
+
+#if CONFIG_5GHz_SUPPORT
+#if CONFIG_11AC
+    if ((band & (BAND_A | BAND_AN | BAND_AAC)) != 0U)
+    {
+#else
+    if ((band & (BAND_A | BAND_AN)) != 0U)
+    {
+#endif
+        /* If band A */
+
+        /* Set channel-frequency-power */
+        pmadapter->universal_channel[i].num_cfp = (t_u8)(sizeof(channel_freq_power_UN_AJ) / size);
+        PRINTM(MINFO, "11D: AJ-band num_cfp=%d\n", pmadapter->universal_channel[i].num_cfp);
+
+        pmadapter->universal_channel[i].pcfp = channel_freq_power_UN_AJ;
+
+        pmadapter->universal_channel[i].valid = MTRUE;
+
+        /* Set region code */
+        pmadapter->universal_channel[i].region = UNIVERSAL_REGION_CODE;
+
+        /* Set band */
+        pmadapter->universal_channel[i].band = BAND_A;
+    }
+#endif /* CONFIG_5GHz_SUPPORT */
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function calculates the scan type for channels
+ *
+ *  @param pmadapter            A pointer to mlan_adapter structure
+ *  @param band                 Band number
+ *  @param chan                 Chan number
+ *  @param parsed_region_chan   Pointer to parsed_region_chan_11d_t
+ *
+ *  @return                     PASSIVE if chan is unknown; ACTIVE if chan is known
+ */
+mlan_scan_type wlan_11d_get_scan_type(mlan_private *pmpriv,
+                                      t_u16 band,
+                                      t_u8 chan,
+                                      parsed_region_chan_11d_t *parsed_region_chan)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+
+    mlan_scan_type scan_type = MLAN_SCAN_TYPE_PASSIVE;
+
+    ENTER();
+
+    if (wlan_11d_channel_known(pmadapter, band, chan, parsed_region_chan) != 0U)
+    {
+        /* Channel found */
+        PRINTM(MINFO, "11D: Channel found and doing Active Scan\n");
+        scan_type = MLAN_SCAN_TYPE_ACTIVE;
+    }
+    else
+    {
+        PRINTM(MINFO, "11D: Channel not found and doing Passive Scan\n");
+    }
+
+    LEAVE();
+    return scan_type;
+}
+
+/**
+ *  @brief This function clears the parsed region table, if 11D is enabled
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_clear_parsedtable(mlan_private *pmpriv)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    if (wlan_11d_is_enabled(pmpriv))
+    {
+        (void)__memset(pmadapter, &(pmadapter->parsed_region_chan), 0, sizeof(parsed_region_chan_11d_t));
+    }
+    else
+    {
+        ret = MLAN_STATUS_FAILURE;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function generates 11D info from user specified regioncode
+ *         and download to FW
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param band         Band to create
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_create_dnld_countryinfo(mlan_private *pmpriv, t_u16 band)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    region_chan_t *region_chan;
+    parsed_region_chan_11d_t parsed_region_chan;
+    t_u8 j;
+
+    ENTER();
+
+    /* Only valid if 11D is enabled */
+    if (wlan_11d_is_enabled(pmpriv))
+    {
+        PRINTM(MINFO, "11D: Band[%d]\n", band);
+
+        /* Update parsed_region_chan; download domain info to FW */
+
+        /* Find region channel */
+        for (j = 0; j < MAX_REGION_CHANNEL_NUM; j++)
+        {
+            bool continue_loop = MFALSE;
+            region_chan        = &pmadapter->region_channel[j];
+
+            PRINTM(MINFO, "11D: [%d] region_chan->Band[%d]\n", j, region_chan->band);
+
+            if (region_chan == MNULL || !region_chan->valid || region_chan->pcfp == MNULL)
+            {
+                continue;
+            }
+            switch (region_chan->band)
+            {
+#if CONFIG_5GHz_SUPPORT
+                case BAND_A:
+                    switch (band)
+                    {
+                        case BAND_A:
+                        case BAND_AN:
+                        case BAND_A | BAND_AN:
+#if CONFIG_11AC
+                        case BAND_A | BAND_AN | BAND_AAC:
+#endif
+#if CONFIG_11AX
+                        case BAND_A | BAND_AN | BAND_AAC | BAND_AAX:
+#endif
+                            break;
+                        default:
+                            continue_loop = MTRUE;
+                            break;
+                    }
+                    break;
+#endif /* CONFIG_5GHz_SUPPORT */
+                case BAND_B:
+                case BAND_G:
+                    switch (band)
+                    {
+                        case BAND_B:
+                        case BAND_G:
+                        case BAND_G | BAND_B:
+                        case BAND_GN:
+                        case BAND_G | BAND_GN:
+                        case BAND_B | BAND_G | BAND_GN:
+#if CONFIG_11AC
+                        case BAND_B | BAND_G | BAND_GN | BAND_GAC:
+#endif
+#if CONFIG_11AX
+                        case BAND_B | BAND_G | BAND_GN | BAND_GAC | BAND_GAX:
+#endif
+                            break;
+                        default:
+                            continue_loop = MTRUE;
+                            break;
+                    }
+                    break;
+                default:
+                    continue_loop = MTRUE;
+                    break;
+            }
+
+            if (continue_loop == MTRUE)
+            {
+                continue;
+            }
+            else
+            {
+                break;
+            }
+        }
+
+        /* Check if region channel found */
+        if (j >= MAX_REGION_CHANNEL_NUM)
+        {
+            PRINTM(MERROR, "11D: region_chan not found. Band[%d]\n", band);
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+
+        /* Generate parsed region channel info from region channel */
+        (void)__memset(pmadapter, &parsed_region_chan, 0, sizeof(parsed_region_chan_11d_t));
+        wlan_11d_generate_parsed_region_chan(pmadapter, region_chan, &parsed_region_chan);
+
+        /* Generate domain info from parsed region channel info */
+        (void)wlan_11d_generate_domain_info(pmadapter, &parsed_region_chan);
+
+        /* Set domain info */
+        ret = wlan_11d_send_domain_info(pmpriv, MNULL, MFALSE);
+        if (ret != MLAN_STATUS_SUCCESS)
+        {
+            PRINTM(MERROR, "11D: Error sending domain info to FW\n");
+        }
+    }
+
+    LEAVE();
+    return ret;
+}
+
+void wlan_filter_domain_channel(mlan_private *pmpriv,
+                                parsed_region_chan_11d_t *origin_region_chan,
+                                parsed_region_chan_11d_t *filtered_region_chan)
+{
+    t_u32 i;
+
+    for (i = 0; (i < origin_region_chan->no_of_chan) && (i < MAX_NO_OF_CHAN); i++)
+    {
+        if(MTRUE == wlan_check_channel_by_region_table(pmpriv, origin_region_chan->chan_pwr[i].chan))
+        {
+            (void)__memcpy(pmpriv->adapter, &filtered_region_chan->chan_pwr[filtered_region_chan->no_of_chan],
+                           &origin_region_chan->chan_pwr[i], sizeof(chan_power_11d_t));
+            filtered_region_chan->no_of_chan++;
+        }
+    }
+}
+/**
+ *  @brief This function parses country info from AP and
+ *           download country info to FW
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc     A pointer to BSS descriptor
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_parse_dnld_countryinfo(mlan_private *pmpriv, BSSDescriptor_t *pbss_desc)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    parsed_region_chan_11d_t region_chan;
+    parsed_region_chan_11d_t bssdesc_region_chan;
+    parsed_region_chan_11d_t filtered_region_chan;
+    t_u32 i, j;
+
+    ENTER();
+
+    /* Only valid if 11D is enabled */
+    if (wlan_11d_is_enabled(pmpriv))
+    {
+        (void)__memset(pmadapter, &region_chan, 0, sizeof(parsed_region_chan_11d_t));
+        (void)__memset(pmadapter, &bssdesc_region_chan, 0, sizeof(parsed_region_chan_11d_t));
+        (void)__memset(pmadapter, &filtered_region_chan, 0, sizeof(parsed_region_chan_11d_t));
+
+        (void)__memcpy(pmadapter, &region_chan, &pmadapter->parsed_region_chan, sizeof(parsed_region_chan_11d_t));
+
+        if (pbss_desc != MNULL)
+        {
+            /** Country code */
+            t_u8 country_code[COUNTRY_CODE_LEN];
+            country_code[0] = pbss_desc->country_info.country_code[0];
+            country_code[1] = pbss_desc->country_info.country_code[1];
+            country_code[2] = ' ';
+
+            if (is_special_region_code(country_code))
+            {
+                PRINTM(MINFO, "Skip special region code in CountryIE");
+                LEAVE();
+                return MLAN_STATUS_SUCCESS;
+            }
+            /* Parse domain info if available */
+            ret = wlan_11d_parse_domain_info(pmadapter, &pbss_desc->country_info, pbss_desc->bss_band,
+                                             &bssdesc_region_chan);
+            if (ret == MLAN_STATUS_SUCCESS)
+            {
+                /* Update the channel-power table */
+                for (i = 0; ((i < bssdesc_region_chan.no_of_chan) && (i < MAX_NO_OF_CHAN)); i++)
+                {
+                    for (j = 0; ((j < region_chan.no_of_chan) && (j < MAX_NO_OF_CHAN)); j++)
+                    {
+                        /*
+                         * Channel already exists, use minimum of existing
+                         * tx power and tx_power received from
+                         * country info of the current AP
+                         */
+                        if (region_chan.chan_pwr[i].chan == bssdesc_region_chan.chan_pwr[j].chan &&
+                            region_chan.chan_pwr[i].band == bssdesc_region_chan.chan_pwr[j].band)
+                        {
+                            region_chan.chan_pwr[j].pwr =
+                                MIN(region_chan.chan_pwr[j].pwr, bssdesc_region_chan.chan_pwr[i].pwr);
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+
+        /* Filter out channel list of current region code, then generate domain info */
+        (void)wlan_filter_domain_channel(pmpriv, &region_chan, &filtered_region_chan);
+
+        /* Generate domain info */
+        (void)wlan_11d_generate_domain_info(pmadapter, &filtered_region_chan);
+
+        /* Set domain info */
+        ret = wlan_11d_send_domain_info(pmpriv, MNULL, MFALSE);
+        if (ret != MLAN_STATUS_SUCCESS)
+        {
+            PRINTM(MERROR, "11D: Error sending domain info to FW\n");
+        }
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function prepares domain info from scan table and
+ *         downloads the domain info command to the FW.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_prepare_dnld_domain_info_cmd(mlan_private *pmpriv)
+{
+    mlan_status ret                               = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter                       = pmpriv->adapter;
+    IEEEtypes_CountryInfoFullSet_t *pcountry_full = MNULL;
+    t_u32 idx;
+
+    ENTER();
+
+    /* Only valid if 11D is enabled */
+    if (wlan_11d_is_enabled(pmpriv) && pmadapter->num_in_scan_table != 0U)
+    {
+        for (idx = 0; idx < pmadapter->num_in_scan_table; idx++)
+        {
+            pcountry_full = &pmadapter->pscan_table[idx].country_info;
+
+            ret = wlan_11d_update_chan_pwr_table(pmpriv, &pmadapter->pscan_table[idx]);
+
+            if (*(pcountry_full->country_code) != 0U && (pcountry_full->len > COUNTRY_CODE_LEN))
+            {
+                /* Country info found in the BSS Descriptor */
+                ret = wlan_11d_process_country_info(pmpriv, &pmadapter->pscan_table[idx]);
+            }
+        }
+
+        /* Sort parsed_region_chan in ascending channel number */
+        wlan_11d_sort_parsed_region_chan(&pmadapter->parsed_region_chan);
+#if 0
+        /* Check if connected */
+        if (pmpriv->media_connected == MTRUE)
+        {
+            ret = wlan_11d_parse_dnld_countryinfo(pmpriv, &pmpriv->curr_bss_params.bss_descriptor);
+        }
+        else
+        {
+            ret = wlan_11d_parse_dnld_countryinfo(pmpriv, MNULL);
+        }
+#endif
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function sets up domain_reg and downloads CMD to FW
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   Pointer to the IOCTL request buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_cfg_domain_info(IN pmlan_adapter pmadapter, IN mlan_ioctl_req *pioctl_req)
+{
+    mlan_status ret                      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv                 = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_11d_domain_info *domain_info = MNULL;
+    mlan_ds_11d_cfg *cfg_11d             = MNULL;
+    t_u8 region_code                     = 0;
+
+    ENTER();
+
+    cfg_11d     = (mlan_ds_11d_cfg *)(void *)pioctl_req->pbuf;
+    domain_info = &cfg_11d->param.domain_info;
+
+#ifdef OTP_CHANINFO
+    if ((pmadapter->otp_region != MNULL) && (pmadapter->otp_region->force_reg != 0U))
+    {
+        (void)PRINTF("ForceRegionRule is set in the on-chip OTP memory\r\n");
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+#endif
+
+    /* Update region code and table based on country code */
+    if (wlan_11d_region_2_code(pmadapter, domain_info->country_code, &region_code) == MLAN_STATUS_SUCCESS)
+    {
+        pmadapter->region_code = region_code;
+        ret                    = wlan_set_regiontable(pmpriv, region_code, pmadapter->fw_bands);
+        if (ret != MLAN_STATUS_SUCCESS)
+        {
+            goto done;
+        }
+    }
+
+    (void)wlan_11d_set_domain_info(pmpriv, domain_info->band, domain_info->country_code, domain_info->no_of_sub_band,
+                                   (IEEEtypes_SubbandSet_t *)(void *)domain_info->sub_band);
+    ret = wlan_11d_send_domain_info(pmpriv, pioctl_req, MFALSE);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+done:
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function handles domain info data from UAP interface.
+ *         Checks conditions, sets up domain_reg, then downloads CMD.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param band         Band interface is operating on
+ *  @param domain_tlv   Pointer to domain_info tlv
+ *  @param pioctl_buf   Pointer to the IOCTL buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_11d_handle_uap_domain_info(mlan_private *pmpriv, t_u16 band, t_u8 *domain_tlv, t_void *pioctl_buf)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    MrvlIEtypes_DomainParamSet_t *pdomain_tlv;
+    t_u8 num_sub_band = 0;
+    t_u8 region_code  = 0;
+
+    ENTER();
+
+    pdomain_tlv = (MrvlIEtypes_DomainParamSet_t *)(void *)domain_tlv;
+
+    // update region code & table based on country string
+    if (wlan_11d_region_2_code(pmadapter, pdomain_tlv->country_code, &region_code) == MLAN_STATUS_SUCCESS)
+    {
+        pmadapter->region_code = region_code;
+        ret                    = wlan_set_regiontable(pmpriv, region_code, pmadapter->fw_bands);
+    }
+
+    num_sub_band = (t_u8)((pdomain_tlv->header.len - COUNTRY_CODE_LEN) / sizeof(IEEEtypes_SubbandSet_t));
+
+    // TODO: don't just clobber pmadapter->domain_reg.
+    // Add some checking or merging between STA & UAP domain_info
+
+    (void)wlan_11d_set_domain_info(pmpriv, band, pdomain_tlv->country_code, num_sub_band, pdomain_tlv->sub_band);
+
+    /* wmsdk: We do not yet have mechanism in wlan_prepare_cmd() to
+       separate uao and sta commands. Hence we have to call uap cmd send
+       function here manually */
+    /* ret = wlan_11d_send_domain_info(pmpriv, pioctl_buf); */
+    int rv = wifi_uap_prepare_and_send_cmd(pmpriv, HostCmd_CMD_802_11D_DOMAIN_INFO, HostCmd_ACT_GEN_SET, 0,
+                                           (t_void *)pioctl_buf, MNULL, MLAN_BSS_TYPE_UAP, NULL);
+    if (rv != 0)
+    {
+        wuap_w("Unable to send uap domain info");
+        ret = MLAN_STATUS_FAILURE;
+    }
+
+    LEAVE();
+    return ret;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11h.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11h.c
new file mode 100644
index 0000000000..5a65f26f53
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11h.c
@@ -0,0 +1,273 @@
+/** @file mlan_11h.c
+ *
+ *  @brief  This file provides functions for 802.11H
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*************************************************************
+Change Log:
+    03/26/2009: initial version
+************************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+/********************************************************
+                Local Variables
+********************************************************/
+/** Default IBSS DFS recovery interval (in TBTTs); used for adhoc start */
+#define WLAN_11H_DEFAULT_DFS_RECOVERY_INTERVAL 100
+
+/** Default 11h power constraint used to offset the maximum transmit power */
+#define WLAN_11H_TPC_POWERCONSTRAINT 0
+
+/** 11h TPC Power capability minimum setting, sent in TPC_INFO command to fw */
+#define WLAN_11H_TPC_POWERCAPABILITY_MIN 5
+
+/** 11h TPC Power capability maximum setting, sent in TPC_INFO command to fw */
+#define WLAN_11H_TPC_POWERCAPABILITY_MAX 20
+
+/** Regulatory requirement for the duration of a channel availability check */
+#define WLAN_11H_CHANNEL_AVAIL_CHECK_DURATION 60000 /* in ms */
+
+/** Starting Frequency for 11A band */
+#define START_FREQ_11A_BAND 5000 /* in MHz */
+
+/** Regulatory requirement for the duration of a non-occupancy period */
+#define WLAN_11H_NON_OCCUPANCY_PERIOD 1800 /* in sec (30mins) */
+
+/** Maximum allowable age (seconds) on DFS report data */
+#define MAX_DFS_REPORT_USABLE_AGE_SEC (120) // 2 minutes
+
+/** Minimum delay for CHAN_SW IE to broadcast by FW */
+#define MIN_RDH_CHAN_SW_IE_PERIOD_MSEC (500) // 5 beacons @ 100ms
+
+/** Maximum delay for CHAN_SW IE to broadcast by FW */
+#define MAX_RDH_CHAN_SW_IE_PERIOD_MSEC (3000) // 5 beacons @ 600ms
+
+/** Maximum retries on selecting new random channel */
+#define MAX_RANDOM_CHANNEL_RETRIES (20)
+
+/** Maximum retries on selecting new random non-dfs channel */
+#define MAX_SWITCH_CHANNEL_RETRIES (30)
+
+/** Value for undetermined priv_curr_idx on first entry to new RDH stage */
+#define RDH_STAGE_FIRST_ENTRY_PRIV_IDX (0xff)
+
+
+/** Internally passed structure used to send a CMD_802_11_TPC_INFO command */
+typedef struct
+{
+    t_u8 chan;             /**< Channel to which the power constraint applies */
+    t_u8 power_constraint; /**< Local power constraint to send to firmware */
+} wlan_11h_tpc_info_param_t;
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+
+/**
+ *  @brief Initialize the 11h parameters and enable 11h when starting an IBSS
+ *
+ *  @param adapter mlan_adapter structure
+ *
+ *  @return      N/A
+ */
+void wlan_11h_init(mlan_adapter *adapter)
+{
+    wlan_11h_device_state_t *pstate_11h      = &adapter->state_11h;
+    IEEEtypes_Quiet_t *pquiet                = &adapter->state_11h.quiet_ie;
+    wlan_dfs_device_state_t *pstate_dfs      = &adapter->state_dfs;
+    wlan_radar_det_hndlg_state_t *pstate_rdh = &adapter->state_rdh;
+
+    ENTER();
+
+    /* Initialize 11H struct */
+    pstate_11h->usr_def_power_constraint        = WLAN_11H_TPC_POWERCONSTRAINT;
+    pstate_11h->min_tx_power_capability         = WLAN_11H_TPC_POWERCAPABILITY_MIN;
+    pstate_11h->max_tx_power_capability         = WLAN_11H_TPC_POWERCAPABILITY_MAX;
+    pstate_11h->recvd_chanswann_event           = MFALSE;
+    pstate_11h->master_radar_det_enable_pending = MFALSE;
+    pstate_11h->slave_radar_det_enable_pending  = MFALSE;
+    pstate_11h->is_master_radar_det_active      = MFALSE;
+    pstate_11h->is_slave_radar_det_active       = MFALSE;
+
+    /* Initialize quiet_ie */
+    (void)__memset(adapter, pquiet, 0, sizeof(IEEEtypes_Quiet_t));
+    pquiet->element_id = QUIET;
+    pquiet->len        = (sizeof(pquiet->quiet_count) + sizeof(pquiet->quiet_period) + sizeof(pquiet->quiet_duration) +
+                   sizeof(pquiet->quiet_offset));
+
+    /* Initialize DFS struct */
+    pstate_dfs->dfs_check_pending   = MFALSE;
+    pstate_dfs->dfs_radar_found     = MFALSE;
+    pstate_dfs->dfs_check_channel   = 0;
+    pstate_dfs->dfs_report_time_sec = 0;
+    util_init_list((pmlan_linked_list)(void *)&pstate_dfs->dfs_ts_head);
+
+    /* Initialize RDH struct */
+    pstate_rdh->stage           = RDH_OFF;
+    pstate_rdh->priv_list_count = 0;
+    pstate_rdh->priv_curr_idx   = 0;
+    pstate_rdh->curr_channel    = 0;
+    pstate_rdh->new_channel     = 0;
+    pstate_rdh->uap_band_cfg    = 0;
+    pstate_rdh->max_bcn_dtim_ms = 0;
+    (void)__memset(adapter, pstate_rdh->priv_list, 0, sizeof(pstate_rdh->priv_list));
+
+    LEAVE();
+}
+
+
+/**
+ *  @brief Initialize the 11h parameters and enable 11h when starting an IBSS
+ *
+ *  @param pmpriv Pointer to mlan_private structure
+ *
+ *  @return      N/A
+ */
+void wlan_11h_priv_init(mlan_private *pmpriv)
+{
+    wlan_11h_interface_state_t *pistate_11h = &pmpriv->intf_state_11h;
+
+    ENTER();
+
+    pistate_11h->is_11h_enabled      = MTRUE;
+    pistate_11h->is_11h_active       = MFALSE;
+    pistate_11h->adhoc_auto_sel_chan = MTRUE;
+    pistate_11h->tx_disabled         = MFALSE;
+
+    LEAVE();
+}
+
+
+/**
+ *  @brief Check if the current region's regulations require the input channel
+ *         to be scanned for radar.
+ *
+ *  Based on statically defined requirements for sub-bands per regulatory
+ *    agency requirements.
+ *
+ *  Used in adhoc start to determine if channel availability check is required
+ *
+ *  @param priv    Private driver information structure
+ *  @param channel Channel to determine radar detection requirements
+ *
+ *  @return
+ *    - MTRUE if radar detection is required
+ *    - MFALSE otherwise
+ */
+/**  @sa wlan_11h_issue_radar_detect
+ */
+t_bool wlan_11h_radar_detect_required(mlan_private *priv, t_u8 channel)
+{
+    t_bool required = MFALSE;
+
+    ENTER();
+
+    /*
+     *   No checks for 11h or measurement code being enabled is placed here
+     *   since regulatory requirements exist whether we support them or not.
+     */
+
+    required = wlan_get_cfp_radar_detect(priv, channel);
+
+    if (!priv->adapter->region_code)
+    {
+        PRINTM(MINFO,
+               "11h: Radar detection in CFP code[BG:%#x, A:%#x] "
+               "is %srequired for channel %d\n",
+               priv->adapter->cfp_code_bg, priv->adapter->cfp_code_a, (required ? "" : "not "), channel);
+    }
+    else
+    {
+        PRINTM(MINFO,
+               "11h: Radar detection in region %#02x "
+               "is %srequired for channel %d\n",
+               priv->adapter->region_code, (required ? "" : "not "), channel);
+    }
+
+    if (required == MTRUE && priv->media_connected == MTRUE && priv->curr_bss_params.bss_descriptor.channel == channel)
+    {
+        required = MFALSE;
+
+        PRINTM(MINFO,
+               "11h: Radar detection not required. "
+               "Already operating on the channel\n");
+    }
+
+    LEAVE();
+    return required;
+}
+
+#if CONFIG_ECSA
+/**
+ *  @brief try to get a non-dfs channel
+ *
+ *  @param priv    Void pointer to mlan_private
+ *
+ *  @param chan    pointer to channel
+ *
+ *  @return MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE or MLAN_STATUS_PENDING
+ */
+mlan_status wlan_get_non_dfs_chan(mlan_private *priv, t_u8 *chan)
+{
+    mlan_status ret = MLAN_STATUS_FAILURE;
+    t_u32 i;
+    t_u32 entry;
+    t_u8 def_chan           = 0;
+    region_chan_t *chn_tbl  = MNULL;
+    pmlan_adapter pmadapter = priv->adapter;
+
+    ENTER();
+
+    /* get the channel table first */
+    for (i = 0; i < MAX_REGION_CHANNEL_NUM; i++)
+    {
+        if (pmadapter->region_channel[i].valid)
+        {
+            chn_tbl = &pmadapter->region_channel[i];
+
+            if (!chn_tbl || !chn_tbl->pcfp)
+            {
+                goto done;
+            }
+
+            for (entry = 0; entry < chn_tbl->num_cfp; entry++)
+            {
+                if (chn_tbl->pcfp[entry].passive_scan_or_radar_detect == MFALSE)
+                {
+                    def_chan = (t_u8)chn_tbl->pcfp[entry].channel;
+                    break;
+                }
+            }
+
+            if (entry == chn_tbl->num_cfp)
+            {
+                goto done;
+            }
+        }
+    }
+
+    *chan = def_chan;
+    ret   = MLAN_STATUS_SUCCESS;
+done:
+    LEAVE();
+    return ret;
+}
+#endif
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11k.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11k.c
new file mode 100644
index 0000000000..5ca115a26c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11k.c
@@ -0,0 +1,1088 @@
+/** @file mlan_11k.c
+ *
+ *  @brief  This file provides functions for process 11k(RRM) feature
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    08/24/2022: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+#if CONFIG_11K
+#define LINK_MSR_REPORT_BUF_SIZE  64U
+#define NEIGHBOR_REQUEST_BUF_SIZE 64U
+#define rrm_bits_max              255U
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+static uint8_t broadcast_mac_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+/********************************************************
+                Local Functions
+********************************************************/
+static t_u8 wlan_rrm_rssi_to_rcpi(int rssi)
+{
+    t_u8 ret_rcpi = 0;
+    int rcpi      = 0;
+
+    if (rssi == 0)
+    {
+        return (t_u8)255U;
+    }
+    else if (rssi > 0)
+    {
+        return (t_u8)220U;
+    }
+    else if (rssi < -110)
+    {
+        return (t_u8)0U;
+    }
+    else
+    {
+        rcpi     = (rssi + 110) * 2;
+        ret_rcpi = (t_u8)rcpi;
+        return ret_rcpi;
+    }
+}
+
+static void wlan_rrm_put_le64(t_u8 *a, t_u64 val)
+{
+    a[7] = (t_u8)(val >> 56);
+    a[6] = (t_u8)(val >> 48);
+    a[5] = (t_u8)(val >> 40);
+    a[4] = (t_u8)(val >> 32);
+    a[3] = (t_u8)(val >> 24);
+    a[2] = (t_u8)(val >> 16);
+    a[1] = (t_u8)(val >> 8);
+    a[0] = (t_u8)(val & 0xffULL);
+}
+
+static void wlan_rrm_put_le16(t_u8 *a, t_u16 val)
+{
+    a[1] = (t_u8)(val >> 8);
+    a[0] = (t_u8)(val & (t_u16)0xff);
+}
+
+static void wlan_rrm_bit_field_set(t_u8 *bits_field, t_u8 bit)
+{
+    if (bit >= (t_u8)rrm_bits_max)
+    {
+        return;
+    }
+
+    bits_field[bit / 8U] |= BIT(bit % 8U);
+}
+
+static bool wlan_rrm_bit_field_is_set(t_u8 *bit_field, t_u8 bit)
+{
+    if (bit >= (t_u8)rrm_bits_max)
+    {
+        return 0;
+    }
+
+    return ((bit_field[bit / (t_u8)8U] & (t_u8)(BIT((bit % 8U)))) != (t_u8)0U);
+}
+
+/* mod_group : ModulationGroup\n
+ *               0: CCK (1,2,5.5,11 Mbps)\n
+ *               1: OFDM (6,9,12,18 Mbps)\n
+ */
+static t_u8 wlan_link_measurement_get_tx_power(wifi_txpwrlimit_t *txpwrlimit, t_u8 ModulationGroup, t_u32 channel)
+{
+    t_u8 i;
+    t_u8 tx_power = 20;
+
+    for (i = 0; i < txpwrlimit->num_chans; i++)
+    {
+        if (txpwrlimit->txpwrlimit_config[i].chan_desc.chan_num == channel)
+        {
+            tx_power = txpwrlimit->txpwrlimit_config[i].txpwrlimit_entry[ModulationGroup].tx_power;
+            return tx_power;
+        }
+    }
+    return tx_power;
+}
+
+static int wlan_process_rm_beacon_req_subelement(wlan_rrm_beacon_report_data *rep_data,
+                                                 t_u8 sub_id,
+                                                 t_u8 sub_len,
+                                                 t_u8 *sub_elem)
+{
+    t_u8 i;
+
+    switch (sub_id)
+    {
+        case WLAN_RRM_BEACON_REQUEST_SUBELEMENT_SSID:
+            if (sub_len == (t_u8)0U)
+            {
+                break;
+            }
+
+            if (sub_len > MLAN_MAX_SSID_LENGTH)
+            {
+                wifi_d("Wrong SSID sub_element len: %u", sub_len);
+                return -1;
+            }
+
+            rep_data->ssid_length = sub_len;
+            (void)memcpy(rep_data->ssid, sub_elem, rep_data->ssid_length);
+            break;
+        case WLAN_RRM_BEACON_REQUEST_SUBELEMENT_REPORTING_INFO:
+            if (sub_len != 2U)
+            {
+                wifi_d("Wrong reporting info sub_element len: %u", sub_len);
+                return -1;
+            }
+
+            break;
+        case WLAN_RRM_BEACON_REQUEST_SUBELEMENT_REPORTING_DETAIL:
+            if (sub_len != 1U)
+            {
+                wifi_d("Wrong reporting datail sub_element len: %u", sub_len);
+                return -1;
+            }
+
+            if (rep_data->report_detail > WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS)
+            {
+                wifi_d("Wrong reporting datail value: %u", rep_data->report_detail);
+                return -1;
+            }
+            rep_data->report_detail = (enum wlan_rrm_beacon_reporting_detail)sub_elem[0];
+
+            break;
+        case WLAN_RRM_BEACON_REQUEST_SUBELEMENT_REQUEST:
+            if (rep_data->report_detail != WLAN_RRM_REPORTING_DETAIL_AS_REQUEST)
+            {
+                wifi_d("Sub_lement request is present with wrong report detail: %u", rep_data->report_detail);
+                return -1;
+            }
+
+            if (sub_len == (t_u8)0U)
+            {
+                wifi_d("wrong request sub_element len: %u", sub_len);
+                return -1;
+            }
+
+            for (i = 0; i < sub_len; i++)
+            {
+                wlan_rrm_bit_field_set(rep_data->bits_field, sub_elem[i]);
+            }
+            break;
+        case WLAN_RRM_BEACON_REQUEST_SUBELEMENT_AP_CHANNEL:
+            if (rep_data->channel_num + sub_len - 1U > (t_u8)MAX_CHANNEL_LIST)
+            {
+                return 0;
+            }
+
+            for (i = 0; i < (t_u8)(sub_len - 1U); i++)
+            {
+                rep_data->channel[rep_data->channel_num + i] = sub_elem[i + 1U];
+            }
+
+            rep_data->channel_num += sub_len - 1U;
+            break;
+        case WLAN_RRM_BEACON_REQUEST_SUBELEMENT_LAST_INDICATION:
+            if (sub_len != 1U)
+            {
+                wifi_d("wrong last indication sub_element len: %u", sub_len);
+                return -1;
+            }
+
+            rep_data->last_ind = sub_elem[0];
+            break;
+        default:
+            wifi_d("Sub element id: %u is not handled for beacon request", sub_id);
+            break;
+    }
+
+    return 0;
+}
+
+static void wlan_process_rm_beacon_report_table(
+    wlan_rrm_beacon_report_data *rep_data, t_u8 dialog_tok, t_u8 *dest_addr, t_u8 *src_addr, bool protect)
+{
+    t_u16 i;
+    t_u8 *rep_buf = NULL;
+    t_u8 *buf_pos = NULL;
+    /* The sufficient size is the length including reporting frame body */
+    t_u16 suffi_len           = 250;
+    t_u32 pos_last_indication = 0;
+    bool match_ap_found       = false;
+    int meas_rep_len          = 0;
+
+#if !CONFIG_MEM_POOLS
+    rep_buf = (t_u8 *)OSA_MemoryAllocate(BEACON_REPORT_BUF_SIZE);
+#else
+    rep_buf = (t_u8 *)OSA_MemoryPoolAllocate(buf_1536_MemoryPool);
+#endif
+
+    if (rep_buf == NULL)
+    {
+        wifi_e("Cannot allocate memory for report buffer");
+        return;
+    }
+
+    (void)memset(rep_buf, 0, BEACON_REPORT_BUF_SIZE);
+    buf_pos = rep_buf;
+    for (i = 0; i < mlan_adap->num_in_scan_table; i++)
+    {
+        if (wlan_rrm_matched_ap_found(rep_data, &mlan_adap->pscan_table[i]))
+        {
+            wlan_add_rm_beacon_report(rep_data, &mlan_adap->pscan_table[i], &buf_pos,
+                                      BEACON_REPORT_BUF_SIZE - (buf_pos - rep_buf), &pos_last_indication);
+        }
+
+        /* If current rep_buf is not enough and still have AP not added, just send the report */
+        if ((buf_pos + suffi_len - rep_buf > BEACON_REPORT_BUF_SIZE) &&
+            (i < (t_u16)(mlan_adap->num_in_scan_table - 1U)) &&
+            wlan_rrm_matched_ap_found(rep_data, &mlan_adap->pscan_table[i + 1U]))
+        {
+            match_ap_found = 1;
+            meas_rep_len   = buf_pos - rep_buf;
+            /* send beacon report, not the last one */
+            wlan_send_mgmt_rm_beacon_report(dialog_tok, dest_addr, src_addr, rep_buf, (t_u32)(meas_rep_len), protect);
+            /* Prepare for the next beacon report */
+            (void)memset(rep_buf, 0, BEACON_REPORT_BUF_SIZE);
+            buf_pos = rep_buf;
+        }
+
+        /* Last AP in scan table, and matched AP found */
+        if ((i == mlan_adap->num_in_scan_table - 1U) && (buf_pos > rep_buf))
+        {
+            match_ap_found = 1;
+            /* Update last indication, the last one */
+            if (rep_data->last_ind > (t_u8)0U && pos_last_indication > 0U)
+            {
+                *(char *)pos_last_indication = (char)1U;
+            }
+            meas_rep_len = buf_pos - rep_buf;
+            /* send beacon report, the last one */
+            wlan_send_mgmt_rm_beacon_report(dialog_tok, dest_addr, src_addr, rep_buf, (t_u32)(meas_rep_len), protect);
+        }
+    }
+
+    /* If no matched AP found, no beacon report detail */
+    if (!match_ap_found)
+    {
+        *buf_pos++ = (t_u8)MEASURE_REPORT;
+        /* Tag length */
+        *buf_pos++   = 3;
+        *buf_pos++   = rep_data->token;
+        *buf_pos++   = WLAN_RRM_REPORT_MODE_ACCEPT;
+        *buf_pos++   = WLAN_RRM_MEASURE_TYPE_BEACON;
+        meas_rep_len = buf_pos - rep_buf;
+        /* send beacon report */
+        wlan_send_mgmt_rm_beacon_report(dialog_tok, dest_addr, src_addr, rep_buf, (t_u32)(meas_rep_len), protect);
+    }
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(rep_buf);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, rep_buf);
+#endif
+}
+
+bool wlan_rrm_matched_ap_found(wlan_rrm_beacon_report_data *rep_data, BSSDescriptor_t *bss_entry)
+{
+    if (memcmp(rep_data->bssid, broadcast_mac_addr, IEEEtypes_ADDRESS_SIZE) != 0 &&
+        memcmp(rep_data->bssid, bss_entry->mac_address, IEEEtypes_ADDRESS_SIZE) != 0)
+    {
+        return 0;
+    }
+
+    if (rep_data->ssid_length > 0U && (rep_data->ssid_length != bss_entry->ssid.ssid_len ||
+                                       memcmp(rep_data->ssid, bss_entry->ssid.ssid, bss_entry->ssid.ssid_len) != 0))
+    {
+        return 0;
+    }
+
+    return 1;
+}
+
+static void wlan_process_rm_beacon_req(t_u8 *req,
+                                       t_u32 len,
+                                       t_u8 element_token,
+                                       t_u8 dialog_tok,
+                                       t_u8 *dest_addr,
+                                       t_u8 *src_addr,
+                                       bool protect,
+                                       bool duration_mandatory)
+{
+    mgmt_rrm_meas_beacon_request *beacon_req = (mgmt_rrm_meas_beacon_request *)(void *)req;
+    t_u8 *sub_element;
+    int element_len;
+    int ret = 0, i;
+    wlan_scan_params_v2_t wlan_scan_param;
+    wlan_rrm_scan_cb_param *param = NULL;
+
+    if (beacon_req->mode != (t_u8)WLAN_RRM_MEASUREMENT_MODE_PASSIVE &&
+        beacon_req->mode != (t_u8)WLAN_RRM_MEASUREMENT_MODE_ACTIVE &&
+        beacon_req->mode != (t_u8)WLAN_RRM_MEASUREMENT_MODE_TABLE)
+    {
+        return;
+    }
+
+    sub_element = beacon_req->variable;
+    element_len = (int)len - ((int)sizeof(mgmt_rrm_meas_beacon_request) - 1);
+
+#if !CONFIG_MEM_POOLS
+    param = (wlan_rrm_scan_cb_param *)OSA_MemoryAllocate(sizeof(wlan_rrm_scan_cb_param));
+#else
+    param = (wlan_rrm_scan_cb_param *)OSA_MemoryPoolAllocate(buf_256_MemoryPool);
+#endif
+    if (param == NULL)
+    {
+        wifi_e("Cannot allocate memory for rm scan param");
+        return;
+    }
+    (void)memset(param, 0, sizeof(wlan_rrm_scan_cb_param));
+    param->rep_data.token         = element_token;
+    param->rep_data.report_detail = WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS;
+    param->rep_data.duration      = wlan_le16_to_cpu(beacon_req->duration);
+    (void)memcpy(param->rep_data.bssid, beacon_req->bssid, IEEEtypes_ADDRESS_SIZE);
+
+    while (element_len >= 2)
+    {
+        ret = wlan_process_rm_beacon_req_subelement(&param->rep_data, sub_element[0], sub_element[1], &sub_element[2]);
+        if (ret < 0)
+        {
+            goto output;
+        }
+
+        element_len -= 2 + (int)sub_element[1];
+        sub_element += 2U + sub_element[1];
+    }
+
+    /* Measurement mode: Beacon Table */
+    if (beacon_req->mode == (t_u8)WLAN_RRM_MEASUREMENT_MODE_TABLE)
+    {
+        wlan_process_rm_beacon_report_table(&param->rep_data, dialog_tok, dest_addr, src_addr, protect);
+        goto output;
+    }
+
+    /* Measurement mode: Passive or Active, need to scan first */
+    (void)memset(&wlan_scan_param, 0, sizeof(wlan_scan_params_v2_t));
+    if (beacon_req->channel > 0U && beacon_req->channel != 255U)
+    {
+        wlan_scan_param.num_channels             = 1;
+        wlan_scan_param.chan_list[0].chan_number = beacon_req->channel;
+        if (beacon_req->mode == (t_u8)WLAN_RRM_MEASUREMENT_MODE_ACTIVE)
+        {
+            wlan_scan_param.chan_list[0].scan_type = MLAN_SCAN_TYPE_ACTIVE;
+        }
+        else
+        {
+            wlan_scan_param.chan_list[0].scan_type = MLAN_SCAN_TYPE_PASSIVE;
+        }
+
+        if (duration_mandatory)
+        {
+            wlan_scan_param.chan_list[0].scan_time = beacon_req->duration;
+        }
+    }
+    else if (beacon_req->channel == 255U && param->rep_data.channel_num > (t_u8)0U)
+    {
+        wlan_scan_param.num_channels = param->rep_data.channel_num;
+        for (i = 0; i < (int)param->rep_data.channel_num && i < MAX_CHANNEL_LIST; i++)
+        {
+            wlan_scan_param.chan_list[i].chan_number = param->rep_data.channel[i];
+            if (beacon_req->mode == (t_u8)WLAN_RRM_MEASUREMENT_MODE_ACTIVE)
+            {
+                wlan_scan_param.chan_list[i].scan_type = MLAN_SCAN_TYPE_ACTIVE;
+            }
+            else
+            {
+                wlan_scan_param.chan_list[i].scan_type = MLAN_SCAN_TYPE_PASSIVE;
+            }
+
+            if (duration_mandatory)
+            {
+                wlan_scan_param.chan_list[i].scan_time = beacon_req->duration;
+            }
+        }
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    if (param->rep_data.ssid_length > (t_u8)0U)
+    {
+        (void)memcpy((void *)&wlan_scan_param.ssid[0], (const void *)param->rep_data.ssid,
+                     (size_t)param->rep_data.ssid_length);
+    }
+
+    param->dialog_tok = dialog_tok;
+    param->protect    = (t_u8)protect;
+    (void)memcpy(param->dst_addr, src_addr, IEEEtypes_ADDRESS_SIZE);
+    wlan_scan_param.cb = _wlan_rrm_scan_cb;
+
+    /* After scanning done, will send beacon report */
+    wlan_rrm_request_scan(&wlan_scan_param, param);
+output:
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(param);
+#else
+    OSA_MemoryPoolFree(buf_256_MemoryPool, param);
+#endif
+
+    return;
+}
+
+/********************************************************
+                Global functions
+********************************************************/
+void wlan_add_rm_beacon_report(wlan_rrm_beacon_report_data *rep_data,
+                               BSSDescriptor_t *bss_entry,
+                               t_u8 **buf_pos,
+                               t_s32 remained_len,
+                               t_u32 *pos_last_indication)
+{
+    mgmt_rrm_meas_beacon_report report;
+    t_u8 *pos         = *buf_pos;
+    t_u8 *pos_tag_len = NULL;
+    t_u8 *pos_sub_len = NULL;
+    t_u16 cap_info    = (t_u16)0U;
+    int meas_tag_len  = 0;
+    int meas_sub_len  = 0;
+
+    (void)memset(&report, 0, sizeof(mgmt_rrm_meas_beacon_report) - 1U);
+    (void)wlan_get_curr_global_oper_class(mlan_adap->priv[0], (t_u8)bss_entry->channel, bss_entry->curr_bandwidth,
+                                          &report.op_class);
+
+    /* Measurement report */
+    *pos++ = (t_u8)MEASURE_REPORT;
+    /* The length will be filled below */
+    pos_tag_len = pos;
+    pos++;
+    *pos++ = rep_data->token;
+    *pos++ = WLAN_RRM_REPORT_MODE_ACCEPT;
+    *pos++ = WLAN_RRM_MEASURE_TYPE_BEACON;
+
+    /* Beacon report element */
+    report.channel = bss_entry->channel;
+    /* Start time is not verified in CERT, to be done */
+    report.m_start_time = 0;
+    report.duration     = wlan_cpu_to_le16(rep_data->duration);
+    report.rcpi         = wlan_rrm_rssi_to_rcpi(-(bss_entry->rssi));
+    report.rsni         = 255;
+    (void)memcpy(report.bssid, bss_entry->mac_address, IEEEtypes_ADDRESS_SIZE);
+    report.ant_id = 0;
+    /* Parent tsf is not verified in CERT, to be done */
+    report.parent_tsf = 0;
+    if (bss_entry->pvht_cap != MNULL)
+    {
+        report.report_info = (t_u8)WLAN_PHY_TYPE_VHT;
+    }
+    else if (bss_entry->pht_cap != MNULL)
+    {
+        report.report_info = (t_u8)WLAN_PHY_TYPE_HT;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    (void)memcpy((void *)pos, (const void *)&report, sizeof(mgmt_rrm_meas_beacon_report) - 1U);
+    pos += sizeof(mgmt_rrm_meas_beacon_report) - 1U;
+
+    /* Start adding reported frame body */
+    if (rep_data->report_detail == WLAN_RRM_REPORTING_DETAIL_NONE)
+    {
+        goto without_subelem;
+    }
+    /* The min length of reported frame body is 14 */
+    if (pos + 14 - *buf_pos > remained_len)
+    {
+        goto without_subelem;
+    }
+
+    *pos++ = WLAN_RRM_BEACON_REP_SUBELEM_FRAME_BODY;
+    /* The length will be filled below */
+    pos_sub_len = pos;
+    pos++;
+    /* TSF to be done */
+    wlan_rrm_put_le64(pos, bss_entry->network_tsf);
+    pos += 8;
+    wlan_rrm_put_le16(pos, bss_entry->beacon_period);
+    pos += 2;
+    (void)memcpy((void *)&cap_info, (const void *)&bss_entry->cap_info, sizeof(t_u16));
+    wlan_rrm_put_le16(pos, cap_info);
+    pos += 2;
+    /* SSID tag */
+    if (rep_data->report_detail == WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS ||
+        wlan_rrm_bit_field_is_set(rep_data->bits_field, (t_u8)SSID))
+    {
+        if (pos + sizeof(IEEEtypes_Header_t) + bss_entry->ssid.ssid_len - *buf_pos > remained_len)
+        {
+            goto part_subelem;
+        }
+
+        *pos++ = (t_u8)SSID;
+        *pos++ = (t_u8)bss_entry->ssid.ssid_len;
+        if (bss_entry->ssid.ssid_len > 0U)
+        {
+            (void)memcpy(pos, &(bss_entry->ssid.ssid), bss_entry->ssid.ssid_len);
+            pos += bss_entry->ssid.ssid_len;
+        }
+    }
+    /* RSN tag */
+    if (rep_data->report_detail == WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS ||
+        wlan_rrm_bit_field_is_set(rep_data->bits_field, (t_u8)RSN_IE))
+    {
+        if (bss_entry->rsn_ie_buff_len > (size_t)0U)
+        {
+            if (pos + bss_entry->rsn_ie_buff_len - *buf_pos > remained_len)
+            {
+                goto part_subelem;
+            }
+
+            (void)memcpy(pos, bss_entry->rsn_ie_buff, bss_entry->rsn_ie_buff_len);
+            pos += bss_entry->rsn_ie_buff_len;
+        }
+    }
+    /* Mobility Domain tag */
+    if (rep_data->report_detail == WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS ||
+        wlan_rrm_bit_field_is_set(rep_data->bits_field, (t_u8)MOBILITY_DOMAIN))
+    {
+        if (pos + sizeof(IEEEtypes_MobilityDomain_t) - *buf_pos > remained_len)
+        {
+            goto part_subelem;
+        }
+
+        if (bss_entry->mob_domain_exist)
+        {
+            (void)memcpy((void *)pos, (const void *)bss_entry->md_ie_buff, sizeof(IEEEtypes_MobilityDomain_t));
+            pos += sizeof(IEEEtypes_MobilityDomain_t);
+        }
+    }
+    /* RM Enable Capabilities tag */
+    if (rep_data->report_detail == WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS ||
+        wlan_rrm_bit_field_is_set(rep_data->bits_field, (t_u8)RRM_ENABLED_CAP))
+    {
+        if (pos + sizeof(bss_entry->rm_cap_saved) - *buf_pos > remained_len)
+        {
+            goto part_subelem;
+        }
+
+        if (bss_entry->rm_cap_exist)
+        {
+            (void)memcpy((void *)pos, (const void *)&bss_entry->rm_cap_saved, sizeof(bss_entry->rm_cap_saved));
+            pos += sizeof(bss_entry->rm_cap_saved);
+        }
+    }
+    /* Vendor Specific tag */
+    if (rep_data->report_detail == WLAN_RRM_REPORTING_DETAIL_ALL_FIELDS_AND_ELEMENTS ||
+        wlan_rrm_bit_field_is_set(rep_data->bits_field, (t_u8)VENDOR_SPECIFIC_221))
+    {
+        /* wpa */
+        if (bss_entry->wpa_ie_buff_len > 0U)
+        {
+            if (pos + bss_entry->wpa_ie_buff_len - *buf_pos > remained_len)
+            {
+                goto part_subelem;
+            }
+
+            (void)memcpy(pos, bss_entry->wpa_ie_buff, bss_entry->wpa_ie_buff_len);
+            pos += bss_entry->wpa_ie_buff_len;
+        }
+        /* wmm */
+        if (pos + sizeof(bss_entry->wmm_ie) - *buf_pos > remained_len)
+        {
+            goto part_subelem;
+        }
+
+        if (wlan_strlen((char *)(&bss_entry->wmm_ie)) > 0U)
+        {
+            (void)memcpy((void *)pos, (const void *)&bss_entry->wmm_ie, sizeof(bss_entry->wmm_ie));
+            pos += sizeof(bss_entry->wmm_ie);
+        }
+        /* Others */
+        if (bss_entry->vendor_ie_len > (t_u8)0U)
+        {
+            if (pos + bss_entry->vendor_ie_len - *buf_pos > remained_len)
+            {
+                goto part_subelem;
+            }
+
+            (void)memcpy(pos, bss_entry->vendor_ie_buff, bss_entry->vendor_ie_len);
+            pos += bss_entry->vendor_ie_len;
+        }
+    }
+
+    if (rep_data->last_ind > 0U)
+    {
+        if (pos + WLAN_RRM_BEACON_REP_FRAME_BODY_FRAGMENT_SUB_LEN + WLAN_RRM_BEACON_REP_LAST_INDICATION_SUB_LEN -
+                *buf_pos >
+            remained_len)
+        {
+            goto part_subelem;
+        }
+
+        /* Frame body fragment id subelement */
+        pos[0] = WLAN_RRM_BEACON_REP_SUBELEM_FRAME_BODY_FRAGMENT_ID;
+        pos[1] = 2; /* Length */
+        pos[2] = 1; /* Beacon report id */
+        pos[3] = 0; /* Fragment id number */
+        pos += WLAN_RRM_BEACON_REP_FRAME_BODY_FRAGMENT_SUB_LEN;
+        /* Last indication subelement */
+        pos[0]               = WLAN_RRM_BEACON_REP_SUBELEM_LAST_INDICATION;
+        pos[1]               = 1; /* Length */
+        pos[2]               = 0; /* Temporarily, not the last packet */
+        *pos_last_indication = (t_u32)&pos[2];
+        pos += WLAN_RRM_BEACON_REP_LAST_INDICATION_SUB_LEN;
+    }
+    /* Fill the length */
+part_subelem:
+    meas_sub_len = pos - pos_sub_len - 1;
+    *pos_sub_len = (t_u8)meas_sub_len;
+without_subelem:
+    meas_tag_len = pos - pos_tag_len - 1;
+    *pos_tag_len = (t_u8)meas_tag_len;
+    *buf_pos     = pos;
+}
+
+void wlan_send_mgmt_rm_beacon_report(
+    t_u8 dialog_tok, t_u8 *src_addr, t_u8 *dst_addr, t_u8 *rep, t_u32 rep_len, bool protect)
+{
+    wlan_mgmt_pkt *pmgmt_pkt_hdr    = MNULL;
+    IEEEtypes_FrameCtl_t *mgmt_fc_p = MNULL;
+    t_u8 *pos                       = MNULL;
+    t_u16 pkt_len                   = 0;
+    int meas_pkt_len                = 0;
+
+    pmgmt_pkt_hdr = wifi_PrepDefaultMgtMsg(
+        SUBTYPE_ACTION, (mlan_802_11_mac_addr *)(void *)dst_addr, (mlan_802_11_mac_addr *)(void *)src_addr,
+        (mlan_802_11_mac_addr *)(void *)dst_addr, sizeof(wlan_mgmt_pkt) + (t_u32)BEACON_REPORT_BUF_SIZE);
+    if (pmgmt_pkt_hdr == MNULL)
+    {
+        wifi_d("No memory available for beacon report");
+        return;
+    }
+
+    mgmt_fc_p = (IEEEtypes_FrameCtl_t *)(void *)&pmgmt_pkt_hdr->wlan_header.frm_ctl;
+    if (protect)
+    {
+        mgmt_fc_p->wep = 1;
+    }
+
+    /* 802.11 management body */
+    pos    = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+    pos[0] = (t_u8)IEEE_MGMT_ACTION_CATEGORY_RADIO_RSRC;
+    pos[1] = (t_u8)IEEE_MGMT_RRM_RADIO_MEASUREMENT_REPORT;
+    pos[2] = dialog_tok;
+
+    pos += 3;
+    if (rep != MNULL && rep_len > 0U)
+    {
+        (void)memcpy(pos, rep, rep_len);
+        pos += rep_len;
+    }
+    meas_pkt_len           = pos - (t_u8 *)pmgmt_pkt_hdr;
+    pkt_len                = (t_u16)(meas_pkt_len);
+    pmgmt_pkt_hdr->frm_len = (t_u16)pkt_len - (t_u16)sizeof(t_u16);
+
+    /* Send packet */
+    (void)wifi_inject_frame(WLAN_BSS_TYPE_STA, (t_u8 *)pmgmt_pkt_hdr, pkt_len);
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+}
+
+void wlan_process_radio_measurement_request(t_u8 *frame, t_u32 len, t_u8 *dest_addr, t_u8 *src_addr, bool protect)
+{
+    t_u8 *pos = frame;
+    t_u8 dialog_tok;
+    bool duration_mandatory;
+
+    if (len < 3U)
+    {
+        wifi_d("Ignoring too short radio measurement request");
+        return;
+    }
+
+    dialog_tok = *pos;
+    /* Bypass dialog token and repetitions */
+    pos += 3;
+    len -= 3U;
+
+    /* Start process measurement quest */
+    mgmt_rrm_radio_meas_request *request = (mgmt_rrm_radio_meas_request *)(void *)pos;
+    if (request->ele_id != (t_u8)MEASURE_REQUEST)
+    {
+        wifi_d("eid %u is not radio measure request element", request->ele_id);
+        return;
+    }
+    if (request->length < 3U)
+    {
+        wifi_d("radio measure request element length too short");
+        return;
+    }
+    if (request->length > len - 2U)
+    {
+        wifi_d("radio measure request element length too long");
+        return;
+    }
+
+    duration_mandatory = !!((request->mode & WLAN_RRM_MEAS_REQUEST_MODE_DURATION_MANDATORY) != 0U);
+
+    switch (request->type)
+    {
+        /* Now only support beacon request */
+        case WLAN_RRM_MEASURE_TYPE_BEACON:
+            wlan_process_rm_beacon_req(request->variable, (t_u32)request->length - (t_u32)3, request->token, dialog_tok,
+                                       dest_addr, src_addr, protect, duration_mandatory);
+            break;
+        default:
+            wifi_d("radio measure request type %u is not supported", request->type);
+            break;
+    }
+}
+
+static void wlan_send_mgmt_link_measurement_report(
+    t_u8 *src_addr, t_u8 *dst_addr, t_u8 *rep, t_u32 rep_len, bool protect)
+{
+    wlan_mgmt_pkt *pmgmt_pkt_hdr    = MNULL;
+    IEEEtypes_FrameCtl_t *mgmt_fc_p = MNULL;
+    t_u8 *pos                       = MNULL;
+    t_u16 pkt_len                   = 0;
+    int meas_pkt_len                = 0;
+
+    pmgmt_pkt_hdr = wifi_PrepDefaultMgtMsg(
+        SUBTYPE_ACTION, (mlan_802_11_mac_addr *)(void *)dst_addr, (mlan_802_11_mac_addr *)(void *)src_addr,
+        (mlan_802_11_mac_addr *)(void *)dst_addr, sizeof(wlan_mgmt_pkt) + LINK_MSR_REPORT_BUF_SIZE);
+    if (pmgmt_pkt_hdr == MNULL)
+    {
+        wifi_d("No memory available for beacon report");
+        return;
+    }
+
+    mgmt_fc_p = (IEEEtypes_FrameCtl_t *)(void *)&pmgmt_pkt_hdr->wlan_header.frm_ctl;
+    if (protect)
+    {
+        mgmt_fc_p->wep = 1;
+    }
+
+    /* 802.11 management body */
+    pos    = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+    pos[0] = (t_u8)IEEE_MGMT_ACTION_CATEGORY_RADIO_RSRC;
+    pos[1] = (t_u8)IEEE_MGMT_RRM_LINK_MEASUREMENT_REPORT;
+    pos += 2;
+
+    if (rep != MNULL && rep_len > 0U)
+    {
+        (void)memcpy(pos, rep, rep_len);
+        pos += rep_len;
+    }
+    meas_pkt_len           = pos - (t_u8 *)pmgmt_pkt_hdr;
+    pkt_len                = (t_u16)meas_pkt_len;
+    pmgmt_pkt_hdr->frm_len = (t_u16)pkt_len - (t_u16)sizeof(t_u16);
+
+    /* Send packet */
+    (void)wifi_inject_frame(WLAN_BSS_TYPE_STA, (t_u8 *)pmgmt_pkt_hdr, pkt_len);
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+}
+
+void wlan_process_link_measurement_request(
+    t_u8 *frame, t_u32 len, t_u8 *dest_addr, t_u8 *src_addr, bool protect, RxPD *rxpd)
+{
+    mgmt_rrm_link_meas_request *request = (mgmt_rrm_link_meas_request *)(void *)frame;
+    mgmt_rrm_link_meas_report report;
+    t_u32 channel;
+    wifi_SubBand_t subband;
+    wlan_txpwrlimit_t *txpwrlimit = NULL;
+    t_u8 ModulationGroup          = 1; /* Default use OFDM modulation */
+    int meas_link_margin          = 0;
+    int meas_noise                = 0;
+
+    if (len < sizeof(mgmt_rrm_link_meas_request) - 1U)
+    {
+        wifi_d("Link measurement request too short");
+        return;
+    }
+
+    (void)memset(&report, 0, sizeof(report));
+    report.dialog_tok = request->dialog_tok;
+    meas_noise        = -((int)rxpd->nf + (int)rxpd->snr);
+    report.rsni       = (t_u8)(meas_noise);
+    report.rcpi       = wlan_rrm_rssi_to_rcpi((int)report.rsni);
+
+    /* TPC Report */
+    channel = mlan_adap->priv[0]->curr_bss_params.bss_descriptor.channel;
+    if (channel <= 14U)
+    {
+        subband = SubBand_2_4_GHz;
+        /* use CCK modulation */
+        ModulationGroup = 0;
+    }
+    else if (channel < 100U)
+    {
+        subband = SubBand_5_GHz_0;
+    }
+    else if (channel < 149U)
+    {
+        subband = SubBand_5_GHz_1;
+    }
+    else if (channel < 183U)
+    {
+        subband = SubBand_5_GHz_2;
+    }
+    else
+    {
+        subband = SubBand_5_GHz_3;
+    }
+
+#if !CONFIG_MEM_POOLS
+    txpwrlimit = OSA_MemoryAllocate(sizeof(wlan_txpwrlimit_t));
+#else
+    txpwrlimit = OSA_MemoryPoolAllocate(buf_2048_MemoryPool);
+#endif
+
+    if (txpwrlimit == NULL)
+    {
+        wifi_e("Cannot allocate memory for txpwrlimit");
+        return;
+    }
+
+    int rv = wlan_get_txpwrlimit(subband, txpwrlimit);
+    if (rv != WM_SUCCESS)
+    {
+        wifi_d("Unable to get TX PWR Limit configuration");
+    }
+    else
+    {
+        report.tpc_report.tx_power = (t_s8)wlan_link_measurement_get_tx_power(txpwrlimit, ModulationGroup, channel);
+    }
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(txpwrlimit);
+#else
+    OSA_MemoryPoolFree(buf_2048_MemoryPool, txpwrlimit);
+#endif
+
+    /* Default use CCK5_5Mbps */
+    meas_link_margin              = 78 - (int)report.rsni;
+    report.tpc_report.link_margin = (t_s8)meas_link_margin;
+    report.tpc_report.element_id  = TPC_REPORT;
+    report.tpc_report.len         = 2;
+
+    wlan_send_mgmt_link_measurement_report(dest_addr, src_addr, (t_u8 *)&report, sizeof(mgmt_rrm_link_meas_report) - 1U,
+                                           protect);
+}
+
+static bool wifi_find_in_channels(t_u8 *channels, t_u8 entry_num, t_u8 chan)
+{
+    t_u8 i;
+    for (i = 0; i < entry_num; i++)
+    {
+        if (channels[i] == chan)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+void wlan_process_neighbor_report_response(t_u8 *frame, t_u32 len, t_u8 *dest_addr, t_u8 *src_addr, bool protect)
+{
+    t_u8 *pos      = frame;
+    t_u8 entry_num = 0, chan;
+#if !CONFIG_MEM_POOLS
+    wlan_nlist_report_param *pnlist_rep_param =
+        (wlan_nlist_report_param *)OSA_MemoryAllocate(sizeof(wlan_nlist_report_param));
+#else
+    wlan_nlist_report_param *pnlist_rep_param = (wlan_nlist_report_param *)OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+
+    wifi_d("Neighbor report event");
+#if CONFIG_WIFI_EXTRA_DEBUG
+    dump_hex(frame, len);
+#endif
+    if (pnlist_rep_param == MNULL)
+    {
+        wifi_e("11k nlist report param buffer alloc failed %d", sizeof(wlan_nlist_report_param));
+        return;
+    }
+
+    if (len < 3U)
+    {
+        wifi_d("Ignoring too short radio measurement request");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+        return;
+    }
+
+    memset(pnlist_rep_param, 0, sizeof(wlan_nlist_report_param));
+    /* Bypass dialog token */
+    pos += 1;
+    len -= 1U;
+
+    /* Start process neighbor report response */
+
+#define NR_IE_MIN_LEN            (IEEEtypes_ADDRESS_SIZE + 4 + 1 + 1 + 1)
+#define WLAN_EID_NEIGHBOR_REPORT 52
+
+    while (len >= 2 + NR_IE_MIN_LEN)
+    {
+        t_u8 nr_len = pos[1];
+
+        if (pos[0] != WLAN_EID_NEIGHBOR_REPORT || nr_len < NR_IE_MIN_LEN)
+        {
+            wifi_d("Invalid Neighbor Report element: id=%u len=%u", pos[0], nr_len);
+            goto out;
+        }
+
+        if (2U + nr_len > len)
+        {
+            wifi_d("Invalid Neighbor Report element: id=%u len=%zu nr_len=%u", pos[0], len, nr_len);
+            goto out;
+        }
+        pos += 2;
+
+        chan = pos[IEEEtypes_ADDRESS_SIZE + 5];
+
+        wifi_d("channel = %d", chan);
+        if (!wifi_find_in_channels(pnlist_rep_param->channels, entry_num, chan))
+        {
+            pnlist_rep_param->channels[entry_num] = chan;
+            entry_num++;
+        }
+
+        pos += nr_len;
+        len -= 2 + nr_len;
+    }
+
+    if (entry_num == 0U)
+    {
+        goto out;
+    }
+
+    pnlist_rep_param->nlist_mode   = WLAN_NLIST_11K;
+    pnlist_rep_param->num_channels = entry_num;
+
+    if (wifi_event_completion(WIFI_EVENT_NLIST_REPORT, WIFI_EVENT_REASON_SUCCESS, pnlist_rep_param) != WM_SUCCESS)
+    {
+        /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+    }
+    return;
+
+out:
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+}
+
+/**
+ * @brief This function sets up the RRM Enabled Capabilites IE.
+ *
+ * @param pRrmCapIe A pointer to Rrm Enabled Capabilities element structure
+ * @param bcnInterval Beacon interval
+ *
+ * @return void
+ */
+void wlan_dot11k_formatRrmCapabilities(IEEEtypes_RrmEnabledCapabilities_t *pRrmCapIe, t_u16 bcnInterval)
+{
+    (void)memset((void *)pRrmCapIe, 0x00, sizeof(IEEEtypes_RrmEnabledCapabilities_t));
+
+    pRrmCapIe->LinkMeas       = 1;
+    pRrmCapIe->NborRpt        = 1;
+    pRrmCapIe->BcnPassiveMeas = 1;
+    pRrmCapIe->BcnActiveMeas  = 1;
+    pRrmCapIe->BcnTableMeas   = 1;
+    pRrmCapIe->TxStreamMeas   = 1;
+
+    pRrmCapIe->OpChanMaxMeas    = 4; /* TBD: copy the result from fw dot11k_getRmMeasMax() */
+    pRrmCapIe->NonOpChanMaxMeas = 2; /* TBD: copy the result from fw dot11k_getRmMeasMax() */
+
+    pRrmCapIe->ParallelMeas = 0;
+    pRrmCapIe->RepeatMeas   = 0;
+}
+
+int wlan_send_mgmt_rm_neighbor_request(mlan_private *pmpriv, t_u8 *ssid, t_u8 ssid_len)
+{
+    t_u16 pkt_len;
+    mlan_802_11_mac_addr *da     = MNULL;
+    mlan_802_11_mac_addr *sa     = MNULL;
+    wlan_mgmt_pkt *pmgmt_pkt_hdr = MNULL;
+    t_u8 *pos                    = MNULL;
+    int meas_pkt_len             = 0;
+
+    if (pmpriv->bss_index != (t_u8)MLAN_BSS_ROLE_STA || pmpriv->media_connected != MTRUE)
+    {
+        wifi_d("invalid interface %d for sending neighbor report request", pmpriv->bss_index);
+        return (int)MLAN_STATUS_FAILURE;
+    }
+
+    da = &pmpriv->curr_bss_params.bss_descriptor.mac_address;
+    sa = (mlan_802_11_mac_addr *)(void *)(&pmpriv->curr_addr[0]);
+    pmgmt_pkt_hdr =
+        wifi_PrepDefaultMgtMsg(SUBTYPE_ACTION, da, sa, da, sizeof(wlan_mgmt_pkt) + NEIGHBOR_REQUEST_BUF_SIZE);
+    if (pmgmt_pkt_hdr == MNULL)
+    {
+        wifi_e("No memory for neighbor report request");
+        return (int)MLAN_STATUS_FAILURE;
+    }
+
+    /* 802.11 management body */
+    pos    = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+    pos[0] = (t_u8)IEEE_MGMT_ACTION_CATEGORY_RADIO_RSRC;
+    pos[1] = (t_u8)IEEE_MGMT_RRM_NEIGHBOR_REPORT_REQUEST;
+    pos[2] = pmpriv->neighbor_rep_token++;
+
+    if (pmpriv->neighbor_rep_token == (t_u8)255U)
+    {
+        pmpriv->neighbor_rep_token = (t_u8)1U;
+    }
+
+    pos += 3;
+
+    /* SSID Tag */
+    if (ssid_len > (t_u8)0U)
+    {
+        pos[0] = (t_u8)SSID;
+        pos[1] = ssid_len;
+        (void)memcpy(&pos[2], ssid, ssid_len);
+        pos += ssid_len + 2U;
+    }
+
+    meas_pkt_len           = pos - (t_u8 *)pmgmt_pkt_hdr;
+    pkt_len                = (t_u16)meas_pkt_len;
+    pmgmt_pkt_hdr->frm_len = pkt_len - (t_u16)sizeof(pmgmt_pkt_hdr->frm_len);
+
+    (void)wifi_inject_frame(WLAN_BSS_TYPE_STA, (t_u8 *)pmgmt_pkt_hdr, pkt_len);
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+
+    return (int)MLAN_STATUS_SUCCESS;
+}
+#endif /* CONFIG_11K */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n.c
new file mode 100644
index 0000000000..7f170ffd5a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n.c
@@ -0,0 +1,1654 @@
+/** @file mlan_11n.c
+ *
+ *  @brief  This file provides functions for 11n handling.
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    11/10/2008: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+    Local Variables
+********************************************************/
+
+/********************************************************
+    Global Variables
+********************************************************/
+
+/********************************************************
+    Local Functions
+********************************************************/
+
+/* Disable the optional features of 11N */
+#undef _80211n_OPT_FEATURES
+
+
+
+/**
+ *  @brief Set/get htcapinfo configuration
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return				MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_11n_ioctl_htusrcfg(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_11n_cfg *cfg = MNULL;
+
+    ENTER();
+
+    cfg = (mlan_ds_11n_cfg *)(void *)pioctl_req->pbuf;
+
+    if (pioctl_req->action == MLAN_ACT_SET)
+    {
+        if (((cfg->param.htcap_cfg.htcap & ~IGN_HW_DEV_CAP) & pmpriv->adapter->hw_dot_11n_dev_cap) !=
+            (cfg->param.htcap_cfg.htcap & ~IGN_HW_DEV_CAP))
+        {
+            pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+            ret                     = MLAN_STATUS_FAILURE;
+        }
+        else
+        {
+            if (cfg->param.htcap_cfg.misc_cfg == BAND_SELECT_BG)
+            {
+                pmadapter->usr_dot_11n_dev_cap_bg = cfg->param.htcap_cfg.htcap;
+                PRINTM(MINFO, "Set: UsrDot11nCap for 2.4GHz 0x%x\n", pmadapter->usr_dot_11n_dev_cap_bg);
+            }
+            if (cfg->param.htcap_cfg.misc_cfg == BAND_SELECT_A)
+            {
+                pmadapter->usr_dot_11n_dev_cap_a = cfg->param.htcap_cfg.htcap;
+                PRINTM(MINFO, "Set: UsrDot11nCap for 5GHz 0x%x\n", pmadapter->usr_dot_11n_dev_cap_a);
+            }
+            if (cfg->param.htcap_cfg.misc_cfg == BAND_SELECT_BOTH)
+            {
+                pmadapter->usr_dot_11n_dev_cap_bg = cfg->param.htcap_cfg.htcap;
+                pmadapter->usr_dot_11n_dev_cap_a  = cfg->param.htcap_cfg.htcap;
+                PRINTM(MINFO, "Set: UsrDot11nCap for 2.4GHz and 5GHz 0x%x\n", cfg->param.htcap_cfg.htcap);
+            }
+        }
+    }
+    else
+    {
+        /* Hardware 11N device capability required */
+        if (cfg->param.htcap_cfg.hw_cap_req != 0U)
+        {
+            cfg->param.htcap_cfg.htcap = pmadapter->hw_dot_11n_dev_cap;
+        }
+        else
+        {
+            if (cfg->param.htcap_cfg.misc_cfg == BAND_SELECT_BG)
+            {
+                cfg->param.htcap_cfg.htcap = pmadapter->usr_dot_11n_dev_cap_bg;
+                PRINTM(MINFO, "Get: UsrDot11nCap for 2.4GHz 0x%x\n", cfg->param.htcap_cfg.htcap);
+            }
+            if (cfg->param.htcap_cfg.misc_cfg == BAND_SELECT_A)
+            {
+                cfg->param.htcap_cfg.htcap = pmadapter->usr_dot_11n_dev_cap_a;
+                PRINTM(MINFO, "Get: UsrDot11nCap for 5GHz 0x%x\n", cfg->param.htcap_cfg.htcap);
+            }
+        }
+    }
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief Set/get 11n configuration
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_11n_ioctl_httxcfg(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_11n_cfg *cfg = MNULL;
+    t_u16 cmd_action     = 0;
+
+    ENTER();
+
+    cfg = (mlan_ds_11n_cfg *)(void *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+    {
+        cmd_action = HostCmd_ACT_GEN_SET;
+    }
+    else
+    {
+        cmd_action = HostCmd_ACT_GEN_GET;
+    }
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_11N_CFG, cmd_action, 0, (t_void *)pioctl_req,
+                           (t_void *)&cfg->param.tx_cfg);
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief This function will send DELBA to entries in the priv's
+ *          Tx BA stream table
+ *
+ *  @param priv                 A pointer to mlan_private
+ *  @param pioctl_req          A pointer to ioctl request buffer
+ *  @param tid                  TID
+ *  @param peer_address         A pointer to peer address
+ *  @param last_tx_ba_to_delete A pointer to the last entry in TxBAStreamTbl
+ *
+ *  @return            MLAN_STATUS_SUCCESS or MLAN_STATUS_PENDING
+ */
+static mlan_status wlan_send_delba_to_entry_in_txbastream_tbl(
+    pmlan_private priv, pmlan_ioctl_req pioctl_req, t_u8 tid, t_u8 *peer_address, TxBAStreamTbl *last_tx_ba_to_delete)
+{
+    pmlan_adapter pmadapter = priv->adapter;
+    TxBAStreamTbl *tx_ba_stream_tbl_ptr;
+    t_u8 zero_mac[MLAN_MAC_ADDR_LENGTH] = {0};
+    mlan_status ret                     = MLAN_STATUS_SUCCESS;
+    int i;
+
+    ENTER();
+
+    wlan_request_ralist_lock(priv);
+    tx_ba_stream_tbl_ptr =
+        (TxBAStreamTbl *)util_peek_list(pmadapter->pmoal_handle, &priv->tx_ba_stream_tbl_ptr, MNULL, MNULL);
+    if (!tx_ba_stream_tbl_ptr)
+    {
+        wlan_release_ralist_lock(priv);
+        LEAVE();
+        return ret;
+    }
+
+    if (__memcmp(pmadapter, peer_address, zero_mac, MLAN_MAC_ADDR_LENGTH))
+    {
+        if (!wlan_11n_get_txbastream_tbl(priv, peer_address))
+            return MLAN_STATUS_FAILURE;
+    }
+
+    while (tx_ba_stream_tbl_ptr != (TxBAStreamTbl *)&priv->tx_ba_stream_tbl_ptr)
+    {
+        if (tx_ba_stream_tbl_ptr->ba_status == BA_STREAM_SETUP_COMPLETE)
+        {
+            if (__memcmp(pmadapter, peer_address, zero_mac, MLAN_MAC_ADDR_LENGTH) &&
+                !__memcmp(pmadapter, peer_address, tx_ba_stream_tbl_ptr->ra, MLAN_MAC_ADDR_LENGTH))
+            {
+                tx_ba_stream_tbl_ptr = wlan_11n_get_txbastream_tbl(priv, peer_address);
+
+                if (tid == DELBA_ALL_TIDS)
+                {
+                    for (i = 0; i < MAX_NUM_TID; i++)
+                    {
+                        if (tx_ba_stream_tbl_ptr->ampdu_stat[i])
+                        {
+                            if (last_tx_ba_to_delete && (tx_ba_stream_tbl_ptr == last_tx_ba_to_delete))
+                                ret = wlan_send_delba(priv, pioctl_req, i, tx_ba_stream_tbl_ptr->ra, 1);
+                            else
+                                ret = wlan_send_delba(priv, MNULL, i, tx_ba_stream_tbl_ptr->ra, 1);
+                        }
+                    }
+                }
+                else
+                {
+                    if (tx_ba_stream_tbl_ptr->ampdu_stat[tid])
+                    {
+                        if (last_tx_ba_to_delete && (tx_ba_stream_tbl_ptr == last_tx_ba_to_delete))
+                            ret = wlan_send_delba(priv, pioctl_req, tid, tx_ba_stream_tbl_ptr->ra, 1);
+                        else
+                            ret = wlan_send_delba(priv, MNULL, tid, tx_ba_stream_tbl_ptr->ra, 1);
+                    }
+                }
+
+                return ret;
+            }
+            else
+            {
+                if (tid == DELBA_ALL_TIDS)
+                {
+                    for (i = 0; i < MAX_NUM_TID; i++)
+                    {
+                        if (tx_ba_stream_tbl_ptr->ampdu_stat[i])
+                        {
+                            if (last_tx_ba_to_delete && (tx_ba_stream_tbl_ptr == last_tx_ba_to_delete))
+                                ret = wlan_send_delba(priv, pioctl_req, i, tx_ba_stream_tbl_ptr->ra, 1);
+                            else
+                                ret = wlan_send_delba(priv, MNULL, i, tx_ba_stream_tbl_ptr->ra, 1);
+                        }
+                    }
+                }
+                else
+                {
+                    if (tx_ba_stream_tbl_ptr->ampdu_stat[tid])
+                    {
+                        if (last_tx_ba_to_delete && (tx_ba_stream_tbl_ptr == last_tx_ba_to_delete))
+                            ret = wlan_send_delba(priv, pioctl_req, tid, tx_ba_stream_tbl_ptr->ra, 1);
+                        else
+                            ret = wlan_send_delba(priv, MNULL, tid, tx_ba_stream_tbl_ptr->ra, 1);
+                    }
+                }
+            }
+        }
+
+        tx_ba_stream_tbl_ptr = tx_ba_stream_tbl_ptr->pnext;
+    }
+    wlan_release_ralist_lock(priv);
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function will send DELBA to entries in the priv's
+ *          rx reordering table
+ *
+ *  @param priv                 A pointer to mlan_private
+ *  @param pioctl_req          A pointer to ioctl request buffer
+ *  @param tid                  TID
+ *  @param peer_address         A pointer to peer address
+ *  @param last_rx_ba_to_delete A pointer to the last entry in RxReorderTbl
+ *
+ *  @return            MLAN_STATUS_SUCCESS or MLAN_STATUS_PENDING
+ */
+static mlan_status wlan_send_delba_to_entry_in_reorder_tbl(
+    pmlan_private priv, pmlan_ioctl_req pioctl_req, t_u8 tid, t_u8 *peer_address, RxReorderTbl *last_rx_ba_to_delete)
+{
+    pmlan_adapter pmadapter = priv->adapter;
+    RxReorderTbl *rx_reor_tbl_ptr;
+    RxReorderTbl *next_rx_reor_tbl_ptr;
+    t_u8 zero_mac[MLAN_MAC_ADDR_LENGTH] = {0};
+    mlan_status ret                     = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    rx_reor_tbl_ptr =
+        (RxReorderTbl *)util_peek_list(pmadapter->pmoal_handle, &priv->rx_reorder_tbl_ptr,
+                                       pmadapter->callbacks.moal_spin_lock, pmadapter->callbacks.moal_spin_unlock);
+    if (!rx_reor_tbl_ptr)
+    {
+        LEAVE();
+        return ret;
+    }
+
+    next_rx_reor_tbl_ptr = rx_reor_tbl_ptr->pnext;
+
+    while (rx_reor_tbl_ptr != (RxReorderTbl *)&priv->rx_reorder_tbl_ptr)
+    {
+        if (rx_reor_tbl_ptr->ba_status == BA_STREAM_SETUP_COMPLETE)
+        {
+            if (((tid == DELBA_ALL_TIDS) || (tid == rx_reor_tbl_ptr->tid)) &&
+                (!__memcmp(pmadapter, peer_address, zero_mac, MLAN_MAC_ADDR_LENGTH) ||
+                 !__memcmp(pmadapter, peer_address, rx_reor_tbl_ptr->ta, MLAN_MAC_ADDR_LENGTH)))
+            {
+                if (last_rx_ba_to_delete && (rx_reor_tbl_ptr == last_rx_ba_to_delete))
+                    ret = wlan_send_delba(priv, pioctl_req, rx_reor_tbl_ptr->tid, rx_reor_tbl_ptr->ta, 0);
+                else
+                    ret = wlan_send_delba(priv, MNULL, rx_reor_tbl_ptr->tid, rx_reor_tbl_ptr->ta, 0);
+            }
+        }
+
+        rx_reor_tbl_ptr = next_rx_reor_tbl_ptr;
+
+        next_rx_reor_tbl_ptr = rx_reor_tbl_ptr->pnext;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief IOCTL to delete BA
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return			MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_11n_ioctl_delba(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_11n_cfg *cfg = MNULL;
+    TxBAStreamTbl *tx_ba_stream_tbl_ptr, *last_tx_ba_to_delete = MNULL;
+    RxReorderTbl *rx_reor_tbl_ptr, *last_rx_ba_to_delete       = MNULL;
+    t_u8 zero_mac[MLAN_MAC_ADDR_LENGTH] = {0};
+    t_u8 tid, *peer_address;
+
+    ENTER();
+
+    cfg          = (mlan_ds_11n_cfg *)pioctl_req->pbuf;
+    tid          = cfg->param.del_ba.tid;
+    peer_address = cfg->param.del_ba.peer_mac_addr;
+
+    PRINTM(MINFO, "DelBA: direction %d, TID %d, peer address " MACSTR "\n", cfg->param.del_ba.direction, tid,
+           MAC2STR(peer_address));
+
+    if (cfg->param.del_ba.direction & DELBA_RX)
+    {
+        rx_reor_tbl_ptr =
+            (RxReorderTbl *)util_peek_list(pmadapter->pmoal_handle, &pmpriv->rx_reorder_tbl_ptr,
+                                           pmadapter->callbacks.moal_spin_lock, pmadapter->callbacks.moal_spin_unlock);
+
+        if (rx_reor_tbl_ptr)
+        {
+            while (rx_reor_tbl_ptr != (RxReorderTbl *)&pmpriv->rx_reorder_tbl_ptr)
+            {
+                if (rx_reor_tbl_ptr->ba_status == BA_STREAM_SETUP_COMPLETE)
+                {
+                    if (((tid == DELBA_ALL_TIDS) || (tid == rx_reor_tbl_ptr->tid)) &&
+                        (!__memcmp(pmadapter, peer_address, zero_mac, MLAN_MAC_ADDR_LENGTH) ||
+                         !__memcmp(pmadapter, peer_address, rx_reor_tbl_ptr->ta, MLAN_MAC_ADDR_LENGTH)))
+                    {
+                        /* Found RX BA to delete */
+                        last_rx_ba_to_delete = rx_reor_tbl_ptr;
+                    }
+                }
+                rx_reor_tbl_ptr = rx_reor_tbl_ptr->pnext;
+            }
+        }
+    }
+
+    if ((last_rx_ba_to_delete == MNULL) && (cfg->param.del_ba.direction & DELBA_TX))
+    {
+        wlan_request_ralist_lock(pmpriv);
+        tx_ba_stream_tbl_ptr =
+            (TxBAStreamTbl *)util_peek_list(pmadapter->pmoal_handle, &pmpriv->tx_ba_stream_tbl_ptr, MNULL, MNULL);
+
+        if (tx_ba_stream_tbl_ptr)
+        {
+            while (tx_ba_stream_tbl_ptr != (TxBAStreamTbl *)&pmpriv->tx_ba_stream_tbl_ptr)
+            {
+                if (tx_ba_stream_tbl_ptr->ba_status == BA_STREAM_SETUP_COMPLETE)
+                {
+                    if (((tid == DELBA_ALL_TIDS) || (tx_ba_stream_tbl_ptr->ampdu_stat[tid])) &&
+                        (!__memcmp(pmadapter, peer_address, zero_mac, MLAN_MAC_ADDR_LENGTH) ||
+                         !__memcmp(pmadapter, peer_address, tx_ba_stream_tbl_ptr->ra, MLAN_MAC_ADDR_LENGTH)))
+                    {
+                        /* Found TX BA to delete */
+                        last_tx_ba_to_delete = tx_ba_stream_tbl_ptr;
+                    }
+                }
+                tx_ba_stream_tbl_ptr = tx_ba_stream_tbl_ptr->pnext;
+            }
+        }
+        wlan_release_ralist_lock(pmpriv);
+    }
+
+    if (cfg->param.del_ba.direction & DELBA_TX)
+    {
+        if (last_rx_ba_to_delete)
+            ret = wlan_send_delba_to_entry_in_txbastream_tbl(pmpriv, MNULL, tid, peer_address, MNULL);
+        else
+            ret =
+                wlan_send_delba_to_entry_in_txbastream_tbl(pmpriv, pioctl_req, tid, peer_address, last_tx_ba_to_delete);
+    }
+    if (last_rx_ba_to_delete)
+    {
+        ret = wlan_send_delba_to_entry_in_reorder_tbl(pmpriv, pioctl_req, tid, peer_address, last_rx_ba_to_delete);
+    }
+
+    LEAVE();
+    return ret;
+}
+
+
+/********************************************************
+    Global Functions
+********************************************************/
+
+/**
+ *  @brief This function fills the cap info
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param pht_cap      A pointer to MrvlIETypes_HTCap_t structure
+ *  @param bands        Band configuration
+ *
+ *  @return             N/A
+ */
+static void wlan_fill_cap_info(mlan_private *priv, MrvlIETypes_HTCap_t *pht_cap, t_u16 bands)
+{
+    mlan_adapter *pmadapter = priv->adapter;
+    t_u32 usr_dot_11n_dev_cap;
+
+    ENTER();
+
+#if CONFIG_5GHz_SUPPORT
+    if ((bands & BAND_A) != 0U)
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_a;
+    }
+    else
+#endif
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_bg;
+    }
+
+    if (ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_SUPPCHANWIDTH(pht_cap->ht_cap.ht_cap_info);
+        SETHT_DSSSCCK40(pht_cap->ht_cap.ht_cap_info);
+    }
+    else
+    {
+        RESETHT_SUPPCHANWIDTH(pht_cap->ht_cap.ht_cap_info);
+        RESETHT_DSSSCCK40(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    if (ISSUPP_GREENFIELD(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_GREENFIELD(pht_cap->ht_cap.ht_cap_info);
+    }
+    else
+    {
+        RESETHT_GREENFIELD(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    if (ISSUPP_SHORTGI20(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_SHORTGI20(pht_cap->ht_cap.ht_cap_info);
+    }
+    else
+    {
+        RESETHT_SHORTGI20(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    if (ISSUPP_SHORTGI40(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_SHORTGI40(pht_cap->ht_cap.ht_cap_info);
+    }
+    else
+    {
+        RESETHT_SHORTGI40(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    if (ISSUPP_RXSTBC(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_RXSTBC(pht_cap->ht_cap.ht_cap_info, 1U);
+    }
+    else
+    {
+        RESETHT_RXSTBC(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    if (ISENABLED_40MHZ_INTOLARENT(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_40MHZ_INTOLARANT(pht_cap->ht_cap.ht_cap_info);
+    }
+    else
+    {
+        RESETHT_40MHZ_INTOLARANT(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    /* No user config for LDPC coding capability yet */
+    if (ISSUPP_RXLDPC(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_LDPCCODINGCAP(pht_cap->ht_cap.ht_cap_info);
+    }
+    else
+    {
+        RESETHT_LDPCCODINGCAP(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    /* No user config for TX STBC yet */
+    if (ISSUPP_TXSTBC(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_TXSTBC(pht_cap->ht_cap.ht_cap_info);
+    }
+    else
+    {
+        RESETHT_TXSTBC(pht_cap->ht_cap.ht_cap_info);
+    }
+
+    /* No user config for Delayed BACK yet */
+    RESETHT_DELAYEDBACK(pht_cap->ht_cap.ht_cap_info);
+
+    /* Need change to support 8k AMSDU receive */
+    RESETHT_MAXAMSDU(pht_cap->ht_cap.ht_cap_info);
+
+    /* SM power save */
+    if (ISSUPP_MIMOPS(priv->adapter->hw_dot_11n_dev_cap) != 0U)
+    {
+        RESETHT_SM_POWERSAVE(pht_cap->ht_cap.ht_cap_info); /* Enable HT SMPS*/
+    }
+    else
+    {
+        SETHT_STATIC_SMPS(pht_cap->ht_cap.ht_cap_info); /* Disable HT SMPS */
+    }
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function fills the HT cap tlv
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param pht_cap      A pointer to MrvlIETypes_HTCap_t structure
+ *  @param bands        Band configuration
+ *
+ *  @return             N/A
+ */
+void wlan_fill_ht_cap_tlv(mlan_private *priv, MrvlIETypes_HTCap_t *pht_cap, t_u16 bands)
+{
+    mlan_adapter *pmadapter = priv->adapter;
+    int rx_mcs_supp;
+    t_u32 usr_dot_11n_dev_cap;
+
+    ENTER();
+
+#if CONFIG_5GHz_SUPPORT
+    if ((bands & BAND_A) != 0U)
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_a;
+    }
+    else
+#endif
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_bg;
+    }
+
+    /* Fill HT cap info */
+    wlan_fill_cap_info(priv, pht_cap, bands);
+    pht_cap->ht_cap.ht_cap_info = wlan_cpu_to_le16(pht_cap->ht_cap.ht_cap_info);
+
+    /* Set ampdu param */
+    SETAMPDU_SIZE(pht_cap->ht_cap.ampdu_param, AMPDU_FACTOR_64K);
+
+#ifdef RW610_SERIES
+    SETAMPDU_SPACING(pht_cap->ht_cap.ampdu_param, 0x5);
+#else
+    SETAMPDU_SPACING(pht_cap->ht_cap.ampdu_param, pmadapter->hw_mpdu_density);
+#endif
+
+    rx_mcs_supp = GET_RXMCSSUPP(pmadapter->usr_dev_mcs_support);
+    /* Set MCS for 1x1/2x2 */
+    (void)__memset(pmadapter, (t_u8 *)pht_cap->ht_cap.supported_mcs_set, 0xff, rx_mcs_supp);
+    /* Clear all the other values */
+    (void)__memset(pmadapter, (t_u8 *)&pht_cap->ht_cap.supported_mcs_set[rx_mcs_supp], 0, NUM_MCS_FIELD - rx_mcs_supp);
+    /* Set MCS32 with 40MHz support */
+    /* if current channel only support 20MHz, we should not set 40Mz supprot*/
+    if (ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_MCS32(pht_cap->ht_cap.supported_mcs_set);
+    }
+
+    /* Clear RD responder bit */
+    RESETHT_EXTCAP_RDG(pht_cap->ht_cap.ht_ext_cap);
+    pht_cap->ht_cap.ht_ext_cap = wlan_cpu_to_le16(pht_cap->ht_cap.ht_ext_cap);
+
+    /* Set Tx BF cap */
+    pht_cap->ht_cap.tx_bf_cap = wlan_cpu_to_le32(priv->tx_bf_cap);
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function prints the 802.11n device capability
+ *
+ *  @param pmadapter     A pointer to mlan_adapter structure
+ *  @param cap           Capability value
+ *
+ *  @return        N/A
+ */
+void wlan_show_dot11ndevcap(pmlan_adapter pmadapter, t_u32 cap)
+{
+    ENTER();
+
+    PRINTM(MINFO, "GET_HW_SPEC: Maximum MSDU length = %s octets\n", (ISSUPP_MAXAMSDU(cap) ? "7935" : "3839"));
+    PRINTM(MINFO, "GET_HW_SPEC: Beam forming %s\n", (ISSUPP_BEAMFORMING(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Greenfield preamble %s\n", (ISSUPP_GREENFIELD(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: AMPDU %s\n", (ISSUPP_AMPDU(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: MIMO Power Save %s\n", (ISSUPP_MIMOPS(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Rx STBC %s\n", (ISSUPP_RXSTBC(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Tx STBC %s\n", (ISSUPP_TXSTBC(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Short GI for 40 Mhz %s\n", (ISSUPP_SHORTGI40(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Short GI for 20 Mhz %s\n", (ISSUPP_SHORTGI20(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: LDPC coded packet receive %s\n", (ISSUPP_RXLDPC(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: Number of TX BA streams supported %d\n", ISSUPP_GETTXBASTREAM(cap));
+    PRINTM(MINFO, "GET_HW_SPEC: 40 Mhz channel width %s\n", (ISSUPP_CHANWIDTH40(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: 20 Mhz channel width %s\n", (ISSUPP_CHANWIDTH20(cap) ? "supported" : "not supported"));
+    PRINTM(MINFO, "GET_HW_SPEC: 10 Mhz channel width %s\n", (ISSUPP_CHANWIDTH10(cap) ? "supported" : "not supported"));
+
+    if (ISSUPP_RXANTENNAA(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Rx antenna A\n");
+    }
+    if (ISSUPP_RXANTENNAB(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Rx antenna B\n");
+    }
+    if (ISSUPP_RXANTENNAC(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Rx antenna C\n");
+    }
+    if (ISSUPP_RXANTENNAD(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Rx antenna D\n");
+    }
+    if (ISSUPP_TXANTENNAA(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Tx antenna A\n");
+    }
+    if (ISSUPP_TXANTENNAB(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Tx antenna B\n");
+    }
+    if (ISSUPP_TXANTENNAC(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Tx antenna C\n");
+    }
+    if (ISSUPP_TXANTENNAD(cap) != 0U)
+    {
+        PRINTM(MINFO, "GET_HW_SPEC: Presence of Tx antenna D\n");
+    }
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function prints the 802.11n device MCS
+ *
+ *  @param pmadapter A pointer to mlan_adapter structure
+ *  @param support   Support value
+ *
+ *  @return        N/A
+ */
+void wlan_show_devmcssupport(pmlan_adapter pmadapter, t_u8 support)
+{
+    ENTER();
+
+    PRINTM(MINFO, "GET_HW_SPEC: MCSs for %dx%d MIMO\n", GET_RXMCSSUPP(support), GET_TXMCSSUPP(support));
+
+    LEAVE();
+    return;
+}
+
+
+/**
+ *  @brief This function prepares command of reconfigure tx buf
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_recfg_tx_buf(mlan_private *priv, HostCmd_DS_COMMAND *cmd, int cmd_action, void *pdata_buf)
+{
+    HostCmd_DS_TXBUF_CFG *ptx_buf = &cmd->params.tx_buf;
+    t_u16 action                  = (t_u16)cmd_action;
+    t_u16 buf_size                = *((t_u16 *)pdata_buf);
+
+    ENTER();
+    cmd->command    = wlan_cpu_to_le16(HostCmd_CMD_RECONFIGURE_TX_BUFF);
+    cmd->size       = wlan_cpu_to_le16(sizeof(HostCmd_DS_TXBUF_CFG) + S_DS_GEN);
+    ptx_buf->action = wlan_cpu_to_le16(action);
+    switch (action)
+    {
+        case HostCmd_ACT_GEN_SET:
+            PRINTM(MCMND, "set tx_buf = %d\n", buf_size);
+            ptx_buf->buff_size = wlan_cpu_to_le16(buf_size);
+            break;
+        case HostCmd_ACT_GEN_GET:
+        default:
+            ptx_buf->buff_size = 0;
+            break;
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of amsdu aggr control
+ *
+ *  @param priv         A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_amsdu_aggr_ctrl(mlan_private *priv, HostCmd_DS_COMMAND *cmd, int cmd_action, void *pdata_buf)
+{
+    HostCmd_DS_AMSDU_AGGR_CTRL *pamsdu_ctrl = &cmd->params.amsdu_aggr_ctrl;
+    t_u16 action                            = (t_u16)cmd_action;
+    mlan_ds_11n_amsdu_aggr_ctrl *aa_ctrl    = (mlan_ds_11n_amsdu_aggr_ctrl *)pdata_buf;
+
+    ENTER();
+
+    cmd->command        = wlan_cpu_to_le16(HostCmd_CMD_AMSDU_AGGR_CTRL);
+    cmd->size           = wlan_cpu_to_le16(sizeof(HostCmd_DS_AMSDU_AGGR_CTRL) + S_DS_GEN);
+    pamsdu_ctrl->action = wlan_cpu_to_le16(action);
+    switch (action)
+    {
+        case HostCmd_ACT_GEN_SET:
+            pamsdu_ctrl->enable        = wlan_cpu_to_le16(aa_ctrl->enable);
+            pamsdu_ctrl->curr_buf_size = 0;
+            break;
+        case HostCmd_ACT_GEN_GET:
+        default:
+            pamsdu_ctrl->curr_buf_size = 0;
+            break;
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of amsdu aggr ctrl
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS
+ */
+#if CONFIG_AMSDU_IN_AMPDU
+mlan_status wlan_ret_amsdu_aggr_ctrl(IN pmlan_private pmpriv,
+                                     IN HostCmd_DS_COMMAND *resp,
+                                     IN mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_11n_cfg *cfg                   = MNULL;
+    HostCmd_DS_AMSDU_AGGR_CTRL *amsdu_ctrl = &resp->params.amsdu_aggr_ctrl;
+
+    ENTER();
+
+
+    if (pioctl_buf != NULL)
+    {
+        cfg                                      = (mlan_ds_11n_cfg *)(void *)pioctl_buf->pbuf;
+        cfg->param.amsdu_aggr_ctrl.enable        = wlan_le16_to_cpu(amsdu_ctrl->enable);
+        cfg->param.amsdu_aggr_ctrl.curr_buf_size = wlan_le16_to_cpu(amsdu_ctrl->curr_buf_size);
+    }
+    pmpriv->is_amsdu_enabled = wlan_le16_to_cpu(amsdu_ctrl->enable);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/**
+ *  @brief This function prepares 11n cfg command
+ *
+ *  @param pmpriv    	A pointer to mlan_private structure
+ *  @param cmd	   	A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action 	the action: GET or SET
+ *  @param pdata_buf 	A pointer to data buffer
+ *  @return 	   	MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_11n_cfg(IN pmlan_private pmpriv,
+                             IN HostCmd_DS_COMMAND *cmd,
+                             IN t_u16 cmd_action,
+                             IN t_void *pdata_buf)
+{
+    HostCmd_DS_11N_CFG *htcfg = &cmd->params.htcfg;
+    mlan_ds_11n_tx_cfg *txcfg = (mlan_ds_11n_tx_cfg *)pdata_buf;
+
+    ENTER();
+    cmd->command       = wlan_cpu_to_le16(HostCmd_CMD_11N_CFG);
+    cmd->size          = wlan_cpu_to_le16(sizeof(HostCmd_DS_11N_CFG) + S_DS_GEN);
+    htcfg->action      = wlan_cpu_to_le16(cmd_action);
+    htcfg->ht_tx_cap   = wlan_cpu_to_le16(txcfg->httxcap);
+    htcfg->ht_tx_info  = wlan_cpu_to_le16(txcfg->httxinfo);
+    htcfg->misc_config = wlan_cpu_to_le16(txcfg->misc_cfg);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of 11ncfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_11n_cfg(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_11n_cfg *cfg      = MNULL;
+    HostCmd_DS_11N_CFG *htcfg = &resp->params.htcfg;
+
+
+    ENTER();
+    if (pioctl_buf != MNULL && (wlan_le16_to_cpu(htcfg->action) == HostCmd_ACT_GEN_GET))
+    {
+        cfg                        = (mlan_ds_11n_cfg *)(void *)pioctl_buf->pbuf;
+        cfg->param.tx_cfg.httxcap  = wlan_le16_to_cpu(htcfg->ht_tx_cap);
+        cfg->param.tx_cfg.httxinfo = wlan_le16_to_cpu(htcfg->ht_tx_info);
+        cfg->param.tx_cfg.misc_cfg = wlan_le16_to_cpu(htcfg->misc_config);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+/**
+ *  @brief This function check if ht40 is allowed in current region
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc    A pointer to BSSDescriptor_t structure
+ *
+ *  @return MTRUE/MFALSE
+ */
+static int wlan_check_chan_width_ht40_by_region(IN mlan_private *pmpriv, IN BSSDescriptor_t *pbss_desc)
+{
+    pmlan_adapter pmadapter = pmpriv->adapter;
+    t_u8 i                  = 0;
+    int cover_pri_chan      = MFALSE;
+    t_u8 pri_chan;
+    t_u8 chan_offset;
+    t_u8 num_cfp;
+
+    ENTER();
+
+    if (pbss_desc->pht_info == MNULL)
+    {
+        PRINTM(MERROR, "ht_info pointer NULL, force use HT20\n");
+        LEAVE();
+        return MFALSE;
+    }
+#if 0
+    if(pmpriv->curr_chan_flags & CHAN_FLAGS_NO_HT40PLUS &&
+        pmpriv->curr_chan_flags & CHAN_FLAGS_NO_HT40MINUS){
+        LEAVE();
+        return MFALSE;
+    }
+#endif
+    pri_chan    = pbss_desc->pht_info->ht_info.pri_chan;
+    chan_offset = GET_SECONDARYCHAN(pbss_desc->pht_info->ht_info.field2);
+#if 0
+    if((chan_offset == SEC_CHAN_ABOVE) && (pmpriv->curr_chan_flags & CHAN_FLAGS_NO_HT40PLUS))
+        return MFALSE;
+    if((chan_offset == SEC_CHAN_BELOW) && (pmpriv->curr_chan_flags & CHAN_FLAGS_NO_HT40MINUS))
+        return MFALSE;
+#endif
+    num_cfp = pmadapter->region_channel[0].num_cfp;
+
+    if ((pbss_desc->bss_band & (BAND_B | BAND_G)) && pmadapter->region_channel[0].valid)
+    {
+        for (i = 0; i < num_cfp; i++)
+        {
+            if (pri_chan == pmadapter->region_channel[0].pcfp[i].channel)
+            {
+                cover_pri_chan = MTRUE;
+                break;
+            }
+        }
+        if (!cover_pri_chan)
+        {
+            PRINTM(MERROR, "Invalid channel, force use HT20\n");
+            LEAVE();
+            return MFALSE;
+        }
+
+        if (chan_offset == (t_u8)SEC_CHAN_ABOVE)
+        {
+            if (pri_chan > num_cfp - 4U)
+            {
+                PRINTM(MERROR, "Invalid second channel offset, force use HT20\n");
+                LEAVE();
+                return MFALSE;
+            }
+        }
+    }
+    LEAVE();
+    return MTRUE;
+}
+
+/**
+ *  @brief This function append the 802_11N tlv
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pbss_desc    A pointer to BSSDescriptor_t structure
+ *  @param ppbuffer     A Pointer to command buffer pointer
+ *
+ *  @return bytes added to the buffer
+ */
+t_u32 wlan_cmd_append_11n_tlv(IN mlan_private *pmpriv, IN BSSDescriptor_t *pbss_desc, OUT t_u8 **ppbuffer)
+{
+    pmlan_adapter pmadapter = pmpriv->adapter;
+    MrvlIETypes_HTCap_t *pht_cap;
+    MrvlIETypes_HTInfo_t *pht_info;
+    MrvlIEtypes_ChanListParamSet_t *pchan_list;
+#if CONFIG_5GHz_SUPPORT
+    MrvlIETypes_2040BSSCo_t *p2040_bss_co;
+#endif
+    MrvlIETypes_ExtCap_t *pext_cap;
+    t_u32 usr_dot_11n_dev_cap, orig_usr_dot_11n_dev_cap = 0;
+    t_u8 usr_dot_11ac_bw;
+    t_u32 ret_len = 0;
+
+    ENTER();
+
+    /* Null Checks */
+    if (ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    if (*ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if ((pbss_desc->bss_band & BAND_A) != 0U)
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_a;
+    }
+    else
+#endif
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_bg;
+    }
+
+    if (pmpriv->bss_mode == MLAN_BSS_MODE_IBSS)
+    {
+        usr_dot_11ac_bw = BW_FOLLOW_VHTCAP;
+    }
+    else
+    {
+        usr_dot_11ac_bw = pmadapter->usr_dot_11ac_bw;
+    }
+
+    if (((pbss_desc->bss_band & (BAND_B | BAND_G
+#if CONFIG_5GHz_SUPPORT
+                                 | BAND_A
+#endif
+                                 )) &&
+         ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap) && !wlan_check_chan_width_ht40_by_region(pmpriv, pbss_desc)) ||
+        (pbss_desc->bss_band & (BAND_B | BAND_G | BAND_GN)))
+    {
+        orig_usr_dot_11n_dev_cap = usr_dot_11n_dev_cap;
+#ifdef RW610
+        RESETSUPP_CHANWIDTH40(usr_dot_11n_dev_cap);
+        RESETSUPP_SHORTGI40(usr_dot_11n_dev_cap);
+#endif
+        RESET_40MHZ_INTOLARENT(usr_dot_11n_dev_cap);
+        pmadapter->usr_dot_11n_dev_cap_bg = usr_dot_11n_dev_cap;
+        pbss_desc->curr_bandwidth         = BW_20MHZ;
+    }
+
+    if (pbss_desc->pht_cap != MNULL)
+    {
+        pht_cap = (MrvlIETypes_HTCap_t *)(void *)*ppbuffer;
+        (void)__memset(pmadapter, pht_cap, 0, sizeof(MrvlIETypes_HTCap_t));
+        pht_cap->header.type = wlan_cpu_to_le16(HT_CAPABILITY);
+        pht_cap->header.len  = sizeof(HTCap_t);
+        (void)__memcpy(pmadapter, (t_u8 *)pht_cap + sizeof(MrvlIEtypesHeader_t),
+                       (t_u8 *)pbss_desc->pht_cap + sizeof(IEEEtypes_Header_t), pht_cap->header.len);
+
+        if (!ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap))
+        {
+            pht_cap->ht_cap.ht_cap_info &= ~(MBIT(1) | MBIT(6));
+        }
+
+        pht_cap->ht_cap.ht_cap_info = wlan_le16_to_cpu(pht_cap->ht_cap.ht_cap_info);
+        pht_cap->ht_cap.ht_ext_cap  = wlan_le16_to_cpu(pht_cap->ht_cap.ht_ext_cap);
+        wlan_fill_ht_cap_tlv(pmpriv, pht_cap, pbss_desc->bss_band);
+        if (wlan_use_non_default_ht_vht_cap(pbss_desc))
+        {
+            /* Indicate 3 streams in TxBF cap*/
+            pht_cap->ht_cap.tx_bf_cap = ((pht_cap->ht_cap.tx_bf_cap & (~(0x3 << 23))) | (0x2 << 23));
+            pht_cap->ht_cap.tx_bf_cap = ((pht_cap->ht_cap.tx_bf_cap & (~(0x3 << 27))) | (0x2 << 27));
+        }
+
+        HEXDUMP("HT_CAPABILITIES IE", (t_u8 *)pht_cap, sizeof(MrvlIETypes_HTCap_t));
+        *ppbuffer += sizeof(MrvlIETypes_HTCap_t);
+        ret_len += sizeof(MrvlIETypes_HTCap_t);
+        pht_cap->header.len = wlan_cpu_to_le16(pht_cap->header.len);
+    }
+
+    if (pbss_desc->pht_info != MNULL)
+    {
+        if (pmpriv->bss_mode == MLAN_BSS_MODE_IBSS)
+        {
+            pht_info = (MrvlIETypes_HTInfo_t *)(void *)*ppbuffer;
+            (void)__memset(pmadapter, pht_info, 0, sizeof(MrvlIETypes_HTInfo_t));
+            pht_info->header.type = wlan_cpu_to_le16(HT_OPERATION);
+            pht_info->header.len  = sizeof(HTInfo_t);
+
+            (void)__memcpy(pmadapter, (t_u8 *)pht_info + sizeof(MrvlIEtypesHeader_t),
+                           (t_u8 *)pbss_desc->pht_info + sizeof(IEEEtypes_Header_t), pht_info->header.len);
+
+            if (!ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap))
+            {
+                RESET_CHANWIDTH40(pht_info->ht_info.field2);
+            }
+
+            *ppbuffer += sizeof(MrvlIETypes_HTInfo_t);
+            ret_len += sizeof(MrvlIETypes_HTInfo_t);
+            pht_info->header.len = wlan_cpu_to_le16(pht_info->header.len);
+        }
+
+        pchan_list = (MrvlIEtypes_ChanListParamSet_t *)(void *)*ppbuffer;
+        (void)__memset(pmadapter, pchan_list, 0, sizeof(MrvlIEtypes_ChanListParamSet_t));
+        pchan_list->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+        pchan_list->header.len  = sizeof(MrvlIEtypes_ChanListParamSet_t) - sizeof(MrvlIEtypesHeader_t);
+        pchan_list->chan_scan_param[0].chan_number = pbss_desc->pht_info->ht_info.pri_chan;
+        pchan_list->chan_scan_param[0].radio_type  = wlan_band_to_radio_type((t_u8)pbss_desc->bss_band);
+        /* support the VHT if the network to be join has the VHT operation */
+        if (ISSUPP_11ACENABLED(pmadapter->fw_cap_info) && (usr_dot_11ac_bw == BW_FOLLOW_VHTCAP) &&
+            ISSUPP_CHANWIDTH40(pmadapter->hw_dot_11n_dev_cap) &&
+            wlan_11ac_bandconfig_allowed(pmpriv, pbss_desc->bss_band) && pbss_desc->pvht_oprat != MNULL &&
+            pbss_desc->pvht_oprat->chan_width == VHT_OPER_CHWD_80MHZ)
+        {
+            //               pchan_list->chan_scan_param[0].bandcfg.chanWidth = CHAN_BW_80MHZ;
+            //               pchan_list->chan_scan_param[0].bandcfg.chan2Offset =
+            //                        GET_SECONDARYCHAN(pbss_desc->pht_info->ht_info.field2);
+            SET_SECONDARYCHAN(pchan_list->chan_scan_param[0].radio_type,
+                              GET_SECONDARYCHAN(pbss_desc->pht_info->ht_info.field2));
+            pchan_list->chan_scan_param[0].radio_type |= (MBIT(2) | MBIT(3));
+            pbss_desc->curr_bandwidth = BW_80MHZ;
+        }
+        else if (ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap) &&
+                 ISALLOWED_CHANWIDTH40(pbss_desc->pht_info->ht_info.field2) &&
+                 wlan_check_chan_width_ht40_by_region(pmpriv, pbss_desc))
+        {
+            SET_SECONDARYCHAN(pchan_list->chan_scan_param[0].radio_type,
+                              GET_SECONDARYCHAN(pbss_desc->pht_info->ht_info.field2));
+            pchan_list->chan_scan_param[0].radio_type |= MBIT(3);
+            pbss_desc->curr_bandwidth = BW_40MHZ;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+
+        HEXDUMP("ChanList", (t_u8 *)pchan_list, sizeof(MrvlIEtypes_ChanListParamSet_t));
+        HEXDUMP("pht_info", (t_u8 *)pbss_desc->pht_info, sizeof(MrvlIETypes_HTInfo_t) - 2);
+        *ppbuffer += sizeof(MrvlIEtypes_ChanListParamSet_t);
+        ret_len += sizeof(MrvlIEtypes_ChanListParamSet_t);
+        pchan_list->header.len = wlan_cpu_to_le16(pchan_list->header.len);
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if ((pbss_desc->bss_band & (BAND_A | BAND_AN)) && pbss_desc->pbss_co_2040 != MNULL)
+    {
+        p2040_bss_co = (MrvlIETypes_2040BSSCo_t *)(void *)*ppbuffer;
+        (void)__memset(pmadapter, p2040_bss_co, 0, sizeof(MrvlIETypes_2040BSSCo_t));
+        p2040_bss_co->header.type = wlan_cpu_to_le16(BSSCO_2040);
+        p2040_bss_co->header.len  = sizeof(BSSCo2040_t);
+
+        (void)__memcpy(pmadapter, (t_u8 *)p2040_bss_co + sizeof(MrvlIEtypesHeader_t),
+                       (t_u8 *)pbss_desc->pbss_co_2040 + sizeof(IEEEtypes_Header_t), p2040_bss_co->header.len);
+
+        HEXDUMP("20/40 BSS Coexistence IE", (t_u8 *)p2040_bss_co, sizeof(MrvlIETypes_2040BSSCo_t));
+        *ppbuffer += sizeof(MrvlIETypes_2040BSSCo_t);
+        ret_len += sizeof(MrvlIETypes_2040BSSCo_t);
+        p2040_bss_co->header.len = wlan_cpu_to_le16(p2040_bss_co->header.len);
+    }
+#endif
+
+    if (pbss_desc->pext_cap != NULL)
+    {
+        pext_cap = (MrvlIETypes_ExtCap_t *)(void *)*ppbuffer;
+        (void)__memset(pmadapter, pext_cap, 0, sizeof(MrvlIETypes_ExtCap_t));
+        pext_cap->header.type = wlan_cpu_to_le16(EXT_CAPABILITY);
+        pext_cap->header.len  = sizeof(ExtCap_t);
+
+        (void)__memcpy(pmadapter, (t_u8 *)pext_cap + sizeof(MrvlIEtypesHeader_t),
+                       (t_u8 *)pbss_desc->pext_cap + sizeof(IEEEtypes_Header_t), pbss_desc->pext_cap->ieee_hdr.len);
+
+        if (pbss_desc && pbss_desc->multi_bssid_ap)
+            SET_EXTCAP_MULTI_BSSID(pext_cap->ext_cap);
+
+#if !defined(SD8801) && !defined(RW610)
+        pext_cap->ext_cap.BSS_CoexistSupport = 0x01; /*2040 CoEx support must be always set*/
+#endif
+
+        if (pmpriv->hotspot_cfg & HOTSPOT_ENABLED)
+        {
+            if ((((t_u8)(pmpriv->hotspot_cfg >> 8)) & HOTSPOT_ENABLE_INTERWORKING_IND) != 0U)
+            {
+                pext_cap->ext_cap.Interworking = 1;
+            }
+            if ((((t_u8)(pmpriv->hotspot_cfg >> 8)) & HOTSPOT_ENABLE_TDLS_IND) != 0U)
+            {
+                pext_cap->ext_cap.TDLSSupport = 1;
+            }
+        }
+#if (CONFIG_WNM_PS)
+        if ((((mlan_private *)mlan_adap->priv[0])->wnm_set == true) && (pbss_desc->pext_cap->ext_cap.WNM_Sleep == true))
+        {
+            pext_cap->ext_cap.WNM_Sleep = 1;
+        }
+        else
+        {
+            pext_cap->ext_cap.WNM_Sleep = 0;
+        }
+#endif
+
+#if CONFIG_11V
+        if (pbss_desc->pext_cap->ext_cap.BSS_Transition == true)
+        {
+            pext_cap->ext_cap.BSS_Transition = 1;
+        }
+        else
+        {
+            pext_cap->ext_cap.BSS_Transition = 0;
+        }
+#endif
+#if CONFIG_11MC || CONFIG_11AZ
+        pext_cap->ext_cap.FTMI = 1;
+#endif
+#if CONFIG_11MC
+        pext_cap->ext_cap.CivicLocation = 1;
+#endif
+#if CONFIG_11AX
+        SET_EXTCAP_TWT_REQ(pext_cap->ext_cap);
+        pext_cap->ext_cap.TWTResp = 0;
+#endif
+        HEXDUMP("Extended Capabilities IE", (t_u8 *)pext_cap, sizeof(MrvlIETypes_ExtCap_t));
+        *ppbuffer += sizeof(MrvlIETypes_ExtCap_t);
+        ret_len += sizeof(MrvlIETypes_ExtCap_t);
+        pext_cap->header.len = wlan_cpu_to_le16(pext_cap->header.len);
+    }
+    else if (pmpriv->hotspot_cfg & HOTSPOT_ENABLED)
+    {
+        wlan_add_ext_capa_info_ie(pmpriv, pbss_desc, ppbuffer);
+        ret_len += sizeof(MrvlIETypes_ExtCap_t);
+    }
+    else
+    {
+        /* Do nothing */
+    }
+    if (orig_usr_dot_11n_dev_cap != 0U)
+    {
+        pmadapter->usr_dot_11n_dev_cap_bg = orig_usr_dot_11n_dev_cap;
+    }
+    LEAVE();
+    return ret_len;
+}
+
+
+/**
+ *  @brief 11n configuration handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+mlan_status wlan_11n_cfg_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status   = MLAN_STATUS_SUCCESS;
+    mlan_ds_11n_cfg *cfg = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_11n_cfg))
+    {
+        PRINTM(MINFO, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_11n_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    cfg = (mlan_ds_11n_cfg *)(void *)pioctl_req->pbuf;
+    switch (cfg->sub_command)
+    {
+        case MLAN_OID_11N_CFG_TX:
+            status = wlan_11n_ioctl_httxcfg(pmadapter, pioctl_req);
+            break;
+        case MLAN_OID_11N_HTCAP_CFG:
+            status = wlan_11n_ioctl_htusrcfg(pmadapter, pioctl_req);
+            break;
+        case MLAN_OID_11N_CFG_DELBA:
+            status = wlan_11n_ioctl_delba(pmadapter, pioctl_req);
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+
+/**
+ *  @brief This function will delete the given entry in Tx BA Stream table
+ *
+ *  @param priv    	Pointer to mlan_private
+ *  @param ptx_tbl	Pointer to tx ba stream entry to delete
+ *
+ *  @return 	        N/A
+ */
+void wlan_11n_delete_txbastream_tbl_entry(mlan_private *priv, t_u8 *ra)
+{
+    TxBAStreamTbl *ptx_tbl  = MNULL;
+    pmlan_adapter pmadapter = priv->adapter;
+
+    ENTER();
+
+    (void)pmadapter->callbacks.moal_spin_lock(pmadapter->pmoal_handle, priv->tx_ba_stream_tbl_ptr.plock);
+
+    if ((ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ra)))
+    {
+        PRINTM(MINFO, "Delete BA stream table entry: %p\n", ptx_tbl);
+
+        util_unlink_list(pmadapter->pmoal_handle, &priv->tx_ba_stream_tbl_ptr, (pmlan_linked_list)ptx_tbl, MNULL,
+                         MNULL);
+    }
+
+    if(ptx_tbl == NULL)
+    {
+        return;
+    }
+
+    (void)pmadapter->callbacks.moal_spin_unlock(pmadapter->pmoal_handle, priv->tx_ba_stream_tbl_ptr.plock);
+
+#if !CONFIG_MEM_POOLS
+    pmadapter->callbacks.moal_mfree(pmadapter->pmoal_handle, (t_u8 *)ptx_tbl);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, ptx_tbl);
+#endif
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function will delete all the entries in Tx BA Stream table
+ *
+ *  @param priv         A pointer to mlan_private
+ *
+ *  @return             N/A
+ */
+void wlan_11n_deleteall_txbastream_tbl(mlan_private *priv)
+{
+    TxBAStreamTbl *del_tbl_ptr = MNULL;
+
+    ENTER();
+
+    wlan_request_ralist_lock(priv);
+    while ((del_tbl_ptr = (TxBAStreamTbl *)util_peek_list(priv->adapter->pmoal_handle, &priv->tx_ba_stream_tbl_ptr,
+                                                          priv->adapter->callbacks.moal_spin_lock,
+                                                          priv->adapter->callbacks.moal_spin_unlock)) != NULL)
+    {
+        wlan_11n_delete_txbastream_tbl_entry(priv, del_tbl_ptr->ra);
+    }
+
+    util_init_list((pmlan_linked_list)&priv->tx_ba_stream_tbl_ptr);
+    wlan_release_ralist_lock(priv);
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function will return the pointer to an entry in BA Stream
+ *  		table which matches the give RA/TID pair
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param ra      RA to find in reordering table
+ *
+ *  @return 	   A pointer to first entry matching RA/TID in BA stream
+ *                 NULL if not found
+ */
+TxBAStreamTbl *wlan_11n_get_txbastream_tbl(mlan_private *priv, t_u8 *ra)
+{
+    TxBAStreamTbl *ptx_tbl;
+    pmlan_adapter pmadapter = priv->adapter;
+
+    ENTER();
+    ptx_tbl = (TxBAStreamTbl *)(void *)util_peek_list(pmadapter->pmoal_handle, &priv->tx_ba_stream_tbl_ptr,
+                                                      pmadapter->callbacks.moal_spin_lock,
+                                                      pmadapter->callbacks.moal_spin_unlock);
+    if (ptx_tbl == MNULL)
+    {
+        LEAVE();
+        return MNULL;
+    }
+
+    while (ptx_tbl != (TxBAStreamTbl *)(void *)&priv->tx_ba_stream_tbl_ptr)
+    {
+        DBG_HEXDUMP(MDAT_D, "RA", ptx_tbl->ra, MLAN_MAC_ADDR_LENGTH);
+
+        if (!__memcmp(pmadapter, ptx_tbl->ra, ra, MLAN_MAC_ADDR_LENGTH))
+        {
+            LEAVE();
+            return ptx_tbl;
+        }
+
+        ptx_tbl = ptx_tbl->pnext;
+    }
+
+    LEAVE();
+    return MNULL;
+}
+
+/**
+ *  @brief This function will create a entry in tx ba stream table for the
+ *  		given RA/TID.
+ *
+ *  @param priv      A pointer to mlan_private
+ *  @param ra        RA to find in reordering table
+ *  @param tid	     TID to find in reordering table
+ *  @param ba_status BA stream status to create the stream with
+ *
+ *  @return 	    N/A
+ */
+void wlan_11n_create_txbastream_tbl(mlan_private *priv, t_u8 *ra, baStatus_e ba_status)
+{
+    TxBAStreamTbl *newNode  = MNULL;
+    pmlan_adapter pmadapter = priv->adapter;
+
+    ENTER();
+
+    if (!wlan_11n_get_txbastream_tbl(priv, ra))
+    {
+        DBG_HEXDUMP(MDAT_D, "RA", ra, MLAN_MAC_ADDR_LENGTH);
+
+#if !CONFIG_MEM_POOLS
+        pmadapter->callbacks.moal_malloc(pmadapter->pmoal_handle, sizeof(TxBAStreamTbl), MLAN_MEM_DEF,
+                                         (t_u8 **)&newNode);
+#else
+        newNode = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+        if (newNode == MNULL)
+        {
+            return;
+        }
+
+        (void)__memset(pmadapter, newNode, 0, sizeof(TxBAStreamTbl));
+        util_init_list((pmlan_linked_list)newNode);
+
+        newNode->ba_status   = ba_status;
+        newNode->txba_thresh = OSA_RandRange(5, 5);
+        (void)__memcpy(pmadapter, newNode->ra, ra, MLAN_MAC_ADDR_LENGTH);
+        (void)__memset(priv->adapter, newNode->rx_seq, 0xff, sizeof(newNode->rx_seq));
+
+        util_enqueue_list_tail(pmadapter->pmoal_handle, &priv->tx_ba_stream_tbl_ptr, (pmlan_linked_list)newNode,
+                               pmadapter->callbacks.moal_spin_lock, pmadapter->callbacks.moal_spin_unlock);
+    }
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function will update ampdu status in tx ba stream table for the
+ *  		given RA/TID.
+ *
+ *  @param priv      A pointer to mlan_private
+ *  @param ra        RA to find in reordering table
+ *  @param tid	     TID to find in reordering table
+ *  @param status    ampdu status
+ *
+ *  @return 	    N/A
+ */
+
+void wlan_11n_update_txbastream_tbl_ampdu_stat(mlan_private *priv, t_u8 *ra, t_u8 status, t_u8 tid)
+{
+    TxBAStreamTbl *ptx_tbl;
+
+    ENTER();
+
+    if ((ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ra)))
+    {
+        ptx_tbl->ampdu_stat[tid] = status;
+    }
+    else
+        PRINTM(MERROR, "update txbastream_tbl ampdu status error\n");
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function will update ampdu supported in tx ba stream table for the
+ *  		given RA.
+ *
+ *  @param priv      A pointer to mlan_private
+ *  @param ra        RA to find in reordering table
+ *  @param supported ampdu support
+ *
+ *  @return 	    N/A
+ */
+
+void wlan_11n_update_txbastream_tbl_ampdu_supported(mlan_private *priv, t_u8 *ra, t_u8 supported)
+{
+    TxBAStreamTbl *ptx_tbl;
+    int i;
+
+    ENTER();
+
+    if ((ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ra)))
+    {
+        for (i = 0; i < MAX_NUM_TID; i++)
+            ptx_tbl->ampdu_supported[i] = supported;
+    }
+    else
+        PRINTM(MERROR, "update txbastream_tbl ampdu supported error\n");
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function will update ampdu tx threshold in tx ba stream table for the
+ *  		given RA.
+ *
+ *  @param priv      A pointer to mlan_private
+ *  @param ra        RA to find in reordering table
+ *  @param tx_thresh tx ba threshold
+ *
+ *  @return 	    N/A
+ */
+
+void wlan_11n_update_txbastream_tbl_tx_thresh(mlan_private *priv, t_u8 *ra, t_u8 tx_thresh)
+{
+    TxBAStreamTbl *ptx_tbl;
+
+    ENTER();
+
+    if ((ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ra)))
+    {
+        ptx_tbl->txba_thresh = tx_thresh;
+    }
+    else
+        PRINTM(MERROR, "update txbastream_tbl ampdu supported error\n");
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function will update ampdu supported in tx ba stream table for the
+ *  		given RA.
+ *
+ *  @param priv      A pointer to mlan_private
+ *  @param ra        RA to find in reordering table
+ *
+ *  @return 	    N/A
+ */
+
+void wlan_11n_update_txbastream_tbl_tx_cnt(mlan_private *priv, t_u8 *ra)
+{
+    TxBAStreamTbl *ptx_tbl;
+
+    ENTER();
+
+    if ((ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ra)))
+    {
+        ptx_tbl->txpkt_cnt++;
+    }
+    else
+        PRINTM(MERROR, "update txbastream_tbl tx cnt error\n");
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function will get sta peer amsdu
+ *
+ *  @param priv      A pointer to mlan_private
+ *
+ *  @return 	    amsdu value
+ */
+
+int wlan_11n_get_sta_peer_amsdu(mlan_private *priv)
+{
+    TxBAStreamTbl *ptx_tbl = MNULL;
+    int ret                = MFALSE;
+
+    ENTER();
+
+    if ((ptx_tbl = wlan_11n_get_txbastream_tbl(priv, priv->curr_bss_params.bss_descriptor.mac_address)))
+    {
+        ret = ptx_tbl->amsdu;
+    }
+
+    LEAVE();
+
+    return ret;
+}
+
+/**
+ *  @brief This function will send a block ack to given tid/ra
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param tid	    TID to send the ADDBA
+ *  @param peer_mac MAC address to send the ADDBA
+ *
+ *  @return 	    MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+int wlan_send_addba(mlan_private *priv, int tid, const t_u8 *peer_mac)
+{
+    HostCmd_DS_11N_ADDBA_REQ add_ba_req;
+    static t_u8 dialog_tok;
+    mlan_status ret;
+
+    ENTER();
+
+    PRINTM(MCMND, "Send addba: TID %d\n", tid);
+    DBG_HEXDUMP(MCMD_D, "Send addba RA", peer_mac, MLAN_MAC_ADDR_LENGTH);
+
+    add_ba_req.block_ack_param_set =
+        (t_u16)((tid << BLOCKACKPARAM_TID_POS) | (priv->add_ba_param.tx_win_size << BLOCKACKPARAM_WINSIZE_POS) |
+                IMMEDIATE_BLOCK_ACK);
+#if CONFIG_AMSDU_IN_AMPDU
+    /** enable AMSDU inside AMPDU */
+    /* To be done: change priv->aggr_prio_tbl[tid].amsdu for specific AMSDU support by CLI cmd */
+#if 0
+    if (priv->add_ba_param.tx_amsdu && (priv->aggr_prio_tbl[tid].amsdu != BA_STREAM_NOT_ALLOWED))
+#else
+    if (priv->add_ba_param.tx_amsdu && priv->bss_type == MLAN_BSS_TYPE_STA)
+#endif
+    {
+        add_ba_req.block_ack_param_set |= BLOCKACKPARAM_AMSDU_SUPP_MASK;
+    }
+#endif
+    add_ba_req.block_ack_tmo = (t_u16)priv->add_ba_param.timeout;
+
+    ++dialog_tok;
+
+    if (dialog_tok == 0U)
+    {
+        dialog_tok = 1;
+    }
+
+    add_ba_req.dialog_token = dialog_tok;
+    (void)__memset(priv->adapter, &add_ba_req.peer_mac_addr, 0x0, MLAN_MAC_ADDR_LENGTH);
+    (void)__memcpy(priv->adapter, &add_ba_req.peer_mac_addr, peer_mac, MLAN_MAC_ADDR_LENGTH);
+#ifdef DUMP_PACKET_MAC
+    wmprintf("wlan_send_addba bss_type:%d\r\n", priv->bss_type);
+    dump_mac_addr(NULL, peer_mac);
+#endif
+    /* We don't wait for the response of this command */
+    ret = wifi_prepare_and_send_cmd(priv, HostCmd_CMD_11N_ADDBA_REQ, 0, 0, MNULL, &add_ba_req, priv->bss_type, NULL);
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function will delete a block ack to given tid/ra
+ *
+ *  @param priv         A pointer to mlan_private
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *  @param tid          TID to send the ADDBA
+ *  @param peer_mac     MAC address to send the ADDBA
+ *  @param initiator    MTRUE if we have initiated ADDBA, MFALSE otherwise
+ *
+ *  @return             MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_send_delba(mlan_private *priv, pmlan_ioctl_req pioctl_req, int tid, t_u8 *peer_mac, int initiator)
+{
+    HostCmd_DS_11N_DELBA delba;
+    mlan_status ret;
+
+    ENTER();
+
+    __memset(priv->adapter, &delba, 0, sizeof(delba));
+    delba.del_ba_param_set = (tid << DELBA_TID_POS);
+
+    if (initiator)
+        DELBA_INITIATOR(delba.del_ba_param_set);
+    else
+        DELBA_RECIPIENT(delba.del_ba_param_set);
+
+    (void)__memcpy(priv->adapter, &delba.peer_mac_addr, peer_mac, MLAN_MAC_ADDR_LENGTH);
+
+    ret = wlan_prepare_cmd(priv, HostCmd_CMD_11N_DELBA, HostCmd_ACT_GEN_SET, 0, (t_void *)pioctl_req, (t_void *)&delba);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function handles the command response of
+ *  		delete a block ack request
+ *
+ *  @param priv		A pointer to mlan_private structure
+ *  @param del_ba	A pointer to command response buffer
+ *
+ *  @return        N/A
+ */
+void wlan_11n_delete_bastream(mlan_private *priv, t_u8 *del_ba)
+{
+    HostCmd_DS_11N_DELBA *pdel_ba = (HostCmd_DS_11N_DELBA *)(void *)del_ba;
+    int tid;
+
+    ENTER();
+
+    DBG_HEXDUMP(MCMD_D, "Delba:", (t_u8 *)pdel_ba, 20);
+    pdel_ba->del_ba_param_set = wlan_le16_to_cpu(pdel_ba->del_ba_param_set);
+    pdel_ba->reason_code      = wlan_le16_to_cpu(pdel_ba->reason_code);
+
+    tid = pdel_ba->del_ba_param_set >> DELBA_TID_POS;
+    mlan_11n_update_bastream_tbl(priv, tid, pdel_ba->peer_mac_addr, TYPE_DELBA_RECEIVE,
+                                 INITIATOR_BIT(pdel_ba->del_ba_param_set));
+
+    LEAVE();
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n_aggr.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n_aggr.c
new file mode 100644
index 0000000000..f73965aa0a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n_aggr.c
@@ -0,0 +1,196 @@
+/** @file mlan_11n_aggr.c
+ *
+ *  @brief  This file provides contains functions for 11n Aggregation
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    11/10/2008: initial version
+********************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+    Local Variables
+********************************************************/
+
+/********************************************************
+    Global Variables
+********************************************************/
+
+/********************************************************
+    Local Functions
+********************************************************/
+
+void wrapper_deliver_amsdu_subframe(pmlan_buffer amsdu_pmbuf, t_u8 *data, t_u16 pkt_len);
+
+
+/**
+ *  @brief Get number of aggregated packets
+ *
+ *  @param data			A pointer to packet data
+ *  @param total_pkt_len	Total packet length
+ *
+ *  @return			Number of packets
+ */
+static int wlan_11n_get_num_aggrpkts(t_u8 *data, t_s32 total_pkt_len)
+{
+    int pkt_count = 0;
+    t_u32 pkt_len, pad;
+
+    ENTER();
+    while (total_pkt_len > 0)
+    {
+        /* Length will be in network format, change it to host */
+        pkt_len = mlan_ntohs((*(t_u16 *)(void *)(data + (2 * MLAN_MAC_ADDR_LENGTH))));
+        pad     = (((pkt_len + sizeof(Eth803Hdr_t)) & 3U)) ? (4U - ((pkt_len + sizeof(Eth803Hdr_t)) & 3U)) : 0U;
+        data += pkt_len + pad + sizeof(Eth803Hdr_t);
+        total_pkt_len -= (t_s32)pkt_len + (t_s32)pad + (t_s32)sizeof(Eth803Hdr_t);
+        ++pkt_count;
+    }
+    LEAVE();
+    return pkt_count;
+}
+
+/********************************************************
+    Global Functions
+********************************************************/
+
+/**
+ *  @brief Deaggregate the received AMSDU packet
+ *
+ *  @param priv		A pointer to mlan_private structure
+ *  @param pmbuf	A pointer to aggregated data packet
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+mlan_status wlan_11n_deaggregate_pkt(mlan_private *priv, pmlan_buffer pmbuf)
+{
+    t_u16 pkt_len;
+    t_s32 total_pkt_len;
+    t_u8 *data;
+    int pad;
+    mlan_status ret = MLAN_STATUS_FAILURE;
+    RxPacketHdr_t *prx_pkt;
+    /* mlan_adapter *pmadapter = priv->adapter; */
+    t_u8 rfc1042_eth_hdr[MLAN_MAC_ADDR_LENGTH] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
+
+    ENTER();
+
+    data          = (t_u8 *)(pmbuf->pbuf + pmbuf->data_offset);
+    total_pkt_len = (t_s32)pmbuf->data_len;
+
+    /* Sanity test */
+    if (total_pkt_len > MLAN_RX_DATA_BUF_SIZE)
+    {
+        PRINTM(MERROR,
+               "Total packet length greater than tx buffer"
+               " size %d\n",
+               total_pkt_len);
+        goto done;
+    }
+
+    pmbuf->use_count = wlan_11n_get_num_aggrpkts(data, total_pkt_len);
+
+    while (total_pkt_len > 0)
+    {
+        prx_pkt = (RxPacketHdr_t *)(void *)data;
+        /* Length will be in network format, change it to host */
+        pkt_len = mlan_ntohs((*(t_u16 *)(void *)(data + (2 * MLAN_MAC_ADDR_LENGTH))));
+        if ((t_s32)pkt_len > total_pkt_len)
+        {
+            PRINTM(MERROR, "Error in packet length: total_pkt_len = %d, pkt_len = %d\n", total_pkt_len, pkt_len);
+            break;
+        }
+
+        pad = (((pkt_len + sizeof(Eth803Hdr_t)) & 3)) ? (4 - ((pkt_len + sizeof(Eth803Hdr_t)) & 3)) : 0;
+
+        total_pkt_len -= (t_s32)pkt_len + pad + (t_s32)sizeof(Eth803Hdr_t);
+
+        if (__memcmp(pmadapter, &prx_pkt->rfc1042_hdr, rfc1042_eth_hdr, sizeof(rfc1042_eth_hdr)) == 0)
+        {
+            (void)__memmove(pmadapter, data + LLC_SNAP_LEN, data, (2 * MLAN_MAC_ADDR_LENGTH));
+            data += LLC_SNAP_LEN;
+            pkt_len += sizeof(Eth803Hdr_t) - LLC_SNAP_LEN;
+        }
+        else
+        {
+            *(t_u16 *)(void *)(data + (2 * MLAN_MAC_ADDR_LENGTH)) = (t_u16)0;
+            pkt_len += sizeof(Eth803Hdr_t);
+        }
+
+        /* This part is customized for WMSDK. We do not need and will not
+           allocate the mlan buffer. */
+        wrapper_deliver_amsdu_subframe(pmbuf, data, pkt_len);
+        ret = MLAN_STATUS_SUCCESS;
+
+
+        switch (ret)
+        {
+            case MLAN_STATUS_SUCCESS:
+                break;
+            default:
+                PRINTM(MINFO, "Unexpected MLAN STATUS deaggregate pkt\n");
+                break;
+        }
+
+        data += pkt_len + pad;
+    }
+
+done:
+    LEAVE();
+    return ret;
+}
+
+#if CONFIG_AMSDU_IN_AMPDU
+int wlan_11n_form_amsdu_pkt(t_u8 *amsdu_buf, t_u8 *data, int pkt_len, int *pad)
+{
+    int dt_offset, amsdu_buf_offset;
+    Rfc1042Hdr_t snap = {
+        0xaa,               /* LLC DSAP */
+        0xaa,               /* LLC SSAP */
+        0x03,               /* LLC CTRL */
+        {0x00, 0x00, 0x00}, /* SNAP OUI */
+        0x0000              /* SNAP type */
+        /*
+         * This field will be overwritten
+         * later with ethertype
+         */
+    };
+
+    ENTER();
+
+    memcpy(amsdu_buf, data, (MLAN_MAC_ADDR_LENGTH)*2);
+    dt_offset = amsdu_buf_offset = (MLAN_MAC_ADDR_LENGTH)*2;
+
+    snap.snap_type = *(t_u16 *)(data + dt_offset);
+    dt_offset += sizeof(t_u16);
+    *(t_u16 *)(amsdu_buf + amsdu_buf_offset) =
+        mlan_htons(pkt_len + LLC_SNAP_LEN - ((2 * MLAN_MAC_ADDR_LENGTH) + sizeof(t_u16)));
+    amsdu_buf_offset += sizeof(t_u16);
+    memcpy(amsdu_buf + amsdu_buf_offset, &snap, LLC_SNAP_LEN);
+    amsdu_buf_offset += LLC_SNAP_LEN;
+#if CONFIG_IMU_GDMA
+    HAL_ImuGdmaCopyData(amsdu_buf + amsdu_buf_offset, data + dt_offset, pkt_len - dt_offset);
+#else
+    memcpy(amsdu_buf + amsdu_buf_offset, data + dt_offset, pkt_len - dt_offset);
+#endif
+    *pad = (((pkt_len + LLC_SNAP_LEN) & 3)) ? (4 - (((pkt_len + LLC_SNAP_LEN)) & 3)) : 0;
+    if (*pad)
+        memset(amsdu_buf + pkt_len + LLC_SNAP_LEN, 0, *pad);
+
+    LEAVE();
+    return pkt_len + LLC_SNAP_LEN + *pad;
+}
+#endif
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n_rxreorder.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n_rxreorder.c
new file mode 100644
index 0000000000..3772490108
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11n_rxreorder.c
@@ -0,0 +1,1296 @@
+/** @file mlan_11n_rxreorder.c
+ *
+ *  @brief  This file provides handling of RxReordering in wlan
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    11/10/2008: initial version
+********************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+#include <wm_net.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+    Local Variables
+********************************************************/
+
+/********************************************************
+    Global Variables
+********************************************************/
+SDK_ALIGN(uint8_t amsdu_inbuf[4096], 32);
+/********************************************************
+    Local Functions
+********************************************************/
+/**
+ *  @brief This function will dispatch amsdu packet and
+ *  		forward it to kernel/upper layer
+ *
+ *  @param priv    	A pointer to mlan_private
+ *  @param pmbuf    A pointer to the received buffer
+ *
+ *  @return 	   	MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_11n_dispatch_amsdu_pkt(mlan_private *priv, pmlan_buffer pmbuf)
+{
+    RxPD *prx_pd;
+    prx_pd = (RxPD *)(void *)(pmbuf->pbuf + pmbuf->data_offset);
+
+    ENTER();
+    if (prx_pd->rx_pkt_type == PKT_TYPE_AMSDU)
+    {
+        pmbuf->data_len = prx_pd->rx_pkt_length;
+        pmbuf->data_offset += prx_pd->rx_pkt_offset;
+
+        (void)__memcpy(priv->adapter, amsdu_inbuf, pmbuf->pbuf, sizeof(RxPD));
+#if defined(SDK_OS_FREE_RTOS)
+        net_stack_buffer_copy_partial(pmbuf->lwip_pbuf, amsdu_inbuf + pmbuf->data_offset, prx_pd->rx_pkt_length, 0);
+#endif
+#if !CONFIG_TX_RX_ZERO_COPY
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(pmbuf->pbuf);
+        net_stack_buffer_free(pmbuf->lwip_pbuf);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf->pbuf);
+#endif
+#endif
+        pmbuf->pbuf = amsdu_inbuf;
+
+        (void)wlan_11n_deaggregate_pkt(priv, pmbuf);
+
+#if CONFIG_TX_RX_ZERO_COPY
+        /* Free the net stack buffer after deaggregation and delivered to stack */
+#if defined(SDK_OS_FREE_RTOS)
+        net_stack_buffer_free(pmbuf->lwip_pbuf);
+#endif
+#else
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(pmbuf);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf);
+#endif
+#endif
+        LEAVE();
+        return MLAN_STATUS_SUCCESS;
+    }
+    LEAVE();
+    return MLAN_STATUS_FAILURE;
+}
+
+/**
+ *  @brief This function will process the rx packet and
+ *  		forward it to kernel/upper layer
+ *
+ *  @param priv    	A pointer to mlan_private
+ *  @param payload  A pointer to rx packet payload
+ *
+ *  @return 	   	MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_11n_dispatch_pkt(t_void *priv, t_void *payload, RxReorderTbl *rx_reor_tbl_ptr)
+{
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+    pmlan_adapter pmadapter = ((pmlan_private)priv)->adapter;
+    ENTER();
+    if (payload == (t_void *)RX_PKT_DROPPED_IN_FW)
+    {
+        LEAVE();
+        return ret;
+    }
+
+
+
+    if (MLAN_STATUS_SUCCESS == wlan_11n_dispatch_amsdu_pkt((mlan_private *)priv, (pmlan_buffer)payload))
+    {
+        LEAVE();
+        return ret;
+    }
+    ret = wlan_process_rx_packet(pmadapter, (pmlan_buffer)payload);
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function restarts the reordering timeout timer
+ *
+ *  @param pmadapter    	A pointer to mlan_adapter
+ *  @param rx_reor_tbl_ptr  A pointer to structure RxReorderTbl
+ *
+ *  @return                 N/A
+ */
+static void mlan_11n_rxreorder_timer_restart(pmlan_adapter pmadapter, RxReorderTbl *rx_reor_tbl_ptr)
+{
+    ENTER();
+    if (rx_reor_tbl_ptr->timer_context.timer_is_set != MFALSE)
+    {
+        (void)pmadapter->callbacks.moal_stop_timer(pmadapter->pmoal_handle, rx_reor_tbl_ptr->timer_context.timer);
+    }
+
+    (void)pmadapter->callbacks.moal_start_timer(pmadapter->pmoal_handle, rx_reor_tbl_ptr->timer_context.timer, MFALSE,
+                                                (rx_reor_tbl_ptr->win_size * MIN_FLUSH_TIMER_MS));
+
+    rx_reor_tbl_ptr->timer_context.timer_is_set = MTRUE;
+    LEAVE();
+}
+
+/**
+ *  @brief This function dispatches all the packets in the buffer.
+ *  		There could be holes in the buffer.
+ *
+ *  @param priv    	        A pointer to mlan_private
+ *  @param rx_reor_tbl_ptr  A pointer to structure RxReorderTbl
+ *  @param start_win        Start window
+ *
+ *  @return 	   	        MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_11n_dispatch_pkt_until_start_win(t_void *priv, RxReorderTbl *rx_reor_tbl_ptr, t_u16 start_win)
+{
+    t_u16 no_pkt_to_send, i, xchg;
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    void *rx_tmp_ptr     = MNULL;
+    mlan_private *pmpriv = (mlan_private *)priv;
+
+    ENTER();
+
+    no_pkt_to_send = (start_win > rx_reor_tbl_ptr->start_win) ?
+                         MIN((start_win - rx_reor_tbl_ptr->start_win), rx_reor_tbl_ptr->win_size) :
+                         rx_reor_tbl_ptr->win_size;
+
+    for (i = 0; i < no_pkt_to_send; ++i)
+    {
+        (void)pmpriv->adapter->callbacks.moal_spin_lock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+        rx_tmp_ptr = MNULL;
+        if (rx_reor_tbl_ptr->rx_reorder_ptr[i] != NULL)
+        {
+            rx_tmp_ptr                         = rx_reor_tbl_ptr->rx_reorder_ptr[i];
+            rx_reor_tbl_ptr->rx_reorder_ptr[i] = MNULL;
+        }
+        (void)pmpriv->adapter->callbacks.moal_spin_unlock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+        if (rx_tmp_ptr != NULL)
+        {
+            (void)wlan_11n_dispatch_pkt(priv, rx_tmp_ptr, rx_reor_tbl_ptr);
+        }
+    }
+
+    (void)pmpriv->adapter->callbacks.moal_spin_lock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+    /*
+     * We don't have a circular buffer, hence use rotation to simulate
+     * circular buffer
+     */
+    xchg = rx_reor_tbl_ptr->win_size - no_pkt_to_send;
+    for (i = 0; i < xchg; ++i)
+    {
+        rx_reor_tbl_ptr->rx_reorder_ptr[i]                  = rx_reor_tbl_ptr->rx_reorder_ptr[no_pkt_to_send + i];
+        rx_reor_tbl_ptr->rx_reorder_ptr[no_pkt_to_send + i] = MNULL;
+    }
+
+    rx_reor_tbl_ptr->start_win = start_win;
+    /* clear the bits of reorder bitmap that has been dispatched */
+    rx_reor_tbl_ptr->bitmap = rx_reor_tbl_ptr->bitmap >> no_pkt_to_send;
+    (void)pmpriv->adapter->callbacks.moal_spin_unlock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function free all the packets in one rxreorder node.
+ *
+ *  @param priv    	        A pointer to mlan_private
+ *
+ *  @return 	   	        MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_11n_free_rxreorder_pkt(t_void *priv, RxReorderTbl *rx_reor_tbl_ptr)
+{
+    mlan_private *pmpriv = (mlan_private *)priv;
+    void *rx_tmp_ptr     = MNULL;
+    int i                = 0;
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    for (i = 0; i < rx_reor_tbl_ptr->win_size; i++)
+    {
+        pmpriv->adapter->callbacks.moal_spin_lock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+        rx_tmp_ptr = MNULL;
+        if (rx_reor_tbl_ptr->rx_reorder_ptr[i] != NULL)
+        {
+            rx_tmp_ptr                         = rx_reor_tbl_ptr->rx_reorder_ptr[i];
+            rx_reor_tbl_ptr->rx_reorder_ptr[i] = MNULL;
+        }
+        pmpriv->adapter->callbacks.moal_spin_unlock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+        if (rx_tmp_ptr != NULL)
+        {
+#if defined(SDK_OS_FREE_RTOS)
+            net_stack_buffer_free(((pmlan_buffer)rx_tmp_ptr)->lwip_pbuf);
+#endif
+#if !CONFIG_TX_RX_ZERO_COPY
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(((pmlan_buffer)rx_tmp_ptr)->pbuf);
+            OSA_MemoryFree(rx_tmp_ptr);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, ((pmlan_buffer)rx_tmp_ptr)->pbuf);
+            OSA_MemoryPoolFree(buf_128_MemoryPool, rx_tmp_ptr);
+#endif
+#endif
+        }
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function will display the rxReorder table
+ *
+ *  @param pmadapter          A pointer to mlan_adapter structure
+ *  @param rx_reor_tbl_ptr    A pointer to structure RxReorderTbl
+ *
+ *  @return 	   	N/A
+ */
+static t_void wlan_11n_display_tbl_ptr(pmlan_adapter pmadapter, RxReorderTbl *rx_reor_tbl_ptr)
+{
+    ENTER();
+
+    DBG_HEXDUMP(MDAT_D, "Reorder ptr", rx_reor_tbl_ptr->rx_reorder_ptr, sizeof(t_void *) * rx_reor_tbl_ptr->win_size);
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function will dispatch all packets sequentially
+ *  		from start_win until a hole is found and adjust the
+ *  		start_win appropriately
+ *
+ *  @param priv    	        A pointer to mlan_private
+ *  @param rx_reor_tbl_ptr  A pointer to structure RxReorderTbl
+ *
+ *  @return 	   	        MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_11n_scan_and_dispatch(t_void *priv, RxReorderTbl *rx_reor_tbl_ptr)
+{
+    t_u16 i, j, xchg;
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    void *rx_tmp_ptr     = MNULL;
+    mlan_private *pmpriv = (mlan_private *)priv;
+
+    ENTER();
+
+    for (i = 0; i < rx_reor_tbl_ptr->win_size; ++i)
+    {
+        (void)pmpriv->adapter->callbacks.moal_spin_lock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+        if (rx_reor_tbl_ptr->rx_reorder_ptr[i] == MNULL)
+        {
+            (void)pmpriv->adapter->callbacks.moal_spin_unlock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+            break;
+        }
+        rx_tmp_ptr                         = rx_reor_tbl_ptr->rx_reorder_ptr[i];
+        rx_reor_tbl_ptr->rx_reorder_ptr[i] = MNULL;
+        (void)pmpriv->adapter->callbacks.moal_spin_unlock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+        (void)wlan_11n_dispatch_pkt(priv, rx_tmp_ptr, rx_reor_tbl_ptr);
+    }
+
+    (void)pmpriv->adapter->callbacks.moal_spin_lock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+    /*
+     * We don't have a circular buffer, hence use rotation to simulate
+     * circular buffer
+     */
+    if (i > 0U)
+    {
+        xchg = rx_reor_tbl_ptr->win_size - i;
+        for (j = 0; j < xchg; ++j)
+        {
+            rx_reor_tbl_ptr->rx_reorder_ptr[j]     = rx_reor_tbl_ptr->rx_reorder_ptr[i + j];
+            rx_reor_tbl_ptr->rx_reorder_ptr[i + j] = MNULL;
+        }
+    }
+    /* clear the bits of reorder bitmap that has been dispatched */
+    rx_reor_tbl_ptr->bitmap = rx_reor_tbl_ptr->bitmap >> i;
+
+    rx_reor_tbl_ptr->start_win = (rx_reor_tbl_ptr->start_win + i) & (MAX_TID_VALUE - 1U);
+
+    (void)pmpriv->adapter->callbacks.moal_spin_unlock(pmpriv->adapter->pmoal_handle, pmpriv->rx_pkt_lock);
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function delete rxreorder table's entry
+ *         	and free the memory
+ *
+ *  @param priv    	        A pointer to mlan_private
+ *  @param rx_reor_tbl_ptr  A pointer to structure RxReorderTbl
+ *
+ *  @return 	   	        N/A
+ */
+static t_void wlan_11n_delete_rxreorder_tbl_entry(mlan_private *priv, RxReorderTbl *rx_reor_tbl_ptr)
+{
+    pmlan_adapter pmadapter = priv->adapter;
+    osa_status_t ret = KOSA_StatusSuccess;
+
+    ENTER();
+
+    if (rx_reor_tbl_ptr == MNULL)
+    {
+        LEAVE();
+        return;
+    }
+
+    /* Get and unlick the delete node using lock */
+    ret = OSA_SemaphoreWait((osa_semaphore_handle_t)priv->rx_reorder_tbl_lock, osaWaitForever_c);
+    if (ret != KOSA_StatusSuccess)
+    {
+        PRINTM(MWARN, "%s: rx_reorder_tbl_lock not ready: %d", __func__, ret);
+        return;
+    }
+    PRINTM(MDAT_D, "Delete rx_reor_tbl_ptr: %p\n", rx_reor_tbl_ptr);
+    rx_reor_tbl_ptr = (RxReorderTbl *)(void *)util_dequeue_list(priv->adapter->pmoal_handle, &priv->rx_reorder_tbl_ptr,
+                            priv->adapter->callbacks.moal_spin_lock,
+                            priv->adapter->callbacks.moal_spin_unlock);
+    OSA_SemaphorePost((osa_semaphore_handle_t)priv->rx_reorder_tbl_lock);
+
+    if (rx_reor_tbl_ptr == MNULL)
+    {
+        LEAVE();
+        return;
+    }
+
+    if (mlan_adap->in_reset)
+        (void)wlan_11n_free_rxreorder_pkt(priv, rx_reor_tbl_ptr);
+    else
+        (void)wlan_11n_dispatch_pkt_until_start_win(
+            priv, rx_reor_tbl_ptr, (rx_reor_tbl_ptr->start_win + rx_reor_tbl_ptr->win_size) & (MAX_TID_VALUE - 1));
+
+    (void)priv->adapter->callbacks.moal_stop_timer(pmadapter->pmoal_handle, rx_reor_tbl_ptr->timer_context.timer);
+    (void)priv->adapter->callbacks.moal_free_timer(pmadapter->pmoal_handle, &rx_reor_tbl_ptr->timer_context.timer);
+
+#if !CONFIG_MEM_POOLS
+    (void)pmadapter->callbacks.moal_mfree(pmadapter->pmoal_handle, (t_u8 *)rx_reor_tbl_ptr->rx_reorder_ptr);
+#else
+    OSA_MemoryPoolFree(buf_1024_MemoryPool, rx_reor_tbl_ptr->rx_reorder_ptr);
+#endif
+
+#if !CONFIG_MEM_POOLS
+    (void)pmadapter->callbacks.moal_mfree(pmadapter->pmoal_handle, (t_u8 *)rx_reor_tbl_ptr);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, rx_reor_tbl_ptr);
+#endif
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function returns the last used sequence number
+ *
+ *  @param rx_reorder_tbl_ptr   A pointer to structure RxReorderTbl
+ *
+ *  @return 	   	            Last used sequence number
+ */
+static t_s16 wlan_11n_find_last_seqnum(RxReorderTbl *rx_reorder_tbl_ptr)
+{
+    t_s16 i;
+
+    ENTER();
+    for (i = (t_s16)(rx_reorder_tbl_ptr->win_size) - 1; i >= 0; --i)
+    {
+        if (rx_reorder_tbl_ptr->rx_reorder_ptr[i] != NULL)
+        {
+            LEAVE();
+            return i;
+        }
+    }
+    LEAVE();
+    return -1;
+}
+
+/**
+ *  @brief This function flushes all data
+ *
+ *  @param context      Reorder context pointer
+ *
+ *  @return 	   	    N/A
+ */
+static t_void wlan_flush_data(osa_timer_arg_t tmr_handle)
+{
+    /* Note: Giving tmr_handle as a parameter in callback is a feature
+       of FreeRTOS. Hence, we have to change the default mlan code here
+       to get the actual context expected by it */
+    reorder_tmr_cnxt_t *reorder_cnxt = (reorder_tmr_cnxt_t *)OSA_TimerGetContext(&tmr_handle);
+    t_u16 startWin_u                 = 0U;
+    t_s16 startWin                   = 0;
+
+    ENTER();
+    if (reorder_cnxt == MNULL)
+    {
+        PRINTM(MWARN, "Flush data failed\n");
+        LEAVE();
+        return;
+    }
+
+    reorder_cnxt->timer_is_set = MFALSE;
+    wlan_11n_display_tbl_ptr(reorder_cnxt->priv->adapter, reorder_cnxt->ptr);
+
+    startWin   = wlan_11n_find_last_seqnum(reorder_cnxt->ptr);
+    startWin_u = (t_u16)startWin;
+
+    if (startWin >= 0)
+    {
+        PRINTM(MINFO, "Flush data %d\n", startWin_u);
+        (void)wlan_11n_dispatch_pkt_until_start_win(
+            reorder_cnxt->priv, reorder_cnxt->ptr,
+            ((reorder_cnxt->ptr->start_win + startWin_u + 1U) & (MAX_TID_VALUE - 1)));
+    }
+
+    wlan_11n_display_tbl_ptr(reorder_cnxt->priv->adapter, reorder_cnxt->ptr);
+    LEAVE();
+}
+
+/**
+ *  @brief This function will create a entry in rx reordering table for the
+ *  		given ta/tid and will initialize it with seq_num, win_size
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param ta       ta to find in reordering table
+ *  @param tid	    tid to find in reordering table
+ *  @param win_size win_size for the give ta/tid pair.
+ *  @param seq_num  Starting sequence number for current entry.
+ *
+ *  @return 	    N/A
+ */
+static t_void wlan_11n_create_rxreorder_tbl(mlan_private *priv, t_u8 *ta, int tid, t_u16 win_size, t_u16 seq_num)
+{
+    t_u16 i;
+    pmlan_adapter pmadapter = priv->adapter;
+    RxReorderTbl *rx_reor_tbl_ptr, *new_node;
+    /* sta_node *sta_ptr = MNULL; */
+    t_u16 last_seq = 0;
+
+    ENTER();
+
+
+    /*
+     * If we get a TID, ta pair which is already present dispatch all the
+     * the packets and move the window size until the ssn
+     */
+    rx_reor_tbl_ptr = wlan_11n_get_rxreorder_tbl(priv, tid, ta);
+    if (rx_reor_tbl_ptr != MNULL)
+    {
+        (void)wlan_11n_dispatch_pkt_until_start_win(priv, rx_reor_tbl_ptr, seq_num);
+    }
+    else
+    {
+        PRINTM(MDAT_D,
+               "%s: seq_num %d, tid %d, ta %02x:%02x:%02x:%02x:"
+               "%02x:%02x, win_size %d\n",
+               __FUNCTION__, seq_num, tid, ta[0], ta[1], ta[2], ta[3], ta[4], ta[5], win_size);
+#if !CONFIG_MEM_POOLS
+        if ((pmadapter->callbacks.moal_malloc(pmadapter->pmoal_handle, sizeof(RxReorderTbl), MLAN_MEM_DEF,
+                                              (t_u8 **)(void **)&new_node)) != MLAN_STATUS_SUCCESS)
+#else
+        new_node = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+        if (new_node == MNULL)
+#endif
+        {
+            PRINTM(MERROR, "Rx reorder memory allocation failed\n");
+            LEAVE();
+            return;
+        }
+
+        util_init_list((pmlan_linked_list)(void *)new_node);
+        new_node->tid = tid;
+        (void)__memcpy(pmadapter, new_node->ta, ta, MLAN_MAC_ADDR_LENGTH);
+        new_node->start_win = seq_num;
+        new_node->pkt_count = 0;
+        if (queuing_ra_based(priv) == MTRUE)
+        {
+            if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP)
+            {
+                TxBAStreamTbl *ptx_tbl = NULL;
+                /* txbastream table also is used as connected STAs data base */
+                if ((ptx_tbl = wlan_11n_get_txbastream_tbl(priv, ta)))
+                {
+                    last_seq = ptx_tbl->rx_seq[tid];
+                }
+            }
+        }
+        else
+        {
+            last_seq = priv->rx_seq[tid];
+        }
+        new_node->last_seq        = last_seq;
+        new_node->win_size        = win_size;
+        new_node->force_no_drop   = MFALSE;
+        new_node->check_start_win = MTRUE;
+        new_node->bitmap          = 0;
+
+#if !CONFIG_MEM_POOLS
+        if ((pmadapter->callbacks.moal_malloc(pmadapter->pmoal_handle, 4U * win_size, MLAN_MEM_DEF,
+                                              (t_u8 **)&new_node->rx_reorder_ptr)) != MLAN_STATUS_SUCCESS)
+#else
+        new_node->rx_reorder_ptr = OSA_MemoryPoolAllocate(buf_1024_MemoryPool);
+        if (new_node->rx_reorder_ptr == MNULL)
+#endif
+        {
+            PRINTM(MERROR,
+                   "Rx reorder table memory allocation"
+                   "failed\n");
+#if !CONFIG_MEM_POOLS
+            (void)pmadapter->callbacks.moal_mfree(pmadapter->pmoal_handle, (t_u8 *)new_node);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, new_node);
+#endif
+            LEAVE();
+            return;
+        }
+
+        PRINTM(MDAT_D, "Create ReorderPtr: %p start_win=%d last_seq=%d\n", new_node, new_node->start_win, last_seq);
+        new_node->timer_context.ptr          = new_node;
+        new_node->timer_context.priv         = priv;
+        new_node->timer_context.timer_is_set = MFALSE;
+        new_node->ba_status                  = BA_STREAM_SETUP_INPROGRESS;
+
+        (void)pmadapter->callbacks.moal_init_timer(pmadapter->pmoal_handle, &new_node->timer_context.timer,
+                                                   wlan_flush_data, &new_node->timer_context);
+        for (i = 0; i < win_size; ++i)
+        {
+            new_node->rx_reorder_ptr[i] = MNULL;
+        }
+
+
+        util_enqueue_list_tail(pmadapter->pmoal_handle, &priv->rx_reorder_tbl_ptr, (pmlan_linked_list)(void *)new_node,
+                               pmadapter->callbacks.moal_spin_lock, pmadapter->callbacks.moal_spin_unlock);
+    }
+
+    LEAVE();
+}
+
+/********************************************************
+    Global Functions
+********************************************************/
+
+/**
+ *  @brief This function will return the pointer to a entry in rx reordering
+ *  		table which matches the give TA/TID pair
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param ta      ta to find in reordering table
+ *  @param tid	   tid to find in reordering table
+ *
+ *  @return	   A pointer to structure RxReorderTbl
+ */
+RxReorderTbl *wlan_11n_get_rxreorder_tbl(mlan_private *priv, int tid, t_u8 *ta)
+{
+    RxReorderTbl *rx_reor_tbl_ptr;
+
+    ENTER();
+    rx_reor_tbl_ptr = (RxReorderTbl *)(void *)util_peek_list(priv->adapter->pmoal_handle, &priv->rx_reorder_tbl_ptr,
+                                                             priv->adapter->callbacks.moal_spin_lock,
+                                                             priv->adapter->callbacks.moal_spin_unlock);
+    if (rx_reor_tbl_ptr == MNULL)
+    {
+        LEAVE();
+        return MNULL;
+    }
+
+    while (rx_reor_tbl_ptr != (RxReorderTbl *)(void *)&priv->rx_reorder_tbl_ptr)
+    {
+        if ((!__memcmp(priv->adapter, rx_reor_tbl_ptr->ta, ta, MLAN_MAC_ADDR_LENGTH)) && (rx_reor_tbl_ptr->tid == tid))
+        {
+            LEAVE();
+            return rx_reor_tbl_ptr;
+        }
+
+        rx_reor_tbl_ptr = rx_reor_tbl_ptr->pnext;
+    }
+
+    LEAVE();
+    return MNULL;
+}
+
+/**
+ *  @brief This function prepares command for adding a block ack
+ *  		request.
+ *
+ *  @param priv        A pointer to mlan_private structure
+ *  @param cmd         A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf   A pointer to data buffer
+ *
+ *  @return            MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_11n_addba_req(mlan_private *priv, HostCmd_DS_COMMAND *cmd, t_void *pdata_buf)
+{
+    HostCmd_DS_11N_ADDBA_REQ *padd_ba_req = (HostCmd_DS_11N_ADDBA_REQ *)&cmd->params.add_ba_req;
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_11N_ADDBA_REQ);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_11N_ADDBA_REQ) + S_DS_GEN);
+
+    (void)__memcpy(priv->adapter, padd_ba_req, pdata_buf, sizeof(HostCmd_DS_11N_ADDBA_REQ));
+    padd_ba_req->block_ack_param_set = wlan_cpu_to_le16(padd_ba_req->block_ack_param_set);
+    padd_ba_req->block_ack_tmo       = wlan_cpu_to_le16(padd_ba_req->block_ack_tmo);
+    padd_ba_req->ssn                 = wlan_cpu_to_le16(padd_ba_req->ssn);
+    padd_ba_req->add_req_result      = 0;
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command for adding a block ack
+ *  		response.
+ *
+ *  @param priv        A pointer to mlan_private structure
+ *  @param cmd         A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf   A pointer to data buffer
+ *
+ *  @return            MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_11n_addba_rspgen(mlan_private *priv, HostCmd_DS_COMMAND *cmd, void *pdata_buf)
+{
+    HostCmd_DS_11N_ADDBA_RSP *padd_ba_rsp    = (HostCmd_DS_11N_ADDBA_RSP *)&cmd->params.add_ba_rsp;
+    HostCmd_DS_11N_ADDBA_REQ *pevt_addba_req = (HostCmd_DS_11N_ADDBA_REQ *)pdata_buf;
+    t_u8 tid                                 = 0U;
+    t_u16 win_size                           = 0U;
+
+    ENTER();
+
+    pevt_addba_req->block_ack_param_set = wlan_le16_to_cpu(pevt_addba_req->block_ack_param_set);
+    pevt_addba_req->block_ack_tmo       = wlan_le16_to_cpu(pevt_addba_req->block_ack_tmo);
+    pevt_addba_req->ssn                 = wlan_le16_to_cpu(pevt_addba_req->ssn);
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_11N_ADDBA_RSP);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_11N_ADDBA_RSP) + S_DS_GEN);
+
+    (void)__memcpy(NULL, padd_ba_rsp->peer_mac_addr, pevt_addba_req->peer_mac_addr, MLAN_MAC_ADDR_LENGTH);
+    padd_ba_rsp->dialog_token   = pevt_addba_req->dialog_token;
+    padd_ba_rsp->block_ack_tmo  = wlan_cpu_to_le16(pevt_addba_req->block_ack_tmo);
+    padd_ba_rsp->ssn            = wlan_cpu_to_le16(pevt_addba_req->ssn);
+    padd_ba_rsp->add_rsp_result = 0;
+
+    padd_ba_rsp->block_ack_param_set = pevt_addba_req->block_ack_param_set;
+    tid = (padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_TID_MASK) >> BLOCKACKPARAM_TID_POS;
+    if ((priv->addba_reject[tid] != ADDBA_RSP_STATUS_ACCEPT)
+    /* wmsdk: we are not using UAP with mlan right now */
+    )
+    {
+        padd_ba_rsp->status_code = wlan_cpu_to_le16(ADDBA_RSP_STATUS_DECLINED);
+    }
+    else
+    {
+        padd_ba_rsp->status_code = wlan_cpu_to_le16(ADDBA_RSP_STATUS_ACCEPT);
+    }
+    padd_ba_rsp->block_ack_param_set &= ~BLOCKACKPARAM_WINSIZE_MASK;
+#if CONFIG_AMSDU_IN_AMPDU
+    /* To be done: change priv->aggr_prio_tbl[tid].amsdu for specific AMSDU support by CLI cmd */
+    if (!priv->add_ba_param.rx_amsdu)
+#endif
+    {
+        /* We do not support AMSDU inside AMPDU, hence reset the bit */
+        padd_ba_rsp->block_ack_param_set &= ~BLOCKACKPARAM_AMSDU_SUPP_MASK;
+    }
+
+    padd_ba_rsp->block_ack_param_set |= (priv->add_ba_param.rx_win_size << BLOCKACKPARAM_WINSIZE_POS);
+    win_size = (padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_WINSIZE_MASK) >> BLOCKACKPARAM_WINSIZE_POS;
+    if (win_size == 0U)
+    {
+        padd_ba_rsp->status_code = wlan_cpu_to_le16(ADDBA_RSP_STATUS_DECLINED);
+    }
+
+    padd_ba_rsp->block_ack_param_set = wlan_cpu_to_le16(padd_ba_rsp->block_ack_param_set);
+
+    if (!wifi_sta_ampdu_rx_enable_per_tid_is_allowed(tid))
+    {
+        padd_ba_rsp->status_code    = wlan_cpu_to_le16(ADDBA_RSP_STATUS_DECLINED);
+        padd_ba_rsp->add_rsp_result = BA_RESULT_FAILURE;
+    }
+
+    if (padd_ba_rsp->status_code == wlan_cpu_to_le16(ADDBA_RSP_STATUS_ACCEPT))
+    {
+        wlan_11n_create_rxreorder_tbl(priv, pevt_addba_req->peer_mac_addr, tid, win_size, pevt_addba_req->ssn);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+mlan_status wlan_cmd_11n_uap_addba_rspgen(mlan_private *priv, HostCmd_DS_COMMAND *cmd, void *pdata_buf)
+{
+    HostCmd_DS_11N_ADDBA_RSP *padd_ba_rsp    = (HostCmd_DS_11N_ADDBA_RSP *)&cmd->params.add_ba_rsp;
+    HostCmd_DS_11N_ADDBA_REQ *pevt_addba_req = (HostCmd_DS_11N_ADDBA_REQ *)pdata_buf;
+    t_u8 tid                                 = 0;
+    int win_size                             = 0;
+
+    ENTER();
+
+    pevt_addba_req->block_ack_param_set = wlan_le16_to_cpu(pevt_addba_req->block_ack_param_set);
+    pevt_addba_req->block_ack_tmo       = wlan_le16_to_cpu(pevt_addba_req->block_ack_tmo);
+    pevt_addba_req->ssn                 = wlan_le16_to_cpu(pevt_addba_req->ssn);
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_11N_ADDBA_RSP);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_11N_ADDBA_RSP) + S_DS_GEN);
+
+    (void)__memcpy(NULL, padd_ba_rsp->peer_mac_addr, pevt_addba_req->peer_mac_addr, MLAN_MAC_ADDR_LENGTH);
+    padd_ba_rsp->dialog_token  = pevt_addba_req->dialog_token;
+    padd_ba_rsp->block_ack_tmo = wlan_cpu_to_le16(pevt_addba_req->block_ack_tmo);
+    padd_ba_rsp->ssn           = wlan_cpu_to_le16(pevt_addba_req->ssn);
+
+    padd_ba_rsp->block_ack_param_set = pevt_addba_req->block_ack_param_set;
+    padd_ba_rsp->add_rsp_result      = 0;
+    tid = (padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_TID_MASK) >> BLOCKACKPARAM_TID_POS;
+    if (priv->addba_reject[tid])
+        padd_ba_rsp->status_code = wlan_cpu_to_le16(ADDBA_RSP_STATUS_DECLINED);
+    else
+        padd_ba_rsp->status_code = wlan_cpu_to_le16(ADDBA_RSP_STATUS_ACCEPT);
+
+#if CONFIG_AMSDU_IN_AMPDU
+        /* To be done: change priv->aggr_prio_tbl[tid].amsdu for specific AMSDU support by CLI cmd */
+#if 0
+    if (!priv->add_ba_param.rx_amsdu || (priv->aggr_prio_tbl[tid].amsdu == BA_STREAM_NOT_ALLOWED))
+#else
+    if (!priv->add_ba_param.rx_amsdu)
+#endif
+#endif
+        /* We do not support AMSDU inside AMPDU, hence reset the bit */
+        padd_ba_rsp->block_ack_param_set &= ~BLOCKACKPARAM_AMSDU_SUPP_MASK;
+
+    if (!wifi_uap_ampdu_rx_enable_per_tid_is_allowed(tid))
+    {
+        padd_ba_rsp->status_code    = wlan_cpu_to_le16(ADDBA_RSP_STATUS_DECLINED);
+        padd_ba_rsp->add_rsp_result = BA_RESULT_FAILURE;
+    }
+    padd_ba_rsp->block_ack_param_set &= ~BLOCKACKPARAM_WINSIZE_MASK;
+    padd_ba_rsp->block_ack_param_set |= (priv->add_ba_param.rx_win_size << BLOCKACKPARAM_WINSIZE_POS);
+    win_size = (padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_WINSIZE_MASK) >> BLOCKACKPARAM_WINSIZE_POS;
+    if (win_size == 0)
+        padd_ba_rsp->status_code = wlan_cpu_to_le16(ADDBA_RSP_STATUS_DECLINED);
+
+    padd_ba_rsp->block_ack_param_set = wlan_cpu_to_le16(padd_ba_rsp->block_ack_param_set);
+
+    if (padd_ba_rsp->status_code == wlan_cpu_to_le16(ADDBA_RSP_STATUS_ACCEPT))
+        wlan_11n_create_rxreorder_tbl(priv, pevt_addba_req->peer_mac_addr, tid, win_size, pevt_addba_req->ssn);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command for deleting a block ack
+ *  		request.
+ *
+ *  @param priv       A pointer to mlan_private structure
+ *  @param cmd        A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf  A pointer to data buffer
+ *
+ *  @return           MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_11n_delba(mlan_private *priv, HostCmd_DS_COMMAND *cmd, void *pdata_buf)
+{
+    HostCmd_DS_11N_DELBA *pdel_ba = (HostCmd_DS_11N_DELBA *)&cmd->params.del_ba;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_11N_DELBA);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_11N_DELBA) + S_DS_GEN);
+
+    (void)__memcpy(priv->adapter, pdel_ba, pdata_buf, sizeof(HostCmd_DS_11N_DELBA));
+    pdel_ba->del_ba_param_set = wlan_cpu_to_le16(pdel_ba->del_ba_param_set);
+    pdel_ba->reason_code      = wlan_cpu_to_le16(pdel_ba->reason_code);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+/**
+ *  @brief This function will identify if RxReodering is needed for the packet
+ *  		and will do the reordering if required before sending it to kernel
+ *
+ *  @param priv     A pointer to mlan_private
+ *  @param seq_num  Seqence number of the current packet
+ *  @param tid	    Tid of the current packet
+ *  @param ta	    Transmiter address of the current packet
+ *  @param pkt_type Packetype for the current packet (to identify if its a BAR)
+ *  @param payload  Pointer to the payload
+ *
+ *  @return 	    MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status mlan_11n_rxreorder_pkt(void *priv, t_u16 seq_num, t_u16 tid, t_u8 *ta, t_u8 pkt_type, void *payload)
+{
+    RxReorderTbl *rx_reor_tbl_ptr;
+    t_u16 start_win, end_win, win_size;
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    pmlan_adapter pmadapter = ((mlan_private *)priv)->adapter;
+
+    ENTER();
+    rx_reor_tbl_ptr = wlan_11n_get_rxreorder_tbl((mlan_private *)priv, (int)tid, ta);
+    if (rx_reor_tbl_ptr == MNULL)
+    {
+        if (pkt_type != PKT_TYPE_BAR)
+        {
+            (void)wlan_11n_dispatch_pkt(priv, payload, rx_reor_tbl_ptr);
+        }
+
+        LEAVE();
+        return ret;
+    }
+    else
+    {
+        if ((pkt_type == PKT_TYPE_AMSDU) && (rx_reor_tbl_ptr->amsdu == 0U))
+        {
+            (void)wlan_11n_dispatch_pkt(priv, payload, rx_reor_tbl_ptr);
+            LEAVE();
+            return ret;
+        }
+        if (pkt_type == PKT_TYPE_BAR)
+        {
+            PRINTM(MDAT_D, "BAR ");
+        }
+        if (pkt_type == PKT_TYPE_AMSDU)
+        {
+            PRINTM(MDAT_D, "AMSDU ");
+        }
+
+        if (rx_reor_tbl_ptr->check_start_win != MFALSE)
+        {
+            if (seq_num == rx_reor_tbl_ptr->start_win)
+            {
+                rx_reor_tbl_ptr->check_start_win = MFALSE;
+            }
+            else
+            {
+                rx_reor_tbl_ptr->pkt_count++;
+                if (rx_reor_tbl_ptr->pkt_count < (rx_reor_tbl_ptr->win_size / 2U))
+                {
+                    if (rx_reor_tbl_ptr->last_seq == seq_num)
+                    {
+                        /** drop duplicate packet */
+                        ret = MLAN_STATUS_FAILURE;
+                    }
+                    else
+                    {
+                        /** forward the packet to kernel */
+                        rx_reor_tbl_ptr->last_seq = seq_num;
+                        if (pkt_type != PKT_TYPE_BAR)
+                        {
+                            (void)wlan_11n_dispatch_pkt(priv, payload, rx_reor_tbl_ptr);
+                        }
+                    }
+                    LEAVE();
+                    return ret;
+                }
+
+                rx_reor_tbl_ptr->check_start_win = MFALSE;
+                if ((seq_num != rx_reor_tbl_ptr->start_win) && (rx_reor_tbl_ptr->last_seq != DEFAULT_SEQ_NUM))
+                {
+                    end_win = (rx_reor_tbl_ptr->start_win + rx_reor_tbl_ptr->win_size - 1U) & (MAX_TID_VALUE - 1U);
+                    if (((end_win > rx_reor_tbl_ptr->start_win) &&
+                         (rx_reor_tbl_ptr->last_seq >= rx_reor_tbl_ptr->start_win) &&
+                         (rx_reor_tbl_ptr->last_seq < end_win)) ||
+                        ((end_win < rx_reor_tbl_ptr->start_win) &&
+                         ((rx_reor_tbl_ptr->last_seq >= rx_reor_tbl_ptr->start_win) ||
+                          (rx_reor_tbl_ptr->last_seq < end_win))))
+                    {
+                        PRINTM(MDAT_D, "Update start_win: last_seq=%d, start_win=%d seq_num=%d\n",
+                               rx_reor_tbl_ptr->last_seq, rx_reor_tbl_ptr->start_win, seq_num);
+                        rx_reor_tbl_ptr->start_win = rx_reor_tbl_ptr->last_seq + 1U;
+                    }
+                    else if ((seq_num < rx_reor_tbl_ptr->start_win) && (seq_num > rx_reor_tbl_ptr->last_seq))
+                    {
+                        PRINTM(MDAT_D, "Update start_win: last_seq=%d, start_win=%d seq_num=%d\n",
+                               rx_reor_tbl_ptr->last_seq, rx_reor_tbl_ptr->start_win, seq_num);
+                        rx_reor_tbl_ptr->start_win = rx_reor_tbl_ptr->last_seq + 1U;
+                    }
+                    else
+                    { /* Do Nothing */
+                    }
+                }
+            }
+        }
+
+        start_win = rx_reor_tbl_ptr->start_win;
+        win_size  = rx_reor_tbl_ptr->win_size;
+        end_win   = ((start_win + win_size) - 1U) & (MAX_TID_VALUE - 1U);
+
+        PRINTM(MDAT_D, "TID %d, TA %02x:%02x:%02x:%02x:%02x:%02x\n", tid, ta[0], ta[1], ta[2], ta[3], ta[4], ta[5]);
+        PRINTM(MDAT_D, "1:seq_num %d start_win %d win_size %d end_win %d\n", seq_num, start_win, win_size, end_win);
+        /*
+         * If seq_num is less then starting win then ignore and drop
+         * the packet
+         */
+        if (rx_reor_tbl_ptr->force_no_drop != MFALSE)
+        {
+            PRINTM(MDAT_D, "Force no drop packet after HS_ACTIVED\n");
+            rx_reor_tbl_ptr->force_no_drop = MFALSE;
+        }
+        else
+        {
+            if ((start_win + TWOPOW11) > (MAX_TID_VALUE - 1U))
+            { /* Wrap */
+                if (seq_num >= ((start_win + (TWOPOW11)) & (MAX_TID_VALUE - 1U)) && (seq_num < start_win))
+                {
+                    ret = MLAN_STATUS_FAILURE;
+                    goto done;
+                }
+            }
+            else if ((seq_num < start_win) || (seq_num > (start_win + (TWOPOW11))))
+            {
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+            else
+            { /* Do Nothing */
+            }
+        }
+
+        /*
+         * If this packet is a BAR we adjust seq_num as
+         * WinStart = seq_num
+         */
+        if (pkt_type == PKT_TYPE_BAR)
+        {
+            seq_num = ((seq_num + win_size) - 1U) & (MAX_TID_VALUE - 1U);
+        }
+
+        PRINTM(MDAT_D, "2:seq_num %d start_win %d win_size %d end_win %d\n", seq_num, start_win, win_size, end_win);
+
+        if (((end_win < start_win) && (seq_num < start_win) && (seq_num > end_win)) ||
+            ((end_win > start_win) && ((seq_num > end_win) || (seq_num < start_win))))
+        {
+            t_s16 delta = (t_s16)seq_num - (t_s16)win_size;
+            end_win     = seq_num;
+            if ((delta + 1) >= 0)
+            {
+                start_win = (end_win - win_size) + 1U;
+            }
+            else
+            {
+                start_win = (MAX_TID_VALUE - (win_size - seq_num)) + 1U;
+            }
+
+            if ((ret = wlan_11n_dispatch_pkt_until_start_win(priv, rx_reor_tbl_ptr, start_win)) != MLAN_STATUS_SUCCESS)
+            {
+                goto done;
+            }
+        }
+
+        PRINTM(MDAT_D,
+               "3:seq_num %d start_win %d win_size %d"
+               " end_win %d\n",
+               seq_num, start_win, win_size, end_win);
+        if (pkt_type != PKT_TYPE_BAR)
+        {
+            if (seq_num >= start_win)
+            {
+                if (rx_reor_tbl_ptr->rx_reorder_ptr[seq_num - start_win] != NULL)
+                {
+                    PRINTM(MDAT_D, "Drop Duplicate Pkt\n");
+                    ret = MLAN_STATUS_FAILURE;
+                    goto done;
+                }
+                rx_reor_tbl_ptr->rx_reorder_ptr[seq_num - start_win] = payload;
+                MLAN_SET_BIT_U64(rx_reor_tbl_ptr->bitmap, seq_num - start_win);
+            }
+            else
+            { /* Wrap condition */
+                if (rx_reor_tbl_ptr->rx_reorder_ptr[(seq_num + (MAX_TID_VALUE)) - start_win] != NULL)
+                {
+                    PRINTM(MDAT_D, "Drop Duplicate Pkt\n");
+                    ret = MLAN_STATUS_FAILURE;
+                    goto done;
+                }
+                rx_reor_tbl_ptr->rx_reorder_ptr[(seq_num + (MAX_TID_VALUE)) - start_win] = payload;
+                MLAN_SET_BIT_U64(rx_reor_tbl_ptr->bitmap, (seq_num + (MAX_TID_VALUE)) - start_win);
+            }
+        }
+
+        wlan_11n_display_tbl_ptr(pmadapter, rx_reor_tbl_ptr);
+
+        /*
+         * Dispatch all packets sequentially from start_win until a
+         * hole is found and adjust the start_win appropriately
+         */
+        ret = wlan_11n_scan_and_dispatch(priv, rx_reor_tbl_ptr);
+
+        wlan_11n_display_tbl_ptr(pmadapter, rx_reor_tbl_ptr);
+    }
+
+done:
+    if ((rx_reor_tbl_ptr->timer_context.timer_is_set != MFALSE) && (rx_reor_tbl_ptr->bitmap == 0U))
+    {
+        (void)pmadapter->callbacks.moal_stop_timer(pmadapter->pmoal_handle, rx_reor_tbl_ptr->timer_context.timer);
+        rx_reor_tbl_ptr->timer_context.timer_is_set = MFALSE;
+    }
+
+    if ((rx_reor_tbl_ptr->timer_context.timer_is_set == MFALSE) && (rx_reor_tbl_ptr->bitmap != 0U))
+    {
+        mlan_11n_rxreorder_timer_restart(pmadapter, rx_reor_tbl_ptr);
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function will update an entry for a given tid/ta pair. tid/ta
+ *  		are taken from delba_event body
+ *
+ *  @param priv    	    A pointer to mlan_private
+ *  @param tid		    tid to send delba
+ *  @param peer_mac	    MAC address to send delba
+ *  @param type 	    TYPE_DELBA_SENT	or TYPE_DELBA_RECEIVE
+ *  @param initiator    MTRUE if we are initiator of ADDBA, MFALSE otherwise
+ *
+ *  @return 	   	    N/A
+ */
+void mlan_11n_update_bastream_tbl(mlan_private *priv, int tid, t_u8 *peer_mac, t_u8 type, int initiator)
+{
+    RxReorderTbl *rx_reor_tbl_ptr;
+    TxBAStreamTbl *ptxtbl;
+    t_u8 cleanup_rx_reorder_tbl;
+
+    ENTER();
+
+    if (type == TYPE_DELBA_RECEIVE)
+    {
+        cleanup_rx_reorder_tbl = (initiator) ? MTRUE : MFALSE;
+    }
+    else
+    {
+        cleanup_rx_reorder_tbl = (initiator) ? MFALSE : MTRUE;
+    }
+
+    PRINTM(MEVENT,
+           "DELBA: %02x:%02x:%02x:%02x:%02x:%02x tid=%d,"
+           "initiator=%d\n",
+           peer_mac[0], peer_mac[1], peer_mac[2], peer_mac[3], peer_mac[4], peer_mac[5], tid, initiator);
+
+    if (cleanup_rx_reorder_tbl != 0U)
+    {
+        rx_reor_tbl_ptr = wlan_11n_get_rxreorder_tbl(priv, tid, peer_mac);
+        if (rx_reor_tbl_ptr == MNULL)
+        {
+            PRINTM(MWARN, "TID, TA not found in table!\n");
+            LEAVE();
+            return;
+        }
+        wlan_11n_delete_rxreorder_tbl_entry(priv, rx_reor_tbl_ptr);
+    }
+    else
+    {
+        wlan_request_ralist_lock(priv);
+        ptxtbl = wlan_11n_get_txbastream_tbl(priv, peer_mac);
+        if (ptxtbl == MNULL)
+        {
+            PRINTM(MWARN, "TID, RA not found in table!\n");
+            wlan_release_ralist_lock(priv);
+            LEAVE();
+            return;
+        }
+
+        wlan_11n_update_txbastream_tbl_ampdu_stat(priv, peer_mac, MFALSE, tid);
+        wlan_release_ralist_lock(priv);
+    }
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function handles the command response of
+ *  		a block ack response
+ *
+ *  @param priv    A pointer to mlan_private structure
+ *  @param resp    A pointer to HostCmd_DS_COMMAND
+ *
+ *  @return        MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_11n_addba_resp(mlan_private *priv, HostCmd_DS_COMMAND *resp)
+{
+    HostCmd_DS_11N_ADDBA_RSP *padd_ba_rsp = (HostCmd_DS_11N_ADDBA_RSP *)&resp->params.add_ba_rsp;
+    int tid;
+    RxReorderTbl *rx_reor_tbl_ptr = MNULL;
+
+    ENTER();
+
+    padd_ba_rsp->status_code         = wlan_le16_to_cpu(padd_ba_rsp->status_code);
+    padd_ba_rsp->block_ack_param_set = wlan_le16_to_cpu(padd_ba_rsp->block_ack_param_set);
+    padd_ba_rsp->block_ack_tmo       = wlan_le16_to_cpu(padd_ba_rsp->block_ack_tmo);
+    padd_ba_rsp->ssn                 = wlan_le16_to_cpu(padd_ba_rsp->ssn);
+
+    tid = (padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_TID_MASK) >> BLOCKACKPARAM_TID_POS;
+    /* Check if we had rejected the ADDBA, if yes then do not create the stream */
+    if (padd_ba_rsp->status_code == BA_RESULT_SUCCESS)
+    {
+        PRINTM(MCMND, "ADDBA RSP: %02x:%02x:%02x:%02x:%02x:%02x tid=%d ssn=%d win_size=%d,amsdu=%d\n",
+               padd_ba_rsp->peer_mac_addr[0], padd_ba_rsp->peer_mac_addr[1], padd_ba_rsp->peer_mac_addr[2],
+               padd_ba_rsp->peer_mac_addr[3], padd_ba_rsp->peer_mac_addr[4], padd_ba_rsp->peer_mac_addr[5], tid,
+               padd_ba_rsp->ssn,
+               ((padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_WINSIZE_MASK) >> BLOCKACKPARAM_WINSIZE_POS),
+               padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_AMSDU_SUPP_MASK);
+
+        if ((rx_reor_tbl_ptr = wlan_11n_get_rxreorder_tbl(priv, tid, padd_ba_rsp->peer_mac_addr)) != NULL)
+        {
+            rx_reor_tbl_ptr->ba_status = BA_STREAM_SETUP_COMPLETE;
+            if ((padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_AMSDU_SUPP_MASK) && priv->add_ba_param.rx_amsdu &&
+                (priv->aggr_prio_tbl[tid].amsdu != BA_STREAM_NOT_ALLOWED))
+            {
+                rx_reor_tbl_ptr->amsdu = MTRUE;
+            }
+            else
+            {
+                rx_reor_tbl_ptr->amsdu = MFALSE;
+            }
+        }
+    }
+    else
+    {
+        PRINTM(MERROR, "ADDBA RSP: Failed(%02x:%02x:%02x:%02x:%02x:%02x tid=%d)\n", padd_ba_rsp->peer_mac_addr[0],
+               padd_ba_rsp->peer_mac_addr[1], padd_ba_rsp->peer_mac_addr[2], padd_ba_rsp->peer_mac_addr[3],
+               padd_ba_rsp->peer_mac_addr[4], padd_ba_rsp->peer_mac_addr[5], tid);
+        if ((rx_reor_tbl_ptr = wlan_11n_get_rxreorder_tbl(priv, tid, padd_ba_rsp->peer_mac_addr)) != NULL)
+        {
+            wlan_11n_delete_rxreorder_tbl_entry(priv, rx_reor_tbl_ptr);
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles ba_stream_timeout event
+ *
+ *  @param priv    	A pointer to mlan_private
+ *  @param event    A pointer to structure HostCmd_DS_11N_BATIMEOUT
+ *
+ *  @return 	   	N/A
+ */
+void wlan_11n_ba_stream_timeout(mlan_private *priv, HostCmd_DS_11N_BATIMEOUT *event)
+{
+    HostCmd_DS_11N_DELBA delba;
+
+    ENTER();
+
+    DBG_HEXDUMP(MCMD_D, "Event:", (t_u8 *)event, 20);
+
+    (void)__memset(priv->adapter, &delba, 0, sizeof(HostCmd_DS_11N_DELBA));
+    (void)__memcpy(priv->adapter, delba.peer_mac_addr, event->peer_mac_addr, MLAN_MAC_ADDR_LENGTH);
+
+    delba.del_ba_param_set |= (t_u16)event->tid << DELBA_TID_POS;
+    delba.del_ba_param_set |= (t_u16)event->origninator << DELBA_INITIATOR_POS;
+    delba.reason_code = REASON_CODE_STA_TIMEOUT;
+    (void)wlan_prepare_cmd(priv, HostCmd_CMD_11N_DELBA, 0, 0, MNULL, &delba);
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function cleans up reorder tbl
+ *
+ *  @param priv    	A pointer to mlan_private
+ *
+ *  @return 	   	N/A
+ */
+void wlan_11n_cleanup_reorder_tbl(mlan_private *priv)
+{
+    RxReorderTbl *del_tbl_ptr;
+
+    ENTER();
+
+    while ((del_tbl_ptr = (RxReorderTbl *)(void *)util_peek_list(priv->adapter->pmoal_handle, &priv->rx_reorder_tbl_ptr,
+                                                                 priv->adapter->callbacks.moal_spin_lock,
+                                                                 priv->adapter->callbacks.moal_spin_unlock)) != MNULL)
+    {
+        wlan_11n_delete_rxreorder_tbl_entry(priv, del_tbl_ptr);
+    }
+
+    util_init_list((pmlan_linked_list)(void *)&priv->rx_reorder_tbl_ptr);
+
+    (void)__memset(priv->adapter, priv->rx_seq, 0xff, sizeof(priv->rx_seq));
+    LEAVE();
+}
+
+/**
+ *  @brief This function cleans up reorder tbl for specific station
+ *
+ *  @param priv    	A pointer to mlan_private
+ *  @param ta      ta to find in reordering table
+ *  @return 	   	N/A
+ */
+void wlan_cleanup_reorder_tbl(mlan_private *priv, t_u8 *ta)
+{
+    RxReorderTbl *rx_reor_tbl_ptr = MNULL;
+    t_u8 i;
+    ENTER();
+    for (i = 0; i < MAX_NUM_TID; ++i)
+    {
+        if ((rx_reor_tbl_ptr = wlan_11n_get_rxreorder_tbl(priv, i, ta)) != NULL)
+        {
+            wlan_11n_delete_rxreorder_tbl_entry(priv, rx_reor_tbl_ptr);
+        }
+    }
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function will set force_no_drop flag in rxreorder_tbl.
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param flag    MTRUE/MFALSE
+ *
+ *  @return	 N/A
+ */
+static void wlan_set_rxreorder_tbl_no_drop_flag(mlan_private *priv, bool flag)
+{
+    RxReorderTbl *rx_reor_tbl_ptr;
+
+    ENTER();
+    rx_reor_tbl_ptr = (RxReorderTbl *)(void *)util_peek_list(priv->adapter->pmoal_handle, &priv->rx_reorder_tbl_ptr,
+                                                             priv->adapter->callbacks.moal_spin_lock,
+                                                             priv->adapter->callbacks.moal_spin_unlock);
+    if (rx_reor_tbl_ptr == MNULL)
+    {
+        LEAVE();
+        return;
+    }
+
+    while (rx_reor_tbl_ptr != (RxReorderTbl *)(void *)&priv->rx_reorder_tbl_ptr)
+    {
+        rx_reor_tbl_ptr->force_no_drop = flag;
+        rx_reor_tbl_ptr                = rx_reor_tbl_ptr->pnext;
+    }
+
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function update all the rx_reorder_tbl's force_no_drop flag
+ *
+ *  @param pmadapter   	A pointer to mlan_adapter
+ *  @param flag		    MTRUE/MFALSE
+ *  @return 	        N/A
+ */
+void wlan_update_rxreorder_tbl(pmlan_adapter pmadapter, bool flag)
+{
+    t_u8 i;
+    pmlan_private priv = MNULL;
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        if (pmadapter->priv[i] != NULL)
+        {
+            priv = pmadapter->priv[i];
+            wlan_set_rxreorder_tbl_no_drop_flag(priv, flag);
+        }
+    }
+    return;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11v.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11v.c
new file mode 100644
index 0000000000..898f649172
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_11v.c
@@ -0,0 +1,401 @@
+/** @file mlan_11v.c
+ *
+ *  @brief  This file provides functions for process 11v(BTM) frames
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    08/11/2022: initial version
+********************************************************/
+
+#include <mlan_api.h>
+#ifndef RW610
+#include "wifi-sdio.h"
+#endif
+#if CONFIG_11V
+#define BTM_RESP_BUF_SIZE      200
+#define WNM_BTM_QUERY_BUF_SIZE 10U
+#define WLAN_FC_TYPE_MGMT      0
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+static void wlan_wnm_parse_neighbor_report(t_u8 *pos, t_u8 len, struct wnm_neighbor_report *rep)
+{
+    t_u8 remain_len = 0;
+    if (len < (t_u8)13U)
+    {
+        wifi_d("WNM: This neighbor report is too short");
+    }
+
+    (void)memcpy(rep->bssid, pos, MLAN_MAC_ADDR_LENGTH);
+    rep->bssid_info = wlan_cpu_to_le32(*(t_u32 *)(void *)(pos + MLAN_MAC_ADDR_LENGTH));
+    rep->reg_class  = *(pos + 10);
+    rep->channel    = *(pos + 11);
+    rep->PhyType    = *(pos + 12);
+    pos += 13;
+    remain_len = (t_u8)(len - (t_u8)13U);
+
+    while (remain_len >= (t_u8)2U)
+    {
+        t_u8 e_id, e_len;
+
+        e_id  = *pos++;
+        e_len = *pos++;
+        remain_len -= (t_u8)2U;
+        if (e_len > remain_len)
+        {
+            wifi_d("WNM: neighbor report length not matched");
+            break;
+        }
+        switch (e_id)
+        {
+            case MGMT_WNM_NEIGHBOR_BSS_TRANSITION_CANDIDATE:
+                if (e_len < (t_u8)1U)
+                {
+                    break;
+                }
+                rep->prefer        = pos[0];
+                rep->prefer_select = 1;
+                break;
+            default:
+                (void)PRINTF("UNKNOWN nbor Report e id\r\n");
+                break;
+        }
+
+        remain_len -= e_len;
+        pos += e_len;
+    }
+}
+
+void wlan_send_mgmt_wnm_btm_resp(t_u8 dialog_token,
+                                 enum wnm_btm_status_code status,
+                                 t_u8 *dst_addr,
+                                 t_u8 *src_addr,
+                                 t_u8 *target_bssid,
+                                 t_u8 *tag_nr,
+                                 t_u8 tag_len,
+                                 bool protect)
+{
+    wlan_mgmt_pkt *pmgmt_pkt_hdr    = MNULL;
+    IEEEtypes_FrameCtl_t *mgmt_fc_p = MNULL;
+    t_u8 *pos                       = MNULL;
+    t_u16 pkt_len                   = 0;
+
+    pmgmt_pkt_hdr = wifi_PrepDefaultMgtMsg(
+        SUBTYPE_ACTION, (mlan_802_11_mac_addr *)(void *)dst_addr, (mlan_802_11_mac_addr *)(void *)src_addr,
+        (mlan_802_11_mac_addr *)(void *)dst_addr, sizeof(wlan_mgmt_pkt) + (size_t)BTM_RESP_BUF_SIZE);
+    if (pmgmt_pkt_hdr == MNULL)
+    {
+        wifi_d("No memory available for BTM resp");
+        return;
+    }
+
+    mgmt_fc_p = (IEEEtypes_FrameCtl_t *)(void *)&pmgmt_pkt_hdr->wlan_header.frm_ctl;
+    if (protect)
+    {
+        mgmt_fc_p->wep = 1;
+    }
+
+    /* 802.11 management body */
+    pos    = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+    pos[0] = (t_u8)IEEE_MGMT_ACTION_CATEGORY_WNM;
+    pos[1] = (t_u8)IEEE_MGMT_WNM_BTM_RESPONSE;
+    pos[2] = dialog_token;
+    pos[3] = (t_u8)status;
+    pos[4] = 0; /* delay */
+    pos += 5;
+
+    if (target_bssid != NULL)
+    {
+        (void)memcpy((void *)pos, (const void *)target_bssid, (size_t)MLAN_MAC_ADDR_LENGTH);
+        pos += 6;
+    }
+    else if (status == WNM_BTM_ACCEPT)
+    {
+        (void)memcpy((void *)pos, "\0\0\0\0\0\0", (size_t)MLAN_MAC_ADDR_LENGTH);
+        pos += 6;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    if (status == WNM_BTM_ACCEPT && tag_nr != NULL)
+    {
+        (void)memcpy((void *)pos, (const void *)tag_nr, (size_t)tag_len);
+        pos += tag_len;
+    }
+    pkt_len                = (t_u16)(pos - (t_u8 *)pmgmt_pkt_hdr);
+    pmgmt_pkt_hdr->frm_len = (t_u16)((t_u16)pkt_len - sizeof(t_u16));
+    (void)wifi_inject_frame(WLAN_BSS_TYPE_STA, (t_u8 *)pmgmt_pkt_hdr, pkt_len);
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+}
+
+static bool wlan_11v_find_in_channels(t_u8 *channels, t_u8 entry_num, t_u8 chan)
+{
+    t_u8 i;
+    for (i = 0; i < entry_num; i++)
+    {
+        if (channels[i] == chan)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+/********************************************************
+                Global functions
+********************************************************/
+/**
+ *  @brief This function process BTM request frame
+ *
+ *  @param pos          BTM request frame head
+ *  @param end          end of frame
+ *  @param src_addr     source address
+ *
+ */
+void wlan_process_mgmt_wnm_btm_req(t_u8 *pos, t_u8 *end, t_u8 *src_addr, t_u8 *dest_addr, bool protect)
+{
+    t_u8 dialog_token;
+    t_u8 wnm_num_neighbor_report = 0, neighbor_index = 0;
+    t_u8 btm_mode;
+    t_u8 prefer_old = 0, prefer_select = 0;
+    t_u8 *ptagnr                              = NULL;
+    t_u8 tagnr_len                            = 0;
+    wlan_nlist_report_param *pnlist_rep_param = MNULL;
+    t_u8 entry_num                            = 0;
+
+    if (end - pos < 5)
+    {
+        return;
+    }
+
+#if !CONFIG_MEM_POOLS
+    pnlist_rep_param = (wlan_nlist_report_param *)OSA_MemoryAllocate(sizeof(wlan_nlist_report_param));
+#else
+    pnlist_rep_param = (wlan_nlist_report_param *)OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+
+    if (pnlist_rep_param == MNULL)
+    {
+        wifi_e("11v nlist report param buffer alloc failed %d", sizeof(wlan_nlist_report_param));
+        return;
+    }
+
+    (void)memset(pnlist_rep_param, 0, sizeof(wlan_nlist_report_param));
+
+    dialog_token = pos[0];
+    btm_mode     = pos[1];
+    pos += 5;
+
+    if ((btm_mode & IEEE_WNM_BTM_REQUEST_BSS_TERMINATION_INCLUDED) != 0U)
+    {
+        pos += 12; /* BSS Termination Duration */
+    }
+
+    if ((btm_mode & IEEE_WNM_BTM_REQUEST_PREFERENCE_CAND_LIST_INCLUDED) != 0U)
+    {
+#if !CONFIG_MEM_POOLS
+        struct wnm_neighbor_report *preport =
+            OSA_MemoryAllocate((size_t)WLAN_WNM_MAX_NEIGHBOR_REPORT * sizeof(struct wnm_neighbor_report));
+#else
+        struct wnm_neighbor_report *preport = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+        if (preport == NULL)
+        {
+            wifi_e("No memory available for neighbor report.");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+            return;
+        }
+
+        while (end - pos >= 2 && wnm_num_neighbor_report < (t_u8)WLAN_WNM_MAX_NEIGHBOR_REPORT)
+        {
+            t_u8 tag = *pos++;
+            t_u8 len = *pos++;
+
+            if ((int)len > (end - pos))
+            {
+                wifi_d("WNM: Truncated BTM request");
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)preport);
+                OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+                OSA_MemoryPoolFree(buf_128_MemoryPool, preport);
+                OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+                return;
+            }
+
+            if (tag == (t_u8)NEIGHBOR_REPORT)
+            {
+                struct wnm_neighbor_report *rep;
+                rep = &preport[wnm_num_neighbor_report];
+                wlan_wnm_parse_neighbor_report(pos, len, rep);
+                if (!wlan_11v_find_in_channels(pnlist_rep_param->channels, entry_num, rep->channel))
+                {
+                    pnlist_rep_param->channels[entry_num] = rep->channel;
+                    entry_num++;
+                }
+                if (rep->prefer_select != (t_u8)0U && (rep->prefer > prefer_old))
+                {
+                    ptagnr         = pos - 2;
+                    tagnr_len      = len + (t_u8)2U;
+                    prefer_old     = (t_u8)rep->prefer;
+                    prefer_select  = 1;
+                    neighbor_index = wnm_num_neighbor_report;
+                }
+                wnm_num_neighbor_report++;
+            }
+            pos += len;
+        }
+
+        if (wnm_num_neighbor_report == (t_u8)0U)
+        {
+            wlan_send_mgmt_wnm_btm_resp(dialog_token, WNM_BTM_REJECT_NO_SUITABLE_CANDIDATES, dest_addr, src_addr, NULL,
+                                        ptagnr, tagnr_len, protect);
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)preport);
+            OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, preport);
+            OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+
+            return;
+        }
+
+        if (prefer_select == (t_u8)1U)
+        {
+            wlan_send_mgmt_wnm_btm_resp(dialog_token, WNM_BTM_ACCEPT, dest_addr, src_addr,
+                                        preport[neighbor_index].bssid, ptagnr, tagnr_len, protect);
+
+            /* disconnect and re-assocate with AP2 */
+            pnlist_rep_param->nlist_mode   = WLAN_NLIST_11V_PREFERRED;
+            pnlist_rep_param->num_channels = 1;
+            pnlist_rep_param->channels[0]  = preport[neighbor_index].channel;
+            pnlist_rep_param->btm_mode     = btm_mode;
+            (void)memcpy((void *)pnlist_rep_param->bssid, (const void *)preport[neighbor_index].bssid,
+                         (size_t)MLAN_MAC_ADDR_LENGTH);
+        }
+        else
+        {
+            pnlist_rep_param->nlist_mode   = WLAN_NLIST_11V;
+            pnlist_rep_param->num_channels = entry_num;
+            pnlist_rep_param->btm_mode     = btm_mode;
+            pnlist_rep_param->dialog_token = dialog_token;
+            pnlist_rep_param->protect      = protect;
+            (void)memcpy((void *)pnlist_rep_param->dst_addr, (const void *)dest_addr, (size_t)MLAN_MAC_ADDR_LENGTH);
+        }
+
+        if (wifi_event_completion(WIFI_EVENT_NLIST_REPORT, WIFI_EVENT_REASON_SUCCESS, (void *)pnlist_rep_param) !=
+            WM_SUCCESS)
+        {
+            /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+        }
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(preport);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, preport);
+#endif
+    }
+    else
+    {
+        enum wnm_btm_status_code status;
+        if ((btm_mode & IEEE_WNM_BTM_REQUEST_ESS_DISASSOC_IMMINENT) != 0U)
+        {
+            status = WNM_BTM_ACCEPT;
+        }
+        else
+        {
+            status = WNM_BTM_REJECT_UNSPECIFIED;
+        }
+
+        wlan_send_mgmt_wnm_btm_resp(dialog_token, status, dest_addr, src_addr, NULL, ptagnr, tagnr_len, protect);
+        /* If don't use variable pnlist_rep_param, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+    }
+}
+
+int wlan_send_mgmt_bss_trans_query(mlan_private *pmpriv, t_u8 query_reason)
+{
+    t_u16 pkt_len;
+    mlan_802_11_mac_addr *da     = MNULL;
+    mlan_802_11_mac_addr *sa     = MNULL;
+    wlan_mgmt_pkt *pmgmt_pkt_hdr = MNULL;
+    t_u8 *pos                    = MNULL;
+    int meas_pkt_len             = 0;
+
+    if (pmpriv->bss_index != (t_u8)MLAN_BSS_ROLE_STA || pmpriv->media_connected != MTRUE)
+    {
+        wifi_d("invalid interface %d for sending neighbor report request", pmpriv->bss_index);
+        return (int)MLAN_STATUS_FAILURE;
+    }
+
+    da            = &pmpriv->curr_bss_params.bss_descriptor.mac_address;
+    sa            = (mlan_802_11_mac_addr *)(void *)(&pmpriv->curr_addr[0]);
+    pmgmt_pkt_hdr = wifi_PrepDefaultMgtMsg(SUBTYPE_ACTION, da, sa, da, sizeof(wlan_mgmt_pkt) + WNM_BTM_QUERY_BUF_SIZE);
+    if (pmgmt_pkt_hdr == MNULL)
+    {
+        wifi_e("No memory for bss transition management query");
+        return (int)MLAN_STATUS_FAILURE;
+    }
+
+    /* 802.11 management body */
+    pos    = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+    pos[0] = (t_u8)IEEE_MGMT_ACTION_CATEGORY_WNM;
+    pos[1] = (t_u8)IEEE_MGMT_WNM_BTM_QUERY;
+    pos[2] = pmpriv->bss_trans_query_token++;
+
+    if (pmpriv->bss_trans_query_token == (t_u8)255U)
+    {
+        pmpriv->bss_trans_query_token = (t_u8)1U;
+    }
+
+    pos[3] = query_reason;
+    pos += 4;
+
+    meas_pkt_len           = pos - (t_u8 *)pmgmt_pkt_hdr;
+    pkt_len                = (t_u16)meas_pkt_len;
+    pmgmt_pkt_hdr->frm_len = pkt_len - (t_u16)sizeof(pmgmt_pkt_hdr->frm_len);
+
+    (void)wifi_inject_frame(WLAN_BSS_TYPE_STA, (t_u8 *)pmgmt_pkt_hdr, pkt_len);
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+
+    return (int)MLAN_STATUS_SUCCESS;
+}
+#endif /* CONFIG_11V */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_action.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_action.c
new file mode 100644
index 0000000000..c581afc2ef
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_action.c
@@ -0,0 +1,187 @@
+/** @file mlan_action.c
+ *
+ *  @brief  This file provides functions for action management frame
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    08/11/2022: initial version
+********************************************************/
+
+#include <mlan_api.h>
+#include "wifi.h"
+#ifdef RW610
+#include "wifi-imu.h"
+#else
+#include "wifi-sdio.h"
+#endif
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+/**
+ *  @brief This function process rx radio measurement action frame
+ *
+ *  @param payload      rx frame including 802.11 header
+ *  @param payload_len  length of action frame
+ *  @param src_addr     source address
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_process_mgmt_radio_measurement_action(
+    t_u8 *payload, t_u32 payload_len, t_u8 *dest_addr, t_u8 *src_addr, RxPD *rxpd)
+{
+    t_u8 action_code = 0;
+    t_u8 *pos;
+    mlan_status ret = MLAN_STATUS_FAILURE;
+
+    pos         = payload + sizeof(wlan_802_11_header) + 1;
+    action_code = *pos++;
+#if CONFIG_11K
+    IEEEtypes_FrameCtl_t *mgmt_fc_p =
+        (IEEEtypes_FrameCtl_t *)(void *)&(((wlan_802_11_header *)(void *)payload)->frm_ctl);
+    payload_len -= (sizeof(wlan_802_11_header) + 2U);
+#endif
+
+    switch (action_code)
+    {
+#if CONFIG_11K
+        case (t_u8)IEEE_MGMT_RRM_RADIO_MEASUREMENT_REQUEST:
+        {
+            wlan_process_radio_measurement_request(pos, payload_len, dest_addr, src_addr, (bool)mgmt_fc_p->wep);
+            ret = MLAN_STATUS_SUCCESS;
+            break;
+        }
+        case (t_u8)IEEE_MGMT_RRM_LINK_MEASUREMENT_REQUEST:
+        {
+            wlan_process_link_measurement_request(pos, payload_len, dest_addr, src_addr, (bool)mgmt_fc_p->wep, rxpd);
+            ret = MLAN_STATUS_SUCCESS;
+            break;
+        }
+        case (t_u8)IEEE_MGMT_RRM_NEIGHBOR_REPORT_RESPONSE:
+        {
+            wlan_process_neighbor_report_response(pos, payload_len, dest_addr, src_addr, (bool)mgmt_fc_p->wep);
+            ret = MLAN_STATUS_SUCCESS;
+            break;
+        }
+#else
+        case 0:
+            break;
+#endif
+        default:
+            wifi_d("RRM: Unknown request: %u", action_code);
+            break;
+    }
+    return ret;
+}
+
+/**
+ *  @brief This function process rx action frame
+ *
+ *  @param payload      rx frame including 802.11 header
+ *  @param payload_len  length of action frame
+ *  @param src_addr     source address
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_process_mgmt_wnm_action(t_u8 *payload, t_u32 payload_len, t_u8 *src_addr, t_u8 *dest_addr)
+{
+    IEEEtypes_WNM_ActionFieldType_e action_code = (IEEEtypes_WNM_ActionFieldType_e)0;
+    t_u8 *pos;
+    mlan_status ret = MLAN_STATUS_FAILURE;
+
+    pos         = payload + sizeof(wlan_802_11_header) + 1;
+    action_code = (IEEEtypes_WNM_ActionFieldType_e)(*pos++);
+
+    switch (action_code)
+    {
+#if CONFIG_11V
+        case IEEE_MGMT_WNM_BTM_REQUEST:
+        {
+            IEEEtypes_FrameCtl_t *mgmt_fc_p =
+                (IEEEtypes_FrameCtl_t *)(void *)&(((wlan_802_11_header *)(void *)payload)->frm_ctl);
+
+            wlan_process_mgmt_wnm_btm_req(pos, (payload + payload_len), src_addr, dest_addr, (bool)mgmt_fc_p->wep);
+            ret = MLAN_STATUS_SUCCESS;
+            break;
+        }
+#endif
+        default:
+            wifi_d("WNM: Unknown request: %u", action_code);
+            break;
+    }
+    return ret;
+}
+
+static mlan_status wlan_process_mgmt_unprotect_wnm_action(t_u8 *payload, t_u32 payload_len, RxPD *rxpd)
+{
+    t_u8 action_code = 0;
+    t_u8 *pos;
+    mlan_status ret = MLAN_STATUS_FAILURE;
+
+    pos         = payload + sizeof(wlan_802_11_header) + 1;
+    action_code = *(pos++);
+
+    switch (action_code)
+    {
+        case 1:
+            break;
+        default:
+            wifi_d("unprotect WNM: Unknown request: %u", action_code);
+            break;
+    }
+    return ret;
+}
+
+
+/********************************************************
+                Global functions
+********************************************************/
+/**
+ *  @brief This function process rx action frame
+ *
+ *  @param payload      rx frame including 802.11 header
+ *  @param payload_len  length of action frame
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_process_mgmt_action(t_u8 *payload, t_u32 payload_len, RxPD *rxpd)
+{
+    wlan_802_11_header *pieee_pkt_hdr   = MNULL;
+    IEEEtypes_ActionCategory_e category = (IEEEtypes_ActionCategory_e)0;
+    mlan_status ret                     = MLAN_STATUS_FAILURE;
+
+    pieee_pkt_hdr = (wlan_802_11_header *)(void *)payload;
+    category      = (IEEEtypes_ActionCategory_e)(*(payload + sizeof(wlan_802_11_header)));
+
+    switch (category)
+    {
+        case IEEE_MGMT_ACTION_CATEGORY_RADIO_RSRC:
+            ret = wlan_process_mgmt_radio_measurement_action(payload, payload_len, pieee_pkt_hdr->addr1,
+                                                             pieee_pkt_hdr->addr2, rxpd);
+            break;
+        case IEEE_MGMT_ACTION_CATEGORY_WNM:
+            ret = wlan_process_mgmt_wnm_action(payload, payload_len, pieee_pkt_hdr->addr1, pieee_pkt_hdr->addr2);
+            break;
+        case IEEE_MGMT_ACTION_CATEGORY_UNPROTECT_WNM:
+            ret = wlan_process_mgmt_unprotect_wnm_action(payload, payload_len, rxpd);
+            break;
+        default:
+            wifi_d("Action: Unknown request: %u", category);
+            break;
+    }
+    return ret;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_api.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_api.c
new file mode 100644
index 0000000000..19171d4715
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_api.c
@@ -0,0 +1,6317 @@
+/** @file mlan_api.c
+ *
+ *  @brief This file provides more APIs for mlan.
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdio.h>
+#include <mlan_api.h>
+#if CONFIG_COMBO_SCAN
+#include <string.h>
+#endif
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+#include <wifi.h>
+
+#if defined(RW610)
+#include "wifi-imu.h"
+#else
+#include "wifi-sdio.h"
+#endif
+#include "wifi-internal.h"
+
+#if CONFIG_DRIVER_MBO
+#include "mlan_mbo.h"
+#endif
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+#if CONFIG_WLS_CSI_PROC
+#include <wls_param_defines.h>
+#include <wls_api.h>
+#include <wls_structure_defs.h>
+#include <range_kalman.h>
+#endif
+#endif
+
+static const char driver_version_format[] = "SD878x-%s-%s-WM";
+static const char driver_version[]        = "702.1.0";
+
+static unsigned int mgmt_ie_index_bitmap = 0x0000000F;
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+ftm_start_param ftm_param;
+#if CONFIG_WLS_CSI_PROC
+#define NL_MAX_PAYLOAD (3 * 1024)
+unsigned int csi_res_array[8];
+uint32_t wls_data[WLS_CSI_DATA_LEN_DW];
+range_kalman_state range_input_str = {0};
+#define RANGE_DRIVE_VAR       1e-5f // in meter/(s^2)
+#define RANGE_MEASUREMENT_VAR 4e-2f // in meter^2
+#define RANGE_RATE_INIT       1e-3f // in (meter/s)^2
+#define CSI_TSF_LEN           6 * sizeof(uint32_t)
+#define FFT_INBUFFER_LEN_DW   (MAX_RX * MAX_TX + NUM_PROC_BUF) * (MAX_IFFT_SIZE_CSI)
+uint32_t fftInBuffer_t[FFT_INBUFFER_LEN_DW];
+#endif
+#endif
+
+/* This were static functions in mlan file */
+mlan_status wlan_cmd_802_11_deauthenticate(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+mlan_status wlan_cmd_reg_access(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf);
+mlan_status wlan_cmd_mem_access(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf);
+mlan_status wlan_cmd_auto_reconnect(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf);
+mlan_status wlan_misc_ioctl_region(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+
+int wifi_set_mac_multicast_addr(const char *mlist, t_u32 num_of_addr);
+int wifi_send_disable_supplicant(int mode);
+int wifi_send_rf_channel_cmd(wifi_rf_channel_t *rf_channel);
+int wifi_get_set_rf_tx_power(t_u16 cmd_action, wifi_tx_power_t *tx_power);
+
+#ifdef RW610
+int wifi_send_shutdown_cmd()
+{
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    wifi_get_command_lock();
+
+    cmd->command = HostCmd_CMD_FUNC_SHUTDOWN;
+    cmd->size    = S_DS_GEN;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    wifi_wait_for_cmdresp(NULL);
+    return WM_SUCCESS;
+}
+#endif
+int wifi_deauthenticate(uint8_t *bssid)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    if (pmpriv->media_connected == MFALSE)
+    {
+        return WM_SUCCESS;
+    }
+
+    (void)wifi_get_command_lock();
+
+    /* fixme: check if this static selection is ok */
+    cmd->seq_num                      = 0x0;
+    cmd->result = 0x0;
+
+    (void)wlan_cmd_802_11_deauthenticate((mlan_private *)mlan_adap->priv[0], cmd, bssid);
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPA_SUPP
+#define REASON_CODE_PEER_STA_LEAVING 36
+int wifi_nxp_deauthenticate(unsigned int bss_type, const uint8_t *bssid, uint16_t reason_code)
+{
+    mlan_private *pmpriv                      = (mlan_private *)mlan_adap->priv[bss_type];
+    HostCmd_DS_COMMAND *cmd                   = wifi_get_command_buffer();
+    HostCmd_DS_802_11_DEAUTHENTICATE *pdeauth = &cmd->params.deauth;
+
+    pmpriv->curr_bss_params.host_mlme = 0;
+    pmpriv->auth_flag                 = 0;
+    pmpriv->auth_alg                  = 0xFFFF;
+
+    if (pmpriv->media_connected == MFALSE)
+    {
+        return WM_SUCCESS;
+    }
+
+    (void)wifi_get_command_lock();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_DEAUTHENTICATE);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_DEAUTHENTICATE) + S_DS_GEN);
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+    cmd->result  = 0x0;
+
+    /* Set AP MAC address */ (void)memcpy((void *)pdeauth->mac_addr, (const void *)bssid, (size_t)MLAN_MAC_ADDR_LENGTH);
+
+    wifi_d("Deauth: %02x:%02x:%02x:%02x:%02x:%02x", pdeauth->mac_addr[0], pdeauth->mac_addr[1], pdeauth->mac_addr[2],
+           pdeauth->mac_addr[3], pdeauth->mac_addr[4], pdeauth->mac_addr[5]);
+
+    if (pmpriv->adapter->state_11h.recvd_chanswann_event)
+    { /** Reason code 36 = Requested from peer station as it is leaving the BSS */
+        pdeauth->reason_code = wlan_cpu_to_le16(REASON_CODE_PEER_STA_LEAVING);
+    }
+    else
+    {
+        pdeauth->reason_code = wlan_cpu_to_le16(reason_code);
+    }
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    return WM_SUCCESS;
+}
+#endif
+
+int wifi_get_eeprom_data(uint32_t offset, uint32_t byte_count, uint8_t *buf)
+{
+    mlan_ds_read_eeprom eeprom_rd;
+    eeprom_rd.offset     = offset;
+    eeprom_rd.byte_count = byte_count;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command = HostCmd_CMD_802_11_EEPROM_ACCESS;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    (void)wlan_cmd_reg_access(cmd, HostCmd_ACT_GEN_GET, &eeprom_rd);
+    (void)wifi_wait_for_cmdresp(buf);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_reg_access(wifi_reg_t reg_type, uint16_t action, uint32_t offset, uint32_t *value)
+{
+    mlan_ds_reg_rw reg_rw;
+    reg_rw.offset = offset;
+    reg_rw.value  = *value;
+    uint16_t hostcmd;
+    int ret = WM_SUCCESS;
+    switch (reg_type)
+    {
+        case REG_MAC:
+            hostcmd = HostCmd_CMD_MAC_REG_ACCESS;
+            break;
+        case REG_BBP:
+            hostcmd = HostCmd_CMD_BBP_REG_ACCESS;
+            break;
+        case REG_RF:
+            hostcmd = HostCmd_CMD_RF_REG_ACCESS;
+            break;
+        case REG_CAU:
+            hostcmd = HostCmd_CMD_CAU_REG_ACCESS;
+            break;
+        default:
+            wifi_e("Incorrect register type");
+            ret = -WM_FAIL;
+            break;
+    }
+
+    if (ret != WM_SUCCESS)
+    {
+        return ret;
+    }
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command = hostcmd;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    (void)wlan_cmd_reg_access(cmd, action, &reg_rw);
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? value : NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_mem_access(uint16_t action, uint32_t addr, uint32_t *value)
+{
+    mlan_ds_mem_rw mem_rw;
+    mem_rw.addr  = addr;
+    mem_rw.value = *value;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command = HostCmd_CMD_MEM_ACCESS;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    (void)wlan_cmd_mem_access(cmd, action, &mem_rw);
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? value : NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+#if CONFIG_WIFI_BOOT_SLEEP
+int wifi_boot_sleep(uint16_t action, uint16_t *enable)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command = HostCmd_CMD_BOOT_SLEEP;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    (void)wlan_cmd_boot_sleep(pmpriv, cmd, action, enable);
+
+    (void)wifi_wait_for_cmdresp(enable);
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_AUTO_RECONNECT
+static int wifi_auto_reconnect(uint16_t action, wifi_auto_reconnect_config_t *auto_reconnect_config)
+{
+    mlan_ds_auto_reconnect auto_reconnect;
+
+    (void)memset(&auto_reconnect, 0x00, sizeof(mlan_ds_auto_reconnect));
+
+    if (auto_reconnect_config)
+    {
+        auto_reconnect.reconnect_counter  = auto_reconnect_config->reconnect_counter;
+        auto_reconnect.reconnect_interval = auto_reconnect_config->reconnect_interval;
+        auto_reconnect.flags              = auto_reconnect_config->flags;
+    }
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command = HostCmd_CMD_AUTO_RECONNECT;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    wlan_cmd_auto_reconnect(cmd, action, &auto_reconnect);
+
+    wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? auto_reconnect_config : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_auto_reconnect_enable(wifi_auto_reconnect_config_t auto_reconnect_config)
+{
+    return wifi_auto_reconnect(HostCmd_ACT_GEN_SET, &auto_reconnect_config);
+}
+
+int wifi_auto_reconnect_disable(void)
+{
+    return wifi_auto_reconnect(HostCmd_ACT_GEN_SET, NULL);
+}
+
+int wifi_get_auto_reconnect_config(wifi_auto_reconnect_config_t *auto_reconnect_config)
+{
+    return wifi_auto_reconnect(HostCmd_ACT_GEN_GET, auto_reconnect_config);
+}
+#endif
+
+int wifi_get_tsf(uint32_t *tsf_high, uint32_t *tsf_low)
+{
+    t_u64 tsf = 0x00;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_GET_TSF,
+                                              HostCmd_ACT_GEN_GET, 0, NULL, NULL, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(&tsf);
+
+    *tsf_high = tsf >> 32;
+    *tsf_low  = (t_u32)tsf;
+
+    return wm_wifi.cmd_resp_status;
+}
+
+
+int wifi_send_rssi_info_cmd(wifi_rssi_info_t *rssi_info)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_RSSI_INFO,
+                                              HostCmd_ACT_GEN_GET, 0, NULL, NULL, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(rssi_info);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_send_rf_channel_cmd(wifi_rf_channel_t *rf_channel)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    /*
+      SET operation is not supported according to spec. So we are
+      sending NULL as one param below.
+    */
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_RF_CHANNEL,
+                                              HostCmd_ACT_GEN_GET, 0, NULL, NULL, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(rf_channel);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_send_remain_on_channel_cmd(unsigned int bss_type, wifi_remain_on_channel_t *remain_on_channel)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, bss_type);
+    cmd->result  = 0x0;
+    /*save remain on channel bss index*/
+    mlan_adap->remain_bss_index = mlan_adap->priv[bss_type]->bss_index;
+    mlan_status rv =
+        wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[bss_type], HostCmd_CMD_802_11_REMAIN_ON_CHANNEL,
+                                 HostCmd_ACT_GEN_SET, 0, NULL, remain_on_channel, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+/* power_level is not used when cmd_action is GET */
+int wifi_get_set_rf_tx_power(t_u16 cmd_action, wifi_tx_power_t *tx_power)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num   = 0x0;
+    cmd->result    = 0x0;
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_RF_TX_POWER,
+                                              cmd_action, 0, NULL, &tx_power->current_level, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(cmd_action == HostCmd_ACT_GEN_GET ? tx_power : NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_data_rate(wifi_ds_rate *ds_rate, mlan_bss_type bss_type)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+    cmd->result  = 0x0;
+
+    mlan_status rv = MLAN_STATUS_SUCCESS;
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        if (is_uap_started())
+            rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[1], HostCmd_CMD_802_11_TX_RATE_QUERY, 0, 0,
+                                          NULL, NULL, cmd);
+        else
+            wifi_e("uap isn't up\n\r");
+    }
+    else if (bss_type == MLAN_BSS_TYPE_STA)
+    {
+        if (is_sta_connected())
+            rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_TX_RATE_QUERY, 0, 0,
+                                          NULL, NULL, cmd);
+        else
+            wifi_e("sta connection required before setting tx rate\n\r");
+    }
+
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        wifi_put_command_lock();
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(ds_rate);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_set_pmfcfg(t_u8 mfpc, t_u8 mfpr)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    pmpriv->pmfcfg.mfpc = mfpc;
+    pmpriv->pmfcfg.mfpr = mfpr;
+
+    return WM_SUCCESS;
+}
+
+int wifi_get_pmfcfg(t_u8 *mfpc, t_u8 *mfpr)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    *mfpc = pmpriv->pmfcfg.mfpc;
+    *mfpr = pmpriv->pmfcfg.mfpr;
+
+    return WM_SUCCESS;
+}
+
+int wifi_uap_get_pmfcfg(t_u8 *mfpc, t_u8 *mfpr)
+{
+    return wifi_uap_pmf_getset(HostCmd_ACT_GEN_GET, mfpc, mfpr);
+}
+
+
+int wifi_set_packet_filters(wifi_flt_cfg_t *flt_cfg)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    HostCmd_DS_MEF_CFG *mef_hdr;
+    mef_entry_header *entry_hdr;
+    t_u8 *buf = (t_u8 *)cmd, *filter_buf = NULL;
+    t_u32 buf_len;
+    int i, j;
+    mef_op op;
+    t_u32 dnum;
+
+    (void)memset(cmd, 0, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MEF_CFG);
+    buf_len      = S_DS_GEN;
+
+    /** Fill HostCmd_DS_MEF_CFG */
+    mef_hdr           = (HostCmd_DS_MEF_CFG *)(void *)(buf + buf_len);
+    mef_hdr->criteria = wlan_cpu_to_le32(flt_cfg->criteria);
+    mef_hdr->nentries = wlan_cpu_to_le16(flt_cfg->nentries);
+    buf_len += sizeof(HostCmd_DS_MEF_CFG);
+
+    for (i = 0; i < flt_cfg->nentries; i++)
+    {
+        /** Fill entry header data */
+        entry_hdr         = (mef_entry_header *)(buf + buf_len);
+        entry_hdr->mode   = flt_cfg->mef_entry[i].mode;
+        entry_hdr->action = flt_cfg->mef_entry[i].action;
+        buf_len += sizeof(mef_entry_header);
+        for (j = 0; j < flt_cfg->mef_entry[i].filter_num; j++)
+        {
+            if (flt_cfg->mef_entry[i].filter_item[j].type == TYPE_DNUM_EQ)
+            {
+                /* Format of decimal num:
+                 * |   5 bytes  |    5 bytes    |    5 bytes    |        1 byte         |
+                 * |   pattern  |     offset    |  num of bytes |  type (TYPE_DNUM_EQ)  |
+                 */
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push pattern */
+                op.operand_type = OPERAND_DNUM;
+                dnum            = flt_cfg->mef_entry[i].filter_item[j].pattern;
+                (void)memcpy(filter_buf, &dnum, sizeof(dnum));
+                (void)memcpy(filter_buf + sizeof(dnum), &(op.operand_type), 1);
+                buf_len += sizeof(dnum) + 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push offset */
+                op.operand_type = OPERAND_DNUM;
+                dnum            = flt_cfg->mef_entry[i].filter_item[j].offset;
+                (void)memcpy(filter_buf, &dnum, sizeof(dnum));
+                (void)memcpy(filter_buf + sizeof(dnum), &(op.operand_type), 1);
+                buf_len += sizeof(dnum) + 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push num of bytes */
+                op.operand_type = OPERAND_DNUM;
+                dnum            = flt_cfg->mef_entry[i].filter_item[j].num_bytes;
+                (void)memcpy(filter_buf, &dnum, sizeof(dnum));
+                (void)memcpy(filter_buf + sizeof(dnum), &(op.operand_type), 1);
+                buf_len += sizeof(dnum) + 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push type */
+                op.operand_type = TYPE_DNUM_EQ;
+                (void)memcpy(filter_buf, &(op.operand_type), 1);
+                buf_len += 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+            }
+            else if (flt_cfg->mef_entry[i].filter_item[j].type == TYPE_BYTE_EQ)
+            {
+                /* Format of byte seq:
+                 * |   5 bytes  |      val      |    5 bytes    |        1 byte         |
+                 * |   repeat   |   bytes seq   |    offset     |  type (TYPE_BYTE_EQ)  |
+                 */
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push repeat */
+                op.operand_type = OPERAND_DNUM;
+                dnum            = flt_cfg->mef_entry[i].filter_item[j].repeat;
+                (void)memcpy(filter_buf, &dnum, sizeof(dnum));
+                (void)memcpy(filter_buf + sizeof(dnum), &(op.operand_type), 1);
+                buf_len += sizeof(dnum) + 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push bytes seq */
+                op.operand_type = OPERAND_BYTE_SEQ;
+                (void)memcpy(filter_buf, flt_cfg->mef_entry[i].filter_item[j].byte_seq,
+                             flt_cfg->mef_entry[i].filter_item[j].num_byte_seq);
+                (void)memcpy(filter_buf + flt_cfg->mef_entry[i].filter_item[j].num_byte_seq,
+                             &(flt_cfg->mef_entry[i].filter_item[j].num_byte_seq), 1);
+                (void)memcpy(filter_buf + flt_cfg->mef_entry[i].filter_item[j].num_byte_seq + 1, &(op.operand_type), 1);
+                buf_len += flt_cfg->mef_entry[i].filter_item[j].num_byte_seq + 2;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push offset */
+                op.operand_type = OPERAND_DNUM;
+                dnum            = flt_cfg->mef_entry[i].filter_item[j].offset;
+                (void)memcpy(filter_buf, &dnum, sizeof(dnum));
+                (void)memcpy(filter_buf + sizeof(dnum), &(op.operand_type), 1);
+                buf_len += sizeof(dnum) + 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push type */
+                op.operand_type = TYPE_BYTE_EQ;
+                (void)memcpy(filter_buf, &(op.operand_type), 1);
+                buf_len += 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+            }
+            else if (flt_cfg->mef_entry[i].filter_item[j].type == TYPE_BIT_EQ)
+            {
+                /* Format of bit seq:
+                 * |   val      |    5 bytes    |      val      |        1 byte         |
+                 * | bytes seq  |    offset     |    mask seq   |  type (TYPE_BIT_EQ)   |
+                 */
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push bytes seq */
+                op.operand_type = OPERAND_BYTE_SEQ;
+                (void)memcpy(filter_buf, flt_cfg->mef_entry[i].filter_item[j].byte_seq,
+                             flt_cfg->mef_entry[i].filter_item[j].num_byte_seq);
+                (void)memcpy(filter_buf + flt_cfg->mef_entry[i].filter_item[j].num_byte_seq,
+                             &(flt_cfg->mef_entry[i].filter_item[j].num_byte_seq), 1);
+                (void)memcpy(filter_buf + flt_cfg->mef_entry[i].filter_item[j].num_byte_seq + 1, &(op.operand_type), 1);
+                buf_len += flt_cfg->mef_entry[i].filter_item[j].num_byte_seq + 2;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push offset */
+                op.operand_type = OPERAND_DNUM;
+                dnum            = flt_cfg->mef_entry[i].filter_item[j].offset;
+                (void)memcpy(filter_buf, &dnum, sizeof(dnum));
+                (void)memcpy(filter_buf + sizeof(dnum), &(op.operand_type), 1);
+                buf_len += sizeof(dnum) + 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push mask seq */
+                op.operand_type = OPERAND_BYTE_SEQ;
+                (void)memcpy(filter_buf, flt_cfg->mef_entry[i].filter_item[j].mask_seq,
+                             flt_cfg->mef_entry[i].filter_item[j].num_mask_seq);
+                (void)memcpy(filter_buf + flt_cfg->mef_entry[i].filter_item[j].num_mask_seq,
+                             &(flt_cfg->mef_entry[i].filter_item[j].num_mask_seq), 1);
+                (void)memcpy(filter_buf + flt_cfg->mef_entry[i].filter_item[j].num_mask_seq + 1, &(op.operand_type), 1);
+                buf_len += flt_cfg->mef_entry[i].filter_item[j].num_mask_seq + 2;
+                filter_buf = (t_u8 *)(buf + buf_len);
+
+                /* push type */
+                op.operand_type = TYPE_BIT_EQ;
+                (void)memcpy(filter_buf, &(op.operand_type), 1);
+                buf_len += 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+            }
+            else
+                goto done;
+            if (j != 0)
+            {
+                filter_buf      = (t_u8 *)(buf + buf_len);
+                op.operand_type = flt_cfg->mef_entry[i].rpn[j];
+                (void)memcpy(filter_buf, &(op.operand_type), 1);
+                buf_len += 1;
+                filter_buf = (t_u8 *)(buf + buf_len);
+            }
+        }
+        if (filter_buf != NULL)
+            entry_hdr->len = (t_u32)filter_buf - (t_u32)entry_hdr - sizeof(mef_entry_header);
+    }
+
+    cmd->size = wlan_cpu_to_le16(buf_len);
+done:
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+#define FLTR_BUF_IP_OFFSET 24
+
+int wifi_set_auto_arp(t_u32 *ipv4_addr)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    HostCmd_DS_MEF_CFG *mef_hdr;
+    t_u8 *buf = (t_u8 *)cmd, *filter = NULL;
+    t_u32 buf_len;
+    t_u8 fltr_buf[] = {0x01, 0x10, 0x21, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x08, 0x06, 0x02, 0x02,
+                       0x14, 0x00, 0x00, 0x00, 0x01, 0x41, 0x01, 0x00, 0x00, 0x00, 0x01, 0xc0, 0xa8,
+                       0x01, 0x6d, 0x04, 0x02, 0x2e, 0x00, 0x00, 0x00, 0x01, 0x41, 0x44};
+
+    (void)memset(cmd, 0, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MEF_CFG);
+    buf_len      = S_DS_GEN;
+
+    /** Fill HostCmd_DS_MEF_CFG*/
+    mef_hdr           = (HostCmd_DS_MEF_CFG *)(buf + buf_len);
+    mef_hdr->criteria = wlan_cpu_to_le32(MBIT(0) | MBIT(1) | MBIT(3));
+    mef_hdr->nentries = wlan_cpu_to_le16(1);
+    buf_len += sizeof(HostCmd_DS_MEF_CFG);
+
+    filter = buf + buf_len;
+    (void)memcpy((void *)filter, (const void *)fltr_buf, sizeof(fltr_buf));
+    (void)memcpy((void *)&filter[FLTR_BUF_IP_OFFSET], (const void *)ipv4_addr, sizeof(t_u32));
+    buf_len += sizeof(fltr_buf);
+
+    cmd->size = wlan_cpu_to_le16(buf_len);
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_tcp_keep_alive(wifi_tcp_keep_alive_t *keep_alive, t_u8 *src_mac, t_u32 src_ip)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    t_u16 cmd_action        = HostCmd_ACT_GEN_SET;
+
+    HostCmd_DS_AUTO_TX *auto_tx_cmd = (HostCmd_DS_AUTO_TX *)((t_u8 *)cmd + S_DS_GEN);
+    t_u8 *pos                       = (t_u8 *)auto_tx_cmd + sizeof(auto_tx_cmd->action);
+    t_u16 len                       = 0;
+
+    MrvlIEtypes_Cloud_Keep_Alive_t *keep_alive_tlv = MNULL;
+    MrvlIEtypes_Keep_Alive_Ctrl_t *ctrl_tlv        = MNULL;
+    MrvlIEtypes_Keep_Alive_Pkt_t *pkt_tlv          = MNULL;
+    t_u8 eth_ip[]                                  = {0x08, 0x00};
+    t_u8 ip_packet[67] = {0x45, 0x00, 0x00, 0x43, 0x8c, 0x9e, 0x00, 0x00, 0xff, 0x06, 0xac, 0xbf, 0xc0, 0xa8,
+                          0x00, 0x7c, 0xc0, 0xa8, 0x00, 0x8a, 0xc0, 0x03, 0x22, 0xb7, 0xb0, 0xb6, 0x60, 0x9f,
+                          0x42, 0xdd, 0x9e, 0x1e, 0x50, 0x18, 0x80, 0x00, 0xd0, 0x88, 0x00, 0x00, 0x74, 0x68,
+                          0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x61, 0x20, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x61,
+                          0x6c, 0x69, 0x76, 0x65, 0x20, 0x70, 0x61, 0x63, 0x6b, 0x65, 0x74};
+#if 0
+	t_u8 ip_packet2[41] = {0x45, 0x00, 0x00, 0x29, 0x76, 0x51, 0x40, 0x00, 0x80, 0x06, 0xf2, 0x4c, 0xc0, 0xa8, 0x01, 0x0a, 0xc0, 0xa8, 0x01, 0x0c, 0xfb, 0xd8, 0x01, 0xbd, 0x76, 0xe3, 0x34, 0x62, 0x06, 0x80, 0x8b, 0x62, 0x50, 0x10, 0x01, 0x00, 0xe1, 0xe4, 0x00, 0x00, 0x00};
+#endif
+    t_u16 pkt_len = 67;
+
+    if (keep_alive->reset)
+        cmd_action = HostCmd_ACT_GEN_RESET;
+
+    cmd->command        = wlan_cpu_to_le16(HostCmd_CMD_AUTO_TX);
+    cmd->size           = S_DS_GEN + sizeof(HostCmd_DS_AUTO_TX);
+    auto_tx_cmd->action = wlan_cpu_to_le16(cmd_action);
+
+    keep_alive_tlv = (MrvlIEtypes_Cloud_Keep_Alive_t *)pos;
+
+    keep_alive_tlv->header.type   = wlan_cpu_to_le16(TLV_TYPE_CLOUD_KEEP_ALIVE);
+    keep_alive_tlv->keep_alive_id = 1; // keep_alive->mkeep_alive_id;
+    keep_alive_tlv->enable        = keep_alive->enable;
+    len                           = len + sizeof(keep_alive_tlv->keep_alive_id) + sizeof(keep_alive_tlv->enable);
+    pos                           = pos + len + sizeof(MrvlIEtypesHeader_t);
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        if (keep_alive->enable)
+        {
+            ctrl_tlv              = (MrvlIEtypes_Keep_Alive_Ctrl_t *)pos;
+            ctrl_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_KEEP_ALIVE_CTRL);
+            ctrl_tlv->header.len =
+                wlan_cpu_to_le16(sizeof(MrvlIEtypes_Keep_Alive_Ctrl_t) - sizeof(MrvlIEtypesHeader_t));
+            ctrl_tlv->snd_interval   = wlan_cpu_to_le32(keep_alive->timeout);
+            ctrl_tlv->retry_interval = wlan_cpu_to_le16(keep_alive->interval);
+            ctrl_tlv->retry_count    = wlan_cpu_to_le16(keep_alive->max_keep_alives);
+            len                      = len + sizeof(MrvlIEtypes_Keep_Alive_Ctrl_t);
+
+            pos                  = pos + sizeof(MrvlIEtypes_Keep_Alive_Ctrl_t);
+            pkt_tlv              = (MrvlIEtypes_Keep_Alive_Pkt_t *)pos;
+            pkt_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_KEEP_ALIVE_PKT);
+            (void)memcpy((void *)pkt_tlv->eth_header.dest_addr, (const void *)keep_alive->dst_mac,
+                         MLAN_MAC_ADDR_LENGTH);
+            (void)memcpy((void *)pkt_tlv->eth_header.src_addr, (const void *)src_mac, MLAN_MAC_ADDR_LENGTH);
+            (void)memcpy((void *)((t_u8 *)&pkt_tlv->eth_header.h803_len), (const void *)eth_ip, sizeof(t_u16));
+            (void)memcpy((void *)(ip_packet + 12), (const void *)&src_ip, sizeof(t_u32));
+            (void)memcpy((void *)(ip_packet + 16), (const void *)&keep_alive->dst_ip, sizeof(t_u32));
+            (void)memcpy((void *)pkt_tlv->ip_packet, (const void *)ip_packet, pkt_len);
+            pkt_tlv->header.len = wlan_cpu_to_le16(sizeof(Eth803Hdr_t) + pkt_len);
+            len                 = len + sizeof(MrvlIEtypesHeader_t) + sizeof(Eth803Hdr_t) + pkt_len;
+        }
+        else
+        {
+            pkt_tlv              = (MrvlIEtypes_Keep_Alive_Pkt_t *)pos;
+            pkt_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_KEEP_ALIVE_PKT);
+            pkt_tlv->header.len  = 0;
+            len                  = len + sizeof(MrvlIEtypesHeader_t);
+        }
+    }
+    if (cmd_action == HostCmd_ACT_GEN_RESET)
+    {
+        pkt_tlv              = (MrvlIEtypes_Keep_Alive_Pkt_t *)pos;
+        pkt_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_KEEP_ALIVE_PKT);
+        pkt_tlv->header.len  = 0;
+        len                  = len + sizeof(MrvlIEtypesHeader_t);
+    }
+    keep_alive_tlv->header.len = wlan_cpu_to_le16(len);
+
+    cmd->size = cmd->size + len + sizeof(MrvlIEtypesHeader_t);
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x00;
+
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+int wifi_cloud_keep_alive(wifi_cloud_keep_alive_t *keep_alive, t_u16 action, t_u8 *enable)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    t_u16 cmd_action;
+    HostCmd_DS_AUTO_TX *auto_tx_cmd                = (HostCmd_DS_AUTO_TX *)((t_u8 *)cmd + S_DS_GEN);
+    t_u8 *pos                                      = (t_u8 *)auto_tx_cmd + sizeof(auto_tx_cmd->action);
+    t_u16 len                                      = 0;
+    MrvlIEtypes_Cloud_Keep_Alive_t *keep_alive_tlv = MNULL;
+
+    if (keep_alive == NULL)
+        return -WM_E_INVAL;
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_STA);
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_AUTO_TX);
+    cmd->size    = S_DS_GEN + sizeof(HostCmd_DS_AUTO_TX);
+
+    if ((action == MLAN_ACT_GET) && (enable != NULL))
+    {
+        cmd_action = HostCmd_ACT_GEN_GET;
+    }
+    else if ((action == MLAN_ACT_SET) && !keep_alive->reset)
+    {
+        cmd_action = HostCmd_ACT_GEN_SET;
+    }
+    else if ((action == MLAN_ACT_SET) && keep_alive->reset)
+    {
+        cmd_action = HostCmd_ACT_GEN_RESET;
+    }
+    else
+    {
+        return -WM_E_INVAL;
+    }
+    auto_tx_cmd->action = wlan_cpu_to_le16(cmd_action);
+
+    keep_alive_tlv = (MrvlIEtypes_Cloud_Keep_Alive_t *)pos;
+
+    keep_alive_tlv->header.type   = wlan_cpu_to_le16(TLV_TYPE_CLOUD_KEEP_ALIVE);
+    keep_alive_tlv->keep_alive_id = keep_alive->mkeep_alive_id;
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        keep_alive_tlv->enable     = MFALSE;
+        len                        = len + sizeof(keep_alive_tlv->keep_alive_id) + sizeof(keep_alive_tlv->enable);
+        keep_alive_tlv->header.len = wlan_cpu_to_le16(len);
+
+        cmd->size = cmd->size + len + sizeof(MrvlIEtypesHeader_t);
+        cmd->size = wlan_cpu_to_le16(cmd->size);
+    }
+    else if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        if (keep_alive->enable)
+        {
+            MrvlIEtypes_Keep_Alive_Ctrl_t *ctrl_tlv = MNULL;
+            MrvlIEtypes_Keep_Alive_Pkt_t *pkt_tlv   = MNULL;
+            t_u8 eth_ip[]                           = {0x08, 0x00};
+
+            keep_alive_tlv->enable = keep_alive->enable;
+            len                    = len + sizeof(keep_alive_tlv->keep_alive_id) + sizeof(keep_alive_tlv->enable);
+            pos                    = pos + len + sizeof(MrvlIEtypesHeader_t);
+            ctrl_tlv               = (MrvlIEtypes_Keep_Alive_Ctrl_t *)pos;
+            ctrl_tlv->header.type  = wlan_cpu_to_le16(TLV_TYPE_KEEP_ALIVE_CTRL);
+            ctrl_tlv->header.len =
+                wlan_cpu_to_le16(sizeof(MrvlIEtypes_Keep_Alive_Ctrl_t) - sizeof(MrvlIEtypesHeader_t));
+            ctrl_tlv->snd_interval   = wlan_cpu_to_le32(keep_alive->send_interval);
+            ctrl_tlv->retry_interval = wlan_cpu_to_le16(keep_alive->retry_interval);
+            ctrl_tlv->retry_count    = wlan_cpu_to_le16(keep_alive->retry_count);
+            len                      = len + sizeof(MrvlIEtypes_Keep_Alive_Ctrl_t);
+
+            pos                  = pos + sizeof(MrvlIEtypes_Keep_Alive_Ctrl_t);
+            pkt_tlv              = (MrvlIEtypes_Keep_Alive_Pkt_t *)pos;
+            pkt_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_KEEP_ALIVE_PKT);
+            (void)memcpy(pkt_tlv->eth_header.dest_addr, keep_alive->dst_mac, MLAN_MAC_ADDR_LENGTH);
+            (void)memcpy(pkt_tlv->eth_header.src_addr, keep_alive->src_mac, MLAN_MAC_ADDR_LENGTH);
+            (void)memcpy((t_u8 *)&pkt_tlv->eth_header.h803_len, eth_ip, sizeof(t_u16));
+            (void)memcpy(pkt_tlv->ip_packet, keep_alive->packet, keep_alive->pkt_len);
+            pkt_tlv->header.len        = wlan_cpu_to_le16(sizeof(Eth803Hdr_t) + keep_alive->pkt_len);
+            len                        = len + sizeof(MrvlIEtypesHeader_t) + sizeof(Eth803Hdr_t) + keep_alive->pkt_len;
+            keep_alive_tlv->header.len = wlan_cpu_to_le16(len);
+
+            cmd->size = cmd->size + len + sizeof(MrvlIEtypesHeader_t);
+            cmd->size = wlan_cpu_to_le16(cmd->size);
+        }
+        else
+        {
+            keep_alive_tlv->enable     = MFALSE;
+            len                        = len + sizeof(keep_alive_tlv->keep_alive_id) + sizeof(keep_alive_tlv->enable);
+            keep_alive_tlv->header.len = wlan_cpu_to_le16(len);
+
+            cmd->size = cmd->size + len + sizeof(MrvlIEtypesHeader_t);
+            cmd->size = wlan_cpu_to_le16(cmd->size);
+        }
+    }
+    else if (cmd_action == HostCmd_ACT_GEN_RESET)
+    {
+        keep_alive_tlv->enable     = MFALSE;
+        len                        = len + sizeof(keep_alive_tlv->keep_alive_id) + sizeof(keep_alive_tlv->enable);
+        keep_alive_tlv->header.len = wlan_cpu_to_le16(len);
+
+        cmd->size = cmd->size + len + sizeof(MrvlIEtypesHeader_t);
+        cmd->size = wlan_cpu_to_le16(cmd->size);
+    }
+
+    cmd->result = 0x00;
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        wifi_wait_for_cmdresp((void *)enable);
+    }
+    else
+    {
+        wifi_wait_for_cmdresp(NULL);
+    }
+
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_RF_TEST_MODE
+#ifdef RW610
+/* 802.11n/a/g/b data rate IDs */
+#define DATARATE_1M  0x0001
+#define DATARATE_2M  0x0002
+#define DATARATE5_5M 0x0003
+#define DATARATE_11M 0x0004
+#define RESERVED_1   0x0005
+
+#define DATARATE_6M  0x0006
+#define DATARATE_9M  0x0007
+#define DATARATE_12M 0x0008
+#define DATARATE_18M 0x0009
+#define DATARATE_24M 0x000A
+#define DATARATE_36M 0x000B
+#define DATARATE_48M 0x000C
+#define DATARATE_54M 0x000D
+#define RESERVED_2   0x000E
+
+#define HT_MCS0 0x000F
+#define HT_MCS1 0x0010
+#define HT_MCS2 0x0011
+#define HT_MCS3 0x0012
+#define HT_MCS4 0x0013
+#define HT_MCS5 0x0014
+#define HT_MCS6 0x0015
+#define HT_MCS7 0x0016
+
+/* 802.11ac VHT MCS rates ID */
+#define VHT_SS1_MCS0 0x1100
+#define VHT_SS1_MCS1 0x1101
+#define VHT_SS1_MCS2 0x1102
+#define VHT_SS1_MCS3 0x1103
+#define VHT_SS1_MCS4 0x1104
+#define VHT_SS1_MCS5 0x1105
+#define VHT_SS1_MCS6 0x1106
+#define VHT_SS1_MCS7 0x1107
+#define VHT_SS1_MCS8 0x1108
+
+/* 802.11ax HE MCS rates ID */
+#define HE_SS1_MCS0 0x2100
+#define HE_SS1_MCS1 0x2101
+#define HE_SS1_MCS2 0x2102
+#define HE_SS1_MCS3 0x2103
+#define HE_SS1_MCS4 0x2104
+#define HE_SS1_MCS5 0x2105
+#define HE_SS1_MCS6 0x2106
+#define HE_SS1_MCS7 0x2107
+#define HE_SS1_MCS8 0x2108
+#define HE_SS1_MCS9 0x2109
+
+static uint32_t tx_data_rate_ids[] = {
+    /* 802.11n/a/g/b data rate IDs */
+    DATARATE_1M, DATARATE_2M, DATARATE5_5M, DATARATE_11M, RESERVED_1, DATARATE_6M, DATARATE_9M, DATARATE_12M,
+    DATARATE_18M, DATARATE_24M, DATARATE_36M, DATARATE_48M, DATARATE_54M, RESERVED_2, HT_MCS0, HT_MCS1, HT_MCS2,
+    HT_MCS3, HT_MCS4, HT_MCS5, HT_MCS6, HT_MCS7,
+    /* 802.11ac VHT MCS rates id */
+    VHT_SS1_MCS0, VHT_SS1_MCS1, VHT_SS1_MCS2, VHT_SS1_MCS3, VHT_SS1_MCS4, VHT_SS1_MCS5, VHT_SS1_MCS6, VHT_SS1_MCS7,
+    VHT_SS1_MCS8,
+    /* 802.11ax HE MCS rates ID */
+    HE_SS1_MCS0, HE_SS1_MCS1, HE_SS1_MCS2, HE_SS1_MCS3, HE_SS1_MCS4, HE_SS1_MCS5, HE_SS1_MCS6, HE_SS1_MCS7, HE_SS1_MCS8,
+    HE_SS1_MCS9};
+#endif
+
+static uint8_t band_set       = 0;
+static uint8_t bandwidth_set  = 0;
+static uint8_t tx_antenna_set = 0;
+static uint8_t rx_antenna_set = 0;
+
+int wifi_get_set_rf_test_generic(t_u16 cmd_action, wifi_mfg_cmd_generic_cfg_t *wifi_mfg_cmd_generic_cfg)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    mlan_ds_misc_cfg misc;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MFG_COMMAND, cmd_action,
+                                              0, NULL, wifi_mfg_cmd_generic_cfg, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    wifi_wait_for_cmdresp(&misc);
+    memcpy(wifi_mfg_cmd_generic_cfg, (wifi_mfg_cmd_generic_cfg_t *)&misc.param.mfg_generic_cfg,
+           sizeof(wifi_mfg_cmd_generic_cfg_t));
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_set_rf_test_tx_frame(t_u16 cmd_action,
+                                  wifi_mfg_cmd_tx_frame_t *wifi_mfg_cmd_tx_frame,
+                                  wifi_mfg_cmd_generic_cfg_t *wifi_mfg_cmd_generic_cfg)
+{
+    wifi_get_command_lock();
+    mlan_ds_misc_cfg misc;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    cmd->seq_num   = 0x0;
+    cmd->result    = 0x0;
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MFG_COMMAND, cmd_action,
+                                              0, NULL, wifi_mfg_cmd_tx_frame, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    wifi_wait_for_cmdresp(&misc);
+    memcpy(wifi_mfg_cmd_generic_cfg, (wifi_mfg_cmd_generic_cfg_t *)&misc.param.mfg_generic_cfg,
+           sizeof(wifi_mfg_cmd_generic_cfg_t));
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_set_rf_trigger_frame_cfg(t_u16 cmd_action,
+                                      wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr_t *wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr,
+                                      wifi_mfg_cmd_generic_cfg_t *wifi_mfg_cmd_generic_cfg)
+{
+    wifi_get_command_lock();
+    mlan_ds_misc_cfg misc;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    cmd->seq_num   = 0x0;
+    cmd->result    = 0x0;
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MFG_COMMAND, cmd_action,
+                                              0, NULL, wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    wifi_wait_for_cmdresp(&misc);
+    memcpy(wifi_mfg_cmd_generic_cfg, (wifi_mfg_cmd_generic_cfg_t *)&misc.param.mfg_generic_cfg,
+           sizeof(wifi_mfg_cmd_generic_cfg_t));
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_set_rf_he_tb_tx(t_u16 cmd_action,
+                             wifi_mfg_cmd_he_tb_tx_t *wifi_mfg_cmd_he_tb_tx,
+                             wifi_mfg_cmd_generic_cfg_t *wifi_mfg_cmd_generic_cfg)
+{
+    wifi_get_command_lock();
+    mlan_ds_misc_cfg misc;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    cmd->seq_num   = 0x0;
+    cmd->result    = 0x0;
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MFG_COMMAND, cmd_action,
+                                              0, NULL, wifi_mfg_cmd_he_tb_tx, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    wifi_wait_for_cmdresp(&misc);
+    memcpy(wifi_mfg_cmd_generic_cfg, (wifi_mfg_cmd_generic_cfg_t *)&misc.param.mfg_generic_cfg,
+           sizeof(wifi_mfg_cmd_generic_cfg_t));
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_set_rf_otp_mac_addr(t_u16 cmd_action, wifi_mfg_cmd_otp_mac_addr_rd_wr_t *wifi_mfg_cmd_otp_mac_addr_rd_wr)
+{
+    wifi_get_command_lock();
+    mlan_ds_misc_cfg misc;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    cmd->seq_num   = 0x0;
+    cmd->result    = 0x0;
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MFG_COMMAND, cmd_action,
+                                              0, NULL, wifi_mfg_cmd_otp_mac_addr_rd_wr, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    wifi_wait_for_cmdresp(&misc);
+    memcpy(wifi_mfg_cmd_otp_mac_addr_rd_wr, (wifi_mfg_cmd_otp_mac_addr_rd_wr_t *)&misc.param.mfg_otp_mac_addr_rd_wr,
+           sizeof(wifi_mfg_cmd_otp_mac_addr_rd_wr_t));
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_set_rf_otp_cal_data(t_u16 cmd_action, wifi_mfg_cmd_otp_cal_data_rd_wr_t *wifi_mfg_cmd_otp_cal_data_rd_wr)
+{
+    wifi_get_command_lock();
+    mlan_ds_misc_cfg *misc  = NULL;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    misc = (mlan_ds_misc_cfg *)OSA_MemoryAllocate(sizeof(mlan_ds_misc_cfg));
+    (void)memset(misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    cmd->seq_num   = 0x0;
+    cmd->result    = 0x0;
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MFG_COMMAND, cmd_action,
+                                              0, NULL, wifi_mfg_cmd_otp_cal_data_rd_wr, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        (void)OSA_MemoryFree(misc);
+        return -WM_FAIL;
+    }
+
+    wifi_wait_for_cmdresp(misc);
+    memcpy(wifi_mfg_cmd_otp_cal_data_rd_wr, (wifi_mfg_cmd_otp_cal_data_rd_wr_t *)&(misc->param.mfg_otp_cal_data_rd_wr),
+           sizeof(wifi_mfg_cmd_otp_cal_data_rd_wr_t));
+    (void)OSA_MemoryFree(misc);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_set_rf_test_tx_cont(t_u16 cmd_action,
+                                 wifi_mfg_cmd_tx_cont_t *wifi_mfg_cmd_tx_cont,
+                                 wifi_mfg_cmd_generic_cfg_t *wifi_mfg_cmd_generic_cfg)
+{
+    wifi_get_command_lock();
+    mlan_ds_misc_cfg misc;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    cmd->seq_num   = 0x0;
+    cmd->result    = 0x0;
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MFG_COMMAND, cmd_action,
+                                              0, NULL, wifi_mfg_cmd_tx_cont, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    wifi_wait_for_cmdresp(&misc);
+    memcpy(wifi_mfg_cmd_generic_cfg, (wifi_mfg_cmd_generic_cfg_t *)&misc.param.mfg_generic_cfg,
+           sizeof(wifi_mfg_cmd_generic_cfg_t));
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_set_rf_test_mode(void)
+{
+    int ret;
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_SET_TEST_MODE;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi set rf test mode fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_unset_rf_test_mode(void)
+{
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_UNSET_TEST_MODE;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+
+    (void)wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_rf_channel(const uint8_t channel)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    /* To align with mxdriver, skip channel valid check for rf test mode */
+#if 0
+    /* Check if Channel is allowed as per WWSM */
+    if (!wlan_is_channel_valid(channel))
+        return -WM_FAIL;
+#endif
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RF_CHAN;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_generic_cfg.data1 = channel;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi set rf channel fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_set_rf_radio_mode(const uint8_t mode)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    /* Check if radio mode is valid */
+    if (!wlan_is_radio_mode_valid(mode))
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RADIO_MODE_CFG;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+    wifi_mfg_cmd_generic_cfg.data1   = mode;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi set radio mode fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_channel(uint8_t *channel)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RF_CHAN;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_generic_cfg);
+
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        *channel = wifi_mfg_cmd_generic_cfg.data1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi get rf channel fail, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_radio_mode(uint8_t *mode)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RADIO_MODE_CFG;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_generic_cfg);
+
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        *mode = wifi_mfg_cmd_generic_cfg.data1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi get rf radio fail, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_set_rf_band(const uint8_t band)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if (band != 0U
+#if CONFIG_5GHz_SUPPORT
+        && band != 1U
+#endif
+    )
+        return -WM_FAIL;
+
+#if CONFIG_5GHz_SUPPORT
+    if ((band == 1) && ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        wifi_e("Not support 5G, please set 2G band");
+        return -WM_FAIL;
+    }
+#endif
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RF_BAND_AG;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_generic_cfg.data1 = band;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        band_set = 1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi set rf band fails, error code: 0x%x", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_band(uint8_t *band)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if (!band_set)
+    {
+        wifi_e("RF Band not set");
+        return -WM_FAIL;
+    }
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RF_BAND_AG;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        *band = wifi_mfg_cmd_generic_cfg.data1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi get rf band fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_set_rf_bandwidth(const uint8_t bandwidth)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if ((bandwidth != 0U)
+#if CONFIG_5GHz_SUPPORT
+        && (bandwidth != 1U)
+#endif
+#if CONFIG_11AC
+        && (bandwidth != 4U)
+#endif
+    )
+    {
+        return -WM_FAIL;
+    }
+
+    if ((bandwidth != 0) && ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        wifi_e("Not support 5G, please set 2G bandwidth");
+        return -WM_FAIL;
+    }
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RF_CHANNELBW;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_generic_cfg.data1 = bandwidth;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        bandwidth_set = 1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi set rf bandwidth fails, error code: 0x%x", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_bandwidth(uint8_t *bandwidth)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if (!bandwidth_set)
+    {
+        wifi_e("Bandwidth not set");
+        return -WM_FAIL;
+    }
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RF_CHANNELBW;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        *bandwidth = wifi_mfg_cmd_generic_cfg.data1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi get rf bandwidth fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_per(uint32_t *rx_tot_pkt_count, uint32_t *rx_mcast_bcast_count, uint32_t *rx_pkt_fcs_error)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_CLR_RX_ERR;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        *rx_tot_pkt_count     = wifi_mfg_cmd_generic_cfg.data1;
+        *rx_mcast_bcast_count = wifi_mfg_cmd_generic_cfg.data2;
+        *rx_pkt_fcs_error     = wifi_mfg_cmd_generic_cfg.data3;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi get rf per fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_set_rf_tx_cont_mode(const uint32_t enable_tx,
+                             const uint32_t cw_mode,
+                             const uint32_t payload_pattern,
+                             const uint32_t cs_mode,
+                             const uint32_t act_sub_ch,
+                             const uint32_t tx_rate)
+{
+    wifi_mfg_cmd_tx_cont_t wifi_mfg_cmd_tx_cont;
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+    int ret;
+
+    if ((enable_tx > 1U) || (cw_mode > 1U) || (cs_mode > 1U) || (act_sub_ch == 2U || act_sub_ch > 3U))
+        return -WM_FAIL;
+
+    (void)memset(&wifi_mfg_cmd_tx_cont, 0x00, sizeof(wifi_mfg_cmd_tx_cont_t));
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_tx_cont.mfg_cmd = MFG_CMD_TX_CONT;
+    wifi_mfg_cmd_tx_cont.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_tx_cont.enable_tx       = enable_tx;
+    wifi_mfg_cmd_tx_cont.cw_mode         = cw_mode;
+    wifi_mfg_cmd_tx_cont.payload_pattern = payload_pattern;
+    wifi_mfg_cmd_tx_cont.cs_mode         = cs_mode;
+    wifi_mfg_cmd_tx_cont.act_sub_ch      = act_sub_ch;
+    wifi_mfg_cmd_tx_cont.tx_rate         = tx_rate;
+
+    ret = wifi_get_set_rf_test_tx_cont(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_tx_cont, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi set rf tx cont mode fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_set_rf_tx_antenna(const uint8_t antenna)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if (antenna != 1U && antenna != 2U)
+        return -WM_FAIL;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_TX_ANT;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_generic_cfg.data1 = antenna;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        tx_antenna_set = 1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi set rf tx antenna fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_tx_antenna(uint8_t *antenna)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if (!tx_antenna_set)
+    {
+        wifi_e("Tx Antenna not set");
+        return -WM_FAIL;
+    }
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_TX_ANT;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        *antenna = wifi_mfg_cmd_generic_cfg.data1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi get rf tx antenna fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+    ;
+}
+
+int wifi_set_rf_rx_antenna(const uint8_t antenna)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if (antenna != 1U && antenna != 2U)
+        return -WM_FAIL;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RX_ANT;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_generic_cfg.data1 = antenna;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        rx_antenna_set = 1;
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi get rf tx antenna fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_rx_antenna(uint8_t *antenna)
+{
+    int ret;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+
+    if (!rx_antenna_set)
+    {
+        wifi_e("Rx antenna not set");
+        return -WM_FAIL;
+    }
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RX_ANT;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_generic_cfg);
+
+    if (ret == WM_SUCCESS)
+        *antenna = wifi_mfg_cmd_generic_cfg.data1;
+
+    return ret;
+}
+
+int wifi_set_rf_tx_power(const uint32_t power, const uint8_t mod, const uint8_t path_id)
+{
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+    int ret;
+
+    if (mod != 0U && mod != 1U && mod != 2U)
+        return -WM_FAIL;
+
+    if (path_id != 0U && path_id != 1U && path_id != 2U)
+        return -WM_FAIL;
+
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+
+    wifi_mfg_cmd_generic_cfg.mfg_cmd = MFG_CMD_RFPWR;
+    wifi_mfg_cmd_generic_cfg.action  = HostCmd_ACT_GEN_SET;
+#ifdef SD9177
+    /* Firecrest firmware expects value * 16 */
+    wifi_mfg_cmd_generic_cfg.data1 = power * 16;
+#else
+    wifi_mfg_cmd_generic_cfg.data1 = power;
+#endif
+    wifi_mfg_cmd_generic_cfg.data2 = mod;
+    wifi_mfg_cmd_generic_cfg.data3 = path_id;
+
+    ret = wifi_get_set_rf_test_generic(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_generic_cfg);
+    if (ret == WM_SUCCESS)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("Wifi set rf tx power fails, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+#ifdef RW610
+static int wifi_check_data_rate_id(const uint32_t data_rate)
+{
+    uint8_t i;
+    for (i = 0; i < sizeof(tx_data_rate_ids) / sizeof(tx_data_rate_ids[0]); i++)
+    {
+        if (data_rate == tx_data_rate_ids[i])
+        {
+            return WM_SUCCESS;
+        }
+    }
+    return -WM_FAIL;
+}
+#endif
+
+int wifi_set_rf_tx_frame(const uint32_t enable,
+                         const uint32_t data_rate,
+                         const uint32_t frame_pattern,
+                         const uint32_t frame_length,
+                         const uint16_t adjust_burst_sifs,
+                         const uint32_t burst_sifs_in_us,
+                         const uint32_t short_preamble,
+                         const uint32_t act_sub_ch,
+                         const uint32_t short_gi,
+                         const uint32_t adv_coding,
+                         const uint32_t tx_bf,
+                         const uint32_t gf_mode,
+                         const uint32_t stbc,
+                         const uint8_t *bssid)
+{
+    wifi_mfg_cmd_tx_frame_t wifi_mfg_cmd_tx_frame;
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+    int ret;
+
+    if (enable > 1U || frame_length < 1U || frame_length > 0x400U || burst_sifs_in_us > 255U || short_preamble > 1U ||
+        act_sub_ch == 2U || act_sub_ch > 3U || short_gi > 1U || adv_coding > 1U || tx_bf > 1U || gf_mode > 1U ||
+        stbc > 1U)
+        return -WM_FAIL;
+
+    (void)memset(&wifi_mfg_cmd_tx_frame, 0x00, sizeof(wifi_mfg_cmd_tx_frame_t));
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+#ifdef RW610
+    ret = wifi_check_data_rate_id(data_rate);
+    if ((enable == 1U) && (ret != WM_SUCCESS))
+    {
+        wifi_e("The configured data rate ID is illegal. data_rate_id: 0x%x\r\n", data_rate);
+        return ret;
+    }
+#endif
+
+    wifi_mfg_cmd_tx_frame.mfg_cmd = MFG_CMD_TX_FRAME;
+    wifi_mfg_cmd_tx_frame.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_tx_frame.enable    = enable;
+    wifi_mfg_cmd_tx_frame.data_rate = data_rate;
+#ifdef RW610
+    /* on fw side, data rate id of 802.11n/a/g/b start from 0, the data rate id need reduce 1 */
+    if (data_rate <= HT_MCS7)
+    {
+        wifi_mfg_cmd_tx_frame.data_rate--;
+    }
+#endif
+
+    wifi_mfg_cmd_tx_frame.frame_pattern = frame_pattern;
+    wifi_mfg_cmd_tx_frame.frame_length  = frame_length;
+    (void)memcpy((void *)wifi_mfg_cmd_tx_frame.bssid, (const void *)bssid, MLAN_MAC_ADDR_LENGTH);
+    wifi_mfg_cmd_tx_frame.adjust_burst_sifs = adjust_burst_sifs;
+    wifi_mfg_cmd_tx_frame.burst_sifs_in_us  = burst_sifs_in_us;
+    wifi_mfg_cmd_tx_frame.short_preamble    = short_preamble;
+    wifi_mfg_cmd_tx_frame.act_sub_ch        = act_sub_ch;
+    wifi_mfg_cmd_tx_frame.short_gi          = short_gi;
+    wifi_mfg_cmd_tx_frame.adv_coding        = adv_coding;
+    wifi_mfg_cmd_tx_frame.tx_bf             = tx_bf;
+    wifi_mfg_cmd_tx_frame.gf_mode           = gf_mode;
+    wifi_mfg_cmd_tx_frame.stbc              = stbc;
+    wifi_mfg_cmd_tx_frame.signal_bw         = -1;
+    wifi_mfg_cmd_tx_frame.NumPkt            = -1;
+    wifi_mfg_cmd_tx_frame.MaxPE             = -1;
+    wifi_mfg_cmd_tx_frame.BeamChange        = -1;
+    wifi_mfg_cmd_tx_frame.Dcm               = -1;
+    wifi_mfg_cmd_tx_frame.Doppler           = -1;
+    wifi_mfg_cmd_tx_frame.MidP              = -1;
+    wifi_mfg_cmd_tx_frame.QNum              = -1;
+
+    ret = wifi_get_set_rf_test_tx_frame(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_tx_frame, &wifi_mfg_cmd_generic_cfg);
+    if (WM_SUCCESS == ret && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi set rf tx frame fail, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_rf_trigger_frame_cfg(uint32_t Enable_tx,
+                              uint32_t Standalone_hetb,
+                              uint8_t FRAME_CTRL_TYPE,
+                              uint8_t FRAME_CTRL_SUBTYPE,
+                              uint16_t FRAME_DURATION,
+                              uint64_t TriggerType,
+                              uint64_t UlLen,
+                              uint64_t MoreTF,
+                              uint64_t CSRequired,
+                              uint64_t UlBw,
+                              uint64_t LTFType,
+                              uint64_t LTFMode,
+                              uint64_t LTFSymbol,
+                              uint64_t UlSTBC,
+                              uint64_t LdpcESS,
+                              uint64_t ApTxPwr,
+                              uint64_t PreFecPadFct,
+                              uint64_t PeDisambig,
+                              uint64_t SpatialReuse,
+                              uint64_t Doppler,
+                              uint64_t HeSig2,
+                              uint32_t AID12,
+                              uint32_t RUAllocReg,
+                              uint32_t RUAlloc,
+                              uint32_t UlCodingType,
+                              uint32_t UlMCS,
+                              uint32_t UlDCM,
+                              uint32_t SSAlloc,
+                              uint8_t UlTargetRSSI,
+                              uint8_t MPDU_MU_SF,
+                              uint8_t TID_AL,
+                              uint8_t AC_PL,
+                              uint8_t Pref_AC)
+{
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr_t wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr;
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+    int ret;
+
+    (void)memset(&wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr, 0x00, sizeof(wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr_t));
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.mfg_cmd = MFG_CMD_CONFIG_TRIGGER_FRAME;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.enable_tx       = Enable_tx;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.standalone_hetb = Standalone_hetb;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.frmCtl.type     = FRAME_CTRL_TYPE;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.frmCtl.sub_type = FRAME_CTRL_SUBTYPE;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.duration        = FRAME_DURATION;
+
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.trigger_type    = TriggerType;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ul_len          = UlLen;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.more_tf         = MoreTF;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.cs_required     = CSRequired;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ul_bw           = UlBw;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ltf_type        = LTFType;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ltf_mode        = LTFMode;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ltf_symbol      = LTFSymbol;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ul_stbc         = UlSTBC;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ldpc_ess        = LdpcESS;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.ap_tx_pwr       = ApTxPwr;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.pre_fec_pad_fct = PreFecPadFct;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.pe_disambig     = PeDisambig;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.spatial_reuse   = SpatialReuse;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.doppler         = Doppler;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_common_field.he_sig2         = HeSig2;
+
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.aid12          = AID12;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.ru_alloc_reg   = RUAllocReg;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.ru_alloc       = RUAlloc;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.ul_coding_type = UlCodingType;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.ul_mcs         = UlMCS;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.ul_dcm         = UlDCM;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.ss_alloc       = SSAlloc;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.trig_user_info_field.ul_target_rssi = UlTargetRSSI;
+
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.basic_trig_user_info.mpdu_mu_sf = MPDU_MU_SF;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.basic_trig_user_info.tid_al     = TID_AL;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.basic_trig_user_info.ac_pl      = AC_PL;
+    wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr.basic_trig_user_info.pref_ac    = Pref_AC;
+
+    ret = wifi_get_set_rf_trigger_frame_cfg(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_IEEEtypes_CtlBasicTrigHdr,
+                                            &wifi_mfg_cmd_generic_cfg);
+    if (WM_SUCCESS == ret && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi set rf tx frame fail, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_cfg_rf_he_tb_tx(uint16_t enable, uint16_t qnum, uint16_t aid, uint16_t axq_mu_timer, int16_t tx_power)
+{
+    wifi_mfg_cmd_he_tb_tx_t wifi_mfg_cmd_he_tb_tx;
+
+    wifi_mfg_cmd_generic_cfg_t wifi_mfg_cmd_generic_cfg;
+    int ret;
+
+    (void)memset(&wifi_mfg_cmd_he_tb_tx, 0x00, sizeof(wifi_mfg_cmd_he_tb_tx_t));
+    (void)memset(&wifi_mfg_cmd_generic_cfg, 0x00, sizeof(wifi_mfg_cmd_generic_cfg_t));
+    wifi_mfg_cmd_he_tb_tx.mfg_cmd = MFG_CMD_CONFIG_MAC_HE_TB_TX;
+    wifi_mfg_cmd_he_tb_tx.action  = HostCmd_ACT_GEN_SET;
+
+    wifi_mfg_cmd_he_tb_tx.enable       = enable;
+    wifi_mfg_cmd_he_tb_tx.qnum         = qnum;
+    wifi_mfg_cmd_he_tb_tx.aid          = aid;
+    wifi_mfg_cmd_he_tb_tx.axq_mu_timer = axq_mu_timer;
+    wifi_mfg_cmd_he_tb_tx.tx_power     = tx_power;
+
+    ret = wifi_get_set_rf_he_tb_tx(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_he_tb_tx, &wifi_mfg_cmd_generic_cfg);
+    if (WM_SUCCESS == ret && wifi_mfg_cmd_generic_cfg.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi set rf tx frame fail, error code: 0x%x\r\n", wifi_mfg_cmd_generic_cfg.error);
+    return -WM_FAIL;
+}
+
+int wifi_set_rf_otp_mac_addr(uint8_t *mac)
+{
+    int ret;
+
+    wifi_mfg_cmd_otp_mac_addr_rd_wr_t wifi_mfg_cmd_otp_mac_addr_rd_wr;
+
+    (void)memset(&wifi_mfg_cmd_otp_mac_addr_rd_wr, 0x00, sizeof(wifi_mfg_cmd_otp_mac_addr_rd_wr_t));
+
+    wifi_mfg_cmd_otp_mac_addr_rd_wr.mfg_cmd = MFG_CMD_OTP_MAC_ADD;
+    wifi_mfg_cmd_otp_mac_addr_rd_wr.action  = HostCmd_ACT_GEN_SET;
+    (void)memcpy((void *)wifi_mfg_cmd_otp_mac_addr_rd_wr.mac_addr, (const void *)mac, MLAN_MAC_ADDR_LENGTH);
+
+    ret = wifi_get_set_rf_otp_mac_addr(HostCmd_ACT_GEN_SET, &wifi_mfg_cmd_otp_mac_addr_rd_wr);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_otp_mac_addr_rd_wr.error == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi set otp mac address fails, error code: 0x%x\r\n", wifi_mfg_cmd_otp_mac_addr_rd_wr.error);
+    return -WM_FAIL;
+}
+
+int wifi_get_rf_otp_mac_addr(uint8_t *mac)
+{
+    int ret;
+
+    wifi_mfg_cmd_otp_mac_addr_rd_wr_t wifi_mfg_cmd_otp_mac_addr_rd_wr;
+
+    (void)memset(&wifi_mfg_cmd_otp_mac_addr_rd_wr, 0x00, sizeof(wifi_mfg_cmd_otp_mac_addr_rd_wr_t));
+
+    wifi_mfg_cmd_otp_mac_addr_rd_wr.mfg_cmd = MFG_CMD_OTP_MAC_ADD;
+    wifi_mfg_cmd_otp_mac_addr_rd_wr.action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_otp_mac_addr(HostCmd_ACT_GEN_GET, &wifi_mfg_cmd_otp_mac_addr_rd_wr);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_otp_mac_addr_rd_wr.error == 0)
+    {
+        (void)memcpy((void *)mac, (const void *)wifi_mfg_cmd_otp_mac_addr_rd_wr.mac_addr, MLAN_MAC_ADDR_LENGTH);
+        return WM_SUCCESS;
+    }
+
+    wifi_e("wifi get otp mac address fails, error code: 0x%x\r\n", wifi_mfg_cmd_otp_mac_addr_rd_wr.error);
+    return -WM_FAIL;
+}
+
+int wifi_set_rf_otp_cal_data(const uint8_t *cal_data, uint32_t cal_data_len)
+{
+    int ret;
+
+    wifi_mfg_cmd_otp_cal_data_rd_wr_t *wifi_mfg_cmd_otp_cal_data_rd_wr = NULL;
+
+    wifi_mfg_cmd_otp_cal_data_rd_wr =
+        (wifi_mfg_cmd_otp_cal_data_rd_wr_t *)OSA_MemoryAllocate(sizeof(wifi_mfg_cmd_otp_cal_data_rd_wr_t));
+    (void)memset(wifi_mfg_cmd_otp_cal_data_rd_wr, 0x00, sizeof(wifi_mfg_cmd_otp_cal_data_rd_wr_t));
+
+    wifi_mfg_cmd_otp_cal_data_rd_wr->mfg_cmd      = MFG_CMD_OTP_CAL_DATA;
+    wifi_mfg_cmd_otp_cal_data_rd_wr->action       = HostCmd_ACT_GEN_SET;
+    wifi_mfg_cmd_otp_cal_data_rd_wr->cal_data_len = cal_data_len;
+    (void)memcpy((void *)wifi_mfg_cmd_otp_cal_data_rd_wr->cal_data, (const void *)cal_data, cal_data_len);
+
+    ret = wifi_get_set_rf_otp_cal_data(HostCmd_ACT_GEN_SET, wifi_mfg_cmd_otp_cal_data_rd_wr);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_otp_cal_data_rd_wr->error == 0)
+    {
+        ret = WM_SUCCESS;
+    }
+    else
+    {
+        wifi_e("wifi set cal data fails, error code: 0x%x\r\n", wifi_mfg_cmd_otp_cal_data_rd_wr->error);
+        ret = -WM_FAIL;
+    }
+
+    (void)OSA_MemoryFree(wifi_mfg_cmd_otp_cal_data_rd_wr);
+    return ret;
+}
+
+int wifi_get_rf_otp_cal_data(uint8_t *cal_data)
+{
+    int ret;
+    uint32_t cal_data_status = 0;
+
+    wifi_mfg_cmd_otp_cal_data_rd_wr_t *wifi_mfg_cmd_otp_cal_data_rd_wr = NULL;
+
+    wifi_mfg_cmd_otp_cal_data_rd_wr =
+        (wifi_mfg_cmd_otp_cal_data_rd_wr_t *)OSA_MemoryAllocate(sizeof(wifi_mfg_cmd_otp_cal_data_rd_wr_t));
+    (void)memset(wifi_mfg_cmd_otp_cal_data_rd_wr, 0x00, sizeof(wifi_mfg_cmd_otp_cal_data_rd_wr_t));
+
+    wifi_mfg_cmd_otp_cal_data_rd_wr->mfg_cmd = MFG_CMD_OTP_CAL_DATA;
+    wifi_mfg_cmd_otp_cal_data_rd_wr->action  = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_get_set_rf_otp_cal_data(HostCmd_ACT_GEN_GET, wifi_mfg_cmd_otp_cal_data_rd_wr);
+    if (ret == WM_SUCCESS && wifi_mfg_cmd_otp_cal_data_rd_wr->error == 0)
+    {
+        cal_data_status = wifi_mfg_cmd_otp_cal_data_rd_wr->cal_data_status;
+        if (cal_data_status == 1)
+        {
+            (void)memcpy((void *)cal_data, (const void *)wifi_mfg_cmd_otp_cal_data_rd_wr->cal_data,
+                         wifi_mfg_cmd_otp_cal_data_rd_wr->cal_data_len);
+            ret = WM_SUCCESS;
+        }
+        else
+        {
+            ret = -WM_FAIL;
+        }
+    }
+    else
+    {
+        wifi_e("wifi get otp cal data fails, error code: 0x%x\r\n", wifi_mfg_cmd_otp_cal_data_rd_wr->error);
+        ret = -WM_FAIL;
+    }
+
+    (void)OSA_MemoryFree(wifi_mfg_cmd_otp_cal_data_rd_wr);
+
+    return ret;
+}
+#endif
+
+/*
+ * fixme: Currently, we support only single SSID based scan. We can extend
+ * this to a list of multiple SSIDs. The mlan API supports this.
+ */
+int wifi_send_scan_cmd(t_u8 bss_mode,
+                       const t_u8 *specific_bssid,
+                       const char *ssid,
+                       uint8_t ssid_num,
+                       const t_u8 num_channels,
+                       const wifi_scan_channel_list_t *chan_list,
+                       const t_u8 num_probes,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                       const t_s16 rssi_threshold,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                       const t_u16 scan_chan_gap,
+#endif
+                       const bool keep_previous_scan,
+                       const bool active_scan_triggered)
+{
+    int ssid_len         = 0;
+    char const *tmp_ssid = ssid;
+    t_u8 i;
+#if CONFIG_COMBO_SCAN
+    const char wildcard_ssid[] = "*";
+#endif
+    mlan_adap->active_scan_triggered = MFALSE;
+
+#if CONFIG_WPA_SUPP
+    if (mlan_adap->wpa_supp_scan_triggered == MTRUE)
+    {
+        return -WM_E_BUSY;
+    }
+
+    mlan_adap->wpa_supp_scan_triggered = wm_wifi.wpa_supp_scan;
+    wm_wifi.wpa_supp_scan              = MFALSE;
+#endif
+    if (ssid_num > MRVDRV_MAX_SSID_LIST_LENGTH)
+        return -WM_E_INVAL;
+    tmp_ssid = ssid;
+    for (i = 0; i < ssid_num; i++)
+    {
+        ssid_len = strlen(tmp_ssid);
+        tmp_ssid += ssid_len;
+        tmp_ssid++;
+        if (ssid_len > MLAN_MAX_SSID_LENGTH)
+        {
+#if CONFIG_WPA_SUPP
+            mlan_adap->wpa_supp_scan_triggered = MFALSE;
+#endif
+            return -WM_E_INVAL;
+        }
+    }
+
+#if !CONFIG_MEM_POOLS
+    wlan_user_scan_cfg *user_scan_cfg = (wlan_user_scan_cfg *)OSA_MemoryAllocate(sizeof(wlan_user_scan_cfg));
+#else
+    wlan_user_scan_cfg *user_scan_cfg = (wlan_user_scan_cfg *)OSA_MemoryPoolAllocate(buf_768_MemoryPool);
+#endif
+    if (user_scan_cfg == MNULL)
+    {
+#if CONFIG_WPA_SUPP
+        mlan_adap->wpa_supp_scan_triggered = MFALSE;
+#endif
+        return -WM_E_NOMEM;
+    }
+
+    (void)memset(user_scan_cfg, 0x00, sizeof(wlan_user_scan_cfg));
+
+    user_scan_cfg->bss_mode           = bss_mode;
+    user_scan_cfg->keep_previous_scan = keep_previous_scan;
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    user_scan_cfg->rssi_threshold = rssi_threshold;
+#endif
+
+    if (num_probes > 0U && num_probes <= MAX_PROBES)
+    {
+        user_scan_cfg->num_probes = num_probes;
+    }
+
+    if (specific_bssid != NULL)
+    {
+        (void)memcpy((void *)user_scan_cfg->specific_bssid, (const void *)specific_bssid, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    tmp_ssid = ssid;
+    for (i = 0; i < ssid_num; i++)
+    {
+        ssid_len = strlen(tmp_ssid);
+        (void)memcpy((void *)user_scan_cfg->ssid_list[i].ssid, (const void *)tmp_ssid, ssid_len);
+        tmp_ssid += ssid_len;
+        tmp_ssid++;
+    }
+
+#if CONFIG_COMBO_SCAN
+    for (i = 0; (i < MRVDRV_MAX_SSID_LIST_LENGTH) && (*user_scan_cfg->ssid_list[i].ssid); i++)
+    {
+        if (!strncmp(wildcard_ssid, (char *)(user_scan_cfg->ssid_list[i].ssid), strlen(wildcard_ssid)))
+        {
+            (void)memset(user_scan_cfg->ssid_list[i].ssid, 0x00, sizeof(user_scan_cfg->ssid_list[i].ssid));
+            user_scan_cfg->ssid_list[i].max_len = 40;
+        }
+    }
+#endif
+
+    if ((chan_list != MNULL) && (chan_list[0].radio_type & BAND_SPECIFIED))
+    {
+        user_scan_cfg->chan_list[0].radio_type = chan_list[0].radio_type;
+    }
+    else if (num_channels > 0U && num_channels <= WLAN_USER_SCAN_CHAN_MAX && chan_list != MNULL)
+    {
+        for (i = 0; i < num_channels; i++)
+        {
+            /** Channel Number to scan */
+            user_scan_cfg->chan_list[i].chan_number = chan_list[i].chan_number;
+            /** Radio type: 'B/G' Band = 0, 'A' Band = 1 */
+            /* fixme: B/G is hardcoded here. Ask the caller first to
+               send the radio type and then change here */
+            if (chan_list[i].chan_number > 14U)
+            {
+                user_scan_cfg->chan_list[i].radio_type = 1;
+            }
+            /** Scan type: Active = 1, Passive = 2 */
+            /* fixme: Active is hardcoded here. Ask the caller first to
+               send the  type and then change here */
+            user_scan_cfg->chan_list[i].scan_type = chan_list[i].scan_type;
+            /** Scan duration in milliseconds; if 0 default used */
+            user_scan_cfg->chan_list[i].scan_time = chan_list[i].scan_time;
+        }
+    }
+
+    if (active_scan_triggered)
+    {
+        mlan_adap->active_scan_triggered = MTRUE;
+    }
+#if CONFIG_SCAN_CHANNEL_GAP
+    user_scan_cfg->scan_chan_gap = scan_chan_gap;
+#endif
+    if (wm_wifi.g_user_scan_cfg != NULL)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)user_scan_cfg);
+#else
+        OSA_MemoryPoolFree(buf_768_MemoryPool, user_scan_cfg);
+#endif
+
+#if CONFIG_WPA_SUPP
+        mlan_adap->wpa_supp_scan_triggered = MFALSE;
+        return -WM_E_BUSY;
+#else
+        return -WM_E_BUSY;
+#endif
+    }
+
+    wm_wifi.g_user_scan_cfg = user_scan_cfg;
+
+#if CONFIG_ZEPHYR
+    (void)OSA_EventNotifyPost(wm_wifi.wifi_scan_task_Handle);
+#else
+    (void)OSA_EventSet((osa_event_handle_t)wm_wifi.wifi_event_Handle, WIFI_EVENT_SCAN);
+#endif
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPA_SUPP
+int wifi_send_sched_scan_cmd(nxp_wifi_trigger_sched_scan_t *params)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    int ret, i;
+
+    memset(&pmpriv->scan_cfg, 0, sizeof(pmpriv->scan_cfg));
+
+    if (params->num_ssids != 0U)
+    {
+        for (i = 0; i < params->num_ssids; i++)
+        {
+            memcpy((void *)pmpriv->scan_cfg.ssid_list[i].ssid, (const void *)params->scan_ssids[i].ssid,
+                   (size_t)params->scan_ssids[i].ssid_len);
+            pmpriv->scan_cfg.ssid_list[i].max_len = 0;
+        }
+    }
+    else
+    {
+        pmpriv->scan_cfg.ssid_list[0].max_len = 0xff;
+    }
+
+    for (i = 0; params->num_chans; i++)
+    {
+        pmpriv->scan_cfg.chan_list[i].chan_number = params->chan_list[i];
+
+        pmpriv->scan_cfg.chan_list[i].scan_type = MLAN_SCAN_TYPE_ACTIVE;
+
+        if (pmpriv->scan_cfg.chan_list[i].chan_number > 14)
+        {
+            pmpriv->scan_cfg.chan_list[i].radio_type = HostCmd_SCAN_RADIO_TYPE_A;
+        }
+        else
+        {
+            pmpriv->scan_cfg.chan_list[i].radio_type = HostCmd_SCAN_RADIO_TYPE_BG;
+        }
+    }
+
+    if (pmpriv->probe_req_index != -1)
+    {
+        ret = wifi_clear_mgmt_ie2(MLAN_BSS_TYPE_STA, pmpriv->probe_req_index);
+
+        if (ret != WM_SUCCESS)
+        {
+            wifi_e("Clear probe req IE failed");
+            return -WM_FAIL;
+        }
+        pmpriv->probe_req_index = -1;
+    }
+
+    if (params->extra_ies.ie_len)
+    {
+        pmpriv->probe_req_index = wifi_set_mgmt_ie2(MLAN_BSS_TYPE_STA, MGMT_MASK_PROBE_REQ,
+                                                    (void *)params->extra_ies.ie, params->extra_ies.ie_len);
+
+        if (pmpriv->probe_req_index == -1)
+        {
+            wifi_e("Set probe req IE failed");
+            return -WM_FAIL;
+        }
+    }
+
+    pmpriv->scan_cfg.report_condition = params->report_condition;
+    pmpriv->scan_cfg.rssi_threshold   = params->filter_rssi;
+    pmpriv->scan_cfg.repeat_count     = params->repeat_count;
+    pmpriv->scan_cfg.scan_interval    = params->scan_interval;
+    pmpriv->scan_cfg.chan_per_scan    = params->chan_per_scan;
+    pmpriv->scan_cfg.num_probes       = 2;
+
+    pmpriv->scan_cfg.bss_type = MLAN_BSS_MODE_INFRA;
+    pmpriv->scan_cfg.action   = BG_SCAN_ACT_SET;
+    pmpriv->scan_cfg.enable   = MTRUE;
+
+    ret = wifi_request_bgscan(pmpriv);
+    if (ret)
+    {
+        wifi_d("Failed to request bgscan");
+        return -WM_FAIL;
+    }
+
+    pmpriv->sched_scanning   = MTRUE;
+    pmpriv->bg_scan_start    = MTRUE;
+    pmpriv->bg_scan_reported = MFALSE;
+
+    return ret;
+}
+
+int wifi_send_stop_sched_scan_cmd(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    pmpriv->sched_scanning   = MFALSE;
+    pmpriv->bg_scan_start    = MFALSE;
+    pmpriv->bg_scan_reported = MFALSE;
+
+    memset(&pmpriv->scan_cfg, 0, sizeof(pmpriv->scan_cfg));
+
+    pmpriv->scan_cfg.action = BG_SCAN_ACT_SET;
+    pmpriv->scan_cfg.enable = MFALSE;
+    int ret                 = wifi_request_bgscan(pmpriv);
+    if (ret)
+    {
+        wifi_d("Failed to request bgscan");
+    }
+
+    return ret;
+}
+#endif
+
+static int wifi_send_key_material_cmd(int bss_index, mlan_ds_sec_cfg *sec)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ioctl_req req;
+    mlan_status rv = MLAN_STATUS_SUCCESS;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)sec;
+    req.buf_len   = sizeof(mlan_ds_sec_cfg);
+    req.bss_index = bss_index;
+    req.req_id    = MLAN_IOCTL_SEC_CFG;
+    req.action    = MLAN_ACT_SET;
+
+    if (bss_index != 0)
+    {
+        rv = wlan_ops_uap_ioctl(mlan_adap, &req);
+    }
+    else
+    {
+        rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    }
+
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_key(int bss_index,
+                 bool is_pairwise,
+                 const uint8_t key_index,
+                 const uint8_t *key,
+                 unsigned key_len,
+                 const uint8_t *seq,
+                 unsigned seq_len,
+                 const uint8_t *mac_addr,
+                 unsigned int flags)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ds_sec_cfg sec;
+    int ret           = WM_SUCCESS;
+    t_u8 bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#if CONFIG_GTK_REKEY_OFFLOAD
+    mlan_private *pmpriv        = (mlan_private *)mlan_adap->priv[bss_index];
+    t_u8 zero_kek[MLAN_KEK_LEN] = {0};
+#endif
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_ENCRYPT_KEY;
+
+    if (key_len > MAX_WEP_KEY_SIZE)
+    {
+        if (seq && seq_len)
+        {
+            memcpy(sec.param.encrypt_key.pn, seq, seq_len);
+            sec.param.encrypt_key.key_flags |= KEY_FLAG_RX_SEQ_VALID;
+        }
+
+        if (mac_addr)
+        {
+            if (is_pairwise)
+            {
+                sec.param.encrypt_key.key_flags |= KEY_FLAG_SET_TX_KEY;
+            }
+            else
+            {
+                sec.param.encrypt_key.key_flags |= KEY_FLAG_GROUP_KEY;
+            }
+            (void)memcpy((void *)sec.param.encrypt_key.mac_addr, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+        }
+        else
+        {
+            memcpy(sec.param.encrypt_key.mac_addr, bcast_addr, MLAN_MAC_ADDR_LENGTH);
+            sec.param.encrypt_key.key_flags |= KEY_FLAG_GROUP_KEY;
+        }
+        sec.param.encrypt_key.key_index = key_index;
+
+        if (flags)
+        {
+            sec.param.encrypt_key.key_flags |= flags;
+        }
+    }
+    else
+    {
+        sec.param.encrypt_key.key_index          = MLAN_KEY_INDEX_DEFAULT;
+        sec.param.encrypt_key.is_current_wep_key = MTRUE;
+    }
+
+    sec.param.encrypt_key.key_len = key_len;
+    (void)memcpy((void *)sec.param.encrypt_key.key_material, (const void *)key, key_len);
+
+    ret = wifi_send_key_material_cmd(bss_index, &sec);
+
+#if CONFIG_GTK_REKEY_OFFLOAD
+
+    if ((ret == WM_SUCCESS) && (is_pairwise == false))
+    {
+        if (memcmp(pmpriv->gtk_rekey.kek, zero_kek, sizeof(zero_kek)) != 0)
+        {
+            mlan_status status = MLAN_STATUS_SUCCESS;
+            ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_CONFIG_GTK_REKEY_OFFLOAD_CFG, HostCmd_ACT_GEN_SET, 0, MNULL,
+                                   &pmpriv->gtk_rekey);
+            if (status)
+            {
+                PRINTM(MINFO, "Error sending message to FW\n");
+                ret = -WM_FAIL;
+            }
+            (void)__memset(pmpriv->adapter, &pmpriv->gtk_rekey, 0, sizeof(mlan_ds_misc_gtk_rekey_data));
+        }
+    }
+#endif
+
+    return ret;
+}
+
+int wifi_set_rekey_info(
+    int bss_index, const t_u8 *kek, size_t kek_len, const t_u8 *kck, size_t kck_len, const t_u8 *replay_ctr)
+{
+#if CONFIG_GTK_REKEY_OFFLOAD
+    mlan_ds_misc_cfg misc;
+    mlan_ioctl_req req;
+    mlan_status rv = MLAN_STATUS_SUCCESS;
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+
+    misc.sub_command = MLAN_OID_MISC_CONFIG_GTK_REKEY_OFFLOAD;
+
+    (void)memcpy(misc.param.gtk_rekey.kek, kek, MLAN_KEK_LEN);
+    (void)memcpy(misc.param.gtk_rekey.kck, kck, MLAN_KCK_LEN);
+    (void)memcpy(misc.param.gtk_rekey.replay_ctr, replay_ctr, MLAN_REPLAY_CTR_LEN);
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)&misc;
+    req.buf_len   = sizeof(mlan_ds_misc_cfg);
+    req.bss_index = bss_index;
+    req.req_id    = MLAN_IOCTL_MISC_CFG;
+    req.action    = MLAN_ACT_SET;
+
+    if (bss_index != 0)
+    {
+        rv = wlan_ops_uap_ioctl(mlan_adap, &req);
+    }
+    else
+    {
+        rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    }
+
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+#else
+    return WM_SUCCESS;
+#endif
+}
+
+int wifi_set_igtk_key(int bss_index, const uint8_t *pn, const uint16_t key_index, const uint8_t *key, unsigned key_len)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_ENCRYPT_KEY;
+
+    sec.param.encrypt_key.key_flags = KEY_FLAG_AES_MCAST_IGTK;
+    sec.param.encrypt_key.key_index = key_index;
+
+    (void)memcpy((void *)sec.param.encrypt_key.pn, (const void *)pn, SEQ_MAX_SIZE);
+    sec.param.encrypt_key.key_len = key_len;
+    (void)memcpy((void *)sec.param.encrypt_key.key_material, (const void *)key, key_len);
+
+    return wifi_send_key_material_cmd(bss_index, &sec);
+}
+
+int wifi_remove_key(int bss_index, bool is_pairwise, const uint8_t key_index, const uint8_t *mac_addr)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_ENCRYPT_KEY;
+
+    if (key_index == KEY_INDEX_CLEAR_ALL)
+    {
+        sec.param.encrypt_key.key_disable = MTRUE;
+    }
+    else
+    {
+        sec.param.encrypt_key.key_remove = MTRUE;
+        sec.param.encrypt_key.key_index  = key_index;
+    }
+
+    sec.param.encrypt_key.key_len   = MLAN_MAX_KEY_LENGTH;
+    sec.param.encrypt_key.key_flags = KEY_FLAG_REMOVE_KEY;
+
+    if (mac_addr)
+    {
+        (void)memcpy((void *)sec.param.encrypt_key.mac_addr, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    return wifi_send_key_material_cmd(bss_index, &sec);
+}
+
+
+
+static int wifi_send_rf_antenna_cmd(t_u16 action, wifi_antcfg_t *wifi_antcfg)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    mlan_ds_ant_cfg_1x1 ant_cfg_1x1;
+
+    (void)memset(&ant_cfg_1x1, 0x00, sizeof(mlan_ds_ant_cfg_1x1));
+
+    ant_cfg_1x1.antenna       = (t_u32) * (wifi_antcfg->ant_mode);
+    ant_cfg_1x1.evaluate_time = (t_u16) * (wifi_antcfg->evaluate_time);
+#ifdef RW610
+    ant_cfg_1x1.evaluate_mode = (t_u8) * (wifi_antcfg->evaluate_mode);
+#endif
+
+    if (action != HostCmd_ACT_GEN_GET && action != HostCmd_ACT_GEN_SET)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0x00, S_DS_GEN + sizeof(HostCmd_DS_802_11_RF_ANTENNA));
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    mlan_status rv =
+        wlan_ops_sta_prepare_cmd(pmpriv, HostCmd_CMD_802_11_RF_ANTENNA, action, 0, NULL, &ant_cfg_1x1, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        (void)wifi_put_command_lock();
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? wifi_antcfg : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+#ifndef RW610
+int wifi_get_antenna(t_u32 *ant_mode, t_u16 *evaluate_time, t_u16 *current_antenna)
+#else
+int wifi_get_antenna(t_u32 *ant_mode, t_u16 *evaluate_time, t_u8 *evaluate_mode, t_u16 *current_antenna)
+#endif
+{
+    if (ant_mode == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    wifi_antcfg_t antenna_cfg;
+    antenna_cfg.ant_mode        = ant_mode;
+    antenna_cfg.evaluate_time   = evaluate_time;
+#ifdef RW610
+    antenna_cfg.evaluate_mode   = evaluate_mode;
+#endif
+    antenna_cfg.current_antenna = current_antenna;
+
+    int rv = wifi_send_rf_antenna_cmd(HostCmd_ACT_GEN_GET, &antenna_cfg);
+    if (rv != WM_SUCCESS || wm_wifi.cmd_resp_status != WM_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+
+#ifndef RW610
+int wifi_set_antenna(t_u32 ant_mode, t_u16 evaluate_time)
+{
+    wifi_antcfg_t antenna_cfg;
+    antenna_cfg.ant_mode      = &ant_mode;
+    antenna_cfg.evaluate_time = &evaluate_time;
+
+    return wifi_send_rf_antenna_cmd(HostCmd_ACT_GEN_SET, &antenna_cfg);
+}
+#else
+int wifi_set_antenna(t_u32 ant_mode, t_u16 evaluate_time, t_u8 evaluate_mode)
+{
+    wifi_antcfg_t antenna_cfg;
+    antenna_cfg.ant_mode      = &ant_mode;
+    antenna_cfg.evaluate_time = &evaluate_time;
+    antenna_cfg.evaluate_mode = &evaluate_mode;
+
+    return wifi_send_rf_antenna_cmd(HostCmd_ACT_GEN_SET, &antenna_cfg);
+}
+#endif /*RW610*/
+
+#if CONFIG_WIFI_GET_LOG
+static int wifi_send_get_log_cmd(wlan_pkt_stats_t *stats, mlan_bss_type bss_type)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+    cmd->result  = 0x0;
+
+    mlan_status rv =
+        wlan_ops_sta_prepare_cmd(pmpriv, HostCmd_CMD_802_11_GET_LOG, HostCmd_ACT_GEN_GET, 0, NULL, NULL, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    return wifi_wait_for_cmdresp(stats);
+}
+
+int wifi_get_log(wlan_pkt_stats_t *stats, mlan_bss_type bss_type)
+
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[bss_type];
+    int rv               = wifi_send_get_log_cmd(stats, bss_type);
+    if (rv != WM_SUCCESS || wm_wifi.cmd_resp_status != WM_SUCCESS)
+        return -WM_FAIL;
+
+    stats->rx_unicast_cnt = stats->rx_frag - stats->mcast_rx_frame;
+    stats->tx_overrun_cnt = pmpriv->tx_overrun_cnt;
+    stats->rx_overrun_cnt = pmpriv->rx_overrun_cnt;
+
+    return WM_SUCCESS;
+}
+#endif
+
+static int wifi_send_cmd_802_11_supplicant_pmk(int mode, mlan_ds_sec_cfg *sec, mlan_act_ioctl action)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ioctl_req req;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)sec;
+    req.buf_len   = sizeof(mlan_ds_sec_cfg);
+    req.bss_index = 0;
+    req.req_id    = MLAN_IOCTL_SEC_CFG;
+    req.action    = action;
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_send_add_wpa_pmk(int mode, char *ssid, char *bssid, char *pmk, unsigned int len)
+{
+    if (ssid == MNULL || (len != MLAN_MAX_KEY_LENGTH))
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_PASSPHRASE;
+
+    /* SSID */
+    int ssid_len = strlen(ssid);
+    if (ssid_len > MLAN_MAX_SSID_LENGTH)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_passphrase *pp = &sec.param.passphrase;
+    pp->ssid.ssid_len      = ssid_len;
+    (void)memcpy((void *)pp->ssid.ssid, (const void *)ssid, ssid_len);
+
+    /* MAC */
+    if (bssid != NULL)
+    {
+        (void)memcpy((void *)pp->bssid, (const void *)bssid, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    /* PMK */
+    pp->psk_type = MLAN_PSK_PMK;
+    (void)memcpy((void *)pp->psk.pmk.pmk, (const void *)pmk, len);
+
+    return wifi_send_cmd_802_11_supplicant_pmk(mode, &sec, MLAN_ACT_SET);
+}
+
+/* fixme: This function has not been tested because of known issue in
+   calling function. The calling function has been disabled for that */
+int wifi_send_get_wpa_pmk(int mode, char *ssid)
+{
+    if (ssid == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_PASSPHRASE;
+
+    /* SSID */
+    int ssid_len = strlen(ssid);
+    if (ssid_len > MLAN_MAX_SSID_LENGTH)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_passphrase *pp = &sec.param.passphrase;
+    pp->ssid.ssid_len      = ssid_len;
+    (void)memcpy((void *)pp->ssid.ssid, (const void *)ssid, ssid_len);
+
+    /* Zero MAC */
+
+    pp->psk_type = MLAN_PSK_QUERY;
+
+    return wifi_send_cmd_802_11_supplicant_pmk(mode, &sec, MLAN_ACT_GET);
+}
+
+/*
+Note:
+Passphrase can be between 8 to 63 if it is ASCII and 64 if its PSK
+hexstring
+*/
+int wifi_send_add_wpa_psk(int mode, char *ssid, char *passphrase, unsigned int len)
+{
+    if (ssid == MNULL || ((len < MLAN_MIN_PASSPHRASE_LENGTH) || (len > MLAN_MAX_PASSPHRASE_LENGTH)))
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_PASSPHRASE;
+
+    /* SSID */
+    int ssid_len = strlen(ssid);
+    if (ssid_len > MLAN_MAX_SSID_LENGTH)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_passphrase *pp = &sec.param.passphrase;
+    pp->ssid.ssid_len      = ssid_len;
+    (void)memcpy((void *)pp->ssid.ssid, (const void *)ssid, ssid_len);
+
+    /* Zero MAC */
+
+    /* Passphrase */
+    pp->psk_type                      = MLAN_PSK_PASSPHRASE;
+    pp->psk.passphrase.passphrase_len = len;
+    (void)memcpy((void *)pp->psk.passphrase.passphrase, (const void *)passphrase, len);
+
+    return wifi_send_cmd_802_11_supplicant_pmk(mode, &sec, MLAN_ACT_SET);
+}
+
+/*
+Note:
+Password can be between 1 to 255 if it is ASCII
+*/
+int wifi_send_add_wpa3_password(int mode, char *ssid, char *password, unsigned int len)
+{
+    if (ssid == MNULL || ((len < MLAN_MIN_PASSWORD_LENGTH) || (len > MLAN_MAX_PASSWORD_LENGTH)))
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_PASSWORD;
+
+    /* SSID */
+    int ssid_len = strlen(ssid);
+    if (ssid_len > MLAN_MAX_SSID_LENGTH)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_passphrase *pp = &sec.param.passphrase;
+    pp->ssid.ssid_len      = ssid_len;
+    (void)memcpy((void *)pp->ssid.ssid, (const void *)ssid, ssid_len);
+
+    /* Zero MAC */
+
+    /* Passphrase */
+    pp->psk_type              = MLAN_PSK_PASSWORD;
+    pp->password.password_len = len;
+    (void)memcpy((void *)pp->password.password, (const void *)password, len);
+
+    return wifi_send_cmd_802_11_supplicant_pmk(mode, &sec, MLAN_ACT_SET);
+}
+
+int wifi_send_clear_wpa_psk(int mode, const char *ssid)
+{
+    if (ssid == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_PASSPHRASE;
+
+    /* SSID */
+    int ssid_len = strlen(ssid);
+    if (ssid_len > MLAN_MAX_SSID_LENGTH)
+    {
+        return -WM_E_INVAL;
+    }
+
+    sec.param.passphrase.ssid.ssid_len = ssid_len;
+    (void)strcpy((char *)sec.param.passphrase.ssid.ssid, ssid);
+
+    /* Zero MAC */
+
+    sec.param.passphrase.psk_type = MLAN_PSK_CLEAR;
+    return wifi_send_cmd_802_11_supplicant_pmk(mode, &sec, MLAN_ACT_SET);
+}
+
+int wifi_send_enable_supplicant(int mode, const char *ssid)
+{
+    if (ssid == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_PASSPHRASE;
+
+    /* SSID */
+    int ssid_len = strlen(ssid);
+    if (ssid_len > MLAN_MAX_SSID_LENGTH)
+    {
+        return -WM_E_INVAL;
+    }
+
+    sec.param.passphrase.ssid.ssid_len = ssid_len;
+    (void)strcpy((char *)sec.param.passphrase.ssid.ssid, ssid);
+
+    /* Zero MAC */
+
+    sec.param.passphrase.psk_type = MLAN_PSK_PASSPHRASE;
+    return wifi_send_cmd_802_11_supplicant_pmk(mode, &sec, MLAN_ACT_SET);
+}
+
+int wifi_send_disable_supplicant(int mode)
+{
+    mlan_ds_sec_cfg sec;
+
+    (void)memset(&sec, 0x00, sizeof(mlan_ds_sec_cfg));
+    sec.sub_command = MLAN_OID_SEC_CFG_PASSPHRASE;
+
+    sec.param.passphrase.psk_type = MLAN_PSK_CLEAR;
+
+    return wifi_send_cmd_802_11_supplicant_pmk(mode, &sec, MLAN_ACT_SET);
+}
+
+int wifi_set_mac_multicast_addr(const char *mlist, t_u32 num_of_addr)
+{
+    if (mlist == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+    if (num_of_addr > MLAN_MAX_MULTICAST_LIST_SIZE)
+    {
+        return -WM_E_INVAL;
+    }
+#if !CONFIG_MEM_POOLS
+    mlan_multicast_list *mcast_list = (mlan_multicast_list *)OSA_MemoryAllocate(sizeof(mlan_multicast_list));
+#else
+    mlan_multicast_list *mcast_list = (mlan_multicast_list *)OSA_MemoryPoolAllocate(buf_256_MemoryPool);
+#endif
+    if (mcast_list == NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memset(mcast_list, 0x0, sizeof(mlan_multicast_list));
+    (void)memcpy(mcast_list->mac_list, (const void *)mlist, num_of_addr * MLAN_MAC_ADDR_LENGTH);
+    mcast_list->num_multicast_addr = num_of_addr;
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MAC_MULTICAST_ADR,
+                                              HostCmd_ACT_GEN_SET, 0, NULL, mcast_list, cmd);
+
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(mcast_list);
+#else
+        OSA_MemoryPoolFree(buf_256_MemoryPool, mcast_list);
+#endif
+
+        return -WM_FAIL;
+    }
+    (void)wifi_wait_for_cmdresp(NULL);
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(mcast_list);
+#else
+    OSA_MemoryPoolFree(buf_256_MemoryPool, mcast_list);
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wifi_get_otp_user_data(uint8_t *buf, uint16_t len)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    mlan_ds_misc_otp_user_data pdata;
+
+    if (buf == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    cmd->seq_num           = 0x0;
+    cmd->result            = 0x0;
+    pdata.user_data_length = len > MAX_OTP_USER_DATA_LEN ? MAX_OTP_USER_DATA_LEN : len;
+
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_OTP_READ_USER_DATA,
+                                              HostCmd_ACT_GEN_GET, 0, NULL, &pdata, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)wifi_wait_for_cmdresp(buf);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_cal_data(wifi_cal_data_t *cal_data)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_802_11_CFG_DATA) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_CFG_DATA);
+
+    HostCmd_DS_802_11_CFG_DATA *cfg_data_cmd = (HostCmd_DS_802_11_CFG_DATA *)((uint32_t)cmd + S_DS_GEN);
+
+    cfg_data_cmd->action   = HostCmd_ACT_GEN_GET;
+    cfg_data_cmd->type     = 0x02;
+    cfg_data_cmd->data_len = 0x00;
+
+    cmd->size    = size;
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(cal_data);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+#if CONFIG_11AX
+void wifi_request_get_fw_info(mlan_private *priv, mlan_fw_info *fw_info)
+{
+    (void)memset(fw_info, 0x0, sizeof(mlan_fw_info));
+
+    fw_info->fw_ver = mlan_adap->fw_release_number;
+    (void)memcpy(fw_info->mac_addr, priv->curr_addr, MLAN_MAC_ADDR_LENGTH);
+    fw_info->fw_bands           = mlan_adap->fw_bands;
+    fw_info->hw_dev_mcs_support = mlan_adap->hw_dev_mcs_support;
+
+    fw_info->hw_2g_hecap_len = mlan_adap->hw_2g_hecap_len;
+
+    (void)memcpy(fw_info->hw_2g_he_cap, mlan_adap->hw_2g_he_cap, mlan_adap->hw_2g_hecap_len);
+
+    fw_info->hw_hecap_len = mlan_adap->hw_hecap_len;
+
+    (void)memcpy(fw_info->hw_he_cap, mlan_adap->hw_he_cap, mlan_adap->hw_hecap_len);
+}
+#endif
+
+#if CONFIG_WIFI_CAPA
+void wifi_get_fw_info(mlan_bss_type type, t_u16 *fw_bands)
+{
+    mlan_fw_info fw_info;
+
+    (void)memset(&fw_info, 0x0, sizeof(mlan_fw_info));
+    fw_info.fw_ver = mlan_adap->fw_release_number;
+    (void)memcpy(fw_info.mac_addr, mlan_adap->priv[type]->curr_addr, MLAN_MAC_ADDR_LENGTH);
+    fw_info.fw_bands           = mlan_adap->fw_bands;
+    fw_info.hw_dev_mcs_support = mlan_adap->hw_dev_mcs_support;
+
+    *fw_bands = fw_info.fw_bands;
+}
+#endif
+
+int wifi_get_firmware_version_ext(wifi_fw_version_ext_t *version_ext)
+{
+    if (version_ext == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    mlan_status rv       = wifi_prepare_and_send_cmd(pmpriv, HostCmd_CMD_VERSION_EXT, HostCmd_ACT_GEN_GET, 0, NULL,
+                                                     &version_ext->version_str_sel, MLAN_BSS_TYPE_STA, version_ext);
+    return (rv == MLAN_STATUS_SUCCESS ? WM_SUCCESS : -WM_FAIL);
+}
+
+int wifi_get_firmware_version(wifi_fw_version_t *ver)
+{
+    if (ver == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    union
+    {
+        uint32_t l;
+        uint8_t c[4];
+    } u_ver;
+    char fw_ver[32];
+
+    u_ver.l = mlan_adap->fw_release_number;
+    (void)sprintf(fw_ver, "%u.%u.%u.p%u", u_ver.c[2], u_ver.c[1], u_ver.c[0], u_ver.c[3]);
+
+    (void)snprintf(ver->version_str, MLAN_MAX_VER_STR_LEN, driver_version_format, fw_ver, driver_version);
+
+    return WM_SUCCESS;
+}
+
+/* Region: US(US) or Canada(CA) or Singapore(SG) 2.4 GHz */
+static wifi_sub_band_set_t subband_US_CA_SG_2_4_GHz[] = {{1, 11, 20}};
+
+/* Region: Europe(EU), Australia(AU), Republic of Korea(KR),
+China(CN) 2.4 GHz */
+static wifi_sub_band_set_t subband_EU_AU_KR_CN_2_4GHz[] = {{1, 13, 20}};
+
+/* Region: Japan(JP) 2.4 GHz */
+static wifi_sub_band_set_t subband_JP_2_4GHz[] = {
+    {1, 14, 20},
+};
+
+/* Region: World Wide Safe Mode(WWSM) 2.4 GHz */
+static wifi_sub_band_set_t subband_WWSM_2_4GHz[] = {
+    {1, 14, 22},
+};
+
+/* Region: Constrained 2.4 Ghz */
+static wifi_sub_band_set_t subband_CS_2_4GHz[] = {{1, 9, 20}, {10, 2, 10}};
+
+#if CONFIG_5GHz_SUPPORT
+
+#if (CONFIG_UNII4_BAND_SUPPORT)
+/* Region: US(US) 5 GHz */
+wifi_sub_band_set_t subband_US_5_GHz[] = {{36, 8, 20}, {100, 11, 20}, {149, 8, 20}};
+
+/* Region: France(FR) or Singapore(SG) 5 GHz */
+wifi_sub_band_set_t subband_SG_FR_5_GHz[] = {{36, 8, 20}, {100, 11, 20}, {149, 5, 20}};
+#else
+/* Region: US(US) or France(FR) or Singapore(SG) 5 GHz */
+static wifi_sub_band_set_t subband_US_SG_FR_5_GHz[] = {{36, 8, 20}, {100, 11, 20}, {149, 5, 20}};
+#endif
+
+/* Region: Canada(CA) 5 GHz */
+static wifi_sub_band_set_t subband_CA_5_GHz[] = {{36, 8, 20}, {100, 5, 20}, {132, 3, 20}, {149, 5, 20}};
+
+/* Region: Region: Europe(EU), Australia(AU), Republic of Korea(KR)
+ * 5 GHz */
+static wifi_sub_band_set_t subband_EU_AU_KR_5_GHz[] = {
+    {36, 8, 20},
+    {100, 11, 20},
+    {149, 5, 20},
+};
+
+/* Region: Japan(JP) 5 GHz */
+static wifi_sub_band_set_t subband_JP_5_GHz[] = {
+    {8, 3, 23},
+    {36, 8, 23},
+    {100, 11, 23},
+};
+
+/* Region: China(CN) 5 Ghz */
+static wifi_sub_band_set_t subband_CN_5_GHz[] = {
+    {36, 4, 23},
+    {52, 4, 23},
+    {149, 5, 33},
+};
+
+/* Region: World Wide Safe Mode(WWSM) 5 GHz */
+static wifi_sub_band_set_t subband_WWSM_5_GHz[] = {{36, 8, 22}, {100, 11, 22}, {149, 5, 22}};
+
+#endif /* CONFIG_5GHz_SUPPORT */
+
+int wifi_get_region_code(t_u32 *region_code)
+{
+    *region_code = mlan_adap->region_code;
+    return WM_SUCCESS;
+}
+
+int wifi_set_region_code(t_u32 region_code)
+{
+    mlan_ds_misc_cfg misc = {
+        .param.region_code = region_code,
+    };
+
+    if ((misc.param.region_code == 0x41) || (misc.param.region_code == 0xFE))
+    {
+        (void)PRINTF("Region code 0XFF is used for Japan to support channels of both 2.4GHz band and 5GHz band.\r\n");
+        (void)PRINTF("Region code 0X40 is used for Japan to support channels of 5GHz band.\r\n");
+        return -WM_FAIL;
+    }
+
+    mlan_ioctl_req req = {
+        .bss_index = 0,
+        .pbuf      = (t_u8 *)&misc,
+        .action    = MLAN_ACT_SET,
+    };
+
+    mlan_status mrv = wlan_misc_ioctl_region(mlan_adap, &req);
+    if (mrv != MLAN_STATUS_SUCCESS)
+    {
+        wifi_w("Unable to set region code");
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_enable_11d_support()
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    wrapper_wlan_11d_enable(ENABLE_11D);
+
+    wlan_11d_support_APIs(pmpriv);
+
+    return wlan_enable_11d_support(pmpriv);
+}
+
+int wifi_enable_uap_11d_support()
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+
+    wrapper_wlan_uap_11d_enable(ENABLE_11D);
+
+    wlan_11d_support_APIs(pmpriv);
+
+    /* set callback for setting domain params when uap start */
+    wifi_uap_enable_11d_support();
+
+    return wlan_enable_11d_support(pmpriv);
+}
+
+int wifi_disable_11d_support()
+{
+    mlan_adap->priv[0]->state_11d.user_enable_11d_support = DISABLE_11D;
+    wrapper_wlan_11d_enable(DISABLE_11D);
+
+    return WM_SUCCESS;
+}
+
+int wifi_disable_uap_11d_support()
+{
+    mlan_adap->priv[1]->state_11d.user_enable_11d_support = DISABLE_11D;
+    wrapper_wlan_uap_11d_enable(DISABLE_11D);
+
+    wm_wifi.enable_11d_support   = false;
+    wm_wifi.uap_support_11d_apis = MNULL;
+    return WM_SUCCESS;
+}
+
+int wifi_enable_11d_support_APIs(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    return wlan_11d_support_APIs(pmpriv);
+}
+
+wifi_sub_band_set_t *get_sub_band_from_region_code(int region_code, t_u8 *nr_sb)
+{
+    *nr_sb                        = 1;
+    wifi_sub_band_set_t *ret_band = NULL;
+
+    switch (region_code)
+    {
+        case 0x10:
+        case 0x20:
+            ret_band = subband_US_CA_SG_2_4_GHz;
+            break;
+        case 0x30:
+        case 0x32:
+        case 0x50:
+            ret_band = subband_EU_AU_KR_CN_2_4GHz;
+            break;
+        case 0xFF:
+            ret_band = subband_JP_2_4GHz;
+            break;
+        case 0x00:
+            ret_band = subband_WWSM_2_4GHz;
+            break;
+        default:
+            *nr_sb   = 2;
+            ret_band = subband_CS_2_4GHz;
+            break;
+    }
+    return ret_band;
+}
+
+#if CONFIG_5GHz_SUPPORT
+wifi_sub_band_set_t *get_sub_band_from_region_code_5ghz(int region_code, t_u8 *nr_sb)
+{
+    *nr_sb                        = 1;
+    wifi_sub_band_set_t *ret_band = NULL;
+
+    switch (region_code)
+    {
+        case 0x10:
+#if (CONFIG_UNII4_BAND_SUPPORT)
+            *nr_sb = 3;
+            return subband_US_5_GHz;
+#endif
+        case 0x32:
+            *nr_sb = 3;
+#if (CONFIG_UNII4_BAND_SUPPORT)
+            ret_band = subband_SG_FR_5_GHz;
+#else
+            ret_band = subband_US_SG_FR_5_GHz;
+#endif
+            break;
+        case 0x20:
+            *nr_sb   = 4;
+            ret_band = subband_CA_5_GHz;
+            break;
+        case 0x30:
+            *nr_sb   = 3;
+            ret_band = subband_EU_AU_KR_5_GHz;
+            break;
+        case 0x40:
+        case 0xFF:
+            *nr_sb   = 3;
+            ret_band = subband_JP_5_GHz;
+            break;
+        case 0x50:
+            *nr_sb   = 3;
+            ret_band = subband_CN_5_GHz;
+            break;
+        case 0x00:
+            *nr_sb   = 3;
+            ret_band = subband_WWSM_5_GHz;
+            break;
+        default:
+            *nr_sb = 3;
+#if (CONFIG_UNII4_BAND_SUPPORT)
+            ret_band = subband_US_5_GHz;
+#else
+            ret_band = subband_US_SG_FR_5_GHz;
+#endif
+            break;
+    }
+    return ret_band;
+}
+#endif /* CONFIG_5GHz_SUPPORT */
+
+bool wifi_11d_is_channel_allowed(int channel)
+{
+    t_u8 i, j;
+    t_u8 k;
+    t_u8 nr_sb = 0;
+
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    wifi_sub_band_set_t *sub_band = NULL;
+
+    if (channel > 14)
+    {
+#if CONFIG_5GHz_SUPPORT
+        sub_band = get_sub_band_from_region_code_5ghz(pmpriv->adapter->region_code, &nr_sb);
+#else
+        wifi_w("5 GHz support is not enabled");
+
+        return false;
+#endif /* CONFIG_5GHz_SUPPORT */
+    }
+    else
+    {
+        sub_band = get_sub_band_from_region_code(pmpriv->adapter->region_code, &nr_sb);
+    }
+
+    for (i = 0; i < nr_sb; i++)
+    {
+        j = sub_band[i].first_chan;
+
+        for (k = 0; k < sub_band[i].no_of_chan; k++)
+        {
+            if (j == channel)
+            {
+                return true;
+            }
+
+            if (channel > 14)
+            {
+                j += 4;
+            }
+            else
+            {
+                j++;
+            }
+        }
+    }
+
+    /*For channel 144*/
+    if (144 == channel)
+    {
+        return wlan_check_channel_by_region_table(pmpriv, channel);
+    }
+
+    return false;
+}
+
+int wifi_enable_ecsa_support(void)
+{
+    return wrapper_wlan_ecsa_enable();
+}
+
+bool wifi_is_ecsa_enabled(void)
+{
+    return mlan_adap->ecsa_enable;
+}
+
+static int get_free_mgmt_ie_index(unsigned int *mgmt_ie_index)
+{
+    unsigned int idx;
+
+    for (idx = 0; idx < 32; idx++)
+    {
+        if ((mgmt_ie_index_bitmap & MBIT((t_u32)idx)) == 0U)
+        {
+            *mgmt_ie_index = idx;
+            return WM_SUCCESS;
+        }
+    }
+    return -WM_FAIL;
+}
+
+static void set_ie_index(unsigned int index)
+{
+    mgmt_ie_index_bitmap |= (MBIT(index));
+}
+
+static void clear_ie_index(unsigned int index)
+{
+    mgmt_ie_index_bitmap &= ~(MBIT(index));
+}
+
+#ifdef SD8801
+static int wifi_config_ext_coex(int action,
+                                const wifi_ext_coex_config_t *ext_coex_config,
+                                wifi_ext_coex_stats_t *ext_coex_stats)
+{
+    int ret;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)wifi_get_command_lock();
+
+    cmd->command                                           = HostCmd_CMD_ROBUST_COEX;
+    cmd->size                                              = sizeof(HostCmd_DS_ExtBLECoex_Config_t) + S_DS_GEN;
+    cmd->seq_num                                           = 0;
+    cmd->result                                            = 0;
+    cmd->params.ext_ble_coex_cfg.action                    = action;
+    cmd->params.ext_ble_coex_cfg.reserved                  = 0;
+    cmd->params.ext_ble_coex_cfg.coex_cfg_data.header.type = TLV_TYPE_EXT_BLE_COEX_CFG;
+    cmd->params.ext_ble_coex_cfg.coex_cfg_data.header.len =
+        sizeof(MrvlIETypes_ExtBLECoex_Config_t) - sizeof(MrvlIEtypesHeader_t);
+
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.Enabled         = ext_coex_config->Enabled;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.IgnorePriority  = ext_coex_config->IgnorePriority;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.DefaultPriority = ext_coex_config->DefaultPriority;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.EXT_RADIO_REQ_ip_gpio_num =
+            ext_coex_config->EXT_RADIO_REQ_ip_gpio_num;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.EXT_RADIO_REQ_ip_gpio_polarity =
+            ext_coex_config->EXT_RADIO_REQ_ip_gpio_polarity;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.EXT_RADIO_PRI_ip_gpio_num =
+            ext_coex_config->EXT_RADIO_PRI_ip_gpio_num;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.EXT_RADIO_PRI_ip_gpio_polarity =
+            ext_coex_config->EXT_RADIO_PRI_ip_gpio_polarity;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.WLAN_GRANT_op_gpio_num = ext_coex_config->WLAN_GRANT_op_gpio_num;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.WLAN_GRANT_op_gpio_polarity =
+            ext_coex_config->WLAN_GRANT_op_gpio_polarity;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.reserved_1 = ext_coex_config->reserved_1;
+        cmd->params.ext_ble_coex_cfg.coex_cfg_data.reserved_2 = ext_coex_config->reserved_2;
+    }
+    ret = wifi_wait_for_cmdresp(ext_coex_stats);
+    return ret;
+}
+#endif
+
+static bool ie_index_is_set(unsigned int index)
+{
+    return (mgmt_ie_index_bitmap & (MBIT(index))) ? MTRUE : MFALSE;
+}
+
+void reset_ie_index()
+{
+    mgmt_ie_index_bitmap = 0x0000000F;
+}
+
+static int wifi_config_mgmt_ie(mlan_bss_type bss_type,
+                               t_u16 action,
+                               IEEEtypes_ElementId_t index,
+                               void *buffer,
+                               unsigned int *ie_len,
+                               int mgmt_bitmap_index)
+{
+    uint8_t *buf, *pos;
+    IEEEtypes_Header_t *ptlv_header = NULL;
+    uint16_t buf_len                = 0;
+    tlvbuf_custom_ie *tlv           = NULL;
+    custom_ie *ie_ptr               = NULL;
+    unsigned int mgmt_ie_index      = -1;
+    int total_len =
+        sizeof(tlvbuf_custom_ie) + 2U * (sizeof(custom_ie) - MAX_IE_SIZE) + sizeof(IEEEtypes_Header_t) + *ie_len;
+    int ret = WM_SUCCESS;
+
+#if !CONFIG_MEM_POOLS
+    buf = (uint8_t *)OSA_MemoryAllocate(total_len);
+#else
+    buf = OSA_MemoryPoolAllocate(buf_512_MemoryPool);
+#endif
+    if (buf == MNULL)
+    {
+        wifi_e("Cannot allocate memory");
+        return -WM_FAIL;
+    }
+
+    (void)memset(buf, 0, total_len);
+
+    tlv       = (tlvbuf_custom_ie *)(void *)buf;
+    tlv->type = MRVL_MGMT_IE_LIST_TLV_ID;
+
+    /* Locate headers */
+    ie_ptr = (custom_ie *)(tlv->ie_data);
+    /* Set TLV fields */
+    buf_len = sizeof(tlvbuf_custom_ie);
+
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        if (*ie_len == 0U)
+        {
+            /*
+               MGMT_WPA_IE = MGMT_VENDOR_SPECIFIC_221
+               MGMT_WPS_IE = MGMT_VENDOR_SPECIFIC_221
+               */
+
+            if (!ie_index_is_set(mgmt_bitmap_index))
+            {
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree(buf);
+#else
+                OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+                return -WM_FAIL;
+            }
+
+            ie_ptr->mgmt_subtype_mask = MGMT_MASK_CLEAR;
+            ie_ptr->ie_length         = 0;
+            ie_ptr->ie_index          = (t_u16)mgmt_bitmap_index;
+
+            tlv->length = sizeof(custom_ie) - MAX_IE_SIZE;
+            buf_len += tlv->length;
+            clear_ie_index(mgmt_bitmap_index);
+        }
+        else
+        {
+            ret = get_free_mgmt_ie_index(&mgmt_ie_index);
+
+            if (WM_SUCCESS != ret)
+            {
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree(buf);
+#else
+                OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+                return -WM_FAIL;
+            }
+
+            pos         = ie_ptr->ie_buffer;
+            ptlv_header = (IEEEtypes_Header_t *)(void *)pos;
+            pos += sizeof(IEEEtypes_Header_t);
+
+            ptlv_header->element_id = (IEEEtypes_ElementId_e)index;
+            ptlv_header->len        = *ie_len;
+            if (bss_type == MLAN_BSS_TYPE_UAP)
+            {
+                ie_ptr->mgmt_subtype_mask =
+                    MGMT_MASK_BEACON | MGMT_MASK_PROBE_RESP | MGMT_MASK_ASSOC_RESP | MGMT_MASK_REASSOC_RESP;
+            }
+            else if (bss_type == MLAN_BSS_TYPE_STA)
+            {
+                ie_ptr->mgmt_subtype_mask = MGMT_MASK_PROBE_REQ | MGMT_MASK_ASSOC_REQ | MGMT_MASK_REASSOC_REQ;
+            }
+            else
+            { /* Do Nothing */
+            }
+
+            tlv->length       = sizeof(custom_ie) + sizeof(IEEEtypes_Header_t) + *ie_len - MAX_IE_SIZE;
+            ie_ptr->ie_length = sizeof(IEEEtypes_Header_t) + *ie_len;
+            ie_ptr->ie_index  = mgmt_ie_index;
+
+            buf_len += tlv->length;
+
+            (void)memcpy((void *)pos, (const void *)buffer, *ie_len);
+        }
+    }
+    else if (action == HostCmd_ACT_GEN_GET)
+    {
+        /* Get WPS IE */
+        tlv->length = 0;
+    }
+    else
+    { /* Do Nothing */
+    }
+
+    mlan_status rv = wrapper_wlan_cmd_mgmt_ie(bss_type, buf, buf_len, action);
+
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+        return -WM_FAIL;
+    }
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        if (wm_wifi.cmd_resp_status != 0)
+        {
+            wifi_w("Unable to get mgmt ie buffer");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(buf);
+#else
+            OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+            return wm_wifi.cmd_resp_status;
+        }
+        ie_ptr = (custom_ie *)(void *)(buf);
+        (void)memcpy((void *)buffer, (const void *)ie_ptr->ie_buffer, ie_ptr->ie_length);
+        *ie_len = ie_ptr->ie_length;
+    }
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(buf);
+#else
+    OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+
+    if ((action == HostCmd_ACT_GEN_SET) && *ie_len)
+    {
+        set_ie_index(mgmt_ie_index);
+        return mgmt_ie_index;
+    }
+    else
+    {
+        return WM_SUCCESS;
+    }
+}
+
+int wifi_get_mgmt_ie(mlan_bss_type bss_type, IEEEtypes_ElementId_t index, void *buf, unsigned int *buf_len)
+{
+    return wifi_config_mgmt_ie(bss_type, HostCmd_ACT_GEN_GET, index, buf, buf_len, 0);
+}
+
+int wifi_set_mgmt_ie(mlan_bss_type bss_type, IEEEtypes_ElementId_t id, void *buf, unsigned int buf_len)
+{
+    unsigned int data_len = buf_len;
+
+    return wifi_config_mgmt_ie(bss_type, HostCmd_ACT_GEN_SET, id, buf, &data_len, 0);
+}
+
+int wifi_clear_mgmt_ie(mlan_bss_type bss_type, IEEEtypes_ElementId_t index, int mgmt_bitmap_index)
+{
+    unsigned int data_len = 0;
+    return wifi_config_mgmt_ie(bss_type, HostCmd_ACT_GEN_SET, index, NULL, &data_len, mgmt_bitmap_index);
+}
+
+static int wifi_config_mgmt_ie2(
+    mlan_bss_type bss_type, t_u16 action, t_u16 mask, void *buffer, unsigned int *ie_len, int mgmt_bitmap_index)
+{
+    uint8_t *buf;
+    uint16_t buf_len           = 0;
+    tlvbuf_custom_ie *tlv      = NULL;
+    custom_ie *ie_ptr          = NULL;
+    unsigned int mgmt_ie_index = -1;
+    int total_len              = sizeof(tlvbuf_custom_ie) + (sizeof(custom_ie) - MAX_IE_SIZE) + *ie_len;
+    int ret                    = WM_SUCCESS;
+
+#if !CONFIG_MEM_POOLS
+    buf = (uint8_t *)OSA_MemoryAllocate(total_len);
+#else
+    buf = OSA_MemoryPoolAllocate(buf_512_MemoryPool);
+#endif
+    if (buf == MNULL)
+    {
+        wifi_e("Cannot allocate memory");
+        return -WM_FAIL;
+    }
+
+    (void)memset(buf, 0, total_len);
+
+    tlv       = (tlvbuf_custom_ie *)(void *)buf;
+    tlv->type = MRVL_MGMT_IE_LIST_TLV_ID;
+
+    /* Locate headers */
+    ie_ptr = (custom_ie *)(tlv->ie_data);
+    /* Set TLV fields */
+    buf_len = sizeof(tlvbuf_custom_ie);
+
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        if (*ie_len == 0U)
+        {
+            /*
+               MGMT_WPA_IE = MGMT_VENDOR_SPECIFIC_221
+               MGMT_WPS_IE = MGMT_VENDOR_SPECIFIC_221
+               */
+
+            if (!ie_index_is_set(mgmt_bitmap_index))
+            {
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree(buf);
+#else
+                OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+                return -WM_FAIL;
+            }
+
+            ie_ptr->mgmt_subtype_mask = MGMT_MASK_CLEAR;
+            ie_ptr->ie_length         = 0;
+            ie_ptr->ie_index          = (t_u16)mgmt_bitmap_index;
+
+            tlv->length = sizeof(custom_ie) - MAX_IE_SIZE;
+            buf_len += tlv->length;
+            clear_ie_index(mgmt_bitmap_index);
+        }
+        else
+        {
+            ret = get_free_mgmt_ie_index(&mgmt_ie_index);
+
+            if (WM_SUCCESS != ret)
+            {
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree(buf);
+#else
+                OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+                return -WM_FAIL;
+            }
+
+            tlv->length      = (sizeof(custom_ie) - MAX_IE_SIZE) + *ie_len;
+            ie_ptr->ie_index = mgmt_ie_index;
+
+            ie_ptr->mgmt_subtype_mask = mask;
+
+            ie_ptr->ie_length = *ie_len;
+
+            buf_len += tlv->length;
+
+            (void)memcpy((void *)&ie_ptr->ie_buffer, (const void *)buffer, *ie_len);
+        }
+    }
+    else if (action == HostCmd_ACT_GEN_GET)
+    {
+        /* Get WPS IE */
+        tlv->length = 0;
+    }
+    else
+    { /* Do Nothing */
+    }
+
+    mlan_status rv = wrapper_wlan_cmd_mgmt_ie(bss_type, buf, buf_len, action);
+
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+        return -WM_FAIL;
+    }
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        if (wm_wifi.cmd_resp_status != 0)
+        {
+            wifi_w("Unable to get mgmt ie buffer");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(buf);
+#else
+            OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+            return wm_wifi.cmd_resp_status;
+        }
+        ie_ptr = (custom_ie *)(void *)(buf);
+        (void)memcpy((void *)buffer, (const void *)ie_ptr->ie_buffer, ie_ptr->ie_length);
+        *ie_len = ie_ptr->ie_length;
+    }
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(buf);
+#else
+    OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+
+    if ((action == HostCmd_ACT_GEN_SET) && *ie_len)
+    {
+        set_ie_index(mgmt_ie_index);
+        return mgmt_ie_index;
+    }
+    else
+    {
+        return WM_SUCCESS;
+    }
+}
+
+int wifi_get_mgmt_ie2(mlan_bss_type bss_type, void *buf, unsigned int *buf_len)
+{
+    return wifi_config_mgmt_ie2(bss_type, HostCmd_ACT_GEN_GET, 0, buf, buf_len, 0);
+}
+
+int wifi_set_mgmt_ie2(mlan_bss_type bss_type, unsigned short mask, void *buf, unsigned int buf_len)
+{
+    unsigned int data_len = buf_len;
+
+    return wifi_config_mgmt_ie2(bss_type, HostCmd_ACT_GEN_SET, mask, buf, &data_len, 0);
+}
+
+int wifi_clear_mgmt_ie2(mlan_bss_type bss_type, int mgmt_bitmap_index)
+{
+    unsigned int data_len = 0;
+
+    return wifi_config_mgmt_ie2(bss_type, HostCmd_ACT_GEN_SET, 0, NULL, &data_len, mgmt_bitmap_index);
+}
+
+#ifdef SD8801
+int wifi_get_ext_coex_stats(wifi_ext_coex_stats_t *ext_coex_stats)
+{
+    if (ext_coex_stats == NULL)
+    {
+        wifi_e("Invalid structure passed");
+        return -WM_FAIL;
+    }
+
+    return wifi_config_ext_coex(HostCmd_ACT_GEN_GET, NULL, ext_coex_stats);
+}
+
+int wifi_set_ext_coex_config(const wifi_ext_coex_config_t *ext_coex_config)
+{
+    if (ext_coex_config == NULL)
+    {
+        wifi_e("Invalid structure passed");
+        return -WM_FAIL;
+    }
+
+    return wifi_config_ext_coex(HostCmd_ACT_GEN_SET, ext_coex_config, NULL);
+}
+#endif
+
+#if CONFIG_WPA_SUPP
+int wifi_set_custom_ie(custom_ie *beacon_ies_data,
+                       custom_ie *beacon_wps_ies_data,
+                       custom_ie *proberesp_ies_data,
+                       custom_ie *assocresp_ies_data)
+{
+    mlan_ds_misc_custom_ie *pcustom_ie = NULL;
+    t_u8 *pos                          = NULL;
+    t_u16 len                          = 0;
+    mlan_status status                 = MLAN_STATUS_SUCCESS;
+    t_u32 remain_len                   = 0;
+    HostCmd_DS_COMMAND *cmd            = NULL;
+
+    ENTER();
+
+    pcustom_ie = OSA_MemoryAllocate(sizeof(mlan_ds_misc_custom_ie));
+    if (!pcustom_ie)
+    {
+        PRINTM(MERROR, "Fail to allocate custome_ie\n");
+        status = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+
+    pcustom_ie->type = TLV_TYPE_MGMT_IE;
+
+    pos        = (t_u8 *)pcustom_ie->ie_data_list;
+    remain_len = sizeof(pcustom_ie->ie_data_list);
+    if (beacon_ies_data)
+    {
+        len = sizeof(*beacon_ies_data) - MAX_IE_SIZE + beacon_ies_data->ie_length;
+        memcpy(pos, beacon_ies_data, len);
+        pos += len;
+        remain_len -= len;
+        pcustom_ie->len += len;
+    }
+
+    if (beacon_wps_ies_data)
+    {
+        len = sizeof(*beacon_wps_ies_data) - MAX_IE_SIZE + beacon_wps_ies_data->ie_length;
+        memcpy(pos, beacon_wps_ies_data, len);
+        pos += len;
+        remain_len -= len;
+        pcustom_ie->len += len;
+    }
+
+    if (proberesp_ies_data)
+    {
+        len = sizeof(*proberesp_ies_data) - MAX_IE_SIZE + proberesp_ies_data->ie_length;
+        memcpy(pos, proberesp_ies_data, len);
+        pos += len;
+        remain_len -= len;
+        pcustom_ie->len += len;
+    }
+
+    if (assocresp_ies_data)
+    {
+        len = sizeof(*assocresp_ies_data) - MAX_IE_SIZE + assocresp_ies_data->ie_length;
+        memcpy(pos, assocresp_ies_data, len);
+        pos += len;
+        remain_len -= len;
+        pcustom_ie->len += len;
+    }
+
+    (void)wifi_get_command_lock();
+
+    cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, MLAN_BSS_TYPE_UAP);
+
+    cmd->result = 0x0;
+
+    status = wlan_ops_uap_prepare_cmd((mlan_private *)mlan_adap->priv[1], HOST_CMD_APCMD_SYS_CONFIGURE,
+                                      HostCmd_ACT_GEN_SET, 0, NULL, (void *)pcustom_ie, cmd);
+
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    OSA_MemoryFree(pcustom_ie);
+
+done:
+    LEAVE();
+    return status;
+}
+
+void wifi_get_scan_table(mlan_private *pmpriv, mlan_scan_resp *pscan_resp)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+
+    pscan_resp->pscan_table       = (t_u8 *)pmadapter->pscan_table;
+    pscan_resp->num_in_scan_table = pmadapter->num_in_scan_table;
+    pscan_resp->age_in_secs       = pmadapter->age_in_secs;
+#if CONFIG_SCAN_CHANNEL_GAP
+    pscan_resp->pchan_stats       = (t_u8 *)pmadapter->pchan_stats;
+    pscan_resp->num_in_chan_stats = pmadapter->num_in_chan_stats;
+#endif
+}
+#endif
+
+int wifi_set_chanlist(wifi_chanlist_t *chanlist)
+{
+    mlan_status ret;
+    t_u8 i         = 0;
+    t_u8 cfp_no_bg = 0;
+#if CONFIG_5GHz_SUPPORT
+    t_u8 cfp_no_a = 0;
+#endif
+    mlan_adapter *pmadapter = mlan_adap->priv[0]->adapter;
+
+#ifdef OTP_CHANINFO
+    if ((pmadapter->otp_region == MNULL) || (pmadapter->otp_region->force_reg == 0U))
+    {
+#endif
+        /*
+         * Validate if the channels provided in the channel list
+         * are valid channels according to World Wide Safe Mode.
+         */
+        for (i = 0; i < chanlist->num_chans; i++)
+        {
+            if (!wlan_is_channel_and_freq_valid(pmadapter, chanlist->chan_info[i].chan_num,
+                                                chanlist->chan_info[i].chan_freq))
+            {
+                wifi_e("Invalid channel %d\r\n", chanlist->chan_info[i].chan_num);
+                return -WM_FAIL;
+            }
+        }
+
+        /* Configure Custom CFP Tables */
+#if CONFIG_5GHz_SUPPORT
+        ret = wlan_set_custom_cfp_table(chanlist, &cfp_no_bg, &cfp_no_a);
+#else
+    ret = wlan_set_custom_cfp_table(chanlist, &cfp_no_bg);
+#endif
+        if (ret != MLAN_STATUS_SUCCESS)
+        {
+            wifi_e("Failed to set Custom CFP Table");
+            return -WM_FAIL;
+        }
+
+        /* Set Region Table */
+#if CONFIG_5GHz_SUPPORT
+        wlan_set_custom_regiontable((mlan_private *)mlan_adap->priv[0], cfp_no_bg, cfp_no_a);
+#else
+    wlan_set_custom_regiontable((mlan_private *)mlan_adap->priv[0], cfp_no_bg);
+#endif
+#ifdef OTP_CHANINFO
+    }
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wifi_get_chanlist(wifi_chanlist_t *chanlist)
+{
+    mlan_adapter *pmadapter      = mlan_adap->priv[0]->adapter;
+    region_chan_t *pchan_region  = MNULL;
+    const chan_freq_power_t *cfp = MNULL;
+    t_u32 region_idx             = 0;
+    t_u32 next_chan              = 0;
+    chanlist->num_chans          = 0;
+
+    for (region_idx = 0; region_idx < NELEMENTS(pmadapter->region_channel); region_idx++)
+    {
+        if (!pmadapter->region_channel[region_idx].valid)
+        {
+            continue;
+        }
+
+        pchan_region = &pmadapter->region_channel[region_idx];
+
+        for (next_chan = 0; next_chan < pchan_region->num_cfp; next_chan++)
+        {
+            cfp = pchan_region->pcfp + next_chan;
+            if (cfp == MNULL)
+            {
+                wifi_e("No cfp configured");
+                return -WM_FAIL;
+            }
+
+            if ((cfp->dynamic.flags & NXP_CHANNEL_DISABLED) != 0U)
+            {
+                continue;
+            }
+
+            chanlist->chan_info[chanlist->num_chans].chan_num                     = cfp->channel;
+            chanlist->chan_info[chanlist->num_chans].chan_freq                    = cfp->freq;
+            chanlist->chan_info[chanlist->num_chans].passive_scan_or_radar_detect = cfp->passive_scan_or_radar_detect;
+            chanlist->num_chans++;
+
+            if (chanlist->num_chans >= NELEMENTS(chanlist->chan_info))
+            {
+                break;
+            }
+        }
+    }
+
+    return WM_SUCCESS;
+}
+
+void wifi_get_active_channel_list(t_u8 *chan_list, t_u8 *num_chans, t_u16 acs_band)
+{
+    if (chan_list != MNULL && num_chans != MNULL)
+    {
+        wlan_get_active_channel_list((mlan_private *)mlan_adap->priv[1], chan_list, num_chans, acs_band);
+    }
+}
+
+int wifi_set_txpwrlimit(wifi_txpwrlimit_t *txpwrlimit)
+{
+    t_u8 i;
+    int ret;
+    HostCmd_DS_COMMAND *cmd                = wifi_get_command_buffer();
+    t_u8 *pByte                            = NULL;
+    MrvlIETypes_ChanTRPCConfig_t *trpc_tlv = NULL;
+
+    (void)wifi_get_command_lock();
+
+    cmd->command = HostCmd_CMD_CHANNEL_TRPC_CONFIG;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+    cmd->size    = S_DS_GEN + 2U * sizeof(t_u16) +
+                txpwrlimit->num_chans * (sizeof(MrvlIEtypesHeader_t) + sizeof(MrvlChannelDesc_t)) +
+                (txpwrlimit->num_chans * txpwrlimit->txpwrlimit_config->num_mod_grps * sizeof(MrvlChanTrpcEntry_t));
+
+    HostCmd_DS_CHAN_TRPC_CONFIG *txpwrlimit_config = (HostCmd_DS_CHAN_TRPC_CONFIG *)(void *)((uint8_t *)cmd + S_DS_GEN);
+
+    txpwrlimit_config->action   = HostCmd_ACT_GEN_SET;
+    txpwrlimit_config->reserved = txpwrlimit->subband;
+
+    pByte = (t_u8 *)txpwrlimit_config->tlv_buffer;
+
+    for (i = 0; i < txpwrlimit->num_chans; i++)
+    {
+        trpc_tlv              = (MrvlIETypes_ChanTRPCConfig_t *)(void *)pByte;
+        trpc_tlv->header.type = TLV_TYPE_CHANNEL_TRPC_CONFIG;
+        trpc_tlv->header.len =
+            sizeof(MrvlChannelDesc_t) + txpwrlimit->txpwrlimit_config->num_mod_grps * sizeof(MrvlChanTrpcEntry_t);
+        trpc_tlv->start_freq = txpwrlimit->txpwrlimit_config[i].chan_desc.start_freq;
+        trpc_tlv->width      = txpwrlimit->txpwrlimit_config[i].chan_desc.chan_width;
+        trpc_tlv->chan_num   = txpwrlimit->txpwrlimit_config[i].chan_desc.chan_num;
+        (void)memcpy((void *)trpc_tlv->mod_group, (const void *)txpwrlimit->txpwrlimit_config[i].txpwrlimit_entry,
+                     txpwrlimit->txpwrlimit_config->num_mod_grps * sizeof(MrvlChanTrpcEntry_t));
+        pByte += trpc_tlv->header.len + sizeof(trpc_tlv->header);
+    }
+    ret = wifi_wait_for_cmdresp(NULL);
+    return ret;
+}
+
+int wifi_get_txpwrlimit(wifi_SubBand_t subband, wifi_txpwrlimit_t *txpwrlimit)
+{
+    int ret;
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)wifi_get_command_lock();
+
+    cmd->command = HostCmd_CMD_CHANNEL_TRPC_CONFIG;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+    cmd->size    = S_DS_GEN + 2U * sizeof(t_u16);
+
+    HostCmd_DS_CHAN_TRPC_CONFIG *txpwrlimit_config = (HostCmd_DS_CHAN_TRPC_CONFIG *)(void *)((uint8_t *)cmd + S_DS_GEN);
+
+    txpwrlimit_config->action   = HostCmd_ACT_GEN_GET;
+    txpwrlimit_config->reserved = subband;
+
+    ret = wifi_wait_for_cmdresp(txpwrlimit);
+    return ret;
+}
+
+int wifi_set_rts(int rts, mlan_bss_type bss_type)
+{
+    mlan_ioctl_req req;
+    mlan_ds_snmp_mib *mib = NULL;
+    mlan_status ret       = MLAN_STATUS_FAILURE;
+    wifi_sta_list_t *sl   = NULL;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+    /* Allocate an IOCTL request buffer */
+#if !CONFIG_MEM_POOLS
+    mib = OSA_MemoryAllocate(sizeof(mlan_ds_snmp_mib));
+#else
+    mib = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+
+    if (mib == NULL)
+        return -WM_FAIL;
+
+    /* Fill request buffer */
+    mib->sub_command = MLAN_OID_SNMP_MIB_RTS_THRESHOLD;
+    req.pbuf         = (t_u8 *)mib;
+    req.buf_len      = sizeof(mlan_ds_snmp_mib);
+    req.req_id       = MLAN_IOCTL_SNMP_MIB;
+    req.action       = MLAN_ACT_SET;
+    req.bss_index    = bss_type;
+
+    if (req.action == MLAN_ACT_SET)
+    {
+        if (rts < MLAN_RTS_MIN_VALUE || rts > MLAN_RTS_MAX_VALUE)
+        {
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(mib);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+            return -WM_FAIL;
+        }
+        mib->param.rts_threshold = rts;
+    }
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        if (!is_uap_started())
+        {
+            wifi_e("uap isn't up\n\r");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(mib);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+            return -WM_FAIL;
+        }
+        wifi_uap_bss_sta_list(&sl);
+        if (!sl)
+        {
+            wifi_e("Failed to get sta list\n\r");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(mib);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+            return -WM_FAIL;
+        }
+        if (sl->count >= 1)
+            ret = wlan_ops_sta_ioctl(mlan_adap, &req);
+        else
+            wifi_e("uap required sta to connect before setting rts threshold\n\r");
+    }
+    else if (bss_type == MLAN_BSS_TYPE_STA)
+    {
+        if (is_sta_connected())
+            ret = wlan_ops_sta_ioctl(mlan_adap, &req);
+        else
+            wifi_e("sta connection required before setting rts threshold\n\r");
+    }
+
+    if (ret != MLAN_STATUS_SUCCESS && ret != MLAN_STATUS_PENDING)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(mib);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+        return -WM_FAIL;
+    }
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(mib);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WIFI_FRAG_THRESHOLD
+int wifi_set_frag(int frag, mlan_bss_type bss_type)
+{
+    mlan_ioctl_req req;
+    mlan_ds_snmp_mib *mib = NULL;
+    mlan_status ret       = MLAN_STATUS_FAILURE;
+    wifi_sta_list_t *sl   = NULL;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+    /* Allocate an IOCTL request buffer */
+#if !CONFIG_MEM_POOLS
+    mib = OSA_MemoryAllocate(sizeof(mlan_ds_snmp_mib));
+#else
+    mib = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+
+    if (mib == NULL)
+        return -WM_FAIL;
+
+    /* Fill request buffer */
+    mib->sub_command = MLAN_OID_SNMP_MIB_FRAG_THRESHOLD;
+    req.pbuf         = (t_u8 *)mib;
+    req.buf_len      = sizeof(mlan_ds_snmp_mib);
+    req.req_id       = MLAN_IOCTL_SNMP_MIB;
+    req.action       = MLAN_ACT_SET;
+    req.bss_index    = bss_type;
+
+    if (req.action == MLAN_ACT_SET)
+    {
+        if (frag < MLAN_FRAG_MIN_VALUE || frag > MLAN_FRAG_MAX_VALUE)
+        {
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(mib);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+            return -WM_FAIL;
+        }
+        mib->param.frag_threshold = frag;
+    }
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        if (!is_uap_started())
+        {
+            wifi_e("uap isn't up\n\r");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(mib);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+            return -WM_FAIL;
+        }
+        wifi_uap_bss_sta_list(&sl);
+        if (!sl)
+        {
+            wifi_e("Failed to get sta list\n\r");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(mib);
+#else
+            OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+            return -WM_FAIL;
+        }
+
+        if (sl->count >= 1)
+            ret = wlan_ops_sta_ioctl(mlan_adap, &req);
+        else
+            wifi_e("uap required sta to connect before setting fragment threshold\n\r");
+    }
+    else if (bss_type == MLAN_BSS_TYPE_STA)
+    {
+        if (is_sta_connected())
+            ret = wlan_ops_sta_ioctl(mlan_adap, &req);
+        else
+            wifi_e("sta connection required before setting fragment threshold\n\r");
+    }
+
+    if (ret != MLAN_STATUS_SUCCESS && ret != MLAN_STATUS_PENDING)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(mib);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+        return -WM_FAIL;
+    }
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(mib);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, mib);
+#endif
+    return WM_SUCCESS;
+}
+#endif
+
+void wifi_set_curr_bss_channel(uint8_t channel)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    pmpriv->curr_bss_params.bss_descriptor.channel = channel;
+}
+
+
+#if CONFIG_11K
+int wifi_host_11k_cfg(int enable_11k)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+#if !CONFIG_WPA_SUPP
+    IEEEtypes_RrmElement_t rrmCap;
+#endif
+    int ret = (int)MLAN_STATUS_SUCCESS;
+
+    if (enable_11k == (int)pmpriv->enable_host_11k)
+    {
+        return (int)MLAN_STATUS_SUCCESS;
+    }
+
+#if !CONFIG_WPA_SUPP
+    if (enable_11k == 1)
+    {
+        if (pmpriv->rrm_mgmt_bitmap_index != -1)
+        {
+            ret = wifi_clear_mgmt_ie(MLAN_BSS_TYPE_STA, MGMT_RRM_ENABLED_CAP, pmpriv->rrm_mgmt_bitmap_index);
+
+            pmpriv->rrm_mgmt_bitmap_index = -1;
+        }
+        rrmCap.element_id = (t_u8)MGMT_RRM_ENABLED_CAP;
+        rrmCap.len        = (t_u8)sizeof(IEEEtypes_RrmEnabledCapabilities_t);
+        wlan_dot11k_formatRrmCapabilities(&(rrmCap.RrmEnabledCapabilities), 100);
+
+        /* Append the passed data to the end of
+         * the genIeBuffer */
+        __memcpy(pmpriv->adapter, pmpriv->assoc_req_buf, &rrmCap, sizeof(IEEEtypes_RrmElement_t));
+
+        /* Increment the stored buffer length by
+         * the size passed */
+        pmpriv->assoc_req_size = sizeof(IEEEtypes_RrmElement_t);
+    }
+    else
+    {
+        pmpriv->assoc_req_size = 0;
+    }
+#endif
+
+    pmpriv->enable_host_11k = (t_u8)enable_11k;
+
+    return ret;
+}
+
+int wifi_host_11k_neighbor_req(const char *ssid)
+{
+    if (wlan_strlen((t_s8 *)ssid) > IEEEtypes_SSID_SIZE)
+    {
+        return -WM_FAIL;
+    }
+    else
+    {
+        return wlan_send_mgmt_rm_neighbor_request(mlan_adap->priv[0], (t_u8 *)ssid, (t_u8)wlan_strlen((t_s8 *)ssid));
+    }
+}
+#endif
+
+#if CONFIG_11V
+int wifi_host_11v_bss_trans_query(t_u8 query_reason)
+{
+    return wlan_send_mgmt_bss_trans_query(mlan_adap->priv[0], query_reason);
+}
+#endif
+
+#if CONFIG_DRIVER_MBO
+int wifi_host_mbo_cfg(int enable_mbo)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    IEEEtypes_VendorSpecific_t mboie;
+    int ret = (int)MLAN_STATUS_SUCCESS;
+    t_u8 *pos;
+    int meas_vend_hdr_len = 0;
+
+    if ((t_u8)enable_mbo == pmpriv->enable_mbo)
+    {
+        /* Do nothing */
+        return (int)MLAN_STATUS_SUCCESS;
+    }
+
+    if (enable_mbo != 0)
+    {
+        mboie.vend_hdr.element_id = (IEEEtypes_ElementId_e)MGMT_MBO_IE;
+        pos                       = mboie.vend_hdr.oui;
+        pos                       = wlan_add_mbo_oui(pos);
+        pos                       = wlan_add_mbo_oui_type(pos);
+        pos                       = wlan_add_mbo_cellular_cap(pos);
+        meas_vend_hdr_len         = pos - mboie.vend_hdr.oui;
+        mboie.vend_hdr.len        = (t_u8)meas_vend_hdr_len;
+        pmpriv->mbo_mgmt_bitmap_index =
+            wifi_set_mgmt_ie(MLAN_BSS_TYPE_STA, MGMT_MBO_IE, (void *)&(mboie.vend_hdr.oui), mboie.vend_hdr.len);
+    }
+    else
+    {
+        ret = wifi_clear_mgmt_ie(MLAN_BSS_TYPE_STA, MGMT_MBO_IE, pmpriv->mbo_mgmt_bitmap_index);
+    }
+    pmpriv->enable_mbo = (t_u8)enable_mbo;
+
+    return ret;
+}
+
+int wifi_mbo_preferch_cfg(t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    IEEEtypes_VendorSpecific_t mboie;
+    int ret = (int)MLAN_STATUS_SUCCESS;
+    t_u8 *pos;
+    int meas_vend_hdr_len = 0;
+
+    if (0U == pmpriv->enable_mbo)
+    {
+        wifi_e("Please enable MBO first!");
+        return (int)MLAN_STATUS_FAILURE;
+    }
+
+    if (pmpriv->enable_mbo != 0U)
+    {
+        /* remove MBO OCE IE in case there is already a MBO OCE IE. */
+        ret                       = wifi_clear_mgmt_ie(MLAN_BSS_TYPE_STA, MGMT_MBO_IE, pmpriv->mbo_mgmt_bitmap_index);
+        mboie.vend_hdr.element_id = (IEEEtypes_ElementId_e)MGMT_MBO_IE;
+        pos                       = mboie.vend_hdr.oui;
+        pos                       = wlan_add_mbo_oui(pos);
+        pos                       = wlan_add_mbo_oui_type(pos);
+        pos                       = wlan_add_mbo_cellular_cap(pos);
+        pos                       = wlan_add_mbo_prefer_ch(pos, ch0, pefer0, ch1, pefer1);
+        meas_vend_hdr_len         = pos - mboie.vend_hdr.oui;
+        mboie.vend_hdr.len        = (t_u8)meas_vend_hdr_len;
+        pmpriv->mbo_mgmt_bitmap_index =
+            wifi_set_mgmt_ie(MLAN_BSS_TYPE_STA, MGMT_MBO_IE, (void *)&(mboie.vend_hdr.oui), mboie.vend_hdr.len);
+    }
+
+    return ret;
+}
+
+int wifi_mbo_send_preferch_wnm(t_u8 *src_addr, t_u8 *target_bssid, t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    int ret              = MLAN_STATUS_SUCCESS;
+    t_u8 *buf, *pos, *pos_len1, *pos_len2;
+    t_u8 global_oper_class_0 = 0, global_oper_class_1 = 0, num = 0, i;
+
+    if (0 == pmpriv->enable_mbo)
+    {
+        wifi_e("Please enable MBO first!\r\n");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    if (pmpriv->enable_mbo)
+    {
+#if !CONFIG_MEM_POOLS
+        buf = OSA_MemoryAllocate(sizeof(IEEEtypes_VendorSpecific_t));
+#else
+        buf = OSA_MemoryPoolAllocate(buf_512_MemoryPool);
+#endif
+        pos = buf;
+
+        /* No non-preferred channels */
+        if (!ch0 && !pefer0 && !ch1 && !pefer1)
+        {
+            *pos = MGMT_MBO_IE;
+            pos++;
+            *pos = 4;
+            pos++;
+            pos = wlan_add_mbo_oui(pos);
+            pos = wlan_add_mbo_attr_id(pos);
+        }
+        else
+        {
+            wlan_get_curr_oper_class(pmpriv, ch0, BW_20MHZ, &global_oper_class_0);
+            wlan_get_curr_oper_class(pmpriv, ch1, BW_20MHZ, &global_oper_class_1);
+            if (global_oper_class_0 != global_oper_class_1 || pefer0 != pefer1)
+                num = 2;
+            else
+                num = 1;
+
+            for (i = 0; i < num; i++)
+            {
+                *pos = MGMT_MBO_IE;
+                pos++;
+                if (i == 0)
+                    pos_len1 = pos;
+                else
+                    pos_len2 = pos;
+                pos++;
+                pos = wlan_add_mbo_oui(pos);
+                pos = wlan_add_mbo_attr_id(pos);
+                if (num == 1)
+                {
+                    pos[0] = global_oper_class_0;
+                    pos[1] = ch0;
+                    pos[2] = ch1;
+                    pos[3] = pefer0;
+                    pos += 4;
+                }
+                else
+                {
+                    if (i == 0)
+                    {
+                        pos[0] = global_oper_class_0;
+                        pos[1] = ch0;
+                        pos[2] = pefer0;
+                    }
+                    else
+                    {
+                        pos[0] = global_oper_class_1;
+                        pos[1] = ch1;
+                        pos[2] = pefer1;
+                    }
+                    pos += 3;
+                }
+
+                /* Reason code */
+                *pos = 0;
+                pos++;
+
+                if (i == 0)
+                    *pos_len1 = pos - (pos_len1 + 1);
+                else
+                    *pos_len2 = pos - (pos_len2 + 1);
+            }
+        }
+        wlan_send_mgmt_wnm_notification(src_addr, target_bssid, target_bssid, buf, pos - buf, false);
+    }
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(buf);
+#else
+    OSA_MemoryPoolFree(buf_512_MemoryPool, buf);
+#endif
+
+    return ret;
+}
+#endif
+
+#ifdef OTP_CHANINFO
+int wifi_get_fw_region_and_cfp_tables(void)
+{
+    int ret;
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)wifi_get_command_lock();
+
+    cmd->command = HostCmd_CMD_CHAN_REGION_CFG;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+    cmd->size    = S_DS_GEN + sizeof(HostCmd_DS_CHAN_REGION_CFG);
+
+    HostCmd_DS_CHAN_REGION_CFG *chan_region_cfg = (HostCmd_DS_CHAN_REGION_CFG *)(void *)((uint8_t *)cmd + S_DS_GEN);
+
+    chan_region_cfg->action = HostCmd_ACT_GEN_GET;
+
+    ret = wifi_wait_for_cmdresp(NULL);
+    return ret;
+}
+
+void wifi_free_fw_region_and_cfp_tables(void)
+{
+    mlan_adapter *pmadapter = mlan_adap->priv[0]->adapter;
+    wlan_free_fw_cfp_tables(pmadapter);
+}
+#endif
+
+int wifi_set_ed_mac_mode(wifi_ed_mac_ctrl_t *wifi_ed_mac_ctrl, int bss_type)
+{
+    int ret;
+
+    if (wifi_ed_mac_ctrl == MNULL)
+    {
+        return -WM_FAIL;
+    }
+
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[bss_type];
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)wifi_get_command_lock();
+
+    cmd->command = HostCmd_CMD_ED_MAC_MODE;
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+    cmd->result  = 0x0;
+    cmd->size    = S_DS_GEN + sizeof(HostCmd_CONFIG_ED_MAC_MODE);
+
+    HostCmd_CONFIG_ED_MAC_MODE *ed_mac_mode = (HostCmd_CONFIG_ED_MAC_MODE *)(void *)((uint8_t *)cmd + S_DS_GEN);
+
+    ed_mac_mode->ed_ctrl_2g   = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_ctrl_2g);
+    ed_mac_mode->ed_offset_2g = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_offset_2g);
+#if CONFIG_5GHz_SUPPORT
+    ed_mac_mode->ed_ctrl_5g   = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_ctrl_5g);
+    ed_mac_mode->ed_offset_5g = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_offset_5g);
+#if defined(SD9177)
+    ed_mac_mode->ed_bitmap_txq_lock = 0x1e00ff;
+#else
+    ed_mac_mode->ed_bitmap_txq_lock = 0xff;
+#endif
+#endif
+
+    pmpriv->ed_mac_mode.ed_ctrl_2g   = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_ctrl_2g);
+    pmpriv->ed_mac_mode.ed_offset_2g = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_offset_2g);
+#if CONFIG_5GHz_SUPPORT
+    pmpriv->ed_mac_mode.ed_ctrl_5g   = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_ctrl_5g);
+    pmpriv->ed_mac_mode.ed_offset_5g = wlan_cpu_to_le16(wifi_ed_mac_ctrl->ed_offset_5g);
+#endif
+
+    ret = wifi_wait_for_cmdresp(NULL);
+    return ret;
+}
+
+int wifi_get_ed_mac_mode(wifi_ed_mac_ctrl_t *wifi_ed_mac_ctrl, int bss_type)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[bss_type];
+
+    if (wifi_ed_mac_ctrl == MNULL)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memset(wifi_ed_mac_ctrl, 0x00, sizeof(wifi_ed_mac_ctrl_t));
+
+    wifi_ed_mac_ctrl->ed_ctrl_2g   = wlan_cpu_to_le16(pmpriv->ed_mac_mode.ed_ctrl_2g);
+    wifi_ed_mac_ctrl->ed_offset_2g = wlan_cpu_to_le16(pmpriv->ed_mac_mode.ed_offset_2g);
+#if CONFIG_5GHz_SUPPORT
+    wifi_ed_mac_ctrl->ed_ctrl_5g   = wlan_cpu_to_le16(pmpriv->ed_mac_mode.ed_ctrl_5g);
+    wifi_ed_mac_ctrl->ed_offset_5g = wlan_cpu_to_le16(pmpriv->ed_mac_mode.ed_offset_5g);
+#endif
+
+    return WM_SUCCESS;
+}
+
+#ifndef IEEEtypes_SSID_SIZE
+#define IEEEtypes_SSID_SIZE 32
+#endif /* IEEEtypes_SSID_SIZE */
+#define MRVL_SSID_TLV_ID          0x0000
+#define MRVL_BEACON_PERIOD_TLV_ID (PROPRIETARY_TLV_BASE_ID + 0x2cU)
+#define TLV_TYPE_SMCADDRRANGE     (PROPRIETARY_TLV_BASE_ID + 0xccU)
+#define TLV_TYPE_SMCFRAMEFILTER   (PROPRIETARY_TLV_BASE_ID + 0xd1U)
+
+int wifi_set_smart_mode_cfg(char *ssid,
+                            int beacon_period,
+                            wifi_chan_list_param_set_t *chan_list,
+                            uint8_t *smc_start_addr,
+                            uint8_t *smc_end_addr,
+                            uint16_t filter_type,
+                            int smc_frame_filter_len,
+                            uint8_t *smc_frame_filter,
+                            int custom_ie_len,
+                            uint8_t *custom_ie)
+{
+    unsigned int ssid_len                              = 0, i;
+    uint32_t size                                      = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+    MrvlIEtypes_SsIdParamSet_t *tlv_ssid               = NULL;
+    MrvlIEtypes_beacon_period_t *tlv_beacon_period     = NULL;
+    MrvlIEtypes_ChanListParamSet_t *tlv_chan_list      = NULL;
+    MrvlIEtypes_Data_t *tlv_custom_ie                  = NULL;
+    MrvlIETypes_SmcAddrRange_t *tlv_smc_addr_range     = NULL;
+    MrvlIETypes_SmcFrameFilter_t *tlv_smc_frame_filter = NULL;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_SMART_MODE_CFG);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    sys_config_cmd->action                = HostCmd_ACT_GEN_SET;
+    uint8_t *tlv                          = (uint8_t *)sys_config_cmd->tlv_buffer;
+
+    ssid_len = strlen(ssid);
+    if (ssid_len > IEEEtypes_SSID_SIZE || custom_ie_len > 255)
+    {
+        return -WM_E_INVAL;
+    };
+
+    tlv_ssid              = (MrvlIEtypes_SsIdParamSet_t *)(void *)sys_config_cmd->tlv_buffer;
+    tlv_ssid->header.type = MRVL_SSID_TLV_ID;
+    tlv_ssid->header.len  = strlen(ssid);
+    (void)memcpy((void *)tlv_ssid->ssid, (const void *)ssid, strlen(ssid));
+    size += sizeof(tlv_ssid->header) + tlv_ssid->header.len;
+    tlv += sizeof(tlv_ssid->header) + tlv_ssid->header.len;
+    tlv_beacon_period                = (MrvlIEtypes_beacon_period_t *)(void *)tlv;
+    tlv_beacon_period->header.type   = MRVL_BEACON_PERIOD_TLV_ID;
+    tlv_beacon_period->header.len    = sizeof(uint16_t);
+    tlv_beacon_period->beacon_period = beacon_period;
+
+    size += sizeof(tlv_beacon_period->header) + tlv_beacon_period->header.len;
+    tlv += sizeof(tlv_beacon_period->header) + tlv_beacon_period->header.len;
+
+    tlv_chan_list              = (MrvlIEtypes_ChanListParamSet_t *)(void *)tlv;
+    tlv_chan_list->header.type = TLV_TYPE_CHANLIST;
+    tlv_chan_list->header.len  = chan_list->no_of_channels * sizeof(ChanScanParamSet_t);
+
+    for (i = 0; i < chan_list->no_of_channels; i++)
+    {
+        tlv_chan_list->chan_scan_param[i].chan_number   = chan_list->chan_scan_param[i].chan_number;
+        tlv_chan_list->chan_scan_param[i].min_scan_time = chan_list->chan_scan_param[i].min_scan_time;
+        tlv_chan_list->chan_scan_param[i].max_scan_time = chan_list->chan_scan_param[i].max_scan_time;
+    }
+
+    size += sizeof(tlv_chan_list->header) + tlv_chan_list->header.len;
+    tlv += sizeof(tlv_chan_list->header) + tlv_chan_list->header.len;
+
+    if (custom_ie != MNULL && custom_ie_len > 0)
+    {
+        tlv_custom_ie              = (MrvlIEtypes_Data_t *)(void *)tlv;
+        tlv_custom_ie->header.type = TLV_TYPE_PASSTHROUGH;
+        tlv_custom_ie->header.len  = custom_ie_len;
+        (void)memcpy((void *)tlv_custom_ie->data, (const void *)custom_ie, custom_ie_len);
+
+        size += sizeof(tlv_custom_ie->header) + tlv_custom_ie->header.len;
+        tlv += sizeof(tlv_custom_ie->header) + tlv_custom_ie->header.len;
+    }
+
+    if (smc_start_addr != MNULL && smc_end_addr != MNULL)
+    {
+        tlv_smc_addr_range              = (MrvlIETypes_SmcAddrRange_t *)(void *)tlv;
+        tlv_smc_addr_range->header.type = TLV_TYPE_SMCADDRRANGE;
+        tlv_smc_addr_range->header.len  = 2U * MLAN_MAC_ADDR_LENGTH + sizeof(uint16_t);
+
+        (void)memcpy((void *)tlv_smc_addr_range->smcstartAddr, (const void *)smc_start_addr, MLAN_MAC_ADDR_LENGTH);
+        (void)memcpy((void *)tlv_smc_addr_range->smcendAddr, (const void *)smc_end_addr, MLAN_MAC_ADDR_LENGTH);
+
+        tlv_smc_addr_range->filter_type = filter_type;
+
+        size += sizeof(tlv_smc_addr_range->header) + tlv_smc_addr_range->header.len;
+        tlv += sizeof(tlv_smc_addr_range->header) + tlv_smc_addr_range->header.len;
+    }
+
+    tlv_smc_frame_filter              = (MrvlIETypes_SmcFrameFilter_t *)(void *)tlv;
+    tlv_smc_frame_filter->header.type = TLV_TYPE_SMCFRAMEFILTER;
+    tlv_smc_frame_filter->header.len  = smc_frame_filter_len;
+    (void)memcpy((void *)tlv_smc_frame_filter->frame_filter, (const void *)smc_frame_filter, smc_frame_filter_len);
+
+    size += sizeof(tlv_smc_frame_filter->header) + tlv_smc_frame_filter->header.len;
+    tlv += sizeof(tlv_smc_frame_filter->header) + tlv_smc_frame_filter->header.len;
+
+    cmd->size    = size;
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    return WM_SUCCESS;
+}
+
+int wifi_get_smart_mode_cfg(void)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_SMART_MODE_CFG);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    sys_config_cmd->action                = HostCmd_ACT_GEN_GET;
+
+    cmd->size    = size;
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(NULL);
+    return WM_SUCCESS;
+}
+
+int wifi_start_smart_mode(void)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_SMART_MODE_CFG);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    sys_config_cmd->action                = HostCmd_ACT_GEN_START;
+
+    cmd->size    = size;
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(NULL);
+    return WM_SUCCESS;
+}
+
+int wifi_stop_smart_mode(void)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_SMART_MODE_CFG);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    sys_config_cmd->action                = HostCmd_ACT_GEN_STOP;
+
+    cmd->size    = size;
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    return WM_SUCCESS;
+}
+
+void wifi_get_band(mlan_private *pmpriv, int *band)
+{
+    int support_band = 0;
+
+    if (pmpriv->config_bands & (BAND_B | BAND_G | BAND_GN))
+        support_band |= WIFI_FREQUENCY_BAND_2GHZ;
+#if CONFIG_5GHz_SUPPORT
+    if (pmpriv->config_bands & (BAND_A | BAND_AN))
+        support_band |= WIFI_FREQUENCY_BAND_5GHZ;
+#endif
+    *band = support_band;
+    if (support_band == WIFI_FREQUENCY_ALL_BAND)
+        *band = WIFI_FREQUENCY_BAND_AUTO;
+}
+
+int wifi_get_bgscan_results(mlan_private *pmpriv)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    int ret                 = 0;
+#if CONFIG_WPA_SUPP
+    BSSDescriptor_t *bss_entry = NULL;
+    int i;
+#endif
+
+    ENTER();
+
+#if CONFIG_WPA_SUPP
+    pmadapter->wpa_supp_scan_triggered = MTRUE;
+    for (i = 0; i < pmadapter->num_in_scan_table; i++)
+    {
+        bss_entry = &pmadapter->pscan_table[i];
+        if (bss_entry && bss_entry->ies != NULL)
+        {
+            OSA_MemoryFree(bss_entry->ies);
+        }
+    }
+#endif
+
+    memset(pmadapter->pscan_table, 0x00, sizeof(BSSDescriptor_t) * MRVDRV_MAX_BSSID_LIST);
+    pmadapter->num_in_scan_table = 0;
+    ret                          = wifi_request_bgscan_query(pmpriv);
+    pmadapter->bgscan_reported   = MFALSE;
+    LEAVE();
+    return ret;
+}
+
+int wifi_send_scan_query(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    int ret              = 0;
+
+    ENTER();
+    ret = wifi_get_bgscan_results(pmpriv);
+    if (ret)
+    {
+        PRINTM(MERROR, "Failed to get scan results\n");
+        goto done;
+    }
+done:
+    /* config rssi low threshold again */
+    pmpriv->rssi_low = DEFAULT_RSSI_LOW_THRESHOLD;
+    LEAVE();
+    return ret;
+}
+
+int wifi_send_hostcmd(
+    const void *cmd_buf, uint32_t cmd_buf_len, void *resp_buf, uint32_t resp_buf_len, uint32_t *reqd_resp_len)
+{
+    uint32_t ret = WM_SUCCESS;
+    /* Store IN & OUT params to be used by driver to update internaally*/
+    /* These variables are updated from reponse handlers */
+    wm_wifi.hostcmd_cfg.resp_buf      = resp_buf;
+    wm_wifi.hostcmd_cfg.resp_buf_len  = resp_buf_len;
+    wm_wifi.hostcmd_cfg.reqd_resp_len = reqd_resp_len;
+
+    /* Check if command is larger than the command size that can be handled by firmware */
+    if (cmd_buf_len > WIFI_FW_CMDBUF_SIZE)
+    {
+        *reqd_resp_len = 0;
+        return WM_E_INBIG;
+    }
+    else if (cmd_buf_len < WIFI_HOST_CMD_FIXED_HEADER_LEN)
+    /* Check if command is smaller than the minimum command size needed, which is WIFI_HOST_CMD_FIXED_HEADER_LEN */
+    {
+        *reqd_resp_len = 0;
+        return WM_E_INSMALL;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+    (void)wifi_get_command_lock();
+    /* Copy command buffer to driver command buffer */
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memcpy((void *)cmd, (const void *)cmd_buf, cmd_buf_len);
+
+    /* Set global variable to say that this command is from user invocation */
+    wm_wifi.hostcmd_cfg.is_hostcmd = true;
+    (void)wifi_wait_for_cmdresp(&wm_wifi.hostcmd_cfg);
+
+    if (*reqd_resp_len > resp_buf_len)
+    {
+        ret = WM_E_OUTBIG;
+    }
+    /*Response fail check not checked here, as thats caller's responsibility */
+    return ret;
+}
+
+#if CONFIG_WIFI_EU_CRYPTO
+int wifi_set_eu_crypto(EU_Crypto *Crypto_Data, enum _crypto_algorithm Algorithm, t_u16 EncDec)
+{
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    t_u16 cmd_size;
+    t_u16 *DataLength = Crypto_Data->DataLength;
+
+    wifi_get_command_lock();
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->command = HostCmd_CMD_EU_CRYPTO;
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, MLAN_BSS_ROLE_STA);
+
+    switch (Algorithm)
+    {
+        case CRYPTO_RC4:
+        case CRYPTO_AES_ECB:
+        case CRYPTO_AES_WRAP:
+        {
+            cmd_size                        = sizeof(HostCmd_DS_EU_CRYPTO) - 1 + 8 /*cmd header */;
+            cmd->params.eu_crypto.Algorithm = Algorithm;
+            cmd->params.eu_crypto.KeyLength = Crypto_Data->KeyLength;
+            memcpy(cmd->params.eu_crypto.Key, Crypto_Data->Key, Crypto_Data->KeyLength);
+            cmd->params.eu_crypto.KeyIVLength = Crypto_Data->KeyIVLength;
+            memcpy(cmd->params.eu_crypto.KeyIV, Crypto_Data->KeyIV, Crypto_Data->KeyIVLength);
+            cmd->params.eu_crypto.DataLength = *DataLength;
+            memcpy(cmd->params.eu_crypto.Data, Crypto_Data->Data, *DataLength);
+            cmd_size += cmd->params.eu_crypto.DataLength;
+            cmd->params.eu_crypto.EncDec   = EncDec;
+            cmd->params.eu_crypto.DataType = 0x0111;
+            break;
+        }
+        case CRYPTO_AES_CCMP:
+        case CRYPTO_AES_GCMP:
+        {
+            cmd_size                            = sizeof(HostCmd_DS_EU_AES_CRYPTO) - 1 + 8 /* cmd header */;
+            cmd->params.eu_aes_crypto.Algorithm = Algorithm;
+            cmd->params.eu_aes_crypto.KeyLength = Crypto_Data->KeyLength;
+            memcpy(cmd->params.eu_aes_crypto.Key, Crypto_Data->Key, Crypto_Data->KeyLength);
+            cmd->params.eu_aes_crypto.NonceLength = Crypto_Data->NonceLength;
+            memcpy(cmd->params.eu_aes_crypto.Nonce, Crypto_Data->Nonce, Crypto_Data->NonceLength);
+            cmd->params.eu_aes_crypto.AADLength = Crypto_Data->AADLength;
+            memcpy(cmd->params.eu_aes_crypto.AAD, Crypto_Data->AAD, Crypto_Data->AADLength);
+            cmd->params.eu_aes_crypto.DataLength = *DataLength;
+            memcpy(cmd->params.eu_aes_crypto.Data, Crypto_Data->Data, *DataLength);
+            cmd_size += cmd->params.eu_aes_crypto.DataLength;
+            cmd->params.eu_aes_crypto.EncDec   = EncDec;
+            cmd->params.eu_aes_crypto.DataType = 0x0111;
+            break;
+        }
+        default:
+            return -WM_FAIL;
+    }
+    cmd->size = cmd_size;
+
+    return wifi_wait_for_cmdresp(Crypto_Data);
+}
+#endif
+
+int wifi_set_rx_mgmt_indication(unsigned int bss_type, unsigned int mgmt_subtype_mask)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[bss_type];
+
+    mlan_ds_rx_mgmt_indication rx_mgmt_indication;
+
+    memset(&rx_mgmt_indication, 0x00, sizeof(mlan_ds_rx_mgmt_indication));
+
+    rx_mgmt_indication.mgmt_subtype_mask = mgmt_subtype_mask;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command = HostCmd_CMD_RX_MGMT_IND;
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, bss_type);
+    cmd->result = 0x0;
+
+    wlan_cmd_rx_mgmt_indication(pmpriv, cmd, HostCmd_ACT_GEN_SET, &rx_mgmt_indication);
+
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_set_bandcfg(wifi_bandcfg_t *bandcfg, mlan_act_ioctl action)
+{
+    mlan_ioctl_req req;
+    mlan_ds_radio_cfg radio_cfg;
+
+    if ((action != MLAN_ACT_GET) && (action != MLAN_ACT_SET))
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    (void)memset(&radio_cfg, 0x00, sizeof(mlan_ds_radio_cfg));
+    radio_cfg.sub_command = MLAN_OID_BAND_CFG;
+
+    req.pbuf      = (t_u8 *)&radio_cfg;
+    req.buf_len   = sizeof(mlan_ds_radio_cfg);
+    req.bss_index = 0;
+    req.req_id    = MLAN_IOCTL_RADIO_CFG;
+    req.action    = action;
+    if (action == MLAN_ACT_SET)
+    {
+        radio_cfg.param.band_cfg.config_bands = bandcfg->config_bands;
+    }
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    if (action == MLAN_ACT_GET)
+    {
+        bandcfg->config_bands = radio_cfg.param.band_cfg.config_bands;
+        bandcfg->fw_bands = radio_cfg.param.band_cfg.fw_bands;
+    }
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPS2
+/* enable/disable WPS session */
+int wifi_send_wps_cfg_cmd(int option)
+{
+    mlan_ioctl_req req;
+    mlan_ds_wps_cfg pwps;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    (void)memset(&pwps, 0x00, sizeof(mlan_ds_wps_cfg));
+    pwps.sub_command = MLAN_OID_WPS_CFG_SESSION;
+    if (option)
+        pwps.param.wps_session = MLAN_WPS_CFG_SESSION_START;
+    else
+        pwps.param.wps_session = MLAN_WPS_CFG_SESSION_END;
+    req.pbuf      = (t_u8 *)&pwps;
+    req.buf_len   = sizeof(mlan_ds_wps_cfg);
+    req.bss_index = 0;
+    req.req_id    = MLAN_IOCTL_WPS_CFG;
+    req.action    = MLAN_ACT_SET;
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+#endif /* CONFIG_WPS2 */
+
+wlan_mgmt_pkt *wifi_PrepDefaultMgtMsg(t_u8 sub_type,
+                                      mlan_802_11_mac_addr *DestAddr,
+                                      mlan_802_11_mac_addr *SrcAddr,
+                                      mlan_802_11_mac_addr *Bssid,
+                                      t_u16 pkt_len)
+{
+    wlan_mgmt_pkt *pmgmt_pkt_hdr    = MNULL;
+    IEEEtypes_FrameCtl_t *mgmt_fc_p = MNULL;
+    t_u8 *pBuf                      = MNULL;
+
+#if !CONFIG_MEM_POOLS
+    pBuf = OSA_MemoryAllocate(pkt_len);
+#else
+    pBuf         = OSA_MemoryPoolAllocate(buf_1536_MemoryPool);
+#endif
+
+    if (pBuf == MNULL)
+    {
+        return MNULL;
+    }
+
+    pmgmt_pkt_hdr = (wlan_mgmt_pkt *)(void *)pBuf;
+    /* 802.11 header */
+    mgmt_fc_p           = (IEEEtypes_FrameCtl_t *)(void *)&pmgmt_pkt_hdr->wlan_header.frm_ctl;
+    mgmt_fc_p->sub_type = sub_type;
+    mgmt_fc_p->type     = (t_u8)IEEE_TYPE_MANAGEMENT;
+    (void)memcpy(pmgmt_pkt_hdr->wlan_header.addr1, DestAddr, MLAN_MAC_ADDR_LENGTH);
+    (void)memcpy(pmgmt_pkt_hdr->wlan_header.addr2, SrcAddr, MLAN_MAC_ADDR_LENGTH);
+    (void)memcpy(pmgmt_pkt_hdr->wlan_header.addr3, Bssid, MLAN_MAC_ADDR_LENGTH);
+
+    return pmgmt_pkt_hdr;
+}
+
+#if CONFIG_ECSA
+wifi_ecsa_status_control ecsa_status_control = {false, 0};
+
+void set_ecsa_block_tx_time(t_u8 switch_count)
+{
+    ecsa_status_control.block_time = switch_count;
+}
+
+t_u8 get_ecsa_block_tx_time()
+{
+    return ecsa_status_control.block_time;
+}
+
+void set_ecsa_block_tx_flag(bool block_tx)
+{
+    ecsa_status_control.required = block_tx;
+}
+
+bool get_ecsa_block_tx_flag()
+{
+    return ecsa_status_control.required;
+}
+
+void wifi_put_ecsa_sem()
+{
+    OSA_SemaphorePost((osa_semaphore_handle_t)ecsa_status_control.ecsa_sem);
+}
+
+int wlan_get_nonglobal_operclass_by_bw_channel(t_u8 bandwidth, t_u8 channel, t_u8 *oper_class)
+{
+    int ret = 0;
+    mlan_ioctl_req req;
+    mlan_ds_misc_cfg *misc = NULL;
+    mlan_status status     = MLAN_STATUS_SUCCESS;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+#if !CONFIG_MEM_POOLS
+    misc = OSA_MemoryAllocate(sizeof(mlan_ds_misc_cfg));
+#else
+    misc = OSA_MemoryPoolAllocate(buf_3072_MemoryPool);
+#endif
+
+    if (misc == NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    req.bss_index                      = MLAN_BSS_ROLE_UAP;
+    req.pbuf                           = (t_u8 *)misc;
+    misc->sub_command                  = MLAN_OID_MISC_OPER_CLASS;
+    req.req_id                         = MLAN_IOCTL_MISC_CFG;
+    req.action                         = MLAN_ACT_GET;
+    misc->param.bw_chan_oper.bandwidth = bandwidth;
+    misc->param.bw_chan_oper.channel   = channel;
+
+    status = wlan_ops_uap_ioctl(mlan_adap, &req);
+    if (status != MLAN_STATUS_SUCCESS)
+    {
+        wifi_e("Failed to get operclass");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(misc);
+#else
+        OSA_MemoryPoolFree(buf_3072_MemoryPool, misc);
+#endif
+        return -WM_FAIL;
+    }
+    *oper_class = misc->param.bw_chan_oper.oper_class;
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(misc);
+#else
+    OSA_MemoryPoolFree(buf_3072_MemoryPool, misc);
+#endif
+
+    return ret;
+}
+
+int wifi_set_ecsa_cfg(t_u8 block_tx, t_u8 oper_class, t_u8 channel, t_u8 switch_count, t_u8 band_width, t_u8 ecsa)
+{
+    IEEEtypes_ExtChanSwitchAnn_t *ext_chan_switch = NULL;
+    IEEEtypes_ChanSwitchAnn_t *chan_switch        = NULL;
+    custom_ie *pcust_chansw_ie                    = NULL;
+    t_u32 usr_dot_11n_dev_cap                     = 0;
+#if CONFIG_5GHz_SUPPORT
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    BSSDescriptor_t *pbss_desc;
+    pbss_desc = &pmpriv->curr_bss_params.bss_descriptor;
+#endif
+    t_u8 new_oper_class = oper_class;
+    t_u8 bw;
+    int ret = MLAN_STATUS_SUCCESS;
+#if (CONFIG_11AC)
+    t_u8 center_freq_idx                       = 0;
+    IEEEtypes_Header_t *pChanSwWrap_ie         = NULL;
+    IEEEtypes_WideBWChanSwitch_t *pbwchansw_ie = NULL;
+    IEEEtypes_VhtTpcEnvelope_t *pvhttpcEnv_ie  = NULL;
+#endif
+    uint8_t *buf               = NULL;
+    tlvbuf_custom_ie *tlv      = NULL;
+    unsigned int mgmt_ie_index = -1;
+    int total_len = sizeof(tlvbuf_custom_ie) + (sizeof(custom_ie) - MAX_IE_SIZE) + sizeof(IEEEtypes_ChanSwitchAnn_t) +
+                    sizeof(IEEEtypes_ExtChanSwitchAnn_t);
+#if (CONFIG_11AC)
+    total_len += sizeof(IEEEtypes_WideBWChanSwitch_t) + sizeof(IEEEtypes_VhtTpcEnvelope_t) + sizeof(IEEEtypes_Header_t);
+#endif
+    uint16_t buf_len = 0;
+
+#if !CONFIG_MEM_POOLS
+    buf = (uint8_t *)OSA_MemoryAllocate(total_len);
+#else
+    buf = OSA_MemoryPoolAllocate(buf_1024_MemoryPool);
+#endif
+    if (!buf)
+    {
+        wifi_e("ECSA allocate memory failed \r\n");
+        return -WM_FAIL;
+    }
+
+    (void)memset(buf, 0, total_len);
+    tlv       = (tlvbuf_custom_ie *)buf;
+    tlv->type = MRVL_MGMT_IE_LIST_TLV_ID;
+
+    ret = get_free_mgmt_ie_index(&mgmt_ie_index);
+    if (WM_SUCCESS != ret)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_1024_MemoryPool, buf);
+#endif
+        return -WM_FAIL;
+    }
+
+    pcust_chansw_ie                    = (custom_ie *)(tlv->ie_data);
+    pcust_chansw_ie->ie_index          = mgmt_ie_index;
+    pcust_chansw_ie->ie_length         = sizeof(IEEEtypes_ChanSwitchAnn_t);
+    pcust_chansw_ie->mgmt_subtype_mask = MGMT_MASK_BEACON | MGMT_MASK_PROBE_RESP; /*Add IE for
+                                                                 BEACON/probe resp*/
+    chan_switch                    = (IEEEtypes_ChanSwitchAnn_t *)pcust_chansw_ie->ie_buffer;
+    chan_switch->element_id        = CHANNEL_SWITCH_ANN;
+    chan_switch->len               = 3;
+    chan_switch->chan_switch_mode  = block_tx;
+    chan_switch->new_channel_num   = channel;
+    chan_switch->chan_switch_count = switch_count;
+    DBG_HEXDUMP(MCMD_D, "CSA IE", (t_u8 *)pcust_chansw_ie->ie_buffer, pcust_chansw_ie->ie_length);
+
+#if CONFIG_5GHz_SUPPORT
+    if (pbss_desc->bss_band & BAND_A)
+        usr_dot_11n_dev_cap = mlan_adap->usr_dot_11n_dev_cap_a;
+    else
+#endif
+        usr_dot_11n_dev_cap = mlan_adap->usr_dot_11n_dev_cap_bg;
+
+    if (!ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap))
+    {
+        band_width = 0;
+    }
+
+    switch (band_width)
+    {
+        case CHANNEL_BW_40MHZ_ABOVE:
+        case CHANNEL_BW_40MHZ_BELOW:
+            bw = 40;
+            break;
+#if (CONFIG_11AC)
+        case CHANNEL_BW_80MHZ:
+            bw = 80;
+            break;
+        case CHANNEL_BW_160MHZ:
+            bw = 160;
+            break;
+#endif
+        default:
+            bw = 20;
+            break;
+    }
+
+    if (!new_oper_class && ecsa)
+        wlan_get_nonglobal_operclass_by_bw_channel(bw, channel, &new_oper_class);
+
+    if (new_oper_class)
+    {
+        pcust_chansw_ie->ie_length += sizeof(IEEEtypes_ExtChanSwitchAnn_t);
+        ext_chan_switch =
+            (IEEEtypes_ExtChanSwitchAnn_t *)(pcust_chansw_ie->ie_buffer + sizeof(IEEEtypes_ChanSwitchAnn_t));
+        ext_chan_switch->element_id        = EXTEND_CHANNEL_SWITCH_ANN;
+        ext_chan_switch->len               = 4;
+        ext_chan_switch->chan_switch_mode  = block_tx;
+        ext_chan_switch->new_oper_class    = new_oper_class;
+        ext_chan_switch->new_channel_num   = channel;
+        ext_chan_switch->chan_switch_count = switch_count;
+        DBG_HEXDUMP(MCMD_D, "ECSA IE", (t_u8 *)(pcust_chansw_ie->ie_buffer + sizeof(IEEEtypes_ChanSwitchAnn_t)),
+                    pcust_chansw_ie->ie_length - sizeof(IEEEtypes_ChanSwitchAnn_t));
+    }
+
+#if (CONFIG_11AC)
+    /* bandwidth 40/80/160 should set channel switch wrapper ie for 11ac 5G
+     * channel*/
+    if (band_width && channel > 14)
+    {
+        pChanSwWrap_ie             = (IEEEtypes_Header_t *)(pcust_chansw_ie->ie_buffer + pcust_chansw_ie->ie_length);
+        pChanSwWrap_ie->element_id = EXT_POWER_CONSTR;
+        pChanSwWrap_ie->len        = sizeof(IEEEtypes_WideBWChanSwitch_t);
+
+        pbwchansw_ie = (IEEEtypes_WideBWChanSwitch_t *)((t_u8 *)pChanSwWrap_ie + sizeof(IEEEtypes_Header_t));
+        pbwchansw_ie->ieee_hdr.element_id = BW_CHANNEL_SWITCH;
+        pbwchansw_ie->ieee_hdr.len        = sizeof(IEEEtypes_WideBWChanSwitch_t) - sizeof(IEEEtypes_Header_t);
+
+        center_freq_idx = wlan_get_center_freq_idx((mlan_private *)mlan_adap->priv[1], BAND_AAC, channel, band_width);
+        if (band_width == CHANNEL_BW_40MHZ_ABOVE || band_width == CHANNEL_BW_40MHZ_BELOW)
+        {
+            pbwchansw_ie->new_channel_width        = 0;
+            pbwchansw_ie->new_channel_center_freq0 = center_freq_idx;
+        }
+        else if (band_width == CHANNEL_BW_80MHZ)
+        {
+            pbwchansw_ie->new_channel_width        = 1;
+            pbwchansw_ie->new_channel_center_freq0 = center_freq_idx - 4;
+            pbwchansw_ie->new_channel_center_freq1 = center_freq_idx + 4;
+        }
+        else if (band_width == CHANNEL_BW_160MHZ)
+        {
+            pbwchansw_ie->new_channel_width        = 2;
+            pbwchansw_ie->new_channel_center_freq0 = center_freq_idx - 8;
+            pbwchansw_ie->new_channel_center_freq1 = center_freq_idx + 8;
+        }
+        else
+            wifi_e("Invalid bandwidth.Support value 1/3/4/5 for 40+/40-/80/160MHZ\n");
+
+        /*prepare the VHT Transmit Power Envelope IE*/
+        pvhttpcEnv_ie = (IEEEtypes_VhtTpcEnvelope_t *)((t_u8 *)pChanSwWrap_ie + sizeof(IEEEtypes_Header_t) +
+                                                       sizeof(IEEEtypes_WideBWChanSwitch_t));
+        pvhttpcEnv_ie->ieee_hdr.element_id = VHT_TX_POWER_ENV;
+        pvhttpcEnv_ie->ieee_hdr.len        = sizeof(IEEEtypes_VhtTpcEnvelope_t) - sizeof(IEEEtypes_Header_t);
+        /* Local Max TX Power Count= 3,
+         * Local TX Power Unit Inter=EIP(0) */
+        pvhttpcEnv_ie->tpc_info                     = 3;
+        pvhttpcEnv_ie->local_max_tp_20mhz           = 0xff;
+        pvhttpcEnv_ie->local_max_tp_40mhz           = 0xff;
+        pvhttpcEnv_ie->local_max_tp_80mhz           = 0xff;
+        pvhttpcEnv_ie->local_max_tp_160mhz_80_80mhz = 0xff;
+        pChanSwWrap_ie->len += sizeof(IEEEtypes_VhtTpcEnvelope_t);
+        pcust_chansw_ie->ie_length += pChanSwWrap_ie->len + sizeof(IEEEtypes_Header_t);
+        DBG_HEXDUMP(MCMD_D, "Channel switch wrapper IE", (t_u8 *)pChanSwWrap_ie,
+                    pChanSwWrap_ie->len + sizeof(IEEEtypes_Header_t));
+    }
+#endif
+    tlv->length = sizeof(custom_ie) + pcust_chansw_ie->ie_length - MAX_IE_SIZE;
+
+    buf_len = pcust_chansw_ie->ie_length + sizeof(tlvbuf_custom_ie) + sizeof(custom_ie) - MAX_IE_SIZE;
+
+    ret = wrapper_wlan_cmd_mgmt_ie(MLAN_BSS_TYPE_UAP, buf, buf_len, HostCmd_ACT_GEN_SET);
+    if (ret != MLAN_STATUS_SUCCESS && ret != MLAN_STATUS_PENDING)
+    {
+        wifi_e("Failed to set ECSA IE");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_1024_MemoryPool, buf);
+#endif
+        return -WM_FAIL;
+    }
+    set_ie_index(mgmt_ie_index);
+
+    OSA_SemaphoreWait((osa_semaphore_handle_t)ecsa_status_control.ecsa_sem, (switch_count + 2) * wm_wifi.beacon_period);
+    set_ecsa_block_tx_flag(false);
+
+    if (!ie_index_is_set(mgmt_ie_index))
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_1024_MemoryPool, buf);
+#endif
+        return -WM_FAIL;
+    }
+
+    /*Clear ECSA ie*/
+    (void)memset(buf, 0, total_len);
+    tlv         = (tlvbuf_custom_ie *)buf;
+    tlv->type   = MRVL_MGMT_IE_LIST_TLV_ID;
+    tlv->length = sizeof(custom_ie) - MAX_IE_SIZE;
+
+    pcust_chansw_ie->mgmt_subtype_mask = MGMT_MASK_CLEAR;
+    pcust_chansw_ie->ie_length         = 0;
+    pcust_chansw_ie->ie_index          = mgmt_ie_index;
+    buf_len                            = sizeof(tlvbuf_custom_ie) + tlv->length;
+
+    ret = wrapper_wlan_cmd_mgmt_ie(MLAN_BSS_TYPE_UAP, buf, buf_len, HostCmd_ACT_GEN_SET);
+    if (ret != MLAN_STATUS_SUCCESS && ret != MLAN_STATUS_PENDING)
+    {
+        wifi_e("Failed to clear ECSA IE");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_1024_MemoryPool, buf);
+#endif
+        return -WM_FAIL;
+    }
+    clear_ie_index(mgmt_ie_index);
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(buf);
+#else
+    OSA_MemoryPoolFree(buf_1024_MemoryPool, buf);
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_action_ecsa_cfg(t_u8 block_tx, t_u8 oper_class, t_u8 channel, t_u8 switch_count)
+{
+    mlan_status ret  = MLAN_STATUS_SUCCESS;
+    mlan_ds_bss *bss = NULL;
+    mlan_ioctl_req req;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+#if !CONFIG_MEM_POOLS
+    bss = OSA_MemoryAllocate(sizeof(mlan_ds_bss));
+#else
+    bss = OSA_MemoryPoolAllocate(buf_1280_MemoryPool);
+#endif
+
+    if (bss == NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    req.bss_index                           = MLAN_BSS_ROLE_UAP;
+    req.pbuf                                = (t_u8 *)bss;
+    bss->sub_command                        = MLAN_OID_ACTION_CHAN_SWITCH;
+    req.req_id                              = MLAN_IOCTL_BSS;
+    req.action                              = MLAN_ACT_SET;
+    bss->param.chanswitch.chan_switch_mode  = block_tx;
+    bss->param.chanswitch.new_channel_num   = channel;
+    bss->param.chanswitch.chan_switch_count = switch_count;
+    bss->param.chanswitch.new_oper_class    = oper_class;
+
+    ret = wlan_ops_uap_ioctl(mlan_adap, &req);
+
+    if (ret != MLAN_STATUS_SUCCESS && ret != MLAN_STATUS_PENDING)
+    {
+        wifi_e("Failed to set ECSA IE");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(bss);
+#else
+        OSA_MemoryPoolFree(buf_1280_MemoryPool, bss);
+#endif
+        return -WM_FAIL;
+    }
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(bss);
+#else
+    OSA_MemoryPoolFree(buf_1280_MemoryPool, bss);
+#endif
+
+    return WM_SUCCESS;
+}
+
+#endif
+
+#define SUBTYPE_AUTH          11
+#define AUTH_REQUEST_BUF_SIZE 512
+
+#if CONFIG_WPA_SUPP
+
+#if CONFIG_11R
+bool wifi_same_ess_ft()
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    return pmpriv->auth_alg == MLAN_AUTH_MODE_FT ? true : false;
+}
+#endif
+
+int wifi_nxp_set_default_scan_ies(const u8 *ies, size_t ies_len)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    if (ies && ies_len < sizeof(pmpriv->default_scan_ies))
+    {
+        pmpriv->default_scan_ies_len = ies_len;
+        memcpy(pmpriv->default_scan_ies, ies, ies_len);
+    }
+
+    return WM_SUCCESS;
+}
+
+#define HEADER_SIZE 8
+// frmctl + durationid + addr1 + addr2 + addr3 + seqctl + addr4
+#define MGMT_HEADER_LEN (2 + 2 + 6 + 6 + 6 + 2 + 6)
+// 6   = auth_alg + auth_transaction +auth_status
+#define AUTH_BODY_LEN 6
+
+static int wlan_send_mgmt_auth_request(mlan_private *pmpriv,
+                                       const t_u8 channel,
+                                       const t_u8 auth_alg,
+                                       const t_u8 *auth_seq_num,
+                                       const t_u8 *status_code,
+                                       const t_u8 *dest,
+                                       const t_u8 *sae_data,
+                                       const t_u16 sae_data_len)
+{
+    mlan_adapter *pmadapter      = pmpriv->adapter;
+    t_u16 pkt_len                = 0;
+    mlan_802_11_mac_addr *da     = MNULL;
+    mlan_802_11_mac_addr *sa     = MNULL;
+    wlan_mgmt_pkt *pmgmt_pkt_hdr = MNULL;
+    t_u8 *pos                    = MNULL;
+    int meas_pkt_len             = 0;
+    t_u8 addr[]                  = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+
+    if (pmpriv->bss_index != (t_u8)MLAN_BSS_ROLE_STA)
+    {
+        wifi_d("invalid interface %d for sending auth request", pmpriv->bss_index);
+        return (int)MLAN_STATUS_FAILURE;
+    }
+
+    da = (mlan_802_11_mac_addr *)(void *)dest;
+    sa = (mlan_802_11_mac_addr *)(void *)(&pmpriv->curr_addr[0]);
+
+    if (pmadapter->cmd_tx_data == 1U)
+    {
+        (void)wifi_get_command_lock();
+        HostCmd_DS_COMMAND *cmd           = wifi_get_command_buffer();
+        mlan_ds_misc_tx_frame tx_frame    = {0};
+        wlan_802_11_header *pwlan_pkt_hdr = MNULL;
+        IEEEtypes_FrameCtl_t *mgmt_fc_p   = MNULL;
+        t_u8 *pBuf                        = &tx_frame.tx_buf[0];
+        t_u32 pkt_type, tx_control;
+
+        pkt_len = MGMT_HEADER_LEN + AUTH_BODY_LEN;
+
+        memset(cmd, 0x00, pkt_len);
+
+        pkt_type   = MRVL_PKT_TYPE_MGMT_FRAME;
+        tx_control = 0;
+
+        /* Add pkt_type and tx_control */
+        memcpy(pBuf, &pkt_type, sizeof(pkt_type));
+        memcpy(pBuf + sizeof(pkt_type), &tx_control, sizeof(tx_control));
+
+        pwlan_pkt_hdr = (wlan_802_11_header *)(void *)(pBuf + HEADER_SIZE + sizeof(pkt_len));
+        /* 802.11 header */
+        mgmt_fc_p           = (IEEEtypes_FrameCtl_t *)(void *)&pwlan_pkt_hdr->frm_ctl;
+        mgmt_fc_p->sub_type = SUBTYPE_AUTH;
+        mgmt_fc_p->type     = (t_u8)IEEE_TYPE_MANAGEMENT;
+        (void)memcpy(pwlan_pkt_hdr->addr1, da, MLAN_MAC_ADDR_LENGTH);
+        (void)memcpy(pwlan_pkt_hdr->addr2, sa, MLAN_MAC_ADDR_LENGTH);
+        (void)memcpy(pwlan_pkt_hdr->addr3, da, MLAN_MAC_ADDR_LENGTH);
+
+        (void)memcpy(pwlan_pkt_hdr->addr4, addr, MLAN_MAC_ADDR_LENGTH);
+
+        /* 802.11 management body */
+        pos    = (t_u8 *)pwlan_pkt_hdr + sizeof(wlan_802_11_header);
+        pos[0] = auth_alg;
+        pos[1] = 0;
+        pos[2] = auth_seq_num[0];
+        pos[3] = auth_seq_num[1];
+        pos[4] = status_code[0];
+        pos[5] = status_code[1];
+
+        pos += 6;
+
+        if ((sae_data != NULL) && (sae_data_len > 0))
+        {
+            memcpy(pos, sae_data, sae_data_len);
+            pos += sae_data_len;
+        }
+
+        meas_pkt_len = pos - (t_u8 *)pwlan_pkt_hdr;
+        pkt_len      = (t_u16)meas_pkt_len;
+
+        /*Add packet len*/
+        pkt_len = wlan_cpu_to_le16(pkt_len);
+        memcpy(pBuf + HEADER_SIZE, &pkt_len, sizeof(pkt_len));
+
+        tx_frame.bandcfg.chanBand = channel > 14 ? BAND_5GHZ : BAND_2GHZ;
+        tx_frame.channel          = channel;
+        tx_frame.data_len         = HEADER_SIZE + pkt_len + 2 * sizeof(pkt_len);
+        tx_frame.buf_type         = MLAN_BUF_TYPE_RAW_DATA;
+        tx_frame.priority         = 7;
+
+        cmd->seq_num = 0x0;
+        cmd->result  = 0x0;
+
+        mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_TX_FRAME,
+                                                  HostCmd_ACT_GEN_SET, 0, NULL, &tx_frame, cmd);
+        if (rv != MLAN_STATUS_SUCCESS)
+        {
+            return -WM_FAIL;
+        }
+
+        (void)wifi_wait_for_cmdresp(NULL);
+        return wm_wifi.cmd_resp_status;
+    }
+    else
+    {
+        pmgmt_pkt_hdr = wifi_PrepDefaultMgtMsg(SUBTYPE_AUTH, da, sa, da, sizeof(wlan_mgmt_pkt) + AUTH_REQUEST_BUF_SIZE);
+        if (pmgmt_pkt_hdr == MNULL)
+        {
+            wifi_e("No memory for auth request");
+            return (int)MLAN_STATUS_FAILURE;
+        }
+
+        (void)memcpy(pmgmt_pkt_hdr->wlan_header.addr4, addr, MLAN_MAC_ADDR_LENGTH);
+
+        /* 802.11 management body */
+        pos    = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+        pos[0] = auth_alg;
+        pos[1] = 0;
+        pos[2] = auth_seq_num[0];
+        pos[3] = auth_seq_num[1];
+        pos[4] = status_code[0];
+        pos[5] = status_code[1];
+
+        pos += 6;
+
+        if ((sae_data != NULL) && (sae_data_len > 0))
+        {
+            memcpy(pos, sae_data, sae_data_len);
+            pos += sae_data_len;
+        }
+
+        meas_pkt_len           = pos - (t_u8 *)pmgmt_pkt_hdr;
+        pkt_len                = (t_u16)meas_pkt_len;
+        pmgmt_pkt_hdr->frm_len = pkt_len - (t_u16)sizeof(pmgmt_pkt_hdr->frm_len);
+
+        (void)wifi_inject_frame(WLAN_BSS_TYPE_STA, (t_u8 *)pmgmt_pkt_hdr, pkt_len);
+
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+        OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+    }
+
+    return (int)MLAN_STATUS_SUCCESS;
+}
+
+int wifi_send_mgmt_auth_request(const t_u8 channel,
+                                const t_u8 auth_alg,
+                                const t_u8 *auth_seq_num,
+                                const t_u8 *status_code,
+                                const t_u8 *dest,
+                                const t_u8 *sae_data,
+                                const t_u16 sae_data_len)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    int ret;
+
+    if ((pmpriv->auth_alg != WLAN_AUTH_SAE) && (pmpriv->auth_flag & HOST_MLME_AUTH_PENDING))
+    {
+        wifi_d("pending auth on going");
+        return -WM_FAIL;
+    }
+
+#if CONFIG_11R
+    if (auth_alg == MLAN_AUTH_MODE_FT)
+    {
+        pmpriv->ft_roam = MTRUE;
+    }
+#endif
+
+    if (pmpriv->auth_flag == 0)
+    {
+        wifi_set_rx_mgmt_indication(MLAN_BSS_TYPE_STA, WIFI_MGMT_AUTH | WIFI_MGMT_DEAUTH | WIFI_MGMT_DIASSOC);
+
+        wifi_remain_on_channel(true, channel, 6000);
+    }
+
+    pmpriv->curr_bss_params.host_mlme = 1;
+    pmpriv->auth_flag                 = HOST_MLME_AUTH_PENDING;
+    pmpriv->auth_alg                  = wlan_cpu_to_le16(auth_alg);
+
+    ret =
+        wlan_send_mgmt_auth_request(pmpriv, channel, auth_alg, auth_seq_num, status_code, dest, sae_data, sae_data_len);
+
+    if (ret != WM_SUCCESS)
+    {
+        wifi_set_rx_mgmt_indication(MLAN_BSS_TYPE_STA, 0);
+        wifi_remain_on_channel(false, 0, 0);
+
+        pmpriv->curr_bss_params.host_mlme = 0;
+        pmpriv->auth_flag                 = 0;
+        pmpriv->auth_alg                  = 0xFFFF;
+#if CONFIG_11R
+        pmpriv->ft_roam = MFALSE;
+#endif
+    }
+    return ret;
+}
+#endif
+
+#if CONFIG_WMM_UAPSD
+int wifi_set_wmm_qos_cfg(t_u8 qos_cfg)
+{
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+    mlan_ioctl_req req;
+    mlan_ds_wmm_cfg cfg;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    (void)memset(&cfg, 0x00, sizeof(mlan_ds_wmm_cfg));
+    cfg.sub_command   = MLAN_OID_WMM_CFG_QOS;
+    cfg.param.qos_cfg = qos_cfg;
+    req.pbuf          = (t_u8 *)&cfg;
+    req.buf_len       = sizeof(mlan_ds_wmm_cfg);
+    req.req_id        = MLAN_IOCTL_WMM_CFG;
+    req.action        = MLAN_ACT_SET;
+
+    ret = wlan_ops_sta_ioctl(mlan_adap, &req);
+    return ret;
+}
+
+void wifi_set_sleep_period(uint16_t sleep_period)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, MLAN_BSS_TYPE_STA);
+    cmd->result  = 0x0;
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_SLEEP_PERIOD, HostCmd_ACT_GEN_SET,
+                             0, NULL, &sleep_period, cmd);
+    wifi_wait_for_cmdresp(NULL);
+}
+#endif
+
+#if CONFIG_11AX
+#if CONFIG_MMSF
+int wifi_mmsf_cfg(const t_u16 action, t_u8 *enable, t_u8 *Density, t_u8 *MMSF)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_DBGS_CFG);
+    cmd->size    = S_DS_GEN;
+
+    HostCmd_DS_MMSF_CFG *MMSF_CFG = (HostCmd_DS_MMSF_CFG *)&cmd->params.mmsf_cfg;
+    MMSF_CFG->action              = wlan_cpu_to_le16(action);
+    MMSF_CFG->sub_id              = wlan_cpu_to_le16(MLAN_11AX_DEBUG_MMSF_SUBID);
+
+    (void)memcpy(&MMSF_CFG->enableMMSF, enable, sizeof(MMSF_CFG->enableMMSF));
+    (void)memcpy(&MMSF_CFG->ampduDensity, Density, sizeof(MMSF_CFG->ampduDensity));
+    (void)memcpy(&MMSF_CFG->ampduMMSF, MMSF, sizeof(MMSF_CFG->ampduMMSF));
+
+    cmd->size += sizeof(HostCmd_DS_MMSF_CFG);
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    if (action == ACTION_SET)
+    {
+        return wifi_wait_for_cmdresp(NULL);
+    }
+    else
+    {
+        wifi_mmsf_cfg_t mmsf_cfg_resp;
+        mmsf_cfg_resp.enable  = enable;
+        mmsf_cfg_resp.Density = Density;
+        mmsf_cfg_resp.MMSF    = MMSF;
+        return wifi_wait_for_cmdresp(&mmsf_cfg_resp);
+    }
+}
+#endif
+#endif
+
+#if CONFIG_WIFI_RECOVERY
+int wifi_recovery_test(void)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_DBGS_CFG);
+    cmd->size    = S_DS_GEN;
+    // HostCmd_DS_TMRC_CFG tmrc_cfg;
+
+    HostCmd_DS_TMRC_CFG *tmrc_cfg = (HostCmd_DS_TMRC_CFG *)&cmd->params.tmrc_cfg;
+    tmrc_cfg->action              = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
+    tmrc_cfg->sub_id              = wlan_cpu_to_le16(MLAN_RECOVERY_TEST_SUBID);
+
+    cmd->size += sizeof(HostCmd_DS_TMRC_CFG);
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+#endif
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+int wifi_tx_ampdu_prot_mode(tx_ampdu_prot_mode_para *prot_mode, t_u16 action)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x0;
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_TX_AMPDU_PROT_MODE, action, 0, NULL,
+                             prot_mode, cmd);
+
+    return wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? prot_mode : NULL);
+}
+#endif
+
+#if CONFIG_CSI
+int wifi_csi_cfg(wifi_csi_config_params_t *csi_params)
+{
+    t_u16 action = CSI_CMD_DISABLE;
+
+    action = csi_params->csi_enable;
+    if (action != CSI_CMD_ENABLE && action != CSI_CMD_DISABLE)
+        return -WM_FAIL;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    if (csi_params->bss_type == BSS_TYPE_UAP)
+        cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_UAP);
+    else
+        cmd->seq_num = 0x0;
+    cmd->result = 0x0;
+
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_CSI,
+                                              csi_params->csi_enable, 0, NULL, csi_params, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        wifi_put_command_lock();
+        return -WM_FAIL;
+    }
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+#endif
+
+#if (CONFIG_IPS)
+/* enable/disable config for IPS */
+int wifi_set_ips_config(mlan_bss_type interface, int option)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    t_u16 cmd_size;
+
+    if ((option != 0) && (option != 1))
+        return -WM_FAIL;
+
+    cmd_size = sizeof(HostCmd_DS_IPS_CONFIG) + S_DS_GEN /* cmd header */;
+    (void)memset(cmd, 0x00, cmd_size);
+    cmd->command = HostCmd_CMD_IPS_CONFIG;
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, interface);
+    cmd->size    = cmd_size;
+
+    cmd->params.ips_config.enable = option;
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+#endif
+
+#if CONFIG_NET_MONITOR
+int wifi_net_monitor_cfg(wifi_net_monitor_t *monitor)
+{
+    t_u16 action = HostCmd_ACT_GEN_SET;
+
+    action = monitor->action;
+
+    if (action != HostCmd_ACT_GEN_GET && action != HostCmd_ACT_GEN_SET)
+        return -WM_FAIL;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    mlan_status rv = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_NET_MONITOR,
+                                              monitor->action, 0, NULL, monitor, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+        return -WM_FAIL;
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+#endif
+
+#if CONFIG_TSP
+int wifi_tsp_cfg(const t_u16 action,
+                 t_u16 *enable,
+                 t_u32 *back_off,
+                 t_u32 *highThreshold,
+                 t_u32 *lowThreshold,
+                 t_u32 *dutycycstep,
+                 t_u32 *dutycycmin,
+                 int *highthrtemp,
+                 int *lowthrtemp,
+                 int *currCAUTemp,
+                 int *currRFUTemp)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    HostCmd_DS_TSP_CFG *tsp_cfg = &cmd->params.tsp_cfg;
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_TSP_CFG);
+    cmd->size    = sizeof(HostCmd_DS_TSP_CFG) + S_DS_GEN;
+
+    (void)memcpy(&tsp_cfg->thermalPowerMgmtenable, enable, sizeof(t_u16));
+    (void)memcpy(&tsp_cfg->powerMgmtBackoff, back_off, sizeof(t_u32));
+    (void)memcpy(&tsp_cfg->highPwrBOThrshld, highThreshold, sizeof(t_u32));
+    (void)memcpy(&tsp_cfg->lowPwrBOThrshld, lowThreshold, sizeof(t_u32));
+    (void)memcpy(&tsp_cfg->dutycycstep, dutycycstep, sizeof(t_u32));
+    (void)memcpy(&tsp_cfg->dutycycmin, dutycycmin, sizeof(t_u32));
+    (void)memcpy(&tsp_cfg->highthrtemp, highthrtemp, sizeof(t_s32));
+    (void)memcpy(&tsp_cfg->lowthrtemp, lowthrtemp, sizeof(t_s32));
+
+    tsp_cfg->action                 = wlan_cpu_to_le16(action);
+    tsp_cfg->thermalPowerMgmtenable = wlan_cpu_to_le16(tsp_cfg->thermalPowerMgmtenable);
+    tsp_cfg->powerMgmtBackoff       = wlan_cpu_to_le16(tsp_cfg->powerMgmtBackoff);
+    tsp_cfg->highPwrBOThrshld       = wlan_cpu_to_le16(tsp_cfg->highPwrBOThrshld);
+    tsp_cfg->lowPwrBOThrshld        = wlan_cpu_to_le16(tsp_cfg->lowPwrBOThrshld);
+    tsp_cfg->dutycycstep            = wlan_cpu_to_le16(tsp_cfg->dutycycstep);
+    tsp_cfg->dutycycmin             = wlan_cpu_to_le16(tsp_cfg->dutycycmin);
+    tsp_cfg->highthrtemp            = wlan_cpu_to_le16(tsp_cfg->highthrtemp);
+    tsp_cfg->lowthrtemp             = wlan_cpu_to_le16(tsp_cfg->lowthrtemp);
+
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    if (action == MLAN_ACT_SET)
+        return wifi_wait_for_cmdresp(NULL);
+    else
+    {
+        TSP_CFG tsp_get_cfg;
+        tsp_get_cfg.thermalPowerMgmtenable = enable;
+        tsp_get_cfg.powerMgmtBackoff       = back_off;
+        tsp_get_cfg.highPwrBOThrshld       = highThreshold;
+        tsp_get_cfg.lowPwrBOThrshld        = lowThreshold;
+        tsp_get_cfg.dutycycstep            = dutycycstep;
+        tsp_get_cfg.dutycycmin             = dutycycmin;
+        tsp_get_cfg.highthrtemp            = highthrtemp;
+        tsp_get_cfg.lowthrtemp             = lowthrtemp;
+        tsp_get_cfg.currCAUTemp            = currCAUTemp;
+        tsp_get_cfg.currRFUTemp            = currRFUTemp;
+
+        return wifi_wait_for_cmdresp(&tsp_get_cfg);
+    }
+}
+#endif
+
+#if CONFIG_TURBO_MODE
+int wifi_get_turbo_mode(t_u8 *mode)
+{
+    return wlan_get_set_turbo_mode(ACTION_GET, mode, MLAN_BSS_TYPE_STA);
+}
+
+int wifi_get_uap_turbo_mode(t_u8 *mode)
+{
+    return wlan_get_set_turbo_mode(ACTION_GET, mode, MLAN_BSS_TYPE_UAP);
+}
+
+int wifi_set_turbo_mode(t_u8 mode)
+{
+    return wlan_get_set_turbo_mode(ACTION_SET, &mode, MLAN_BSS_TYPE_STA);
+}
+
+int wifi_set_uap_turbo_mode(t_u8 mode)
+{
+    return wlan_get_set_turbo_mode(ACTION_SET, &mode, MLAN_BSS_TYPE_UAP);
+}
+
+int wlan_get_set_turbo_mode(t_u16 action, t_u8 *mode, mlan_bss_type bss_type)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SNMP_MIB);
+    cmd->size    = S_DS_GEN;
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+
+    uint8_t *tlv = (uint8_t *)((uint8_t *)cmd + S_DS_GEN);
+
+    turbo_mode_para *turbo_ptr = (turbo_mode_para *)tlv;
+    turbo_ptr->action          = action;
+    turbo_ptr->oid             = OID_WMM_TURBO_MODE;
+    turbo_ptr->size            = 0x1;
+    if (action == ACTION_SET)
+        (void)memcpy(&turbo_ptr->mode, mode, sizeof(t_u8));
+
+    cmd->size += sizeof(turbo_mode_para);
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    if (action == ACTION_GET)
+        return wifi_wait_for_cmdresp(mode);
+    else
+        return wifi_wait_for_cmdresp(NULL);
+}
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+int wifi_unassoc_ftm_cfg(const t_u16 action, const t_u16 config)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                       = wlan_cpu_to_le16(HostCmd_CMD_DOT11MC_UNASSOC_FTM_CFG);
+    cmd->size                          = S_DS_GEN + sizeof(HostCmd_DOT11MC_UNASSOC_FTM_CFG);
+    cmd->size                          = wlan_cpu_to_le16(cmd->size);
+    cmd->params.unassoc_ftm_cfg.action = wlan_cpu_to_le16(action);
+    cmd->params.unassoc_ftm_cfg.config = wlan_cpu_to_le16(config);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wifi_ftm_start_stop(const t_u16 action, const t_u8 loop_cnt, const t_u8 *mac, const t_u8 channel)
+{
+    if (action != FTM_ACTION_STOP)
+    {
+        ftm_param.channel = channel;
+        (void)memcpy(ftm_param.peer_mac, mac, MLAN_MAC_ADDR_LENGTH);
+        ftm_param.loop_cnt = loop_cnt;
+        ftm_param.status   = (ftm_param.loop_cnt == 0) ? 1 : 0;
+#if CONFIG_WLS_CSI_PROC
+        g_csi_event_for_wls = 1;
+#endif
+        return wifi_ftm_start(action, mac, channel);
+    }
+    else
+    {
+        ftm_param.loop_cnt = 0;
+        ftm_param.status   = 0;
+#if CONFIG_WLS_CSI_PROC
+        g_csi_event_for_wls = 0;
+#endif
+        return wifi_ftm_stop(FTM_ACTION_STOP, ftm_param.peer_mac, ftm_param.channel);
+    }
+}
+
+int wifi_ftm_start(const t_u16 action, const t_u8 *mac, const t_u8 channel)
+{
+    /*if (is_sta_connected() || is_sta_ipv4_connected()
+#if CONFIG_IPV6
+        || is_sta_ipv6_connected()
+#endif
+    )*/
+    {
+        wifi_get_command_lock();
+        HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+        cmd->command                             = wlan_cpu_to_le16(HostCmd_CMD_FTM_SESSION_CTRL);
+        cmd->size                                = S_DS_GEN + sizeof(HostCmd_FTM_SESSION_CTRL);
+        cmd->size                                = wlan_cpu_to_le16(cmd->size);
+        cmd->params.ftm_session_ctrl.action      = wlan_cpu_to_le16(action);
+        cmd->params.ftm_session_ctrl.for_ranging = wlan_cpu_to_le16(FOR_RANGING);
+        (void)memcpy(cmd->params.ftm_session_ctrl.peer_mac, mac, MLAN_MAC_ADDR_LENGTH);
+        cmd->params.ftm_session_ctrl.chan     = wlan_cpu_to_le16(channel);
+        cmd->params.ftm_session_ctrl.chanBand = (cmd->params.ftm_session_ctrl.chan < 32) ? 0 : 1;
+
+        return wifi_wait_for_cmdresp(NULL);
+    }
+    /*    else
+        {
+            PRINTF("Cannot Start FTM, STA not associated !\r\n");
+            return -WM_FAIL;
+        }*/
+}
+
+int wifi_ftm_stop(const t_u16 action, const t_u8 *mac, const t_u8 channel)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                             = wlan_cpu_to_le16(HostCmd_CMD_FTM_SESSION_CTRL);
+    cmd->size                                = S_DS_GEN + sizeof(HostCmd_FTM_SESSION_CTRL);
+    cmd->size                                = wlan_cpu_to_le16(cmd->size);
+    cmd->params.ftm_session_ctrl.action      = wlan_cpu_to_le16(action);
+    cmd->params.ftm_session_ctrl.for_ranging = wlan_cpu_to_le16(FOR_RANGING);
+    (void)memcpy(cmd->params.ftm_session_ctrl.peer_mac, mac, MLAN_MAC_ADDR_LENGTH);
+    cmd->params.ftm_session_ctrl.chan = wlan_cpu_to_le16(channel);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wifi_ftm_11mc_cfg(ftm_11mc_nego_cfg_t *ftm_11mc_nego_cfg)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                       = wlan_cpu_to_le16(HostCmd_CMD_FTM_SESSION_CFG);
+    cmd->size                          = wlan_cpu_to_le16(S_DS_GEN);
+    cmd->params.ftm_session_cfg.action = MLAN_ACT_SET;
+
+    wlan_dot11mc_ftm_cfg(cmd, ftm_11mc_nego_cfg);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wifi_ftm_location_cfg(location_cfg_info_t *ftm_location_cfg)
+{
+    wlan_location_ftm_cfg(ftm_location_cfg);
+}
+
+int wifi_ftm_civic_cfg(location_civic_rep_t *ftm_civic_cfg)
+{
+    wlan_civic_ftm_cfg(ftm_civic_cfg);
+}
+
+int wifi_ftm_cfg(const t_u8 protocol, ranging_11az_cfg_t *ftm_ranging_cfg)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                       = wlan_cpu_to_le16(HostCmd_CMD_FTM_SESSION_CFG);
+    cmd->size                          = wlan_cpu_to_le16(S_DS_GEN);
+    cmd->params.ftm_session_cfg.action = MLAN_ACT_SET;
+
+    HostCmd_FTM_SESSION_CFG ftm_session_cfg;
+    dot11az_ftm_cfg_t *cfg_11az                       = (dot11az_ftm_cfg_t *)&ftm_session_cfg.tlv.cfg_11az;
+    cfg_11az->range_tlv.val.format_bw                 = ftm_ranging_cfg->format_bw;
+    cfg_11az->range_tlv.val.max_i2r_sts_upto80        = ftm_ranging_cfg->max_i2r_sts_upto80;
+    cfg_11az->range_tlv.val.max_r2i_sts_upto80        = ftm_ranging_cfg->max_r2i_sts_upto80;
+    cfg_11az->range_tlv.val.az_measurement_freq       = ftm_ranging_cfg->az_measurement_freq;
+    cfg_11az->range_tlv.val.az_number_of_measurements = ftm_ranging_cfg->az_number_of_measurements;
+    cfg_11az->range_tlv.val.i2r_lmr_feedback          = ftm_ranging_cfg->i2r_lmr_feedback;
+    cfg_11az->range_tlv.val.civic_req                 = ftm_ranging_cfg->civic_req;
+    cfg_11az->range_tlv.val.lci_req                   = ftm_ranging_cfg->lci_req;
+    wlan_dto11az_ranging_cfg(cmd, protocol, &ftm_session_cfg);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wifi_process_wlc_ftm_event()
+{
+    int ret = -WM_FAIL;
+    if (ftm_param.loop_cnt > 0)
+        ftm_param.loop_cnt--;
+    if (ftm_param.loop_cnt > 0 || (ftm_param.status))
+        ret = wifi_ftm_start(FTM_ACTION_START, ftm_param.peer_mac, ftm_param.channel);
+    // else
+    //    ret = wifi_ftm_stop(FTM_ACTION_STOP, ftm_param.peer_mac, ftm_param.channel);
+
+    return ret;
+}
+
+#if CONFIG_WLS_CSI_PROC
+
+static int mlanwls_update_distance_to_gui(int distance, unsigned int tsf)
+{
+    int distance_m, distance_cm;
+    unsigned int time_ms = tsf / 1000;
+    float distance_flt   = 1.0f * distance / (1 << 8); // in meters
+    float distance_kalman;
+    OSA_TimeDelay(10);
+
+    if (range_input_str.time == 0)
+    {
+        range_kalman_init(&range_input_str, distance_flt, time_ms, RANGE_DRIVE_VAR, RANGE_MEASUREMENT_VAR,
+                          RANGE_RATE_INIT);
+        range_input_str.time = 1;
+    }
+    else
+    {
+        range_input_str.range_measurement = distance_flt;
+        range_input_str.time              = time_ms;
+        range_kalman(&range_input_str);
+    }
+    distance_kalman = range_input_str.last_range;
+
+    distance_cm = (int)(distance_kalman * 100);
+    distance_m  = distance_cm / 100;
+    distance_cm -= distance_m * 100;
+
+    wifi_d("Measured Distance: %f m; Kalman Distance: %f m [%d ms]\r\n", (double)distance_flt, (double)distance_kalman,
+           time_ms);
+
+    return 0;
+}
+
+static int send_csi_ack(unsigned int *resArray)
+{
+    int ret;
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    HostCmd_WLS_CSI_ACK *phostcmd = (HostCmd_WLS_CSI_ACK *)&cmd->params.wls_csi_ack;
+
+    cmd->command     = wlan_cpu_to_le16(HostCmd_CMD_DBGS_CFG);
+    cmd->size        = S_DS_GEN + sizeof(HostCmd_WLS_CSI_ACK) + 8;
+    phostcmd->action = 0;
+    phostcmd->sub_id = 0x333;
+    phostcmd->ack    = 1;
+
+    phostcmd->phase_roll       = resArray[0];
+    phostcmd->firstpath_delay  = resArray[1];
+    phostcmd->fft_size_pointer = resArray[2];
+    phostcmd->csi_tsf          = resArray[3];
+
+    cmd->size += CSI_TSF_LEN;
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    ret = wifi_wait_for_cmdresp(NULL);
+
+    return ret;
+}
+
+static void proc_csi_event(void *event, unsigned int *resArray)
+{
+    uint8_t *csiBuffer = (uint8_t *)(event);
+    hal_wls_packet_params_t packetparams;
+    hal_wls_processing_input_params_t inputVals;
+    unsigned int tsf = ((unsigned int *)csiBuffer)[3];
+    int distance     = ((unsigned int *)csiBuffer)[19];
+
+    if (distance >= 0)
+        mlanwls_update_distance_to_gui(distance, tsf);
+
+    inputVals.enableCsi              = 1;                  // turn on CSI processing
+    inputVals.enableAoA              = AOA_DEFAULT;        // turn on AoA (req. enableCsi==1)
+    inputVals.nTx                    = 3;                  // limit # tx streams to process
+    inputVals.nRx                    = 3;                  // limit # rx to process
+    inputVals.selCal                 = 0;                  // choose cal values
+    inputVals.dumpMul                = 0;                  // dump extra peaks in AoA
+    inputVals.enableAntCycling       = 0;                  // enable antenna cycling
+    inputVals.dumpRawAngle           = 0;                  // Dump Raw Angle
+    inputVals.useToaMin              = TOA_MIN_DEFAULT;    // 1: use min combining, 0: power combining;
+    inputVals.useSubspace            = SUBSPACE_DEFAULT;   // 1: use subspace algo; 0: no;
+    inputVals.useFindAngleDelayPeaks = ENABLE_DELAY_PEAKS; // use this algorithm for AoA
+
+    resArray[0] = 0xffffffff;
+    resArray[1] = 0xffffffff;
+    resArray[2] = 0xffffffff;
+    resArray[3] = 0xffffffff;
+
+    wls_process_csi((unsigned int *)csiBuffer, (unsigned int *)fftInBuffer_t, &packetparams, &inputVals, resArray);
+    // record TSF
+    resArray[3] = tsf;
+
+    wifi_d("EVENT: MLAN_CSI Processing results: %d | %d (%x), TSF[%x]\r\n", resArray[0], resArray[1], resArray[2], tsf);
+
+    return;
+}
+
+int wifi_process_wls_csi_event(void *p_data)
+{
+    int ret;
+
+    proc_csi_event(((t_u8 *)p_data + sizeof(csi_event_t)), csi_res_array);
+    // wifi_put_wls_csi_sem(); // After processing CSI raw data, release csi sem for next CSI event.
+    ret = send_csi_ack(csi_res_array);
+    return ret;
+}
+
+#endif
+
+#endif
+
+#if CONFIG_COEX_DUTY_CYCLE
+int wifi_single_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->command                               = wlan_cpu_to_le16(HostCmd_CMD_ROBUST_COEX);
+    cmd->size                                  = sizeof(HostCmd_SIGNLE_ANT_DUTY_CYCLE) + S_DS_GEN;
+    cmd->seq_num                               = 0x0;
+    cmd->result                                = 0x00;
+    cmd->params.single_ant_duty_cycle.action   = HostCmd_ACT_GEN_SET;
+    cmd->params.single_ant_duty_cycle.reserved = 0;
+    cmd->params.single_ant_duty_cycle.single_ant_cfg_data.header.type = TLV_TYPE_COEX_DUTY_CYCLE;
+
+    if (enable)
+    {
+        cmd->params.single_ant_duty_cycle.single_ant_cfg_data.header.len =
+            sizeof(MrvlIETypes_SingleAntDutyCycle_Config_t) - 4;
+        cmd->params.single_ant_duty_cycle.single_ant_cfg_data.enabled  = 0x0002;
+        cmd->params.single_ant_duty_cycle.single_ant_cfg_data.nbTime   = nbTime;
+        cmd->params.single_ant_duty_cycle.single_ant_cfg_data.wlanTime = wlanTime;
+    }
+    else
+    {
+        cmd->params.single_ant_duty_cycle.single_ant_cfg_data.header.len = sizeof(t_u16);
+        cmd->params.single_ant_duty_cycle.single_ant_cfg_data.enabled    = 0x0004;
+    }
+
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_dual_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime, t_u16 wlanBlockTime)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->command                                                  = wlan_cpu_to_le16(HostCmd_CMD_ROBUST_COEX);
+    cmd->size                                                     = sizeof(HostCmd_DUAL_ANT_DUTY_CYCLE) + S_DS_GEN;
+    cmd->seq_num                                                  = 0x0;
+    cmd->result                                                   = 0x00;
+    cmd->params.dual_ant_duty_cycle.action                        = HostCmd_ACT_GEN_SET;
+    cmd->params.dual_ant_duty_cycle.reserved                      = 0;
+    cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.header.type = TLV_TYPE_COEX_DUTY_CYCLE;
+
+    if (enable)
+    {
+        cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.header.len =
+            sizeof(MrvlIETypes_DualAntDutyCycle_Config_t) - 4;
+        cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.enabled       = 0x0002;
+        cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.nbTime        = nbTime;
+        cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.wlanTime      = wlanTime;
+        cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.wlanBlockTime = wlanBlockTime;
+    }
+    else
+    {
+        cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.header.len = sizeof(t_u16);
+        cmd->params.dual_ant_duty_cycle.dual_ant_cfg_data.enabled    = 0x0004;
+    }
+
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_EXTERNAL_COEX_PTA
+
+int wifi_external_coex_pta_cfg(ext_coex_pta_cfg coex_pta_config)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_ROBUST_COEX);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_EXTERNAL_COEX_PTA) + S_DS_GEN);
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x00;
+
+    HostCmd_EXTERNAL_COEX_PTA *external_coex_pta = (HostCmd_EXTERNAL_COEX_PTA *)&cmd->params.external_coex_pta;
+    external_coex_pta->action                    = wlan_cpu_to_le16(ACTION_SET);
+    external_coex_pta->reserved                  = 0x00;
+
+    MrvlIETypes_ExternalCoexPta_Config_t *coex_pta_cfg_data =
+        (MrvlIETypes_ExternalCoexPta_Config_t *)&external_coex_pta->coex_pta_cfg_data;
+
+    coex_pta_cfg_data->param.tlv_type = wlan_cpu_to_le16(TLV_TYPE_ROBUST_COEX);
+    coex_pta_cfg_data->param.tlv_length =
+        wlan_cpu_to_le16(sizeof(MrvlIETypes_ExternalCoexPta_Config_t) - sizeof(MrvlIETypes_Coex_params_t));
+
+    coex_pta_cfg_data->enabled                = wlan_cpu_to_le16(coex_pta_config.enabled);
+    coex_pta_cfg_data->ext_WifiBtArb          = wlan_cpu_to_le16(coex_pta_config.ext_WifiBtArb);
+    coex_pta_cfg_data->polGrantPin            = wlan_cpu_to_le16(coex_pta_config.polGrantPin);
+    coex_pta_cfg_data->enable_PriPtaInt       = wlan_cpu_to_le16(coex_pta_config.enable_PriPtaInt);
+    coex_pta_cfg_data->enable_StatusFromPta   = wlan_cpu_to_le16(coex_pta_config.enable_StatusFromPta);
+    coex_pta_cfg_data->setPriSampTiming       = wlan_cpu_to_le16(coex_pta_config.setPriSampTiming);
+    coex_pta_cfg_data->setStateInfoSampTiming = wlan_cpu_to_le16(coex_pta_config.setStateInfoSampTiming);
+    coex_pta_cfg_data->extRadioTrafficPrio    = wlan_cpu_to_le16(coex_pta_config.extRadioTrafficPrio);
+    coex_pta_cfg_data->extCoexHwIntWci2       = wlan_cpu_to_le16(coex_pta_config.extCoexHwIntWci2);
+
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_IMD3_CFG
+int wifi_imd3_cfg(t_u8 imd3_value)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_ROBUST_COEX);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_IMD3_CFG) + S_DS_GEN);
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x00;
+
+    HostCmd_IMD3_CFG *imd3_cfg = (HostCmd_IMD3_CFG *)&cmd->params.imd3_cfg;
+    imd3_cfg->action           = wlan_cpu_to_le16(ACTION_SET);
+    imd3_cfg->reserved         = 0x00;
+
+    MrvlIETypes_IMD_Config_t *imd_cfg = (MrvlIETypes_IMD_Config_t *)&imd3_cfg->imd_cfg;
+
+    imd_cfg->param.tlv_type   = wlan_cpu_to_le16(TLV_TYPE_IMD_VALIDATION);
+    imd_cfg->param.tlv_length = wlan_cpu_to_le16(sizeof(MrvlIETypes_IMD_Config_t) - sizeof(MrvlIETypes_Coex_params_t));
+
+    imd_cfg->rbc_mode    = 0x00;
+    imd_cfg->reserved    = wlan_cpu_to_le16(imd3_value);
+    imd_cfg->DynamicMode = 0x0000;
+
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_INACTIVITY_TIMEOUT_EXT
+int wifi_sta_inactivityto(wifi_inactivity_to_t *inac_to, t_u16 cmd_action)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    HostCmd_DS_INACTIVITY_TIMEOUT_EXT *inac_to_ext = (HostCmd_DS_INACTIVITY_TIMEOUT_EXT *)&cmd->params.inactivity_to;
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_INACTIVITY_TIMEOUT_EXT);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_INACTIVITY_TIMEOUT_EXT) + S_DS_GEN);
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x00;
+
+    inac_to_ext->action = wlan_cpu_to_le16(cmd_action);
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        inac_to_ext->timeout_unit     = wlan_cpu_to_le16((t_u16)inac_to->timeout_unit);
+        inac_to_ext->unicast_timeout  = wlan_cpu_to_le16((t_u16)inac_to->unicast_timeout);
+        inac_to_ext->mcast_timeout    = wlan_cpu_to_le16((t_u16)inac_to->mcast_timeout);
+        inac_to_ext->ps_entry_timeout = wlan_cpu_to_le16((t_u16)inac_to->ps_entry_timeout);
+        inac_to_ext->ps_cmd_timeout   = wlan_cpu_to_le16((t_u16)inac_to->ps_cmd_timeout);
+        wifi_wait_for_cmdresp(NULL);
+    }
+    else
+    {
+        wifi_wait_for_cmdresp(inac_to);
+    }
+
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_AUTO_NULL_TX
+int wifi_auto_null_tx(wifi_auto_null_tx_t *auto_null_tx, mlan_bss_type bss_type)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd         = wifi_get_command_buffer();
+    HostCmd_DS_AUTO_TX *auto_tx_cmd = (HostCmd_DS_AUTO_TX *)((t_u8 *)cmd + S_DS_GEN);
+
+    if (auto_null_tx == NULL)
+        return -WM_E_INVAL;
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num        = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+    cmd->command        = wlan_cpu_to_le16(HostCmd_CMD_AUTO_TX);
+    cmd->size           = S_DS_GEN + sizeof(HostCmd_DS_AUTO_TX);
+    auto_tx_cmd->action = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+
+    if (auto_null_tx->start)
+    {
+        MrvlIEtypes_Auto_Null_Tx_t *auto_null_tx_tlv =
+            (MrvlIEtypes_Auto_Null_Tx_t *)((t_u8 *)auto_tx_cmd + sizeof(auto_tx_cmd->action));
+        auto_null_tx_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_AUTO_TX);
+        auto_null_tx_tlv->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_Auto_Null_Tx_t) - sizeof(MrvlIEtypesHeader_t));
+        auto_null_tx_tlv->interval = auto_null_tx->interval;
+        auto_null_tx_tlv->priority = auto_null_tx->priority;
+        /* Packet index, set to 0 for auto null tx */
+        auto_null_tx_tlv->index = 0;
+        /* getTodToAForPkts, set to 0 for auto null tx */
+        auto_null_tx_tlv->getTodToAForPkts = 0;
+        auto_null_tx_tlv->frame_len        = sizeof(auto_null_tx_tlv->dest_mac_addr) +
+                                      sizeof(auto_null_tx_tlv->dest_mac_addr) +
+                                      sizeof(auto_null_tx_tlv->frame_body_len);
+
+        (void)memcpy((void *)auto_null_tx_tlv->dest_mac_addr, (const void *)auto_null_tx->dst_mac,
+                     MLAN_MAC_ADDR_LENGTH);
+        (void)memcpy((void *)auto_null_tx_tlv->src_mac_addr, (const void *)auto_null_tx->src_mac, MLAN_MAC_ADDR_LENGTH);
+        /* fram body length, '0x00,0x00' for auto null tx */
+        auto_null_tx_tlv->frame_body_len = 0;
+        cmd->size                        = cmd->size + sizeof(MrvlIEtypes_Auto_Null_Tx_t);
+        cmd->size                        = wlan_cpu_to_le16(cmd->size);
+    }
+
+    cmd->result = 0x00;
+
+    wifi_wait_for_cmdresp(NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_cfp.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_cfp.c
new file mode 100644
index 0000000000..1b085f2962
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_cfp.c
@@ -0,0 +1,2891 @@
+/** @file mlan_cfp.c
+ *
+ *  @brief  This file provides WLAN client mode channel, frequency and power related code
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*************************************************************
+Change Log:
+    04/16/2009: initial version
+************************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+    Local Variables
+********************************************************/
+
+/** 100mW */
+#define WLAN_TX_PWR_DEFAULT 20
+/** 100mW */
+#define WLAN_TX_PWR_US_DEFAULT 20
+/** 100mW */
+#define WLAN_TX_PWR_JP_BG_DEFAULT 20
+/** 200mW */
+#define WLAN_TX_PWR_JP_A_DEFAULT 23
+/** 100mW */
+#define WLAN_TX_PWR_FR_100MW 20
+/** 10mW */
+#define WLAN_TX_PWR_FR_10MW 10
+/** 100mW */
+#define WLAN_TX_PWR_EMEA_DEFAULT 20
+/** 200mW */
+#define WLAN_TX_PWR_200MW 23
+/** 2000mW */
+#define WLAN_TX_PWR_CN_2000MW 33
+#if defined(RW610)
+/** 22dBm */
+#define WLAN_TX_PWR_WW_DEFAULT 22
+#else
+/** 8dBm */
+#define WLAN_TX_PWR_WW_DEFAULT 8
+#endif
+/** Region code mapping */
+typedef struct _country_code_mapping
+{
+    /** Region */
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /** Code for B/G CFP table */
+    t_u8 cfp_code_bg;
+    /** Code for A CFP table */
+    t_u8 cfp_code_a;
+} country_code_mapping_t;
+
+static const country_code_mapping_t country_code_mapping[] = {
+    {"WW", 0x00, 0x00}, /* World Wide Safe */
+    {"US", 0x10, 0x10}, /* US FCC */
+    {"CA", 0x10, 0x20}, /* IC Canada */
+    {"SG", 0x10, 0x10}, /* Singapore */
+    {"EU", 0x30, 0x30}, /* ETSI */
+    {"AU", 0x30, 0x30}, /* Australia */
+    {"KR", 0x30, 0x30}, /* Republic Of Korea */
+    {"FR", 0x32, 0x32}, /* France */
+    {"JP", 0xFF, 0x40}, /* Japan */
+    {"CN", 0x30, 0x50}, /* China */
+};
+
+#define COUNTRY_ID_US 0
+#define COUNTRY_ID_JP 1
+#define COUNTRY_ID_CN 2
+#define COUNTRY_ID_EU 3
+
+typedef struct _oper_bw_chan
+{
+    /*non-global operating class*/
+    t_u8 oper_class;
+    /*global operating class*/
+    t_u8 global_oper_class;
+    /*bandwidth 0-20M 1-40M 2-80M 3-160M*/
+    t_u8 bandwidth;
+    /*channel list*/
+    t_u8 channel_list[13];
+} oper_bw_chan;
+
+/** oper class table for US*/
+static oper_bw_chan oper_bw_chan_us[] = {
+    /** non-Global oper class, global oper class, bandwidth, channel list*/
+    {1, 115, 0, {36, 40, 44, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {2, 118, 0, {52, 56, 60, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {3, 124, 0, {149, 153, 157, 161, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {4, 121, 0, {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 0}},
+    {5, 125, 0, {149, 153, 157, 161, 165, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {12, 81, 0, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0, 0}},
+    {22, 116, 1, {36, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {23, 119, 1, {52, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {24, 122, 1, {100, 108, 116, 124, 132, 140, 0, 0, 0, 0, 0, 0, 0}},
+    {25, 126, 1, {149, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {26, 126, 1, {149, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {27, 117, 1, {40, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {28, 120, 1, {56, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {29, 123, 1, {104, 112, 120, 128, 136, 144, 0, 0, 0, 0, 0, 0, 0}},
+    {30, 127, 1, {153, 161, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {31, 127, 1, {153, 161, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {32, 83, 1, {1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0}},
+    {33, 84, 1, {5, 6, 7, 8, 9, 10, 11, 0, 0, 0, 0, 0, 0}},
+#if CONFIG_11AC
+    {128, 128, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+    {129, 129, 3, {50, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {130, 130, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+#endif
+};
+
+/** oper class table for EU*/
+static oper_bw_chan oper_bw_chan_eu[] = {
+    /** non-global oper class,global oper class, bandwidth, channel list*/
+    {1, 115, 0, {36, 40, 44, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {2, 118, 0, {52, 56, 60, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {3, 121, 0, {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0, 0}},
+    {4, 81, 0, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}},
+    {5, 116, 1, {36, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {6, 119, 1, {52, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {7, 122, 1, {100, 108, 116, 124, 132, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {8, 117, 1, {40, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {9, 120, 1, {56, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {10, 123, 1, {104, 112, 120, 128, 136, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {11, 83, 1, {1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0}},
+    {12, 84, 1, {5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 0, 0, 0}},
+    {17, 125, 0, {149, 153, 157, 161, 165, 169, 0, 0, 0, 0, 0, 0, 0}},
+#if CONFIG_11AC
+    {128, 128, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+    {129, 129, 3, {50, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {130, 130, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+#endif
+};
+
+/** oper class table for Japan*/
+static oper_bw_chan oper_bw_chan_jp[] = {
+    /** non-Global oper class,global oper class, bandwidth, channel list*/
+    {1, 115, 0, {34, 38, 42, 46, 36, 40, 44, 48, 0, 0, 0, 0, 0}},
+    {30, 81, 0, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}},
+    {31, 82, 0, {14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {32, 118, 0, {52, 56, 60, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {33, 118, 0, {52, 56, 60, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {34, 121, 0, {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0, 0}},
+    {35, 121, 0, {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0, 0}},
+    {36, 116, 1, {36, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {37, 119, 1, {52, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {38, 119, 1, {52, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {39, 122, 1, {100, 108, 116, 124, 132, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {40, 122, 1, {100, 108, 116, 124, 132, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {41, 117, 1, {40, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {42, 120, 1, {56, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {43, 120, 1, {56, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {44, 123, 1, {104, 112, 120, 128, 136, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {45, 123, 1, {104, 112, 120, 128, 136, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {56, 83, 1, {1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0}},
+    {57, 84, 1, {5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 0, 0, 0}},
+    {58, 121, 0, {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0, 0}},
+#if CONFIG_11AC
+    {128, 128, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+    {129, 129, 3, {50, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {130, 130, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+#endif
+};
+
+/** oper class table for China*/
+static oper_bw_chan oper_bw_chan_cn[] = {
+    /** non-Global oper class,global oper class, bandwidth, channel list*/
+    {1, 115, 0, {36, 40, 44, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {2, 118, 0, {52, 56, 60, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {3, 125, 0, {149, 153, 157, 161, 165, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {4, 116, 1, {36, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {5, 119, 1, {52, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {6, 126, 1, {149, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {7, 81, 0, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}},
+    {8, 83, 0, {1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0}},
+    {9, 84, 1, {5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 0, 0, 0}},
+#if CONFIG_11AC
+    {128, 128, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+    {129, 129, 3, {50, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
+    {130, 130, 2, {42, 58, 106, 122, 138, 155, 0, 0, 0, 0, 0, 0, 0}},
+#endif
+};
+
+/** Country code for ETSI */
+static t_u8 eu_country_code_table[][COUNTRY_CODE_LEN] = {
+    "AL", "AD", "AT", "AU", "BY", "BE", "BA", "BG", "HR", "CY", "CZ", "DK", "EE", "FI", "FR", "MK",
+    "DE", "GR", "HU", "IS", "IE", "IT", "KR", "LV", "LI", "LT", "LU", "MT", "MD", "MC", "ME", "NL",
+    "NO", "PL", "RO", "RU", "SM", "RS", "SI", "SK", "ES", "SE", "CH", "TR", "UA", "UK", "GB", "NZ"};
+
+/**
+ * The structure for Channel-Frequency-Power table
+ */
+typedef struct _cfp_table
+{
+    /** Region or Code */
+    t_u8 code;
+    /** Frequency/Power */
+    const chan_freq_power_t *cfp;
+    /** No of CFP flag */
+    int cfp_no;
+} cfp_table_t;
+
+/* Format { Channel, Frequency (MHz), MaxTxPower } */
+/** Band: 'B/G', Region: USA FCC/Canada IC */
+static const chan_freq_power_t channel_freq_power_US_BG[] = {
+    {1, 2412, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {2, 2417, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {3, 2422, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {4, 2427, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {5, 2432, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {6, 2437, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {7, 2442, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {8, 2447, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {9, 2452, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {10, 2457, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {11, 2462, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}};
+
+/** Band: 'B/G', Region: Europe ETSI/China */
+static const chan_freq_power_t channel_freq_power_EU_BG[] = {
+    {1, 2412, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},  {2, 2417, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {3, 2422, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},  {4, 2427, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {5, 2432, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},  {6, 2437, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {7, 2442, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},  {8, 2447, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {9, 2452, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},  {10, 2457, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {11, 2462, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE}, {12, 2467, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {13, 2472, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE}};
+
+/** Band: 'B/G', Region: France */
+static const chan_freq_power_t channel_freq_power_FR_BG[] = {
+    {1, 2412, WLAN_TX_PWR_FR_100MW, (bool)MFALSE}, {2, 2417, WLAN_TX_PWR_FR_100MW, (bool)MFALSE},
+    {3, 2422, WLAN_TX_PWR_FR_100MW, (bool)MFALSE}, {4, 2427, WLAN_TX_PWR_FR_100MW, (bool)MFALSE},
+    {5, 2432, WLAN_TX_PWR_FR_100MW, (bool)MFALSE}, {6, 2437, WLAN_TX_PWR_FR_100MW, (bool)MFALSE},
+    {7, 2442, WLAN_TX_PWR_FR_100MW, (bool)MFALSE}, {8, 2447, WLAN_TX_PWR_FR_100MW, (bool)MFALSE},
+    {9, 2452, WLAN_TX_PWR_FR_100MW, (bool)MFALSE}, {10, 2457, WLAN_TX_PWR_FR_10MW, (bool)MFALSE},
+    {11, 2462, WLAN_TX_PWR_FR_10MW, (bool)MFALSE}, {12, 2467, WLAN_TX_PWR_FR_10MW, (bool)MFALSE},
+    {13, 2472, WLAN_TX_PWR_FR_10MW, (bool)MFALSE}};
+
+
+/** Band: 'B/G', Region: Japan */
+static const chan_freq_power_t channel_freq_power_JPN40_BG[] = {{14, 2484, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE}};
+
+
+/** Band : 'B/G', Region: Special */
+static const chan_freq_power_t channel_freq_power_SPECIAL_BG[] = {
+    {1, 2412, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},  {2, 2417, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},
+    {3, 2422, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},  {4, 2427, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},
+    {5, 2432, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},  {6, 2437, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},
+    {7, 2442, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},  {8, 2447, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},
+    {9, 2452, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},  {10, 2457, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},
+    {11, 2462, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE}, {12, 2467, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE},
+    {13, 2472, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE}, {14, 2484, WLAN_TX_PWR_JP_BG_DEFAULT, (bool)MFALSE}};
+
+/** Band : 'B/G', Region: World Wide Safe */
+static chan_freq_power_t channel_freq_power_WW_BG[] = {
+    {1, 2412, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},  {2, 2417, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {3, 2422, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},  {4, 2427, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {5, 2432, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},  {6, 2437, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {7, 2442, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},  {8, 2447, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {9, 2452, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},  {10, 2457, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {11, 2462, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {12, 2467, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {13, 2472, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE}};
+
+/** Band : 'B/G', Region: Custom - Place holder for Max 14 channels (As defined in WWSM)*/
+static chan_freq_power_t channel_freq_power_Custom_BG[] = {
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}};
+
+static uint8_t rf_radio_modes_group[] = {
+    0,  /* set the radio in power down mode */
+    /*1,   sets the radio in 5GHz band, 2X2 mode(path A+B) */
+    3,  /* sets the radio in 5GHz band, 1X1 mode(path A) */
+   /* 4,   sets the radio in 5GHz band, 1X1 mode(path B) */
+   /* 9,   sets the radio in 2.4GHz band, 2X2 mode(path A+B) */
+    11, /* sets the radio in 2.4GHz band, 1X1 mode(path A) */
+   /* 14, sets the radio in 2.4GHz band, 1X1 mode(path B)*/
+};
+
+/**
+ * The 2.4GHz CFP tables
+ */
+static cfp_table_t cfp_table_BG[] = {
+    {
+        0x00, /* World Wide Safe */
+        (chan_freq_power_t *)channel_freq_power_WW_BG,
+        (int)(sizeof(channel_freq_power_WW_BG) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x10, /* US FCC */
+        (const chan_freq_power_t *)channel_freq_power_US_BG,
+        (int)(sizeof(channel_freq_power_US_BG) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x20, /* CANADA IC */
+        (const chan_freq_power_t *)channel_freq_power_US_BG,
+        (int)(sizeof(channel_freq_power_US_BG) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x30, /* EU */
+        (const chan_freq_power_t *)channel_freq_power_EU_BG,
+        (int)(sizeof(channel_freq_power_EU_BG) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x32, /* FRANCE */
+        (const chan_freq_power_t *)channel_freq_power_FR_BG,
+        (int)(sizeof(channel_freq_power_FR_BG) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x40, /* JAPAN */
+        (const chan_freq_power_t *)channel_freq_power_JPN40_BG,
+        (int)(sizeof(channel_freq_power_JPN40_BG) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x50, /* China */
+        (const chan_freq_power_t *)channel_freq_power_EU_BG,
+        (int)(sizeof(channel_freq_power_EU_BG) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0xff, /* Special */
+        (const chan_freq_power_t *)channel_freq_power_SPECIAL_BG,
+        (int)(sizeof(channel_freq_power_SPECIAL_BG) / sizeof(chan_freq_power_t)),
+    },
+    /* Add new region here */
+};
+
+/** Number of the CFP tables for 2.4GHz */
+#define MLAN_CFP_TABLE_SIZE_BG (sizeof(cfp_table_BG) / sizeof(cfp_table_t))
+
+#if CONFIG_5GHz_SUPPORT
+/* Format { Channel, Frequency (MHz), MaxTxPower, DFS } */
+/** Band: 'A', Region: USA FCC, Spain, France */
+static const chan_freq_power_t channel_freq_power_A[] = {
+    {36, 5180, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},  {40, 5200, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {44, 5220, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},  {48, 5240, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {52, 5260, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},   {56, 5280, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {60, 5300, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},   {64, 5320, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {100, 5500, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {104, 5520, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {108, 5540, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {112, 5560, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {116, 5580, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {120, 5600, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {124, 5620, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {128, 5640, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {132, 5660, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {136, 5680, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {140, 5700, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {144, 5720, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {149, 5745, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {153, 5765, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {157, 5785, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {161, 5805, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {165, 5825, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+#if CONFIG_UNII4_BAND_SUPPORT
+    {169, 5845, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {173, 5865, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {177, 5885, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+#endif
+};
+
+/** Band: 'A', Region: Canada IC */
+static const chan_freq_power_t channel_freq_power_CAN_A[] = {
+    {36, 5180, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},  {40, 5200, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {44, 5220, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},  {48, 5240, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {52, 5260, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},   {56, 5280, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {60, 5300, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},   {64, 5320, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {100, 5500, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {104, 5520, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {108, 5540, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {112, 5560, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {116, 5580, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {132, 5660, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+    {136, 5680, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},  {140, 5700, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+#if CONFIG_11AC
+     {144, 5720, WLAN_TX_PWR_US_DEFAULT, (bool)MTRUE},
+#endif
+    {149, 5745, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {153, 5765, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {157, 5785, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}, {161, 5805, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE},
+    {165, 5825, WLAN_TX_PWR_US_DEFAULT, (bool)MFALSE}};
+
+/** Band: 'A', Region: Europe ETSI */
+static const chan_freq_power_t channel_freq_power_EU_A[] = {
+    {36, 5180, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE}, {40, 5200, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {44, 5220, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE}, {48, 5240, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {52, 5260, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},  {56, 5280, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},
+    {60, 5300, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},  {64, 5320, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},
+    {100, 5500, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE}, {104, 5520, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},
+    {108, 5540, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE}, {112, 5560, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},
+    {116, 5580, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE}, {120, 5600, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},
+    {124, 5620, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE}, {128, 5640, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},
+    {132, 5660, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE}, {136, 5680, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE},
+    {140, 5700, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MTRUE}, {149, 5745, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {153, 5765, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE}, {157, 5785, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE},
+    {161, 5805, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE}, {165, 5825, WLAN_TX_PWR_EMEA_DEFAULT, (bool)MFALSE}};
+
+/** Band: 'A', Region: Japan */
+static const chan_freq_power_t channel_freq_power_JPN_A[] = {
+    {36, 5180, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MFALSE}, {40, 5200, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MFALSE},
+    {44, 5220, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MFALSE}, {48, 5240, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MFALSE},
+    {52, 5260, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},  {56, 5280, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},
+    {60, 5300, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},  {64, 5320, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},
+    {100, 5500, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE}, {104, 5520, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},
+    {108, 5540, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE}, {112, 5560, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},
+    {116, 5580, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE}, {120, 5600, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},
+    {124, 5620, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE}, {128, 5640, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},
+    {132, 5660, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE}, {136, 5680, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE},
+    {140, 5700, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE}, {144, 5720, WLAN_TX_PWR_JP_A_DEFAULT, (bool)MTRUE}};
+
+/** Band: 'A', Region: China */
+static const chan_freq_power_t channel_freq_power_CN_A[] = {
+    {36, 5180, WLAN_TX_PWR_200MW, MFALSE}, {40, 5200, WLAN_TX_PWR_200MW, MFALSE},
+    {44, 5220, WLAN_TX_PWR_200MW, MFALSE}, {48, 5240, WLAN_TX_PWR_200MW, MFALSE},
+    {52, 5260, WLAN_TX_PWR_200MW, MTRUE},  {56, 5280, WLAN_TX_PWR_200MW, MTRUE},
+    {60, 5300, WLAN_TX_PWR_200MW, MTRUE},  {64, 5320, WLAN_TX_PWR_200MW, MTRUE},
+    {149, 5745, WLAN_TX_PWR_CN_2000MW, MFALSE}, {153, 5765, WLAN_TX_PWR_CN_2000MW, MFALSE},
+    {157, 5785, WLAN_TX_PWR_CN_2000MW, MFALSE}, {161, 5805, WLAN_TX_PWR_CN_2000MW, MFALSE},
+    {165, 5825, WLAN_TX_PWR_CN_2000MW, MFALSE}};
+
+
+/** Band: 'A', Region: World Wide Safe */
+static chan_freq_power_t channel_freq_power_WW_A[] = {
+    {36, 5180, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {40, 5200, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {44, 5220, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {48, 5240, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {52, 5260, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},  {56, 5280, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {60, 5300, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},  {64, 5320, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {100, 5500, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE}, {104, 5520, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {108, 5540, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE}, {112, 5560, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {116, 5580, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE}, {120, 5600, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {124, 5620, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE}, {128, 5640, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {132, 5660, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE}, {136, 5680, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {140, 5700, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE}, {144, 5720, WLAN_TX_PWR_WW_DEFAULT, (bool)MTRUE},
+    {149, 5745, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {153, 5765, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {157, 5785, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {161, 5805, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {165, 5825, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}};
+
+/** Band: 'A', Region: Custom - Place holder for Max 25 channels (As defined in WWSM) */
+static chan_freq_power_t channel_freq_power_Custom_A[] = {
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+#if CONFIG_UNII4_BAND_SUPPORT
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE}, {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+    {0, 0, WLAN_TX_PWR_WW_DEFAULT, (bool)MFALSE},
+#endif
+};
+
+
+/** Band: 'A', Code: 1, Low band (5150-5250 MHz) channels */
+static const chan_freq_power_t channel_freq_power_low_band[] = {
+    {36, 5180, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+    {40, 5200, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+    {44, 5220, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+    {48, 5240, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+};
+
+/** Band: 'A', Code: 2, Lower middle band (5250-5350 MHz) channels */
+static const chan_freq_power_t channel_freq_power_lower_middle_band[] = {
+    {52, 5260, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {56, 5280, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {60, 5300, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {64, 5320, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+};
+
+/** Band: 'A', Code: 3, Upper middle band (5470-5725 MHz) channels */
+static const chan_freq_power_t channel_freq_power_upper_middle_band[] = {
+    {100, 5500, WLAN_TX_PWR_DEFAULT, (bool)MTRUE}, {104, 5520, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {108, 5540, WLAN_TX_PWR_DEFAULT, (bool)MTRUE}, {112, 5560, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {116, 5580, WLAN_TX_PWR_DEFAULT, (bool)MTRUE}, {120, 5600, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {124, 5620, WLAN_TX_PWR_DEFAULT, (bool)MTRUE}, {128, 5640, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {132, 5660, WLAN_TX_PWR_DEFAULT, (bool)MTRUE}, {136, 5680, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+    {140, 5700, WLAN_TX_PWR_DEFAULT, (bool)MTRUE},
+};
+
+/** Band: 'A', Code: 4, High band (5725-5850 MHz) channels */
+static const chan_freq_power_t channel_freq_power_high_band[] = {{149, 5745, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+                                                                 {153, 5765, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+                                                                 {157, 5785, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+                                                                 {161, 5805, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+                                                                 {165, 5825, WLAN_TX_PWR_DEFAULT, (bool)MFALSE}};
+
+/** Band: 'A', Code: 5, Low band (5150-5250 MHz) and
+ * High band (5725-5850 MHz) channels */
+static const chan_freq_power_t channel_freq_power_low_high_band[] = {
+    {36, 5180, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},  {40, 5200, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+    {44, 5220, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},  {48, 5240, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+    {149, 5745, WLAN_TX_PWR_DEFAULT, (bool)MFALSE}, {153, 5765, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+    {157, 5785, WLAN_TX_PWR_DEFAULT, (bool)MFALSE}, {161, 5805, WLAN_TX_PWR_DEFAULT, (bool)MFALSE},
+    {165, 5825, WLAN_TX_PWR_DEFAULT, (bool)MFALSE}};
+
+/**
+ * The 5GHz CFP tables
+ */
+static cfp_table_t cfp_table_A[] = {
+    {
+        0x00, /* World Wide Safe*/
+        (chan_freq_power_t *)channel_freq_power_WW_A,
+        (int)(sizeof(channel_freq_power_WW_A) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x10, /* US FCC */
+        (const chan_freq_power_t *)channel_freq_power_A,
+        (int)(sizeof(channel_freq_power_A) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x20, /* CANADA IC */
+        (const chan_freq_power_t *)channel_freq_power_CAN_A,
+        (int)(sizeof(channel_freq_power_CAN_A) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x30, /* EU */
+        (const chan_freq_power_t *)channel_freq_power_EU_A,
+        (int)(sizeof(channel_freq_power_EU_A) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x32, /* FRANCE */
+        (const chan_freq_power_t *)channel_freq_power_A,
+        (int)(sizeof(channel_freq_power_A) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0x40, /* JAPAN */
+        (const chan_freq_power_t *)channel_freq_power_JPN_A,
+        (int)((int)(sizeof(channel_freq_power_JPN_A) / sizeof(chan_freq_power_t))),
+    },
+    {
+        0x50, /* China */
+        (const chan_freq_power_t *)channel_freq_power_CN_A,
+        (int)(sizeof(channel_freq_power_CN_A) / sizeof(chan_freq_power_t)),
+    },
+    {
+        0xff, /* Special */
+        (const chan_freq_power_t *)channel_freq_power_JPN_A,
+        (int)(sizeof(channel_freq_power_JPN_A) / sizeof(chan_freq_power_t)),
+    },
+    {0x1, /* Low band (5150-5250 MHz) channels */
+     (const chan_freq_power_t *)channel_freq_power_low_band,
+     (int)(sizeof(channel_freq_power_low_band) / sizeof(chan_freq_power_t))},
+    {0x2, /* Lower middle band (5250-5350 MHz) channels */
+     (const chan_freq_power_t *)channel_freq_power_lower_middle_band,
+     (int)(sizeof(channel_freq_power_lower_middle_band) / sizeof(chan_freq_power_t))},
+    {0x3, /* Upper middle band (5470-5725 MHz) channels */
+     (const chan_freq_power_t *)channel_freq_power_upper_middle_band,
+     (int)(sizeof(channel_freq_power_upper_middle_band) / sizeof(chan_freq_power_t))},
+    {0x4, /* High band (5725-5850 MHz) channels */
+     (const chan_freq_power_t *)channel_freq_power_high_band,
+     (int)(sizeof(channel_freq_power_high_band) / sizeof(chan_freq_power_t))},
+    {0x5, /* Low band (5150-5250 MHz) and High band (5725-5850 MHz) channels */
+     (const chan_freq_power_t *)channel_freq_power_low_high_band,
+     (int)(sizeof(channel_freq_power_low_high_band) / sizeof(chan_freq_power_t))},
+    /* Add new region here */
+};
+
+/** Number of the CFP tables for 5GHz */
+#define MLAN_CFP_TABLE_SIZE_A (sizeof(cfp_table_A) / sizeof(cfp_table_t))
+
+#endif /* CONFIG_5GHz_SUPPORT */
+
+/********************************************************
+    Global Variables
+********************************************************/
+/**
+ * The table to keep region code
+ */
+t_u16 region_code_index[MRVDRV_MAX_REGION_CODE] = {0x00, 0x10, 0x20, 0x30, 0x32, 0x40, 0x41, 0x50, 0xfe, 0xff};
+
+
+/** The table to keep CFP code for A */
+t_u16 cfp_code_index_a[MRVDRV_MAX_CFP_CODE_A] = {0x1, 0x2, 0x3, 0x4, 0x5};
+
+/**
+ * The rates supported for ad-hoc B mode
+ */
+t_u8 AdhocRates_B[B_SUPPORTED_RATES] = {0x82, 0x84, 0x8b, 0x96, 0};
+
+/**
+ * The rates supported for ad-hoc G mode
+ */
+t_u8 AdhocRates_G[G_SUPPORTED_RATES] = {0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c, 0};
+
+/**
+ * The rates supported for ad-hoc BG mode
+ */
+t_u8 AdhocRates_BG[BG_SUPPORTED_RATES] = {0x82, 0x84, 0x8b, 0x96, 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c, 0};
+
+/**
+ * The rates supported in A mode for ad-hoc
+ */
+t_u8 AdhocRates_A[A_SUPPORTED_RATES] = {0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c, 0};
+
+/**
+ * The rates supported in A mode (used for BAND_A)
+ */
+t_u8 SupportedRates_A[A_SUPPORTED_RATES] = {0x0c, 0x12, 0x18, 0x24, 0xb0, 0x48, 0x60, 0x6c, 0};
+
+/**
+ * The rates supported by the card
+ */
+static t_u16 WlanDataRates[WLAN_SUPPORTED_RATES_EXT] = {
+    0x02,  0x04, 0x0B, 0x16, 0x00, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6C, 0x90, 0x0D,
+    0x1A,  0x27, 0x34, 0x4E, 0x68, 0x75, 0x82, 0x0C, 0x1B, 0x36, 0x51, 0x6C, 0xA2, 0xD8, 0xF3,
+    0x10E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+/**
+ * The rates supported in B mode
+ */
+t_u8 SupportedRates_B[B_SUPPORTED_RATES] = {0x02, 0x04, 0x0b, 0x16, 0};
+
+/**
+ * The rates supported in G mode (BAND_G, BAND_G|BAND_GN)
+ */
+t_u8 SupportedRates_G[G_SUPPORTED_RATES] = {0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c, 0};
+
+/**
+ * The rates supported in BG mode (BAND_B|BAND_G, BAND_B|BAND_G|BAND_GN)
+ */
+t_u8 SupportedRates_BG[BG_SUPPORTED_RATES] = {0x02, 0x04, 0x0b, 0x0c, 0x12, 0x16, 0x18,
+                                              0x24, 0x30, 0x48, 0x60, 0x6c, 0};
+
+/**
+ * The rates supported in N mode
+ */
+t_u8 SupportedRates_N[N_SUPPORTED_RATES] = {0x02, 0x04, 0};
+
+#if CONFIG_11AX
+#define MCS_NUM_AX 12
+/**
+ * for MCS0/MCS1/MCS3/MCS4 have 4 additional DCM=1 value
+ * note: the value in the table is 2 multiplier of the actual rate
+ */
+static t_u16 ax_mcs_rate_nss1[12][MCS_NUM_AX + 4] = {
+    {0x90, 0x48, 0x120, 0x90, 0x1B0, 0x240, 0x120, 0x360, 0x1B0, 0x481, 0x511, 0x5A1, 0x6C1, 0x781, 0x871,
+     0x962}, /*SG 160M*/
+    {0x88, 0x44, 0x110, 0x88, 0x198, 0x220, 0x110, 0x330, 0x198, 0x440, 0x4C9, 0x551, 0x661, 0x716, 0x7F9,
+     0x8DC}, /*MG 160M*/
+    {0x7A, 0x3D, 0xF5, 0x7A, 0x16F, 0x1EA, 0xF5, 0x2DF, 0x16F, 0x3D4, 0x44E, 0x4C9, 0x5BE, 0x661, 0x72D,
+     0x7F9}, /*LG 160M*/
+    {0x48, 0x24, 0x90, 0x48, 0xD8, 0x120, 0x90, 0x1B0, 0xD8, 0x240, 0x288, 0x2D0, 0x360, 0x3C0, 0x438,
+     0x4B0}, /*SG 80M*/
+    {0x44, 0x22, 0x88, 0x44, 0xCC, 0x110, 0x88, 0x198, 0xCC, 0x220, 0x264, 0x2A8, 0x330, 0x38B, 0x3FC,
+     0x46E},                                                                                                  /*MG 80M*/
+    {0x3D, 0x1E, 0x7A, 0x3D, 0xB7, 0xF5, 0x7A, 0x16F, 0xB7, 0x1EA, 0x227, 0x264, 0x2DF, 0x330, 0x396, 0x3FC}, /*LG 80M*/
+    {0x22, 0x11, 0x44, 0x22, 0x67, 0x89, 0x44, 0xCE, 0x67, 0x113, 0x135, 0x158, 0x19D, 0x1CA, 0x204, 0x23D},  /*SG 40M*/
+    {0x20, 0x10, 0x41, 0x20, 0x61, 0x82, 0x41, 0xC3, 0x61, 0x104, 0x124, 0x145, 0x186, 0x1B1, 0x1E7, 0x21D},  /*MG 40M*/
+    {0x1D, 0xE, 0x3A, 0x1D, 0x57, 0x75, 0x3A, 0xAF, 0x57, 0xEA, 0x107, 0x124, 0x15F, 0x186, 0x1B6, 0x1E7},    /*LG 40M*/
+    {0x11, 0x8, 0x22, 0x11, 0x33, 0x44, 0x22, 0x67, 0x33, 0x89, 0x9A, 0xAC, 0xCE, 0xE5, 0x102, 0x11E},        /*SG 20M*/
+    {0x10, 0x8, 0x20, 0x10, 0x30, 0x41, 0x20, 0x61, 0x30, 0x82, 0x92, 0xA2, 0xC3, 0xD8, 0xF3, 0x10E},         /*MG 20M*/
+    {0xE, 0x7, 0x1D, 0xE, 0x2B, 0x3A, 0x1D, 0x57, 0x2B, 0x75, 0x83, 0x92, 0xAF, 0xC3, 0xDB, 0xF3}             /*LG 20M*/
+};
+#endif
+
+
+/**
+ *  @brief This function finds the CFP in
+ *  		cfp_table_BG/A based on region/code and band parameter.
+ *
+ *  @param pmadapter  A pointer to mlan_adapter structure
+ *  @param region     The region code
+ *  @param band       The band
+ *  @param cfp_no     A pointer to CFP number
+ *
+ *  @return           A pointer to CFP
+ */
+static const chan_freq_power_t *wlan_get_region_cfp_table(pmlan_adapter pmadapter, t_u8 region, t_u16 band, int *cfp_no)
+{
+    t_u32 i;
+    t_u8 cfp_bg;
+#if CONFIG_5GHz_SUPPORT
+    t_u8 cfp_a;
+#endif /* CONFIG_5GHz_SUPPORT */
+
+    ENTER();
+
+    cfp_bg = region;
+#if CONFIG_5GHz_SUPPORT
+    cfp_a = region;
+#endif /* CONFIG_5GHz_SUPPORT */
+    if (region == 0U || region == 0x40)
+    {
+        /* Invalid region code or Japan case, use CFP code */
+        cfp_bg = pmadapter->cfp_code_bg;
+#if CONFIG_5GHz_SUPPORT
+        cfp_a = pmadapter->cfp_code_a;
+#endif /* CONFIG_5GHz_SUPPORT */
+    }
+
+    if ((band & (BAND_B | BAND_G | BAND_GN | BAND_GAC)) != 0U)
+    {
+#ifdef OTP_CHANINFO
+        /* Return the FW cfp table for requested region code, if available.
+         * If region is not forced and the requested region code is different,
+         * simply return the corresponding pre-defined table.
+         */
+        if ((pmadapter->otp_region != MNULL) && (pmadapter->cfp_otp_bg != MNULL))
+        {
+            if (pmadapter->otp_region->force_reg != (t_u16)MFALSE ||
+                (cfp_bg == (t_u8)pmadapter->otp_region->region_code))
+            {
+                *cfp_no = (int)pmadapter->tx_power_table_bg_rows;
+                LEAVE();
+                return pmadapter->cfp_otp_bg;
+            }
+        }
+#endif
+        for (i = 0; i < MLAN_CFP_TABLE_SIZE_BG; i++)
+        {
+            PRINTM(MINFO, "cfp_table_BG[%d].code=%d\n", i, cfp_table_BG[i].code);
+            /* Check if region/code matches for BG bands */
+            if (cfp_table_BG[i].code == cfp_bg)
+            {
+                /* Select by band */
+                *cfp_no = cfp_table_BG[i].cfp_no;
+                LEAVE();
+                return cfp_table_BG[i].cfp;
+            }
+        }
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if ((band & (BAND_A | BAND_AN | BAND_AAC)) != 0U)
+    {
+#ifdef OTP_CHANINFO
+        /* Return the FW cfp table for requested region code */
+        if ((pmadapter->otp_region != MNULL) && (pmadapter->cfp_otp_a != MNULL))
+        {
+            if (pmadapter->otp_region->force_reg != (t_u16)MFALSE ||
+                (cfp_a == (t_u8)pmadapter->otp_region->region_code))
+            {
+                *cfp_no = (int)pmadapter->tx_power_table_a_rows;
+                LEAVE();
+                return pmadapter->cfp_otp_a;
+            }
+        }
+#endif
+        for (i = 0; i < MLAN_CFP_TABLE_SIZE_A; i++)
+        {
+            PRINTM(MINFO, "cfp_table_A[%d].code=%d\n", i, cfp_table_A[i].code);
+            /* Check if region/code matches for A bands */
+            if (cfp_table_A[i].code == cfp_a)
+            {
+                /* Select by band */
+                *cfp_no = cfp_table_A[i].cfp_no;
+                LEAVE();
+                return cfp_table_A[i].cfp;
+            }
+        }
+    }
+#endif /* CONFIG_5GHz_SUPPORT */
+
+    if (region == 0U)
+    {
+#if CONFIG_5GHz_SUPPORT
+        PRINTM(MERROR, "Error Band[0x%x] or code[BG:%#x, A:%#x]\n", band, cfp_bg, cfp_a);
+
+#else
+        PRINTM(MERROR, "Error Band[0x%x] or code[BG:%#x]\n", band, cfp_bg);
+#endif /* CONFIG_5GHz_SUPPORT */
+    }
+    else
+    {
+        PRINTM(MERROR, "Error Band[0x%x] or region[%#x]\n", band, region);
+    }
+
+    LEAVE();
+    return MNULL;
+}
+
+/********************************************************
+    Global Functions
+********************************************************/
+/**
+ *  @brief This function converts region string to integer code
+ *
+ *  @param pmadapter        A pointer to mlan_adapter structure
+ *  @param country_code     Country string
+ *  @param cfp_bg           Pointer to buffer
+ *  @param cfp_a            Pointer to buffer
+ *
+ *  @return                 MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_misc_country_2_cfp_table_code(pmlan_adapter pmadapter, t_u8 *country_code, t_u8 *cfp_bg, t_u8 *cfp_a)
+{
+    t_u8 i;
+
+    ENTER();
+
+    /* Look for code in mapping table */
+    for (i = 0; i < NELEMENTS(country_code_mapping); i++)
+    {
+        if (!__memcmp(pmadapter, country_code_mapping[i].country_code, country_code, COUNTRY_CODE_LEN - 1))
+        {
+            *cfp_bg = country_code_mapping[i].cfp_code_bg;
+            *cfp_a  = country_code_mapping[i].cfp_code_a;
+            LEAVE();
+            return MLAN_STATUS_SUCCESS;
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_FAILURE;
+}
+
+#ifdef SD8801
+/**
+ *  @brief Use index to get the data rate
+ *
+ *  @param pmadapter   A pointer to mlan_adapter structure
+ *  @param index       The index of data rate
+ *  @param ht_info     HT info
+ *
+ *  @return            Data rate or 0
+ */
+t_u32 wlan_index_to_data_rate(pmlan_adapter pmadapter, t_u8 index, t_u8 ht_info)
+{
+#define MCS_NUM_SUPP 8
+    t_u16 mcs_num_supp              = MCS_NUM_SUPP;
+    t_u16 mcs_rate[4][MCS_NUM_SUPP] = {{0x1b, 0x36, 0x51, 0x6c, 0xa2, 0xd8, 0xf3, 0x10e},  /*LG 40M*/
+                                       {0x1e, 0x3c, 0x5a, 0x78, 0xb4, 0xf0, 0x10e, 0x12c}, /*SG 40M */
+                                       {0x0d, 0x1a, 0x27, 0x34, 0x4e, 0x68, 0x75, 0x82},   /*LG 20M */
+                                       {0x0e, 0x1c, 0x2b, 0x39, 0x56, 0x73, 0x82, 0x90}};  /*SG 20M */
+    t_u32 rate = 0;
+
+    ENTER();
+
+    if (ht_info & MBIT(0))
+    {
+        if (index == MLAN_RATE_BITMAP_MCS0)
+        {
+            if (ht_info & MBIT(2))
+                rate = 0x0D; /* MCS 32 SGI rate */
+            else
+                rate = 0x0C; /* MCS 32 LGI rate */
+        }
+        else if (index < mcs_num_supp)
+        {
+            if (ht_info & MBIT(1))
+            {
+                if (ht_info & MBIT(2))
+                    rate = mcs_rate[1][index]; /* SGI, 40M */
+                else
+                    rate = mcs_rate[0][index]; /* LGI, 40M */
+            }
+            else
+            {
+                if (ht_info & MBIT(2))
+                    rate = mcs_rate[3][index]; /* SGI, 20M */
+                else
+                    rate = mcs_rate[2][index]; /* LGI, 20M */
+            }
+        }
+        else
+            rate = WlanDataRates[0];
+    }
+    else
+    {
+        /* 11n non HT rates */
+        if (index >= WLAN_SUPPORTED_RATES_EXT)
+        {
+            index = 0;
+        }
+        rate = WlanDataRates[index];
+    }
+    LEAVE();
+    return rate;
+}
+#else
+/**
+ *  @brief Use index to get the data rate
+ *
+ *  @param pmadapter        A pointer to mlan_adapter structure
+ *  @param index            The index of data rate
+ *  @param tx_rate_info     Tx rate info
+ *  @param ext_rate_info    Extend tx rate info
+ *  @return                 Data rate or 0
+ */
+t_u32 wlan_index_to_data_rate(pmlan_adapter pmadapter,
+                              t_u8 index,
+                              t_u8 tx_rate_info
+#if CONFIG_11AX
+                              ,
+                              t_u8 ext_rate_info
+#endif
+)
+{
+#define MCS_NUM_SUPP 8U
+    t_u16 mcs_rate[4][MCS_NUM_SUPP] = {{0x1b, 0x36, 0x51, 0x6c, 0xa2, 0xd8, 0xf3, 0x10e},  /*LG 40M*/
+                                       {0x1e, 0x3c, 0x5a, 0x78, 0xb4, 0xf0, 0x10e, 0x12c}, /*SG 40M */
+                                       {0x0d, 0x1a, 0x27, 0x34, 0x4e, 0x68, 0x75, 0x82},   /*LG 20M */
+                                       {0x0e, 0x1c, 0x2b, 0x39, 0x56, 0x73, 0x82, 0x90}};  /*SG 20M */
+
+#if CONFIG_11AC
+#define MCS_NUM_AC 10
+    /* NSS 1. note: the value in the table is 2 multiplier of the actual rate
+     *              in other words, it is in the unit of 500 Kbs
+     */
+    t_u16 ac_mcs_rate_nss1[8][MCS_NUM_AC] = {
+        {0x75, 0xEA, 0x15F, 0x1D4, 0x2BE, 0x3A8, 0x41D, 0x492, 0x57C, 0x618},  /* LG 160M*/
+        {0x82, 0x104, 0x186, 0x208, 0x30C, 0x410, 0x492, 0x514, 0x618, 0x6C6}, /* SG 160M*/
+        {0x3B, 0x75, 0xB0, 0xEA, 0x15F, 0x1D4, 0x20F, 0x249, 0x2BE, 0x30C},    /* LG 80M */
+        {0x41, 0x82, 0xC3, 0x104, 0x186, 0x208, 0x249, 0x28A, 0x30C, 0x363},   /* SG 80M */
+        {0x1B, 0x36, 0x51, 0x6C, 0xA2, 0xD8, 0xF3, 0x10E, 0x144, 0x168},       /* LG 40M */
+        {0x1E, 0x3C, 0x5A, 0x78, 0xB4, 0xF0, 0x10E, 0x12C, 0x168, 0x190},      /* SG 40M */
+        {0xD, 0x1A, 0x27, 0x34, 0x4E, 0x68, 0x75, 0x82, 0x9C, 0x00},           /* LG 20M */
+        {0xF, 0x1D, 0x2C, 0x3A, 0x57, 0x74, 0x82, 0x91, 0xAE, 0x00},           /* SG 20M */
+    };
+#endif /* CONFIG_11AC */
+
+    t_u32 rate     = 0;
+#if (CONFIG_11AC) || (CONFIG_11AX)
+    t_u8 mcs_index = 0;
+#endif
+#if CONFIG_11AX
+    t_u8 he_dcm    = 0;
+    t_u8 stbc      = 0;
+#endif
+    t_u8 bw        = 0;
+    t_u8 gi        = 0;
+    ENTER();
+
+#if CONFIG_11AC
+    if ((tx_rate_info & 0x3U) == (t_u8)MLAN_RATE_FORMAT_VHT)
+    {
+        /* VHT rate */
+        mcs_index = index & 0xFU;
+
+        if (mcs_index > 9U)
+        {
+            mcs_index = 9U;
+        }
+
+        /* 20M: bw=0, 40M: bw=1, 80M: bw=2, 160M: bw=3 */
+        bw = (tx_rate_info & 0xCU) >> 2U;
+        /* LGI: gi =0, SGI: gi = 1 */
+        gi = (tx_rate_info & 0x10U) >> 4U;
+        {
+            /* NSS = 1 */
+            rate = ac_mcs_rate_nss1[2U * (3U - bw) + gi][mcs_index];
+        }
+    }
+    else
+#endif
+#if CONFIG_11AX
+        if ((mlan_rate_format)(tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_HE)
+    {
+        /* HE rate */
+        mcs_index = index & 0xF;
+        he_dcm    = ext_rate_info & MBIT(0);
+        if (mcs_index > MCS_NUM_AX - 1)
+            mcs_index = MCS_NUM_AX - 1;
+        /* 20M: bw=0, 40M: bw=1, 80M: bw=2, 160M: bw=3 */
+        bw = (tx_rate_info & (MBIT(3) | MBIT(2))) >> 2;
+        /* BIT7:BIT4 0:0= 0.8us,0:1= 0.8us, 1:0=1.6us, 1:1=3.2us or 0.8us */
+        gi = (tx_rate_info & MBIT(4)) >> 4 | (tx_rate_info & MBIT(7)) >> 6;
+        /* STBC: BIT5 in tx rate info */
+        stbc = (tx_rate_info & MBIT(5)) >> 5;
+        if (gi > 3)
+        {
+            PRINTM(MERROR, "Invalid gi value");
+            return 0;
+        }
+        if ((gi == 3) && stbc && he_dcm)
+        {
+            gi     = 0;
+            stbc   = 0;
+            he_dcm = 0;
+        }
+        /* map to gi 0:0.8us,1:1.6us 2:3.2us*/
+        if (gi > 0)
+            gi = gi - 1;
+        switch (mcs_index)
+        {
+            case 0:
+            case 1:
+                rate = ax_mcs_rate_nss1[3 * (3 - bw) + gi][mcs_index * 2 + he_dcm];
+                break;
+            case 2:
+                rate = ax_mcs_rate_nss1[3 * (3 - bw) + gi][mcs_index * 2];
+                break;
+            case 3:
+            case 4:
+                rate = ax_mcs_rate_nss1[3 * (3 - bw) + gi][mcs_index * 2 - 1 + he_dcm];
+                break;
+            default:
+                rate = ax_mcs_rate_nss1[3 * (3 - bw) + gi][mcs_index + 4];
+                break;
+        }
+    }
+    else
+#endif
+        if ((tx_rate_info & 0x3U) == (t_u8)MLAN_RATE_FORMAT_HT)
+    {
+        /* HT rate */
+        /* 20M: bw=0, 40M: bw=1 */
+        bw = (tx_rate_info & 0xCU) >> 2U;
+        /* LGI: gi =0, SGI: gi = 1 */
+        gi = (tx_rate_info & 0x10U) >> 4U;
+        if (index == MLAN_RATE_BITMAP_MCS0)
+        {
+            if (gi == 1U)
+            {
+                rate = 0x0D; /* MCS 32 SGI rate */
+            }
+            else
+            {
+                rate = 0x0C; /* MCS 32 LGI rate */
+            }
+        }
+        else if (index < MCS_NUM_SUPP)
+        {
+            if (bw <= 1U)
+            {
+                rate = mcs_rate[2U * (1U - bw) + gi][index];
+            }
+            else
+            {
+                rate = WlanDataRates[0];
+            }
+        }
+        else
+        {
+            rate = WlanDataRates[0];
+        }
+    }
+    else
+    {
+        /* 11n non HT rates */
+        if (index >= WLAN_SUPPORTED_RATES_EXT)
+        {
+            index = 0;
+        }
+        rate = WlanDataRates[index];
+    }
+    LEAVE();
+    return rate;
+}
+#endif
+
+
+/**
+ *  @brief Get active data rates
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param bss_mode         The specified BSS mode (Infra/IBSS)
+ *  @param config_bands     The specified band configuration
+ *  @param rates            The buf to return the active rates
+ *
+ *  @return                 The number of Rates
+ */
+t_u32 wlan_get_active_data_rates(mlan_private *pmpriv,
+                                 mlan_bss_mode bss_mode,
+                                 t_u16 config_bands,
+                                 WLAN_802_11_RATES rates)
+{
+    t_u32 k;
+
+    ENTER();
+
+    if (pmpriv->media_connected != MTRUE)
+    {
+        k = wlan_get_supported_rates(pmpriv, bss_mode, config_bands, rates);
+    }
+    else
+    {
+        k = wlan_copy_rates(rates, 0, pmpriv->curr_bss_params.data_rates, (int)pmpriv->curr_bss_params.num_of_rates);
+    }
+
+    LEAVE();
+    return k;
+}
+
+/**
+ *  @brief This function search through all the regions cfp table to find the channel,
+ *            if the channel is found then gets the MIN txpower of the channel
+ *            present in all the regions.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param channel      Channel number.
+ *
+ *  @return             The Tx power
+ */
+t_u8 wlan_get_txpwr_of_chan_from_cfp(mlan_private *pmpriv, t_u8 channel)
+{
+    t_u8 i        = 0;
+    t_u8 j        = 0;
+    t_u8 tx_power = 0;
+    t_u32 cfp_no;
+    const chan_freq_power_t *cfp = MNULL;
+#if CONFIG_5GHz_SUPPORT
+    const chan_freq_power_t *cfp_a = MNULL;
+    t_u32 cfp_no_a;
+#endif /* CONFIG_5GHz_SUPPORT */
+
+    ENTER();
+
+    for (i = 0; i < MLAN_CFP_TABLE_SIZE_BG; i++)
+    {
+        /* Get CFP */
+        cfp    = cfp_table_BG[i].cfp;
+        cfp_no = (t_u32)cfp_table_BG[i].cfp_no;
+        /* Find matching channel and get Tx power */
+        for (j = 0; j < cfp_no; j++)
+        {
+            if ((cfp + j)->channel == channel)
+            {
+                if (tx_power != 0U)
+                {
+                    tx_power = MIN(tx_power, (t_u8)((cfp + j)->max_tx_power));
+                }
+                else
+                {
+                    tx_power = (t_u8)(cfp + j)->max_tx_power;
+                }
+                break;
+            }
+        }
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    for (i = 0; i < MLAN_CFP_TABLE_SIZE_A; i++)
+    {
+        /* Get CFP */
+        cfp_a    = cfp_table_A[i].cfp;
+        cfp_no_a = (t_u32)cfp_table_A[i].cfp_no;
+        for (j = 0; j < cfp_no_a; j++)
+        {
+            if ((cfp_a + j)->channel == channel)
+            {
+                if (tx_power != 0U)
+                {
+                    tx_power = MIN(tx_power, (t_u8)((cfp_a + j)->max_tx_power));
+                }
+                else
+                {
+                    tx_power = (t_u8)((cfp_a + j)->max_tx_power);
+                }
+                break;
+            }
+        }
+    }
+#endif /* CONFIG_5GHz_SUPPORT */
+
+    LEAVE();
+    return tx_power;
+}
+
+/**
+ *  @brief Get the channel frequency power info for a specific channel
+ *
+ *  @param pmadapter            A pointer to mlan_adapter structure
+ *  @param band                 It can be BAND_A, BAND_G or BAND_B
+ *  @param channel              The channel to search for
+ *  @param region_channel       A pointer to region_chan_t structure
+ *
+ *  @return                     A pointer to chan_freq_power_t structure or MNULL if not found.
+ */
+
+const chan_freq_power_t *wlan_get_cfp_by_band_and_channel(pmlan_adapter pmadapter,
+                                                          t_u16 band,
+                                                          t_u16 channel,
+                                                          region_chan_t *region_channel)
+{
+    region_chan_t *rc;
+    const chan_freq_power_t *cfp = MNULL;
+    t_u8 i, j;
+
+    ENTER();
+
+    j = 0;
+    while (cfp == MNULL && (j < MAX_REGION_CHANNEL_NUM))
+    {
+        bool continue_loop = MFALSE;
+        rc                 = &region_channel[j];
+
+        if (rc->valid == (t_u8)MFALSE || rc->pcfp == MNULL)
+        {
+            j++;
+            continue;
+        }
+        switch (rc->band)
+        {
+            case BAND_A:
+                switch (band)
+                {
+                    case BAND_AN:
+                    case BAND_A | BAND_AN:
+                    case BAND_A | BAND_AN | BAND_AAC:
+                    case BAND_A: /* Matching BAND_A */
+                        break;
+
+                    default:
+                        j++;
+                        continue_loop = MTRUE;
+                        break;
+                }
+                break;
+            case BAND_B:
+            case BAND_G:
+                switch (band)
+                {
+                    case BAND_GN:
+                    case BAND_B | BAND_G | BAND_GN:
+                    case BAND_G | BAND_GN:
+                    case BAND_GN | BAND_GAC:
+                    case BAND_B | BAND_G | BAND_GN | BAND_GAC:
+                    case BAND_G | BAND_GN | BAND_GAC:
+                    case BAND_B | BAND_G:
+                    case BAND_B: /* Matching BAND_B/G */
+                    case BAND_G:
+                        break;
+                    default:
+                        j++;
+                        continue_loop = MTRUE;
+                        break;
+                }
+                break;
+            default:
+                j++;
+                continue_loop = MTRUE;
+                break;
+        }
+        if (continue_loop == MTRUE)
+        {
+            continue;
+        }
+        if (channel == FIRST_VALID_CHANNEL)
+        {
+            cfp = &rc->pcfp[0];
+        }
+        else
+        {
+            for (i = 0; i < rc->num_cfp; i++)
+            {
+                if (rc->pcfp[i].channel == channel)
+                {
+                    cfp = &rc->pcfp[i];
+                    break;
+                }
+            }
+        }
+        j++;
+    }
+
+    if (cfp == MNULL && channel != 0U)
+    {
+        PRINTM(MERROR,
+               "wlan_get_cfp_by_band_and_channel(): cannot find "
+               "cfp by band %d & channel %d\n",
+               band, channel);
+    }
+
+    LEAVE();
+    return cfp;
+}
+
+/**
+ *  @brief Find the channel frequency power info for a specific channel
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param band         It can be BAND_A, BAND_G or BAND_B
+ *  @param channel      The channel to search for
+ *
+ *  @return             A pointer to chan_freq_power_t structure or MNULL if not found.
+ */
+const chan_freq_power_t *wlan_find_cfp_by_band_and_channel(mlan_adapter *pmadapter, t_u16 band, t_u16 channel)
+{
+    const chan_freq_power_t *cfp = MNULL;
+
+    ENTER();
+
+    /* Any station(s) with 11D enabled */
+    if (wlan_count_priv_cond(pmadapter, wlan_11d_is_enabled, wlan_is_station) > 0)
+    {
+        cfp = wlan_get_cfp_by_band_and_channel(pmadapter, band, channel, pmadapter->universal_channel);
+    }
+    else
+    {
+        cfp = wlan_get_cfp_by_band_and_channel(pmadapter, band, channel, pmadapter->region_channel);
+    }
+
+    LEAVE();
+    return cfp;
+}
+
+/**
+ *  @brief Find the channel frequency power info for a specific frequency
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param band         It can be BAND_A, BAND_G or BAND_B
+ *  @param freq         The frequency to search for
+ *
+ *  @return         Pointer to chan_freq_power_t structure; MNULL if not found
+ */
+const chan_freq_power_t *wlan_find_cfp_by_band_and_freq(mlan_adapter *pmadapter, t_u16 band, t_u32 freq)
+{
+    const chan_freq_power_t *cfp = MNULL;
+    region_chan_t *rc;
+    t_u8 i, j;
+
+    ENTER();
+
+    j = 0;
+    while (cfp == MNULL && (j < MAX_REGION_CHANNEL_NUM))
+    {
+        bool continue_loop = MFALSE;
+        rc                 = &pmadapter->region_channel[j];
+
+        /* Any station(s) with 11D enabled */
+        if (wlan_count_priv_cond(pmadapter, wlan_11d_is_enabled, wlan_is_station) > 0)
+        {
+            rc = &pmadapter->universal_channel[j];
+        }
+
+        if (rc->valid == 0U || rc->pcfp == MNULL)
+        {
+            j++;
+            continue;
+        }
+        switch (rc->band)
+        {
+            case BAND_A:
+                switch (band)
+                {
+                    case BAND_AN:
+                    case BAND_A | BAND_AN:
+                    case BAND_A | BAND_AN | BAND_AAC:
+                    case BAND_A: /* Matching BAND_A */
+                        break;
+                    default:
+                        j++;
+                        continue_loop = MTRUE;
+                        break;
+                }
+                break;
+            case BAND_B:
+            case BAND_G:
+                switch (band)
+                {
+                    case BAND_GN:
+                    case BAND_B | BAND_G | BAND_GN:
+                    case BAND_G | BAND_GN:
+                    case BAND_GN | BAND_GAC:
+                    case BAND_B | BAND_G | BAND_GN | BAND_GAC:
+                    case BAND_G | BAND_GN | BAND_GAC:
+                    case BAND_B | BAND_G:
+                    case BAND_B:
+                    case BAND_G:
+                        break;
+                    default:
+                        j++;
+                        continue_loop = MTRUE;
+                        break;
+                }
+                break;
+            default:
+                j++;
+                continue_loop = MTRUE;
+                break;
+        }
+        if (continue_loop == MTRUE)
+        {
+            continue;
+        }
+        for (i = 0; i < rc->num_cfp; i++)
+        {
+            if (rc->pcfp[i].freq == freq)
+            {
+                cfp = &rc->pcfp[i];
+                break;
+            }
+        }
+        j++;
+    }
+
+    if (cfp == MNULL && freq != 0U)
+    {
+        PRINTM(MERROR,
+               "wlan_find_cfp_by_band_and_freq(): cannot find cfp by "
+               "band %d & freq %d\n",
+               band, freq);
+    }
+
+    LEAVE();
+    return cfp;
+}
+
+/**
+ *  @brief Check if Rate Auto
+ *
+ *  @param pmpriv               A pointer to mlan_private structure
+ *
+ *  @return                     MTRUE or MFALSE
+ */
+bool wlan_is_rate_auto(mlan_private *pmpriv)
+{
+    t_u32 i;
+    int rate_num = 0;
+
+    ENTER();
+
+    for (i = 0; i < NELEMENTS(pmpriv->bitmap_rates); i++)
+    {
+        if (pmpriv->bitmap_rates[i] != 0U)
+        {
+            rate_num++;
+        }
+    }
+
+    LEAVE();
+    if (rate_num > 1)
+    {
+        return MTRUE;
+    }
+    else
+    {
+        return MFALSE;
+    }
+}
+
+/**
+ *  @brief Covert Rate Bitmap to Rate index
+ *
+ *  @param pmadapter    Pointer to mlan_adapter structure
+ *  @param rate_bitmap  Pointer to rate bitmap
+ *  @param size         Size of the bitmap array
+ *
+ *  @return             Rate index
+ */
+int wlan_get_rate_index(pmlan_adapter pmadapter, t_u16 *rate_bitmap, int size)
+{
+    int i;
+
+    ENTER();
+
+    for (i = 0; i < size * 8; i++)
+    {
+        if ((rate_bitmap[i / 16] & ((t_u32)1U << ((t_u32)i % 16U))) != 0U)
+        {
+            LEAVE();
+            return i;
+        }
+    }
+
+    LEAVE();
+    return -1;
+}
+
+/**
+ *  @brief Convert config_bands to B/G/A band
+ *
+ *  @param config_bands     The specified band configuration
+ *
+ *  @return                 BAND_B|BAND_G|BAND_A
+ */
+t_u16 wlan_convert_config_bands(t_u16 config_bands)
+{
+    t_u16 bands = 0;
+    if (config_bands & BAND_B)
+        bands |= BAND_B;
+    if (config_bands & BAND_G || config_bands & BAND_GN
+#ifdef ENABLE_802_11AC
+        || config_bands & BAND_GAC
+#endif
+#ifdef ENABLE_802_11AX
+        || config_bands & BAND_GAX
+#endif
+    )
+        bands |= BAND_G;
+    if (config_bands & BAND_A || config_bands & BAND_AN
+#ifdef ENABLE_802_11AC
+        || config_bands & BAND_AAC
+#endif
+#ifdef ENABLE_802_11AX
+        || config_bands & BAND_AAX
+#endif
+    )
+        bands |= BAND_A;
+    return bands;
+}
+
+/**
+ *  @brief Get supported data rates
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param bss_mode         The specified BSS mode (Infra/IBSS)
+ *  @param config_bands     The specified band configuration
+ *  @param rates            The buf to return the supported rates
+ *
+ *  @return                 The number of Rates
+ */
+t_u32 wlan_get_supported_rates(mlan_private *pmpriv,
+                               mlan_bss_mode bss_mode,
+                               t_u16 config_bands,
+                               WLAN_802_11_RATES rates)
+{
+    t_u32 k     = 0;
+    t_u16 bands = 0;
+
+    ENTER();
+
+    bands = wlan_convert_config_bands(config_bands);
+    if (bss_mode == MLAN_BSS_MODE_INFRA)
+    {
+        /* Infra. mode */
+        if (bands == BAND_B)
+        {
+            /* B only */
+            k = wlan_copy_rates(rates, k, SupportedRates_B, sizeof(SupportedRates_B));
+        }
+        else if (bands == BAND_G)
+        {
+            /* G only */
+            k = wlan_copy_rates(rates, k, SupportedRates_G, sizeof(SupportedRates_G));
+        }
+        else if (bands & (BAND_B | BAND_G))
+        {
+            /* BG only */
+                k = wlan_copy_rates(rates, k, SupportedRates_BG, sizeof(SupportedRates_BG));
+        }
+        else if (bands & BAND_A)
+        {
+            /* support A */
+            k = wlan_copy_rates(rates, k, SupportedRates_A, sizeof(SupportedRates_A));
+        }
+    }
+    else
+    {
+        /* Adhoc. mode */
+        if (bands == BAND_B)
+        {
+            /* B only */
+            k = wlan_copy_rates(rates, k, AdhocRates_B, sizeof(AdhocRates_B));
+        }
+        else if (bands == BAND_G)
+        {
+            /* G only */
+            k = wlan_copy_rates(rates, k, AdhocRates_G, sizeof(AdhocRates_G));
+        }
+        else if (bands & BAND_A)
+        {
+            /* support A */
+            k = wlan_copy_rates(rates, k, AdhocRates_A, sizeof(AdhocRates_A));
+        }
+        else
+        {
+            k = wlan_copy_rates(rates, k, AdhocRates_BG, sizeof(AdhocRates_BG));
+        }
+    }
+
+    LEAVE();
+    return k;
+}
+
+/**
+ *  @brief This function sets region table.
+ *
+ *  @param pmpriv  A pointer to mlan_private structure
+ *  @param region  The region code
+ *  @param band    The band
+ *
+ *  @return        MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_set_regiontable(mlan_private *pmpriv, t_u8 region, t_u16 band)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    int i                   = 0;
+    const chan_freq_power_t *cfp;
+    int cfp_no;
+
+    ENTER();
+
+    (void)__memset(pmadapter, pmadapter->region_channel, 0, sizeof(pmadapter->region_channel));
+
+    if ((band & (BAND_B | BAND_G | BAND_GN)) != 0U)
+    {
+        cfp = wlan_get_region_cfp_table(pmadapter, region, (BAND_G | BAND_B | BAND_GN), &cfp_no);
+        if (cfp != MNULL)
+        {
+            pmadapter->region_channel[i].num_cfp = (t_u8)cfp_no;
+            pmadapter->region_channel[i].pcfp    = cfp;
+        }
+        else
+        {
+            PRINTM(MERROR, "wrong region code %#x in Band B-G\n", region);
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        pmadapter->region_channel[i].valid  = (t_u8)MTRUE;
+        pmadapter->region_channel[i].region = region;
+        if ((band & BAND_GN) != 0U)
+        {
+            pmadapter->region_channel[i].band = BAND_G;
+        }
+        else
+        {
+            pmadapter->region_channel[i].band = (band & BAND_G) != 0U ? BAND_G : BAND_B;
+        }
+        i++;
+    }
+#if CONFIG_5GHz_SUPPORT
+    if ((band & (BAND_A | BAND_AN | BAND_AAC)) != 0U)
+    {
+        cfp = wlan_get_region_cfp_table(pmadapter, region, BAND_A, &cfp_no);
+        if (cfp != MNULL)
+        {
+            pmadapter->region_channel[i].num_cfp = (t_u8)cfp_no;
+            pmadapter->region_channel[i].pcfp    = cfp;
+        }
+        else
+        {
+            PRINTM(MERROR, "wrong region code %#x in Band A\n", region);
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        pmadapter->region_channel[i].valid  = (t_u8)MTRUE;
+        pmadapter->region_channel[i].region = region;
+        pmadapter->region_channel[i].band   = BAND_A;
+    }
+#endif /* CONFIG_5GHz_SUPPORT */
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Get if radar detection is enabled or not on a certain channel
+ *
+ *  @param priv    Private driver information structure
+ *  @param chnl Channel to determine radar detection requirements
+ *
+ *  @return
+ *    - MTRUE if radar detection is required
+ *    - MFALSE otherwise
+ */
+t_bool wlan_get_cfp_radar_detect(mlan_private *priv, t_u8 chnl)
+{
+    t_u8 i, j;
+    t_bool required               = MFALSE;
+    const chan_freq_power_t *pcfp = MNULL;
+
+    ENTER();
+
+    /* get the cfp table first */
+    for (i = 0; i < MAX_REGION_CHANNEL_NUM; i++)
+    {
+        if (priv->adapter->region_channel[i].band == BAND_A)
+        {
+            pcfp = priv->adapter->region_channel[i].pcfp;
+            break;
+        }
+    }
+
+    if (pcfp == MNULL)
+    {
+        /* This means operation in BAND-A is not support, we can just return
+           false here, it's harmless */
+        goto done;
+    }
+
+    /* get the radar detection requirements according to chan num */
+    for (j = 0; j < priv->adapter->region_channel[i].num_cfp; j++)
+    {
+        if (pcfp[j].channel == chnl)
+        {
+            required = pcfp[j].passive_scan_or_radar_detect;
+            break;
+        }
+    }
+
+done:
+    LEAVE();
+    return required;
+}
+
+/**
+ *  @brief Get if scan type is passive or not on a certain channel for b/g band
+ *
+ *  @param priv    Private driver information structure
+ *  @param chnl Channel to determine scan type
+ *
+ *  @return
+ *    - MTRUE if scan type is passive
+ *    - MFALSE otherwise
+ */
+
+t_bool wlan_bg_scan_type_is_passive(mlan_private *priv, t_u8 chnl)
+{
+    t_u8 i, j;
+    t_bool passive                = MFALSE;
+    const chan_freq_power_t *pcfp = MNULL;
+
+    ENTER();
+
+    /* get the cfp table first */
+    for (i = 0; i < MAX_REGION_CHANNEL_NUM; i++)
+    {
+        if ((priv->adapter->region_channel[i].band & (BAND_B | BAND_G)) != 0U)
+        {
+            pcfp = priv->adapter->region_channel[i].pcfp;
+            break;
+        }
+    }
+
+    if (pcfp == MNULL)
+    {
+        /* This means operation in BAND-B or BAND_G is not support, we can
+           just return false here */
+        goto done;
+    }
+
+    /* get the bg scan type according to chan num */
+    for (j = 0; j < priv->adapter->region_channel[i].num_cfp; j++)
+    {
+        if (pcfp[j].channel == chnl)
+        {
+            passive = pcfp[j].passive_scan_or_radar_detect;
+            break;
+        }
+    }
+
+done:
+    LEAVE();
+    return passive;
+}
+
+/**
+ * @bried convert ht_info to rate_info
+ *
+ * @param ht_info	ht_info
+ *
+ * @return		rate_info
+ */
+t_u8 wlan_convert_v14_rate_ht_info(t_u8 ht_info)
+{
+    t_u8 rate_info = 0;
+    rate_info      = ht_info & 0x01U;
+    /* band */
+    rate_info |= (ht_info & MBIT(1)) << 1;
+    /* Short GI */
+    rate_info |= (ht_info & MBIT(2)) << 1;
+    return rate_info;
+}
+
+/**
+ * @brief Validate if channel is in range of World Wide Safe Mode
+ *
+ * @param chan_num	Channel Number
+ *
+ * @return		Valid or Invalid
+ */
+t_bool wlan_is_channel_valid(t_u8 chan_num)
+{
+    t_bool valid = MFALSE;
+    int i        = 0;
+    chan_freq_power_t *cfp_wwsm;
+    int cfp_no = 0;
+
+    ENTER();
+
+    cfp_wwsm = (chan_freq_power_t *)channel_freq_power_WW_BG;
+    cfp_no   = (int)(sizeof(channel_freq_power_WW_BG) / sizeof(chan_freq_power_t));
+
+    for (i = 0; i < cfp_no; i++)
+    {
+        /* Channel 0 is invalid */
+        if (chan_num == 0U)
+        {
+            PRINTM(MERROR, "Invalid channel. Channel number can't be %d\r\n", chan_num);
+            valid = MFALSE;
+            break;
+        }
+
+        if (chan_num == cfp_wwsm[i].channel)
+        {
+            valid = MTRUE;
+            break;
+        }
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if (!valid)
+    {
+        cfp_wwsm = (chan_freq_power_t *)channel_freq_power_WW_A;
+        cfp_no   = (int)(sizeof(channel_freq_power_WW_A) / sizeof(chan_freq_power_t));
+
+        for (i = 0; i < cfp_no; i++)
+        {
+            /* Channel 0 is invalid */
+            if (chan_num == 0U)
+            {
+                PRINTM(MERROR, "Invalid channel. Channel number can't be %d\r\n", chan_num);
+                valid = MFALSE;
+                break;
+            }
+
+            if (chan_num == cfp_wwsm[i].channel)
+            {
+                valid = MTRUE;
+                break;
+            }
+        }
+    }
+#endif
+
+    LEAVE();
+    return valid;
+}
+
+/**
+ * @brief Validate if channel is in range of region table
+ *
+ * @param priv    Private driver information structure
+ * @param chan_num	Channel Number
+ *
+ * @return		Valid or Invalid
+ */
+t_bool wlan_check_channel_by_region_table(mlan_private *pmpriv, t_u8 chan_num)
+{
+    t_bool valid = MFALSE;
+    int i        = 0;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    const chan_freq_power_t *cfp = pmadapter->region_channel[0].pcfp;
+    int cfp_no  = pmadapter->region_channel[0].num_cfp;
+
+    ENTER();
+
+    if(NULL == cfp)
+        return MFALSE;
+
+    /* Channel 0 is invalid */
+    if (chan_num == 0)
+    {
+        PRINTM(MERROR, "Invalid channel. Channel number can't be %d\r\n", chan_num);
+        valid = MFALSE;
+        return valid;
+    }
+
+    for (i = 0; i < cfp_no; i++)
+    {
+        if (chan_num == cfp[i].channel)
+        {
+            valid = MTRUE;
+            break;
+        }
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if (!valid)
+    {
+        cfp = pmadapter->region_channel[1].pcfp;
+        cfp_no   = pmadapter->region_channel[1].num_cfp;
+
+        if(NULL == cfp)
+            return MFALSE;
+
+        for (i = 0; i < cfp_no; i++)
+        {
+            if (chan_num == cfp[i].channel)
+            {
+                valid = MTRUE;
+                break;
+            }
+        }
+    }
+#endif
+
+    LEAVE();
+    return valid;
+}
+
+/**
+ * @brief Validate if radio mode is in range of World Wide Safe Mode
+ *
+ * @param mode	radio mode
+ *
+ * @return		Valid or Invalid
+ */
+t_bool wlan_is_radio_mode_valid(t_u8 mode)
+{
+    t_bool valid = MFALSE;
+    int i        = 0;
+    int mode_num;
+
+    ENTER();
+    mode_num = (sizeof(rf_radio_modes_group) / sizeof(rf_radio_modes_group[0]));
+
+    for (i = 0; i < mode_num; i++)
+    {
+        if (mode == rf_radio_modes_group[i])
+        {
+            valid = MTRUE;
+            break;
+        }
+    }
+
+    if (valid == MFALSE)
+    {
+        PRINTF("Invalid radio mode. Radio mode can't be %d\r\n", mode);
+    }
+    LEAVE();
+    return valid;
+}
+
+/**
+ * @brief Validate if channel and its frequency is in range of World Wide Safe Mode
+ *
+ * @param chan_num	Channel Number
+ * @param chan_freq	Channel Frequency
+ *
+ * @return		Valid or Invalid
+ */
+t_bool wlan_is_channel_and_freq_valid(mlan_adapter *pmadapter, t_u8 chan_num, t_u16 chan_freq)
+{
+    t_bool valid = MFALSE;
+    int i        = 0;
+    const chan_freq_power_t *cfp;
+    int cfp_no = 0;
+
+    ENTER();
+
+    cfp = wlan_get_region_cfp_table(pmadapter, pmadapter->region_code, (BAND_G | BAND_B | BAND_GN), &cfp_no);
+
+    for (i = 0; i < cfp_no; i++)
+    {
+        /* Channel 0 is invalid */
+        if (chan_num == 0U)
+        {
+            PRINTM(MERROR, "Invalid channel. Channel number can't be %d\r\n", chan_num);
+            valid = MFALSE;
+            break;
+        }
+
+        if (chan_num == cfp[i].channel)
+        {
+            /* Channel Number is valid. Now validate the corresponding frequency as well */
+            if (chan_freq == cfp[i].freq)
+            {
+                valid = MTRUE;
+            }
+            else
+            {
+                PRINTM(MERROR, "Channel freq mismatch. Expected %d, Configured %d\r\n", cfp[i].freq, chan_freq);
+                valid = MFALSE;
+            }
+
+            break;
+        }
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if (!valid)
+    {
+        cfp = wlan_get_region_cfp_table(pmadapter, pmadapter->region_code, BAND_A, &cfp_no);
+
+        for (i = 0; i < cfp_no; i++)
+        {
+            /* Channel 0 is invalid */
+            if (chan_num == 0U)
+            {
+                PRINTM(MERROR, "Invalid channel. Channel number can't be %d\r\n", chan_num);
+                valid = MFALSE;
+                break;
+            }
+
+            if (chan_num == cfp[i].channel)
+            {
+                /* Channel Number is valid. Now validate the corresponding frequency as well */
+                if (chan_freq == cfp[i].freq)
+                {
+                    valid = MTRUE;
+                }
+                else
+                {
+                    PRINTM(MERROR, "Channel freq mismatch. Expected %d, Configured %d\r\n", cfp[i].freq,
+                           chan_freq);
+                    valid = MFALSE;
+                }
+
+                break;
+            }
+        }
+    }
+#endif
+
+    LEAVE();
+    return valid;
+}
+
+/**
+ * @brief Set Custom CFP Table
+ *
+ * @param chanlist	Channel List Config
+ * @param cfp_no_bg	A pointer to the number of CFP entries for Band BG
+ * @param cfp_no_a	A pointer to the number of CFP entries for Band A
+ *
+ * @return              MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+#if CONFIG_5GHz_SUPPORT
+mlan_status wlan_set_custom_cfp_table(wifi_chanlist_t *chanlist, t_u8 *cfp_no_bg, t_u8 *cfp_no_a)
+#else
+mlan_status wlan_set_custom_cfp_table(wifi_chanlist_t *chanlist, t_u8 *cfp_no_bg)
+#endif
+{
+    t_u8 i      = 0;
+    t_u8 idx_bg = 0;
+    *cfp_no_bg  = 0;
+
+#if CONFIG_5GHz_SUPPORT
+    t_u8 idx_a = 0;
+    *cfp_no_a  = 0;
+#endif
+
+    ENTER();
+
+    for (i = 0; i < chanlist->num_chans; i++)
+    {
+        if ((chanlist->chan_info[i].chan_num <= MAX_CHANNELS_BG) &&
+            (idx_bg < (sizeof(channel_freq_power_Custom_BG) / sizeof(chan_freq_power_t))))
+        {
+            channel_freq_power_Custom_BG[idx_bg].channel = chanlist->chan_info[i].chan_num;
+            channel_freq_power_Custom_BG[idx_bg].freq    = chanlist->chan_info[i].chan_freq;
+            channel_freq_power_Custom_BG[idx_bg].passive_scan_or_radar_detect =
+                chanlist->chan_info[i].passive_scan_or_radar_detect;
+            idx_bg++;
+            *cfp_no_bg = idx_bg;
+        }
+#if CONFIG_5GHz_SUPPORT
+        else if ((chanlist->chan_info[i].chan_num > MAX_CHANNELS_BG) &&
+                 (idx_a < (sizeof(channel_freq_power_Custom_A) / sizeof(chan_freq_power_t))))
+        {
+            channel_freq_power_Custom_A[idx_a].channel = chanlist->chan_info[i].chan_num;
+            channel_freq_power_Custom_A[idx_a].freq    = chanlist->chan_info[i].chan_freq;
+            channel_freq_power_Custom_A[idx_a].passive_scan_or_radar_detect =
+                chanlist->chan_info[i].passive_scan_or_radar_detect;
+            idx_a++;
+            *cfp_no_a = idx_a;
+        }
+#endif
+        else
+        {
+#if CONFIG_5GHz_SUPPORT
+            PRINTM(MERROR, "Error in configuring custom CFP table. ch %d, idx_bg %d, idx_a %d\r\n",
+                   chanlist->chan_info[i].chan_num, idx_bg, idx_a);
+#else
+            PRINTM(MERROR, "Error in configuring custom CFP table. ch %d, idx_bg %d\r\n", chanlist->chan_info[i].chan_num,
+                   idx_bg);
+#endif
+            return MLAN_STATUS_FAILURE;
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function sets custom region table.
+ *
+ *  @param pmpriv 	A pointer to mlan_private structure
+ *  @param cfp_no_bg	Number of CFP entries for Band BG
+ *  @param cfp_no_a	Number of CFP entries for Band A
+ *
+ *  @return        MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+#if CONFIG_5GHz_SUPPORT
+void wlan_set_custom_regiontable(mlan_private *pmpriv, t_u8 cfp_no_bg, t_u8 cfp_no_a)
+#else
+void wlan_set_custom_regiontable(mlan_private *pmpriv, t_u8 cfp_no_bg)
+#endif
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    int i                   = 0;
+
+    ENTER();
+
+    if (cfp_no_bg != 0U)
+    {
+        pmadapter->region_channel[i].num_cfp = (t_u8)cfp_no_bg;
+        pmadapter->region_channel[i].pcfp    = channel_freq_power_Custom_BG;
+    }
+
+    i++;
+
+#if CONFIG_5GHz_SUPPORT
+    if (cfp_no_a != 0U)
+    {
+        pmadapter->region_channel[i].num_cfp = (t_u8)cfp_no_a;
+        pmadapter->region_channel[i].pcfp    = channel_freq_power_Custom_A;
+    }
+#endif
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function gets the list of configured active channels.
+ *
+ *  @param pmpriv 	A pointer to mlan_private structure
+ *  @param chan_list	A pointer to the channel list
+ *  @param num_chans	A pointer to the number of active channels
+ *  @param acs_band  ACS band info     0: get 2.4G channel list
+ *                                     1: get 5G channel list
+ */
+void wlan_get_active_channel_list(mlan_private *pmpriv, t_u8 *chan_list, t_u8 *num_chans, t_u16 acs_band)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    int i                   = 0;
+    int j                   = 0;
+    const chan_freq_power_t *cfp;
+    int cfp_no;
+
+    ENTER();
+
+    *num_chans = 0;
+
+    if (acs_band == 0)
+    {
+        cfp    = pmadapter->region_channel[i].pcfp;
+        cfp_no = pmadapter->region_channel[i].num_cfp;
+        for (j = 0; j < cfp_no; j++)
+        {
+            if ((!(cfp[j].dynamic.flags & NXP_CHANNEL_DISABLED)) && (!cfp[j].passive_scan_or_radar_detect))
+            {
+                *(chan_list++) = cfp[j].channel;
+                *num_chans     = *num_chans + 1;
+            }
+        }
+    }
+    if (acs_band == 1)
+    {
+#if CONFIG_5GHz_SUPPORT
+        i      = 1;
+        cfp    = pmadapter->region_channel[i].pcfp;
+        cfp_no = (int)pmadapter->region_channel[i].num_cfp;
+
+        for (j = 0; j < cfp_no; j++)
+        {
+            if ((!(cfp[j].dynamic.flags & NXP_CHANNEL_DISABLED)) && (!cfp[j].passive_scan_or_radar_detect))
+            {
+                *(chan_list++) = (t_u8)cfp[j].channel;
+                *num_chans     = *num_chans + 1U;
+            }
+        }
+
+#endif
+    }
+}
+
+#ifdef OTP_CHANINFO
+/**
+ *  @brief	Update CFP tables and power tables from FW
+ *
+ *  @param priv		Private driver information structure
+ *  @param buf		Pointer to the buffer holding TLV data
+ *					from 0x242 command response.
+ *  @param buf_left	bufsize
+ *
+ *  @return
+ *    None
+ */
+void wlan_add_fw_cfp_tables(pmlan_private pmpriv, t_u8 *buf, t_u16 buf_left)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    mlan_callbacks *pcb     = (mlan_callbacks *)&pmadapter->callbacks;
+    MrvlIEtypesHeader_t *head;
+    t_u16 tlv;
+    t_u16 tlv_buf_len;
+    t_u16 tlv_buf_left;
+    t_u16 i;
+    int k               = 0, rows, cols;
+    t_u16 max_tx_pwr_bg = WLAN_TX_PWR_DEFAULT;
+#if CONFIG_5GHz_SUPPORT
+    t_u16 max_tx_pwr_a = WLAN_TX_PWR_DEFAULT;
+#endif
+    t_u8 *tlv_buf;
+    t_u8 *data;
+    t_u8 *tmp;
+    mlan_status ret;
+
+    ENTER();
+
+    if (buf == MNULL)
+    {
+        PRINTM(MERROR, "CFP table update failed!\n");
+        goto out;
+    }
+    if (pmadapter->otp_region != MNULL)
+    {
+        wlan_free_fw_cfp_tables(pmadapter);
+    }
+
+    pmadapter->tx_power_table_bg_rows = FW_CFP_TABLE_MAX_ROWS_BG;
+    pmadapter->tx_power_table_bg_cols = FW_CFP_TABLE_MAX_COLS_BG;
+#if CONFIG_5GHz_SUPPORT
+    pmadapter->tx_power_table_a_rows = FW_CFP_TABLE_MAX_ROWS_A;
+    pmadapter->tx_power_table_a_cols = FW_CFP_TABLE_MAX_COLS_A;
+#endif
+    tlv_buf      = (t_u8 *)buf;
+    tlv_buf_left = buf_left;
+
+    while (tlv_buf_left >= sizeof(*head))
+    {
+        head        = (MrvlIEtypesHeader_t *)(void *)tlv_buf;
+        tlv         = wlan_le16_to_cpu(head->type);
+        tlv_buf_len = wlan_le16_to_cpu(head->len);
+
+        if (tlv_buf_left < (sizeof(*head) + tlv_buf_len))
+        {
+            break;
+        }
+        data = (t_u8 *)head + sizeof(*head);
+
+        switch (tlv)
+        {
+            case TLV_TYPE_REGION_INFO:
+                /* Skip adding fw region info if it already exists or
+                 * if this TLV has no set data
+                 */
+                if (*data == 0U)
+                {
+                    break;
+                }
+                if (pmadapter->otp_region != MNULL)
+                {
+                    break;
+                }
+
+                ret = pcb->moal_malloc(pmadapter->pmoal_handle, sizeof(otp_region_info_t), MLAN_MEM_DEF,
+                                       (t_u8 **)(void **)&pmadapter->otp_region);
+
+                if (ret != MLAN_STATUS_SUCCESS || (pmadapter->otp_region == MNULL))
+                {
+                    PRINTM(MERROR,
+                           "Memory allocation for the otp region"
+                           " info struct failed!\n");
+                    break;
+                }
+                /* Save region info values from OTP in the otp_region
+                 * structure
+                 */
+                (void)__memcpy(pmadapter, pmadapter->otp_region, data, sizeof(otp_region_info_t));
+
+                data += sizeof(otp_region_info_t);
+                /* Get pre-defined cfp tables corresponding to the region code
+                 * in OTP
+                 */
+                for (i = 0; i < MLAN_CFP_TABLE_SIZE_BG; i++)
+                {
+                    if (cfp_table_BG[i].code == pmadapter->otp_region->region_code)
+                    {
+                        max_tx_pwr_bg = (cfp_table_BG[i].cfp)->max_tx_power;
+                        break;
+                    }
+                }
+#if CONFIG_5GHz_SUPPORT
+                for (i = 0; i < MLAN_CFP_TABLE_SIZE_A; i++)
+                {
+                    if (cfp_table_A[i].code == pmadapter->otp_region->region_code)
+                    {
+                        max_tx_pwr_a = (cfp_table_A[i].cfp)->max_tx_power;
+                        break;
+                    }
+                }
+#endif
+                /* Update the region code and the country code in pmadapter */
+                pmadapter->region_code                = pmadapter->otp_region->region_code;
+                pmadapter->country_code[0]            = pmadapter->otp_region->country_code[0];
+                pmadapter->country_code[1]            = pmadapter->otp_region->country_code[1];
+                pmadapter->country_code[2]            = (t_u8)'\0';
+                pmadapter->domain_reg.country_code[0] = pmadapter->otp_region->country_code[0];
+                pmadapter->domain_reg.country_code[1] = pmadapter->otp_region->country_code[1];
+                pmadapter->domain_reg.country_code[2] = (t_u8)'\0';
+                pmadapter->cfp_code_bg                = pmadapter->otp_region->region_code;
+#if CONFIG_5GHz_SUPPORT
+                pmadapter->cfp_code_a = pmadapter->otp_region->region_code;
+#endif
+                break;
+            case TLV_TYPE_CHAN_ATTR_CFG:
+                /* Skip adding fw cfp tables if they already exist or
+                 * if this TLV has no set data
+                 */
+                if (*data == 0U)
+                {
+                    break;
+                }
+
+#if CONFIG_5GHz_SUPPORT
+                if ((pmadapter->cfp_otp_bg != MNULL) || (pmadapter->cfp_otp_a != MNULL))
+#else
+                if (pmadapter->cfp_otp_bg != MNULL)
+#endif
+                {
+                    break;
+                }
+
+                ret = pcb->moal_malloc(pmadapter->pmoal_handle,
+                                       pmadapter->tx_power_table_bg_rows * sizeof(chan_freq_power_t), MLAN_MEM_DEF,
+                                       (t_u8 **)(void **)&pmadapter->cfp_otp_bg);
+                if ((ret != MLAN_STATUS_SUCCESS) || (pmadapter->cfp_otp_bg == MNULL))
+                {
+                    PRINTM(MERROR,
+                           "Memory allocation for storing otp bg"
+                           " table data failed!\n");
+                    break;
+                }
+                (void)__memset(pmadapter, pmadapter->cfp_otp_bg, 0, pmadapter->tx_power_table_bg_rows * sizeof(chan_freq_power_t));
+                /* Save channel usability flags from OTP data in the fw cfp bg
+                 * table and set frequency and max_tx_power values
+                 */
+                for (i = 0; i < pmadapter->tx_power_table_bg_rows; i++)
+                {
+                    (pmadapter->cfp_otp_bg + i)->channel = *data;
+                    if (*data == 14U)
+                    {
+                        (pmadapter->cfp_otp_bg + i)->freq = 2484;
+                    }
+                    else
+                    {
+                        (pmadapter->cfp_otp_bg + i)->freq = (t_u32)2412U + (t_u32)5U * ((t_u32)*data - (t_u32)1U);
+                    }
+                    (pmadapter->cfp_otp_bg + i)->max_tx_power = max_tx_pwr_bg;
+                    data++;
+                    (pmadapter->cfp_otp_bg + i)->dynamic.flags = *data;
+                    if ((*data & NXP_CHANNEL_DFS) != 0U)
+                    {
+                        (pmadapter->cfp_otp_bg + i)->passive_scan_or_radar_detect = MTRUE;
+                    }
+                    data++;
+                }
+#if CONFIG_5GHz_SUPPORT
+                ret = pcb->moal_malloc(pmadapter->pmoal_handle,
+                                       pmadapter->tx_power_table_a_rows * sizeof(chan_freq_power_t), MLAN_MEM_DEF,
+                                       (t_u8 **)(void *)&pmadapter->cfp_otp_a);
+                if ((ret != MLAN_STATUS_SUCCESS) || (pmadapter->cfp_otp_a == MNULL))
+                {
+                    PRINTM(MERROR,
+                           "Memory allocation for storing otp a"
+                           " table data failed!\n");
+                    break;
+                }
+                (void)__memset(pmadapter, pmadapter->cfp_otp_bg, 0, pmadapter->tx_power_table_bg_rows * sizeof(chan_freq_power_t));
+                /* Save channel usability flags from OTP data in the fw cfp a
+                 * table and set frequency and max_tx_power values
+                 */
+                for (i = 0; i < pmadapter->tx_power_table_a_rows; i++)
+                {
+                    (pmadapter->cfp_otp_a + i)->channel = *data;
+                    if (*data < 183U)
+                    {
+                        /* 5GHz channels */
+                        (pmadapter->cfp_otp_a + i)->freq = (t_u32)5035U + (t_u32)5U * ((t_u32)*data - (t_u32)7U);
+                    }
+                    else
+                    {
+                        /* 4GHz channels */
+                        (pmadapter->cfp_otp_a + i)->freq = (t_u32)4915U + (t_u32)5U * ((t_u32)*data - (t_u32)183U);
+                    }
+                    (pmadapter->cfp_otp_a + i)->max_tx_power = max_tx_pwr_a;
+                    data++;
+                    (pmadapter->cfp_otp_a + i)->dynamic.flags = *data;
+                    if ((*data & NXP_CHANNEL_DFS) != 0U)
+                    {
+                        (pmadapter->cfp_otp_a + i)->passive_scan_or_radar_detect = MTRUE;
+                    }
+                    data++;
+                }
+#endif
+                break;
+            case TLV_TYPE_POWER_TABLE:
+                /* Skip adding fw power tables if this TLV has no data or
+                 * if they already exists but force reg rule is set in the otp
+                 */
+                if (*data == 0U)
+                {
+                    break;
+                }
+                if ((pmadapter->otp_region != MNULL) && (pmadapter->otp_region->force_reg != 0U) &&
+                    (pmadapter->tx_power_table_bg != MNULL))
+                {
+                    break;
+                }
+
+                /* Save the tlv data in power tables for band BG and A */
+                tmp = data;
+                i   = 0;
+                while ((i < (t_u16)pmadapter->tx_power_table_bg_rows * (t_u16)pmadapter->tx_power_table_bg_cols) &&
+                       (i < tlv_buf_len) && (*tmp != 36U))
+                {
+                    i++;
+                    tmp++;
+                }
+                if (pmadapter->tx_power_table_bg == MNULL)
+                {
+                    ret = pcb->moal_malloc(pmadapter->pmoal_handle, i, MLAN_MEM_DEF,
+                                           (t_u8 **)&pmadapter->tx_power_table_bg);
+                    if ((ret != MLAN_STATUS_SUCCESS) || (pmadapter->tx_power_table_bg == MNULL))
+                    {
+                        PRINTM(MERROR,
+                               "Memory allocation for the BG-band"
+                               " power table falied!\n");
+                        break;
+                    }
+                }
+                if (i > 0U)
+                {
+                    (void)__memcpy(pmadapter, pmadapter->tx_power_table_bg, data, i);
+                }
+                pmadapter->tx_power_table_bg_size = i;
+                data += i;
+#if CONFIG_5GHz_SUPPORT
+                i = 0;
+                while ((i < (t_u16)pmadapter->tx_power_table_a_rows * (t_u16)pmadapter->tx_power_table_a_cols) &&
+                       (i < (tlv_buf_len - pmadapter->tx_power_table_bg_size)))
+                {
+                    i++;
+                }
+                if (pmadapter->tx_power_table_a == MNULL)
+                {
+                    ret = pcb->moal_malloc(pmadapter->pmoal_handle, i, MLAN_MEM_DEF,
+                                           (t_u8 **)&pmadapter->tx_power_table_a);
+                    if ((ret != MLAN_STATUS_SUCCESS) || (pmadapter->tx_power_table_a == MNULL))
+                    {
+                        PRINTM(MERROR,
+                               "Memory allocation for the A-band"
+                               " power table failed!\n");
+                        break;
+                    }
+                }
+                if (i > 0U)
+                {
+                    (void)__memcpy(pmadapter, pmadapter->tx_power_table_a, data, i);
+                }
+                pmadapter->tx_power_table_a_size = i;
+#endif
+                break;
+            case TLV_TYPE_POWER_TABLE_ATTR:
+                pmadapter->tx_power_table_bg_rows = ((power_table_attr_t *)(void *)data)->rows_2g;
+                pmadapter->tx_power_table_bg_cols = ((power_table_attr_t *)(void *)data)->cols_2g;
+#if CONFIG_5GHz_SUPPORT
+                pmadapter->tx_power_table_a_rows = ((power_table_attr_t *)(void *)data)->rows_5g;
+                pmadapter->tx_power_table_a_cols = ((power_table_attr_t *)(void *)data)->cols_5g;
+#endif
+                break;
+            default:
+                PRINTM(MINFO, "Unexpected TLV \n");
+                break;
+        }
+        tlv_buf += (sizeof(*head) + tlv_buf_len);
+        tlv_buf_left -= ((t_u16)sizeof(*head) + tlv_buf_len);
+    }
+    if ((pmadapter->cfp_otp_bg == MNULL) || (pmadapter->tx_power_table_bg == MNULL))
+    {
+        goto out;
+    }
+    /* Set remaining flags for BG */
+    rows = (int)pmadapter->tx_power_table_bg_rows;
+    cols = (int)pmadapter->tx_power_table_bg_cols;
+
+    for (i = 0; i < (t_u16)rows; i++)
+    {
+        k = ((int)i * (int)cols) + (int)1U;
+        if (((pmadapter->cfp_otp_bg + i)->dynamic.flags & NXP_CHANNEL_DISABLED) != 0U)
+        {
+            continue;
+        }
+
+        if (pmadapter->tx_power_table_bg[k + (int)MOD_CCK] == 0U)
+        {
+            (pmadapter->cfp_otp_bg + i)->dynamic.flags |= NXP_CHANNEL_NO_CCK;
+        }
+
+        if (pmadapter->tx_power_table_bg[k + (int)MOD_OFDM_PSK] == 0U &&
+            pmadapter->tx_power_table_bg[k + (int)MOD_OFDM_QAM16] == 0U &&
+            pmadapter->tx_power_table_bg[k + (int)MOD_OFDM_QAM64] == 0U)
+        {
+            (pmadapter->cfp_otp_bg + i)->dynamic.flags |= NXP_CHANNEL_NO_OFDM;
+        }
+    }
+out:
+    LEAVE();
+}
+
+/**
+ *  @brief	This function deallocates otp cfp and power tables memory.
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ */
+void wlan_free_fw_cfp_tables(mlan_adapter *pmadapter)
+{
+    pmlan_callbacks pcb;
+
+    ENTER();
+
+    pcb = &pmadapter->callbacks;
+    if (pmadapter->otp_region != NULL)
+    {
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter->otp_region);
+    }
+    if (pmadapter->cfp_otp_bg != NULL)
+    {
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter->cfp_otp_bg);
+    }
+    if (pmadapter->tx_power_table_bg != NULL)
+    {
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter->tx_power_table_bg);
+    }
+    pmadapter->otp_region             = MNULL;
+    pmadapter->cfp_otp_bg             = MNULL;
+    pmadapter->tx_power_table_bg      = MNULL;
+    pmadapter->tx_power_table_bg_size = 0;
+#if CONFIG_5GHz_SUPPORT
+    if (pmadapter->cfp_otp_a != NULL)
+    {
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter->cfp_otp_a);
+    }
+    if (pmadapter->tx_power_table_a != NULL)
+    {
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter->tx_power_table_a);
+    }
+    pmadapter->cfp_otp_a             = MNULL;
+    pmadapter->tx_power_table_a      = MNULL;
+    pmadapter->tx_power_table_a_size = 0;
+#endif
+    LEAVE();
+}
+#endif /* OTP_CHANINFO */
+
+t_bool wlan_is_etsi_country(pmlan_adapter pmadapter, t_u8 *country_code)
+{
+    t_u8 i;
+    t_u32 meas_country_code_len = 0;
+
+    ENTER();
+    /* Look for code in EU country code table */
+    for (i = 0; i < NELEMENTS(eu_country_code_table); i++)
+    {
+        meas_country_code_len = COUNTRY_CODE_LEN - 1U;
+        if (__memcmp(pmadapter, eu_country_code_table[i], country_code, meas_country_code_len) == 0)
+        {
+            LEAVE();
+            return MTRUE;
+        }
+    }
+
+    LEAVE();
+    return MFALSE;
+}
+
+static oper_bw_chan *wlan_get_nonglobal_operclass_table(mlan_private *pmpriv, int *arraysize)
+{
+    t_u8 country_code[][COUNTRY_CODE_LEN] = {"US", "JP", "CN"};
+    int country_id                        = 0;
+    oper_bw_chan *poper_bw_chan           = MNULL;
+    t_u32 meas_country_code_len           = 0;
+
+    ENTER();
+    for (country_id = 0; country_id < 3; country_id++)
+    {
+        meas_country_code_len = COUNTRY_CODE_LEN - 1U;
+        if (__memcmp(pmpriv->adapter, pmpriv->adapter->country_code, country_code[country_id], meas_country_code_len) ==
+            0)
+        {
+            break;
+        }
+    }
+    if (country_id >= 3)
+    {
+        country_id = COUNTRY_ID_US; /*Set default to US*/
+    }
+    if (wlan_is_etsi_country(pmpriv->adapter, pmpriv->adapter->country_code))
+    {
+        country_id = COUNTRY_ID_EU; /** Country in EU */
+    }
+
+    switch (country_id)
+    {
+        case COUNTRY_ID_US:
+            poper_bw_chan = oper_bw_chan_us;
+            *arraysize    = (int)sizeof(oper_bw_chan_us);
+            break;
+        case COUNTRY_ID_JP:
+            poper_bw_chan = oper_bw_chan_jp;
+            *arraysize    = (int)sizeof(oper_bw_chan_jp);
+            break;
+        case COUNTRY_ID_CN:
+            poper_bw_chan = oper_bw_chan_cn;
+            *arraysize    = (int)sizeof(oper_bw_chan_cn);
+            break;
+        case COUNTRY_ID_EU:
+            poper_bw_chan = oper_bw_chan_eu;
+            *arraysize    = (int)sizeof(oper_bw_chan_eu);
+            break;
+        default:
+            PRINTM(MERROR, "Country not support!\n");
+            break;
+    }
+
+    LEAVE();
+    return poper_bw_chan;
+}
+
+mlan_status wlan_get_global_nonglobal_oper_class(
+    mlan_private *pmpriv, t_u8 channel, t_u8 bw, t_u8 *oper_class, t_u8 *global_op_class)
+{
+    oper_bw_chan *poper_bw_chan = MNULL;
+#if CONFIG_11AC
+    t_u8 center_freq_idx = 0;
+#endif
+    t_u8 center_freqs[] = {42, 50, 58, 106, 114, 122, 138, 155};
+    int i = 0, arraysize = 0, channum = 0, table_size = 0;
+
+    ENTER();
+    poper_bw_chan = wlan_get_nonglobal_operclass_table(pmpriv, &arraysize);
+    if (poper_bw_chan == MNULL)
+    {
+        PRINTM(MCMND, "Operating class table do not find!\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    for (i = 0; i < (int)sizeof(center_freqs); i++)
+    {
+        if (channel == center_freqs[i])
+        {
+            PRINTM(MERROR, "Invalid channel number %d!\n", channel);
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+    }
+#if CONFIG_11AC
+    if (bw == (t_u8)BW_80MHZ)
+    {
+        center_freq_idx = wlan_get_center_freq_idx(pmpriv, BAND_AAC, channel, CHANNEL_BW_80MHZ);
+        channel         = center_freq_idx;
+    }
+#endif
+    table_size = arraysize / (int)sizeof(oper_bw_chan);
+    for (i = 0; i < table_size; i++)
+    {
+        if (poper_bw_chan[i].bandwidth == bw)
+        {
+            for (channum = 0; channum < (int)(sizeof(poper_bw_chan[i].channel_list)); channum++)
+            {
+                if (poper_bw_chan[i].channel_list[channum] != (t_u8)0U &&
+                    poper_bw_chan[i].channel_list[channum] == channel)
+                {
+                    if (oper_class != MNULL)
+                    {
+                        *oper_class = poper_bw_chan[i].oper_class;
+                    }
+                    if (global_op_class != MNULL)
+                    {
+                        *global_op_class = poper_bw_chan[i].global_oper_class;
+                    }
+                    return MLAN_STATUS_SUCCESS;
+                }
+            }
+        }
+    }
+    PRINTM(MCMND, "Operating class not find!\n");
+    LEAVE();
+    return MLAN_STATUS_FAILURE;
+}
+
+int wlan_add_supported_oper_class_ie(mlan_private *pmpriv, t_u8 **pptlv_out, t_u8 curr_oper_class)
+{
+    t_u8 oper_class_us[] = {115,
+                            118,
+                            124,
+                            121,
+                            125,
+                            81,
+                            116,
+                            119,
+                            122,
+                            126,
+                            126,
+                            117,
+                            120,
+                            123,
+                            127,
+                            127,
+                            83,
+                            84
+#if CONFIG_11AC
+                            ,
+                            128,
+                            129,
+                            130
+#endif
+    };
+    t_u8 oper_class_eu[] = {115,
+                            118,
+                            121,
+                            81,
+                            116,
+                            119,
+                            122,
+                            117,
+                            120,
+                            123,
+                            83,
+                            84,
+                            125
+#if CONFIG_11AC
+                            ,
+                            128,
+                            129,
+                            130
+#endif
+    };
+    t_u8 oper_class_jp[] = {115,
+                            81,
+                            82,
+                            118,
+                            118,
+                            121,
+                            121,
+                            116,
+                            119,
+                            119,
+                            122,
+                            122,
+                            117,
+                            120,
+                            120,
+                            123,
+                            123,
+                            83,
+                            84,
+                            121
+#if CONFIG_11AC
+                            ,
+                            128,
+                            129,
+                            130
+#endif
+    };
+    t_u8 oper_class_cn[] = {115,
+                            118,
+                            125,
+                            116,
+                            119,
+                            126,
+                            81,
+                            83,
+                            84
+#if CONFIG_11AC
+                            ,
+                            128,
+                            129,
+                            130
+#endif
+    };
+    t_u8 country_code[][COUNTRY_CODE_LEN] = {"US", "JP", "CN"};
+    int country_id = 0, ret = 0;
+    MrvlIETypes_SuppOperClass_t *poper_class = MNULL;
+    t_u32 meas_country_code_len              = 0;
+
+    ENTER();
+
+    for (country_id = 0; country_id < 3; country_id++)
+    {
+        meas_country_code_len = COUNTRY_CODE_LEN - 1U;
+        if (__memcmp(pmpriv->adapter, pmpriv->adapter->country_code, country_code[country_id], meas_country_code_len) ==
+            0)
+        {
+            break;
+        }
+    }
+    if (country_id >= 3)
+    {
+        country_id = COUNTRY_ID_US; /*Set default to US*/
+    }
+    if (wlan_is_etsi_country(pmpriv->adapter, pmpriv->adapter->country_code))
+    {
+        country_id = COUNTRY_ID_EU; /** Country in EU */
+    }
+    poper_class = (MrvlIETypes_SuppOperClass_t *)(void *)*pptlv_out;
+    (void)__memset(pmpriv->adapter, poper_class, 0, sizeof(MrvlIETypes_SuppOperClass_t));
+    poper_class->header.type = wlan_cpu_to_le16(REGULATORY_CLASS);
+    if (country_id == COUNTRY_ID_US)
+    {
+        poper_class->header.len = (t_u16)sizeof(oper_class_us);
+        (void)__memcpy(pmpriv->adapter, &poper_class->oper_class, oper_class_us, sizeof(oper_class_us));
+    }
+    else if (country_id == COUNTRY_ID_JP)
+    {
+        poper_class->header.len = (t_u16)sizeof(oper_class_jp);
+        (void)__memcpy(pmpriv->adapter, &poper_class->oper_class, oper_class_jp, sizeof(oper_class_jp));
+    }
+    else if (country_id == COUNTRY_ID_CN)
+    {
+        poper_class->header.len = (t_u16)sizeof(oper_class_cn);
+        (void)__memcpy(pmpriv->adapter, &poper_class->oper_class, oper_class_cn, sizeof(oper_class_cn));
+    }
+    else if (country_id == COUNTRY_ID_EU)
+    {
+        poper_class->header.len = (t_u16)sizeof(oper_class_eu);
+        (void)__memcpy(pmpriv->adapter, &poper_class->oper_class, oper_class_eu, sizeof(oper_class_eu));
+    }
+    else
+    {
+        /* Do nothing */
+    }
+    poper_class->current_oper_class = curr_oper_class;
+    poper_class->header.len += (t_u16)sizeof(poper_class->current_oper_class);
+    DBG_HEXDUMP(MCMD_D, "Operating class", (t_u8 *)poper_class, sizeof(MrvlIEtypesHeader_t) + poper_class->header.len);
+    ret = (int)sizeof(MrvlIEtypesHeader_t) + (int)poper_class->header.len;
+    *pptlv_out += ret;
+    poper_class->header.len = wlan_cpu_to_le16(poper_class->header.len);
+
+    LEAVE();
+    return ret;
+}
+
+#if CONFIG_ECSA
+/**
+ *  @brief Check validation of given channel and oper class
+ *
+ *  @param pmpriv             A pointer to mlan_private structure
+ *  @param channel            Channel number
+ *  @param oper_class         operating class
+ *
+ *  @return                   MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_check_operclass_validation(mlan_private *pmpriv, t_u8 channel, t_u8 oper_class)
+{
+    int arraysize = 0, i = 0, channum = 0;
+    oper_bw_chan *poper_bw_chan = MNULL;
+#if CONFIG_11AC
+    t_u8 center_freq_idx = 0;
+#endif
+    t_u8 center_freqs[] = {42, 50, 58, 106, 114, 122, 138, 155};
+
+    ENTER();
+
+    for (i = 0; i < (int)sizeof(center_freqs); i++)
+    {
+        if (channel == center_freqs[i])
+        {
+            PRINTM(MERROR, "Invalid channel number %d!\n", channel);
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+    }
+    if (oper_class <= 0 || oper_class > 130)
+    {
+        PRINTM(MERROR, "Invalid operating class!\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+#if CONFIG_11AC
+    if (oper_class >= 128)
+    {
+        center_freq_idx = wlan_get_center_freq_idx(pmpriv, BAND_AAC, channel, CHANNEL_BW_80MHZ);
+        channel         = center_freq_idx;
+    }
+#endif
+    poper_bw_chan = wlan_get_nonglobal_operclass_table(pmpriv, &arraysize);
+
+    if (!poper_bw_chan)
+    {
+        PRINTM(MCMND, "Operating class table do not find!\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    for (i = 0; i < (int)(arraysize / sizeof(oper_bw_chan)); i++)
+    {
+        if (poper_bw_chan[i].oper_class == oper_class || poper_bw_chan[i].global_oper_class == oper_class)
+        {
+            for (channum = 0; channum < (int)sizeof(poper_bw_chan[i].channel_list); channum++)
+            {
+                if (poper_bw_chan[i].channel_list[channum] && poper_bw_chan[i].channel_list[channum] == channel)
+                {
+                    LEAVE();
+                    return MLAN_STATUS_SUCCESS;
+                }
+            }
+        }
+    }
+
+    PRINTM(MCMND, "Operating class %d do not match channel %d!\n", oper_class, channel);
+    LEAVE();
+    return MLAN_STATUS_FAILURE;
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_cmdevt.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_cmdevt.c
new file mode 100644
index 0000000000..76e835325a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_cmdevt.c
@@ -0,0 +1,2386 @@
+/** @file mlan_cmdevt.c
+ *
+ *  @brief  This file provides the handling of CMD/EVENT in MLAN
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*************************************************************
+Change Log:
+    05/12/2009: initial version
+************************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/*******************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+
+
+/**
+ *  @brief This function prepare the command before sending to firmware.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd_no       Command number
+ *  @param cmd_action   Command action: GET or SET
+ *  @param cmd_oid      Cmd oid: treated as sub command
+ *  @param pioctl_buf   A pointer to MLAN IOCTL Request buffer
+ *  @param pdata_buf    A pointer to information buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_prepare_cmd(IN mlan_private *pmpriv,
+                             IN t_u16 cmd_no,
+                             IN t_u16 cmd_action,
+                             IN t_u32 cmd_oid,
+                             IN t_void *pioctl_buf,
+                             IN t_void *pdata_buf)
+{
+    /* Note: We send only one command at a time and do not need the linked
+       list based implementation used here. So we will call our own
+       implementation here.
+    */
+
+    return wifi_prepare_and_send_cmd(pmpriv, cmd_no, cmd_action, cmd_oid, pioctl_buf, pdata_buf, pmpriv->bss_type,
+                                     NULL);
+}
+
+#if CONFIG_11AX
+/**
+ *  @brief Fetch bitmap rate index
+ *
+ *  @param rate_scope  A pointer to MrvlRateScope_t
+ *
+ *  @return            bitmap rate index
+ */
+static t_u16 wlan_get_bitmap_index(MrvlRateScope_t *rate_scope)
+{
+    t_u16 index = 0;
+    if (rate_scope != MNULL)
+    {
+        index += NELEMENTS(rate_scope->ht_mcs_rate_bitmap);
+        index += NELEMENTS(rate_scope->vht_mcs_rate_bitmap);
+    }
+    return index;
+}
+#endif
+
+/**
+ *  @brief This function prepares command of power mode
+ *
+ *  @param pmpriv		A pointer to mlan_private structure
+ *  @param cmd	   		A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param ps_bitmap    PS bitmap
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_enh_power_mode(pmlan_private pmpriv,
+                                    IN HostCmd_DS_COMMAND *cmd,
+                                    IN ENH_PS_MODES cmd_action,
+                                    IN t_u16 ps_bitmap,
+                                    IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_PS_MODE_ENH *psmode_enh = &cmd->params.psmode_enh;
+    t_u8 *tlv                                 = MNULL;
+    t_u16 cmd_size                            = 0;
+
+    ENTER();
+
+    PRINTM(MCMND, "PS Command: action = 0x%x, bitmap = 0x%x\n", cmd_action, ps_bitmap);
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_PS_MODE_ENH);
+    if (cmd_action == DIS_AUTO_PS)
+    {
+        psmode_enh->action           = (ENH_PS_MODES)(wlan_cpu_to_le16(DIS_AUTO_PS));
+        psmode_enh->params.ps_bitmap = wlan_cpu_to_le16(ps_bitmap);
+        cmd->size                    = wlan_cpu_to_le16(S_DS_GEN + AUTO_PS_FIX_SIZE);
+    }
+#if (CONFIG_WNM_PS)
+    else if (cmd_action == DIS_WNM_PS)
+    {
+        psmode_enh->action           = (ENH_PS_MODES)(wlan_cpu_to_le16(DIS_WNM_PS));
+        psmode_enh->params.ps_bitmap = wlan_cpu_to_le16(ps_bitmap);
+        cmd->size                    = wlan_cpu_to_le16(S_DS_GEN + AUTO_PS_FIX_SIZE);
+    }
+#endif
+    else if (cmd_action == GET_PS)
+    {
+        psmode_enh->action           = (ENH_PS_MODES)(wlan_cpu_to_le16(GET_PS));
+        psmode_enh->params.ps_bitmap = wlan_cpu_to_le16(ps_bitmap);
+        cmd->size                    = wlan_cpu_to_le16(S_DS_GEN + AUTO_PS_FIX_SIZE);
+    }
+    else if (cmd_action == EXT_PS_PARAM)
+    {
+        psmode_enh->action                    = wlan_cpu_to_le16(EXT_PS_PARAM);
+        psmode_enh->params.ext_param.reserved = 0;
+        cmd->size                             = wlan_cpu_to_le16(S_DS_GEN + sizeof(t_u16) + sizeof(ext_ps_param));
+        psmode_enh->params.ext_param.param.header.type = wlan_cpu_to_le16(TLV_TYPE_PS_EXT_PARAM);
+        psmode_enh->params.ext_param.param.header.len  = sizeof(t_u32);
+        psmode_enh->params.ext_param.param.mode        = wlan_cpu_to_le32(*((t_u32 *)pdata_buf));
+    }
+    else if (cmd_action == EN_AUTO_PS)
+    {
+        psmode_enh->action                   = (ENH_PS_MODES)(wlan_cpu_to_le16(EN_AUTO_PS));
+        psmode_enh->params.auto_ps.ps_bitmap = wlan_cpu_to_le16(ps_bitmap);
+        cmd_size                             = S_DS_GEN + AUTO_PS_FIX_SIZE;
+        tlv                                  = (t_u8 *)cmd + cmd_size;
+        if ((ps_bitmap & BITMAP_STA_PS) != 0U)
+        {
+            pmlan_adapter pmadapter        = pmpriv->adapter;
+            MrvlIEtypes_ps_param_t *ps_tlv = (MrvlIEtypes_ps_param_t *)(void *)tlv;
+            ps_param *ps_mode              = (ps_param *)&ps_tlv->param;
+            ps_tlv->header.type            = wlan_cpu_to_le16(TLV_TYPE_PS_PARAM);
+            ps_tlv->header.len = wlan_cpu_to_le16(sizeof(MrvlIEtypes_ps_param_t) - sizeof(MrvlIEtypesHeader_t));
+            cmd_size += (t_u16)sizeof(MrvlIEtypes_ps_param_t);
+            tlv += (t_u8)sizeof(MrvlIEtypes_ps_param_t);
+            ps_mode->null_pkt_interval     = wlan_cpu_to_le16(pmadapter->null_pkt_interval);
+            ps_mode->multiple_dtims        = wlan_cpu_to_le16(pmadapter->multiple_dtim);
+            ps_mode->bcn_miss_timeout      = wlan_cpu_to_le16(pmadapter->bcn_miss_time_out);
+            ps_mode->local_listen_interval = wlan_cpu_to_le16(pmadapter->local_listen_interval);
+            ps_mode->adhoc_wake_period     = wlan_cpu_to_le16(pmadapter->adhoc_awake_period);
+            ps_mode->delay_to_ps           = wlan_cpu_to_le16(pmadapter->delay_to_ps);
+            ps_mode->mode                  = wlan_cpu_to_le16(pmadapter->enhanced_ps_mode);
+        }
+
+        if ((ps_bitmap & BITMAP_AUTO_DS) != 0U)
+        {
+            MrvlIEtypes_auto_ds_param_t *auto_ps_tlv = (MrvlIEtypes_auto_ds_param_t *)(void *)tlv;
+            auto_ds_param *auto_ds                   = (auto_ds_param *)&auto_ps_tlv->param;
+            t_u16 idletime                           = 0;
+            auto_ps_tlv->header.type                 = wlan_cpu_to_le16(TLV_TYPE_AUTO_DS_PARAM);
+            auto_ps_tlv->header.len =
+                wlan_cpu_to_le16(sizeof(MrvlIEtypes_auto_ds_param_t) - sizeof(MrvlIEtypesHeader_t));
+            cmd_size += (t_u16)sizeof(MrvlIEtypes_auto_ds_param_t);
+            tlv += (t_u8)sizeof(MrvlIEtypes_auto_ds_param_t);
+            if (pdata_buf != NULL)
+            {
+                idletime = ((mlan_ds_auto_ds *)pdata_buf)->idletime;
+            }
+            auto_ds->deep_sleep_timeout = wlan_cpu_to_le16(idletime);
+        }
+        /* fixme :
+         * This macro is not defined as if now
+         * once full fledged support is added in the SDK
+         * for UAP this macro will be defined and
+         * line below will be uncommented*/
+        /* #if defined(UAP_SUPPORT)*/
+        if ((pdata_buf != MNULL) && (ps_bitmap & (BITMAP_UAP_INACT_PS | BITMAP_UAP_DTIM_PS)))
+        {
+            mlan_ds_ps_mgmt *ps_mgmt                   = (mlan_ds_ps_mgmt *)pdata_buf;
+            MrvlIEtypes_sleep_param_t *sleep_tlv       = MNULL;
+            MrvlIEtypes_inact_sleep_param_t *inact_tlv = MNULL;
+            if ((ps_mgmt->flags & PS_FLAG_SLEEP_PARAM) != 0U)
+            {
+                sleep_tlv              = (MrvlIEtypes_sleep_param_t *)(void *)tlv;
+                sleep_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_AP_SLEEP_PARAM);
+                sleep_tlv->header.len =
+                    wlan_cpu_to_le16(sizeof(MrvlIEtypes_sleep_param_t) - sizeof(MrvlIEtypesHeader_t));
+                sleep_tlv->ctrl_bitmap = wlan_cpu_to_le32(ps_mgmt->sleep_param.ctrl_bitmap);
+                sleep_tlv->min_sleep   = wlan_cpu_to_le32(ps_mgmt->sleep_param.min_sleep);
+                sleep_tlv->max_sleep   = wlan_cpu_to_le32(ps_mgmt->sleep_param.max_sleep);
+                cmd_size += (t_u16)sizeof(MrvlIEtypes_sleep_param_t);
+                tlv += (t_u8)sizeof(MrvlIEtypes_sleep_param_t);
+            }
+            if ((ps_mgmt->flags & PS_FLAG_INACT_SLEEP_PARAM) != 0U)
+            {
+                inact_tlv              = (MrvlIEtypes_inact_sleep_param_t *)(void *)tlv;
+                inact_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_AP_INACT_SLEEP_PARAM);
+                inact_tlv->header.len =
+                    wlan_cpu_to_le16(sizeof(MrvlIEtypes_inact_sleep_param_t) - sizeof(MrvlIEtypesHeader_t));
+                inact_tlv->inactivity_to = wlan_cpu_to_le32(ps_mgmt->inact_param.inactivity_to);
+                inact_tlv->min_awake     = wlan_cpu_to_le32(ps_mgmt->inact_param.min_awake);
+                inact_tlv->max_awake     = wlan_cpu_to_le32(ps_mgmt->inact_param.max_awake);
+                cmd_size += (t_u16)sizeof(MrvlIEtypes_inact_sleep_param_t);
+                tlv += (t_u8)sizeof(MrvlIEtypes_inact_sleep_param_t);
+            }
+        }
+        /*#endif*/
+        cmd->size = wlan_cpu_to_le16(cmd_size);
+    }
+#if (CONFIG_WNM_PS)
+    else if (cmd_action == EN_WNM_PS)
+    {
+        psmode_enh->action                   = wlan_cpu_to_le16(EN_WNM_PS);
+        psmode_enh->params.auto_ps.ps_bitmap = wlan_cpu_to_le16(ps_bitmap);
+        cmd_size                             = S_DS_GEN + AUTO_PS_FIX_SIZE;
+        tlv                                  = (t_u8 *)cmd + cmd_size;
+        if ((ps_bitmap & BITMAP_STA_PS) != 0)
+        {
+            if (pdata_buf != NULL)
+            {
+                pmlan_adapter pmadapter                = pmpriv->adapter;
+                MrvlIEtypes_wnm_ps_param_t *wnm_ps_tlv = (MrvlIEtypes_wnm_ps_param_t *)tlv;
+                wnm_ps_param *wnm_ps                   = (wnm_ps_param *)&wnm_ps_tlv->param;
+                t_u16 internal                         = 0;
+                wnm_ps_tlv->header.type                = wlan_cpu_to_le16(TLV_TYPE_WNM_PARAM);
+                wnm_ps_tlv->header.len =
+                    wlan_cpu_to_le16(sizeof(MrvlIEtypes_wnm_ps_param_t) - sizeof(MrvlIEtypesHeader_t));
+                cmd_size += sizeof(MrvlIEtypes_wnm_ps_param_t);
+                tlv += sizeof(MrvlIEtypes_wnm_ps_param_t);
+                internal                      = *(t_u32 *)pdata_buf;
+                wnm_ps->action                = 0;
+                wnm_ps->null_pkt_interval     = wlan_cpu_to_le16(pmadapter->null_pkt_interval);
+                wnm_ps->bcn_miss_timeout      = wlan_cpu_to_le16(pmadapter->bcn_miss_time_out);
+                wnm_ps->local_listen_interval = wlan_cpu_to_le16(pmadapter->local_listen_interval);
+                wnm_ps->ps_mode               = wlan_cpu_to_le16(pmadapter->enhanced_ps_mode);
+                wnm_ps->delay_to_ps           = DELAY_TO_PS_WNM;
+                wnm_ps->wnm_sleep_interval    = wlan_cpu_to_le16(internal);
+            }
+        }
+        cmd->size = wlan_cpu_to_le16(cmd_size);
+    }
+#endif
+    else
+    { /* Do Nothing */
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+#ifdef SD8801
+mlan_status wlan_ret_802_11_tx_rate_query(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN void *pioctl)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    wifi_ds_rate *rate      = MNULL;
+    ENTER();
+
+    pmpriv->tx_rate = resp->params.tx_rate.tx_rate;
+    pmpriv->tx_htinfo = resp->params.tx_rate.ht_info;
+    if (!pmpriv->is_data_rate_auto)
+    {
+        pmpriv->data_rate = wlan_index_to_data_rate(pmadapter, pmpriv->tx_rate, pmpriv->tx_htinfo);
+    }
+
+    if (pioctl)
+    {
+        rate = (wifi_ds_rate *)pioctl;
+        if (rate->sub_command == WIFI_DS_RATE_CFG)
+        {
+#if 0
+            if(rate->param.rate_cfg.rate_type == MLAN_RATE_INDEX) {
+#endif
+            if (pmpriv->tx_htinfo & MBIT(0))
+                rate->param.rate_cfg.rate = pmpriv->tx_rate + MLAN_RATE_INDEX_MCS0;
+            else
+                /* For HostCmd_CMD_802_11_TX_RATE_QUERY, there is a hole in rate table
+                 * between HR/DSSS and OFDM rates, so minus 1 for OFDM rate index */
+                rate->param.rate_cfg.rate =
+                    (pmpriv->tx_rate > MLAN_RATE_INDEX_OFDM0) ? pmpriv->tx_rate - 1 : pmpriv->tx_rate;
+#if 0
+            }
+            else {
+                    rate->param.rate_cfg.rate = wlan_index_to_data_rate(pmadapter, pmpriv->tx_rate,
+                                                pmpriv->tx_htinfo);
+            }
+#endif
+        }
+        else if (rate->sub_command == WIFI_DS_GET_DATA_RATE)
+        {
+            if (pmpriv->tx_htinfo & MBIT(0))
+            {
+                rate->param.data_rate.tx_data_rate = pmpriv->tx_rate + MLAN_RATE_INDEX_MCS0;
+                if (pmpriv->tx_htinfo & MBIT(1))
+                    rate->param.data_rate.tx_bw = MLAN_HT_BW40;
+                else
+                    rate->param.data_rate.tx_bw = MLAN_HT_BW20;
+                if (pmpriv->tx_htinfo & MBIT(2))
+                    rate->param.data_rate.tx_gi = MLAN_HT_SGI;
+                else
+                    rate->param.data_rate.tx_gi = MLAN_HT_LGI;
+            }
+            else
+                /* For HostCmd_CMD_802_11_TX_RATE_QUERY, there is a hole in rate table
+                   between HR/DSSS and OFDM rates, so minus 1 for OFDM rate index */
+                rate->param.data_rate.tx_data_rate =
+                    (pmpriv->tx_rate > MLAN_RATE_INDEX_OFDM0) ? pmpriv->tx_rate - 1 : pmpriv->tx_rate;
+            if (pmpriv->rxpd_htinfo & MBIT(0))
+            {
+                rate->param.data_rate.rx_data_rate = pmpriv->rxpd_rate + MLAN_RATE_INDEX_MCS0;
+                if (pmpriv->rxpd_htinfo & MBIT(1))
+                    rate->param.data_rate.rx_bw = MLAN_HT_BW40;
+                else
+                    rate->param.data_rate.rx_bw = MLAN_HT_BW20;
+                if (pmpriv->rxpd_htinfo & MBIT(2))
+                    rate->param.data_rate.rx_gi = MLAN_HT_SGI;
+                else
+                    rate->param.data_rate.rx_gi = MLAN_HT_LGI;
+            }
+            else
+                /* For rate index in RxPD, there is a hole in rate table
+                   between HR/DSSS and OFDM rates, so minus 1 for OFDM rate index */
+                rate->param.data_rate.rx_data_rate =
+                    (pmpriv->rxpd_rate > MLAN_RATE_INDEX_OFDM0) ? pmpriv->rxpd_rate - 1 : pmpriv->rxpd_rate;
+        }
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#else
+/**
+ *  @brief This function handles the command response of tx rate query
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_802_11_tx_rate_query(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN void *pioctl)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    wifi_ds_rate *rate      = MNULL;
+    ENTER();
+
+    pmpriv->tx_rate      = resp->params.tx_rate.tx_rate;
+    pmpriv->tx_rate_info = resp->params.tx_rate.tx_rate_info;
+
+#if CONFIG_11AX
+    if ((mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_HE)
+        pmpriv->ext_tx_rate_info = resp->params.tx_rate.ext_tx_rate_info;
+#endif
+
+    if (!pmpriv->is_data_rate_auto)
+    {
+        pmpriv->data_rate = wlan_index_to_data_rate(pmadapter, pmpriv->tx_rate, pmpriv->tx_rate_info
+#if CONFIG_11AX
+                                                    ,
+                                                    pmpriv->ext_tx_rate_info
+#endif
+        );
+    }
+
+    if (pioctl != NULL)
+    {
+        rate = (wifi_ds_rate *)pioctl;
+        if (rate->sub_command == WIFI_DS_RATE_CFG)
+        {
+#if 0
+            if(rate->param.rate_cfg.rate_type == MLAN_RATE_INDEX) {
+#endif
+#if CONFIG_11AC
+            if ((mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_VHT
+#if CONFIG_11AX
+                || ((mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_HE)
+#endif
+            )
+            {
+                /* VHT rate */
+                rate->param.rate_cfg.rate = (t_u32)((pmpriv->tx_rate) & 0xF);
+            }
+            else
+#endif
+                if ((mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_HT)
+            {
+                /* HT rate */
+                rate->param.rate_cfg.rate = pmpriv->tx_rate + MLAN_RATE_INDEX_MCS0;
+            }
+            else
+            {
+                /* LG rate */
+                /* For HostCmd_CMD_802_11_TX_RATE_QUERY,
+                 * there is a hole (0x4) in rate table
+                 * between HR/DSSS and OFDM rates,
+                 * so minus 1 for OFDM rate index */
+                rate->param.rate_cfg.rate =
+                    (pmpriv->tx_rate > MLAN_RATE_INDEX_OFDM0) ? pmpriv->tx_rate - 1U : pmpriv->tx_rate;
+            }
+#if 0
+            }
+            else {
+                /* rate_type = MLAN_RATE_VALUE */
+                rate->param.rate_cfg.rate = wlan_index_to_data_rate(pmadapter,
+                                                pmpriv->tx_rate,
+                                                pmpriv->tx_rate_info);
+            }
+#endif
+        }
+        else if (rate->sub_command == WIFI_DS_GET_DATA_RATE)
+        {
+            /* Tx rate info */
+#if CONFIG_11AC
+            if ((mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_VHT
+#if CONFIG_11AX
+                || (mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_HE
+#endif
+            )
+            {
+                /* VHT/HE rate */
+                rate->param.data_rate.tx_rate_format = (mlan_rate_format)(pmpriv->tx_rate_info & 0x3U);
+                rate->param.data_rate.tx_bw          = (t_u32)((pmpriv->tx_rate_info & 0xC) >> 2);
+
+#if CONFIG_11AX
+                if ((mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_HE)
+                    rate->param.data_rate.tx_gi =
+                        (pmpriv->tx_rate_info & 0x10) >> 4 | (pmpriv->tx_rate_info & 0x80) >> 6;
+                else
+#endif
+                    rate->param.data_rate.tx_gi = (t_u32)((pmpriv->tx_rate_info & 0x10) >> 4);
+                rate->param.data_rate.tx_nss       = ((pmpriv->tx_rate) >> 4) & 0x03;
+                rate->param.data_rate.tx_mcs_index = (t_u32)((pmpriv->tx_rate) & 0xF);
+                rate->param.data_rate.tx_data_rate =
+                    wlan_index_to_data_rate(pmadapter, pmpriv->tx_rate, pmpriv->tx_rate_info
+#if CONFIG_11AX
+                                            ,
+                                            pmpriv->ext_tx_rate_info
+#endif
+                    );
+            }
+            else
+#endif
+                if ((mlan_rate_format)(pmpriv->tx_rate_info & 0x3U) == MLAN_RATE_FORMAT_HT)
+            {
+                /* HT rate */
+                rate->param.data_rate.tx_rate_format = MLAN_RATE_FORMAT_HT;
+                rate->param.data_rate.tx_bw          = (pmpriv->tx_rate_info & 0xCU) >> 2U;
+                rate->param.data_rate.tx_gi          = (pmpriv->tx_rate_info & 0x10U) >> 4U;
+                rate->param.data_rate.tx_mcs_index   = pmpriv->tx_rate;
+                rate->param.data_rate.tx_data_rate =
+                    wlan_index_to_data_rate(pmadapter, pmpriv->tx_rate, pmpriv->tx_rate_info
+#if CONFIG_11AX
+                                            ,
+                                            pmpriv->ext_tx_rate_info
+#endif
+                    );
+            }
+            else
+            {
+                /* LG rate */
+                rate->param.data_rate.tx_rate_format = MLAN_RATE_FORMAT_LG;
+                /* For HostCmd_CMD_802_11_TX_RATE_QUERY,
+                 * there is a hole in rate table
+                 * between HR/DSSS and OFDM rates,
+                 * so minus 1 for OFDM rate index */
+                rate->param.data_rate.tx_data_rate =
+                    (pmpriv->tx_rate > MLAN_RATE_INDEX_OFDM0) ? pmpriv->tx_rate - 1U : pmpriv->tx_rate;
+            }
+
+            /* Rx rate info */
+#if CONFIG_11AC
+            if ((mlan_rate_format)(pmpriv->rxpd_rate_info & 0x3U) == MLAN_RATE_FORMAT_VHT
+#if CONFIG_11AX
+                || (pmpriv->rxpd_rate_info & 0x3) == MLAN_RATE_FORMAT_HE
+#endif
+            )
+            {
+                /* VHT/HE rate */
+                rate->param.data_rate.rx_rate_format = (mlan_rate_format)(pmpriv->rxpd_rate_info & 0x3);
+                rate->param.data_rate.rx_bw          = (t_u32)((pmpriv->rxpd_rate_info & 0xC) >> 2);
+
+#if CONFIG_11AX
+                if ((pmpriv->rxpd_rate_info & 0x3) == MLAN_RATE_FORMAT_HE)
+                    rate->param.data_rate.rx_gi =
+                        (pmpriv->rxpd_rate_info & 0x10) >> 4 | (pmpriv->rxpd_rate_info & 0x80) >> 6;
+                else
+#endif
+                    rate->param.data_rate.rx_gi = (t_u32)((pmpriv->rxpd_rate_info & 0x10) >> 4);
+                rate->param.data_rate.rx_nss       = ((pmpriv->rxpd_rate) >> 4) & 0x3;
+                rate->param.data_rate.rx_mcs_index = (t_u32)((pmpriv->rxpd_rate) & 0xF);
+                rate->param.data_rate.rx_data_rate =
+                    wlan_index_to_data_rate(pmadapter, pmpriv->rxpd_rate, pmpriv->rxpd_rate_info
+#if CONFIG_11AX
+                                            ,
+                                            pmpriv->ext_tx_rate_info
+#endif
+                    );
+            }
+            else
+#endif
+                if ((pmpriv->rxpd_rate_info & 0x3) == MLAN_RATE_FORMAT_HT)
+            {
+                /* HT rate */
+                rate->param.data_rate.rx_rate_format = MLAN_RATE_FORMAT_HT;
+                rate->param.data_rate.rx_bw          = (pmpriv->rxpd_rate_info & 0xCU) >> 2U;
+                rate->param.data_rate.rx_gi          = (pmpriv->rxpd_rate_info & 0x10U) >> 4U;
+                rate->param.data_rate.rx_mcs_index   = pmpriv->rxpd_rate;
+                rate->param.data_rate.rx_data_rate =
+                    wlan_index_to_data_rate(pmadapter, pmpriv->rxpd_rate, pmpriv->rxpd_rate_info
+#if CONFIG_11AX
+                                            ,
+                                            pmpriv->ext_tx_rate_info
+#endif
+                    );
+            }
+            else
+            {
+                /* LG rate */
+                rate->param.data_rate.rx_rate_format = MLAN_RATE_FORMAT_LG;
+                /* For rate index in RxPD,
+                 * there is a hole in rate table
+                 * between HR/DSSS and OFDM rates,
+                 * so minus 1 for OFDM rate index */
+                rate->param.data_rate.rx_data_rate =
+                    (t_u32)((pmpriv->rxpd_rate > MLAN_RATE_INDEX_OFDM0) ? pmpriv->rxpd_rate - 1 : pmpriv->rxpd_rate);
+            }
+        }
+        else
+        { /* Do Nothing */
+        }
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/**
+ *  @brief This function prepares command of tx_rate_cfg.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_tx_rate_cfg(IN pmlan_private pmpriv,
+                                 IN HostCmd_DS_COMMAND *cmd,
+                                 IN t_u16 cmd_action,
+                                 IN t_void *pdata_buf,
+                                 IN mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_TX_RATE_CFG *rate_cfg = (HostCmd_DS_TX_RATE_CFG *)&cmd->params.tx_rate_cfg;
+    MrvlRateScope_t *rate_scope;
+    MrvlRateDropPattern_t *rate_drop;
+#if CONFIG_11AX
+    MrvlIETypes_rate_setting_t *rate_setting_tlv;
+    mlan_ds_rate *ds_rate = MNULL;
+#endif
+    t_u16 *pbitmap_rates  = (t_u16 *)pdata_buf;
+
+    t_u32 i;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_TX_RATE_CFG);
+
+    rate_cfg->action    = wlan_cpu_to_le16(cmd_action);
+    rate_cfg->cfg_index = 0;
+
+    rate_scope = (MrvlRateScope_t *)(void *)((t_u8 *)rate_cfg + sizeof(HostCmd_DS_TX_RATE_CFG));
+    // coverity[overrun-local:SUPPRESS]
+    rate_scope->type   = wlan_cpu_to_le16(TLV_TYPE_RATE_SCOPE);
+    rate_scope->length = wlan_cpu_to_le16(sizeof(MrvlRateScope_t) - sizeof(MrvlIEtypesHeader_t));
+    if (pbitmap_rates != MNULL)
+    {
+        rate_scope->hr_dsss_rate_bitmap = wlan_cpu_to_le16(pbitmap_rates[0]);
+        rate_scope->ofdm_rate_bitmap    = wlan_cpu_to_le16(pbitmap_rates[1]);
+        for (i = 0; i < NELEMENTS(rate_scope->ht_mcs_rate_bitmap); i++)
+        {
+            rate_scope->ht_mcs_rate_bitmap[i] = wlan_cpu_to_le16(pbitmap_rates[2U + i]);
+        }
+#if CONFIG_11AC
+        for (i = 0; i < NELEMENTS(rate_scope->vht_mcs_rate_bitmap); i++)
+        {
+            rate_scope->vht_mcs_rate_bitmap[i] =
+                wlan_cpu_to_le16(pbitmap_rates[2U + NELEMENTS(rate_scope->ht_mcs_rate_bitmap) + i]);
+        }
+#endif
+#if CONFIG_11AX
+        if (IS_FW_SUPPORT_11AX(pmpriv->adapter))
+        {
+            for (i = 0; i < NELEMENTS(rate_scope->he_mcs_rate_bitmap); i++)
+                rate_scope->he_mcs_rate_bitmap[i] =
+                    wlan_cpu_to_le16(pbitmap_rates[2U + wlan_get_bitmap_index(rate_scope) + i]);
+        }
+        else
+        {
+            rate_scope->length = wlan_cpu_to_le16(sizeof(MrvlRateScope_t) - sizeof(rate_scope->he_mcs_rate_bitmap) -
+                                                  sizeof(MrvlIEtypesHeader_t));
+        }
+#endif
+    }
+    else
+    {
+        rate_scope->hr_dsss_rate_bitmap = wlan_cpu_to_le16(pmpriv->bitmap_rates[0]);
+        rate_scope->ofdm_rate_bitmap    = wlan_cpu_to_le16(pmpriv->bitmap_rates[1]);
+        for (i = 0; i < NELEMENTS(rate_scope->ht_mcs_rate_bitmap); i++)
+        {
+            rate_scope->ht_mcs_rate_bitmap[i] = wlan_cpu_to_le16(pmpriv->bitmap_rates[2U + i]);
+        }
+#if CONFIG_11AC
+        for (i = 0; i < NELEMENTS(rate_scope->vht_mcs_rate_bitmap); i++)
+        {
+            rate_scope->vht_mcs_rate_bitmap[i] =
+                wlan_cpu_to_le16(pmpriv->bitmap_rates[2U + NELEMENTS(rate_scope->ht_mcs_rate_bitmap) + i]);
+        }
+#endif
+#if CONFIG_11AX
+        if (IS_FW_SUPPORT_11AX(pmpriv->adapter))
+        {
+            for (i = 0; i < NELEMENTS(rate_scope->he_mcs_rate_bitmap); i++)
+                rate_scope->he_mcs_rate_bitmap[i] =
+                    wlan_cpu_to_le16(pmpriv->bitmap_rates[2U + wlan_get_bitmap_index(rate_scope) + i]);
+        }
+        else
+        {
+            rate_scope->length = wlan_cpu_to_le16(sizeof(MrvlRateScope_t) - sizeof(rate_scope->he_mcs_rate_bitmap) -
+                                                  sizeof(MrvlIEtypesHeader_t));
+        }
+#endif
+    }
+
+    rate_drop                 = (MrvlRateDropPattern_t *)(void *)((t_u8 *)rate_scope + sizeof(MrvlRateScope_t));
+    rate_drop->type           = wlan_cpu_to_le16(TLV_TYPE_RATE_DROP_PATTERN);
+    rate_drop->length         = wlan_cpu_to_le16(sizeof(rate_drop->rate_drop_mode));
+    rate_drop->rate_drop_mode = 0;
+
+    cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_TX_RATE_CFG) + sizeof(MrvlRateScope_t) +
+                                 sizeof(MrvlRateDropPattern_t));
+
+#if CONFIG_11AX
+    if (pioctl_buf)
+    {
+        ds_rate          = (mlan_ds_rate *)pioctl_buf->pbuf;
+        rate_setting_tlv = (MrvlIETypes_rate_setting_t *)((t_u8 *)rate_drop + sizeof(MrvlRateDropPattern_t));
+        rate_setting_tlv->header.type  = wlan_cpu_to_le16(TLV_TYPE_TX_RATE_CFG);
+        rate_setting_tlv->header.len   = wlan_cpu_to_le16(sizeof(rate_setting_tlv->rate_setting));
+        rate_setting_tlv->rate_setting = wlan_cpu_to_le16(ds_rate->param.rate_cfg.rate_setting);
+        PRINTM(MCMND, "he rate setting = %d\n", rate_setting_tlv->rate_setting);
+        cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_TX_RATE_CFG) + sizeof(MrvlRateScope_t) +
+                                     sizeof(MrvlRateDropPattern_t) + sizeof(MrvlIETypes_rate_setting_t));
+    }
+#endif
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of tx_rate_cfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ret_tx_rate_cfg(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN void *pioctl)
+{
+    mlan_adapter *pmadapter           = pmpriv->adapter;
+    wifi_ds_rate *ds_rate             = MNULL;
+    HostCmd_DS_TX_RATE_CFG *prate_cfg = MNULL;
+    MrvlRateScope_t *prate_scope;
+    MrvlIEtypesHeader_t *head = MNULL;
+    t_u16 tlv;
+    t_u16 tlv_buf_len = 0;
+    t_u8 *tlv_buf;
+    t_u32 i;
+    t_s32 index;
+    mlan_status ret                              = MLAN_STATUS_SUCCESS;
+    MrvlIETypes_rate_setting_t *rate_setting_tlv = MNULL;
+    t_u16 rate_setting                           = 0xffff;
+
+    ENTER();
+
+    if (resp == MNULL)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    prate_cfg = (HostCmd_DS_TX_RATE_CFG *)&(resp->params.tx_rate_cfg);
+
+    tlv_buf = (t_u8 *)((t_u8 *)prate_cfg) + sizeof(HostCmd_DS_TX_RATE_CFG);
+    if (tlv_buf != NULL)
+    {
+        tlv_buf_len = resp->size - (sizeof(HostCmd_DS_TX_RATE_CFG) + S_DS_GEN);
+        tlv_buf_len = wlan_le16_to_cpu(tlv_buf_len);
+    }
+
+    while (tlv_buf_len > 0U)
+    {
+        // coverity[overrun-local:SUPPRESS]
+        tlv = (t_u16)(*tlv_buf);
+        tlv = tlv | (*(tlv_buf + 1) << 8);
+
+        switch (tlv)
+        {
+            case TLV_TYPE_RATE_SCOPE:
+                prate_scope             = (MrvlRateScope_t *)(void *)tlv_buf;
+                pmpriv->bitmap_rates[0] = wlan_le16_to_cpu(prate_scope->hr_dsss_rate_bitmap);
+                pmpriv->bitmap_rates[1] = wlan_le16_to_cpu(prate_scope->ofdm_rate_bitmap);
+                for (i = 0; i < sizeof(prate_scope->ht_mcs_rate_bitmap) / sizeof(t_u16); i++)
+                {
+                    pmpriv->bitmap_rates[2U + i] = wlan_le16_to_cpu(prate_scope->ht_mcs_rate_bitmap[i]);
+                }
+#if CONFIG_11AC
+                for (i = 0; i < NELEMENTS(prate_scope->vht_mcs_rate_bitmap); i++)
+                {
+                    pmpriv->bitmap_rates[2 + sizeof(prate_scope->ht_mcs_rate_bitmap) / sizeof(t_u16) + i] =
+                        wlan_le16_to_cpu(prate_scope->vht_mcs_rate_bitmap[i]);
+                }
+
+#endif
+#if CONFIG_11AX
+                if (IS_FW_SUPPORT_11AX(pmadapter))
+                {
+                    for (i = 0; i < NELEMENTS(prate_scope->he_mcs_rate_bitmap); i++)
+                    {
+                        pmpriv->bitmap_rates[2 + sizeof(prate_scope->ht_mcs_rate_bitmap) / sizeof(t_u16) +
+                                             sizeof(prate_scope->vht_mcs_rate_bitmap) / sizeof(t_u16) + i] =
+                            wlan_le16_to_cpu(prate_scope->he_mcs_rate_bitmap[i]);
+                    }
+                }
+#endif
+                break;
+            case TLV_TYPE_TX_RATE_CFG:
+                rate_setting_tlv = (MrvlIETypes_rate_setting_t *)tlv_buf;
+                rate_setting     = rate_setting_tlv->rate_setting;
+                break;
+                /* Add RATE_DROP tlv here */
+            default:
+                PRINTM(MINFO, "Unexpected TLV for rate cfg \n");
+                break;
+        }
+
+        head      = (MrvlIEtypesHeader_t *)(void *)tlv_buf;
+        head->len = wlan_le16_to_cpu(head->len);
+        tlv_buf += head->len + sizeof(MrvlIEtypesHeader_t);
+        tlv_buf_len -= (head->len + sizeof(MrvlIEtypesHeader_t));
+    }
+
+    pmpriv->is_data_rate_auto = wlan_is_rate_auto(pmpriv);
+
+    if (pmpriv->is_data_rate_auto != 0U)
+    {
+        pmpriv->data_rate = 0;
+        PRINTM(MINFO, "Rate is Auto\r\n");
+    }
+
+    if (pioctl != NULL)
+    {
+        ds_rate = (wifi_ds_rate *)pioctl;
+        if (ds_rate == MNULL)
+        {
+            PRINTM(MERROR, "Request buffer not found!\n");
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        if (pmpriv->is_data_rate_auto != 0U)
+        {
+            // ds_rate->param.rate_cfg.is_rate_auto = MTRUE;
+            ds_rate->param.rate_cfg.rate_format = MLAN_RATE_FORMAT_AUTO;
+        }
+        else
+        {
+            /* check the LG rate */
+            index = wlan_get_rate_index(pmadapter, &pmpriv->bitmap_rates[0], 4);
+            if (index != -1)
+            {
+                if ((index >= MLAN_RATE_BITMAP_OFDM0) && (index <= MLAN_RATE_BITMAP_OFDM7))
+                {
+                    index -= (MLAN_RATE_BITMAP_OFDM0 - MLAN_RATE_INDEX_OFDM0);
+                }
+
+                ds_rate->param.rate_cfg.rate_format = MLAN_RATE_FORMAT_LG;
+                ds_rate->param.rate_cfg.rate        = (t_u32)index;
+            }
+            /* check the HT rate */
+            index = wlan_get_rate_index(pmadapter, &pmpriv->bitmap_rates[2], 16);
+            if (index != -1)
+            {
+                ds_rate->param.rate_cfg.rate_format = MLAN_RATE_FORMAT_HT;
+                ds_rate->param.rate_cfg.rate        = (t_u32)index;
+            }
+
+#if CONFIG_11AC
+            /* check the VHT rate */
+            index = wlan_get_rate_index(pmadapter, &pmpriv->bitmap_rates[10], 16);
+
+            if (index != -1)
+            {
+                ds_rate->param.rate_cfg.rate_format = MLAN_RATE_FORMAT_VHT;
+                ds_rate->param.rate_cfg.rate        = (t_u32)(index % 16);
+                ds_rate->param.rate_cfg.nss         = (t_u32)(index / 16);
+                ds_rate->param.rate_cfg.nss += MLAN_RATE_NSS1;
+            }
+#endif
+#if CONFIG_11AX
+            /* check the HE rate */
+            if (IS_FW_SUPPORT_11AX(pmadapter))
+            {
+                index = wlan_get_rate_index(pmadapter, &pmpriv->bitmap_rates[18], 16);
+                if (index != -1)
+                {
+                    ds_rate->param.rate_cfg.rate_format = MLAN_RATE_FORMAT_HE;
+                    ds_rate->param.rate_cfg.rate        = index % 16;
+                    ds_rate->param.rate_cfg.nss         = index / 16;
+                    ds_rate->param.rate_cfg.nss += MLAN_RATE_NSS1;
+                }
+            }
+#endif
+            ds_rate->param.rate_cfg.rate_setting = rate_setting;
+            PRINTM(MINFO, "Rate index is %d\n", ds_rate->param.rate_cfg.rate);
+
+            ds_rate->param.rate_cfg.rate_index = ds_rate->param.rate_cfg.rate;
+        }
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function prepares command of get_hw_spec.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pcmd         A pointer to HostCmd_DS_COMMAND structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_get_hw_spec(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *pcmd)
+{
+    HostCmd_DS_GET_HW_SPEC *hw_spec = &pcmd->params.hw_spec;
+
+    ENTER();
+
+    pcmd->command = wlan_cpu_to_le16(HostCmd_CMD_GET_HW_SPEC);
+    pcmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_GET_HW_SPEC) + S_DS_GEN);
+    (void)__memcpy(pmpriv->adapter, hw_spec->permanent_addr, pmpriv->curr_addr, MLAN_MAC_ADDR_LENGTH);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of HostCmd_CMD_GET_TSF
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_get_tsf(pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action)
+{
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_GET_TSF);
+    cmd->size    = wlan_cpu_to_le16((sizeof(HostCmd_DS_TSF)) + S_DS_GEN);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if (CONFIG_WIFI_TX_PER_TRACK) || (CONFIG_TX_RX_HISTOGRAM)
+/**
+ *  @brief This function prepares command of txrx_histogram and tx_pert, distinguish by cmd_action.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_txrx_pkt_stats(pmlan_private pmpriv,
+                                    IN HostCmd_DS_COMMAND *cmd,
+                                    IN t_u16 cmd_action,
+                                    IN t_void *pdata_buf)
+{
+#if CONFIG_WIFI_TX_PER_TRACK
+    if (cmd_action == HostCmd_ACT_SET_TX_PER_TRACKING)
+    {
+        wlan_cmd_tx_pert(pmpriv, cmd, cmd_action, pdata_buf);
+    }
+#endif
+#if CONFIG_TX_RX_HISTOGRAM
+    if (cmd_action != HostCmd_ACT_SET_TX_PER_TRACKING)
+    {
+        wlan_cmd_txrx_histogram(pmpriv, cmd, pdata_buf);
+    }
+#endif
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_WIFI_TX_PER_TRACK
+/**
+ *  @brief This function prepares command of tx_pert.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_tx_pert(pmlan_private pmpriv,
+                             IN HostCmd_DS_COMMAND *cmd,
+                             IN t_u16 cmd_action,
+                             IN t_void *pdata_buf)
+{
+    HostCmd_DS_TX_RX_PKT_STATS *pkt_stats = &cmd->params.pkt_stats;
+    MrvlTxPerTrackInfo_t *tx_pert         = NULL;
+    tx_pert_info *cfg                     = (tx_pert_info *)pdata_buf;
+
+    ENTER();
+    cmd->command      = wlan_cpu_to_le16(HostCmd_CMD_TX_RX_PKT_STATS);
+    pkt_stats->action = wlan_cpu_to_le16(cmd_action);
+    pkt_stats->enable = cfg->tx_pert_check;
+    if (cmd_action == HostCmd_ACT_SET_TX_PER_TRACKING)
+    {
+        tx_pert = (MrvlTxPerTrackInfo_t *)((t_u8 *)pkt_stats + sizeof(HostCmd_DS_TX_RX_PKT_STATS));
+        // coverity[overrun-local:SUPPRESS]
+        tx_pert->type                 = wlan_cpu_to_le16(TLV_TYPE_TX_PER_TRACK);
+        tx_pert->length               = wlan_cpu_to_le16(sizeof(MrvlTxPerTrackInfo_t) - sizeof(MrvlIEtypesHeader_t));
+        tx_pert->tx_stat_check_period = cfg->tx_pert_check_peroid;
+        tx_pert->tx_stat_check_ratio  = cfg->tx_pert_check_ratio;
+        tx_pert->tx_stat_check_num    = wlan_cpu_to_le16(cfg->tx_pert_check_num);
+    }
+    cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_TX_RX_PKT_STATS) + sizeof(MrvlTxPerTrackInfo_t));
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+/**
+ *  @brief This function prepares command of txrx_histogram.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_txrx_histogram(pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf)
+{
+    HostCmd_DS_TX_RX_HISTOGRAM *histogram = &cmd->params.histogram;
+    txrx_histogram_info *cfg              = (txrx_histogram_info *)pdata_buf;
+
+    ENTER();
+    cmd->command      = wlan_cpu_to_le16(HostCmd_CMD_TX_RX_PKT_STATS);
+    histogram->action = cfg->action;
+    histogram->enable = cfg->enable;
+    cmd->size         = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_TX_RX_HISTOGRAM));
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+
+/** *  @brief This function gets the no 5G status
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_get_no_5G_status(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u16 left_len;
+    t_u16 tlv_type                        = 0;
+    t_u16 tlv_len                         = 0;
+    MrvlIEtypesHeader_t *tlv              = MNULL;
+    MrvlIEtypes_fw_cap_info_t *fw_cap_tlv = MNULL;
+
+    left_len = resp->size - sizeof(HostCmd_DS_GET_HW_SPEC) - S_DS_GEN;
+    tlv      = (MrvlIEtypesHeader_t *)((t_u8 *)resp + S_DS_GEN + sizeof(HostCmd_DS_GET_HW_SPEC));
+    while (left_len > sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+        if (tlv_type == TLV_TYPE_FW_CAP_INFO)
+        {
+            fw_cap_tlv            = (MrvlIEtypes_fw_cap_info_t *)tlv;
+            pmadapter->fw_cap_ext = wlan_le32_to_cpu(fw_cap_tlv->fw_cap_ext);
+            break;
+        }
+        left_len -= (sizeof(MrvlIEtypesHeader_t) + tlv_len);
+        tlv = (MrvlIEtypesHeader_t *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of get_hw_spec
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to command buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ret_get_hw_spec(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf)
+{
+    HostCmd_DS_GET_HW_SPEC *hw_spec = &resp->params.hw_spec;
+    mlan_adapter *pmadapter         = pmpriv->adapter;
+    mlan_status ret                 = MLAN_STATUS_SUCCESS;
+    t_u32 i;
+    pmlan_ioctl_req pioctl_req = (mlan_ioctl_req *)pioctl_buf;
+    t_u16 left_len;
+    t_u16 tlv_type           = 0;
+    t_u16 tlv_len            = 0;
+    MrvlIEtypesHeader_t *tlv = MNULL;
+#if CONFIG_11AX
+    MrvlIEtypes_Extension_t *ext_tlv = MNULL;
+#ifdef RW610
+    int he_tlv_idx = 0;
+#endif
+#endif
+    MrvlIEtypes_fw_cap_info_t *fw_cap_tlv = MNULL;
+    ENTER();
+
+    pmadapter->fw_cap_info = wlan_le32_to_cpu(hw_spec->fw_cap_info);
+    /* Get no 5G status to check whether need to disable 5G */
+    wlan_get_no_5G_status(pmpriv, resp);
+    if ((IS_SUPPORT_MULTI_BANDS(pmadapter)) != 0U)
+    {
+        pmadapter->fw_bands = (t_u16)GET_FW_DEFAULT_BANDS(pmadapter);
+        if (ISSUPP_NO5G(pmadapter->fw_cap_ext))
+        {
+            pmadapter->fw_bands &= ~(BAND_A | BAND_AN | BAND_AAC);
+        }
+#if !CONFIG_5GHz_SUPPORT
+        /* fixme: Re-check if this is the correct way to disable 5 GHz. */
+        pmadapter->fw_bands &= ~(BAND_A | BAND_AN | BAND_AAC);
+#endif /* CONFIG_5GHz_SUPPORT */
+    }
+    else
+    {
+        pmadapter->fw_bands = BAND_B;
+    }
+
+    pmadapter->config_bands = pmadapter->fw_bands;
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        if (pmadapter->priv[i] != MNULL)
+        {
+            pmadapter->priv[i]->config_bands = pmadapter->fw_bands;
+        }
+    }
+
+    if ((pmadapter->fw_bands & BAND_A) != 0U)
+    {
+        if ((pmadapter->fw_bands & BAND_GN) != 0U)
+        {
+            pmadapter->config_bands |= BAND_AN;
+            for (i = 0; i < pmadapter->priv_num; i++)
+            {
+                if (pmadapter->priv[i] != MNULL)
+                {
+                    pmadapter->priv[i]->config_bands |= BAND_AN;
+                }
+            }
+
+            pmadapter->fw_bands |= BAND_AN;
+        }
+        if ((pmadapter->fw_bands & BAND_AAC) != 0U)
+        {
+            pmadapter->config_bands |= BAND_AAC;
+            for (i = 0; i < pmadapter->priv_num; i++)
+            {
+                if (pmadapter->priv[i] != MNULL)
+                {
+                    pmadapter->priv[i]->config_bands |= BAND_AAC;
+                }
+            }
+        }
+        if ((pmadapter->fw_bands & BAND_AN) != 0U)
+        {
+            pmadapter->adhoc_start_band  = (BAND_A | BAND_AN);
+            pmadapter->adhoc_11n_enabled = MTRUE;
+        }
+        else
+        {
+            pmadapter->adhoc_start_band = BAND_A;
+        }
+        pmpriv->adhoc_channel = DEFAULT_AD_HOC_CHANNEL_A;
+    }
+    else if ((pmadapter->fw_bands & BAND_GN) != 0U)
+    {
+        pmadapter->adhoc_start_band  = (BAND_G | BAND_B | BAND_GN);
+        pmpriv->adhoc_channel        = DEFAULT_AD_HOC_CHANNEL;
+        pmadapter->adhoc_11n_enabled = MTRUE;
+    }
+    else if ((pmadapter->fw_bands & BAND_G) != 0U)
+    {
+        pmadapter->adhoc_start_band = (BAND_G | BAND_B);
+        pmpriv->adhoc_channel       = DEFAULT_AD_HOC_CHANNEL;
+    }
+    else if ((pmadapter->fw_bands & BAND_B) != 0U)
+    {
+        pmadapter->adhoc_start_band = BAND_B;
+        pmpriv->adhoc_channel       = DEFAULT_AD_HOC_CHANNEL;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    pmadapter->fw_release_number = hw_spec->fw_release_number;
+    pmadapter->number_of_antenna = wlan_le16_to_cpu(hw_spec->number_of_antenna);
+
+    PRINTM(MINFO, "GET_HW_SPEC: fw_release_number- 0x%X\n", wlan_le32_to_cpu(pmadapter->fw_release_number));
+    PRINTM(MINFO, "GET_HW_SPEC: Permanent addr- %2x:%2x:%2x:%2x:%2x:%2x\n", hw_spec->permanent_addr[0],
+           hw_spec->permanent_addr[1], hw_spec->permanent_addr[2], hw_spec->permanent_addr[3],
+           hw_spec->permanent_addr[4], hw_spec->permanent_addr[5]);
+    PRINTM(MINFO, "GET_HW_SPEC: hw_if_version=0x%X  version=0x%X\n", wlan_le16_to_cpu(hw_spec->hw_if_version),
+           wlan_le16_to_cpu(hw_spec->version));
+
+    if (pmpriv->curr_addr[0] == 0xffU)
+    {
+        (void)__memmove(pmadapter, pmpriv->curr_addr, hw_spec->permanent_addr, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    pmadapter->hw_dot_11n_dev_cap     = wlan_le32_to_cpu(hw_spec->dot_11n_dev_cap);
+    pmadapter->usr_dot_11n_dev_cap_bg = pmadapter->hw_dot_11n_dev_cap & DEFAULT_11N_CAP_MASK_BG;
+    pmadapter->usr_dot_11n_dev_cap_a  = pmadapter->hw_dot_11n_dev_cap & DEFAULT_11N_CAP_MASK_A;
+    pmadapter->usr_dev_mcs_support = pmadapter->hw_dev_mcs_support = hw_spec->dev_mcs_support;
+    pmadapter->hw_mpdu_density                                     = GET_MPDU_DENSITY(hw_spec->hw_dev_cap);
+    PRINTM(MCMND, "GET_HW_SPEC: hw_mpdu_density=%d dev_mcs_support=0x%x\n", pmadapter->hw_mpdu_density,
+           hw_spec->dev_mcs_support);
+
+    wlan_show_dot11ndevcap(pmadapter, pmadapter->hw_dot_11n_dev_cap);
+    wlan_show_devmcssupport(pmadapter, pmadapter->hw_dev_mcs_support);
+
+    pmadapter->hw_dot_11ac_dev_cap     = wlan_le32_to_cpu(hw_spec->Dot11acDevCap);
+    pmadapter->hw_dot_11ac_mcs_support = wlan_le32_to_cpu(hw_spec->Dot11acMcsSupport);
+
+    pmadapter->usr_dot_11ac_mcs_support = pmadapter->hw_dot_11ac_mcs_support;
+
+    pmadapter->usr_dot_11ac_dev_cap_bg = pmadapter->hw_dot_11ac_dev_cap & ~DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK;
+#if CONFIG_5GHz_SUPPORT
+    pmadapter->usr_dot_11ac_dev_cap_a = pmadapter->hw_dot_11ac_dev_cap & ~DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK;
+#endif
+    pmadapter->usr_dot_11ac_bw = BW_FOLLOW_VHTCAP;
+
+    pmadapter->mp_end_port = wlan_le16_to_cpu(hw_spec->mp_end_port);
+
+#ifndef RW610
+    for (i = 1; i <= (unsigned)(MAX_PORT - pmadapter->mp_end_port); i++)
+    {
+        pmadapter->mp_data_port_mask &= ~(1U << (MAX_PORT - i));
+    }
+#endif
+
+
+#ifdef OTP_CHANINFO
+    if ((pmadapter->otp_region != MNULL) && (pmadapter->otp_region->force_reg == 0U))
+    {
+#endif
+
+        /* Set the region code to WWSM by default */
+        pmadapter->region_code = hw_spec->region_code;
+        for (i = 0; i < MRVDRV_MAX_REGION_CODE; i++)
+        {
+            /* Use the region code to search for the index */
+            if (pmadapter->region_code == region_code_index[i])
+            {
+                break;
+            }
+        }
+        /* If it's unidentified region code, use the default */
+        if (i >= MRVDRV_MAX_REGION_CODE)
+        {
+            pmadapter->region_code = MRVDRV_DEFAULT_REGION_CODE;
+            PRINTM(MWARN, "unidentified region code, use the default (0x%02x)\n", MRVDRV_DEFAULT_REGION_CODE);
+        }
+
+        /* Back up hw_region_code in case it is overwritten by the supplicant process*/
+        pmadapter->hw_region_code = pmadapter->region_code;
+
+        /* Synchronize CFP code with region code */
+        pmadapter->cfp_code_bg = (t_u8)pmadapter->region_code;
+        pmadapter->cfp_code_a  = (t_u8)pmadapter->region_code;
+#ifdef OTP_CHANINFO
+    }
+#endif
+    if (wlan_set_regiontable(pmpriv, (t_u8)pmadapter->region_code, pmadapter->fw_bands) != MLAN_STATUS_SUCCESS)
+    {
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_CMD_SCAN_FAIL;
+        }
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+    if (wlan_11d_set_universaltable(pmpriv, pmadapter->fw_bands) != MLAN_STATUS_SUCCESS)
+    {
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_CMD_SCAN_FAIL;
+        }
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+    left_len = resp->size - (t_u16)sizeof(HostCmd_DS_GET_HW_SPEC) - (t_u16)S_DS_GEN;
+    tlv      = (MrvlIEtypesHeader_t *)(void *)((t_u8 *)(&resp->params) + sizeof(HostCmd_DS_GET_HW_SPEC));
+    while (left_len > sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+        switch (tlv_type)
+        {
+#if CONFIG_11AX
+            case TLV_TYPE_EXTENSION_ID:
+                ext_tlv = (MrvlIEtypes_Extension_t *)tlv;
+                if (ext_tlv->ext_id == HE_CAPABILITY)
+                {
+                    ext_tlv->type = tlv_type;
+                    ext_tlv->len  = tlv_len;
+#ifndef RW610
+                    wlan_update_11ax_cap(pmadapter, (MrvlIEtypes_Extension_t *)ext_tlv);
+#else
+                    if ((he_tlv_idx == AX_2G_TLV_INDEX) || !ISSUPP_NO5G(pmadapter->fw_cap_ext))
+                    {
+                        wlan_update_11ax_cap(pmadapter, (MrvlIEtypes_Extension_t *)ext_tlv, he_tlv_idx);
+                        he_tlv_idx++;
+                    }
+#endif
+                }
+                break;
+#endif
+            case TLV_TYPE_FW_CAP_INFO:
+                fw_cap_tlv             = (MrvlIEtypes_fw_cap_info_t *)(void *)tlv;
+                pmadapter->fw_cap_info = wlan_le32_to_cpu(fw_cap_tlv->fw_cap_info);
+                pmadapter->fw_cap_ext  = wlan_le32_to_cpu(fw_cap_tlv->fw_cap_ext);
+                PRINTM(MCMND, "fw_cap_info=0x%x fw_cap_ext=0x%x\n", pmadapter->fw_cap_info, pmadapter->fw_cap_ext);
+                break;
+            default:
+                PRINTM(MINFO, "Unexpected TLV hw spec \n");
+                break;
+        }
+        left_len -= (t_u16)(sizeof(MrvlIEtypesHeader_t) + tlv_len);
+        tlv = (MrvlIEtypesHeader_t *)(void *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+
+#if defined(SD8987) || defined(SD9177)
+    pmadapter->cmd_tx_data = IS_FW_SUPPORT_CMD_TX_DATA(pmadapter) ? 0x01 : 0x00;
+#endif
+
+done:
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief This function prepares command of remain_on_channel.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_remain_on_channel(IN pmlan_private pmpriv,
+                                       IN HostCmd_DS_COMMAND *cmd,
+                                       IN t_u16 cmd_action,
+                                       IN t_void *pdata_buf)
+{
+    HostCmd_DS_REMAIN_ON_CHANNEL *remain_channel = &cmd->params.remain_on_chan;
+    mlan_ds_remain_chan *cfg                     = (mlan_ds_remain_chan *)pdata_buf;
+    ENTER();
+    cmd->size              = wlan_cpu_to_le16((sizeof(HostCmd_DS_REMAIN_ON_CHANNEL)) + S_DS_GEN);
+    cmd->command           = wlan_cpu_to_le16(HostCmd_CMD_802_11_REMAIN_ON_CHANNEL);
+    remain_channel->action = cmd_action;
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        if (cfg->remove != 0U)
+        {
+            remain_channel->action = HostCmd_ACT_GEN_REMOVE;
+        }
+        else
+        {
+            remain_channel->status        = 0;
+            remain_channel->reserved      = 0;
+            remain_channel->bandcfg       = cfg->bandcfg;
+            remain_channel->channel       = cfg->channel;
+            remain_channel->remain_period = wlan_cpu_to_le32(cfg->remain_period);
+        }
+    }
+    remain_channel->action = wlan_cpu_to_le16(remain_channel->action);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+#ifdef OTP_CHANINFO
+/**
+ *  @brief This function handles the command response of chan_region_cfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to command buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_chan_region_cfg(IN pmlan_private pmpriv,
+                                     IN HostCmd_DS_COMMAND *resp,
+                                     IN mlan_ioctl_req *pioctl_buf)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u16 action;
+    HostCmd_DS_CHAN_REGION_CFG *reg = MNULL;
+    t_u8 *tlv_buf                   = MNULL;
+    t_u16 tlv_buf_left;
+    mlan_ds_misc_cfg *misc_cfg     = MNULL;
+    mlan_ds_misc_chnrgpwr_cfg *cfg = MNULL;
+    mlan_status ret                = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    reg = (HostCmd_DS_CHAN_REGION_CFG *)(void *)&resp->params;
+    if (reg == MNULL)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+
+    action = wlan_le16_to_cpu(reg->action);
+    if (action != HostCmd_ACT_GEN_GET)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+
+    tlv_buf      = (t_u8 *)reg + sizeof(*reg);
+    tlv_buf_left = (t_u16)(wlan_le16_to_cpu(resp->size) - S_DS_GEN - sizeof(*reg));
+
+    /* Add FW cfp tables and region info */
+    wlan_add_fw_cfp_tables(pmpriv, tlv_buf, tlv_buf_left);
+
+    if (pioctl_buf == MNULL)
+    {
+        goto done;
+    }
+
+    if (pioctl_buf->pbuf == MNULL)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+
+    misc_cfg = (mlan_ds_misc_cfg *)(void *)pioctl_buf->pbuf;
+
+    if (misc_cfg->sub_command == MLAN_OID_MISC_GET_REGIONPWR_CFG)
+    {
+        cfg         = (mlan_ds_misc_chnrgpwr_cfg *)&(misc_cfg->param.rgchnpwr_cfg);
+        cfg->length = wlan_le16_to_cpu(resp->size);
+        (void)__memcpy(pmpriv->adapter, cfg->chnrgpwr_buf, (t_u8 *)resp, cfg->length);
+    }
+    else
+    {
+        (void)__memset(pmpriv->adapter, &misc_cfg->param.custom_reg_domain, 0, sizeof(mlan_ds_custom_reg_domain));
+        if (pmadapter->otp_region != MNULL)
+        {
+            (void)__memcpy(pmpriv->adapter, &misc_cfg->param.custom_reg_domain.region, pmadapter->otp_region,
+                           sizeof(otp_region_info_t));
+        }
+        if (pmadapter->cfp_otp_bg != MNULL)
+        {
+            misc_cfg->param.custom_reg_domain.num_bg_chan = pmadapter->tx_power_table_bg_rows;
+            (void)__memcpy(pmpriv->adapter, (t_u8 *)misc_cfg->param.custom_reg_domain.cfp_tbl,
+                           (t_u8 *)pmadapter->cfp_otp_bg,
+                           pmadapter->tx_power_table_bg_rows * sizeof(chan_freq_power_t));
+        }
+#if CONFIG_5GHz_SUPPORT
+        if (pmadapter->cfp_otp_a != MNULL)
+        {
+            misc_cfg->param.custom_reg_domain.num_a_chan = pmadapter->tx_power_table_a_rows;
+            (void)__memcpy(pmpriv->adapter,
+                           (t_u8 *)misc_cfg->param.custom_reg_domain.cfp_tbl +
+                               pmadapter->tx_power_table_bg_rows * sizeof(chan_freq_power_t),
+                           (t_u8 *)pmadapter->cfp_otp_a, pmadapter->tx_power_table_a_rows * sizeof(chan_freq_power_t));
+        }
+#endif
+    }
+done:
+    LEAVE();
+    return ret;
+}
+#endif
+
+#if CONFIG_COMPRESS_TX_PWTBL
+mlan_status wlan_cmd_region_power_cfg(pmlan_private pmpriv,
+                                      HostCmd_DS_COMMAND *cmd,
+                                      t_u16 cmd_action,
+                                      t_void *pdata_buf)
+{
+    t_u16 buf_len;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_REGION_POWER_CFG);
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        buf_len = cmd->size - S_DS_GEN;
+        __memcpy(pmpriv->adapter, (t_u8 *)cmd + S_DS_GEN, pdata_buf, buf_len);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+
+#if CONFIG_RX_ABORT_CFG
+/**
+ *  @brief This function sends rx abort cfg command to firmware.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          Hostcmd ID
+ *  @param cmd_action   Command action
+ *  @param pdata_buf    A void pointer to information buffer
+ *  @return             N/A
+ */
+mlan_status wlan_cmd_rx_abort_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    HostCmd_DS_RX_ABORT_CFG *rx_abort_cfg = &cmd->params.rx_abort_cfg;
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    rx_abort_cfg_t *cfg = (rx_abort_cfg_t *)pdata_buf;
+
+    ENTER();
+
+    cmd->command         = wlan_cpu_to_le16(HostCmd_CMD_RX_ABORT_CFG);
+    cmd->size            = wlan_cpu_to_le16(sizeof(HostCmd_DS_RX_ABORT_CFG) + S_DS_GEN);
+    rx_abort_cfg->action = wlan_cpu_to_le16(cmd_action);
+
+    if (rx_abort_cfg->action == HostCmd_ACT_GEN_SET)
+    {
+        rx_abort_cfg->enable         = cfg->enable;
+        rx_abort_cfg->rssi_threshold = (t_s8)cfg->rssi_threshold;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+/**
+ *  @brief This function sends rx abort cfg ext command to firmware.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          Hostcmd ID
+ *  @param cmd_action   Command action
+ *  @param pdata_buf    A void pointer to information buffer
+ *  @return             N/A
+ */
+mlan_status wlan_cmd_rx_abort_cfg_ext(pmlan_private pmpriv,
+                                      HostCmd_DS_COMMAND *cmd,
+                                      t_u16 cmd_action,
+                                      t_void *pdata_buf)
+{
+    HostCmd_DS_RX_ABORT_CFG_EXT *rx_abort_cfg_ext = (HostCmd_DS_RX_ABORT_CFG_EXT *)&cmd->params.rx_abort_cfg_ext;
+    rx_abort_cfg_ext_t *cfg                       = (rx_abort_cfg_ext_t *)pdata_buf;
+
+    ENTER();
+
+    cmd->command             = wlan_cpu_to_le16(HostCmd_CMD_RX_ABORT_CFG_EXT);
+    cmd->size                = wlan_cpu_to_le16(sizeof(HostCmd_DS_RX_ABORT_CFG_EXT) + S_DS_GEN);
+    rx_abort_cfg_ext->action = wlan_cpu_to_le16(cmd_action);
+
+    if (rx_abort_cfg_ext->action == HostCmd_ACT_GEN_SET)
+    {
+        rx_abort_cfg_ext->enable               = cfg->enable;
+        rx_abort_cfg_ext->rssi_margin          = (t_s8)cfg->rssi_margin;
+        rx_abort_cfg_ext->ceil_rssi_threshold  = (t_s8)cfg->ceil_rssi_threshold;
+        rx_abort_cfg_ext->floor_rssi_threshold = (t_s8)cfg->floor_rssi_threshold;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+/**
+ *  @brief This function sends cck desense cfg command to firmware.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          Hostcmd ID
+ *  @param cmd_action   Command action
+ *  @param pdata_buf    A void pointer to information buffer
+ *  @return             N/A
+ */
+mlan_status wlan_cmd_cck_desense_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    HostCmd_DS_CCK_DESENSE_CFG *cfg_cmd = (HostCmd_DS_CCK_DESENSE_CFG *)&cmd->params.cck_desense_cfg;
+    cck_desense_cfg_t *cfg              = (cck_desense_cfg_t *)pdata_buf;
+
+    ENTER();
+
+    cmd->command    = wlan_cpu_to_le16(HostCmd_CMD_CCK_DESENSE_CFG);
+    cmd->size       = wlan_cpu_to_le16(sizeof(HostCmd_DS_CCK_DESENSE_CFG) + S_DS_GEN);
+    cfg_cmd->action = wlan_cpu_to_le16(cmd_action);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        cfg_cmd->mode              = wlan_cpu_to_le16(cfg->mode);
+        cfg_cmd->margin            = (t_s8)cfg->margin;
+        cfg_cmd->ceil_thresh       = (t_s8)cfg->ceil_thresh;
+        cfg_cmd->num_on_intervals  = (t_u8)cfg->num_on_intervals;
+        cfg_cmd->num_off_intervals = (t_u8)cfg->num_off_intervals;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+/**
+ *  @brief This function prepares command of GPIO TSF LATCH.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req buf
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_gpio_tsf_latch(
+    pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, mlan_ioctl_req *pioctl_buf, t_void *pdata_buf)
+{
+    HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG *gpio_tsf_config = &cmd->params.gpio_tsf_latch;
+    mlan_ds_gpio_tsf_latch *cfg                             = (mlan_ds_gpio_tsf_latch *)pdata_buf;
+    mlan_ds_misc_cfg *misc_cfg                              = (mlan_ds_misc_cfg *)pioctl_buf->pbuf;
+
+    mlan_ds_tsf_info *tsf_info                               = (mlan_ds_tsf_info *)pdata_buf;
+    MrvlIEtypes_GPIO_TSF_LATCH_CONFIG *gpio_tsf_latch_config = MNULL;
+    MrvlIEtypes_GPIO_TSF_LATCH_REPORT *gpio_tsf_latch_report = MNULL;
+    t_u8 *tlv                                                = MNULL;
+    ENTER();
+
+    cmd->size               = sizeof(HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG) + S_DS_GEN;
+    cmd->command            = wlan_cpu_to_le16(HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG);
+    gpio_tsf_config->action = wlan_cpu_to_le16(cmd_action);
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        tlv = (t_u8 *)gpio_tsf_config->tlv_buf;
+        if (misc_cfg->sub_command == (t_u32)MLAN_OID_MISC_GPIO_TSF_LATCH)
+        {
+            gpio_tsf_latch_config              = (MrvlIEtypes_GPIO_TSF_LATCH_CONFIG *)tlv;
+            gpio_tsf_latch_config->header.type = wlan_cpu_to_le16(TLV_TYPE_GPIO_TSF_LATCH_CONFIG);
+            gpio_tsf_latch_config->header.len =
+                wlan_cpu_to_le16(sizeof(MrvlIEtypes_GPIO_TSF_LATCH_CONFIG) - sizeof(MrvlIEtypesHeader_t));
+            gpio_tsf_latch_config->clock_sync_mode              = cfg->clock_sync_mode;
+            gpio_tsf_latch_config->clock_sync_Role              = cfg->clock_sync_Role;
+            gpio_tsf_latch_config->clock_sync_gpio_pin_number   = cfg->clock_sync_gpio_pin_number;
+            gpio_tsf_latch_config->clock_sync_gpio_level_toggle = cfg->clock_sync_gpio_level_toggle;
+            gpio_tsf_latch_config->clock_sync_gpio_pulse_width  = wlan_cpu_to_le16(cfg->clock_sync_gpio_pulse_width);
+            cmd->size += sizeof(MrvlIEtypes_GPIO_TSF_LATCH_CONFIG);
+            tlv += sizeof(MrvlIEtypes_GPIO_TSF_LATCH_CONFIG);
+            PRINTM(
+                MCMND,
+                "Set GPIO TSF latch config: \r\nMode=%d Role=%d, \r\nGPIO Pin Number=%d, \r\nGPIO level/toggle=%d GPIO "
+                "pulse "
+                "width=%d\n\r",
+                cfg->clock_sync_mode, cfg->clock_sync_Role, cfg->clock_sync_gpio_pin_number,
+                cfg->clock_sync_gpio_level_toggle, (int)cfg->clock_sync_gpio_pulse_width);
+        }
+    }
+    else if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        tlv = (t_u8 *)gpio_tsf_config->tlv_buf;
+        if (misc_cfg->sub_command == (t_u32)MLAN_OID_MISC_GPIO_TSF_LATCH)
+        {
+            gpio_tsf_latch_config              = (MrvlIEtypes_GPIO_TSF_LATCH_CONFIG *)tlv;
+            gpio_tsf_latch_config->header.type = wlan_cpu_to_le16(TLV_TYPE_GPIO_TSF_LATCH_CONFIG);
+            gpio_tsf_latch_config->header.len =
+                wlan_cpu_to_le16(sizeof(MrvlIEtypes_GPIO_TSF_LATCH_CONFIG) - sizeof(MrvlIEtypesHeader_t));
+            cmd->size += sizeof(MrvlIEtypes_GPIO_TSF_LATCH_CONFIG);
+            tlv += sizeof(MrvlIEtypes_GPIO_TSF_LATCH_CONFIG);
+        }
+
+        if (misc_cfg->sub_command == (t_u32)MLAN_OID_MISC_GET_TSF_INFO)
+        {
+            gpio_tsf_latch_report = (MrvlIEtypes_GPIO_TSF_LATCH_REPORT *)tlv;
+            (void)memset(gpio_tsf_latch_report, 0, sizeof(MrvlIEtypes_GPIO_TSF_LATCH_REPORT));
+            gpio_tsf_latch_report->header.type = wlan_cpu_to_le16(TLV_TYPE_GPIO_TSF_LATCH_REPORT);
+            gpio_tsf_latch_report->header.len =
+                wlan_cpu_to_le16(sizeof(MrvlIEtypes_GPIO_TSF_LATCH_REPORT) - sizeof(MrvlIEtypesHeader_t));
+            gpio_tsf_latch_report->tsf_format = wlan_cpu_to_le16(tsf_info->tsf_format);
+            PRINTM(MCMND, "Get TSF info: format=%d\n\r", tsf_info->tsf_format);
+            cmd->size += sizeof(MrvlIEtypes_GPIO_TSF_LATCH_REPORT);
+        }
+    }
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of GPIO TSF Latch
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_gpio_tsf_latch(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG *gpio_tsf_config  = &resp->params.gpio_tsf_latch;
+    mlan_ds_misc_cfg *cfg                                    = MNULL;
+    MrvlIEtypes_GPIO_TSF_LATCH_CONFIG *gpio_tsf_latch_config = MNULL;
+    MrvlIEtypes_GPIO_TSF_LATCH_REPORT *gpio_tsf_latch_report = MNULL;
+    MrvlIEtypesHeader_t *tlv                                 = MNULL;
+    t_u16 tlv_buf_left                                       = 0;
+    t_u16 tlv_type                                           = 0;
+    t_u16 tlv_len                                            = 0;
+
+    ENTER();
+    if (wlan_le16_to_cpu(gpio_tsf_config->action) == HostCmd_ACT_GEN_GET)
+    {
+        if (pioctl_buf)
+        {
+            cfg          = (mlan_ds_misc_cfg *)pioctl_buf->pbuf;
+            tlv          = (MrvlIEtypesHeader_t *)(gpio_tsf_config->tlv_buf);
+            tlv_buf_left = resp->size - (sizeof(HostCmd_DS_GPIO_TSF_LATCH_PARAM_CONFIG) + S_DS_GEN);
+            while (tlv_buf_left >= sizeof(MrvlIEtypesHeader_t))
+            {
+                tlv_type = wlan_le16_to_cpu(tlv->type);
+                tlv_len  = wlan_le16_to_cpu(tlv->len);
+                if (tlv_buf_left < (tlv_len + sizeof(MrvlIEtypesHeader_t)))
+                {
+                    PRINTM(MCMND, "Error processing gpio tsf latch config TLVs, bytes left < TLV length\n");
+                    break;
+                }
+                switch (tlv_type)
+                {
+                    case TLV_TYPE_GPIO_TSF_LATCH_CONFIG:
+                        if (cfg->sub_command == (t_u32)MLAN_OID_MISC_GPIO_TSF_LATCH)
+                        {
+                            gpio_tsf_latch_config                            = (MrvlIEtypes_GPIO_TSF_LATCH_CONFIG *)tlv;
+                            cfg->param.gpio_tsf_latch_config.clock_sync_mode = gpio_tsf_latch_config->clock_sync_mode;
+                            cfg->param.gpio_tsf_latch_config.clock_sync_Role = gpio_tsf_latch_config->clock_sync_Role;
+                            cfg->param.gpio_tsf_latch_config.clock_sync_gpio_pin_number =
+                                gpio_tsf_latch_config->clock_sync_gpio_pin_number;
+                            cfg->param.gpio_tsf_latch_config.clock_sync_gpio_level_toggle =
+                                gpio_tsf_latch_config->clock_sync_gpio_level_toggle;
+                            cfg->param.gpio_tsf_latch_config.clock_sync_gpio_pulse_width =
+                                wlan_le16_to_cpu(gpio_tsf_latch_config->clock_sync_gpio_pulse_width);
+                            PRINTM(
+                                MCMND,
+                                "Get GPIO TSF latch config: Mode=%d Role=%d, GPIO Pin Number=%d, GPIO level/toggle=%d "
+                                "GPIO pulse width=%d\n\r",
+                                cfg->param.gpio_tsf_latch_config.clock_sync_mode,
+                                cfg->param.gpio_tsf_latch_config.clock_sync_Role,
+                                cfg->param.gpio_tsf_latch_config.clock_sync_gpio_pin_number,
+                                cfg->param.gpio_tsf_latch_config.clock_sync_gpio_level_toggle,
+                                (int)cfg->param.gpio_tsf_latch_config.clock_sync_gpio_pulse_width);
+                        }
+                        break;
+                    case TLV_TYPE_GPIO_TSF_LATCH_REPORT:
+                        if (cfg->sub_command == (t_u32)MLAN_OID_MISC_GET_TSF_INFO)
+                        {
+                            gpio_tsf_latch_report          = (MrvlIEtypes_GPIO_TSF_LATCH_REPORT *)tlv;
+                            cfg->param.tsf_info.tsf_format = wlan_le16_to_cpu(gpio_tsf_latch_report->tsf_format);
+                            cfg->param.tsf_info.tsf_info   = wlan_le16_to_cpu(gpio_tsf_latch_report->tsf_info);
+                            cfg->param.tsf_info.tsf        = wlan_le64_to_cpu(gpio_tsf_latch_report->tsf);
+                            cfg->param.tsf_info.tsf_offset = wlan_le16_to_cpu(gpio_tsf_latch_report->tsf_offset);
+                            PRINTM(MCMND, "Get GPIO TSF latch report : format=%d\n info=%d tsf=%llu offset=%d\r\n",
+                                   cfg->param.tsf_info.tsf_format, cfg->param.tsf_info.tsf_info,
+                                   cfg->param.tsf_info.tsf, cfg->param.tsf_info.tsf_offset);
+                        }
+                        break;
+                    default:
+                        wifi_d("gpio tsf latch: Unknown tlv type");
+                        break;
+                }
+                tlv_buf_left -= tlv_len + sizeof(MrvlIEtypesHeader_t);
+                tlv = (MrvlIEtypesHeader_t *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+            }
+            if (cfg->sub_command == (t_u32)MLAN_OID_MISC_GPIO_TSF_LATCH)
+                pioctl_buf->data_read_written = sizeof(mlan_ds_gpio_tsf_latch);
+            else if (cfg->sub_command == (t_u32)MLAN_OID_MISC_GET_TSF_INFO)
+                pioctl_buf->data_read_written = sizeof(mlan_ds_tsf_info);
+        }
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+#if CONFIG_MULTI_CHAN
+/**
+ *  @brief This function prepares the command MULTI_CHAN_CFG
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   Command action: GET or SET
+ *  @param pdata_buf    A pointer to new setting buf
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_multi_chan_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    mlan_ds_multi_chan_cfg *multi_chan_cfg = (mlan_ds_multi_chan_cfg *)pdata_buf;
+    HostCmd_DS_MULTI_CHAN_CFG *pmchan_cfg  = (HostCmd_DS_MULTI_CHAN_CFG *)&cmd->params.multi_chan_cfg;
+
+    ENTER();
+
+    cmd->command       = wlan_cpu_to_le16(HostCmd_CMD_MULTI_CHAN_CONFIG);
+    pmchan_cfg->action = wlan_cpu_to_le16(cmd_action);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        pmchan_cfg->buffer_weight = multi_chan_cfg->buffer_weight;
+        pmchan_cfg->channel_time  = wlan_cpu_to_le32(multi_chan_cfg->channel_time);
+        PRINTM(MCMND, "Set multi-channel: buffer_weight=%d channel_time=%d\n", multi_chan_cfg->buffer_weight,
+               multi_chan_cfg->channel_time);
+        cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_MULTI_CHAN_CFG));
+    }
+    else
+    {
+        cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(cmd_action));
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of MULTI_CHAN_CFG
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_multi_chan_cfg(pmlan_private pmpriv, const HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *pcfg                     = MNULL;
+    const HostCmd_DS_MULTI_CHAN_CFG *presp_cfg = &resp->params.multi_chan_cfg;
+
+    ENTER();
+
+    if (pioctl_buf)
+    {
+        pcfg                                     = (mlan_ds_misc_cfg *)pioctl_buf->pbuf;
+        pcfg->param.multi_chan_cfg.channel_time  = wlan_le32_to_cpu(presp_cfg->channel_time);
+        pcfg->param.multi_chan_cfg.buffer_weight = presp_cfg->buffer_weight;
+        pcfg->param.multi_chan_cfg.tlv_len = resp->size - (sizeof(HostCmd_DS_GEN) + sizeof(HostCmd_DS_MULTI_CHAN_CFG));
+        PRINTM(MCMND, "Get multi-channel: buffer_weight=%d channel_time=%d tlv_len=%d\n",
+               pcfg->param.multi_chan_cfg.buffer_weight, pcfg->param.multi_chan_cfg.channel_time,
+               pcfg->param.multi_chan_cfg.tlv_len);
+        __memcpy(pmpriv->adapter, pcfg->param.multi_chan_cfg.tlv_buf, presp_cfg->tlv_buf,
+                 pcfg->param.multi_chan_cfg.tlv_len);
+        pioctl_buf->buf_len = sizeof(mlan_ds_multi_chan_cfg) + pcfg->param.multi_chan_cfg.tlv_len;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares the command MULTI_CHAN_POLICY
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   Command action: GET or SET
+ *  @param pdata_buf    A pointer to new setting buf
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_multi_chan_policy(pmlan_private pmpriv,
+                                       HostCmd_DS_COMMAND *cmd,
+                                       t_u16 cmd_action,
+                                       t_void *pdata_buf)
+{
+    t_u16 policy                                     = 0;
+    HostCmd_DS_MULTI_CHAN_POLICY *pmulti_chan_policy = (HostCmd_DS_MULTI_CHAN_POLICY *)&cmd->params.multi_chan_policy;
+
+    ENTER();
+
+    cmd->command               = wlan_cpu_to_le16(HostCmd_CMD_MULTI_CHAN_POLICY);
+    pmulti_chan_policy->action = wlan_cpu_to_le16(cmd_action);
+    cmd->size                  = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_MULTI_CHAN_POLICY));
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        policy                     = *((t_u16 *)pdata_buf);
+        pmulti_chan_policy->policy = wlan_cpu_to_le16(policy);
+        PRINTM(MCMND, "Set multi-channel policy: %d\n", policy);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of MULTI_CHAN_POLICY
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_multi_chan_policy(pmlan_private pmpriv, const HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *pcfg                        = MNULL;
+    const HostCmd_DS_MULTI_CHAN_POLICY *presp_cfg = &resp->params.multi_chan_policy;
+
+    ENTER();
+
+    if (pioctl_buf)
+    {
+        pcfg                          = (mlan_ds_misc_cfg *)pioctl_buf->pbuf;
+        pcfg->param.multi_chan_policy = wlan_le16_to_cpu(presp_cfg->policy);
+
+        if (pioctl_buf->action == HostCmd_ACT_GEN_SET)
+        {
+            if (pcfg->param.multi_chan_policy)
+                pmpriv->adapter->mc_policy = MTRUE;
+            else
+                pmpriv->adapter->mc_policy = MFALSE;
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares the command DRCD_CFG
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   Command action: GET or SET
+ *  @param pdata_buf    A pointer to new setting buf
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_drcs_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    mlan_ds_drcs_cfg *drcs_cfg                      = (mlan_ds_drcs_cfg *)pdata_buf;
+    HostCmd_DS_DRCS_CFG *pdrcs_cfg                  = (HostCmd_DS_DRCS_CFG *)&cmd->params.drcs_cfg;
+    MrvlTypes_DrcsTimeSlice_t *channel_time_slicing = &pdrcs_cfg->time_slicing;
+
+    ENTER();
+
+    cmd->command      = wlan_cpu_to_le16(HostCmd_CMD_DRCS_CONFIG);
+    pdrcs_cfg->action = wlan_cpu_to_le16(cmd_action);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        channel_time_slicing->header.type = wlan_cpu_to_le16(MRVL_DRCS_TIME_SLICE_TLV_ID);
+        channel_time_slicing->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlTypes_DrcsTimeSlice_t) - sizeof(MrvlIEtypesHeader_t));
+        channel_time_slicing->chan_idx   = wlan_cpu_to_le16(drcs_cfg->chan_idx);
+        channel_time_slicing->chantime   = drcs_cfg->chantime;
+        channel_time_slicing->switchtime = drcs_cfg->switchtime;
+        channel_time_slicing->undozetime = drcs_cfg->undozetime;
+        channel_time_slicing->mode       = drcs_cfg->mode;
+        PRINTM(MCMND, "Set multi-channel: chan_idx=%d chantime=%d switchtime=%d undozetime=%d mode=%d\n",
+               channel_time_slicing->chan_idx, channel_time_slicing->chantime, channel_time_slicing->switchtime,
+               channel_time_slicing->undozetime, channel_time_slicing->mode);
+        cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_DRCS_CFG));
+        /* Set two channels different parameters */
+        if (0x3 != channel_time_slicing->chan_idx)
+        {
+            drcs_cfg++;
+            channel_time_slicing              = pdrcs_cfg->drcs_buf;
+            channel_time_slicing->header.type = wlan_cpu_to_le16(MRVL_DRCS_TIME_SLICE_TLV_ID);
+            channel_time_slicing->header.len =
+                wlan_cpu_to_le16(sizeof(MrvlTypes_DrcsTimeSlice_t) - sizeof(MrvlIEtypesHeader_t));
+            channel_time_slicing->chan_idx   = wlan_cpu_to_le16(drcs_cfg->chan_idx);
+            channel_time_slicing->chantime   = drcs_cfg->chantime;
+            channel_time_slicing->switchtime = drcs_cfg->switchtime;
+            channel_time_slicing->undozetime = drcs_cfg->undozetime;
+            channel_time_slicing->mode       = drcs_cfg->mode;
+            PRINTM(MCMND, "Set multi-channel: chan_idx=%d chantime=%d switchtime=%d undozetime=%d mode=%d\n",
+                   channel_time_slicing->chan_idx, channel_time_slicing->chantime, channel_time_slicing->switchtime,
+                   channel_time_slicing->undozetime, channel_time_slicing->mode);
+            cmd->size += wlan_cpu_to_le16(sizeof(MrvlTypes_DrcsTimeSlice_t));
+        }
+    }
+    else
+    {
+        cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(cmd_action));
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of DRCS_CFG
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_drcs_cfg(pmlan_private pmpriv, const HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *pcfg                                 = MNULL;
+    const HostCmd_DS_DRCS_CFG *presp_cfg                   = &resp->params.drcs_cfg;
+    const MrvlTypes_DrcsTimeSlice_t *channel_time_slicing  = &presp_cfg->time_slicing;
+    const MrvlTypes_DrcsTimeSlice_t *channel_time_slicing1 = MNULL;
+    mlan_ds_drcs_cfg *drcs_cfg1                            = MNULL;
+
+    ENTER();
+
+    if (pioctl_buf)
+    {
+        pcfg = (mlan_ds_misc_cfg *)pioctl_buf->pbuf;
+        if (wlan_le16_to_cpu(channel_time_slicing->header.type) != MRVL_DRCS_TIME_SLICE_TLV_ID ||
+            wlan_le16_to_cpu(channel_time_slicing->header.len) !=
+                sizeof(MrvlTypes_DrcsTimeSlice_t) - sizeof(MrvlIEtypesHeader_t))
+        {
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        pcfg->param.drcs_cfg[0].chan_idx   = wlan_le16_to_cpu(channel_time_slicing->chan_idx);
+        pcfg->param.drcs_cfg[0].chantime   = channel_time_slicing->chantime;
+        pcfg->param.drcs_cfg[0].switchtime = channel_time_slicing->switchtime;
+        pcfg->param.drcs_cfg[0].undozetime = channel_time_slicing->undozetime;
+        pcfg->param.drcs_cfg[0].mode       = channel_time_slicing->mode;
+        PRINTM(MCMND, "multi-channel: chan_idx=%d chantime=%d switchtime=%d undozetime=%d mode=%d\n",
+               pcfg->param.drcs_cfg[0].chan_idx, channel_time_slicing->chantime, channel_time_slicing->switchtime,
+               channel_time_slicing->undozetime, channel_time_slicing->mode);
+        pioctl_buf->buf_len = sizeof(mlan_ds_drcs_cfg);
+        /*Channel for chan_idx 1 and 2 have different parameters*/
+        if (0x3 != pcfg->param.drcs_cfg[0].chan_idx)
+        {
+            channel_time_slicing1 = presp_cfg->drcs_buf;
+            if (wlan_le16_to_cpu(channel_time_slicing1->header.type) != MRVL_DRCS_TIME_SLICE_TLV_ID ||
+                wlan_le16_to_cpu(channel_time_slicing1->header.len) !=
+                    sizeof(MrvlTypes_DrcsTimeSlice_t) - sizeof(MrvlIEtypesHeader_t))
+            {
+                LEAVE();
+                return MLAN_STATUS_FAILURE;
+            }
+            drcs_cfg1             = (mlan_ds_drcs_cfg *)&pcfg->param.drcs_cfg[1];
+            drcs_cfg1->chan_idx   = wlan_le16_to_cpu(channel_time_slicing1->chan_idx);
+            drcs_cfg1->chantime   = channel_time_slicing1->chantime;
+            drcs_cfg1->switchtime = channel_time_slicing1->switchtime;
+            drcs_cfg1->undozetime = channel_time_slicing1->undozetime;
+            drcs_cfg1->mode       = channel_time_slicing1->mode;
+            PRINTM(MCMND, "multi-channel: chan_idx=%d chantime=%d switchtime=%d undozetime=%d mode=%d\n",
+                   drcs_cfg1->chan_idx, drcs_cfg1->chantime, drcs_cfg1->switchtime, drcs_cfg1->undozetime,
+                   drcs_cfg1->mode);
+            pioctl_buf->buf_len += sizeof(mlan_ds_drcs_cfg);
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+
+#if CONFIG_FW_VDLL
+
+extern const unsigned char wlan_fw_bin[];
+extern unsigned int wlan_fw_bin_len;
+
+/**
+ *  @brief This function download the vdll block.
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param block            A pointer to VDLL block
+ *  @param block_len      The VDLL block length
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_download_vdll_block(mlan_adapter *pmadapter, t_u8 *block, t_u16 block_len)
+{
+    mlan_status status   = MLAN_STATUS_FAILURE;
+    int ret              = -WM_FAIL;
+    pvdll_dnld_ctrl ctrl = &pmadapter->vdll_ctrl;
+    t_u16 msg_len        = block_len + sizeof(HostCmd_DS_GEN);
+    HostCmd_DS_GEN *cmd_hdr;
+
+    ENTER();
+
+    if ((msg_len > WIFI_FW_CMDBUF_SIZE) || (ctrl == NULL))
+    {
+        wevt_d("VDLL block mem greater than cmd buf/vdll struct not inited");
+        goto done;
+    }
+
+    cmd_hdr = (HostCmd_DS_GEN *)ctrl->cmd_buf;
+
+    cmd_hdr->command = wlan_cpu_to_le16(HostCmd_CMD_VDLL);
+    cmd_hdr->seq_num = wlan_cpu_to_le16(0xFF00);
+    cmd_hdr->size    = wlan_cpu_to_le16(msg_len);
+
+    (void)__memcpy(pmadapter, ctrl->cmd_buf + sizeof(HostCmd_DS_GEN), block, block_len);
+
+#if CONFIG_FW_VDLL_DEBUG
+    wevt_d("DNLD_VDLL : block_len=%d", block_len);
+#endif
+
+    ret = wifi_wait_for_vdllcmdresp(NULL);
+
+    if (ret == -WM_FAIL)
+    {
+        wevt_d("DNLD_VDLL: Host to Card Failed");
+    }
+    else
+    {
+        status = MLAN_STATUS_SUCCESS;
+    }
+
+done:
+    LEAVE();
+    return status;
+}
+
+/**
+ *  @brief The function Get the VDLL image from moal
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param offset          offset
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ *
+ */
+static mlan_status wlan_get_vdll_image(pmlan_adapter pmadapter, t_u32 vdll_len)
+{
+    /*Since f/w is already in .h in RT so we will use the offsets directly*/
+
+    vdll_dnld_ctrl *ctrl = &pmadapter->vdll_ctrl;
+    ENTER();
+    if (ctrl != NULL)
+    {
+        ctrl->vdll_mem = (t_u8 *)(pmadapter->fw_start_addr + (wlan_fw_bin_len - vdll_len));
+        ctrl->vdll_len = vdll_len;
+        ctrl->cmd_buf  = (t_u8 *)wifi_get_vdllcommand_buffer();
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handle the multi_chan info event
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pevent       A pointer to event buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_process_vdll_event(pmlan_private pmpriv, t_u8 *pevent)
+{
+    mlan_status status      = MLAN_STATUS_SUCCESS;
+    vdll_ind *ind           = MNULL;
+    t_u32 offset            = 0;
+    t_u16 block_len         = 0;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    vdll_dnld_ctrl *ctrl    = &pmadapter->vdll_ctrl;
+
+    ENTER();
+    ind = (vdll_ind *)(pevent + sizeof(mlan_event_id));
+
+    switch (wlan_le16_to_cpu(ind->type))
+    {
+        case VDLL_IND_TYPE_REQ:
+            offset    = wlan_le32_to_cpu(ind->offset);
+            block_len = wlan_le16_to_cpu(ind->block_len);
+#if CONFIG_FW_VDLL_DEBUG
+            wevt_d("VDLL_IND: type=%d offset = 0x%x, len = %d, vdll_len=0x%x", wlan_le16_to_cpu(ind->type), offset,
+                   block_len, ctrl->vdll_len);
+#endif
+            if (offset <= ctrl->vdll_len)
+            {
+                block_len = MIN(block_len, ctrl->vdll_len - offset);
+                status    = wlan_download_vdll_block(pmadapter, ctrl->vdll_mem + offset, block_len);
+                if (status)
+                {
+                    wevt_d("Fail to download VDLL block");
+                }
+                if (pmadapter->vdll_in_progress == MFALSE)
+                {
+                    (void)pmadapter->callbacks.moal_start_timer(pmadapter->pmoal_handle, pmadapter->vdll_timer, MFALSE,
+                                                                2000);
+                    pmadapter->vdll_in_progress = MTRUE;
+                }
+                else
+                {
+                    (void)pmadapter->callbacks.moal_reset_timer(pmadapter->pmoal_handle, pmadapter->vdll_timer);
+                }
+            }
+            else
+            {
+                wevt_d("Invalid VDLL req: offset=0x%x, len=%d, vdll_len=0x%x", offset, block_len, ctrl->vdll_len);
+            }
+            break;
+
+        case VDLL_IND_TYPE_OFFSET:
+            offset = wlan_le32_to_cpu(ind->offset);
+#if CONFIG_FW_VDLL_DEBUG
+            wevt_d("VDLL_IND (OFFSET): vdll_len=0x%x", offset);
+#endif
+            wlan_get_vdll_image(pmadapter, offset);
+            break;
+        case VDLL_IND_TYPE_ERR_SIG:
+            wevt_d("VDLL_IND (SIG ERR).");
+            break;
+        case VDLL_IND_TYPE_ERR_ID:
+            wevt_d("VDLL_IND (ID ERR).");
+            break;
+#if defined(SD9177)
+        case VDLL_IND_TYPE_ERR_SECURE:
+            wevt_d("VDLL_IND (SECURE ERR).");
+            break;
+        case VDLL_IND_TYPE_COMPLETE:
+            wevt_d("VDLL_IND (ID COMPLETE).");
+            break;
+#elif defined(SD8978) || defined(SD8987) || defined(SD8997)
+        case VDLL_IND_TYPE_INTF_RESET:
+            wevt_d("VDLLV2_IND (INTF RESET).");
+            sd_wifi_reset_ports();
+            break;
+#endif
+        default:
+            wevt_d("unknown vdll ind type=%d", ind->type);
+            break;
+    }
+    LEAVE();
+    return status;
+}
+#endif /* CONFIG_FW_VDLL */
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+/**
+ *  @brief This function prepares command of independent reset.
+ *
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_ind_rst_cfg(HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    mlan_ds_ind_rst_cfg *pdata_ind_rst            = (mlan_ds_ind_rst_cfg *)pdata_buf;
+    HostCmd_DS_INDEPENDENT_RESET_CFG *ind_rst_cfg = (HostCmd_DS_INDEPENDENT_RESET_CFG *)&cmd->params.ind_rst_cfg;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_INDEPENDENT_RESET_CFG);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_INDEPENDENT_RESET_CFG) + S_DS_GEN);
+
+    ind_rst_cfg->action = wlan_cpu_to_le16(cmd_action);
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        ind_rst_cfg->ir_mode  = pdata_ind_rst->ir_mode;
+        ind_rst_cfg->gpio_pin = pdata_ind_rst->gpio_pin;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+/**
+ *  @brief This function handles the command response of independent reset
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to command buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_ind_rst_cfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *misc                              = MNULL;
+    const HostCmd_DS_INDEPENDENT_RESET_CFG *ind_rst_cfg = (HostCmd_DS_INDEPENDENT_RESET_CFG *)&resp->params.ind_rst_cfg;
+
+    ENTER();
+
+    if (pioctl_buf)
+    {
+        misc = (mlan_ds_misc_cfg *)pioctl_buf->pbuf;
+
+        if (wlan_le16_to_cpu(ind_rst_cfg->action) == HostCmd_ACT_GEN_GET)
+        {
+            misc->param.ind_rst_cfg.ir_mode  = ind_rst_cfg->ir_mode;
+            misc->param.ind_rst_cfg.gpio_pin = ind_rst_cfg->gpio_pin;
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/**
+ *  @brief This function sends boot sleep configure command to firmware.
+ *
+ *  @param pmpriv         A pointer to mlan_private structure
+ *  @param cmd          Hostcmd ID
+ *  @param cmd_action   Command action
+ *  @param pdata_buf    A void pointer to information buffer
+ *  @return             MLAN_STATUS_SUCCESS/ MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_cmd_boot_sleep(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    HostCmd_DS_BOOT_SLEEP *boot_sleep = MNULL;
+    t_u16 enable                      = *(t_u16 *)pdata_buf;
+
+    ENTER();
+
+    cmd->command       = wlan_cpu_to_le16(HostCmd_CMD_BOOT_SLEEP);
+    boot_sleep         = &cmd->params.boot_sleep;
+    boot_sleep->action = wlan_cpu_to_le16(cmd_action);
+    boot_sleep->enable = wlan_cpu_to_le16(enable);
+
+    cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_BOOT_SLEEP));
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of boot sleep cfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_boot_sleep(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_BOOT_SLEEP *boot_sleep = &resp->params.boot_sleep;
+    mlan_ds_misc_cfg *cfg             = (mlan_ds_misc_cfg *)pioctl_buf->pbuf;
+
+    ENTER();
+
+    cfg->param.boot_sleep = wlan_le16_to_cpu(boot_sleep->enable);
+    PRINTM(MCMND, "boot sleep cfg status %u", cfg->param.boot_sleep);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of hs wakeup reason.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_hs_wakeup_reason(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_void *pdata_buf)
+{
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_HS_WAKEUP_REASON);
+    cmd->size    = wlan_cpu_to_le16((sizeof(HostCmd_DS_HS_WAKEUP_REASON)) + S_DS_GEN);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of
+ *          hs wakeup reason
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to command buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_hs_wakeup_reason(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_HS_WAKEUP_REASON *hs_wakeup_reason = (HostCmd_DS_HS_WAKEUP_REASON *)&resp->params.hs_wakeup_reason;
+    mlan_ds_pm_cfg *pm_cfg                        = MNULL;
+
+    ENTER();
+
+    pm_cfg                                       = (mlan_ds_pm_cfg *)pioctl_buf->pbuf;
+    pm_cfg->param.wakeup_reason.hs_wakeup_reason = wlan_le16_to_cpu(hs_wakeup_reason->wakeup_reason);
+    pioctl_buf->data_read_written                = sizeof(mlan_ds_pm_cfg);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of TX_FRAME
+ *
+ *  @param pmpriv      A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_tx_frame(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_void *pdata_buf)
+{
+    t_u16 cmd_size                          = 0;
+    HostCmd_DS_80211_TX_FRAME *tx_frame_cmd = &cmd->params.tx_frame;
+    mlan_ds_misc_tx_frame *tx_frame         = (mlan_ds_misc_tx_frame *)pdata_buf;
+    TxPD *plocal_tx_pd                      = (TxPD *)tx_frame_cmd->buffer;
+    t_u32 pkt_type                          = 0;
+    t_u32 tx_control                        = 0;
+    t_u8 *pdata                             = tx_frame->tx_buf;
+    t_u16 data_len                          = tx_frame->data_len;
+
+    ENTER();
+    cmd->command         = wlan_cpu_to_le16(HostCmd_CMD_802_11_TX_FRAME);
+    cmd_size             = sizeof(HostCmd_DS_80211_TX_FRAME) + S_DS_GEN;
+    tx_frame_cmd->action = 0;
+    tx_frame_cmd->status = 0;
+    (void)__memcpy(pmpriv->adapter, &tx_frame_cmd->band_config, (t_u8 *)&tx_frame->bandcfg, sizeof(t_u8));
+    tx_frame_cmd->channel = tx_frame->channel;
+
+    if (tx_frame->buf_type == MLAN_BUF_TYPE_RAW_DATA)
+    {
+        (void)__memcpy(pmpriv->adapter, &pkt_type, tx_frame->tx_buf, sizeof(pkt_type));
+        (void)__memcpy(pmpriv->adapter, &tx_control, tx_frame->tx_buf + sizeof(pkt_type), sizeof(tx_control));
+        data_len -= sizeof(pkt_type) + sizeof(tx_control);
+        pdata += sizeof(pkt_type) + sizeof(tx_control);
+    }
+    (void)__memcpy(pmpriv->adapter, tx_frame_cmd->buffer + sizeof(TxPD), pdata, data_len);
+
+    (void)__memset(pmpriv->adapter, plocal_tx_pd, 0, sizeof(TxPD));
+    plocal_tx_pd->bss_num       = GET_BSS_NUM(pmpriv);
+    plocal_tx_pd->bss_type      = pmpriv->bss_type;
+    plocal_tx_pd->tx_pkt_length = (t_u16)data_len;
+    plocal_tx_pd->priority      = (t_u8)tx_frame->priority;
+    plocal_tx_pd->tx_pkt_offset = sizeof(TxPD);
+    plocal_tx_pd->pkt_delay_2ms = 0xff;
+
+    if (tx_frame->buf_type == MLAN_BUF_TYPE_RAW_DATA)
+    {
+        plocal_tx_pd->tx_pkt_type = (t_u16)pkt_type;
+        plocal_tx_pd->tx_control  = tx_control;
+    }
+
+    if (tx_frame->flags & MLAN_BUF_FLAG_TX_STATUS)
+    {
+#ifdef TXPD_RXPD_V3
+        plocal_tx_pd->tx_control_1 |= tx_frame->tx_seq_num << 8;
+#else
+        plocal_tx_pd->tx_token_id = (t_u8)tx_frame->tx_seq_num;
+#endif
+        plocal_tx_pd->flags |= MRVDRV_TxPD_FLAGS_TX_PACKET_STATUS;
+    }
+
+    endian_convert_TxPD(plocal_tx_pd);
+    cmd_size += sizeof(TxPD) + data_len;
+    cmd->size = wlan_cpu_to_le16(cmd_size);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_glue.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_glue.c
new file mode 100644
index 0000000000..a577e3d79c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_glue.c
@@ -0,0 +1,8073 @@
+/** @file mlan_glue.c
+ *
+ *  @brief This file acts as a glue between legacy wlan code and mlan based wlan
+ *  code
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+#include <wifi_events.h>
+#include <wifi-debug.h>
+
+#include <wifi.h>
+#include "wifi-internal.h"
+#if defined(RW610)
+#include "wifi-imu.h"
+#include "fsl_ocotp.h"
+#else
+#include "wifi-sdio.h"
+#endif
+
+#if CONFIG_WPA_SUPP
+#include "wifi_nxp.h"
+#endif
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+#if CONFIG_WIFI_FW_DEBUG
+#define FW_DEBUG_INFO_SIZE 400
+#endif
+#define RUTXCMD_RESP_BUFF_SIZE 1024
+
+static const uint8_t wpa2_akmp_oui[4] = {0x00, 0x0f, 0xac, 0x01};
+#ifdef WLAN_LOW_POWER_ENABLE
+bool low_power_mode;
+#endif
+bool cal_data_valid = 0;
+static uint8_t *cal_data;
+static uint32_t cal_data_len;
+
+bool mac_addr_valid;
+static uint8_t *mac_addr;
+#if CONFIG_WIFI_TX_BUFF
+#if CONFIG_AMSDU_IN_AMPDU
+uint16_t tx_buf_size = MLAN_TX_DATA_BUF_SIZE_4K;
+#else
+uint16_t tx_buf_size = MLAN_TX_DATA_BUF_SIZE_2K;
+#endif
+#endif
+#ifdef RW610
+extern t_u32 last_resp_rcvd;
+#endif
+
+extern uint8_t dev_mac_addr[MLAN_MAC_ADDR_LENGTH];
+extern uint8_t dev_mac_addr_uap[MLAN_MAC_ADDR_LENGTH];
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+extern ftm_start_param ftm_param;
+static char ftm_address[255] = CIVIC_ADDRESS;
+#if CONFIG_WLS_CSI_PROC
+extern uint8_t wls_data[WLS_CSI_DATA_LEN];
+#endif
+#endif
+
+#if CONFIG_WPA2_ENTP
+bool scan_enable_wpa2_enterprise_ap_only;
+#endif
+
+#if CONFIG_11K
+typedef MLAN_PACK_START struct _Event_Gen_t
+{
+    /** Event ID */
+    uint16_t event_id;
+    /** BSS index number for multiple BSS support */
+    uint8_t bss_index;
+    /** BSS type */
+    uint8_t bss_type;
+    /** No of bytes in packet including this field */
+    uint16_t length;
+    /** tlv */
+    uint8_t tlv[1];
+} MLAN_PACK_END Event_Gen_t;
+#endif
+
+/*
+ *  fixme: This entry is not present in mlan_fw.h. It is likely possible
+ *  that this code is no-op in the firmware. Keeping it as it is for
+ *  maintaining backward compatibility. Can be removed later.
+ */
+#define host_CMD_802_11_AUTHENTICATE 0x0011
+
+/* Following is allocated in mlan_register */
+mlan_adapter *mlan_adap;
+
+static mlan_device mlan_dev;
+
+uint8_t g_rssi;
+int16_t g_bcn_nf_last;
+
+/* fixme: This global variable is needed
+ *  to save the correct event since SLP_CFRM command
+ *  returns incorrect bitmap. This will be  further investigated
+ *  and if possile global variable will be removed.*/
+static t_u16 ps_event;
+
+#if CONFIG_NET_MONITOR
+/* record status */
+bool g_monitor_status = false;
+
+/* monitor recv data user callback */
+int (*net_monitor_callback)(void *buffer, t_u16 data_len) = NULL;
+#endif
+
+int mlan_subsys_init(void);
+int mlan_subsys_deinit(void);
+
+void wifi_get_mac_address_from_cmdresp(const HostCmd_DS_COMMAND *resp, uint8_t *get_mac_addr);
+void wifi_get_value1_from_cmdresp(const HostCmd_DS_COMMAND *resp, uint32_t *dev_value1);
+void wifi_get_firmware_ver_ext_from_cmdresp(const HostCmd_DS_COMMAND *resp, uint8_t *fw_ver_ext);
+int wifi_set_tx_power_ext(uint32_t len, uint32_t *power_data);
+int wifi_send_bss_ioctl(mlan_ds_bss *bss);
+
+void wifi_prepare_get_fw_ver_ext_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number, int version_str_sel);
+void wifi_prepare_get_value1(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+void wifi_prepare_enable_amsdu_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+void wifi_prepare_get_mac_addr_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+void wifi_prepare_get_hw_spec_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+void wifi_prepare_set_mac_addr_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+void wifi_prepare_set_cal_data_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+void wifi_prepare_reconfigure_tx_buf_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+void wlan_prepare_mac_control_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+
+#ifdef OTP_CHANINFO
+void wifi_prepare_get_channel_region_cfg_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number);
+#endif
+
+void wrapper_wlan_cmd_11n_cfg(HostCmd_DS_COMMAND *cmd);
+void wrapper_deliver_amsdu_subframe(pmlan_buffer amsdu_pmbuf, t_u8 *data, t_u16 pkt_len);
+int wrapper_wlan_set_regiontable(t_u8 region, t_u16 band);
+int wrapper_wlan_handle_rx_packet(t_u16 datalen, RxPD *rxpd, void *p, void *payload);
+int wrapper_get_wpa_ie_in_assoc(uint8_t *wpa_ie);
+
+int wrapper_wlan_handle_amsdu_rx_packet(const t_u8 *rcvdata, const t_u16 datalen);
+
+void wlan_process_hang(uint8_t fw_reload);
+
+/*
+ * The command event received from the firmware (e.g. EVENT_ADDBA) cannot
+ * be processed immediately. We need to do it the WLC manager context. For
+ * that we will save the buffer lest some other event destroy it. WLC
+ * manager will be notified of this event.
+ *
+ * Returns NULL if buffer allocation failed.
+ */
+static void *wifi_11n_save_request(Event_Ext_t *evt)
+{
+#if !CONFIG_MEM_POOLS
+    void *dot11n_eventbuf = OSA_MemoryAllocate(evt->length);
+#else
+    void *dot11n_eventbuf                     = OSA_MemoryPoolAllocate(buf_256_MemoryPool);
+#endif
+
+    if (dot11n_eventbuf == MNULL)
+    {
+        wifi_w("11n eventbuf alloc failed %d", evt->length);
+        return NULL;
+    }
+
+    (void)memcpy((void *)dot11n_eventbuf, (const void *)evt, evt->length);
+    return dot11n_eventbuf;
+}
+
+
+void wrapper_deliver_amsdu_subframe(pmlan_buffer amsdu_pmbuf, t_u8 *data, t_u16 pkt_len)
+{
+    RxPD *prx_pd = (RxPD *)(void *)amsdu_pmbuf->pbuf;
+    w_pkt_d("[amsdu] [push]: BSS Type: %d L: %d", prx_pd->bss_type, pkt_len);
+    wm_wifi.amsdu_data_input_callback(prx_pd->bss_type, data, pkt_len);
+}
+
+static mlan_status wrapper_moal_recv_packet(IN t_void *pmoal_handle, IN pmlan_buffer pmbuf)
+{
+    RxPD *prx_pd = (RxPD *)(void *)(pmbuf->pbuf + pmbuf->data_offset);
+    if (pmbuf->data_offset != 0U)
+    {
+        wifi_e("pmbuf->data_offset != 0 (%d)?", pmbuf->data_offset);
+        while (true)
+        {
+            ;
+        }
+    }
+
+    w_pkt_d("[push] %p + %d:  DELV: %p L: %d", pmbuf->pbuf, pmbuf->data_offset, pmbuf->lwip_pbuf, pmbuf->data_len);
+
+    wm_wifi.deliver_packet_above_callback((void *)prx_pd, prx_pd->bss_type, pmbuf->lwip_pbuf);
+
+#if !(CONFIG_TX_RX_ZERO_COPY) && !(FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER)
+    /* Free RxPD */
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmbuf->pbuf);
+    OSA_MemoryFree(pmbuf);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf->pbuf);
+    OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf);
+#endif
+
+#endif
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Copy memory from one area to another
+ *
+ *  @param pmoal Pointer to the MOAL context
+ *  @param pdest    Pointer to the dest memory
+ *  @param psrc     Pointer to the src memory
+ *  @param num      Number of bytes to move
+ *  @param dest_size size of dest memory.
+ *
+ *  @return         Pointer to the dest memory
+ */
+t_void *wrapper_moal_memcpy_ext(t_void *pmoal, t_void *pdest, const t_void *psrc, t_u32 num, t_u32 dest_size)
+{
+    t_void *p = pdest;
+    if (pdest && psrc && num && dest_size)
+        p = memcpy(pdest, psrc, MIN(num, dest_size));
+
+    return p;
+}
+
+/** moal_init_timer*/
+static mlan_status wrapper_moal_init_timer(IN t_void *pmoal_handle,
+                                           OUT t_void *ptimer,
+                                           IN t_void (*callback)(osa_timer_arg_t arg),
+                                           IN t_void *pcontext)
+{
+    w_tmr_d("Creating timer");
+
+    /*
+     * As can be seen from the arguments to our function, we do not
+     * have a timer period parameter. Nor do we have a parameter to
+     * specify whether the user wants a periodic or a one-shot
+     * timer. We have to wait for these paramters till the next call to
+     * wrapper_moal_start_timer.
+     *
+     * But a timer object cannot be created in
+     * wrapper_moal_start_timer. Because the timer handle is passed by
+     * value.
+     *
+     * Considering all this we will need to create the timer object in the
+     * current function. We will provide a dummy time here one and
+     * change in later. One assumption from the current observation is
+     * that only one shot timers are created. So we will assume this
+     * and raise assert in *timer_start if this is not the case.
+     */
+#define DUMMY_TIME_PARAM 10
+
+    osa_status_t status = OSA_TimerCreate((osa_timer_handle_t)ptimer, DUMMY_TIME_PARAM, callback, pcontext,
+                                          KOSA_TimerOnce, OSA_TIMER_NO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        w_tmr_e("Unable to create timer");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** moal_start_timer*/
+static mlan_status wrapper_moal_start_timer(IN t_void *pmoal_handle, IN t_void *ptimer, IN bool periodic, IN t_u32 msec)
+{
+    w_tmr_d("Starting timer: %p for %d mS", ptimer, msec);
+
+    if (periodic == MTRUE)
+    {
+        /* Check note in wrapper_moal_init_timer for details */
+        w_tmr_w("Periodic is not supported temporarily");
+        while (true)
+        {
+            ;
+        }
+        // wmpanic();
+    }
+
+    osa_status_t status = OSA_TimerChange((osa_timer_handle_t)ptimer, msec, 0);
+    if (status != KOSA_StatusSuccess)
+    {
+        w_tmr_e("Unable to change period in timer");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    status = OSA_TimerActivate((osa_timer_handle_t)ptimer);
+    if (status != KOSA_StatusSuccess)
+    {
+        w_tmr_e("Unable to start timer");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** moal_reset_timer*/
+static mlan_status wrapper_moal_reset_timer(IN t_void *pmoal_handle, IN t_void *ptimer)
+{
+    w_tmr_d("Resetting timer: %p", ptimer);
+
+    int rv = OSA_TimerReset((osa_timer_handle_t)ptimer);
+    if (rv != WM_SUCCESS)
+    {
+        w_tmr_e("Unable to reset timer.");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** moal_stop_timer*/
+static mlan_status wrapper_moal_stop_timer(IN t_void *pmoal_handle, IN t_void *ptimer)
+{
+    w_tmr_d("Stopping timer: %p", ptimer);
+
+    int rv = OSA_TimerDeactivate((osa_timer_handle_t)ptimer);
+    if (rv != WM_SUCCESS)
+    {
+        w_tmr_e("Unable to stop timer.");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** moal_free_timer */
+static mlan_status wrapper_moal_free_timer(IN t_void *pmoal_handle, IN t_void *ptimer)
+{
+    w_tmr_d("Deleting timer: %p", *((uint32_t *)ptimer));
+
+    int rv = OSA_TimerDestroy((osa_timer_handle_t)ptimer);
+    if (rv != WM_SUCCESS)
+    {
+        w_tmr_e("Unable to delete timer.");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+static mlan_status wrapper_moal_init_lock(IN t_void *pmoal_handle, OUT t_void *plock)
+{
+#ifdef DEBUG_DEVELOPMENT
+    wmprintf("%s: Locks not needed for now\n\r", __func__);
+#endif /* DEBUG_DEVELOPMENT */
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** moal_free_lock */
+static mlan_status wrapper_moal_free_lock(IN t_void *pmoal_handle, IN t_void *plock)
+{
+#ifdef DEBUG_DEVELOPMENT
+    wmprintf("%s: Locks not needed for now\n\r", __func__);
+#endif /* DEBUG_DEVELOPMENT */
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** moal_spin_lock */
+static mlan_status wrapper_moal_spin_lock(IN t_void *pmoal_handle, IN t_void *plock)
+{
+#ifdef DEBUG_DEVELOPMENT
+    wmprintf("%s: Locks not needed for now\n\r", __func__);
+#endif /* DEBUG_DEVELOPMENT */
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** moal_spin_unlock */
+static mlan_status wrapper_moal_spin_unlock(IN t_void *pmoal_handle, IN t_void *plock)
+{
+#ifdef DEBUG_DEVELOPMENT
+    wmprintf("%s: Locks not needed for now\n\r", __func__);
+#endif /* DEBUG_DEVELOPMENT */
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if CONFIG_WMM
+/* os_semaphore_t equals (t_void *)(*pplock) */
+static mlan_status wrapper_moal_init_semaphore(IN t_void *pmoal_handle, IN const char *name, OUT t_void *plock)
+{
+    //    if (*((os_semaphore_t *)pplock) != MNULL)
+    //        return MLAN_STATUS_SUCCESS;
+
+    if (OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)plock) != KOSA_StatusSuccess)
+        return MLAN_STATUS_FAILURE;
+
+    OSA_SemaphorePost((osa_semaphore_handle_t)plock);
+    return MLAN_STATUS_SUCCESS;
+}
+
+static mlan_status wrapper_moal_free_semaphore(IN t_void *pmoal_handle, IN t_void *plock)
+{
+    //    if (*((os_semaphore_t *)pplock) == MNULL)
+    //        return MLAN_STATUS_SUCCESS;
+
+    if (OSA_SemaphoreDestroy((osa_semaphore_handle_t)plock) != KOSA_StatusSuccess)
+        return MLAN_STATUS_FAILURE;
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+static mlan_status wrapper_moal_semaphore_get(IN t_void *pmoal_handle, IN t_void *plock)
+{
+    if (OSA_SemaphoreWait((osa_semaphore_handle_t)plock, 60000) != KOSA_StatusSuccess)
+    {
+        assert(0);
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+static mlan_status wrapper_moal_semaphore_put(IN t_void *pmoal_handle, IN t_void *plock)
+{
+    if (OSA_SemaphorePost((osa_semaphore_handle_t)plock) != KOSA_StatusSuccess)
+        return MLAN_STATUS_FAILURE;
+
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/** woal_callbacks */
+static mlan_callbacks woal_callbacks = {
+    .moal_malloc      = wrapper_moal_malloc,
+    .moal_mfree       = wrapper_moal_mfree,
+    .moal_recv_packet = wrapper_moal_recv_packet,
+    .moal_memcpy_ext  = wrapper_moal_memcpy_ext,
+    .moal_init_timer  = wrapper_moal_init_timer,
+    .moal_free_timer  = wrapper_moal_free_timer,
+    .moal_start_timer = wrapper_moal_start_timer,
+    .moal_reset_timer = wrapper_moal_reset_timer,
+    .moal_stop_timer  = wrapper_moal_stop_timer,
+    .moal_init_lock   = wrapper_moal_init_lock,
+    .moal_free_lock   = wrapper_moal_free_lock,
+    .moal_spin_lock   = wrapper_moal_spin_lock,
+    .moal_spin_unlock = wrapper_moal_spin_unlock,
+#if CONFIG_WMM
+    .moal_init_semaphore = wrapper_moal_init_semaphore,
+    .moal_free_semaphore = wrapper_moal_free_semaphore,
+    .moal_semaphore_get  = wrapper_moal_semaphore_get,
+    .moal_semaphore_put  = wrapper_moal_semaphore_put,
+#endif
+};
+
+int mlan_subsys_init(void)
+{
+    (void)memcpy((void *)&mlan_dev.callbacks, (const void *)&woal_callbacks, sizeof(mlan_callbacks));
+
+    /* The mlinux driver has an array of these which is dynamically allocated
+     * in function woal_update_drv_tbl (moal_main.c). We have only one.
+     */
+    /** BSS type */
+    mlan_dev.bss_attr[0].bss_type = MLAN_BSS_TYPE_STA;
+    /** Data frame type: Ethernet II, 802.11, etc. */
+    mlan_dev.bss_attr[0].frame_type = MLAN_DATA_FRAME_TYPE_ETH_II;
+    /** The BSS is active (non-0) or not (0). */
+    mlan_dev.bss_attr[0].active = MTRUE;
+    /** BSS Priority */
+    mlan_dev.bss_attr[0].bss_priority = 0;
+    /** BSS number */
+    mlan_dev.bss_attr[0].bss_num = 0;
+    /* 11d initialization */
+    /* mlan_dev.cfg_11d = 0; */
+
+    mlan_dev.bss_attr[1].bss_type = MLAN_BSS_TYPE_UAP;
+    /** Data frame type: Ethernet II, 802.11, etc. */
+    mlan_dev.bss_attr[1].frame_type = MLAN_DATA_FRAME_TYPE_ETH_II;
+    /** The BSS is active (non-0) or not (0). */
+    mlan_dev.bss_attr[1].active = MTRUE;
+    /** BSS Priority */
+    mlan_dev.bss_attr[1].bss_priority = 0;
+    /** BSS number */
+    mlan_dev.bss_attr[1].bss_num = 0;
+
+    /* fixme: check return value above status */
+    (void)mlan_register(&mlan_dev, (t_void **)&mlan_adap);
+
+    (void)mlan_init_fw(mlan_adap);
+    /* wlan_init_adapter(mlan_adap); */
+
+    return WM_SUCCESS;
+}
+
+int mlan_subsys_deinit(void)
+{
+    wlan_clear_scan_bss();
+    (void)mlan_unregister(mlan_adap);
+    mlan_adap = MNULL;
+
+    return WM_SUCCESS;
+}
+
+
+/* Note: The saved_event_buff is allocated by the cmd resp/event handler
+   thread. We need to free it in this function */
+int wrapper_wlan_cmd_11n_addba_rspgen(void *saved_event_buff)
+{
+    Event_Ext_t *evt = (Event_Ext_t *)saved_event_buff;
+
+    (void)wifi_get_command_lock();
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    if (evt->bss_type == BSS_TYPE_STA)
+    {
+        cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, BSS_TYPE_STA);
+        (void)wlan_cmd_11n_addba_rspgen((mlan_private *)mlan_adap->priv[evt->bss_type], cmd, &evt->reason_code);
+    }
+    else if (evt->bss_type == BSS_TYPE_UAP)
+    {
+        cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, BSS_TYPE_UAP);
+
+        (void)wlan_cmd_11n_uap_addba_rspgen((mlan_private *)mlan_adap->priv[evt->bss_type], cmd, &evt->reason_code);
+    }
+    else
+    { /* Do Nothing */
+    }
+
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(saved_event_buff);
+#else
+    OSA_MemoryPoolFree(buf_256_MemoryPool, saved_event_buff);
+#endif
+
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    return 0;
+}
+
+int wrapper_wlan_cmd_11n_ba_stream_timeout(void *saved_event_buff)
+{
+    Event_Ext_t *evt = (Event_Ext_t *)saved_event_buff;
+
+    wlan_11n_ba_stream_timeout(mlan_adap->priv[evt->bss_type], (HostCmd_DS_11N_BATIMEOUT *)(void *)&evt->reason_code);
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(saved_event_buff);
+#else
+    OSA_MemoryPoolFree(buf_256_MemoryPool, saved_event_buff);
+#endif
+
+    return 0;
+}
+
+int wrapper_wlan_cmd_11n_delba_rspgen(void *saved_event_buff)
+{
+    Event_Ext_t *evt = (Event_Ext_t *)saved_event_buff;
+
+    wlan_11n_delete_bastream((mlan_private *)mlan_adap->priv[evt->bss_type], (t_u8 *)&evt->reason_code);
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(saved_event_buff);
+#else
+    OSA_MemoryPoolFree(buf_256_MemoryPool, saved_event_buff);
+#endif
+
+    return 0;
+}
+
+void wrapper_wlan_update_uap_rxrate_info(RxPD *rxpd)
+{
+    pmlan_private priv = mlan_adap->priv[1];
+
+    priv->rxpd_rate = rxpd->rx_rate;
+#ifdef SD8801
+    priv->rxpd_htinfo = rxpd->ht_info;
+#else
+    priv->rxpd_rate_info = rxpd->rate_info;
+#endif
+}
+
+int wrapper_wlan_uap_ampdu_enable(uint8_t *addr
+#if CONFIG_WMM
+                                  ,
+                                  t_u8 tid
+#endif
+)
+{
+    int ret;
+    TxBAStreamTbl *ptx_tbl;
+    mlan_private *pmpriv_uap = mlan_adap->priv[1];
+
+    if (!(pmpriv_uap->is_11n_enabled))
+        return MLAN_STATUS_SUCCESS;
+
+    wlan_request_ralist_lock(pmpriv_uap);
+    wlan_11n_update_txbastream_tbl_tx_cnt(pmpriv_uap, addr);
+    if ((ptx_tbl = wlan_11n_get_txbastream_tbl(pmpriv_uap, addr)))
+    {
+        if (
+#if CONFIG_WMM
+            !ptx_tbl->ampdu_stat[tid] && ptx_tbl->ampdu_supported[tid]
+#else
+            !ptx_tbl->ampdu_stat[0] && ptx_tbl->ampdu_supported[0]
+#endif
+            && ptx_tbl->txpkt_cnt >= ptx_tbl->txba_thresh)
+        {
+            ptx_tbl->ba_status = BA_STREAM_SETUP_INPROGRESS;
+            wlan_release_ralist_lock(pmpriv_uap);
+            ret = wlan_send_addba(pmpriv_uap,
+#if CONFIG_WMM
+                                  tid,
+#else
+                                  0,
+#endif
+                                  addr);
+            if (ret != 0)
+            {
+                wifi_d("uap failed to send addba req");
+                return MLAN_STATUS_FAILURE;
+            }
+        }
+        else
+            wlan_release_ralist_lock(pmpriv_uap);
+    }
+    else
+        wlan_release_ralist_lock(pmpriv_uap);
+    return MLAN_STATUS_SUCCESS;
+}
+
+static mlan_status do_wlan_ret_11n_addba_resp(HostCmd_DS_COMMAND *resp)
+{
+    mlan_status rv = MLAN_STATUS_SUCCESS;
+
+    if (resp->result != HostCmd_RESULT_OK)
+    {
+        wifi_d("Failed: ADDBA RESULT: %d", resp->result);
+        return MLAN_STATUS_FAILURE;
+    }
+
+    int bss_type = HostCmd_GET_BSS_TYPE(resp->seq_num);
+
+    if (bss_type == BSS_TYPE_STA)
+    {
+        mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+        rv                   = wlan_ret_11n_addba_resp(pmpriv, resp);
+    }
+    if (bss_type == BSS_TYPE_UAP)
+    {
+        mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+        rv                   = wlan_ret_11n_addba_resp(pmpriv, resp);
+    }
+
+    return rv;
+}
+
+static mlan_status do_wlan_ret_11n_addba_req(mlan_private *priv, HostCmd_DS_COMMAND *resp)
+{
+    t_u8 tid;
+    HostCmd_DS_11N_ADDBA_RSP *padd_ba_rsp = (HostCmd_DS_11N_ADDBA_RSP *)&resp->params.add_ba_rsp;
+    padd_ba_rsp->status_code              = wlan_le16_to_cpu(padd_ba_rsp->status_code);
+    TxBAStreamTbl *ptx_ba_tbl;
+
+    padd_ba_rsp->block_ack_param_set = wlan_le16_to_cpu(padd_ba_rsp->block_ack_param_set);
+    padd_ba_rsp->block_ack_tmo       = wlan_le16_to_cpu(padd_ba_rsp->block_ack_tmo);
+    padd_ba_rsp->ssn                 = (wlan_le16_to_cpu(padd_ba_rsp->ssn)) & SSN_MASK;
+    padd_ba_rsp->status_code         = wlan_le16_to_cpu(padd_ba_rsp->status_code);
+
+    tid = (padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_TID_MASK) >> BLOCKACKPARAM_TID_POS;
+
+    if (padd_ba_rsp->status_code == BA_RESULT_SUCCESS)
+    {
+        wlan_request_ralist_lock(priv);
+        if ((ptx_ba_tbl = wlan_11n_get_txbastream_tbl(priv, padd_ba_rsp->peer_mac_addr)))
+        {
+            wlan_11n_update_txbastream_tbl_ampdu_stat(priv, padd_ba_rsp->peer_mac_addr, MTRUE, tid);
+
+            PRINTM(MCMND, "ADDBA REQ: %02x:%02x:%02x:%02x:%02x:%02x tid=%d ssn=%d win_size=%d,amsdu=%d\n",
+                   padd_ba_rsp->peer_mac_addr[0], padd_ba_rsp->peer_mac_addr[1], padd_ba_rsp->peer_mac_addr[2],
+                   padd_ba_rsp->peer_mac_addr[3], padd_ba_rsp->peer_mac_addr[4], padd_ba_rsp->peer_mac_addr[5], tid,
+                   padd_ba_rsp->ssn,
+                   ((padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_WINSIZE_MASK) >> BLOCKACKPARAM_WINSIZE_POS),
+                   padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_AMSDU_SUPP_MASK);
+
+            ptx_ba_tbl->ba_status = BA_STREAM_SETUP_COMPLETE;
+
+            if ((padd_ba_rsp->block_ack_param_set & BLOCKACKPARAM_AMSDU_SUPP_MASK) && priv->add_ba_param.tx_amsdu)
+                ptx_ba_tbl->amsdu = MTRUE;
+            else
+                ptx_ba_tbl->amsdu = MFALSE;
+            wlan_release_ralist_lock(priv);
+        }
+        else
+        {
+            wlan_release_ralist_lock(priv);
+            PRINTM(MERROR, "BA stream not created\n");
+        }
+    }
+    else
+    {
+        if (padd_ba_rsp->add_rsp_result != BA_RESULT_TIMEOUT)
+        {
+            wlan_request_ralist_lock(priv);
+            if ((ptx_ba_tbl = wlan_11n_get_txbastream_tbl(priv, padd_ba_rsp->peer_mac_addr)))
+            {
+                wlan_11n_update_txbastream_tbl_ampdu_stat(priv, padd_ba_rsp->peer_mac_addr, MFALSE, tid);
+                ptx_ba_tbl->ampdu_supported[tid] = MFALSE;
+            }
+            wlan_release_ralist_lock(priv);
+        }
+        else
+        {
+            wlan_request_ralist_lock(priv);
+            if ((ptx_ba_tbl = wlan_11n_get_txbastream_tbl(priv, padd_ba_rsp->peer_mac_addr)))
+            {
+                /* Clear txpkt_cnt to avoid collision between our STA and our uAP */
+                ptx_ba_tbl->txpkt_cnt = 0;
+            }
+            wlan_release_ralist_lock(priv);
+        }
+        wifi_d("Failed: ADDBA req: %d", padd_ba_rsp->add_rsp_result);
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+static mlan_status do_wlan_ret_11n_delba(mlan_private *priv, HostCmd_DS_COMMAND *resp)
+{
+    HostCmd_DS_11N_DELBA *pdel_ba = (HostCmd_DS_11N_DELBA *)&resp->params.del_ba;
+    int tid;
+
+    pdel_ba->del_ba_param_set = wlan_le16_to_cpu(pdel_ba->del_ba_param_set);
+    tid                       = pdel_ba->del_ba_param_set >> DELBA_TID_POS;
+
+    if (pdel_ba->del_result == BA_RESULT_SUCCESS)
+    {
+        mlan_11n_update_bastream_tbl(priv, tid, pdel_ba->peer_mac_addr, TYPE_DELBA_SENT,
+                                     INITIATOR_BIT(pdel_ba->del_ba_param_set));
+    }
+    else
+    {
+        wifi_d("Failed: DELBA: %d", pdel_ba->del_result);
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+// Only Enable AMPDU for station interface
+int wrapper_wlan_sta_ampdu_enable(
+#if CONFIG_WMM
+    t_u8 tid
+#endif
+)
+{
+    int ret;
+    mlan_private *pmpriv               = (mlan_private *)mlan_adap->priv[0];
+    t_u8 cur_mac[MLAN_MAC_ADDR_LENGTH] = {0};
+    TxBAStreamTbl *ptx_tbl             = NULL;
+
+    wlan_request_ralist_lock(pmpriv);
+    if (pmpriv->media_connected == MTRUE)
+    {
+        (void)memcpy(cur_mac, pmpriv->curr_bss_params.bss_descriptor.mac_address, MLAN_MAC_ADDR_LENGTH);
+        ptx_tbl = wlan_11n_get_txbastream_tbl(pmpriv, cur_mac);
+        if (!ptx_tbl)
+        {
+            wlan_11n_create_txbastream_tbl(pmpriv, cur_mac, BA_STREAM_NOT_SETUP);
+
+            ptx_tbl              = wlan_11n_get_txbastream_tbl(pmpriv, cur_mac);
+            ptx_tbl->txba_thresh = 1;
+
+            if (pmpriv->curr_bss_params.bss_descriptor.pht_cap)
+            {
+                wlan_11n_update_txbastream_tbl_ampdu_supported(pmpriv, cur_mac, MTRUE);
+            }
+            else
+            {
+                wlan_release_ralist_lock(pmpriv);
+                return MLAN_STATUS_SUCCESS;
+            }
+        }
+    }
+    else
+    {
+        wifi_d("sta not connected: failed to send addba req");
+        wlan_release_ralist_lock(pmpriv);
+        return MLAN_STATUS_FAILURE;
+    }
+
+    wlan_11n_update_txbastream_tbl_tx_cnt(pmpriv, cur_mac);
+
+#if CONFIG_WMM
+    if (!ptx_tbl->ampdu_stat[tid] && ptx_tbl->ampdu_supported[tid] && (ptx_tbl->txpkt_cnt >= ptx_tbl->txba_thresh))
+#else
+    if (!ptx_tbl->ampdu_stat[0] && ptx_tbl->ampdu_supported[0] && (ptx_tbl->txpkt_cnt >= ptx_tbl->txba_thresh))
+#endif
+    {
+        ptx_tbl->ba_status = BA_STREAM_SETUP_INPROGRESS;
+        wlan_release_ralist_lock(pmpriv);
+        ret = wlan_send_addba(pmpriv,
+#if CONFIG_WMM
+                              tid,
+#else
+                              0,
+#endif
+                              (t_u8 *)cur_mac);
+        if (ret != 0)
+        {
+            wifi_d("sta: failed to send addba req");
+            return MLAN_STATUS_FAILURE;
+        }
+    }
+    else
+        wlan_release_ralist_lock(pmpriv);
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+int wrapper_wlan_11d_enable(t_u32 state)
+{
+    t_u32 enable_11d = state;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = 0x00;
+    cmd->result  = 0x0;
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_SNMP_MIB, HostCmd_ACT_GEN_SET,
+                             Dot11D_i, NULL, &enable_11d, cmd);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wrapper_wlan_uap_11d_enable(t_u32 state)
+{
+    t_u32 enable_11d = state;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_UAP);
+    cmd->result  = 0x0;
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_SNMP_MIB, HostCmd_ACT_GEN_SET,
+                             Dot11D_i, NULL, &enable_11d, cmd);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wifi_11h_enable(void)
+{
+    t_u32 enable_11h = (t_u32)ENABLE_11H;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_SNMP_MIB, HostCmd_ACT_GEN_SET,
+                                   (t_u32)Dot11H_i, NULL, &enable_11h, cmd);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wrapper_wlan_ecsa_enable(void)
+{
+    bool ecsa_enable = MTRUE;
+
+    if ((mlan_adap->fw_cap_info & FW_CAPINFO_ECSA) == 0U)
+    {
+        return -WM_FAIL;
+    }
+
+    mlan_adap->ecsa_enable = MTRUE;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_SNMP_MIB, HostCmd_ACT_GEN_SET,
+                                   (t_u32)ECSAEnable_i, NULL, &ecsa_enable, cmd);
+
+    return wifi_wait_for_cmdresp(NULL);
+}
+
+int wrapper_wlan_cmd_get_hw_spec(void)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+    (void)wlan_cmd_get_hw_spec((mlan_private *)mlan_adap->priv[0], cmd);
+    (void)wifi_wait_for_cmdresp(NULL);
+    return 0;
+}
+
+mlan_status wrapper_wlan_cmd_mgmt_ie(int bss_type, void *buffer, unsigned int len, t_u16 action)
+{
+    void *pdata_buf = NULL;
+    HostCmd_DS_MGMT_IE_LIST_CFG ds_mgmt_ie_list_cfg;
+    mlan_status status = MLAN_STATUS_SUCCESS;
+
+    (void)wifi_get_command_lock();
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num       = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, bss_type);
+    cmd->result = 0x0;
+
+    (void)memset(&ds_mgmt_ie_list_cfg, 0x00, sizeof(HostCmd_DS_MGMT_IE_LIST_CFG));
+
+    (void)memcpy((void *)&ds_mgmt_ie_list_cfg, (const void *)buffer, len);
+
+    pdata_buf = &ds_mgmt_ie_list_cfg;
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+        status = wlan_ops_uap_prepare_cmd((mlan_private *)mlan_adap->priv[1], HOST_CMD_APCMD_SYS_CONFIGURE, action, 0,
+                                          NULL, pdata_buf, cmd);
+    else
+        status = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MGMT_IE_LIST, action, 0, NULL,
+                                          pdata_buf, cmd);
+
+    (void)wifi_wait_for_cmdresp(buffer);
+    return status;
+}
+
+int wrapper_wlan_handle_rx_packet(t_u16 datalen, RxPD *rxpd, void *p, void *payload)
+{
+    w_pkt_d("[recv]                  : %p T: %d L: %d", p, rxpd->rx_pkt_type, rxpd->rx_pkt_length);
+
+#if !(CONFIG_TX_RX_ZERO_COPY) && !(FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER)
+    /* fixme: Check if mlan buffer can be allocated from standard mlan
+       function */
+#if !CONFIG_MEM_POOLS
+    pmlan_buffer pmbuf = OSA_MemoryAllocate(sizeof(mlan_buffer));
+#else
+    pmlan_buffer pmbuf = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+
+    if (pmbuf == MNULL)
+    {
+        /* No mlan_buffer available. Drop this packet */
+        /* fixme: Need to note this event. */
+        wifi_w("No memory available. Have to drop packet.");
+        return -WM_FAIL;
+    }
+#else
+    pmlan_buffer pmbuf = (pmlan_buffer)((t_u8 *)rxpd - INTF_HEADER_LEN - sizeof(mlan_buffer));
+#endif
+    /** Buffer descriptor, e.g. skb in Linux */
+    /* Note: We are storing payload member here. We need to unwind
+       pointer when passing pbuf to lwip */
+    pmbuf->pdesc = payload;
+
+    /* Store it for later retrivval. mlan stack does not know about this */
+    pmbuf->lwip_pbuf = p;
+
+    /* fixme: check that no data is accessed after this pointer
+      Note: Important: mlan requires RxPD in number of places. We
+    already have duplicated the ethernet packet in the pbuf. We cannot
+    afford to duplicate the entire SDIO buffer and reduplicate the
+    ethernet part of it into pbuf which the lwip requires. So, we will
+    duplicate only the RxPD for ourselves. We will have to change all
+    the code which assumes that there is ethernet packet after RxPD */
+    /** Pointer to buffer */
+    /* fixme: CHK this*/
+#if !(CONFIG_TX_RX_ZERO_COPY) && !(FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER)
+#if !CONFIG_MEM_POOLS
+    pmbuf->pbuf = (t_u8 *)OSA_MemoryAllocate(sizeof(RxPD));
+#else
+    pmbuf->pbuf        = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+    if (pmbuf->pbuf == MNULL)
+    {
+        /* No buffer available. Drop this packet */
+        /* fixme: Need to note this event. */
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(pmbuf);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf);
+#endif
+        wifi_w("No memory available. Have to drop packet.");
+        return -WM_FAIL;
+    }
+    (void)memcpy((void *)pmbuf->pbuf, (const void *)rxpd, sizeof(RxPD));
+#else
+    pmbuf->pbuf        = (t_u8 *)rxpd;
+#endif
+    /** Offset to data */
+    /* This should ideally be INTF_HEADER_LEN. But we not be storing
+       initial INTF_HEADER_LEN bytes. We will store RxPD directly */
+    /* fixme: CHK this*/
+    pmbuf->data_offset = 0;
+
+    /** Data length */
+    /* fixme: CHK this*/
+    pmbuf->data_len = datalen;
+    /** Buffer type: data, cmd, event etc. */
+    pmbuf->buf_type = MLAN_BUF_TYPE_DATA;
+    /** Fields below are valid for data packet only */
+    /** QoS priority */
+    /* t_u32 priority; */
+    /** Time stamp when packet is received (seconds) */
+    /* t_u32 in_ts_sec; */
+    /** Time stamp when packet is received (micro seconds) */
+    /* t_u32 in_ts_usec; */
+    /** Time stamp when packet is processed (seconds) */
+    /* t_u32 out_ts_sec; */
+    /** Time stamp when packet is processed (micro seconds) */
+    /* t_u32 out_ts_usec; */
+
+    /** Fields below are valid for MLAN module only */
+    /** Pointer to parent mlan_buffer */
+    /* struct _mlan_buffer *pparent; */
+    /** Use count for this buffer */
+    /* t_u32 use_count; */
+
+    mlan_status rv = wlan_handle_rx_packet(mlan_adap, pmbuf);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        /* mlan did not accept this packet for some reason. Some
+           probable reasons are - duplicate packet - packet outside
+           the current 11n aggregation window.
+
+           We need to free allocated structures.
+        */
+#if !(CONFIG_TX_RX_ZERO_COPY) && !(FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER)
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(pmbuf->pbuf);
+        OSA_MemoryFree(pmbuf);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf->pbuf);
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf);
+#endif
+#endif
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+/* fixme: This AMSDU special handling needs to be redesigned. We could
+   create a copy of the SDIO packet buffer for _every_ packet AMSDU and
+   non-AMSDU. We could then use RAW_PBUF allocation to allocate pbufs
+   during final step of packet delivery to lwip stack.
+
+   Note: This is not AMSDU inside AMPDU. This is a pure AMSDU.
+   Note: We will not be duplicating the AMSDU packet from the SDIO
+   buffer. So, we have to ensure that there are no race
+   conditions. i.e. the SDIO buffer is not overwritten in the background.
+*/
+int wrapper_wlan_handle_amsdu_rx_packet(const t_u8 *rcvdata, const t_u16 datalen)
+{
+    w_pkt_d("[amsdu] [recv]       : L: %d", datalen);
+
+    RxPD *rxpd = (RxPD *)(void *)((t_u8 *)rcvdata + INTF_HEADER_LEN);
+
+    /* fixme: Check if mlan buffer can be allocated from standard mlan
+       function */
+#if !CONFIG_MEM_POOLS
+    pmlan_buffer pmbuf = OSA_MemoryAllocate(sizeof(mlan_buffer));
+#else
+    pmlan_buffer pmbuf = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+#endif
+
+    if (pmbuf == MNULL)
+    {
+        /* No mlan_buffer available. Drop this packet */
+        /* fixme: Need to note this event. */
+        w_pkt_e("[amsdu] No memory available. Have to drop packet");
+        return -WM_FAIL;
+    }
+    (void)memset(pmbuf, 0x00, sizeof(mlan_buffer));
+
+    /** Buffer descriptor, e.g. skb in Linux */
+    /* Note: We are storing payload member here. We need to unwind
+       pointer when passing pbuf to lwip */
+    pmbuf->pdesc = ((t_u8 *)rcvdata + INTF_HEADER_LEN + rxpd->rx_pkt_offset);
+
+    /* Store it for later retrivval. mlan stack does not know about this */
+    pmbuf->lwip_pbuf = NULL;
+
+    /* Since this is an AMSDU packet we have the entire SDIO buffer
+       with us. So we do not need to duplicate RxPD
+    */
+    pmbuf->pbuf = (t_u8 *)rxpd;
+    /** Offset to data */
+    pmbuf->data_offset = 0;
+
+    /** Data length */
+    /* fixme: CHK this*/
+    pmbuf->data_len = datalen;
+    /** Buffer type: data, cmd, event etc. */
+    pmbuf->buf_type = MLAN_BUF_TYPE_DATA;
+    /** Fields below are valid for data packet only */
+    /** QoS priority */
+    /* t_u32 priority; */
+    /** Time stamp when packet is received (seconds) */
+    /* t_u32 in_ts_sec; */
+    /** Time stamp when packet is received (micro seconds) */
+    /* t_u32 in_ts_usec; */
+    /** Time stamp when packet is processed (seconds) */
+    /* t_u32 out_ts_sec; */
+    /** Time stamp when packet is processed (micro seconds) */
+    /* t_u32 out_ts_usec; */
+
+    /** Fields below are valid for MLAN module only */
+    /** Pointer to parent mlan_buffer */
+    /* struct _mlan_buffer *pparent; */
+    /** Use count for this buffer */
+    /* t_u32 use_count; */
+
+    if (rxpd->bss_type == (t_u8)MLAN_BSS_ROLE_STA)
+    {
+        (void)wlan_handle_rx_packet(mlan_adap, pmbuf);
+    }
+    else
+    {
+        pmlan_private priv = wlan_get_priv(mlan_adap, MLAN_BSS_ROLE_UAP);
+        pmbuf->data_len    = rxpd->rx_pkt_length;
+        pmbuf->data_offset += rxpd->rx_pkt_offset;
+        (void)wlan_11n_deaggregate_pkt(priv, pmbuf);
+    }
+    /* if (rv != MLAN_STATUS_SUCCESS) { */
+    /*
+      We need to free allocated structures. In case of AMSDU this pmbuf
+      is not freed inside mlan
+    */
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmbuf);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, pmbuf);
+#endif
+
+    /* return -WM_FAIL; */
+    /* } */
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_NET_MONITOR
+void register_monitor_user_callback(int (*monitor_cb)(void *frame, t_u16 len))
+{
+    net_monitor_callback = monitor_cb;
+}
+
+void deregister_monitor_user_callback()
+{
+    net_monitor_callback = NULL;
+}
+
+void set_monitor_flag(bool flag)
+{
+    g_monitor_status = flag;
+}
+
+bool get_monitor_flag()
+{
+    return g_monitor_status;
+}
+
+void user_recv_monitor_data(const t_u8 *rcvdata)
+{
+    t_s8 rssi              = 0;
+    t_u16 datalen          = 0;
+    t_u8 *net_monitor_data = NULL;
+    RxPD *rxpd             = (RxPD *)((t_u8 *)rcvdata + INTF_HEADER_LEN);
+    t_u16 inimupkt_len     = *(t_u16 *)rcvdata;
+
+    datalen = rxpd->rx_pkt_length + sizeof(t_s8);
+    rssi    = rxpd->snr - rxpd->nf;
+
+    if ((rxpd->rx_pkt_length + rxpd->rx_pkt_offset + INTF_HEADER_LEN) != inimupkt_len)
+    {
+        wifi_w("rx_pkt_length + rx_pkt_offset + INTF_HEADER_LEN is not equal to inimupkt_len \n\r");
+        wifi_w("Invalid data, discard \n\r");
+        wifi_w("rx_pkt_length :%d \n\r", rxpd->rx_pkt_length);
+        wifi_w("rx_pkt_offset :%d \n\r", rxpd->rx_pkt_offset);
+        wifi_w("inimupkt_len  :%d \n\r", inimupkt_len);
+        return;
+    }
+
+    if (net_monitor_callback != NULL)
+    {
+        net_monitor_data = OSA_MemoryAllocate(datalen);
+
+        if (!net_monitor_data)
+        {
+            wifi_w("No mem. Cannot process net monitor data");
+            return;
+        }
+
+        memcpy(net_monitor_data, &rssi, sizeof(t_s8));
+        memcpy(net_monitor_data + sizeof(t_s8), ((t_u8 *)rcvdata + INTF_HEADER_LEN + rxpd->rx_pkt_offset),
+               rxpd->rx_pkt_length);
+
+        net_monitor_callback((void *)net_monitor_data, datalen);
+
+        OSA_MemoryFree(net_monitor_data);
+    }
+
+    return;
+}
+#endif
+void wrapper_wlan_cmd_11n_cfg(HostCmd_DS_COMMAND *cmd)
+{
+    mlan_ds_11n_tx_cfg txcfg = {/** HTTxCap */
+                                .httxcap = DOT11N_CFG_ENABLE_GREENFIELD_XMIT | DOT11N_CFG_ENABLE_SHORT_GI_20MHZ |
+                                           DOT11N_CFG_ENABLE_SHORT_GI_40MHZ,
+                                /** HTTxInfo */
+                                .httxinfo = DOT11N_CFG_ENABLE_RIFS,
+                                /** Band selection */
+                                .misc_cfg = BAND_SELECT_BOTH};
+
+    (void)wlan_cmd_11n_cfg((mlan_private *)mlan_adap->priv[0], cmd, HostCmd_ACT_GEN_SET, &txcfg);
+}
+
+/*
+  fixme: Following three functions will not be needed when
+  wlan_11h_handle_event_chanswann is used to handle the relevant event */
+void set_event_chanswann(void)
+{
+    mlan_adap->state_11h.recvd_chanswann_event = MTRUE;
+}
+
+void clear_event_chanswann(void)
+{
+    mlan_adap->state_11h.recvd_chanswann_event = MFALSE;
+}
+
+void wrapper_wlan_11d_clear_parsedtable(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    (void)wlan_11d_clear_parsedtable(pmpriv);
+}
+
+/*
+  This was added to solve the radar DFS issue. The function
+  wlan_11h_radar_detect_required() checks for this and sets the scan to
+  active if media is connected. The temporary problem with our current port
+  of mlan is that after a deauth is sent after channel switch event from
+  the AP, the media connected event is still MTRUE. Hence, during scan the
+  old channel of the AP is marked as active scan which is not a correct way
+  of scanning on that channel (since radar interference is detected on
+  it). So, for now we clear this bit manually to avoid active scan on the
+  old channel. This bit will be set again at the next association completion.
+
+  fixme: Check this later.
+ */
+void wrapper_clear_media_connected_event(void)
+{
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[0];
+    pmpriv->media_connected = MFALSE;
+}
+
+mlan_status wifi_prepare_and_send_cmd(IN mlan_private *pmpriv,
+                                      IN t_u16 cmd_no,
+                                      IN t_u16 cmd_action,
+                                      IN t_u32 cmd_oid,
+                                      IN t_void *pioctl_buf,
+                                      IN t_void *pdata_buf,
+                                      mlan_bss_type bss_type,
+                                      void *priv)
+{
+    pmlan_ioctl_req pioctl_req = (mlan_ioctl_req *)pioctl_buf;
+    mlan_status rv             = MLAN_STATUS_SUCCESS;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    if (pioctl_req != NULL)
+    {
+        if (pioctl_req->bss_index == 1U)
+        {
+            bss_type = MLAN_BSS_TYPE_UAP;
+        }
+    }
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, (t_u8)bss_type);
+    cmd->result = 0x0;
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        rv = wlan_ops_uap_prepare_cmd(pmpriv, cmd_no, cmd_action, cmd_oid, pioctl_buf, pdata_buf, cmd);
+    }
+    else
+    {
+        rv = wlan_ops_sta_prepare_cmd(pmpriv, cmd_no, cmd_action, cmd_oid, pioctl_buf, pdata_buf, cmd);
+    }
+
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        wifi_d("Failed to prepare cmd.");
+        wm_wifi.cmd_resp_priv = NULL;
+        (void)wifi_put_command_lock();
+        return rv;
+    }
+
+    (void)wifi_wait_for_cmdresp(priv);
+    return MLAN_STATUS_SUCCESS;
+}
+
+bool wmsdk_is_11N_enabled(void)
+{
+    return true;
+}
+
+/* static */ int wifi_send_bss_ioctl(mlan_ds_bss *bss)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ioctl_req req;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)bss;
+    req.buf_len   = sizeof(mlan_ds_bss);
+    req.bss_index = 0;
+    req.req_id    = MLAN_IOCTL_BSS;
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wrapper_get_wpa_ie_in_assoc(uint8_t *wpa_ie)
+{
+    mlan_private *priv = (mlan_private *)mlan_adap->priv[0];
+
+    /* Reset all state variables */
+    (void)memcpy((void *)wpa_ie, (const void *)&priv->wpa_ie, sizeof(priv->wpa_ie));
+
+    return (int)priv->wpa_ie_len;
+}
+
+static int wifi_send_11n_cfg_ioctl(mlan_act_ioctl action, mlan_ds_11n_cfg *ds_11n_cfg)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ioctl_req req;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)ds_11n_cfg;
+    req.buf_len   = sizeof(mlan_ds_11n_cfg);
+    req.bss_index = 0;
+    req.req_id    = MLAN_IOCTL_11N_CFG;
+    req.action    = action;
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+static int wifi_send_uap_11n_cfg_ioctl(mlan_act_ioctl action, mlan_ds_11n_cfg *ds_11n_cfg)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ioctl_req req;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)ds_11n_cfg;
+    req.buf_len   = sizeof(mlan_ds_11n_cfg);
+    req.bss_index = 1;
+    req.req_id    = MLAN_IOCTL_11N_CFG;
+    req.action    = action;
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_txbfcap(unsigned int tx_bf_cap)
+{
+    mlan_ds_11n_cfg ds_11n_cfg;
+
+    (void)memset(&ds_11n_cfg, 0x00, sizeof(mlan_ds_11n_cfg));
+
+    ds_11n_cfg.sub_command     = MLAN_OID_11N_CFG_TX_BF_CAP;
+    ds_11n_cfg.param.tx_bf_cap = tx_bf_cap;
+
+    return wifi_send_11n_cfg_ioctl(MLAN_ACT_SET, &ds_11n_cfg);
+}
+
+int wifi_set_htcapinfo(unsigned int htcapinfo)
+{
+    mlan_ds_11n_cfg ds_11n_cfg;
+
+    (void)memset(&ds_11n_cfg, 0x00, sizeof(mlan_ds_11n_cfg));
+
+    ds_11n_cfg.sub_command           = MLAN_OID_11N_HTCAP_CFG;
+    ds_11n_cfg.param.htcap_cfg.htcap = htcapinfo;
+#if CONFIG_5GHz_SUPPORT
+    ds_11n_cfg.param.htcap_cfg.misc_cfg = BAND_SELECT_BOTH;
+#else
+    ds_11n_cfg.param.htcap_cfg.misc_cfg = BAND_SELECT_BG;
+#endif
+
+    return wifi_send_11n_cfg_ioctl(MLAN_ACT_SET, &ds_11n_cfg);
+}
+
+int wifi_set_httxcfg(unsigned short httxcfg)
+{
+    mlan_ds_11n_cfg ds_11n_cfg;
+
+    (void)memset(&ds_11n_cfg, 0x00, sizeof(mlan_ds_11n_cfg));
+
+    ds_11n_cfg.sub_command          = MLAN_OID_11N_CFG_TX;
+    ds_11n_cfg.param.tx_cfg.httxcap = httxcfg;
+#if CONFIG_5GHz_SUPPORT
+    ds_11n_cfg.param.tx_cfg.misc_cfg = BAND_SELECT_BOTH;
+#else
+    ds_11n_cfg.param.tx_cfg.misc_cfg    = BAND_SELECT_BG;
+#endif
+
+    return wifi_send_11n_cfg_ioctl(MLAN_ACT_SET, &ds_11n_cfg);
+}
+
+int wifi_uap_set_httxcfg_int(unsigned short httxcfg)
+{
+    mlan_ds_11n_cfg ds_11n_cfg;
+
+    (void)memset(&ds_11n_cfg, 0x00, sizeof(mlan_ds_11n_cfg));
+
+    ds_11n_cfg.sub_command          = MLAN_OID_11N_CFG_TX;
+    ds_11n_cfg.param.tx_cfg.httxcap = httxcfg;
+#if CONFIG_5GHz_SUPPORT
+    ds_11n_cfg.param.tx_cfg.misc_cfg = BAND_SELECT_BOTH;
+#else
+    ds_11n_cfg.param.tx_cfg.misc_cfg    = BAND_SELECT_BG;
+#endif
+
+    return wifi_send_uap_11n_cfg_ioctl(MLAN_ACT_SET, &ds_11n_cfg);
+}
+
+static int wifi_send_tx_power_cfg_ioctl(mlan_act_ioctl action, mlan_ds_power_cfg *ds_power_cfg)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ioctl_req req;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)ds_power_cfg;
+    req.buf_len   = sizeof(mlan_ds_power_cfg);
+    req.bss_index = 0;
+    req.req_id    = MLAN_IOCTL_POWER_CFG;
+    req.action    = action;
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_tx_power(t_u32 power_level)
+{
+    mlan_ds_power_cfg ds_power_cfg;
+
+    (void)memset(&ds_power_cfg, 0x00, sizeof(mlan_ds_power_cfg));
+
+    ds_power_cfg.sub_command                   = MLAN_OID_POWER_CFG;
+    ds_power_cfg.param.power_cfg.is_power_auto = MFALSE;
+    ds_power_cfg.param.power_cfg.power_level   = power_level;
+
+    return wifi_send_tx_power_cfg_ioctl(MLAN_ACT_SET, &ds_power_cfg);
+}
+
+int wifi_set_tx_power_ext(uint32_t len, uint32_t *power_data)
+{
+    mlan_ds_power_cfg ds_power_cfg;
+
+    (void)memset(&ds_power_cfg, 0x00, sizeof(mlan_ds_power_cfg));
+
+    ds_power_cfg.sub_command         = MLAN_OID_POWER_CFG_EXT;
+    ds_power_cfg.param.power_ext.len = len;
+    (void)memcpy((void *)ds_power_cfg.param.power_ext.power_data, (const void *)power_data, len);
+
+    return wifi_send_tx_power_cfg_ioctl(MLAN_ACT_SET, &ds_power_cfg);
+}
+
+int wifi_get_tx_power(t_u32 *power_level)
+{
+    int ret;
+    mlan_ds_power_cfg ds_power_cfg;
+    mlan_ioctl_req ioctl_req_pwr_cfg;
+    (void)memset(&ds_power_cfg, 0x00, sizeof(mlan_ds_power_cfg));
+    (void)memset(&ioctl_req_pwr_cfg, 0x00, sizeof(mlan_ioctl_req));
+
+    ds_power_cfg.sub_command                   = MLAN_OID_POWER_CFG;
+    ds_power_cfg.param.power_cfg.is_power_auto = MFALSE;
+    wm_wifi.cmd_resp_ioctl                     = &ioctl_req_pwr_cfg;
+    ioctl_req_pwr_cfg.pbuf                     = (t_u8 *)(&ds_power_cfg);
+    ioctl_req_pwr_cfg.buf_len                  = sizeof(mlan_ds_power_cfg);
+    ret                                        = wifi_send_tx_power_cfg_ioctl(MLAN_ACT_GET, &ds_power_cfg);
+    wm_wifi.cmd_resp_ioctl                     = NULL;
+
+    if (ret == WM_SUCCESS)
+    {
+        *power_level = ds_power_cfg.param.power_cfg.power_level;
+    }
+    return ret;
+}
+
+static int wifi_send_tx_rate_cfg_ioctl(mlan_act_ioctl action, mlan_ds_rate *ds_rate_cfg, mlan_bss_type bss_type)
+{
+    /* fixme: check if this needs to go on heap */
+    mlan_ioctl_req req;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    req.pbuf      = (t_u8 *)ds_rate_cfg;
+    req.buf_len   = sizeof(mlan_ds_rate);
+    req.bss_index = bss_type;
+    req.req_id    = MLAN_IOCTL_RATE;
+    req.action    = action;
+
+    mlan_status rv = MLAN_STATUS_SUCCESS;
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        if (!is_uap_started())
+        {
+            wifi_e("uap isn't up\n\r");
+            return -WM_FAIL;
+        }
+        rv = wlan_ops_uap_ioctl(mlan_adap, &req);
+    }
+    else if (bss_type == MLAN_BSS_TYPE_STA)
+    {
+        if (is_sta_connected())
+        {
+            rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+        }
+        else
+        {
+            wifi_e("sta connection required before setting tx rate\n\r");
+        }
+    }
+
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_txratecfg(wifi_ds_rate ds_rate, mlan_bss_type bss_type)
+{
+    mlan_ds_rate ds_rate_cfg;
+
+    if (ds_rate.sub_command != WIFI_DS_RATE_CFG)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memset(&ds_rate_cfg, 0x00, sizeof(mlan_ds_rate));
+#if CONFIG_AUTO_NULL_TX
+    ds_rate_cfg.auto_null_fixrate_enable = 0xff;
+#endif
+
+    ds_rate_cfg.sub_command = MLAN_OID_RATE_CFG;
+    if (ds_rate.param.rate_cfg.rate_format == MLAN_RATE_FORMAT_AUTO)
+    {
+        ds_rate_cfg.param.rate_cfg.is_rate_auto = MTRUE;
+    }
+    else
+    {
+#if CONFIG_AUTO_NULL_TX
+        ds_rate_cfg.auto_null_fixrate_enable = ds_rate.auto_null_fixrate_enable;
+#endif
+        ds_rate_cfg.param.rate_cfg.is_rate_auto = MFALSE;
+        ds_rate_cfg.param.rate_cfg.rate_type    = MLAN_RATE_INDEX;
+        ds_rate_cfg.param.rate_cfg.rate         = ds_rate.param.rate_cfg.rate_index;
+        ds_rate_cfg.param.rate_cfg.rate_format  = ds_rate.param.rate_cfg.rate_format;
+#ifdef SD8801
+        if (ds_rate.param.rate_cfg.rate_format == MLAN_RATE_FORMAT_HT)
+            ds_rate_cfg.param.rate_cfg.rate += MLAN_RATE_INDEX_MCS0;
+#endif
+#if CONFIG_11AC
+        if (ds_rate.param.rate_cfg.rate_format == MLAN_RATE_FORMAT_VHT
+#if CONFIG_11AX
+            || ds_rate.param.rate_cfg.rate_format == MLAN_RATE_FORMAT_HE
+#endif
+        )
+            ds_rate_cfg.param.rate_cfg.nss = ds_rate.param.rate_cfg.nss;
+#endif
+        if (ds_rate.param.rate_cfg.rate_setting != 0xffff)
+            ds_rate_cfg.param.rate_cfg.rate_setting = ds_rate.param.rate_cfg.rate_setting & ~0x0C00;
+        else
+            ds_rate_cfg.param.rate_cfg.rate_setting = ds_rate.param.rate_cfg.rate_setting;
+    }
+    return wifi_send_tx_rate_cfg_ioctl(MLAN_ACT_SET, &ds_rate_cfg, bss_type);
+}
+
+int wifi_get_txratecfg(wifi_ds_rate *ds_rate, mlan_bss_type bss_type)
+{
+    int ret;
+
+    mlan_ds_rate ds_rate_cfg;
+
+    if (ds_rate->sub_command != WIFI_DS_RATE_CFG)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memset(&ds_rate_cfg, 0x00, sizeof(mlan_ds_rate));
+
+    ds_rate_cfg.sub_command = MLAN_OID_RATE_CFG;
+
+    wm_wifi.cmd_resp_ioctl = ds_rate;
+
+    ret = wifi_send_tx_rate_cfg_ioctl(MLAN_ACT_GET, &ds_rate_cfg, bss_type);
+
+    wm_wifi.cmd_resp_ioctl = NULL;
+
+    return ret;
+}
+
+bool wrapper_wlan_11d_support_is_enabled(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    return wlan_11d_support_is_enabled(pmpriv);
+}
+
+/*
+ * fixme: This function is temporarily present till the mlan transition is complete.
+ */
+int wrapper_wifi_assoc(
+    const unsigned char *bssid, int wlan_security, bool is_wpa_tkip, unsigned int owe_trans_mode, bool is_ft)
+{
+#if !CONFIG_11R
+    (void)is_ft;
+#endif
+    mlan_private *priv = (mlan_private *)mlan_adap->priv[0];
+    t_u8 country_code[COUNTRY_CODE_LEN];
+    /* BSSDescriptor_t *bssDesc = OSA_MemoryAllocate(sizeof(BSSDescriptor_t)); */
+    /* if (!bssDesc) */
+    /* 	return -WM_FAIL; */
+    int idx = wlan_find_bssid_in_list(priv, (const unsigned char *)bssid, MLAN_BSS_MODE_NEGATIVE);
+    if (idx == -1)
+    {
+        wifi_w("Could not find BSSID in mlan scan list");
+        return -WM_FAIL;
+    }
+
+    /* Reset all state variables */
+    (void)memset(&priv->wpa_ie, 0, sizeof(priv->wpa_ie));
+    priv->wpa_ie_len                   = 0;
+    priv->sec_info.wpa2_enabled        = false;
+    priv->sec_info.wapi_enabled        = false;
+    priv->sec_info.ewpa_enabled        = false;
+    priv->sec_info.wpa_enabled         = false;
+    priv->sec_info.authentication_mode = MLAN_AUTH_MODE_AUTO;
+
+#if CONFIG_11K
+    if (priv->assoc_req_size != 0U)
+    {
+        /* Append the passed data to the end of
+         * the genIeBuffer */
+        __memcpy(priv->adapter, priv->gen_ie_buf, priv->assoc_req_buf, priv->assoc_req_size);
+
+        /* Increment the stored buffer length by
+         * the size passed */
+        priv->gen_ie_buf_len = priv->assoc_req_size;
+    }
+#endif
+
+#if CONFIG_11R
+    priv->sec_info.is_ft = is_ft;
+    if (is_ft)
+    {
+        priv->sec_info.authentication_mode = MLAN_AUTH_MODE_FT;
+    }
+#endif
+
+    BSSDescriptor_t *d = &mlan_adap->pscan_table[idx];
+    /* fixme: This code is quite hacky and is present only because
+     * security part is yet not fully integrated into mlan. This will
+     * not be necessary after the integration is complete.
+     */
+#if CONFIG_WPA2_ENTP
+    if (d->prsn_ie && (wlan_security == WLAN_SECURITY_EAP_TLS || wlan_security == WLAN_SECURITY_EAP_PEAP_MSCHAPV2))
+    {
+        priv->sec_info.wpa2_enabled = true;
+        if (d->rsn_ie_buff_len <= sizeof(priv->wpa_ie))
+        {
+            (void)memcpy(priv->wpa_ie, d->rsn_ie_buff, d->rsn_ie_buff_len);
+            priv->wpa_ie_len = d->rsn_ie_buff_len;
+        }
+        else
+        {
+            wifi_e("Failed to copy RSN IE");
+            return -WM_FAIL;
+        }
+    }
+    else
+#endif
+        if ((d->pwpa_ie != MNULL) && (d->prsn_ie != MNULL) && (wlan_security == WLAN_SECURITY_WPA_WPA2_MIXED))
+    {
+        priv->sec_info.is_wpa_tkip  = is_wpa_tkip;
+        priv->sec_info.wpa2_enabled = true;
+        if (d->rsn_ie_buff_len <= sizeof(priv->wpa_ie))
+        {
+            (void)memcpy((void *)priv->wpa_ie, (const void *)d->rsn_ie_buff, d->rsn_ie_buff_len);
+            priv->wpa_ie_len = (t_u8)d->rsn_ie_buff_len;
+        }
+        else
+        {
+            wifi_e("Failed to copy RSN IE");
+            return -WM_FAIL;
+        }
+    }
+    else if ((d->pwpa_ie != MNULL) &&
+             (wlan_security == WLAN_SECURITY_WPA || wlan_security == WLAN_SECURITY_WPA_WPA2_MIXED))
+    {
+        priv->sec_info.is_wpa_tkip = is_wpa_tkip;
+        priv->sec_info.wpa_enabled = true;
+        if (d->wpa_ie_buff_len <= sizeof(priv->wpa_ie))
+        {
+            (void)memcpy((void *)priv->wpa_ie, (const void *)d->wpa_ie_buff, d->wpa_ie_buff_len);
+            priv->wpa_ie_len = (t_u8)d->wpa_ie_buff_len;
+        }
+        else
+        {
+            wifi_e("Failed to copy WPA IE");
+            return -WM_FAIL;
+        }
+    }
+    else if ((d->prsn_ie != MNULL) &&
+#if CONFIG_11R
+             (!is_ft) &&
+#endif
+             (wlan_security == WLAN_SECURITY_WPA2 || wlan_security == WLAN_SECURITY_WPA_WPA2_MIXED ||
+#if CONFIG_DRIVER_OWE
+              owe_trans_mode == OWE_TRANS_MODE_OWE || wlan_security == WLAN_SECURITY_OWE_ONLY ||
+#endif
+              wlan_security == WLAN_SECURITY_WPA3_SAE || wlan_security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED
+#if CONFIG_11R
+              || wlan_security == WLAN_SECURITY_WPA2_FT
+#endif
+              ))
+    {
+        priv->sec_info.is_wpa_tkip  = is_wpa_tkip;
+        priv->sec_info.wpa2_enabled = true;
+        if (d->rsn_ie_buff_len <= sizeof(priv->wpa_ie))
+        {
+            (void)memcpy((void *)priv->wpa_ie, (const void *)d->rsn_ie_buff, d->rsn_ie_buff_len);
+            priv->wpa_ie_len = (t_u8)d->rsn_ie_buff_len;
+        }
+        else
+        {
+            wifi_e("Failed to copy RSN IE.");
+            return -WM_FAIL;
+        }
+#if CONFIG_11R
+        if ((!is_ft) && (wlan_security == WLAN_SECURITY_WPA2 || wlan_security == WLAN_SECURITY_WPA3_SAE ||
+                         wlan_security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED || wlan_security == WLAN_SECURITY_WPA2_FT))
+        {
+            if (d->md_ie_buff_len <= sizeof(priv->md_ie))
+            {
+                (void)memcpy((void *)priv->md_ie, (const void *)d->md_ie_buff, (size_t)d->md_ie_buff_len);
+                priv->md_ie_len = d->md_ie_buff_len;
+            }
+        }
+#endif
+        /* In case of WPA3 SAE-PSK mixed mode AP, RSN IE processing sets the SAE AKM,
+         * but if the configured security is WPA2 PSK then AKM must be of PSK
+         * hence update the AKM to WPA2 PSK and reset the PMF capabilities
+         */
+
+        /* Skip index to 1 byte (RSN information) + 1 byte (Tag length) + 2 byte (RSN version) + 4 byte (Group Cipher
+         * Suite)*/
+        int index      = 8;
+        int rsnc_index = 0;
+        /* Get pairwise count value from wpa_ie (2 Bytes LE) */
+        uint16_t pairwise_count = priv->wpa_ie[index + 1] << 8 | priv->wpa_ie[index];
+        /* Skip 2 bytes pairwise_count + all pairwise cipher suite in list (Each 4 bytes) */
+        index = index + 2 + pairwise_count * 4;
+        /* Get AKM count value from wpa_ie (2 Bytes LE) */
+        uint16_t akm_count = priv->wpa_ie[index + 1] << 8 | priv->wpa_ie[index];
+        /* Skip 2 bytes akm_count */
+        index = index + 2;
+        if (wlan_security == WLAN_SECURITY_WPA2)
+        {
+            /* Skip OUI */
+            index = index + 3;
+            for (int i = 0; i < akm_count; i++)
+            {
+                /* Check AKM type field is SAE (0x8) */
+                if (priv->wpa_ie[index] == 0x8)
+                {
+                    /* Replace AKM type to PSK (0x2) */
+                    priv->wpa_ie[index] = 0x02;
+                    /* Reset PMF capabilities*/
+                    /* RSN capabilities index can be calculated in RSN IE by adding all fields present before it that
+                     * are
+                     * Tag Number                   - 1 byte
+                     * Tag Length                   - 1 byte
+                     * RSN Version                  - 2 bytes Group
+                     * Cipher Suite                 - 4 bytes
+                     * Pairwise Cipher Suite Count  - 2 bytes
+                     * Pairwise Cipher Suite List   - pairwise_count * 4 bytes
+                     * AKM Suite Count              - 2 bytes
+                     * AKM List                     - akm_count * 4 bytes
+                     *
+                     * rsnc_index = 12 + 4 * (pairwise_count + akm_count)
+                     *
+                     * */
+                    rsnc_index                   = 12 + 4 * (pairwise_count + akm_count);
+                    priv->wpa_ie[rsnc_index]     = 0x00;
+                    priv->wpa_ie[rsnc_index + 1] = 0x00;
+                }
+                /* Skip OUI (1 byte) + AKM type (1 byte) */
+                index = index + 4;
+            }
+        }
+    }
+    else
+    { /* Do Nothing */
+    }
+
+    if ((MNULL != d) && (*d->country_info.country_code) && (d->country_info.len > COUNTRY_CODE_LEN) &&
+        (!priv->adapter->country_ie_ignore))
+    {
+        country_code[0] = d->country_info.country_code[0];
+        country_code[1] = d->country_info.country_code[1];
+        country_code[2] = ' ';
+
+        wlan_set_country_code((const char *)country_code);
+    }
+
+    /* The original assoc cmd handling function of mlan sends
+       additional two commands to the firmware; both
+       HostCmd_CMD_802_11D_DOMAIN_INFO. In the current wmsdk wifi
+       driver design we have only one command buffer. Thus, we cannot
+       new cmd while the current cmd is being sent. We will change the
+       default flow a little and send the 801.11D domain info commands
+       first and skip that step later */
+    if (wlan_11d_support_is_enabled(priv) && !mlan_adap->country_ie_ignore)
+    {
+        if (priv->support_11d != NULL)
+        {
+            if (priv->support_11d->wlan_11d_create_dnld_countryinfo_p(priv, BAND_B) != MLAN_STATUS_SUCCESS)
+            {
+                PRINTM(MERROR, "Dnld_countryinfo_11d failed\n");
+                return -WM_FAIL;
+            }
+#if CONFIG_5GHz_SUPPORT
+            if (priv->support_11d->wlan_11d_create_dnld_countryinfo_p(priv, BAND_A) != MLAN_STATUS_SUCCESS)
+            {
+                PRINTM(MERROR, "Dnld_countryinfo_11d failed\n");
+                return -WM_FAIL;
+            }
+#endif
+            if (priv->support_11d->wlan_11d_parse_dnld_countryinfo_p(priv, d) != MLAN_STATUS_SUCCESS)
+            {
+                return -WM_FAIL;
+            }
+        }
+    }
+    /* fixme: check if this needs to go on heap */
+    mlan_ds_bss bss;
+    (void)memset(&bss, 0x00, sizeof(mlan_ds_bss));
+    bss.sub_command          = MLAN_OID_BSS_START;
+    bss.param.ssid_bssid.idx = (t_u32)idx + 1UL; /* + 1 req. by mlan */
+    return wifi_send_bss_ioctl(&bss);
+}
+
+#if CONFIG_WPA_SUPP
+static mlan_status wlan_set_wpa_ie_helper(mlan_private *priv, t_u8 *ie_data_ptr, t_u16 ie_len)
+{
+    ENTER();
+
+    if (ie_len)
+    {
+        if (ie_len > sizeof(priv->wpa_ie))
+        {
+            PRINTM(MERROR, "failed to copy, WPA IE is too big\n");
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        __memcpy(priv->adapter, priv->wpa_ie, ie_data_ptr, ie_len);
+        priv->wpa_ie_len = (t_u8)ie_len;
+        PRINTM(MIOCTL, "Set Wpa_ie_len=%d IE=%#x\n", priv->wpa_ie_len, priv->wpa_ie[0]);
+        DBG_HEXDUMP(MCMD_D, "Wpa_ie", priv->wpa_ie, priv->wpa_ie_len);
+        if (priv->wpa_ie[0] == WPA_IE)
+        {
+            priv->sec_info.wpa_enabled = MTRUE;
+        }
+        else if (priv->wpa_ie[0] == RSN_IE)
+        {
+            priv->sec_info.wpa2_enabled = MTRUE;
+        }
+        else
+        {
+            priv->sec_info.wpa_enabled  = MFALSE;
+            priv->sec_info.wpa2_enabled = MFALSE;
+        }
+    }
+    else
+    {
+        __memset(priv->adapter, priv->wpa_ie, 0, sizeof(priv->wpa_ie));
+        priv->wpa_ie_len = 0;
+        PRINTM(MINFO, "Reset Wpa_ie_len=%d IE=%#x\n", priv->wpa_ie_len, priv->wpa_ie[0]);
+        priv->sec_info.wpa_enabled  = MFALSE;
+        priv->sec_info.wpa2_enabled = MFALSE;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+static mlan_status wlan_set_gen_ie_helper(mlan_private *priv, t_u8 *ie_data_ptr, t_u16 ie_len)
+{
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+    IEEEtypes_VendorHeader_t *pvendor_ie;
+    const t_u8 wpa_oui[] = {0x00, 0x50, 0xf2, 0x01};
+#if CONFIG_WPA_SUPP_WPS
+    const t_u8 wps_oui[] = {0x00, 0x50, 0xf2, 0x04};
+#endif
+#if CONFIG_WPA_SUPP_WPS
+    const t_u8 wpse_oui[] = {0x00, 0x50, 0xf2, 0x10};
+#endif
+#ifdef ENABLE_HOTSPOT
+    const t_u8 osen_oui[] = {0x50, 0x6f, 0x9a, 0x12};
+#endif
+    t_u8 i = 0, temp[12] = {0};
+
+    ENTER();
+
+    /* If the passed length is zero, reset the buffer */
+    if (!ie_len)
+    {
+        priv->gen_ie_buf_len = 0;
+#if CONFIG_WPA_SUPP_WPS
+        priv->wps.session_enable = MFALSE;
+#endif
+        wlan_set_wpa_ie_helper(priv, MNULL, 0);
+#ifdef ENABLE_HOTSPOT
+        wlan_set_osen_ie(priv, MNULL, 0);
+#endif
+    }
+    else if (!ie_data_ptr)
+    {
+        /* MNULL check */
+        ret = MLAN_STATUS_FAILURE;
+    }
+    else
+    {
+        pvendor_ie = (IEEEtypes_VendorHeader_t *)ie_data_ptr;
+        if (pvendor_ie->element_id == EXT_CAPABILITY)
+        {
+            __memcpy(priv->adapter, temp, &priv->ext_cap, sizeof(priv->ext_cap));
+            for (i = 0; i < MIN(sizeof(priv->ext_cap), pvendor_ie->len); i++)
+                temp[i] |= ie_data_ptr[2 + i];
+            __memcpy(priv->adapter, &priv->ext_cap, temp, sizeof(priv->ext_cap));
+        }
+        else
+            /* Test to see if it is a WPA IE, if not, then it is a
+               gen IE*/
+            if (((pvendor_ie->element_id == WPA_IE) &&
+                 (!__memcmp(priv->adapter, pvendor_ie->oui, wpa_oui, sizeof(pvendor_ie->oui))) &&
+                 (pvendor_ie->oui_type == wpa_oui[3U])) ||
+                (pvendor_ie->element_id == RSN_IE))
+            {
+                /* IE is a WPA/WPA2 IE so call set_wpa function */
+                ret = wlan_set_wpa_ie_helper(priv, ie_data_ptr, ie_len);
+#if CONFIG_WPA_SUPP_WPS
+                priv->wps.session_enable = MFALSE;
+#endif /* CONFIG_WPA_SUPP_WPS */
+            }
+            else
+#ifdef ENABLE_HOTSPOT
+                if ((pvendor_ie->element_id == VENDOR_SPECIFIC_221) &&
+                    (!__memcmp(priv->adapter, pvendor_ie->oui, osen_oui, sizeof(pvendor_ie->oui))) &&
+                    (pvendor_ie->oui_type == osen_oui[3U]))
+            {
+                /* IE is a OSEN IE so call set_osen function */
+                ret = wlan_set_osen_ie(priv, ie_data_ptr, ie_len);
+            }
+            else
+#endif
+#if CONFIG_WPA_SUPP_WPS
+                if (pvendor_ie->element_id == VENDOR_SPECIFIC_221 &&
+                    (!__memcmp(priv->adapter, pvendor_ie->oui, wps_oui, sizeof(pvendor_ie->oui))) &&
+                    (pvendor_ie->oui_type == wps_oui[3U]))
+            {
+                /*
+                 * Discard first two byte (Element ID and Length)
+                 * because they are not needed in the case of setting
+                 * WPS_IE
+                 */
+                if (pvendor_ie->len > 4)
+                {
+                    __memcpy(priv->adapter, (t_u8 *)&priv->wps.wps_ie, ie_data_ptr, ie_len);
+
+                    HEXDUMP("wps_ie", (t_u8 *)&priv->wps.wps_ie, priv->wps.wps_ie.vend_hdr.len + 2);
+                }
+                else
+                {
+                    /* Only wps oui exist, reset driver wps buffer
+                     */
+                    __memset(priv->adapter, (t_u8 *)&priv->wps.wps_ie, 0x00, sizeof(priv->wps.wps_ie));
+                    PRINTM(MINFO, "wps_ie cleared\n");
+                }
+            }
+            else
+#endif
+            {
+                /*
+                 * Verify that the passed length is not larger than
+                 * the available space remaining in the buffer
+                 */
+                if (ie_len < (sizeof(priv->gen_ie_buf) - priv->gen_ie_buf_len))
+                {
+#if CONFIG_WPA_SUPP_WPS
+                    /* Test to see if it is a WPS IE, if so, enable
+                     * wps session flag */
+                    pvendor_ie = (IEEEtypes_VendorHeader_t *)ie_data_ptr;
+                    if ((pvendor_ie->element_id == WPS_IE) &&
+                        (!__memcmp(priv->adapter, pvendor_ie->oui, wps_oui, sizeof(pvendor_ie->oui))) &&
+                        (pvendor_ie->oui_type == wps_oui[3U]))
+                    {
+                        priv->wps.session_enable = MTRUE;
+                        PRINTM(MINFO, "WPS Session Enabled.\n");
+                    }
+#endif
+
+#if CONFIG_WPA_SUPP_WPS
+                    /* Test to see if it is a WPSE IE, if so,
+                     * enable wps session flag */
+                    pvendor_ie = (IEEEtypes_VendorHeader_t *)ie_data_ptr;
+                    if ((pvendor_ie->element_id == WPS_IE) &&
+                        (!__memcmp(priv->adapter, pvendor_ie->oui, wpse_oui, sizeof(pvendor_ie->oui))) &&
+                        (pvendor_ie->oui_type == wpse_oui[3U]))
+                    {
+                        priv->wps.session_enable = MTRUE;
+                        PRINTM(MINFO, "WPSE Session Enabled.\n");
+                    }
+#endif
+                    /* Append the passed data to the end of
+                     * the genIeBuffer */
+                    __memcpy(priv->adapter, priv->gen_ie_buf + priv->gen_ie_buf_len, ie_data_ptr, ie_len);
+
+                    /* Increment the stored buffer length by
+                     * the size passed */
+                    priv->gen_ie_buf_len += ie_len;
+                }
+                else
+                {
+                    /* Passed data does not fit in the
+                     * remaining buffer space */
+                    ret = MLAN_STATUS_FAILURE;
+                }
+            }
+    }
+
+    /* Return MLAN_STATUS_SUCCESS, or MLAN_STATUS_FAILURE for error case */
+    LEAVE();
+    return ret;
+}
+
+static int wifi_set_ies_cfg(mlan_private *priv, t_u8 *ie, int ie_len)
+{
+    int bytes_left     = ie_len;
+    t_u8 *pcurrent_ptr = ie;
+    int total_ie_len;
+    t_u8 element_len;
+    int ret = WM_SUCCESS;
+    IEEEtypes_ElementId_e element_id;
+#if CONFIG_WPA_SUPP_WPS
+    IEEEtypes_VendorSpecific_t *pvendor_ie;
+    t_u8 wps_oui[] = {0x00, 0x50, 0xf2, 0x04};
+#endif
+#ifdef HOST_CCX
+    t_u8 ccx_oui[] = {0x00, 0x40, 0x96, 0x03};
+#endif /* HOST_CCX */
+#ifdef ENABLE_HOTSPOT
+    t_u8 hs20_oui[] = {0x50, 0x6f, 0x9a, 0x10};
+#endif /* ENABLE_HOTSPOT */
+
+#ifdef EASYMESH
+    t_u8 multiap_oui[] = {0x50, 0x6f, 0x9a, 0x1b};
+    t_u8 multiap_flag  = 0;
+#endif
+
+    while (bytes_left >= 2)
+    {
+        element_id   = (IEEEtypes_ElementId_e)(*((t_u8 *)pcurrent_ptr));
+        element_len  = *((t_u8 *)pcurrent_ptr + 1);
+        total_ie_len = element_len + sizeof(IEEEtypes_Header_t);
+        if (bytes_left < total_ie_len)
+        {
+            PRINTM(MERROR, "InterpretIE: Error in processing IE, bytes left < IE length\n");
+            bytes_left = 0;
+            continue;
+        }
+        switch (element_id)
+        {
+            case RSN_IE:
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    PRINTM(MERROR, "Fail to set RSN IE\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                PRINTM(MIOCTL, "Set RSN IE\n");
+                break;
+            case VENDOR_SPECIFIC_221:
+#if CONFIG_WPA_SUPP_WPS
+                pvendor_ie = (IEEEtypes_VendorSpecific_t *)pcurrent_ptr;
+                if (!memcmp(pvendor_ie->vend_hdr.oui, wps_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                    (pvendor_ie->vend_hdr.oui_type == wps_oui[3]))
+                {
+                    wifi_d("Enable WPS session\r\n");
+                    priv->wps.session_enable = MTRUE;
+                }
+#endif
+
+#ifdef EASYMESH
+                if (!memcmp(pvendor_ie->vend_hdr.oui, multiap_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                    (pvendor_ie->vend_hdr.oui_type == multiap_oui[3]))
+                {
+                    multiap_flag = pvendor_ie->data[0];
+                    if (MLAN_STATUS_SUCCESS != woal_multi_ap_cfg(priv, wait_option, multiap_flag))
+                    {
+                        PRINTM(MERROR, "%s: failed to configure multi ap\n", __func__);
+                        ret = -WM_FAIL;
+                        goto done;
+                    }
+                }
+#endif
+
+#ifdef HOST_CCX
+                if (!memcmp(pvendor_ie->vend_hdr.oui, ccx_oui, sizeof(ccx_oui)))
+                {
+                    PRINTM(MIOCTL, "CCX is enabled for this bss\n");
+                    priv->is_ccx = 1;
+                }
+#endif
+#ifdef ENABLE_HOTSPOT
+                if (!memcmp(pvendor_ie->vend_hdr.oui, hs20_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                    (pvendor_ie->vend_hdr.oui_type == hs20_oui[3]))
+                {
+                    PRINTM(MIOCTL, "Hotspot2.0 is enabled for this bss\n");
+                    if (MLAN_STATUS_SUCCESS !=
+                        woal_set_hotspotcfg(priv, wait_option, (HOTSPOT_BY_SUPPLICANT | HOTSPOT_ENABLED)))
+                    {
+                        PRINTM(MERROR, "Fail to enable hotspot 2.0\n");
+                        ret = -WM_FAIL;
+                        goto done;
+                    }
+                }
+#endif
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    PRINTM(MERROR, "Fail to Set VENDOR SPECIFIC IE\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                wifi_d("Set VENDOR SPECIFIC IE, OUI: %02x:%02x:%02x:%02x\r\n", pvendor_ie->vend_hdr.oui[0],
+                       pvendor_ie->vend_hdr.oui[1], pvendor_ie->vend_hdr.oui[2], pvendor_ie->vend_hdr.oui_type);
+                break;
+#if CONFIG_11R
+            case MOBILITY_DOMAIN:
+                (void)memcpy((void *)priv->md_ie, (const void *)pcurrent_ptr, (size_t)total_ie_len);
+                priv->md_ie_len = (size_t)total_ie_len;
+                wifi_d("Set MD IE\r\n");
+                break;
+            case FAST_BSS_TRANSITION:
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    wifi_d(
+                        "Fail to set"
+                        "FAST_BSS_TRANSITION IE\r\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                wifi_d("Set FAST_BSS_TRANSITION IE\r\n");
+                priv->sec_info.is_ft = true;
+                break;
+            case RIC:
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    wifi_d(
+                        "Fail to set"
+                        "RESOURCE INFORMATION CONTAINER IE\r\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                wifi_d("Set RESOURCE INFORMATION CONTAINER IE\r\n");
+                break;
+#endif
+            case EXT_CAPABILITY:
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    PRINTM(MERROR, "Fail to set Extended Capabilites IE\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                wifi_d("Set Extended Capabilities IE\n");
+                break;
+            case EXTENSION:
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    PRINTM(MERROR, "Fail to set Extension IE\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                PRINTM(MIOCTL, "Set Extension IE\n");
+                break;
+            case FRAGMENT:
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    PRINTM(MERROR, "Fail to set Fragmented IE\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                PRINTM(MIOCTL, "Set Fragmented IE\n");
+                break;
+            default:
+                if (MLAN_STATUS_SUCCESS != wlan_set_gen_ie_helper(priv, pcurrent_ptr, total_ie_len))
+                {
+                    PRINTM(MERROR, "Fail to set GEN IE\n");
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+                PRINTM(MIOCTL, "Set GEN IE\n");
+                break;
+        }
+        pcurrent_ptr += element_len + 2;
+        /* Need to account for IE ID and IE Len */
+        bytes_left -= (element_len + 2);
+    }
+done:
+    return ret;
+}
+
+int wifi_set_scan_ies(void *ie, size_t ie_len)
+{
+    mlan_private *priv = (mlan_private *)mlan_adap->priv[0];
+    int ret            = -WM_FAIL;
+#if (CONFIG_WPA_SUPP) && (CONFIG_WPA_SUPP_WPS)
+    priv->wps.session_enable = MFALSE;
+#endif
+
+    /* Reset the generic IE buffer */
+    priv->gen_ie_buf_len = 0;
+
+    ret = wifi_set_ies_cfg(priv, (t_u8 *)ie, ie_len);
+
+    if (ret != MLAN_STATUS_SUCCESS)
+    {
+        wifi_w("Could not set the IEs");
+        return (int)-WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+static int wifi_assocreq_wps_ie_cfg(mlan_private *priv)
+{
+    int ret       = WM_SUCCESS;
+    int wpsie_len = 0;
+    u8 *wps_buf   = NULL;
+    wpsie_len     = sizeof(IEEEtypes_Header_t) + priv->wps.wps_ie.vend_hdr.len;
+    wps_buf       = (t_u8 *)OSA_MemoryAllocate(wpsie_len);
+    (void)memset(wps_buf, 0, wpsie_len);
+    (void)__memcpy(priv->adapter, wps_buf, (t_u8 *)&priv->wps.wps_ie, wpsie_len);
+    priv->wps.wps_mgmt_bitmap_index =
+        wifi_set_mgmt_ie2(priv->bss_type, MGMT_MASK_ASSOC_REQ | MGMT_MASK_REASSOC_REQ, (void *)wps_buf, wpsie_len);
+    if (-WM_FAIL != priv->wps.wps_mgmt_bitmap_index)
+        ret = WM_SUCCESS;
+    else
+        ret = -WM_FAIL;
+    OSA_MemoryFree(wps_buf);
+    return ret;
+}
+#endif
+#endif
+
+int wifi_nxp_send_assoc(nxp_wifi_assoc_info_t *assoc_info)
+{
+    int ret                    = -WM_FAIL;
+    const unsigned char *bssid = (const unsigned char *)&assoc_info->bssid;
+
+    mlan_private *priv = (mlan_private *)mlan_adap->priv[0];
+    t_u8 country_code[COUNTRY_CODE_LEN];
+
+    if (priv->auth_alg == WLAN_AUTH_SAE)
+    {
+        priv->auth_flag = HOST_MLME_AUTH_DONE;
+    }
+
+    wifi_remain_on_channel(false, 0, 0);
+
+    if (priv->auth_flag && !(priv->auth_flag & HOST_MLME_AUTH_DONE))
+    {
+        return -WM_FAIL;
+    }
+
+    int idx = wlan_find_bssid_in_list(priv, (const unsigned char *)bssid, MLAN_BSS_MODE_NEGATIVE);
+    if (idx == -1)
+    {
+        wifi_w("Could not find BSSID in mlan scan list");
+        return ret;
+    }
+
+    BSSDescriptor_t *d = &mlan_adap->pscan_table[idx];
+
+    priv->curr_bss_params.host_mlme = 1;
+
+    __memcpy(priv->adapter, &priv->curr_bss_params.prev_bssid, assoc_info->prev_bssid, MLAN_MAC_ADDR_LENGTH);
+
+    /* Reset all state variables */
+    (void)memset(&priv->wpa_ie, 0, sizeof(priv->wpa_ie));
+    priv->wpa_ie_len                   = 0;
+    priv->sec_info.wpa2_enabled        = MFALSE;
+    priv->sec_info.wapi_enabled        = MFALSE;
+    priv->sec_info.ewpa_enabled        = MFALSE;
+    priv->sec_info.wpa_enabled         = MFALSE;
+    priv->sec_info.authentication_mode = MLAN_AUTH_MODE_AUTO;
+
+    priv->sec_info.is_wpa_tkip = MFALSE;
+#if CONFIG_11R
+    priv->sec_info.is_ft = MFALSE;
+    priv->md_ie_len      = 0;
+#endif
+
+    /* Reset the generic IE buffer */
+    priv->gen_ie_buf_len = 0;
+
+#if CONFIG_WPA_SUPP_WPS
+    priv->wps.session_enable = MFALSE;
+#endif
+
+    ret = wifi_set_ies_cfg(priv, (t_u8 *)assoc_info->wpa_ie.ie, assoc_info->wpa_ie.ie_len);
+
+    if (ret != WM_SUCCESS)
+    {
+        wifi_w("Could not set the IEs");
+        return -WM_FAIL;
+    }
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    if (priv->wps.wps_mgmt_bitmap_index != -1)
+    {
+        ret = wifi_clear_mgmt_ie2(priv->bss_type, priv->wps.wps_mgmt_bitmap_index);
+        if (ret != WM_SUCCESS)
+        {
+            wifi_e("Clear Assoc req IE failed");
+            return -WM_FAIL;
+        }
+        priv->wps.wps_mgmt_bitmap_index = -1;
+    }
+    else if (priv->wps.session_enable == MTRUE)
+    {
+        ret = wifi_assocreq_wps_ie_cfg(priv);
+        if (ret != WM_SUCCESS)
+        {
+            wifi_w("add WPS_IE to assocreq fail");
+            return -WM_FAIL;
+        }
+    }
+#endif
+#endif
+
+    (void)wifi_set_rx_mgmt_indication(MLAN_BSS_TYPE_STA, WIFI_MGMT_DEAUTH | WIFI_MGMT_DIASSOC | WIFI_MGMT_ACTION);
+
+#if CONFIG_11R
+    if (priv->sec_info.is_ft)
+    {
+        priv->sec_info.authentication_mode = MLAN_AUTH_MODE_FT;
+#if CONFIG_GTK_REKEY_OFFLOAD
+        (void)__memset(pmadapter, &priv->gtk_rekey, 0, sizeof(priv->gtk_rekey));
+#endif
+    }
+#endif
+
+    if ((MNULL != d) && (*d->country_info.country_code) && (d->country_info.len > COUNTRY_CODE_LEN) &&
+        (!priv->adapter->country_ie_ignore))
+    {
+        country_code[0] = d->country_info.country_code[0];
+        country_code[1] = d->country_info.country_code[1];
+        country_code[2] = ' ';
+
+        wlan_set_country_code((const char *)country_code);
+    }
+
+    /* The original assoc cmd handling function of mlan sends
+       additional two commands to the firmware; both
+       HostCmd_CMD_802_11D_DOMAIN_INFO. In the current wmsdk wifi
+       driver design we have only one command buffer. Thus, we cannot
+       new cmd while the current cmd is being sent. We will change the
+       default flow a little and send the 801.11D domain info commands
+       first and skip that step later */
+    if (wlan_11d_support_is_enabled(priv) && !mlan_adap->country_ie_ignore)
+    {
+        if (priv->support_11d != NULL)
+        {
+            if (priv->support_11d->wlan_11d_create_dnld_countryinfo_p(priv, BAND_B) != MLAN_STATUS_SUCCESS)
+            {
+                PRINTM(MERROR, "Dnld_countryinfo_11d failed\n");
+                return -WM_FAIL;
+            }
+#if CONFIG_5GHz_SUPPORT
+            if (priv->support_11d->wlan_11d_create_dnld_countryinfo_p(priv, BAND_A) != MLAN_STATUS_SUCCESS)
+            {
+                PRINTM(MERROR, "Dnld_countryinfo_11d failed\n");
+                return -WM_FAIL;
+            }
+#endif
+            if (priv->support_11d->wlan_11d_parse_dnld_countryinfo_p(priv, d) != MLAN_STATUS_SUCCESS)
+            {
+                return -WM_FAIL;
+            }
+        }
+    }
+    /* fixme: check if this needs to go on heap */
+    mlan_ds_bss bss;
+    (void)memset(&bss, 0x00, sizeof(mlan_ds_bss));
+    bss.sub_command          = MLAN_OID_BSS_START;
+    bss.param.ssid_bssid.idx = (t_u32)idx + 1UL; /* + 1 req. by mlan */
+    return wifi_send_bss_ioctl(&bss);
+}
+#endif
+
+static void compute_rssi_values(HostCmd_DS_802_11_RSSI_INFO_RSP *prssi_info_rsp, wifi_rssi_info_t *rssi_info)
+{
+    g_rssi        = prssi_info_rsp->bcn_rssi_last;
+    g_bcn_nf_last = prssi_info_rsp->bcn_nf_last;
+
+    rssi_info->bcn_rssi_last  = prssi_info_rsp->bcn_rssi_last;
+    rssi_info->bcn_rssi_avg   = prssi_info_rsp->bcn_rssi_avg;
+    rssi_info->data_rssi_last = prssi_info_rsp->data_rssi_last;
+    rssi_info->data_rssi_avg  = prssi_info_rsp->data_rssi_avg;
+
+    rssi_info->bcn_snr_last  = CAL_SNR(prssi_info_rsp->bcn_rssi_last, prssi_info_rsp->bcn_nf_last);
+    rssi_info->bcn_snr_avg   = CAL_SNR(prssi_info_rsp->bcn_rssi_avg, prssi_info_rsp->bcn_nf_avg);
+    rssi_info->data_snr_last = CAL_SNR(prssi_info_rsp->data_rssi_last, prssi_info_rsp->data_nf_last);
+    rssi_info->data_snr_avg  = CAL_SNR(prssi_info_rsp->data_rssi_avg, prssi_info_rsp->data_nf_avg);
+
+    rssi_info->bcn_nf_last  = prssi_info_rsp->bcn_nf_last;
+    rssi_info->bcn_nf_avg   = prssi_info_rsp->bcn_nf_avg;
+    rssi_info->data_nf_last = prssi_info_rsp->data_nf_last;
+    rssi_info->data_nf_avg  = prssi_info_rsp->data_nf_avg;
+}
+/* Function of copy hostcmd response to buffers set in wm_wifi structure */
+static void wifi_set_hostcmd_resp(const HostCmd_DS_COMMAND *resp)
+{
+    if (wm_wifi.cmd_resp_priv == MNULL)
+    {
+        return;
+    }
+    /* reset is_hostcmd to 0, so that other commands can be processed */
+    wm_wifi.hostcmd_cfg.is_hostcmd = false;
+
+    hostcmd_cfg_t *hcmd_cfg = (hostcmd_cfg_t *)wm_wifi.cmd_resp_priv;
+
+    *hcmd_cfg->reqd_resp_len = resp->size;
+    /* Copy if response buffer is suffcient to hold response data */
+    if (hcmd_cfg->resp_buf_len >= resp->size)
+    {
+        (void)memcpy((void *)hcmd_cfg->resp_buf, (const void *)resp, resp->size);
+    }
+    /* Initialize user pointer to NULL*/
+    wm_wifi.cmd_resp_priv = NULL;
+}
+
+static void load_bss_list(const HostCmd_DS_STA_LIST *sta_list)
+{
+    if (wm_wifi.cmd_resp_priv == MNULL)
+    {
+        return;
+    }
+
+    /* Initialize user pointer */
+    *(wifi_sta_list_t **)wm_wifi.cmd_resp_priv = NULL;
+
+    t_u16 c = sta_list->sta_count;
+    if (c > MAX_NUM_CLIENTS)
+    {
+        wifi_w("Too many clients: %d", c);
+        return;
+    }
+
+#if !CONFIG_MEM_POOLS
+    wifi_sta_list_t *sl = OSA_MemoryAllocate(sizeof(wifi_sta_list_t) + c * sizeof(wifi_sta_info_t));
+#else
+    wifi_sta_list_t *sl                 = OSA_MemoryPoolAllocate(buf_256_MemoryPool);
+#endif
+
+    if (sl == MNULL)
+    {
+        return;
+    }
+
+    sl->count            = c;
+    wifi_sta_info_t *sta = (wifi_sta_info_t *)(void *)(((t_u8 *)&sl->count) + sizeof(int));
+
+    int i;
+    MrvlIEtypes_sta_info_t *si = (MrvlIEtypes_sta_info_t *)(((t_u8 *)&sta_list->sta_count) + sizeof(t_u16));
+    for (i = 0; i < c && i < MAX_NUM_CLIENTS; i++)
+    {
+        if ((si->rssi & 0x80) != 0)
+        {
+            // coverity[overrun-local:SUPPRESS]
+            sta[i].rssi = -(256 - si->rssi);
+        }
+        else
+        {
+            sta[i].rssi = si->rssi;
+        }
+
+        (void)memcpy(sta[i].mac, si->mac_address, MLAN_MAC_ADDR_LENGTH);
+        sta[i].power_mgmt_status = si->power_mfg_status;
+        si = (MrvlIEtypes_sta_info_t *)((t_u8 *)si + (si->header.len + sizeof(MrvlIEtypesHeader_t)));
+
+        wifi_d("RSSI: 0x%x %d dbm", sta[i].rssi, sta[i].rssi);
+    }
+
+    /* Note: Caller needs to free this */
+    *(wifi_sta_list_t **)wm_wifi.cmd_resp_priv = sl;
+
+    wm_wifi.cmd_resp_status = WM_SUCCESS;
+    wm_wifi.cmd_resp_priv   = NULL;
+}
+
+static void load_ver_ext(HostCmd_DS_COMMAND *resp)
+{
+    if (wm_wifi.cmd_resp_priv == MNULL)
+    {
+        return;
+    }
+
+    HostCmd_DS_VERSION_EXT *ver_ext     = &resp->params.verext;
+    wifi_fw_version_ext_t *user_ver_ext = (wifi_fw_version_ext_t *)wm_wifi.cmd_resp_priv;
+
+    (void)memcpy((void *)user_ver_ext->version_str, (const void *)ver_ext->version_str, resp->size - 10U);
+
+    wm_wifi.cmd_resp_status = WM_SUCCESS;
+    wm_wifi.cmd_resp_priv   = NULL;
+}
+
+int wifi_process_cmd_response(HostCmd_DS_COMMAND *resp)
+{
+    mlan_private *pmpriv          = (mlan_private *)mlan_adap->priv[0];
+    mlan_status rv                = MLAN_STATUS_SUCCESS;
+    enum wifi_event_reason result = WIFI_EVENT_REASON_FAILURE;
+    t_u8 *sta_addr;
+
+    t_u16 command = (resp->command & HostCmd_CMD_ID_MASK);
+#ifdef RW610
+    last_resp_rcvd = command;
+#endif
+
+#if !CONFIG_WIFI_PS_DEBUG
+    if ((resp->command & 0x0fffU) != HostCmd_CMD_802_11_PS_MODE_ENH)
+    {
+        wcmdr_d("CMD_RESP - : 0x%x, result %d, len %d, seqno 0x%x", resp->command, resp->result, resp->size,
+                resp->seq_num);
+    }
+#else
+    wcmdr_d("CMD_RESP - : 0x%x, result %d, len %d, seqno 0x%x", resp->command, resp->result, resp->size, resp->seq_num);
+#endif
+
+#if CONFIG_FW_VDLL
+    mlan_adap->vdll_in_progress = MFALSE;
+#endif
+
+    mlan_bss_type bss_type = (mlan_bss_type)HostCmd_GET_BSS_TYPE(resp->seq_num);
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        pmpriv = (mlan_private *)mlan_adap->priv[1];
+    }
+    else
+    {
+        pmpriv = (mlan_private *)mlan_adap->priv[0];
+    }
+
+    if (mlan_adap->ps_state == PS_STATE_SLEEP)
+    {
+        OSA_RWLockWriteUnlock(&sleep_rwlock);
+        mlan_adap->ps_state = PS_STATE_AWAKE;
+    }
+
+    /* Check if the command is a user issued host command */
+    if (wm_wifi.hostcmd_cfg.is_hostcmd == true)
+    {
+        wifi_set_hostcmd_resp(resp);
+        rv = MLAN_STATUS_SUCCESS;
+    }
+    else
+    {
+        switch (command)
+        {
+            case HOST_CMD_SMART_MODE_CFG:
+            {
+#if CONFIG_WIFI_EXTRA_DEBUG
+                HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)&resp->params.sys_config;
+
+                if (sys_config_cmd->action == HostCmd_ACT_GEN_GET)
+                    dump_hex(resp, resp->size);
+#endif
+            }
+            break;
+            case HOST_CMD_APCMD_BSS_STOP:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    pmpriv->uap_bss_started = MFALSE;
+                    bss_type                = (mlan_bss_type)HostCmd_GET_BSS_TYPE(resp->seq_num);
+                    if ((bss_type == MLAN_BSS_TYPE_UAP)
+                    )
+                    {
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                        wlan_clean_txrx(pmpriv);
+                        (void)wifi_event_completion(WIFI_EVENT_UAP_STOPPED, WIFI_EVENT_REASON_SUCCESS, NULL);
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCMD_APCMD_ACS_SCAN:
+#ifdef SD8801
+            case HostCmd_MMH_ACS_CFG:
+#endif
+            {
+#ifdef SD8801
+                HostCmd_DS_ACS_CONFIG *acs_scan = (HostCmd_DS_ACS_CONFIG *)&resp->params.acs_scan;
+#else
+                HostCMD_DS_APCMD_ACS_SCAN *acs_scan = (HostCMD_DS_APCMD_ACS_SCAN *)&resp->params.acs_scan;
+#endif
+                wm_wifi.acs_chan = 0;
+
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.acs_chan = acs_scan->chan;
+
+                    bss_type = (mlan_bss_type)HostCmd_GET_BSS_TYPE(resp->seq_num);
+                    if ((bss_type == MLAN_BSS_TYPE_UAP)
+                    )
+                    {
+#if CONFIG_WPA_SUPP
+                        nxp_wifi_acs_params acs_params;
+#ifndef SD8801
+                        t_u8 chan_offset;
+#endif
+
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+#ifndef SD8801
+                        wifi_d("ACS scan done: bandcfg=%x, channel=%d\r\n", acs_scan->bandcfg, acs_scan->chan);
+#else
+                        wifi_d("ACS scan done: bandcfg=0, channel=%d\r\n", acs_scan->chan);
+#endif
+
+                        memset(&acs_params, 0, sizeof(nxp_wifi_acs_params));
+
+#if defined(SD8801) || defined(RW610)
+#ifdef SD8801
+                        acs_params.pri_freq = channel_to_frequency(acs_scan->chan, 0);
+                        acs_params.hw_mode  = 1;
+#else
+                        acs_params.pri_freq = channel_to_frequency(acs_scan->chan, acs_scan->bandcfg.chanBand);
+                        acs_params.hw_mode  = acs_scan->bandcfg.chanBand == 0 ? 1 : 2;
+#endif
+                        acs_params.ch_width = 20;
+#else
+                        acs_params.pri_freq = channel_to_frequency(acs_scan->chan, acs_scan->bandcfg.chanBand);
+
+                        chan_offset = wifi_get_sec_channel_offset(acs_scan->chan);
+                        if (chan_offset == SEC_CHAN_ABOVE)
+                        {
+                            acs_params.sec_freq = acs_params.pri_freq + 20;
+                        }
+                        else if (chan_offset == SEC_CHAN_BELOW)
+                        {
+                            acs_params.sec_freq = acs_params.pri_freq - 20;
+                        }
+                        else
+                        {
+                            acs_params.sec_freq = acs_params.pri_freq;
+                        }
+
+#if CONFIG_11AC
+                        if (wm_wifi.bandwidth == BANDWIDTH_80MHZ)
+                        {
+#if CONFIG_5GHz_SUPPORT
+                            if (acs_scan->chan > MAX_CHANNELS_BG)
+                            {
+                                acs_params.ch_width = 80;
+                            }
+#endif
+                        }
+                        else
+#endif
+                            if (wm_wifi.bandwidth == BANDWIDTH_40MHZ)
+                        {
+                            acs_params.ch_width = 40;
+                        }
+                        else
+                        {
+                            acs_params.sec_freq = 0;
+                            acs_params.ch_width = 20;
+                            wifi_uap_set_bandwidth(BANDWIDTH_20MHZ);
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+                            wifi_event_completion(WIFI_EVENT_ACS_COMPLETE, WIFI_EVENT_REASON_SUCCESS, NULL);
+#endif
+#endif
+                        }
+                        if (acs_scan->chan == 165)
+                        {
+                            acs_params.sec_freq = 0;
+                            acs_params.ch_width = 20;
+                            wifi_uap_set_bandwidth(BANDWIDTH_20MHZ);
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+                            wifi_event_completion(WIFI_EVENT_ACS_COMPLETE, WIFI_EVENT_REASON_SUCCESS, NULL);
+#endif
+#endif
+                        }
+                        acs_params.hw_mode = acs_scan->bandcfg.chanBand == 0 ? 1 : 2;
+#endif
+                        if (wm_wifi.supp_if_callbk_fns->acs_channel_sel_callbk_fn)
+                        {
+                            wm_wifi.supp_if_callbk_fns->acs_channel_sel_callbk_fn(wm_wifi.hapd_if_priv, &acs_params);
+                        }
+#endif
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HOST_CMD_APCMD_BSS_START:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    bss_type = (mlan_bss_type)HostCmd_GET_BSS_TYPE(resp->seq_num);
+                    if ((bss_type == MLAN_BSS_TYPE_UAP)
+                    )
+                    {
+#if CONFIG_WMM_UAPSD
+                        /* disable uapsd for uAP */
+                        mlan_adap->pps_uapsd_mode = MFALSE;
+                        mlan_adap->tx_lock_flag   = MFALSE;
+#endif
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                        (void)wifi_event_completion(WIFI_EVENT_UAP_STARTED, WIFI_EVENT_REASON_SUCCESS, NULL);
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HOST_CMD_APCMD_STA_LIST:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    const HostCmd_DS_STA_LIST *sta_list = &resp->params.sta_list;
+                    load_bss_list(sta_list);
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_802_11_TX_RATE_QUERY:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    int bss_type = HostCmd_GET_BSS_TYPE(resp->seq_num);
+                    if (bss_type == MLAN_BSS_TYPE_UAP)
+                        pmpriv = (mlan_private *)mlan_adap->priv[1];
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        wifi_ds_rate *ds_rate = (wifi_ds_rate *)wm_wifi.cmd_resp_priv;
+                        rv                    = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, ds_rate);
+                        if (rv != MLAN_STATUS_SUCCESS)
+                        {
+                            wm_wifi.cmd_resp_status = -WM_FAIL;
+                        }
+                        else
+                        {
+                            wm_wifi.cmd_resp_status = WM_SUCCESS;
+                        }
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_TBTT_OFFSET:
+            {
+                HostCmd_DS_TBTT_OFFSET *tbtt_offset;
+                tbtt_offset = (HostCmd_DS_TBTT_OFFSET *)&resp->params.tbtt_offset;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (tbtt_offset->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            wifi_tbtt_offset_t *tbtt_offset_t = (wifi_tbtt_offset_t *)wm_wifi.cmd_resp_priv;
+
+                            tbtt_offset_t->min_tbtt_offset = tbtt_offset->min_tbtt_offset;
+                            tbtt_offset_t->max_tbtt_offset = tbtt_offset->max_tbtt_offset;
+                            tbtt_offset_t->avg_tbtt_offset = tbtt_offset->avg_tbtt_offset;
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_MEF_CFG:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_802_11_RF_TX_POWER:
+            {
+                const HostCmd_DS_802_11_RF_TX_POWER *txp = &resp->params.txp;
+                if (txp->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        wifi_tx_power_t *tx_p = (wifi_tx_power_t *)wm_wifi.cmd_resp_priv;
+                        tx_p->current_level   = txp->current_level;
+                        tx_p->max_power       = txp->max_power;
+                        tx_p->min_power       = txp->min_power;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_802_11D_DOMAIN_INFO:
+            {
+                HostCmd_DS_802_11D_DOMAIN_INFO *domain_info =
+                    (HostCmd_DS_802_11D_DOMAIN_INFO *)&resp->params.domain_info;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else if (domain_info->action == HostCmd_ACT_SPC_SET)
+                {
+                    /*FW not supported yet, always set command response status success for action code
+                     * HostCmd_ACT_SPC_SET*/
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_GET_HW_SPEC:
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+                if (rv != MLAN_STATUS_SUCCESS)
+                {
+                    return -WM_FAIL;
+                }
+
+                (void)wifi_event_completion(WIFI_EVENT_GET_HW_SPEC, WIFI_EVENT_REASON_SUCCESS, NULL);
+                break;
+            case HostCmd_CMD_802_11_SCAN:
+                if (resp->result != HostCmd_RESULT_OK)
+                {
+                    if (resp->result == HostCmd_RESULT_BUSY)
+                    {
+                        wifi_w("ED MAC: Scan temporary aborted, due to noisy environment");
+                    }
+                    else
+                    {
+                        wifi_w("Scan temporary failure");
+                    }
+                    /*
+                     * Abort the split scan. The firmware has returned
+                     * scan failure.
+                     */
+                    wlan_abort_split_scan();
+                    wifi_user_scan_config_cleanup();
+
+                    (void)wifi_event_completion(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_FAILURE, NULL);
+                    break;
+                }
+
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+                if (rv != MLAN_STATUS_SUCCESS)
+                {
+                    wifi_user_scan_config_cleanup();
+                    return -WM_FAIL;
+                }
+
+                if (is_split_scan_complete())
+                {
+                    wifi_d("Split scan complete");
+                    wifi_user_scan_config_cleanup();
+
+                    (void)wifi_event_completion(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_SUCCESS, NULL);
+                }
+                break;
+#if CONFIG_EXT_SCAN_SUPPORT
+            case HostCmd_CMD_802_11_SCAN_EXT:
+                if (resp->result != 0)
+                {
+                    wifi_w("Scan temporary failure");
+                    /*
+                     * Abort the split scan. The firmware has returned
+                     * scan failure.
+                     */
+                    wlan_abort_split_scan();
+                    wifi_user_scan_config_cleanup();
+
+                    (void)wifi_event_completion(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_FAILURE, NULL);
+                }
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+                if (rv != MLAN_STATUS_SUCCESS)
+                {
+                    return -WM_FAIL;
+                }
+                break;
+#endif
+            case HostCmd_CMD_802_11_DEAUTHENTICATE:
+                (void)wlan_ret_802_11_deauthenticate(pmpriv, resp, NULL);
+#if !CONFIG_WPA_SUPP
+                (void)wifi_event_completion(WIFI_EVENT_DEAUTHENTICATION, WIFI_EVENT_REASON_SUCCESS, NULL);
+#endif
+                break;
+            case HostCmd_CMD_802_11_HS_CFG_ENH:
+#if CONFIG_HOST_SLEEP
+                wifi_process_hs_cfg_resp((t_u8 *)resp);
+#endif
+                break;
+            case HostCmd_CMD_802_11_PS_MODE_ENH:
+            {
+#if !CONFIG_MEM_POOLS
+                t_u16 *ps_action_p = (t_u16 *)OSA_MemoryAllocate(sizeof(t_u16));
+#else
+                t_u16 *ps_action_p                  = (t_u16 *)OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+                if (ps_action_p != NULL)
+                {
+                    result = wifi_process_ps_enh_response((t_u8 *)resp, &ps_event, ps_action_p);
+
+                    if (ps_event != (t_u16)WIFI_EVENT_PS_INVALID)
+                    {
+#if CONFIG_WNM_PS
+                        if (ps_event == WIFI_EVENT_WNM_PS)
+                        {
+                            if (wifi_event_completion((enum wifi_event)ps_event, result,
+                                                      (void *)((t_u32)ps_action_p)) != WM_SUCCESS)
+                            {
+#if !CONFIG_MEM_POOLS
+                                OSA_MemoryFree((void *)ps_action_p);
+#else
+                                OSA_MemoryPoolFree(buf_32_MemoryPool, ps_action_p);
+#endif
+                            }
+                        }
+                        else
+#endif
+                        {
+                            if (wifi_event_completion((enum wifi_event)ps_event, result, (void *)ps_action_p) !=
+                                WM_SUCCESS)
+                            {
+#if !CONFIG_MEM_POOLS
+                                OSA_MemoryFree((void *)ps_action_p);
+#else
+                                OSA_MemoryPoolFree(buf_32_MemoryPool, ps_action_p);
+#endif
+                            }
+                            else
+                            {
+                                /*do nothing*/
+                            }
+                        }
+                    }
+                    else
+                    {
+#if !CONFIG_MEM_POOLS
+                        OSA_MemoryFree((void *)ps_action_p);
+#else
+                        OSA_MemoryPoolFree(buf_32_MemoryPool, ps_action_p);
+#endif
+                    }
+                }
+            }
+            break;
+#if 0
+            case HostCmd_CMD_SUPPLICANT_PMK:
+                (void)wifi_event_completion(WIFI_EVENT_SUPPLICANT_PMK,
+                        WIFI_EVENT_REASON_SUCCESS,
+                        resp);
+                break;
+#endif
+#if CONFIG_WMM_UAPSD
+            case HostCmd_CMD_802_11_SLEEP_PERIOD:
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, wm_wifi.cmd_resp_priv);
+                if (rv != MLAN_STATUS_SUCCESS)
+                    return -WM_FAIL;
+                break;
+#endif
+            case HostCmd_CMD_802_11_RF_CHANNEL:
+            {
+                const HostCmd_DS_802_11_RF_CHANNEL *ch = &resp->params.rf_channel;
+                if (ch->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        wifi_rf_channel_t *rf_c = (wifi_rf_channel_t *)wm_wifi.cmd_resp_priv;
+                        rf_c->current_channel   = ch->current_channel;
+                        rf_c->rf_type           = ch->rf_type;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+                /* Is this required */
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+            }
+            break;
+#ifdef SD8801
+            case HostCmd_CMD_ROBUST_COEX:
+            {
+                const HostCmd_DS_ExtBLECoex_Config_t *coex = &resp->params.ext_ble_coex_cfg;
+                if (coex->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        wifi_ext_coex_stats_t *stats = (wifi_ext_coex_stats_t *)wm_wifi.cmd_resp_priv;
+                        stats->ext_radio_req_count   = coex->coex_cfg_data.EXT_RADIO_REQ_count;
+                        stats->ext_radio_pri_count   = coex->coex_cfg_data.EXT_RADIO_PRI_count;
+                        stats->wlan_grant_count      = coex->coex_cfg_data.WLAN_GRANT_count;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+#endif
+            case HostCmd_CMD_11N_CFG:
+                rv = wlan_ret_11n_cfg(pmpriv, resp, NULL);
+                break;
+            case HostCmd_CMD_11N_ADDBA_REQ:
+                (void)do_wlan_ret_11n_addba_req(pmpriv, resp);
+                break;
+            case HostCmd_CMD_11N_DELBA:
+                (void)do_wlan_ret_11n_delba(pmpriv, resp);
+                break;
+            case HostCmd_CMD_11N_ADDBA_RSP:
+                (void)do_wlan_ret_11n_addba_resp(resp);
+                break;
+#if CONFIG_AMSDU_IN_AMPDU
+            case HostCmd_CMD_AMSDU_AGGR_CTRL:
+                rv = wlan_ret_amsdu_aggr_ctrl(pmpriv, resp, NULL);
+                break;
+#endif
+            case HostCmd_CMD_MAC_MULTICAST_ADR:
+                break;
+            case HostCmd_CMD_802_11_ASSOCIATE:
+            {
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+#if !CONFIG_WPA_SUPP
+                if (rv != MLAN_STATUS_SUCCESS)
+                {
+                    (void)wifi_event_completion(WIFI_EVENT_ASSOCIATION, WIFI_EVENT_REASON_FAILURE, NULL);
+                    return -WM_FAIL;
+                }
+#endif
+
+#if CONFIG_WPA_SUPP
+                nxp_wifi_assoc_event_mlme_t *assoc_resp = &wm_wifi.assoc_resp;
+                memset(assoc_resp, 0, sizeof(nxp_wifi_assoc_event_mlme_t));
+
+                IEEEtypes_AssocRsp_t *passoc_rsp1 = (IEEEtypes_AssocRsp_t *)(void *)&resp->params;
+
+                if (passoc_rsp1->status_code == WLAN_STATUS_UNSPECIFIED_FAILURE)
+                {
+                    result = WIFI_EVENT_REASON_FAILURE;
+                    goto assoc_resp_ret;
+                }
+
+                IEEEtypes_AssocRsp_t *passoc_rsp =
+                    (IEEEtypes_AssocRsp_t *)((t_u8 *)(&resp->params) + sizeof(IEEEtypes_MgmtHdr_t));
+
+#if CONFIG_11R
+                pmpriv->ft_roam = MFALSE;
+#endif
+                assoc_resp->frame.frame_len = resp->size - S_DS_GEN;
+                if (assoc_resp->frame.frame_len > (int)sizeof(assoc_resp->frame.frame))
+                {
+                    wifi_e("Assocate response payload length (%d) overs the max length(%d), dropping it",
+                           assoc_resp->frame.frame_len, sizeof(assoc_resp->frame.frame));
+                    assoc_resp->frame.frame_len = 0;
+                    result                      = WIFI_EVENT_REASON_FAILURE;
+                    goto assoc_resp_ret;
+                }
+                // coverity[overrun-buffer-arg:SUPPRESS]
+                memcpy(assoc_resp->frame.frame, passoc_rsp1, assoc_resp->frame.frame_len);
+
+                if (pmpriv->assoc_req_size && (pmpriv->assoc_req_size <= (int)sizeof(assoc_resp->req_ie)))
+                {
+                    assoc_resp->req_ie_len = pmpriv->assoc_req_size;
+                    // coverity[overrun-buffer-arg:SUPPRESS]
+                    memcpy(assoc_resp->req_ie, pmpriv->assoc_req_buf, assoc_resp->req_ie_len);
+                }
+                if (wm_wifi.supp_if_callbk_fns->assoc_resp_callbk_fn)
+                {
+                    pmpriv->auth_flag = 0;
+
+                    wm_wifi.supp_if_callbk_fns->assoc_resp_callbk_fn(wm_wifi.if_priv, assoc_resp,
+                                                                     sizeof(nxp_wifi_assoc_event_mlme_t));
+                }
+#else
+                IEEEtypes_AssocRsp_t *passoc_rsp = (IEEEtypes_AssocRsp_t *)(void *)&resp->params;
+#endif
+                if (passoc_rsp->status_code == 0U)
+                {
+                    result = WIFI_EVENT_REASON_SUCCESS;
+                }
+                else
+                {
+#if CONFIG_WIFI_EXTRA_DEBUG
+                    wifi_w("Assoc failed: Status: %d\n\r", passoc_rsp->status_code);
+                    wifi_show_assoc_fail_reason(passoc_rsp->status_code);
+#endif
+                    /* Since we have failed assoc attempt clear this */
+                    pmpriv->media_connected = MFALSE;
+                }
+                /** Clear BSS blacklist if association is successful */
+                if (result == WIFI_EVENT_REASON_SUCCESS)
+                {
+                    (void)memset(&pmpriv->adapter->blacklist_bss.bssids, 0x0,
+                                 sizeof(pmpriv->adapter->blacklist_bss.bssids));
+                    pmpriv->adapter->blacklist_bss.num_bssid = 0;
+                }
+#if CONFIG_WPA_SUPP
+            assoc_resp_ret:
+#endif
+                (void)wifi_event_completion(WIFI_EVENT_ASSOCIATION, result, NULL);
+            }
+            break;
+            case HostCmd_CMD_802_11_MAC_ADDRESS:
+            {
+                HostCmd_DS_802_11_MAC_ADDRESS *pmac_addr = &resp->params.mac_addr;
+                int ret                                  = -WM_FAIL;
+#if !CONFIG_MEM_POOLS
+                sta_addr = OSA_MemoryAllocate(MLAN_MAC_ADDR_LENGTH);
+#else
+                sta_addr                         = OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+                if (sta_addr == MNULL)
+                {
+                    wifi_w("No mem. Cannot process MAC address command");
+                    break;
+                }
+                (void)memcpy((void *)sta_addr, (const void *)((uint8_t *)&pmac_addr->mac_addr), MLAN_MAC_ADDR_LENGTH);
+                if (bss_type == MLAN_BSS_TYPE_STA)
+                {
+                    (void)memcpy(dev_mac_addr, sta_addr, MLAN_MAC_ADDR_LENGTH);
+                    ret = wifi_event_completion(WIFI_EVENT_STA_MAC_ADDR_CONFIG, WIFI_EVENT_REASON_SUCCESS, sta_addr);
+                }
+                else if (bss_type == MLAN_BSS_TYPE_UAP)
+                {
+                    (void)memcpy(dev_mac_addr_uap, sta_addr, MLAN_MAC_ADDR_LENGTH);
+                    ret = wifi_event_completion(WIFI_EVENT_UAP_MAC_ADDR_CONFIG, WIFI_EVENT_REASON_SUCCESS, sta_addr);
+                }
+
+                if (ret != WM_SUCCESS)
+                {
+                    /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                    OSA_MemoryFree((void *)sta_addr);
+#else
+                    OSA_MemoryPoolFree(buf_32_MemoryPool, sta_addr);
+#endif
+                }
+            }
+            break;
+            case HostCmd_CMD_802_11_KEY_MATERIAL:
+                break;
+            case HostCmd_CMD_MAC_REG_ACCESS:
+            {
+                HostCmd_DS_MAC_REG_ACCESS *reg;
+                reg = (HostCmd_DS_MAC_REG_ACCESS *)&resp->params.mac_reg;
+                if (reg->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *mac_reg = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        *mac_reg          = reg->value;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_BBP_REG_ACCESS:
+            {
+                HostCmd_DS_BBP_REG_ACCESS *reg;
+                reg = (HostCmd_DS_BBP_REG_ACCESS *)&resp->params.bbp_reg;
+                if (reg->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *bbp_reg = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        *bbp_reg          = reg->value;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_RF_REG_ACCESS:
+            {
+                HostCmd_DS_RF_REG_ACCESS *reg;
+                reg = (HostCmd_DS_RF_REG_ACCESS *)&resp->params.rf_reg;
+                if (reg->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *rf_reg = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        *rf_reg          = reg->value;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_CAU_REG_ACCESS:
+            {
+                HostCmd_DS_RF_REG_ACCESS *reg;
+                reg = (HostCmd_DS_RF_REG_ACCESS *)&resp->params.rf_reg;
+                if (reg->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *cau_reg = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        *cau_reg          = reg->value;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_802_11_EEPROM_ACCESS:
+            {
+                HostCmd_DS_802_11_EEPROM_ACCESS *eeprom;
+                eeprom = (HostCmd_DS_802_11_EEPROM_ACCESS *)&resp->params.eeprom;
+                if (wm_wifi.cmd_resp_priv != NULL)
+                {
+                    uint8_t *buf = (uint8_t *)wm_wifi.cmd_resp_priv;
+                    (void)memcpy((void *)buf, (const void *)&eeprom->value, eeprom->byte_count);
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_MEM_ACCESS:
+            {
+                HostCmd_DS_MEM_ACCESS *mem;
+                mem = (HostCmd_DS_MEM_ACCESS *)&resp->params.mem;
+                if (mem->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *mem_value = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        *mem_value          = mem->value;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_MGMT_IE_LIST:
+            {
+                HostCmd_DS_MGMT_IE_LIST_CFG *ie_list_cfg;
+                ie_list_cfg = (HostCmd_DS_MGMT_IE_LIST_CFG *)&resp->params.mgmt_ie_list;
+                if (wm_wifi.cmd_resp_priv != NULL)
+                {
+                    uint8_t *buf = (uint8_t *)wm_wifi.cmd_resp_priv;
+                    (void)memcpy((void *)buf, (const void *)(&ie_list_cfg->ds_mgmt_ie.ie_data_list[0]),
+                                 ie_list_cfg->ds_mgmt_ie.len);
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_VERSION_EXT:
+                load_ver_ext(resp);
+                break;
+            case HostCmd_CMD_802_11_RF_ANTENNA:
+            {
+                HostCmd_DS_802_11_RF_ANTENNA *rf_antenna_ctrl;
+                rf_antenna_ctrl = (HostCmd_DS_802_11_RF_ANTENNA *)&resp->params.antenna;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (rf_antenna_ctrl->action == HostCmd_ACT_GET_BOTH)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            wifi_antcfg_t *antcfg      = (wifi_antcfg_t *)wm_wifi.cmd_resp_priv;
+                            *(antcfg->ant_mode)        = rf_antenna_ctrl->antenna_mode;
+                            *(antcfg->evaluate_time)   = rf_antenna_ctrl->evaluate_time;
+                            *(antcfg->current_antenna) = rf_antenna_ctrl->current_antenna;
+#ifdef RW610
+                            *(antcfg->evaluate_mode) = rf_antenna_ctrl->evaluate_mode;
+#endif
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_CW_MODE_CTRL:
+            {
+                HostCmd_DS_CW_MODE_CTRL *cw_mode_ctrl;
+                cw_mode_ctrl = (HostCmd_DS_CW_MODE_CTRL *)&resp->params.cwmode;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (cw_mode_ctrl->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            wifi_cw_mode_ctrl_t *cwmode_ctrl = (wifi_cw_mode_ctrl_t *)wm_wifi.cmd_resp_priv;
+                            cwmode_ctrl->mode                = cw_mode_ctrl->mode;
+                            cwmode_ctrl->channel             = cw_mode_ctrl->channel;
+                            cwmode_ctrl->chanInfo            = cw_mode_ctrl->chanInfo;
+                            cwmode_ctrl->txPower             = wlan_cpu_to_le16(cw_mode_ctrl->txPower);
+                            cwmode_ctrl->rateInfo            = wlan_cpu_to_le32(cw_mode_ctrl->rateInfo);
+                            cwmode_ctrl->pktLength           = wlan_cpu_to_le16(cw_mode_ctrl->pktLength);
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_RSSI_INFO:
+            {
+                HostCmd_DS_802_11_RSSI_INFO_RSP *prssi_info_rsp =
+                    (HostCmd_DS_802_11_RSSI_INFO_RSP *)(void *)&resp->params;
+                if (wm_wifi.cmd_resp_priv != NULL)
+                {
+                    wifi_rssi_info_t *rssi_info = (wifi_rssi_info_t *)wm_wifi.cmd_resp_priv;
+                    compute_rssi_values(prssi_info_rsp, rssi_info);
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case HostCmd_CMD_802_11_NET_MONITOR:
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+                break;
+            case HOST_CMD_APCMD_SYS_CONFIGURE:
+                wifi_uap_handle_cmd_resp(resp);
+                break;
+            case HostCmd_CMD_TXPWR_CFG:
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, wm_wifi.cmd_resp_ioctl);
+                if (rv != MLAN_STATUS_SUCCESS)
+                {
+                    return -WM_FAIL;
+                }
+                break;
+            case HostCmd_CMD_TX_RATE_CFG:
+            {
+                const HostCmd_DS_TX_RATE_CFG *tx_rate_cfg = &resp->params.tx_rate_cfg;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (tx_rate_cfg->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_ioctl != NULL)
+                        {
+                            wifi_ds_rate *ds_rate = (wifi_ds_rate *)wm_wifi.cmd_resp_ioctl;
+                            rv                    = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, ds_rate);
+                            if (rv != MLAN_STATUS_SUCCESS)
+                            {
+                                wm_wifi.cmd_resp_status = -WM_FAIL;
+                            }
+                            else
+                            {
+                                wm_wifi.cmd_resp_status = WM_SUCCESS;
+                            }
+                        }
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_802_11_SNMP_MIB:
+#if CONFIG_TURBO_MODE
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    t_u8 *turbo_mode           = (t_u8 *)wm_wifi.cmd_resp_priv;
+                    t_u8 *tlv                  = (t_u8 *)((t_u8 *)resp + S_DS_GEN);
+                    turbo_mode_para *turbo_ptr = (turbo_mode_para *)tlv;
+                    if (turbo_ptr->action == ACTION_GET)
+                    {
+                        (void)memcpy(turbo_mode, &turbo_ptr->mode, sizeof(t_u8));
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+#endif
+                rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+                if (rv != MLAN_STATUS_SUCCESS)
+                {
+                    return -WM_FAIL;
+                }
+                break;
+            case HostCmd_CMD_OTP_READ_USER_DATA:
+            {
+                const HostCmd_DS_OTP_USER_DATA *user_data = &resp->params.otp_user_data;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (user_data->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            uint8_t *buf = (uint8_t *)wm_wifi.cmd_resp_priv;
+                            (void)memcpy((void *)buf, (const void *)user_data->user_data, user_data->user_data_length);
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_CFG_DATA:
+            {
+                const HostCmd_DS_802_11_CFG_DATA *cfg_data = &resp->params.cfg_data;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (cfg_data->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            wifi_cal_data_t *cal_data_cfg = (wifi_cal_data_t *)wm_wifi.cmd_resp_priv;
+#if !CONFIG_MEM_POOLS
+                            cal_data_cfg->data = (uint8_t *)OSA_MemoryAllocate(cfg_data->data_len);
+#else
+                            cal_data_cfg->data = (uint8_t *)OSA_MemoryPoolAllocate(buf_2048_MemoryPool);
+#endif
+                            if (cal_data_cfg->data == MNULL)
+                            {
+                                wifi_w(
+                                    "No mem. Cannot"
+                                    "process CAL DATA command");
+                                break;
+                            }
+                            cal_data_cfg->data_len = cfg_data->data_len;
+
+                            (void)memcpy((void *)cal_data_cfg->data, (const void *)cfg_data->data, cfg_data->data_len);
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_AUTO_RECONNECT:
+            {
+                const HostCmd_DS_AUTO_RECONNECT *auto_reconn = &resp->params.auto_reconnect;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (auto_reconn->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            wifi_auto_reconnect_config_t *auto_reconnect_config =
+                                (wifi_auto_reconnect_config_t *)wm_wifi.cmd_resp_priv;
+
+                            auto_reconnect_config->reconnect_counter  = auto_reconn->reconnect_counter;
+                            auto_reconnect_config->reconnect_interval = auto_reconn->reconnect_interval;
+                            auto_reconnect_config->flags              = auto_reconn->flags;
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_HS_WAKEUP_REASON:
+            {
+                const HostCmd_DS_HS_WAKEUP_REASON *hs_wakeup_reason = &resp->params.hs_wakeup_reason;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        t_u16 *wakeup_reason = (t_u16 *)wm_wifi.cmd_resp_priv;
+                        *wakeup_reason       = hs_wakeup_reason->wakeup_reason;
+                    }
+
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_RX_MGMT_IND:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_CHANNEL_TRPC_CONFIG:
+            {
+                HostCmd_DS_CHAN_TRPC_CONFIG *chan_trpc_cfg = &resp->params.chan_trpc_cfg;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (chan_trpc_cfg->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            t_u8 i;
+                            t_u8 mod_num = 0;
+                            t_u8 *pByte  = NULL;
+                            t_u16 left_len;
+                            MrvlIETypes_ChanTRPCConfig_t *trpc_tlv = NULL;
+                            MrvlIEtypes_Data_t *pTlvHdr;
+                            wifi_txpwrlimit_t *txpwrlimit = (wifi_txpwrlimit_t *)wm_wifi.cmd_resp_priv;
+
+                            txpwrlimit->subband = (wifi_SubBand_t)chan_trpc_cfg->reserved;
+
+                            pByte    = (t_u8 *)chan_trpc_cfg + 4;
+                            left_len = resp->size - (t_u16)S_DS_GEN - 4U;
+                            while (left_len >= sizeof(pTlvHdr->header))
+                            {
+                                pTlvHdr             = (MrvlIEtypes_Data_t *)(void *)pByte;
+                                pTlvHdr->header.len = wlan_le16_to_cpu(pTlvHdr->header.len);
+
+                                switch (wlan_le16_to_cpu(pTlvHdr->header.type))
+                                {
+                                    case TLV_TYPE_CHAN_TRPC_CONFIG:
+                                        trpc_tlv = (MrvlIETypes_ChanTRPCConfig_t *)(void *)pTlvHdr;
+#if !CONFIG_11AC
+                                        /*
+                                         * For 2.4 GHz band, we do not support HT40 Modulation Groups.
+                                         * Limit the number of mod groups to 7.
+                                         */
+                                        if (!txpwrlimit->subband)
+                                        {
+                                            mod_num = 7;
+                                        }
+                                        else
+                                        {
+#endif /* CONFIG_11AC */
+                                            mod_num =
+                                                ((t_u8)pTlvHdr->header.len - 4U) / ((t_u8)sizeof(mod_group_setting));
+#if !CONFIG_11AC
+                                        }
+#endif /* CONFIG_11AC */
+                                        txpwrlimit->txpwrlimit_config[txpwrlimit->num_chans].num_mod_grps = mod_num;
+                                        txpwrlimit->txpwrlimit_config[txpwrlimit->num_chans].chan_desc.start_freq =
+                                            trpc_tlv->start_freq;
+                                        txpwrlimit->txpwrlimit_config[txpwrlimit->num_chans].chan_desc.chan_width =
+                                            trpc_tlv->width;
+                                        txpwrlimit->txpwrlimit_config[txpwrlimit->num_chans].chan_desc.chan_num =
+                                            trpc_tlv->chan_num;
+                                        for (i = 0; i < mod_num; i++)
+                                        {
+                                            // coverity[overrun-local:SUPPRESS]
+                                            txpwrlimit->txpwrlimit_config[txpwrlimit->num_chans]
+                                                .txpwrlimit_entry[i]
+                                                .mod_group = trpc_tlv->mod_group[i].mod_group;
+                                            txpwrlimit->txpwrlimit_config[txpwrlimit->num_chans]
+                                                .txpwrlimit_entry[i]
+                                                .tx_power = trpc_tlv->mod_group[i].power;
+                                        }
+                                        txpwrlimit->num_chans++;
+                                        break;
+                                    default:
+                                        PRINTM(MINFO, "Unexpected host cmd response \n");
+                                        break;
+                                }
+                                left_len -= (pTlvHdr->header.len + (t_u16)sizeof(pTlvHdr->header));
+                                pByte += (t_u8)pTlvHdr->header.len + (t_u8)sizeof(pTlvHdr->header);
+                            }
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_802_11_GET_LOG:
+            {
+                const HostCmd_DS_802_11_GET_LOG *get_log = &resp->params.get_log;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint8_t *buf = (uint8_t *)wm_wifi.cmd_resp_priv;
+                        (void)memcpy((void *)buf, (const void *)get_log, sizeof(HostCmd_DS_802_11_GET_LOG));
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_RECONFIGURE_TX_BUFF:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+                break;
+            case HostCmd_CMD_PMF_PARAMS:
+            {
+                const HostCmd_DS_PMF_PARAMS *get_pmf_params = &resp->params.pmf_params;
+                if ((resp->result == HostCmd_RESULT_OK) && (get_pmf_params->action == HostCmd_ACT_GEN_GET))
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        wifi_pmf_params_t *wifi_pmf_params = (wifi_pmf_params_t *)wm_wifi.cmd_resp_priv;
+
+                        wifi_pmf_params->mfpc = get_pmf_params->params.mfpc;
+                        wifi_pmf_params->mfpr = get_pmf_params->params.mfpr;
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#if CONFIG_RF_TEST_MODE
+            case HostCmd_CMD_MFG_COMMAND:
+            {
+                if ((resp->result == HostCmd_RESULT_OK) && wm_wifi.cmd_resp_priv)
+                {
+                    rv = wlan_ret_mfg(pmpriv, resp, wm_wifi.cmd_resp_priv);
+                    if (rv == MLAN_STATUS_SUCCESS)
+                    {
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    }
+                    else
+                    {
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#endif
+            case HostCmd_CMD_GET_TSF:
+            {
+                const HostCmd_DS_TSF *tsf_pointer = (HostCmd_DS_TSF *)&resp->params.tsf_cfg;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        t_u64 *tsf = (t_u64 *)(wm_wifi.cmd_resp_priv);
+
+                        *tsf = tsf_pointer->tsf;
+
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    }
+                    else
+                    {
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_BOOT_SLEEP:
+            {
+                const HostCmd_DS_BOOT_SLEEP *boot_sleep_pointer = (HostCmd_DS_BOOT_SLEEP *)&resp->params.tsf_cfg;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        t_u16 *enable = (t_u16 *)(wm_wifi.cmd_resp_priv);
+
+                        *enable = boot_sleep_pointer->enable;
+
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    }
+                    else
+                    {
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#if CONFIG_WIFI_CLOCKSYNC
+            case HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, wm_wifi.cmd_resp_ioctl);
+                    if (rv != MLAN_STATUS_SUCCESS)
+                    {
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    }
+                    else
+                    {
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    }
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+#endif
+            case HostCmd_CMD_AUTO_TX:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+#if CONFIG_CLOUD_KEEP_ALIVE
+                    const HostCmd_DS_AUTO_TX *auto_tx              = (HostCmd_DS_AUTO_TX *)&resp->params.auto_tx;
+                    MrvlIEtypes_Cloud_Keep_Alive_t *keep_alive_tlv = MNULL;
+                    t_u8 *enable;
+                    MrvlIEtypesHeader_t *header = (MrvlIEtypesHeader_t *)auto_tx->tlv_buffer;
+                    header->type                = wlan_le16_to_cpu(header->type);
+
+                    if ((auto_tx->action == HostCmd_ACT_GEN_GET) && (header->type == TLV_TYPE_CLOUD_KEEP_ALIVE) &&
+                        (wm_wifi.cmd_resp_priv != NULL))
+                    {
+                        keep_alive_tlv        = (MrvlIEtypes_Cloud_Keep_Alive_t *)auto_tx->tlv_buffer;
+                        enable                = (t_u8 *)wm_wifi.cmd_resp_priv;
+                        *enable               = keep_alive_tlv->enable;
+                        wm_wifi.cmd_resp_priv = NULL;
+                    }
+#endif
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#ifdef OTP_CHANINFO
+            case HostCmd_CMD_CHAN_REGION_CFG:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+                    if (rv != MLAN_STATUS_SUCCESS)
+                    {
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    }
+                    else
+                    {
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    }
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#endif
+#if CONFIG_11AX
+            case HostCmd_CMD_11AX_CFG:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        mlan_ds_11ax_he_cfg *cfg = (mlan_ds_11ax_he_cfg *)wm_wifi.cmd_resp_priv;
+                        rv                       = wlan_ret_11ax_cfg(pmpriv, resp, cfg);
+                        if (rv != MLAN_STATUS_SUCCESS)
+                            wm_wifi.cmd_resp_status = -WM_FAIL;
+                        else
+                            wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    }
+                }
+                else
+                {
+                    rv                      = MLAN_STATUS_FAILURE;
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#if CONFIG_11AX_TWT
+            case HostCmd_CMD_TWT_CFG:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        if (resp->params.twtcfg.sub_id == MLAN_11AX_TWT_SETUP_SUBID)
+                        {
+                            mlan_ds_twt_setup *cfg = (mlan_ds_twt_setup *)wm_wifi.cmd_resp_priv;
+                            (void)memcpy(cfg, &resp->params.twtcfg.param.twt_setup, sizeof(mlan_ds_twt_setup));
+                        }
+                        else if (resp->params.twtcfg.sub_id == MLAN_11AX_TWT_REPORT_SUBID)
+                        {
+                            mlan_ds_twt_report *cfg = (mlan_ds_twt_report *)wm_wifi.cmd_resp_priv;
+                            (void)memcpy(cfg, &resp->params.twtcfg.param.twt_report, sizeof(mlan_ds_twt_report));
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    rv                      = MLAN_STATUS_FAILURE;
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#endif /* CONFIG_11AX_TWT */
+            case HostCmd_CMD_11AX_CMD:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, wm_wifi.cmd_resp_ioctl);
+                    if (rv != MLAN_STATUS_SUCCESS)
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    else
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    rv                      = MLAN_STATUS_FAILURE;
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#if CONFIG_MMSF
+            case HostCmd_CMD_DBGS_CFG:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        wifi_mmsf_cfg_t *mmsf_cfg     = (wifi_mmsf_cfg_t *)wm_wifi.cmd_resp_priv;
+                        HostCmd_DS_MMSF_CFG *MMSF_CFG = (HostCmd_DS_MMSF_CFG *)&resp->params.mmsf_cfg;
+                        if (MMSF_CFG->action == HostCmd_ACT_GEN_GET)
+                        {
+                            (void)memcpy(mmsf_cfg->enable, &MMSF_CFG->enableMMSF, sizeof(MMSF_CFG->enableMMSF));
+                            (void)memcpy(mmsf_cfg->Density, &MMSF_CFG->ampduDensity, sizeof(MMSF_CFG->ampduDensity));
+                            (void)memcpy(mmsf_cfg->MMSF, &MMSF_CFG->ampduMMSF, sizeof(MMSF_CFG->ampduMMSF));
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+#endif
+#endif
+#if (CONFIG_WIFI_TX_PER_TRACK) || (CONFIG_TX_RX_HISTOGRAM)
+            case HostCmd_CMD_TX_RX_PKT_STATS:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+#if CONFIG_TX_RX_HISTOGRAM
+                    const HostCmd_DS_TX_RX_HISTOGRAM *txrx_histogram = &resp->params.histogram;
+                    if (txrx_histogram->action != HostCmd_ACT_SET_TX_PER_TRACKING)
+                    {
+                        t_u16 cmdsize   = wlan_le16_to_cpu(resp->size);
+                        t_u16 length    = 0;
+                        t_u16 data_size = 0;
+                        t_u8 *pos       = NULL;
+
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            t_u8 *tx_rx_histogram_data = wm_wifi.cmd_resp_priv;
+                            (void)memcpy(&data_size, tx_rx_histogram_data, sizeof(data_size));
+                            length = cmdsize - S_DS_GEN - sizeof(HostCmd_DS_TX_RX_HISTOGRAM);
+
+                            if (length > 0 && (data_size >= length + sizeof(length)))
+                            {
+                                (void)memcpy(tx_rx_histogram_data, (t_u8 *)&length, sizeof(length));
+                                pos = (t_u8 *)resp + S_DS_GEN + sizeof(HostCmd_DS_TX_RX_HISTOGRAM);
+                                (void)memcpy(tx_rx_histogram_data + sizeof(length), pos, length);
+                            }
+                            else
+                            {
+                                wifi_w("TX RX histogram data error\n");
+                            }
+                        }
+                    }
+#endif
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#endif
+            case HostCmd_CMD_802_11_BG_SCAN_CONFIG:
+            {
+                HostCmd_DS_802_11_BG_SCAN_CONFIG *bg_scan = &resp->params.bg_scan_config;
+                /* TODO: command response handler for GET command */
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (bg_scan->enable)
+                        pmpriv->roaming_configured = MTRUE;
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+            case HostCmd_CMD_802_11_BG_SCAN_QUERY:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, NULL);
+                    if (rv != MLAN_STATUS_SUCCESS)
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    else
+                    {
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                        wifi_d("BG scan query complete");
+
+                        (void)wifi_event_completion(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_SUCCESS, NULL);
+                    }
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+            case HostCmd_CMD_802_11_SUBSCRIBE_EVENT:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, wm_wifi.cmd_resp_priv);
+                    if (rv != MLAN_STATUS_SUCCESS)
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    else
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+#if CONFIG_WIFI_EU_CRYPTO
+            case HostCmd_CMD_EU_CRYPTO:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        EU_Crypto *EU_Data = (EU_Crypto *)wm_wifi.cmd_resp_priv;
+                        HostCmd_DS_EU_AES_CRYPTO *cmd_aes_ccmp =
+                            (HostCmd_DS_EU_AES_CRYPTO *)&resp->params.eu_aes_crypto;
+                        HostCmd_DS_EU_CRYPTO *cmd_eu_crypto = (HostCmd_DS_EU_CRYPTO *)&resp->params.eu_crypto;
+                        if (cmd_eu_crypto->Algorithm == CRYPTO_RC4 || cmd_eu_crypto->Algorithm == CRYPTO_AES_ECB ||
+                            cmd_eu_crypto->Algorithm == CRYPTO_AES_WRAP)
+                        {
+                            memcpy(EU_Data->DataLength, &cmd_eu_crypto->DataLength, sizeof(t_u16) / sizeof(t_u8));
+                            memcpy(EU_Data->Data, cmd_eu_crypto->Data, cmd_eu_crypto->DataLength);
+                        }
+                        else if (cmd_aes_ccmp->Algorithm == CRYPTO_AES_CCMP ||
+                                 cmd_aes_ccmp->Algorithm == CRYPTO_AES_GCMP)
+                        {
+                            memcpy(EU_Data->DataLength, &cmd_aes_ccmp->DataLength, sizeof(t_u16) / sizeof(t_u8));
+                            memcpy(EU_Data->Data, cmd_aes_ccmp->Data, cmd_aes_ccmp->DataLength);
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    rv                      = MLAN_STATUS_FAILURE;
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+#endif
+#if CONFIG_MULTI_CHAN
+            case HostCmd_CMD_MULTI_CHAN_CONFIG:
+            case HostCmd_CMD_MULTI_CHAN_POLICY:
+            case HostCmd_CMD_DRCS_CONFIG:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wlan_ops_sta_process_cmdresp(pmpriv, command, resp, wm_wifi.cmd_resp_ioctl);
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    rv                      = MLAN_STATUS_FAILURE;
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+                break;
+#endif
+#if CONFIG_WPA_SUPP
+            case HostCmd_CMD_802_11_REMAIN_ON_CHANNEL:
+            {
+                const HostCmd_DS_REMAIN_ON_CHANNEL *remain_channel = &resp->params.remain_on_chan;
+#if !CONFIG_MEM_POOLS
+                t_u8 *cancel_channel = (t_u8 *)OSA_MemoryAllocate(sizeof(t_u8));
+#else
+                t_u8 *cancel_channel = (t_u8 *)OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+                if (cancel_channel != NULL)
+                {
+                    *cancel_channel              = remain_channel->action == HostCmd_ACT_GEN_REMOVE ? MTRUE : MFALSE;
+                    mlan_adap->remain_on_channel = remain_channel->action == HostCmd_ACT_GEN_REMOVE ? MFALSE : MTRUE;
+                    if (*cancel_channel)
+                    {
+                        if (wifi_event_completion(WIFI_EVENT_REMAIN_ON_CHANNEL, WIFI_EVENT_REASON_SUCCESS,
+                                                  (void *)cancel_channel) != WM_SUCCESS)
+                        {
+#if !CONFIG_MEM_POOLS
+                            OSA_MemoryFree(cancel_channel);
+#else
+                            OSA_MemoryPoolFree(buf_32_MemoryPool, cancel_channel);
+#endif
+                            cancel_channel = NULL;
+                        }
+                    }
+                    else
+                    {
+                        if (wifi_event_completion(WIFI_EVENT_REMAIN_ON_CHANNEL, WIFI_EVENT_REASON_SUCCESS,
+                                                  (void *)cancel_channel) != WM_SUCCESS)
+                        {
+#if !CONFIG_MEM_POOLS
+                            OSA_MemoryFree(cancel_channel);
+#else
+                            OSA_MemoryPoolFree(buf_32_MemoryPool, cancel_channel);
+#endif
+                            cancel_channel = NULL;
+                        }
+                    }
+                }
+            }
+            break;
+#endif
+
+#if CONFIG_RX_ABORT_CFG
+            case HostCmd_CMD_RX_ABORT_CFG:
+            {
+                HostCmd_DS_RX_ABORT_CFG *cfg;
+                cfg = (HostCmd_DS_RX_ABORT_CFG *)&resp->params.rx_abort_cfg;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (cfg->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            rx_abort_cfg_t *rx_abort_cfg = (rx_abort_cfg_t *)wm_wifi.cmd_resp_priv;
+                            rx_abort_cfg->enable         = cfg->enable;
+                            rx_abort_cfg->rssi_threshold = (int)cfg->rssi_threshold;
+                            if (rx_abort_cfg->rssi_threshold > 0x7f)
+                            {
+                                rx_abort_cfg->rssi_threshold = -(256 - rx_abort_cfg->rssi_threshold);
+                            }
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+#endif
+#if CONFIG_RX_ABORT_CFG_EXT
+            case HostCmd_CMD_RX_ABORT_CFG_EXT:
+            {
+                HostCmd_DS_RX_ABORT_CFG_EXT *cfg;
+                cfg = (HostCmd_DS_RX_ABORT_CFG_EXT *)&resp->params.rx_abort_cfg_ext;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (cfg->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            rx_abort_cfg_ext_t *rx_abort_cfg_ext   = (rx_abort_cfg_ext_t *)wm_wifi.cmd_resp_priv;
+                            rx_abort_cfg_ext->enable               = cfg->enable;
+                            rx_abort_cfg_ext->rssi_margin          = (int)cfg->rssi_margin;
+                            rx_abort_cfg_ext->ceil_rssi_threshold  = (int)cfg->ceil_rssi_threshold;
+                            rx_abort_cfg_ext->floor_rssi_threshold = (int)cfg->floor_rssi_threshold;
+                            rx_abort_cfg_ext->current_dynamic_rssi_threshold = (int)cfg->current_dynamic_rssi_threshold;
+                            rx_abort_cfg_ext->rssi_default_config            = (int)cfg->rssi_default_config;
+                            rx_abort_cfg_ext->edmac_enable                   = (int)cfg->edmac_enable;
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+#endif
+#if CONFIG_CCK_DESENSE_CFG
+            case HostCmd_CMD_CCK_DESENSE_CFG:
+            {
+                HostCmd_DS_CCK_DESENSE_CFG *cfg_cmd;
+                cfg_cmd = (HostCmd_DS_CCK_DESENSE_CFG *)&resp->params.cck_desense_cfg;
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    if (cfg_cmd->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            cck_desense_cfg_t *cck_desense_cfg = (cck_desense_cfg_t *)wm_wifi.cmd_resp_priv;
+                            cck_desense_cfg->mode              = wlan_le16_to_cpu(cfg_cmd->mode);
+                            cck_desense_cfg->margin            = (int)cfg_cmd->margin;
+                            if (cck_desense_cfg->margin > 0x7f)
+                            {
+                                cck_desense_cfg->margin = -(256 - cck_desense_cfg->margin);
+                            }
+                            cck_desense_cfg->ceil_thresh = (int)cfg_cmd->ceil_thresh;
+                            if (cck_desense_cfg->ceil_thresh > 0x7f)
+                            {
+                                cck_desense_cfg->ceil_thresh = -(256 - cck_desense_cfg->ceil_thresh);
+                            }
+                            cck_desense_cfg->num_on_intervals  = (int)cfg_cmd->num_on_intervals;
+                            cck_desense_cfg->num_off_intervals = (int)cfg_cmd->num_off_intervals;
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+#endif
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+            case HostCmd_CMD_TX_AMPDU_PROT_MODE:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    const HostCmd_DS_CMD_TX_AMPDU_PROT_MODE *data = &resp->params.tx_ampdu_prot_mode;
+                    if (data->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            tx_ampdu_prot_mode_para *prot_mode = (tx_ampdu_prot_mode_para *)wm_wifi.cmd_resp_priv;
+                            prot_mode->mode                    = data->mode;
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                break;
+#endif
+#if CONFIG_TSP
+            case HostCmd_CMD_TSP_CFG:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    TSP_CFG *tsp_get_cfg     = (TSP_CFG *)wm_wifi.cmd_resp_priv;
+                    HostCmd_DS_TSP_CFG *data = &resp->params.tsp_cfg;
+                    if (data->action == HostCmd_ACT_GEN_GET)
+                    {
+                        *(tsp_get_cfg->thermalPowerMgmtenable) = data->thermalPowerMgmtenable;
+                        *(tsp_get_cfg->powerMgmtBackoff)       = data->powerMgmtBackoff;
+                        *(tsp_get_cfg->lowPwrBOThrshld)        = data->lowPwrBOThrshld;
+                        *(tsp_get_cfg->highPwrBOThrshld)       = data->highPwrBOThrshld;
+                        *(tsp_get_cfg->dutycycstep)            = data->dutycycstep;
+                        *(tsp_get_cfg->dutycycmin)             = data->dutycycmin;
+                        *(tsp_get_cfg->highthrtemp)            = data->highthrtemp;
+                        *(tsp_get_cfg->lowthrtemp)             = data->lowthrtemp;
+                        *(tsp_get_cfg->currCAUTemp)            = data->currCAUTemp;
+                        *(tsp_get_cfg->currRFUTemp)            = data->currRFUTemp;
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                break;
+#endif
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+            case HostCmd_CMD_FTM_SESSION_CFG:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    wifi_ftm_process_cfg_resp(resp);
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                break;
+            case HostCmd_CMD_FTM_SESSION_CTRL:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    wifi_ftm_process_ctrl_resp(resp);
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                break;
+#endif
+#if (CONFIG_COEX_DUTY_CYCLE) || (CONFIG_EXTERNAL_COEX_PTA) || (CONFIG_IMD3_CFG)
+            case HostCmd_CMD_ROBUST_COEX:
+                if (resp->result == HostCmd_RESULT_OK)
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                break;
+#endif
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+            case HostCmd_CMD_INDEPENDENT_RESET_CFG:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    rv = wlan_ops_sta_process_cmdresp(pmpriv, command, resp, wm_wifi.cmd_resp_ioctl);
+                    if (rv != MLAN_STATUS_SUCCESS)
+                    {
+                        wm_wifi.cmd_resp_status = -WM_FAIL;
+                    }
+                    else
+                    {
+                        wm_wifi.cmd_resp_status = WM_SUCCESS;
+                    }
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+            }
+            break;
+#endif
+#if CONFIG_INACTIVITY_TIMEOUT_EXT
+            case HostCmd_CMD_INACTIVITY_TIMEOUT_EXT:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    const HostCmd_DS_INACTIVITY_TIMEOUT_EXT *data = &resp->params.inactivity_to;
+                    if (data->action == HostCmd_ACT_GEN_GET)
+                    {
+                        if (wm_wifi.cmd_resp_priv != NULL)
+                        {
+                            wifi_inactivity_to_t *inac_to = (wifi_inactivity_to_t *)wm_wifi.cmd_resp_priv;
+                            inac_to->timeout_unit         = data->timeout_unit;
+                            inac_to->unicast_timeout      = data->unicast_timeout;
+                            inac_to->mcast_timeout        = data->mcast_timeout;
+                            inac_to->ps_entry_timeout     = data->ps_entry_timeout;
+                            inac_to->ps_cmd_timeout       = data->ps_cmd_timeout;
+                        }
+                    }
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                break;
+#endif
+            case HostCmd_CMD_802_11_TX_FRAME:
+            {
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+            }
+            break;
+            case HostCmd_CMD_ADD_NEW_STATION:
+                if (resp->result == HostCmd_RESULT_OK)
+                {
+                    wm_wifi.cmd_resp_status = WM_SUCCESS;
+                }
+                else
+                {
+                    wm_wifi.cmd_resp_status = -WM_FAIL;
+                }
+                break;
+
+            default:
+                /* fixme: Currently handled by the legacy code. Change this
+                   handling later. Also check the default return value then*/
+                break;
+        }
+    }
+
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+/**
+ *  @brief This function will search for the specific ie
+ *
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param ie_buf  A pointer to ie_buf
+ *  @param ie_len  total ie length
+ *  @param id      ie's id
+ *
+ *  @return	       ie's poiner or MNULL
+ */
+t_u8 *wlan_get_specific_ie(pmlan_private priv, t_u8 *ie_buf, t_u8 ie_len, IEEEtypes_ElementId_e id, t_u8 ext_id)
+{
+    t_u8 bytes_left    = ie_len;
+    t_u8 *pcurrent_ptr = ie_buf;
+    t_u8 total_ie_len;
+    t_u8 *ie_ptr = MNULL;
+    IEEEtypes_ElementId_e element_id;
+    t_u8 element_len;
+#if CONFIG_11AX
+    t_u8 element_eid;
+#endif
+    ENTER();
+
+    DBG_HEXDUMP(MCMD_D, "ie", ie_buf, ie_len);
+    while (bytes_left >= 2U)
+    {
+        element_id  = (IEEEtypes_ElementId_e)(*((t_u8 *)pcurrent_ptr));
+        element_len = *((t_u8 *)pcurrent_ptr + 1);
+#if CONFIG_11AX
+        element_eid = *((t_u8 *)pcurrent_ptr + 2);
+#endif
+        total_ie_len = element_len + (t_u8)sizeof(IEEEtypes_Header_t);
+        if (bytes_left < total_ie_len)
+        {
+            PRINTM(MERROR,
+                   "InterpretIE: Error in processing IE, "
+                   "bytes left < IE length\n");
+            break;
+        }
+        if ((
+#if CONFIG_11AX
+                (ext_id == 0U) &&
+#endif
+                element_id == id)
+#if CONFIG_11AX
+            || (id == EXTENSION && element_id == id && ext_id == element_eid)
+#endif
+        )
+        {
+#if CONFIG_11AX
+            PRINTM(MCMND, "Find IE: id=%d ext_id=%d\n", id, ext_id);
+#else
+            PRINTM(MCMND, "Find IE: id=%d\n", id);
+#endif
+            DBG_HEXDUMP(MCMND, "IE", pcurrent_ptr, total_ie_len);
+            ie_ptr = pcurrent_ptr;
+            break;
+        }
+        pcurrent_ptr += element_len + 2U;
+        /* Need to account for IE ID and IE Len */
+        bytes_left -= (element_len + 2U);
+    }
+
+    LEAVE();
+
+    return ie_ptr;
+}
+
+/**
+ *  @brief This function will search for the specific ie
+ *
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param pevent  A pointer to event buf
+ *  @param sta_ptr A pointer to sta_node
+ *
+ *  @return	       N/A
+ */
+static void wrapper_wlan_check_sta_capability(pmlan_private priv, Event_Ext_t *pevent, sta_node *sta_ptr)
+{
+    t_u16 tlv_type, tlv_len;
+    t_u16 frame_control, frame_sub_type = 0;
+    t_u8 *assoc_req_ie = MNULL;
+    t_u8 ie_len = 0, assoc_ie_len = 0;
+    IEEEtypes_HTCap_t *pht_cap = MNULL;
+#if CONFIG_11AC
+    IEEEtypes_VHTCap_t *pvht_cap = MNULL;
+#endif
+#if CONFIG_11AX
+    IEEEtypes_Extension_t *phe_cap = MNULL;
+#endif
+    int tlv_buf_left         = (int)pevent->length - (int)INTF_HEADER_LEN - (int)ASSOC_EVENT_FIX_SIZE;
+    MrvlIEtypesHeader_t *tlv = (MrvlIEtypesHeader_t *)(void *)((char *)pevent + INTF_HEADER_LEN + ASSOC_EVENT_FIX_SIZE);
+    MrvlIETypes_MgmtFrameSet_t *mgmt_tlv = MNULL;
+
+    ENTER();
+    while (tlv_buf_left >= (int)sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+        if ((sizeof(MrvlIEtypesHeader_t) + tlv_len) > (unsigned int)tlv_buf_left)
+        {
+            PRINTM(MERROR, "wrong tlv: tlvLen=%d, tlvBufLeft=%d\n", tlv_len, tlv_buf_left);
+            break;
+        }
+        if (tlv_type == TLV_TYPE_UAP_MGMT_FRAME)
+        {
+            mgmt_tlv = (MrvlIETypes_MgmtFrameSet_t *)(void *)tlv;
+            (void)memcpy((void *)&frame_control, (const void *)((t_u8 *)&(mgmt_tlv->frame_control)),
+                         sizeof(frame_control));
+            frame_sub_type = IEEE80211_GET_FC_MGMT_FRAME_SUBTYPE(frame_control);
+            if ((mgmt_tlv->frame_control.type == 0U) &&
+                ((frame_sub_type == SUBTYPE_ASSOC_REQUEST) || (frame_sub_type == SUBTYPE_REASSOC_REQUEST)))
+            {
+                if (frame_sub_type == SUBTYPE_ASSOC_REQUEST)
+                {
+                    assoc_ie_len = (t_u8)sizeof(IEEEtypes_AssocRqst_t);
+                }
+                else if (frame_sub_type == SUBTYPE_REASSOC_REQUEST)
+                {
+                    assoc_ie_len = (t_u8)sizeof(IEEEtypes_ReAssocRqst_t);
+                }
+                else
+                { /* Do Nothing */
+                }
+
+                ie_len       = (t_u8)tlv_len - (t_u8)sizeof(IEEEtypes_FrameCtl_t) - assoc_ie_len;
+                assoc_req_ie = (t_u8 *)tlv + sizeof(MrvlIETypes_MgmtFrameSet_t) + assoc_ie_len;
+                pht_cap =
+                    (IEEEtypes_HTCap_t *)(void *)wlan_get_specific_ie(priv, assoc_req_ie, ie_len, HT_CAPABILITY, 0);
+
+                if (pht_cap != NULL)
+                {
+                    PRINTM(MCMND, "STA supports 11n\n");
+                    sta_ptr->is_11n_enabled = MTRUE;
+                    if (GETHT_MAXAMSDU(pht_cap->ht_cap.ht_cap_info) != 0U)
+                    {
+                        sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_8K;
+                    }
+                    else
+                    {
+                        sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_4K;
+                    }
+                }
+                else
+                {
+                    PRINTM(MCMND,
+                           "STA doesn't "
+                           "support 11n\n");
+                }
+#if CONFIG_11AC
+                pvht_cap =
+                    (IEEEtypes_VHTCap_t *)(void *)wlan_get_specific_ie(priv, assoc_req_ie, ie_len, VHT_CAPABILITY, 0);
+                if ((pvht_cap != MNULL) && (priv->is_11ac_enabled == MTRUE))
+                {
+                    PRINTM(MCMND, "STA supports 11ac\n");
+                    sta_ptr->is_11ac_enabled = MTRUE;
+                    if (GET_VHTCAP_MAXMPDULEN(wlan_le32_to_cpu(pvht_cap->vht_cap.vht_cap_info)) == 2U)
+                    {
+                        sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_12K;
+                    }
+                    else if (GET_VHTCAP_MAXMPDULEN(wlan_le32_to_cpu(pvht_cap->vht_cap.vht_cap_info)) == 1U)
+                    {
+                        sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_8K;
+                    }
+                    else
+                    {
+                        sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_4K;
+                    }
+                }
+                else
+                {
+                    PRINTM(MCMND, "STA doesn't support 11ac\n");
+                }
+#endif
+#if CONFIG_11AX
+                phe_cap =
+                    (IEEEtypes_Extension_t *)wlan_get_specific_ie(priv, assoc_req_ie, ie_len, EXTENSION, HE_CAPABILITY);
+                if (phe_cap && (priv->is_11ax_enabled == MTRUE))
+                {
+                    PRINTM(MCMND, "STA supports 11ax\n");
+                    sta_ptr->is_11ax_enabled = MTRUE;
+                    (void)memcpy((void *)((t_u8 *)&sta_ptr->he_cap), (const void *)phe_cap,
+                                 phe_cap->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                    sta_ptr->he_cap.ieee_hdr.len =
+                        MIN(phe_cap->ieee_hdr.len, sizeof(IEEEtypes_HECap_t) - sizeof(IEEEtypes_Header_t));
+                }
+                else
+                    PRINTM(MCMND, "STA doesn't support 11ax\n");
+#endif
+                break;
+            }
+        }
+        tlv_buf_left -= (int)sizeof(MrvlIEtypesHeader_t) + (int)tlv_len;
+        tlv = (MrvlIEtypesHeader_t *)(void *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+    LEAVE();
+
+    return;
+}
+
+/** Fixed size of bss start event */
+#define BSS_START_EVENT_FIX_SIZE 12U
+
+/**
+ *  @brief This function will search for the specific ie
+ *
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param pevent  A pointer to event buf
+ *
+ *  @return           N/A
+ */
+static void wrapper_wlan_check_uap_capability(pmlan_private priv, Event_Ext_t *pevent)
+{
+    t_u16 tlv_type, tlv_len;
+    int tlv_buf_left = (int)pevent->length - (int)INTF_HEADER_LEN - (int)BSS_START_EVENT_FIX_SIZE;
+    MrvlIEtypesHeader_t *tlv =
+        (MrvlIEtypesHeader_t *)(void *)((char *)pevent + INTF_HEADER_LEN + BSS_START_EVENT_FIX_SIZE);
+#if CONFIG_11AX
+    MrvlIEtypes_He_cap_t *pext_tlv = MNULL;
+#endif
+    priv->wmm_enabled    = MFALSE;
+    priv->pkt_fwd        = 0U;
+    priv->is_11n_enabled = MFALSE;
+#if CONFIG_11AC
+    priv->is_11ac_enabled = MFALSE;
+#endif
+#if CONFIG_11AX
+    priv->is_11ax_enabled = MFALSE;
+#endif
+    ENTER();
+
+    while (tlv_buf_left >= (int)sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+        if ((sizeof(MrvlIEtypesHeader_t) + tlv_len) > (unsigned int)tlv_buf_left)
+        {
+            PRINTM(MERROR, "wrong tlv: tlvLen=%d, tlvBufLeft=%d\n", tlv_len, tlv_buf_left);
+            break;
+        }
+        if (tlv_type == (t_u16)HT_CAPABILITY)
+        {
+            DBG_HEXDUMP(MCMD_D, "HT_CAP tlv", tlv, tlv_len + sizeof(MrvlIEtypesHeader_t));
+            priv->is_11n_enabled = MTRUE;
+        }
+#if CONFIG_11AC
+        if (tlv_type == (t_u16)VHT_CAPABILITY)
+        {
+            DBG_HEXDUMP(MCMD_D, "VHT_CAP tlv", tlv, tlv_len + sizeof(MrvlIEtypesHeader_t));
+            priv->is_11ac_enabled = MTRUE;
+        }
+#endif
+#if CONFIG_11AX
+        if (tlv_type == EXTENSION)
+        {
+            pext_tlv = (MrvlIEtypes_He_cap_t *)tlv;
+            if (pext_tlv->ext_id == HE_CAPABILITY)
+            {
+                DBG_HEXDUMP(MCMD_D, "HE_CAP tlv", tlv, tlv_len + sizeof(MrvlIEtypesHeader_t));
+                priv->is_11ax_enabled = MTRUE;
+            }
+        }
+#endif
+        if (tlv_type == (t_u16)TLV_TYPE_UAP_PKT_FWD_CTL)
+        {
+            DBG_HEXDUMP(MCMD_D, "pkt_fwd tlv", tlv, tlv_len + sizeof(MrvlIEtypesHeader_t));
+            priv->pkt_fwd = *((t_u8 *)tlv + sizeof(MrvlIEtypesHeader_t));
+            PRINTM(MCMND, "pkt_fwd FW: 0x%x\n", priv->pkt_fwd);
+            if ((priv->pkt_fwd & PKT_FWD_FW_BIT) != 0U)
+            {
+                priv->pkt_fwd = 0U;
+            }
+            else
+            {
+                priv->pkt_fwd |= PKT_FWD_ENABLE_BIT;
+            }
+            PRINTM(MCMND, "pkt_fwd DRV: 0x%x\n", priv->pkt_fwd);
+        }
+        tlv_buf_left -= (int)sizeof(MrvlIEtypesHeader_t) + (int)tlv_len;
+        tlv = (MrvlIEtypesHeader_t *)(void *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+    LEAVE();
+}
+
+#if (CONFIG_WNM_PS)
+void wlan_update_wnm_ps_status(wnm_ps_result *wnm_ps_result)
+{
+    if ((wnm_ps_result->action == 0) && (wnm_ps_result->result == 0))
+    {
+        /* Do nothing */
+    }
+    else if ((wnm_ps_result->action == 1) && (wnm_ps_result->result == 0))
+    {
+        ((mlan_private *)mlan_adap->priv[0])->wnm_set = false;
+    }
+    else if ((wnm_ps_result->action == 0) && (wnm_ps_result->result == 1))
+    {
+        ((mlan_private *)mlan_adap->priv[0])->wnm_set = false;
+    }
+    else if ((wnm_ps_result->action == 1) && (wnm_ps_result->result == 1))
+    {
+        /* Do nothing */
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}
+#endif
+
+#if CONFIG_WMM
+static inline void wifi_wmm_queue_lock(mlan_private *priv, t_u8 ac)
+{
+    priv->adapter->callbacks.moal_semaphore_get(priv->adapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[ac].ra_list.plock);
+}
+
+static inline void wifi_wmm_queue_unlock(mlan_private *priv, t_u8 ac)
+{
+    priv->adapter->callbacks.moal_semaphore_put(priv->adapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[ac].ra_list.plock);
+}
+
+static inline void wifi_wmm_trigger_tx(t_u8 tx_pause)
+{
+    if (tx_pause == MFALSE)
+    {
+        send_wifi_driver_tx_data_event(MLAN_BSS_TYPE_STA);
+    }
+}
+
+/*
+ *  update sta tx pause status
+ *  trigger tx handler if this is an unpause event
+ */
+static void wifi_sta_handle_event_data_pause(mlan_private *priv, MrvlIEtypes_tx_pause_t *tx_pause_tlv)
+{
+    int i;
+    t_u8 *bssid                         = MNULL;
+    raListTbl *ra_list                  = MNULL;
+    t_u8 zero_mac[MLAN_MAC_ADDR_LENGTH] = {0};
+
+    if (!priv->media_connected)
+        return;
+
+    bssid = priv->curr_bss_params.bss_descriptor.mac_address;
+    if (!__memcmp(mlan_adap, bssid, zero_mac, MLAN_MAC_ADDR_LENGTH))
+        return;
+
+    if (!__memcmp(mlan_adap, bssid, tx_pause_tlv->peermac, MLAN_MAC_ADDR_LENGTH))
+    {
+        priv->tx_pause = (tx_pause_tlv->tx_pause) ? MTRUE : MFALSE;
+
+        /* update ralists for finding alternative buffer when queue full */
+        for (i = 0; i < MAX_AC_QUEUES; i++)
+        {
+            wifi_wmm_queue_lock(priv, i);
+
+            ra_list = wlan_wmm_get_ralist_node(priv, i, tx_pause_tlv->peermac);
+            if (ra_list == MNULL)
+            {
+                wifi_wmm_queue_unlock(priv, i);
+                continue;
+            }
+
+            ra_list->tx_pause = priv->tx_pause;
+
+            wifi_wmm_queue_unlock(priv, i);
+        }
+    }
+
+    wifi_wmm_trigger_tx(tx_pause_tlv->tx_pause);
+}
+
+/*
+ *  update uap tx pause status
+ *  for self address, update the whole priv interface status
+ *  for other addresses, update corresponding ralist status
+ *  trigger tx handler if this is an unpause event
+ */
+static void wifi_uap_handle_event_data_pause(mlan_private *priv_uap, MrvlIEtypes_tx_pause_t *tx_pause_tlv)
+{
+    int i;
+    raListTbl *ra_list = MNULL;
+
+    if (!memcmp(priv_uap->curr_addr, tx_pause_tlv->peermac, MLAN_MAC_ADDR_LENGTH))
+    {
+        priv_uap->tx_pause = (tx_pause_tlv->tx_pause) ? MTRUE : MFALSE;
+    }
+    else
+    {
+        for (i = 0; i < MAX_AC_QUEUES; i++)
+        {
+            wifi_wmm_queue_lock(priv_uap, i);
+
+            ra_list = wlan_wmm_get_ralist_node(priv_uap, i, tx_pause_tlv->peermac);
+            if (ra_list == MNULL)
+            {
+                wifi_wmm_queue_unlock(priv_uap, i);
+                continue;
+            }
+
+            ra_list->tx_pause = (tx_pause_tlv->tx_pause) ? MTRUE : MFALSE;
+
+            wifi_wmm_queue_unlock(priv_uap, i);
+        }
+    }
+
+    wifi_wmm_trigger_tx(tx_pause_tlv->tx_pause);
+}
+
+void wifi_handle_event_data_pause(void *data)
+{
+    mlan_private *priv     = mlan_adap->priv[0];
+    mlan_private *priv_uap = mlan_adap->priv[1];
+    /* Event_Ext_t shares the same header but from reason_code, payload differs with tx_pause cmd */
+    Event_Ext_t *evt = (Event_Ext_t *)data;
+    t_u16 tlv_type, tlv_len;
+    int tlv_buf_left         = evt->length - MLAN_FIELD_OFFSET(Event_Ext_t, reason_code);
+    MrvlIEtypesHeader_t *tlv = (MrvlIEtypesHeader_t *)&evt->reason_code;
+
+    /* set tx pause */
+    while (tlv_buf_left >= (int)sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+
+        if ((sizeof(MrvlIEtypesHeader_t) + tlv_len) > (unsigned int)tlv_buf_left)
+        {
+            wifi_e("wrong tlv: tlvLen=%d, tlvBufLeft=%d", tlv_len, tlv_buf_left);
+            break;
+        }
+
+        if (tlv_type == TLV_TYPE_TX_PAUSE)
+        {
+            if (evt->bss_type == MLAN_BSS_TYPE_STA)
+            {
+                wifi_sta_handle_event_data_pause(priv, (MrvlIEtypes_tx_pause_t *)tlv);
+            }
+            else if (evt->bss_type == MLAN_BSS_TYPE_UAP)
+            {
+                wifi_uap_handle_event_data_pause(priv_uap, (MrvlIEtypes_tx_pause_t *)tlv);
+            }
+            else
+            {
+                wifi_w("Not support bss_type %d", evt->bss_type);
+            }
+        }
+
+        /* iterate */
+        tlv_buf_left -= (sizeof(MrvlIEtypesHeader_t) + tlv_len);
+        tlv = (MrvlIEtypesHeader_t *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+}
+#endif
+
+static void wifi_handle_event_tx_status_report(Event_Ext_t *evt)
+{
+#if CONFIG_WPA_SUPP
+    tx_status_event *tx_status = MNULL;
+    unsigned int bss_type      = (unsigned int)evt->bss_type;
+
+    tx_status = (tx_status_event *)(void *)&evt->reason_code;
+
+    if (tx_status->packet_type == 0xe5)
+    {
+        if (tx_status->status == 0U)
+        {
+            (void)wifi_event_completion(WIFI_EVENT_MGMT_TX_STATUS, WIFI_EVENT_REASON_SUCCESS, (void *)bss_type);
+        }
+        return;
+    }
+#endif
+
+}
+
+#define REASON_CODE_BSS_BLOCKED 0x21
+static void wifi_handle_blocked_sta_report(Event_Ext_t *evt)
+{
+    mlan_adapter *pmadapter = mlan_adap;
+    t_u16 reason_code       = 0;
+    int idx                 = 0;
+
+    reason_code = evt->reason_code;
+    if (reason_code == REASON_CODE_BSS_BLOCKED)
+    {
+        if (pmadapter->blacklist_bss.num_bssid == MLAN_MAX_BSS_NUM)
+        {
+            wifi_e("BSSID blacklist is full!");
+            return;
+        }
+        idx = pmadapter->blacklist_bss.num_bssid;
+        memcpy(pmadapter->blacklist_bss.bssids[idx], evt->src_mac_addr, MLAN_MAC_ADDR_LENGTH);
+        pmadapter->blacklist_bss.num_bssid++;
+        (void)PRINTF("Added BSSID ");
+        print_mac((const char *)evt->src_mac_addr);
+        (void)PRINTF("to blacklist\r\n");
+    }
+    else
+        wifi_w("Unknown reason code! Ignore the event");
+}
+
+/* fixme: duplicated from legacy. needs to be cleaned up later */
+#define IEEEtypes_REASON_UNSPEC                     1U
+#define IEEEtypes_REASON_PRIOR_AUTH_INVALID         2U
+#define IEEEtypes_REASON_DEAUTH_LEAVING             3
+#define IEEEtypes_REASON_DISASSOC_DUE_TO_INACTIVITY 4U
+#define AP_DEAUTH_REASON_MAC_ADDR_BLOCKED           6U
+
+#if CONFIG_WIFI_TX_PER_TRACK
+#define OFFSET_SEQNUM 8
+static void wifi_tx_pert_report(void *pbuf)
+{
+    (void)PRINTF("current PER is %d%%\r\n", wlan_le16_to_cpu(*(t_u16 *)((t_u8 *)pbuf + 8)));
+    (void)PRINTF("User configure:\r\n");
+    (void)PRINTF("       tx_pert_check_period : %d sec\r\n", mlan_adap->tx_pert.tx_pert_check_peroid);
+    (void)PRINTF("       tx_pert_check_ratio  : %d%%\r\n", mlan_adap->tx_pert.tx_pert_check_ratio);
+    (void)PRINTF("       tx_pert_check_num    : %d\r\n", mlan_adap->tx_pert.tx_pert_check_num);
+    return;
+}
+#endif
+
+int wifi_request_bgscan(mlan_private *pmpriv)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = 0;
+    cmd->result  = 0x0;
+    wlan_ops_sta_prepare_cmd(pmpriv, HostCmd_CMD_802_11_BG_SCAN_CONFIG, HostCmd_ACT_GEN_SET, 0, NULL, &pmpriv->scan_cfg,
+                             cmd);
+    wifi_wait_for_cmdresp(NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_set_rssi_low_threshold(uint8_t *low_rssi)
+{
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_ROAMING)
+    mlan_private *pmpriv = mlan_adap->priv[0];
+    mlan_ds_subscribe_evt subscribe_evt;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num                = 0;
+    cmd->result                 = 0x0;
+    subscribe_evt.evt_action    = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    subscribe_evt.evt_bitmap    = SUBSCRIBE_EVT_RSSI_LOW;
+    subscribe_evt.low_rssi      = *low_rssi;
+    subscribe_evt.low_rssi_freq = 0;
+    wlan_ops_sta_prepare_cmd(pmpriv, HostCmd_CMD_802_11_SUBSCRIBE_EVENT, HostCmd_ACT_GEN_SET, 0, NULL, &subscribe_evt,
+                             cmd);
+    wifi_wait_for_cmdresp(NULL);
+
+    if ((*low_rssi + RSSI_HYSTERESIS) <= LOWEST_RSSI_THRESHOLD)
+    {
+        *low_rssi += RSSI_HYSTERESIS;
+    }
+
+    return wm_wifi.cmd_resp_status;
+#else
+    return 0;
+#endif
+}
+
+int wifi_request_bgscan_query(mlan_private *pmpriv)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = 0;
+    cmd->result  = 0x0;
+    wlan_ops_sta_prepare_cmd(pmpriv, HostCmd_CMD_802_11_BG_SCAN_QUERY, HostCmd_ACT_GEN_GET, 0, NULL, NULL, cmd);
+    wifi_wait_for_cmdresp(NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_config_bgscan_and_rssi(const char *ssid)
+{
+    mlan_private *pmpriv = mlan_adap->priv[0];
+    int band             = 0;
+    int ret              = -WM_FAIL;
+
+    ENTER();
+
+    if (pmpriv->roaming_enabled == MFALSE)
+    {
+        wifi_d("Roaming is disabled");
+        goto done;
+    }
+
+    memset(&pmpriv->scan_cfg, 0, sizeof(pmpriv->scan_cfg));
+
+    if (wm_wifi.g_user_scan_cfg != NULL)
+    {
+        pmpriv->scan_cfg.start_later = MTRUE;
+    }
+
+    /* Fill scan config field for bg scan */
+    strncpy((char *)pmpriv->scan_cfg.ssid_list[0].ssid, (char *)ssid, MLAN_MAX_SSID_LENGTH);
+    pmpriv->scan_cfg.ssid_list[0].ssid[MLAN_MAX_SSID_LENGTH] = '\0';
+    pmpriv->scan_cfg.ssid_list[0].max_len                    = 0x00;
+    pmpriv->scan_cfg.report_condition                        = BG_SCAN_SSID_RSSI_MATCH | BG_SCAN_WAIT_ALL_CHAN_DONE;
+    pmpriv->scan_cfg.rssi_threshold                          = pmpriv->rssi_low;
+    pmpriv->scan_cfg.repeat_count                            = DEF_REPEAT_COUNT;
+    pmpriv->scan_cfg.scan_interval                           = MIN_BGSCAN_INTERVAL;
+    pmpriv->scan_cfg.chan_per_scan                           = WLAN_USER_SCAN_CHAN_MAX;
+    pmpriv->scan_cfg.num_probes                              = 2;
+#if CONFIG_SCAN_CHANNEL_GAP
+    pmpriv->scan_cfg.scan_chan_gap = SCAN_CHANNEL_GAP_VALUE;
+#endif
+
+    wifi_get_band(pmpriv, &band);
+    switch (band)
+    {
+        case WIFI_FREQUENCY_BAND_2GHZ:
+            pmpriv->scan_cfg.chan_list[0].radio_type = 0 | BAND_SPECIFIED;
+            break;
+        case WIFI_FREQUENCY_BAND_5GHZ:
+            pmpriv->scan_cfg.chan_list[0].radio_type = 1 | BAND_SPECIFIED;
+            break;
+        default:
+            PRINTM(MINFO, "Unexpected freq band \n");
+            break;
+    }
+    pmpriv->scan_cfg.bss_type = MLAN_BSS_MODE_INFRA;
+    pmpriv->scan_cfg.action   = BG_SCAN_ACT_SET;
+    pmpriv->scan_cfg.enable   = MTRUE;
+    ret                       = wifi_request_bgscan(pmpriv);
+    if (ret)
+    {
+        wifi_d("Failed to request bgscan");
+    }
+
+done:
+    LEAVE();
+
+    return ret;
+}
+
+mlan_status wifi_stop_bgscan()
+{
+    mlan_private *pmpriv = mlan_adap->priv[0];
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+
+    memset(&pmpriv->scan_cfg, 0, sizeof(pmpriv->scan_cfg));
+    pmpriv->scan_cfg.bss_type = MLAN_BSS_MODE_INFRA;
+    pmpriv->scan_cfg.action   = BG_SCAN_ACT_SET;
+    pmpriv->scan_cfg.enable   = MFALSE;
+    ret                       = (mlan_status)wifi_request_bgscan(pmpriv);
+    if (ret)
+        PRINTM(MERROR, "Failed to stop bgscan\n");
+    return ret;
+}
+
+int wifi_handle_fw_event(struct bus_message *msg)
+{
+    mlan_private *pmpriv     = (mlan_private *)mlan_adap->priv[0];
+    mlan_private *pmpriv_uap = (mlan_private *)mlan_adap->priv[1];
+#if CONFIG_WMM_UAPSD
+    t_u8 tx_lock_flag_org = 0;
+#endif
+#if CONFIG_EXT_SCAN_SUPPORT
+    mlan_status rv = MLAN_STATUS_SUCCESS;
+#endif
+
+#if CONFIG_WPA_SUPP
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.if_priv;
+#endif
+
+    Event_Ext_t *evt = ((Event_Ext_t *)msg->data);
+    t_u8 *sta_addr = NULL, *event_sta_addr = NULL;
+    wifi_ecsa_info *pecsa_info = NULL;
+    wifi_uap_client_disassoc_t *disassoc_resp;
+
+    sta_node *sta_node_ptr;
+#if CONFIG_EXT_SCAN_SUPPORT
+    mlan_event_scan_result *pext_scan_result;
+#endif
+    if (evt == NULL)
+    {
+        wevt_d("No mem allocated for msg.data");
+        return -WM_FAIL;
+    }
+
+#if !CONFIG_WIFI_PS_DEBUG
+    if ((evt->event_id != EVENT_PS_SLEEP) && (evt->event_id != EVENT_PS_AWAKE))
+    {
+        wevt_d("EVENT - : 0x%x Len : %d Reason: %d", evt->event_id, evt->length, evt->reason_code);
+    }
+#else
+    wevt_d("EVENT - : 0x%x Len : %d Reason: %d", evt->event_id, evt->length, evt->reason_code);
+#endif
+
+    if ((evt->event_id != EVENT_PS_AWAKE) && (mlan_adap->ps_state == PS_STATE_SLEEP))
+    {
+        OSA_RWLockWriteUnlock(&sleep_rwlock);
+        pmpriv->adapter->ps_state = PS_STATE_AWAKE;
+    }
+
+    switch (evt->event_id)
+    {
+        case EVENT_LINK_LOST:
+            (void)wifi_event_completion(WIFI_EVENT_LINK_LOSS, WIFI_EVENT_REASON_FAILURE,
+                                        (void *)IEEEtypes_REASON_DEAUTH_LEAVING);
+#if CONFIG_WPA_SUPP
+            wifi_if_ctx_rtos->associated = MFALSE;
+
+            wpa_supp_handle_link_lost(pmpriv);
+#else
+            /* fixme: Should this be outside CONFIG_11N ? */
+            wlan_handle_disconnect_event(pmpriv);
+#endif
+            break;
+        case EVENT_DEAUTHENTICATED:
+#if CONFIG_WPA_SUPP
+            wifi_if_ctx_rtos->associated = MFALSE;
+#endif
+            if (evt->reason_code == 0U)
+            {
+                (void)wifi_event_completion(WIFI_EVENT_LINK_LOSS, WIFI_EVENT_REASON_FAILURE,
+                                            (void *)IEEEtypes_REASON_DEAUTH_LEAVING);
+            }
+            else
+            {
+                (void)wifi_event_completion(WIFI_EVENT_AUTHENTICATION, WIFI_EVENT_REASON_FAILURE,
+                                            (void *)&evt->reason_code);
+            }
+
+            /* fixme: Should this be outside CONFIG_11N ? */
+            wlan_handle_disconnect_event(pmpriv);
+            break;
+        case EVENT_DISASSOCIATED:
+#if CONFIG_WPA_SUPP
+            wifi_if_ctx_rtos->associated = MFALSE;
+#endif
+
+#if !CONFIG_WPA_SUPP
+            (void)wifi_event_completion(WIFI_EVENT_DISASSOCIATION, WIFI_EVENT_REASON_FAILURE,
+                                        (void *)IEEEtypes_REASON_DEAUTH_LEAVING);
+#else
+            (void)wifi_event_completion(WIFI_EVENT_DISASSOCIATION, WIFI_EVENT_REASON_SUCCESS,
+                                        (void *)&evt->reason_code);
+#endif
+
+            /* fixme: Should this be outside CONFIG_11N ? */
+            wlan_handle_disconnect_event(pmpriv);
+            break;
+        case EVENT_PORT_RELEASE:
+#if !CONFIG_WPA_SUPP
+            (void)wifi_event_completion(WIFI_EVENT_AUTHENTICATION, WIFI_EVENT_REASON_SUCCESS, NULL);
+#endif
+            break;
+        case EVENT_PS_SLEEP:
+#if CONFIG_WIFI_PS_DEBUG
+            wevt_d("_");
+#endif
+            if (mlan_adap->ps_state != PS_STATE_PRE_SLEEP)
+            {
+                mlan_adap->ps_state = PS_STATE_PRE_SLEEP;
+#if CONFIG_HOST_SLEEP
+                wakelock_get();
+#endif
+                if (split_scan_in_progress == false)
+                {
+                    /* When received EVENT_PS_SLEEP, firstly send msg to wifi_powersave task
+                     * with lowest priority, then send msg to wlcmgr task. This will let all
+                     * TX data transmitted, then continue the 0xe4 cmd handshake */
+                    struct wifi_message ps_msg;
+                    ps_msg.reason = WIFI_EVENT_REASON_SUCCESS;
+                    ps_msg.event  = WIFI_EVENT_SLEEP;
+                    OSA_MsgQPut((osa_msgq_handle_t)wm_wifi.powersave_queue, &ps_msg);
+                }
+                else
+                {
+                    /** Do Nothing */
+                }
+            }
+            else
+            {
+                /* Unexpected PS SLEEP event */
+                wevt_w("Receive PS SLEEP event when presleep: %d", mlan_adap->ps_state);
+            }
+            break;
+        case EVENT_PS_AWAKE:
+#if CONFIG_WIFI_PS_DEBUG
+            wevt_d("|");
+#endif
+#if CONFIG_WMM_UAPSD
+            if (!pmpriv->adapter->pps_uapsd_mode && pmpriv->media_connected && pmpriv->adapter->sleep_period.period)
+            {
+                pmpriv->adapter->pps_uapsd_mode = MTRUE;
+                PRINTM(MEVENT, "PPS/UAPSD mode activated\n");
+            }
+
+            tx_lock_flag_org = pmpriv->adapter->tx_lock_flag;
+
+            if (pmpriv->adapter->pps_uapsd_mode)
+            {
+                OSA_SemaphorePost((osa_semaphore_handle_t)uapsd_sem);
+                /* For the continous 0xA event handling case, wifi_driver_tx task
+                 * is not allowed to send packets until the last 0xA is processed */
+                pmpriv->adapter->tx_lock_flag = MTRUE;
+                /* As the wifi_driver task has priority of 3, so sleep 1ms to yield to the CMD sending task */
+                OSA_TimeDelay(1);
+            }
+
+            /* If original tx_lock_flag is false, we don't change the tx_lock_flag to
+             * false again, to avoid sending two last packets to FW in one sleep period */
+            if (tx_lock_flag_org == MTRUE)
+            {
+                pmpriv->adapter->tx_lock_flag = MFALSE;
+            }
+
+            if (pmpriv->adapter->pps_uapsd_mode && pmpriv->media_connected && pmpriv->adapter->gen_null_pkt &&
+                wifi_check_no_packet_indication(pmpriv))
+            {
+                /* wifi_driver_tx task process the null packet sending */
+                send_wifi_driver_tx_null_data_event(MLAN_BSS_TYPE_STA);
+            }
+#endif
+            if (mlan_adap->ps_state == PS_STATE_SLEEP)
+            {
+                OSA_RWLockWriteUnlock(&sleep_rwlock);
+                mlan_adap->ps_state = PS_STATE_AWAKE;
+            }
+            else if (mlan_adap->ps_state == PS_STATE_PRE_SLEEP)
+            {
+                /* If driver did not send out sleep confirm in the expected time,
+                   FW would take it as timeout, switch to awake and send out PS AWAKE event */
+                wevt_w("Receive PS AWAKE event when presleep: %d", mlan_adap->ps_state);
+                OSA_RWLockWriteUnlock(&sleep_rwlock);
+                mlan_adap->ps_state = PS_STATE_AWAKE;
+            }
+            else
+            {
+                /*Do Nothing*/
+            }
+            break;
+#if (CONFIG_WNM_PS)
+        case EVENT_WNM_PS:
+        {
+#if !CONFIG_MEM_POOLS
+            t_u16 *wnm_action_p = (t_u16 *)OSA_MemoryAllocate(sizeof(t_u16));
+#else
+            t_u16 *wnm_action_p = (t_u16 *)OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+            if (!wnm_action_p)
+            {
+                wifi_w("No mem. Cannot process wnm ps event");
+                break;
+            }
+
+            *wnm_action_p = evt->reason_code;
+            wlan_update_wnm_ps_status((wnm_ps_result *)wnm_action_p);
+            if (wifi_event_completion(WIFI_EVENT_WNM_PS, WIFI_EVENT_REASON_SUCCESS, (void *)((t_u32)wnm_action_p)) !=
+                WM_SUCCESS)
+            {
+                /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)wnm_action_p);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, wnm_action_p);
+#endif
+            }
+        }
+        break;
+#endif
+        case EVENT_MIC_ERR_MULTICAST:
+            (void)wifi_event_completion(WIFI_EVENT_ERR_MULTICAST, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_MIC_ERR_UNICAST:
+            (void)wifi_event_completion(WIFI_EVENT_ERR_UNICAST, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_BG_SCAN_REPORT:
+            pmpriv->adapter->bgscan_reported = MTRUE;
+            pmpriv->roaming_configured       = MFALSE;
+            (void)wifi_event_completion(WIFI_EVENT_BG_SCAN_REPORT, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_BG_SCAN_STOPPED:
+            pmpriv->roaming_configured = MFALSE;
+            (void)wifi_event_completion(WIFI_EVENT_BG_SCAN_STOPPED, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+#if CONFIG_HOST_SLEEP
+        case EVENT_HS_ACT_REQ:
+            if (pmpriv->adapter->is_hs_configured == MTRUE)
+                (void)wifi_event_completion(WIFI_EVENT_HS_CONFIG, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+#endif
+#ifdef SD9177
+        case EVENT_IMD3_CAL_START:
+            wifi_d("got event: IMD3 cal started");
+            break;
+        case EVENT_IMD3_CAL_END:
+            wifi_d("got event: IMD3 cal stopped");
+            break;
+#endif
+        case EVENT_RSSI_LOW:
+            (void)wifi_event_completion(WIFI_EVENT_RSSI_LOW, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+        case EVENT_RSSI_HIGH:
+            (void)wifi_event_completion(WIFI_EVENT_RSSI_HIGH, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_SNR_LOW:
+            (void)wifi_event_completion(WIFI_EVENT_SNR_LOW, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_SNR_HIGH:
+            (void)wifi_event_completion(WIFI_EVENT_SNR_HIGH, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_MAX_FAIL:
+            (void)wifi_event_completion(WIFI_EVENT_MAX_FAIL, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_DATA_RSSI_LOW:
+            (void)wifi_event_completion(WIFI_EVENT_DATA_RSSI_LOW, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_DATA_RSSI_HIGH:
+            (void)wifi_event_completion(WIFI_EVENT_DATA_RSSI_HIGH, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_DATA_SNR_LOW:
+            (void)wifi_event_completion(WIFI_EVENT_DATA_SNR_LOW, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_DATA_SNR_HIGH:
+            (void)wifi_event_completion(WIFI_EVENT_DATA_SNR_HIGH, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_LINK_QUALITY:
+            (void)wifi_event_completion(WIFI_EVENT_FW_LINK_QUALITY, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_PRE_BEACON_LOST:
+            (void)wifi_event_completion(WIFI_EVENT_FW_PRE_BCN_LOST, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+#endif
+        case EVENT_ADDBA:
+        {
+            void *saved_event_buff = wifi_11n_save_request(evt);
+            if (saved_event_buff != NULL)
+            {
+                if (wifi_event_completion(WIFI_EVENT_11N_ADDBA, WIFI_EVENT_REASON_SUCCESS, saved_event_buff) !=
+                    WM_SUCCESS)
+                {
+                    /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                    OSA_MemoryFree((void *)saved_event_buff);
+#else
+                    OSA_MemoryPoolFree(buf_256_MemoryPool, saved_event_buff);
+#endif
+                }
+            }
+            /* If allocation failed ignore this event quietly ! */
+        }
+        break;
+        case EVENT_DELBA:
+        {
+            wlan_11n_delete_bastream((mlan_private *)mlan_adap->priv[evt->bss_type], (t_u8 *)&evt->reason_code);
+        }
+        break;
+        case EVENT_BA_STREAM_TIMEOUT:
+        {
+            void *saved_event_buff = wifi_11n_save_request(evt);
+            if (saved_event_buff != NULL)
+            {
+                if (wifi_event_completion(WIFI_EVENT_11N_BA_STREAM_TIMEOUT, WIFI_EVENT_REASON_SUCCESS,
+                                          saved_event_buff) != WM_SUCCESS)
+                {
+                    /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                    OSA_MemoryFree((void *)saved_event_buff);
+#else
+                    OSA_MemoryPoolFree(buf_256_MemoryPool, saved_event_buff);
+#endif
+                }
+            }
+            /* If allocation failed ignore this event quietly ! */
+        }
+        break;
+        case EVENT_AMSDU_AGGR_CTRL:
+            /*
+             * Currently this event buffer isn't being used. Enable
+             * this when required.
+             */
+            /* wifi_11n_save_request(evt); */
+            (void)wifi_event_completion(WIFI_EVENT_11N_AGGR_CTRL, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_CHANNEL_SWITCH_ANN:
+            (void)wifi_event_completion(WIFI_EVENT_CHAN_SWITCH_ANN, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case EVENT_CHANNEL_SWITCH:
+        {
+#if !CONFIG_MEM_POOLS
+            pecsa_info = OSA_MemoryAllocate(sizeof(wifi_ecsa_info));
+#else
+            pecsa_info = OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+            if (!pecsa_info)
+            {
+                wifi_w("No mem. Cannot process new channel from channel switch");
+                break;
+            }
+
+            MrvlIEtypes_channel_band_t *tlv = (MrvlIEtypes_channel_band_t *)&evt->reason_code;
+
+            pecsa_info->bss_type    = evt->bss_type;
+            pecsa_info->band_config = tlv->band_config;
+            pecsa_info->channel     = tlv->channel;
+
+            if (wifi_event_completion(WIFI_EVENT_CHAN_SWITCH, WIFI_EVENT_REASON_SUCCESS, pecsa_info) != WM_SUCCESS)
+            {
+                /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)pecsa_info);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, pecsa_info);
+#endif
+            }
+        }
+        break;
+        case EVENT_MICRO_AP_STA_ASSOC:
+        {
+            /*
+             * Alloc memory to store the STA mac id. This will be
+             * passed to event receiver thread. Freeing this is
+             * responsibility of the receiving thread.
+             */
+#if !CONFIG_MEM_POOLS
+            sta_addr = OSA_MemoryAllocate(MLAN_MAC_ADDR_LENGTH);
+#else
+            sta_addr = OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+            if (sta_addr == MNULL)
+            {
+                wifi_w("No mem. Cannot process MAC address from assoc");
+                break;
+            }
+
+            event_sta_addr = (t_u8 *)&evt->src_mac_addr;
+            (void)memcpy((void *)sta_addr, (const void *)event_sta_addr, MLAN_MAC_ADDR_LENGTH);
+
+            wlan_request_ralist_lock(mlan_adap->priv[1]);
+            /* Clear corresponding tx/rx table if necessary */
+            if (wlan_11n_get_txbastream_tbl((mlan_private *)mlan_adap->priv[1], sta_addr))
+                wlan_11n_delete_txbastream_tbl_entry((mlan_private *)mlan_adap->priv[1], sta_addr);
+
+            wlan_cleanup_reorder_tbl((mlan_private *)mlan_adap->priv[1], sta_addr);
+#if CONFIG_WMM
+            wlan_ralist_del_enh(mlan_adap->priv[1], sta_addr);
+#endif
+            /* txbastream table also is used as connected STAs data base */
+            wlan_11n_create_txbastream_tbl((mlan_private *)mlan_adap->priv[1], sta_addr, BA_STREAM_NOT_SETUP);
+            wlan_11n_update_txbastream_tbl_tx_thresh((mlan_private *)mlan_adap->priv[1], sta_addr, 3);
+
+#if !CONFIG_MEM_POOLS
+            sta_node_ptr = OSA_MemoryAllocate(sizeof(sta_node));
+#else
+            sta_node_ptr = OSA_MemoryPoolAllocate(buf_256_MemoryPool);
+#endif
+            if (sta_node_ptr == MNULL)
+            {
+                wifi_w("No mem. Cannot check station type");
+                wlan_release_ralist_lock(mlan_adap->priv[1]);
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree(sta_addr);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, sta_addr);
+#endif
+                break;
+            }
+            memset(sta_node_ptr, 0x00, sizeof(sta_node));
+
+            wrapper_wlan_check_sta_capability((mlan_private *)mlan_adap->priv[1], msg->data, sta_node_ptr);
+
+            if (sta_node_ptr->is_11n_enabled)
+            {
+                wlan_11n_update_txbastream_tbl_ampdu_supported((mlan_private *)mlan_adap->priv[1], sta_addr, MTRUE);
+            }
+
+            wlan_release_ralist_lock(mlan_adap->priv[1]);
+
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(sta_node_ptr);
+#else
+            OSA_MemoryPoolFree(buf_256_MemoryPool, sta_node_ptr);
+#endif
+
+
+#if CONFIG_WMM
+            wlan_ralist_add_enh(mlan_adap->priv[1], sta_addr);
+#endif
+
+            if (wifi_event_completion(WIFI_EVENT_UAP_CLIENT_ASSOC, WIFI_EVENT_REASON_SUCCESS, sta_addr) != WM_SUCCESS)
+            {
+                /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)sta_addr);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, sta_addr);
+#endif
+            }
+        }
+        break;
+        case EVENT_MICRO_AP_RSN_CONNECT:
+        {
+            /*
+             * Alloc memory to store the STA mac id. This will be
+             * passed to event receiver thread. Freeing this is
+             * responsibility of the receiving thread.
+             */
+#if !CONFIG_MEM_POOLS
+            sta_addr = OSA_MemoryAllocate(MLAN_MAC_ADDR_LENGTH);
+#else
+            sta_addr = OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+            if (sta_addr == MNULL)
+            {
+                wifi_w("No mem. Cannot process MAC address from conn");
+                break;
+            }
+
+            event_sta_addr = (t_u8 *)&evt->src_mac_addr;
+            (void)memcpy((void *)sta_addr, (const void *)event_sta_addr, MLAN_MAC_ADDR_LENGTH);
+            if (wifi_event_completion(WIFI_EVENT_UAP_CLIENT_CONN, WIFI_EVENT_REASON_SUCCESS, sta_addr) != WM_SUCCESS)
+            {
+                /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)sta_addr);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, sta_addr);
+#endif
+            }
+        }
+        break;
+        case EVENT_MICRO_AP_STA_DEAUTH:
+            /*
+             * Alloc memory to store the STA mac id. This will be
+             * passed to event receiver thread. Freeing this is
+             * responsibility of the receiving thread.
+             */
+#if !CONFIG_MEM_POOLS
+            disassoc_resp = OSA_MemoryAllocate(sizeof(wifi_uap_client_disassoc_t));
+#else
+            disassoc_resp = OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+            if (disassoc_resp == MNULL)
+            {
+                wifi_w("No mem. Cannot add mac and reason code for deauth event to app");
+                break;
+            }
+            sta_addr                   = disassoc_resp->sta_addr;
+            disassoc_resp->reason_code = (int)evt->reason_code;
+
+            event_sta_addr = (t_u8 *)&evt->src_mac_addr;
+            (void)memcpy((void *)sta_addr, (const void *)event_sta_addr, MLAN_MAC_ADDR_LENGTH);
+
+            if (pmpriv_uap->is_11n_enabled)
+            {
+                wlan_cleanup_reorder_tbl(pmpriv_uap, sta_addr);
+                wlan_request_ralist_lock(pmpriv_uap);
+                wlan_11n_delete_txbastream_tbl_entry(pmpriv_uap, sta_addr);
+                wlan_release_ralist_lock(pmpriv_uap);
+            }
+
+            wlan_delete_station_entry(pmpriv_uap, sta_addr);
+
+#ifdef CONFIG_WPA_SUPP_AP
+            /* BIT 14 indicate deauth is initiated by FW */
+            if (disassoc_resp->reason_code & MBIT(14))
+            {
+                if (disassoc_resp->reason_code & MBIT(1))
+                {
+                    t_u16 reason_code = IEEEtypes_REASON_DISASSOC_DUE_TO_INACTIVITY;
+                    wifi_nxp_uap_disconnect(pmpriv_uap, reason_code, sta_addr);
+                }
+                else
+                {
+                    wifi_nxp_uap_disconnect(pmpriv_uap, 0, sta_addr);
+                }
+            }
+#endif
+
+            if (wifi_event_completion(WIFI_EVENT_UAP_CLIENT_DEAUTH, WIFI_EVENT_REASON_SUCCESS, disassoc_resp) !=
+                WM_SUCCESS)
+            {
+                /* If fail to send message on queue, free allocated memory ! */
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)disassoc_resp);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, disassoc_resp);
+#endif
+            }
+#if CONFIG_WMM
+            wlan_ralist_del_enh(mlan_adap->priv[1], evt->src_mac_addr);
+#endif
+            if (evt->reason_code == AP_DEAUTH_REASON_MAC_ADDR_BLOCKED)
+            {
+                wevt_d("EVENT: Blacklist sta %02x:%02x:%02x:%02x:%02x:%02x: try to join the network \r\n",
+                       evt->src_mac_addr[0], evt->src_mac_addr[1], evt->src_mac_addr[2], evt->src_mac_addr[3],
+                       evt->src_mac_addr[4], evt->src_mac_addr[5]);
+            }
+            break;
+        case EVENT_MICRO_AP_BSS_START:
+            wifi_d("uAP start event received");
+            /*
+             * wmsdk: statement copied from
+             * mlan_uap_cmdevent.c. Necessary for other uAP functions.
+             */
+            wrapper_wlan_check_uap_capability((mlan_private *)mlan_adap->priv[1], msg->data);
+            pmpriv_uap->uap_bss_started = MTRUE;
+            /* set uap mac addr */
+            (void)memcpy((void *)pmpriv_uap->curr_addr, (const void *)evt->src_mac_addr, (size_t)MLAN_MAC_ADDR_LENGTH);
+            break;
+        case EVENT_MICRO_AP_BSS_ACTIVE:
+            PRINTM(MEVENT, "EVENT: MICRO_AP_BSS_ACTIVE\n");
+            pmpriv_uap->media_connected = MTRUE;
+            break;
+        case EVENT_MICRO_AP_BSS_IDLE:
+            PRINTM(MEVENT, "EVENT: MICRO_AP_BSS_IDLE\n");
+            pmpriv_uap->media_connected = MFALSE;
+            wlan_clean_txrx(pmpriv_uap);
+            wlan_delete_station_list(pmpriv_uap);
+            break;
+#if CONFIG_WMM
+        case EVENT_TX_DATA_PAUSE:
+            wifi_handle_event_data_pause(evt);
+            break;
+#endif
+#if CONFIG_WIFI_TX_PER_TRACK
+        case EVENT_PER_STATUS_REPORT:
+            PRINTM(MEVENT, "EVENT: PER_STATUS_REPORT\n");
+            wifi_tx_pert_report((void *)evt);
+            break;
+#endif
+        case EVENT_TX_STATUS_REPORT:
+            wifi_handle_event_tx_status_report(evt);
+            break;
+        case EVENT_BLOCKEDSTA_AUTH_REPORT:
+            wifi_handle_blocked_sta_report(evt);
+            break;
+#if CONFIG_EXT_SCAN_SUPPORT
+        case EVENT_EXT_SCAN_REPORT:
+            pext_scan_result = (mlan_event_scan_result *)((t_u8 *)msg->data + 4);
+
+            rv = wlan_handle_event_ext_scan_report(pmpriv, (t_u8 *)pext_scan_result);
+
+            if (rv != MLAN_STATUS_SUCCESS)
+            {
+                wifi_user_scan_config_cleanup();
+                return -WM_FAIL;
+            }
+#ifndef SD8801
+            if (is_split_scan_complete() && !pext_scan_result->more_event)
+            {
+                wifi_d("Split scan complete");
+                wifi_user_scan_config_cleanup();
+                wifi_event_completion(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_SUCCESS, NULL);
+            }
+#endif
+            break;
+#endif
+#if CONFIG_WIFI_FW_DEBUG
+        case EVENT_FW_DEBUG_INFO:
+        {
+#if !CONFIG_MEM_POOLS
+            t_u8 *debug = (t_u8 *)OSA_MemoryAllocate(FW_DEBUG_INFO_SIZE);
+#else
+            t_u8 *debug = (t_u8 *)OSA_MemoryPoolAllocate(buf_512_MemoryPool);
+#endif
+            if (!debug)
+            {
+                wifi_w("No mem. Cannot print debug event");
+                break;
+            }
+
+            (void)memcpy((void *)debug, (const void *)((uint8_t *)&evt->reason_code), evt->length - 8);
+            (void)PRINTF("EVENT: FW Debug Info %s\r\n", debug);
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)debug);
+#else
+            OSA_MemoryPoolFree(buf_512_MemoryPool, debug);
+#endif
+        }
+        break;
+#endif
+#if (CONFIG_CSI) || (((CONFIG_11AZ) || (CONFIG_11MC)))
+        case EVENT_CSI:
+        {
+            PRINTM(MEVENT, "EVENT: EVENT_CSI\n");
+#if CONFIG_CSI
+            csi_deliver_data_to_user();
+#endif
+#if (CONFIG_11AZ) || (CONFIG_11MC)
+#if CONFIG_WLS_CSI_PROC
+            // wifi_get_wls_csi_sem(); // Get wls csi sem to prevent CSI event raw data from being overwritten before
+            //  processing.
+            if (g_csi_event_for_wls)
+            {
+                memcpy(wls_data, (t_u8 *)msg->data, WLS_CSI_DATA_LEN);
+                wifi_event_completion(WIFI_EVENT_WLS_CSI, WIFI_EVENT_REASON_SUCCESS, wls_data);
+            }
+#endif
+#endif
+        }
+        break;
+#endif
+        case EVENT_MEF_HOST_WAKEUP:
+            wifi_d("Host recevied host wake-up event from firmware");
+            break;
+#if CONFIG_MULTI_CHAN
+        case EVENT_MULTI_CHAN_INFO:
+            break;
+#endif
+#if CONFIG_WPA_SUPP
+        case EVENT_ASSOC_REQ_IE:
+#if CONFIG_AUTO_RECONNECT
+            if (pmpriv->media_connected == MTRUE)
+            {
+                wifi_event_completion(WIFI_EVENT_ASSOCIATION_NOTIFY, WIFI_EVENT_REASON_SUCCESS, NULL);
+            }
+#endif
+            pmpriv->assoc_req_size = evt->length - 8;
+            (void)memcpy((void *)pmpriv->assoc_req_buf, (const void *)((uint8_t *)&evt->reason_code),
+                         pmpriv->assoc_req_size);
+            break;
+#endif
+#if CONFIG_5GHz_SUPPORT
+        case EVENT_RADAR_DETECTED:
+            wevt_d("EVENT:RADAR_DETECTED -> detect_count=%d, reg_domain=%d, det_type=%d(%s)\n",
+                   wlan_le32_to_cpu(((Event_Radar_Detected_Info *)msg->data)->detect_count),
+                   ((Event_Radar_Detected_Info *)msg->data)->reg_domain,
+                   ((Event_Radar_Detected_Info *)msg->data)->main_det_type,
+                   (((Event_Radar_Detected_Info *)msg->data)->main_det_type == 2) ? "PRI" :
+                   (((Event_Radar_Detected_Info *)msg->data)->main_det_type == 1) ? "PW" :
+                                                                                    "");
+
+            break;
+#endif
+#if CONFIG_CLOUD_KEEP_ALIVE
+        case EVENT_CLOUD_KEEP_ALIVE_RETRY_FAIL:
+            wevt_d("EVENT: EVENT_CLOUD_KEEP_ALIVE_RETRY_FAIL received\n\r");
+            break;
+#endif
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+        case EVENT_WLS_FTM_COMPLETE:
+            wifi_ftm_process_event(msg->data);
+            break;
+#endif
+        case EVENT_ACCESS_BY_HOST:
+            break;
+        case EVENT_REMAIN_ON_CHANNEL_EXPIRED:
+            mlan_adap->remain_on_channel = MFALSE;
+            /* Restore tx after remain on channel expired */
+            wifi_set_tx_status(WIFI_DATA_RUNNING);
+
+#if CONFIG_WMM
+            send_wifi_driver_tx_data_event(MLAN_BSS_TYPE_STA);
+            send_wifi_driver_tx_data_event(MLAN_BSS_TYPE_UAP);
+#endif
+            break;
+        default:
+            wifi_d("Event 0x%x not implemented", evt->event_id);
+            break;
+    }
+
+    return WM_SUCCESS;
+}
+
+static void process_rsn_ie(t_u8 *rsn_ie,
+                           _Cipher_t *mcstCipher,
+                           _Cipher_t *ucstCipher,
+                           t_u8 *ap_mfpc,
+                           t_u8 *ap_mfpr,
+                           _SecurityMode_t *WPA_WPA2_WEP)
+{
+    t_u8 *temp;
+    t_u16 count;
+    t_u16 group_cipher_count    = 0;
+    t_u16 pairwise_cipher_count = 0;
+    t_u16 akm_suite_count       = 0;
+    t_u16 rsn_cap               = 0;
+    t_u8 wpa2_oui01[4]          = {0x00, 0x0f, 0xac, 0x01};
+    t_u8 wpa2_oui02[4]          = {0x00, 0x0f, 0xac, 0x02};
+    t_u8 wpa2_oui04[4]          = {0x00, 0x0f, 0xac, 0x04};
+    t_u8 wpa2_oui05[4]          = {0x00, 0x0f, 0xac, 0x05};
+    t_u8 wpa2_oui06[4]          = {0x00, 0x0f, 0xac, 0x06};
+
+    t_u8 wpa3_oui08[4] = {0x00, 0x0f, 0xac, 0x08};
+    t_u8 wpa3_oui0b[4] = {0x00, 0x0f, 0xac, 0x0b};
+    t_u8 wpa3_oui0c[4] = {0x00, 0x0f, 0xac, 0x0c};
+#if CONFIG_DRIVER_OWE
+    t_u8 wpa3_oui12[4] = {0x00, 0x0f, 0xac, 0x12};
+#endif
+#if CONFIG_11R
+    t_u8 rsn_ft_1x_oui[4]  = {0x00, 0x0f, 0xac, 0x03};
+    t_u8 rsn_ft_psk_oui[4] = {0x00, 0x0f, 0xac, 0x04};
+    t_u8 rsn_ft_sae_oui[4] = {0x00, 0x0f, 0xac, 0x09};
+    t_u8 wpa3_oui0d[4]     = {0x00, 0x0f, 0xac, 0x0d};
+#endif
+
+    ENTER();
+
+    if (rsn_ie == MNULL)
+    {
+        goto done;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    if (rsn_ie[0] != (t_u8)RSN_IE)
+    {
+        goto done;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+    /*  2 bytes header + 2 bytes version + 4 bytes group_cipher_suite +
+     *  2 bytes pairwise_cipher_count + pairwise_cipher_count *
+     * PAIRWISE_CIPHER_SUITE_LEN (4) + 2 bytes akm_suite_count +
+     * akm_suite_count * AKM_SUITE_LEN (4)
+     */
+    count              = *(t_u16 *)(void *)(rsn_ie + 2);
+    count              = wlan_le16_to_cpu(count);
+    group_cipher_count = count;
+    temp               = (t_u8 *)(rsn_ie + 2 + sizeof(t_u16));
+
+    while (count > 0U)
+    {
+        if (!memcmp(temp, (const void *)wpa2_oui04, sizeof(wpa2_oui04)))
+        {
+            mcstCipher->ccmp = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa2_oui02, sizeof(wpa2_oui02)))
+        {
+            mcstCipher->tkip = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa2_oui05, sizeof(wpa2_oui05)))
+        {
+            mcstCipher->wep104 = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa2_oui01, sizeof(wpa2_oui01)))
+        {
+            mcstCipher->wep40 = true;
+        }
+        else
+        { /* Do nothing */
+        }
+        count--;
+        temp += 4;
+    }
+
+    count                 = *(t_u16 *)(void *)(rsn_ie + 2 + sizeof(t_u16) + (int)group_cipher_count * 4);
+    count                 = wlan_le16_to_cpu(count);
+    pairwise_cipher_count = count;
+
+    temp = (t_u8 *)(rsn_ie + 2 + sizeof(t_u16) + (int)group_cipher_count * 4 + (int)sizeof(t_u16));
+
+    while (count > 0U)
+    {
+        if (!memcmp(temp, (const void *)wpa2_oui04, sizeof(wpa2_oui04)))
+        {
+            ucstCipher->ccmp = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa2_oui02, sizeof(wpa2_oui02)))
+        {
+            ucstCipher->tkip = true;
+        }
+        else
+        { /* Do Nothing */
+        }
+        count--;
+        temp += 4;
+    }
+
+    count           = *(t_u16 *)(void *)(rsn_ie + 2 + sizeof(t_u16) + (int)group_cipher_count * 4 + (int)sizeof(t_u16) +
+                               (int)pairwise_cipher_count * 4);
+    count           = wlan_le16_to_cpu(count);
+    akm_suite_count = count;
+
+    temp = (t_u8 *)(rsn_ie + 2 + sizeof(t_u16) + (int)group_cipher_count * 4 + (int)sizeof(t_u16) +
+                    (int)pairwise_cipher_count * 4 + (int)sizeof(t_u16));
+
+    while (count > 0U)
+    {
+        if (memcmp(temp, wpa3_oui08, sizeof(wpa3_oui08)) == 0)
+        {
+            WPA_WPA2_WEP->wpa3_sae = 1;
+        }
+        else if (memcmp(temp, wpa3_oui0b, sizeof(wpa3_oui0b)) == 0)
+        {
+            WPA_WPA2_WEP->wpa3_1x_sha256 = 1;
+        }
+        else if (memcmp(temp, wpa3_oui0c, sizeof(wpa3_oui0c)) == 0)
+        {
+            WPA_WPA2_WEP->wpa3_1x_sha384 = 1;
+        }
+#if CONFIG_DRIVER_OWE
+        else if (memcmp(temp, wpa3_oui12, sizeof(wpa3_oui12)) == 0)
+        {
+            WPA_WPA2_WEP->owe = 1;
+        }
+#endif
+        else if (memcmp(temp, wpa2_oui01, sizeof(wpa2_oui01)) == 0)
+        {
+            WPA_WPA2_WEP->wpa2_entp = 1;
+        }
+        else if (memcmp(temp, wpa2_oui02, sizeof(wpa2_oui02)) == 0)
+        {
+            WPA_WPA2_WEP->wpa2 = 1;
+        }
+        else if (memcmp(temp, wpa2_oui05, sizeof(wpa2_oui05)) == 0)
+        {
+            WPA_WPA2_WEP->wpa2_entp_sha256 = 1;
+        }
+        else if (memcmp(temp, wpa2_oui06, sizeof(wpa2_oui06)) == 0)
+        {
+            WPA_WPA2_WEP->wpa2_sha256 = 1;
+        }
+
+#if CONFIG_11R
+        else if (memcmp(temp, rsn_ft_1x_oui, sizeof(rsn_ft_1x_oui)) == 0)
+        {
+            WPA_WPA2_WEP->ft_1x = 1;
+            WPA_WPA2_WEP->wpa2  = 1;
+        }
+        else if (memcmp(temp, wpa3_oui0d, sizeof(wpa3_oui0d)) == 0)
+        {
+            WPA_WPA2_WEP->ft_1x_sha384 = 1;
+        }
+        else if (memcmp(temp, rsn_ft_psk_oui, sizeof(rsn_ft_psk_oui)) == 0)
+        {
+            WPA_WPA2_WEP->ft_psk = 1;
+            WPA_WPA2_WEP->wpa2   = 1;
+        }
+        else if (memcmp(temp, rsn_ft_sae_oui, sizeof(rsn_ft_sae_oui)) == 0)
+        {
+            WPA_WPA2_WEP->ft_sae   = 1;
+            WPA_WPA2_WEP->wpa3_sae = 1;
+        }
+#endif
+        else
+        { /* Do Nothing */
+        }
+        temp += 4;
+        count--;
+    }
+
+    rsn_cap = *(t_u16 *)(void *)(rsn_ie + 2 + sizeof(t_u16) + 4 * (int)sizeof(t_u8) + (int)sizeof(t_u16) +
+                                 (int)pairwise_cipher_count * 4 + (int)sizeof(t_u16) + (int)akm_suite_count * 4);
+    rsn_cap = (t_u16)wlan_le16_to_cpu(rsn_cap);
+
+    *ap_mfpc = ((rsn_cap & (0x1 << MFPC_BIT)) == (0x1 << MFPC_BIT));
+    *ap_mfpr = ((rsn_cap & (0x1 << MFPR_BIT)) == (0x1 << MFPR_BIT));
+done:
+    LEAVE();
+}
+
+static void process_wpa_ie(t_u8 *wpa_ie,
+                           _Cipher_t *mcstCipher,
+                           _Cipher_t *ucstCipher,
+                           t_u8 *ap_mfpc,
+                           t_u8 *ap_mfpr,
+                           _SecurityMode_t *WPA_WPA2_WEP)
+{
+    t_u16 wpa_ie_len;
+    t_u8 *temp;
+    t_u8 *ptr;
+    t_u8 *wpa_ie_len_ptr;
+    t_u8 *pairwise_cipher_count_ptr;
+    t_u16 count;
+    t_u16 group_cipher_count    = 0;
+    t_u16 pairwise_cipher_count = 0;
+    t_u8 wpa_oui01[4]           = {0x00, 0x50, 0xf2, 0x01};
+    t_u8 wpa_oui02[4]           = {0x00, 0x50, 0xf2, 0x02};
+    t_u8 wpa_oui04[4]           = {0x00, 0x50, 0xf2, 0x04};
+    t_u8 wpa_oui05[4]           = {0x00, 0x50, 0xf2, 0x05};
+
+    ENTER();
+
+    if (wpa_ie == MNULL)
+    {
+        goto done;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    if (wpa_ie[0] != (t_u8)WPA_IE)
+    {
+        goto done;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+    /*  2 bytes header + 4 bytes oui + 2 bytes version + 4 bytes group_cipher_suite +
+     *  2 bytes pairwise_cipher_count + pairwise_cipher_count *
+     * PAIRWISE_CIPHER_SUITE_LEN (4) + 2 bytes akm_suite_count +
+     * akm_suite_count * AKM_SUITE_LEN (4)
+     */
+    ptr            = (t_u8 *)(wpa_ie + 1);
+    wpa_ie_len_ptr = ptr;
+
+    wpa_ie_len = wlan_le16_to_cpu(*(t_u16 *)ptr);
+
+    count              = *(t_u16 *)(void *)(wpa_ie + 2 + 4);
+    count              = wlan_le16_to_cpu(count);
+    group_cipher_count = count;
+    temp               = (t_u8 *)(wpa_ie + 2 + 4 + sizeof(t_u16));
+
+    while (count > 0U)
+    {
+        if (!memcmp(temp, (const void *)wpa_oui04, sizeof(wpa_oui04)))
+        {
+            mcstCipher->ccmp = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa_oui02, sizeof(wpa_oui02)))
+        {
+            mcstCipher->tkip = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa_oui05, sizeof(wpa_oui05)))
+        {
+            mcstCipher->wep104 = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa_oui01, sizeof(wpa_oui01)))
+        {
+            mcstCipher->wep40 = true;
+        }
+        else
+        { /* Do nothing */
+        }
+        count--;
+        temp += 4;
+    }
+
+    ptr                       = (t_u8 *)(wpa_ie + 2 + 4 + sizeof(t_u16) + (int)group_cipher_count * 4);
+    pairwise_cipher_count_ptr = ptr;
+
+    count                 = *(t_u16 *)(void *)ptr;
+    count                 = wlan_le16_to_cpu(count);
+    pairwise_cipher_count = count;
+    temp                  = (t_u8 *)(wpa_ie + 2 + 4 + sizeof(t_u16) + (int)group_cipher_count * 4 + (int)sizeof(t_u16));
+
+    while (count > 0U)
+    {
+        if (!memcmp(temp, (const void *)wpa_oui04, sizeof(wpa_oui04)))
+        {
+            ucstCipher->ccmp = true;
+        }
+        else if (!memcmp(temp, (const void *)wpa_oui02, sizeof(wpa_oui02)))
+        {
+            ucstCipher->tkip = true;
+        }
+        else
+        { /* Do Nothing */
+        }
+        count--;
+        temp += 4;
+    }
+
+    if (pairwise_cipher_count == 2)
+    {
+        ptr           = wpa_ie_len_ptr;
+        *(t_u16 *)ptr = wlan_cpu_to_le16(wpa_ie_len - 4);
+        ptr           = pairwise_cipher_count_ptr;
+        *(t_u16 *)ptr = wlan_cpu_to_le16(1);
+        temp          = (t_u8 *)(wpa_ie + 2 + 4 + sizeof(t_u16) + (int)group_cipher_count * 4 + (int)sizeof(t_u16));
+
+        if (!memcmp((temp + 4), (const void *)wpa_oui04, sizeof(wpa_oui04)))
+        {
+            memmove(temp, (temp + 4), (4 + sizeof(t_u16) + 4));
+        }
+        else
+        {
+            /* 2 bytes header + 4 bytes oui + 2 bytes version + 4 bytes group_cipher_suite +
+             *  2 bytes pairwise_cipher_count + pairwise_cipher_1 (4) +
+             *  pairwise_cipher_2 (4) + 2 bytes akm_suite_count +
+             *  akm_suite_count * AKM_SUITE_LEN (4)
+             *
+             *  Here move memory of 4bytes(pairwise_cipher_2) if the cipher type is not wpa_oui04,
+             *  dest = (temp + 4) and src = (temp + 8),
+             *  this memmove will keep akm data intact */
+            memmove((temp + 4), (temp + 8), (sizeof(t_u16) + 4));
+        }
+    }
+done:
+    LEAVE();
+}
+
+int wrapper_bssdesc_first_set(int bss_index,
+                              uint8_t *BssId,
+                              bool *is_ibss_bit_set,
+                              int *ssid_len,
+                              uint8_t *ssid,
+                              uint8_t *Channel,
+                              uint8_t *RSSI,
+                              uint16_t *beacon_period,
+                              uint16_t *dtim_period,
+                              _SecurityMode_t *WPA_WPA2_WEP,
+                              _Cipher_t *wpa_mcstCipher,
+                              _Cipher_t *wpa_ucstCipher,
+                              _Cipher_t *rsn_mcstCipher,
+                              _Cipher_t *rsn_ucstCipher,
+                              t_u8 *ap_mfpc,
+                              t_u8 *ap_mfpr,
+                              t_u8 *ap_pwe)
+{
+    uint8_t i = WLAN_SUPPORTED_RATES;
+    if (bss_index >= (int)mlan_adap->num_in_scan_table)
+    {
+        wifi_w("Unable to find given entry %d in BSS table", bss_index);
+        return -WM_FAIL;
+    }
+
+    /* TODO
+     * Removed : const BSSDescriptor_t *d = &mlan_adap->pscan_table[bss_index]; */
+    BSSDescriptor_t *d = &mlan_adap->pscan_table[bss_index];
+
+    (void)memcpy((void *)BssId, (const void *)d->mac_address, MLAN_MAC_ADDR_LENGTH);
+
+    if (d->cap_info.ibss != 0U)
+    {
+        *is_ibss_bit_set = true;
+    }
+    else
+    {
+        *is_ibss_bit_set = false;
+    }
+
+    if (d->ssid.ssid_len <= MLAN_MAX_SSID_LENGTH)
+    {
+        *ssid_len = (int)d->ssid.ssid_len;
+        (void)memcpy((void *)ssid, (const void *)d->ssid.ssid, d->ssid.ssid_len);
+    }
+
+    *Channel = d->channel; /*!< Channel associated to the BSSID */
+
+    *RSSI = (uint8_t)d->rssi;
+    /* uint8_t RSSI; */ /*!< Received signal strength */
+    *beacon_period = d->beacon_period;
+    *dtim_period   = d->dtim_period;
+
+    if (d->pwpa_ie != MNULL || d->prsn_ie != MNULL)
+    {
+        if (d->pwpa_ie != MNULL)
+        {
+            WPA_WPA2_WEP->wpa = 1;
+
+            process_wpa_ie(d->wpa_ie_buff, wpa_mcstCipher, wpa_ucstCipher, ap_mfpc, ap_mfpr, WPA_WPA2_WEP);
+        }
+
+        if (d->prsn_ie != MNULL)
+        {
+            process_rsn_ie(d->rsn_ie_buff, rsn_mcstCipher, rsn_ucstCipher, ap_mfpc, ap_mfpr, WPA_WPA2_WEP);
+        }
+    }
+    else
+    {
+        /* Check if WEP */
+        if (d->cap_info.privacy != 0U)
+        {
+            WPA_WPA2_WEP->wepStatic = 1;
+        }
+    }
+
+    if ((d->prsnx_ie != MNULL) && (d->prsnx_ie->data[0] & (0x1 << SAE_H2E_BIT)))
+    {
+        *ap_pwe = 2;
+        for (i = WLAN_SUPPORTED_RATES; i > 0; i--)
+        {
+            if (d->data_rates[i - 1] == 0xFB)
+            {
+                *ap_pwe = 1;
+                break;
+            }
+        }
+    }
+    else
+    {
+        *ap_pwe = 0;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wrapper_bssdesc_second_set(int bss_index,
+                               bool *phtcap_ie_present,
+                               bool *phtinfo_ie_present,
+#if CONFIG_11AC
+                               bool *pvhtcap_ie_present,
+#endif
+#if CONFIG_11AX
+                               bool *phecap_ie_present,
+#endif
+                               bool *wmm_ie_present,
+                               uint16_t *band,
+                               bool *wps_IE_exist,
+                               uint16_t *wps_session,
+                               bool *wpa2_entp_IE_exist,
+#if CONFIG_11R
+                               uint16_t *mdid,
+#endif
+#if CONFIG_11K
+                               bool *neighbor_report_supported,
+#endif
+#if CONFIG_11V
+                               bool *bss_transition_supported,
+#endif
+                               uint8_t *trans_mode,
+                               uint8_t *trans_bssid,
+                               int *trans_ssid_len,
+                               uint8_t *trans_ssid
+#if CONFIG_DRIVER_MBO
+                               ,
+                               bool *mbo_assoc_disallowed
+#endif
+)
+{
+    if (bss_index >= mlan_adap->num_in_scan_table)
+    {
+        wifi_w("Unable to find given entry %d in BSS table", bss_index);
+        return -WM_FAIL;
+    }
+    const BSSDescriptor_t *d = &mlan_adap->pscan_table[bss_index];
+#if CONFIG_11R
+    IEEEtypes_MobilityDomain_t *pmd_ie;
+#endif
+
+    if (d->pht_cap != NULL)
+    {
+        *phtcap_ie_present = true;
+    }
+    else
+    {
+        *phtcap_ie_present = false;
+    }
+
+    if (d->pht_info != NULL)
+    {
+        *phtinfo_ie_present = true;
+    }
+    else
+    {
+        *phtinfo_ie_present = false;
+    }
+#if CONFIG_11AC
+    if (d->pvht_cap != NULL)
+    {
+        *pvhtcap_ie_present = true;
+    }
+    else
+    {
+        *pvhtcap_ie_present = false;
+    }
+#endif
+#if CONFIG_11AX
+    if (d->phe_cap != NULL)
+    {
+        *phecap_ie_present = true;
+    }
+    else
+    {
+        *phecap_ie_present = false;
+    }
+#endif
+    if (d->wmm_ie.vend_hdr.element_id == WMM_IE)
+    {
+        *wmm_ie_present = true;
+    }
+    else
+    {
+        *wmm_ie_present = false;
+    }
+
+#if CONFIG_DRIVER_MBO
+    *mbo_assoc_disallowed = d->mbo_assoc_disallowed;
+#endif
+
+    *band = d->bss_band;
+
+    if (wps_IE_exist != NULL)
+    {
+        *wps_IE_exist = d->wps_IE_exist;
+    }
+    if (wps_session != NULL)
+    {
+        *wps_session = d->wps_session;
+    }
+
+    if (wpa2_entp_IE_exist != NULL)
+    {
+        *wpa2_entp_IE_exist = d->wpa2_entp_IE_exist;
+    }
+
+#if CONFIG_11R
+    if (mdid != NULL)
+    {
+        pmd_ie = (IEEEtypes_MobilityDomain_t *)d->md_ie_buff;
+        *mdid  = pmd_ie->mdid;
+    }
+#endif
+#if CONFIG_11K
+    if (neighbor_report_supported != NULL)
+    {
+        *neighbor_report_supported = (bool)d->rm_cap_saved.RrmEnabledCapabilities.NborRpt;
+    }
+#endif
+#if CONFIG_11V
+    if (bss_transition_supported != NULL)
+    {
+        *bss_transition_supported = (bool)d->ext_cap_saved.ext_cap.BSS_Transition;
+    }
+#endif
+
+#if CONFIG_DRIVER_OWE
+    *trans_mode = d->owe_transition_mode;
+#endif
+    (void)memcpy((void *)trans_bssid, (const void *)d->trans_mac_address, MLAN_MAC_ADDR_LENGTH);
+
+    if (d->trans_ssid.ssid_len <= MLAN_MAX_SSID_LENGTH)
+    {
+        *trans_ssid_len = (int)d->trans_ssid.ssid_len;
+        (void)memcpy((void *)trans_ssid, (const void *)d->trans_ssid.ssid, d->trans_ssid.ssid_len);
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_get_scan_result_count(unsigned *count)
+{
+    if (count == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    *count = mlan_adap->num_in_scan_table;
+    return WM_SUCCESS;
+}
+
+int wrapper_wlan_set_regiontable(t_u8 region, t_u16 band)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    mlan_status rv       = wlan_set_regiontable(pmpriv, region, band);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+/*
+ * This function is supposed to be called after scan is complete.
+ */
+void wifi_scan_process_results(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    /*
+     * This function is normally supposed to be called from inside
+     * mlan_scan.c during parsing of scanning results. But we do not
+     * have async. cmd send functionality in the current design. So, we
+     * have moved this outside.
+     */
+    wlan_scan_process_results(pmpriv);
+}
+
+#if CONFIG_WPA2_ENTP
+void wifi_scan_enable_wpa2_enterprise_ap_only()
+{
+    scan_enable_wpa2_enterprise_ap_only = true;
+}
+
+bool wifi_get_scan_enable_wpa2_enterprise_ap_only()
+{
+    return scan_enable_wpa2_enterprise_ap_only;
+}
+#endif
+
+bool check_for_wpa2_entp_ie(bool *wpa2_entp_IE_exist, const void *element_data, unsigned element_len)
+{
+    uint8_t wpa2_ent_IE[4];
+    uint16_t len;
+
+    (void)memcpy((void *)&len, (const void *)element_data, sizeof(len));
+
+    if (len * 4U >= element_len)
+    {
+        return false;
+    }
+
+    (void)memcpy((void *)&wpa2_ent_IE, (const void *)((const char *)element_data + len * 4U + 2U * sizeof(len)), 4U);
+
+    if (!memcmp(wpa2_ent_IE, wpa2_akmp_oui, sizeof(wpa2_akmp_oui)))
+    {
+        /* WPA2 Enterprise IE is present in probe response. */
+        wifi_d("WPA2 Enterprise AKMP IE :: %x:%x:%x:%x\r\n", wpa2_ent_IE[0], wpa2_ent_IE[1], wpa2_ent_IE[2],
+               wpa2_ent_IE[3]);
+
+        *wpa2_entp_IE_exist = true;
+
+        return true;
+    }
+
+    return false;
+}
+
+/*
+ * The below wifi authenticate code, data structures and macros seems to be
+ * completely absent from mlan. Our current code, including the wlc manager
+ * currently depends on this command and its response (though it may be a
+ * no-op).
+ *
+ * fixme: remove this later when appropriate.
+ */
+#define host_CMD_802_11_AUTHENTICATE 0x0011
+#define AUTH_OPEN_SYSTEM             0
+
+typedef PACK_START struct host_802_11Authenticate_t
+{
+    uint8_t MacAddr[MLAN_MAC_ADDR_LENGTH];
+    uint8_t AuthType;
+    uint16_t TimeOut;
+    uint8_t Reserved[2];
+} PACK_END host_802_11Authenticate_t;
+
+void wifi_get_value1_from_cmdresp(const HostCmd_DS_COMMAND *resp, uint32_t *dev_value1)
+{
+    if (resp->params.mac_reg.offset == wlan_cpu_to_le16((t_u16)WLAN_VALUE1))
+    {
+        *dev_value1 = resp->params.mac_reg.value;
+    }
+}
+
+/*
+ * fixme: This function will be present till mlan integration is complete
+ */
+void wifi_get_mac_address_from_cmdresp(const HostCmd_DS_COMMAND *resp, uint8_t *get_mac_addr)
+{
+    (void)memcpy((void *)get_mac_addr, (const void *)&resp->params.mac_addr.mac_addr, MLAN_MAC_ADDR_LENGTH);
+}
+
+void wifi_get_firmware_ver_ext_from_cmdresp(const HostCmd_DS_COMMAND *resp, uint8_t *fw_ver_ext)
+{
+    uint8_t comma = 0x2C, space = 0x20;
+#ifdef RW610
+    uint8_t ver_str_len = resp->size - WIFI_HOST_CMD_FIXED_HEADER_LEN - sizeof(resp->params.verext.version_str_sel);
+#endif
+
+    if (!resp->params.verext.version_str_sel)
+    {
+        /* TODO: Below change is added to change 8978 firmware name to IW416.
+         * This change is temporary and can be removed once firmware changes are in place */
+        if (strstr((const char *)&resp->params.verext.version_str, "w8978o") != NULL)
+        {
+            (void)memcpy((void *)fw_ver_ext, (const void *)"IW416", 6);
+            (void)memcpy((void *)(fw_ver_ext + strlen((const char *)fw_ver_ext)),
+                         (const void *)&resp->params.verext.version_str[6],
+                         strlen((const char *)(&resp->params.verext.version_str)) - strlen((const char *)fw_ver_ext));
+        }
+        else
+        {
+            (void)memcpy((void *)fw_ver_ext, (const void *)&resp->params.verext.version_str,
+#ifdef RW610
+                         ver_str_len
+#else
+                         strlen((const char *)(&resp->params.verext.version_str))
+#endif
+            );
+        }
+    }
+    else if (resp->params.verext.version_str_sel == 3U && strlen((const char *)(&resp->params.verext.version_str)))
+    {
+        (void)memcpy((void *)(fw_ver_ext + strlen((const char *)fw_ver_ext)), (const void *)&comma, 1);
+        (void)memcpy((void *)(fw_ver_ext + strlen((const char *)fw_ver_ext)), (const void *)&space, 1);
+        (void)memcpy((void *)(fw_ver_ext + strlen((const char *)fw_ver_ext)),
+                     (const void *)&resp->params.verext.version_str,
+#ifdef RW610
+                     ver_str_len
+#else
+                     strlen((const char *)(&resp->params.verext.version_str))
+#endif
+        );
+    }
+    else if (resp->params.verext.version_str_sel == 4U && strlen((const char *)(&resp->params.verext.version_str)))
+    {
+        (void)memcpy((void *)(fw_ver_ext + strlen((const char *)fw_ver_ext)), (const void *)&comma, 1);
+        (void)memcpy((void *)(fw_ver_ext + strlen((const char *)fw_ver_ext)), (const void *)&space, 1);
+        (void)memcpy((void *)(fw_ver_ext + strlen((const char *)fw_ver_ext)),
+                     (const void *)&resp->params.verext.version_str,
+#ifdef RW610
+                     ver_str_len
+#else
+                     strlen((const char *)(&resp->params.verext.version_str))
+#endif
+        );
+    }
+    else
+    { /* Do Nothing */
+    }
+}
+
+void wifi_prepare_set_cal_data_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command = HostCmd_CMD_CFG_DATA;
+    cmd->size    = (t_u16)sizeof(HostCmd_DS_802_11_CFG_DATA) + (t_u16)S_DS_GEN + (t_u16)cal_data_len - (t_u16)1;
+    cmd->seq_num = seq_number;
+    cmd->result  = 0;
+    cmd->params.cfg_data.action   = HostCmd_ACT_GEN_SET;
+    cmd->params.cfg_data.type     = 0x02;
+    cmd->params.cfg_data.data_len = cal_data_len;
+    (void)memcpy((void *)cmd->params.cfg_data.data, (const void *)cal_data, cal_data_len);
+}
+
+#ifdef OTP_CHANINFO
+void wifi_prepare_get_channel_region_cfg_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command               = HostCmd_CMD_CHAN_REGION_CFG;
+    cmd->size                  = sizeof(HostCmd_DS_CHAN_REGION_CFG) + S_DS_GEN;
+    cmd->seq_num               = seq_number;
+    cmd->result                = 0;
+    cmd->params.reg_cfg.action = HostCmd_ACT_GEN_GET;
+}
+#endif
+
+#if CONFIG_COMPRESS_TX_PWTBL
+int wifi_set_region_power_cfg(const t_u8 *data, t_u16 len)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, 0 /* bss_type */);
+    cmd->result  = 0x0;
+    cmd->size    = len + S_DS_GEN;
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_REGION_POWER_CFG, HostCmd_ACT_GEN_SET, 0,
+                             NULL, (void *)data, cmd);
+    wifi_wait_for_cmdresp(NULL);
+    return WM_SUCCESS;
+}
+#endif
+
+void wifi_prepare_get_hw_spec_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command = HostCmd_CMD_GET_HW_SPEC;
+    cmd->size    = sizeof(HostCmd_DS_GET_HW_SPEC) + S_DS_GEN;
+    cmd->seq_num = seq_number;
+    cmd->result  = 0;
+}
+
+void wifi_prepare_reconfigure_tx_buf_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command = HostCmd_CMD_RECONFIGURE_TX_BUFF;
+    /* TODO: Replace hardcoded size with logical implementation */
+    cmd->size                    = 16;
+    cmd->seq_num                 = seq_number;
+    cmd->result                  = 0;
+    cmd->params.tx_buf.action    = HostCmd_ACT_GEN_SET;
+    cmd->params.tx_buf.buff_size = 2048;
+}
+
+/*
+ * fixme: This function will be present till mlan integration is complete
+ */
+void wifi_prepare_get_mac_addr_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command                = HostCmd_CMD_802_11_MAC_ADDRESS;
+    cmd->size                   = sizeof(HostCmd_DS_802_11_MAC_ADDRESS) + S_DS_GEN;
+    cmd->seq_num                = seq_number;
+    cmd->result                 = 0;
+    cmd->params.mac_addr.action = HostCmd_ACT_GEN_GET;
+}
+
+void wifi_prepare_get_fw_ver_ext_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number, int version_str_sel)
+{
+    cmd->command                       = HostCmd_CMD_VERSION_EXT;
+    cmd->size                          = sizeof(HostCmd_DS_VERSION_EXT) + S_DS_GEN;
+    cmd->seq_num                       = seq_number;
+    cmd->result                        = 0;
+    cmd->params.verext.version_str_sel = version_str_sel;
+}
+
+void wifi_prepare_get_value1(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command               = HostCmd_CMD_MAC_REG_ACCESS;
+    cmd->command               = wlan_cpu_to_le16(cmd->command);
+    cmd->size                  = wlan_cpu_to_le16(sizeof(HostCmd_DS_MAC_REG_ACCESS) + S_DS_GEN);
+    cmd->seq_num               = 0x0;
+    cmd->result                = 0x0;
+    cmd->params.mac_reg.action = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
+    cmd->params.mac_reg.offset = wlan_cpu_to_le16((t_u16)WLAN_VALUE1);
+    cmd->params.mac_reg.value  = 0x0;
+}
+
+void wifi_prepare_set_mac_addr_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command                = HostCmd_CMD_802_11_MAC_ADDRESS;
+    cmd->size                   = sizeof(HostCmd_DS_802_11_MAC_ADDRESS) + S_DS_GEN;
+    cmd->seq_num                = seq_number;
+    cmd->result                 = 0;
+    cmd->params.mac_addr.action = HostCmd_ACT_GEN_SET;
+    (void)memcpy((void *)cmd->params.mac_addr.mac_addr, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+}
+
+
+#if CONFIG_WIFI_TX_BUFF
+void wifi_prepare_set_tx_buf_size(HostCmd_DS_COMMAND *cmd, int seq_number)
+{
+    cmd->command                 = HostCmd_CMD_RECONFIGURE_TX_BUFF;
+    cmd->size                    = sizeof(HostCmd_DS_TXBUF_CFG) + S_DS_GEN;
+    cmd->seq_num                 = seq_number;
+    cmd->result                  = 0;
+    cmd->params.tx_buf.action    = HostCmd_ACT_GEN_SET;
+    cmd->params.tx_buf.buff_size = tx_buf_size;
+}
+#endif
+
+void wifi_prepare_enable_amsdu_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command                              = HostCmd_CMD_AMSDU_AGGR_CTRL;
+    cmd->size                                 = sizeof(HostCmd_DS_AMSDU_AGGR_CTRL) + S_DS_GEN;
+    cmd->seq_num                              = seq_number;
+    cmd->result                               = 0;
+    cmd->params.amsdu_aggr_ctrl.action        = HostCmd_ACT_GEN_SET;
+    cmd->params.amsdu_aggr_ctrl.enable        = 0x1;
+    cmd->params.amsdu_aggr_ctrl.curr_buf_size = 0x0;
+}
+
+#ifdef WLAN_LOW_POWER_ENABLE
+void wifi_prepare_low_power_mode_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command = HostCmd_CMD_LOW_POWER_MODE;
+    cmd->size    = sizeof(HostCmd_CONFIG_LOW_PWR_MODE) + S_DS_GEN;
+    cmd->seq_num = seq_number;
+    cmd->result  = 0;
+
+    cmd->params.low_pwr_mode_cfg.enable = 1;
+
+    return;
+}
+#endif
+
+void wlan_prepare_mac_control_cmd(HostCmd_DS_COMMAND *cmd, t_u16 seq_number)
+{
+    cmd->command = HostCmd_CMD_MAC_CONTROL;
+    cmd->size    = sizeof(HostCmd_DS_MAC_CONTROL) + S_DS_GEN;
+    cmd->seq_num = seq_number;
+    cmd->result  = 0;
+
+    cmd->params.mac_ctrl.action =
+#if CONFIG_11AC
+        HostCmd_ACT_MAC_STATIC_DYNAMIC_BW_ENABLE |
+#endif
+        HostCmd_ACT_MAC_RTS_CTS_ENABLE | HostCmd_ACT_MAC_RX_ON | HostCmd_ACT_MAC_TX_ON |
+        HostCmd_ACT_MAC_ETHERNETII_ENABLE;
+
+    return;
+}
+
+void wifi_set_cal_data(const uint8_t *cdata, const unsigned int clen)
+{
+    cal_data       = (uint8_t *)cdata;
+    cal_data_len   = (unsigned int)clen;
+    cal_data_valid = true;
+}
+
+void wifi_set_mac_addr(uint8_t *mac)
+{
+    mac_addr       = mac;
+    mac_addr_valid = true;
+}
+
+void _wifi_set_mac_addr(const uint8_t *mac, mlan_bss_type bss_type)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, bss_type);
+
+    cmd->result = 0x0;
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_MAC_ADDRESS,
+                                   HostCmd_ACT_GEN_SET, 0, NULL, (uint8_t *)mac, cmd);
+    (void)wifi_wait_for_cmdresp(NULL);
+    /* Also need to update priv->curr_addr, as rx reorder will check mac address using priv->curr_addr */
+    if (bss_type == MLAN_BSS_TYPE_STA)
+    {
+        (void)memcpy(&mlan_adap->priv[0]->curr_addr[0], &mac[0], MLAN_MAC_ADDR_LENGTH);
+#if CONFIG_WPA_SUPP
+        if (wm_wifi.supp_if_callbk_fns->mac_changed_callbk_fn)
+        {
+            wm_wifi.supp_if_callbk_fns->mac_changed_callbk_fn(wm_wifi.if_priv);
+        }
+#endif
+    }
+    else if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        (void)memcpy(&mlan_adap->priv[1]->curr_addr[0], &mac[0], MLAN_MAC_ADDR_LENGTH);
+#if CONFIG_WPA_SUPP
+        if (wm_wifi.supp_if_callbk_fns->mac_changed_callbk_fn)
+        {
+            wm_wifi.supp_if_callbk_fns->mac_changed_callbk_fn(wm_wifi.hapd_if_priv);
+        }
+#endif
+    }
+}
+
+#if CONFIG_WMM_UAPSD
+/**
+ *  @brief This function checks if there is no packet indication.
+ *
+ *  @param priv    A pointer to mlan_private structure
+ *
+ *  @return        true or false
+ */
+t_u8 wifi_check_no_packet_indication(mlan_private *priv)
+{
+    if ((wifi_wmm_get_packet_cnt() == 0) && priv->wmm_qosinfo && priv->curr_bss_params.wmm_uapsd_enabled)
+        return true;
+    else
+        return false;
+}
+
+/**
+ *  @brief This function checks if we need to send last packet indication.
+ *
+ *  @param priv    A pointer to mlan_private structure
+ *
+ *  @return        true or false
+ */
+t_u8 wifi_check_last_packet_indication(mlan_private *priv)
+{
+    if ((wifi_wmm_get_packet_cnt() == 1) && priv->wmm_qosinfo && priv->curr_bss_params.wmm_uapsd_enabled)
+        return true;
+    else
+        return false;
+}
+
+int wifi_wmm_qos_cfg(t_u8 *qos_cfg, t_u8 action)
+{
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+    mlan_ioctl_req req;
+    mlan_ds_wmm_cfg cfg;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    (void)memset(&cfg, 0x00, sizeof(mlan_ds_wmm_cfg));
+    cfg.sub_command = MLAN_OID_WMM_CFG_QOS;
+    if (action == HostCmd_ACT_GEN_SET)
+        cfg.param.qos_cfg = *qos_cfg;
+    req.pbuf    = (t_u8 *)&cfg;
+    req.buf_len = sizeof(mlan_ds_wmm_cfg);
+    req.req_id  = MLAN_IOCTL_WMM_CFG;
+
+    if (action == HostCmd_ACT_GEN_SET)
+        req.action = MLAN_ACT_SET;
+    else if (action == HostCmd_ACT_GEN_GET)
+        req.action = MLAN_ACT_GET;
+    ret = wlan_ops_sta_ioctl(mlan_adap, &req);
+
+    if (action == HostCmd_ACT_GEN_GET)
+        *qos_cfg = cfg.param.qos_cfg;
+    return ret;
+}
+
+int wifi_sleep_period(unsigned int *sleep_period, int action)
+{
+    int ret = WM_SUCCESS;
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, MLAN_BSS_TYPE_STA);
+    cmd->result  = 0x0;
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_SLEEP_PERIOD, action, 0, NULL,
+                             sleep_period, cmd);
+    if (action == HostCmd_ACT_GEN_SET)
+        ret = wifi_wait_for_cmdresp(NULL);
+    else if (action == HostCmd_ACT_GEN_GET)
+    {
+        mlan_ds_pm_cfg pm_cfg;
+        mlan_ioctl_req pioctl_buf;
+        pioctl_buf.pbuf = (t_u8 *)&pm_cfg;
+        memset((t_u8 *)&pioctl_buf, 0, sizeof(pioctl_buf));
+        memset((t_u8 *)&pm_cfg, 0, sizeof(pm_cfg));
+        ret           = wifi_wait_for_cmdresp(&pioctl_buf);
+        pm_cfg        = *(mlan_ds_pm_cfg *)pioctl_buf.pbuf;
+        *sleep_period = pm_cfg.param.sleep_period;
+    }
+    return ret;
+}
+#endif
+
+#if CONFIG_WIFI_TX_BUFF
+bool wifi_calibrate_tx_buf_size(uint16_t buf_size)
+{
+    uint16_t pre_tx_buf_size = tx_buf_size;
+    tx_buf_size              = MLAN_TX_DATA_BUF_SIZE_2K;
+
+#if defined(RW610)
+    if (buf_size >= MLAN_TX_DATA_BUF_SIZE_4K)
+        tx_buf_size = MLAN_TX_DATA_BUF_SIZE_4K;
+    _wlan_return_all_tx_buf(kIMU_LinkCpu1Cpu3);
+#else
+    if (buf_size >= MLAN_TX_DATA_BUF_SIZE_8K)
+        tx_buf_size = MLAN_TX_DATA_BUF_SIZE_8K;
+    else if (buf_size >= MLAN_TX_DATA_BUF_SIZE_4K)
+        tx_buf_size = MLAN_TX_DATA_BUF_SIZE_4K;
+#endif
+
+    return (tx_buf_size != pre_tx_buf_size) ? true : false;
+}
+
+void wifi_recfg_tx_buf_size(uint16_t buf_size)
+{
+    tx_buf_size = buf_size;
+}
+
+void _wifi_recfg_tx_buf_size(uint16_t buf_size, mlan_bss_type bss_type)
+{
+    if (!wifi_calibrate_tx_buf_size(buf_size))
+        return;
+
+    wifi_get_command_lock();
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+    cmd->result  = 0x0;
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_RECONFIGURE_TX_BUFF, HostCmd_ACT_GEN_SET,
+                             0, NULL, &tx_buf_size, cmd);
+    wifi_wait_for_cmdresp(NULL);
+}
+
+#endif
+
+#if CONFIG_WIFI_TX_PER_TRACK
+int wifi_set_tx_pert(void *cfg, mlan_bss_type bss_type)
+{
+    tx_pert_info *tx_pert = (tx_pert_info *)cfg;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    /* Store tx per tracking config in driver */
+    (void)memcpy((t_u8 *)&(mlan_adap->tx_pert), tx_pert, sizeof(tx_pert_info));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, bss_type);
+    cmd->result  = 0x0;
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_TX_RX_PKT_STATS,
+                             HostCmd_ACT_SET_TX_PER_TRACKING, 0, NULL, tx_pert, cmd);
+    wifi_wait_for_cmdresp(NULL);
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+int wifi_set_txrx_histogram(void *cfg, t_u8 *data)
+{
+    txrx_histogram_info *txrx_histogram    = (txrx_histogram_info *)cfg;
+    txrx_histogram_info txrx_histogram_cmd = {0};
+
+    txrx_histogram_cmd.enable = txrx_histogram->enable;
+    txrx_histogram_cmd.action = txrx_histogram->action;
+
+    if (txrx_histogram_cmd.enable == GET_TX_RX_HISTOGRAM)
+    {
+        txrx_histogram_cmd.enable = ENABLE_TX_RX_HISTOGRAM;
+    }
+    else
+    {
+        txrx_histogram_cmd.action = 0;
+    }
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_TX_RX_PKT_STATS, HostCmd_ACT_GEN_GET, 0,
+                             NULL, &txrx_histogram_cmd, cmd);
+    wifi_wait_for_cmdresp(data);
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_RX_ABORT_CFG
+int wifi_set_get_rx_abort_cfg(void *cfg, t_u16 action)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    cmd->seq_num            = 0x0;
+    cmd->result             = 0x0;
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_RX_ABORT_CFG, action, 0, NULL, cfg, cmd);
+    wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? cfg : NULL);
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+int wifi_set_get_rx_abort_cfg_ext(void *cfg, t_u16 action)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_RX_ABORT_CFG_EXT, action, 0, NULL, cfg,
+                             cmd);
+    wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? cfg : NULL);
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+int wifi_set_get_cck_desense_cfg(void *cfg, t_u16 action)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    cmd->seq_num            = 0x0;
+    cmd->result             = 0x0;
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_CCK_DESENSE_CFG, action, 0, NULL, cfg,
+                             cmd);
+    wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? cfg : NULL);
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+#ifdef WLAN_LOW_POWER_ENABLE
+void wifi_enable_low_pwr_mode()
+{
+    low_power_mode = true;
+}
+#endif
+
+#if CONFIG_ROAMING
+int wifi_config_roaming(const int enable, uint8_t *rssi_low)
+{
+    mlan_private *pmpriv = mlan_adap->priv[0];
+    int ret              = WM_SUCCESS;
+
+    if (enable)
+    {
+        pmpriv->roaming_enabled = MTRUE;
+        pmpriv->rssi_low        = *rssi_low;
+        ret                     = wifi_set_rssi_low_threshold(rssi_low);
+        if (ret != WM_SUCCESS)
+        {
+            wifi_e("Failed to config rssi threshold for roaming");
+            return -WM_FAIL;
+        }
+    }
+    else
+    {
+        if (pmpriv->roaming_enabled)
+        {
+            pmpriv->roaming_enabled = MFALSE;
+            pmpriv->rssi_low        = 0;
+            wifi_stop_bgscan();
+        }
+    }
+    return ret;
+}
+#endif
+
+#if CONFIG_11AX
+int wifi_set_11ax_tx_omi(const mlan_bss_type bss_type,
+                         const t_u16 tx_omi,
+                         const t_u8 tx_option,
+                         const t_u8 num_data_pkts)
+{
+    mlan_ioctl_req req;
+
+    mlan_ds_11ax_cmd_cfg cfg;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    (void)memset(&cfg, 0x00, sizeof(mlan_ds_11ax_cmd_cfg));
+
+    req.req_id  = MLAN_IOCTL_11AX_CFG;
+    req.action  = MLAN_ACT_SET;
+    req.pbuf    = (t_u8 *)&cfg;
+    req.buf_len = sizeof(mlan_ds_11ax_cmd_cfg);
+
+    cfg.sub_command                   = MLAN_OID_11AX_CMD_CFG;
+    cfg.sub_id                        = MLAN_11AXCMD_TXOMI_SUBID;
+    cfg.param.txomi_cfg.omi           = tx_omi;
+    cfg.param.txomi_cfg.tx_option     = tx_option;
+    cfg.param.txomi_cfg.num_data_pkts = num_data_pkts;
+
+    mlan_status rv;
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        req.bss_index = (t_u32)MLAN_BSS_TYPE_UAP;
+        rv            = wlan_ops_uap_ioctl(mlan_adap, &req);
+    }
+    else
+    {
+        req.bss_index = (t_u32)MLAN_BSS_TYPE_STA;
+        rv            = wlan_ops_sta_ioctl(mlan_adap, &req);
+    }
+
+    wm_wifi.cmd_resp_ioctl = NULL;
+
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_11ax_tol_time(const t_u32 tol_time)
+{
+    mlan_ioctl_req req;
+
+    mlan_ds_11ax_cmd_cfg cfg;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+    (void)memset(&cfg, 0x00, sizeof(mlan_ds_11ax_cmd_cfg));
+
+    req.req_id  = MLAN_IOCTL_11AX_CFG;
+    req.action  = MLAN_ACT_SET;
+    req.pbuf    = (t_u8 *)&cfg;
+    req.buf_len = sizeof(mlan_ds_11ax_cmd_cfg);
+
+    cfg.sub_command                = MLAN_OID_11AX_CMD_CFG;
+    cfg.sub_id                     = MLAN_11AXCMD_OBSS_TOLTIME_SUBID;
+    cfg.param.toltime_cfg.tol_time = tol_time;
+
+    mlan_status rv = wlan_ops_sta_ioctl(mlan_adap, &req);
+
+    if (rv != MLAN_STATUS_SUCCESS && rv != MLAN_STATUS_PENDING)
+        return MLAN_STATUS_FAILURE;
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+int wifi_set_11ax_rutxpowerlimit(const void *rutx_pwr_cfg, uint32_t rutx_pwr_cfg_len)
+{
+    int ret;
+    uint32_t reqd_len = 0;
+
+#if !CONFIG_MEM_POOLS
+    void *rutxcmd_resp_buff = OSA_MemoryAllocate(RUTXCMD_RESP_BUFF_SIZE);
+#else
+    void *rutxcmd_resp_buff = OSA_MemoryPoolAllocate(buf_1024_MemoryPool);
+#endif
+
+    if (rutxcmd_resp_buff == NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    ret = wlan_send_hostcmd(rutx_pwr_cfg, rutx_pwr_cfg_len / sizeof(uint8_t), rutxcmd_resp_buff, RUTXCMD_RESP_BUFF_SIZE,
+                            &reqd_len);
+
+    if (ret != WM_SUCCESS)
+    {
+        wifi_d("RUTXcmd failed error: %d", ret);
+    }
+
+    if (rutxcmd_resp_buff != NULL)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(rutxcmd_resp_buff);
+#else
+        OSA_MemoryPoolFree(buf_1024_MemoryPool, rutxcmd_resp_buff);
+#endif
+
+        return ret;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_11ax_rutxpowerlimit_legacy(const wifi_rutxpwrlimit_t *ru_pwr_cfg)
+{
+    t_u8 i;
+    int ret;
+    HostCmd_DS_COMMAND *cmd                    = wifi_get_command_buffer();
+    t_u8 *pByte                                = NULL;
+    mlan_ds_11ax_chanlrupwrcft_cmd *chrupc_tlv = NULL;
+
+    (void)wifi_get_command_lock();
+
+    cmd->command = HostCmd_CMD_11AX_CMD;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+    cmd->size    = sizeof(HostCmd_DS_11AX_CMD_CFG) + S_DS_GEN +
+                ru_pwr_cfg->num_chans * (sizeof(wifi_rupwrlimit_config_t) + sizeof(MrvlIEtypesHeader_t));
+
+    HostCmd_DS_11AX_CMD_CFG *axcmd = &cmd->params.axcmd;
+
+    axcmd->action = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+    axcmd->sub_id = wlan_cpu_to_le16(MLAN_11AXCMD_RUPOWER_SUBID);
+
+    pByte = (t_u8 *)axcmd->val;
+    for (i = 0; i < ru_pwr_cfg->num_chans; i++)
+    {
+        t_u8 j;
+        chrupc_tlv                               = (mlan_ds_11ax_chanlrupwrcft_cmd *)(void *)pByte;
+        chrupc_tlv->type                         = TLV_TYPE_CHANNEL_RU_PWR_CONFIG;
+        chrupc_tlv->len                          = sizeof(wifi_rupwrlimit_config_t);
+        chrupc_tlv->rupwrlimit_config.start_freq = ru_pwr_cfg->rupwrlimit_config[i].start_freq;
+        chrupc_tlv->rupwrlimit_config.width      = ru_pwr_cfg->rupwrlimit_config[i].width;
+        chrupc_tlv->rupwrlimit_config.chan_num   = ru_pwr_cfg->rupwrlimit_config[i].chan_num;
+        for (j = 0; j < MAX_RU_COUNT; j++)
+        {
+            chrupc_tlv->rupwrlimit_config.ruPower[j] = (t_s8)ru_pwr_cfg->rupwrlimit_config[i].ruPower[j];
+        }
+        pByte += chrupc_tlv->len + sizeof(MrvlIEtypesHeader_t);
+    }
+    ret = wifi_wait_for_cmdresp(NULL);
+    return ret;
+}
+
+int wifi_get_11ax_rutxpowerlimit_legacy(wifi_rutxpwrlimit_t *ru_pwr_cfg)
+{
+    int ret;
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)wifi_get_command_lock();
+
+    cmd->command = HostCmd_CMD_11AX_CMD;
+    cmd->seq_num = 0x0;
+    cmd->result  = 0x0;
+    cmd->size    = S_DS_GEN + 2U * sizeof(t_u16);
+
+    HostCmd_DS_11AX_CMD_CFG *rutxpwrlimit_config = (HostCmd_DS_11AX_CMD_CFG *)(void *)((uint8_t *)cmd + S_DS_GEN);
+
+    rutxpwrlimit_config->action = HostCmd_ACT_GEN_GET;
+
+    rutxpwrlimit_config->sub_id = MLAN_11AXCMD_RUPOWER_SUBID;
+
+    ret = wifi_wait_for_cmdresp(ru_pwr_cfg);
+
+    return ret;
+}
+
+int wifi_set_11ax_cfg(wifi_11ax_config_t *ax_config)
+{
+    /* alloc cmd and wait for response in prepare cmd, no need to deal with cmd outside */
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_11AX_CFG, HostCmd_ACT_GEN_SET, 0, NULL,
+                             ax_config, NULL);
+    return WM_SUCCESS;
+}
+
+#if CONFIG_11AX_TWT
+int wifi_set_btwt_cfg(const wifi_btwt_config_t *btwt_config)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_STA);
+    cmd->result  = 0x0;
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_DBGS_CFG);
+    cmd->size    = sizeof(wifi_btwt_config_t) + S_DS_GEN;
+    (void)memcpy(&cmd->params, btwt_config, sizeof(wifi_btwt_config_t));
+
+    wifi_wait_for_cmdresp(NULL);
+    return WM_SUCCESS;
+}
+
+int wifi_set_twt_setup_cfg(const wifi_twt_setup_config_t *twt_setup)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    mlan_ds_twtcfg twt_cfg  = {0};
+    MrvlIEtypes_He_cap_t *hw_he_cap;
+    MrvlIEtypes_He_cap_t *hw_2g_he_cap;
+    int ret = 0;
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_STA);
+    cmd->result  = 0x0;
+
+    twt_cfg.sub_id = MLAN_11AX_TWT_SETUP_SUBID;
+    (void)memcpy(&twt_cfg.param.twt_setup, twt_setup, sizeof(twt_cfg.param.twt_setup));
+
+    /* block BTWT setup command if firmware does not support BTWT */
+    if (twt_cfg.param.twt_setup.negotiation_type == 3)
+    {
+        hw_he_cap    = (MrvlIEtypes_He_cap_t *)&mlan_adap->hw_he_cap[0];
+        hw_2g_he_cap = (MrvlIEtypes_He_cap_t *)&mlan_adap->hw_2g_he_cap[0];
+        /* BTWT support bit 20 */
+        if ((hw_he_cap->he_mac_cap[2] & MBIT(4)) == 0 && (hw_2g_he_cap->he_mac_cap[2] & MBIT(4)) == 0)
+        {
+            wifi_put_command_lock();
+            wifi_e("Firmware does not support Broadcast TWT, please use support BTWT version");
+            return -WM_FAIL;
+        }
+    }
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_TWT_CFG, HostCmd_ACT_GEN_SET, 0, NULL,
+                             &twt_cfg, cmd);
+    ret = wifi_wait_for_cmdresp(&twt_cfg.param.twt_setup);
+    if (ret == WM_SUCCESS)
+    {
+        if (wm_wifi.cmd_resp_status != WM_SUCCESS)
+        {
+            wifi_e("TWT setup cfg error");
+        }
+        else
+        {
+            (void)PRINTF("TWT flow id: %d\r\n", twt_cfg.param.twt_setup.flow_identifier);
+        }
+    }
+    return WM_SUCCESS;
+}
+
+int wifi_set_twt_teardown_cfg(const wifi_twt_teardown_config_t *teardown_config)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    mlan_ds_twtcfg twt_cfg  = {0};
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_STA);
+    cmd->result  = 0x0;
+
+    twt_cfg.sub_id = MLAN_11AX_TWT_TEARDOWN_SUBID;
+    (void)memcpy(&twt_cfg.param.twt_teardown, teardown_config, sizeof(twt_cfg.param.twt_teardown));
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_TWT_CFG, HostCmd_ACT_GEN_SET, 0, NULL,
+                             &twt_cfg, cmd);
+    wifi_wait_for_cmdresp(NULL);
+    return WM_SUCCESS;
+}
+
+int wifi_get_twt_report(wifi_twt_report_t *twt_report)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    mlan_ds_twtcfg twt_cfg  = {0};
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_STA);
+    cmd->result  = 0x0;
+
+    twt_cfg.sub_id = MLAN_11AX_TWT_REPORT_SUBID;
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_TWT_CFG, HostCmd_ACT_GEN_GET, 0, NULL,
+                             &twt_cfg, cmd);
+    wifi_wait_for_cmdresp(twt_report);
+    return WM_SUCCESS;
+}
+
+#endif /* CONFIG_11AX_TWT */
+#endif
+
+#if CONFIG_WIFI_CLOCKSYNC
+int wifi_set_clocksync_cfg(const wifi_clock_sync_gpio_tsf_t *tsf_latch, mlan_bss_type bss_type)
+{
+    int ret;
+    mlan_ds_misc_cfg misc;
+    mlan_ioctl_req req;
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+    (void)memcpy((void *)&misc.param.gpio_tsf_latch_config, (const void *)tsf_latch,
+                 sizeof(misc.param.gpio_tsf_latch_config));
+
+    misc.sub_command       = (t_u32)MLAN_OID_MISC_GPIO_TSF_LATCH;
+    wm_wifi.cmd_resp_ioctl = &req;
+    req.pbuf               = (t_u8 *)&misc;
+    req.buf_len            = sizeof(mlan_ds_misc_cfg);
+    req.req_id             = (t_u32)MLAN_IOCTL_MISC_CFG;
+    req.action             = MLAN_ACT_SET;
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        req.bss_index = (t_u32)MLAN_BSS_TYPE_UAP;
+        ret           = (int)wlan_ops_uap_ioctl(mlan_adap, &req);
+    }
+    else
+    {
+        req.bss_index = (t_u32)MLAN_BSS_TYPE_STA;
+        ret           = (int)wlan_ops_sta_ioctl(mlan_adap, &req);
+    }
+
+    wm_wifi.cmd_resp_ioctl = NULL;
+    return ret;
+}
+
+int wifi_get_tsf_info(wifi_tsf_info_t *tsf_info)
+{
+    int ret;
+    mlan_ds_misc_cfg misc;
+    mlan_ioctl_req req;
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+    (void)memcpy((void *)&misc.param.tsf_info, (void *)tsf_info, sizeof(misc.param.tsf_info));
+
+    misc.sub_command       = (t_u32)MLAN_OID_MISC_GET_TSF_INFO;
+    wm_wifi.cmd_resp_ioctl = &req;
+    req.pbuf               = (t_u8 *)&misc;
+    req.buf_len            = sizeof(mlan_ds_misc_cfg);
+    req.bss_index          = 0;
+    req.req_id             = (t_u32)MLAN_IOCTL_MISC_CFG;
+    req.action             = MLAN_ACT_GET;
+
+    ret                    = (int)wlan_ops_sta_ioctl(mlan_adap, &req);
+    wm_wifi.cmd_resp_ioctl = NULL;
+
+    if (ret == WM_SUCCESS)
+    {
+        (void)memcpy((void *)tsf_info, (void *)&misc.param.tsf_info, sizeof(mlan_ds_tsf_info));
+    }
+    return ret;
+}
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+
+#if CONFIG_WMM
+static void wifi_wmm_tx_stats_dump_ralist(mlan_list_head *ra_list_head)
+{
+    raListTbl *ra_list = MNULL;
+
+    ra_list = (raListTbl *)util_peek_list(mlan_adap->pmoal_handle, ra_list_head, MNULL, MNULL);
+    while (ra_list && ra_list != (raListTbl *)ra_list_head)
+    {
+        wifi_w("    [%02X:XX:XX:XX:%02X:%02X] drop_cnt[%d] total_pkts[%d]", ra_list->ra[0], ra_list->ra[4],
+               ra_list->ra[5], ra_list->drop_count, ra_list->total_pkts);
+
+        ra_list = ra_list->pnext;
+    }
+}
+
+void wifi_wmm_tx_stats_dump(int bss_type)
+{
+    int i;
+    mlan_private *priv = MNULL;
+
+    if (bss_type == MLAN_BSS_TYPE_STA)
+        priv = mlan_adap->priv[0];
+    else if (bss_type == MLAN_BSS_TYPE_UAP)
+        priv = mlan_adap->priv[1];
+    else
+        return;
+
+    for (i = 0; i < MAX_AC_QUEUES; i++)
+    {
+        wifi_w("Dump priv[%d] ac_queue[%d]", bss_type, i);
+        wifi_wmm_tx_stats_dump_ralist(&priv->wmm.tid_tbl_ptr[i].ra_list);
+    }
+
+    wifi_w("Dump priv[%d] driver_error_cnt:", bss_type);
+    wifi_w("    tx_no_media[%hu]", priv->driver_error_cnt.tx_no_media);
+    wifi_w("    tx_err_mem[%hu]", priv->driver_error_cnt.tx_err_mem);
+    wifi_w("    tx_wmm_retried_drop[%hu]", priv->driver_error_cnt.tx_wmm_retried_drop);
+    wifi_w("    tx_wmm_pause_drop[%hu]", priv->driver_error_cnt.tx_wmm_pause_drop);
+    wifi_w("    tx_wmm_pause_replaced[%hu]", priv->driver_error_cnt.tx_wmm_pause_replaced);
+    wifi_w("    rx_reorder_drop[%hu]", priv->driver_error_cnt.rx_reorder_drop);
+
+    int free_cnt_real   = 0;
+    mlan_linked_list *p = MNULL;
+
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+
+    p = util_peek_list(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list, MNULL, MNULL);
+    while (p && p != (mlan_linked_list *)&mlan_adap->outbuf_pool.free_list)
+    {
+        free_cnt_real++;
+        p = p->pnext;
+    }
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+    wifi_w("TX buffer pool: free_cnt[%d] real_free_cnt[%d]", mlan_adap->outbuf_pool.free_cnt, free_cnt_real);
+
+#if CONFIG_WMM_DEBUG
+    for (i = 0; i < MAX_AC_QUEUES; i++)
+    {
+        wifi_w("Dump priv[%d] ac_queue[%d] history ra", bss_type, i);
+        wifi_wmm_tx_stats_dump_ralist(&priv->wmm.hist_ra[i]);
+    }
+#endif
+}
+#endif
+
+#if CONFIG_MULTI_CHAN
+int wifi_set_mc_cfg(uint32_t channel_time)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd               = wifi_get_command_buffer();
+    mlan_ds_multi_chan_cfg multi_chan_cfg = {0};
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, 0U /* bss_type */);
+    cmd->result  = 0x0;
+
+    multi_chan_cfg.channel_time  = channel_time;
+    multi_chan_cfg.buffer_weight = 1;
+
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MULTI_CHAN_CONFIG,
+                                   HostCmd_ACT_GEN_SET, 0, NULL, &multi_chan_cfg, cmd);
+    (void)wifi_wait_for_cmdresp(NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_mc_cfg(uint32_t *channel_time)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd    = wifi_get_command_buffer();
+    mlan_ioctl_req ioctl_req   = {0};
+    mlan_ds_misc_cfg ioctl_cfg = {0};
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, 0U /* bss_type */);
+    cmd->result  = 0x0;
+
+    wm_wifi.cmd_resp_ioctl = &ioctl_req;
+    ioctl_req.pbuf         = (t_u8 *)&ioctl_cfg;
+    ioctl_req.buf_len      = sizeof(ioctl_cfg);
+
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MULTI_CHAN_CONFIG,
+                                   HostCmd_ACT_GEN_GET, 0, NULL, &ioctl_cfg.param.multi_chan_cfg, cmd);
+    (void)wifi_wait_for_cmdresp(NULL);
+    wm_wifi.cmd_resp_ioctl = NULL;
+    (*channel_time)        = ioctl_cfg.param.multi_chan_cfg.channel_time;
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_set_mc_policy(const int status)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd    = wifi_get_command_buffer();
+    t_u16 mc_policy            = (t_u16)status;
+    mlan_ioctl_req ioctl_req   = {0};
+    mlan_ds_misc_cfg ioctl_cfg = {0};
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, 0U /* bss_type */);
+    cmd->result  = 0x0;
+
+    wm_wifi.cmd_resp_ioctl            = &ioctl_req;
+    ioctl_req.action                  = (mlan_act_ioctl)HostCmd_ACT_GEN_SET;
+    ioctl_req.pbuf                    = (t_u8 *)&ioctl_cfg;
+    ioctl_req.buf_len                 = sizeof(ioctl_cfg);
+    ioctl_cfg.param.multi_chan_policy = mc_policy;
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_MULTI_CHAN_POLICY,
+                                   HostCmd_ACT_GEN_SET, 0, NULL, &mc_policy, cmd);
+    (void)wifi_wait_for_cmdresp(NULL);
+    wm_wifi.cmd_resp_ioctl = NULL;
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_mc_policy(void)
+{
+    return (int)mlan_adap->mc_policy;
+}
+
+int wifi_set_mc_cfg_ext(const wifi_drcs_cfg_t *drcs, const int num)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd      = wifi_get_command_buffer();
+    mlan_ds_drcs_cfg drcs_cfg[2] = {0};
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, 0U /* bss_type */);
+    cmd->result  = 0x0;
+
+    /* struct align is different */
+    (void)memcpy(&drcs_cfg[0], drcs, sizeof(mlan_ds_drcs_cfg));
+    if (num == 2)
+    {
+        (void)memcpy(&drcs_cfg[1], drcs + 1, sizeof(mlan_ds_drcs_cfg));
+    }
+
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_DRCS_CONFIG, HostCmd_ACT_GEN_SET, 0,
+                                   NULL, &drcs_cfg, cmd);
+    (void)wifi_wait_for_cmdresp(NULL);
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_get_mc_cfg_ext(wifi_drcs_cfg_t *drcs, int num)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd    = wifi_get_command_buffer();
+    mlan_ioctl_req ioctl_req   = {0};
+    mlan_ds_misc_cfg ioctl_cfg = {0};
+
+    if (num != 2)
+    {
+        wifi_e("drcs should get 2 drcs config");
+        (void)wifi_put_command_lock();
+        return -WM_FAIL;
+    }
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, 0U /* bss_type */);
+    cmd->result  = 0x0;
+
+    wm_wifi.cmd_resp_ioctl = &ioctl_req;
+    ioctl_req.pbuf         = (t_u8 *)&ioctl_cfg;
+    ioctl_req.buf_len      = sizeof(ioctl_cfg);
+
+    (void)wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_DRCS_CONFIG, HostCmd_ACT_GEN_GET, 0,
+                                   NULL, &ioctl_cfg.param.drcs_cfg[0], cmd);
+    (void)wifi_wait_for_cmdresp(NULL);
+    wm_wifi.cmd_resp_ioctl = NULL;
+
+    /* struct align is different */
+    (void)memcpy(drcs, &ioctl_cfg.param.drcs_cfg[0], sizeof(mlan_ds_drcs_cfg));
+    (void)memcpy(drcs + 1, &ioctl_cfg.param.drcs_cfg[1], sizeof(mlan_ds_drcs_cfg));
+    return wm_wifi.cmd_resp_status;
+}
+#endif
+
+
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+/**
+ *  @brief This function submit the subscribe event command to firmware.
+ *
+ *  @param priv       A pointer to mlan_private structure.
+ *  @sub_evt          subscribe event to submit.
+ *
+ *  @return           MLAN_STATUS_SUCCESS, WM_E_INVAL or MLAN_STATUS_FAILURE
+ */
+int wifi_subscribe_event_submit(mlan_private *pmpriv, mlan_ds_subscribe_evt *sub_evt)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->command = HostCmd_CMD_802_11_SUBSCRIBE_EVENT;
+    cmd->seq_num = 0;
+    cmd->result  = 0x0;
+
+    if (sub_evt->evt_action != HostCmd_ACT_GEN_GET)
+    {
+        wlan_ops_sta_prepare_cmd(pmpriv, HostCmd_CMD_802_11_SUBSCRIBE_EVENT, HostCmd_ACT_GEN_SET, 0, NULL, sub_evt,
+                                 cmd);
+        wifi_wait_for_cmdresp(NULL);
+    }
+    else if (sub_evt->evt_action == HostCmd_ACT_GEN_GET)
+    {
+        wlan_ops_sta_prepare_cmd(pmpriv, HostCmd_CMD_802_11_SUBSCRIBE_EVENT, HostCmd_ACT_GEN_GET, 0, NULL, NULL, cmd);
+        wifi_wait_for_cmdresp(sub_evt);
+    }
+    else
+        return WM_E_INVAL;
+
+    return wm_wifi.cmd_resp_status;
+}
+
+/**
+ *  @brief This function get all subscribe event from firmware.
+ *
+ *  @param priv       A pointer to mlan_private structure.
+ *  @sub_evt          subscribe event to submit.
+ *
+ *  @return           MLAN_STATUS_SUCCESS, WM_E_INVAL or MLAN_STATUS_FAILURE
+ */
+int wifi_get_subscribe_event(mlan_private *pmpriv, mlan_ds_subscribe_evt *sub_evt)
+{
+    if (!sub_evt)
+        return WM_E_INVAL;
+    if (!pmpriv)
+        pmpriv = mlan_adap->priv[0];
+    sub_evt->evt_action = HostCmd_ACT_GEN_GET;
+    return wifi_subscribe_event_submit(pmpriv, sub_evt);
+}
+
+/**
+ *  @brief This function disable the specific subscribe event.
+ *
+ *  @param priv       A pointer to mlan_private structure.
+ *  @sbitmap          the specific subscribe event will be disabled.
+ *
+ *  @return           MLAN_STATUS_SUCCESS, WM_E_INVAL or MLAN_STATUS_FAILURE
+ */
+int wifi_clear_subscribe_event(mlan_private *pmpriv, int evt_bitmap)
+{
+    mlan_ds_subscribe_evt sub_evt;
+    if (!pmpriv)
+        pmpriv = mlan_adap->priv[0];
+    memset((t_u8 *)&sub_evt, 0, sizeof(sub_evt));
+    sub_evt.evt_action = SUBSCRIBE_EVT_ACT_BITWISE_CLR;
+    sub_evt.evt_bitmap = evt_bitmap;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_rssi_low(mlan_private *pmpriv, unsigned int rssi_low, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action    = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap    = SUBSCRIBE_EVT_RSSI_LOW;
+    sub_evt.low_rssi      = rssi_low;
+    sub_evt.low_rssi_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+int wifi_set_threshold_rssi_high(mlan_private *pmpriv, unsigned int rssi_high, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action     = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap     = SUBSCRIBE_EVT_RSSI_HIGH;
+    sub_evt.high_rssi      = rssi_high;
+    sub_evt.high_rssi_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+int wifi_set_threshold_snr_low(mlan_private *pmpriv, unsigned int snr_low, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action   = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap   = SUBSCRIBE_EVT_SNR_LOW;
+    sub_evt.low_snr      = snr_low;
+    sub_evt.low_snr_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_snr_high(mlan_private *pmpriv, unsigned int snr_high, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action    = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap    = SUBSCRIBE_EVT_SNR_HIGH;
+    sub_evt.high_snr      = snr_high;
+    sub_evt.high_snr_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+int wifi_set_threshold_max_fail(mlan_private *pmpriv, unsigned int max_fail, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action         = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap         = SUBSCRIBE_EVT_MAX_FAIL;
+    sub_evt.failure_count      = max_fail;
+    sub_evt.failure_count_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_beacon_miss(mlan_private *pmpriv, unsigned int beacon_miss, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action       = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap       = SUBSCRIBE_EVT_BEACON_MISSED;
+    sub_evt.beacon_miss      = beacon_miss;
+    sub_evt.beacon_miss_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_data_rssi_low(mlan_private *pmpriv, unsigned int data_rssi_low, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action         = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap         = SUBSCRIBE_EVT_DATA_RSSI_LOW;
+    sub_evt.data_low_rssi      = data_rssi_low;
+    sub_evt.data_low_rssi_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_data_rssi_high(mlan_private *pmpriv, unsigned int data_rssi_high, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action          = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap          = SUBSCRIBE_EVT_DATA_RSSI_HIGH;
+    sub_evt.data_high_rssi      = data_rssi_high;
+    sub_evt.data_high_rssi_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_data_snr_low(mlan_private *pmpriv, unsigned int data_snr_low, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action        = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap        = SUBSCRIBE_EVT_DATA_SNR_LOW;
+    sub_evt.data_low_snr      = data_snr_low;
+    sub_evt.data_low_snr_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_data_snr_high(mlan_private *pmpriv, unsigned int data_snr_high, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action         = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap         = SUBSCRIBE_EVT_DATA_SNR_HIGH;
+    sub_evt.data_high_snr      = data_snr_high;
+    sub_evt.data_high_snr_freq = freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_link_quality(mlan_private *pmpriv,
+                                    unsigned int link_snr,
+                                    unsigned int link_snr_freq,
+                                    unsigned int link_rate,
+                                    unsigned int link_rate_freq,
+                                    unsigned int link_tx_latency,
+                                    unsigned int link_tx_lantency_freq)
+{
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action            = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap            = SUBSCRIBE_EVT_LINK_QUALITY;
+    sub_evt.link_snr              = link_snr;
+    sub_evt.link_snr_freq         = link_snr_freq;
+    sub_evt.link_rate             = link_rate;
+    sub_evt.link_rate_freq        = link_rate_freq;
+    sub_evt.link_tx_latency       = link_tx_latency;
+    sub_evt.link_tx_lantency_freq = link_tx_lantency_freq;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+
+int wifi_set_threshold_pre_beacon_lost(mlan_private *pmpriv, unsigned int pre_beacon_lost, unsigned int freq)
+{
+    if (!pmpriv)
+        return WM_E_INVAL;
+    mlan_ds_subscribe_evt sub_evt;
+    sub_evt.evt_action      = SUBSCRIBE_EVT_ACT_BITWISE_SET;
+    sub_evt.evt_bitmap      = SUBSCRIBE_EVT_PRE_BEACON_LOST;
+    sub_evt.pre_beacon_miss = pre_beacon_lost;
+    return wifi_subscribe_event_submit(pmpriv, &sub_evt);
+}
+#endif
+
+#if CONFIG_11MC
+location_cfg_info_t g_ftm_location_cfg;
+location_civic_rep_t g_ftm_civic_cfg;
+
+void wlan_civic_ftm_cfg(location_civic_rep_t *ftm_civic_cfg)
+{
+    g_ftm_civic_cfg.civic_location_type = ftm_civic_cfg->civic_location_type;
+    g_ftm_civic_cfg.civic_address_type  = ftm_civic_cfg->civic_address_type;
+    g_ftm_civic_cfg.civic_req           = ftm_civic_cfg->civic_req;
+    g_ftm_civic_cfg.country_code        = ftm_civic_cfg->country_code;
+}
+
+void wlan_location_ftm_cfg(location_cfg_info_t *ftm_location_cfg)
+{
+    g_ftm_location_cfg.lat_unc   = ftm_location_cfg->lat_unc;
+    g_ftm_location_cfg.long_unc  = ftm_location_cfg->long_unc;
+    g_ftm_location_cfg.alt_unc   = ftm_location_cfg->alt_unc;
+    g_ftm_location_cfg.lci_req   = ftm_location_cfg->lci_req;
+    g_ftm_location_cfg.longitude = ftm_location_cfg->longitude;
+    g_ftm_location_cfg.latitude  = ftm_location_cfg->latitude;
+    g_ftm_location_cfg.altitude  = ftm_location_cfg->altitude;
+}
+
+void wlan_dot11mc_ftm_cfg(void *p_buf, ftm_11mc_nego_cfg_t *ftm_11mc_nego_cfg)
+{
+    HostCmd_DS_COMMAND *cmd     = (HostCmd_DS_COMMAND *)p_buf;
+    dot11mc_ftm_cfg_t *cfg_11mc = (dot11mc_ftm_cfg_t *)&cmd->params.ftm_session_cfg.tlv.cfg_11mc;
+
+    cfg_11mc->sess_tlv.type                = wlan_cpu_to_le16(FTM_SESSION_CFG_INITATOR_TLV_ID);
+    cfg_11mc->sess_tlv.len                 = wlan_cpu_to_le16(sizeof(ftm_session_cfg_t) + sizeof(t_u16));
+    cfg_11mc->sess_tlv.val.burst_exponent  = ftm_11mc_nego_cfg->burst_exponent;
+    cfg_11mc->sess_tlv.val.burst_duration  = ftm_11mc_nego_cfg->burst_duration;
+    cfg_11mc->sess_tlv.val.min_delta_FTM   = ftm_11mc_nego_cfg->min_delta_FTM;
+    cfg_11mc->sess_tlv.val.is_ASAP         = ftm_11mc_nego_cfg->is_ASAP;
+    cfg_11mc->sess_tlv.val.per_burst_FTM   = ftm_11mc_nego_cfg->per_burst_FTM;
+    cfg_11mc->sess_tlv.val.channel_spacing = ftm_11mc_nego_cfg->channel_spacing;
+    cfg_11mc->sess_tlv.val.burst_period    = wlan_cpu_to_le16(ftm_11mc_nego_cfg->burst_period);
+    cfg_11mc->sess_tlv.civic_req           = g_ftm_civic_cfg.civic_req;
+    cfg_11mc->sess_tlv.lci_req             = g_ftm_location_cfg.lci_req;
+    cmd->size += sizeof(ftm_session_cfg_tlv_t);
+
+    if (cfg_11mc->sess_tlv.lci_req)
+    {
+        cfg_11mc->lci_tlv.type          = wlan_cpu_to_le16(FTM_SESSION_CFG_LCI_TLV_ID);
+        cfg_11mc->lci_tlv.len           = wlan_cpu_to_le16(sizeof(lci_cfg_t));
+        cfg_11mc->lci_tlv.val.altitude  = g_ftm_location_cfg.altitude;
+        cfg_11mc->lci_tlv.val.alt_unc   = g_ftm_location_cfg.alt_unc;
+        cfg_11mc->lci_tlv.val.latitude  = g_ftm_location_cfg.latitude;
+        cfg_11mc->lci_tlv.val.lat_unc   = g_ftm_location_cfg.lat_unc;
+        cfg_11mc->lci_tlv.val.longitude = g_ftm_location_cfg.longitude;
+        cfg_11mc->lci_tlv.val.long_unc  = g_ftm_location_cfg.long_unc;
+        cfg_11mc->lci_tlv.val.z_info    = Z_INFO;
+        cmd->size += sizeof(lci_tlv_t);
+    }
+
+    if (cfg_11mc->sess_tlv.civic_req)
+    {
+        cfg_11mc->civic_tlv.type                     = wlan_cpu_to_le16(FTM_SESSION_CFG_LOCATION_CIVIC_TLV_ID);
+        cfg_11mc->civic_tlv.len                      = wlan_cpu_to_le16(sizeof(civic_loc_cfg_t) -
+                                                                        sizeof(cfg_11mc->civic_tlv.val.civic_address) + strlen(ftm_address));
+        cfg_11mc->civic_tlv.val.civic_address_type   = g_ftm_civic_cfg.civic_address_type;
+        cfg_11mc->civic_tlv.val.civic_location_type  = g_ftm_civic_cfg.civic_location_type;
+        cfg_11mc->civic_tlv.val.country_code         = wlan_cpu_to_le16(g_ftm_civic_cfg.country_code);
+        cfg_11mc->civic_tlv.val.civic_address_length = strlen(ftm_address);
+        (void)memcpy(cfg_11mc->civic_tlv.val.civic_address, ftm_address, strlen(ftm_address));
+        cmd->size += (cfg_11mc->civic_tlv.len + sizeof(t_u32)) + sizeof(t_u16);
+    }
+
+    cmd->size                  = wlan_cpu_to_le16(cmd->size);
+    g_ftm_location_cfg.lci_req = 0;
+    g_ftm_civic_cfg.civic_req  = 0;
+}
+#endif
+
+#if CONFIG_11AZ
+void wlan_dto11az_ranging_cfg(void *p_buf, const t_u8 protocl, HostCmd_FTM_SESSION_CFG *ftm_session_cfg)
+{
+    HostCmd_DS_COMMAND *cmd        = (HostCmd_DS_COMMAND *)p_buf;
+    dot11az_ftm_cfg_t *cfg_11az    = (dot11az_ftm_cfg_t *)&cmd->params.ftm_session_cfg.tlv.cfg_11az;
+    dot11az_ftm_cfg_t *in_cfg_11az = &ftm_session_cfg->tlv.cfg_11az;
+    cfg_11az->range_tlv.len        = wlan_cpu_to_le16(sizeof(ranging_cfg_t));
+
+    if (protocl == PROTO_DOT11AZ_TB)
+        cfg_11az->range_tlv.type = wlan_cpu_to_le16(FTM_TB_RANGING_CFG_TLV_ID);
+    else
+        cfg_11az->range_tlv.type = wlan_cpu_to_le16(FTM_NTB_RANGING_CFG_TLV_ID);
+
+    cfg_11az->range_tlv.val.format_bw                 = in_cfg_11az->range_tlv.val.format_bw;
+    cfg_11az->range_tlv.val.max_i2r_sts_upto80        = in_cfg_11az->range_tlv.val.max_i2r_sts_upto80;
+    cfg_11az->range_tlv.val.max_r2i_sts_upto80        = in_cfg_11az->range_tlv.val.max_r2i_sts_upto80;
+    cfg_11az->range_tlv.val.az_measurement_freq       = in_cfg_11az->range_tlv.val.az_measurement_freq;
+    cfg_11az->range_tlv.val.az_number_of_measurements = in_cfg_11az->range_tlv.val.az_number_of_measurements;
+    cfg_11az->range_tlv.val.i2r_lmr_feedback          = in_cfg_11az->range_tlv.val.i2r_lmr_feedback;
+
+    cfg_11az->range_tlv.val.civic_req = in_cfg_11az->range_tlv.val.civic_req;
+    cfg_11az->range_tlv.val.lci_req   = in_cfg_11az->range_tlv.val.lci_req;
+
+    cmd->size += (sizeof(dot11az_ftm_cfg_t));
+}
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+void wifi_ftm_process_cfg_resp(void *resp_buff)
+{
+    HostCmd_DS_COMMAND *resp = (HostCmd_DS_COMMAND *)resp_buff;
+
+    if ((wlan_cpu_to_le16(resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.type) == FTM_NTB_RANGING_CFG_TLV_ID) ||
+        (wlan_cpu_to_le16(resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.type) == FTM_TB_RANGING_CFG_TLV_ID))
+    {
+        if (resp->params.ftm_session_cfg.action == MLAN_ACT_SET)
+            wifi_d("\n\nSet Ranging Parameters: \r\n");
+        else
+            wifi_d("\n\nGet Ranging Parameters: \r\n");
+        wifi_d("---------------------------------\r\n");
+        wifi_d("format_bw:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.val.format_bw);
+        wifi_d("az_measurement_freq:%d \r\n",
+               resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.val.az_measurement_freq);
+        wifi_d("az_number_of_measurements:%d \r\n",
+               resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.val.az_number_of_measurements);
+        wifi_d("max_i2r_sts_upto80:%d \r\n",
+               resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.val.max_i2r_sts_upto80);
+        wifi_d("max_r2i_sts_upto80:%d \r\n",
+               resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.val.max_r2i_sts_upto80);
+        wifi_d("i2r_lmr_feedback:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11az.range_tlv.val.i2r_lmr_feedback);
+    }
+    else if (wlan_cpu_to_le16(resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.type) ==
+             FTM_SESSION_CFG_INITATOR_TLV_ID)
+    {
+        if (resp->params.ftm_session_cfg.action == BG_SCAN_ACT_SET)
+            wifi_d("\n\nSet dot11mc ftm session config: \r\n");
+        else
+            wifi_d("\n\nGet dot11mc ftm session config: \r\n");
+
+        wifi_d("---------------------------------\r\n");
+        wifi_d("burst_exponent:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.val.burst_exponent);
+        wifi_d("burst_duration:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.val.burst_duration);
+        wifi_d("min_delta_FTM:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.val.min_delta_FTM);
+        wifi_d("is_ASAP:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.val.is_ASAP);
+        wifi_d("per_burst_FTM:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.val.per_burst_FTM);
+        wifi_d("channel_spacing:%d \r\n", resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.val.channel_spacing);
+        wifi_d("burst_period:%d \n\n", resp->params.ftm_session_cfg.tlv.cfg_11mc.sess_tlv.val.burst_period);
+    }
+    else
+        wifi_d("Invaild TLV return code \r\n");
+}
+
+void wifi_ftm_process_ctrl_resp(void *resp_buff)
+{
+    HostCmd_DS_COMMAND *resp = (HostCmd_DS_COMMAND *)resp_buff;
+
+    if (resp->result == HostCmd_RESULT_OK)
+    {
+        if (resp->params.ftm_session_ctrl.action == FTM_ACTION_START)
+        {
+            wifi_d("[INFO] FTM Session Control Started on %d channel with Peer %02X:%02X:%02X:%02X:%02X:%02X \r\n",
+                   resp->params.ftm_session_ctrl.chan, resp->params.ftm_session_ctrl.peer_mac[0],
+                   resp->params.ftm_session_ctrl.peer_mac[1], resp->params.ftm_session_ctrl.peer_mac[2],
+                   resp->params.ftm_session_ctrl.peer_mac[3], resp->params.ftm_session_ctrl.peer_mac[4],
+                   resp->params.ftm_session_ctrl.peer_mac[5]);
+        }
+        else if (resp->params.ftm_session_ctrl.action == FTM_ACTION_STOP)
+            wifi_d("[INFO] FTM Session Stopped\r\n");
+        else
+            wifi_d("[ERROR] Hostcmd action not supported\r\n");
+    }
+    else
+    {
+        wifi_d("[ERROR] Hostcmd failed: ReturnCode=%#04x, Result=%#04x\n", wlan_cpu_to_le16(resp->command),
+               wlan_cpu_to_le16(resp->result));
+    }
+}
+
+void wifi_ftm_process_event(void *p_data)
+{
+    wls_event_t *ftm_event = (wls_event_t *)p_data;
+    double distance        = 0.0;
+
+    PRINTF("[INFO] EventID: 0x%x SubeventID:%d \r\n", ftm_event->event_id, ftm_event->sub_event_id);
+
+    switch (ftm_event->sub_event_id)
+    {
+        case WLS_SUB_EVENT_FTM_COMPLETE:
+            PRINTF("\n\nFTM Session Complete:\r\n");
+            PRINTF("=====================\r\n");
+            PRINTF("Average RTT: %d ns\r\n", ftm_event->e.ftm_complete.avg_rtt);
+            PRINTF("Average Clockoffset:%d ns\r\n", ftm_event->e.ftm_complete.avg_clk_offset);
+            distance = ((ftm_event->e.ftm_complete.avg_clk_offset / 2) * (0.0003));
+            PRINTF("Distance: %.6f meters\r\n\n", distance);
+            wlan_wlcmgr_send_msg(WIFI_EVENT_FTM_COMPLETE, WIFI_EVENT_REASON_SUCCESS, NULL);
+            break;
+        case WLS_SUB_EVENT_RADIO_RECEIVED:
+            wifi_d("WLS_SUB_EVENT_RADIO_RECEIVED\n");
+            break;
+        case WLS_SUB_EVENT_RADIO_RPT_RECEIVED:
+            wifi_d("WLS_SUB_EVENT_RADIO_RPT_RECEIVED\n");
+            break;
+        case WLS_SUB_EVENT_ANQP_RESP_RECEIVED:
+            wifi_d("WLS_SUB_EVENT_ANQP_RESP_RECEIVED\n");
+            break;
+        case WLS_SUB_EVENT_FTM_FAIL:
+            wifi_d("WLS_SUB_EVENT_ANQP_RESP_RECEIVED\n");
+            PRINTF("\nFTM Session Failed!\r\n");
+            break;
+        default:
+            wifi_d("[ERROR] Unknown sub event\n");
+            break;
+    }
+}
+#endif
+
+#ifdef RW610
+uint32_t wifi_get_board_type()
+{
+    status_t status;
+    static uint32_t wifi_rw610_package_type = 0xFFFFFFFF;
+
+    if (0xFFFFFFFF == wifi_rw610_package_type)
+    {
+        OCOTP_OtpInit();
+        status = OCOTP_ReadPackage(&wifi_rw610_package_type);
+        if (status != kStatus_Success)
+        {
+            /*If status error, use BGA as default type*/
+            wifi_rw610_package_type = RW610_PACKAGE_TYPE_BGA;
+        }
+        OCOTP_OtpDeinit();
+    }
+
+    return wifi_rw610_package_type;
+}
+#endif
+
+#ifdef RW610
+void wifi_cau_temperature_enable()
+{
+    t_u32 val;
+
+    val = WIFI_REG32(WLAN_CAU_ENABLE_ADDR);
+    val &= ~(0xC);
+    val |= (2 << 2);
+    WIFI_WRITE_REG32(WLAN_CAU_ENABLE_ADDR, val);
+    OSA_TimeDelay(1);
+}
+
+int32_t wifi_get_temperature(void)
+{
+    int32_t val                   = 0;
+    uint32_t reg_val              = 0;
+    uint32_t temp_Cau_Raw_Reading = 0;
+    uint32_t board_type           = 0;
+
+    reg_val              = WIFI_REG32(WLAN_CAU_TEMPERATURE_ADDR);
+    temp_Cau_Raw_Reading = ((reg_val & 0XFFC00) >> 10);
+    board_type           = wifi_get_board_type();
+
+    switch (board_type)
+    {
+        case RW610_PACKAGE_TYPE_QFN:
+            val = (((((int32_t)(temp_Cau_Raw_Reading)) * 484260) - 220040600) / 1000000);
+            break;
+
+        case RW610_PACKAGE_TYPE_CSP:
+            val = (((((int32_t)(temp_Cau_Raw_Reading)) * 480560) - 220707000) / 1000000);
+            break;
+
+        case RW610_PACKAGE_TYPE_BGA:
+            val = (((((int32_t)(temp_Cau_Raw_Reading)) * 480561) - 220707400) / 1000000);
+            break;
+
+        default:
+            PRINTF("Unknown board type, use BGA temperature \r\n");
+            val = (((((int32_t)(temp_Cau_Raw_Reading)) * 480561) - 220707400) / 1000000);
+            break;
+    }
+
+    return val;
+}
+
+int wifi_cau_temperature_write_to_firmware()
+{
+    int32_t val = 0;
+
+    val = wifi_get_temperature();
+    WIFI_WRITE_REG32(WLAN_CAU_TEMPERATURE_FW_ADDR, val);
+    return val;
+}
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+int wifi_set_indrst_cfg(const wifi_indrst_cfg_t *indrst_cfg, mlan_bss_type bss_type)
+{
+    int ret;
+    mlan_ds_misc_cfg misc;
+    mlan_ioctl_req req;
+
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+    misc.param.ind_rst_cfg.ir_mode  = indrst_cfg->ir_mode;
+    misc.param.ind_rst_cfg.gpio_pin = indrst_cfg->gpio_pin;
+
+    misc.sub_command       = (t_u32)MLAN_OID_MISC_IND_RST_CFG;
+    wm_wifi.cmd_resp_ioctl = &req;
+    req.pbuf               = (t_u8 *)&misc;
+    req.buf_len            = sizeof(mlan_ds_misc_cfg);
+    req.req_id             = (t_u32)MLAN_IOCTL_MISC_CFG;
+    req.action             = MLAN_ACT_SET;
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    {
+        req.bss_index = (t_u32)MLAN_BSS_TYPE_UAP;
+        ret           = (int)wlan_ops_uap_ioctl(mlan_adap, &req);
+    }
+    else
+    {
+        req.bss_index = (t_u32)MLAN_BSS_TYPE_STA;
+        ret           = (int)wlan_ops_sta_ioctl(mlan_adap, &req);
+    }
+
+    wm_wifi.cmd_resp_ioctl = NULL;
+    return ret;
+}
+
+int wifi_get_indrst_cfg(wifi_indrst_cfg_t *indrst_cfg, mlan_bss_type bss_type)
+{
+    int ret;
+    mlan_ds_misc_cfg misc;
+    mlan_ioctl_req req;
+    (void)memset(&misc, 0x00, sizeof(mlan_ds_misc_cfg));
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+
+    misc.sub_command = (t_u32)MLAN_OID_MISC_IND_RST_CFG;
+
+    wm_wifi.cmd_resp_ioctl = &req;
+    req.pbuf               = (t_u8 *)&misc;
+    req.buf_len            = sizeof(mlan_ds_misc_cfg);
+    req.req_id             = (t_u32)MLAN_IOCTL_MISC_CFG;
+    req.action             = MLAN_ACT_GET;
+
+    ret                    = (int)wlan_ops_sta_ioctl(mlan_adap, &req);
+    wm_wifi.cmd_resp_ioctl = NULL;
+
+    if (ret == WM_SUCCESS)
+    {
+        indrst_cfg->ir_mode  = misc.param.ind_rst_cfg.ir_mode;
+        indrst_cfg->gpio_pin = misc.param.ind_rst_cfg.gpio_pin;
+    }
+    return ret;
+}
+
+int wifi_test_independent_reset()
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    HostCmd_DS_IND_RST ind;
+    /** Action */
+    ind.action = 0;
+    /** CMD_SUBID */
+    ind.sub_id = 0x117;
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_STA);
+    cmd->result  = 0x0;
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_DBGS_CFG);
+    cmd->size    = sizeof(HostCmd_DS_IND_RST) + S_DS_GEN;
+    (void)memcpy(&cmd->params.ind_rst, &ind, sizeof(HostCmd_DS_IND_RST));
+
+    wifi_wait_for_cmdresp(NULL);
+    return WM_SUCCESS;
+}
+
+int wifi_trigger_oob_indrst()
+{
+    wlan_process_hang(FW_RELOAD_NO_EMULATION);
+
+    return WM_SUCCESS;
+}
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_init.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_init.c
new file mode 100644
index 0000000000..fbfbbaef1c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_init.c
@@ -0,0 +1,548 @@
+/** @file mlan_init.c
+ *
+ *  @brief  This file provides initialization for FW and HW
+ *
+ *  Copyright 2008-2021, 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    10/13/2008: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+#include "fsl_common.h"
+#ifndef __ZEPHYR__
+#ifndef RW610
+#include "sdmmc_config.h"
+#endif
+#endif
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+        Global Variables
+********************************************************/
+
+#ifdef __ZEPHYR__
+#define BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE 32
+#endif
+
+//_IOBUFS_ALIGNED(SDIO_DMA_ALIGNMENT)
+#if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177)
+static t_u8 mp_regs_buffer[MAX_MP_REGS + DMA_ALIGNMENT];
+#elif defined(SD8801)
+SDK_ALIGN(uint8_t mp_regs_buffer[MAX_MP_REGS], BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE);
+#endif
+
+/* We are allocating BSS list globally as we need heap for other purposes */
+SDK_ALIGN(BSSDescriptor_t BSS_List[MRVDRV_MAX_BSSID_LIST], 32);
+
+#if CONFIG_SCAN_CHANNEL_GAP
+
+#if !CONFIG_5GHz_SUPPORT
+static ChanStatistics_t Chan_Stats[14];
+#else
+static ChanStatistics_t Chan_Stats[48];
+#endif
+
+#endif
+
+/********************************************************
+        Local Functions
+********************************************************/
+
+/********************************************************
+        Global Functions
+********************************************************/
+
+/**
+ *  @brief This function allocates buffer for the members of adapter
+ *  		structure like command buffer and BSSID list.
+ *
+ *  @param pmadapter A pointer to mlan_adapter structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_allocate_adapter(pmlan_adapter pmadapter)
+{
+    (void)__memset(MNULL, &BSS_List, 0x00, sizeof(BSS_List));
+
+    pmadapter->pscan_table = BSS_List;
+#if CONFIG_SCAN_CHANNEL_GAP
+
+#if !CONFIG_5GHz_SUPPORT
+    pmadapter->num_in_chan_stats = 14;
+#else
+    pmadapter->num_in_chan_stats = 48;
+#endif
+    pmadapter->pchan_stats = Chan_Stats;
+#endif
+
+       /* wmsdk: Use a statically allocated DMA aligned buffer */
+#if defined(SD8801)
+    pmadapter->mp_regs = mp_regs_buffer;
+#elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177)
+    pmadapter->mp_regs = (t_u8 *)ALIGN_ADDR(mp_regs_buffer, DMA_ALIGNMENT);
+// mp_regs_buffer;
+#endif
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+void wlan_clear_scan_bss(void)
+{
+#if CONFIG_WPA_SUPP
+    BSSDescriptor_t *bss_entry = NULL;
+    int i;
+
+    for (i = 0; i < mlan_adap->num_in_scan_table; i++)
+    {
+        bss_entry = &mlan_adap->pscan_table[i];
+        if (bss_entry && bss_entry->ies != NULL)
+        {
+            OSA_MemoryFree(bss_entry->ies);
+        }
+    }
+#endif
+    (void)__memset(MNULL, &BSS_List, 0x00, sizeof(BSS_List));
+}
+
+/**
+ *  @brief This function initializes the private structure
+ *  		and sets default values to the members of mlan_private.
+ *
+ *  @param priv    A pointer to mlan_private structure
+ *
+ *  @return        MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_init_priv(pmlan_private priv)
+{
+    t_u32 i;
+    /* pmlan_adapter pmadapter = priv->adapter; */
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    priv->media_connected = MFALSE;
+    (void)__memset(pmadapter, priv->curr_addr, 0xff, MLAN_MAC_ADDR_LENGTH);
+
+    priv->pkt_tx_ctrl = 0;
+    priv->bss_mode    = MLAN_BSS_MODE_INFRA;
+
+    priv->data_rate         = 0; /* Initially indicate the rate as auto */
+    priv->data_rate_index   = (t_s8)-1;
+    priv->is_data_rate_auto = MTRUE;
+    priv->bcn_avg_factor    = DEFAULT_BCN_AVG_FACTOR;
+    priv->data_avg_factor   = DEFAULT_DATA_AVG_FACTOR;
+
+    priv->sec_info.wep_status          = Wlan802_11WEPDisabled;
+    priv->sec_info.authentication_mode = MLAN_AUTH_MODE_AUTO;
+    priv->sec_info.encryption_mode     = MLAN_ENCRYPTION_MODE_NONE;
+    for (i = 0; i < sizeof(priv->wep_key) / sizeof(priv->wep_key[0]); i++)
+    {
+        (void)__memset(pmadapter, &priv->wep_key[i], 0, sizeof(mrvl_wep_key_t));
+    }
+    priv->wep_key_curr_index = 0;
+    priv->ewpa_query         = MFALSE;
+    priv->adhoc_aes_enabled  = MFALSE;
+    priv->curr_pkt_filter =
+#if CONFIG_11AC
+        HostCmd_ACT_MAC_STATIC_DYNAMIC_BW_ENABLE |
+#endif
+        HostCmd_ACT_MAC_RTS_CTS_ENABLE | HostCmd_ACT_MAC_RX_ON | HostCmd_ACT_MAC_TX_ON |
+        HostCmd_ACT_MAC_ETHERNETII_ENABLE;
+
+#if CONFIG_GTK_REKEY_OFFLOAD
+    (void)__memset(pmadapter, &priv->gtk_rekey, 0, sizeof(priv->gtk_rekey));
+#endif
+    (void)__memset(pmadapter, &priv->curr_bss_params, 0, sizeof(priv->curr_bss_params));
+    priv->listen_interval = MLAN_DEFAULT_LISTEN_INTERVAL;
+    wlan_11d_priv_init(priv);
+    wlan_11h_priv_init(priv);
+
+    priv->uap_bss_started = MFALSE;
+    (void)__memset(pmadapter, &priv->uap_state_chan_cb, 0, sizeof(priv->uap_state_chan_cb));
+    priv->num_drop_pkts = 0;
+
+    priv->wpa_is_gtk_set = MFALSE;
+
+#ifdef RW610
+    priv->tx_bf_cap = DEFAULT_11N_TX_BF_CAP;
+#else
+    priv->tx_bf_cap = 0;
+#endif
+    priv->wmm_required = MTRUE;
+    priv->wmm_enabled  = MFALSE;
+    priv->wmm_qosinfo  = 0;
+    priv->pmfcfg.mfpc = 0;
+    priv->pmfcfg.mfpr = 0;
+
+#if CONFIG_11K
+    priv->enable_host_11k = (t_u8)MFALSE;
+#endif
+#if CONFIG_11K
+    priv->neighbor_rep_token    = (t_u8)1U;
+    priv->rrm_mgmt_bitmap_index = -1;
+#endif
+#if CONFIG_11V
+    priv->bss_trans_query_token = (t_u8)1U;
+#endif
+    for (i = 0; i < MAX_NUM_TID; i++)
+    {
+        priv->addba_reject[i] = ADDBA_RSP_STATUS_ACCEPT;
+    }
+    priv->max_amsdu = 0;
+
+    priv->scan_block = MFALSE;
+
+    if (GET_BSS_ROLE(priv) == (unsigned)MLAN_BSS_ROLE_STA)
+    {
+        priv->port_ctrl_mode = MTRUE;
+    }
+    else
+    {
+        priv->port_ctrl_mode = MFALSE;
+    }
+    priv->port_open = MFALSE;
+#if CONFIG_ROAMING
+    priv->roaming_enabled = MFALSE;
+#endif
+
+    priv->uap_bss_started = MFALSE;
+    priv->uap_host_based  = MFALSE;
+
+#if CONFIG_WPA_SUPP
+    reset_ie_index();
+    priv->default_scan_ies_len = 0;
+    priv->probe_req_index      = -1;
+#if CONFIG_WPA_SUPP_WPS
+    priv->wps.wps_mgmt_bitmap_index = -1;
+#endif
+#if CONFIG_WPA_SUPP_AP
+    priv->beacon_vendor_index = -1;
+    priv->beacon_index        = 0;
+    priv->proberesp_index     = 1;
+    priv->assocresp_index     = 2;
+    priv->beacon_wps_index    = 3;
+#endif
+#endif
+#if CONFIG_TCP_ACK_ENH
+    priv->enable_tcp_ack_enh = MTRUE;
+#endif
+
+#if CONFIG_WPA_SUPP_DPP
+    priv->is_dpp_connect = MFALSE;
+#endif
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function initializes the adapter structure
+ *  		and sets default values to the members of adapter.
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *
+ *  @return		N/A
+ */
+t_void wlan_init_adapter(pmlan_adapter pmadapter)
+{
+    pmadapter->mp_rd_bitmap = 0;
+
+    /*
+     * wmsdk: fixme: Originally mp_wr_bitmap was set to 0. We have changed
+     * it only for legacy reason. Please check it and restore on high
+     * priority.
+     */
+    pmadapter->mp_wr_bitmap = 0;
+#ifndef RW610
+#if defined(SD8801)
+    pmadapter->curr_rd_port = 1;
+    pmadapter->curr_wr_port = 1;
+#elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177)
+    pmadapter->curr_rd_port      = 0;
+    pmadapter->curr_wr_port      = 0;
+#endif
+    pmadapter->mp_data_port_mask = DATA_PORT_MASK;
+#endif
+
+    /* Scan type */
+    pmadapter->scan_type = MLAN_SCAN_TYPE_ACTIVE;
+    /* Scan mode */
+    pmadapter->scan_mode = HostCmd_BSS_MODE_ANY;
+    /* Scan time */
+    pmadapter->specific_scan_time = MRVDRV_SPECIFIC_SCAN_CHAN_TIME;
+    pmadapter->active_scan_time   = MRVDRV_ACTIVE_SCAN_CHAN_TIME;
+    pmadapter->passive_scan_time  = MRVDRV_PASSIVE_SCAN_CHAN_TIME;
+
+    pmadapter->num_in_scan_table = 0;
+
+    pmadapter->ecsa_enable = MFALSE;
+
+    /* fixme: enable this later when required */
+#if CONFIG_EXT_SCAN_SUPPORT
+    pmadapter->ext_scan = 1;
+#endif
+    pmadapter->scan_probes = DEFAULT_PROBES;
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    pmadapter->rssi_threshold = 0;
+#endif
+
+    /* fixme: enable this later when required */
+    pmadapter->multiple_dtim         = MRVDRV_DEFAULT_MULTIPLE_DTIM;
+    pmadapter->local_listen_interval = 0; /* default value in firmware
+                                             will be used */
+
+    pmadapter->delay_to_ps       = DELAY_TO_PS_DEFAULT;
+    pmadapter->enhanced_ps_mode  = PS_MODE_AUTO;
+    pmadapter->bcn_miss_time_out = DEFAULT_BCN_MISS_TIMEOUT;
+
+#if CONFIG_WMM_UAPSD
+    pmadapter->gen_null_pkt   = MFALSE; /* Disable NULL Pkt generation-default */
+    pmadapter->pps_uapsd_mode = MFALSE; /* Disable pps/uapsd mode -default */
+#endif
+#if CONFIG_HOST_SLEEP
+    pmadapter->is_hs_configured          = MFALSE;
+    pmadapter->mgmt_filter[0].action     = 0;      /* discard and not wakeup host */
+    pmadapter->mgmt_filter[0].type       = 0xff;   /* management frames */
+    pmadapter->mgmt_filter[0].frame_mask = 0x1400; /* Frame-Mask bits :
+                                                      : Bit 0 - Association Request
+                                                      : Bit 1 - Association Response
+                                                      : Bit 2 - Re-Association Request
+                                                      : Bit 3 - Re-Association Response
+                                                      : Bit 4 - Probe Request
+                                                      : Bit 5 - Probe Response
+                                                      : Bit 8 - Beacon Frames
+                                                      : Bit 10 - Disassociation
+                                                      : Bit 11 - Authentication
+                                                      : Bit 12 - Deauthentication
+                                                      : Bit 13 - Action Frames
+                                                   */
+#endif
+
+    pmadapter->hw_dot_11n_dev_cap     = 0;
+    pmadapter->hw_dev_mcs_support     = 0;
+    pmadapter->usr_dot_11n_dev_cap_bg = 0;
+    pmadapter->usr_dot_11n_dev_cap_a  = 0;
+    pmadapter->usr_dev_mcs_support    = 0;
+    pmadapter->chan_bandwidth    = 0;
+    pmadapter->adhoc_11n_enabled = MFALSE;
+
+    pmadapter->hw_dot_11ac_dev_cap       = 0;
+    pmadapter->hw_dot_11ac_mcs_support   = 0;
+    pmadapter->usr_dot_11ac_opermode_bw  = 0;
+    pmadapter->usr_dot_11ac_opermode_nss = 0;
+#if CONFIG_WIFI_CAPA
+    pmadapter->usr_dot_11n_enable = MFALSE;
+#if CONFIG_11AC
+    pmadapter->usr_dot_11ac_enable = MFALSE;
+#endif
+#if CONFIG_11AX
+    pmadapter->usr_dot_11ax_enable = MFALSE;
+#endif
+#endif
+
+    /* Initialize 802.11d */
+    wlan_11d_init(pmadapter);
+    wlan_11h_init(pmadapter);
+
+    wlan_wmm_init(pmadapter);
+    wlan_init_wmm_param(pmadapter);
+#if CONFIG_WMM_UAPSD
+    (void)__memset(pmadapter, &pmadapter->sleep_params, 0, sizeof(pmadapter->sleep_params));
+    (void)__memset(pmadapter, &pmadapter->sleep_period, 0, sizeof(pmadapter->sleep_period));
+
+    pmadapter->tx_lock_flag = MFALSE;
+#endif /* CONFIG_WMM_UAPSD */
+    pmadapter->null_pkt_interval = 0;
+    pmadapter->fw_bands          = 0U;
+    pmadapter->config_bands      = 0U;
+    pmadapter->adhoc_start_band  = 0U;
+    /* pmadapter->pscan_channels = MNULL; */
+    pmadapter->fw_release_number = 0;
+    pmadapter->fw_cap_info       = 0;
+    (void)__memset(pmadapter, &pmadapter->region_channel, 0, sizeof(pmadapter->region_channel));
+    pmadapter->region_code = MRVDRV_DEFAULT_REGION_CODE;
+    (void)__memcpy(pmadapter, pmadapter->country_code, MRVDRV_DEFAULT_COUNTRY_CODE, COUNTRY_CODE_LEN);
+    pmadapter->adhoc_awake_period = 0;
+    pmadapter->ps_state           = PS_STATE_AWAKE;
+    return;
+}
+
+/**
+ *  @brief This function intializes the lock variables and
+ *  the list heads.
+ *
+ *  @param pmadapter  A pointer to a mlan_adapter structure
+ *
+ *  @return           MLAN_STATUS_SUCCESS -- on success,
+ *                    otherwise MLAN_STATUS_FAILURE
+ *
+ */
+mlan_status wlan_init_lock_list(IN pmlan_adapter pmadapter)
+{
+    mlan_status ret    = MLAN_STATUS_SUCCESS;
+    pmlan_private priv = MNULL;
+    /* pmlan_callbacks pcb = &pmadapter->callbacks; */
+    t_u8 i = 0;
+    t_u8 j = 0;
+
+    ENTER();
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        if (pmadapter->priv[i] != NULL)
+        {
+            priv = pmadapter->priv[i];
+            for (j = 0; j < MAX_NUM_TID; ++j)
+            {
+                util_init_list_head((t_void *)pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[j].ra_list, MTRUE,
+                                    priv->adapter->callbacks.moal_init_lock);
+            }
+
+#if CONFIG_WMM
+            /* wmm enhanced reuses 4 ac xmit queues */
+            for (j = 0; j < MAX_AC_QUEUES; ++j)
+            {
+                if (priv->adapter->callbacks.moal_init_semaphore(pmadapter->pmoal_handle, "ra_list_sem",
+                                                                 &priv->wmm.tid_tbl_ptr[j].ra_list.plock) !=
+                    MLAN_STATUS_SUCCESS)
+                {
+                    wifi_e("Create ra_list_sem failed");
+                    ret = MLAN_STATUS_FAILURE;
+                    goto done;
+                }
+#if CONFIG_WMM_DEBUG
+                util_init_list_head((t_void *)pmadapter->pmoal_handle, &priv->wmm.hist_ra[j], MFALSE, MNULL);
+#endif
+            }
+#endif
+
+            ret = (mlan_status)OSA_MutexCreate((osa_mutex_handle_t)priv->tx_ba_stream_tbl_lock);
+            if (ret != MLAN_STATUS_SUCCESS)
+            {
+                wifi_e("Create Tx BA tbl sem failed");
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+
+            util_init_list_head((t_void *)pmadapter->pmoal_handle, &priv->tx_ba_stream_tbl_ptr, MTRUE,
+                                pmadapter->callbacks.moal_init_lock);
+
+            ret = (mlan_status)OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)priv->rx_reorder_tbl_lock);
+            if (ret != MLAN_STATUS_SUCCESS)
+            {
+                wifi_e("Create Rx Reorder tbl lock failed");
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+            OSA_SemaphorePost((osa_semaphore_handle_t)priv->rx_reorder_tbl_lock);
+            util_init_list_head((t_void *)pmadapter->pmoal_handle, &priv->rx_reorder_tbl_ptr, MTRUE,
+                                pmadapter->callbacks.moal_init_lock);
+
+            util_scalar_init((t_void *)pmadapter->pmoal_handle, &priv->wmm.tx_pkts_queued, 0,
+                             priv->wmm.ra_list_spinlock, pmadapter->callbacks.moal_init_lock);
+            util_scalar_init((t_void *)pmadapter->pmoal_handle, &priv->wmm.highest_queued_prio, HIGH_PRIO_TID,
+                             priv->wmm.ra_list_spinlock, pmadapter->callbacks.moal_init_lock);
+            util_init_list_head((t_void *)pmadapter->pmoal_handle, &priv->sta_list, MTRUE,
+                                pmadapter->callbacks.moal_init_lock);
+        }
+    }
+
+done:
+    /* error: */
+    if (ret != MLAN_STATUS_SUCCESS)
+    {
+        for (i = 0; i < pmadapter->priv_num; i++)
+        {
+            priv = pmadapter->priv[i];
+#if CONFIG_WMM
+            for (j = 0; j < MAX_AC_QUEUES; ++j)
+            {
+                if ((uint32_t *)(*(uint32_t *)priv->wmm.tid_tbl_ptr[j].ra_list.plock) != NULL)
+                    priv->adapter->callbacks.moal_free_semaphore(
+                        pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[j].ra_list.plock);
+            }
+#endif
+            if ((uint32_t *)(*(uint32_t *)priv->tx_ba_stream_tbl_lock) != NULL)
+                OSA_MutexDestroy((osa_mutex_handle_t)priv->tx_ba_stream_tbl_lock);
+            if ((uint32_t *)(*(uint32_t *)priv->rx_reorder_tbl_lock) != NULL)
+                OSA_SemaphoreDestroy((osa_semaphore_handle_t)priv->rx_reorder_tbl_lock);
+        }
+    }
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief  This function initializes firmware
+ *
+ *  @param pmadapter		A pointer to mlan_adapter
+ *
+ *  @return		MLAN_STATUS_SUCCESS, MLAN_STATUS_PENDING or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_init_fw(IN pmlan_adapter pmadapter)
+{
+    mlan_status ret    = MLAN_STATUS_SUCCESS;
+    pmlan_private priv = MNULL;
+    t_u8 i             = 0;
+
+    ENTER();
+
+    /* Initialize adapter structure */
+    wlan_init_adapter(pmadapter);
+
+    for (i = 0; i < pmadapter->priv_num; i++)
+    {
+        if (pmadapter->priv[i] != NULL)
+        {
+            priv = pmadapter->priv[i];
+
+            /* Initialize private structure */
+            if ((ret = wlan_init_priv(priv)) != MLAN_STATUS_SUCCESS)
+            {
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+        }
+    }
+        /* Issue firmware initialize commands for first BSS, for other
+           interfaces it will be called after getting the last init command
+           response of previous interface */
+done:
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function frees the structure of adapter
+ *
+ *  @param pmadapter      A pointer to mlan_adapter structure
+ *
+ *  @return             N/A
+ */
+t_void wlan_free_adapter(pmlan_adapter pmadapter)
+{
+    ENTER();
+
+    if (!pmadapter)
+    {
+        PRINTM(MERROR, "The adapter is NULL\n");
+        LEAVE();
+        return;
+    }
+
+
+    LEAVE();
+    return;
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_join.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_join.c
new file mode 100644
index 0000000000..db3a15ecda
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_join.c
@@ -0,0 +1,1555 @@
+/** @file mlan_join.c
+ *
+ *  @brief  This file provides Functions implementing wlan infrastructure
+ *  and adhoc join routines IOCTL handlers as well as command preparation
+ *  and response routines for sending adhoc start, adhoc join, and
+ *  association commands to the firmware.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/30/2008: initial version
+******************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+#if CONFIG_WPS2
+#include "wifi_nxp_wps.h"
+#endif
+/********************************************************
+                Local Constants
+********************************************************/
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+/**
+ *  @brief Append a generic IE as a pass through TLV to a TLV buffer.
+ *
+ *  This function is called from the network join command prep. routine.
+ *    If the IE buffer has been setup by the application, this routine appends
+ *    the buffer as a pass through TLV type to the request.
+ *
+ *  @param priv     A pointer to mlan_private structure
+ *  @param ppbuffer pointer to command buffer pointer
+ *
+ *  @return         bytes added to the buffer
+ */
+static int wlan_cmd_append_generic_ie(mlan_private *priv, t_u8 **ppbuffer)
+{
+    int ret_len = 0;
+    MrvlIEtypesHeader_t ie_header;
+
+    ENTER();
+
+    /* Null Checks */
+    if (ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    if (*ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+
+    /*
+     * If there is a generic ie buffer setup, append it to the return
+     *   parameter buffer pointer.
+     */
+    if (priv->gen_ie_buf_len)
+    {
+        PRINTM(MINFO, "append generic IE %d to %p\n", priv->gen_ie_buf_len, *ppbuffer);
+
+        /* Wrap the generic IE buffer with a pass through TLV type */
+        ie_header.type = wlan_cpu_to_le16(TLV_TYPE_PASSTHROUGH);
+        ie_header.len  = wlan_cpu_to_le16(priv->gen_ie_buf_len);
+        (void)__memcpy(priv->adapter, *ppbuffer, &ie_header, sizeof(ie_header));
+
+        /* Increment the return size and the return buffer pointer param */
+        *ppbuffer += sizeof(ie_header);
+        ret_len += sizeof(ie_header);
+
+        /* Copy the generic IE buffer to the output buffer, advance pointer */
+        (void)__memcpy(priv->adapter, *ppbuffer, priv->gen_ie_buf, priv->gen_ie_buf_len);
+
+        /* Increment the return size and the return buffer pointer param */
+        *ppbuffer += priv->gen_ie_buf_len;
+        ret_len += priv->gen_ie_buf_len;
+
+        /* Reset the generic IE buffer */
+        priv->gen_ie_buf_len = 0;
+    }
+
+    /* return the length appended to the buffer */
+    LEAVE();
+    return ret_len;
+}
+
+
+/**
+ *  @brief This function finds out the common rates between rate1 and rate2.
+ *
+ *  It will fill common rates in rate1 as output if found.
+ *
+ *  NOTE: Setting the MSB of the basic rates needs to be taken
+ *   care of, either before or after calling this function
+ *
+ *  @param pmpriv      A pointer to mlan_private structure
+ *  @param rate1       the buffer which keeps input and output
+ *  @param rate1_size  the size of rate1 buffer
+ *  @param rate2       the buffer which keeps rate2
+ *  @param rate2_size  the size of rate2 buffer.
+ *
+ *  @return            MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_get_common_rates(
+    IN mlan_private *pmpriv, IN t_u8 *rate1, IN t_u32 rate1_size, IN t_u8 *rate2, IN t_u32 rate2_size)
+{
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+#if !CONFIG_MEM_POOLS
+    mlan_callbacks *pcb = (mlan_callbacks *)&pmpriv->adapter->callbacks;
+#endif
+    t_u8 *ptr = rate1;
+    t_u8 *tmp = MNULL;
+    t_u32 i, j;
+
+    ENTER();
+
+#if !CONFIG_MEM_POOLS
+    ret = pcb->moal_malloc(pmpriv->adapter->pmoal_handle, rate1_size, MLAN_MEM_DEF, &tmp);
+    if (ret != MLAN_STATUS_SUCCESS || (tmp == MNULL))
+#else
+    tmp = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+    if (tmp == MNULL)
+#endif
+    {
+        PRINTM(MERROR, "Failed to allocate buffer\n");
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+
+    (void)__memcpy(pmpriv->adapter, tmp, rate1, rate1_size);
+    (void)__memset(pmpriv->adapter, rate1, 0, rate1_size);
+
+    for (i = 0; rate2[i] && i < rate2_size; i++)
+    {
+        for (j = 0; tmp[j] && j < rate1_size; j++)
+        {
+            /* Check common rate, excluding the bit for basic rate */
+            if ((rate2[i] & 0x7FU) == (tmp[j] & 0x7FU))
+            {
+                *rate1++ = tmp[j];
+                break;
+            }
+        }
+    }
+
+    HEXDUMP("rate1 (AP) Rates", tmp, rate1_size);
+    HEXDUMP("rate2 (Card) Rates", rate2, rate2_size);
+    HEXDUMP("Common Rates", ptr, rate1 - ptr);
+    PRINTM(MINFO, "Tx DataRate is set to 0x%X\n", pmpriv->data_rate);
+
+    if (!pmpriv->is_data_rate_auto)
+    {
+        while (*ptr != 0U)
+        {
+            if ((*ptr & 0x7fU) == pmpriv->data_rate)
+            {
+                ret = MLAN_STATUS_SUCCESS;
+                goto done;
+            }
+            ptr++;
+        }
+        PRINTM(MMSG,
+               "Previously set fixed data rate %#x is not "
+               "compatible with the network\n",
+               pmpriv->data_rate);
+
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+
+    ret = MLAN_STATUS_SUCCESS;
+done:
+    if (tmp != MNULL)
+    {
+#if !CONFIG_MEM_POOLS
+        (void)pcb->moal_mfree(pmpriv->adapter->pmoal_handle, tmp);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, tmp);
+#endif
+    }
+
+    LEAVE();
+    return ret;
+}
+
+#if 0
+/**
+ *  @brief Create the intersection of the rates supported by a target BSS and
+ *         our pmadapter settings for use in an assoc/join command.
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param pbss_desc        BSS Descriptor whose rates are used in the setup
+ *  @param pout_rates       Output: Octet array of rates common between the BSS
+ *                          and the pmadapter supported rates settings
+ *  @param pout_rates_size  Output: Number of rates/octets set in pout_rates
+ *
+ *  @return                 MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_setup_rates_from_bssdesc(IN mlan_private *pmpriv,
+                                                 IN BSSDescriptor_t *pbss_desc,
+                                                 OUT t_u8 *pout_rates,
+                                                 OUT t_u32 *pout_rates_size)
+{
+    t_u8 card_rates[WLAN_SUPPORTED_RATES] = {0x0};
+    t_u32 card_rates_size                 = 0;
+    ENTER();
+
+    (void)__memset(pmadapter, card_rates, 0x00, WLAN_SUPPORTED_RATES);
+    /* Copy AP supported rates */
+    (void)__memcpy(pmpriv->adapter, pout_rates, pbss_desc->supported_rates, WLAN_SUPPORTED_RATES);
+    /* Get the STA supported rates */
+    card_rates_size = wlan_get_active_data_rates(pmpriv, pmpriv->bss_mode, pmpriv->config_bands, card_rates);
+    /* Get the common rates between AP and STA supported rates */
+    if (wlan_get_common_rates(pmpriv, pout_rates, WLAN_SUPPORTED_RATES, card_rates, card_rates_size) !=
+        MLAN_STATUS_SUCCESS)
+    {
+        *pout_rates_size = 0;
+        PRINTM(MERROR, "wlan_get_common_rates failed\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    *pout_rates_size = MIN(wlan_strlen((char *)pout_rates), WLAN_SUPPORTED_RATES);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/**
+ *  @brief Create the intersection of the rates supported by a target BSS and
+ *         our pmadapter settings for use in an assoc/join command.
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param pbss_desc        BSS Descriptor whose rates are used in the setup
+ *  @param pout_rates       Output: Octet array of rates common between the BSS
+ *                          and the pmadapter supported rates settings
+ *  @param pout_rates_size  Output: Number of rates/octets set in pout_rates
+ *
+ *  @return                 MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_setup_rates_from_bssdesc(mlan_private *pmpriv,
+                                                 BSSDescriptor_t *pbss_desc,
+                                                 t_u8 *pout_rates,
+                                                 t_u32 *pout_rates_size)
+{
+    t_u8 card_rates[WLAN_SUPPORTED_RATES] = {0};
+    t_u32 card_rates_size                 = 0;
+    ENTER();
+    /* Copy AP supported rates */
+    (void)__memcpy(pmpriv->adapter, pout_rates, pbss_desc->supported_rates, WLAN_SUPPORTED_RATES);
+
+    if ((pmpriv->adapter->region_code == COUNTRY_CODE_JP_40 || pmpriv->adapter->region_code == COUNTRY_CODE_JP_FF) &&
+        (pbss_desc->phy_param_set.ds_param_set.current_chan == 14))
+    {
+        /* Special Case: For Japan, 11G rates on CH14 are not allowed*/
+        card_rates_size = wlan_get_supported_rates(pmpriv, pmpriv->bss_mode, BAND_B, card_rates);
+    }
+    else
+    {
+        /* Get the STA supported rates */
+        card_rates_size = wlan_get_supported_rates(pmpriv, pmpriv->bss_mode, pmpriv->config_bands, card_rates);
+    }
+    /* Get the common rates between AP and STA supported rates */
+    if (wlan_get_common_rates(pmpriv, pout_rates, WLAN_SUPPORTED_RATES, card_rates, card_rates_size))
+    {
+        *pout_rates_size = 0;
+        PRINTM(MERROR, "wlan_get_common_rates failed\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    *pout_rates_size = MIN(wlan_strlen((char *)pout_rates), WLAN_SUPPORTED_RATES);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+/**
+ *  @brief This function updates RSN IE in the association request.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *
+ *  @param ptlv_rsn_ie       A pointer to rsn_ie TLV
+ */
+static int wlan_update_rsn_ie(mlan_private *pmpriv,
+                              MrvlIEtypes_RsnParamSet_t *ptlv_rsn_ie,
+                              t_u16 *rsn_ie_len,
+                              t_u8 *akm_type)
+{
+    t_u16 *prsn_cap;
+    t_u8 *ptr;
+    t_u8 *pairwise_cipher_count_ptr;
+    t_u8 *group_mgmt_cipher_suite_ptr = MNULL;
+    t_u8 *pmkid_list_ptr              = MNULL;
+    t_u8 *end_ptr;
+    t_u16 pmf_mask              = 0x00;
+    t_u16 pairwise_cipher_count = 0;
+    t_u16 akm_suite_count       = 0;
+    t_u16 pmkid_count           = 0;
+    t_u8 i;
+
+#define PREFERENCE_TKIP 1
+    /* Cipher Perference Order:
+       (5) CIPHER_SYITE_TYPE_GCMP_256 = 9
+       (4) CIPHER_SYITE_TYPE_GCMP_128 = 8
+       (3) CIPHER_SYITE_TYPE_CCMP_256 = 10
+       (2) CIPHER_SYITE_TYPE_CCMP_128 = 4
+       (1) CIPHER_SYITE_TYPE_TKIP     = 2
+       (0) Skip
+    */
+    t_u8 preference_selected;
+    t_u8 cipher_selected_id;
+#if CONFIG_WPA_SUPP
+    t_u8 cipher_preference[11] = {0, 0, 1, 0, 2, 0, 0, 0, 4, 5, 3};
+#else
+    t_u8 cipher_preference[5] = {0, 0, 1, 0, 2};
+#endif
+    t_u8 oui[4] = {0x00, 0x0f, 0xac, 0x00};
+
+    /* AKM Perference Order:
+       (13) AKM_SUITE_TYPE_SAE_EXT_KEY       = 24
+       (12) AKM_SUITE_TYPE_1X_SUITEB_FT_SHA384  = 13
+       (11) AKM_SUITE_TYPE_1X_SUITEB_SHA384  = 12
+       (10) AKM_SUITE_TYPE_1X_SUITEB_SHA256  = 11
+       (9) AKM_SUITE_TYPE_1X_FT  = 3
+       (8) AKM_SUITE_TYPE_1X_SHA256  = 5
+       (7) AKM_SUITE_TYPE_1X         = 1
+       (6) AKM_SUITE_TYPE_FT_SAE     = 9   //Not supported in esupp
+       (5) AKM_SUITE_TYPE_SAE        = 8
+       (4) AKM_SUITE_TYPE_OWE        = 18
+       (3) AKM_SUITE_TYPE_FT_PSK     = 4   //Not supported in esupp
+       (2) AKM_SUITE_TYPE_PSK_SHA256 = 6
+       (1) AKM_SUITE_TYPE_PSK        = 2
+       (0) Skip
+    */
+    t_u8 akm_type_selected;
+    t_u8 akm_type_id        = 0;
+#if CONFIG_11R
+    t_u8 akm_preference[25] = {0, 7, 1, 9, 3, 8, 2, 0, 5, 6, 0, 10, 11, 12, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 13};
+#else
+    t_u8 akm_preference[25] = {0, 7, 1, 0, 0, 8, 2, 0, 5, 0, 0, 10, 11, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 13};
+#endif
+
+    int ap_mfpc = 0, ap_mfpr = 0, ret = MLAN_STATUS_SUCCESS;
+
+    pmf_mask = (((pmpriv->pmfcfg.mfpc << MFPC_BIT) | (pmpriv->pmfcfg.mfpr << MFPR_BIT)) | (~PMF_MASK));
+    /* prsn_cap = prsn_ie->rsn_ie + 2 bytes version + 4 bytes
+     * group_cipher_suite + 2 bytes pairwise_cipher_count +
+     * pairwise_cipher_count * PAIRWISE_CIPHER_SUITE_LEN + 2 bytes
+     * akm_suite_count + akm_suite_count * AKM_SUITE_LEN
+     */
+    end_ptr = ptlv_rsn_ie->rsn_ie + *rsn_ie_len;
+
+    ptr = ptlv_rsn_ie->rsn_ie + sizeof(t_u16) + 4 * sizeof(t_u8);
+
+    pairwise_cipher_count_ptr = ptr;
+    pairwise_cipher_count     = wlan_le16_to_cpu(*(t_u16 *)ptr);
+    ptr += sizeof(t_u16);
+
+    preference_selected = 0;
+    cipher_selected_id  = 0;
+    for (i = 0; i < pairwise_cipher_count; i++)
+    {
+        if ((ptr[3] < sizeof(cipher_preference)) && (cipher_preference[ptr[3]] > preference_selected))
+        {
+            preference_selected = cipher_preference[ptr[3]];
+            cipher_selected_id  = ptr[3];
+        }
+        ptr += PAIRWISE_CIPHER_SUITE_LEN;
+    }
+
+    if (preference_selected == 0)
+    {
+        PRINTM(MERROR, "RSNE: PAIRWISE_CIPHER not supported\n");
+        return MLAN_STATUS_FAILURE;
+    }
+    if ((preference_selected == PREFERENCE_TKIP) && ((*akm_type == AssocAgentAuth_Wpa3Sae)
+#if CONFIG_DRIVER_OWE
+                                                     || (*akm_type == AssocAgentAuth_Owe)))
+    {
+#else
+                                                         ))
+    {
+#endif
+        PRINTM(MERROR, "RSNE: PAIRWISE_CIPHER TKIP not allowed for AKM %s\n",
+               (*akm_type == AssocAgentAuth_Wpa3Sae) ? "SAE" : "OWE");
+        return MLAN_STATUS_FAILURE;
+    }
+    if ((preference_selected == PREFERENCE_TKIP) && (*akm_type == AssocAgentAuth_Auto))
+    {
+        *akm_type = AssocAgentAuth_Open;
+    }
+    /* Process AKM
+     * Preference order for AssocAgentAuth_Auto:
+     *  FT Authentication using SAE 00-0F-AC:9  (not supported in embedded supplicant)
+     *  SAE Authentication 00-0F-AC:8
+     *  OWE Authentication 00-0F-AC:18
+     *  FT Authentication using PSK 00-0F-AC:4  (not supported in embedded supplicant)
+     *  PSK using SHA-256 00-0F-AC:6
+     *  PSK 00-0F-AC:2
+     */
+    ptr = ptlv_rsn_ie->rsn_ie + sizeof(t_u16) + 4 * sizeof(t_u8) + sizeof(t_u16) +
+          pairwise_cipher_count * PAIRWISE_CIPHER_SUITE_LEN;
+    akm_suite_count = wlan_le16_to_cpu(*(t_u16 *)ptr);
+    ptr += sizeof(t_u16); // move pointer to AKM suite
+
+    akm_type_selected = 0;
+
+    if (*akm_type == AssocAgentAuth_Auto)
+    {
+        // find the best one
+        for (i = 0; i < akm_suite_count; i++)
+        {
+            if ((ptr[3] < sizeof(akm_preference)) && (akm_preference[ptr[3]] > akm_type_selected))
+            {
+                akm_type_selected = akm_preference[ptr[3]];
+                akm_type_id       = ptr[3];
+            }
+            ptr += AKM_SUITE_LEN;
+        }
+        if (akm_type_selected)
+        {
+            if (akm_type_id == 6)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+            else if (akm_type_id == 1)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+            else if (akm_type_id == 3)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+            else if (akm_type_id == 5)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+            else if (akm_type_id == 11)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+            else if (akm_type_id == 12)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+            else if (akm_type_id == 13)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+            else if (akm_type_id == 2)
+            {
+                *akm_type = AssocAgentAuth_Open;
+            }
+#if CONFIG_11R
+            else if (akm_type_id == 4)
+            {
+                *akm_type = AssocAgentAuth_FastBss;
+            }
+#endif
+#if CONFIG_DRIVER_OWE
+            else if (akm_type_id == 18)
+            {
+                *akm_type = AssocAgentAuth_Owe;
+            }
+#endif
+            else if (akm_type_id == 8 || akm_type_id == 24)
+            {
+                *akm_type = AssocAgentAuth_Wpa3Sae;
+            }
+#if CONFIG_11R
+            else if (akm_type_id == 9)
+            {
+                *akm_type = AssocAgentAuth_FastBss_SAE;
+            }
+#endif
+        }
+    }
+    else
+    {
+        // find the matched AKM
+
+        for (i = 0; i < akm_suite_count; i++)
+        {
+            if (ptr[3] < sizeof(akm_preference))
+            {
+#if CONFIG_11R
+                if ((*akm_type == AssocAgentAuth_FastBss_Skip) && (ptr[3] == 13))
+                {
+                    break;
+                }
+                else
+#endif
+                    if ((*akm_type == AssocAgentAuth_Open) && (ptr[3] == 12))
+                {
+                    break;
+                }
+                else if ((*akm_type == AssocAgentAuth_Open) && (ptr[3] == 11))
+                {
+                    break;
+                }
+#if CONFIG_11R
+                else if ((*akm_type == AssocAgentAuth_FastBss_Skip) && (ptr[3] == 3))
+                {
+                    break;
+                }
+#endif
+                else if ((*akm_type == AssocAgentAuth_Open) && (ptr[3] == 5))
+                {
+                    break;
+                }
+                else if ((*akm_type == AssocAgentAuth_Open) && (ptr[3] == 1))
+                {
+                    break;
+                }
+#if CONFIG_11R
+                else if ((*akm_type == AssocAgentAuth_FastBss_Skip) && (ptr[3] == 9))
+                {
+                    break;
+                }
+#endif
+                else if ((*akm_type == AssocAgentAuth_Wpa3Sae) && (ptr[3] == 8 || ptr[3] == 24))
+                {
+                    break;
+                }
+#if CONFIG_DRIVER_OWE
+                else if ((*akm_type == AssocAgentAuth_Owe) && (ptr[3] == 18))
+                {
+                    break;
+                }
+#endif
+#if CONFIG_11R
+                else if ((*akm_type == AssocAgentAuth_FastBss_Skip) && (ptr[3] == 4))
+                {
+                    break;
+                }
+#endif
+                if ((*akm_type == AssocAgentAuth_Open) && (ptr[3] == 6))
+                {
+                    break;
+                }
+                else if ((*akm_type == AssocAgentAuth_Open) && (ptr[3] == 2))
+                {
+                    break;
+                }
+            }
+            ptr += AKM_SUITE_LEN;
+        }
+        if (i == akm_suite_count)
+        {
+            akm_type_selected = 0; // not found
+        }
+        else
+        {
+            akm_type_selected = akm_preference[ptr[3]];
+            akm_type_id       = ptr[3];
+        }
+    }
+    if (akm_type_selected == 0)
+    {
+        PRINTM(MERROR, "RSNE: AKM Suite not found for authtype %d\n", *akm_type);
+        return MLAN_STATUS_FAILURE;
+    }
+    /* Process RSNCAP */
+    ptr = ptlv_rsn_ie->rsn_ie + sizeof(t_u16) + 4 * sizeof(t_u8) + sizeof(t_u16) +
+          pairwise_cipher_count * PAIRWISE_CIPHER_SUITE_LEN + sizeof(t_u16) + akm_suite_count * AKM_SUITE_LEN;
+    prsn_cap = (t_u16 *)ptr;
+
+    ap_mfpc = ((*prsn_cap & (0x1 << MFPC_BIT)) == (0x1 << MFPC_BIT));
+    ap_mfpr = ((*prsn_cap & (0x1 << MFPR_BIT)) == (0x1 << MFPR_BIT));
+
+    if ((!ap_mfpc && !ap_mfpr && pmpriv->pmfcfg.mfpr) || ((!ap_mfpc) && ap_mfpr) ||
+        (ap_mfpc && ap_mfpr && (!pmpriv->pmfcfg.mfpc)))
+    {
+        PRINTM(MERROR, "RSNE: Mismatch in PMF config of STA and AP, can't associate to AP\n");
+        return MLAN_STATUS_FAILURE;
+    }
+    *prsn_cap |= PMF_MASK;
+    *prsn_cap &= pmf_mask;
+
+    // PMKID
+    ptr += sizeof(t_u16);
+    if (end_ptr >= (ptr + 2))
+    {
+        pmkid_count = wlan_le16_to_cpu(*(t_u16 *)ptr);
+        ptr += sizeof(t_u16);
+        pmkid_list_ptr = ptr;
+        ptr += pmkid_count * PMKID_LEN;
+    }
+    // Group Mgmt Cipher Suite
+    if ((end_ptr >= (ptr + 4)) && (pmf_mask & PMF_MASK))
+    {
+        group_mgmt_cipher_suite_ptr = ptr;
+    }
+    /* Compose new RSNE */
+    // pairwiase
+    ptr           = pairwise_cipher_count_ptr;
+    *(t_u16 *)ptr = wlan_cpu_to_le16(1);
+    ptr += sizeof(t_u16);
+    oui[3]        = cipher_selected_id;
+    *(t_u32 *)ptr = *(t_u32 *)oui;
+    ptr += PAIRWISE_CIPHER_SUITE_LEN;
+    // akm
+    *(t_u16 *)ptr = wlan_cpu_to_le16(1);
+    ptr += sizeof(t_u16);
+    oui[3]        = akm_type_id;
+    *(t_u32 *)ptr = *(t_u32 *)oui;
+    ptr += AKM_SUITE_LEN;
+    // RSNCAP
+    *(t_u16 *)ptr = wlan_cpu_to_le16(*prsn_cap);
+    ptr += sizeof(t_u16);
+    // PMKID list
+    if (pmkid_list_ptr || group_mgmt_cipher_suite_ptr)
+    {
+        // Add PMKID
+        *(t_u16 *)ptr = wlan_cpu_to_le16(pmkid_count);
+        ptr += sizeof(t_u16);
+        if (pmkid_count)
+        {
+            (void)memmove(ptr, (t_u8 *)pmkid_list_ptr, (end_ptr - ptr));
+            ptr += pmkid_count * PMKID_LEN;
+        }
+        if (group_mgmt_cipher_suite_ptr)
+        {
+            // Add Group Mgmt Cipher Suite
+            (void)memmove(ptr, (t_u8 *)group_mgmt_cipher_suite_ptr, (end_ptr - ptr));
+            ptr += GROUP_MGMT_CIPHER_SUITE_LEN;
+        }
+    }
+    *rsn_ie_len = ptr - ptlv_rsn_ie->rsn_ie;
+    return ret;
+}
+
+#if CONFIG_11R
+/**
+ *  @brief This function is to find FT AKM in RSN.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *
+ *  @param rsn_ie       A pointer to rsn_ie
+ *
+ *  @return             1 when FT AKM is in RSN, otherwise 0
+ */
+t_u8 wlan_ft_akm_is_used(mlan_private *pmpriv, t_u8 *rsn_ie)
+{
+    t_u8 *temp;
+    t_u16 count;
+    t_u16 pairwise_cipher_count  = 0;
+    t_u16 akm_suite_count        = 0;
+    t_u8 found                   = 0;
+    t_u8 rsn_ft_1x_oui[4]        = {0x00, 0x0f, 0xac, 0x03};
+    t_u8 rsn_ft_psk_oui[4]       = {0x00, 0x0f, 0xac, 0x04};
+    t_u8 rsn_ft_sae_oui[4]       = {0x00, 0x0f, 0xac, 0x09};
+    t_u8 rsn_ft_1x_sha384_oui[4] = {0x00, 0x0f, 0xac, 0x0d};
+
+    ENTER();
+
+    if (rsn_ie == MNULL)
+    {
+        goto done;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    if (rsn_ie[0] != (t_u8)RSN_IE)
+    {
+        goto done;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    /*  4 bytes header + 2 bytes version + 4 bytes group_cipher_suite +
+     *  2 bytes pairwise_cipher_count + pairwise_cipher_count *
+     * PAIRWISE_CIPHER_SUITE_LEN (4) + 2 bytes akm_suite_count +
+     * akm_suite_count * AKM_SUITE_LEN (4)
+     */
+    count                 = *(t_u16 *)(void *)(rsn_ie + 4 + 2 + 4 * (int)sizeof(t_u8));
+    pairwise_cipher_count = wlan_le16_to_cpu(count);
+    count                 = *(t_u16 *)(void *)(rsn_ie + 4 + 2 + 4 * (int)sizeof(t_u8) + (int)sizeof(t_u16) +
+                               (int)pairwise_cipher_count * 4);
+    akm_suite_count       = (t_u16)wlan_le16_to_cpu(count);
+    temp                  = (t_u8 *)(rsn_ie + 4 + sizeof(t_u16) + 4 * (int)sizeof(t_u8) + (int)sizeof(t_u16) +
+                    (int)pairwise_cipher_count * 4 + sizeof(t_u16));
+
+    while (akm_suite_count > 0U)
+    {
+        if (__memcmp(pmpriv->adapter, temp, rsn_ft_1x_oui, sizeof(rsn_ft_1x_oui)) == 0 ||
+            __memcmp(pmpriv->adapter, temp, rsn_ft_psk_oui, sizeof(rsn_ft_psk_oui)) == 0 ||
+            __memcmp(pmpriv->adapter, temp, rsn_ft_sae_oui, sizeof(rsn_ft_sae_oui)) == 0 ||
+            __memcmp(pmpriv->adapter, temp, rsn_ft_1x_sha384_oui, sizeof(rsn_ft_1x_sha384_oui)) == 0)
+        {
+            found = 1;
+            break;
+        }
+        temp += 4;
+        akm_suite_count--;
+    }
+
+done:
+    LEAVE();
+    return found;
+}
+
+/**
+ *  @brief Append  IE as a pass through TLV to a TLV buffer.
+ *
+ *  This routine appends IE as a pass through TLV type to the request.
+ *
+ *  @param priv     A pointer to mlan_private structure
+ *  @param ie       A pointer to IE buffer
+ *  @param ppbuffer pointer to command buffer pointer
+ *
+ *  @return         bytes added to the buffer
+ */
+static int wlan_cmd_append_pass_through_ie(mlan_private *priv, IEEEtypes_Generic_t *ie, t_u8 **ppbuffer)
+{
+    int ret_len = 0;
+    MrvlIEtypesHeader_t ie_header;
+
+    ENTER();
+
+    /* Null Checks */
+    if (ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    if (*ppbuffer == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    if (ie->ieee_hdr.len)
+    {
+        PRINTM(MINFO, "append generic IE %d to %p\n", ie->ieee_hdr.len, *ppbuffer);
+
+        /* Wrap the generic IE buffer with a pass through TLV type */
+        ie_header.type = wlan_cpu_to_le16(TLV_TYPE_PASSTHROUGH);
+        ie_header.len  = wlan_cpu_to_le16(ie->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+        __memcpy(priv->adapter, *ppbuffer, &ie_header, sizeof(ie_header));
+
+        /* Increment the return size and the return buffer pointer param
+         */
+        *ppbuffer += sizeof(ie_header);
+        ret_len += sizeof(ie_header);
+
+        /* Copy the generic IE buffer to the output buffer, advance
+         * pointer */
+        __memcpy(priv->adapter, *ppbuffer, ie, ie->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+
+        /* Increment the return size and the return buffer pointer param
+         */
+        *ppbuffer += ie->ieee_hdr.len + sizeof(IEEEtypes_Header_t);
+        ret_len += ie->ieee_hdr.len + sizeof(IEEEtypes_Header_t);
+    }
+    /* return the length appended to the buffer */
+    LEAVE();
+    return ret_len;
+}
+#endif
+
+/********************************************************
+                Global Functions
+********************************************************/
+/**
+ *  @brief This function prepares command of association.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf    A pointer cast of BSSDescriptor_t from the
+ *                        scan table to assoc
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_cmd_802_11_associate(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf)
+{
+    mlan_status ret                    = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter            = pmpriv->adapter;
+    HostCmd_DS_802_11_ASSOCIATE *passo = &cmd->params.associate;
+    BSSDescriptor_t *pbss_desc;
+    MrvlIEtypes_SsIdParamSet_t *pssid_tlv;
+    MrvlIEtypes_PhyParamSet_t *pphy_tlv;
+    MrvlIEtypes_SsParamSet_t *pss_tlv;
+    MrvlIEtypes_RatesParamSet_t *prates_tlv;
+    MrvlIEtypes_AuthType_t *pauth_tlv      = MNULL;
+    MrvlIEtypes_RsnParamSet_t *prsn_ie_tlv = MNULL;
+    MrvlIEtypes_ChanListParamSet_t *pchan_tlv;
+    WLAN_802_11_RATES rates = {0x00};
+    t_u32 rates_size;
+    t_u16 tmp_cap;
+    t_u8 *pos, *auth_pos = NULL;
+    t_u8 akm_type = 0;
+#if CONFIG_11R
+    t_u8 ft_akm = 0;
+#endif
+    MrvlIEtypes_PrevBssid_t *prev_bssid_tlv = MNULL;
+    t_u8 zero_mac[MLAN_MAC_ADDR_LENGTH]     = {0};
+#if CONFIG_DRIVER_MBO
+    t_u8 oper_class = 1;
+#endif
+
+    MrvlIEtypes_HostMlme_t *host_mlme_tlv = MNULL;
+
+    ENTER();
+
+    (void)__memset(pmadapter, &rates, 0x00, sizeof(WLAN_802_11_RATES));
+    pbss_desc = (BSSDescriptor_t *)pdata_buf;
+    pos       = (t_u8 *)&cmd->params;
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_ASSOCIATE);
+
+    /* Save so we know which BSS Desc to use in the response handler */
+    pmpriv->pattempted_bss_desc = pbss_desc;
+    (void)__memcpy(pmadapter, &pmpriv->curr_bss_params.attemp_bssid, pbss_desc->mac_address, MLAN_MAC_ADDR_LENGTH);
+    pmpriv->assoc_req_size = 0;
+
+    (void)__memcpy(pmadapter, passo->peer_sta_addr, pbss_desc->mac_address, sizeof(passo->peer_sta_addr));
+
+    /* fixme: Look at this value carefully later. The listen interval is given to AP during
+     * this assoc. The listen_interval set later during IEEE PS should not (?) exceed this
+     */
+    /* Set the listen interval */
+    passo->listen_interval = wlan_cpu_to_le16(pmpriv->listen_interval);
+    /* Set the beacon period */
+    passo->beacon_period = wlan_cpu_to_le16(pbss_desc->beacon_period);
+
+    pos                    = (t_u8 *)cmd + S_DS_GEN + sizeof(HostCmd_DS_802_11_ASSOCIATE);
+    pssid_tlv              = (MrvlIEtypes_SsIdParamSet_t *)(void *)pos;
+    pssid_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_SSID);
+    pssid_tlv->header.len  = (t_u16)pbss_desc->ssid.ssid_len;
+    (void)__memcpy(pmadapter, pssid_tlv->ssid, pbss_desc->ssid.ssid, pssid_tlv->header.len);
+    pos += sizeof(pssid_tlv->header) + pssid_tlv->header.len;
+    pssid_tlv->header.len = wlan_cpu_to_le16(pssid_tlv->header.len);
+
+    pphy_tlv              = (MrvlIEtypes_PhyParamSet_t *)(void *)pos;
+    pphy_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_PHY_DS);
+    pphy_tlv->header.len  = sizeof(pphy_tlv->fh_ds.ds_param_set);
+    (void)__memcpy(pmadapter, &pphy_tlv->fh_ds.ds_param_set, &pbss_desc->phy_param_set.ds_param_set.current_chan,
+                   sizeof(pphy_tlv->fh_ds.ds_param_set));
+    pos += sizeof(pphy_tlv->header) + pphy_tlv->header.len;
+    pphy_tlv->header.len = wlan_cpu_to_le16(pphy_tlv->header.len);
+
+    pss_tlv              = (MrvlIEtypes_SsParamSet_t *)(void *)pos;
+    pss_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_CF);
+    pss_tlv->header.len  = sizeof(pss_tlv->cf_ibss.cf_param_set);
+    pos += sizeof(pss_tlv->header) + pss_tlv->header.len;
+    pss_tlv->header.len = wlan_cpu_to_le16(pss_tlv->header.len);
+
+    /* Get the common rates supported between the driver and the BSS Desc */
+    if (wlan_setup_rates_from_bssdesc(pmpriv, pbss_desc, rates, &rates_size) != MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+
+    /* Save the data rates into Current BSS state structure */
+    pmpriv->curr_bss_params.num_of_rates = rates_size;
+    (void)__memcpy(pmadapter, &pmpriv->curr_bss_params.data_rates, rates, rates_size);
+
+    /* Setup the Rates TLV in the association command */
+    prates_tlv              = (MrvlIEtypes_RatesParamSet_t *)(void *)pos;
+    prates_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_RATES);
+    prates_tlv->header.len  = wlan_cpu_to_le16((t_u16)rates_size);
+    (void)__memcpy(pmadapter, prates_tlv->rates, rates, rates_size);
+    pos += sizeof(prates_tlv->header) + rates_size;
+    PRINTM(MINFO, "ASSOC_CMD: Rates size = %d\n", rates_size);
+
+    /* Add the Authentication type to be used for Auth frames if needed */
+    if ((pmpriv->sec_info.authentication_mode != MLAN_AUTH_MODE_AUTO)
+#if CONFIG_DRIVER_OWE
+        || (pbss_desc->owe_transition_mode == OWE_TRANS_MODE_OWE)
+#endif
+    )
+    {
+        pauth_tlv              = (MrvlIEtypes_AuthType_t *)(void *)pos;
+        pauth_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_AUTH_TYPE);
+        pauth_tlv->header.len  = sizeof(pauth_tlv->auth_type);
+        if (pmpriv->sec_info.authentication_mode == MLAN_AUTH_MODE_SAE)
+        {
+            pauth_tlv->auth_type = wlan_cpu_to_le16((t_u16)AssocAgentAuth_Wpa3Sae);
+        }
+#if CONFIG_11R
+        else if (pmpriv->sec_info.authentication_mode == MLAN_AUTH_MODE_FT)
+        {
+            if (pmpriv->curr_bss_params.host_mlme)
+            {
+                pauth_tlv->auth_type = wlan_cpu_to_le16(AssocAgentAuth_FastBss_Skip);
+            }
+            else
+            {
+                pauth_tlv->auth_type = wlan_cpu_to_le16(AssocAgentAuth_FastBss);
+            }
+        }
+#endif
+#if CONFIG_DRIVER_OWE
+        else if (
+            !pmpriv->curr_bss_params.host_mlme &&
+            ((pbss_desc->owe_transition_mode == OWE_TRANS_MODE_OWE) ||
+             (pmpriv->sec_info.authentication_mode == MLAN_AUTH_MODE_OWE)))
+        {
+            pauth_tlv->auth_type = wlan_cpu_to_le16((t_u16)AssocAgentAuth_Owe);
+        }
+#endif
+        else if (pmpriv->sec_info.wep_status == Wlan802_11WEPEnabled)
+        {
+            pauth_tlv->auth_type = wlan_cpu_to_le16((t_u16)pmpriv->sec_info.authentication_mode);
+        }
+        else
+        {
+            pauth_tlv->auth_type = wlan_cpu_to_le16(MLAN_AUTH_MODE_OPEN);
+        }
+        pos += sizeof(pauth_tlv->header) + pauth_tlv->header.len;
+        pauth_tlv->header.len = wlan_cpu_to_le16(pauth_tlv->header.len);
+    }
+
+    if (IS_SUPPORT_MULTI_BANDS(pmadapter) && (pbss_desc->bss_band & pmpriv->config_bands) &&
+        !(ISSUPP_11NENABLED(pmadapter->fw_cap_info) && (!pbss_desc->disable_11n) &&
+          (pmpriv->config_bands & BAND_GN || pmpriv->config_bands & BAND_AN) && (pbss_desc->pht_cap != MNULL)))
+    {
+        /* Append a channel TLV for the channel the attempted AP was found on */
+        pchan_tlv              = (MrvlIEtypes_ChanListParamSet_t *)(void *)pos;
+        pchan_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+        pchan_tlv->header.len  = wlan_cpu_to_le16(sizeof(ChanScanParamSet_t));
+
+        (void)__memset(pmadapter, pchan_tlv->chan_scan_param, 0x00, sizeof(ChanScanParamSet_t));
+        pchan_tlv->chan_scan_param[0].chan_number = (pbss_desc->phy_param_set.ds_param_set.current_chan);
+        PRINTM(MINFO, "Assoc: TLV Chan = %d\n", pchan_tlv->chan_scan_param[0].chan_number);
+
+        pchan_tlv->chan_scan_param[0].radio_type = wlan_band_to_radio_type((t_u8)pbss_desc->bss_band);
+
+        PRINTM(MINFO, "Assoc: TLV Band = %d\n", pchan_tlv->chan_scan_param[0].radio_type);
+        pos += sizeof(pchan_tlv->header) + sizeof(ChanScanParamSet_t);
+    }
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    if (pmpriv->wps.session_enable == MFALSE)
+    {
+#endif /* CONFIG_WPA_SUPP_WPS */
+#elif (CONFIG_WPS2)
+    if (wlan_get_prov_session() != PROV_WPS_SESSION_ATTEMPT)
+    {
+#endif
+        /* fixme: The above 'if' is used instead of below 'if' for now since
+           WPS module is mlan integrated yet. Fix after it is done.
+        */
+        /* if (!pmpriv->wps.session_enable) { */
+        if ((pmpriv->sec_info.wpa_enabled || pmpriv->sec_info.wpa2_enabled)
+#if CONFIG_DRIVER_OWE
+            || (pbss_desc->owe_transition_mode == OWE_TRANS_MODE_OWE) ||
+            (pmpriv->sec_info.authentication_mode == MLAN_AUTH_MODE_OWE)
+#endif
+        )
+        {
+            if ((pauth_tlv == MNULL) && (pmpriv->sec_info.authentication_mode == MLAN_AUTH_MODE_AUTO))
+            {
+                auth_pos = pos;
+                pos += sizeof(MrvlIEtypes_AuthType_t);
+            }
+
+            prsn_ie_tlv              = (MrvlIEtypes_RsnParamSet_t *)(void *)pos;
+            prsn_ie_tlv->header.type = (t_u16)pmpriv->wpa_ie[0]; /* WPA_IE
+                                                                    or
+                                                                    RSN_IE
+                                                                  */
+            prsn_ie_tlv->header.type = prsn_ie_tlv->header.type & 0x00FF;
+            prsn_ie_tlv->header.type = wlan_cpu_to_le16(prsn_ie_tlv->header.type);
+            prsn_ie_tlv->header.len  = (t_u16)pmpriv->wpa_ie[1];
+            prsn_ie_tlv->header.len  = prsn_ie_tlv->header.len & 0x00FF;
+            if (prsn_ie_tlv->header.len <= (sizeof(pmpriv->wpa_ie) - 2))
+            {
+                (void)__memcpy(pmadapter, prsn_ie_tlv->rsn_ie, &pmpriv->wpa_ie[2], prsn_ie_tlv->header.len);
+                if (pmpriv->sec_info.wpa2_enabled
+#if CONFIG_WPA_SUPP_DPP
+                    && pmpriv->is_dpp_connect == MFALSE
+#endif
+                )
+                {
+                    akm_type             = pauth_tlv ? wlan_le16_to_cpu(pauth_tlv->auth_type) : AssocAgentAuth_Auto;
+                    t_u16 rsn_ie_tlv_len = prsn_ie_tlv->header.len;
+                    ret = (mlan_status)wlan_update_rsn_ie(pmpriv, prsn_ie_tlv, &rsn_ie_tlv_len, &akm_type);
+                    prsn_ie_tlv->header.len = rsn_ie_tlv_len;
+#if CONFIG_11R
+                    /** parse rsn ie to find whether ft akm is used*/
+                    ft_akm = wlan_ft_akm_is_used(pmpriv, (t_u8 *)prsn_ie_tlv);
+#endif
+                }
+            }
+            else
+            {
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+            HEXDUMP("ASSOC_CMD: RSN IE", (t_u8 *)prsn_ie_tlv, sizeof(prsn_ie_tlv->header) + prsn_ie_tlv->header.len);
+            pos += sizeof(prsn_ie_tlv->header) + prsn_ie_tlv->header.len;
+            prsn_ie_tlv->header.len = wlan_cpu_to_le16(prsn_ie_tlv->header.len);
+
+#if CONFIG_11R
+            if ((akm_type == AssocAgentAuth_FastBss) && (pmpriv->sec_info.is_ft == false))
+            {
+                akm_type = AssocAgentAuth_Open;
+            }
+            if ((akm_type == AssocAgentAuth_FastBss_SAE) && (pmpriv->sec_info.is_ft == false))
+            {
+                akm_type = AssocAgentAuth_Wpa3Sae;
+            }
+#endif
+#if CONFIG_DRIVER_OWE
+            if ((akm_type == AssocAgentAuth_Owe) && (pmpriv->curr_bss_params.host_mlme))
+            {
+                akm_type = AssocAgentAuth_Open;
+            }
+#endif
+            if ((pauth_tlv == MNULL) && (pmpriv->sec_info.authentication_mode == MLAN_AUTH_MODE_AUTO))
+            {
+                pauth_tlv              = (MrvlIEtypes_AuthType_t *)auth_pos;
+                pauth_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_AUTH_TYPE);
+                pauth_tlv->header.len  = sizeof(pauth_tlv->auth_type);
+                pauth_tlv->auth_type   = wlan_cpu_to_le16(akm_type);
+
+                pauth_tlv->header.len = wlan_cpu_to_le16(pauth_tlv->header.len);
+            }
+        }
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    }
+#endif /* CONFIG_WPA_SUPP_WPS */
+#elif (CONFIG_WPS2)
+    }
+#endif
+
+    if ((pauth_tlv != MNULL) && (pauth_tlv->auth_type == wlan_cpu_to_le16(AssocAgentAuth_Wpa3Sae)))
+    {
+        if ((pbss_desc->prsnx_ie != MNULL) && pbss_desc->prsnx_ie->ieee_hdr.len &&
+            (pbss_desc->prsnx_ie->data[0] & (0x1 << SAE_H2E_BIT)))
+        {
+            MrvlIEtypes_SAE_PWE_Mode_t *psae_pwe_mode_tlv;
+
+            /* Setup the sae mode TLV in the association command */
+            psae_pwe_mode_tlv              = (MrvlIEtypes_SAE_PWE_Mode_t *)(void *)pos;
+            psae_pwe_mode_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_WPA3_SAE_PWE_DERIVATION_MODE);
+            psae_pwe_mode_tlv->header.len  = sizeof(psae_pwe_mode_tlv->pwe);
+            psae_pwe_mode_tlv->pwe[0]      = pbss_desc->prsnx_ie->data[0];
+            pos += sizeof(psae_pwe_mode_tlv->header) + sizeof(psae_pwe_mode_tlv->pwe);
+        }
+    }
+
+    if (ISSUPP_11NENABLED(pmadapter->fw_cap_info) && (!pbss_desc->disable_11n) &&
+        (pmpriv->config_bands & BAND_GN || pmpriv->config_bands & BAND_AN) && wmsdk_is_11N_enabled() &&
+        (!pmpriv->sec_info.is_wpa_tkip))
+    {
+        (void)wlan_cmd_append_11n_tlv(pmpriv, pbss_desc, &pos);
+    }
+    else if (pmpriv->hotspot_cfg & HOTSPOT_ENABLED)
+    {
+        wlan_add_ext_capa_info_ie(pmpriv, pbss_desc, &pos);
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+#if CONFIG_11AC
+    if (ISSUPP_11ACENABLED(pmadapter->fw_cap_info) && (!pbss_desc->disable_11n) &&
+        wlan_11ac_bandconfig_allowed(pmpriv, pbss_desc->bss_band))
+    {
+        (void)wlan_cmd_append_11ac_tlv(pmpriv, pbss_desc, &pos);
+    }
+#endif
+
+#if CONFIG_11AX
+    if ((IS_FW_SUPPORT_11AX(pmadapter)) && (!pbss_desc->disable_11n) &&
+        wlan_11ax_bandconfig_allowed(pmpriv, pbss_desc->bss_band))
+        wlan_cmd_append_11ax_tlv(pmpriv, pbss_desc, &pos);
+#endif
+
+    (void)wlan_wmm_process_association_req(pmpriv, &pos, &pbss_desc->wmm_ie, pbss_desc->pht_cap);
+
+#if CONFIG_11R
+#if CONFIG_WPA_SUPP
+    if (pmpriv->md_ie_len != 0U)
+#else
+    if (ft_akm == 1U)
+#endif
+    {
+        wlan_cmd_append_pass_through_ie(pmpriv, (IEEEtypes_Generic_t *)(void *)pmpriv->md_ie, &pos);
+    }
+    else
+    {
+        /* Do nothing */
+    }
+#endif
+
+    if (pmpriv->curr_bss_params.host_mlme)
+    {
+        host_mlme_tlv              = (MrvlIEtypes_HostMlme_t *)pos;
+        host_mlme_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_HOST_MLME);
+        host_mlme_tlv->header.len  = wlan_cpu_to_le16(sizeof(host_mlme_tlv->host_mlme));
+        host_mlme_tlv->host_mlme   = MTRUE;
+        pos += sizeof(host_mlme_tlv->header) + host_mlme_tlv->header.len;
+    }
+    if (memcmp(&pmpriv->curr_bss_params.prev_bssid, zero_mac, MLAN_MAC_ADDR_LENGTH))
+    {
+        prev_bssid_tlv              = (MrvlIEtypes_PrevBssid_t *)pos;
+        prev_bssid_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_PREV_BSSID);
+        prev_bssid_tlv->header.len  = wlan_cpu_to_le16(MLAN_MAC_ADDR_LENGTH);
+        __memcpy(pmadapter, prev_bssid_tlv->prev_bssid, &pmpriv->curr_bss_params.prev_bssid, MLAN_MAC_ADDR_LENGTH);
+        PRINTM(MCMND, "ASSOCIATE: PREV_BSSID = " MACSTR "\n", MAC2STR(pmpriv->curr_bss_params.prev_bssid));
+        pos += sizeof(prev_bssid_tlv->header) + MLAN_MAC_ADDR_LENGTH;
+    }
+
+#if CONFIG_DRIVER_MBO
+    wlan_get_curr_global_oper_class(pmpriv, pbss_desc->phy_param_set.ds_param_set.current_chan, BW_20MHZ, &oper_class);
+    wlan_add_supported_oper_class_ie(pmpriv, &pos, oper_class);
+#endif
+
+    /* fixme: Currently not required */
+
+    wlan_cmd_append_generic_ie(pmpriv, &pos);
+
+
+    cmd->size = wlan_cpu_to_le16((t_u16)(pos - (t_u8 *)passo) + S_DS_GEN);
+
+    /* Set the Capability info at last */
+    (void)__memcpy(pmadapter, &tmp_cap, &pbss_desc->cap_info, sizeof(passo->cap_info));
+
+    if (pmpriv->config_bands == BAND_B)
+    {
+        SHORT_SLOT_TIME_DISABLED(tmp_cap);
+    }
+
+    /* set SpectrumMgmt(BIT8) and RadioMeasurement(BIT12) if 11K is enabled
+     */
+
+#if CONFIG_11K
+        if (pmpriv->enable_host_11k == (t_u8)1U)
+    {
+        SPECTRUM_MGMT_ENABLED(tmp_cap);
+        RADIO_MEASUREMENT_ENABLED(tmp_cap);
+    }
+    else
+#endif
+    {
+        RADIO_MEASUREMENT_DISABLED(tmp_cap);
+    }
+
+    tmp_cap &= CAPINFO_MASK;
+    PRINTM(MINFO, "ASSOC_CMD: tmp_cap=%4X CAPINFO_MASK=%4lX\n", tmp_cap, CAPINFO_MASK);
+    tmp_cap = wlan_cpu_to_le16(tmp_cap);
+    (void)__memcpy(pmadapter, &passo->cap_info, &tmp_cap, sizeof(passo->cap_info));
+
+done:
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Association firmware command response handler
+ *
+ *   The response buffer for the association command has the following
+ *      memory layout.
+ *
+ *   For cases where an association response was not received (indicated
+ *      by the CapInfo and AId field):
+ *
+ *     .------------------------------------------------------------.
+ *     |  Header(4 * sizeof(t_u16)):  Standard command response hdr |
+ *     .------------------------------------------------------------.
+ *     |  cap_info/Error Return(t_u16):                             |
+ *     |           0xFFFF(-1): Internal error for association       |
+ *     |           0xFFFE(-2): Authentication unhandled message     |
+ *     |           0xFFFD(-3): Authentication refused               |
+ *     |           0xFFFC(-4): Timeout waiting for AP response      |
+ *     |           0xFFFB(-5): Internal error for authentication    |
+ *     .------------------------------------------------------------.
+ *     |  status_code(t_u16):                                       |
+ *     |        If cap_info is -1:                                  |
+ *     |           An internal firmware failure prevented the       |
+ *     |           command from being processed. The status code    |
+ *     |           is 6 if associate response parameter invlaid,    |
+ *     |           1 otherwise.                                     |
+ *     |                                                            |
+ *     |        If cap_info is -2:                                  |
+ *     |           An authentication frame was received but was     |
+ *     |           not handled by the firmware. IEEE Status code    |
+ *     |           for the failure is returned.                     |
+ *     |                                                            |
+ *     |        If cap_info is -3:                                  |
+ *     |           An authentication frame was received and the     |
+ *     |           status_code is the IEEE Status reported in the   |
+ *     |           response.                                        |
+ *     |                                                            |
+ *     |        If cap_info is -4:                                  |
+ *     |           (1) Association response timeout                 |
+ *     |           (2) Authentication response timeout              |
+ *     |                                                            |
+ *     |        If cap_info is -5:                                  |
+ *     |           An internal firmware failure prevented the       |
+ *     |           command from being processed. The status code    |
+ *     |           is 6 if authentication parameter invlaid,        |
+ *     |           1 otherwise.                                     |
+ *     .------------------------------------------------------------.
+ *     |  a_id(t_u16): 0xFFFF                                       |
+ *     .------------------------------------------------------------.
+ *
+ *
+ *   For cases where an association response was received, the IEEE
+ *     standard association response frame is returned:
+ *
+ *     .------------------------------------------------------------.
+ *     |  Header(4 * sizeof(t_u16)):  Standard command response hdr |
+ *     .------------------------------------------------------------.
+ *     |  cap_info(t_u16): IEEE Capability                          |
+ *     .------------------------------------------------------------.
+ *     |  status_code(t_u16): IEEE Status Code                      |
+ *     .------------------------------------------------------------.
+ *     |  a_id(t_u16): IEEE Association ID                          |
+ *     .------------------------------------------------------------.
+ *     |  IEEE IEs(variable): Any received IEs comprising the       |
+ *     |                      remaining portion of a received       |
+ *     |                      association response frame.           |
+ *     .------------------------------------------------------------.
+ *
+ *  For simplistic handling, the status_code field can be used to determine
+ *    an association success (0) or failure (non-zero).
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ret_802_11_associate(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf)
+{
+    mlan_status ret            = MLAN_STATUS_SUCCESS;
+    mlan_ioctl_req *pioctl_req = (mlan_ioctl_req *)pioctl_buf;
+    IEEEtypes_AssocRsp_t *passoc_rsp;
+    BSSDescriptor_t *pbss_desc;
+    /* t_u8 enable_data = MTRUE; */
+    /* t_u8 event_buf[100]; */
+    /* mlan_event *pevent = (mlan_event *) event_buf; */
+    t_u8 cur_mac[MLAN_MAC_ADDR_LENGTH] = {0x0};
+#if CONFIG_WMM
+    t_u8 media_connected = pmpriv->media_connected;
+#endif
+    /* mlan_adapter *pmadapter = pmpriv->adapter; */
+
+    IEEEtypes_MgmtHdr_t *hdr;
+
+    ENTER();
+
+    if (pmpriv->curr_bss_params.host_mlme)
+    {
+        hdr = (IEEEtypes_MgmtHdr_t *)&resp->params;
+        if (!__memcmp(pmpriv->adapter, hdr->BssId, pmpriv->pattempted_bss_desc->mac_address, MLAN_MAC_ADDR_LENGTH))
+        {
+            passoc_rsp = (IEEEtypes_AssocRsp_t *)((t_u8 *)(&resp->params) + sizeof(IEEEtypes_MgmtHdr_t));
+        }
+        else
+        {
+            passoc_rsp = (IEEEtypes_AssocRsp_t *)&resp->params;
+        }
+    }
+    else
+
+        passoc_rsp = (IEEEtypes_AssocRsp_t *)(void *)&resp->params;
+    passoc_rsp->status_code = wlan_le16_to_cpu(passoc_rsp->status_code);
+    if (pmpriv->media_connected == MTRUE)
+    {
+        (void)__memcpy(pmpriv->adapter, cur_mac, pmpriv->curr_bss_params.bss_descriptor.mac_address,
+                       MLAN_MAC_ADDR_LENGTH);
+    }
+
+    /* fixme: Enable this when req. We may not need to save the
+       resp. buffer at all */
+
+    /* fixme: This is not needed as of now. */
+    if (passoc_rsp->status_code)
+    {
+        if (pmpriv->media_connected == MTRUE)
+        {
+            if (pmpriv->port_ctrl_mode == MTRUE)
+                pmpriv->port_open = pmpriv->prior_port_status;
+            if (!__memcmp(pmpriv->adapter, cur_mac, pmpriv->pattempted_bss_desc->mac_address, MLAN_MAC_ADDR_LENGTH))
+                wlan_reset_connect_state(pmpriv, MTRUE);
+        }
+
+        wifi_d(
+            "ASSOC_RESP: Association Failed, "
+            "status code = %d, a_id = 0x%x",
+            wlan_le16_to_cpu(passoc_rsp->status_code), wlan_le16_to_cpu(passoc_rsp->a_id));
+
+        return MLAN_STATUS_FAILURE;
+    }
+
+    /* Send a Media Connected event, according to the Spec */
+    pmpriv->media_connected = MTRUE;
+
+#if CONFIG_WMM_UAPSD
+    pmpriv->adapter->pps_uapsd_mode = MFALSE;
+    pmpriv->adapter->tx_lock_flag   = MFALSE;
+#endif
+
+    /* Set the attempted BSSID Index to current */
+    pbss_desc = pmpriv->pattempted_bss_desc;
+
+    PRINTM(MINFO, "ASSOC_RESP: %s\n", pbss_desc->ssid.ssid);
+
+    /* Make a copy of current BSSID descriptor */
+    (void)__memcpy(pmpriv->adapter, &pmpriv->curr_bss_params.bss_descriptor, pbss_desc, sizeof(BSSDescriptor_t));
+
+    /* Update curr_bss_params */
+    pmpriv->curr_bss_params.bss_descriptor.channel = pbss_desc->phy_param_set.ds_param_set.current_chan;
+
+    pmpriv->curr_bss_params.band = (t_u8)pbss_desc->bss_band;
+
+
+    if (pbss_desc->wmm_ie.vend_hdr.element_id == WMM_IE)
+    {
+        pmpriv->curr_bss_params.wmm_enabled = MTRUE;
+    }
+    else
+    {
+        pmpriv->curr_bss_params.wmm_enabled = MFALSE;
+    }
+
+    if ((pmpriv->wmm_required ||
+         ((pbss_desc->pht_cap != MNULL) && (pbss_desc->pht_cap->ieee_hdr.element_id == HT_CAPABILITY))) &&
+        pmpriv->curr_bss_params.wmm_enabled)
+    {
+        pmpriv->wmm_enabled = MTRUE;
+    }
+    else
+    {
+        pmpriv->wmm_enabled = MFALSE;
+    }
+
+    /* fixme: Enable if req */
+#if CONFIG_WMM_UAPSD
+    pmpriv->curr_bss_params.wmm_uapsd_enabled = MFALSE;
+
+    if (pmpriv->wmm_enabled == MTRUE)
+    {
+        pmpriv->curr_bss_params.wmm_uapsd_enabled = pbss_desc->wmm_ie.qos_info.qos_uapsd;
+    }
+#endif
+    if (pmpriv->sec_info.wpa_enabled || pmpriv->sec_info.wpa2_enabled)
+    {
+        pmpriv->wpa_is_gtk_set = MFALSE;
+    }
+
+
+    /* Reset SNR/NF/RSSI values */
+    pmpriv->data_rssi_last = 0;
+    pmpriv->data_nf_last   = 0;
+    pmpriv->data_rssi_avg  = 0;
+    pmpriv->data_nf_avg    = 0;
+    pmpriv->bcn_rssi_last  = 0;
+    pmpriv->bcn_nf_last    = 0;
+    pmpriv->bcn_rssi_avg   = 0;
+    pmpriv->bcn_nf_avg     = 0;
+    pmpriv->rxpd_rate      = 0;
+#ifdef SD8801
+    pmpriv->rxpd_htinfo = 0;
+#else
+    pmpriv->rxpd_rate_info = 0;
+#endif
+    if (pbss_desc->pht_cap != MNULL)
+    {
+        if ((GETHT_MAXAMSDU(pbss_desc->pht_cap->ht_cap.ht_cap_info)) != 0U)
+        {
+            pmpriv->max_amsdu = MLAN_TX_DATA_BUF_SIZE_8K;
+        }
+        else
+        {
+            pmpriv->max_amsdu = MLAN_TX_DATA_BUF_SIZE_4K;
+        }
+    }
+
+
+#if CONFIG_WMM
+    /* Add the ra_list here for infra mode as there will be only 1 ra always */
+    if (media_connected == MTRUE)
+    {
+        if (0 == wlan_ralist_update_enh(pmpriv, cur_mac, pmpriv->curr_bss_params.bss_descriptor.mac_address))
+        {
+            wlan_ralist_add_enh(pmpriv, pmpriv->curr_bss_params.bss_descriptor.mac_address);
+        }
+
+        wlan_11n_cleanup_reorder_tbl(pmpriv);
+        wlan_11n_deleteall_txbastream_tbl(pmpriv);
+    }
+    else
+    {
+        wlan_ralist_add_enh(pmpriv, pmpriv->curr_bss_params.bss_descriptor.mac_address);
+    }
+#endif
+
+
+    if (!pmpriv->sec_info.wpa_enabled && !pmpriv->sec_info.wpa2_enabled && !pmpriv->sec_info.ewpa_enabled &&
+        !pmpriv->sec_info.wapi_enabled)
+    {
+        /* We are in Open/WEP mode, open port immediately */
+        if (pmpriv->port_ctrl_mode == MTRUE)
+        {
+            pmpriv->port_open = MTRUE;
+            PRINTM(MINFO, "ASSOC_RESP: port_status = OPEN\n");
+        }
+    }
+
+    if (pmpriv->sec_info.wpa_enabled || pmpriv->sec_info.wpa2_enabled || pmpriv->sec_info.ewpa_enabled ||
+        pmpriv->sec_info.wapi_enabled)
+    {
+        pmpriv->scan_block = MTRUE;
+    }
+
+    /* done: */
+    /* Need to indicate IOCTL complete */
+    if (pioctl_req != MNULL)
+    {
+            pioctl_req->status_code = MLAN_ERROR_NO_ERROR;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief Associated to a specific BSS discovered in a scan
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pioctl_buf   A pointer to MLAN IOCTL Request buffer
+ *  @param pbss_desc     A pointer to the BSS descriptor to associate with.
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_associate(IN mlan_private *pmpriv, IN t_void *pioctl_buf, IN BSSDescriptor_t *pbss_desc)
+{
+    mlan_status ret                          = MLAN_STATUS_SUCCESS;
+    t_u8 current_bssid[MLAN_MAC_ADDR_LENGTH] = {0x0};
+    pmlan_ioctl_req pioctl_req               = (mlan_ioctl_req *)pioctl_buf;
+
+    ENTER();
+
+    /* Return error if the pmadapter or table entry is not marked as infra */
+    if ((pmpriv->bss_mode != MLAN_BSS_MODE_INFRA) || (pbss_desc->bss_mode != MLAN_BSS_MODE_INFRA))
+    {
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+        }
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    (void)__memcpy(pmpriv->adapter, &current_bssid, &pmpriv->curr_bss_params.bss_descriptor.mac_address,
+                   sizeof(current_bssid));
+
+    /* Clear any past association response stored for application retrieval */
+    /* fixme: enable this later if assoc rsp buffer is needed */
+    /* pmpriv->assoc_rsp_size = 0; */
+
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_802_11_ASSOCIATE, HostCmd_ACT_GEN_SET, 0, pioctl_buf, pbss_desc);
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief Convert band to radio type used in channel TLV
+ *
+ *  @param band		Band enumeration to convert to a channel TLV radio type
+ *
+ *  @return		Radio type designator for use in a channel TLV
+ */
+t_u8 wlan_band_to_radio_type(IN t_u8 band)
+{
+    t_u8 ret_radio_type;
+
+    ENTER();
+
+    switch (band)
+    {
+        case BAND_A:
+        case BAND_AN:
+        case BAND_A | BAND_AN:
+            ret_radio_type = HostCmd_SCAN_RADIO_TYPE_A;
+            break;
+        case BAND_B:
+        case BAND_G:
+        case BAND_B | BAND_G:
+        default:
+            ret_radio_type = HostCmd_SCAN_RADIO_TYPE_BG;
+            break;
+    }
+
+    LEAVE();
+    return ret_radio_type;
+}
+
+bool wlan_use_non_default_ht_vht_cap(IN BSSDescriptor_t *pbss_desc)
+{
+    /* If connect to 11ax or non-brcm AP, still use default HT/VHT cap */
+    if (
+#if CONFIG_11AX
+        pbss_desc->phe_cap ||
+#endif
+        (!pbss_desc->brcm_ie_exist && !pbss_desc->epigram_ie_exist))
+        return false;
+
+    /* In HT cap, check if "Transmit Null Data Packet" is set to 0,
+     * In VHT cap, check if "Number of Sounding Dimensions" is set to 3,
+     * If both are true, do not use default HT/VHT cap */
+    if ((pbss_desc->pht_cap && (((pbss_desc->ht_cap_saved.ht_cap.tx_bf_cap >> 4) & 0x1) == 0x0))
+#if CONFIG_11AC
+        && (!pbss_desc->pvht_cap ||
+            (pbss_desc->pvht_cap && (GET_VHTCAP_NUMSNDDM(pbss_desc->vht_cap_saved.vht_cap.vht_cap_info) == 0x2)))
+#endif
+    )
+    {
+        return true;
+    }
+
+    return false;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_mbo.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_mbo.c
new file mode 100644
index 0000000000..6fd0992ddc
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_mbo.c
@@ -0,0 +1,171 @@
+/** @file mlan_mbo.c
+ *
+ *  @brief  This file provides functions for process MBO feature
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    8/SEP/2022: initial version
+********************************************************/
+
+#include <mlan_api.h>
+#include "mlan_mbo.h"
+
+#if CONFIG_DRIVER_MBO
+#define WNM_NOTIFICATION_SIZE 200U
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+const t_u8 mbo_oui[3]             = {0x50, 0x6f, 0x9a};
+static const t_u8 mbo_oui_type[1] = {0x16};
+/* MBO ATTR ID NON PREF CHAN REPORT */
+static const t_u8 mbo_attr_id[1] = {0x2};
+/********************************************************
+                Local Functions
+********************************************************/
+/** Dialog Token */
+static t_u8 mbo_dialog_token = 0;
+/********************************************************
+                Global functions
+********************************************************/
+
+/**
+ * @brief This function add MBO OUI.
+ *
+ * @param oui A pointer to MBO OCE element structure
+ *
+ * @return pointer incremented to the end of the element
+ */
+t_u8 *wlan_add_mbo_oui(t_u8 *oui)
+{
+    (void)memcpy(oui, mbo_oui, sizeof(mbo_oui));
+    return (oui + sizeof(mbo_oui));
+}
+
+/**
+ * @brief This function add MBO OUI TYPE.
+ *
+ * @param oui A pointer to MBO OCE element structure
+ *
+ * @return void
+ */
+t_u8 *wlan_add_mbo_oui_type(t_u8 *oui_type)
+{
+    (void)memcpy(oui_type, mbo_oui_type, sizeof(mbo_oui_type));
+    return (oui_type + sizeof(mbo_oui_type));
+}
+
+/**
+ * @brief This function add MBO Attributes id.
+ *
+ * @param oui A pointer to MBO OCE element structure
+ *
+ * @return void
+ */
+t_u8 *wlan_add_mbo_attr_id(t_u8 *attr_id)
+{
+    (void)memcpy(attr_id, mbo_attr_id, sizeof(mbo_attr_id));
+    return (attr_id + sizeof(mbo_attr_id));
+}
+
+/**
+ * @brief This function add cellular data CAP attribute into MBO OCE IE.
+ *
+ * @param oui A pointer to MBO OCE element structure
+ *
+ * @return void
+ */
+t_u8 *wlan_add_mbo_cellular_cap(t_u8 *attrib)
+{
+    attrib[0] = (t_u8)MBO_CELLULAR_DATA_CAP;
+    attrib[1] = 0x01;
+    attrib[2] = 0x03;
+    return (attrib + 3);
+}
+
+/**
+ * @brief This function add prefer or non-prefer channels into MBO OCE IE.
+ *
+ * @param oui A pointer to MBO OCE element structure
+ *
+ * @return void
+ */
+t_u8 *wlan_add_mbo_prefer_ch(t_u8 *attrib, t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1)
+{
+    t_u8 oper_class      = 0;
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    attrib[0] = (t_u8)MBO_NON_PERFER_CH_REPORT;
+    attrib[1] = 0x04;
+    (void)wlan_get_curr_global_oper_class(pmpriv, ch0, BW_20MHZ, &oper_class);
+    attrib[2] = oper_class; /*Wi-Fi CERTIFIED Agile Multiband. Test Plan v1.4 section 5.2.8. Set Global operating class
+                               to this field. */
+    attrib[3] = ch0;
+    attrib[4] = pefer0;
+    attrib[5] = 0;
+
+    attrib[6] = (t_u8)MBO_NON_PERFER_CH_REPORT;
+    attrib[7] = 0x04;
+    (void)wlan_get_curr_global_oper_class(pmpriv, ch1, BW_20MHZ, &oper_class);
+    attrib[8]  = oper_class;
+    attrib[9]  = ch1;
+    attrib[10] = pefer1;
+    attrib[11] = 0;
+    return (attrib + 12);
+}
+
+void wlan_send_mgmt_wnm_notification(
+    t_u8 *src_addr, t_u8 *dst_addr, t_u8 *target_bssid, t_u8 *tag_nr, t_u8 tag_len, bool protect)
+{
+    wlan_mgmt_pkt *pmgmt_pkt_hdr    = MNULL;
+    IEEEtypes_FrameCtl_t *mgmt_fc_p = MNULL;
+    t_u8 *pos                       = MNULL;
+    t_u16 pkt_len                   = 0;
+    t_u32 meas_pkt_len              = 0;
+
+    pmgmt_pkt_hdr = wifi_PrepDefaultMgtMsg(
+        SUBTYPE_ACTION, (mlan_802_11_mac_addr *)(void *)dst_addr, (mlan_802_11_mac_addr *)(void *)src_addr,
+        (mlan_802_11_mac_addr *)(void *)dst_addr, sizeof(wlan_mgmt_pkt) + WNM_NOTIFICATION_SIZE);
+    if (pmgmt_pkt_hdr == MNULL)
+    {
+        PRINTM(MERROR, "No memory available for BTM resp");
+        return;
+    }
+
+    mgmt_fc_p = (IEEEtypes_FrameCtl_t *)(void *)&pmgmt_pkt_hdr->wlan_header.frm_ctl;
+    if (protect)
+    {
+        mgmt_fc_p->wep = 1;
+    }
+
+    /* 802.11 management body */
+    pos    = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+    pos[0] = (t_u8)IEEE_MGMT_ACTION_CATEGORY_WNM;
+    pos[1] = (t_u8)IEEE_MGMT_WNM_NOTIFICATION_REQUEST;
+    pos[2] = mbo_dialog_token++;
+    pos[3] = 221; /* type */
+    pos += 4;
+    (void)memcpy(pos, tag_nr, tag_len);
+    pos += tag_len;
+
+    meas_pkt_len           = sizeof(wlan_mgmt_pkt) + 4U + (t_u32)tag_len;
+    pkt_len                = (t_u16)meas_pkt_len;
+    pmgmt_pkt_hdr->frm_len = (t_u16)pkt_len - (t_u16)sizeof(t_u16);
+    (void)wifi_inject_frame(WLAN_BSS_TYPE_STA, (t_u8 *)pmgmt_pkt_hdr, pkt_len);
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+}
+
+#endif /* CONFIG_DRIVER_MBO */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_misc.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_misc.c
new file mode 100644
index 0000000000..b6df9a28d2
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_misc.c
@@ -0,0 +1,1018 @@
+/** @file mlan_misc.c
+ *
+ *  @brief  This file provides Miscellaneous functions for MLAN module
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*************************************************************
+Change Log:
+    05/11/2009: initial version
+************************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+#include <mlan_fw.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+
+/**
+ *  @brief This function allocates a mlan_buffer.
+ *
+ *  @param pmadapter Pointer to mlan_adapter
+ *  @param data_len   Data length
+ *  @param head_room  head_room reserved in mlan_buffer
+ *  @param malloc_flag  flag to user moal_malloc
+ *  @return           mlan_buffer pointer or MNULL
+ */
+pmlan_buffer wlan_alloc_mlan_buffer(mlan_adapter *pmadapter, t_u32 data_len, t_u32 head_room, t_u32 malloc_flag)
+{
+    mlan_status ret    = MLAN_STATUS_SUCCESS;
+    pmlan_buffer pmbuf = MNULL;
+    t_u32 buf_size     = 0;
+    /* t_u8 *tmp_buf = MNULL; */
+    pmlan_callbacks pcb = &pmadapter->callbacks;
+
+    ENTER();
+
+    /* make sure that the data length is at least SDIO block size */
+    data_len = ALIGN_SZ(data_len, MLAN_SDIO_BLOCK_SIZE);
+
+    /* head_room is not implemented for malloc mlan buffer */
+    if (malloc_flag == MTRUE)
+    {
+        buf_size = sizeof(mlan_buffer) + data_len + DMA_ALIGNMENT;
+        ret =
+            pcb->moal_malloc(pmadapter->pmoal_handle, buf_size, MLAN_MEM_DEF | MLAN_MEM_DMA, (t_u8 **)(void **)&pmbuf);
+        if ((ret != MLAN_STATUS_SUCCESS) || (pmbuf == MNULL))
+        {
+            pmbuf = MNULL;
+            goto exit;
+        }
+        (void)__memset(pmadapter, pmbuf, 0, sizeof(mlan_buffer));
+
+        pmbuf->pdesc = MNULL;
+        /* Align address */
+        pmbuf->pbuf        = (t_u8 *)ALIGN_ADDR((t_u8 *)pmbuf + sizeof(mlan_buffer), DMA_ALIGNMENT);
+        pmbuf->data_offset = 0;
+        pmbuf->data_len    = data_len;
+        pmbuf->flags |= MLAN_BUF_FLAG_MALLOC_BUF;
+    }
+exit:
+    LEAVE();
+    return pmbuf;
+}
+
+/**
+ *  @brief This function frees a mlan_buffer.
+ *
+ *  @param pmadapter  Pointer to mlan_adapter
+ *  @param pmbuf      Pointer to mlan_buffer
+ *
+ *  @return           N/A
+ */
+t_void wlan_free_mlan_buffer(mlan_adapter *pmadapter, pmlan_buffer pmbuf)
+{
+    return;
+}
+
+
+/**
+ *  @brief This function will check if station list is empty
+ *
+ *  @param priv    A pointer to mlan_private
+ *
+ *  @return	   MFALSE/MTRUE
+ */
+t_u8 wlan_is_station_list_empty(mlan_private *priv)
+{
+    ENTER();
+    if (!(util_peek_list(priv->adapter->pmoal_handle, &priv->sta_list, priv->adapter->callbacks.moal_spin_lock,
+                         priv->adapter->callbacks.moal_spin_unlock)))
+    {
+        LEAVE();
+        return MTRUE;
+    }
+    LEAVE();
+    return MFALSE;
+}
+
+/**
+ *  @brief This function will return the pointer to station entry in station list
+ *  		table which matches the give mac address
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param mac     mac address to find in station list table
+ *
+ *  @return	   A pointer to structure sta_node
+ */
+sta_node *wlan_get_station_entry(mlan_private *priv, t_u8 *mac)
+{
+    sta_node *sta_ptr;
+
+    ENTER();
+
+    if (!mac)
+    {
+        LEAVE();
+        return MNULL;
+    }
+    if (!(sta_ptr = (sta_node *)util_peek_list(priv->adapter->pmoal_handle, &priv->sta_list,
+                                               priv->adapter->callbacks.moal_spin_lock,
+                                               priv->adapter->callbacks.moal_spin_unlock)))
+    {
+        LEAVE();
+        return MNULL;
+    }
+    while (sta_ptr != (sta_node *)&priv->sta_list)
+    {
+        if (!__memcmp(priv->adapter, sta_ptr->mac_addr, mac, MLAN_MAC_ADDR_LENGTH))
+        {
+            LEAVE();
+            return sta_ptr;
+        }
+        sta_ptr = sta_ptr->pnext;
+    }
+    LEAVE();
+    return MNULL;
+}
+
+/**
+ *  @brief This function will add a pointer to station entry in station list
+ *  		table with the give mac address, if it does not exist already
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param mac     mac address to find in station list table
+ *
+ *  @return	   A pointer to structure sta_node
+ */
+sta_node *wlan_add_station_entry(mlan_private *priv, t_u8 *mac)
+{
+    sta_node *sta_ptr       = MNULL;
+    mlan_adapter *pmadapter = priv->adapter;
+
+    ENTER();
+    pmadapter->callbacks.moal_spin_lock(pmadapter->pmoal_handle, priv->wmm.ra_list_spinlock);
+
+    sta_ptr = wlan_get_station_entry(priv, mac);
+    if (sta_ptr)
+        goto done;
+    if (priv->adapter->callbacks.moal_malloc(priv->adapter->pmoal_handle, sizeof(sta_node), MLAN_MEM_DEF,
+                                             (t_u8 **)&sta_ptr))
+    {
+        PRINTM(MERROR, "Failed to allocate memory for station node\n");
+        LEAVE();
+        return MNULL;
+    }
+    (void)__memset(priv->adapter, sta_ptr, 0, sizeof(sta_node));
+    (void)__memcpy(priv->adapter, sta_ptr->mac_addr, mac, MLAN_MAC_ADDR_LENGTH);
+    util_enqueue_list_tail(priv->adapter->pmoal_handle, &priv->sta_list, (pmlan_linked_list)sta_ptr,
+                           priv->adapter->callbacks.moal_spin_lock, priv->adapter->callbacks.moal_spin_unlock);
+done:
+    pmadapter->callbacks.moal_spin_unlock(pmadapter->pmoal_handle, priv->wmm.ra_list_spinlock);
+    LEAVE();
+    return sta_ptr;
+}
+
+/**
+ *  @brief This function will delete a station entry from station list
+ *
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param mac     station's mac address
+ *
+ *  @return	   N/A
+ */
+t_void wlan_delete_station_entry(mlan_private *priv, t_u8 *mac)
+{
+    sta_node *sta_ptr       = MNULL;
+    mlan_adapter *pmadapter = priv->adapter;
+    ENTER();
+    pmadapter->callbacks.moal_spin_lock(pmadapter->pmoal_handle, priv->wmm.ra_list_spinlock);
+    if ((sta_ptr = wlan_get_station_entry(priv, mac)))
+    {
+        util_unlink_list(priv->adapter->pmoal_handle, &priv->sta_list, (pmlan_linked_list)sta_ptr,
+                         priv->adapter->callbacks.moal_spin_lock, priv->adapter->callbacks.moal_spin_unlock);
+        priv->adapter->callbacks.moal_mfree(priv->adapter->pmoal_handle, (t_u8 *)sta_ptr);
+    }
+    pmadapter->callbacks.moal_spin_unlock(pmadapter->pmoal_handle, priv->wmm.ra_list_spinlock);
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief Clean up wapi station list
+ *
+ *  @param priv  Pointer to the mlan_private driver data struct
+ *
+ *  @return      N/A
+ */
+t_void wlan_delete_station_list(pmlan_private priv)
+{
+    sta_node *sta_ptr;
+
+    ENTER();
+    while ((sta_ptr = (sta_node *)util_dequeue_list(priv->adapter->pmoal_handle, &priv->sta_list,
+                                                    priv->adapter->callbacks.moal_spin_lock,
+                                                    priv->adapter->callbacks.moal_spin_unlock)))
+    {
+        priv->adapter->callbacks.moal_mfree(priv->adapter->pmoal_handle, (t_u8 *)sta_ptr);
+    }
+    LEAVE();
+    return;
+}
+
+
+
+/**
+ *   @brief This function processes the 802.11 mgmt Frame
+ *
+ *   @param priv      A pointer to mlan_private
+ *   @param payload   A pointer to the received buffer
+ *   @param payload_len Length of the received buffer
+ *
+ *   @return        MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_process_802dot11_mgmt_pkt(IN mlan_private *priv, IN t_u8 *payload, IN t_u32 payload_len, RxPD *rxpd)
+{
+    mlan_status ret                   = MLAN_STATUS_SUCCESS;
+    wlan_802_11_header *pieee_pkt_hdr = MNULL;
+    t_u16 sub_type                    = 0;
+    ENTER();
+    /* Check packet type-subtype and compare with mgmt_passthru_mask If event
+       is needed to host, just eventify it */
+    pieee_pkt_hdr = (wlan_802_11_header *)payload;
+    sub_type      = IEEE80211_GET_FC_MGMT_FRAME_SUBTYPE(pieee_pkt_hdr->frm_ctl);
+    if ((((1 << sub_type) & priv->mgmt_frame_passthru_mask) == 0) && (sub_type != SUBTYPE_ACTION))
+    {
+        PRINTM(MINFO, "Dropping mgmt frame for subtype %d.\n", sub_type);
+        LEAVE();
+        return ret;
+    }
+    switch (sub_type)
+    {
+        case SUBTYPE_ACTION:
+            ret = wlan_process_mgmt_action(payload, payload_len, rxpd);
+            if (ret == MLAN_STATUS_SUCCESS)
+            {
+                return ret;
+            }
+            break;
+        case SUBTYPE_ASSOC_REQUEST:
+        case SUBTYPE_REASSOC_REQUEST:
+        case SUBTYPE_DISASSOC:
+        case SUBTYPE_DEAUTH:
+        case SUBTYPE_AUTH:
+        case SUBTYPE_PROBE_RESP:
+            break;
+        default:
+            PRINTM(MINFO, "Unexpected pkt subtype \n");
+            break;
+    }
+    LEAVE();
+    return ret;
+}
+
+mlan_status wlan_bypass_802dot11_mgmt_pkt(void *data)
+{
+    RxPD *rxpd                        = (RxPD *)data;
+    wlan_mgmt_pkt *pmgmt_pkt_hdr      = NULL;
+    t_u16 sub_type                    = 0;
+    wlan_802_11_header *pieee_pkt_hdr = MNULL;
+    t_u8 category                     = 0;
+    mlan_private *priv                = mlan_adap->priv[0];
+    mlan_status ret                   = MLAN_STATUS_SUCCESS;
+
+    pmgmt_pkt_hdr = (wlan_mgmt_pkt *)((t_u8 *)rxpd + rxpd->rx_pkt_offset);
+    pieee_pkt_hdr = (wlan_802_11_header *)&pmgmt_pkt_hdr->wlan_header;
+    sub_type      = IEEE80211_GET_FC_MGMT_FRAME_SUBTYPE(pieee_pkt_hdr->frm_ctl);
+    // coverity[overrun-local:SUPPRESS]
+    category = *((t_u8 *)pieee_pkt_hdr + sizeof(wlan_802_11_header));
+
+    if ((pmgmt_pkt_hdr->wlan_header.frm_ctl & IEEE80211_FC_MGMT_FRAME_TYPE_MASK) == 0)
+    {
+        if ((((1 << sub_type) & priv->mgmt_frame_passthru_mask) == 0) && (sub_type != SUBTYPE_ACTION))
+        {
+            PRINTM(MINFO, "Dropping mgmt frame for subtype %d.\n", sub_type);
+            LEAVE();
+            return ret;
+        }
+
+        if (sub_type == SUBTYPE_ACTION)
+        {
+            if (category == IEEE_MGMT_ACTION_CATEGORY_BLOCK_ACK)
+            {
+                PRINTM(MINFO, "Dropping mgmt frame for category %d.\n", category);
+                LEAVE();
+                return ret;
+            }
+        }
+    }
+
+    ret = MLAN_STATUS_FAILURE;
+    return ret;
+}
+
+
+/**
+ *  @brief Add Extended Capabilities IE
+ *
+ *  @param pmpriv             A pointer to mlan_private structure
+ *  @param pptlv_out          A pointer to TLV to fill in
+ *  @param BSSDescriptor      A poiter to bss descriptor
+ *  @return                   N/A
+ */
+void wlan_add_ext_capa_info_ie(IN mlan_private *pmpriv, IN BSSDescriptor_t *pbss_desc, OUT t_u8 **pptlv_out)
+{
+    MrvlIETypes_ExtCap_t *pext_cap = MNULL;
+
+    ENTER();
+
+    pext_cap = (MrvlIETypes_ExtCap_t *)(void *)*pptlv_out;
+    (void)__memset(pmpriv->adapter, pext_cap, 0, sizeof(MrvlIETypes_ExtCap_t));
+    pext_cap->header.type = wlan_cpu_to_le16(EXT_CAPABILITY);
+    pext_cap->header.len  = wlan_cpu_to_le16(sizeof(ExtCap_t));
+    if ((((t_u8)(pmpriv->hotspot_cfg >> 8)) & HOTSPOT_ENABLE_INTERWORKING_IND) != 0U)
+    {
+        pext_cap->ext_cap.Interworking = 1;
+    }
+    if ((((t_u8)(pmpriv->hotspot_cfg >> 8)) & HOTSPOT_ENABLE_TDLS_IND) != 0U)
+    {
+        pext_cap->ext_cap.TDLSSupport = 1;
+    }
+
+#if (CONFIG_WNM_PS)
+    if ((((mlan_private *)mlan_adap->priv[0])->wnm_set == true) && (pbss_desc != MNULL) &&
+        (pbss_desc->pext_cap->ext_cap.WNM_Sleep == true))
+    {
+        pext_cap->ext_cap.WNM_Sleep = 1;
+    }
+    else
+    {
+        pext_cap->ext_cap.WNM_Sleep = 0;
+    }
+#endif
+#if CONFIG_11AX
+    if (pbss_desc && pbss_desc->multi_bssid_ap)
+        SET_EXTCAP_MULTI_BSSID(pext_cap->ext_cap);
+    if (wlan_check_11ax_twt_supported(pmpriv, pbss_desc))
+        SET_EXTCAP_TWT_REQ(pext_cap->ext_cap);
+#endif
+#if CONFIG_11V
+    pext_cap->ext_cap.BSS_Transition = 1;
+#endif
+#if CONFIG_11MC
+    pext_cap->ext_cap.FTMI          = 1;
+    pext_cap->ext_cap.CivicLocation = 1;
+#endif
+
+    *pptlv_out += sizeof(MrvlIETypes_ExtCap_t);
+
+    LEAVE();
+}
+
+
+/**
+ *  @brief Get rate index
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_rate_ioctl_get_rate_index(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_TX_RATE_CFG, HostCmd_ACT_GEN_GET, 0, (t_void *)pioctl_req, MNULL);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Set rate index
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_rate_ioctl_set_rate_index(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    t_s32 rate_index;
+    mlan_rate_format rate_format;
+#if (CONFIG_11AC) || (CONFIG_11AX)
+    t_u32 nss;
+#endif
+    t_u32 i;
+    mlan_ds_rate *ds_rate = MNULL;
+    mlan_status ret       = MLAN_STATUS_FAILURE;
+    mlan_private *pmpriv  = pmadapter->priv[pioctl_req->bss_index];
+    t_u16 bitmap_rates[MAX_BITMAP_RATES_SIZE];
+    t_u16 shift_index = 1U;
+
+    ENTER();
+
+    ds_rate = (mlan_ds_rate *)(void *)pioctl_req->pbuf;
+
+    rate_format = ds_rate->param.rate_cfg.rate_format;
+#if (CONFIG_11AC) || (CONFIG_11AX)
+    nss = ds_rate->param.rate_cfg.nss;
+#endif
+    rate_index = (t_s32)ds_rate->param.rate_cfg.rate;
+
+    if (ds_rate->param.rate_cfg.is_rate_auto == MTRUE)
+    {
+        (void)__memset(pmadapter, bitmap_rates, 0, sizeof(bitmap_rates));
+        /* Rates talbe [0]: HR/DSSS;[1]: OFDM; [2..9] HT; */
+        /* Support all HR/DSSS rates */
+        bitmap_rates[0] = 0x000F;
+        /* Support all OFDM rates */
+        bitmap_rates[1] = 0x00FF;
+        /* Support all HT-MCSs rate */
+        for (i = 2; i < 9U; i++)
+        {
+            bitmap_rates[i] = 0xFFFF;
+        }
+        bitmap_rates[9] = 0x3FFF;
+#if CONFIG_11AC
+        /* [10..17] VHT */
+#ifdef RW610
+        /* RW610 only supports VHT MCS0 ~ MCS8*/
+        bitmap_rates[10] = 0x01FF; /* 9 Bits valid */
+        /* RW610 only supports 1 NSS*/
+        bitmap_rates[11] = 0x0;
+#else
+        /* Support all VHT-MCSs rate for NSS 1 and 2 */
+        for (i = 10; i < 12; i++)
+        {
+            bitmap_rates[i] = 0x03FF; /* 10 Bits valid */
+        }
+#endif
+        /* Set to 0 as default value for all other NSSs */
+        for (i = 12; i < NELEMENTS(bitmap_rates); i++)
+        {
+            bitmap_rates[i] = 0x0;
+        }
+#endif
+#if CONFIG_11AX
+        /* [18..25] HE */
+#ifdef RW610
+        /* RW610 only supports HE MCS0 ~ MCS9*/
+        bitmap_rates[18] = 0x03FF; /* 10 Bits valid */
+        /* RW610 only supports 1 NSS*/
+        bitmap_rates[19] = 0x0;
+#else
+        /* Support all HE-MCSs rate for NSS1 and 2 */
+        for (i = 18; i < 20; i++)
+            bitmap_rates[i] = 0x0FFF;
+#endif
+        for (i = 20; i < NELEMENTS(bitmap_rates); i++)
+            bitmap_rates[i] = 0x0;
+#endif
+    }
+    else
+    {
+        PRINTM(MINFO, "Rate index is %d\n", rate_index);
+
+
+        (void)__memset(pmadapter, bitmap_rates, 0, sizeof(bitmap_rates));
+        if (rate_format == MLAN_RATE_FORMAT_LG)
+        {
+            /* Bitmap of HR/DSSS rates */
+            if (rate_index <= MLAN_RATE_INDEX_HRDSSS3)
+            {
+                bitmap_rates[0] = (shift_index << rate_index);
+                ret             = MLAN_STATUS_SUCCESS;
+                /* Bitmap of OFDM rates */
+            }
+            else if (rate_index <= MLAN_RATE_INDEX_OFDM7)
+            {
+                bitmap_rates[1] = (shift_index << (rate_index - MLAN_RATE_INDEX_OFDM0));
+                ret             = MLAN_STATUS_SUCCESS;
+            }
+            else
+            {
+                /*Do Nothing*/
+            }
+        }
+        else if (rate_format == MLAN_RATE_FORMAT_HT)
+        {
+            if (rate_index <= MLAN_RATE_INDEX_MCS32)
+            {
+#ifdef SD8801
+                rate_index -= MLAN_RATE_INDEX_MCS0;
+#endif
+                bitmap_rates[2 + (rate_index / 16)] = (shift_index << (rate_index % 16));
+                ret                                 = MLAN_STATUS_SUCCESS;
+            }
+        }
+        else
+        {
+            /*DO Nothing*/
+        }
+
+#if CONFIG_11AC
+        if (rate_format == MLAN_RATE_FORMAT_VHT)
+        {
+            if ((rate_index <= MLAN_RATE_INDEX_MCS9) && (MLAN_RATE_NSS1 <= nss) && (nss <= MLAN_RATE_NSS2))
+            {
+                bitmap_rates[10 + nss - MLAN_RATE_NSS1] = (shift_index << rate_index);
+                ret                                     = MLAN_STATUS_SUCCESS;
+            }
+        }
+#endif
+#if CONFIG_11AX
+        if (rate_format == MLAN_RATE_FORMAT_HE)
+        {
+            if (IS_FW_SUPPORT_11AX(pmadapter))
+            {
+                if ((rate_index <= MLAN_RATE_INDEX_MCS11) && (MLAN_RATE_NSS1 <= nss) && (nss <= MLAN_RATE_NSS2))
+                {
+                    bitmap_rates[18 + nss - MLAN_RATE_NSS1] = (1 << rate_index);
+                    ret                                     = MLAN_STATUS_SUCCESS;
+                }
+            }
+            else
+            {
+                PRINTM(MERROR, "Error! Fw doesn't support 11AX\n");
+                LEAVE();
+                return MLAN_STATUS_FAILURE;
+            }
+        }
+#endif
+        if (ret == MLAN_STATUS_FAILURE)
+        {
+            PRINTM(MERROR, "Invalid MCS index=%d. \n", rate_index);
+            pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+    }
+
+    PRINTM(MINFO,
+           "RateBitmap=%04x%04x%04x%04x%04x%04x%04x%04x"
+           "%04x%04x%04x%04x%04x%04x%04x%04x%04x%04x, "
+           "IsRateAuto=%d, DataRate=%d\n",
+           bitmap_rates[17], bitmap_rates[16], bitmap_rates[15], bitmap_rates[14], bitmap_rates[13], bitmap_rates[12],
+           bitmap_rates[11], bitmap_rates[10], bitmap_rates[9], bitmap_rates[8], bitmap_rates[7], bitmap_rates[6],
+           bitmap_rates[5], bitmap_rates[4], bitmap_rates[3], bitmap_rates[2], bitmap_rates[1], bitmap_rates[0],
+           pmpriv->is_data_rate_auto, pmpriv->data_rate);
+
+    /* Send request to firmware */
+#if CONFIG_AUTO_NULL_TX
+    if (ds_rate->auto_null_fixrate_enable == 1)
+    {
+        ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_TX_RATE_CFG, HostCmd_ACT_SPC_AUTO_SET, 0, (t_void *)pioctl_req,
+                               bitmap_rates);
+        ds_rate->auto_null_fixrate_enable = 0xff;
+    }
+    else if (ds_rate->auto_null_fixrate_enable == 0)
+    {
+        ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_TX_RATE_CFG, HostCmd_ACT_SPC_AUTO_NOSET, 0, (t_void *)pioctl_req,
+                               bitmap_rates);
+        ds_rate->auto_null_fixrate_enable = 0xff;
+    }
+    else
+#endif
+        ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_TX_RATE_CFG, HostCmd_ACT_GEN_SET, 0, (t_void *)pioctl_req,
+                               (t_void *)bitmap_rates);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Rate configuration command handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_rate_ioctl_cfg(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+        if (pioctl_req->action == MLAN_ACT_GET)
+        {
+            status = wlan_rate_ioctl_get_rate_index(pmadapter, pioctl_req);
+        }
+        else
+        {
+            status = wlan_rate_ioctl_set_rate_index(pmadapter, pioctl_req);
+        }
+
+    LEAVE();
+    return status;
+}
+
+/**
+ *  @brief This function prepares command of rf_antenna.
+ *
+ *  @param pmpriv   A pointer to mlan_private structure
+ *  @param cmd      A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_802_11_rf_antenna(IN pmlan_private pmpriv,
+                                       IN HostCmd_DS_COMMAND *cmd,
+                                       IN t_u16 cmd_action,
+                                       IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_RF_ANTENNA *pantenna = &cmd->params.antenna;
+    mlan_ds_ant_cfg_1x1 *ant_cfg_1x1 = (mlan_ds_ant_cfg_1x1 *)pdata_buf;
+
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RF_ANTENNA);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_RF_ANTENNA) + S_DS_GEN);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        pantenna->action        = wlan_cpu_to_le16(HostCmd_ACT_SET_BOTH);
+        pantenna->antenna_mode  = wlan_cpu_to_le16((t_u16)ant_cfg_1x1->antenna);
+        pantenna->evaluate_time = wlan_cpu_to_le16((t_u16)ant_cfg_1x1->evaluate_time);
+#ifdef RW610
+        pantenna->evaluate_mode = wlan_cpu_to_le16((t_u8)ant_cfg_1x1->evaluate_mode);
+#endif
+    }
+    else
+    {
+        pantenna->action        = wlan_cpu_to_le16(HostCmd_ACT_GET_BOTH);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if CONFIG_NET_MONITOR
+mlan_status wlan_cmd_802_11_net_monitor(IN pmlan_private pmpriv,
+                                        IN HostCmd_DS_COMMAND *cmd,
+                                        IN t_u16 cmd_action,
+                                        IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_NET_MONITOR *net_mon = &cmd->params.net_mon;
+    wifi_net_monitor_t *monitor            = (wifi_net_monitor_t *)pdata_buf;
+    ENTER();
+
+    (void)__memset(pmpriv->adapter, net_mon, 0x00, sizeof(HostCmd_DS_802_11_NET_MONITOR));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_NET_MONITOR);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_NET_MONITOR) + S_DS_GEN);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        net_mon->action                                         = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+        net_mon->monitor_activity                               = wlan_cpu_to_le16(monitor->monitor_activity);
+        net_mon->filter_flags                                   = wlan_cpu_to_le16(monitor->filter_flags);
+        net_mon->monitor_channel.header.type                    = TLV_TYPE_UAP_CHAN_BAND_CONFIG;
+        net_mon->monitor_channel.header.len                     = 2;
+        net_mon->monitor_channel.chan_band_param[0].radio_type  = (t_u8)monitor->radio_type;
+        net_mon->monitor_channel.chan_band_param[0].chan_number = (t_u8)monitor->chan_number;
+
+        net_mon->monitor_filter.header.type = TLV_TYPE_UAP_STA_MAC_ADDR_FILTER;
+        net_mon->monitor_filter.header.len  = MLAN_MAC_ADDR_LENGTH * monitor->filter_num + sizeof(t_u8);
+        net_mon->monitor_filter.filter_num  = (t_u8)monitor->filter_num;
+        __memcpy(priv->adapter, (t_u8 *)net_mon->monitor_filter.mac_list, (t_u8 *)monitor->mac_addr,
+                 MAX_MONIT_MAC_FILTER_NUM * MLAN_MAC_ADDR_LENGTH);
+    }
+    else
+    {
+        net_mon->action = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+
+#ifdef WLAN_LOW_POWER_ENABLE
+/**
+ *  @brief Set/Get Low Power Mode
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_misc_ioctl_low_pwr_mode(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret        = MLAN_STATUS_SUCCESS;
+    mlan_ds_misc_cfg *misc = MNULL;
+    mlan_private *pmpriv   = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+
+    misc = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_LOW_POWER_MODE, HostCmd_ACT_GEN_SET, 0, (t_void *)pioctl_req,
+                           &misc->param.low_pwr_mode);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+
+    LEAVE();
+    return ret;
+}
+#endif // WLAN_LOW_POWER_ENABLE
+
+#if CONFIG_WIFI_CLOCKSYNC
+/**
+ *  @brief Set/Get GPIO TSF Latch config
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+mlan_status wlan_misc_gpio_tsf_latch_config(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret            = MLAN_STATUS_SUCCESS;
+    mlan_ds_misc_cfg *misc_cfg = MNULL;
+    t_u16 cmd_action           = 0;
+    mlan_private *pmpriv       = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+
+    misc_cfg = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+        cmd_action = HostCmd_ACT_GEN_SET;
+    else
+        cmd_action = HostCmd_ACT_GEN_GET;
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG, cmd_action, 0, (t_void *)pioctl_req,
+                           &misc_cfg->param.gpio_tsf_latch_config);
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Get TSF info
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+mlan_status wlan_misc_get_tsf_info(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret            = MLAN_STATUS_SUCCESS;
+    mlan_ds_misc_cfg *misc_cfg = MNULL;
+    t_u16 cmd_action           = 0;
+    mlan_private *pmpriv       = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+
+    misc_cfg   = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+    cmd_action = HostCmd_ACT_GEN_GET;
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG, cmd_action, 0, (t_void *)pioctl_req,
+                           &misc_cfg->param.tsf_info);
+
+    LEAVE();
+    return ret;
+}
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+#if CONFIG_ECSA
+/**
+ *  @brief Get non-global operating class
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   Pointer to the IOCTL request buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_misc_ioctl_oper_class(pmlan_adapter pmadapter, mlan_ioctl_req *pioctl_req)
+{
+    pmlan_private pmpriv   = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_misc_cfg *misc = MNULL;
+    t_u8 channel, bandwidth, oper_class = 0;
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    misc    = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+    channel = misc->param.bw_chan_oper.channel;
+    switch (misc->param.bw_chan_oper.bandwidth)
+    {
+        case 20:
+            bandwidth = BW_20MHZ;
+            break;
+        case 40:
+            bandwidth = BW_40MHZ;
+            break;
+        case 80:
+            bandwidth = BW_80MHZ;
+            break;
+        default:
+            bandwidth = BW_20MHZ;
+            break;
+    }
+
+    if (pioctl_req->action == MLAN_ACT_GET)
+    {
+        ret                                 = wlan_get_curr_oper_class(pmpriv, channel, bandwidth, &oper_class);
+        misc->param.bw_chan_oper.oper_class = oper_class;
+    }
+    else
+    {
+        PRINTM(MERROR, "Unsupported cmd_action\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Check operating class validation
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   Pointer to the IOCTL request buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_misc_ioctl_operclass_validation(pmlan_adapter pmadapter, mlan_ioctl_req *pioctl_req)
+{
+    pmlan_private pmpriv   = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_misc_cfg *misc = MNULL;
+    t_u8 channel, oper_class;
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    misc       = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+    channel    = misc->param.bw_chan_oper.channel;
+    oper_class = misc->param.bw_chan_oper.oper_class;
+    if (pioctl_req->action == MLAN_ACT_GET)
+    {
+        ret = wlan_check_operclass_validation(pmpriv, channel, oper_class);
+    }
+    else
+    {
+        PRINTM(MERROR, "Unsupported cmd_action\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    LEAVE();
+    return ret;
+}
+#endif
+
+#if CONFIG_RF_TEST_MODE
+/**
+ *  @brief RF Test Mode config
+ *
+ *  @param pmadapter   A pointer to mlan_adapter structure
+ *  @param pioctl_req  A pointer to ioctl request buffer
+ *
+ *  @return        MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_misc_ioctl_rf_test_cfg(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_private *pmpriv    = MNULL;
+    mlan_ds_misc_cfg *pmisc = MNULL;
+    mlan_status ret         = MLAN_STATUS_FAILURE;
+    t_u16 cmd_action        = 0;
+
+    ENTER();
+
+    if (!pioctl_req)
+        goto done;
+
+    pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    pmisc  = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+
+    switch (pmisc->sub_command)
+    {
+        case MLAN_OID_MISC_RF_TEST_GENERIC:
+            if (pioctl_req->action == MLAN_ACT_SET)
+                cmd_action = HostCmd_ACT_GEN_SET;
+            else
+                cmd_action = HostCmd_ACT_GEN_GET;
+            ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_MFG_COMMAND, cmd_action, 0, (t_void *)pioctl_req,
+                                   &(pmisc->param.mfg_generic_cfg));
+            break;
+        case MLAN_OID_MISC_RF_TEST_TX_CONT:
+            if (pioctl_req->action == MLAN_ACT_SET)
+                cmd_action = HostCmd_ACT_GEN_SET;
+            else
+            {
+                PRINTM(MERROR, "Unsupported cmd_action\n");
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+            ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_MFG_COMMAND, cmd_action, 0, (t_void *)pioctl_req,
+                                   &(pmisc->param.mfg_tx_cont));
+            break;
+        case MLAN_OID_MISC_RF_TEST_TX_FRAME:
+            if (pioctl_req->action == MLAN_ACT_SET)
+                cmd_action = HostCmd_ACT_GEN_SET;
+            else
+            {
+                PRINTM(MERROR, "Unsupported cmd_action\n");
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+            ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_MFG_COMMAND, cmd_action, 0, (t_void *)pioctl_req,
+                                   &(pmisc->param.mfg_tx_frame2));
+            break;
+        case MLAN_OID_MISC_RF_TEST_CONFIG_TRIGGER_FRAME:
+            if (pioctl_req->action == MLAN_ACT_SET)
+                cmd_action = HostCmd_ACT_GEN_SET;
+            else
+            {
+                PRINTM(MERROR, "Unsupported cmd_action\n");
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+            ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_MFG_COMMAND, cmd_action, 0, (t_void *)pioctl_req,
+                                   &(pmisc->param.mfg_tx_trigger_config));
+            break;
+
+        case MLAN_OID_MISC_RF_TEST_HE_POWER:
+            if (pioctl_req->action == MLAN_ACT_SET)
+                cmd_action = HostCmd_ACT_GEN_SET;
+            else
+            {
+                PRINTM(MERROR, "Unsupported cmd_action\n");
+                ret = MLAN_STATUS_FAILURE;
+                goto done;
+            }
+            ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_MFG_COMMAND, cmd_action, 0, (t_void *)pioctl_req,
+                                   &(pmisc->param.mfg_he_power));
+            break;
+    }
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+done:
+    LEAVE();
+    return ret;
+}
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+/**
+ *  @brief Configure GPIO independent reset
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return             MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_misc_ioctl_ind_rst_cfg(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_private *pmpriv   = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_misc_cfg *misc = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+    mlan_status ret        = MLAN_STATUS_SUCCESS;
+    t_u16 cmd_action       = 0;
+
+    ENTER();
+
+    if (pioctl_req->action == MLAN_ACT_GET)
+        cmd_action = HostCmd_ACT_GEN_GET;
+    else
+        cmd_action = HostCmd_ACT_GEN_SET;
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_INDEPENDENT_RESET_CFG, cmd_action, 0, (t_void *)pioctl_req,
+                           (t_void *)&misc->param.ind_rst_cfg);
+
+    LEAVE();
+    return ret;
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_scan.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_scan.c
new file mode 100644
index 0000000000..76ea5b92a5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_scan.c
@@ -0,0 +1,5192 @@
+/** @file mlan_scan.c
+ *
+ *  @brief  This file provides wlan scan IOCTL and firmware command APIs
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/28/2008: initial version
+******************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+                Local Constants
+********************************************************/
+#if defined(RW610) || defined(SD9177)
+/** minimum scan time for passive to active scan */
+#define MIN_PASSIVE_TO_ACTIVE_SCAN_TIME 150
+#endif
+
+/** The maximum number of channels the firmware can scan per command */
+#define MRVDRV_MAX_CHANNELS_PER_SPECIFIC_SCAN 3
+
+/**
+ * Number of channels to scan per firmware scan command issuance.
+ *
+ * Number restricted to prevent hitting the limit on the amount of scan data
+ * returned in a single firmware scan command.
+ */
+#define MRVDRV_CHANNELS_PER_SCAN_CMD 4
+
+/** Memory needed to store a max sized Channel List TLV for a firmware scan */
+#define CHAN_TLV_MAX_SIZE \
+    (sizeof(MrvlIEtypesHeader_t) + (MRVDRV_MAX_CHANNELS_PER_SPECIFIC_SCAN * sizeof(ChanScanParamSet_t)))
+
+/** Memory needed to store supported rate */
+#define RATE_TLV_MAX_SIZE (sizeof(MrvlIEtypes_RatesParamSet_t) + HOSTCMD_SUPPORTED_RATES)
+
+/** Memory needed to store a max number/size WildCard SSID TLV for a firmware scan */
+#define WILDCARD_SSID_TLV_MAX_SIZE \
+    (MRVDRV_MAX_SSID_LIST_LENGTH * (sizeof(MrvlIEtypes_WildCardSsIdParamSet_t) + MRVDRV_MAX_SSID_LENGTH))
+
+/** WPS TLV MAX size is MAX IE size plus 2 bytes for t_u16 MRVL TLV extension */
+#define WPS_TLV_MAX_SIZE (sizeof(IEEEtypes_VendorSpecific_t) + 2)
+/** Maximum memory needed for a wlan_scan_cmd_config with all TLVs at max */
+#define MAX_SCAN_CFG_ALLOC                                                                          \
+    (sizeof(wlan_scan_cmd_config) + sizeof(MrvlIEtypes_NumProbes_t) + sizeof(MrvlIETypes_HTCap_t) + \
+     CHAN_TLV_MAX_SIZE + RATE_TLV_MAX_SIZE + WILDCARD_SSID_TLV_MAX_SIZE + WPS_TLV_MAX_SIZE)
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/* Global data required for split scan requests */
+static bool abort_split_scan;
+
+#if CONFIG_MEM_POOLS
+static BSSDescriptor_t s_bss_new_entry;
+static BSSDescriptor_t s2_bss_new_entry;
+#endif
+
+int get_split_scan_delay_ms(void);
+
+/**
+ * Interally used to send a configured scan cmd between driver routines
+ */
+typedef union
+{
+    /** Scan configuration (variable length) */
+    wlan_scan_cmd_config config;
+    /** Max allocated block */
+    t_u8 config_alloc_buf[MAX_SCAN_CFG_ALLOC];
+} wlan_scan_cmd_config_tlv;
+
+/********************************************************
+                Global Variables
+********************************************************/
+bool split_scan_in_progress;
+
+/********************************************************
+                Local Functions
+********************************************************/
+/** Cipher suite definition */
+typedef enum cipher_suite
+{
+    CIPHER_SUITE_TKIP,
+    CIPHER_SUITE_CCMP,
+    CIPHER_SUITE_MAX
+} cipher_suite;
+
+static t_u8 wpa_oui[CIPHER_SUITE_MAX][4] = {
+    {0x00, 0x50, 0xf2, 0x02}, /* TKIP */
+    {0x00, 0x50, 0xf2, 0x04}, /* AES */
+};
+
+static t_u8 rsn_oui[CIPHER_SUITE_MAX][4] = {
+    {0x00, 0x0f, 0xac, 0x02}, /* TKIP */
+    {0x00, 0x0f, 0xac, 0x04}, /* AES */
+};
+
+static t_u32 wlan_find_worst_network_in_list(const BSSDescriptor_t *pbss_desc, t_u32 num_entries);
+
+bool is_split_scan_complete(void)
+{
+    return (split_scan_in_progress == false);
+}
+
+/*
+ * wmsdk: Split scan needs to be aborted at times by the application. This
+ * API will help the caller do that.
+ */
+void wlan_abort_split_scan(void)
+{
+    if (split_scan_in_progress)
+    {
+        abort_split_scan = true;
+    }
+}
+
+/**
+ *  @brief This function will parse a given IE for a given OUI
+ *
+ *  Parse a given WPA/RSN IE to find if it has a given oui in PTK,
+ *  if no OUI found for PTK it returns 0.
+ *
+ *  @param pbss_desc       A pointer to current BSS descriptor
+ *  @return                0 on failure to find OUI, 1 on success.
+ */
+static t_u8 search_oui_in_ie(mlan_adapter *pmadapter, IEBody *ie_body, t_u8 *oui)
+{
+    t_u8 count;
+
+    count = ie_body->PtkCnt[0];
+
+    ENTER();
+    /* There could be multiple OUIs for PTK hence 1) Take the length. 2) Check
+       all the OUIs for AES. 3) If one of them is AES then pass success. */
+    while (count != 0U)
+    {
+        if (!__memcmp(pmadapter, ie_body->PtkBody, oui, sizeof(ie_body->PtkBody)))
+        {
+            LEAVE();
+            return MLAN_OUI_PRESENT;
+        }
+
+        --count;
+        if (count != 0U)
+        {
+            ie_body = (IEBody *)(void *)((t_u8 *)ie_body + sizeof(ie_body->PtkBody));
+        }
+    }
+
+    PRINTM(MINFO, "The OUI %x:%x:%x:%x is not found in PTK \n", oui[0], oui[1], oui[2], oui[3]);
+    LEAVE();
+    return MLAN_OUI_NOT_PRESENT;
+}
+
+/**
+ *  @brief This function will pass the correct ie and oui to search_oui_in_ie
+ *
+ *  Check the pbss_desc for appropriate IE and then check if RSN IE has AES
+ *  OUI in it. If RSN IE does not have AES in PTK then return 0;
+ *
+ *  @param pbss_desc       A pointer to current BSS descriptor
+ *  @return                0 on failure to find AES OUI, 1 on success.
+ */
+static t_u8 is_rsn_oui_present(mlan_adapter *pmadapter, BSSDescriptor_t *pbss_desc, cipher_suite cipher)
+{
+    t_u8 *oui       = MNULL;
+    IEBody *ie_body = MNULL;
+    t_u8 ret        = MLAN_OUI_NOT_PRESENT;
+
+    ENTER();
+    if (((pbss_desc->prsn_ie != MNULL) && ((*(pbss_desc->prsn_ie)).ieee_hdr.element_id == RSN_IE)))
+    {
+        ie_body = (IEBody *)(void *)(((t_u8 *)pbss_desc->prsn_ie->data) + RSN_GTK_OUI_OFFSET);
+        oui     = &rsn_oui[cipher][0];
+        if ((ret = search_oui_in_ie(pmadapter, ie_body, oui)) != 0U)
+        {
+            LEAVE();
+            return ret;
+        }
+    }
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function will pass the correct ie and oui to search_oui_in_ie
+ *
+ *  Check the pbss_desc for appropriate IE and then check if WPA IE has AES
+ *  OUI in it. If WPA IE does not have AES in PTK then return 0;
+ *
+ *  @param pbss_desc       A pointer to current BSS descriptor
+ *  @return                0 on failure to find AES OUI, 1 on success.
+ */
+static t_u8 is_wpa_oui_present(mlan_adapter *pmadapter, BSSDescriptor_t *pbss_desc, cipher_suite cipher)
+{
+    t_u8 *oui       = MNULL;
+    IEBody *ie_body = MNULL;
+    t_u8 ret        = MLAN_OUI_NOT_PRESENT;
+
+    ENTER();
+    if (((pbss_desc->pwpa_ie != MNULL) && ((*(pbss_desc->pwpa_ie)).vend_hdr.element_id == WPA_IE)))
+    {
+        ie_body = (IEBody *)(void *)pbss_desc->pwpa_ie->data;
+        oui     = &wpa_oui[(int)cipher][0];
+        if ((ret = search_oui_in_ie(pmadapter, ie_body, oui)) != 0U)
+        {
+            LEAVE();
+            return ret;
+        }
+    }
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Convert radio type scan parameter to a band config used in join cmd
+ *
+ *  @param radio_type Scan parameter indicating the radio used for a channel
+ *                    in a scan command.
+ *
+ *  @return          Band type conversion of scanBand used in join/assoc cmds
+ *
+ */
+static t_u16 radio_type_to_band(t_u8 radio_type)
+{
+    t_u16 ret_band;
+
+    switch (radio_type)
+    {
+        case HostCmd_SCAN_RADIO_TYPE_A:
+            ret_band = BAND_A;
+            break;
+        case HostCmd_SCAN_RADIO_TYPE_BG:
+        default:
+            ret_band = BAND_G;
+            break;
+    }
+
+    return ret_band;
+}
+
+#if CONFIG_SCAN_CHANNEL_GAP
+/**
+ *  @brief This function will update the channel statistics from scan result
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param pchanstats_tlv   A pointer to MrvlIEtypes_ChannelStats_t tlv
+ *
+ *  @return                NA
+ */
+static void wlan_update_chan_statistics(mlan_private *pmpriv, MrvlIEtypes_ChannelStats_t *pchanstats_tlv)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u8 i;
+    chan_statistics_t *pchan_stats = (chan_statistics_t *)((t_u8 *)pchanstats_tlv + sizeof(MrvlIEtypesHeader_t));
+    t_u8 num_chan                  = wlan_le16_to_cpu(pchanstats_tlv->header.len) / sizeof(chan_statistics_t);
+
+    ENTER();
+
+    for (i = 0; i < num_chan; i++)
+    {
+        if (pchan_stats->chan_num == 0U)
+        {
+            break;
+        }
+
+        if (pmadapter->idx_chan_stats >= pmadapter->num_in_chan_stats)
+        {
+            wifi_d("Over flow: idx_chan_stats=%d, num_in_chan_stats=%d", pmadapter->idx_chan_stats,
+                   pmadapter->num_in_chan_stats);
+            break;
+        }
+        pchan_stats->total_networks    = wlan_le16_to_cpu(pchan_stats->total_networks);
+        pchan_stats->cca_scan_duration = wlan_le16_to_cpu(pchan_stats->cca_scan_duration);
+        pchan_stats->cca_busy_duration = wlan_le16_to_cpu(pchan_stats->cca_busy_duration);
+        wifi_d("chan=%d, noise=%d, total_network=%d scan_duration=%d, busy_duration=%d", pchan_stats->chan_num,
+               pchan_stats->noise, pchan_stats->total_networks, pchan_stats->cca_scan_duration,
+               pchan_stats->cca_busy_duration);
+        __memcpy(pmadapter, (chan_statistics_t *)&pmadapter->pchan_stats[pmadapter->idx_chan_stats], pchan_stats,
+                 sizeof(chan_statistics_t));
+        pmadapter->idx_chan_stats++;
+        pchan_stats++;
+    }
+    LEAVE();
+    return;
+}
+#endif
+
+/**
+ *  @brief compare config band and a band from the scan result,
+ *  which is defined by functiion radio_type_to_band(t_u8 radio_type) above
+ *
+ *  @param cfg_band:  band configured
+ *         scan_band: band from scan result
+ *
+ *  @return  matched: non-zero. unmatched: 0
+ *
+ */
+static t_u8 wlan_is_band_compatible(t_u16 cfg_band, t_u16 scan_band)
+{
+    t_u16 band;
+    switch (scan_band)
+    {
+        case BAND_A:
+            band = (BAND_A | BAND_AN | BAND_AAC);
+            break;
+        case BAND_G:
+        default:
+            band = (BAND_B | BAND_G | BAND_GN | BAND_GAC);
+            break;
+    }
+    return (cfg_band & band);
+}
+
+
+/**
+ *  @brief Create a channel list for the driver to scan based on region info
+ *
+ *  Use the driver region/band information to construct a comprehensive list
+ *    of channels to scan.  This routine is used for any scan that is not
+ *    provided a specific channel list to scan.
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param puser_scan_in    MNULL or pointer to scan configuration parameters
+ *  @param pscan_chan_list  Output parameter: Resulting channel list to scan
+ *  @param filtered_scan    Flag indicating whether or not a BSSID or SSID filter
+ *                          is being sent in the command to firmware.  Used to
+ *                          increase the number of channels sent in a scan
+ *                          command and to disable the firmware channel scan
+ *                          filter.
+ *
+ *  @return                 N/A
+ */
+static t_void wlan_scan_create_channel_list(IN mlan_private *pmpriv,
+                                            IN const wlan_user_scan_cfg *puser_scan_in,
+                                            OUT ChanScanParamSet_t *pscan_chan_list,
+                                            IN t_u8 filtered_scan)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    region_chan_t *pscan_region;
+    const chan_freq_power_t *cfp;
+    t_u32 region_idx;
+    t_u32 chan_idx = 0;
+    t_u32 next_chan;
+    mlan_scan_type scan_type;
+    t_u8 radio_type;
+
+    ENTER();
+
+    for (region_idx = 0; region_idx < NELEMENTS(pmadapter->region_channel); region_idx++)
+    {
+        if (wlan_11d_support_is_enabled(pmpriv) && wlan_11d_is_enabled(pmpriv) && pmpriv->media_connected != MTRUE)
+        {
+            /* Scan all the supported chan for the first scan */
+            if (!pmadapter->universal_channel[region_idx].valid)
+            {
+                continue;
+            }
+            pscan_region = &pmadapter->universal_channel[region_idx];
+        }
+        else
+        {
+            if (!pmadapter->region_channel[region_idx].valid)
+            {
+                continue;
+            }
+            pscan_region = &pmadapter->region_channel[region_idx];
+        }
+
+        if ((puser_scan_in != MNULL) && !puser_scan_in->chan_list[0].chan_number &&
+            puser_scan_in->chan_list[0].radio_type & BAND_SPECIFIED)
+        {
+            radio_type = (t_u8)(puser_scan_in->chan_list[0].radio_type & ~BAND_SPECIFIED);
+            if (!radio_type && (pscan_region->band != BAND_B) && (pscan_region->band != BAND_G))
+            {
+                continue;
+            }
+            if (radio_type && (pscan_region->band != BAND_A))
+            {
+                continue;
+            }
+        }
+        if (!wlan_is_band_compatible(pmpriv->config_bands, pscan_region->band))
+        {
+            continue;
+        }
+        for (next_chan = 0; next_chan < pscan_region->num_cfp; next_chan++)
+        {
+            /* Set the default scan type to the user specified type, will later
+               be changed to passive on a per channel basis if restricted by
+               regulatory requirements (11d or 11h) */
+            scan_type = pmadapter->scan_type;
+            cfp       = pscan_region->pcfp + next_chan;
+            if ((cfp->dynamic.flags & NXP_CHANNEL_DISABLED) != 0U)
+            {
+                continue;
+            }
+
+            switch (pscan_region->band)
+            {
+#if CONFIG_5GHz_SUPPORT
+                case BAND_A:
+                    pscan_chan_list[chan_idx].radio_type = HostCmd_SCAN_RADIO_TYPE_A;
+                    /* 11D not available... play it safe on DFS channels */
+                    if (wlan_11h_radar_detect_required(pmpriv, (t_u8)cfp->channel))
+                    {
+                        /* Skip DFS channels if required */
+                        if (pmadapter->skip_dfs)
+                            continue;
+#if defined(RW610) || defined(SD9177)
+                        scan_type = MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE;
+#else
+                        scan_type = MLAN_SCAN_TYPE_PASSIVE;
+#endif
+                    }
+                    break;
+#endif
+                case BAND_B:
+                case BAND_G:
+                    if (wlan_bg_scan_type_is_passive(pmpriv, (t_u8)cfp->channel))
+                    {
+                        scan_type = MLAN_SCAN_TYPE_PASSIVE;
+                    }
+                    pscan_chan_list[chan_idx].radio_type = HostCmd_SCAN_RADIO_TYPE_BG;
+                    break;
+                default:
+                    pscan_chan_list[chan_idx].radio_type = HostCmd_SCAN_RADIO_TYPE_BG;
+                    break;
+            }
+
+            if ((puser_scan_in != MNULL) && puser_scan_in->chan_list[0].scan_time)
+            {
+                pscan_chan_list[chan_idx].max_scan_time =
+                    wlan_cpu_to_le16((t_u16)puser_scan_in->chan_list[0].scan_time);
+            }
+#if defined(RW610) || defined(SD9177)
+            else if (scan_type == MLAN_SCAN_TYPE_PASSIVE || scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE)
+#else
+            else if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+#endif
+            {
+                pscan_chan_list[chan_idx].max_scan_time = wlan_cpu_to_le16(pmadapter->passive_scan_time);
+            }
+            else if (filtered_scan != 0U)
+            {
+                pscan_chan_list[chan_idx].max_scan_time = wlan_cpu_to_le16(pmadapter->specific_scan_time);
+            }
+            else
+            {
+                pscan_chan_list[chan_idx].max_scan_time = wlan_cpu_to_le16(pmadapter->active_scan_time);
+            }
+
+#if defined(RW610) || defined(SD9177)
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE)
+            {
+                pscan_chan_list[chan_idx].max_scan_time =
+                    wlan_cpu_to_le16(MAX(pmadapter->passive_scan_time, MIN_PASSIVE_TO_ACTIVE_SCAN_TIME));
+                pscan_chan_list[chan_idx].chan_scan_mode.passive_to_active_scan = MTRUE;
+            }
+#endif
+#if defined(RW610) || defined(SD9177)
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE || scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE)
+#else
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+#endif
+            {
+                pscan_chan_list[chan_idx].chan_scan_mode.passive_scan       = MTRUE;
+                pscan_chan_list[chan_idx].chan_scan_mode.hidden_ssid_report = MTRUE;
+            }
+            else
+            {
+                pscan_chan_list[chan_idx].chan_scan_mode.passive_scan = MFALSE;
+            }
+
+            pscan_chan_list[chan_idx].chan_number = (t_u8)cfp->channel;
+
+#if defined(RW610) || defined(SD9177)
+            wscan_d("Channel: %d Type: %s %d", cfp->channel,
+                    scan_type == MLAN_SCAN_TYPE_PASSIVE           ? "Passive" :
+                    scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE ? "PassiveToActive" :
+                                                                    "Active",
+                    cfp->max_tx_power);
+#else
+            wscan_d("Channel: %d Type: %s %d", cfp->channel, scan_type == MLAN_SCAN_TYPE_PASSIVE ? "Passive" : "Active",
+                    cfp->max_tx_power);
+#endif
+            chan_idx++;
+        }
+    }
+
+    LEAVE();
+}
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+/**
+ *  @brief Add WPS IE to probe request frame
+ *
+ *  @param pmpriv             A pointer to mlan_private structure
+ *  @param pptlv_out          A pointer to TLV to fill in
+ *
+ *  @return                   N/A
+ */
+static void wlan_add_wps_probe_request_ie(IN mlan_private *pmpriv, OUT t_u8 **pptlv_out)
+{
+    MrvlIEtypesHeader_t *tlv;
+
+    ENTER();
+
+    if (pmpriv->wps.wps_ie.vend_hdr.len)
+    {
+        tlv       = (MrvlIEtypesHeader_t *)*pptlv_out;
+        tlv->type = wlan_cpu_to_le16(VENDOR_SPECIFIC_221);
+        tlv->len  = wlan_cpu_to_le16(pmpriv->wps.wps_ie.vend_hdr.len);
+        *pptlv_out += sizeof(MrvlIEtypesHeader_t);
+        (void)__memcpy(pmpriv->adapter, *pptlv_out, pmpriv->wps.wps_ie.vend_hdr.oui, pmpriv->wps.wps_ie.vend_hdr.len);
+        *pptlv_out += (pmpriv->wps.wps_ie.vend_hdr.len + sizeof(MrvlIEtypesHeader_t));
+        *pptlv_out += pmpriv->wps.wps_ie.vend_hdr.len;
+    }
+    LEAVE();
+}
+#endif
+
+/**
+ *  @brief Add IE to probe request frame
+ *
+ *  @param pmpriv             A pointer to mlan_private structure
+ *  @param pptlv_out          A pointer to TLV to fill in
+ *
+ *  @return                   N/A
+ */
+static void wlan_add_probe_request_ie(IN mlan_private *pmpriv, OUT t_u8 **pptlv_out)
+{
+    MrvlIEtypesHeader_t *tlv;
+    t_u8 *ies                     = MNULL;
+    t_u8 ies_len                  = 0;
+    t_u32 bytes_left              = 0;
+    t_u8 *pcurrent_ptr            = MNULL;
+    IEEEtypes_Header_t *pieee_hdr = MNULL;
+
+    ENTER();
+
+    if (pmpriv->default_scan_ies_len != 0)
+    {
+        ies     = pmpriv->default_scan_ies;
+        ies_len = pmpriv->default_scan_ies_len;
+    }
+    else if (pmpriv->gen_ie_buf_len != 0)
+    {
+        ies     = pmpriv->gen_ie_buf;
+        ies_len = pmpriv->gen_ie_buf_len;
+    }
+    else
+    {
+        return;
+    }
+
+    bytes_left   = ies_len;
+    pcurrent_ptr = ies;
+
+    while (bytes_left >= sizeof(IEEEtypes_Header_t))
+    {
+        pieee_hdr = (IEEEtypes_Header_t *)pcurrent_ptr;
+
+        if (pieee_hdr->element_id == EXT_CAPABILITY)
+        {
+            goto skip;
+        }
+
+        tlv       = (MrvlIEtypesHeader_t *)*pptlv_out;
+        tlv->type = wlan_cpu_to_le16(pieee_hdr->element_id);
+        tlv->len  = wlan_cpu_to_le16(pieee_hdr->len);
+        *pptlv_out += sizeof(MrvlIEtypesHeader_t);
+        (void)__memcpy(pmpriv->adapter, *pptlv_out, pcurrent_ptr + sizeof(IEEEtypes_Header_t), pieee_hdr->len);
+        *pptlv_out += pieee_hdr->len;
+
+    skip:
+        pcurrent_ptr += pieee_hdr->len + sizeof(IEEEtypes_Header_t);
+        bytes_left -= pieee_hdr->len + sizeof(IEEEtypes_Header_t);
+    }
+
+    LEAVE();
+}
+#endif
+
+/**
+ *  @brief Construct and send multiple scan config commands to the firmware
+ *
+ *  Previous routines have created a wlan_scan_cmd_config with any requested
+ *   TLVs.  This function splits the channel TLV into max_chan_per_scan lists
+ *   and sends the portion of the channel TLV along with the other TLVs
+ *   to the wlan_cmd routines for execution in the firmware.
+ *
+ *  @param pmpriv             A pointer to mlan_private structure
+ *  @param pioctl_buf         A pointer to MLAN IOCTL Request buffer
+ *  @param max_chan_per_scan  Maximum number channels to be included in each
+ *                            scan command sent to firmware
+ *  @param filtered_scan      Flag indicating whether or not a BSSID or SSID
+ *                            filter is being used for the firmware command
+ *                            scan command sent to firmware
+ *  @param pscan_cfg_out      Scan configuration used for this scan.
+ *  @param pchan_tlv_out      Pointer in the pscan_cfg_out where the channel TLV
+ *                            should start.  This is past any other TLVs that
+ *                            must be sent down in each firmware command.
+ *  @param pscan_chan_list    List of channels to scan in max_chan_per_scan segments
+ *
+ *  @return                   MLAN_STATUS_SUCCESS or error return otherwise
+ */
+static mlan_status wlan_scan_channel_list(IN mlan_private *pmpriv,
+                                          IN t_void *pioctl_buf,
+                                          IN t_u32 max_chan_per_scan,
+                                          IN t_u8 filtered_scan,
+                                          OUT wlan_scan_cmd_config *pscan_cfg_out,
+                                          OUT MrvlIEtypes_ChanListParamSet_t *pchan_tlv_out,
+                                          IN ChanScanParamSet_t *pscan_chan_list)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    MrvlIEtypes_ChanListParamSet_t *pchan_tlv_out_temp;
+    ChanScanParamSet_t *ptmp_chan_list;
+    ChanScanParamSet_t *pstart_chan;
+    pmlan_ioctl_req pioctl_req = (mlan_ioctl_req *)pioctl_buf;
+
+    t_u32 tlv_idx;
+    t_u32 total_scan_time;
+    t_u32 done_early;
+    t_u32 cmd_no;
+
+#if CONFIG_11AX
+    MrvlIEtypes_Extension_t *phe_cap;
+    t_u16 len = 0;
+#endif
+
+    ENTER();
+
+    if ((pscan_cfg_out == MNULL) || (pchan_tlv_out == MNULL) || (pscan_chan_list == MNULL))
+    {
+        PRINTM(MINFO, "Scan: Null detect: %p, %p, %p\n", pscan_cfg_out, pchan_tlv_out, pscan_chan_list);
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_CMD_SCAN_FAIL;
+        }
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    if (!pscan_chan_list->chan_number)
+    {
+        PRINTM(MERROR, "Scan: No channel configured\n");
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_CMD_SCAN_FAIL;
+        }
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    pchan_tlv_out->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+
+    pchan_tlv_out_temp = pchan_tlv_out;
+
+    /* Set the temp channel struct pointer to the start of the desired list */
+    ptmp_chan_list = pscan_chan_list;
+
+    if (pmpriv->roaming_configured)
+    {
+        pmpriv->roaming_configured = MFALSE;
+        /* Cancel bg scan */
+        ret = wifi_stop_bgscan();
+        if (ret)
+            return MLAN_STATUS_FAILURE;
+    }
+
+    /* Loop through the desired channel list, sending a new firmware scan
+       commands for each max_chan_per_scan channels (or for 1,6,11 individually
+       if configured accordingly) */
+    while (ptmp_chan_list->chan_number != 0U)
+    {
+        tlv_idx                   = 0;
+        total_scan_time           = 0;
+        pchan_tlv_out->header.len = 0;
+        pstart_chan               = ptmp_chan_list;
+        done_early                = MFALSE;
+
+        t_u8 *ptlv_pos = (t_u8 *)pchan_tlv_out_temp;
+        MrvlIEtypes_RatesParamSet_t *prates_tlv;
+        t_u16 config_bands;
+        WLAN_802_11_RATES rates;
+        t_u32 rates_size;
+
+        config_bands = pmpriv->config_bands;
+        if (pstart_chan->chan_number > MAX_CHANNELS_BG)
+        {
+            config_bands &= ~(BAND_B | BAND_G | BAND_GN
+#if CONFIG_11AC
+                              | BAND_GAC
+#endif
+#if CONFIG_11AX
+                              | BAND_GAX
+#endif
+            );
+        }
+        else
+        {
+#if CONFIG_11AX
+            config_bands &= ~(BAND_AAX);
+#endif
+        }
+
+        config_bands = (pmpriv->bss_mode == MLAN_BSS_MODE_INFRA) ? config_bands : pmadapter->adhoc_start_band;
+
+        /* Append rates tlv */
+        (void)__memset(pmadapter, rates, 0, sizeof(rates));
+        rates_size              = wlan_get_supported_rates(pmpriv, pmpriv->bss_mode, config_bands, rates);
+        prates_tlv              = (MrvlIEtypes_RatesParamSet_t *)ptlv_pos;
+        prates_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_RATES);
+        prates_tlv->header.len  = wlan_cpu_to_le16((t_u16)rates_size);
+
+        if (rates_size != 0U && rates_size <= sizeof(prates_tlv->rates))
+        {
+            (void)__memcpy(pmadapter, prates_tlv->rates, rates, rates_size);
+        }
+
+        ptlv_pos += sizeof(prates_tlv->header) + rates_size;
+        PRINTM(MINFO, "SCAN_CMD: Rates size = %d\n", rates_size);
+
+#if CONFIG_11AX
+        if (IS_FW_SUPPORT_11AX(pmadapter) && ((config_bands & BAND_GAX) || (config_bands & BAND_AAX)))
+        {
+            phe_cap = (MrvlIEtypes_Extension_t *)ptlv_pos;
+            len     = wlan_fill_he_cap_tlv(pmpriv, config_bands, phe_cap, MFALSE);
+            HEXDUMP("SCAN: HE_CAPABILITIES IE", (t_u8 *)phe_cap, len);
+            ptlv_pos += len;
+        }
+#endif
+
+        pchan_tlv_out              = (MrvlIEtypes_ChanListParamSet_t *)ptlv_pos;
+        pchan_tlv_out->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+        pchan_tlv_out->header.len  = 0;
+
+        /*
+         * Construct the Channel TLV for the scan command.  Continue to
+         * insert channel TLVs until:
+         *   - the tlv_idx hits the maximum configured per scan command
+         *   - the next channel to insert is 0 (end of desired channel list)
+         *   - done_early is set (controlling individual scanning of 1,6,11)
+         */
+        while (tlv_idx < max_chan_per_scan && ptmp_chan_list->chan_number && !done_early)
+        {
+            wscan_d("Scan: Chan(%3d), Radio(%d), Mode(%d,%d), Dur(%d)", ptmp_chan_list->chan_number,
+                    ptmp_chan_list->radio_type, ptmp_chan_list->chan_scan_mode.passive_scan,
+                    ptmp_chan_list->chan_scan_mode.disable_chan_filt, wlan_le16_to_cpu(ptmp_chan_list->max_scan_time));
+
+            /* Copy the current channel TLV to the command being prepared */
+            (void)__memcpy(pmadapter, pchan_tlv_out->chan_scan_param + tlv_idx, ptmp_chan_list,
+                           sizeof(pchan_tlv_out->chan_scan_param));
+
+            /* Increment the TLV header length by the size appended */
+            pchan_tlv_out->header.len += (t_u16)sizeof(pchan_tlv_out->chan_scan_param);
+
+            /*
+             * The tlv buffer length is set to the number of bytes of the
+             *   between the channel tlv pointer and the start of the
+             *   tlv buffer.  This compensates for any TLVs that were appended
+             *   before the channel list.
+             */
+            pscan_cfg_out->tlv_buf_len = (t_u32)((t_u8 *)pchan_tlv_out - pscan_cfg_out->tlv_buf);
+
+            /* Add the size of the channel tlv header and the data length */
+            pscan_cfg_out->tlv_buf_len += (sizeof(pchan_tlv_out->header) + pchan_tlv_out->header.len);
+
+            /* Increment the index to the channel tlv we are constructing */
+            tlv_idx++;
+
+            /* Count the total scan time per command */
+            total_scan_time += wlan_le16_to_cpu(ptmp_chan_list->max_scan_time);
+
+            done_early = MFALSE;
+
+            /* Stop the loop if the *current* channel is in the 1,6,11 set and
+               we are not filtering on a BSSID or SSID. */
+            if (!filtered_scan && (ptmp_chan_list->chan_number == 1U || ptmp_chan_list->chan_number == 6U ||
+                                   ptmp_chan_list->chan_number == 11U))
+            {
+                done_early = MTRUE;
+            }
+
+            /* Increment the tmp pointer to the next channel to be scanned */
+            ptmp_chan_list++;
+
+            /* Stop the loop if the *next* channel is in the 1,6,11 set.  This
+               will cause it to be the only channel scanned on the next
+               interation */
+            if (!filtered_scan && (ptmp_chan_list->chan_number == 1U || ptmp_chan_list->chan_number == 6U ||
+                                   ptmp_chan_list->chan_number == 11U))
+            {
+                done_early = MTRUE;
+            }
+
+            /* Stop the loop if the *next* channel is 36. Get supported rates for 2G/5G channels seperately */
+            if (ptmp_chan_list->chan_number == 36)
+            {
+                done_early = MTRUE;
+            }
+        }
+
+        /* The total scan time should be less than scan command timeout value */
+        if (total_scan_time > MRVDRV_MAX_TOTAL_SCAN_TIME)
+        {
+            wscan_d("Total scan time %d ms is over limit (%d ms), scan skipped", total_scan_time,
+                    MRVDRV_MAX_TOTAL_SCAN_TIME);
+            if (pioctl_req != MNULL)
+            {
+                pioctl_req->status_code = MLAN_ERROR_CMD_SCAN_FAIL;
+            }
+            ret = MLAN_STATUS_FAILURE;
+            break;
+        }
+
+        pchan_tlv_out->header.len = wlan_cpu_to_le16(pchan_tlv_out->header.len);
+
+        pmadapter->pscan_channels = pstart_chan;
+
+        /* Do sleep confirm handshake if received sleep event.
+         * Fw will delay all events if handshake is not done
+         * yet after ps sleep event.
+         */
+        if (mlan_adap->ps_state == PS_STATE_PRE_SLEEP && split_scan_in_progress)
+        {
+            send_sleep_confirm_command((mlan_bss_type)WLAN_BSS_TYPE_STA);
+        }
+
+        if (!ptmp_chan_list->chan_number)
+        {
+            /* wmsdk: Once we set this the response handling code can
+               send event to the WLC manager. Since the event is send
+               only after command response we can be sure that there
+               is no race condition */
+            split_scan_in_progress = false;
+        }
+
+        /* Send the scan command to the firmware with the specified cfg */
+#if CONFIG_EXT_SCAN_SUPPORT
+        if (pmadapter->ext_scan)
+        {
+            cmd_no = HostCmd_CMD_802_11_SCAN_EXT;
+        }
+        else
+#endif
+        {
+            cmd_no = HostCmd_CMD_802_11_SCAN;
+        }
+        ret = wlan_prepare_cmd(pmpriv, (t_u16)cmd_no, HostCmd_ACT_GEN_SET, 0, pioctl_buf, pscan_cfg_out);
+        if (ret != MLAN_STATUS_SUCCESS)
+        {
+            break;
+        }
+
+        if (pmpriv->media_connected == MTRUE)
+        {
+            OSA_TimeDelay((uint32_t)get_split_scan_delay_ms());
+        }
+
+        if (abort_split_scan)
+        {
+#if CONFIG_WPA_SUPP
+            BSSDescriptor_t *bss_entry = NULL;
+            int i;
+#endif
+            abort_split_scan       = false;
+            split_scan_in_progress = false;
+#if CONFIG_WPA_SUPP
+            for (i = 0; i < pmadapter->num_in_scan_table; i++)
+            {
+                bss_entry = &pmadapter->pscan_table[i];
+                if (bss_entry && bss_entry->ies != NULL)
+                {
+                    OSA_MemoryFree(bss_entry->ies);
+                }
+            }
+
+            pmadapter->num_in_scan_table = 0;
+            ret                          = MLAN_STATUS_FAILURE;
+#endif
+            break;
+        }
+    }
+
+    LEAVE();
+
+    if (ret != MLAN_STATUS_SUCCESS)
+    {
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Construct a wlan_scan_cmd_config structure to use in scan commands
+ *
+ *  Application layer or other functions can invoke wlan_scan_networks
+ *    with a scan configuration supplied in a wlan_ioctl_user_scan_cfg struct.
+ *    This structure is used as the basis of one or many wlan_scan_cmd_config
+ *    commands that are sent to the command processing module and sent to
+ *    firmware.
+ *
+ *  Create a wlan_scan_cmd_config based on the following user supplied
+ *    parameters (if present):
+ *             - SSID filter
+ *             - BSSID filter
+ *             - Number of Probes to be sent
+ *             - Channel list
+ *
+ *  If the SSID or BSSID filter is not present, disable/clear the filter.
+ *  If the number of probes is not set, use the adapter default setting
+ *  Qualify the channel
+ *
+ *  @param pmpriv              A pointer to mlan_private structure
+ *  @param puser_scan_in       MNULL or pointer to scan config parameters
+ *  @param pscan_cfg_out       Output parameter: Resulting scan configuration
+ *  @param ppchan_list_out     Output parameter: Pointer to the start of the
+ *                             channel TLV portion of the output scan config
+ *  @param pscan_chan_list     Output parameter: Pointer to the resulting
+ *                             channel list to scan
+ *  @param pmax_chan_per_scan  Output parameter: Number of channels to scan for
+ *                             each issuance of the firmware scan command
+ *  @param pfiltered_scan      Output parameter: Flag indicating whether or not
+ *                             a BSSID or SSID filter is being sent in the
+ *                             command to firmware. Used to increase the number
+ *                             of channels sent in a scan command and to
+ *                             disable the firmware channel scan filter.
+ *  @param pscan_current_only  Output parameter: Flag indicating whether or not
+ *                             we are only scanning our current active channel
+ *
+ *  @return                 MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_scan_setup_scan_config(IN mlan_private *pmpriv,
+                                               IN const wlan_user_scan_cfg *puser_scan_in,
+                                               OUT wlan_scan_cmd_config *pscan_cfg_out,
+                                               OUT MrvlIEtypes_ChanListParamSet_t **ppchan_list_out,
+                                               OUT ChanScanParamSet_t *pscan_chan_list,
+                                               OUT t_u8 *pmax_chan_per_scan,
+                                               OUT t_u8 *pfiltered_scan,
+                                               OUT t_u8 *pscan_current_only)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    MrvlIEtypes_NumProbes_t *pnum_probes_tlv;
+    MrvlIEtypes_WildCardSsIdParamSet_t *pwildcard_ssid_tlv;
+#if CONFIG_EXT_SCAN_SUPPORT
+    MrvlIEtypes_Bssid_List_t *pbssid_tlv;
+#endif
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    MrvlIEtypes_RssiThresholdParamSet_t *prssi_threshold_tlv;
+#endif
+    const t_u8 zero_mac[MLAN_MAC_ADDR_LENGTH] = {0, 0, 0, 0, 0, 0};
+    t_u8 *ptlv_pos;
+    t_u32 num_probes;
+    t_u32 ssid_len;
+    t_u32 chan_idx;
+    mlan_scan_type scan_type;
+    t_u16 scan_dur;
+    t_u8 channel;
+    t_u8 radio_type;
+    t_u32 ssid_idx;
+    t_u8 ssid_filter;
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    t_u8 rssi_threshold_enable;
+    t_s16 rssi_threshold;
+#endif
+    MrvlIETypes_HTCap_t *pht_cap;
+#if CONFIG_11AC
+    MrvlIETypes_VHTCap_t *pvht_cap;
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+    MrvlIEtypes_ScanChanGap_t *pscan_gap_tlv;
+#endif
+    ENTER();
+
+    pmpriv->ssid_filter = MFALSE;
+    (void)memset(&pmpriv->filter_ssid[0], 0x00, sizeof(pmpriv->filter_ssid));
+
+    /* The tlv_buf_len is calculated for each scan command.  The TLVs added in
+       this routine will be preserved since the routine that sends the command
+       will append channelTLVs at *ppchan_list_out.  The difference between the
+       *ppchan_list_out and the tlv_buf start will be used to calculate the
+       size of anything we add in this routine. */
+    pscan_cfg_out->tlv_buf_len = 0;
+
+    /* Running tlv pointer.  Assigned to ppchan_list_out at end of function so
+       later routines know where channels can be added to the command buf */
+    ptlv_pos = pscan_cfg_out->tlv_buf;
+
+    /* Initialize the scan as un-filtered; the flag is later set to TRUE below
+       if a SSID or BSSID filter is sent in the command */
+    *pfiltered_scan = MFALSE;
+
+    /* Initialize the scan as not being only on the current channel.  If the
+       channel list is customized, only contains one channel, and is the active
+       channel, this is set true and data flow is not halted. */
+    *pscan_current_only = MFALSE;
+
+    if (puser_scan_in != MNULL)
+    {
+        ssid_filter = MFALSE;
+
+        /* Set the bss type scan filter, use Adapter setting if unset */
+        pscan_cfg_out->bss_mode =
+            (puser_scan_in->bss_mode ? (t_u8)puser_scan_in->bss_mode : (t_u8)pmadapter->scan_mode);
+
+        /* Set the number of probes to send, use Adapter setting if unset */
+        num_probes = (puser_scan_in->num_probes ? puser_scan_in->num_probes : pmadapter->scan_probes);
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+        /* Set the threshold value of rssi to send */
+        rssi_threshold = puser_scan_in->rssi_threshold;
+        /* Enable/Disable rssi threshold function */
+        rssi_threshold_enable = (rssi_threshold < 0 ? MTRUE : MFALSE);
+#endif
+        /*
+         * Set the BSSID filter to the incoming configuration,
+         *   if non-zero.  If not set, it will remain disabled (all zeros).
+         */
+        (void)__memcpy(pmadapter, pscan_cfg_out->specific_bssid, puser_scan_in->specific_bssid,
+                       sizeof(pscan_cfg_out->specific_bssid));
+
+#if CONFIG_EXT_SCAN_SUPPORT
+        if (pmadapter->ext_scan && __memcmp(pmadapter, pscan_cfg_out->specific_bssid, &zero_mac, sizeof(zero_mac)))
+        {
+            pbssid_tlv              = (MrvlIEtypes_Bssid_List_t *)ptlv_pos;
+            pbssid_tlv->header.type = TLV_TYPE_BSSID;
+            pbssid_tlv->header.len  = MLAN_MAC_ADDR_LENGTH;
+            (void)__memcpy(pmadapter, pbssid_tlv->bssid, puser_scan_in->specific_bssid, MLAN_MAC_ADDR_LENGTH);
+            ptlv_pos += sizeof(MrvlIEtypes_Bssid_List_t);
+        }
+#endif
+
+        for (ssid_idx = 0; ((ssid_idx < NELEMENTS(puser_scan_in->ssid_list)) &&
+                            (*puser_scan_in->ssid_list[ssid_idx].ssid || puser_scan_in->ssid_list[ssid_idx].max_len));
+             ssid_idx++)
+        {
+            ssid_len = wlan_strlen((const char *)puser_scan_in->ssid_list[ssid_idx].ssid);
+
+            pwildcard_ssid_tlv                  = (MrvlIEtypes_WildCardSsIdParamSet_t *)(void *)ptlv_pos;
+            pwildcard_ssid_tlv->header.type     = wlan_cpu_to_le16(TLV_TYPE_WILDCARDSSID);
+            pwildcard_ssid_tlv->header.len      = (t_u16)(ssid_len + sizeof(pwildcard_ssid_tlv->max_ssid_length));
+            pwildcard_ssid_tlv->max_ssid_length = puser_scan_in->ssid_list[ssid_idx].max_len;
+
+            if ((ssid_len > 0) && (ssid_len <= MLAN_MAX_SSID_LENGTH))
+            {
+                (void)__memcpy(pmadapter, pwildcard_ssid_tlv->ssid, puser_scan_in->ssid_list[ssid_idx].ssid,
+                               MIN(MLAN_MAX_SSID_LENGTH, ssid_len));
+            }
+
+            ptlv_pos += (sizeof(pwildcard_ssid_tlv->header) + pwildcard_ssid_tlv->header.len);
+
+            pwildcard_ssid_tlv->header.len = wlan_cpu_to_le16(pwildcard_ssid_tlv->header.len);
+
+            PRINTM(MINFO, "Scan: ssid_list[%d]: %s, %d\n", ssid_idx, pwildcard_ssid_tlv->ssid,
+                   pwildcard_ssid_tlv->max_ssid_length);
+
+            if (ssid_len != 0U)
+            {
+                ssid_filter = MTRUE;
+                (void)__memcpy(pmadapter, pmpriv->filter_ssid[ssid_idx].ssid, puser_scan_in->ssid_list[ssid_idx].ssid,
+                               MIN(MLAN_MAX_SSID_LENGTH, ssid_len));
+                pmpriv->filter_ssid[ssid_idx].ssid_len = ssid_len;
+            }
+        }
+
+        /*
+         *  The default number of channels sent in the command is low to
+         *    ensure the response buffer from the firmware does not truncate
+         *    scan results.  That is not an issue with an SSID or BSSID
+         *    filter applied to the scan results in the firmware.
+         */
+        if ((ssid_idx && ssid_filter) ||
+            __memcmp(pmadapter, pscan_cfg_out->specific_bssid, &zero_mac, sizeof(zero_mac)))
+        {
+            if (ssid_filter)
+            {
+                pmpriv->ssid_filter = ssid_filter;
+            }
+            *pfiltered_scan = MTRUE;
+        }
+    }
+    else
+    {
+        pscan_cfg_out->bss_mode = (t_u8)pmadapter->scan_mode;
+        num_probes              = pmadapter->scan_probes;
+#if CONFIG_SCAN_WITH_RSSIFILTER
+        rssi_threshold        = 0;
+        rssi_threshold_enable = 0;
+#endif
+    }
+
+    /*
+     *  If a specific BSSID or SSID is used, the number of channels in the
+     *  scan command will be increased to the absolute maximum.
+     */
+    if (*pfiltered_scan == MTRUE)
+    {
+        *pmax_chan_per_scan = MRVDRV_MAX_CHANNELS_PER_SPECIFIC_SCAN;
+    }
+    else
+    {
+        *pmax_chan_per_scan = MRVDRV_CHANNELS_PER_SCAN_CMD;
+    }
+#if CONFIG_SCAN_CHANNEL_GAP
+    if (puser_scan_in)
+    {
+        if (puser_scan_in->scan_chan_gap)
+        {
+            *pmax_chan_per_scan = MRVDRV_MAX_CHANNELS_PER_SPECIFIC_SCAN;
+            PRINTM(MCMND, "Scan: channel gap = 0x%x\n", puser_scan_in->scan_chan_gap);
+            pscan_gap_tlv              = (MrvlIEtypes_ScanChanGap_t *)ptlv_pos;
+            pscan_gap_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_SCAN_CHANNEL_GAP);
+            pscan_gap_tlv->header.len  = sizeof(pscan_gap_tlv->gap);
+            pscan_gap_tlv->gap         = wlan_cpu_to_le16((t_u16)puser_scan_in->scan_chan_gap);
+            ptlv_pos += sizeof(pscan_gap_tlv->header) + pscan_gap_tlv->header.len;
+            pscan_gap_tlv->header.len = wlan_cpu_to_le16(pscan_gap_tlv->header.len);
+        }
+    }
+    else if (pmadapter->scan_chan_gap)
+    {
+        *pmax_chan_per_scan = MRVDRV_MAX_CHANNELS_PER_SPECIFIC_SCAN;
+        PRINTM(MCMND, "Scan: channel gap = 0x%x\n", pmadapter->scan_chan_gap);
+        pscan_gap_tlv              = (MrvlIEtypes_ScanChanGap_t *)ptlv_pos;
+        pscan_gap_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_SCAN_CHANNEL_GAP);
+        pscan_gap_tlv->header.len  = sizeof(pscan_gap_tlv->gap);
+        pscan_gap_tlv->gap         = wlan_cpu_to_le16((t_u16)pmadapter->scan_chan_gap);
+        ptlv_pos += sizeof(pscan_gap_tlv->header) + pscan_gap_tlv->header.len;
+        pscan_gap_tlv->header.len = wlan_cpu_to_le16(pscan_gap_tlv->header.len);
+    }
+#endif
+    /* If the input config or adapter has the number of Probes set, add tlv */
+    if (num_probes != 0U)
+    {
+        PRINTM(MINFO, "Scan: num_probes = %d\n", num_probes);
+
+        pnum_probes_tlv              = (MrvlIEtypes_NumProbes_t *)(void *)ptlv_pos;
+        pnum_probes_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_NUMPROBES);
+        pnum_probes_tlv->header.len  = (t_u16)sizeof(pnum_probes_tlv->num_probes);
+        pnum_probes_tlv->num_probes  = wlan_cpu_to_le16((t_u16)num_probes);
+
+        ptlv_pos += sizeof(pnum_probes_tlv->header) + pnum_probes_tlv->header.len;
+
+        pnum_probes_tlv->header.len = wlan_cpu_to_le16(pnum_probes_tlv->header.len);
+    }
+
+    if (ISSUPP_11NENABLED(pmpriv->adapter->fw_cap_info) &&
+        (pmpriv->config_bands & BAND_GN || pmpriv->config_bands & BAND_AN) && wmsdk_is_11N_enabled())
+    {
+        pht_cap = (MrvlIETypes_HTCap_t *)(void *)ptlv_pos;
+        (void)__memset(pmadapter, pht_cap, 0, sizeof(MrvlIETypes_HTCap_t));
+        pht_cap->header.type = wlan_cpu_to_le16(HT_CAPABILITY);
+        pht_cap->header.len  = (t_u16)sizeof(HTCap_t);
+        wlan_fill_ht_cap_tlv(pmpriv, pht_cap, pmpriv->config_bands);
+        HEXDUMP("SCAN: HT_CAPABILITIES IE", (t_u8 *)pht_cap, sizeof(MrvlIETypes_HTCap_t));
+        ptlv_pos += sizeof(MrvlIETypes_HTCap_t);
+        pht_cap->header.len = wlan_cpu_to_le16(pht_cap->header.len);
+    }
+
+#if CONFIG_11AC
+    if (ISSUPP_11ACENABLED(pmpriv->adapter->fw_cap_info) && (pmpriv->config_bands & BAND_AAC))
+    {
+        pvht_cap = (MrvlIETypes_VHTCap_t *)(void *)ptlv_pos;
+        (void)__memset(pmadapter, pvht_cap, 0, sizeof(MrvlIETypes_VHTCap_t));
+        pvht_cap->header.type = wlan_cpu_to_le16(VHT_CAPABILITY);
+        pvht_cap->header.len  = (t_u16)sizeof(VHT_capa_t);
+        wlan_fill_vht_cap_tlv(pmpriv, pvht_cap, pmpriv->config_bands, MFALSE);
+        HEXDUMP("SCAN: VHT_CAPABILITIES IE", (t_u8 *)pvht_cap, sizeof(MrvlIETypes_VHTCap_t));
+        ptlv_pos += sizeof(MrvlIETypes_VHTCap_t);
+        pvht_cap->header.len = wlan_cpu_to_le16(pvht_cap->header.len);
+    }
+#endif
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    /*
+     * Append rssi threshold tlv
+     *
+     * Note: According to the value of rssi_threshold, it is divided into three situations:
+     *     rssi_threshold  |  rssi_threshold_enable  |  Whether to carry TLV
+     *           <0        |          MTRUE          |          Yes
+     *            0        |          MFALSE         |          No
+     *           >0        |          MFALSE         |          Yes
+     */
+    if (rssi_threshold)
+    {
+        prssi_threshold_tlv              = (MrvlIEtypes_RssiThresholdParamSet_t *)ptlv_pos;
+        prssi_threshold_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_RSSI_THRESHOLD);
+        prssi_threshold_tlv->header.len =
+            (t_u16)(sizeof(prssi_threshold_tlv->enable) + sizeof(prssi_threshold_tlv->rssi_threshold) +
+                    sizeof(prssi_threshold_tlv->reserved));
+        prssi_threshold_tlv->enable         = rssi_threshold_enable;
+        prssi_threshold_tlv->rssi_threshold = rssi_threshold;
+
+        ptlv_pos += sizeof(prssi_threshold_tlv->header) + prssi_threshold_tlv->header.len;
+
+        prssi_threshold_tlv->header.len = wlan_cpu_to_le16(prssi_threshold_tlv->header.len);
+
+        pmadapter->rssi_threshold = (rssi_threshold < 0 ? rssi_threshold : 0);
+
+        PRINTM(MINFO, "SCAN_CMD: Rssi threshold = %d\n", rssi_threshold);
+    }
+#endif
+
+    /* fixme: enable this later when req. */
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    wlan_add_wps_probe_request_ie(pmpriv, &ptlv_pos);
+#endif
+    wlan_add_probe_request_ie(pmpriv, &ptlv_pos);
+#endif
+
+#if (CONFIG_DRIVER_MBO) || (CONFIG_WPA_SUPP)
+    wlan_add_ext_capa_info_ie(pmpriv, NULL, &ptlv_pos);
+#endif
+
+    /*
+     * Set the output for the channel TLV to the address in the tlv buffer
+     *   past any TLVs that were added in this function (SSID, num_probes).
+     *   Channel TLVs will be added past this for each scan command, preserving
+     *   the TLVs that were previously added.
+     */
+    *ppchan_list_out = (MrvlIEtypes_ChanListParamSet_t *)(void *)ptlv_pos;
+
+    if ((puser_scan_in != MNULL) && puser_scan_in->chan_list[0].chan_number)
+    {
+        PRINTM(MINFO, "Scan: Using supplied channel list\n");
+
+        for (chan_idx = 0; chan_idx < WLAN_USER_SCAN_CHAN_MAX && puser_scan_in->chan_list[chan_idx].chan_number;
+             chan_idx++)
+        {
+            radio_type = puser_scan_in->chan_list[chan_idx].radio_type;
+            if (!wlan_is_band_compatible(pmpriv->config_bands, radio_type_to_band(radio_type)))
+            {
+                continue;
+            }
+
+            channel                                   = puser_scan_in->chan_list[chan_idx].chan_number;
+            (pscan_chan_list + chan_idx)->chan_number = channel;
+
+            (pscan_chan_list + chan_idx)->radio_type = radio_type;
+
+            scan_type = puser_scan_in->chan_list[chan_idx].scan_type;
+            if (scan_type == MLAN_SCAN_TYPE_UNCHANGED)
+            {
+                scan_type = pmadapter->scan_type;
+            }
+
+            if (radio_type == HostCmd_SCAN_RADIO_TYPE_A)
+            {
+                if ((pmadapter->fw_bands & BAND_A) != 0U)
+                {
+                    PRINTM(MINFO, "UserScan request for A Band channel %d!!\n", channel);
+                }
+                else
+                {
+                    PRINTM(MERROR, "Scan in A band is not allowed!!\n");
+                    ret = MLAN_STATUS_FAILURE;
+                    LEAVE();
+                    return ret;
+                }
+            }
+
+            if (pmadapter->active_scan_triggered == MFALSE)
+            {
+                /* Prevent active scanning on a radar controlled channel */
+#if CONFIG_5GHz_SUPPORT
+                if (radio_type == HostCmd_SCAN_RADIO_TYPE_A)
+                {
+                    if (wlan_11h_radar_detect_required(pmpriv, channel))
+                    {
+                        /* Skip DFS channels if required */
+                        if (pmadapter->skip_dfs)
+                            continue;
+#if defined(RW610) || defined(SD9177)
+                        scan_type = MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE;
+#else
+                        scan_type = MLAN_SCAN_TYPE_PASSIVE;
+#endif
+                    }
+                }
+#endif
+                if (radio_type == HostCmd_SCAN_RADIO_TYPE_BG)
+                {
+                    if (wlan_bg_scan_type_is_passive(pmpriv, channel))
+                    {
+                        scan_type = MLAN_SCAN_TYPE_PASSIVE;
+                    }
+                }
+            }
+#if defined(RW610) || defined(SD9177)
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE || scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE)
+#else
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+#endif
+            {
+                (pscan_chan_list + chan_idx)->chan_scan_mode.passive_scan       = MTRUE;
+                (pscan_chan_list + chan_idx)->chan_scan_mode.hidden_ssid_report = MTRUE;
+            }
+            else
+            {
+                (pscan_chan_list + chan_idx)->chan_scan_mode.passive_scan = MFALSE;
+            }
+
+            if (puser_scan_in->chan_list[chan_idx].scan_time != 0U)
+            {
+                scan_dur = (t_u16)puser_scan_in->chan_list[chan_idx].scan_time;
+            }
+            else
+            {
+#if defined(RW610) || defined(SD9177)
+                if (scan_type == MLAN_SCAN_TYPE_PASSIVE || scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE)
+#else
+                if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+#endif
+                {
+                    scan_dur = pmadapter->passive_scan_time;
+                }
+                else if (*pfiltered_scan == MTRUE)
+                {
+                    scan_dur = pmadapter->specific_scan_time;
+                }
+                else
+                {
+                    scan_dur = pmadapter->active_scan_time;
+                }
+            }
+
+#if defined(RW610) || defined(SD9177)
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE)
+            {
+                (pscan_chan_list + chan_idx)->chan_scan_mode.passive_to_active_scan = MTRUE;
+                scan_dur = MAX(MIN_PASSIVE_TO_ACTIVE_SCAN_TIME, scan_dur);
+            }
+#endif
+            (pscan_chan_list + chan_idx)->min_scan_time = wlan_cpu_to_le16(scan_dur);
+            (pscan_chan_list + chan_idx)->max_scan_time = wlan_cpu_to_le16(scan_dur);
+
+#if defined(RW610) || defined(SD9177)
+            wscan_d("Channel: %d Type: %s ", channel,
+                    scan_type == MLAN_SCAN_TYPE_PASSIVE           ? "Passive" :
+                    scan_type == MLAN_SCAN_TYPE_PASSIVE_TO_ACTIVE ? "PassiveToActive" :
+                                                                    "Active");
+#else
+            wscan_d("Channel: %d Type: %s ", channel, scan_type == MLAN_SCAN_TYPE_PASSIVE ? "Passive" : "Active");
+#endif
+        }
+
+        /* Check if we are only scanning the current channel */
+        if ((chan_idx == 1U) &&
+            (puser_scan_in->chan_list[0].chan_number == pmpriv->curr_bss_params.bss_descriptor.channel))
+        {
+            *pscan_current_only = MTRUE;
+            PRINTM(MINFO, "Scan: Scanning current channel only\n");
+        }
+    }
+    else
+    {
+        PRINTM(MINFO, "Scan: Creating full region channel list\n");
+        wlan_scan_create_channel_list(pmpriv, puser_scan_in, pscan_chan_list, *pfiltered_scan);
+    }
+
+    LEAVE();
+    return ret;
+}
+
+#if (CONFIG_WPS2) || (CONFIG_WPA_SUPP_WPS)
+void check_for_wps_ie(const uint8_t *poui,
+                      t_u8 oui_type,
+                      bool *wps_IE_exist,
+                      t_u16 *wps_session,
+                      void *element_data,
+                      unsigned element_len);
+#endif /* CONFIG_WPA_SUPP_WPS */
+
+/**
+ *  @brief  Check if any hidden SSID found in passive scan channels
+ *          and do specific SSID active scan for those channels
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MTRUE/MFALSE
+ */
+bool wlan_active_scan_req_for_passive_chan(mlan_private *pmpriv, wlan_user_scan_cfg *puser_scan_in)
+{
+    bool ret                = MFALSE;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    bool scan_reqd          = MFALSE;
+    bool chan_listed        = MFALSE;
+    t_u8 id                 = 0;
+    t_u32 bss_idx, i;
+    t_u8 null_ssid[MLAN_MAX_SSID_LENGTH] = {0};
+#if !CONFIG_MEM_POOLS
+    mlan_callbacks *pcb                  = (mlan_callbacks *)&pmpriv->adapter->callbacks;
+#endif
+    wlan_user_scan_cfg *user_scan_cfg    = MNULL;
+    t_u16 band;
+
+    ENTER();
+
+    if (!pmpriv->ssid_filter)
+    {
+        goto done;
+    }
+
+    if (pmadapter->active_scan_triggered)
+    {
+        pmadapter->active_scan_triggered = MFALSE;
+        goto done;
+    }
+#if !CONFIG_MEM_POOLS
+    if ((pcb->moal_malloc(pmadapter->pmoal_handle, sizeof(wlan_user_scan_cfg), MLAN_MEM_DEF, (t_u8 **)&user_scan_cfg) !=
+         MLAN_STATUS_SUCCESS) ||
+        !user_scan_cfg)
+#else
+    user_scan_cfg = OSA_MemoryPoolAllocate(buf_768_MemoryPool);
+    if (user_scan_cfg == NULL)
+#endif
+    {
+        wifi_d("Memory allocation for user_scan_cfg failed\r\n");
+        goto done;
+    }
+
+    memset(user_scan_cfg, 0x00, sizeof(wlan_user_scan_cfg));
+
+    for (bss_idx = 0; bss_idx < pmadapter->num_in_scan_table; bss_idx++)
+    {
+        scan_reqd = MFALSE;
+        if (!memcmp(pmadapter->pscan_table[bss_idx].ssid.ssid, null_ssid,
+                    pmadapter->pscan_table[bss_idx].ssid.ssid_len))
+        {
+            if (puser_scan_in && puser_scan_in->chan_list[0].chan_number)
+            {
+                for (i = 0; i < WLAN_USER_SCAN_CHAN_MAX && puser_scan_in->chan_list[i].chan_number; i++)
+                {
+                    if (puser_scan_in->chan_list[i].chan_number == pmadapter->pscan_table[bss_idx].channel)
+                    {
+                        if (puser_scan_in->chan_list[i].scan_type == MLAN_SCAN_TYPE_PASSIVE)
+                            scan_reqd = MTRUE;
+                        break;
+                    }
+                }
+            }
+            else if (pmadapter->scan_type == MLAN_SCAN_TYPE_PASSIVE)
+            {
+                scan_reqd = MTRUE;
+            }
+            else
+            {
+#if CONFIG_5GHz_SUPPORT
+                if ((pmadapter->pscan_table[bss_idx].bss_band & BAND_A) &&
+                    wlan_11h_radar_detect_required(pmpriv, pmadapter->pscan_table[bss_idx].channel))
+                    scan_reqd = MTRUE;
+#endif
+                if (pmadapter->pscan_table[bss_idx].bss_band & (BAND_B | BAND_G) &&
+                    wlan_bg_scan_type_is_passive(pmpriv, pmadapter->pscan_table[bss_idx].channel))
+                    scan_reqd = MTRUE;
+            }
+
+            if (scan_reqd)
+            {
+                chan_listed = MFALSE;
+                for (i = 0; i < id; i++)
+                {
+                    band = radio_type_to_band(user_scan_cfg->chan_list[i].radio_type);
+
+                    if ((user_scan_cfg->chan_list[i].chan_number == pmadapter->pscan_table[bss_idx].channel) &&
+                        (band & pmadapter->pscan_table[bss_idx].bss_band))
+                    {
+                        chan_listed = MTRUE;
+                        break;
+                    }
+                }
+                if (chan_listed == MTRUE)
+                    continue;
+                user_scan_cfg->chan_list[id].chan_number = pmadapter->pscan_table[bss_idx].channel;
+                if (pmadapter->pscan_table[bss_idx].bss_band & (BAND_B | BAND_G))
+                    user_scan_cfg->chan_list[id].radio_type = BAND_2GHZ;
+#if CONFIG_5GHz_SUPPORT
+                if (pmadapter->pscan_table[bss_idx].bss_band & BAND_A)
+                    user_scan_cfg->chan_list[id].radio_type = BAND_5GHZ;
+#endif
+                user_scan_cfg->chan_list[id].scan_type = MLAN_SCAN_TYPE_ACTIVE;
+
+                user_scan_cfg->chan_list[id].scan_time = MRVDRV_ACTIVE_SCAN_CHAN_TIME;
+
+                id++;
+
+                if (id >= WLAN_USER_SCAN_CHAN_MAX)
+                    break;
+            }
+        }
+    }
+    if (id)
+    {
+        pmadapter->active_scan_triggered = MTRUE;
+        (void)__memcpy(pmadapter, user_scan_cfg->ssid_list, puser_scan_in->ssid_list, sizeof(user_scan_cfg->ssid_list));
+        user_scan_cfg->keep_previous_scan = MTRUE;
+#ifdef EXT_SCAN_ENH
+        if (pmadapter->ext_scan_type == EXT_SCAN_ENHANCE)
+            user_scan_cfg->ext_scan_type = EXT_SCAN_ENHANCE;
+#endif
+        wifi_d("active scan request for passive channel %d\r\n", id);
+        if (MLAN_STATUS_SUCCESS != wlan_scan_networks(pmpriv, NULL, user_scan_cfg))
+        {
+            goto done;
+        }
+        ret = MTRUE;
+    }
+done:
+    split_scan_in_progress = false;
+    if (user_scan_cfg)
+    {
+#if !CONFIG_MEM_POOLS
+        pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)user_scan_cfg);
+#else
+        OSA_MemoryPoolFree(buf_768_MemoryPool, user_scan_cfg);
+#endif
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Interpret a BSS scan response returned from the firmware
+ *
+ *  Parse the various fixed fields and IEs passed back for a BSS probe
+ *   response or beacon from the scan command.  Record information as needed
+ *   in the scan table BSSDescriptor_t for that entry.
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pbss_entry   Output parameter: Pointer to the BSS Entry
+ *  @param pbeacon_info Pointer to the Beacon information
+ *  @param bytes_left   Number of bytes left to parse
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_interpret_bss_desc_with_ie(IN pmlan_adapter pmadapter,
+                                                   OUT BSSDescriptor_t *pbss_entry,
+                                                   IN t_u8 **pbeacon_info,
+                                                   IN t_u32 *bytes_left,
+                                                   IN t_u8 ext_scan)
+{
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+    IEEEtypes_ElementId_e element_id;
+    IEEEtypes_FhParamSet_t *pfh_param_set;
+    IEEEtypes_DsParamSet_t *pds_param_set;
+    IEEEtypes_DtimParamSet_t *pdtim_param_set;
+    IEEEtypes_CfParamSet_t *pcf_param_set;
+    IEEEtypes_IbssParamSet_t *pibss_param_set;
+    IEEEtypes_CapInfo_t *pcap_info;
+    WLAN_802_11_FIXED_IEs fixed_ie;
+    t_u8 *pcurrent_ptr;
+    t_u8 *prate;
+    t_u8 element_len;
+    t_u16 total_ie_len;
+    t_u8 bytes_to_copy;
+    t_u8 rate_size;
+    t_u16 beacon_size;
+    t_u8 found_data_rate_ie;
+    t_u32 bytes_left_for_current_beacon;
+    /* IEEEtypes_ERPInfo_t *perp_info; */
+
+    IEEEtypes_VendorSpecific_t *pvendor_ie;
+    const t_u8 wpa_oui[3]       = {0x00, 0x50, 0xf2};
+    const t_u8 wpa_type[1]      = {0x01};
+    const t_u8 wmm_oui[3]       = {0x00, 0x50, 0xf2};
+    const t_u8 wmm_type[1]      = {0x02};
+    const t_u8 brcm_oui[3]      = {0x00, 0x10, 0x18};
+    const t_u8 brcm_type[1]     = {0x02};
+    const t_u8 epigram_oui[3]   = {0x00, 0x90, 0x4c};
+    const t_u8 epigram_type1[1] = {0x33};
+    const t_u8 epigram_type2[1] = {0x34};
+
+#if CONFIG_DRIVER_OWE
+    const t_u8 owe_oui[3]  = {0x50, 0x6f, 0x9a};
+    const t_u8 owe_type[1] = {0x01c};
+#endif
+#if CONFIG_DRIVER_MBO
+    const t_u8 scan_mbo_oui[3]  = {0x50, 0x6f, 0x9a};
+    const t_u8 scan_mbo_type[1] = {0x016};
+#endif
+
+    IEEEtypes_CountryInfoSet_t *pcountry_info;
+#if CONFIG_11AX
+    IEEEtypes_Extension_t *pext_tlv;
+#endif
+
+    ENTER();
+
+    found_data_rate_ie = MFALSE;
+    rate_size          = 0;
+    beacon_size        = 0;
+
+    if (*bytes_left >= sizeof(beacon_size))
+    {
+        /* Extract & convert beacon size from the command buffer */
+        (void)__memcpy(pmadapter, &beacon_size, *pbeacon_info, sizeof(beacon_size));
+        beacon_size = wlan_le16_to_cpu(beacon_size);
+        *bytes_left -= sizeof(beacon_size);
+        *pbeacon_info += sizeof(beacon_size);
+    }
+
+    if (!beacon_size || beacon_size > *bytes_left)
+    {
+        *pbeacon_info += *bytes_left;
+        *bytes_left = 0;
+
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    /* Initialize the current working beacon pointer for this BSS iteration */
+    pcurrent_ptr = *pbeacon_info;
+
+    /* Advance the return beacon pointer past the current beacon */
+    *pbeacon_info += beacon_size;
+    *bytes_left -= beacon_size;
+
+    bytes_left_for_current_beacon = beacon_size;
+
+    if (bytes_left_for_current_beacon < (MLAN_MAC_ADDR_LENGTH + sizeof(t_u8) + sizeof(WLAN_802_11_FIXED_IEs)))
+    {
+        PRINTM(MERROR, "InterpretIE: Not enough bytes left\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    (void)__memcpy(pmadapter, pbss_entry->mac_address, pcurrent_ptr, MLAN_MAC_ADDR_LENGTH);
+    wifi_d("InterpretIE: AP MAC Addr-%02x:%02x:%02x:%02x:%02x:%02x", pbss_entry->mac_address[0],
+           pbss_entry->mac_address[1], pbss_entry->mac_address[2], pbss_entry->mac_address[3],
+           pbss_entry->mac_address[4], pbss_entry->mac_address[5]);
+
+    pcurrent_ptr += MLAN_MAC_ADDR_LENGTH;
+    bytes_left_for_current_beacon -= MLAN_MAC_ADDR_LENGTH;
+
+    /*
+     * Next 4 fields are RSSI (for legacy scan only), time stamp,
+     *   beacon interval, and capability information
+     */
+#if CONFIG_EXT_SCAN_SUPPORT
+    if (ext_scan == (t_u8)0U)
+    {
+#endif
+        /* RSSI is 1 byte long */
+        pbss_entry->rssi = (t_s32)(*pcurrent_ptr);
+        PRINTM(MINFO, "InterpretIE: RSSI=%02X\n", *pcurrent_ptr);
+        pcurrent_ptr += 1;
+        bytes_left_for_current_beacon -= 1U;
+#if CONFIG_EXT_SCAN_SUPPORT
+    }
+#endif
+
+    /*
+     *  The RSSI is not part of the beacon/probe response.  After we have
+     *    advanced pcurrent_ptr past the RSSI field, save the remaining
+     *    data for use at the application layer
+     */
+    pbss_entry->pbeacon_buf     = pcurrent_ptr;
+    pbss_entry->beacon_buf_size = bytes_left_for_current_beacon;
+
+    (void)__memcpy(pmadapter, pbss_entry->time_stamp, pcurrent_ptr, 8);
+
+    pbss_entry->scan_result_tsf = (OSA_TimeGetMsec() * 1000);
+
+    pcurrent_ptr += 8;
+    bytes_left_for_current_beacon -= 8U;
+
+    /* Beacon interval is 2 bytes long */
+    (void)__memcpy(pmadapter, &fixed_ie.beacon_interval, pcurrent_ptr, 2);
+    pbss_entry->beacon_period = wlan_le16_to_cpu(fixed_ie.beacon_interval);
+    pcurrent_ptr += 2;
+    bytes_left_for_current_beacon -= 2U;
+
+    /* Capability information is 2 bytes long */
+    (void)__memcpy(pmadapter, &fixed_ie.capabilities, pcurrent_ptr, 2);
+    PRINTM(MINFO, "InterpretIE: fixed_ie.capabilities=0x%X\n", fixed_ie.capabilities);
+    fixed_ie.capabilities = wlan_le16_to_cpu(fixed_ie.capabilities);
+    pcap_info             = (IEEEtypes_CapInfo_t *)(void *)&fixed_ie.capabilities;
+    (void)__memcpy(pmadapter, &pbss_entry->cap_info, pcap_info, sizeof(IEEEtypes_CapInfo_t));
+    pcurrent_ptr += 2;
+    bytes_left_for_current_beacon -= 2U;
+
+    /* Rest of the current buffer are IE's */
+    wifi_d("InterpretIE: IELength for this AP = %d", bytes_left_for_current_beacon);
+
+    HEXDUMP("InterpretIE: IE info", (t_u8 *)pcurrent_ptr, bytes_left_for_current_beacon);
+
+#if CONFIG_WPA_SUPP
+    /* Store IE pointer and len for wpa supplicant scan result, no need to process each IE below*/
+    if (pmadapter->wpa_supp_scan_triggered == MTRUE)
+    {
+        wifi_d("Alloc ies for BSS");
+        pbss_entry->ies = (u8 *)OSA_MemoryAllocate(bytes_left_for_current_beacon);
+        if (pbss_entry->ies == MNULL)
+        {
+            wifi_d("Failed to alloc memory for BSS ies");
+            return MLAN_STATUS_FAILURE;
+        }
+        (void)__memcpy(pmadapter, pbss_entry->ies, (t_u8 *)pcurrent_ptr, bytes_left_for_current_beacon);
+        pbss_entry->ies_len = bytes_left_for_current_beacon;
+    }
+#endif
+
+    if (pcap_info->privacy == MTRUE)
+    {
+        PRINTM(MINFO, "InterpretIE: AP WEP enabled\n");
+        pbss_entry->privacy = (t_u32)Wlan802_11PrivFilter8021xWEP;
+    }
+    else
+    {
+        pbss_entry->privacy = (t_u32)Wlan802_11PrivFilterAcceptAll;
+    }
+
+    if (pcap_info->ibss == 1U)
+    {
+        pbss_entry->bss_mode = MLAN_BSS_MODE_IBSS;
+    }
+    else
+    {
+        pbss_entry->bss_mode = MLAN_BSS_MODE_INFRA;
+    }
+
+
+    /* Process variable IE */
+    while (bytes_left_for_current_beacon >= 2U)
+    {
+        element_id   = (IEEEtypes_ElementId_e)(*((t_u8 *)pcurrent_ptr));
+        element_len  = *((t_u8 *)pcurrent_ptr + 1);
+        total_ie_len = (t_u16)(element_len + sizeof(IEEEtypes_Header_t));
+
+        if (bytes_left_for_current_beacon < total_ie_len)
+        {
+            PRINTM(MERROR,
+                   "InterpretIE: Error in processing IE, "
+                   "bytes left < IE length\n");
+            bytes_left_for_current_beacon = 0;
+            continue;
+        }
+
+        switch (element_id)
+        {
+            case SSID:
+                if (element_len > MRVDRV_MAX_SSID_LENGTH)
+                {
+                    bytes_left_for_current_beacon = 0;
+                    continue;
+                }
+                pbss_entry->ssid.ssid_len = element_len;
+                (void)__memcpy(pmadapter, pbss_entry->ssid.ssid, (pcurrent_ptr + 2), element_len);
+                wscan_d("AP: %s", pbss_entry->ssid.ssid);
+                PRINTM(MINFO, "InterpretIE: ssid: %-32s\n", pbss_entry->ssid.ssid);
+                break;
+
+            case SUPPORTED_RATES:
+                if (element_len > WLAN_SUPPORTED_RATES)
+                {
+                    bytes_left_for_current_beacon = 0;
+                    continue;
+                }
+                (void)__memcpy(pmadapter, pbss_entry->data_rates, pcurrent_ptr + 2, element_len);
+                (void)__memcpy(pmadapter, pbss_entry->supported_rates, pcurrent_ptr + 2, element_len);
+                HEXDUMP("InterpretIE: SupportedRates:", pbss_entry->supported_rates, element_len);
+                rate_size          = element_len;
+                found_data_rate_ie = MTRUE;
+                break;
+
+            case FH_PARAM_SET:
+                pfh_param_set                = (IEEEtypes_FhParamSet_t *)(void *)pcurrent_ptr;
+                pbss_entry->network_type_use = Wlan802_11FH;
+                (void)__memcpy(pmadapter, &pbss_entry->phy_param_set.fh_param_set, pfh_param_set,
+                               MIN(total_ie_len, sizeof(IEEEtypes_FhParamSet_t)));
+                pbss_entry->phy_param_set.fh_param_set.len =
+                    MIN(element_len, (sizeof(IEEEtypes_FhParamSet_t) - sizeof(IEEEtypes_Header_t)));
+                pbss_entry->phy_param_set.fh_param_set.dwell_time =
+                    wlan_le16_to_cpu(pbss_entry->phy_param_set.fh_param_set.dwell_time);
+                break;
+
+            case DS_PARAM_SET:
+                pds_param_set = (IEEEtypes_DsParamSet_t *)(void *)pcurrent_ptr;
+
+                pbss_entry->network_type_use = Wlan802_11DS;
+                pbss_entry->channel          = pds_param_set->current_chan;
+
+                (void)__memcpy(pmadapter, &pbss_entry->phy_param_set.ds_param_set, pds_param_set,
+                               MIN(total_ie_len, sizeof(IEEEtypes_DsParamSet_t)));
+                pbss_entry->phy_param_set.ds_param_set.len =
+                    MIN(element_len, (sizeof(IEEEtypes_DsParamSet_t) - sizeof(IEEEtypes_Header_t)));
+                break;
+
+            case CF_PARAM_SET:
+                pcf_param_set = (IEEEtypes_CfParamSet_t *)(void *)pcurrent_ptr;
+                (void)__memcpy(pmadapter, &pbss_entry->ss_param_set.cf_param_set, pcf_param_set,
+                               MIN(total_ie_len, sizeof(IEEEtypes_CfParamSet_t)));
+                pbss_entry->ss_param_set.cf_param_set.len =
+                    MIN(element_len, (sizeof(IEEEtypes_CfParamSet_t) - sizeof(IEEEtypes_Header_t)));
+                break;
+
+            case DTIM_PARAM_SET:
+                pdtim_param_set = (IEEEtypes_DtimParamSet_t *)(void *)pcurrent_ptr;
+
+                pbss_entry->dtim_period = pdtim_param_set->dtim_period;
+                break;
+
+            case IBSS_PARAM_SET:
+                pibss_param_set         = (IEEEtypes_IbssParamSet_t *)(void *)pcurrent_ptr;
+                pbss_entry->atim_window = wlan_le16_to_cpu(pibss_param_set->atim_window);
+                (void)__memcpy(pmadapter, &pbss_entry->ss_param_set.ibss_param_set, pibss_param_set,
+                               MIN(total_ie_len, sizeof(IEEEtypes_IbssParamSet_t)));
+                pbss_entry->ss_param_set.ibss_param_set.len =
+                    MIN(element_len, (sizeof(IEEEtypes_IbssParamSet_t) - sizeof(IEEEtypes_Header_t)));
+                break;
+
+                /* Handle Country Info IE */
+            case COUNTRY_INFO:
+                /* Disabling this because IEEEtypes_CountryInfoSet_t size
+                   is 254 bytes. Check later if can be optimized */
+                pcountry_info = (IEEEtypes_CountryInfoSet_t *)(void *)pcurrent_ptr;
+
+                if (pcountry_info->len < sizeof(pcountry_info->country_code) ||
+                    (unsigned)(pcountry_info->len + 2) > sizeof(IEEEtypes_CountryInfoFullSet_t))
+                {
+                    PRINTM(MERROR,
+                           "InterpretIE: 11D- Err "
+                           "country_info len =%d min=%d max=%d\n",
+                           pcountry_info->len, sizeof(pcountry_info->country_code),
+                           sizeof(IEEEtypes_CountryInfoFullSet_t));
+                    LEAVE();
+                    return MLAN_STATUS_FAILURE;
+                }
+
+                (void)__memcpy(pmadapter, &pbss_entry->country_info, pcountry_info, pcountry_info->len + 2);
+                HEXDUMP("InterpretIE: 11D- country_info:", (t_u8 *)pcountry_info, (t_u32)(pcountry_info->len + 2));
+                break;
+            case POWER_CONSTRAINT:
+            case POWER_CAPABILITY:
+            case TPC_REPORT:
+            case CHANNEL_SWITCH_ANN:
+            case QUIET:
+            case IBSS_DFS:
+            case SUPPORTED_CHANNELS:
+            case TPC_REQUEST:
+                /* fixme: Not enabled yet */
+                /* wlan_11h_process_bss_elem(pmadapter, &pbss_entry->wlan_11h_bss_info, */
+                /*                       pcurrent_ptr); */
+                break;
+            case EXTENDED_SUPPORTED_RATES:
+                /*
+                 * Only process extended supported rate
+                 * if data rate is already found.
+                 * Data rate IE should come before
+                 * extended supported rate IE
+                 */
+                if (found_data_rate_ie == MTRUE)
+                {
+                    if ((element_len + rate_size) > WLAN_SUPPORTED_RATES)
+                    {
+                        bytes_to_copy = (WLAN_SUPPORTED_RATES - rate_size);
+                    }
+                    else
+                    {
+                        bytes_to_copy = element_len;
+                    }
+
+                    prate = (t_u8 *)pbss_entry->data_rates;
+                    prate += rate_size;
+                    (void)__memcpy(pmadapter, prate, pcurrent_ptr + 2, bytes_to_copy);
+
+                    prate = (t_u8 *)pbss_entry->supported_rates;
+                    prate += rate_size;
+                    (void)__memcpy(pmadapter, prate, pcurrent_ptr + 2, bytes_to_copy);
+                }
+                HEXDUMP("InterpretIE: ExtSupportedRates:", pbss_entry->supported_rates, element_len + rate_size);
+                break;
+
+            case VENDOR_SPECIFIC_221:
+                pvendor_ie = (IEEEtypes_VendorSpecific_t *)(void *)pcurrent_ptr;
+
+                if ((__memcmp(pmadapter, pvendor_ie->vend_hdr.oui, wpa_oui, sizeof(wpa_oui))) == 0 &&
+                    (pvendor_ie->vend_hdr.oui_type == wpa_type[0]))
+                {
+                    /* Save it here since we do not have beacon buffer */
+                    /* fixme : Verify if this is the right approach. This had to be
+                       done because IEEEtypes_Rsn_t was not the correct data
+                       structure to map here  */
+                    if (element_len <= (sizeof(pbss_entry->wpa_ie_buff) - sizeof(IEEEtypes_Header_t)))
+                    {
+                        (void)__memcpy(NULL, pbss_entry->wpa_ie_buff, pcurrent_ptr,
+                                       element_len + sizeof(IEEEtypes_Header_t));
+                        pbss_entry->pwpa_ie         = (IEEEtypes_VendorSpecific_t *)(void *)pbss_entry->wpa_ie_buff;
+                        pbss_entry->wpa_ie_buff_len = element_len + sizeof(IEEEtypes_Header_t);
+
+                        if (wifi_check_bss_entry_wpa2_entp_only(pbss_entry, VENDOR_SPECIFIC_221) != MLAN_STATUS_SUCCESS)
+                        {
+                            return MLAN_STATUS_RESOURCE;
+                        }
+                    }
+                    else
+                    {
+                        wifi_e("Insufficient space to save WPA_IE size: %d", element_len);
+                    }
+
+                    /* pbss_entry->pwpa_ie = */
+                    /*     (IEEEtypes_VendorSpecific_t *) pcurrent_ptr; */
+                    /* pbss_entry->wpa_offset = */
+                    /*     (t_u16) (pcurrent_ptr - pbss_entry->pbeacon_buf); */
+                    HEXDUMP("InterpretIE: Resp WPA_IE", (t_u8 *)pbss_entry->pwpa_ie,
+                            ((*(pbss_entry->pwpa_ie)).vend_hdr.len + sizeof(IEEEtypes_Header_t)));
+                }
+                else if ((__memcmp(pmadapter, pvendor_ie->vend_hdr.oui, wmm_oui, sizeof(wmm_oui))) == 0 &&
+                         (pvendor_ie->vend_hdr.oui_type == wmm_type[0]))
+                {
+                    if (total_ie_len == sizeof(IEEEtypes_WmmParameter_t) || total_ie_len == sizeof(IEEEtypes_WmmInfo_t))
+                    {
+                        /*
+                         * Only accept and copy the WMM IE if it matches
+                         * the size expected for the WMM Info IE or the
+                         * WMM Parameter IE.
+                         */
+                        (void)__memcpy(pmadapter, (t_u8 *)&pbss_entry->wmm_ie, pcurrent_ptr, total_ie_len);
+                        HEXDUMP("InterpretIE: Resp WMM_IE", (t_u8 *)&pbss_entry->wmm_ie, total_ie_len);
+                    }
+                }
+                else if ((__memcmp(pmadapter, pvendor_ie->vend_hdr.oui, brcm_oui, sizeof(brcm_oui))) == 0 &&
+                         (pvendor_ie->vend_hdr.oui_type == brcm_type[0]))
+                {
+                    pbss_entry->brcm_ie_exist = 1;
+                }
+                else if ((__memcmp(pmadapter, pvendor_ie->vend_hdr.oui, epigram_oui, sizeof(epigram_oui))) == 0 &&
+                         (pvendor_ie->vend_hdr.oui_type == epigram_type1[0] ||
+                          pvendor_ie->vend_hdr.oui_type == epigram_type2[0]))
+                {
+                    pbss_entry->epigram_ie_exist = 1;
+                }
+#if CONFIG_DRIVER_OWE
+                else if (IS_FW_SUPPORT_EMBEDDED_OWE(pmadapter) &&
+                         (!__memcmp(pmadapter, pvendor_ie->vend_hdr.oui, owe_oui, sizeof(owe_oui)) &&
+                          (pvendor_ie->vend_hdr.oui_type == owe_type[0])))
+                {
+                    /* Current Format of OWE IE is element_id:element_len:oui:MAC Address:SSID length:SSID */
+                    t_u8 trans_ssid_len =
+                        *(pcurrent_ptr + sizeof(IEEEtypes_Header_t) + sizeof(owe_oui) + MLAN_MAC_ADDR_LENGTH);
+
+                    if (!trans_ssid_len || trans_ssid_len > MRVDRV_MAX_SSID_LENGTH)
+                    {
+                        bytes_left_for_current_beacon = 0;
+                        continue;
+                    }
+                    if (!pcap_info->privacy)
+                    {
+                        pbss_entry->owe_transition_mode = OWE_TRANS_MODE_OPEN;
+                    }
+                    else
+                    {
+                        pbss_entry->owe_transition_mode = OWE_TRANS_MODE_OWE;
+                    }
+
+                    (void)__memcpy(pmadapter, pbss_entry->trans_mac_address,
+                                   (pcurrent_ptr + sizeof(IEEEtypes_Header_t) + sizeof(owe_oui)), MLAN_MAC_ADDR_LENGTH);
+                    pbss_entry->trans_ssid.ssid_len = trans_ssid_len;
+                    (void)__memcpy(pmadapter, pbss_entry->trans_ssid.ssid,
+                                   (pcurrent_ptr + sizeof(IEEEtypes_Header_t) + sizeof(owe_oui) + MLAN_MAC_ADDR_LENGTH +
+                                    sizeof(t_u8)),
+                                   trans_ssid_len);
+
+                    PRINTM(MCMND, "InterpretIE: OWE Transition AP privacy=%d MAC Addr-" MACSTR " ssid %s\n",
+                           pbss_entry->owe_transition_mode, MAC2STR(pbss_entry->trans_mac_address),
+                           pbss_entry->trans_ssid.ssid);
+                }
+#endif
+#if CONFIG_DRIVER_MBO
+                else if (__memcmp(pmadapter, pvendor_ie->vend_hdr.oui, scan_mbo_oui, sizeof(scan_mbo_oui)) == 0 &&
+                         (pvendor_ie->vend_hdr.oui_type == scan_mbo_type[0]))
+                {
+                    t_u8 *pcurrent_attr = pcurrent_ptr + MBO_IE_HEADER_LEN;
+                    t_u8 mbo_attr_id;
+                    t_u8 mbo_attr_len = 0;
+                    t_u8 mbo_cur_len  = MBO_IE_HEADER_LEN - sizeof(IEEEtypes_Header_t);
+
+                    pbss_entry->mbo_assoc_disallowed = false;
+
+                    while (mbo_cur_len < element_len)
+                    {
+                        mbo_attr_id  = *((t_u8 *)pcurrent_attr);
+                        mbo_attr_len = *((t_u8 *)pcurrent_attr + 1);
+
+                        if (mbo_attr_id == 0x4U)
+                        {
+                            pbss_entry->mbo_assoc_disallowed = true;
+                        }
+
+                        mbo_cur_len += (t_u8)MBO_ATTR_HEADER_LEN + mbo_attr_len;
+                        pcurrent_attr = pcurrent_attr + MBO_ATTR_HEADER_LEN + mbo_attr_len;
+                    }
+                }
+#endif
+#if CONFIG_11K
+                /* Voice Enterprise Test Plan V1.2, test case 5.4, store other vendor specific ie */
+                else
+                {
+                    if (pbss_entry->vendor_ie_len + element_len + (t_u8)sizeof(IEEEtypes_Header_t) <
+                        (t_u8)sizeof(pbss_entry->vendor_ie_buff))
+                    {
+                        (void)__memcpy(pmadapter, pbss_entry->vendor_ie_buff + pbss_entry->vendor_ie_len, pcurrent_ptr,
+                                       element_len + sizeof(IEEEtypes_Header_t));
+                        pbss_entry->vendor_ie_len += element_len + (t_u8)sizeof(IEEEtypes_Header_t);
+                    }
+                }
+#else
+                else
+                {
+                    /* Do Nothing */
+                }
+#endif
+
+#if (CONFIG_WPS2) || (CONFIG_WPA_SUPP_WPS)
+                /* fixme: Added for WMSDK. Check if can be merged properly with
+                   mlan. There should be a better way */
+                check_for_wps_ie(pvendor_ie->vend_hdr.oui, pvendor_ie->vend_hdr.oui_type, &pbss_entry->wps_IE_exist,
+                                 &pbss_entry->wps_session, pcurrent_ptr + 2, element_len);
+#endif /* CONFIG_WPA_SUPP_WPS */
+                break;
+            case RSN_IE:
+                /* Save it here since we do not have beacon buffer */
+                /* fixme : Verify if this is the right approach. This had to be
+                   done because IEEEtypes_Rsn_t was not the correct data
+                   structure to map here  */
+                if (element_len <= (sizeof(pbss_entry->rsn_ie_buff) - sizeof(IEEEtypes_Header_t)))
+                {
+                    (void)__memcpy(NULL, pbss_entry->rsn_ie_buff, pcurrent_ptr,
+                                   element_len + sizeof(IEEEtypes_Header_t));
+                    pbss_entry->rsn_ie_buff_len = element_len + sizeof(IEEEtypes_Header_t);
+                    pbss_entry->prsn_ie         = (IEEEtypes_Generic_t *)(void *)pbss_entry->rsn_ie_buff;
+
+                    if (wifi_check_bss_entry_wpa2_entp_only(pbss_entry, RSN_IE) != MLAN_STATUS_SUCCESS)
+                    {
+                        return MLAN_STATUS_RESOURCE;
+                    }
+                }
+                else
+                {
+                    wifi_e("Insufficient space to save RSN_IE size: %d", element_len);
+                }
+
+                /* pbss_entry->prsn_ie = (IEEEtypes_Generic_t *) pcurrent_ptr; */
+                /* pbss_entry->rsn_offset = */
+                /*     (t_u16) (pcurrent_ptr - pbss_entry->pbeacon_buf); */
+                HEXDUMP("InterpretIE: Resp RSN_IE", (t_u8 *)pbss_entry->prsn_ie,
+                        (*(pbss_entry->prsn_ie)).ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                break;
+#if (CONFIG_11R) || (CONFIG_11K)
+            case MOBILITY_DOMAIN:
+                if (element_len <= (sizeof(pbss_entry->md_ie_buff) - sizeof(IEEEtypes_Header_t)))
+                {
+                    (void)__memcpy(NULL, pbss_entry->md_ie_buff, pcurrent_ptr,
+                                   element_len + sizeof(IEEEtypes_Header_t));
+                    pbss_entry->md_ie_buff_len   = element_len + sizeof(IEEEtypes_Header_t);
+                    pbss_entry->pmd_ie           = (IEEEtypes_MobilityDomain_t *)(void *)pbss_entry->md_ie_buff;
+                    pbss_entry->mob_domain_exist = 1;
+                    /* dump_hex(pbss_entry->pmd_ie, pbss_entry->md_ie_buff_len); */
+                }
+                else
+                {
+                    wifi_e("Insufficient space to save MD_IE size: %d", element_len);
+                }
+                break;
+#endif
+#if CONFIG_11K
+            case RRM_ENABLED_CAP:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->rm_cap_saved, pcurrent_ptr, sizeof(IEEEtypes_RrmElement_t));
+                pbss_entry->rm_cap_exist = 1;
+                break;
+#endif
+            case WAPI_IE:
+                break;
+            case MULTI_BSSID:
+                if (IS_FW_SUPPORT_MULTIBSSID(pmadapter))
+                {
+                    pbss_entry->multi_bssid_ap = MULTI_BSSID_AP;
+                    HEXDUMP("InterpretIE: Multi BSSID IE", (t_u8 *)pcurrent_ptr, total_ie_len);
+                }
+                break;
+            case HT_CAPABILITY:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->ht_cap_saved, pcurrent_ptr, sizeof(IEEEtypes_HTCap_t));
+                pbss_entry->pht_cap = &pbss_entry->ht_cap_saved;
+                /* pbss_entry->pht_cap = (IEEEtypes_HTCap_t *) pcurrent_ptr; */
+                /* pbss_entry->ht_cap_offset = */
+                /*     (t_u16) (pcurrent_ptr - pbss_entry->pbeacon_buf); */
+                HEXDUMP("InterpretIE: Resp HTCAP_IE", (t_u8 *)pbss_entry->pht_cap,
+                        (*(pbss_entry->pht_cap)).ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                break;
+            case HT_OPERATION:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->ht_info_saved, pcurrent_ptr, sizeof(IEEEtypes_HTInfo_t));
+                pbss_entry->pht_info = &pbss_entry->ht_info_saved;
+                /* pbss_entry->pht_info = (IEEEtypes_HTInfo_t *) pcurrent_ptr; */
+                /* pbss_entry->ht_info_offset = */
+                /*     (t_u16) (pcurrent_ptr - pbss_entry->pbeacon_buf); */
+                HEXDUMP("InterpretIE: Resp HTINFO_IE", (t_u8 *)pbss_entry->pht_info,
+                        (*(pbss_entry->pht_info)).ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                break;
+            case BSSCO_2040:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->bss_co_2040_saved, pcurrent_ptr, sizeof(IEEEtypes_2040BSSCo_t));
+                pbss_entry->pbss_co_2040 = &pbss_entry->bss_co_2040_saved;
+                /* pbss_entry->pbss_co_2040 = (IEEEtypes_2040BSSCo_t *) pcurrent_ptr; */
+                /* pbss_entry->bss_co_2040_offset = */
+                /*     (t_u16) (pcurrent_ptr - pbss_entry->pbeacon_buf); */
+                HEXDUMP("InterpretIE: Resp 2040BSSCOEXISTANCE_IE", (t_u8 *)pbss_entry->pbss_co_2040,
+                        (*(pbss_entry->pbss_co_2040)).ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                break;
+#if CONFIG_11AC
+            case VHT_CAPABILITY:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->vht_cap_saved, pcurrent_ptr, sizeof(IEEEtypes_VHTCap_t));
+                pbss_entry->pvht_cap = &pbss_entry->vht_cap_saved;
+                break;
+            case VHT_OPERATION:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->vht_oprat_saved, pcurrent_ptr, sizeof(IEEEtypes_VHTOprat_t));
+                pbss_entry->pvht_oprat = &pbss_entry->vht_oprat_saved;
+                break;
+            case VHT_TX_POWER_ENV:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->vht_txpower_saved, pcurrent_ptr, sizeof(IEEEtypes_VHTtxpower_t));
+                pbss_entry->pvht_txpower = &pbss_entry->vht_txpower_saved;
+                break;
+            case OPER_MODE_NTF:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->poper_mode_saved, pcurrent_ptr, sizeof(IEEEtypes_OperModeNtf_t));
+                pbss_entry->ppoper_mode = &pbss_entry->poper_mode_saved;
+                break;
+#endif
+            case EXT_CAPABILITY:
+                /* Save it here since we do not have beacon buffer */
+                (void)__memcpy(NULL, &pbss_entry->ext_cap_saved, pcurrent_ptr, sizeof(IEEEtypes_ExtCap_t));
+                pbss_entry->pext_cap = &pbss_entry->ext_cap_saved;
+                break;
+#if CONFIG_11AX
+            case EXTENSION:
+                pext_tlv = (IEEEtypes_Extension_t *)pcurrent_ptr;
+                switch (pext_tlv->ext_id)
+                {
+                    case HE_CAPABILITY:
+                        /* Save it here since we do not have beacon buffer */
+                        (void)__memcpy(NULL, &pbss_entry->he_cap_saved, pcurrent_ptr, sizeof(IEEEtypes_HECap_t));
+                        pbss_entry->phe_cap = &pbss_entry->he_cap_saved;
+                        break;
+                    case HE_OPERATION:
+                        /* Save it here since we do not have beacon buffer */
+                        (void)__memcpy(NULL, &pbss_entry->he_oprat_saved, pcurrent_ptr, MIN(total_ie_len, sizeof(IEEEtypes_HeOp_t)));
+                        pbss_entry->phe_oprat = &pbss_entry->he_oprat_saved;
+                        break;
+                    default:
+                        PRINTM(MINFO, "Unexpected extension id\n");
+                        break;
+                }
+                break;
+#endif
+            case RSNX_IE:
+                (void)__memcpy(NULL, &pbss_entry->rsnx_ie_saved, pcurrent_ptr, sizeof(pbss_entry->rsnx_ie_saved));
+                pbss_entry->prsnx_ie = &pbss_entry->rsnx_ie_saved;
+                wscan_d("RSNX_IE: tag len %d data 0x%02x", pbss_entry->prsnx_ie->ieee_hdr.len,
+                        pbss_entry->prsnx_ie->data[0]);
+                break;
+
+            default:
+                PRINTM(MINFO, "Unexpected IE \n");
+                break;
+        }
+
+        pcurrent_ptr += element_len + 2U;
+
+        /* Need to account for IE ID and IE Len */
+        bytes_left_for_current_beacon -= (element_len + 2U);
+
+    } /* while (bytes_left_for_current_beacon > 2) */
+
+    if (wifi_check_bss_entry_wpa2_entp_only(pbss_entry, SSID) != MLAN_STATUS_SUCCESS)
+    {
+        return MLAN_STATUS_RESOURCE;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+
+#if CONFIG_SCAN_CHANNEL_GAP
+/**
+ *  @brief get the chan load from chan stats.
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param channel      channel  *
+ *
+ *  @return             channel load
+ */
+static t_u16 wlan_get_chan_load(mlan_adapter *pmadapter, t_u8 channel)
+{
+    t_u16 chan_load = 0;
+    int i;
+    for (i = 0; i < (int)pmadapter->num_in_chan_stats; i++)
+    {
+        if ((pmadapter->pchan_stats[i].chan_num == channel) && pmadapter->pchan_stats[i].cca_scan_duration)
+        {
+            chan_load =
+                (pmadapter->pchan_stats[i].cca_busy_duration * 100) / pmadapter->pchan_stats[i].cca_scan_duration;
+            break;
+        }
+    }
+    return chan_load;
+}
+
+static t_u16 wlan_get_chan_noise(mlan_adapter *pmadapter, t_u8 channel)
+{
+    t_u16 chan_noise = 0;
+    int i;
+    for (i = 0; i < (int)pmadapter->num_in_chan_stats; i++)
+    {
+        if ((pmadapter->pchan_stats[i].chan_num == channel) && pmadapter->pchan_stats[i].noise)
+        {
+            chan_noise = pmadapter->pchan_stats[i].noise;
+            break;
+        }
+    }
+    return chan_noise;
+}
+
+/**
+ *  @brief get the chan min/max rssi
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param channel      channel  *
+ *  @param min_flag     flag to get min rssi
+ *  @return             rssi
+ */
+static t_u8 wlan_get_chan_rssi(mlan_adapter *pmadapter, t_u8 channel, t_u8 min_flag)
+{
+    t_u8 rssi = 0;
+    int i;
+    for (i = 0; i < (int)pmadapter->num_in_scan_table; i++)
+    {
+        if (pmadapter->pscan_table[i].channel == channel)
+        {
+            if (rssi == 0)
+                rssi = (t_s32)pmadapter->pscan_table[i].rssi;
+            else
+            {
+                if (min_flag)
+                    rssi = MIN(rssi, pmadapter->pscan_table[i].rssi);
+                else
+                    rssi = MAX(rssi, pmadapter->pscan_table[i].rssi);
+            }
+        }
+    }
+    return rssi;
+}
+
+/**
+ *  @brief update the min/max rssi for channel statistics.
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *	@return             N/A
+ */
+static t_void wlan_update_chan_rssi(mlan_adapter *pmadapter)
+{
+    int i;
+    t_s8 min_rssi = 0;
+    t_s8 max_rssi = 0;
+    t_s8 rss      = 0;
+    for (i = 0; i < (int)pmadapter->num_in_chan_stats; i++)
+    {
+        if (pmadapter->pchan_stats[i].chan_num && pmadapter->pchan_stats[i].cca_scan_duration)
+        {
+            min_rssi = -wlan_get_chan_rssi(pmadapter, pmadapter->pchan_stats[i].chan_num, MFALSE);
+            max_rssi = -wlan_get_chan_rssi(pmadapter, pmadapter->pchan_stats[i].chan_num, MTRUE);
+            rss      = min_rssi - pmadapter->pchan_stats[i].noise;
+            // rss should always > 0, FW need fix the wrong
+            // rssi/noise in scantable
+            if (rss > 0)
+                pmadapter->pchan_stats[i].min_rss = rss;
+            else
+                pmadapter->pchan_stats[i].min_rss = 0;
+
+            rss = max_rssi - pmadapter->pchan_stats[i].noise;
+            if (rss > 0)
+                pmadapter->pchan_stats[i].max_rss = rss;
+            else
+                pmadapter->pchan_stats[i].max_rss = 0;
+            PRINTM(MCMND, "chan=%d, min_rssi=%d, max_rssi=%d noise=%d min_rss=%d, max_rss=%d\n",
+                   pmadapter->pchan_stats[i].chan_num, min_rssi, max_rssi, pmadapter->pchan_stats[i].noise,
+                   pmadapter->pchan_stats[i].min_rss, pmadapter->pchan_stats[i].max_rss);
+        }
+    }
+    return;
+}
+#endif
+
+/**
+ *  @brief Post process the scan table after a new scan command has completed
+ *
+ *  Inspect each entry of the scan table and try to find an entry that
+ *    matches our current associated/joined network from the scan.  If
+ *    one is found, update the stored copy of the BSSDescriptor for our
+ *    current network.
+ *
+ *  Debug dump the current scan table contents if compiled accordingly.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *
+ *  @return             N/A
+ */
+/* static */ void wlan_scan_process_results(IN mlan_private *pmpriv)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u32 i;
+
+
+    for (i = 0; i < pmadapter->num_in_scan_table; i++)
+    {
+        PRINTM(MINFO,
+               "Scan:(%02d) %02x:%02x:%02x:%02x:%02x:%02x, "
+               "RSSI[%03d], SSID[%s]\n",
+               i, pmadapter->pscan_table[i].mac_address[0], pmadapter->pscan_table[i].mac_address[1],
+               pmadapter->pscan_table[i].mac_address[2], pmadapter->pscan_table[i].mac_address[3],
+               pmadapter->pscan_table[i].mac_address[4], pmadapter->pscan_table[i].mac_address[5],
+               (t_s32)pmadapter->pscan_table[i].rssi, pmadapter->pscan_table[i].ssid.ssid);
+#if CONFIG_SCAN_CHANNEL_GAP
+        pmadapter->pscan_table[i].chan_load  = wlan_get_chan_load(pmadapter, pmadapter->pscan_table[i].channel);
+        pmadapter->pscan_table[i].chan_noise = wlan_get_chan_noise(pmadapter, pmadapter->pscan_table[i].channel);
+#endif
+    }
+#if CONFIG_SCAN_CHANNEL_GAP
+    wlan_update_chan_rssi(pmadapter);
+#endif
+    /*
+     * Prepares domain info from scan table and downloads the
+     *   domain info command to the FW.
+     */
+    if (wlan_11d_support_is_enabled(pmpriv))
+    {
+        if (pmpriv->support_11d != NULL)
+        {
+            (void)pmpriv->support_11d->wlan_11d_prepare_dnld_domain_info_cmd_p(pmpriv);
+        }
+    }
+
+    LEAVE();
+}
+
+/********************************************************
+                Global Functions
+********************************************************/
+
+/**
+ *  @brief Check if a scanned network compatible with the driver settings
+ *
+ *   WEP     WPA     WPA2    ad-hoc  encrypt                      Network
+ * enabled enabled  enabled   AES     mode   Privacy  WPA  WPA2  Compatible
+ *    0       0        0       0      NONE      0      0    0   yes No security
+ *    0       1        0       0       x        1x     1    x   yes WPA (disable HT if no AES)
+ *    0       0        1       0       x        1x     x    1   yes WPA2 (disable HT if no AES)
+ *    0       0        0       1      NONE      1      0    0   yes Ad-hoc AES
+ *    1       0        0       0      NONE      1      0    0   yes Static WEP (disable HT)
+ *    0       0        0       0     !=NONE     1      0    0   yes Dynamic WEP
+ *
+ *  @param pmpriv  A pointer to mlan_private
+ *  @param index   Index in scan table to check against current driver settings
+ *  @param mode    Network mode: Infrastructure or IBSS
+ *
+ *  @return        Index in ScanTable, or negative value if error
+ */
+t_s32 wlan_is_network_compatible(IN mlan_private *pmpriv, IN t_u32 index, IN mlan_bss_mode mode)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    BSSDescriptor_t *pbss_desc;
+
+    ENTER();
+
+    pbss_desc              = &pmadapter->pscan_table[index];
+    pbss_desc->disable_11n = MFALSE;
+
+    /* Don't check for compatibility if roaming */
+    if ((pmpriv->media_connected == MTRUE) && (pmpriv->bss_mode == MLAN_BSS_MODE_INFRA) &&
+        (pbss_desc->bss_mode == MLAN_BSS_MODE_INFRA))
+    {
+        LEAVE();
+        return (t_s32)index;
+    }
+
+#if CONFIG_11AC
+    /* if the VHT CAP IE exists, the HT CAP IE should exist too */
+    if ((pbss_desc->pvht_cap != MNULL) && (pbss_desc->pht_cap == MNULL))
+    {
+        PRINTM(MINFO, "Disable 11n if HT CAP IE is not found from the 11AC AP\n");
+        pbss_desc->disable_11n = MTRUE;
+    }
+#endif
+#if CONFIG_11AX
+    /* if the HE CAP IE exists, HT CAP IE should exist too */
+    /* 2.4G AX AP, don't have VHT CAP */
+    if (pbss_desc->phe_cap && !pbss_desc->pht_cap)
+    {
+        PRINTM(MINFO, "Disable 11n if VHT CAP/HT CAP IE is not found from the 11AX AP\n");
+        pbss_desc->disable_11n = MTRUE;
+    }
+#endif
+
+
+#if (CONFIG_WPS2) || (CONFIG_WPA_SUPP_WPS)
+    if (pmpriv->wps.session_enable == MTRUE)
+    {
+        PRINTM(MINFO, "Return success directly in WPS period\n");
+        LEAVE();
+        return index;
+    }
+#endif /* CONFIG_WPS2 */
+#if CONFIG_DRIVER_OWE
+    if ((pbss_desc->owe_transition_mode == OWE_TRANS_MODE_OPEN) &&
+        (pmpriv->sec_info.authentication_mode != MLAN_AUTH_MODE_OWE))
+    {
+        PRINTM(MINFO, "Return success directly in OWE Transition mode\n");
+        LEAVE();
+        return index;
+    }
+#endif
+    if ((pbss_desc->bss_mode == mode) && (pmpriv->sec_info.ewpa_enabled == MTRUE))
+    {
+        if (((pbss_desc->pwpa_ie != MNULL) && ((*(pbss_desc->pwpa_ie)).vend_hdr.element_id == WPA_IE)) ||
+            ((pbss_desc->prsn_ie != MNULL) && ((*(pbss_desc->prsn_ie)).ieee_hdr.element_id == RSN_IE)))
+        {
+            if (((pmpriv->adapter->config_bands & BAND_GN || pmpriv->adapter->config_bands & BAND_AN) &&
+                 (pbss_desc->pht_cap != MNULL)) &&
+                (pmpriv->bss_mode == MLAN_BSS_MODE_INFRA) &&
+                !is_wpa_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_CCMP) &&
+                !is_rsn_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_CCMP))
+            {
+                if (is_wpa_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_TKIP) ||
+                    is_rsn_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_TKIP))
+                {
+                    PRINTM(MINFO, "Disable 11n if AES is not supported by AP\n");
+                    pbss_desc->disable_11n = MTRUE;
+                }
+                else
+                {
+                    LEAVE();
+                    return -1;
+                }
+            }
+            LEAVE();
+            return (t_s32)index;
+        }
+        else
+        {
+            PRINTM(MINFO, "ewpa_enabled: Ignore none WPA/WPA2 AP\n");
+            LEAVE();
+            return -1;
+        }
+    }
+
+    if (pmpriv->sec_info.wapi_enabled &&
+        ((pbss_desc->pwapi_ie != MNULL) && ((*(pbss_desc->pwapi_ie)).ieee_hdr.element_id == WAPI_IE)))
+    {
+        PRINTM(MINFO, "Return success for WAPI AP\n");
+        LEAVE();
+        return (t_s32)index;
+    }
+
+    if (pbss_desc->bss_mode == mode)
+    {
+        if (pmpriv->sec_info.wep_status == Wlan802_11WEPDisabled && !pmpriv->sec_info.wpa_enabled &&
+            !pmpriv->sec_info.wpa2_enabled &&
+            ((pbss_desc->pwpa_ie == MNULL) || ((*(pbss_desc->pwpa_ie)).vend_hdr.element_id != WPA_IE)) &&
+            ((pbss_desc->prsn_ie == MNULL) || ((*(pbss_desc->prsn_ie)).ieee_hdr.element_id != RSN_IE)) &&
+            !pmpriv->adhoc_aes_enabled && pmpriv->sec_info.encryption_mode == MLAN_ENCRYPTION_MODE_NONE &&
+            !pbss_desc->privacy)
+        {
+            /* No security */
+            LEAVE();
+            return (t_s32)index;
+        }
+        else if (pmpriv->sec_info.wep_status == Wlan802_11WEPEnabled && !pmpriv->sec_info.wpa_enabled &&
+                 !pmpriv->sec_info.wpa2_enabled && !pmpriv->adhoc_aes_enabled && pbss_desc->privacy)
+        {
+            /* Static WEP enabled */
+            PRINTM(MINFO, "Disable 11n in WEP mode\n");
+            pbss_desc->disable_11n = MTRUE;
+            LEAVE();
+            return (t_s32)index;
+        }
+        else if (pmpriv->sec_info.wep_status == Wlan802_11WEPDisabled && pmpriv->sec_info.wpa_enabled &&
+                 !pmpriv->sec_info.wpa2_enabled &&
+                 ((pbss_desc->pwpa_ie != MNULL) && ((*(pbss_desc->pwpa_ie)).vend_hdr.element_id == WPA_IE)) &&
+                 !pmpriv->adhoc_aes_enabled
+                 /*
+                  * Privacy bit may NOT be set in some APs like LinkSys WRT54G
+                  * && pbss_desc->privacy
+                  */
+        )
+        {
+            /* WPA enabled */
+            PRINTM(MINFO,
+                   "wlan_is_network_compatible() WPA: index=%d wpa_ie=%#x "
+                   "rsn_ie=%#x WEP=%s WPA=%s WPA2=%s EncMode=%#x "
+                   "privacy=%#x\n",
+                   index, (pbss_desc->pwpa_ie) ? (*(pbss_desc->pwpa_ie)).vend_hdr.element_id : 0,
+                   (pbss_desc->prsn_ie) ? (*(pbss_desc->prsn_ie)).ieee_hdr.element_id : 0,
+                   (pmpriv->sec_info.wep_status == Wlan802_11WEPEnabled) ? "e" : "d",
+                   (pmpriv->sec_info.wpa_enabled) ? "e" : "d", (pmpriv->sec_info.wpa2_enabled) ? "e" : "d",
+                   pmpriv->sec_info.encryption_mode, pbss_desc->privacy);
+            if (((pmpriv->adapter->config_bands & BAND_GN || pmpriv->adapter->config_bands & BAND_AN) &&
+                 (pbss_desc->pht_cap != MNULL)) &&
+                (pmpriv->bss_mode == MLAN_BSS_MODE_INFRA) &&
+                !is_wpa_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_CCMP))
+            {
+                if (is_wpa_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_TKIP) != 0U)
+                {
+                    PRINTM(MINFO, "Disable 11n if AES is not supported by AP\n");
+                    pbss_desc->disable_11n = MTRUE;
+                }
+                else
+                {
+                    LEAVE();
+                    return -1;
+                }
+            }
+            LEAVE();
+            return (t_s32)index;
+        }
+        else if (pmpriv->sec_info.wep_status == Wlan802_11WEPDisabled && !pmpriv->sec_info.wpa_enabled &&
+                 pmpriv->sec_info.wpa2_enabled &&
+                 ((pbss_desc->prsn_ie != MNULL) && ((*(pbss_desc->prsn_ie)).ieee_hdr.element_id == RSN_IE)) &&
+                 !pmpriv->adhoc_aes_enabled
+                 /*
+                  * Privacy bit may NOT be set in some APs like LinkSys WRT54G
+                  * && pbss_desc->privacy
+                  */
+        )
+        {
+            /* WPA2 enabled */
+            PRINTM(MINFO,
+                   "wlan_is_network_compatible() WPA2: index=%d wpa_ie=%#x "
+                   "rsn_ie=%#x WEP=%s WPA=%s WPA2=%s EncMode=%#x "
+                   "privacy=%#x\n",
+                   index, (pbss_desc->pwpa_ie) ? (*(pbss_desc->pwpa_ie)).vend_hdr.element_id : 0,
+                   (pbss_desc->prsn_ie) ? (*(pbss_desc->prsn_ie)).ieee_hdr.element_id : 0,
+                   (pmpriv->sec_info.wep_status == Wlan802_11WEPEnabled) ? "e" : "d",
+                   (pmpriv->sec_info.wpa_enabled) ? "e" : "d", (pmpriv->sec_info.wpa2_enabled) ? "e" : "d",
+                   pmpriv->sec_info.encryption_mode, pbss_desc->privacy);
+            if (((pmpriv->adapter->config_bands & BAND_GN || pmpriv->adapter->config_bands & BAND_AN) &&
+                 (pbss_desc->pht_cap != MNULL)) &&
+                (pmpriv->bss_mode == MLAN_BSS_MODE_INFRA) &&
+                !is_rsn_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_CCMP))
+            {
+                if (is_rsn_oui_present(pmpriv->adapter, pbss_desc, CIPHER_SUITE_TKIP) != 0U)
+                {
+                    PRINTM(MINFO, "Disable 11n if AES is not supported by AP\n");
+                    pbss_desc->disable_11n = MTRUE;
+                }
+                else
+                {
+                    LEAVE();
+                    return -1;
+                }
+            }
+            LEAVE();
+            return (t_s32)index;
+        }
+        else if (pmpriv->sec_info.wep_status == Wlan802_11WEPDisabled && !pmpriv->sec_info.wpa_enabled &&
+                 !pmpriv->sec_info.wpa2_enabled &&
+                 ((pbss_desc->pwpa_ie == MNULL) || ((*(pbss_desc->pwpa_ie)).vend_hdr.element_id != WPA_IE)) &&
+                 ((pbss_desc->prsn_ie == MNULL) || ((*(pbss_desc->prsn_ie)).ieee_hdr.element_id != RSN_IE)) &&
+                 pmpriv->adhoc_aes_enabled && pmpriv->sec_info.encryption_mode == MLAN_ENCRYPTION_MODE_NONE &&
+                 pbss_desc->privacy)
+        {
+            /* Ad-hoc AES enabled */
+            LEAVE();
+            return (t_s32)index;
+        }
+        else if (pmpriv->sec_info.wep_status == Wlan802_11WEPDisabled && !pmpriv->sec_info.wpa_enabled &&
+                 !pmpriv->sec_info.wpa2_enabled &&
+                 ((pbss_desc->pwpa_ie == MNULL) || ((*(pbss_desc->pwpa_ie)).vend_hdr.element_id != WPA_IE)) &&
+                 ((pbss_desc->prsn_ie == MNULL) || ((*(pbss_desc->prsn_ie)).ieee_hdr.element_id != RSN_IE)) &&
+                 !pmpriv->adhoc_aes_enabled && pmpriv->sec_info.encryption_mode != MLAN_ENCRYPTION_MODE_NONE &&
+                 pbss_desc->privacy)
+        {
+            /* Dynamic WEP enabled */
+            PRINTM(MINFO,
+                   "wlan_is_network_compatible() dynamic WEP: index=%d "
+                   "wpa_ie=%#x rsn_ie=%#x EncMode=%#x privacy=%#x\n",
+                   index, (pbss_desc->pwpa_ie) ? (*(pbss_desc->pwpa_ie)).vend_hdr.element_id : 0,
+                   (pbss_desc->prsn_ie) ? (*(pbss_desc->prsn_ie)).ieee_hdr.element_id : 0,
+                   pmpriv->sec_info.encryption_mode, pbss_desc->privacy);
+            LEAVE();
+            return (t_s32)index;
+        }
+
+        else
+        {
+            /* Security doesn't match */
+            PRINTM(MINFO,
+                   "wlan_is_network_compatible() FAILED: index=%d wpa_ie=%#x "
+                   "rsn_ie=%#x WEP=%s WPA=%s WPA2=%s EncMode=%#x privacy=%#x\n",
+                   index, (pbss_desc->pwpa_ie) ? (*(pbss_desc->pwpa_ie)).vend_hdr.element_id : 0,
+                   (pbss_desc->prsn_ie) ? (*(pbss_desc->prsn_ie)).ieee_hdr.element_id : 0,
+                   (pmpriv->sec_info.wep_status == Wlan802_11WEPEnabled) ? "e" : "d",
+                   (pmpriv->sec_info.wpa_enabled) ? "e" : "d", (pmpriv->sec_info.wpa2_enabled) ? "e" : "d",
+                   pmpriv->sec_info.encryption_mode, pbss_desc->privacy);
+            LEAVE();
+            return -1;
+        }
+    }
+
+    /* Mode doesn't match */
+    LEAVE();
+    return -1;
+}
+
+
+/**
+ *  @brief Internal function used to start a scan based on an input config
+ *
+ *  Use the input user scan configuration information when provided in
+ *    order to send the appropriate scan commands to firmware to populate or
+ *    update the internal driver scan table
+ *
+ *  @param pmpriv          A pointer to mlan_private structure
+ *  @param pioctl_buf      A pointer to MLAN IOCTL Request buffer
+ *  @param puser_scan_in   Pointer to the input configuration for the requested
+ *                         scan.
+ *
+ *  @return              MLAN_STATUS_SUCCESS or < 0 if error
+ */
+mlan_status wlan_scan_networks(IN mlan_private *pmpriv,
+                               IN t_void *pioctl_buf,
+                               IN const wlan_user_scan_cfg *puser_scan_in)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    mlan_callbacks *pcb     = (mlan_callbacks *)&pmadapter->callbacks;
+    /* cmd_ctrl_node *pcmd_node = MNULL; */
+    pmlan_ioctl_req pioctl_req = (mlan_ioctl_req *)pioctl_buf;
+
+    wlan_scan_cmd_config_tlv *pscan_cfg_out = MNULL;
+    MrvlIEtypes_ChanListParamSet_t *pchan_list_out;
+    t_u32 buf_size;
+    ChanScanParamSet_t *pscan_chan_list;
+
+    t_u8 keep_previous_scan;
+    t_u8 filtered_scan;
+    t_u8 scan_current_chan_only;
+    t_u8 max_chan_per_scan;
+
+    ENTER();
+
+#if !CONFIG_MEM_POOLS
+    ret = pcb->moal_malloc(pmadapter->pmoal_handle, sizeof(wlan_scan_cmd_config_tlv), MLAN_MEM_DEF,
+                           (t_u8 **)(void **)&pscan_cfg_out);
+    if (ret != MLAN_STATUS_SUCCESS || (pscan_cfg_out == MNULL))
+#else
+    pscan_cfg_out = (wlan_scan_cmd_config_tlv *)OSA_MemoryPoolAllocate(buf_1024_MemoryPool);
+    if (pscan_cfg_out == MNULL)
+#endif
+    {
+        PRINTM(MERROR, "Memory allocation for pscan_cfg_out failed!\n");
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_NO_MEM;
+        }
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    buf_size = sizeof(ChanScanParamSet_t) * WLAN_USER_SCAN_CHAN_MAX;
+#if !CONFIG_MEM_POOLS
+    ret = pcb->moal_malloc(pmadapter->pmoal_handle, buf_size, MLAN_MEM_DEF, (t_u8 **)(void **)&pscan_chan_list);
+    if (ret != MLAN_STATUS_SUCCESS || (pscan_chan_list == MNULL))
+#else
+    pscan_chan_list = (ChanScanParamSet_t *)OSA_MemoryPoolAllocate(buf_512_MemoryPool);
+    if (pscan_chan_list == MNULL)
+#endif
+    {
+        PRINTM(MERROR, "Failed to allocate scan_chan_list\n");
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pscan_cfg_out);
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_NO_MEM;
+        }
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    (void)__memset(pmadapter, pscan_chan_list, 0x00, buf_size);
+    (void)__memset(pmadapter, pscan_cfg_out, 0x00, sizeof(wlan_scan_cmd_config_tlv));
+
+    keep_previous_scan = MFALSE;
+
+    ret = wlan_scan_setup_scan_config(pmpriv, puser_scan_in, &pscan_cfg_out->config, &pchan_list_out, pscan_chan_list,
+                                      &max_chan_per_scan, &filtered_scan, &scan_current_chan_only);
+    if (ret != MLAN_STATUS_SUCCESS)
+    {
+        PRINTM(MERROR, "Failed to setup scan config\n");
+#if !CONFIG_MEM_POOLS
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pscan_cfg_out);
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pscan_chan_list);
+#else
+        OSA_MemoryPoolFree(buf_1024_MemoryPool, pscan_cfg_out);
+        OSA_MemoryPoolFree(buf_512_MemoryPool, pscan_chan_list);
+#endif
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+        }
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    if (puser_scan_in != MNULL)
+    {
+        keep_previous_scan = puser_scan_in->keep_previous_scan;
+    }
+
+    if (keep_previous_scan == MFALSE)
+    {
+#if CONFIG_WPA_SUPP
+        BSSDescriptor_t *bss_entry = NULL;
+        int i;
+
+        for (i = 0; i < pmadapter->num_in_scan_table; i++)
+        {
+            bss_entry = &pmadapter->pscan_table[i];
+            if (bss_entry && bss_entry->ies != NULL)
+            {
+                OSA_MemoryFree(bss_entry->ies);
+            }
+        }
+#endif
+        (void)__memset(pmadapter, pmadapter->pscan_table, 0x00, sizeof(BSSDescriptor_t) * MRVDRV_MAX_BSSID_LIST);
+        pmadapter->num_in_scan_table = 0;
+    }
+
+#if CONFIG_SCAN_CHANNEL_GAP
+    pmadapter->idx_chan_stats = 0;
+#endif
+
+    split_scan_in_progress = true;
+    ret = wlan_scan_channel_list(pmpriv, pioctl_buf, max_chan_per_scan, filtered_scan, &pscan_cfg_out->config,
+                                 pchan_list_out, pscan_chan_list);
+    /* Get scan command from scan_pending_q and put to cmd_pending_q */
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        /* fixme: This functionality is not needed. Recheck later */
+    }
+#if !CONFIG_MEM_POOLS
+    (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pscan_cfg_out);
+    (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pscan_chan_list);
+#else
+    OSA_MemoryPoolFree(buf_1024_MemoryPool, pscan_cfg_out);
+    OSA_MemoryPoolFree(buf_512_MemoryPool, pscan_chan_list);
+#endif
+
+    LEAVE();
+    return ret;
+}
+
+#if !CONFIG_EXT_SCAN_SUPPORT
+/**
+ *  @brief Prepare a scan command to be sent to the firmware
+ *
+ *  Use the wlan_scan_cmd_config sent to the command processing module in
+ *   the wlan_prepare_cmd to configure a HostCmd_DS_802_11_SCAN command
+ *   struct to send to firmware.
+ *
+ *  The fixed fields specifying the BSS type and BSSID filters as well as a
+ *   variable number/length of TLVs are sent in the command to firmware.
+ *
+ *  @param pmpriv     A pointer to mlan_private structure
+ *  @param pcmd       A pointer to HostCmd_DS_COMMAND structure to be sent to
+ *                    firmware with the HostCmd_DS_801_11_SCAN structure
+ *  @param pdata_buf  Void pointer cast of a wlan_scan_cmd_config struct used
+ *                    to set the fields/TLVs for the command sent to firmware
+ *
+ *  @return           MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_802_11_scan(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *pcmd, IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_SCAN *pscan_cmd = &pcmd->params.scan;
+    wlan_scan_cmd_config *pscan_cfg;
+
+    ENTER();
+
+    pscan_cfg = (wlan_scan_cmd_config *)pdata_buf;
+
+    /* Set fixed field variables in scan command */
+    pscan_cmd->bss_mode = pscan_cfg->bss_mode;
+    (void)__memcpy(pmpriv->adapter, pscan_cmd->bssid, pscan_cfg->specific_bssid, sizeof(pscan_cmd->bssid));
+    (void)__memcpy(pmpriv->adapter, pscan_cmd->tlv_buffer, pscan_cfg->tlv_buf, pscan_cfg->tlv_buf_len);
+
+    pcmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SCAN);
+
+    /* Size is equal to the sizeof(fixed portions) + the TLV len + header */
+    pcmd->size = (t_u16)wlan_cpu_to_le16(
+        (t_u16)(sizeof(pscan_cmd->bss_mode) + sizeof(pscan_cmd->bssid) + pscan_cfg->tlv_buf_len + S_DS_GEN));
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/*
+ * Fills the pointer variables with correct address.
+ *
+ * Original mlan stores the entire beacon. We cannot do that as it would
+ * take approx 4K RAM per entry. Instead we have added some variables to
+ * the original BSSDescriptor_t structure. These will keep the data needed
+ * later. The pointers in this structure which would (ideally) point to
+ * addresses in beacon buffer now point to these internal variables.
+ *
+ * Due beacon parsing a separate structure was used. That is mem-copied
+ * into an entry in the static BSS_List. After this copy the internal
+ * pointers still point to buffer addresses in the separate structure. We
+ * will update them here.
+ */
+static void adjust_pointers_to_internal_buffers(BSSDescriptor_t *pbss_entry, BSSDescriptor_t *pbss_new_entry)
+{
+    if (pbss_entry->pht_cap != NULL)
+    {
+        pbss_entry->pht_cap = &pbss_entry->ht_cap_saved;
+    }
+    if (pbss_entry->pht_info != NULL)
+    {
+        pbss_entry->pht_info = &pbss_entry->ht_info_saved;
+    }
+#if CONFIG_11AC
+    if (pbss_entry->pvht_cap != NULL)
+    {
+        pbss_entry->pvht_cap = &pbss_entry->vht_cap_saved;
+    }
+    if (pbss_entry->pvht_oprat != NULL)
+    {
+        pbss_entry->pvht_oprat = &pbss_entry->vht_oprat_saved;
+    }
+    if (pbss_entry->pvht_txpower != NULL)
+    {
+        pbss_entry->pvht_txpower = &pbss_entry->vht_txpower_saved;
+    }
+    if (pbss_entry->ppoper_mode != NULL)
+    {
+        pbss_entry->ppoper_mode = &pbss_entry->poper_mode_saved;
+    }
+    if (pbss_entry->pext_cap != NULL)
+    {
+        pbss_entry->pext_cap = &pbss_entry->ext_cap_saved;
+    }
+#endif
+#if CONFIG_11AX
+    if (pbss_entry->phe_cap != NULL)
+    {
+        pbss_entry->phe_cap = &pbss_entry->he_cap_saved;
+    }
+    if (pbss_entry->phe_oprat != NULL)
+    {
+        pbss_entry->phe_oprat = &pbss_entry->he_oprat_saved;
+    }
+#endif
+    if (pbss_entry->pbss_co_2040 != NULL)
+    {
+        pbss_entry->pbss_co_2040 = &pbss_entry->bss_co_2040_saved;
+    }
+    if (pbss_entry->pwpa_ie != NULL)
+    {
+        pbss_entry->pwpa_ie = (IEEEtypes_VendorSpecific_t *)(void *)pbss_entry->wpa_ie_buff;
+    }
+    if (pbss_entry->prsn_ie != NULL)
+    {
+        pbss_entry->prsn_ie = (IEEEtypes_Generic_t *)(void *)pbss_entry->rsn_ie_buff;
+    }
+    if (pbss_entry->prsnx_ie != NULL)
+    {
+        pbss_entry->prsnx_ie = &pbss_entry->rsnx_ie_saved;
+    }
+#if CONFIG_WPA_SUPP
+    if (pbss_new_entry->ies != NULL)
+    {
+        pbss_entry->ies = pbss_new_entry->ies;
+    }
+#endif
+}
+
+/**
+ *  @brief This function handles the command response of scan
+ *
+ *   The response buffer for the scan command has the following
+ *      memory layout:
+ *
+ *     .-------------------------------------------------------------.
+ *     |  Header (4 * sizeof(t_u16)):  Standard command response hdr |
+ *     .-------------------------------------------------------------.
+ *     |  BufSize (t_u16) : sizeof the BSS Description data          |
+ *     .-------------------------------------------------------------.
+ *     |  NumOfSet (t_u8) : Number of BSS Descs returned             |
+ *     .-------------------------------------------------------------.
+ *     |  BSSDescription data (variable, size given in BufSize)      |
+ *     .-------------------------------------------------------------.
+ *     |  TLV data (variable, size calculated using Header->Size,    |
+ *     |            BufSize and sizeof the fixed fields above)       |
+ *     .-------------------------------------------------------------.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ret_802_11_scan(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+#if !CONFIG_MEM_POOLS
+    mlan_callbacks *pcb        = MNULL;
+    mlan_ioctl_req *pioctl_req = (mlan_ioctl_req *)pioctl_buf;
+#endif
+    /* cmd_ctrl_node *pcmd_node = MNULL; */
+    HostCmd_DS_802_11_SCAN_RSP *pscan_rsp = MNULL;
+    BSSDescriptor_t *bss_new_entry        = MNULL;
+    MrvlIEtypes_Data_t *ptlv;
+    MrvlIEtypes_TsfTimestamp_t *ptsf_tlv = MNULL;
+    t_u8 *pbss_info;
+    t_u32 scan_resp_size;
+    t_u32 bytes_left;
+    t_u32 num_in_table;
+    t_u32 bss_idx;
+    t_u32 idx;
+    t_u32 tlv_buf_size;
+    t_u64 tsf_val;
+    const chan_freq_power_t *cfp;
+    MrvlIEtypes_ChanBandListParamSet_t *pchan_band_tlv = MNULL;
+    ChanBandParamSet_t *pchan_band;
+    t_u16 band;
+    t_u8 is_bgscan_resp;
+    /* t_u32 age_ts_usec; */
+    t_u32 lowest_rssi_index = 0;
+#if CONFIG_SCAN_CHANNEL_GAP
+    MrvlIEtypes_ChannelStats_t *pchanstats_tlv = MNULL;
+#endif
+    t_u8 null_ssid[MLAN_MAX_SSID_LENGTH] = {0};
+    MrvlIEtypes_Data_t *pcurrent_tlv;
+    t_u32 tlv_buf_left;
+    t_u16 tlv_type;
+    t_u16 tlv_len;
+
+    ENTER();
+#if !CONFIG_MEM_POOLS
+    pcb = (pmlan_callbacks)&pmadapter->callbacks;
+#endif
+
+    is_bgscan_resp = ((resp->command & HostCmd_CMD_ID_MASK) == HostCmd_CMD_802_11_BG_SCAN_QUERY);
+    if (is_bgscan_resp)
+    {
+        pscan_rsp = &resp->params.bg_scan_query_resp.scan_resp;
+    }
+    else
+    {
+        pscan_rsp = &resp->params.scan_resp;
+    }
+
+    /* Note: We do not expect to have the entire list of AP's with us in
+       the driver. This is because we are memory constrained. So will
+       modify the handling of the AP list and keep only AP's with high RSSI */
+
+    bytes_left = wlan_le16_to_cpu(pscan_rsp->bss_descript_size);
+    PRINTM(MINFO, "SCAN_RESP: bss_descript_size %d\n", bytes_left);
+
+    if ((pscan_rsp->number_of_sets == 0U) && (bytes_left == 0U))
+    {
+        wscan_d("SCAN_RESP: number of sets are zero");
+        goto done;
+    }
+
+    scan_resp_size = resp->size;
+
+    PRINTM(MINFO, "SCAN_RESP: returned %d APs before parsing\n", pscan_rsp->number_of_sets);
+
+    num_in_table = pmadapter->num_in_scan_table;
+    pbss_info    = pscan_rsp->bss_desc_and_tlv_buffer;
+
+    /*
+     * The size of the TLV buffer is equal to the entire command response
+     *   size (scan_resp_size) minus the fixed fields (sizeof()'s), the
+     *   BSS Descriptions (bss_descript_size as bytesLef) and the command
+     *   response header (S_DS_GEN)
+     */
+    tlv_buf_size = scan_resp_size -
+                   (bytes_left + sizeof(pscan_rsp->bss_descript_size) + sizeof(pscan_rsp->number_of_sets) + S_DS_GEN);
+
+    if (is_bgscan_resp && (tlv_buf_size > sizeof(resp->params.bg_scan_query_resp.report_condition)))
+    {
+        tlv_buf_size -= sizeof(resp->params.bg_scan_query_resp.report_condition);
+    }
+    ptlv = (MrvlIEtypes_Data_t *)(void *)(pscan_rsp->bss_desc_and_tlv_buffer + bytes_left);
+
+    pcurrent_tlv = ptlv;
+    tlv_buf_left = tlv_buf_size;
+
+    wscan_d("SCAN_RESP: tlv_buf_size = %d", tlv_buf_size);
+
+    while (tlv_buf_left >= sizeof(MrvlIEtypesHeader_t))
+    {
+        /* Barriers are normally not required but do ensure the code is
+         * completely within the specified behaviour for the architecture. */
+        __asm volatile("dsb" ::: "memory");
+        __asm volatile("isb");
+        tlv_type = wlan_le16_to_cpu(pcurrent_tlv->header.type);
+        tlv_len  = wlan_le16_to_cpu(pcurrent_tlv->header.len);
+
+        if (sizeof(ptlv->header) + tlv_len > tlv_buf_left)
+        {
+            wscan_d("SCAN_RESP: TLV buffer corrupt");
+            break;
+        }
+
+        switch (tlv_type)
+        {
+            case TLV_TYPE_TSFTIMESTAMP:
+                wscan_d("SCAN_RESP: TSF Timestamp TLV, len = %d", tlv_len);
+                ptsf_tlv = (MrvlIEtypes_TsfTimestamp_t *)pcurrent_tlv;
+                break;
+            case TLV_TYPE_CHANNELBANDLIST:
+                wscan_d("SCAN_RESP: CHANNEL BAND LIST TLV, len = %d", tlv_len);
+                pchan_band_tlv = (MrvlIEtypes_ChanBandListParamSet_t *)pcurrent_tlv;
+                break;
+#if CONFIG_SCAN_CHANNEL_GAP
+            case TLV_TYPE_CHANNEL_STATS:
+                wscan_d("SCAN_RESP: CHANNEL STATS TLV, len = %d", tlv_len);
+                pchanstats_tlv = (MrvlIEtypes_ChannelStats_t *)pcurrent_tlv;
+                break;
+#endif
+            default:
+                wscan_d("SCAN_RESP: Unhandled TLV = %d", tlv_type);
+                break;
+        }
+
+        tlv_buf_left -= (sizeof(ptlv->header) + tlv_len);
+        pcurrent_tlv = (MrvlIEtypes_Data_t *)(void *)(pcurrent_tlv->data + tlv_len);
+
+    } /* while */
+
+#if CONFIG_SCAN_CHANNEL_GAP
+    if (pchanstats_tlv != MNULL)
+    {
+        wlan_update_chan_statistics(pmpriv, pchanstats_tlv);
+    }
+#endif
+
+    /*
+     *  Process each scan response returned (pscan_rsp->number_of_sets).  Save
+     *    the information in the bss_new_entry and then insert into the
+     *    driver scan table either as an update to an existing entry
+     *    or as an addition at the end of the table
+     */
+#if !CONFIG_MEM_POOLS
+    ret = pcb->moal_malloc(pmadapter->pmoal_handle, sizeof(BSSDescriptor_t), MLAN_MEM_DEF,
+                           (t_u8 **)(void **)&bss_new_entry);
+
+    if (ret != MLAN_STATUS_SUCCESS || (bss_new_entry == MNULL))
+    {
+        PRINTM(MERROR, "Memory allocation for bss_new_entry failed!\n");
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_ERROR_NO_MEM;
+        }
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+#else
+    bss_new_entry = &s_bss_new_entry;
+#endif
+
+    idx = 0;
+    while (idx < pscan_rsp->number_of_sets && bytes_left)
+    {
+        /* Zero out the bss_new_entry we are about to store info in */
+        (void)__memset(pmadapter, bss_new_entry, 0x00, sizeof(BSSDescriptor_t));
+
+        /* Process the data fields and IEs returned for this BSS */
+        if (wlan_interpret_bss_desc_with_ie(pmadapter, bss_new_entry, &pbss_info, &bytes_left, MFALSE) ==
+            MLAN_STATUS_SUCCESS)
+        {
+            wscan_d("SCAN_RESP: BSSID = %02x:%02x:%02x:%02x:%02x:%02x", bss_new_entry->mac_address[0],
+                    bss_new_entry->mac_address[1], bss_new_entry->mac_address[2], bss_new_entry->mac_address[3],
+                    bss_new_entry->mac_address[4], bss_new_entry->mac_address[5]);
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+            if (pmpriv->wps.session_enable == MTRUE)
+            {
+                if ((bss_new_entry->wps_IE_exist == MFALSE) || (bss_new_entry->wps_session == 0xffff))
+                {
+                    if (bss_new_entry->ies != NULL)
+                    {
+                        OSA_MemoryFree(bss_new_entry->ies);
+                        bss_new_entry->ies = NULL;
+                    }
+                    continue;
+                }
+            }
+#endif /* CONFIG_WPA_SUPP_WPS */
+#endif
+
+            /*
+             * Search the scan table for the same bssid
+             */
+            for (bss_idx = 0; bss_idx < num_in_table; bss_idx++)
+            {
+                if (!__memcmp(pmadapter, bss_new_entry->mac_address, pmadapter->pscan_table[bss_idx].mac_address,
+                              sizeof(bss_new_entry->mac_address)))
+                {
+                    /*
+                     * If the SSID matches as well, it is a duplicate of
+                     *   this entry.  Keep the bss_idx set to this
+                     *   entry so we replace the old contents in the table
+                     */
+                    if ((bss_new_entry->ssid.ssid_len == pmadapter->pscan_table[bss_idx].ssid.ssid_len) &&
+                        (!__memcmp(pmadapter, bss_new_entry->ssid.ssid, pmadapter->pscan_table[bss_idx].ssid.ssid,
+                                   bss_new_entry->ssid.ssid_len)))
+                    {
+                        wscan_d("SCAN_RESP: Duplicate of index: %d", bss_idx);
+                        break;
+                    }
+                    /*
+                     * If the SSID is NULL for same BSSID
+                     * keep the bss_idx set to this entry
+                     * so we replace the old contents in
+                     * the table
+                     */
+                    if (!__memcmp(pmadapter, pmadapter->pscan_table[bss_idx].ssid.ssid, null_ssid,
+                                  pmadapter->pscan_table[bss_idx].ssid.ssid_len))
+                    {
+                        wscan_d("SCAN_RESP: Duplicate of index: %d", bss_idx);
+                        break;
+                    }
+                }
+            }
+            /*
+             * If the bss_idx is equal to the number of entries in the table,
+             *   the new entry was not a duplicate; append it to the scan
+             *   table
+             */
+            if (bss_idx == num_in_table)
+            {
+                /* Range check the bss_idx, keep it limited to the last entry */
+                if (bss_idx == MRVDRV_MAX_BSSID_LIST)
+                {
+                    lowest_rssi_index = wlan_find_worst_network_in_list(pmadapter->pscan_table, MRVDRV_MAX_BSSID_LIST);
+                }
+                else
+                {
+                    num_in_table++;
+                }
+            }
+            else
+            {
+                if ((bss_new_entry->channel != pmadapter->pscan_table[bss_idx].channel) &&
+                    (bss_new_entry->rssi > pmadapter->pscan_table[bss_idx].rssi))
+                {
+                    wscan_d("skip update the duplicate entry with low rssi");
+#if CONFIG_WPA_SUPP
+                    if (bss_new_entry->ies != NULL)
+                    {
+                        OSA_MemoryFree(bss_new_entry->ies);
+                        bss_new_entry->ies = NULL;
+                    }
+#endif
+                    continue;
+                }
+            }
+
+            /* fixme: Don't know if we need this right now */
+            /*
+             * If the TSF TLV was appended to the scan results, save
+             *   this entry's TSF value in the networkTSF field.  The
+             *   networkTSF is the firmware's TSF value at the time the
+             *   beacon or probe response was received.
+             */
+            if (ptsf_tlv != MNULL)
+            {
+                (void)__memcpy(pmpriv->adapter, &tsf_val, &ptsf_tlv->tsf_data[idx * TSF_DATA_SIZE], sizeof(tsf_val));
+                tsf_val = wlan_le64_to_cpu(tsf_val);
+                (void)__memcpy(pmpriv->adapter, &bss_new_entry->network_tsf, &tsf_val,
+                               sizeof(bss_new_entry->network_tsf));
+            }
+            band = BAND_G;
+            if (pchan_band_tlv != MNULL)
+            {
+                pchan_band = &pchan_band_tlv->chan_band_param[idx];
+                if (bss_new_entry->channel == 0)
+                {
+                    bss_new_entry->channel = pchan_band->chan_number;
+                }
+                band = radio_type_to_band(pchan_band->radio_type & (MBIT(0) | MBIT(1)));
+            }
+
+            /* Save the band designation for this entry for use in join */
+            bss_new_entry->bss_band = band;
+            cfp = wlan_find_cfp_by_band_and_channel(pmadapter, bss_new_entry->bss_band, (t_u16)bss_new_entry->channel);
+
+            if (cfp != MNULL)
+            {
+                bss_new_entry->freq = cfp->freq;
+            }
+            else
+            {
+                bss_new_entry->freq = 0;
+            }
+
+            if ((is_bgscan_resp) && (pmpriv->roaming_enabled == MTRUE))
+            {
+                if (num_in_table == 2U)
+                {
+                    if (pmadapter->pscan_table[0].rssi > bss_new_entry->rssi)
+                    {
+#if CONFIG_WPA_SUPP
+                        /* If the scan table is full, free ies of the lowest rssi entry before this entry is replaced */
+                        if (pmadapter->pscan_table[0].ies != NULL)
+                        {
+                            OSA_MemoryFree(pmadapter->pscan_table[0].ies);
+                            pmadapter->pscan_table[0].ies = NULL;
+                        }
+#endif
+                        (void)__memcpy(pmadapter, &pmadapter->pscan_table[0], bss_new_entry,
+                                       sizeof(pmadapter->pscan_table[0]));
+                        adjust_pointers_to_internal_buffers(&pmadapter->pscan_table[0], bss_new_entry);
+                    }
+#if CONFIG_WPA_SUPP
+                    /* If the scan table is full, free ies of the new entry with lowest rssi, which won't be added into
+                     * table */
+                    else
+                    {
+                        if (bss_new_entry->ies != NULL)
+                        {
+                            OSA_MemoryFree(bss_new_entry->ies);
+                            bss_new_entry->ies = NULL;
+                        }
+                    }
+#endif
+                    num_in_table--;
+                    continue;
+                }
+            }
+
+            if (bss_idx == MRVDRV_MAX_BSSID_LIST)
+            {
+                if (pmadapter->pscan_table[lowest_rssi_index].rssi > bss_new_entry->rssi)
+                {
+#if CONFIG_WPA_SUPP
+                    /* If the scan table is full, free ies of the lowest rssi entry before this entry is replaced */
+                    if (pmadapter->pscan_table[lowest_rssi_index].ies != NULL)
+                    {
+                        OSA_MemoryFree(pmadapter->pscan_table[lowest_rssi_index].ies);
+                        pmadapter->pscan_table[lowest_rssi_index].ies = NULL;
+                    }
+#endif
+                    (void)__memcpy(pmadapter, &pmadapter->pscan_table[lowest_rssi_index], bss_new_entry,
+                                   sizeof(pmadapter->pscan_table[lowest_rssi_index]));
+                    adjust_pointers_to_internal_buffers(&pmadapter->pscan_table[lowest_rssi_index], bss_new_entry);
+                }
+#if CONFIG_WPA_SUPP
+                /* If the scan table is full, free ies of the new entry with lowest rssi, which won't be added into
+                 * table */
+                else
+                {
+                    if (bss_new_entry->ies != NULL)
+                    {
+                        OSA_MemoryFree(bss_new_entry->ies);
+                        bss_new_entry->ies = NULL;
+                    }
+                }
+#endif
+            }
+            else
+            {
+#if CONFIG_WPA_SUPP
+                /* Free ies of the old entry if it's duplicate entry */
+                if (pmadapter->pscan_table[bss_idx].ies != NULL)
+                {
+                    OSA_MemoryFree(pmadapter->pscan_table[bss_idx].ies);
+                    pmadapter->pscan_table[bss_idx].ies = NULL;
+                }
+#endif
+
+                /* Copy the locally created bss_new_entry to the scan table */
+                (void)__memcpy(pmadapter, &pmadapter->pscan_table[bss_idx], bss_new_entry,
+                               sizeof(pmadapter->pscan_table[bss_idx]));
+                adjust_pointers_to_internal_buffers(&pmadapter->pscan_table[bss_idx], bss_new_entry);
+            }
+        }
+        else
+        {
+            /* Error parsing/interpreting the scan response, skipped */
+            PRINTM(MERROR, "SCAN_RESP: wlan_interpret_bss_desc_with_ie returned error\n");
+#if CONFIG_WPA_SUPP
+            if (bss_new_entry->ies != NULL)
+            {
+                OSA_MemoryFree(bss_new_entry->ies);
+                bss_new_entry->ies = NULL;
+            }
+#endif
+        }
+        idx++;
+    }
+
+    wscan_d("SCAN_RESP: Scanned %2d APs, %d valid, %d total", pscan_rsp->number_of_sets,
+            num_in_table - pmadapter->num_in_scan_table, num_in_table);
+
+    /* Update the total number of BSSIDs in the scan table */
+    pmadapter->num_in_scan_table = num_in_table;
+
+    /* fixme: the following code does not seem relevant */
+
+done:
+#if !CONFIG_MEM_POOLS
+    if (bss_new_entry != MNULL)
+    {
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)bss_new_entry);
+    }
+#endif
+
+    LEAVE();
+    return ret;
+}
+
+#if (CONFIG_EXT_SCAN_SUPPORT)
+/**
+ *  @brief Prepare an extended scan command to be sent to the firmware
+ *
+ *  Use the wlan_scan_cmd_config sent to the command processing module in
+ *   the wlan_prepare_cmd to configure a HostCmd_DS_802_11_SCAN_EXT command
+ *   struct to send to firmware.
+ *
+ *  @param pmpriv     A pointer to mlan_private structure
+ *  @param pcmd       A pointer to HostCmd_DS_COMMAND structure to be sent to
+ *                    firmware with the HostCmd_DS_802_11_SCAN_EXT structure
+ *  @param pdata_buf  Void pointer cast of a wlan_scan_cmd_config struct used
+ *                    to set the fields/TLVs for the command sent to firmware
+ *
+ *  @return           MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_802_11_scan_ext(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *pcmd, IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_SCAN_EXT *pext_scan_cmd = &pcmd->params.ext_scan;
+    wlan_scan_cmd_config *pscan_cfg           = MNULL;
+
+    ENTER();
+
+    pscan_cfg = (wlan_scan_cmd_config *)pdata_buf;
+
+    /* Set fixed field variables in scan command */
+    pext_scan_cmd->reserved = 0x00;
+    (void)__memcpy(pmpriv->adapter, pext_scan_cmd->tlv_buffer, pscan_cfg->tlv_buf, pscan_cfg->tlv_buf_len);
+
+    pcmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SCAN_EXT);
+
+    /* Size is equal to the sizeof(fixed portions) + the TLV len + header */
+    pcmd->size = wlan_cpu_to_le16((t_u16)(sizeof(pext_scan_cmd->reserved) + pscan_cfg->tlv_buf_len + S_DS_GEN));
+
+    LEAVE();
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of extended scan
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ret_802_11_scan_ext(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *resp, IN t_void *pioctl_buf)
+{
+#if (CONFIG_SCAN_CHANNEL_GAP) || defined(EXT_SCAN_ENH)
+    HostCmd_DS_802_11_SCAN_EXT *pext_scan_cmd = &(resp->params.ext_scan);
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+    MrvlIEtypesHeader_t *tlv                  = MNULL;
+    MrvlIEtypes_ChannelStats_t *tlv_chanstats = MNULL;
+    t_u16 tlv_buf_left                        = 0;
+    t_u16 tlv_type                            = 0;
+    t_u16 tlv_len                             = 0;
+#endif
+#ifdef EXT_SCAN_ENH
+    t_u32 ext_scan_type;
+    mlan_callbacks *pcb        = (mlan_callbacks *)&pmpriv->adapter->callbacks;
+    pmlan_ioctl_req pioctl_req = (pmlan_ioctl_req)pioctl_buf;
+    mlan_adapter *pmadapter    = pmpriv->adapter;
+#endif
+    ENTER();
+
+    PRINTM(MINFO, "EXT scan returns successfully\n");
+#ifdef EXT_SCAN_ENH
+    pmadapter->scan_state |= wlan_get_ext_scan_state(resp);
+    ext_scan_type = pext_scan_cmd->ext_scan_type;
+    if (ext_scan_type == EXT_SCAN_CANCEL)
+    {
+        PRINTM(MCMND, "Cancel scan command completed!\n");
+        wlan_request_cmd_lock(pmadapter);
+        pmadapter->scan_processing = MFALSE;
+        pmadapter->scan_state |= SCAN_STATE_SCAN_COMPLETE;
+        pmadapter->ext_scan_type = EXT_SCAN_DEFAULT;
+#ifdef HOST_CCX
+        pmadapter->scan_data_block = MFALSE;
+#endif
+        wlan_release_cmd_lock(pmadapter);
+        /* Need to indicate IOCTL complete */
+        if (pioctl_req != MNULL)
+        {
+            pioctl_req->status_code = MLAN_STATUS_SUCCESS;
+            /* Indicate ioctl complete */
+            pcb->moal_ioctl_complete(pmadapter->pmoal_handle, (pmlan_ioctl_req)pioctl_req, MLAN_STATUS_SUCCESS);
+        }
+        LEAVE();
+        return MLAN_STATUS_SUCCESS;
+    }
+    else if (ext_scan_type == EXT_SCAN_ENHANCE)
+    {
+        /* Setup the timer after scan command response */
+        pcb->moal_start_timer(pmpriv->adapter->pmoal_handle, pmpriv->adapter->pmlan_cmd_timer, MFALSE,
+                              MRVDRV_TIMER_10S * 2);
+        pmpriv->adapter->cmd_timer_is_set = MTRUE;
+        LEAVE();
+        return MLAN_STATUS_SUCCESS;
+    }
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+    tlv          = (MrvlIEtypesHeader_t *)pext_scan_cmd->tlv_buffer;
+    tlv_buf_left = resp->size - (sizeof(HostCmd_DS_802_11_SCAN_EXT) - 1 + S_DS_GEN);
+    while (tlv_buf_left >= sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+        if (tlv_buf_left < (tlv_len + sizeof(MrvlIEtypesHeader_t)))
+        {
+            PRINTM(MERROR, "Error processing scan gap TLV\n");
+            break;
+        }
+        switch (tlv_type)
+        {
+            case TLV_TYPE_CHANNEL_STATS:
+                tlv_chanstats = (MrvlIEtypes_ChannelStats_t *)tlv;
+                wlan_update_chan_statistics(pmpriv, tlv_chanstats);
+                break;
+            default:
+                break;
+        }
+        tlv_buf_left -= tlv_len + sizeof(MrvlIEtypesHeader_t);
+        tlv = (MrvlIEtypesHeader_t *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+#endif
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/** 8 bytes timestamp, 2 bytest interval, 2 bytes capability */
+#define BEACON_FIX_SIZE 12
+
+/**
+ *  @brief This function realloc the beacon buffer and update ssid for new entry
+ *
+ *  @param pmadpater        A pointer to mlan_adapter structure
+ *  @param pbss_entry       A pointer to the bss_entry which has multi-bssid IE
+ *  @param pnew_entry       A pinter to new entry
+ *  @param pssid            A pointer to ssid IE
+ *  @param pnew_extcap      A pointer to EXT CAP IE
+ *  @param pnew_rsnx        A pointer to RSNX IE
+ *  @param pnew_rsn         A pointer to RSN IE
+ *
+ *  @return                MLAN_STATUS_FAILURE/MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_update_ssid_in_beacon_buf(mlan_adapter *pmadapter,
+                                                  BSSDescriptor_t *pbss_entry,
+                                                  BSSDescriptor_t *pnew_entry,
+                                                  IEEEtypes_Ssid_t *pssid,
+                                                  IEEEtypes_ExtCap_t *pnew_extcap,
+                                                  IEEEtypes_Generic_t *pnew_rsnx,
+                                                  IEEEtypes_Generic_t *pnew_rsn)
+{
+#if CONFIG_WPA_SUPP
+    mlan_callbacks *pcb = (pmlan_callbacks)&pmadapter->callbacks;
+    t_u8 *pbeacon_buf   = MNULL;
+#endif
+    t_u32 beacon_buf_size = 0;
+    t_s8 offset           = pnew_entry->ssid.ssid_len - pbss_entry->ssid.ssid_len;
+    mlan_status ret       = MLAN_STATUS_FAILURE;
+
+    if (pnew_entry->ssid.ssid_len >= pbss_entry->ssid.ssid_len)
+        beacon_buf_size = pbss_entry->beacon_buf_size + (pnew_entry->ssid.ssid_len - pbss_entry->ssid.ssid_len);
+    else
+        beacon_buf_size = pbss_entry->beacon_buf_size - (pbss_entry->ssid.ssid_len - pnew_entry->ssid.ssid_len);
+
+    if (pnew_rsnx)
+        beacon_buf_size += pnew_rsnx->ieee_hdr.len + sizeof(IEEEtypes_Header_t);
+#if CONFIG_WPA_SUPP
+    ret = pcb->moal_malloc(pmadapter->pmoal_handle, beacon_buf_size, MLAN_MEM_DEF, (t_u8 **)&pbeacon_buf);
+    if (ret != MLAN_STATUS_SUCCESS || !pbeacon_buf)
+    {
+        wifi_d("Memory allocation for beacon buf for bss_new_entry");
+        goto done;
+    }
+#endif
+
+#if CONFIG_WIFI_IO_DUMP
+    wifi_d("BSS Entry");
+    dump_hex(pbss_entry->pbeacon_buf, pbss_entry->beacon_buf_size);
+#endif
+
+    pnew_entry->beacon_buf_size = beacon_buf_size;
+#if CONFIG_WPA_SUPP
+    pnew_entry->pbeacon_buf = pbeacon_buf;
+#else
+    pnew_entry->pbeacon_buf = pbss_entry->pbeacon_buf;
+#endif
+    if (pnew_entry->pext_cap)
+    {
+        pnew_entry->ext_cap_offset += offset;
+        if (pnew_extcap)
+        {
+            (void)__memcpy(pmadapter, &pnew_entry->ext_cap_saved, pnew_extcap, sizeof(IEEEtypes_ExtCap_t));
+            pnew_entry->pext_cap = &pnew_entry->ext_cap_saved;
+        }
+    }
+    if (pnew_rsnx)
+    {
+        (void)__memcpy(pmadapter, &pnew_entry->rsnx_ie_saved, pnew_rsnx,
+                       pnew_rsnx->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+        pnew_entry->prsnx_ie = &pnew_entry->rsnx_ie_saved;
+    }
+
+    if (pnew_rsn)
+    {
+        (void)__memcpy(pmadapter, pnew_entry->rsn_ie_buff, pnew_rsn,
+                       pnew_rsn->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+        pnew_entry->rsn_ie_buff_len = pnew_rsn->ieee_hdr.len + sizeof(IEEEtypes_Header_t);
+        pnew_entry->prsn_ie         = (IEEEtypes_Generic_t *)pnew_entry->rsn_ie_buff;
+    }
+
+#if CONFIG_WPA_SUPP
+    /** copy fixed IE */
+    (void)__memcpy(pmadapter, pbeacon_buf, pbss_entry->pbeacon_buf, BEACON_FIX_SIZE);
+    /** copy new ssid ie */
+    (void)__memcpy(pmadapter, pbeacon_buf + BEACON_FIX_SIZE, (t_u8 *)pssid, pssid->len + sizeof(IEEEtypes_Header_t));
+    /** copy left IE to new beacon buffer */
+    (void)__memcpy(
+        pmadapter, pbeacon_buf + BEACON_FIX_SIZE + pssid->len + sizeof(IEEEtypes_Header_t),
+        pbss_entry->pbeacon_buf + BEACON_FIX_SIZE + pbss_entry->ssid.ssid_len + sizeof(IEEEtypes_Header_t),
+        pbss_entry->beacon_buf_size - BEACON_FIX_SIZE - (pbss_entry->ssid.ssid_len + sizeof(IEEEtypes_Header_t)));
+#if 0
+    /* adjust the ie pointer */
+    if (pnew_entry->pwpa_ie)
+        pnew_entry->wpa_offset += offset;
+    if (pnew_entry->prsn_ie)
+        pnew_entry->rsn_offset += offset;
+
+#ifdef ENABLE_HOTSPOT
+    if (pnew_entry->posen_ie)
+        pnew_entry->osen_offset += offset;
+#endif /* ENABLE_HOTSPOT */
+#if CONFIG_11R
+    if (pnew_entry->pmd_ie)
+        pnew_entry->md_offset += offset;
+#endif /* ENABLE_HOTSPOT */
+    if (pnew_entry->pht_cap)
+        pnew_entry->ht_cap_offset += offset;
+    if (pnew_entry->pht_info)
+        pnew_entry->ht_info_offset += offset;
+    if (pnew_entry->pbss_co_2040)
+        pnew_entry->bss_co_2040_offset += offset;
+    if (pnew_entry->poverlap_bss_scan_param)
+        pnew_entry->overlap_bss_offset += offset;
+#if CONFIG_11AC
+    if (pnew_entry->pvht_cap)
+        pnew_entry->vht_cap_offset += offset;
+    if (pnew_entry->pvht_oprat)
+        pnew_entry->vht_oprat_offset += offset;
+    if (pnew_entry->pvht_txpower)
+        pnew_entry->vht_txpower_offset += offset;
+    if (pnew_entry->pext_pwer)
+        pnew_entry->ext_pwer_offset += offset;
+    if (pnew_entry->pext_bssload)
+        pnew_entry->ext_bssload_offset += offset;
+    if (pnew_entry->pquiet_chan)
+        pnew_entry->quiet_chan_offset += offset;
+    if (pnew_entry->poper_mode)
+        pnew_entry->oper_mode_offset += offset;
+#endif /* CONFIG_11AC */
+#if CONFIG_11AX
+    if (pnew_entry->phe_cap)
+        pnew_entry->he_cap_offset += offset;
+    if (pnew_entry->phe_oprat)
+        pnew_entry->he_oprat_offset += offset;
+#endif /* CONFIG_11AX */
+#ifdef ENABLE_802_116E
+    if (pnew_entry->phe_6g_cap)
+        pnew_entry->he_6g_cap_offset += offset;
+#endif
+#endif
+
+#if CONFIG_WIFI_IO_DUMP
+    wifi_d("BSS New Entry");
+    dump_hex(pbeacon_buf, beacon_buf_size);
+#endif
+#endif
+    ret = MLAN_STATUS_SUCCESS;
+#if CONFIG_WPA_SUPP
+done:
+#endif
+    return ret;
+}
+
+/**
+ *  @brief This function generate the bssid from bssid_idx
+ *
+ *  @param pmadpater        A pointer to mlan_adapter structure
+ *  @param pbss_entry       A pointer to the bss_entry which has multi-bssid IE
+ *  @param pnew_entry       A pinter to new entry
+ *  @param bssid_index      bssid_index from BSSID_IDX IE
+ *
+ *  @return                N/A
+ */
+static void wlan_gen_multi_bssid_by_bssid_index(pmlan_adapter pmadapter,
+                                                BSSDescriptor_t *pbss_entry,
+                                                BSSDescriptor_t *pnew_entry,
+                                                t_u8 bssid_index,
+                                                t_u8 max_bssid_indicator)
+{
+    t_u8 mask = 0xff;
+    t_u8 new_bssid[6];
+    t_u8 bssid_a;
+    t_u8 src_bssid[6];
+    (void)__memcpy(pmadapter, (t_u8 *)src_bssid, pbss_entry->mac_address,
+                   MIN(sizeof(mlan_802_11_mac_addr), sizeof(src_bssid)));
+    (void)__memcpy(pmadapter, (t_u8 *)new_bssid, (t_u8 *)&pbss_entry->mac_address,
+                   MIN(sizeof(mlan_802_11_mac_addr), sizeof(new_bssid)));
+
+    mask         = (mask >> (8 - max_bssid_indicator));
+    bssid_a      = src_bssid[5] & (~mask);
+    src_bssid[5] = (src_bssid[5] + bssid_index) & mask;
+    new_bssid[5] = bssid_a | src_bssid[5];
+
+    (void)__memcpy(pmadapter, (t_u8 *)&pnew_entry->mac_address, new_bssid,
+                   MIN(sizeof(new_bssid), sizeof(mlan_802_11_mac_addr)));
+    (void)__memcpy(pmadapter, (t_u8 *)&pnew_entry->multi_bssid_ap_addr, (t_u8 *)&pbss_entry->mac_address,
+                   MIN(sizeof(mlan_802_11_mac_addr), sizeof(mlan_802_11_mac_addr)));
+}
+
+/**
+ *  @brief This function parse the non_trans_bssid_profile
+ *
+ *  @param pmadapter        A pointer to mlan_adapter structure
+ *  @param pbss_entry       A pointer to BSSDescriptor_t which has multi-bssid
+ * IE
+ *  @param pbss_profile     A pointer to IEEEtypes_NonTransBSSIDprofile_t
+ *  @param num_in_table     A pointer to buffer to save num of entry in scan
+ * table.
+ *  @param  max_bssid_indicator max bssid indicator
+ *
+ *  @return                 N/A
+ */
+static t_void wlan_parse_non_trans_bssid_profile(mlan_private *pmpriv,
+                                                 BSSDescriptor_t *pbss_entry,
+                                                 IEEEtypes_NonTransBSSIDProfile_t *pbss_profile,
+                                                 t_u32 *num_in_table,
+                                                 t_u8 max_bssid_indicator)
+{
+    mlan_adapter *pmadapter                   = pmpriv->adapter;
+    IEEEtypes_Header_t *pheader               = (IEEEtypes_Header_t *)pbss_profile->profile_data;
+    IEEEtypes_MultiBSSIDIndex_t *pbssid_index = MNULL;
+    IEEEtypes_Ssid_t *pssid                   = MNULL;
+    IEEEtypes_Generic_t *prsn                 = MNULL;
+    IEEEtypes_NotxBssCap_t *pcap              = (IEEEtypes_NotxBssCap_t *)pbss_profile->profile_data;
+    t_u8 *pos                                 = pbss_profile->profile_data;
+    t_s8 left_len                             = pbss_profile->ieee_hdr.len;
+    t_u8 ret                                  = MFALSE;
+    t_u32 bss_idx;
+    t_u32 lowest_rssi_index        = 0;
+    t_u32 num_in_tbl               = *num_in_table;
+    mlan_callbacks *pcb            = (pmlan_callbacks)&pmadapter->callbacks;
+    BSSDescriptor_t *bss_new_entry = MNULL;
+#if CONFIG_WPA_SUPP
+    t_u8 *pbeacon_buf = MNULL;
+#endif
+    IEEEtypes_ExtCap_t *pextcap = MNULL;
+    IEEEtypes_Generic_t *prsnx  = MNULL;
+
+    ENTER();
+
+    /* The first element within the Nontransmitted
+     * BSSID Profile is not the Nontransmitted
+     * BSSID Capability element.
+     */
+    if (pcap->element_id != NONTX_BSSID_CAP || pcap->len != 2)
+    {
+        PRINTM(MERROR,
+               "The first element within the Nontransmitted BSSID Profile is not the NontransmittedBSSID Capability "
+               "element\n");
+        LEAVE();
+        return;
+    }
+
+    while (left_len >= 2)
+    {
+        pheader = (IEEEtypes_Header_t *)pos;
+        if ((t_s8)(pheader->len + sizeof(IEEEtypes_Header_t)) > left_len)
+        {
+            PRINTM(MMSG, "invalid IE length = %d left len %d\n", pheader->len, left_len);
+            break;
+        }
+        switch (pheader->element_id)
+        {
+            case MBSSID_INDEX:
+                pbssid_index = (IEEEtypes_MultiBSSIDIndex_t *)pos;
+                if (pbssid_index->bssid_index == 0 || pbssid_index->bssid_index > 46)
+                {
+                    PRINTM(MERROR, " No valid Multiple BSSID-Index element\n");
+                    goto done;
+                }
+                PRINTM(MCMND, "MBSSID: Find mbssid_index=%d\n", pbssid_index->bssid_index);
+                ret = MTRUE;
+                break;
+            case EXT_CAPABILITY:
+                pextcap = (IEEEtypes_ExtCap_t *)pos;
+                DBG_HEXDUMP(MCMD_D, "MBSSID extcap", pos, pextcap->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                break;
+            case RSNX_IE:
+                prsnx = (IEEEtypes_Generic_t *)pos;
+                DBG_HEXDUMP(MCMD_D, "MBSSID RSNX", pos, prsnx->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                break;
+            case SSID:
+                pssid = (IEEEtypes_Ssid_t *)pos;
+                PRINTM(MCMND, "MBSSID: Find mbssid ssid=%s\n", pssid->ssid);
+                break;
+            case RSN_IE:
+                prsn = (IEEEtypes_Generic_t *)pos;
+                DBG_HEXDUMP(MCMD_D, "MBSSID RSN", pos, prsn->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+                break;
+            default:
+                break;
+        }
+        left_len -= pheader->len + sizeof(IEEEtypes_Header_t);
+        pos += pheader->len + sizeof(IEEEtypes_Header_t);
+    }
+    if (ret == MTRUE)
+    {
+#if !CONFIG_MEM_POOLS
+        ret = pcb->moal_malloc(pmadapter->pmoal_handle, sizeof(BSSDescriptor_t), MLAN_MEM_DEF, (t_u8 **)&bss_new_entry);
+        if (ret != MLAN_STATUS_SUCCESS || !bss_new_entry)
+        {
+            PRINTM(MERROR, "Memory allocation for bss_new_entry failed!\n");
+            goto done;
+        }
+#else
+        bss_new_entry = &s2_bss_new_entry;
+#endif
+        (void)__memcpy(pmadapter, bss_new_entry, pbss_entry, sizeof(BSSDescriptor_t));
+        wlan_gen_multi_bssid_by_bssid_index(pmadapter, pbss_entry, bss_new_entry, pbssid_index->bssid_index,
+                                            max_bssid_indicator);
+        if (pssid)
+        {
+            __memset(pmadapter, (t_u8 *)&bss_new_entry->ssid, 0, sizeof(mlan_802_11_ssid));
+            bss_new_entry->ssid.ssid_len = pssid->len;
+            (void)__memcpy(pmadapter, bss_new_entry->ssid.ssid, pssid->ssid, MIN(pssid->len, MLAN_MAX_SSID_LENGTH));
+            if (MLAN_STATUS_SUCCESS !=
+                wlan_update_ssid_in_beacon_buf(pmadapter, pbss_entry, bss_new_entry, pssid, pextcap, prsnx, prsn))
+            {
+                PRINTM(MERROR, "Fail to update MBSSID beacon buf\n");
+                pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)bss_new_entry);
+                goto done;
+            }
+#if CONFIG_WPA_SUPP
+            pbeacon_buf = bss_new_entry->pbeacon_buf;
+#endif
+        }
+        (void)__memcpy(pmadapter, &bss_new_entry->cap_info, &pcap->cap,
+                       MIN(sizeof(IEEEtypes_CapInfo_t), sizeof(IEEEtypes_CapInfo_t)));
+        bss_new_entry->multi_bssid_ap = MULTI_BSSID_SUB_AP;
+#if CONFIG_WPA_SUPP
+        if (pmadapter->wpa_supp_scan_triggered == MTRUE)
+        {
+            wifi_d("Alloc ies for Multi BSS. ies_len=%d", bss_new_entry->beacon_buf_size);
+            bss_new_entry->ies = (u8 *)OSA_MemoryAllocate(bss_new_entry->beacon_buf_size - BEACON_FIX_SIZE);
+            if (bss_new_entry->ies == MNULL)
+            {
+                wifi_d("Failed to alloc memory for Multi BSS ies");
+                goto done;
+            }
+            (void)__memcpy(pmadapter, bss_new_entry->ies, bss_new_entry->pbeacon_buf + BEACON_FIX_SIZE,
+                           bss_new_entry->beacon_buf_size - BEACON_FIX_SIZE);
+            bss_new_entry->ies_len = bss_new_entry->beacon_buf_size;
+        }
+#endif
+        /*add to scan table*/
+        /*
+         * Search the scan table for the same bssid
+         */
+        for (bss_idx = 0; bss_idx < num_in_tbl; bss_idx++)
+        {
+            if (!__memcmp(pmadapter, bss_new_entry->mac_address, pmadapter->pscan_table[bss_idx].mac_address,
+                          sizeof(bss_new_entry->mac_address)))
+            {
+                /*
+                 * If the SSID matches as well, it is a duplicate of
+                 *   this entry.  Keep the bss_idx set to this
+                 *   entry so we replace the old contents in the table
+                 */
+                if ((bss_new_entry->ssid.ssid_len == pmadapter->pscan_table[bss_idx].ssid.ssid_len) &&
+                    (!__memcmp(pmadapter, bss_new_entry->ssid.ssid, pmadapter->pscan_table[bss_idx].ssid.ssid,
+                               bss_new_entry->ssid.ssid_len)))
+                {
+                    PRINTM(MINFO, "SCAN_RESP: Duplicate of index: %d\n", bss_idx);
+                    break;
+                }
+            }
+        }
+        if (bss_idx == num_in_tbl)
+        {
+            /* Range check the bss_idx, keep it limited to the last entry */
+            if (bss_idx == MRVDRV_MAX_BSSID_LIST)
+            {
+                lowest_rssi_index = wlan_find_worst_network_in_list(pmadapter->pscan_table, MRVDRV_MAX_BSSID_LIST);
+            }
+            else
+            {
+                num_in_tbl++;
+            }
+        }
+
+        if (bss_idx == MRVDRV_MAX_BSSID_LIST)
+        {
+            if (pmadapter->pscan_table[lowest_rssi_index].rssi > bss_new_entry->rssi)
+            {
+#if CONFIG_WPA_SUPP
+                if (pmadapter->pscan_table[lowest_rssi_index].ies != NULL)
+                {
+                    OSA_MemoryFree(pmadapter->pscan_table[lowest_rssi_index].ies);
+                    pmadapter->pscan_table[lowest_rssi_index].ies = NULL;
+                }
+#endif
+                (void)__memcpy(pmadapter, &pmadapter->pscan_table[lowest_rssi_index], bss_new_entry,
+                               sizeof(pmadapter->pscan_table[lowest_rssi_index]));
+                adjust_pointers_to_internal_buffers(&pmadapter->pscan_table[lowest_rssi_index], bss_new_entry);
+            }
+#if CONFIG_WPA_SUPP
+            /* If the scan table is full, free ies of the new entry with lowest rssi, which won't be added into table */
+            else
+            {
+                if (bss_new_entry->ies != NULL)
+                {
+                    OSA_MemoryFree(bss_new_entry->ies);
+                    bss_new_entry->ies = NULL;
+                }
+            }
+#endif
+        }
+        else
+        {
+            /* Copy the locally created bss_new_entry to the scan table */
+#if CONFIG_WPA_SUPP
+            if (pmadapter->pscan_table[bss_idx].ies != NULL)
+            {
+                OSA_MemoryFree(pmadapter->pscan_table[bss_idx].ies);
+                pmadapter->pscan_table[bss_idx].ies = NULL;
+            }
+#endif
+            (void)__memcpy(pmadapter, &pmadapter->pscan_table[bss_idx], bss_new_entry,
+                           sizeof(pmadapter->pscan_table[bss_idx]));
+            adjust_pointers_to_internal_buffers(&pmadapter->pscan_table[bss_idx], bss_new_entry);
+        }
+#if CONFIG_WPA_SUPP
+        if (pssid && pbeacon_buf)
+            pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pbeacon_buf);
+#endif
+#if !CONFIG_MEM_POOLS
+        pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)bss_new_entry);
+#endif
+    }
+done:
+    *num_in_table = num_in_tbl;
+    LEAVE();
+    return;
+}
+
+/**
+ *  @brief This function parse the multi_bssid IE from pbss_entry
+ *
+ *  @param pmpriv        A pointer to mlan_private structure
+ *  @param pbss_entry       A pointer to BSSDescriptor_t which has multi-bssid
+ * IE
+ *  @param num_in_table     A pointer to buffer to save num of entry in scan
+ * table.
+ *
+ *  @return                 number entry in scan table
+ */
+static t_void wlan_parse_multi_bssid_ie(mlan_private *pmpriv,
+                                        BSSDescriptor_t *pbss_entry,
+                                        IEEEtypes_MultiBSSID_t *pmulti_bssid,
+                                        t_u32 *num_in_table)
+{
+    t_u32 bytes_left                                 = 0;
+    t_u8 *pcurrent_ptr                               = MNULL;
+    IEEEtypes_NonTransBSSIDProfile_t *pbssid_profile = MNULL;
+
+    if (!pmulti_bssid)
+        return;
+    bytes_left   = pmulti_bssid->ieee_hdr.len - 1;
+    pcurrent_ptr = pmulti_bssid->sub_elem_data;
+    while (bytes_left >= 2)
+    {
+        pbssid_profile = (IEEEtypes_NonTransBSSIDProfile_t *)pcurrent_ptr;
+        if (pbssid_profile->ieee_hdr.element_id != NONTRANS_BSSID_PROFILE_SUBELEM_ID)
+        {
+            PRINTM(MERROR, "Invalid multi-bssid IE\n");
+            break;
+        }
+        if (bytes_left < (t_u32)(pbssid_profile->ieee_hdr.len + 2))
+        {
+            PRINTM(MERROR, "Invalid multi-bssid IE\n");
+            break;
+        }
+        wlan_parse_non_trans_bssid_profile(pmpriv, pbss_entry, pbssid_profile, num_in_table,
+                                           pmulti_bssid->max_bssid_indicator);
+        pcurrent_ptr += pbssid_profile->ieee_hdr.len + 2;
+        bytes_left -= pbssid_profile->ieee_hdr.len + 2;
+    }
+    return;
+}
+
+/**
+ *  @brief This function search all the mbssid IE in the beacon buffer
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param pbss_entry       A pointer to BSSDescriptor_t which has multi-bssid
+ * IE
+ *  @param num_in_table     A pointer to buffer to save num of entry in scan
+ * table.
+ *
+ *  @return                 N/A
+ */
+static void wlan_parse_multi_bssid_ap(mlan_private *pmpriv, BSSDescriptor_t *pbss_entry, t_u32 *num_in_table)
+{
+    IEEEtypes_ElementId_e element_id;
+    t_u8 element_len;
+    t_u16 total_ie_len;
+    t_u32 bytes_left        = pbss_entry->beacon_buf_size - BEACON_FIX_SIZE;
+    t_u8 *pcurrent_ptr      = pbss_entry->pbeacon_buf + BEACON_FIX_SIZE;
+    IEEEtypes_Ssid_t *pssid = (IEEEtypes_Ssid_t *)pcurrent_ptr;
+
+    if (pssid->element_id != SSID)
+    {
+        PRINTM(MERROR, "Invalid beacon ie, ssid should be in the first element\n");
+        return;
+    }
+    /* Process variable IE */
+    while (bytes_left >= 2)
+    {
+        element_id   = (IEEEtypes_ElementId_e)(*((t_u8 *)pcurrent_ptr));
+        element_len  = *((t_u8 *)pcurrent_ptr + 1);
+        total_ie_len = element_len + sizeof(IEEEtypes_Header_t);
+
+        if (bytes_left < total_ie_len)
+        {
+            PRINTM(MERROR,
+                   "InterpretIE: Error in processing IE, "
+                   "bytes left < IE length\n");
+            bytes_left = 0;
+            continue;
+        }
+        if (element_id == MULTI_BSSID)
+            wlan_parse_multi_bssid_ie(pmpriv, pbss_entry, (IEEEtypes_MultiBSSID_t *)pcurrent_ptr, num_in_table);
+        pcurrent_ptr += total_ie_len;
+        bytes_left -= total_ie_len;
+    }
+    return;
+}
+
+/**
+ *  @brief This function parse and store the extended scan results
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param number_of_sets   Number of BSS
+ *  @param pscan_resp       A pointer to scan response buffer
+ *  @param scan_resp_size   Size of scan response buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_parse_ext_scan_result(IN mlan_private *pmpriv,
+                                              IN t_u8 number_of_sets,
+                                              IN t_u8 *pscan_resp,
+                                              IN t_u16 scan_resp_size)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = pmpriv->adapter;
+#if !CONFIG_MEM_POOLS
+    mlan_callbacks *pcb = MNULL;
+#endif
+    BSSDescriptor_t *bss_new_entry = MNULL;
+    t_u8 *pbss_info;
+    t_u32 bytes_left;
+    t_u32 bytes_left_for_tlv;
+    t_u32 num_in_table;
+    t_u32 bss_idx;
+    t_u32 idx;
+    t_u32 idx2;
+    t_u64 tsf_val;
+    const chan_freq_power_t *cfp;
+    t_u16 tlv_type, tlv_len;
+    MrvlIEtypes_Data_t *ptlv                    = MNULL;
+    MrvlIEtypes_Bss_Scan_Rsp_t *pscan_rsp_tlv   = MNULL;
+    MrvlIEtypes_Bss_Scan_Info_t *pscan_info_tlv = MNULL;
+    t_u16 band;
+    /* t_u32 age_ts_usec; */
+    t_u32 lowest_rssi_index              = 0;
+    t_u8 null_ssid[MLAN_MAX_SSID_LENGTH] = {0};
+
+    ENTER();
+
+#if !CONFIG_MEM_POOLS
+    pcb = (pmlan_callbacks)&pmadapter->callbacks;
+#endif
+
+
+    bytes_left = scan_resp_size;
+    PRINTM(MINFO, "EXT_SCAN: bss_descript_size %d\n", scan_resp_size);
+    PRINTM(MINFO, "EXT_SCAN: returned %d APs before parsing\n", number_of_sets);
+
+    if ((number_of_sets == 0U) && (bytes_left == 0U))
+    {
+        wscan_d("SCAN_RESP: number of sets are zero");
+        goto done;
+    }
+
+    num_in_table = pmadapter->num_in_scan_table;
+    ptlv         = (MrvlIEtypes_Data_t *)pscan_resp;
+
+    /*
+     *  Process each scan response returned number_of_sets. Save
+     *    the information in the bss_new_entry and then insert into the
+     *    driver scan table either as an update to an existing entry
+     *    or as an addition at the end of the table
+     */
+#if !CONFIG_MEM_POOLS
+    ret = pcb->moal_malloc(pmadapter->pmoal_handle, sizeof(BSSDescriptor_t), MLAN_MEM_DEF, (t_u8 **)&bss_new_entry);
+
+    if (ret != MLAN_STATUS_SUCCESS || !bss_new_entry)
+    {
+        PRINTM(MERROR, "Memory allocation for bss_new_entry failed!\n");
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+#else
+    bss_new_entry = &s_bss_new_entry;
+#endif
+
+    for (idx = 0; idx < number_of_sets && bytes_left > sizeof(MrvlIEtypesHeader_t); idx++)
+    {
+        tlv_type = wlan_le16_to_cpu(ptlv->header.type);
+        tlv_len  = wlan_le16_to_cpu(ptlv->header.len);
+        if (bytes_left < sizeof(MrvlIEtypesHeader_t) + tlv_len)
+        {
+            PRINTM(MERROR, "EXT_SCAN: Error bytes left < TLV length\n");
+            break;
+        }
+        pscan_rsp_tlv      = MNULL;
+        pscan_info_tlv     = MNULL;
+        bytes_left_for_tlv = bytes_left;
+        /* BSS response TLV with beacon or probe response buffer at the initial
+           position of each descriptor */
+        if (tlv_type == TLV_TYPE_BSS_SCAN_RSP)
+        {
+            pbss_info     = (t_u8 *)ptlv;
+            pscan_rsp_tlv = (MrvlIEtypes_Bss_Scan_Rsp_t *)ptlv;
+            ptlv          = (MrvlIEtypes_Data_t *)(ptlv->data + tlv_len);
+            bytes_left_for_tlv -= (tlv_len + sizeof(MrvlIEtypesHeader_t));
+        }
+        else
+            break;
+
+        /* Process variable TLV */
+        // coverity[sensitive_memory_access:SUPPRESS]
+        while (bytes_left_for_tlv >= sizeof(MrvlIEtypesHeader_t) &&
+               wlan_le16_to_cpu(ptlv->header.type) != TLV_TYPE_BSS_SCAN_RSP)
+        {
+            /* Barriers are normally not required but do ensure the code is
+             * completely within the specified behaviour for the architecture. */
+            __asm volatile("dsb" ::: "memory");
+            __asm volatile("isb");
+            tlv_type = wlan_le16_to_cpu(ptlv->header.type);
+            tlv_len  = wlan_le16_to_cpu(ptlv->header.len);
+            if (bytes_left_for_tlv < sizeof(MrvlIEtypesHeader_t) + tlv_len)
+            {
+                PRINTM(MERROR,
+                       "EXT_SCAN: Error in processing TLV, "
+                       "bytes left < TLV length\n");
+                pscan_rsp_tlv      = MNULL;
+                bytes_left_for_tlv = 0;
+                continue;
+            }
+            switch (tlv_type)
+            {
+                case TLV_TYPE_BSS_SCAN_INFO:
+                    pscan_info_tlv = (MrvlIEtypes_Bss_Scan_Info_t *)ptlv;
+                    if (tlv_len != sizeof(MrvlIEtypes_Bss_Scan_Info_t) - sizeof(MrvlIEtypesHeader_t))
+                    {
+                        bytes_left_for_tlv = 0;
+                        continue;
+                    }
+                    break;
+                default:
+                    PRINTM(MINFO, "Unexpected tlv in scan result\n");
+                    break;
+            }
+            ptlv = (MrvlIEtypes_Data_t *)(ptlv->data + tlv_len);
+            bytes_left -= (tlv_len + sizeof(MrvlIEtypesHeader_t));
+            bytes_left_for_tlv -= (tlv_len + sizeof(MrvlIEtypesHeader_t));
+        }
+        /* No BSS response TLV */
+        if (pscan_rsp_tlv == MNULL)
+            break;
+
+        /* Advance pointer to the beacon buffer length and update the bytes
+           count so that the function wlan_interpret_bss_desc_with_ie() can
+           handle the scan buffer withut any change */
+        pbss_info += sizeof(t_u16);
+        bytes_left -= sizeof(t_u16);
+
+        /* Zero out the bss_new_entry we are about to store info in */
+        (void)__memset(pmadapter, bss_new_entry, 0x00, sizeof(BSSDescriptor_t));
+
+        /* Process the data fields and IEs returned for this BSS */
+        if (wlan_interpret_bss_desc_with_ie(pmadapter, bss_new_entry, &pbss_info, &bytes_left, MTRUE) ==
+            MLAN_STATUS_SUCCESS)
+        {
+            PRINTM(MINFO, "EXT_SCAN: BSSID = %02x:%02x:%02x:%02x:%02x:%02x\n", bss_new_entry->mac_address[0],
+                   bss_new_entry->mac_address[1], bss_new_entry->mac_address[2], bss_new_entry->mac_address[3],
+                   bss_new_entry->mac_address[4], bss_new_entry->mac_address[5]);
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+            if (pmpriv->wps.session_enable == MTRUE)
+            {
+                if ((bss_new_entry->wps_IE_exist == MFALSE) || (bss_new_entry->wps_session == 0xffff))
+                {
+                    if (bss_new_entry->ies != NULL)
+                    {
+                        OSA_MemoryFree(bss_new_entry->ies);
+                        bss_new_entry->ies = NULL;
+                    }
+                    continue;
+                }
+            }
+#endif /* CONFIG_WPA_SUPP_WPS */
+#endif
+
+            band = BAND_G;
+            /*
+             * If the BSS info TLV was appended to the scan results, save
+             *   this entry's TSF value in the networkTSF field. The
+             *   networkTSF is the firmware's TSF value at the time the
+             *   beacon or probe response was received.
+             */
+            if (pscan_info_tlv)
+            {
+                /* RSSI is 2 byte long */
+                bss_new_entry->rssi = -(t_s32)(wlan_le16_to_cpu(pscan_info_tlv->rssi));
+#if 0
+                if(bss_new_entry->rssi > 0x7f)
+                    bss_new_entry->rssi = - (256 - bss_new_entry->rssi);
+#endif
+                PRINTM(MINFO, "EXT_SCAN: RSSI=%d\n", bss_new_entry->rssi);
+                (void)__memcpy(pmpriv->adapter, &tsf_val, &pscan_info_tlv->tsf, sizeof(tsf_val));
+                tsf_val = wlan_le64_to_cpu(tsf_val);
+                (void)__memcpy(pmpriv->adapter, &bss_new_entry->network_tsf, &tsf_val,
+                               sizeof(bss_new_entry->network_tsf));
+                band = radio_type_to_band(pscan_info_tlv->band);
+                if (bss_new_entry->channel == 0)
+                    bss_new_entry->channel = pscan_info_tlv->channel;
+            }
+            /* Save the band designation for this entry for use in join */
+            bss_new_entry->bss_band = band;
+            cfp = wlan_find_cfp_by_band_and_channel(pmadapter, bss_new_entry->bss_band, (t_u16)bss_new_entry->channel);
+
+            if (cfp)
+                bss_new_entry->freq = cfp->freq;
+            else
+                bss_new_entry->freq = 0;
+            if (IS_FW_SUPPORT_MULTIBSSID(pmadapter))
+            {
+                if (bss_new_entry->multi_bssid_ap == MULTI_BSSID_AP)
+                    wlan_parse_multi_bssid_ap(pmpriv, bss_new_entry, &num_in_table);
+            }
+
+            if (pmpriv->ssid_filter)
+            {
+                for (idx2 = 0; idx2 < NELEMENTS(pmpriv->filter_ssid); idx2 ++)
+                {
+                    if (pmpriv->filter_ssid[idx2].ssid_len && (bss_new_entry->ssid.ssid_len == pmpriv->filter_ssid[idx2].ssid_len)
+                       && (!__memcmp(pmadapter, bss_new_entry->ssid.ssid, pmpriv->filter_ssid[idx2].ssid, bss_new_entry->ssid.ssid_len)))
+                    {
+                        break;
+                    }
+                }
+
+                if (idx2 == NELEMENTS(pmpriv->filter_ssid))
+                {
+#if CONFIG_WPA_SUPP
+                    if (bss_new_entry->ies != NULL)
+                    {
+                        OSA_MemoryFree(bss_new_entry->ies);
+                        bss_new_entry->ies = NULL;
+                    }
+#endif
+                    continue;
+                }
+            }
+
+            /*
+             * Search the scan table for the same bssid
+             */
+            for (bss_idx = 0; bss_idx < num_in_table; bss_idx++)
+            {
+                if (!__memcmp(pmadapter, bss_new_entry->mac_address, pmadapter->pscan_table[bss_idx].mac_address,
+                              sizeof(bss_new_entry->mac_address)))
+                {
+                    /*
+                     * If the SSID matches as well, it is a duplicate of
+                     *   this entry.  Keep the bss_idx set to this
+                     *   entry so we replace the old contents in the table
+                     */
+                    if ((bss_new_entry->ssid.ssid_len == pmadapter->pscan_table[bss_idx].ssid.ssid_len) &&
+                        (!__memcmp(pmadapter, bss_new_entry->ssid.ssid, pmadapter->pscan_table[bss_idx].ssid.ssid,
+                                   bss_new_entry->ssid.ssid_len)))
+                    {
+                        PRINTM(MINFO, "EXT_SCAN: Duplicate of index: %d\n", bss_idx);
+                        break;
+                    }
+                    /*
+                     * If the SSID is NULL for same BSSID
+                     * keep the bss_idx set to this entry
+                     * so we replace the old contents in
+                     * the table
+                     */
+                    if (!__memcmp(pmadapter, pmadapter->pscan_table[bss_idx].ssid.ssid, null_ssid,
+                                  pmadapter->pscan_table[bss_idx].ssid.ssid_len))
+                    {
+                        PRINTM(MINFO, "SCAN_RESP: Duplicate of index: %d\n", bss_idx);
+                        break;
+                    }
+                }
+            }
+            /*
+             * If the bss_idx is equal to the number of entries in the table,
+             *   the new entry was not a duplicate; append it to the scan
+             *   table
+             */
+            if (bss_idx == num_in_table)
+            {
+                /* Range check the bss_idx, keep it limited to the last entry */
+                if (bss_idx == MRVDRV_MAX_BSSID_LIST)
+                {
+                    lowest_rssi_index = wlan_find_worst_network_in_list(pmadapter->pscan_table, MRVDRV_MAX_BSSID_LIST);
+                }
+                else
+                {
+                    num_in_table++;
+                }
+            }
+            else
+            {
+                if ((bss_new_entry->channel != pmadapter->pscan_table[bss_idx].channel) &&
+                    (bss_new_entry->rssi > pmadapter->pscan_table[bss_idx].rssi))
+                {
+                    PRINTM(MCMND, "skip update the duplicate entry with low rssi\n");
+#if CONFIG_WPA_SUPP
+                    if (bss_new_entry->ies != NULL)
+                    {
+                        OSA_MemoryFree(bss_new_entry->ies);
+                        bss_new_entry->ies = NULL;
+                    }
+#endif
+                    continue;
+                }
+            }
+
+            if (bss_idx == MRVDRV_MAX_BSSID_LIST)
+            {
+                if (pmadapter->pscan_table[lowest_rssi_index].rssi > bss_new_entry->rssi)
+                {
+#if CONFIG_WPA_SUPP
+                    if (pmadapter->pscan_table[lowest_rssi_index].ies != NULL)
+                    {
+                        OSA_MemoryFree(pmadapter->pscan_table[lowest_rssi_index].ies);
+                        pmadapter->pscan_table[lowest_rssi_index].ies = NULL;
+                    }
+#endif
+                    (void)__memcpy(pmadapter, &pmadapter->pscan_table[lowest_rssi_index], bss_new_entry,
+                                   sizeof(pmadapter->pscan_table[lowest_rssi_index]));
+                    adjust_pointers_to_internal_buffers(&pmadapter->pscan_table[lowest_rssi_index], bss_new_entry);
+                }
+#if CONFIG_WPA_SUPP
+                /* If the scan table is full, free ies of the new entry with lowest rssi, which won't be added into
+                 * table */
+                else
+                {
+                    if (bss_new_entry->ies != NULL)
+                    {
+                        OSA_MemoryFree(bss_new_entry->ies);
+                        bss_new_entry->ies = NULL;
+                    }
+                }
+#endif
+            }
+            else
+            {
+                /* Copy the locally created bss_new_entry to the scan table */
+#if CONFIG_WPA_SUPP
+                if (pmadapter->pscan_table[bss_idx].ies != NULL)
+                {
+                    OSA_MemoryFree(pmadapter->pscan_table[bss_idx].ies);
+                    pmadapter->pscan_table[bss_idx].ies = NULL;
+                }
+#endif
+                (void)__memcpy(pmadapter, &pmadapter->pscan_table[bss_idx], bss_new_entry,
+                               sizeof(pmadapter->pscan_table[bss_idx]));
+                adjust_pointers_to_internal_buffers(&pmadapter->pscan_table[bss_idx], bss_new_entry);
+            }
+        }
+        else
+        {
+            /* Error parsing/interpreting the scan response, skipped */
+            PRINTM(MERROR, "EXT_SCAN: wlan_interpret_bss_desc_with_ie returned error\n");
+#if CONFIG_WPA_SUPP
+            if (bss_new_entry->ies != NULL)
+            {
+                OSA_MemoryFree(bss_new_entry->ies);
+                bss_new_entry->ies = NULL;
+            }
+#endif
+        }
+    }
+
+    PRINTM(MINFO, "EXT_SCAN: Scanned %2d APs, %d valid, %d total\n", number_of_sets,
+           num_in_table - pmadapter->num_in_scan_table, num_in_table);
+
+    /* Update the total number of BSSIDs in the scan table */
+    pmadapter->num_in_scan_table = num_in_table;
+    /* fixme: the following code does not seem relevant */
+done:
+#if !CONFIG_MEM_POOLS
+    if (bss_new_entry)
+    {
+        pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)bss_new_entry);
+    }
+#endif
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function handles the event extended scan report
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pmbuf        A pointer to mlan_buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_handle_event_ext_scan_report(IN mlan_private *pmpriv, IN t_u8 *pmbuf)
+{
+    /* mlan_adapter *pmadapter = pmpriv->adapter;
+    mlan_callbacks *pcb = &pmadapter->callbacks;
+    mlan_ioctl_req *pioctl_req = MNULL;
+    cmd_ctrl_node *pcmd_node = MNULL; */
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+
+    mlan_event_scan_result *pevent_scan = (pmlan_event_scan_result)(pmbuf);
+    t_u8 *ptlv                          = (pmbuf + sizeof(mlan_event_scan_result));
+    t_u16 tlv_buf_left                  = wlan_cpu_to_le16(pevent_scan->buf_size);
+
+    ret = wlan_parse_ext_scan_result(pmpriv, pevent_scan->num_of_set, ptlv, tlv_buf_left);
+
+#if 0
+    if (!pevent_scan->more_event) {
+        pioctl_req = pmadapter->pext_scan_ioctl_req;
+        if (!util_peek_list(pmadapter->pmoal_handle,
+                            &pmadapter->scan_pending_q, pcb->moal_spin_lock,
+                            pcb->moal_spin_unlock)) {
+            pmadapter->pext_scan_ioctl_req = MNULL;
+            wlan_request_cmd_lock(pmadapter);
+            pmadapter->scan_processing = MFALSE;
+            wlan_release_cmd_lock(pmadapter);
+            /*
+             * Process the resulting scan table:
+             *   - Remove any bad ssids
+             *   - Update our current BSS information from scan data
+             */
+            wlan_scan_process_results(pmpriv);
+
+            /* Need to indicate IOCTL complete */
+            if (pioctl_req != MNULL) {
+                pioctl_req->status_code = MLAN_ERROR_NO_ERROR;
+                /* Indicate ioctl complete */
+                pcb->moal_ioctl_complete(pmadapter->pmoal_handle,
+                                         (pmlan_ioctl_req) pioctl_req,
+                                         MLAN_STATUS_SUCCESS);
+            }
+            wlan_recv_event(pmpriv, MLAN_EVENT_ID_DRV_SCAN_REPORT, MNULL);
+        } else {
+            /* If firmware not ready, do not issue any more scan commands */
+            if (pmadapter->hw_status != WlanHardwareStatusReady) {
+                /* Flush all pending scan commands */
+                wlan_flush_scan_queue(pmadapter);
+                /* Indicate IOCTL complete */
+                if (pioctl_req != MNULL) {
+                    pioctl_req->status_code = MLAN_ERROR_FW_NOT_READY;
+
+                    /* Indicate ioctl complete */
+                    pcb->moal_ioctl_complete(pmadapter->pmoal_handle,
+                                             (pmlan_ioctl_req) pioctl_req,
+                                             MLAN_STATUS_FAILURE);
+                }
+            } else {
+                /* Get scan command from scan_pending_q and put to
+                   cmd_pending_q */
+                pcmd_node =
+                    (cmd_ctrl_node *) util_dequeue_list(pmadapter->pmoal_handle,
+                                                        &pmadapter->
+                                                        scan_pending_q,
+                                                        pcb->moal_spin_lock,
+                                                        pcb->moal_spin_unlock);
+                wlan_insert_cmd_to_pending_q(pmadapter, pcmd_node, MTRUE);
+            }
+        }
+    }
+#endif
+    LEAVE();
+    return ret;
+}
+#endif /* CONFIG_EXT_SCAN_SUPPORT */
+
+/**
+ *  @brief This function prepares command of bg_scan_query.
+ *
+ *  @param pmpriv     A pointer to mlan_private structure
+ *  @param pcmd       A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf  Void pointer cast of a wlan_scan_cmd_config struct used
+ *                    to set the fields/TLVs for the command sent to firmware
+ *
+ *  @return           MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_802_11_bg_scan_query(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *pcmd, IN t_u16 cmd_action)
+{
+    HostCmd_DS_802_11_BG_SCAN_QUERY *bg_query = &pcmd->params.bg_scan_query;
+
+    ENTER();
+
+    pcmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_BG_SCAN_QUERY);
+    pcmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_BG_SCAN_QUERY) + S_DS_GEN);
+
+    bg_query->flush = MTRUE;
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Create a channel list for the driver to scan based on region info
+ *
+ *  Use the driver region/band information to construct a comprehensive list
+ *    of channels to scan.  This routine is used for any scan that is not
+ *    provided a specific channel list to scan.
+ *
+ *  @param pmpriv           A pointer to mlan_private structure
+ *  @param pbg_scan_in      pointer to scan configuration parameters
+ *  @param tlv_chan_list    A pointer to structure MrvlIEtypes_ChanListParamSet_t
+ *
+ *  @return                 channel number
+ */
+static t_u8 wlan_bgscan_create_channel_list(IN mlan_private *pmpriv,
+                                            IN const wlan_bgscan_cfg *pbg_scan_in,
+                                            MrvlIEtypes_ChanListParamSet_t *tlv_chan_list)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    region_chan_t *pscan_region;
+    const chan_freq_power_t *cfp;
+    t_u32 region_idx;
+    t_u32 chan_idx = 0;
+    t_u32 next_chan;
+    t_u8 scan_type;
+    t_u8 radio_type;
+
+    ENTER();
+
+    for (region_idx = 0; region_idx < NELEMENTS(pmadapter->region_channel); region_idx++)
+    {
+        if (wlan_11d_is_enabled(pmpriv) && pmpriv->media_connected != MTRUE)
+        {
+            /* Scan all the supported chan for the first scan */
+            if (!pmadapter->universal_channel[region_idx].valid)
+                continue;
+            pscan_region = &pmadapter->universal_channel[region_idx];
+        }
+        else
+        {
+            if (!pmadapter->region_channel[region_idx].valid)
+                continue;
+            pscan_region = &pmadapter->region_channel[region_idx];
+        }
+
+        if (pbg_scan_in && !pbg_scan_in->chan_list[0].chan_number &&
+            pbg_scan_in->chan_list[0].radio_type & BAND_SPECIFIED)
+        {
+            radio_type = pbg_scan_in->chan_list[0].radio_type & ~BAND_SPECIFIED;
+            if (!radio_type && (pscan_region->band != BAND_B) && (pscan_region->band != BAND_G))
+                continue;
+            if (radio_type && (pscan_region->band != BAND_A))
+                continue;
+        }
+        if (!wlan_is_band_compatible(pmpriv->config_bands | pmadapter->adhoc_start_band, pscan_region->band))
+            continue;
+        for (next_chan = 0; next_chan < pscan_region->num_cfp; next_chan++, chan_idx++)
+        {
+            if (chan_idx >= WLAN_BG_SCAN_CHAN_MAX)
+                break;
+            /* Set the default scan type to ACTIVE SCAN type, will later be
+               changed to passive on a per channel basis if restricted by
+               regulatory requirements (11d or 11h) */
+            scan_type = MLAN_SCAN_TYPE_ACTIVE;
+            cfp       = pscan_region->pcfp + next_chan;
+            if (scan_type == MLAN_SCAN_TYPE_ACTIVE && wlan_11d_support_is_enabled(pmpriv))
+            {
+                scan_type = wlan_11d_get_scan_type(pmpriv, pscan_region->band, (t_u8)cfp->channel,
+                                                   &pmadapter->parsed_region_chan);
+            }
+            switch (pscan_region->band)
+            {
+#if CONFIG_5GHz_SUPPORT
+                case BAND_A:
+                    tlv_chan_list->chan_scan_param[chan_idx].radio_type = HostCmd_SCAN_RADIO_TYPE_A;
+                    if (!wlan_11d_is_enabled(pmpriv))
+                    {
+                        /* 11D not available... play it safe on DFS channels */
+                        if (wlan_11h_radar_detect_required(pmpriv, (t_u8)cfp->channel))
+                            scan_type = MLAN_SCAN_TYPE_PASSIVE;
+                    }
+                    break;
+#endif
+                case BAND_B:
+                case BAND_G:
+                    if (wlan_bg_scan_type_is_passive(pmpriv, (t_u8)cfp->channel))
+                        scan_type = MLAN_SCAN_TYPE_PASSIVE;
+                default:
+                    tlv_chan_list->chan_scan_param[chan_idx].radio_type = HostCmd_SCAN_RADIO_TYPE_BG;
+                    break;
+            }
+
+            if (pbg_scan_in && pbg_scan_in->chan_list[0].scan_time)
+            {
+                tlv_chan_list->chan_scan_param[chan_idx].max_scan_time =
+                    wlan_cpu_to_le16((t_u16)pbg_scan_in->chan_list[0].scan_time);
+                tlv_chan_list->chan_scan_param[chan_idx].min_scan_time =
+                    wlan_cpu_to_le16((t_u16)pbg_scan_in->chan_list[0].scan_time);
+            }
+            else if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+            {
+                tlv_chan_list->chan_scan_param[chan_idx].max_scan_time = wlan_cpu_to_le16(pmadapter->passive_scan_time);
+                tlv_chan_list->chan_scan_param[chan_idx].min_scan_time = wlan_cpu_to_le16(pmadapter->passive_scan_time);
+            }
+            else
+            {
+                tlv_chan_list->chan_scan_param[chan_idx].max_scan_time =
+                    wlan_cpu_to_le16(pmadapter->specific_scan_time);
+                tlv_chan_list->chan_scan_param[chan_idx].min_scan_time =
+                    wlan_cpu_to_le16(pmadapter->specific_scan_time);
+            }
+
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+            {
+                tlv_chan_list->chan_scan_param[chan_idx].chan_scan_mode.passive_scan = MTRUE;
+            }
+            else
+            {
+                tlv_chan_list->chan_scan_param[chan_idx].chan_scan_mode.passive_scan = MFALSE;
+            }
+
+            tlv_chan_list->chan_scan_param[chan_idx].chan_number = (t_u8)cfp->channel;
+        }
+    }
+
+    LEAVE();
+    return chan_idx;
+}
+/**
+ *  @brief This function prepares command of bg_scan_config
+ *
+ *  @param pmpriv     A pointer to mlan_private structure
+ *  @param pcmd       A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf  Void pointer cast of a wlan_scan_cmd_config struct used
+ *                    to set the fields/TLVs for the command sent to firmware
+ *
+ *  @return           MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_bgscan_config(IN mlan_private *pmpriv,
+                                   IN HostCmd_DS_COMMAND *pcmd,
+                                   IN t_u16 cmd_action,
+                                   IN t_void *pdata_buf)
+{
+    mlan_adapter *pmadapter                                = pmpriv->adapter;
+    HostCmd_DS_802_11_BG_SCAN_CONFIG *bg_scan              = &pcmd->params.bg_scan_config;
+    wlan_bgscan_cfg *bg_scan_in                            = (wlan_bgscan_cfg *)pdata_buf;
+    t_u16 cmd_size                                         = 0;
+    MrvlIEtypes_NumProbes_t *pnum_probes_tlv               = MNULL;
+    MrvlIEtypes_BeaconLowRssiThreshold_t *rssi_tlv         = MNULL;
+    MrvlIEtypes_BeaconLowSnrThreshold_t *snr_tlv           = MNULL;
+    MrvlIEtypes_WildCardSsIdParamSet_t *pwildcard_ssid_tlv = MNULL;
+    MrvlIEtypes_ChanListParamSet_t *tlv_chan_list          = MNULL;
+    MrvlIEtypes_StartLater_t *tlv_start_later              = MNULL;
+    MrvlIEtypes_RepeatCount_t *tlv_repeat                  = MNULL;
+    MrvlIETypes_HTCap_t *pht_cap                           = MNULL;
+#if CONFIG_11AC
+    MrvlIETypes_VHTCap_t *pvht_cap = MNULL;
+#endif
+#if CONFIG_11AX
+    MrvlIEtypes_Extension_t *phe_cap = MNULL;
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+    MrvlIEtypes_ScanChanGap_t *pscan_gap_tlv;
+#endif
+    t_u8 *tlv        = MNULL;
+    t_u16 num_probes = 0;
+    t_u16 len        = 0;
+    t_u32 ssid_idx;
+    t_u32 ssid_len = 0;
+    t_u32 chan_idx;
+    t_u32 chan_num;
+    t_u8 radio_type;
+    t_u16 scan_dur;
+    t_u8 scan_type;
+    t_u8 max_bgscan_chan = 0;
+#if CONFIG_SCAN_CHANNEL_GAP
+    t_u16 scan_chan_gap = 0;
+#endif
+
+    ENTER();
+
+    max_bgscan_chan = WLAN_BG_SCAN_CHAN_MAX;
+
+#if CONFIG_UNII4_BAND_SUPPORT
+#if defined(SD9177)
+    max_bgscan_chan = WLAN_BG_SCAN_CHAN_MAX_UNII_4;
+#endif
+#endif
+
+    pcmd->command     = wlan_cpu_to_le16(HostCmd_CMD_802_11_BG_SCAN_CONFIG);
+    bg_scan->action   = wlan_cpu_to_le16(bg_scan_in->action);
+    bg_scan->enable   = bg_scan_in->enable;
+    bg_scan->bss_type = bg_scan_in->bss_type;
+    cmd_size          = sizeof(HostCmd_DS_802_11_BG_SCAN_CONFIG) + S_DS_GEN;
+    if (bg_scan_in->scan_interval)
+        bg_scan->scan_interval = wlan_cpu_to_le32(bg_scan_in->scan_interval);
+    else
+        bg_scan->scan_interval = wlan_cpu_to_le32(DEFAULT_BGSCAN_INTERVAL);
+    bg_scan->report_condition = wlan_cpu_to_le32(bg_scan_in->report_condition);
+
+    if ((bg_scan_in->action == BG_SCAN_ACT_GET)
+#if CONFIG_WMM_UAPSD
+        || (bg_scan_in->action == BG_SCAN_ACT_GET_PPS_UAPSD)
+#endif
+        || (!bg_scan->enable))
+        goto done;
+
+    tlv        = (t_u8 *)bg_scan + sizeof(HostCmd_DS_802_11_BG_SCAN_CONFIG);
+    num_probes = (bg_scan_in->num_probes ? bg_scan_in->num_probes : pmadapter->scan_probes);
+    if (num_probes)
+    {
+        pnum_probes_tlv = (MrvlIEtypes_NumProbes_t *)tlv;
+        // coverity[overrun-local:SUPPRESS]
+        // coverity[overrun-local:SUPPRESS]
+        pnum_probes_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_NUMPROBES);
+        pnum_probes_tlv->header.len  = wlan_cpu_to_le16(sizeof(pnum_probes_tlv->num_probes));
+        pnum_probes_tlv->num_probes  = wlan_cpu_to_le16((t_u16)num_probes);
+        tlv += sizeof(MrvlIEtypes_NumProbes_t);
+        cmd_size += sizeof(MrvlIEtypes_NumProbes_t);
+    }
+    if (bg_scan_in->rssi_threshold)
+    {
+        rssi_tlv              = (MrvlIEtypes_BeaconLowRssiThreshold_t *)tlv;
+        rssi_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_RSSI_LOW);
+        rssi_tlv->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        rssi_tlv->value     = bg_scan_in->rssi_threshold;
+        rssi_tlv->frequency = 0;
+        tlv += sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t);
+    }
+    if (bg_scan_in->snr_threshold)
+    {
+        snr_tlv              = (MrvlIEtypes_BeaconLowSnrThreshold_t *)tlv;
+        snr_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_SNR_LOW);
+        snr_tlv->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_BeaconLowSnrThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        snr_tlv->value     = bg_scan_in->snr_threshold;
+        snr_tlv->frequency = 0;
+        tlv += sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t);
+    }
+    if (bg_scan_in->repeat_count)
+    {
+        tlv_repeat               = (MrvlIEtypes_RepeatCount_t *)tlv;
+        tlv_repeat->header.type  = wlan_cpu_to_le16(TLV_TYPE_REPEAT_COUNT);
+        tlv_repeat->header.len   = wlan_cpu_to_le16(sizeof(MrvlIEtypes_RepeatCount_t) - sizeof(MrvlIEtypesHeader_t));
+        tlv_repeat->repeat_count = wlan_cpu_to_le16(bg_scan_in->repeat_count);
+        tlv += sizeof(MrvlIEtypes_RepeatCount_t);
+        cmd_size += sizeof(MrvlIEtypes_RepeatCount_t);
+    }
+#if CONFIG_SCAN_CHANNEL_GAP
+    scan_chan_gap = (bg_scan_in->scan_chan_gap ? bg_scan_in->scan_chan_gap : pmadapter->scan_chan_gap);
+    if (scan_chan_gap)
+    {
+        pscan_gap_tlv = (MrvlIEtypes_ScanChanGap_t *)tlv;
+        PRINTM(MCMND, "bgScan: channel gap = 0x%x\n", scan_chan_gap);
+        pscan_gap_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_SCAN_CHANNEL_GAP);
+        pscan_gap_tlv->header.len  = sizeof(pscan_gap_tlv->gap);
+        pscan_gap_tlv->gap         = wlan_cpu_to_le16((t_u16)scan_chan_gap);
+        /** indicate FW, gap is optional */
+        pscan_gap_tlv->gap |= GAP_FLAG_OPTIONAL;
+        tlv += sizeof(pscan_gap_tlv->header) + pscan_gap_tlv->header.len;
+        cmd_size += sizeof(MrvlIEtypes_ScanChanGap_t);
+    }
+#endif
+    for (ssid_idx = 0; ((ssid_idx < NELEMENTS(bg_scan_in->ssid_list)) &&
+                        (*bg_scan_in->ssid_list[ssid_idx].ssid || bg_scan_in->ssid_list[ssid_idx].max_len));
+         ssid_idx++)
+    {
+        ssid_len                            = wlan_strlen((t_s8 *)bg_scan_in->ssid_list[ssid_idx].ssid);
+        pwildcard_ssid_tlv                  = (MrvlIEtypes_WildCardSsIdParamSet_t *)tlv;
+        pwildcard_ssid_tlv->header.type     = wlan_cpu_to_le16(TLV_TYPE_WILDCARDSSID);
+        pwildcard_ssid_tlv->header.len      = (t_u16)(ssid_len + sizeof(pwildcard_ssid_tlv->max_ssid_length));
+        pwildcard_ssid_tlv->max_ssid_length = bg_scan_in->ssid_list[ssid_idx].max_len;
+
+        if (ssid_len != 0U)
+        {
+            (void)__memcpy(pmadapter, pwildcard_ssid_tlv->ssid, bg_scan_in->ssid_list[ssid_idx].ssid,
+                           MIN(MLAN_MAX_SSID_LENGTH, ssid_len));
+        }
+
+        tlv += sizeof(pwildcard_ssid_tlv->header) + pwildcard_ssid_tlv->header.len;
+        cmd_size += sizeof(pwildcard_ssid_tlv->header) + pwildcard_ssid_tlv->header.len;
+        pwildcard_ssid_tlv->header.len = wlan_cpu_to_le16(pwildcard_ssid_tlv->header.len);
+        PRINTM(MINFO, "Scan: ssid_list[%d]: %s, %d\n", ssid_idx, pwildcard_ssid_tlv->ssid,
+               pwildcard_ssid_tlv->max_ssid_length);
+    }
+    if (bg_scan_in->chan_list[0].chan_number)
+    {
+        tlv_chan_list = (MrvlIEtypes_ChanListParamSet_t *)tlv;
+        PRINTM(MINFO, "Scan: Using supplied channel list\n");
+        chan_num = 0;
+        for (chan_idx = 0; chan_idx < WLAN_BG_SCAN_CHAN_MAX && bg_scan_in->chan_list[chan_idx].chan_number; chan_idx++)
+        {
+            radio_type = bg_scan_in->chan_list[chan_idx].radio_type;
+            if (!wlan_is_band_compatible(pmpriv->config_bands | pmadapter->adhoc_start_band,
+                                         radio_type_to_band(radio_type)))
+                continue;
+            scan_type = bg_scan_in->chan_list[chan_idx].scan_type;
+            /* Prevent active scanning on a radar controlled channel */
+#if CONFIG_5GHz_SUPPORT
+            if (radio_type == HostCmd_SCAN_RADIO_TYPE_A)
+            {
+                if (wlan_11h_radar_detect_required(pmpriv, bg_scan_in->chan_list[chan_idx].chan_number))
+                {
+                    scan_type = MLAN_SCAN_TYPE_PASSIVE;
+                }
+            }
+#endif
+            if (radio_type == HostCmd_SCAN_RADIO_TYPE_BG)
+            {
+                if (wlan_bg_scan_type_is_passive(pmpriv, bg_scan_in->chan_list[chan_idx].chan_number))
+                {
+                    scan_type = MLAN_SCAN_TYPE_PASSIVE;
+                }
+            }
+            tlv_chan_list->chan_scan_param[chan_num].chan_number = bg_scan_in->chan_list[chan_idx].chan_number;
+            tlv_chan_list->chan_scan_param[chan_num].radio_type  = bg_scan_in->chan_list[chan_idx].radio_type;
+
+            if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+            {
+                tlv_chan_list->chan_scan_param[chan_num].chan_scan_mode.passive_scan = MTRUE;
+            }
+            else
+            {
+                tlv_chan_list->chan_scan_param[chan_num].chan_scan_mode.passive_scan = MFALSE;
+            }
+            if (bg_scan_in->chan_list[chan_idx].scan_time)
+            {
+                scan_dur = (t_u16)bg_scan_in->chan_list[chan_idx].scan_time;
+            }
+            else
+            {
+                if (scan_type == MLAN_SCAN_TYPE_PASSIVE)
+                {
+                    scan_dur = pmadapter->passive_scan_time;
+                }
+                else
+                {
+                    scan_dur = pmadapter->specific_scan_time;
+                }
+            }
+            tlv_chan_list->chan_scan_param[chan_num].min_scan_time = wlan_cpu_to_le16(scan_dur);
+            tlv_chan_list->chan_scan_param[chan_num].max_scan_time = wlan_cpu_to_le16(scan_dur);
+            chan_num++;
+        }
+        tlv_chan_list->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+        tlv_chan_list->header.len  = wlan_cpu_to_le16(sizeof(ChanScanParamSet_t) * chan_num);
+        tlv += sizeof(MrvlIEtypesHeader_t) + sizeof(ChanScanParamSet_t) * chan_num;
+        cmd_size += sizeof(MrvlIEtypesHeader_t) + sizeof(ChanScanParamSet_t) * chan_num;
+    }
+    else
+    {
+        tlv_chan_list              = (MrvlIEtypes_ChanListParamSet_t *)tlv;
+        chan_num                   = wlan_bgscan_create_channel_list(pmpriv, bg_scan_in, tlv_chan_list);
+        tlv_chan_list->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+        tlv_chan_list->header.len  = wlan_cpu_to_le16(sizeof(ChanScanParamSet_t) * chan_num);
+        tlv += sizeof(MrvlIEtypesHeader_t) + sizeof(ChanScanParamSet_t) * chan_num;
+        cmd_size += sizeof(MrvlIEtypesHeader_t) + sizeof(ChanScanParamSet_t) * chan_num;
+    }
+    if (bg_scan_in->chan_per_scan)
+    {
+        bg_scan->chan_per_scan = MIN(max_bgscan_chan, bg_scan_in->chan_per_scan);
+    }
+    else
+    {
+        if (bg_scan_in->report_condition & BG_SCAN_WAIT_ALL_CHAN_DONE)
+            bg_scan->chan_per_scan = chan_num;
+        else
+            bg_scan->chan_per_scan = MRVDRV_MAX_CHANNELS_PER_SPECIFIC_SCAN;
+    }
+    if (ISSUPP_11NENABLED(pmpriv->adapter->fw_cap_info) && (pmpriv->config_bands & BAND_GN
+#if CONFIG_5GHz_SUPPORT
+                                                            || pmpriv->config_bands & BAND_AN
+#endif
+                                                            ))
+    {
+        pht_cap = (MrvlIETypes_HTCap_t *)tlv;
+        (void)__memset(pmadapter, pht_cap, 0, sizeof(MrvlIETypes_HTCap_t));
+        pht_cap->header.type = wlan_cpu_to_le16(HT_CAPABILITY);
+        pht_cap->header.len  = sizeof(HTCap_t);
+        wlan_fill_ht_cap_tlv(pmpriv, pht_cap, pmpriv->config_bands);
+        DBG_HEXDUMP(MCMD_D, "BGSCAN: HT_CAPABILITIES IE", (t_u8 *)pht_cap, sizeof(MrvlIETypes_HTCap_t));
+        tlv += sizeof(MrvlIETypes_HTCap_t);
+        cmd_size += sizeof(MrvlIETypes_HTCap_t);
+        pht_cap->header.len = wlan_cpu_to_le16(pht_cap->header.len);
+    }
+#if CONFIG_11AC
+    if (ISSUPP_11ACENABLED(pmpriv->adapter->fw_cap_info) && (pmpriv->config_bands & BAND_AAC))
+    {
+        pvht_cap = (MrvlIETypes_VHTCap_t *)tlv;
+        (void)__memset(pmadapter, pvht_cap, 0, sizeof(MrvlIETypes_VHTCap_t));
+        pvht_cap->header.type = wlan_cpu_to_le16(VHT_CAPABILITY);
+        pvht_cap->header.len  = sizeof(VHT_capa_t);
+        wlan_fill_vht_cap_tlv(pmpriv, pvht_cap, pmpriv->config_bands, MFALSE);
+        DBG_HEXDUMP(MCMD_D, "BGSCAN: VHT_CAPABILITIES IE", (t_u8 *)pvht_cap, sizeof(MrvlIETypes_VHTCap_t));
+        tlv += sizeof(MrvlIETypes_VHTCap_t);
+        cmd_size += sizeof(MrvlIETypes_VHTCap_t);
+        pvht_cap->header.len = wlan_cpu_to_le16(pvht_cap->header.len);
+    }
+#endif
+
+#if CONFIG_11AX
+    if (IS_FW_SUPPORT_11AX(pmadapter) && ((pmpriv->config_bands & BAND_GAX)
+#if CONFIG_5GHz_SUPPORT
+                                          || (pmpriv->config_bands & BAND_AAX)
+#endif
+                                              ))
+    {
+        phe_cap = (MrvlIEtypes_Extension_t *)tlv;
+        len     = wlan_fill_he_cap_tlv(pmpriv, pmpriv->config_bands, phe_cap, MFALSE);
+        DBG_HEXDUMP(MCMD_D, "BGSCAN: HE_CAPABILITIES IE", (t_u8 *)phe_cap, len);
+        tlv += len;
+        cmd_size += len;
+    }
+#endif
+
+#if (CONFIG_DRIVER_MBO) || (CONFIG_WPA_SUPP)
+    wlan_add_ext_capa_info_ie(pmpriv, MNULL, &tlv);
+    cmd_size += sizeof(MrvlIETypes_ExtCap_t);
+#endif
+
+    if (pmpriv->adapter->ecsa_enable)
+    {
+        t_u8 bandwidth  = BW_20MHZ;
+        t_u8 oper_class = 1;
+        t_u32 usr_dot_11n_dev_cap;
+        if (pmpriv->media_connected)
+        {
+#if CONFIG_5GHz_SUPPORT
+            if (pmpriv->config_bands & BAND_A)
+                usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_a;
+            else
+#endif
+                usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_bg;
+            if (usr_dot_11n_dev_cap & MBIT(17))
+            {
+                bandwidth = BW_40MHZ;
+#if CONFIG_11AC
+                if (ISSUPP_11ACENABLED(pmadapter->fw_cap_info) && (pmpriv->config_bands & BAND_AAC))
+                    bandwidth = BW_80MHZ;
+#endif
+            }
+            wlan_get_curr_oper_class(pmpriv, pmpriv->curr_bss_params.bss_descriptor.channel, bandwidth, &oper_class);
+        }
+        len = wlan_add_supported_oper_class_ie(pmpriv, &tlv, oper_class);
+        cmd_size += len;
+    }
+
+    tlv_start_later              = (MrvlIEtypes_StartLater_t *)tlv;
+    tlv_start_later->header.type = wlan_cpu_to_le16(TLV_TYPE_STARTBGSCANLATER);
+    tlv_start_later->header.len  = wlan_cpu_to_le16(sizeof(MrvlIEtypes_StartLater_t) - sizeof(MrvlIEtypesHeader_t));
+    tlv_start_later->value       = bg_scan_in->start_later;
+    tlv += sizeof(MrvlIEtypes_StartLater_t);
+    cmd_size += sizeof(MrvlIEtypes_StartLater_t);
+done:
+    pcmd->size = wlan_cpu_to_le16(cmd_size);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+/**
+ *  @brief This function handles the command response of extended scan
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ret_bgscan_config(IN mlan_private *pmpriv, IN HostCmd_DS_COMMAND *resp, IN mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_scan *pscan                       = MNULL;
+    HostCmd_DS_802_11_BG_SCAN_CONFIG *bg_scan = &resp->params.bg_scan_config;
+    wlan_bgscan_cfg *bg_scan_out              = MNULL;
+
+    ENTER();
+    if (pioctl_buf)
+    {
+        pscan               = (mlan_ds_scan *)pioctl_buf->pbuf;
+        bg_scan_out         = (wlan_bgscan_cfg *)pscan->param.user_scan.scan_cfg_buf;
+        bg_scan_out->action = wlan_le16_to_cpu(bg_scan->action);
+#if CONFIG_WMM_UAPSD
+        if ((bg_scan_out->action == BG_SCAN_ACT_GET) && (bg_scan_out->action == BG_SCAN_ACT_GET_PPS_UAPSD))
+        {
+            bg_scan_out->enable           = bg_scan->enable;
+            bg_scan_out->bss_type         = bg_scan->bss_type;
+            bg_scan_out->chan_per_scan    = bg_scan->chan_per_scan;
+            bg_scan_out->scan_interval    = wlan_le32_to_cpu(bg_scan->scan_interval);
+            bg_scan_out->report_condition = wlan_le32_to_cpu(bg_scan->report_condition);
+            pioctl_buf->data_read_written = sizeof(mlan_ds_scan) + MLAN_SUB_COMMAND_SIZE;
+        }
+#endif
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function finds ssid in ssid list.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param ssid         SSID to find in the list
+ *  @param bssid        BSSID to qualify the SSID selection (if provided)
+ *  @param mode         Network mode: Infrastructure or IBSS
+ *
+ *  @return             index in BSSID list or < 0 if error
+ */
+t_s32 wlan_find_ssid_in_list(IN mlan_private *pmpriv, IN mlan_802_11_ssid *ssid, IN t_u8 *bssid, IN mlan_bss_mode mode)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_s32 net               = -1, j;
+    t_u8 best_rssi          = 0;
+    t_u32 i                 = 0U;
+
+    ENTER();
+    PRINTM(MINFO, "Num of entries in scan table = %d\n", pmadapter->num_in_scan_table);
+
+    /*
+     * Loop through the table until the maximum is reached or until a match
+     *   is found based on the bssid field comparison
+     */
+    while (i < pmadapter->num_in_scan_table && (bssid == MNULL || net < 0))
+    {
+        if ((wlan_ssid_cmp(pmadapter, &pmadapter->pscan_table[i].ssid, ssid) == 0) &&
+            ((bssid == MNULL) ||
+             (__memcmp(pmadapter, pmadapter->pscan_table[i].mac_address, bssid, MLAN_MAC_ADDR_LENGTH) == 0)))
+        {
+            if (((mode == MLAN_BSS_MODE_INFRA) &&
+                 (wlan_is_band_compatible(pmpriv->config_bands, pmadapter->pscan_table[i].bss_band) == 0U)) ||
+                (wlan_find_cfp_by_band_and_channel(pmadapter, pmadapter->pscan_table[i].bss_band,
+                                                   (t_u16)pmadapter->pscan_table[i].channel) == MNULL))
+            {
+                i++;
+                continue;
+            }
+
+            switch (mode)
+            {
+                case MLAN_BSS_MODE_INFRA:
+                case MLAN_BSS_MODE_IBSS:
+                    j = wlan_is_network_compatible(pmpriv, (t_u32)i, mode);
+
+                    if (j >= 0)
+                    {
+                        if (SCAN_RSSI(pmadapter->pscan_table[i].rssi) > best_rssi)
+                        {
+                            best_rssi = (t_u8)(SCAN_RSSI(pmadapter->pscan_table[i].rssi));
+                            net       = (t_s32)i;
+                        }
+                    }
+                    else
+                    {
+                        if (net == -1)
+                        {
+                            net = j;
+                        }
+                    }
+                    break;
+                case MLAN_BSS_MODE_AUTO:
+                default:
+                    /*
+                     * Do not check compatibility if the mode requested is
+                     *   Auto/Unknown.  Allows generic find to work without
+                     *   verifying against the Adapter security settings
+                     */
+                    if (SCAN_RSSI(pmadapter->pscan_table[i].rssi) > best_rssi)
+                    {
+                        best_rssi = (t_u8)(SCAN_RSSI(pmadapter->pscan_table[i].rssi));
+                        net       = (t_s32)i;
+                    }
+                    break;
+            }
+        }
+        i++;
+    }
+
+    LEAVE();
+    return net;
+}
+
+/**
+ *  @brief This function finds a specific compatible BSSID in the scan list
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param bssid        BSSID to find in the scan list
+ *  @param mode         Network mode: Infrastructure or IBSS
+ *
+ *  @return             index in BSSID list or < 0 if error
+ */
+t_s32 wlan_find_bssid_in_list(IN mlan_private *pmpriv, IN const t_u8 *bssid, IN mlan_bss_mode mode)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_s32 net               = -1;
+    t_u32 i                 = 0U;
+
+    ENTER();
+
+    if (bssid == MNULL)
+    {
+        LEAVE();
+        return -1;
+    }
+
+    PRINTM(MINFO, "FindBSSID: Num of BSSIDs = %d\n", pmadapter->num_in_scan_table);
+
+    /*
+     * Look through the scan table for a compatible match. The ret return
+     *   variable will be equal to the index in the scan table (greater
+     *   than zero) if the network is compatible.  The loop will continue
+     *   past a matched bssid that is not compatible in case there is an
+     *   AP with multiple SSIDs assigned to the same BSSID
+     */
+    while (i < pmadapter->num_in_scan_table)
+    {
+        if ((__memcmp(pmadapter, pmadapter->pscan_table[i].mac_address, bssid, MLAN_MAC_ADDR_LENGTH) == 0))
+        {
+            if (((mode == MLAN_BSS_MODE_INFRA) &&
+                 (wlan_is_band_compatible(pmpriv->config_bands, pmadapter->pscan_table[i].bss_band) == 0U)) ||
+                (wlan_find_cfp_by_band_and_channel(pmadapter, pmadapter->pscan_table[i].bss_band,
+                                                   (t_u16)pmadapter->pscan_table[i].channel) == MNULL))
+            {
+                i++;
+                continue;
+            }
+            switch (mode)
+            {
+                case MLAN_BSS_MODE_INFRA:
+                case MLAN_BSS_MODE_IBSS:
+                    /* fixme: temp disable. enable after below function is enabled */
+                    /* net = wlan_is_network_compatible(pmpriv, i, mode); */
+                    break;
+                default:
+                    net = (t_s32)i;
+                    if (pmadapter->pscan_table[i].ssid.ssid_len != 0)
+                        break;
+            }
+        }
+        i++;
+    }
+
+    LEAVE();
+    return net;
+}
+
+/**
+ *  @brief Compare two SSIDs
+ *
+ *  @param pmadapter A pointer to mlan_adapter structure
+ *  @param ssid1     A pointer to ssid to compare
+ *  @param ssid2     A pointer to ssid to compare
+ *
+ *  @return         0--ssid is same, otherwise is different
+ */
+t_s32 wlan_ssid_cmp(IN pmlan_adapter pmadapter, IN mlan_802_11_ssid *ssid1, IN mlan_802_11_ssid *ssid2)
+{
+    ENTER();
+
+    if ((ssid1 == MNULL) || (ssid2 == MNULL))
+    {
+        LEAVE();
+        return -1;
+    }
+
+    if (ssid1->ssid_len != ssid2->ssid_len)
+    {
+        LEAVE();
+        return -1;
+    }
+
+    LEAVE();
+    return __memcmp(pmadapter, ssid1->ssid, ssid2->ssid, ssid1->ssid_len);
+}
+
+
+static t_u32 wlan_find_worst_network_in_list(const BSSDescriptor_t *pbss_desc, t_u32 num_entries)
+{
+    t_u32 worst_net = 0U;
+    /* To start with */
+    t_s32 worst_rssi = pbss_desc[worst_net].rssi;
+    t_u32 i          = 0U;
+
+    ENTER();
+
+    for (i = 1; i < num_entries; i++)
+    {
+        /* Smaller is better i.e. smaller rssi value here means better
+           signal strength */
+        if (pbss_desc[i].rssi > worst_rssi)
+        {
+            worst_rssi = pbss_desc[i].rssi;
+            worst_net  = i;
+        }
+    }
+
+    LEAVE();
+    return worst_net;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_shim.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_shim.c
new file mode 100644
index 0000000000..075721762f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_shim.c
@@ -0,0 +1,359 @@
+/** @file mlan_shim.c
+ *
+ *  @brief  This file provides  APIs to MOAL module
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/**
+ *  @mainpage MLAN Driver
+ *
+ *  @section overview_sec Overview
+ *
+ *  The MLAN is an OS independent WLAN driver for NXP 802.11
+ *  embedded chipset.
+ */
+
+/********************************************************
+Change log:
+    10/13/2008: initial version
+********************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+        Global Variables
+********************************************************/
+static mlan_operations mlan_sta_ops = {
+    /* cmd handler */
+    wlan_ops_sta_prepare_cmd,
+    /* rx handler */
+    wlan_ops_process_rx_packet,
+    /* BSS role: STA */
+    MLAN_BSS_ROLE_STA,
+};
+static mlan_operations mlan_uap_ops = {
+    /* cmd handler */
+    wlan_ops_uap_prepare_cmd,
+       /* rx handler */
+    wlan_ops_process_rx_packet,
+    /* BSS role: uAP */
+    MLAN_BSS_ROLE_UAP,
+};
+
+/** mlan function table */
+static mlan_operations *mlan_ops[] = {
+    &mlan_sta_ops,
+    &mlan_uap_ops,
+    MNULL,
+};
+#if defined(RW610)
+extern bus_operations imu_ops;
+#endif
+/** Global moal_assert callback */
+t_void (*assert_callback)(IN t_void *pmoal_handle, IN t_u32 cond) = MNULL;
+#ifdef DEBUG_LEVEL1
+#ifdef DEBUG_LEVEL2
+#define DEFAULT_DEBUG_MASK (0xffffffffU)
+#else
+#define DEFAULT_DEBUG_MASK (MMSG | MFATAL | MERROR)
+#endif
+
+/** Global moal_print callback */
+t_void (*print_callback)(IN t_void *pmoal_handle, IN t_u32 level, IN t_s8 *pformat, IN...) = MNULL;
+
+/** Global moal_get_system_time callback */
+mlan_status (*get_sys_time_callback)(IN t_void *pmoal_handle, OUT t_u32 *psec, OUT t_u32 *pusec) = MNULL;
+
+/** Global driver debug mit masks */
+t_u32 drvdbg = DEFAULT_DEBUG_MASK;
+#endif
+
+/********************************************************
+        Local Functions
+*******************************************************/
+
+/********************************************************
+        Global Functions
+********************************************************/
+
+/**
+ *  @brief This function registers MOAL to MLAN module.
+ *
+ *  @param pmdevice        A pointer to a mlan_device structure
+ *                         allocated in MOAL
+ *  @param ppmlan_adapter  A pointer to a t_void pointer to store
+ *                         mlan_adapter structure pointer as the context
+ *
+ *  @return                MLAN_STATUS_SUCCESS
+ *                             The registration succeeded.
+ *                         MLAN_STATUS_FAILURE
+ *                             The registration failed.
+ *
+ * mlan_status mlan_register (
+ *   IN pmlan_device     pmdevice,
+ *   OUT t_void          **ppmlan_adapter
+ * );
+ *
+ * Comments
+ *   MOAL constructs mlan_device data structure to pass moal_handle and
+ *   mlan_callback table to MLAN. MLAN returns mlan_adapter pointer to
+ *   the ppmlan_adapter buffer provided by MOAL.
+ * Headers:
+ *   declared in mlan_decl.h
+ * See Also
+ *   mlan_unregister
+ */
+mlan_status mlan_register(IN pmlan_device pmdevice, OUT t_void **ppmlan_adapter)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    pmlan_adapter pmadapter = MNULL;
+    pmlan_callbacks pcb     = MNULL;
+    t_u8 i                  = 0;
+    t_u32 j                 = 0;
+
+    MASSERT(pmdevice);
+    MASSERT(ppmlan_adapter);
+    /* MASSERT(pmdevice->callbacks.moal_print); */
+#ifdef DEBUG_LEVEL1
+    print_callback        = pmdevice->callbacks.moal_print;
+    get_sys_time_callback = pmdevice->callbacks.moal_get_system_time;
+#endif
+    /* assert_callback = pmdevice->callbacks.moal_assert; */
+
+    ENTER();
+
+    MASSERT(pmdevice->callbacks.moal_malloc);
+    /* MASSERT(pmdevice->callbacks.moal_memset); */
+    /* MASSERT(pmdevice->callbacks.moal_memmove); */
+
+    /* Allocate memory for adapter structure */
+#if !CONFIG_MEM_POOLS
+    if ((pmdevice->callbacks.moal_malloc(/* pmdevice->pmoal_handle */ NULL, sizeof(mlan_adapter), MLAN_MEM_DEF,
+                                         (t_u8 **)(void **)&pmadapter) != MLAN_STATUS_SUCCESS) ||
+        (pmadapter == MNULL))
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto exit_register;
+    }
+#else
+    pmadapter = OSA_MemoryPoolAllocate(pmAdapterMemoryPool);
+    if (pmadapter == MNULL)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto exit_register;
+    }
+#endif
+
+    (void)__memset(pmadapter, pmadapter, 0, sizeof(mlan_adapter));
+
+    pcb = &pmadapter->callbacks;
+
+    /* Save callback functions */
+    (void)__memmove(pmadapter->pmoal_handle, pcb, &pmdevice->callbacks, sizeof(mlan_callbacks));
+
+    pmadapter->priv_num = 0;
+    for (i = 0; i < MLAN_MAX_BSS_NUM; i++)
+    {
+        pmadapter->priv[i] = MNULL;
+        if (pmdevice->bss_attr[i].active == MTRUE)
+        {
+            /* For valid bss_attr, allocate memory for private structure */
+#if !CONFIG_MEM_POOLS
+            if ((pcb->moal_malloc(pmadapter->pmoal_handle, sizeof(mlan_private), MLAN_MEM_DEF,
+                                  (t_u8 **)(void **)&pmadapter->priv[i]) != MLAN_STATUS_SUCCESS) ||
+                (pmadapter->priv[i] == MNULL))
+            {
+                ret = MLAN_STATUS_FAILURE;
+                goto error;
+            }
+#else
+            pmadapter->priv[i] = OSA_MemoryPoolAllocate(pmPrivateMemoryPool);
+            if (pmadapter->priv[i] == MNULL)
+            {
+                ret = MLAN_STATUS_FAILURE;
+                goto error;
+            }
+#endif
+            pmadapter->priv_num++;
+            (void)__memset(pmadapter, pmadapter->priv[i], 0, sizeof(mlan_private));
+
+            pmadapter->priv[i]->adapter = pmadapter;
+
+            /* Save bss_type, frame_type & bss_priority */
+            pmadapter->priv[i]->bss_type     = pmdevice->bss_attr[i].bss_type;
+            pmadapter->priv[i]->frame_type   = (t_u8)pmdevice->bss_attr[i].frame_type;
+            pmadapter->priv[i]->bss_priority = (t_u8)pmdevice->bss_attr[i].bss_priority;
+            if (pmdevice->bss_attr[i].bss_type == MLAN_BSS_TYPE_STA)
+            {
+                pmadapter->priv[i]->bss_role = MLAN_BSS_ROLE_STA;
+                pmadapter->priv[i]->bss_mode = MLAN_BSS_MODE_INFRA;
+            }
+            else if (pmdevice->bss_attr[i].bss_type == MLAN_BSS_TYPE_UAP)
+            {
+                pmadapter->priv[i]->bss_role = MLAN_BSS_ROLE_UAP;
+                pmadapter->priv[i]->bss_mode = MLAN_BSS_MODE_AUTO;
+            }
+            else
+            {
+                /*Do Nothing*/
+            }
+            /* Save bss_index and bss_num */
+            pmadapter->priv[i]->bss_index = i;
+            pmadapter->priv[i]->bss_num   = (t_u8)pmdevice->bss_attr[i].bss_num;
+
+            /* init function table */
+            for (j = 0; mlan_ops[j] != MNULL; j++)
+            {
+                if (mlan_ops[j]->bss_role == GET_BSS_ROLE(pmadapter->priv[i]))
+                {
+                    (void)__memcpy(pmadapter, &pmadapter->priv[i]->ops, mlan_ops[j], sizeof(mlan_operations));
+                }
+            }
+        }
+    }
+
+#if defined(RW610)
+    (void)__memcpy(pmadapter, &pmadapter->bus_ops, &imu_ops, sizeof(bus_operations));
+#endif
+
+    /* Initialize lock variables */
+    if (wlan_init_lock_list(pmadapter) != MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto error;
+    }
+
+    /* Allocate memory for member of adapter structure */
+    if (wlan_allocate_adapter(pmadapter) != MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto error;
+    }
+
+    /* Return pointer of mlan_adapter to MOAL */
+    *ppmlan_adapter = pmadapter;
+
+    goto exit_register;
+
+error:
+    PRINTM(MINFO, "Leave mlan_register with error\n");
+
+    for (i = 0; i < MLAN_MAX_BSS_NUM; i++)
+    {
+        if (pmadapter->priv[i])
+#if !CONFIG_MEM_POOLS
+            pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter->priv[i]);
+#else
+            OSA_MemoryPoolFree(pmPrivateMemoryPool, pmadapter->priv[i]);
+#endif
+    }
+#if !CONFIG_MEM_POOLS
+    (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter);
+#else
+    OSA_MemoryPoolFree(pmAdapterMemoryPool, pmadapter);
+#endif
+
+exit_register:
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function unregisters MOAL from MLAN module.
+ *
+ *  @param pmlan_adapter   A pointer to a mlan_device structure
+ *                         allocated in MOAL
+ *
+ *  @return                MLAN_STATUS_SUCCESS
+ *                             The deregistration succeeded.
+ */
+MLAN_API mlan_status mlan_unregister(IN t_void *pmlan_adapter)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = (mlan_adapter *)pmlan_adapter;
+#if !CONFIG_MEM_POOLS
+    pmlan_callbacks pcb;
+#endif
+    t_s32 i = 0;
+
+    MASSERT(pmlan_adapter);
+
+    ENTER();
+
+#if !CONFIG_MEM_POOLS
+    pcb = &pmadapter->callbacks;
+#endif
+
+    wlan_free_adapter(pmadapter);
+
+    /* Free private structures */
+    for (i = 0; i < MIN(pmadapter->priv_num, MLAN_MAX_BSS_NUM); i++)
+    {
+        if (pmadapter->priv[i] != MNULL)
+        {
+            wlan_delete_station_list(pmadapter->priv[i]);
+#if !CONFIG_MEM_POOLS
+            (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter->priv[i]);
+#else
+            OSA_MemoryPoolFree(pmPrivateMemoryPool, pmadapter->priv[i]);
+#endif
+            pmadapter->priv[i] = MNULL;
+        }
+    }
+
+#if !CONFIG_MEM_POOLS
+    /* Free mlan_adapter */
+    (void)pcb->moal_mfree(pmadapter->pmoal_handle, (t_u8 *)pmadapter);
+#else
+    OSA_MemoryPoolFree(pmAdapterMemoryPool, pmadapter);
+#endif
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief This function initializes the firmware
+ *
+ *  @param pmlan_adapter   A pointer to a t_void pointer to store
+ *                         mlan_adapter structure pointer
+ *
+ *  @return                MLAN_STATUS_SUCCESS
+ *                             The firmware initialization succeeded.
+ *                         MLAN_STATUS_PENDING
+ *                             The firmware initialization is pending.
+ *                         MLAN_STATUS_FAILURE
+ *                             The firmware initialization failed.
+ */
+mlan_status mlan_init_fw(IN t_void *pmlan_adapter)
+{
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    mlan_adapter *pmadapter = (mlan_adapter *)pmlan_adapter;
+
+    ENTER();
+    MASSERT(pmlan_adapter);
+
+    /* pmadapter->hw_status = WlanHardwareStatusInitializing; */
+
+    /* Initialize firmware, may return PENDING */
+    ret = wlan_init_fw(pmadapter);
+    PRINTM(MINFO, "wlan_init_fw returned ret=0x%x\n", ret);
+
+    LEAVE();
+    return ret;
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_cmd.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_cmd.c
new file mode 100644
index 0000000000..93dcc824f6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_cmd.c
@@ -0,0 +1,2198 @@
+/** @file mlan_sta_cmd.c
+ *
+ *  @brief This file provides the handling of command. It prepares command and sends it to firmware when it is ready
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/21/2008: initial version
+******************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+mlan_status wlan_cmd_auto_reconnect(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf);
+mlan_status wlan_cmd_mem_access(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf);
+mlan_status wlan_cmd_reg_access(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf);
+mlan_status wlan_cmd_802_11_deauthenticate(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf);
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+#if CONFIG_RF_TEST_MODE
+/**
+ *  @brief This function prepares command of MFG Continuous Tx cmd.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param action       The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_mfg_tx_cont(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 action, t_void *pdata_buf)
+{
+    HostCmd_DS_MFG_CMD_TX_CONT *mcmd = (HostCmd_DS_MFG_CMD_TX_CONT *)&cmd->params.mfg_tx_cont;
+    mlan_ds_mfg_cmd_tx_cont *cfg     = (mlan_ds_mfg_cmd_tx_cont *)pdata_buf;
+
+    ENTER();
+
+    (void)__memset(pmpriv->adapter, mcmd, 0x00, sizeof(HostCmd_DS_MFG_CMD_TX_CONT));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MFG_CMD_TX_CONT) + S_DS_GEN);
+
+    mcmd->mfg_cmd = wlan_cpu_to_le32(cfg->mfg_cmd);
+    mcmd->action  = wlan_cpu_to_le16(action);
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        mcmd->enable_tx       = wlan_cpu_to_le32(cfg->enable_tx);
+        mcmd->cw_mode         = wlan_cpu_to_le32(cfg->cw_mode);
+        mcmd->payload_pattern = wlan_cpu_to_le32(cfg->payload_pattern);
+        mcmd->cs_mode         = wlan_cpu_to_le32(cfg->cs_mode);
+        mcmd->act_sub_ch      = wlan_cpu_to_le32(cfg->act_sub_ch);
+        mcmd->tx_rate         = wlan_cpu_to_le32(cfg->tx_rate);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of MFG Tx frame.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param action       The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_mfg_tx_frame(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 action, t_void *pdata_buf)
+{
+    HostCmd_DS_MFG_CMD_TX_FRAME2 *mcmd = (HostCmd_DS_MFG_CMD_TX_FRAME2 *)&cmd->params.mfg_tx_frame2;
+    mlan_ds_mfg_cmd_tx_frame2 *cfg     = (mlan_ds_mfg_cmd_tx_frame2 *)pdata_buf;
+
+    ENTER();
+
+    (void)__memset(pmpriv->adapter, mcmd, 0x00, sizeof(HostCmd_DS_MFG_CMD_TX_FRAME2));
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MFG_CMD_TX_FRAME2) + S_DS_GEN);
+
+    mcmd->mfg_cmd = wlan_cpu_to_le32(cfg->mfg_cmd);
+    mcmd->action  = wlan_cpu_to_le16(action);
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        mcmd->enable            = wlan_cpu_to_le32(cfg->enable);
+        mcmd->data_rate         = wlan_cpu_to_le32(cfg->data_rate);
+        mcmd->frame_pattern     = wlan_cpu_to_le32(cfg->frame_pattern);
+        mcmd->frame_length      = wlan_cpu_to_le32(cfg->frame_length);
+        mcmd->adjust_burst_sifs = wlan_cpu_to_le16(cfg->adjust_burst_sifs);
+        mcmd->burst_sifs_in_us  = wlan_cpu_to_le32(cfg->burst_sifs_in_us);
+        mcmd->short_preamble    = wlan_cpu_to_le32(cfg->short_preamble);
+        mcmd->act_sub_ch        = wlan_cpu_to_le32(cfg->act_sub_ch);
+        mcmd->short_gi          = wlan_cpu_to_le32(cfg->short_gi);
+        mcmd->adv_coding        = wlan_cpu_to_le32(cfg->adv_coding);
+        mcmd->tx_bf             = wlan_cpu_to_le32(cfg->tx_bf);
+        mcmd->gf_mode           = wlan_cpu_to_le32(cfg->gf_mode);
+        mcmd->stbc              = wlan_cpu_to_le32(cfg->stbc);
+        mcmd->signal_bw         = wlan_cpu_to_le32(cfg->signal_bw);
+        mcmd->NumPkt            = wlan_cpu_to_le32(cfg->NumPkt);
+        mcmd->MaxPE             = wlan_cpu_to_le32(cfg->MaxPE);
+        mcmd->BeamChange        = wlan_cpu_to_le32(cfg->BeamChange);
+        mcmd->Dcm               = wlan_cpu_to_le32(cfg->Dcm);
+        mcmd->Doppler           = wlan_cpu_to_le32(cfg->Doppler);
+        mcmd->MidP              = wlan_cpu_to_le32(cfg->MidP);
+        mcmd->QNum              = wlan_cpu_to_le32(cfg->QNum);
+        (void)__memcpy(pmpriv->adapter, mcmd->bssid, cfg->bssid, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of MFG HE TB Tx.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param action       The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+
+static mlan_status wlan_cmd_mfg_he_tb_tx(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 action, t_void *pdata_buf)
+{
+    HostCmd_DS_MFG_CMD_HE_TBTX_T *mcmd = (HostCmd_DS_MFG_CMD_HE_TBTX_T *)&cmd->params.mfg_he_power;
+    mlan_ds_mfg_Cmd_HE_TBTx_t *cfg     = (mlan_ds_mfg_Cmd_HE_TBTx_t *)pdata_buf;
+    ENTER();
+    (void)__memset(pmpriv->adapter, mcmd, 0x00, sizeof(HostCmd_DS_MFG_CMD_HE_TBTX_T));
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MFG_CMD_HE_TBTX_T) + S_DS_GEN);
+
+    mcmd->mfg_cmd = wlan_cpu_to_le32(cfg->mfg_cmd);
+    mcmd->action  = wlan_cpu_to_le16(action);
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        mcmd->enable       = wlan_cpu_to_le16(cfg->enable);
+        mcmd->qnum         = wlan_cpu_to_le16(cfg->qnum);
+        mcmd->aid          = wlan_cpu_to_le16(cfg->aid);
+        mcmd->axq_mu_timer = wlan_cpu_to_le16(cfg->axq_mu_timer);
+        mcmd->tx_power     = wlan_cpu_to_le16(cfg->tx_power);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of MFG OTP MAC add.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param action       The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+
+static mlan_status wlan_cmd_mfg_otp_mac_add(pmlan_private pmpriv,
+                                            HostCmd_DS_COMMAND *cmd,
+                                            t_u16 action,
+                                            t_void *pdata_buf)
+{
+    HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T *mcmd    = (HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T *)&cmd->params.mfg_otp_mac_addr_rd_wr;
+    mlan_ds_mfg_cmd_otp_mac_addr_rd_wr_t *cfg = (mlan_ds_mfg_cmd_otp_mac_addr_rd_wr_t *)pdata_buf;
+    ENTER();
+    (void)__memset(pmpriv->adapter, mcmd, 0x00, sizeof(HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T));
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T) + S_DS_GEN);
+
+    mcmd->mfg_cmd = wlan_cpu_to_le32(cfg->mfg_cmd);
+    mcmd->action  = wlan_cpu_to_le16(action);
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        (void)__memcpy(pmpriv->adapter, mcmd->mac_addr, cfg->mac_addr, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of MFG OTP cal data.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param action       The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+
+static mlan_status wlan_cmd_mfg_otp_cal_data(pmlan_private pmpriv,
+                                             HostCmd_DS_COMMAND *cmd,
+                                             t_u16 action,
+                                             t_void *pdata_buf)
+{
+    HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T *mcmd = (HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T *)&cmd->params.mfg_otp_cal_data_rd_wr;
+    mlan_ds_mfg_cmd_otp_cal_data_rd_wr_t *cfg = (mlan_ds_mfg_cmd_otp_cal_data_rd_wr_t *)pdata_buf;
+    ENTER();
+    (void)__memset(pmpriv->adapter, mcmd, 0x00, sizeof(HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T));
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T) + S_DS_GEN);
+
+    mcmd->mfg_cmd         = wlan_cpu_to_le32(cfg->mfg_cmd);
+    mcmd->action          = wlan_cpu_to_le16(action);
+    mcmd->cal_data_status = wlan_cpu_to_le16(cfg->cal_data_status);
+    mcmd->cal_data_len    = wlan_cpu_to_le16(cfg->cal_data_len);
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        (void)__memcpy(pmpriv->adapter, mcmd->cal_data, cfg->cal_data, cfg->cal_data_len);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of MFG config trigger frame.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param action       The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_mfg_config_trigger_frame(pmlan_private pmpriv,
+                                                     HostCmd_DS_COMMAND *cmd,
+                                                     t_u16 action,
+                                                     t_void *pdata_buf)
+{
+    HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T *mcmd =
+        (HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T *)&cmd->params.mfg_tx_trigger_config;
+    mfg_Cmd_IEEEtypes_CtlBasicTrigHdr_t *cfg = (mfg_Cmd_IEEEtypes_CtlBasicTrigHdr_t *)pdata_buf;
+
+    ENTER();
+    (void)__memset(pmpriv->adapter, mcmd, 0x00, sizeof(HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T));
+    cmd->command  = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
+    cmd->size     = wlan_cpu_to_le16(sizeof(HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T) + S_DS_GEN);
+    mcmd->mfg_cmd = wlan_cpu_to_le32(cfg->mfg_cmd);
+    mcmd->action  = wlan_cpu_to_le16(action);
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        mcmd->enable_tx       = wlan_cpu_to_le32(cfg->enable_tx);
+        mcmd->standalone_hetb = wlan_cpu_to_le32(cfg->standalone_hetb);
+        mcmd->frmCtl.type     = wlan_cpu_to_le16(cfg->frmCtl.type);
+        mcmd->frmCtl.sub_type = wlan_cpu_to_le16(cfg->frmCtl.sub_type);
+        mcmd->duration        = wlan_cpu_to_le16(cfg->duration);
+
+        mcmd->trig_common_field    = wlan_cpu_to_le64(cfg->trig_common_field);
+        mcmd->trig_user_info_field = wlan_cpu_to_le64(cfg->trig_user_info_field);
+        mcmd->basic_trig_user_info = wlan_cpu_to_le16(cfg->basic_trig_user_info);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of MFG cmd.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param action       The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_mfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 action, t_void *pdata_buf)
+{
+    HostCmd_DS_MFG_CMD_GENERIC_CFG *mcmd = (HostCmd_DS_MFG_CMD_GENERIC_CFG *)&cmd->params.mfg_generic_cfg;
+    mlan_ds_mfg_cmd_generic_cfg *cfg     = (mlan_ds_mfg_cmd_generic_cfg *)pdata_buf;
+    mlan_status ret                      = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    if (!mcmd || !cfg)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto cmd_mfg_done;
+    }
+
+    (void)__memset(pmpriv->adapter, mcmd, 0x00, sizeof(HostCmd_DS_MFG_CMD_GENERIC_CFG));
+
+    switch (cfg->mfg_cmd)
+    {
+        case MFG_CMD_TX_FRAME:
+            ret = wlan_cmd_mfg_tx_frame(pmpriv, cmd, action, pdata_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_TX_CONT:
+            ret = wlan_cmd_mfg_tx_cont(pmpriv, cmd, action, pdata_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_CONFIG_MAC_HE_TB_TX:
+            ret = wlan_cmd_mfg_he_tb_tx(pmpriv, cmd, action, pdata_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_CONFIG_TRIGGER_FRAME:
+            ret = wlan_cmd_mfg_config_trigger_frame(pmpriv, cmd, action, pdata_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_OTP_MAC_ADD:
+            ret = wlan_cmd_mfg_otp_mac_add(pmpriv, cmd, action, pdata_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_OTP_CAL_DATA:
+            ret = wlan_cmd_mfg_otp_cal_data(pmpriv, cmd, action, pdata_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_SET_TEST_MODE:
+        case MFG_CMD_UNSET_TEST_MODE:
+        case MFG_CMD_TX_ANT:
+        case MFG_CMD_RX_ANT:
+        case MFG_CMD_RF_CHAN:
+        case MFG_CMD_CLR_RX_ERR:
+        case MFG_CMD_RF_BAND_AG:
+        case MFG_CMD_RF_CHANNELBW:
+        case MFG_CMD_RFPWR:
+        case MFG_CMD_RADIO_MODE_CFG:
+            break;
+        default:
+            ret = MLAN_STATUS_FAILURE;
+            goto cmd_mfg_done;
+    }
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MFG_CMD_GENERIC_CFG) + S_DS_GEN);
+
+    mcmd->mfg_cmd = wlan_cpu_to_le32(cfg->mfg_cmd);
+    mcmd->action  = wlan_cpu_to_le16(action);
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        mcmd->data1 = wlan_cpu_to_le32(cfg->data1);
+        mcmd->data2 = wlan_cpu_to_le32(cfg->data2);
+        mcmd->data3 = wlan_cpu_to_le32(cfg->data3);
+    }
+cmd_mfg_done:
+    LEAVE();
+    return ret;
+}
+#endif
+
+/**
+ *  @brief This function prepares command of RSSI info.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pcmd         A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   Command action
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_rssi_info(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *pcmd, IN t_u16 cmd_action)
+{
+    ENTER();
+
+    pcmd->command                 = wlan_cpu_to_le16(HostCmd_CMD_RSSI_INFO);
+    pcmd->size                    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_RSSI_INFO) + S_DS_GEN);
+    pcmd->params.rssi_info.action = wlan_cpu_to_le16(cmd_action);
+    pcmd->params.rssi_info.ndata  = wlan_cpu_to_le16(pmpriv->data_avg_factor);
+    pcmd->params.rssi_info.nbcn   = wlan_cpu_to_le16(pmpriv->bcn_avg_factor);
+
+    /* Reset SNR/NF/RSSI values in private structure */
+    pmpriv->data_rssi_last = 0;
+    pmpriv->data_nf_last   = 0;
+    pmpriv->data_rssi_avg  = 0;
+    pmpriv->data_nf_avg    = 0;
+    pmpriv->bcn_rssi_last  = 0;
+    pmpriv->bcn_nf_last    = 0;
+    pmpriv->bcn_rssi_avg   = 0;
+    pmpriv->bcn_nf_avg     = 0;
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of mac_control.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pcmd         A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   Command action
+ *  @param pdata_buf    A pointer to command information buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_cmd_mac_control(IN pmlan_private pmpriv,
+                                        IN HostCmd_DS_COMMAND *pcmd,
+                                        IN t_u16 cmd_action,
+                                        IN t_void *pdata_buf)
+{
+    HostCmd_DS_MAC_CONTROL *pmac = &pcmd->params.mac_ctrl;
+    t_u16 action                 = *((t_u16 *)pdata_buf);
+
+    ENTER();
+
+    if (cmd_action != HostCmd_ACT_GEN_SET)
+    {
+        PRINTM(MERROR, "wlan_cmd_mac_control(): support SET only.\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    pcmd->command = wlan_cpu_to_le16(HostCmd_CMD_MAC_CONTROL);
+    pcmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MAC_CONTROL) + S_DS_GEN);
+    pmac->action  = wlan_cpu_to_le16(action);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of snmp_mib.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param cmd_oid      OID: ENABLE or DISABLE
+ *  @param pdata_buf    A pointer to command information buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_snmp_mib(
+    IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_u32 cmd_oid, IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_SNMP_MIB *psnmp_mib = &cmd->params.smib;
+    t_u32 ul_temp;
+
+    ENTER();
+    PRINTM(MINFO, "SNMP_CMD: cmd_oid = 0x%x\n", cmd_oid);
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SNMP_MIB);
+    cmd->size    = sizeof(HostCmd_DS_802_11_SNMP_MIB) - 1U + S_DS_GEN;
+
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        psnmp_mib->query_type = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
+        psnmp_mib->buf_size   = wlan_cpu_to_le16(MAX_SNMP_BUF_SIZE);
+        cmd->size += MAX_SNMP_BUF_SIZE;
+    }
+
+    switch (cmd_oid)
+    {
+#if CONFIG_WIFI_FRAG_THRESHOLD
+        case FragThresh_i:
+            psnmp_mib->oid = wlan_cpu_to_le16((t_u16)FragThresh_i);
+            if (cmd_action == HostCmd_ACT_GEN_SET)
+            {
+                psnmp_mib->query_type          = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+                psnmp_mib->buf_size            = wlan_cpu_to_le16(sizeof(t_u16));
+                ul_temp                        = *((t_u32 *)pdata_buf);
+                *((t_u16 *)(psnmp_mib->value)) = wlan_cpu_to_le16((t_u16)ul_temp);
+                cmd->size += sizeof(t_u16);
+            }
+            break;
+#endif
+        case RtsThresh_i:
+            psnmp_mib->oid = wlan_cpu_to_le16((t_u16)RtsThresh_i);
+            if (cmd_action == HostCmd_ACT_GEN_SET)
+            {
+                psnmp_mib->query_type        = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+                psnmp_mib->buf_size          = wlan_cpu_to_le16(sizeof(t_u16));
+                ul_temp                      = *((t_u32 *)pdata_buf);
+                *(t_u16 *)(psnmp_mib->value) = wlan_cpu_to_le16((t_u16)ul_temp);
+                cmd->size += sizeof(t_u16);
+            }
+            break;
+        case Dot11D_i:
+            psnmp_mib->oid = wlan_cpu_to_le16((t_u16)Dot11D_i);
+            if (cmd_action == HostCmd_ACT_GEN_SET)
+            {
+                psnmp_mib->query_type                  = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+                psnmp_mib->buf_size                    = wlan_cpu_to_le16(sizeof(t_u16));
+                ul_temp                                = *(t_u32 *)pdata_buf;
+                *((t_u16 *)(void *)(psnmp_mib->value)) = wlan_cpu_to_le16((t_u16)ul_temp);
+                cmd->size += (t_u16)sizeof(t_u16);
+            }
+            break;
+        case Dot11H_i:
+            psnmp_mib->oid = wlan_cpu_to_le16((t_u16)Dot11H_i);
+            if (cmd_action == HostCmd_ACT_GEN_SET)
+            {
+                psnmp_mib->query_type                  = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+                psnmp_mib->buf_size                    = wlan_cpu_to_le16(sizeof(t_u16));
+                ul_temp                                = *(t_u32 *)pdata_buf;
+                *((t_u16 *)(void *)(psnmp_mib->value)) = wlan_cpu_to_le16((t_u16)ul_temp);
+                cmd->size += (t_u16)sizeof(t_u16);
+            }
+            break;
+        case ECSAEnable_i:
+            psnmp_mib->oid = wlan_cpu_to_le16((t_u16)ECSAEnable_i);
+            if (cmd_action == HostCmd_ACT_GEN_SET)
+            {
+                psnmp_mib->query_type = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+                psnmp_mib->buf_size   = wlan_cpu_to_le16(sizeof(t_u8));
+                psnmp_mib->value[0]   = *((t_u8 *)pdata_buf);
+                cmd->size += (t_u16)sizeof(t_u8);
+            }
+            break;
+        default:
+            PRINTM(MINFO, "Unexpected SNMP MIB INDEX \n");
+            break;
+    }
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+    PRINTM(MINFO, "SNMP_CMD: Action=0x%x, OID=0x%x, OIDSize=0x%x, Value=0x%x\n", cmd_action, cmd_oid,
+           wlan_le16_to_cpu(psnmp_mib->buf_size), wlan_le16_to_cpu(*(t_u16 *)psnmp_mib->value));
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of get_log.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_get_log(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd)
+{
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_GET_LOG);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_GET_LOG) + S_DS_GEN);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of tx_power_cfg.
+ *
+ *  @param pmpriv      A pointer to mlan_private structure
+ *  @param cmd         A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action  The action: GET or SET
+ *  @param pdata_buf   A pointer to data buffer
+ *
+ *  @return            MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_tx_power_cfg(IN pmlan_private pmpriv,
+                                         IN HostCmd_DS_COMMAND *cmd,
+                                         IN t_u16 cmd_action,
+                                         IN t_void *pdata_buf)
+{
+    MrvlTypes_Power_Group_t *ppg_tlv = MNULL;
+    HostCmd_DS_TXPWR_CFG *ptxp       = MNULL;
+    HostCmd_DS_TXPWR_CFG *ptxp_cfg   = &cmd->params.txp_cfg;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_TXPWR_CFG);
+    cmd->size    = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_TXPWR_CFG));
+    switch (cmd_action)
+    {
+        case HostCmd_ACT_GEN_SET:
+            ptxp = (HostCmd_DS_TXPWR_CFG *)pdata_buf;
+            if (ptxp->mode != 0U)
+            {
+                ppg_tlv = (MrvlTypes_Power_Group_t *)(void *)((t_u8 *)pdata_buf + sizeof(HostCmd_DS_TXPWR_CFG));
+                (void)__memmove(
+                    pmpriv->adapter, ptxp_cfg, pdata_buf,
+                    sizeof(HostCmd_DS_TXPWR_CFG) + sizeof(MrvlTypes_Power_Group_t) + (t_u32)ppg_tlv->length);
+
+                ppg_tlv = (MrvlTypes_Power_Group_t *)(void *)((t_u8 *)&cmd->params + sizeof(HostCmd_DS_TXPWR_CFG));
+                cmd->size += (t_u16)(wlan_cpu_to_le16(sizeof(MrvlTypes_Power_Group_t) + ppg_tlv->length));
+                ppg_tlv->type   = wlan_cpu_to_le16(ppg_tlv->type);
+                ppg_tlv->length = wlan_cpu_to_le16(ppg_tlv->length);
+            }
+            else
+            {
+                (void)__memmove(pmpriv->adapter, ptxp_cfg, pdata_buf, sizeof(HostCmd_DS_TXPWR_CFG));
+            }
+            ptxp_cfg->action    = wlan_cpu_to_le16(cmd_action);
+            ptxp_cfg->cfg_index = wlan_cpu_to_le16(ptxp_cfg->cfg_index);
+            ptxp_cfg->mode      = wlan_cpu_to_le32(ptxp_cfg->mode);
+            break;
+        case HostCmd_ACT_GEN_GET:
+            ptxp_cfg->action = wlan_cpu_to_le16(cmd_action);
+            break;
+        default:
+            PRINTM(MINFO, "Unexpected Host Cmd tx_power_cfg\n");
+            break;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of rf_tx_power.
+ *
+ *  @param pmpriv     A pointer to wlan_private structure
+ *  @param cmd        A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action the action: GET or SET
+ *  @param pdata_buf  A pointer to data buffer
+ *  @return           MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_rf_tx_power(IN pmlan_private pmpriv,
+                                               IN HostCmd_DS_COMMAND *cmd,
+                                               IN t_u16 cmd_action,
+                                               IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_RF_TX_POWER *prtp = &cmd->params.txp;
+
+    ENTER();
+
+    cmd->size    = wlan_cpu_to_le16((sizeof(HostCmd_DS_802_11_RF_TX_POWER)) + S_DS_GEN);
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RF_TX_POWER);
+    prtp->action = cmd_action;
+
+    PRINTM(MINFO, "RF_TX_POWER_CMD: Size:%d Cmd:0x%x Act:%d\n", cmd->size, cmd->command, prtp->action);
+
+    switch (cmd_action)
+    {
+        case HostCmd_ACT_GEN_GET:
+            prtp->action        = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
+            prtp->current_level = 0;
+            break;
+
+        case HostCmd_ACT_GEN_SET:
+            prtp->action        = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+            prtp->current_level = wlan_cpu_to_le16(*((t_u16 *)pdata_buf));
+            break;
+        default:
+            PRINTM(MINFO, "Unexpected Host Cmd rf_tx_power \n");
+            break;
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ * @brief This function prepares command of hs_cfg.
+ *
+ * @param pmpriv       A pointer to mlan_private structure
+ * @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ * @param cmd_action   The action: GET or SET
+ * @param pdata_buf    A pointer to data buffer
+ *
+ * @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_hs_cfg(IN pmlan_private pmpriv,
+                                          IN HostCmd_DS_COMMAND *cmd,
+                                          IN t_u16 cmd_action,
+                                          IN hs_config_param *pdata_buf)
+{
+    HostCmd_DS_802_11_HS_CFG_ENH *phs_cfg = &cmd->params.opt_hs_cfg;
+    t_u16 hs_activate                     = MFALSE;
+
+    ENTER();
+    if (pdata_buf == MNULL)
+    {
+        /* New Activate command */
+        hs_activate = MTRUE;
+    }
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_HS_CFG_ENH);
+
+        cmd->size = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_802_11_HS_CFG_ENH));
+
+    if (hs_activate != 0U)
+    {
+        phs_cfg->action                       = wlan_cpu_to_le16(HS_ACTIVATE);
+        phs_cfg->params.hs_activate.resp_ctrl = wlan_cpu_to_le16(RESP_NEEDED);
+    }
+    else
+    {
+        phs_cfg->action                      = wlan_cpu_to_le16(HS_CONFIGURE);
+        phs_cfg->params.hs_config.conditions = wlan_cpu_to_le32(pdata_buf->conditions);
+        phs_cfg->params.hs_config.gpio       = pdata_buf->gpio;
+        phs_cfg->params.hs_config.gap        = pdata_buf->gap;
+        PRINTM(MCMND, "HS_CFG_CMD: condition:0x%x gpio:0x%x gap:0x%x\n", phs_cfg->params.hs_config.conditions,
+               phs_cfg->params.hs_config.gpio, phs_cfg->params.hs_config.gap);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of mac_address.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_mac_address(IN pmlan_private pmpriv,
+                                               IN HostCmd_DS_COMMAND *cmd,
+                                               IN t_u16 cmd_action,
+                                               t_void *pdata_buf)
+{
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_MAC_ADDRESS);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_MAC_ADDRESS) + S_DS_GEN);
+    cmd->result  = 0;
+
+    cmd->params.mac_addr.action = wlan_cpu_to_le16(cmd_action);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        (void)__memcpy(pmpriv->adapter, cmd->params.mac_addr.mac_addr, pdata_buf, MLAN_MAC_ADDR_LENGTH);
+        // HEXDUMP("SET_CMD: MAC ADDRESS-", priv->CurrentAddr, 6);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if CONFIG_WMM_UAPSD
+/**
+ * @brief This function prepares command of sleep_period.
+ *
+ * @param pmpriv       A pointer to mlan_private structure
+ * @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ * @param cmd_action   The action: GET or SET
+ * @param pdata_buf    A pointer to data buffer
+ *
+ * @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_sleep_period(IN pmlan_private pmpriv,
+                                                IN HostCmd_DS_COMMAND *cmd,
+                                                IN t_u16 cmd_action,
+                                                IN t_u16 *pdata_buf)
+{
+    HostCmd_DS_802_11_SLEEP_PERIOD *pcmd_sleep_pd = &cmd->params.sleep_pd;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SLEEP_PERIOD);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_SLEEP_PERIOD) + S_DS_GEN);
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        pcmd_sleep_pd->sleep_pd = wlan_cpu_to_le16(*(t_u16 *)pdata_buf);
+    }
+    pcmd_sleep_pd->action = wlan_cpu_to_le16(cmd_action);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+/**
+ *  @brief This function prepares command of mac_multicast_adr.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_mac_multicast_adr(IN pmlan_private pmpriv,
+                                              IN HostCmd_DS_COMMAND *cmd,
+                                              IN t_u16 cmd_action,
+                                              IN t_void *pdata_buf)
+{
+    mlan_multicast_list *pmcast_list       = (mlan_multicast_list *)pdata_buf;
+    HostCmd_DS_MAC_MULTICAST_ADR *pmc_addr = &cmd->params.mc_addr;
+
+    ENTER();
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MAC_MULTICAST_ADR) + S_DS_GEN);
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MAC_MULTICAST_ADR);
+
+    pmc_addr->action      = wlan_cpu_to_le16(cmd_action);
+    pmc_addr->num_of_adrs = wlan_cpu_to_le16((t_u16)pmcast_list->num_multicast_addr);
+    (void)__memcpy(pmpriv->adapter, pmc_addr->mac_list, pmcast_list->mac_list,
+                   pmcast_list->num_multicast_addr * MLAN_MAC_ADDR_LENGTH);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of deauthenticate.
+ *
+ * @param pmpriv       A pointer to mlan_private structure
+ * @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ * @param pdata_buf    A pointer to data buffer
+ *
+ * @return             MLAN_STATUS_SUCCESS
+ */
+/* static */ mlan_status wlan_cmd_802_11_deauthenticate(IN pmlan_private pmpriv,
+                                                        IN HostCmd_DS_COMMAND *cmd,
+                                                        IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_DEAUTHENTICATE *pdeauth = &cmd->params.deauth;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_DEAUTHENTICATE);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_DEAUTHENTICATE) + S_DS_GEN);
+
+    /* Set AP MAC address */
+    (void)__memcpy(pmpriv->adapter, pdeauth->mac_addr, (t_u8 *)pdata_buf, MLAN_MAC_ADDR_LENGTH);
+
+    PRINTM(MCMND, "Deauth: %02x:%02x:%02x:%02x:%02x:%02x\n", pdeauth->mac_addr[0], pdeauth->mac_addr[1],
+           pdeauth->mac_addr[2], pdeauth->mac_addr[3], pdeauth->mac_addr[4], pdeauth->mac_addr[5]);
+
+    if (pmpriv->adapter->state_11h.recvd_chanswann_event)
+    {
+/** Reason code 36 = Requested from peer station as it is leaving the BSS */
+#define REASON_CODE_PEER_STA_LEAVING 36
+        pdeauth->reason_code = wlan_cpu_to_le16(REASON_CODE_PEER_STA_LEAVING);
+    }
+    else
+    {
+/** Reason code 3 = Station is leaving */
+#define REASON_CODE_STA_LEAVING 3
+        pdeauth->reason_code = wlan_cpu_to_le16(REASON_CODE_STA_LEAVING);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+/**
+ *  @brief This function prepares command of key_material.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param cmd_oid      OID: ENABLE or DISABLE
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_cmd_802_11_key_material(
+    pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_u32 cmd_oid, t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_KEY_MATERIAL *pkey_material = &cmd->params.key_material;
+    mlan_ds_encrypt_key *pkey                     = (mlan_ds_encrypt_key *)pdata_buf;
+    mlan_status ret                               = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+    if (!pkey)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+    cmd->command          = wlan_cpu_to_le16(HostCmd_CMD_802_11_KEY_MATERIAL);
+    pkey_material->action = wlan_cpu_to_le16(cmd_action);
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        wifi_d("GET Key");
+        pkey_material->key_param_set.key_idx = pkey->key_index & KEY_INDEX_MASK;
+        pkey_material->key_param_set.type    = wlan_cpu_to_le16(TLV_TYPE_KEY_PARAM_V2);
+        pkey_material->key_param_set.length  = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.mac_addr, pkey->mac_addr, MLAN_MAC_ADDR_LENGTH,
+                   MLAN_MAC_ADDR_LENGTH);
+        if (pkey->key_flags & KEY_FLAG_GROUP_KEY)
+            pkey_material->key_param_set.key_info |= KEY_INFO_MCAST_KEY;
+        else
+            pkey_material->key_param_set.key_info |= KEY_INFO_UCAST_KEY;
+        if (pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK)
+            pkey_material->key_param_set.key_info = KEY_INFO_CMAC_AES_KEY;
+        pkey_material->key_param_set.key_info = wlan_cpu_to_le16(pkey_material->key_param_set.key_info);
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(pkey_material->action));
+        goto done;
+    }
+    (void)__memset(pmpriv->adapter, &pkey_material->key_param_set, 0, sizeof(MrvlIEtype_KeyParamSetV2_t));
+    if (pkey->key_flags & KEY_FLAG_REMOVE_KEY)
+    {
+        pkey_material->action                = wlan_cpu_to_le16(HostCmd_ACT_GEN_REMOVE);
+        pkey_material->key_param_set.type    = wlan_cpu_to_le16(TLV_TYPE_KEY_PARAM_V2);
+        pkey_material->key_param_set.length  = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN);
+        pkey_material->key_param_set.key_idx = pkey->key_index & KEY_INDEX_MASK;
+        pkey_material->key_param_set.key_info =
+            wlan_cpu_to_le16(KEY_INFO_MCAST_KEY | KEY_INFO_UCAST_KEY | KEY_INFO_CMAC_AES_KEY);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.mac_addr, pkey->mac_addr, MLAN_MAC_ADDR_LENGTH,
+                   MLAN_MAC_ADDR_LENGTH);
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(pkey_material->action));
+        wifi_d("Remove Key");
+        goto done;
+    }
+    pkey_material->action                 = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+    pkey_material->key_param_set.key_idx  = pkey->key_index & KEY_INDEX_MASK;
+    pkey_material->key_param_set.type     = wlan_cpu_to_le16(TLV_TYPE_KEY_PARAM_V2);
+    pkey_material->key_param_set.key_info = KEY_INFO_ENABLE_KEY;
+    memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.mac_addr, pkey->mac_addr, MLAN_MAC_ADDR_LENGTH,
+               MLAN_MAC_ADDR_LENGTH);
+    if (pkey->key_len <= MAX_WEP_KEY_SIZE)
+    {
+        pkey_material->key_param_set.length   = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(wep_param_t));
+        pkey_material->key_param_set.key_type = KEY_TYPE_ID_WEP;
+        if (pkey->is_current_wep_key)
+        {
+            pkey_material->key_param_set.key_info |= KEY_INFO_MCAST_KEY | KEY_INFO_UCAST_KEY;
+            if (pkey_material->key_param_set.key_idx == (pmpriv->wep_key_curr_index & KEY_INDEX_MASK))
+                pkey_material->key_param_set.key_info |= KEY_INFO_DEFAULT_KEY;
+        }
+        else
+        {
+            if (pkey->key_flags & KEY_FLAG_GROUP_KEY)
+                pkey_material->key_param_set.key_info |= KEY_INFO_MCAST_KEY;
+            else
+                pkey_material->key_param_set.key_info |= KEY_INFO_UCAST_KEY;
+        }
+        pkey_material->key_param_set.key_info               = wlan_cpu_to_le16(pkey_material->key_param_set.key_info);
+        pkey_material->key_param_set.key_params.wep.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.wep.key, pkey->key_material, pkey->key_len,
+                   MAX_WEP_KEY_SIZE);
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(wep_param_t) + sizeof(pkey_material->action));
+        wifi_d("Set WEP Key");
+        goto done;
+    }
+    if (pkey->key_flags & KEY_FLAG_GROUP_KEY)
+        pkey_material->key_param_set.key_info |= KEY_INFO_MCAST_KEY;
+    else
+        pkey_material->key_param_set.key_info |= KEY_INFO_UCAST_KEY;
+    if (pkey->key_flags & KEY_FLAG_SET_TX_KEY)
+        pkey_material->key_param_set.key_info |= KEY_INFO_TX_KEY | KEY_INFO_RX_KEY;
+    else
+        pkey_material->key_param_set.key_info |= KEY_INFO_RX_KEY;
+    if (pmpriv->bss_mode == MLAN_BSS_MODE_INFRA)
+    {
+        /* Enable default key for WPA/WPA2 */
+        if (!pmpriv->wpa_is_gtk_set)
+            pkey_material->key_param_set.key_info |= KEY_INFO_DEFAULT_KEY;
+    }
+    else
+    {
+        pkey_material->key_param_set.key_info |= KEY_INFO_DEFAULT_KEY;
+        /* Enable unicast bit for WPA-NONE/ADHOC_AES */
+        if ((!pmpriv->sec_info.wpa2_enabled) && (pkey->key_flags & KEY_FLAG_SET_TX_KEY))
+            pkey_material->key_param_set.key_info |= KEY_INFO_UCAST_KEY;
+    }
+    pkey_material->key_param_set.key_info = wlan_cpu_to_le16(pkey_material->key_param_set.key_info);
+    if (pkey->key_flags & KEY_FLAG_GCMP || pkey->key_flags & KEY_FLAG_GCMP_256)
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+        {
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.gcmp.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        }
+        if (pkey->key_flags & KEY_FLAG_GCMP)
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_GCMP;
+        else
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_GCMP_256;
+        pkey_material->key_param_set.key_params.gcmp.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.gcmp.key, pkey->key_material, pkey->key_len,
+                   WPA_GCMP_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(gcmp_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(gcmp_param) + sizeof(pkey_material->action));
+        wifi_d("Set GCMP Key");
+        goto done;
+    }
+    if (pkey->key_flags & KEY_FLAG_CCMP_256)
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+        {
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.ccmp256.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        }
+        pkey_material->key_param_set.key_type                   = KEY_TYPE_ID_CCMP_256;
+        pkey_material->key_param_set.key_params.ccmp256.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.ccmp256.key, pkey->key_material,
+                   pkey->key_len, WPA_CCMP_256_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(ccmp_256_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(ccmp_256_param) + sizeof(pkey_material->action));
+        wifi_d("Set CCMP256 Key");
+        goto done;
+    }
+    if (pkey->key_len == WPA_AES_KEY_LEN && !(pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK))
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.aes.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        pkey_material->key_param_set.key_type               = KEY_TYPE_ID_AES;
+        pkey_material->key_param_set.key_params.aes.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.aes.key, pkey->key_material, pkey->key_len,
+                   WPA_AES_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(aes_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN + sizeof(aes_param) +
+                                     sizeof(pkey_material->action));
+        wifi_d("Set AES Key");
+        goto done;
+    }
+    if (pkey->key_len == WPA_IGTK_KEY_LEN && (pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK))
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.cmac_aes.ipn, pkey->pn, SEQ_MAX_SIZE,
+                       IGTK_PN_SIZE);
+        pkey_material->key_param_set.key_info &= ~(wlan_cpu_to_le16(KEY_INFO_MCAST_KEY));
+        pkey_material->key_param_set.key_info |= wlan_cpu_to_le16(KEY_INFO_AES_MCAST_IGTK);
+        if (pkey->key_flags & KEY_FLAG_GMAC_128)
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_BIP_GMAC_128;
+        else
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_AES_CMAC;
+        pkey_material->key_param_set.key_params.cmac_aes.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.cmac_aes.key, pkey->key_material,
+                   pkey->key_len, CMAC_AES_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(cmac_aes_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(cmac_aes_param) + sizeof(pkey_material->action));
+        if (pkey->key_flags & KEY_FLAG_GMAC_128)
+            wifi_d("Set AES 128 GMAC Key");
+        else
+            wifi_d("Set CMAC AES Key");
+        goto done;
+    }
+    if (pkey->key_len == WPA_IGTK_256_KEY_LEN && (pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK))
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            (void)__memcpy(pmpriv->adapter, pkey_material->key_param_set.key_params.gmac_aes.ipn, pkey->pn,
+                           SEQ_MAX_SIZE);
+        pkey_material->key_param_set.key_info &= ~(wlan_cpu_to_le16(KEY_INFO_MCAST_KEY));
+        pkey_material->key_param_set.key_info |= wlan_cpu_to_le16(KEY_INFO_AES_MCAST_IGTK);
+        pkey_material->key_param_set.key_type                    = KEY_TYPE_ID_BIP_GMAC_256;
+        pkey_material->key_param_set.key_params.gmac_aes.key_len = wlan_cpu_to_le16(pkey->key_len);
+        (void)__memcpy(pmpriv->adapter, pkey_material->key_param_set.key_params.gmac_aes.key, pkey->key_material,
+                       pkey->key_len);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(gmac_aes_256_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(gmac_aes_256_param) + sizeof(pkey_material->action));
+        wifi_d("Set AES 256 GMAC Key");
+        goto done;
+    }
+    if (pkey->key_len == WPA_TKIP_KEY_LEN)
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.tkip.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        pkey_material->key_param_set.key_type                = KEY_TYPE_ID_TKIP;
+        pkey_material->key_param_set.key_params.tkip.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.tkip.key, pkey->key_material, pkey->key_len,
+                   WPA_TKIP_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(tkip_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(tkip_param) + sizeof(pkey_material->action));
+        wifi_d("Set TKIP Key");
+    }
+done:
+    LEAVE();
+    return ret;
+}
+
+#if CONFIG_GTK_REKEY_OFFLOAD
+/**
+ *  @brief This function prepares command of gtk rekey offload
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param cmd_oid      OID: ENABLE or DISABLE
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_cmd_gtk_rekey_offload(
+    pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_u32 cmd_oid, t_void *pdata_buf)
+{
+    HostCmd_DS_GTK_REKEY_PARAMS *rekey = &cmd->params.gtk_rekey;
+    mlan_ds_misc_gtk_rekey_data *data  = (mlan_ds_misc_gtk_rekey_data *)pdata_buf;
+    t_u64 rekey_ctr;
+
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_CONFIG_GTK_REKEY_OFFLOAD_CFG);
+    cmd->size    = wlan_cpu_to_le16(sizeof(*rekey) + S_DS_GEN);
+
+    rekey->action = wlan_cpu_to_le16(cmd_action);
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        memcpy_ext(pmpriv->adapter, rekey->kek, data->kek, MLAN_KEK_LEN, MLAN_KEK_LEN);
+        memcpy_ext(pmpriv->adapter, rekey->kck, data->kck, MLAN_KCK_LEN, MLAN_KCK_LEN);
+        rekey_ctr              = wlan_le64_to_cpu(swap_byte_64(*(t_u64 *)data->replay_ctr));
+        rekey->replay_ctr_low  = wlan_cpu_to_le32((t_u32)rekey_ctr);
+        rekey->replay_ctr_high = wlan_cpu_to_le32((t_u64)rekey_ctr >> 32);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/**
+ *  @brief This function prepares command of supplicant pmk
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_cmd_802_11_supplicant_pmk(IN pmlan_private pmpriv,
+                                                  IN HostCmd_DS_COMMAND *cmd,
+                                                  IN t_u16 cmd_action,
+                                                  IN t_void *pdata_buf)
+{
+    MrvlIEtypes_PMK_t *ppmk_tlv                        = MNULL;
+    MrvlIEtypes_Passphrase_t *ppassphrase_tlv          = MNULL;
+    MrvlIEtypes_Password_t *ppassword_tlv              = MNULL;
+    MrvlIEtypes_SsIdParamSet_t *pssid_tlv              = MNULL;
+    MrvlIEtypes_Bssid_t *pbssid_tlv                    = MNULL;
+    HostCmd_DS_802_11_SUPPLICANT_PMK *pesupplicant_psk = &cmd->params.esupplicant_psk;
+    t_u8 *ptlv_buffer                                  = (t_u8 *)pesupplicant_psk->tlv_buffer;
+    mlan_ds_passphrase *psk                            = (mlan_ds_passphrase *)pdata_buf;
+    t_u8 zero_mac[]                                    = {0, 0, 0, 0, 0, 0};
+
+    ENTER();
+    /*
+     * Parse the rest of the buf here
+     *      1)  <ssid="valid ssid"> - This will get the passphrase, AKMP
+     *          for specified ssid, if none specified then it will get all.
+     *          Eg: iwpriv <mlanX> passphrase 0:ssid=nxp
+     *      2)  <psk="psk">:<passphrase="passphare">:<bssid="00:50:43:ef:23:f3">
+     *          <ssid="valid ssid"> - passphrase and psk cannot be provided to
+     *          the same SSID, Takes one SSID at a time, If ssid= is present
+     *          the it should contain a passphrase or psk. If no arguments are
+     *          provided then AKMP=802.1x, and passphrase should be provided
+     *          after association.
+     *          End of each parameter should be followed by a ':'(except for the
+     *          last parameter) as the delimiter. If ':' has to be used in
+     *          an SSID then a '/' should be preceded to ':' as a escape.
+     *          Eg:iwpriv <mlanX> passphrase
+     *                    "1:ssid=mrvl AP:psk=abcdefgh:bssid=00:50:43:ef:23:f3"
+     *          iwpriv <mlanX> passphrase
+     *                 "1:ssid=mrvl/: AP:psk=abcdefgd:bssid=00:50:43:ef:23:f3"
+     *          iwpriv <mlanX> passphrase "1:ssid=mrvlAP:psk=abcdefgd"
+     *      3)  <ssid="valid ssid"> - This will clear the passphrase
+     *          for specified ssid, if none specified then it will clear all.
+     *          Eg: iwpriv <mlanX> passphrase 2:ssid=nxp
+     */
+
+    /* -1 is for t_u8 TlvBuffer[1] as this should not be included */
+    cmd->size = sizeof(HostCmd_DS_802_11_SUPPLICANT_PMK) + S_DS_GEN - 1U;
+    if (psk->ssid.ssid_len != 0U)
+    {
+        pssid_tlv              = (MrvlIEtypes_SsIdParamSet_t *)(void *)ptlv_buffer;
+        pssid_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_SSID);
+        pssid_tlv->header.len  = (t_u16)MIN(MLAN_MAX_SSID_LENGTH, psk->ssid.ssid_len);
+        (void)__memcpy(pmpriv->adapter, (char *)pssid_tlv->ssid, psk->ssid.ssid,
+                       MIN(MLAN_MAX_SSID_LENGTH, psk->ssid.ssid_len));
+        ptlv_buffer += (pssid_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        cmd->size += (t_u16)(pssid_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        pssid_tlv->header.len = wlan_cpu_to_le16(pssid_tlv->header.len);
+    }
+    if (__memcmp(pmpriv->adapter, (t_u8 *)&psk->bssid, zero_mac, sizeof(zero_mac)) != 0)
+    {
+        pbssid_tlv              = (MrvlIEtypes_Bssid_t *)(void *)ptlv_buffer;
+        pbssid_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_BSSID);
+        pbssid_tlv->header.len  = MLAN_MAC_ADDR_LENGTH;
+        (void)__memcpy(pmpriv->adapter, pbssid_tlv->bssid, (t_u8 *)&psk->bssid, MLAN_MAC_ADDR_LENGTH);
+        ptlv_buffer += (pbssid_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        cmd->size += (t_u16)(pbssid_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        pbssid_tlv->header.len = wlan_cpu_to_le16(pbssid_tlv->header.len);
+    }
+    if (psk->psk_type == MLAN_PSK_PASSPHRASE)
+    {
+        ppassphrase_tlv              = (MrvlIEtypes_Passphrase_t *)(void *)ptlv_buffer;
+        ppassphrase_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_PASSPHRASE);
+        ppassphrase_tlv->header.len  = (t_u16)MIN(MLAN_MAX_PASSPHRASE_LENGTH, psk->psk.passphrase.passphrase_len);
+        (void)__memcpy(pmpriv->adapter, ppassphrase_tlv->passphrase, psk->psk.passphrase.passphrase,
+                       MIN(MLAN_MAX_PASSPHRASE_LENGTH, psk->psk.passphrase.passphrase_len));
+        ptlv_buffer += (ppassphrase_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        cmd->size += (t_u16)(ppassphrase_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        ppassphrase_tlv->header.len = wlan_cpu_to_le16(ppassphrase_tlv->header.len);
+    }
+    if (psk->psk_type == MLAN_PSK_PASSWORD)
+    {
+        ppassword_tlv              = (MrvlIEtypes_Password_t *)(void *)ptlv_buffer;
+        ppassword_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_WPA3_SAE_PASSWORD);
+        ppassword_tlv->header.len  = (t_u16)MIN(MLAN_MAX_PASSWORD_LENGTH, psk->password.password_len);
+        (void)__memcpy(pmpriv->adapter, ppassword_tlv->password, psk->password.password,
+                       MIN(MLAN_MAX_PASSWORD_LENGTH, psk->password.password_len));
+        ptlv_buffer += (ppassword_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        cmd->size += (t_u16)(ppassword_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        ppassword_tlv->header.len = wlan_cpu_to_le16(ppassword_tlv->header.len);
+    }
+    if (psk->psk_type == MLAN_PSK_PMK)
+    {
+        ppmk_tlv              = (MrvlIEtypes_PMK_t *)(void *)ptlv_buffer;
+        ppmk_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_PMK);
+        ppmk_tlv->header.len  = MLAN_MAX_KEY_LENGTH;
+        (void)__memcpy(pmpriv->adapter, ppmk_tlv->pmk, psk->psk.pmk.pmk, MLAN_MAX_KEY_LENGTH);
+        ptlv_buffer += (ppmk_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        cmd->size += (t_u16)(ppmk_tlv->header.len + sizeof(MrvlIEtypesHeader_t));
+        ppmk_tlv->header.len = wlan_cpu_to_le16(ppmk_tlv->header.len);
+    }
+    if ((cmd_action == HostCmd_ACT_GEN_SET) &&
+        (((pssid_tlv != MNULL) || (pbssid_tlv != MNULL)) &&
+         ((ppmk_tlv == MNULL) && (ppassphrase_tlv == MNULL) && (ppassword_tlv == MNULL))))
+    {
+        PRINTM(MERROR, "Invalid case,ssid/bssid present without pmk or passphrase or password\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    cmd->command                   = wlan_cpu_to_le16(HostCmd_CMD_SUPPLICANT_PMK);
+    pesupplicant_psk->action       = wlan_cpu_to_le16(cmd_action);
+    pesupplicant_psk->cache_result = 0;
+    cmd->size                      = wlan_cpu_to_le16(cmd->size);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+/**
+ *  @brief This function prepares command of rf_channel.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_802_11_rf_channel(IN pmlan_private pmpriv,
+                                              IN HostCmd_DS_COMMAND *cmd,
+                                              IN t_u16 cmd_action,
+                                              IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_RF_CHANNEL *prf_chan = &cmd->params.rf_channel;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RF_CHANNEL);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_RF_CHANNEL) + S_DS_GEN);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        if ((pmpriv->adapter->adhoc_start_band & BAND_A) || (pmpriv->adapter->adhoc_start_band & BAND_AN))
+        {
+            prf_chan->rf_type = HostCmd_SCAN_RADIO_TYPE_A;
+        }
+        SET_SECONDARYCHAN(prf_chan->rf_type, pmpriv->adapter->chan_bandwidth);
+        prf_chan->rf_type         = wlan_cpu_to_le16(prf_chan->rf_type);
+        prf_chan->current_channel = wlan_cpu_to_le16(*((t_u16 *)pdata_buf));
+    }
+    prf_chan->action = wlan_cpu_to_le16(cmd_action);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+/**
+ *  @brief This function prepares command of mgmt IE list.
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf	A pointer to data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_mgmt_ie_list(IN pmlan_private pmpriv,
+                                         IN HostCmd_DS_COMMAND *cmd,
+                                         IN t_u16 cmd_action,
+                                         IN t_void *pdata_buf)
+{
+    t_u16 req_len = 0, travel_len = 0;
+    custom_ie *cptr                            = MNULL;
+    mlan_ds_misc_custom_ie *cust_ie            = MNULL;
+    HostCmd_DS_MGMT_IE_LIST_CFG *pmgmt_ie_list = &(cmd->params.mgmt_ie_list);
+
+    ENTER();
+
+    cmd->command          = wlan_cpu_to_le16(HostCmd_CMD_MGMT_IE_LIST);
+    cmd->size             = sizeof(HostCmd_DS_MGMT_IE_LIST_CFG) + S_DS_GEN;
+    cmd->result           = 0;
+    pmgmt_ie_list->action = wlan_cpu_to_le16(cmd_action);
+
+    cust_ie                        = (mlan_ds_misc_custom_ie *)pdata_buf;
+    pmgmt_ie_list->ds_mgmt_ie.type = wlan_cpu_to_le16(cust_ie->type);
+    pmgmt_ie_list->ds_mgmt_ie.len  = wlan_cpu_to_le16(cust_ie->len);
+
+    if ((pmgmt_ie_list != MNULL) && (cust_ie != MNULL))
+    {
+        req_len    = cust_ie->len;
+        travel_len = 0;
+        /* conversion for index, mask, len */
+        if (req_len == sizeof(t_u16))
+        {
+            cust_ie->ie_data_list[0].ie_index = wlan_cpu_to_le16(cust_ie->ie_data_list[0].ie_index);
+        }
+
+        while (req_len > sizeof(t_u16))
+        {
+            cptr = (custom_ie *)(void *)(((t_u8 *)cust_ie->ie_data_list) + travel_len);
+            travel_len += (t_u16)(cptr->ie_length + sizeof(custom_ie) - MAX_IE_SIZE);
+            req_len -= (t_u16)(cptr->ie_length + sizeof(custom_ie) - MAX_IE_SIZE);
+            cptr->ie_index          = wlan_cpu_to_le16(cptr->ie_index);
+            cptr->mgmt_subtype_mask = wlan_cpu_to_le16(cptr->mgmt_subtype_mask);
+            cptr->ie_length         = wlan_cpu_to_le16(cptr->ie_length);
+        }
+        if (cust_ie->len != 0U)
+        {
+            (void)__memcpy(pmpriv->adapter, pmgmt_ie_list->ds_mgmt_ie.ie_data_list, cust_ie->ie_data_list,
+                           cust_ie->len);
+        }
+    }
+
+    cmd->size -= (MAX_MGMT_IE_INDEX_TO_FW * sizeof(custom_ie)) + sizeof(tlvbuf_max_mgmt_ie);
+    cmd->size += cust_ie->len;
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+       /**
+        *  @brief This function prepares command of reg_access.
+        *
+        *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+        *  @param cmd_action   the action: GET or SET
+        *  @param pdata_buf    A pointer to data buffer
+        *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+        */
+/* static */ mlan_status wlan_cmd_reg_access(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf)
+{
+    mlan_ds_reg_rw *reg_rw;
+    bool invalid_hostcmd = MFALSE;
+
+    ENTER();
+
+    reg_rw = (mlan_ds_reg_rw *)pdata_buf;
+    switch (cmd->command)
+    {
+        case HostCmd_CMD_MAC_REG_ACCESS:
+        {
+            HostCmd_DS_MAC_REG_ACCESS *mac_reg;
+            cmd->size       = wlan_cpu_to_le16(sizeof(HostCmd_DS_MAC_REG_ACCESS) + S_DS_GEN);
+            mac_reg         = (HostCmd_DS_MAC_REG_ACCESS *)&cmd->params.mac_reg;
+            mac_reg->action = wlan_cpu_to_le16(cmd_action);
+            mac_reg->offset = wlan_cpu_to_le16((t_u16)reg_rw->offset);
+            mac_reg->value  = wlan_cpu_to_le32(reg_rw->value);
+            break;
+        }
+        case HostCmd_CMD_BBP_REG_ACCESS:
+        {
+            HostCmd_DS_BBP_REG_ACCESS *bbp_reg;
+            cmd->size       = wlan_cpu_to_le16(sizeof(HostCmd_DS_BBP_REG_ACCESS) + S_DS_GEN);
+            bbp_reg         = (HostCmd_DS_BBP_REG_ACCESS *)&cmd->params.bbp_reg;
+            bbp_reg->action = wlan_cpu_to_le16(cmd_action);
+            bbp_reg->offset = wlan_cpu_to_le16((t_u16)reg_rw->offset);
+            bbp_reg->value  = (t_u8)reg_rw->value;
+            break;
+        }
+        case HostCmd_CMD_RF_REG_ACCESS:
+        {
+            HostCmd_DS_RF_REG_ACCESS *rf_reg;
+            cmd->size      = wlan_cpu_to_le16(sizeof(HostCmd_DS_RF_REG_ACCESS) + S_DS_GEN);
+            rf_reg         = (HostCmd_DS_RF_REG_ACCESS *)&cmd->params.rf_reg;
+            rf_reg->action = wlan_cpu_to_le16(cmd_action);
+            rf_reg->offset = wlan_cpu_to_le16((t_u16)reg_rw->offset);
+            rf_reg->value  = (t_u8)reg_rw->value;
+            break;
+        }
+        case HostCmd_CMD_CAU_REG_ACCESS:
+        {
+            HostCmd_DS_RF_REG_ACCESS *cau_reg;
+            cmd->size       = wlan_cpu_to_le16(sizeof(HostCmd_DS_RF_REG_ACCESS) + S_DS_GEN);
+            cau_reg         = (HostCmd_DS_RF_REG_ACCESS *)&cmd->params.rf_reg;
+            cau_reg->action = wlan_cpu_to_le16(cmd_action);
+            cau_reg->offset = wlan_cpu_to_le16((t_u16)reg_rw->offset);
+            cau_reg->value  = (t_u8)reg_rw->value;
+            break;
+        }
+        case HostCmd_CMD_802_11_EEPROM_ACCESS:
+        {
+            mlan_ds_read_eeprom *rd_eeprom              = (mlan_ds_read_eeprom *)pdata_buf;
+            HostCmd_DS_802_11_EEPROM_ACCESS *cmd_eeprom = (HostCmd_DS_802_11_EEPROM_ACCESS *)&cmd->params.eeprom;
+            cmd->size              = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_EEPROM_ACCESS) + S_DS_GEN);
+            cmd_eeprom->action     = wlan_cpu_to_le16(cmd_action);
+            cmd_eeprom->offset     = wlan_cpu_to_le16(rd_eeprom->offset);
+            cmd_eeprom->byte_count = wlan_cpu_to_le16(rd_eeprom->byte_count);
+            cmd_eeprom->value      = 0;
+            break;
+        }
+        default:
+            invalid_hostcmd = MTRUE;
+            break;
+    }
+    if (invalid_hostcmd == MTRUE)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    cmd->command = wlan_cpu_to_le16(cmd->command);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of mem_access.
+ *
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_mem_access(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf)
+{
+    mlan_ds_mem_rw *mem_rw            = (mlan_ds_mem_rw *)pdata_buf;
+    HostCmd_DS_MEM_ACCESS *mem_access = (HostCmd_DS_MEM_ACCESS *)&cmd->params.mem;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_MEM_ACCESS);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_MEM_ACCESS) + S_DS_GEN);
+
+    mem_access->action = wlan_cpu_to_le16(cmd_action);
+    mem_access->addr   = wlan_cpu_to_le32(mem_rw->addr);
+    mem_access->value  = wlan_cpu_to_le32(mem_rw->value);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of auto_reconnect
+ *
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_auto_reconnect(IN HostCmd_DS_COMMAND *cmd, IN t_u16 cmd_action, IN t_void *pdata_buf)
+{
+    mlan_ds_auto_reconnect *auto_reconnect = (mlan_ds_auto_reconnect *)pdata_buf;
+    HostCmd_DS_AUTO_RECONNECT *auto_reconn = (HostCmd_DS_AUTO_RECONNECT *)&cmd->params.auto_reconnect;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_AUTO_RECONNECT);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_AUTO_RECONNECT) + S_DS_GEN);
+
+    auto_reconn->action             = wlan_cpu_to_le16(cmd_action);
+    auto_reconn->reconnect_counter  = auto_reconnect->reconnect_counter;
+    auto_reconn->reconnect_interval = auto_reconnect->reconnect_interval;
+    auto_reconn->flags              = wlan_cpu_to_le16(auto_reconnect->flags);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of rx management indication
+ *
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_rx_mgmt_indication(IN pmlan_private pmpriv,
+                                        IN HostCmd_DS_COMMAND *cmd,
+                                        IN t_u16 cmd_action,
+                                        IN t_void *pdata_buf)
+{
+    mlan_ds_rx_mgmt_indication *rx_mgmt_indication = (mlan_ds_rx_mgmt_indication *)pdata_buf;
+    HostCmd_DS_RX_MGMT_IND *rx_mgmt                = (HostCmd_DS_RX_MGMT_IND *)&cmd->params.rx_mgmt_ind;
+
+    ENTER();
+
+    /* Set passthru mask for mgmt frame */
+    pmpriv->mgmt_frame_passthru_mask = rx_mgmt_indication->mgmt_subtype_mask;
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_RX_MGMT_IND);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_RX_MGMT_IND) + S_DS_GEN);
+
+    rx_mgmt->action            = wlan_cpu_to_le16(cmd_action);
+    rx_mgmt->mgmt_subtype_mask = wlan_cpu_to_le32(rx_mgmt_indication->mgmt_subtype_mask);
+
+    rx_mgmt->data_subtype_mask = 0;
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+
+#if (CONFIG_SUBSCRIBE_EVENT_SUPPORT) || (CONFIG_ROAMING)
+int wlan_parse_getdata(HostCmd_DS_COMMAND *resp, mlan_ds_subscribe_evt *sub_evt)
+{
+    if (!resp || !sub_evt)
+        return WM_E_INVAL;
+    HostCmd_DS_SUBSCRIBE_EVENT *evt                     = &resp->params.subscribe_event;
+    int tyhdsize                                        = sizeof(MrvlIEtypesHeader_t);
+    t_u8 *tlv0                                          = (t_u8 *)resp + sizeof(HostCmd_DS_SUBSCRIBE_EVENT) + S_DS_GEN;
+    t_u8 *tlv                                           = tlv0;
+    MrvlIEtypes_BeaconLowRssiThreshold_t *rssi_low      = MNULL;
+    MrvlIEtypes_BeaconLowSnrThreshold_t *snr_low        = MNULL;
+    MrvlIEtypes_FailureCount_t *fail_count              = MNULL;
+    MrvlIEtypes_BeaconsMissed_t *beacon_missed          = MNULL;
+    MrvlIEtypes_BeaconHighRssiThreshold_t *rssi_high    = MNULL;
+    MrvlIEtypes_BeaconHighSnrThreshold_t *snr_high      = MNULL;
+    MrvlIEtypes_DataLowRssiThreshold_t *data_rssi_low   = MNULL;
+    MrvlIEtypes_DataLowSnrThreshold_t *data_snr_low     = MNULL;
+    MrvlIEtypes_DataHighRssiThreshold_t *data_rssi_high = MNULL;
+    MrvlIEtypes_DataHighSnrThreshold_t *data_snr_high   = MNULL;
+    MrvlIEtypes_LinkQualityThreshold_t *link_quality    = MNULL;
+    MrvlIETypes_PreBeaconMissed_t *pre_bcn_missed       = MNULL;
+
+    sub_evt->evt_action = wlan_le16_to_cpu(evt->action);
+    sub_evt->evt_bitmap = wlan_le16_to_cpu(evt->event_bitmap);
+    /*rssi_low*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    rssi_low               = (MrvlIEtypes_BeaconLowRssiThreshold_t *)tlv;
+    sub_evt->low_rssi      = rssi_low->value;
+    sub_evt->low_rssi_freq = rssi_low->frequency;
+    tlv += rssi_low->header.len + tyhdsize;
+
+    /*snr_low*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    snr_low               = (MrvlIEtypes_BeaconLowSnrThreshold_t *)tlv;
+    sub_evt->low_snr      = snr_low->value;
+    sub_evt->low_snr_freq = snr_low->frequency;
+    tlv += sizeof(MrvlIEtypes_BeaconLowSnrThreshold_t);
+
+    /*max fail*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    fail_count                  = (MrvlIEtypes_FailureCount_t *)tlv;
+    sub_evt->failure_count      = fail_count->value;
+    sub_evt->failure_count_freq = fail_count->frequency;
+    tlv += sizeof(MrvlIEtypes_FailureCount_t);
+
+    /*beacon miss*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    beacon_missed             = (MrvlIEtypes_BeaconsMissed_t *)tlv;
+    sub_evt->beacon_miss      = beacon_missed->value;
+    sub_evt->beacon_miss_freq = beacon_missed->frequency;
+    tlv += sizeof(MrvlIEtypes_BeaconsMissed_t);
+
+    /*rssi high*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    rssi_high               = (MrvlIEtypes_BeaconHighRssiThreshold_t *)tlv;
+    sub_evt->high_rssi      = rssi_high->value;
+    sub_evt->high_rssi_freq = rssi_high->frequency;
+    tlv += sizeof(MrvlIEtypes_BeaconHighRssiThreshold_t);
+
+    /*snr high*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    snr_high               = (MrvlIEtypes_BeaconHighSnrThreshold_t *)tlv;
+    sub_evt->high_snr      = snr_high->value;
+    sub_evt->high_snr_freq = snr_high->frequency;
+    tlv += sizeof(MrvlIEtypes_BeaconHighSnrThreshold_t);
+
+    /*data rssi low*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    data_rssi_low               = (MrvlIEtypes_DataLowRssiThreshold_t *)tlv;
+    sub_evt->data_low_rssi      = data_rssi_low->value;
+    sub_evt->data_low_rssi_freq = data_rssi_low->frequency;
+    tlv += sizeof(MrvlIEtypes_DataLowRssiThreshold_t);
+
+    /*data snr low*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    data_snr_low               = (MrvlIEtypes_DataLowSnrThreshold_t *)tlv;
+    sub_evt->data_low_snr      = data_snr_low->value;
+    sub_evt->data_low_snr_freq = data_snr_low->frequency;
+    tlv += sizeof(MrvlIEtypes_DataLowSnrThreshold_t);
+
+    /*data rssi high*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    data_rssi_high               = (MrvlIEtypes_DataHighRssiThreshold_t *)tlv;
+    sub_evt->data_high_rssi      = data_rssi_high->value;
+    sub_evt->data_high_rssi_freq = data_rssi_high->frequency;
+    tlv += sizeof(MrvlIEtypes_DataHighRssiThreshold_t);
+
+    /*data snr high*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    data_snr_high               = (MrvlIEtypes_DataHighSnrThreshold_t *)tlv;
+    sub_evt->data_high_snr      = data_snr_high->value;
+    sub_evt->data_high_snr_freq = data_snr_high->frequency;
+    tlv += sizeof(MrvlIEtypes_DataHighSnrThreshold_t);
+
+    /*link quality*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    link_quality                   = (MrvlIEtypes_LinkQualityThreshold_t *)tlv;
+    sub_evt->link_snr              = wlan_le16_to_cpu(link_quality->link_snr);
+    sub_evt->link_snr_freq         = wlan_le16_to_cpu(link_quality->link_snr_freq);
+    sub_evt->link_rate             = wlan_le16_to_cpu(link_quality->link_rate);
+    sub_evt->link_rate_freq        = wlan_le16_to_cpu(link_quality->link_rate_freq);
+    sub_evt->link_tx_latency       = wlan_le16_to_cpu(link_quality->link_tx_latency);
+    sub_evt->link_tx_lantency_freq = wlan_le16_to_cpu(link_quality->link_tx_lantency_freq);
+    tlv += link_quality->header.len + tyhdsize;
+
+    /*pre beacon lost*/
+    if ((tlv - tlv0) > resp->size)
+        return WM_E_IO;
+    pre_bcn_missed           = (MrvlIETypes_PreBeaconMissed_t *)tlv;
+    sub_evt->pre_beacon_miss = pre_bcn_missed->value;
+    tlv += tyhdsize + pre_bcn_missed->header.len;
+
+    return WM_SUCCESS;
+}
+#endif
+
+/**
+ *  @brief This function prepares command of subscribe event.
+ *
+ *  @param pmpriv    	A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_subscribe_event(IN pmlan_private pmpriv,
+                                     IN HostCmd_DS_COMMAND *cmd,
+                                     IN t_u16 cmd_action,
+                                     IN t_void *pdata_buf)
+{
+    mlan_ds_subscribe_evt *sub_evt                      = (mlan_ds_subscribe_evt *)pdata_buf;
+    HostCmd_DS_SUBSCRIBE_EVENT *evt                     = (HostCmd_DS_SUBSCRIBE_EVENT *)&cmd->params.subscribe_event;
+    t_u16 cmd_size                                      = 0;
+    t_u8 *tlv                                           = MNULL;
+    MrvlIEtypes_BeaconLowRssiThreshold_t *rssi_low      = MNULL;
+    MrvlIEtypes_BeaconLowSnrThreshold_t *snr_low        = MNULL;
+    MrvlIEtypes_FailureCount_t *fail_count              = MNULL;
+    MrvlIEtypes_BeaconsMissed_t *beacon_missed          = MNULL;
+    MrvlIEtypes_BeaconHighRssiThreshold_t *rssi_high    = MNULL;
+    MrvlIEtypes_BeaconHighSnrThreshold_t *snr_high      = MNULL;
+    MrvlIEtypes_DataLowRssiThreshold_t *data_rssi_low   = MNULL;
+    MrvlIEtypes_DataLowSnrThreshold_t *data_snr_low     = MNULL;
+    MrvlIEtypes_DataHighRssiThreshold_t *data_rssi_high = MNULL;
+    MrvlIEtypes_DataHighSnrThreshold_t *data_snr_high   = MNULL;
+    MrvlIEtypes_LinkQualityThreshold_t *link_quality    = MNULL;
+    MrvlIETypes_PreBeaconMissed_t *pre_bcn_missed       = MNULL;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SUBSCRIBE_EVENT);
+    evt->action  = wlan_cpu_to_le16(cmd_action);
+    cmd_size     = sizeof(HostCmd_DS_SUBSCRIBE_EVENT) + S_DS_GEN;
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+        goto done;
+    if (sub_evt->evt_action == SUBSCRIBE_EVT_ACT_BITWISE_CLR)
+    {
+        evt->action       = wlan_cpu_to_le16(SUBSCRIBE_EVT_ACT_BITWISE_CLR);
+        evt->event_bitmap = wlan_cpu_to_le16(sub_evt->evt_bitmap);
+        goto done;
+    }
+
+#define HostCmd_ACT_BITWISE_SET 0x02
+    evt->action       = wlan_cpu_to_le16(HostCmd_ACT_BITWISE_SET);
+    evt->event_bitmap = wlan_cpu_to_le16(sub_evt->evt_bitmap);
+    tlv               = (t_u8 *)cmd + cmd_size;
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_RSSI_LOW)
+    {
+        rssi_low              = (MrvlIEtypes_BeaconLowRssiThreshold_t *)tlv;
+        rssi_low->header.type = wlan_cpu_to_le16(TLV_TYPE_RSSI_LOW);
+        rssi_low->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        rssi_low->value     = sub_evt->low_rssi;
+        rssi_low->frequency = sub_evt->low_rssi_freq;
+        tlv += sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_BeaconLowRssiThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_SNR_LOW)
+    {
+        snr_low              = (MrvlIEtypes_BeaconLowSnrThreshold_t *)tlv;
+        snr_low->header.type = wlan_cpu_to_le16(TLV_TYPE_SNR_LOW);
+        snr_low->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_BeaconLowSnrThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        snr_low->value     = sub_evt->low_snr;
+        snr_low->frequency = sub_evt->low_snr_freq;
+        tlv += sizeof(MrvlIEtypes_BeaconLowSnrThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_BeaconLowSnrThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_MAX_FAIL)
+    {
+        fail_count              = (MrvlIEtypes_FailureCount_t *)tlv;
+        fail_count->header.type = wlan_cpu_to_le16(TLV_TYPE_FAILCOUNT);
+        fail_count->header.len  = wlan_cpu_to_le16(sizeof(MrvlIEtypes_FailureCount_t) - sizeof(MrvlIEtypesHeader_t));
+        fail_count->value       = sub_evt->failure_count;
+        fail_count->frequency   = sub_evt->failure_count_freq;
+        tlv += sizeof(MrvlIEtypes_FailureCount_t);
+        cmd_size += sizeof(MrvlIEtypes_FailureCount_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_BEACON_MISSED)
+    {
+        beacon_missed              = (MrvlIEtypes_BeaconsMissed_t *)tlv;
+        beacon_missed->header.type = wlan_cpu_to_le16(TLV_TYPE_BCNMISS);
+        beacon_missed->header.len = wlan_cpu_to_le16(sizeof(MrvlIEtypes_BeaconsMissed_t) - sizeof(MrvlIEtypesHeader_t));
+        beacon_missed->value      = sub_evt->beacon_miss;
+        beacon_missed->frequency  = sub_evt->beacon_miss_freq;
+        tlv += sizeof(MrvlIEtypes_BeaconsMissed_t);
+        cmd_size += sizeof(MrvlIEtypes_BeaconsMissed_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_RSSI_HIGH)
+    {
+        rssi_high              = (MrvlIEtypes_BeaconHighRssiThreshold_t *)tlv;
+        rssi_high->header.type = wlan_cpu_to_le16(TLV_TYPE_RSSI_HIGH);
+        rssi_high->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_BeaconHighRssiThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        rssi_high->value     = sub_evt->high_rssi;
+        rssi_high->frequency = sub_evt->high_rssi_freq;
+        tlv += sizeof(MrvlIEtypes_BeaconHighRssiThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_BeaconHighRssiThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_SNR_HIGH)
+    {
+        snr_high              = (MrvlIEtypes_BeaconHighSnrThreshold_t *)tlv;
+        snr_high->header.type = wlan_cpu_to_le16(TLV_TYPE_SNR_HIGH);
+        snr_high->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_BeaconHighSnrThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        snr_high->value     = sub_evt->high_snr;
+        snr_high->frequency = sub_evt->high_snr_freq;
+        tlv += sizeof(MrvlIEtypes_BeaconHighSnrThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_BeaconHighSnrThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_DATA_RSSI_LOW)
+    {
+        data_rssi_low              = (MrvlIEtypes_DataLowRssiThreshold_t *)tlv;
+        data_rssi_low->header.type = wlan_cpu_to_le16(TLV_TYPE_RSSI_LOW_DATA);
+        data_rssi_low->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_DataLowRssiThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        data_rssi_low->value     = sub_evt->data_low_rssi;
+        data_rssi_low->frequency = sub_evt->data_low_rssi_freq;
+        tlv += sizeof(MrvlIEtypes_DataLowRssiThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_DataLowRssiThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_DATA_SNR_LOW)
+    {
+        data_snr_low              = (MrvlIEtypes_DataLowSnrThreshold_t *)tlv;
+        data_snr_low->header.type = wlan_cpu_to_le16(TLV_TYPE_SNR_LOW_DATA);
+        data_snr_low->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_DataLowSnrThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        data_snr_low->value     = sub_evt->data_low_snr;
+        data_snr_low->frequency = sub_evt->data_low_snr_freq;
+        tlv += sizeof(MrvlIEtypes_DataLowSnrThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_DataLowSnrThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_DATA_RSSI_HIGH)
+    {
+        data_rssi_high              = (MrvlIEtypes_DataHighRssiThreshold_t *)tlv;
+        data_rssi_high->header.type = wlan_cpu_to_le16(TLV_TYPE_RSSI_HIGH_DATA);
+        data_rssi_high->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_DataHighRssiThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        data_rssi_high->value     = sub_evt->data_high_rssi;
+        data_rssi_high->frequency = sub_evt->data_high_rssi_freq;
+        tlv += sizeof(MrvlIEtypes_DataHighRssiThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_DataHighRssiThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_DATA_SNR_HIGH)
+    {
+        data_snr_high              = (MrvlIEtypes_DataHighSnrThreshold_t *)tlv;
+        data_snr_high->header.type = wlan_cpu_to_le16(TLV_TYPE_SNR_HIGH_DATA);
+        data_snr_high->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_DataHighSnrThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        data_snr_high->value     = sub_evt->data_high_snr;
+        data_snr_high->frequency = sub_evt->data_high_snr_freq;
+        tlv += sizeof(MrvlIEtypes_DataHighSnrThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_DataHighSnrThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_LINK_QUALITY)
+    {
+        link_quality              = (MrvlIEtypes_LinkQualityThreshold_t *)tlv;
+        link_quality->header.type = wlan_cpu_to_le16(TLV_TYPE_LINK_QUALITY);
+        link_quality->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIEtypes_LinkQualityThreshold_t) - sizeof(MrvlIEtypesHeader_t));
+        link_quality->link_snr              = wlan_cpu_to_le16(sub_evt->link_snr);
+        link_quality->link_snr_freq         = wlan_cpu_to_le16(sub_evt->link_snr_freq);
+        link_quality->link_rate             = wlan_cpu_to_le16(sub_evt->link_rate);
+        link_quality->link_rate_freq        = wlan_cpu_to_le16(sub_evt->link_rate_freq);
+        link_quality->link_tx_latency       = wlan_cpu_to_le16(sub_evt->link_tx_latency);
+        link_quality->link_tx_lantency_freq = wlan_cpu_to_le16(sub_evt->link_tx_lantency_freq);
+        tlv += sizeof(MrvlIEtypes_LinkQualityThreshold_t);
+        cmd_size += sizeof(MrvlIEtypes_LinkQualityThreshold_t);
+    }
+    if (sub_evt->evt_bitmap & SUBSCRIBE_EVT_PRE_BEACON_LOST)
+    {
+        pre_bcn_missed              = (MrvlIETypes_PreBeaconMissed_t *)tlv;
+        pre_bcn_missed->header.type = wlan_cpu_to_le16(TLV_TYPE_PRE_BCNMISS);
+        pre_bcn_missed->header.len =
+            wlan_cpu_to_le16(sizeof(MrvlIETypes_PreBeaconMissed_t) - sizeof(MrvlIEtypesHeader_t));
+        pre_bcn_missed->value     = sub_evt->pre_beacon_miss;
+        pre_bcn_missed->frequency = 0;
+        tlv += sizeof(MrvlIETypes_PreBeaconMissed_t);
+        cmd_size += sizeof(MrvlIETypes_PreBeaconMissed_t);
+    }
+done:
+    cmd->size = wlan_cpu_to_le16(cmd_size);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of OTP user data.
+ *
+ *  @param pmpriv    	A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_otp_user_data(IN pmlan_private pmpriv,
+                                          IN HostCmd_DS_COMMAND *cmd,
+                                          IN t_u16 cmd_action,
+                                          IN t_void *pdata_buf)
+{
+    mlan_ds_misc_otp_user_data *user_data   = (mlan_ds_misc_otp_user_data *)pdata_buf;
+    HostCmd_DS_OTP_USER_DATA *cmd_user_data = (HostCmd_DS_OTP_USER_DATA *)&cmd->params.otp_user_data;
+    t_u16 cmd_size                          = 0;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_OTP_READ_USER_DATA);
+    cmd_size     = sizeof(HostCmd_DS_OTP_USER_DATA) + S_DS_GEN - 1U;
+
+    cmd_user_data->action           = wlan_cpu_to_le16(cmd_action);
+    cmd_user_data->reserved         = 0;
+    cmd_user_data->user_data_length = wlan_cpu_to_le16(user_data->user_data_length);
+    /* wmsdk: below change is added in order to count user_data_length size
+     * for SET/Write operation only, in case GET/Read it is not required
+     * (SDIO cmd size remains same).
+     */
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        cmd_size += user_data->user_data_length;
+    }
+    cmd->size = wlan_cpu_to_le16(cmd_size);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+/**
+ *  @brief This function handles the command response of Tx ampdu prot mode
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param pdata_buf    A pointer to command information buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_tx_ampdu_prot_mode(IN pmlan_private pmpriv,
+                                               IN HostCmd_DS_COMMAND *cmd,
+                                               IN t_u16 cmd_action,
+                                               IN t_void *pdata_buf)
+{
+    HostCmd_DS_CMD_TX_AMPDU_PROT_MODE *prot_mode = &cmd->params.tx_ampdu_prot_mode;
+    tx_ampdu_prot_mode_para *para                = (tx_ampdu_prot_mode_para *)pdata_buf;
+
+    ENTER();
+
+    cmd->command      = wlan_cpu_to_le16(HostCmd_CMD_TX_AMPDU_PROT_MODE);
+    cmd->size         = wlan_cpu_to_le16(sizeof(HostCmd_DS_CMD_TX_AMPDU_PROT_MODE) + S_DS_GEN);
+    prot_mode->action = wlan_cpu_to_le16(cmd_action);
+
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        prot_mode->mode = wlan_cpu_to_le16(para->mode);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_CSI
+/**
+ * @brief This function enable/disable CSI support.
+ *
+ * @param pmpriv       A pointer to mlan_private structure
+ * @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ * @param cmd_action   The action: GET or SET
+ * @param pdata_buf    A pointer to data buffer
+ *
+ * @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_cmd_csi(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_u16 *pdata_buf)
+{
+    HostCmd_DS_CSI_CFG *csi_cfg_cmd      = &cmd->params.csi_params;
+    wifi_csi_config_params_t *csi_params = MNULL;
+
+    ENTER();
+
+    cmd->command        = wlan_cpu_to_le16(HostCmd_CMD_CSI);
+    cmd->size           = sizeof(HostCmd_DS_CSI_CFG) + S_DS_GEN;
+    csi_cfg_cmd->action = wlan_cpu_to_le16(cmd_action);
+    switch (cmd_action)
+    {
+        case CSI_CMD_ENABLE:
+            csi_params                  = (wifi_csi_config_params_t *)pdata_buf;
+            csi_cfg_cmd->head_id        = wlan_cpu_to_le32(csi_params->head_id);
+            csi_cfg_cmd->tail_id        = wlan_cpu_to_le32(csi_params->tail_id);
+            csi_cfg_cmd->chip_id        = csi_params->chip_id;
+            csi_cfg_cmd->csi_filter_cnt = csi_params->csi_filter_cnt;
+
+            csi_cfg_cmd->channel_bandconfig.header.type        = wlan_cpu_to_le16(TLV_TYPE_CSI_MONITOR_CFG);
+            csi_cfg_cmd->channel_bandconfig.header.len         = 4;
+            csi_cfg_cmd->channel_bandconfig.bandconfig         = csi_params->band_config;
+            csi_cfg_cmd->channel_bandconfig.channel            = csi_params->channel;
+            csi_cfg_cmd->channel_bandconfig.csi_monitor_enable = csi_params->csi_monitor_enable;
+            csi_cfg_cmd->channel_bandconfig.ra4us              = csi_params->ra4us;
+
+            if (csi_cfg_cmd->csi_filter_cnt > CSI_FILTER_MAX)
+                csi_cfg_cmd->csi_filter_cnt = CSI_FILTER_MAX;
+            memcpy((t_u8 *)csi_cfg_cmd->csi_filter, (t_u8 *)csi_params->csi_filter,
+                   sizeof(wifi_csi_filter_t) * csi_cfg_cmd->csi_filter_cnt);
+
+            DBG_HEXDUMP(MCMD_D, "Enable CSI", csi_cfg_cmd, sizeof(HostCmd_DS_CSI_CFG));
+            break;
+        case CSI_CMD_DISABLE:
+            DBG_HEXDUMP(MCMD_D, "Disable CSI", csi_cfg_cmd, sizeof(HostCmd_DS_CSI_CFG));
+        default:
+            break;
+    }
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/********************************************************
+                Global Functions
+********************************************************/
+
+/**
+ *  @brief This function prepare the command before sending to firmware.
+ *
+ *  @param priv       A pointer to mlan_private structure
+ *  @param cmd_no       Command number
+ *  @param cmd_action   Command action: GET or SET
+ *  @param cmd_oid      Cmd oid: treated as sub command
+ *  @param pioctl_buf   A pointer to MLAN IOCTL Request buffer
+ *  @param pdata_buf    A pointer to information buffer
+ *  @param pcmd_buf      A pointer to cmd buf
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ops_sta_prepare_cmd(IN t_void *priv,
+                                     IN t_u16 cmd_no,
+                                     IN t_u16 cmd_action,
+                                     IN t_u32 cmd_oid,
+                                     IN t_void *pioctl_buf,
+                                     IN t_void *pdata_buf,
+                                     IN t_void *pcmd_buf)
+{
+    HostCmd_DS_COMMAND *cmd_ptr = (HostCmd_DS_COMMAND *)pcmd_buf;
+    mlan_private *pmpriv        = (mlan_private *)priv;
+    mlan_status ret             = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    /* Prepare command */
+    switch (cmd_no)
+    {
+        case HostCmd_CMD_MAC_CONTROL:
+            ret = wlan_cmd_mac_control(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_MAC_ADDRESS:
+            ret = wlan_cmd_802_11_mac_address(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_MAC_MULTICAST_ADR:
+            ret = wlan_cmd_mac_multicast_adr(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_TX_RATE_CFG:
+            ret = wlan_cmd_tx_rate_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf, pioctl_buf);
+            break;
+        case HostCmd_CMD_802_11_RF_ANTENNA:
+            ret = wlan_cmd_802_11_rf_antenna(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#if CONFIG_NET_MONITOR
+        case HostCmd_CMD_802_11_NET_MONITOR:
+            ret = wlan_cmd_802_11_net_monitor(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_TXPWR_CFG:
+            ret = wlan_cmd_tx_power_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_RF_TX_POWER:
+            ret = wlan_cmd_802_11_rf_tx_power(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_HS_CFG_ENH:
+            ret = wlan_cmd_802_11_hs_cfg(pmpriv, cmd_ptr, cmd_action, (hs_config_param *)pdata_buf);
+            break;
+#if CONFIG_WMM_UAPSD
+        case HostCmd_CMD_802_11_SLEEP_PERIOD:
+            ret = wlan_cmd_802_11_sleep_period(pmpriv, cmd_ptr, cmd_action, (t_u16 *)pdata_buf);
+            break;
+#endif
+#if !CONFIG_EXT_SCAN_SUPPORT
+        case HostCmd_CMD_802_11_SCAN:
+            ret = wlan_cmd_802_11_scan(pmpriv, cmd_ptr, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_802_11_BG_SCAN_CONFIG:
+            ret = wlan_cmd_bgscan_config(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_BG_SCAN_QUERY:
+            ret = wlan_cmd_802_11_bg_scan_query(pmpriv, cmd_ptr, cmd_action);
+            break;
+        case HostCmd_CMD_802_11_ASSOCIATE:
+            ret = wlan_cmd_802_11_associate(pmpriv, cmd_ptr, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_GET_LOG:
+            ret = wlan_cmd_802_11_get_log(pmpriv, cmd_ptr);
+            break;
+        case HostCmd_CMD_RSSI_INFO:
+            ret = wlan_cmd_802_11_rssi_info(pmpriv, cmd_ptr, cmd_action);
+            break;
+        case HostCmd_CMD_802_11_SNMP_MIB:
+            ret = wlan_cmd_802_11_snmp_mib(pmpriv, cmd_ptr, cmd_action, cmd_oid, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_TX_RATE_QUERY:
+            cmd_ptr->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_TX_RATE_QUERY);
+            cmd_ptr->size    = wlan_cpu_to_le16(sizeof(HostCmd_TX_RATE_QUERY) + S_DS_GEN);
+            pmpriv->tx_rate  = 0;
+            ret              = MLAN_STATUS_SUCCESS;
+            break;
+        case HostCmd_CMD_TBTT_OFFSET:
+            cmd_ptr->command                   = wlan_cpu_to_le16(HostCmd_CMD_TBTT_OFFSET);
+            cmd_ptr->size                      = wlan_cpu_to_le16(S_DS_GEN + sizeof(t_u16));
+            cmd_ptr->params.tbtt_offset.action = HostCmd_ACT_GEN_GET;
+            ret                                = MLAN_STATUS_SUCCESS;
+            break;
+        case HostCmd_CMD_VERSION_EXT:
+            (void)__memset(pmpriv->adapter, cmd_ptr, 0x00, sizeof(HostCmd_DS_COMMAND));
+            cmd_ptr->command                       = wlan_cpu_to_le16(cmd_no);
+            cmd_ptr->params.verext.version_str_sel = *(t_u8 *)pdata_buf;
+            cmd_ptr->size                          = wlan_cpu_to_le16(sizeof(HostCmd_DS_VERSION_EXT) + S_DS_GEN);
+            ret                                    = MLAN_STATUS_SUCCESS;
+            break;
+        case HostCmd_CMD_802_11_RF_CHANNEL:
+            ret = wlan_cmd_802_11_rf_channel(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_11N_ADDBA_REQ:
+            ret = wlan_cmd_11n_addba_req(pmpriv, cmd_ptr, pdata_buf);
+            break;
+        case HostCmd_CMD_11N_DELBA:
+            ret = wlan_cmd_11n_delba(pmpriv, cmd_ptr, pdata_buf);
+            break;
+        case HostCmd_CMD_11N_ADDBA_RSP:
+            ret = wlan_cmd_11n_addba_rspgen(pmpriv, cmd_ptr, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_KEY_MATERIAL:
+            ret = wlan_cmd_802_11_key_material(pmpriv, cmd_ptr, cmd_action, cmd_oid, pdata_buf);
+            break;
+#if CONFIG_GTK_REKEY_OFFLOAD
+        case HostCmd_CMD_CONFIG_GTK_REKEY_OFFLOAD_CFG:
+            ret = wlan_cmd_gtk_rekey_offload(pmpriv, cmd_ptr, cmd_action, cmd_oid, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_SUPPLICANT_PMK:
+            ret = wlan_cmd_802_11_supplicant_pmk(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11D_DOMAIN_INFO:
+            if (pmpriv->support_11d_APIs != MNULL)
+            {
+                ret = pmpriv->support_11d_APIs->wlan_cmd_802_11d_domain_info_p(pmpriv, cmd_ptr, cmd_action);
+            }
+            break;
+        case HostCmd_CMD_11N_CFG:
+            ret = wlan_cmd_11n_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_11AC_CFG:
+            ret = wlan_cmd_11ac_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#if CONFIG_WMM
+        case HostCmd_CMD_WMM_PARAM_CONFIG:
+            ret = wlan_cmd_wmm_param_config(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_MGMT_IE_LIST:
+            ret = wlan_cmd_mgmt_ie_list(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#if CONFIG_EXT_SCAN_SUPPORT
+        case HostCmd_CMD_802_11_SCAN_EXT:
+            ret = wlan_cmd_802_11_scan_ext(pmpriv, cmd_ptr, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_802_11_REMAIN_ON_CHANNEL:
+            ret = wlan_cmd_remain_on_channel(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_SUBSCRIBE_EVENT:
+            ret = wlan_cmd_subscribe_event(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_OTP_READ_USER_DATA:
+            ret = wlan_cmd_otp_user_data(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_HS_WAKEUP_REASON:
+            ret = wlan_cmd_hs_wakeup_reason(pmpriv, cmd_ptr, pdata_buf);
+            break;
+        case HostCmd_CMD_GET_TSF:
+            ret = wlan_cmd_get_tsf(pmpriv, cmd_ptr, cmd_action);
+            break;
+#if CONFIG_WIFI_CLOCKSYNC
+        case HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG:
+            ret = wlan_cmd_gpio_tsf_latch(pmpriv, cmd_ptr, cmd_action, pioctl_buf, pdata_buf);
+            break;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+#if (CONFIG_WIFI_TX_PER_TRACK) || (CONFIG_TX_RX_HISTOGRAM)
+        case HostCmd_CMD_TX_RX_PKT_STATS:
+            ret = wlan_cmd_txrx_pkt_stats(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if CONFIG_RF_TEST_MODE
+        case HostCmd_CMD_MFG_COMMAND:
+            ret = wlan_cmd_mfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_BOOT_SLEEP:
+            ret = wlan_cmd_boot_sleep(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#if CONFIG_11AX
+        case HostCmd_CMD_11AX_CMD:
+            ret = (mlan_status)wlan_cmd_11ax_cmd(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_11AX_CFG:
+            ret = (mlan_status)wlan_cmd_11ax_cfg(pmpriv, cmd_action, pdata_buf);
+            break;
+#if CONFIG_11AX_TWT
+        case HostCmd_CMD_TWT_CFG:
+            ret = wlan_cmd_twt_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif /* CONFIG_11AX_TWT */
+#endif /* CONFIG_11AX */
+#if CONFIG_MULTI_CHAN
+        case HostCmd_CMD_MULTI_CHAN_CONFIG:
+            ret = wlan_cmd_multi_chan_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_MULTI_CHAN_POLICY:
+            ret = wlan_cmd_multi_chan_policy(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_DRCS_CONFIG:
+            ret = wlan_cmd_drcs_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if CONFIG_COMPRESS_TX_PWTBL
+        case HostCmd_CMD_REGION_POWER_CFG:
+            ret = wlan_cmd_region_power_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if CONFIG_TX_AMPDU_PROT_MODE
+        case HostCmd_CMD_TX_AMPDU_PROT_MODE:
+            ret = wlan_cmd_tx_ampdu_prot_mode(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if CONFIG_CSI
+        case HostCmd_CMD_CSI:
+            ret = wlan_cmd_csi(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if CONFIG_RX_ABORT_CFG
+        case HostCmd_CMD_RX_ABORT_CFG:
+            ret = wlan_cmd_rx_abort_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if CONFIG_RX_ABORT_CFG_EXT
+        case HostCmd_CMD_RX_ABORT_CFG_EXT:
+            ret = wlan_cmd_rx_abort_cfg_ext(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if CONFIG_CCK_DESENSE_CFG
+        case HostCmd_CMD_CCK_DESENSE_CFG:
+            ret = wlan_cmd_cck_desense_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+        case HostCmd_CMD_INDEPENDENT_RESET_CFG:
+            ret = wlan_cmd_ind_rst_cfg(cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_802_11_TX_FRAME:
+            ret = wlan_cmd_tx_frame(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        default:
+            PRINTM(MERROR, "PREP_CMD: unknown command- %#x\n", cmd_no);
+            ret = MLAN_STATUS_FAILURE;
+            break;
+    }
+
+    LEAVE();
+    return ret;
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_cmdresp.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_cmdresp.c
new file mode 100644
index 0000000000..59ebb41af7
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_cmdresp.c
@@ -0,0 +1,909 @@
+/** @file mlan_sta_cmdresp.c
+ *
+ *  @brief  This file provides the handling of command
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/21/2008: initial version
+******************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+#if CONFIG_RF_TEST_MODE
+
+/**
+ *  @brief This function prepares command resp of MFG Continuous Tx
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_mfg_tx_cont(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *misc           = MNULL;
+    HostCmd_DS_MFG_CMD_TX_CONT *mcmd = (HostCmd_DS_MFG_CMD_TX_CONT *)&resp->params.mfg_tx_cont;
+    mlan_ds_mfg_cmd_tx_cont *cfg     = MNULL;
+
+    ENTER();
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    misc = (mlan_ds_misc_cfg *)pioctl_buf;
+    cfg  = (mlan_ds_mfg_cmd_tx_cont *)&misc->param.mfg_tx_cont;
+
+    cfg->error           = wlan_le32_to_cpu(mcmd->error);
+    cfg->enable_tx       = wlan_le32_to_cpu(mcmd->enable_tx);
+    cfg->cw_mode         = wlan_le32_to_cpu(mcmd->cw_mode);
+    cfg->payload_pattern = wlan_le32_to_cpu(mcmd->payload_pattern);
+    cfg->cs_mode         = wlan_le32_to_cpu(mcmd->cs_mode);
+    cfg->act_sub_ch      = wlan_le32_to_cpu(mcmd->act_sub_ch);
+    cfg->tx_rate         = wlan_le32_to_cpu(mcmd->tx_rate);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command resp of MFG Tx frame
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_mfg_tx_frame(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *misc             = MNULL;
+    HostCmd_DS_MFG_CMD_TX_FRAME2 *mcmd = (HostCmd_DS_MFG_CMD_TX_FRAME2 *)&resp->params.mfg_tx_frame2;
+    mlan_ds_mfg_cmd_tx_frame2 *cfg     = MNULL;
+
+    ENTER();
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    misc = (mlan_ds_misc_cfg *)pioctl_buf;
+    cfg  = (mlan_ds_mfg_cmd_tx_frame2 *)&misc->param.mfg_tx_frame2;
+
+    cfg->error             = wlan_le32_to_cpu(mcmd->error);
+    cfg->enable            = wlan_le32_to_cpu(mcmd->enable);
+    cfg->data_rate         = wlan_le32_to_cpu(mcmd->data_rate);
+    cfg->frame_pattern     = wlan_le32_to_cpu(mcmd->frame_pattern);
+    cfg->frame_length      = wlan_le32_to_cpu(mcmd->frame_length);
+    cfg->adjust_burst_sifs = wlan_le16_to_cpu(mcmd->adjust_burst_sifs);
+    cfg->burst_sifs_in_us  = wlan_le32_to_cpu(mcmd->burst_sifs_in_us);
+    cfg->short_preamble    = wlan_le32_to_cpu(mcmd->short_preamble);
+    cfg->act_sub_ch        = wlan_le32_to_cpu(mcmd->act_sub_ch);
+    cfg->short_gi          = wlan_le32_to_cpu(mcmd->short_gi);
+    cfg->adv_coding        = wlan_le32_to_cpu(mcmd->adv_coding);
+    cfg->tx_bf             = wlan_le32_to_cpu(mcmd->tx_bf);
+    cfg->gf_mode           = wlan_le32_to_cpu(mcmd->gf_mode);
+    cfg->stbc              = wlan_le32_to_cpu(mcmd->stbc);
+    cfg->signal_bw         = wlan_le32_to_cpu(mcmd->signal_bw);
+    cfg->NumPkt            = wlan_le32_to_cpu(mcmd->NumPkt);
+    cfg->MaxPE             = wlan_le32_to_cpu(mcmd->MaxPE);
+    cfg->BeamChange        = wlan_le32_to_cpu(mcmd->BeamChange);
+    cfg->Dcm               = wlan_le32_to_cpu(mcmd->Dcm);
+    cfg->Doppler           = wlan_le32_to_cpu(mcmd->Doppler);
+    cfg->MidP              = wlan_le32_to_cpu(mcmd->MidP);
+    cfg->QNum              = wlan_le32_to_cpu(mcmd->QNum);
+    memcpy(cfg->bssid, mcmd->bssid, sizeof(cfg->bssid));
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command resp of MFG HE TB Tx
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+
+static mlan_status wlan_ret_mfg_he_tb_tx(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *misc             = MNULL;
+    HostCmd_DS_MFG_CMD_HE_TBTX_T *mcmd = (HostCmd_DS_MFG_CMD_HE_TBTX_T *)&resp->params.mfg_he_power;
+    mlan_ds_mfg_Cmd_HE_TBTx_t *cfg     = MNULL;
+
+    ENTER();
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    misc = (mlan_ds_misc_cfg *)pioctl_buf;
+    cfg  = (mlan_ds_mfg_Cmd_HE_TBTx_t *)&misc->param.mfg_he_power;
+
+    cfg->enable       = wlan_le16_to_cpu(mcmd->enable);
+    cfg->qnum         = wlan_le16_to_cpu(mcmd->qnum);
+    cfg->aid          = wlan_le16_to_cpu(mcmd->aid);
+    cfg->axq_mu_timer = wlan_le16_to_cpu(mcmd->axq_mu_timer);
+    cfg->tx_power     = wlan_le16_to_cpu(mcmd->tx_power);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command resp of MFG OTP MAC add
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+
+static mlan_status wlan_ret_mfg_otp_mac_add(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *misc                 = MNULL;
+    HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T *mcmd = (HostCmd_DS_MFG_CMD_OTP_MAC_ADD_T *)&resp->params.mfg_otp_mac_addr_rd_wr;
+    mlan_ds_mfg_cmd_otp_mac_addr_rd_wr_t *cfg = MNULL;
+
+    ENTER();
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    misc = (mlan_ds_misc_cfg *)pioctl_buf;
+    cfg  = (mlan_ds_mfg_cmd_otp_mac_addr_rd_wr_t *)&misc->param.mfg_otp_mac_addr_rd_wr;
+
+    memcpy(cfg->mac_addr, mcmd->mac_addr, MLAN_MAC_ADDR_LENGTH);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command resp of MFG OTP cal data
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+
+static mlan_status wlan_ret_mfg_otp_cal_data(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *misc                  = MNULL;
+    HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T *mcmd = (HostCmd_DS_MFG_CMD_OTP_CAL_DATA_T *)&resp->params.mfg_otp_cal_data_rd_wr;
+    mlan_ds_mfg_cmd_otp_cal_data_rd_wr_t *cfg = MNULL;
+
+    ENTER();
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    misc = (mlan_ds_misc_cfg *)pioctl_buf;
+    cfg  = (mlan_ds_mfg_cmd_otp_cal_data_rd_wr_t *)&misc->param.mfg_otp_cal_data_rd_wr;
+
+    cfg->cal_data_status = mcmd->cal_data_status;
+    cfg->cal_data_len    = mcmd->cal_data_len;
+    memcpy(cfg->cal_data, mcmd->cal_data, mcmd->cal_data_len);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command resp of MFG config Trigger frame
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_mfg_config_trigger_frame(pmlan_private pmpriv,
+                                                     HostCmd_DS_COMMAND *resp,
+                                                     mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_misc_cfg *misc = MNULL;
+    HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T *mcmd =
+        (HostCmd_MFG_CMD_IEEETYPES_CTLBASICTRIGHDR_T *)&resp->params.mfg_tx_trigger_config;
+    mfg_Cmd_IEEEtypes_CtlBasicTrigHdr_t *cfg = MNULL;
+
+    ENTER();
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    misc = (mlan_ds_misc_cfg *)pioctl_buf;
+    cfg  = (mfg_Cmd_IEEEtypes_CtlBasicTrigHdr_t *)&misc->param.mfg_tx_trigger_config;
+
+    cfg->enable_tx       = wlan_le32_to_cpu(mcmd->enable_tx);
+    cfg->standalone_hetb = wlan_le32_to_cpu(mcmd->standalone_hetb);
+    cfg->frmCtl.type     = wlan_le16_to_cpu(mcmd->frmCtl.type);
+    cfg->frmCtl.sub_type = wlan_le16_to_cpu(mcmd->frmCtl.sub_type);
+    cfg->duration        = wlan_le16_to_cpu(mcmd->duration);
+
+    cfg->trig_common_field = wlan_le64_to_cpu(mcmd->trig_common_field);
+
+    cfg->trig_user_info_field = wlan_le64_to_cpu(mcmd->trig_user_info_field);
+
+    // memcpy_ext(pmpriv->adapter, &cfg->trig_user_info_field, &mcmd->trig_user_info_field,
+    //      sizeof(mcmd->trig_user_info_field), sizeof(cfg->trig_user_info_field));
+
+    cfg->basic_trig_user_info = wlan_le16_to_cpu(mcmd->basic_trig_user_info);
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command resp of MFG Cmd
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_mfg(pmlan_private pmpriv, HostCmd_DS_COMMAND *resp, void *pioctl_buf)
+{
+    HostCmd_DS_MFG_CMD_GENERIC_CFG *mcmd = (HostCmd_DS_MFG_CMD_GENERIC_CFG *)&resp->params.mfg_generic_cfg;
+    mlan_ds_misc_cfg *misc_cfg           = (mlan_ds_misc_cfg *)pioctl_buf;
+    mlan_ds_mfg_cmd_generic_cfg *cfg     = MNULL;
+    mlan_status ret                      = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    switch (wlan_le32_to_cpu(mcmd->mfg_cmd))
+    {
+        case MFG_CMD_TX_CONT:
+            ret = wlan_ret_mfg_tx_cont(pmpriv, resp, pioctl_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_TX_FRAME:
+            ret = wlan_ret_mfg_tx_frame(pmpriv, resp, pioctl_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_CONFIG_MAC_HE_TB_TX:
+            ret = wlan_ret_mfg_he_tb_tx(pmpriv, resp, pioctl_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_CONFIG_TRIGGER_FRAME:
+            ret = wlan_ret_mfg_config_trigger_frame(pmpriv, resp, pioctl_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_OTP_MAC_ADD:
+            ret = wlan_ret_mfg_otp_mac_add(pmpriv, resp, pioctl_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_OTP_CAL_DATA:
+            ret = wlan_ret_mfg_otp_cal_data(pmpriv, resp, pioctl_buf);
+            goto cmd_mfg_done;
+        case MFG_CMD_SET_TEST_MODE:
+        case MFG_CMD_UNSET_TEST_MODE:
+        case MFG_CMD_TX_ANT:
+        case MFG_CMD_RX_ANT:
+        case MFG_CMD_RF_CHAN:
+        case MFG_CMD_CLR_RX_ERR:
+        case MFG_CMD_RF_BAND_AG:
+        case MFG_CMD_RF_CHANNELBW:
+        case MFG_CMD_RADIO_MODE_CFG:
+        case MFG_CMD_RFPWR:
+            break;
+        default:
+            ret = MLAN_STATUS_FAILURE;
+            goto cmd_mfg_done;
+    }
+    cfg = (mlan_ds_mfg_cmd_generic_cfg *)&(misc_cfg->param);
+
+    cfg->error = wlan_le32_to_cpu(mcmd->error);
+    cfg->data1 = wlan_le32_to_cpu(mcmd->data1);
+    cfg->data2 = wlan_le32_to_cpu(mcmd->data2);
+    cfg->data3 = wlan_le32_to_cpu(mcmd->data3);
+cmd_mfg_done:
+    LEAVE();
+    return ret;
+}
+#endif
+
+
+/**
+ *  @brief This function handles the command response of snmp_mib
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_802_11_snmp_mib(IN pmlan_private pmpriv,
+                                            IN HostCmd_DS_COMMAND *resp,
+                                            IN mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_802_11_SNMP_MIB *psmib = &resp->params.smib;
+    t_u16 oid                         = wlan_le16_to_cpu(psmib->oid);
+    t_u16 query_type                  = wlan_le16_to_cpu(psmib->query_type);
+    t_u32 ul_temp;
+
+    mlan_ds_snmp_mib *mib = MNULL;
+
+    ENTER();
+
+    if (pioctl_buf != MNULL)
+    {
+        mib = (mlan_ds_snmp_mib *)(void *)pioctl_buf->pbuf;
+    }
+
+    /* wmsdk */
+    PRINTM(MINFO, "SNMP_RESP: value of the oid = 0x%x, query_type=0x%x\n", oid, query_type);
+    PRINTM(MINFO, "SNMP_RESP: Buf size  = 0x%x\n", wlan_le16_to_cpu(psmib->buf_size));
+
+    if (query_type == HostCmd_ACT_GEN_GET)
+    {
+        /* wmsdk: GET is not used. Disable */
+        switch (oid)
+        {
+            case DtimPeriod_i:
+                ul_temp = psmib->value[0];
+                PRINTM(MINFO, "SNMP_RESP: DTIM Period =%u\n", ul_temp);
+                if (mib != MNULL)
+                {
+                    mib->param.dtim_period = ul_temp;
+                }
+                break;
+#if CONFIG_WIFI_FRAG_THRESHOLD
+            case FragThresh_i:
+                ul_temp = wlan_le16_to_cpu(*((t_u16 *)(psmib->value)));
+                PRINTM(MINFO, "SNMP_RESP: FragThsd =%u\n", ul_temp);
+                if (mib)
+                {
+                    mib->param.frag_threshold = ul_temp;
+                }
+                break;
+#endif
+            case RtsThresh_i:
+                ul_temp = wlan_le16_to_cpu(*((t_u16 *)(psmib->value)));
+                PRINTM(MINFO, "SNMP_RESP: RTSThsd =%u\n", ul_temp);
+                if (mib)
+                {
+                    mib->param.rts_threshold = ul_temp;
+                }
+                break;
+            default:
+                PRINTM(MINFO, "Unexpected snmp_mib oid\n");
+                break;
+        }
+    }
+    else
+    { /* (query_type == HostCmd_ACT_GEN_SET) */
+        /* Update state for 11d */
+        if (oid == Dot11D_i)
+        {
+            ul_temp = wlan_le16_to_cpu(*((t_u16 *)(void *)(psmib->value)));
+            /* Set 11d state to private */
+            pmpriv->state_11d.enable_11d = (state_11d_t)ul_temp;
+            /* Set user enable flag if called from ioctl */
+            if (pioctl_buf != NULL)
+            {
+                pmpriv->state_11d.user_enable_11d = (state_11d_t)ul_temp;
+            }
+        }
+        /* Update state for 11h */
+        if (oid == Dot11H_i)
+        {
+            ul_temp = wlan_le16_to_cpu(*((t_u16 *)(void *)(psmib->value)));
+            /* Set 11h state to priv */
+            pmpriv->intf_state_11h.is_11h_active = (ul_temp & ENABLE_11H_MASK) ? MTRUE : MFALSE;
+            /* Set radar_det state to adapter */
+            pmpriv->adapter->state_11h.is_master_radar_det_active = (ul_temp & MASTER_RADAR_DET_MASK) ? MTRUE : MFALSE;
+            pmpriv->adapter->state_11h.is_slave_radar_det_active  = (ul_temp & SLAVE_RADAR_DET_MASK) ? MTRUE : MFALSE;
+        }
+    }
+
+    if (pioctl_buf != NULL)
+    {
+        /* Indicate ioctl complete */
+        pioctl_buf->data_read_written = sizeof(mlan_ds_snmp_mib);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of get_log
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_get_log(IN pmlan_private pmpriv, IN HostCmd_DS_COMMAND *resp, IN mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_802_11_GET_LOG *pget_log = (HostCmd_DS_802_11_GET_LOG *)&resp->params.get_log;
+    mlan_ds_get_info *pget_info         = MNULL;
+
+    ENTER();
+    if (pioctl_buf != NULL)
+    {
+        pget_info                               = (mlan_ds_get_info *)(void *)pioctl_buf->pbuf;
+        pget_info->param.stats.mcast_tx_frame   = wlan_le32_to_cpu(pget_log->mcast_tx_frame);
+        pget_info->param.stats.failed           = wlan_le32_to_cpu(pget_log->failed);
+        pget_info->param.stats.retry            = wlan_le32_to_cpu(pget_log->retry);
+        pget_info->param.stats.multi_retry      = wlan_le32_to_cpu(pget_log->multiretry);
+        pget_info->param.stats.frame_dup        = wlan_le32_to_cpu(pget_log->frame_dup);
+        pget_info->param.stats.rts_success      = wlan_le32_to_cpu(pget_log->rts_success);
+        pget_info->param.stats.rts_failure      = wlan_le32_to_cpu(pget_log->rts_failure);
+        pget_info->param.stats.ack_failure      = wlan_le32_to_cpu(pget_log->ack_failure);
+        pget_info->param.stats.rx_frag          = wlan_le32_to_cpu(pget_log->rx_frag);
+        pget_info->param.stats.mcast_rx_frame   = wlan_le32_to_cpu(pget_log->mcast_rx_frame);
+        pget_info->param.stats.fcs_error        = wlan_le32_to_cpu(pget_log->fcs_error);
+        pget_info->param.stats.tx_frame         = wlan_le32_to_cpu(pget_log->tx_frame);
+        pget_info->param.stats.wep_icv_error[0] = wlan_le32_to_cpu(pget_log->wep_icv_err_cnt[0]);
+        pget_info->param.stats.wep_icv_error[1] = wlan_le32_to_cpu(pget_log->wep_icv_err_cnt[1]);
+        pget_info->param.stats.wep_icv_error[2] = wlan_le32_to_cpu(pget_log->wep_icv_err_cnt[2]);
+        pget_info->param.stats.wep_icv_error[3] = wlan_le32_to_cpu(pget_log->wep_icv_err_cnt[3]);
+        /* Indicate ioctl complete */
+        pioctl_buf->data_read_written = sizeof(mlan_ds_get_info);
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Get power level and rate index
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param pdata_buf    Pointer to the data buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_get_power_level(pmlan_private pmpriv, void *pdata_buf)
+{
+    int length = -1, max_power = -1, min_power = -1;
+    MrvlTypes_Power_Group_t *ppg_tlv = MNULL;
+    Power_Group_t *pg                = MNULL;
+
+    ENTER();
+
+    if (pdata_buf != NULL)
+    {
+        ppg_tlv = (MrvlTypes_Power_Group_t *)(void *)((t_u8 *)pdata_buf + sizeof(HostCmd_DS_TXPWR_CFG));
+        pg      = (Power_Group_t *)(void *)((t_u8 *)ppg_tlv + sizeof(MrvlTypes_Power_Group_t));
+        length  = (int)ppg_tlv->length;
+        if (length > 0)
+        {
+            max_power = (int)pg->power_max;
+            min_power = (int)pg->power_min;
+            length -= (int)sizeof(Power_Group_t);
+        }
+        while (length > 0)
+        {
+            pg++;
+            if (max_power < pg->power_max)
+            {
+                max_power = (int)pg->power_max;
+            }
+            if (min_power > pg->power_min)
+            {
+                min_power = (int)pg->power_min;
+            }
+            length -= (int)sizeof(Power_Group_t);
+        }
+        if (ppg_tlv->length > 0U)
+        {
+            pmpriv->min_tx_power_level = (t_u8)min_power;
+            pmpriv->max_tx_power_level = (t_u8)max_power;
+        }
+    }
+    else
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+/**
+ *  @brief This function handles the command response of tx_power_cfg
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_tx_power_cfg(IN pmlan_private pmpriv,
+                                         IN HostCmd_DS_COMMAND *resp,
+                                         IN mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_TXPWR_CFG *ptxp_cfg   = &resp->params.txp_cfg;
+    MrvlTypes_Power_Group_t *ppg_tlv = MNULL;
+    Power_Group_t *pg                = MNULL;
+    t_u16 action                     = wlan_le16_to_cpu(ptxp_cfg->action);
+    mlan_ds_power_cfg *power         = MNULL;
+    t_u32 data[5];
+    bool invalid_hostcmd = MFALSE;
+
+    ENTER();
+
+    ppg_tlv = (MrvlTypes_Power_Group_t *)(void *)((t_u8 *)&resp->params + sizeof(HostCmd_DS_TXPWR_CFG));
+    pg      = (Power_Group_t *)(void *)((t_u8 *)ppg_tlv + sizeof(MrvlTypes_Power_Group_t));
+
+    switch (action)
+    {
+        case HostCmd_ACT_GEN_GET:
+            ppg_tlv->length = wlan_le16_to_cpu(ppg_tlv->length);
+            if (pmpriv->adapter->hw_status == WlanHardwareStatusInitializing)
+            {
+                // coverity[overrun-buffer-val:SUPPRESS]
+                (void)wlan_get_power_level(pmpriv, ptxp_cfg);
+            }
+            pmpriv->tx_power_level = (t_u16)pg->power_min;
+            PRINTM(MMSG, "The Sta tx power level: %d\r\n", pmpriv->tx_power_level);
+            break;
+
+        case HostCmd_ACT_GEN_SET:
+            if (wlan_le32_to_cpu(ptxp_cfg->mode) != 0U)
+            {
+                if (pg->power_max == pg->power_min)
+                {
+                    pmpriv->tx_power_level = (t_u16)pg->power_min;
+                }
+            }
+            break;
+        default:
+            PRINTM(MERROR, "CMD_RESP: unknown command action %d\n", action);
+            invalid_hostcmd = MTRUE;
+            break;
+    }
+    if (invalid_hostcmd == MTRUE)
+    {
+        LEAVE();
+        return MLAN_STATUS_SUCCESS;
+    }
+
+    PRINTM(MINFO, "Current TxPower Level = %d,Max Power=%d, Min Power=%d\n", pmpriv->tx_power_level,
+           pmpriv->max_tx_power_level, pmpriv->min_tx_power_level);
+
+    if (pioctl_buf != MNULL)
+    {
+        power = (mlan_ds_power_cfg *)(void *)pioctl_buf->pbuf;
+        if (action == HostCmd_ACT_GEN_GET)
+        {
+            if (power->sub_command == MLAN_OID_POWER_CFG)
+            {
+                pioctl_buf->data_read_written      = sizeof(mlan_power_cfg_t) + MLAN_SUB_COMMAND_SIZE;
+                power->param.power_cfg.power_level = pmpriv->tx_power_level;
+                if (wlan_le32_to_cpu(ptxp_cfg->mode) != 0U)
+                {
+                    power->param.power_cfg.is_power_auto = MFALSE;
+                }
+                else
+                {
+                    power->param.power_cfg.is_power_auto = MTRUE;
+                }
+            }
+            else
+            {
+                power->param.power_ext.len = 0;
+                while (ppg_tlv->length != 0U)
+                {
+                    data[0] = pg->first_rate_code;
+                    data[1] = pg->last_rate_code;
+                    if (pg->modulation_class == MOD_CLASS_OFDM)
+                    {
+                        data[0] += MLAN_RATE_INDEX_OFDM0;
+                        data[1] += MLAN_RATE_INDEX_OFDM0;
+                    }
+                    else if (pg->modulation_class == MOD_CLASS_HT)
+                    {
+                        data[0] += MLAN_RATE_INDEX_MCS0;
+                        data[1] += MLAN_RATE_INDEX_MCS0;
+                        if (pg->ht_bandwidth == HT_BW_40)
+                        {
+                            data[0] |= TX_RATE_HT_BW40_BIT;
+                            data[1] |= TX_RATE_HT_BW40_BIT;
+                        }
+                    }
+                    else
+                    {
+                        /* Do Nothing */
+                    }
+                    data[2] = (t_u32)pg->power_min;
+                    data[3] = (t_u32)pg->power_max;
+                    data[4] = (t_u32)pg->power_step;
+                    (void)__memcpy(pmpriv->adapter,
+                                   (t_u8 *)(&power->param.power_ext.power_data[power->param.power_ext.len]),
+                                   (t_u8 *)data, sizeof(data));
+                    power->param.power_ext.len += 5U;
+                    pg++;
+                    ppg_tlv->length -= (t_u16)sizeof(Power_Group_t);
+                }
+                pioctl_buf->data_read_written = sizeof(mlan_power_cfg_ext) + MLAN_SUB_COMMAND_SIZE;
+            }
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#if CONFIG_WMM_UAPSD
+/**
+ *  @brief This function handles the command response of sleep_period
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_802_11_sleep_period(IN pmlan_private pmpriv,
+                                                IN HostCmd_DS_COMMAND *resp,
+                                                IN mlan_ioctl_req *pioctl_buf)
+{
+    HostCmd_DS_802_11_SLEEP_PERIOD *pcmd_sleep_pd = &resp->params.sleep_pd;
+    mlan_ds_pm_cfg *pm_cfg                        = MNULL;
+    t_u16 sleep_pd                                = 0;
+
+    ENTER();
+
+    sleep_pd = wlan_le16_to_cpu(pcmd_sleep_pd->sleep_pd);
+    if (pioctl_buf)
+    {
+        pm_cfg                        = (mlan_ds_pm_cfg *)pioctl_buf->pbuf;
+        pm_cfg->param.sleep_period    = (t_u32)sleep_pd;
+        pioctl_buf->data_read_written = sizeof(pm_cfg->param.sleep_period) + MLAN_SUB_COMMAND_SIZE;
+    }
+    pmpriv->adapter->sleep_period.period = sleep_pd;
+
+    pmpriv->adapter->pps_uapsd_mode = MFALSE;
+    pmpriv->adapter->tx_lock_flag   = MFALSE;
+    if ((pmpriv->adapter->sleep_period.period != 0) &&
+        (pmpriv->adapter->sleep_period.period != SLEEP_PERIOD_RESERVED_FF))
+    {
+        pmpriv->adapter->gen_null_pkt = MTRUE;
+    }
+    else
+    {
+        pmpriv->adapter->gen_null_pkt = MFALSE;
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+/**
+ *  @brief This function handles the command response of deauthenticate
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_802_11_deauthenticate(IN pmlan_private pmpriv,
+                                           IN HostCmd_DS_COMMAND *resp,
+                                           IN mlan_ioctl_req *pioctl_buf)
+{
+    ENTER();
+        wlan_reset_connect_state(pmpriv, MTRUE);
+
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+/**
+ *  @brief This function handles the command response of rf_channel
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_802_11_rf_channel(IN pmlan_private pmpriv,
+                                              IN HostCmd_DS_COMMAND *resp,
+                                              IN mlan_ioctl_req *pioctl_buf)
+{
+    ENTER();
+    /* fixme: enable this part when needed */
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+
+#if (CONFIG_SUBSCRIBE_EVENT_SUPPORT)
+/**
+ *  @brief This function handles the command response of
+ *  subscribe event
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to command buffer
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_ret_subscribe_event(IN pmlan_private pmpriv,
+                                            IN HostCmd_DS_COMMAND *resp,
+                                            IN mlan_ioctl_req *sub_evt)
+{
+    ENTER();
+    if (sub_evt && wlan_parse_getdata(resp, (mlan_ds_subscribe_evt *)sub_evt) != WM_SUCCESS)
+    {
+        wevt_w("get subscribe event fail\n");
+        return MLAN_STATUS_FAILURE;
+    }
+    LEAVE();
+
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+
+/********************************************************
+                Global Functions
+********************************************************/
+/**
+ *  @brief This function handles the station command response
+ *
+ *  @param priv             A pointer to mlan_private structure
+ *  @param cmdresp_no       cmd no
+ *  @param pcmd_buf         cmdresp buf
+ *  @param pioctl           A pointer to ioctl buf
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ops_sta_process_cmdresp(IN t_void *priv, IN t_u16 cmdresp_no, IN t_void *pcmd_buf, IN t_void *pioctl)
+{
+    mlan_status ret            = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv       = (mlan_private *)priv;
+    HostCmd_DS_COMMAND *resp   = (HostCmd_DS_COMMAND *)pcmd_buf;
+    mlan_ioctl_req *pioctl_buf = (mlan_ioctl_req *)pioctl;
+    /* mlan_adapter *pmadapter = pmpriv->adapter; */
+    /* int ctr; */
+
+    ENTER();
+
+    /* fixme: enable below code when required */
+    /* Command successful, handle response */
+    switch (cmdresp_no)
+    {
+        case HostCmd_CMD_GET_HW_SPEC:
+            ret = wlan_ret_get_hw_spec(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_TXPWR_CFG:
+            ret = wlan_ret_tx_power_cfg(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_TX_RATE_CFG:
+            ret = wlan_ret_tx_rate_cfg(pmpriv, resp, pioctl_buf);
+            break;
+#if !CONFIG_EXT_SCAN_SUPPORT
+        case HostCmd_CMD_802_11_SCAN:
+            ret        = wlan_ret_802_11_scan(pmpriv, resp, pioctl_buf);
+            pioctl_buf = MNULL;
+            /* pmadapter->curr_cmd->pioctl_buf = MNULL; */
+            break;
+#else
+        case HostCmd_CMD_802_11_SCAN_EXT:
+            ret        = wlan_ret_802_11_scan_ext(pmpriv, resp, pioctl_buf);
+            pioctl_buf = MNULL;
+            break;
+#endif /* CONFIG_EXT_SCAN_SUPPORT */
+#if CONFIG_WMM_UAPSD
+        case HostCmd_CMD_802_11_SLEEP_PERIOD:
+            ret = wlan_ret_802_11_sleep_period(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+        case HostCmd_CMD_802_11_ASSOCIATE:
+            ret = wlan_ret_802_11_associate(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_802_11_GET_LOG:
+            ret = wlan_ret_get_log(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_802_11_SNMP_MIB:
+            ret = wlan_ret_802_11_snmp_mib(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_802_11_TX_RATE_QUERY:
+            ret = wlan_ret_802_11_tx_rate_query(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_802_11_RF_CHANNEL:
+            ret = wlan_ret_802_11_rf_channel(pmpriv, resp, pioctl_buf);
+            break;
+#if CONFIG_WMM
+        case HostCmd_CMD_WMM_PARAM_CONFIG:
+            ret = wlan_ret_wmm_param_config(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+        case HostCmd_CMD_802_11_SUBSCRIBE_EVENT:
+            ret = wlan_ret_subscribe_event(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+        case HostCmd_CMD_802_11_BG_SCAN_QUERY:
+            ret = wlan_ret_802_11_scan(pmpriv, resp, pioctl_buf);
+            PRINTM(MINFO, "CMD_RESP: BG_SCAN result is ready!\n");
+            break;
+#if CONFIG_RF_TEST_MODE
+        case HostCmd_CMD_MFG_COMMAND:
+            ret = wlan_ret_mfg(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+#ifdef OTP_CHANINFO
+        case HostCmd_CMD_CHAN_REGION_CFG:
+            ret = wlan_ret_chan_region_cfg(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+        case HostCmd_CMD_BOOT_SLEEP:
+            ret = wlan_ret_boot_sleep(pmpriv, resp, pioctl_buf);
+            break;
+#if CONFIG_11AX
+        case HostCmd_CMD_11AX_CMD:
+            ret = wlan_ret_11ax_cmd(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+#if CONFIG_WIFI_CLOCKSYNC
+        case HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG:
+            ret = wlan_ret_gpio_tsf_latch(pmpriv, resp, pioctl_buf);
+            break;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+#if CONFIG_MULTI_CHAN
+        case HostCmd_CMD_MULTI_CHAN_CONFIG:
+            ret = wlan_ret_multi_chan_cfg(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_MULTI_CHAN_POLICY:
+            ret = wlan_ret_multi_chan_policy(pmpriv, resp, pioctl_buf);
+            break;
+        case HostCmd_CMD_DRCS_CONFIG:
+            ret = wlan_ret_drcs_cfg(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+        case HostCmd_CMD_INDEPENDENT_RESET_CFG:
+            ret = wlan_ret_ind_rst_cfg(pmpriv, resp, pioctl_buf);
+            break;
+#endif
+        default:
+            PRINTM(MERROR, "CMD_RESP: Unknown command response %#x\n", resp->command);
+            break;
+    }
+
+    LEAVE();
+    return ret;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_event.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_event.c
new file mode 100644
index 0000000000..d89b569a94
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_event.c
@@ -0,0 +1,136 @@
+/** @file mlan_sta_event.c
+ *
+ *  @brief  This file provides Function for STA event handling
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    10/13/2008: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+/**
+ *  @brief This function handles disconnect event, reports disconnect
+ *  		to upper layer, cleans tx/rx packets,
+ *  		resets link state etc.
+ *
+ *  @param priv            A pointer to mlan_private structure
+ *  @param drv_disconnect  Flag indicating the driver should disconnect
+ *                         and flush pending packets.
+ *
+ *  @return        N/A
+ */
+t_void wlan_reset_connect_state(pmlan_private priv, t_u8 drv_disconnect)
+{
+    ENTER();
+
+
+    PRINTM(MINFO, "Handles disconnect event.\n");
+
+    if (drv_disconnect == MTRUE)
+    {
+        priv->media_connected = MFALSE;
+    }
+
+    if (priv->port_ctrl_mode == MTRUE)
+    {
+        /* Close the port on Disconnect */
+        PRINTM(MINFO, "DISC: port_status = CLOSED\n");
+        priv->port_open = MFALSE;
+    }
+    priv->scan_block = MFALSE;
+
+    /* Reset SNR/NF/RSSI values */
+    priv->data_rssi_last = 0;
+    priv->data_nf_last   = 0;
+    priv->data_rssi_avg  = 0;
+    priv->data_nf_avg    = 0;
+    priv->bcn_rssi_last  = 0;
+    priv->bcn_nf_last    = 0;
+    priv->bcn_rssi_avg   = 0;
+    priv->bcn_nf_avg     = 0;
+    priv->rxpd_rate      = 0;
+#ifdef SD8801
+    priv->rxpd_htinfo = 0;
+#else
+    priv->rxpd_rate_info = 0;
+#endif
+    priv->max_amsdu = 0;
+
+    priv->tx_pause = 0;
+#if (CONFIG_WPS2) || (CONFIG_WPA_SUPP_WPS)
+    priv->wps.session_enable = MFALSE;
+    (void)__memset(priv->adapter, (t_u8 *)&priv->wps.wps_ie, 0x00, sizeof(priv->wps.wps_ie));
+#endif /* CONFIG_WPS2 */
+
+    /* Enable auto data rate */
+    priv->is_data_rate_auto = MTRUE;
+    priv->data_rate         = 0;
+#if CONFIG_11K
+    priv->neighbor_rep_token = (t_u8)1U;
+#endif
+#if CONFIG_11V
+    priv->bss_trans_query_token = (t_u8)1U;
+#endif
+    if (priv->bss_mode == MLAN_BSS_MODE_IBSS)
+    {
+        priv->adhoc_state                        = (t_u8)ADHOC_IDLE;
+        priv->adhoc_is_link_sensed               = MFALSE;
+        priv->intf_state_11h.adhoc_auto_sel_chan = MTRUE;
+    }
+
+#if CONFIG_WMM_UAPSD
+    /* Need to put uapsd_sem before getting ra_list.plock in wlan_ralist_del_all_enh */
+    if (priv->adapter->pps_uapsd_mode)
+    {
+        OSA_SemaphorePost((osa_semaphore_handle_t)uapsd_sem);
+    }
+    priv->adapter->tx_lock_flag   = MFALSE;
+    priv->adapter->pps_uapsd_mode = MFALSE;
+#endif
+
+#if CONFIG_GTK_REKEY_OFFLOAD
+    (void)__memset(pmadapter, &priv->gtk_rekey, 0, sizeof(priv->gtk_rekey));
+#endif
+
+    if (drv_disconnect == MTRUE)
+    {
+        /* Free Tx and Rx packets, report disconnect to upper layer */
+        wlan_clean_txrx(priv);
+
+        /* Need to erase the current SSID and BSSID info */
+        (void)__memset(priv->adapter, &priv->curr_bss_params, 0x00, sizeof(priv->curr_bss_params));
+    }
+
+    LEAVE();
+}
+
+/**
+ *  @brief This function handles link lost, deauth and
+ *  		disassoc events.
+ *
+ *  @param priv    A pointer to mlan_private structure
+ *  @return        N/A
+ */
+t_void wlan_handle_disconnect_event(pmlan_private pmpriv)
+{
+    ENTER();
+
+        wlan_reset_connect_state(pmpriv, MTRUE);
+
+    LEAVE();
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_ioctl.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_ioctl.c
new file mode 100644
index 0000000000..8d8b89f62f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_ioctl.c
@@ -0,0 +1,1519 @@
+/** @file mlan_sta_ioctl.c
+ *
+ *  @brief  This file provides functions for station ioctl
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/******************************************************
+Change log:
+    10/21/2008: initial version
+******************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+
+mlan_status wlan_misc_ioctl_region(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req);
+t_u8 wlan_get_random_charactor(pmlan_adapter pmadapter);
+
+/**
+ *  @brief Set/Get SNMP MIB handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_snmp_mib_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    pmlan_private pmpriv  = pmadapter->priv[pioctl_req->bss_index];
+    mlan_status ret       = MLAN_STATUS_SUCCESS;
+    t_u16 cmd_action      = 0;
+    t_u16 cmd_oid         = 0;
+    mlan_ds_snmp_mib *mib = MNULL;
+    t_u32 value           = 0;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_snmp_mib))
+    {
+        PRINTM(MWARN, "MLAN IOCTL information buffer length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_snmp_mib);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        ret                           = MLAN_STATUS_RESOURCE;
+        goto exit;
+    }
+
+    mib = (mlan_ds_snmp_mib *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+        cmd_action = HostCmd_ACT_GEN_SET;
+    else
+        cmd_action = HostCmd_ACT_GEN_GET;
+
+    switch (mib->sub_command)
+    {
+        case MLAN_OID_SNMP_MIB_RTS_THRESHOLD:
+            value   = mib->param.rts_threshold;
+            cmd_oid = RtsThresh_i;
+            break;
+        case MLAN_OID_SNMP_MIB_FRAG_THRESHOLD:
+            value   = mib->param.frag_threshold;
+            cmd_oid = FragThresh_i;
+            break;
+        case MLAN_OID_SNMP_MIB_RETRY_COUNT:
+            value   = mib->param.retry_count;
+            cmd_oid = ShortRetryLim_i;
+            break;
+        case MLAN_OID_SNMP_MIB_DTIM_PERIOD:
+            value   = mib->param.dtim_period;
+            cmd_oid = DtimPeriod_i;
+            break;
+    }
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_802_11_SNMP_MIB, cmd_action, cmd_oid, (t_void *)pioctl_req, &value);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+
+exit:
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Set/Get Infra/Ad-hoc band configuration
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_radio_ioctl_band_cfg(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    t_u8 i = 0;
+    t_u16 global_band = 0;
+    t_u16 infra_band              = 0;
+    mlan_ds_radio_cfg *radio_cfg = MNULL;
+    mlan_private *pmpriv         = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+
+    radio_cfg = (mlan_ds_radio_cfg *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+    {
+        infra_band    = radio_cfg->param.band_cfg.config_bands;
+
+        /* SET Infra band */
+        if ((infra_band | pmadapter->fw_bands) & ~pmadapter->fw_bands)
+        {
+            pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+
+
+        for (i = 0; i < pmadapter->priv_num; i++)
+        {
+            if (pmadapter->priv[i] && pmadapter->priv[i] != pmpriv &&
+                GET_BSS_ROLE(pmadapter->priv[i]) == MLAN_BSS_ROLE_STA)
+                global_band |= pmadapter->priv[i]->config_bands;
+        }
+        global_band |= infra_band;
+
+        if (wlan_set_regiontable(pmpriv, (t_u8)pmadapter->region_code, global_band
+        ))
+        {
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_FAIL;
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+
+        if (wlan_11d_set_universaltable(pmpriv, global_band
+        ))
+        {
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_FAIL;
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        pmpriv->config_bands    = infra_band;
+        pmadapter->config_bands = global_band;
+
+    }
+    else
+    {
+        radio_cfg->param.band_cfg.config_bands = pmpriv->config_bands;            /* Infra
+                                                                                     Bands
+                                                                                   */
+        radio_cfg->param.band_cfg.adhoc_start_band = pmadapter->adhoc_start_band; /* Adhoc
+                                                                                     Band
+                                                                                   */
+        radio_cfg->param.band_cfg.adhoc_channel = pmpriv->adhoc_channel;          /* Adhoc
+                                                                                     Channel
+                                                                                   */
+        radio_cfg->param.band_cfg.fw_bands = pmadapter->fw_bands;                 /* FW
+                                                                                     support
+                                                                                     Bands
+                                                                                   */
+        PRINTM(MINFO, "Global config band = %d\n", pmadapter->config_bands);
+        radio_cfg->param.band_cfg.sec_chan_offset = pmadapter->chan_bandwidth;    /* adhoc
+                                                                                     channel
+                                                                                     bandwidth
+                                                                                   */
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief Radio command handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_radio_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status           = MLAN_STATUS_SUCCESS;
+    mlan_ds_radio_cfg *radio_cfg = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_radio_cfg))
+    {
+        PRINTM(MWARN, "MLAN IOCTL information buffer length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_radio_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    radio_cfg = (mlan_ds_radio_cfg *)pioctl_req->pbuf;
+    switch (radio_cfg->sub_command)
+    {
+        case MLAN_OID_BAND_CFG:
+            status = wlan_radio_ioctl_band_cfg(pmadapter, pioctl_req);
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+
+    LEAVE();
+    return status;
+}
+
+
+/**
+ *  @brief Start BSS
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_bss_ioctl_start(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_bss *bss     = (mlan_ds_bss *)(void *)pioctl_req->pbuf;
+    t_s32 i              = -1;
+    t_u8 zero_mac[]      = {0, 0, 0, 0, 0, 0};
+
+    ENTER();
+
+    /* Before ASSOC REQ, If "port ctrl" mode is enabled, move the port to
+       CLOSED state */
+    if (pmpriv->port_ctrl_mode == MTRUE)
+    {
+        PRINTM(MINFO, "bss_ioctl_start(): port_state=CLOSED\n");
+        pmpriv->prior_port_status = pmpriv->port_open;
+        pmpriv->port_open         = MFALSE;
+    }
+    pmpriv->scan_block = MFALSE;
+
+    if (pmpriv->bss_mode == MLAN_BSS_MODE_INFRA)
+    {
+        if (!bss->param.ssid_bssid.idx || bss->param.ssid_bssid.idx > pmadapter->num_in_scan_table)
+        {
+            /* Search for the requested SSID in the scan table */
+            if (bss->param.ssid_bssid.ssid.ssid_len != 0U)
+            {
+                if (__memcmp(pmadapter, &bss->param.ssid_bssid.bssid, zero_mac, sizeof(zero_mac)) != 0U)
+                {
+                    i = wlan_find_ssid_in_list(pmpriv, &bss->param.ssid_bssid.ssid,
+                                               (t_u8 *)&bss->param.ssid_bssid.bssid, MLAN_BSS_MODE_INFRA);
+                }
+                else
+                {
+                    i = wlan_find_ssid_in_list(pmpriv, &bss->param.ssid_bssid.ssid, MNULL, MLAN_BSS_MODE_INFRA);
+                }
+            }
+            else
+            {
+                i = wlan_find_bssid_in_list(pmpriv, (t_u8 *)&bss->param.ssid_bssid.bssid, MLAN_BSS_MODE_INFRA);
+            }
+        }
+        else
+        {
+            /* fixme: Disabled for now since handling is done in legacy
+             * code. It is IMPORTANT and needs to enabled.
+             */
+            i = ((t_s32)bss->param.ssid_bssid.idx - 1);
+        }
+        if (i >= 0)
+        {
+            PRINTM(MINFO, "SSID found in scan list ... associating...\n");
+
+            /* Clear any past association response stored for application
+               retrieval */
+            /* fixme: enable if needed later */
+            /* pmpriv->assoc_rsp_size = 0; */
+            ret = wlan_associate(pmpriv, pioctl_req, &pmadapter->pscan_table[i]);
+            if (ret != MLAN_STATUS_SUCCESS)
+            {
+                goto start_ssid_done;
+            }
+        }
+        else
+        {   /* i >= 0 */
+            /* fixme: The below seems related to Adhoc. Check later. */
+        }
+    }
+    else
+    {
+    }
+
+        ret = MLAN_STATUS_PENDING;
+
+start_ssid_done:
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief BSS command handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_bss_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status = MLAN_STATUS_SUCCESS;
+    mlan_ds_bss *bss   = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_bss))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_bss);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+
+    bss = (mlan_ds_bss *)(void *)pioctl_req->pbuf;
+
+    switch (bss->sub_command)
+    {
+        case MLAN_OID_BSS_START:
+            status = wlan_bss_ioctl_start(pmadapter, pioctl_req);
+            break;
+        default:
+            status = MLAN_STATUS_FAILURE;
+            break;
+    }
+
+    LEAVE();
+    return status;
+}
+
+
+/**
+ *  @brief Rate command handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_rate_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status = MLAN_STATUS_SUCCESS;
+    mlan_ds_rate *rate = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_rate))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_rate);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    rate = (mlan_ds_rate *)(void *)pioctl_req->pbuf;
+    switch (rate->sub_command)
+    {
+        case MLAN_OID_RATE_CFG:
+            status = wlan_rate_ioctl_cfg(pmadapter, pioctl_req);
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+
+/**
+ *  @brief Get Tx power configuration
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param cmd_no	Firmware command number used to retrieve power values
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_power_ioctl_get_power(IN pmlan_adapter pmadapter,
+                                              IN t_u16 cmd_no,
+                                              IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, cmd_no, HostCmd_ACT_GEN_GET, 0, (t_void *)pioctl_req, MNULL);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Set Tx power configuration
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_power_ioctl_set_power(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_ds_power_cfg *power = MNULL;
+    mlan_status ret          = MLAN_STATUS_SUCCESS;
+
+    HostCmd_DS_TXPWR_CFG *txp_cfg   = MNULL;
+    MrvlTypes_Power_Group_t *pg_tlv = MNULL;
+    Power_Group_t *pg               = MNULL;
+    pmlan_callbacks pcb             = &pmadapter->callbacks;
+    t_u8 *buf                       = MNULL;
+    t_u16 dbm                       = 0;
+    mlan_private *pmpriv            = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+
+    power = (mlan_ds_power_cfg *)(void *)pioctl_req->pbuf;
+    if (!power->param.power_cfg.is_power_auto)
+    {
+        dbm = (t_u16)power->param.power_cfg.power_level;
+#if 0
+        if ((dbm < pmpriv->min_tx_power_level) ||
+            (dbm > pmpriv->max_tx_power_level)) {
+            PRINTM(MERROR,
+                   "The set txpower value %d dBm is out of range (%d dBm-%d dBm)!\n",
+                   dbm, pmpriv->min_tx_power_level, pmpriv->max_tx_power_level);
+            pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+            ret = MLAN_STATUS_FAILURE;
+            goto exit;
+        }
+#endif
+    }
+
+    ret = pcb->moal_malloc(pmadapter->pmoal_handle, MRVDRV_SIZE_OF_CMD_BUFFER, MLAN_MEM_DEF, &buf);
+    if (ret != MLAN_STATUS_SUCCESS || (buf == MNULL))
+    {
+        PRINTM(MERROR, "ALLOC_CMD_BUF: Failed to allocate command buffer\n");
+        pioctl_req->status_code = MLAN_ERROR_NO_MEM;
+        ret                     = MLAN_STATUS_FAILURE;
+        goto exit;
+    }
+    (void)__memset(pmadapter, buf, 0, MRVDRV_SIZE_OF_CMD_BUFFER);
+    txp_cfg         = (HostCmd_DS_TXPWR_CFG *)(void *)buf;
+    txp_cfg->action = HostCmd_ACT_GEN_SET;
+    if (!power->param.power_cfg.is_power_auto)
+    {
+        txp_cfg->mode  = 1;
+        pg_tlv         = (MrvlTypes_Power_Group_t *)(void *)(buf + sizeof(HostCmd_DS_TXPWR_CFG));
+        pg_tlv->type   = TLV_TYPE_POWER_GROUP;
+        pg_tlv->length = 4U * sizeof(Power_Group_t);
+        pg = (Power_Group_t *)(void *)(buf + sizeof(HostCmd_DS_TXPWR_CFG) + sizeof(MrvlTypes_Power_Group_t));
+        /* Power group for modulation class HR/DSSS */
+        pg->first_rate_code  = 0x00;
+        pg->last_rate_code   = 0x03;
+        pg->modulation_class = MOD_CLASS_HR_DSSS;
+        pg->power_step       = (t_s8)0;
+        pg->power_min        = (t_s8)dbm;
+        pg->power_max        = (t_s8)dbm;
+        pg++;
+        /* Power group for modulation class OFDM */
+        pg->first_rate_code  = 0x00;
+        pg->last_rate_code   = 0x07;
+        pg->modulation_class = MOD_CLASS_OFDM;
+        pg->power_step       = (t_s8)0;
+        pg->power_min        = (t_s8)dbm;
+        pg->power_max        = (t_s8)dbm;
+        pg++;
+        /* Power group for modulation class HTBW20 */
+        pg->first_rate_code  = 0x00;
+        pg->last_rate_code   = 0x20;
+        pg->modulation_class = MOD_CLASS_HT;
+        pg->power_step       = (t_s8)0;
+        pg->power_min        = (t_s8)dbm;
+        pg->power_max        = (t_s8)dbm;
+        pg->ht_bandwidth     = HT_BW_20;
+        pg++;
+        /* Power group for modulation class HTBW40 */
+        pg->first_rate_code  = 0x00;
+        pg->last_rate_code   = 0x20;
+        pg->modulation_class = MOD_CLASS_HT;
+        pg->power_step       = (t_s8)0;
+        pg->power_min        = (t_s8)dbm;
+        pg->power_max        = (t_s8)dbm;
+        pg->ht_bandwidth     = HT_BW_40;
+    }
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_TXPWR_CFG, HostCmd_ACT_GEN_SET, 0, (t_void *)pioctl_req, buf);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    (void)pcb->moal_mfree(pmadapter->pmoal_handle, buf);
+
+exit:
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Get modulation class from rate index
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param rate_index	Rate index
+ *
+ *  @return		0 fail, otherwise return modulation class
+ */
+static int wlan_get_modulation_class(pmlan_adapter pmadapter, int rate_index)
+{
+    ENTER();
+    if (rate_index >= MLAN_RATE_INDEX_HRDSSS0 && rate_index <= MLAN_RATE_INDEX_HRDSSS3)
+    {
+        LEAVE();
+        return (int)MOD_CLASS_HR_DSSS;
+    }
+    else if (rate_index >= MLAN_RATE_INDEX_OFDM0 && rate_index <= MLAN_RATE_INDEX_OFDM7)
+    {
+        LEAVE();
+        return (int)MOD_CLASS_OFDM;
+    }
+    else if (rate_index <= MLAN_RATE_INDEX_MCS127)
+    {
+        LEAVE();
+        return (int)MOD_CLASS_HT;
+    }
+    else
+    { /* Do Nothing */
+    }
+    PRINTM(MERROR, "Invalid rate index = %d supplied!\n", rate_index);
+
+    LEAVE();
+    return 0;
+}
+
+/**
+ *  @brief Set extended power configuration
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_power_ioctl_set_power_ext(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret                 = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv            = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_power_cfg *power        = MNULL;
+    pmlan_callbacks pcb             = &pmadapter->callbacks;
+    t_u8 *buf                       = MNULL;
+    HostCmd_DS_TXPWR_CFG *txp_cfg   = MNULL;
+    MrvlTypes_Power_Group_t *pg_tlv = MNULL;
+    Power_Group_t *pg               = MNULL;
+    int mod_class;
+    t_u32 data[4] = {0};
+    t_u8 ht_bw;
+
+    ENTER();
+
+    power = (mlan_ds_power_cfg *)(void *)pioctl_req->pbuf;
+    ret   = pcb->moal_malloc(pmadapter->pmoal_handle, MRVDRV_SIZE_OF_CMD_BUFFER, MLAN_MEM_DEF, &buf);
+    if (ret != MLAN_STATUS_SUCCESS || (buf == MNULL))
+    {
+        PRINTM(MERROR, "ALLOC_CMD_BUF: Failed to allocate command buffer\n");
+        pioctl_req->status_code = MLAN_ERROR_NO_MEM;
+        ret                     = MLAN_STATUS_FAILURE;
+        goto exit;
+    }
+    (void)__memset(pmadapter, buf, 0, MRVDRV_SIZE_OF_CMD_BUFFER);
+    txp_cfg         = (HostCmd_DS_TXPWR_CFG *)(void *)buf;
+    txp_cfg->action = HostCmd_ACT_GEN_SET;
+    (void)__memcpy(pmadapter, (t_u8 *)&data, (t_u8 *)power->param.power_ext.power_data, sizeof(data));
+    switch (power->param.power_ext.len)
+    {
+        case 1:
+            if (data[0] == 0xFFU)
+            {
+                txp_cfg->mode = 0;
+            }
+            else
+            {
+                pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+                ret                     = MLAN_STATUS_FAILURE;
+            }
+            break;
+        case 2:
+        case 4:
+            ht_bw = (data[0] & TX_RATE_HT_BW40_BIT) ? HT_BW_40 : HT_BW_20;
+            data[0] &= ~TX_RATE_HT_BW40_BIT;
+            if (!(mod_class = wlan_get_modulation_class(pmadapter, (int)data[0])))
+            {
+                pioctl_req->status_code = MLAN_ERROR_CMD_RESP_FAIL;
+                ret                     = MLAN_STATUS_FAILURE;
+                break;
+            }
+            if (ht_bw && mod_class != MOD_CLASS_HT)
+            {
+                pioctl_req->status_code = MLAN_ERROR_CMD_RESP_FAIL;
+                ret                     = MLAN_STATUS_FAILURE;
+                break;
+            }
+            txp_cfg->mode  = 1;
+            pg_tlv         = (MrvlTypes_Power_Group_t *)(void *)(buf + sizeof(HostCmd_DS_TXPWR_CFG));
+            pg_tlv->type   = TLV_TYPE_POWER_GROUP;
+            pg_tlv->length = (t_u16)sizeof(Power_Group_t);
+            pg = (Power_Group_t *)(void *)(buf + sizeof(HostCmd_DS_TXPWR_CFG) + sizeof(MrvlTypes_Power_Group_t));
+            pg->modulation_class = (t_u8)mod_class;
+            pg->first_rate_code  = (t_u8)data[0];
+            pg->last_rate_code   = (t_u8)data[0];
+            if (mod_class == MOD_CLASS_OFDM)
+            {
+                pg->first_rate_code = (t_u8)(data[0] - MLAN_RATE_INDEX_OFDM0);
+                pg->last_rate_code  = (t_u8)(data[0] - MLAN_RATE_INDEX_OFDM0);
+            }
+            else if (mod_class == MOD_CLASS_HT)
+            {
+                pg->first_rate_code = (t_u8)(data[0] - MLAN_RATE_INDEX_MCS0);
+                pg->last_rate_code  = (t_u8)(data[0] - MLAN_RATE_INDEX_MCS0);
+                pg->ht_bandwidth    = ht_bw;
+            }
+            else
+            {
+                /* Do Nothing */
+            }
+            pg->power_min = (t_s8)data[1];
+            pg->power_max = (t_s8)data[1];
+            if (power->param.power_ext.len == 4U)
+            {
+                pg->power_max  = (t_s8)data[2];
+                pg->power_step = (t_s8)data[3];
+            }
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+            ret                     = MLAN_STATUS_FAILURE;
+            break;
+    }
+    if (ret == MLAN_STATUS_FAILURE)
+    {
+        (void)pcb->moal_mfree(pmadapter->pmoal_handle, buf);
+        goto exit;
+    }
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_TXPWR_CFG, HostCmd_ACT_GEN_SET, 0, (t_void *)pioctl_req, buf);
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+    (void)pcb->moal_mfree(pmadapter->pmoal_handle, buf);
+
+exit:
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Power configuration command handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_power_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status       = MLAN_STATUS_SUCCESS;
+    mlan_ds_power_cfg *power = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_power_cfg))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_power_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    power = (mlan_ds_power_cfg *)(void *)pioctl_req->pbuf;
+    switch (power->sub_command)
+    {
+        case MLAN_OID_POWER_CFG:
+            if (pioctl_req->action == MLAN_ACT_GET)
+            {
+                status = wlan_power_ioctl_get_power(pmadapter, HostCmd_CMD_TXPWR_CFG, pioctl_req);
+            }
+            else
+            {
+                status = wlan_power_ioctl_set_power(pmadapter, pioctl_req);
+            }
+            break;
+        case MLAN_OID_POWER_CFG_EXT:
+            if (pioctl_req->action == MLAN_ACT_GET)
+            {
+                status = wlan_power_ioctl_get_power(pmadapter, HostCmd_CMD_TXPWR_CFG, pioctl_req);
+            }
+            else
+            {
+                status = wlan_power_ioctl_set_power_ext(pmadapter, pioctl_req);
+            }
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+
+#if CONFIG_WMM_UAPSD
+/**
+ *  @brief Set/Get WMM QoS configuration
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success
+ */
+static mlan_status wlan_wmm_ioctl_qos(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_wmm_cfg *wmm = MNULL;
+
+    ENTER();
+
+    wmm = (mlan_ds_wmm_cfg *)pioctl_req->pbuf;
+
+    if (pioctl_req->action == MLAN_ACT_GET)
+        wmm->param.qos_cfg = pmpriv->wmm_qosinfo;
+    else
+    {
+        pmpriv->wmm_qosinfo = wmm->param.qos_cfg;
+    }
+
+    pioctl_req->data_read_written = sizeof(t_u8) + MLAN_SUB_COMMAND_SIZE;
+
+    LEAVE();
+    return ret;
+}
+#endif
+#if CONFIG_WMM_UAPSD
+#endif
+#if CONFIG_WMM_UAPSD
+/**
+ *  @brief WMM configuration handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_wmm_cfg_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status   = MLAN_STATUS_SUCCESS;
+    mlan_ds_wmm_cfg *wmm = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_wmm_cfg))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_wmm_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    wmm = (mlan_ds_wmm_cfg *)pioctl_req->pbuf;
+    switch (wmm->sub_command)
+    {
+        case MLAN_OID_WMM_CFG_QOS:
+            status = wlan_wmm_ioctl_qos(pmadapter, pioctl_req);
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+#endif
+
+/**
+ *  @brief Get Random charactor
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *
+ *  @return		random charactor
+ */
+t_u8 wlan_get_random_charactor(pmlan_adapter pmadapter)
+{
+    t_u32 sec, usec;
+    t_u32 ch_32 = 0;
+    t_u8 ch     = 0;
+
+    ENTER();
+
+    sec  = 10; // wmtime_time_get_posix();
+    usec = 0;
+
+    sec   = (sec & 0xFFFFU) + (sec >> 16);
+    usec  = (usec & 0xFFFFU) + (usec >> 16);
+    ch_32 = (((sec << 16) + usec) % 26U);
+    ch    = (t_u8)ch_32 + (t_u8)'a';
+
+    LEAVE();
+    return ch;
+}
+
+
+/**
+ *  @brief Set WEP keys
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+
+/**
+ *  @brief Set WPA key
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_sec_ioctl_set_wpa_key(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_sec_cfg *sec = MNULL;
+
+    ENTER();
+
+    sec = (mlan_ds_sec_cfg *)(void *)pioctl_req->pbuf;
+    /* Current driver only supports key length of up to 32 bytes */
+    if (sec->param.encrypt_key.key_len > MLAN_MAX_KEY_LENGTH)
+    {
+        PRINTM(MERROR, "Key length is incorrect\n");
+        pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+        ret                     = MLAN_STATUS_FAILURE;
+        goto exit;
+    }
+
+
+
+
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_802_11_KEY_MATERIAL, HostCmd_ACT_GEN_SET, 0, (t_void *)pioctl_req,
+                           &sec->param.encrypt_key);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+exit:
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief Set security key(s)
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_sec_ioctl_encrypt_key(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status   = MLAN_STATUS_SUCCESS;
+    mlan_ds_sec_cfg *sec = MNULL;
+    ENTER();
+    sec = (mlan_ds_sec_cfg *)(void *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+    {
+            if (sec->param.encrypt_key.key_len > MAX_WEP_KEY_SIZE)
+        {
+            status = wlan_sec_ioctl_set_wpa_key(pmadapter, pioctl_req);
+        }
+    }
+    else
+    {
+        /* fixme: enable when needed */
+        /* status = wlan_sec_ioctl_get_key(pmadapter, pioctl_req); */
+    }
+    LEAVE();
+    return status;
+}
+
+
+/**
+ *  @brief Set/Get WPA passphrase from embedded supplicant
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_sec_ioctl_passphrase(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_sec_cfg *sec = MNULL;
+    t_u16 cmd_action     = 0;
+    /* BSSDescriptor_t *pbss_desc; */
+    /* int i = 0; */
+
+    ENTER();
+
+    sec = (mlan_ds_sec_cfg *)(void *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+    {
+        if (sec->param.passphrase.psk_type == MLAN_PSK_CLEAR)
+        {
+            cmd_action = HostCmd_ACT_GEN_REMOVE;
+        }
+        else
+        {
+            cmd_action = HostCmd_ACT_GEN_SET;
+        }
+    }
+    else
+    {
+        if (sec->param.passphrase.psk_type == MLAN_PSK_QUERY)
+        {
+            if (sec->param.passphrase.ssid.ssid_len == 0U)
+            {
+                /* fixme: We do not need this functionality right now. */
+            }
+            else
+            {
+                (void)__memset(pmadapter, &sec->param.passphrase.bssid, 0, MLAN_MAC_ADDR_LENGTH);
+            }
+        }
+        cmd_action = HostCmd_ACT_GEN_GET;
+    }
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_SUPPLICANT_PMK, cmd_action, 0, (t_void *)pioctl_req,
+                           &sec->param.passphrase);
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief Set/Get WPA3 SAE password from embedded supplicant
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_sec_ioctl_password(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_sec_cfg *sec = MNULL;
+    t_u16 cmd_action     = 0;
+    /* BSSDescriptor_t *pbss_desc; */
+    /* int i = 0; */
+
+    ENTER();
+
+    sec = (mlan_ds_sec_cfg *)(void *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+    {
+        if (sec->param.passphrase.psk_type == MLAN_PSK_CLEAR)
+        {
+            cmd_action = HostCmd_ACT_GEN_REMOVE;
+        }
+        else
+        {
+            cmd_action = HostCmd_ACT_GEN_SET;
+        }
+    }
+    else
+    {
+        if (sec->param.passphrase.psk_type == MLAN_PSK_QUERY)
+        {
+            if (sec->param.passphrase.ssid.ssid_len == 0U)
+            {
+                /* fixme: We do not need this functionality right now. */
+            }
+            else
+            {
+                (void)__memset(pmadapter, &sec->param.passphrase.bssid, 0, MLAN_MAC_ADDR_LENGTH);
+            }
+        }
+        cmd_action = HostCmd_ACT_GEN_GET;
+    }
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_SUPPLICANT_PMK, cmd_action, 0, (t_void *)pioctl_req,
+                           &sec->param.passphrase);
+    if (ret == MLAN_STATUS_SUCCESS)
+    {
+        ret = MLAN_STATUS_PENDING;
+    }
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief Security configuration handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_sec_cfg_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status   = MLAN_STATUS_SUCCESS;
+    mlan_ds_sec_cfg *sec = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_sec_cfg))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_sec_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    sec = (mlan_ds_sec_cfg *)(void *)pioctl_req->pbuf;
+    switch (sec->sub_command)
+    {
+        case MLAN_OID_SEC_CFG_ENCRYPT_KEY:
+            status = wlan_sec_ioctl_encrypt_key(pmadapter, pioctl_req);
+            break;
+        case MLAN_OID_SEC_CFG_PASSPHRASE:
+            status = wlan_sec_ioctl_passphrase(pmadapter, pioctl_req);
+            break;
+        case MLAN_OID_SEC_CFG_PASSWORD:
+            status = wlan_sec_ioctl_password(pmadapter, pioctl_req);
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+
+
+/**
+ *  @brief 11D configuration handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_11d_cfg_ioctl(IN mlan_private *pmpriv, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_adapter *pmadapter   = pmpriv->adapter;
+    mlan_status status        = MLAN_STATUS_SUCCESS;
+    mlan_ds_11d_cfg *pcfg_11d = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_11d_cfg))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_11d_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        status                        = MLAN_STATUS_RESOURCE;
+        goto exit;
+    }
+
+    pcfg_11d = (mlan_ds_11d_cfg *)(void *)pioctl_req->pbuf;
+    switch (pcfg_11d->sub_command)
+    {
+        case MLAN_OID_11D_DOMAIN_INFO:
+            if (pmpriv->support_11d_APIs != NULL)
+            {
+                status = pmpriv->support_11d_APIs->wlan_11d_cfg_domain_info_p(pmadapter, pioctl_req);
+            }
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+
+exit:
+    LEAVE();
+    return status;
+}
+
+#if CONFIG_WPS2
+/**
+ *  @brief WPS configuration handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_wps_cfg_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status    = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv  = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_wps_cfg *pwps = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_wps_cfg))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_wps_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+
+    pwps = (mlan_ds_wps_cfg *)pioctl_req->pbuf;
+    switch (pwps->sub_command)
+    {
+        case MLAN_OID_WPS_CFG_SESSION:
+            if (pioctl_req->action == MLAN_ACT_SET)
+            {
+                if (pwps->param.wps_session == MLAN_WPS_CFG_SESSION_START)
+                    pmpriv->wps.session_enable = MTRUE;
+                else
+                    pmpriv->wps.session_enable = MFALSE;
+            }
+            else
+            {
+                pwps->param.wps_session       = (t_u32)pmpriv->wps.session_enable;
+                pioctl_req->data_read_written = sizeof(t_u32);
+                PRINTM(MINFO, "wpscfg GET=%d\n", pwps->param.wps_session);
+            }
+            break;
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+
+    LEAVE();
+    return status;
+}
+#endif /* CONFIG_WPS2 */
+
+
+       /**
+        *  @brief Set/Get region code
+        *
+        *  @param pmadapter	A pointer to mlan_adapter structure
+        *  @param pioctl_req	A pointer to ioctl request buffer
+        *
+        *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+        */
+/* static */ mlan_status wlan_misc_ioctl_region(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret        = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv   = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_misc_cfg *misc = MNULL;
+    int i;
+
+    ENTER();
+
+    misc = (mlan_ds_misc_cfg *)(void *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_GET)
+    {
+        misc->param.region_code = pmadapter->region_code;
+    }
+    else
+    {
+#ifdef OTP_CHANINFO
+        if (pmadapter->otp_region && pmadapter->otp_region->force_reg)
+        {
+            (void)PRINTF(
+                "ForceRegionRule is set in the on-chip OTP"
+                " memory\r\n");
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+#endif
+        for (i = 0; i < MRVDRV_MAX_REGION_CODE; i++)
+        {
+            /* Use the region code to search for the index */
+            if (misc->param.region_code == region_code_index[i])
+            {
+                pmadapter->region_code = (t_u16)misc->param.region_code;
+                break;
+            }
+        }
+        /* It's unidentified region code */
+        if (i >= MRVDRV_MAX_REGION_CODE)
+        {
+            PRINTM(MERROR, "Region Code not identified\n");
+            pioctl_req->status_code = MLAN_ERROR_INVALID_PARAMETER;
+            LEAVE();
+            return MLAN_STATUS_FAILURE;
+        }
+        pmadapter->cfp_code_bg = (t_u8)misc->param.region_code;
+        pmadapter->cfp_code_a  = (t_u8)misc->param.region_code;
+        if (wlan_set_regiontable(pmpriv, (t_u8)pmadapter->region_code,
+                                 (t_u16)(pmadapter->config_bands | pmadapter->adhoc_start_band)) != MLAN_STATUS_SUCCESS)
+        {
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_FAIL;
+            ret                     = MLAN_STATUS_FAILURE;
+        }
+    }
+    pioctl_req->data_read_written = sizeof(t_u32) + MLAN_SUB_COMMAND_SIZE;
+
+    LEAVE();
+    return ret;
+}
+
+
+#if CONFIG_GTK_REKEY_OFFLOAD
+/**
+ *  @brief Gtk Rekey Offload
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+static mlan_status wlan_misc_ioctl_gtk_rekey_offload(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret            = MLAN_STATUS_SUCCESS;
+    mlan_ds_misc_cfg *misc_cfg = MNULL;
+    t_u16 cmd_action           = 0;
+    mlan_private *pmpriv       = pmadapter->priv[pioctl_req->bss_index];
+
+    ENTER();
+    misc_cfg = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+        cmd_action = HostCmd_ACT_GEN_SET;
+    else if (pioctl_req->action == MLAN_ACT_CLEAR)
+        cmd_action = HostCmd_ACT_GEN_REMOVE;
+    else
+        cmd_action = HostCmd_ACT_GEN_GET;
+
+    if (!pmpriv->wpa_is_gtk_set)
+    {
+        /* Store the gtk rekey data if it has already set gtk */
+        (void)__memcpy(pmadapter, &pmpriv->gtk_rekey, &misc_cfg->param.gtk_rekey, sizeof(mlan_ds_misc_gtk_rekey_data));
+        LEAVE();
+        return ret;
+    }
+    /* Send request to firmware if it hasn't set gtk yet */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_CONFIG_GTK_REKEY_OFFLOAD_CFG, cmd_action, 0, (t_void *)pioctl_req,
+                           &misc_cfg->param.gtk_rekey);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+
+    LEAVE();
+    return ret;
+}
+#endif
+
+/**
+ *  @brief Get/Set subscribe event
+ *
+ *  @param pmadapter    A pointer to mlan_adapter structure
+ *  @param pioctl_req   A pointer to ioctl request buffer
+ *
+ *  @return             MLAN_STATUS_PENDING -- success, otherwise fail
+ */
+mlan_status wlan_misc_ioctl_subscribe_evt(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_private *pmpriv   = pmadapter->priv[pioctl_req->bss_index];
+    mlan_status ret        = MLAN_STATUS_SUCCESS;
+    mlan_ds_misc_cfg *misc = MNULL;
+    t_u16 cmd_action       = 0;
+
+    ENTER();
+
+    misc = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+    if (pioctl_req->action == MLAN_ACT_SET)
+    {
+        cmd_action = HostCmd_ACT_GEN_SET;
+    }
+    else
+    {
+        cmd_action = HostCmd_ACT_GEN_GET;
+    }
+
+    /* Send command to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_802_11_SUBSCRIBE_EVENT, cmd_action, 0, (t_void *)pioctl_req,
+                           &misc->param.subscribe_event);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief Miscellaneous configuration handler
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_misc_cfg_ioctl(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status status     = MLAN_STATUS_SUCCESS;
+    mlan_ds_misc_cfg *misc = MNULL;
+
+    ENTER();
+
+    if (pioctl_req->buf_len < sizeof(mlan_ds_misc_cfg))
+    {
+        PRINTM(MWARN, "MLAN bss IOCTL length is too short.\n");
+        pioctl_req->data_read_written = 0;
+        pioctl_req->buf_len_needed    = sizeof(mlan_ds_misc_cfg);
+        pioctl_req->status_code       = MLAN_ERROR_INVALID_PARAMETER;
+        LEAVE();
+        return MLAN_STATUS_RESOURCE;
+    }
+    if ((pioctl_req == MNULL) || (pioctl_req->pbuf == MNULL))
+    {
+        PRINTM(MERROR, "Request buffer not found!\n");
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    misc = (mlan_ds_misc_cfg *)(void *)pioctl_req->pbuf;
+    switch (misc->sub_command)
+    {
+        case MLAN_OID_MISC_REGION:
+            status = wlan_misc_ioctl_region(pmadapter, pioctl_req);
+            break;
+#if CONFIG_GTK_REKEY_OFFLOAD
+        case MLAN_OID_MISC_CONFIG_GTK_REKEY_OFFLOAD:
+            status = wlan_misc_ioctl_gtk_rekey_offload(pmadapter, pioctl_req);
+            break;
+#endif
+#if CONFIG_ROAMING
+        case MLAN_OID_MISC_SUBSCRIBE_EVENT:
+            status = wlan_misc_ioctl_subscribe_evt(pmadapter, pioctl_req);
+            break;
+#endif
+#ifdef WLAN_LOW_POWER_ENABLE
+        case MLAN_OID_MISC_LOW_PWR_MODE:
+            status = wlan_misc_ioctl_low_pwr_mode(pmadapter, pioctl_req);
+            break;
+#endif // WLAN_LOW_POWER_ENABLE
+#if CONFIG_WIFI_CLOCKSYNC
+        case MLAN_OID_MISC_GPIO_TSF_LATCH:
+            status = wlan_misc_gpio_tsf_latch_config(pmadapter, pioctl_req);
+            break;
+        case MLAN_OID_MISC_GET_TSF_INFO:
+            status = wlan_misc_get_tsf_info(pmadapter, pioctl_req);
+            break;
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+#if CONFIG_RF_TEST_MODE
+        case MLAN_OID_MISC_RF_TEST_GENERIC:
+        case MLAN_OID_MISC_RF_TEST_TX_CONT:
+        case MLAN_OID_MISC_RF_TEST_CONFIG_TRIGGER_FRAME:
+        case MLAN_OID_MISC_RF_TEST_TX_FRAME:
+        case MLAN_OID_MISC_RF_TEST_HE_POWER:
+            status = wlan_misc_ioctl_rf_test_cfg(pmadapter, pioctl_req);
+            break;
+#endif /* CONFIG_RF_TEST_MODE */
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+        case MLAN_OID_MISC_IND_RST_CFG:
+            status = wlan_misc_ioctl_ind_rst_cfg(pmadapter, pioctl_req);
+            break;
+#endif
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+
+            status = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
+
+
+
+/**
+ *  @brief MLAN station ioctl handler
+ *
+ *  @param adapter 	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_ops_sta_ioctl(t_void *adapter, pmlan_ioctl_req pioctl_req)
+{
+    pmlan_private pmpriv    = MNULL;
+    pmlan_adapter pmadapter = (pmlan_adapter)adapter;
+    mlan_status status      = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    if (pioctl_req != MNULL)
+    {
+        pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    }
+    else
+    {
+        PRINTM(MERROR, "MLAN IOCTL information is not present\n");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    switch (pioctl_req->req_id)
+    {
+        case MLAN_IOCTL_BSS:
+            status = wlan_bss_ioctl(pmadapter, pioctl_req);
+            break;
+        case MLAN_IOCTL_RADIO_CFG:
+            status = wlan_radio_ioctl(pmadapter, pioctl_req);
+            break;
+        case MLAN_IOCTL_SNMP_MIB:
+            status = wlan_snmp_mib_ioctl(pmadapter, pioctl_req);
+            break;
+        case MLAN_IOCTL_SEC_CFG:
+            status = wlan_sec_cfg_ioctl(pmadapter, pioctl_req);
+            break;
+        case MLAN_IOCTL_RATE:
+            status = wlan_rate_ioctl(pmadapter, pioctl_req);
+            break;
+        case MLAN_IOCTL_POWER_CFG:
+            status = wlan_power_ioctl(pmadapter, pioctl_req);
+            break;
+#if CONFIG_WMM_UAPSD
+        case MLAN_IOCTL_WMM_CFG:
+            status = wlan_wmm_cfg_ioctl(pmadapter, pioctl_req);
+            break;
+#endif
+#if CONFIG_WPS2
+        case MLAN_IOCTL_WPS_CFG:
+            status = wlan_wps_cfg_ioctl(pmadapter, pioctl_req);
+            break;
+#endif /* CONFIG_WPS2 */
+        case MLAN_IOCTL_11N_CFG:
+            status = wlan_11n_cfg_ioctl(pmadapter, pioctl_req);
+            break;
+        case MLAN_IOCTL_11D_CFG:
+            if (pmpriv->support_11d_APIs != NULL)
+            {
+                status = pmpriv->support_11d_APIs->wlan_11d_cfg_ioctl_p(pmpriv, pioctl_req);
+            }
+            break;
+        case MLAN_IOCTL_MISC_CFG:
+            status = wlan_misc_cfg_ioctl(pmadapter, pioctl_req);
+            break;
+#if CONFIG_11AX
+        case MLAN_IOCTL_11AX_CFG:
+            status = wlan_11ax_cfg_ioctl(pmadapter, pioctl_req);
+            break;
+#endif
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            status                  = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return status;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_rx.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_rx.c
new file mode 100644
index 0000000000..718884a7a8
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_sta_rx.c
@@ -0,0 +1,271 @@
+/** @file mlan_sta_rx.c
+ *
+ *  @brief  This file provides  handling of RX in MLA  module.
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    10/27/2008: initial version
+********************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+  Local Variables
+********************************************************/
+
+/** Ethernet II header */
+typedef struct
+{
+    /** Ethernet II header destination address */
+    t_u8 dest_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Ethernet II header source address */
+    t_u8 src_addr[MLAN_MAC_ADDR_LENGTH];
+    /** Ethernet II header length */
+    t_u16 ethertype;
+
+} EthII_Hdr_t;
+
+/** IPv4 ARP request header */
+typedef MLAN_PACK_START struct
+{
+    /** Hardware type */
+    t_u16 Htype;
+    /** Protocol type */
+    t_u16 Ptype;
+    /** Hardware address length */
+    t_u8 addr_len;
+    /** Protocol address length */
+    t_u8 proto_len;
+    /** Operation code */
+    t_u16 op_code;
+    /** Source mac address */
+    t_u8 src_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Sender IP address */
+    t_u8 src_ip[4];
+    /** Destination mac address */
+    t_u8 dst_mac[MLAN_MAC_ADDR_LENGTH];
+    /** Destination IP address */
+    t_u8 dst_ip[4];
+} MLAN_PACK_END IPv4_ARP_t;
+
+/** IPv6 Nadv packet header */
+typedef MLAN_PACK_START struct
+{
+    /** IP protocol version */
+    t_u8 version;
+    /** flow label */
+    t_u8 flow_lab[3];
+    /** Payload length */
+    t_u16 payload_len;
+    /** Next header type */
+    t_u8 next_hdr;
+    /** Hot limit */
+    t_u8 hop_limit;
+    /** Source address */
+    t_u8 src_addr[16];
+    /** Destination address */
+    t_u8 dst_addr[16];
+    /** ICMP type */
+    t_u8 icmp_type;
+    /** IPv6 Code */
+    t_u8 ipv6_code;
+    /** IPv6 Checksum */
+    t_u16 ipv6_checksum;
+    /** Flags */
+    t_u32 flags;
+    /** Target address */
+    t_u8 taget_addr[16];
+    /** Reserved */
+    t_u8 rev[8];
+} MLAN_PACK_END IPv6_Nadv_t;
+
+/********************************************************
+  Global Variables
+********************************************************/
+
+/********************************************************
+  Local Functions
+********************************************************/
+
+/********************************************************
+  Global functions
+********************************************************/
+/**
+ *  @brief This function processes received packet and forwards it
+ *  		to kernel/upper layer
+ *
+ *  @param pmadapter A pointer to mlan_adapter
+ *  @param pmbuf     A pointer to mlan_buffer which includes the received packet
+ *
+ *  @return 	   MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_process_rx_packet(pmlan_adapter pmadapter, pmlan_buffer pmbuf)
+{
+    mlan_status ret    = MLAN_STATUS_SUCCESS;
+    pmlan_private priv = pmadapter->priv[pmbuf->bss_index];
+    /* RxPacketHdr_t *prx_pkt; */
+    RxPD *prx_pd;
+    ENTER();
+
+    prx_pd = (RxPD *)(void *)(pmbuf->pbuf + pmbuf->data_offset);
+    /* Note: Important. We do not have actual data @ prx_pd->rx_pkt_offset */
+    /* prx_pkt = (RxPacketHdr_t *) ((t_u8 *) prx_pd + prx_pd->rx_pkt_offset); */
+    /* prx_pkt = (RxPacketHdr_t *)pmbuf->pdesc; */
+
+/** Small debug type */
+#define DBG_TYPE_SMALL 2
+/** Size of debugging structure */
+#define SIZE_OF_DBG_STRUCT 4
+    /*
+       This additional processing does not seem to be required by us for
+       the moment. Let skip it for now. They seem to be doing some kind of
+       ethernet header processing.
+    */
+
+    priv->rxpd_rate = prx_pd->rx_rate;
+#ifdef SD8801
+    priv->rxpd_htinfo = prx_pd->ht_info;
+#else
+    priv->rxpd_rate_info = prx_pd->rate_info;
+#endif
+
+    ret = pmadapter->callbacks.moal_recv_packet(pmadapter->pmoal_handle, pmbuf);
+    if (ret == MLAN_STATUS_FAILURE)
+    {
+        pmbuf->status_code = (t_u32)MLAN_ERROR_PKT_INVALID;
+        PRINTM(MERROR, "STA Rx Error: moal_recv_packet returned error\n");
+    }
+    /* done: */
+    if (ret != MLAN_STATUS_PENDING)
+    {
+        wlan_free_mlan_buffer(pmadapter, pmbuf);
+    }
+    LEAVE();
+
+    return ret;
+}
+
+/**
+ *   @brief This function processes the received buffer
+ *
+ *   @param adapter A pointer to mlan_adapter
+ *   @param pmbuf     A pointer to the received buffer
+ *
+ *   @return        MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ops_process_rx_packet(IN t_void *adapter, IN pmlan_buffer pmbuf)
+{
+    pmlan_adapter pmadapter = (pmlan_adapter)adapter;
+    mlan_status ret         = MLAN_STATUS_SUCCESS;
+    RxPD *prx_pd;
+    RxPacketHdr_t *prx_pkt;
+    pmlan_private priv            = pmadapter->priv[pmbuf->bss_index];
+    t_u8 ta[MLAN_MAC_ADDR_LENGTH] = {0};
+    t_u16 rx_pkt_type             = 0;
+    ENTER();
+    TxBAStreamTbl *ptx_tbl = NULL;
+
+    prx_pd = (RxPD *)(void *)(pmbuf->pbuf + pmbuf->data_offset);
+    /* Endian conversion */
+    endian_convert_RxPD(prx_pd);
+    rx_pkt_type = prx_pd->rx_pkt_type;
+
+    /* Note: We do not have data @ some offset of pbuf. pbuf only has RxPD */
+    /* prx_pkt = (RxPacketHdr_t *) ((t_u8 *) prx_pd + prx_pd->rx_pkt_offset); */
+    prx_pkt = (RxPacketHdr_t *)pmbuf->pdesc;
+
+    /* PRINTM(MMSG, "%p + %d: O: %d PL: %d DL: %d\n\r", */
+    /* 	     pmbuf->pbuf, pmbuf->data_offset, */
+    /* 	     prx_pd->rx_pkt_offset, prx_pd->rx_pkt_length, pmbuf->data_len); */
+
+    if ((prx_pd->rx_pkt_offset + prx_pd->rx_pkt_length) > (t_u16)pmbuf->data_len)
+    {
+        PRINTM(MERROR,
+               "Wrong rx packet: len=%d,rx_pkt_offset=%d,"
+               " rx_pkt_length=%d\n",
+               pmbuf->data_len, prx_pd->rx_pkt_offset, prx_pd->rx_pkt_length);
+        pmbuf->status_code = (t_u32)MLAN_ERROR_PKT_SIZE_INVALID;
+        ret                = MLAN_STATUS_FAILURE;
+        wlan_free_mlan_buffer(pmadapter, pmbuf);
+        goto done;
+    }
+    pmbuf->data_len = prx_pd->rx_pkt_offset + prx_pd->rx_pkt_length;
+
+    if (pmadapter->priv[pmbuf->bss_index]->mgmt_frame_passthru_mask && prx_pd->rx_pkt_type == PKT_TYPE_MGMT_FRAME)
+    {
+        /* Check if this is mgmt packet and needs to forwarded to app as an
+           event */
+        /* fixme */
+        wifi_e("Is a management packet expected here?");
+        while (true)
+        {
+            OSA_TimeDelay(10);
+        }
+    }
+
+#ifdef DUMP_PACKET_MAC
+    dump_mac_addr("Own: ", priv->curr_addr);
+    dump_mac_addr("Dest: ", prx_pkt->eth803_hdr.dest_addr);
+#endif /* DUMP_PACKET_MAC */
+
+    if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP)
+    {
+        /* txbastream table also is used as connected STAs data base */
+        ptx_tbl = wlan_11n_get_txbastream_tbl(priv, prx_pkt->eth803_hdr.src_addr);
+    }
+
+    /*
+     * If 11n isn't enabled, or if the packet is not an unicast packet for STA case,
+     * then send the packet directly to os. Don't pass thru rx reordering
+     */
+    if (((GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_STA) &&
+         ((!IS_11N_ENABLED(priv)) ||
+          __memcmp(priv->adapter, priv->curr_addr, prx_pkt->eth803_hdr.dest_addr, MLAN_MAC_ADDR_LENGTH))) ||
+        ((GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP) && ptx_tbl && (!ptx_tbl->ampdu_supported[0])))
+    {
+        (void)wlan_process_rx_packet(pmadapter, pmbuf);
+        goto done;
+    }
+
+    if (queuing_ra_based(priv) == MTRUE)
+    {
+        if ((GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP) && ptx_tbl && (rx_pkt_type != PKT_TYPE_BAR) &&
+            (prx_pd->priority < MAX_NUM_TID))
+        {
+            ptx_tbl->rx_seq[prx_pd->priority] = prx_pd->seq_num;
+        }
+        (void)__memcpy(pmadapter, ta, prx_pkt->eth803_hdr.src_addr, MLAN_MAC_ADDR_LENGTH);
+    }
+    else
+    {
+        if ((rx_pkt_type != PKT_TYPE_BAR) && (prx_pd->priority < MAX_NUM_TID))
+        {
+            priv->rx_seq[prx_pd->priority] = prx_pd->seq_num;
+        }
+        (void)__memcpy(pmadapter, ta, priv->curr_bss_params.bss_descriptor.mac_address, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    /* Reorder and send to OS */
+    if ((ret = mlan_11n_rxreorder_pkt(priv, prx_pd->seq_num, prx_pd->priority, ta, (t_u8)prx_pd->rx_pkt_type,
+                                      (void *)pmbuf)) ||
+        (rx_pkt_type == PKT_TYPE_BAR))
+    {
+        wlan_free_mlan_buffer(pmadapter, pmbuf);
+    }
+
+done:
+
+    LEAVE();
+    return (ret);
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_txrx.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_txrx.c
new file mode 100644
index 0000000000..d2700c19b6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_txrx.c
@@ -0,0 +1,82 @@
+/** @file mlan_txrx.c
+ *
+ *  @brief  This file provides the handling of TX/RX in MLAN
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*************************************************************
+Change Log:
+    05/11/2009: initial version
+************************************************************/
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+                Local Variables
+********************************************************/
+
+/********************************************************
+                Global Variables
+********************************************************/
+
+/********************************************************
+                Local Functions
+********************************************************/
+
+/********************************************************
+                Global Functions
+********************************************************/
+/**
+ *   @brief This function processes the received buffer
+ *
+ *   @param pmadapter A pointer to mlan_adapter
+ *   @param pmbuf     A pointer to the received buffer
+ *
+ *   @return        MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_handle_rx_packet(pmlan_adapter pmadapter, pmlan_buffer pmbuf)
+{
+    mlan_status ret    = MLAN_STATUS_SUCCESS;
+    pmlan_private priv = wlan_get_priv(pmadapter, MLAN_BSS_ROLE_ANY);
+    RxPD *prx_pd;
+#ifdef DEBUG_LEVEL1
+    t_u32 sec, usec;
+#endif
+
+    ENTER();
+
+    prx_pd = (RxPD *)(void *)(pmbuf->pbuf + pmbuf->data_offset);
+    /* Get the BSS number from RxPD, get corresponding priv */
+    priv = wlan_get_priv_by_id(pmadapter, prx_pd->bss_num & BSS_NUM_MASK, prx_pd->bss_type);
+    if (priv == MNULL)
+    {
+        priv = wlan_get_priv(pmadapter, MLAN_BSS_ROLE_ANY);
+    }
+    pmbuf->bss_index = priv->bss_index;
+    PRINTM_GET_SYS_TIME(MDATA, &sec, &usec);
+    PRINTM_NETINTF(MDATA, priv);
+    /* PRINTM(MDATA, "%lu.%06lu : Data <= FW\n", sec, usec); */
+    ret = priv->ops.process_rx_packet(pmadapter, pmbuf);
+
+    LEAVE();
+    return ret;
+}
+
+/**
+ *  @brief This function checks the conditions and sends packet to device
+ *
+ *  @param priv	   A pointer to mlan_private structure
+ *  @param pmbuf   A pointer to the mlan_buffer for process
+ *  @param tx_param A pointer to mlan_tx_param structure
+ *
+ *  @return 	    MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise failure
+ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_uap_cmdevent.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_uap_cmdevent.c
new file mode 100644
index 0000000000..e32c984be4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_uap_cmdevent.c
@@ -0,0 +1,1393 @@
+/** @file mlan_uap_cmdevent.c
+ *
+ *  @brief  This file provides the handling of AP mode command and event
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    02/05/2009: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+
+/**
+ *  @brief This function prepares command for config uap settings
+ *
+ *  @param pmpriv		A pointer to mlan_private structure
+ *  @param cmd	   		A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *  @return         MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_uap_cmd_ap_config(pmlan_private pmpriv,
+                                          IN HostCmd_DS_COMMAND *cmd,
+                                          IN t_u16 cmd_action,
+                                          IN pmlan_ioctl_req pioctl_buf)
+{
+    mlan_ds_bss *bss                               = MNULL;
+    HostCmd_DS_SYS_CONFIG *sys_config              = (HostCmd_DS_SYS_CONFIG *)&cmd->params.sys_config;
+    t_u8 *tlv                                      = MNULL;
+    MrvlIEtypes_MacAddr_t *tlv_mac                 = MNULL;
+    MrvlIEtypes_SsIdParamSet_t *tlv_ssid           = MNULL;
+    MrvlIEtypes_beacon_period_t *tlv_beacon_period = MNULL;
+    MrvlIEtypes_ecsa_config_t *tlv_ecsa_config     = MNULL;
+    MrvlIEtypes_dtim_period_t *tlv_dtim_period     = MNULL;
+    MrvlIEtypes_RatesParamSet_t *tlv_rates         = MNULL;
+    MrvlIEtypes_bcast_ssid_t *tlv_bcast_ssid = MNULL;
+    MrvlIEtypes_auth_type_t *tlv_auth_type               = MNULL;
+    MrvlIEtypes_channel_band_t *tlv_chan_band            = MNULL;
+    MrvlIEtypes_ChanListParamSet_t *tlv_chan_list        = MNULL;
+    ChanScanParamSet_t *pscan_chan                       = MNULL;
+    MrvlIEtypes_encrypt_protocol_t *tlv_encrypt_protocol = MNULL;
+    MrvlIEtypes_akmp_t *tlv_akmp                         = MNULL;
+    MrvlIEtypes_pwk_cipher_t *tlv_pwk_cipher             = MNULL;
+    MrvlIEtypes_gwk_cipher_t *tlv_gwk_cipher             = MNULL;
+    MrvlIEtypes_passphrase_t *tlv_passphrase = MNULL;
+    MrvlIEtypes_password_t *tlv_password     = MNULL;
+    MrvlIEtypes_wmm_parameter_t *tlv_wmm_parameter = MNULL;
+    MrvlIETypes_HTCap_t *tlv_htcap = MNULL;
+    t_u32 cmd_size  = 0;
+    t_u8 zero_mac[] = {0, 0, 0, 0, 0, 0};
+    t_u16 i;
+    t_u16 ac;
+
+    ENTER();
+    if (pioctl_buf == MNULL)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    bss = (mlan_ds_bss *)(void *)pioctl_buf->pbuf;
+
+    cmd->command       = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    sys_config->action = wlan_cpu_to_le16(cmd_action);
+    cmd_size           = sizeof(HostCmd_DS_SYS_CONFIG) - 1U + S_DS_GEN;
+
+    tlv = (t_u8 *)sys_config->tlv_buffer;
+    if (__memcmp(pmpriv->adapter, zero_mac, &bss->param.bss_config.mac_addr, MLAN_MAC_ADDR_LENGTH) != 0)
+    {
+        tlv_mac              = (MrvlIEtypes_MacAddr_t *)(void *)tlv;
+        tlv_mac->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_MAC_ADDRESS);
+        tlv_mac->header.len  = wlan_cpu_to_le16(MLAN_MAC_ADDR_LENGTH);
+        (void)__memcpy(pmpriv->adapter, tlv_mac->mac, &bss->param.bss_config.mac_addr, MLAN_MAC_ADDR_LENGTH);
+        cmd_size += sizeof(MrvlIEtypes_MacAddr_t);
+        tlv += sizeof(MrvlIEtypes_MacAddr_t);
+    }
+
+    if (bss->param.bss_config.ssid.ssid_len != 0U)
+    {
+        tlv_ssid              = (MrvlIEtypes_SsIdParamSet_t *)(void *)tlv;
+        tlv_ssid->header.type = wlan_cpu_to_le16(TLV_TYPE_SSID);
+        tlv_ssid->header.len  = wlan_cpu_to_le16((t_u16)bss->param.bss_config.ssid.ssid_len);
+        (void)__memcpy(pmpriv->adapter, tlv_ssid->ssid, bss->param.bss_config.ssid.ssid,
+                       bss->param.bss_config.ssid.ssid_len);
+        cmd_size += sizeof(MrvlIEtypesHeader_t) + bss->param.bss_config.ssid.ssid_len;
+        tlv += sizeof(MrvlIEtypesHeader_t) + bss->param.bss_config.ssid.ssid_len;
+    }
+
+    if ((bss->param.bss_config.beacon_period >= MIN_BEACON_PERIOD) &&
+        (bss->param.bss_config.beacon_period <= MAX_BEACON_PERIOD))
+    {
+        tlv_beacon_period                = (MrvlIEtypes_beacon_period_t *)(void *)tlv;
+        tlv_beacon_period->header.type   = wlan_cpu_to_le16(TLV_TYPE_UAP_BEACON_PERIOD);
+        tlv_beacon_period->header.len    = wlan_cpu_to_le16(sizeof(t_u16));
+        tlv_beacon_period->beacon_period = wlan_cpu_to_le16(bss->param.bss_config.beacon_period);
+        cmd_size += sizeof(MrvlIEtypes_beacon_period_t);
+        tlv += sizeof(MrvlIEtypes_beacon_period_t);
+    }
+
+    if ((bss->param.bss_config.chan_sw_count >= MIN_CHSW_COUNT) &&
+        (bss->param.bss_config.chan_sw_count <= MAX_CHSW_COUNT))
+    {
+        tlv_ecsa_config                     = (MrvlIEtypes_ecsa_config_t *)(void *)tlv;
+        tlv_ecsa_config->header.type        = wlan_cpu_to_le16(TLV_TYPE_UAP_ECSA_CONFIG);
+        tlv_ecsa_config->header.len         = wlan_cpu_to_le16(sizeof(t_u16) + sizeof(t_u8) + sizeof(t_u8));
+        tlv_ecsa_config->enable             = 1;
+        tlv_ecsa_config->ChannelSwitchMode  = 0;
+        tlv_ecsa_config->ChannelSwitchCount = bss->param.bss_config.chan_sw_count;
+        cmd_size += sizeof(MrvlIEtypes_ecsa_config_t);
+        tlv += sizeof(MrvlIEtypes_ecsa_config_t);
+    }
+
+    if ((bss->param.bss_config.dtim_period >= MIN_DTIM_PERIOD) &&
+        (bss->param.bss_config.dtim_period <= MAX_DTIM_PERIOD))
+    {
+        tlv_dtim_period              = (MrvlIEtypes_dtim_period_t *)(void *)tlv;
+        tlv_dtim_period->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_DTIM_PERIOD);
+        tlv_dtim_period->header.len  = wlan_cpu_to_le16(sizeof(t_u8));
+        tlv_dtim_period->dtim_period = bss->param.bss_config.dtim_period;
+        cmd_size += sizeof(MrvlIEtypes_dtim_period_t);
+        tlv += sizeof(MrvlIEtypes_dtim_period_t);
+    }
+
+    if (bss->param.bss_config.rates[0] != 0U)
+    {
+        tlv_rates              = (MrvlIEtypes_RatesParamSet_t *)(void *)tlv;
+        tlv_rates->header.type = wlan_cpu_to_le16(TLV_TYPE_RATES);
+        for (i = 0; i < MAX_DATA_RATES && bss->param.bss_config.rates[i]; i++)
+        {
+            tlv_rates->rates[i] = bss->param.bss_config.rates[i];
+        }
+        tlv_rates->header.len = wlan_cpu_to_le16(i);
+        cmd_size += sizeof(MrvlIEtypesHeader_t) + i;
+        tlv += sizeof(MrvlIEtypesHeader_t) + i;
+    }
+
+
+    if (bss->param.bss_config.bcast_ssid_ctl <= MAX_BCAST_SSID_CTL)
+    {
+        tlv_bcast_ssid                 = (MrvlIEtypes_bcast_ssid_t *)(void *)tlv;
+        tlv_bcast_ssid->header.type    = wlan_cpu_to_le16(TLV_TYPE_UAP_BCAST_SSID_CTL);
+        tlv_bcast_ssid->header.len     = wlan_cpu_to_le16(sizeof(t_u8));
+        tlv_bcast_ssid->bcast_ssid_ctl = bss->param.bss_config.bcast_ssid_ctl;
+        cmd_size += sizeof(MrvlIEtypes_bcast_ssid_t);
+        tlv += sizeof(MrvlIEtypes_bcast_ssid_t);
+    }
+
+
+    if ((((bss->param.bss_config.band_cfg & BAND_CONFIG_ACS_MODE) == BAND_CONFIG_MANUAL) &&
+         (bss->param.bss_config.channel > 0U) && (bss->param.bss_config.channel <= MLAN_MAX_CHANNEL)) ||
+        (bss->param.bss_config.band_cfg & BAND_CONFIG_ACS_MODE))
+    {
+        tlv_chan_band              = (MrvlIEtypes_channel_band_t *)(void *)tlv;
+        tlv_chan_band->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_CHAN_BAND_CONFIG);
+        tlv_chan_band->header.len  = wlan_cpu_to_le16(sizeof(t_u8) + sizeof(t_u8));
+        tlv_chan_band->band_config = bss->param.bss_config.band_cfg;
+        tlv_chan_band->channel     = bss->param.bss_config.channel;
+        cmd_size += sizeof(MrvlIEtypes_channel_band_t);
+        tlv += sizeof(MrvlIEtypes_channel_band_t);
+    }
+
+    if ((bss->param.bss_config.num_of_chan) && (bss->param.bss_config.num_of_chan <= MLAN_MAX_CHANNEL))
+    {
+        tlv_chan_list              = (MrvlIEtypes_ChanListParamSet_t *)(void *)tlv;
+        tlv_chan_list->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+        tlv_chan_list->header.len =
+            wlan_cpu_to_le16((t_u16)(sizeof(ChanScanParamSet_t) * bss->param.bss_config.num_of_chan));
+        pscan_chan = tlv_chan_list->chan_scan_param;
+        for (i = 0; i < bss->param.bss_config.num_of_chan; i++)
+        {
+            (void)__memset(pmpriv->adapter, pscan_chan, 0x00, sizeof(ChanScanParamSet_t));
+            pscan_chan->chan_number = bss->param.bss_config.chan_list[i].chan_number;
+            pscan_chan->radio_type  = bss->param.bss_config.chan_list[i].band_config_type;
+            pscan_chan++;
+        }
+        cmd_size += sizeof(tlv_chan_list->header) + (sizeof(ChanScanParamSet_t) * bss->param.bss_config.num_of_chan);
+        tlv += sizeof(tlv_chan_list->header) + (sizeof(ChanScanParamSet_t) * bss->param.bss_config.num_of_chan);
+    }
+
+    if ((bss->param.bss_config.auth_mode <= MLAN_AUTH_MODE_SHARED) ||
+        (bss->param.bss_config.auth_mode == MLAN_AUTH_MODE_AUTO))
+    {
+        tlv_auth_type                 = (MrvlIEtypes_auth_type_t *)tlv;
+        tlv_auth_type->header.type    = wlan_cpu_to_le16(TLV_TYPE_AUTH_TYPE);
+        tlv_auth_type->header.len     = wlan_cpu_to_le16(sizeof(MrvlIEtypes_auth_type_t) - sizeof(MrvlIEtypesHeader_t));
+        tlv_auth_type->auth_type      = (t_u8)bss->param.bss_config.auth_mode;
+        tlv_auth_type->PWE_derivation = (t_u8)bss->param.bss_config.pwe_derivation;
+        tlv_auth_type->transition_disable = (t_u8)bss->param.bss_config.transition_disable;
+        cmd_size += sizeof(MrvlIEtypes_auth_type_t);
+        tlv += sizeof(MrvlIEtypes_auth_type_t);
+    }
+
+    if (bss->param.bss_config.protocol != 0U)
+    {
+        tlv_encrypt_protocol              = (MrvlIEtypes_encrypt_protocol_t *)(void *)tlv;
+        tlv_encrypt_protocol->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_ENCRYPT_PROTOCOL);
+        tlv_encrypt_protocol->header.len  = wlan_cpu_to_le16(sizeof(t_u16));
+        tlv_encrypt_protocol->protocol    = wlan_cpu_to_le16(bss->param.bss_config.protocol);
+        cmd_size += sizeof(MrvlIEtypes_encrypt_protocol_t);
+        tlv += sizeof(MrvlIEtypes_encrypt_protocol_t);
+    }
+
+    if ((bss->param.bss_config.protocol & PROTOCOL_WPA) || (bss->param.bss_config.protocol & PROTOCOL_WPA2) ||
+        (bss->param.bss_config.protocol & PROTOCOL_WPA3_SAE) ||
+#if CONFIG_DRIVER_OWE
+        (bss->param.bss_config.protocol & PROTOCOL_OWE) ||
+#endif
+        (bss->param.bss_config.protocol & PROTOCOL_EAP))
+    {
+        tlv_akmp                     = (MrvlIEtypes_akmp_t *)(void *)tlv;
+        tlv_akmp->header.type        = wlan_cpu_to_le16(TLV_TYPE_UAP_AKMP);
+        tlv_akmp->key_mgmt           = wlan_cpu_to_le16(bss->param.bss_config.key_mgmt);
+        tlv_akmp->header.len         = (t_u16)sizeof(t_u16);
+        tlv_akmp->key_mgmt_operation = wlan_cpu_to_le16(bss->param.bss_config.key_mgmt_operation);
+        tlv_akmp->header.len += (t_u16)sizeof(t_u16);
+        tlv_akmp->header.len = wlan_cpu_to_le16(tlv_akmp->header.len);
+        cmd_size += sizeof(MrvlIEtypes_akmp_t);
+        tlv += sizeof(MrvlIEtypes_akmp_t);
+
+        if ((bss->param.bss_config.wpa_cfg.pairwise_cipher_wpa & VALID_CIPHER_BITMAP) != 0U)
+        {
+            tlv_pwk_cipher                  = (MrvlIEtypes_pwk_cipher_t *)(void *)tlv;
+            tlv_pwk_cipher->header.type     = wlan_cpu_to_le16(TLV_TYPE_PWK_CIPHER);
+            tlv_pwk_cipher->header.len      = wlan_cpu_to_le16(sizeof(t_u16) + sizeof(t_u8) + sizeof(t_u8));
+            tlv_pwk_cipher->protocol        = wlan_cpu_to_le16(PROTOCOL_WPA);
+            tlv_pwk_cipher->pairwise_cipher = bss->param.bss_config.wpa_cfg.pairwise_cipher_wpa;
+            cmd_size += sizeof(MrvlIEtypes_pwk_cipher_t);
+            tlv += sizeof(MrvlIEtypes_pwk_cipher_t);
+        }
+
+        if ((bss->param.bss_config.wpa_cfg.pairwise_cipher_wpa2 & VALID_CIPHER_BITMAP) != 0U)
+        {
+            tlv_pwk_cipher              = (MrvlIEtypes_pwk_cipher_t *)(void *)tlv;
+            tlv_pwk_cipher->header.type = wlan_cpu_to_le16(TLV_TYPE_PWK_CIPHER);
+            tlv_pwk_cipher->header.len  = wlan_cpu_to_le16(sizeof(t_u16) + sizeof(t_u8) + sizeof(t_u8));
+            if ((bss->param.bss_config.protocol & PROTOCOL_WPA3_SAE) != 0U)
+            {
+                tlv_pwk_cipher->protocol = wlan_cpu_to_le16(PROTOCOL_WPA3_SAE);
+            }
+            else
+            {
+                tlv_pwk_cipher->protocol = wlan_cpu_to_le16(PROTOCOL_WPA2);
+            }
+            tlv_pwk_cipher->pairwise_cipher = bss->param.bss_config.wpa_cfg.pairwise_cipher_wpa2;
+            cmd_size += sizeof(MrvlIEtypes_pwk_cipher_t);
+            tlv += sizeof(MrvlIEtypes_pwk_cipher_t);
+        }
+
+        if ((bss->param.bss_config.wpa_cfg.group_cipher & VALID_CIPHER_BITMAP) != 0U)
+        {
+            tlv_gwk_cipher               = (MrvlIEtypes_gwk_cipher_t *)(void *)tlv;
+            tlv_gwk_cipher->header.type  = wlan_cpu_to_le16(TLV_TYPE_GWK_CIPHER);
+            tlv_gwk_cipher->header.len   = wlan_cpu_to_le16(sizeof(t_u8) + sizeof(t_u8));
+            tlv_gwk_cipher->group_cipher = bss->param.bss_config.wpa_cfg.group_cipher;
+            cmd_size += sizeof(MrvlIEtypes_gwk_cipher_t);
+            tlv += sizeof(MrvlIEtypes_gwk_cipher_t);
+        }
+
+
+        if (bss->param.bss_config.wpa_cfg.length != 0U)
+        {
+            tlv_passphrase              = (MrvlIEtypes_passphrase_t *)(void *)tlv;
+            tlv_passphrase->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_WPA_PASSPHRASE);
+            tlv_passphrase->header.len  = (t_u16)wlan_cpu_to_le16(bss->param.bss_config.wpa_cfg.length);
+            (void)__memcpy(pmpriv->adapter, tlv_passphrase->passphrase, bss->param.bss_config.wpa_cfg.passphrase,
+                           bss->param.bss_config.wpa_cfg.length);
+            cmd_size += sizeof(MrvlIEtypesHeader_t) + bss->param.bss_config.wpa_cfg.length;
+            tlv += sizeof(MrvlIEtypesHeader_t) + bss->param.bss_config.wpa_cfg.length;
+        }
+
+        if (bss->param.bss_config.wpa_cfg.password_length != 0U)
+        {
+            tlv_password              = (MrvlIEtypes_password_t *)(void *)tlv;
+            tlv_password->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_WPA3_SAE_PASSWORD);
+            tlv_password->header.len  = (t_u16)wlan_cpu_to_le16(bss->param.bss_config.wpa_cfg.password_length);
+            (void)__memcpy(pmpriv->adapter, tlv_password->password, bss->param.bss_config.wpa_cfg.password,
+                           bss->param.bss_config.wpa_cfg.password_length);
+            cmd_size += sizeof(MrvlIEtypesHeader_t) + bss->param.bss_config.wpa_cfg.password_length;
+            tlv += sizeof(MrvlIEtypesHeader_t) + bss->param.bss_config.wpa_cfg.password_length;
+        }
+
+    }
+    else
+    {
+    }
+
+    if ((bss->param.bss_config.ht_cap_info) != 0U)
+    {
+        /* wmsdk: All the values received will be zero by default. */
+        tlv_htcap                     = (MrvlIETypes_HTCap_t *)(void *)tlv;
+        tlv_htcap->header.type        = wlan_cpu_to_le16(HT_CAPABILITY);
+        tlv_htcap->header.len         = wlan_cpu_to_le16(sizeof(HTCap_t));
+        tlv_htcap->ht_cap.ht_cap_info = wlan_cpu_to_le16(bss->param.bss_config.ht_cap_info);
+        tlv_htcap->ht_cap.ampdu_param = bss->param.bss_config.ampdu_param;
+        (void)__memcpy(pmpriv->adapter, tlv_htcap->ht_cap.supported_mcs_set, bss->param.bss_config.supported_mcs_set,
+                       16);
+#if CONFIG_WIFI_CAPA
+        /* Disable 802.11n */
+        if (!pmpriv->adapter->usr_dot_11n_enable)
+        {
+            tlv_htcap->ht_cap.supported_mcs_set[0] = 0;
+            tlv_htcap->ht_cap.supported_mcs_set[4] = 0;
+        }
+#endif
+        tlv_htcap->ht_cap.ht_ext_cap = wlan_cpu_to_le16(bss->param.bss_config.ht_ext_cap);
+        tlv_htcap->ht_cap.tx_bf_cap  = wlan_cpu_to_le32(bss->param.bss_config.tx_bf_cap);
+        tlv_htcap->ht_cap.asel       = bss->param.bss_config.asel;
+        cmd_size += sizeof(MrvlIETypes_HTCap_t);
+        tlv += sizeof(MrvlIETypes_HTCap_t);
+    }
+
+
+    if ((bss->param.bss_config.uap_host_based_config == MTRUE) ||
+        (bss->param.bss_config.wmm_para.qos_info & 0x80 || bss->param.bss_config.wmm_para.qos_info == 0x00))
+    {
+        tlv_wmm_parameter              = (MrvlIEtypes_wmm_parameter_t *)tlv;
+        tlv_wmm_parameter->header.type = wlan_cpu_to_le16(TLV_TYPE_VENDOR_SPECIFIC_IE);
+        tlv_wmm_parameter->header.len  = wlan_cpu_to_le16(sizeof(bss->param.bss_config.wmm_para));
+        (void)__memcpy(pmpriv->adapter, tlv_wmm_parameter->wmm_para.ouitype, bss->param.bss_config.wmm_para.ouitype,
+                       sizeof(tlv_wmm_parameter->wmm_para.ouitype));
+        tlv_wmm_parameter->wmm_para.ouisubtype = bss->param.bss_config.wmm_para.ouisubtype;
+        tlv_wmm_parameter->wmm_para.version    = bss->param.bss_config.wmm_para.version;
+        tlv_wmm_parameter->wmm_para.qos_info   = bss->param.bss_config.wmm_para.qos_info;
+        tlv_wmm_parameter->wmm_para.reserved   = 0x00;
+        for (ac = 0; ac < 4; ac++)
+        {
+            tlv_wmm_parameter->wmm_para.ac_params[ac].aci_aifsn.aifsn =
+                bss->param.bss_config.wmm_para.ac_params[ac].aci_aifsn.aifsn;
+            tlv_wmm_parameter->wmm_para.ac_params[ac].aci_aifsn.acm =
+                bss->param.bss_config.wmm_para.ac_params[ac].aci_aifsn.acm;
+            tlv_wmm_parameter->wmm_para.ac_params[ac].aci_aifsn.aci =
+                bss->param.bss_config.wmm_para.ac_params[ac].aci_aifsn.aci;
+            tlv_wmm_parameter->wmm_para.ac_params[ac].ecw.ecw_max =
+                bss->param.bss_config.wmm_para.ac_params[ac].ecw.ecw_max;
+            tlv_wmm_parameter->wmm_para.ac_params[ac].ecw.ecw_min =
+                bss->param.bss_config.wmm_para.ac_params[ac].ecw.ecw_min;
+            tlv_wmm_parameter->wmm_para.ac_params[ac].tx_op_limit =
+                wlan_cpu_to_le16(bss->param.bss_config.wmm_para.ac_params[ac].tx_op_limit);
+        }
+        cmd_size += sizeof(MrvlIEtypes_wmm_parameter_t);
+        tlv += sizeof(MrvlIEtypes_wmm_parameter_t);
+    }
+
+    cmd->size = (t_u16)wlan_cpu_to_le16(cmd_size);
+    PRINTM(MCMND, "AP config: cmd_size=%d\n", cmd_size);
+#if CONFIG_WIFI_EXTRA_DEBUG
+    PRINTF("wlan_uap_cmd_ap_config : cmd\r\n");
+    dump_hex(cmd, cmd->size);
+#endif
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of sys_config
+ *
+ *  @param pmpriv		A pointer to mlan_private structure
+ *  @param cmd	   		A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *  @return         MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_uap_cmd_sys_configure(pmlan_private pmpriv,
+                                              IN HostCmd_DS_COMMAND *cmd,
+                                              IN t_u16 cmd_action,
+                                              IN pmlan_ioctl_req pioctl_buf,
+                                              IN t_void *pdata_buf)
+{
+    mlan_ds_bss *bss                          = MNULL;
+    HostCmd_DS_SYS_CONFIG *sys_config         = (HostCmd_DS_SYS_CONFIG *)&cmd->params.sys_config;
+    MrvlIEtypes_channel_band_t *chan_band_tlv = MNULL, *pdat_tlv_cb = MNULL;
+    MrvlIEtypes_max_sta_count_t *max_sta_cnt_tlv = MNULL, *pdat_tlv_ccb = MNULL;
+    mlan_ds_misc_custom_ie *cust_ie = MNULL;
+    MrvlIEtypesHeader_t *ie_header  = (MrvlIEtypesHeader_t *)sys_config->tlv_buffer;
+    t_u8 *ie                        = (t_u8 *)sys_config->tlv_buffer + sizeof(MrvlIEtypesHeader_t);
+    t_u16 req_len = 0, travel_len = 0;
+    custom_ie *cptr = MNULL;
+
+#if CONFIG_ECSA
+    MrvlIEtypes_action_chan_switch_t *tlv_chan_switch = MNULL;
+    IEEEtypes_ChanSwitchAnn_t *csa_ie                 = MNULL;
+    IEEEtypes_ExtChanSwitchAnn_t *ecsa_ie             = MNULL;
+#endif
+
+    mlan_status ret = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+
+    cmd->command       = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    sys_config->action = wlan_cpu_to_le16(cmd_action);
+    cmd->size          = wlan_cpu_to_le16(sizeof(HostCmd_DS_SYS_CONFIG) - 1U + S_DS_GEN);
+    if (pioctl_buf == MNULL)
+    {
+        if (pdata_buf != NULL)
+        {
+            switch (*(t_u16 *)pdata_buf)
+            {
+                case TLV_TYPE_UAP_CHAN_BAND_CONFIG:
+                    pdat_tlv_cb                = (MrvlIEtypes_channel_band_t *)pdata_buf;
+                    chan_band_tlv              = (MrvlIEtypes_channel_band_t *)(void *)sys_config->tlv_buffer;
+                    cmd->size                  = wlan_cpu_to_le16(sizeof(HostCmd_DS_SYS_CONFIG) - 1U + S_DS_GEN +
+                                                                  sizeof(MrvlIEtypes_channel_band_t));
+                    chan_band_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_CHAN_BAND_CONFIG);
+                    chan_band_tlv->header.len =
+                        wlan_cpu_to_le16(sizeof(MrvlIEtypes_channel_band_t) - sizeof(MrvlIEtypesHeader_t));
+                    if (cmd_action != 0U)
+                    {
+                        chan_band_tlv->band_config = pdat_tlv_cb->band_config;
+                        chan_band_tlv->channel     = pdat_tlv_cb->channel;
+                    }
+                    ret = MLAN_STATUS_SUCCESS;
+                    break;
+                case TLV_TYPE_UAP_MAX_STA_CNT:
+                    pdat_tlv_ccb                 = (MrvlIEtypes_max_sta_count_t *)pdata_buf;
+                    max_sta_cnt_tlv              = (MrvlIEtypes_max_sta_count_t *)(void *)sys_config->tlv_buffer;
+                    cmd->size                    = wlan_cpu_to_le16(sizeof(HostCmd_DS_SYS_CONFIG) - 1U + S_DS_GEN +
+                                                                    sizeof(MrvlIEtypes_max_sta_count_t));
+                    max_sta_cnt_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_MAX_STA_CNT);
+
+                    if (cmd_action != 0U)
+                    {
+                        max_sta_cnt_tlv->header.len =
+                            wlan_cpu_to_le16(sizeof(MrvlIEtypes_max_sta_count_t) - sizeof(MrvlIEtypesHeader_t));
+                        max_sta_cnt_tlv->max_sta_count = pdat_tlv_ccb->max_sta_count;
+                    }
+                    else
+                    {
+                        max_sta_cnt_tlv->header.len    = 0;
+                        max_sta_cnt_tlv->max_sta_count = 0;
+                    }
+                    ret = MLAN_STATUS_SUCCESS;
+                    break;
+                case TLV_TYPE_MGMT_IE:
+                    cust_ie         = (mlan_ds_misc_custom_ie *)pdata_buf;
+                    cmd->size       = wlan_cpu_to_le16(sizeof(HostCmd_DS_SYS_CONFIG) - 1 + S_DS_GEN +
+                                                       sizeof(MrvlIEtypesHeader_t) + cust_ie->len);
+                    ie_header->type = wlan_cpu_to_le16(TLV_TYPE_MGMT_IE);
+                    ie_header->len  = wlan_cpu_to_le16(cust_ie->len);
+
+                    if (ie)
+                    {
+                        req_len    = cust_ie->len;
+                        travel_len = 0;
+                        /* conversion for index, mask, len */
+                        if (req_len == sizeof(t_u16))
+                            cust_ie->ie_data_list[0].ie_index = wlan_cpu_to_le16(cust_ie->ie_data_list[0].ie_index);
+                        while (req_len > sizeof(t_u16))
+                        {
+                            cptr = (custom_ie *)(((t_u8 *)&cust_ie->ie_data_list) + travel_len);
+                            travel_len += cptr->ie_length + sizeof(custom_ie) - MAX_IE_SIZE;
+                            req_len -= cptr->ie_length + sizeof(custom_ie) - MAX_IE_SIZE;
+                            cptr->ie_index          = wlan_cpu_to_le16(cptr->ie_index);
+                            cptr->mgmt_subtype_mask = wlan_cpu_to_le16(cptr->mgmt_subtype_mask);
+                            cptr->ie_length         = wlan_cpu_to_le16(cptr->ie_length);
+                        }
+                        (void)__memcpy(pmpriv->adapter, ie, cust_ie->ie_data_list, cust_ie->len);
+                    }
+                    break;
+                default:
+                    PRINTM(MERROR, "Wrong data, or missing TLV_TYPE 0x%04x handler.\n", *(t_u16 *)pdata_buf);
+                    break;
+            }
+            goto done;
+        }
+        else
+        {
+        }
+    }
+
+    if (pioctl_buf->req_id == (t_u32)MLAN_IOCTL_BSS)
+    {
+        bss = (mlan_ds_bss *)(void *)pioctl_buf->pbuf;
+        if (bss->sub_command == MLAN_OID_BSS_MAC_ADDR)
+        {
+        }
+        else if ((bss->sub_command == MLAN_OID_UAP_BSS_CONFIG) && (cmd_action == HostCmd_ACT_GEN_SET))
+        {
+            ret = wlan_uap_cmd_ap_config(pmpriv, cmd, cmd_action, pioctl_buf);
+            goto done;
+        }
+#if CONFIG_ECSA
+        else if (bss->sub_command == MLAN_OID_ACTION_CHAN_SWITCH)
+        {
+            cmd->size       = sizeof(HostCmd_DS_SYS_CONFIG) - 1 + S_DS_GEN + sizeof(MrvlIEtypes_action_chan_switch_t);
+            tlv_chan_switch = (MrvlIEtypes_action_chan_switch_t *)sys_config->tlv_buffer;
+            tlv_chan_switch->header.type = wlan_cpu_to_le16(MRVL_ACTION_CHAN_SWITCH_ANNOUNCE);
+            // mode reserve for future use
+            tlv_chan_switch->mode = 0;
+            if (bss->param.chanswitch.new_oper_class)
+            {
+                tlv_chan_switch->header.len =
+                    wlan_cpu_to_le16(sizeof(MrvlIEtypes_action_chan_switch_t) - sizeof(MrvlIEtypesHeader_t) +
+                                     sizeof(IEEEtypes_ExtChanSwitchAnn_t));
+                ecsa_ie                    = (IEEEtypes_ExtChanSwitchAnn_t *)tlv_chan_switch->ie_buf;
+                ecsa_ie->element_id        = EXTEND_CHANNEL_SWITCH_ANN;
+                ecsa_ie->len               = sizeof(IEEEtypes_ExtChanSwitchAnn_t) - sizeof(IEEEtypes_Header_t);
+                ecsa_ie->chan_switch_mode  = bss->param.chanswitch.chan_switch_mode;
+                ecsa_ie->chan_switch_count = bss->param.chanswitch.chan_switch_count;
+                ecsa_ie->new_channel_num   = bss->param.chanswitch.new_channel_num;
+                ecsa_ie->new_oper_class    = bss->param.chanswitch.new_oper_class;
+                cmd->size += sizeof(IEEEtypes_ExtChanSwitchAnn_t);
+            }
+            else
+            {
+                tlv_chan_switch->header.len =
+                    wlan_cpu_to_le16(sizeof(MrvlIEtypes_action_chan_switch_t) - sizeof(MrvlIEtypesHeader_t) +
+                                     sizeof(IEEEtypes_ChanSwitchAnn_t));
+                csa_ie                    = (IEEEtypes_ChanSwitchAnn_t *)tlv_chan_switch->ie_buf;
+                csa_ie->element_id        = CHANNEL_SWITCH_ANN;
+                csa_ie->len               = sizeof(IEEEtypes_ChanSwitchAnn_t) - sizeof(IEEEtypes_Header_t);
+                csa_ie->chan_switch_mode  = bss->param.chanswitch.chan_switch_mode;
+                csa_ie->chan_switch_count = bss->param.chanswitch.chan_switch_count;
+                csa_ie->new_channel_num   = bss->param.chanswitch.new_channel_num;
+                cmd->size += sizeof(IEEEtypes_ChanSwitchAnn_t);
+            }
+            cmd->size = wlan_cpu_to_le16(cmd->size);
+        }
+#endif
+        else
+        { /* Do Nothing */
+        }
+    }
+    else if (pioctl_buf->req_id == (t_u32)MLAN_IOCTL_MISC_CFG)
+    {
+    }
+    else
+    {
+        goto done;
+    }
+done:
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief This function prepares command of snmp_mib
+ *
+ *  @param pmpriv		A pointer to mlan_private structure
+ *  @param cmd	   		A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   the action: GET or SET
+ *  @param cmd_oid      Cmd oid: treated as sub command
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *  @param pdata_buf    A pointer to information buffer
+ *  @return         MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_uap_cmd_snmp_mib(pmlan_private pmpriv,
+                                         IN HostCmd_DS_COMMAND *cmd,
+                                         IN t_u16 cmd_action,
+                                         IN t_u32 cmd_oid,
+                                         IN pmlan_ioctl_req pioctl_buf,
+                                         IN t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_SNMP_MIB *psnmp_mib = &cmd->params.smib;
+    mlan_status ret                       = MLAN_STATUS_SUCCESS;
+    t_u8 *psnmp_oid                       = MNULL;
+    t_u32 ul_temp;
+    t_u8 i;
+
+    t_u8 snmp_oids[] = {
+        (t_u8)tkip_mic_failures,
+        (t_u8)ccmp_decrypt_errors,
+        (t_u8)wep_undecryptable_count,
+        (t_u8)wep_icv_error_count,
+        (t_u8)decrypt_failure_count,
+        (t_u8)dot11_mcast_tx_count,
+        (t_u8)dot11_failed_count,
+        (t_u8)dot11_retry_count,
+        (t_u8)dot11_multi_retry_count,
+        (t_u8)dot11_frame_dup_count,
+        (t_u8)dot11_rts_success_count,
+        (t_u8)dot11_rts_failure_count,
+        (t_u8)dot11_ack_failure_count,
+        (t_u8)dot11_rx_fragment_count,
+        (t_u8)dot11_mcast_rx_frame_count,
+        (t_u8)dot11_fcs_error_count,
+        (t_u8)dot11_tx_frame_count,
+        (t_u8)dot11_rsna_tkip_cm_invoked,
+        (t_u8)dot11_rsna_4way_hshk_failures,
+    };
+
+    ENTER();
+
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        cmd->command          = wlan_cpu_to_le16(HostCmd_CMD_802_11_SNMP_MIB);
+        psnmp_mib->query_type = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
+        if (cmd_oid == (t_u32)StopDeauth_i)
+        {
+            psnmp_mib->oid      = wlan_cpu_to_le16((t_u16)StopDeauth_i);
+            psnmp_mib->buf_size = wlan_cpu_to_le16(sizeof(t_u8));
+            cmd->size           = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_SNMP_MIB) + S_DS_GEN);
+        }
+        else
+        {
+            cmd->size = wlan_cpu_to_le16(sizeof(t_u16) + S_DS_GEN + sizeof(snmp_oids) * sizeof(MrvlIEtypes_snmp_oid_t));
+            psnmp_oid = (t_u8 *)&psnmp_mib->oid;
+            for (i = 0; i < sizeof(snmp_oids); i++)
+            {
+                /* SNMP OID header type */
+                // coverity[overrun-local:SUPPRESS]
+                *(t_u16 *)(void *)psnmp_oid = wlan_cpu_to_le16(snmp_oids[i]);
+                psnmp_oid += sizeof(t_u16);
+                /* SNMP OID header length */
+                *(t_u16 *)(void *)psnmp_oid = wlan_cpu_to_le16(sizeof(t_u32));
+                psnmp_oid += sizeof(t_u16) + sizeof(t_u32);
+            }
+        }
+    }
+    else
+    { /* cmd_action == ACT_SET */
+        cmd->command          = wlan_cpu_to_le16(HostCmd_CMD_802_11_SNMP_MIB);
+        cmd->size             = sizeof(HostCmd_DS_802_11_SNMP_MIB) - 1U + S_DS_GEN;
+        psnmp_mib->query_type = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+
+        switch (cmd_oid)
+        {
+            case Dot11D_i:
+            case Dot11H_i:
+                psnmp_mib->oid      = wlan_cpu_to_le16((t_u16)cmd_oid);
+                psnmp_mib->buf_size = wlan_cpu_to_le16(sizeof(t_u16));
+                // ul_temp = *(t_u32 *) pdata_buf;
+                //*((t_u16 *) (psnmp_mib->value)) = wlan_cpu_to_le16((t_u16) ul_temp);
+                cmd->size += (t_u16)sizeof(t_u16);
+                break;
+            case StopDeauth_i:
+                psnmp_mib->oid      = wlan_cpu_to_le16((t_u16)cmd_oid);
+                psnmp_mib->buf_size = wlan_cpu_to_le16(sizeof(t_u8));
+                psnmp_mib->value[0] = *((t_u8 *)pdata_buf);
+                cmd->size += (t_u16)sizeof(t_u8);
+                break;
+#if CONFIG_WIFI_FRAG_THRESHOLD
+            case FragThresh_i:
+                psnmp_mib->oid                 = wlan_cpu_to_le16((t_u16)FragThresh_i);
+                psnmp_mib->buf_size            = wlan_cpu_to_le16(sizeof(t_u16));
+                ul_temp                        = *((t_u32 *)pdata_buf);
+                *((t_u16 *)(psnmp_mib->value)) = wlan_cpu_to_le16((t_u16)ul_temp);
+                cmd->size += sizeof(t_u16);
+                break;
+#endif
+            case RtsThresh_i:
+                psnmp_mib->oid                 = wlan_cpu_to_le16((t_u16)RtsThresh_i);
+                psnmp_mib->buf_size            = wlan_cpu_to_le16(sizeof(t_u16));
+                ul_temp                        = *((t_u32 *)pdata_buf);
+                *((t_u16 *)(psnmp_mib->value)) = wlan_cpu_to_le16((t_u16)ul_temp);
+                cmd->size += sizeof(t_u16);
+                break;
+            default:
+                PRINTM(MERROR, "Unsupported OID.\n");
+                ret = MLAN_STATUS_FAILURE;
+                break;
+        }
+        cmd->size = wlan_cpu_to_le16(cmd->size);
+    }
+
+    LEAVE();
+    return ret;
+}
+
+
+/**
+ *  @brief This function prepares command of deauth station
+ *
+ *  @param pmpriv		A pointer to mlan_private structure
+ *  @param cmd	   		A pointer to HostCmd_DS_COMMAND structure
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_uap_cmd_sta_deauth(pmlan_private pmpriv, IN HostCmd_DS_COMMAND *cmd, IN t_void *pdata_buf)
+{
+    HostCmd_DS_STA_DEAUTH *pcmd_sta_deauth = (HostCmd_DS_STA_DEAUTH *)&cmd->params.sta_deauth;
+    mlan_deauth_param *deauth              = (mlan_deauth_param *)pdata_buf;
+
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HOST_CMD_APCMD_STA_DEAUTH);
+    cmd->size    = wlan_cpu_to_le16(S_DS_GEN + sizeof(HostCmd_DS_STA_DEAUTH));
+    (void)__memcpy(pmpriv->adapter, pcmd_sta_deauth->mac, deauth->mac_addr, MLAN_MAC_ADDR_LENGTH);
+    pcmd_sta_deauth->reason = wlan_cpu_to_le16(deauth->reason_code);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+
+#if defined(WAPI_AP) || defined(HOST_AUTHENTICATOR) || (CONFIG_WPA_SUPP_AP)
+
+/**
+ *  @brief This function prepares command of key material
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   The action: GET or SET
+ *  @param cmd_oid      OID: ENABLE or DISABLE
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+static mlan_status wlan_uap_cmd_key_material(
+    pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u16 cmd_action, t_u16 cmd_oid, t_void *pdata_buf)
+{
+    HostCmd_DS_802_11_KEY_MATERIAL *pkey_material = &cmd->params.key_material;
+    mlan_ds_encrypt_key *pkey                     = (mlan_ds_encrypt_key *)pdata_buf;
+    mlan_status ret                               = MLAN_STATUS_SUCCESS;
+
+    ENTER();
+    if (!pkey)
+    {
+        ret = MLAN_STATUS_FAILURE;
+        goto done;
+    }
+    cmd->command          = wlan_cpu_to_le16(HostCmd_CMD_802_11_KEY_MATERIAL);
+    pkey_material->action = wlan_cpu_to_le16(cmd_action);
+    if (cmd_action == HostCmd_ACT_GEN_GET)
+    {
+        cmd->size = wlan_cpu_to_le16(sizeof(pkey_material->action) + S_DS_GEN);
+        goto done;
+    }
+    memset(&pkey_material->key_param_set, 0, sizeof(MrvlIEtype_KeyParamSetV2_t));
+    if (pkey->key_flags & KEY_FLAG_REMOVE_KEY)
+    {
+        pkey_material->action                 = wlan_cpu_to_le16(HostCmd_ACT_GEN_REMOVE);
+        pkey_material->key_param_set.type     = wlan_cpu_to_le16(TLV_TYPE_KEY_PARAM_V2);
+        pkey_material->key_param_set.length   = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN);
+        pkey_material->key_param_set.key_idx  = pkey->key_index & KEY_INDEX_MASK;
+        pkey_material->key_param_set.key_info = wlan_cpu_to_le16(KEY_INFO_MCAST_KEY | KEY_INFO_UCAST_KEY);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.mac_addr, pkey->mac_addr, MLAN_MAC_ADDR_LENGTH,
+                   MLAN_MAC_ADDR_LENGTH);
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(pkey_material->action));
+        wifi_d("Remove Key");
+        goto done;
+    }
+    pkey_material->action                 = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+    pkey_material->key_param_set.key_idx  = pkey->key_index & KEY_INDEX_MASK;
+    pkey_material->key_param_set.type     = wlan_cpu_to_le16(TLV_TYPE_KEY_PARAM_V2);
+    pkey_material->key_param_set.key_info = KEY_INFO_ENABLE_KEY;
+    memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.mac_addr, pkey->mac_addr, MLAN_MAC_ADDR_LENGTH,
+               MLAN_MAC_ADDR_LENGTH);
+    if (pkey->key_len <= MAX_WEP_KEY_SIZE)
+    {
+        pkey_material->key_param_set.length   = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(wep_param_t));
+        pkey_material->key_param_set.key_type = KEY_TYPE_ID_WEP;
+        pkey_material->key_param_set.key_info |= KEY_INFO_MCAST_KEY | KEY_INFO_UCAST_KEY;
+        if (pkey_material->key_param_set.key_idx == (pmpriv->wep_key_curr_index & KEY_INDEX_MASK))
+            pkey_material->key_param_set.key_info |= KEY_INFO_DEFAULT_KEY;
+        pkey_material->key_param_set.key_info               = wlan_cpu_to_le16(pkey_material->key_param_set.key_info);
+        pkey_material->key_param_set.key_params.wep.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.wep.key, pkey->key_material, pkey->key_len,
+                   MAX_WEP_KEY_SIZE);
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(wep_param_t) + sizeof(pkey_material->action));
+        wifi_d("Set WEP Key");
+        goto done;
+    }
+    if (pkey->key_flags & KEY_FLAG_GROUP_KEY)
+        pkey_material->key_param_set.key_info |= KEY_INFO_MCAST_KEY;
+    else
+        pkey_material->key_param_set.key_info |= KEY_INFO_UCAST_KEY;
+    if (pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK)
+        pkey_material->key_param_set.key_info |= KEY_INFO_CMAC_AES_KEY;
+    if (pkey->key_flags & KEY_FLAG_SET_TX_KEY)
+        pkey_material->key_param_set.key_info |= KEY_INFO_TX_KEY | KEY_INFO_RX_KEY;
+    else
+        pkey_material->key_param_set.key_info |= KEY_INFO_TX_KEY;
+    pkey_material->key_param_set.key_info |= KEY_INFO_DEFAULT_KEY;
+    pkey_material->key_param_set.key_info = wlan_cpu_to_le16(pkey_material->key_param_set.key_info);
+    if (pkey->key_flags & KEY_FLAG_GCMP || pkey->key_flags & KEY_FLAG_GCMP_256)
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+        {
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.gcmp.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        }
+        if (pkey->key_flags & KEY_FLAG_GCMP)
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_GCMP;
+        else
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_GCMP_256;
+        pkey_material->key_param_set.key_params.gcmp.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.gcmp.key, pkey->key_material, pkey->key_len,
+                   WPA_GCMP_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(gcmp_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(gcmp_param) + sizeof(pkey_material->action));
+        PRINTM(MCMND, "Set GCMP Key\n");
+        goto done;
+    }
+    if (pkey->key_flags & KEY_FLAG_CCMP_256)
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+        {
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.ccmp256.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        }
+        pkey_material->key_param_set.key_type                   = KEY_TYPE_ID_CCMP_256;
+        pkey_material->key_param_set.key_params.ccmp256.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.ccmp256.key, pkey->key_material,
+                   pkey->key_len, WPA_CCMP_256_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(ccmp_256_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(ccmp_256_param) + sizeof(pkey_material->action));
+        PRINTM(MCMND, "Set CCMP256 Key\n");
+        goto done;
+    }
+    if (pkey->key_len == WPA_AES_KEY_LEN && !(pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK))
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.aes.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        pkey_material->key_param_set.key_type               = KEY_TYPE_ID_AES;
+        pkey_material->key_param_set.key_params.aes.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.aes.key, pkey->key_material, pkey->key_len,
+                   WPA_AES_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(aes_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN + sizeof(aes_param) +
+                                     sizeof(pkey_material->action));
+        wifi_d("Set AES Key");
+        goto done;
+    }
+    if (pkey->key_len == WPA_IGTK_KEY_LEN && (pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK))
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.cmac_aes.ipn, pkey->pn, SEQ_MAX_SIZE,
+                       IGTK_PN_SIZE);
+        pkey_material->key_param_set.key_info &= ~(wlan_cpu_to_le16(KEY_INFO_MCAST_KEY));
+        pkey_material->key_param_set.key_info |= wlan_cpu_to_le16(KEY_INFO_AES_MCAST_IGTK);
+        if (pkey->key_flags & KEY_FLAG_GMAC_128)
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_BIP_GMAC_128;
+        else
+            pkey_material->key_param_set.key_type = KEY_TYPE_ID_AES_CMAC;
+        pkey_material->key_param_set.key_params.cmac_aes.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.cmac_aes.key, pkey->key_material,
+                   pkey->key_len, CMAC_AES_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(cmac_aes_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(cmac_aes_param) + sizeof(pkey_material->action));
+        if (pkey->key_flags & KEY_FLAG_GMAC_128)
+            PRINTM(MCMND, "Set AES 128 GMAC Key\n");
+        else
+            PRINTM(MCMND, "Set CMAC AES Key\n");
+        goto done;
+    }
+    if (pkey->key_len == WPA_IGTK_256_KEY_LEN && (pkey->key_flags & KEY_FLAG_AES_MCAST_IGTK))
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.gmac_aes.ipn, pkey->pn, SEQ_MAX_SIZE,
+                       IGTK_PN_SIZE);
+        pkey_material->key_param_set.key_info &= ~(wlan_cpu_to_le16(KEY_INFO_MCAST_KEY));
+        pkey_material->key_param_set.key_info |= wlan_cpu_to_le16(KEY_INFO_AES_MCAST_IGTK);
+        pkey_material->key_param_set.key_type                    = KEY_TYPE_ID_BIP_GMAC_256;
+        pkey_material->key_param_set.key_params.gmac_aes.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.gmac_aes.key, pkey->key_material,
+                   pkey->key_len, WPA_IGTK_256_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(gmac_aes_256_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(gmac_aes_256_param) + sizeof(pkey_material->action));
+        PRINTM(MCMND, "Set AES 256 GMAC Key\n");
+        goto done;
+    }
+    if (pkey->key_len == WPA_TKIP_KEY_LEN)
+    {
+        if (pkey->key_flags & (KEY_FLAG_RX_SEQ_VALID | KEY_FLAG_TX_SEQ_VALID))
+            memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.tkip.pn, pkey->pn, SEQ_MAX_SIZE,
+                       WPA_PN_SIZE);
+        pkey_material->key_param_set.key_type                = KEY_TYPE_ID_TKIP;
+        pkey_material->key_param_set.key_params.tkip.key_len = wlan_cpu_to_le16(pkey->key_len);
+        memcpy_ext(pmpriv->adapter, pkey_material->key_param_set.key_params.tkip.key, pkey->key_material, pkey->key_len,
+                   WPA_TKIP_KEY_LEN);
+        pkey_material->key_param_set.length = wlan_cpu_to_le16(KEY_PARAMS_FIXED_LEN + sizeof(tkip_param));
+        cmd->size = wlan_cpu_to_le16(sizeof(MrvlIEtypesHeader_t) + S_DS_GEN + KEY_PARAMS_FIXED_LEN +
+                                     sizeof(tkip_param) + sizeof(pkey_material->action));
+        PRINTM(MCMND, "Set TKIP Key\n");
+    }
+done:
+    LEAVE();
+    return ret;
+}
+
+#endif /* WAPI_AP || HOST_AUTHENTICATOR || CONFIG_WPA_SUPP_AP */
+
+
+/**
+ *  @brief This function will search for the specific ie
+ *
+ *
+ *  @param priv    A pointer to mlan_private
+ *  @param pevent  A pointer to event buf
+ *  @param sta_ptr A pointer to sta_node
+ *
+ *  @return	       N/A
+ */
+void wlan_check_sta_capability(pmlan_private priv, pmlan_buffer pevent, sta_node *sta_ptr)
+{
+    t_u16 tlv_type, tlv_len;
+    t_u16 frame_control, frame_sub_type = 0;
+    t_u8 *assoc_req_ie = MNULL;
+    t_u8 ie_len = 0, assoc_ie_len = 0;
+    IEEEtypes_HTCap_t *pht_cap = MNULL;
+    int tlv_buf_left           = pevent->data_len - ASSOC_EVENT_FIX_SIZE;
+    MrvlIEtypesHeader_t *tlv   = (MrvlIEtypesHeader_t *)(pevent->pbuf + pevent->data_offset + ASSOC_EVENT_FIX_SIZE);
+    MrvlIETypes_MgmtFrameSet_t *mgmt_tlv = MNULL;
+
+    ENTER();
+    while (tlv_buf_left >= (int)sizeof(MrvlIEtypesHeader_t))
+    {
+        tlv_type = wlan_le16_to_cpu(tlv->type);
+        tlv_len  = wlan_le16_to_cpu(tlv->len);
+        if ((sizeof(MrvlIEtypesHeader_t) + tlv_len) > (unsigned int)tlv_buf_left)
+        {
+            wifi_d("wrong tlv: tlvLen=%d, tlvBufLeft=%d", tlv_len, tlv_buf_left);
+            break;
+        }
+        if (tlv_type == TLV_TYPE_UAP_MGMT_FRAME)
+        {
+            mgmt_tlv = (MrvlIETypes_MgmtFrameSet_t *)tlv;
+            (void)__memcpy(priv->adapter, &frame_control, (t_u8 *)&(mgmt_tlv->frame_control), sizeof(frame_control));
+            frame_sub_type = IEEE80211_GET_FC_MGMT_FRAME_SUBTYPE(frame_control);
+            if ((mgmt_tlv->frame_control.type == 0) &&
+                ((frame_sub_type == SUBTYPE_ASSOC_REQUEST) || (frame_sub_type == SUBTYPE_REASSOC_REQUEST)))
+            {
+                if (frame_sub_type == SUBTYPE_ASSOC_REQUEST)
+                    assoc_ie_len = sizeof(IEEEtypes_AssocRqst_t);
+                else if (frame_sub_type == SUBTYPE_REASSOC_REQUEST)
+                    assoc_ie_len = sizeof(IEEEtypes_ReAssocRqst_t);
+
+                ie_len       = tlv_len - sizeof(IEEEtypes_FrameCtl_t) - assoc_ie_len;
+                assoc_req_ie = (t_u8 *)tlv + sizeof(MrvlIETypes_MgmtFrameSet_t) + assoc_ie_len;
+                pht_cap      = (IEEEtypes_HTCap_t *)wlan_get_specific_ie(priv, assoc_req_ie, ie_len, HT_CAPABILITY, 0);
+                if (pht_cap)
+                {
+                    wifi_d("STA supports 11n");
+                    sta_ptr->is_11n_enabled = MTRUE;
+                    if (GETHT_MAXAMSDU(pht_cap->ht_cap.ht_cap_info))
+                        sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_8K;
+                    else
+                        sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_4K;
+                }
+                else
+                {
+                    wifi_d("STA doesn't support 11n");
+                }
+                break;
+            }
+        }
+        tlv_buf_left -= (sizeof(MrvlIEtypesHeader_t) + tlv_len);
+        tlv = (MrvlIEtypesHeader_t *)((t_u8 *)tlv + tlv_len + sizeof(MrvlIEtypesHeader_t));
+    }
+    LEAVE();
+
+    return;
+}
+
+
+/**
+ *  @brief	Check 11B support Rates
+ *
+ *
+ *  @param pmadapter	Private mlan adapter structure
+ *
+ *  @return MTRUE/MFALSE
+ *
+ */
+static t_u8 wlan_check_11B_support_rates(MrvlIEtypes_RatesParamSet_t *prates_tlv)
+{
+    int i;
+    t_u8 rate;
+    t_u8 ret = MTRUE;
+    for (i = 0; i < prates_tlv->header.len; i++)
+    {
+        rate = prates_tlv->rates[i] & 0x7f;
+        if ((rate != 0x02) && (rate != 0x04) && (rate != 0x0b) && (rate != 0x16))
+        {
+            ret = MFALSE;
+            break;
+        }
+    }
+    return ret;
+}
+
+/**
+ *  @brief This function prepares command of sys_config
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   cmd action
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *  @return         MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_uap_cmd_add_station(pmlan_private pmpriv,
+                                            HostCmd_DS_COMMAND *cmd,
+                                            t_u16 cmd_action,
+                                            pmlan_ioctl_req pioctl_buf)
+{
+    mlan_ds_bss *bss                = MNULL;
+    HostCmd_DS_ADD_STATION *new_sta = (HostCmd_DS_ADD_STATION *)&cmd->params.sta_info;
+    sta_node *sta_ptr               = MNULL;
+    t_u16 tlv_buf_left;
+    t_u8 *pos        = MNULL;
+    t_u8 *tlv_buf    = MNULL;
+    t_u16 travel_len = 0;
+    MrvlIEtypesHeader_t *tlv;
+    t_u16 tlv_len = 0;
+    t_u8 b_only   = MFALSE;
+    MrvlIETypes_HTCap_t *phtcap;
+#if CONFIG_11AC
+    MrvlIETypes_VHTCap_t *pvhtcap;
+#endif
+#if CONFIG_11AX
+    MrvlIEtypes_Extension_t *pext_tlv = MNULL;
+#endif
+    MrvlIEtypes_StaFlag_t *pstaflag;
+    int i;
+
+    ENTER();
+
+    if (!pioctl_buf)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    (void)__memset(pmpriv->adapter, new_sta, 0x00, sizeof(HostCmd_DS_ADD_STATION));
+    bss = (mlan_ds_bss *)pioctl_buf->pbuf;
+
+    cmd->command    = wlan_cpu_to_le16(HostCmd_CMD_ADD_NEW_STATION);
+    new_sta->action = wlan_cpu_to_le16(cmd_action);
+    cmd->size       = sizeof(HostCmd_DS_ADD_STATION) + S_DS_GEN;
+    if (cmd_action == HostCmd_ACT_ADD_STA)
+    {
+        sta_ptr = wlan_get_station_entry(pmpriv, bss->param.sta_info.peer_mac);
+        if (!sta_ptr)
+            sta_ptr = wlan_add_station_entry(pmpriv, bss->param.sta_info.peer_mac);
+    }
+    else
+    {
+        sta_ptr = wlan_add_station_entry(pmpriv, bss->param.sta_info.peer_mac);
+    }
+    if (!sta_ptr)
+    {
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+#ifdef EASYMESH
+    /* Save station aid for multi-ap */
+    sta_ptr->aid = bss->param.sta_info.aid;
+#endif
+    (void)__memcpy(NULL, new_sta->peer_mac, bss->param.sta_info.peer_mac, MLAN_MAC_ADDR_LENGTH);
+    if (cmd_action != HostCmd_ACT_ADD_STA)
+        goto done;
+    new_sta->aid             = wlan_cpu_to_le16(bss->param.sta_info.aid);
+    new_sta->listen_interval = wlan_cpu_to_le32(bss->param.sta_info.listen_interval);
+    if (bss->param.sta_info.cap_info)
+        new_sta->cap_info = wlan_cpu_to_le16(bss->param.sta_info.cap_info);
+    else
+        new_sta->cap_info = wlan_cpu_to_le16(sta_ptr->capability);
+    tlv_buf_left = bss->param.sta_info.tlv_len;
+    pos          = new_sta->tlv;
+    tlv_buf      = bss->param.sta_info.tlv;
+    tlv          = (MrvlIEtypesHeader_t *)tlv_buf;
+    if (bss->param.sta_info.sta_flags & STA_FLAG_WME)
+    {
+        wifi_d("STA flags supports wmm");
+        sta_ptr->is_wmm_enabled = MTRUE;
+    }
+    // append sta_flag_flags.
+    pstaflag              = (MrvlIEtypes_StaFlag_t *)pos;
+    pstaflag->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_STA_FLAGS);
+    pstaflag->header.len  = wlan_cpu_to_le16(sizeof(t_u32));
+    pstaflag->sta_flags   = wlan_cpu_to_le32(bss->param.sta_info.sta_flags);
+    pos += sizeof(MrvlIEtypes_StaFlag_t);
+    cmd->size += sizeof(MrvlIEtypes_StaFlag_t);
+
+    while (tlv_buf_left >= sizeof(MrvlIEtypesHeader_t))
+    {
+        if (tlv_buf_left < (sizeof(MrvlIEtypesHeader_t) + tlv->len))
+            break;
+        switch (tlv->type)
+        {
+            case EXT_CAPABILITY:
+                break;
+            case SUPPORTED_RATES:
+                b_only = wlan_check_11B_support_rates((MrvlIEtypes_RatesParamSet_t *)tlv);
+                if (b_only)
+                    wm_wifi.bandwidth = BANDWIDTH_20MHZ;
+                break;
+            case QOS_INFO:
+                wifi_d("STA supports wmm");
+                sta_ptr->is_wmm_enabled = MTRUE;
+                break;
+            case HT_CAPABILITY:
+                wifi_d("STA supports 11n");
+                sta_ptr->is_11n_enabled = MTRUE;
+                phtcap                  = (MrvlIETypes_HTCap_t *)tlv;
+                if (sta_ptr->HTcap.ieee_hdr.element_id == HT_CAPABILITY)
+                {
+                    if (GETHT_40MHZ_INTOLARANT(sta_ptr->HTcap.ht_cap.ht_cap_info))
+                    {
+                        wifi_d("SETHT_40MHZ_INTOLARANT");
+                        SETHT_40MHZ_INTOLARANT(phtcap->ht_cap.ht_cap_info);
+                    }
+                }
+                if (GETHT_MAXAMSDU(phtcap->ht_cap.ht_cap_info))
+                    sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_8K;
+                else
+                    sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_4K;
+                break;
+#if CONFIG_11AC
+            case VHT_CAPABILITY:
+                wifi_d("STA supports 11ac");
+                sta_ptr->is_11ac_enabled = MTRUE;
+                pvhtcap                  = (MrvlIETypes_VHTCap_t *)tlv;
+                if (GET_VHTCAP_MAXMPDULEN(pvhtcap->vht_cap.vht_cap_info) == 2)
+                    sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_12K;
+                else if (GET_VHTCAP_MAXMPDULEN(pvhtcap->vht_cap.vht_cap_info) == 1)
+                    sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_8K;
+                else
+                    sta_ptr->max_amsdu = MLAN_TX_DATA_BUF_SIZE_4K;
+                break;
+            case OPER_MODE_NTF:
+                break;
+#endif
+#if CONFIG_11AX
+            case EXTENSION:
+                pext_tlv = (MrvlIEtypes_Extension_t *)tlv;
+                if (pext_tlv->ext_id == HE_CAPABILITY)
+                {
+                    sta_ptr->is_11ax_enabled = MTRUE;
+                    wifi_d("STA supports 11ax");
+                }
+#ifdef ENABLE_802_116E
+                else if (pext_tlv->ext_id == HE_6G_CAPABILITY)
+                {
+                    MrvlIEtypes_He_6g_cap_t *phe_6g_cap = MNULL;
+                    phe_6g_cap                          = (MrvlIEtypes_He_6g_cap_t *)tlv;
+                    if (GET_6G_BAND_CAP_MAXMPDULEN(phe_6g_cap->capa) == 2)
+                        pmpriv->max_amsdu = MLAN_TX_DATA_BUF_SIZE_12K;
+                    else if (GET_6G_BAND_CAP_MAXMPDULEN(phe_6g_cap->capa) == 1)
+                        pmpriv->max_amsdu = MLAN_TX_DATA_BUF_SIZE_8K;
+                    else
+                        pmpriv->max_amsdu = MLAN_TX_DATA_BUF_SIZE_4K;
+                }
+#endif
+                else
+                {
+                    pext_tlv = MNULL;
+                }
+                break;
+#endif
+            default:
+                break;
+        }
+        tlv->type = wlan_cpu_to_le16(tlv->type);
+        tlv->len  = wlan_cpu_to_le16(tlv->len);
+        tlv_len   = tlv->len;
+        (void)__memcpy(NULL, pos, (t_u8 *)tlv, sizeof(MrvlIEtypesHeader_t) + tlv_len);
+        pos += sizeof(MrvlIEtypesHeader_t) + tlv_len;
+        tlv_buf += sizeof(MrvlIEtypesHeader_t) + tlv_len;
+        tlv = (MrvlIEtypesHeader_t *)tlv_buf;
+        travel_len += sizeof(MrvlIEtypesHeader_t) + tlv_len;
+        tlv_buf_left -= sizeof(MrvlIEtypesHeader_t) + tlv_len;
+    }
+#if CONFIG_11AX
+    if (sta_ptr->is_11ax_enabled)
+    {
+        if (pext_tlv == MNULL)
+        {
+            tlv       = (MrvlIEtypesHeader_t *)pos;
+            tlv->type = wlan_cpu_to_le16(EXTENSION);
+            tlv->len  = wlan_cpu_to_le16(
+                MIN(sta_ptr->he_cap.ieee_hdr.len, sizeof(IEEEtypes_HECap_t) - sizeof(IEEEtypes_Header_t)));
+
+            pos += sizeof(MrvlIEtypesHeader_t);
+            (void)__memcpy(NULL, pos, (t_u8 *)&sta_ptr->he_cap.ext_id, tlv->len);
+            travel_len += sizeof(MrvlIEtypesHeader_t) + tlv->len;
+        }
+    }
+#endif
+
+    if (sta_ptr->is_11n_enabled)
+    {
+        if (pmpriv->uap_channel <= 14)
+            sta_ptr->bandmode = BAND_GN;
+#if CONFIG_5GHz_SUPPORT
+        else
+            sta_ptr->bandmode = BAND_AN;
+#endif
+    }
+    else if (!b_only)
+    {
+        if (pmpriv->uap_channel <= 14)
+            sta_ptr->bandmode = BAND_G;
+#if CONFIG_5GHz_SUPPORT
+        else
+            sta_ptr->bandmode = BAND_A;
+#endif
+    }
+    else
+        sta_ptr->bandmode = BAND_B;
+#if CONFIG_11AC
+    if (sta_ptr->is_11ac_enabled)
+    {
+        if (pmpriv->uap_channel <= 14)
+            sta_ptr->bandmode = BAND_GAC;
+        else
+            sta_ptr->bandmode = BAND_AAC;
+    }
+#endif
+#if CONFIG_11AX
+    if (sta_ptr->is_11ax_enabled)
+    {
+        if (pmpriv->uap_channel <= 14)
+            sta_ptr->bandmode = BAND_GAX;
+        else
+            sta_ptr->bandmode = BAND_AAX;
+    }
+#endif
+
+    for (i = 0; i < MAX_NUM_TID; i++)
+    {
+        if (sta_ptr->is_11n_enabled
+#if CONFIG_11AX
+            || sta_ptr->is_11ax_enabled
+#endif
+        )
+            sta_ptr->ampdu_sta[i] = pmpriv->aggr_prio_tbl[i].ampdu_user;
+        else
+            sta_ptr->ampdu_sta[i] = BA_STREAM_NOT_ALLOWED;
+    }
+    (void)__memset(pmpriv->adapter, sta_ptr->rx_seq, 0xff, sizeof(sta_ptr->rx_seq));
+done:
+    cmd->size += travel_len;
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function prepares command of bss_start.
+ *
+ * @param pmpriv       A pointer to mlan_private structure
+ * @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *
+ * @return             MLAN_STATUS_SUCCESS
+ **/
+static mlan_status wlan_uap_cmd_bss_start(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd)
+{
+    MrvlIEtypes_HostMlme_t *tlv;
+    ENTER();
+    cmd->command = wlan_cpu_to_le16(HOST_CMD_APCMD_BSS_START);
+    cmd->size    = S_DS_GEN;
+    if (pmpriv->uap_host_based)
+    {
+        tlv              = (MrvlIEtypes_HostMlme_t *)((t_u8 *)cmd + cmd->size);
+        tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_HOST_MLME);
+        tlv->header.len  = wlan_cpu_to_le16(sizeof(tlv->host_mlme));
+        tlv->host_mlme   = MTRUE;
+        cmd->size += sizeof(MrvlIEtypes_HostMlme_t);
+    }
+    cmd->size = wlan_cpu_to_le16(cmd->size);
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/********************************************************
+    Global Functions
+********************************************************/
+/**
+ *  @brief This function prepare the command before sending to firmware.
+ *
+ *  @param priv       A pointer to mlan_private structure
+ *  @param cmd_no       Command number
+ *  @param cmd_action   Command action: GET or SET
+ *  @param cmd_oid      Cmd oid: treated as sub command
+ *  @param pioctl_buf   A pointer to MLAN IOCTL Request buffer
+ *  @param pdata_buf    A pointer to information buffer
+ *  @param pcmd_buf      A pointer to cmd buf
+ *
+ *  @return             MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wlan_ops_uap_prepare_cmd(IN t_void *priv,
+                                     IN t_u16 cmd_no,
+                                     IN t_u16 cmd_action,
+                                     IN t_u32 cmd_oid,
+                                     IN t_void *pioctl_buf,
+                                     IN t_void *pdata_buf,
+                                     IN t_void *pcmd_buf)
+{
+    HostCmd_DS_COMMAND *cmd_ptr = (HostCmd_DS_COMMAND *)pcmd_buf;
+    mlan_private *pmpriv        = (mlan_private *)priv;
+    mlan_status ret             = MLAN_STATUS_SUCCESS;
+    pmlan_ioctl_req pioctl_req  = (mlan_ioctl_req *)pioctl_buf;
+
+    ENTER();
+
+    /* Prepare command */
+    switch (cmd_no)
+    {
+        case HostCMD_APCMD_ACS_SCAN:
+        case HostCmd_CMD_SOFT_RESET:
+        case HOST_CMD_APCMD_BSS_STOP:
+        case HOST_CMD_APCMD_SYS_INFO:
+        case HOST_CMD_APCMD_SYS_RESET:
+        case HOST_CMD_APCMD_STA_LIST:
+            cmd_ptr->command = wlan_cpu_to_le16(cmd_no);
+            cmd_ptr->size    = wlan_cpu_to_le16(S_DS_GEN);
+            break;
+        case HOST_CMD_APCMD_BSS_START:
+            ret = wlan_uap_cmd_bss_start(pmpriv, cmd_ptr);
+            break;
+        case HOST_CMD_APCMD_SYS_CONFIGURE:
+            ret = wlan_uap_cmd_sys_configure(pmpriv, cmd_ptr, cmd_action, (pmlan_ioctl_req)pioctl_buf, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11_SNMP_MIB:
+            ret = wlan_uap_cmd_snmp_mib(pmpriv, cmd_ptr, cmd_action, cmd_oid, (pmlan_ioctl_req)pioctl_buf, pdata_buf);
+            break;
+        case HostCmd_CMD_802_11D_DOMAIN_INFO:
+            if (pmpriv->support_11d_APIs != NULL)
+            {
+                ret = pmpriv->support_11d_APIs->wlan_cmd_802_11d_domain_info_p(pmpriv, cmd_ptr, cmd_action);
+            }
+            break;
+        case HOST_CMD_APCMD_STA_DEAUTH:
+            ret = wlan_uap_cmd_sta_deauth(pmpriv, cmd_ptr, pdata_buf);
+            break;
+#if defined(WAPI_AP) || defined(HOST_AUTHENTICATOR) || (CONFIG_WPA_SUPP_AP)
+        case HostCmd_CMD_802_11_KEY_MATERIAL:
+            ret = wlan_uap_cmd_key_material(pmpriv, cmd_ptr, cmd_action, cmd_oid, pdata_buf);
+            break;
+#endif
+        case HostCmd_CMD_11N_CFG:
+            ret = wlan_cmd_11n_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_11N_ADDBA_REQ:
+            ret = wlan_cmd_11n_addba_req(pmpriv, cmd_ptr, pdata_buf);
+            break;
+        case HostCmd_CMD_11N_DELBA:
+            ret = wlan_cmd_11n_delba(pmpriv, cmd_ptr, pdata_buf);
+            break;
+        case HostCmd_CMD_ADD_NEW_STATION:
+            ret = wlan_uap_cmd_add_station(pmpriv, cmd_ptr, cmd_action, (pmlan_ioctl_req)pioctl_buf);
+            break;
+        case HostCmd_CMD_TX_RATE_CFG:
+            ret = wlan_cmd_tx_rate_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf, (pmlan_ioctl_req)pioctl_buf);
+            break;
+        case HostCmd_CMD_802_11_TX_RATE_QUERY:
+            cmd_ptr->command = wlan_cpu_to_le16(HostCmd_CMD_802_11_TX_RATE_QUERY);
+            cmd_ptr->size    = wlan_cpu_to_le16(sizeof(HostCmd_TX_RATE_QUERY) + S_DS_GEN);
+            pmpriv->tx_rate  = 0;
+            ret              = MLAN_STATUS_SUCCESS;
+            break;
+        case HostCmd_CMD_11AC_CFG:
+            ret = wlan_cmd_11ac_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#if CONFIG_WIFI_CLOCKSYNC
+        case HostCmd_GPIO_TSF_LATCH_PARAM_CONFIG:
+            ret = wlan_cmd_gpio_tsf_latch(pmpriv, cmd_ptr, cmd_action, pioctl_buf, pdata_buf);
+            break;
+#endif
+#if CONFIG_11AX
+        case HostCmd_CMD_11AX_CMD:
+            ret = (mlan_status)wlan_cmd_11ax_cmd(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+        case HostCmd_CMD_11AX_CFG:
+            ret = (mlan_status)wlan_cmd_11ax_cfg(pmpriv, cmd_action, pdata_buf);
+            break;
+#if CONFIG_11AX_TWT
+        case HostCmd_CMD_TWT_CFG:
+            ret = wlan_cmd_twt_cfg(pmpriv, cmd_ptr, cmd_action, pdata_buf);
+            break;
+#endif /* CONFIG_11AX_TWT */
+#endif /* CONFIG_11AX */
+        default:
+            PRINTM(MERROR, "PREP_CMD: unknown command- %#x\n", cmd_no);
+            if (pioctl_req != NULL)
+            {
+                pioctl_req->status_code = MLAN_ERROR_CMD_INVALID;
+            }
+            ret = MLAN_STATUS_FAILURE;
+            break;
+    }
+    LEAVE();
+    return ret;
+}
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_uap_ioctl.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_uap_ioctl.c
new file mode 100644
index 0000000000..9630fbd9c5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_uap_ioctl.c
@@ -0,0 +1,160 @@
+/** @file mlan_uap_ioctl.c
+ *
+ *  @brief  This file provides handling of AP mode ioctls
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    02/05/2009: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+
+#if defined(WAPI_AP) || defined(HOST_AUTHENTICATOR) || (CONFIG_WPA_SUPP_AP)
+/**
+ *  @brief Set encrypt key
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS/MLAN_STATUS_PENDING --success, otherwise fail
+ */
+static mlan_status wlan_uap_sec_ioctl_set_encrypt_key(IN pmlan_adapter pmadapter, IN pmlan_ioctl_req pioctl_req)
+{
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_ds_sec_cfg *sec = MNULL;
+
+    ENTER();
+    sec = (mlan_ds_sec_cfg *)pioctl_req->pbuf;
+    if (pioctl_req->action != MLAN_ACT_SET)
+    {
+        pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+        LEAVE();
+        return MLAN_STATUS_FAILURE;
+    }
+    if (!sec->param.encrypt_key.key_remove && !sec->param.encrypt_key.key_len)
+    {
+        PRINTM(MCMND, "Skip set key with key_len = 0\n");
+        LEAVE();
+        return ret;
+    }
+    ret = wlan_prepare_cmd(pmpriv, HostCmd_CMD_802_11_KEY_MATERIAL, HostCmd_ACT_GEN_SET, KEY_INFO_ENABLED,
+                           (t_void *)pioctl_req, &sec->param.encrypt_key);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+    LEAVE();
+    return ret;
+}
+#endif
+
+
+#if CONFIG_ECSA
+/**
+ *  @brief Handle channel switch
+ *
+ *  @param pmadapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_PENDING --success, otherwise fail
+ */
+mlan_status wlan_uap_bss_ioctl_action_chan_switch(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req)
+{
+    mlan_private *pmpriv = pmadapter->priv[pioctl_req->bss_index];
+    mlan_status ret      = MLAN_STATUS_SUCCESS;
+    t_u16 cmd_action     = 0;
+
+    ENTER();
+
+    cmd_action = HostCmd_ACT_GEN_SET;
+
+    /* Send request to firmware */
+    ret = wlan_prepare_cmd(pmpriv, HOST_CMD_APCMD_SYS_CONFIGURE, cmd_action, 0, (t_void *)pioctl_req, MNULL);
+
+    if (ret == MLAN_STATUS_SUCCESS)
+        ret = MLAN_STATUS_PENDING;
+
+    LEAVE();
+    return ret;
+}
+#endif
+
+/**
+ *  @brief MLAN uap ioctl handler
+ *
+ *  @param adapter	A pointer to mlan_adapter structure
+ *  @param pioctl_req	A pointer to ioctl request buffer
+ *
+ *  @return		MLAN_STATUS_SUCCESS --success, otherwise fail
+ */
+mlan_status wlan_ops_uap_ioctl(t_void *adapter, pmlan_ioctl_req pioctl_req)
+{
+    pmlan_adapter pmadapter = (pmlan_adapter)adapter;
+    mlan_status status      = MLAN_STATUS_SUCCESS;
+#if CONFIG_ECSA
+    mlan_ds_misc_cfg *misc = MNULL;
+    mlan_ds_bss *bss       = MNULL;
+#endif
+#if defined(WAPI_AP) || defined(HOST_AUTHENTICATOR) || (CONFIG_WPA_SUPP_AP)
+    mlan_ds_sec_cfg *sec = MNULL;
+#endif
+    mlan_ds_rate *rate = MNULL;
+
+    ENTER();
+
+    switch (pioctl_req->req_id)
+    {
+#if defined(WAPI_AP) || defined(HOST_AUTHENTICATOR) || (CONFIG_WPA_SUPP_AP)
+        case MLAN_IOCTL_SEC_CFG:
+            sec = (mlan_ds_sec_cfg *)pioctl_req->pbuf;
+            if (sec->sub_command == MLAN_OID_SEC_CFG_ENCRYPT_KEY)
+                status = wlan_uap_sec_ioctl_set_encrypt_key(pmadapter, pioctl_req);
+            break;
+#endif /* WAPI_AP || HOST_AUTHENTICATOR */
+        case MLAN_IOCTL_RATE:
+            rate = (mlan_ds_rate *)(void *)pioctl_req->pbuf;
+            if (rate->sub_command == MLAN_OID_RATE_CFG)
+            {
+                status = wlan_rate_ioctl_cfg(pmadapter, pioctl_req);
+            }
+            break;
+#if CONFIG_ECSA
+        case MLAN_IOCTL_MISC_CFG:
+            misc = (mlan_ds_misc_cfg *)pioctl_req->pbuf;
+            if (misc->sub_command == MLAN_OID_MISC_OPER_CLASS)
+                status = wlan_misc_ioctl_oper_class(pmadapter, pioctl_req);
+            if (misc->sub_command == MLAN_OID_MISC_OPER_CLASS_CHECK)
+                status = wlan_misc_ioctl_operclass_validation(pmadapter, pioctl_req);
+            break;
+        case MLAN_IOCTL_BSS:
+            bss = (mlan_ds_bss *)pioctl_req->pbuf;
+            if (bss->sub_command == MLAN_OID_ACTION_CHAN_SWITCH)
+                status = wlan_uap_bss_ioctl_action_chan_switch(pmadapter, pioctl_req);
+            break;
+#endif
+#if CONFIG_11AX
+        case MLAN_IOCTL_11AX_CFG:
+            status = wlan_11ax_cfg_ioctl(pmadapter, pioctl_req);
+            break;
+#endif
+        default:
+            pioctl_req->status_code = MLAN_ERROR_IOCTL_INVALID;
+            break;
+    }
+    LEAVE();
+    return status;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_wmm.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_wmm.c
new file mode 100644
index 0000000000..6760620004
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/mlan_wmm.c
@@ -0,0 +1,1215 @@
+/** @file mlan_wmm.c
+ *
+ *  @brief  This file provides functions for WMM
+ *
+ *  Copyright 2008-2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/********************************************************
+Change log:
+    10/24/2008: initial version
+********************************************************/
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+#if CONFIG_TX_RX_ZERO_COPY
+#include <wm_net.h>
+#endif
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+/********************************************************
+    Local Variables
+********************************************************/
+
+/** Maximum value FW can accept for driver delay in packet transmission */
+#define DRV_PKT_DELAY_TO_FW_MAX 512
+
+/*
+ * Upper and Lower threshold for packet queuing in the driver
+
+ *    - When the number of packets queued reaches the upper limit,
+ *      the driver will stop the net queue in the app/kernel space.
+
+ *    - When the number of packets drops beneath the lower limit after
+ *      having reached the upper limit, the driver will restart the net
+ *      queue.
+ */
+
+/** Lower threshold for packet queuing in the driver.
+ * When the number of packets drops beneath the lower limit after having
+ * reached the upper limit, the driver will restart the net queue.
+ */
+#define WMM_QUEUED_PACKET_LOWER_LIMIT 180
+
+/** Upper threshold for packet queuing in the driver.
+ * When the number of packets queued reaches the upper limit, the driver
+ * will stop the net queue in the app/kernel space.
+ */
+#define WMM_QUEUED_PACKET_UPPER_LIMIT 200
+
+/** Offset for TOS field in the IP header */
+#define IPTOS_OFFSET 5
+
+/** WMM information IE */
+static const t_u8 wmm_info_ie[] = {(t_u8)WMM_IE, 0x07, 0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};
+
+/** Type enumeration of WMM AC_QUEUES */
+typedef MLAN_PACK_START enum _wmm_ac_e { AC_BE, AC_BK, AC_VI, AC_VO } MLAN_PACK_END wmm_ac_e;
+
+
+/**
+ * This table will be used to store the tid values based on ACs.
+ * It is initialized to default values per TID.
+ */
+static t_u8 tos_to_tid[] = {
+    /* TID DSCP_P2 DSCP_P1 DSCP_P0 WMM_AC */
+    0x01, /* 0 1 0 AC_BK */
+    0x02, /* 0 0 0 AC_BK */
+    0x00, /* 0 0 1 AC_BE */
+    0x03, /* 0 1 1 AC_BE */
+    0x04, /* 1 0 0 AC_VI */
+    0x05, /* 1 0 1 AC_VI */
+    0x06, /* 1 1 0 AC_VO */
+    0x07  /* 1 1 1 AC_VO */
+};
+
+
+/**
+ * This table will provide the tid value for given ac. This table does not
+ * change and will be used to copy back the default values to tos_to_tid in
+ * case of disconnect.
+ */
+static const t_u8 ac_to_tid[4][2] = {{1, 2}, {0, 3}, {4, 5}, {6, 7}};
+raListTbl *wlan_wmm_get_ralist_node(pmlan_private priv, t_u8 tid, t_u8 *ra_addr);
+/********************************************************
+    Local Functions
+********************************************************/
+#ifdef DEBUG_LEVEL2
+/**
+ *  @brief Debug print function to display the priority parameters for a WMM AC
+ *
+ *  @param pac_param	Pointer to the AC parameters to display
+ *
+ *  @return		N/A
+ */
+static void wlan_wmm_ac_debug_print(const IEEEtypes_WmmAcParameters_t *pac_param)
+{
+    const char *ac_str[] = {"BK", "BE", "VI", "VO"};
+
+    ENTER();
+
+    PRINTM(MINFO,
+           "WMM AC_%s: ACI=%d, ACM=%d, Aifsn=%d, "
+           "EcwMin=%d, EcwMax=%d, TxopLimit=%d\n",
+           ac_str[wmm_aci_to_qidx_map[pac_param->aci_aifsn.aci]], pac_param->aci_aifsn.aci, pac_param->aci_aifsn.acm,
+           pac_param->aci_aifsn.aifsn, pac_param->ecw.ecw_min, pac_param->ecw.ecw_max,
+           wlan_le16_to_cpu(pac_param->tx_op_limit));
+
+    LEAVE();
+}
+
+/** Print the WMM AC for debug purpose */
+#define PRINTM_AC(pac_param) wlan_wmm_ac_debug_print(pac_param)
+#else
+/** Print the WMM AC for debug purpose */
+#define PRINTM_AC(pac_param)
+#endif
+
+
+/**
+ *  @brief  This function cleans Tx/Rx queues
+ *
+ *  @param priv		A pointer to mlan_private
+ *
+ *  @return		N/A
+ */
+t_void wlan_clean_txrx(pmlan_private priv)
+{
+    mlan_adapter *pmadapter = priv->adapter;
+
+    ENTER();
+
+#if CONFIG_WMM
+    wlan_cleanup_bypass_txq(GET_BSS_ROLE(priv));
+#endif
+
+    wlan_11n_cleanup_reorder_tbl(priv);
+
+    (void)pmadapter->callbacks.moal_spin_lock(pmadapter->pmoal_handle, priv->wmm.ra_list_spinlock);
+    wlan_11n_deleteall_txbastream_tbl(priv);
+#if CONFIG_WMM
+    wlan_ralist_del_all_enh(priv);
+#endif /* CONFIG_WMM */
+    (void)__memcpy(pmadapter, tos_to_tid, ac_to_tid, sizeof(tos_to_tid));
+
+    priv->num_drop_pkts = 0;
+    (void)pmadapter->callbacks.moal_spin_unlock(pmadapter->pmoal_handle, priv->wmm.ra_list_spinlock);
+
+    LEAVE();
+}
+
+/**
+ *  @brief Set the WMM queue priorities to their default values
+ *
+ *  @param priv     Pointer to the mlan_private driver data struct
+ *
+ *  @return         N/A
+ */
+void wlan_wmm_default_queue_priorities(pmlan_private priv)
+{
+    ENTER();
+
+    /* Default queue priorities: VO->VI->BE->BK */
+    priv->wmm.queue_priority[0] = (t_u8)WMM_AC_VO;
+    priv->wmm.queue_priority[1] = (t_u8)WMM_AC_VI;
+    priv->wmm.queue_priority[2] = (t_u8)WMM_AC_BE;
+    priv->wmm.queue_priority[3] = (t_u8)WMM_AC_BK;
+
+    LEAVE();
+}
+
+
+/**
+ *  @brief Initialize the WMM parameter.
+ *
+ *  @param pmadapter  Pointer to the mlan_adapter data structure
+ *
+ *  @return         N/A
+ */
+t_void wlan_init_wmm_param(pmlan_adapter pmadapter)
+{
+    /* Reuse the same structure of WmmAcParameters_t for configuration
+     * purpose here. the definition of acm bit is changed to ucm (user
+     * configuration mode) FW will take the setting of
+     * aifsn,ecw_max,ecw_min, tx_op_limit only when ucm is set to 1.
+     * othewise the default setting/behavoir in firmware will be used.
+     */
+#ifdef RW610
+    pmadapter->ac_params[AC_BE].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_BE].aci_aifsn.aci   = AC_BE;
+    pmadapter->ac_params[AC_BE].aci_aifsn.aifsn = 5;
+    pmadapter->ac_params[AC_BE].ecw.ecw_max     = 6;
+    pmadapter->ac_params[AC_BE].ecw.ecw_min     = 4;
+    pmadapter->ac_params[AC_BE].tx_op_limit     = 0;
+
+    pmadapter->ac_params[AC_BK].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_BK].aci_aifsn.aci   = AC_BK;
+    pmadapter->ac_params[AC_BK].aci_aifsn.aifsn = 9;
+    pmadapter->ac_params[AC_BK].ecw.ecw_max     = 10;
+    pmadapter->ac_params[AC_BK].ecw.ecw_min     = 4;
+    pmadapter->ac_params[AC_BK].tx_op_limit     = 0;
+
+    pmadapter->ac_params[AC_VI].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_VI].aci_aifsn.aci   = AC_VI;
+    pmadapter->ac_params[AC_VI].aci_aifsn.aifsn = 3;
+    pmadapter->ac_params[AC_VI].ecw.ecw_max     = 4;
+    pmadapter->ac_params[AC_VI].ecw.ecw_min     = 3;
+    pmadapter->ac_params[AC_VI].tx_op_limit     = 94;
+
+    pmadapter->ac_params[AC_VO].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_VO].aci_aifsn.aci   = AC_VO;
+    pmadapter->ac_params[AC_VO].aci_aifsn.aifsn = 3;
+    pmadapter->ac_params[AC_VO].ecw.ecw_max     = 3;
+    pmadapter->ac_params[AC_VO].ecw.ecw_min     = 2;
+    pmadapter->ac_params[AC_VO].tx_op_limit     = 47;
+#else
+    pmadapter->ac_params[AC_BE].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_BE].aci_aifsn.aci   = AC_BE;
+    pmadapter->ac_params[AC_BE].aci_aifsn.aifsn = 3;
+    pmadapter->ac_params[AC_BE].ecw.ecw_max     = 10;
+    pmadapter->ac_params[AC_BE].ecw.ecw_min     = 4;
+    pmadapter->ac_params[AC_BE].tx_op_limit     = 0;
+
+    pmadapter->ac_params[AC_BK].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_BK].aci_aifsn.aci   = AC_BK;
+    pmadapter->ac_params[AC_BK].aci_aifsn.aifsn = 7;
+    pmadapter->ac_params[AC_BK].ecw.ecw_max     = 10;
+    pmadapter->ac_params[AC_BK].ecw.ecw_min     = 4;
+    pmadapter->ac_params[AC_BK].tx_op_limit     = 0;
+
+    pmadapter->ac_params[AC_VI].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_VI].aci_aifsn.aci   = AC_VI;
+    pmadapter->ac_params[AC_VI].aci_aifsn.aifsn = 2;
+    pmadapter->ac_params[AC_VI].ecw.ecw_max     = 4;
+    pmadapter->ac_params[AC_VI].ecw.ecw_min     = 3;
+    pmadapter->ac_params[AC_VI].tx_op_limit     = 188;
+
+    pmadapter->ac_params[AC_VO].aci_aifsn.acm   = 0;
+    pmadapter->ac_params[AC_VO].aci_aifsn.aci   = AC_VO;
+    pmadapter->ac_params[AC_VO].aci_aifsn.aifsn = 2;
+    pmadapter->ac_params[AC_VO].ecw.ecw_max     = 3;
+    pmadapter->ac_params[AC_VO].ecw.ecw_min     = 2;
+    pmadapter->ac_params[AC_VO].tx_op_limit     = 102;
+#endif
+}
+
+/**
+ *  @brief Initialize the WMM state information and the WMM data path queues.
+ *
+ *  @param pmadapter  Pointer to the mlan_adapter data structure
+ *
+ *  @return         N/A
+ */
+t_void wlan_wmm_init(pmlan_adapter pmadapter)
+{
+    t_u8 i, j;
+    pmlan_private priv;
+
+    ENTER();
+
+    for (j = 0; j < pmadapter->priv_num; ++j)
+    {
+        priv = pmadapter->priv[j];
+        if (priv != MNULL)
+        {
+            for (i = 0; i < MAX_NUM_TID; ++i)
+            {
+                priv->wmm.pkts_queued[i]              = 0;
+                priv->wmm.tid_tbl_ptr[i].ra_list_curr = MNULL;
+            }
+
+            priv->add_ba_param.timeout = MLAN_DEFAULT_BLOCK_ACK_TIMEOUT;
+            if (priv->bss_type == MLAN_BSS_TYPE_STA)
+            {
+                priv->add_ba_param.tx_win_size = MLAN_STA_AMPDU_DEF_TXWINSIZE;
+                priv->add_ba_param.rx_win_size = MLAN_STA_AMPDU_DEF_RXWINSIZE;
+            }
+            if (priv->bss_type == MLAN_BSS_TYPE_UAP
+            )
+            {
+                priv->add_ba_param.tx_win_size = MLAN_UAP_AMPDU_DEF_TXWINSIZE;
+                priv->add_ba_param.rx_win_size = MLAN_UAP_AMPDU_DEF_RXWINSIZE;
+            }
+            priv->add_ba_param.tx_amsdu = MTRUE;
+            priv->add_ba_param.rx_amsdu = MTRUE;
+            (void)__memset(priv->adapter, priv->rx_seq, 0xff, sizeof(priv->rx_seq));
+            wlan_wmm_default_queue_priorities(priv);
+        }
+    }
+
+    LEAVE();
+}
+
+/**
+ *   @brief Get ralist node
+ *
+ *   @param priv     Pointer to the mlan_private driver data struct
+ *   @param tid      TID
+ *   @param ra_addr  Pointer to the route address
+ *
+ *   @return         ra_list or MNULL
+ */
+raListTbl *wlan_wmm_get_ralist_node(pmlan_private priv, t_u8 tid, t_u8 *ra_addr)
+{
+    raListTbl *ra_list;
+    ENTER();
+    ra_list =
+        (raListTbl *)util_peek_list(priv->adapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[tid].ra_list, MNULL, MNULL);
+    while (ra_list && (ra_list != (raListTbl *)&priv->wmm.tid_tbl_ptr[tid].ra_list))
+    {
+        if (!__memcmp(priv->adapter, ra_list->ra, ra_addr, MLAN_MAC_ADDR_LENGTH))
+        {
+            LEAVE();
+            return ra_list;
+        }
+        ra_list = ra_list->pnext;
+    }
+    LEAVE();
+    return MNULL;
+}
+
+
+
+/**
+ *  @brief Call back from the command module to allow insertion of a WMM TLV
+ *
+ *  If the BSS we are associating to supports WMM, add the required WMM
+ *    Information IE to the association request command buffer in the form
+ *    of a NXP extended IEEE IE.
+ *
+ *  @param priv        Pointer to the mlan_private driver data struct
+ *  @param ppAssocBuf  Output parameter: Pointer to the TLV output buffer,
+ *                     modified on return to point after the appended WMM TLV
+ *  @param pWmmIE      Pointer to the WMM IE for the BSS we are joining
+ *  @param pHTCap      Pointer to the HT IE for the BSS we are joining
+ *
+ *  @return Length of data appended to the association tlv buffer
+ */
+t_u32 wlan_wmm_process_association_req(pmlan_private priv,
+                                       t_u8 **ppAssocBuf,
+                                       IEEEtypes_WmmParameter_t *pWmmIE,
+                                       IEEEtypes_HTCap_t *pHTCap)
+{
+    MrvlIEtypes_WmmParamSet_t *pwmm_tlv;
+    t_u32 ret_len = 0;
+
+    ENTER();
+
+    /* Null checks */
+    if (ppAssocBuf == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+    if ((*ppAssocBuf) == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+
+    if (pWmmIE == MNULL)
+    {
+        LEAVE();
+        return 0;
+    }
+
+    PRINTM(MINFO, "WMM: process assoc req: bss->wmmIe=0x%x\n", pWmmIE->vend_hdr.element_id);
+
+    if ((priv->wmm_required || ((pHTCap != MNULL) && (pHTCap->ieee_hdr.element_id == HT_CAPABILITY) &&
+                                (priv->config_bands & BAND_GN || priv->config_bands & BAND_AN))) &&
+        pWmmIE->vend_hdr.element_id == WMM_IE)
+    {
+        pwmm_tlv              = (MrvlIEtypes_WmmParamSet_t *)(void *)*ppAssocBuf;
+        pwmm_tlv->header.type = (t_u16)wmm_info_ie[0];
+        pwmm_tlv->header.type = wlan_cpu_to_le16(pwmm_tlv->header.type);
+        pwmm_tlv->header.len  = (t_u16)wmm_info_ie[1];
+        (void)__memcpy(priv->adapter, pwmm_tlv->wmm_ie, &wmm_info_ie[2], pwmm_tlv->header.len);
+        if (pWmmIE->qos_info.qos_uapsd != 0U)
+        {
+            (void)__memcpy(priv->adapter, (t_u8 *)(pwmm_tlv->wmm_ie + pwmm_tlv->header.len - sizeof(priv->wmm_qosinfo)),
+                           &priv->wmm_qosinfo, sizeof(priv->wmm_qosinfo));
+        }
+
+        ret_len              = sizeof(pwmm_tlv->header) + pwmm_tlv->header.len;
+        pwmm_tlv->header.len = wlan_cpu_to_le16(pwmm_tlv->header.len);
+
+        HEXDUMP("ASSOC_CMD: WMM IE", (t_u8 *)pwmm_tlv, ret_len);
+        *ppAssocBuf += ret_len;
+    }
+
+    LEAVE();
+    return ret_len;
+}
+
+#if CONFIG_WMM
+/**
+ *  @brief This function prepares the command of WMM_PARAM_CONFIG
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param cmd          A pointer to HostCmd_DS_COMMAND structure
+ *  @param cmd_action   cmd action.
+ *  @param pdata_buf    A pointer to data buffer
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_cmd_wmm_param_config(pmlan_private pmpriv, HostCmd_DS_COMMAND *cmd, t_u8 cmd_action, t_void *pdata_buf)
+{
+    wmm_ac_parameters_t *ac_params        = (wmm_ac_parameters_t *)pdata_buf;
+    HostCmd_DS_WMM_PARAM_CONFIG *pcmd_cfg = &cmd->params.param_config;
+    t_u8 i                                = 0;
+
+    ENTER();
+
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_WMM_PARAM_CONFIG);
+    cmd->size    = wlan_cpu_to_le16(sizeof(HostCmd_DS_WMM_PARAM_CONFIG) + S_DS_GEN);
+    cmd->result  = 0;
+
+    pcmd_cfg->action = cmd_action;
+    if (cmd_action == HostCmd_ACT_GEN_SET)
+    {
+        (void)__memcpy(pmpriv->adapter, pcmd_cfg->ac_params, ac_params, sizeof(wmm_ac_parameters_t) * MAX_AC_QUEUES);
+        for (i = 0; i < MAX_AC_QUEUES; i++)
+        {
+            pcmd_cfg->ac_params[i].tx_op_limit = wlan_cpu_to_le16(pcmd_cfg->ac_params[i].tx_op_limit);
+        }
+    }
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function handles the command response of WMM_PARAM_CONFIG
+ *
+ *  @param pmpriv       A pointer to mlan_private structure
+ *  @param resp         A pointer to HostCmd_DS_COMMAND
+ *  @param pioctl_buf   A pointer to mlan_ioctl_req structure
+ *
+ *  @return             MLAN_STATUS_SUCCESS
+ */
+mlan_status wlan_ret_wmm_param_config(pmlan_private pmpriv, const HostCmd_DS_COMMAND *resp, mlan_ioctl_req *pioctl_buf)
+{
+    mlan_ds_wmm_cfg *pwmm             = MNULL;
+    HostCmd_DS_WMM_PARAM_CONFIG *pcfg = (HostCmd_DS_WMM_PARAM_CONFIG *)&resp->params.param_config;
+    t_u8 i;
+
+    ENTER();
+
+    if (pioctl_buf)
+    {
+        pwmm = (mlan_ds_wmm_cfg *)pioctl_buf->pbuf;
+        for (i = 0; i < MAX_AC_QUEUES; i++)
+        {
+            pcfg->ac_params[i].tx_op_limit = wlan_le16_to_cpu(pcfg->ac_params[i].tx_op_limit);
+        }
+        (void)__memcpy(pmpriv->adapter, pwmm->param.ac_params, pcfg->ac_params,
+                       sizeof(wmm_ac_parameters_t) * MAX_AC_QUEUES);
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_WMM
+#if CONFIG_WMM_DEBUG
+#define MAX_HISTORY_RA_LIST_NUM 32
+
+static raListTbl *wlan_ralist_get_history(mlan_private *priv, t_u8 *ra, t_u8 ac)
+{
+    raListTbl *ra_list = (raListTbl *)util_peek_list(priv->adapter->pmoal_handle, &priv->wmm.hist_ra[ac], MNULL, MNULL);
+
+    if (ra_list == MNULL)
+        return MNULL;
+
+    while (ra_list && ra_list != (raListTbl *)&priv->wmm.hist_ra[ac])
+    {
+        if (!memcmp(priv->adapter, ra, ra_list->ra, MLAN_MAC_ADDR_LENGTH))
+            return ra_list;
+
+        ra_list = ra_list->pnext;
+    }
+    return MNULL;
+}
+
+/* restore ralist to history list for debug */
+static void wlan_ralist_restore_history(mlan_private *priv, raListTbl *ra_list, t_u8 ac)
+{
+    raListTbl *tmp = MNULL;
+
+    /* history lists has same ra, update stats and insert to tail */
+    tmp = wlan_ralist_get_history(priv, ra_list->ra, ac);
+    if (tmp != MNULL)
+    {
+        util_unlink_list(priv->adapter->pmoal_handle, &priv->wmm.hist_ra[ac], (mlan_linked_list *)tmp, MNULL, MNULL);
+        ra_list->drop_count += tmp->drop_count;
+        util_enqueue_list_tail(priv->adapter->pmoal_handle, &priv->wmm.hist_ra[ac], (mlan_linked_list *)ra_list, MNULL,
+                               MNULL);
+        goto FREE_TMP;
+    }
+
+    /* history ralist count reaches max, dequeue the earliest ralist */
+    if (priv->wmm.hist_ra_count[ac] >= MAX_HISTORY_RA_LIST_NUM)
+    {
+        tmp = (raListTbl *)util_dequeue_list(priv->adapter->pmoal_handle, &priv->wmm.hist_ra[ac], MNULL, MNULL);
+        if (tmp == MNULL)
+        {
+            wifi_e("%s error history ralist count %hhu", priv->wmm.hist_ra_count[ac]);
+            goto FREE_IN;
+        }
+
+        util_enqueue_list_tail(priv->adapter->pmoal_handle, &priv->wmm.hist_ra[ac], (mlan_linked_list *)ra_list, MNULL,
+                               MNULL);
+        goto FREE_TMP;
+    }
+    else
+    {
+        util_enqueue_list_tail(priv->adapter->pmoal_handle, &priv->wmm.hist_ra[ac], (mlan_linked_list *)ra_list, MNULL,
+                               MNULL);
+        priv->wmm.hist_ra_count[ac]++;
+    }
+
+    return;
+FREE_TMP:
+    priv->adapter->callbacks.moal_free_semaphore(priv->adapter->pmoal_handle, &tmp->buf_head.plock);
+    priv->adapter->callbacks.moal_mfree(priv->adapter->pmoal_handle, (t_u8 *)tmp);
+    return;
+FREE_IN:
+    priv->adapter->callbacks.moal_free_semaphore(priv->adapter->pmoal_handle, &ra_list->buf_head.plock);
+    priv->adapter->callbacks.moal_mfree(priv->adapter->pmoal_handle, (t_u8 *)ra_list);
+    return;
+}
+#endif
+
+/*
+ *  transfer destination address to receive address
+ *  consider 802.3 DA as RA
+ *  for broadcast and multicast, consider RA as broadcast mac address
+ */
+void wifi_wmm_da_to_ra(uint8_t *da, uint8_t *ra)
+{
+    if ((da[0] & 0x01) == 1)
+        (void)__memset(mlan_adap, ra, 0xff, MLAN_MAC_ADDR_LENGTH);
+    else
+        (void)__memcpy(mlan_adap, ra, da, MLAN_MAC_ADDR_LENGTH);
+}
+
+/*
+ *  check ra tx_pause status
+ *  1. STA mode: check priv->tx_pause
+ *  2. UAP mode:
+ *      a. broadcast/multicast ra: check in ralists
+ *      b. unicast ra: check in ampdu_stat_array for quick access
+ */
+static uint8_t wifi_wmm_is_tx_pause(const uint8_t interface, mlan_wmm_ac_e queue, uint8_t *ra)
+{
+    t_u8 is_tx_pause   = MFALSE;
+    raListTbl *ra_list = MNULL;
+
+    if (interface == MLAN_BSS_TYPE_STA)
+    {
+        is_tx_pause = mlan_adap->priv[0]->tx_pause;
+    }
+    else if (interface == MLAN_BSS_TYPE_UAP)
+    {
+        if (mlan_adap->priv[1]->tx_pause == MTRUE)
+        {
+            is_tx_pause = MTRUE;
+        }
+        else
+        {
+            mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle,
+                                                    &mlan_adap->priv[interface]->wmm.tid_tbl_ptr[queue].ra_list.plock);
+
+            ra_list = wlan_wmm_get_ralist_node(mlan_adap->priv[interface], queue, ra);
+            if (ra_list != MNULL)
+                is_tx_pause = ra_list->tx_pause;
+
+            mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle,
+                                                    &mlan_adap->priv[interface]->wmm.tid_tbl_ptr[queue].ra_list.plock);
+        }
+    }
+
+    return is_tx_pause;
+}
+
+/*
+ *  find the alternative buffer paused in txqueue and replace it,
+ *  priv->tx_pause 1: replace any ra node's oldest packet
+ *  tx_pause 1: replace the same ra node's oldest packet
+ *  tx_pause 0: replace any other tx_paused ra node's oldest packet
+ */
+static outbuf_t *wifi_wmm_get_alter_buf_from_txqueue(const uint8_t interface, t_u8 *ra, t_u8 queue, t_u8 tx_pause)
+{
+    raListTbl *ra_list_head = MNULL;
+    raListTbl *ra_list      = MNULL;
+    outbuf_t *buf           = MNULL;
+
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle,
+                                            &mlan_adap->priv[interface]->wmm.tid_tbl_ptr[queue].ra_list.plock);
+
+    if (mlan_adap->priv[interface]->wmm.pkts_queued[queue] == 0)
+        goto FAIL;
+
+    ra_list_head = (raListTbl *)&mlan_adap->priv[interface]->wmm.tid_tbl_ptr[queue].ra_list;
+    ra_list      = (raListTbl *)util_peek_list(mlan_adap->pmoal_handle, (mlan_list_head *)ra_list_head, MNULL, MNULL);
+
+    while (ra_list && ra_list != ra_list_head)
+    {
+        mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &ra_list->buf_head.plock);
+        if (__memcmp(mlan_adap, ra, ra_list->ra, MLAN_MAC_ADDR_LENGTH) && ra_list->tx_pause == MTRUE &&
+            ra_list->total_pkts != 0)
+        {
+            buf = (outbuf_t *)util_dequeue_list(mlan_adap->pmoal_handle, &ra_list->buf_head, MNULL, MNULL);
+            if (buf != MNULL)
+                goto SUCC;
+        }
+        mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &ra_list->buf_head.plock);
+        ra_list = ra_list->pnext;
+    }
+
+FAIL:
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle,
+                                            &mlan_adap->priv[interface]->wmm.tid_tbl_ptr[queue].ra_list.plock);
+    return MNULL;
+SUCC:
+    mlan_adap->priv[interface]->wmm.pkts_queued[queue]--;
+    ra_list->total_pkts--;
+    ra_list->drop_count++;
+#if CONFIG_TX_RX_ZERO_COPY
+    /* Before replacement, need free the buffer from stack first */
+    net_stack_buffer_free(buf->buffer);
+#endif
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &ra_list->buf_head.plock);
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle,
+                                            &mlan_adap->priv[interface]->wmm.tid_tbl_ptr[queue].ra_list.plock);
+
+    wifi_wmm_drop_pause_replaced(interface);
+    return buf;
+}
+
+/* wmm enhance get free buffer */
+uint8_t *wifi_wmm_get_outbuf_enh(
+    uint32_t *outbuf_len, mlan_wmm_ac_e queue, const uint8_t interface, uint8_t *ra, bool *is_tx_pause)
+{
+    t_u8 i;
+    outbuf_t *buf = MNULL;
+    t_u8 tx_pause;
+
+    buf = wifi_wmm_buf_get();
+    if (buf != MNULL)
+        goto SUCC;
+
+    /* check tx_pause */
+    tx_pause     = wifi_wmm_is_tx_pause(interface, queue, ra);
+    *is_tx_pause = (tx_pause == MTRUE) ? true : false;
+
+    /* loop tid_tbl to find buf to replace in wmm ralists */
+    if (tx_pause == MFALSE)
+    {
+        for (i = 0; i < MAX_AC_QUEUES; i++)
+        {
+            buf = wifi_wmm_get_alter_buf_from_txqueue(interface, ra, i, tx_pause);
+            if (buf != MNULL)
+                goto SUCC;
+        }
+    }
+
+    *outbuf_len = 0;
+    return MNULL;
+SUCC:
+    *outbuf_len = OUTBUF_WMM_LEN;
+    return (uint8_t *)buf;
+}
+
+/*
+ *  get RA list for tx enqueue,
+ *  check add broadcast RA list,
+ *  drop unknown RA packets in UAP mode
+ */
+static raListTbl *wlan_wmm_get_queue_raptr_enh(pmlan_private priv, t_u8 ac, t_u8 *ra_addr)
+{
+    raListTbl *ra_list = MNULL;
+    t_u8 bcast_addr[]  = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+    ra_list = wlan_wmm_get_ralist_node(priv, ac, ra_addr);
+    if (ra_list != MNULL)
+        return ra_list;
+
+#if CONFIG_WPA_SUPP
+    if ((GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP) &&
+         (0 != memcmp(ra_addr, bcast_addr, sizeof(bcast_addr))))
+    {
+        if (MNULL == wlan_get_station_entry(priv, ra_addr))
+        {
+            PRINTM(MERROR, "Drop packets to unknow station " MACSTR "\n",  MAC2STR(ra_addr));
+            LEAVE();
+            return MNULL;
+        }
+    }
+#else
+    if (GET_BSS_ROLE(priv) == MLAN_BSS_ROLE_UAP && __memcmp(priv->adapter, ra_addr, bcast_addr, MLAN_MAC_ADDR_LENGTH))
+        return MNULL;
+#endif
+
+    /* wlan_ralist_add_enh will hold wmm lock, so need to unlock first */
+    priv->adapter->callbacks.moal_semaphore_put(priv->adapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[ac].ra_list.plock);
+
+    wlan_ralist_add_enh(priv, ra_addr);
+
+    priv->adapter->callbacks.moal_semaphore_get(priv->adapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[ac].ra_list.plock);
+
+    ra_list = wlan_wmm_get_ralist_node(priv, ac, ra_addr);
+    return ra_list;
+}
+
+/* wmm enhance enqueue tx buffer */
+int wlan_wmm_add_buf_txqueue_enh(const uint8_t interface, const uint8_t *buffer, const uint16_t len, uint8_t pkt_prio)
+{
+    mlan_private *priv            = MNULL;
+    t_u8 ra[MLAN_MAC_ADDR_LENGTH] = {0x0};
+    raListTbl *ralist             = MNULL;
+
+    if (interface == MLAN_BSS_TYPE_STA)
+        priv = mlan_adap->priv[0];
+    else
+        priv = mlan_adap->priv[1];
+
+        /* refer to low_level_output payload memcpy */
+#if CONFIG_TX_RX_ZERO_COPY
+    wifi_wmm_da_to_ra(&((outbuf_t *)buffer)->eth_header[0], ra);
+#else
+    wifi_wmm_da_to_ra(&((outbuf_t *)buffer)->data[0], ra);
+#endif
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &priv->wmm.tid_tbl_ptr[pkt_prio].ra_list.plock);
+
+    ralist = wlan_wmm_get_queue_raptr_enh(priv, pkt_prio, ra);
+    if (ralist == MNULL)
+    {
+        /* drop for unknown ra when enqueue */
+        wifi_wmm_buf_put((outbuf_t *)buffer);
+        mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle,
+                                                &priv->wmm.tid_tbl_ptr[pkt_prio].ra_list.plock);
+        return MLAN_STATUS_FAILURE;
+    }
+
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+
+    util_enqueue_list_tail(mlan_adap->pmoal_handle, &ralist->buf_head, (mlan_linked_list *)buffer, MNULL, MNULL);
+    ralist->total_pkts++;
+    priv->wmm.pkts_queued[pkt_prio]++;
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &priv->wmm.tid_tbl_ptr[pkt_prio].ra_list.plock);
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/* wmm enhance buffer pool management */
+/* return NULL if wmm free list is empty */
+outbuf_t *wifi_wmm_buf_get(void)
+{
+    outbuf_t *buf = MNULL;
+
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+
+    assert(mlan_adap->outbuf_pool.free_cnt >= 0);
+
+    if (mlan_adap->outbuf_pool.free_cnt == 0)
+    {
+        mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+        return MNULL;
+    }
+
+    buf = (outbuf_t *)util_dequeue_list(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list, MNULL, MNULL);
+    assert(buf != MNULL);
+    mlan_adap->outbuf_pool.free_cnt--;
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+    return buf;
+}
+
+void wifi_wmm_buf_put(outbuf_t *buf)
+{
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+
+    assert(mlan_adap->outbuf_pool.free_cnt < MAX_WMM_BUF_NUM);
+
+#if CONFIG_TX_RX_ZERO_COPY
+    /* Free driver's reference count for network buffer */
+    net_stack_buffer_free(buf->buffer);
+#endif
+
+    util_enqueue_list_tail(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list, &buf->entry, MNULL, MNULL);
+    mlan_adap->outbuf_pool.free_cnt++;
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+}
+
+/* init free list, insert all buffers to free list */
+int wifi_wmm_buf_pool_init(uint8_t *pool)
+{
+    int i;
+    outbuf_t *buf = MNULL;
+
+    __memset(mlan_adap, &mlan_adap->outbuf_pool, 0x00, sizeof(outbuf_pool_t));
+
+    util_init_list_head(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list, MFALSE, MNULL);
+
+    if (mlan_adap->callbacks.moal_init_semaphore(mlan_adap->pmoal_handle, "wmm_buf_pool_sem",
+                                                 &mlan_adap->outbuf_pool.free_list.plock) != MLAN_STATUS_SUCCESS)
+        return WM_E_NOMEM;
+
+    for (i = 0; i < MAX_WMM_BUF_NUM; i++)
+    {
+        /* TODO: where to put buffer pool mgmt codes */
+        // buf = (outbuf_t *)&outbuf_arr[i][0];
+        buf = (outbuf_t *)(pool + (i * OUTBUF_WMM_LEN));
+        util_init_list(&buf->entry);
+        util_enqueue_list_tail(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list, &buf->entry, MNULL, MNULL);
+    }
+    mlan_adap->outbuf_pool.free_cnt = MAX_WMM_BUF_NUM;
+
+    return WM_SUCCESS;
+}
+
+/* deinit free list, should be called after all buffers are put back */
+void wifi_wmm_buf_pool_deinit(void)
+{
+    mlan_adap->outbuf_pool.free_cnt = 0;
+
+    mlan_adap->callbacks.moal_free_semaphore(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list.plock);
+
+    util_free_list_head(mlan_adap->pmoal_handle, &mlan_adap->outbuf_pool.free_list, MNULL);
+
+    __memset(mlan_adap, &mlan_adap->outbuf_pool, 0x00, sizeof(outbuf_pool_t));
+}
+
+/* wmm enhance ralist operation */
+/* should be called inside wmm tid_tbl_ptr ra_list lock */
+void wlan_ralist_pkts_free_enh(mlan_private *priv, raListTbl *ra_list, t_u8 ac)
+{
+    outbuf_t *buff = MNULL;
+
+    priv->adapter->callbacks.moal_semaphore_get(priv->adapter->pmoal_handle, &ra_list->buf_head.plock);
+
+    while ((buff = (outbuf_t *)util_peek_list(priv->adapter->pmoal_handle, &ra_list->buf_head, MNULL, MNULL)))
+    {
+        util_unlink_list(priv->adapter->pmoal_handle, &ra_list->buf_head, &buff->entry, MNULL, MNULL);
+        wifi_wmm_buf_put(buff);
+
+        priv->wmm.pkts_queued[ac]--;
+        wifi_wmm_drop_no_media(priv->bss_index);
+        ra_list->drop_count++;
+    }
+    ra_list->total_pkts = 0;
+
+    priv->adapter->callbacks.moal_semaphore_put(priv->adapter->pmoal_handle, &ra_list->buf_head.plock);
+}
+
+/* should be called inside wmm tid_tbl_ptr ra_list lock */
+static void wlan_ralist_free_enh(mlan_private *priv, raListTbl *ra_list, t_u8 ac)
+{
+#if CONFIG_WMM_DEBUG
+    wlan_ralist_restore_history(priv, ra_list, ac);
+#else
+    priv->adapter->callbacks.moal_free_semaphore(priv->adapter->pmoal_handle, &ra_list->buf_head.plock);
+#if !CONFIG_MEM_POOLS
+
+    priv->adapter->callbacks.moal_mfree(priv->adapter->pmoal_handle, (t_u8 *)ra_list);
+#else
+    OSA_MemoryPoolFree(buf_128_MemoryPool, ra_list);
+#endif
+#endif
+}
+
+static raListTbl *wlan_ralist_alloc_enh(pmlan_adapter pmadapter, t_u8 *ra)
+{
+    mlan_status ret;
+    raListTbl *ra_list = MNULL;
+
+#if !CONFIG_MEM_POOLS
+    ret = pmadapter->callbacks.moal_malloc(pmadapter->pmoal_handle, sizeof(raListTbl), MLAN_MEM_DEF, (t_u8 **)&ra_list);
+    if (ret != MLAN_STATUS_SUCCESS || ra_list == MNULL)
+        return MNULL;
+#else
+    ra_list = OSA_MemoryPoolAllocate(buf_128_MemoryPool);
+    if (ra_list == MNULL)
+    {
+        return MNULL;
+    }
+
+#endif
+
+    util_init_list((pmlan_linked_list)ra_list);
+    util_init_list_head((t_void *)pmadapter->pmoal_handle, &ra_list->buf_head, MFALSE, MNULL);
+
+    ret = pmadapter->callbacks.moal_init_semaphore(pmadapter->pmoal_handle, "buf_head_sem", &ra_list->buf_head.plock);
+    if (ret != MLAN_STATUS_SUCCESS)
+    {
+        pmadapter->callbacks.moal_mfree(pmadapter->pmoal_handle, (t_u8 *)ra_list);
+        return MNULL;
+    }
+
+    (void)__memcpy(pmadapter, ra_list->ra, ra, MLAN_MAC_ADDR_LENGTH);
+
+    ra_list->total_pkts = 0;
+    ra_list->tx_pause   = 0;
+    ra_list->drop_count = 0;
+
+    wifi_d("RAList: Allocating buffers for TID %p\n", ra_list);
+
+    return ra_list;
+}
+
+void wlan_ralist_add_enh(mlan_private *priv, t_u8 *ra)
+{
+    int i;
+    raListTbl *ra_list      = MNULL;
+    pmlan_adapter pmadapter = priv->adapter;
+
+    for (i = 0; i < MAX_AC_QUEUES; i++)
+    {
+        if ((ra_list = wlan_wmm_get_ralist_node(priv, i, ra)))
+            continue;
+
+        ra_list = wlan_ralist_alloc_enh(pmadapter, ra);
+        wifi_d("Creating RA List %p for tid %d\n", ra_list, i);
+        if (ra_list == MNULL)
+        {
+            wifi_e("Creating RA List for tid %d fail", i);
+            break;
+        }
+
+        pmadapter->callbacks.moal_semaphore_get(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+
+        util_enqueue_list_tail(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list, (pmlan_linked_list)ra_list,
+                               MNULL, MNULL);
+
+        if (priv->wmm.tid_tbl_ptr[i].ra_list_curr == MNULL)
+            priv->wmm.tid_tbl_ptr[i].ra_list_curr = ra_list;
+
+        pmadapter->callbacks.moal_semaphore_put(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+    }
+}
+
+int wlan_ralist_update_enh(mlan_private *priv, t_u8 *old_ra, t_u8 *new_ra)
+{
+    int i;
+    int update_count   = 0;
+    raListTbl *ra_list = MNULL;
+#if CONFIG_WMM_DEBUG
+    raListTbl *hist_ra_list = MNULL;
+#endif
+
+    for (i = 0; i < MAX_AC_QUEUES; i++)
+    {
+        priv->adapter->callbacks.moal_semaphore_get(priv->adapter->pmoal_handle,
+                                                    &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+
+        ra_list = wlan_wmm_get_ralist_node(priv, i, old_ra);
+        if (ra_list == MNULL)
+        {
+            priv->adapter->callbacks.moal_semaphore_put(priv->adapter->pmoal_handle,
+                                                        &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+            continue;
+        }
+
+        update_count++;
+
+        wlan_ralist_pkts_free_enh(priv, ra_list, i);
+        ra_list->tx_pause = MFALSE;
+
+        (void)__memcpy(priv->adapter, ra_list->ra, new_ra, MLAN_MAC_ADDR_LENGTH);
+
+#if CONFIG_WMM_DEBUG
+        hist_ra_list = wlan_ralist_alloc_enh(priv->adapter, old_ra);
+        if (hist_ra_list != MNULL)
+        {
+            hist_ra_list->drop_count = ra_list->drop_count;
+            wlan_ralist_free_enh(priv, hist_ra_list, i);
+        }
+#endif
+
+        priv->adapter->callbacks.moal_semaphore_put(priv->adapter->pmoal_handle,
+                                                    &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+    }
+
+    return update_count;
+}
+
+void wlan_ralist_del_enh(mlan_private *priv, t_u8 *ra)
+{
+    int i;
+    pmlan_adapter pmadapter = priv->adapter;
+    raListTbl *ra_list      = MNULL;
+
+    for (i = 0; i < MAX_AC_QUEUES; i++)
+    {
+        pmadapter->callbacks.moal_semaphore_get(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+
+        ra_list = wlan_wmm_get_ralist_node(priv, i, ra);
+        if (ra_list == MNULL)
+        {
+            pmadapter->callbacks.moal_semaphore_put(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+            continue;
+        }
+
+        wlan_ralist_pkts_free_enh(priv, ra_list, i);
+
+        util_unlink_list(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list, (pmlan_linked_list)ra_list, MNULL,
+                         MNULL);
+
+        if (priv->wmm.tid_tbl_ptr[i].ra_list_curr == ra_list)
+            priv->wmm.tid_tbl_ptr[i].ra_list_curr = (raListTbl *)&priv->wmm.tid_tbl_ptr[i].ra_list;
+
+        wlan_ralist_free_enh(priv, ra_list, i);
+
+        pmadapter->callbacks.moal_semaphore_put(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+    }
+}
+
+void wlan_ralist_del_all_enh(mlan_private *priv)
+{
+    int i;
+    raListTbl *ra_list      = MNULL;
+    pmlan_adapter pmadapter = priv->adapter;
+
+    for (i = 0; i < MAX_AC_QUEUES; i++)
+    {
+        priv->adapter->callbacks.moal_semaphore_get(priv->adapter->pmoal_handle,
+                                                    &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+
+        while ((ra_list = (raListTbl *)util_peek_list(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list, MNULL,
+                                                      MNULL)))
+        {
+            util_unlink_list(pmadapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list, (pmlan_linked_list)ra_list,
+                             MNULL, MNULL);
+
+            wlan_ralist_pkts_free_enh(priv, ra_list, i);
+
+            wlan_ralist_free_enh(priv, ra_list, i);
+        }
+
+        /* do not reinit list lock, so use util_init_list instead of util_init_list_head */
+        util_init_list((pmlan_linked_list)&priv->wmm.tid_tbl_ptr[i].ra_list);
+        priv->wmm.tid_tbl_ptr[i].ra_list_curr = MNULL;
+        priv->wmm.pkts_queued[i]              = 0;
+
+        priv->adapter->callbacks.moal_semaphore_put(priv->adapter->pmoal_handle,
+                                                    &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+    }
+}
+
+void wlan_ralist_deinit_enh(mlan_private *priv)
+{
+    int i;
+
+    /* already del all ralists in wlan_clean_txrx */
+    // wlan_ralist_del_all_enh(priv);
+
+    for (i = 0; i < MAX_AC_QUEUES; i++)
+    {
+        /* free ralist lock */
+        priv->adapter->callbacks.moal_free_semaphore(priv->adapter->pmoal_handle,
+                                                     &priv->wmm.tid_tbl_ptr[i].ra_list.plock);
+
+        /* deinit ralists table */
+        util_free_list_head(priv->adapter->pmoal_handle, &priv->wmm.tid_tbl_ptr[i].ra_list, MNULL);
+    }
+}
+
+/* debug statistics */
+void wifi_wmm_drop_err_mem(const uint8_t interface)
+{
+    if (interface == MLAN_BSS_TYPE_STA)
+        mlan_adap->priv[0]->driver_error_cnt.tx_err_mem++;
+    else if (interface == MLAN_BSS_TYPE_UAP)
+        mlan_adap->priv[1]->driver_error_cnt.tx_err_mem++;
+}
+
+void wifi_wmm_drop_no_media(const uint8_t interface)
+{
+    if (interface == MLAN_BSS_TYPE_STA)
+        mlan_adap->priv[0]->driver_error_cnt.tx_no_media++;
+    else if (interface == MLAN_BSS_TYPE_UAP)
+        mlan_adap->priv[1]->driver_error_cnt.tx_no_media++;
+}
+
+void wifi_wmm_drop_retried_drop(const uint8_t interface)
+{
+    if (interface == MLAN_BSS_TYPE_STA)
+        mlan_adap->priv[0]->driver_error_cnt.tx_wmm_retried_drop++;
+    else if (interface == MLAN_BSS_TYPE_UAP)
+        mlan_adap->priv[1]->driver_error_cnt.tx_wmm_retried_drop++;
+}
+
+void wifi_wmm_drop_pause_drop(const uint8_t interface)
+{
+    if (interface == MLAN_BSS_TYPE_STA)
+        mlan_adap->priv[0]->driver_error_cnt.tx_wmm_pause_drop++;
+    else if (interface == MLAN_BSS_TYPE_UAP)
+        mlan_adap->priv[1]->driver_error_cnt.tx_wmm_pause_drop++;
+}
+
+void wifi_wmm_drop_pause_replaced(const uint8_t interface)
+{
+    if (interface == MLAN_BSS_TYPE_STA)
+        mlan_adap->priv[0]->driver_error_cnt.tx_wmm_pause_replaced++;
+    else if (interface == MLAN_BSS_TYPE_UAP)
+        mlan_adap->priv[1]->driver_error_cnt.tx_wmm_pause_replaced++;
+}
+
+void wlan_get_bypass_lock(uint8_t interface)
+{
+    pmlan_private priv = mlan_adap->priv[interface];
+
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &priv->bypass_txq.plock);
+}
+
+void wlan_put_bypass_lock(uint8_t interface)
+{
+    pmlan_private priv = mlan_adap->priv[interface];
+
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &priv->bypass_txq.plock);
+}
+
+void wlan_add_buf_bypass_txq(const uint8_t *buffer, const uint8_t interface)
+{
+    pmlan_private priv = mlan_adap->priv[interface];
+
+    wlan_get_bypass_lock(interface);
+
+    util_enqueue_list_tail(mlan_adap->pmoal_handle, &priv->bypass_txq, (mlan_linked_list *)buffer, MNULL, MNULL);
+    priv->bypass_txq_cnt++;
+
+    wlan_put_bypass_lock(interface);
+}
+
+t_u8 wlan_bypass_txq_empty(uint8_t interface)
+{
+    return (mlan_adap->priv[interface]->bypass_txq_cnt) ? MFALSE : MTRUE;
+}
+
+int wifi_bypass_txq_init(void)
+{
+    pmlan_private priv = NULL;
+    int i;
+
+    for (i = 0; i < mlan_adap->priv_num; ++i)
+    {
+        priv = mlan_adap->priv[i];
+        if (priv != MNULL)
+        {
+            /* Initialize bypass_txq */
+            util_init_list_head((t_void *)mlan_adap->pmoal_handle, &priv->bypass_txq, MFALSE, MNULL);
+            priv->bypass_txq_cnt = 0;
+
+            if (mlan_adap->callbacks.moal_init_semaphore(mlan_adap->pmoal_handle, "bypass_txq_sem",
+                                                         &priv->bypass_txq.plock) != MLAN_STATUS_SUCCESS)
+                return WM_E_NOMEM;
+        }
+    }
+
+    return WM_SUCCESS;
+}
+
+void wlan_cleanup_bypass_txq(uint8_t interface)
+{
+    bypass_outbuf_t *buf;
+    pmlan_private priv = mlan_adap->priv[interface];
+
+    /*Free hold buff*/
+    while (!wlan_bypass_txq_empty(interface))
+    {
+        wlan_get_bypass_lock(interface);
+
+        buf = (bypass_outbuf_t *)util_dequeue_list(mlan_adap->pmoal_handle, &priv->bypass_txq, MNULL, MNULL);
+        priv->bypass_txq_cnt--;
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_1536_MemoryPool, buf);
+#endif
+
+        wlan_put_bypass_lock(interface);
+    }
+}
+
+void wifi_bypass_txq_deinit(void)
+{
+    pmlan_private priv = NULL;
+    int i;
+
+    for (i = 0; i < mlan_adap->priv_num; ++i)
+    {
+        priv = mlan_adap->priv[i];
+        if (priv != MNULL)
+        {
+            wlan_cleanup_bypass_txq(i);
+
+            mlan_adap->callbacks.moal_free_semaphore(mlan_adap->pmoal_handle, &priv->bypass_txq.plock);
+            /* Deinit bypass_txq */
+            util_free_list_head(mlan_adap->pmoal_handle, &priv->bypass_txq, MNULL);
+            priv->bypass_txq_cnt = 0;
+        }
+    }
+}
+#endif /* CONFIG_WMM */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-debug.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-debug.c
new file mode 100644
index 0000000000..cdfaf9f6ca
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-debug.c
@@ -0,0 +1,118 @@
+/** @file wifi-debug.c
+ *
+ *  @brief This file provides WIFI debug APIs.
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <osa.h>
+
+#include <wifi-debug.h>
+
+#if CONFIG_WIFI_EXTRA_DEBUG
+static const char *const status_table[] = {
+    [0]  = "Successful",
+    [1]  = "Unspecified failure",
+    [10] = "Information field does not support all requested capabilities.",
+    [11] = "Could not confirm existing assiciation. Denied reassociation.",
+    [12] = "Denied Association. Reason beyond scope of Standard.",
+    [13] = "Auth Algo not supported by responding station.",
+    [14] = "Transaction sequence number of received authentication frame is out of expected sequence.",
+    [15] = "Challenge failure. Rejected Auth.",
+    [16] = "Timeout waiting for next frame in sequence. Rejected Auth.",
+    [17] = "Failure at AP to to handle additional associated STA. Rejected Assoc.",
+    [18] = "Requesting STA does not support all BSSBasicRateSet data rated. Denied Assoc.",
+    [19] = "Requesting STA does not support short preamble option. Denied Assoc.",
+    [20] = "Requesting STA does not support PBCC modulation option. Denied Assoc.",
+    [21] = "Requesting STA does not support channel agility option. Denied Assoc.",
+    [22] = "Spectrum Management capability needed. Rejected Assoc.",
+    [23] = "Power Capability element info is unacceptable. Rejected Assoc.",
+    [24] = "Supported Channels element info is unacceptable. Rejected Assoc.",
+    [25] = "Requesting STA does not support short slot time option. Rejected Assoc.",
+    [26] = "Requesting STA does not support ER-PBCC modulation option. Rejected Assoc.",
+    [27] = "Requesting STA does not support HT features. Denied Assoc.",
+    [28] = "Unreachable R0KH",
+    [29] = "AP needs PCO transition support. Requesting STA does not support it. Denied Assoc.",
+    [30] = "Try again later. Temporarily Rejected Assoc.",
+    [31] = "Violation of policy for Robust Management frame",
+    [32] = "Unspecified, QoS related failure",
+    [33] = "Insufficient bandwidth with QAP to handle another QSTA. Denied Assoc.",
+    [34] = "Poor channel conditions resulting in Assoic Denied.",
+    [35] = "Requesting STA does not support QoS facility. Denied Assoc (with QBSS).",
+    [37] = "The request has been declined",
+    [38] = "The failed. One or more parameters have invalid values",
+    [39] =
+        "The TS has not been created because the request cannot be "
+        "honored. However, a suggested Tspec is provided so that the "
+        "initiating QSTA may attempt to send another TS with the suggested "
+        "changes to the TSpec",
+    [40] = "Information Element is Invalid",
+    [41] = "Invalid Group Cipher",
+    [42] = "Invalid Pairwise Cipher",
+    [43] = "Invalid AKMP",
+    [44] = "RSN IE version unsupported ",
+    [45] = "RSN IE Capabilities are invalid ",
+    [46] = "Security policy does not allows rejected Cipher suite",
+    [47] =
+        "The TS has not been created. However, the HC may be capable "
+        "of creating a TS, in response to a request, after the time "
+        "indicated in the TS Delay element",
+    [48] = "By policy BSS not allow Direct link",
+    [49] = "QBSS does not include Destination STA",
+    [50] = "The destination STA is not a QSTA",
+    [51] = "Listen Interval is too large. Assoc Denied",
+    [52] = "Fast BSS Transition Action Frame Count Invalid",
+    [53] = "PMKID Invalid",
+    [54] = "MDIE Invalid",
+    [55] = "FTIE Invalid",
+};
+
+const char *get_status_str(uint16_t status)
+{
+    if (status < sizeof(status_table) / sizeof(status_table[0]) && status_table[status])
+        return status_table[status];
+    return "<unknown>";
+}
+#endif /* CONFIG_WIFI_EXTRA_DEBUG */
+
+void wifi_show_assoc_fail_reason(int status)
+{
+#if CONFIG_WIFI_EXTRA_DEBUG
+    (void)PRINTF("[wifi] Assoc Status: %s\n\r", get_status_str(status));
+
+    switch (status)
+    {
+        case 13:
+            (void)PRINTF("Assoc failed: Network not found.\n\r");
+            break;
+        case 18:
+            (void)PRINTF("(11n disabled ?)\n\r");
+            break;
+    }
+#endif /* CONFIG_WIFI_EXTRA_DEBUG */
+}
+
+#ifdef DUMP_PACKET_MAC
+void dump_mac_addr(const char *msg, unsigned char *addr)
+{
+    if (msg)
+        (void)PRINTF("%s: ", msg);
+    else
+        (void)PRINTF("mac: ", msg);
+
+    int i;
+    for (i = 0; i < MLAN_MAC_ADDR_LENGTH; i++)
+    {
+        (void)PRINTF("%x", addr[i]);
+        if (i != (MLAN_MAC_ADDR_LENGTH - 1))
+            (void)PRINTF(":");
+    }
+
+    (void)PRINTF("\n\r");
+}
+#endif /* DUMP_PACKET_MAC */
+
+
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-debug.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-debug.h
new file mode 100644
index 0000000000..a6c75569d6
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-debug.h
@@ -0,0 +1,106 @@
+/** @file wifi-debug.h
+ *
+ *  @brief WLAN Debug Header
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __WIFI_DEBUG_H__
+#define __WIFI_DEBUG_H__
+
+#include <mlan_api.h>
+#include <wmlog.h>
+
+#define wscan_e(...) wmlog_e("wscan", ##__VA_ARGS__)
+#define wscan_w(...) wmlog_w("wscan", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_SCAN_DEBUG
+#define wscan_d(...) wmlog("wscan", ##__VA_ARGS__)
+#else
+#define wscan_d(...)
+#endif /* ! CONFIG_WIFI_SCAN_DEBUG */
+
+#define wifi_e(...) wmlog_e("wifi", ##__VA_ARGS__)
+#define wifi_w(...) wmlog_w("wifi", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_EXTRA_DEBUG
+#define wifi_d(...) wmlog("wifi", ##__VA_ARGS__)
+#else
+#define wifi_d(...)
+#endif /* ! CONFIG_WIFI_EXTRA_DEBUG */
+
+#define ampdu_e(...) wmlog_e("ampdu", ##__VA_ARGS__)
+#define ampdu_w(...) wmlog_w("ampdu", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_AMPDU_DEBUG
+#define ampdu_d(...) wmlog("ampdu", ##__VA_ARGS__)
+#else
+#define ampdu_d(...)
+#endif /* ! CONFIG_WIFI_AMPDU_DEBUG */
+
+#define w_tmr_e(...) wmlog_e("w_tmr", ##__VA_ARGS__)
+#define w_tmr_w(...) wmlog_w("w_tmr", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_TIMER_DEBUG
+#define w_tmr_d(...) wmlog("w_tmr", ##__VA_ARGS__)
+#else
+#define w_tmr_d(...)
+#endif /* CONFIG_WIFI_TIMER_DEBUG */
+
+#define w_mem_e(...) wmlog_e("w_mem", ##__VA_ARGS__)
+#define w_mem_w(...) wmlog_w("w_mem", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_MEM_DEBUG
+#define w_mem_d(...) wmlog("w_mem", ##__VA_ARGS__)
+#else
+#define w_mem_d(...)
+#endif /* ! CONFIG_WIFI_MEM_DEBUG */
+
+#define w_pkt_e(...) wmlog_e("w_pkt", ##__VA_ARGS__)
+#define w_pkt_w(...) wmlog_w("w_pkt", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_PKT_DEBUG
+#define w_pkt_d(...) wmlog("w_pkt", ##__VA_ARGS__)
+#else
+#define w_pkt_d(...)
+#endif /* ! CONFIG_WIFI_PKT_DEBUG */
+
+#define wevt_e(...) wmlog_e("wevt", ##__VA_ARGS__)
+#define wevt_w(...) wmlog_w("wevt", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_EVENTS_DEBUG
+#define wevt_d(...) wmlog("wevt", ##__VA_ARGS__)
+#else
+#define wevt_d(...)
+#endif /* ! CONFIG_WIFI_EVENTS_DEBUG */
+
+#define wcmdr_e(...) wmlog_e("wcmdr", ##__VA_ARGS__)
+#define wcmdr_w(...) wmlog_w("wcmdr", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_CMD_RESP_DEBUG
+#define wcmdr_d(...) wmlog("wcmdr", ##__VA_ARGS__)
+#else
+#define wcmdr_d(...)
+#endif /* ! CONFIG_WIFI_CMD_RESP_DEBUG */
+
+#define wuap_e(...) wmlog_e("uap", ##__VA_ARGS__)
+#define wuap_w(...) wmlog_w("uap", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_UAP_DEBUG
+#define wuap_d(...) wmlog("uap", ##__VA_ARGS__)
+#else
+#define wuap_d(...)
+#endif /* ! CONFIG_WIFI_UAP_DEBUG */
+
+void wifi_show_assoc_fail_reason(int status);
+
+#ifdef DUMP_PACKET_MAC
+void dump_mac_addr(const char *msg, unsigned char *addr);
+#endif /* DUMP_PACKET_MAC */
+
+
+
+#endif /* __WIFI_DEBUG_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-imu.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-imu.c
new file mode 100644
index 0000000000..576373b910
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-imu.c
@@ -0,0 +1,1815 @@
+/** @file wifi-imu.c
+ *
+ *  @brief  This file provides WLAN Card related API
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mlan_api.h>
+#ifndef RW610
+#include <mlan_sdio_api.h>
+#endif
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+#include <wm_utils.h>
+#include <mlan_fw.h>
+#include "wifi-imu.h"
+#include "wifi-internal.h"
+#include "fsl_common.h"
+#include "fsl_adapter_imu.h"
+#include "fsl_imu.h"
+#include "fsl_loader.h"
+
+/* Buffer pointers to point to command and, command response buffer */
+static uint8_t cmd_buf[WIFI_FW_CMDBUF_SIZE];
+// static t_u32 seqnum;
+// static int pm_handle;
+#define IMU_OUTBUF_LEN       3072
+#define IMU_INIT_FW_CMD_SIZE 256
+
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#ifndef MCI_WAKEUP_DONE_PRIORITY
+#define MCI_WAKEUP_DONE_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1)
+#endif
+#ifndef MCI_WAKEUP_SRC_PRIORITY
+#define MCI_WAKEUP_SRC_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 2)
+#endif
+#else
+#ifndef MCI_WAKEUP_DONE_PRIORITY
+#define MCI_WAKEUP_DONE_PRIORITY (3U)
+#endif
+#ifndef MCI_WAKEUP_SRC_PRIORITY
+#define MCI_WAKEUP_SRC_PRIORITY (4U)
+#endif
+#endif
+/*
+ * Used to authorize the SDIO interrupt handler to accept the incoming
+ * packet from the SDIO interface. If this flag is set a semaphore is
+ * signalled.
+ */
+bool g_txrx_flag;
+
+#ifdef RW610
+bool cal_data_valid_rw610;
+#endif
+
+int mlan_subsys_init(void);
+int mlan_subsys_deinit();
+
+const uint8_t *wlanfw;
+
+t_u32 last_resp_rcvd, last_cmd_sent;
+
+OSA_MUTEX_HANDLE_DEFINE(txrx_mutex);
+
+#ifndef RW610
+osa_task_handle_t wifi_core_thread;
+#endif
+static struct
+{
+    /* Where the cmdresp/event should be dispached depends on its value */
+    /* int special; */
+    /* Default queue where the cmdresp/events will be sent */
+    osa_msgq_handle_t event_queue;
+    int (*wifi_low_level_input)(const uint8_t interface, const uint8_t *buffer, const uint16_t len);
+} bus;
+
+/* remove this after mlan integration complete */
+enum
+{
+    MLAN_CARD_NOT_DETECTED = 3,
+    MLAN_STATUS_FW_DNLD_FAILED,
+    MLAN_STATUS_FW_NOT_DETECTED = 5,
+    MLAN_STATUS_FW_NOT_READY,
+    MLAN_STATUS_FW_XZ_FAILED,
+    MLAN_CARD_CMD_TIMEOUT
+};
+
+/* @brief decription about the read/write buffer
+ * The size of the read/write buffer should be a multiple of 512, since SDHC/SDXC card uses 512-byte fixed
+ * block length and this driver example is enabled with a SDHC/SDXC card.If you are using a SDSC card, you
+ * can define the block length by yourself if the card supports partial access.
+ * The address of the read/write buffer should align to the specific DMA data buffer address align value if
+ * DMA transfer is used, otherwise the buffer address is not important.
+ * At the same time buffer address/size should be aligned to the cache line size if cache is supported.
+ */
+/*! @brief Data written to the card */
+SDK_ALIGN(uint8_t outbuf[IMU_OUTBUF_LEN], 32);
+
+#ifdef RW610
+SDK_ALIGN(uint8_t inbuf[2 * DATA_BUFFER_SIZE], 32);
+#else
+/*! @brief Data read from the card */
+SDK_ALIGN(uint8_t inbuf[SDIO_MP_AGGR_DEF_PKT_LIMIT * 2 * DATA_BUFFER_SIZE], 32);
+#endif
+#if CONFIG_AMSDU_IN_AMPDU
+SDK_ALIGN(uint8_t amsdu_outbuf[MAX_SUPPORT_AMSDU_SIZE], 32);
+#endif
+
+hal_imumc_status_t imumc_cmdrsp_handler(IMU_Msg_t *pImuMsg, uint32_t length);
+hal_imumc_status_t imumc_event_handler(IMU_Msg_t *pImuMsg, uint32_t length);
+hal_imumc_status_t imumc_rxpkt_handler(IMU_Msg_t *pImuMsg, uint32_t length);
+hal_imumc_status_t imumc_ctrl_handler(IMU_Msg_t *pImuMsg, uint32_t length);
+
+/* Remove me: This structure is not present in mlan and can be removed later */
+typedef MLAN_PACK_START struct
+{
+    t_u16 size;
+    t_u16 pkttype;
+    HostCmd_DS_COMMAND hostcmd;
+} MLAN_PACK_END IMUPkt;
+
+IMUPkt *imupkt = (IMUPkt *)outbuf;
+
+#if CONFIG_PALLADIUM_SUPPORT
+#define WIFI_POLL_CMD_RESP_TIME 1
+#else
+#define WIFI_POLL_CMD_RESP_TIME 10
+#endif
+#if CONFIG_TX_RX_ZERO_COPY
+extern void net_tx_zerocopy_process_cb(void *destAddr, void *srcAddr, uint32_t len);
+#endif
+void wrapper_wlan_cmd_11n_cfg(void *hostcmd);
+void wrapper_wifi_ret_mib(void *resp);
+uint32_t dev_value1 = -1;
+uint8_t dev_mac_addr[MLAN_MAC_ADDR_LENGTH];
+uint8_t dev_mac_addr_uap[MLAN_MAC_ADDR_LENGTH];
+static uint8_t dev_fw_ver_ext[MLAN_MAX_VER_STR_LEN];
+
+static void wifi_init_imulink(void)
+{
+    /* Assign IMU channel for CPU1-CPU3 communication */
+    HAL_ImuInit(kIMU_LinkCpu1Cpu3);
+}
+
+uint8_t cmd_seqno = 0;
+static hal_imumc_status_t wifi_send_fw_cmd(t_u16 cmd_type, t_u8 *cmd_payload, t_u32 length)
+{
+    IMUPkt *imu_cmd         = (IMUPkt *)cmd_payload;
+    HostCmd_DS_COMMAND *cmd = NULL;
+
+    if (cmd_payload == NULL || length == 0)
+        return kStatus_HAL_ImumcError;
+
+    cmd          = &(imu_cmd->hostcmd);
+    cmd->seq_num = (cmd->seq_num & 0xFF00) | cmd_seqno;
+    cmd_seqno++;
+
+#if (CONFIG_ENABLE_WARNING_LOGS) || (CONFIG_WIFI_CMD_RESP_DEBUG)
+    wcmdr_d("DNLD_CMD: 0x%x, act 0x%x, len %d, seqno 0x%x", cmd->command, *(t_u16 *)((t_u8 *)cmd + S_DS_GEN), cmd->size,
+            cmd->seq_num);
+#endif /* CONFIG_ENABLE_WARNING_LOGS || CONFIG_WIFI_CMD_RESP_DEBUG*/
+
+#if CONFIG_WIFI_IO_DUMP
+    (void)PRINTF("OUT_CMD");
+    dump_hex(cmd_payload, length);
+#endif /* CONFIG_WIFI_IO_DUMP */
+
+    while (kStatus_HAL_ImumcSuccess != HAL_ImuSendCommand(kIMU_LinkCpu1Cpu3, cmd_payload, length))
+    {
+        OSA_TimeDelay(1);
+    }
+    return kStatus_HAL_ImumcSuccess;
+}
+
+static hal_imumc_status_t wifi_send_fw_data(t_u8 *data, t_u32 length)
+{
+    if (data == NULL || length == 0)
+        return kStatus_HAL_ImumcError;
+    w_pkt_d("Data TX SIG: Driver=>FW, len %d", length);
+    return HAL_ImuSendTxData(kIMU_LinkCpu1Cpu3, data, length);
+}
+
+int wifi_imu_lock()
+{
+    return OSA_MutexLock((osa_mutex_handle_t)txrx_mutex, osaWaitForever_c);
+}
+
+void wifi_imu_unlock()
+{
+    (void)OSA_MutexUnlock((osa_mutex_handle_t)txrx_mutex);
+}
+
+uint32_t wifi_get_device_value1()
+{
+    return dev_value1;
+}
+
+int wifi_get_device_mac_addr(wifi_mac_addr_t *mac_addr)
+{
+    (void)memcpy(mac_addr->mac, dev_mac_addr, MLAN_MAC_ADDR_LENGTH);
+    return WM_SUCCESS;
+}
+
+int wifi_get_device_uap_mac_addr(wifi_mac_addr_t *mac_addr_uap)
+{
+    (void)memcpy(mac_addr_uap->mac, dev_mac_addr_uap, MLAN_MAC_ADDR_LENGTH);
+    return WM_SUCCESS;
+}
+
+int wifi_get_device_firmware_version_ext(wifi_fw_version_ext_t *fw_ver_ext)
+{
+    (void)memcpy(fw_ver_ext->version_str, dev_fw_ver_ext, MLAN_MAX_VER_STR_LEN);
+    return WM_SUCCESS;
+}
+
+/* Initializes the driver struct */
+static int wlan_init_struct()
+{
+    osa_status_t status;
+
+    status = OSA_MutexCreate((osa_mutex_handle_t)txrx_mutex);
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return imu_create_task_lock();
+}
+
+static int wlan_deinit_struct()
+{
+    osa_status_t status;
+
+    status = OSA_MutexDestroy((osa_mutex_handle_t)txrx_mutex);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_io_e("%s mutex deletion error %d", __FUNCTION__, status);
+        return -WM_FAIL;
+    }
+
+    imu_delete_task_lock();
+
+    (void)memset(dev_mac_addr, 0, sizeof(dev_mac_addr));
+    (void)memset(dev_fw_ver_ext, 0, sizeof(dev_fw_ver_ext));
+
+    return WM_SUCCESS;
+}
+
+int raw_process_pkt_hdrs(void *pbuf, t_u32 payloadlen, t_u8 interface)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    IMUPkt *imuhdr       = (IMUPkt *)pbuf;
+    TxPD *ptxpd          = (TxPD *)((uint8_t *)pbuf + INTF_HEADER_LEN);
+
+    ptxpd->bss_type      = interface;
+    ptxpd->bss_num       = GET_BSS_NUM(pmpriv);
+    ptxpd->tx_pkt_offset = 0x14; /* we'll just make this constant */
+    ptxpd->tx_pkt_length = payloadlen - ptxpd->tx_pkt_offset - INTF_HEADER_LEN;
+    ptxpd->tx_pkt_type   = 0xE5;
+    ptxpd->tx_control    = 0;
+    ptxpd->priority      = 0;
+    ptxpd->flags         = 0;
+    ptxpd->pkt_delay_2ms = 0;
+    /* set tx_token_id to 1 to get tx_status_event from FW */
+    ptxpd->tx_token_id = 1;
+
+    imuhdr->size = payloadlen + ptxpd->tx_pkt_offset + INTF_HEADER_LEN;
+
+    return ptxpd->tx_pkt_offset + INTF_HEADER_LEN;
+}
+
+/*
+ * fixme: mlan_sta_tx.c can be used directly here. This functionality is
+ * already present there.
+ */
+/* SDIO  TxPD  PAYLOAD | 4 | 22 | payload | */
+
+/* we return the offset of the payload from the beginning of the buffer */
+void process_pkt_hdrs(void *pbuf, t_u32 payloadlen, t_u8 interface, t_u8 tid, t_u32 tx_control)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    IMUPkt *imuhdr       = (IMUPkt *)pbuf;
+    TxPD *ptxpd          = (TxPD *)((uint8_t *)pbuf + INTF_HEADER_LEN);
+
+    ptxpd->bss_type      = interface;
+    ptxpd->bss_num       = GET_BSS_NUM(pmpriv);
+    ptxpd->tx_pkt_offset = 0x16; /* we'll just make this constant */
+    ptxpd->tx_pkt_length = payloadlen - ptxpd->tx_pkt_offset - INTF_HEADER_LEN;
+    if (ptxpd->tx_pkt_type == 0xe5)
+    {
+        ptxpd->tx_pkt_offset = 0x14; /* Override for special frame */
+        ptxpd->tx_pkt_length = payloadlen - ptxpd->tx_pkt_offset - INTF_HEADER_LEN;
+    }
+    ptxpd->tx_control    = tx_control;
+    ptxpd->priority      = tid;
+    ptxpd->flags         = 0;
+    ptxpd->pkt_delay_2ms = 0;
+
+    imuhdr->size = payloadlen;
+}
+
+#if CONFIG_AMSDU_IN_AMPDU
+#if defined(RW610)
+int process_amsdu_pkt_hdrs(void *pbuf, t_u32 payloadlen, mlan_wmm_ac_e ac, t_u8 interface)
+#else
+int process_amsdu_pkt_hdrs(void *pbuf, t_u32 payloadlen, mlan_wmm_ac_e ac)
+#endif
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+    IMUPkt *imuhdr       = (IMUPkt *)pbuf;
+    TxPD *ptxpd          = (TxPD *)((uint8_t *)pbuf + INTF_HEADER_LEN);
+
+#if defined(RW610)
+    ptxpd->bss_type = interface;
+#else
+    TxPD *ptxpd_orig = (TxPD *)((uint8_t *)wifi_get_wmm_send_outbuf(ac, 0) + INTF_HEADER_LEN);
+    ptxpd->bss_type  = ptxpd_orig->bss_type;
+#endif
+    ptxpd->bss_num       = GET_BSS_NUM(pmpriv);
+    ptxpd->tx_pkt_offset = 0x16; /* we'll just make this constant */
+    ptxpd->tx_pkt_length = payloadlen - ptxpd->tx_pkt_offset - INTF_HEADER_LEN;
+    ptxpd->tx_pkt_type   = PKT_TYPE_AMSDU;
+    ptxpd->tx_control    = 0;
+    ptxpd->priority      = 0;
+    ptxpd->flags         = 0;
+    ptxpd->pkt_delay_2ms = 0;
+
+    imuhdr->size = payloadlen;
+
+    return ptxpd->tx_pkt_offset + INTF_HEADER_LEN;
+}
+#endif
+
+void process_pkt_hdrs_flags(void *pbuf, t_u8 flags)
+{
+    TxPD *ptxpd  = (TxPD *)((uint8_t *)pbuf + INTF_HEADER_LEN);
+    ptxpd->flags = flags;
+}
+
+int bus_register_event_queue(osa_msgq_handle_t event_queue)
+{
+    if (bus.event_queue != NULL)
+        return -WM_FAIL;
+
+    bus.event_queue = event_queue;
+
+    return WM_SUCCESS;
+}
+
+void bus_deregister_event_queue()
+{
+    if (bus.event_queue != NULL)
+        bus.event_queue = NULL;
+}
+
+int bus_register_data_input_function(int (*wifi_low_level_input)(const uint8_t interface,
+                                                                 const uint8_t *buffer,
+                                                                 const uint16_t len))
+{
+    if (bus.wifi_low_level_input != NULL)
+        return -WM_FAIL;
+
+    bus.wifi_low_level_input = wifi_low_level_input;
+
+    return WM_SUCCESS;
+}
+
+void bus_deregister_data_input_funtion(void)
+{
+    bus.wifi_low_level_input = NULL;
+}
+
+void wifi_get_mac_address_from_cmdresp(void *resp, t_u8 *mac_addr);
+void wifi_get_firmware_ver_ext_from_cmdresp(void *resp, t_u8 *fw_ver_ext);
+void wifi_get_value1_from_cmdresp(void *resp, uint32_t *dev_value1);
+
+#if CONFIG_FW_VDLLV2
+static mlan_status wlan_handle_vdllv2_event_packet(t_u8 *pmbuf)
+{
+    mlan_status status = MLAN_STATUS_SUCCESS;
+    pmlan_event_vdll_indication pevent_vdll_ind;
+
+    pevent_vdll_ind = (pmlan_event_vdll_indication)(pmbuf);
+    switch (wlan_le16_to_cpu(pevent_vdll_ind->vdllInd.type))
+    {
+        case VDLL_IND_TYPE_REQ:
+            wevt_d("VDLL_IND (VDLL REQ).");
+            (void)sb3_fw_download(LOAD_WIFI_VDLL_FIRMWARE, 1, pevent_vdll_ind->vdllInd.offset);
+            break;
+        case VDLL_IND_TYPE_INTF_RESET:
+            wevt_d("VDLLV2_IND (INTF RESET).");
+            HAL_ImuResetWlanTxq(kIMU_LinkCpu1Cpu3);
+            break;
+        default:
+            PRINTF("receive vdll event type=%d, Unhandled!\r\n", pevent_vdll_ind->vdllInd.type);
+            break;
+    }
+    return status;
+}
+#endif
+
+mlan_status wlan_handle_cmd_resp_packet(t_u8 *pmbuf)
+{
+    HostCmd_DS_GEN *cmdresp;
+    t_u32 cmdtype;
+    t_u32 cmdsize;
+    int bss_type;
+
+    cmdresp = (HostCmd_DS_GEN *)(pmbuf + INTF_HEADER_LEN); /* size + pkttype=4 */
+    cmdtype = cmdresp->command & HostCmd_CMD_ID_MASK;
+    cmdsize = cmdresp->size;
+#if CONFIG_IMU_GDMA
+    HAL_ImuGdmaCopyData(inbuf, cmdresp, cmdsize);
+#else
+    memcpy(inbuf, cmdresp, cmdsize);
+#endif
+    cmdresp  = (HostCmd_DS_GEN *)inbuf;
+    bss_type = HostCmd_GET_BSS_TYPE(cmdresp->seq_num);
+
+    last_resp_rcvd = cmdtype;
+
+    if ((cmdresp->command & 0xf000) != 0x8000)
+    {
+        wifi_io_d("cmdresp->command = (0x%x)", cmdresp->command);
+    }
+
+    /* Do not process response of wlan firmware shutdown command
+     *
+     * This is required to flush out any previous response
+     * from the wlan_deinit() which might have been called
+     * prior to this.
+     *
+     */
+    if ((cmdresp->command & 0x00ff) == HostCmd_CMD_FUNC_SHUTDOWN)
+        return MLAN_STATUS_SUCCESS;
+
+    if ((cmdresp->command & 0x0fff) != last_cmd_sent)
+    {
+        wifi_io_d("cmdresp->command = (0x%x) last_cmd_sent = (0x%x)", cmdresp->command, last_cmd_sent);
+    }
+
+    if (cmdresp->result != 0U)
+    {
+        wifi_io_d("cmdresp->result = (0x%x)", cmdresp->result);
+    }
+
+    wifi_io_d("Resp : (0x%x)", cmdtype);
+    switch (cmdtype)
+    {
+        case HostCmd_CMD_MAC_CONTROL:
+        case HostCmd_CMD_FUNC_INIT:
+        case HostCmd_CMD_CFG_DATA:
+            break;
+        case HostCmd_CMD_MAC_REG_ACCESS:
+            wifi_get_value1_from_cmdresp(cmdresp, &dev_value1);
+            break;
+        case HostCmd_CMD_802_11_MAC_ADDRESS:
+            if (bss_type == MLAN_BSS_TYPE_UAP)
+            {
+                wifi_get_mac_address_from_cmdresp(cmdresp, dev_mac_addr_uap);
+            }
+            else
+            {
+                wifi_get_mac_address_from_cmdresp(cmdresp, dev_mac_addr);
+            }
+            break;
+#ifdef OTP_CHANINFO
+        case HostCmd_CMD_CHAN_REGION_CFG:
+            wlan_ret_chan_region_cfg((mlan_private *)mlan_adap->priv[0], (HostCmd_DS_COMMAND *)cmdresp, NULL);
+            break;
+#endif
+        case HostCmd_CMD_GET_HW_SPEC:
+            wlan_ret_get_hw_spec((mlan_private *)mlan_adap->priv[0], (HostCmd_DS_COMMAND *)cmdresp, NULL);
+#ifdef RW610
+            t_u32 fw_cap_ext_rw610;
+            fw_cap_ext_rw610 = mlan_adap->priv[0]->adapter->fw_cap_ext;
+#if !CONFIG_CUSTOM_CALDATA
+            cal_data_valid_rw610 = (((fw_cap_ext_rw610 & 0x0800) == 0) ? 0 : 1);
+#else
+            cal_data_valid_rw610 = 0;
+#endif
+#endif
+            break;
+        case HostCmd_CMD_VERSION_EXT:
+            wifi_get_firmware_ver_ext_from_cmdresp(cmdresp, dev_fw_ver_ext);
+            break;
+        case HostCmd_CMD_11N_CFG:
+            break;
+#if CONFIG_AMSDU_IN_AMPDU
+        case HostCmd_CMD_AMSDU_AGGR_CTRL:
+            wlan_ret_amsdu_aggr_ctrl((mlan_private *)mlan_adap->priv[0], (HostCmd_DS_COMMAND *)cmdresp, NULL);
+            break;
+#endif
+        case HostCmd_CMD_FUNC_SHUTDOWN:
+            break;
+#ifdef WLAN_LOW_POWER_ENABLE
+        case HostCmd_CMD_LOW_POWER_MODE:
+            break;
+#endif
+        case HostCmd_CMD_ED_MAC_MODE:
+        case HostCmd_CMD_CHANNEL_TRPC_CONFIG:
+            break;
+#if CONFIG_WIFI_TX_BUFF
+        case HostCmd_CMD_RECONFIGURE_TX_BUFF:
+            mlan_adap->tx_buffer_size = ((HostCmd_DS_COMMAND *)cmdresp)->params.tx_buf.buff_size;
+            break;
+#endif
+        default:
+            wifi_io_d("Unimplemented Resp : (0x%x)", cmdtype);
+            break;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/*
+ * Accepts event and command packets. Redirects them to queues if
+ * registered. If queues are not registered (as is the case during
+ * initialization then the packet is given to lower layer cmd/event
+ * handling part.
+ */
+static mlan_status wlan_decode_rx_packet(t_u8 *pmbuf, t_u32 upld_type)
+{
+    IMUPkt *imupkt    = (IMUPkt *)pmbuf;
+    t_u32 event_cause = 0;
+    int status;
+    struct bus_message msg;
+#if CONFIG_FW_VDLLV2
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+#endif
+
+    if (upld_type == MLAN_TYPE_DATA)
+        return MLAN_STATUS_FAILURE;
+    if (upld_type == MLAN_TYPE_CMD)
+    {
+        wifi_io_d("  --- Rx: Cmd Response ---");
+        wcmdr_d("CMD_RESP: 0x%x, result %d, len %d, seqno 0x%x", imupkt->hostcmd.command, imupkt->hostcmd.result,
+                imupkt->hostcmd.size, imupkt->hostcmd.seq_num);
+
+        if (mlan_adap->cmd_sent != 0U)
+        {
+            mlan_adap->cmd_sent = MFALSE;
+        }
+        PRINTM(MINFO, "cmd_sent=%d\n", mlan_adap->cmd_sent);
+    }
+    else
+    {
+        event_cause = *((t_u32 *)(pmbuf + INTF_HEADER_LEN));
+        wifi_io_d(" --- Rx: EVENT Response ---");
+        if (event_cause != EVENT_PS_SLEEP && event_cause != EVENT_PS_AWAKE)
+            wevt_d("Event: 0x%x", event_cause);
+    }
+
+#if CONFIG_WIFI_IO_DUMP
+    (void)PRINTF("Resp");
+    dump_hex(pmbuf, imupkt->size);
+#endif
+
+#if CONFIG_FW_VDLLV2
+    if (upld_type == MLAN_TYPE_EVENT && (wlan_le16_to_cpu(imupkt->hostcmd.command) == EVENT_VDLL_IND))
+    {
+        if (mlan_adap->ps_state == PS_STATE_SLEEP)
+        {
+            OSA_RWLockWriteUnlock(&sleep_rwlock);
+            pmpriv->adapter->ps_state = PS_STATE_AWAKE;
+        }
+        return wlan_handle_vdllv2_event_packet(pmbuf + INTF_HEADER_LEN);
+    }
+#endif
+    if (bus.event_queue != NULL)
+    {
+        if (upld_type == MLAN_TYPE_CMD)
+            msg.data = wifi_mem_malloc_cmdrespbuf();
+        else
+            msg.data = wifi_malloc_eventbuf(imupkt->size);
+
+        if (!msg.data)
+        {
+            wifi_io_e("[fail] Buffer alloc: T: %d S: %d", upld_type, imupkt->size);
+            return MLAN_STATUS_FAILURE;
+        }
+
+        msg.event = upld_type;
+#if CONFIG_IMU_GDMA
+        HAL_ImuGdmaCopyData(msg.data, pmbuf, imupkt->size);
+#else
+        memcpy(msg.data, pmbuf, imupkt->size);
+#endif
+
+        status = OSA_MsgQPut(bus.event_queue, &msg);
+
+        if (status != KOSA_StatusSuccess)
+        {
+            wifi_io_e("Failed to send response on Queue: upld_type=%d id=0x%x", upld_type,
+                      (upld_type == MLAN_TYPE_CMD) ? imupkt->hostcmd.command : event_cause);
+            if (upld_type != MLAN_TYPE_CMD)
+                wifi_free_eventbuf(msg.data);
+            return MLAN_STATUS_FAILURE;
+        }
+    }
+    else
+    {
+        /* No queues registered yet. Use local handling */
+        wlan_handle_cmd_resp_packet(pmbuf);
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+static inline t_u32 wlan_get_next_seq_num()
+{
+    return 0;
+}
+
+void wifi_prepare_set_cal_data_cmd(void *cmd, int seq_number);
+static int _wlan_set_cal_data()
+{
+    (void)memset(outbuf, 0, IMU_OUTBUF_LEN);
+
+    /* imupkt = outbuf */
+    wifi_prepare_set_cal_data_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_CFG_DATA;
+
+    /* send CMD53 to write the command to get mac address */
+    wifi_send_fw_cmd(HostCmd_CMD_CFG_DATA, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+
+void wifi_prepare_get_mac_addr_cmd(void *cmd, int seq_number);
+void wifi_prepare_get_channel_region_cfg_cmd(HostCmd_DS_COMMAND *cmd, int seq_number);
+void wifi_prepare_get_hw_spec_cmd(HostCmd_DS_COMMAND *cmd, int seq_number);
+
+#ifdef OTP_CHANINFO
+static int wlan_get_channel_region_cfg()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+    /* imupkt = outbuf */
+    wifi_prepare_get_channel_region_cfg_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_CHAN_REGION_CFG;
+    wifi_send_fw_cmd(HostCmd_CMD_CHAN_REGION_CFG, (uint8_t *)outbuf, imupkt->size);
+
+    return true;
+}
+#endif
+
+static int wlan_get_hw_spec()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+    /* imupkt = outbuf */
+    wifi_prepare_get_hw_spec_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_GET_HW_SPEC;
+
+    wifi_send_fw_cmd(HostCmd_CMD_GET_HW_SPEC, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+
+static int wlan_get_mac_addr_sta()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wifi_prepare_get_mac_addr_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_802_11_MAC_ADDRESS;
+
+    /* send CMD53 to write the command to get mac address */
+    wifi_send_fw_cmd(HostCmd_CMD_802_11_MAC_ADDRESS, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+
+static int wlan_get_mac_addr_uap()
+{
+    int seq_number = 0;
+
+    seq_number = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, MLAN_BSS_TYPE_UAP);
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wifi_prepare_get_mac_addr_cmd(&imupkt->hostcmd, seq_number);
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_802_11_MAC_ADDRESS;
+
+    /* send CMD53 to write the command to get mac address */
+    wifi_send_fw_cmd(HostCmd_CMD_802_11_MAC_ADDRESS, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+
+void wifi_prepare_get_fw_ver_ext_cmd(void *cmd, int seq_number, int version_str_sel);
+static int wlan_get_fw_ver_ext(int version_str_sel)
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wifi_prepare_get_fw_ver_ext_cmd(&imupkt->hostcmd, wlan_get_next_seq_num(), version_str_sel);
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_VERSION_EXT;
+
+    /* send CMD53 to write the command to get mac address */
+    wifi_send_fw_cmd(HostCmd_CMD_VERSION_EXT, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+
+void wifi_prepare_get_value1(void *cmd, int seq_number);
+
+static int wlan_get_value1()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wifi_prepare_get_value1(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_MAC_REG_ACCESS;
+    wifi_send_fw_cmd(HostCmd_CMD_MAC_REG_ACCESS, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+
+void wifi_prepare_set_mac_addr_cmd(void *cmd, int seq_number);
+static int _wlan_set_mac_addr()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wifi_prepare_set_mac_addr_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_802_11_MAC_ADDRESS;
+
+    /* send CMD53 to write the command to get mac address */
+    wifi_send_fw_cmd(HostCmd_CMD_802_11_MAC_ADDRESS, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+
+static int wlan_set_11n_cfg()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+    wrapper_wlan_cmd_11n_cfg(&imupkt->hostcmd);
+    /* imupkt = outbuf */
+    imupkt->hostcmd.seq_num = wlan_get_next_seq_num();
+    imupkt->pkttype         = MLAN_TYPE_CMD;
+    imupkt->size            = imupkt->hostcmd.size + INTF_HEADER_LEN;
+    last_cmd_sent           = HostCmd_CMD_11N_CFG;
+    wifi_send_fw_cmd(HostCmd_CMD_11N_CFG, (uint8_t *)outbuf, imupkt->size);
+
+    return true;
+}
+
+#if CONFIG_WIFI_TX_BUFF
+int _wlan_return_all_tx_buf(imu_link_t link)
+{
+    HAL_ImuReturnAllTxBuf(link);
+
+    return true;
+}
+
+void wifi_prepare_set_tx_buf_size(void *cmd, int seq_number);
+static int _wlan_recfg_tx_buf_size(uint16_t buf_size)
+{
+    wifi_calibrate_tx_buf_size(buf_size);
+
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wifi_prepare_set_tx_buf_size(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_RECONFIGURE_TX_BUFF;
+
+    wifi_send_fw_cmd(HostCmd_CMD_RECONFIGURE_TX_BUFF, (uint8_t *)outbuf, imupkt->size);
+
+    return true;
+}
+#endif
+
+#if CONFIG_AMSDU_IN_AMPDU
+void wifi_prepare_enable_amsdu_cmd(void *cmd, int seq_number);
+static int wlan_enable_amsdu()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wifi_prepare_enable_amsdu_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_AMSDU_AGGR_CTRL;
+
+    wifi_send_fw_cmd(HostCmd_CMD_AMSDU_AGGR_CTRL, (uint8_t *)outbuf, imupkt->size);
+
+    return true;
+}
+#endif
+/* This function was only used in imu_wifi_deinit, and now is replaced by wifi_send_shutdown_cmd with the same 0xaa cmd
+ */
+#if 0
+static int wlan_cmd_shutdown()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    imupkt->hostcmd.command = HostCmd_CMD_FUNC_SHUTDOWN;
+    imupkt->hostcmd.size    = S_DS_GEN;
+    imupkt->hostcmd.seq_num = wlan_get_next_seq_num();
+    imupkt->hostcmd.result  = 0;
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_FUNC_SHUTDOWN;
+
+    wifi_send_fw_cmd(HostCmd_CMD_FUNC_SHUTDOWN, (uint8_t *)outbuf, imupkt->size);
+
+    return true;
+}
+#endif
+
+void wlan_prepare_mac_control_cmd(void *cmd, int seq_number);
+static int wlan_set_mac_ctrl()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    wlan_prepare_mac_control_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_MAC_CONTROL;
+
+    wifi_send_fw_cmd(HostCmd_CMD_MAC_CONTROL, (uint8_t *)outbuf, imupkt->size);
+
+    return true;
+}
+
+static int wlan_cmd_init()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+    imupkt->hostcmd.command = HostCmd_CMD_FUNC_INIT;
+    imupkt->hostcmd.size    = S_DS_GEN;
+    imupkt->hostcmd.seq_num = wlan_get_next_seq_num();
+    imupkt->hostcmd.result  = 0;
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_FUNC_INIT;
+
+    wifi_send_fw_cmd(HostCmd_CMD_FUNC_INIT, (uint8_t *)outbuf, imupkt->size);
+
+    return true;
+}
+
+#ifdef WLAN_LOW_POWER_ENABLE
+void wifi_prepare_low_power_mode_cmd(HostCmd_DS_COMMAND *cmd, int seq_number);
+static int wlan_set_low_power_mode()
+{
+    (void)memset(outbuf, 0, IMU_INIT_FW_CMD_SIZE);
+
+    /* imupkt = outbuf */
+
+    wifi_prepare_low_power_mode_cmd(&imupkt->hostcmd, wlan_get_next_seq_num());
+
+    imupkt->pkttype = MLAN_TYPE_CMD;
+    imupkt->size    = imupkt->hostcmd.size + INTF_HEADER_LEN;
+
+    last_cmd_sent = HostCmd_CMD_LOW_POWER_MODE;
+
+    wifi_send_fw_cmd(HostCmd_CMD_LOW_POWER_MODE, (uint8_t *)outbuf, imupkt->size);
+    return true;
+}
+#endif
+
+static int wlan_wait_for_last_resp_rcvd(t_u16 command)
+{
+    int retry_cnt = WIFI_COMMAND_RESPONSE_WAIT_MS / WIFI_POLL_CMD_RESP_TIME;
+
+    while ((last_resp_rcvd != command) && (retry_cnt > 0))
+    {
+        OSA_TimeDelay(WIFI_POLL_CMD_RESP_TIME);
+        retry_cnt--;
+    }
+
+    if (last_resp_rcvd == command)
+    {
+        return true;
+    }
+    else
+    {
+        wifi_io_e("%s: wait cmd 0x%x fail (last 0x%x)", __FUNCTION__, command, last_resp_rcvd);
+        return false;
+    }
+}
+
+// mlan_status wlan_process_int_status(mlan_adapter *pmadapter);
+/* Setup the firmware with commands */
+static int wlan_fw_init_cfg()
+{
+    wcmdr_d("FWCMD : INIT (0xa9)");
+
+    /* Add while loop here to wait until command buffer has been attached */
+    while (HAL_ImuLinkIsUp(kIMU_LinkCpu1Cpu3) != 0)
+    {
+        OSA_TimeDelay(WIFI_POLL_CMD_RESP_TIME);
+    }
+
+    wlan_cmd_init();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_FUNC_INIT) != true)
+    {
+        return false;
+    }
+
+#ifdef WLAN_LOW_POWER_ENABLE
+    if (low_power_mode)
+    {
+        wcmdr_d("CMD : LOW_POWER_MODE (0x128)");
+
+        wlan_set_low_power_mode();
+
+        if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_LOW_POWER_MODE) != true)
+        {
+            return false;
+        }
+    }
+#endif
+
+    if (mac_addr_valid)
+    {
+        wcmdr_d("CMD : SET_MAC_ADDR (0x4d)");
+
+        _wlan_set_mac_addr();
+
+        if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_802_11_MAC_ADDRESS) != true)
+        {
+            return false;
+        }
+    }
+
+#ifdef OTP_CHANINFO
+    wcmdr_d("CMD : Channel Region CFG (0x0242)");
+
+    wlan_get_channel_region_cfg();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_CHAN_REGION_CFG) != true)
+    {
+        return false;
+    }
+#endif
+
+    wcmdr_d("CMD : GET_HW_SPEC (0x03)");
+
+    wlan_get_hw_spec();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_GET_HW_SPEC) != true)
+    {
+        return false;
+    }
+    if (cal_data_valid
+#ifdef RW610
+        && !cal_data_valid_rw610
+#endif
+    )
+    {
+        wcmdr_d("CMD : SET_CAL_DATA (0x8f)");
+
+        _wlan_set_cal_data();
+
+        if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_CFG_DATA) != true)
+        {
+            return false;
+        }
+    }
+
+#if CONFIG_WIFI_TX_BUFF
+    // TODO:Reconfig tx buffer size to 4K
+    wcmdr_d("CMD : RECONFIGURE_TX_BUFF (0xd9)");
+
+    _wlan_recfg_tx_buf_size(tx_buf_size);
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_RECONFIGURE_TX_BUFF) != true)
+    {
+        return false;
+    }
+#endif
+
+    wcmdr_d("CMD : MAC_REG_ACCESS (0x19)");
+
+    wlan_get_value1();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_MAC_REG_ACCESS) != true)
+    {
+        return false;
+    }
+
+    wcmdr_d("CMD : GET_FW_VER_EXT (0x97)");
+
+    wlan_get_fw_ver_ext(0);
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_VERSION_EXT) != true)
+    {
+        return false;
+    }
+
+    wcmdr_d("CMD : GET_MAC_ADDR (0x4d)");
+
+    wlan_get_mac_addr_sta();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_802_11_MAC_ADDRESS) != true)
+    {
+        return false;
+    }
+
+    last_resp_rcvd = 0;
+
+    wlan_get_mac_addr_uap();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_802_11_MAC_ADDRESS) != true)
+    {
+        return false;
+    }
+
+    wcmdr_d("CMD : GET_FW_VER_EXT (0x97)");
+
+    wlan_get_fw_ver_ext(3);
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_VERSION_EXT) != true)
+    {
+        return false;
+    }
+
+    wcmdr_d("CMD : MAC_CTRL (0x28)");
+
+    wlan_set_mac_ctrl();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_MAC_CONTROL) != true)
+    {
+        return false;
+    }
+
+    wcmdr_d("CMD : GET_FW_VER_EXT (0x97)");
+
+    wlan_get_fw_ver_ext(4);
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_VERSION_EXT) != true)
+    {
+        return false;
+    }
+
+    wcmdr_d("CMD : 11N_CFG (0xcd)");
+    wlan_set_11n_cfg();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_11N_CFG) != true)
+    {
+        return false;
+    }
+
+#if CONFIG_AMSDU_IN_AMPDU
+    wcmdr_d("CMD : AMSDU_AGGR_CTRL (0xdf)");
+    wlan_enable_amsdu();
+
+    if (wlan_wait_for_last_resp_rcvd(HostCmd_CMD_AMSDU_AGGR_CTRL) != true)
+    {
+        return false;
+    }
+#endif
+
+    return true;
+}
+
+int wlan_send_imu_cmd(t_u8 *buf)
+{
+    IMUPkt *imu_cmd = (IMUPkt *)outbuf;
+
+    wifi_imu_lock();
+
+    (void)memcpy(outbuf, buf, MIN(WIFI_FW_CMDBUF_SIZE, IMU_OUTBUF_LEN));
+    imu_cmd->pkttype = MLAN_TYPE_CMD;
+    imu_cmd->size    = imu_cmd->hostcmd.size + INTF_HEADER_LEN;
+    wifi_send_fw_cmd(imu_cmd->hostcmd.command, (uint8_t *)outbuf, imu_cmd->size);
+
+    last_cmd_sent = imu_cmd->hostcmd.command;
+    wifi_imu_unlock();
+
+    return WM_SUCCESS;
+}
+
+int wifi_send_cmdbuffer(void)
+{
+    return wlan_send_imu_cmd(cmd_buf);
+}
+
+uint8_t *wifi_get_imu_outbuf(uint32_t *outbuf_len)
+{
+    *outbuf_len = sizeof(outbuf);
+    return outbuf;
+}
+#if CONFIG_AMSDU_IN_AMPDU
+uint8_t *wifi_get_amsdu_outbuf(uint32_t offset)
+{
+    return (amsdu_outbuf + offset);
+}
+#endif
+t_u16 get_mp_end_port(void);
+mlan_status wlan_xmit_pkt(t_u8 *buffer, t_u32 txlen, t_u8 interface, t_u32 tx_control)
+{
+    int ret;
+
+    wifi_io_info_d("OUT: i/f: %d len: %d", interface, txlen);
+
+    process_pkt_hdrs((t_u8 *)buffer, txlen, interface, 0, tx_control);
+    /* send tx data via imu */
+    ret = wifi_send_fw_data(buffer, txlen);
+
+    if (ret != kStatus_HAL_ImumcSuccess)
+    {
+        wifi_io_e("Send tx data via imu failed (%d)", ret);
+#if CONFIG_WIFI_FW_DEBUG
+#if 0
+        if (wm_wifi.wifi_usb_mount_cb != NULL)
+        {
+            ret = wm_wifi.wifi_usb_mount_cb();
+            if (ret == WM_SUCCESS)
+                wifi_dump_firmware_info(NULL);
+            else
+                wifi_e("USB mounting failed");
+        }
+        else
+            wifi_e("USB mount callback is not registered");
+#endif
+        wifi_dump_firmware_info();
+#endif
+        return MLAN_STATUS_FAILURE;
+    }
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if CONFIG_WMM
+mlan_status wlan_xmit_bypass_pkt(t_u8 *buffer, t_u32 txlen, t_u8 interface)
+{
+    int ret;
+
+    wifi_io_info_d("OUT: i/f: %d len: %d", interface, txlen);
+
+    wifi_imu_lock();
+    /* send tx data via imu */
+    ret = wifi_send_fw_data(buffer, txlen);
+
+    if (ret != kStatus_HAL_ImumcSuccess)
+    {
+        wifi_io_e("Send tx data via imu failed (%d)", ret);
+#if CONFIG_WIFI_FW_DEBUG
+#if 0
+        if (wm_wifi.wifi_usb_mount_cb != NULL)
+        {
+            ret = wm_wifi.wifi_usb_mount_cb();
+            if (ret == WM_SUCCESS)
+                wifi_dump_firmware_info(NULL);
+            else
+                wifi_e("USB mounting failed");
+        }
+        else
+            wifi_e("USB mount callback is not registered");
+#endif
+        wifi_dump_firmware_info();
+#endif
+
+        wifi_imu_unlock();
+        return MLAN_STATUS_FAILURE;
+    }
+
+    wifi_imu_unlock();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+#if CONFIG_WMM
+mlan_status wlan_xmit_wmm_pkt(t_u8 interface, t_u32 txlen, t_u8 *tx_buf)
+{
+    int ret;
+#if CONFIG_WMM_UAPSD
+    bool last_packet = 0;
+#endif
+
+    wifi_io_info_d("OUT: i/f: %d len: %d", interface, txlen);
+
+    wifi_imu_lock();
+#if CONFIG_WMM_UAPSD
+    if (mlan_adap->priv[interface]->adapter->pps_uapsd_mode &&
+        wifi_check_last_packet_indication(mlan_adap->priv[interface]))
+    {
+#if CONFIG_TX_RX_ZERO_COPY
+        process_pkt_hdrs_flags(&((outbuf_t *)tx_buf)->intf_header[0], MRVDRV_TxPD_POWER_MGMT_LAST_PACKET);
+#else
+        process_pkt_hdrs_flags((t_u8 *)tx_buf, MRVDRV_TxPD_POWER_MGMT_LAST_PACKET);
+#endif
+        last_packet = 1;
+    }
+#endif
+
+#if CONFIG_TX_RX_ZERO_COPY
+    ret = HAL_ImuAddWlanTxPacketExt(kIMU_LinkCpu1Cpu3, tx_buf, txlen, net_tx_zerocopy_process_cb);
+#else
+    ret              = HAL_ImuAddWlanTxPacket(kIMU_LinkCpu1Cpu3, tx_buf, txlen);
+#endif
+
+    if (ret != kStatus_HAL_ImumcSuccess)
+    {
+#if CONFIG_WMM_UAPSD
+        if (last_packet)
+        {
+#if CONFIG_TX_RX_ZERO_COPY
+            process_pkt_hdrs_flags(&((outbuf_t *)tx_buf)->intf_header[0], 0);
+#else
+            process_pkt_hdrs_flags((t_u8 *)tx_buf, 0);
+#endif
+        }
+#endif
+
+        wifi_imu_unlock();
+        return MLAN_STATUS_FAILURE;
+    }
+
+#if CONFIG_WMM_UAPSD
+    if (last_packet)
+    {
+        mlan_adap->priv[interface]->adapter->tx_lock_flag = MTRUE;
+        OSA_SemaphoreWait((osa_semaphore_handle_t)uapsd_sem, osaWaitForever_c);
+    }
+#endif
+
+    wifi_imu_unlock();
+    return MLAN_STATUS_SUCCESS;
+}
+
+mlan_status wlan_flush_wmm_pkt(int pkt_cnt)
+{
+    int ret;
+
+    if (pkt_cnt == 0)
+        return MLAN_STATUS_SUCCESS;
+
+    w_pkt_d("Data TX: Driver=>FW, pkt_cnt %d", pkt_cnt);
+
+    ret = HAL_ImuSendMultiTxData(kIMU_LinkCpu1Cpu3);
+    ;
+    if (ret != kStatus_HAL_ImumcSuccess)
+    {
+        wifi_io_e("wlan_flush_wmm_pkt failed (%d)", ret);
+#if CONFIG_WIFI_FW_DEBUG
+#if 0
+        if (wm_wifi.wifi_usb_mount_cb != NULL)
+        {
+            ret = wm_wifi.wifi_usb_mount_cb();
+            if (ret == WM_SUCCESS)
+                wifi_dump_firmware_info(NULL);
+            else
+                wifi_e("USB mounting failed");
+        }
+        else
+            wifi_e("USB mount callback is not registered");
+#endif
+        wifi_dump_firmware_info();
+#endif
+        return MLAN_STATUS_FAILURE;
+    }
+    return MLAN_STATUS_SUCCESS;
+}
+
+#if CONFIG_AMSDU_IN_AMPDU
+/**
+ *  @brief This function checks if we need to send last amsdu indication.
+ *
+ *  @param priv    A pointer to mlan_private structure
+ *
+ *  @return        MTRUE or MFALSE
+ */
+static t_u8 wifi_check_last_amsdu_packet_indication(mlan_private *priv, t_u8 amsdu_cnt)
+{
+    if ((wifi_wmm_get_packet_cnt() == amsdu_cnt) && priv->wmm_qosinfo && priv->curr_bss_params.wmm_uapsd_enabled)
+        return TRUE;
+    else
+        return FALSE;
+}
+
+mlan_status wlan_xmit_wmm_amsdu_pkt(mlan_wmm_ac_e ac, t_u8 interface, t_u32 txlen, t_u8 *tx_buf, t_u8 amsdu_cnt)
+{
+    int ret;
+#if CONFIG_WMM_UAPSD
+    bool last_packet = 0;
+#endif
+
+    wifi_io_info_d("OUT: i/f: %d len: %d", interface, txlen);
+
+    wifi_imu_lock();
+#if defined(RW610)
+    process_amsdu_pkt_hdrs((t_u8 *)tx_buf, txlen, ac, interface);
+#if CONFIG_WMM_UAPSD
+    if (mlan_adap->priv[interface]->adapter->pps_uapsd_mode &&
+        wifi_check_last_amsdu_packet_indication(mlan_adap->priv[interface], amsdu_cnt))
+    {
+        process_pkt_hdrs_flags((t_u8 *)tx_buf, MRVDRV_TxPD_POWER_MGMT_LAST_PACKET);
+        last_packet = 1;
+    }
+#endif
+#else
+    process_amsdu_pkt_hdrs((t_u8 *)tx_buf, txlen, ac);
+#endif
+
+    ret = HAL_ImuAddWlanTxPacket(kIMU_LinkCpu1Cpu3, tx_buf, txlen);
+
+    if (ret != kStatus_HAL_ImumcSuccess)
+    {
+#if CONFIG_WMM_UAPSD
+        if (last_packet)
+            process_pkt_hdrs_flags((t_u8 *)tx_buf, 0);
+#endif
+        wifi_imu_unlock();
+        return MLAN_STATUS_FAILURE;
+    }
+
+#if CONFIG_WMM_UAPSD
+    if (last_packet)
+    {
+        mlan_adap->priv[interface]->adapter->tx_lock_flag = MTRUE;
+        OSA_SemaphoreWait((osa_semaphore_handle_t)uapsd_sem, osaWaitForever_c);
+    }
+#endif
+
+    wifi_imu_unlock();
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+#endif
+
+mlan_status wlan_send_null_packet(pmlan_private priv, t_u8 flags)
+{
+    int ret;
+    t_u8 pbuf[32] = {0};
+    TxPD *ptxpd   = (TxPD *)((uint8_t *)pbuf + INTF_HEADER_LEN);
+
+    ptxpd->bss_type      = priv->bss_type;
+    ptxpd->bss_num       = GET_BSS_NUM(priv);
+    ptxpd->tx_pkt_offset = 0x16; /* we'll just make this constant */
+    ptxpd->tx_pkt_length = 0;
+    ptxpd->tx_control    = 0;
+    ptxpd->priority      = 0;
+    ptxpd->flags         = flags;
+    ptxpd->pkt_delay_2ms = 0;
+
+    ret = wifi_send_fw_data(pbuf, sizeof(TxPD) + INTF_HEADER_LEN);
+    if (ret != kStatus_HAL_ImumcSuccess)
+    {
+        wifi_io_e("imu_drv_write failed (%d)", ret);
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+hal_imumc_status_t imumc_cmdrsp_handler(IMU_Msg_t *pImuMsg, uint32_t length)
+{
+    assert(NULL != pImuMsg);
+    assert(0 != length);
+    assert(IMU_MSG_COMMAND_RESPONSE == pImuMsg->Hdr.type);
+
+#if CONFIG_HOST_SLEEP
+    if (POWER_GetWakeupStatus(WL_MCI_WAKEUP0_IRQn))
+    {
+        wakeup_by                      = WAKEUP_BY_WLAN;
+        mlan_adap->wlan_wakeup.type    = IMU_MSG_COMMAND_RESPONSE;
+        mlan_adap->wlan_wakeup.subtype = 0;
+        mlan_adap->wlan_wakeup.id      = *(uint16_t *)((uint8_t *)pImuMsg->PayloadPtr[0] + 4);
+        POWER_ClearWakeupStatus(WL_MCI_WAKEUP0_IRQn);
+    }
+#endif
+
+    wlan_decode_rx_packet((t_u8 *)pImuMsg->PayloadPtr[0], MLAN_TYPE_CMD);
+
+    return kStatus_HAL_ImumcSuccess;
+}
+
+hal_imumc_status_t imumc_event_handler(IMU_Msg_t *pImuMsg, uint32_t length)
+{
+    assert(NULL != pImuMsg);
+    assert(0 != length);
+    assert(IMU_MSG_EVENT == pImuMsg->Hdr.type);
+
+#if CONFIG_HOST_SLEEP
+    if (POWER_GetWakeupStatus(WL_MCI_WAKEUP0_IRQn))
+    {
+        wakeup_by                      = WAKEUP_BY_WLAN;
+        mlan_adap->wlan_wakeup.type    = IMU_MSG_EVENT;
+        mlan_adap->wlan_wakeup.subtype = 0;
+        mlan_adap->wlan_wakeup.id      = *(uint16_t *)((uint8_t *)pImuMsg->PayloadPtr[0] + 4);
+        POWER_ClearWakeupStatus(WL_MCI_WAKEUP0_IRQn);
+    }
+#endif
+
+#if CONFIG_CSI
+    if (EVENT_CSI == *((t_u8 *)pImuMsg->PayloadPtr[0] + 4))
+    {
+        csi_save_data_to_local_buff((t_u8 *)pImuMsg->PayloadPtr[0] + 8);
+    }
+#endif
+
+    wlan_decode_rx_packet((t_u8 *)pImuMsg->PayloadPtr[0], MLAN_TYPE_EVENT);
+
+    return kStatus_HAL_ImumcSuccess;
+}
+
+hal_imumc_status_t imumc_rxpkt_handler(IMU_Msg_t *pImuMsg, uint32_t length)
+{
+    IMUPkt *inimupkt;
+    t_u32 size;
+    t_u8 interface;
+    t_u8 i = 0;
+
+    assert(NULL != pImuMsg);
+    assert(0 != length);
+    assert((IMU_MSG_RX_DATA == pImuMsg->Hdr.type) || (IMU_MSG_MULTI_RX_DATA == pImuMsg->Hdr.type));
+
+#if CONFIG_HOST_SLEEP
+    wakelock_get();
+    if (POWER_GetWakeupStatus(WL_MCI_WAKEUP0_IRQn))
+    {
+        wakeup_by                      = WAKEUP_BY_WLAN;
+        mlan_adap->wlan_wakeup.type    = pImuMsg->Hdr.type;
+        mlan_adap->wlan_wakeup.subtype = 0;
+        mlan_adap->wlan_wakeup.id      = 0;
+        POWER_ClearWakeupStatus(WL_MCI_WAKEUP0_IRQn);
+    }
+#endif
+
+    for (i = 0; i < pImuMsg->Hdr.length; i++)
+    {
+        inimupkt = (IMUPkt *)pImuMsg->PayloadPtr[i];
+        size     = inimupkt->size;
+        if ((size <= INTF_HEADER_LEN) || (size > sizeof(inbuf)))
+        {
+#if CONFIG_HOST_SLEEP
+            wakelock_put();
+#endif
+            wifi_io_e("pImuMsg->PayloadPtr[%u] has invalid size=%u", i, size);
+            return kStatus_HAL_ImumcError;
+        }
+
+#if !CONFIG_TX_RX_ZERO_COPY
+#if CONFIG_IMU_GDMA
+        HAL_ImuGdmaCopyData(inbuf, inimupkt, size);
+#else
+        memcpy(inbuf, inimupkt, size);
+#endif
+#endif
+        interface = *((t_u8 *)inimupkt + INTF_HEADER_LEN);
+        wifi_io_info_d("IN: i/f: %d len: %d", interface, size);
+        w_pkt_d("Data RX: FW=>Driver, if %d, len %d", interface, size);
+
+        if (bus.wifi_low_level_input != NULL)
+#if CONFIG_TX_RX_ZERO_COPY
+            bus.wifi_low_level_input(interface, (uint8_t *)inimupkt, size);
+#else
+            bus.wifi_low_level_input(interface, inbuf, size);
+#endif
+    }
+#if CONFIG_HOST_SLEEP
+    wakelock_put();
+#endif
+    /*! To be the last action of the handler*/
+    return kStatus_HAL_ImumcSuccess;
+}
+
+static bool imu_fw_is_hang(void)
+{
+    uint32_t *peer_magic_addr = (uint32_t *)0x41380000;
+
+    if ((*peer_magic_addr) == 0xDEADDEAD)
+        return true;
+    else
+        return false;
+}
+
+hal_imumc_status_t imumc_ctrl_handler(IMU_Msg_t *pImuMsg, uint32_t length)
+{
+    t_u32 imuControlType;
+
+    assert(NULL != pImuMsg);
+    assert(IMU_MSG_CONTROL == pImuMsg->Hdr.type);
+
+#if CONFIG_HOST_SLEEP
+    if (POWER_GetWakeupStatus(WL_MCI_WAKEUP0_IRQn))
+    {
+        wakeup_by                      = WAKEUP_BY_WLAN;
+        mlan_adap->wlan_wakeup.type    = IMU_MSG_CONTROL;
+        mlan_adap->wlan_wakeup.subtype = pImuMsg->Hdr.sub_type;
+        mlan_adap->wlan_wakeup.id      = 0;
+        POWER_ClearWakeupStatus(WL_MCI_WAKEUP0_IRQn);
+    }
+#endif
+
+    imuControlType = pImuMsg->Hdr.sub_type;
+    switch (imuControlType)
+    {
+        case IMU_MSG_CONTROL_TX_BUF_ADDR:
+#if CONFIG_WMM
+
+            if (mlan_adap->wait_txbuf == true)
+            {
+                OSA_SemaphorePost((osa_semaphore_handle_t)txbuf_sem);
+            }
+
+            send_wifi_driver_tx_data_event(0);
+#endif
+            break;
+        default:
+            break;
+    }
+    return kStatus_HAL_ImumcSuccess;
+}
+
+void imu_wakeup_card()
+{
+    /* Wakeup CPU1 */
+    PMU_EnableWlanWakeup(1);
+}
+
+void WL_MCI_WAKEUP_DONE0_DriverIRQHandler(void)
+{
+    IRQn_Type irq_num = WL_MCI_WAKEUP_DONE0_IRQn;
+
+    /* Mask IMU ICU interrupt */
+    DisableIRQ(irq_num);
+    /* Clear CPU1 wakeup register */
+    PMU_DisableWlanWakeup(1);
+    EnableIRQ(irq_num);
+}
+
+void mlan_init_wakeup_irq()
+{
+#ifndef __ZEPHYR__
+    /* Enable WLAN wakeup done interrupt */
+    NVIC_SetPriority(WL_MCI_WAKEUP_DONE0_IRQn, MCI_WAKEUP_DONE_PRIORITY);
+    NVIC_EnableIRQ(WL_MCI_WAKEUP_DONE0_IRQn);
+#endif
+}
+
+void mlan_deinit_wakeup_irq()
+{
+#ifndef __ZEPHYR__
+    NVIC_DisableIRQ(WL_MCI_WAKEUP_DONE0_IRQn);
+    NVIC_ClearPendingIRQ(WL_MCI_WAKEUP_DONE0_IRQn);
+#endif
+}
+
+mlan_status imu_wifi_init(enum wlan_type type, const uint8_t *fw_ram_start_addr, const size_t size)
+{
+    mlan_status mlanstatus = MLAN_STATUS_SUCCESS;
+    int ret                = 0;
+    int retry_cnt          = 3;
+    int retry_cnt_fw_init  = 3;
+#ifdef RW610
+    int temperature_val = 0;
+#endif
+
+    ret = wlan_init_struct();
+    if (ret != WM_SUCCESS)
+    {
+        wifi_io_e("Init failed. Cannot create init struct");
+        return MLAN_STATUS_FAILURE;
+    }
+
+    /* Initialize the mlan subsystem before initializing 878x driver */
+    mlan_subsys_init();
+
+retry:
+    /* Comment out this line if CPU1 image is downloaded through J-Link.
+     * This is for load service case only.
+     */
+    power_off_device(LOAD_WIFI_FIRMWARE);
+    wifi_io_d("%u IMU download WLAN FW.\n", OSA_TicksGet());
+    /* Download firmware */
+    ret = sb3_fw_download(LOAD_WIFI_FIRMWARE, 1, (uint32_t)fw_ram_start_addr);
+    /* If fw download is failed, retry downloading for 3 times. */
+    if (ret)
+    {
+        if (retry_cnt != 0)
+        {
+            retry_cnt--;
+            goto retry;
+        }
+        else
+        {
+            wifi_io_e("Download firmware failed");
+            mlanstatus = MLAN_STATUS_FAILURE;
+            return mlanstatus;
+        }
+    }
+    wifi_io_d("%u WLAN FW is active.\n", OSA_TicksGet());
+#if CONFIG_WIFI_RECOVERY
+    if (wifi_recovery_enable)
+    {
+        wifi_w("WiFi recovery mode done!");
+        wifi_recovery_enable = false;
+    }
+#endif
+    if (wifi_shutdown_enable)
+    {
+        wifi_shutdown_enable = false;
+    }
+
+#ifdef RW610
+    wifi_cau_temperature_enable();
+    temperature_val = wifi_cau_temperature_write_to_firmware();
+    PRINTF("Wi-Fi cau temperature : %d\r\n", temperature_val);
+#endif
+
+    wifi_init_imulink();
+
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, imumc_cmdrsp_handler, IMU_MSG_COMMAND_RESPONSE);
+
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, imumc_event_handler, IMU_MSG_EVENT);
+
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, imumc_rxpkt_handler, IMU_MSG_RX_DATA);
+
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, imumc_ctrl_handler, IMU_MSG_CONTROL);
+
+    /* If we're running a Manufacturing image, start the tasks.
+       If not, initialize and setup the firmware */
+    switch (type)
+    {
+        case WLAN_TYPE_NORMAL:
+            ret = wlan_fw_init_cfg();
+            if (ret != true)
+            {
+                if (retry_cnt_fw_init > 0)
+                {
+                    wifi_io_e("wlan_fw_init_cfg failed: retry %d", retry_cnt_fw_init);
+                    (void)HAL_ImuGetTaskLock();
+                    mlan_deinit_wakeup_irq();
+                    HAL_ImuDeinit(kIMU_LinkCpu1Cpu3, MBIT(1) | MBIT(0));
+                    (void)HAL_ImuPutTaskLock();
+                    retry_cnt_fw_init--;
+                    goto retry;
+                }
+                else
+                {
+                    wifi_io_e("wlan_fw_init_cfg failed: return for retry done");
+                    mlanstatus = MLAN_STATUS_FAILURE;
+                    return mlanstatus;
+                }
+            }
+            break;
+        case WLAN_TYPE_WIFI_CALIB:
+            g_txrx_flag = true;
+            break;
+        case WLAN_TYPE_FCC_CERTIFICATION:
+            g_txrx_flag = true;
+            break;
+        default:
+            wifi_io_e("Enter a valid input to sd_wifi_init");
+            return MLAN_STATUS_FAILURE;
+    }
+
+    mlan_init_wakeup_irq();
+
+    return mlanstatus;
+}
+
+void imu_wifi_deinit(void)
+{
+    uint32_t flag = 0;
+
+#ifdef WLAN_LOW_POWER_ENABLE
+    low_power_mode = false;
+#endif
+    cal_data_valid = false;
+    mac_addr_valid = false;
+#if 0
+    wlan_cmd_shutdown();
+    // sdio_drv_deinit();
+#endif
+    wlan_deinit_struct();
+
+    flag = MBIT(1) | MBIT(0);
+#if CONFIG_WIFI_RECOVERY
+    flag |= wifi_recovery_enable;
+#endif
+
+    mlan_deinit_wakeup_irq();
+    HAL_ImuDeinit(kIMU_LinkCpu1Cpu3, flag);
+
+    mlan_subsys_deinit();
+}
+
+void imu_uninstall_callback(void)
+{
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, NULL, IMU_MSG_COMMAND_RESPONSE);
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, NULL, IMU_MSG_EVENT);
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, NULL, IMU_MSG_RX_DATA);
+    HAL_ImuInstallCallback(kIMU_LinkCpu1Cpu3, NULL, IMU_MSG_CONTROL);
+}
+
+HostCmd_DS_COMMAND *wifi_get_command_buffer()
+{
+    /* First 4 bytes reserved for SDIO pkt header */
+    return (HostCmd_DS_COMMAND *)(cmd_buf + INTF_HEADER_LEN);
+}
+
+bus_operations imu_ops = {
+    .fw_is_hang      = imu_fw_is_hang,
+    .intf_header_len = INTF_HEADER_LEN,
+};
+
+int imu_create_task_lock(void)
+{
+    int ret = 0;
+
+    ret = HAL_ImuCreateTaskLock();
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("Create imu task lock failed.");
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+void imu_delete_task_lock(void)
+{
+    HAL_ImuDeleteTaskLock();
+}
+
+int imu_get_task_lock(void)
+{
+    int ret = 0;
+
+    ret = HAL_ImuGetTaskLock();
+    if (ret != WM_SUCCESS)
+    {
+        wifi_d("Get imu task lock failed.");
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int imu_put_task_lock(void)
+{
+    int ret = 0;
+
+    ret = HAL_ImuPutTaskLock();
+    if (ret != WM_SUCCESS)
+    {
+        wifi_d("Put imu task lock failed.");
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_HOST_SLEEP
+void wifi_print_wakeup_reason(t_u16 hs_wakeup_reason)
+{
+    ARG_UNUSED(hs_wakeup_reason);
+    if (mlan_adap->wlan_wakeup.type == IMU_MSG_CONTROL)
+        PRINTF("Woken up by WLAN(IMU ctrl msg subtype 0x%x)\r\n", mlan_adap->wlan_wakeup.subtype);
+    else if (mlan_adap->wlan_wakeup.type == IMU_MSG_COMMAND_RESPONSE)
+        PRINTF("Woken up by WLAN(command response 0x%x)\r\n", mlan_adap->wlan_wakeup.id);
+    else if (mlan_adap->wlan_wakeup.type == IMU_MSG_EVENT)
+        PRINTF("Woken up by WLAN(event 0x%x)\r\n", mlan_adap->wlan_wakeup.id);
+    else if (mlan_adap->wlan_wakeup.type == IMU_MSG_RX_DATA || mlan_adap->wlan_wakeup.type == IMU_MSG_MULTI_RX_DATA)
+        PRINTF("Woken up by WLAN(Rx data)\r\n");
+}
+
+void wifi_clear_wakeup_reason(void)
+{
+    if (mlan_adap != NULL)
+    {
+        memset(&mlan_adap->wlan_wakeup, 0x0, sizeof(wlan_wakeup_reason));
+    }
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-imu.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-imu.h
new file mode 100644
index 0000000000..509ea4d29d
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-imu.h
@@ -0,0 +1,141 @@
+/** @file wifi-imu.h
+ *
+ *  @brief WLAN on IMU
+ *
+ *  Copyright 2022 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __WIFI_IMU_H__
+#define __WIFI_IMU_H__
+
+#include <wifi.h>
+#include "fsl_power.h"
+
+#ifndef RW610
+#include "firmware_dnld.h"
+#endif
+
+#define wifi_io_e(...) wmlog_e("wifi_io", ##__VA_ARGS__)
+#define wifi_io_w(...) wmlog_w("wifi_io", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_IO_DEBUG
+#define wifi_io_d(...) wmlog("wifi_io", ##__VA_ARGS__)
+#else
+#define wifi_io_d(...)
+#endif /* ! CONFIG_WIFI_IO_DEBUG */
+
+#define wifi_io_info_e(...) wmlog_e("wpkt", ##__VA_ARGS__)
+#define wifi_io_info_w(...) wmlog_w("wpkt", ##__VA_ARGS__)
+
+#if CONFIG_WIFI_IO_INFO_DUMP
+#define wifi_io_info_d(...) wmlog("wpkt", ##__VA_ARGS__)
+#else
+#define wifi_io_info_d(...)
+#endif
+
+#define WLAN_MAGIC_NUM (('W' << 0) | ('L' << 8) | ('F' << 16) | ('W' << 24))
+
+#define WIFI_FW_CMDBUF_SIZE 3072U
+
+#define WIFI_RESP_WAIT_TIME 10
+
+#define WLAN_VALUE1 0x45001114
+
+/*! @brief Data block count accessed in card */
+#define DATA_BLOCK_COUNT (4U)
+/*! @brief Data buffer size. */
+#define DATA_BUFFER_SIZE (512 * DATA_BLOCK_COUNT)
+
+/** Card Control Registers : Function 1 Block size 0 */
+#define FN1_BLOCK_SIZE_0 0x110
+/** Card Control Registers : Function 1 Block size 1 */
+#define FN1_BLOCK_SIZE_1 0x111
+
+/* Duplicated in wlan.c. keep in sync till we can be included directly */
+typedef struct __nvram_backup_struct
+{
+    t_u32 ioport;
+    t_u32 curr_wr_port;
+    t_u32 curr_rd_port;
+    t_u32 mp_end_port;
+    t_u32 bss_num;
+    t_u32 sta_mac_addr1;
+    t_u32 sta_mac_addr2;
+    t_u32 wifi_state;
+} nvram_backup_t;
+#ifndef RW610
+extern osa_task_handle_t wifi_core_thread;
+#endif
+extern bool g_txrx_flag;
+#ifdef WLAN_LOW_POWER_ENABLE
+extern bool low_power_mode;
+#endif
+extern bool cal_data_valid;
+extern bool mac_addr_valid;
+#if CONFIG_WIFI_TX_BUFF
+extern uint16_t tx_buf_size;
+#endif
+extern bool txpwrlimit_data_valid;
+extern uint8_t trpc_country;
+extern bus_operations imu_ops;
+
+mlan_status imu_wifi_init(enum wlan_type type, const uint8_t *fw_ram_start_addr, const size_t size);
+void imu_wifi_deinit(void);
+void imu_uninstall_callback(void);
+
+/*
+ * @internal
+ *
+ *
+ */
+int wlan_send_imu_cmd(t_u8 *buf);
+
+/*
+ * @internal
+ *
+ *
+ */
+int wifi_send_cmdbuffer(void);
+
+/*
+ * @internal
+ *
+ *
+ */
+HostCmd_DS_COMMAND *wifi_get_command_buffer(void);
+
+mlan_status wlan_xmit_pkt(t_u8 *buffer, t_u32 txlen, t_u8 interface, t_u32 tx_control);
+int raw_process_pkt_hdrs(void *pbuf, t_u32 payloadlen, t_u8 interface);
+uint32_t wifi_get_device_value1();
+
+uint8_t *wifi_get_imu_outbuf(uint32_t *outbuf_len);
+
+void process_pkt_hdrs(void *pbuf, t_u32 payloadlen, t_u8 interface, t_u8 tid, t_u32 tx_control);
+
+#if CONFIG_WIFI_FW_DEBUG
+extern void wifi_dump_firmware_info();
+#endif /* CONFIG_WIFI_FW_DEBUG */
+
+#if CONFIG_WMM
+mlan_status wlan_xmit_wmm_pkt(t_u8 interface, t_u32 txlen, t_u8 *tx_buf);
+mlan_status wlan_flush_wmm_pkt(int pkt_cnt);
+mlan_status wlan_xmit_bypass_pkt(t_u8 *buffer, t_u32 txlen, t_u8 interface);
+#if CONFIG_AMSDU_IN_AMPDU
+uint8_t *wifi_get_amsdu_outbuf(uint32_t offset);
+mlan_status wlan_xmit_wmm_amsdu_pkt(mlan_wmm_ac_e ac, t_u8 interface, t_u32 txlen, t_u8 *tx_buf, t_u8 amsdu_cnt);
+#endif
+#endif
+
+void imu_wakeup_card();
+#if CONFIG_WIFI_TX_BUFF
+int _wlan_return_all_tx_buf(imu_link_t link);
+#endif
+
+int imu_create_task_lock(void);
+void imu_delete_task_lock(void);
+int imu_get_task_lock(void);
+int imu_put_task_lock(void);
+#endif /* __WIFI_SDIO_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-internal.h
new file mode 100644
index 0000000000..3d026f00d5
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-internal.h
@@ -0,0 +1,459 @@
+/** @file wifi-internal.h
+ *
+ *  @brief WLAN Internal API
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __WIFI_INTERNAL_H__
+#define __WIFI_INTERNAL_H__
+
+#include <limits.h>
+
+#if CONFIG_WPA_SUPP
+#include "wifi_nxp_internal.h"
+#endif
+
+#include <mlan_api.h>
+
+#include <osa.h>
+#include <wifi_events.h>
+#include <wifi-decl.h>
+#if CONFIG_WPA_SUPP
+#include <ieee802_11_defs.h>
+#endif
+
+/* We don't see events coming in quick succession,
+ * MAX_EVENTS = 20 is fairly big value */
+#define MAX_EVENTS 20
+
+struct bus_message
+{
+    uint16_t event;
+    uint16_t reason;
+    void *data;
+};
+
+typedef struct
+{
+    int (*wifi_uap_downld_domain_params_p)(int band);
+} wifi_uap_11d_apis_t;
+
+typedef struct mcast_filter
+{
+    uint8_t mac_addr[MLAN_MAC_ADDR_LENGTH];
+    struct mcast_filter *next;
+} mcast_filter;
+
+/* User response buffer parameters for hostcmd */
+typedef struct _hostcmd_cfg
+{
+    void *resp_buf;
+    uint32_t resp_buf_len;
+    uint32_t *reqd_resp_len;
+    bool is_hostcmd;
+} hostcmd_cfg_t;
+
+/** This enum defines various thread events
+ * for which thread processing will occur */
+enum wifi_thread_event_t
+{
+    WIFI_EVENT_STA            = 1,
+    WIFI_EVENT_UAP            = 1 << 1,
+    WIFI_EVENT_SDIO           = 1 << 2,
+    WIFI_EVENT_SCAN           = 1 << 3,
+    WIFI_EVENT_TX_DATA        = 1 << 4,
+    WIFI_EVENT_TX_NULL_DATA   = 1 << 5,
+    WIFI_EVENT_TX_BYPASS_DATA = 1 << 6,
+};
+
+typedef struct
+{
+    const uint8_t *fw_start_addr;
+    size_t size;
+    t_u8 wifi_init_done;
+    t_u8 wifi_core_init_done;
+    OSA_TASK_HANDLE_DEFINE(wifi_drv_task_Handle);
+
+#ifndef RW610
+    OSA_TASK_HANDLE_DEFINE(wifi_core_task_Handle);
+#endif
+    OSA_TASK_HANDLE_DEFINE(wifi_scan_task_Handle);
+#if CONFIG_WMM
+    /** Thread handle for sending data */
+    OSA_TASK_HANDLE_DEFINE(wifi_drv_tx_task_Handle);
+#endif
+    OSA_TASK_HANDLE_DEFINE(wifi_powersave_task_Handle);
+
+    OSA_EVENT_HANDLE_DEFINE(wifi_event_Handle);
+
+    osa_msgq_handle_t *wlc_mgr_event_queue;
+
+    void (*data_input_callback)(const uint8_t interface, const uint8_t *buffer, const uint16_t len);
+#if FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER
+    void *(*wifi_get_rxbuf_desc)(t_u16 rx_len);
+#endif
+    void (*amsdu_data_input_callback)(uint8_t interface, uint8_t *buffer, uint16_t len);
+    void (*deliver_packet_above_callback)(void *rxpd, t_u8 interface, t_void *lwip_pbuf);
+    bool (*wrapper_net_is_ip_or_ipv6_callback)(const t_u8 *buffer);
+
+    OSA_MUTEX_HANDLE_DEFINE(command_lock);
+
+    OSA_SEMAPHORE_HANDLE_DEFINE(command_resp_sem);
+
+    OSA_MUTEX_HANDLE_DEFINE(mcastf_mutex);
+
+#if CONFIG_WMM
+    /** Semaphore to protect data parameters */
+    OSA_SEMAPHORE_HANDLE_DEFINE(tx_data_sem);
+#ifdef __ZEPHYR__
+    /** Queue for sending data packets to fw */
+    OSA_MSGQ_HANDLE_DEFINE(tx_data, MAX_EVENTS, sizeof(struct bus_message));
+#endif
+#endif
+    unsigned last_sent_cmd_msec;
+
+    /* Queue for events/data from low level interface driver */
+    OSA_MSGQ_HANDLE_DEFINE(io_events, MAX_EVENTS, sizeof(struct bus_message));
+    OSA_MSGQ_HANDLE_DEFINE(powersave_queue, MAX_EVENTS, sizeof(struct bus_message));
+
+    mcast_filter *start_list;
+
+    /*
+     * Usage note:
+     * There are a number of API's (for e.g. wifi_get_antenna()) which
+     * return some data in the buffer passed by the caller. Most of the
+     * time this data needs to be retrived from the firmware. This
+     * retrival happens in a different thread context. Hence, we need
+     * to store the buffer pointer passed by the user at a shared
+     * location. This pointer to used for this purpose.
+     *
+     * Note to the developer: Please ensure to set this to NULL after
+     * use in the wifi driver thread context.
+     */
+    void *cmd_resp_priv;
+    void *cmd_resp_ioctl;
+    /*
+     * In continuation with the description written for the
+     * cmd_resp_priv member above, the below member indicates the
+     * result of the retrieval operation from the firmware.
+     */
+    int cmd_resp_status;
+
+    /*
+     * Store 11D support status in Wi-Fi driver.
+     */
+    bool enable_11d_support;
+    /*
+     * 11D support callback function
+     */
+    wifi_uap_11d_apis_t *uap_support_11d_apis;
+    /** Broadcast ssid control */
+    t_u8 hidden_ssid;
+    /** beacon period */
+    t_u16 beacon_period;
+    /** Wi-Fi Bandwidth */
+    t_u8 bandwidth;
+    /** channel switch time to send ECSA */
+    t_u8 chan_sw_count;
+    /** Sniffer channel number */
+    t_u8 chan_num;
+    /** ACS channel number */
+    t_u8 acs_chan;
+    /** HT Capability Info */
+    t_u16 ht_cap_info;
+    /** HTTX Cfg */
+    t_u16 ht_tx_cfg;
+#if CONFIG_WIFI_FW_DEBUG
+    /** This function mount USB device.
+     *
+     * return WM_SUCCESS on success
+     * return -WM_FAIL on failure.
+     */
+    int (*wifi_usb_mount_cb)();
+    /** This function will open file for writing FW dump.
+     *
+     * \param[in] test_file_name Name of file to write FW dump data.
+     *
+     * \return WM_SUCCESS if opening of file is successful.
+     * \return -WM_FAIL in case of failure.
+     */
+    int (*wifi_usb_file_open_cb)(char *test_file_name);
+    /** This function will write data to file opened using wifi_usb_file_open_cb()
+     *
+     * \param[in] data Buffer containing FW dump data.
+     * \param[in] data_len Length of data that needs to be written.
+     *
+     * \return WM_SUCCESS if write is successful
+     * \return -WM_FAIL in case of failure.
+     */
+    int (*wifi_usb_file_write_cb)(uint8_t *data, size_t data_len);
+    /** This function will close the file on which FW dump is written.
+     *
+     * \note This will close file that is opened using wifi_usb_file_open_cb().
+     *
+     * \return WM_SUCCESS on success.
+     * \return -WM_FAIL on failure.
+     */
+    int (*wifi_usb_file_close_cb)();
+#endif
+    /** Structure to store the response from WiFi firmware in
+     * response buffer provided by application layers
+     * structure also stores lengths for usage and validation internally*/
+    hostcmd_cfg_t hostcmd_cfg;
+    wlan_user_scan_cfg *g_user_scan_cfg;
+
+    bool scan_stop;
+#if CONFIG_WPA_SUPP
+    void *if_priv;
+    void *hapd_if_priv;
+    wifi_nxp_callbk_fns_t *supp_if_callbk_fns;
+    nxp_wifi_event_mlme_t mgmt_resp;
+    nxp_wifi_assoc_event_mlme_t assoc_resp;
+    nxp_wifi_event_mlme_t mgmt_rx;
+    nxp_wifi_event_eapol_mlme_t eapol_rx;
+    bool wpa_supp_scan;
+    bool external_scan;
+#if CONFIG_HOSTAPD
+    bool hostapd_op;
+#endif
+#endif
+} wm_wifi_t;
+
+extern wm_wifi_t wm_wifi;
+extern bool split_scan_in_progress;
+
+/* fixme: This structure seems to have been removed from mlan. This was
+   copied from userif_ext.h file temporarily. Change the handling of events to
+   make it similar to what mlan does */
+
+/** Event structure */
+typedef MLAN_PACK_START struct _Event_Ext_t
+{
+    /** No of bytes in packet including this field */
+    uint16_t length;
+    /** Type: Event (3) */
+    uint16_t type;
+    /** Event ID */
+    uint16_t event_id;
+    /** BSS index number for multiple BSS support */
+    uint8_t bss_index;
+    /** BSS type */
+    uint8_t bss_type;
+    /** Reason code */
+    uint16_t reason_code;
+    /** Source MAC address */
+    uint8_t src_mac_addr[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END Event_Ext_t;
+
+typedef MLAN_PACK_START struct _mac_address
+{
+    unsigned char addr[MLAN_MAC_ADDR_LENGTH];
+} MLAN_PACK_END mac_address_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_acl_info
+{
+    unsigned char acl_policy;
+    unsigned int num_mac_acl;
+    mac_address_t mac_acl[];
+} MLAN_PACK_END nxp_wifi_acl_info_t;
+
+/* PACK_START struct ieee80211_hdr
+{
+    t_u16 frame_control;
+    t_u16 duration_id;
+    t_u8 addr1[6];
+    t_u8 addr2[6];
+    t_u8 addr3[6];
+    t_u16 seq_ctrl;
+    t_u8 addr4[6];
+} PACK_END; */
+
+/**
+ * This function handles events received from the firmware.
+ */
+int wifi_handle_fw_event(struct bus_message *msg);
+
+/**
+ * This function is used to send events to the upper layer through the
+ * message queue registered by the upper layer.
+ */
+int wifi_event_completion(enum wifi_event event, enum wifi_event_reason result, void *data);
+
+/**
+ * Use this function to know whether a split scan is in progress.
+ */
+bool is_split_scan_complete(void);
+
+/**
+ * Waits for Command processing to complete and waits for command response
+ */
+int wifi_wait_for_cmdresp(void *cmd_resp_priv);
+#if CONFIG_FW_VDLL
+/**
+ * Waits for Command processing to complete and waits for command response for VDLL
+ */
+int wifi_wait_for_vdllcmdresp(void *cmd_resp_priv);
+#endif
+/**
+ * Register an event queue
+ *
+ * This queue is used to send events and command responses to the wifi
+ * driver from the stack dispatcher thread.
+ */
+int bus_register_event_queue(osa_msgq_handle_t event_queue);
+
+/**
+ * De-register the event queue.
+ */
+void bus_deregister_event_queue(void);
+
+/**
+ * Register DATA input function with SDIO driver.
+ *
+ * This queue is used to DATA frames to the wifi
+ * driver from the stack dispatcher thread.
+ */
+int bus_register_data_input_function(int (*wifi_low_level_input)(const uint8_t interface,
+                                                                 const uint8_t *buffer,
+                                                                 const uint16_t len));
+
+/**
+ * De-register the DATA input function with SDIO driver.
+ */
+void bus_deregister_data_input_funtion(void);
+
+/*
+ * @internal
+ *
+ *
+ */
+int wifi_get_command_lock(void);
+
+int wifi_put_command_resp_sem(void);
+
+/*
+ * @internal
+ *
+ *
+ */
+int wifi_put_command_lock(void);
+
+#if ((CONFIG_11MC) || (CONFIG_11AZ)) && (CONFIG_WLS_CSI_PROC)
+/*
+ * @internal
+ *
+ *
+ */
+int wifi_get_wls_csi_sem(void);
+
+/*
+ * @internal
+ *
+ *
+ */
+int wifi_put_wls_csi_sem(void);
+#endif
+
+/*
+ * Process the command reponse received from the firmware.
+ *
+ * Change the type of param below to HostCmd_DS_COMMAND after mlan
+ * integration complete and then move it to header file.
+ */
+int wifi_process_cmd_response(HostCmd_DS_COMMAND *resp);
+
+/*
+ * @internal
+ *
+ *
+ */
+void *wifi_mem_malloc_cmdrespbuf(void);
+
+/*
+ * @internal
+ *
+ *
+ */
+void *wifi_malloc_eventbuf(size_t size);
+void wifi_free_eventbuf(void *buffer);
+
+void wifi_uap_handle_cmd_resp(HostCmd_DS_COMMAND *resp);
+
+mlan_status wrapper_moal_malloc(t_void *pmoal_handle, t_u32 size, t_u32 flag, t_u8 **ppbuf);
+mlan_status wrapper_moal_mfree(t_void *pmoal_handle, t_u8 *pbuf);
+
+#if defined(RW610)
+int wifi_imu_lock(void);
+void wifi_imu_unlock(void);
+#else
+int wifi_sdio_lock(void);
+void wifi_sdio_unlock(void);
+#endif
+
+#if CONFIG_WIFI_IND_RESET
+bool wifi_ind_reset_in_progress(void);
+void wifi_ind_reset_start(void);
+void wifi_ind_reset_stop(void);
+#endif
+
+mlan_status wrapper_wlan_cmd_mgmt_ie(int bss_type, void *buffer, unsigned int len, t_u16 action);
+
+/**
+ * This function should be called when user scan is
+ * finished with success/failure.
+ *
+ */
+void wifi_user_scan_config_cleanup(void);
+
+/**
+ * This function should be called to wait for scan task done before resetting.
+ *
+ */
+void wifi_scan_stop(void);
+int wifi_remain_on_channel(const bool status, const uint8_t channel, const uint32_t duration);
+#if CONFIG_WPA_SUPP
+void wpa_supp_handle_link_lost(mlan_private *priv);
+
+int wifi_set_scan_ies(void *ie, size_t ie_len);
+#if CONFIG_WPA_SUPP_WPS
+bool wifi_nxp_wps_session_enable(void);
+#endif
+
+int wifi_setup_ht_cap(t_u16 *ht_capab, t_u8 *mcs_set, t_u8 *a_mpdu_params, t_u8 band);
+void wifi_setup_channel_info(void *channels, int num_channels, t_u8 band);
+
+#if CONFIG_11AC
+int wifi_setup_vht_cap(t_u32 *vht_capab, t_u8 *vht_mcs_set, t_u8 band);
+#endif
+
+#if CONFIG_11AX
+int wifi_setup_he_cap(nxp_wifi_he_capabilities *he_cap, t_u8 band);
+#endif
+int wifi_nxp_send_assoc(nxp_wifi_assoc_info_t *assoc_info);
+int wifi_nxp_send_mlme(unsigned int bss_type, int channel, unsigned int wait_time, const t_u8 *data, size_t data_len);
+int wifi_nxp_beacon_config(nxp_wifi_ap_info_t *params);
+int wifi_set_uap_rts(int rts_threshold);
+int wifi_set_uap_frag(int frag_threshold);
+int wifi_nxp_sta_add(nxp_wifi_sta_info_t *params);
+int wifi_nxp_sta_remove(const uint8_t *addr);
+void wifi_nxp_uap_disconnect(mlan_private *priv, t_u16 reason_code, t_u8 *mac);
+int wifi_nxp_stop_ap(void);
+int wifi_nxp_set_acl(nxp_wifi_acl_info_t *acl_params);
+int wifi_nxp_set_country(unsigned int bss_type, const char *alpha2);
+int wifi_nxp_get_country(unsigned int bss_type, char *alpha2);
+int wifi_nxp_get_signal(unsigned int bss_type, nxp_wifi_signal_info_t *signal_params);
+int wifi_nxp_scan_res_num(void);
+int wifi_nxp_scan_res_get2(t_u32 table_idx, nxp_wifi_event_new_scan_result_t *scan_res);
+#endif /* CONFIG_WPA_SUPP */
+
+
+#if CONFIG_WMM
+int send_wifi_driver_tx_data_event(t_u8 interface);
+int send_wifi_driver_tx_null_data_event(t_u8 interface);
+#endif
+
+#endif /* __WIFI_INTERNAL_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-mem.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-mem.c
new file mode 100644
index 0000000000..1af23411fd
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-mem.c
@@ -0,0 +1,88 @@
+/** @file wifi-mem.c
+ *
+ *  @brief This file provides WIFI dymanic memory allocation APIs.
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <mlan_api.h>
+#include <string.h>
+#include <osa.h>
+
+#include <wifi-debug.h>
+
+/* Simple memory allocator for Operating Systems that do not support dynamic
+ * allocation. The size of the allocation is hard-coded to the need of the cli
+ * module.
+ *
+ * If required this can be blown into a better slab-kind of allocator.
+ */
+#define HUGE_BUF_SIZE 2000
+static char buffhuge[HUGE_BUF_SIZE];
+
+void *wifi_mem_malloc_cmdrespbuf(void)
+{
+    /* NOTE: There is no corresponding free call for cmdrespbuf */
+    /* CMD are all serialised and they dont need any locking */
+    return buffhuge;
+}
+
+void *wifi_malloc_eventbuf(size_t size)
+{
+#if !CONFIG_MEM_POOLS
+    void *ptr = OSA_MemoryAllocate(size);
+
+    if (ptr != NULL)
+    {
+        w_mem_d("[evtbuf] Alloc: A: %p S: %d", ptr, size);
+    }
+    else
+    {
+        w_mem_e("[evtbuf] Alloc: S: %d FAILED", size);
+    }
+#else
+    void *ptr = OSA_MemoryPoolAllocate(buf_2560_MemoryPool);
+#endif
+
+    return ptr;
+}
+
+void wifi_free_eventbuf(void *buffer)
+{
+#if !CONFIG_MEM_POOLS
+    w_mem_d("[evtbuf] Free: A: %p\n\r", buffer);
+    OSA_MemoryFree(buffer);
+#else
+    OSA_MemoryPoolFree(buf_2560_MemoryPool, buffer);
+#endif
+}
+
+mlan_status wrapper_moal_malloc(IN t_void *pmoal_handle, IN t_u32 size, IN t_u32 flag, OUT t_u8 **ppbuf)
+{
+    *ppbuf = OSA_MemoryAllocate(size);
+
+
+    if (*ppbuf != NULL)
+    {
+        w_mem_d("[mlan]: Alloc: A: %p S: %d", *ppbuf, size);
+        return MLAN_STATUS_SUCCESS;
+    }
+    else
+    {
+        w_mem_e("[mlan] Alloc: S: %d FAILED", size);
+        /*
+         * fixme: check if MLAN_STATUS_SUCCESS is to be returned in
+         * spite of the status failure.
+         */
+        return MLAN_STATUS_FAILURE;
+    }
+}
+
+mlan_status wrapper_moal_mfree(IN t_void *pmoal_handle, IN t_u8 *pbuf)
+{
+    w_mem_d("[mlan] Free: A: %p", pbuf);
+    OSA_MemoryFree(pbuf);
+    return MLAN_STATUS_SUCCESS;
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-uap.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-uap.c
new file mode 100644
index 0000000000..133fb72fa4
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-uap.c
@@ -0,0 +1,4796 @@
+/** @file wifi-uap.c
+ *
+ *  @brief This file provides UAP related APIs.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mlan_api.h>
+
+/* Additional WMSDK header files */
+#include <wmerrno.h>
+#include <osa.h>
+#include "wifi_nxp_internal.h"
+#include <wifi.h>
+#if defined(RW610)
+#include "wifi-imu.h"
+#else
+#include "wifi-sdio.h"
+#endif
+#if CONFIG_WPA_SUPP_AP
+#include "rtos_wpa_supp_if.h"
+#endif
+#include "wifi-internal.h"
+#include "mlan_ieee.h"
+#include <mlan_remap_mem_operations.h>
+
+/* fixme: Some of the following options could be added to kconfig. While
+   adding the ranges in kconfig use the ones given as macros in
+   mlan_uap_cmdevent.c */
+#ifdef RW610
+#define UAP_BEACON_PERIOD 100U
+#else
+#define UAP_BEACON_PERIOD 200U
+#endif
+#define UAP_DTIM_PERIOD 1
+#define MAX_RATES       14U
+
+#if CONFIG_5GHz_SUPPORT
+static uint8_t rates_5ghz[] = {0x8c, 0x98, 0xb0, 0x12, 0x24, 0x48, 0x60, 0x6c, 0x00};
+#endif
+
+static uint8_t rates_2ghz[] = {0x82, 0x84, 0x8b, 0x96, 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c, 0x00};
+
+static uint8_t rates_2ghz_b[] = {0x82, 0x84, 0x8b, 0x96, 0x00};
+
+#if CONFIG_11AC
+/**
+ * @brief initialize AP bss config
+ * @param pmpriv            A pointer to mlan_private structure
+ * @param band            BAND_5G/BAND_2GHZ
+ * @return                0 -- success, otherwise fail
+ */
+static bool wifi_check_11ac_capability(mlan_private *pmpriv, t_u8 band)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    bool enable_11ac        = MFALSE;
+
+    ENTER();
+#if CONFIG_WIFI_CAPA
+    if (!pmadapter->usr_dot_11ac_enable)
+    {
+        return enable_11ac;
+    }
+#endif
+    if ((band == BAND_CONFIG_5GHZ) && !(pmadapter->fw_bands & BAND_AAC))
+    {
+        PRINTM(MCMND, "FW don't support 5G AC\n");
+        LEAVE();
+        return enable_11ac;
+    }
+    if ((band == BAND_CONFIG_ACS_MODE || band == BAND_CONFIG_MANUAL) && !(pmadapter->fw_bands & BAND_GAC))
+    {
+        PRINTM(MCMND, "FW don't support 2G AC");
+        LEAVE();
+        return enable_11ac;
+    }
+    enable_11ac = MTRUE;
+
+    LEAVE();
+    return enable_11ac;
+}
+
+#define VHT_CAP_11AC_MASK 0x007fffff
+
+/**
+ *  @brief enable/disable 11AC
+ *
+ *  @param pmpriv   A pointer to mlan_private structure
+ *  @param action   MLAN_ACT_DISABLE or MLAN_ACT_ENABLE
+ *  @param band     band config
+ *
+ *  @return         0--success, otherwise failure
+ */
+static int wifi_uap_set_11ac_status(mlan_private *pmpriv, t_u8 action, t_u8 bandwidth, t_u8 channel)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    int ret                 = 0;
+    mlan_ds_11ac_vht_cfg vht_cfg;
+
+    (void)memset(&vht_cfg, 0, sizeof(vht_cfg));
+
+#if CONFIG_5GHz_SUPPORT
+    if (channel > MAX_CHANNELS_BG)
+    {
+        vht_cfg.band = BAND_SELECT_A;
+    }
+    else
+    {
+        vht_cfg.band = BAND_SELECT_BG;
+    }
+#else
+    vht_cfg.band                     = BAND_SELECT_BG;
+#endif
+    vht_cfg.txrx = MLAN_RADIO_TXRX;
+
+    vht_cfg.vht_cap_info = pmadapter->usr_dot_11ac_dev_cap_a;
+    if (action == MLAN_ACT_DISABLE)
+    {
+        vht_cfg.bwcfg = BW_FOLLOW_HTCAP;
+        vht_cfg.vht_cap_info &= ~VHT_CAP_11AC_MASK;
+        vht_cfg.vht_rx_mcs = vht_cfg.vht_tx_mcs = 0xffff;
+        vht_cfg.skip_usr_11ac_mcs_cfg           = MTRUE;
+    }
+    else
+    {
+        if (BANDWIDTH_80MHZ == bandwidth)
+        {
+            vht_cfg.bwcfg = BW_FOLLOW_VHTCAP;
+        }
+        else
+        {
+            vht_cfg.bwcfg = BW_FOLLOW_HTCAP;
+        }
+
+        vht_cfg.vht_cap_info &= ~DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK;
+#ifdef RW610
+        vht_cfg.vht_cap_info &= ~DEFALUT_11AC_CAP_SHORTGI_80MHZ_RESET_MASK;
+#endif
+        vht_cfg.vht_tx_mcs            = pmadapter->usr_dot_11ac_mcs_support >> 16;
+        vht_cfg.vht_rx_mcs            = pmadapter->usr_dot_11ac_mcs_support & 0xffff;
+        vht_cfg.skip_usr_11ac_mcs_cfg = MTRUE;
+    }
+
+    if ((GET_VHTCAP_MAXMPDULEN(vht_cfg.vht_cap_info)) != 0U)
+    {
+        RESET_11ACMAXMPDULEN(vht_cfg.vht_cap_info);
+    }
+    else
+    {
+        /** Do Nothing */
+    }
+
+    wifi_d("Uap:11ac=%d vht_cap_info=0x%x, vht_tx_mcs=0x%x, vht_rx_mcs=0x%x\r\n", action, vht_cfg.vht_cap_info,
+           vht_cfg.vht_tx_mcs, vht_cfg.vht_rx_mcs);
+    ret = (int)wlan_11ac_ioctl_vhtcfg(pmpriv, (t_u8)MLAN_ACT_SET, &vht_cfg);
+    return ret;
+}
+#endif
+
+#if CONFIG_11AX
+/**
+ * @brief initialize AP bss config
+ * @param pmpriv            A pointer to mlan_private structure
+ * @param band            BAND_5G/BAND_2GHZ
+ * @return                0 -- success, otherwise fail
+ */
+static t_u8 wifi_check_11ax_capability(mlan_private *pmpriv, t_u8 band)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u8 enable_11ax        = MFALSE;
+
+    ENTER();
+#if CONFIG_WIFI_CAPA
+    if (!pmadapter->usr_dot_11ax_enable)
+    {
+        return enable_11ax;
+    }
+#endif
+    if ((band == BAND_CONFIG_5GHZ) && !(pmadapter->fw_bands & BAND_AAX))
+    {
+        PRINTM(MCMND, "FW don't support 5G AX\n");
+        LEAVE();
+        return enable_11ax;
+    }
+    if ((band == BAND_CONFIG_ACS_MODE || band == BAND_CONFIG_MANUAL) && !(pmadapter->fw_bands & BAND_GAX))
+    {
+        PRINTM(MCMND, "FW don't support 2G AX\n");
+        LEAVE();
+        return enable_11ax;
+    }
+    enable_11ax = MTRUE;
+    PRINTM(MCMND, "enable_11ax=%d\n", enable_11ax);
+    LEAVE();
+    return enable_11ax;
+}
+
+/**
+ *  @brief enable/disable 11AX
+ *
+ *  @param pmpriv   A pointer to mlan_private structure
+ *  @param action   MLAN_ACT_DISABLE or MLAN_ACT_ENABLE
+ *  @param band     band config
+ *
+ *  @return         0--success, otherwise failure
+ */
+int wifi_uap_set_11ax_status(mlan_private *pmpriv, t_u8 action, t_u8 band, t_u8 bandwidth)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    int ret                 = 0;
+    mlan_ds_11ax_he_cfg he_cfg;
+
+    ENTER();
+    if ((band == BAND_CONFIG_5GHZ && !(pmadapter->fw_bands & BAND_AAX)) ||
+        ((band == BAND_CONFIG_ACS_MODE || band == BAND_CONFIG_MANUAL) && !(pmadapter->fw_bands & BAND_GAX)))
+    {
+        PRINTM(MERROR, "fw doesn't support 11ax\n");
+        ret = -WM_FAIL;
+        goto done;
+    }
+    memset(&he_cfg, 0, sizeof(he_cfg));
+    if (band == BAND_CONFIG_5GHZ)
+    {
+        he_cfg.band = MBIT(1);
+        (void)memcpy((void *)&he_cfg.he_cap, (const void *)pmadapter->hw_he_cap, pmadapter->hw_hecap_len);
+        if (bandwidth == BANDWIDTH_20MHZ)
+        {
+            he_cfg.he_cap.he_phy_cap[0] &= ~(MBIT(2));
+        }
+    }
+    else if (band == BAND_CONFIG_ACS_MODE || band == BAND_CONFIG_MANUAL)
+    {
+        he_cfg.band = MBIT(0);
+        (void)memcpy((void *)&he_cfg.he_cap, (const void *)pmadapter->hw_2g_he_cap, pmadapter->hw_2g_hecap_len);
+        if (bandwidth == BANDWIDTH_20MHZ)
+        {
+            he_cfg.he_cap.he_phy_cap[0] &= ~(MBIT(1));
+            he_cfg.he_cap.he_phy_cap[0] &= ~(MBIT(2));
+        }
+    }
+    else
+    {
+        PRINTM(MERROR, "Invalid band!\n");
+        ret = -WM_E_INVAL;
+        goto done;
+    }
+
+#ifdef RW610
+    he_cfg.he_cap.he_phy_cap[0] &= ~DEFAULT_11AX_CAP_40MHZIH2_4GHZBAND_RESET_MASK;
+#endif
+
+#if CONFIG_11AX_TWT
+    /* uap mode clear TWT request bit */
+    he_cfg.he_cap.he_mac_cap[0] &= ~HE_MAC_CAP_TWT_REQ_SUPPORT;
+#endif
+
+    if (action == MLAN_ACT_DISABLE)
+    {
+        if (he_cfg.he_cap.len && (he_cfg.he_cap.ext_id == HE_CAPABILITY))
+            memset(he_cfg.he_cap.he_txrx_mcs_support, 0xff, sizeof(he_cfg.he_cap.he_txrx_mcs_support));
+        else
+        {
+            PRINTM(MCMND, "11ax already disabled\n");
+            goto done;
+        }
+    }
+    DBG_HEXDUMP(MCMD_D, "HE_CFG ", (t_u8 *)&he_cfg, sizeof(he_cfg));
+    ret = wlan_cmd_11ax_cfg(pmpriv, HostCmd_ACT_GEN_SET, &he_cfg);
+done:
+    LEAVE();
+    return ret;
+}
+#endif /* CONFIG_11AX */
+
+void wifi_uap_clear_domain_info()
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd                     = wifi_get_command_buffer();
+    HostCmd_DS_802_11D_DOMAIN_INFO *domain_info = (HostCmd_DS_802_11D_DOMAIN_INFO *)((t_u8 *)cmd + S_DS_GEN);
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_UAP);
+    cmd->command = wlan_cpu_to_le16(HostCmd_CMD_802_11D_DOMAIN_INFO);
+    cmd->size    = S_DS_GEN + sizeof(domain_info->action) + sizeof(MrvlIEtypesHeader_t);
+
+    domain_info->action             = HostCmd_ACT_GEN_SET;
+    domain_info->domain.header.type = wlan_cpu_to_le16(TLV_TYPE_DOMAIN);
+
+    wifi_wait_for_cmdresp(NULL);
+}
+
+int wifi_uap_prepare_and_send_cmd(mlan_private *pmpriv,
+                                  t_u16 cmd_no,
+                                  t_u16 cmd_action,
+                                  t_u32 cmd_oid,
+                                  t_void *pioctl_buf,
+                                  t_void *pdata_buf,
+                                  mlan_bss_type bss_type,
+                                  void *priv)
+{
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, (uint16_t)bss_type);
+    cmd->result  = 0x0;
+
+    mlan_status rv = wlan_ops_uap_prepare_cmd(pmpriv, cmd_no, cmd_action, cmd_oid, pioctl_buf, pdata_buf, cmd);
+    if (rv != MLAN_STATUS_SUCCESS)
+    {
+        wifi_w("Failed to prepare cmd for uAP");
+        (void)wifi_put_command_lock();
+        return (int)rv;
+    }
+
+    (void)wifi_wait_for_cmdresp(priv);
+    return wm_wifi.cmd_resp_status;
+}
+
+/*
+ * Note: wlan_uap_domain_info() and wlan_uap_callback_domain_info() are the
+ * original function which handles this functionality. However, it does it
+ * through and IOCTL and its control flow will not work in our case. To
+ * elaborate, it first gets the channel number by sending a command to
+ * firmware. Then in the cmd resp handler to sends the domain info
+ * command. As per the current design of our driver we cannot send command
+ * from command resp handler. Hence, we have modified the control flow to
+ * suit our design.
+ *
+ * This Api is set as callback and called during uap start phase,
+ * getting region code by pmadapter.
+ * Then it sends 80211 domain info command to firmware
+ */
+int wifi_uap_downld_domain_params(int band)
+{
+    int rv;
+    mlan_private *priv_uap   = mlan_adap->priv[1];
+    int region_code          = mlan_adap->region_code;
+    const t_u8 *country_code = NULL;
+    t_u8 nr_sb;
+    wifi_sub_band_set_t *sub_band_list = NULL;
+
+    /* get band and sub band lists */
+#if CONFIG_5GHz_SUPPORT
+    if (band == BAND_A)
+    {
+        sub_band_list = get_sub_band_from_region_code_5ghz(region_code, &nr_sb);
+    }
+    else
+    {
+        sub_band_list = get_sub_band_from_region_code(region_code, &nr_sb);
+    }
+#else
+    sub_band_list = get_sub_band_from_region_code(region_code, &nr_sb);
+#endif
+
+    /* get country code string from region code */
+    country_code = wlan_11d_code_2_region(mlan_adap, (t_u8)region_code);
+    if (country_code == NULL)
+    {
+        wuap_e("wifi_uap_downld_domain_params get country_code from region_code failed");
+        return -WM_FAIL;
+    }
+
+    /* restore domain info params for fw command */
+    wlan_11d_set_domain_info(priv_uap, band, country_code, nr_sb, (IEEEtypes_SubbandSet_t *)sub_band_list);
+
+    rv = wifi_uap_prepare_and_send_cmd(priv_uap, HostCmd_CMD_802_11D_DOMAIN_INFO, HostCmd_ACT_GEN_SET, 0, NULL, NULL,
+                                       MLAN_BSS_TYPE_UAP, NULL);
+    if (rv != 0)
+    {
+        wuap_w("Unable to send uap domain info");
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+static int wifi_cmd_uap_config(char *ssid,
+                               t_u8 *mac_addr,
+                               enum wlan_security_type security,
+                               int key_mgmt,
+                               char *passphrase,
+                               char *password,
+                               t_u8 channel,
+                               wifi_scan_chan_list_t scan_chan_list,
+                               t_u8 pwe_derivation,
+                               t_u8 transition_disable,
+                               t_u16 beacon_period,
+                               t_u8 bandwidth,
+                               t_u8 dtim_period,
+                               t_u8 chan_sw_count,
+                               mlan_bss_type bss_type,
+                               bool mfpc,
+                               bool mfpr)
+{
+    t_u32 ssid_len = strlen(ssid);
+    uint8_t i;
+    const t_u8 wmm_oui[4] = {0x00, 0x50, 0xf2, 0x02};
+    int ret;
+    t_u8 supported_mcs_set[] = {0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+#if CONFIG_11AC
+    bool enable_11ac = MFALSE;
+#endif
+#if CONFIG_11AX
+    t_u8 enable_11ax = MFALSE;
+#endif
+
+    if (!(security == WLAN_SECURITY_NONE || security == WLAN_SECURITY_WPA2 ||
+          security == WLAN_SECURITY_WPA_WPA2_MIXED || security == WLAN_SECURITY_WPA3_SAE ||
+          security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED
+#if CONFIG_DRIVER_OWE
+          || security == WLAN_SECURITY_OWE_ONLY
+#endif
+          ))
+    {
+        return -WM_E_INVAL;
+    }
+
+#if !CONFIG_WPA_SUPP
+    int passphrase_len = (int)strlen(passphrase);
+    int password_len   = (int)strlen(password);
+#endif
+
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    wifi_uap_set_beacon_period(beacon_period);
+
+    /* fixme: check if this needs to go on heap */
+    mlan_ds_bss bss;
+    (void)memset(&bss, 0x00, sizeof(mlan_ds_bss));
+
+    bss.sub_command = MLAN_OID_UAP_BSS_CONFIG;
+
+    bss.param.bss_config.ssid.ssid_len = ssid_len;
+    (void)memcpy((void *)bss.param.bss_config.ssid.ssid, (const void *)ssid, ssid_len);
+
+    if (mac_addr != NULL)
+    {
+        (void)memcpy((void *)bss.param.bss_config.mac_addr, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+    }
+
+    if (bss_type == MLAN_BSS_TYPE_UAP)
+    { /* Not required for WFD */
+        bss.param.bss_config.beacon_period = beacon_period;
+        bss.param.bss_config.dtim_period   = dtim_period;
+        if (!wm_wifi.hidden_ssid)
+            bss.param.bss_config.bcast_ssid_ctl = 1;
+        else if (wm_wifi.hidden_ssid == 1)
+            bss.param.bss_config.bcast_ssid_ctl = 0;
+        else if (wm_wifi.hidden_ssid == 2)
+            bss.param.bss_config.bcast_ssid_ctl = 2;
+
+        if (chan_sw_count != 0U)
+        {
+            bss.param.bss_config.dtim_period   = 1;
+            bss.param.bss_config.chan_sw_count = chan_sw_count;
+        }
+    }
+    /* Auto channel selection is not handled in 5GHz band, only
+     * manual channel selection is supported right now.
+     */
+    if (channel != 0U)
+    {
+#if CONFIG_5GHz_SUPPORT
+        if (channel > MAX_CHANNELS_BG)
+        {
+            mlan_private *priv_sta = (mlan_private *)mlan_adap->priv[0];
+            if ((priv_sta->media_connected == MFALSE) && wlan_11h_radar_detect_required(pmpriv, channel))
+            {
+                wuap_e("Cannot start uAP on DFS channel %d", channel);
+                return -WM_E_INVAL;
+            }
+#if CONFIG_UNII4_BAND_SUPPORT
+            /* TODO: Temporary work around until firmware fix is available */
+            if (channel == 173)
+            {
+                bss.param.bss_config.band_cfg = BAND_CONFIG_CH_173;
+            }
+            else if((channel == 169) || (channel == 177))
+            {
+                bss.param.bss_config.band_cfg = BAND_CONFIG_CH_169_177;
+            }
+            else
+#endif
+            {
+                bss.param.bss_config.band_cfg = BAND_CONFIG_5GHZ;
+            }
+            (void)memcpy((void *)bss.param.bss_config.rates, (const void *)rates_5ghz, sizeof(rates_5ghz));
+        }
+        else
+        {
+            if (channel == 14)
+            {
+                (void)memcpy((void *)bss.param.bss_config.rates, (const void *)rates_2ghz_b, sizeof(rates_2ghz_b));
+            }
+            else
+            {
+                (void)memcpy((void *)bss.param.bss_config.rates, (const void *)rates_2ghz, sizeof(rates_2ghz));
+            }
+            bss.param.bss_config.band_cfg = BAND_CONFIG_MANUAL;
+        }
+#else
+        if (channel == 14)
+        {
+            (void)memcpy((void *)bss.param.bss_config.rates, (const void *)rates_2ghz_b, sizeof(rates_2ghz_b));
+        }
+        else
+        {
+            (void)memcpy((void *)bss.param.bss_config.rates, (const void *)rates_2ghz, sizeof(rates_2ghz));
+        }
+        bss.param.bss_config.band_cfg = BAND_CONFIG_MANUAL;
+#endif
+        bss.param.bss_config.channel = channel;
+    }
+    else
+    {
+        /* Auto channel selection from all channels*/
+        bss.param.bss_config.band_cfg = BAND_CONFIG_ACS_MODE;
+        bss.param.bss_config.channel  = 0;
+
+        if (scan_chan_list.num_of_chan != 0U)
+        {
+            /* Specify channels if any for Auto channel selection */
+            bss.param.bss_config.num_of_chan = scan_chan_list.num_of_chan;
+            for (i = 0; i < scan_chan_list.num_of_chan; i++)
+            {
+                bss.param.bss_config.chan_list[i].chan_number = scan_chan_list.chan_number[i];
+#if CONFIG_5GHz_SUPPORT
+                if (scan_chan_list.chan_number[i] > MAX_CHANNELS_BG)
+                {
+                    bss.param.bss_config.chan_list[i].band_config_type = BAND_CONFIG_5GHZ;
+                    (void)memcpy((void *)bss.param.bss_config.rates, (const void *)rates_5ghz, sizeof(rates_5ghz));
+                }
+                else
+#endif
+                {
+                    bss.param.bss_config.chan_list[i].band_config_type = 0x10;
+                    (void)memcpy(bss.param.bss_config.rates, rates_2ghz, sizeof(rates_2ghz));
+                }
+            }
+        }
+    }
+
+#if CONFIG_11AC
+    enable_11ac = wifi_check_11ac_capability(pmpriv, bss.param.bss_config.band_cfg);
+#endif
+#if CONFIG_11AX
+    enable_11ax = wifi_check_11ax_capability(pmpriv, bss.param.bss_config.band_cfg);
+#endif
+#if !CONFIG_WPA_SUPP
+    if (security == WLAN_SECURITY_NONE)
+    {
+        bss.param.bss_config.protocol = PROTOCOL_NO_SECURITY;
+    }
+
+    if (security == WLAN_SECURITY_WPA2 || security == WLAN_SECURITY_WPA_WPA2_MIXED ||
+        security == WLAN_SECURITY_WPA3_SAE || security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED
+#if CONFIG_DRIVER_OWE
+        || security == WLAN_SECURITY_OWE_ONLY
+#endif
+    )
+    {
+        bss.param.bss_config.wpa_cfg.pairwise_cipher_wpa2 = CIPHER_AES_CCMP;
+        bss.param.bss_config.wpa_cfg.group_cipher         = CIPHER_AES_CCMP;
+        if (security == WLAN_SECURITY_WPA2)
+        {
+            bss.param.bss_config.protocol = PROTOCOL_WPA2;
+            if (key_mgmt & WLAN_KEY_MGMT_PSK)
+            {
+                bss.param.bss_config.key_mgmt = KEY_MGMT_PSK;
+            }
+            if (key_mgmt & WLAN_KEY_MGMT_PSK_SHA256)
+            {
+                bss.param.bss_config.key_mgmt |= KEY_MGMT_PSK_SHA256;
+            }
+        }
+        else if (security == WLAN_SECURITY_WPA_WPA2_MIXED)
+        {
+            bss.param.bss_config.protocol = PROTOCOL_WPA2_MIXED;
+            if (key_mgmt & WLAN_KEY_MGMT_PSK)
+            {
+                bss.param.bss_config.key_mgmt = KEY_MGMT_PSK;
+            }
+            if (key_mgmt & WLAN_KEY_MGMT_PSK_SHA256)
+            {
+                bss.param.bss_config.key_mgmt |= KEY_MGMT_PSK_SHA256;
+            }
+            bss.param.bss_config.wpa_cfg.pairwise_cipher_wpa  = CIPHER_TKIP | CIPHER_AES_CCMP;
+            bss.param.bss_config.wpa_cfg.pairwise_cipher_wpa2 = CIPHER_TKIP | CIPHER_AES_CCMP;
+            bss.param.bss_config.wpa_cfg.group_cipher         = CIPHER_TKIP;
+        }
+        else if (security == WLAN_SECURITY_WPA3_SAE)
+        {
+            bss.param.bss_config.protocol = PROTOCOL_WPA3_SAE;
+            if (key_mgmt & WLAN_KEY_MGMT_SAE)
+            {
+                bss.param.bss_config.key_mgmt = KEY_MGMT_SAE;
+            }
+        }
+        else if (security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED)
+        {
+            bss.param.bss_config.protocol = PROTOCOL_WPA2 | PROTOCOL_WPA3_SAE;
+            if (key_mgmt & WLAN_KEY_MGMT_PSK)
+            {
+                bss.param.bss_config.key_mgmt = KEY_MGMT_PSK;
+            }
+            if (key_mgmt & WLAN_KEY_MGMT_PSK_SHA256)
+            {
+                bss.param.bss_config.key_mgmt |= KEY_MGMT_PSK_SHA256;
+            }
+            if (key_mgmt & WLAN_KEY_MGMT_SAE)
+            {
+                bss.param.bss_config.key_mgmt |= KEY_MGMT_SAE;
+            }
+        }
+#if CONFIG_DRIVER_OWE
+        else if (security == WLAN_SECURITY_OWE_ONLY)
+        {
+            bss.param.bss_config.protocol = PROTOCOL_OWE;
+            if (key_mgmt & WLAN_KEY_MGMT_OWE)
+            {
+                bss.param.bss_config.key_mgmt = KEY_MGMT_OWE;
+            }
+        }
+#endif
+        else
+        { /* Do Nothing */
+        }
+        /***************************************
+         * Operation UINT16 Bits[15:2]: Reserved      *
+         *                                  Bit[1]: Authenticator     *
+         *                                  Bit[0]: KeyExchange      *
+         ****************************************/
+        bss.param.bss_config.key_mgmt_operation = 0x00;
+
+            if (security == WLAN_SECURITY_WPA2 || security == WLAN_SECURITY_WPA_WPA2_MIXED ||
+                security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED)
+            {
+                /*app has converted pmk with psk*/
+                bss.param.bss_config.wpa_cfg.length = (t_u32)passphrase_len;
+                (void)memcpy((void *)bss.param.bss_config.wpa_cfg.passphrase, (const void *)passphrase,
+                             (size_t)passphrase_len);
+            }
+        if (security == WLAN_SECURITY_WPA3_SAE || security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED)
+        {
+            bss.param.bss_config.auth_mode               = MLAN_AUTH_MODE_AUTO;
+            bss.param.bss_config.pwe_derivation          = pwe_derivation;
+            bss.param.bss_config.transition_disable      = transition_disable;
+            bss.param.bss_config.wpa_cfg.password_length = (t_u32)password_len;
+            (void)memcpy((void *)bss.param.bss_config.wpa_cfg.password, (const void *)password, (size_t)password_len);
+        }
+    }
+#endif
+    bss.param.bss_config.ht_cap_info = wm_wifi.ht_cap_info == 0 ? (t_u16)0x112c : wm_wifi.ht_cap_info;
+    wm_wifi.ht_tx_cfg                = wm_wifi.ht_tx_cfg == 0 ? (t_u16)0x002c : wm_wifi.ht_tx_cfg;
+
+    if (bandwidth == BANDWIDTH_40MHZ
+#if CONFIG_11AC
+        || bandwidth == BANDWIDTH_80MHZ
+#endif
+    )
+    {
+        if (ISSUPP_CHANWIDTH40(mlan_adap->hw_dot_11n_dev_cap) != 0U)
+        {
+            bss.param.bss_config.ht_cap_info |= MBIT(1);
+            wm_wifi.ht_tx_cfg |= MBIT(1);
+            if (ISSUPP_SHORTGI40(mlan_adap->hw_dot_11n_dev_cap) != 0U)
+            {
+                bss.param.bss_config.ht_cap_info |= MBIT(6);
+                wm_wifi.ht_tx_cfg |= MBIT(6);
+            }
+        }
+    }
+    else if (bandwidth == BANDWIDTH_20MHZ)
+    {
+        wm_wifi.ht_tx_cfg &= ~MBIT(1);
+        wm_wifi.ht_tx_cfg &= ~MBIT(6);
+        bss.param.bss_config.ht_cap_info &= ~MBIT(12);
+    }
+    else
+    {
+        /*Do Nothing*/
+    }
+
+    if (ISSUPP_RXLDPC(mlan_adap->hw_dot_11n_dev_cap) != 0U)
+    {
+        SETHT_LDPCCODINGCAP(bss.param.bss_config.ht_cap_info);
+        SETHT_LDPCCODINGCAP(wm_wifi.ht_tx_cfg);
+    }
+    ret = wifi_uap_set_httxcfg_int(wm_wifi.ht_tx_cfg);
+    if (ret != WM_SUCCESS)
+    {
+        wuap_e("Cannot set uAP HT TX Cfg:%x", wm_wifi.ht_tx_cfg);
+        return -WM_E_INVAL;
+    }
+
+    if (!ISSUPP_TXSTBC(mlan_adap->hw_dot_11n_dev_cap))
+        bss.param.bss_config.ht_cap_info &= (~MBIT(7));
+    if (!ISSUPP_RXSTBC(mlan_adap->hw_dot_11n_dev_cap))
+        bss.param.bss_config.ht_cap_info &= (~(MBIT(8) | MBIT(9)));
+    if (!ISSUPP_CHANWIDTH40(mlan_adap->hw_dot_11n_dev_cap))
+        bss.param.bss_config.ht_cap_info &= (~MBIT(12));
+
+#ifdef RW610
+    /* Set Tx Beam Forming Cap */
+    bss.param.bss_config.tx_bf_cap = mlan_adap->priv[1]->tx_bf_cap;
+#endif
+
+#if CONFIG_11AC
+    if (enable_11ac)
+    {
+        (void)wifi_uap_set_11ac_status(pmpriv, MLAN_ACT_ENABLE, bandwidth, channel);
+    }
+    else
+    {
+        (void)wifi_uap_set_11ac_status(pmpriv, MLAN_ACT_DISABLE, bandwidth, channel);
+    }
+#endif
+#if CONFIG_11AX
+    if (enable_11ax)
+    {
+        wifi_uap_set_11ax_status(pmpriv, MLAN_ACT_ENABLE, bss.param.bss_config.band_cfg, bandwidth);
+    }
+    else
+    {
+        wifi_uap_set_11ax_status(pmpriv, MLAN_ACT_DISABLE, bss.param.bss_config.band_cfg, bandwidth);
+    }
+#endif
+#ifdef RW610_SERIES
+    bss.param.bss_config.ampdu_param = 0x17;
+#else
+    bss.param.bss_config.ampdu_param = 0x03;
+#endif
+    (void)memcpy((void *)bss.param.bss_config.supported_mcs_set, (const void *)supported_mcs_set,
+                 sizeof(bss.param.bss_config.supported_mcs_set));
+    /*
+     * Note that we are leaving htcap info set to zero by default. This
+     *  will ensure that 11N is disabled.
+     */
+
+    memset(&bss.param.bss_config.wmm_para, 0x00, sizeof(wmm_parameter_t));
+
+    memcpy(&bss.param.bss_config.wmm_para.ouitype, wmm_oui, sizeof(wmm_oui));
+#if CONFIG_WIFI_CAPA
+    if (pmpriv->adapter->usr_dot_11n_enable)
+#endif
+    {
+        bss.param.bss_config.wmm_para.ouisubtype = 0x01;
+        bss.param.bss_config.wmm_para.version    = 0x01;
+        bss.param.bss_config.wmm_para.reserved   = 0x00;
+
+        memcpy(&bss.param.bss_config.wmm_para.ac_params, &mlan_adap->ac_params,
+               sizeof(wmm_ac_parameters_t) * MAX_AC_QUEUES);
+        for (i = 0; i < MAX_AC_QUEUES; i++)
+        {
+            bss.param.bss_config.wmm_para.ac_params[i].tx_op_limit =
+                wlan_cpu_to_le16(mlan_adap->ac_params[i].tx_op_limit);
+        }
+    }
+
+    mlan_ioctl_req ioctl_buf;
+    (void)memset(&ioctl_buf, 0x00, sizeof(mlan_ioctl_req));
+
+    ioctl_buf.req_id = (t_u32)MLAN_IOCTL_BSS;
+    /** Pointer to buffer */
+    ioctl_buf.pbuf = (t_u8 *)&bss;
+
+    return wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_SYS_CONFIGURE, HostCmd_ACT_GEN_SET, 0, &ioctl_buf, NULL,
+                                         bss_type, NULL);
+}
+
+static wifi_uap_11d_apis_t wifi_uap_11d_apis = {
+    .wifi_uap_downld_domain_params_p = wifi_uap_downld_domain_params,
+};
+
+int wifi_uap_enable_11d_support(void)
+{
+    wuap_d("Enabling 11d support APIs");
+
+    wm_wifi.enable_11d_support   = true;
+    wm_wifi.uap_support_11d_apis = &wifi_uap_11d_apis;
+    return WM_SUCCESS;
+}
+
+int wifi_uap_ctrl_deauth(bool enable)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    return wifi_uap_prepare_and_send_cmd(pmpriv, HostCmd_CMD_802_11_SNMP_MIB, HostCmd_ACT_GEN_SET, (t_u32)StopDeauth_i,
+                                         NULL, &enable, MLAN_BSS_TYPE_UAP, NULL);
+}
+
+void wifi_uap_set_beacon_period(const t_u16 beacon_period)
+{
+    wm_wifi.beacon_period = beacon_period;
+}
+
+int wifi_uap_set_bandwidth(const t_u8 bandwidth)
+{
+    if (bandwidth == BANDWIDTH_20MHZ || bandwidth == BANDWIDTH_40MHZ
+#if CONFIG_11AC
+        || bandwidth == BANDWIDTH_80MHZ
+#endif
+    )
+    {
+        wm_wifi.bandwidth = bandwidth;
+        return WM_SUCCESS;
+    }
+    return (-WM_FAIL);
+}
+
+t_u8 wifi_uap_get_bandwidth()
+{
+    return wm_wifi.bandwidth;
+}
+
+void wifi_uap_set_hidden_ssid(const t_u8 hidden_ssid)
+{
+    wm_wifi.hidden_ssid = hidden_ssid;
+}
+
+void wifi_uap_set_ecsa(void)
+{
+#if defined(SD8801)
+    wm_wifi.chan_sw_count = 7;
+#endif
+}
+
+void wifi_uap_set_htcapinfo(const t_u16 ht_cap_info)
+{
+    wm_wifi.ht_cap_info = ht_cap_info;
+}
+
+void wifi_uap_set_httxcfg(const t_u16 ht_tx_cfg)
+{
+    wm_wifi.ht_tx_cfg = ht_tx_cfg;
+}
+
+#if CONFIG_WPA_SUPP
+/**
+ * @brief Get second channel offset
+ *
+ * @param chan            channel num
+ * @return                second channel offset
+ */
+t_u8 wlan_get_second_channel_offset(mlan_private *priv, int chan)
+{
+    t_u8 chan2Offset = SEC_CHAN_NONE;
+
+    /* Special Case: 20Mhz-only Channel */
+#if CONFIG_UNII4_BAND_SUPPORT
+    if (priv->adapter->region_code != COUNTRY_CODE_US && chan == 165)
+#else
+    if (chan == 165)
+#endif
+        return chan2Offset;
+
+    switch (chan)
+    {
+        case 36:
+        case 44:
+        case 52:
+        case 60:
+        case 100:
+        case 108:
+        case 116:
+        case 124:
+        case 132:
+        case 140:
+        case 149:
+        case 157:
+#if CONFIG_UNII4_BAND_SUPPORT
+        case 165:
+        case 173:
+#endif
+            chan2Offset = SEC_CHAN_ABOVE;
+            break;
+        case 40:
+        case 48:
+        case 56:
+        case 64:
+        case 104:
+        case 112:
+        case 120:
+        case 128:
+        case 136:
+        case 144:
+        case 153:
+        case 161:
+#if CONFIG_UNII4_BAND_SUPPORT
+        case 169:
+        case 177:
+#endif
+            chan2Offset = SEC_CHAN_BELOW;
+            break;
+    }
+    return chan2Offset;
+}
+
+t_u8 wifi_get_sec_channel_offset(unsigned int chan)
+{
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[1];
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u16 band;
+    t_u8 chan_offset;
+
+#if CONFIG_5GHz_SUPPORT
+    if (chan > MAX_CHANNELS_BG)
+    {
+        band = BAND_AN;
+    }
+    else
+    {
+        band = BAND_GN;
+    }
+#else
+    band = BAND_GN;
+#endif
+
+    chan_offset = SEC_CHAN_ABOVE;
+
+    if (band & BAND_GN)
+    {
+        if ((chan == 1) || (chan == 2) || (chan == 3) || (chan == 4))
+            chan_offset = SEC_CHAN_ABOVE;
+        else if ((chan == 10) || (chan == 11) || (chan == 12) || (chan == 13))
+            chan_offset = SEC_CHAN_BELOW;
+        else if (chan == 14)
+            chan_offset = SEC_CHAN_NONE;
+
+        /* check if channel 12 is supported in the region */
+        if (!wlan_find_cfp_by_band_and_channel(pmadapter, band, 12))
+            if ((chan == 8) || (chan == 9))
+                chan_offset = SEC_CHAN_BELOW;
+    }
+#if CONFIG_5GHz_SUPPORT
+    else if (band & BAND_AN)
+        chan_offset = wlan_get_second_channel_offset(pmpriv, chan);
+#endif
+
+    return chan_offset;
+}
+#endif
+
+#if CONFIG_WIFI_CAPA
+void wifi_uap_config_wifi_capa(uint8_t wlan_capa)
+{
+    if (wlan_capa & WIFI_SUPPORT_LEGACY)
+    {
+        if (wlan_capa & WIFI_SUPPORT_11N)
+        {
+            mlan_adap->usr_dot_11n_enable = MTRUE;
+#if CONFIG_11AC
+            if (wlan_capa & WIFI_SUPPORT_11AC)
+            {
+                mlan_adap->usr_dot_11ac_enable = MTRUE;
+#if CONFIG_11AX
+                if (wlan_capa & WIFI_SUPPORT_11AX)
+                {
+                    mlan_adap->usr_dot_11ax_enable = MTRUE;
+                }
+                else
+                {
+                    mlan_adap->usr_dot_11ax_enable = MFALSE;
+                }
+#endif
+            }
+            else
+#endif
+            {
+#if CONFIG_11AC
+                mlan_adap->usr_dot_11ac_enable = MFALSE;
+#endif
+#if CONFIG_11AX
+                mlan_adap->usr_dot_11ax_enable = MFALSE;
+#endif
+            }
+        }
+        else
+        {
+            mlan_adap->usr_dot_11n_enable = MFALSE;
+#if CONFIG_11AC
+            mlan_adap->usr_dot_11ac_enable = MFALSE;
+#endif
+#if CONFIG_11AX
+            mlan_adap->usr_dot_11ax_enable = MFALSE;
+#endif
+        }
+    }
+    else
+    {
+        wuap_e("Invalid wifi capaibility setting\n");
+    }
+    return;
+}
+#endif
+
+int wifi_uap_start(mlan_bss_type type,
+                   char *ssid,
+                   uint8_t *mac_addr,
+                   int security,
+                   int key_mgmt,
+                   char *passphrase,
+                   char *password,
+                   int channel,
+                   wifi_scan_chan_list_t scan_chan_list,
+                   uint8_t pwe_derivation,
+                   uint8_t transition_disable,
+                   bool mfpc,
+#if CONFIG_WIFI_DTIM_PERIOD
+                   bool mfpr,
+                   uint8_t dtim
+#else
+                   bool mfpr
+#endif
+)
+{
+    wuap_d("Configuring");
+#if CONFIG_11AC
+    if ((BANDWIDTH_80MHZ == wm_wifi.bandwidth) && (channel <= MAX_CHANNELS_BG) && (channel != 0))
+    {
+        wuap_e(
+            "Cannot start uAP if bandwidth is configured to 80MHz, "
+            "while channel is selected automatically or set to less than %d.",
+            MAX_CHANNELS_BG);
+        return -WM_FAIL;
+    }
+    else
+    {
+        /** Do Nothing */
+    }
+#endif
+    if (channel == 14 || channel == 165)
+    {
+        wm_wifi.bandwidth = BANDWIDTH_20MHZ;
+    }
+
+    /* Configure SSID */
+    int rv = wifi_cmd_uap_config(ssid, mac_addr, (enum wlan_security_type)security, key_mgmt, passphrase, password,
+                                 (t_u8)channel, scan_chan_list, pwe_derivation, transition_disable,
+                                 wm_wifi.beacon_period == 0U ? UAP_BEACON_PERIOD : wm_wifi.beacon_period,
+                                 wm_wifi.bandwidth == 0U ? BANDWIDTH_40MHZ : wm_wifi.bandwidth,
+#if CONFIG_WIFI_DTIM_PERIOD
+                                 dtim == 0 ? UAP_DTIM_PERIOD : dtim,
+#else
+                                 UAP_DTIM_PERIOD,
+#endif
+                                 wm_wifi.chan_sw_count, type, mfpc, mfpr);
+
+    if (rv != WM_SUCCESS)
+    {
+        wuap_e("config failed. Cannot start");
+        return rv;
+    }
+
+    if ((security == WLAN_SECURITY_WPA2 || security == WLAN_SECURITY_WPA_WPA2_MIXED ||
+         security == WLAN_SECURITY_WPA3_SAE || security == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED
+#if CONFIG_DRIVER_OWE
+         || security == WLAN_SECURITY_OWE_ONLY
+#endif
+         ))
+    {
+        (void)wifi_uap_pmf_getset(HostCmd_ACT_GEN_SET, (uint8_t *)&mfpc, (uint8_t *)&mfpr);
+    }
+
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    mlan_private *remain_priv = pmpriv->adapter->priv[pmpriv->adapter->remain_bss_index];
+    if (wifi_is_remain_on_channel() && remain_priv)
+    {
+        wuap_d("Cancel Remain on Channel before Starting AP");
+        wifi_remain_on_channel(false, 0, 0);
+    }
+
+    if (wm_wifi.enable_11d_support && wm_wifi.uap_support_11d_apis)
+    {
+        wuap_d("Downloading domain params");
+        wm_wifi.uap_support_11d_apis->wifi_uap_downld_domain_params_p(BAND_B);
+#if CONFIG_5GHz_SUPPORT
+        wm_wifi.uap_support_11d_apis->wifi_uap_downld_domain_params_p(BAND_A);
+#endif
+    }
+
+    wuap_d("Starting BSS");
+    /* Start BSS */
+    return wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_BSS_START, HostCmd_ACT_GEN_SET, 0, NULL, NULL, type,
+                                         NULL);
+}
+
+int wifi_uap_bss_sta_list(wifi_sta_list_t **list)
+{
+    if (list == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+
+    /* Start BSS */
+    return wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_STA_LIST, HostCmd_ACT_GEN_GET, 0, NULL, NULL,
+                                         MLAN_BSS_TYPE_UAP, list);
+
+    /* *list must have been filled now if everything went well */
+}
+
+
+int wifi_sta_deauth(uint8_t *mac_addr, uint16_t reason_code)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    mlan_deauth_param deauth;
+
+    if (mac_addr == MNULL)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memcpy((void *)deauth.mac_addr, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+    deauth.reason_code = reason_code;
+
+    if (pmpriv->media_connected == MFALSE)
+    {
+        return -WM_FAIL;
+    }
+
+    /* Start BSS */
+    return wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_STA_DEAUTH, HostCmd_ACT_GEN_SET, 0, NULL, &deauth,
+                                         MLAN_BSS_TYPE_UAP, NULL);
+}
+
+int wifi_uap_stop()
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    int rv               = 0;
+
+    /* Start BSS */
+    rv = wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_BSS_STOP, HostCmd_ACT_GEN_SET, 0, NULL, NULL,
+                                       MLAN_BSS_TYPE_UAP, NULL);
+    wifi_uap_clear_domain_info();
+
+    return rv;
+}
+
+#ifdef SD8801
+static int wifi_uap_acs_config_set()
+{
+    uint8_t i     = 0;
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_ACS_CONFIG) - 1U;
+    uint8_t active_chan_list[40];
+    uint8_t active_num_chans                      = 0;
+    MrvlIEtypes_ChanListParamSet_t *tlv_chan_list = NULL;
+    HostCmd_DS_COMMAND *cmd;
+
+    wifi_get_active_channel_list(active_chan_list, &active_num_chans, 0);
+
+    (void)wifi_get_command_lock();
+
+    cmd = wifi_get_command_buffer();
+
+    memset(cmd, 0x00, size);
+
+    cmd->command                   = wlan_cpu_to_le16(HostCmd_MMH_ACS_CFG);
+    HostCmd_DS_ACS_CONFIG *acs_cmd = (HostCmd_DS_ACS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    uint8_t *tlv                   = acs_cmd->tlv_buffer;
+
+    tlv_chan_list = (MrvlIEtypes_ChanListParamSet_t *)(void *)tlv;
+
+    memset(tlv_chan_list, 0x00, sizeof(MrvlIEtypesHeader_t) + active_num_chans * sizeof(ChanScanParamSet_t));
+
+    tlv_chan_list->header.type = TLV_TYPE_CHANLIST;
+    tlv_chan_list->header.len  = active_num_chans * sizeof(ChanScanParamSet_t);
+
+    for (i = 0; i < active_num_chans; i++)
+    {
+        tlv_chan_list->chan_scan_param[i].chan_number   = active_chan_list[i];
+        tlv_chan_list->chan_scan_param[i].min_scan_time = MRVDRV_ACTIVE_SCAN_CHAN_TIME;
+        tlv_chan_list->chan_scan_param[i].max_scan_time = MRVDRV_ACTIVE_SCAN_CHAN_TIME;
+    }
+
+    size += sizeof(tlv_chan_list->header) + tlv_chan_list->header.len;
+
+    cmd->size    = (t_u16)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(NULL);
+
+    return WM_SUCCESS;
+}
+#endif
+
+#if CONFIG_WPA_SUPP_AP
+int wifi_uap_do_acs(const int *freq_list)
+#else
+int wifi_uap_do_acs(const int *freq_list, const t_u16 acs_band)
+#endif
+{
+#ifndef SD8801
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+#endif
+    MrvlIEtypes_channel_band_t *tlv_chan_band     = MNULL;
+    MrvlIEtypes_ChanListParamSet_t *tlv_chan_list = MNULL;
+    ChanScanParamSet_t *pscan_chan                = MNULL;
+    t_u8 *tlv                                     = MNULL;
+    uint8_t active_chan_list[WIFI_MAX_CHANNEL_NUM];
+    uint8_t active_num_chans = 0;
+    t_u16 scan_chan_num      = 0;
+    t_u16 cmd_size;
+    int i;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd           = wifi_get_command_buffer();
+    HostCmd_DS_SYS_CONFIG *sys_config = (HostCmd_DS_SYS_CONFIG *)&cmd->params.sys_config;
+
+    cmd->command       = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    cmd->seq_num       = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, MLAN_BSS_TYPE_UAP);
+    cmd->result        = 0x00;
+    sys_config->action = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
+    cmd_size           = sizeof(HostCmd_DS_SYS_CONFIG) - 1 + S_DS_GEN;
+
+    /* set band config tlv */
+    tlv                        = (t_u8 *)sys_config->tlv_buffer;
+    tlv_chan_band              = (MrvlIEtypes_channel_band_t *)tlv;
+    tlv_chan_band->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_CHAN_BAND_CONFIG);
+    tlv_chan_band->header.len  = wlan_cpu_to_le16(sizeof(t_u8) + sizeof(t_u8));
+    tlv_chan_band->band_config = BAND_CONFIG_ACS_MODE;
+    tlv_chan_band->channel     = 0;
+    cmd_size += sizeof(MrvlIEtypes_channel_band_t);
+    tlv += sizeof(MrvlIEtypes_channel_band_t);
+
+    /* set scan channel list tlv */
+    tlv_chan_list              = (MrvlIEtypes_ChanListParamSet_t *)tlv;
+    tlv_chan_list->header.type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
+    pscan_chan                 = tlv_chan_list->chan_scan_param;
+
+    /* fill in scan channel list */
+    if (freq_list && freq_list[0] != 0)
+    {
+        /* use hostapd channel list */
+        for (i = 0; i < WIFI_MAX_CHANNEL_NUM; i++)
+        {
+            if (freq_list[i] == 0)
+                break;
+            /* Following condition occurs in JP region where CH14 is allowed only in b mode.
+             * But now we already have asked hostAPD to start with HT/VHT/HE modes, CH14 will not work here.
+             * To avoid this, CH14 is omitted in ACS scan. Manual start of uAP in CH 14 is expected to use CH14 in JP region.
+             */
+            if (i == 13)
+                continue;
+            (void)memset(pscan_chan, 0x00, sizeof(ChanScanParamSet_t));
+            pscan_chan->chan_number = freq_to_chan(freq_list[i]);
+            pscan_chan->radio_type  = freq_list[i] >= 5180 ? BAND_5GHZ : BAND_2GHZ;
+            pscan_chan++;
+        }
+        scan_chan_num = i;
+        /* Following condition occurs in JP region where CH14 is allowed only in b mode.
+         * But now we already have asked hostAPD to start with HT/VHT/HE modes, CH14 will not work here.
+         * To avoid this, CH14 is omitted in ACS scan. Manual start of uAP in CH 14 is expected to use CH14 in JP region.
+         */
+        if (scan_chan_num == 14)
+            scan_chan_num = 13;
+    }
+    else
+    {
+        /* create our own scan channel list on default 2.4G, as error protection */
+#if CONFIG_WPA_SUPP_AP
+        wifi_get_active_channel_list(active_chan_list, &active_num_chans, BAND_2GHZ);
+#else
+        wifi_get_active_channel_list(active_chan_list, &active_num_chans, acs_band);
+#endif
+
+        if (active_num_chans != 0 && active_num_chans < WIFI_MAX_CHANNEL_NUM)
+        {
+            for (i = 0; i < active_num_chans; i++)
+            {
+                (void)memset(pscan_chan, 0x00, sizeof(ChanScanParamSet_t));
+                pscan_chan->chan_number = active_chan_list[i];
+                pscan_chan->radio_type  = BAND_2GHZ;
+                pscan_chan++;
+            }
+            scan_chan_num = active_num_chans;
+        }
+    }
+
+    tlv_chan_list->header.len = wlan_cpu_to_le16(scan_chan_num * sizeof(ChanScanParamSet_t));
+    cmd_size += sizeof(tlv_chan_list->header) + (scan_chan_num * sizeof(ChanScanParamSet_t));
+    tlv += sizeof(tlv_chan_list->header) + (scan_chan_num * sizeof(ChanScanParamSet_t));
+
+    cmd->size = (t_u16)wlan_cpu_to_le16(cmd_size);
+
+    wifi_wait_for_cmdresp(NULL);
+
+    /* Start ACS SCAN */
+#ifdef SD8801
+    return wifi_uap_acs_config_set();
+#else
+    return wifi_uap_prepare_and_send_cmd(pmpriv, HostCMD_APCMD_ACS_SCAN, HostCmd_ACT_GEN_SET, 0, NULL, NULL,
+                                         MLAN_BSS_TYPE_UAP, NULL);
+#endif
+}
+
+#if CONFIG_WIFI_UAP_WORKAROUND_STICKY_TIM
+/*
+ * The following configuration was added because of a particular
+ * bug on 8787 and 8782 firmware. The firmware bugzilla ID for the
+ * bug is 39609. The bug causes the firmware to send packets to the
+ * STA even after giving ACK for IEEE PS. The prov. mode scanning
+ * coupled with this bug causes large scale packet losses and TCP
+ * backoffs finally resulting in long load times for HTTP served
+ * pages for prov. UI.
+ */
+
+/** TLV header length */
+#define TLVHEADER_LEN 4
+
+#define MRVL_STICKY_TIM_CONFIG_TLV_ID (PROPRIETARY_TLV_BASE_ID + 0x96)
+/** TLV : Sticky TIM MAC address */
+#define MRVL_STICKY_TIM_STA_MAC_ADDR_TLV_ID (PROPRIETARY_TLV_BASE_ID + 0x97)
+
+/** TLV buffer : sticky tim config */
+typedef PACK_START struct _tlvbuf_sticky_tim_config
+{
+    /** Header */
+    t_u16 tag;
+    /** Length */
+    t_u16 length;
+    /** Enable */
+    t_u16 enable;
+    /** Duration */
+    t_u16 duration;
+    /** Sticky Bitmask */
+    t_u16 sticky_bitmask;
+} PACK_END tlvbuf_sticky_tim_config;
+
+/** TLV buffer : sticky tim sta mac address */
+typedef PACK_START struct _tlvbuf_sticky_tim_sta_mac_addr
+{
+    /** Header */
+    t_u16 tag;
+    /** Length */
+    t_u16 length;
+    /** Control */
+    t_u16 control;
+    /** Station MAC address */
+    t_u8 sta_mac_address[MLAN_MAC_ADDR_LENGTH];
+} PACK_END tlvbuf_sticky_tim_sta_mac_addr;
+
+/*
+ * This configures sticky TIM configuration for given MAC.
+ *
+ * Note that this is not present in mlan. So we have to add it here.
+ */
+void wifi_uap_enable_sticky_bit(const uint8_t *mac_addr)
+{
+    static bool global_sticky_enabled;
+
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1;
+
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    sys_config_cmd->action                = HostCmd_ACT_GEN_SET;
+    uint8_t *tlv                          = sys_config_cmd->tlv_buffer;
+
+    if (!global_sticky_enabled)
+    {
+        /*
+         * This enables the global sticky TIM bit enable. This
+         * needs to be done only once.
+         */
+        tlvbuf_sticky_tim_config *tlv_sticky_tim_cfg = (tlvbuf_sticky_tim_config *)tlv;
+
+        tlv_sticky_tim_cfg->tag    = MRVL_STICKY_TIM_CONFIG_TLV_ID;
+        tlv_sticky_tim_cfg->length = sizeof(tlvbuf_sticky_tim_config) - TLVHEADER_LEN;
+        tlv_sticky_tim_cfg->enable = 1;
+        /* Set it permanently */
+        tlv_sticky_tim_cfg->duration = 0;
+        /* MoreData bit and TIM bit is made sticky */
+        tlv_sticky_tim_cfg->sticky_bitmask = (t_u16)0x3;
+
+        size += sizeof(MrvlIEtypesHeader_t) + tlv_sticky_tim_cfg->length;
+        tlv += sizeof(MrvlIEtypesHeader_t) + tlv_sticky_tim_cfg->length;
+
+        global_sticky_enabled = true;
+    }
+
+    tlvbuf_sticky_tim_sta_mac_addr *tim_cfg = (tlvbuf_sticky_tim_sta_mac_addr *)tlv;
+
+    tim_cfg->tag    = MRVL_STICKY_TIM_STA_MAC_ADDR_TLV_ID;
+    tim_cfg->length = sizeof(tlvbuf_sticky_tim_sta_mac_addr) - TLVHEADER_LEN;
+    (void)memcpy((void *)tim_cfg->sta_mac_address, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+    tim_cfg->control = 1;
+
+    size += sizeof(MrvlIEtypesHeader_t) + tim_cfg->length;
+
+    cmd->size    = size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    wifi_wait_for_cmdresp(NULL);
+}
+#endif /* CONFIG_WIFI_UAP_WORKAROUND_STICKY_TIM */
+
+/*
+ * Note: This function handles only one (first) TLV from the response.
+ */
+void wifi_uap_handle_cmd_resp(HostCmd_DS_COMMAND *resp)
+{
+    mlan_private *pmpriv              = (mlan_private *)mlan_adap->priv[1];
+    HostCmd_DS_SYS_CONFIG *sys_config = (HostCmd_DS_SYS_CONFIG *)&resp->params.sys_config;
+    uint8_t *tlv                      = sys_config->tlv_buffer;
+    MrvlIEtypesHeader_t *header       = (MrvlIEtypesHeader_t *)(void *)tlv;
+    if (resp->result == 0U)
+    {
+        switch (header->type)
+        {
+            case TLV_TYPE_UAP_TX_POWER:
+            {
+                MrvlIEtypes_tx_power_t *tlv_tx_power = (MrvlIEtypes_tx_power_t *)(void *)tlv;
+                if (sys_config->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint8_t *tx_power     = (uint8_t *)wm_wifi.cmd_resp_priv;
+                        wm_wifi.cmd_resp_priv = NULL;
+                        *tx_power             = tlv_tx_power->tx_power;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case TLV_TYPE_UAP_STA_AGEOUT_TIMER:
+            {
+                MrvlIEtypes_sta_ageout_t *tlv_sta_ageout_timer = (MrvlIEtypes_sta_ageout_t *)(void *)tlv;
+                if (sys_config->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *sta_ageout_timer = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        wm_wifi.cmd_resp_priv      = NULL;
+                        *sta_ageout_timer          = tlv_sta_ageout_timer->sta_ageout_timer;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case TLV_TYPE_UAP_PS_STA_AGEOUT_TIMER:
+            {
+                MrvlIEtypes_ps_sta_ageout_t *tlv_ps_sta_ageout_timer = (MrvlIEtypes_ps_sta_ageout_t *)(void *)tlv;
+                if (sys_config->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *ps_sta_ageout_timer = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        wm_wifi.cmd_resp_priv         = NULL;
+                        *ps_sta_ageout_timer          = tlv_ps_sta_ageout_timer->ps_sta_ageout_timer;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case TLV_TYPE_UAP_GRP_REKEY_TIME:
+            {
+                MrvlIEtypes_group_rekey_time_t *tlv_group_rekey_timer = (MrvlIEtypes_group_rekey_time_t *)(void *)tlv;
+                if (sys_config->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint32_t *group_rekey_timer = (uint32_t *)wm_wifi.cmd_resp_priv;
+                        wm_wifi.cmd_resp_priv       = NULL;
+                        *group_rekey_timer          = tlv_group_rekey_timer->gk_rekey_time;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case TLV_TYPE_UAP_MCBC_DATA_RATE:
+            {
+                MrvlIEtypes_mcbc_rate_t *tlv_mcbc_rate = (MrvlIEtypes_mcbc_rate_t *)(void *)tlv;
+                if (sys_config->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        uint16_t *mcbc_rate   = (uint16_t *)wm_wifi.cmd_resp_priv;
+                        wm_wifi.cmd_resp_priv = NULL;
+                        *mcbc_rate            = tlv_mcbc_rate->mcbc_data_rate;
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case TLV_TYPE_RATES:
+            {
+                MrvlIEtypes_RatesParamSet_t *tlv_rates = (MrvlIEtypes_RatesParamSet_t *)(void *)tlv;
+
+                if (sys_config->action == HostCmd_ACT_GEN_GET)
+                {
+                    if (wm_wifi.cmd_resp_priv != NULL)
+                    {
+                        char *rates           = (char *)wm_wifi.cmd_resp_priv;
+                        wm_wifi.cmd_resp_priv = NULL;
+                        (void)memset((void *)rates, 0, MAX_RATES);
+                        (void)memcpy((void *)rates, (const void *)tlv_rates->rates,
+                                     MIN(MAX_RATES, tlv_rates->header.len));
+                    }
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case TLV_TYPE_UAP_CHAN_BAND_CONFIG:
+            {
+                MrvlIEtypes_channel_band_t *tlv_cb    = (MrvlIEtypes_channel_band_t *)(void *)tlv;
+                pmpriv->uap_state_chan_cb.band_config = tlv_cb->band_config;
+                pmpriv->uap_state_chan_cb.channel     = tlv_cb->channel;
+                if (wm_wifi.cmd_resp_priv != NULL)
+                {
+                    t_u8 *channel         = (t_u8 *)wm_wifi.cmd_resp_priv;
+                    wm_wifi.cmd_resp_priv = NULL;
+                    *channel              = tlv_cb->channel;
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            case TLV_TYPE_UAP_MAX_STA_CNT:
+            {
+                MrvlIEtypes_max_sta_count_t *tlv_sta_cnt = (MrvlIEtypes_max_sta_count_t *)(void *)tlv;
+                pmpriv->uap_state_chan_cb.max_sta_count  = tlv_sta_cnt->max_sta_count;
+                pmpriv->uap_max_sta                      = tlv_sta_cnt->max_sta_count;
+                if (wm_wifi.cmd_resp_priv != NULL)
+                {
+                    int *sta_count        = (int *)wm_wifi.cmd_resp_priv;
+                    wm_wifi.cmd_resp_priv = NULL;
+                    *sta_count            = (int)tlv_sta_cnt->max_sta_count;
+                }
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+            }
+            break;
+            default:
+                wm_wifi.cmd_resp_status = WM_SUCCESS;
+                break;
+        }
+    }
+    else
+    {
+        wm_wifi.cmd_resp_status = -WM_FAIL;
+    }
+}
+
+int wifi_uap_rates_getset(uint8_t action, char *rates, uint8_t num_rates)
+{
+    uint8_t i     = 0;
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    uint8_t *tlv                          = sys_config_cmd->tlv_buffer;
+
+    MrvlIEtypes_RatesParamSet_t *tlv_rates = (MrvlIEtypes_RatesParamSet_t *)(void *)tlv;
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_GET;
+    }
+    else
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_SET;
+        for (i = 0; i < num_rates; i++)
+        {
+            tlv_rates->rates[i] = (t_u8)rates[i];
+        }
+    }
+
+    tlv_rates->header.type = wlan_cpu_to_le16(TLV_TYPE_RATES);
+    tlv_rates->header.len  = wlan_cpu_to_le16(i);
+
+    size += sizeof(MrvlIEtypesHeader_t) + i;
+    tlv += sizeof(MrvlIEtypesHeader_t) + i;
+
+    cmd->size    = (t_u16)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? rates : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_uap_mcbc_rate_getset(uint8_t action, uint16_t *mcbc_rate)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    uint8_t *tlv                          = sys_config_cmd->tlv_buffer;
+
+    MrvlIEtypes_mcbc_rate_t *tlv_mcbc_rate = (MrvlIEtypes_mcbc_rate_t *)(void *)tlv;
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_GET;
+    }
+    else
+    {
+        sys_config_cmd->action        = HostCmd_ACT_GEN_SET;
+        tlv_mcbc_rate->mcbc_data_rate = *mcbc_rate;
+    }
+
+    tlv_mcbc_rate->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_MCBC_DATA_RATE);
+    tlv_mcbc_rate->header.len  = wlan_cpu_to_le16(sizeof(t_u16));
+
+    size += sizeof(MrvlIEtypes_mcbc_rate_t);
+    tlv += sizeof(MrvlIEtypes_mcbc_rate_t);
+
+    cmd->size    = (t_u16)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? mcbc_rate : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_uap_tx_power_getset(uint8_t action, uint8_t *tx_power_dbm)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    uint8_t *tlv                          = sys_config_cmd->tlv_buffer;
+
+    MrvlIEtypes_tx_power_t *tlv_tx_power = (MrvlIEtypes_tx_power_t *)(void *)tlv;
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_GET;
+    }
+    else
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_SET;
+        tlv_tx_power->tx_power = *tx_power_dbm;
+    }
+    tlv_tx_power->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_TX_POWER);
+    tlv_tx_power->header.len  = wlan_cpu_to_le16(sizeof(t_u8));
+
+    size += sizeof(MrvlIEtypes_tx_power_t);
+    tlv += sizeof(MrvlIEtypes_tx_power_t);
+
+    cmd->size    = (uint16_t)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? tx_power_dbm : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_uap_sta_ageout_timer_getset(uint8_t action, uint32_t *sta_ageout_timer)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    uint8_t *tlv                          = sys_config_cmd->tlv_buffer;
+
+    MrvlIEtypes_sta_ageout_t *tlv_sta_ageout_timer = (MrvlIEtypes_sta_ageout_t *)(void *)tlv;
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_GET;
+    }
+    else
+    {
+        sys_config_cmd->action                 = HostCmd_ACT_GEN_SET;
+        tlv_sta_ageout_timer->sta_ageout_timer = wlan_cpu_to_le32(*sta_ageout_timer);
+    }
+    tlv_sta_ageout_timer->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_STA_AGEOUT_TIMER);
+    tlv_sta_ageout_timer->header.len  = wlan_cpu_to_le16(sizeof(t_u32));
+
+    size += sizeof(MrvlIEtypes_sta_ageout_t);
+    tlv += sizeof(MrvlIEtypes_sta_ageout_t);
+
+    cmd->size    = (t_u16)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? sta_ageout_timer : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_uap_ps_sta_ageout_timer_getset(uint8_t action, uint32_t *ps_sta_ageout_timer)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    uint8_t *tlv                          = sys_config_cmd->tlv_buffer;
+
+    MrvlIEtypes_ps_sta_ageout_t *tlv_ps_sta_ageout_timer = (MrvlIEtypes_ps_sta_ageout_t *)(void *)tlv;
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_GET;
+    }
+    else
+    {
+        sys_config_cmd->action                       = HostCmd_ACT_GEN_SET;
+        tlv_ps_sta_ageout_timer->ps_sta_ageout_timer = wlan_cpu_to_le32(*ps_sta_ageout_timer);
+    }
+    tlv_ps_sta_ageout_timer->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_PS_STA_AGEOUT_TIMER);
+    tlv_ps_sta_ageout_timer->header.len  = wlan_cpu_to_le16(sizeof(t_u32));
+
+    size += sizeof(MrvlIEtypes_ps_sta_ageout_t);
+    tlv += sizeof(MrvlIEtypes_ps_sta_ageout_t);
+
+    cmd->size    = (uint16_t)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? ps_sta_ageout_timer : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+int wifi_uap_group_rekey_timer_getset(uint8_t action, uint32_t *group_rekey_timer)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_SYS_CONFIG) - 1U;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HOST_CMD_APCMD_SYS_CONFIGURE);
+    HostCmd_DS_SYS_CONFIG *sys_config_cmd = (HostCmd_DS_SYS_CONFIG *)((uint32_t)cmd + S_DS_GEN);
+    uint8_t *tlv                          = sys_config_cmd->tlv_buffer;
+
+    MrvlIEtypes_group_rekey_time_t *tlv_group_rekey_timer = (MrvlIEtypes_group_rekey_time_t *)(void *)tlv;
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        sys_config_cmd->action = HostCmd_ACT_GEN_GET;
+    }
+    else
+    {
+        sys_config_cmd->action               = HostCmd_ACT_GEN_SET;
+        tlv_group_rekey_timer->gk_rekey_time = wlan_cpu_to_le32(*group_rekey_timer);
+    }
+    tlv_group_rekey_timer->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_GRP_REKEY_TIME);
+    tlv_group_rekey_timer->header.len  = wlan_cpu_to_le16(sizeof(t_u32));
+
+    size += sizeof(MrvlIEtypes_group_rekey_time_t);
+    tlv += sizeof(MrvlIEtypes_group_rekey_time_t);
+
+    cmd->size    = (t_u16)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? group_rekey_timer : NULL);
+
+    return wm_wifi.cmd_resp_status;
+}
+
+/* Content reproduced from wlan_uap_get_channel() */
+static int wifi_send_uap_get_channel_cmd(int *channel)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    t_u16 tlv_type       = TLV_TYPE_UAP_CHAN_BAND_CONFIG;
+
+    int rv = wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_SYS_CONFIGURE, HostCmd_ACT_GEN_GET, 0, MNULL,
+                                           &tlv_type, MLAN_BSS_TYPE_UAP, channel);
+    if (rv != WM_SUCCESS)
+    {
+        return rv;
+    }
+
+    if (wm_wifi.cmd_resp_status != 0)
+    {
+        wifi_w("Unable to uap channel");
+        return wm_wifi.cmd_resp_status;
+    }
+
+    return rv;
+}
+
+/* Content reproduced from wlan_uap_get_channel() */
+static int wifi_send_uap_max_sta_num_cmd(uint8_t action, unsigned int *max_sta_num)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    MrvlIEtypes_max_sta_count_t max_sta_count_tlv;
+
+    (void)memset(&max_sta_count_tlv, 0, sizeof(MrvlIEtypes_max_sta_count_t));
+
+    max_sta_count_tlv.header.type = TLV_TYPE_UAP_MAX_STA_CNT;
+
+    if (action == HostCmd_ACT_GEN_SET)
+    {
+        max_sta_count_tlv.header.len    = (t_u16)sizeof(MrvlIEtypes_max_sta_count_t);
+        max_sta_count_tlv.max_sta_count = (t_u16)*max_sta_num;
+    }
+
+    int rv = wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_SYS_CONFIGURE, action, 0, MNULL, &max_sta_count_tlv,
+                                           MLAN_BSS_TYPE_UAP, max_sta_num);
+    if (rv != WM_SUCCESS)
+    {
+        return rv;
+    }
+
+    if (wm_wifi.cmd_resp_status != 0)
+    {
+        wifi_w("Unable to uap max_sta_num");
+        return wm_wifi.cmd_resp_status;
+    }
+
+    return rv;
+}
+
+int wifi_get_uap_max_clients(unsigned int *max_sta_num)
+{
+    return wifi_send_uap_max_sta_num_cmd(HostCmd_ACT_GEN_GET, max_sta_num);
+}
+
+int wifi_set_uap_max_clients(unsigned int *max_sta_num)
+{
+    return wifi_send_uap_max_sta_num_cmd(HostCmd_ACT_GEN_SET, max_sta_num);
+}
+
+/*
+ * Note: channel can be NULL. The side effects of this function also are of
+ * interest to us as pmpriv->uap_state_chan_cb.band_config and
+ * pmpriv->uap_state_chan_cb.channel are updated.
+ */
+int wifi_get_uap_channel(int *channel)
+{
+    return wifi_send_uap_get_channel_cmd(channel);
+}
+
+int wifi_uap_pmf_getset(uint8_t action, uint8_t *mfpc, uint8_t *mfpr)
+{
+    uint32_t size = S_DS_GEN + sizeof(HostCmd_DS_PMF_PARAMS);
+    wifi_pmf_params_t wifi_pmf_params;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    cmd->command                          = wlan_cpu_to_le16(HostCmd_CMD_PMF_PARAMS);
+    HostCmd_DS_PMF_PARAMS *sys_pmf_params = (HostCmd_DS_PMF_PARAMS *)((uint32_t)cmd + S_DS_GEN);
+
+    (void)memset(sys_pmf_params, 0x00, sizeof(HostCmd_DS_PMF_PARAMS));
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        sys_pmf_params->action = HostCmd_ACT_GEN_GET;
+    }
+    else
+    {
+        sys_pmf_params->action = HostCmd_ACT_GEN_SET;
+    }
+
+    sys_pmf_params->params.mfpc = *mfpc;
+    sys_pmf_params->params.mfpr = *mfpr;
+
+    cmd->size    = (t_u16)size;
+    cmd->seq_num = (0x01) << 12;
+    cmd->result  = 0x00;
+
+    (void)wifi_wait_for_cmdresp(action == HostCmd_ACT_GEN_GET ? &wifi_pmf_params : NULL);
+
+    if (action == HostCmd_ACT_GEN_GET)
+    {
+        *mfpc = wifi_pmf_params.mfpc;
+        *mfpr = wifi_pmf_params.mfpr;
+    }
+
+    return wm_wifi.cmd_resp_status;
+}
+
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+int wifi_set_sta_mac_filter(int filter_mode, int mac_count, unsigned char *mac_addr)
+{
+    t_u8 *buffer  = NULL;
+    t_u16 cmd_len = 0;
+    t_u16 buf_len = MRVDRV_SIZE_OF_CMD_BUFFER;
+
+    HostCmd_DS_GEN *cmd_buf           = NULL;
+    MrvlIEtypes_mac_filter_t *tlv     = NULL;
+    HostCmd_DS_SYS_CONFIG *sys_config = NULL;
+
+    /* Initialize the command length */
+    if (filter_mode == 0)
+    {
+        cmd_len = sizeof(HostCmd_DS_GEN) + (sizeof(HostCmd_DS_SYS_CONFIG) - 1) +
+                  (sizeof(MrvlIEtypes_mac_filter_t) - 1) + (WLAN_MAX_STA_FILTER_NUM * MLAN_MAC_ADDR_LENGTH);
+    }
+    else
+    {
+        cmd_len = sizeof(HostCmd_DS_GEN) + (sizeof(HostCmd_DS_SYS_CONFIG) - 1) +
+                  (sizeof(MrvlIEtypes_mac_filter_t) - 1) + mac_count * MLAN_MAC_ADDR_LENGTH;
+    }
+
+    /* Initialize the command buffer */
+#if !CONFIG_MEM_POOLS
+    buffer = (t_u8 *)OSA_MemoryAllocate(buf_len);
+#else
+    buffer = (t_u8 *)OSA_MemoryPoolAllocate(buf_2048_MemoryPool);
+#endif
+    if (!buffer)
+    {
+        wuap_e("ERR:Cannot allocate buffer for command!\r\n");
+        return -WM_FAIL;
+    }
+
+    memset(buffer, 0, buf_len);
+
+    /* Locate headers */
+    cmd_buf    = (HostCmd_DS_GEN *)buffer;
+    sys_config = (HostCmd_DS_SYS_CONFIG *)(buffer + sizeof(HostCmd_DS_GEN));
+    tlv        = (MrvlIEtypes_mac_filter_t *)(buffer + sizeof(HostCmd_DS_GEN) + (sizeof(HostCmd_DS_SYS_CONFIG) - 1));
+
+    /* Fill the command buffer */
+    cmd_buf->command = HOST_CMD_APCMD_SYS_CONFIGURE;
+    cmd_buf->size    = cmd_len;
+    cmd_buf->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, MLAN_BSS_TYPE_UAP);
+    cmd_buf->result  = 0;
+
+    sys_config->action = HostCmd_ACT_GEN_SET;
+
+    tlv->count       = mac_count;
+    tlv->filter_mode = filter_mode;
+    tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_UAP_STA_MAC_ADDR_FILTER);
+
+    if (tlv->count)
+    {
+        tlv->header.len = tlv->count * MLAN_MAC_ADDR_LENGTH + 2;
+        (void)memcpy(tlv->mac_address, mac_addr, mac_count * MLAN_MAC_ADDR_LENGTH);
+    }
+    else
+    {
+        tlv->header.len = WLAN_MAX_STA_FILTER_NUM * MLAN_MAC_ADDR_LENGTH + 2;
+    }
+
+    if (is_uap_started())
+    {
+        wuap_e("down the uap before setting sta filter\n\r");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buffer);
+#else
+        OSA_MemoryPoolFree(buf_2048_MemoryPool, buffer);
+#endif
+        return -WM_FAIL;
+    }
+
+    wifi_get_command_lock();
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memcpy((t_u8 *)cmd, cmd_buf, cmd_len);
+
+    wifi_wait_for_cmdresp(NULL);
+
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buffer);
+#else
+        OSA_MemoryPoolFree(buf_2048_MemoryPool, buffer);
+#endif
+
+    return WM_SUCCESS;
+}
+
+#endif
+
+#if CONFIG_WPA_SUPP_AP
+
+void wifi_uap_client_assoc(t_u8 *sta_addr, unsigned char is_11n_enabled)
+{
+    wlan_request_ralist_lock(mlan_adap->priv[1]);
+    /* Clear corresponding tx/rx table if necessary */
+    if (wlan_11n_get_txbastream_tbl((mlan_private *)mlan_adap->priv[1], sta_addr))
+    {
+        wlan_11n_delete_txbastream_tbl_entry((mlan_private *)mlan_adap->priv[1], sta_addr);
+    }
+
+    wlan_cleanup_reorder_tbl((mlan_private *)mlan_adap->priv[1], sta_addr);
+#if CONFIG_WMM
+    wlan_ralist_del_enh(mlan_adap->priv[1], sta_addr);
+#endif
+    /* txbastream table also is used as connected STAs data base */
+    wlan_11n_create_txbastream_tbl((mlan_private *)mlan_adap->priv[1], sta_addr, BA_STREAM_NOT_SETUP);
+    wlan_11n_update_txbastream_tbl_tx_thresh((mlan_private *)mlan_adap->priv[1], sta_addr, 3);
+
+    if (is_11n_enabled)
+    {
+        wlan_11n_update_txbastream_tbl_ampdu_supported((mlan_private *)mlan_adap->priv[1], sta_addr, MTRUE);
+    }
+
+    wlan_release_ralist_lock(mlan_adap->priv[1]);
+
+
+#if CONFIG_WMM
+    wlan_ralist_add_enh(mlan_adap->priv[1], sta_addr);
+#endif
+}
+
+void wifi_uap_client_deauth(t_u8 *sta_addr)
+{
+    if ((mlan_private *)mlan_adap->priv[1]->is_11n_enabled)
+    {
+        wlan_cleanup_reorder_tbl((mlan_private *)mlan_adap->priv[1], sta_addr);
+        wlan_request_ralist_lock((mlan_private *)mlan_adap->priv[1]);
+        wlan_11n_delete_txbastream_tbl_entry((mlan_private *)mlan_adap->priv[1], sta_addr);
+        wlan_release_ralist_lock((mlan_private *)mlan_adap->priv[1]);
+    }
+
+#if CONFIG_WMM
+    wlan_ralist_del_enh(mlan_adap->priv[1], sta_addr);
+#endif
+}
+
+/**
+ * @brief Verify RSN IE
+ *
+ * @param rsn_ie          Pointer RSN IE
+ * @param sys_config      Pointer to mlan_uap_bss_param structure
+ *
+ * @return                MTRUE/MFALSE
+ */
+static t_u8 wifi_check_rsn_ie(IEEEtypes_Rsn_t *rsn_ie, mlan_uap_bss_param *sys_config)
+{
+    int left                            = 0;
+    int count                           = 0;
+    int i                               = 0;
+    wpa_suite_auth_key_mgmt_t *key_mgmt = NULL;
+    left                                = rsn_ie->len + 2;
+    if (left < (int)sizeof(IEEEtypes_Rsn_t))
+        return MFALSE;
+    sys_config->wpa_cfg.group_cipher         = 0;
+    sys_config->wpa_cfg.pairwise_cipher_wpa2 = 0;
+    sys_config->key_mgmt                     = 0;
+    /* check the group cipher */
+    switch (rsn_ie->group_cipher.type)
+    {
+        case WPA_CIPHER_TKIP2:
+            sys_config->wpa_cfg.group_cipher = CIPHER_TKIP;
+            break;
+        case WPA_CIPHER_AES_CCM:
+        case WPA_CIPHER_AES_GCM:
+        case WPA_CIPHER_AES_CCM_256:
+        case WPA_CIPHER_AES_GCM_256:
+            sys_config->wpa_cfg.group_cipher = CIPHER_AES_CCMP;
+            break;
+        default:
+            break;
+    }
+    count = wlan_le16_to_cpu(rsn_ie->pairwise_cipher.count);
+    for (i = 0; i < count; i++)
+    {
+        switch (rsn_ie->pairwise_cipher.list[i].type)
+        {
+            case WPA_CIPHER_TKIP2:
+                sys_config->wpa_cfg.pairwise_cipher_wpa2 |= CIPHER_TKIP;
+                break;
+            case WPA_CIPHER_AES_CCM:
+            case WPA_CIPHER_AES_GCM:
+            case WPA_CIPHER_AES_CCM_256:
+            case WPA_CIPHER_AES_GCM_256:
+                sys_config->wpa_cfg.pairwise_cipher_wpa2 |= CIPHER_AES_CCMP;
+                break;
+            default:
+                break;
+        }
+    }
+    left -= sizeof(IEEEtypes_Rsn_t) + (count - 1) * sizeof(wpa_suite);
+    if (left < (int)sizeof(wpa_suite_auth_key_mgmt_t))
+        return MFALSE;
+    key_mgmt = (wpa_suite_auth_key_mgmt_t *)((u8 *)rsn_ie + sizeof(IEEEtypes_Rsn_t) + (count - 1) * sizeof(wpa_suite));
+    count    = wlan_le16_to_cpu(key_mgmt->count);
+    if (left < (int)(sizeof(wpa_suite_auth_key_mgmt_t) + (count - 1) * sizeof(wpa_suite)))
+        return MFALSE;
+    for (i = 0; i < count; i++)
+    {
+        switch (key_mgmt->list[i].type)
+        {
+            case RSN_AKM_8021X:
+            case RSN_AKM_8021X_SHA256:
+            case RSN_AKM_8021X_SUITEB:
+            case RSN_AKM_8021X_SUITEB_192:
+#if CONFIG_11R
+            case RSN_AKM_FT_8021X:
+            case RSN_AKM_FT_8021X_SHA384:
+#endif
+                sys_config->key_mgmt |= KEY_MGMT_EAP;
+                break;
+            case RSN_AKM_PSK:
+#if CONFIG_11R
+            case RSN_AKM_FT_PSK:
+#endif
+                sys_config->key_mgmt |= KEY_MGMT_PSK;
+                break;
+            case RSN_AKM_PSK_SHA256:
+                sys_config->key_mgmt |= KEY_MGMT_PSK_SHA256;
+                break;
+            case RSN_AKM_SAE:
+#if CONFIG_11R
+            case RSN_AKM_FT_SAE:
+#endif
+                sys_config->key_mgmt |= KEY_MGMT_SAE;
+                break;
+            case RSN_AKM_OWE:
+#if CONFIG_DRIVER_OWE
+                sys_config->key_mgmt |= KEY_MGMT_OWE;
+#endif
+                break;
+        }
+    }
+    return MTRUE;
+}
+
+/**
+ *  @brief Verify WPA IE`
+ *  @param wpa_ie          Pointer WPA IE
+ *  @param sys_config      Pointer to mlan_uap_bss_param structure
+ *
+ * @return                MTRUE/MFALSE
+ */
+static t_u8 wifi_check_wpa_ie(IEEEtypes_Wpa_t *wpa_ie, mlan_uap_bss_param *sys_config)
+{
+    int left                            = 0;
+    int count                           = 0;
+    int i                               = 0;
+    wpa_suite_auth_key_mgmt_t *key_mgmt = NULL;
+    left                                = wpa_ie->len + 2;
+    if (left < (int)sizeof(IEEEtypes_Wpa_t))
+        return MFALSE;
+    sys_config->wpa_cfg.group_cipher        = 0;
+    sys_config->wpa_cfg.pairwise_cipher_wpa = 0;
+    switch (wpa_ie->group_cipher.type)
+    {
+        case WPA_CIPHER_TKIP2:
+            sys_config->wpa_cfg.group_cipher = CIPHER_TKIP;
+            break;
+        case WPA_CIPHER_AES_CCM:
+            sys_config->wpa_cfg.group_cipher = CIPHER_AES_CCMP;
+            break;
+        default:
+            break;
+    }
+    count = wlan_le16_to_cpu(wpa_ie->pairwise_cipher.count);
+    for (i = 0; i < count; i++)
+    {
+        switch (wpa_ie->pairwise_cipher.list[i].type)
+        {
+            case WPA_CIPHER_TKIP2:
+                sys_config->wpa_cfg.pairwise_cipher_wpa |= CIPHER_TKIP;
+                break;
+            case WPA_CIPHER_AES_CCM:
+                sys_config->wpa_cfg.pairwise_cipher_wpa |= CIPHER_AES_CCMP;
+                break;
+            default:
+                break;
+        }
+    }
+    left -= sizeof(IEEEtypes_Wpa_t) + (count - 1) * sizeof(wpa_suite);
+    if (left < (int)sizeof(wpa_suite_auth_key_mgmt_t))
+        return MFALSE;
+    key_mgmt = (wpa_suite_auth_key_mgmt_t *)((u8 *)wpa_ie + sizeof(IEEEtypes_Wpa_t) + (count - 1) * sizeof(wpa_suite));
+    count    = wlan_le16_to_cpu(key_mgmt->count);
+    if (left < (int)(sizeof(wpa_suite_auth_key_mgmt_t) + (count - 1) * sizeof(wpa_suite)))
+        return MFALSE;
+    for (i = 0; i < count; i++)
+    {
+        switch (key_mgmt->list[i].type)
+        {
+            case RSN_AKM_8021X:
+                sys_config->key_mgmt = KEY_MGMT_EAP;
+                break;
+            case RSN_AKM_PSK:
+                sys_config->key_mgmt = KEY_MGMT_PSK;
+                break;
+        }
+    }
+    return MTRUE;
+}
+
+/**
+ * @brief Find RSN/WPA IES
+ *
+ * @param ie              Pointer IE buffer
+ * @param sys_config      Pointer to mlan_uap_bss_param structure
+ * @return                MTRUE/MFALSE
+ */
+static t_u8 wifi_find_wpa_ies(const t_u8 *ie, int len, mlan_uap_bss_param *sys_config)
+{
+    int bytes_left           = len;
+    const t_u8 *pcurrent_ptr = ie;
+    t_u16 total_ie_len;
+    t_u8 element_len;
+    t_u8 wpa2 = 0;
+    t_u8 wpa  = 0;
+    t_u8 ret  = MFALSE;
+    IEEEtypes_ElementId_e element_id;
+    IEEEtypes_VendorSpecific_t *pvendor_ie;
+    const t_u8 wpa_oui[4] = {0x00, 0x50, 0xf2, 0x01};
+    while (bytes_left >= 2)
+    {
+        element_id   = (IEEEtypes_ElementId_e)(*((t_u8 *)pcurrent_ptr));
+        element_len  = *((t_u8 *)pcurrent_ptr + 1);
+        total_ie_len = element_len + sizeof(IEEEtypes_Header_t);
+        if (bytes_left < total_ie_len)
+        {
+            PRINTM(MERROR, "InterpretIE: Error in processing IE, bytes left < IE length\n");
+            bytes_left = 0;
+            continue;
+        }
+        switch (element_id)
+        {
+            case RSN_IE:
+                wpa2 = wifi_check_rsn_ie((IEEEtypes_Rsn_t *)pcurrent_ptr, sys_config);
+                break;
+            case VENDOR_SPECIFIC_221:
+                pvendor_ie = (IEEEtypes_VendorSpecific_t *)pcurrent_ptr;
+                if (!memcmp(pvendor_ie->vend_hdr.oui, wpa_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                    (pvendor_ie->vend_hdr.oui_type == wpa_oui[3]))
+                {
+                    wpa = wifi_check_wpa_ie((IEEEtypes_Wpa_t *)pcurrent_ptr, sys_config);
+                }
+                break;
+            default:
+                break;
+        }
+        pcurrent_ptr += element_len + 2;
+        /* Need to account for IE ID and IE Len */
+        bytes_left -= (element_len + 2);
+    }
+    if (wpa && wpa2)
+    {
+        sys_config->protocol = PROTOCOL_WPA | PROTOCOL_WPA2;
+        ret                  = MTRUE;
+    }
+    else if (wpa2)
+    {
+        sys_config->protocol = PROTOCOL_WPA2;
+        ret                  = MTRUE;
+    }
+    else if (wpa)
+    {
+        sys_config->protocol = PROTOCOL_WPA;
+        ret                  = MTRUE;
+    }
+    return ret;
+}
+
+/**
+ * @brief Find and set WMM IES
+ *  @param priv            Pointer to moal_private
+ *  @param ie              Pointer IE buffer
+ *  @param sys_config      Pointer to mlan_uap_bss_param structure
+ *
+ * @return                N/A
+ *
+ **/
+static t_void wifi_set_wmm_ies(mlan_private *priv, const t_u8 *ie, int len, mlan_uap_bss_param *sys_config)
+{
+    int bytes_left           = len;
+    const t_u8 *pcurrent_ptr = ie;
+    t_u16 total_ie_len;
+    t_u8 element_len;
+    IEEEtypes_VendorSpecific_t *pvendor_ie;
+    IEEEtypes_ElementId_e element_id;
+    const t_u8 wmm_oui[4] = {0x00, 0x50, 0xf2, 0x02};
+
+    while (bytes_left >= 2)
+    {
+        element_id   = (IEEEtypes_ElementId_e)(*((t_u8 *)pcurrent_ptr));
+        element_len  = *((t_u8 *)pcurrent_ptr + 1);
+        total_ie_len = element_len + sizeof(IEEEtypes_Header_t);
+        if (bytes_left < total_ie_len)
+        {
+            PRINTM(MERROR, "InterpretIE: Error in processing IE, bytes left < IE length\n");
+            bytes_left = 0;
+            continue;
+        }
+        switch (element_id)
+        {
+            case VENDOR_SPECIFIC_221:
+                pvendor_ie = (IEEEtypes_VendorSpecific_t *)pcurrent_ptr;
+                if (!memcmp(pvendor_ie->vend_hdr.oui, wmm_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                    pvendor_ie->vend_hdr.oui_type == wmm_oui[3])
+                {
+                    if (total_ie_len == sizeof(IEEEtypes_WmmParameter_t))
+                    {
+#if CONFIG_WIFI_CAPA
+                        if (priv->adapter->usr_dot_11n_enable)
+#endif
+                        {
+                            /*
+                             * Only accept and copy the WMM IE if
+                             * it matches the size expected for the
+                             * WMM Parameter IE.
+                             */
+                            memcpy(&sys_config->wmm_para, pcurrent_ptr + sizeof(IEEEtypes_Header_t), element_len);
+
+                            /** Disable U-APSD for now */
+                            sys_config->wmm_para.qos_info &= 0x7F;
+
+                            /** set uap_host_based_config to true */
+                            sys_config->uap_host_based_config = MTRUE;
+                        }
+#if CONFIG_WIFI_CAPA
+                        else
+                        {
+                            memset(sys_config->wmm_para.ac_params, 0x00, sizeof(wmm_ac_parameters_t) * MAX_AC_QUEUES);
+                        }
+#endif
+                    }
+                }
+
+                break;
+            default:
+                break;
+        }
+        pcurrent_ptr += element_len + 2;
+        /* Need to account for IE ID and IE Len */
+        bytes_left -= (element_len + 2);
+    }
+}
+
+/**
+ *  @brief Set/Get system configuration parameters
+ *
+ *  @param priv             A pointer to moal_private structure
+ *  @param action           MLAN_ACT_SET or MLAN_ACT_GET
+ *  @param wait_option      Wait option
+ *  @param sys_cfg          A pointer to mlan_uap_bss_param structure
+ *
+ *  @return                 MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+mlan_status wifi_set_get_sys_config(mlan_private *priv, t_u16 action, mlan_uap_bss_param *sys_cfg)
+{
+    int ret;
+    mlan_ds_bss bss;
+    mlan_ioctl_req ioctl_buf;
+
+    ENTER();
+
+    (void)memset(&bss, 0x00, sizeof(mlan_ds_bss));
+
+    bss.sub_command = MLAN_OID_UAP_BSS_CONFIG;
+
+    if (action == MLAN_ACT_SET)
+        memcpy(&bss.param.bss_config, sys_cfg, sizeof(mlan_uap_bss_param));
+
+    (void)memset(&ioctl_buf, 0x00, sizeof(mlan_ioctl_req));
+
+    ioctl_buf.req_id = (t_u32)MLAN_IOCTL_BSS;
+    /** Pointer to buffer */
+    ioctl_buf.pbuf = (t_u8 *)&bss;
+
+    ret = wifi_uap_prepare_and_send_cmd(priv, HOST_CMD_APCMD_SYS_CONFIGURE, HostCmd_ACT_GEN_SET, 0, &ioctl_buf, NULL,
+                                        MLAN_BSS_TYPE_UAP, NULL);
+    if (ret != WM_SUCCESS)
+    {
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+#define IE_MASK_WPS    0x0001
+#define IE_MASK_P2P    0x0002
+#define IE_MASK_WFD    0x0004
+#define IE_MASK_VENDOR 0x0008
+#define IE_MASK_EXTCAP 0x0010
+
+/**
+ * @brief get specific ie
+ *
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ * @param ie_out          Pointer to out IE buf
+ * @param ie_out_len    Total length of ie_out
+ * @param mask            IE mask
+ *
+ * @return                out IE length
+ */
+static t_u16 wifi_get_specific_ie(const t_u8 *ie, int len, t_u8 *ie_out, t_u32 ie_out_len, t_u16 mask)
+{
+    int left_len    = len;
+    const t_u8 *pos = ie;
+    int length;
+    t_u8 id                                = 0;
+    t_u16 out_len                          = 0;
+    IEEEtypes_VendorSpecific_t *pvendor_ie = NULL;
+    const u8 wps_oui[4]                    = {0x00, 0x50, 0xf2, 0x04};
+    const u8 p2p_oui[4]                    = {0x50, 0x6f, 0x9a, 0x09};
+    const u8 wfd_oui[4]                    = {0x50, 0x6f, 0x9a, 0x0a};
+    const t_u8 wmm_oui[4]                  = {0x00, 0x50, 0xf2, 0x02};
+
+    ENTER();
+    while (left_len >= 2)
+    {
+        length = *(pos + 1);
+        id     = *pos;
+        if ((length + 2) > left_len)
+            break;
+        if (id == VENDOR_SPECIFIC_221)
+        {
+            pvendor_ie = (IEEEtypes_VendorSpecific_t *)pos;
+            if (!memcmp(pvendor_ie->vend_hdr.oui, wmm_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                pvendor_ie->vend_hdr.oui_type == wmm_oui[3])
+            {
+                PRINTM(MIOCTL, "find WMM IE\n");
+            }
+            else if (!memcmp(pvendor_ie->vend_hdr.oui, p2p_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                     pvendor_ie->vend_hdr.oui_type == p2p_oui[3])
+            {
+                if (mask & IE_MASK_P2P)
+                {
+                    /** only get first p2p ie here */
+                    __memcpy(NULL, ie_out + out_len, pos, length + 2);
+                    out_len += length + 2;
+                    break;
+                }
+            }
+            else if (!memcmp(pvendor_ie->vend_hdr.oui, wps_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                     pvendor_ie->vend_hdr.oui_type == wps_oui[3])
+            {
+                if (mask & IE_MASK_WPS)
+                {
+                    if ((out_len + length + 2) < (int)ie_out_len)
+                    {
+                        __memcpy(NULL, ie_out + out_len, pos, length + 2);
+                        out_len += length + 2;
+                    }
+                    else
+                    {
+                        PRINTM(MERROR, "get_specific_ie: IE too big, fail copy WPS IE\n");
+                        break;
+                    }
+                }
+            }
+            else if (!memcmp(pvendor_ie->vend_hdr.oui, wfd_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                     pvendor_ie->vend_hdr.oui_type == wfd_oui[3])
+            {
+                if (mask & IE_MASK_WFD)
+                {
+                    if ((out_len + length + 2) < (int)ie_out_len)
+                    {
+                        __memcpy(NULL, ie_out + out_len, pos, length + 2);
+                        out_len += length + 2;
+                    }
+                    else
+                    {
+                        PRINTM(MERROR, "get_specific_ie: IE too big, fail copy WFD IE\n");
+                        break;
+                    }
+                }
+            }
+            else if (mask & IE_MASK_VENDOR)
+            {
+                if ((out_len + length + 2) < (int)ie_out_len)
+                {
+                    __memcpy(NULL, ie_out + out_len, pos, length + 2);
+                    out_len += length + 2;
+                }
+                else
+                {
+                    PRINTM(MERROR, "get_specific_ie:IE too big, fail copy VENDOR IE\n");
+                    break;
+                }
+            }
+        }
+        pos += (length + 2);
+        left_len -= (length + 2);
+    }
+    LEAVE();
+    return out_len;
+}
+
+/**
+ * @brief Find specific IE from IE buffer
+ *
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ * @param spec_ie         Pointer to specific IE buffer
+ * @param spec_len        Total length of specific IE
+ *
+ * @return                out IE length
+ */
+static t_u8 wifi_find_ie(const t_u8 *ie, int len, const t_u8 *spec_ie, int spec_len)
+{
+    int left_len    = len;
+    const t_u8 *pos = ie;
+    int length;
+
+    while (left_len >= 2)
+    {
+        length = *(pos + 1);
+        if ((length + 2) > left_len)
+            break;
+        if ((length + 2) == spec_len)
+        {
+            if (!memcmp(pos, spec_ie, spec_len))
+                return MTRUE;
+        }
+        pos += (length + 2);
+        left_len -= (length + 2);
+    }
+    return MFALSE;
+}
+
+/**
+ * @brief Filter specific IE in ie buf
+ *
+ * @param priv            pointer to moal private structure
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ * @param ie_out		  Pointer to out IE buf
+ * @param ie_out_len      Total length of ie_out
+ * @param wps_flag	      flag for wps/p2p
+ * @param dup_ie          Pointer to duplicate ie
+ * @param dup_ie_len	  duplicate IE len
+ *
+ * @return                out IE length
+ */
+static t_u16 wifi_filter_beacon_ies(mlan_private *priv,
+                                    const t_u8 *ie,
+                                    int len,
+                                    t_u8 *ie_out,
+                                    t_u32 ie_out_len,
+                                    t_u16 wps_flag,
+                                    const t_u8 *dup_ie,
+                                    int dup_ie_len)
+{
+    int left_len    = len;
+    const t_u8 *pos = ie;
+    int length;
+    t_u8 id                                = 0;
+    t_u16 out_len                          = 0;
+    IEEEtypes_VendorSpecific_t *pvendor_ie = NULL;
+    const u8 wps_oui[4]                    = {0x00, 0x50, 0xf2, 0x04};
+    const u8 p2p_oui[4]                    = {0x50, 0x6f, 0x9a, 0x09};
+    const u8 wfd_oui[4]                    = {0x50, 0x6f, 0x9a, 0x0a};
+    const t_u8 wmm_oui[4]                  = {0x00, 0x50, 0xf2, 0x02};
+    t_u8 find_p2p_ie                       = MFALSE;
+    t_u8 enable_11d                        = MFALSE;
+#if CONFIG_11AX
+    t_u8 ext_id = 0;
+#endif
+    // int ie_len;
+
+    /* ERP_INFO/EXTENDED_SUPPORT_RATES/HT_CAPABILITY/HT_OPERATION/WMM
+     * and WPS/P2P/WFD IE will be fileter out
+     */
+    while (left_len >= 2)
+    {
+        length = *(pos + 1);
+        id     = *pos;
+        if ((length + 2) > left_len)
+            break;
+        if (dup_ie && dup_ie_len && wifi_find_ie(dup_ie, dup_ie_len, pos, length + 2))
+        {
+            wifi_d("skip duplicate IE");
+            pos += (length + 2);
+            left_len -= (length + 2);
+            continue;
+        }
+        switch (id)
+        {
+            case COUNTRY_INFO:
+                enable_11d = MTRUE;
+                if ((out_len + length + 2) < (int)ie_out_len)
+                {
+                    __memcpy(priv, ie_out + out_len, pos, length + 2);
+                    out_len += length + 2;
+                }
+                else
+                {
+                    wifi_d("IE too big, fail copy COUNTRY INFO IE");
+                }
+                break;
+            case HT_CAPABILITY:
+            case HT_OPERATION:
+#if CONFIG_11AC
+            case VHT_CAPABILITY:
+            case VHT_OPERATION:
+#endif
+                if ((out_len + length + 2) < (int)ie_out_len)
+                {
+                    __memcpy(priv, ie_out + out_len, pos, length + 2);
+                    out_len += length + 2;
+                }
+                else
+                {
+                    wifi_d("IE too big, fail copy COUNTRY INFO IE");
+                }
+                break;
+            case EXTENDED_SUPPORTED_RATES:
+            case WLAN_EID_ERP_INFO:
+                /* Fall Through */
+            case REGULATORY_CLASS:
+                /* Fall Through */
+            case OVERLAPBSSSCANPARAM:
+                break;
+#if CONFIG_11AX
+            case EXTENSION:
+                ext_id = *(pos + 2);
+#if CONFIG_11AX
+                if (ext_id == HE_CAPABILITY)
+                {
+                    mlan_ds_11ax_he_cfg he_cfg;
+                    IEEEtypes_HECap_t *hecap_ie = NULL;
+                    (void)memset((void *)&he_cfg, 0, sizeof(mlan_ds_11ax_he_cfg));
+
+                    if (priv->uap_channel <= 14)
+                        he_cfg.band = MBIT(0);
+                    else
+                        he_cfg.band = MBIT(1);
+
+                    wifi_d("Retrieve 11ax cfg by channel=%d band=%d", priv->uap_channel, he_cfg.band);
+
+                    if (0 == wlan_cmd_11ax_cfg(priv, HostCmd_ACT_GEN_GET, &he_cfg))
+                    {
+                        t_u16 he_cap_len;
+                        hecap_ie                      = (IEEEtypes_HECap_t *)&he_cfg.he_cap.len;
+                        he_cap_len                    = he_cfg.he_cap.len;
+                        hecap_ie->ieee_hdr.len        = he_cap_len;
+                        hecap_ie->ieee_hdr.element_id = he_cfg.he_cap.id;
+
+                        __memcpy(priv, ie_out + out_len, hecap_ie, hecap_ie->ieee_hdr.len + 2);
+
+                        out_len += hecap_ie->ieee_hdr.len + 2;
+                    }
+                    else
+                    {
+                        wifi_d("Fail to get 11ax he_cap parameters");
+                    }
+                }
+                else
+#endif
+                {
+                    if ((out_len + length + 2) < (int)ie_out_len)
+                    {
+                        __memcpy(priv, ie_out + out_len, pos, length + 2);
+                        out_len += length + 2;
+                    }
+                    else
+                    {
+                        wifi_d("IE too big, fail copy EXTENSION IE");
+                    }
+                }
+                break;
+#endif
+            case EXT_CAPABILITY:
+                /* filter out EXTCAP */
+                if (wps_flag & IE_MASK_EXTCAP)
+                {
+#if 0
+                    ie_len = length + 2;
+                    if (MLAN_STATUS_SUCCESS !=
+                            wifi_set_get_gen_ie(priv, MLAN_ACT_SET,
+                                (t_u8 *)pos, &ie_len,
+                                MOAL_IOCTL_WAIT))
+                        PRINTM(MERROR,
+                                "Fail to set EXTCAP IE\n");
+#endif
+                    break;
+                }
+                if ((out_len + length + 2) < (int)ie_out_len)
+                {
+                    __memcpy(priv, ie_out + out_len, pos, length + 2);
+                    out_len += length + 2;
+                }
+                else
+                {
+                    wifi_d("IE too big, fail copy EXTCAP IE");
+                }
+                break;
+            case VENDOR_SPECIFIC_221:
+                /* filter out wmm ie */
+                pvendor_ie = (IEEEtypes_VendorSpecific_t *)pos;
+                if (!memcmp(pvendor_ie->vend_hdr.oui, wmm_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                    pvendor_ie->vend_hdr.oui_type == wmm_oui[3])
+                {
+                    break;
+                }
+                /* filter out wps ie */
+                else if (!memcmp(pvendor_ie->vend_hdr.oui, wps_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                         pvendor_ie->vend_hdr.oui_type == wps_oui[3])
+                {
+                    if (wps_flag & IE_MASK_WPS)
+                        break;
+                }
+                /* filter out first p2p ie */
+                else if (!memcmp(pvendor_ie->vend_hdr.oui, p2p_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                         pvendor_ie->vend_hdr.oui_type == p2p_oui[3])
+                {
+                    if (!find_p2p_ie && (wps_flag & IE_MASK_P2P))
+                    {
+                        find_p2p_ie = MTRUE;
+                        break;
+                    }
+                }
+                /* filter out wfd ie */
+                else if (!memcmp(pvendor_ie->vend_hdr.oui, wfd_oui, sizeof(pvendor_ie->vend_hdr.oui)) &&
+                         pvendor_ie->vend_hdr.oui_type == wfd_oui[3])
+                {
+                    if (wps_flag & IE_MASK_WFD)
+                        break;
+                }
+                else if (wps_flag & IE_MASK_VENDOR)
+                {
+                    // filter out vendor IE
+                    break;
+                }
+                if ((out_len + length + 2) < (int)ie_out_len)
+                {
+                    __memcpy(priv, ie_out + out_len, pos, length + 2);
+                    out_len += length + 2;
+                }
+                else
+                {
+                    wifi_d("IE too big, fail copy VENDOR_SPECIFIC_221 IE");
+                }
+                break;
+            default:
+                if ((out_len + length + 2) < (int)ie_out_len)
+                {
+                    __memcpy(priv, ie_out + out_len, pos, length + 2);
+                    out_len += length + 2;
+                }
+                else
+                {
+                    wifi_d("IE too big, fail copy %d IE", id);
+                }
+                break;
+        }
+
+        pos += (length + 2);
+        left_len -= (length + 2);
+    }
+
+    if (enable_11d && !priv->bss_started && !wlan_11d_is_enabled(priv))
+    {
+        wuap_d("Enable 11D support");
+        wifi_enable_uap_11d_support();
+    }
+    return out_len;
+}
+
+static int wifi_nxp_set_mgmt_ies(mlan_private *priv,
+                                 char *tail_ies,
+                                 unsigned short tail_ies_len,
+                                 char *beacon_ies,
+                                 unsigned short beacon_ies_len,
+                                 char *proberesp_ies,
+                                 unsigned short proberesp_ies_len,
+                                 char *assocresp_ies,
+                                 unsigned short assocresp_ies_len)
+{
+    int ret        = WM_SUCCESS;
+    const t_u8 *ie = NULL;
+    t_u8 ie_buffer[MAX_IE_SIZE];
+    t_u16 ie_len, ie_length = 0;
+    custom_ie *beacon_ies_data     = NULL;
+    custom_ie *beacon_wps_ies_data = NULL;
+    custom_ie *proberesp_ies_data  = NULL;
+    custom_ie *assocresp_ies_data  = NULL;
+
+    beacon_ies_data     = (custom_ie *)OSA_MemoryAllocate(sizeof(custom_ie));
+    beacon_wps_ies_data = (custom_ie *)OSA_MemoryAllocate(sizeof(custom_ie));
+    proberesp_ies_data  = (custom_ie *)OSA_MemoryAllocate(sizeof(custom_ie));
+
+    assocresp_ies_data = (custom_ie *)OSA_MemoryAllocate(sizeof(custom_ie));
+
+    if ((!beacon_ies_data) || (!beacon_wps_ies_data) || (!proberesp_ies_data) || (!assocresp_ies_data))
+    {
+        if (beacon_ies_data)
+        {
+            OSA_MemoryFree(beacon_ies_data);
+        }
+        if (beacon_wps_ies_data)
+        {
+            OSA_MemoryFree(beacon_wps_ies_data);
+        }
+        if (proberesp_ies_data)
+        {
+            OSA_MemoryFree(proberesp_ies_data);
+        }
+        if (assocresp_ies_data)
+        {
+            OSA_MemoryFree(assocresp_ies_data);
+        }
+        return -WM_FAIL;
+    }
+
+    ie        = (const t_u8 *)tail_ies;
+    ie_len    = tail_ies_len;
+    ie_length = 0;
+
+    if ((ie != NULL) && (ie_len != 0U))
+    {
+        if (priv->beacon_vendor_index != -1)
+        {
+            ret = wifi_clear_mgmt_ie2(MLAN_BSS_TYPE_UAP, priv->beacon_vendor_index);
+            if (ret != WM_SUCCESS)
+            {
+                wuap_e("Clear uAP vendor IE failed");
+                ret = -WM_FAIL;
+                goto done;
+            }
+            priv->beacon_vendor_index = -1;
+        }
+
+        ie_length = wifi_get_specific_ie(ie, ie_len, ie_buffer, MAX_IE_SIZE, IE_MASK_VENDOR);
+#if CONFIG_WIFI_IO_DUMP
+        PRINTF("VENDOR IE\r\n");
+        dump_hex(ie_buffer, ie_length);
+#endif
+
+        if (ie_length)
+        {
+            priv->beacon_vendor_index =
+                wifi_set_mgmt_ie2(MLAN_BSS_TYPE_UAP, MGMT_MASK_BEACON | MGMT_MASK_ASSOC_RESP | MGMT_MASK_PROBE_RESP,
+                                  (void *)ie_buffer, ie_length);
+
+            if (priv->beacon_vendor_index == -1)
+            {
+                wuap_e("Set uAP vendor IE failed");
+                ret = -WM_FAIL;
+                goto done;
+            }
+        }
+
+        ie_length = wifi_filter_beacon_ies(priv, ie, ie_len, ie_buffer, MAX_IE_SIZE,
+                                           IE_MASK_WPS | IE_MASK_WFD | IE_MASK_P2P | IE_MASK_VENDOR,
+                                           (const t_u8 *)proberesp_ies, proberesp_ies_len);
+#if CONFIG_WIFI_IO_DUMP
+        PRINTF("Beacon IE\r\n");
+        dump_hex(ie_buffer, ie_length);
+#endif
+    }
+
+    beacon_ies_data->ie_index = priv->beacon_index;
+
+    if (ie_length)
+    {
+        beacon_ies_data->mgmt_subtype_mask = MGMT_MASK_BEACON | MGMT_MASK_ASSOC_RESP | MGMT_MASK_PROBE_RESP;
+        beacon_ies_data->ie_length         = ie_length;
+        memcpy(beacon_ies_data->ie_buffer, (void *)ie_buffer, ie_length);
+    }
+    else
+    {
+        beacon_ies_data->mgmt_subtype_mask = MGMT_MASK_CLEAR;
+    }
+
+    ie        = (const t_u8 *)beacon_ies;
+    ie_len    = beacon_ies_len;
+    ie_length = 0;
+
+    if ((ie != NULL) && (ie_len != 0U))
+    {
+        ie_length = wifi_filter_beacon_ies(priv, ie, ie_len, ie_buffer, MAX_IE_SIZE, IE_MASK_VENDOR, NULL, 0);
+#if CONFIG_WIFI_IO_DUMP
+        PRINTF("Beacon WPS IE\r\n");
+        dump_hex(ie_buffer, ie_length);
+#endif
+    }
+
+    beacon_wps_ies_data->ie_index = priv->beacon_wps_index;
+    if (ie_length)
+    {
+        beacon_wps_ies_data->mgmt_subtype_mask = MGMT_MASK_BEACON;
+        beacon_wps_ies_data->ie_length         = ie_length;
+        memcpy(beacon_wps_ies_data->ie_buffer, (void *)ie_buffer, ie_length);
+    }
+    else
+    {
+        beacon_wps_ies_data->mgmt_subtype_mask = MGMT_MASK_CLEAR;
+    }
+
+    ie        = (const t_u8 *)proberesp_ies;
+    ie_len    = proberesp_ies_len;
+    ie_length = 0;
+
+    if ((ie != NULL) && (ie_len != 0U))
+    {
+        ie_length =
+            wifi_filter_beacon_ies(priv, ie, ie_len, ie_buffer, MAX_IE_SIZE, IE_MASK_P2P | IE_MASK_VENDOR, NULL, 0);
+#if CONFIG_WIFI_IO_DUMP
+        PRINTF("ProbeResp IE\r\n");
+        dump_hex(ie_buffer, ie_length);
+#endif
+    }
+
+    proberesp_ies_data->ie_index = priv->proberesp_index;
+    if (ie_length)
+    {
+        proberesp_ies_data->mgmt_subtype_mask = MGMT_MASK_PROBE_RESP;
+        proberesp_ies_data->ie_length         = ie_length;
+        memcpy(proberesp_ies_data->ie_buffer, (void *)ie_buffer, ie_length);
+    }
+    else
+    {
+        proberesp_ies_data->mgmt_subtype_mask = MGMT_MASK_CLEAR;
+    }
+
+    ie        = (const t_u8 *)assocresp_ies;
+    ie_len    = assocresp_ies_len;
+    ie_length = 0;
+
+    if ((ie != NULL) && (ie_len != 0U))
+    {
+#if CONFIG_WIFI_IO_DUMP
+        PRINTF("AssocResp IE\r\n");
+        dump_hex(ie, ie_len);
+#endif
+    }
+
+    assocresp_ies_data->ie_index = priv->assocresp_index;
+    if (ie_len)
+    {
+        assocresp_ies_data->mgmt_subtype_mask = MGMT_MASK_ASSOC_RESP;
+        assocresp_ies_data->ie_length         = ie_len;
+        memcpy(assocresp_ies_data->ie_buffer, (void *)ie, ie_len);
+    }
+    else
+    {
+        assocresp_ies_data->mgmt_subtype_mask = MGMT_MASK_CLEAR;
+    }
+
+    ret = wifi_set_custom_ie(beacon_ies_data, beacon_wps_ies_data, proberesp_ies_data, assocresp_ies_data);
+    if (ret != WM_SUCCESS)
+    {
+        ret = -WM_FAIL;
+        goto done;
+    }
+    ret = WM_SUCCESS;
+done:
+    if (beacon_ies_data)
+    {
+        OSA_MemoryFree(beacon_ies_data);
+    }
+    if (beacon_wps_ies_data)
+    {
+        OSA_MemoryFree(beacon_wps_ies_data);
+    }
+    if (proberesp_ies_data)
+    {
+        OSA_MemoryFree(proberesp_ies_data);
+    }
+    if (assocresp_ies_data)
+    {
+        OSA_MemoryFree(assocresp_ies_data);
+    }
+
+    return ret;
+}
+
+#if CONFIG_5GHz_SUPPORT
+/**
+ * @brief Get second channel offset
+ *
+ * @param priv         A pointer to moal_private structure
+ * @param chan             channel num
+ * @return                second channel offset
+ */
+t_u8 wifi_get_second_channel_offset(mlan_private *priv, int chan)
+{
+    t_u8 chan2Offset = SEC_CHAN_NONE;
+
+#if CONFIG_UNII4_BAND_SUPPORT
+    mlan_adapter *pmadapter = priv->adapter;
+    if (pmadapter->region_code != COUNTRY_CODE_US && chan == 165)
+#else
+    if (chan == 165)
+#endif
+        return chan2Offset;
+
+    switch (chan)
+    {
+        case 36:
+        case 44:
+        case 52:
+        case 60:
+        case 100:
+        case 108:
+        case 116:
+        case 124:
+        case 132:
+#if CONFIG_11AC
+        case 140:
+#endif
+        case 149:
+        case 157:
+#if CONFIG_UNII4_BAND_SUPPORT
+        case 165:
+        case 173:
+#endif
+            chan2Offset = SEC_CHAN_ABOVE;
+            break;
+        case 40:
+        case 48:
+        case 56:
+        case 64:
+        case 104:
+        case 112:
+        case 120:
+        case 128:
+        case 136:
+#if CONFIG_11AC
+        case 144:
+#endif
+        case 153:
+        case 161:
+#if CONFIG_UNII4_BAND_SUPPORT
+        case 169:
+        case 177:
+#endif
+            chan2Offset = SEC_CHAN_BELOW;
+            break;
+    }
+    return chan2Offset;
+}
+#endif
+
+/**
+ * @brief Look up specific IE in a buf
+ *
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ * @param id              Element id to lookup
+ *
+ * @return                Pointer of the specific IE -- success, NULL -- fail
+ */
+const t_u8 *wifi_parse_ie_tlv(const t_u8 *ie, int len, t_u8 id)
+{
+    int left_len    = len;
+    const t_u8 *pos = ie;
+    int length;
+
+    /* IE format:
+     * |   u8  |   id   |
+     * |   u8  |   len  |
+     * |   var |   data |
+     */
+    while (left_len >= 2)
+    {
+        length = *(pos + 1);
+        if ((*pos == id) && (length + 2) <= left_len)
+            return pos;
+        pos += (length + 2);
+        left_len -= (length + 2);
+    }
+
+    return NULL;
+}
+
+/**
+ * @brief Look up specific IE in Extension IE
+ *
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ * @param ext_id         Extended Element id to lookup
+ *
+ * @return                Pointer of the specific Extended IE -- success, NULL
+ * -- fail
+ */
+const t_u8 *wifi_parse_ext_ie_tlv(const t_u8 *ie, int len, t_u8 ext_id)
+{
+    int left_len    = len;
+    const t_u8 *pos = ie;
+    int length;
+
+    /* Extension IE format:
+     * |   u8  |   id   |
+     * |   u8  |   len  |
+     * |   u8  |   ext_id |
+     * |   var |   data |
+     */
+    while (left_len >= 2)
+    {
+        length = *(pos + 1);
+        if ((*pos == EXTENSION) && (length + 2) <= left_len)
+        {
+            if (*(pos + 2) == ext_id)
+                return pos;
+        }
+        pos += (length + 2);
+        left_len -= (length + 2);
+    }
+    return NULL;
+}
+
+/**
+ * @brief get ht_cap from beacon ie
+ *
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ *
+ * @return                ht_cap
+ */
+static t_u16 wifi_get_htcap_info(const t_u8 *ie, int len)
+{
+    t_u16 ht_cap_info           = 0;
+    IEEEtypes_HTCap_t *htcap_ie = NULL;
+    htcap_ie                    = (IEEEtypes_HTCap_t *)wifi_parse_ie_tlv(ie, len, HT_CAPABILITY);
+    if (htcap_ie)
+    {
+        /* hostap has converted ht_cap_info to little endian, here
+         * conver to host endian */
+        ht_cap_info = wlan_le16_to_cpu(htcap_ie->ht_cap.ht_cap_info);
+        wifi_d("Get ht_cap from beacon ies: 0x%x\r\n", ht_cap_info);
+    }
+    return ht_cap_info;
+}
+
+#if CONFIG_11AC
+/**
+ * @brief get vht_cap from beacon ie
+ *
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ *
+ * @return                Pointer to vht_cap ie
+ */
+static IEEEtypes_VHTCap_t *wifi_get_vhtcap_info(const t_u8 *ie, int len)
+{
+    IEEEtypes_VHTCap_t *vhtcap_ie = NULL;
+    vhtcap_ie                     = (IEEEtypes_VHTCap_t *)wifi_parse_ie_tlv(ie, len, VHT_CAPABILITY);
+    if (vhtcap_ie)
+        wifi_d("Get vht_cap from beacon ies: 0x%x\r\n", vhtcap_ie->vht_cap.vht_cap_info);
+    return vhtcap_ie;
+}
+
+/**
+ * @brief get vht_oper from beacon ie
+ *
+ * @param ie              Pointer to IEs
+ * @param len             Total length of ie
+ *
+ * @return                Pointer to vht_opr ie
+ */
+static IEEEtypes_VHTOprat_t *wifi_get_vht_oprat_ie(const t_u8 *ie, int len)
+{
+    IEEEtypes_VHTOprat_t *vht_oprat_ie = NULL;
+    vht_oprat_ie                       = (IEEEtypes_VHTOprat_t *)wifi_parse_ie_tlv(ie, len, VHT_OPERATION);
+    if (vht_oprat_ie)
+        wifi_d("Get vht_oprat_ie from beacon ies: chan_width=%d\r\n", vht_oprat_ie->chan_width);
+    return vht_oprat_ie;
+}
+
+/**
+ *  @brief enable/disable 11AC
+ *
+ *  @param priv     A pointer to moal_private structure
+ *  @param action   MLAN_ACT_DISABLE or MLAN_ACT_ENABLE
+ *  @param vht20_40 Enable VHT 20 MHz or 40 MHz band
+ *  @param vhtcap_ie A pointer to vht capability IE
+ *
+ *  @return         0--success, otherwise failure
+ */
+int wifi_uap_set_11ac_status2(mlan_private *priv, t_u8 action, t_u8 vht20_40, IEEEtypes_VHTCap_t *vhtcap_ie)
+{
+    mlan_adapter *pmadapter = priv->adapter;
+    mlan_ds_11ac_vht_cfg vht_cfg;
+    int ret = 0;
+
+    ENTER();
+
+    (void)memset(&vht_cfg, 0, sizeof(vht_cfg));
+
+#if CONFIG_5GHz_SUPPORT
+    if (priv->uap_channel > MAX_CHANNELS_BG)
+    {
+        vht_cfg.band = BAND_SELECT_A;
+    }
+    else
+    {
+        vht_cfg.band = BAND_SELECT_BG;
+    }
+#else
+    vht_cfg.band = BAND_SELECT_BG;
+#endif
+    vht_cfg.txrx = MLAN_RADIO_TXRX;
+
+    /*
+     * p2p GO (negotiation or auto GO) cases, wpa_supplicant will download
+     * invalid vht capability with value 0 in beacon parameters, so for p2p
+     * GO case (vht_cap_info = 0), driver will use hardware 11ac vht
+     * capability value instead of up layer value.
+     */
+    if (vhtcap_ie && vhtcap_ie->vht_cap.vht_cap_info != 0)
+    {
+        vht_cfg.vht_cap_info = wlan_le32_to_cpu(vhtcap_ie->vht_cap.vht_cap_info);
+        /** todo mcs configuration */
+    }
+    else
+    {
+#if CONFIG_5GHz_SUPPORT
+        vht_cfg.vht_cap_info = pmadapter->usr_dot_11ac_dev_cap_a;
+#else
+        vht_cfg.vht_cap_info = pmadapter->usr_dot_11ac_dev_cap_bg;
+#endif
+    }
+    if (action == MLAN_ACT_DISABLE)
+    {
+        vht_cfg.bwcfg = MFALSE;
+        vht_cfg.vht_cap_info &= ~VHT_CAP_11AC_MASK;
+        vht_cfg.vht_rx_mcs = vht_cfg.vht_tx_mcs = 0xffff;
+        vht_cfg.skip_usr_11ac_mcs_cfg           = MTRUE;
+    }
+    else
+    {
+        if (vht20_40)
+            vht_cfg.bwcfg = MFALSE;
+        else
+            vht_cfg.bwcfg = MTRUE;
+        vht_cfg.vht_cap_info &= ~DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK;
+        vht_cfg.vht_tx_mcs            = pmadapter->usr_dot_11ac_mcs_support >> 16;
+        vht_cfg.vht_rx_mcs            = pmadapter->usr_dot_11ac_mcs_support & 0xffff;
+        vht_cfg.skip_usr_11ac_mcs_cfg = MTRUE;
+    }
+
+    if ((GET_VHTCAP_MAXMPDULEN(vht_cfg.vht_cap_info)) != 0U)
+    {
+        RESET_11ACMAXMPDULEN(vht_cfg.vht_cap_info);
+    }
+    else
+    {
+        /** Do Nothing */
+    }
+
+    wifi_d("Uap:11ac=%d vht_cap_info=0x%x, vht_tx_mcs=0x%x, vht_rx_mcs=0x%x\r\n", action, vht_cfg.vht_cap_info,
+           vht_cfg.vht_tx_mcs, vht_cfg.vht_rx_mcs);
+
+    ret = (int)wlan_11ac_ioctl_vhtcfg(priv, (t_u8)MLAN_ACT_SET, &vht_cfg);
+    return ret;
+}
+#endif
+
+#if CONFIG_11AX
+
+/**
+ *  @brief enable/disable 11AX
+ *
+ *  @param pmpriv   A pointer to mlan_private structure
+ *  @param action   MLAN_ACT_DISABLE or MLAN_ACT_ENABLE
+ *  @param band     band config
+ *
+ *  @return         0--success, otherwise failure
+ */
+int wifi_uap_set_11ax_status2(mlan_private *pmpriv, t_u8 action, t_u8 band, IEEEtypes_HECap_t *hecap_ie, t_u8 bandwidth)
+{
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    int ret                 = 0;
+    mlan_ds_11ax_he_cfg he_cfg;
+
+    ENTER();
+    if ((band == BAND_CONFIG_5GHZ && !(pmadapter->fw_bands & BAND_AAX)) ||
+        ((band == BAND_CONFIG_ACS_MODE || band == BAND_CONFIG_MANUAL) && !(pmadapter->fw_bands & BAND_GAX)))
+    {
+        PRINTM(MERROR, "fw doesn't support 11ax\n");
+        ret = -WM_FAIL;
+        goto done;
+    }
+    memset(&he_cfg, 0, sizeof(he_cfg));
+    if (band == BAND_CONFIG_5GHZ)
+    {
+        he_cfg.band = MBIT(1);
+        (void)memcpy((void *)&he_cfg.he_cap, (const void *)pmadapter->hw_he_cap, pmadapter->hw_hecap_len);
+    }
+    else if (band == BAND_CONFIG_ACS_MODE || band == BAND_CONFIG_MANUAL)
+    {
+        he_cfg.band = MBIT(0);
+        (void)memcpy((void *)&he_cfg.he_cap, (const void *)pmadapter->hw_2g_he_cap, pmadapter->hw_2g_hecap_len);
+        if (bandwidth == BANDWIDTH_20MHZ)
+        {
+            he_cfg.he_cap.he_phy_cap[0] &= ~(MBIT(1));
+        }
+    }
+    else
+    {
+        PRINTM(MERROR, "Invalid band!\n");
+        ret = -WM_E_INVAL;
+        goto done;
+    }
+#ifdef RW610
+    he_cfg.he_cap.he_phy_cap[0] &= ~DEFAULT_11AX_CAP_40MHZIH2_4GHZBAND_RESET_MASK;
+#endif
+#if CONFIG_11AX_TWT
+    /* uap mode clear TWT request bit */
+    he_cfg.he_cap.he_mac_cap[0] &= ~HE_MAC_CAP_TWT_REQ_SUPPORT;
+#endif
+#if 0
+    if (wlan_cmd_11ax_cfg(pmpriv, HostCmd_ACT_GEN_GET, &he_cfg))
+    {
+        PRINTM(MERROR, "Fail to get 11ax cfg!\n");
+        ret = -WM_FAIL;
+        goto done;
+    }
+#endif
+    if (hecap_ie)
+    {
+        DBG_HEXDUMP(MCMD_D, "hecap_ie", (t_u8 *)hecap_ie, hecap_ie->ieee_hdr.len + sizeof(IEEEtypes_Header_t));
+        he_cfg.he_cap.id  = hecap_ie->ieee_hdr.element_id;
+        he_cfg.he_cap.len = hecap_ie->ieee_hdr.len;
+        memcpy(&he_cfg.he_cap.ext_id, &hecap_ie->ext_id, he_cfg.he_cap.len);
+        if ((band == BAND_2GHZ) && (bandwidth == BANDWIDTH_20MHZ))
+        {
+            he_cfg.he_cap.he_phy_cap[0] &= ~(MBIT(1));
+        }
+    }
+
+    if (action == MLAN_ACT_DISABLE)
+    {
+        if (he_cfg.he_cap.len && (he_cfg.he_cap.ext_id == HE_CAPABILITY))
+            memset(he_cfg.he_cap.he_txrx_mcs_support, 0xff, sizeof(he_cfg.he_cap.he_txrx_mcs_support));
+        else
+        {
+            PRINTM(MCMND, "11ax already disabled\n");
+            goto done;
+        }
+    }
+    DBG_HEXDUMP(MCMD_D, "HE_CFG ", (t_u8 *)&he_cfg, sizeof(he_cfg));
+    ret = wlan_cmd_11ax_cfg(pmpriv, HostCmd_ACT_GEN_SET, &he_cfg);
+done:
+    LEAVE();
+    return ret;
+}
+#endif /* CONFIG_11AX */
+
+#if CONFIG_5GHz_SUPPORT
+static void wifi_set_uap_dfs_cac(mlan_private *priv, Band_Config_t *bandcfg, t_u8 ht_enabled)
+{
+    if (priv->uap_channel > MAX_CHANNELS_BG)
+    {
+        mlan_private *priv_sta = (mlan_private *)mlan_adap->priv[0];
+        if ((priv_sta->media_connected == MTRUE) && wlan_11h_radar_detect_required(priv, priv->uap_channel))
+        {
+            nxp_wifi_dfs_cac_info cacinfo;
+            t_u8 center_chan = 0;
+
+            memset(&cacinfo, 0, sizeof(nxp_wifi_dfs_cac_info));
+            cacinfo.center_freq  = channel_to_frequency(priv->uap_channel, bandcfg->chanBand);
+            cacinfo.ht_enabled   = ht_enabled;
+            cacinfo.ch_offset    = bandcfg->chan2Offset;
+            cacinfo.center_freq2 = 0;
+
+            switch (bandcfg->chanWidth)
+            {
+                case CHAN_BW_20MHZ:
+                    if (ht_enabled)
+                        cacinfo.ch_width = CHAN_BAND_WIDTH_20;
+                    else
+                        cacinfo.ch_width = CHAN_BAND_WIDTH_20_NOHT;
+                    cacinfo.center_freq1 = cacinfo.center_freq;
+                    break;
+
+                case CHAN_BW_40MHZ:
+                    cacinfo.ch_width = CHAN_BAND_WIDTH_40;
+                    if (bandcfg->chan2Offset == SEC_CHAN_ABOVE)
+                        cacinfo.center_freq1 = cacinfo.center_freq + 10;
+                    else if (bandcfg->chan2Offset == SEC_CHAN_BELOW)
+                        cacinfo.center_freq1 = cacinfo.center_freq - 10;
+                    break;
+
+#if (CONFIG_11AC)
+                case CHAN_BW_80MHZ:
+                    cacinfo.ch_width = CHAN_BAND_WIDTH_80;
+                    center_chan      = wlan_get_center_freq_idx(priv, BAND_AAC, priv->uap_channel, CHANNEL_BW_80MHZ);
+                    cacinfo.center_freq1 = channel_to_frequency(center_chan, bandcfg->chanBand);
+                    break;
+#endif
+
+                default:
+                    break;
+            }
+
+            /* STA has connected to EXT-AP on DFS channel, then uAP should support start network
+             * on DFS channel. If DFS is offloaded to the driver, supplicant won't setup uAP until
+             * the CAC is done by driver. When DFS master mode is not supported, driver needs to
+             * send the EVENT_DFS_CAC_STARTED event to supplicant to set the cac_started flag, and
+             * send EVENT_DFS_CAC_FINISHED event to supplicant to continue AP setup for DFS channel */
+            if (wm_wifi.supp_if_callbk_fns->dfs_cac_started_callbk_fn)
+            {
+                wm_wifi.supp_if_callbk_fns->dfs_cac_started_callbk_fn(wm_wifi.hapd_if_priv, &cacinfo);
+            }
+            if (wm_wifi.supp_if_callbk_fns->dfs_cac_finished_callbk_fn)
+            {
+                wm_wifi.supp_if_callbk_fns->dfs_cac_finished_callbk_fn(wm_wifi.hapd_if_priv, &cacinfo);
+            }
+        }
+    }
+}
+#endif
+
+int wifi_nxp_beacon_config(nxp_wifi_ap_info_t *params)
+{
+    mlan_private *priv = (mlan_private *)mlan_adap->priv[1];
+    mlan_private *remain_priv = NULL;
+    // mlan_adapter *pmadapter = priv->adapter;
+
+    const t_u8 *ie                 = NULL;
+    int ret                        = 0, ie_len;
+    mlan_uap_bss_param *sys_config = NULL;
+    // int i                          = 0;
+    t_u8 rates_b[5]   = {0x82, 0x84, 0x8b, 0x96, 0x00};
+    t_u8 rates_bg[13] = {0x82, 0x84, 0x8b, 0x96, 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c, 0x00};
+#if CONFIG_5GHz_SUPPORT
+    t_u8 rates_a[9] = {0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c, 0x00};
+#endif
+    t_u8 supported_mcs_set[] = {0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+    t_u8 chan2Offset         = SEC_CHAN_NONE;
+    t_u8 enable_11n          = MTRUE;
+    t_u8 bandwidth           = BANDWIDTH_40MHZ;
+    t_u16 ht_cap             = 0;
+#if CONFIG_11AC
+    t_u8 enable_11ac                = MFALSE;
+    t_u8 vht20_40                   = MFALSE;
+    IEEEtypes_VHTCap_t *vhtcap_ie   = NULL;
+    IEEEtypes_VHTOprat_t *vhtopr_ie = NULL;
+#endif
+#if CONFIG_11AX
+    IEEEtypes_HECap_t *hecap_ie = NULL;
+    t_u8 enable_11ax            = MFALSE;
+#endif
+    Band_Config_t bandcfg;
+    wifi_scan_chan_list_t scan_chan_list;
+
+    ENTER();
+
+    (void)bandwidth;
+
+    if (!params)
+    {
+        return -WM_FAIL;
+    }
+
+    memset(&scan_chan_list, 0, sizeof(wifi_scan_chan_list_t));
+
+    ie     = (const t_u8 *)params->tail_ie.ie;
+    ie_len = params->tail_ie.ie_len;
+    remain_priv = priv->adapter->priv[priv->adapter->remain_bss_index];
+    if (wifi_is_remain_on_channel() && remain_priv)
+    {
+        wuap_d("Cancel Remain on Channel before Starting AP");
+        wifi_remain_on_channel(false, 0, 0);
+    }
+
+    if (params->beacon_set)
+    {
+        ret = wifi_nxp_set_mgmt_ies(priv, params->tail_ie.ie, params->tail_ie.ie_len, params->beacon_ies.ie,
+                                    params->beacon_ies.ie_len, params->proberesp_ies.ie, params->proberesp_ies.ie_len,
+                                    params->assocresp_ies.ie, params->assocresp_ies.ie_len);
+        if (ret != WM_SUCCESS)
+        {
+            wuap_e("Set uAP mgmt ie failed");
+            return -WM_FAIL;
+        }
+    }
+    else
+    {
+        sys_config = OSA_MemoryAllocate(sizeof(mlan_uap_bss_param));
+        if (!sys_config)
+        {
+            wuap_e("Fail to alloc memory for mlan_uap_bss_param");
+            ret = -WM_FAIL;
+            goto done;
+        }
+
+        memset(&bandcfg, 0, sizeof(Band_Config_t));
+
+        if (priv->uap_max_sta)
+            sys_config->max_sta_count = priv->uap_max_sta;
+
+        /* Setting the default values */
+        sys_config->channel = params->chan.channel;
+        priv->uap_channel   = sys_config->channel;
+        if (priv->uap_channel != 0U)
+        {
+#if CONFIG_5GHz_SUPPORT
+            if (priv->uap_channel > MAX_CHANNELS_BG)
+            {
+                mlan_private *priv_sta = (mlan_private *)mlan_adap->priv[0];
+                if ((priv_sta->media_connected == MFALSE) && wlan_11h_radar_detect_required(priv, priv->uap_channel))
+                {
+                    wuap_e("Cannot start uAP on DFS channel %d", priv->uap_channel);
+                    ret = -WM_FAIL;
+                    goto done;
+                }
+
+                bandcfg.chanBand = BAND_5GHZ;
+            }
+            else
+            {
+                bandcfg.chanBand = BAND_2GHZ;
+            }
+#else
+            bandcfg.chanBand = BAND_2GHZ;
+#endif
+        }
+
+        sys_config->preamble_type         = 0;
+        sys_config->mgmt_ie_passthru_mask = priv->mgmt_frame_passthru_mask;
+        memcpy(sys_config->mac_addr, params->bssid, ETH_ALEN);
+
+        /* Set frag_threshold, rts_threshold, and retry limit */
+        sys_config->frag_threshold = MLAN_FRAG_MAX_VALUE;
+        sys_config->rts_threshold  = MLAN_RTS_MAX_VALUE;
+
+        sys_config->pwe_derivation = params->sae_pwe;
+
+        if (params->beacon_int)
+            sys_config->beacon_period = params->beacon_int;
+
+        if (params->dtim_period)
+            sys_config->dtim_period = params->dtim_period;
+
+        if (sys_config->channel <= MAX_CHANNELS_BG)
+        {
+            if (sys_config->channel == 14)
+            {
+                memcpy(sys_config->rates, rates_b, sizeof(rates_b));
+            }
+            else
+            {
+                memcpy(sys_config->rates, rates_bg, sizeof(rates_bg));
+            }
+        }
+#if CONFIG_5GHz_SUPPORT
+        else
+        {
+            memcpy(sys_config->rates, rates_a, sizeof(rates_a));
+        }
+#endif
+
+        if (params->chan.ht_enabled != 1)
+        {
+            enable_11n = MFALSE;
+        }
+
+        if (params->chan.sec_channel_offset == 1)
+        {
+            chan2Offset = SEC_CHAN_ABOVE;
+        }
+        else if (params->chan.sec_channel_offset == -1)
+        {
+            chan2Offset = SEC_CHAN_BELOW;
+        }
+
+        if (params->chan.bandwidth == 20)
+        {
+            bandwidth         = BANDWIDTH_20MHZ;
+            bandcfg.chanWidth = CHAN_BW_20MHZ;
+        }
+        else if (params->chan.bandwidth == 40)
+        {
+            bandwidth         = BANDWIDTH_40MHZ;
+            bandcfg.chanWidth = CHAN_BW_40MHZ;
+        }
+#if CONFIG_11AC
+#if CONFIG_5GHz_SUPPORT
+        else if (params->chan.bandwidth == 80)
+        {
+            bandwidth         = BANDWIDTH_80MHZ;
+            bandcfg.chanWidth = CHAN_BW_80MHZ;
+            chan2Offset       = wifi_get_second_channel_offset(priv, priv->uap_channel);
+        }
+#endif
+#endif
+
+        bandcfg.chan2Offset = chan2Offset;
+        (void)memcpy((void *)&sys_config->band_cfg, (const void *)&bandcfg, sizeof(bandcfg));
+
+#if CONFIG_11AC
+        if (params->chan.vht_enabled == 1)
+        {
+            enable_11ac = wifi_check_11ac_capability(priv, bandcfg.chanBand);
+            if (enable_11ac && ((bandwidth == BANDWIDTH_20MHZ) || (bandwidth == BANDWIDTH_40MHZ)))
+            {
+                vht20_40 = MTRUE;
+            }
+        }
+#endif
+#if CONFIG_11AX
+        if (params->chan.he_enabled == 1)
+        {
+            enable_11ax = wifi_check_11ax_capability(priv, bandcfg.chanBand);
+        }
+#endif
+
+        /* Disable GreenField by default */
+        sys_config->ht_cap_info = 0x10c;
+        if (enable_11n)
+            sys_config->ht_cap_info |= 0x20;
+        if (chan2Offset)
+        {
+            sys_config->ht_cap_info |= 0x1042;
+            sys_config->ampdu_param = 3;
+        }
+
+        if (enable_11n)
+        {
+            ht_cap = wifi_get_htcap_info(ie, ie_len);
+            if (ht_cap)
+            {
+                if (bandcfg.chanBand == BAND_2GHZ)
+                    sys_config->ht_cap_info = (ht_cap & 0x13ff) | 0x0c;
+                else
+                    sys_config->ht_cap_info = (ht_cap & 0x13ff) | 0x0c;
+            }
+            wifi_d(
+                "11n=%d, ht_cap=0x%x, channel=%d, bandcfg:chanBand=0x%x chanWidth=0x%x chan2Offset=0x%x "
+                "scanMode=0x%x\n",
+                enable_11n, sys_config->ht_cap_info, priv->uap_channel, bandcfg.chanBand, bandcfg.chanWidth,
+                bandcfg.chan2Offset, bandcfg.scanMode);
+
+            ret = wifi_uap_set_httxcfg_int(ht_cap);
+            if (ret != WM_SUCCESS)
+            {
+                wuap_e("Cannot set uAP HT TX Cfg:%x", sys_config->ht_cap_info);
+                ret = -WM_FAIL;
+                goto done;
+            }
+
+            sys_config->ampdu_param = 3;
+
+            /* Set MCS32 with 40MHz support */
+            if ((bandcfg.chanWidth == CHAN_BW_40MHZ) || (bandcfg.chanWidth == CHAN_BW_80MHZ))
+                SETHT_MCS32(supported_mcs_set);
+
+            (void)memcpy((void *)sys_config->supported_mcs_set, (const void *)supported_mcs_set,
+                         sizeof(sys_config->supported_mcs_set));
+        }
+
+        if (!params->ssid.ssid_len)
+        {
+            ret = -WM_FAIL;
+            goto done;
+        }
+        memcpy(sys_config->ssid.ssid, params->ssid.ssid, MIN(MLAN_MAX_SSID_LENGTH, params->ssid.ssid_len));
+        sys_config->ssid.ssid_len = MIN(MLAN_MAX_SSID_LENGTH, params->ssid.ssid_len);
+        /**
+         * hidden_ssid=0: broadcast SSID in beacons.
+         * hidden_ssid=1: send empty SSID (length=0) in beacon.
+         * hidden_ssid=2: clear SSID (ACSII 0), but keep the original length
+         */
+        if (!params->hide_ssid)
+            sys_config->bcast_ssid_ctl = 1;
+        else if (params->hide_ssid == 1)
+            sys_config->bcast_ssid_ctl = 0;
+        else if (params->hide_ssid == 2)
+            sys_config->bcast_ssid_ctl = 2;
+
+        sys_config->auth_mode = MLAN_AUTH_MODE_OPEN;
+
+        sys_config->protocol = PROTOCOL_NO_SECURITY;
+        if ((params->wpa_version & WIFI_NXP_WPA_VERSION_1) && (params->wpa_version & WIFI_NXP_WPA_VERSION_2))
+            sys_config->protocol = PROTOCOL_WPA | PROTOCOL_WPA2;
+        else if (params->wpa_version & WIFI_NXP_WPA_VERSION_2)
+            sys_config->protocol = PROTOCOL_WPA2;
+        else if (params->wpa_version & WIFI_NXP_WPA_VERSION_1)
+            sys_config->protocol = PROTOCOL_WPA;
+
+        if (params->key_mgmt_suites || (params->privacy && params->wpa_version))
+            wifi_find_wpa_ies(ie, ie_len, sys_config);
+
+        /*find and set wmm ie*/
+        wifi_set_wmm_ies(priv, ie, ie_len, sys_config);
+
+#if CONFIG_11AC
+        if (enable_11ac && enable_11n)
+        {
+            vhtcap_ie = wifi_get_vhtcap_info(ie, ie_len);
+            vhtopr_ie = wifi_get_vht_oprat_ie(ie, ie_len);
+            // Enable VHT80
+            if (vhtopr_ie && vhtopr_ie->chan_width)
+                vht20_40 = 0;
+            wifi_uap_set_11ac_status2(priv, MLAN_ACT_ENABLE, vht20_40, vhtcap_ie);
+        }
+        else
+        {
+            wifi_uap_set_11ac_status2(priv, MLAN_ACT_DISABLE, vht20_40, NULL);
+        }
+#endif
+#if CONFIG_11AX
+        if (enable_11ax && enable_11n)
+        {
+            hecap_ie = (IEEEtypes_HECap_t *)wifi_parse_ext_ie_tlv(ie, ie_len, HE_CAPABILITY);
+            wifi_uap_set_11ax_status2(priv, MLAN_ACT_ENABLE, bandcfg.chanBand, hecap_ie, bandwidth);
+        }
+        else
+            wifi_uap_set_11ax_status2(priv, MLAN_ACT_DISABLE, bandcfg.chanBand, NULL, bandwidth);
+#endif
+
+        if (params->ap_max_inactivity)
+        {
+            sys_config->sta_ageout_timer    = params->ap_max_inactivity * 10;
+            sys_config->ps_sta_ageout_timer = params->ap_max_inactivity * 10;
+        }
+        PRINTM(MIOCTL, "inactivity_timeout=%d\n", params->ap_max_inactivity);
+        PRINTM(MIOCTL, "sta_ageout_timer=%d ps_sta_ageout_timer=%d\n", sys_config->sta_ageout_timer,
+               sys_config->ps_sta_ageout_timer);
+
+        if (MLAN_STATUS_SUCCESS != wifi_set_get_sys_config(priv, MLAN_ACT_SET, sys_config))
+        {
+            wuap_e("Set uAP sys config failed");
+            ret = -WM_FAIL;
+            goto done;
+        }
+
+        ret = wifi_nxp_set_mgmt_ies(priv, params->tail_ie.ie, params->tail_ie.ie_len, params->beacon_ies.ie,
+                                    params->beacon_ies.ie_len, params->proberesp_ies.ie, params->proberesp_ies.ie_len,
+                                    params->assocresp_ies.ie, params->assocresp_ies.ie_len);
+        if (ret != WM_SUCCESS)
+        {
+            wuap_e("Set uAP mgmt ie failed");
+            ret = -WM_FAIL;
+            goto done;
+        }
+
+        if (wm_wifi.enable_11d_support && wm_wifi.uap_support_11d_apis)
+        {
+            wuap_d("Downloading domain params");
+            wm_wifi.uap_support_11d_apis->wifi_uap_downld_domain_params_p(BAND_B);
+#if CONFIG_5GHz_SUPPORT
+            wm_wifi.uap_support_11d_apis->wifi_uap_downld_domain_params_p(BAND_A);
+#endif
+        }
+
+#if CONFIG_5GHz_SUPPORT
+        wifi_set_uap_dfs_cac(priv, &bandcfg, enable_11n);
+#endif
+        priv->uap_host_based = MTRUE;
+
+        if (!params->beacon_set)
+        {
+            wuap_d("Starting BSS");
+            /* Start BSS */
+            if (MLAN_STATUS_SUCCESS != wifi_uap_prepare_and_send_cmd(priv, HOST_CMD_APCMD_BSS_START,
+                                                                     HostCmd_ACT_GEN_SET, 0, NULL, NULL,
+                                                                     MLAN_BSS_TYPE_UAP, NULL))
+            {
+                wuap_e("Start BSS failed");
+                priv->uap_host_based = MFALSE;
+                ret                  = -WM_FAIL;
+                goto done;
+            }
+            wuap_d("wlan: AP started");
+
+            (void)wifi_set_rx_mgmt_indication(MLAN_BSS_TYPE_UAP, WIFI_MGMT_AUTH | MGMT_MASK_ASSOC_REQ |
+                                                                     MGMT_MASK_REASSOC_REQ | WIFI_MGMT_DEAUTH |
+                                                                     WIFI_MGMT_ACTION | WIFI_MGMT_DIASSOC);
+        }
+
+    done:
+        if (sys_config != NULL)
+        {
+            OSA_MemoryFree(sys_config);
+        }
+    }
+
+    LEAVE();
+    return ret;
+}
+
+int wifi_setup_ht_cap(t_u16 *ht_capab, t_u8 *pmcs_set, t_u8 *a_mpdu_params, t_u8 band)
+{
+    mlan_private *priv      = (mlan_private *)mlan_adap->priv[1];
+    mlan_adapter *pmadapter = priv->adapter;
+    t_u32 usr_dot_11n_dev_cap;
+    int rx_mcs_supp;
+    t_u8 mcs_set[NUM_MCS_FIELD];
+
+    ENTER();
+
+    *ht_capab = HT_CAP_INFO_DSSS_CCK40MHZ;
+
+    *a_mpdu_params = 3;
+
+#if CONFIG_5GHz_SUPPORT
+    if (band == BAND_5GHZ)
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_a;
+    }
+    else
+#endif
+    {
+        usr_dot_11n_dev_cap = pmadapter->usr_dot_11n_dev_cap_bg;
+    }
+
+    if (ISSUPP_RXLDPC(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_LDPC_CODING_CAP;
+    }
+    if (ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET;
+    }
+    else
+    {
+        *ht_capab &= ~(HT_CAP_INFO_DSSS_CCK40MHZ);
+    }
+    if ((usr_dot_11n_dev_cap >> 20) & 0x03) /* Delayed ACK supported */
+    {
+        *ht_capab |= HT_CAP_INFO_DELAYED_BA;
+    }
+    if (ISSUPP_GREENFIELD(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_GREEN_FIELD;
+    }
+    if (ISSUPP_SHORTGI20(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_SHORT_GI20MHZ;
+    }
+    if (ISSUPP_SHORTGI40(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_SHORT_GI40MHZ;
+    }
+    if (ISSUPP_TXSTBC(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_TX_STBC;
+    }
+    if (ISSUPP_RXSTBC(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_RX_STBC_1;
+    }
+    if (ISSUPP_MIMOPS(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_SMPS_STATIC;
+    }
+    else
+    {
+        *ht_capab |= HT_CAP_INFO_SMPS_DISABLED;
+    }
+    if (ISSUPP_MAXAMSDU(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_MAX_AMSDU_SIZE;
+    }
+    if (ISENABLED_40MHZ_INTOLARENT(usr_dot_11n_dev_cap))
+    {
+        *ht_capab |= HT_CAP_INFO_40MHZ_INTOLERANT;
+    }
+
+    rx_mcs_supp = GET_RXMCSSUPP(pmadapter->usr_dev_mcs_support);
+    /* Set MCS for 1x1/2x2 */
+    (void)__memset(pmadapter, (t_u8 *)mcs_set, 0xff, rx_mcs_supp);
+    /* Clear all the other values */
+    (void)__memset(pmadapter, (t_u8 *)&mcs_set[rx_mcs_supp], 0, NUM_MCS_FIELD - rx_mcs_supp);
+    /* Set MCS32 with 40MHz support */
+    if (ISSUPP_CHANWIDTH40(usr_dot_11n_dev_cap))
+        SETHT_MCS32(mcs_set);
+
+    (void)__memcpy(pmadapter, pmcs_set, mcs_set, NUM_MCS_FIELD);
+
+    LEAVE();
+
+    return WM_SUCCESS;
+}
+
+t_u16 wifi_get_default_ht_capab()
+{
+    t_u16 ht_capab;
+    t_u8 mcs_set[16];
+    t_u8 a_mpdu_params;
+
+    wifi_setup_ht_cap(&ht_capab, &mcs_set[0], &a_mpdu_params, 0);
+
+    return ht_capab;
+}
+
+static void wifi_setup_channel_flag(void *channels, int num_chan, region_chan_t *region)
+{
+    int i;
+    int set_idx                             = 0;
+    int get_idx                             = 0;
+    const chan_freq_power_t *pchans_get     = region->pcfp;
+    struct hostapd_channel_data *pchans_set = (struct hostapd_channel_data *)channels;
+
+    for (i = 0; i < MAX(num_chan, region->num_cfp); i++)
+    {
+        if (set_idx >= num_chan)
+            break;
+
+        if (get_idx >= region->num_cfp || pchans_set[set_idx].chan < pchans_get[get_idx].channel)
+        {
+            pchans_set[set_idx].flag |= HOSTAPD_CHAN_DISABLED;
+
+            set_idx++;
+        }
+        else if (pchans_set[set_idx].chan == pchans_get[get_idx].channel)
+        {
+            /* set passive scan or radar detect flag */
+            if (pchans_get[get_idx].passive_scan_or_radar_detect == MTRUE)
+                pchans_set[set_idx].flag |= HOSTAPD_CHAN_RADAR;
+
+            set_idx++;
+            get_idx++;
+        }
+        else
+        {
+            get_idx++;
+        }
+    }
+}
+
+void wifi_setup_channel_info(void *channels, int num_channels, t_u8 band)
+{
+    mlan_adapter *pmadapter = (mlan_adapter *)mlan_adap;
+    region_chan_t *region   = NULL;
+
+    if (band == BAND_2GHZ)
+    {
+        if (pmadapter->region_channel[0].valid)
+            region = &pmadapter->region_channel[0];
+        else if (pmadapter->universal_channel[0].valid)
+            region = &pmadapter->universal_channel[0];
+        else
+            return;
+
+        wifi_setup_channel_flag(channels, num_channels, region);
+    }
+    else if (band == BAND_5GHZ)
+    {
+        if (pmadapter->region_channel[1].valid)
+            region = &pmadapter->region_channel[1];
+        else if (pmadapter->universal_channel[1].valid)
+            region = &pmadapter->universal_channel[1];
+        else
+            return;
+
+        wifi_setup_channel_flag(channels, num_channels, region);
+    }
+    else
+    {
+        wuap_e("wifi_setup_channel_info unsupported band %d", band);
+    }
+}
+
+#if CONFIG_11AC
+int wifi_setup_vht_cap(t_u32 *vht_capab, t_u8 *vht_mcs_set, t_u8 band)
+{
+    mlan_private *priv      = (mlan_private *)mlan_adap->priv[1];
+    mlan_adapter *pmadapter = priv->adapter;
+    // t_u32 usr_dot_11ac_dev_cap;
+    t_u16 vht_tx_mcs, vht_rx_mcs;
+
+    ENTER();
+
+    *vht_capab = pmadapter->usr_dot_11ac_dev_cap_a;
+
+    *vht_capab &= ~DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK;
+#ifdef RW610
+    *vht_capab &= ~DEFALUT_11AC_CAP_SHORTGI_80MHZ_RESET_MASK;
+#endif
+
+    if ((GET_VHTCAP_MAXMPDULEN(*vht_capab)) != 0U)
+    {
+        RESET_11ACMAXMPDULEN(*vht_capab);
+    }
+    else
+    {
+        /** Do Nothing */
+    }
+
+    vht_tx_mcs = pmadapter->usr_dot_11ac_mcs_support >> 16;
+    vht_rx_mcs = pmadapter->usr_dot_11ac_mcs_support & 0xffff;
+
+    (void)__memcpy(pmadapter, &vht_mcs_set[0], &vht_rx_mcs, sizeof(t_u16));
+
+    (void)__memcpy(pmadapter, &vht_mcs_set[4], &vht_tx_mcs, sizeof(t_u16));
+
+    LEAVE();
+
+    return WM_SUCCESS;
+}
+
+t_u32 wifi_get_default_vht_capab()
+{
+    t_u32 vht_capab;
+    t_u8 vht_mcs_set[8];
+
+    wifi_setup_vht_cap(&vht_capab, &vht_mcs_set[0], 0);
+
+    return vht_capab;
+}
+#endif
+
+#if CONFIG_11AX
+/*
+===============
+11AX CAP for uAP
+===============
+Note: bits not mentioned below are set to 0.
+
+5G
+===
+HE MAC Cap:
+Bit0:  1  (+HTC HE Support)
+Bit25: 1  (OM Control Support. But uAP does not support
+           Tx OM received from the STA, as it does not support UL OFDMA)
+
+HE PHY Cap:
+Bit1-7: 0x2 (Supported Channel Width Set.
+             Note it would be changed after 80+80 MHz is supported)
+Bit8-11: 0x3 (Punctured Preamble Rx.
+              Note: it would be changed after 80+80 MHz is supported)
+Bit12: 0x0 (Device Class)
+Bit13: 0x1 (LDPC coding in Payload)
+Bit17: 0x1 (NDP with 4xHE-LTF+3.2usGI)
+Bit18: 0x1 (STBC Tx <= 80 MHz)
+Bit19: 0x1 (STBC Rx <= 80 MHz)
+Bit20: 0x1 (Doppler Tx)
+Bit21: 0x1 (Doppler Rx)
+Bit24-25: 0x1 (DCM Max Constellation Tx)
+Bit27-28: 0x1 (DCM Max Constellation Rx)
+Bit31: 0x1 (SU Beamformer)
+Bit32: 0x1 (SU BeamFormee)
+Bit34-36: 0x7 (Beamformee STS <= 80 MHz)
+Bit40-42: 0x1 (Number of Sounding Dimentions <= 80 MHz)
+Bit53: 0x1 (Partial Bandwidth Extended Range)
+Bit55: 0x1 (PPE Threshold Present.
+            Note: PPE threshold may have some changes later)
+Bit58: 0x1 (HE SU PPDU and HE MU PPDU with 4xHE-LTF+0.8usGI)
+Bit59-61: 0x1 (Max Nc)
+Bit64: 0x1 (HE ER SU PPDU with 4xHE-LTF+0.8usGI)
+Bit75: 0x1 (Rx 1024-QAM Support < 242-tone RU)
+*/
+
+#define UAP_HE_MAC_CAP0_MASK  0x04
+#define UAP_HE_MAC_CAP1_MASK  0x00
+#define UAP_HE_MAC_CAP2_MASK  0x10
+#define UAP_HE_MAC_CAP3_MASK  0x02
+#define UAP_HE_MAC_CAP4_MASK  0x00
+#define UAP_HE_MAC_CAP5_MASK  0x00
+#define UAP_HE_PHY_CAP0_MASK  0x04
+#define UAP_HE_PHY_CAP1_MASK  0x23
+#define UAP_HE_PHY_CAP2_MASK  0x3E
+#define UAP_HE_PHY_CAP3_MASK  0x89
+#define UAP_HE_PHY_CAP4_MASK  0x1D
+#define UAP_HE_PHY_CAP5_MASK  0x01
+#define UAP_HE_PHY_CAP6_MASK  0xA0
+#define UAP_HE_PHY_CAP7_MASK  0x0C
+#define UAP_HE_PHY_CAP8_MASK  0x01
+#define UAP_HE_PHY_CAP9_MASK  0x08
+#define UAP_HE_PHY_CAP10_MASK 0x00
+
+/*
+2G
+===
+HE MAC Cap:
+Bit0:   1  (+HTC HE Support)
+Bit25: 1  (OM Control Support. Note: uAP does not support
+        Tx OM received from the STA, as it does not support UL OFDMA)
+
+HE PHY Cap:
+Bit1-7: 0x1 (Supported Channel Width Set)
+Bit8-11: 0x0 (Punctured Preamble Rx)
+Bit12: 0x0 (Device Class)
+Bit13: 0x1 (LDPC coding in Payload)
+Bit17: 0x1 (NDP with 4xLTF+3.2usGI)
+Bit18: 0x1 (STBC Tx <= 80 MHz)
+Bit19: 0x1 (STBC Rx <= 80 MHz)
+Bit20: 0x1 (Doppler Tx)
+Bit21: 0x1 (Doppler Rx)
+Bit24-25: 0x1 (DCM Max Constellation Tx)
+Bit27-28: 0x1 (DCM Max Constellation Rx)
+Bit31: 0x1 (SU Beamformer)
+Bit32: 0x1 (SU BeamFormee)
+Bit34-36: 0x7 (Beamformee STS <= 80 MHz)
+Bit40-42: 0x1 (Number of Sounding Dimentions <= 80 MHz)
+Bit53: 0x1 (Partial Bandwidth Extended Range)
+Bit55: 0x1 (PPE Threshold Present.
+            Note: PPE threshold may have some changes later)
+Bit58: 0x1 (HE SU PPDU and HE MU PPDU with 4xHE-LTF+0.8usGI)
+Bit59-61: 0x1 (Max Nc)
+Bit64: 0x1 (HE ER SU PPDU with 4xHE-LTF+0.8usGI)
+Bit75: 0x1 (Rx 1024-QAM Support < 242-tone RU)
+*/
+#define UAP_HE_2G_MAC_CAP0_MASK  0x04
+#define UAP_HE_2G_MAC_CAP1_MASK  0x00
+#define UAP_HE_2G_MAC_CAP2_MASK  0x10
+#define UAP_HE_2G_MAC_CAP3_MASK  0x02
+#define UAP_HE_2G_MAC_CAP4_MASK  0x00
+#define UAP_HE_2G_MAC_CAP5_MASK  0x00
+#define UAP_HE_2G_PHY_CAP0_MASK  0x02
+#define UAP_HE_2G_PHY_CAP1_MASK  0x20
+#define UAP_HE_2G_PHY_CAP2_MASK  0x3E
+#define UAP_HE_2G_PHY_CAP3_MASK  0x89
+#define UAP_HE_2G_PHY_CAP4_MASK  0x1D
+#define UAP_HE_2G_PHY_CAP5_MASK  0x01
+#define UAP_HE_2G_PHY_CAP6_MASK  0xA0
+#define UAP_HE_2G_PHY_CAP7_MASK  0x0C
+#define UAP_HE_2G_PHY_CAP8_MASK  0x01
+#define UAP_HE_2G_PHY_CAP9_MASK  0x08
+#define UAP_HE_2G_PHY_CAP10_MASK 0x00
+
+/**
+ *  @brief update 11ax ie for AP mode *
+ *  @param band     channel band
+ *  @hecap_ie       a pointer to mlan_ds_11ax_he_capa
+ *
+ *  @return         0--success, otherwise failure
+ */
+static void wifi_uap_update_11ax_ie(t_u8 band, mlan_ds_11ax_he_capa *hecap_ie)
+{
+    if (band == BAND_5GHZ
+#ifdef ENABLE_802_116E
+        || band == BAND_6GHZ
+#endif
+    )
+    {
+        hecap_ie->he_mac_cap[0] &= UAP_HE_MAC_CAP0_MASK;
+        hecap_ie->he_mac_cap[1] &= UAP_HE_MAC_CAP1_MASK;
+        hecap_ie->he_mac_cap[2] &= UAP_HE_MAC_CAP2_MASK;
+        hecap_ie->he_mac_cap[3] &= UAP_HE_MAC_CAP3_MASK;
+        hecap_ie->he_mac_cap[4] &= UAP_HE_MAC_CAP4_MASK;
+        hecap_ie->he_mac_cap[5] &= UAP_HE_MAC_CAP5_MASK;
+        hecap_ie->he_phy_cap[0] &= UAP_HE_PHY_CAP0_MASK;
+        hecap_ie->he_phy_cap[1] &= UAP_HE_PHY_CAP1_MASK;
+        hecap_ie->he_phy_cap[2] &= UAP_HE_PHY_CAP2_MASK;
+        hecap_ie->he_phy_cap[3] &= UAP_HE_PHY_CAP3_MASK;
+        hecap_ie->he_phy_cap[4] &= UAP_HE_PHY_CAP4_MASK;
+        hecap_ie->he_phy_cap[5] &= UAP_HE_PHY_CAP5_MASK;
+        hecap_ie->he_phy_cap[6] &= UAP_HE_PHY_CAP6_MASK;
+        hecap_ie->he_phy_cap[7] &= UAP_HE_PHY_CAP7_MASK;
+        hecap_ie->he_phy_cap[8] &= UAP_HE_PHY_CAP8_MASK;
+        hecap_ie->he_phy_cap[9] &= UAP_HE_PHY_CAP9_MASK;
+        hecap_ie->he_phy_cap[10] &= UAP_HE_PHY_CAP10_MASK;
+    }
+    else
+    {
+        hecap_ie->he_mac_cap[0] &= UAP_HE_2G_MAC_CAP0_MASK;
+        hecap_ie->he_mac_cap[1] &= UAP_HE_2G_MAC_CAP1_MASK;
+        hecap_ie->he_mac_cap[2] &= UAP_HE_2G_MAC_CAP2_MASK;
+        hecap_ie->he_mac_cap[3] &= UAP_HE_2G_MAC_CAP3_MASK;
+        hecap_ie->he_mac_cap[4] &= UAP_HE_2G_MAC_CAP4_MASK;
+        hecap_ie->he_mac_cap[5] &= UAP_HE_2G_MAC_CAP5_MASK;
+        hecap_ie->he_phy_cap[0] &= UAP_HE_2G_PHY_CAP0_MASK;
+        hecap_ie->he_phy_cap[1] &= UAP_HE_2G_PHY_CAP1_MASK;
+        hecap_ie->he_phy_cap[2] &= UAP_HE_2G_PHY_CAP2_MASK;
+        hecap_ie->he_phy_cap[3] &= UAP_HE_2G_PHY_CAP3_MASK;
+        hecap_ie->he_phy_cap[4] &= UAP_HE_2G_PHY_CAP4_MASK;
+        hecap_ie->he_phy_cap[5] &= UAP_HE_2G_PHY_CAP5_MASK;
+        hecap_ie->he_phy_cap[6] &= UAP_HE_2G_PHY_CAP6_MASK;
+        hecap_ie->he_phy_cap[7] &= UAP_HE_2G_PHY_CAP7_MASK;
+        hecap_ie->he_phy_cap[8] &= UAP_HE_2G_PHY_CAP8_MASK;
+        hecap_ie->he_phy_cap[9] &= UAP_HE_2G_PHY_CAP9_MASK;
+        hecap_ie->he_phy_cap[10] &= UAP_HE_2G_PHY_CAP10_MASK;
+    }
+    return;
+}
+
+#if 1
+/**
+ *  @brief Sets up the CFG802.11 specific HE capability fields *  with default
+ * values
+ *
+ *  @param priv         A pointer to moal private structure
+ *  @param iftype_data  A pointer to ieee80211_sband_iftype_data structure
+ *
+ *  @return             N/A
+ */
+int wifi_setup_he_cap(nxp_wifi_he_capabilities *he_cap, t_u8 band)
+{
+    mlan_private *priv = (mlan_private *)mlan_adap->priv[1];
+
+    mlan_fw_info fw_info;
+    t_u8 extra_mcs_size           = 0;
+    int ppe_threshold_len         = 0;
+    mlan_ds_11ax_he_capa *phe_cap = NULL;
+    t_u8 hw_hecap_len             = 0;
+
+    memset(&fw_info, 0, sizeof(mlan_fw_info));
+
+    wifi_request_get_fw_info(priv, &fw_info);
+
+#if CONFIG_5GHz_SUPPORT
+    if (band == BAND_5GHZ)
+    {
+        phe_cap      = (mlan_ds_11ax_he_capa *)fw_info.hw_he_cap;
+        hw_hecap_len = fw_info.hw_hecap_len;
+        wifi_uap_update_11ax_ie(BAND_5GHZ, phe_cap);
+    }
+    else
+#endif
+#ifdef ENABLE_802_116E
+        if (band == BAND_6GHZ)
+    {
+        phe_cap      = (mlan_ds_11ax_he_capa *)fw_info.hw_he_cap;
+        hw_hecap_len = fw_info.hw_hecap_len;
+        wifi_uap_update_11ax_ie(BAND_6GHZ, phe_cap);
+    }
+    else
+#endif
+    {
+        phe_cap      = (mlan_ds_11ax_he_capa *)fw_info.hw_2g_he_cap;
+        hw_hecap_len = fw_info.hw_2g_hecap_len;
+        wifi_uap_update_11ax_ie(BAND_2GHZ, phe_cap);
+    }
+
+    if (!hw_hecap_len)
+        return -WM_FAIL;
+
+    he_cap->he_supported = 1;
+    (void)__memcpy(priv, he_cap->mac_cap, phe_cap->he_mac_cap, sizeof(phe_cap->he_mac_cap));
+    (void)__memcpy(priv, he_cap->phy_cap, phe_cap->he_phy_cap, sizeof(phe_cap->he_phy_cap));
+    memset(&he_cap->mcs, 0xff, WIFI_HE_MAX_MCS_CAPAB_SIZE);
+    (void)__memcpy(priv, &he_cap->mcs, phe_cap->he_txrx_mcs_support, sizeof(phe_cap->he_txrx_mcs_support));
+
+    // Support 160Mhz
+    if (phe_cap->he_phy_cap[0] & MBIT(3))
+        extra_mcs_size += 4;
+
+    // Support 80+80
+    if (phe_cap->he_phy_cap[0] & MBIT(4))
+        extra_mcs_size += 4;
+    if (extra_mcs_size)
+        (void)__memcpy(priv, (t_u8 *)&he_cap->mcs + sizeof(phe_cap->he_txrx_mcs_support), phe_cap->val, extra_mcs_size);
+
+#define HE_CAP_FIX_SIZE 22
+    // Support PPE threshold
+    ppe_threshold_len = phe_cap->len - HE_CAP_FIX_SIZE - extra_mcs_size;
+    if (phe_cap->he_phy_cap[6] & MBIT(7) && ppe_threshold_len)
+    {
+        (void)__memcpy(priv, he_cap->ppet, &phe_cap->val[extra_mcs_size], ppe_threshold_len);
+    }
+    else
+    {
+        he_cap->phy_cap[6] &= ~MBIT(7);
+        wifi_d("Clear PPE threshold 0x%x\r\n", he_cap->phy_cap[7]);
+    }
+#ifdef ENABLE_802_116E
+    if (band->band == BAND_6GHZ)
+        iftype_data->he_6ghz_capa.capa = fw_info.hw_he_6g_cap;
+#endif
+    LEAVE();
+
+    return WM_SUCCESS;
+}
+#else
+/**
+ *  @brief setup uap he_cap based on FW he_cap
+ *
+ *  @param priv         A pointer to moal private structure
+ *  @param wait_option  wait_option
+ *
+ *  @return             N/A
+ */
+void woal_cfg80211_setup_uap_he_cap(moal_private *priv, t_u8 wait_option)
+{
+    mlan_ds_11ax_he_capa *phe_cap = NULL;
+    mlan_ds_11ax_he_cfg he_cfg;
+    t_u8 hw_hecap_len;
+    mlan_fw_info fw_info;
+    int ret = 0;
+
+    woal_request_get_fw_info(priv, MOAL_IOCTL_WAIT, &fw_info);
+
+    // Enable 2G 11AX on UAP
+    if (fw_info.fw_bands & BAND_GAX)
+    {
+        memset(&he_cfg, 0, sizeof(he_cfg));
+        phe_cap      = (mlan_ds_11ax_he_capa *)fw_info.hw_2g_he_cap;
+        hw_hecap_len = fw_info.hw_2g_hecap_len;
+        if (hw_hecap_len)
+        {
+            woal_uap_update_11ax_ie(BAND_2GHZ, phe_cap);
+            he_cfg.band = MBIT(0);
+            moal_memcpy_ext(priv->phandle, &he_cfg.he_cap, phe_cap, hw_hecap_len, sizeof(mlan_ds_11ax_he_capa));
+            DBG_HEXDUMP(MCMD_D, "2G HE_CFG ", (t_u8 *)&he_cfg, sizeof(he_cfg));
+            ret = woal_11ax_cfg(priv, MLAN_ACT_SET, &he_cfg, wait_option);
+            if (ret)
+                PRINTM(MERROR, "Fail to set 2G HE CAP\n");
+        }
+    }
+#ifdef ENABLE_802_11A
+    // Enable 5G 11AX on UAP
+    if (fw_info.fw_bands & BAND_AAX)
+    {
+        memset(&he_cfg, 0, sizeof(he_cfg));
+        phe_cap      = (mlan_ds_11ax_he_capa *)fw_info.hw_he_cap;
+        hw_hecap_len = fw_info.hw_hecap_len;
+        if (hw_hecap_len)
+        {
+            woal_uap_update_11ax_ie(BAND_5GHZ, phe_cap);
+            he_cfg.band = MBIT(1);
+            moal_memcpy_ext(priv->phandle, &he_cfg.he_cap, phe_cap, hw_hecap_len, sizeof(mlan_ds_11ax_he_capa));
+            DBG_HEXDUMP(MCMD_D, "5G HE_CFG ", (t_u8 *)&he_cfg, sizeof(he_cfg));
+            ret = woal_11ax_cfg(priv, MLAN_ACT_SET, &he_cfg, wait_option);
+            if (ret)
+                PRINTM(MERROR, "Fail to set 5G HE CAP\n");
+        }
+    }
+#endif
+    return;
+}
+#endif
+#endif
+
+/**
+ *  @brief Set/Get sta information parameters
+ *
+ *  @param priv             A pointer to moal_private structure
+ *  @param action           MLAN_ACT_SET or MLAN_ACT_GET
+ *  @param wait_option      Wait option
+ *  @param sys_cfg          A pointer to mlan_uap_bss_param structure
+ *
+ *  @return                 MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wifi_uap_sta_info(mlan_private *priv, t_u16 action, mlan_ds_sta_info *sta_info)
+{
+    int ret;
+    mlan_ds_bss bss;
+    mlan_ioctl_req ioctl_buf;
+
+    ENTER();
+
+    (void)memset(&bss, 0x00, sizeof(mlan_ds_bss));
+
+    bss.sub_command = MLAN_OID_UAP_ADD_STATION;
+
+    // if (action == HostCmd_ACT_ADD_STA)
+    memcpy((void *)&bss.param.sta_info, (const void *)sta_info, sizeof(mlan_ds_sta_info) + (size_t)sta_info->tlv_len);
+
+    (void)memset(&ioctl_buf, 0x00, sizeof(mlan_ioctl_req));
+
+    ioctl_buf.req_id = (t_u32)MLAN_IOCTL_BSS;
+    /** Pointer to buffer */
+    ioctl_buf.pbuf = (t_u8 *)&bss;
+
+    ret = wifi_uap_prepare_and_send_cmd(priv, HostCmd_CMD_ADD_NEW_STATION, action, 0, &ioctl_buf, NULL,
+                                        MLAN_BSS_TYPE_UAP, NULL);
+    if (ret != WM_SUCCESS)
+    {
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief uap remove sta
+ *
+ *  @param priv             A pointer to moal_private structure
+ *  @param addr             A pointer to mac address
+ *
+ *  @return                 MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wifi_uap_sta_remove(mlan_private *priv, const uint8_t *addr)
+{
+    int ret;
+    mlan_deauth_param data_buf;
+
+    ENTER();
+
+    (void)memset(&data_buf, 0x00, sizeof(data_buf));
+
+    memcpy((void *)data_buf.mac_addr, (const void *)addr, sizeof(data_buf.mac_addr));
+    data_buf.reason_code = WLAN_REASON_UNSPECIFIED;
+
+    ret = wifi_uap_prepare_and_send_cmd(priv, HOST_CMD_APCMD_STA_DEAUTH, 0, 0, NULL, &data_buf,
+                                        MLAN_BSS_TYPE_UAP, NULL);
+    if (ret != WM_SUCCESS)
+    {
+        return MLAN_STATUS_FAILURE;
+    }
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+int wifi_nxp_sta_add(nxp_wifi_sta_info_t *params)
+{
+    mlan_private *priv         = (mlan_private *)mlan_adap->priv[1];
+    int ret                    = 0;
+    mlan_ds_sta_info *sta_info = NULL;
+    t_u8 *pos;
+    t_u8 qosinfo;
+    MrvlIEtypes_Data_t *tlv;
+    t_u32 req_len = 0;
+#if CONFIG_11AX
+    MrvlExtIEtypes_Data_t *ext_tlv;
+#endif
+
+    ENTER();
+
+    if (!params)
+    {
+        ret = -WM_FAIL;
+        goto done;
+    }
+
+    req_len = sizeof(mlan_ds_sta_info);
+    if (params->ext_capab_len)
+        req_len += sizeof(MrvlIEtypesHeader_t) + params->ext_capab_len;
+    if (params->supp_rates_len)
+        req_len += sizeof(MrvlIEtypesHeader_t) + params->supp_rates_len;
+    if (params->qosinfo)
+        req_len += sizeof(MrvlIEtypesHeader_t) + sizeof(qosinfo);
+    if (params->ht_capab_len)
+        req_len += sizeof(MrvlIEtypesHeader_t) + sizeof(ieee80211_ht_capab_t);
+#if CONFIG_11AC
+    if (params->vht_capab_len)
+        req_len += sizeof(MrvlIEtypesHeader_t) + sizeof(ieee80211_vht_capab_t);
+#endif
+
+#if CONFIG_11AX
+    if (params->he_capab_len)
+        req_len += sizeof(MrvlExtIEtypesHeader_t) + params->he_capab_len;
+#endif
+
+    sta_info = OSA_MemoryAllocate(req_len);
+    if (!sta_info)
+    {
+        wuap_e("Fail to alloc memory for mlan_ds_sta_info");
+        ret = -WM_FAIL;
+        goto done;
+    }
+
+    memset(sta_info, 0x00, req_len);
+
+    sta_info->listen_interval = params->listen_interval;
+    sta_info->aid             = params->aid;
+    sta_info->cap_info        = params->capability;
+    sta_info->tlv_len         = 0;
+    sta_info->sta_flags       = params->flags;
+
+    memcpy(sta_info->peer_mac, params->addr, MLAN_MAC_ADDR_LENGTH);
+
+    wuap_d("wlan: UAP/GO add peer station, address =" MACSTR "", MAC2STR(params->addr));
+
+    wuap_d("sta_flags=0x%x listen_interval=%d aid=%d cap_info=0x%x", params->flags, params->listen_interval,
+           params->aid, params->capability);
+
+    pos = &sta_info->tlv[0];
+    if (params->ext_capab_len)
+    {
+        tlv              = (MrvlIEtypes_Data_t *)pos;
+        tlv->header.type = EXT_CAPABILITY;
+        tlv->header.len  = params->ext_capab_len;
+        memcpy(tlv->data, params->ext_capab, tlv->header.len);
+        pos += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        sta_info->tlv_len += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        tlv = (MrvlIEtypes_Data_t *)pos;
+    }
+    if (params->supp_rates_len)
+    {
+        tlv              = (MrvlIEtypes_Data_t *)pos;
+        tlv->header.type = SUPPORTED_RATES;
+        tlv->header.len  = params->supp_rates_len;
+        memcpy(tlv->data, params->supp_rates, tlv->header.len);
+        pos += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        sta_info->tlv_len += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        tlv = (MrvlIEtypes_Data_t *)pos;
+    }
+    if (params->qosinfo)
+    {
+        tlv              = (MrvlIEtypes_Data_t *)pos;
+        tlv->header.type = QOS_INFO;
+        tlv->header.len  = sizeof(qosinfo);
+        qosinfo          = params->qosinfo;
+        memcpy(tlv->data, &qosinfo, tlv->header.len);
+        pos += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        sta_info->tlv_len += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        tlv = (MrvlIEtypes_Data_t *)pos;
+    }
+    if (params->ht_capab_len)
+    {
+        tlv              = (MrvlIEtypes_Data_t *)pos;
+        tlv->header.type = HT_CAPABILITY;
+        tlv->header.len  = sizeof(ieee80211_ht_capab_t);
+        memcpy(tlv->data, &params->ht_capab, tlv->header.len);
+        pos += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        sta_info->tlv_len += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        tlv = (MrvlIEtypes_Data_t *)pos;
+    }
+#if CONFIG_11AC
+    if (params->vht_capab_len)
+    {
+        tlv              = (MrvlIEtypes_Data_t *)pos;
+        tlv->header.type = VHT_CAPABILITY;
+        tlv->header.len  = sizeof(ieee80211_vht_capab_t);
+        memcpy(tlv->data, &params->vht_capab, tlv->header.len);
+        pos += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        sta_info->tlv_len += sizeof(MrvlIEtypesHeader_t) + tlv->header.len;
+        tlv = (MrvlIEtypes_Data_t *)pos;
+    }
+#endif
+#if CONFIG_11AX
+    if (params->he_capab_len)
+    {
+        ext_tlv                = (MrvlExtIEtypes_Data_t *)pos;
+        ext_tlv->header.type   = EXTENSION;
+        ext_tlv->header.len    = params->he_capab_len + sizeof(u8);
+        ext_tlv->header.ext_id = HE_CAPABILITY;
+        memcpy(ext_tlv->data, (u8 *)&params->he_capab, params->he_capab_len);
+        pos += sizeof(MrvlExtIEtypesHeader_t) + params->he_capab_len;
+        sta_info->tlv_len += sizeof(MrvlExtIEtypesHeader_t) + params->he_capab_len;
+        tlv = (MrvlIEtypes_Data_t *)pos;
+    }
+#endif
+
+    if (MLAN_STATUS_SUCCESS != wifi_uap_sta_info(priv, HostCmd_ACT_ADD_STA, sta_info))
+    {
+        wuap_e("uAP add station failed");
+        ret = -WM_FAIL;
+        goto done;
+    }
+
+done:
+    if (sta_info)
+        OSA_MemoryFree(sta_info);
+
+    LEAVE();
+    return ret;
+}
+
+int wifi_nxp_sta_remove(const uint8_t *addr)
+{
+    mlan_private *priv         = (mlan_private *)mlan_adap->priv[1];
+    int ret                    = 0;
+    mlan_ds_sta_info *sta_info = NULL;
+
+    ENTER();
+
+    if (!addr)
+    {
+        ret = -WM_FAIL;
+        goto done;
+    }
+
+    if (MLAN_STATUS_SUCCESS != wifi_uap_sta_remove(priv, addr))
+    {
+        wuap_e("uAP remove station failed");
+        ret = -WM_FAIL;
+        goto done;
+    }
+
+#if 0
+    sta_info = OSA_MemoryAllocate(sizeof(mlan_ds_sta_info));
+    if (!sta_info)
+    {
+        wuap_e("Fail to alloc memory for mlan_ds_sta_info");
+        ret = -WM_FAIL;
+        goto done;
+    }
+
+    memset(sta_info, 0x00, sizeof(mlan_ds_sta_info));
+
+    memcpy(sta_info->peer_mac, addr, MLAN_MAC_ADDR_LENGTH);
+
+    wuap_d("wlan: UAP/GO remove peer station, address =" MACSTR "", MAC2STR(addr));
+
+    if (MLAN_STATUS_SUCCESS != wifi_uap_sta_info(priv, HostCmd_ACT_REMOVE_STA, sta_info))
+    {
+        wuap_e("uAP remove station failed");
+        ret = -WM_FAIL;
+        goto done;
+    }
+#endif
+
+done:
+#if 0
+    if (sta_info)
+        OSA_MemoryFree(sta_info);
+#endif
+
+    LEAVE();
+    return ret;
+}
+
+int wifi_set_uap_rts(int rts_threshold)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    MrvlIEtypes_rts_threshold_t rts_threshold_tlv;
+
+    (void)memset(&rts_threshold_tlv, 0, sizeof(MrvlIEtypes_rts_threshold_t));
+    rts_threshold_tlv.header.type   = TLV_TYPE_UAP_RTS_THRESHOLD;
+    rts_threshold_tlv.header.len    = (t_u16)sizeof(MrvlIEtypes_rts_threshold_t);
+    rts_threshold_tlv.rts_threshold = (t_u16)rts_threshold;
+
+    int rv = wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_SYS_CONFIGURE, HostCmd_ACT_GEN_SET, 0, MNULL,
+                                           &rts_threshold_tlv, MLAN_BSS_TYPE_UAP, NULL);
+    if (rv != WM_SUCCESS)
+    {
+        return rv;
+    }
+
+    if (wm_wifi.cmd_resp_status != 0)
+    {
+        wifi_w("Unable to set rts threshold");
+        return wm_wifi.cmd_resp_status;
+    }
+
+    return rv;
+}
+
+int wifi_set_uap_frag(int frag_threshold)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    MrvlIEtypes_frag_threshold_t frag_threshold_tlv;
+
+    (void)memset(&frag_threshold_tlv, 0, sizeof(MrvlIEtypes_frag_threshold_t));
+    frag_threshold_tlv.header.type    = TLV_TYPE_UAP_RTS_THRESHOLD;
+    frag_threshold_tlv.header.len     = (t_u16)sizeof(MrvlIEtypes_frag_threshold_t);
+    frag_threshold_tlv.frag_threshold = (t_u16)frag_threshold;
+
+    int rv = wifi_uap_prepare_and_send_cmd(pmpriv, HOST_CMD_APCMD_SYS_CONFIGURE, HostCmd_ACT_GEN_SET, 0, MNULL,
+                                           &frag_threshold_tlv, MLAN_BSS_TYPE_UAP, NULL);
+    if (rv != WM_SUCCESS)
+    {
+        return rv;
+    }
+
+    if (wm_wifi.cmd_resp_status != 0)
+    {
+        wifi_w("Unable to set frag threshold");
+        return wm_wifi.cmd_resp_status;
+    }
+
+    return rv;
+}
+
+void wifi_nxp_uap_disconnect(mlan_private *priv, t_u16 reason_code, t_u8 *mac)
+{
+    wlan_mgmt_pkt *pmgmt_pkt_hdr    = MNULL;
+    nxp_wifi_event_mlme_t *mgmt_rx  = &wm_wifi.mgmt_rx;
+    t_u8 *pos                       = MNULL;
+    t_u16 reason;
+    t_u32 payload_len;
+
+    pmgmt_pkt_hdr = wifi_PrepDefaultMgtMsg(SUBTYPE_DEAUTH, (mlan_802_11_mac_addr *)(void *)priv->curr_addr,
+        (mlan_802_11_mac_addr *)(void *)mac, (mlan_802_11_mac_addr *)(void *)priv->curr_addr, 100);
+    if (pmgmt_pkt_hdr == MNULL)
+    {
+        wifi_e("No memory available for deauth");
+        return;
+    }
+
+    pos = (t_u8 *)pmgmt_pkt_hdr + sizeof(wlan_mgmt_pkt);
+    reason = wlan_cpu_to_le16(reason_code);
+    (void)memcpy(pos, &reason, sizeof(reason));
+    payload_len = sizeof(reason) + sizeof(pmgmt_pkt_hdr->wlan_header);
+
+    if (payload_len <= (int)sizeof(mgmt_rx->frame.frame))
+    {
+        memset(mgmt_rx, 0, sizeof(nxp_wifi_event_mlme_t));
+        mgmt_rx->frame.frame_len = payload_len;
+        (void)memcpy((void *)mgmt_rx->frame.frame, (const void *)(&pmgmt_pkt_hdr->wlan_header), mgmt_rx->frame.frame_len);
+        if (wm_wifi.supp_if_callbk_fns->mgmt_rx_callbk_fn)
+        {
+            wm_wifi.supp_if_callbk_fns->mgmt_rx_callbk_fn(wm_wifi.hapd_if_priv, mgmt_rx, mgmt_rx->frame.frame_len);
+        }
+    }
+    else
+    {
+        wifi_e("Insufficient frame buffer");
+    }
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(pmgmt_pkt_hdr);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, pmgmt_pkt_hdr);
+#endif
+}
+
+int wifi_nxp_stop_ap()
+{
+    mlan_private *priv = (mlan_private *)mlan_adap->priv[1];
+    int ret            = WM_SUCCESS;
+
+    if ((mlan_adap->in_reset == MTRUE) && (priv->media_connected == MFALSE))
+    {
+        return ret;
+    }
+
+    (void)wifi_set_rx_mgmt_indication(MLAN_BSS_TYPE_UAP, 0);
+
+    if (priv->beacon_vendor_index != -1)
+    {
+        ret = wifi_clear_mgmt_ie2(MLAN_BSS_TYPE_UAP, priv->beacon_vendor_index);
+        if (ret != WM_SUCCESS)
+        {
+            wuap_e("Clear uAP vendor IE failed");
+            return -WM_FAIL;
+        }
+        priv->beacon_vendor_index = -1;
+    }
+
+    ret = wifi_nxp_set_mgmt_ies(priv, NULL, 0, NULL, 0, NULL, 0, NULL, 0);
+    if (ret != WM_SUCCESS)
+    {
+        wuap_e("Set uAP mgmt ie failed");
+        ret = -WM_FAIL;
+        goto done;
+    }
+
+    wuap_d("Stopping BSS"); /* Stop BSS */
+    if (MLAN_STATUS_SUCCESS != wifi_uap_prepare_and_send_cmd(priv, HOST_CMD_APCMD_BSS_STOP, HostCmd_ACT_GEN_SET, 0,
+                                                             NULL, NULL, MLAN_BSS_TYPE_UAP, NULL))
+    {
+        wuap_e("Stop BSS failed");
+        return -WM_FAIL;
+    }
+    wifi_uap_clear_domain_info();
+    priv->uap_host_based = MFALSE;
+
+    wuap_d("wlan: AP stopped");
+
+done:
+    LEAVE();
+    return ret;
+}
+
+int wifi_nxp_set_acl(nxp_wifi_acl_info_t *params)
+{
+    mlan_private *priv             = (mlan_private *)mlan_adap->priv[1];
+    int ret                        = -WM_FAIL;
+    mlan_uap_bss_param *sys_config = NULL;
+    bool bss_started               = MFALSE;
+
+    if (!params)
+    {
+        goto done;
+    }
+
+    sys_config = OSA_MemoryAllocate(sizeof(mlan_uap_bss_param));
+
+    if (!sys_config)
+    {
+        wuap_e("Fail to alloc memory for mlan_uap_bss_param");
+        goto done;
+    }
+
+    memset(sys_config, 0x00, sizeof(mlan_uap_bss_param));
+
+    if (params->num_mac_acl <= MAX_MAC_FILTER_NUM)
+        sys_config->filter.mac_count = params->num_mac_acl;
+    else
+        sys_config->filter.mac_count = MAX_MAC_FILTER_NUM;
+
+    if (params->acl_policy == 1U)
+        sys_config->filter.filter_mode = MAC_FILTER_MODE_ALLOW_MAC;
+    else if (params->acl_policy == 0U)
+        sys_config->filter.filter_mode = MAC_FILTER_MODE_BLOCK_MAC;
+    memcpy(sys_config->filter.mac_list, params->mac_acl, sys_config->filter.mac_count * sizeof(mlan_802_11_mac_addr));
+
+    if (priv->uap_host_based == MTRUE)
+    {
+        bss_started = MTRUE;
+
+        if (MLAN_STATUS_SUCCESS != wifi_uap_prepare_and_send_cmd(priv, HOST_CMD_APCMD_BSS_STOP, HostCmd_ACT_GEN_SET, 0,
+                                                                 NULL, NULL, MLAN_BSS_TYPE_UAP, NULL))
+        {
+            wuap_e("Stop BSS failed");
+        }
+    }
+
+    if (MLAN_STATUS_SUCCESS == wifi_set_get_sys_config(priv, MLAN_ACT_SET, sys_config))
+    {
+        ret = WM_SUCCESS;
+    }
+
+    if (bss_started)
+    {
+        if (MLAN_STATUS_SUCCESS != wifi_uap_prepare_and_send_cmd(priv, HOST_CMD_APCMD_BSS_START, HostCmd_ACT_GEN_SET, 0,
+                                                                 NULL, NULL, MLAN_BSS_TYPE_UAP, NULL))
+        {
+            wuap_e("Start BSS failed");
+        }
+    }
+
+done:
+    if (sys_config)
+        OSA_MemoryFree(sys_config);
+
+    LEAVE();
+    return ret;
+}
+
+#endif /* CONFIG_WPA_SUPP_AP */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-wps.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-wps.c
new file mode 100644
index 0000000000..9c763a91a0
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi-wps.c
@@ -0,0 +1,94 @@
+/** @file wifi-wps.c
+ *
+ *  @brief This file provides WPS IE and parser.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mlan_api.h>
+
+#define SC_Device_Password_ID 0x1012
+
+const t_u8 wps_oui[4] = {0x00, 0x50, 0xf2, 0x04};
+
+typedef MLAN_PACK_START struct
+{
+    t_u16 Type;
+    t_u16 Length;
+} MLAN_PACK_END MrvlIEParamSet_t;
+
+/**
+ *  @brief  Parsing Device Password ID
+ *
+ *  @param message      A pointer to buffer for parsing
+ *  @param size         Length of buffer
+ *  @return             Device Password ID
+ */
+static t_u16 wps_parser(t_u8 *message, size_t size)
+{
+    t_u16 device_password_id = 0xffff;
+    MrvlIEParamSet_t *ptlv;
+    t_u8 *plast_byte, *data;
+    t_u16 len;
+
+    /* Beginning from Version, skip IE_ID/Length/SC_OUI field */
+    ptlv       = (MrvlIEParamSet_t *)(message + 4);
+    data       = (t_u8 *)ptlv;
+    plast_byte = (t_u8 *)(message + (t_u8)size);
+
+    while ((void *)ptlv < (void *)plast_byte)
+    {
+		/* Barriers are normally not required but do ensure the code is
+		 * completely within the specified behaviour for the architecture. */
+        __asm volatile ( "dsb" ::: "memory" );
+        __asm volatile ( "isb" );
+
+		ptlv->Type   = mlan_ntohs(ptlv->Type);
+        ptlv->Length = mlan_ntohs(ptlv->Length);
+
+        switch (ptlv->Type)
+        {
+            case SC_Device_Password_ID:
+                wifi_d("SC_Device_Password_ID :: ");
+                memcpy(&device_password_id, data, sizeof(t_u16));
+                device_password_id = mlan_ntohs(device_password_id);
+                wifi_d("device_password_id = 0x%x", device_password_id);
+                break;
+            default:
+                break;
+        }
+
+        len = ptlv->Length + sizeof(MrvlIEParamSet_t);
+
+        ptlv->Type   = mlan_htons(ptlv->Type);
+        ptlv->Length = mlan_htons(ptlv->Length);
+
+        ptlv = (MrvlIEParamSet_t *)((t_u8 *)ptlv + len);
+
+        data = (t_u8 *)ptlv;
+        data += sizeof(MrvlIEParamSet_t);
+    } /* while */
+
+    return device_password_id;
+}
+
+void check_for_wps_ie(
+    const t_u8 *poui, t_u8 oui_type, bool *wps_IE_exist, t_u16 *wps_session, void *element_data, unsigned element_len)
+{
+    if (!memcmp(poui, &wps_oui, sizeof(wps_oui) - 1U) && oui_type == wps_oui[3])
+    {
+        /* WPS IE is present in probe response. */
+        wifi_d("WPS IE :: %x:%x:%x:%x", poui[0], poui[1], poui[2], oui_type);
+
+        *wps_IE_exist = true;
+        *wps_session  = wps_parser(element_data, element_len);
+    }
+    else if (!(*wps_IE_exist))
+    {
+        *wps_IE_exist = false;
+        *wps_session  = 0xffff;
+    }
+}
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi.c
new file mode 100644
index 0000000000..0f37e9aef2
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi.c
@@ -0,0 +1,5068 @@
+/** @file wifi.c
+ *
+ *  @brief  This file provides WiFi Core API
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mlan_api.h>
+
+#include <stdio.h>
+#include <string.h>
+#include <wifi.h>
+#include <osa.h>
+
+#include "wifi-internal.h"
+#include <wm_net.h>
+#if defined(RW610)
+#include "wifi-imu.h"
+#else
+#include <mlan_sdio_api.h>
+#include "wifi-sdio.h"
+#include "mlan_sdio.h"
+#include "sdio.h"
+#include "firmware_dnld.h"
+
+#endif
+#ifdef RW610
+#include "fsl_adapter_imu.h"
+#endif
+
+/* Always keep this include at the end of all include files */
+#include <mlan_remap_mem_operations.h>
+
+#if CONFIG_HEAP_DEBUG
+OSA_SEMAPHORE_HANDLE_DEFINE(os_mem_stat_sem);
+
+t_u32 valid_item_cnt = 0;
+wifi_os_mem_info wifi_os_mem_stat[OS_MEM_STAT_TABLE_SIZE];
+#endif
+
+#if CONFIG_CSI
+#define MAX_CSI_LOCAL_BUF        80
+#define CSI_LOCAL_BUF_ENTRY_SIZE 768
+t_u8 csi_local_buff[MAX_CSI_LOCAL_BUF][CSI_LOCAL_BUF_ENTRY_SIZE] = {
+    0,
+};
+
+csi_local_buff_statu csi_buff_stat = {0, 0, 0};
+
+int csi_event_cnt        = 0;
+t_u64 csi_event_data_len = 0;
+#endif
+
+#if CONFIG_ECSA
+extern wifi_ecsa_status_control ecsa_status_control;
+#endif
+
+#if !CONFIG_WIFI_CORE_STACK_SIZE
+#define CONFIG_WIFI_CORE_STACK_SIZE (2048)
+#endif
+
+#define MAX_MCAST_LEN (MLAN_MAX_MULTICAST_LIST_SIZE * MLAN_MAC_ADDR_LENGTH)
+#define MAX_WAIT_TIME 3000
+
+#ifndef USB_SUPPORT_ENABLE
+#define _T(x) x
+#endif
+
+#if CONFIG_WMM
+#define BOARD_DATA_BUFFER_ALIGN_SIZE 32
+
+SDK_ALIGN(uint8_t outbuf_arr[MAX_WMM_BUF_NUM][OUTBUF_WMM_LEN], BOARD_DATA_BUFFER_ALIGN_SIZE);
+#endif
+
+#define RXPD_CHAN_MASK 0x3FE0
+
+/* Global variable wm_rand_seed */
+uint32_t wm_rand_seed = 0xFFFFFFFFU;
+
+#if CONFIG_WMM
+OSA_SEMAPHORE_HANDLE_DEFINE(txbuf_sem);
+#endif
+
+bool sta_ampdu_tx_enable         = true;
+t_u8 sta_ampdu_tx_enable_per_tid = 0xFF;
+
+bool sta_ampdu_rx_enable         = true;
+t_u8 sta_ampdu_rx_enable_per_tid = 0xFF;
+
+bool uap_ampdu_tx_enable         = true;
+t_u8 uap_ampdu_tx_enable_per_tid = 0xFF;
+
+bool uap_ampdu_rx_enable         = true;
+t_u8 uap_ampdu_rx_enable_per_tid = 0xFF;
+
+/* tx status: 0-RUNNING, 1-BLOCK */
+t_u8 wifi_tx_status = WIFI_DATA_RUNNING;
+/* tx data count blocked */
+t_u8 wifi_tx_block_cnt = 0;
+/* rx status: 0-RUNNING, 1-BLOCK */
+t_u8 wifi_rx_status = WIFI_DATA_RUNNING;
+/* rx data count blocked */
+t_u8 wifi_rx_block_cnt = 0;
+
+int retry_attempts;
+wm_wifi_t wm_wifi;
+static bool xfer_pending;
+static bool scan_thread_in_process = false;
+
+#if CONFIG_HOST_SLEEP
+OSA_SEMAPHORE_HANDLE_DEFINE(wakelock);
+int wakeup_by = 0;
+#endif
+#if CONFIG_WIFI_RECOVERY
+bool wifi_recovery_enable = false;
+t_u16 wifi_recovery_cnt   = 0;
+#endif
+bool wifi_shutdown_enable = false;
+
+typedef enum __mlan_status
+{
+    MLAN_STATUS_FW_DNLD_SKIP = 1,
+    MLAN_CARD_NOT_DETECTED   = 3,
+    MLAN_STATUS_FW_DNLD_FAILED,
+    MLAN_STATUS_FW_NOT_DETECTED,
+    MLAN_STATUS_FW_NOT_READY,
+    MLAN_CARD_CMD_TIMEOUT
+} __mlan_status;
+#ifndef RW610
+
+static void wifi_core_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(wifi_core_task, WLAN_TASK_PRI_HIGH, 1, CONFIG_WIFI_CORE_STACK_SIZE, 0);
+
+#endif
+
+#if !CONFIG_WIFI_SCAN_STACK_SIZE
+#define CONFIG_WIFI_SCAN_STACK_SIZE (2048)
+#endif
+
+static void wifi_scan_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(wifi_scan_task, WLAN_TASK_PRI_LOW, 1, CONFIG_WIFI_SCAN_STACK_SIZE, 0);
+
+#if !CONFIG_WIFI_DRIVER_STACK_SIZE
+#define CONFIG_WIFI_DRIVER_STACK_SIZE (2048)
+#endif
+
+static void wifi_drv_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(wifi_drv_task, WLAN_TASK_PRI_HIGH, 1, CONFIG_WIFI_DRIVER_STACK_SIZE, 0);
+
+#if CONFIG_WMM
+
+#if !CONFIG_WIFI_DRV_TX_STACK_SIZE
+#define CONFIG_WIFI_DRV_TX_STACK_SIZE (2048)
+#endif
+
+static void wifi_drv_tx_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+#ifdef RW610
+static OSA_TASK_DEFINE(wifi_drv_tx_task, WLAN_TASK_PRI_NORMAL, 1, CONFIG_WIFI_DRV_TX_STACK_SIZE, 0);
+#else
+static OSA_TASK_DEFINE(wifi_drv_tx_task, WLAN_TASK_PRI_HIGH, 1, CONFIG_WIFI_DRV_TX_STACK_SIZE, 0);
+#endif
+#endif
+
+#if !CONFIG_WIFI_POWERSAVE_STACK_SIZE
+#define CONFIG_WIFI_POWERSAVE_STACK_SIZE (512)
+#endif
+
+static void wifi_powersave_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(wifi_powersave_task, WLAN_TASK_PRI_LOW, 1, CONFIG_WIFI_POWERSAVE_STACK_SIZE, 0);
+
+int wifi_set_mac_multicast_addr(const char *mlist, t_u32 num_of_addr);
+int wrapper_get_wpa_ie_in_assoc(uint8_t *wpa_ie);
+
+#if CONFIG_HOST_SLEEP
+int wakelock_get(void)
+{
+    int ret = WM_SUCCESS;
+#if CONFIG_POWER_MANAGER
+    ret = OSA_SemaphorePost((osa_semaphore_handle_t)wakelock);
+    if (ret != WM_SUCCESS)
+        wifi_e("Failed to get wakelock");
+#endif
+    return ret;
+}
+
+int wakelock_put(void)
+{
+    int ret = WM_SUCCESS;
+#if CONFIG_POWER_MANAGER
+    ret = OSA_SemaphoreWait((osa_semaphore_handle_t)wakelock, 0);
+    if (ret != WM_SUCCESS)
+        wifi_e("Failed to put wakelock");
+#endif
+    return ret;
+}
+
+int wakelock_isheld(void)
+{
+#if CONFIG_POWER_MANAGER
+    return OSA_MsgQAvailableMsgs((osa_msgq_handle_t)wakelock);
+#else
+    return 1;
+#endif
+}
+#endif
+extern void process_pkt_hdrs(void *pbuf, t_u32 payloadlen, t_u8 interface, t_u8 tid, t_u32 tx_control);
+
+unsigned wifi_get_last_cmd_sent_ms(void)
+{
+    return wm_wifi.last_sent_cmd_msec;
+}
+
+uint32_t wifi_get_value1(void)
+{
+    return wifi_get_device_value1();
+}
+
+/* Wake up Wi-Fi card */
+void wifi_wake_up_card(uint32_t *resp)
+{
+#if CONFIG_WIFI_PS_DEBUG
+    wcmdr_d("Wakeup device...");
+#endif
+
+#ifndef RW610
+    (void)sdio_drv_creg_write(0x0, 1, 0x02, resp);
+#else
+    imu_wakeup_card();
+#endif
+}
+
+/* When Wi-Fi card is in IEEE PS and sleeping
+ * CMD or Data cannot be transmited.
+ * The card must be woken up.
+ * So data or command trasnfer is temporarily kept
+ * in pending state. This function returns value
+ * of pending flag true/false.
+ */
+bool wifi_get_xfer_pending(void)
+{
+    return xfer_pending;
+}
+/*
+ * This function sets the flag value
+ */
+void wifi_set_xfer_pending(bool xfer_val)
+{
+    xfer_pending = xfer_val;
+}
+
+void wifi_update_last_cmd_sent_ms(void)
+{
+    wm_wifi.last_sent_cmd_msec = OSA_TimeGetMsec();
+}
+
+static int wifi_get_command_resp_sem(unsigned long wait)
+{
+    return OSA_SemaphoreWait((osa_semaphore_handle_t)wm_wifi.command_resp_sem, wait);
+}
+
+int wifi_put_command_resp_sem(void)
+{
+    return OSA_SemaphorePost((osa_semaphore_handle_t)wm_wifi.command_resp_sem);
+}
+
+#define WL_ID_WIFI_CMD "wifi_cmd"
+
+int wifi_get_command_lock(void)
+{
+    osa_status_t status;
+
+#if CONFIG_HOST_SLEEP
+    wakelock_get();
+#endif
+    status = OSA_MutexLock((osa_mutex_handle_t)wm_wifi.command_lock, osaWaitForever_c);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_put_command_lock(void)
+{
+    osa_status_t status;
+
+#if CONFIG_HOST_SLEEP
+    wakelock_put();
+#endif
+    status = OSA_MutexUnlock((osa_mutex_handle_t)wm_wifi.command_lock);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+static int wifi_get_mcastf_lock(void)
+{
+    osa_status_t status;
+
+    status = OSA_MutexLock((osa_mutex_handle_t)wm_wifi.mcastf_mutex, osaWaitForever_c);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+static int wifi_put_mcastf_lock(void)
+{
+    osa_status_t status;
+
+    status = OSA_MutexUnlock((osa_mutex_handle_t)wm_wifi.mcastf_mutex);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WIFI_FW_DEBUG
+
+void wifi_register_fw_dump_cb(int (*wifi_usb_mount_cb)(),
+                              int (*wifi_usb_file_open_cb)(char *test_file_name),
+                              int (*wifi_usb_file_write_cb)(uint8_t *data, size_t data_len),
+                              int (*wifi_usb_file_close_cb)())
+{
+    wm_wifi.wifi_usb_mount_cb      = wifi_usb_mount_cb;
+    wm_wifi.wifi_usb_file_open_cb  = wifi_usb_file_open_cb;
+    wm_wifi.wifi_usb_file_write_cb = wifi_usb_file_write_cb;
+    wm_wifi.wifi_usb_file_close_cb = wifi_usb_file_close_cb;
+}
+
+#ifdef SD8801
+
+#define DEBUG_HOST_READY     0xEE
+#define DEBUG_FW_DONE        0xFF
+#define DEBUG_MEMDUMP_FINISH 0xFE
+#define SDIO_SCRATCH_REG     0x60
+#define DEBUG_ITCM_DONE      0xaa
+#define DEBUG_DTCM_DONE      0xbb
+#define DEBUG_SQRAM_DONE     0xcc
+
+#define DEBUG_DUMP_CTRL_REG  0x63
+#define DEBUG_DUMP_FIRST_REG 0x62
+#define DEBUG_DUMP_START_REG 0x64
+#define DEBUG_DUMP_END_REG   0x6a
+#define ITCM_SIZE            0x60000
+
+#define SQRAM_SIZE 0x33500
+
+#define DTCM_SIZE 0x14000
+
+char itcm_dump_file_name[]  = _T("1:/itcm.bin");
+char dtcm_dump_file_name[]  = _T("1:/dtcm.bin");
+char sqram_dump_file_name[] = _T("1:/sqram.bin");
+
+/**
+ *  @brief This function dump firmware memory to file
+ *
+ *  @return         N/A
+ */
+void wifi_dump_firmware_info()
+{
+    int ret = 0;
+    unsigned int reg, reg_start, reg_end;
+    t_u8 ctrl_data = 0;
+    int tries;
+    t_u8 data[8], i;
+    uint32_t resp;
+#ifndef __ZEPHYR__
+    wifi_d("==== DEBUG MODE OUTPUT START: %d ====", OSA_GetTimestamp());
+#endif
+    if (wm_wifi.wifi_usb_file_open_cb != NULL)
+    {
+        ret = wm_wifi.wifi_usb_file_open_cb(itcm_dump_file_name);
+        if (ret != WM_SUCCESS)
+        {
+            wifi_e("File opening failed");
+            goto done;
+        }
+    }
+    else
+    {
+        wifi_e("File open callback is not registered");
+        goto done;
+    }
+#ifndef __ZEPHYR__
+    wifi_d("Start ITCM output %d, please wait...", OSA_GetTimestamp());
+#endif
+    reg_start = DEBUG_DUMP_START_REG;
+    reg_end   = DEBUG_DUMP_END_REG;
+    do
+    {
+        ret = sdio_drv_creg_write(DEBUG_DUMP_CTRL_REG, 1, DEBUG_HOST_READY, &resp);
+        if (!ret)
+        {
+            wifi_e("SDIO Write ERR");
+            goto done;
+        }
+
+        for (tries = 0; tries < MAX_POLL_TRIES; tries++)
+        {
+            ret = sdio_drv_creg_read(DEBUG_DUMP_CTRL_REG, 1, &resp);
+            if (!ret)
+            {
+                wifi_e("SDIO READ ERR");
+                goto done;
+            }
+            ctrl_data = resp & 0xff;
+
+            if ((ctrl_data == DEBUG_FW_DONE) || (ctrl_data == DEBUG_ITCM_DONE) || (ctrl_data == DEBUG_DTCM_DONE) ||
+                (ctrl_data == DEBUG_SQRAM_DONE))
+                break;
+            if (ctrl_data != DEBUG_HOST_READY)
+            {
+                ret = sdio_drv_creg_write(DEBUG_DUMP_CTRL_REG, 1, DEBUG_HOST_READY, &resp);
+                if (!ret)
+                {
+                    wifi_e("SDIO Write ERR");
+                    goto done;
+                }
+            }
+            OSA_TimeDelay(10);
+        }
+        if (ctrl_data == DEBUG_HOST_READY)
+        {
+            wifi_e("Fail to pull ctrl_data");
+            goto done;
+        }
+        reg = DEBUG_DUMP_FIRST_REG;
+        ret = sdio_drv_creg_read(reg, 1, &resp);
+        if (!ret)
+        {
+            wifi_e("SDIO READ ERR");
+            goto done;
+        }
+
+        i = 0;
+        for (reg = reg_start; reg <= reg_end; reg++)
+        {
+            ret = sdio_drv_creg_read(reg, 1, &resp);
+            if (!ret)
+            {
+                wifi_e("SDIO READ ERR");
+                goto done;
+            }
+            data[i++] = resp & 0xff;
+        }
+
+        dump_hex(data, sizeof(data));
+
+        if (wm_wifi.wifi_usb_file_write_cb != NULL)
+        {
+            ret = wm_wifi.wifi_usb_file_write_cb(data, sizeof(data));
+            if (ret != WM_SUCCESS)
+            {
+                wifi_e("File writing failed");
+                goto done;
+            }
+        }
+        else
+        {
+            wifi_e("File write callback is not registered");
+            goto done;
+        }
+        switch (ctrl_data)
+        {
+            case DEBUG_ITCM_DONE:
+                if (wm_wifi.wifi_usb_file_close_cb != NULL)
+                {
+                    ret = wm_wifi.wifi_usb_file_close_cb();
+                    if (ret != WM_SUCCESS)
+                    {
+                        wifi_e("File closing failed");
+                        goto done;
+                    }
+                }
+                else
+                {
+                    wifi_e("File close callback is not registered");
+                    goto done;
+                }
+                if (wm_wifi.wifi_usb_file_open_cb != NULL)
+                {
+                    ret = wm_wifi.wifi_usb_file_open_cb(dtcm_dump_file_name);
+                    if (ret != WM_SUCCESS)
+                    {
+                        wifi_e("File opening failed");
+                        goto done;
+                    }
+#ifndef __ZEPHYR__
+                    wifi_d("Start DTCM output %d, please wait...", OSA_GetTimestamp());
+#endif
+                }
+                else
+                {
+                    wifi_e("USB open callback is not registered");
+                    goto done;
+                }
+                break;
+            case DEBUG_DTCM_DONE:
+                if (wm_wifi.wifi_usb_file_close_cb != NULL)
+                {
+                    ret = wm_wifi.wifi_usb_file_close_cb();
+                    if (ret != WM_SUCCESS)
+                    {
+                        wifi_e("File closing failed");
+                        goto done;
+                    }
+                }
+                else
+                {
+                    wifi_e("File close callback is not registered");
+                    goto done;
+                }
+                if (wm_wifi.wifi_usb_file_open_cb != NULL)
+                {
+                    ret = wm_wifi.wifi_usb_file_open_cb(sqram_dump_file_name);
+                    if (ret != WM_SUCCESS)
+                    {
+                        wifi_e("File opening failed");
+                        goto done;
+                    }
+#ifndef __ZEPHYR__
+                    wifi_d("Start SQRAM output %u.%06u, please wait...", OSA_GetTimestamp());
+#endif
+                }
+                else
+                {
+                    wifi_e("USB open cb is not registered");
+                    goto done;
+                }
+                break;
+            case DEBUG_SQRAM_DONE:
+                if (wm_wifi.wifi_usb_file_close_cb != NULL)
+                {
+                    ret = wm_wifi.wifi_usb_file_close_cb();
+                    if (ret != WM_SUCCESS)
+                    {
+                        wifi_e("File closing failed");
+                        goto done;
+                    }
+                    wifi_d("End output!");
+                }
+                else
+                {
+                    wifi_e("File close callback is not registered");
+                    goto done;
+                }
+                break;
+            default:
+                wifi_d("Unexpected wifi debug \n");
+                break;
+        }
+    } while (ctrl_data != DEBUG_SQRAM_DONE);
+
+    wifi_d("The output ITCM/DTCM/SQRAM have been saved to files successfully!");
+    /* end dump fw memory */
+done:
+#ifndef __ZEPHYR__
+    wifi_d("==== DEBUG MODE OUTPUT END: %d ====\n", OSA_GetTimestamp());
+#endif
+
+    while (1)
+        ;
+}
+
+#ifndef RW610
+/**
+ *  @brief This function reads and displays SDIO registers for debugging
+ *
+ *  @return         N/A
+ */
+void wifi_sdio_reg_dbg()
+{
+    int ret = 0;
+    t_u8 loop, index = 0, func, data;
+    unsigned int reg, reg_start, reg_end;
+    unsigned int scratch_reg = SDIO_SCRATCH_REG;
+    unsigned int reg_table[] = {0x28, 0x30, 0x34, 0x38, 0x3c};
+    char buf[256], *ptr;
+    uint32_t resp;
+
+    for (loop = 0; loop < 5; loop++)
+    {
+        (void)memset(buf, 0, sizeof(buf));
+        ptr = buf;
+        if (loop == 0)
+        {
+            /* Read the registers of SDIO function0 */
+            func      = loop;
+            reg_start = 0;
+            reg_end   = 9;
+        }
+        else if (loop == 1)
+        {
+            /* Read the registers of SDIO function1 */
+            func      = loop;
+            reg_start = 4;
+            reg_end   = 9;
+        }
+        else if (loop == 2)
+        {
+            /* Read specific registers of SDIO function1 */
+            index     = 0;
+            func      = 1;
+            reg_start = reg_table[index++];
+            reg_end   = reg_table[ARRAY_SIZE(reg_table) - 1];
+        }
+        else
+        {
+            /* Read the scratch registers of SDIO function1 */
+            if (loop == 4)
+                OSA_TimeDelay(1);
+            func      = 1;
+            reg_start = scratch_reg;
+            reg_end   = scratch_reg + 10;
+        }
+        if (loop != 2)
+            ptr += sprintf(ptr, "SDIO Func%d (%#x-%#x): ", func, reg_start, reg_end);
+        else
+            ptr += sprintf(ptr, "SDIO Func%d: ", func);
+        for (reg = reg_start; reg <= reg_end;)
+        {
+#ifndef RW610
+            ret = sdio_drv_creg_read(reg, func, &resp);
+#endif
+            data = resp & 0xff;
+            if (loop == 2)
+                ptr += sprintf(ptr, "(%#x) ", reg);
+            if (!ret)
+                ptr += sprintf(ptr, "%02x ", data);
+            else
+            {
+                ptr += sprintf(ptr, "ERR");
+                break;
+            }
+            if (loop == 2 && reg < reg_end)
+                reg = reg_table[index++];
+            else
+                reg++;
+        }
+        wifi_d("%s", buf);
+    }
+}
+#endif
+#elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || \
+    defined(SD9177) || defined(RW610_SERIES)
+
+#define DEBUG_HOST_READY     0xCC
+#define DEBUG_FW_DONE        0xFF
+#define DEBUG_MEMDUMP_FINISH 0xFE
+
+#define DEBUG_DUMP_CTRL_REG    0xF9
+#define DEBUG_DUMP_START_REG   0xF1
+#define DEBUG_DUMP_END_REG     0xF8
+#define SDIO_SCRATCH_REG       0xE8
+#define DEBUG_DUMP_SCRATCH_REG (void *)0x41382488
+
+char fw_dump_file_name[] = _T("1:/fw_dump.bin");
+
+typedef enum
+{
+    DUMP_TYPE_ITCM        = 0,
+    DUMP_TYPE_DTCM        = 1,
+    DUMP_TYPE_SQRAM       = 2,
+    DUMP_TYPE_APU_REGS    = 3,
+    DUMP_TYPE_CIU_REGS    = 4,
+    DUMP_TYPE_ICU_REGS    = 5,
+    DUMP_TYPE_MAC_REGS    = 6,
+    DUMP_TYPE_EXTEND_7    = 7,
+    DUMP_TYPE_EXTEND_8    = 8,
+    DUMP_TYPE_EXTEND_9    = 9,
+    DUMP_TYPE_EXTEND_10   = 10,
+    DUMP_TYPE_EXTEND_11   = 11,
+    DUMP_TYPE_EXTEND_12   = 12,
+    DUMP_TYPE_EXTEND_13   = 13,
+    DUMP_TYPE_EXTEND_LAST = 14
+} dumped_mem_type;
+
+#define MAX_NAME_LEN      8
+#define MAX_FULL_NAME_LEN 32
+
+typedef struct
+{
+    t_u8 mem_name[MAX_NAME_LEN];
+    t_u8 *mem_Ptr;
+    struct file *pfile_mem;
+    t_u8 done_flag;
+    t_u8 type;
+} memory_type_mapping;
+
+memory_type_mapping mem_type_mapping_tbl = {"DUMP", NULL, NULL, 0xDD};
+
+typedef enum
+{
+    RDWR_STATUS_SUCCESS = 0,
+    RDWR_STATUS_FAILURE = 1,
+    RDWR_STATUS_DONE    = 2
+} rdwr_status;
+
+/**
+ *  @brief This function read/write firmware via cmd52
+ *
+ *  @param doneflag  A flag
+ *
+ *  @return         MLAN_STATUS_SUCCESS
+ */
+rdwr_status wifi_cmd52_rdwr_firmware(t_u8 doneflag)
+{
+    int ret                = 0;
+    int tries              = 0;
+    t_u8 ctrl_data         = 0;
+    t_u8 dbg_dump_ctrl_reg = 0;
+    t_u8 debug_host_ready  = 0;
+    uint32_t resp;
+
+    dbg_dump_ctrl_reg = DEBUG_DUMP_CTRL_REG;
+    debug_host_ready  = DEBUG_HOST_READY;
+
+    ret = sdio_drv_creg_write(dbg_dump_ctrl_reg, 1, debug_host_ready, &resp);
+    if (!ret)
+    {
+        wifi_e("SDIO Write ERR");
+        return RDWR_STATUS_FAILURE;
+    }
+    for (tries = 0; tries < MAX_POLL_TRIES; tries++)
+    {
+        ret = sdio_drv_creg_read(dbg_dump_ctrl_reg, 1, &resp);
+        if (!ret)
+        {
+            wifi_e("SDIO READ ERR");
+            return RDWR_STATUS_FAILURE;
+        }
+        ctrl_data = resp & 0xff;
+        if (ctrl_data == DEBUG_FW_DONE)
+            break;
+        if (doneflag && ctrl_data == doneflag)
+            return RDWR_STATUS_DONE;
+        if (ctrl_data != debug_host_ready)
+        {
+            ret = sdio_drv_creg_write(dbg_dump_ctrl_reg, 1, debug_host_ready, &resp);
+            if (!ret)
+            {
+                wifi_e("SDIO Write ERR");
+                return RDWR_STATUS_FAILURE;
+            }
+        }
+        OSA_TimeDelay(1);
+    }
+    if (ctrl_data == debug_host_ready)
+    {
+        wifi_e("Fail to pull ctrl_data");
+        return RDWR_STATUS_FAILURE;
+    }
+
+    return RDWR_STATUS_SUCCESS;
+}
+
+/**
+ *  @brief This function dump firmware memory to file
+ *
+ *  @return         N/A
+ */
+void wifi_dump_firmware_info()
+{
+    int ret   = 0;
+    int tries = 0;
+    unsigned int reg, reg_start, reg_end;
+    t_u8 start_flag = 0;
+    t_u8 doneflag   = 0;
+    rdwr_status stat;
+    t_u8 dbg_dump_start_reg                    = 0;
+    t_u8 dbg_dump_end_reg                      = 0;
+    memory_type_mapping *pmem_type_mapping_tbl = &mem_type_mapping_tbl;
+    t_u8 data[8], i;
+    uint32_t resp;
+
+    dbg_dump_start_reg = DEBUG_DUMP_START_REG;
+    dbg_dump_end_reg   = DEBUG_DUMP_END_REG;
+
+#ifndef __ZEPHYR__
+    wifi_d("==== DEBUG MODE OUTPUT START: %d.%06u ====", OSA_GetTimestamp());
+#endif
+    /* read the number of the memories which will dump */
+    if (RDWR_STATUS_FAILURE == wifi_cmd52_rdwr_firmware(doneflag))
+        goto done;
+
+    /** check the reg which indicate dump starting */
+    for (reg = dbg_dump_start_reg; reg <= dbg_dump_end_reg; reg++)
+    {
+        for (tries = 0; tries < MAX_POLL_TRIES; tries++)
+        {
+            ret = sdio_drv_creg_read(reg, 1, &resp);
+            if (!ret)
+            {
+                wifi_e("SDIO READ ERR");
+                goto done;
+            }
+            start_flag = resp & 0xff;
+            /** 0 means dump starting*/
+            if (start_flag == 0)
+                break;
+            OSA_TimeDelay(1);
+        }
+        if (tries == MAX_POLL_TRIES)
+        {
+            wifi_d("FW not ready to dump");
+            goto done;
+        }
+    }
+    if (wm_wifi.wifi_usb_file_open_cb != NULL)
+    {
+        ret = wm_wifi.wifi_usb_file_open_cb(fw_dump_file_name);
+        if (ret != WM_SUCCESS)
+        {
+            wifi_e("File opening failed");
+            goto done;
+        }
+    }
+    else
+    {
+        wifi_e("File open callback is not registered");
+        goto done;
+    }
+
+    doneflag = pmem_type_mapping_tbl->done_flag;
+#ifndef __ZEPHYR__
+    wifi_d("Start %s output %d, please wait...", pmem_type_mapping_tbl->mem_name, OSA_GetTimestamp());
+#endif
+    do
+    {
+        stat = wifi_cmd52_rdwr_firmware(doneflag);
+        if (RDWR_STATUS_FAILURE == stat)
+            goto done;
+
+        reg_start = dbg_dump_start_reg;
+        reg_end   = dbg_dump_end_reg;
+        i         = 0;
+        for (reg = reg_start; reg <= reg_end; reg++)
+        {
+            ret = sdio_drv_creg_read(reg, 1, &resp);
+            if (!ret)
+            {
+                wifi_e("SDIO READ ERR");
+                goto done;
+            }
+            data[i++] = (resp & 0xff);
+        }
+        if (wm_wifi.wifi_usb_file_write_cb != NULL)
+        {
+            ret = wm_wifi.wifi_usb_file_write_cb(data, sizeof(data));
+            if (ret != WM_SUCCESS)
+            {
+                wifi_e("File writing failed");
+                goto done;
+            }
+        }
+        else
+        {
+            wifi_e("File write callback is not registered");
+            goto done;
+        }
+
+        if (RDWR_STATUS_DONE == stat)
+        {
+            if (wm_wifi.wifi_usb_file_close_cb != NULL)
+            {
+                ret = wm_wifi.wifi_usb_file_close_cb();
+                if (ret != WM_SUCCESS)
+                {
+                    wifi_e("File closing failed");
+                    goto done;
+                }
+            }
+            else
+            {
+                wifi_e("File close callback is not registered");
+                goto done;
+            }
+            break;
+        }
+    } while (1);
+
+#ifndef __ZEPHYR__
+    wifi_d("==== DEBUG MODE OUTPUT END: %d ====\n", OSA_GetTimestamp());
+#endif
+    /* end dump fw memory */
+done:
+    while (1)
+        ;
+}
+
+#ifndef RW610
+/**
+ *  @brief This function reads and displays SDIO registers for debugging
+ *
+ *  @return         N/A
+ */
+void wifi_sdio_reg_dbg()
+{
+    int ret = 0;
+    t_u8 loop, index = 0, func, data;
+    unsigned int reg, reg_start, reg_end;
+    unsigned int scratch_reg = SDIO_SCRATCH_REG;
+    unsigned int reg_table[] = {0x08, 0x58, 0x5C, 0x5D, 0x60, 0x61, 0x62, 0x64, 0x65, 0x66, 0x68, 0x69, 0x6a};
+    char buf[256], *ptr;
+    uint32_t resp;
+
+    for (loop = 0; loop < 5; loop++)
+    {
+        (void)memset(buf, 0, sizeof(buf));
+        ptr = buf;
+        if (loop == 0)
+        {
+            /* Read the registers of SDIO function0 */
+            func      = loop;
+            reg_start = 0;
+            reg_end   = 9;
+        }
+        else if (loop == 1)
+        {
+            /* Read the registers of SDIO function1 */
+            func      = loop;
+            reg_start = 0x10;
+            reg_end   = 0x17;
+        }
+        else if (loop == 2)
+        {
+            /* Read specific registers of SDIO function1 */
+            index     = 0;
+            func      = 1;
+            reg_start = reg_table[index++];
+            reg_end   = reg_table[ARRAY_SIZE(reg_table) - 1];
+        }
+        else
+        {
+            /* Read the scratch registers of SDIO function1 */
+            if (loop == 4)
+                OSA_TimeDelay(1);
+            func      = 1;
+            reg_start = scratch_reg;
+            reg_end   = scratch_reg + 10;
+        }
+        if (loop != 2)
+            ptr += sprintf(ptr, "SDIO Func%d (%#x-%#x): ", func, reg_start, reg_end);
+        else
+            ptr += sprintf(ptr, "SDIO Func%d: ", func);
+        for (reg = reg_start; reg <= reg_end;)
+        {
+            ret  = sdio_drv_creg_read(reg, func, &resp);
+            data = resp & 0xff;
+            if (loop == 2)
+                ptr += sprintf(ptr, "(%#x) ", reg);
+            if (ret)
+                ptr += sprintf(ptr, "%02x ", data);
+            else
+            {
+                ptr += sprintf(ptr, "ERR");
+                break;
+            }
+            if (loop == 2 && reg < reg_end)
+                reg = reg_table[index++];
+            else
+                reg++;
+        }
+        wifi_d("%s", buf);
+    }
+}
+#endif
+
+#elif defined(RW610)
+/**
+ *  @brief This function dump firmware memory to file
+ *
+ *  @return         N/A
+ */
+void wifi_dump_firmware_info()
+{
+    /*Dummy for RW610 */
+}
+
+#endif
+#endif
+
+#if CONFIG_FW_VDLL
+int wifi_wait_for_vdllcmdresp(void *cmd_resp_priv)
+{
+    int ret                 = WM_SUCCESS;
+    HostCmd_DS_COMMAND *cmd = wifi_get_vdllcommand_buffer();
+#ifndef RW610
+    t_u32 buf_len = MLAN_SDIO_BLOCK_SIZE;
+    t_u32 tx_blocks;
+#endif
+
+#ifndef RW610
+#if (CONFIG_WIFI_CMD_RESP_DEBUG) && (CONFIG_FW_VDLL_DEBUG)
+
+    wcmdr_d("VDLL CMD --- : 0x%x Size: %d Seq: %x", cmd->command, cmd->size, cmd->seq_num);
+#endif /* CONFIG_ENABLE_WARNING_LOGS || CONFIG_WIFI_CMD_RESP_DEBUG*/
+#endif
+    if (cmd->size > WIFI_FW_CMDBUF_SIZE)
+    {
+        /*
+         * This is a error added to be flagged during
+         * development cycle. It is not expected to
+         * occur in production. The legacy code below
+         * only sents out MLAN_SDIO_BLOCK_SIZE or 2 *
+         * MLAN_SDIO_BLOCK_SIZE sized packet. If ever
+         * in future greater packet size generated then
+         * this error will help to localize the problem.
+         */
+        wifi_e("cmd size greater than WIFI_FW_CMDBUF_SIZE\r\n");
+        return -WM_FAIL;
+    }
+
+#ifndef RW610
+    tx_blocks = ((t_u32)cmd->size + MLAN_SDIO_BLOCK_SIZE - 1U) / MLAN_SDIO_BLOCK_SIZE;
+#endif
+
+#if defined(RW610)
+    (void)wifi_send_cmdbuffer();
+#else
+    (void)wifi_send_vdllcmdbuffer(tx_blocks, buf_len);
+#endif
+
+    return ret;
+}
+#endif
+
+#if (CONFIG_WIFI_IND_DNLD)
+static int wifi_reinit(uint8_t fw_reload);
+t_u8 wifi_rx_block_cnt;
+t_u8 wifi_tx_block_cnt;
+
+void wlan_process_hang(uint8_t fw_reload)
+{
+    int i, ret = WM_SUCCESS;
+
+    if (mlan_adap->in_reset == true)
+    {
+        wifi_d("Already in process hanging");
+        return;
+    }
+
+    wifi_d("Start to process hanging");
+
+#if CONFIG_WIFI_IND_RESET
+    wifi_ind_reset_start();
+#endif
+
+    /* Block TX data */
+    wifi_set_tx_status(WIFI_DATA_BLOCK);
+    /* Block RX data */
+    wifi_set_rx_status(WIFI_DATA_BLOCK);
+
+    if (is_split_scan_complete() == false)
+    {
+        wifi_user_scan_config_cleanup();
+        (void)wifi_event_completion(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_FAILURE, NULL);
+    }
+
+    mlan_adap->in_reset = true;
+    for (i = 0; i < (int)(MIN(MLAN_MAX_BSS_NUM, mlan_adap->priv_num)); i++)
+    {
+        if (mlan_adap->priv[i]->media_connected == MTRUE)
+        {
+            mlan_adap->priv[i]->media_connected = MFALSE;
+
+            if (mlan_adap->priv[i]->bss_type == MLAN_BSS_TYPE_STA)
+            {
+            }
+            else if (mlan_adap->priv[i]->bss_type == MLAN_BSS_TYPE_UAP)
+            {
+                mlan_adap->priv[i]->uap_bss_started = MFALSE;
+            }
+        }
+
+        if (mlan_adap->priv[i])
+        {
+            wlan_clean_txrx(mlan_adap->priv[i]);
+        }
+    }
+
+    (void)wifi_event_completion(WIFI_EVENT_FW_HANG, WIFI_EVENT_REASON_SUCCESS, NULL);
+
+    ret = wifi_reinit(fw_reload);
+
+    if (ret != WM_SUCCESS)
+    {
+        ASSERT(0);
+    }
+
+    /* Unblock TX data */
+    wifi_set_tx_status(WIFI_DATA_RUNNING);
+    /* Unblock RX data */
+    wifi_set_rx_status(WIFI_DATA_RUNNING);
+    mlan_adap->in_reset = false;
+    wifi_tx_block_cnt   = 0;
+    wifi_rx_block_cnt   = 0;
+
+    (void)wifi_event_completion(WIFI_EVENT_FW_RESET, WIFI_EVENT_REASON_SUCCESS, NULL);
+
+}
+#endif
+
+int wifi_wait_for_cmdresp(void *cmd_resp_priv)
+{
+    int ret;
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+#ifndef RW610
+    t_u32 buf_len = MLAN_SDIO_BLOCK_SIZE;
+    t_u32 tx_blocks;
+#endif
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[0];
+    mlan_adapter *pmadapter = pmpriv->adapter;
+
+#ifndef RW610
+#if (CONFIG_ENABLE_WARNING_LOGS) || (CONFIG_WIFI_CMD_RESP_DEBUG)
+
+#if !CONFIG_WIFI_PS_DEBUG
+    if (cmd->command != HostCmd_CMD_802_11_PS_MODE_ENH)
+    {
+        wcmdr_d("CMD --- : 0x%x Size: %d Seq: %d", cmd->command, cmd->size, cmd->seq_num);
+    }
+#else
+    wcmdr_d("CMD --- : 0x%x Size: %d Seq: %d", cmd->command, cmd->size, cmd->seq_num);
+#endif
+
+#endif /* CONFIG_ENABLE_WARNING_LOGS || CONFIG_WIFI_CMD_RESP_DEBUG*/
+#endif
+
+#if CONFIG_WIFI_IND_RESET
+    /* IR is in progress so any CMD coming during progress should be ignored */
+    if (wifi_ind_reset_in_progress() == true)
+    {
+        (void)wifi_put_command_lock();
+        return WM_SUCCESS;
+    }
+#endif
+
+#if CONFIG_FW_VDLL
+    while (pmadapter->vdll_in_progress == MTRUE)
+    {
+        OSA_TimeDelay(50);
+    }
+#endif
+
+    if (cmd->size > WIFI_FW_CMDBUF_SIZE)
+    {
+        /*
+         * This is a error added to be flagged during
+         * development cycle. It is not expected to
+         * occur in production. The legacy code below
+         * only sents out MLAN_SDIO_BLOCK_SIZE or 2 *
+         * MLAN_SDIO_BLOCK_SIZE sized packet. If ever
+         * in future greater packet size generated then
+         * this error will help to localize the problem.
+         */
+        wifi_e("cmd size greater than WIFI_FW_CMDBUF_SIZE\r\n");
+
+        (void)wifi_put_command_lock();
+        return -WM_FAIL;
+    }
+
+#if CONFIG_WIFI_RECOVERY
+    if (wifi_recovery_enable)
+    {
+        wifi_w("Recovery in progress. command 0x%x skipped", cmd->command);
+
+        wifi_put_command_lock();
+        return -WM_FAIL;
+    }
+#endif
+    if (wifi_shutdown_enable)
+    {
+        wifi_w("FW shutdown in progress. command 0x%x skipped", cmd->command);
+
+        wifi_put_command_lock();
+        return -WM_FAIL;
+    }
+
+#ifndef RW610
+    tx_blocks = ((t_u32)cmd->size + MLAN_SDIO_BLOCK_SIZE - 1U) / MLAN_SDIO_BLOCK_SIZE;
+#endif
+
+#if !CONFIG_UART_WIFI_BRIDGE
+    ret = OSA_RWLockReadLock(&sleep_rwlock, MAX_WAIT_TIME);
+    if (ret != WM_SUCCESS)
+    {
+#if CONFIG_WIFI_PS_DEBUG
+        wifi_e("Failed to wakeup card");
+#endif
+
+        // wakelock_put(WL_ID_LL_OUTPUT);
+        (void)wifi_put_command_lock();
+#if CONFIG_WIFI_RECOVERY
+        wifi_recovery_enable = true;
+        return -WM_FAIL;
+#else
+        assert(0);
+#endif
+    }
+#endif
+#if CONFIG_WMM_UAPSD
+    /*
+     * No PS handshake between driver and FW for the uapsd case,
+     * CMD should not wakeup FW, needs to wait to send till receiving PS_AWAKE Event from FW.
+     */
+    OSA_SemaphoreWait((osa_semaphore_handle_t)uapsd_sem, osaWaitForever_c);
+#endif
+    /*
+     * This is the private pointer. Only the command response handler
+     * function knows what it means or where it points to. It can be
+     * NULL.
+     */
+    wm_wifi.cmd_resp_priv = cmd_resp_priv;
+#if defined(RW610)
+    (void)wifi_send_cmdbuffer();
+#else
+    (void)wifi_send_cmdbuffer(tx_blocks, buf_len);
+#endif
+#if !CONFIG_UART_WIFI_BRIDGE
+    /* put the sleep_rwlock after send command but not wait for the command response,
+     * for sleep confirm command, sleep confirm response(in wifi_process_ps_enh_response())
+     * would try to get the sleep_rwlock until get it,
+     * so here put the sleep_rwlock as early as possible.
+     */
+    (void)OSA_RWLockReadUnlock(&sleep_rwlock);
+#endif
+
+    pmadapter->cmd_sent = MTRUE;
+
+    /* Wait max 20 sec for the command response */
+    ret = wifi_get_command_resp_sem(WIFI_COMMAND_RESPONSE_WAIT_MS);
+    if (ret != WM_SUCCESS)
+    {
+        pmadapter->cmd_sent = MFALSE;
+#if CONFIG_ENABLE_WARNING_LOGS
+        t_u32 outbuf_len = 0;
+        HostCmd_DS_COMMAND *tmo_cmd =
+            (HostCmd_DS_COMMAND *)((t_u8 *)wifi_get_outbuf((uint32_t *)(&outbuf_len)) + INTF_HEADER_LEN);
+        wifi_w("Command response timed out. command 0x%x, len %d, seqno 0x%x", tmo_cmd->command, tmo_cmd->size,
+               tmo_cmd->seq_num);
+#endif /* CONFIG_ENABLE_WARNING_LOGS */
+#if CONFIG_WIFI_FW_DEBUG
+#ifndef RW610
+        wifi_sdio_reg_dbg();
+        if (wm_wifi.wifi_usb_mount_cb != NULL)
+        {
+            ret = wm_wifi.wifi_usb_mount_cb();
+            if (ret == WM_SUCCESS)
+                wifi_dump_firmware_info();
+            else
+            {
+                wifi_e("USB mounting failed");
+            }
+        }
+        else
+            wifi_e("USB mount callback is not registered");
+#else
+        wifi_dump_firmware_info();
+#endif
+#endif
+#if CONFIG_WIFI_RECOVERY
+        wifi_recovery_enable = true;
+#else
+        /* assert as command flow cannot work anymore */
+#if (CONFIG_WIFI_IND_DNLD)
+        wlan_process_hang(FW_RELOAD_SDIO_INBAND_RESET);
+#else
+        ASSERT(0);
+#endif
+#endif
+    }
+
+    if (cmd->command == HostCmd_CMD_FUNC_SHUTDOWN)
+    {
+        wifi_shutdown_enable = true;
+    }
+
+    wm_wifi.cmd_resp_priv = NULL;
+#if CONFIG_WMM_UAPSD
+    OSA_SemaphorePost((osa_semaphore_handle_t)uapsd_sem);
+#endif
+    wifi_set_xfer_pending(false);
+
+    (void)wifi_put_command_lock();
+    return ret;
+}
+
+
+int wifi_event_completion(enum wifi_event event, enum wifi_event_reason result, void *data)
+{
+    struct wifi_message msg;
+    if (wm_wifi.wlc_mgr_event_queue == MNULL)
+    {
+        wifi_e("wlc_mgr_event_queue has not been created, event %d", event);
+        return -WM_FAIL;
+    }
+
+    msg.data   = data;
+    msg.reason = result;
+    msg.event  = (uint16_t)event;
+    if (OSA_MsgQPut((osa_msgq_handle_t)wm_wifi.wlc_mgr_event_queue, &msg) != KOSA_StatusSuccess)
+    {
+        wifi_e("Failed to send response on Queue, event %d", event);
+        return -WM_FAIL;
+    }
+    return WM_SUCCESS;
+}
+
+static int cmp_mac_addr(uint8_t *mac_addr1, uint8_t *mac_addr2)
+{
+    int i = 0;
+
+    if ((mac_addr1 == MNULL) || (mac_addr2 == MNULL))
+    {
+        return 1;
+    }
+
+    for (i = 0; i < MLAN_MAC_ADDR_LENGTH; i++)
+    {
+        if (mac_addr1[i] != mac_addr2[i])
+        {
+            return 1;
+        }
+    }
+    return 0;
+}
+
+static int add_mcast_ip(uint8_t *mac_addr)
+{
+    mcast_filter *node_t, *new_node;
+    (void)wifi_get_mcastf_lock();
+    node_t = wm_wifi.start_list;
+    if (wm_wifi.start_list == NULL)
+    {
+#if !CONFIG_MEM_POOLS
+        new_node = OSA_MemoryAllocate(sizeof(mcast_filter));
+#else
+        new_node = (mcast_filter *)OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+        if (new_node == NULL)
+        {
+            (void)wifi_put_mcastf_lock();
+            return -WM_FAIL;
+        }
+        (void)memcpy((void *)new_node->mac_addr, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+        new_node->next     = NULL;
+        wm_wifi.start_list = new_node;
+        (void)wifi_put_mcastf_lock();
+        return WM_SUCCESS;
+    }
+    while (node_t->next != NULL && cmp_mac_addr(node_t->mac_addr, mac_addr))
+    {
+        node_t = node_t->next;
+    }
+
+    if (!cmp_mac_addr(node_t->mac_addr, mac_addr))
+    {
+        (void)wifi_put_mcastf_lock();
+        return -WM_E_EXIST;
+    }
+#if !CONFIG_MEM_POOLS
+    new_node = OSA_MemoryAllocate(sizeof(mcast_filter));
+#else
+    new_node = (mcast_filter *)OSA_MemoryPoolAllocate(buf_32_MemoryPool);
+#endif
+    if (new_node == NULL)
+    {
+        (void)wifi_put_mcastf_lock();
+        return -WM_FAIL;
+    }
+    (void)memcpy((void *)new_node->mac_addr, (const void *)mac_addr, MLAN_MAC_ADDR_LENGTH);
+    new_node->next = NULL;
+    node_t->next   = new_node;
+    (void)wifi_put_mcastf_lock();
+    return WM_SUCCESS;
+}
+
+static int remove_mcast_ip(uint8_t *mac_addr)
+{
+    mcast_filter *curr_node, *prev_node;
+    (void)wifi_get_mcastf_lock();
+    if (wm_wifi.start_list == NULL)
+    {
+        (void)wifi_put_mcastf_lock();
+        return -WM_FAIL;
+    }
+    curr_node = wm_wifi.start_list->next;
+    prev_node = wm_wifi.start_list;
+    if (curr_node == NULL && cmp_mac_addr(prev_node->mac_addr, mac_addr))
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(prev_node);
+#else
+        OSA_MemoryPoolFree(buf_32_MemoryPool, prev_node);
+#endif
+        wm_wifi.start_list = NULL;
+        (void)wifi_put_mcastf_lock();
+        return WM_SUCCESS;
+    }
+    /* If search element is at first location */
+    if (!cmp_mac_addr(prev_node->mac_addr, mac_addr))
+    {
+        wm_wifi.start_list = prev_node->next;
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(prev_node);
+#else
+        OSA_MemoryPoolFree(buf_32_MemoryPool, prev_node);
+#endif
+        (void)wifi_put_mcastf_lock();
+        return WM_SUCCESS;
+    }
+    /* Find node in linked list */
+    while (cmp_mac_addr(curr_node->mac_addr, mac_addr) && curr_node->next != NULL)
+    {
+        prev_node = curr_node;
+        curr_node = curr_node->next;
+    }
+    if (!cmp_mac_addr(curr_node->mac_addr, mac_addr))
+    {
+        prev_node->next = curr_node->next;
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(curr_node);
+#else
+        OSA_MemoryPoolFree(buf_32_MemoryPool, curr_node);
+#endif
+        (void)wifi_put_mcastf_lock();
+        return WM_SUCCESS;
+    }
+    (void)wifi_put_mcastf_lock();
+    return -WM_FAIL;
+}
+
+static int make_filter_list(char *mlist, int maxlen)
+{
+    mcast_filter *node_t;
+    int maddr_cnt = 0;
+    (void)wifi_get_mcastf_lock();
+    node_t = wm_wifi.start_list;
+    while (node_t != NULL)
+    {
+        (void)memcpy((void *)mlist, (const void *)node_t->mac_addr, MLAN_MAC_ADDR_LENGTH);
+        node_t = (struct mcast_filter *)node_t->next;
+        mlist  = mlist + MLAN_MAC_ADDR_LENGTH;
+        maddr_cnt++;
+        if (maddr_cnt > (maxlen / 6U))
+        {
+            break;
+        }
+    }
+    (void)wifi_put_mcastf_lock();
+    return maddr_cnt;
+}
+
+void wifi_get_ipv4_multicast_mac(uint32_t ipaddr, uint8_t *mac_addr)
+{
+    int i = 0, j = 0;
+    uint32_t mac_addr_r = 0x01005E;
+    ipaddr              = ipaddr & 0x7FFFFFU;
+    /* Generate Multicast Mapped Mac Address for IPv4
+     * To get Multicast Mapped MAC address,
+     * To calculate 6 byte Multicast-Mapped MAC Address.
+     * 1) Fill higher 24-bits with IANA Multicast OUI (01-00-5E)
+     * 2) Set 24th bit as Zero
+     * 3) Fill lower 23-bits with from IP address (ignoring higher
+     * 9bits).
+     */
+    for (i = 2; i >= 0; i--)
+    {
+        mac_addr[j] = (uint8_t)((char)(mac_addr_r >> 8 * i) & 0xFF);
+        j++;
+    }
+
+    for (i = 2; i >= 0; i--)
+    {
+        mac_addr[j] = (uint8_t)((char)(ipaddr >> 8 * i) & 0xFF);
+        j++;
+    }
+}
+
+#if CONFIG_IPV6
+void wifi_get_ipv6_multicast_mac(uint32_t ipaddr, uint8_t *mac_addr)
+{
+    int i = 0, j = 0;
+    uint32_t mac_addr_r = 0x3333;
+    /* Generate Multicast Mapped Mac Address for IPv6
+     * To get Multicast Mapped MAC address,
+     * To calculate 6 byte Multicast-Mapped MAC Address.
+     * 1) Fill higher 16-bits with IANA Multicast OUI (33-33)
+     * 2) Fill lower 24-bits with from IP address
+     */
+    for (i = 1; i >= 0; i--)
+    {
+        mac_addr[j] = (char)(mac_addr_r >> 8 * i) & 0xFF;
+        j++;
+    }
+
+    for (i = 3; i >= 0; i--)
+    {
+        mac_addr[j] = (char)(ipaddr >> 8 * i) & 0xFF;
+        j++;
+    }
+}
+#endif /* CONFIG_IPV6 */
+
+int wifi_add_mcast_filter(uint8_t *mac_addr)
+{
+    char mlist[MAX_MCAST_LEN] = {0};
+    int len, ret;
+    /* If MAC address is 00:11:22:33:44:55,
+     * then pass mac_addr array in following format:
+     * mac_addr[0] = 00
+     * mac_addr[1] = 11
+     * mac_addr[2] = 22
+     * mac_addr[3] = 33
+     * mac_addr[4] = 44
+     * mac_addr[5] = 55
+     */
+
+    (void)memset(&mlist, 0x00, MAX_MCAST_LEN);
+    ret = add_mcast_ip(mac_addr);
+    if (ret != WM_SUCCESS)
+    {
+        return ret;
+    }
+    len = make_filter_list(mlist, (int)MAX_MCAST_LEN);
+    return wifi_set_mac_multicast_addr(mlist, (t_u32)len);
+}
+
+int wifi_remove_mcast_filter(uint8_t *mac_addr)
+{
+    char mlist[MAX_MCAST_LEN];
+    int len, ret;
+    /* If MAC address is 00:11:22:33:44:55,
+     * then pass mac_addr array in following format:
+     * mac_addr[0] = 00
+     * mac_addr[1] = 11
+     * mac_addr[2] = 22
+     * mac_addr[3] = 33
+     * mac_addr[4] = 44
+     * mac_addr[5] = 55
+     */
+
+    (void)memset(&mlist, 0x00, MAX_MCAST_LEN);
+    ret = remove_mcast_ip(mac_addr);
+    if (ret != WM_SUCCESS)
+    {
+        return ret;
+    }
+    len = make_filter_list(mlist, (int)MAX_MCAST_LEN);
+    ret = wifi_set_mac_multicast_addr(mlist, (uint32_t)len);
+    return ret;
+}
+
+void wifi_remove_all_mcast_filter(uint8_t need_lock)
+{
+    mcast_filter *node = NULL;
+
+    if (wm_wifi.start_list == NULL)
+        return;
+
+    if (need_lock)
+        wifi_get_mcastf_lock();
+
+    while (wm_wifi.start_list)
+    {
+        node               = wm_wifi.start_list;
+        wm_wifi.start_list = node->next;
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(node);
+#else
+        OSA_MemoryPoolFree(buf_32_MemoryPool, node);
+#endif
+    }
+
+    if (need_lock)
+        wifi_put_mcastf_lock();
+}
+
+static struct wifi_scan_result2 common_desc;
+int wifi_get_scan_result(unsigned int index, struct wifi_scan_result2 **desc)
+{
+    (void)memset(&common_desc, 0x00, sizeof(struct wifi_scan_result2));
+    int rv =
+        wrapper_bssdesc_first_set((int)index, common_desc.bssid, &common_desc.is_ibss_bit_set, &common_desc.ssid_len,
+                                  common_desc.ssid, &common_desc.Channel, &common_desc.RSSI, &common_desc.beacon_period,
+                                  &common_desc.dtim_period, &common_desc.WPA_WPA2_WEP, &common_desc.wpa_mcstCipher,
+                                  &common_desc.wpa_ucstCipher, &common_desc.rsn_mcstCipher, &common_desc.rsn_ucstCipher,
+                                  &common_desc.ap_mfpc, &common_desc.ap_mfpr, &common_desc.ap_pwe);
+    if (rv != WM_SUCCESS)
+    {
+        wifi_e("wifi_get_scan_result failed");
+        return rv;
+    }
+
+    /* Country info not populated */
+    rv = wrapper_bssdesc_second_set((int)index, &common_desc.phtcap_ie_present, &common_desc.phtinfo_ie_present,
+#if CONFIG_11AC
+                                    &common_desc.pvhtcap_ie_present,
+#endif
+#if CONFIG_11AX
+                                    &common_desc.phecap_ie_present,
+#endif
+                                    &common_desc.wmm_ie_present, &common_desc.band, &common_desc.wps_IE_exist,
+                                    &common_desc.wps_session, &common_desc.wpa2_entp_IE_exist,
+#if CONFIG_11R
+                                    &common_desc.mdid,
+#endif
+#if CONFIG_11K
+                                    &common_desc.neighbor_report_supported,
+#endif
+#if CONFIG_11V
+                                    &common_desc.bss_transition_supported,
+#endif
+                                    &common_desc.trans_mode, common_desc.trans_bssid, &common_desc.trans_ssid_len,
+                                    common_desc.trans_ssid
+#if CONFIG_DRIVER_MBO
+                                    ,
+                                    &common_desc.mbo_assoc_disallowed
+#endif
+    );
+
+    if (rv != WM_SUCCESS)
+    {
+        wifi_e("wifi_get_scan_result failed");
+        return rv;
+    }
+
+    *desc = &common_desc;
+
+    return WM_SUCCESS;
+}
+
+int wifi_register_event_queue(osa_msgq_handle_t event_queue)
+{
+    if (event_queue == MNULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (wm_wifi.wlc_mgr_event_queue != NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    wm_wifi.wlc_mgr_event_queue = event_queue;
+    return WM_SUCCESS;
+}
+
+int wifi_unregister_event_queue(osa_msgq_handle_t event_queue)
+{
+    if ((wm_wifi.wlc_mgr_event_queue == MNULL) || wm_wifi.wlc_mgr_event_queue != event_queue)
+    {
+        return -WM_FAIL;
+    }
+
+    wm_wifi.wlc_mgr_event_queue = NULL;
+    return WM_SUCCESS;
+}
+
+
+int wifi_get_wpa_ie_in_assoc(uint8_t *wpa_ie)
+{
+    return wrapper_get_wpa_ie_in_assoc(wpa_ie);
+}
+
+#define WL_ID_WIFI_MAIN_LOOP "wifi_drv_task"
+
+static void wifi_drv_task(void *argv)
+{
+    osa_status_t status;
+    struct bus_message msg;
+
+    (void)memset((void *)&msg, 0, sizeof(struct bus_message));
+
+    /* Main Loop */
+    while (true)
+    {
+        status = OSA_MsgQGet((osa_msgq_handle_t)wm_wifi.io_events, &msg, osaWaitForever_c);
+        if (status == KOSA_StatusSuccess)
+        {
+            // wakelock_get(WL_ID_WIFI_MAIN_LOOP);
+
+            if (msg.event == MLAN_TYPE_EVENT)
+            {
+                (void)wifi_handle_fw_event(&msg);
+                /*
+                 * Free the buffer after the event is
+                 * handled.
+                 */
+                if (msg.data != NULL)
+                {
+                    wifi_free_eventbuf(msg.data);
+                }
+            }
+            else if (msg.event == MLAN_TYPE_CMD)
+            {
+                (void)wifi_process_cmd_response((HostCmd_DS_COMMAND *)(void *)((uint8_t *)msg.data + INTF_HEADER_LEN));
+                wifi_update_last_cmd_sent_ms();
+                (void)wifi_put_command_resp_sem();
+            }
+            else
+            { /* Do Nothing */
+            }
+
+            // wakelock_put(WL_ID_WIFI_MAIN_LOOP);
+        }
+    }
+}
+
+#ifndef RW610
+#define WL_ID_WIFI_CORE_INPUT "wifi_core_task"
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface.
+ */
+static void wifi_core_task(void *argv)
+{
+    OSA_SR_ALLOC();
+#ifndef __ZEPHYR__
+    osa_event_flags_t flagsToWait = WIFI_EVENT_SDIO;
+    osa_event_flags_t pSetFlags;
+#endif
+
+    for (;;)
+    {
+        OSA_ENTER_CRITICAL();
+
+        /* Allow interrupt handler to deliver us a packet */
+        g_txrx_flag = true;
+        //		SDIOC_IntMask(SDIOC_INT_CDINT, UNMASK);
+        //		SDIOC_IntSigMask(SDIOC_INT_CDINT, UNMASK);
+#ifndef RW610
+        sdio_enable_interrupt();
+#endif
+
+        OSA_EXIT_CRITICAL();
+
+#ifdef __ZEPHYR__
+        (void)OSA_EventNotifyGet(osaWaitForever_c);
+#else
+        /* Wait till we receive a packet from SDIO */
+        (void)OSA_EventWait((osa_event_handle_t)wm_wifi.wifi_event_Handle, flagsToWait, false, osaWaitForever_c,
+                            &pSetFlags);
+
+        if ((pSetFlags & WIFI_EVENT_SDIO) == 0U)
+        {
+            continue;
+        }
+#endif
+
+        // wakelock_get(WL_ID_WIFI_CORE_INPUT);
+
+#if defined(RW610)
+        (void)wifi_imu_lock();
+#else
+        /* Protect the SDIO from other parallel activities */
+        (void)wifi_sdio_lock();
+
+        (void)wlan_process_int_status(mlan_adap);
+#endif
+
+#if defined(RW610)
+        wifi_imu_unlock();
+#else
+        wifi_sdio_unlock();
+#endif
+        // wakelock_put(WL_ID_WIFI_CORE_INPUT);
+    } /* for ;; */
+}
+#endif
+void wifi_user_scan_config_cleanup(void)
+{
+    if (wm_wifi.g_user_scan_cfg != NULL)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)wm_wifi.g_user_scan_cfg);
+#else
+        OSA_MemoryPoolFree(buf_768_MemoryPool, wm_wifi.g_user_scan_cfg);
+#endif
+        wm_wifi.g_user_scan_cfg = NULL;
+    }
+}
+
+void wifi_scan_stop(void)
+{
+    wm_wifi.scan_stop = true;
+    while (scan_thread_in_process)
+    {
+        /* wait for scan task done */
+        OSA_TimeDelay(1000);
+    }
+    wm_wifi.scan_stop = false;
+}
+
+/**
+ * This function should be called when scan command is ready
+ *
+ */
+static void wifi_scan_task(void *argv)
+{
+    mlan_status rv;
+#ifndef __ZEPHYR__
+    osa_event_flags_t flagsToWait = WIFI_EVENT_SCAN;
+    osa_event_flags_t pSetFlags;
+#endif
+
+    for (;;)
+    {
+#ifdef __ZEPHYR__
+        (void)OSA_EventNotifyGet(osaWaitForever_c);
+#else
+        /* Wait till we receive scan command */
+        (void)OSA_EventWait((osa_event_handle_t)wm_wifi.wifi_event_Handle, flagsToWait, false, osaWaitForever_c,
+                            &pSetFlags);
+
+        OSA_EventClear((osa_event_handle_t)wm_wifi.wifi_event_Handle, WIFI_EVENT_SCAN);
+
+        if ((pSetFlags & WIFI_EVENT_SCAN) == 0U)
+        {
+            continue;
+        }
+#endif
+        if (wm_wifi.scan_stop == true)
+        {
+            wm_wifi.scan_stop = false;
+            wifi_user_scan_config_cleanup();
+            break;
+        }
+
+        scan_thread_in_process = true;
+        if (wm_wifi.g_user_scan_cfg != NULL)
+        {
+#if CONFIG_WPA_SUPP
+            (void)wifi_event_completion(WIFI_EVENT_SCAN_START, WIFI_EVENT_REASON_SUCCESS, NULL);
+#endif
+            rv = wlan_scan_networks((mlan_private *)mlan_adap->priv[0], NULL, wm_wifi.g_user_scan_cfg);
+            if (rv != MLAN_STATUS_SUCCESS)
+            {
+                wifi_user_scan_config_cleanup();
+                (void)wifi_event_completion(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_FAILURE, NULL);
+            }
+        }
+        scan_thread_in_process = false;
+    } /* for ;; */
+    while (true)
+    {
+        OSA_TimeDelay(60000);
+    }
+}
+
+static void wifi_powersave_task(void *data)
+{
+    osa_status_t status;
+    struct wifi_message msg;
+
+    while (1)
+    {
+        status = OSA_MsgQGet((osa_msgq_handle_t)wm_wifi.powersave_queue, &msg, osaWaitForever_c);
+        if (status == KOSA_StatusSuccess)
+        {
+            switch (msg.event)
+            {
+                case WIFI_EVENT_SLEEP:
+                    wifi_event_completion(WIFI_EVENT_SLEEP, WIFI_EVENT_REASON_SUCCESS, NULL);
+                    break;
+                default:
+                    wifi_w("got unknown message: %d", msg.event);
+                    break;
+            }
+        }
+    }
+}
+
+#if CONFIG_FW_VDLL
+/**
+ *  @brief This function flushes all data
+ *
+ *  @param context      Reorder context pointer
+ *
+ *  @return 	   	    N/A
+ */
+static t_void wlan_vdll_complete(osa_timer_arg_t tmr_handle)
+{
+    mlan_adap->vdll_in_progress = MFALSE;
+}
+#endif
+
+static void wifi_core_deinit(void);
+static int wifi_low_level_input(const uint8_t interface, const uint8_t *buffer, const uint16_t len);
+
+static int wifi_core_init(void)
+{
+    osa_status_t status;
+    int ret;
+
+    if (wm_wifi.wifi_core_init_done != 0U)
+    {
+        return WM_SUCCESS;
+    }
+
+    status = OSA_MutexCreate((osa_mutex_handle_t)wm_wifi.command_lock);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create command_lock failed");
+        goto fail;
+    }
+
+    status = OSA_EventCreate((osa_event_handle_t)wm_wifi.wifi_event_Handle, 1);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create event handle failed");
+        goto fail;
+    }
+
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)wm_wifi.command_resp_sem);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create command resp sem failed");
+        goto fail;
+    }
+    OSA_SemaphorePost((osa_semaphore_handle_t)wm_wifi.command_resp_sem);
+    status = OSA_MutexCreate((osa_mutex_handle_t)wm_wifi.mcastf_mutex);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create mcastf mutex failed");
+        goto fail;
+    }
+    /*
+     * Take the cmd resp lock immediately so that we can later block on
+     * it.
+     */
+    (void)wifi_get_command_resp_sem(osaWaitForever_c);
+
+    status = OSA_MsgQCreate((osa_msgq_handle_t)wm_wifi.io_events, MAX_EVENTS, sizeof(struct bus_message));
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create io events queue failed");
+        goto fail;
+    }
+
+    ret = bus_register_event_queue((osa_msgq_handle_t)wm_wifi.io_events);
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("Register io events queue failed");
+        goto fail;
+    }
+
+    status = OSA_TaskCreate((osa_task_handle_t)wm_wifi.wifi_drv_task_Handle, OSA_TASK(wifi_drv_task), NULL);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create wifi driver thread failed");
+        goto fail;
+    }
+
+    ret = bus_register_data_input_function(&wifi_low_level_input);
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("Register wifi low level input failed");
+        goto fail;
+    }
+
+    status = OSA_TaskCreate((osa_task_handle_t)wm_wifi.wifi_scan_task_Handle, OSA_TASK(wifi_scan_task), NULL);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create wifi scan thread failed");
+        goto fail;
+    }
+#ifndef RW610
+    status = OSA_TaskCreate((osa_task_handle_t)wm_wifi.wifi_core_task_Handle, OSA_TASK(wifi_core_task), NULL);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create stack dispatcher thread failed");
+        goto fail;
+    }
+#endif
+
+    wm_wifi.wifi_core_init_done = 1;
+
+#if CONFIG_WMM
+    ret = wifi_wmm_buf_pool_init(&outbuf_arr[0][0]);
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("Unable to init wmm buffer pool");
+        goto fail;
+    }
+
+    ret = wifi_bypass_txq_init();
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("Init bypass txq failed\r\n");
+        goto fail;
+    }
+
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)txbuf_sem);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create txbuf sem failed");
+        return ret;
+    }
+
+    /* Semaphore to protect wmm data parameters */
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)wm_wifi.tx_data_sem);
+    if (status != KOSA_StatusSuccess)
+    {
+        PRINTF("Create tx data sem failed");
+        goto fail;
+    }
+    OSA_SemaphorePost((osa_semaphore_handle_t)wm_wifi.tx_data_sem);
+#ifdef __ZEPHYR__
+    status = OSA_MsgQCreate((osa_msgq_handle_t)wm_wifi.tx_data, MAX_EVENTS, sizeof(struct bus_message));
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create tx_data queue failed");
+        goto fail;
+    }
+#endif
+
+    status = OSA_TaskCreate((osa_task_handle_t)wm_wifi.wifi_drv_tx_task_Handle, OSA_TASK(wifi_drv_tx_task), NULL);
+    if (status != KOSA_StatusSuccess)
+    {
+        PRINTF("Create tx data thread failed");
+        goto fail;
+    }
+#endif
+
+    status = OSA_MsgQCreate((osa_msgq_handle_t)wm_wifi.powersave_queue, MAX_EVENTS, sizeof(struct bus_message));
+    if (status != KOSA_StatusSuccess)
+    {
+        PRINTF("Create power save queue failed");
+        goto fail;
+    }
+
+    status = OSA_TaskCreate((osa_task_handle_t)wm_wifi.wifi_powersave_task_Handle, OSA_TASK(wifi_powersave_task), NULL);
+    if (status != KOSA_StatusSuccess)
+    {
+        PRINTF("Create power save thread failed");
+        goto fail;
+    }
+
+#if CONFIG_CSI
+    /* Semaphore to protect data parameters */
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem);
+    if (status != KOSA_StatusSuccess)
+    {
+        PRINTF("Create usb data sem failed");
+        goto fail;
+    }
+    OSA_SemaphorePost((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem);
+#endif
+
+#if CONFIG_ECSA
+    /* Semaphore to wait ECSA complete */
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)ecsa_status_control.ecsa_sem);
+    if (status != KOSA_StatusSuccess)
+    {
+        PRINTF("Create ecsa sem failed");
+        goto fail;
+    }
+#endif
+
+#if CONFIG_FW_VDLL
+    (void)mlan_adap->callbacks.moal_init_timer(mlan_adap->pmoal_handle, &mlan_adap->vdll_timer, wlan_vdll_complete,
+                                               NULL);
+#endif
+
+    wm_wifi.wifi_core_init_done = 1;
+
+#if defined(SD8801) || defined(RW610)
+    wifi_uap_set_bandwidth(BANDWIDTH_20MHZ);
+#else
+    wifi_uap_set_bandwidth(BANDWIDTH_40MHZ);
+#endif
+
+    return WM_SUCCESS;
+
+fail:
+
+    wifi_core_deinit();
+
+    return -WM_FAIL;
+}
+
+static void wifi_core_deinit(void)
+{
+    int i = 0;
+
+    mlan_adap->in_reset = true;
+    for (i = 0; i < (int)(MIN(MLAN_MAX_BSS_NUM, mlan_adap->priv_num)); i++)
+    {
+        if (mlan_adap->priv[i])
+        {
+            wlan_clean_txrx(mlan_adap->priv[i]);
+            (void)OSA_MutexDestroy((osa_mutex_handle_t)mlan_adap->priv[i]->tx_ba_stream_tbl_lock);
+            (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)mlan_adap->priv[i]->rx_reorder_tbl_lock);
+#if CONFIG_WMM
+            wlan_ralist_deinit_enh(mlan_adap->priv[i]);
+#endif
+        }
+    }
+
+    wm_wifi.wifi_core_init_done = 0;
+
+    bus_deregister_event_queue();
+    bus_deregister_data_input_funtion();
+
+    (void)OSA_MsgQDestroy((osa_msgq_handle_t)wm_wifi.io_events);
+
+    (void)OSA_MsgQDestroy((osa_msgq_handle_t)wm_wifi.powersave_queue);
+
+#if CONFIG_WMM
+#ifdef __ZEPHYR__
+    (void)OSA_MsgQDestroy((osa_msgq_handle_t)wm_wifi.tx_data);
+#endif
+    wifi_wmm_buf_pool_deinit();
+    wifi_bypass_txq_deinit();
+
+    (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)txbuf_sem);
+#endif
+
+    wifi_remove_all_mcast_filter(0);
+
+    (void)OSA_MutexDestroy((osa_mutex_handle_t)wm_wifi.mcastf_mutex);
+    (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)wm_wifi.command_resp_sem);
+#if CONFIG_WMM
+    (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)wm_wifi.tx_data_sem);
+#endif
+    (void)OSA_MutexDestroy((osa_mutex_handle_t)wm_wifi.command_lock);
+    (void)OSA_EventDestroy((osa_event_handle_t)wm_wifi.wifi_event_Handle);
+#ifndef RW610
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_drv_task_Handle);
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_core_task_Handle);
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_scan_task_Handle);
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_powersave_task_Handle);
+#if CONFIG_WMM
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_drv_tx_task_Handle);
+#endif
+#else
+    wm_wifi.cmd_resp_priv   = NULL;
+    wm_wifi.cmd_resp_ioctl  = NULL;
+    wm_wifi.cmd_resp_status = 0;
+    memset(&wm_wifi, 0x00, sizeof(wm_wifi));
+#endif
+#if CONFIG_CSI
+    (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem);
+#endif
+#if CONFIG_ECSA
+    (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)ecsa_status_control.ecsa_sem);
+#endif
+#if CONFIG_FW_VDLL
+    (void)mlan_adap->callbacks.moal_stop_timer(mlan_adap->pmoal_handle, mlan_adap->vdll_timer);
+    (void)mlan_adap->callbacks.moal_free_timer(mlan_adap->pmoal_handle, &mlan_adap->vdll_timer);
+#endif
+}
+
+int wifi_init(const uint8_t *fw_start_addr, const size_t size)
+{
+    int ret = WM_SUCCESS;
+    if (wm_wifi.wifi_init_done != 0U)
+    {
+        return WM_SUCCESS;
+    }
+
+    (void)memset(&wm_wifi, 0, sizeof(wm_wifi_t));
+
+    wm_wifi.fw_start_addr = fw_start_addr;
+    wm_wifi.size          = size;
+
+#if defined(RW610)
+    ret = (int)imu_wifi_init(WLAN_TYPE_NORMAL, fw_start_addr, size);
+#else
+    ret = (int)sd_wifi_init(WLAN_TYPE_NORMAL, fw_start_addr, size);
+#endif
+    if (ret != WM_SUCCESS)
+    {
+#if defined(RW610)
+        wifi_e("imu_wifi_init failed. status code %d", ret);
+#else
+        wifi_e("sd_wifi_init failed. status code %d", ret);
+#endif
+        switch (ret)
+        {
+            case MLAN_CARD_CMD_TIMEOUT:
+            case MLAN_CARD_NOT_DETECTED:
+                ret = -WIFI_ERROR_CARD_NOT_DETECTED;
+                break;
+            case MLAN_STATUS_FW_DNLD_FAILED:
+                ret = -WIFI_ERROR_FW_DNLD_FAILED;
+                break;
+            case MLAN_STATUS_FW_NOT_DETECTED:
+                ret = -WIFI_ERROR_FW_NOT_DETECTED;
+                break;
+            case MLAN_STATUS_FW_NOT_READY:
+                ret = -WIFI_ERROR_FW_NOT_READY;
+                break;
+            default:
+                PRINTM(MINFO, "Unexpected MLAN FW Status \n");
+                break;
+        }
+        return ret;
+    }
+
+    ret = wifi_core_init();
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("wifi_core_init failed. status code %d", ret);
+        return ret;
+    }
+
+#ifndef RW610
+    ret = (int)sd_wifi_post_init(WLAN_TYPE_NORMAL);
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("sd_wifi_post_init failed. status code %d", ret);
+        return ret;
+    }
+#endif
+    if (ret == WM_SUCCESS)
+    {
+        wm_wifi.wifi_init_done = 1;
+    }
+
+    return ret;
+}
+
+#if (CONFIG_WIFI_IND_DNLD)
+static int wifi_reinit(uint8_t fw_reload)
+{
+    int ret = WM_SUCCESS;
+
+    ret = (int)sd_wifi_reinit(WLAN_TYPE_NORMAL, wm_wifi.fw_start_addr, wm_wifi.size, fw_reload);
+#if CONFIG_WIFI_IND_RESET
+    wifi_ind_reset_stop();
+#endif
+    if (ret != WM_SUCCESS)
+    {
+        if (ret != MLAN_STATUS_FW_DNLD_SKIP)
+        {
+            wifi_e("sd_wifi_reinit failed. status code %d", ret);
+        }
+        switch (ret)
+        {
+            case MLAN_CARD_CMD_TIMEOUT:
+            case MLAN_CARD_NOT_DETECTED:
+                ret = -WIFI_ERROR_CARD_NOT_DETECTED;
+                break;
+            case MLAN_STATUS_FW_DNLD_FAILED:
+                ret = -WIFI_ERROR_FW_DNLD_FAILED;
+                break;
+            case MLAN_STATUS_FW_NOT_DETECTED:
+                ret = -WIFI_ERROR_FW_NOT_DETECTED;
+                break;
+            case MLAN_STATUS_FW_NOT_READY:
+                ret = -WIFI_ERROR_FW_NOT_READY;
+                break;
+            case MLAN_STATUS_FW_DNLD_SKIP:
+                ret = WM_SUCCESS;
+                break;
+            default:
+                PRINTM(MINFO, "Unexpected MLAN FW Status \n");
+                ret = -WM_FAIL;
+                break;
+        }
+    }
+#ifndef RW610
+    else
+    {
+        ret = (int)sd_wifi_post_init(WLAN_TYPE_NORMAL);
+        if (ret != WM_SUCCESS)
+        {
+            wifi_e("sd_wifi_post_init failed. status code %d", ret);
+            return ret;
+        }
+    }
+#endif
+
+    return ret;
+}
+#endif
+
+#ifndef RW610
+int wifi_init_fcc(const uint8_t *fw_start_addr, const size_t size)
+{
+    if (wm_wifi.wifi_init_done != 0U)
+    {
+        return WM_SUCCESS;
+    }
+
+    int ret = (int)sd_wifi_init(WLAN_TYPE_FCC_CERTIFICATION, fw_start_addr, size);
+    if (ret != 0)
+    {
+        wifi_e("sd_wifi_init failed. status code %d", ret);
+        switch (ret)
+        {
+            case MLAN_CARD_CMD_TIMEOUT:
+            case MLAN_CARD_NOT_DETECTED:
+                ret = -WIFI_ERROR_CARD_NOT_DETECTED;
+                break;
+            case MLAN_STATUS_FW_DNLD_FAILED:
+                ret = -WIFI_ERROR_FW_DNLD_FAILED;
+                break;
+            case MLAN_STATUS_FW_NOT_DETECTED:
+                ret = -WIFI_ERROR_FW_NOT_DETECTED;
+                break;
+            case MLAN_STATUS_FW_NOT_READY:
+                ret = -WIFI_ERROR_FW_NOT_READY;
+                break;
+            default:
+                wifi_d("sd_wifi_init unexpected MLAN Status %d", ret);
+                break;
+        }
+        return ret;
+    }
+
+    ret = wifi_core_init();
+    if (ret != 0)
+    {
+        wifi_e("wifi_core_init failed. status code %d", ret);
+    }
+
+    if (ret == WM_SUCCESS)
+    {
+        wm_wifi.wifi_init_done = 1;
+    }
+#ifndef RW610
+    ret = (int)sd_wifi_post_init(WLAN_TYPE_FCC_CERTIFICATION);
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("sd_wifi_post_init failed. status code %d", ret);
+        return ret;
+    }
+#endif
+
+    return ret;
+}
+#endif
+
+void wifi_deinit(void)
+{
+    if (wm_wifi.wifi_init_done == 0U)
+    {
+        return;
+    }
+
+    wm_wifi.wifi_init_done = 0;
+
+    wifi_core_deinit();
+
+#if defined(RW610)
+    imu_wifi_deinit();
+#else
+    sd_wifi_deinit();
+#endif
+}
+
+#ifdef RW610
+bool wifi_fw_is_hang(void)
+{
+    if (mlan_adap && mlan_adap->bus_ops.fw_is_hang)
+        return mlan_adap->bus_ops.fw_is_hang();
+    return false;
+}
+
+void wifi_destroy_wifidriver_tasks(void)
+{
+#if CONFIG_WMM
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_drv_tx_task_Handle);
+#endif
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_drv_task_Handle);
+#ifndef RW610
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_core_task_Handle);
+#endif
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_scan_task_Handle);
+    (void)OSA_TaskDestroy((osa_task_handle_t)wm_wifi.wifi_powersave_task_Handle);
+
+    imu_uninstall_callback();
+}
+#endif
+void wifi_set_tx_status(t_u8 status)
+{
+    wifi_tx_status = status;
+}
+
+void wifi_set_rx_status(t_u8 status)
+{
+    wifi_rx_status = status;
+}
+
+void wifi_set_packet_retry_count(const int count)
+{
+    retry_attempts = count;
+}
+
+void wifi_sta_ampdu_tx_enable(void)
+{
+    sta_ampdu_tx_enable = true;
+}
+
+void wifi_sta_ampdu_tx_disable(void)
+{
+    sta_ampdu_tx_enable = false;
+}
+
+void wifi_sta_ampdu_tx_enable_per_tid(t_u8 tid)
+{
+    sta_ampdu_tx_enable_per_tid = tid;
+}
+
+t_u8 wifi_sta_ampdu_tx_enable_per_tid_is_allowed(t_u8 tid)
+{
+    if ((sta_ampdu_tx_enable_per_tid >> tid) & 0x01)
+        return MTRUE;
+    else
+        return MFALSE;
+}
+
+void wifi_sta_ampdu_rx_enable(void)
+{
+    sta_ampdu_rx_enable = true;
+}
+
+void wifi_sta_ampdu_rx_disable(void)
+{
+    sta_ampdu_rx_enable = false;
+}
+
+void wifi_sta_ampdu_rx_enable_per_tid(t_u8 tid)
+{
+    sta_ampdu_rx_enable_per_tid = tid;
+}
+
+t_u8 wifi_sta_ampdu_rx_enable_per_tid_is_allowed(t_u8 tid)
+{
+    if ((sta_ampdu_rx_enable_per_tid >> tid) & 0x01)
+        return MTRUE;
+    else
+        return MFALSE;
+}
+
+void wifi_uap_ampdu_tx_enable(void)
+{
+    uap_ampdu_tx_enable = true;
+}
+
+void wifi_uap_ampdu_tx_disable(void)
+{
+    uap_ampdu_tx_enable = false;
+}
+
+void wifi_uap_ampdu_tx_enable_per_tid(t_u8 tid)
+{
+    uap_ampdu_tx_enable_per_tid = tid;
+}
+
+t_u8 wifi_uap_ampdu_tx_enable_per_tid_is_allowed(t_u8 tid)
+{
+    if ((uap_ampdu_tx_enable_per_tid >> tid) & 0x01)
+        return MTRUE;
+    else
+        return MFALSE;
+}
+
+void wifi_uap_ampdu_rx_enable(void)
+{
+    uap_ampdu_rx_enable = true;
+}
+
+void wifi_uap_ampdu_rx_disable(void)
+{
+    uap_ampdu_rx_enable = false;
+}
+
+void wifi_uap_ampdu_rx_enable_per_tid(t_u8 tid)
+{
+    uap_ampdu_rx_enable_per_tid = tid;
+}
+
+t_u8 wifi_uap_ampdu_rx_enable_per_tid_is_allowed(t_u8 tid)
+{
+    if ((uap_ampdu_rx_enable_per_tid >> tid) & 0x01)
+        return MTRUE;
+    else
+        return MFALSE;
+}
+
+#if ((FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER) && FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER > 0U)
+int wifi_register_get_rxbuf_desc_callback(void *(*wifi_get_rxbuf_desc)(t_u16 rx_len))
+{
+    if (wm_wifi.wifi_get_rxbuf_desc != NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    wm_wifi.wifi_get_rxbuf_desc = wifi_get_rxbuf_desc;
+
+    return WM_SUCCESS;
+}
+
+void wifi_deregister_get_rxbuf_desc_callback(void)
+{
+    wm_wifi.wifi_get_rxbuf_desc = NULL;
+}
+#endif
+
+int wifi_register_data_input_callback(void (*data_input_callback)(const uint8_t interface,
+                                                                  const uint8_t *buffer,
+                                                                  const uint16_t len))
+{
+#if CONFIG_HEAP_DEBUG
+    static bool mem_stat_sem_init = 0;
+    int ret;
+#endif
+    if (wm_wifi.data_input_callback != NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    wm_wifi.data_input_callback = data_input_callback;
+
+#if CONFIG_HEAP_DEBUG
+    /* Semaphore to protect os mem stat */
+    if (!mem_stat_sem_init)
+    {
+        ret = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)os_mem_stat_sem);
+        if (ret != WM_SUCCESS)
+        {
+            PRINTF("Create os mem stat sem failed");
+            return -WM_FAIL;
+        }
+        OSA_SemaphorePost((osa_semaphore_handle_t)os_mem_stat_sem);
+        mem_stat_sem_init = 1;
+    }
+#endif
+
+    return WM_SUCCESS;
+}
+
+void wifi_deregister_data_input_callback(void)
+{
+    wm_wifi.data_input_callback = NULL;
+}
+
+int wifi_register_amsdu_data_input_callback(void (*amsdu_data_input_callback)(uint8_t interface,
+                                                                              uint8_t *buffer,
+                                                                              uint16_t len))
+{
+    if (wm_wifi.amsdu_data_input_callback != NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    wm_wifi.amsdu_data_input_callback = amsdu_data_input_callback;
+
+    return WM_SUCCESS;
+}
+
+void wifi_deregister_amsdu_data_input_callback(void)
+{
+    wm_wifi.amsdu_data_input_callback = NULL;
+}
+
+int wifi_register_deliver_packet_above_callback(void (*deliver_packet_above_callback)(void *rxpd,
+                                                                                      uint8_t interface,
+                                                                                      void *lwip_pbuf))
+{
+    if (wm_wifi.deliver_packet_above_callback != NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    wm_wifi.deliver_packet_above_callback = deliver_packet_above_callback;
+
+    return WM_SUCCESS;
+}
+
+void wifi_deregister_deliver_packet_above_callback(void)
+{
+    wm_wifi.deliver_packet_above_callback = NULL;
+}
+
+int wifi_register_wrapper_net_is_ip_or_ipv6_callback(bool (*wrapper_net_is_ip_or_ipv6_callback)(const t_u8 *buffer))
+{
+    if (wm_wifi.wrapper_net_is_ip_or_ipv6_callback != NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    wm_wifi.wrapper_net_is_ip_or_ipv6_callback = wrapper_net_is_ip_or_ipv6_callback;
+
+    return WM_SUCCESS;
+}
+
+void wifi_deregister_wrapper_net_is_ip_or_ipv6_callback(void)
+{
+    wm_wifi.wrapper_net_is_ip_or_ipv6_callback = NULL;
+}
+
+#if CONFIG_WPA_SUPP
+
+void wpa_supp_handle_link_lost(mlan_private *priv)
+{
+    t_u8 broadcast_addr[ETH_ALEN]      = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+    nxp_wifi_event_mlme_t *deauth_resp = &wm_wifi.mgmt_resp;
+    IEEE80211_MGMT *mgmt               = (IEEE80211_MGMT *)deauth_resp->frame.frame;
+
+    if (priv->bss_role == MLAN_BSS_ROLE_STA)
+    {
+        memset(mgmt, 0, sizeof(IEEE80211_MGMT));
+
+        mgmt->frame_control            = SUBTYPE_DEAUTH;
+        mgmt->duration                 = 0;
+        mgmt->seq_ctrl                 = 0;
+        mgmt->u.deauth_req.reason_code = WLAN_REASON_DEAUTH_LEAVING;
+
+        memcpy((void *)mgmt->da, broadcast_addr, MLAN_MAC_ADDR_LENGTH);
+        memcpy((void *)mgmt->sa, priv->curr_bss_params.bss_descriptor.mac_address, MLAN_MAC_ADDR_LENGTH);
+        memcpy((void *)mgmt->bssid, priv->curr_bss_params.bss_descriptor.mac_address, MLAN_MAC_ADDR_LENGTH);
+
+        deauth_resp->frame.frame_len = 26;
+
+        priv->curr_bss_params.host_mlme = 0;
+        priv->auth_flag                 = 0;
+
+        if (wm_wifi.supp_if_callbk_fns->deauth_callbk_fn)
+        {
+            wm_wifi.supp_if_callbk_fns->deauth_callbk_fn(wm_wifi.if_priv, deauth_resp, deauth_resp->frame.frame_len);
+        }
+    }
+}
+
+/**
+ *   @brief This function processes the 802.11 mgmt Frame
+ *
+ *   @param priv            A pointer to mlan_private
+ *
+ *   @param payload         A pointer to the received buffer
+ *   @param payload_len     Length of the received buffer
+ *   @param prx_pd          A pointer to RxPD
+ *
+ *   @return                MLAN_STATUS_SUCCESS or MLAN_STATUS_FAILURE
+ */
+static mlan_status wlan_process_802dot11_mgmt_pkt2(mlan_private *priv, t_u8 *payload, t_u32 payload_len, RxPD *prx_pd)
+{
+    // pmlan_adapter pmadapter = priv->adapter;
+    // pmlan_callbacks pcb = &pmadapter->callbacks;
+    mlan_status ret                   = MLAN_STATUS_SUCCESS;
+    wlan_802_11_header *pieee_pkt_hdr = MNULL;
+    t_u16 sub_type                    = 0;
+    // t_u8 *event_buf = MNULL;
+    // mlan_event *pevent = MNULL;
+    t_u8 unicast     = 0;
+    t_u8 broadcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#if CONFIG_WIFI_EXTRA_DEBUG
+    IEEE80211_MGMT *mgmt = MNULL;
+#endif
+    t_u8 band_config = (prx_pd->rx_info & 0x3); /* Bit[1:0] 0: HALCHANBAND_BG, 1:HALCHANBAND_A, 2: HALCHANBAND_6E */
+    t_u8 chan_num    = (prx_pd->rx_info & RXPD_CHAN_MASK) >>
+                    5; /* Bit[13: 5] Non zero channel number on which this packet is received */
+    t_u8 category    = 0;
+    t_u8 action_code = 0;
+#ifdef DOT1AS_SUPPORT
+    struct timestamps tstamps;
+#endif
+    // t_u8 *sta_addr = NULL;
+    // sta_node *sta_ptr = MNULL;
+    // MrvlIETypes_MgmtFrameSet_t *tlv;
+    // pmlan_buffer pmbuf;
+
+    ENTER();
+#if 0
+/* rx buffer read from data path, nothing with MAX_EVENT_SIZE */
+    if (payload_len > (MAX_EVENT_SIZE - sizeof(mlan_event)))
+    {
+        wifi_d("Dropping large mgmt frame,len =%d", payload_len);
+        LEAVE();
+        return ret;
+    }
+#endif
+    /* Check  packet type-subtype and compare with mgmt_passthru_mask
+     * If event is needed to host, just eventify it */
+    pieee_pkt_hdr = (wlan_802_11_header *)payload;
+    sub_type      = IEEE80211_GET_FC_MGMT_FRAME_SUBTYPE(pieee_pkt_hdr->frm_ctl);
+    if (((1 << sub_type) & priv->mgmt_frame_passthru_mask) == 0)
+    {
+        wifi_d("Dropping mgmt frame for subtype %d snr=%d.", sub_type, prx_pd->snr);
+        LEAVE();
+        return ret;
+    }
+    switch (sub_type)
+    {
+        case SUBTYPE_ASSOC_REQUEST:
+        case SUBTYPE_REASSOC_REQUEST:
+            if (priv->uap_host_based)
+            {
+                if (!memcmp(pieee_pkt_hdr->addr3, priv->curr_addr, MLAN_MAC_ADDR_LENGTH))
+                {
+                    wifi_d("wlan: HostMlme MICRO_AP_STA_ASSOC " MACSTR "", MAC2STR(pieee_pkt_hdr->addr2));
+
+#if 0
+                    sta_addr = OSA_MemoryAllocate(MLAN_MAC_ADDR_LENGTH);
+                    if (sta_addr == MNULL)
+                    {
+                        wifi_w("No mem. Cannot process MAC address from assoc");
+                        LEAVE();
+                        return ret;
+                    }
+
+                    (void)memcpy((void *)sta_addr, (const void *)pieee_pkt_hdr->addr2, MLAN_MAC_ADDR_LENGTH);
+                    if (wifi_event_completion(WIFI_EVENT_UAP_CLIENT_ASSOC, WIFI_EVENT_REASON_SUCCESS, sta_addr) !=
+                        WM_SUCCESS)
+                    {
+                        /* If fail to send message on queue, free allocated memory ! */
+                        OSA_MemoryFree((void *)sta_addr);
+                    }
+
+                    mgmt    = (IEEE80211_MGMT *)payload;
+                    sta_ptr = wlan_add_station_entry(priv, pieee_pkt_hdr->addr2);
+                    if (sta_ptr)
+                    {
+                        sta_ptr->capability = wlan_le16_to_cpu(mgmt->u.assoc_req.capab_info);
+                        pmbuf               = wlan_alloc_mlan_buffer(pmadapter, payload_len, 0, MTRUE);
+                        if (pmbuf)
+                        {
+                            wifi_d("check sta capability");
+                            pmbuf->data_len = ASSOC_EVENT_FIX_SIZE;
+                            tlv = (MrvlIETypes_MgmtFrameSet_t *)(pmbuf->pbuf + pmbuf->data_offset + pmbuf->data_len);
+                            tlv->type = wlan_cpu_to_le16(TLV_TYPE_MGMT_FRAME);
+                            tlv->len  = sizeof(IEEEtypes_FrameCtl_t);
+                            __memcpy(pmadapter, (t_u8 *)&tlv->frame_control, &pieee_pkt_hdr->frm_ctl,
+                                     sizeof(IEEEtypes_FrameCtl_t));
+                            pmbuf->data_len += sizeof(MrvlIETypes_MgmtFrameSet_t);
+                            __memcpy(pmadapter, pmbuf->pbuf + pmbuf->data_offset + pmbuf->data_len,
+                                     payload + sizeof(wlan_802_11_header), payload_len - sizeof(wlan_802_11_header));
+                            pmbuf->data_len += payload_len - sizeof(wlan_802_11_header);
+                            tlv->len += payload_len - sizeof(wlan_802_11_header);
+                            tlv->len = wlan_cpu_to_le16(tlv->len);
+                            DBG_HEXDUMP(MCMD_D, "assoc_req", pmbuf->pbuf + pmbuf->data_offset, pmbuf->data_len);
+                            wlan_check_sta_capability(priv, pmbuf, sta_ptr);
+                            wlan_free_mlan_buffer(pmadapter, pmbuf);
+
+                            OSA_MemoryFree(pmbuf);
+                        }
+                    }
+#endif
+                }
+                else
+                {
+                    wifi_d("wlan: Drop MICRO_AP_STA_ASSOC " MACSTR " from unknown BSSID " MACSTR "\r\n",
+                           MAC2STR(pieee_pkt_hdr->addr2), MAC2STR(pieee_pkt_hdr->addr3));
+                }
+            }
+            unicast = MTRUE;
+            break;
+        case SUBTYPE_AUTH:
+            unicast = MTRUE;
+            wifi_d("wlan: HostMlme Auth received from " MACSTR "\r\n", MAC2STR(pieee_pkt_hdr->addr2));
+
+            if (priv->bss_role == MLAN_BSS_ROLE_STA)
+            {
+                if (priv->curr_bss_params.host_mlme)
+                {
+                    if (priv->auth_flag & HOST_MLME_AUTH_PENDING)
+                    {
+                        if (priv->auth_alg != WLAN_AUTH_SAE)
+                        {
+                            priv->auth_flag &= ~HOST_MLME_AUTH_PENDING;
+                            priv->auth_flag |= HOST_MLME_AUTH_DONE;
+                        }
+                    }
+                }
+            }
+            break;
+        case SUBTYPE_PROBE_RESP:
+            unicast = MTRUE;
+            break;
+        case SUBTYPE_DISASSOC:
+        case SUBTYPE_DEAUTH:
+            if (memcmp(pieee_pkt_hdr->addr1, broadcast, MLAN_MAC_ADDR_LENGTH))
+                unicast = MTRUE;
+            if (priv->uap_host_based)
+            {
+                if (!memcmp(pieee_pkt_hdr->addr3, priv->curr_addr, MLAN_MAC_ADDR_LENGTH))
+                {
+#if CONFIG_WIFI_EXTRA_DEBUG
+                    mgmt = (IEEE80211_MGMT *)payload;
+#endif
+
+                    wifi_d("wlan: HostMlme Deauth Receive from " MACSTR " reason code: %d\r\n",
+                           MAC2STR(pieee_pkt_hdr->addr2), mgmt->u.deauth_req.reason_code);
+
+#if 0
+                    sta_addr = OSA_MemoryAllocate(MLAN_MAC_ADDR_LENGTH);
+                    if (sta_addr == MNULL)
+                    {
+                        wifi_w("No mem. Cannot process MAC address from deauth");
+                        LEAVE();
+                        return ret;
+                    }
+
+                    (void)memcpy((void *)sta_addr, (const void *)pieee_pkt_hdr->addr2, MLAN_MAC_ADDR_LENGTH);
+                    if (wifi_event_completion(WIFI_EVENT_UAP_CLIENT_DEAUTH, WIFI_EVENT_REASON_SUCCESS, sta_addr) !=
+                        WM_SUCCESS)
+                    {
+                        /* If fail to send message on queue, free allocated memory ! */
+                        OSA_MemoryFree((void *)sta_addr);
+                    }
+#endif
+                }
+                else
+                {
+                    LEAVE();
+                    return ret;
+                }
+            }
+            if (priv->bss_role == MLAN_BSS_ROLE_STA)
+            {
+				/* check receiving broadcast deauth frame from other BSSID and drop the deauh frame */
+				t_u8 zero_mac[MLAN_MAC_ADDR_LENGTH] = {0};
+				if ((memcmp(pieee_pkt_hdr->addr3, (t_u8 *)priv->curr_bss_params.bss_descriptor.mac_address,
+						   MLAN_MAC_ADDR_LENGTH) &&
+					memcmp(zero_mac, (t_u8 *)priv->curr_bss_params.bss_descriptor.mac_address,
+						   MLAN_MAC_ADDR_LENGTH)) ||
+					memcmp(pieee_pkt_hdr->addr3, (t_u8 *)priv->curr_bss_params.attemp_bssid,
+						   MLAN_MAC_ADDR_LENGTH))
+				{
+					wifi_d("Dropping Deauth frame from other bssid: type=%d " MACSTR "\r\n", sub_type,
+						   MAC2STR(pieee_pkt_hdr->addr3));
+					LEAVE();
+					return ret;
+				}
+				wifi_d("wlan: HostMlme Disconnected: sub_type=%d\n", sub_type);
+#if 0
+				pmadapter->pending_disconnect_priv = priv;
+				wlan_recv_event(
+					priv, MLAN_EVENT_ID_DRV_DEFER_HANDLING,
+					MNULL);
+#endif
+            }
+            break;
+        case SUBTYPE_ACTION:
+            category    = *(payload + sizeof(wlan_802_11_header));
+            action_code = *(payload + sizeof(wlan_802_11_header) + 1);
+            /*wpa_supplicant only deals with those action frame below*/
+            if (category != IEEE_MGMT_ACTION_CATEGORY_WMM_TSPEC && category != IEEE_MGMT_ACTION_CATEGORY_FST &&
+                category != IEEE_MGMT_ACTION_CATEGORY_PUBLIC && category != IEEE_MGMT_ACTION_CATEGORY_RADIO_RSRC &&
+                category != IEEE_MGMT_ACTION_CATEGORY_PROTECTED_DUAL && category != IEEE_MGMT_ACTION_CATEGORY_QOS &&
+                category != IEEE_MGMT_ACTION_CATEGORY_FAST_BSS_TRANS &&
+                category != IEEE_MGMT_ACTION_CATEGORY_SA_QUERY && category != IEEE_MGMT_ACTION_CATEGORY_AV_STREAMING &&
+                category != IEEE_MGMT_ACTION_CATEGORY_WNM)
+            {
+                wifi_d("Drop action frame: category = %d, action_code=%d", category, action_code);
+                LEAVE();
+                return ret;
+            }
+            if (category == IEEE_MGMT_ACTION_CATEGORY_BLOCK_ACK)
+            {
+                wifi_d("Drop BLOCK ACK action frame: action_code=%d", action_code);
+                LEAVE();
+                return ret;
+            }
+            if ((category == IEEE_MGMT_ACTION_CATEGORY_PUBLIC) &&
+                (action_code == BSS_20_40_COEX || action_code == FILS_DISCOVERY))
+            {
+                wifi_d("Drop unneed public action frame %d", action_code);
+                LEAVE();
+                return ret;
+            }
+#ifdef DOT1AS_SUPPORT
+            if ((category == IEEE_MGMT_ACTION_CATEGORY_UNPROTECT_WNM) && (action_code == 0x1))
+            {
+                prx_pd->toa_tod_tstamps = wlan_le64_to_cpu(prx_pd->toa_tod_tstamps);
+                tstamps.t3              = prx_pd->toa_tod_tstamps >> 32;
+                tstamps.t2              = (t_u32)prx_pd->toa_tod_tstamps;
+                tstamps.t2_err       = 0;
+                tstamps.t3_err       = 0;
+                tstamps.ingress_time = pcb->moal_do_div(pmadapter->host_bbu_clk_delta, 10);
+                tstamps.ingress_time += tstamps.t2; // t2, t3 is 10ns
+                                                    // and delta is in 1
+                                                    // ns unit;
+                PRINTM(MINFO, "T2: %d, T3: %d, ingress: %lu\n", tstamps.t2, tstamps.t3, tstamps.ingress_time);
+            }
+#endif
+            if (memcmp(pieee_pkt_hdr->addr1, broadcast, MLAN_MAC_ADDR_LENGTH))
+                unicast = MTRUE;
+            break;
+        default:
+            break;
+    }
+    if (unicast == MTRUE)
+    {
+        if (memcmp(pieee_pkt_hdr->addr1, priv->curr_addr, MLAN_MAC_ADDR_LENGTH))
+        {
+            wifi_d("Dropping mgmt frame for others: type=%d " MACSTR "\r\n", sub_type, MAC2STR(pieee_pkt_hdr->addr1));
+            LEAVE();
+            return ret;
+        }
+    }
+
+#if 0
+	/* Allocate memory for event buffer */
+	ret = pcb->moal_malloc(pmadapter->pmoal_handle, MAX_EVENT_SIZE,
+			       MLAN_MEM_DEF, &event_buf);
+	if ((ret != MLAN_STATUS_SUCCESS) || !event_buf) {
+		PRINTM(MERROR, "Could not allocate buffer for event buf\n");
+		LEAVE();
+		return MLAN_STATUS_FAILURE;
+	}
+	pevent = (pmlan_event)event_buf;
+	pevent->bss_index = priv->bss_index;
+#ifdef ENABLE_802_11R
+	mgmt = (IEEE80211_MGMT *)payload;
+	if (
+		priv->bss_role == MLAN_BSS_ROLE_STA &&
+		!priv->curr_bss_params.host_mlme &&
+		sub_type == SUBTYPE_ACTION &&
+		mgmt->u.ft_resp.category == FT_CATEGORY &&
+		mgmt->u.ft_resp.action == FT_ACTION_RESPONSE &&
+		mgmt->u.ft_resp.status_code == 0) {
+		PRINTM(MCMND, "FT Action response received\n");
+#define FT_ACTION_HEAD_LEN (24 + 6 + 16)
+		pevent->event_id = MLAN_EVENT_ID_DRV_FT_RESPONSE;
+		pevent->event_len =
+			payload_len + MLAN_MAC_ADDR_LENGTH - FT_ACTION_HEAD_LEN;
+		memcpy_ext(pmadapter, (t_u8 *)pevent->event_buf,
+			   &mgmt->u.ft_resp.target_ap_addr,
+			   MLAN_MAC_ADDR_LENGTH, MLAN_MAC_ADDR_LENGTH);
+		memcpy_ext(pmadapter,
+			   (t_u8 *)(pevent->event_buf + MLAN_MAC_ADDR_LENGTH),
+			   payload + FT_ACTION_HEAD_LEN,
+			   payload_len - FT_ACTION_HEAD_LEN,
+			   pevent->event_len - MLAN_MAC_ADDR_LENGTH);
+	} else if (
+		priv->bss_role == MLAN_BSS_ROLE_STA &&
+		!priv->curr_bss_params.host_mlme &&
+		sub_type == SUBTYPE_AUTH &&
+		mgmt->u.auth.auth_alg == MLAN_AUTH_MODE_FT &&
+		mgmt->u.auth.auth_transaction == 2 &&
+		mgmt->u.auth.status_code == 0) {
+		PRINTM(MCMND, "FT auth response received \n");
+#define AUTH_PACKET_LEN (24 + 6 + 6)
+		pevent->event_id = MLAN_EVENT_ID_DRV_FT_RESPONSE;
+		pevent->event_len =
+			payload_len + MLAN_MAC_ADDR_LENGTH - AUTH_PACKET_LEN;
+		memcpy_ext(pmadapter, (t_u8 *)pevent->event_buf, mgmt->sa,
+			   MLAN_MAC_ADDR_LENGTH, MLAN_MAC_ADDR_LENGTH);
+		memcpy_ext(pmadapter,
+			   (t_u8 *)(pevent->event_buf + MLAN_MAC_ADDR_LENGTH),
+			   payload + AUTH_PACKET_LEN,
+			   payload_len - AUTH_PACKET_LEN,
+			   pevent->event_len - MLAN_MAC_ADDR_LENGTH);
+	} else {
+#endif
+		pevent->event_id = MLAN_EVENT_ID_DRV_MGMT_FRAME;
+		pevent->event_len = payload_len + sizeof(pevent->event_id);
+		pevent->event_buf[0] = band_config;
+		pevent->event_buf[1] = chan_num;
+		memcpy_ext(
+			pmadapter,
+			(t_u8 *)(pevent->event_buf + sizeof(pevent->event_id)),
+			payload, payload_len, payload_len);
+#ifdef DOT1AS_SUPPORT
+		// Append timestamp info at the end of event
+		if ((category == IEEE_MGMT_ACTION_CATEGORY_UNPROTECT_WNM) &&
+		    (action_code == 0x1)) {
+			memcpy_ext(pmadapter,
+				   (t_u8 *)(pevent->event_buf +
+					    sizeof(pevent->event_id) +
+					    payload_len),
+				   &tstamps, sizeof(struct timestamps),
+				   sizeof(struct timestamps));
+			pevent->event_len = payload_len +
+					    sizeof(pevent->event_id) +
+					    sizeof(struct timestamps);
+		}
+#endif
+#ifdef ENABLE_802_11R
+	}
+#endif
+	wlan_recv_event(priv, pevent->event_id, pevent);
+	if (event_buf)
+		pcb->moal_mfree(pmadapter->pmoal_handle, event_buf);
+#endif
+
+    memmove((uint8_t *)pieee_pkt_hdr + (sizeof(wlan_802_11_header) - MLAN_MAC_ADDR_LENGTH),
+            (uint8_t *)pieee_pkt_hdr + (sizeof(wlan_802_11_header)), payload_len - sizeof(wlan_802_11_header));
+
+    payload_len -= MLAN_MAC_ADDR_LENGTH;
+    if (payload_len > sizeof(wm_wifi.mgmt_resp.frame.frame))
+    {
+        wifi_w("The payload length (%d) overs the max length(%d), dropping mgmt frame: type=%d", payload_len,
+               sizeof(wm_wifi.mgmt_resp.frame.frame), sub_type);
+        dump_hex(payload, 64);
+        return MLAN_STATUS_FAILURE;
+    }
+
+    if (priv->bss_role == MLAN_BSS_ROLE_STA)
+    {
+        if (sub_type == (t_u16)SUBTYPE_AUTH)
+        {
+            nxp_wifi_event_mlme_t *auth_resp = &wm_wifi.mgmt_resp;
+
+            if (payload_len <= sizeof(auth_resp->frame.frame))
+            {
+                memset(auth_resp, 0, sizeof(nxp_wifi_event_mlme_t));
+                auth_resp->frame.frame_len = payload_len;
+                memcpy((void *)auth_resp->frame.frame, (const void *)pieee_pkt_hdr, payload_len);
+                if (wm_wifi.supp_if_callbk_fns->auth_resp_callbk_fn)
+                {
+                    wm_wifi.supp_if_callbk_fns->auth_resp_callbk_fn(wm_wifi.if_priv, auth_resp,
+                                                                    auth_resp->frame.frame_len);
+                }
+            }
+            else
+            {
+                wifi_e("Insufficient frame buffer");
+            }
+        }
+
+        if (sub_type == (t_u16)SUBTYPE_DEAUTH)
+        {
+            nxp_wifi_event_mlme_t *deauth_resp = &wm_wifi.mgmt_resp;
+
+            wlan_abort_split_scan();
+            wifi_user_scan_config_cleanup();
+
+            if (payload_len <= (int)sizeof(deauth_resp->frame.frame))
+            {
+                memset(deauth_resp, 0, sizeof(nxp_wifi_event_mlme_t));
+                deauth_resp->frame.frame_len = payload_len;
+                memcpy((void *)deauth_resp->frame.frame, (const void *)pieee_pkt_hdr, deauth_resp->frame.frame_len);
+                if (wm_wifi.supp_if_callbk_fns->deauth_callbk_fn)
+                {
+                    wm_wifi.supp_if_callbk_fns->deauth_callbk_fn(wm_wifi.if_priv, deauth_resp,
+                                                                 deauth_resp->frame.frame_len);
+                }
+            }
+            else
+            {
+                wifi_e("Insufficient frame buffer");
+            }
+        }
+
+        if (sub_type == (t_u16)SUBTYPE_DISASSOC)
+        {
+            nxp_wifi_event_mlme_t *disassoc_resp = &wm_wifi.mgmt_resp;
+
+            wlan_abort_split_scan();
+            wifi_user_scan_config_cleanup();
+
+            if (payload_len <= (int)sizeof(disassoc_resp->frame.frame))
+            {
+                memset(disassoc_resp, 0, sizeof(nxp_wifi_event_mlme_t));
+                disassoc_resp->frame.frame_len = payload_len;
+                memcpy((void *)disassoc_resp->frame.frame, (const void *)pieee_pkt_hdr, disassoc_resp->frame.frame_len);
+                if (wm_wifi.supp_if_callbk_fns->disassoc_callbk_fn)
+                {
+                    wm_wifi.supp_if_callbk_fns->disassoc_callbk_fn(wm_wifi.if_priv, disassoc_resp,
+                                                                   disassoc_resp->frame.frame_len);
+                }
+            }
+            else
+            {
+                wifi_e("Insufficient frame buffer");
+            }
+        }
+
+        if (sub_type == (t_u16)SUBTYPE_ACTION)
+        {
+            nxp_wifi_event_mlme_t *mgmt_rx = &wm_wifi.mgmt_rx;
+
+            if (payload_len <= (int)sizeof(mgmt_rx->frame.frame))
+            {
+                memset(mgmt_rx, 0, sizeof(nxp_wifi_event_mlme_t));
+                mgmt_rx->frame.frame_len = payload_len;
+                memcpy((void *)mgmt_rx->frame.frame, (const void *)pieee_pkt_hdr, mgmt_rx->frame.frame_len);
+                mgmt_rx->frame.freq = channel_to_frequency(chan_num, band_config);
+                if (wm_wifi.supp_if_callbk_fns->mgmt_rx_callbk_fn)
+                {
+                    wm_wifi.supp_if_callbk_fns->mgmt_rx_callbk_fn(wm_wifi.if_priv, mgmt_rx, mgmt_rx->frame.frame_len);
+                }
+            }
+            else
+            {
+                wifi_e("Insufficient frame buffer");
+            }
+        }
+    }
+    else if (priv->bss_role == MLAN_BSS_ROLE_UAP)
+    {
+        nxp_wifi_event_mlme_t *mgmt_rx = &wm_wifi.mgmt_rx;
+
+        mgmt_rx->frame.frame_len = payload_len;
+
+        if (mgmt_rx->frame.frame_len <= (int)sizeof(mgmt_rx->frame.frame))
+        {
+            memcpy((void *)mgmt_rx->frame.frame, (const void *)pieee_pkt_hdr, mgmt_rx->frame.frame_len);
+            mgmt_rx->frame.freq = channel_to_frequency(chan_num, band_config);
+            if (wm_wifi.supp_if_callbk_fns->mgmt_rx_callbk_fn)
+            {
+                wm_wifi.supp_if_callbk_fns->mgmt_rx_callbk_fn(wm_wifi.hapd_if_priv, mgmt_rx, mgmt_rx->frame.frame_len);
+            }
+        }
+        else
+        {
+            wifi_e("Insufficient frame buffer");
+        }
+    }
+
+    LEAVE();
+    return MLAN_STATUS_SUCCESS;
+}
+
+void wifi_is_wpa_supplicant_input(const uint8_t interface, const uint8_t *buffer, const uint16_t len)
+{
+    mlan_private *priv           = (mlan_private *)mlan_adap->priv[interface];
+    RxPD *prx_pd                 = (RxPD *)(void *)((t_u8 *)buffer + INTF_HEADER_LEN);
+    wlan_mgmt_pkt *pmgmt_pkt_hdr = MNULL;
+
+    /* Check if this is mgmt packet and needs to
+     * forwarded to app as an event
+     */
+    pmgmt_pkt_hdr          = (wlan_mgmt_pkt *)((t_u8 *)prx_pd + prx_pd->rx_pkt_offset);
+    pmgmt_pkt_hdr->frm_len = wlan_le16_to_cpu(pmgmt_pkt_hdr->frm_len);
+
+    if ((pmgmt_pkt_hdr->wlan_header.frm_ctl & IEEE80211_FC_MGMT_FRAME_TYPE_MASK) == 0)
+        wlan_process_802dot11_mgmt_pkt2(priv, (t_u8 *)&pmgmt_pkt_hdr->wlan_header,
+                                        pmgmt_pkt_hdr->frm_len + sizeof(wlan_mgmt_pkt) - sizeof(pmgmt_pkt_hdr->frm_len),
+                                        prx_pd);
+}
+
+void wifi_wpa_supplicant_eapol_input(const uint8_t interface,
+                                     const uint8_t *src_addr,
+                                     const uint8_t *buffer,
+                                     const uint16_t len)
+{
+    nxp_wifi_event_eapol_mlme_t *eapol_rx = &wm_wifi.eapol_rx;
+
+    memcpy((void *)eapol_rx->mac_addr, (const void *)src_addr, MLAN_MAC_ADDR_LENGTH);
+
+    eapol_rx->frame.frame_len = len;
+    memcpy((void *)eapol_rx->frame.frame, (const void *)buffer, eapol_rx->frame.frame_len);
+    if (wm_wifi.supp_if_callbk_fns->eapol_rx_callbk_fn)
+    {
+        wm_wifi.supp_if_callbk_fns->eapol_rx_callbk_fn(
+            interface == MLAN_BSS_TYPE_STA ? wm_wifi.if_priv : wm_wifi.hapd_if_priv, eapol_rx,
+            eapol_rx->frame.frame_len);
+    }
+}
+
+#define RX_PKT_TYPE_OFFSET  5U
+#define ETH_PROTO_EAPOL     0x888EU
+#define WIFI_SIZEOF_ETH_HDR 14U
+static t_u8 rfc1042_eth_hdr[MLAN_MAC_ADDR_LENGTH] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
+#endif
+
+static int wifi_low_level_input(const uint8_t interface, const uint8_t *buffer, const uint16_t len)
+{
+#if CONFIG_WPA_SUPP
+    RxPD *prx_pd  = (RxPD *)(void *)((t_u8 *)buffer + INTF_HEADER_LEN);
+    eth_hdr *ethh = MNULL;
+    t_u16 eth_proto;
+    t_u8 offset = 0;
+
+    if (*((t_u16 *)buffer + RX_PKT_TYPE_OFFSET) == PKT_TYPE_MGMT_FRAME)
+    {
+        wifi_is_wpa_supplicant_input(interface, buffer, len);
+        return WM_SUCCESS;
+    }
+
+    ethh = (eth_hdr *)((t_u8 *)prx_pd + prx_pd->rx_pkt_offset);
+
+    eth_proto = mlan_ntohs(ethh->h_proto);
+
+    if (memcmp((t_u8 *)prx_pd + prx_pd->rx_pkt_offset + WIFI_SIZEOF_ETH_HDR, rfc1042_eth_hdr,
+               sizeof(rfc1042_eth_hdr)) == 0U)
+    {
+        eth_llc_hdr *ethllchdr = (eth_llc_hdr *)(void *)((t_u8 *)prx_pd + prx_pd->rx_pkt_offset + WIFI_SIZEOF_ETH_HDR);
+        eth_proto              = mlan_ntohs(ethllchdr->type);
+        offset                 = sizeof(eth_llc_hdr);
+    }
+
+    if (eth_proto == ETH_PROTO_EAPOL)
+    {
+        wifi_wpa_supplicant_eapol_input(interface, ethh->src_addr, (uint8_t *)(ethh + 1) + offset,
+                                        prx_pd->rx_pkt_length - sizeof(eth_hdr) - offset);
+        return WM_SUCCESS;
+    }
+#endif
+    if (wifi_rx_status == WIFI_DATA_BLOCK)
+    {
+        wifi_rx_block_cnt++;
+        return WM_SUCCESS;
+    }
+
+    if (mlan_adap->ps_state == PS_STATE_SLEEP)
+    {
+        OSA_RWLockWriteUnlock(&sleep_rwlock);
+        mlan_adap->ps_state = PS_STATE_AWAKE;
+    }
+
+    if (wm_wifi.data_input_callback != NULL)
+    {
+        wm_wifi.data_input_callback(interface, buffer, len);
+        return WM_SUCCESS;
+    }
+
+
+    return -WM_FAIL;
+}
+
+#define ERR_INPROGRESS -5
+
+#define WL_ID_LL_OUTPUT "wifi_low_level_output"
+
+void wifi_tx_card_awake_lock(void)
+{
+    int ret;
+
+    /* Write mutex is used to avoid the case that, during waitting for sleep confirm cmd response,
+     * wifi_driver_tx task might be scheduled and send data to FW */
+    (void)OSA_MutexLock((osa_mutex_handle_t)sleep_rwlock.write_mutex, osaWaitForever_c);
+    ret = OSA_RWLockReadLock(&sleep_rwlock, MAX_WAIT_TIME);
+    (void)OSA_MutexUnlock((osa_mutex_handle_t)sleep_rwlock.write_mutex);
+    if (ret != WM_SUCCESS)
+    {
+#if CONFIG_WIFI_PS_DEBUG
+        wifi_e("Failed to wakeup card for Tx");
+#endif
+#if CONFIG_WIFI_RECOVERY
+        wifi_recovery_enable = true;
+#else
+        assert(0);
+#endif
+    }
+}
+
+void wifi_tx_card_awake_unlock(void)
+{
+    OSA_RWLockReadUnlock(&sleep_rwlock);
+}
+
+#if CONFIG_WMM
+
+#define ETHER_TYPE_IP_01         0xc
+#define ETHER_TYPE_IP_02         0xd
+#define ETHER_TYPE_IPV4_VALUE_01 0x8
+#define ETHER_TYPE_IPV4_VALUE_02 0x0
+#define WMM_PACKET_TOS_IV4       0xf
+#define PRIORITY_COMPENSATOR     0x20
+#define UDP_IDENTIFIER_POS       0x11
+#define UDP_IDENTIFIER_VAL       0xda
+
+#define ETHER_TYPE_IPV6_VALUE_01 0x86
+#define ETHER_TYPE_IPV6_VALUE_02 0xdd
+#define WMM_PACKET_TOS_IPV6_01   0xe
+#define WMM_PACKET_TOS_IPV6_02   0xf
+#define TOS_MASK_IPV6            0x0ff0 /* 0000111111110000 */
+
+void wifi_wmm_init()
+{
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[0];
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    mlan_status status      = MLAN_STATUS_SUCCESS;
+
+    status =
+        wlan_prepare_cmd(pmpriv, HostCmd_CMD_WMM_PARAM_CONFIG, HostCmd_ACT_GEN_SET, 0, MNULL, &pmadapter->ac_params);
+    if (status != MLAN_STATUS_SUCCESS)
+    {
+        wifi_e("ERR: WMM wlan_prepare_cmd returned status=0x%x", status);
+    }
+}
+
+/* Packet priority is 16th byte of payload.
+ * Provided that the packet is IPV4 type
+ * Since value comes between the range of 0-255, coversion is expected between 0-7 to map to TIDs.
+ * */
+t_u32 wifi_wmm_get_pkt_prio(void *buf, t_u8 *tid)
+{
+    bool ip_hdr = 0;
+
+    if (buf == NULL)
+        return -WM_FAIL;
+    t_u8 *type_01 = net_stack_buffer_skip(buf, ETHER_TYPE_IP_01);
+    t_u8 *type_02 = net_stack_buffer_skip(buf, ETHER_TYPE_IP_02);
+    if (*type_01 == ETHER_TYPE_IPV4_VALUE_01 && *type_02 == ETHER_TYPE_IPV4_VALUE_02)
+    {
+        t_u8 *id = net_stack_buffer_skip(buf, WMM_PACKET_TOS_IV4);
+        *tid     = *id / PRIORITY_COMPENSATOR;
+        ip_hdr   = 1;
+    }
+    else if (*type_01 == ETHER_TYPE_IPV6_VALUE_01 && *type_02 == ETHER_TYPE_IPV6_VALUE_02)
+    {
+        t_u8 *tos1     = net_stack_buffer_skip(buf, WMM_PACKET_TOS_IPV6_01);
+        t_u8 *tos2     = net_stack_buffer_skip(buf, WMM_PACKET_TOS_IPV6_02);
+        t_u16 ipv6_tos = (*tos1 << 8) | (*tos2);
+        *tid           = (t_u8)(((ipv6_tos & TOS_MASK_IPV6) >> 4) / PRIORITY_COMPENSATOR);
+        ip_hdr         = 1;
+    }
+    if (ip_hdr)
+    {
+        switch (*tid)
+        {
+            case 0:
+                return WMM_AC_BE;
+            case 1:
+            case 2:
+                return WMM_AC_BK;
+            case 3:
+                return WMM_AC_BE;
+            case 4:
+            case 5:
+                return WMM_AC_VI;
+            case 6:
+            case 7:
+                return WMM_AC_VO;
+            default:
+                return WMM_AC_BE;
+        }
+    }
+    else
+        return WMM_AC_BE;
+}
+
+INLINE t_u8 wifi_wmm_get_packet_cnt(void)
+{
+    return (MAX_WMM_BUF_NUM - mlan_adap->outbuf_pool.free_cnt);
+}
+
+#if CONFIG_WIFI_TP_STAT
+t_u32 g_wifi_xmit_schedule_end = 0;
+#endif
+
+#if CONFIG_AMSDU_IN_AMPDU
+/* aggregate one amsdu packet and xmit */
+static mlan_status wifi_xmit_amsdu_pkts(mlan_private *priv, t_u8 ac, raListTbl *ralist)
+{
+    outbuf_t *buf                = MNULL;
+    t_u32 max_amsdu_size         = MIN(priv->max_amsdu, priv->adapter->tx_buffer_size);
+    t_u32 amsdu_offset           = sizeof(TxPD) + INTF_HEADER_LEN;
+    t_u8 amsdu_cnt               = 0;
+    t_u32 amsdu_buf_used_size    = 0;
+    int amsdu_buf_available_size = max_amsdu_size - amsdu_buf_used_size;
+    t_u32 amsdu_pkt_len          = 0;
+    int pad_len                  = 0;
+    int last_pad_len             = 0;
+#if CONFIG_WIFI_TP_STAT
+    t_u8 *buf_end = MNULL;
+#endif
+
+    while (ralist->total_pkts > 0)
+    {
+        mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+        buf = (outbuf_t *)util_peek_list(mlan_adap->pmoal_handle, &ralist->buf_head, MNULL, MNULL);
+        ASSERT(buf != NULL);
+
+#if CONFIG_WIFI_TP_STAT
+        buf_end = &buf->data[0] + buf->tx_pd.tx_pkt_length;
+        wifi_stat_tx_dequeue_start(buf_end, g_wifi_xmit_schedule_end);
+#endif
+
+        /* calculate amsdu buffer length */
+        amsdu_buf_used_size += buf->tx_pd.tx_pkt_length + sizeof(TxPD) + INTF_HEADER_LEN;
+        if (amsdu_cnt == 0)
+        {
+            /* First A-MSDU packet */
+            amsdu_buf_available_size = max_amsdu_size - amsdu_buf_used_size - LLC_SNAP_LEN;
+        }
+        else
+        {
+            /* The following A-MSDU packets */
+            amsdu_pkt_len            = amsdu_buf_used_size - sizeof(TxPD) - INTF_HEADER_LEN + LLC_SNAP_LEN;
+            pad_len                  = ((amsdu_pkt_len & 3)) ? (4 - ((amsdu_pkt_len)&3)) : 0;
+            amsdu_buf_available_size = max_amsdu_size - amsdu_pkt_len - pad_len;
+        }
+
+        /* dequeue and store this buffer in amsdu buffer */
+        if (amsdu_buf_available_size >= 0)
+        {
+            util_unlink_list(mlan_adap->pmoal_handle, &ralist->buf_head, &buf->entry, MNULL, MNULL);
+            ralist->total_pkts--;
+            mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+
+            amsdu_offset += wlan_11n_form_amsdu_pkt(wifi_get_amsdu_outbuf(amsdu_offset), &buf->data[0],
+                                                    buf->tx_pd.tx_pkt_length, &last_pad_len);
+            amsdu_cnt++;
+
+#if CONFIG_WIFI_TP_STAT
+            wifi_stat_tx_dequeue_end(buf_end);
+#endif
+            wifi_wmm_buf_put(buf);
+            priv->wmm.pkts_queued[ac]--;
+        }
+        else
+        {
+            mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+        }
+
+        /*
+         * amsdu buffer room not enough, or last packet in this ra_list in AC queue,
+         * add amsdu buffer to imu queue
+         */
+        if (amsdu_buf_available_size < 0 || ralist->total_pkts == 0)
+        {
+            return wlan_xmit_wmm_amsdu_pkt((mlan_wmm_ac_e)ac, priv->bss_index, amsdu_offset - last_pad_len,
+                                           wifi_get_amsdu_outbuf(0), amsdu_cnt);
+        }
+    }
+    return MLAN_STATUS_SUCCESS;
+}
+#endif
+
+t_u8 wifi_txbuf_available()
+{
+#ifdef RW610
+    return !(HAL_ImuIsTxBufQueueEmpty(kIMU_LinkCpu1Cpu3));
+#else
+    return !!(mlan_adap->mp_wr_bitmap);
+#endif
+}
+
+static inline t_u8 wifi_is_max_tx_cnt(t_u8 pkt_cnt)
+{
+#ifdef RW610
+    return (pkt_cnt >= IMU_PAYLOAD_SIZE) ? MTRUE : MFALSE;
+#else
+    return (pkt_cnt >= SDIO_PAYLOAD_SIZE) ? MTRUE : MFALSE;
+#endif
+}
+
+/* dequeue and xmit one packet */
+static mlan_status wifi_xmit_pkts(mlan_private *priv, t_u8 ac, raListTbl *ralist)
+{
+    mlan_status ret;
+    outbuf_t *buf = MNULL;
+
+    mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+    buf = (outbuf_t *)util_dequeue_list(mlan_adap->pmoal_handle, &ralist->buf_head, MNULL, MNULL);
+    ralist->total_pkts--;
+    mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+    ASSERT(buf != MNULL);
+
+    /* TODO: this may go wrong for TxPD->tx_pkt_type 0xe5 */
+    /* this will get card port lock and probably sleep */
+#if CONFIG_TX_RX_ZERO_COPY
+    ret = wlan_xmit_wmm_pkt(priv->bss_index, buf->tx_pd.tx_pkt_length + sizeof(TxPD) + INTF_HEADER_LEN, (t_u8 *)buf);
+#else
+    ret = wlan_xmit_wmm_pkt(priv->bss_index, buf->tx_pd.tx_pkt_length + sizeof(TxPD) + INTF_HEADER_LEN,
+                            (t_u8 *)&buf->intf_header[0]);
+#endif
+    if (ret != MLAN_STATUS_SUCCESS)
+    {
+#ifdef RW610
+        ASSERT(0);
+#else
+        mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+        util_enqueue_list_head(mlan_adap->pmoal_handle, &ralist->buf_head, &buf->entry, MNULL, MNULL);
+        ralist->total_pkts++;
+        mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &ralist->buf_head.plock);
+        return MLAN_STATUS_RESOURCE;
+#endif
+    }
+
+    wifi_wmm_buf_put(buf);
+    priv->wmm.pkts_queued[ac]--;
+
+    return MLAN_STATUS_SUCCESS;
+}
+
+/*
+ *  xmit all buffers under this ralist
+ *  should be called inside wmm tid_tbl_ptr ra_list lock,
+ *  return MLAN_STATUS_SUCESS to continue looping ralists,
+ *  return MLAN_STATUS_RESOURCE to break looping ralists
+ */
+static mlan_status wifi_xmit_ralist_pkts(mlan_private *priv, t_u8 ac, raListTbl *ralist, t_u8 *pkt_cnt)
+{
+    mlan_status ret;
+
+    if (ralist->tx_pause == MTRUE)
+        return MLAN_STATUS_SUCCESS;
+
+    while (ralist->total_pkts > 0)
+    {
+        if ((wifi_txbuf_available() == MFALSE) || (WIFI_DATA_RUNNING != wifi_tx_status))
+            break;
+
+#if CONFIG_AMSDU_IN_AMPDU
+        if (wlan_is_amsdu_allowed(priv, priv->bss_index, ralist->total_pkts, ac))
+            ret = wifi_xmit_amsdu_pkts(priv, ac, ralist);
+        else
+#endif
+            ret = wifi_xmit_pkts(priv, ac, ralist);
+
+        if (ret != MLAN_STATUS_SUCCESS)
+            return ret;
+
+        /*
+         * in amsdu case,
+         * multiple packets aggregated as one amsdu packet, are counted as one imu packet
+         */
+        (*pkt_cnt)++;
+        if (wifi_is_max_tx_cnt(*pkt_cnt) == MTRUE)
+        {
+            wlan_flush_wmm_pkt(*pkt_cnt);
+            *pkt_cnt = 0;
+        }
+    }
+    return MLAN_STATUS_SUCCESS;
+}
+
+/*
+ *  dequeue and xmit all buffers under ac queue
+ *  loop each ac queue
+ *  loop each ralist
+ *  dequeue all buffers from buf_head list and xmit
+ */
+static int wifi_xmit_wmm_ac_pkts_enh(mlan_private *priv)
+{
+    int ac;
+    mlan_status ret;
+    t_u8 pkt_cnt       = 0;
+    raListTbl *ralist  = MNULL;
+    tid_tbl_t *tid_ptr = MNULL;
+
+#if CONFIG_WIFI_TP_STAT
+    g_wifi_xmit_schedule_end = OSA_GetTimestamp();
+#endif
+
+    for (ac = WMM_AC_VO; ac >= 0; ac--)
+    {
+        tid_ptr = &priv->wmm.tid_tbl_ptr[ac];
+
+        mlan_adap->callbacks.moal_semaphore_get(mlan_adap->pmoal_handle, &tid_ptr->ra_list.plock);
+
+        if (priv->wmm.pkts_queued[ac] == 0)
+        {
+            mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &tid_ptr->ra_list.plock);
+            continue;
+        }
+
+        ralist =
+            (raListTbl *)util_peek_list(mlan_adap->pmoal_handle, (mlan_list_head *)&tid_ptr->ra_list, MNULL, MNULL);
+
+        while (ralist && ralist != (raListTbl *)&tid_ptr->ra_list)
+        {
+            ret = wifi_xmit_ralist_pkts(priv, ac, ralist, &pkt_cnt);
+            if (ret != MLAN_STATUS_SUCCESS)
+            {
+                mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &tid_ptr->ra_list.plock);
+                goto RET;
+            }
+            ralist = ralist->pnext;
+        }
+        mlan_adap->callbacks.moal_semaphore_put(mlan_adap->pmoal_handle, &tid_ptr->ra_list.plock);
+    }
+
+RET:
+    wlan_flush_wmm_pkt(pkt_cnt);
+    return WM_SUCCESS;
+}
+
+t_void wlan_process_bypass_txq(t_u8 interface)
+{
+    bypass_outbuf_t *buf;
+    mlan_status status = MLAN_STATUS_SUCCESS;
+    pmlan_private priv = mlan_adap->priv[interface];
+
+    wifi_tx_card_awake_lock();
+#ifndef RW610
+    wifi_sdio_lock();
+#endif
+
+    while (!wlan_bypass_txq_empty(interface) && (wifi_txbuf_available() == MTRUE))
+    {
+        wlan_get_bypass_lock(interface);
+        buf = (bypass_outbuf_t *)util_dequeue_list(mlan_adap->pmoal_handle, &priv->bypass_txq, MNULL, MNULL);
+        priv->bypass_txq_cnt--;
+        wlan_put_bypass_lock(interface);
+
+        status = wlan_xmit_bypass_pkt((t_u8 *)&buf->intf_header[0],
+                                      buf->tx_pd.tx_pkt_length + sizeof(TxPD) + INTF_HEADER_LEN, interface);
+
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(buf);
+#else
+        OSA_MemoryPoolFree(buf_1536_MemoryPool, buf);
+#endif
+
+        if (status != MLAN_STATUS_SUCCESS)
+        {
+            wifi_d("[%s] bypass xmit pkt failed \r\n", __func__);
+        }
+    }
+
+#ifndef RW610
+    wifi_sdio_unlock();
+#endif
+    wifi_tx_card_awake_unlock();
+}
+
+typedef enum _wifi_tx_event
+{
+    TX_TYPE_DATA = 10U,
+    TX_TYPE_NULL_DATA,
+    TX_TYPE_BYPASS_DATA,
+} wifi_tx_event_t;
+
+#ifdef __ZEPHYR__
+static void notify_wifi_driver_tx_event(uint32_t events)
+{
+    struct bus_message msg;
+    osa_status_t status;
+
+    if (events & WIFI_EVENT_TX_DATA)
+    {
+        msg.event = MLAN_TYPE_DATA;
+    }
+    else if (events & WIFI_EVENT_TX_NULL_DATA)
+    {
+        msg.event = MLAN_TYPE_NULL_DATA;
+    }
+    else if (events & WIFI_EVENT_TX_BYPASS_DATA)
+    {
+        msg.event = MLAN_TYPE_BYPASS_DATA;
+    }
+    else
+    {
+        msg.event = MLAN_TYPE_DATA;
+        wifi_w("unknown tx event");
+    }
+
+    msg.reason = (events & 1) ? MLAN_BSS_TYPE_STA : MLAN_BSS_TYPE_UAP;
+
+    status = OSA_MsgQPut((osa_msgq_handle_t)wm_wifi.tx_data, &msg);
+    if (status == KOSA_StatusSuccess)
+    {
+        if (msg.event == MLAN_TYPE_BYPASS_DATA && !OSA_IsISR())
+        {
+            OSA_TaskYield();
+        }
+    }
+}
+#endif
+
+int send_wifi_driver_tx_data_event(t_u8 interface)
+{
+    osa_event_flags_t events;
+
+    events = (1U << interface) | WIFI_EVENT_TX_DATA;
+
+    if(1 != wm_wifi.wifi_core_init_done)
+        return 0;
+
+#ifdef __ZEPHYR__
+    notify_wifi_driver_tx_event(events);
+#else
+    (void)OSA_EventSet((osa_event_handle_t)wm_wifi.wifi_event_Handle, events);
+    if (!__get_IPSR())
+    {
+        OSA_TaskYield();
+    }
+#endif
+
+    return 0;
+}
+
+int send_wifi_driver_tx_null_data_event(t_u8 interface)
+{
+    osa_event_flags_t events;
+
+    events = (1U << interface) | WIFI_EVENT_TX_NULL_DATA;
+
+#ifdef __ZEPHYR__
+    notify_wifi_driver_tx_event(events);
+#else
+    (void)OSA_EventSet((osa_event_handle_t)wm_wifi.wifi_event_Handle, events);
+    if (!__get_IPSR())
+    {
+        OSA_TaskYield();
+    }
+#endif
+
+    return 0;
+}
+
+int send_wifi_driver_bypass_data_event(t_u8 interface)
+{
+    osa_event_flags_t events;
+
+    events = (1U << interface) | WIFI_EVENT_TX_BYPASS_DATA;
+
+#ifdef __ZEPHYR__
+    notify_wifi_driver_tx_event(events);
+#else
+    (void)OSA_EventSet((osa_event_handle_t)wm_wifi.wifi_event_Handle, events);
+    if (!__get_IPSR())
+    {
+        OSA_TaskYield();
+    }
+#endif
+
+    return 0;
+}
+
+static void wifi_drv_tx_task(osa_task_param_t arg)
+{
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[0];
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    t_u8 i;
+    t_u16 event    = 0;
+    t_u8 interface = 0;
+#ifdef __ZEPHYR__
+    struct bus_message msg;
+    osa_status_t status;
+#else
+    osa_event_flags_t flagsToWait =
+        WIFI_EVENT_STA | WIFI_EVENT_UAP | WIFI_EVENT_TX_DATA | WIFI_EVENT_TX_NULL_DATA | WIFI_EVENT_TX_BYPASS_DATA;
+    osa_event_flags_t pSetFlags;
+#endif
+
+    for (;;)
+    {
+        event     = 0;
+        interface = 0;
+
+#if CONFIG_ECSA
+        /*
+         * Reduce block tx check interval, try to make it sync with ECSA status.
+         */
+        while (true == get_ecsa_block_tx_flag())
+        {
+            OSA_TimeDelay(wm_wifi.beacon_period);
+        }
+#endif
+#ifdef __ZEPHYR__
+        status = OSA_MsgQGet((osa_msgq_handle_t)wm_wifi.tx_data, &msg, osaWaitForever_c);
+        if (status == KOSA_StatusSuccess)
+        {
+            event     = msg.event;
+            interface = msg.reason;
+        }
+#else
+        (void)OSA_EventWait((osa_event_handle_t)wm_wifi.wifi_event_Handle, flagsToWait, false, osaWaitForever_c,
+                            &pSetFlags);
+
+        OSA_EventClear((osa_event_handle_t)wm_wifi.wifi_event_Handle, WIFI_EVENT_STA | WIFI_EVENT_UAP |
+                                                                          WIFI_EVENT_TX_DATA | WIFI_EVENT_TX_NULL_DATA |
+                                                                          WIFI_EVENT_TX_BYPASS_DATA);
+
+        if ((pSetFlags & (WIFI_EVENT_STA | WIFI_EVENT_UAP | WIFI_EVENT_TX_DATA | WIFI_EVENT_TX_NULL_DATA |
+                          WIFI_EVENT_TX_BYPASS_DATA)) == 0U)
+        {
+            continue;
+        }
+
+        if (pSetFlags & WIFI_EVENT_STA)
+        {
+            interface = MLAN_BSS_TYPE_STA;
+        }
+
+        if (pSetFlags & WIFI_EVENT_UAP)
+        {
+            interface = MLAN_BSS_TYPE_UAP;
+        }
+
+        if ((interface != MLAN_BSS_TYPE_STA) && (interface != MLAN_BSS_TYPE_UAP))
+        {
+            continue;
+        }
+
+        if (pSetFlags & WIFI_EVENT_TX_DATA)
+        {
+            event = MLAN_TYPE_DATA;
+        }
+
+        if (pSetFlags & WIFI_EVENT_TX_NULL_DATA)
+        {
+            event = MLAN_TYPE_NULL_DATA;
+        }
+
+        if (pSetFlags & WIFI_EVENT_TX_BYPASS_DATA)
+        {
+            event = MLAN_TYPE_BYPASS_DATA;
+        }
+#endif
+        pmadapter = mlan_adap;
+
+#if CONFIG_HOST_SLEEP
+        wakelock_get();
+#endif
+        if (event == MLAN_TYPE_DATA || event == MLAN_TYPE_NULL_DATA || event == MLAN_TYPE_BYPASS_DATA)
+        {
+#if CONFIG_WMM_UAPSD
+            while (pmadapter->pps_uapsd_mode && (pmadapter->tx_lock_flag == MTRUE))
+            {
+                OSA_TimeDelay(1);
+            }
+#endif
+            for (i = 0; i < MLAN_MAX_BSS_NUM; i++)
+            {
+                if (!wlan_bypass_txq_empty(i))
+                {
+                    /*Give high priority to xmit bypass txqueue*/
+                    wlan_process_bypass_txq(i);
+                }
+            }
+
+            /* Send packet when the outbuf pool is not empty and not in block tx status*/
+            if ((wifi_wmm_get_packet_cnt() > 0) && (WIFI_DATA_RUNNING == wifi_tx_status))
+            {
+                for (i = 0; i < MLAN_MAX_BSS_NUM; i++)
+                {
+                    pmpriv = pmadapter->priv[i];
+                    if (!pmpriv->media_connected || pmpriv->tx_pause)
+                    {
+                        continue;
+                    }
+
+                    wifi_tx_card_awake_lock();
+#ifndef RW610
+                    wifi_sdio_lock();
+#endif
+                    wifi_xmit_wmm_ac_pkts_enh(pmpriv);
+#ifndef RW610
+                    wifi_sdio_unlock();
+#endif
+                    wifi_tx_card_awake_unlock();
+                }
+            }
+#if CONFIG_WMM_UAPSD
+            else
+            {
+                if (event == MLAN_TYPE_NULL_DATA)
+                {
+                    wifi_tx_card_awake_lock();
+                    /* send null packet until the finish of CMD response processing */
+                    OSA_SemaphoreWait((osa_semaphore_handle_t)uapsd_sem, osaWaitForever_c);
+                    pmpriv = pmadapter->priv[interface];
+                    if (pmadapter->pps_uapsd_mode && pmpriv->media_connected && pmadapter->gen_null_pkt)
+                    {
+                        if (wlan_send_null_packet(
+                                pmpriv, MRVDRV_TxPD_POWER_MGMT_NULL_PACKET | MRVDRV_TxPD_POWER_MGMT_LAST_PACKET) ==
+                            MLAN_STATUS_SUCCESS)
+                        {
+                            pmadapter->tx_lock_flag = MTRUE;
+                        }
+                        else
+                        {
+                            OSA_SemaphorePost((osa_semaphore_handle_t)uapsd_sem);
+                            pmadapter->tx_lock_flag = MFALSE;
+                        }
+                    }
+                    else
+                    {
+                        wifi_d(
+                            "No need to send null packet, pps_uapsd_mode: %d, media_connected: %d, gen_null_pkt: "
+                            "%d",
+                            pmadapter->pps_uapsd_mode, pmpriv->media_connected, pmadapter->gen_null_pkt);
+                        OSA_SemaphorePost((osa_semaphore_handle_t)uapsd_sem);
+                        pmadapter->tx_lock_flag = MFALSE;
+                    }
+                    wifi_tx_card_awake_unlock();
+                }
+            }
+#endif
+        }
+#if CONFIG_HOST_SLEEP
+        wakelock_put();
+#endif
+    }
+}
+#endif /* CONFIG_WMM */
+
+#ifndef __ZEPHYR__
+#if CONFIG_11AX
+#if CONFIG_TCP_ACK_ENH
+#define ETH_PROTO_IP     0x0800U
+#define WIFI_IPPROTO_TCP 6
+
+#define RATEID_VHT_MCS7_1SS_BW80 58
+#define RATEID_VHT_MCS7_1SS_BW40 48
+#define RATEID_VHT_MCS7_1SS_BW20 38
+
+#define RATEID_VHT_MCS8_1SS_BW80 59
+#define RATEID_VHT_MCS8_1SS_BW40 49
+#define RATEID_VHT_MCS8_1SS_BW20 39
+
+#define RATEID_VHT_MCS9_1SS_BW80 60
+#define RATEID_VHT_MCS9_1SS_BW40 50
+#define RATEID_VHT_MCS9_1SS_BW20 40
+
+#define RATEID_HE_MCS9_1SS_BW80 94
+#define RATEID_HE_MCS8_1SS_BW40 81
+#define RATEID_HE_MCS4_1SS_BW40 77
+#define RATEID_HE_MCS7_1SS_BW20 68
+
+static int wlan_is_tcp_ack(mlan_private *priv, const t_u8 *pmbuf)
+{
+    eth_hdr *ethh = NULL;
+    ip_hdr *iph   = NULL;
+    tcp_hdr *tcph = NULL;
+
+    ENTER();
+
+    /** check the tcp packet */
+#if CONFIG_TX_RX_ZERO_COPY
+    ethh = (eth_hdr *)(((outbuf_t *)pmbuf)->eth_header);
+#else
+    ethh = (eth_hdr *)(pmbuf);
+#endif
+    if (mlan_ntohs(ethh->h_proto) != ETH_PROTO_IP)
+    {
+        LEAVE();
+        return 0;
+    }
+#if CONFIG_TX_RX_ZERO_COPY
+    iph = (ip_hdr *)(((outbuf_t *)pmbuf)->payload);
+#else
+    iph  = (ip_hdr *)((t_u8 *)ethh + sizeof(eth_hdr));
+#endif
+    if (iph->protocol != WIFI_IPPROTO_TCP)
+    {
+        LEAVE();
+        return 0;
+    }
+#if CONFIG_TX_RX_ZERO_COPY
+    tcph = (tcp_hdr *)(net_stack_buffer_skip(((outbuf_t *)pmbuf)->buffer, (uint16_t)(iph->ihl * 4)));
+#else
+    tcph = (tcp_hdr *)((t_u8 *)iph + iph->ihl * 4);
+#endif
+
+    if (*((t_u8 *)tcph + 13) == 0x10)
+    {
+        /* Only replace ACK */
+        if (mlan_ntohs(iph->tot_len) > (iph->ihl + tcph->_hdrlen_rsvd_flags.doff) * 4)
+        {
+            /* Don't drop ACK with payload */
+            /* TODO: should we delete previous TCP session */
+            LEAVE();
+            return 0;
+        }
+        return 1;
+    }
+
+    LEAVE();
+    return 0;
+}
+#endif /** CONFIG_TCP_ACK_ENH */
+#endif /** CONFIG_11AX*/
+#endif
+
+#if CONFIG_WMM
+
+int wifi_add_to_bypassq(const t_u8 interface, void *pkt, t_u32 len)
+{
+    t_u32 pkt_len            = 0;
+    t_u32 link_point_len     = 0;
+    bypass_outbuf_t *poutbuf = NULL;
+    t_u16 eth_type           = 0;
+    t_u32 magic_cookie       = 0;
+
+    eth_type = mlan_ntohs(*(t_u16 *)(net_stack_buffer_skip(pkt, MLAN_ETHER_PKT_TYPE_OFFSET)));
+
+    if (len > MLAN_ETHER_PKT_DHCP_MAGIC_COOKIE_OFFSET)
+    {
+        magic_cookie = mlan_ntohl(*((t_u32 *)(net_stack_buffer_skip(pkt, MLAN_ETHER_PKT_DHCP_MAGIC_COOKIE_OFFSET))));
+    }
+
+    if ((eth_type == MLAN_ETHER_PKT_TYPE_EAPOL) || (eth_type == MLAN_ETHER_PKT_TYPE_ARP) ||
+        (magic_cookie == MLAN_ETHER_PKT_DHCP_MAGIC_COOKIE))
+    {
+        /*Dword align*/
+        pkt_len        = sizeof(TxPD) + INTF_HEADER_LEN;
+        link_point_len = sizeof(mlan_linked_list);
+
+#if !CONFIG_MEM_POOLS
+        poutbuf = OSA_MemoryAllocate(link_point_len + pkt_len + len);
+#else
+        poutbuf = (bypass_outbuf_t *)OSA_MemoryPoolAllocate(buf_1536_MemoryPool);
+#endif
+        if (!poutbuf)
+        {
+            wuap_e("[%s] ERR:Cannot allocate buffer!\r\n", __func__);
+            mlan_adap->priv[interface]->tx_overrun_cnt++;
+            return -WM_FAIL;
+        }
+
+        (void)memset((t_u8 *)poutbuf, 0, link_point_len + pkt_len);
+
+        (void)net_stack_buffer_copy_partial(pkt, (void *)((t_u8 *)poutbuf + link_point_len + pkt_len), (t_u16)len, 0);
+
+        /* process packet headers with interface header and TxPD */
+        process_pkt_hdrs((void *)((t_u8 *)poutbuf + link_point_len), pkt_len + len, interface, 0, 0);
+
+        wlan_add_buf_bypass_txq((t_u8 *)poutbuf, interface);
+        send_wifi_driver_bypass_data_event(interface);
+
+        return WM_SUCCESS;
+    }
+
+    return -WM_FAIL;
+}
+#endif
+
+int wifi_low_level_output(const t_u8 interface,
+                          const t_u8 *sd_buffer,
+                          const t_u16 len
+#if CONFIG_WMM
+                          ,
+                          t_u8 pkt_prio,
+                          t_u8 tid
+#endif
+)
+{
+    int ret;
+#if CONFIG_TX_RX_ZERO_COPY
+    const t_u8 *buffer = ((outbuf_t *)sd_buffer)->eth_header;
+#else
+    const t_u8 *buffer = sd_buffer +
+#if CONFIG_WMM
+                         sizeof(mlan_linked_list) +
+#endif
+                         sizeof(TxPD) + INTF_HEADER_LEN;
+#endif
+#if !CONFIG_WMM
+    int retry = retry_attempts;
+    mlan_status i;
+#endif
+
+    /** Tx control */
+    t_u32 tx_control = 0;
+#ifndef __ZEPHYR__
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[interface];
+#endif
+
+    w_pkt_d("Data TX: Kernel=>Driver, if %d, len %d", interface, len);
+
+    // wakelock_get(WL_ID_LL_OUTPUT);
+    /* Following condition is added to check if device is not connected and data packet is being transmitted */
+#ifndef __ZEPHYR__
+    if ((pmpriv->media_connected == MFALSE))
+    {
+#if CONFIG_WMM
+        wifi_wmm_buf_put((outbuf_t *)sd_buffer);
+        wifi_wmm_drop_no_media(interface);
+#endif
+        return -WM_E_BUSY;
+    }
+
+#if CONFIG_11AX
+#if CONFIG_TCP_ACK_ENH
+    if ((interface == MLAN_BSS_TYPE_STA) && (pmpriv->enable_tcp_ack_enh == MTRUE) &&
+        (pmpriv->curr_bss_params.bss_descriptor.phe_cap != NULL))
+    {
+#if CONFIG_TX_RX_ZERO_COPY
+        ret = wlan_is_tcp_ack(pmpriv, sd_buffer);
+#else
+        ret = wlan_is_tcp_ack(pmpriv, buffer);
+#endif
+        if (ret)
+        {
+            if (pmpriv->curr_bss_params.bss_descriptor.curr_bandwidth == BW_80MHZ)
+            {
+                if (pmpriv->curr_bss_params.bss_descriptor.phe_cap != NULL)
+                {
+                    tx_control = (RATEID_HE_MCS9_1SS_BW80 << 16) | TXPD_TXRATE_ENABLE;
+                }
+                else if (pmpriv->curr_bss_params.bss_descriptor.pvht_cap != NULL)
+                {
+                    tx_control = (RATEID_VHT_MCS9_1SS_BW80 << 16) | TXPD_TXRATE_ENABLE;
+                }
+#if CONFIG_WMM
+                /* Though TID is not used in case of TCP traffic,
+                 * but making tid as voice traffic is a way to tell firmware to not to use
+                 * MCS rates above 9 for TCP ack packets.
+                 * This introduction is harmless for TCP traffic as TID is dont care
+                 * */
+                tid = WMM_HIGHEST_PRIORITY - 1;
+#endif
+            }
+            else if (pmpriv->curr_bss_params.bss_descriptor.curr_bandwidth == BW_40MHZ)
+            {
+                if (pmpriv->curr_bss_params.bss_descriptor.phe_cap != NULL)
+                {
+                    tx_control = (RATEID_HE_MCS4_1SS_BW40 << 16) | TXPD_TXRATE_ENABLE;
+                }
+                else if (pmpriv->curr_bss_params.bss_descriptor.pvht_cap != NULL)
+                {
+                    tx_control = (RATEID_VHT_MCS8_1SS_BW40 << 16) | TXPD_TXRATE_ENABLE;
+                }
+#if CONFIG_WMM
+                /* Though TID is not used in case of TCP traffic,
+                 * but making tid as voice traffic is a way to tell firmware to not to use
+                 * MCS rates above 9 for TCP ack packets.
+                 * This introduction is harmless for TCP traffic as TID is dont care
+                 * */
+                tid = WMM_HIGHEST_PRIORITY - 1;
+#endif
+            }
+            else if (pmpriv->curr_bss_params.bss_descriptor.curr_bandwidth == BW_20MHZ)
+            {
+                if (pmpriv->curr_bss_params.bss_descriptor.phe_cap != NULL)
+                {
+                    tx_control = (RATEID_HE_MCS7_1SS_BW20 << 16) | TXPD_TXRATE_ENABLE;
+                }
+                else if (pmpriv->curr_bss_params.bss_descriptor.pvht_cap != NULL)
+                {
+                    tx_control = (RATEID_VHT_MCS7_1SS_BW20 << 16) | TXPD_TXRATE_ENABLE;
+                }
+            }
+        }
+    }
+    else if (interface == MLAN_BSS_TYPE_UAP)
+    {
+        ret = wlan_is_tcp_ack(pmpriv, buffer);
+        if (ret)
+        {
+            if (wm_wifi.bandwidth == BANDWIDTH_80MHZ)
+            {
+                if (mlan_adap->usr_dot_11ax_enable == MTRUE)
+                {
+                    tx_control = (RATEID_HE_MCS9_1SS_BW80 << 16) | TXPD_TXRATE_ENABLE;
+                }
+                else if (mlan_adap->usr_dot_11ac_enable == MTRUE)
+                {
+                    tx_control = (RATEID_VHT_MCS9_1SS_BW80 << 16) | TXPD_TXRATE_ENABLE;
+                }
+            }
+            else if (wm_wifi.bandwidth == BANDWIDTH_40MHZ)
+            {
+                if (mlan_adap->usr_dot_11ax_enable == MTRUE)
+                {
+                    tx_control = (RATEID_HE_MCS8_1SS_BW40 << 16) | TXPD_TXRATE_ENABLE;
+                }
+                else if (mlan_adap->usr_dot_11ac_enable == MTRUE)
+                {
+                    tx_control = (RATEID_VHT_MCS8_1SS_BW40 << 16) | TXPD_TXRATE_ENABLE;
+                }
+            }
+            else if (wm_wifi.bandwidth == BANDWIDTH_20MHZ)
+            {
+                if (mlan_adap->usr_dot_11ax_enable == MTRUE)
+                {
+                    tx_control = (RATEID_HE_MCS7_1SS_BW20 << 16) | TXPD_TXRATE_ENABLE;
+                }
+                else if (mlan_adap->usr_dot_11ac_enable == MTRUE)
+                {
+                    tx_control = (RATEID_VHT_MCS7_1SS_BW20 << 16) | TXPD_TXRATE_ENABLE;
+                }
+            }
+        }
+    }
+#endif /** CONFIG_TCP_ACK_ENH */
+#endif /** CONFIG_11AX */
+#endif
+
+#if CONFIG_WMM
+    /* process packet headers with interface header and TxPD */
+    process_pkt_hdrs((void *)(sd_buffer + sizeof(mlan_linked_list)), len - sizeof(mlan_linked_list), interface, tid,
+                     tx_control);
+
+    /* add buffer to ra lists */
+    if (wlan_wmm_add_buf_txqueue_enh(interface, sd_buffer, len, pkt_prio) != MLAN_STATUS_SUCCESS)
+    {
+        wifi_wmm_drop_no_media(interface);
+        ret = -WM_E_BUSY;
+        goto exit_fn;
+    }
+
+    send_wifi_driver_tx_data_event(interface);
+#else
+    wifi_tx_card_awake_lock();
+#if defined(RW610)
+    wifi_imu_lock();
+#else
+    (void)wifi_sdio_lock();
+#endif
+
+    while (true)
+    {
+        i = wlan_xmit_pkt((t_u8 *)sd_buffer, len, interface, tx_control);
+#if defined(RW610)
+        wifi_imu_unlock();
+#else
+        wifi_sdio_unlock();
+#endif
+        if (i == MLAN_STATUS_SUCCESS)
+        {
+            break;
+        }
+        else
+        {
+            if (i == MLAN_STATUS_FAILURE)
+            {
+                ret = -WM_E_NOMEM;
+                goto exit_fn;
+            }
+            else if (i == MLAN_STATUS_RESOURCE)
+            {
+                if (retry == 0)
+                {
+                    ret = -WM_E_BUSY;
+                    goto exit_fn;
+                }
+                else
+                {
+                    retry--;
+                    /* Allow the other thread to run and hence
+                     * update the write bitmap so that pkt
+                     * can be sent to FW */
+                    OSA_TimeDelay(1);
+#if defined(RW610)
+                    wifi_imu_lock();
+#else
+                    (void)wifi_sdio_lock();
+#endif
+                    continue;
+                }
+            }
+            else
+            { /* Do Nothing */
+            }
+            break;
+        } /* if (i != MLAN_STATUS_SUCCESS) */
+    }     /* while(true) */
+
+    wifi_tx_card_awake_unlock();
+#endif
+
+    if (interface == BSS_TYPE_STA && sta_ampdu_tx_enable
+#if CONFIG_WMM
+        && wifi_sta_ampdu_tx_enable_per_tid_is_allowed(tid)
+#endif
+    )
+    {
+        if (wm_wifi.wrapper_net_is_ip_or_ipv6_callback(buffer))
+        {
+            (void)wrapper_wlan_sta_ampdu_enable(
+#if CONFIG_WMM
+                tid
+#endif
+            );
+        }
+    }
+
+    if (interface == BSS_TYPE_UAP && uap_ampdu_tx_enable
+#if CONFIG_WMM
+        && wifi_uap_ampdu_tx_enable_per_tid_is_allowed(tid)
+#endif
+    )
+    {
+        if (wm_wifi.wrapper_net_is_ip_or_ipv6_callback(buffer))
+        {
+            (void)wrapper_wlan_uap_ampdu_enable((uint8_t *)buffer
+#if CONFIG_WMM
+                                                ,
+                                                tid
+#endif
+            );
+        }
+    }
+
+    ret = WM_SUCCESS;
+
+exit_fn:
+
+#if !CONFIG_WMM
+    if (ret != WM_SUCCESS)
+    {
+        wifi_tx_card_awake_unlock();
+    }
+#endif
+
+    wifi_set_xfer_pending(false);
+    // wakelock_put(WL_ID_LL_OUTPUT);
+
+    return ret;
+}
+
+uint8_t *wifi_get_outbuf(uint32_t *outbuf_len)
+{
+#if defined(RW610)
+    return wifi_get_imu_outbuf(outbuf_len);
+#else
+    return wifi_get_sdio_outbuf(outbuf_len);
+#endif
+}
+
+#if CONFIG_HEAP_DEBUG
+static bool get_os_mem_stat_index(char const *func, t_u32 *index)
+{
+    int i     = 0;
+    t_u32 len = strlen(func);
+
+    len = (len > MAX_FUNC_SYMBOL_LEN - 1) ? (MAX_FUNC_SYMBOL_LEN - 1) : len;
+
+    for (i = 0; i < valid_item_cnt; i++)
+    {
+        if (!strncmp(wifi_os_mem_stat[i].name, func, len))
+        {
+            // Find matched item
+            *index = i;
+            return true;
+        }
+    }
+
+    if (valid_item_cnt >= OS_MEM_STAT_TABLE_SIZE)
+    {
+        (void)PRINTF("os_mem_stat table full\r\n");
+        *index = OS_MEM_STAT_TABLE_SIZE - 1;
+    }
+    else
+    {
+        // Add a new item, increase valid_item_cnt
+        *index = valid_item_cnt;
+        valid_item_cnt++;
+    }
+
+    return false;
+}
+
+static int record_os_mem_item(t_u32 size, char const *func, t_u32 line_num, bool is_alloc)
+{
+    t_u32 index = 0;
+    t_u32 len   = strlen(func);
+
+    len = (len > MAX_FUNC_SYMBOL_LEN - 1) ? (MAX_FUNC_SYMBOL_LEN - 1) : len;
+
+    // If don't get matched item, record stat in new item; else just increase alloc_cnt or free_cnt.
+    if (false == get_os_mem_stat_index(func, &index))
+    {
+        wifi_os_mem_stat[index].line_num = line_num;
+
+        if (true == is_alloc)
+        {
+            wifi_os_mem_stat[index].size = size;
+        }
+
+        memcpy(wifi_os_mem_stat[index].name, func, len);
+    }
+
+    return index;
+}
+
+void record_os_mem_alloc(t_u32 size, char const *func, t_u32 line_num)
+{
+    int index     = 0;
+    bool is_alloc = true;
+
+    OSA_SemaphoreWait((osa_semaphore_handle_t)os_mem_stat_sem, osaWaitForever_c);
+    index = record_os_mem_item(size, func, line_num, is_alloc);
+    wifi_os_mem_stat[index].alloc_cnt++;
+    OSA_SemaphorePost((osa_semaphore_handle_t)os_mem_stat_sem);
+}
+
+void record_os_mem_free(char const *func, t_u32 line_num)
+{
+    int index     = 0;
+    t_u32 size    = 0;
+    bool is_alloc = false;
+
+    OSA_SemaphoreWait((osa_semaphore_handle_t)os_mem_stat_sem, osaWaitForever_c);
+    index = record_os_mem_item(size, func, line_num, is_alloc);
+    wifi_os_mem_stat[index].free_cnt++;
+    OSA_SemaphorePost((osa_semaphore_handle_t)os_mem_stat_sem);
+}
+
+void wifi_show_os_mem_stat()
+{
+    int index = 0;
+
+    (void)PRINTF("os_mem_alloc_stat: \r\n");
+    (void)PRINTF(
+        "Func name                                                         line_num    size        alloc_cnt    "
+        "free_cnt\r\n");
+
+    for (index = 0; index < valid_item_cnt; index++)
+    {
+        (void)PRINTF("%-64s  %-10d  %-10d  %-10d   %-10d \r\n", wifi_os_mem_stat[index].name,
+                     wifi_os_mem_stat[index].line_num, wifi_os_mem_stat[index].size, wifi_os_mem_stat[index].alloc_cnt,
+                     wifi_os_mem_stat[index].free_cnt);
+    }
+}
+#endif
+
+/**
+ * Frame Tx - Injecting Wireless frames from Host
+ *
+ * This function is used to Inject Wireless frames from application
+ * directly.
+ *
+ * \param[in] interface Interface on which frame to be injected.
+ * \param[in] buf Buffer holding 802.11 Wireless frame (Header + Data).
+ * \param[in] len Length of the 802.11 Wireless frame.
+ *
+ * \return WM_SUCCESS on success or error code.
+ *
+ */
+static int raw_low_level_output(const t_u8 interface, const t_u8 *buf, t_u32 len)
+{
+#if (CONFIG_WMM)
+    t_u32 pkt_len            = 0;
+    t_u32 link_point_len     = 0;
+    bypass_outbuf_t *poutbuf = NULL;
+
+    /*Dword align*/
+    pkt_len        = sizeof(TxPD) + INTF_HEADER_LEN - 2;
+    link_point_len = sizeof(mlan_linked_list);
+
+#if !CONFIG_MEM_POOLS
+    poutbuf = OSA_MemoryAllocate(link_point_len + pkt_len + len);
+#else
+    poutbuf = (bypass_outbuf_t *)OSA_MemoryPoolAllocate(buf_1536_MemoryPool);
+#endif
+    if (!poutbuf)
+    {
+        wuap_e("[%s] ERR:Cannot allocate buffer!\r\n", __func__);
+        return -WM_FAIL;
+    }
+
+    (void)memset((t_u8 *)poutbuf, 0, link_point_len + pkt_len);
+
+    (void)raw_process_pkt_hdrs((t_u8 *)poutbuf + link_point_len, pkt_len + len, interface);
+    (void)memcpy((void *)((t_u8 *)poutbuf + link_point_len + pkt_len), (const void *)buf, (size_t)len);
+    /* process packet headers with interface header and TxPD */
+    process_pkt_hdrs((void *)((t_u8 *)poutbuf + link_point_len), pkt_len + len, interface, 0, 0);
+
+    wlan_add_buf_bypass_txq((t_u8 *)poutbuf, interface);
+    send_wifi_driver_bypass_data_event(interface);
+
+    return WM_SUCCESS;
+#else
+    mlan_status i;
+    t_u32 pkt_len       = 0;
+    uint32_t outbuf_len = 0;
+    uint8_t *poutbuf    = wifi_get_outbuf(&outbuf_len);
+
+    pkt_len = sizeof(TxPD) + INTF_HEADER_LEN;
+
+    wifi_tx_card_awake_lock();
+#if defined(RW610)
+    wifi_imu_lock();
+#else
+    (void)wifi_sdio_lock();
+#endif
+
+    (void)memset(poutbuf, 0, pkt_len);
+
+    (void)raw_process_pkt_hdrs((t_u8 *)poutbuf, pkt_len + len - 2U, interface);
+    (void)memcpy((void *)((t_u8 *)poutbuf + pkt_len - 2), (const void *)buf, (size_t)len);
+    i = wlan_xmit_pkt(poutbuf, pkt_len + len - 2U, interface, 0);
+
+#if defined(RW610)
+    wifi_imu_unlock();
+#else
+    wifi_sdio_unlock();
+#endif
+    wifi_tx_card_awake_unlock();
+
+    if (i == MLAN_STATUS_FAILURE)
+    {
+        return (int)-WM_FAIL;
+    }
+
+    wifi_set_xfer_pending(false);
+    return WM_SUCCESS;
+
+#endif
+}
+
+int wifi_inject_frame(const enum wlan_bss_type bss_type, const uint8_t *buff, const size_t len)
+{
+    return raw_low_level_output((t_u8)bss_type, buff, len);
+}
+
+#if CONFIG_WPS2
+int wps_low_level_output(const uint8_t interface, const uint8_t *buf, const uint16_t len)
+{
+    mlan_status i;
+    t_u32 pkt_len;
+    uint32_t outbuf_len = 0;
+
+    uint8_t *outbuf = wifi_get_outbuf(&outbuf_len);
+    if (!outbuf)
+        return (int)-WM_FAIL;
+
+    pkt_len = sizeof(TxPD) + INTF_HEADER_LEN;
+    if ((pkt_len + len) > outbuf_len)
+    {
+        return (int)-WM_FAIL;
+    }
+
+    wifi_tx_card_awake_lock();
+#if defined(RW610)
+    wifi_imu_lock();
+#else
+    wifi_sdio_lock();
+#endif
+
+    (void)memset(outbuf, 0x00, pkt_len);
+
+    (void)memcpy((t_u8 *)outbuf + pkt_len, buf, len);
+
+    i = wlan_xmit_pkt(outbuf, pkt_len + len, interface, 0);
+
+#if defined(RW610)
+    wifi_imu_unlock();
+#else
+    wifi_sdio_unlock();
+#endif
+    wifi_tx_card_awake_unlock();
+
+    if (i == MLAN_STATUS_FAILURE)
+    {
+        return (int)-WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+#endif /* CONFIG_WPS2 */
+
+int wifi_set_country_code(const char *alpha2)
+{
+    mlan_adapter *pmadapter             = (mlan_adapter *)mlan_adap;
+    t_u8 country_code[COUNTRY_CODE_LEN] = {0};
+
+#ifdef OTP_CHANINFO
+    if (pmadapter->otp_region && pmadapter->otp_region->force_reg)
+    {
+        wifi_e("ForceRegionRule is set in the on-chip OTP memory");
+        return -WM_FAIL;
+    }
+#endif
+
+    (void)memcpy(country_code, alpha2, COUNTRY_CODE_LEN - 1);
+
+    pmadapter->region_code = region_string_2_region_code(country_code);
+
+    pmadapter->cfp_code_bg = pmadapter->region_code;
+#if CONFIG_5GHz_SUPPORT
+    pmadapter->cfp_code_a = pmadapter->region_code;
+#endif
+
+    if (wlan_set_regiontable(pmadapter->priv[1], pmadapter->region_code, pmadapter->config_bands))
+    {
+        wifi_e("%s set regiontable fail", __func__);
+        return -WM_FAIL;
+    }
+    (void)memcpy(pmadapter->country_code, country_code, COUNTRY_CODE_LEN);
+
+#if CONFIG_WPA_SUPP
+    if (wm_wifi.supp_if_callbk_fns->chan_list_changed_callbk_fn)
+    {
+        wm_wifi.supp_if_callbk_fns->chan_list_changed_callbk_fn(wm_wifi.if_priv, alpha2);
+    }
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wifi_get_country_code(char *alpha2)
+{
+    (void)memcpy(alpha2, mlan_adap->country_code, COUNTRY_CODE_LEN - 1);
+
+    return WM_SUCCESS;
+}
+
+int wifi_set_country_ie_ignore(uint8_t *ignore)
+{
+    mlan_adap->country_ie_ignore = *ignore;
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPA_SUPP
+int wifi_nxp_scan_res_num(void)
+{
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[0];
+    mlan_adapter *pmadapter = pmpriv->adapter;
+
+    return pmadapter->num_in_scan_table;
+}
+
+int wifi_nxp_scan_res_get2(t_u32 table_idx, nxp_wifi_event_new_scan_result_t *scan_res)
+{
+    mlan_private *pmpriv    = (mlan_private *)mlan_adap->priv[0];
+    mlan_adapter *pmadapter = pmpriv->adapter;
+    struct os_time t;
+    BSSDescriptor_t *bss_new_entry;
+
+    bss_new_entry = &pmadapter->pscan_table[table_idx];
+    memcpy(scan_res->mac_addr, bss_new_entry->mac_address, sizeof(bss_new_entry->mac_address));
+    scan_res->frequency  = channel_to_frequency(bss_new_entry->channel, (bss_new_entry->bss_band == BAND_A ? 1 : 0));
+    scan_res->chan_width = bss_new_entry->curr_bandwidth;
+    scan_res->beacon_interval = bss_new_entry->beacon_period;
+    memcpy(&scan_res->capability, &bss_new_entry->cap_info, sizeof(unsigned short));
+    memcpy(&scan_res->ies_tsf, bss_new_entry->time_stamp, sizeof(bss_new_entry->time_stamp));
+    os_get_time(&t);
+    scan_res->seen_ms_ago = t.sec * 1000 - bss_new_entry->scan_result_tsf / 1000000 * 1000;
+    if (bss_new_entry->ies_len > 0)
+    {
+        scan_res->ies.ie     = bss_new_entry->ies;
+        bss_new_entry->ies   = NULL;
+        scan_res->ies.ie_len = (t_u16)bss_new_entry->ies_len;
+    }
+    else
+    {
+        scan_res->ies.ie_len = (t_u16)0U;
+    }
+
+    scan_res->rssi = (t_u8) - (bss_new_entry->rssi);
+#if CONFIG_SCAN_CHANNEL_GAP
+    scan_res->noise = bss_new_entry->chan_noise;
+#endif
+
+    if ((pmpriv->media_connected == MTRUE) &&
+        (memcmp(bss_new_entry->mac_address, (t_u8 *)&pmpriv->curr_bss_params.bss_descriptor.mac_address,
+                MLAN_MAC_ADDR_LENGTH) == 0U))
+
+    {
+        scan_res->status = 1;
+    }
+    return WM_SUCCESS;
+}
+
+void wifi_nxp_reset_scan_flag()
+{
+    mlan_adap->wpa_supp_scan_triggered = MFALSE;
+}
+
+int wifi_nxp_survey_res_get(void)
+{
+#if CONFIG_SCAN_CHANNEL_GAP
+    mlan_private *pmpriv          = (mlan_private *)mlan_adap->priv[0];
+    ChanStatistics_t *pchan_stats = NULL;
+    mlan_scan_resp scan_resp;
+    t_u32 idx;
+    nxp_wifi_event_new_survey_result_t survey_res;
+    bool more_res = true;
+#endif
+
+    ENTER();
+    wifi_d("dump_survey");
+
+#if CONFIG_SCAN_CHANNEL_GAP
+    memset(&scan_resp, 0, sizeof(scan_resp));
+    wifi_get_scan_table(pmpriv, &scan_resp);
+
+    pchan_stats = (ChanStatistics_t *)scan_resp.pchan_stats;
+
+    for (idx = 0; idx < scan_resp.num_in_chan_stats; idx++)
+    {
+        if (pchan_stats[idx].chan_num == 0)
+        {
+            if (wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn)
+            {
+#if CONFIG_HOSTAPD
+                if (wm_wifi.hostapd_op)
+                {
+                    wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn(wm_wifi.hapd_if_priv, NULL, 0, false);
+                }
+                else
+#endif
+                {
+                    wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn(wm_wifi.if_priv, NULL, 0, false);
+                }
+
+                OSA_TimeDelay(50);
+            }
+
+            break;
+        }
+
+        memset(&survey_res, 0x00, sizeof(nxp_wifi_event_new_survey_result_t));
+
+        survey_res.freq         = channel_to_frequency(pchan_stats[idx].chan_num, pchan_stats[idx].bandcfg.chanBand);
+        survey_res.nf           = pchan_stats[idx].noise;
+        survey_res.channel_time = pchan_stats[idx].cca_scan_duration;
+        survey_res.channel_time_busy = pchan_stats[idx].cca_busy_duration;
+
+        if (pchan_stats[idx + 1].chan_num == 0)
+        {
+            more_res = false;
+        }
+        if (wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn)
+        {
+#if CONFIG_HOSTAPD
+            if (wm_wifi.hostapd_op)
+            {
+                wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn(wm_wifi.hapd_if_priv, &survey_res,
+                                                                 sizeof(nxp_wifi_event_new_survey_result_t), more_res);
+            }
+            else
+#endif
+            {
+                wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn(wm_wifi.if_priv, &survey_res,
+                                                                 sizeof(nxp_wifi_event_new_survey_result_t), more_res);
+            }
+
+            OSA_TimeDelay(50);
+        }
+    }
+#else
+    if (wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn)
+    {
+#if CONFIG_HOSTAPD
+        if (wm_wifi.hostapd_op)
+        {
+            wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn(wm_wifi.hapd_if_priv, NULL, 0, false);
+        }
+        else
+#endif
+        {
+            wm_wifi.supp_if_callbk_fns->survey_res_callbk_fn(wm_wifi.if_priv, NULL, 0, false);
+        }
+
+        OSA_TimeDelay(50);
+    }
+#endif
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPA_SUPP_WPS
+bool wifi_nxp_wps_session_enable(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    return pmpriv->wps.session_enable;
+}
+#endif
+
+
+static int supp_low_level_output(const t_u8 interface, const t_u8 *buf, t_u32 len)
+{
+#if (CONFIG_WMM)
+    t_u32 pkt_len            = 0;
+    t_u32 link_point_len     = 0;
+    bypass_outbuf_t *poutbuf = NULL;
+
+    /*Dword align*/
+    pkt_len        = sizeof(TxPD) + INTF_HEADER_LEN;
+    link_point_len = sizeof(mlan_linked_list);
+
+#if !CONFIG_MEM_POOLS
+    poutbuf = OSA_MemoryAllocate(link_point_len + pkt_len + len);
+#else
+    poutbuf = (bypass_outbuf_t *)OSA_MemoryPoolAllocate(buf_1536_MemoryPool);
+#endif
+    if (!poutbuf)
+    {
+        wuap_e("[%s] ERR:Cannot allocate buffer!\r\n", __func__);
+        return -WM_FAIL;
+    }
+
+    (void)memset((t_u8 *)poutbuf, 0, link_point_len + pkt_len);
+
+    (void)memcpy((void *)((t_u8 *)poutbuf + link_point_len + pkt_len), (const void *)buf, (size_t)len);
+    /* process packet headers with interface header and TxPD */
+    process_pkt_hdrs((void *)((t_u8 *)poutbuf + link_point_len), pkt_len + len, interface, 0, 0);
+
+    wlan_add_buf_bypass_txq((t_u8 *)poutbuf, interface);
+    send_wifi_driver_bypass_data_event(interface);
+
+    return WM_SUCCESS;
+#else
+    mlan_status i;
+    uint32_t pkt_len, outbuf_len;
+
+    uint8_t *outbuf = wifi_get_outbuf(&outbuf_len);
+
+    if (!outbuf)
+    {
+        return (int)-WM_FAIL;
+    }
+
+    pkt_len = sizeof(TxPD) + INTF_HEADER_LEN;
+
+    if ((len + pkt_len) > outbuf_len)
+    {
+        return (int)-WM_FAIL;
+    }
+
+    wifi_tx_card_awake_lock();
+#if defined(RW610)
+    wifi_imu_lock();
+#else
+    wifi_sdio_lock();
+#endif
+
+    (void)memset(outbuf, 0x00, pkt_len);
+
+    (void)memcpy((t_u8 *)outbuf + pkt_len, buf, len);
+
+    i = wlan_xmit_pkt(outbuf, pkt_len + len, interface, 0);
+
+#if defined(RW610)
+    wifi_imu_unlock();
+#else
+    wifi_sdio_unlock();
+#endif
+    wifi_tx_card_awake_unlock();
+
+    if (i == MLAN_STATUS_FAILURE)
+    {
+        return (int)-WM_FAIL;
+    }
+
+    wifi_set_xfer_pending(false);
+    return (int)WM_SUCCESS;
+
+#endif
+}
+
+int wifi_supp_inject_frame(const unsigned int bss_type, const uint8_t *buff, const size_t len)
+{
+    return supp_low_level_output((t_u8)bss_type, buff, len);
+}
+
+/**
+ *  Alpha2 may has only 2 octets.
+ *  Need to avoid accessing the third octet.
+ *  If On-Chip OTP memory sets ForceRegion Rule, set country may return fail.
+ *  Ignore it to not let it block AP setup.
+ */
+int wifi_nxp_set_country(unsigned int bss_type, const char *alpha2)
+{
+    (void)wifi_set_country_code(alpha2);
+    return WM_SUCCESS;
+}
+
+/**
+ *  Alpha2 may has only 2 octets.
+ *  Need to avoid accessing the third octet.
+ */
+int wifi_nxp_get_country(unsigned int bss_type, char *alpha2)
+{
+    return wifi_get_country_code(alpha2);
+}
+
+int wifi_nxp_get_signal(unsigned int bss_type, nxp_wifi_signal_info_t *signal_params)
+{
+    wifi_rssi_info_t rssi_info;
+
+    (void)wifi_send_rssi_info_cmd(&rssi_info);
+
+    signal_params->current_signal    = rssi_info.bcn_rssi_last;
+    signal_params->avg_signal        = rssi_info.data_rssi_avg;
+    signal_params->avg_beacon_signal = rssi_info.bcn_rssi_avg;
+    signal_params->current_noise     = rssi_info.bcn_nf_last;
+
+    return WM_SUCCESS;
+}
+
+int wifi_nxp_send_mlme(unsigned int bss_type, int channel, unsigned int wait_time, const t_u8 *data, size_t data_len)
+{
+    mlan_private *pmpriv              = (mlan_private *)mlan_adap->priv[bss_type];
+    wlan_mgmt_pkt *pmgmt_pkt_hdr      = MNULL;
+    wlan_802_11_header *pieee_pkt_hdr = MNULL;
+    t_u8 buf[1580];
+
+    // dump_hex(data, data_len);
+    memset(buf, 0x00, sizeof(buf));
+
+    if ((bss_type == BSS_TYPE_STA) && (pmpriv->media_connected == MFALSE))
+    {
+        if (wait_time == 0)
+        {
+            wait_time = 1000;
+        }
+        wifi_remain_on_channel(true, channel, wait_time);
+    }
+
+    pmgmt_pkt_hdr = (wlan_mgmt_pkt *)&buf[0];
+
+    pmgmt_pkt_hdr->frm_len = data_len + MLAN_MAC_ADDR_LENGTH;
+
+    pieee_pkt_hdr = (wlan_802_11_header *)(void *)&pmgmt_pkt_hdr->wlan_header;
+
+    memcpy(pieee_pkt_hdr, data, sizeof(wlan_802_11_header) - MLAN_MAC_ADDR_LENGTH);
+    // coverity[overrun-local:SUPPRESS]
+    memcpy(pieee_pkt_hdr + 1, data + sizeof(wlan_802_11_header) - MLAN_MAC_ADDR_LENGTH,
+           data_len - (sizeof(wlan_802_11_header) - MLAN_MAC_ADDR_LENGTH));
+
+    data_len = pmgmt_pkt_hdr->frm_len + 2U;
+
+    return wifi_inject_frame((enum wlan_bss_type)bss_type, buf, data_len);
+}
+#else
+int wifi_supp_inject_frame(const unsigned int bss_type, const uint8_t *buff, const size_t len)
+{
+    (void)bss_type;
+    (void)buff;
+    (void)len;
+
+    return WM_SUCCESS;
+}
+#endif
+
+bool wifi_is_remain_on_channel(void)
+{
+    return (mlan_adap->remain_on_channel ? true : false);
+}
+
+int wifi_remain_on_channel(const bool status, const uint8_t channel, const uint32_t duration)
+{
+    wifi_remain_on_channel_t roc;
+
+    (void)memset(&roc, 0x00, sizeof(wifi_remain_on_channel_t));
+
+    roc.remove = (uint16_t)!status;
+
+    roc.channel = channel;
+
+    roc.remain_period = duration;
+
+#if CONFIG_5GHz_SUPPORT
+    if (channel > 14)
+    {
+        roc.bandcfg |= 1;
+    }
+#endif
+#if CONFIG_WMM
+    if (true == status)
+    {
+        /* Block tx data before send remain on channel,
+         * then get txbuf_sem, keep the next auth frame can get txbuf
+         */
+        wifi_set_tx_status(WIFI_DATA_BLOCK);
+
+        if (wifi_txbuf_available() == MFALSE)
+        {
+            mlan_adap->wait_txbuf = true;
+            OSA_SemaphoreWait((osa_semaphore_handle_t)txbuf_sem, osaWaitForever_c);
+            mlan_adap->wait_txbuf = false;
+        }
+    }
+    else if (false == status)
+    {
+        /* Restore tx when cancel remain on channel*/
+        wifi_set_tx_status(WIFI_DATA_RUNNING);
+
+        send_wifi_driver_tx_data_event(MLAN_BSS_TYPE_STA);
+        send_wifi_driver_tx_data_event(MLAN_BSS_TYPE_UAP);
+    }
+#endif
+
+    return wifi_send_remain_on_channel_cmd(MLAN_BSS_TYPE_STA, &roc);
+}
+
+#ifdef RW610
+int wifi_imu_get_task_lock(void)
+{
+    return imu_get_task_lock();
+}
+
+int wifi_imu_put_task_lock(void)
+{
+    return imu_put_task_lock();
+}
+#endif
+
+#if CONFIG_CSI
+
+/* csi data recv user callback */
+int (*csi_data_recv)(void *buffer, size_t len) = NULL;
+
+int register_csi_user_callback(int (*csi_data_recv_callback)(void *buffer, size_t len))
+{
+    csi_data_recv = csi_data_recv_callback;
+
+    return WM_SUCCESS;
+}
+
+int unregister_csi_user_callback(void)
+{
+    csi_data_recv = NULL;
+
+    return WM_SUCCESS;
+}
+
+void process_csi_info_callback(void *data, size_t len)
+{
+    if (csi_data_recv != NULL)
+    {
+        csi_data_recv(data, len);
+    }
+}
+
+void csi_local_buff_init()
+{
+    csi_event_cnt      = 0;
+    csi_event_data_len = 0;
+
+    csi_buff_stat.write_index    = 0;
+    csi_buff_stat.read_index     = 0;
+    csi_buff_stat.valid_data_cnt = 0;
+
+    memset(csi_local_buff, 0x00, sizeof(csi_local_buff));
+}
+
+void csi_save_data_to_local_buff(void *data)
+{
+    OSA_SemaphoreWait((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem, osaWaitForever_c);
+
+    if (csi_buff_stat.valid_data_cnt >= MAX_CSI_LOCAL_BUF)
+    {
+        OSA_SemaphorePost((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem);
+        wifi_w("******csi_local_buff is full******\r\n");
+        return;
+    }
+
+    memcpy(&csi_local_buff[csi_buff_stat.write_index][0], (t_u8 *)data, CSI_LOCAL_BUF_ENTRY_SIZE);
+
+    csi_buff_stat.valid_data_cnt++;
+
+    csi_buff_stat.write_index = (csi_buff_stat.write_index + 1) % MAX_CSI_LOCAL_BUF;
+
+    OSA_SemaphorePost((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem);
+}
+
+void csi_deliver_data_to_user()
+{
+    int i               = 0;
+    t_u16 save_data_len = 0;
+
+    OSA_SemaphoreWait((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem, osaWaitForever_c);
+
+    for (i = 0; (i < MAX_CSI_LOCAL_BUF) && (csi_buff_stat.valid_data_cnt > 0); i++)
+    {
+        pcsi_record_ds csi_record = (pcsi_record_ds)(&csi_local_buff[csi_buff_stat.read_index][0]);
+        save_data_len             = (csi_record->Len & 0x1fff) * 4;
+        save_data_len = (save_data_len >= CSI_LOCAL_BUF_ENTRY_SIZE) ? CSI_LOCAL_BUF_ENTRY_SIZE : save_data_len;
+
+        process_csi_info_callback((t_u8 *)csi_record, save_data_len);
+
+        csi_buff_stat.valid_data_cnt--;
+
+        csi_buff_stat.read_index = (csi_buff_stat.read_index + 1) % MAX_CSI_LOCAL_BUF;
+    }
+
+    OSA_SemaphorePost((osa_semaphore_handle_t)csi_buff_stat.csi_data_sem);
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi_common.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi_common.h
new file mode 100644
index 0000000000..d7cb21733a
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi_common.h
@@ -0,0 +1,198 @@
+/** @file  wifi_common.h
+ *
+ *  @brief Header file for wifi common functions
+ *
+ *  Copyright 2008-2021 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef _WIFI_COMMON_H
+#define _WIFI_COMMON_H
+#include <wifi.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <ctype.h>
+
+#define wfd_e(...) wmlog_e("p2p", ##__VA_ARGS__)
+#define wfd_w(...) wmlog_w("p2p", ##__VA_ARGS__)
+
+#define wfd_d(...)
+
+/** Success */
+#define SUCCESS 1
+/** Failure */
+#define FAILURE 0
+/** MAC BROADCAST */
+#define WIFIDIRECT_RET_MAC_BROADCAST 0x1FF
+/** MAC MULTICAST */
+#define WIFIDIRECT_RET_MAC_MULTICAST 0x1FE
+
+/* fixme: remove this after mlan integration complete
+ */
+/* Definition of firmware host command */
+/** HostCmd_DS_GEN */
+typedef PACK_START struct
+{
+    /** Command */
+    t_u16 command;
+    /** Size */
+    t_u16 size;
+    /** Sequence number */
+    t_u16 seq_num;
+    /** Result */
+    t_u16 result;
+} PACK_END HostCmd_DS_GEN;
+
+/**
+ *  @brief  Detects duplicates channel in array of strings
+ *
+ *  @param  argc    Number of elements
+ *  @param  argv    Array of strings
+ *  @return UAP_FAILURE or UAP_SUCCESS
+ */
+static inline int has_dup_channel(int argc, char *argv[])
+{
+    int i, j;
+    /* Check for duplicate */
+    for (i = 0; i < (argc - 1); i++)
+    {
+        for (j = i + 1; j < argc; j++)
+        {
+            if (atoi(argv[i]) == atoi(argv[j]))
+                return FAILURE;
+        }
+    }
+    return SUCCESS;
+}
+
+/**
+ *  @brief Converts colon separated MAC address to hex value
+ *
+ *  @param mac      A pointer to the colon separated MAC string
+ *  @param raw      A pointer to the hex data buffer
+ *  @return         SUCCESS or FAILURE
+ *                  WIFIDIRECT_RET_MAC_BROADCAST  - if broadcast mac
+ *                  WIFIDIRECT_RET_MAC_MULTICAST - if multicast mac
+ */
+static int mac2raw(char *mac, t_u8 *raw)
+{
+    unsigned int temp_raw[ETH_ALEN];
+    int num_tokens = 0;
+    int i;
+    if (strlen(mac) != ((2 * ETH_ALEN) + (ETH_ALEN - 1)))
+        return FAILURE;
+    num_tokens = sscanf(mac, "%2x:%2x:%2x:%2x:%2x:%2x", temp_raw + 0, temp_raw + 1, temp_raw + 2, temp_raw + 3,
+                        temp_raw + 4, temp_raw + 5);
+    if (num_tokens != ETH_ALEN)
+        return FAILURE;
+
+    for (i = 0; i < num_tokens; i++)
+        raw[i] = (t_u8)temp_raw[i];
+
+    if (memcmp(raw, "\xff\xff\xff\xff\xff\xff", ETH_ALEN) == 0)
+        return WIFIDIRECT_RET_MAC_BROADCAST;
+    else if (raw[0] & 0x01)
+        return WIFIDIRECT_RET_MAC_MULTICAST;
+    return SUCCESS;
+}
+
+/**
+ *  @brief Parses a command line
+ *
+ *  @param line     The line to parse
+ *  @param args     Pointer to the argument buffer to be filled in
+ *  @return         Number of arguments in the line or EOF
+ */
+static int parse_line(char *line, char *args[])
+{
+    int arg_num  = 0;
+    int is_start = 0;
+    int is_quote = 0;
+    int length   = 0;
+    int i        = 0;
+
+    arg_num = 0;
+    length  = strlen(line);
+    /* Process line */
+
+    /* Find number of arguments */
+    is_start = 0;
+    is_quote = 0;
+    for (i = 0; i < length; i++)
+    {
+        /* Ignore leading spaces */
+        if (is_start == 0)
+        {
+            if (line[i] == ' ')
+            {
+                continue;
+            }
+            else if (line[i] == '\t')
+            {
+                continue;
+            }
+            else if (line[i] == '\n')
+            {
+                break;
+            }
+            else
+            {
+                is_start      = 1;
+                args[arg_num] = &line[i];
+                arg_num++;
+            }
+        }
+        if (is_start == 1)
+        {
+            /* Ignore comments */
+            if (line[i] == '#')
+            {
+                if (is_quote == 0)
+                {
+                    line[i] = '\0';
+                    arg_num--;
+                }
+                break;
+            }
+            /* Separate by '=' */
+            if (line[i] == '=')
+            {
+                line[i]  = '\0';
+                is_start = 0;
+                continue;
+            }
+            /* Separate by ',' */
+            if (line[i] == ',')
+            {
+                line[i]  = '\0';
+                is_start = 0;
+                continue;
+            }
+            /* Change ',' to ' ', but not inside quotes */
+            if ((line[i] == ',') && (is_quote == 0))
+            {
+                line[i] = ' ';
+                continue;
+            }
+        }
+        /* Remove newlines */
+        if (line[i] == '\n')
+            line[i] = '\0';
+        /* Check for quotes */
+        if (line[i] == '"')
+        {
+            is_quote = (is_quote == 1) ? 0 : 1;
+            continue;
+        }
+        if (((line[i] == ' ') || (line[i] == '\t')) && (is_quote == 0))
+        {
+            line[i]  = '\0';
+            is_start = 0;
+            continue;
+        }
+    }
+    return arg_num;
+}
+
+#endif /* _WIFI_COMMON_H */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi_pwrmgr.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi_pwrmgr.c
new file mode 100644
index 0000000000..de64f59148
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wifi_pwrmgr.c
@@ -0,0 +1,648 @@
+/** @file wifi_pwrmgr.c
+ *
+ *  @brief This file provides all power management code for WIFI.
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mlan_api.h>
+
+#include <wmerrno.h>
+#include <osa.h>
+#include <wifi.h>
+#include <wifi_events.h>
+
+#include <wmlog.h>
+#if defined(RW610)
+#include "wifi-imu.h"
+#else
+#include "wifi-sdio.h"
+#endif
+#include "wifi-internal.h"
+
+#define pwr_e(...) wmlog_e("pwr", ##__VA_ARGS__)
+#define pwr_w(...) wmlog_w("pwr", ##__VA_ARGS__)
+
+#define pwr_d(...)
+
+#define MAX_LISTEN_INTERVAL_IN_BCON     49
+#define MIN_LISTEN_INTERVAL_IN_TU       50
+#define MAX_LISTEN_INTERVAL_IN_TU       65000
+#define CLOSEST_DTIM_TO_LISTEN_INTERVAL 65534
+
+static bool ieeeps_enabled;
+static bool deepsleepps_enabled;
+
+void wifi_set_ps_cfg(t_u16 multiple_dtims,
+                     t_u16 bcn_miss_timeout,
+                     t_u16 local_listen_interval,
+                     t_u16 adhoc_wake_period,
+                     t_u16 mode,
+                     t_u16 delay_to_ps)
+{
+    pmlan_adapter pmadapter          = ((mlan_private *)mlan_adap->priv[0])->adapter;
+    pmadapter->bcn_miss_time_out     = bcn_miss_timeout;
+    pmadapter->multiple_dtim         = multiple_dtims;
+    pmadapter->local_listen_interval = local_listen_interval;
+    pmadapter->delay_to_ps           = delay_to_ps;
+    pmadapter->enhanced_ps_mode      = mode;
+    pmadapter->adhoc_awake_period    = adhoc_wake_period;
+}
+
+void wifi_configure_null_pkt_interval(unsigned int null_pkt_interval)
+{
+    pmlan_adapter pmadapter      = ((mlan_private *)mlan_adap->priv[0])->adapter;
+    pmadapter->null_pkt_interval = (t_u16)null_pkt_interval;
+}
+
+void wifi_configure_listen_interval(int listen_interval)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[0];
+
+    pmpriv->listen_interval = (t_u16)listen_interval;
+
+    pmlan_adapter pmadapter = ((mlan_private *)mlan_adap->priv[0])->adapter;
+    wifi_set_ps_cfg(CLOSEST_DTIM_TO_LISTEN_INTERVAL, DEFAULT_BCN_MISS_TIMEOUT, 0, 0, PS_MODE_AUTO, DELAY_TO_PS_DEFAULT);
+    pmadapter->local_listen_interval = (t_u16)listen_interval;
+}
+
+void wifi_configure_delay_to_ps(unsigned int timeout_ms)
+{
+    pmlan_adapter pmadapter = ((mlan_private *)mlan_adap->priv[0])->adapter;
+
+    pmadapter->delay_to_ps = (t_u16)timeout_ms;
+}
+
+unsigned short wifi_get_listen_interval()
+{
+    pmlan_adapter pmadapter = ((mlan_private *)mlan_adap->priv[0])->adapter;
+
+    return (unsigned short)pmadapter->local_listen_interval;
+}
+
+unsigned int wifi_get_delay_to_ps()
+{
+    pmlan_adapter pmadapter = ((mlan_private *)mlan_adap->priv[0])->adapter;
+
+    return (unsigned int)pmadapter->delay_to_ps;
+}
+
+#if CONFIG_HOST_SLEEP
+int wifi_send_hs_cfg_cmd(mlan_bss_type interface, t_u32 ipv4_addr, t_u16 action, t_u32 conditions)
+{
+    pmlan_adapter pmadapter     = ((mlan_private *)mlan_adap->priv[0])->adapter;
+    arpfilter_header *arpfilter = NULL;
+    filter_entry *entry         = NULL;
+    void *pdata_buf             = NULL;
+    hs_config_param hs_cfg_obj;
+    t_u8 *tlv                                      = NULL;
+    MrvlIEtypes_MgmtFrameFilter_t *mgmt_filter_tlv = NULL;
+
+    (void)wifi_get_command_lock();
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    (void)memset(&hs_cfg_obj, 0x00, sizeof(hs_config_param));
+
+    cmd->seq_num = (t_u16)(HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, (t_u32)(interface)));
+    if (action == (t_u16)HS_CONFIGURE)
+    {
+        hs_cfg_obj.conditions = conditions;
+        hs_cfg_obj.gap        = 0xc8;
+#ifdef RW610
+        hs_cfg_obj.gpio = 0xff;
+#else
+        hs_cfg_obj.gpio = HOST_WAKEUP_GPIO_PIN;
+#endif
+        pdata_buf = &hs_cfg_obj;
+
+        /* wake conditions for broadcast is
+         * enabled when bit 0 is set.
+         * The code below sets the correct bit which
+         * firmware will use to give host wakeup
+         */
+        if ((conditions != (t_u32)(HOST_SLEEP_CFG_CANCEL)) &&
+            ((conditions & (t_u32)(WIFI_WAKE_ON_ARP_BROADCAST)) != 0U))
+        {
+            hs_cfg_obj.conditions |= (t_u32)(WIFI_WAKE_ON_ALL_BROADCAST);
+            hs_cfg_obj.conditions &= ~((t_u32)(WIFI_WAKE_ON_ARP_BROADCAST));
+        }
+    }
+
+    mlan_status status = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_HS_CFG_ENH,
+                                                  HostCmd_ACT_GEN_SET, 0, NULL, pdata_buf, cmd);
+    /* Construct the ARP filter TLV */
+    arpfilter       = (arpfilter_header *)((uint32_t)cmd + cmd->size);
+    arpfilter->type = TLV_TYPE_ARP_FILTER;
+    arpfilter->len  = 0;
+
+    if ((ipv4_addr != 0U) && (action == (t_u16)HS_CONFIGURE) &&
+        (conditions &
+         (WIFI_WAKE_ON_MULTICAST | WIFI_WAKE_ON_ALL_BROADCAST | WIFI_WAKE_ON_UNICAST | WIFI_WAKE_ON_ARP_BROADCAST)))
+    {
+        entry = (filter_entry *)((uint32_t)arpfilter + sizeof(arpfilter_header));
+        if ((conditions & (t_u32)(WIFI_WAKE_ON_MULTICAST)) != 0U)
+        {
+            entry->addr_type = ADDR_TYPE_MULTICAST;
+            entry->eth_type  = ETHER_TYPE_ANY;
+            entry->ipv4_addr = IPV4_ADDR_ANY;
+            entry++;
+            arpfilter->len += sizeof(filter_entry);
+        }
+
+        if ((conditions & (t_u32)(WIFI_WAKE_ON_ALL_BROADCAST | WIFI_WAKE_ON_ARP_BROADCAST)) != 0U)
+        {
+            entry->addr_type = ADDR_TYPE_BROADCAST;
+            if ((conditions & (t_u32)(WIFI_WAKE_ON_ALL_BROADCAST)) != 0U)
+            {
+                entry->eth_type  = ETHER_TYPE_ANY;
+                entry->ipv4_addr = IPV4_ADDR_ANY;
+            }
+            else
+            {
+                entry->eth_type  = ETHER_TYPE_ARP;
+                entry->ipv4_addr = ipv4_addr;
+            }
+            entry++;
+            arpfilter->len += sizeof(filter_entry);
+        }
+
+        if ((conditions & (t_u32)(WIFI_WAKE_ON_UNICAST)) != 0U)
+        {
+            entry->addr_type = ADDR_TYPE_UNICAST;
+            entry->eth_type  = ETHER_TYPE_ANY;
+            entry->ipv4_addr = IPV4_ADDR_ANY;
+            arpfilter->len += sizeof(filter_entry);
+        }
+        cmd->size = (t_u16)(cmd->size + sizeof(arpfilter_header) + arpfilter->len);
+    }
+    else if (action == (t_u16)HS_ACTIVATE)
+    {
+        arpfilter->len = 0;
+        cmd->size -= (t_u16)sizeof(t_u32);
+    }
+    else
+    {
+        /** Do nothing */
+    }
+    if (action == (t_u16)HS_CONFIGURE)
+    {
+        tlv = (t_u8 *)((uint32_t)cmd + cmd->size);
+
+        if (pmadapter->mgmt_filter[0].type)
+        {
+            int i = 0;
+            mgmt_frame_filter mgmt_filter[MAX_MGMT_FRAME_FILTER];
+            (void)memset(mgmt_filter, 0, MAX_MGMT_FRAME_FILTER * sizeof(mgmt_frame_filter));
+            mgmt_filter_tlv              = (MrvlIEtypes_MgmtFrameFilter_t *)tlv;
+            mgmt_filter_tlv->header.type = wlan_cpu_to_le16(TLV_TYPE_MGMT_FRAME_WAKEUP);
+            tlv += sizeof(MrvlIEtypesHeader_t);
+            while (i < MAX_MGMT_FRAME_FILTER && pmadapter->mgmt_filter[i].type)
+            {
+                mgmt_filter[i].action     = (t_u8)pmadapter->mgmt_filter[i].action;
+                mgmt_filter[i].type       = (t_u8)pmadapter->mgmt_filter[i].type;
+                mgmt_filter[i].frame_mask = wlan_cpu_to_le32(pmadapter->mgmt_filter[i].frame_mask);
+                i++;
+            }
+            (void)memcpy((t_u8 *)mgmt_filter_tlv->filter, (t_u8 *)mgmt_filter, i * sizeof(mgmt_frame_filter));
+            tlv += i * sizeof(mgmt_frame_filter);
+            mgmt_filter_tlv->header.len = wlan_cpu_to_le16(i * sizeof(mgmt_frame_filter));
+            cmd->size += i * sizeof(mgmt_frame_filter) + sizeof(MrvlIEtypesHeader_t);
+        }
+    }
+
+    (void)wifi_wait_for_cmdresp(NULL);
+    return (int)status;
+}
+
+int wifi_cancel_host_sleep(mlan_bss_type interface)
+{
+    void *pdata_buf = NULL;
+    hs_config_param hs_cfg_obj;
+
+    wifi_get_command_lock();
+
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    (void)memset(&hs_cfg_obj, 0x00, sizeof(hs_config_param));
+
+    cmd->seq_num          = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, interface);
+    hs_cfg_obj.conditions = HOST_SLEEP_CFG_CANCEL;
+    pdata_buf             = &hs_cfg_obj;
+    mlan_status status    = wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_802_11_HS_CFG_ENH,
+                                                     HostCmd_ACT_GEN_SET, 0, NULL, pdata_buf, cmd);
+    wifi_wait_for_cmdresp(NULL);
+    return status;
+}
+#endif
+
+static int wifi_send_power_save_command(ENH_PS_MODES action, t_u16 ps_bitmap, mlan_bss_type interface, void *pdata_buf)
+{
+    mlan_status status;
+    mlan_ds_auto_ds ds_param;
+
+    (void)wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, (t_u8)(interface));
+    if (ps_bitmap == BITMAP_AUTO_DS)
+    {
+        ds_param.idletime = (*(t_u16 *)pdata_buf);
+        pdata_buf         = &ds_param;
+    }
+
+    cmd->result = 0x0;
+    status      = wlan_cmd_enh_power_mode((mlan_private *)mlan_adap->priv[0], cmd, action, (t_u16)ps_bitmap, pdata_buf);
+
+    (void)wifi_wait_for_cmdresp(NULL);
+    return (int)status;
+}
+
+int wifi_enter_ieee_power_save(void)
+{
+    return wifi_send_power_save_command(EN_AUTO_PS, BITMAP_STA_PS, MLAN_BSS_TYPE_STA, NULL);
+}
+
+int wifi_exit_ieee_power_save(void)
+{
+    return wifi_send_power_save_command(DIS_AUTO_PS, BITMAP_STA_PS, MLAN_BSS_TYPE_STA, NULL);
+}
+
+#if (CONFIG_WNM_PS)
+int wifi_enter_wnm_power_save(t_u16 wnm_sleep_time)
+{
+    ((mlan_private *)mlan_adap->priv[0])->wnm_set = true;
+    t_u16 interval                                = wnm_sleep_time;
+    return wifi_send_power_save_command(EN_WNM_PS, BITMAP_STA_PS, MLAN_BSS_TYPE_STA, &interval);
+}
+
+int wifi_exit_wnm_power_save(void)
+{
+    return wifi_send_power_save_command(DIS_WNM_PS, BITMAP_STA_PS, MLAN_BSS_TYPE_STA, NULL);
+}
+#endif
+
+int wifi_enter_deepsleep_power_save(void)
+{
+    t_u16 idletime = 0;
+    /* Set default idle time for deep sleep mode.
+     * If not set, fw will use 10ms as default value and this will
+     * cause small time gap between ps_wakeup and ps_sleep events
+     */
+    idletime = DEEP_SLEEP_IDLE_TIME;
+    return wifi_send_power_save_command(EN_AUTO_PS, BITMAP_AUTO_DS, MLAN_BSS_TYPE_STA, &idletime);
+}
+
+int wifi_exit_deepsleep_power_save(void)
+{
+    t_u16 idletime = 0;
+    return wifi_send_power_save_command(DIS_AUTO_PS, BITMAP_AUTO_DS, MLAN_BSS_TYPE_STA, &idletime);
+}
+
+int wifi_set_power_save_mode(void)
+{
+    t_u32 mode = BLOCK_CMD_IN_PRE_ASLEEP;
+
+    return wifi_send_power_save_command(EXT_PS_PARAM, 0U, MLAN_BSS_TYPE_STA, &mode);
+}
+
+int wifi_uap_ps_inactivity_sleep_enter(mlan_bss_type type,
+                                       unsigned int ctrl_bitmap,
+                                       unsigned int min_sleep,
+                                       unsigned int max_sleep,
+                                       unsigned int inactivity_to,
+                                       unsigned int min_awake,
+                                       unsigned int max_awake)
+{
+    mlan_ds_ps_mgmt data_buff;
+
+    (void)memset(&data_buff, 0x00, sizeof(mlan_ds_ps_mgmt));
+
+    data_buff.sleep_param.ctrl_bitmap   = ctrl_bitmap;
+    data_buff.sleep_param.min_sleep     = min_sleep;
+    data_buff.sleep_param.max_sleep     = max_sleep;
+    data_buff.inact_param.inactivity_to = inactivity_to;
+    data_buff.inact_param.min_awake     = min_awake;
+    data_buff.inact_param.max_awake     = max_awake;
+    data_buff.ps_mode                   = PS_MODE_INACTIVITY;
+    data_buff.flags                     = PS_FLAG_INACT_SLEEP_PARAM | PS_FLAG_SLEEP_PARAM;
+
+    return wifi_send_power_save_command(EN_AUTO_PS, BITMAP_UAP_INACT_PS, type, &data_buff);
+}
+
+int wifi_uap_ps_inactivity_sleep_exit(mlan_bss_type type)
+{
+    return wifi_send_power_save_command(DIS_AUTO_PS, BITMAP_UAP_INACT_PS, type, NULL);
+}
+
+void send_sleep_confirm_command(mlan_bss_type interface)
+{
+    OPT_Confirm_Sleep *ps_cfm_sleep;
+
+    HostCmd_DS_COMMAND *command = wifi_get_command_buffer();
+
+    (void)wifi_get_command_lock();
+    ps_cfm_sleep = (OPT_Confirm_Sleep *)(void *)(command);
+
+    (void)memset(ps_cfm_sleep, 0, sizeof(OPT_Confirm_Sleep));
+    ps_cfm_sleep->command = HostCmd_CMD_802_11_PS_MODE_ENH;
+    ps_cfm_sleep->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0U /* seq_num */, 0U /* bss_num */, (t_u8)(interface));
+
+    ps_cfm_sleep->size                = (t_u16)sizeof(OPT_Confirm_Sleep);
+    ps_cfm_sleep->result              = 0;
+    ps_cfm_sleep->action              = (t_u16)SLEEP_CONFIRM;
+    ps_cfm_sleep->sleep_cfm.resp_ctrl = (t_u16)RESP_NEEDED;
+
+    /* If driver did not send out sleep confirm in the expected time,
+       FW would switch to awake and send out PS AWAKE event.
+       After received AWAKE event when presleep, state would switch to AWAKE.
+       So here only send out sleep confirm when state is presleep,
+       and would not send out sleep confirm if state has switched to AWAKE */
+    if (mlan_adap->ps_state == PS_STATE_PRE_SLEEP)
+    {
+        mlan_adap->ps_state = PS_STATE_SLEEP_CFM;
+#if CONFIG_WIFI_PS_DEBUG
+        wcmdr_d("+");
+#endif
+
+        /* Write mutex is used to avoid the case that, during waiting for sleep confirm cmd response,
+         * wifi_driver_tx task or other tx task might be scheduled and send data to FW */
+        (void)OSA_MutexLock((osa_mutex_handle_t)sleep_rwlock.write_mutex, osaWaitForever_c);
+
+        (void)wifi_wait_for_cmdresp(NULL);
+
+        OSA_MutexUnlock((osa_mutex_handle_t)sleep_rwlock.write_mutex);
+    }
+    else
+    {
+        (void)wifi_put_command_lock();
+    }
+}
+
+#if CONFIG_HOST_SLEEP
+/* fixme: accept HostCmd_DS_COMMAND directly */
+void wifi_process_hs_cfg_resp(t_u8 *cmd_res_buffer)
+{
+    pmlan_adapter pmadapter              = ((mlan_private *)mlan_adap->priv[0])->adapter;
+    HostCmd_DS_802_11_HS_CFG_ENH *hs_cfg = (HostCmd_DS_802_11_HS_CFG_ENH *)(void *)(cmd_res_buffer + S_DS_GEN);
+    if (hs_cfg->action == (t_u16)HS_ACTIVATE)
+    {
+        pwr_d("Host sleep activated");
+        pmadapter->is_hs_configured = MFALSE;
+        wlan_update_rxreorder_tbl(pmadapter, MTRUE);
+        wifi_event_completion(WIFI_EVENT_HS_ACTIVATED, WIFI_EVENT_REASON_SUCCESS, NULL);
+    }
+    else
+    {
+        if (hs_cfg->params.hs_config.conditions != HOST_SLEEP_CFG_CANCEL)
+        {
+            pmadapter->is_hs_configured = MTRUE;
+        }
+        pwr_d("Host sleep configuration done");
+    }
+}
+#endif
+
+enum wifi_event_reason wifi_process_ps_enh_response(t_u8 *cmd_res_buffer, t_u16 *ps_event, t_u16 *action)
+{
+    enum wifi_event_reason result = WIFI_EVENT_REASON_FAILURE;
+    MrvlIEtypesHeader_t *mrvl_tlv = NULL;
+#if CONFIG_HOST_SLEEP
+    pmlan_adapter pmadapter = ((mlan_private *)mlan_adap->priv[0])->adapter;
+#endif
+    HostCmd_DS_802_11_PS_MODE_ENH *ps_mode = (HostCmd_DS_802_11_PS_MODE_ENH *)(void *)(cmd_res_buffer + S_DS_GEN);
+
+    *ps_event = (t_u16)WIFI_EVENT_PS_INVALID;
+    *action   = (t_u16)(ps_mode->action);
+    if (ps_mode->action == (t_u16)EN_AUTO_PS)
+    {
+        if ((ps_mode->params.auto_ps.ps_bitmap & BITMAP_AUTO_DS) != 0U)
+        {
+            pwr_d("Enabled deep sleep mode");
+            mrvl_tlv = (MrvlIEtypesHeader_t *)(void *)((uint8_t *)ps_mode + AUTO_PS_FIX_SIZE);
+            while (mrvl_tlv->type != TLV_TYPE_AUTO_DS_PARAM)
+            {
+                mrvl_tlv =
+                    (MrvlIEtypesHeader_t *)(void *)((uint8_t *)mrvl_tlv + mrvl_tlv->len + sizeof(MrvlIEtypesHeader_t));
+            }
+
+            *ps_event           = (t_u16)WIFI_EVENT_DEEP_SLEEP;
+            deepsleepps_enabled = true;
+        }
+        if ((ps_mode->params.auto_ps.ps_bitmap & BITMAP_STA_PS) != 0U)
+        {
+            pwr_d(
+                "Enabled IEEE power "
+                "save mode");
+            mrvl_tlv = (MrvlIEtypesHeader_t *)(void *)((uint8_t *)ps_mode + AUTO_PS_FIX_SIZE);
+            while (mrvl_tlv->type != TLV_TYPE_PS_PARAM)
+            {
+                mrvl_tlv =
+                    (MrvlIEtypesHeader_t *)(void *)((uint8_t *)mrvl_tlv + mrvl_tlv->len + sizeof(MrvlIEtypesHeader_t));
+            }
+            pwr_d(
+                "pscfg: %u %u %u %u "
+                "%u %u",
+                ps_tlv->param.null_pkt_interval, ps_tlv->param.multiple_dtims, ps_tlv->param.local_listen_interval,
+                ps_tlv->param.bcn_miss_timeout, ps_tlv->param.delay_to_ps, ps_tlv->param.mode);
+
+            *ps_event      = (t_u16)WIFI_EVENT_IEEE_PS;
+            ieeeps_enabled = true;
+        }
+        return WIFI_EVENT_REASON_SUCCESS;
+    }
+    else if (ps_mode->action == (t_u16)DIS_AUTO_PS)
+    {
+        if ((ps_mode->params.ps_bitmap & BITMAP_AUTO_DS) != 0U)
+        {
+            pwr_d("Disabled DeepSleep mode");
+            *ps_event           = (t_u16)WIFI_EVENT_DEEP_SLEEP;
+            deepsleepps_enabled = false;
+        }
+        if ((ps_mode->params.ps_bitmap & BITMAP_STA_PS) != 0U)
+        {
+            pwr_d(
+                "Disabled IEEE power "
+                "save mode");
+            *ps_event      = (t_u16)WIFI_EVENT_IEEE_PS;
+            ieeeps_enabled = false;
+        }
+        return WIFI_EVENT_REASON_SUCCESS;
+    }
+#if (CONFIG_WNM_PS)
+    else if (ps_mode->action == EN_WNM_PS)
+    {
+        if ((ps_mode->params.auto_ps.ps_bitmap & BITMAP_STA_PS) != 0)
+        {
+            mrvl_tlv = (MrvlIEtypesHeader_t *)((uint8_t *)ps_mode + AUTO_PS_FIX_SIZE);
+            pwr_d("ps_enh_response: bitmap = 0x%x, type = 0x%x\n", ps_mode->params.auto_ps.ps_bitmap, mrvl_tlv->type);
+            if (((mlan_private *)mlan_adap->priv[0])->wnm_set == true)
+            {
+                pwr_d("Enable WNM PS mode, wait for the enable success event");
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+
+        *ps_event = (t_u16)WIFI_EVENT_WNM_PS;
+        result    = WIFI_EVENT_REASON_SUCCESS;
+    }
+    else if (ps_mode->action == DIS_WNM_PS)
+    {
+        if ((ps_mode->params.ps_bitmap & BITMAP_STA_PS) != 0)
+        {
+            if (((mlan_private *)mlan_adap->priv[0])->wnm_set == true)
+            {
+                pwr_d(
+                    "Disabled WNM power "
+                    "save mode");
+                *ps_event                                     = (t_u16)WIFI_EVENT_WNM_PS;
+                ((mlan_private *)mlan_adap->priv[0])->wnm_set = false;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+
+        *ps_event = (t_u16)WIFI_EVENT_WNM_PS;
+        return WIFI_EVENT_REASON_SUCCESS;
+    }
+#endif
+    else if (ps_mode->action == (t_u16)GET_PS)
+    {
+        if ((ps_mode->params.ps_bitmap & BITMAP_AUTO_DS) != 0U)
+        {
+            pwr_d("Deep sleep mode is on");
+            mrvl_tlv = (MrvlIEtypesHeader_t *)(void *)((uint8_t *)ps_mode + AUTO_PS_FIX_SIZE);
+            while (mrvl_tlv->type != TLV_TYPE_AUTO_DS_PARAM)
+            {
+                mrvl_tlv =
+                    (MrvlIEtypesHeader_t *)(void *)((uint8_t *)mrvl_tlv + mrvl_tlv->len + sizeof(MrvlIEtypesHeader_t));
+            }
+        }
+        if ((ps_mode->params.ps_bitmap & BITMAP_STA_PS) != 0U)
+        {
+            pwr_d("IEEE power save mode is on");
+            mrvl_tlv = (MrvlIEtypesHeader_t *)(void *)((uint8_t *)ps_mode + AUTO_PS_FIX_SIZE);
+            while (mrvl_tlv->type != TLV_TYPE_PS_PARAM)
+            {
+                mrvl_tlv =
+                    (MrvlIEtypesHeader_t *)(void *)((uint8_t *)mrvl_tlv + mrvl_tlv->len + sizeof(MrvlIEtypesHeader_t));
+            }
+            pwr_d(
+                "pscfg: %u %u %u %u "
+                "%u %u\r\n",
+                ps_tlv->param.null_pkt_interval, ps_tlv->param.multiple_dtims, ps_tlv->param.local_listen_interval,
+                ps_tlv->param.bcn_miss_timeout, ps_tlv->param.delay_to_ps, ps_tlv->param.mode);
+        }
+    }
+    else if (ps_mode->action == (t_u16)SLEEP_CONFIRM)
+    {
+#if CONFIG_WIFI_PS_DEBUG
+        wcmdr_d("#");
+#endif
+
+        if ((ieeeps_enabled) && (deepsleepps_enabled))
+        {
+            *ps_event = (t_u16)WIFI_EVENT_IEEE_DEEP_SLEEP;
+        }
+#if (CONFIG_WNM_PS)
+        else if ((((mlan_private *)mlan_adap->priv[0])->wnm_set) && (deepsleepps_enabled))
+        {
+            *ps_event = (t_u16)WIFI_EVENT_WNM_DEEP_SLEEP;
+        }
+#endif
+        else if (ieeeps_enabled)
+        {
+            *ps_event = (t_u16)WIFI_EVENT_IEEE_PS;
+        }
+        else if (deepsleepps_enabled)
+        {
+            *ps_event = (t_u16)WIFI_EVENT_DEEP_SLEEP;
+        }
+#if (CONFIG_WNM_PS)
+        else if (((mlan_private *)mlan_adap->priv[0])->wnm_set)
+        {
+            *ps_event = (t_u16)WIFI_EVENT_WNM_PS;
+        }
+#endif
+        else
+        {
+            return WIFI_EVENT_REASON_FAILURE;
+        }
+
+        if (ieeeps_enabled || deepsleepps_enabled
+#if CONFIG_WNM_PS
+            || (((mlan_private *)mlan_adap->priv[0])->wnm_set)
+#endif
+        )
+        {
+            /* sleep confirm response needs to get the sleep_rwlock, for this lock
+             * is an indication that host needs to wakeup FW when reader (cmd/tx)
+             * could not get the sleep_rwlock */
+            int ret             = OSA_RWLockWriteLock(&sleep_rwlock, osaWaitForever_c);
+            mlan_adap->ps_state = PS_STATE_SLEEP;
+#if CONFIG_HOST_SLEEP
+            wakelock_put();
+#endif
+            if (ret == WM_SUCCESS)
+            {
+#if CONFIG_WIFI_PS_DEBUG
+                wcmdr_d("Get sleep rw lock successfully");
+#endif
+            }
+            else
+            {
+#if CONFIG_WIFI_PS_DEBUG
+                pwr_e("Failed to get sleep rw lock");
+#endif
+                return WIFI_EVENT_REASON_FAILURE;
+            }
+        }
+        else
+        {
+            return WIFI_EVENT_REASON_FAILURE;
+        }
+
+        result = WIFI_EVENT_REASON_SUCCESS;
+#if CONFIG_HOST_SLEEP
+        if (pmadapter->is_hs_configured)
+        {
+            pwr_d("Host sleep activated");
+            pmadapter->is_hs_configured = MFALSE;
+            wlan_update_rxreorder_tbl(pmadapter, MTRUE);
+            wifi_event_completion(WIFI_EVENT_SLEEP_CONFIRM_DONE, result, NULL);
+        }
+#endif
+    }
+    else
+    { /* Do Nothing */
+    }
+
+    return result;
+}
+
+#if CONFIG_HOST_SLEEP
+int wifi_get_wakeup_reason(t_u16 *hs_wakeup_reason)
+{
+    wifi_get_command_lock();
+    HostCmd_DS_COMMAND *cmd = wifi_get_command_buffer();
+
+    (void)memset(cmd, 0x00, sizeof(HostCmd_DS_COMMAND));
+    cmd->seq_num = HostCmd_SET_SEQ_NO_BSS_INFO(0 /* seq_num */, 0 /* bss_num */, BSS_TYPE_STA);
+    cmd->result  = 0x0;
+
+    wlan_ops_sta_prepare_cmd((mlan_private *)mlan_adap->priv[0], HostCmd_CMD_HS_WAKEUP_REASON, HostCmd_ACT_GEN_GET, 0,
+                             NULL, hs_wakeup_reason, cmd);
+    wifi_wait_for_cmdresp(hs_wakeup_reason);
+    return WM_SUCCESS;
+}
+#endif
+
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/incl/rtos_wpa_supp_if.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/incl/rtos_wpa_supp_if.h
new file mode 100644
index 0000000000..15b0ca3cd9
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/incl/rtos_wpa_supp_if.h
@@ -0,0 +1,171 @@
+/** @file rtos_wpa_supp_if.h
+ *
+ *  @brief  This file provides RTOS WPA Supplicant interface wifi APIs
+ *
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RTOS_WPA_SUPP_IF_H__
+#define __RTOS_WPA_SUPP_IF_H__
+
+#include <wifi_config_default.h>
+
+#if CONFIG_WPA_SUPP
+#include "includes.h"
+#include "common.h"
+#include "eloop.h"
+#include "wpa_supplicant/config.h"
+#include "wpa_supplicant_i.h"
+#include "bss.h"
+#include "driver_i.h"
+
+#include <wmlog.h>
+#include <wifi_nxp.h>
+#include <wifi_nxp_internal.h>
+
+#define supp_e(...) wmlog_e("supp_if", ##__VA_ARGS__)
+
+#if CONFIG_SUPP_DEBUG
+#define supp_d(...) wmlog("supp_if", ##__VA_ARGS__)
+#else
+#define supp_d(...)
+#endif /* ! CONFIG_SUPP_DEBUG */
+
+void *wifi_nxp_wpa_supp_dev_init(void *supp_drv_if_ctx,
+                                 const char *iface_name,
+                                 rtos_wpa_supp_dev_callbk_fns *supp_callbk_fns);
+
+void wifi_nxp_wpa_supp_dev_deinit(void *if_priv);
+
+int wifi_nxp_wpa_supp_scan2(void *if_priv, struct wpa_driver_scan_params *params);
+
+int wifi_nxp_wpa_supp_set_default_scan_ies(void *priv, const u8 *ies, size_t ies_len);
+
+int wifi_nxp_wpa_supp_sched_scan(void *if_priv, struct wpa_driver_scan_params *params);
+
+int wifi_nxp_wpa_supp_stop_sched_scan(void *if_priv);
+
+int wifi_nxp_wpa_supp_scan_abort(void *if_priv);
+
+int wifi_nxp_wpa_supp_scan_results_get(void *if_priv, struct wpa_scan_results *scan_res2);
+
+int wifi_nxp_wpa_supp_survey_results_get(void *if_priv);
+
+int wifi_nxp_wpa_supp_deauthenticate(void *if_priv, const char *addr, unsigned short reason_code);
+
+int wifi_nxp_wpa_supp_authenticate(void *if_priv, struct wpa_driver_auth_params *params, struct wpa_bss *curr_bss);
+
+int wifi_nxp_wpa_supp_associate(void *if_priv, struct wpa_driver_associate_params *params);
+
+int wifi_nxp_wpa_set_supp_port(void *if_priv, int authorized, char *bssid);
+
+int wifi_nxp_wpa_supp_set_country(void *if_priv, const char *alpha2);
+
+int wifi_nxp_wpa_supp_get_country(void *if_priv, char *alpha2);
+
+int wifi_nxp_wpa_supp_signal_poll(void *if_priv, struct wpa_signal_info *si, unsigned char *bssid);
+
+int wifi_nxp_wpa_send_mlme(void *if_priv,
+                           const u8 *data,
+                           size_t data_len,
+                           int noack,
+                           unsigned int freq,
+                           int no_cck,
+                           int offchanok,
+                           unsigned int wait_time,
+                           int cookie);
+
+int wifi_nxp_wpa_supp_set_key(void *if_priv,
+                              const unsigned char *ifname,
+                              enum wpa_alg alg,
+                              const unsigned char *addr,
+                              int key_idx,
+                              int set_tx,
+                              const unsigned char *seq,
+                              size_t seq_len,
+                              const unsigned char *key,
+                              size_t key_len,
+                              enum key_flag key_flag);
+
+int wifi_nxp_wpa_supp_del_key(void *if_priv, const unsigned char *addr, int key_idx);
+
+int wifi_nxp_wpa_supp_set_rekey_info(
+    void *if_priv, const u8 *kek, size_t kek_len, const u8 *kck, size_t kck_len, const u8 *replay_ctr);
+
+int wifi_nxp_wpa_supp_remain_on_channel(void *if_priv, unsigned int freq, unsigned int duration);
+
+int wifi_nxp_wpa_supp_cancel_remain_on_channel(void *if_priv);
+
+void wifi_nxp_wpa_supp_event_proc_mac_changed(void *if_priv);
+
+void wifi_nxp_wpa_supp_event_proc_chan_list_changed(void *if_priv, const char *alpha2);
+
+void wifi_nxp_wpa_supp_event_proc_scan_start(void *if_priv);
+
+void wifi_nxp_wpa_supp_event_proc_scan_abort(void *if_priv);
+
+void wifi_nxp_wpa_supp_event_proc_scan_done(void *if_priv, int aborted, int external_scan);
+
+void wifi_nxp_wpa_supp_event_proc_scan_res(void *if_priv,
+                                           nxp_wifi_event_new_scan_result_t *scan_res,
+                                           unsigned int event_len,
+                                           bool more_res);
+
+void wifi_nxp_wpa_supp_event_proc_survey_res(void *if_priv,
+                                             nxp_wifi_event_new_survey_result_t *survey_res,
+                                             unsigned int event_len,
+                                             bool more_res);
+
+void wifi_nxp_wpa_supp_event_proc_auth_resp(void *if_priv,
+                                            nxp_wifi_event_mlme_t *auth_resp_event,
+                                            unsigned int event_len);
+
+void wifi_nxp_wpa_supp_event_proc_assoc_resp(void *if_priv,
+                                             nxp_wifi_assoc_event_mlme_t *assoc_resp_event,
+                                             unsigned int event_len);
+
+void wifi_nxp_wpa_supp_event_proc_deauth(void *if_priv, nxp_wifi_event_mlme_t *deauth_event, unsigned int event_len);
+
+void wifi_nxp_wpa_supp_event_proc_disassoc(void *if_priv,
+                                           nxp_wifi_event_mlme_t *disassoc_event,
+                                           unsigned int event_len);
+
+void wifi_nxp_wpa_supp_event_acs_channel_selected(void *if_priv, nxp_wifi_acs_params *acs_params);
+
+void wifi_nxp_wpa_supp_event_proc_unprot_mgmt(void *if_priv,
+                                              nxp_wifi_event_mlme_t *unprot_mgmt_event,
+                                              unsigned int event_len);
+void wifi_nxp_wpa_supp_event_proc_remain_on_channel(void *if_priv, int cancel_channel);
+void wifi_nxp_wpa_supp_event_proc_mgmt_rx(void *if_priv, nxp_wifi_event_mlme_t *mgmt_rx, unsigned int event_len);
+void wifi_nxp_wpa_supp_event_proc_eapol_rx(void *if_priv,
+                                           nxp_wifi_event_eapol_mlme_t *eapol_rx,
+                                           unsigned int event_len);
+void wifi_nxp_wpa_supp_event_mgmt_tx_status(void *if_priv, nxp_wifi_event_mlme_t *mlme_event, unsigned int event_len);
+
+void wifi_nxp_wpa_supp_event_proc_ecsa_complete(void *if_priv, nxp_wifi_ch_switch_info *ch_switch_info);
+void wifi_nxp_wpa_supp_event_proc_dfs_cac_started(void *if_priv, nxp_wifi_dfs_cac_info *dfs_cac_info);
+void wifi_nxp_wpa_supp_event_proc_dfs_cac_finished(void *if_priv, nxp_wifi_dfs_cac_info *dfs_cac_info);
+
+void *wifi_nxp_hostapd_dev_init(void *hapd_drv_if_ctx,
+                                const char *iface_name,
+                                rtos_hostapd_dev_callbk_fns *hostapd_callbk_fns);
+void wifi_nxp_hostapd_dev_deinit(void *if_priv);
+int wifi_nxp_hostapd_do_acs(void *priv, struct drv_acs_params *params);
+int wifi_nxp_hostapd_set_ap(void *if_priv, int beacon_set, struct wpa_driver_ap_params *params);
+int wifi_nxp_hostapd_set_modes(void *if_priv, struct hostapd_hw_modes *modes);
+int wifi_nxp_hostapd_sta_add(void *if_priv, struct hostapd_sta_add_params *params);
+int wifi_nxp_hostapd_sta_remove(void *if_priv, const u8 *addr);
+int wifi_nxp_hostapd_send_eapol(void *if_priv, const u8 *data, size_t data_len);
+int wifi_nxp_hostapd_set_freq(void *if_priv, struct hostapd_freq_params *freq);
+int wifi_nxp_hostapd_set_rts(void *if_priv, int rts_threshold);
+int wifi_nxp_hostapd_set_frag(void *if_priv, int frag_threshold);
+int wifi_nxp_hostapd_stop_ap(void *if_priv);
+int wifi_nxp_hostapd_set_acl(void *if_priv, struct hostapd_acl_params *params);
+int wifi_nxp_wpa_dpp_listen(void *if_priv, bool enable);
+bool wifi_nxp_wpa_get_modes(void *if_priv);
+#endif /* CONFIG_WPA_SUPP */
+#endif /*  __rtos_WPA_SUPP_IF_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/incl/wifi_nxp_internal.h b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/incl/wifi_nxp_internal.h
new file mode 100644
index 0000000000..32e9aa5f79
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/incl/wifi_nxp_internal.h
@@ -0,0 +1,513 @@
+/** @file wifi_nxp_internal.h
+ *
+ * @brief This file provides Core Wi-Fi definition for wpa supplicant RTOS driver.
+ *
+ * Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __WIFI_NXP_INTERNAL_H__
+#define __WIFI_NXP_INTERNAL_H__
+
+#include <stdio.h>
+
+#include <wifi_config_default.h>
+
+#if CONFIG_WPA_SUPP
+
+#define WIFI_HE_MAX_MAC_CAPAB_SIZE  6
+#define WIFI_HE_MAX_PHY_CAPAB_SIZE  11
+#define WIFI_HE_MAX_MCS_CAPAB_SIZE  12
+#define WIFI_HE_MAX_PPET_CAPAB_SIZE 25
+
+/**
+ * struct he_capabilities - IEEE 802.11ax HE capabilities
+ */
+typedef MLAN_PACK_START struct _nxp_wifi_he_capabilities
+{
+    unsigned char he_supported;
+    unsigned char phy_cap[WIFI_HE_MAX_PHY_CAPAB_SIZE];
+    unsigned char mac_cap[WIFI_HE_MAX_MAC_CAPAB_SIZE];
+    unsigned char mcs[WIFI_HE_MAX_MCS_CAPAB_SIZE];
+    unsigned char ppet[WIFI_HE_MAX_PPET_CAPAB_SIZE];
+    unsigned short he_6ghz_capa;
+} MLAN_PACK_END nxp_wifi_he_capabilities;
+
+#define WIFI_MAX_IE_LEN 500U
+
+typedef MLAN_PACK_START struct _nxp_wifi_ie
+{
+    unsigned short ie_len;
+    char ie[WIFI_MAX_IE_LEN];
+} MLAN_PACK_END nxp_wifi_ie_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_ie2
+{
+    unsigned short ie_len;
+    unsigned char *ie;
+} MLAN_PACK_END nxp_wifi_ie2_t;
+
+#define WIFI_MAX_SSID_LEN 32U
+#define WIFI_ETH_ADDR_LEN 6U
+
+typedef MLAN_PACK_START struct _nxp_wifi_ssid
+{
+    unsigned char ssid_len;
+    unsigned char ssid[WIFI_MAX_SSID_LEN];
+} MLAN_PACK_END nxp_wifi_ssid_t;
+
+#define WIFI_SCAN_MAX_NUM_SSIDS 2U
+#define WIFI_SCAN_MAX_NUM_CHAN  41U
+#define MAX_NUM_CHANNELS        39U
+
+typedef MLAN_PACK_START struct _nxp_wifi_trigger_scan
+{
+    bool hostapd;
+    unsigned char num_ssids;
+    nxp_wifi_ssid_t scan_ssids[WIFI_SCAN_MAX_NUM_SSIDS];
+    unsigned char num_chans;
+    unsigned char chan_list[WIFI_SCAN_MAX_NUM_CHAN];
+    nxp_wifi_ie_t extra_ies;
+    int filter_rssi;
+    unsigned char bssid[WIFI_ETH_ADDR_LEN];
+    unsigned int only_new_results : 1;
+} MLAN_PACK_END nxp_wifi_trigger_scan_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_trigger_sched_scan
+{
+    unsigned int chan_per_scan;
+    unsigned char num_ssids;
+    nxp_wifi_ssid_t scan_ssids[WIFI_SCAN_MAX_NUM_SSIDS];
+    unsigned char num_chans;
+    unsigned char chan_list[WIFI_SCAN_MAX_NUM_CHAN];
+    nxp_wifi_ie_t extra_ies;
+    unsigned int scan_interval;
+    unsigned int report_condition;
+    unsigned short repeat_count;
+    int filter_rssi;
+} MLAN_PACK_END nxp_wifi_trigger_sched_scan_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_event_new_scan_result
+{
+    unsigned int frequency;
+    unsigned int chan_width;
+    unsigned int seen_ms_ago;
+    int status;
+    unsigned long long ies_tsf;
+    unsigned long long beacon_ies_tsf;
+    unsigned short beacon_interval;
+    unsigned short capability;
+    nxp_wifi_ie2_t ies;
+    unsigned char rssi;
+    unsigned short noise;
+    unsigned char mac_addr[WIFI_ETH_ADDR_LEN];
+    bool more_res;
+} MLAN_PACK_END nxp_wifi_event_new_scan_result_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_trigger_op
+{
+    bool hostapd;
+} MLAN_PACK_END nxp_wifi_trigger_op_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_event_new_survey_result
+{
+    unsigned int freq;
+    char nf;
+    unsigned long long channel_time;
+    unsigned long long channel_time_busy;
+    unsigned long long channel_time_rx;
+    unsigned long long channel_time_tx;
+    bool more_res;
+} MLAN_PACK_END nxp_wifi_event_new_survey_result_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_acs_params
+{
+    unsigned int pri_freq;
+    unsigned int sec_freq;
+    unsigned short ch_width;
+    unsigned int hw_mode;
+} MLAN_PACK_END nxp_wifi_acs_params;
+
+#define WIFI_MAX_FRAME_LEN 1500U
+
+typedef MLAN_PACK_START struct _nxp_wifi_frame
+{
+    int frame_len;
+    int freq;
+    unsigned char frame[WIFI_MAX_FRAME_LEN];
+} MLAN_PACK_END nxp_wifi_frame_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_event_mlme
+{
+    nxp_wifi_frame_t frame;
+    unsigned char mac_addr[WIFI_ETH_ADDR_LEN];
+} MLAN_PACK_END nxp_wifi_event_mlme_t;
+
+#define WIFI_EAPOL_MAX_FRAME_LEN 1500U
+
+typedef MLAN_PACK_START struct _nxp_wifi_eapol_frame
+{
+    int frame_len;
+    unsigned char frame[WIFI_EAPOL_MAX_FRAME_LEN];
+} MLAN_PACK_END nxp_wifi_eapol_frame_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_event_eapol_mlme
+{
+    nxp_wifi_eapol_frame_t frame;
+    unsigned char mac_addr[WIFI_ETH_ADDR_LEN];
+} MLAN_PACK_END nxp_wifi_event_eapol_mlme_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_assoc_event_mlme
+{
+    nxp_wifi_frame_t frame;
+    unsigned char mac_addr[WIFI_ETH_ADDR_LEN];
+    unsigned int req_ie_len;
+    unsigned char req_ie[WIFI_MAX_FRAME_LEN];
+} MLAN_PACK_END nxp_wifi_assoc_event_mlme_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_gsta_info
+{
+    unsigned char mac_addr[WIFI_ETH_ADDR_LEN];
+} MLAN_PACK_END nxp_wifi_gsta_info_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_event_new_station
+{
+    // struct wpa_signal_info for supplicant
+    unsigned char wme;
+    unsigned char is_sta_legacy;
+    unsigned char mac_addr[WIFI_ETH_ADDR_LEN];
+    unsigned int generation;
+    nxp_wifi_gsta_info_t sta_info;
+    nxp_wifi_ie_t assoc_req_ies;
+} MLAN_PACK_END nxp_wifi_event_new_station_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_chan_definition
+{
+    int width;
+    unsigned int center_frequency1;
+    unsigned int center_frequency2;
+} MLAN_PACK_END nxp_wifi_chan_definition_t;
+
+#define IFACENAMSIZ 10U
+
+typedef MLAN_PACK_START struct _nxp_wifi_interface_info
+{
+    // struct wpa_signal_info for supplicant
+    int nrf_wifi_iftype;
+    char ifacename[IFACENAMSIZ];
+    unsigned char nxp_wifi_eth_addr[WIFI_ETH_ADDR_LEN];
+    nxp_wifi_chan_definition_t chan_def;
+    nxp_wifi_ssid_t ssid;
+} MLAN_PACK_END nxp_wifi_interface_info_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_auth_info
+{
+    unsigned char auth_alg;
+    unsigned char auth_trans_num;
+    unsigned char status_code;
+    unsigned char bssid[WIFI_ETH_ADDR_LEN];
+    int channel;
+    nxp_wifi_ie_t auth_ie;
+} MLAN_PACK_END nxp_wifi_auth_info_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_deauth_info
+{
+    unsigned char bssid[WIFI_ETH_ADDR_LEN];
+    unsigned short reason_code;
+} MLAN_PACK_END nxp_wifi_deauth_info_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_assoc_info
+{
+    unsigned int center_frequency;
+    nxp_wifi_ssid_t ssid;
+    unsigned char bssid[WIFI_ETH_ADDR_LEN];
+    unsigned char prev_bssid[WIFI_ETH_ADDR_LEN];
+    int channel;
+    nxp_wifi_ie_t wpa_ie;
+    unsigned char use_mfp;
+    char control_port;
+    bool is_ft;
+} MLAN_PACK_END nxp_wifi_assoc_info_t;
+
+#define WIFI_MAX_KEY_LEN 256U
+
+typedef MLAN_PACK_START struct _nxp_wifi_key_info
+{
+    bool is_pairwise;
+    int key_idx;
+    unsigned char key[WIFI_MAX_KEY_LEN];
+    size_t key_len;
+    unsigned char bssid[WIFI_ETH_ADDR_LEN];
+} MLAN_PACK_END nxp_wifi_key_info_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_port_info
+{
+    int authorized;
+    unsigned char bssid[WIFI_ETH_ADDR_LEN];
+} MLAN_PACK_END nxp_wifi_port_info_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_signal_info
+{
+    int current_signal;
+    int avg_signal;
+    int avg_beacon_signal;
+    int current_noise;
+    int current_txrate;
+} MLAN_PACK_END nxp_wifi_signal_info_t;
+
+#define WIFI_MAX_DATA_LEN 400U
+
+typedef MLAN_PACK_START struct _nxp_wifi_mgmt_tx_info
+{
+    int channel;
+    unsigned int wait_time;
+    size_t data_len;
+    unsigned char data[WIFI_MAX_DATA_LEN];
+} MLAN_PACK_END nxp_wifi_mgmt_tx_info_t;
+
+enum wifi_mode
+{
+    MODE_IEEE80211B,
+    MODE_IEEE80211G,
+    MODE_IEEE80211A,
+    MODE_IEEE80211AD,
+    MODE_IEEE80211ANY,
+    NUM_MODES
+};
+
+typedef MLAN_PACK_START struct _nxp_wifi_chan_info
+{
+    enum wifi_mode mode;
+    int freq;
+    int channel;
+    int sec_channel_offset;
+    int bandwidth;
+    int ht_enabled;
+    int vht_enabled;
+    int he_enabled;
+    int center_freq1;
+    int center_freq2;
+} MLAN_PACK_END nxp_wifi_chan_info_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_ap_info
+{
+    int beacon_set;
+    unsigned char bssid[WIFI_ETH_ADDR_LEN];
+    nxp_wifi_ie_t head_ie;
+    nxp_wifi_ie_t tail_ie;
+    int dtim_period;
+    int beacon_int;
+    nxp_wifi_chan_info_t chan;
+    nxp_wifi_ie_t proberesp;
+    nxp_wifi_ssid_t ssid;
+    int hide_ssid;
+    unsigned int pairwise_ciphers;
+    unsigned int group_cipher;
+    unsigned int key_mgmt_suites;
+    unsigned int auth_algs;
+    unsigned int wpa_version;
+    int privacy;
+    nxp_wifi_ie_t beacon_ies;
+    nxp_wifi_ie_t proberesp_ies;
+    nxp_wifi_ie_t assocresp_ies;
+    int ht_opmode;
+    int ap_max_inactivity;
+    int reenable;
+    int twt_responder;
+    int sae_pwe;
+} MLAN_PACK_END nxp_wifi_ap_info_t;
+
+/* HT Capabilities element */
+typedef MLAN_PACK_START struct _ieee80211_ht_capab
+{
+    unsigned short ht_capabilities_info;
+    unsigned char a_mpdu_params;
+    unsigned char supported_mcs_set[16];
+    unsigned short ht_extended_capabilities;
+    unsigned int tx_bf_capability_info;
+    unsigned char asel_capabilities;
+} MLAN_PACK_END ieee80211_ht_capab_t;
+
+typedef MLAN_PACK_START struct _ieee80211_vht_capab
+{
+    unsigned int vht_capabilities_info;
+    struct
+    {
+        unsigned short rx_map;
+        unsigned short rx_highest;
+        unsigned short tx_map;
+        unsigned short tx_highest;
+    } vht_supported_mcs_set;
+} MLAN_PACK_END ieee80211_vht_capab_t;
+
+typedef MLAN_PACK_START struct _ieee80211_he_capab
+{
+    unsigned char he_mac_capab_info[6];
+    unsigned char he_phy_capab_info[11];
+    unsigned char optional[37];
+} MLAN_PACK_END ieee80211_he_capab_t;
+
+typedef MLAN_PACK_START struct _nxp_wifi_sta_info
+{
+    unsigned char addr[WIFI_ETH_ADDR_LEN];
+    unsigned short aid;
+    unsigned short capability;
+    unsigned char supp_rates[30];
+    size_t supp_rates_len;
+    unsigned short listen_interval;
+    ieee80211_ht_capab_t ht_capab;
+    size_t ht_capab_len;
+    ieee80211_vht_capab_t vht_capab;
+    size_t vht_capab_len;
+    int vht_opmode_enabled;
+    unsigned char vht_opmode;
+    ieee80211_he_capab_t he_capab;
+    size_t he_capab_len;
+    unsigned int flags; /* bitmask of WPA_STA_* flags */
+    int set;            /* Set STA parameters instead of add */
+    unsigned char qosinfo;
+    unsigned char ext_capab[10];
+    size_t ext_capab_len;
+} MLAN_PACK_END nxp_wifi_sta_info_t;
+
+enum chanWidth
+{
+    CHAN_BAND_WIDTH_20_NOHT,
+    CHAN_BAND_WIDTH_20,
+    CHAN_BAND_WIDTH_40,
+    CHAN_BAND_WIDTH_80,
+    CHAN_BAND_WIDTH_80P80,
+    CHAN_BAND_WIDTH_160,
+};
+
+typedef MLAN_PACK_START struct _nxp_wifi_ch_switch_info
+{
+    int center_freq;
+    int ht_enabled;
+    int ch_offset;
+    enum chanWidth ch_width;
+    int center_freq1;
+    int center_freq2;
+} MLAN_PACK_END nxp_wifi_ch_switch_info;
+
+typedef MLAN_PACK_START struct _nxp_wifi_dfs_cac_info
+{
+    int center_freq;
+    int ht_enabled;
+    int ch_offset;
+    enum chanWidth ch_width;
+    int center_freq1;
+    int center_freq2;
+} MLAN_PACK_END nxp_wifi_dfs_cac_info;
+/**
+ * struct wifi_nxp_callbk_fns - Callback functions to be invoked by Wi-Fi driver
+ * when a paticular event occurs.
+ * @if_state_chg_callbk_fn: Callback function to be called when an interface
+ *                          state changes.
+ * @rx_frm_callbk_fn: Callback function to be called when a frame is received.
+ *
+ * This structure contains function pointers to all the callback functions that
+ * the Wi-Fi driver needs to invoked for various events.
+ */
+typedef MLAN_PACK_START struct _wifi_nxp_callbk_fns
+{
+    void (*mac_changed_callbk_fn)(void *if_priv);
+
+    void (*chan_list_changed_callbk_fn)(void *if_priv, const char *alpha2);
+
+    void (*scan_start_callbk_fn)(void *if_priv);
+
+    void (*scan_done_callbk_fn)(void *if_priv, int external_scan);
+
+    void (*scan_abort_callbk_fn)(void *if_priv);
+
+    void (*survey_res_callbk_fn)(void *if_priv,
+                                 nxp_wifi_event_new_survey_result_t *survey_res,
+                                 unsigned int event_len,
+                                 bool more_res);
+
+    void (*auth_resp_callbk_fn)(void *if_priv, nxp_wifi_event_mlme_t *auth_resp_event, unsigned int event_len);
+
+    void (*assoc_resp_callbk_fn)(void *if_priv, nxp_wifi_assoc_event_mlme_t *assoc_resp_event, unsigned int event_len);
+
+    void (*deauth_callbk_fn)(void *if_priv, nxp_wifi_event_mlme_t *deauth_event, unsigned int event_len);
+
+    void (*disassoc_callbk_fn)(void *if_priv, nxp_wifi_event_mlme_t *disassoc_event, unsigned int event_len);
+
+    void (*acs_channel_sel_callbk_fn)(void *if_priv, nxp_wifi_acs_params *acs_params);
+
+    void (*mgmt_rx_callbk_fn)(void *if_priv, nxp_wifi_event_mlme_t *mgmt_rx_event, unsigned int event_len);
+    void (*eapol_rx_callbk_fn)(void *if_priv, nxp_wifi_event_eapol_mlme_t *mgmt_rx_event, unsigned int event_len);
+    void (*unprot_mlme_mgmt_rx_callbk_fn)(void *if_priv,
+                                          nxp_wifi_event_mlme_t *unprot_mlme_event,
+                                          unsigned int event_len);
+
+    void (*mgmt_tx_status_callbk_fn)(void *if_priv, nxp_wifi_event_mlme_t *mlme_event, unsigned int event_len);
+    void (*remain_on_channel_callbk_fn)(void *if_priv, int cancel_channel);
+    void (*ecsa_complete_callbk_fn)(void *if_priv, nxp_wifi_ch_switch_info *ch_switch_info);
+    void (*dfs_cac_started_callbk_fn)(void *if_priv, nxp_wifi_dfs_cac_info *ch_switch_info);
+    void (*dfs_cac_finished_callbk_fn)(void *if_priv, nxp_wifi_dfs_cac_info *ch_switch_info);
+} MLAN_PACK_END wifi_nxp_callbk_fns_t;
+#endif
+typedef struct _chan_to_freq_t
+{
+    /** Channel */
+    t_u16 channel;
+    /** Frequency */
+    t_u32 freq;
+    /** Band */
+    t_u8 band;
+} chan_to_freq_t;
+static const chan_to_freq_t chan_to_freq[] = {
+    {1, 2412, 0},   {2, 2417, 0},   {3, 2422, 0},   {4, 2427, 0},   {5, 2432, 0},   {6, 2437, 0},   {7, 2442, 0},
+    {8, 2447, 0},   {9, 2452, 0},   {10, 2457, 0},  {11, 2462, 0},  {12, 2467, 0},  {13, 2472, 0},  {14, 2484, 0},
+    {183, 4915, 1}, {184, 4920, 1}, {185, 4925, 1}, {187, 4935, 1}, {188, 4940, 1}, {189, 4945, 1}, {192, 4960, 1},
+    {196, 4980, 1}, {7, 5035, 1},   {8, 5040, 1},   {9, 5045, 1},   {11, 5055, 1},  {12, 5060, 1},  {16, 5080, 1},
+    {34, 5170, 1},  {36, 5180, 1},  {38, 5190, 1},  {40, 5200, 1},  {42, 5210, 1},  {44, 5220, 1},  {46, 5230, 1},
+    {48, 5240, 1},  {52, 5260, 1},  {56, 5280, 1},  {60, 5300, 1},  {64, 5320, 1},  {100, 5500, 1}, {104, 5520, 1},
+    {108, 5540, 1}, {112, 5560, 1}, {116, 5580, 1}, {120, 5600, 1}, {124, 5620, 1}, {128, 5640, 1}, {132, 5660, 1},
+    {136, 5680, 1}, {140, 5700, 1}, {144, 5720, 1}, {149, 5745, 1}, {153, 5765, 1}, {157, 5785, 1}, {161, 5805, 1},
+#if CONFIG_UNII4_BAND_SUPPORT
+    {165, 5825, 1}, {169, 5845, 1}, {173, 5865, 1}, {177, 5885, 1},
+#else
+    {165, 5825, 1},
+#endif
+};
+/** Convertion from/to frequency/channel */
+/**
+ *  @brief Get frequency for channel in given band
+ *
+ *  @param channel      channel
+ *  @param band         band
+ *
+ *  @return             freq
+ */
+static inline int channel_to_frequency(t_u16 channel, t_u8 band)
+{
+    int i = 0;
+    for (i = 0; i < (int)ARRAY_SIZE(chan_to_freq); i++)
+    {
+        if (channel == chan_to_freq[i].channel && band == chan_to_freq[i].band)
+        {
+            return chan_to_freq[i].freq;
+        }
+    }
+    return 0;
+}
+
+static inline t_u16 freq_to_chan(unsigned int freq)
+{
+    int i = 0;
+    for (i = 0; i < (int)ARRAY_SIZE(chan_to_freq); i++)
+    {
+        if (freq == chan_to_freq[i].freq)
+        {
+            return chan_to_freq[i].channel;
+        }
+    }
+    return 0;
+}
+
+#endif /* __WIFI_NXP_INTERNAL_H__ */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/rtos_wpa_supp_if.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/rtos_wpa_supp_if.c
new file mode 100644
index 0000000000..243b79d4c2
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/rtos_wpa_supp_if.c
@@ -0,0 +1,2634 @@
+/** @file rtos_wpa_supp_if.c
+ *
+ *  @brief  This file provides RTOS WPA Supplicant interface wifi APIs
+ *
+ *
+ *  Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdlib.h>
+#include "fsl_os_abstraction.h"
+#include "wifi.h"
+#include <wm_net.h>
+
+#ifndef __ZEPHYR__
+#include "fsl_debug_console.h"
+#endif
+
+#if CONFIG_WPA_SUPP
+
+#include "rtos_wpa_supp_if.h"
+#include "wifi-internal.h"
+
+#define MAX_MGMT_TX_FRAME_SIZE 1500
+
+static unsigned char get_algo_from_auth_type(int wpa_auth_alg)
+{
+    if (wpa_auth_alg & WPA_AUTH_ALG_OPEN)
+    {
+        return MLAN_AUTH_MODE_OPEN;
+    }
+    if (wpa_auth_alg & WPA_AUTH_ALG_SHARED)
+    {
+        return MLAN_AUTH_MODE_SHARED;
+    }
+    if (wpa_auth_alg & WPA_AUTH_ALG_LEAP)
+    {
+        return MLAN_AUTH_MODE_NETWORKEAP;
+    }
+    if (wpa_auth_alg & WPA_AUTH_ALG_FT)
+    {
+        return MLAN_AUTH_MODE_FT;
+    }
+    if (wpa_auth_alg & WPA_AUTH_ALG_SAE)
+    {
+        return MLAN_AUTH_MODE_SAE;
+    }
+
+    return MLAN_AUTH_MODE_AUTO;
+}
+
+static unsigned int wpa_alg_to_cipher_suite(enum wpa_alg alg, size_t key_len)
+{
+    unsigned flags = 0;
+
+    if (alg == WPA_ALG_GCMP)
+    {
+        flags |= KEY_FLAG_GCMP;
+    }
+    else if (alg == WPA_ALG_GCMP_256)
+    {
+        flags |= KEY_FLAG_GCMP_256;
+    }
+
+    if (alg == WPA_ALG_CCMP_256)
+    {
+        flags |= KEY_FLAG_CCMP_256;
+    }
+
+    if ((alg == WPA_ALG_BIP_CMAC_128) || (alg == WPA_ALG_BIP_CMAC_256) || (alg == WPA_ALG_BIP_GMAC_128) ||
+        (alg == WPA_ALG_BIP_GMAC_256))
+    {
+        flags |= KEY_FLAG_AES_MCAST_IGTK;
+
+        if (alg == WPA_ALG_BIP_GMAC_128)
+        {
+            flags |= KEY_FLAG_GMAC_128;
+        }
+        else if (alg == WPA_ALG_BIP_GMAC_256)
+        {
+            flags |= KEY_FLAG_GMAC_256;
+        }
+    }
+
+    return flags;
+}
+
+#if 0
+static enum chan_width drv2supp_chan_width(int width)
+{
+	switch (width) {
+	case NXP_WIFI_CHAN_WIDTH_20_NOHT:
+		return CHAN_WIDTH_20_NOHT;
+	case NXP_WIFI_CHAN_WIDTH_20:
+		return CHAN_WIDTH_20;
+	case NXP_WIFI_CHAN_WIDTH_40:
+		return CHAN_WIDTH_40;
+	case NXP_WIFI_CHAN_WIDTH_80:
+		return CHAN_WIDTH_80;
+	case NXP_WIFI_CHAN_WIDTH_80P80:
+		return CHAN_WIDTH_80P80;
+	case NXP_WIFI_CHAN_WIDTH_160:
+		return CHAN_WIDTH_160;
+	default:
+		break;
+	}
+	return CHAN_WIDTH_UNKNOWN;
+}
+#endif
+
+void wifi_nxp_wpa_supp_event_proc_mac_changed(void *if_priv)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.mac_changed(wifi_if_ctx_rtos->hapd_drv_if_ctx);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.mac_changed(wifi_if_ctx_rtos->supp_drv_if_ctx);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_chan_list_changed(void *if_priv, const char *alpha2)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Missing interface context", __func__);
+        return;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    memset(&event, 0, sizeof(event));
+
+    if (!alpha2)
+    {
+        supp_e("%s: Missing alpha2 data", __func__);
+        return;
+    }
+
+    event.channel_list_changed.initiator = REGDOM_SET_BY_USER;
+    event.channel_list_changed.type      = REGDOM_TYPE_COUNTRY;
+    event.channel_list_changed.alpha2[0] = alpha2[0];
+    event.channel_list_changed.alpha2[1] = alpha2[1];
+    event.channel_list_changed.alpha2[2] = alpha2[2];
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.chan_list_changed(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.chan_list_changed(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_scan_start(void *if_priv)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    struct os_time t;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    os_get_time(&t);
+
+    memcpy(&wifi_if_ctx_rtos->scan_start_tsf_bssid, &wifi_if_ctx_rtos->assoc_bssid, ETH_ALEN);
+
+    wifi_if_ctx_rtos->scan_start_tsf = t.sec * 1000;
+
+    if (wifi_if_ctx_rtos->supp_callbk_fns.scan_start)
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.scan_start(wifi_if_ctx_rtos->supp_drv_if_ctx);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_scan_abort(void *if_priv)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    wifi_if_ctx_rtos->scan_in_progress = false;
+
+    wifi_if_ctx_rtos->supp_callbk_fns.scan_abort(wifi_if_ctx_rtos->supp_drv_if_ctx);
+}
+
+void wifi_nxp_wpa_supp_event_proc_scan_done(void *if_priv, int aborted, int external_scan)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+    struct scan_info *info = NULL;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    memset(&event, 0, sizeof(event));
+
+    info                = &event.scan_info;
+    info->aborted       = aborted;
+    info->external_scan = external_scan;
+    info->nl_scan_event = 1;
+
+    memcpy(&info->scan_start_tsf, &wifi_if_ctx_rtos->scan_start_tsf, sizeof(info->scan_start_tsf));
+
+    memcpy(&info->scan_start_tsf_bssid, &wifi_if_ctx_rtos->scan_start_tsf_bssid, ETH_ALEN);
+
+    wifi_if_ctx_rtos->scan_in_progress = false;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.scan_done(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.scan_done(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_survey_res(void *if_priv,
+                                             nxp_wifi_event_new_survey_result_t *survey_res,
+                                             unsigned int event_len,
+                                             bool more_res)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    struct freq_survey *survey                 = NULL;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (survey_res == NULL)
+    {
+#if CONFIG_HOSTAPD
+        if (wifi_if_ctx_rtos->hostapd)
+        {
+            wifi_if_ctx_rtos->hostapd_callbk_fns.survey_res(wifi_if_ctx_rtos->hapd_drv_if_ctx, survey, more_res);
+        }
+        else
+#endif
+        {
+            wifi_if_ctx_rtos->supp_callbk_fns.survey_res(wifi_if_ctx_rtos->supp_drv_if_ctx, survey, more_res);
+        }
+        return;
+    }
+
+    survey = (struct freq_survey *)OSA_MemoryAllocate(sizeof(*survey));
+
+    if (!survey)
+    {
+        supp_e("%s: Unable to calloc memory for survey result\n", __func__);
+        return;
+    }
+
+    survey->freq = survey_res->freq;
+
+    if (survey_res->nf)
+    {
+        survey->nf = survey_res->nf;
+        survey->filled |= SURVEY_HAS_NF;
+    }
+
+    if (survey_res->channel_time)
+    {
+        (void)memcpy((void *)&survey->channel_time, (const void *)&survey_res->channel_time,
+                     sizeof(survey->channel_time));
+        survey->filled |= SURVEY_HAS_CHAN_TIME;
+    }
+
+    if (survey_res->channel_time_busy)
+    {
+        (void)memcpy((void *)&survey->channel_time_busy, (const void *)&survey_res->channel_time_busy,
+                     sizeof(survey->channel_time_busy));
+        survey->filled |= SURVEY_HAS_CHAN_TIME_BUSY;
+    }
+
+    if (survey_res->channel_time_rx)
+    {
+        (void)memcpy((void *)&survey->channel_time_rx, (const void *)&survey_res->channel_time_rx,
+                     sizeof(survey->channel_time_rx));
+        survey->filled |= SURVEY_HAS_CHAN_TIME_RX;
+    }
+
+    if (survey_res->channel_time_tx)
+    {
+        (void)memcpy((void *)&survey->channel_time_tx, (const void *)&survey_res->channel_time_tx,
+                     sizeof(survey->channel_time_tx));
+        survey->filled |= SURVEY_HAS_CHAN_TIME_TX;
+    }
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.survey_res(wifi_if_ctx_rtos->hapd_drv_if_ctx, survey, more_res);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.survey_res(wifi_if_ctx_rtos->supp_drv_if_ctx, survey, more_res);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_auth_resp(void *if_priv, nxp_wifi_event_mlme_t *auth_resp, unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+    const struct ieee80211_mgmt *mgmt = NULL;
+    const unsigned char *frame        = NULL;
+    unsigned int frame_len            = 0;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    frame     = (const unsigned char *)auth_resp->frame.frame;
+    frame_len = auth_resp->frame.frame_len;
+    mgmt      = (const struct ieee80211_mgmt *)frame;
+
+    if (frame_len < 4 + (2 * WIFI_ETH_ADDR_LEN))
+    {
+        supp_e("%s: MLME event too short", __func__);
+        return;
+    }
+
+    if (frame_len < 24 + sizeof(mgmt->u.auth))
+    {
+        supp_e("%s: Authentication response frame too short", __func__);
+        return;
+    }
+
+    memset(&event, 0, sizeof(event));
+
+    memcpy(event.auth.peer, mgmt->sa, ETH_ALEN);
+
+    event.auth.auth_type = le_to_host16(mgmt->u.auth.auth_alg);
+
+    event.auth.auth_transaction = le_to_host16(mgmt->u.auth.auth_transaction);
+
+    event.auth.status_code = le_to_host16(mgmt->u.auth.status_code);
+
+    if (frame_len > 24 + sizeof(mgmt->u.auth))
+    {
+        event.auth.ies     = mgmt->u.auth.variable;
+        event.auth.ies_len = (frame_len - 24 - sizeof(mgmt->u.auth));
+    }
+
+    wifi_if_ctx_rtos->supp_callbk_fns.auth_resp(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+}
+
+void wifi_nxp_wpa_supp_event_proc_assoc_resp(void *if_priv,
+                                             nxp_wifi_assoc_event_mlme_t *assoc_resp,
+                                             unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+    const struct ieee80211_mgmt *mgmt              = NULL;
+    const unsigned char *frame                     = NULL;
+    const unsigned char *req_frame                 = NULL;
+    const unsigned char *bssid                     = NULL;
+    unsigned int frame_len                         = 0;
+    unsigned short status                          = WLAN_STATUS_UNSPECIFIED_FAILURE;
+    enum sta_connect_fail_reason_codes reason_code = STA_CONNECT_FAIL_REASON_UNSPECIFIED;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    frame     = (const unsigned char *)assoc_resp->frame.frame;
+    frame_len = assoc_resp->frame.frame_len;
+    req_frame = (const unsigned char *)assoc_resp->req_ie;
+
+    mgmt = (const struct ieee80211_mgmt *)frame;
+
+    memset(&event, 0, sizeof(event));
+    memset(&wifi_if_ctx_rtos->assoc_bssid, 0, ETH_ALEN);
+
+    if (frame_len < 24 + sizeof(mgmt->u.assoc_resp))
+    {
+        supp_d("%s: Association response frame too short", __func__);
+        bssid       = (unsigned char *)&wifi_if_ctx_rtos->attempt_bssid;
+        reason_code = STA_CONNECT_FAIL_REASON_ASSOC_NO_RESP_RECEIVED;
+        goto fail;
+    }
+
+    status = le_to_host16(mgmt->u.assoc_resp.status_code);
+
+    bssid = mgmt->bssid;
+
+    if (status != WLAN_STATUS_SUCCESS)
+    {
+    fail:
+        wifi_if_ctx_rtos->associated = false;
+        event.assoc_reject.bssid     = bssid;
+
+        if (frame_len > 24 + sizeof(mgmt->u.assoc_resp))
+        {
+            event.assoc_reject.resp_ies     = (unsigned char *)mgmt->u.assoc_resp.variable;
+            event.assoc_reject.resp_ies_len = (frame_len - 24 - sizeof(mgmt->u.assoc_resp));
+        }
+
+        event.assoc_reject.status_code    = status;
+        event.assoc_reject.reason_code    = reason_code;
+        event.assoc_reject.timeout_reason = NULL;
+    }
+    else
+    {
+        wifi_if_ctx_rtos->associated = true;
+        memcpy(&wifi_if_ctx_rtos->assoc_bssid, mgmt->bssid, ETH_ALEN);
+
+        event.assoc_info.addr           = mgmt->bssid;
+        event.assoc_info.resp_frame     = frame;
+        event.assoc_info.resp_frame_len = frame_len;
+        event.assoc_info.freq           = wifi_if_ctx_rtos->assoc_freq;
+
+        if (frame_len > 24 + sizeof(mgmt->u.assoc_resp))
+        {
+            event.assoc_info.resp_ies     = (unsigned char *)mgmt->u.assoc_resp.variable;
+            event.assoc_info.resp_ies_len = (frame_len - 24 - sizeof(mgmt->u.assoc_resp));
+        }
+        if (assoc_resp->req_ie_len)
+        {
+            event.assoc_info.req_ies     = (unsigned char *)req_frame;
+            event.assoc_info.req_ies_len = assoc_resp->req_ie_len;
+        }
+    }
+
+    wifi_if_ctx_rtos->supp_callbk_fns.assoc_resp(wifi_if_ctx_rtos->supp_drv_if_ctx, &event, status);
+}
+
+void wifi_nxp_wpa_supp_event_proc_deauth(void *if_priv, nxp_wifi_event_mlme_t *deauth, unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+    const struct ieee80211_mgmt *mgmt = NULL;
+    const unsigned char *frame        = NULL;
+    unsigned int frame_len            = 0;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    frame     = (const unsigned char *)deauth->frame.frame;
+    frame_len = deauth->frame.frame_len;
+    mgmt      = (const struct ieee80211_mgmt *)frame;
+
+    if (frame_len < 24 + sizeof(mgmt->u.deauth))
+    {
+        supp_e("%s: Deauthentication response frame too short", __func__);
+        return;
+    }
+
+    memset(&event, 0, sizeof(event));
+
+    event.deauth_info.addr        = &mgmt->sa[0];
+    event.deauth_info.reason_code = le_to_host16(WLAN_REASON_DEAUTH_LEAVING);
+    if (frame + frame_len > mgmt->u.deauth.variable)
+    {
+        event.deauth_info.ie     = mgmt->u.deauth.variable;
+        event.deauth_info.ie_len = (frame + frame_len - mgmt->u.deauth.variable);
+    }
+
+    (void)wifi_event_completion(WIFI_EVENT_DEAUTHENTICATION, le_to_host16(mgmt->u.deauth.reason_code), NULL);
+
+    wifi_if_ctx_rtos->supp_callbk_fns.deauth(wifi_if_ctx_rtos->supp_drv_if_ctx, &event, mgmt);
+}
+
+void wifi_nxp_wpa_supp_event_proc_disassoc(void *if_priv, nxp_wifi_event_mlme_t *disassoc, unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+    const struct ieee80211_mgmt *mgmt = NULL;
+    const unsigned char *frame        = NULL;
+    unsigned int frame_len            = 0;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    frame     = (const unsigned char *)disassoc->frame.frame;
+    frame_len = disassoc->frame.frame_len;
+    mgmt      = (const struct ieee80211_mgmt *)frame;
+
+    if (frame_len < 24 + sizeof(mgmt->u.disassoc))
+    {
+        supp_e("%s: Dis-association response frame too short", __func__);
+        return;
+    }
+
+    memset(&event, 0, sizeof(event));
+
+    event.disassoc_info.addr        = &mgmt->sa[0];
+    event.disassoc_info.reason_code = le_to_host16(mgmt->u.disassoc.reason_code);
+    if (frame + frame_len > mgmt->u.disassoc.variable)
+    {
+        event.disassoc_info.ie     = mgmt->u.disassoc.variable;
+        event.disassoc_info.ie_len = (frame + frame_len - mgmt->u.disassoc.variable);
+    }
+
+    wifi_if_ctx_rtos->supp_callbk_fns.disassoc(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+}
+
+void wifi_nxp_wpa_supp_event_proc_remain_on_channel(void *if_priv, int cancel_channel)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    wifi_if_ctx_rtos                           = (struct wifi_nxp_ctx_rtos *)if_priv;
+    union wpa_event_data event;
+    os_memset(&event, 0, sizeof(event));
+    event.remain_on_channel.freq     = wifi_if_ctx_rtos->remain_on_channel_freq;
+    event.remain_on_channel.duration = wifi_if_ctx_rtos->remain_on_channel_duration;
+    wifi_if_ctx_rtos->supp_callbk_fns.remain_on_channel(wifi_if_ctx_rtos->supp_drv_if_ctx, cancel_channel, &event);
+}
+
+void *wifi_nxp_wpa_supp_dev_init(void *supp_drv_if_ctx,
+                                 const char *iface_name,
+                                 rtos_wpa_supp_dev_callbk_fns *supp_callbk_fns)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    const struct netif *iface = NULL;
+
+#ifdef __ZEPHYR__
+    iface = net_if_get_binding(iface_name);
+#else
+    LOCK_TCPIP_CORE();
+    iface = netif_find(iface_name);
+    UNLOCK_TCPIP_CORE();
+#endif
+
+    if (!iface)
+    {
+        supp_e("%s: Interface %s not found", __func__, iface_name);
+        return NULL;
+    }
+
+    if (strstr(iface_name, "ml"))
+        wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.if_priv;
+    else
+        wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.hapd_if_priv;
+
+    if (!wifi_if_ctx_rtos)
+    {
+        supp_e("%s: Interface %s not properly initialized", __func__, iface_name);
+        return NULL;
+    }
+
+    memset(wifi_if_ctx_rtos, 0x00, sizeof(struct wifi_nxp_ctx_rtos));
+
+    wifi_if_ctx_rtos->iface_ctx       = iface;
+    wifi_if_ctx_rtos->supp_drv_if_ctx = supp_drv_if_ctx;
+
+    if (strstr(iface_name, "ml"))
+    {
+        wifi_if_ctx_rtos->bss_type = BSS_TYPE_STA;
+    }
+    else
+    {
+        wifi_if_ctx_rtos->bss_type = BSS_TYPE_UAP;
+    }
+    wifi_if_ctx_rtos->last_mgmt_tx_data = (uint8_t *)OSA_MemoryAllocate(MAX_MGMT_TX_FRAME_SIZE);
+
+    if (!wifi_if_ctx_rtos->last_mgmt_tx_data)
+    {
+        supp_e("%s: Buffer to store mgmt tx failed", __func__);
+        return NULL;
+    }
+
+    memcpy(&wifi_if_ctx_rtos->supp_callbk_fns, supp_callbk_fns, sizeof(wifi_if_ctx_rtos->supp_callbk_fns));
+    return wifi_if_ctx_rtos;
+}
+
+void wifi_nxp_wpa_supp_dev_deinit(void *if_priv)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (wifi_if_ctx_rtos != NULL)
+    {
+        if (wifi_if_ctx_rtos->last_mgmt_tx_data != NULL)
+        {
+            OSA_MemoryFree(wifi_if_ctx_rtos->last_mgmt_tx_data);
+        }
+        memset(wifi_if_ctx_rtos, 0x00, sizeof(struct wifi_nxp_ctx_rtos));
+    }
+}
+
+static void wifi_nxp_sort_channels(t_u8 channels[], unsigned char num_chans)
+{
+    t_u8 i, j;
+
+    /* Bubble sort */
+    for (i = 0; i < num_chans; i++)
+    {
+        for (j = 1; j < num_chans - i; j++)
+        {
+            if ((t_u8)channels[j - 1] > (t_u8)channels[j])
+            {
+                SWAP_U8(channels[j - 1], channels[j]);
+            }
+        }
+    }
+}
+
+int wifi_nxp_wpa_supp_scan2(void *if_priv, struct wpa_driver_scan_params *params)
+{
+    int status                                 = -WM_FAIL;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                                    = -1;
+    int i                                      = 0;
+    unsigned char num_chans                    = 0;
+    t_u8 bss_mode                              = BSS_INFRASTRUCTURE;
+    const char *ssid = NULL, *ssid2 = NULL;
+    char ssid_v[(MLAN_MAX_SSID_LENGTH + 1) * MRVDRV_MAX_SSID_LIST_LENGTH] = {0};
+    const t_u8 *bssid                                                     = NULL;
+    wifi_scan_channel_list_t *chan_list                                   = NULL;
+    t_u8 channels[WIFI_SCAN_MAX_NUM_CHAN]                                 = {0};
+    mlan_scan_type scan_type                                              = MLAN_SCAN_TYPE_ACTIVE;
+
+    if (!if_priv || !params)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (wifi_if_ctx_rtos->scan_in_progress)
+    {
+        supp_d("%s: Scan already in progress", __func__);
+        ret = -EBUSY;
+        goto out;
+    }
+
+    if (wifi_is_remain_on_channel())
+    {
+        supp_e("%s: Block scan while remaining on channel", __func__);
+        ret = -EBUSY;
+        goto out;
+    }
+
+    wifi_d("initiating wifi-scan");
+
+    if (params->freqs)
+    {
+        for (i = 0; params->freqs[i] && i < WIFI_SCAN_MAX_NUM_CHAN; i++)
+        {
+            channels[i] = freq_to_chan(params->freqs[i]);
+        }
+
+        num_chans = i;
+    }
+    else
+    {
+        num_chans = 0;
+    }
+    uint8_t ssid_off = 0;
+    for (i = 0; i < params->num_ssids; i++)
+    {
+        memcpy(ssid_v + ssid_off, (const char *)params->ssids[i].ssid, params->ssids[i].ssid_len);
+        ssid_off += params->ssids[i].ssid_len;
+        ssid_v[ssid_off] = '\0';
+        ssid_off++;
+    }
+    ssid = (const char *)&ssid_v;
+#if 0
+#if CONFIG_COMBO_SCAN
+    if (params->num_filter_ssids > 1)
+    {
+        if (params->filter_ssids[1].ssid_len)
+        {
+            memcpy(ssid_v2, (const char *)params->filter_ssids[1].ssid, params->filter_ssids[1].ssid_len);
+            ssid2 = (const char *)&ssid_v2;
+        }
+    }
+#endif
+#endif
+    /*
+     * no ssids means passive scan
+     * refer to woal_cfg80211_scan
+     */
+    if (!params->num_ssids)
+    {
+        scan_type = MLAN_SCAN_TYPE_PASSIVE;
+    }
+
+    bssid = params->bssid;
+
+    if (num_chans != 0)
+    {
+        chan_list = OSA_MemoryAllocate(sizeof(wifi_scan_channel_list_t) * num_chans);
+
+        if (chan_list != NULL)
+        {
+            wifi_nxp_sort_channels(channels, num_chans);
+            for (i = 0; i < num_chans; i++)
+            {
+                chan_list[i].chan_number = channels[i];
+                chan_list[i].scan_type   = scan_type;
+                chan_list[i].scan_time   = 100;
+            }
+        }
+    }
+
+    if (params->extra_ies_len)
+    {
+        status = wifi_set_scan_ies((void *)params->extra_ies, params->extra_ies_len);
+
+        if (status != WM_SUCCESS)
+        {
+            wifi_d("wifi set scan IEs failed");
+            goto out;
+        }
+    }
+
+    wm_wifi.external_scan = false;
+    wm_wifi.wpa_supp_scan = true;
+
+#if CONFIG_HOSTAPD
+    wm_wifi.hostapd_op = false;
+
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wm_wifi.hostapd_op = true;
+    }
+#endif
+
+    status = wifi_send_scan_cmd(bss_mode, bssid, ssid, params->num_ssids, num_chans, chan_list, 0,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                                params->filter_rssi,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                                50U,
+#endif
+                                false, false);
+    if (status != WM_SUCCESS)
+    {
+        wifi_d("wifi send scan cmd failed");
+        goto out;
+    }
+
+    wifi_if_ctx_rtos->scan_in_progress = true;
+    ret                                = 0;
+out:
+    if (chan_list != NULL)
+    {
+        OSA_MemoryFree((void *)chan_list);
+    }
+
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_set_default_scan_ies(void *priv, const u8 *ies, size_t ies_len)
+{
+    int ret = -1;
+
+    if ((!priv) || (!ies))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    ret = wifi_nxp_set_default_scan_ies(ies, ies_len);
+
+    if (ret != WM_SUCCESS)
+    {
+        supp_e("%s: Default scan ies set failed", __func__);
+    }
+    else
+    {
+        supp_d("%s: Default scan ies set successfully", __func__);
+    }
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_sched_scan(void *if_priv, struct wpa_driver_scan_params *params)
+{
+    int status = -WM_FAIL;
+    // struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret = -1;
+    int i   = 0;
+    nxp_wifi_trigger_sched_scan_t *wifi_sched_scan_params;
+
+    if (!if_priv || !params)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    // wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    wifi_sched_scan_params = (nxp_wifi_trigger_sched_scan_t *)OSA_MemoryAllocate(sizeof(nxp_wifi_trigger_sched_scan_t));
+
+    if (!wifi_sched_scan_params)
+    {
+        supp_e("%s:  wifi sched scan params calloc failed", __func__);
+        goto out;
+    }
+
+    if (params->num_ssids != 0U)
+    {
+        wifi_sched_scan_params->num_ssids = MIN(WIFI_SCAN_MAX_NUM_SSIDS, params->num_ssids);
+
+        for (i = 0; i < wifi_sched_scan_params->num_ssids; i++)
+        {
+            memcpy(wifi_sched_scan_params->scan_ssids[i].ssid, (const unsigned char *)params->ssids[i].ssid,
+                   params->ssids[i].ssid_len);
+
+            wifi_sched_scan_params->scan_ssids[i].ssid_len = params->ssids[i].ssid_len;
+        }
+    }
+
+    for (i = 0; params->freqs[i] && i < WIFI_SCAN_MAX_NUM_CHAN; i++)
+    {
+        wifi_sched_scan_params->chan_list[i] = freq_to_chan(params->freqs[i]);
+    }
+
+    wifi_sched_scan_params->num_chans = i;
+
+    if ((params->extra_ies) && (params->extra_ies_len))
+    {
+        memcpy(wifi_sched_scan_params->extra_ies.ie, params->extra_ies, params->extra_ies_len);
+        wifi_sched_scan_params->extra_ies.ie_len = params->extra_ies_len;
+    }
+
+    wifi_sched_scan_params->chan_per_scan = MIN(WLAN_BG_SCAN_CHAN_MAX, wifi_sched_scan_params->num_chans);
+
+    wifi_sched_scan_params->scan_interval = MIN_BGSCAN_INTERVAL;
+    wifi_sched_scan_params->repeat_count  = 2;
+
+    wifi_sched_scan_params->report_condition = BG_SCAN_SSID_MATCH | BG_SCAN_WAIT_ALL_CHAN_DONE;
+
+    wifi_sched_scan_params->filter_rssi = params->filter_rssi;
+
+    status = wifi_send_sched_scan_cmd(wifi_sched_scan_params);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: Sched Scan trigger failed", __func__);
+        goto out;
+    }
+    ret = 0;
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_stop_sched_scan(void *if_priv)
+{
+    int status = WM_SUCCESS;
+    int ret    = -1;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    status = wifi_send_stop_sched_scan_cmd();
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi_supp_stop_sched_scan failed", __func__);
+        goto out;
+    }
+    ret = 0;
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_scan_abort(void *if_priv)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int status                                 = -WM_FAIL;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (!wifi_if_ctx_rtos || (!wifi_if_ctx_rtos->scan_in_progress))
+    {
+        supp_d("%s:Ignore scan abort, no scan in progress", __func__);
+        goto out;
+    }
+
+    wlan_abort_split_scan();
+
+    status = WM_SUCCESS;
+
+out:
+    return status;
+}
+
+struct wpa_scan_res *wifi_nxp_wpa_supp_proc_scan_res(nxp_wifi_event_new_scan_result_t *scan_res,
+                                                     struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos)
+{
+    struct wpa_scan_res *r  = NULL;
+    const unsigned char *ie = NULL;
+    unsigned int ie_len     = 0;
+    unsigned char *pos      = NULL;
+
+    if (scan_res->ies.ie_len != 0U)
+    {
+        ie     = (const unsigned char *)scan_res->ies.ie;
+        ie_len = scan_res->ies.ie_len;
+    }
+
+    r = (struct wpa_scan_res *)OSA_MemoryAllocate(sizeof(*r) + ie_len);
+
+    if (!r)
+    {
+        supp_e("%s: Unable to calloc  memory for scan result\n", __func__);
+        if (ie)
+        {
+            OSA_MemoryFree((void *)ie);
+        }
+        return NULL;
+    }
+
+    memcpy(r->bssid, scan_res->mac_addr, ETH_ALEN);
+
+    r->freq = scan_res->frequency;
+
+    r->beacon_int = scan_res->beacon_interval;
+
+    r->caps = scan_res->capability;
+
+    if (scan_res->noise == 0)
+    {
+        r->flags |= WPA_SCAN_NOISE_INVALID;
+    }
+    else
+    {
+        r->noise = scan_res->noise;
+    }
+
+    r->level = scan_res->rssi;
+
+    r->flags |= WPA_SCAN_LEVEL_DBM | WPA_SCAN_QUAL_INVALID;
+
+    (void)memcpy((void *)&r->tsf, (const void *)&scan_res->ies_tsf, sizeof(r->tsf));
+
+    if (scan_res->beacon_ies_tsf > r->tsf)
+    {
+        (void)memcpy((void *)&r->tsf, (const void *)&scan_res->beacon_ies_tsf, sizeof(r->tsf));
+    }
+
+    if (scan_res->seen_ms_ago)
+    {
+        r->age = scan_res->seen_ms_ago;
+    }
+
+    (void)memcpy((void *)&r->parent_tsf, (const void *)&scan_res->ies_tsf, sizeof(r->parent_tsf));
+
+    memcpy(r->tsf_bssid, wifi_if_ctx_rtos->scan_start_tsf_bssid, ETH_ALEN);
+
+    r->ie_len = ie_len;
+
+    pos = (unsigned char *)(r + 1);
+
+    if (ie_len)
+    {
+        memcpy(pos, ie, ie_len);
+
+        pos += ie_len;
+
+        OSA_MemoryFree((void *)ie);
+    }
+
+    if (scan_res->status)
+    {
+        r->flags |= WPA_SCAN_ASSOCIATED;
+    }
+
+    return r;
+}
+
+int wifi_nxp_wpa_supp_scan_results_get(void *if_priv, struct wpa_scan_results *scan_res2)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+    int ret                                    = -1;
+    unsigned int i, num;
+    nxp_wifi_event_new_scan_result_t scan_res;
+    struct wpa_scan_res *sr = NULL;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    num = wifi_nxp_scan_res_num();
+
+    if (num == 0)
+    {
+        supp_d("%s: No networks found", __func__);
+        goto done;
+    }
+
+    scan_res2->res = (struct wpa_scan_res **)OSA_MemoryAllocate(num * sizeof(struct wpa_scan_res *));
+    if (!scan_res2->res)
+    {
+        supp_e("%s: Failed to calloc scan result array", __func__);
+        goto out;
+    }
+
+    for (i = 0; i < num; i++)
+    {
+        memset(&scan_res, 0, sizeof(nxp_wifi_event_new_scan_result_t));
+        (void)wifi_nxp_scan_res_get2(i, &scan_res);
+
+        sr = wifi_nxp_wpa_supp_proc_scan_res(&scan_res, wifi_if_ctx_rtos);
+
+        if (sr)
+        {
+            scan_res2->res[scan_res2->num++] = sr;
+        }
+    }
+
+done:
+    ret = 0;
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_survey_results_get(void *if_priv)
+{
+    int status                                 = WM_SUCCESS;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                                    = -1;
+    nxp_wifi_trigger_op_t *wifi_survey_params;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    wifi_survey_params = (nxp_wifi_trigger_op_t *)OSA_MemoryAllocate(sizeof(nxp_wifi_trigger_op_t));
+
+    if (!wifi_survey_params)
+    {
+        supp_e("%s:  wifi survey params calloc failed", __func__);
+        goto out;
+    }
+
+    wifi_survey_params->hostapd = wifi_if_ctx_rtos->hostapd;
+
+    status = wifi_event_completion(WIFI_EVENT_SURVEY_RESULT_GET, WIFI_EVENT_REASON_SUCCESS, wifi_survey_params);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi_supp_survey_res_get failed", __func__);
+        OSA_MemoryFree(wifi_survey_params);
+        goto out;
+    }
+    ret = 0;
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_deauthenticate(void *if_priv, const char *addr, unsigned short reason_code)
+{
+    int status = -WM_FAIL;
+    int ret    = -1;
+
+    if ((!if_priv) || (!addr))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_d("initiating wifi-deauth");
+
+    status = wifi_nxp_deauthenticate(MLAN_BSS_TYPE_STA, (const unsigned char *)addr, reason_code);
+#if CONFIG_11MC
+    g_ftm_civic_cfg.civic_req  = 0;
+    g_ftm_location_cfg.lci_req = 0;
+#endif
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi_nxp_wpa_supp_deauthenticate failed", __func__);
+        goto out;
+    }
+    ret = 0;
+out:
+    return ret;
+}
+
+#if 0
+int wifi_nxp_wpa_supp_add_key(struct nxp_wifi_umac_key_info *key_info, enum wpa_alg alg,
+			      int key_idx,
+			      int defkey, const unsigned char *seq, size_t seq_len,
+			      const unsigned char *key, size_t key_len)
+{
+	unsigned int suite = 0;
+
+	suite = wpa_alg_to_cipher_suite(alg, key_len);
+
+	if (!suite) {
+		return -1;
+	}
+
+	if (defkey && alg == WPA_ALG_BIP_CMAC_128) {
+		key_info->nxp_wifi_flags = NXP_WIFI_KEY_DEFAULT_MGMT;
+	} else if (defkey) {
+		key_info->nxp_wifi_flags = NXP_WIFI_KEY_DEFAULT;
+	}
+
+	key_info->key_idx = key_idx;
+	key_info->cipher_suite = suite;
+
+	if (key && key_len) {
+		memcpy(key_info->key.nxp_wifi_key, key, key_len);
+		key_info->key.nxp_wifi_key_len = key_len;
+	}
+	if (seq && seq_len) {
+		memcpy(key_info->seq.nxp_wifi_seq, seq, seq_len);
+		key_info->seq.nxp_wifi_seq_len = seq_len;
+	}
+
+	return 0;
+}
+#endif
+
+int wifi_nxp_wpa_supp_authenticate(void *if_priv, struct wpa_driver_auth_params *params, struct wpa_bss *curr_bss)
+{
+    int status         = -WM_FAIL;
+    unsigned char *pos = NULL;
+    unsigned char auth_alg;
+    unsigned char auth_trans_num[2] = {1, 0};
+    unsigned char status_code[2]    = {0, 0};
+    int ret                         = -1;
+    unsigned short len              = 0;
+    int channel;
+
+    if ((!if_priv) || (!params))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    auth_alg = get_algo_from_auth_type(params->auth_alg);
+
+    if (params->auth_alg == WPA_AUTH_ALG_FT)
+    {
+        pos = (unsigned char *)params->ie;
+        len = params->ie_len;
+    }
+    else if ((params->auth_data != NULL) && (params->auth_data_len >= 4))
+    {
+        pos = (unsigned char *)params->auth_data;
+
+        auth_trans_num[0] = pos[0];
+        auth_trans_num[1] = pos[1];
+        status_code[0]    = pos[2];
+        status_code[1]    = pos[3];
+        pos += 4;
+        len = params->auth_data_len - 4;
+    }
+
+    channel = freq_to_chan(params->freq);
+
+    wifi_d("initiating wifi-auth");
+
+    status = wifi_send_mgmt_auth_request(channel, auth_alg, auth_trans_num, status_code, params->bssid,
+                                         (const unsigned char *)pos, len);
+
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: MLME command failed (auth): ret=%d", __func__, ret);
+        ret = -1;
+    }
+    else
+    {
+        supp_d("%s:Authentication request sent successfully", __func__);
+        ret = 0;
+    }
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_associate(void *if_priv, struct wpa_driver_associate_params *params)
+{
+    int status                                 = -WM_FAIL;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    nxp_wifi_assoc_info_t *assoc_params;
+    int ret = -1;
+
+    if ((!if_priv) || (!params))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    assoc_params = (nxp_wifi_assoc_info_t *)OSA_MemoryAllocate(sizeof(nxp_wifi_assoc_info_t));
+
+    if (!assoc_params)
+    {
+        supp_e("%s: assoc params calloc failed", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos->associated = false;
+
+    if (params->auth_alg & WPA_AUTH_ALG_FT)
+    {
+        assoc_params->is_ft = true;
+    }
+
+    if (params->bssid)
+    {
+        memcpy(&wifi_if_ctx_rtos->attempt_bssid, params->bssid, ETH_ALEN);
+
+        memcpy(assoc_params->bssid, params->bssid, sizeof(assoc_params->bssid));
+    }
+
+    if (params->prev_bssid)
+    {
+        memcpy(assoc_params->prev_bssid, params->prev_bssid, sizeof(assoc_params->prev_bssid));
+    }
+
+    if (params->freq.freq)
+    {
+        int channel           = freq_to_chan(params->freq.freq);
+        assoc_params->channel = channel;
+
+        wifi_if_ctx_rtos->assoc_freq = params->freq.freq;
+    }
+    else
+    {
+        wifi_if_ctx_rtos->assoc_freq = 0;
+    }
+
+    if (params->ssid)
+    {
+        assoc_params->ssid.ssid_len = params->ssid_len;
+
+        memcpy(assoc_params->ssid.ssid, params->ssid, params->ssid_len);
+    }
+
+    if (params->wpa_ie)
+    {
+        assoc_params->wpa_ie.ie_len = params->wpa_ie_len;
+        memcpy(assoc_params->wpa_ie.ie, params->wpa_ie, params->wpa_ie_len);
+    }
+
+    assoc_params->control_port = 1;
+
+    wifi_d("initiating wifi-assoc");
+
+    status = wifi_nxp_send_assoc(assoc_params);
+
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: MLME command failed (assoc)", __func__);
+    }
+    else
+    {
+        supp_d("%s: Association request sent successfully", __func__);
+        ret = 0;
+    }
+    OSA_MemoryFree((void *)assoc_params);
+
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_set_key(void *if_priv,
+                              const unsigned char *ifname,
+                              enum wpa_alg alg,
+                              const unsigned char *addr,
+                              int key_idx,
+                              int set_tx,
+                              const unsigned char *seq,
+                              size_t seq_len,
+                              const unsigned char *key,
+                              size_t key_len,
+                              enum key_flag key_flag)
+
+{
+    int status                                 = -WM_FAIL;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    unsigned int flags                         = 0;
+    int ret                                    = -1;
+    bool is_pairwise                           = false;
+    int skip_set_key                           = 1;
+
+    if ((!if_priv) || (!ifname))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+    if ((key_flag & KEY_FLAG_PAIRWISE_MASK) == KEY_FLAG_PAIRWISE_RX_TX_MODIFY)
+    {
+        supp_d("SET_KEY (pairwise RX/TX modify)");
+    }
+    else if (alg == WPA_ALG_NONE && (key_flag & KEY_FLAG_RX_TX))
+    {
+        supp_d("%s: invalid key_flag to delete key", __func__);
+        ret = -1;
+        goto out;
+    }
+    else if (alg == WPA_ALG_NONE)
+    {
+        supp_d("DEL_KEY");
+
+        status = wifi_remove_key(wifi_if_ctx_rtos->bss_type, is_pairwise, key_idx, addr);
+
+        if (status != WM_SUCCESS)
+        {
+            supp_e("%s: wifi_nxp_del_key failed", __func__);
+        }
+        else
+        {
+            ret = 0;
+        }
+    }
+    else
+    {
+        flags = wpa_alg_to_cipher_suite(alg, key_len);
+
+        /* TODO: Implement/check set_tx */
+        if (addr && !is_broadcast_ether_addr(addr))
+        {
+            is_pairwise = true;
+            if ((key_flag & KEY_FLAG_PAIRWISE_MASK) == KEY_FLAG_PAIRWISE_RX ||
+                (key_flag & KEY_FLAG_PAIRWISE_MASK) == KEY_FLAG_PAIRWISE_RX_TX_MODIFY)
+            {
+            }
+            else if ((key_flag & KEY_FLAG_GROUP_MASK) == KEY_FLAG_GROUP_RX)
+            {
+            }
+            else if (!(key_flag & KEY_FLAG_PAIRWISE))
+            {
+                supp_d("   key_flag missing PAIRWISE when setting a pairwise key");
+                ret = -1;
+                goto out;
+            }
+            else if (alg == WPA_ALG_WEP && (key_flag & KEY_FLAG_RX_TX) == KEY_FLAG_RX_TX)
+            {
+                supp_d("   unicast WEP key");
+                skip_set_key = 0;
+            }
+            else
+            {
+                supp_d("   pairwise key");
+            }
+        }
+        else if ((key_flag & KEY_FLAG_PAIRWISE) || !(key_flag & KEY_FLAG_GROUP))
+        {
+            supp_d("   invalid key_flag for a broadcast key");
+            ret = -1;
+            goto out;
+        }
+        else
+        {
+            supp_d("   broadcast key");
+            is_pairwise = false;
+            if (key_flag & KEY_FLAG_DEFAULT)
+                skip_set_key = 0;
+        }
+
+        status =
+            wifi_set_key(wifi_if_ctx_rtos->bss_type, is_pairwise, key_idx, key, key_len, seq, seq_len, addr, flags);
+
+        if (status != WM_SUCCESS)
+        {
+            supp_e("%s: wifi_set_key failed", __func__);
+        }
+        else
+        {
+            ret = 0;
+        }
+
+        if (ret || skip_set_key)
+            return ret;
+    }
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_del_key(void *if_priv, const unsigned char *addr, int key_idx)
+
+{
+    int status                                 = -WM_FAIL;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                                    = -1;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    status = wifi_remove_key(wifi_if_ctx_rtos->bss_type, 0, key_idx, addr);
+
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi_nxp_del_key failed", __func__);
+    }
+    else
+    {
+        ret = 0;
+    }
+
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_set_rekey_info(
+    void *if_priv, const u8 *kek, size_t kek_len, const u8 *kck, size_t kck_len, const u8 *replay_ctr)
+{
+    int status                                 = -WM_FAIL;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                                    = -1;
+
+    if ((!if_priv) || (!kek) || (!kck) || (!replay_ctr))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    status = wifi_set_rekey_info(wifi_if_ctx_rtos->bss_type, kek, kek_len, kck, kck_len, replay_ctr);
+
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi_set_rekey_info failed", __func__);
+        goto out;
+    }
+    else
+    {
+        ret = 0;
+    }
+
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_set_supp_port(void *if_priv, int authorized, char *bssid)
+{
+    int ret                                    = -1;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    if ((!if_priv) || (!bssid))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    wifi_d("initiating wifi-set-port authorized: %d", authorized);
+
+    if (wifi_if_ctx_rtos->associated)
+    {
+#if CONFIG_WPA_SUPP_WPS
+        if (!wifi_nxp_wps_session_enable())
+        {
+#endif
+            if (authorized)
+            {
+                (void)wifi_event_completion(WIFI_EVENT_AUTHENTICATION, WIFI_EVENT_REASON_SUCCESS, NULL);
+            }
+#if CONFIG_WPA_SUPP_WPS
+        }
+#endif
+    }
+
+    ret = 0;
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_set_country(void *if_priv, const char *alpha2)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                                    = -WM_FAIL;
+    char *country                              = NULL;
+
+    country = OSA_MemoryAllocate(COUNTRY_CODE_LEN);
+    (void)memcpy(country, alpha2, COUNTRY_CODE_LEN - 1);
+
+    if ((!if_priv) || (!alpha2))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+    ret              = wifi_nxp_set_country(wifi_if_ctx_rtos->bss_type, alpha2);
+
+    if (ret == WM_SUCCESS)
+    {
+        (void)wifi_event_completion(WIFI_EVENT_REGION_POWER_CFG, WIFI_EVENT_REASON_SUCCESS, (void *)country);
+    }
+
+    return ret;
+
+out:
+    return -1;
+}
+
+int wifi_nxp_wpa_supp_get_country(void *if_priv, char *alpha2)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    if ((!if_priv) || (!alpha2))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    return wifi_nxp_get_country(wifi_if_ctx_rtos->bss_type, alpha2);
+
+out:
+    return -1;
+}
+
+int wifi_nxp_wpa_supp_signal_poll(void *if_priv, struct wpa_signal_info *si, unsigned char *bssid)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                                    = -WM_FAIL;
+    nxp_wifi_signal_info_t signal_params;
+
+    if (!if_priv || !si || !bssid)
+    {
+        supp_e("%s: Invalid params\r\n", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    ret = wifi_nxp_get_signal(wifi_if_ctx_rtos->bss_type, &signal_params);
+    if (ret != WM_SUCCESS)
+    {
+        supp_e("%s: wifi_nxp_get_signal failed", __func__);
+        goto out;
+    }
+
+    memset(si, 0x00, sizeof(struct wpa_signal_info));
+
+    si->frequency         = wifi_if_ctx_rtos->assoc_freq;
+    si->current_signal    = signal_params.current_signal;
+    si->avg_signal        = signal_params.avg_signal;
+    si->avg_beacon_signal = signal_params.avg_beacon_signal;
+    si->current_noise     = signal_params.current_noise;
+
+out:
+    return ret;
+}
+
+void wifi_nxp_wpa_supp_event_acs_channel_selected(void *if_priv, nxp_wifi_acs_params *acs_params)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Missing interface context", __func__);
+        return;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    memset(&event, 0, sizeof(event));
+
+    if (!acs_params)
+    {
+        supp_e("%s: Missing acs params data", __func__);
+        return;
+    }
+
+    event.acs_selected_channels.pri_freq = acs_params->pri_freq;
+    event.acs_selected_channels.sec_freq = acs_params->sec_freq;
+    event.acs_selected_channels.ch_width = acs_params->ch_width;
+    event.acs_selected_channels.hw_mode  = (enum hostapd_hw_mode)acs_params->hw_mode;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.acs_channel_sel(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.acs_channel_sel(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_mgmt_tx_status(void *if_priv, nxp_wifi_event_mlme_t *mlme_event, unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Missing interface context", __func__);
+        return;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (!mlme_event)
+    {
+        supp_e("%s: Missing MLME event data", __func__);
+        return;
+    }
+
+    if (wifi_if_ctx_rtos->mgmt_tx_status == 0U)
+    {
+        supp_d("%s: Only send mgmt tx status", __func__);
+        return;
+    }
+
+    if (wifi_if_ctx_rtos->last_mgmt_tx_data_len && wifi_if_ctx_rtos->mgmt_tx_status)
+    {
+        memcpy((void *)mlme_event->frame.frame, (const void *)wifi_if_ctx_rtos->last_mgmt_tx_data,
+               (size_t)wifi_if_ctx_rtos->last_mgmt_tx_data_len);
+        mlme_event->frame.frame_len             = wifi_if_ctx_rtos->last_mgmt_tx_data_len;
+        wifi_if_ctx_rtos->last_mgmt_tx_data_len = 0;
+        wifi_if_ctx_rtos->mgmt_tx_status        = 0;
+    }
+
+    wifi_if_ctx_rtos->mgmt_tx_status = 0;
+
+    if (mlme_event->frame.frame_len == 0)
+    {
+        supp_d("%s: mgmt tx status frame invalid", __func__);
+        return;
+    }
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.mgmt_tx_status(wifi_if_ctx_rtos->hapd_drv_if_ctx,
+                                                            (const unsigned char *)mlme_event->frame.frame,
+                                                            mlme_event->frame.frame_len, true);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.mgmt_tx_status(wifi_if_ctx_rtos->supp_drv_if_ctx,
+                                                         (const unsigned char *)mlme_event->frame.frame,
+                                                         mlme_event->frame.frame_len, true);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_unprot_mgmt(void *if_priv, nxp_wifi_event_mlme_t *unprot_mgmt, unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+    const struct ieee80211_mgmt *mgmt = NULL;
+    const unsigned char *frame        = NULL;
+    unsigned int frame_len            = 0;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Missing interface context", __func__);
+        return;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    frame     = (const unsigned char *)unprot_mgmt->frame.frame;
+    frame_len = unprot_mgmt->frame.frame_len;
+
+    mgmt = (const struct ieee80211_mgmt *)frame;
+
+    if (frame_len < 24 + sizeof(mgmt->u.deauth))
+    {
+        supp_e("%s: Unprotected mgmt frame too short", __func__);
+        return;
+    }
+
+    memset(&event, 0, sizeof(event));
+
+    event.unprot_deauth.sa = &mgmt->sa[0];
+    event.unprot_deauth.da = &mgmt->da[0];
+
+    //	if (cmd_evnt == NXP_WIFI_EVENT_UNPROT_DEAUTHENTICATE) {
+    event.unprot_deauth.reason_code = le_to_host16(mgmt->u.deauth.reason_code);
+    wifi_if_ctx_rtos->supp_callbk_fns.unprot_deauth(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    //	} else if (cmd_evnt == NXP_WIFI_EVENT_UNPROT_DISASSOCIATE) {
+    event.unprot_disassoc.reason_code = le_to_host16(mgmt->u.deauth.reason_code);
+    wifi_if_ctx_rtos->supp_callbk_fns.unprot_disassoc(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    //	}
+}
+
+int wifi_nxp_wpa_send_mlme(void *if_priv,
+                           const u8 *data,
+                           size_t data_len,
+                           int noack,
+                           unsigned int freq,
+                           int no_cck,
+                           int offchanok,
+                           unsigned int wait_time,
+                           int cookie)
+{
+    int status                                 = -WM_FAIL;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    const struct ieee80211_hdr *hdr;
+    u16 fc, stype;
+
+    hdr   = (const struct ieee80211_hdr *)data;
+    fc    = le_to_host16(hdr->frame_control);
+    stype = WLAN_FC_GET_STYPE(fc);
+
+    if (!if_priv)
+    {
+        supp_e("%s: Missing interface context", __func__);
+        goto out;
+    }
+
+    if (data_len > 1500)
+    {
+        supp_d("%s: Invalid data length", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    wifi_if_ctx_rtos->mgmt_tx_status = 0;
+
+    status = wifi_nxp_send_mlme(wifi_if_ctx_rtos->bss_type, freq_to_chan(freq), wait_time, data, data_len);
+
+    if (status == -WM_FAIL)
+    {
+        wifi_if_ctx_rtos->last_mgmt_tx_data_len = 0;
+        wifi_if_ctx_rtos->mgmt_tx_status        = 0;
+        supp_e("%s: wifi_inject_frame failed", __func__);
+        goto out;
+    }
+
+    if (((wifi_if_ctx_rtos->bss_type == BSS_TYPE_UAP) &&
+         ((stype == WLAN_FC_STYPE_ASSOC_RESP) || (stype == WLAN_FC_STYPE_REASSOC_RESP))) ||
+        (stype == WLAN_FC_STYPE_ACTION))
+    {
+        memcpy((void *)wifi_if_ctx_rtos->last_mgmt_tx_data, (const void *)data, (size_t)data_len);
+        wifi_if_ctx_rtos->last_mgmt_tx_data_len = data_len;
+        wifi_if_ctx_rtos->mgmt_tx_status        = 1;
+    }
+    else
+    {
+        wifi_if_ctx_rtos->last_mgmt_tx_data_len = 0;
+    }
+
+out:
+    return status;
+}
+
+int wifi_nxp_wpa_supp_remain_on_channel(void *if_priv, unsigned int freq, unsigned int duration)
+{
+    int status                                 = -WM_FAIL;
+    int ret                                    = -1;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int channel;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+    if (freq)
+    {
+        wifi_if_ctx_rtos->remain_on_channel_freq = freq;
+    }
+    wifi_if_ctx_rtos->remain_on_channel_duration = duration;
+
+    channel = freq_to_chan(wifi_if_ctx_rtos->remain_on_channel_freq);
+
+    wifi_if_ctx_rtos->supp_called_remain_on_chan = true;
+    wifi_if_ctx_rtos->remain_on_chan_is_canceled = false;
+    status                                       = wifi_remain_on_channel(true, channel, duration);
+
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: Remain on channel cmd failed", __func__);
+        ret = -1;
+    }
+    else
+    {
+        supp_d("%s:Remain on channel sent successfully", __func__);
+        ret = 0;
+    }
+out:
+    return ret;
+}
+
+int wifi_nxp_wpa_supp_cancel_remain_on_channel(void *if_priv)
+{
+    int status                                 = -WM_FAIL;
+    int ret                                    = -1;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+    if (wifi_if_ctx_rtos->remain_on_chan_is_canceled)
+    {
+        supp_d("%s:Already canceled, ignore it", __func__);
+        ret = 0;
+        goto out;
+    }
+
+    wifi_if_ctx_rtos->supp_called_remain_on_chan = true;
+    wifi_if_ctx_rtos->remain_on_chan_is_canceled = true;
+    status                                       = wifi_remain_on_channel(false, 0, 0);
+
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: Cancel on channel cmd failed", __func__);
+        ret = -1;
+    }
+    else
+    {
+        supp_d("%s:Cancel on channel sent successfully", __func__);
+        ret = 0;
+    }
+out:
+    return ret;
+}
+
+void wifi_nxp_wpa_supp_event_proc_mgmt_rx(void *if_priv, nxp_wifi_event_mlme_t *mgmt_rx, unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+    const struct ieee80211_mgmt *mgmt = NULL;
+    const unsigned char *frame        = NULL;
+    unsigned int frame_len            = 0;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    frame     = (const unsigned char *)mgmt_rx->frame.frame;
+    frame_len = mgmt_rx->frame.frame_len;
+    mgmt      = (const struct ieee80211_mgmt *)frame;
+
+    if (frame_len < 4 + (2 * WIFI_ETH_ADDR_LEN))
+    {
+        supp_e("%s: MLME event too short", __func__);
+        return;
+    }
+
+    if (frame_len < 24 + sizeof(mgmt->u.deauth))
+    {
+        supp_e("%s: MGMT RX frame too short", __func__);
+        return;
+    }
+
+    memset(&event, 0, sizeof(event));
+
+    event.rx_mgmt.frame     = (const u8 *)mgmt;
+    event.rx_mgmt.frame_len = frame_len;
+    event.rx_mgmt.freq      = mgmt_rx->frame.freq;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.mgmt_rx(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.mgmt_rx(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_eapol_rx(void *if_priv, nxp_wifi_event_eapol_mlme_t *eapol_rx, unsigned int event_len)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    memset(&event, 0, sizeof(event));
+
+    event.eapol_rx.src      = (const unsigned char *)eapol_rx->mac_addr;
+    event.eapol_rx.data     = (const unsigned char *)eapol_rx->frame.frame;
+    event.eapol_rx.data_len = eapol_rx->frame.frame_len;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.eapol_rx(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.eapol_rx(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_ecsa_complete(void *if_priv, nxp_wifi_ch_switch_info *ch_switch_info)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    memset(&event, 0, sizeof(event));
+
+    event.ch_switch.freq       = ch_switch_info->center_freq;
+    event.ch_switch.ht_enabled = ch_switch_info->ht_enabled;
+    event.ch_switch.ch_offset  = ch_switch_info->ch_offset;
+    event.ch_switch.ch_width   = (enum chan_width)ch_switch_info->ch_width;
+    event.ch_switch.cf1        = ch_switch_info->center_freq1;
+    event.ch_switch.cf2        = ch_switch_info->center_freq2;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.ecsa_complete(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.ecsa_complete(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_dfs_cac_started(void *if_priv, nxp_wifi_dfs_cac_info *dfs_cac_info)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    memset(&event, 0, sizeof(event));
+
+    event.dfs_event.freq        = dfs_cac_info->center_freq;
+    event.dfs_event.ht_enabled  = dfs_cac_info->ht_enabled;
+    event.dfs_event.chan_offset = dfs_cac_info->ch_offset;
+    event.dfs_event.chan_width  = (enum chan_width)dfs_cac_info->ch_width;
+    event.dfs_event.cf1         = dfs_cac_info->center_freq1;
+    event.dfs_event.cf2         = dfs_cac_info->center_freq2;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.dfs_cac_started(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.dfs_cac_started(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void wifi_nxp_wpa_supp_event_proc_dfs_cac_finished(void *if_priv, nxp_wifi_dfs_cac_info *dfs_cac_info)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    union wpa_event_data event;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    memset(&event, 0, sizeof(event));
+
+    event.dfs_event.freq        = dfs_cac_info->center_freq;
+    event.dfs_event.ht_enabled  = dfs_cac_info->ht_enabled;
+    event.dfs_event.chan_offset = dfs_cac_info->ch_offset;
+    event.dfs_event.chan_width  = (enum chan_width)dfs_cac_info->ch_width;
+    event.dfs_event.cf1         = dfs_cac_info->center_freq1;
+    event.dfs_event.cf2         = dfs_cac_info->center_freq2;
+
+#if CONFIG_HOSTAPD
+    if (wifi_if_ctx_rtos->hostapd)
+    {
+        wifi_if_ctx_rtos->hostapd_callbk_fns.dfs_cac_finished(wifi_if_ctx_rtos->hapd_drv_if_ctx, &event);
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos->supp_callbk_fns.dfs_cac_finished(wifi_if_ctx_rtos->supp_drv_if_ctx, &event);
+    }
+}
+
+void *wifi_nxp_hostapd_dev_init(void *hapd_drv_if_ctx,
+                                const char *iface_name,
+                                rtos_hostapd_dev_callbk_fns *hostapd_callbk_fns)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    const struct netif *iface = NULL;
+
+#ifdef __ZEPHYR__
+    iface = net_if_get_binding(iface_name);
+#else
+    LOCK_TCPIP_CORE();
+    iface = netif_find(iface_name);
+    UNLOCK_TCPIP_CORE();
+#endif
+
+    if (!iface)
+    {
+        supp_e("%s: Interface %s not found", __func__, iface_name);
+        return NULL;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.hapd_if_priv;
+
+    if (!wifi_if_ctx_rtos)
+    {
+        supp_e("%s: Interface %s not properly initialized", __func__, iface_name);
+        return NULL;
+    }
+
+    memset(wifi_if_ctx_rtos, 0x00, sizeof(struct wifi_nxp_ctx_rtos));
+
+    wifi_if_ctx_rtos->iface_ctx = iface;
+
+    wifi_if_ctx_rtos->hostapd = true;
+
+    wifi_if_ctx_rtos->bss_type = BSS_TYPE_UAP;
+
+    wifi_if_ctx_rtos->hapd_drv_if_ctx = hapd_drv_if_ctx;
+
+    wifi_if_ctx_rtos->last_mgmt_tx_data = (uint8_t *)OSA_MemoryAllocate(MAX_MGMT_TX_FRAME_SIZE);
+
+    if (!wifi_if_ctx_rtos->last_mgmt_tx_data)
+    {
+        supp_e("%s: Buffer to store mgmt tx failed", __func__);
+        return NULL;
+    }
+
+    memcpy(&wifi_if_ctx_rtos->hostapd_callbk_fns, hostapd_callbk_fns, sizeof(wifi_if_ctx_rtos->hostapd_callbk_fns));
+
+    return wifi_if_ctx_rtos;
+}
+
+void wifi_nxp_hostapd_dev_deinit(void *if_priv)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (wifi_if_ctx_rtos != NULL)
+    {
+        OSA_MemoryFree((void *)wifi_if_ctx_rtos->last_mgmt_tx_data);
+        memset(wifi_if_ctx_rtos, 0x00, sizeof(struct wifi_nxp_ctx_rtos));
+    }
+}
+
+int wifi_nxp_hostapd_set_modes(void *if_priv, struct hostapd_hw_modes *modes)
+{
+    int status     = -WM_FAIL;
+    t_u8 bandwidth = wifi_uap_get_bandwidth();
+
+    if ((!if_priv) || (!modes))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    status = wifi_setup_ht_cap(&modes[HOSTAPD_MODE_IEEE80211G].ht_capab, &modes[HOSTAPD_MODE_IEEE80211G].mcs_set[0],
+                               &modes[HOSTAPD_MODE_IEEE80211G].a_mpdu_params, 0);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi nxp set 2G infra ht cap failed", __func__);
+        goto out;
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if (!ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        status = wifi_setup_ht_cap(&modes[HOSTAPD_MODE_IEEE80211A].ht_capab, &modes[HOSTAPD_MODE_IEEE80211A].mcs_set[0],
+                                   &modes[HOSTAPD_MODE_IEEE80211A].a_mpdu_params, 1);
+        if (status != WM_SUCCESS)
+        {
+            supp_e("%s: wifi nxp set 5G infra ht cap failed", __func__);
+            goto out;
+        }
+    }
+#endif
+
+    modes[HOSTAPD_MODE_IEEE80211G].flags |= HOSTAPD_MODE_FLAG_HT_INFO_KNOWN;
+#if CONFIG_5GHz_SUPPORT
+    if (!ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        modes[HOSTAPD_MODE_IEEE80211A].flags |= HOSTAPD_MODE_FLAG_HT_INFO_KNOWN;
+    }
+#endif
+
+#if CONFIG_11AC
+    status = wifi_setup_vht_cap((t_u32 *)&modes[HOSTAPD_MODE_IEEE80211G].vht_capab,
+                                modes[HOSTAPD_MODE_IEEE80211G].vht_mcs_set, 0);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi nxp set 2G infra vht cap failed", __func__);
+        goto out;
+    }
+
+#if CONFIG_5GHz_SUPPORT
+    if (!ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        status = wifi_setup_vht_cap((t_u32 *)&modes[HOSTAPD_MODE_IEEE80211A].vht_capab,
+                                    modes[HOSTAPD_MODE_IEEE80211A].vht_mcs_set, 1);
+        if (status != WM_SUCCESS)
+        {
+            supp_e("%s: wifi nxp set 5G infra vht cap failed", __func__);
+            goto out;
+        }
+    }
+#endif
+
+    modes[HOSTAPD_MODE_IEEE80211G].flags |= HOSTAPD_MODE_FLAG_VHT_INFO_KNOWN;
+#if CONFIG_5GHz_SUPPORT
+    if (!ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        modes[HOSTAPD_MODE_IEEE80211A].flags |= HOSTAPD_MODE_FLAG_VHT_INFO_KNOWN;
+    }
+#endif
+#endif
+
+#if CONFIG_11AX
+    if (IS_FW_SUPPORT_11AX(mlan_adap))
+    {
+        status = wifi_setup_he_cap(
+            (nxp_wifi_he_capabilities *)&modes[HOSTAPD_MODE_IEEE80211G].he_capab[IEEE80211_MODE_INFRA], 0);
+        if (status != WM_SUCCESS)
+        {
+            supp_e("%s: wifi nxp set 2G infra he cap failed", __func__);
+            goto out;
+        }
+
+        status = wifi_setup_he_cap(
+            (nxp_wifi_he_capabilities *)&modes[HOSTAPD_MODE_IEEE80211G].he_capab[IEEE80211_MODE_AP], 0);
+        if (status != WM_SUCCESS)
+        {
+            supp_e("%s: wifi nxp set 2G ap he cap failed", __func__);
+            goto out;
+        }
+        if (bandwidth == BANDWIDTH_20MHZ)
+        {
+            modes[HOSTAPD_MODE_IEEE80211G].he_capab[IEEE80211_MODE_AP].phy_cap[HE_PHYCAP_CHANNEL_WIDTH_SET_IDX] = 0;
+        }
+#if CONFIG_5GHz_SUPPORT
+        if (!ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+        {
+            status = wifi_setup_he_cap(
+                (nxp_wifi_he_capabilities *)&modes[HOSTAPD_MODE_IEEE80211A].he_capab[IEEE80211_MODE_INFRA], 1);
+            if (status != WM_SUCCESS)
+            {
+                supp_e("%s: wifi nxp set 5G infra he cap failed", __func__);
+                goto out;
+            }
+
+            status = wifi_setup_he_cap(
+                (nxp_wifi_he_capabilities *)&modes[HOSTAPD_MODE_IEEE80211A].he_capab[IEEE80211_MODE_AP], 1);
+            if (status != WM_SUCCESS)
+            {
+                supp_e("%s: wifi nxp set 5G ap he cap failed", __func__);
+                goto out;
+            }
+        }
+        if (bandwidth == BANDWIDTH_20MHZ)
+        {
+            modes[HOSTAPD_MODE_IEEE80211A].he_capab[IEEE80211_MODE_AP].phy_cap[HE_PHYCAP_CHANNEL_WIDTH_SET_IDX] = 0;
+        }
+#endif
+    }
+#endif
+
+    wifi_setup_channel_info(modes[HOSTAPD_MODE_IEEE80211B].channels, modes[HOSTAPD_MODE_IEEE80211B].num_channels,
+                            BAND_2GHZ);
+    wifi_setup_channel_info(modes[HOSTAPD_MODE_IEEE80211G].channels, modes[HOSTAPD_MODE_IEEE80211G].num_channels,
+                            BAND_2GHZ);
+#if CONFIG_5GHz_SUPPORT
+    if (!ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        wifi_setup_channel_info(modes[HOSTAPD_MODE_IEEE80211A].channels, modes[HOSTAPD_MODE_IEEE80211A].num_channels,
+                                BAND_5GHZ);
+    }
+#endif
+
+    status = WM_SUCCESS;
+
+out:
+    return status;
+}
+
+int wifi_nxp_hostapd_do_acs(void *if_priv, struct drv_acs_params *params)
+{
+    int status = -WM_FAIL;
+
+    if ((!if_priv) || (!params))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    status = wifi_uap_do_acs(params->freq_list);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi uap do acs failed", __func__);
+        goto out;
+    }
+
+    status = WM_SUCCESS;
+
+out:
+    return status;
+}
+
+#define BSSID_OFFSET 16
+
+int wifi_nxp_hostapd_set_ap(void *if_priv, int beacon_set, struct wpa_driver_ap_params *params)
+{
+    int status                                 = -WM_FAIL;
+    int ret                                    = -1;
+    nxp_wifi_ap_info_t *ap_params              = NULL;
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if ((!if_priv) || (!params))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    ap_params = (nxp_wifi_ap_info_t *)OSA_MemoryAllocate(sizeof(nxp_wifi_ap_info_t));
+
+    if (!ap_params)
+    {
+        supp_e("%s: ap params calloc failed", __func__);
+        goto out;
+    }
+
+    ap_params->beacon_set = beacon_set;
+
+    memcpy(ap_params->bssid, params->head + BSSID_OFFSET, WIFI_ETH_ADDR_LEN);
+
+    memcpy(ap_params->head_ie.ie, params->head, params->head_len);
+
+    ap_params->head_ie.ie_len = params->head_len;
+
+    memcpy(ap_params->tail_ie.ie, params->tail, params->tail_len);
+
+    ap_params->tail_ie.ie_len = params->tail_len;
+
+    ap_params->dtim_period = params->dtim_period;
+
+    ap_params->beacon_int = params->beacon_int;
+
+    if (params->proberesp && params->proberesp_len)
+    {
+        memcpy(ap_params->proberesp.ie, params->proberesp, params->proberesp_len);
+
+        ap_params->proberesp_ies.ie_len = params->proberesp_len;
+    }
+
+    if (params->ssid && params->ssid_len)
+    {
+        memcpy((void *)ap_params->ssid.ssid, (const void *)params->ssid, (size_t)params->ssid_len);
+
+        ap_params->ssid.ssid_len = params->ssid_len;
+    }
+
+    ap_params->hide_ssid = params->hide_ssid;
+
+    ap_params->pairwise_ciphers = params->pairwise_ciphers;
+    ap_params->group_cipher     = params->group_cipher;
+    ap_params->key_mgmt_suites  = params->key_mgmt_suites;
+    ap_params->auth_algs        = params->auth_algs;
+    ap_params->wpa_version      = params->wpa_version;
+    ap_params->privacy          = params->privacy;
+
+    if (params->beacon_ies)
+    {
+        memcpy(ap_params->beacon_ies.ie, params->beacon_ies->buf, params->beacon_ies->used);
+
+        ap_params->beacon_ies.ie_len = params->beacon_ies->used;
+    }
+
+    if (params->proberesp_ies)
+    {
+        memcpy(ap_params->proberesp_ies.ie, params->proberesp_ies->buf, params->proberesp_ies->used);
+
+        ap_params->proberesp_ies.ie_len = params->proberesp_ies->used;
+    }
+
+    if (params->assocresp_ies)
+    {
+        memcpy(ap_params->assocresp_ies.ie, params->assocresp_ies->buf, params->assocresp_ies->used);
+
+        ap_params->assocresp_ies.ie_len = params->assocresp_ies->used;
+    }
+
+    ap_params->ht_opmode         = params->ht_opmode;
+    ap_params->ap_max_inactivity = params->ap_max_inactivity;
+    ap_params->reenable          = params->reenable;
+    ap_params->twt_responder     = params->twt_responder;
+    ap_params->sae_pwe           = params->sae_pwe;
+
+    if (params->freq)
+    {
+        ap_params->chan.mode               = (enum wifi_mode)params->freq->mode;
+        ap_params->chan.freq               = params->freq->freq;
+        ap_params->chan.channel            = params->freq->channel;
+        ap_params->chan.sec_channel_offset = params->freq->sec_channel_offset;
+        ap_params->chan.bandwidth          = params->freq->bandwidth;
+        ap_params->chan.ht_enabled         = params->freq->ht_enabled;
+        ap_params->chan.vht_enabled        = params->freq->vht_enabled;
+        ap_params->chan.he_enabled         = params->freq->he_enabled;
+        ap_params->chan.center_freq1       = params->freq->center_freq1;
+        ap_params->chan.center_freq2       = params->freq->center_freq2;
+    }
+
+    status = wifi_nxp_beacon_config(ap_params);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi nxp beacon config failed", __func__);
+        goto out;
+    }
+
+    if (!beacon_set)
+    {
+        wifi_if_ctx_rtos->uap_started = true;
+    }
+
+    ret = 0;
+out:
+    if (ap_params != NULL)
+    {
+        OSA_MemoryFree((void *)ap_params);
+    }
+    return ret;
+}
+
+int wifi_nxp_hostapd_sta_add(void *if_priv, struct hostapd_sta_add_params *params)
+{
+    int status                      = -WM_FAIL;
+    nxp_wifi_sta_info_t *sta_params = NULL;
+
+    if ((!if_priv) || (!params))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    sta_params = (nxp_wifi_sta_info_t *)OSA_MemoryAllocate(sizeof(nxp_wifi_sta_info_t));
+
+    if (!sta_params)
+    {
+        supp_e("%s: sta params calloc failed", __func__);
+        goto out;
+    }
+
+    sta_params->set = params->set;
+
+    memcpy(sta_params->addr, params->addr, WIFI_ETH_ADDR_LEN);
+
+    sta_params->aid = params->aid;
+
+    sta_params->capability = params->capability;
+
+    if (params->supp_rates_len)
+    {
+        sta_params->supp_rates_len = params->supp_rates_len;
+        memcpy((void *)sta_params->supp_rates, (const void *)params->supp_rates, (size_t)sta_params->supp_rates_len);
+    }
+
+    sta_params->listen_interval = params->listen_interval;
+
+    if (params->ext_capab)
+    {
+        memcpy(sta_params->ext_capab, params->ext_capab, params->ext_capab_len);
+        sta_params->ext_capab_len = params->ext_capab_len;
+    }
+
+    sta_params->qosinfo = params->qosinfo;
+
+    if (params->flags & WPA_STA_AUTHORIZED)
+        sta_params->flags |= STA_FLAG_AUTHORIZED;
+
+    if (params->flags & WPA_STA_WMM)
+        sta_params->flags |= STA_FLAG_WME;
+
+    if (params->flags & WPA_STA_SHORT_PREAMBLE)
+        sta_params->flags |= STA_FLAG_SHORT_PREAMBLE;
+
+    if (params->flags & WPA_STA_MFP)
+        sta_params->flags |= STA_FLAG_MFP;
+
+    if (params->flags & WPA_STA_AUTHENTICATED)
+        sta_params->flags |= STA_FLAG_AUTHENTICATED;
+
+    if (params->flags & WPA_STA_ASSOCIATED)
+        sta_params->flags |= STA_FLAG_ASSOCIATED;
+
+    if (params->ht_capabilities)
+    {
+        memcpy(&sta_params->ht_capab, params->ht_capabilities, sizeof(struct ieee80211_ht_capabilities));
+        sta_params->ht_capab_len = sizeof(struct ieee80211_ht_capabilities);
+    }
+
+    if (params->vht_capabilities)
+    {
+        memcpy(&sta_params->vht_capab, params->vht_capabilities, sizeof(struct ieee80211_vht_capabilities));
+        sta_params->vht_capab_len = sizeof(struct ieee80211_vht_capabilities);
+    }
+
+    if (params->he_capab)
+    {
+        memcpy(&sta_params->he_capab, params->he_capab, sizeof(struct ieee80211_he_capabilities));
+        sta_params->he_capab_len = params->he_capab_len;
+    }
+
+    status = wifi_nxp_sta_add(sta_params);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi nxp sta add failed", __func__);
+    }
+out:
+    if (sta_params != NULL)
+    {
+        OSA_MemoryFree((void *)sta_params);
+    }
+    return status;
+}
+
+int wifi_nxp_hostapd_sta_remove(void *if_priv, const u8 *addr)
+{
+    int status = -WM_FAIL;
+
+    if ((!if_priv) || (!addr))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    status = wifi_nxp_sta_remove(addr);
+    if (status != WM_SUCCESS)
+    {
+        supp_e("%s: wifi nxp sta remove failed", __func__);
+    }
+out:
+    return status;
+}
+
+int wifi_nxp_hostapd_send_eapol(void *if_priv, const u8 *data, size_t data_len)
+{
+    int ret = -1;
+    if ((!if_priv) || (!data))
+    {
+        supp_e("%s: Invalid params\n", __func__);
+        goto out;
+    }
+
+    ret = wifi_supp_inject_frame(WLAN_BSS_TYPE_UAP, data, data_len);
+
+out:
+    return ret;
+}
+
+int wifi_nxp_hostapd_set_freq(void *if_priv, struct hostapd_freq_params *freq)
+{
+    int ret = -1;
+    nxp_wifi_chan_info_t chan;
+
+    if ((!if_priv) || (!freq))
+    {
+        supp_e("%s: Invalid params\n", __func__);
+        goto out;
+    }
+
+    memset(&chan, 0x00, sizeof(nxp_wifi_chan_info_t));
+
+#if 0
+    PRINTF("freq->freq: %d\r\n", freq->freq);
+    PRINTF("freq->channel: %d\r\n", freq->channel);
+    PRINTF("freq->ht_enabled: %d\r\n", freq->ht_enabled);
+    PRINTF("freq->sec_channel_offset: %d\r\n", freq->sec_channel_offset);
+    PRINTF("freq->vht_enabled: %d\r\n", freq->vht_enabled);
+    PRINTF("freq->he_enabled: %d\r\n", freq->he_enabled);
+    PRINTF("freq->bandwidth: %d\r\n", freq->bandwidth);
+#endif
+    ret = 0;
+
+    chan.mode               = (enum wifi_mode)freq->mode;
+    chan.freq               = freq->freq;
+    chan.channel            = freq->channel;
+    chan.sec_channel_offset = freq->sec_channel_offset;
+    chan.bandwidth          = freq->bandwidth;
+    chan.ht_enabled         = freq->ht_enabled;
+    chan.vht_enabled        = freq->vht_enabled;
+    chan.he_enabled         = freq->he_enabled;
+    chan.center_freq1       = freq->center_freq1;
+    chan.center_freq2       = freq->center_freq2;
+
+    ret = 0; // wifi_nxp_set_chan(chan);
+
+out:
+    return ret;
+}
+
+int wifi_nxp_hostapd_set_rts(void *if_priv, int rts_threshold)
+{
+    int ret = -1;
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params\n", __func__);
+        goto out;
+    }
+
+    // ret = wifi_nxp_set_rts(rts_threshold);
+    ret = wifi_set_uap_rts(rts_threshold);
+
+out:
+    return ret;
+}
+
+int wifi_nxp_hostapd_set_frag(void *if_priv, int frag_threshold)
+{
+    int ret = -1;
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params\n", __func__);
+        goto out;
+    }
+
+    ret = wifi_set_uap_frag(frag_threshold);
+
+out:
+    return ret;
+}
+
+int wifi_nxp_hostapd_stop_ap(void *if_priv)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                                    = -1;
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    ret = wifi_nxp_stop_ap();
+    if (ret != 0)
+    {
+        supp_e("%s: Stop AP failed", __func__);
+        goto out;
+    }
+    wifi_if_ctx_rtos->uap_started = false;
+out:
+    return ret;
+}
+
+int wifi_nxp_hostapd_set_acl(void *if_priv, struct hostapd_acl_params *params)
+{
+    // struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+    int ret                         = -1;
+    nxp_wifi_acl_info_t *acl_params = NULL;
+    size_t acl_sz                   = 0;
+    unsigned int i;
+
+    if ((!if_priv) || (!params))
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    // wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    acl_sz = WIFI_ETH_ADDR_LEN * params->num_mac_acl;
+
+    acl_params = (nxp_wifi_acl_info_t *)OSA_MemoryAllocate(sizeof(nxp_wifi_acl_info_t) + acl_sz);
+    if (!acl_params)
+    {
+        supp_e("%s: acl params calloc failed", __func__);
+        goto out;
+    }
+
+    acl_params->acl_policy  = params->acl_policy;
+    acl_params->num_mac_acl = params->num_mac_acl;
+
+    for (i = 0; i < params->num_mac_acl; i++)
+    {
+        memcpy(acl_params->mac_acl[i].addr, params->mac_acl[i].addr, WIFI_ETH_ADDR_LEN);
+    }
+
+    ret = wifi_nxp_set_acl(acl_params);
+    if (ret != 0)
+    {
+        supp_e("%s: Set ACL failed", __func__);
+    }
+
+out:
+    if (acl_params)
+        OSA_MemoryFree((void *)acl_params);
+    return ret;
+}
+
+int wifi_nxp_wpa_dpp_listen(void *if_priv, bool enable)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    if (!if_priv)
+    {
+        supp_e("%s: Invalid params", __func__);
+        goto out;
+    }
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+    if (enable && (wifi_if_ctx_rtos->bss_type == BSS_TYPE_STA))
+    {
+        return wifi_set_rx_mgmt_indication(wifi_if_ctx_rtos->bss_type, WLAN_MGMT_ACTION);
+    }
+    else
+    {
+        return 0;
+    }
+
+out:
+    return -1;
+}
+
+bool wifi_nxp_wpa_get_modes(void *if_priv)
+{
+    return (!ISSUPP_NO5G(mlan_adap->fw_cap_ext));
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/wifi_nxp.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/wifi_nxp.c
new file mode 100644
index 0000000000..dda431e54c
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/wifi_nxp.c
@@ -0,0 +1,273 @@
+/** @file wifi_nxp.c
+ *
+ * @brief This file provides Core Wi-Fi definition for wpa supplicant rtos driver.
+ *
+ * Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <osa.h>
+#include <wm_net.h>
+#include <wifi.h>
+#include <wifi-debug.h>
+
+#if CONFIG_WPA_SUPP
+
+#include <wifi_nxp.h>
+#include <rtos_wpa_supp_if.h>
+
+#include "supp_main.h"
+
+static t_u8 wifi_supp_init_done;
+static struct wifi_nxp_ctx_rtos *g_wifi_if_ctx_rtos = NULL;
+
+int wifi_nxp_set_mac_addr(const t_u8 *mac);
+
+static int wifi_nxp_wpa_supp_set_mac_addr(void *if_priv, const t_u8 *addr)
+{
+    if (!if_priv || !addr)
+    {
+        supp_e("%s: Invalid params", __func__);
+        return -WM_FAIL;
+    }
+
+    return wifi_nxp_set_mac_addr(addr);
+}
+
+const rtos_wpa_supp_dev_ops wpa_supp_ops = {
+    .init                     = wifi_nxp_wpa_supp_dev_init,
+    .deinit                   = wifi_nxp_wpa_supp_dev_deinit,
+    .hapd_init                = wifi_nxp_hostapd_dev_init,
+    .hapd_deinit              = wifi_nxp_hostapd_dev_deinit,
+    .set_mac_addr             = wifi_nxp_wpa_supp_set_mac_addr,
+    .scan2                    = wifi_nxp_wpa_supp_scan2,
+    .set_default_scan_ies     = wifi_nxp_wpa_supp_set_default_scan_ies,
+    .sched_scan               = wifi_nxp_wpa_supp_sched_scan,
+    .stop_sched_scan          = wifi_nxp_wpa_supp_stop_sched_scan,
+    .scan_abort               = wifi_nxp_wpa_supp_scan_abort,
+    .get_scan_results2        = wifi_nxp_wpa_supp_scan_results_get,
+    .deauthenticate           = wifi_nxp_wpa_supp_deauthenticate,
+    .authenticate             = wifi_nxp_wpa_supp_authenticate,
+    .associate                = wifi_nxp_wpa_supp_associate,
+    .set_key                  = wifi_nxp_wpa_supp_set_key,
+    .del_key                  = wifi_nxp_wpa_supp_del_key,
+    .set_rekey_info           = wifi_nxp_wpa_supp_set_rekey_info,
+    .set_supp_port            = wifi_nxp_wpa_set_supp_port,
+    .set_country              = wifi_nxp_wpa_supp_set_country,
+    .get_country              = wifi_nxp_wpa_supp_get_country,
+    .signal_poll              = wifi_nxp_wpa_supp_signal_poll,
+    .send_mlme                = wifi_nxp_wpa_send_mlme,
+    .remain_on_channel        = wifi_nxp_wpa_supp_remain_on_channel,
+    .cancel_remain_on_channel = wifi_nxp_wpa_supp_cancel_remain_on_channel,
+    .get_survey_results       = wifi_nxp_wpa_supp_survey_results_get,
+    .set_modes                = wifi_nxp_hostapd_set_modes,
+    .do_acs                   = wifi_nxp_hostapd_do_acs,
+    .set_ap                   = wifi_nxp_hostapd_set_ap,
+    .sta_add                  = wifi_nxp_hostapd_sta_add,
+    .sta_remove               = wifi_nxp_hostapd_sta_remove,
+    .hapd_send_eapol          = wifi_nxp_hostapd_send_eapol,
+    .set_freq                 = wifi_nxp_hostapd_set_freq,
+    .set_rts                  = wifi_nxp_hostapd_set_rts,
+    .set_frag                 = wifi_nxp_hostapd_set_frag,
+    .stop_ap                  = wifi_nxp_hostapd_stop_ap,
+    .set_acl                  = wifi_nxp_hostapd_set_acl,
+    .dpp_listen               = wifi_nxp_wpa_dpp_listen,
+    .get_modes                = wifi_nxp_wpa_get_modes,
+};
+
+static void wifi_nxp_event_proc_scan_start(void *if_ctx)
+{
+    wifi_nxp_wpa_supp_event_proc_scan_start(if_ctx);
+}
+
+static void wifi_nxp_event_proc_scan_abort(void *if_ctx)
+{
+    wifi_nxp_wpa_supp_event_proc_scan_abort(if_ctx);
+}
+
+static void wifi_nxp_event_proc_scan_done(void *if_priv, int external_scan)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (wifi_if_ctx_rtos == NULL)
+    {
+        wifi_e("%s: wifi_if_ctx_rtos is NULL", __func__);
+        return;
+    }
+    wifi_nxp_wpa_supp_event_proc_scan_done(if_priv, 0, external_scan);
+}
+
+static void wifi_nxp_event_reamin_on_channel(void *if_priv, int cancel_channel)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+    wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)if_priv;
+
+    if (wifi_if_ctx_rtos == NULL)
+    {
+        wifi_e("%s: wifi_if_ctx_rtos is NULL", __func__);
+        return;
+    }
+    wifi_nxp_wpa_supp_event_proc_remain_on_channel(if_priv, cancel_channel);
+}
+
+static const wifi_nxp_callbk_fns_t supp_callbk_fns = {
+    .mac_changed_callbk_fn         = wifi_nxp_wpa_supp_event_proc_mac_changed,
+    .chan_list_changed_callbk_fn   = wifi_nxp_wpa_supp_event_proc_chan_list_changed,
+    .scan_start_callbk_fn          = wifi_nxp_event_proc_scan_start,
+    .scan_done_callbk_fn           = wifi_nxp_event_proc_scan_done,
+    .scan_abort_callbk_fn          = wifi_nxp_event_proc_scan_abort,
+    .survey_res_callbk_fn          = wifi_nxp_wpa_supp_event_proc_survey_res,
+    .auth_resp_callbk_fn           = wifi_nxp_wpa_supp_event_proc_auth_resp,
+    .assoc_resp_callbk_fn          = wifi_nxp_wpa_supp_event_proc_assoc_resp,
+    .deauth_callbk_fn              = wifi_nxp_wpa_supp_event_proc_deauth,
+    .disassoc_callbk_fn            = wifi_nxp_wpa_supp_event_proc_disassoc,
+    .acs_channel_sel_callbk_fn     = wifi_nxp_wpa_supp_event_acs_channel_selected,
+    .mgmt_tx_status_callbk_fn      = wifi_nxp_wpa_supp_event_mgmt_tx_status,
+    .unprot_mlme_mgmt_rx_callbk_fn = wifi_nxp_wpa_supp_event_proc_unprot_mgmt,
+    .remain_on_channel_callbk_fn   = wifi_nxp_event_reamin_on_channel,
+    .mgmt_rx_callbk_fn             = wifi_nxp_wpa_supp_event_proc_mgmt_rx,
+    .eapol_rx_callbk_fn            = wifi_nxp_wpa_supp_event_proc_eapol_rx,
+    .ecsa_complete_callbk_fn       = wifi_nxp_wpa_supp_event_proc_ecsa_complete,
+    .dfs_cac_started_callbk_fn     = wifi_nxp_wpa_supp_event_proc_dfs_cac_started,
+    .dfs_cac_finished_callbk_fn    = wifi_nxp_wpa_supp_event_proc_dfs_cac_finished,
+};
+
+#ifndef __ZEPHYR__
+static int g_net_idx = -1;
+#endif
+
+int wifi_supp_init(void)
+{
+    int ret = -WM_FAIL;
+    char sta_iface_name[NETIF_NAMESIZE], uap_iface_name[NETIF_NAMESIZE];
+    struct netif *iface = NULL;
+
+    if (wifi_supp_init_done != 0U)
+    {
+        return WM_SUCCESS;
+    }
+
+    wm_wifi.supp_if_callbk_fns = (wifi_nxp_callbk_fns_t *)&supp_callbk_fns;
+
+    g_wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)OSA_MemoryAllocate(sizeof(struct wifi_nxp_ctx_rtos));
+
+    if (!g_wifi_if_ctx_rtos)
+    {
+        wifi_e("Interface ctx alloc failed.");
+        goto out;
+    }
+
+    wm_wifi.if_priv = (void *)g_wifi_if_ctx_rtos;
+
+    iface = net_get_sta_interface();
+
+    if (iface == NULL)
+    {
+        wifi_e("net_get_sta_interface failed. status code %d", ret);
+        goto out;
+    }
+
+#ifndef __ZEPHYR__
+    if (g_net_idx == -1)
+    {
+        g_net_idx = net_alloc_client_data_id();
+
+        if (g_net_idx == -1)
+        {
+            wifi_e("net_alloc_client_data_id failed. net idx %d", g_net_idx);
+            goto out;
+        }
+    }
+
+    netif_set_client_data(iface, LWIP_NETIF_CLIENT_DATA_INDEX_MAX, (void *)&wpa_supp_ops);
+#endif
+
+    (void)net_get_if_name_netif(sta_iface_name, iface);
+
+    g_wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)OSA_MemoryAllocate(sizeof(struct wifi_nxp_ctx_rtos));
+
+    if (!g_wifi_if_ctx_rtos)
+    {
+        wifi_e("Interface ctx alloc failed.");
+        goto out;
+    }
+
+    wm_wifi.hapd_if_priv = (void *)g_wifi_if_ctx_rtos;
+
+    iface = net_get_uap_interface();
+
+    if (iface == NULL)
+    {
+        wifi_e("net_get_uap_interface failed. status code %d", ret);
+        goto out;
+    }
+
+#ifndef __ZEPHYR__
+    netif_set_client_data(iface, LWIP_NETIF_CLIENT_DATA_INDEX_MAX, (void *)&wpa_supp_ops);
+#endif
+
+    (void)net_get_if_name_netif(uap_iface_name, iface);
+
+    ret = start_wpa_supplicant(sta_iface_name);
+
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("start wpa supplicant failed. status code %d", ret);
+        goto out;
+    }
+
+    if (ret == WM_SUCCESS)
+    {
+        wifi_supp_init_done = 1U;
+    }
+
+    return WM_SUCCESS;
+
+out:
+    wifi_supp_deinit();
+    return ret;
+}
+
+void wifi_supp_deinit(void)
+{
+    int ret;
+
+    if (wifi_supp_init_done != 1U)
+    {
+        return;
+    }
+
+    ret = stop_wpa_supplicant();
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("stop wpa supplicant failed. status code %d", ret);
+    }
+
+    if (wm_wifi.if_priv)
+    {
+        OSA_MemoryFree(wm_wifi.if_priv);
+        wm_wifi.if_priv = NULL;
+    }
+
+    if (wm_wifi.hapd_if_priv)
+    {
+        OSA_MemoryFree(wm_wifi.hapd_if_priv);
+        wm_wifi.hapd_if_priv = NULL;
+    }
+    wifi_supp_init_done = 0U;
+}
+
+int wifi_nxp_set_mac_addr(const t_u8 *mac)
+{
+    wlan_set_mac_addr((uint8_t *)mac);
+    return WM_SUCCESS;
+}
+#endif /* CONFIG_WPA_SUPP */
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/wifi_nxp_internal.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/wifi_nxp_internal.c
new file mode 100644
index 0000000000..ecaca6bc27
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wifidriver/wpa_supp_if/wifi_nxp_internal.c
@@ -0,0 +1,154 @@
+/** @file wifi_nxp_internal.c
+ *
+ * @brief This file provides Core Wi-Fi definition for wpa supplicant rtos driver.
+ *
+ * Copyright 2008-2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <osa.h>
+#include <wm_net.h>
+#include <wifi.h>
+#include <wifi_nxp.h>
+#include <dhcp-server.h>
+#include <wifi-internal.h>
+#include <wifi-debug.h>
+
+#if CONFIG_WPA_SUPP
+
+#include <rtos_wpa_supp_if.h>
+#include "supp_main.h"
+
+void wifi_survey_result_get(struct wifi_message *msg)
+{
+    nxp_wifi_trigger_op_t *wifi_survey_params = (nxp_wifi_trigger_op_t *)msg->data;
+
+#if CONFIG_HOSTAPD
+    wm_wifi.hostapd_op = false;
+
+    if (wifi_survey_params->hostapd)
+    {
+        wm_wifi.hostapd_op = true;
+    }
+#endif
+
+    wifi_nxp_survey_res_get();
+    OSA_MemoryFree(wifi_survey_params);
+}
+
+/* Event handlers*/
+void wifi_scan_start(struct wifi_message *msg)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.if_priv;
+
+    if (wifi_if_ctx_rtos->scan_in_progress)
+    {
+        if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+        {
+            if (wm_wifi.supp_if_callbk_fns->scan_start_callbk_fn)
+            {
+                wm_wifi.supp_if_callbk_fns->scan_start_callbk_fn(wm_wifi.if_priv);
+            }
+        }
+    }
+}
+
+void wifi_scan_done(struct wifi_message *msg)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = NULL;
+
+#if CONFIG_HOSTAPD
+    if (wm_wifi.hostapd_op)
+    {
+        wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.hapd_if_priv;
+
+        wm_wifi.hostapd_op = false;
+    }
+    else
+#endif
+    {
+        wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.if_priv;
+    }
+
+    wifi_nxp_reset_scan_flag();
+
+    if (msg->reason == WIFI_EVENT_REASON_FAILURE)
+    {
+        if (wm_wifi.supp_if_callbk_fns->scan_abort_callbk_fn)
+        {
+            wm_wifi.supp_if_callbk_fns->scan_abort_callbk_fn(wm_wifi.if_priv);
+        }
+    }
+
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+        if (wm_wifi.supp_if_callbk_fns->scan_done_callbk_fn)
+        {
+#if CONFIG_HOSTAPD
+            if (wifi_if_ctx_rtos->hostapd)
+            {
+                wm_wifi.supp_if_callbk_fns->scan_done_callbk_fn(wm_wifi.hapd_if_priv, wm_wifi.external_scan);
+            }
+            else
+#endif
+            {
+                wm_wifi.supp_if_callbk_fns->scan_done_callbk_fn(wm_wifi.if_priv, wm_wifi.external_scan);
+            }
+        }
+    }
+
+    wm_wifi.external_scan = false;
+}
+
+void wifi_process_remain_on_channel(struct wifi_message *msg)
+{
+    struct wifi_nxp_ctx_rtos *wifi_if_ctx_rtos = (struct wifi_nxp_ctx_rtos *)wm_wifi.if_priv;
+    if (wifi_if_ctx_rtos->supp_called_remain_on_chan == true)
+    {
+        if ((msg->reason == WIFI_EVENT_REASON_SUCCESS) &&
+            (wm_wifi.supp_if_callbk_fns->remain_on_channel_callbk_fn != NULL))
+        {
+            if (*(t_u8 *)(msg->data) == true)
+            {
+                wm_wifi.supp_if_callbk_fns->remain_on_channel_callbk_fn(wifi_if_ctx_rtos, 1);
+            }
+            else
+            {
+                wm_wifi.supp_if_callbk_fns->remain_on_channel_callbk_fn(wifi_if_ctx_rtos, 0);
+            }
+        }
+        wifi_if_ctx_rtos->supp_called_remain_on_chan = false;
+    }
+    if (msg->data)
+    {
+        OSA_MemoryFree(msg->data);
+        msg->data = NULL;
+    }
+}
+
+void wifi_process_mgmt_tx_status(struct wifi_message *msg)
+{
+    nxp_wifi_event_mlme_t *resp = &wm_wifi.mgmt_resp;
+    resp->frame.frame_len       = 0;
+
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+        if (wm_wifi.supp_if_callbk_fns->mgmt_tx_status_callbk_fn)
+        {
+            if ((t_u32)(msg->data) == MLAN_BSS_TYPE_UAP)
+            {
+                wm_wifi.supp_if_callbk_fns->mgmt_tx_status_callbk_fn(wm_wifi.hapd_if_priv, resp, resp->frame.frame_len);
+            }
+            else
+            {
+                wm_wifi.supp_if_callbk_fns->mgmt_tx_status_callbk_fn(wm_wifi.if_priv, resp, resp->frame.frame_len);
+            }
+        }
+    }
+}
+
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wlcmgr/wlan.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wlcmgr/wlan.c
new file mode 100644
index 0000000000..f2d7dd124f
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wlcmgr/wlan.c
@@ -0,0 +1,15586 @@
+/** @file wlan.c
+ *
+ *  @brief  This file provides Core WLAN definition
+ *
+ *  Copyright 2008-2024 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <string.h>
+#include <wm_utils.h>
+#include <wlan.h>
+#include <wifi.h>
+#include <osa.h>
+#include <wm_net.h>
+#include <wifi-debug.h>
+#include <wlan_11d.h>
+#include <stdint.h>
+#ifndef RW610
+#include <mlan_sdio_api.h>
+#endif
+#if (CONFIG_HOST_PMK) || (CONFIG_WPS2)
+#include <wm_mbedtls_helper_api.h>
+#include <mbedtls/x509_crt.h>
+#endif /* (CONFIG_HOST_PMK) || (CONFIG_WPS2) */
+#ifdef RW610
+#include <wifi_cal_data_ext.h>
+#endif
+#ifdef OVERRIDE_CALIBRATION_DATA
+#include OVERRIDE_CALIBRATION_DATA
+#else
+#include <wifi_cal_data_ext.h>
+#endif
+#include <fsl_common.h>
+#include <dhcp-server.h>
+#ifdef RW610
+#include "fsl_loader.h"
+#endif
+
+#if CONFIG_SIGMA_AGENT
+#include "wifi_ping.h"
+#endif
+
+#if CONFIG_HOST_SLEEP
+#ifdef RW610
+#include  "fsl_power.h"
+#ifndef __ZEPHYR__
+#if !(CONFIG_WIFI_BLE_COEX_APP)
+#if CONFIG_NCP
+#include  "ncp_lpm.h"
+#else
+#include  "lpm.h"
+#endif
+#include  "host_sleep.h"
+#endif
+#if CONFIG_POWER_MANAGER
+#include  "fsl_pm_core.h"
+#include  "fsl_pm_device.h"
+#endif
+#endif
+#endif
+#endif
+#if CONFIG_WPS2
+#include  <wifi_nxp_wps.h>
+#include  <wps_def.h>
+#endif
+#if CONFIG_WPA_SUPP
+#include <supp_main.h>
+#include <supp_api.h>
+#include <supp_crypto.h>
+#include <wifi_nxp.h>
+#include "utils/common.h"
+#if CONFIG_WIFI_SHELL
+#include "wpa_cli.h"
+#endif
+#endif
+
+#if (CONFIG_WPA2_ENTP) || ((CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE) && !(CONFIG_WIFI_USB_FILE_ACCESS))
+#include "ca-cert.h"
+#include "client-cert.h"
+#include "client-key.h"
+#include "dh-param.h"
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+#include "server-cert.h"
+#include "server-key.h"
+#endif
+#endif
+#endif
+#include "mlan_decl.h"
+
+#if CONFIG_NCP
+#include "app_notify.h"
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+#include "board.h"
+
+#if (defined(CPU_MIMXRT1062DVMAA_cm7) || defined(CPU_MIMXRT1062DVL6A_cm7) || defined (CPU_MIMXRT1062DVL6B_cm7))
+#if defined(SD8978) || defined(SD8987)
+/* IR-OOB TRIGGER Connect Fly-Wire between J16.1 and J108.4 for 1XK-M2, 1ZM-M2*/
+#define IR_OUTBAND_TRIGGER_GPIO			GPIO1
+#define IR_OUTBAND_TRIGGER_GPIO_PIN		(23U)
+#define IR_OUTBAND_TRIGGER_GPIO_NAME   "GPIO1"
+//#define IOMUXC_GPIO_IR_OUTBAND_TRIGGER IOMUXC_GPIO_AD_B1_07_GPIO1_IO23
+#elif defined(SD9177)
+/* IR-OOB TRIGGER for 2EL-M2, Internal Routing to M2 Slot*/
+#define IR_OUTBAND_TRIGGER_GPIO			GPIO1
+#define IR_OUTBAND_TRIGGER_GPIO_PIN		(24U)
+#define IR_OUTBAND_TRIGGER_GPIO_NAME   "GPIO1"
+//#define IOMUXC_GPIO_IR_OUTBAND_TRIGGER IOMUXC_GPIO_AD_B1_08_GPIO1_IO24
+#endif
+
+#elif defined(CPU_MIMXRT1176DVMAA_cm7) // For RT1170
+/* IR OUT-BAND TRIGGER GPIO*/
+/*Output GPIO J9 PIN2 (IOMUXC_GPIO_DISP_B2_11) for RT1170-EVKA/B*/
+#define IR_OUTBAND_TRIGGER_GPIO   		GPIO5
+#define IR_OUTBAND_TRIGGER_GPIO_PIN   	(12U)
+#define IR_OUTBAND_TRIGGER_GPIO_NAME  	"GPIO5"
+
+#endif /* (defined(CPU_MIMXRT1062DVMAA_cm7) || (CPU_MIMXRT1062DVL6A_cm7)) */
+#endif
+
+#define DELAYED_SLP_CFM_DUR 10U
+#define BAD_MIC_TIMEOUT     (60 * 1000)
+
+#if CONFIG_WPA_SUPP
+#define SUPP_STATUS_TIMEOUT (2 * 1000)
+#define ROAM_SCAN_TIMEOUT   (60 * 1000)
+#endif
+
+#define WL_ID_CONNECT      "wifi_connect"
+#define WL_ID_DEEPSLEEP_SM "wlcm_deepsleep_sm"
+#define WL_ID_WIFI_RSSI    "wifi_rssi"
+
+/** Find maximum */
+#ifndef MAX
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+
+#if CONFIG_ECSA
+#define DEF_SWITCH_COUNT 10
+#endif
+
+#define BG_SCAN_LIMIT 3
+
+static bool wlan_uap_scan_chan_list_set;
+
+wlan_flt_cfg_t g_flt_cfg;
+#ifdef RW610
+#if CONFIG_MONOLITHIC_WIFI
+extern const unsigned char *wlan_fw_bin;
+extern const unsigned int wlan_fw_bin_len;
+#else
+const unsigned char *wlan_fw_bin   = (const unsigned char *)(void *)0;
+const unsigned int wlan_fw_bin_len = 0;
+#endif /* CONFIG_MONOLITHIC_WIFI */
+#ifdef __ZEPHYR__
+extern int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data);
+#define wlan_event_callback nxp_wifi_wlan_event_callback
+#else
+extern int wlan_event_callback(enum wlan_event_reason reason, void *data);
+#endif
+#endif
+
+static int wifi_wakeup_card_cb(osa_rw_lock_t *plock, unsigned int wait_time);
+
+#if CONFIG_WPA2_ENTP
+extern int wpa2_ent_connect(struct wlan_network *wpa2_network);
+extern void wpa2_shutdown();
+#endif
+
+#if CONFIG_NCP
+/* uap provision callbacks */
+int (*uap_prov_deinit_cb)(void) = NULL;
+void (*uap_prov_cleanup_cb)(void) = NULL;
+#endif
+
+
+osa_rw_lock_t sleep_rwlock;
+
+#if CONFIG_WMM_UAPSD
+OSA_SEMAPHORE_HANDLE_DEFINE(uapsd_sem);
+#endif
+
+#if CONFIG_CPU_LOADING
+#define CPU_LOADING_ACTION_STOP        0
+#define CPU_LOADING_ACTION_START       1
+#define CPU_LOADING_STATUS_ONGOING     2
+#define CPU_LOADING_STATUS_ENDING      3
+#define CPU_LOADING_STATUS_DEAD        4
+#define CPU_LOADING_PERIOD             2000
+#define CPU_LOADING_TASK_NUM           20
+#define CPU_LOADING_KEEPING            -1
+
+#define CONFIG_CPU_LOADING_STACK_SIZE (2048)
+
+static void cpu_loading_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(cpu_loading_task, WLAN_TASK_PRI_HIGH, 1, CONFIG_CPU_LOADING_STACK_SIZE, 0);
+
+static struct
+{
+    /*The number of tasks.*/
+    uint8_t task_nums;
+    /*The total length of cpu info struct*/
+    uint32_t task_status_len;
+    /*Pointer to buffer of storing cpu Loading info.*/
+    char *cpu_loading_info;
+    /*CPU loading status: CPU_LOADING_STATUS_ENDING / CPU_LOADING_STATUS_ONGOING / CPU_LOADING_STATUS_DEAD*/
+    uint8_t status;
+    /*Index of collecting CPU loading info.*/
+    uint32_t index;
+    /*Remaining time of collecting CPU loading info.*/
+    int sampling_loops;
+    /*The value of timer time out*/
+    uint32_t sampling_period;
+    /*CPU loading timer.*/
+    OSA_TIMER_HANDLE_DEFINE(cpu_loading_timer);
+    /*CPU loading thread.*/
+    OSA_TASK_HANDLE_DEFINE(cpu_loading_task_Handle);
+
+    /*Array of recording names of tasks.*/
+    char task_name[CPU_LOADING_TASK_NUM][configMAX_TASK_NAME_LEN];
+    /*Array of recording runing time of tasks.*/
+    uint64_t data_cur[CPU_LOADING_TASK_NUM];
+    uint64_t data_pre[CPU_LOADING_TASK_NUM];
+    /*Array of recording the first runing time of tasks.*/
+    uint64_t first_data[CPU_LOADING_TASK_NUM];
+}cpu_loading;
+
+char task_string_name[CPU_LOADING_TASK_NUM][configMAX_TASK_NAME_LEN];
+
+#endif
+
+#if ((CONFIG_11MC) || (CONFIG_11AZ)) && (CONFIG_WLS_CSI_PROC)
+OSA_SEMAPHORE_HANDLE_DEFINE(wls_csi_sem);
+#endif
+
+#if CONFIG_WPS2
+int prov_session_attempt = PROV_NON_SESSION_ATTEMPT;
+extern WPS_DATA wps_global;
+#endif
+
+#define MAX_EVENTS 20
+#define CONNECTION_EVENT(r, data) \
+    if (wlan.cb != NULL)          \
+    {                             \
+        (void)wlan.cb(r, data);   \
+    }
+
+#ifdef RW610
+OSA_MUTEX_HANDLE_DEFINE(reset_lock);
+/* Mon thread */
+static bool mon_thread_init = 0;
+#endif
+
+#if CONFIG_HOST_SLEEP
+#if CONFIG_POWER_MANAGER
+#ifndef __ZEPHYR__
+status_t powerManager_WlanNotify(pm_event_type_t eventType, uint8_t powerState, void *data);
+AT_ALWAYS_ON_DATA_INIT(pm_notify_element_t wlan_notify) =
+{
+    .notifyCallback = powerManager_WlanNotify,
+    .data           = NULL,
+};
+bool is_wakeup_cond_set = false;
+#endif
+#if !(CONFIG_WIFI_BLE_COEX_APP)
+int wlan_host_sleep_state = HOST_SLEEP_DISABLE;
+#else
+int wlan_host_sleep_state = HOST_SLEEP_PERIODIC;
+#endif
+#if CONFIG_UART_INTERRUPT
+/* This flag is used for Power Manager only.
+ * When using Power Manager, the uart task holds the rxSemaphore and waits
+ * on uart event group to receive input from uart. With this flag, uart task
+ * will have chance to release the lock so that IDLE task can do uart deinit
+ * before entering PM3.
+ * When using suspend mode, no such observations.
+ */
+bool usart_suspend_flag = false;
+#endif
+#if (!CONFIG_WIFI_BLE_COEX_APP) && (!CONFIG_NCP_BLE)
+OSA_TIMER_HANDLE_DEFINE(wake_timer);
+#endif
+#endif
+int is_hs_handshake_done = 0;
+bool wlan_hs_pre_cfg_done = false;
+
+extern OSA_SEMAPHORE_HANDLE_DEFINE(wakelock);
+extern int wakeup_by;
+
+bool wlan_is_manual = false;
+#endif
+
+#if CONFIG_SCAN_CHANNEL_GAP
+static t_u16 scan_channel_gap = (t_u16)SCAN_CHANNEL_GAP_VALUE;
+#endif
+
+#if defined(SDK_OS_FREE_RTOS)
+#ifdef SD9177
+#define POLL_TIMEOUT (20 * 1000)
+static struct udp_pcb *udp_raw_pcb;
+#endif
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V)
+#define NEIGHBOR_REQ_TIMEOUT (60 * 1000)
+#endif
+
+#if CONFIG_11R
+#if CONFIG_WPA_SUPP
+#define FT_ROAM_TIMEOUT (20 * 1000)
+#endif
+#endif
+
+#if CONFIG_POWER_MANAGER
+#define WAKE_TIMEOUT (5 * 1000)
+#endif
+
+#ifdef RW610
+#define TEMPERATURE_MON_TIMEOUT (5 * 1000)
+OSA_TIMER_HANDLE_DEFINE(temperature_mon_timer);
+#endif
+
+enum user_request_type
+{
+    /* we append our user-generated events to the wifi interface events and
+     * handle them accordingly */
+    CM_STA_USER_REQUEST_CONNECT = WIFI_EVENT_LAST + 1,
+    CM_STA_USER_REQUEST_DISCONNECT,
+    CM_STA_USER_REQUEST_SCAN,
+#if (CONFIG_11K) || (CONFIG_11V)
+    CM_STA_USER_REQUEST_SET_RSSI_THRESHOLD,
+#endif
+#if CONFIG_HOST_SLEEP
+    CM_STA_USER_REQUEST_HS,
+#endif
+    CM_STA_USER_REQUEST_PS_ENTER,
+    CM_STA_USER_REQUEST_PS_EXIT,
+#if CONFIG_CPU_LOADING
+    CM_STA_USER_REQUEST_CPU_LOADING,
+#endif
+    CM_STA_USER_REQUEST_LAST,
+    /* All the STA related request are above and uAP related requests are
+       below */
+    CM_UAP_USER_REQUEST_START,
+    CM_UAP_USER_REQUEST_STOP,
+    CM_UAP_USER_REQUEST_PS_ENTER,
+    CM_UAP_USER_REQUEST_PS_EXIT,
+    CM_UAP_USER_REQUEST_LAST,
+    CM_WLAN_USER_REQUEST_DEINIT,
+    CM_WLAN_USER_REQUEST_SHUTDOWN
+};
+
+static int send_user_request(enum user_request_type request, unsigned int data);
+
+enum cm_sta_state
+{
+    CM_STA_INITIALIZING = 0,
+    CM_STA_IDLE,
+    CM_STA_SCANNING,
+    CM_STA_SCANNING_USER,
+    CM_STA_ASSOCIATING,
+    CM_STA_ASSOCIATED,
+    CM_STA_AUTHENTICATED,
+    CM_STA_REQUESTING_ADDRESS,
+    CM_STA_OBTAINING_ADDRESS,
+    CM_STA_CONNECTED,
+};
+
+enum cm_uap_state
+{
+    CM_UAP_INITIALIZING = 0,
+    CM_UAP_CONFIGURED,
+    CM_UAP_STARTED,
+    CM_UAP_IP_UP,
+};
+
+static struct wifi_scan_params_t g_wifi_scan_params = {NULL,
+                                                       NULL,
+                                                       {
+                                                           0,
+                                                       },
+                                                       BSS_ANY,
+                                                       60,
+                                                       250};
+
+#define CONFIG_WLCMGR_STACK_SIZE (5120)
+
+static void wlcmgr_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(wlcmgr_task, WLAN_TASK_PRI_HIGH, 1, CONFIG_WLCMGR_STACK_SIZE, 0);
+
+#if CONFIG_WPS2
+#define CONFIG_WPS_STACK_SIZE (5120)
+
+static void wps_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(wps_task, WLAN_TASK_PRI_HIGH, 1, CONFIG_WPS_STACK_SIZE, 0);
+
+static int wlcm_wps_callback(enum wps_event event, void *data, uint16_t len);
+
+typedef enum
+{
+    PROV_WPS_NONE,
+    PROV_WPS_STARTED,     /* WPS provisioning started */
+    PROV_WPS_PBC_ENABLED, /* WPS pushbutton attempt enabled */
+    PROV_WPS_PIN_ENABLED, /* WPS PIN attempt enabled */
+    PROV_WPS_SUCCESSFUL,  /* WPS based provisioning successful */
+} wps_state_t;
+
+static struct
+{
+    wps_state_t wps_state;
+    enum wps_session_command wps_cmd;
+    uint32_t wps_pin;
+
+    /* WPS thread */
+    OSA_TASK_HANDLE_DEFINE(wps_task_Handle);
+
+    OSA_SEMAPHORE_HANDLE_DEFINE(wps_scan_done);
+    struct wlan_scan_result wps_res;
+} wlan_wps;
+
+static struct wps_config wps_conf = {
+    .role                    = 1, //WPS_ENROLLEE
+    .pin_generator           = 1,
+    .version                 = 0x20,
+    .version2                = 0x20,
+    .device_name             = "Redfinch",
+    .manufacture             = "NXP",
+    .model_name              = "rw610",
+    .model_number            = "0001",
+    .serial_number           = "0001",
+    .config_methods          = 0x2388,
+    .primary_dev_category    = 01,
+    .primary_dev_subcategory = 01,
+    .rf_bands                = 2,
+    .os_version              = 0xFFFFFFFF,
+    .wps_msg_max_retry       = 5,
+    .wps_msg_timeout         = 5000,
+    .pin_len                 = 8,
+    .wps_callback            = wlcm_wps_callback,
+    .prov_session            = PROV_NON_SESSION_ATTEMPT,
+};
+#endif /* CONFIG_WPS2 */
+#ifdef RW610
+
+#define CONFIG_WLCMGR_MON_STACK_SIZE (2048)
+
+static void wlcmgr_mon_task(osa_task_param_t arg);
+
+/* OSA_TASKS: name, priority, instances, stackSz, useFloat */
+static OSA_TASK_DEFINE(wlcmgr_mon_task, WLAN_TASK_PRI_LOW , 1, CONFIG_WLCMGR_MON_STACK_SIZE, 0);
+
+/* The monitor thread event queue receives events from the power manager
+ * wlan notifier when idle hook is invoked and host is ready to enter
+ * specific low power mode
+ */
+OSA_MSGQ_HANDLE_DEFINE(mon_thread_events, MAX_EVENTS, sizeof(struct wlan_message));
+
+#endif
+typedef enum
+{
+    WLCMGR_INACTIVE,
+    WLCMGR_INIT_DONE,
+    WLCMGR_ACTIVATED,
+    WLCMGR_THREAD_STOPPED,
+    WLCMGR_THREAD_DELETED,
+} wlcmgr_status_t;
+
+static struct
+{
+    /* This lock enables the scan response data to be accessed by multiple
+     * threads with the expectation that any thread accessing the scan lock may
+     * have to sleep until it is available.  The lock is taken by calling
+     * wlan_scan() and it is released by the WLAN Connection Manager main
+     * thread when the scan response data has been handled and
+     * is therefore free for another user.  This lock must never be taken
+     * in the WLAN Connection Manager main thread and it must only be
+     * released by that thread. The lock count must be 0 or 1. */
+    OSA_SEMAPHORE_HANDLE_DEFINE(scan_lock);
+    bool is_scan_lock;
+
+    /* The WLAN Connection Manager event queue receives events (command
+     * responses, WiFi events, TCP stack events) from the wifi interface as
+     * well as user requests (connect, disconnect, scan).  This is the main
+     * blocking point for the main thread and acts as the state machine tick.*/
+    OSA_MSGQ_HANDLE_DEFINE(events, MAX_EVENTS, sizeof(struct wifi_message));
+
+    /* internal state */
+    enum cm_sta_state sta_state, sta_ipv4_state;
+#if CONFIG_IPV6
+    enum cm_sta_state sta_ipv6_state;
+#endif
+    enum cm_sta_state sta_return_to;
+    enum cm_uap_state uap_state;
+    enum cm_uap_state uap_return_to;
+    /* store sta mac addr */
+    uint8_t sta_mac[MLAN_MAC_ADDR_LENGTH];
+    /* store uap mac addr */
+    uint8_t uap_mac[MLAN_MAC_ADDR_LENGTH];
+    /* callbacks */
+    int (*cb)(enum wlan_event_reason reason, void *data);
+    int (*scan_cb)(unsigned int count);
+    void (*event_cb)(int type);
+
+    /* known networks list */
+    struct wlan_network networks[WLAN_MAX_KNOWN_NETWORKS];
+    int cur_network_idx;
+    int cur_uap_network_idx;
+
+    unsigned int num_networks;
+    unsigned int scan_count;
+
+    unsigned int uap_supported_max_sta_num;
+
+    /* CM thread */
+    OSA_TASK_HANDLE_DEFINE(wlcmgr_task_Handle);
+
+    unsigned running : 1;
+    unsigned stop_request : 1;
+    wlcmgr_status_t status;
+
+    /*
+     * Power save state configuration
+     * These are states corresponding to the network that we are currently
+     * connected to. Not relevant, when we are not connected.
+     */
+    bool cm_ieeeps_configured : 1;
+    bool cm_deepsleepps_configured : 1;
+    bool connect_wakelock_taken : 1;
+    unsigned int wakeup_conditions;
+#if CONFIG_HOST_SLEEP
+    bool is_hs_configured : 1;
+#endif
+    bool is_mef_enabled : 1;
+#if (CONFIG_WNM_PS)
+    bool cm_wnmps_configured;
+    t_u16 wnm_sleep_time;
+#endif
+    wifi_fw_version_ext_t fw_ver_ext;
+
+    int uap_rsn_ie_index;
+    bool smart_mode_active : 1;
+#if CONFIG_WPA_SUPP
+    OSA_TIMER_HANDLE_DEFINE(supp_status_timer);
+    bool pending_disconnect_request : 1;
+    int status_timeout;
+    bool connect : 1;
+#if CONFIG_WPA_SUPP_WPS
+    int wps_session_attempt;
+#endif
+#endif
+#if (CONFIG_WPA2_ENTP) || ((CONFIG_WPA_SUPP) && (CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE))
+    t_u8 *ca_cert_data;
+    t_u32 ca_cert_len;
+    t_u8 *client_cert_data;
+    t_u32 client_cert_len;
+    t_u8 *client_key_data;
+    t_u32 client_key_len;
+    t_u8 *ca_cert2_data;
+    t_u32 ca_cert2_len;
+    t_u8 *client_cert2_data;
+    t_u32 client_cert2_len;
+    t_u8 *client_key2_data;
+    t_u32 client_key2_len;
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    t_u8 *dh_data;
+    t_u32 dh_len;
+    t_u8 *server_cert_data;
+    t_u32 server_cert_len;
+    t_u8 *server_key_data;
+    t_u32 server_key_len;
+#endif
+#endif
+#endif
+    OSA_TIMER_HANDLE_DEFINE(assoc_timer);
+    bool assoc_paused : 1;
+    bool pending_assoc_request : 1;
+    bool reassoc_control : 1;
+    bool reassoc_request : 1;
+    unsigned int reassoc_count;
+    bool hs_enabled;
+    unsigned int hs_wakeup_condition;
+    wifi_scan_chan_list_t scan_chan_list;
+#if CONFIG_WPA2_ENTP
+    bool allow_wpa2_enterprise_ap_only : 1;
+#endif
+    bool hidden_scan_on : 1;
+#if CONFIG_ROAMING
+    bool roaming_enabled : 1;
+#endif
+#if CONFIG_11R
+    bool ft_bss : 1;
+#endif
+    bool same_ess : 1;
+    unsigned int bgscan_attempt;
+    bool roam_reassoc : 1;
+#if CONFIG_WIFI_FW_DEBUG
+    void (*wlan_usb_init_cb)(void);
+#endif
+#if defined(SDK_OS_FREE_RTOS)
+#ifdef SD9177
+    OSA_TIMER_HANDLE_DEFINE(poll_timer);
+#endif
+#endif
+#if CONFIG_11R
+#if CONFIG_WPA_SUPP
+    OSA_TIMER_HANDLE_DEFINE(ft_roam_timer);
+#endif
+#endif
+#if CONFIG_11K
+    bool enable_11k : 1;
+    wlan_rrm_scan_cb_param rrm_scan_cb_param;
+#endif
+#if (CONFIG_11K) || (CONFIG_11V)
+    OSA_TIMER_HANDLE_DEFINE(neighbor_req_timer);
+    bool neighbor_req : 1;
+#endif
+#if (CONFIG_11K) || (CONFIG_11V)
+    wlan_nlist_report_param nlist_rep_param;
+    wlan_rrm_neighbor_report_t nbr_rpt;
+#endif
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_11R) || (CONFIG_ROAMING)
+    uint8_t rssi_low_threshold;
+#endif
+    uint8_t ind_reset;
+#if CONFIG_HOST_SLEEP
+    uint8_t hs_dummy_send;
+#endif
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+    uint8_t ir_mode;
+#endif
+    bool internal : 1;
+} wlan;
+
+OSA_TASK_HANDLE_DEFINE(wlcmgr_mon_task_Handle);
+bool wlan_in_reset = false;
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+#define MIN_KEEP_ALIVE_ID 0
+#define MAX_KEEP_ALIVE_ID 4
+wlan_cloud_keep_alive_t cloud_keep_alive_param[MAX_KEEP_ALIVE_ID];
+#endif
+
+void wlan_wake_up_card(void);
+
+#if CONFIG_CSI
+wlan_csi_config_params_t g_csi_params_default = {0};
+#endif
+
+#if CONFIG_WLCMGR_DEBUG
+static char *dbg_sta_state_name(enum cm_sta_state state)
+{
+    switch (state)
+    {
+        case CM_STA_INITIALIZING:
+            return "initializing";
+        case CM_STA_IDLE:
+            return "idle";
+        case CM_STA_SCANNING:
+            return "scanning";
+        case CM_STA_SCANNING_USER:
+            return "user scanning";
+        case CM_STA_ASSOCIATING:
+            return "associating";
+        case CM_STA_ASSOCIATED:
+            return "associated";
+        case CM_STA_AUTHENTICATED:
+            return "authenticated";
+        case CM_STA_REQUESTING_ADDRESS:
+            return "requesting address";
+        case CM_STA_OBTAINING_ADDRESS:
+            return "obtaining address";
+        case CM_STA_CONNECTED:
+            return "connected";
+        default:
+            return "unknown";
+    }
+}
+
+static char *dbg_uap_state_name(enum cm_uap_state state)
+{
+    switch (state)
+    {
+        case CM_UAP_INITIALIZING:
+            return "initializing";
+        case CM_UAP_CONFIGURED:
+            return "configured";
+        case CM_UAP_STARTED:
+            return "started";
+        case CM_UAP_IP_UP:
+            return "IP configured";
+        default:
+            return "unknown";
+    }
+}
+
+static void dbg_lock_info(void)
+{
+#if 0
+	int ret;
+	char *name;
+	unsigned long cur_val, suspended_count;
+	TX_THREAD *first_suspended;
+	TX_SEMAPHORE *next;
+
+	ret = tx_semaphore_info_get(&wlan.scan_lock, &name, &cur_val,
+				    &first_suspended, &suspended_count, &next);
+	if (ret) {
+		wlcm_e("unable to fetch scan lock info");
+		return;
+	}
+
+	wlcm_d("scan lock info: count=%ld, suspended=%ld", cur_val,
+	       suspended_count);
+#endif
+}
+#else
+#define dbg_lock_info(...)
+#define dbg_sta_state_name(...)
+#define dbg_uap_state_name(...)
+#endif /* CONFIG_WLCMGR_DEBUG */
+
+#if CONFIG_WLS_CSI_PROC
+t_u8 g_csi_event_for_wls;
+#endif
+
+/*
+ * Utility Functions
+ */
+
+int verify_scan_duration_value(int scan_duration)
+{
+    if (scan_duration >= 50 && scan_duration <= 500)
+    {
+        return WM_SUCCESS;
+    }
+    return -WM_FAIL;
+}
+
+int verify_scan_channel_value(int channel)
+{
+    if (channel >= 0 && channel <= 11)
+    {
+        return WM_SUCCESS;
+    }
+    return -WM_FAIL;
+}
+
+int verify_split_scan_delay(int delay)
+{
+    if (delay >= 30 && delay <= 300)
+    {
+        return WM_SUCCESS;
+    }
+    return -WM_FAIL;
+}
+
+int set_scan_params(struct wifi_scan_params_t *wifi_scan_params)
+{
+    if (!verify_scan_duration_value(wifi_scan_params->scan_duration))
+    {
+        g_wifi_scan_params.scan_duration = wifi_scan_params->scan_duration;
+    }
+    if (!verify_scan_channel_value(wifi_scan_params->channel[0]))
+    {
+        g_wifi_scan_params.channel[0] = wifi_scan_params->channel[0];
+    }
+    if (!verify_split_scan_delay(wifi_scan_params->split_scan_delay))
+    {
+        g_wifi_scan_params.split_scan_delay = wifi_scan_params->split_scan_delay;
+    }
+    return WM_SUCCESS;
+}
+
+#if CONFIG_RX_ABORT_CFG
+int wlan_set_get_rx_abort_cfg(struct wlan_rx_abort_cfg *cfg, t_u16 action)
+{
+    return wifi_set_get_rx_abort_cfg((void *)cfg, action);
+}
+#endif
+
+#if CONFIG_RX_ABORT_CFG_EXT
+int wlan_set_rx_abort_cfg_ext(const struct wlan_rx_abort_cfg_ext *cfg)
+{
+    return wifi_set_get_rx_abort_cfg_ext((void *)cfg, ACTION_SET);
+}
+
+int wlan_get_rx_abort_cfg_ext(struct wlan_rx_abort_cfg_ext *cfg)
+{
+    return wifi_set_get_rx_abort_cfg_ext((void *)cfg, ACTION_GET);
+}
+#endif
+
+#if CONFIG_CCK_DESENSE_CFG
+int wlan_set_get_cck_desense_cfg(struct wlan_cck_desense_cfg *cfg, t_u16 action)
+{
+    return wifi_set_get_cck_desense_cfg((void *)cfg, action);
+}
+#endif
+
+int get_scan_params(struct wifi_scan_params_t *wifi_scan_params)
+{
+    wifi_scan_params->scan_duration    = g_wifi_scan_params.scan_duration;
+    wifi_scan_params->channel[0]       = g_wifi_scan_params.channel[0];
+    wifi_scan_params->split_scan_delay = g_wifi_scan_params.split_scan_delay;
+    return WM_SUCCESS;
+}
+
+void wlan_dhcp_cleanup()
+{
+#if defined(SDK_OS_FREE_RTOS)
+    net_stop_dhcp_timer();
+#endif
+    net_interface_dhcp_stop(net_get_mlan_handle());
+#ifndef __ZEPHYR__
+    net_interface_dhcp_cleanup(net_get_mlan_handle());
+#endif
+}
+
+#if CONFIG_HOST_SLEEP
+static uint32_t wlan_map_to_wifi_wakeup_condtions(const uint32_t wlan_wakeup_condtions)
+{
+    uint32_t conditions = 0;
+    if ((wlan_wakeup_condtions & WAKE_ON_UNICAST) != 0U)
+    {
+        conditions |= WIFI_WAKE_ON_UNICAST;
+    }
+
+    if ((wlan_wakeup_condtions & WAKE_ON_ALL_BROADCAST) != 0U)
+    {
+        conditions |= WIFI_WAKE_ON_ALL_BROADCAST;
+    }
+
+    if ((wlan_wakeup_condtions & WAKE_ON_MULTICAST) != 0U)
+    {
+        conditions |= WIFI_WAKE_ON_MULTICAST;
+    }
+
+    if ((wlan_wakeup_condtions & WAKE_ON_ARP_BROADCAST) != 0U)
+    {
+        conditions |= WIFI_WAKE_ON_ARP_BROADCAST;
+    }
+
+    if ((wlan_wakeup_condtions & WAKE_ON_MAC_EVENT) != 0U)
+    {
+        conditions |= WIFI_WAKE_ON_MAC_EVENT;
+    }
+
+    if ((wlan_wakeup_condtions & WAKE_ON_MGMT_FRAME) != 0U)
+    {
+        conditions |= WIFI_WAKE_ON_MGMT_FRAME;
+    }
+
+    return conditions;
+}
+#endif
+
+int wlan_is_started(void)
+{
+    return ((wlan.running == 1) && (wlan.status == WLCMGR_ACTIVATED));
+}
+
+static bool is_user_scanning(void)
+{
+    return (wlan.sta_state == CM_STA_SCANNING_USER);
+}
+
+static bool is_state(enum cm_sta_state state)
+{
+    if (is_user_scanning() == true)
+    {
+        return (wlan.sta_return_to == state);
+    }
+
+    return (wlan.sta_state == state);
+}
+
+static bool is_uap_state(enum cm_uap_state state)
+{
+    return (wlan.uap_state == state);
+}
+
+static int wlan_get_ipv4_addr(unsigned int *ipv4_addr)
+{
+    struct wlan_network* network = NULL;
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+    {
+        network = &wlan.networks[wlan.cur_network_idx];
+    }
+
+    if (network == NULL)
+    {
+        wlcm_e("cannot get network info");
+        *ipv4_addr = 0;
+        return -WM_FAIL;
+    }
+
+    *ipv4_addr = network->ip.ipv4.address;
+
+    return WM_SUCCESS;
+}
+
+static int wlan_get_uap_ipv4_addr(unsigned int *ipv4_addr)
+{
+    struct wlan_network* network = NULL;
+
+    if (wlan.running && (is_uap_state(CM_UAP_IP_UP) || is_uap_state(CM_UAP_STARTED)))
+    {
+        network = &wlan.networks[wlan.cur_uap_network_idx];
+    }
+
+    if (network == NULL)
+    {
+        wlcm_e("cannot get uap network info");
+        *ipv4_addr = 0;
+        return -WM_FAIL;
+    }
+
+    *ipv4_addr = network->ip.ipv4.address;
+
+    return WM_SUCCESS;
+}
+
+static int wlan_set_pmfcfg(uint8_t mfpc, uint8_t mfpr);
+
+#if CONFIG_HOST_SLEEP
+static int wlan_send_host_sleep_int(uint32_t wake_up_conds, bool is_config)
+{
+    int ret = WM_SUCCESS;
+    unsigned int ipv4_addr = 0;
+    enum wlan_bss_type type = WLAN_BSS_TYPE_STA;
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Wakeup condition configure is not allowed when WIFI is disabled\r\n");
+        return -WM_FAIL;
+    }
+
+    /* Check if wake_up_conds is valid or not */
+    if (wake_up_conds && (wake_up_conds != HOST_SLEEP_CFG_CANCEL) && (wake_up_conds & 0x20))
+    {
+        (void)PRINTF("Invalid wake_up_conds. Bit 5 is reserved.\r\n");
+        return -WM_FAIL;
+    }
+
+    if (!is_sta_connected() && !mlan_adap->priv[1]->media_connected)
+    {
+        if ((wake_up_conds & (WAKE_ON_ALL_BROADCAST | WAKE_ON_UNICAST | WAKE_ON_MULTICAST
+                                   | WAKE_ON_ARP_BROADCAST | WAKE_ON_MGMT_FRAME)) != 0)
+        {
+            wlcm_e("Connection on STA or uAP is required for configured bitmap!\r\n");
+            ret = -WM_FAIL;
+            return ret;
+        }
+    }
+
+    if (wake_up_conds == HOST_SLEEP_CFG_CANCEL)
+    {
+        wlan.hs_enabled = MFALSE;
+        wlan.hs_wakeup_condition = wake_up_conds;
+        wlan.is_mef_enabled = MFALSE;
+        (void)memset(&g_flt_cfg, 0, sizeof(wlan_flt_cfg_t));
+        wifi_set_packet_filters(&g_flt_cfg);
+    }
+#if CONFIG_CLOUD_KEEP_ALIVE
+    else if(is_config == MFALSE)
+    {
+        wlan_start_cloud_keep_alive();
+    }
+#endif
+
+#ifndef RW610
+    if (wake_up_conds == HOST_SLEEP_NO_COND)
+    {
+        wlan.hs_enabled = MTRUE;
+        wlan.hs_wakeup_condition = wake_up_conds;
+        if (g_flt_cfg.nentries == 0 && (is_config == MFALSE))
+        {
+            (void)PRINTF("No user configured MEF entries, use default ARP filters.\r\n");
+            /* User doesn't configure MEF, use default MEF entry */
+            wlan_mef_set_auto_arp(MEF_ACTION_ALLOW_AND_WAKEUP_HOST);
+        }
+        if (wlan.is_mef_enabled == MFALSE)
+        {
+            wlan.is_mef_enabled = MTRUE;
+            wifi_set_packet_filters(&g_flt_cfg);
+        }
+    }
+    else
+#endif
+    {
+        wlan.hs_enabled = MTRUE;
+        wlan.hs_wakeup_condition = wlan_map_to_wifi_wakeup_condtions(wake_up_conds);
+    }
+
+    if (is_sta_ipv4_connected() != 0)
+    {
+        ret = wlan_get_ipv4_addr(&ipv4_addr);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("HS: cannot get STA IP, check if STA disconnected");
+            return -WM_FAIL;
+        }
+    }
+    else if (is_uap_started())
+    {
+        ret = wlan_get_uap_ipv4_addr(&ipv4_addr);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("HS: cannot get UAP IP, check if uAP stopped");
+            return -WM_FAIL;
+        }
+        type = WLAN_BSS_TYPE_UAP;
+    }
+    else
+    {
+        ipv4_addr = 0;
+    }
+
+    if (wlan.hs_dummy_send == MFALSE || is_config == MFALSE)
+    {
+        wifi_send_hs_cfg_cmd((mlan_bss_type)type, ipv4_addr, HS_CONFIGURE, wlan.hs_wakeup_condition);
+        wlan.hs_dummy_send = MTRUE;
+    }
+    return ret;
+}
+
+void wlan_hs_pre_cfg(void)
+{
+    if (wlan.hs_enabled == MTRUE)
+    {
+        (void)wlan_send_host_sleep_int(wlan.hs_wakeup_condition, MFALSE);
+        /** Wait for HS Activate to complete */
+        OSA_TimeDelay(1000);
+    }
+}
+
+void wlan_hs_post_cfg(void)
+{
+    uint16_t hs_wakeup_reason;
+
+    if (wlan.hs_enabled == MTRUE)
+    {
+        (void)wifi_get_wakeup_reason(&hs_wakeup_reason);
+
+        (void)wifi_print_wakeup_reason(hs_wakeup_reason);
+    }
+}
+
+int wlan_send_host_sleep(uint32_t wake_up_conds)
+{
+    if (!wlan.running)
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    wakelock_get();
+
+    (void)send_user_request(CM_STA_USER_REQUEST_HS, wake_up_conds);
+
+    return WM_SUCCESS;
+}
+
+int wlan_get_wakeup_reason(uint16_t *hs_wakeup_reason)
+{
+    return wifi_get_wakeup_reason(hs_wakeup_reason);
+}
+
+#endif
+
+#if CONFIG_HOST_SLEEP
+#ifdef RW610
+status_t wlan_hs_send_event(int id, void *data)
+{
+    struct wlan_message msg;
+
+    (void)memset(&msg, 0U, sizeof(struct wlan_message));
+    msg.data = data;
+    msg.id  = id;
+    if (OSA_MsgQPut((osa_msgq_handle_t)mon_thread_events, &msg) != KOSA_StatusSuccess)
+    {
+        (void)PRINTF("PM: Failed to send msg to queue\r\n");
+#ifdef __ZEPHYR__
+        return -WM_FAIL;
+#else
+        return kStatus_Fail;
+#endif
+    }
+#ifdef __ZEPHYR__
+    return WM_SUCCESS;
+#else
+    return kStatus_Success;
+#endif
+}
+#endif
+
+#if CONFIG_POWER_MANAGER
+#if (!CONFIG_WIFI_BLE_COEX_APP) && (!CONFIG_NCP_BLE)
+static void wake_timer_cb(osa_timer_arg_t arg)
+{
+    if(wakelock_isheld())
+        wakelock_put();
+}
+#endif
+
+#ifndef __ZEPHYR__
+status_t powerManager_WlanNotify(pm_event_type_t eventType, uint8_t powerState, void *data)
+{
+    int ret;
+
+    if (eventType == kPM_EventEnteringSleep
+#ifdef RW610
+            && powerState > PM_LP_STATE_PM0
+#endif
+            )
+    {
+        /* Entering low power mode is not allowed in any of below conditions:
+         * 1. Host sleep is disabled
+         * 2. wlan initialization is still on going
+         * 3. wakelock is held by any task
+         * 4. Host sleep handshake is on going or fail
+         * 5. UAPSD/PPS is activated
+         */
+        if (!wlan_host_sleep_state || wlan.status != WLCMGR_ACTIVATED ||
+            wakelock_isheld()
+#if CONFIG_WMM_UAPSD
+            || mlan_adap->pps_uapsd_mode
+#endif
+            )
+            return kStatus_PMPowerStateNotAllowed;
+#ifdef RW610
+        /* Skip host sleep handshake for PM1 */
+        if (powerState == PM_LP_STATE_PM1)
+            goto done;
+#endif
+        if (!is_hs_handshake_done)
+        {
+            is_hs_handshake_done = WLAN_HOSTSLEEP_IN_PROCESS;
+            ret = wlan_hs_send_event(HOST_SLEEP_HANDSHAKE, NULL);
+            if (ret != 0)
+                return kStatus_PMNotifyEventError;
+            return kStatus_PMPowerStateNotAllowed;
+        }
+        /* If hanshake is still in process, entring low power mode is not allowed */
+        if (is_hs_handshake_done == WLAN_HOSTSLEEP_IN_PROCESS)
+            return kStatus_PMPowerStateNotAllowed;
+        if (is_hs_handshake_done == WLAN_HOSTSLEEP_FAIL)
+        {
+            is_hs_handshake_done = 0;
+            return kStatus_PMNotifyEventError;
+        }
+#ifdef RW610
+#if !(CONFIG_WIFI_BLE_COEX_APP) && !(CONFIG_NCP)
+        ret = host_sleep_pre_cfg((int)powerState);
+        if(ret != 0)
+        {
+            return kStatus_PMPowerStateNotAllowed;
+        }
+#endif
+        wlan_hs_pre_cfg_done = true;
+#endif
+    }
+    else if (eventType == kPM_EventExitingSleep)
+    {
+#ifdef RW610
+        /* Skip host sleep handshake for PM1 */
+        if (powerState == PM_LP_STATE_PM1)
+            goto done;
+#endif
+        if (is_hs_handshake_done == WLAN_HOSTSLEEP_SUCCESS && wlan_hs_pre_cfg_done == true)
+        {
+            ret = wlan_hs_send_event(HOST_SLEEP_EXIT, NULL);
+            if (ret != 0)
+                return kStatus_PMNotifyEventError;
+            /* reset hs hanshake flag after waking up */
+            is_hs_handshake_done = 0;
+            wlan_hs_pre_cfg_done = false;
+#if !(CONFIG_WIFI_BLE_COEX_APP) && !(CONFIG_NCP)
+#ifdef RW610
+            host_sleep_post_cfg((int)powerState);
+#endif
+            /* If periodic host sleep is not enabled, reset the flag to disable host sleep */
+            if (wlan_host_sleep_state == HOST_SLEEP_ONESHOT)
+                wlan_host_sleep_state = HOST_SLEEP_DISABLE;
+#endif
+        }
+    }
+#ifdef RW610
+done:
+#endif
+    return kStatus_PMSuccess;
+}
+#endif
+#endif
+
+int wlan_wowlan_config(uint8_t is_mef, t_u32 wake_up_conds)
+{
+    int ret = WM_SUCCESS;
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Wakeup condition configure is not allowed when WIFI is disabled\r\n");
+        return -WM_FAIL;
+    }
+
+    /* Check if wake_up_conds is valid or not */
+    if (wake_up_conds && (wake_up_conds & 0x20))
+    {
+        (void)PRINTF("Invalid wake_up_conds. Bit 5 is reserved.\r\n");
+        return -WM_FAIL;
+    }
+
+    if (!is_sta_connected() && !mlan_adap->priv[1]->media_connected)
+    {
+        if (is_mef)
+        {
+            wlcm_e("Connection on STA or uAP is required for MEF configuration\r\n");
+            ret = -WM_FAIL;
+            return ret;
+        }
+        else
+             if ((wake_up_conds & (WAKE_ON_ALL_BROADCAST | WAKE_ON_UNICAST | WAKE_ON_MULTICAST
+                                   | WAKE_ON_ARP_BROADCAST | WAKE_ON_MGMT_FRAME)) != 0)
+        {
+            wlcm_e("Connection on STA or uAP is required for configured bitmap!\r\n");
+            ret = -WM_FAIL;
+            return ret;
+        }
+    }
+
+    if (is_mef)
+    {
+        wlan.wakeup_conditions = 0;
+        if (g_flt_cfg.nentries == 0)
+        {
+            (void)PRINTF("No user configured MEF entries, use default ARP filters.\r\n");
+            /* User doesn't configure MEF, use default MEF entry */
+            wlan_mef_set_auto_arp(MEF_ACTION_ALLOW_AND_WAKEUP_HOST);
+        }
+        wifi_set_packet_filters(&g_flt_cfg);
+    }
+    else
+    {
+        wlan.wakeup_conditions = wake_up_conds;
+        if (wake_up_conds & WIFI_WAKE_ON_MGMT_FRAME)
+        {
+          /* Set management frame wakeup filter config */
+          mlan_adap->mgmt_filter[0].action     = 0x3;      /* not discard packet, wakeup host */
+          mlan_adap->mgmt_filter[0].type       = 0xff;     /* management frames */
+          mlan_adap->mgmt_filter[0].frame_mask = 0x3C0F;   /* Frame-Mask bits :
+                                                              : Bit 0 - Association Request(unmask)
+                                                              : Bit 1 - Association Response(unmask)
+                                                              : Bit 2 - Re-Association Request(unmask)
+                                                              : Bit 3 - Re-Association Response(unmask)
+                                                              : Bit 4 - Probe Request(mask)
+                                                              : Bit 5 - Probe Response(mask)
+                                                              : Bit 8 - Beacon Frames(mask)
+                                                              : Bit 10 - Disassociation(unmask)
+                                                              : Bit 11 - Authentication(unmask)
+                                                              : Bit 12 - Deauthentication(unmask)
+                                                              : Bit 13 - Action Frames(unmask)
+                                                            */
+        }
+        /* Clear previous MEF entries */
+        if (g_flt_cfg.nentries != 0)
+        {
+            (void)memset(&g_flt_cfg, 0, sizeof(wlan_flt_cfg_t));
+            wifi_set_packet_filters(&g_flt_cfg);
+        }
+    }
+
+    return ret;
+}
+
+void wlan_config_host_sleep(bool is_manual, t_u8 is_periodic)
+{
+    int ret = 0;
+
+#if CONFIG_WMM_UAPSD
+    if (mlan_adap && mlan_adap->pps_uapsd_mode)
+    {
+        wlcm_e("Host sleep is not allowed if UAPSD/PPS is activated");
+        return;
+    }
+#endif
+    wlan_is_manual = is_manual;
+    if (!wlan_is_manual)
+    {
+#if CONFIG_POWER_MANAGER
+	if (!wlan_is_started())
+        {
+            wlcm_e("Host sleep is not allowed when WIFI is disabled\r\n");
+            return;
+        }
+        if (is_periodic)
+            wlan_host_sleep_state = HOST_SLEEP_PERIODIC;
+        else
+            wlan_host_sleep_state = HOST_SLEEP_ONESHOT;
+#endif
+    }
+    else
+    {
+#if CONFIG_POWER_MANAGER
+        /* Reset flag and stop timer if manual mode is selected without cancel periodic sleep */
+        wlan_host_sleep_state = HOST_SLEEP_DISABLE;
+#if (!CONFIG_WIFI_BLE_COEX_APP) && (!CONFIG_NCP_BLE)
+        if (OSA_TimerIsRunning((osa_timer_handle_t)wake_timer))
+        {
+            OSA_TimerDeactivate((osa_timer_handle_t)wake_timer);
+            wakelock_put();
+        }
+#endif
+#endif
+        if (wlan.status == WLCMGR_ACTIVATED)
+        {
+#if CONFIG_HOST_SLEEP
+            /* Start host sleep handshake here if manual mode is selected */
+            ret = wlan_send_host_sleep_int(wlan.wakeup_conditions, MFALSE);
+            if (ret != WM_SUCCESS)
+            {
+#if CONFIG_NCP
+                app_notify_event(APP_EVT_HS_CONFIG, APP_EVT_REASON_FAILURE, NULL, 0);
+#endif
+                wlcm_e("Error: Failed to config host sleep");
+                return;
+            }
+#endif
+        }
+    }
+}
+
+void wlan_cancel_host_sleep(void)
+{
+    int ret = 0;
+    enum wlan_bss_type type = WLAN_BSS_TYPE_STA;
+
+    if (!wlan_is_started())
+    {
+        PRINTF("Wlan not started, can't cancel host sleep\r\n");
+        return;
+    }
+
+    if (is_uap_started() != 0)
+        type = WLAN_BSS_TYPE_UAP;
+    ret = wifi_cancel_host_sleep((mlan_bss_type)type);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Error: Failed to send host sleep cancel command");
+        return;
+    }
+}
+
+void wlan_clear_host_sleep_config(void)
+{
+    wlan_is_manual = MFALSE;
+#if CONFIG_POWER_MANAGER
+    wlan_host_sleep_state = HOST_SLEEP_DISABLE;
+#if CONFIG_UART_INTERRUPT
+    usart_suspend_flag = MFALSE;
+#endif
+#if (!CONFIG_WIFI_BLE_COEX_APP) && (!CONFIG_NCP_BLE)
+    if (OSA_TimerIsRunning((osa_timer_handle_t)wake_timer))
+    {
+        OSA_TimerDeactivate((osa_timer_handle_t)wake_timer);
+        wakelock_put();
+    }
+#endif
+    is_hs_handshake_done = 0;
+#endif
+    memset(&g_flt_cfg, 0x0, sizeof(wlan_flt_cfg_t));
+
+    if (wlan_is_started())
+    {
+	wifi_set_packet_filters(&g_flt_cfg);
+    }
+    wakeup_by = 0;
+    wifi_clear_wakeup_reason();
+    wlan.wakeup_conditions = 0;
+    wlan.is_hs_configured = MFALSE;
+}
+#endif
+
+static void wlan_send_sleep_confirm(void)
+{
+    enum wlan_bss_type type = WLAN_BSS_TYPE_STA;
+
+    if (is_uap_started() != 0)
+    {
+        type = WLAN_BSS_TYPE_UAP;
+    }
+
+    send_sleep_confirm_command((mlan_bss_type)type);
+}
+
+static int is_bssid_any(char *b)
+{
+    return (int)(!b[0] && !b[1] && !b[2] && !b[3] && !b[4] && !b[5]);
+}
+
+/* Check to see if the security features of our network, 'config', match with
+ * those of a scan result, 'res' and return 1 if they do, 0 if they do not. */
+static int security_profile_matches(const struct wlan_network *network, const struct wifi_scan_result2 *res)
+{
+    const struct wlan_network_security *config = &network->security;
+
+    /* No security: just check that the scan result doesn't specify security */
+    if (config->type == WLAN_SECURITY_NONE)
+    {
+#if CONFIG_WPS2
+        if (res->wps_session != WPS_SESSION_INACTIVE)
+            return 1;
+#endif
+#if CONFIG_DRIVER_OWE
+        if (res->trans_mode == OWE_TRANS_MODE_OPEN)
+        {
+            return res->trans_ssid_len;
+        }
+        else if (res->trans_mode == OWE_TRANS_MODE_OWE)
+        {
+            return res->WPA_WPA2_WEP.wpa2;
+        }
+        else
+        { /* Do Nothing */
+        }
+#endif
+
+        if (res->WPA_WPA2_WEP.wepStatic || res->WPA_WPA2_WEP.wpa2 || res->WPA_WPA2_WEP.wpa)
+        {
+            return WM_SUCCESS;
+        }
+
+        return 1;
+    }
+
+    /* WEP mode: if we are using WEP, the AP must use static WEP */
+    if (config->type == WLAN_SECURITY_WEP_OPEN || config->type == WLAN_SECURITY_WEP_SHARED)
+    {
+        if (res->phtcap_ie_present)
+        {
+            wlcm_e(
+                "As per Wi-Fi Certification WEP "
+                "is not used with HT associations "
+                "in 11n devices");
+            return 0;
+        }
+        return (int)res->WPA_WPA2_WEP.wepStatic;
+    }
+
+    /* WPA/WPA2 mode: if we are using WPA/WPA2, the AP must use WPA/WPA2 */
+    if (config->type == WLAN_SECURITY_WPA_WPA2_MIXED)
+    {
+        return (int)(res->WPA_WPA2_WEP.wpa | res->WPA_WPA2_WEP.wpa2);
+    }
+
+    /* WPA2 mode: if we are using WPA2, the AP must use WPA2 */
+    if (config->type == WLAN_SECURITY_WPA2)
+    {
+        return (int)(res->WPA_WPA2_WEP.wpa2 | res->WPA_WPA2_WEP.wpa2_sha256);
+
+    }
+
+#if CONFIG_11R
+    /* WPA2_FT mode: if we are using WPA2, the AP must use WPA2_FT */
+    if (config->type == WLAN_SECURITY_WPA2_FT)
+    {
+        return (int)(res->WPA_WPA2_WEP.ft_psk);
+
+    }
+#endif
+
+    /* OWE mode: if we are using OWE, the AP must use OWE */
+#if CONFIG_DRIVER_OWE
+    if (config->type == WLAN_SECURITY_OWE_ONLY)
+    {
+        return (int)res->WPA_WPA2_WEP.owe;
+    }
+#endif
+
+    /* WPA mode: if we are using WPA, the AP must use WPA */
+    if (config->type == WLAN_SECURITY_WPA)
+    {
+        if (res->wpa_ucstCipher.tkip != 0U)
+        {
+            wlcm_e(
+                "As per Wi-Fi Certification security "
+                "combinations \"WPA\" alone is not allowed "
+                "security type.");
+            wlcm_e(
+                "Please use WLAN_SECURITY_WPA_WPA2_MIXED "
+                "security type to connect to "
+                "WPA(TKIP) Only AP.");
+            return (int)!res->wpa_ucstCipher.tkip;
+        }
+        return (int)res->WPA_WPA2_WEP.wpa;
+    }
+
+#if CONFIG_WPA2_ENTP
+    /* WPA2 Enterprise mode: if we are using WPA2 Enterprise,
+     * the AP must use WPA2 Enterpise */
+    if (config->type == WLAN_SECURITY_EAP_TLS || config->type == WLAN_SECURITY_EAP_PEAP_MSCHAPV2)
+        return res->wpa2_entp_IE_exist;
+#endif
+
+    if ((config->type == WLAN_SECURITY_WPA3_SAE) || (config->type == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED))
+    {
+        uint8_t mfpc, mfpr;
+
+        (void)wlan_get_pmfcfg(&mfpc, &mfpr);
+
+        if (!mfpc && !mfpr)
+        {
+            wlcm_e("As per WPA3 SAE Certification, PMF is mandatory.\r\n");
+            return WM_SUCCESS;
+        }
+        if (config->type == WLAN_SECURITY_WPA3_SAE)
+            return (int)(res->WPA_WPA2_WEP.wpa3_sae);
+        if (config->type == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED)
+            return (int)(res->WPA_WPA2_WEP.wpa3_sae | res->WPA_WPA2_WEP.wpa2 | res->WPA_WPA2_WEP.wpa2_sha256);
+    }
+    return WM_SUCCESS;
+}
+
+/* Check if 'network' matches the scan result 'res' based on network properties
+ * and the security profile.  If we found a match, update 'network' with any
+ * new information discovered when parsing 'res'. 192 We may update the channel,
+ * BSSID, or SSID but not the security profile. */
+static int network_matches_scan_result(const struct wlan_network *network,
+                                       const struct wifi_scan_result2 *res,
+                                       uint8_t *num_channels,
+                                       wlan_scan_channel_list_t *chan_list)
+{
+    uint8_t null_ssid[IEEEtypes_SSID_SIZE] = {0};
+    uint16_t idx = 0;
+
+#if CONFIG_11V
+    if ((wlan.roam_reassoc == true) && (wlan.nlist_rep_param.nlist_mode == WLAN_NLIST_11V) &&
+        ((wlan.nlist_rep_param.btm_mode & 0x1C) != 0U))
+    {
+        if (memcmp((const void *)network->bssid, (const void *)res->bssid, (size_t)IEEEtypes_ADDRESS_SIZE) == 0)
+        {
+            return -WM_FAIL;
+        }
+    }
+#endif
+    /* Check basic network information that we know */
+    if (network->channel_specific && network->channel != res->Channel)
+    {
+        wlcm_d("%s: Channel mismatch. Got: %d Expected: %d", network->ssid, res->Channel, network->channel);
+        return -WM_FAIL;
+    }
+    if (network->bssid_specific && memcmp(network->bssid, res->bssid, 6))
+    {
+        wlcm_d("%s: bssid mismatch.", network->ssid);
+        return -WM_FAIL;
+    }
+
+    if (network->ssid_specific != 0U)
+    {
+        if (!wlan.hidden_scan_on && (!memcmp(null_ssid, (const char *)res->ssid, (size_t)res->ssid_len)))
+        {
+            chan_list[*num_channels].chan_number = res->Channel;
+            chan_list[*num_channels].scan_type   = MLAN_SCAN_TYPE_ACTIVE;
+            chan_list[*num_channels].scan_time   = 150;
+            (*num_channels)++;
+        }
+        if ((res->ssid_len == 0) ||
+            (strncmp((const char *)network->ssid, (const char *)res->ssid,
+                     (size_t)MAX(strlen(network->ssid), (unsigned int)res->ssid_len)) != 0)
+#if CONFIG_DRIVER_OWE
+            || ((res->trans_mode == OWE_TRANS_MODE_OWE) &&
+                (strncmp((const char *)network->trans_ssid, (const char *)res->ssid,
+                         (size_t)MAX(strlen(network->trans_ssid), (unsigned int)res->ssid_len))) != 0)
+#endif
+        )
+        {
+            wlcm_d("ssid mismatch: Got: %s Expected: %s", (char *)res->ssid, network->ssid);
+            return -WM_FAIL;
+        }
+    }
+
+    /* In case of CONFIG_WD_EXTERAL we don't parse and
+       store the security profile.
+       Instead the respective IE are stored in network struct as is */
+    /* Check security information */
+    if (network->security_specific != 0U)
+    {
+        if (!security_profile_matches(network, res))
+        {
+            wlcm_d("%s: security profile mismatch", network->ssid);
+            return -WM_FAIL;
+        }
+    }
+
+    if (!(res->WPA_WPA2_WEP.wepStatic || res->WPA_WPA2_WEP.wpa3_sae || res->WPA_WPA2_WEP.wpa2 || res->WPA_WPA2_WEP.wpa || res->WPA_WPA2_WEP.wpa2_sha256) && (network->security.psk_len || network->security.password_len))
+    {
+        wlcm_d("%s: security profile mismatch", network->ssid);
+        return -WM_FAIL;
+    }
+
+    if (!wifi_11d_is_channel_allowed((int)res->Channel))
+    {
+        wlcm_d("%d: Channel not allowed.", res->Channel);
+        return -WM_FAIL;
+    }
+
+    if ((res->ap_pwe != network->security.pwe_derivation) && ((res->ap_pwe | network->security.pwe_derivation) == 1))
+    {
+        wlcm_d("%d: H2E configuration mismatch", res->ap_pwe);
+        return -WM_FAIL;
+    }
+#if CONFIG_DRIVER_MBO
+    if (res->mbo_assoc_disallowed)
+    {
+        wlcm_d("%s: MBO Association disallowed.", network->ssid);
+        return -WM_FAIL;
+    }
+#endif
+
+#if CONFIG_DRIVER_OWE
+    wlcm_d("%s: Match successful", res->trans_mode == OWE_TRANS_MODE_OWE ? network->trans_ssid : network->ssid);
+#endif
+    /* If the bss blacklist is not empty, check whether the network is in the blacklist or not. */
+    /* If yes, skip this network. */
+    if(mlan_adap->blacklist_bss.num_bssid)
+    {
+        for(idx = 0; idx < mlan_adap->blacklist_bss.num_bssid; idx++)
+        {
+            if(!memcmp(res->bssid, mlan_adap->blacklist_bss.bssids[idx], MLAN_MAC_ADDR_LENGTH))
+            {
+                wlcm_d("%02X:%02X:%02X:%02X:%02X:%02X : BSSID is not allowed.", res->bssid[0], res->bssid[1], res->bssid[2],
+                       res->bssid[3], res->bssid[4], res->bssid[5]);
+                return WM_SUCCESS;
+            }
+        }
+    }
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPA2_ENTP
+static int wpa2_tls_init(struct wlan_network *network)
+{
+    network->security.wlan_ctx =
+        wm_mbedtls_ssl_config_new(&network->security.tls_cert, MBEDTLS_SSL_IS_CLIENT, MBEDTLS_SSL_VERIFY_NONE);
+
+    if (!network->security.wlan_ctx)
+    {
+        wlcm_e("TLS session init failed (ctx failed)");
+        return -WM_FAIL;
+    }
+
+    network->security.wlan_ssl = wm_mbedtls_ssl_new(network->security.wlan_ctx, 0, NULL);
+
+    if (!network->security.wlan_ssl)
+    {
+        wlcm_e("TLS session init failed (ssl failed)");
+        wm_mbedtls_ssl_config_free(network->security.wlan_ctx);
+        network->security.wlan_ctx = NULL;
+        return -WM_FAIL;
+    }
+
+    /* Disable SSL application data splitting as FreeRADIUS fails to
+     * process splitted data
+     */
+    mbedtls_ssl_conf_cbc_record_splitting(network->security.wlan_ctx, MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED);
+
+    return WM_SUCCESS;
+}
+
+static void wpa2_tls_cleanup(struct wlan_network *network, bool force)
+{
+    if (force)
+    {
+        if (network->security.wlan_ssl)
+        {
+            wm_mbedtls_ssl_free(network->security.wlan_ssl);
+            network->security.wlan_ssl = NULL;
+            if (network->security.wlan_ctx)
+            {
+                wm_mbedtls_ssl_config_free(network->security.wlan_ctx);
+                network->security.wlan_ctx = NULL;
+            }
+        }
+    }
+
+    wpa2_shutdown();
+    wlan_set_prov_session(PROV_NON_SESSION_ATTEMPT);
+}
+#endif
+
+static void wlcm_request_reconnect(enum cm_sta_state *next, struct wlan_network *network);
+int load_wep_key(const uint8_t *input, uint8_t *output, uint8_t *output_len, const unsigned max_output_len);
+
+/* Configure the firmware and PSK Supplicant for the security settings
+ * specified in 'network'.  For WPA and WPA2 networks, we must chose between
+ * the older TKIP cipher or the newer CCMP cipher.  We prefer CCMP, however we
+ * will chose TKIP if the AP doesn't report CCMP support.  CCMP is optional for
+ * WPA and required for WPA2, however a WPA2 AP may still have it disabled. */
+static int configure_security(struct wlan_network *network, struct wifi_scan_result2 *res)
+{
+    int ret = WM_SUCCESS;
+    switch (network->security.type)
+    {
+#if CONFIG_WPA2_ENTP
+        case WLAN_SECURITY_EAP_TLS:
+        case WLAN_SECURITY_EAP_PEAP_MSCHAPV2:
+            if (network->security.pmk_valid == false)
+            {
+                wlan_set_prov_session(PROV_ENTP_SESSION_ATTEMPT);
+                ret = wpa2_tls_init(network);
+                if (ret != WM_SUCCESS)
+                    return -WM_FAIL;
+            }
+
+            ret                 = wifi_send_enable_supplicant(network->role, network->ssid);
+            if (ret != WM_SUCCESS)
+                return -WM_FAIL;
+
+            break;
+#endif
+        case WLAN_SECURITY_WPA:
+        case WLAN_SECURITY_WPA2:
+        case WLAN_SECURITY_WPA_WPA2_MIXED:
+#if CONFIG_11R
+        case WLAN_SECURITY_WPA2_FT:
+#endif
+#if CONFIG_WPS2
+            wlan_set_prov_session(PROV_NON_SESSION_ATTEMPT);
+#endif
+            if (network->security.type == WLAN_SECURITY_WPA)
+            {
+                wlcm_d("configuring WPA security");
+            }
+            else if (network->security.type == WLAN_SECURITY_WPA2)
+            {
+                wlcm_d("configuring WPA2 security");
+            }
+            else
+            {
+                wlcm_d("configuring WPA/WPA2 Mixed security");
+            }
+
+            /* the handler for the "add PSK" command calls supplicantEnable() so we
+             * don't do it here
+             *
+             * TODO: at this time, the firmware will not generate a specific
+             * response to the command sent by wifi_add_wpa_psk().  The
+             * command+response sequence should be worked into the WLAN Connection
+             * Manager once this is fixed.
+             *
+             * TODO: at this time, the PSK Supplicant caches passphrases on the
+             * SSID however this won't work for networks with a hidden SSID.  The
+             * WLAN Connection manager will need to be updated once that's
+             * resolved. */
+            if (network->security.pmk_valid)
+            {
+                wlcm_d("adding SSID and PMK to supplicant cache");
+
+                /* Do not pass BSSID here as embedded supplicant fails
+                 * to derive session keys
+                 */
+                ret = wifi_send_add_wpa_pmk((int)network->role, network->ssid, NULL, network->security.pmk,
+                                            WLAN_PMK_LENGTH);
+            }
+            else
+            {
+#if CONFIG_11R
+                if (!wlan.ft_bss)
+#endif
+                {
+                    wlcm_d("adding SSID and PSK to supplicant cache");
+                    ret = wifi_send_add_wpa_psk((int)network->role, network->ssid, network->security.psk,
+                                                (unsigned int)network->security.psk_len);
+                }
+            }
+
+            if (ret != WM_SUCCESS)
+            {
+                return -WM_FAIL;
+            }
+            break;
+#if CONFIG_DRIVER_OWE
+        case WLAN_SECURITY_OWE_ONLY:
+            if (res->WPA_WPA2_WEP.owe != 0U)
+            {
+                /** This is dummy command to enable the embedded supplicant in Wi-Fi fimrware, OWE never uses any password */
+                wlcm_d("configuring OWE security");
+                ret = wifi_send_add_wpa3_password((int)network->role, network->ssid, "12345678",
+                                                  8U);
+            }
+            else
+            { /* Do Nothing */
+            }
+            if (ret != WM_SUCCESS)
+            {
+                return -WM_FAIL;
+            }
+            break;
+#endif
+        case WLAN_SECURITY_WPA3_SAE:
+        case WLAN_SECURITY_WPA2_WPA3_SAE_MIXED:
+            if (res->WPA_WPA2_WEP.wpa3_sae != 0U)
+            {
+                wlcm_d("configuring WPA3 SAE security");
+                wlcm_d("adding SSID and WPA3 SAE PASSWORD to supplicant cache");
+                ret = wifi_send_add_wpa3_password((int)network->role, network->ssid, network->security.password,
+                                                  network->security.password_len);
+            }
+            else if (res->WPA_WPA2_WEP.wpa2 != 0U || res->WPA_WPA2_WEP.wpa2_sha256 != 0U)
+            {
+                wlcm_d("configuring WPA2 security");
+                wlcm_d("adding SSID and PSK to supplicant cache");
+                ret = wifi_send_add_wpa_psk((int)network->role, network->ssid, network->security.password,
+                                            network->security.password_len);
+            }
+            else
+            { /* Do Nothing */
+            }
+            if (ret != WM_SUCCESS)
+            {
+                return -WM_FAIL;
+            }
+            break;
+        case WLAN_SECURITY_WEP_OPEN:
+        case WLAN_SECURITY_WEP_SHARED:
+            ret = load_wep_key((const uint8_t *)network->security.psk, (uint8_t *)network->security.psk,
+                               (uint8_t *)&network->security.psk_len, sizeof(network->security.psk));
+            if (ret != WM_SUCCESS)
+            {
+                return -WM_E_INVAL;
+            }
+
+            ret = wifi_set_key(BSS_TYPE_STA, true, 0U, (const uint8_t *)network->security.psk,
+                               (unsigned)network->security.psk_len, NULL, 0, (const uint8_t *)network->bssid, 0);
+
+            if (ret != WM_SUCCESS)
+            {
+                return -WM_FAIL;
+            }
+            break;
+
+        case WLAN_SECURITY_NONE:
+#if CONFIG_WPS2
+            if (network->wps_specific && res->wps_session != WPS_SESSION_INACTIVE)
+                wlan_set_prov_session(PROV_WPS_SESSION_ATTEMPT);
+#endif
+            break;
+        default:
+            wlcm_d("Unexpected wlan security");
+            break;
+    }
+
+    return WM_SUCCESS;
+}
+
+static bool is_running(void)
+{
+    return (wlan.running && wlan.sta_state >= CM_STA_IDLE);
+}
+
+static bool is_sta_connecting(void)
+{
+    return ((wlan.sta_state > CM_STA_ASSOCIATING) && (wlan.sta_state <= CM_STA_CONNECTED));
+}
+
+/* Check whether we are allowed to start a user-requested scan right now. */
+static bool is_scanning_allowed(void)
+{
+    return (is_state(CM_STA_IDLE) || is_state(CM_STA_CONNECTED) || is_state(CM_STA_AUTHENTICATED));
+}
+
+/*
+ * Connection Manager actions
+ */
+static void do_scan(struct wlan_network *network)
+{
+    int ret;
+    uint8_t *bssid = NULL;
+    char *ssid     = NULL;
+    unsigned int channel = 0;
+    IEEEtypes_Bss_t type;
+    wlan_scan_channel_list_t chan_list[1];
+    (void)memset((uint8_t *)chan_list, 0x00, sizeof(wlan_scan_channel_list_t) * 1);
+
+    wlcm_d("initiating scan for network \"%s\"", network->name);
+
+    if (network->bssid_specific != 0U)
+    {
+        bssid = (uint8_t *)network->bssid;
+    }
+    if (network->ssid_specific != 0U)
+    {
+        ssid = network->ssid;
+    }
+#if CONFIG_DRIVER_OWE
+    if (network->owe_trans_mode == OWE_TRANS_MODE_OPEN)
+    {
+        ssid    = network->trans_ssid;
+        channel = network->channel;
+    }
+#endif
+    if (network->channel_specific != 0U)
+    {
+        channel = network->channel;
+    }
+
+    switch (network->role)
+    {
+        case WLAN_BSS_ROLE_STA:
+            type = BSS_INFRASTRUCTURE;
+            break;
+        default:
+            type = BSS_INFRASTRUCTURE;
+            break;
+    }
+
+    wlan.sta_state = CM_STA_SCANNING;
+
+    /* comment out this, need to check if 11d needs 3 times full channel scan */
+    /*
+    if (wrapper_wlan_11d_support_is_enabled() && wlan.scan_count < WLAN_11D_SCAN_LIMIT)
+    {
+        ret = wifi_send_scan_cmd((t_u8)g_wifi_scan_params.bss_type, g_wifi_scan_params.bssid, g_wifi_scan_params.ssid,
+                                 1, 0, NULL, 0,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                                 0,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                                 scan_channel_gap,
+#endif
+                                 false, false);
+    }
+    else
+    */
+    {
+        if (channel != 0)
+        {
+            chan_list[0].chan_number = (t_u8)channel;
+            chan_list[0].scan_type   = MLAN_SCAN_TYPE_ACTIVE;
+            chan_list[0].scan_time   = 120;
+#if CONFIG_SCAN_WITH_RSSIFILTER
+            ret = wifi_send_scan_cmd((t_u8)type, bssid, ssid, 1, 1, chan_list, 0, 0,
+#if CONFIG_SCAN_CHANNEL_GAP
+                                     scan_channel_gap,
+#endif
+                                     false, false);
+#else
+            ret = wifi_send_scan_cmd((t_u8)type, bssid, ssid, 1, 1, chan_list, 0,
+#if CONFIG_SCAN_CHANNEL_GAP
+                                     scan_channel_gap,
+#endif
+                                     false, false);
+#endif
+        }
+        else
+        {
+#if CONFIG_SCAN_WITH_RSSIFILTER
+            ret = wifi_send_scan_cmd((t_u8)type, bssid, ssid, 1, 0, NULL, 0, 0,
+#if CONFIG_SCAN_CHANNEL_GAP
+                                     scan_channel_gap,
+#endif
+                                     false, false);
+#else
+            ret = wifi_send_scan_cmd((t_u8)type, bssid, ssid, 1, 0, NULL, 0,
+#if CONFIG_SCAN_CHANNEL_GAP
+                                     scan_channel_gap,
+#endif
+                                     false, false);
+#endif
+        }
+    }
+    if (ret != 0)
+    {
+        (void)wlan_wlcmgr_send_msg(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_FAILURE, NULL);
+        wlcm_e("error: scan failed");
+    }
+    else
+    {
+        wlan.scan_count++;
+    }
+}
+
+static void do_hidden_scan(struct wlan_network *network, uint8_t num_channels, wlan_scan_channel_list_t *chan_list)
+{
+    int ret;
+    uint8_t *bssid = NULL;
+    char *ssid     = NULL;
+    IEEEtypes_Bss_t type;
+
+    wlcm_d("initiating scan for hidden network \"%s\"", network->name);
+
+    if (network->bssid_specific != 0U)
+    {
+        bssid = (uint8_t *)network->bssid;
+    }
+    if (network->ssid_specific != 0U)
+    {
+        ssid = network->ssid;
+    }
+
+    switch (network->role)
+    {
+        case WLAN_BSS_ROLE_STA:
+            type = BSS_INFRASTRUCTURE;
+            break;
+        default:
+            type = BSS_INFRASTRUCTURE;
+            break;
+    }
+
+    wlan.sta_state = CM_STA_SCANNING;
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+    ret = wifi_send_scan_cmd((t_u8)type, bssid, ssid, 1, num_channels, chan_list, 0, 0,
+#if CONFIG_SCAN_CHANNEL_GAP
+                             scan_channel_gap,
+#endif
+                             false, true);
+#else
+    ret = wifi_send_scan_cmd((t_u8)type, bssid, ssid, 1, num_channels, chan_list, 0,
+#if CONFIG_SCAN_CHANNEL_GAP
+                             scan_channel_gap,
+#endif
+                             false, true);
+#endif
+    if (ret != 0)
+    {
+        (void)wlan_wlcmgr_send_msg(WIFI_EVENT_SCAN_RESULT, WIFI_EVENT_REASON_FAILURE, NULL);
+        wlcm_e("error: scan failed");
+    }
+}
+
+static void do_connect_failed(enum wlan_event_reason reason);
+
+#if !CONFIG_WPA_SUPP
+/* Start a connection attempt.  To do this we choose a specific network to scan
+ * for or the first of our list of known networks. If that network uses WEP
+ * security, we first issue the WEP configuration command and enter the
+ * CM_STA_CONFIGURING state, we'll get a response to this command which will
+ * transition us to the CM_STA_SCANNING state.  Otherwise we issue a scan and
+ * enter the CM_STA_SCANNING state now. */
+static int do_connect(int netindex)
+{
+
+
+    /* try the specified network */
+    if (wlan.networks[netindex].role != WLAN_BSS_ROLE_STA)
+    {
+        return -WM_E_INVAL;
+    }
+
+#if CONFIG_DRIVER_OWE
+    wlan.networks[netindex].owe_trans_mode = 0;
+#endif
+    wlan.cur_network_idx = netindex;
+    wlan.scan_count      = 0;
+
+    do_scan(&wlan.networks[netindex]);
+
+    return WM_SUCCESS;
+}
+#endif
+
+static int do_start(struct wlan_network *network)
+{
+    int ret;
+    uint8_t active_chan_list[40];
+    uint8_t active_num_chans = 0;
+    wifi_scan_chan_list_t scan_chan_list;
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_uap_interface();
+#else
+    uint8_t i;
+#endif
+
+    if (network->role == WLAN_BSS_ROLE_UAP)
+    {
+        if (network->channel_specific == 0U)
+        {
+            network->channel = UAP_DEFAULT_CHANNEL;
+
+            if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+            {
+                network->channel = wlan.networks[wlan.cur_network_idx].channel;
+#if CONFIG_WPA_SUPP
+            network->sec_channel_offset = wifi_get_sec_channel_offset(network->channel);
+            if (network->channel == 14)
+            {
+                wpa_supp_set_ap_bw(netif, 1);
+            }
+#endif
+            }
+            else
+            {
+                if (!wlan_uap_scan_chan_list_set)
+                {
+                    wifi_get_active_channel_list(active_chan_list, &active_num_chans,
+                                                 wlan.networks[wlan.cur_uap_network_idx].acs_band);
+
+                    if (active_num_chans != 0U)
+                    {
+                        scan_chan_list.num_of_chan = active_num_chans;
+                        (void)memcpy((void *)scan_chan_list.chan_number, (const void *)active_chan_list,
+                                     active_num_chans);
+                        wlan_uap_set_scan_chan_list(scan_chan_list);
+                    }
+                }
+
+#if !CONFIG_WPA_SUPP
+                wifi_uap_do_acs(NULL, wlan.networks[wlan.cur_uap_network_idx].acs_band);
+
+                if (wm_wifi.acs_chan != 0)
+                {
+                    network->channel = wm_wifi.acs_chan;
+                }
+                if (network->channel == 165)
+                {
+                    wifi_uap_set_bandwidth(BANDWIDTH_20MHZ);
+                }
+#endif
+            }
+        }
+        else
+        {
+#if CONFIG_11AC
+            t_u8 bandwidth = wifi_uap_get_bandwidth();
+            if (bandwidth == BANDWIDTH_80MHZ)
+            {
+                if ((wlan.networks[wlan.cur_uap_network_idx].acs_band == 0)
+#if CONFIG_WIFI_CAPA
+                        || ((wlan.networks[wlan.cur_uap_network_idx].acs_band == 1) && (!(network->wlan_capa & (WIFI_SUPPORT_11AX | WIFI_SUPPORT_11AC))))
+#endif
+                   )
+                {
+                    wlcm_e("uAP configured bandwidth not allowed");
+                    CONNECTION_EVENT(WLAN_REASON_UAP_START_FAILED, NULL);
+                    wlan.cur_uap_network_idx = -1;
+                    return -WM_FAIL;
+                }
+            }
+#endif
+#if CONFIG_WPA_SUPP
+            network->sec_channel_offset = wifi_get_sec_channel_offset(network->channel);
+            if (network->channel == 14)
+            {
+                wpa_supp_set_ap_bw(netif, 1);
+            }
+#else
+            if (network->channel > MAX_CHANNELS_BG)
+                wifi_get_active_channel_list(active_chan_list, &active_num_chans, BAND_5GHZ);
+            else
+                wifi_get_active_channel_list(active_chan_list, &active_num_chans, BAND_2GHZ);
+
+            for (i = 0; i < active_num_chans; i++)
+            {
+                if (network->channel == active_chan_list[i])
+                {
+                    break;
+                }
+            }
+            if (i == active_num_chans)
+            {
+                wlcm_e("uAP configured channel not allowed");
+                CONNECTION_EVENT(WLAN_REASON_UAP_START_FAILED, NULL);
+                wlan.cur_uap_network_idx = -1;
+                return -WM_FAIL;
+            }
+#endif
+        }
+
+        if (network->channel_specific == 0U)
+        {
+#if CONFIG_11AC
+            t_u8 bandwidth = wifi_uap_get_bandwidth();
+            if (bandwidth == BANDWIDTH_80MHZ)
+            {
+                if ((wlan.networks[wlan.cur_uap_network_idx].acs_band == 0)
+#if CONFIG_WIFI_CAPA
+                        || ((wlan.networks[wlan.cur_uap_network_idx].acs_band == 1) && (!(network->wlan_capa & (WIFI_SUPPORT_11AX | WIFI_SUPPORT_11AC))))
+#endif
+                   )
+                {
+                    wlcm_e("uAP configured bandwidth not allowed");
+                    CONNECTION_EVENT(WLAN_REASON_UAP_START_FAILED, NULL);
+                    wlan.cur_uap_network_idx = -1;
+                    return -WM_FAIL;
+                }
+            }
+#endif
+        }
+
+        wlcm_d("starting our own network");
+
+#if CONFIG_WIFI_CAPA
+        if (network->channel == 14)
+        {
+            wifi_uap_config_wifi_capa(WIFI_SUPPORT_LEGACY);
+        }
+        else
+        {
+            wifi_uap_config_wifi_capa(network->wlan_capa);
+        }
+#endif
+
+#if CONFIG_WPA_SUPP
+        if (network->bssid_specific == 0U)
+        {
+            (void)memcpy(&network->bssid[0], &wlan.uap_mac[0], MLAN_MAC_ADDR_LENGTH);
+        }
+
+        t_u8 bandwidth = wifi_uap_get_bandwidth();
+
+#if defined(SD8801) || defined(RW610)
+        wpa_supp_set_ap_bw(netif, 1);
+#else
+        wpa_supp_set_ap_bw(netif, bandwidth);
+#endif
+        ret = wpa_supp_start_ap(netif, network, 0);
+#else
+        if (network->channel == 14)
+        {
+            wifi_uap_set_bandwidth(BANDWIDTH_20MHZ);
+        }
+
+        ret = wifi_uap_start((mlan_bss_type)network->type, network->ssid,
+                             wlan.uap_mac,
+                             (int)network->security.type, network->security.key_mgmt, &network->security.psk[0], &network->security.password[0],
+                             (int)network->channel, wlan.scan_chan_list,
+                             network->security.pwe_derivation,
+                             network->security.transition_disable,
+                             network->security.mfpc,
+#if CONFIG_WIFI_DTIM_PERIOD
+                             network->security.mfpr, network->dtim_period
+#else
+                             network->security.mfpr
+#endif
+        );
+#endif
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("uAP start failed, giving up");
+            CONNECTION_EVENT(WLAN_REASON_UAP_START_FAILED, NULL);
+            wlan.cur_uap_network_idx = -1;
+            return -WM_FAIL;
+        }
+
+#if CONFIG_WPA_SUPP
+        if (ret == WM_SUCCESS)
+        {
+            wlan.connect        = false;
+            wlan.status_timeout = 0;
+            (void)OSA_TimerActivate((osa_timer_handle_t)wlan.supp_status_timer);
+        }
+#endif
+
+        wlan.uap_state = CM_UAP_CONFIGURED;
+    }
+    return WM_SUCCESS;
+}
+
+static int do_stop(struct wlan_network *network)
+{
+    int ret = WM_SUCCESS;
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_uap_interface();
+#endif
+
+    wlcm_d("stopping our own network");
+
+    if (network->role == WLAN_BSS_ROLE_UAP)
+    {
+#if CONFIG_WPA_SUPP
+        ret = wpa_supp_stop_ap(netif, network);
+#else
+        ret = wifi_uap_stop();
+#endif
+        if (ret != 0)
+        {
+            wlcm_e("uAP stop failed, giving up");
+            CONNECTION_EVENT(WLAN_REASON_UAP_STOP_FAILED, NULL);
+            return -WM_FAIL;
+        }
+        wlan_uap_set_bandwidth(UAP_DEFAULT_BANDWIDTH);
+        wlan_uap_set_beacon_period(UAP_DEFAULT_BEACON_PERIOD);
+        wlan_uap_set_hidden_ssid(UAP_DEFAULT_HIDDEN_SSID);
+        wlan.uap_state           = CM_UAP_INITIALIZING;
+        wlan.cur_uap_network_idx = -1;
+    }
+
+    return WM_SUCCESS;
+}
+
+/* A connection attempt has failed for 'reason', decide whether to try to
+ * connect to another network (in that case, tell the state machine to
+ * transition to CM_STA_CONFIGURING to try that network) or finish attempting to
+ * connect by releasing the scan lock and informing the user. */
+static void do_connect_failed(enum wlan_event_reason reason)
+{
+#if (CONFIG_DRIVER_OWE) || (CONFIG_WPA2_ENTP)
+    struct wlan_network *network = &wlan.networks[wlan.cur_network_idx];
+#endif
+
+#if CONFIG_WPA2_ENTP
+    if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+    {
+        wpa2_tls_cleanup(network, false);
+    }
+#endif
+    if (wlan.connect_wakelock_taken)
+    {
+#if CONFIG_HOST_SLEEP
+        wakelock_put();
+#endif
+        wlan.connect_wakelock_taken = false;
+    }
+
+#if CONFIG_DRIVER_OWE
+    if (network->trans_ssid_specific && network->trans_ssid_len)
+    {
+        (void)memset(&network->trans_ssid, 0x00, sizeof(network->trans_ssid));
+        network->trans_ssid_len = 0;
+    }
+#endif
+
+    wlcm_d("connecting to \"%s\" failed", wlan.networks[wlan.cur_network_idx].name);
+
+    if (wlan.sta_state == CM_STA_SCANNING_USER)
+    {
+        wlan.sta_return_to = CM_STA_IDLE;
+    }
+
+    wlan.sta_state = CM_STA_IDLE;
+    CONNECTION_EVENT(reason, NULL);
+}
+
+static void report_scan_results(void)
+{
+    unsigned int count;
+    if (wlan.scan_cb != NULL)
+    {
+        if (wifi_get_scan_result_count(&count) != WM_SUCCESS)
+        {
+            count = 0;
+        }
+        (void)wlan.scan_cb(count);
+        wlan.scan_cb = NULL;
+    }
+}
+
+static void update_network_params(struct wlan_network *network, const struct wifi_scan_result2 *res)
+{
+    if (!network->security_specific)
+    {
+        /* Wildcard: If wildcard security is specified, copy the highest
+         * security available in the scan result to the configuration
+         * structure
+         */
+        enum wlan_security_type t = WLAN_SECURITY_NONE;
+        int key_mgmt = WLAN_KEY_MGMT_NONE;
+
+        if ((res->WPA_WPA2_WEP.wpa3_sae != 0U) && (res->WPA_WPA2_WEP.wpa2 != 0U))
+        {
+            t = WLAN_SECURITY_WPA2_WPA3_SAE_MIXED;
+            key_mgmt = WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_SAE;
+        }
+        else if (res->WPA_WPA2_WEP.wpa3_sae != 0U)
+        {
+            t = WLAN_SECURITY_WPA3_SAE;
+            key_mgmt = WLAN_KEY_MGMT_SAE;
+        }
+        else if (res->WPA_WPA2_WEP.wpa2 != 0U)
+        {
+            t = WLAN_SECURITY_WPA2;
+            key_mgmt = WLAN_KEY_MGMT_PSK;
+        }
+        else if (res->WPA_WPA2_WEP.wpa != 0U)
+        {
+            t = WLAN_SECURITY_WPA_WPA2_MIXED;
+            key_mgmt = WLAN_KEY_MGMT_PSK;
+        }
+        else if (res->WPA_WPA2_WEP.wepStatic != 0U)
+        {
+            t = WLAN_SECURITY_WEP_OPEN;
+        }
+#if CONFIG_DRIVER_OWE
+        else if (res->WPA_WPA2_WEP.wpa2 && res->WPA_WPA2_WEP.owe)
+        {
+            t = WLAN_SECURITY_OWE_ONLY;
+            key_mgmt = WLAN_KEY_MGMT_OWE;
+        }
+#endif
+        else
+        {
+            t = WLAN_SECURITY_NONE;
+            key_mgmt = WLAN_KEY_MGMT_NONE;
+        }
+
+        network->security.type = t;
+        network->security.key_mgmt = key_mgmt;
+
+        if ((network->security.type == WLAN_SECURITY_WPA2) || (network->security.type == WLAN_SECURITY_WPA3_SAE) || (network->security.type == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED))
+        {
+            network->security.mfpr = 0;
+            (void)wlan_set_pmfcfg((t_u8)network->security.mfpc, (t_u8)network->security.mfpr);
+        }
+    }
+
+#if CONFIG_11R
+
+    network->mdid = res->mdid;
+
+    if (res->WPA_WPA2_WEP.ft_1x != 0U)
+    {
+        network->ft_1x = 1;
+    }
+    else if (res->WPA_WPA2_WEP.ft_psk != 0U)
+    {
+        network->ft_psk = 1;
+    }
+    else if (res->WPA_WPA2_WEP.ft_sae != 0U)
+    {
+        network->ft_sae = 1;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+#endif
+
+    /* We have a match based on the criteria we checked, update the known
+     * network with any additional information that we got from the scan but
+     * did not know before */
+    if (!network->channel_specific)
+    {
+        network->channel = res->Channel;
+    }
+    if (!network->bssid_specific)
+    {
+        (void)memcpy((void *)network->bssid, (const void *)res->bssid, MLAN_MAC_ADDR_LENGTH);
+    }
+    if (!network->ssid_specific)
+    {
+        (void)memcpy((void *)network->ssid, (const void *)res->ssid, (size_t)res->ssid_len);
+    }
+
+    network->beacon_period = res->beacon_period;
+    network->dtim_period   = res->dtim_period;
+#if CONFIG_DRIVER_OWE
+    network->owe_trans_mode = res->trans_mode;
+
+    if (res->trans_mode == OWE_TRANS_MODE_OPEN)
+    {
+        (void)memset(&network->trans_ssid, 0x00, sizeof(network->trans_ssid));
+        (void)memcpy((void *)network->trans_ssid, (const void *)res->trans_ssid, res->trans_ssid_len);
+        network->trans_ssid_len = res->trans_ssid_len;
+    }
+#endif
+
+#if CONFIG_11K
+    if (res->neighbor_report_supported == true)
+    {
+        network->neighbor_report_supported = true;
+    }
+    else
+    {
+        network->neighbor_report_supported = false;
+    }
+#endif
+
+#if CONFIG_11V
+    if (res->bss_transition_supported == true)
+    {
+        network->bss_transition_supported = true;
+    }
+    else
+    {
+        network->bss_transition_supported = false;
+    }
+#endif
+
+    network->security.is_pmf_required = res->is_pmf_required;
+
+    switch (network->security.type)
+    {
+        case WLAN_SECURITY_WPA:
+            network->security.mcstCipher.tkip = res->wpa_mcstCipher.tkip;
+            network->security.ucstCipher.tkip = res->wpa_ucstCipher.tkip;
+            network->security.mcstCipher.ccmp = res->wpa_mcstCipher.ccmp;
+            network->security.ucstCipher.ccmp = res->wpa_ucstCipher.ccmp;
+            break;
+        case WLAN_SECURITY_WPA2:
+        case WLAN_SECURITY_WPA_WPA2_MIXED:
+#if CONFIG_WPA2_ENTP
+        case WLAN_SECURITY_EAP_TLS:
+        case WLAN_SECURITY_EAP_PEAP_MSCHAPV2:
+#endif
+            network->security.mcstCipher.ccmp = res->rsn_mcstCipher.ccmp;
+            network->security.ucstCipher.ccmp = res->rsn_ucstCipher.ccmp;
+            if (!res->rsn_mcstCipher.ccmp)
+            {
+                network->security.mcstCipher.tkip = res->rsn_mcstCipher.tkip;
+            }
+            if (!res->rsn_ucstCipher.ccmp)
+            {
+                network->security.ucstCipher.tkip = res->rsn_ucstCipher.tkip;
+            }
+            if (!res->rsn_mcstCipher.tkip && !res->rsn_ucstCipher.tkip && !res->rsn_mcstCipher.ccmp &&
+                !res->rsn_ucstCipher.ccmp)
+            {
+                network->security.mcstCipher.ccmp = res->wpa_mcstCipher.ccmp;
+                network->security.ucstCipher.ccmp = res->wpa_ucstCipher.ccmp;
+                if (!res->wpa_mcstCipher.ccmp)
+                {
+                    network->security.mcstCipher.tkip = res->wpa_mcstCipher.tkip;
+                }
+                if (!res->wpa_ucstCipher.ccmp)
+                {
+                    network->security.ucstCipher.tkip = res->wpa_ucstCipher.tkip;
+                }
+            }
+            break;
+        case WLAN_SECURITY_NONE:
+            break;
+        default:
+            wlcm_d("Unexpected security nw param");
+            break;
+    }
+}
+
+static int start_association(struct wlan_network *network, struct wifi_scan_result2 *res)
+{
+    int ret                     = WM_SUCCESS;
+    unsigned int owe_trans_mode = 0;
+    bool is_ft                  = false;
+
+    wlcm_d("starting association to \"%s\"", network->name);
+    wlan.roam_reassoc = false;
+    ret               = configure_security(network, res);
+    if (ret != 0)
+    {
+        wlcm_d("setting security params failed");
+        do_connect_failed(WLAN_REASON_NETWORK_AUTH_FAILED);
+        return -WM_FAIL;
+    }
+#if CONFIG_DRIVER_OWE
+    owe_trans_mode = res->trans_mode;
+#endif
+#if CONFIG_11R
+    is_ft       = wlan.ft_bss;
+    wlan.ft_bss = false;
+#endif
+
+    ret = wrapper_wifi_assoc(res->bssid, (int)network->security.type, (bool)network->security.ucstCipher.tkip,
+                             owe_trans_mode, is_ft);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_d("association failed");
+        do_connect_failed(WLAN_REASON_NETWORK_AUTH_FAILED);
+        return -WM_FAIL;
+    }
+
+    return ret;
+}
+
+#if CONFIG_11V
+static void wlan_send_btm_response(t_u8 *bssid, enum wnm_btm_status_code status)
+{
+    wlan_send_mgmt_wnm_btm_resp(wlan.nlist_rep_param.dialog_token, status, wlan.nlist_rep_param.dst_addr, wlan.sta_mac,
+                                bssid, NULL, 0, wlan.nlist_rep_param.protect);
+
+    memset(&wlan.nlist_rep_param, 0x00, sizeof(wlan_nlist_report_param));
+}
+#endif
+
+static void handle_scan_results(void)
+{
+    unsigned int count;
+    int ret;
+    unsigned int i;
+    struct wifi_scan_result2 *res;
+    struct wlan_network *network = &wlan.networks[wlan.cur_network_idx];
+    bool matching_ap_found       = false;
+    uint8_t num_channels         = 0;
+    wlan_scan_channel_list_t chan_list[40];
+
+    /* comment out this, need to check if 11d needs 3 times full channel scan */
+    /*
+    if (wrapper_wlan_11d_support_is_enabled() && wlan.scan_count < WLAN_11D_SCAN_LIMIT)
+    {
+        wlcm_d("11D enabled, re-scanning");
+        do_scan(network);
+        return;
+    }
+    */
+
+    /*
+     * We need an allocation here because the lower layer puts all the
+     * results into the same global buffer. Hence, we need a private
+     * copy. fixme: Can be removed after this issue is fixed in the
+     * lower layer.
+     */
+#if !CONFIG_MEM_POOLS
+    struct wifi_scan_result2 *best_ap = OSA_MemoryAllocate(sizeof(struct wifi_scan_result2));
+#else
+    struct wifi_scan_result2 *best_ap = OSA_MemoryPoolAllocate(buf_512_MemoryPool);
+#endif
+
+    if (best_ap == NULL)
+    {
+        wlcm_d("%s: Failed to alloc scan result object", __func__);
+        return;
+    }
+
+    /* We're associating unless an error occurs, in which case we make a
+     * decision to rescan (transition to CM_STA_SCANNING) or fail
+     * (transition to CM_STA_IDLE or a new connection attempt) */
+    wlan.sta_state = CM_STA_ASSOCIATING;
+
+    ret = wifi_get_scan_result_count(&count);
+    if (ret != 0)
+    {
+        count = 0;
+    }
+
+    /* 'count' scan results available, is our network there? */
+    for (i = 0; i < count; i++)
+    {
+        ret = wifi_get_scan_result(i, &res);
+        if (ret == WM_SUCCESS)
+        {
+            ret = network_matches_scan_result(network, res, &num_channels, chan_list);
+            if (ret == WM_SUCCESS)
+            {
+                if (!matching_ap_found)
+                {
+                    /* First matching AP found */
+                    (void)memcpy((void *)best_ap, (const void *)res, sizeof(struct wifi_scan_result2));
+                    matching_ap_found = true;
+                    /*
+                     * Continue the search. There may be an AP
+                     * with same name but better RSSI.
+                     */
+                    continue;
+                }
+
+                wlcm_d("RSSI: Best AP=%d Result AP=%d", best_ap->RSSI, res->RSSI);
+                if (best_ap->RSSI > res->RSSI)
+                {
+                    /*
+                     * We found a network better that current
+                     * best_ap
+                     */
+                    wlcm_d("Found better AP %s on channel %d", res->ssid, res->Channel);
+                    /* Assign the new found as curr_best */
+                    (void)memcpy((void *)best_ap, (const void *)res, sizeof(struct wifi_scan_result2));
+                }
+
+                /* Continue the search */
+            }
+        }
+    }
+
+    if (matching_ap_found)
+    {
+        if (wlan.roam_reassoc == true)
+        {
+            if (memcmp((const void *)network->bssid, (const void *)best_ap->bssid, (size_t)IEEEtypes_ADDRESS_SIZE) == 0)
+            {
+#if CONFIG_11V
+                if (wlan.nlist_rep_param.nlist_mode == WLAN_NLIST_11V)
+                {
+                    wlan_send_btm_response(NULL, WNM_BTM_REJECT_NO_SUITABLE_CANDIDATES);
+                }
+#endif
+                wlan.sta_state    = CM_STA_CONNECTED;
+                wlan.roam_reassoc = false;
+                PRINTF("Already connected to best AP\r\n");
+                PRINTF("Connected to following BSS:\r\n");
+                PRINTF("SSID = [%s]\r\n", network->ssid);
+#if CONFIG_11R
+                wlan.ft_bss = false;
+#endif
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)best_ap);
+#else
+                OSA_MemoryPoolFree(buf_512_MemoryPool, best_ap);
+#endif
+                return;
+            }
+#if CONFIG_11V
+            if (wlan.nlist_rep_param.nlist_mode == WLAN_NLIST_11V)
+            {
+                wlan_send_btm_response(best_ap->bssid, WNM_BTM_ACCEPT);
+            }
+#endif
+        }
+
+        wlan.same_ess = false;
+
+#if CONFIG_11R
+        if ((wlan.ft_bss == true) && (network->mdid == best_ap->mdid))
+        {
+            wlan.same_ess = true;
+        }
+#endif
+        wlan.same_ess |= wlan.roam_reassoc;
+
+        update_network_params(network, best_ap);
+#if CONFIG_DRIVER_OWE
+        if (network->owe_trans_mode == OWE_TRANS_MODE_OPEN)
+        {
+            wlcm_d("do scan for OWE Transition SSID: %s", network->trans_ssid);
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)best_ap);
+#else
+            OSA_MemoryPoolFree(buf_512_MemoryPool, best_ap);
+#endif
+            do_scan(network);
+            return;
+        }
+        else
+        {
+#endif
+            ret = start_association(network, best_ap);
+            if (ret == WM_SUCCESS)
+            {
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree((void *)best_ap);
+#else
+                OSA_MemoryPoolFree(buf_512_MemoryPool, best_ap);
+#endif
+                return;
+            }
+#if CONFIG_DRIVER_OWE
+        }
+#endif
+    }
+    else if (num_channels != 0U)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)best_ap);
+#else
+        OSA_MemoryPoolFree(buf_512_MemoryPool, best_ap);
+#endif
+        wlan.hidden_scan_on = true;
+        do_hidden_scan(network, num_channels, chan_list);
+        return;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree((void *)best_ap);
+#else
+    OSA_MemoryPoolFree(buf_512_MemoryPool, best_ap);
+#endif
+
+    if (wlan.roam_reassoc == true)
+    {
+        wlan.sta_state    = CM_STA_CONNECTED;
+        wlan.roam_reassoc = false;
+#if CONFIG_11R
+        wlan.ft_bss = false;
+#endif
+        return;
+    }
+
+#ifdef RW610
+    /* If reset is in process, skip re-scan */
+    if (OSA_MutexLock((osa_mutex_handle_t)reset_lock, 0) != WM_SUCCESS)
+    {
+        (void)PRINTF("skip re-scan when reset is in process\r\n");
+        return;
+    }
+    OSA_MutexUnlock((osa_mutex_handle_t)reset_lock);
+#endif
+
+    /* We didn't find our network in the scan results set: rescan if we
+     * have rescan attempts remaining, otherwise give up.
+     */
+    if (wlan.scan_count < WLAN_RESCAN_LIMIT)
+    {
+        wlcm_d("network not found, re-scanning");
+        wlan.hidden_scan_on = false;
+        do_scan(network);
+    }
+    else
+    {
+        wlcm_d("rescan limit exceeded, giving up");
+        do_connect_failed(WLAN_REASON_NETWORK_NOT_FOUND);
+
+        if (wlan.reassoc_control)
+        {
+            wlcm_request_reconnect(&wlan.sta_state, network);
+        }
+    }
+}
+
+static void wlan_disable_power_save(int action)
+{
+    switch (action)
+    {
+        case WLAN_DEEP_SLEEP:
+            wlcm_d("stopping deep sleep ps mode");
+            (void)wifi_exit_deepsleep_power_save();
+            break;
+        case WLAN_IEEE:
+            wlcm_d("stopping IEEE ps mode");
+            (void)wifi_exit_ieee_power_save();
+            break;
+#if (CONFIG_WNM_PS)
+        case WLAN_WNM:
+            wlcm_d("stopping WNM ps mode");
+            (void)wifi_exit_wnm_power_save();
+            break;
+#endif
+        default:
+            wlcm_d("Unexpected disable ps action");
+            break;
+    }
+}
+
+static void wlan_enable_power_save(int action)
+{
+    switch (action)
+    {
+        case WLAN_DEEP_SLEEP:
+            wlcm_d("starting deep sleep ps mode");
+            (void)wifi_enter_deepsleep_power_save();
+            break;
+        case WLAN_IEEE:
+            wlcm_d("starting IEEE ps mode");
+            (void)wifi_enter_ieee_power_save();
+            break;
+#if (CONFIG_WNM_PS)
+        case WLAN_WNM:
+            wlcm_d("starting WNM ps mode");
+            (void)wifi_enter_wnm_power_save(wlan.wnm_sleep_time);
+            break;
+#endif
+        default:
+            wlcm_d("Unexpected ps mode");
+            break;
+    }
+}
+
+static void wlcm_process_sleep_event(void)
+{
+    wlan_send_sleep_confirm();
+}
+
+static void wlcm_process_ieeeps_event(struct wifi_message *msg)
+{
+    ENH_PS_MODES action = (ENH_PS_MODES)(*((uint32_t *)msg->data));
+    wlcm_d("got msg data :: %x", action);
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(msg->data);
+#else
+    OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+        if (action == EN_AUTO_PS)
+        {
+            if (!wlan.cm_ieeeps_configured)
+            {
+                CONNECTION_EVENT(WLAN_REASON_PS_ENTER, (void *)WLAN_IEEE);
+                wlan.cm_ieeeps_configured = true;
+            }
+        }
+        else if (action == DIS_AUTO_PS)
+        {
+            wlan.cm_ieeeps_configured = false;
+            CONNECTION_EVENT(WLAN_REASON_PS_EXIT, (void *)WLAN_IEEE);
+        }
+        else if (action == SLEEP_CONFIRM)
+        {
+        }
+        else
+        { /* Do Nothing */
+        }
+    }
+}
+
+static void wlcm_process_deepsleep_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+    ENH_PS_MODES action = (ENH_PS_MODES)(*((uint32_t *)msg->data));
+#if CONFIG_WIFI_PS_DEBUG
+    wlcm_d("got msg data :: %x", action);
+#endif
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(msg->data);
+#else
+    OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+        if (action == EN_AUTO_PS)
+        {
+            if(!wlan.cm_deepsleepps_configured)
+            {
+                CONNECTION_EVENT(WLAN_REASON_PS_ENTER, (void *)WLAN_DEEP_SLEEP);
+                wlan.cm_deepsleepps_configured = true;
+            }
+        }
+        else if (action == DIS_AUTO_PS)
+        {
+            wlan.cm_deepsleepps_configured = false;
+            // CONNECTION_EVENT(WLAN_REASON_INITIALIZED, NULL);
+            /* Skip ps-exit event for the first time
+               after waking from PM4+DS. This will ensure
+               that we do not send ps-exit event until
+               wlan-init event has been sent */
+            CONNECTION_EVENT(WLAN_REASON_PS_EXIT, (void *)WLAN_DEEP_SLEEP);
+        }
+        else if (action == SLEEP_CONFIRM)
+        {
+        }
+        else
+        { /* Do Nothing */
+        }
+    }
+}
+
+#if (CONFIG_WNM_PS)
+static void wlcm_process_wnmps_event(struct wifi_message *msg)
+{
+    uint16_t action                      = (uint16_t)(*((uint32_t *)msg->data));
+    wnm_sleep_result_t *wnm_sleep_result = (wnm_sleep_result_t *)&action;
+
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(msg->data);
+#else
+    OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+        if ((wnm_sleep_result->action == 0) && (wnm_sleep_result->result == 0))
+        {
+            wlcm_d("WNM enable success event: action %x result %x", wnm_sleep_result->action, wnm_sleep_result->result);
+            if (!wlan.cm_wnmps_configured)
+            {
+                CONNECTION_EVENT(WLAN_REASON_PS_ENTER, (void *)WLAN_WNM);
+                wlan.cm_wnmps_configured = true;
+            }
+        }
+        else if ((wnm_sleep_result->action == 0) && (wnm_sleep_result->result == 1))
+        {
+            wlcm_d("WNM enable fail event: action %x result %x", wnm_sleep_result->action, wnm_sleep_result->result);
+            wlan.cm_wnmps_configured = false;
+        }
+        else if (action == DIS_WNM_PS)
+        {
+            wlcm_d("WNM disable success event");
+            wlan.cm_wnmps_configured = false;
+            CONNECTION_EVENT(WLAN_REASON_PS_EXIT, (void *)WLAN_WNM);
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+}
+#endif
+
+#define WL_ID_STA_DISCONN "sta_disconnected"
+
+/* fixme: duplicated from legacy. Needs to be removed later. */
+#define IEEEtypes_REASON_MIC_FAILURE          14U
+#define IEEEtypes_REASON_4WAY_HANDSHK_TIMEOUT 15
+#define WPA2_ENTERPRISE_FAILED                0xFF
+
+static void wlcm_process_scan_result_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+        wifi_scan_process_results();
+    }
+
+    if (wlan.sta_state == CM_STA_SCANNING)
+    {
+        if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+        {
+            handle_scan_results();
+        }
+        *next = wlan.sta_state;
+        wlcm_d("SM: returned to %s", dbg_sta_state_name(*next));
+        wlcm_d("releasing scan lock (connect scan)");
+    }
+    else if (wlan.sta_state == CM_STA_SCANNING_USER)
+    {
+#if CONFIG_WPA_SUPP
+#if CONFIG_11K
+        if (wlan.enable_11k == 1U)
+        {
+            wifi_scan_done(msg);
+        }
+#endif
+#endif
+        if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+        {
+            report_scan_results();
+        }
+        *next = wlan.sta_return_to;
+        wlcm_d("SM: returned to %s", dbg_sta_state_name(*next));
+        wlcm_d("releasing scan lock (user scan)");
+    }
+    else
+    {
+#if CONFIG_NCP
+        if(wlan.scan_cb != NULL)
+        {
+            report_scan_results();
+        }
+#endif
+#if CONFIG_WPA_SUPP
+        if (wlan.is_scan_lock)
+        {
+            wlcm_d("releasing scan lock (connect scan)");
+            (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+            wlan.is_scan_lock = 0;
+        }
+
+        wifi_scan_done(msg);
+        return;
+#else
+        if (wlan.roam_reassoc == true)
+        {
+            if (wlan.sta_state == CM_STA_CONNECTED)
+            {
+                wlcm_d("SM: returned to %s", dbg_sta_state_name(*next));
+                handle_scan_results();
+                *next = wlan.sta_state;
+                return;
+            }
+        }
+#endif
+    }
+
+    (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+    wlan.is_scan_lock = 0;
+}
+
+static void wlcm_process_sta_addr_config_event(struct wifi_message *msg,
+                                               enum cm_sta_state *next,
+                                               struct wlan_network *network)
+{
+    /* We have a response to our configuration request from the TCP stack.
+     * If we configured the stack with a static IP address and this was
+     * successful, we are effectively connected so we can report success
+     * and proceed to CM_STA_CONNECTED.  If we configured the stack with
+     * DHCP and the response is successful then the TCP stack is trying to
+     * obtain an address for us and we should proceed to the
+     * CM_STA_OBTAINING_ADDRESS state and wait for the
+     * WIFI_EVENT_DHCP_CONFIG event,
+     * which will tell us whether or not the DHCP address was
+     * obtained.  Otherwise, if we got an unsuccessful response then we
+     * must report a connection error.
+     *
+     * This event is only relevant if we are connecting and have requested
+     * a TCP stack configuration (that is, we are in the
+     * CM_STA_REQUESTING_ADDRESS state).  Otherwise, we ignore it. */
+
+    if (!is_state(CM_STA_REQUESTING_ADDRESS))
+    {
+        if (wlan.connect_wakelock_taken)
+        {
+#if CONFIG_HOST_SLEEP
+            wakelock_put();
+#endif
+            wlan.connect_wakelock_taken = false;
+        }
+        wlcm_d("ignoring TCP configure response");
+        return;
+    }
+    if (msg->reason != WIFI_EVENT_REASON_SUCCESS)
+    {
+        do_connect_failed(WLAN_REASON_ADDRESS_FAILED);
+        *next = wlan.sta_state;
+        return;
+    }
+    void *if_handle = NULL;
+    switch (network->ip.ipv4.addr_type)
+    {
+        case ADDR_TYPE_STATIC:
+            net_configure_dns((struct net_ip_config *)&network->ip, network->role);
+            if (network->type == WLAN_BSS_TYPE_STA)
+            {
+                if_handle = net_get_mlan_handle();
+            }
+            (void)net_get_if_addr((struct net_ip_config *)&network->ip, if_handle);
+            wlan.sta_state = CM_STA_CONNECTED;
+            if (wlan.connect_wakelock_taken)
+            {
+#if CONFIG_HOST_SLEEP
+                wakelock_put();
+#endif
+                wlan.connect_wakelock_taken = false;
+            }
+            *next                       = CM_STA_CONNECTED;
+            wlan.sta_ipv4_state         = CM_STA_CONNECTED;
+                if (wlan.reassoc_control && wlan.reassoc_request)
+                {
+                    wlan.reassoc_count   = 0;
+                    wlan.reassoc_request = false;
+                }
+            mlan_adap->skip_dfs = false;
+            CONNECTION_EVENT(WLAN_REASON_SUCCESS, NULL);
+            break;
+        case ADDR_TYPE_DHCP:
+        case ADDR_TYPE_LLA:
+            *next               = CM_STA_OBTAINING_ADDRESS;
+            wlan.sta_ipv4_state = CM_STA_OBTAINING_ADDRESS;
+            break;
+        default:
+            wlcm_d("Unexpected addr type");
+            break;
+    } /* end of switch */
+#if CONFIG_IPV6
+    /* Set the ipv6 state to obtaining address */
+    wlan.sta_ipv6_state = CM_STA_OBTAINING_ADDRESS;
+#endif
+}
+
+static void wlcm_process_channel_switch_ann(enum cm_sta_state *next, struct wlan_network *network)
+{
+    if (!wifi_is_ecsa_enabled())
+    {
+        if (is_state(CM_STA_CONNECTED))
+        {
+            wlcm_d("Sending deauth because of channel switch");
+            set_event_chanswann();
+            (void)wifi_deauthenticate((uint8_t *)network->bssid);
+            /*
+              This function call is already present in
+              wlan_11h_handle_event_chanswann(). Remove it from here when
+              that function is used directly.
+            */
+            wrapper_wlan_11d_clear_parsedtable();
+            wrapper_clear_media_connected_event();
+            clear_event_chanswann();
+            wlan.sta_state = CM_STA_IDLE;
+            *next          = CM_STA_IDLE;
+            CONNECTION_EVENT(WLAN_REASON_CHAN_SWITCH, NULL);
+        }
+    }
+}
+
+#if CONFIG_WPA_SUPP
+enum mlan_channel_type wlan_get_chan_type(nxp_wifi_ch_switch_info chandef)
+{
+    switch (chandef.ch_width) {
+    case CHAN_BAND_WIDTH_20_NOHT:
+        return CHAN_NO_HT;
+    case CHAN_BAND_WIDTH_20:
+        return CHAN_HT20;
+    case CHAN_BAND_WIDTH_40:
+        if (chandef.center_freq1 > chandef.center_freq)
+            return CHAN_HT40PLUS;
+        return CHAN_HT40MINUS;
+    default:
+
+        return CHAN_NO_HT;
+    }
+}
+
+int wlan_get_chan_offset(int width, int freq, int cf1, int cf2)
+{
+    int freq1 = 0;
+
+    switch (width)
+    {
+        case CHAN_BAND_WIDTH_20_NOHT:
+        case CHAN_BAND_WIDTH_20:
+            return 0;
+        case CHAN_BAND_WIDTH_40:
+            freq1 = cf1 - 10;
+            break;
+        case CHAN_BAND_WIDTH_80:
+            freq1 = cf1 - 30;
+            break;
+        case CHAN_BAND_WIDTH_160:
+            freq1 = cf1 - 70;
+            break;
+        case CHAN_BAND_WIDTH_80P80:
+            freq1 = cf1 - 30;
+            break;
+        default:
+            /* FIXME: implement this */
+            return 0;
+    }
+
+    return (abs(freq - freq1) / 20) % 2 == 0 ? 1 : -1;
+}
+
+static void wlcm_process_channel_switch_supp(struct wifi_message *msg)
+{
+    chan_band_info  pchan_band_info ;
+    nxp_wifi_ch_switch_info chandef = {0,};
+    t_u8 band = BAND_2GHZ;
+    enum mlan_channel_type ch_type = CHAN_NO_HT;
+    uint8_t bss_type = 0;
+    pmlan_private pmpriv = NULL;
+    wifi_ecsa_info *pchan_info = NULL;
+    t_u8 channel= 0 ;
+    const chan_freq_power_t *cfp = MNULL;
+    mlan_adapter *pmadapter = NULL;
+
+    if (wifi_is_ecsa_enabled())
+    {
+        if (msg->data != NULL)
+        {
+            memset(&pchan_band_info , 0, sizeof(chan_band_info));
+            pchan_info = (wifi_ecsa_info *)msg->data;
+            bss_type = pchan_info->bss_type;
+            pmpriv = mlan_adap->priv[bss_type];
+            pmadapter = pmpriv->adapter;
+            channel= pchan_info->channel;
+
+            if(is_uap_started())
+            {
+                wlan.networks[wlan.cur_uap_network_idx].channel = channel;
+                pmpriv->uap_channel = channel;
+        		pmpriv->uap_state_chan_cb.channel = channel;
+        		pmpriv->uap_state_chan_cb.band_config = pchan_info->band_config;
+
+                pchan_band_info.is_11n_enabled = pmpriv->is_11n_enabled;
+            }
+
+            if (is_sta_connected())
+            {
+                wlan.networks[wlan.cur_network_idx].channel = channel;
+                wifi_set_curr_bss_channel(wlan.networks[wlan.cur_network_idx].channel);
+
+#define MAX_CHANNEL_BAND_B 14
+			if (channel <= MAX_CHANNEL_BAND_B)
+				cfp = wlan_find_cfp_by_band_and_channel(pmadapter, BAND_B, channel);
+#if CONFIG_5GHz_SUPPORT
+			else
+				cfp = wlan_find_cfp_by_band_and_channel(pmadapter, BAND_A, channel);
+#endif
+			if (cfp)
+				pmpriv->curr_bss_params.bss_descriptor.freq = cfp->freq;
+			else
+				pmpriv->curr_bss_params.bss_descriptor.freq = 0;
+            }
+
+            /* Handle Host-based DFS and non-DFS(normal uap) case */
+            memcpy((t_u8 *)&pchan_band_info.bandcfg,(t_u8 *)&pchan_info->band_config, sizeof(pchan_info->band_config));
+		    pchan_band_info.channel = channel;
+#if (CONFIG_11AC)
+		    if (pchan_band_info.bandcfg.chanWidth == CHAN_BW_80MHZ)
+			pchan_band_info.center_chan = wlan_get_center_freq_idx(pmpriv, BAND_AAC,channel,CHANNEL_BW_80MHZ);
+#endif
+
+            /*Get freq and width info*/
+            memset(&chandef,0, sizeof(nxp_wifi_ch_switch_info));
+            chandef.center_freq2 = 0;
+
+            if (pchan_band_info.bandcfg.chanBand == BAND_2GHZ)
+                band = BAND_2GHZ;
+            else if (pchan_band_info.bandcfg.chanBand == BAND_5GHZ)
+                band = BAND_5GHZ;
+
+            chandef.center_freq = channel_to_frequency(pchan_band_info.channel, band);
+
+            switch (pchan_band_info.bandcfg.chanWidth)
+            {
+                case CHAN_BW_20MHZ:
+                    if (pchan_band_info.is_11n_enabled)
+                        chandef.ch_width = CHAN_BAND_WIDTH_20;
+                    else
+                        chandef.ch_width = CHAN_BAND_WIDTH_20_NOHT;
+                    chandef.center_freq1 = chandef.center_freq;
+                    break;
+
+                case CHAN_BW_40MHZ:
+                    chandef.ch_width = CHAN_BAND_WIDTH_40;
+                    if (pchan_band_info.bandcfg.chan2Offset == SEC_CHAN_ABOVE)
+                        chandef.center_freq1 = chandef.center_freq + 10;
+                    else if (pchan_band_info.bandcfg.chan2Offset == SEC_CHAN_BELOW)
+                        chandef.center_freq1 = chandef.center_freq - 10;
+                    break;
+
+#if (CONFIG_11AC)
+                case CHAN_BW_80MHZ:
+                    chandef.ch_width = CHAN_BAND_WIDTH_80;
+                    chandef.center_freq1 = channel_to_frequency(pchan_band_info.center_chan, band);
+                    break;
+#endif
+
+                default:
+                    break;
+            }
+
+            /*Get type*/
+            switch (chandef.ch_width)
+            {
+                case CHAN_BAND_WIDTH_20_NOHT:
+                case CHAN_BAND_WIDTH_20:
+                case CHAN_BAND_WIDTH_40:
+                    ch_type = wlan_get_chan_type(chandef);
+                    break;
+                default:
+                    break;
+            }
+
+            chandef.ht_enabled = 1;
+            /*Get ht and ch_offset info*/
+            switch (ch_type)
+            {
+                case CHAN_NO_HT:
+                    chandef.ht_enabled = 0;
+                    break;
+                case CHAN_HT20:
+                    break;
+                case CHAN_HT40PLUS:
+                    chandef.ch_offset = 1;
+                    break;
+                case CHAN_HT40MINUS:
+                    chandef.ch_offset = -1;
+                    break;
+                default:
+                    if (chandef.ch_width && chandef.center_freq1)
+                    {
+                        /* This can happen for example with VHT80 ch switch */
+                        chandef.ch_offset = wlan_get_chan_offset(chandef.ch_width, chandef.center_freq, chandef.center_freq1, chandef.center_freq2 ? chandef.center_freq2 : 0);
+                    }
+                    else
+                    {
+                        PRINTF("Unknown secondary channel information - following channel definition calculations may fail\r\n");
+                    }
+                    break;
+           }
+
+            if(is_uap_started())
+            {
+                wm_wifi.supp_if_callbk_fns->ecsa_complete_callbk_fn(wm_wifi.hapd_if_priv, &chandef);
+                (void)PRINTF("uap switch to channel %d success!\r\n", channel);
+            }
+
+            if (is_sta_connected())
+            {
+                wm_wifi.supp_if_callbk_fns->ecsa_complete_callbk_fn(wm_wifi.if_priv, &chandef);
+                (void)PRINTF("sta switch to channel %d success!\r\n", channel);
+            }
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+        }
+
+#if CONFIG_ECSA
+        wifi_put_ecsa_sem();
+        set_ecsa_block_tx_flag(false);
+#endif
+    }
+    else
+    {
+        wlcm_d("ECSA not support");
+        if (msg->data != NULL)
+        {
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+        }
+    }
+}
+#else
+static void wlcm_process_channel_switch(struct wifi_message *msg)
+{
+    t_u8 channel= 0 ;
+    wifi_ecsa_info *pchan_info = NULL;
+
+    if (wifi_is_ecsa_enabled())
+    {
+        if (msg->data != NULL)
+        {
+            pchan_info = (wifi_ecsa_info *)msg->data;
+            channel= pchan_info->channel;
+
+            if(is_uap_started())
+            {
+                (void)PRINTF("uap switch to channel %d success!\r\n", channel);
+                wlan.networks[wlan.cur_uap_network_idx].channel = channel;
+            }
+
+            if (is_sta_connected())
+            {
+                (void)PRINTF("sta switch to channel %d success!\r\n", channel);
+                wlan.networks[wlan.cur_network_idx].channel = channel;
+                wifi_set_curr_bss_channel(wlan.networks[wlan.cur_network_idx].channel);
+            }
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+        }
+
+#if CONFIG_ECSA
+        wifi_put_ecsa_sem();
+        set_ecsa_block_tx_flag(false);
+#endif
+    }
+    else
+    {
+        wlcm_d("ECSA not support");
+        if (msg->data != NULL)
+        {
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree((void *)msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+        }
+    }
+}
+#endif /*End of CONFIG_WPA_SUPP*/
+
+#if CONFIG_HOST_SLEEP
+static void wlcm_process_hs_config_event(void)
+{
+    /* host sleep config done event received */
+    int ret = WM_SUCCESS;
+    unsigned int ipv4_addr = 0;
+    enum wlan_bss_type type = WLAN_BSS_TYPE_STA;
+
+    if(is_sta_ipv4_connected() != 0)
+    {
+        ret = wlan_get_ipv4_addr(&ipv4_addr);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("HS : Cannot get STA IP, check if STA disconnected");
+            return;
+        }
+    }
+    /* If uap interface is up
+     * configure host sleep for uap interface
+     * else confiugre host sleep for station
+     * interface.
+     */
+    else if (is_uap_started() != 0)
+    {
+        ret = wlan_get_uap_ipv4_addr(&ipv4_addr);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("HS: Cannot get UAP IP, check if uAP stopped");
+            return;
+        }
+        type = WLAN_BSS_TYPE_UAP;
+    }
+    else
+        ipv4_addr = 0;
+
+    (void)wifi_send_hs_cfg_cmd((mlan_bss_type)type, ipv4_addr, (uint16_t)HS_ACTIVATE, 0);
+}
+#endif
+
+static void wlcm_process_addba_request(struct wifi_message *msg)
+{
+    if (is_state(CM_STA_ASSOCIATED) || is_state(CM_STA_REQUESTING_ADDRESS) || is_state(CM_STA_OBTAINING_ADDRESS) ||
+        is_state(CM_STA_CONNECTED) || is_uap_started())
+    {
+        (void)wrapper_wlan_cmd_11n_addba_rspgen(msg->data);
+    }
+    else
+    {
+        wlcm_d("Ignore ADDBA Request event in disconnected state");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)msg->data);
+#else
+        OSA_MemoryPoolFree(buf_256_MemoryPool, msg->data);
+#endif
+    }
+}
+
+static void wlcm_process_delba_request(struct wifi_message *msg)
+{
+    if (is_state(CM_STA_ASSOCIATED) || is_state(CM_STA_REQUESTING_ADDRESS) || is_state(CM_STA_OBTAINING_ADDRESS) ||
+        is_state(CM_STA_CONNECTED) || is_uap_started())
+    {
+        (void)wrapper_wlan_cmd_11n_delba_rspgen(msg->data);
+    }
+    else
+    {
+        wlcm_d("Ignore DELBA Request event in disconnected state");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)msg->data);
+#else
+        OSA_MemoryPoolFree(buf_256_MemoryPool, msg->data);
+#endif
+    }
+}
+
+static void wlcm_process_ba_stream_timeout_request(struct wifi_message *msg)
+{
+    if (is_state(CM_STA_ASSOCIATED) || is_state(CM_STA_REQUESTING_ADDRESS) || is_state(CM_STA_OBTAINING_ADDRESS) ||
+        is_state(CM_STA_CONNECTED) || is_uap_started())
+    {
+        (void)wrapper_wlan_cmd_11n_ba_stream_timeout(msg->data);
+    }
+    else
+    {
+        wlcm_d(
+            "Ignore BA STREAM TIMEOUT Request"
+            " event in disconnected state");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)msg->data);
+#else
+        OSA_MemoryPoolFree(buf_256_MemoryPool, msg->data);
+#endif
+    }
+}
+
+static void wlcm_process_association_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+#if CONFIG_WPA2_ENTP
+    int ret;
+    struct wlan_network *network = &wlan.networks[wlan.cur_network_idx];
+#endif
+
+#if CONFIG_WPA_SUPP
+    if (wlan.is_scan_lock)
+    {
+      	wlcm_d("releasing scan lock (connect scan)");
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+       	wlan.is_scan_lock = 0;
+    }
+#endif
+
+    /* We have received a response to the association command.  We may now
+     * proceed to authenticating if it was successful, otherwise this
+     * connection attempt has failed.
+     *
+     * This event is only relevant if we have sent an association command
+     * while connecting (that is, we are in the CM_STA_ASSOCIATING state).
+     * Otherwise, it is ignored. */
+
+#if !CONFIG_WPA_SUPP
+    if (!is_state(CM_STA_ASSOCIATING))
+    {
+        wlcm_d("ignoring association result event");
+        return;
+    }
+#endif
+
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+        wlan.sta_state = CM_STA_ASSOCIATED;
+        *next          = CM_STA_ASSOCIATED;
+
+#if CONFIG_WPA2_ENTP
+        if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+        {
+            ret = wpa2_ent_connect(network);
+            if (ret != WM_SUCCESS)
+            {
+                wlcm_e("wpa2_ent_connect failed");
+            }
+        }
+#endif
+        wlan.scan_count = 0;
+    }
+#if !CONFIG_WPA_SUPP
+    else if (wlan.scan_count < WLAN_RESCAN_LIMIT)
+    {
+        wlcm_d("association failed, re-scanning");
+#if CONFIG_WPA2_ENTP
+        if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+        {
+            wpa2_tls_cleanup(network, true);
+        }
+#endif
+        /*
+         *  this scan does not hold scan lock as it was already put by wlcmgr task
+         *  need to check if need to hold scan lock again
+         */
+        do_scan(&wlan.networks[wlan.cur_network_idx]);
+        *next = CM_STA_SCANNING;
+    }
+#endif
+    else
+    {
+#if CONFIG_WPA2_ENTP
+        if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+        {
+            wpa2_tls_cleanup(network, true);
+        }
+#endif
+#if CONFIG_WPA_SUPP
+        OSA_TimerDeactivate((osa_timer_handle_t)wlan.supp_status_timer);
+        wlan.status_timeout = 0;
+#endif
+
+#if !CONFIG_WPA_SUPP
+        do_connect_failed(WLAN_REASON_NETWORK_AUTH_FAILED);
+
+        if (wlan.reassoc_control)
+        {
+            wlcm_request_reconnect(next, &wlan.networks[wlan.cur_network_idx]);
+        }
+#endif
+        *next = wlan.sta_state;
+    }
+}
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_AUTO_RECONNECT
+static void wlcm_process_association_notify_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    (void)msg;
+    (void)next;
+
+    if (wlan.roam_reassoc == false)
+    {
+        (void)wpa_supp_notify_assoc(netif);
+    }
+}
+#endif
+#if CONFIG_WPA_SUPP_AP
+static void wlcm_process_acs_notify_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+    struct netif *netif = net_get_uap_interface();
+
+    (void)msg;
+    (void)next;
+
+    (void)wpa_supp_notify_acs(netif);
+}
+#endif
+#endif
+
+static void wlcm_process_pmk_event(struct wifi_message *msg, enum cm_sta_state *next, struct wlan_network *network)
+{
+    char *bssid = network->bssid;
+
+    if (msg->data != NULL)
+    {
+        network->security.pmk_valid = true;
+        (void)memcpy((void *)network->security.pmk, (const void *)msg->data, WLAN_PMK_LENGTH);
+        if (network->role == WLAN_BSS_ROLE_STA)
+        {
+#if CONFIG_WPA2_ENTP
+            if (network->security.type == WLAN_SECURITY_EAP_TLS)
+            {
+                /* OKC-802.1X case, roaming without specifying bssid */
+                bssid = NULL;
+            }
+#endif
+            (void)wifi_send_add_wpa_pmk((int)network->role, network->ssid, bssid, network->security.pmk,
+                                        WLAN_PMK_LENGTH);
+        }
+    }
+}
+
+static void wlcm_process_authentication_event(struct wifi_message *msg,
+                                              enum cm_sta_state *next,
+                                              struct wlan_network *network)
+{
+#if CONFIG_STA_AUTO_DHCPV4
+    int ret         = 0;
+#endif
+    void *if_handle = NULL;
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+#if CONFIG_WPS2
+    if (wlan_get_prov_session() == PROV_WPS_SESSION_ATTEMPT)
+    {
+        if(wlan.connect_wakelock_taken)
+        {
+#if CONFIG_HOST_SLEEP
+            wakelock_put();
+#endif
+            wlan.connect_wakelock_taken = false;
+        }
+        return;
+    }
+#endif
+
+    if (!is_state(CM_STA_ASSOCIATING) && !is_state(CM_STA_ASSOCIATED) && !is_state(CM_STA_REQUESTING_ADDRESS) &&
+        !is_state(CM_STA_OBTAINING_ADDRESS) && !is_state(CM_STA_CONNECTED))
+    {
+        if (wlan.connect_wakelock_taken)
+        {
+#if CONFIG_HOST_SLEEP
+            wakelock_put();
+#endif
+            wlan.connect_wakelock_taken = false;
+        }
+        wlcm_d("ignoring authentication event");
+        return;
+    }
+
+    if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+    {
+            if (network->type == WLAN_BSS_TYPE_STA)
+            {
+                if_handle = net_get_mlan_handle();
+            }
+            CONNECTION_EVENT(WLAN_REASON_AUTH_SUCCESS, NULL);
+
+#if defined(SDK_OS_FREE_RTOS)
+#ifdef SD9177
+            (void)OSA_TimerActivate((osa_timer_handle_t)wlan.poll_timer);
+#endif
+#endif
+
+            wlan.bgscan_attempt = 0;
+
+#if CONFIG_WPA_SUPP
+            OSA_TimerDeactivate((osa_timer_handle_t)wlan.supp_status_timer);
+            wlan.status_timeout = 0;
+
+            wpa_supp_network_status(netif, network);
+#else
+            network->dot11n = wlan_11n_allowed(network);
+#if CONFIG_11AC
+            network->dot11ac = wlan_11ac_allowed(network);
+#endif
+#if CONFIG_11AX
+            network->dot11ax = wlan_11ax_allowed(network);
+#endif
+#endif
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_11R
+            wlan.same_ess = wifi_same_ess_ft();
+#endif
+            wlan.roam_reassoc = false;
+#endif
+            if (wlan.same_ess == true)
+            {
+#if CONFIG_11R
+                wlan.ft_bss = false;
+#endif
+                (void)net_get_if_addr((struct net_ip_config *)&network->ip, if_handle);
+                wlan.sta_state      = CM_STA_CONNECTED;
+                *next               = CM_STA_CONNECTED;
+                wlan.sta_ipv4_state = CM_STA_CONNECTED;
+
+                if (wlan.reassoc_control && wlan.reassoc_request)
+                {
+                    wlan.reassoc_count   = 0;
+                    wlan.reassoc_request = false;
+                }
+                mlan_adap->skip_dfs = false;
+                CONNECTION_EVENT(WLAN_REASON_SUCCESS, NULL);
+                return;
+            }
+
+#if CONFIG_STA_AUTO_DHCPV4
+            ret = net_configure_address((struct net_ip_config *)&network->ip, if_handle);
+            if (ret != 0)
+            {
+                wlcm_e("Configure Address failed");
+                do_connect_failed(WLAN_REASON_ADDRESS_FAILED);
+                *next = wlan.sta_state;
+            }
+            else
+            {
+                *next               = CM_STA_REQUESTING_ADDRESS;
+                wlan.sta_ipv4_state = CM_STA_REQUESTING_ADDRESS;
+#if CONFIG_IPV6
+                wlan.sta_ipv6_state = CM_STA_REQUESTING_ADDRESS;
+#endif
+            }
+#else
+            *next               = CM_STA_AUTHENTICATED;
+            wlan.sta_ipv4_state = CM_STA_AUTHENTICATED;
+#if CONFIG_IPV6
+            wlan.sta_ipv6_state = CM_STA_AUTHENTICATED;
+#endif
+#endif
+
+#if CONFIG_WPA2_ENTP
+        if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT &&
+            (network->security.type != WLAN_SECURITY_EAP_PEAP_MSCHAPV2))
+        {
+            wpa2_tls_cleanup(network, false);
+        }
+#endif
+    }
+    else
+    {
+#if CONFIG_WPA2_ENTP
+        if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+        {
+            wpa2_tls_cleanup(network, false);
+        }
+        else if (wlan_get_prov_session() == PROV_NON_SESSION_ATTEMPT &&
+                 network->security.pmk_valid == true &&
+                 (network->security.type == WLAN_SECURITY_EAP_TLS || network->security.type == WLAN_SECURITY_EAP_PEAP_MSCHAPV2)
+                )
+        {
+            /* If EAP_TLS re-connected but get auth failed, clear pmk_valid/pmk and enter "PROV_ENTP_SESSION_ATTEMPT" again */
+            network->security.pmk_valid = false;
+            memset(network->security.pmk, 0, WLAN_PMK_LENGTH);
+        }
+#endif
+        if (*((uint16_t *)msg->data) == IEEEtypes_REASON_MIC_FAILURE)
+        {
+            wlan.assoc_paused = true;
+            (void)OSA_TimerActivate((osa_timer_handle_t)wlan.assoc_timer);
+        }
+
+        if (is_state(CM_STA_REQUESTING_ADDRESS) || is_state(CM_STA_OBTAINING_ADDRESS))
+        {
+            void *if_handle = NULL;
+            /* On Link loss, we need to take down the interface. */
+            if (network->type == WLAN_BSS_TYPE_STA)
+            {
+                if_handle = net_get_mlan_handle();
+            }
+
+            if (if_handle != NULL)
+            {
+                /* Forcefully stop dhcp on given interface.
+                 * net_interface_dhcp_stop internally does nothing
+                 * if dhcp client is not started.
+                 */
+                net_interface_dhcp_stop(if_handle);
+                net_interface_down(if_handle);
+            }
+        }
+
+#if !CONFIG_WPA_SUPP
+        if (is_state(CM_STA_ASSOCIATED))
+        {
+            (void)wifi_deauthenticate((uint8_t *)network->bssid);
+        }
+#endif
+        wlan.sta_return_to  = CM_STA_IDLE;
+        wlan.sta_state      = CM_STA_IDLE;
+        *next               = CM_STA_IDLE;
+        wlan.sta_ipv4_state = CM_STA_IDLE;
+#if CONFIG_IPV6
+        wlan.sta_ipv6_state = CM_STA_IDLE;
+#endif
+
+#if !CONFIG_WPA_SUPP
+        do_connect_failed(WLAN_REASON_NETWORK_AUTH_FAILED);
+#endif
+
+        if (wlan.reassoc_control)
+        {
+            wlcm_request_reconnect(next, network);
+        }
+
+    }
+}
+
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_ROAMING)
+static void wlcm_process_rssi_low_event(struct wifi_message *msg, enum cm_sta_state *next, struct wlan_network *network)
+{
+    bool set_rssi_threshold = false;
+
+#if CONFIG_ROAMING
+    if (wlan.roaming_enabled == true)
+    {
+        if (wlan.roam_reassoc == false)
+        {
+            wlan.roam_reassoc = true;
+#if CONFIG_11R
+            wlan.ft_bss = false;
+            if ((network->ft_psk | network->ft_1x | network->ft_sae) == 1U)
+            {
+                wlan.ft_bss = true;
+            }
+#endif
+            int ret = wifi_config_bgscan_and_rssi(network->ssid);
+            if (ret == WM_SUCCESS)
+            {
+                wlcm_d("bgscan config successful");
+                return;
+            }
+            wlan.roam_reassoc = false;
+            set_rssi_threshold = true;
+        }
+        else
+        {
+            wlcm_d("Roaming already in progress");
+            (void)wifi_set_rssi_low_threshold(&wlan.rssi_low_threshold);
+            return;
+        }
+    }
+#endif /* CONFIG_ROAMING */
+
+#if CONFIG_11K
+    if (network->neighbor_report_supported == true)
+    {
+        int ret;
+        ret = wlan_host_11k_neighbor_req((const char *)network->ssid);
+        if (ret == WM_SUCCESS)
+        {
+            wlcm_d("Sent 11K neighbor request");
+            return;
+        }
+        set_rssi_threshold = true;
+    }
+#endif /* CONFIG_11K */
+
+#if CONFIG_11V
+    if (network->bss_transition_supported == true)
+    {
+        int ret;
+        ret = wlan_host_11v_bss_trans_query(0x10);
+        if (ret == WM_SUCCESS)
+        {
+            wlcm_d("Sent 11V bss transition query");
+            return;
+        }
+        set_rssi_threshold = true;
+    }
+#endif /* CONFIG_11V */
+
+    if (set_rssi_threshold == true)
+    {
+        (void)wifi_set_rssi_low_threshold(&wlan.rssi_low_threshold);
+    }
+}
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V)
+static void wlan_sort_nlist_channels(wlan_nlist_report_param *pnlist_rep_param)
+{
+    t_u8 i, j;
+
+    /* Bubble sort */
+    for (i = 0; i < pnlist_rep_param->num_channels; i++)
+    {
+        for (j = 1; j < pnlist_rep_param->num_channels - i; j++)
+        {
+            if ((t_u8)pnlist_rep_param->channels[j - 1] > (t_u8)pnlist_rep_param->channels[j])
+            {
+                SWAP_U8(pnlist_rep_param->channels[j - 1], pnlist_rep_param->channels[j]);
+            }
+        }
+    }
+}
+
+#if CONFIG_WPA_SUPP
+int wlan_11k_roam()
+{
+    int ret;
+    struct wlan_network *network = &wlan.networks[wlan.cur_network_idx];
+    wlan_nlist_report_param *pnlist_rep_param = (wlan_nlist_report_param *)&wlan.nlist_rep_param;
+    t_u8 i;
+    wlan_scan_params_v2_t params;
+    struct netif *netif = net_get_sta_interface();
+
+    if (is_state(CM_STA_IDLE))
+    {
+        (void)PRINTF("Station is not connected\r\n");
+        return -WM_FAIL;
+    }
+
+    memset(&params, 0x00, sizeof(wlan_scan_params_v2_t));
+
+    memcpy(params.ssid, network->ssid, strlen(network->ssid));
+    params.is_ssid = 1;
+
+    params.num_channels = pnlist_rep_param->num_channels;
+
+    for (i = 0; i < pnlist_rep_param->num_channels; i++)
+    {
+        params.chan_list[i].chan_number = (t_u8)pnlist_rep_param->channels[i];
+        params.chan_list[i].scan_type   = MLAN_SCAN_TYPE_ACTIVE;
+        params.chan_list[i].scan_time   = 60;
+
+    }
+
+    ret = wpa_supp_roam(netif, NULL);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("wlan ft roam failed");
+        return -WM_FAIL;
+    }
+
+    ret = wpa_supp_scan(netif, &params);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("wlan ft roam scan failed");
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+static void wlcm_process_neighbor_list_report_event(struct wifi_message *msg,
+                                                    enum cm_sta_state *next,
+                                                    struct wlan_network *network)
+{
+    // unsigned int i;
+    int ret;
+    wlan_nlist_report_param *pnlist_rep_param = (wlan_nlist_report_param *)&wlan.nlist_rep_param;
+
+    if (is_state(CM_STA_IDLE) || (pnlist_rep_param == NULL))
+    {
+        wlcm_d("ignoring neighbor list report event in idle state");
+        return;
+    }
+
+#if CONFIG_11K
+    if (pnlist_rep_param->nlist_mode == WLAN_NLIST_11K)
+    {
+        wlan.neighbor_req = false;
+        (void)OSA_TimerDeactivate((osa_timer_handle_t)wlan.neighbor_req_timer);
+    }
+#endif
+
+    wlan_sort_nlist_channels(pnlist_rep_param);
+
+    ret = wlan_11k_roam();
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("11k roam failed");
+    }
+
+    memset(&wlan.nlist_rep_param, 0x00, sizeof(wlan_nlist_report_param));
+}
+#else
+static void wlcm_process_neighbor_list_report_event(struct wifi_message *msg,
+                                                    enum cm_sta_state *next,
+                                                    struct wlan_network *network)
+{
+    unsigned int i;
+    int ret;
+    wlan_scan_channel_list_t chan_list[MAX_NUM_CHANS_IN_NBOR_RPT];
+    t_u8 *bssid                               = NULL;
+    wlan_nlist_report_param *pnlist_rep_param = (wlan_nlist_report_param *)msg->data;
+
+    wlan.roam_reassoc = false;
+
+    if (is_state(CM_STA_IDLE) || (pnlist_rep_param == NULL))
+    {
+        wlcm_d("ignoring neighbor list report event in idle state");
+        return;
+    }
+
+#if CONFIG_11K
+    if (pnlist_rep_param->nlist_mode == WLAN_NLIST_11K)
+    {
+        wlan.neighbor_req = false;
+        (void)OSA_TimerDeactivate((osa_timer_handle_t)wlan.neighbor_req_timer);
+    }
+#endif
+
+#if CONFIG_11V
+    if ((pnlist_rep_param->nlist_mode == WLAN_NLIST_11V) || (pnlist_rep_param->nlist_mode == WLAN_NLIST_11V_PREFERRED))
+    {
+        wlan.neighbor_req = false;
+        (void)OSA_TimerDeactivate((osa_timer_handle_t)wlan.neighbor_req_timer);
+    }
+#endif
+
+    wlan_sort_nlist_channels(pnlist_rep_param);
+    memcpy(&wlan.nlist_rep_param, pnlist_rep_param, sizeof(wlan_nlist_report_param));
+
+#if CONFIG_11V
+    if (pnlist_rep_param->nlist_mode == WLAN_NLIST_11V_PREFERRED)
+    {
+        bssid = pnlist_rep_param->bssid;
+    }
+#endif
+
+    for (i = 0; i < pnlist_rep_param->num_channels; i++)
+    {
+        chan_list[i].chan_number = (t_u8)pnlist_rep_param->channels[i];
+        chan_list[i].scan_type   = MLAN_SCAN_TYPE_ACTIVE;
+        chan_list[i].scan_time   = 60;
+    }
+
+#if CONFIG_11R
+    wlan.ft_bss = false;
+    if ((network->ft_psk | network->ft_1x | network->ft_sae) == 1U)
+    {
+        wlan.ft_bss = true;
+    }
+#endif
+    wlan.roam_reassoc = true;
+    ret = wifi_send_scan_cmd((t_u8)BSS_INFRASTRUCTURE, bssid, network->ssid, 1, pnlist_rep_param->num_channels,
+                             chan_list, 0,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                             0,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                             scan_channel_gap,
+#endif
+                             false, false);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("neighbor list scan failed");
+#if CONFIG_11R
+        wlan.ft_bss = false;
+#endif
+        wlan.roam_reassoc = false;
+    }
+
+    if (pnlist_rep_param != NULL)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree((void *)pnlist_rep_param);
+#else
+        OSA_MemoryPoolFree(buf_128_MemoryPool, pnlist_rep_param);
+#endif
+    }
+}
+#endif
+#endif
+
+#if CONFIG_11R
+#if CONFIG_WPA_SUPP
+int wlan_ft_roam(const t_u8 *bssid, const t_u8 channel)
+{
+    int ret;
+    wlan_scan_params_v2_t params;
+    t_u8 curr_bss[MLAN_MAC_ADDR_LENGTH] = {0};
+
+    struct netif *netif = net_get_sta_interface();
+
+    if (is_state(CM_STA_IDLE))
+    {
+        (void)PRINTF("Station is not connected\r\n");
+        return -WM_FAIL;
+    }
+    if (wlan.roam_reassoc == true)
+    {
+        (void)PRINTF("Roaming already in progress\r\n");
+        return WM_SUCCESS;
+    }
+
+    wlan.roam_reassoc = false;
+
+    memset(&params, 0x00, sizeof(wlan_scan_params_v2_t));
+
+    if (bssid)
+    {
+        if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+        {
+            memcpy(curr_bss, wlan.networks[wlan.cur_network_idx].bssid, MLAN_MAC_ADDR_LENGTH);
+            if(memcmp(curr_bss, bssid, MLAN_MAC_ADDR_LENGTH) == 0)
+            {
+                (void)PRINTF("Already connected to this BSS. Skip roaming.\r\n");
+                return WM_SUCCESS;
+            }
+        }
+        memcpy(params.bssid, bssid, MLAN_MAC_ADDR_LENGTH);
+        params.is_bssid = 1;
+    }
+
+    if (channel)
+    {
+        params.num_channels = 1;
+        params.chan_list[0].chan_number = channel;
+    }
+
+    ret = wpa_supp_roam(netif, (t_u8 *)bssid);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_d("wlan ft roam failed");
+        return -WM_FAIL;
+    }
+
+    ret = wpa_supp_scan(netif, &params);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_d("wlan ft roam scan failed");
+        return -WM_FAIL;
+    }
+
+    wlan.roam_reassoc = true;
+
+    (void)OSA_TimerActivate((osa_timer_handle_t)wlan.ft_roam_timer);
+
+    (void)PRINTF("Started FT Roaming...\r\n");
+
+    return WM_SUCCESS;
+}
+#else
+static wlan_scan_channel_list_t chan_list;
+int wlan_ft_roam(const t_u8 *bssid, const t_u8 channel)
+{
+    struct wlan_network *network = &wlan.networks[wlan.cur_network_idx];
+
+    if (is_state(CM_STA_IDLE))
+    {
+        (void)PRINTF("Station is not connected\r\n");
+        return -WM_FAIL;
+    }
+
+    if ((network->ft_psk | network->ft_1x | network->ft_sae) == 1U)
+    {
+        int ret;
+
+        chan_list.chan_number = channel;
+        chan_list.scan_type   = MLAN_SCAN_TYPE_ACTIVE;
+        chan_list.scan_time   = 120;
+
+        wlan.ft_bss       = true;
+        wlan.roam_reassoc = true;
+        ret               = wifi_send_scan_cmd((t_u8)BSS_INFRASTRUCTURE, bssid, network->ssid, 1, 1, &chan_list, 0,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                                 0,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                                 scan_channel_gap,
+#endif
+                                 false, false);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("wlan ft roam scan failed");
+            wlan.ft_bss       = false;
+            wlan.roam_reassoc = false;
+            return -WM_FAIL;
+        }
+
+        return WM_SUCCESS;
+    }
+    else
+    {
+        (void)PRINTF("Current associated AP do not support FT BSS transition\r\n");
+    }
+
+    return -WM_FAIL;
+}
+#endif
+#endif
+
+#if CONFIG_ECSA
+static int wlan_check_valid_channel_operclass(t_u8 channel, t_u8 oper_class)
+{
+    int ret = 0;
+    mlan_ioctl_req req;
+    mlan_ds_misc_cfg *misc = NULL;
+    mlan_status status     = MLAN_STATUS_SUCCESS;
+
+    (void)memset(&req, 0x00, sizeof(mlan_ioctl_req));
+#if !CONFIG_MEM_POOLS
+    misc = OSA_MemoryAllocate(sizeof(mlan_ds_misc_cfg));
+#else
+    misc = OSA_MemoryPoolAllocate(buf_3072_MemoryPool);
+#endif
+    if (misc == NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    req.bss_index                       = MLAN_BSS_ROLE_UAP;
+    req.pbuf                            = (t_u8 *)misc;
+    misc->sub_command                   = MLAN_OID_MISC_OPER_CLASS_CHECK;
+    req.req_id                          = MLAN_IOCTL_MISC_CFG;
+    req.action                          = MLAN_ACT_GET;
+    misc->param.bw_chan_oper.oper_class = oper_class;
+    misc->param.bw_chan_oper.channel    = channel;
+
+    status = wlan_ops_uap_ioctl(mlan_adap, &req);
+    if (status != MLAN_STATUS_SUCCESS)
+    {
+        PRINTM(MERROR, "Failed to get operclass\n");
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(misc);
+#else
+        OSA_MemoryPoolFree(buf_3072_MemoryPool, misc);
+#endif
+        return -WM_FAIL;
+    }
+
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(misc);
+#else
+        OSA_MemoryPoolFree(buf_3072_MemoryPool, misc);
+#endif
+
+    return ret;
+}
+
+static int wlan_set_uap_ecsa_cfg(
+    t_u8 block_tx, t_u8 oper_class, t_u8 channel, t_u8 switch_count, t_u8 band_width, t_u8 ecsa)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    bool block_tx_flag   = (1 == block_tx) ? true : false;
+
+    if (wlan_11h_radar_detect_required(pmpriv, channel))
+    {
+        wlcm_e("Please set non-dfs channel");
+        return -WM_FAIL;
+    }
+
+    if ((channel > MAX_CHANNELS_BG) && ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        wlcm_e("Not support 5G, please set 2G channel");
+        return -WM_FAIL;
+    }
+
+    if (wlan_check_channel_by_region_table(pmpriv, channel) == MFALSE)
+    {
+        (void)PRINTF("uAP target channel not allowed\n\r");
+        return -WM_FAIL;
+    }
+
+    if (is_uap_started() && (!is_sta_connected()))
+    {
+        if (oper_class)
+        {
+            if (wlan_check_valid_channel_operclass(channel, oper_class))
+            {
+                wlcm_e("Wrong channel switch parameters!");
+                return -EINVAL;
+            }
+        }
+
+        set_ecsa_block_tx_flag(block_tx_flag);
+
+        if (0 != switch_count)
+        {
+            set_ecsa_block_tx_time(switch_count);
+            return wifi_set_ecsa_cfg(block_tx, oper_class, channel, switch_count, band_width, ecsa);
+        }
+        else
+        {
+            return wifi_set_action_ecsa_cfg(block_tx, oper_class, channel, switch_count);
+        }
+    }
+    else
+    {
+        wlcm_e("uap isn't up OR station is connected");
+        return -WM_FAIL;
+    }
+}
+
+static void wlan_switch_to_nondfs_channel(void)
+{
+    mlan_private *pmpriv = (mlan_private *)mlan_adap->priv[1];
+    t_u8 uap_channel     = 0;
+    t_u8 block_tx        = 1;
+    t_u8 oper_class      = 0;
+    t_u8 switch_count    = DEF_SWITCH_COUNT;
+    t_u8 band_width      = 0;
+    t_u8 ecsa            = MTRUE;
+
+    if (is_uap_started())
+    {
+        uap_channel = (t_u8)wlan.networks[wlan.cur_uap_network_idx].channel;
+
+        if (MTRUE == wlan_11h_radar_detect_required(pmpriv, uap_channel))
+        {
+            if (MLAN_STATUS_SUCCESS == wlan_get_non_dfs_chan(pmpriv, &uap_channel))
+            {
+                wlan_set_uap_ecsa_cfg(block_tx, oper_class, uap_channel, switch_count, band_width, ecsa);
+            }
+            else
+            {
+                return;
+            }
+        }
+    }
+}
+#endif
+
+static void wlcm_process_link_loss_event(struct wifi_message *msg,
+                                         enum cm_sta_state *next,
+                                         struct wlan_network *network)
+{
+    /* We're being informed about an asynchronous link loss (ex: beacon loss
+     * counter detected that the AP is gone, security failure, etc). If we
+     * were connected, we need to report this event and proceed to idle.
+     * If we were in the middle of a connection attempt, we need to treat
+     * this as a connection attempt failure via do_connect_fail() and
+     * proceed accordingly.
+     */
+    if (is_state(CM_STA_IDLE))
+    {
+        wlcm_d("ignoring link loss event in idle state");
+        return;
+    }
+
+    void *if_handle = NULL;
+    /* On Link loss, we need to take down the interface. */
+    if (network->type == WLAN_BSS_TYPE_STA)
+    {
+        if_handle = net_get_mlan_handle();
+    }
+
+    if (if_handle != NULL)
+    {
+        /* Forcefully stop dhcp on given interface.
+         * net_interface_dhcp_stop internally does nothing
+         * if dhcp client is not started.
+         */
+        net_interface_dhcp_stop(if_handle);
+        net_interface_down(if_handle);
+    }
+
+    /* If we were connected and lost the link, we must report that now and
+     * return to CM_STA_IDLE
+     */
+    if (is_state(CM_STA_CONNECTED))
+    {
+        if (is_user_scanning() != 0)
+        {
+            wlan.sta_return_to = CM_STA_IDLE;
+        }
+        else
+        {
+            *next = CM_STA_IDLE;
+        }
+        wlan.sta_state      = CM_STA_IDLE;
+        wlan.sta_ipv4_state = CM_STA_IDLE;
+#if CONFIG_IPV6
+        wlan.sta_ipv6_state = CM_STA_IDLE;
+#endif
+        if ((int)msg->data == IEEEtypes_REASON_MIC_FAILURE)
+        {
+            /* In case of a LINK loss because of bad MIC
+             * failure, directly send a deauth.
+             */
+            wlcm_d(
+                "Sending deauth because of"
+                " successive bad MIC failures");
+            (void)wlan_disconnect();
+            *next = CM_STA_IDLE;
+        }
+
+#if CONFIG_11MC
+        g_ftm_civic_cfg.civic_req = 0;
+        g_ftm_location_cfg.lci_req = 0;
+#endif
+        CONNECTION_EVENT(WLAN_REASON_LINK_LOST, NULL);
+#if CONFIG_ECSA
+        wrapper_clear_media_connected_event();
+        wlan_switch_to_nondfs_channel();
+#endif
+    }
+    else
+    {
+        /* Stop the dhcp timer first after link lost occurs, as the dhcp timer
+         * callback may lead to that the connection state is out-of-sync with FW */
+        net_stop_dhcp_timer();
+
+        /* we were attempting a connection and lost the link,
+         * so treat this as a connection attempt failure
+         */
+        switch ((int)msg->data)
+        {
+            case IEEEtypes_REASON_4WAY_HANDSHK_TIMEOUT:
+                do_connect_failed(WLAN_REASON_NETWORK_AUTH_FAILED);
+                break;
+            default:
+                do_connect_failed(WLAN_REASON_NETWORK_AUTH_FAILED);
+                break;
+        }
+        *next = wlan.sta_state;
+    }
+#if CONFIG_WPA2_ENTP
+    if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+    {
+        wpa2_tls_cleanup(network, false);
+    }
+#endif
+
+#if !CONFIG_WPA_SUPP
+    if (wlan.reassoc_control)
+    {
+        wlcm_request_reconnect(next, network);
+    }
+#endif
+}
+
+
+static void wlcm_process_disassoc_event(struct wifi_message *msg, enum cm_sta_state *next, struct wlan_network *network)
+{
+    /* We're being informed about an asynchronous disassociation from AP
+     * As were in the middle of a connection attempt, we need to treat
+     * this as a connection attempt failure via do_connect_fail() and
+     * proceed accordingly.
+     */
+#if CONFIG_WPA2_ENTP
+    if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+    {
+        wpa2_tls_cleanup(network, false);
+    }
+    else if (wlan_get_prov_session() == PROV_NON_SESSION_ATTEMPT && is_state(CM_STA_CONNECTED) &&
+             network->security.pmk_valid == true &&
+             (network->security.type == WLAN_SECURITY_EAP_TLS || network->security.type == WLAN_SECURITY_EAP_PEAP_MSCHAPV2)
+            )
+    {
+        /* Connects with security EAP_TLS, if AP reset PMK and send disassoc, STA clear pmk_valid/pmk and enter "PROV_ENTP_SESSION_ATTEMPT" again */
+        network->security.pmk_valid = false;
+        memset(network->security.pmk, 0, WLAN_PMK_LENGTH);
+    }
+#endif
+    if (is_user_scanning() != 0)
+    {
+        wlan.sta_return_to = CM_STA_IDLE;
+    }
+    *next          = CM_STA_IDLE;
+    wlan.sta_state = CM_STA_IDLE;
+
+    do_connect_failed(WLAN_REASON_NETWORK_AUTH_FAILED);
+
+    if (wlan.reassoc_control)
+    {
+        wlcm_request_reconnect(next, network);
+    }
+}
+
+static void wlcm_process_deauthentication_event(struct wifi_message *msg,
+                                                enum cm_sta_state *next,
+                                                struct wlan_network *network)
+{
+#if CONFIG_WPA2_ENTP
+    if (wlan_get_prov_session() == PROV_ENTP_SESSION_ATTEMPT)
+    {
+        wpa2_tls_cleanup(network, false);
+    }
+#endif
+#if CONFIG_WPA_SUPP
+    if ((network->security.type == WLAN_SECURITY_WPA3_SAE ||
+         network->security.type == WLAN_SECURITY_WPA3_SAE_EXT_KEY) &&
+        (msg->reason == WLAN_REASON_PREV_AUTH_NOT_VALID ||
+        msg->reason == WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY ||
+        msg->reason == WLAN_REASON_INVALID_IE))
+    {
+        /*
+         *  Clear pmksa cache in case AP wants to redo sae auth.
+         *  But send successful assoc resp and send deauth right after.
+         *  Then we will always using pmksa cache if it exists.
+         */
+        wlan_pmksa_flush();
+    }
+#endif
+    wlan_handle_disconnect_event(mlan_adap->priv[0]);
+}
+
+static void wlcm_process_net_dhcp_config(struct wifi_message *msg,
+                                         enum cm_sta_state *next,
+                                         struct wlan_network *network)
+{
+    /* We have received a response from the embedded DHCP client.  If
+     * successful, we now have a DHCP lease and can update our IP address
+     * information and procceed to the CM_STA_CONNECTED state, otherwise we
+     * failed to obtain a DHCP lease and report that we failed to connect.
+     *
+     * This event is only relevant if we are attempting a connection and
+     * are in the CM_STA_OBTAINING_ADDRESS state (due to configuring the TCP
+     * stack with DHCP), otherwise we ignore it. */
+
+    void *if_handle = NULL;
+    // wakelock_put(WL_ID_CONNECT);
+    // wlan.connect_wakelock_taken = false;
+    if (wlan.sta_ipv4_state == CM_STA_OBTAINING_ADDRESS)
+    {
+        if (wlan.connect_wakelock_taken)
+        {
+#if CONFIG_HOST_SLEEP
+            wakelock_put();
+#endif
+            wlan.connect_wakelock_taken = false;
+        }
+        if (msg->reason != WIFI_EVENT_REASON_SUCCESS)
+        {
+            wlcm_d("got event: DHCP failure");
+#if CONFIG_IPV6
+            if (wlan.sta_ipv6_state != CM_STA_CONNECTED)
+            {
+#endif
+
+                do_connect_failed(WLAN_REASON_ADDRESS_FAILED);
+
+                if (wlan.reassoc_control)
+                {
+                    wlcm_request_reconnect(next, network);
+                }
+
+                *next = wlan.sta_state;
+#if CONFIG_IPV6
+            }
+            else if (wlan.sta_ipv6_state == CM_STA_CONNECTED)
+            {
+                wlan.sta_state = CM_STA_CONNECTED;
+                *next          = CM_STA_CONNECTED;
+                if (network->type == WLAN_BSS_TYPE_STA)
+                {
+                    if_handle = net_get_mlan_handle();
+                }
+
+                net_interface_up(if_handle);
+                mlan_adap->skip_dfs = false;
+                CONNECTION_EVENT(WLAN_REASON_SUCCESS, NULL);
+            }
+            else
+            {
+                /* Do Nothing */
+            }
+#endif
+            return;
+        }
+        char ip[16];
+        wlcm_d("got event: DHCP success");
+        net_stop_dhcp_timer();
+        net_configure_dns((struct net_ip_config *)&network->ip, network->role);
+        if (network->type == WLAN_BSS_TYPE_STA)
+        {
+            if_handle = net_get_mlan_handle();
+        }
+        (void)net_get_if_addr((struct net_ip_config *)&network->ip, if_handle);
+        // net_inet_ntoa(network->ip.ipv4.address, ip);
+        wlan.sta_state      = CM_STA_CONNECTED;
+        *next               = CM_STA_CONNECTED;
+        wlan.sta_ipv4_state = CM_STA_CONNECTED;
+
+#if CONFIG_WPS2
+        wlan_set_prov_session(PROV_NON_SESSION_ATTEMPT);
+#endif
+        if (wlan.reassoc_control && wlan.reassoc_request)
+        {
+            wlan.reassoc_count   = 0;
+            wlan.reassoc_request = false;
+        }
+        mlan_adap->skip_dfs = false;
+        CONNECTION_EVENT(WLAN_REASON_SUCCESS, &ip);
+
+    }
+    else
+    {
+        wlcm_d("got event from dhcp client %d", msg->reason);
+        if (msg->reason != WIFI_EVENT_REASON_SUCCESS)
+        {
+            /* There was some problem with dhcp lease
+             * renewal, so just disconnect from wlan.
+             */
+
+#if CONFIG_IPV6
+            /* Do not disconnect-connect if the STA interface has
+             * obtained IPv6 address */
+            if (wlan.sta_ipv6_state != CM_STA_CONNECTED)
+            {
+#endif
+                if (wlan.sta_ipv4_state == CM_STA_CONNECTED)
+                {
+                    wlcm_d("Lease renewal failed, disconnecting");
+
+
+                    do_connect_failed(WLAN_REASON_ADDRESS_FAILED);
+
+                    if (wlan.reassoc_control)
+                    {
+                        wlcm_request_reconnect(next, network);
+                    }
+
+                    *next = wlan.sta_state;
+                }
+#if CONFIG_IPV6
+            }
+#endif
+            return;
+        }
+        /* Successful in getting ip address, so update
+         * local wlan-info params */
+        wlcm_d("update wlan-info params");
+        if (network->type == WLAN_BSS_TYPE_STA)
+        {
+            if_handle = net_get_mlan_handle();
+        }
+        (void)net_get_if_addr((struct net_ip_config *)&network->ip, if_handle);
+        CONNECTION_EVENT(WLAN_REASON_ADDRESS_SUCCESS, NULL);
+    }
+}
+
+#if CONFIG_IPV6
+static void wlcm_process_net_ipv6_config(struct wifi_message *msg,
+                                         enum cm_sta_state *next,
+                                         struct wlan_network *network)
+{
+    void *if_handle = net_get_mlan_handle();
+    int i, found = 0;
+    if (network->type != WLAN_BSS_TYPE_STA || (if_handle == NULL))
+    {
+        return;
+    }
+
+    net_get_if_ipv6_addr((struct net_ip_config *)&network->ip, if_handle);
+#ifndef __ZEPHYR__
+    for (i = 0; i < CONFIG_MAX_IPV6_ADDRESSES; i++)
+    {
+        if (ip6_addr_isvalid((network->ip.ipv6[i].addr_state)) != 0U)
+#else
+    for (i = 0; i < CONFIG_MAX_IPV6_ADDRESSES && i < network->ip.ipv6_count; i++)
+    {
+        if ((network->ip.ipv6[i].addr_state == NET_ADDR_TENTATIVE) ||
+                (network->ip.ipv6[i].addr_state == NET_ADDR_PREFERRED))
+#endif
+        {
+            found++;
+            /* Not considering link-local address as of now */
+            if (wlan.sta_ipv6_state != CM_STA_CONNECTED)
+            {
+                wlan.sta_ipv6_state = CM_STA_CONNECTED;
+
+                if (wlan.reassoc_control && wlan.reassoc_request)
+                {
+                    wlan.reassoc_count   = 0;
+                    wlan.reassoc_request = false;
+                }
+            }
+        }
+    }
+
+    if (wlan.sta_ipv6_state >= CM_STA_OBTAINING_ADDRESS && !found)
+    {
+        /* If the state is either obtaining address or connected and
+         * if none of the IP addresses is preferred, then
+         * change/maintain the state to obtaining address */
+        wlan.sta_ipv6_state = CM_STA_OBTAINING_ADDRESS;
+    }
+}
+#endif /* CONFIG_IPV6 */
+
+int wlan_rx_mgmt_indication(const enum wlan_bss_type bss_type,
+                            const uint32_t mgmt_subtype_mask,
+                            int (*rx_mgmt_callback)(const enum wlan_bss_type bss_type,
+                                                    const wlan_mgmt_frame_t *frame,
+                                                    const size_t len))
+{
+#ifdef MGMT_RX
+    if (mgmt_subtype_mask)
+        rx_mgmt_register_callback(rx_mgmt_callback);
+    else
+        rx_mgmt_deregister_callback();
+#endif
+
+    return wifi_set_rx_mgmt_indication(bss_type, mgmt_subtype_mask);
+}
+
+#if CONFIG_WPA_SUPP
+
+static void wlcm_process_scan_failed()
+{
+    if (wlan.pending_disconnect_request == true)
+    {
+        wlan_disconnect();
+    }
+}
+
+#define IEEEtypes_REASON_DEAUTH_LEAVING     3
+
+static void wlcm_process_disconnected()
+{
+    (void)wifi_event_completion(WIFI_EVENT_LINK_LOSS, WIFI_EVENT_REASON_FAILURE, (void *)IEEEtypes_REASON_DEAUTH_LEAVING);
+}
+
+#if CONFIG_11K
+static void wlan_parse_neighbor_report_response(const char *nbr_response, wlan_rrm_neighbor_report_t *nbr_rpt)
+{
+    char event[32] = {0};
+    char bssid[32] = {0};
+    char info[32]  = {0};
+    int op_class,channel,phy_type;
+
+    if (!nbr_response || nbr_response[0] == '\0')
+    {
+        wlcm_e("11K: Neighbor response is NULL");
+        return;
+    }
+    else if (!nbr_rpt)
+    {
+        wlcm_e("11K: Input Neighbor report is NULL");
+        return;
+    }
+
+// Sample Response Pattern
+//<3>RRM-NEIGHBOR-REP-RECEIVED bssid=ec:aa:a0:81:7f:20 info=0x1801 op_class=0 chan=153 phy_type=1 lci=0100080010000000000000000000000000000000000406000000000000060101 civic=02000b0000ed000000
+
+    if (sscanf(nbr_response,"%s bssid=%s info=%s op_class=%d chan=%d phy_type=%d", event, bssid, info, &op_class, &channel, &phy_type) == 6)
+    {
+        int i;
+        int match  = 0;
+        size_t len = 0;
+
+        // Check if the bssid is already present in list
+
+        for (i = 0; i < nbr_rpt->neighbor_cnt; i++)
+        {
+            if (strncmp((const char *)nbr_rpt->neighbor_ap[i].bssid, bssid, 32) == 0)
+            {
+                match = 1;
+                break;
+            }
+
+            if (nbr_rpt->neighbor_ap[i].channel == channel)
+            {
+                match = 1;
+                break;
+            }
+        }
+
+        if (!match && (nbr_rpt->neighbor_cnt < MAX_NEIGHBOR_AP_LIMIT))
+        {
+            strncpy((char *)nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].bssid, bssid, sizeof(nbr_rpt->neighbor_ap->bssid));
+            len = strlen(bssid);
+            nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].bssid[len] = (t_u8)'\0';
+
+            strncpy((char *)nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].bssidInfo, info, sizeof(nbr_rpt->neighbor_ap->bssidInfo));
+            len = strlen(info);
+            nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].bssidInfo[len] = (t_u8)'\0';
+
+            nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].channel = channel;
+            wlan.nlist_rep_param.channels[wlan.nlist_rep_param.num_channels] = channel;
+            nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].op_class = op_class;
+            nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].phy_type = phy_type;
+            //nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].freq = wifi_getRadioFrequencyFromChannel(channel);
+
+            wlcm_d("RRM Neighbor[%d] - Bssid = %s , Info = %s, op_class=%d, Channel = %d, Phy_Type = %d, Freq=%d ", nbr_rpt->neighbor_cnt, nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].bssid, nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].bssidInfo, nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].op_class, nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].channel,nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].phy_type,nbr_rpt->neighbor_ap[nbr_rpt->neighbor_cnt].freq);
+
+            nbr_rpt->neighbor_cnt += 1;
+            wlan.nlist_rep_param.num_channels += 1;
+
+            wlan.nlist_rep_param.nlist_mode = WLAN_NLIST_11K;
+        }
+        else if (match)
+        {
+            wlcm_d("BSSID already present in neighbor list, Skipping %s ",bssid);
+        }
+        else
+        {
+            wlcm_d("Maximum neighbors added to list, Skipping.");
+        }
+    }
+    else
+    {
+        wlcm_d("Failed to Parse Neighbor Report - Skipping entry\n");
+    }
+}
+#endif
+
+#if CONFIG_WPA_SUPP
+static int wlcm_process_add_unspecified_network(const char *name)
+{
+    int ret, i;
+    struct wlan_network *network;
+    size_t len       = 0;
+    const char *ssid = "w";
+
+    network = OSA_MemoryAllocate(sizeof(struct wlan_network));
+
+    if (network == NULL)
+    {
+        wlcm_d("%s: Failed to alloc wlan_network network", __func__);
+        return -WM_FAIL;
+    }
+
+    (void)memset(network, 0, sizeof(struct wlan_network));
+    (void)memcpy(network->name, name, strlen(name));
+    len = strlen(name);
+    network->name[len] = '\0';
+    (void)memcpy(network->ssid, ssid, strlen(ssid));
+
+    network->ip.ipv4.addr_type = ADDR_TYPE_DHCP;
+
+    ret = wlan_add_network(network);
+
+    OSA_MemoryFree(network);
+
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Failed to add wps network");
+        return ret;
+    }
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0' && strlen(wlan.networks[i].name) == len &&
+                !strncmp(wlan.networks[i].name, name, len))
+        {
+            wlan.cur_network_idx = i;
+            break;
+        }
+    }
+    return WM_SUCCESS;
+}
+#endif
+
+static void wpa_supplicant_msg_cb(const char *buf, size_t len)
+{
+    const char *s;
+    unsigned char is_11n_enabled;
+    int ret;
+    struct netif *netif = net_get_uap_interface();
+    struct netif *sta_netif = net_get_sta_interface();
+    struct wlan_network *network = &wlan.networks[wlan.cur_network_idx];
+
+    wlcm_d("%s: %s", __func__, buf);
+
+    if (strstr(buf, WPA_EVENT_SCAN_FAILED))
+    {
+        wlcm_process_scan_failed();
+    }
+    else if (strstr(buf, WPA_EVENT_DISCONNECTED))
+    {
+        wlcm_process_disconnected();
+        wlan_handle_disconnect_event(mlan_adap->priv[0]);
+    }
+    else if (strstr(buf, WPA_EVENT_NETWORK_NOT_FOUND))
+    {
+        wlcm_d("No suitable network was found");
+
+        if (wlan.roam_reassoc == true)
+        {
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_ROAMING)
+            (void)wifi_set_rssi_low_threshold(&wlan.rssi_low_threshold);
+            wlan.roam_reassoc = false;
+#endif
+        }
+        else
+        {
+            wlan.scan_count++;
+
+            do_connect_failed(WLAN_REASON_NETWORK_NOT_FOUND);
+
+            if (wlan.scan_count > WLAN_RESCAN_LIMIT)
+            {
+                wlan.cur_network_idx = -1;
+                (void)wpa_supp_disable(sta_netif, network);
+            }
+        }
+    }
+    else if (strstr(buf, WPA_EVENT_AUTH_REJECT))
+    {
+        wlcm_d("Authentication rejected during connection attempt");
+        if ((wlan.roam_reassoc != true) && (!(strlen(buf) > strlen(WPA_EVENT_AUTH_REJECT))))
+        {
+            (void)send_user_request(CM_STA_USER_REQUEST_CONNECT, wlan.cur_network_idx);
+        }
+        wlan.roam_reassoc = false;
+    }
+    else if (strstr(buf, AP_STA_CONNECTED))
+    {
+        wlcm_d("AP: Station connected");
+        t_u8 addr[MLAN_MAC_ADDR_LENGTH];
+
+        s = strchr(buf, ' ');
+        if (s == NULL)
+            return;
+
+        if (hwaddr_aton(s + 1, addr))
+            return;
+
+        ret = wpa_supp_get_sta_info(netif, addr, &is_11n_enabled);
+        if (ret != 0)
+            return;
+
+        wifi_uap_client_assoc(addr, is_11n_enabled);
+
+        CONNECTION_EVENT(WLAN_REASON_UAP_CLIENT_CONN, addr);
+    }
+    if (strstr(buf, AP_STA_DISCONNECTED))
+    {
+        wlcm_d("AP: Station dis-connected");
+
+        wifi_uap_client_disassoc_t disassoc_resp;
+
+        disassoc_resp.reason_code = 0;
+
+        s = strchr(buf, ' ');
+        if (s == NULL)
+            return;
+
+        if (hwaddr_aton(s + 1, disassoc_resp.sta_addr))
+            return;
+
+        wifi_uap_client_deauth(disassoc_resp.sta_addr);
+
+        CONNECTION_EVENT(WLAN_REASON_UAP_CLIENT_DISSOC, (void *)&disassoc_resp);
+    }
+#if CONFIG_WPA_SUPP_WPS
+    else if (strstr(buf, WPS_EVENT_OVERLAP))
+    {
+        wlcm_d("WPS overlap detected in PBC mode");
+    }
+    else if (strstr(buf, WPS_EVENT_AP_AVAILABLE_PBC))
+    {
+        wlcm_d("Available WPS AP with active PBC found in scan results");
+    }
+    else if (strstr(buf, WPS_EVENT_AP_AVAILABLE_PIN))
+    {
+        wlcm_d("Available WPS AP with recently selected PIN registrar found in scan results");
+    }
+    else if (strstr(buf, WPS_EVENT_AP_AVAILABLE))
+    {
+        wlcm_d("Available WPS AP found in scan results");
+    }
+    else if (strstr(buf, WPS_EVENT_CRED_RECEIVED))
+    {
+        wlcm_d("A new credential received");
+    }
+    else if (strstr(buf, WPS_EVENT_DISABLE))
+    {
+        wlcm_d("PBC mode was disabled");
+        wlan.wps_session_attempt = 0;
+    }
+    else if (strstr(buf, WPS_EVENT_ACTIVE))
+    {
+        wlcm_d("PBC mode was activated");
+        wlan.wps_session_attempt = 1;
+    }
+    else if (strstr(buf, WPS_EVENT_PIN_ACTIVE))
+    {
+        wlcm_d("PIN mode was activated");
+        wlan.wps_session_attempt = 1;
+    }
+    else if (strstr(buf, WPS_EVENT_TIMEOUT))
+    {
+        wlcm_d("WPS enrollment attempt timed out and was terminated");
+        wlan.wps_session_attempt = 0;
+    }
+    else if (strstr(buf, WPS_EVENT_FAIL))
+    {
+        wlcm_d("WPS registration failed after M2/M2D");
+        wlan.wps_session_attempt = 0;
+    }
+    else if (strstr(buf, WPS_EVENT_CANCEL))
+    {
+        wlcm_d("WPS mode was canceled");
+        wlan.wps_session_attempt = 0;
+    }
+    else if (strstr(buf, WPS_EVENT_SUCCESS))
+    {
+        wlcm_d("WPS registration completed successfully");
+        if (wlan.wps_session_attempt)
+        {
+            if (wlcm_process_add_unspecified_network("wps_network") == WM_SUCCESS)
+            {
+                wlan.wps_session_attempt = 0;
+            }
+        }
+    }
+    else
+#endif
+#if CONFIG_11K
+        if (strstr(buf, RRM_EVENT_NEIGHBOR_REP_RXED))
+    {
+        wlcm_d("11K RRM event neighbor response received");
+        wlan_parse_neighbor_report_response(buf, &wlan.nbr_rpt);
+    }
+    else if (strstr(buf, RRM_EVENT_NEIGHBOR_REP_COMPLETED))
+    {
+        if (wlan.nbr_rpt.neighbor_cnt != 0U)
+        {
+            memset(&wlan.nbr_rpt, 0x00, sizeof(wlan_rrm_neighbor_report_t));
+            (void)wifi_event_completion(WIFI_EVENT_NLIST_REPORT, WIFI_EVENT_REASON_SUCCESS, NULL);
+        }
+    }
+    else if (strstr(buf, RRM_EVENT_NEIGHBOR_REP_FAILED))
+    {
+        wlcm_d("11K RRM event neighbor report request failed");
+    }
+    else
+#endif
+#if CONFIG_WPA_SUPP_DPP
+        if (strstr(buf, DPP_EVENT_CONF_RECEIVED))
+    {
+        if (!is_uap_started())
+        {
+            wlcm_d("DPP starts to new a network profile");
+            (void)wlcm_process_add_unspecified_network("dpp_network");
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_CONFOBJ_AKM))
+    {
+        unsigned int network_idx = -1;
+
+        if (is_uap_started())
+        {
+            network_idx = wlan.cur_uap_network_idx;
+        }
+        else
+        {
+            network_idx = wlan.cur_network_idx;
+        }
+        /* Only for STA associate */
+        mlan_adap->priv[0]->is_dpp_connect = MTRUE;
+        if (network_idx < WLAN_MAX_KNOWN_NETWORKS)
+        {
+            struct wlan_network_security *security = &(wlan.networks[network_idx].security);
+            const char *pos = buf + sizeof(DPP_EVENT_CONFOBJ_AKM) - 1;
+            security->pmk_valid = false;
+            security->type = WLAN_SECURITY_NONE;
+            if (memcmp("psk", pos, strlen("psk")) == 0)
+            {
+                security->type     = WLAN_SECURITY_WPA2;
+                security->key_mgmt = WLAN_KEY_MGMT_PSK;
+            }
+            else if (memcmp("sae", pos, strlen("sae")) == 0)
+            {
+                security->type     = WLAN_SECURITY_WPA3_SAE;
+                security->key_mgmt = WLAN_KEY_MGMT_SAE;
+            }
+            else if ((memcmp("psk-sae", pos, strlen("psk-sae")) == 0) ||
+                     (memcmp("psk+sae", pos, strlen("psk+sae")) == 0))
+            {
+                security->type = WLAN_SECURITY_WPA2_WPA3_SAE_MIXED;
+                security->key_mgmt = WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_SAE;
+            }
+            else if ((memcmp("sae-dpp", pos, strlen("sae-dpp")) == 0) ||
+                     (memcmp("dpp+sae", pos, strlen("dpp+sae")) == 0))
+            {
+                security->type        = WLAN_SECURITY_WPA3_SAE;
+                security->key_mgmt = WLAN_KEY_MGMT_DPP | WLAN_KEY_MGMT_SAE;
+            }
+            else if ((memcmp("psk-sae-dpp", pos, strlen("psk-sae-dpp")) == 0) ||
+                     (memcmp("dpp+psk+sae", pos, strlen("dpp+psk+sae")) == 0))
+            {
+                security->type = WLAN_SECURITY_WPA2_WPA3_SAE_MIXED;
+                security->key_mgmt = WLAN_KEY_MGMT_DPP | WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_SAE;
+            }
+            else if (memcmp("dpp", pos, strlen("dpp")) == 0)
+            {
+                security->type = WLAN_SECURITY_DPP;
+                security->key_mgmt = WLAN_KEY_MGMT_DPP;
+            }
+            else if (memcmp("dot1x", pos, strlen("dot1x")) == 0)
+            {
+#if CONFIG_EAP_TLS
+                security->type = WLAN_SECURITY_EAP_TLS_SHA256;
+#endif
+                security->key_mgmt = WLAN_KEY_MGMT_IEEE8021X;
+            }
+            else
+            {
+                wlcm_e("DPP AKM type(%s) unknown!", pos);
+                return ;
+            }
+            security->pairwise_cipher = 0x10; /* CCMP */
+            security->mfpc = 1;
+            security->mfpr = 1;
+            wlan_set_pmfcfg(security->mfpc, security->mfpr);
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_CONFOBJ_SSID))
+    {
+        unsigned int network_idx = -1;
+
+        if (is_uap_started())
+        {
+            network_idx = wlan.cur_uap_network_idx;
+        }
+        else
+        {
+            network_idx = wlan.cur_network_idx;
+        }
+        if (network_idx < WLAN_MAX_KNOWN_NETWORKS)
+        {
+            const char *pos = buf + sizeof(DPP_EVENT_CONFOBJ_SSID) - 1;
+            if (strlen(pos) < IEEEtypes_SSID_SIZE)
+            {
+                (void)memcpy(wlan.networks[network_idx].ssid, pos, strlen(pos));
+            }
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_CONFOBJ_PASS))
+    {
+        unsigned int network_idx = -1;
+
+        if (is_uap_started())
+        {
+            network_idx = wlan.cur_uap_network_idx;
+        }
+        else
+        {
+            network_idx = wlan.cur_network_idx;
+        }
+        if (network_idx < WLAN_MAX_KNOWN_NETWORKS)
+        {
+            char psk[WLAN_PSK_MAX_LENGTH];
+            unsigned int hex_len = 0;
+            struct wlan_network_security *security = &(wlan.networks[network_idx].security);
+            const char *pos = buf + sizeof(DPP_EVENT_CONFOBJ_PASS) - 1;
+
+            hex_len = strlen(pos);
+            if (hex_len <= (WLAN_PSK_MAX_LENGTH * 2))
+            {
+                memset(psk, 0, sizeof(psk));
+                hexstr2bin(pos, (unsigned char *)psk, hex_len/2);
+                security->psk_len = strlen(psk);
+                (void)strcpy(security->psk, psk);
+                security->password_len = strlen(psk);
+                (void)strcpy(security->password, psk);
+            }
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_CONFOBJ_PSK))
+    {
+        unsigned int network_idx = -1;
+
+        if (is_uap_started())
+        {
+            network_idx = wlan.cur_uap_network_idx;
+        }
+        else
+        {
+            network_idx = wlan.cur_network_idx;
+        }
+        if (network_idx < WLAN_MAX_KNOWN_NETWORKS)
+        {
+            char pmk[WLAN_PMK_LENGTH];
+            unsigned int hex_len = 0;
+            struct wlan_network_security *security = &(wlan.networks[network_idx].security);
+            const char *pos = buf + sizeof(DPP_EVENT_CONFOBJ_PSK) - 1;
+
+            hex_len = strlen(pos);
+            if (hex_len <= (WLAN_PMK_LENGTH * 2))
+            {
+                memset(pmk, 0, sizeof(pmk));
+                hexstr2bin(pos, (unsigned char *)pmk, hex_len/2);
+                security->pmk_valid = true;
+                (void)memcpy(security->pmk, pmk, WLAN_PMK_LENGTH);
+            }
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_CONNECTOR))
+    {
+        unsigned int network_idx = -1;
+
+        if (is_uap_started())
+        {
+            network_idx = wlan.cur_uap_network_idx;
+        }
+        else
+        {
+            network_idx = wlan.cur_network_idx;
+        }
+        if (network_idx < WLAN_MAX_KNOWN_NETWORKS)
+        {
+            struct wlan_network_security *security = &(wlan.networks[network_idx].security);
+            const char *pos = buf + sizeof(DPP_EVENT_CONNECTOR) - 1;
+
+            if (security->dpp_connector)
+            {
+                OSA_MemoryFree(security->dpp_connector);
+            }
+            security->dpp_connector = OSA_MemoryAllocate(strlen(pos) + 1);
+            if (security->dpp_connector == NULL)
+            {
+                wlcm_e("Allocate %s memory failed!", DPP_EVENT_CONNECTOR);
+                return ;
+            }
+            (void)memcpy(security->dpp_connector, pos, strlen(pos));
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_C_SIGN_KEY))
+    {
+        unsigned int network_idx = -1;
+
+        if (is_uap_started())
+        {
+            network_idx = wlan.cur_uap_network_idx;
+        }
+        else
+        {
+            network_idx = wlan.cur_network_idx;
+        }
+        if (network_idx < WLAN_MAX_KNOWN_NETWORKS)
+        {
+            struct wlan_network_security *security = &(wlan.networks[network_idx].security);
+            const char *pos = buf + sizeof(DPP_EVENT_C_SIGN_KEY) - 1;
+
+            if (security->dpp_c_sign_key)
+            {
+                OSA_MemoryFree(security->dpp_c_sign_key);
+            }
+            security->dpp_c_sign_key = OSA_MemoryAllocate(strlen(pos) + 1);
+            if (security->dpp_c_sign_key == NULL)
+            {
+                wlcm_e("Allocate %s memory failed!", DPP_EVENT_C_SIGN_KEY);
+                return ;
+            }
+            (void)memcpy(security->dpp_c_sign_key, pos, strlen(pos));
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_NET_ACCESS_KEY))
+    {
+        unsigned int network_idx = -1;
+
+        if (is_uap_started())
+        {
+            network_idx = wlan.cur_uap_network_idx;
+        }
+        else
+        {
+            network_idx = wlan.cur_network_idx;
+        }
+        if (network_idx < WLAN_MAX_KNOWN_NETWORKS)
+        {
+            struct wlan_network_security *security = &(wlan.networks[network_idx].security);
+            const char *pos = buf + sizeof(DPP_EVENT_NET_ACCESS_KEY) - 1;
+
+            if (security->dpp_net_access_key)
+            {
+                OSA_MemoryFree(security->dpp_net_access_key);
+            }
+            security->dpp_net_access_key = OSA_MemoryAllocate(strlen(pos) + 1);
+            if (security->dpp_net_access_key == NULL)
+            {
+                wlcm_e("Allocate %s memory failed!", DPP_EVENT_NET_ACCESS_KEY);
+                return ;
+            }
+            (void)memcpy(security->dpp_net_access_key, pos, strlen(pos));
+            if (is_uap_started())
+            {
+                wlcm_d("DPP reload uap");
+                wlan_enable_uap_11d(MTRUE);
+                wpa_supp_start_ap(netif, &wlan.networks[network_idx], 1);
+            }
+        }
+    }
+    else if (strstr(buf, DPP_EVENT_INTRO))
+    {
+        wlan_deepsleepps_on();
+        wlan_ieeeps_on(wlan.wakeup_conditions);
+    }
+    else
+#endif
+    {
+    }
+}
+#endif
+
+#define MAX_RETRY_TICKS 50
+
+static void wlcm_process_init_params()
+{
+    wlan.cm_ieeeps_configured = false;
+
+    wlan.cm_deepsleepps_configured = false;
+
+#if (CONFIG_WNM_PS)
+    wlan.cm_wnmps_configured = false;
+    wlan.wnm_sleep_time      = 0;
+#endif
+#if (CONFIG_11K) || (CONFIG_11V)
+    memset(&wlan.nlist_rep_param, 0x00, sizeof(wlan_nlist_report_param));
+#endif
+
+    wlan.bgscan_attempt = 0;
+
+    wlan.cur_network_idx     = -1;
+    wlan.cur_uap_network_idx = -1;
+}
+
+static void wlcm_process_init(enum cm_sta_state *next)
+{
+    int ret;
+    (void)ret;
+
+    wlan.sta_state = CM_STA_IDLE;
+    *next          = CM_STA_IDLE;
+
+    wlcm_process_init_params();
+
+
+#if OTP_CHANINFO
+    (void)wifi_get_fw_region_and_cfp_tables();
+#endif
+
+    (void)wifi_get_uap_max_clients(&wlan.uap_supported_max_sta_num);
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+    struct netif *uap_netif = net_get_uap_interface();
+
+    wpa_supp_set_ap_max_num_sta(uap_netif, wlan.uap_supported_max_sta_num);
+#endif
+#endif
+
+    (void)wrapper_wlan_cmd_get_hw_spec();
+
+#ifndef RW610
+#ifndef __ZEPHYR__
+    wlan_ed_mac_ctrl_t wlan_ed_mac_ctrl = WLAN_ED_MAC_CTRL;
+#else
+    wlan_ed_mac_ctrl_t wlan_ed_mac_ctrl = {
+        0x01,
+        CONFIG_NXP_WIFI_ED_OFFSET_2G
+#if CONFIG_5GHz_SUPPORT
+        ,
+        0x01,
+        CONFIG_NXP_WIFI_ED_OFFSET_5G
+#endif
+    };
+#endif
+    (void)wlan_set_ed_mac_mode(wlan_ed_mac_ctrl);
+    (void)wlan_set_uap_ed_mac_mode(wlan_ed_mac_ctrl);
+#endif
+
+    (void)wifi_enable_ecsa_support();
+
+    //		uint16_t ant = 1; //board_antenna_select();
+    //                if (board_antenna_switch_ctrl())
+    //			rfctrl_set_config(ant);
+
+#if defined(SD8801) || defined(SD8978) || defined(SD8987)
+    uint32_t ant           = 1;
+    uint16_t evaluate_time = 0x1770;
+
+    ret = wifi_set_antenna(ant, evaluate_time);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_d("Failed to set antenna configuration");
+    }
+    else
+    {
+        wlcm_d("Antenna selected: %d", ant);
+    }
+#endif /* defined(SD8801, 8978, 8987) */
+
+    wifi_set_packet_retry_count(MAX_RETRY_TICKS);
+
+#if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177)
+
+    wifi_set_txbfcap(0x19e74608);
+
+    /*Enabling 20/40MHz enable(bit 1)
+     * enabling Short GI in 40 Mhz(bit 6)
+     * and 20MHz(bit 5),
+     * Reserved bits to be set to 1 (Bits 2,3)*/
+    uint16_t httxcfg = 0x6E; // TODO need to add defines for this setting
+
+    ret = wlan_set_httxcfg(httxcfg);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Failed to set HT TX configuration");
+        return;
+    }
+
+    wlan_uap_set_httxcfg(httxcfg);
+#endif
+
+#if CONFIG_11K
+    (void)wifi_host_11k_cfg(1);
+#endif
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_1AS)
+#if !CONFIG_WPA_SUPP
+    (void)wlan_rx_mgmt_indication(WLAN_BSS_TYPE_STA, WLAN_MGMT_ACTION, NULL);
+#endif
+#endif
+
+#if !CONFIG_WPA_SUPP
+#if CONFIG_DRIVER_MBO
+    wifi_host_mbo_cfg(1);
+#endif
+#endif
+
+#if CONFIG_WIFI_AUTO_POWER_SAVE
+    wlan_deepsleepps_on();
+    wifi_set_power_save_mode();
+    wlan_ieeeps_on(wlan.wakeup_conditions);
+#endif
+
+    wlan_set_11d_state(WLAN_BSS_TYPE_UAP, 1);
+    wlan_set_11d_state(WLAN_BSS_TYPE_STA, 1);
+
+}
+
+static void wlcm_process_net_if_config_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+    int ret;
+#endif
+
+    if (wlan.sta_state != CM_STA_INITIALIZING)
+    {
+        wlcm_d("ignoring TCP configure response");
+        return;
+    }
+
+    if (msg->reason != WIFI_EVENT_REASON_SUCCESS)
+    {
+        wlcm_e("Interfaces init failed");
+        CONNECTION_EVENT(WLAN_REASON_INITIALIZATION_FAILED, NULL);
+        /* stay here until user re-inits */
+        *next = CM_STA_INITIALIZING;
+        return;
+    }
+#if CONFIG_WPA_SUPP
+    ret = wpa_supp_init(wpa_supplicant_msg_cb);
+    if (ret != 0)
+    {
+        wlcm_e("wpa_supp_init failed. status code %d", ret);
+        return;
+    }
+
+    ret = wifi_supp_init();
+    if (ret != 0)
+    {
+        wlcm_e("wifi_supp_init failed. status code %d", ret);
+        return;
+    }
+
+    ret = wpa_supp_status(netif);
+    if (ret != 0)
+    {
+        wlcm_e("wpa_supp_status failed. status code %d", ret);
+        return;
+    }
+
+    /* ret = monitor_start();
+    if (ret != 0)
+    {
+        wlcm_e("monitor_start failed. status code %d", ret);
+        return;
+    } */
+
+#endif
+
+    wlcm_process_init(next);
+}
+
+static void wlcm_request_disconnect(enum cm_sta_state *next, struct wlan_network *curr_nw);
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+static void wlcm_process_fw_hang_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+    (void)msg;
+
+    CONNECTION_EVENT(WLAN_REASON_FW_HANG, NULL);
+
+    if (wlan.sta_state > CM_STA_IDLE)
+    {
+#if CONFIG_WPA_SUPP
+        wpa_supp_disconnect(netif);
+#endif
+        wlcm_request_disconnect(next, &wlan.networks[wlan.cur_network_idx]);
+        wlan_dhcp_cleanup();
+    }
+
+    if (wlan.uap_state > CM_UAP_INITIALIZING)
+    {
+        (void)do_stop(&wlan.networks[wlan.cur_uap_network_idx]);
+    }
+}
+
+static void wlcm_process_fw_reset_event(struct wifi_message *msg, enum cm_sta_state *next)
+{
+    (void)msg;
+    (void)next;
+
+    wlan.ind_reset = 1;
+
+    wlcm_process_init(next);
+
+    CONNECTION_EVENT(WLAN_REASON_FW_RESET, NULL);
+}
+#endif
+
+static enum cm_uap_state uap_state_machine(struct wifi_message *msg)
+{
+    struct wlan_network *network = NULL;
+    enum cm_uap_state next       = wlan.uap_state;
+    int ret                      = 0;
+    void *if_handle              = NULL;
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_uap_interface();
+#endif
+
+    network = &wlan.networks[wlan.cur_uap_network_idx];
+
+    switch (msg->event)
+    {
+        case CM_UAP_USER_REQUEST_START:
+            wlan.cur_uap_network_idx = (int)msg->data;
+            wlan.scan_count          = 0;
+
+            (void)do_start(&wlan.networks[wlan.cur_uap_network_idx]);
+            next = wlan.uap_state;
+            break;
+        case CM_UAP_USER_REQUEST_STOP:
+            if (wlan.uap_state < CM_UAP_CONFIGURED)
+            {
+                break;
+            }
+            (void)do_stop(&wlan.networks[wlan.cur_uap_network_idx]);
+            next = wlan.uap_state;
+#if CONFIG_WPA_SUPP
+            if (wlan.status_timeout)
+            {
+                OSA_TimerDeactivate((osa_timer_handle_t)wlan.supp_status_timer);
+                wlan.status_timeout = 0;
+                CONNECTION_EVENT(WLAN_REASON_UAP_START_FAILED, NULL);
+            }
+#endif
+            break;
+        case WIFI_EVENT_UAP_STARTED:
+            if (!is_uap_state(CM_UAP_CONFIGURED))
+            {
+                wlcm_w(
+                    "Ignoring address config event as uap not "
+                    "in configured state");
+                break;
+            }
+
+            if (msg->reason == WIFI_EVENT_REASON_SUCCESS)
+            {
+                if (network->type == WLAN_BSS_TYPE_UAP)
+                {
+                    (void)memcpy((void *)&network->bssid[0], (const void *)&wlan.uap_mac[0], 6);
+                    if_handle = net_get_uap_handle();
+                }
+#if CONFIG_WPA_SUPP
+                OSA_TimerDeactivate((osa_timer_handle_t)wlan.supp_status_timer);
+                wlan.status_timeout = 0;
+
+                wpa_supp_network_status(netif, network);
+#endif
+
+#ifdef __ZEPHYR__
+                net_interface_up(if_handle);
+#endif
+
+                ret = net_configure_address((struct net_ip_config *)&network->ip, if_handle);
+                if (ret != 0)
+                {
+                    wlcm_e("TCP/IP stack setup failed");
+                    CONNECTION_EVENT(WLAN_REASON_ADDRESS_FAILED, NULL);
+                }
+                else
+                {
+                    next = CM_UAP_STARTED;
+                }
+            }
+            else
+            {
+                CONNECTION_EVENT(WLAN_REASON_UAP_START_FAILED, NULL);
+            }
+            break;
+        case WIFI_EVENT_UAP_CLIENT_ASSOC:
+#if CONFIG_WIFI_UAP_WORKAROUND_STICKY_TIM
+            if (network->type == WLAN_BSS_TYPE_UAP)
+            {
+                wifi_uap_enable_sticky_bit(msg->data);
+            }
+#endif /* CONFIG_WIFI_UAP_WORKAROUND_STICKY_TIM */
+            CONNECTION_EVENT(WLAN_REASON_UAP_CLIENT_ASSOC, msg->data);
+            /* This was allocated by the sender */
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+            break;
+        case WIFI_EVENT_UAP_CLIENT_CONN:
+            CONNECTION_EVENT(WLAN_REASON_UAP_CLIENT_CONN, msg->data);
+            /* This was allocated by the sender */
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+            break;
+        case WIFI_EVENT_UAP_CLIENT_DEAUTH:
+#ifdef CONFIG_WPA_SUPP_AP
+            {
+                wlan_uap_client_disassoc_t *disassoc_resp = msg->data;
+                /* BIT 14 indicate deauth is initiated by FW */
+                if(!(disassoc_resp->reason_code & MBIT(14)))
+                {
+                    wifi_nxp_sta_remove(disassoc_resp->sta_addr);
+                }
+            }
+#else
+            CONNECTION_EVENT(WLAN_REASON_UAP_CLIENT_DISSOC, msg->data);
+#endif
+            /* This was allocated by the sender */
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+            break;
+        case WIFI_EVENT_UAP_STOPPED:
+            CONNECTION_EVENT(WLAN_REASON_UAP_STOPPED, NULL);
+            break;
+        case WIFI_EVENT_UAP_NET_ADDR_CONFIG:
+            if (!is_uap_state(CM_UAP_STARTED))
+            {
+                wlcm_w(
+                    "Ignoring address config event as uap not "
+                    "in started state");
+                break;
+            }
+
+            if (msg->reason == WIFI_EVENT_REASON_SUCCESS && network->ip.ipv4.addr_type == ADDR_TYPE_STATIC)
+            {
+                if (network->type == WLAN_BSS_TYPE_UAP)
+                {
+                    if_handle = net_get_uap_handle();
+                }
+
+                (void)net_get_if_addr((struct net_ip_config *)&network->ip, if_handle);
+                /* UAP case set dns same as gateway */
+                network->ip.ipv4.dns1 = network->ip.ipv4.gw;
+                network->ip.ipv4.dns2 = 0;
+#if CONFIG_IPV6
+                (void)net_get_if_ipv6_addr((struct net_ip_config *)&network->ip, if_handle);
+#endif
+                next = CM_UAP_IP_UP;
+                CONNECTION_EVENT(WLAN_REASON_UAP_SUCCESS, NULL);
+            }
+            else
+            {
+                CONNECTION_EVENT(WLAN_REASON_ADDRESS_FAILED, NULL);
+                next = CM_UAP_INITIALIZING;
+            }
+            break;
+        default:
+            wlcm_w("got unknown message  UAP  : %d", msg->event);
+            break;
+    }
+    return next;
+}
+
+static void wlcm_request_scan(struct wifi_message *msg, enum cm_sta_state *next)
+{
+    char ssid[(MLAN_MAX_SSID_LENGTH + 1) * MRVDRV_MAX_SSID_LIST_LENGTH]  = {0};
+    uint8_t ssid_num = 0, ssid_off = 0;
+    if (msg->data == NULL)
+    {
+        wlcm_w("ignoring scan request with NULL scan params");
+        wlcm_d("releasing scan lock");
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+        wlan.is_scan_lock = 0;
+        return;
+    }
+
+    wlan_scan_params_v2_t *wlan_scan_param = (wlan_scan_params_v2_t *)msg->data;
+
+    if ((!is_scanning_allowed())
+#if CONFIG_WPS2
+        || (wlan_get_prov_session() != PROV_NON_SESSION_ATTEMPT)
+#endif
+    )
+    {
+        wlcm_w("ignoring scan result in invalid state");
+        wlcm_d("releasing scan lock");
+        /* Free allocated wifi scan parameters */
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(wlan_scan_param);
+#else
+        OSA_MemoryPoolFree(buf_512_MemoryPool, wlan_scan_param);
+#endif
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+        wlan.is_scan_lock = 0;
+        return;
+    }
+
+#if CONFIG_COMBO_SCAN
+    memcpy(ssid+ssid_off, wlan_scan_param->ssid[0], strlen(wlan_scan_param->ssid[0]));
+    ssid_off += strlen(wlan_scan_param->ssid[0]);
+    ssid[ssid_off] = '\0';
+    ssid_off++;
+    ssid_num++;
+
+    if (strlen(wlan_scan_param->ssid[1]))
+    {
+        memcpy(ssid+ssid_off, wlan_scan_param->ssid[1], strlen(wlan_scan_param->ssid[1]));
+        ssid_off += strlen(wlan_scan_param->ssid[1]);
+        ssid[ssid_off] = '\0';
+        ssid_num++;
+    }
+#else
+    memcpy(ssid + ssid_off, wlan_scan_param->ssid, strlen(wlan_scan_param->ssid));
+    ssid_off += strlen(wlan_scan_param->ssid);
+    ssid[ssid_off] = '\0';
+    ssid_off++;
+    ssid_num++;
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+    if (is_uap_started() || is_sta_connected())
+        wlan_scan_param->scan_chan_gap = scan_channel_gap;
+    else
+        wlan_scan_param->scan_chan_gap = 0;
+#endif
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_11K
+    if (wlan.enable_11k == 1U)
+    {
+        wm_wifi.wpa_supp_scan = true;
+        wm_wifi.external_scan = true;
+    }
+#endif
+#endif
+
+    wlcm_d("initiating wlan-scan (return to %s)", dbg_sta_state_name(wlan.sta_state));
+
+
+    int ret = wifi_send_scan_cmd((t_u8)g_wifi_scan_params.bss_type, wlan_scan_param->bssid,
+                                 ssid, ssid_num,
+                                 wlan_scan_param->num_channels, wlan_scan_param->chan_list, wlan_scan_param->num_probes,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                                 wlan_scan_param->rssi_threshold,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                                 wlan_scan_param->scan_chan_gap,
+#endif
+                                 false, false);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("wifi send scan cmd failed");
+        *next = wlan.sta_state;
+#if CONFIG_WPA_SUPP
+        wm_wifi.wpa_supp_scan = false;
+        wm_wifi.external_scan = false;
+#endif
+        wlcm_d("releasing scan lock");
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+        wlan.is_scan_lock = 0;
+#if CONFIG_NCP
+        if(wlan_scan_param->cb != NULL)
+        {
+            app_notify_event(APP_EVT_SCAN_RESULT, ret, NULL, 0);
+        }
+#endif
+    }
+    else
+    {
+        wlan.scan_cb       = (int (*)(unsigned int count))(wlan_scan_param->cb);
+        wlan.sta_return_to = wlan.sta_state;
+        *next              = CM_STA_SCANNING_USER;
+    }
+    /* Free allocated wifi scan parameters */
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(wlan_scan_param);
+#else
+    OSA_MemoryPoolFree(buf_512_MemoryPool, wlan_scan_param);
+#endif
+}
+
+static void wlcm_deinit(int action)
+{
+    if ((wlan.status != WLCMGR_ACTIVATED) && (wlan.status != WLCMGR_INIT_DONE))
+    {
+        wlcm_e("cannot deinit wlcmgr. unexpected status: %d\n\r", wlan.status);
+        return;
+    }
+
+    wifi_scan_stop();
+    wifi_deinit();
+
+    wlan.status = WLCMGR_INACTIVE;
+}
+
+static void wlcm_request_disconnect(enum cm_sta_state *next, struct wlan_network *curr_nw)
+{
+    void *if_handle = NULL;
+    /* On disconnect request, we need to take down the interface.
+       This is required to fix bug # 52964 */
+    if (curr_nw->type == WLAN_BSS_TYPE_STA)
+    {
+        if_handle = net_get_mlan_handle();
+    }
+    if (if_handle == NULL)
+    {
+#if CONFIG_NCP
+        CONNECTION_EVENT(WLAN_REASON_USER_DISCONNECT, (void *)(-WM_FAIL));
+#endif
+#if CONFIG_HOST_SLEEP
+        wakelock_put();
+#endif
+        wlcm_w("No interface is up\r\n");
+        return;
+    }
+    net_stop_dhcp_timer();
+    /* Forcefully stop dhcp on given interface.
+     * net_interface_dhcp_stop internally does nothing
+     * if dhcp client is not started.
+     */
+    net_interface_dhcp_stop(if_handle);
+    net_interface_down(if_handle);
+
+    if (
+#if CONFIG_WPS2
+        (wlan_get_prov_session() == PROV_NON_SESSION_ATTEMPT) &&
+#endif
+        (wlan.sta_state < CM_STA_IDLE || is_state(CM_STA_IDLE)))
+    {
+
+#if CONFIG_WPA_SUPP
+        if (wlan.status_timeout)
+        {
+            OSA_TimerDeactivate((osa_timer_handle_t)wlan.supp_status_timer);
+            wlan.status_timeout = 0;
+            CONNECTION_EVENT(WLAN_REASON_USER_DISCONNECT, NULL);
+        }
+        else
+#endif
+        {
+#if CONFIG_NCP
+            CONNECTION_EVENT(WLAN_REASON_USER_DISCONNECT, (void *)(-WM_FAIL));
+#endif
+        }
+        if (wlan.connect_wakelock_taken)
+        {
+            wlan.connect_wakelock_taken = false;
+        }
+
+#if CONFIG_HOST_SLEEP
+        wakelock_put();
+#endif
+        wlan.cur_network_idx = -1;
+        return;
+    }
+
+    if (is_user_scanning() && wlan.sta_return_to != CM_STA_IDLE)
+    {
+        /* we're in a user scan: we'll need to disconnect and
+         * return to the idle state once this scan completes */
+        if (wlan.sta_return_to >= CM_STA_ASSOCIATING)
+        {
+#if !CONFIG_WPA_SUPP
+            (void)wifi_deauthenticate((uint8_t *)curr_nw->bssid);
+#endif
+            wlan.sta_return_to  = CM_STA_IDLE;
+            *next               = CM_STA_IDLE;
+            wlan.sta_ipv4_state = CM_STA_IDLE;
+#if CONFIG_IPV6
+            wlan.sta_ipv6_state = CM_STA_IDLE;
+#endif
+        }
+    }
+    else if (wlan.sta_state >= CM_STA_ASSOCIATING)
+    {
+        /* if we aren't idle or user scanning,
+         * we'll need to actually
+         * disconnect */
+#if !CONFIG_WPA_SUPP
+        (void)wifi_deauthenticate((uint8_t *)curr_nw->bssid);
+#endif
+        if (wlan.is_scan_lock)
+        {
+            wlcm_d("releasing scan lock");
+            (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+            wlan.is_scan_lock = 0;
+        }
+        wlan.sta_return_to  = CM_STA_IDLE;
+        wlan.sta_state      = CM_STA_IDLE;
+        *next               = CM_STA_IDLE;
+        wlan.sta_ipv4_state = CM_STA_IDLE;
+#if CONFIG_IPV6
+        wlan.sta_ipv6_state = CM_STA_IDLE;
+#endif
+    }
+    else if (wlan.sta_state == CM_STA_SCANNING)
+    {
+        wlan.sta_state      = CM_STA_IDLE;
+        *next               = CM_STA_IDLE;
+        wlan.sta_ipv4_state = CM_STA_IDLE;
+#if CONFIG_IPV6
+        wlan.sta_ipv6_state = CM_STA_IDLE;
+#endif
+    }
+    else
+    { /* Do Nothing */
+    }
+    wlan.cur_network_idx =-1;
+
+#if CONFIG_WPS2
+    if (wlan_get_prov_session() == PROV_WPS_SESSION_ATTEMPT)
+    {
+        CONNECTION_EVENT(WLAN_REASON_WPS_DISCONNECT, NULL);
+        wlan_set_prov_session(PROV_NON_SESSION_ATTEMPT);
+    }
+    else
+#endif
+#if CONFIG_WPA_SUPP
+        if (wlan.status_timeout)
+    {
+#if CONFIG_WPA_SUPP_WPS
+        wlan.wps_session_attempt = 0;
+#endif
+        OSA_TimerDeactivate((osa_timer_handle_t)wlan.supp_status_timer);
+        wlan.status_timeout = 0;
+    }
+#endif
+    CONNECTION_EVENT(WLAN_REASON_USER_DISCONNECT, NULL);
+
+    if (wlan.reassoc_control && wlan.reassoc_request)
+    {
+        wlan.scan_count      = WLAN_RESCAN_LIMIT;
+        wlan.reassoc_count   = WLAN_RECONNECT_LIMIT;
+        wlan.reassoc_request = false;
+    }
+
+    if (wlan.connect_wakelock_taken)
+    {
+#if CONFIG_HOST_SLEEP
+        wakelock_put();
+#endif
+        wlan.connect_wakelock_taken = false;
+    }
+#if CONFIG_HOST_SLEEP
+     /* The wakelock will be taken when user issue disconnect command and this time flag wlan.connect_wakelock_taken is false.
+      * Release wakelock when disconnect process is done without check.
+      */
+    wakelock_put();
+#endif
+}
+
+static void wlcm_request_connect(struct wifi_message *msg, enum cm_sta_state *next, struct wlan_network *network)
+{
+    int ret;
+    struct wlan_network *new_network = &wlan.networks[(unsigned int)msg->data];
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+#if CONFIG_HOST_SLEEP
+    if (!wlan.connect_wakelock_taken)
+    {
+        wakelock_get();
+        wlan.connect_wakelock_taken = true;
+    }
+#endif
+
+    (void)wlan_set_pmfcfg((t_u8)new_network->security.mfpc, (t_u8)new_network->security.mfpr);
+
+    if ((wlan.roam_reassoc == false) && (wlan.sta_state >= CM_STA_ASSOCIATING))
+    {
+        if (new_network->role == WLAN_BSS_ROLE_STA)
+        {
+            wlcm_d(
+                "deauthenticating before"
+                " attempting new connection");
+            (void)wifi_deauthenticate((uint8_t *)network->bssid);
+        }
+    }
+
+    wlcm_d("starting %s to network: %d", wlan.roam_reassoc == false ? "connection" : "reassociation", (int)msg->data);
+
+#if !CONFIG_WPA_SUPP
+    ret = do_connect((int)msg->data);
+#else
+    wlan.scan_count      = 0;
+    wlan.cur_network_idx = (int)msg->data;
+    if (wlan.roam_reassoc == true)
+    {
+        ret                  = wpa_supp_reassociate(netif);
+    }
+    else
+    {
+        ret                  = wpa_supp_connect(netif, new_network);
+    }
+#endif
+
+    /* Release the connect scan lock if do_connect fails,
+     * in successful case it gets freed in scan result event.
+     */
+    if (ret != WM_SUCCESS)
+    {
+        if (wlan.is_scan_lock)
+        {
+            wlcm_d("releasing scan lock (connect scan)");
+            (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+            wlan.is_scan_lock = 0;
+        }
+        wlan.cur_network_idx = -1;
+        CONNECTION_EVENT(WLAN_REASON_CONNECT_FAILED, NULL);
+    }
+
+#if CONFIG_WPA_SUPP
+    if (ret == WM_SUCCESS)
+    {
+        wlan.sta_state      = CM_STA_ASSOCIATING;
+        wlan.connect        = true;
+        wlan.status_timeout = 0;
+        (void)OSA_TimerActivate((osa_timer_handle_t)wlan.supp_status_timer);
+    }
+#endif
+
+    *next = wlan.sta_state;
+}
+
+static void wlcm_request_reconnect(enum cm_sta_state *next, struct wlan_network *network)
+{
+    struct wifi_message msg;
+    msg.event  = 0;
+    msg.reason = WIFI_EVENT_REASON_SUCCESS;
+    msg.data   = (void *)(wlan.cur_network_idx);
+
+    wlcm_d("Reconnect in progress ...");
+
+    wlan.reassoc_request = true;
+
+    if (wlan.reassoc_count < WLAN_RECONNECT_LIMIT)
+    {
+        wlcm_d("Reconnect attempt # %d", wlan.reassoc_count + 1);
+        wlan.reassoc_count++;
+        wlcm_request_connect(&msg, next, network);
+    }
+    else
+    {
+        wlcm_d("Reconnection failed. Giving up.");
+        wlan.reassoc_request = false;
+        wlan.reassoc_count   = 0;
+
+        wlan.cur_network_idx = -1;
+        CONNECTION_EVENT(WLAN_REASON_CONNECT_FAILED, NULL);
+
+        wlcm_d("Disconnecting ... ");
+        (void)wlan_disconnect();
+    }
+}
+
+static void wifi_process_bg_scan_stopped(struct wifi_message *msg)
+{
+    (void)msg;
+
+    if (wlan.roam_reassoc && wlan.bgscan_attempt < BG_SCAN_LIMIT)
+    {
+        wlan.bgscan_attempt++;
+        wlan.roam_reassoc = false;
+        (void)wifi_event_completion(WIFI_EVENT_RSSI_LOW, WIFI_EVENT_REASON_SUCCESS, NULL);
+    }
+    else
+    {
+        wlan.bgscan_attempt = 0;
+        wlan.roam_reassoc = false;
+        PRINTF("Soft Roam: AP with better RSSI not found");
+        CONNECTION_EVENT(WLAN_REASON_BGSCAN_NETWORK_NOT_FOUND, NULL);
+    }
+}
+
+static void wlcm_process_bg_scan_report(void)
+{
+    wifi_send_scan_query();
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_ROAMING)
+    /* Set rssi low threshold and subscribe rssi low event again */
+    (void)wifi_set_rssi_low_threshold(&wlan.rssi_low_threshold);
+#endif
+}
+
+static void wlcm_process_get_hw_spec_event(void)
+{
+#if CONFIG_WMM
+    (void)wifi_wmm_init();
+#endif
+
+#if CONFIG_WIFI_SMOKE_TESTS
+    extern int initNetwork(void);
+    /* network enet init */
+    int ret = initNetwork();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("FAILED to init network (ret=%d). Reboot the board and try again.\r\n", ret);
+    }
+#endif
+
+#if CONFIG_SIGMA_AGENT
+    extern int sigma_agent_init(void);
+
+    (void)sigma_agent_init();
+#endif
+
+    /* Set Tx Power Limits in Wi-Fi firmware */
+    (void)wlan_set_wwsm_txpwrlimit();
+
+    if (wlan.ind_reset == 0)
+    {
+        CONNECTION_EVENT(WLAN_REASON_INITIALIZED, NULL);
+    }
+#if CONFIG_WIFI_IND_RESET
+    wlan.ind_reset = 0;
+#endif
+}
+
+#if defined(SDK_OS_FREE_RTOS)
+
+static void wlcm_process_mgmt_frame(void *data)
+{
+    RxPD *rxpd                   = (RxPD *)(net_stack_buffer_get_payload(data));
+    wlan_mgmt_pkt *pmgmt_pkt_hdr = NULL;
+
+    pmgmt_pkt_hdr          = (wlan_mgmt_pkt *)(void *)((uint8_t *)rxpd + rxpd->rx_pkt_offset);
+    pmgmt_pkt_hdr->frm_len = wlan_le16_to_cpu(pmgmt_pkt_hdr->frm_len);
+    if ((pmgmt_pkt_hdr->wlan_header.frm_ctl & (t_u16)IEEE80211_FC_MGMT_FRAME_TYPE_MASK) == (t_u16)0U)
+    {
+        // coverity[overrun-buffer-val:SUPPRESS]
+		(void)wlan_process_802dot11_mgmt_pkt(
+            mlan_adap->priv[0], (t_u8 *)&pmgmt_pkt_hdr->wlan_header,
+            pmgmt_pkt_hdr->frm_len + sizeof(wlan_mgmt_pkt) - sizeof(pmgmt_pkt_hdr->frm_len), rxpd);
+    }
+}
+
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+static int wlcm_process_ftm_complete_event()
+{
+	return wifi_process_wlc_ftm_event();
+}
+
+#if CONFIG_WLS_CSI_PROC
+static int wlcm_process_wls_csi_event(void *p_data)
+{
+	return wifi_process_wls_csi_event(p_data);
+}
+
+int wifi_get_wls_csi_sem(void)
+{
+    osa_status_t status = KOSA_StatusSuccess;
+
+    status = OSA_SemaphoreWait((osa_semaphore_handle_t)wls_csi_sem, osaWaitForever_c);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wifi_put_wls_csi_sem(void)
+{
+    osa_status_t status = KOSA_StatusSuccess;
+
+    status = OSA_SemaphorePost((osa_semaphore_handle_t)wls_csi_sem);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+#endif
+
+#endif
+
+static void wlcm_process_region_power_cfg(struct wifi_message *msg)
+{
+    t_u8 *country_code = (t_u8 *)msg->data;
+
+#if CONFIG_COMPRESS_TX_PWTBL
+    t_u8 region_code;
+
+    region_code = region_string_2_region_code(country_code);
+    wlan_set_rg_power_cfg(region_code);
+#endif
+
+    OSA_MemoryFree(country_code);
+}
+
+#if (CONFIG_11K) || (CONFIG_11V)
+static void wlcm_set_rssi_low_threshold(enum cm_sta_state *next, struct wlan_network *curr_nw)
+{
+    (void)next;
+    (void)curr_nw;
+
+    (void)wifi_set_rssi_low_threshold(&wlan.rssi_low_threshold);
+}
+#endif
+
+#if CONFIG_HOST_SLEEP
+static void wlcm_send_host_sleep(struct wifi_message *msg, enum cm_sta_state *next, struct wlan_network *network)
+{
+    uint32_t wake_up_conds = (uint32_t)msg->data;
+
+    (void)next;
+    (void)network;
+
+    (void)wlan_send_host_sleep_int(wake_up_conds, MTRUE);
+}
+#endif
+
+#if CONFIG_CPU_LOADING
+static void wlan_cpu_loading_info_display(void)
+{
+    uint64_t total_runtime = 0;
+    uint64_t task_runtime[CPU_LOADING_TASK_NUM] = {0};
+    float task_runtime_percentage[CPU_LOADING_TASK_NUM] = {0};
+    uint8_t task_index = 0, i = 0;
+    uint32_t collect_time = 0;
+    char cpu_loading_task_name[] = "cpu_loading_task";
+
+    for(i = 0; i < cpu_loading.task_nums; i++) //Don't calculate cpu info of cpu_loading_thread task.
+    {
+        if(!memcmp(cpu_loading_task_name, cpu_loading.task_name[i], strlen(cpu_loading_task_name)))
+            continue;
+
+        if(cpu_loading.status == CPU_LOADING_STATUS_ONGOING)
+            task_runtime[i] = cpu_loading.data_cur[i] - cpu_loading.data_pre[i];
+        else
+            task_runtime[i] = cpu_loading.data_cur[i] - cpu_loading.first_data[i];
+
+        total_runtime += task_runtime[i];
+    }
+
+    collect_time = ((cpu_loading.index - 1) * cpu_loading.sampling_period) /1000;
+    (void)PRINTF("\r\n");
+    if(cpu_loading.status != CPU_LOADING_STATUS_ENDING)
+        (void)PRINTF("CPU loading: %ds ~ %ds \r\n", (collect_time - cpu_loading.sampling_period /1000) + 1, collect_time);
+    else
+        (void)PRINTF("Total CPU loading info in previous %d seconds\r\n", cpu_loading.index * cpu_loading.sampling_period / 1000);
+
+    (void)PRINTF("taskName             \t\tPercentage\r\n");
+    for(int i = 0; i < cpu_loading.task_nums; i++)
+    {
+        if(!memcmp(cpu_loading_task_name, cpu_loading.task_name[i], strlen(cpu_loading_task_name)))
+            continue;
+        task_runtime_percentage[i] = (float)(((float)(task_runtime[i]) / total_runtime) * 100);
+        (void)PRINTF("%s \t\t%6.2f%%\r\n", task_string_name[i], task_runtime_percentage[i]);
+    }
+}
+
+static int wlan_cpu_loading_stop()
+{
+    cpu_loading.status = CPU_LOADING_STATUS_ENDING;
+    wlan_cpu_loading_info_display();
+
+    cpu_loading.index = 0;
+
+    (void)send_user_request(CM_STA_USER_REQUEST_CPU_LOADING, 0); // Notify wlcmgr task to destory cpu_loading_thread task.
+
+    return WM_SUCCESS;
+}
+
+static void wlan_cpu_loading_request()
+{
+    osa_status_t status;
+
+    status = OSA_TimerDestroy((osa_timer_handle_t)cpu_loading.cpu_loading_timer);
+    if (status != KOSA_StatusSuccess)
+    {
+        (void)PRINTF("Failed to delete cpu loading timer: %d.\r\n", ret);
+    }
+
+    OSA_MemoryFree(cpu_loading.cpu_loading_info);
+
+    status = OSA_TaskDestroy((osa_task_handle_t)cpu_loading.cpu_loading_task_Handle);
+    if (status != KOSA_StatusSuccess)
+    {
+        (void)PRINTF("Failed to delete cpu_loading_task: %d.\r\n", ret);
+    }
+
+    cpu_loading.status = CPU_LOADING_STATUS_DEAD;
+
+    (void)PRINTF("Success to stop CPU loading test.\r\n");
+}
+#endif
+
+/*
+ * Event Handlers
+ */
+
+static enum cm_sta_state handle_message(struct wifi_message *msg)
+{
+    enum cm_sta_state next       = wlan.sta_state;
+    struct wlan_network *network = NULL;
+#if CONFIG_WPA_SUPP
+    int ret;
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+    network = &wlan.networks[wlan.cur_network_idx];
+
+    switch (msg->event)
+    {
+        case CM_STA_USER_REQUEST_CONNECT:
+            wlan.pending_assoc_request = false;
+            if (!wlan.assoc_paused)
+            {
+                wlcm_request_connect(msg, &next, network);
+            }
+            else
+            {
+                wlan.pending_assoc_request = true;
+            }
+            break;
+
+        case CM_STA_USER_REQUEST_DISCONNECT:
+#if CONFIG_WPA_SUPP
+            wlan.pending_disconnect_request = false;
+            ret = wpa_supp_abort_scan(netif);
+            if (ret == WM_SUCCESS)
+            {
+                wlan.pending_disconnect_request = true;
+            }
+            wpa_supp_disconnect(netif);
+#endif
+            wlcm_request_disconnect(&next, network);
+            break;
+
+        case CM_STA_USER_REQUEST_SCAN:
+            wlcm_request_scan(msg, &next);
+            break;
+#if (CONFIG_11K) || (CONFIG_11V)
+        case CM_STA_USER_REQUEST_SET_RSSI_THRESHOLD:
+            wlcm_set_rssi_low_threshold(&next, network);
+            break;
+#endif
+#if CONFIG_HOST_SLEEP
+        case CM_STA_USER_REQUEST_HS:
+            wlcm_send_host_sleep(msg, &next, network);
+            break;
+#endif
+        case CM_STA_USER_REQUEST_PS_ENTER:
+            if (wlan.sta_state >= CM_STA_SCANNING && wlan.sta_state <= CM_STA_OBTAINING_ADDRESS)
+            {
+                wlcm_w("ignoring ps enter in invalid state");
+                wlcm_e("Error entering power save mode");
+                break;
+            }
+            if (msg->data == NULL)
+            {
+                wlcm_w("ignoring ps enter request with NULL ps mode");
+                wlcm_e("entering power save mode");
+                break;
+            }
+            wlan_enable_power_save((int)msg->data);
+            break;
+        case CM_STA_USER_REQUEST_PS_EXIT:
+            if (msg->data == NULL)
+            {
+                wlcm_w("ignoring ps exit request with NULL ps mode");
+                break;
+            }
+            wlan_disable_power_save((int)msg->data);
+            break;
+#if CONFIG_CPU_LOADING
+        case CM_STA_USER_REQUEST_CPU_LOADING:
+            wlan_cpu_loading_request();
+            break;
+#endif
+        case WIFI_EVENT_SCAN_START:
+#if CONFIG_WPA_SUPP
+            wifi_scan_start(msg);
+#endif
+            break;
+        case WIFI_EVENT_SCAN_RESULT:
+            wlcm_d("got event: scan result");
+            wlcm_process_scan_result_event(msg, &next);
+            break;
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+        case WIFI_EVENT_FW_HANG:
+            wlcm_d("got event: fw hang");
+            wlcm_process_fw_hang_event(msg, &next);
+            break;
+        case WIFI_EVENT_FW_RESET:
+            wlcm_d("got event: fw reset");
+            wlcm_process_fw_reset_event(msg, &next);
+            break;
+#endif
+
+#if CONFIG_WPA_SUPP
+        case WIFI_EVENT_SURVEY_RESULT_GET:
+            wifi_survey_result_get(msg);
+            break;
+#endif
+
+        case WIFI_EVENT_ASSOCIATION:
+            wlcm_d("got event: association result: %s",
+                    msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+
+            wlcm_process_association_event(msg, &next);
+            break;
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_AUTO_RECONNECT
+        case WIFI_EVENT_ASSOCIATION_NOTIFY:
+            wlcm_d("got event: association notify: %s",
+                    msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+
+            wlcm_process_association_notify_event(msg, &next);
+            break;
+#endif
+#if CONFIG_WPA_SUPP_AP
+        case WIFI_EVENT_ACS_COMPLETE:
+            wlcm_d("got event: acs complete: %s",
+                    msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+
+            wlcm_process_acs_notify_event(msg, &next);
+            break;
+#endif
+#endif
+
+        case WIFI_EVENT_PMK:
+            wlcm_d("got event: PMK result: %s", msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+            wlcm_process_pmk_event(msg, &next, network);
+            break;
+            /* We have received a event from firmware whether
+             * authentication with given wireless credentials was successful
+             * or not. If successful, we are authenticated and can proceed
+             * to IP-level setup by configuring the TCP stack for our
+             * desired address and transitioning to the
+             * CM_STA_REQUESTING_ADDRESS state where we wait for the TCP
+             * stack configuration response.  Otherwise we have failed to
+             * connect to the network.
+             */
+        case WIFI_EVENT_AUTHENTICATION:
+            wlcm_d("got event: authentication result: %s",
+                    msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+            if(msg->reason == WIFI_EVENT_REASON_FAILURE)
+            {
+#if CONFIG_ECSA
+                wrapper_clear_media_connected_event();
+                wlan_switch_to_nondfs_channel();
+#endif
+            }
+            wlcm_process_authentication_event(msg, &next, network);
+            break;
+        case WIFI_EVENT_LINK_LOSS:
+            wlcm_d("got event: link loss, code=%d", (int)msg->data);
+            wlcm_process_link_loss_event(msg, &next, network);
+            break;
+        case WIFI_EVENT_RSSI_LOW:
+            wlcm_d("got event: rssi low");
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_ROAMING)
+            wlcm_process_rssi_low_event(msg, &next, network);
+#else
+            CONNECTION_EVENT(WLAN_REASON_RSSI_LOW, NULL);
+#endif
+            break;
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+        case WIFI_EVENT_RSSI_HIGH:
+            wlcm_d("got event: RSSI high");
+            CONNECTION_EVENT(WLAN_REASON_RSSI_HIGH, NULL);
+            break;
+        case WIFI_EVENT_SNR_LOW:
+            wlcm_d("got event: SNR low");
+            CONNECTION_EVENT(WLAN_REASON_SNR_LOW, NULL);
+            break;
+        case WIFI_EVENT_SNR_HIGH:
+            wlcm_d("got event: SNR high");
+            CONNECTION_EVENT(WLAN_REASON_SNR_HIGH, NULL);
+            break;
+        case WIFI_EVENT_MAX_FAIL:
+            wlcm_d("got event: MAX fail");
+            CONNECTION_EVENT(WLAN_REASON_MAX_FAIL, NULL);
+            break;
+        case WIFI_EVENT_BEACON_MISSED:
+            wlcm_d("got event: Beacon missed");
+            CONNECTION_EVENT(WLAN_REASON_BEACON_MISSED, NULL);
+            break;
+        case WIFI_EVENT_DATA_RSSI_LOW:
+            wlcm_d("got event: DATA_RSSI low");
+            CONNECTION_EVENT(WLAN_REASON_DATA_RSSI_LOW, NULL);
+            break;
+        case WIFI_EVENT_DATA_RSSI_HIGH:
+            wlcm_d("got event: DATA_RSSI high");
+            CONNECTION_EVENT(WLAN_REASON_DATA_RSSI_HIGH, NULL);
+            break;
+        case WIFI_EVENT_DATA_SNR_LOW:
+            wlcm_d("got event: DATA_SNR low");
+            CONNECTION_EVENT(WLAN_REASON_DATA_SNR_LOW, NULL);
+            break;
+        case WIFI_EVENT_DATA_SNR_HIGH:
+            wlcm_d("got event: DATA_SNR high");
+            CONNECTION_EVENT(WLAN_REASON_DATA_SNR_HIGH, NULL);
+            break;
+        case WIFI_EVENT_FW_LINK_QUALITY:
+            wlcm_d("got event: LINK_QUALITY");
+            CONNECTION_EVENT(WLAN_REASON_LINK_QUALITY, NULL);
+            break;
+        case WIFI_EVENT_FW_PRE_BCN_LOST:
+            wlcm_d("got event: PRE_BEACON_LOST");
+            CONNECTION_EVENT(WLAN_REASON_PRE_BEACON_LOST, NULL);
+            break;
+#endif
+#if CONFIG_HOST_SLEEP
+        case WIFI_EVENT_HS_ACTIVATED:
+        case WIFI_EVENT_SLEEP_CONFIRM_DONE:
+#if CONFIG_POWER_MANAGER
+            if (!wlan_is_manual)
+            {
+                is_hs_handshake_done = WLAN_HOSTSLEEP_SUCCESS;
+#ifdef RW610
+                (void)OSA_TimerDeactivate((osa_timer_handle_t)temperature_mon_timer);
+#ifndef __ZEPHYR__
+#if !(CONFIG_WIFI_BLE_COEX_APP)
+                host_sleep_cli_notify();
+#endif
+#endif
+#endif
+            }
+#endif
+            break;
+#endif
+#if (CONFIG_11K) || (CONFIG_11V)
+        case WIFI_EVENT_NLIST_REPORT:
+            wlcm_d("got event: neighbor list report");
+            wlcm_process_neighbor_list_report_event(msg, &next, network);
+            break;
+#endif
+        case WIFI_EVENT_DISASSOCIATION:
+            wlcm_d("got event: disassociation, code=%d", (int)(msg->data));
+#if CONFIG_ECSA
+            wrapper_clear_media_connected_event();
+            wlan_switch_to_nondfs_channel();
+#endif
+            wlcm_process_disassoc_event(msg, &next, network);
+            break;
+
+        case WIFI_EVENT_DEAUTHENTICATION:
+            wlcm_d("got event: deauthentication");
+            wlcm_process_deauthentication_event(msg, &next, network);
+            break;
+
+        case WIFI_EVENT_NET_STA_ADDR_CONFIG:
+            wlcm_d("got event: TCP configured");
+            wlcm_process_sta_addr_config_event(msg, &next, network);
+            break;
+
+        case WIFI_EVENT_GET_HW_SPEC:
+            wlcm_process_get_hw_spec_event();
+            break;
+
+        case WIFI_EVENT_NET_INTERFACE_CONFIG:
+            wlcm_d("got event: Interfaces configured");
+            wlcm_process_net_if_config_event(msg, &next);
+            break;
+
+        case WIFI_EVENT_NET_DHCP_CONFIG:
+            wlcm_process_net_dhcp_config(msg, &next, network);
+            break;
+#if CONFIG_IPV6
+        case WIFI_EVENT_NET_IPV6_CONFIG:
+            wlcm_d("got event: net ipv6 config");
+            if (wlan.cur_network_idx >= WLAN_MAX_KNOWN_NETWORKS)
+                break;
+
+            wlcm_process_net_ipv6_config(msg, &next, network);
+            break;
+#endif /* CONFIG_IPV6 */
+
+        case WIFI_EVENT_CHAN_SWITCH_ANN:
+            wlcm_d("got event: channel switch announcement");
+            wlcm_process_channel_switch_ann(&next, network);
+            break;
+        case WIFI_EVENT_CHAN_SWITCH:
+            wlcm_d("got event: channel switch");
+#if CONFIG_WPA_SUPP
+            wlcm_process_channel_switch_supp(msg);
+#else
+            wlcm_process_channel_switch(msg);
+#endif
+            break;
+
+        case WIFI_EVENT_SLEEP:
+#if CONFIG_WIFI_PS_DEBUG
+            wlcm_d("got event: sleep");
+#endif
+            wlcm_process_sleep_event();
+            break;
+
+        case WIFI_EVENT_IEEE_PS:
+#if CONFIG_WIFI_PS_DEBUG
+            wlcm_d("got event: IEEE ps result: %s", msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+#endif
+            wlcm_process_ieeeps_event(msg);
+            break;
+
+        case WIFI_EVENT_DEEP_SLEEP:
+#if CONFIG_WIFI_PS_DEBUG
+            wlcm_d("got event: deep sleep result: %s",
+                    msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+#endif
+            wlcm_process_deepsleep_event(msg, &next);
+
+            break;
+#if (CONFIG_WNM_PS)
+        case WIFI_EVENT_WNM_PS:
+#if CONFIG_WIFI_PS_DEBUG
+            wlcm_d("got event: WNM ps result: %s", msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+#endif
+            wlcm_process_wnmps_event(msg);
+            break;
+#endif
+        case WIFI_EVENT_IEEE_DEEP_SLEEP:
+#if CONFIG_WIFI_PS_DEBUG
+            wlcm_d("got event: IEEE deep sleep result: %s",
+                    msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+#endif
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+            break;
+        case WIFI_EVENT_WNM_DEEP_SLEEP:
+#if CONFIG_WIFI_PS_DEBUG
+            wlcm_d("got event: WNM deep sleep result: %s",
+                    msg->reason == WIFI_EVENT_REASON_SUCCESS ? "success" : "failure");
+#endif
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(msg->data);
+#else
+            OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+            break;
+#if CONFIG_HOST_SLEEP
+        case WIFI_EVENT_HS_CONFIG:
+            wlcm_process_hs_config_event();
+            break;
+#endif
+        case WIFI_EVENT_11N_ADDBA:
+            wlcm_process_addba_request(msg);
+            break;
+        case WIFI_EVENT_11N_DELBA:
+            wlcm_process_delba_request(msg);
+            break;
+        case WIFI_EVENT_11N_BA_STREAM_TIMEOUT:
+            wlcm_process_ba_stream_timeout_request(msg);
+            break;
+        case WIFI_EVENT_11N_AGGR_CTRL:
+            wlcm_d("AGGR_CTRL ignored for now");
+            break;
+        case WIFI_EVENT_STA_MAC_ADDR_CONFIG:
+            if (msg->data != NULL)
+            {
+                (void)memcpy((void *)&wlan.sta_mac[0], (const void *)msg->data, MLAN_MAC_ADDR_LENGTH);
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree(msg->data);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+            }
+            break;
+        case WIFI_EVENT_UAP_MAC_ADDR_CONFIG:
+            if (msg->data != NULL)
+            {
+                (void)memcpy((void *)&wlan.uap_mac[0], (const void *)msg->data, MLAN_MAC_ADDR_LENGTH);
+#if !CONFIG_MEM_POOLS
+                OSA_MemoryFree(msg->data);
+#else
+                OSA_MemoryPoolFree(buf_32_MemoryPool, msg->data);
+#endif
+            }
+            break;
+        case WIFI_EVENT_BG_SCAN_STOPPED:
+            wlcm_d("got event: BG scan stopped");
+            wifi_process_bg_scan_stopped(msg);
+            break;
+        case WIFI_EVENT_BG_SCAN_REPORT:
+            wlcm_d("got event: BG scan report");
+            wlcm_process_bg_scan_report();
+            break;
+        case WIFI_EVENT_MGMT_FRAME:
+#if defined(SDK_OS_FREE_RTOS)
+            wlcm_d("got event: management frame");
+            wlcm_process_mgmt_frame(msg->data);
+            next = wlan.sta_state;
+            net_stack_buffer_free(msg->data);
+#endif
+            break;
+#if CONFIG_WPA_SUPP
+        case WIFI_EVENT_REMAIN_ON_CHANNEL:
+            wifi_process_remain_on_channel(msg);
+            break;
+        case WIFI_EVENT_MGMT_TX_STATUS:
+            wifi_process_mgmt_tx_status(msg);
+            break;
+#endif
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+        case WIFI_EVENT_FTM_COMPLETE:
+            wlcm_d("got event: continue to ftm or stop");
+            wlcm_process_ftm_complete_event();
+            break;
+#if CONFIG_WLS_CSI_PROC
+        case WIFI_EVENT_WLS_CSI:
+            wlcm_d("got event: receive WLS csi data");
+            if (g_csi_event_for_wls)
+            {
+                wlcm_process_wls_csi_event(msg->data);
+            }
+            break;
+#endif
+#endif
+        case WIFI_EVENT_REGION_POWER_CFG:
+            wlcm_process_region_power_cfg(msg);
+            break;
+        default:
+            wlcm_w("got unknown message: %d", msg->event);
+            break;
+    }
+
+    return next;
+}
+
+static bool is_uap_msg(struct wifi_message *msg)
+{
+    return (((msg->event >= CM_UAP_USER_REQUEST_START) && (msg->event < CM_WLAN_USER_REQUEST_DEINIT)) ||
+            (msg->event <= WIFI_EVENT_UAP_LAST));
+}
+
+/*
+ * Main Thread: the WLAN Connection Manager event queue handler and state
+ * machine.
+ */
+static void wlcmgr_task(void *data)
+{
+    osa_status_t status;
+    struct wifi_message msg;
+    enum cm_sta_state next_sta_state;
+    enum cm_uap_state next_uap_state;
+
+    (void)memset((void *)&msg, 0, sizeof(struct wifi_message));
+
+    /* Wait for all the data structures to be created */
+    while (!wlan.running)
+    {
+        OSA_TimeDelay(500);
+    }
+
+    (void)net_wlan_init();
+
+    while (true)
+    {
+        status = OSA_MsgQGet((osa_msgq_handle_t)wlan.events, &msg, osaWaitForever_c);
+        if ((wlan.stop_request != 0U) && (msg.event == (uint16_t)CM_WLAN_USER_REQUEST_SHUTDOWN))
+        {
+            wlcm_d("Received shutdown request");
+            wlan.status = WLCMGR_THREAD_STOPPED;
+            while (true)
+            {
+                OSA_TimeDelay(60000);
+            }
+        }
+
+        if (status == KOSA_StatusSuccess)
+        {
+#if !CONFIG_WIFI_PS_DEBUG
+            if (msg.event != WIFI_EVENT_SLEEP && msg.event != WIFI_EVENT_IEEE_PS &&
+                    msg.event != WIFI_EVENT_DEEP_SLEEP && msg.event != WIFI_EVENT_IEEE_DEEP_SLEEP)
+            {
+                wlcm_d("got wifi message: %d %d %p", msg.event, msg.reason, msg.data);
+            }
+#else
+            wlcm_d("got wifi message: %d %d %p", msg.event, msg.reason, msg.data);
+#endif
+
+            if (is_uap_msg(&msg) != 0)
+            {
+                /* uAP related msg */
+                next_uap_state = uap_state_machine(&msg);
+                if (wlan.uap_state == next_uap_state)
+                {
+                    continue;
+                }
+
+                wlcm_d("SM uAP %s -> %s", dbg_uap_state_name(wlan.uap_state), dbg_uap_state_name(next_uap_state));
+                wlan.uap_state = next_uap_state;
+            }
+            else if (msg.event == (uint16_t)CM_WLAN_USER_REQUEST_DEINIT)
+            {
+                wlcm_deinit((int)msg.data);
+            }
+            else
+            {
+                /* STA related msg */
+                next_sta_state = handle_message(&msg);
+                if (wlan.sta_state == next_sta_state)
+                {
+                    continue;
+                }
+
+                wlcm_d("SM STA %s -> %s", dbg_sta_state_name(wlan.sta_state), dbg_sta_state_name(next_sta_state));
+                wlan.sta_state = next_sta_state;
+            }
+        }
+        else
+        {
+            wlcm_d("SM queue recv Timed out ");
+        }
+    }
+}
+
+#if CONFIG_WPS2
+/* WLAN Connection Manager scan results callback */
+static int prov_wps_scan_results(unsigned int count)
+{
+    int i;
+    int err;
+
+    if (count == 0)
+    {
+        OSA_SemaphorePost((osa_semaphore_handle_t)wlan_wps.wps_scan_done);
+        return 0;
+    }
+
+    for (i = 0; i < count; i++)
+    {
+        err = wlan_get_scan_result(i, &wlan_wps.wps_res);
+        if (err != 0)
+        {
+            wlcm_e("Error: can't get scan res %d", i);
+            continue;
+        }
+
+        if ((wlan_wps.wps_res.wps_session == WPS_SESSION_PBC) || (wlan_wps.wps_res.wps_session == WPS_SESSION_PIN))
+            break;
+    }
+
+    OSA_SemaphorePost((osa_semaphore_handle_t)wlan_wps.wps_scan_done);
+
+    return 0;
+}
+
+static void wps_task(void *data)
+{
+    osa_status_t status;
+
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)wlan_wps.wps_scan_done);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Failed to create WPS scan semaphore");
+    }
+
+    while (1)
+    {
+        OSA_TimeDelay(500);
+        if ((wlan_wps.wps_state == PROV_WPS_PBC_ENABLED) || (wlan_wps.wps_state == PROV_WPS_PIN_ENABLED))
+        {
+            int i = 5;
+
+            wlcm_d("WPS is enabled");
+            if (is_uap_started())
+            {
+                wlan_wps.wps_state = PROV_WPS_STARTED;
+                wps_conf.role = 2; //WPS_REGISTRAR
+                wlan_set_prov_session(PROV_WPS_SESSION_ATTEMPT);
+                wps_connect(wlan_wps.wps_cmd, wlan_wps.wps_pin, &wlan_wps.wps_res);
+            }
+            else
+            {
+                while (i)
+                {
+                    if (wlan_scan(prov_wps_scan_results) != 0)
+                    {
+                        (void)PRINTF("Error: scan request failed, sta_state");
+#if CONFIG_WLCMGR_DEBUG
+                        (void)PRINTF("(%s)", dbg_sta_state_name(wlan.sta_state));
+#else
+                        (void)PRINTF("(%d)", wlan.sta_state);
+#endif
+                        (void)PRINTF(" is not idle/connected\r\n");
+                        (void)PRINTF("Wait or disconnect network\r\n");
+                        break;
+                    }
+                    OSA_SemaphoreWait((osa_semaphore_handle_t)wlan_wps.wps_scan_done, osaWaitForever_c);
+                    if ((wlan_wps.wps_res.wps_session == WPS_SESSION_PIN) ||
+                        (wlan_wps.wps_res.wps_session == WPS_SESSION_PBC))
+                    {
+                        wlcm_d("WPS Session from AP started");
+                        wlan_wps.wps_state = PROV_WPS_STARTED;
+                        wlan_set_prov_session(PROV_WPS_SESSION_ATTEMPT);
+                        wps_connect(wlan_wps.wps_cmd, wlan_wps.wps_pin, &wlan_wps.wps_res);
+                        break;
+                    }
+                    i--;
+                }
+            }
+
+            wlan_wps.wps_state = PROV_WPS_NONE;
+            memset(&wlan_wps.wps_res, 0, sizeof(wlan_wps.wps_res));
+        }
+    }
+}
+#endif
+/*
+ * WLAN API
+ */
+
+static int send_user_request(enum user_request_type request, unsigned int data)
+{
+    struct wifi_message msg;
+
+    msg.event  = (uint16_t)request;
+    msg.reason = WIFI_EVENT_REASON_SUCCESS;
+    msg.data   = (void *)data;
+
+    if (OSA_MsgQPut((osa_msgq_handle_t)wlan.events, &msg) == KOSA_StatusSuccess)
+    {
+        return WM_SUCCESS;
+    }
+
+    return -WM_FAIL;
+}
+
+static void copy_network(struct wlan_network *dst, struct wlan_network *src)
+{
+    (void)memcpy((void *)dst, (const void *)src, sizeof(struct wlan_network));
+    /* Omit any information that was dynamically
+     * learned from the network so that users can
+     * see which parameters were actually
+     * configured by the user.
+     */
+    if (!src->bssid_specific)
+    {
+        (void)memset(dst->bssid, 0, IEEEtypes_ADDRESS_SIZE);
+    }
+    if (!src->ssid_specific)
+    {
+        (void)memset(dst->ssid, 0, IEEEtypes_SSID_SIZE);
+    }
+    if (!src->channel_specific)
+    {
+        dst->channel = 0;
+    }
+    if (src->ip.ipv4.addr_type != 0U)
+    {
+        dst->ip.ipv4.address = 0;
+        dst->ip.ipv4.gw      = 0;
+        dst->ip.ipv4.netmask = 0;
+        dst->ip.ipv4.dns1    = 0;
+        dst->ip.ipv4.dns2    = 0;
+    }
+}
+
+static int wifi_wakeup_card_cb(osa_rw_lock_t *plock, unsigned int wait_time)
+{
+    osa_status_t status = OSA_SemaphoreWait((osa_semaphore_handle_t)plock->rw_lock, 0);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlan_wake_up_card();
+        status = OSA_SemaphoreWait((osa_semaphore_handle_t)plock->rw_lock, wait_time);
+    }
+
+    if (status != KOSA_StatusSuccess)
+    {
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_init(const uint8_t *fw_start_addr, const size_t size)
+{
+    int ret;
+#if (CONFIG_WMM_UAPSD) || (CONFIG_HOST_SLEEP)
+    osa_status_t status;
+#endif
+
+    if (wlan.status != WLCMGR_INACTIVE)
+    {
+        return WM_SUCCESS;
+    }
+
+#if CONFIG_MEM_POOLS
+    ret = mem_pool_init();
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Failed to init Memory Pools");
+        return ret;
+    }
+#endif
+
+#ifdef OVERRIDE_CALIBRATION_DATA
+    wlan_set_cal_data(ext_cal_data, sizeof(ext_cal_data));
+#else
+#ifndef RW610
+    wlan_set_cal_data(int_cal_data, sizeof(int_cal_data));
+#else
+    wlan_set_cal_data(cal_data_rw610, sizeof(cal_data_rw610));
+#endif
+#endif
+
+#if (CONFIG_HOST_PMK) || (CONFIG_WPS2)
+    wm_mbedtls_lib_init();
+#endif /* (CONFIG_HOST_PMK) || (CONFIG_WPS2) */
+
+    ret = OSA_RWLockCreateWithCB(&sleep_rwlock, "sleep_mutex", "sleep_rwlock", wifi_wakeup_card_cb);
+    if (ret != WM_SUCCESS)
+    {
+        wifi_e("Create sleep cmd lock failed");
+        return ret;
+    }
+
+#if CONFIG_WMM_UAPSD
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)uapsd_sem);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Create uapsd sem failed");
+        return ret;
+    }
+    OSA_SemaphorePost((osa_semaphore_handle_t)uapsd_sem);
+#endif
+#if CONFIG_HOST_SLEEP
+    status = OSA_SemaphoreCreate((osa_semaphore_handle_t)wakelock, 0);
+    if (status != KOSA_StatusSuccess)
+    {
+        wifi_e("Failed to create wake-lock semaphore");
+        return ret;
+    }
+#endif
+
+    ret = wifi_init(fw_start_addr, size);
+    if (ret != 0)
+    {
+        wlcm_e("wifi_init failed. status code %d", ret);
+        return ret;
+    }
+
+    wlan.status = WLCMGR_INIT_DONE;
+    wifi_mac_addr_t mac_addr;
+    wifi_mac_addr_t mac_addr_uap;
+    ret = wifi_get_device_mac_addr(&mac_addr);
+
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Failed to get sta mac address");
+        return ret;
+    }
+
+    ret = wifi_get_device_uap_mac_addr(&mac_addr_uap);
+
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Failed to get uap mac address");
+        return ret;
+    }
+
+    (void)memcpy((void *)&wlan.uap_mac[0], (const void *)mac_addr_uap.mac, MLAN_MAC_ADDR_LENGTH);
+    (void)memcpy((void *)&wlan.sta_mac[0], (const void *)mac_addr.mac, MLAN_MAC_ADDR_LENGTH);
+    (void)PRINTF("MAC Address: ");
+    print_mac((const char *)&wlan.uap_mac);
+    (void)PRINTF("\r\n");
+
+    ret = wifi_get_device_firmware_version_ext(&wlan.fw_ver_ext);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Failed to get verext");
+        return ret;
+    }
+    wlcm_d("WLAN FW ext_version: %s", wlan.fw_ver_ext.version_str);
+
+#if CONFIG_WIFI_FW_DEBUG
+    if (wlan.wlan_usb_init_cb != NULL)
+        wlan.wlan_usb_init_cb();
+    else
+        wifi_d("USB init callback is not registered");
+#endif
+
+#if CONFIG_WPA_SUPP
+#ifdef RW610
+    supp_set_mbedtls_set_time();
+#endif
+#endif
+
+    return ret;
+}
+
+void wlan_deinit(int action)
+{
+    if (wlan.running != 0U)
+    {
+        (void)send_user_request(CM_WLAN_USER_REQUEST_DEINIT, (unsigned int)action);
+    }
+    else
+    {
+        wlcm_deinit(action);
+    }
+#if CONFIG_CSI
+    wlan_reset_csi_filter_data();
+#endif
+#ifndef RW610
+    OSA_RWLockDestroy(&sleep_rwlock);
+#endif
+}
+
+#if CONFIG_WPS2
+static int wlcm_wps_callback(enum wps_event event, void *data, uint16_t len)
+{
+    int ret                  = WM_SUCCESS;
+    struct wlan_network *net = (struct wlan_network *)data;
+
+    wlcm_d("WPS EVENT = %d data = %p len=%d", event, data, len);
+
+    if (event == WPS_STARTED) {
+        wifi_send_wps_cfg_cmd(1); /* Notify wifidriver that wps session has started */
+    }
+    else if (event == WPS_SESSION_SUCCESSFUL)
+    {
+        if (data == NULL)
+        {
+            wifi_send_wps_cfg_cmd(0); /* Notify wifidriver that wps session end */
+            if (wps_conf.role != 2) /* if not WPS_REGISTRAR */
+            {
+                wlcm_e("Invalid data for WPS SESSION SUCCESSFUL");
+                return -WM_FAIL;
+            }
+        }
+        if (len == sizeof(struct wlan_network))
+        {
+            /* It's WPS SESSION */
+            wifi_send_wps_cfg_cmd(0); /* Notify wifidriver that wps session end */
+            ret = wlan_add_network(net);
+
+            if (ret != WM_SUCCESS)
+            {
+                wlcm_d("Adding network failed");
+                return ret;
+            }
+#if CONFIG_NCP
+            CONNECTION_EVENT(WLAN_REASON_WPS_SESSION_DONE, net);
+#endif
+            ret = wlan_connect(net->name);
+            if (ret != WM_SUCCESS)
+            {
+                wlcm_d("Connecting to network failed");
+                return ret;
+            }
+        }
+        else
+        {
+            /* It's ENTP SESSION */
+            ret = wlan_wlcmgr_send_msg(WIFI_EVENT_PMK, WIFI_EVENT_REASON_SUCCESS, data);
+        }
+
+    }
+    else if (event == WPS_SESSION_TIMEOUT || event == WPS_SESSION_FAILED)
+    {
+        wifi_send_wps_cfg_cmd(0); /* Notify wifidriver that wps session end */
+        ret =
+            wlan_wlcmgr_send_msg(WIFI_EVENT_AUTHENTICATION, WIFI_EVENT_REASON_FAILURE, (void *)WPA2_ENTERPRISE_FAILED);
+    }
+
+    return ret;
+}
+#endif
+
+static void assoc_timer_cb(osa_timer_arg_t arg)
+{
+    wlan.assoc_paused = false;
+    if (wlan.pending_assoc_request)
+    {
+        (void)send_user_request(CM_STA_USER_REQUEST_CONNECT, 0);
+    }
+}
+
+#if CONFIG_WPA_SUPP
+static void supp_status_timer_cb(osa_timer_arg_t arg)
+{
+    int ret;
+
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+    if (wlan.status_timeout == 60)
+#else
+    if (wlan.status_timeout == 40)
+#endif
+    {
+        ret = wpa_supp_req_status(wlan.connect ? CONNECT : START);
+
+        if (ret != WM_SUCCESS)
+        {
+            (void)send_user_request(wlan.connect ? CM_STA_USER_REQUEST_DISCONNECT : CM_UAP_USER_REQUEST_STOP, 0);
+        }
+    }
+
+    wlan.status_timeout++;
+}
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V)
+static void neighbor_req_timer_cb(osa_timer_arg_t arg)
+{
+    if (wlan.neighbor_req == true)
+    {
+        wlan.neighbor_req = false;
+        (void)send_user_request(CM_STA_USER_REQUEST_SET_RSSI_THRESHOLD, 0);
+    }
+}
+#endif
+
+#if CONFIG_11R
+#if CONFIG_WPA_SUPP
+static void ft_roam_timer_cb(osa_timer_arg_t arg)
+{
+    wlan.roam_reassoc = false;
+}
+#endif
+#endif
+
+#ifdef RW610
+static void temperature_mon_cb(osa_timer_arg_t arg)
+{
+#if CONFIG_WIFI_RECOVERY
+    if (wifi_recovery_enable || wifi_fw_is_hang())
+    {
+        struct wlan_message msg;
+        (void)memset(&msg, 0U, sizeof(struct wlan_message));
+        msg.data = NULL;
+        msg.id  = WIFI_RECOVERY_REQ;
+        if (OSA_MsgQPut((osa_msgq_handle_t)mon_thread_events, &msg) != KOSA_StatusSuccess)
+        {
+            (void)PRINTF("Failed to send wifi recovery msg to queue\r\n");
+        }
+        return;
+    }
+#endif
+    /*
+     *  get CAU module temperature and write to firmware SMU in every 5s
+     *  can also read FW power status by REG PMU->WLAN_CTRL 0x4003_1068
+     *  bit[3:2] == 3 means FW is in sleep status
+     */
+    if ((mlan_adap != NULL) && (mlan_adap->ps_state == PS_STATE_AWAKE))
+    {
+        wifi_cau_temperature_write_to_firmware();
+    }
+}
+#endif
+
+#if defined(SDK_OS_FREE_RTOS)
+#ifdef SD9177
+
+#include "lwip/udp.h"
+
+static ip_addr_t udp_addr;
+static int udp_addr_set;
+static struct net_ip_config net_udp_addr;
+/*!
+ * @brief Invokes UDP polling, to be run on tcpip_thread.
+ */
+static void poll_udp_client(void *arg)
+{
+    LWIP_UNUSED_ARG(arg);
+    struct pbuf *p;
+    uint8_t udp_data[4] = {1, 2, 3, 4};
+    err_t i;
+
+    if (udp_raw_pcb == NULL)
+        udp_raw_pcb = udp_new_ip_type(IPADDR_TYPE_ANY);
+
+    if (udp_raw_pcb != NULL)
+    {
+        p = pbuf_alloc(PBUF_TRANSPORT, sizeof(udp_data), PBUF_RAM);
+        if (p)
+        {
+            memcpy(p->payload, udp_data, sizeof(udp_data));
+            i = udp_sendto(udp_raw_pcb, p, &udp_addr, 1234);
+            if (i != ERR_OK)
+            {
+                wlcm_d("Got error %d when sending UDP packet!\r\n", i);
+            }
+            pbuf_free(p);
+        }
+        else
+        {
+            wlcm_d("Couldn't allocate a pbuf!!\r\n");
+        }
+    }
+}
+
+static void udp_remove_cb(void *arg)
+{
+    udp_remove((struct udp_pcb *)arg);
+}
+
+static void poll_timer_cb(osa_timer_arg_t arg)
+{
+    void *if_handle = NULL;
+
+    if ((is_sta_ipv4_connected() != 0) && (wlan.cm_ieeeps_configured == true))
+    {
+        if (udp_addr_set == 0)
+        {
+            if_handle = net_get_mlan_handle();
+
+            if (net_get_if_addr(&net_udp_addr, if_handle) != 0)
+            {
+                return;
+            }
+
+#if CONFIG_IPV6
+            memcpy((void *)&udp_addr.u_addr.ip4.addr, (void *)&net_udp_addr.ipv4.gw, sizeof(unsigned int));
+            udp_addr.type = IPADDR_TYPE_V4;
+#else
+            memcpy((void *)&udp_addr.addr, (void *)&net_udp_addr.ipv4.gw, sizeof(unsigned int));
+#endif
+            udp_addr_set = 1;
+        }
+
+        (void)tcpip_try_callback(poll_udp_client, NULL);
+    }
+    else
+    {
+        udp_addr_set = 0;
+        if(udp_raw_pcb != NULL)
+        {
+            (void)tcpip_try_callback(udp_remove_cb, udp_raw_pcb);
+            udp_raw_pcb = NULL;
+        }
+    }
+}
+#endif
+#endif
+
+static void wlan_wait_wlmgr_ready()
+{
+    while (wlan.sta_state == CM_STA_INITIALIZING)
+    {
+        /* wait for wlmgr ready */
+        OSA_TimeDelay(50);
+    }
+}
+
+int wlan_start(int (*cb)(enum wlan_event_reason reason, void *data))
+{
+#ifdef RW610
+    static bool reset_mutex_init = 0;
+#endif
+    int ret;
+    osa_status_t status;
+
+    if (!((wlan.status == WLCMGR_INIT_DONE) || (wlan.status == WLCMGR_INACTIVE)))
+    {
+        wlcm_e("cannot start wlcmgr. unexpected status: %d", wlan.status);
+        return WLAN_ERROR_STATE;
+    }
+
+    if (cb == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (wlan.running != 0U)
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    wlan.sta_state = CM_STA_INITIALIZING;
+
+    wlan.sta_return_to = CM_STA_IDLE;
+    wlan.uap_state     = CM_UAP_INITIALIZING;
+    wlan.uap_return_to = CM_UAP_INITIALIZING;
+
+#if CONFIG_WIFI_STA_RECONNECT
+    wlan.reassoc_control = true;
+#endif
+    wlan.hidden_scan_on  = false;
+
+    wlcm_process_init_params();
+
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_ROAMING)
+    wlan.rssi_low_threshold = 70;
+#endif
+
+#ifdef RW610
+    wlan.wakeup_conditions = 0;
+#else
+    wlan.wakeup_conditions = (unsigned int)WAKE_ON_UNICAST | (unsigned int)WAKE_ON_MAC_EVENT |
+                             (unsigned int)WAKE_ON_MULTICAST | (unsigned int)WAKE_ON_ARP_BROADCAST;
+#endif
+
+    wlan.num_networks = 0;
+    (void)memset(&wlan.networks[0], 0, sizeof(wlan.networks));
+    (void)memset(&wlan.scan_chan_list, 0, sizeof(wifi_scan_chan_list_t));
+    wlan.scan_count = 0;
+    wlan.cb         = cb;
+    wlan.scan_cb    = NULL;
+    wlan.internal = 0;
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+    wlan.ca_cert_data     = NULL;
+    wlan.ca_cert_len      = 0;
+    wlan.client_cert_data = NULL;
+    wlan.client_cert_len  = 0;
+    wlan.client_key_data  = NULL;
+    wlan.client_key_len   = 0;
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    wlan.dh_data          = NULL;
+    wlan.dh_len           = 0;
+    wlan.server_cert_data = NULL;
+    wlan.server_cert_len  = 0;
+    wlan.server_key_data  = NULL;
+    wlan.server_key_len   = 0;
+#endif
+#endif
+#endif
+#endif
+
+    status = OSA_MsgQCreate((osa_msgq_handle_t)wlan.events, MAX_EVENTS, sizeof(struct wifi_message));
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("unable to create event queue: %d", status);
+        return -WM_FAIL;
+    }
+
+    ret = wifi_register_event_queue((osa_msgq_handle_t)wlan.events);
+
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("unable to register event queue");
+        OSA_MsgQDestroy((osa_msgq_handle_t)wlan.events);
+        return -WM_FAIL;
+    }
+
+    status = OSA_TaskCreate((osa_task_handle_t)wlan.wlcmgr_task_Handle, OSA_TASK(wlcmgr_task), NULL);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlan.cb = NULL;
+        (void)wifi_unregister_event_queue(&wlan.events);
+        OSA_MsgQDestroy((osa_msgq_handle_t)wlan.events);
+        return -WM_FAIL;
+    }
+
+#if ((CONFIG_11MC) || (CONFIG_11AZ)) && (CONFIG_WLS_CSI_PROC)
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)wls_csi_sem) ;
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("unable to create wls csi lock: %d", status);
+        return -WM_FAIL;
+    }
+    OSA_SemaphorePost((osa_semaphore_handle_t)wls_csi_sem);
+#endif
+
+    if (OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)wlan.scan_lock) != KOSA_StatusSuccess)
+    {
+        (void)wifi_unregister_event_queue(&wlan.events);
+        OSA_MsgQDestroy((osa_msgq_handle_t)wlan.events);
+        OSA_TaskDestroy((osa_task_handle_t)wlan.wlcmgr_task_Handle);
+        return -WM_FAIL;
+    }
+    OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+
+#ifdef RW610
+    if (!reset_mutex_init)
+    {
+        status = OSA_MutexCreate((osa_mutex_handle_t)reset_lock);
+        if (status != KOSA_StatusSuccess)
+        {
+            wlan.cb = NULL;
+            wifi_unregister_event_queue(&wlan.events);
+            OSA_MsgQDestroy((osa_msgq_handle_t)wlan.events);
+            OSA_TaskDestroy((osa_task_handle_t)wlan.wlcmgr_task_Handle);
+            OSA_SemaphoreDestroy((osa_semaphore_handle_t)wlan.scan_lock);
+            return -WM_FAIL;
+        }
+        reset_mutex_init = 1;
+    }
+    if (!mon_thread_init)
+    {
+
+        status = OSA_MsgQCreate((osa_msgq_handle_t)mon_thread_events, MAX_EVENTS, sizeof(struct wlan_message));
+        if (status != KOSA_StatusSuccess)
+        {
+            wlcm_e("unable to create event queue: %d", status);
+            return -WM_FAIL;
+        }
+#if ((defined(APP_LOWPOWER_ENABLED) && (APP_LOWPOWER_ENABLED == 1)) && \
+     ((CONFIG_WIFI_BLE_COEX_APP) && (CONFIG_WIFI_BLE_COEX_APP == 1)))
+        /* For coex app, only register wlan notify callback when APP_LOWPOWER_ENABLED == 1 */
+#if CONFIG_HOST_SLEEP
+#if CONFIG_POWER_MANAGER
+        PM_RegisterNotify(kPM_NotifyGroup0, &wlan_notify);
+#endif
+#endif
+#endif
+        /* Host sleep hanshake will be done in IDLE task and infinite
+         * while loop is added to wait for hankshake complete to
+         * prevent IDLE task from entering suspend state.
+         * If mon_thread using same priority of IDLE task, then the
+         * mon_thread task could not be scheduled as we did not
+         * enabled time slice.
+         */
+        status = OSA_TaskCreate((osa_task_handle_t)wlcmgr_mon_task_Handle, OSA_TASK(wlcmgr_mon_task), NULL);
+        if (status != KOSA_StatusSuccess)
+        {
+            wlan.cb = NULL;
+            wifi_unregister_event_queue(&wlan.events);
+            OSA_MsgQDestroy((osa_msgq_handle_t)wlan.events);
+            OSA_TaskDestroy((osa_task_handle_t)wlan.wlcmgr_task_Handle);
+            OSA_SemaphoreDestroy((osa_semaphore_handle_t)wlan.scan_lock);
+            OSA_MutexDestroy((osa_mutex_handle_t)reset_lock);
+            return -WM_FAIL;
+        }
+        mon_thread_init = 1;
+    }
+    wifi_cau_temperature_enable();
+    status = OSA_TimerCreate((osa_timer_handle_t)temperature_mon_timer, TEMPERATURE_MON_TIMEOUT,
+                             &temperature_mon_cb, NULL, KOSA_TimerPeriodic, OSA_TIMER_AUTO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Unable to create temperature monitor timer");
+    }
+#endif
+
+    wlan.running = 1;
+
+    wlan.status = WLCMGR_ACTIVATED;
+
+#if CONFIG_WPS2
+    wlcm_d("WPS started");
+    wps_start(&wps_conf);
+
+    status = OSA_TaskCreate((osa_task_handle_t)wlan_wps.wps_task_Handle, OSA_TASK(wps_task), NULL);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlan.cb = NULL;
+        wifi_unregister_event_queue(&wlan.events);
+        OSA_MsgQDestroy((osa_msgq_handle_t)wlan.events);
+        OSA_TaskDestroy((osa_task_handle_t)wlan.wlcmgr_task_Handle);
+        OSA_SemaphoreDestroy((osa_semaphore_handle_t)wlan.scan_lock);
+        OSA_MutexDestroy((osa_mutex_handle_t)reset_lock);
+        return -WM_FAIL;
+    }
+#endif
+
+#if CONFIG_CPU_LOADING
+    cpu_loading.status = CPU_LOADING_STATUS_DEAD;
+    cpu_loading.sampling_period = CPU_LOADING_PERIOD;
+#endif
+
+    status = OSA_TimerCreate((osa_timer_handle_t)wlan.assoc_timer, BAD_MIC_TIMEOUT, &assoc_timer_cb, NULL,
+                          KOSA_TimerOnce, OSA_TIMER_NO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Unable to create unicast bad mic timer");
+        return -WM_FAIL;
+    }
+
+#if CONFIG_WPA_SUPP
+    status = OSA_TimerCreate((osa_timer_handle_t)wlan.supp_status_timer, SUPP_STATUS_TIMEOUT,
+                          &supp_status_timer_cb, NULL, KOSA_TimerPeriodic, OSA_TIMER_NO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Unable to create supp status timer");
+        return -WM_FAIL;
+    }
+#endif
+
+
+#if CONFIG_11K
+
+    memset(&wlan.nbr_rpt, 0x00, sizeof(wlan_rrm_neighbor_report_t));
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V)
+    status = OSA_TimerCreate((osa_timer_handle_t)wlan.neighbor_req_timer, NEIGHBOR_REQ_TIMEOUT,
+                          &neighbor_req_timer_cb, NULL, KOSA_TimerOnce, OSA_TIMER_NO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Unable to create neighbor request timer");
+        return ret;
+    }
+#endif
+
+#if defined(SDK_OS_FREE_RTOS)
+#ifdef SD9177
+    status = OSA_TimerCreate((osa_timer_handle_t)wlan.poll_timer, POLL_TIMEOUT,
+                          &poll_timer_cb, NULL, KOSA_TimerPeriodic, OSA_TIMER_NO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Unable to create poll timer");
+        return -WM_FAIL;
+    }
+#endif
+#endif
+
+#if CONFIG_11R
+#if CONFIG_WPA_SUPP
+    status = OSA_TimerCreate((osa_timer_handle_t)wlan.ft_roam_timer, FT_ROAM_TIMEOUT,
+                          &ft_roam_timer_cb, NULL, KOSA_TimerOnce, OSA_TIMER_NO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Unable to create ft roam timer");
+        return -WM_FAIL;
+    }
+#endif
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+#ifdef IR_OUTBAND_TRIGGER_GPIO
+    gpio_pin_config_t out_config = {kGPIO_DigitalOutput, 1, kGPIO_NoIntmode};
+
+#if defined(IOMUXC_GPIO_IR_OUTBAND_TRIGGER)
+    IOMUXC_SetPinMux(IOMUXC_GPIO_IR_OUTBAND_TRIGGER, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
+                     0U);
+#endif
+    GPIO_PinInit(IR_OUTBAND_TRIGGER_GPIO, IR_OUTBAND_TRIGGER_GPIO_PIN, &out_config);
+#endif
+
+#endif
+
+    wlan_wait_wlmgr_ready();
+
+#if CONFIG_WIFI_SHELL
+#if CONFIG_WIFI_RF_TEST_MODE
+    ret = wlan_test_mode_cli_init();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("Failed to initialize WLAN RF test mode CLIs\r\n");
+        return 0;
+    }
+#endif
+#if !(CONFIG_WIFI_RF_TEST_MODE) || (CONFIG_RW610)
+    ret = wlan_basic_cli_init();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("Failed to initialize BASIC WLAN CLIs\r\n");
+        return 0;
+    }
+    ret = wlan_cli_init();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("Failed to initialize WLAN CLIs\r\n");
+        return 0;
+    }
+#if CONFIG_SIGMA_AGENT
+    ret = ping_cli_init();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("Failed to initialize PING CLI\r\n");
+        return 0;
+    }
+#endif
+    ret = wlan_enhanced_cli_init();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("Failed to initialize WLAN Enhanced CLIs\r\n");
+        return 0;
+    }
+#if CONFIG_WPA_SUPP
+    ret = wpa_cli_init();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("Failed to initialize WPA SUPP CLIs\r\n");
+        return 0;
+    }
+#endif
+#if (CONFIG_HOST_SLEEP) && !defined(__ZEPHYR__)
+    ret = host_sleep_cli_init();
+    if (ret != WM_SUCCESS)
+    {
+        PRINTF("Failed to initialize WLAN CLIs\r\n");
+        return 0;
+    }
+#endif
+#endif
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wlan_stop(void)
+{
+    osa_status_t status = KOSA_StatusIdle;
+    int ret = WM_SUCCESS;
+#ifndef RW610
+    int total_wait_time = 1000; /* millisecs */
+    int check_interval  = 200;  /* millisecs */
+    int num_iterations  = total_wait_time / check_interval;
+#endif
+
+    if (wlan.status != WLCMGR_ACTIVATED)
+    {
+        wlcm_e("cannot stop wlcmgr. unexpected status: %d", wlan.status);
+        return WLAN_ERROR_STATE;
+    }
+
+    if (!wlan.running)
+    {
+        wlcm_e("cannot stop wlcmgr. unexpected wlan.running: %d", wlan.running);
+        return WLAN_ERROR_STATE;
+    }
+#if OTP_CHANINFO
+    wifi_free_fw_region_and_cfp_tables();
+#endif
+
+#ifndef RW610
+    wlan.running = 0;
+    wlan.scan_cb = NULL;
+
+#if CONFIG_WPA_SUPP
+
+    wifi_supp_deinit();
+
+    ret = wpa_supp_deinit();
+    if (ret != 0)
+    {
+        wlcm_e("wpa_supp_deinit failed. status code %d", ret);
+        return WLAN_ERROR_STATE;
+    }
+#endif
+
+    /* We need to wait for scan_lock as wifi scan might have been
+     * scheduled, so it must be completed before deleting cm_main_thread
+     * here. Otherwise deadlock situation might arrive as both of them
+     * share command_lock semaphore.
+     */
+    status = OSA_SemaphoreWait((osa_semaphore_handle_t)wlan.scan_lock, osaWaitForever_c);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to get scan lock: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+#else
+    /* If CONFIG_WIFI_RECOVERY is defined, 0xb2 CMD will be skipped, but dhcp_server_stop()
+     * is called in 0xb2 CMD response. So it needs to be called here to stop DHCP server
+     */
+#if !CONFIG_WIFI_RECOVERY
+    if (wlan.uap_state == CM_UAP_IP_UP)
+        dhcp_server_stop();
+#endif
+#endif
+    status = OSA_SemaphoreDestroy((osa_semaphore_handle_t)wlan.scan_lock);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete scan lock: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+    wlan.is_scan_lock = 0;
+
+    wlan.scan_cb = NULL;
+
+    status = OSA_TimerDestroy((osa_timer_handle_t)wlan.assoc_timer);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete assoc timer: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+    wlan.scan_cb = NULL;
+
+#if CONFIG_WPA_SUPP
+    status = OSA_TimerDestroy((osa_timer_handle_t)wlan.supp_status_timer);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete supp status timer: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V)
+    status = OSA_TimerDestroy((osa_timer_handle_t)wlan.neighbor_req_timer);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete neighbor req timer: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+#endif
+
+#if CONFIG_11R
+#if CONFIG_WPA_SUPP
+    status = OSA_TimerDestroy((osa_timer_handle_t)wlan.ft_roam_timer);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete ft roam timer: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+#endif
+#endif
+
+#if defined(SDK_OS_FREE_RTOS)
+#ifdef SD9177
+    status = OSA_TimerDestroy((osa_timer_handle_t)wlan.poll_timer);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete poll timer: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+#endif
+#endif
+
+#ifdef RW610
+    status = OSA_TimerDestroy((osa_timer_handle_t)temperature_mon_timer);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete temperature monitor timer: %d.", ret);
+        return WLAN_ERROR_STATE;
+    }
+#else
+    /* We need to tell the AP that we're going away, however we've already
+     * stopped the main thread so we can't do this by means of the state
+     * machine.  Unregister from the wifi interface and explicitly send a
+     * deauth request and then proceed to tearing the main thread down. */
+
+    /* Set stop_request and wait for wlcmgr thread to acknowledge it */
+    wlan.stop_request = (uint8_t) true;
+
+    wlcm_d("Sent wlcmgr shutdown request. Current State: %d", wlan.status);
+
+    (void)send_user_request(CM_WLAN_USER_REQUEST_SHUTDOWN, 0);
+
+    --num_iterations;
+    while (wlan.status != WLCMGR_THREAD_STOPPED && num_iterations)
+    {
+        --num_iterations;
+        OSA_TimeDelay((uint32_t)check_interval);
+    }
+
+    if (wlan.status != WLCMGR_THREAD_STOPPED && !num_iterations)
+    {
+        wlcm_d("Timed out waiting for wlcmgr to stop\r\n");
+        wlcm_d("Forcing halt for wlcmgr thread\r\n");
+        /* Reinitiailize variable states */
+        wlan.status = WLCMGR_THREAD_STOPPED;
+    }
+
+    wlan.stop_request = (uint8_t) false;
+#endif
+    if (wm_wifi.wlc_mgr_event_queue)
+    {
+        ret = wifi_unregister_event_queue(&wlan.events);
+
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_w("failed to unregister wifi event queue: %d", ret);
+            return WLAN_ERROR_STATE;
+        }
+    }
+
+    status = OSA_MsgQDestroy((osa_msgq_handle_t)wlan.events);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to delete event queue: %d", ret);
+        return WLAN_ERROR_STATE;
+    }
+
+#if CONFIG_HOST_SLEEP
+    OSA_SemaphoreDestroy(wakelock);
+#endif
+#if ((CONFIG_11MC) || (CONFIG_11AZ)) && (CONFIG_WLS_CSI_PROC)
+    (void)OSA_SemaphoreDestroy((osa_semaphore_handle_t)wls_csi_sem);
+#endif
+
+#ifndef RW610
+    if (wlan.sta_state > CM_STA_ASSOCIATING)
+    {
+        (void)wifi_deauthenticate((uint8_t *)wlan.networks[wlan.cur_network_idx].bssid);
+        wlan.sta_return_to = CM_STA_IDLE;
+    }
+    if (wlan.uap_state > CM_UAP_CONFIGURED)
+    {
+        (void)wifi_uap_stop();
+        (void)dhcp_server_stop();
+    }
+
+    status = OSA_TaskDestroy((osa_task_handle_t)wlan.wlcmgr_task_Handle);
+
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_w("failed to terminate thread: %d", ret);
+        return WLAN_ERROR_STATE;
+    }
+
+#ifndef __ZEPHYR__
+    wlan_dhcp_cleanup();
+#endif
+
+    (void)net_wlan_deinit();
+
+    wlan.status = WLCMGR_INIT_DONE;
+    wlcm_d("WLCMGR thread deleted\n\r");
+#else
+    wlan.running = 0;
+    wlan.status  = WLCMGR_INACTIVE;
+    memset(&wlan, 0x00, sizeof(wlan));
+
+    wifi_deinit();
+
+    OSA_RWLockDestroy(&sleep_rwlock);
+#endif
+
+#if CONFIG_WMM_UAPSD
+    OSA_SemaphoreDestroy((osa_semaphore_handle_t)uapsd_sem);
+#endif
+#if CONFIG_11MC
+    g_ftm_civic_cfg.civic_req = 0;
+    g_ftm_location_cfg.lci_req = 0;
+#endif
+    return ret;
+}
+
+#if defined(SDK_OS_FREE_RTOS)
+#define DEF_UAP_IP 0xc0a80a01UL /* 192.168.10.1 */
+static unsigned int uap_ip = DEF_UAP_IP;
+#endif
+
+void wlan_initialize_uap_network(struct wlan_network *net)
+{
+    (void)memset(net, 0, sizeof(struct wlan_network));
+    /* Set profile name */
+    (void)strcpy(net->name, "uap-network");
+    /* Set channel selection to auto (0) */
+    net->channel = 0;
+    /* Set network type to uAP */
+    net->type = WLAN_BSS_TYPE_UAP;
+    /* Set network role to uAP */
+    net->role = WLAN_BSS_ROLE_UAP;
+#if defined(SDK_OS_FREE_RTOS)
+    /* Set IP address to 192.168.10.1 */
+    net->ip.ipv4.address = htonl(uap_ip);
+    /* Set default gateway to 192.168.10.1 */
+    net->ip.ipv4.gw = htonl(uap_ip);
+    /* Set netmask to 255.255.255.0 */
+    net->ip.ipv4.netmask = htonl(0xffffff00UL);
+#endif
+    /* Specify address type as static assignment */
+    net->ip.ipv4.addr_type = ADDR_TYPE_STATIC;
+}
+
+void wlan_initialize_sta_network(struct wlan_network *net)
+{
+    (void)memset(net, 0, sizeof(struct wlan_network));
+    /* Set profile name */
+    (void)strcpy(net->name, "sta-network");
+    /* Set channel selection to auto (0) */
+    net->channel = 0;
+    /* Set network type to sta */
+    net->type = WLAN_BSS_TYPE_STA;
+    /* Set network role to sta */
+    net->role = WLAN_BSS_ROLE_STA;
+    /* Specify address type as dynamic assignment */
+    net->ip.ipv4.addr_type = ADDR_TYPE_DHCP;
+}
+
+static bool isHexNumber(const char *str, const uint8_t len)
+{
+    for (int i = 0; i < len; ++i)
+    {
+        if (('0' > str[i] || '9' < str[i]) && ('A' > str[i] || 'F' < str[i]) && ('a' > str[i] || 'f' < str[i]))
+        {
+            return false;
+        }
+    }
+
+    return true;
+}
+
+static bool wlan_is_key_valid(struct wlan_network *network)
+{
+    enum wlan_security_type type = network->security.type;
+    bool valid                   = true;
+
+    switch (type)
+    {
+        case WLAN_SECURITY_WPA:
+        case WLAN_SECURITY_WPA2:
+        case WLAN_SECURITY_WPA_WPA2_MIXED:
+#if CONFIG_11R
+        case WLAN_SECURITY_WPA2_FT:
+#endif
+            /* check the length of PSK phrase */
+            if (network->security.psk_len < WLAN_PSK_MIN_LENGTH || network->security.psk_len >= WLAN_PSK_MAX_LENGTH)
+            {
+                wlcm_e(
+                    "Invalid passphrase length %d "
+                    "(expected ASCII characters: 8..63)",
+                    network->security.psk_len);
+                return false;
+            }
+            if ((network->security.psk_len == WLAN_PSK_MAX_LENGTH - 1) &&
+                (isHexNumber(network->security.psk, network->security.psk_len) == false))
+            {
+                wlcm_e(
+                    "Invalid hexadecimal digits psk"
+                    "(expected Hexadecimal digits: 64)");
+                return false;
+            }
+            break;
+        case WLAN_SECURITY_WPA2_WPA3_SAE_MIXED:
+            /* check the length of PSK phrase */
+            if (network->security.psk_len < WLAN_PSK_MIN_LENGTH || network->security.psk_len >= WLAN_PSK_MAX_LENGTH)
+            {
+                wlcm_e(
+                    "Invalid passphrase length %d "
+                    "(expected ASCII characters: 8..63)",
+                    network->security.psk_len);
+                return false;
+            }
+            if ((network->security.psk_len == WLAN_PSK_MAX_LENGTH - 1) &&
+                (isHexNumber(network->security.psk, network->security.psk_len) == false))
+            {
+                wlcm_e(
+                    "Invalid hexadecimal digits psk"
+                    "(expected Hexadecimal digits: 64)");
+                return false;
+            }
+        case WLAN_SECURITY_WPA3_SAE:
+#if CONFIG_WPA_SUPP
+#if CONFIG_11R
+        case WLAN_SECURITY_WPA3_FT_SAE:
+#endif
+#endif
+        case WLAN_SECURITY_WPA3_SAE_EXT_KEY:
+            if (network->security.password_len < WLAN_PASSWORD_MIN_LENGTH ||
+                network->security.password_len > WLAN_PASSWORD_MAX_LENGTH)
+            {
+                wlcm_e("Invalid password length %d (expected 8..255)", network->security.password_len);
+                return false;
+            }
+            break;
+        case WLAN_SECURITY_NONE:
+        case WLAN_SECURITY_WILDCARD:
+#if CONFIG_DRIVER_OWE
+        case WLAN_SECURITY_OWE_ONLY:
+#endif
+#if CONFIG_WPA2_ENTP
+        case WLAN_SECURITY_EAP_TLS:
+#elif CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if CONFIG_EAP_TLS
+        case WLAN_SECURITY_EAP_TLS:
+        case WLAN_SECURITY_EAP_TLS_SHA256:
+#if CONFIG_11R
+        case WLAN_SECURITY_EAP_TLS_FT:
+        case WLAN_SECURITY_EAP_TLS_FT_SHA384:
+#endif
+#endif
+#if CONFIG_EAP_TTLS
+        case WLAN_SECURITY_EAP_TTLS:
+#if CONFIG_EAP_MSCHAPV2
+        case WLAN_SECURITY_EAP_TTLS_MSCHAPV2:
+#endif
+#endif
+#if CONFIG_EAP_PEAP
+#if CONFIG_EAP_MSCHAPV2
+        case WLAN_SECURITY_EAP_PEAP_MSCHAPV2:
+#endif
+#if CONFIG_EAP_TLS
+        case WLAN_SECURITY_EAP_PEAP_TLS:
+#endif
+#if CONFIG_EAP_GTC
+        case WLAN_SECURITY_EAP_PEAP_GTC:
+#endif
+#endif
+#if CONFIG_EAP_SIM
+        case WLAN_SECURITY_EAP_SIM:
+#endif
+#if CONFIG_EAP_AKA
+        case WLAN_SECURITY_EAP_AKA:
+#endif
+#if CONFIG_EAP_AKA_PRIME
+        case WLAN_SECURITY_EAP_AKA_PRIME:
+#endif
+#if CONFIG_EAP_FAST
+#if CONFIG_EAP_MSCHAPV2
+        case WLAN_SECURITY_EAP_FAST_MSCHAPV2:
+#endif
+#if CONFIG_EAP_GTC
+        case WLAN_SECURITY_EAP_FAST_GTC:
+#endif
+#endif
+#endif
+#endif
+#if CONFIG_PEAP_MSCHAPV2
+        case WLAN_SECURITY_EAP_PEAP_MSCHAPV2:
+#endif
+            valid = true;
+            break;
+        case WLAN_SECURITY_WEP_OPEN:
+        case WLAN_SECURITY_WEP_SHARED:
+            valid = false;
+            break;
+        default:
+
+            valid = false;
+            break;
+    }
+
+    if (valid == false)
+    {
+        return false;
+    }
+    else
+    {
+        return true;
+    }
+}
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if CONFIG_EAP_TLS
+static bool wlan_is_eap_tls_security(enum wlan_security_type security)
+{
+    if ((security == WLAN_SECURITY_EAP_TLS) || (security == WLAN_SECURITY_EAP_TLS_SHA256)
+#if CONFIG_11R
+        || (security == WLAN_SECURITY_EAP_TLS_FT) || (security == WLAN_SECURITY_EAP_TLS_FT_SHA384)
+#endif
+       )
+        return true;
+    return false;
+}
+#endif
+
+#if CONFIG_EAP_TTLS
+static bool wlan_is_eap_ttls_security(enum wlan_security_type security)
+{
+    if (security == WLAN_SECURITY_EAP_TTLS)
+        return true;
+#if CONFIG_EAP_MSCHAPV2
+    if (security == WLAN_SECURITY_EAP_TTLS_MSCHAPV2)
+        return true;
+#endif
+
+    return false;
+}
+#endif
+
+#if CONFIG_EAP_PEAP
+static bool wlan_is_eap_peap_security(enum wlan_security_type security)
+{
+#if CONFIG_EAP_MSCHAPV2
+    if (security == WLAN_SECURITY_EAP_PEAP_MSCHAPV2)
+        return true;
+#endif
+#if CONFIG_EAP_GTC
+    if (security == WLAN_SECURITY_EAP_PEAP_GTC)
+        return true;
+#endif
+#if CONFIG_EAP_TLS
+    if (security == WLAN_SECURITY_EAP_PEAP_TLS)
+        return true;
+#endif
+    return false;
+}
+#endif
+
+static bool wlan_is_eap_fast_security(enum wlan_security_type security)
+{
+#if CONFIG_EAP_MSCHAPV2
+    if (security == WLAN_SECURITY_EAP_FAST_MSCHAPV2)
+        return true;
+#endif
+#if CONFIG_EAP_GTC
+    if (security == WLAN_SECURITY_EAP_FAST_GTC)
+        return true;
+#endif
+    return false;
+}
+
+static bool wlan_is_skip_cert_cfg(enum wlan_security_type security)
+{
+#if CONFIG_EAP_MSCHAPV2
+    if (security == WLAN_SECURITY_EAP_TTLS_MSCHAPV2)
+        return true;
+
+    if (security == WLAN_SECURITY_EAP_PEAP_MSCHAPV2)
+        return true;
+#endif
+
+    return false;
+}
+
+#endif
+#endif
+
+static int wlan_key_mgmt_wpa_psk(int akm)
+{
+    int rakm = (WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_FT_PSK | WLAN_KEY_MGMT_PSK_SHA256);
+
+    if (akm == 0)
+    {
+        return 0;
+    }
+
+    akm &= ~(WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_FT_PSK | WLAN_KEY_MGMT_PSK_SHA256);
+
+    return (!akm && rakm);
+}
+
+#if CONFIG_11R
+static int wlan_key_mgmt_ft_psk(int akm)
+{
+    int rakm = WLAN_KEY_MGMT_FT_PSK;
+
+    if (akm == 0)
+    {
+        return 0;
+    }
+
+    akm &= ~WLAN_KEY_MGMT_FT_PSK;
+
+    return (!akm && rakm);
+}
+#endif
+
+static int wlan_key_mgmt_sae(int akm)
+{
+    int rakm;
+
+    if (akm == 0)
+    {
+        return 0;
+    }
+
+    rakm = (
+#if CONFIG_WPA_SUPP_DPP
+            WLAN_KEY_MGMT_DPP |
+#endif
+            WLAN_KEY_MGMT_SAE |
+            WLAN_KEY_MGMT_SAE_EXT_KEY);
+
+    akm &= ~(
+#if CONFIG_WPA_SUPP_DPP
+            WLAN_KEY_MGMT_DPP |
+#endif
+            WLAN_KEY_MGMT_SAE |
+            WLAN_KEY_MGMT_SAE_EXT_KEY);
+
+    return (!akm && rakm);
+}
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_11R
+static int wlan_key_mgmt_ft_sae(int akm)
+{
+    int rakm =~WLAN_KEY_MGMT_FT_SAE;
+
+    if (akm == 0)
+    {
+        return 0;
+    }
+
+    akm &= ~WLAN_KEY_MGMT_FT_SAE;
+
+    return (!akm && rakm);
+}
+#endif
+#endif
+
+static int wlan_key_mgmt_wpa_psk_sae(int akm)
+{
+    int rakm;
+
+    if (akm == 0)
+    {
+        return 0;
+    }
+
+    rakm = (
+#if CONFIG_WPA_SUPP_DPP
+                WLAN_KEY_MGMT_DPP |
+#endif
+                WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_PSK_SHA256 | WLAN_KEY_MGMT_SAE);
+
+    akm &= ~(
+#if CONFIG_WPA_SUPP_DPP
+            WLAN_KEY_MGMT_DPP |
+#endif
+            WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_PSK_SHA256 | WLAN_KEY_MGMT_SAE);
+
+    return (!akm && rakm);
+}
+
+#if CONFIG_DRIVER_OWE
+static int wlan_key_mgmt_owe(int akm)
+{
+    int rakm = WLAN_KEY_MGMT_OWE;
+
+    if (akm == 0)
+    {
+        return 0;
+    }
+
+    akm &= ~WLAN_KEY_MGMT_OWE;
+
+    return (!akm && rakm);
+}
+#endif
+
+#if CONFIG_WPA_SUPP_DPP
+static int wlan_key_mgmt_dpp(int akm)
+{
+    int rakm = WLAN_KEY_MGMT_DPP;
+
+    if (akm == 0)
+    {
+        return 0;
+    }
+
+    akm &= ~WLAN_KEY_MGMT_DPP;
+
+    return (!akm && rakm);
+}
+#endif
+
+int wlan_add_network(struct wlan_network *network)
+{
+    int pos = -1;
+    int i;
+    unsigned int len;
+    int ret;
+
+    if (!wlan.running)
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+    if (network == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if ((network->channel > MAX_CHANNELS_BG) && ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        wlcm_e("Not support 5G, please set 2G channel");
+        return -WM_E_INVAL;
+    }
+    if ((network->acs_band == 1) && ISSUPP_NO5G(mlan_adap->fw_cap_ext))
+    {
+        wlcm_e("Not support 5G, please not set acs_band 1");
+        return -WM_E_INVAL;
+    }
+
+    if (network->role == WLAN_BSS_ROLE_STA)
+    {
+        if (is_running() && !is_state(CM_STA_IDLE) && !is_state(CM_STA_ASSOCIATED) && !is_state(CM_STA_CONNECTED))
+        {
+            return WLAN_ERROR_STATE;
+        }
+    }
+
+    /* make sure that the network name length is acceptable */
+    len = strlen(network->name);
+    if (len < WLAN_NETWORK_NAME_MIN_LENGTH || len >= WLAN_NETWORK_NAME_MAX_LENGTH)
+    {
+        wlcm_e("name length is out of bounds");
+        return -WM_E_INVAL;
+    }
+
+    /* make sure that either the SSID or BSSID field is present */
+    if (network->ssid[0] == '\0' && is_bssid_any(network->bssid))
+    {
+        wlcm_e("SSID or BSSID is required");
+        return -WM_E_INVAL;
+    }
+
+    if ((network->role == WLAN_BSS_ROLE_UAP) && (network->ip.ipv4.gw != network->ip.ipv4.address))
+    {
+        wlcm_e("IP address and Default gateway must be same for uAP");
+        return -WM_E_INVAL;
+    }
+
+    /* Always set PMF capable by default for sae conditions */
+    if(network->security.type != WLAN_SECURITY_WPA2 || network->security.mfpc == -1)
+        network->security.mfpc = 1;
+
+    /* Always set mfpc 0  by default for WPA/OPEN/WPA-WPA2 Mixed conditions */
+    if(network->security.type == WLAN_SECURITY_NONE || network->security.type == WLAN_SECURITY_WPA
+        || network->security.type == WLAN_SECURITY_WPA_WPA2_MIXED)
+        network->security.mfpc = 0;
+
+    if(network->security.mfpr == -1)
+        network->security.mfpr = 0;
+
+    if (((network->role == WLAN_BSS_ROLE_UAP) || (network->role == WLAN_BSS_ROLE_STA)) &&
+        ((network->security.type == WLAN_SECURITY_WPA3_SAE)
+        || (network->security.type == WLAN_SECURITY_WPA3_SAE_EXT_KEY)
+#if CONFIG_DRIVER_OWE
+         || (network->security.type == WLAN_SECURITY_OWE_ONLY)
+#endif
+         ))
+    {
+        network->security.mfpr = 1;
+    }
+
+#if CONFIG_WPA2_ENTP
+    /* make sure that if in policy wireless connection is allowed
+     * only with WPA2 Enterprise AP then add the network
+     */
+    if ((network->role == WLAN_BSS_ROLE_STA) &&
+        ((network->security.type != WLAN_SECURITY_EAP_TLS) ||
+         (network->security.type != WLAN_SECURITY_EAP_PEAP_MSCHAPV2)) &&
+        wlan.allow_wpa2_enterprise_ap_only)
+    {
+        return -WM_E_INVAL;
+    }
+#endif
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+    if ((is_ep_valid_security(network->security.type)) && ((network->security.wpa3_sb == 1U) || (network->security.wpa3_sb_192 == 1U)))
+    {
+        network->security.mfpr = 1;
+    }
+#endif
+#endif
+
+#if CONFIG_11R
+    if ((network->role == WLAN_BSS_ROLE_STA) &&
+            ((network->security.type == WLAN_SECURITY_WPA2_FT)
+#if CONFIG_WPA_SUPP
+             || (network->security.type == WLAN_SECURITY_WPA3_FT_SAE)
+#endif
+            ) && (network->channel != 0U))
+    {
+        wlcm_e("Specific channel not allowed in FT security");
+        return -WM_E_INVAL;
+    }
+#endif
+
+    if (!is_valid_security(network->security.type))
+    {
+        wlcm_e("Invalid security type is configured");
+        return -WM_E_INVAL;
+    }
+
+    if (network->security.key_mgmt == 0)
+    {
+        if (network->security.type == WLAN_SECURITY_NONE)
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_NONE;
+        }
+        else if ((network->security.type == WLAN_SECURITY_WPA) || (network->security.type == WLAN_SECURITY_WPA2) || (network->security.type == WLAN_SECURITY_WPA_WPA2_MIXED))
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_PSK;
+        }
+        else if (network->security.type == WLAN_SECURITY_WPA3_SAE)
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_SAE;
+        }
+        else if (network->security.type == WLAN_SECURITY_WPA3_SAE_EXT_KEY)
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_SAE_EXT_KEY;
+        }
+#if CONFIG_DRIVER_OWE
+        else if (network->security.type == WLAN_SECURITY_OWE_ONLY)
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_OWE;
+        }
+#endif
+#if CONFIG_11R
+        else if (network->security.type == WLAN_SECURITY_WPA2_FT)
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_FT_PSK;
+        }
+#if CONFIG_WPA_SUPP
+        else if (network->security.type == WLAN_SECURITY_WPA3_FT_SAE)
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_FT_SAE;
+        }
+#endif
+#endif
+        else if (network->security.type == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED)
+        {
+            network->security.key_mgmt = WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_SAE;
+        }
+    }
+
+    if ((network->role == WLAN_BSS_ROLE_UAP) || (network->role == WLAN_BSS_ROLE_STA))
+    {
+        if (network->role == WLAN_BSS_ROLE_STA)
+        {
+            if ((network->security.type == WLAN_SECURITY_WPA2) && (network->security.mfpc))
+            {
+                network->security.key_mgmt |= WLAN_KEY_MGMT_PSK_SHA256;
+            }
+            if ((network->security.type == WLAN_SECURITY_WPA_WPA2_MIXED) && (network->security.mfpr))
+            {
+                network->security.key_mgmt |= WLAN_KEY_MGMT_PSK_SHA256;
+            }
+	}
+        if (network->role == WLAN_BSS_ROLE_UAP)
+        {
+            if ((network->security.type == WLAN_SECURITY_WPA2) && (network->security.mfpr))
+            {
+                network->security.key_mgmt |= WLAN_KEY_MGMT_PSK_SHA256;
+            }
+        }
+    }
+
+    if (((network->role == WLAN_BSS_ROLE_UAP) || (network->role == WLAN_BSS_ROLE_STA)) &&
+        ((((network->security.type == WLAN_SECURITY_WPA) || (network->security.type == WLAN_SECURITY_WPA2) || (network->security.type == WLAN_SECURITY_WPA_WPA2_MIXED)) &&
+        (!wlan_key_mgmt_wpa_psk(network->security.key_mgmt)))
+#if CONFIG_11R
+        || ((network->security.type == WLAN_SECURITY_WPA2_FT) && (!wlan_key_mgmt_ft_psk(network->security.key_mgmt)))
+#endif
+        || ((network->security.type == WLAN_SECURITY_WPA3_SAE) && (!wlan_key_mgmt_sae(network->security.key_mgmt)))
+        || ((network->security.type == WLAN_SECURITY_WPA3_SAE_EXT_KEY) && (!wlan_key_mgmt_sae(network->security.key_mgmt)))
+#if CONFIG_WPA_SUPP
+#if CONFIG_11R
+        || ((network->security.type == WLAN_SECURITY_WPA3_FT_SAE) && (!wlan_key_mgmt_ft_sae(network->security.key_mgmt)))
+#endif
+#endif
+        || ((network->security.type == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED) && (!wlan_key_mgmt_wpa_psk_sae(network->security.key_mgmt)))
+#if CONFIG_DRIVER_OWE
+        || ((network->security.type == WLAN_SECURITY_OWE_ONLY) && (!wlan_key_mgmt_owe(network->security.key_mgmt)))
+#endif
+#if CONFIG_WPA_SUPP_DPP
+        || ((network->security.type == WLAN_SECURITY_DPP) && (!wlan_key_mgmt_dpp(network->security.key_mgmt)))
+#endif
+        ))
+    {
+        wlcm_e("Invalid security/key mgmt is configured");
+        return -WM_E_INVAL;
+    }
+
+    if (((network->role == WLAN_BSS_ROLE_UAP) || (network->role == WLAN_BSS_ROLE_STA)) &&
+        (network->security.key_mgmt == WLAN_KEY_MGMT_PSK_SHA256) &&
+        (!network->security.mfpc && !network->security.mfpr))
+    {
+        wlcm_e("MFP is not configured");
+        return -WM_E_INVAL;
+    }
+
+    if (((network->role == WLAN_BSS_ROLE_UAP) || (network->role == WLAN_BSS_ROLE_STA)) &&
+        (network->security.type == WLAN_SECURITY_WPA2_WPA3_SAE_MIXED) &&
+        (!(network->security.mfpc && !network->security.mfpr)))
+    {
+        wlcm_e("MFP capable only is allowed");
+        return -WM_E_INVAL;
+    }
+
+    if (wlan_is_key_valid(network) == false)
+    {
+        wlcm_e("Invalid passphrase/password is configured");
+        return -WM_E_INVAL;
+    }
+
+    /* Make sure network type is set correctly if not
+     * set correct values as per role*/
+    if ((network->type == WLAN_BSS_TYPE_STA) || (network->type == WLAN_BSS_TYPE_ANY))
+    {
+        if (network->role == WLAN_BSS_ROLE_UAP)
+        {
+            network->type = WLAN_BSS_TYPE_UAP;
+#if CONFIG_WPA_SUPP
+            netif = net_get_uap_interface();
+#endif
+        }
+        else if (network->role == WLAN_BSS_ROLE_STA)
+        {
+            network->type = WLAN_BSS_TYPE_STA;
+#if CONFIG_WPA_SUPP
+            netif = net_get_sta_interface();
+#endif
+        }
+        else
+        { /* Do Nothing */
+        }
+    }
+
+    if (network->role == WLAN_BSS_ROLE_UAP)
+    {
+#if CONFIG_WIFI_CAPA
+        if (network->channel != 14)
+        {
+        /* If no capability was configured, set capa up to 11ax by default */
+        if (!network->wlan_capa)
+            network->wlan_capa =
+#if CONFIG_11AX
+                WIFI_SUPPORT_11AX |
+#endif
+#if CONFIG_11AC
+                WIFI_SUPPORT_11AC |
+#endif
+                WIFI_SUPPORT_11N | WIFI_SUPPORT_LEGACY;
+        }
+        else
+        {
+            network->wlan_capa = WIFI_SUPPORT_LEGACY;
+        }
+
+#if CONFIG_11AX
+        network->dot11ax = wlan_11ax_allowed(network);
+#endif
+#if CONFIG_11AC
+        network->dot11ac = wlan_11ac_allowed(network);
+#endif
+        network->dot11n = wlan_11n_allowed(network);
+#else
+        if (network->channel != 14)
+        {
+#if CONFIG_11AX
+        network->dot11ax = 1;
+#endif
+#if CONFIG_11AC
+        network->dot11ac = 1;
+#endif
+        network->dot11n = 1;
+        }
+#endif
+    }
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+    if (network->role == WLAN_BSS_ROLE_UAP)
+    {
+
+        if (network->ht_capab == 0)
+        {
+            network->ht_capab = wifi_get_default_ht_capab();
+        }
+#if CONFIG_11AC
+        if (network->vht_capab == 0)
+        {
+            network->vht_capab = wifi_get_default_vht_capab();
+        }
+        if (network->vht_oper_chwidth == 0)
+        {
+            network->vht_oper_chwidth = 1;
+        }
+#endif
+#if CONFIG_11AX
+        if (network->he_oper_chwidth == 0)
+        {
+            network->he_oper_chwidth = 1;
+        }
+#endif
+    }
+#endif
+    if (network->security.sae_groups == NULL)
+    {
+        network->security.sae_groups = wlan_string_dup("19");
+    }
+#if CONFIG_DRIVER_OWE
+    if (network->security.owe_groups == NULL)
+    {
+        network->security.owe_groups = wlan_string_dup("19");
+    }
+#endif
+    if (network->security.group_cipher == 0)
+    {
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+        if (network->security.wpa3_sb_192 == 1U)
+        {
+            network->security.group_cipher = WLAN_CIPHER_GCMP_256;
+        }
+        else if (network->security.wpa3_sb == 1U)
+        {
+            network->security.group_cipher = WLAN_CIPHER_GCMP;
+        }
+        else
+#endif
+        {
+            network->security.group_cipher = WLAN_CIPHER_CCMP;
+        }
+    }
+    else
+    {
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+        if (network->security.wpa3_sb_192 == 1U)
+        {
+            if (network->security.group_cipher != WLAN_CIPHER_GCMP_256)
+            {
+                wlcm_e("Group cipher configuration not allowed");
+                goto INVAL;
+            }
+        }
+        else if (network->security.wpa3_sb == 1U)
+        {
+            if (network->security.group_cipher != WLAN_CIPHER_GCMP)
+            {
+                wlcm_e("Group cipher configuration not allowed");
+                goto INVAL;
+            }
+        }
+        else
+#endif
+            if (network->security.type != WLAN_SECURITY_NONE)
+        {
+                if ((network->security.group_cipher != WLAN_CIPHER_CCMP) && (network->security.group_cipher != WLAN_CIPHER_TKIP))
+                {
+                    wlcm_e("Group cipher configuration not allowed");
+                    goto INVAL;
+                }
+        }
+        else
+        {
+            wlcm_e("Group cipher configuration not allowed");
+            goto INVAL;
+        }
+    }
+
+    if (network->security.pairwise_cipher == 0)
+    {
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+        if (network->security.wpa3_sb_192 == 1U)
+        {
+            network->security.pairwise_cipher = WLAN_CIPHER_GCMP_256;
+        }
+        else if (network->security.wpa3_sb == 1U)
+        {
+            network->security.pairwise_cipher = WLAN_CIPHER_GCMP;
+        }
+        else
+#endif
+        {
+            network->security.pairwise_cipher = WLAN_CIPHER_CCMP;
+        }
+    }
+    else
+    {
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+        if (network->security.wpa3_sb_192 == 1U)
+        {
+            if (network->security.pairwise_cipher != WLAN_CIPHER_GCMP_256)
+            {
+                wlcm_e("Pairwise cipher configuration not allowed");
+                goto INVAL;
+            }
+        }
+        else if (network->security.wpa3_sb == 1U)
+        {
+            if (network->security.pairwise_cipher != WLAN_CIPHER_GCMP)
+            {
+                wlcm_e("Pairwise cipher configuration not allowed");
+                goto INVAL;
+            }
+        }
+        else
+#endif
+            if (network->security.type != WLAN_SECURITY_NONE)
+        {
+                if ((network->security.pairwise_cipher != WLAN_CIPHER_CCMP) && (network->security.pairwise_cipher != WLAN_CIPHER_TKIP))
+                {
+                    wlcm_e("Pairwise cipher configuration not allowed");
+                    goto INVAL;
+                }
+        }
+        else
+        {
+            wlcm_e("Pairwise cipher configuration not allowed");
+            goto INVAL;
+        }
+    }
+
+    if (network->security.group_mgmt_cipher == 0)
+    {
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+        if (network->security.wpa3_sb_192 == 1U)
+        {
+            network->security.group_mgmt_cipher = WLAN_CIPHER_BIP_GMAC_256;
+        }
+        else if (network->security.wpa3_sb == 1U)
+        {
+            network->security.group_mgmt_cipher = WLAN_CIPHER_BIP_GMAC_128;
+        }
+        else
+#endif
+        {
+            network->security.group_mgmt_cipher = WLAN_CIPHER_AES_128_CMAC;
+        }
+    }
+    else
+    {
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+        if (network->security.wpa3_sb_192 == 1U)
+        {
+            if (network->security.group_mgmt_cipher != WLAN_CIPHER_BIP_GMAC_256)
+            {
+                wlcm_e("Group mgmt cipher configuration not allowed");
+                goto INVAL;
+            }
+        }
+        else if (network->security.wpa3_sb == 1U)
+        {
+            if (network->security.group_mgmt_cipher != WLAN_CIPHER_BIP_GMAC_128)
+            {
+                wlcm_e("Group mgmt cipher configuration not allowed");
+                goto INVAL;
+            }
+        }
+        else
+#endif
+            if (network->security.type != WLAN_SECURITY_NONE)
+        {
+                if (network->security.group_mgmt_cipher != WLAN_CIPHER_AES_128_CMAC)
+                {
+                    wlcm_e("Group mgmt cipher configuration not allowed");
+                    goto INVAL;
+                }
+        }
+        else
+        {
+            wlcm_e("Group mgmt cipher configuration not allowed");
+            goto INVAL;
+        }
+    }
+
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+    if (
+#if CONFIG_EAP_TLS
+            (wlan_is_eap_tls_security(network->security.type)) ||
+#endif
+#if CONFIG_EAP_TTLS
+            (wlan_is_eap_ttls_security(network->security.type)) ||
+#endif
+#if CONFIG_EAP_PEAP
+            (wlan_is_eap_peap_security(network->security.type)) ||
+#endif
+#if CONFIG_EAP_FAST
+            (wlan_is_eap_fast_security(network->security.type)) ||
+#endif
+            false)
+    {
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+        if (network->role == WLAN_BSS_ROLE_UAP)
+        {
+            /* Specify CA certificate */
+            network->security.ca_cert_len =
+                wlan_get_entp_cert_files(FILE_TYPE_ENTP_CA_CERT, &network->security.ca_cert_data);
+            if (network->security.ca_cert_len == 0)
+            {
+                wlan_free_entp_cert_files();
+                wlcm_e("CA cert is not configured");
+                goto INVAL;
+            }
+
+            /* Specify Server certificate */
+            network->security.server_cert_len =
+                wlan_get_entp_cert_files(FILE_TYPE_ENTP_SERVER_CERT, &network->security.server_cert_data);
+            if (network->security.server_cert_len == 0)
+            {
+                wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                OSA_MemoryFree(network->security.ca_cert_data);
+#endif
+                wlcm_e("Server cert is not configured");
+                goto INVAL;
+            }
+            /* Specify Server key */
+            network->security.server_key_len =
+                wlan_get_entp_cert_files(FILE_TYPE_ENTP_SERVER_KEY, &network->security.server_key_data);
+            if (network->security.server_key_len == 0)
+            {
+                wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                OSA_MemoryFree(network->security.ca_cert_data);
+                OSA_MemoryFree(network->security.server_cert_data);
+#endif
+                wlcm_e("Server key is not configured");
+                goto INVAL;
+            }
+            /* Specify DH params */
+            network->security.dh_len = wlan_get_entp_cert_files(FILE_TYPE_ENTP_DH_PARAMS, &network->security.dh_data);
+            if (network->security.dh_len == 0)
+            {
+                wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                OSA_MemoryFree(network->security.ca_cert_data);
+                OSA_MemoryFree(network->security.server_cert_data);
+                OSA_MemoryFree(network->security.server_key_data);
+#endif
+                wlcm_e("DH params are not configured");
+                goto INVAL;
+            }
+
+#if CONFIG_EAP_FAST
+            if (wlan_is_eap_fast_security(network->security.type))
+            {
+                if (strlen(network->security.pac_opaque_encr_key) != (PAC_OPAQUE_ENCR_KEY_MAX_LENGTH - 1))
+                {
+                    wlcm_e("Invalid PAC Opaque Encryption key");
+                    goto INVAL;
+                }
+                if (strlen(network->security.a_id) != (A_ID_MAX_LENGTH - 1))
+                {
+                    wlcm_e("Invalid authority identity(a_id)");
+                    goto INVAL;
+                }
+            }
+#endif
+        }
+        else
+#endif
+#endif
+        {
+            if (false == wlan_is_skip_cert_cfg(network->security.type))
+            {
+                /* Specify CA certificate */
+                network->security.ca_cert_len =
+                    wlan_get_entp_cert_files(FILE_TYPE_ENTP_CA_CERT, &network->security.ca_cert_data);
+                if (network->security.ca_cert_len == 0)
+                {
+                    wlan_free_entp_cert_files();
+                    wlcm_e("CA cert is not configured");
+                    goto INVAL;
+                }
+
+                /* Specify Client certificate */
+                network->security.client_cert_len =
+                    wlan_get_entp_cert_files(FILE_TYPE_ENTP_CLIENT_CERT, &network->security.client_cert_data);
+                if (network->security.client_cert_len == 0)
+                {
+                    wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                    OSA_MemoryFree(network->security.ca_cert_data);
+#endif
+                    wlcm_e("Client cert is not configured");
+                    goto INVAL;
+                }
+                /* Specify Client key */
+                network->security.client_key_len =
+                    wlan_get_entp_cert_files(FILE_TYPE_ENTP_CLIENT_KEY, &network->security.client_key_data);
+                if (network->security.client_key_len == 0)
+                {
+                    wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                    OSA_MemoryFree(network->security.ca_cert_data);
+                    OSA_MemoryFree(network->security.client_cert_data);
+#endif
+                    wlcm_e("Client key is not configured");
+                    goto INVAL;
+                }
+            }
+        }
+#ifdef CONFIG_EAP_TTLS
+        if (WLAN_SECURITY_EAP_TTLS == network->security.type)
+        {
+            if (network->role == WLAN_BSS_ROLE_STA)
+            {
+
+                /* Specify CA certificate2 */
+                network->security.ca_cert2_len =
+                    wlan_get_entp_cert_files(FILE_TYPE_ENTP_CA_CERT2, &network->security.ca_cert2_data);
+                if (network->security.ca_cert2_len == 0)
+                {
+                    wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                    OSA_MemoryFree(network->security.ca_cert_data);
+                    OSA_MemoryFree(network->security.client_cert_data);
+                    OSA_MemoryFree(network->security.client_key_data);
+#endif
+                    wlcm_e("CA cert2 is not configured");
+                    goto INVAL;
+                }
+                /* Specify Client certificate2 */
+                network->security.client_cert2_len =
+                    wlan_get_entp_cert_files(FILE_TYPE_ENTP_CLIENT_CERT, &network->security.client_cert2_data);
+                if (network->security.client_cert2_len == 0)
+                {
+                    wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                    OSA_MemoryFree(network->security.ca_cert_data);
+                    OSA_MemoryFree(network->security.client_cert_data);
+                    OSA_MemoryFree(network->security.client_key_data);
+                    OSA_MemoryFree(network->security.ca_cert2_data);
+#endif
+                    wlcm_e("Client cert2 is not configured");
+                    goto INVAL;
+                }
+                /* Specify Client key2 */
+                network->security.client_key2_len =
+                    wlan_get_entp_cert_files(FILE_TYPE_ENTP_CLIENT_KEY, &network->security.client_key2_data);
+                if (network->security.client_key_len == 0)
+                {
+                    wlan_free_entp_cert_files();
+#if CONFIG_WIFI_USB_FILE_ACCESS
+                    OSA_MemoryFree(network->security.ca_cert_data);
+                    OSA_MemoryFree(network->security.client_cert_data);
+                    OSA_MemoryFree(network->security.client_key_data);
+                    OSA_MemoryFree(network->security.ca_cert2_data);
+                    OSA_MemoryFree(network->security.client_cert2_data);
+#endif
+                    wlcm_e("Client key2 is not configured");
+                    goto INVAL;
+                }
+            }
+        }
+#endif
+    }
+#endif
+#endif
+    /* Find a slot for the new network but check all existing networks in
+     * case the new one has a duplicate name, which is not allowed. */
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0')
+        {
+            if (strlen(wlan.networks[i].name) == len && !strncmp(wlan.networks[i].name, network->name, len))
+            {
+                goto INVAL;
+            }
+        }
+        else if (pos == -1)
+        {
+            pos = i;
+        }
+        else
+        { /* Do Nothing */
+        }
+    }
+#if CONFIG_WPA_SUPP
+    if (pos < 0)
+    {
+        if (network->security.sae_groups)
+        {
+            OSA_MemoryFree(network->security.sae_groups);
+            network->security.sae_groups = NULL;
+        }
+#if CONFIG_DRIVER_OWE
+        if (network->security.owe_groups)
+        {
+            OSA_MemoryFree(network->security.owe_groups);
+            network->security.owe_groups = NULL;
+        }
+#endif
+        return -WM_E_NOMEM;
+    }
+#endif
+
+    wlan.networks[pos].dtim_period = network->dtim_period;
+    wlan.networks[pos].acs_band    = network->acs_band;
+    /* save and set private fields */
+    (void)memcpy((void *)&wlan.networks[pos], (const void *)network, sizeof(struct wlan_network));
+    wlan.networks[pos].ssid_specific    = (uint8_t)(network->ssid[0] != '\0');
+    wlan.networks[pos].bssid_specific   = (uint8_t)!is_bssid_any(network->bssid);
+    wlan.networks[pos].channel_specific = (uint8_t)(network->channel != 0U);
+    if (wlan.networks[pos].channel_specific == 1U)
+    {
+#if CONFIG_5GHz_SUPPORT
+        if (network->channel > MAX_CHANNELS_BG)
+        {
+            wlan.networks[pos].acs_band    = 1;
+        }
+        else
+#endif
+        {
+            wlan.networks[pos].acs_band    = 0;
+        }
+    }
+
+    if (network->security.type != WLAN_SECURITY_WILDCARD)
+    {
+        wlan.networks[pos].security_specific = 1;
+    }
+
+#if !CONFIG_WPA_SUPP
+    if ((network->role == WLAN_BSS_ROLE_STA) &&
+        (network->security.type != WLAN_SECURITY_NONE && network->security.type != WLAN_SECURITY_WEP_OPEN))
+    {
+        ret = wifi_send_clear_wpa_psk((int)network->role, network->ssid);
+        if (ret != WM_SUCCESS)
+        {
+            return WLAN_ERROR_ACTION;
+        }
+    }
+#endif
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    if (!wlan.wps_session_attempt)
+    {
+#endif
+        ret = wpa_supp_add_network(netif, &wlan.networks[pos]);
+        if (ret < 0)
+        {
+            wlan_remove_network(wlan.networks[pos].name);
+            return -WM_E_NOMEM;
+        }
+#if CONFIG_WPA_SUPP_WPS
+    }
+#endif
+#endif
+
+    wlan.num_networks++;
+
+    return WM_SUCCESS;
+
+INVAL:
+#if CONFIG_WPA_SUPP
+    if (network->security.sae_groups)
+    {
+        OSA_MemoryFree(network->security.sae_groups);
+        network->security.sae_groups = NULL;
+    }
+#if CONFIG_DRIVER_OWE
+    if (network->security.owe_groups)
+    {
+        OSA_MemoryFree(network->security.owe_groups);
+        network->security.owe_groups = NULL;
+    }
+#endif
+#endif
+    return -WM_E_INVAL;
+}
+
+#if CONFIG_WIFI_CAPA
+uint8_t wlan_check_11n_capa(unsigned int channel)
+{
+    uint8_t enable_11n = false;
+    uint16_t fw_bands  = 0U;
+
+    wifi_get_fw_info(MLAN_BSS_TYPE_UAP, &fw_bands);
+
+    if (channel > 14 && (fw_bands & BAND_AN))
+    {
+        enable_11n = true;
+    }
+    else if (channel <= 14 && (fw_bands & BAND_GN))
+    {
+        enable_11n = true;
+    }
+    return enable_11n;
+}
+
+uint8_t wlan_check_11ac_capa(unsigned int channel)
+{
+    uint8_t enable_11ac = false;
+    uint16_t fw_bands   = 0U;
+
+    wifi_get_fw_info(MLAN_BSS_TYPE_UAP, &fw_bands);
+
+#if CONFIG_11AC
+    if (channel > 14 && (fw_bands & BAND_AAC))
+    {
+        enable_11ac = true;
+    }
+    else if (channel <= 14 && (fw_bands & BAND_GAC))
+    {
+        enable_11ac = true;
+    }
+#endif
+    return enable_11ac;
+}
+
+uint8_t wlan_check_11ax_capa(unsigned int channel)
+{
+    uint8_t enable_11ax = false;
+    uint16_t fw_bands   = 0U;
+
+    wifi_get_fw_info(MLAN_BSS_TYPE_UAP, &fw_bands);
+
+#if CONFIG_11AX
+    if (channel > 14 && (fw_bands & BAND_AAX))
+    {
+        enable_11ax = true;
+    }
+    else if (channel <= 14 && (fw_bands & BAND_GAX))
+    {
+        enable_11ax = true;
+    }
+#endif
+    return enable_11ax;
+}
+#endif
+
+int wlan_remove_network(const char *name)
+{
+    unsigned int len, i;
+#if CONFIG_WPA_SUPP
+    int ret = -WM_E_INVAL;
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+    if (!is_running())
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    if (name == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    len = strlen(name);
+
+    /* find the first network whose name matches and clear it out */
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0' && strlen(wlan.networks[i].name) == len &&
+            !strncmp(wlan.networks[i].name, name, len))
+        {
+            if (false == wlan_in_reset)
+            {
+                if (wlan.running && wlan.cur_network_idx == i)
+                {
+                    return WLAN_ERROR_STATE;
+                }
+                if (wlan.cur_uap_network_idx == i)
+                {
+                    return WLAN_ERROR_STATE;
+                }
+            }
+#if CONFIG_WPA2_ENTP
+            if (wlan.networks[i].security.tls_cert.ca_chain)
+            {
+                wm_mbedtls_free_cert(wlan.networks[i].security.tls_cert.ca_chain);
+            }
+            if (wlan.networks[i].security.tls_cert.own_cert)
+            {
+                wm_mbedtls_free_cert(wlan.networks[i].security.tls_cert.own_cert);
+            }
+            if (wlan.networks[i].security.tls_cert.own_key)
+            {
+                wm_mbedtls_free_key(wlan.networks[i].security.tls_cert.own_key);
+            }
+#endif
+#if CONFIG_WPA_SUPP
+            if (wlan.networks[i].role == WLAN_BSS_ROLE_STA)
+            {
+                netif = net_get_sta_interface();
+            }
+            else if (wlan.networks[i].role == WLAN_BSS_ROLE_UAP)
+            {
+                netif = net_get_uap_interface();
+            }
+            else
+            {
+                /* Do nothing */
+            }
+            wpa_supp_remove_network(netif, &wlan.networks[i]);
+
+            if (wlan.networks[i].security.sae_groups)
+            {
+                OSA_MemoryFree(wlan.networks[i].security.sae_groups);
+                wlan.networks[i].security.sae_groups = NULL;
+            }
+#if CONFIG_DRIVER_OWE
+            if (wlan.networks[i].security.owe_groups)
+            {
+                OSA_MemoryFree(wlan.networks[i].security.owe_groups);
+                wlan.networks[i].security.owe_groups = NULL;
+            }
+#endif
+#if CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE
+#if CONFIG_WIFI_USB_FILE_ACCESS
+            if (wlan.networks[i].role == WLAN_BSS_ROLE_STA)
+            {
+                if (wlan.networks[i].security.ca_cert_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.ca_cert_data);
+                }
+                if (wlan.networks[i].security.client_cert_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.client_cert_data);
+                }
+                if (wlan.networks[i].security.client_key_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.client_key_data);
+                }
+                if (wlan.networks[i].security.ca_cert2_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.ca_cert2_data);
+                }
+                if (wlan.networks[i].security.client_cert2_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.client_cert2_data);
+                }
+                if (wlan.networks[i].security.client_key2_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.client_key2_data);
+                }
+            }
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+            else if (wlan.networks[i].role == WLAN_BSS_ROLE_UAP)
+            {
+                if (wlan.networks[i].security.ca_cert_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.ca_cert_data);
+                }
+                if (wlan.networks[i].security.server_cert_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.server_cert_data);
+                }
+                if (wlan.networks[i].security.server_key_data)
+                {
+                    OSA_MemoryFree(wlan.networks[i].security.server_key_data);
+                }
+            }
+#endif
+#endif
+#endif
+#endif
+#if CONFIG_WPA_SUPP_DPP
+            if (wlan.networks[i].security.dpp_connector)
+            {
+                OSA_MemoryFree(wlan.networks[i].security.dpp_connector);
+            }
+            if (wlan.networks[i].security.dpp_c_sign_key)
+            {
+                OSA_MemoryFree(wlan.networks[i].security.dpp_c_sign_key);
+            }
+            if (wlan.networks[i].security.dpp_net_access_key)
+            {
+                OSA_MemoryFree(wlan.networks[i].security.dpp_net_access_key);
+            }
+#endif
+#endif
+            (void)memset(&wlan.networks[i], 0, sizeof(struct wlan_network));
+            wlan.num_networks--;
+            return WM_SUCCESS;
+        }
+    }
+    /* network name wasn't found */
+    return -WM_E_INVAL;
+}
+
+int wlan_get_network_count(unsigned int *count)
+{
+    if (count == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    *count = wlan.num_networks;
+    return WM_SUCCESS;
+}
+
+int wlan_get_current_network(struct wlan_network *network)
+{
+    short rssi;
+    int snr;
+
+    if (network == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED) || is_state(CM_STA_AUTHENTICATED)))
+    {
+        (void)memcpy((void *)network, (const void *)&wlan.networks[wlan.cur_network_idx], sizeof(struct wlan_network));
+
+        wlan_get_current_signal_strength(&rssi, &snr);
+
+        network->rssi = rssi;
+
+        return WM_SUCCESS;
+    }
+
+    return WLAN_ERROR_STATE;
+}
+
+int wlan_get_current_network_ssid(char *ssid)
+{
+    if (ssid == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED) || is_state(CM_STA_AUTHENTICATED)))
+    {
+        (void)memcpy((void *)ssid, (const void *)&wlan.networks[wlan.cur_network_idx].ssid, IEEEtypes_SSID_SIZE + 1);
+
+        return WM_SUCCESS;
+    }
+
+    return WLAN_ERROR_STATE;
+}
+
+int wlan_get_current_network_bssid(char *bssid)
+{
+    if (bssid == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+    {
+        (void)memcpy((void *)bssid, (const void *)&wlan.networks[wlan.cur_network_idx].bssid, IEEEtypes_ADDRESS_SIZE);
+
+        return WM_SUCCESS;
+    }
+
+    return WLAN_ERROR_STATE;
+}
+
+int wlan_get_current_uap_network(struct wlan_network *network)
+{
+    if (network == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (wlan.running && (is_uap_state(CM_UAP_IP_UP) || is_uap_state(CM_UAP_STARTED)))
+    {
+        (void)memcpy((void *)network, (const void *)&wlan.networks[wlan.cur_uap_network_idx],
+                     sizeof(struct wlan_network));
+        return WM_SUCCESS;
+    }
+    return WLAN_ERROR_STATE;
+}
+
+int wlan_get_current_uap_network_ssid(char *ssid)
+{
+    if (ssid == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (wlan.running && (is_uap_state(CM_UAP_IP_UP) || is_uap_state(CM_UAP_STARTED)))
+    {
+        (void)memcpy((void *)ssid, (const void *)&wlan.networks[wlan.cur_uap_network_idx].ssid, IEEEtypes_SSID_SIZE + 1);
+
+        return WM_SUCCESS;
+    }
+
+    return WLAN_ERROR_STATE;
+}
+
+#if CONFIG_SCAN_WITH_RSSIFILTER
+int wlan_set_rssi_threshold(int rssithr)
+{
+    if (rssithr)
+        wlan.networks[wlan.cur_network_idx].rssi_threshold = (rssithr < 0 ? rssithr : 0);
+
+    return WM_SUCCESS;
+}
+#endif
+
+bool is_uap_started(void)
+{
+    return is_uap_state(CM_UAP_IP_UP);
+}
+bool is_sta_connected(void)
+{
+    return (wlan.sta_state == CM_STA_CONNECTED);
+}
+
+bool is_sta_ipv4_connected(void)
+{
+    return (wlan.sta_ipv4_state == CM_STA_CONNECTED);
+}
+
+#if CONFIG_IPV6
+bool is_sta_ipv6_connected(void)
+{
+    return (wlan.sta_ipv6_state == CM_STA_CONNECTED);
+}
+#endif
+
+int wlan_get_network(unsigned int index, struct wlan_network *network)
+{
+    unsigned int i;
+    int pos = -1;
+
+    if (network == NULL || index > ARRAY_SIZE(wlan.networks))
+    {
+        return -WM_E_INVAL;
+    }
+
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        ++pos;
+        if (wlan.networks[i].name[0] != '\0' && pos == (int)index)
+        {
+            copy_network(network, &wlan.networks[i]);
+            return WM_SUCCESS;
+        }
+    }
+
+    return -WM_E_INVAL;
+}
+
+int wlan_get_current_nf(void)
+{
+    return -g_data_nf_last;
+}
+
+int wlan_get_current_signal_strength(short *rssi, int *snr)
+{
+    wifi_rssi_info_t rssi_info;
+    (void)wifi_send_rssi_info_cmd(&rssi_info);
+
+    *snr  = rssi_info.bcn_rssi_last - rssi_info.bcn_nf_last;
+    *rssi = rssi_info.bcn_rssi_last;
+    return WM_SUCCESS;
+}
+
+int wlan_get_average_signal_strength(short *rssi, int *snr)
+{
+    wifi_rssi_info_t rssi_info;
+    (void)wifi_send_rssi_info_cmd(&rssi_info);
+
+    *snr  = rssi_info.bcn_snr_avg;
+    *rssi = rssi_info.bcn_rssi_avg;
+    return WM_SUCCESS;
+}
+
+int wlan_get_current_rssi(short *rssi)
+{
+    g_rssi = (uint8_t)(g_data_snr_last - g_data_nf_last);
+    *rssi  = (short)(g_rssi - 256U);
+    return WM_SUCCESS;
+}
+
+int wlan_get_network_byname(char *name, struct wlan_network *network)
+{
+    unsigned int i;
+
+    if (network == NULL || name == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0' && !strcmp(wlan.networks[i].name, name))
+        {
+            copy_network(network, &wlan.networks[i]);
+            return WM_SUCCESS;
+        }
+    }
+
+    return -WM_E_INVAL;
+}
+
+int wlan_set_network_ip_byname(char *name, struct wlan_ip_config *ip)
+{
+    unsigned int i;
+
+    if (ip == NULL || name == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0' && !strcmp(wlan.networks[i].name, name))
+        {
+            memcpy(&(wlan.networks[i].ip), ip, sizeof(struct wlan_ip_config));
+            return WM_SUCCESS;
+        }
+    }
+
+    return -WM_E_INVAL;
+}
+
+int wlan_remove_all_network_profiles(void)
+{
+    unsigned int i;
+    int ret;
+
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0')
+        {
+            ret = wlan_remove_network(wlan.networks[i].name);
+            if (ret != WM_SUCCESS)
+            {
+                return -WM_E_INVAL;
+            }
+        }
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_disconnect(void)
+{
+    if (!wlan.running)
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+#if CONFIG_HOST_SLEEP
+    wakelock_get();
+#endif
+
+    (void)send_user_request(CM_STA_USER_REQUEST_DISCONNECT, 0);
+
+#if CONFIG_ECSA
+    /*Wait for sta to enter the disconnect state, and then send ECSA cmd*/
+    OSA_TimeDelay(1000);
+    wrapper_clear_media_connected_event();
+    wlan_switch_to_nondfs_channel();
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wlan_connect(char *name)
+{
+    unsigned int len = name != NULL ? strlen(name) : 0U;
+    int i            = 0, ret;
+
+    if (!wlan.running)
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    if (wlan.num_networks == 0U || len == 0U)
+    {
+        return -WM_E_INVAL;
+    }
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    if (wlan.wps_session_attempt)
+    {
+        wlcm_d("WPS session is in progress");
+        return WLAN_ERROR_STATE;
+    }
+#endif
+#endif
+
+    wlan.roam_reassoc = false;
+
+    /* connect to a specific network */
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0' && strlen(wlan.networks[i].name) == len &&
+            !strncmp(wlan.networks[i].name, name, len))
+        {
+            switch (wlan.networks[i].role)
+            {
+                case MLAN_BSS_ROLE_UAP:
+                    wlcm_e("Invalid bss role. Bss role is uap.");
+                    ret = WLAN_ERROR_PARAM;
+                    break;
+                case MLAN_BSS_ROLE_ANY:
+                    wlcm_e("Invalid bss role. Bss role is any.");
+                    ret = WLAN_ERROR_PARAM;
+                    break;
+                default:
+                    ret = WLAN_ERROR_NONE;
+                    break;
+            }
+
+            if(ret != WLAN_ERROR_NONE)
+                return ret;
+
+            wlcm_d("taking the scan lock (connect scan)");
+            dbg_lock_info();
+            ret = OSA_SemaphoreWait((osa_semaphore_handle_t)wlan.scan_lock, osaWaitForever_c);
+            if (ret != WM_SUCCESS)
+            {
+                wlcm_e("failed to get scan lock: 0x%X", ret);
+                return WLAN_ERROR_ACTION;
+            }
+            wlcm_d("got the scan lock (connect scan)");
+            wlan.is_scan_lock = 1;
+            /* Reset reassoc count as this is set to WLAN_RECONNECT_LIMIT
+             * during disconnect */
+            wlan.reassoc_count = 0;
+
+            return send_user_request(CM_STA_USER_REQUEST_CONNECT, i);
+        }
+    }
+
+    /* specified network was not found */
+    return -WM_E_INVAL;
+}
+
+int wlan_connect_opt(char *name, bool skip_dfs)
+{
+    int ret = 0;
+
+    mlan_adap->skip_dfs = false;
+    if(skip_dfs)
+        mlan_adap->skip_dfs = true;
+
+    ret = wlan_connect(name);
+    if(ret != WM_SUCCESS)
+    {
+        mlan_adap->skip_dfs = false;
+    }
+
+    return ret;
+}
+
+int wlan_reassociate(void)
+{
+    int ret;
+
+    if (!wlan.running)
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    if (wlan.num_networks == 0U)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (!is_sta_connected())
+    {
+        wlcm_d("Error: sta connection is required before sending reassociate request");
+        return WLAN_ERROR_STATE;
+    }
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+    if (wlan.wps_session_attempt)
+    {
+        wlcm_d("WPS session is in progress");
+        return WLAN_ERROR_STATE;
+    }
+#endif
+#endif
+
+    wlcm_d("taking the scan lock (reassociate scan)");
+    dbg_lock_info();
+    ret = OSA_SemaphoreWait((osa_semaphore_handle_t)wlan.scan_lock, osaWaitForever_c);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("failed to get scan lock: 0x%X", ret);
+        return WLAN_ERROR_ACTION;
+    }
+    wlcm_d("got the scan lock (reassociate scan)");
+    wlan.is_scan_lock = 1;
+
+    wlan.roam_reassoc = true;
+
+    ret = send_user_request(CM_STA_USER_REQUEST_CONNECT, wlan.cur_network_idx);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_d("Error: Reassociate failed");
+        wlan.roam_reassoc = false;
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan.scan_lock);
+        wlan.is_scan_lock = 0;
+    }
+
+    return ret;
+}
+
+int wlan_start_network(const char *name)
+{
+    unsigned int i;
+    unsigned int len;
+
+    if (name == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    len = strlen(name);
+    if (len == 0 || wlan.num_networks == 0U)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (is_uap_started() != 0)
+    {
+        wlcm_e(
+            "%s network cannot be started, "
+            "as the uAP is already running",
+            name);
+        return WLAN_ERROR_STATE;
+    }
+
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].name[0] != '\0' && strlen(wlan.networks[i].name) == len &&
+            !strncmp(wlan.networks[i].name, name, len) && (wlan.networks[i].role == WLAN_BSS_ROLE_UAP) &&
+            wlan.networks[i].ssid_specific)
+        {
+#if CONFIG_MULTI_CHAN
+            /* when multi-channel is enabled, uap and sta can start on different channel */
+            if (wifi_get_mc_policy() == 0)
+#endif
+            {
+                if ((wlan.networks[i].channel_specific) && (wlan.networks[i].channel != 0))
+                {
+                    wlcm_w(
+                        "NOTE: uAP will automatically switch to"
+                        " the channel that station is on.");
+                    if(is_sta_connected())
+                        wlan.networks[i].channel = wlan.networks[wlan.cur_network_idx].channel;
+                }
+            }
+            if (wlan.networks[i].role == WLAN_BSS_ROLE_UAP)
+            {
+                return send_user_request(CM_UAP_USER_REQUEST_START, i);
+            }
+        }
+    }
+
+    /* specified network was not found */
+    return -WM_E_INVAL;
+}
+
+int wlan_stop_network(const char *name)
+{
+    unsigned int i;
+    unsigned int len;
+
+    if (name == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    len = strlen(name);
+    if (len == 0U || wlan.num_networks == 0U)
+    {
+        return -WM_E_INVAL;
+    }
+
+    wlan_uap_scan_chan_list_set = false;
+    /* Search for matching SSID
+     * If found send stop request
+     */
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if ((wlan.networks[i].name[0] == '\0') || (strlen(wlan.networks[i].name) != len) ||
+            (strncmp(wlan.networks[i].name, name, len)) != 0)
+        {
+            continue;
+        }
+
+        if (wlan.networks[i].role == WLAN_BSS_ROLE_UAP && wlan.networks[i].ssid_specific)
+        {
+            net_interface_down(net_get_uap_handle());
+            return send_user_request(CM_UAP_USER_REQUEST_STOP, i);
+        }
+    } /* end of loop */
+    /* specified network was not found */
+    return -WM_E_INVAL;
+}
+
+#if defined(RW610)
+int wlan_remove_all_networks(void)
+{
+    void *intrfc_handle = NULL;
+    /* No need to remove net interfaces here, as they are added only once.
+     * Moreover, removing and adding net interface will increase netif_num cumulatively,
+     * which will mismatch with "ua2" during creating dhcpd.
+     */
+    wlan_in_reset = true;
+    wlan_remove_all_network_profiles();
+
+    intrfc_handle = net_get_sta_handle();
+    net_interface_down(intrfc_handle);
+
+    intrfc_handle = net_get_uap_handle();
+    net_interface_down(intrfc_handle);
+
+    return WM_SUCCESS;
+}
+
+void wlan_destroy_all_tasks(void)
+{
+    OSA_LockSchedule();
+
+    /* Destroy cm_main thread */
+    OSA_TaskDestroy((osa_task_handle_t)wlan.wlcmgr_task_Handle);
+
+#if CONFIG_WPS2
+    /* Destroy wps_main thread */
+    OSA_TaskDestroy((osa_task_handle_t)wlan_wps.wps_task_Handle);
+    OSA_SemaphoreDestroy((osa_semaphore_handle_t)wlan_wps.wps_scan_done);
+#endif
+
+    /* Destroy wifidriver thread */
+    wifi_destroy_wifidriver_tasks();
+
+    OSA_UnlockSchedule();
+}
+
+int wlan_imu_get_task_lock(void)
+{
+    return wifi_imu_get_task_lock();
+}
+
+int wlan_imu_put_task_lock(void)
+{
+    return wifi_imu_put_task_lock();
+}
+
+void wlan_reset(cli_reset_option ResetOption)
+{
+    if (OSA_MutexLock((osa_mutex_handle_t)reset_lock, 0) != WM_SUCCESS)
+    {
+        PRINTF("already in process...\r\n");
+        return;
+    }
+
+    if (ResetOption == CLI_DISABLE_WIFI || ResetOption == CLI_RESET_WIFI)
+    {
+        PRINTF("--- Disable WiFi ---\r\n");
+        if (wlan_is_started())
+        {
+#if CONFIG_HOST_SLEEP
+#if CONFIG_POWER_MANAGER
+            /* Reset host sleep state flag first */
+            wlan_host_sleep_state = HOST_SLEEP_DISABLE;
+#endif
+#endif
+#if (CONFIG_WPA_SUPP) && (CONFIG_UAP_STA_MAC_ADDR_FILTER)
+        wlan_set_sta_mac_filter(0, 0, NULL);
+#endif
+            /*Disconnect form AP if station is associated with an AP.*/
+            if (wlan.sta_state > CM_STA_ASSOCIATING)
+            {
+                wlan_disconnect();
+                while (wlan.sta_state != CM_STA_IDLE)
+                {
+                    OSA_TimeDelay(1000);
+                }
+            }
+
+            /*Stop current uAP if uAP is started.*/
+            if (wlan.uap_state > CM_UAP_CONFIGURED)
+            {
+                wlan_stop_network(wlan.networks[wlan.cur_uap_network_idx].name);
+                while (wlan.uap_state != CM_UAP_INITIALIZING)
+                {
+                    OSA_TimeDelay(1000);
+                }
+            }
+#if CONFIG_CPU_LOADING
+            if(cpu_loading.status != CPU_LOADING_STATUS_DEAD)
+                wlan_cpu_loading_stop();
+            while(cpu_loading.status != CPU_LOADING_STATUS_DEAD)
+            {
+                OSA_TimeDelay(50);
+            }
+#endif
+            /* Block TX data */
+            wifi_set_tx_status(WIFI_DATA_BLOCK);
+            /* Block RX data */
+            wifi_set_rx_status(WIFI_DATA_BLOCK);
+
+#ifndef __ZEPHYR__
+            /* DHCP Cleanup */
+            wlan_dhcp_cleanup();
+#endif
+#if CONFIG_NCP
+            /* Stop uap provisioning if it started */
+            if (uap_prov_deinit_cb)
+                uap_prov_deinit_cb();
+#endif
+            /* Stop and Remove all network interfaces */
+            wlan_remove_all_networks();
+
+            (void)net_wlan_deinit();
+
+            wifi_scan_stop();
+            mlan_adap->skip_dfs = false;
+            if (!wifi_fw_is_hang())
+                wifi_send_shutdown_cmd();
+
+#if CONFIG_WPA_SUPP
+            wifi_supp_deinit();
+            wpa_supp_deinit();
+#endif
+
+            /* wait for imu task done */
+            wlan_imu_get_task_lock();
+            /* Destroy all tasks before touch the global vars */
+            wlan_destroy_all_tasks();
+#if CONFIG_NCP
+            if (uap_prov_cleanup_cb)
+                uap_prov_cleanup_cb();
+#endif
+#if CONFIG_WPS2
+            wps_stop();
+#endif /* CONFIG_WPS2 */
+
+#if CONFIG_WPA2_ENTP
+            wlan_free_entp_cert_files();
+#endif
+
+            wlan_imu_put_task_lock();
+            /* Clear wlcmgr */
+            wlan_stop();
+        }
+        power_off_device(LOAD_WIFI_FIRMWARE);
+    }
+
+    if (ResetOption == CLI_ENABLE_WIFI || ResetOption == CLI_RESET_WIFI)
+    {
+        PRINTF("--- Enable WiFi ---\r\n");
+        if (!wlan_is_started())
+        {
+            PRINTF("Initialize WLAN Driver\r\n");
+            /* Initialize WIFI Driver */
+            if (WM_SUCCESS != (wlan_init(wlan_fw_bin, wlan_fw_bin_len)))
+            {
+                wlcm_e("wlan init failed\r\n");
+                OSA_MutexUnlock((osa_mutex_handle_t)reset_lock);
+                assert(0);
+                return;
+            }
+
+            if (WM_SUCCESS != (wlan_start(wlan_event_callback)))
+            {
+                wlcm_e("wlan start failed\r\n");
+                OSA_MutexUnlock((osa_mutex_handle_t)reset_lock);
+                return;
+            }
+
+            /* update the netif hwaddr after reset */
+            net_wlan_set_mac_address(&wlan.sta_mac[0], &wlan.uap_mac[0]);
+            /* Unblock TX data */
+            wifi_set_tx_status(WIFI_DATA_RUNNING);
+            /* Unblock RX data */
+            wifi_set_rx_status(WIFI_DATA_RUNNING);
+            wifi_tx_block_cnt = 0;
+            wifi_rx_block_cnt = 0;
+#if (CONFIG_WIFI_BLE_COEX_APP) && (CONFIG_WIFI_BLE_COEX_APP == 1)
+#if CONFIG_HOST_SLEEP
+#if CONFIG_POWER_MANAGER
+            /* Re-enable host sleep for coex app */
+            wlan_host_sleep_state = HOST_SLEEP_PERIODIC;
+#endif
+#endif
+#endif
+        }
+    }
+
+    OSA_MutexUnlock((osa_mutex_handle_t)reset_lock);
+
+    wlan_in_reset = false;
+    PRINTF("--- Done ---\r\n");
+}
+
+static void wlcmgr_mon_task(void * data)
+{
+#if CONFIG_HOST_SLEEP
+    int ret = 0;
+#endif
+    osa_status_t status;
+    struct wlan_message msg;
+
+#if CONFIG_POWER_MANAGER
+#if (!CONFIG_WIFI_BLE_COEX_APP) && (!CONFIG_NCP_BLE)
+    status = OSA_TimerCreate((osa_timer_handle_t)wake_timer, WAKE_TIMEOUT,
+                          &wake_timer_cb, NULL, KOSA_TimerOnce, OSA_TIMER_NO_ACTIVATE);
+    if (status != KOSA_StatusSuccess)
+    {
+        wlcm_e("Unable to create wake timer");
+    }
+#endif
+#endif
+    while (1)
+    {
+        status = OSA_MsgQGet((osa_msgq_handle_t)mon_thread_events, &msg, osaWaitForever_c);
+        if (status == KOSA_StatusSuccess)
+        {
+            /*Elements of wlan is not avaliable during wlan reset, so wait ending of wlan reset*/
+            while(wlan_in_reset)
+            {
+                OSA_TimeDelay(10);
+            }
+#if CONFIG_HOST_SLEEP
+            wlcm_d("got mon thread event: %d", msg.id);
+            if (msg.id == HOST_SLEEP_HANDSHAKE)
+            {
+                ret = wlan_send_host_sleep_int(wlan.wakeup_conditions, MFALSE);
+                if (ret != WM_SUCCESS)
+                {
+                   is_hs_handshake_done = WLAN_HOSTSLEEP_FAIL;
+                }
+            }
+            else if (msg.id == HOST_SLEEP_EXIT)
+            {
+#if CONFIG_POWER_MANAGER
+#if (!CONFIG_WIFI_BLE_COEX_APP) && (!CONFIG_NCP_BLE)
+                if(!wlan_is_manual && wlan_host_sleep_state == HOST_SLEEP_PERIODIC)
+                {
+                    wakelock_get();
+                    (void)OSA_TimerActivate((osa_timer_handle_t)wake_timer);
+                }
+#endif
+#endif
+                wlan_cancel_host_sleep();
+                /* Check fw status and write temperature to firmware after waking up */
+                temperature_mon_cb(NULL);
+                (void)OSA_TimerActivate((osa_timer_handle_t)temperature_mon_timer);
+            }
+#endif
+#if CONFIG_WIFI_RECOVERY
+            else if (msg.id == WIFI_RECOVERY_REQ)
+            {
+                wlan_reset(CLI_RESET_WIFI);
+                wifi_recovery_cnt ++;
+            }
+#endif
+        }
+        else
+        {
+            wlcm_e("Failed to get events from monitor task queue");
+        }
+    }
+}
+#endif // RW610
+
+#if CONFIG_NCP
+int wlan_stop_all_networks(void)
+{
+    wifi_scan_stop();
+
+    net_interface_down(net_get_sta_handle());
+    wlan_disconnect();
+
+    net_interface_down(net_get_uap_handle());
+    send_user_request(CM_UAP_USER_REQUEST_STOP, 0);
+
+    return WM_SUCCESS;
+}
+
+void wlan_register_uap_prov_deinit_cb(int (*cb)(void))
+{
+    uap_prov_deinit_cb = cb;
+}
+
+void wlan_register_uap_prov_cleanup_cb(void (*cb)(void))
+{
+    uap_prov_cleanup_cb = cb;
+}
+#endif
+
+int wlan_get_scan_result(unsigned int index, struct wlan_scan_result *res)
+{
+    struct wifi_scan_result2 *desc;
+
+    if (res == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (!is_running())
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    if (wifi_get_scan_result(index, &desc) != 0)
+    {
+        return -WM_FAIL;
+    }
+
+    (void)memset(res, 0, sizeof(struct wlan_scan_result));
+
+    (void)memcpy((void *)&res->bssid[0], (const void *)&desc->bssid[0], sizeof(res->bssid));
+    (void)memcpy((void *)&res->ssid[0], (const void *)((char *)&desc->ssid[0]), (size_t)desc->ssid_len);
+    res->ssid[desc->ssid_len] = (char)0;
+    res->ssid_len             = (size_t)desc->ssid_len;
+    res->channel              = desc->Channel;
+    res->beacon_period        = desc->beacon_period;
+    res->dtim_period          = desc->dtim_period;
+
+    if (!desc->is_ibss_bit_set)
+    {
+        res->role = WLAN_BSS_ROLE_STA;
+    }
+    res->dot11n = (uint8_t)desc->phtcap_ie_present;
+#if CONFIG_11AC
+    res->dot11ac = (uint8_t)desc->pvhtcap_ie_present;
+#endif
+#if CONFIG_11AX
+    res->dot11ax = (uint8_t)desc->phecap_ie_present;
+#endif
+
+    res->wmm = (uint8_t)desc->wmm_ie_present;
+#if (CONFIG_WPA_SUPP_WPS)
+    if (desc->wps_IE_exist == true)
+    {
+        res->wps         = desc->wps_IE_exist;
+        res->wps_session = desc->wps_session;
+    }
+#elif (CONFIG_WPS2)
+    if (desc->wps_IE_exist == true)
+        res->wps = desc->wps_IE_exist;
+    res->wps_session = desc->wps_session;
+#endif
+    if (desc->WPA_WPA2_WEP.wpa2_entp != 0U)
+    {
+        res->wpa2_entp = 1;
+    }
+    else if (desc->WPA_WPA2_WEP.wpa2_entp_sha256 != 0U)
+    {
+        res->wpa2_entp_sha256 = 1;
+    }
+    else if (desc->WPA_WPA2_WEP.wpa3_1x_sha256 != 0U)
+    {
+        res->wpa3_1x_sha256 = 1;
+    }
+    else if (desc->WPA_WPA2_WEP.wpa3_1x_sha384 != 0U)
+    {
+        res->wpa3_1x_sha384 = 1;
+    }
+    else
+    {
+        if (desc->WPA_WPA2_WEP.wpa != 0U)
+        {
+            res->wpa = 1;
+        }
+        if (desc->WPA_WPA2_WEP.wpa3_sae != 0U)
+        {
+            res->wpa3_sae = 1;
+        }
+        if (desc->WPA_WPA2_WEP.owe != 0U)
+        {
+#if CONFIG_DRIVER_OWE
+            res->owe = 1;
+#endif
+        }
+        if (desc->WPA_WPA2_WEP.wpa2 != 0U)
+        {
+            res->wpa2 = 1;
+        }
+        if (desc->WPA_WPA2_WEP.wpa2_sha256 != 0U)
+        {
+            res->wpa2_sha256 = 1;
+        }
+        if ((desc->WPA_WPA2_WEP.wepStatic != 0U) || (desc->WPA_WPA2_WEP.wepDynamic != 0U))
+        {
+            res->wep = 1;
+        }
+    }
+#if CONFIG_11R
+    if (res->wpa2_entp != 0U)
+    {
+        res->ft_1x = (t_u8)desc->WPA_WPA2_WEP.ft_1x;
+    }
+    if (res->wpa2 != 0U)
+    {
+        res->ft_psk = (t_u8)desc->WPA_WPA2_WEP.ft_psk;
+    }
+    if (res->wpa3_sae != 0U)
+    {
+        res->ft_sae = (t_u8)desc->WPA_WPA2_WEP.ft_sae;
+    }
+    if (res->wpa3_1x_sha384 != 0U)
+    {
+        res->ft_1x_sha384 = (t_u8)desc->WPA_WPA2_WEP.ft_1x_sha384;
+    }
+#endif
+    res->rssi = desc->RSSI;
+
+    (void)memcpy((void *)&res->trans_bssid[0], (const void *)&desc->trans_bssid[0], sizeof(res->trans_bssid));
+    (void)memcpy((void *)&res->trans_ssid[0], (const void *)((char *)&desc->trans_ssid[0]),
+                 (unsigned int)desc->trans_ssid_len);
+    res->trans_ssid[desc->trans_ssid_len] = (char)0;
+    res->trans_ssid_len                   = (unsigned int)desc->trans_ssid_len;
+
+#if CONFIG_11K
+    if (desc->neighbor_report_supported == true)
+    {
+        res->neighbor_report_supported = true;
+    }
+    else
+    {
+        res->neighbor_report_supported = false;
+    }
+#endif
+
+#if CONFIG_11V
+    if (desc->bss_transition_supported == true)
+    {
+        res->bss_transition_supported = true;
+    }
+    else
+    {
+        res->bss_transition_supported = false;
+    }
+#endif
+
+    res->ap_mfpc = desc->ap_mfpc;
+    res->ap_mfpr = desc->ap_mfpr;
+    res->ap_pwe = desc->ap_pwe;
+
+    return WM_SUCCESS;
+}
+
+void wlan_set_cal_data(const uint8_t *cal_data, const unsigned int cal_data_size)
+{
+    if (cal_data_size > 1)
+    {
+        wifi_set_cal_data(cal_data, cal_data_size);
+    }
+}
+
+int wlan_set_mac_addr(uint8_t *mac)
+{
+    uint8_t ap_mac[MLAN_MAC_ADDR_LENGTH];
+
+    if (!is_uap_state(CM_UAP_INITIALIZING) || is_sta_connecting())
+    {
+        return -WM_FAIL;
+    }
+
+    if (wlan.status == WLCMGR_INIT_DONE || wlan.status == WLCMGR_ACTIVATED)
+    {
+        (void)memcpy(ap_mac, mac, MLAN_MAC_ADDR_LENGTH);
+        ap_mac[4] += 1;
+
+        net_wlan_set_mac_address((unsigned char *)mac, (unsigned char *)ap_mac);
+
+        _wifi_set_mac_addr(mac, MLAN_BSS_TYPE_STA);
+
+        _wifi_set_mac_addr(&ap_mac[0], MLAN_BSS_TYPE_UAP);
+
+        /* save the sta mac */
+        (void)memcpy(&wlan.sta_mac[0], mac, MLAN_MAC_ADDR_LENGTH);
+        /* save the uap mac */
+        (void)memcpy(&wlan.uap_mac[0], &ap_mac[0], MLAN_MAC_ADDR_LENGTH);
+    }
+    else
+    {
+        wifi_set_mac_addr(mac);
+    }
+#if CONFIG_WPS2
+    (void)memcpy(wps_global.my_mac_addr, mac, MLAN_MAC_ADDR_LENGTH);
+    (void)memcpy(wps_global.l2->my_mac_addr, mac, MLAN_MAC_ADDR_LENGTH);
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wlan_set_uap_mac_addr(uint8_t *mac)
+{
+    /* Only suppoprt unicast mac */
+    if (mac[0] & 0x01)
+    {
+        return -WM_FAIL;
+    }
+
+    if (!is_uap_state(CM_UAP_INITIALIZING))
+    {
+        return -WM_FAIL;
+    }
+
+    if (memcmp(mac, &wlan.sta_mac[0], MLAN_MAC_ADDR_LENGTH) == 0)
+    {
+        return -WM_FAIL;
+    }
+
+    if (wlan.status == WLCMGR_INIT_DONE || wlan.status == WLCMGR_ACTIVATED)
+    {
+        net_wlan_set_mac_address(NULL, (unsigned char *)mac);
+
+        _wifi_set_mac_addr(mac, MLAN_BSS_TYPE_UAP);
+
+        /* save the uap mac */
+        (void)memcpy(&wlan.uap_mac[0], mac, MLAN_MAC_ADDR_LENGTH);
+    }
+    else
+    {
+        wifi_set_mac_addr(mac);
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_set_sta_mac_addr(uint8_t *mac)
+{
+    /* Only suppoprt unicast mac */
+    if (mac[0] & 0x01)
+    {
+        return -WM_FAIL;
+    }
+
+    if (is_sta_connecting())
+    {
+        return -WM_FAIL;
+    }
+
+    if (memcmp(mac, &wlan.uap_mac[0], MLAN_MAC_ADDR_LENGTH) == 0)
+    {
+        return -WM_FAIL;
+    }
+
+    if (wlan.status == WLCMGR_INIT_DONE || wlan.status == WLCMGR_ACTIVATED)
+    {
+        net_wlan_set_mac_address((unsigned char *)mac, NULL);
+
+        _wifi_set_mac_addr(mac, MLAN_BSS_TYPE_STA);
+
+        /* save the sta mac */
+        (void)memcpy(&wlan.sta_mac[0], mac, MLAN_MAC_ADDR_LENGTH);
+    }
+    else
+    {
+        wifi_set_mac_addr(mac);
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_scan(int (*cb)(unsigned int count))
+{
+    int ret;
+
+    wlan_scan_params_v2_t wlan_scan_param;
+
+    (void)memset(&wlan_scan_param, 0, sizeof(wlan_scan_params_v2_t));
+
+    wlan_scan_param.cb = cb;
+
+    ret = wlan_scan_with_opt(wlan_scan_param);
+
+    return ret;
+}
+
+static int wlan_pscan(int (*cb)(unsigned int count))
+{
+    struct wlan_network* network = NULL;
+    wlan_scan_params_v2_t wlan_scan_param;
+    int ret;
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+    {
+        network = &wlan.networks[wlan.cur_network_idx];
+    }
+
+    if (network == NULL)
+    {
+        wlcm_e("cannot get network info");
+        return -WM_FAIL;
+    }
+
+    (void)memset(&wlan_scan_param, 0, sizeof(wlan_scan_params_v2_t));
+
+    wlan_scan_param.cb = cb;
+
+    (void)memcpy((void *)wlan_scan_param.bssid, (const void *)network->bssid, MLAN_MAC_ADDR_LENGTH);
+
+    (void)memcpy((void *)wlan_scan_param.ssid, (const void *)network->ssid, strlen(network->ssid));
+
+    wlan_scan_param.num_channels = 1;
+
+    wlan_scan_param.chan_list[0].chan_number = (t_u8)network->channel;
+    wlan_scan_param.chan_list[0].scan_type   = MLAN_SCAN_TYPE_PASSIVE;
+    wlan_scan_param.chan_list[0].scan_time   = 200;
+
+    ret = wlan_scan_with_opt(wlan_scan_param);
+
+    return ret;
+}
+
+int wlan_scan_with_opt(wlan_scan_params_v2_t t_wlan_scan_param)
+{
+    int ret;
+    uint32_t chan_idx = 0;
+    uint32_t t_idx = 0;
+    wlan_scan_params_v2_t *wlan_scan_param = NULL;
+
+    if (t_wlan_scan_param.cb == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (!is_running() || !is_scanning_allowed())
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+#if !CONFIG_MEM_POOLS
+    wlan_scan_param = (wlan_scan_params_v2_t *)OSA_MemoryAllocate(sizeof(wlan_scan_params_v2_t));
+#else
+     wlan_scan_param = (wlan_scan_params_v2_t *)OSA_MemoryPoolAllocate(buf_512_MemoryPool);
+#endif
+
+    if (wlan_scan_param == NULL)
+    {
+        return -WM_E_NOMEM;
+    }
+
+    (void)memcpy((void *)wlan_scan_param, (const void *)&t_wlan_scan_param, sizeof(wlan_scan_params_v2_t));
+
+    if (t_wlan_scan_param.num_channels > 0)
+    {
+        wlan_scan_param->num_channels = 0;
+        (void)memset((void *)&wlan_scan_param->chan_list[0], 0x0, MAX_CHANNEL_LIST * sizeof(wifi_scan_channel_list_t));
+#if defined(RW610) && (CONFIG_ANT_DETECT)
+        for (t_idx = 0; t_idx < ANT_DETECT_MAX_CHANNEL_LIST && t_wlan_scan_param.chan_list[t_idx].chan_number; t_idx++)
+#else
+        for (t_idx = 0; t_idx < MAX_CHANNEL_LIST && t_wlan_scan_param.chan_list[t_idx].chan_number; t_idx++)
+#endif
+        {
+            if(!wlan_check_channel_by_region_table((mlan_private *)mlan_adap->priv[0], t_wlan_scan_param.chan_list[t_idx].chan_number))
+            {
+                continue;
+            }
+            (void)memcpy((void *)&wlan_scan_param->chan_list[chan_idx], (const void *)&t_wlan_scan_param.chan_list[t_idx], sizeof(wifi_scan_channel_list_t));
+            chan_idx++;
+        }
+        wlan_scan_param->num_channels = chan_idx;
+
+        if (chan_idx == 0 && t_wlan_scan_param.num_channels > 0)
+        {
+            wlcm_e("no valid channel to scan");
+#if !CONFIG_MEM_POOLS
+            OSA_MemoryFree(wlan_scan_param);
+#else
+            OSA_MemoryPoolFree(buf_512_MemoryPool, wlan_scan_param);
+#endif
+
+            return -WM_E_INVAL;
+        }
+    }
+
+    wlcm_d("taking the scan lock (user scan)");
+    dbg_lock_info();
+    ret = OSA_SemaphoreWait((osa_semaphore_handle_t)wlan.scan_lock, osaWaitForever_c);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("failed to get scan lock: 0x%X", ret);
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(wlan_scan_param);
+#else
+        OSA_MemoryPoolFree(buf_512_MemoryPool, wlan_scan_param);
+#endif
+        return -WM_FAIL;
+    }
+    wlcm_d("got the scan lock (user scan)");
+    wlan.is_scan_lock = 1;
+
+    ret = send_user_request(CM_STA_USER_REQUEST_SCAN, (unsigned int)wlan_scan_param);
+
+    if (ret != WM_SUCCESS)
+    {
+#if !CONFIG_MEM_POOLS
+        OSA_MemoryFree(wlan_scan_param);
+#else
+        OSA_MemoryPoolFree(buf_512_MemoryPool, wlan_scan_param);
+#endif
+    }
+
+    return ret;
+}
+
+int wlan_get_connection_state(enum wlan_connection_state *state)
+{
+    enum cm_sta_state cur;
+
+    if (state == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (!is_running())
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    if (is_user_scanning() != 0)
+    {
+        cur = wlan.sta_return_to;
+    }
+    else
+    {
+        cur = wlan.sta_state;
+    }
+
+    switch (cur)
+    {
+        case CM_STA_IDLE:
+            *state = WLAN_DISCONNECTED;
+            break;
+        case CM_STA_SCANNING:
+            *state = WLAN_SCANNING;
+            break;
+        case CM_STA_ASSOCIATING:
+            *state = WLAN_ASSOCIATING;
+            break;
+        case CM_STA_ASSOCIATED:
+            *state = WLAN_ASSOCIATED;
+            break;
+        case CM_STA_AUTHENTICATED:
+            *state = WLAN_AUTHENTICATED;
+            break;
+        case CM_STA_REQUESTING_ADDRESS:
+        case CM_STA_OBTAINING_ADDRESS:
+            *state = WLAN_CONNECTING;
+            break;
+        case CM_STA_CONNECTED:
+            *state = WLAN_CONNECTED;
+            break;
+        default:
+            *state = WLAN_DISCONNECTED;
+            break;
+    }
+    return WM_SUCCESS;
+}
+
+int wlan_get_ps_mode(enum wlan_ps_mode *ps_mode)
+{
+    if (ps_mode == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    *ps_mode = WLAN_ACTIVE;
+
+    if (wlan.cm_ieeeps_configured && wlan.cm_deepsleepps_configured)
+    {
+        if (is_state(CM_STA_CONNECTED))
+        {
+            *ps_mode = WLAN_IEEE;
+        }
+        else
+        {
+            *ps_mode = WLAN_DEEP_SLEEP;
+        }
+    }
+#if CONFIG_WNM_PS
+    else if (wlan.cm_wnmps_configured && wlan.cm_deepsleepps_configured)
+    {
+        if (is_state(CM_STA_CONNECTED))
+        {
+            *ps_mode = WLAN_WNM;
+        }
+        else
+        {
+            *ps_mode = WLAN_DEEP_SLEEP;
+        }
+    }
+    else if (wlan.cm_wnmps_configured)
+    {
+        *ps_mode = WLAN_WNM;
+    }
+#endif
+    else if (wlan.cm_deepsleepps_configured)
+    {
+        *ps_mode = WLAN_DEEP_SLEEP;
+    }
+    else if (wlan.cm_ieeeps_configured)
+    {
+        *ps_mode = WLAN_IEEE;
+    }
+    else
+    { /* Do Nothing */
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_get_uap_connection_state(enum wlan_connection_state *state)
+{
+    enum cm_uap_state cur;
+
+    if (state == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (!is_running())
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    cur = wlan.uap_state;
+
+    switch (cur)
+    {
+        case CM_UAP_INITIALIZING:
+        case CM_UAP_CONFIGURED:
+            *state = WLAN_UAP_STOPPED;
+            break;
+        case CM_UAP_STARTED:
+        case CM_UAP_IP_UP:
+            *state = WLAN_UAP_STARTED;
+            break;
+        default:
+            *state = WLAN_UAP_STOPPED;
+            break;
+    }
+    return WM_SUCCESS;
+}
+
+int wlan_get_address(struct wlan_ip_config *addr)
+{
+    void *if_handle = NULL;
+    if (addr == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    if (!is_running() || !is_state(CM_STA_CONNECTED))
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    if_handle = net_get_mlan_handle();
+    if (net_get_if_addr((struct net_ip_config *)addr, if_handle) != 0)
+    {
+        return -WM_FAIL;
+    }
+
+#if CONFIG_IPV6
+    if (net_get_if_ipv6_addr((struct net_ip_config *)addr, if_handle) != 0)
+    {
+        return -WM_FAIL;
+    }
+#endif
+
+    return WM_SUCCESS;
+}
+
+int wlan_get_uap_address(struct wlan_ip_config *addr)
+{
+    void *if_handle = NULL;
+    if (addr == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+    if (!is_running() || !is_uap_state(CM_UAP_IP_UP))
+    {
+        return WLAN_ERROR_STATE;
+    }
+
+    if_handle = net_get_uap_handle();
+    if (net_get_if_addr((struct net_ip_config *)addr, if_handle) != 0)
+    {
+        return -WM_FAIL;
+    }
+    return WM_SUCCESS;
+}
+
+int wlan_get_uap_channel(int *channel)
+{
+    if (channel != NULL)
+    {
+        *channel = 0;
+    }
+    else
+    {
+        return (int)(-WM_E_INVAL);
+    }
+
+    return wifi_get_uap_channel(channel);
+}
+
+
+int wlan_get_mac_address(unsigned char *dest)
+{
+    if (!dest)
+        return -WM_E_INVAL;
+    (void)memset(dest, 0, MLAN_MAC_ADDR_LENGTH);
+    (void)memcpy(dest, &wlan.sta_mac[0], MLAN_MAC_ADDR_LENGTH);
+    return WM_SUCCESS;
+}
+
+int wlan_get_mac_address_uap(unsigned char *dest)
+{
+    if (!dest)
+        return -WM_E_INVAL;
+    (void)memset(dest, 0, MLAN_MAC_ADDR_LENGTH);
+    (void)memcpy(dest, &wlan.uap_mac[0], MLAN_MAC_ADDR_LENGTH);
+    return WM_SUCCESS;
+}
+
+
+void wlan_wake_up_card(void)
+{
+    uint32_t resp;
+
+    wifi_wake_up_card(&resp);
+}
+
+int wlan_set_ieeeps_cfg(struct wlan_ieeeps_config *ps_cfg)
+{
+    wlan_configure_null_pkt_interval(ps_cfg->ps_null_interval);
+
+    return send_user_request(CM_STA_USER_REQUEST_PS_ENTER, WLAN_IEEE);
+}
+
+void wlan_configure_listen_interval(int listen_interval)
+{
+    wifi_configure_listen_interval(listen_interval);
+}
+
+void wlan_configure_delay_to_ps(unsigned int timeout_ms)
+{
+    wifi_configure_delay_to_ps(timeout_ms);
+}
+
+unsigned short wlan_get_listen_interval(void)
+{
+    return wifi_get_listen_interval();
+}
+
+unsigned int wlan_get_delay_to_ps(void)
+{
+    return wifi_get_delay_to_ps();
+}
+
+bool wlan_is_power_save_enabled(void)
+{
+    if (wlan.cm_ieeeps_configured
+#if CONFIG_WNM_PS
+        || wlan.cm_wnmps_configured
+#endif
+        || wlan.cm_deepsleepps_configured)
+    {
+        return true;
+    }
+
+    return false;
+}
+
+void wlan_configure_null_pkt_interval(int time_in_secs)
+{
+    wifi_configure_null_pkt_interval((unsigned int)time_in_secs);
+}
+
+int wlan_ieeeps_on(unsigned int wakeup_conditions)
+{
+    enum wlan_connection_state state;
+
+    if ((!wlan.running) || (wlan_get_uap_connection_state(&state) != 0) || (state == WLAN_UAP_STARTED))
+    {
+        return -WM_FAIL;
+    }
+
+    if (wlan.cm_ieeeps_configured
+#if CONFIG_WNM_PS
+        || wlan.cm_wnmps_configured
+#endif
+       )
+    {
+#if CONFIG_WNM_PS
+        if (wlan.cm_wnmps_configured == true)
+        {
+            wlcm_d("wnm ps already enabled: %d, ieee ps could not be enabled", wlan.cm_wnmps_configured);
+            return -WM_FAIL;
+        }
+        else
+#endif
+        {
+            wlcm_d("ieee ps already enabled");
+        }
+
+        CONNECTION_EVENT(WLAN_REASON_PS_ENTER, (void *)WLAN_IEEE);
+        return WM_SUCCESS;
+    }
+
+    return send_user_request(CM_STA_USER_REQUEST_PS_ENTER, WLAN_IEEE);
+}
+
+int wlan_ieeeps_off(void)
+{
+    if (wlan.cm_ieeeps_configured)
+    {
+        return send_user_request(CM_STA_USER_REQUEST_PS_EXIT, WLAN_IEEE);
+    }
+
+    CONNECTION_EVENT(WLAN_REASON_PS_EXIT, (void *)WLAN_IEEE);
+    return WM_SUCCESS;
+}
+
+#if !CONFIG_WPA_SUPP
+#if (CONFIG_WNM_PS)
+int wlan_wnmps_on(unsigned int wakeup_conditions, t_u16 wnm_sleep_time)
+{
+    enum wlan_connection_state state;
+
+    if ((!wlan.running) || (wlan_get_uap_connection_state(&state) != 0) || (state == WLAN_UAP_STARTED))
+    {
+        return -WM_FAIL;
+    }
+
+    if (wlan.cm_ieeeps_configured || wlan.cm_wnmps_configured)
+    {
+        if (wlan.cm_ieeeps_configured == true)
+        {
+            wlcm_d("ieee ps already enabled: %d, wnm ps could not be enabled", wlan.cm_ieeeps_configured);
+            return -WM_FAIL;
+        }
+        else
+        {
+            wlcm_d("wnm ps already enabled");
+        }
+
+        CONNECTION_EVENT(WLAN_REASON_PS_ENTER, (void *)WLAN_WNM);
+        return WM_SUCCESS;
+    }
+
+    wlan.wakeup_conditions   = wakeup_conditions;
+    wlan.wnm_sleep_time      = wnm_sleep_time;
+    return send_user_request(CM_STA_USER_REQUEST_PS_ENTER, WLAN_WNM);
+}
+
+int wlan_wnmps_off()
+{
+    if (wlan.cm_wnmps_configured)
+    {
+        return send_user_request(CM_STA_USER_REQUEST_PS_EXIT, WLAN_WNM);
+    }
+
+    CONNECTION_EVENT(WLAN_REASON_PS_EXIT, (void *)WLAN_WNM);
+    return WM_SUCCESS;
+}
+#endif
+#endif
+
+int wlan_deepsleepps_on(void)
+{
+    enum wlan_connection_state state;
+
+    if ((!wlan.running) || (wlan_get_uap_connection_state(&state) != 0) || (state == WLAN_UAP_STARTED))
+    {
+        return -WM_FAIL;
+    }
+
+    if (wlan.cm_deepsleepps_configured)
+    {
+        CONNECTION_EVENT(WLAN_REASON_PS_ENTER, (void *)WLAN_DEEP_SLEEP);
+        return WM_SUCCESS;
+    }
+
+    return send_user_request(CM_STA_USER_REQUEST_PS_ENTER, WLAN_DEEP_SLEEP);
+}
+
+int wlan_deepsleepps_off(void)
+{
+    if (wlan.cm_deepsleepps_configured)
+    {
+        return send_user_request(CM_STA_USER_REQUEST_PS_EXIT, WLAN_DEEP_SLEEP);
+    }
+
+    CONNECTION_EVENT(WLAN_REASON_PS_EXIT, (void *)WLAN_DEEP_SLEEP);
+    return WM_SUCCESS;
+}
+
+#if CONFIG_WPS2
+int wlan_start_wps_pbc()
+{
+    wlan_wps.wps_state = PROV_WPS_PBC_ENABLED;
+    wlan_wps.wps_cmd   = CMD_WPS_PBC;
+    wlan_wps.wps_pin   = 0;
+
+    return WM_SUCCESS;
+}
+
+void wlan_wps_generate_pin(uint32_t *pin)
+{
+    wps_generate_pin(pin);
+}
+
+int wlan_start_wps_pin(uint32_t pin)
+{
+    if (wps_validate_pin(pin) != WM_SUCCESS)
+    {
+        wlcm_d("WPS PIN validation failed for %d", pin);
+        return -WM_FAIL;
+    }
+
+    wlan_wps.wps_state = PROV_WPS_PIN_ENABLED;
+    wlan_wps.wps_cmd   = CMD_WPS_PIN;
+    wlan_wps.wps_pin   = pin;
+
+    return WM_SUCCESS;
+}
+#endif
+
+#ifndef RW610
+int wlan_set_antcfg(uint32_t ant, uint16_t evaluate_time)
+{
+    int rv = wifi_set_antenna(ant, evaluate_time);
+    if (rv != WM_SUCCESS)
+    {
+        wlcm_e("Unable to set antenna");
+        return WLAN_ERROR_STATE;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_get_antcfg(uint32_t *ant, uint16_t *evaluate_time, uint16_t *current_antenna)
+{
+    int rv = wifi_get_antenna((unsigned int *)ant, evaluate_time, current_antenna);
+    if (rv != WM_SUCCESS)
+    {
+        wlcm_e("Unable to get current antenna");
+        return WLAN_ERROR_STATE;
+    }
+
+    return WM_SUCCESS;
+}
+#else
+int wlan_set_antcfg(uint32_t ant, uint16_t evaluate_time, uint8_t evaluate_mode)
+{
+    int rv = wifi_set_antenna(ant, evaluate_time, evaluate_mode);
+    if (rv != WM_SUCCESS)
+    {
+        wlcm_e("Unable to set antenna");
+        return WLAN_ERROR_STATE;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_get_antcfg(uint32_t *ant, uint16_t *evaluate_time, uint8_t *evaluate_mode, uint16_t *current_antenna)
+{
+    int rv = wifi_get_antenna((unsigned int *)ant, evaluate_time, evaluate_mode, current_antenna);
+    if (rv != WM_SUCCESS)
+    {
+        wlcm_e("Unable to get current antenna");
+        return WLAN_ERROR_STATE;
+    }
+
+    return WM_SUCCESS;
+}
+#endif /*RW610*/
+
+
+int wlan_wlcmgr_send_msg(enum wifi_event event, enum wifi_event_reason reason, void *data)
+{
+    struct wifi_message msg;
+
+    msg.event  = (uint16_t)event;
+    msg.reason = reason;
+    msg.data   = (void *)data;
+
+    if (OSA_MsgQPut((osa_msgq_handle_t)wlan.events, &msg) == KOSA_StatusSuccess)
+    {
+        return WM_SUCCESS;
+    }
+
+    return -WM_FAIL;
+}
+
+/*
+  This function validates input string for a valid WEP key, converts
+  it to appropriate format
+
+  Returns positive integer equal to size of the output string
+  for successful operation or -WM_FAIL in case of failure to convert. Note
+  that the output string is not NULL terminated.
+ */
+int load_wep_key(const uint8_t *input, uint8_t *output, uint8_t *output_len, const unsigned max_output_len)
+{
+    if (input == NULL || output == NULL)
+    {
+        return -WM_FAIL;
+    }
+
+    unsigned len = *output_len;
+
+    /* fixme: add macros here after mlan integration */
+    if (len == 10U || len == 26U)
+    {
+        /* Looks like this is an hexadecimal key */
+        int ret = (int)wm_hex2bin(input, output, max_output_len);
+        if (ret == 0)
+        {
+            return -WM_FAIL;
+        }
+
+        len = len / 2U;
+    }
+    else if (len == 5U || len == 13U)
+    {
+        /* Looks like this is ASCII key  */
+        if (len > max_output_len)
+        {
+            return -WM_FAIL;
+        }
+
+        (void)memcpy((void *)output, (const void *)input, len);
+    }
+    else
+    {
+        return -WM_FAIL;
+    }
+
+    *output_len = (uint8_t)len;
+
+    return WM_SUCCESS;
+}
+
+int get_split_scan_delay_ms(void)
+{
+    return g_wifi_scan_params.split_scan_delay;
+}
+
+char *wlan_get_firmware_version_ext(void)
+{
+    return wlan.fw_ver_ext.version_str;
+}
+
+unsigned int wlan_get_uap_supported_max_clients(void)
+{
+    return wlan.uap_supported_max_sta_num;
+}
+
+int wlan_get_uap_max_clients(unsigned int *max_sta_num)
+{
+    return wifi_get_uap_max_clients(max_sta_num);
+}
+
+int wlan_set_uap_max_clients(unsigned int max_sta_num)
+{
+    int ret = -WM_FAIL;
+
+    if (is_uap_started() != 0)
+    {
+        wlcm_e(
+                "Cannot set the max station number "
+                "as the uAP is already running");
+        return -WM_FAIL;
+    }
+    else if (max_sta_num > wlan.uap_supported_max_sta_num)
+    {
+        wlcm_e(
+                "Maximum supported station number "
+                "limit is = %d",
+                wlan.uap_supported_max_sta_num);
+        return -WM_FAIL;
+    }
+    else
+    {
+        ret = wifi_set_uap_max_clients(&max_sta_num);
+
+        if (ret != WM_SUCCESS)
+        {
+            return ret;
+        }
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+        struct netif *uap_netif = net_get_uap_interface();
+
+        wpa_supp_set_ap_max_num_sta(uap_netif, max_sta_num);
+#endif
+#endif
+        return ret;
+    }
+}
+
+int wlan_get_mgmt_ie(enum wlan_bss_type bss_type, IEEEtypes_ElementId_t index, void *buf, unsigned int *buf_len)
+{
+    return wifi_get_mgmt_ie((mlan_bss_type)bss_type, index, buf, buf_len);
+}
+
+int wlan_set_mgmt_ie(enum wlan_bss_type bss_type, IEEEtypes_ElementId_t id, void *buf, unsigned int buf_len)
+{
+    return wifi_set_mgmt_ie((mlan_bss_type)bss_type, id, buf, buf_len);
+}
+
+#ifdef SD8801
+int wlan_get_ext_coex_stats(wlan_ext_coex_stats_t *ext_coex_stats)
+{
+    return wifi_get_ext_coex_stats(ext_coex_stats);
+}
+
+int wlan_set_ext_coex_config(const wlan_ext_coex_config_t ext_coex_config)
+{
+    return wifi_set_ext_coex_config(&ext_coex_config);
+}
+#endif
+
+int wlan_clear_mgmt_ie(enum wlan_bss_type bss_type, IEEEtypes_ElementId_t index, int mgmt_bitmap_index)
+{
+    return wifi_clear_mgmt_ie((mlan_bss_type)bss_type, index, mgmt_bitmap_index);
+}
+
+int wlan_set_txbfcap(unsigned int tx_bf_cap)
+{
+    return wifi_set_txbfcap(tx_bf_cap);
+}
+
+int wlan_set_htcapinfo(unsigned int htcapinfo)
+{
+    return wifi_set_htcapinfo(htcapinfo);
+}
+
+int wlan_set_httxcfg(unsigned short httxcfg)
+{
+    return wifi_set_httxcfg(httxcfg);
+}
+
+int wlan_set_txratecfg(wlan_ds_rate ds_rate, mlan_bss_type bss_type)
+{
+    return wifi_set_txratecfg(ds_rate, bss_type);
+}
+
+int wlan_get_txratecfg(wlan_ds_rate *ds_rate, mlan_bss_type bss_type)
+{
+    int ret;
+
+    ret = wifi_get_txratecfg(ds_rate, bss_type);
+
+    if (ret != WM_SUCCESS)
+    {
+        return ret;
+    }
+
+    ret = wifi_get_data_rate(ds_rate, bss_type);
+
+    if (ret != WM_SUCCESS)
+    {
+        return ret;
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_set_sta_tx_power(t_u32 power_level)
+{
+    return wifi_set_tx_power(power_level);
+}
+
+int wlan_get_sta_tx_power(t_u32 *power_level)
+{
+    return wifi_get_tx_power(power_level);
+}
+
+#if CONFIG_COMPRESS_TX_PWTBL
+int wlan_set_region_power_cfg(const t_u8 *data, t_u16 len)
+{
+    return wifi_set_region_power_cfg(data, len);
+}
+#endif
+
+int wlan_set_chanlist_and_txpwrlimit(wlan_chanlist_t *chanlist, wlan_txpwrlimit_t *txpwrlimit)
+{
+    int ret = WM_SUCCESS;
+
+    ret = wlan_set_chanlist(chanlist);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Cannot set Channel List");
+        return ret;
+    }
+
+    ret = wlan_set_txpwrlimit(txpwrlimit);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Cannot set Tx Power");
+    }
+
+    return ret;
+}
+
+int wlan_set_chanlist(wlan_chanlist_t *chanlist)
+{
+    if (chanlist != NULL)
+    {
+        return wifi_set_chanlist(chanlist);
+    }
+
+    return -WM_FAIL;
+}
+
+int wlan_get_chanlist(wlan_chanlist_t *chanlist)
+{
+    if (chanlist != NULL)
+    {
+        return wifi_get_chanlist(chanlist);
+    }
+
+    return -WM_FAIL;
+}
+
+int wlan_set_txpwrlimit(wlan_txpwrlimit_t *txpwrlimit)
+{
+    if (txpwrlimit != NULL)
+    {
+        return wifi_set_txpwrlimit(txpwrlimit);
+    }
+
+    return -WM_FAIL;
+}
+
+int wlan_get_txpwrlimit(wifi_SubBand_t subband, wifi_txpwrlimit_t *txpwrlimit)
+{
+    if (txpwrlimit != NULL)
+    {
+        (void)memset(txpwrlimit, 0x00, sizeof(wifi_txpwrlimit_t));
+        return wifi_get_txpwrlimit(subband, txpwrlimit);
+    }
+
+    return -WM_FAIL;
+}
+
+#if WLAN_LOW_POWER_ENABLE
+int wlan_enable_low_pwr_mode(void)
+{
+    if (wlan.status == WLCMGR_INACTIVE)
+    {
+        wifi_enable_low_pwr_mode();
+        return WM_SUCCESS;
+    }
+    else
+        return -WM_FAIL;
+}
+#endif
+
+void wlan_set_reassoc_control(bool reassoc_control)
+{
+    wlan.reassoc_control = reassoc_control;
+    wlcm_d("Reassoc control %s", reassoc_control ? "enabled" : "disabled");
+}
+
+int wlan_set_ed_mac_mode(wlan_ed_mac_ctrl_t wlan_ed_mac_ctrl)
+{
+    return wifi_set_ed_mac_mode(&wlan_ed_mac_ctrl, MLAN_BSS_TYPE_STA);
+}
+
+int wlan_get_ed_mac_mode(wlan_ed_mac_ctrl_t *wlan_ed_mac_ctrl)
+{
+    return wifi_get_ed_mac_mode(wlan_ed_mac_ctrl, MLAN_BSS_TYPE_STA);
+}
+
+int wlan_set_uap_ed_mac_mode(wlan_ed_mac_ctrl_t wlan_ed_mac_ctrl)
+{
+    return wifi_set_ed_mac_mode(&wlan_ed_mac_ctrl, MLAN_BSS_TYPE_UAP);
+}
+
+int wlan_get_uap_ed_mac_mode(wlan_ed_mac_ctrl_t *wlan_ed_mac_ctrl)
+{
+    return wifi_get_ed_mac_mode(wlan_ed_mac_ctrl, MLAN_BSS_TYPE_UAP);
+}
+
+bool wlan_get_11d_enable_status(void)
+{
+    return wrapper_wlan_11d_support_is_enabled();
+}
+
+int wlan_remain_on_channel(const enum wlan_bss_type bss_type,
+                           const bool status,
+                           const uint8_t channel,
+                           const uint32_t duration)
+{
+    wifi_remain_on_channel_t roc;
+
+    (void)memset(&roc, 0x00, sizeof(wifi_remain_on_channel_t));
+
+    roc.remove = (uint16_t)!status;
+
+    roc.channel = channel;
+
+    roc.remain_period = duration;
+
+#if CONFIG_5GHz_SUPPORT
+    if (channel > 14)
+    {
+        roc.bandcfg = 1;
+    }
+#endif
+
+    return wifi_send_remain_on_channel_cmd((uint32_t)bss_type, &roc);
+}
+
+int wlan_get_otp_user_data(uint8_t *buf, uint16_t len)
+{
+    if (buf == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    return wifi_get_otp_user_data(buf, len);
+}
+
+#if CONFIG_WIFI_GET_LOG
+int wlan_get_log(wlan_pkt_stats_t *stats)
+{
+    if (!stats)
+        return -WM_E_INVAL;
+
+    return wifi_get_log(stats, MLAN_BSS_TYPE_STA);
+}
+
+int wlan_uap_get_log(wlan_pkt_stats_t *stats)
+{
+    if (!stats)
+        return -WM_E_INVAL;
+
+    return wifi_get_log(stats, MLAN_BSS_TYPE_UAP);
+}
+#endif
+
+int wlan_get_cal_data(wlan_cal_data_t *cal_data)
+{
+    if (cal_data == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    return wifi_get_cal_data(cal_data);
+}
+
+#if CONFIG_AUTO_RECONNECT
+int wlan_auto_reconnect_enable(wlan_auto_reconnect_config_t auto_reconnect_config)
+{
+    if (is_sta_connected())
+    {
+        wlcm_e("Can not enable auto reconnect in connected state");
+        return -WM_E_INVAL;
+    }
+
+    return wifi_auto_reconnect_enable(auto_reconnect_config);
+}
+
+int wlan_auto_reconnect_disable(void)
+{
+    return wifi_auto_reconnect_disable();
+}
+
+int wlan_get_auto_reconnect_config(wlan_auto_reconnect_config_t *auto_reconnect_config)
+{
+    if (auto_reconnect_config == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    return wifi_get_auto_reconnect_config(auto_reconnect_config);
+}
+#endif
+
+int wlan_get_tsf(uint32_t *tsf_high, uint32_t *tsf_low)
+{
+    return wifi_get_tsf(tsf_high, tsf_low);
+}
+
+int wlan_tcp_keep_alive(wlan_tcp_keep_alive_t *tcp_keep_alive)
+{
+    int ret;
+    unsigned int ipv4_addr;
+
+    ret = wlan_get_ipv4_addr(&ipv4_addr);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Cannot get IP");
+        return -WM_FAIL;
+    }
+
+    return wifi_tcp_keep_alive(tcp_keep_alive, wlan.sta_mac, ipv4_addr);
+}
+
+
+#if CONFIG_CLOUD_KEEP_ALIVE
+/* Here the length of ip_packet for test is 40 */
+static t_u16 pkt_len_default = 40;
+/* ip packet content */
+static t_u8 packet_default[40] = {0x45, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0xff, 0x06, 0x00, 0x00, 0xc0, 0xa8,
+                                  0x00, 0x7c, 0xc0, 0xa8, 0x00, 0x8a, 0xc0, 0x03, 0x22, 0xb7, 0xb0, 0xb6, 0x60, 0x9f,
+                                  0x42, 0xdd, 0x9e, 0x1e, 0x50, 0x18, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+int wlan_save_cloud_keep_alive_params(wlan_cloud_keep_alive_t *cloud_keep_alive,
+                                      t_u16 src_port,
+                                      t_u16 dst_port,
+                                      t_u32 seq_number,
+                                      t_u32 ack_number,
+                                      t_u8 enable)
+{
+    if (enable)
+    {
+        if (cloud_keep_alive == NULL)
+        {
+            return -WM_E_INVAL;
+        }
+
+        if (!is_sta_connected())
+        {
+            wlcm_e("Can not start cloud keep alive in disconnected state");
+            return -WM_E_INVAL;
+        }
+
+        if (
+			cloud_keep_alive->mkeep_alive_id >= MAX_KEEP_ALIVE_ID)
+        {
+            wlcm_e("Invalid keep alive id");
+            return -WM_E_INVAL;
+        }
+
+        /* Get source mac address */
+        uint8_t sta_mac[MLAN_MAC_ADDR_LENGTH];
+        if (wlan_get_mac_address(sta_mac))
+        {
+            wlcm_e("Unable to retrieve MAC address\r\n");
+        }
+        (void)memcpy(cloud_keep_alive->src_mac, sta_mac, MLAN_MAC_ADDR_LENGTH);
+
+        /* Get source ip */
+        int ret = -WM_FAIL;
+        ret     = wlan_get_ipv4_addr(&cloud_keep_alive->src_ip);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("Cannot get IP");
+        }
+        (void)memcpy(&cloud_keep_alive_param[cloud_keep_alive->mkeep_alive_id], cloud_keep_alive, sizeof(wlan_cloud_keep_alive_t));
+    }
+    else
+    {
+        int i;
+
+        for (i = 0; i < MAX_KEEP_ALIVE_ID; i++)
+        {
+            cloud_keep_alive = &cloud_keep_alive_param[i];
+
+            if (cloud_keep_alive && cloud_keep_alive->enable && (ntohs(dst_port) == cloud_keep_alive->dst_port))
+            {
+                /* Copy source port, destination port, sequece number, ack number, window size for keep alive.
+                   IP header checksum and TCP pesudo header checksum are calculated by WLAN FW */
+                (void)memcpy(packet_default + 12, &cloud_keep_alive->src_ip, sizeof(cloud_keep_alive->src_ip));
+                (void)memcpy(packet_default + 16, &cloud_keep_alive->dst_ip, sizeof(cloud_keep_alive->dst_ip));
+                (void)memcpy(packet_default + 20, &src_port, sizeof(src_port));
+                (void)memcpy(packet_default + 22, &dst_port, sizeof(dst_port));
+                (void)memcpy(packet_default + 24, &seq_number, sizeof(seq_number));
+                (void)memcpy(packet_default + 28, &ack_number, sizeof(ack_number));
+
+                cloud_keep_alive->pkt_len = pkt_len_default;
+                (void)memcpy(cloud_keep_alive->packet, packet_default, cloud_keep_alive->pkt_len);
+
+                cloud_keep_alive->cached = MTRUE;
+            }
+        }
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_cloud_keep_alive_enabled(t_u32 dst_ip, t_u16 dst_port)
+{
+    int i;
+    wifi_cloud_keep_alive_t *cloud_keep_alive = NULL;
+
+    for (i = 0; i < MAX_KEEP_ALIVE_ID; i++)
+    {
+        cloud_keep_alive = &cloud_keep_alive_param[i];
+        if (cloud_keep_alive && (cloud_keep_alive->dst_ip == dst_ip) && (cloud_keep_alive->dst_port == dst_port))
+        {
+            return 1;
+        }
+    }
+
+    return 0;
+}
+
+int wlan_start_cloud_keep_alive(void)
+{
+    int i;
+    wifi_cloud_keep_alive_t *cloud_keep_alive = NULL;
+
+    for (i = 0; i < MAX_KEEP_ALIVE_ID; i++)
+    {
+        cloud_keep_alive = &cloud_keep_alive_param[i];
+        if (cloud_keep_alive && cloud_keep_alive->cached && cloud_keep_alive->enable)
+        {
+            cloud_keep_alive->cached = MFALSE;
+            wifi_cloud_keep_alive(cloud_keep_alive, MLAN_ACT_SET, NULL);
+        }
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_stop_cloud_keep_alive(wlan_cloud_keep_alive_t *cloud_keep_alive)
+{
+    t_u8 enable = MTRUE;
+
+    if (cloud_keep_alive == NULL)
+        return -WM_E_INVAL;
+
+    wifi_cloud_keep_alive(cloud_keep_alive, MLAN_ACT_GET, &enable);
+
+    if (enable == MFALSE)
+    {
+        wlcm_e("Cloud keep alive is already stoped");
+        return 0;
+    }
+    return wifi_cloud_keep_alive(cloud_keep_alive, MLAN_ACT_SET, NULL);
+}
+#endif
+
+uint16_t wlan_get_beacon_period(void)
+{
+    struct wlan_network* network = NULL;
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+    {
+        network = &wlan.networks[wlan.cur_network_idx];
+    }
+
+    if (network == NULL)
+    {
+        wlcm_e("cannot get network info");
+        return 0;
+    }
+
+    return network->beacon_period;
+}
+
+OSA_SEMAPHORE_HANDLE_DEFINE(wlan_dtim_sem);
+
+static uint8_t dtim_period;
+
+static int pscan_cb(unsigned int count)
+{
+    struct wlan_scan_result res;
+    unsigned int i;
+    int err;
+
+    dtim_period = 0;
+
+    if (count == 0U)
+    {
+        (void)PRINTF("networks not found\r\n");
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan_dtim_sem);
+        return 0;
+    }
+
+    for (i = 0; i < count; i++)
+    {
+        err = wlan_get_scan_result(i, &res);
+        if (err != 0)
+        {
+            (void)PRINTF("Error: can't get scan res %d\r\n", i);
+            continue;
+        }
+
+        dtim_period = res.dtim_period;
+    }
+
+    (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan_dtim_sem);
+
+    return 0;
+}
+
+uint8_t wlan_get_dtim_period(void)
+{
+    osa_status_t status;
+
+    status = OSA_SemaphoreCreateBinary((osa_semaphore_handle_t)wlan_dtim_sem);
+    if (status != KOSA_StatusSuccess)
+    {
+        return 0;
+    }
+
+    if (wlan_pscan(pscan_cb) != 0)
+    {
+        (void)PRINTF("Error: scan request failed\r\n");
+        (void)OSA_SemaphorePost((osa_semaphore_handle_t)wlan_dtim_sem);
+        (void)OSA_SemaphoreDestroy(wlan_dtim_sem);
+        return 0;
+    }
+
+    /* Wait till scan for DTIM is complete */
+    /*TODO:This need to be handled in better way. */
+    if (OSA_SemaphoreWait((osa_semaphore_handle_t)wlan_dtim_sem, 500) != KOSA_StatusSuccess)
+    {
+        wlcm_e("Do not call this API from wlan event handler\r\n");
+        dtim_period = 0;
+    }
+    (void)OSA_SemaphoreDestroy(wlan_dtim_sem);
+
+    return dtim_period;
+}
+
+int wlan_get_data_rate(wlan_ds_rate *ds_rate, mlan_bss_type bss_type)
+{
+    return wifi_get_data_rate(ds_rate, bss_type);
+}
+
+static int wlan_set_pmfcfg(uint8_t mfpc, uint8_t mfpr)
+{
+    if (!mfpc && mfpr)
+    {
+        return -WM_FAIL;
+    }
+
+    return wifi_set_pmfcfg(mfpc, mfpr);
+}
+
+int wlan_get_pmfcfg(uint8_t *mfpc, uint8_t *mfpr)
+{
+    return wifi_get_pmfcfg(mfpc, mfpr);
+}
+
+int wlan_uap_get_pmfcfg(uint8_t *mfpc, uint8_t *mfpr)
+{
+    if (is_uap_started())
+    {
+        return wifi_uap_get_pmfcfg(mfpc, mfpr);
+    }
+    return -WM_FAIL;
+}
+
+
+int wlan_set_packet_filters(wlan_flt_cfg_t *flt_cfg)
+{
+    return wifi_set_packet_filters(flt_cfg);
+}
+
+int wlan_set_auto_arp(void)
+{
+    int ret;
+    unsigned int ipv4_addr;
+    wlan_flt_cfg_t flt_cfg;
+
+    ret = wlan_get_ipv4_addr(&ipv4_addr);
+    if (ret != WM_SUCCESS)
+    {
+        wlcm_e("Cannot get IP");
+        return -WM_FAIL;
+    }
+
+    (void)memset(&flt_cfg, 0, sizeof(wlan_flt_cfg_t));
+
+    flt_cfg.criteria = CRITERIA_BROADCAST;
+    flt_cfg.nentries = 1;
+
+    flt_cfg.mef_entry[0].mode   = MEF_MODE_HOST_SLEEP; // MBIT(0);
+    flt_cfg.mef_entry[0].action = MEF_AUTO_ARP;
+
+    flt_cfg.mef_entry[0].filter_num = 3;
+
+    flt_cfg.mef_entry[0].filter_item[0].type         = TYPE_BYTE_EQ;
+    flt_cfg.mef_entry[0].filter_item[0].repeat       = 6;
+    flt_cfg.mef_entry[0].filter_item[0].offset       = 0;
+    flt_cfg.mef_entry[0].filter_item[0].num_byte_seq = 1;
+    flt_cfg.mef_entry[0].filter_item[0].byte_seq[0]  = 0xff;
+    flt_cfg.mef_entry[0].rpn[1]                      = RPN_TYPE_AND;
+
+    flt_cfg.mef_entry[0].filter_item[1].type         = TYPE_BYTE_EQ;
+    flt_cfg.mef_entry[0].filter_item[1].repeat       = 1;
+    flt_cfg.mef_entry[0].filter_item[1].offset       = 20;
+    flt_cfg.mef_entry[0].filter_item[1].num_byte_seq = 2;
+    (void)memcpy((void *)flt_cfg.mef_entry[0].filter_item[1].byte_seq, (const void *)"\x08\x06", 2);
+    flt_cfg.mef_entry[0].rpn[2] = RPN_TYPE_AND;
+
+    flt_cfg.mef_entry[0].filter_item[2].type         = TYPE_BYTE_EQ;
+    flt_cfg.mef_entry[0].filter_item[2].repeat       = 1;
+    flt_cfg.mef_entry[0].filter_item[2].offset       = 46;
+    flt_cfg.mef_entry[0].filter_item[2].num_byte_seq = 4;
+    (void)memcpy((void *)flt_cfg.mef_entry[0].filter_item[2].byte_seq, (const void *)&ipv4_addr, 4);
+
+    return wifi_set_packet_filters(&flt_cfg);
+}
+
+#ifndef __ZEPHYR__
+#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d))
+#endif
+
+#if !CONFIG_WPA_SUPP
+static inline bool is_broadcast_ether_addr(const t_u8 *addr)
+{
+    return (*(const t_u16 *)(addr + 0) & *(const t_u16 *)(addr + 2) & *(const t_u16 *)(addr + 4)) == 0xffff;
+}
+#endif
+
+/**
+ * @brief is_wowlan_pattern_supported
+ *
+ * @param priv                 A pointer to moal_private
+ * @param pat                 A pointer to wowlan pattern
+ * @param byte_seq       A pointer to byte_seq
+ *
+ * @return                      1 -- support, 0 -- not support
+ */
+static t_bool is_wowlan_pattern_supported(wifi_wowlan_pattern_t *pat, t_u8 *byte_seq)
+{
+    int j, k, valid_byte_cnt = 0;
+    t_bool dont_care_byte = false;
+
+    for (j = 0; j < DIV_ROUND_UP(pat->pattern_len, 8); j++)
+    {
+        for (k = 0; k < 8; k++)
+        {
+            if (pat->mask[j] & 1 << k)
+            {
+                (void)memcpy((void *)(byte_seq + valid_byte_cnt), (const void *)&pat->pattern[j * 8 + k], 1);
+                valid_byte_cnt++;
+                if (dont_care_byte)
+                    return false;
+            }
+            else
+            {
+                if (valid_byte_cnt)
+                    dont_care_byte = true;
+            }
+
+            if (valid_byte_cnt > MAX_NUM_BYTE_SEQ)
+                return false;
+        }
+    }
+
+    byte_seq[MAX_NUM_BYTE_SEQ] = valid_byte_cnt;
+
+    return true;
+}
+
+int wlan_wowlan_cfg_ptn_match(wlan_wowlan_ptn_cfg_t *ptn_cfg)
+{
+    wlan_flt_cfg_t flt_cfg;
+    wifi_mef_entry_t *mef_entry;
+    t_u8 byte_seq[MAX_NUM_BYTE_SEQ + 1];
+    const t_u8 ipv4_mc_mac[] = {0x33, 0x33};
+    const t_u8 ipv6_mc_mac[] = {0x01, 0x00, 0x5e};
+    int filt_num = 0, i = 0, ret = 0;
+    t_bool first_pat = true;
+    memset(&flt_cfg, 0, sizeof(flt_cfg));
+    //  mef_cfg.mef_act_type = MEF_ACT_WOWLAN;
+    mef_entry = &flt_cfg.mef_entry[0];
+
+    mef_entry->mode   = MEF_MODE_HOST_SLEEP;
+    mef_entry->action = MEF_ACTION_ALLOW_AND_WAKEUP_HOST;
+
+    for (i = 0; i < ptn_cfg->n_patterns; i++)
+    {
+        memset(byte_seq, 0, sizeof(byte_seq));
+        if (!is_wowlan_pattern_supported(&ptn_cfg->patterns[i], byte_seq))
+        {
+            PRINTM(MERROR, "Pattern not supported\n");
+            ret = -EOPNOTSUPP;
+            return ret;
+        }
+        if (!ptn_cfg->patterns[i].pkt_offset)
+        {
+            if (!(byte_seq[0] & 0x01) && (byte_seq[MAX_NUM_BYTE_SEQ] == 1))
+            {
+                flt_cfg.criteria |= CRITERIA_UNICAST;
+                continue;
+            }
+            else if (is_broadcast_ether_addr(byte_seq))
+            {
+                flt_cfg.criteria |= CRITERIA_BROADCAST;
+                continue;
+            }
+            else if ((!memcmp(byte_seq, ipv4_mc_mac, 2) && (byte_seq[MAX_NUM_BYTE_SEQ] == 2)) ||
+                     (!memcmp(byte_seq, ipv6_mc_mac, 3) && (byte_seq[MAX_NUM_BYTE_SEQ] == 3)))
+            {
+                flt_cfg.criteria |= CRITERIA_MULTICAST;
+                continue;
+            }
+        }
+
+        //    mef_entry->filter_item[filt_num].fill_flag =
+        //          (FILLING_TYPE | FILLING_REPEAT | FILLING_BYTE_SEQ |
+        //         FILLING_OFFSET);
+        mef_entry->filter_item[filt_num].repeat = 1;
+        mef_entry->filter_item[filt_num].offset = ptn_cfg->patterns[i].pkt_offset;
+        (void)memcpy((void *)mef_entry->filter_item[filt_num].byte_seq, (const void *)byte_seq, MAX_NUM_BYTE_SEQ);
+        mef_entry->filter_item[filt_num].num_byte_seq = byte_seq[MAX_NUM_BYTE_SEQ];
+        mef_entry->filter_item[filt_num].type         = TYPE_BYTE_EQ;
+        if (first_pat)
+            first_pat = false;
+        else
+            mef_entry->rpn[filt_num] = RPN_TYPE_OR;
+
+        filt_num++;
+    }
+    if (ptn_cfg->enable)
+    {
+        //   (void)memset(&flt_cfg, 0, sizeof(wlan_flt_cfg_t));
+
+        flt_cfg.criteria = CRITERIA_UNICAST | CRITERIA_BROADCAST | CRITERIA_MULTICAST;
+        flt_cfg.nentries = 1;
+
+        flt_cfg.mef_entry[0].mode   = MEF_MODE_HOST_SLEEP;
+        flt_cfg.mef_entry[0].action = MEF_ACTION_ALLOW_AND_WAKEUP_HOST;
+
+        flt_cfg.mef_entry[0].filter_num = 2;
+
+        flt_cfg.mef_entry[0].filter_item[filt_num].type         = TYPE_BYTE_EQ;
+        flt_cfg.mef_entry[0].filter_item[filt_num].repeat       = 16;
+        flt_cfg.mef_entry[0].filter_item[filt_num].offset       = 56;
+        flt_cfg.mef_entry[0].filter_item[filt_num].num_byte_seq = MLAN_MAC_ADDR_LENGTH;
+        (void)memcpy((void *)flt_cfg.mef_entry[0].filter_item[filt_num].byte_seq, (const void *)wlan.sta_mac,
+                     MLAN_MAC_ADDR_LENGTH);
+        if (filt_num)
+            flt_cfg.mef_entry[0].rpn[filt_num] = RPN_TYPE_OR;
+        filt_num++;
+        // flt_cfg.mef_entry.filter_item[1].fill_flag	  = (FILLING_TYPE | FILLING_REPEAT | FILLING_BYTE_SEQ |
+        // FILLING_OFFSET);
+        flt_cfg.mef_entry[0].filter_item[filt_num].type         = TYPE_BYTE_EQ;
+        flt_cfg.mef_entry[0].filter_item[filt_num].repeat       = 16;
+        flt_cfg.mef_entry[0].filter_item[filt_num].offset       = 28;
+        flt_cfg.mef_entry[0].filter_item[filt_num].num_byte_seq = MLAN_MAC_ADDR_LENGTH;
+        (void)memcpy((void *)flt_cfg.mef_entry[0].filter_item[filt_num].byte_seq, (const void *)wlan.sta_mac,
+                     MLAN_MAC_ADDR_LENGTH);
+        if (filt_num)
+            flt_cfg.mef_entry[0].rpn[filt_num] = RPN_TYPE_OR;
+        filt_num++;
+    }
+    flt_cfg.mef_entry[0].filter_num = filt_num;
+    return wifi_set_packet_filters(&flt_cfg);
+}
+
+
+int wlan_set_ipv6_ns_offload(void)
+{
+    wlan_flt_cfg_t flt_cfg;
+
+    (void)memset(&flt_cfg, 0, sizeof(wlan_flt_cfg_t));
+
+    flt_cfg.criteria = (MBIT(1) | MBIT(3));
+    flt_cfg.nentries = 1;
+
+    flt_cfg.mef_entry[0].mode   = MBIT(0);
+    flt_cfg.mef_entry[0].action = 0x40;
+
+    flt_cfg.mef_entry[0].filter_num = 2;
+
+    flt_cfg.mef_entry[0].filter_item[0].type         = TYPE_BYTE_EQ;
+    flt_cfg.mef_entry[0].filter_item[0].repeat       = 1;
+    flt_cfg.mef_entry[0].filter_item[0].offset       = 20;
+    flt_cfg.mef_entry[0].filter_item[0].num_byte_seq = 2;
+    (void)memcpy((void *)flt_cfg.mef_entry[0].filter_item[0].byte_seq, (const void *)"\x86\xdd", 2);
+    flt_cfg.mef_entry[0].rpn[1] = RPN_TYPE_AND;
+
+    flt_cfg.mef_entry[0].filter_item[1].type         = TYPE_BYTE_EQ;
+    flt_cfg.mef_entry[0].filter_item[1].repeat       = 1;
+    flt_cfg.mef_entry[0].filter_item[1].offset       = 62;
+    flt_cfg.mef_entry[0].filter_item[1].num_byte_seq = 1;
+    (void)memcpy((void *)flt_cfg.mef_entry[0].filter_item[1].byte_seq, (const void *)"\x87", 1);
+
+    return wifi_set_packet_filters(&flt_cfg);
+}
+
+int wlan_get_current_bssid(uint8_t *bssid)
+{
+    struct wlan_network* network = NULL;
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+    {
+        network = &wlan.networks[wlan.cur_network_idx];
+    }
+
+    if (network == NULL)
+    {
+        wlcm_e("cannot get network info");
+        return -WM_FAIL;
+    }
+    if (bssid != NULL)
+    {
+        (void)memcpy((void *)bssid, (const void *)network->bssid, IEEEtypes_ADDRESS_SIZE);
+        return WM_SUCCESS;
+    }
+
+    return -WM_FAIL;
+}
+
+uint8_t wlan_get_current_channel(void)
+{
+    struct wlan_network* network = NULL;
+
+    if (wlan.running && (is_state(CM_STA_CONNECTED) || is_state(CM_STA_ASSOCIATED)))
+    {
+        network = &wlan.networks[wlan.cur_network_idx];
+    }
+
+    if (network == NULL)
+    {
+        wlcm_e("cannot get network info");
+        return 0;
+    }
+
+    return (uint8_t)network->channel;
+}
+
+void wlan_sta_ampdu_tx_enable(void)
+{
+    wifi_sta_ampdu_tx_enable();
+}
+
+void wlan_sta_ampdu_tx_disable(void)
+{
+    wifi_sta_ampdu_tx_disable();
+}
+
+void wlan_sta_ampdu_rx_enable(void)
+{
+    wifi_sta_ampdu_rx_enable();
+}
+
+void wlan_sta_ampdu_rx_disable(void)
+{
+    wifi_sta_ampdu_rx_disable();
+}
+
+void wlan_uap_ampdu_tx_enable(void)
+{
+    wifi_uap_ampdu_tx_enable();
+}
+
+void wlan_uap_ampdu_tx_disable(void)
+{
+    wifi_uap_ampdu_tx_disable();
+}
+
+void wlan_uap_ampdu_rx_enable(void)
+{
+    wifi_uap_ampdu_rx_enable();
+}
+
+void wlan_uap_ampdu_rx_disable(void)
+{
+    wifi_uap_ampdu_rx_disable();
+}
+
+
+void wlan_uap_set_scan_chan_list(wifi_scan_chan_list_t scan_chan_list)
+{
+    wlan_uap_scan_chan_list_set = true;
+    (void)memcpy((void *)&wlan.scan_chan_list, (const void *)&scan_chan_list, sizeof(wifi_scan_chan_list_t));
+}
+
+void wlan_uap_set_beacon_period(const uint16_t beacon_period)
+{
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+    struct netif *netif = net_get_uap_interface();
+
+    wpa_supp_set_ap_beacon_int(netif, beacon_period);
+#endif
+#endif
+
+    wifi_uap_set_beacon_period(beacon_period);
+}
+
+int wlan_uap_set_bandwidth(const uint8_t bandwidth)
+{
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+    struct netif *netif = net_get_uap_interface();
+
+    wpa_supp_set_ap_bw(netif, bandwidth);
+#endif
+#endif
+
+    return wifi_uap_set_bandwidth(bandwidth);
+}
+
+int wlan_uap_get_bandwidth(uint8_t *bandwidth)
+{
+    *bandwidth = wifi_uap_get_bandwidth();
+    if (*bandwidth == BANDWIDTH_20MHZ || *bandwidth == BANDWIDTH_40MHZ
+#if CONFIG_11AC
+        || *bandwidth == BANDWIDTH_80MHZ
+#endif
+    )
+    {
+        return WM_SUCCESS;
+    }
+    else
+    {
+        return -WM_FAIL;
+    }
+}
+
+int wlan_uap_set_hidden_ssid(const t_u8 hidden_ssid)
+{
+    if (hidden_ssid != 0 && hidden_ssid != 1 && hidden_ssid != 2)
+    {
+        return -WM_FAIL;
+    }
+
+    if (is_uap_started())
+    {
+        (void)PRINTF("Pls set hidden_ssid before start uAP.\r\n");
+        return -WM_FAIL;
+    }
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+    struct netif *netif = net_get_uap_interface();
+
+    wpa_supp_set_ap_hidden_ssid(netif, hidden_ssid);
+#endif
+#endif
+
+    wifi_uap_set_hidden_ssid(hidden_ssid);
+
+    return WM_SUCCESS;
+}
+
+void wlan_uap_ctrl_deauth(const bool enable)
+{
+    (void)wifi_uap_ctrl_deauth(enable);
+}
+
+void wlan_uap_set_ecsa(void)
+{
+    wifi_uap_set_ecsa();
+}
+
+void wlan_uap_set_htcapinfo(const uint16_t ht_cap_info)
+{
+    wifi_uap_set_htcapinfo(ht_cap_info);
+}
+
+void wlan_uap_set_httxcfg(unsigned short httxcfg)
+{
+    wifi_uap_set_httxcfg(httxcfg);
+}
+
+
+int wlan_set_rts(int rts)
+{
+    return wifi_set_rts(rts, MLAN_BSS_TYPE_STA);
+}
+
+int wlan_set_uap_rts(int rts)
+{
+    return wifi_set_rts(rts, MLAN_BSS_TYPE_UAP);
+}
+
+#if CONFIG_WIFI_FRAG_THRESHOLD
+int wlan_set_frag(int frag)
+{
+    return wifi_set_frag(frag, MLAN_BSS_TYPE_STA);
+}
+
+int wlan_set_uap_frag(int frag)
+{
+    return wifi_set_frag(frag, MLAN_BSS_TYPE_UAP);
+}
+#endif
+
+#if CONFIG_11K
+int _wlan_rrm_scan_cb(unsigned int count)
+{
+    t_u16 i;
+    t_u8 *rep_buf = NULL;
+    t_u8 *buf_pos = NULL;
+    /* The sufficient size is the length including reporting frame body */
+    t_u16 suffi_len           = 250U;
+    t_u32 pos_last_indication = 0U;
+    bool match_ap_found       = false;
+    int meas_report_len       = 0;
+
+    /* process scan result */
+#if !CONFIG_MEM_POOLS
+    rep_buf = (t_u8 *)OSA_MemoryAllocate(BEACON_REPORT_BUF_SIZE);
+#else
+    rep_buf = (t_u8 *)OSA_MemoryPoolAllocate(buf_1536_MemoryPool);
+#endif
+
+    if (rep_buf == NULL)
+    {
+        PRINTM(MERROR, "Cannot allocate memory for report buffer");
+        return -1;
+    }
+
+    (void)memset(rep_buf, 0, BEACON_REPORT_BUF_SIZE);
+    buf_pos = rep_buf;
+    for (i = 0; i < count; i++)
+    {
+        if (wlan_rrm_matched_ap_found(&wlan.rrm_scan_cb_param.rep_data, &mlan_adap->pscan_table[i]))
+        {
+            wlan_add_rm_beacon_report(&wlan.rrm_scan_cb_param.rep_data, &mlan_adap->pscan_table[i], &buf_pos,
+                                      BEACON_REPORT_BUF_SIZE - (buf_pos - rep_buf), &pos_last_indication);
+        }
+
+        /* If current rep_buf is not enough and still have AP not added, just send the report */
+        if ((buf_pos + suffi_len - rep_buf > BEACON_REPORT_BUF_SIZE) && (i < count - 1U) &&
+            wlan_rrm_matched_ap_found(&wlan.rrm_scan_cb_param.rep_data, &mlan_adap->pscan_table[i + 1U]))
+        {
+            match_ap_found  = 1;
+            meas_report_len = buf_pos - rep_buf;
+            /* send beacon report, not the last one */
+            wlan_send_mgmt_rm_beacon_report(wlan.rrm_scan_cb_param.dialog_tok, wlan.sta_mac,
+                                            wlan.rrm_scan_cb_param.dst_addr, rep_buf, (t_u32)meas_report_len,
+                                            (bool)wlan.rrm_scan_cb_param.protect);
+            /* Prepare for the next beacon report */
+            (void)memset(rep_buf, 0, BEACON_REPORT_BUF_SIZE);
+            buf_pos = rep_buf;
+        }
+
+        /* Last AP in scan table, and matched AP found */
+        if ((i == count - 1U) && (buf_pos > rep_buf))
+        {
+            match_ap_found = 1;
+            /* Update last indication, the last one */
+            if (wlan.rrm_scan_cb_param.rep_data.last_ind != 0U && pos_last_indication != 0U)
+            {
+                *(char *)pos_last_indication = (char)1U;
+            }
+            meas_report_len = buf_pos - rep_buf;
+            /* send beacon report, the last one */
+            wlan_send_mgmt_rm_beacon_report(wlan.rrm_scan_cb_param.dialog_tok, wlan.sta_mac,
+                                            wlan.rrm_scan_cb_param.dst_addr, rep_buf, (t_u32)meas_report_len,
+                                            (bool)wlan.rrm_scan_cb_param.protect);
+        }
+    }
+
+    /* If no matched AP found, no beacon report detail */
+    if (!match_ap_found)
+    {
+        *buf_pos++ = (t_u8)MEASURE_REPORT;
+        /* Tag length */
+        *buf_pos++      = 3;
+        *buf_pos++      = wlan.rrm_scan_cb_param.rep_data.token;
+        *buf_pos++      = WLAN_RRM_REPORT_MODE_ACCEPT;
+        *buf_pos++      = WLAN_RRM_MEASURE_TYPE_BEACON;
+        meas_report_len = buf_pos - rep_buf;
+        /* send beacon report */
+        wlan_send_mgmt_rm_beacon_report(wlan.rrm_scan_cb_param.dialog_tok, wlan.sta_mac,
+                                        wlan.rrm_scan_cb_param.dst_addr, rep_buf, (t_u32)meas_report_len,
+                                        (bool)wlan.rrm_scan_cb_param.protect);
+    }
+#if !CONFIG_MEM_POOLS
+    OSA_MemoryFree(rep_buf);
+#else
+    OSA_MemoryPoolFree(buf_1536_MemoryPool, rep_buf);
+#endif
+
+    return 0;
+}
+
+void wlan_rrm_request_scan(wlan_scan_params_v2_t *wlan_scan_param, wlan_rrm_scan_cb_param *scan_cb_param)
+{
+    char ssid[(MLAN_MAX_SSID_LENGTH + 1) * MRVDRV_MAX_SSID_LIST_LENGTH]  = {0};
+    uint8_t ssid_num = 0, ssid_off = 0;
+#if CONFIG_COMBO_SCAN
+    memcpy(ssid+ssid_off, wlan_scan_param->ssid[0], strlen(wlan_scan_param->ssid[0]));
+    ssid_off += strlen(wlan_scan_param->ssid[0]);
+    ssid[ssid_off] = '\0';
+    ssid_off++;
+    ssid_num++;
+
+    if (strlen(wlan_scan_param->ssid[1]))
+    {
+        memcpy(ssid+ssid_off, wlan_scan_param->ssid[1], strlen(wlan_scan_param->ssid[1]));
+        ssid_off += strlen(wlan_scan_param->ssid[1]);
+        ssid[ssid_off] = '\0';
+        ssid_num++;
+    }
+#else
+    memcpy(ssid + ssid_off, wlan_scan_param->ssid, strlen(wlan_scan_param->ssid));
+    ssid_off += strlen(wlan_scan_param->ssid);
+    ssid[ssid_off] = '\0';
+    ssid_off++;
+    ssid_num++;
+#endif
+
+    if (wlan_scan_param == NULL || scan_cb_param == NULL)
+    {
+        wlcm_d("ignoring scan request with NULL scan or cb params");
+        return;
+    }
+    if (!is_scanning_allowed())
+    {
+        wlcm_d("ignoring scan request in invalid state");
+        return;
+    }
+
+    (void)memcpy(&wlan.rrm_scan_cb_param, scan_cb_param, sizeof(wlan_rrm_scan_cb_param));
+
+#if CONFIG_SCAN_CHANNEL_GAP
+    if (is_uap_started() || is_sta_connected())
+        wlan_scan_param->scan_chan_gap = scan_channel_gap;
+    else
+        wlan_scan_param->scan_chan_gap = (t_u16)0U;
+#endif
+
+    int ret = wifi_send_scan_cmd((t_u8)BSS_ANY, wlan_scan_param->bssid,
+                                 ssid, ssid_num,
+                                 wlan_scan_param->num_channels, wlan_scan_param->chan_list, wlan_scan_param->num_probes,
+#if CONFIG_SCAN_WITH_RSSIFILTER
+                                 wlan_scan_param->rssi_threshold,
+#endif
+#if CONFIG_SCAN_CHANNEL_GAP
+                                 wlan_scan_param->scan_chan_gap,
+#endif
+                                 false, false);
+    if (ret == WM_SUCCESS)
+    {
+        wlan.scan_cb       = (int (*)(unsigned int count))(wlan_scan_param->cb);
+        wlan.sta_return_to = wlan.sta_state;
+        wlan.sta_state     = CM_STA_SCANNING_USER;
+    }
+    else
+    {
+        wlcm_e("wifi send scan cmd failed");
+    }
+}
+#endif
+
+
+#if CONFIG_SCAN_CHANNEL_GAP
+void wlan_set_scan_channel_gap(unsigned scan_chan_gap)
+{
+    scan_channel_gap = (t_u16)scan_chan_gap;
+    return;
+}
+#endif
+
+#if CONFIG_11K
+int wlan_host_11k_cfg(int enable_11k)
+{
+#if CONFIG_WPA_SUPP
+    wlan.enable_11k = enable_11k;
+    return WM_SUCCESS;
+#else
+    return wifi_host_11k_cfg(enable_11k);
+#endif
+}
+
+bool wlan_get_host_11k_status(void)
+{
+    return wlan.enable_11k;
+}
+
+int wlan_host_11k_neighbor_req(const char *ssid)
+{
+    int ret = -WM_FAIL;
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+    if (!is_sta_connected())
+    {
+        wlcm_d("Error: sta connection is required before sending neighbor report req");
+        return -WM_FAIL;
+    }
+
+#if CONFIG_WPA_SUPP
+    ret = wpa_supp_send_neighbor_rep(netif, (char *)ssid, 0, 0);
+#else
+    ret = wifi_host_11k_neighbor_req(ssid);
+#endif
+    if (ret == WM_SUCCESS)
+    {
+        wlan.neighbor_req = true;
+        (void)OSA_TimerActivate((osa_timer_handle_t)wlan.neighbor_req_timer);
+    }
+    return ret;
+}
+#endif
+
+#if CONFIG_11V
+int wlan_host_11v_bss_trans_query(t_u8 query_reason)
+{
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+#else
+    int ret = -WM_FAIL;
+#endif
+
+    if (!is_sta_connected())
+    {
+        wlcm_d("Error: sta connection is required before sending bss transition query");
+        return -WM_FAIL;
+    }
+
+#if CONFIG_WPA_SUPP
+    return wpa_supp_send_btm_query(netif, query_reason);
+#else
+    ret = wifi_host_11v_bss_trans_query(query_reason);
+    if (ret == WM_SUCCESS)
+    {
+        wlan.neighbor_req = true;
+        (void)OSA_TimerActivate((osa_timer_handle_t)wlan.neighbor_req_timer);
+    }
+    return ret;
+#endif
+}
+#endif
+
+#if !CONFIG_WPA_SUPP
+#if CONFIG_DRIVER_MBO
+int wlan_host_mbo_cfg(int enable_mbo)
+{
+    return wifi_host_mbo_cfg(enable_mbo);
+}
+
+int wlan_mbo_peferch_cfg(t_u8 ch0, t_u8 pefer0, t_u8 ch1, t_u8 pefer1)
+{
+    uint8_t ap_addr[IEEEtypes_ADDRESS_SIZE];
+    if (is_sta_connected())
+    {
+        (void)wlan_get_current_bssid(ap_addr);
+        return wifi_mbo_send_preferch_wnm(wlan.sta_mac, (t_u8 *)ap_addr, ch0, pefer0, ch1, pefer1);
+    }
+    else
+    {
+        return wifi_mbo_preferch_cfg(ch0, pefer0, ch1, pefer1);
+    }
+}
+#endif
+#endif
+
+#if (CONFIG_11MC) || (CONFIG_11AZ)
+int wlan_unassoc_ftm_cfg(const t_u16 action, const t_u16 config)
+{
+	return wifi_unassoc_ftm_cfg(action, config);
+}
+
+int wlan_ftm_start_stop(const t_u16 action, const t_u8 loop_cnt, const t_u8 *mac, const t_u8 channel)
+{
+	return wifi_ftm_start_stop(action, loop_cnt, mac, channel);
+}
+
+int wlan_ftm_cfg(const t_u8 protocol, ranging_11az_cfg_t *ftm_ranging_cfg)
+{
+	return wifi_ftm_cfg(protocol, ftm_ranging_cfg);
+}
+
+int wlan_ftm_11mc_cfg(ftm_11mc_nego_cfg_t *ftm_11mc_nego_cfg)
+{
+	return wifi_ftm_11mc_cfg(ftm_11mc_nego_cfg);
+}
+
+int wlan_ftm_location_cfg(location_cfg_info_t *ftm_location_cfg)
+{
+	return wifi_ftm_location_cfg(ftm_location_cfg);
+}
+
+int wlan_ftm_civic_cfg(location_civic_rep_t *ftm_civic_cfg)
+{
+	return wifi_ftm_civic_cfg(ftm_civic_cfg);
+}
+#endif
+
+#if CONFIG_WPA_SUPP
+#if (CONFIG_11AX && defined(CONFIG_MBO))
+int wlan_mbo_peferch_cfg(const char *non_pref_chan)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_mbo_update_non_pref_chan(netif, non_pref_chan);
+}
+
+int wlan_mbo_set_cell_capa(t_u8 cell_capa)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    if (cell_capa != 1 && cell_capa != 2 && cell_capa != 3)
+    {
+        return -WM_E_PERM;
+    }
+
+    return wpa_supp_mbo_set_cell_capa(netif, cell_capa);
+}
+
+int wlan_mbo_set_oce(t_u8 oce)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    if (oce != 1 && oce != 2)
+    {
+        return -WM_E_PERM;
+    }
+
+    return wpa_supp_mbo_set_oce(netif, oce);
+
+}
+#endif
+
+int wlan_set_okc(t_u8 okc)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    if (okc != 0 && okc != 1)
+    {
+        return -WM_E_PERM;
+    }
+
+    return wpa_supp_set_okc(netif, okc);
+
+}
+
+int wlan_pmksa_list(char *buf, size_t buflen)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_pmksa_list(netif, buf, buflen);
+}
+
+int wlan_pmksa_flush(void)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_pmksa_flush(netif);
+}
+
+int wlan_set_scan_interval(int scan_int)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_set_scan_interval(netif, scan_int);
+}
+#endif
+
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+int wlan_set_sta_mac_filter(int filter_mode, int mac_count, unsigned char *mac_addr)
+{
+#if CONFIG_WPA_SUPP
+    return wlan_host_set_sta_mac_filter(filter_mode, mac_count, mac_addr);
+#else
+    return wifi_set_sta_mac_filter(filter_mode, mac_count, mac_addr);
+#endif
+}
+#endif
+
+#if CONFIG_WPA2_ENTP
+void wlan_enable_wpa2_enterprise_ap_only(void)
+{
+    wlan.allow_wpa2_enterprise_ap_only = true;
+    wifi_scan_enable_wpa2_enterprise_ap_only();
+}
+#endif
+
+void wlan_version_extended(void)
+{
+#if SDK_DEBUGCONSOLE != DEBUGCONSOLE_DISABLE
+    char *version_str;
+
+    version_str = wlan_get_firmware_version_ext();
+
+    (void)PRINTF("WLAN Driver Version   : %s\r\n", WLAN_DRV_VERSION);
+    (void)PRINTF("WLAN Firmware Version : %s\r\n", version_str);
+#endif
+}
+
+#if CONFIG_WIFI_TX_PER_TRACK
+void wlan_set_tx_pert(struct wlan_tx_pert_info *tx_pert, mlan_bss_type bss_type)
+{
+    int ret = WM_SUCCESS;
+
+    ret = wifi_set_tx_pert((void *)tx_pert, bss_type);
+    if (ret != WM_SUCCESS)
+        (void)PRINTF("Failed to set tx per tracking.\r\n");
+    return;
+}
+#endif
+
+#if CONFIG_TX_RX_HISTOGRAM
+void wlan_set_txrx_histogram(struct wlan_txrx_histogram_info *txrx_histogram, t_u8 *data)
+{
+    int ret = WM_SUCCESS;
+
+    wifi_set_txrx_histogram((void *)txrx_histogram, data);
+    if (ret != WM_SUCCESS)
+        (void)PRINTF("Failed to set txrx histogram config.\r\n");
+    return;
+}
+#endif
+
+#if CONFIG_ROAMING
+int wlan_set_roaming(const int enable, const uint8_t rssi_low_threshold)
+{
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_sta_interface();
+#endif
+
+    wlan.roaming_enabled = enable;
+
+#if CONFIG_WPA_SUPP
+    wpa_supp_set_okc(netif, wlan.roaming_enabled == true ? 0 : 1);
+#endif
+
+    wlan.rssi_low_threshold = rssi_low_threshold;
+
+    return wifi_config_roaming(enable, &wlan.rssi_low_threshold);
+}
+
+int wlan_get_roaming_status(void)
+{
+    return wlan.roaming_enabled;
+}
+#endif
+
+#if CONFIG_WIFI_MEM_ACCESS
+int wlan_mem_access(uint16_t action, uint32_t addr, uint32_t *value)
+{
+    return wifi_mem_access(action, addr, value);
+}
+#endif
+
+#if CONFIG_WIFI_BOOT_SLEEP
+int wlan_boot_sleep(uint16_t action, uint16_t *enable)
+{
+
+    if ((*enable != 0) && (*enable != 1))
+    {
+        return -WM_FAIL;
+    }
+
+    return wifi_boot_sleep(action, enable);
+}
+#endif
+
+#if CONFIG_RF_TEST_MODE
+
+int wlan_set_rf_test_mode(void)
+{
+    wlan_ieeeps_off();
+    wlan_deepsleepps_off();
+    return wifi_set_rf_test_mode();
+}
+
+int wlan_unset_rf_test_mode(void)
+{
+    (void)wifi_unset_rf_test_mode();
+#if CONFIG_WIFI_AUTO_POWER_SAVE
+    wlan_deepsleepps_on();
+    wlan_ieeeps_on(wlan.wakeup_conditions);
+#endif
+    return WM_SUCCESS;
+}
+
+int wlan_set_rf_channel(const uint8_t channel)
+{
+    return wifi_set_rf_channel(channel);
+}
+
+int wlan_set_rf_radio_mode(const uint8_t mode)
+{
+    return wifi_set_rf_radio_mode(mode);
+}
+
+int wlan_get_rf_channel(uint8_t *channel)
+{
+    if (channel != NULL)
+        return wifi_get_rf_channel(channel);
+
+    return -WM_FAIL;
+}
+
+int wlan_get_rf_radio_mode(uint8_t *mode)
+{
+    if (mode)
+        return wifi_get_rf_radio_mode(mode);
+
+    return -WM_FAIL;
+}
+
+int wlan_set_rf_bandwidth(const uint8_t bandwidth)
+{
+    return wifi_set_rf_bandwidth(bandwidth);
+}
+
+int wlan_set_rf_band(const uint8_t band)
+{
+    return wifi_set_rf_band(band);
+}
+
+int wlan_get_rf_band(uint8_t *band)
+{
+    if (band != NULL)
+        return wifi_get_rf_band(band);
+
+    return -WM_FAIL;
+}
+
+int wlan_get_rf_bandwidth(uint8_t *bandwidth)
+{
+    if (bandwidth != NULL)
+        return wifi_get_rf_bandwidth(bandwidth);
+
+    return -WM_FAIL;
+}
+
+int wlan_get_rf_per(uint32_t *rx_tot_pkt_count, uint32_t *rx_mcast_bcast_count, uint32_t *rx_pkt_fcs_error)
+{
+    if ((rx_tot_pkt_count != NULL) && (rx_mcast_bcast_count != NULL) && (rx_pkt_fcs_error != NULL))
+        return wifi_get_rf_per(rx_tot_pkt_count, rx_mcast_bcast_count, rx_pkt_fcs_error);
+
+    return -WM_FAIL;
+}
+
+int wlan_set_rf_tx_cont_mode(const uint32_t enable_tx,
+                             const uint32_t cw_mode,
+                             const uint32_t payload_pattern,
+                             const uint32_t cs_mode,
+                             const uint32_t act_sub_ch,
+                             const uint32_t tx_rate)
+{
+    return wifi_set_rf_tx_cont_mode(enable_tx, cw_mode, payload_pattern, cs_mode, act_sub_ch, tx_rate);
+}
+
+int wlan_set_rf_tx_antenna(const uint8_t antenna)
+{
+    return wifi_set_rf_tx_antenna(antenna);
+}
+
+int wlan_get_rf_tx_antenna(uint8_t *antenna)
+{
+    if (antenna != NULL)
+        return wifi_get_rf_tx_antenna(antenna);
+
+    return -WM_FAIL;
+}
+
+int wlan_set_rf_rx_antenna(const uint8_t antenna)
+{
+    return wifi_set_rf_rx_antenna(antenna);
+}
+
+int wlan_get_rf_rx_antenna(uint8_t *antenna)
+{
+    if (antenna != NULL)
+        return wifi_get_rf_rx_antenna(antenna);
+
+    return -WM_FAIL;
+}
+
+int wlan_set_rf_tx_power(const uint32_t power, const uint8_t mod, const uint8_t path_id)
+{
+    return wifi_set_rf_tx_power(power, mod, path_id);
+}
+
+int wlan_cfg_rf_he_tb_tx(uint16_t enable,uint16_t qnum,uint16_t aid,uint16_t axq_mu_timer,int16_t tx_power)
+{
+	return wifi_cfg_rf_he_tb_tx(enable, qnum, aid,axq_mu_timer,tx_power);
+}
+
+int wlan_rf_trigger_frame_cfg(uint32_t Enable_tx,uint32_t Standalone_hetb,uint8_t FRAME_CTRL_TYPE,
+                              uint8_t FRAME_CTRL_SUBTYPE,uint16_t FRAME_DURATION,uint64_t TriggerType,
+							  uint64_t UlLen,uint64_t MoreTF,uint64_t CSRequired,uint64_t UlBw,
+							  uint64_t LTFType,uint64_t LTFMode,uint64_t LTFSymbol,uint64_t UlSTBC,
+							  uint64_t LdpcESS,uint64_t ApTxPwr,uint64_t PreFecPadFct,
+							  uint64_t PeDisambig,uint64_t SpatialReuse,uint64_t Doppler,
+							  uint64_t HeSig2,uint32_t AID12,uint32_t RUAllocReg,uint32_t RUAlloc,
+							  uint32_t UlCodingType,uint32_t UlMCS,uint32_t UlDCM,uint32_t SSAlloc,
+							  uint8_t UlTargetRSSI,uint8_t MPDU_MU_SF,uint8_t TID_AL,uint8_t AC_PL,
+							  uint8_t Pref_AC)
+{
+	return wifi_rf_trigger_frame_cfg(Enable_tx,Standalone_hetb,FRAME_CTRL_TYPE,
+                                     FRAME_CTRL_SUBTYPE,FRAME_DURATION,TriggerType,
+			                         UlLen,MoreTF,CSRequired,UlBw,LTFType,LTFMode,
+			                         LTFSymbol,UlSTBC,LdpcESS,ApTxPwr,PreFecPadFct,
+			                         PeDisambig,SpatialReuse,Doppler,HeSig2,AID12,
+			                         RUAllocReg,RUAlloc,UlCodingType,UlMCS,UlDCM,
+			                         SSAlloc,UlTargetRSSI,MPDU_MU_SF,TID_AL,AC_PL,
+			                         Pref_AC);
+}
+
+int wlan_set_rf_tx_frame(const uint32_t enable,
+                         const uint32_t data_rate,
+                         const uint32_t frame_pattern,
+                         const uint32_t frame_length,
+                         const uint16_t adjust_burst_sifs,
+                         const uint32_t burst_sifs_in_us,
+                         const uint32_t short_preamble,
+                         const uint32_t act_sub_ch,
+                         const uint32_t short_gi,
+                         const uint32_t adv_coding,
+                         const uint32_t tx_bf,
+                         const uint32_t gf_mode,
+                         const uint32_t stbc,
+                         const uint8_t *bssid)
+{
+    return wifi_set_rf_tx_frame(enable, data_rate, frame_pattern, frame_length, adjust_burst_sifs, burst_sifs_in_us,
+                                short_preamble, act_sub_ch, short_gi, adv_coding, tx_bf, gf_mode, stbc, bssid);
+}
+
+int wlan_set_rf_otp_mac_addr(uint8_t *mac)
+{
+    return wifi_set_rf_otp_mac_addr(mac);
+}
+
+int wlan_get_rf_otp_mac_addr(uint8_t *mac)
+{
+    if (mac != NULL)
+      return wifi_get_rf_otp_mac_addr(mac);
+
+    return -WM_FAIL;
+}
+
+int wlan_set_rf_otp_cal_data(const uint8_t *cal_data, uint32_t cal_data_len)
+{
+    return wifi_set_rf_otp_cal_data(cal_data, cal_data_len);
+}
+
+int wlan_get_rf_otp_cal_data(uint8_t *cal_data)
+{
+    if (cal_data != NULL)
+      return wifi_get_rf_otp_cal_data(cal_data);
+
+    return -WM_FAIL;
+}
+#endif
+#if CONFIG_WIFI_FW_DEBUG
+void wlan_register_fw_dump_cb(void (*wlan_usb_init_cb)(void),
+                              int (*wlan_usb_mount_cb)(),
+                              int (*wlan_usb_file_open_cb)(char *test_file_name),
+                              int (*wlan_usb_file_write_cb)(uint8_t *data, size_t data_len),
+                              int (*wlan_usb_file_close_cb)())
+{
+    wlan.wlan_usb_init_cb = wlan_usb_init_cb;
+    wifi_register_fw_dump_cb(wlan_usb_mount_cb, wlan_usb_file_open_cb, wlan_usb_file_write_cb, wlan_usb_file_close_cb);
+}
+#endif
+
+#if CONFIG_WMM
+void wlan_wmm_tx_stats_dump(int bss_type)
+{
+    wifi_wmm_tx_stats_dump(bss_type);
+}
+#endif
+
+int wlan_send_hostcmd(
+    const void *cmd_buf, uint32_t cmd_buf_len, void *host_resp_buf, uint32_t resp_buf_len, uint32_t *reqd_resp_len)
+{
+    if ((cmd_buf == NULL) || (host_resp_buf == NULL) || (reqd_resp_len == NULL))
+    {
+        return (int)WM_E_NOMEM;
+    }
+    if (!cmd_buf_len || !resp_buf_len)
+    {
+        return (int)WM_E_INVAL;
+    }
+
+    return wifi_send_hostcmd(cmd_buf, cmd_buf_len, host_resp_buf, resp_buf_len, reqd_resp_len);
+}
+
+#if CONFIG_11AX
+int wlan_enable_disable_htc(uint8_t option)
+{
+    int ret                 = -WM_FAIL;
+    uint8_t send_htc_set[]  = {0x8b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x24, 0x01, 0x01, 0x00, 0x00, 0x00};
+    uint8_t debug_resp_buf[32] = {0};
+    uint32_t reqd_len       = 0;
+
+    send_htc_set[12] = option;
+
+    ret = wlan_send_hostcmd(send_htc_set, sizeof(send_htc_set) / sizeof(uint8_t), debug_resp_buf, sizeof(debug_resp_buf),
+                            &reqd_len);
+
+    return ret;
+}
+
+int wlan_send_debug_htc(const uint8_t count,
+		const uint8_t vht,
+		const uint8_t he,
+		const uint8_t rxNss,
+		const uint8_t channelWidth,
+		const uint8_t ulMuDisable,
+		const uint8_t txNSTS,
+		const uint8_t erSuDisable,
+		const uint8_t dlResoundRecomm,
+		const uint8_t ulMuDataDisable)
+{
+    int ret           = -WM_FAIL;
+    int i;
+    uint8_t debug_cmd_buf[] = {0x8b, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x11, 0x01, 0x40, 0x01, 0x01, 0x00,
+			0x02, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+    uint8_t debug_resp_buf[32] = {0};
+    uint32_t reqd_len = 0;
+
+    (void)memset(debug_resp_buf, 0, sizeof(debug_resp_buf));
+
+    debug_cmd_buf[12] = count;
+    debug_cmd_buf[13] = vht;
+    debug_cmd_buf[14] = he;
+    debug_cmd_buf[15] = rxNss;
+    debug_cmd_buf[16] = channelWidth;
+    debug_cmd_buf[17] = ulMuDisable;
+    debug_cmd_buf[18] = txNSTS;
+    debug_cmd_buf[19] = erSuDisable;
+    debug_cmd_buf[20] = dlResoundRecomm;
+    debug_cmd_buf[21] = ulMuDataDisable;
+
+    ret = wlan_send_hostcmd(debug_cmd_buf, sizeof(debug_cmd_buf) / sizeof(uint8_t), debug_resp_buf, sizeof(debug_resp_buf),
+                            &reqd_len);
+    if (ret == WM_SUCCESS)
+    {
+        (void)PRINTF("Hostcmd success, response is\r\n");
+        for (i = 0; i < reqd_len; i++)
+            (void)PRINTF("%x\t", debug_resp_buf[i]);
+    }
+    else
+    {
+        (void)PRINTF("Hostcmd failed error: %d", ret);
+    }
+    return ret;
+}
+int wlan_set_11ax_tx_omi(const t_u8 interface, const t_u16 tx_omi, const t_u8 tx_option, const t_u8 num_data_pkts)
+{
+    if (interface == MLAN_BSS_TYPE_STA)
+    {
+
+        if (num_data_pkts > 16)
+        {
+            (void)PRINTF("Minimum value of num_data_pkts should be 1 and maximum should be 16");
+            return -WM_FAIL;
+        }
+
+        if (is_sta_connected())
+        {
+            return wifi_set_11ax_tx_omi(MLAN_BSS_TYPE_STA, tx_omi, tx_option, num_data_pkts);
+        }
+        else
+        {
+            wifi_d("STA not connected");
+            return -WM_FAIL;
+        }
+    }
+    else if (interface == MLAN_BSS_TYPE_UAP)
+    {
+        if (is_uap_started())
+        {
+            return wifi_set_11ax_tx_omi(MLAN_BSS_TYPE_UAP, tx_omi, tx_option, num_data_pkts);
+        }
+        else
+        {
+            wifi_d("uAP not started");
+            return -WM_FAIL;
+        }
+    }
+    else
+    {
+        wifi_d("Interface not supported");
+        return -WM_FAIL;
+    }
+}
+
+int wlan_set_11ax_tol_time(const t_u32 tol_time)
+{
+    if (tol_time < 1 || tol_time > 3600)
+    {
+        wlcm_d("Error: invalid tolerance time value, range[[1..3600]].");
+        return -WM_FAIL;
+        ;
+    }
+
+    if (is_sta_connecting())
+    {
+        wlcm_d("Pls set OBSS Tolerance Time value before connecting to AP.");
+        return -WM_FAIL;
+    }
+
+    return wifi_set_11ax_tol_time(tol_time);
+}
+
+int wlan_set_11ax_rutxpowerlimit(const void *rutx_pwr_cfg, uint32_t rutx_pwr_cfg_len)
+{
+    if (rutx_pwr_cfg != NULL)
+    {
+        return wifi_set_11ax_rutxpowerlimit(rutx_pwr_cfg, rutx_pwr_cfg_len);
+    }
+
+    return -WM_FAIL;
+}
+
+
+int wlan_set_11ax_rutxpowerlimit_legacy(const wifi_rutxpwrlimit_t *ru_pwr_cfg)
+{
+    if (ru_pwr_cfg != NULL)
+    {
+        return wifi_set_11ax_rutxpowerlimit_legacy(ru_pwr_cfg);
+    }
+
+    return -WM_FAIL;
+}
+
+int wlan_get_11ax_rutxpowerlimit_legacy(wifi_rutxpwrlimit_t *ru_pwr_cfg)
+{
+    if (ru_pwr_cfg != NULL)
+    {
+        (void)memset(ru_pwr_cfg, 0x00, sizeof(wlan_rutxpwrlimit_t));
+        return wifi_get_11ax_rutxpowerlimit_legacy(ru_pwr_cfg);
+    }
+
+    return -WM_FAIL;
+}
+
+/* cfg tables for 11axcfg and twt commands to FW */
+static uint8_t g_11ax_cfg_default[] = {
+    /* band */
+    0x03,
+    /* HE cap */
+    0xff, 0x00,                                                       // ID
+    0x18, 0x00,                                                       // Length
+    0x23,                                                             // he capability id
+    0x03, 0x08, 0x00, 0x82, 0x00, 0x00,                               // HE MAC capability info
+    0x40, 0x50, 0x42, 0x49, 0x0d, 0x00, 0x20, 0x1e, 0x17, 0x31, 0x00, // HE PHY capability info
+    0xfd, 0xff, 0xfd, 0xff,                                           // Tx Rx HE-MCS NSS support
+    0x88, 0x1f, 0x00, 0x00
+};
+
+
+int wlan_set_11ax_cfg(wlan_11ax_config_t *ax_config)
+{
+    return wifi_set_11ax_cfg(ax_config);
+}
+
+uint8_t * wlan_get_11ax_cfg(void)
+{
+    return g_11ax_cfg_default;
+}
+
+#if CONFIG_11AX_TWT
+static uint8_t g_btwt_cfg_default[] = {/* action */
+                               0x01, 0x00,
+                               /* sub_id */
+                               0x25, 0x01,
+                               /* btwt_cfg */
+                               0x40, 0x04, 0x63, 0x00, 0x70, 0x02, 0x0a, 0x05};
+
+int wlan_set_btwt_cfg(const wlan_btwt_config_t *btwt_config)
+{
+    return wifi_set_btwt_cfg(btwt_config);
+}
+
+uint8_t * wlan_get_btwt_cfg(void)
+{
+    return g_btwt_cfg_default;
+}
+
+static uint8_t g_twt_setup_cfg_default[] = {0x01, 0x00, 0x00, 0x01, 0x00, 0x40, 0x00, 0x01, 0x0a, 0x00, 0x02, 0x00};
+
+/* Below macros are defined as in FW under dot11ax_twt.c */
+#define TWT_EARLY_WAKEUP_ADJUSTMENT 1000                                // us
+#define TWT_SLEEP_MIN               (756 + TWT_EARLY_WAKEUP_ADJUSTMENT) // us
+int wlan_set_twt_setup_cfg(const wlan_twt_setup_config_t *twt_setup)
+{
+    if (((twt_setup->twt_mantissa << twt_setup->twt_exponent) - (twt_setup->twt_wakeup_duration * 256)) < TWT_SLEEP_MIN)
+    {
+        wlcm_e("Service period (SP) value is : %u us", twt_setup->twt_mantissa << twt_setup->twt_exponent);
+        wlcm_e("Wakeup duration (WD) value is : %u us", twt_setup->twt_wakeup_duration * 256);
+        wlcm_e("Minimum sleep time (SP - WD) should be greater than: %u us", TWT_SLEEP_MIN);
+        return -WM_FAIL;
+    }
+    return wifi_set_twt_setup_cfg(twt_setup);
+}
+
+uint8_t * wlan_get_twt_setup_cfg(void)
+{
+    return g_twt_setup_cfg_default;
+}
+
+static uint8_t g_twt_teardown_cfg_default[] = {0x00, 0x00, 0x00};
+
+int wlan_set_twt_teardown_cfg(const wlan_twt_teardown_config_t *teardown_config)
+{
+    return wifi_set_twt_teardown_cfg(teardown_config);
+}
+
+uint8_t * wlan_get_twt_teardown_cfg(void)
+{
+    return g_twt_teardown_cfg_default;
+}
+
+int wlan_get_twt_report(wlan_twt_report_t *twt_report)
+{
+    return wifi_get_twt_report(twt_report);
+}
+
+#endif /* CONFIG_11AX_TWT */
+#endif /* CONFIG_11AX */
+
+#if CONFIG_WIFI_CLOCKSYNC
+int wlan_get_tsf_info(wlan_tsf_info_t *tsf_info)
+{
+    return wifi_get_tsf_info(tsf_info);
+}
+int wlan_set_clocksync_cfg(const wlan_clock_sync_gpio_tsf_t *tsf_latch)
+{
+    return wifi_set_clocksync_cfg(tsf_latch, (mlan_bss_type)WLAN_BSS_TYPE_STA);
+}
+#endif /* CONFIG_WIFI_CLOCKSYNC */
+
+#if CONFIG_WIFI_EU_CRYPTO
+int wlan_set_crypto_RC4_encrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength)
+{
+    t_u16 rc4_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 rc4_keyiv_length = EU_CRYPTO_KEYIV_MAX_LENGTH;
+    t_u16 rc4_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > rc4_key_length)
+        return -WM_FAIL;
+    if (KeyIVLength > rc4_keyiv_length)
+        return -WM_FAIL;
+    if (*DataLength > rc4_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_RC4_Param;
+    Crypto_RC4_Param.KeyIVLength = KeyIVLength;
+    memcpy(Crypto_RC4_Param.KeyIV, KeyIV, KeyIVLength);
+    Crypto_RC4_Param.KeyLength = KeyLength;
+    memcpy(Crypto_RC4_Param.Key, Key, KeyLength);
+    Crypto_RC4_Param.DataLength = DataLength;
+    Crypto_RC4_Param.Data       = Data;
+
+    t_u16 EncDec = 1;
+
+    return wifi_set_eu_crypto(&Crypto_RC4_Param, CRYPTO_RC4, EncDec);
+}
+
+int wlan_set_crypto_RC4_decrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength)
+{
+    t_u16 rc4_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 rc4_keyiv_length = EU_CRYPTO_KEYIV_MAX_LENGTH;
+    t_u16 rc4_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > rc4_key_length)
+        return -WM_FAIL;
+    if (KeyIVLength > rc4_keyiv_length)
+        return -WM_FAIL;
+    if (*DataLength > rc4_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_RC4_Param;
+    Crypto_RC4_Param.KeyIVLength = KeyIVLength;
+    memcpy(Crypto_RC4_Param.KeyIV, KeyIV, KeyIVLength);
+    Crypto_RC4_Param.KeyLength = KeyLength;
+    memcpy(Crypto_RC4_Param.Key, Key, KeyLength);
+    Crypto_RC4_Param.DataLength = DataLength;
+    Crypto_RC4_Param.Data       = Data;
+
+    t_u16 EncDec = 0;
+
+    return wifi_set_eu_crypto(&Crypto_RC4_Param, CRYPTO_RC4, EncDec);
+}
+
+int wlan_set_crypto_AES_ECB_encrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength)
+{
+    t_u16 aes_ecb_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_ecb_keyiv_length = EU_CRYPTO_KEYIV_MAX_LENGTH;
+    t_u16 aes_ecb_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_ecb_key_length)
+        return -WM_FAIL;
+    if (KeyIVLength > aes_ecb_keyiv_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_ecb_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_AES_ECB_Param;
+    Crypto_AES_ECB_Param.KeyIVLength = KeyIVLength;
+    memcpy(Crypto_AES_ECB_Param.KeyIV, KeyIV, KeyIVLength);
+    Crypto_AES_ECB_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_ECB_Param.Key, Key, KeyLength);
+    Crypto_AES_ECB_Param.DataLength = DataLength;
+    Crypto_AES_ECB_Param.Data       = Data;
+
+    t_u16 EncDec = 1;
+
+    return wifi_set_eu_crypto(&Crypto_AES_ECB_Param, CRYPTO_AES_ECB, EncDec);
+}
+
+int wlan_set_crypto_AES_ECB_decrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength)
+{
+    t_u16 aes_ecb_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_ecb_keyiv_length = EU_CRYPTO_KEYIV_MAX_LENGTH;
+    t_u16 aes_ecb_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_ecb_key_length)
+        return -WM_FAIL;
+    if (KeyIVLength > aes_ecb_keyiv_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_ecb_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_AES_ECB_Param;
+    Crypto_AES_ECB_Param.KeyIVLength = KeyIVLength;
+    memcpy(Crypto_AES_ECB_Param.KeyIV, KeyIV, KeyIVLength);
+    Crypto_AES_ECB_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_ECB_Param.Key, Key, KeyLength);
+    Crypto_AES_ECB_Param.DataLength = DataLength;
+    Crypto_AES_ECB_Param.Data       = Data;
+
+    t_u16 EncDec = 0;
+
+    return wifi_set_eu_crypto(&Crypto_AES_ECB_Param, CRYPTO_AES_ECB, EncDec);
+}
+
+int wlan_set_crypto_AES_WRAP_encrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength)
+{
+    t_u16 aes_wrap_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_wrap_keyiv_length = EU_CRYPTO_KEYIV_MAX_LENGTH;
+    t_u16 aes_wrap_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_wrap_key_length)
+        return -WM_FAIL;
+    if (KeyIVLength > aes_wrap_keyiv_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_wrap_data_length)
+        return -WM_FAIL;
+
+    EU_Crypto Crypto_AES_WRAP_Param;
+    Crypto_AES_WRAP_Param.KeyIVLength = KeyIVLength;
+    memcpy(Crypto_AES_WRAP_Param.KeyIV, KeyIV, KeyIVLength);
+    Crypto_AES_WRAP_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_WRAP_Param.Key, Key, KeyLength);
+    Crypto_AES_WRAP_Param.DataLength = DataLength;
+    Crypto_AES_WRAP_Param.Data       = Data;
+
+    t_u16 EncDec = 1;
+
+    return wifi_set_eu_crypto(&Crypto_AES_WRAP_Param, CRYPTO_AES_WRAP, EncDec);
+}
+
+int wlan_set_crypto_AES_WRAP_decrypt(
+    const t_u8 *Key, const t_u16 KeyLength, const t_u8 *KeyIV, const t_u16 KeyIVLength, t_u8 *Data, t_u16 *DataLength)
+{
+    t_u16 aes_wrap_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_wrap_keyiv_length = EU_CRYPTO_KEYIV_MAX_LENGTH;
+    t_u16 aes_wrap_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_wrap_key_length)
+        return -WM_FAIL;
+    if (KeyIVLength > aes_wrap_keyiv_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_wrap_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_AES_WRAP_Param;
+    Crypto_AES_WRAP_Param.KeyIVLength = KeyIVLength;
+    memcpy(Crypto_AES_WRAP_Param.KeyIV, KeyIV, KeyIVLength);
+    Crypto_AES_WRAP_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_WRAP_Param.Key, Key, KeyLength);
+    Crypto_AES_WRAP_Param.DataLength = DataLength;
+    Crypto_AES_WRAP_Param.Data       = Data;
+
+    t_u16 EncDec = 0;
+
+    return wifi_set_eu_crypto(&Crypto_AES_WRAP_Param, CRYPTO_AES_WRAP, EncDec);
+}
+
+int wlan_set_crypto_AES_CCMP_encrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength)
+{
+    t_u16 aes_ccmp_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_ccmp_AAD_length   = EU_CRYPTO_AAD_MAX_LENGTH;
+    t_u16 aes_ccmp_Nonce_length = EU_CRYPTO_NONCE_MAX_LENGTH;
+    t_u16 aes_ccmp_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+#if defined(SD8978)
+    if (KeyLength == aes_ccmp_key_length)
+    {
+        return -WM_E_PERM;
+    }
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_ccmp_key_length)
+        return -WM_FAIL;
+    if (AADLength > aes_ccmp_AAD_length)
+        return -WM_FAIL;
+    if (NonceLength > aes_ccmp_Nonce_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_ccmp_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_AES_CCMP_Param;
+    Crypto_AES_CCMP_Param.AADLength = AADLength;
+    memcpy(Crypto_AES_CCMP_Param.AAD, AAD, AADLength);
+    Crypto_AES_CCMP_Param.NonceLength = NonceLength;
+    memcpy(Crypto_AES_CCMP_Param.Nonce, Nonce, NonceLength);
+    Crypto_AES_CCMP_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_CCMP_Param.Key, Key, KeyLength);
+    Crypto_AES_CCMP_Param.DataLength = DataLength;
+    Crypto_AES_CCMP_Param.Data       = Data;
+
+    t_u16 EncDec = 1;
+
+    return wifi_set_eu_crypto(&Crypto_AES_CCMP_Param, CRYPTO_AES_CCMP, EncDec);
+}
+
+int wlan_set_crypto_AES_CCMP_decrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength)
+{
+    t_u16 aes_ccmp_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_ccmp_AAD_length   = EU_CRYPTO_AAD_MAX_LENGTH;
+    t_u16 aes_ccmp_Nonce_length = EU_CRYPTO_NONCE_MAX_LENGTH;
+    t_u16 aes_ccmp_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+#if defined(SD8801)
+    return -WM_E_PERM;
+#endif
+
+#if defined(SD8978)
+    if (KeyLength == aes_ccmp_key_length)
+    {
+        return -WM_E_PERM;
+    }
+#endif
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_ccmp_key_length)
+        return -WM_FAIL;
+    if (AADLength > aes_ccmp_AAD_length)
+        return -WM_FAIL;
+    if (NonceLength > aes_ccmp_Nonce_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_ccmp_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_AES_CCMP_Param;
+    Crypto_AES_CCMP_Param.AADLength = AADLength;
+    memcpy(Crypto_AES_CCMP_Param.AAD, AAD, AADLength);
+    Crypto_AES_CCMP_Param.NonceLength = NonceLength;
+    memcpy(Crypto_AES_CCMP_Param.Nonce, Nonce, NonceLength);
+    Crypto_AES_CCMP_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_CCMP_Param.Key, Key, KeyLength);
+    Crypto_AES_CCMP_Param.DataLength = DataLength;
+    Crypto_AES_CCMP_Param.Data       = Data;
+
+    t_u16 EncDec = 0;
+
+    return wifi_set_eu_crypto(&Crypto_AES_CCMP_Param, CRYPTO_AES_CCMP, EncDec);
+}
+
+int wlan_set_crypto_AES_GCMP_encrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength)
+{
+#if defined(SD8801) || defined(SD8978)
+    return -WM_E_PERM;
+#else
+    t_u16 aes_gcmp_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_gcmp_AAD_length   = EU_CRYPTO_AAD_MAX_LENGTH;
+    t_u16 aes_gcmp_Nonce_length = EU_CRYPTO_NONCE_MAX_LENGTH;
+    t_u16 aes_gcmp_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_gcmp_key_length)
+        return -WM_FAIL;
+    if (AADLength > aes_gcmp_AAD_length)
+        return -WM_FAIL;
+    if (NonceLength > aes_gcmp_Nonce_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_gcmp_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_AES_GCMP_Param;
+    Crypto_AES_GCMP_Param.AADLength = AADLength;
+    memcpy(Crypto_AES_GCMP_Param.AAD, AAD, AADLength);
+    Crypto_AES_GCMP_Param.NonceLength = NonceLength;
+    memcpy(Crypto_AES_GCMP_Param.Nonce, Nonce, NonceLength);
+    Crypto_AES_GCMP_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_GCMP_Param.Key, Key, KeyLength);
+    Crypto_AES_GCMP_Param.DataLength = DataLength;
+    Crypto_AES_GCMP_Param.Data       = Data;
+
+    t_u16 EncDec = 1;
+
+    return wifi_set_eu_crypto(&Crypto_AES_GCMP_Param, CRYPTO_AES_GCMP, EncDec);
+#endif
+}
+
+int wlan_set_crypto_AES_GCMP_decrypt(const t_u8 *Key,
+                                     const t_u16 KeyLength,
+                                     const t_u8 *AAD,
+                                     const t_u16 AADLength,
+                                     const t_u8 *Nonce,
+                                     const t_u16 NonceLength,
+                                     t_u8 *Data,
+                                     t_u16 *DataLength)
+{
+#if defined(SD8801) || defined(SD8978)
+    return -WM_E_PERM;
+#else
+    t_u16 aes_gcmp_key_length   = EU_CRYPTO_KEY_MAX_LENGTH;
+    t_u16 aes_gcmp_AAD_length   = EU_CRYPTO_AAD_MAX_LENGTH;
+    t_u16 aes_gcmp_Nonce_length = EU_CRYPTO_NONCE_MAX_LENGTH;
+    t_u16 aes_gcmp_data_length  = EU_CRYPTO_DATA_MAX_LENGTH;
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("Must enable Wi-Fi firstly\r\n");
+        return -WM_FAIL;
+    }
+
+    if (KeyLength > aes_gcmp_key_length)
+        return -WM_FAIL;
+    if (AADLength > aes_gcmp_AAD_length)
+        return -WM_FAIL;
+    if (NonceLength > aes_gcmp_Nonce_length)
+        return -WM_FAIL;
+    if (*DataLength > aes_gcmp_data_length)
+        return -WM_FAIL;
+    EU_Crypto Crypto_AES_GCMP_Param;
+    Crypto_AES_GCMP_Param.AADLength = AADLength;
+    memcpy(Crypto_AES_GCMP_Param.AAD, AAD, AADLength);
+    Crypto_AES_GCMP_Param.NonceLength = NonceLength;
+    memcpy(Crypto_AES_GCMP_Param.Nonce, Nonce, NonceLength);
+    Crypto_AES_GCMP_Param.KeyLength = KeyLength;
+    memcpy(Crypto_AES_GCMP_Param.Key, Key, KeyLength);
+    Crypto_AES_GCMP_Param.DataLength = DataLength;
+    Crypto_AES_GCMP_Param.Data       = Data;
+
+    t_u16 EncDec = 0;
+
+    return wifi_set_eu_crypto(&Crypto_AES_GCMP_Param, CRYPTO_AES_GCMP, EncDec);
+#endif
+}
+#endif /* CONFIG_WIFI_EU_CRYPTO */
+
+#if CONFIG_HEAP_DEBUG
+void wlan_show_os_mem_stat()
+{
+    wifi_show_os_mem_stat();
+}
+#endif
+
+#if CONFIG_MULTI_CHAN
+int wlan_set_multi_chan_status(const int status)
+{
+    return wifi_set_mc_policy(status);
+}
+
+int wlan_get_multi_chan_status(int *status)
+{
+    (*status) = wifi_get_mc_policy();
+    return WM_SUCCESS;
+}
+
+int wlan_set_drcs_cfg(const wlan_drcs_cfg_t *drcs_cfg, const int num)
+{
+    return wifi_set_mc_cfg_ext((wifi_drcs_cfg_t *)drcs_cfg, num);
+}
+
+int wlan_get_drcs_cfg(wlan_drcs_cfg_t *drcs_cfg, int num)
+{
+    return wifi_get_mc_cfg_ext((wifi_drcs_cfg_t *)drcs_cfg, num);
+}
+#endif
+
+#if CONFIG_WPS2
+void wlan_set_prov_session(int session)
+{
+    prov_session_attempt = session;
+    wps_conf.prov_session = session;
+}
+
+int wlan_get_prov_session(void)
+{
+    return prov_session_attempt;
+}
+#endif
+
+
+#if CONFIG_ECSA
+
+int wlan_uap_set_ecsa_cfg(t_u8 block_tx, t_u8 oper_class, t_u8 channel, t_u8 switch_count, t_u8 band_width)
+{
+    t_u8 ecsa = MFALSE;
+    int ret   = 0;
+
+    ret = wlan_set_uap_ecsa_cfg(block_tx, oper_class, channel, switch_count, band_width, ecsa);
+
+    return ret;
+}
+
+#endif
+#if CONFIG_11AX
+#if CONFIG_MMSF
+int wlan_set_mmsf(const t_u8 enable, const t_u8 Density, const t_u8 MMSF)
+{
+    return wifi_mmsf_cfg(ACTION_SET, (t_u8 *)&enable, (t_u8 *)&Density, (t_u8 *)&MMSF);
+}
+
+int wlan_get_mmsf(t_u8 *enable, t_u8 *Density, t_u8 *MMSF)
+{
+    return wifi_mmsf_cfg(ACTION_GET, enable, Density, MMSF);
+}
+#endif
+#endif
+
+#if CONFIG_WIFI_RECOVERY
+int wlan_recovery_test(void)
+{
+    return wifi_recovery_test();
+}
+#endif
+
+#if CONFIG_SUBSCRIBE_EVENT_SUPPORT
+/**
+ *  @brief This function subscribe event to firmware.
+ *
+ *  @param sbitmap    A pointer to specific event from user.
+ *  @param thresh_value     A pointer to value from user.
+ *  @param freq      A pointer to freq from user.
+ *
+ *  @return             MLAN_STATUS_SUCCESS, MLAN_STATUS_FAILURE or WM_E_INVAL
+ */
+int wlan_set_subscribe_event(unsigned int event_id, unsigned int thresh_value, unsigned int freq)
+{
+    int ret = WM_E_INVAL;
+    switch (event_id)
+    {
+        case EVENT_SUB_RSSI_LOW:
+            ret = wifi_set_threshold_rssi_low(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_RSSI_HIGH:
+            ret = wifi_set_threshold_rssi_high(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_SNR_LOW:
+            ret = wifi_set_threshold_snr_low(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_SNR_HIGH:
+            ret = wifi_set_threshold_snr_high(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_MAX_FAIL:
+            ret = wifi_set_threshold_max_fail(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_BEACON_MISSED:
+            ret = wifi_set_threshold_beacon_miss(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_DATA_RSSI_LOW:
+            ret = wifi_set_threshold_data_rssi_low(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_DATA_RSSI_HIGH:
+            ret = wifi_set_threshold_data_rssi_high(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_DATA_SNR_LOW:
+            ret = wifi_set_threshold_data_snr_low(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_DATA_SNR_HIGH:
+            ret = wifi_set_threshold_data_snr_high(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        case EVENT_SUB_PRE_BEACON_LOST:
+            ret = wifi_set_threshold_pre_beacon_lost(mlan_adap->priv[0], thresh_value, freq);
+            break;
+        default:
+            ret = WM_E_INVAL;
+            break;
+    }
+    return ret;
+}
+
+int wlan_get_subscribe_event(wlan_ds_subscribe_evt *sub_evt)
+{
+    int ret = WM_E_INVAL;
+    mlan_ds_subscribe_evt msub_evt;
+    memset(&msub_evt, 0, sizeof(msub_evt));
+    ret = wifi_get_subscribe_event(mlan_adap->priv[0], &msub_evt);
+    memcpy((t_u8 *)sub_evt, (t_u8 *)&msub_evt.evt_bitmap, sizeof(wlan_ds_subscribe_evt));
+    return ret;
+}
+
+int wlan_clear_subscribe_event(unsigned int event_id)
+{
+    /*bitmap parameter analyse*/
+    int evt_bitmap = 0;
+    switch (event_id)
+    {
+        case EVENT_SUB_RSSI_LOW:
+            evt_bitmap = SUBSCRIBE_EVT_RSSI_LOW;
+            break;
+        case EVENT_SUB_RSSI_HIGH:
+            evt_bitmap = SUBSCRIBE_EVT_RSSI_HIGH;
+            break;
+        case EVENT_SUB_SNR_LOW:
+            evt_bitmap = SUBSCRIBE_EVT_SNR_LOW;
+            break;
+        case EVENT_SUB_SNR_HIGH:
+            evt_bitmap = SUBSCRIBE_EVT_SNR_HIGH;
+            break;
+        case EVENT_SUB_MAX_FAIL:
+            evt_bitmap = SUBSCRIBE_EVT_MAX_FAIL;
+            break;
+        case EVENT_SUB_BEACON_MISSED:
+            evt_bitmap = SUBSCRIBE_EVT_BEACON_MISSED;
+            break;
+        case EVENT_SUB_DATA_RSSI_LOW:
+            evt_bitmap = SUBSCRIBE_EVT_DATA_RSSI_LOW;
+            break;
+        case EVENT_SUB_DATA_RSSI_HIGH:
+            evt_bitmap = SUBSCRIBE_EVT_DATA_RSSI_HIGH;
+            break;
+        case EVENT_SUB_DATA_SNR_LOW:
+            evt_bitmap = SUBSCRIBE_EVT_DATA_SNR_LOW;
+            break;
+        case EVENT_SUB_DATA_SNR_HIGH:
+            evt_bitmap = SUBSCRIBE_EVT_DATA_SNR_HIGH;
+            break;
+        case EVENT_SUB_LINK_QUALITY:
+            evt_bitmap = SUBSCRIBE_EVT_LINK_QUALITY;
+            break;
+        case EVENT_SUB_PRE_BEACON_LOST:
+            evt_bitmap = SUBSCRIBE_EVT_PRE_BEACON_LOST;
+            break;
+        default:
+            return WM_E_INVAL;
+            break;
+    }
+    return wifi_clear_subscribe_event(mlan_adap->priv[0], evt_bitmap);
+}
+
+int wlan_set_threshold_link_quality(unsigned int event_id,
+                                    unsigned int link_snr,
+                                    unsigned int link_snr_freq,
+                                    unsigned int link_rate,
+                                    unsigned int link_rate_freq,
+                                    unsigned int link_tx_latency,
+                                    unsigned int link_tx_lantency_freq)
+{
+    if (event_id == EVENT_SUB_LINK_QUALITY)
+        return wifi_set_threshold_link_quality(mlan_adap->priv[0], link_snr, link_snr_freq, link_rate, link_rate_freq,
+                                               link_tx_latency, link_tx_lantency_freq);
+    return WM_E_INVAL;
+}
+#endif
+
+#if CONFIG_WIFI_REG_ACCESS
+int wlan_reg_access(wifi_reg_t type, uint16_t action, uint32_t offset, uint32_t *value)
+{
+    return wifi_reg_access(type, action, offset, value);
+}
+#endif
+
+#if CONFIG_WMM_UAPSD
+static t_u8 uapsd_qos_info             = WMM_UAPSD_QOS_INFO;
+static unsigned int uapsd_sleep_period = WMM_UAPSD_SLEEP_PERIOD;
+int wlan_wmm_uapsd_qosinfo(t_u8 *qos_info, t_u8 action)
+{
+    int ret = WM_SUCCESS;
+
+    ret = wifi_wmm_qos_cfg(qos_info, action);
+    if (ret == WM_SUCCESS && action == ACTION_SET)
+        uapsd_qos_info = *qos_info;
+
+    return ret;
+}
+
+int wlan_set_wmm_uapsd(t_u8 uapsd_enable)
+{
+#if !CONFIG_WNM_PS
+    unsigned int condition = 0;
+#endif
+
+    if (!is_uap_state(CM_UAP_INITIALIZING) || is_sta_connecting())
+    {
+        (void)PRINTF("Failed to enable/disable UAPSD, because uAP is up/STA is connecting\n");
+        return -WM_FAIL;
+    }
+
+    if (uapsd_enable)
+    {
+        (void)wifi_wmm_qos_cfg(&uapsd_qos_info, 1);
+        (void)wifi_sleep_period(&uapsd_sleep_period, 1);
+#if !CONFIG_WNM_PS
+        (void)wlan_ieeeps_on(condition);
+#endif
+    }
+    else
+    {
+        t_u8 qos_info       = 0;
+        unsigned int period = 0;
+        (void)wifi_wmm_qos_cfg(&qos_info, 1);
+        (void)wifi_sleep_period(&period, 1);
+        (void)wlan_ieeeps_off();
+    }
+	return WM_SUCCESS;
+}
+int wlan_sleep_period(unsigned int *sleep_period, t_u8 action)
+{
+    int ret = WM_SUCCESS;
+
+    ret = wifi_sleep_period(sleep_period, action);
+    if (ret == WM_SUCCESS && action == ACTION_SET)
+        uapsd_sleep_period = *sleep_period;
+
+    return ret;
+}
+
+t_u8 wlan_is_wmm_uapsd_enabled(void)
+{
+    return (mlan_adap ? mlan_adap->pps_uapsd_mode : false);
+}
+#endif
+
+#if CONFIG_TX_AMPDU_PROT_MODE
+int wlan_tx_ampdu_prot_mode(tx_ampdu_prot_mode_para *prot_mode, t_u16 action)
+{
+    return wifi_tx_ampdu_prot_mode(prot_mode, action);
+}
+#endif
+
+int wlan_mef_set_auto_arp(t_u8 mef_action)
+{
+    int ret, index;
+    unsigned int ipv4_addr[2];
+    int ipv4_addr_num = 0;
+    int filter_num = 0;
+
+    if(!is_sta_ipv4_connected() && !is_uap_started())
+    {
+        wlcm_e("No connection on STA and uAP is not activated.");
+        wlcm_e("Should at least meet one condition.");
+        return -WM_E_PERM;
+    }
+
+    if (g_flt_cfg.nentries >= MAX_NUM_ENTRIES)
+    {
+        wlcm_e("Number of MEF entries(%d) exceeds limit(8)!", g_flt_cfg.nentries);
+        return -WM_FAIL;
+    }
+
+    (void)memset(ipv4_addr, 0x0, sizeof(ipv4_addr));
+    if(is_sta_ipv4_connected() != 0)
+    {
+        ret = wlan_get_ipv4_addr(&ipv4_addr[0]);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("Cannot get STA IP");
+            return -WM_FAIL;
+        }
+        ipv4_addr_num++;
+    }
+    if(is_uap_started() != 0)
+    {
+        ret = wlan_get_uap_ipv4_addr(&ipv4_addr[1]);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("Cannot get UAP IP");
+            return -WM_FAIL;
+        }
+        ipv4_addr_num++;
+    }
+    index = g_flt_cfg.nentries;
+    g_flt_cfg.criteria |= (CRITERIA_BROADCAST | CRITERIA_UNICAST);
+    g_flt_cfg.nentries++;
+
+    g_flt_cfg.mef_entry[index].mode                        = MEF_MODE_HOST_SLEEP;
+    g_flt_cfg.mef_entry[index].action                      = (MEF_AUTO_ARP | (mef_action & 0xF));
+    g_flt_cfg.mef_entry[index].filter_num                  = 1;
+    g_flt_cfg.mef_entry[index].filter_item[0].type         = TYPE_BYTE_EQ;
+    g_flt_cfg.mef_entry[index].filter_item[0].repeat       = 1;
+    g_flt_cfg.mef_entry[index].filter_item[0].offset       = IPV4_PKT_OFFSET;
+    g_flt_cfg.mef_entry[index].filter_item[0].num_byte_seq = 2;
+    (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[0].byte_seq, "\x08\x06", 2);
+    g_flt_cfg.mef_entry[index].rpn[1] = RPN_TYPE_AND;
+
+    if(is_sta_ipv4_connected() != 0)
+    {
+        g_flt_cfg.mef_entry[index].filter_num++;
+        filter_num = g_flt_cfg.mef_entry[index].filter_num;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].type         = TYPE_BYTE_EQ;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].repeat       = 1;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].offset       = 46;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].num_byte_seq = 4;
+        (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].byte_seq,
+                     &ipv4_addr[0], 4); // STA IP address
+    }
+
+    if(is_uap_started() != 0)
+    {
+        g_flt_cfg.mef_entry[index].filter_num++;
+        filter_num = g_flt_cfg.mef_entry[index].filter_num;
+        if(ipv4_addr_num == 2)
+            g_flt_cfg.mef_entry[index].rpn[filter_num] = RPN_TYPE_OR;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].type         = TYPE_BYTE_EQ;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].repeat       = 1;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].offset       = 46;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].num_byte_seq = 4;
+        (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].byte_seq,
+                     &ipv4_addr[1], 4); // UAP IP address
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_mef_set_auto_ping(t_u8 mef_action)
+{
+    int ret, index;
+    unsigned int ipv4_addr[2];
+    int ipv4_addr_num = 0;
+    int filter_num = 0;
+
+    if(!is_sta_ipv4_connected() && !is_uap_started())
+    {
+        wlcm_e("No connection on STA and uAP is not activated.");
+        wlcm_e("Should at least meet one condition.");
+        return -WM_E_PERM;
+    }
+
+    if (g_flt_cfg.nentries >= MAX_NUM_ENTRIES)
+    {
+        wlcm_e("Number of MEF entries(%d) exceeds limit(8)!", g_flt_cfg.nentries);
+        return -WM_FAIL;
+    }
+
+    (void)memset(ipv4_addr, 0x0, sizeof(ipv4_addr));
+    if(is_sta_ipv4_connected() != 0)
+    {
+        ret = wlan_get_ipv4_addr(&ipv4_addr[0]);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("Cannot get STA IP");
+            return -WM_FAIL;
+        }
+        ipv4_addr_num++;
+    }
+    if(is_uap_started() != 0)
+    {
+        ret = wlan_get_uap_ipv4_addr(&ipv4_addr[1]);
+        if (ret != WM_SUCCESS)
+        {
+            wlcm_e("Cannot get UAP IP");
+            return -WM_FAIL;
+        }
+        ipv4_addr_num++;
+    }
+    index = g_flt_cfg.nentries;
+    g_flt_cfg.criteria |= (CRITERIA_BROADCAST | CRITERIA_UNICAST);
+    g_flt_cfg.nentries++;
+    g_flt_cfg.mef_entry[index].mode                        = MEF_MODE_HOST_SLEEP;
+    g_flt_cfg.mef_entry[index].action                      = (MEF_AUTO_PING | (mef_action & 0xF));
+    g_flt_cfg.mef_entry[index].filter_num                  = 2;
+    g_flt_cfg.mef_entry[index].filter_item[0].type         = TYPE_BYTE_EQ;
+    g_flt_cfg.mef_entry[index].filter_item[0].repeat       = 1;
+    g_flt_cfg.mef_entry[index].filter_item[0].offset       = IPV4_PKT_OFFSET;
+    g_flt_cfg.mef_entry[index].filter_item[0].num_byte_seq = 2;
+    (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[0].byte_seq, "\x08\x00", 2);
+    g_flt_cfg.mef_entry[index].rpn[1] = RPN_TYPE_AND;
+
+    g_flt_cfg.mef_entry[index].filter_item[1].type      = TYPE_DNUM_EQ;
+    g_flt_cfg.mef_entry[index].filter_item[1].pattern   = ICMP_OF_IP_PROTOCOL;
+    g_flt_cfg.mef_entry[index].filter_item[1].offset    = IP_PROTOCOL_OFFSET;
+    g_flt_cfg.mef_entry[index].filter_item[1].num_bytes = 1;
+    g_flt_cfg.mef_entry[index].rpn[2]                   = RPN_TYPE_AND;
+
+    if(is_sta_ipv4_connected() != 0)
+    {
+        g_flt_cfg.mef_entry[index].filter_num++;
+        filter_num = g_flt_cfg.mef_entry[index].filter_num;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].type         = TYPE_BYTE_EQ;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].repeat       = 1;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].offset       = 38;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].num_byte_seq = 4;
+        (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].byte_seq,
+                     &ipv4_addr[0], 4); //STA IP address
+    }
+
+    if(is_uap_started() != 0)
+    {
+        g_flt_cfg.mef_entry[index].filter_num++;
+        filter_num = g_flt_cfg.mef_entry[index].filter_num;
+        if(ipv4_addr_num == 2)
+            g_flt_cfg.mef_entry[index].rpn[filter_num - 1] = RPN_TYPE_OR;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].type         = TYPE_BYTE_EQ;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].repeat       = 1;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].offset       = 38;
+        g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].num_byte_seq = 4;
+        (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[filter_num - 1].byte_seq,
+                     &ipv4_addr[1], 4); // UAP IP address
+    }
+
+    return WM_SUCCESS;
+}
+
+int wlan_set_ipv6_ns_mef(t_u8 mef_action)
+{
+	int index;
+
+    if (g_flt_cfg.nentries >= MAX_NUM_ENTRIES)
+    {
+        wlcm_e("Number of MEF entries(%d) exceeds limit(8)!", g_flt_cfg.nentries);
+        return -WM_FAIL;
+    }
+
+    index = g_flt_cfg.nentries;
+    g_flt_cfg.criteria |= (CRITERIA_UNICAST | CRITERIA_MULTICAST);
+    g_flt_cfg.nentries++;
+    g_flt_cfg.mef_entry[index].mode = MEF_MODE_HOST_SLEEP;
+    g_flt_cfg.mef_entry[index].action = (MEF_NS_RESP| (mef_action & 0xF));
+    g_flt_cfg.mef_entry[index].filter_num = 2;
+
+	g_flt_cfg.mef_entry[index].filter_item[0].fill_flag = (FILLING_TYPE | FILLING_REPEAT | FILLING_OFFSET | FILLING_BYTE_SEQ);
+    g_flt_cfg.mef_entry[index].filter_item[0].type         = TYPE_BYTE_EQ;
+    g_flt_cfg.mef_entry[index].filter_item[0].repeat       = 1;
+    g_flt_cfg.mef_entry[index].filter_item[0].offset       = IPV4_PKT_OFFSET;
+    g_flt_cfg.mef_entry[index].filter_item[0].num_byte_seq = 2;
+    (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[0].byte_seq, "\x86\xdd", 2);
+    g_flt_cfg.mef_entry[index].rpn[1] = RPN_TYPE_AND;
+
+	g_flt_cfg.mef_entry[index].filter_item[1].fill_flag = (FILLING_TYPE | FILLING_REPEAT | FILLING_OFFSET | FILLING_BYTE_SEQ);
+    g_flt_cfg.mef_entry[index].filter_item[1].type         = TYPE_BYTE_EQ;
+    g_flt_cfg.mef_entry[index].filter_item[1].repeat       = 1;
+    g_flt_cfg.mef_entry[index].filter_item[1].offset       = 62;
+    g_flt_cfg.mef_entry[index].filter_item[1].num_byte_seq = 1;
+    (void)memcpy(g_flt_cfg.mef_entry[index].filter_item[1].byte_seq, "\x87", 1);
+
+    return WM_SUCCESS;
+}
+
+int wlan_mef_set_multicast(t_u8 mef_action)
+{
+    t_u32 index = 0;
+
+    if (g_flt_cfg.nentries >= MAX_NUM_ENTRIES)
+    {
+        wlcm_e("Number of MEF entries(%d) exceeds limit(8)!", g_flt_cfg.nentries);
+        return -WM_FAIL;
+    }
+    index = g_flt_cfg.nentries;
+    g_flt_cfg.criteria |= (CRITERIA_MULTICAST | CRITERIA_UNICAST);
+    g_flt_cfg.nentries++;
+
+    g_flt_cfg.mef_entry[index].mode                        = MEF_MODE_HOST_SLEEP;
+    g_flt_cfg.mef_entry[index].action                      = mef_action;
+    g_flt_cfg.mef_entry[index].filter_num                  = 2;
+    g_flt_cfg.mef_entry[index].filter_item[0].type         = TYPE_BIT_EQ;
+    g_flt_cfg.mef_entry[index].filter_item[0].offset       = 0;
+    g_flt_cfg.mef_entry[index].filter_item[0].num_byte_seq = 1;
+    g_flt_cfg.mef_entry[index].filter_item[0].byte_seq[0]  = 0x01;
+    g_flt_cfg.mef_entry[index].filter_item[0].num_mask_seq = 1;
+    g_flt_cfg.mef_entry[index].filter_item[0].mask_seq[0]  = 0x01;
+    g_flt_cfg.mef_entry[index].rpn[1]                      = RPN_TYPE_OR;
+
+    g_flt_cfg.mef_entry[index].filter_item[1].type         = TYPE_BIT_EQ;
+    g_flt_cfg.mef_entry[index].filter_item[1].offset       = 38;
+    g_flt_cfg.mef_entry[index].filter_item[1].num_byte_seq = 1;
+    g_flt_cfg.mef_entry[index].filter_item[1].byte_seq[0]  = 0xE0;
+    g_flt_cfg.mef_entry[index].filter_item[1].num_mask_seq = 1;
+    g_flt_cfg.mef_entry[index].filter_item[1].mask_seq[0]  = 0xF0;
+
+    return WM_SUCCESS;
+}
+
+int wlan_config_mef(int type, t_u8 mef_action)
+{
+    int ret = -WM_FAIL;
+
+    if (!wlan_is_started())
+    {
+        (void)PRINTF("MEF configure is not allowed when WIFI is disabled\r\n");
+        return -WM_FAIL;
+    }
+
+    switch (type)
+    {
+        case MEF_TYPE_DELETE:
+            (void)memset(&g_flt_cfg, 0, sizeof(wlan_flt_cfg_t));
+            ret = wifi_set_packet_filters(&g_flt_cfg);
+            if(ret == WM_SUCCESS)
+                (void)PRINTF("delete all MEF entries Successful\n\r");
+            else
+                (void)PRINTF("delete all MEF entries Failed\n\r");
+            break;
+        case MEF_TYPE_PING:
+            ret = wlan_mef_set_auto_ping(mef_action);
+            if (ret == WM_SUCCESS)
+                (void)PRINTF("Add ping MEF entry successful\n\r");
+            else
+                (void)PRINTF("Add ping MEF entry Failed\n\r");
+            break;
+        case MEF_TYPE_ARP:
+            ret = wlan_mef_set_auto_arp(mef_action);
+            if (ret == WM_SUCCESS)
+            {
+                (void)PRINTF("Add ARP MEF entry successful\n\r");
+            }
+            else
+                (void)PRINTF("Add ARP MEF entry Failed\n\r");
+            break;
+        case MEF_TYPE_MULTICAST:
+            ret = wlan_mef_set_multicast(mef_action);
+            if (ret == WM_SUCCESS)
+                (void)PRINTF("Add multicast MEF entry successful\n\r");
+            else
+                (void)PRINTF("Add multicast MEF entry Failed\n\r");
+            break;
+        case MEF_TYPE_IPV6_NS:
+            ret = wlan_set_ipv6_ns_mef(mef_action);
+            if (ret == WM_SUCCESS)
+                (void)PRINTF("Add ns MEF entry successful\n\r");
+            else
+                (void)PRINTF("Add ns MEF entry Failed\n\r");
+            break;
+        default:
+            (void)PRINTF("Error: unknown MEF type:%d", type);
+            break;
+    }
+
+    return ret;
+}
+
+#if CONFIG_CSI
+wlan_csi_config_params_t * wlan_get_csi_cfg_param_default(void)
+{
+    return &g_csi_params_default;
+}
+
+int wlan_set_csi_cfg_param_default(wlan_csi_config_params_t *in_csi_cfg)
+{
+    if (in_csi_cfg)
+    {
+        memcpy((void *)&g_csi_params_default, (void *)in_csi_cfg, sizeof(wlan_csi_config_params_t));
+        return MTRUE;
+    }
+    else
+        return MFALSE;
+}
+
+void wlan_reset_csi_filter_data(void)
+{
+    (void)memset((void*)&g_csi_params_default, 0, sizeof(wlan_csi_config_params_t));
+}
+
+int wlan_register_csi_user_callback(int (*csi_data_recv_callback)(void *buffer, size_t len))
+{
+    return register_csi_user_callback(csi_data_recv_callback);
+}
+
+int wlan_unregister_csi_user_callback(void)
+{
+    return unregister_csi_user_callback();
+}
+
+int wlan_csi_cfg(wlan_csi_config_params_t *csi_params)
+{
+    int ret = WM_SUCCESS;
+
+    if (csi_params->csi_enable == 1)
+    {
+        csi_local_buff_init();
+    }
+    else
+    {
+        ret = unregister_csi_user_callback();
+    }
+
+    ret = wifi_csi_cfg(csi_params);
+
+    return ret;
+}
+#endif
+
+#if (CONFIG_11K) || (CONFIG_11V) || (CONFIG_11R) || (CONFIG_ROAMING)
+void wlan_set_rssi_low_threshold(uint8_t threshold)
+{
+    wlan.rssi_low_threshold = threshold;
+
+    if (is_sta_connected())
+    {
+#if CONFIG_ROAMING
+        if (wlan.roaming_enabled == true)
+        {
+            (void)wifi_config_roaming(true, &wlan.rssi_low_threshold);
+        }
+        else
+#endif
+        {
+            (void)wifi_set_rssi_low_threshold(&wlan.rssi_low_threshold);
+        }
+    }
+}
+#endif
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_WPS
+static int wlan_remove_wps_network(void)
+{
+    unsigned int len, i;
+    int ret = -WM_E_INVAL;
+    struct netif *netif = net_get_sta_interface();
+
+    ret = wpa_supp_cancel_scan(netif);
+    /* find the first network whose name matches and clear it out */
+    for (i = 0; i < ARRAY_SIZE(wlan.networks); i++)
+    {
+        if (wlan.networks[i].wps_network)
+            ret = wpa_supp_remove_network(netif, &wlan.networks[i]);
+    }
+    return ret;
+}
+
+int wlan_start_wps_pbc(void)
+{
+    int ret = -WM_FAIL;
+    struct netif *netif = net_get_sta_interface();
+
+    if (wlan.wps_session_attempt)
+    {
+        wlcm_d("WPS session is already in progress");
+        return ret;
+    }
+    wlan_remove_wps_network();
+    ret = wpa_supp_start_wps_pbc(netif, 0);
+
+    if (ret == -2)
+    {
+        wlcm_e("WPS PBC overlap detected");
+    }
+    return ret;
+}
+
+void wlan_wps_generate_pin(uint32_t *pin)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    wpa_supp_wps_generate_pin(netif, (unsigned int *)pin);
+}
+
+int wlan_start_wps_pin(const char *pin)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    if (wlan.wps_session_attempt)
+    {
+        wlcm_d("WPS session is already in progress");
+        return -WM_FAIL;
+    }
+
+    if (wpa_supp_wps_pin_valid(netif, (const unsigned char *)pin) != WM_SUCCESS)
+    {
+        wlcm_d("WPS PIN validation failed for %s", pin);
+        return -WM_FAIL;
+    }
+    wlan_remove_wps_network();
+    return wpa_supp_start_wps_pin(netif, pin, 0);
+}
+
+int wlan_wps_cancel(void)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    if (wlan.wps_session_attempt == 0)
+    {
+        return WM_SUCCESS;
+    }
+
+    return wpa_supp_cancel_wps(netif, 0);
+}
+
+#if CONFIG_WPA_SUPP_AP
+int wlan_start_ap_wps_pbc(void)
+{
+    struct netif *netif = net_get_uap_interface();
+
+    if (is_uap_started() == 0)
+    {
+        wlcm_e("Cannot Start WPS PBC as uAP is not running");
+        return -WM_FAIL;
+    }
+
+    return wpa_supp_start_wps_pbc(netif, 1);
+}
+
+int wlan_start_ap_wps_pin(const char *pin)
+{
+    struct netif *netif = net_get_uap_interface();
+
+    if (is_uap_started() == 0)
+    {
+        wlcm_e("Cannot Start WPS PIN as uAP is not running");
+        return -WM_FAIL;
+    }
+
+    if (wpa_supp_wps_pin_valid(netif, (const unsigned char *)pin) != WM_SUCCESS)
+    {
+        wlcm_d("WPS PIN validation failed for %s", pin);
+        return -WM_FAIL;
+    }
+
+    return wpa_supp_start_wps_pin(netif, pin, 1);
+}
+
+int wlan_wps_ap_cancel(void)
+{
+    struct netif *netif = net_get_uap_interface();
+
+    return wpa_supp_cancel_wps(netif, 1);
+}
+#endif
+#endif
+#endif
+
+#if (CONFIG_WPA2_ENTP) || (CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE)
+#if CONFIG_WIFI_USB_FILE_ACCESS
+static void wlan_entp_cert_cleanup()
+{
+    if (wlan.ca_cert_data != NULL)
+    {
+        OSA_MemoryFree(wlan.ca_cert_data);
+    }
+    if (wlan.client_cert_data != NULL)
+    {
+        OSA_MemoryFree(wlan.client_cert_data);
+    }
+    if (wlan.client_key_data != NULL)
+    {
+        OSA_MemoryFree(wlan.client_key_data);
+    }
+    if (wlan.ca_cert2_data != NULL)
+    {
+        OSA_MemoryFree(wlan.ca_cert2_data);
+    }
+    if (wlan.client_cert2_data != NULL)
+    {
+        OSA_MemoryFree(wlan.client_cert2_data);
+    }
+    if (wlan.client_key2_data != NULL)
+    {
+        OSA_MemoryFree(wlan.client_key2_data);
+    }
+
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    if (wlan.dh_data != NULL)
+    {
+        OSA_MemoryFree(wlan.dh_data);
+    }
+    if (wlan.server_cert_data != NULL)
+    {
+        OSA_MemoryFree(wlan.server_cert_data);
+    }
+    if (wlan.server_key_data != NULL)
+    {
+        OSA_MemoryFree(wlan.server_key_data);
+    }
+#endif
+#endif
+}
+
+int wlan_set_entp_cert_files(int cert_type, t_u8 *data, t_u32 data_len)
+{
+    if (cert_type == FILE_TYPE_ENTP_CA_CERT)
+    {
+        wlan.ca_cert_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.ca_cert_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("CA Cert malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.ca_cert_data, data, data_len);
+        wlan.ca_cert_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_CERT)
+    {
+        wlan.client_cert_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.client_cert_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Client Cert malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.client_cert_data, data, data_len);
+        wlan.client_cert_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_KEY)
+    {
+        wlan.client_key_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.client_key_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Client Key malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.client_key_data, data, data_len);
+        wlan.client_key_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CA_CERT2)
+    {
+        wlan.ca_cert2_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.ca_cert2_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("CA Cert2 malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.ca_cert2_data, data, data_len);
+        wlan.ca_cert2_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_CERT2)
+    {
+        wlan.client_cert2_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.client_cert2_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Client Cert2 malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.client_cert2_data, data, data_len);
+        wlan.client_cert2_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_KEY2)
+    {
+        wlan.client_key2_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.client_key2_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Client Key2 malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.client_key2_data, data, data_len);
+        wlan.client_key2_len = data_len;
+    }
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    else if (cert_type == FILE_TYPE_ENTP_DH_PARAMS)
+    {
+        wlan.dh_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.dh_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("DH params malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.dh_data, data, data_len);
+        wlan.dh_len = data_len;
+    }
+#endif
+#endif
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    else if (cert_type == FILE_TYPE_ENTP_SERVER_CERT)
+    {
+        wlan.server_cert_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.server_cert_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Server Cert malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.server_cert_data, data, data_len);
+        wlan.server_cert_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_SERVER_KEY)
+    {
+        wlan.server_key_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.server_key_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Server Key malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.server_key_data, data, data_len);
+        wlan.server_key_len = data_len;
+    }
+#endif
+#endif
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    else if (cert_type == FILE_TYPE_ENTP_SERVER_CERT)
+    {
+        wlan.server_cert_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.server_cert_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Server Cert malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.server_cert_data, data, data_len);
+        wlan.server_cert_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_SERVER_KEY)
+    {
+        wlan.server_key_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.server_key_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("Server Key malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.server_key_data, data, data_len);
+        wlan.server_key_len = data_len;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_DH_PARAMS)
+    {
+        wlan.dh_data = OSA_MemoryAllocate(data_len);
+        if (!wlan.dh_data)
+        {
+            wlan_entp_cert_cleanup();
+            wlcm_e("DH params malloc failed");
+            return -WM_FAIL;
+        }
+        memcpy(wlan.dh_data, data, data_len);
+        wlan.dh_len = data_len;
+    }
+#endif
+#endif
+    else
+    {
+        wlcm_e("Invalid file type");
+        return -WM_FAIL;
+    }
+
+    return WM_SUCCESS;
+}
+#endif
+
+t_u32 wlan_get_entp_cert_files(int cert_type, t_u8 **data)
+{
+    int len = 0;
+    if (cert_type == FILE_TYPE_ENTP_CA_CERT)
+    {
+        *data = wlan.ca_cert_data;
+        len   = wlan.ca_cert_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.ca_cert_data)
+        {
+            *data = (t_u8 *)ca_der;
+            len   = ca_der_len;
+        }
+#endif
+        wlan.ca_cert_data = NULL;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_CERT)
+    {
+        *data = wlan.client_cert_data;
+        len   = wlan.client_cert_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.client_cert_data)
+        {
+            *data = (t_u8 *)client_der;
+            len   = client_der_len;
+        }
+#endif
+        wlan.client_cert_data = NULL;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_KEY)
+    {
+        *data = wlan.client_key_data;
+        len   = wlan.client_key_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.client_key_data)
+        {
+            *data = (t_u8 *)client_key_der;
+            len   = client_key_der_len;
+        }
+#endif
+        wlan.client_key_data = NULL;
+    }
+    if (cert_type == FILE_TYPE_ENTP_CA_CERT2)
+    {
+        *data = wlan.ca_cert2_data;
+        len   = wlan.ca_cert2_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.ca_cert2_data)
+        {
+            *data = (t_u8 *)ca_der;
+            len   = ca_der_len;
+        }
+#endif
+        wlan.ca_cert2_data = NULL;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_CERT2)
+    {
+        *data = wlan.client_cert2_data;
+        len   = wlan.client_cert2_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.client_cert2_data)
+        {
+            *data = (t_u8 *)client_der;
+            len   = client_der_len;
+        }
+#endif
+        wlan.client_cert2_data = NULL;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_CLIENT_KEY2)
+    {
+        *data = wlan.client_key2_data;
+        len   = wlan.client_key2_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.client_key2_data)
+        {
+            *data = (t_u8 *)client_key_der;
+            len   = client_key_der_len;
+        }
+#endif
+        wlan.client_key2_data = NULL;
+    }
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    else if (cert_type == FILE_TYPE_ENTP_DH_PARAMS)
+    {
+        *data = wlan.dh_data;
+        len   = wlan.dh_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.dh_data)
+        {
+            *data = (t_u8 *)dh_der;
+            len   = dh_der_len;
+        }
+#endif
+        wlan.dh_data = NULL;
+    }
+#endif
+#endif
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    else if (cert_type == FILE_TYPE_ENTP_SERVER_CERT)
+    {
+        *data = wlan.server_cert_data;
+        len   = wlan.server_cert_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.server_cert_data)
+        {
+            *data = (t_u8 *)server_der;
+            len   = server_der_len;
+        }
+#endif
+        wlan.server_cert_data = NULL;
+    }
+    else if (cert_type == FILE_TYPE_ENTP_SERVER_KEY)
+    {
+        *data = wlan.server_key_data;
+        len   = wlan.server_key_len;
+#if !CONFIG_WIFI_USB_FILE_ACCESS
+        if (!wlan.server_key_data)
+        {
+            *data = (t_u8 *)server_key_der;
+            len   = server_key_der_len;
+        }
+#endif
+        wlan.server_key_data = NULL;
+    }
+#endif
+#endif
+
+    return len;
+}
+
+void wlan_free_entp_cert_files(void)
+{
+#if CONFIG_WIFI_USB_FILE_ACCESS
+    if (wlan.ca_cert_data != NULL)
+    {
+        wlan.ca_cert_data = NULL;
+        wlan.ca_cert_len  = 0;
+    }
+    if (wlan.client_cert_data != NULL)
+    {
+        wlan.client_cert_data = NULL;
+        wlan.client_cert_len  = 0;
+    }
+    if (wlan.client_key_data != NULL)
+    {
+        wlan.client_key_data = NULL;
+        wlan.client_key_len  = 0;
+    }
+    if (wlan.ca_cert2_data != NULL)
+    {
+        wlan.ca_cert2_data = NULL;
+        wlan.ca_cert2_len  = 0;
+    }
+    if (wlan.client_cert2_data != NULL)
+    {
+        wlan.client_cert2_data = NULL;
+        wlan.client_cert2_len  = 0;
+    }
+    if (wlan.client_key2_data != NULL)
+    {
+        wlan.client_key2_data = NULL;
+        wlan.client_key2_len  = 0;
+    }
+#if CONFIG_HOSTAPD
+#if CONFIG_WPA_SUPP_CRYPTO_AP_ENTERPRISE
+    if (wlan.dh_data != NULL)
+    {
+        wlan.dh_data = NULL;
+        wlan.dh_len  = 0;
+    }
+    if (wlan.server_cert_data != NULL)
+    {
+        wlan.server_cert_data = NULL;
+        wlan.server_cert_len  = 0;
+    }
+    if (wlan.server_key_data != NULL)
+    {
+        wlan.server_key_data = NULL;
+        wlan.server_key_len  = 0;
+    }
+#endif
+#endif
+#endif
+}
+#endif
+
+#if CONFIG_NET_MONITOR
+void wlan_register_monitor_user_callback(int (*monitor_data_recv_callback)(void *buffer, t_u16 data_len))
+{
+    register_monitor_user_callback(monitor_data_recv_callback);
+}
+
+void wlan_deregister_net_monitor_user_callback(void)
+{
+    deregister_monitor_user_callback();
+}
+
+int wlan_net_monitor_cfg(wlan_net_monitor_t *monitor)
+{
+    bool flag = false;
+
+    if (is_sta_connected() || is_uap_started())
+    {
+        (void)PRINTF("down the uap and disconnet sta first\n\r");
+        return WM_FAIL;
+    }
+
+    flag = (1 == monitor->monitor_activity) ? true : false;
+    set_monitor_flag(flag);
+    return wifi_net_monitor_cfg(monitor);
+}
+#endif
+
+#if CONFIG_TSP
+int wlan_get_tsp_cfg(t_u16 *enable,
+                     t_u32 *back_off,
+                     t_u32 *highThreshold,
+                     t_u32 *lowThreshold,
+                     t_u32 *dutycycstep,
+                     t_u32 *dutycycmin,
+                     int *highthrtemp,
+                     int *lowthrtemp,
+                     int *currCAUTemp,
+                     int *currRFUTemp)
+{
+    t_u16 action = 0;
+
+    return wifi_tsp_cfg(action, enable, back_off, highThreshold, lowThreshold, dutycycstep, dutycycmin, highthrtemp, lowthrtemp, currCAUTemp, currRFUTemp);
+}
+int wlan_set_tsp_cfg(t_u16 enable,
+                     t_u32 back_off,
+                     t_u32 highThreshold,
+                     t_u32 lowThreshold,
+                     t_u32 dutycycstep,
+                     t_u32 dutycycmin,
+                     int highthrtemp,
+                     int lowthrtemp)
+{
+    t_u16 action = 1;
+
+    return wifi_tsp_cfg(action, &enable, &back_off, &highThreshold, &lowThreshold, &dutycycstep, &dutycycmin, &highthrtemp, &lowthrtemp, NULL, NULL);
+}
+#endif
+
+int wlan_get_signal_info(wlan_rssi_info_t *signal)
+{
+    return wifi_send_rssi_info_cmd(signal);
+}
+
+int wlan_set_bandcfg(wlan_bandcfg_t *bandcfg)
+{
+    return wifi_get_set_bandcfg(bandcfg, MLAN_ACT_SET);
+}
+
+int wlan_get_bandcfg(wlan_bandcfg_t *bandcfg)
+{
+    return wifi_get_set_bandcfg(bandcfg, MLAN_ACT_GET);
+}
+
+#if CONFIG_TURBO_MODE
+int wlan_get_turbo_mode(t_u8 *mode)
+{
+    return wifi_get_turbo_mode(mode);
+}
+
+int wlan_get_uap_turbo_mode(t_u8 *mode)
+{
+    return wifi_get_uap_turbo_mode(mode);
+}
+
+int wlan_set_turbo_mode(t_u8 mode)
+{
+    return wifi_set_turbo_mode(mode);
+}
+
+int wlan_set_uap_turbo_mode(t_u8 mode)
+{
+    return wifi_set_uap_turbo_mode(mode);
+}
+#endif
+
+void wlan_set_ps_cfg(t_u16 multiple_dtims,
+                     t_u16 bcn_miss_timeout,
+                     t_u16 local_listen_interval,
+                     t_u16 adhoc_wake_period,
+                     t_u16 mode,
+                     t_u16 delay_to_ps)
+{
+    wifi_set_ps_cfg(multiple_dtims, bcn_miss_timeout, local_listen_interval, adhoc_wake_period, mode, delay_to_ps);
+}
+
+#if (CONFIG_IPS)
+int wlan_set_ips(int option)
+{
+    return wifi_set_ips_config(MLAN_BSS_TYPE_STA, option);
+}
+#endif
+
+int wlan_set_country_code(const char *alpha2)
+{
+    int ret;
+    t_u8 region_code_rw610;
+    unsigned char country3 = 0x20;
+    char country_code[COUNTRY_CODE_LEN] = {0};
+#ifndef RW610
+    char region_code[COUNTRY_CODE_LEN] = {0};
+    const char *wlan_region_code       = NULL;
+
+    wlan_region_code = wlan_get_wlan_region_code();
+
+    region_code[0] = alpha2[0];
+    region_code[1] = alpha2[1];
+
+    if (strstr(wlan_region_code, region_code) == NULL)
+    {
+        wlcm_d("Region %s is configured, re-config not allowed", wlan_region_code);
+        return -WM_FAIL;
+    }
+#endif
+
+    if ((alpha2[2] == 0x4f) || (alpha2[2] == 0x49) || (alpha2[2] == 0x58) || (alpha2[2] == 0x04))
+    {
+        country3 = alpha2[2];
+    }
+
+    country_code[0] = alpha2[0];
+    country_code[1] = alpha2[1];
+    country_code[2] = country3;
+
+    ret = wlan_11d_region_2_code(mlan_adap, (t_u8 *)country_code, &region_code_rw610);
+    if(ret != WM_SUCCESS)
+    {
+        wlcm_e("%s: Invalid country code.",country_code);
+        return ret;
+    }
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_WPA_SUPP_AP
+    struct netif *netif = net_get_uap_interface();
+
+    ret = wpa_supp_set_ap_country(netif, alpha2, country3);
+    if (ret != WM_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+#endif
+#endif
+    ret = wifi_set_country_code(country_code);
+    if (ret != WM_SUCCESS)
+        return ret;
+
+#if defined(RW610) && (CONFIG_COMPRESS_TX_PWTBL)
+    ret = wlan_set_rg_power_cfg(region_code_rw610);
+    if (ret != WM_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+#endif
+#if defined(RW610) && ((CONFIG_COMPRESS_RU_TX_PWTBL) && (CONFIG_11AX))
+    ret = wlan_set_ru_power_cfg(region_code_rw610);
+    if (ret != WM_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+#endif
+
+    return ret;
+}
+
+int wlan_set_country_ie_ignore(uint8_t *ignore)
+{
+    return wifi_set_country_ie_ignore(ignore);
+}
+
+int wlan_set_region_code(unsigned int region_code)
+{
+    char *country;
+
+    if ((region_code == 0x40) || (region_code == 0x41) || (region_code == 0xFE))
+    {
+        (void)PRINTF("Region code 0XFF is used for Japan to support channels of both 2.4GHz band and 5GHz band.\r\n");
+        return -WM_FAIL;
+    }
+
+    country = (char *)wlan_11d_code_2_region(mlan_adap, (unsigned char)region_code);
+    return wlan_set_country_code(country);
+}
+
+int wlan_get_region_code(unsigned int *region_code)
+{
+    return wifi_get_region_code(region_code);
+}
+
+int wlan_set_11d_state(int bss_type, int state)
+{
+#if CONFIG_WPA_SUPP_AP
+    struct netif *netif;
+#endif
+    if (bss_type == WLAN_BSS_TYPE_UAP)
+    {
+#if CONFIG_WPA_SUPP_AP
+        netif = net_get_uap_interface();
+        wpa_supp_set_ap_11d_state(netif, state);
+#endif
+
+        return wlan_enable_uap_11d(state);
+    }
+    else
+    {
+        return wlan_enable_11d(state);
+    }
+}
+
+#if CONFIG_COEX_DUTY_CYCLE
+int wlan_single_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime)
+{
+    return wifi_single_ant_duty_cycle(enable, nbTime, wlanTime);
+}
+
+int wlan_dual_ant_duty_cycle(t_u16 enable, t_u16 nbTime, t_u16 wlanTime, t_u16 wlanBlockTime)
+{
+    return wifi_dual_ant_duty_cycle(enable, nbTime, wlanTime, wlanBlockTime);
+}
+#endif
+
+#if CONFIG_EXTERNAL_COEX_PTA
+int wlan_external_coex_pta_cfg(ext_coex_pta_cfg coex_pta_config)
+{
+    return wifi_external_coex_pta_cfg(coex_pta_config);
+}
+#endif
+
+#if CONFIG_WPA_SUPP_DPP
+int wlan_dpp_configurator_add(int is_ap, const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+    int ret;
+
+    ret = wpa_supp_dpp_configurator_add(netif, is_ap, cmd);
+    if (ret <= 0)
+    {
+        wlcm_e("DPP add configurator failed!!");
+        return -WM_FAIL;
+    }
+    return ret;
+}
+
+void wlan_dpp_configurator_params(int is_ap, const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    wpa_supp_dpp_configurator_params(netif, is_ap, cmd);
+}
+
+void wlan_dpp_mud_url(int is_ap, const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    wpa_supp_dpp_mud_url(netif, is_ap, cmd);
+}
+
+int wlan_dpp_bootstrap_gen(int is_ap, const char *cmd)
+{
+    int id;
+    struct netif *netif = net_get_sta_interface();
+
+    id = wpa_supp_dpp_bootstrap_gen(netif, is_ap, cmd);
+    if (id < 0)
+    {
+        wlcm_e("DPP generate qrcode failed!!");
+        id = -WM_FAIL;
+    }
+    return id;
+}
+
+const char *wlan_dpp_bootstrap_get_uri(int is_ap, unsigned int id)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_dpp_bootstrap_get_uri(netif, is_ap, id);
+}
+
+int wlan_dpp_qr_code(int is_ap, char *uri)
+{
+    int id;
+    struct netif *netif = net_get_sta_interface();
+
+    id = wpa_supp_dpp_qr_code(netif, is_ap, uri);
+    if (id < 0)
+    {
+        wlcm_e("DPP enter QR code failed!!");
+        return -WM_FAIL;
+    }
+
+    return id;
+}
+
+int wlan_dpp_auth_init(int is_ap, const char *cmd)
+{
+    int ret;
+    struct netif *netif = net_get_sta_interface();
+
+    if (!is_ap)
+    {
+        wifi_set_rx_mgmt_indication(WLAN_BSS_ROLE_STA, WLAN_MGMT_ACTION);
+    }
+    ret = wpa_supp_dpp_auth_init(netif, is_ap, cmd);
+    if (ret < 0)
+    {
+        wlcm_e("DPP Auth Init failed!!");
+        return -WM_FAIL;
+    }
+
+    return ret;
+}
+
+int wlan_dpp_listen(int is_ap, const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_dpp_listen(netif, is_ap, cmd);
+}
+
+int wlan_dpp_stop_listen(int is_ap)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_dpp_stop_listen(netif, is_ap);
+}
+
+int wlan_dpp_pkex_add(int is_ap, const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    if (!is_ap)
+    {
+        wifi_set_rx_mgmt_indication(WLAN_BSS_ROLE_STA, WLAN_MGMT_ACTION);
+    }
+    if (wpa_supp_dpp_pkex_add(netif, is_ap, cmd) < 0)
+    {
+        wlcm_e("DPP add PKEX failed!!");
+        return -WM_FAIL;
+    }
+    return WM_SUCCESS;
+}
+
+int wlan_dpp_chirp(int is_ap, const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    if (!is_ap)
+    {
+        wifi_set_rx_mgmt_indication(WLAN_BSS_ROLE_STA, WLAN_MGMT_ACTION);
+    }
+    return wpa_supp_dpp_chirp(netif, is_ap, cmd);
+}
+
+int wlan_dpp_reconfig(const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_dpp_reconfig(netif, cmd);
+}
+
+int wlan_dpp_configurator_sign(int is_ap, const char *cmd)
+{
+    struct netif *netif = net_get_sta_interface();
+
+    return wpa_supp_dpp_configurator_sign(netif, is_ap, cmd);
+}
+#endif /* CONFIG_WPA_SUPP_DPP */
+
+#if CONFIG_IMD3_CFG
+int wlan_imd3_cfg(t_u8 imd3_value)
+{
+    return wifi_imd3_cfg(imd3_value);
+}
+#endif
+
+#if CONFIG_WPA_SUPP
+#if CONFIG_UAP_STA_MAC_ADDR_FILTER
+int wlan_host_set_sta_mac_filter(int filter_mode, int mac_count, unsigned char *mac_addr)
+{
+    int ret = 0;
+    struct netif *uap_netif = net_get_uap_interface();
+    ret = wpa_supp_set_mac_acl(uap_netif, filter_mode, mac_count, mac_addr);
+    if (ret < 0)
+        return -WM_FAIL;
+    else
+        return WM_SUCCESS;
+}
+#endif
+#endif
+
+#if (CONFIG_WIFI_IND_RESET) && (CONFIG_WIFI_IND_DNLD)
+int wlan_set_indrst_cfg(const wlan_indrst_cfg_t *indrst_cfg)
+{
+    wlan.ir_mode = indrst_cfg->ir_mode;
+
+    return wifi_set_indrst_cfg(indrst_cfg, (mlan_bss_type)WLAN_BSS_TYPE_STA);
+}
+
+int wlan_get_indrst_cfg(wlan_indrst_cfg_t *indrst_cfg)
+{
+    return wifi_get_indrst_cfg(indrst_cfg, (mlan_bss_type)WLAN_BSS_TYPE_STA);
+}
+
+static int wlan_trigger_oob_ind_reset()
+{
+    (void)wlan_ieeeps_off();
+
+    OSA_TimeDelay(1000);
+
+    (void)wlan_deepsleepps_off();
+
+    OSA_TimeDelay(1000);
+
+#ifdef IR_OUTBAND_TRIGGER_GPIO
+    GPIO_PinWrite(IR_OUTBAND_TRIGGER_GPIO, IR_OUTBAND_TRIGGER_GPIO_PIN, 0);
+
+    OSA_TimeDelay(10);
+
+    GPIO_PinWrite(IR_OUTBAND_TRIGGER_GPIO, IR_OUTBAND_TRIGGER_GPIO_PIN, 1);
+#endif
+
+    return wifi_trigger_oob_indrst();
+}
+
+int wlan_independent_reset(void)
+{
+    if (wlan.ir_mode == 1)
+    {
+        return wlan_trigger_oob_ind_reset();
+    }
+    else if (wlan.ir_mode == 2)
+    {
+        return wifi_test_independent_reset();
+    }
+
+    return -WM_FAIL;
+}
+#endif
+
+#if CONFIG_INACTIVITY_TIMEOUT_EXT
+int wlan_sta_inactivityto(wlan_inactivity_to_t *inac_to, t_u16 action)
+{
+    return wifi_sta_inactivityto(inac_to, action);
+}
+#endif
+
+#if CONFIG_CPU_LOADING
+
+static void wlan_cpu_loading_record_data(void)
+{
+    memset(cpu_loading.cpu_loading_info, 0, cpu_loading.task_status_len);
+
+    char run_task_name[configMAX_TASK_NAME_LEN];
+    char cpu_run_data[20];
+    unsigned int value;
+    int task_name_index = 0, task_time_index = 0, index = 0, task_index = 0;
+
+    OSA_GetRuntimeStats(cpu_loading.cpu_loading_info);
+
+    uint32_t len_data = strlen(cpu_loading.cpu_loading_info);
+    do
+    {
+        memset(run_task_name, 0, strlen(run_task_name));
+        /*Record task name*/
+        do
+        {
+            if(cpu_loading.cpu_loading_info[index] == ' ' && cpu_loading.cpu_loading_info[index + 1] == ' ') // Complete name parsing
+                break;
+            else
+                run_task_name[task_name_index++] = cpu_loading.cpu_loading_info[index++];
+        }while(index < len_data);
+
+        do      //Filter out padding spaces between task names and run time values.
+        {
+            if(cpu_loading.cpu_loading_info[index++] == '\t')
+                break;
+        } while (index < len_data);
+
+        /*Record task run time*/
+        do
+        {
+            if(cpu_loading.cpu_loading_info[index] < '0' || cpu_loading.cpu_loading_info[index] > '9')
+                break;
+            cpu_run_data[task_time_index++] = cpu_loading.cpu_loading_info[index++];
+        }while(index < len_data);
+
+        cpu_run_data[task_time_index] = '\0';
+        get_uint(cpu_run_data, &value, strlen(cpu_run_data));
+
+        if(cpu_loading.index > 0)
+        {
+            for(int i = 0; i < cpu_loading.task_nums; i++)  // To collect CPU loading info according to fixed task name sequence.
+            {
+                if(!strcmp(cpu_loading.task_name[i], run_task_name))
+                {
+                    cpu_loading.data_pre[i] = cpu_loading.data_cur[i];
+                    cpu_loading.data_cur[i] = value;
+                    break;
+                }
+            }
+        }
+        else
+        {
+            memset(task_string_name[task_index],' ', configMAX_TASK_NAME_LEN);
+            task_string_name[task_index][configMAX_TASK_NAME_LEN -1] = '\0';
+
+            memcpy(cpu_loading.task_name[task_index], run_task_name, strlen(run_task_name));
+            memcpy(task_string_name[task_index], run_task_name, strlen(run_task_name));
+            cpu_loading.data_pre[task_index] = value;
+            cpu_loading.data_cur[task_index] = value;
+            cpu_loading.first_data[task_index] = value;
+
+            cpu_loading.task_name[task_index][strlen(run_task_name)] = '\0';
+        }
+
+        /*Filter percentage value*/
+        do
+        {
+            if(cpu_loading.cpu_loading_info[index] == '\r' && cpu_loading.cpu_loading_info[index + 1] == '\n')
+            {
+                index += 2;
+                break;
+            }
+
+            index++;
+        }while((index < len_data));
+
+        task_time_index = 0;
+        task_name_index = 0;
+        task_index ++;
+
+    }while (index < len_data);
+
+    cpu_loading.index ++;
+    cpu_loading.sampling_loops --;
+}
+
+static void cpu_loading_task(osa_task_param_t arg)
+{
+    for(;;)
+    {
+        /* Wait till cpu loading timer time out. */
+        (void)os_event_notify_get(OS_WAIT_FOREVER);
+
+        if(cpu_loading.sampling_loops == 0)
+        {
+            wlan_cpu_loading_stop();
+        }
+        else
+        {
+            wlan_cpu_loading_record_data();
+            if(cpu_loading.index > 1)
+                wlan_cpu_loading_info_display();
+        }
+    }
+
+    OSA_ThreadSelfComplete(NULL);
+}
+
+static void cpu_loading_cb(osa_timer_arg_t arg)
+{
+    (void)os_event_notify_put(cpu_loading.cpu_loading_thread);
+}
+
+static int wlan_cpu_loading_start(uint32_t number, uint8_t period)
+{
+    int ret;
+    osa_status_t status;
+
+    if(cpu_loading.status == CPU_LOADING_STATUS_DEAD)
+    {
+        memset(&cpu_loading, 0, sizeof(cpu_loading));
+        if(period == 0)
+            cpu_loading.sampling_period = CPU_LOADING_PERIOD;
+        else
+            cpu_loading.sampling_period = period * (CPU_LOADING_PERIOD / 2);
+
+        status = OSA_TimerCreate((osa_timer_handle_t)cpu_loading.cpu_loading_timer, cpu_loading.sampling_period,
+                          &cpu_loading_cb, NULL, KOSA_TimerPeriodic, OSA_TIMER_NO_ACTIVATE);
+        if (status != KOSA_StatusSuccess)
+        {
+            (void)PRINTF("Unable to create cpu loading timer.\r\n");
+            return -WM_FAIL;
+        }
+
+        status = OSA_TaskCreate((osa_task_handle_t)cpu_loading.cpu_loading_task_Handle, OSA_TASK(cpu_loading_task), NULL);
+        if (status != KOSA_StatusSuccess)
+        {
+            (void)PRINTF("Unable to create cpu loading thread.\r\n");
+            return -WM_FAIL;
+        }
+
+        os_get_num_of_tasks(&cpu_loading.task_nums);
+        cpu_loading.task_status_len = cpu_loading.task_nums * sizeof(TaskStatus_t);
+        cpu_loading.cpu_loading_info = (char *)OSA_MemoryAllocate(cpu_loading.task_status_len);
+        if (cpu_loading.cpu_loading_info == NULL)
+        {
+            (void)PRINTF("%s: Failed to alloc cpu loading info\r\n", __func__);
+            return -WM_FAIL;
+        }
+
+        cpu_loading.index = 0;
+        if(number != 0)
+            cpu_loading.sampling_loops = number;
+        else
+            cpu_loading.sampling_loops = CPU_LOADING_KEEPING;
+
+        cpu_loading.status = CPU_LOADING_STATUS_ONGOING;
+
+        memset(cpu_loading.data_cur, 0, sizeof(cpu_loading.data_cur));
+        memset(cpu_loading.data_pre, 0, sizeof(cpu_loading.data_pre));
+        (void)OSA_TimerActivate((osa_timer_handle_t)cpu_loading.cpu_loading_timer);
+        return WM_SUCCESS;
+    }
+    else
+    {
+        wlcm_e("Unable to start cpu loading timer, pls stop the previous cpu loading test firstly.");
+        return -WM_FAIL;
+    }
+}
+
+int wlan_cpu_loading(uint8_t start, uint32_t number, uint8_t period)
+{
+    int ret;
+    if(start == CPU_LOADING_ACTION_STOP)
+    {
+        if(cpu_loading.status == CPU_LOADING_STATUS_DEAD)
+        {
+            (void)PRINTF("Collecting CPU loading info has already ended.\r\n");
+            return WM_SUCCESS;
+        }
+        else
+        {
+            cpu_loading.sampling_loops = 0;
+            OSA_TimerChange((osa_timer_handle_t)cpu_loading.cpu_loading_timer, 100, 0); // Chages value of cpu loading timer to stop cpu loading test quickly.
+            if(cpu_loading.status != CPU_LOADING_STATUS_DEAD)
+            {
+                OSA_TimeDelay(50);
+            }
+            return WM_SUCCESS;
+        }
+    }
+    else
+    {
+        return wlan_cpu_loading_start(number, period);
+    }
+}
+
+#endif
+
+#if CONFIG_AUTO_NULL_TX
+int wlan_auto_null_tx(wlan_auto_null_tx_t *auto_null_tx, mlan_bss_type bss_type)
+{
+    if (auto_null_tx == NULL)
+    {
+        return -WM_E_INVAL;
+    }
+
+    return wifi_auto_null_tx(auto_null_tx, bss_type);
+}
+#endif
+
+t_u16 wlan_get_status_code(enum wlan_event_reason reason)
+{
+    t_u16 status_code = 0;
+
+    switch (reason)
+    {
+        case WLAN_REASON_SUCCESS:
+            status_code = IEEE_STATUS_CODE_SUCCESS;
+            break;
+        case WLAN_REASON_USER_DISCONNECT:
+            status_code = IEEE_STATUS_CODE_REASON_UNSPECIFIED;
+            break;
+        case WLAN_REASON_LINK_LOST:
+            status_code = IEEE_STATUS_CODE_REASON_UNSPECIFIED;
+            break;
+        case WLAN_REASON_NETWORK_AUTH_FAILED:
+            status_code = IEEE_STATUS_CODE_INVALID_PARAMETERS;
+            break;
+        case WLAN_REASON_NETWORK_NOT_FOUND:
+            status_code = IEEE_STATUS_CODE_POOR_CHANNEL_CONDITIONS;
+            break;
+        case WLAN_REASON_CONNECT_FAILED:
+            status_code = IEEE_STATUS_CODE_REQUEST_DECLINED;
+            break;
+        default:
+            status_code = IEEE_STATUS_CODE_REASON_UNSPECIFIED;
+            break;
+    }
+
+    return status_code;
+}
+
+#ifdef RW610
+int32_t wlan_get_temperature()
+{
+    return wifi_get_temperature();
+}
+#endif
+
+char *wlan_string_dup(const char *s)
+{
+    char *snew = (char *)OSA_MemoryAllocate(strlen(s) + 1);
+    if (snew)
+        (void)strcpy(snew, s);
+    return snew;
+}
+
+uint32_t wlan_get_board_type(void)
+{
+    uint32_t board_type = 0xff;
+
+#ifdef RW610
+    board_type = wifi_get_board_type();
+#endif
+
+    return board_type;
+}
+
+int wlan_uap_disconnect_sta(uint8_t *sta_addr)
+{
+    int ret;
+    t_u16 reason_code = WLAN_REASON_CODE_PREV_AUTH_NOT_VALID;
+
+#if CONFIG_WPA_SUPP
+    struct netif *netif = net_get_uap_interface();
+    ret = wpa_supp_deauth_sta(netif, sta_addr);
+#else
+    ret = wifi_sta_deauth(sta_addr, reason_code);
+#endif
+
+    if(ret != WM_SUCCESS)
+    {
+        (void)PRINTF("Error: Failed to disconnect sta.\r\n");
+    }
+
+    return ret;
+}
+
+int wlan_11n_allowed(struct wlan_network *network)
+{
+    mlan_private *pmpriv       = (mlan_private *)mlan_adap->priv[network->role];
+    mlan_adapter *pmadapter    = pmpriv->adapter;
+    BSSDescriptor_t *pbss_desc = NULL;
+
+    if (ISSUPP_11NENABLED(pmadapter->fw_cap_info) &&
+        (pmpriv->config_bands & BAND_GN || pmpriv->config_bands & BAND_AN))
+    {
+        if (network->role == WLAN_BSS_ROLE_STA)
+        {
+            pbss_desc = &pmpriv->curr_bss_params.bss_descriptor;
+            return ((!pbss_desc->disable_11n) && (pbss_desc->pht_cap != NULL));
+        }
+#if CONFIG_WIFI_CAPA
+        else if (network->role == WLAN_BSS_ROLE_UAP)
+        {
+            if (network->wlan_capa & WIFI_SUPPORT_11N)
+                return 1;
+        }
+#endif
+    }
+
+    return 0;
+}
+
+#if CONFIG_11AC
+int wlan_11ac_allowed(struct wlan_network *network)
+{
+    mlan_private *pmpriv       = (mlan_private *)mlan_adap->priv[network->role];
+    mlan_adapter *pmadapter    = pmpriv->adapter;
+    BSSDescriptor_t *pbss_desc = NULL;
+
+    if (ISSUPP_11ACENABLED(pmadapter->fw_cap_info))
+    {
+        if (network->role == WLAN_BSS_ROLE_STA)
+        {
+            pbss_desc = &pmpriv->curr_bss_params.bss_descriptor;
+            if (wlan_11ac_bandconfig_allowed(pmpriv, pbss_desc->bss_band))
+                return ((!pbss_desc->disable_11n) && (pbss_desc->pvht_cap != NULL));
+        }
+#if CONFIG_WIFI_CAPA
+        else if (network->role == WLAN_BSS_ROLE_UAP)
+        {
+            if ((pmpriv->config_bands & BAND_GAC || pmpriv->config_bands & BAND_AAC) && (network->wlan_capa & WIFI_SUPPORT_11AC))
+                return 1;
+        }
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+#if CONFIG_11AX
+int wlan_11ax_allowed(struct wlan_network *network)
+{
+    mlan_private *pmpriv       = (mlan_private *)mlan_adap->priv[network->role];
+    mlan_adapter *pmadapter    = pmpriv->adapter;
+    BSSDescriptor_t *pbss_desc = NULL;
+
+    if (IS_FW_SUPPORT_11AX(pmadapter))
+    {
+        if (network->role == WLAN_BSS_ROLE_STA)
+        {
+            pbss_desc = &pmpriv->curr_bss_params.bss_descriptor;
+            if (wlan_11ax_bandconfig_allowed(pmpriv, pbss_desc->bss_band))
+                return ((!pbss_desc->disable_11n) && (pbss_desc->phe_cap != NULL));
+        }
+#if CONFIG_WIFI_CAPA
+        else if (network->role == WLAN_BSS_ROLE_UAP)
+        {
+            if ((pmpriv->config_bands & BAND_GAX || pmpriv->config_bands & BAND_AAX) && (network->wlan_capa & WIFI_SUPPORT_11AX))
+                return 1;
+        }
+#endif
+    }
+
+    return 0;
+}
+#endif
diff --git a/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wlcmgr/wlan_txpwrlimit_cfg.c b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wlcmgr/wlan_txpwrlimit_cfg.c
new file mode 100644
index 0000000000..39b31a1f78
--- /dev/null
+++ b/tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/wifi/wlcmgr/wlan_txpwrlimit_cfg.c
@@ -0,0 +1,369 @@
+/** @file wlan_txpwrlimit_cfg.c
+ *
+ *  @brief  This file provides WLAN World Wide Safe Mode Tx Power Limit APIs.
+ *
+ *  Copyright 2008-2021, 2023 NXP
+ *
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <wlan.h>
+#include <wifi.h>
+#ifdef RW610
+#include "fsl_ocotp.h"
+#endif
+
+#ifdef WIFI_BT_TX_PWR_LIMITS
+#include WIFI_BT_TX_PWR_LIMITS
+#else
+#error "Region tx power config not defined"
+#endif
+
+#if defined(RW610) && (CONFIG_COMPRESS_TX_PWTBL || ((CONFIG_COMPRESS_RU_TX_PWTBL) && (CONFIG_11AX)))
+typedef struct _rg_power_info
+{
+    t_u8 *rg_power_table;
+    t_u16 rg_len;
+} rg_power_info;
+#endif
+
+#if defined(RW610) && ((CONFIG_COMPRESS_RU_TX_PWTBL) && (CONFIG_11AX))
+typedef struct _ru_power_cfg
+{
+    t_u16 region_code;
+    rg_power_info power_info;
+} ru_power_cfg;
+
+/* All type boards ru txpwr data is same, */
+ru_power_cfg ru_power_cfg_rw610[] = {
+    {0x00, .power_info = {(t_u8 *)rutxpowerlimit_cfg_set_WW, sizeof(rutxpowerlimit_cfg_set_WW)}},
+    {0x10, .power_info = {(t_u8 *)rutxpowerlimit_cfg_set_FCC, sizeof(rutxpowerlimit_cfg_set_FCC)}},
+    {0x30, .power_info = {(t_u8 *)rutxpowerlimit_cfg_set_EU, sizeof(rutxpowerlimit_cfg_set_EU)}},
+    {0x50, .power_info = {(t_u8 *)rutxpowerlimit_cfg_set_CN, sizeof(rutxpowerlimit_cfg_set_CN)}},
+    {0xFF, .power_info = {(t_u8 *)rutxpowerlimit_cfg_set_JP, sizeof(rutxpowerlimit_cfg_set_JP)}},
+};
+
+int wlan_set_ru_power_cfg(t_u16 region_code)
+{
+    int i  = 0;
+    int rv = -WM_FAIL;
+
+    for (i = 0; i < sizeof(ru_power_cfg_rw610) / sizeof(ru_power_cfg); i++)
+    {
+        if (region_code == ru_power_cfg_rw610[i].region_code)
+        {
+            rv = wlan_set_11ax_rutxpowerlimit(ru_power_cfg_rw610[i].power_info.rg_power_table,
+                                              ru_power_cfg_rw610[i].power_info.rg_len);
+
+            return rv;
+        }
+    }
+
+    /* Set default world wide ru txpwr if ru_power_cfg_rw610 does not have a corresponding region_code temporarily */
+    wlcm_d("power_info of region_code %d not available, use default world wide ru txpwr by default.", region_code);
+
+    rv = wlan_set_11ax_rutxpowerlimit(ru_power_cfg_rw610[0].power_info.rg_power_table,
+                                      ru_power_cfg_rw610[0].power_info.rg_len);
+
+    return rv;
+}
+#endif
+
+#if defined(RW610) && (CONFIG_COMPRESS_TX_PWTBL)
+#define MAX_SOC_OTP_LINE 64
+#define OTP_PKG_TAG      0x15D
+#define PKG_TYPE_MAX     3
+
+typedef struct _rg_power_cfg
+{
+    t_u16 region_code;
+    rg_power_info power_info[PKG_TYPE_MAX];
+} rg_power_cfg;
+
+/* For CSP board, we didn't get tx_power_table data, so use bga data temporary
+ * And maybe no BGA or QFN data for avaliable region, use other type data
+ */
+rg_power_cfg rg_power_cfg_rw610[] = {
+    {0x00, .power_info[RW610_PACKAGE_TYPE_QFN] = {(t_u8 *)rg_rw610_WW, sizeof(rg_rw610_WW)},
+     .power_info[RW610_PACKAGE_TYPE_CSP] = {(t_u8 *)rg_rw610_WW, sizeof(rg_rw610_WW)},
+     .power_info[RW610_PACKAGE_TYPE_BGA] = {(t_u8 *)rg_rw610_WW, sizeof(rg_rw610_WW)}},
+    {0x10, .power_info[RW610_PACKAGE_TYPE_QFN] = {(t_u8 *)rg_rw610_qfn, sizeof(rg_rw610_qfn)},
+     .power_info[RW610_PACKAGE_TYPE_CSP] = {(t_u8 *)rg_rw610_csp, sizeof(rg_rw610_csp)},
+     .power_info[RW610_PACKAGE_TYPE_BGA] = {(t_u8 *)rg_rw610_bga, sizeof(rg_rw610_bga)}},
+    {0x30, .power_info[RW610_PACKAGE_TYPE_QFN] = {(t_u8 *)rg_rw610_EU, sizeof(rg_rw610_EU)},
+     .power_info[RW610_PACKAGE_TYPE_CSP] = {(t_u8 *)rg_rw610_EU, sizeof(rg_rw610_EU)},
+     .power_info[RW610_PACKAGE_TYPE_BGA] = {(t_u8 *)rg_rw610_EU, sizeof(rg_rw610_EU)}},
+    {0x50, .power_info[RW610_PACKAGE_TYPE_QFN] = {(t_u8 *)rg_rw610_CN, sizeof(rg_rw610_CN)},
+     .power_info[RW610_PACKAGE_TYPE_CSP] = {(t_u8 *)rg_rw610_CN, sizeof(rg_rw610_CN)},
+     .power_info[RW610_PACKAGE_TYPE_BGA] = {(t_u8 *)rg_rw610_CN, sizeof(rg_rw610_CN)}},
+    {0xFF, .power_info[RW610_PACKAGE_TYPE_QFN] = {(t_u8 *)rg_rw610_JP, sizeof(rg_rw610_JP)},
+     .power_info[RW610_PACKAGE_TYPE_CSP] = {(t_u8 *)rg_rw610_JP, sizeof(rg_rw610_JP)},
+     .power_info[RW610_PACKAGE_TYPE_BGA] = {(t_u8 *)rg_rw610_JP, sizeof(rg_rw610_JP)}},
+};
+
+int wlan_set_rg_power_cfg(t_u16 region_code)
+{
+    int i               = 0;
+    uint32_t board_type = 0;
+    int rv              = WM_SUCCESS;
+
+    board_type = wifi_get_board_type();
+    if (RW610_PACKAGE_TYPE_QFN == board_type)
+    {
+        (void)PRINTF("PKG_TYPE: QFN\r\n");
+        (void)PRINTF("Set QFN tx power table data \r\n");
+    }
+    else if (RW610_PACKAGE_TYPE_BGA == board_type)
+    {
+        (void)PRINTF("PKG_TYPE: BGA\r\n");
+        (void)PRINTF("Set BGA tx power table data \r\n");
+    }
+    else if (RW610_PACKAGE_TYPE_CSP == board_type)
+    {
+        (void)PRINTF("PKG_TYPE: CSP\r\n");
+        (void)PRINTF("Set CSP tx power table data \r\n");
+    }
+    else
+    {
+        board_type = RW610_PACKAGE_TYPE_BGA;
+        (void)PRINTF("PKG_TYPE: UNKNOWN\r\n");
+        (void)PRINTF("Set BGA tx power table data \r\n");
+        (void)PRINTF("Can't get board type, we use bga data default \r\n");
+    }
+
+    for (i = 0; i < sizeof(rg_power_cfg_rw610) / sizeof(rg_power_cfg); i++)
+    {
+        if (region_code == rg_power_cfg_rw610[i].region_code)
+        {
+            rv = wlan_set_region_power_cfg(rg_power_cfg_rw610[i].power_info[board_type].rg_power_table,
+                                           rg_power_cfg_rw610[i].power_info[board_type].rg_len);
+
+            return rv;
+        }
+    }
+
+    /* Set default world wide power table if rg_power_cfg_rw610 does not have a corresponding region_code temporarily */
+    wlcm_d("power_info of region_code %d not available, use default world wide power table by default.", region_code);
+
+    rv = wlan_set_region_power_cfg(rg_power_cfg_rw610[0].power_info[board_type].rg_power_table,
+                                   rg_power_cfg_rw610[0].power_info[board_type].rg_len);
+
+    return rv;
+}
+#elif (CONFIG_COMPRESS_TX_PWTBL)
+typedef struct _rg_power_cfg
+{
+    t_u16 region_code;
+    t_u8 *rg_power_table;
+    t_u16 rg_len;
+} rg_power_cfg;
+
+rg_power_cfg rg_power_cfg_FC[] = {
+    {
+        0x00,
+        (t_u8 *)rg_table_fc,
+        sizeof(rg_table_fc),
+    },
+};
+
+int wlan_set_rg_power_cfg(t_u16 region_code)
+{
+    int i  = 0;
+    int rv = WM_SUCCESS;
+
+    for (i = 0; i < sizeof(rg_power_cfg_FC) / sizeof(rg_power_cfg); i++)
+    {
+        if (region_code == rg_power_cfg_FC[i].region_code)
+        {
+            rv = wlan_set_region_power_cfg(rg_power_cfg_FC[i].rg_power_table, rg_power_cfg_FC[i].rg_len);
+            if (rv != WM_SUCCESS)
+                (void)PRINTF("Unable to set compressed TX power table configuration\r\n");
+            return rv;
+        }
+    }
+
+    return -WM_FAIL;
+}
+
+#endif
+
+#if CONFIG_COMPRESS_TX_PWTBL || ((CONFIG_COMPRESS_RU_TX_PWTBL) && (CONFIG_11AX))
+int wlan_set_wwsm_txpwrlimit()
+{
+    int rv = WM_SUCCESS;
+#ifdef WLAN_REGION_CODE
+    rv = wlan_set_country_code(WLAN_REGION_CODE);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set country code\r\n");
+        return -WM_FAIL;
+    }
+#endif
+#ifdef RW610
+    unsigned int region_code = 0;
+#endif
+#ifdef WLAN_REGION_CODE
+    rv = wlan_set_country_code(WLAN_REGION_CODE);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set country code\r\n");
+        return -WM_FAIL;
+    }
+#endif
+#ifdef RW610
+    ARG_UNUSED(tx_pwrlimit_2g_cfg);
+    ARG_UNUSED(chanlist_2g_cfg);
+#if CONFIG_5GHz_SUPPORT
+    ARG_UNUSED(tx_pwrlimit_5g_cfg);
+    ARG_UNUSED(chanlist_5g_cfg);
+#endif
+#endif
+#ifndef RW610
+    rv = wlan_set_chanlist(&chanlist_2g_cfg);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set 2G chanlist configuration\r\n");
+        return -WM_FAIL;
+    }
+#if CONFIG_5GHz_SUPPORT
+    rv = wlan_set_chanlist(&chanlist_5g_cfg);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set 5G chanlist configuration\r\n");
+        return -WM_FAIL;
+    }
+#endif
+#endif
+#ifdef RW610
+    wlan_get_region_code(&region_code);
+#if CONFIG_COMPRESS_TX_PWTBL
+    rv = wlan_set_rg_power_cfg(region_code);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set compressed TX power table configuration\r\n");
+        return -WM_FAIL;
+    }
+#endif
+
+#if (CONFIG_COMPRESS_RU_TX_PWTBL) && (CONFIG_11AX)
+    rv = wlan_set_ru_power_cfg(region_code);
+    if (rv != WM_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+#endif
+
+#else
+    rv = wlan_set_region_power_cfg(rg_table_fc, rg_table_fc_len);
+    if (rv != WM_SUCCESS)
+    {
+        return -WM_FAIL;
+    }
+#endif /* RW610 */
+
+#ifndef RW610
+#if CONFIG_11AX
+#if CONFIG_COMPRESS_RU_TX_PWTBL
+    rv = wlan_set_11ax_rutxpowerlimit(rutxpowerlimit_cfg_set, sizeof(rutxpowerlimit_cfg_set));
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set RU TX PWR Limit configuration\r\n");
+        return -WM_FAIL;
+    }
+#else
+    rv = wlan_set_11ax_rutxpowerlimit_legacy(&rutxpowerlimit_2g_cfg_set);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set 2G RU TX PWR Limit configuration\r\n");
+        return -WM_FAIL;
+    }
+#if CONFIG_5GHz_SUPPORT
+    else
+    {
+        rv = wlan_set_11ax_rutxpowerlimit_legacy(&rutxpowerlimit_5g_cfg_set);
+        if (rv != WM_SUCCESS)
+        {
+            (void)PRINTF("Unable to set 5G RU TX PWR Limit configuration\r\n");
+            return -WM_FAIL;
+        }
+    }
+#endif
+#endif /* CONFIG_COMPRESS_RU_TX_PWTBL */
+#endif /* CONFIG_11AX */
+#endif /* RW610 */
+
+    return rv;
+}
+#else
+int wlan_set_wwsm_txpwrlimit(void)
+{
+    int rv = WM_SUCCESS;
+#ifdef WLAN_REGION_CODE
+    rv     = wlan_set_country_code(WLAN_REGION_CODE);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set country code\r\n");
+        return -WM_FAIL;
+    }
+#endif
+    rv = wlan_set_chanlist_and_txpwrlimit(&chanlist_2g_cfg, &tx_pwrlimit_2g_cfg);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set 2G TX PWR Limit configuration\r\n");
+        return -WM_FAIL;
+    }
+#if CONFIG_5GHz_SUPPORT
+    rv = wlan_set_chanlist_and_txpwrlimit(&chanlist_5g_cfg, &tx_pwrlimit_5g_cfg);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set 5G TX PWR Limit configuration\r\n");
+        return -WM_FAIL;
+    }
+#endif
+
+#ifndef RW610
+#if CONFIG_11AX
+#if CONFIG_COMPRESS_RU_TX_PWTBL
+    rv = wlan_set_11ax_rutxpowerlimit(rutxpowerlimit_cfg_set, sizeof(rutxpowerlimit_cfg_set));
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set RU TX PWR Limit configuration\r\n");
+        return -WM_FAIL;
+    }
+#else
+    rv = wlan_set_11ax_rutxpowerlimit_legacy(&rutxpowerlimit_2g_cfg_set);
+    if (rv != WM_SUCCESS)
+    {
+        (void)PRINTF("Unable to set 2G RU TX PWR Limit configuration\r\n");
+        return -WM_FAIL;
+    }
+#if CONFIG_5GHz_SUPPORT
+    else
+    {
+        rv = wlan_set_11ax_rutxpowerlimit_legacy(&rutxpowerlimit_5g_cfg_set);
+        if (rv != WM_SUCCESS)
+        {
+            (void)PRINTF("Unable to set 5G RU TX PWR Limit configuration\r\n");
+            return -WM_FAIL;
+        }
+    }
+#endif
+#endif /* CONFIG_COMPRESS_RU_TX_PWTBL */
+#endif /* CONFIG_11AX */
+#endif /* RW610 */
+
+    return rv;
+}
+#endif /* CONFIG_COMPRESS_TX_PWTBL */
+
+#ifndef RW610
+const char *wlan_get_wlan_region_code(void)
+{
+#ifdef WLAN_REGION_CODE
+    return WLAN_REGION_CODE;
+#else
+#error "Please define WLAN_REGION_CODE in Region tx power config file"
+#endif
+}
+#endif
diff --git a/tutorials/pico-sdk/pico-2-w-picosdk-baremetal-builtin-ap/main.c b/tutorials/pico-sdk/pico-2-w-picosdk-baremetal-builtin-ap/main.c
index 47e77dd4a5..f1dfccf137 100644
--- a/tutorials/pico-sdk/pico-2-w-picosdk-baremetal-builtin-ap/main.c
+++ b/tutorials/pico-sdk/pico-2-w-picosdk-baremetal-builtin-ap/main.c
@@ -7,7 +7,6 @@
 #define WIFI_SSID "YOUR_WIFI_NETWORK_NAME"  // SET THIS!
 #define WIFI_PASS "YOUR_WIFI_PASSWORD"      // SET THIS!
 
-static uint32_t s_ip, s_mask;
 
 
 // mif user states
@@ -21,13 +20,7 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
   }
   switch(state) {
     case AP: // we are in AP mode, wait for a user connection to trigger a scan or a connection to a network
-      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
-        MG_INFO(("Access Point started"));
-        s_ip = ifp->ip, ifp->ip = MG_IPV4(192, 168, 169, 1);
-        s_mask = ifp->mask, ifp->mask = MG_IPV4(255, 255, 255, 0);
-        ifp->enable_dhcp_client = false;
-        ifp->enable_dhcp_server = true;
-      } else if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
         MG_INFO(("Access Point READY !"));
 
         // simulate user request to scan for networks
@@ -53,18 +46,14 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
       break;
     case STOPPING_AP:
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_pico_w_data *d = (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
-        d->apmode = false;
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_pico_w_data *) ifp->driver_data)->wifi;
+        wifi->apmode = false;
 
         // simulate user selection of a network (2/2: actual connect)
-        bool res = mg_wifi_connect(d->ssid, d->pass);
+        bool res = mg_wifi_connect(wifi);
         MG_INFO(("Manually connecting: %s", res ? "OK":"FAIL"));
         if (res) {
           state = CONNECTING;
-          ifp->ip = s_ip;
-          ifp->mask = s_mask;
-          if (ifp->ip == 0) ifp->enable_dhcp_client = true;
-          ifp->enable_dhcp_server = false;
         } // else manually start AP as below
       }
       break;
@@ -84,13 +73,13 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
     case READY:
       // go back to AP mode after a disconnection (simulation 2/2), you could retry
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_pico_w_data *d = (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
-        bool res = mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_pico_w_data *) ifp->driver_data)->wifi;
+        bool res = mg_wifi_ap_start(wifi);
         MG_INFO(("Disconnected"));
         MG_INFO(("Manually starting AP: %s", res ? "OK":"FAIL"));
         if (res) {
           state = AP;
-          d->apmode = true;
+          wifi->apmode = true;
         }
       }
       break;
@@ -108,17 +97,19 @@ int main(void) {
 
   // Initialise WiFi creds
   struct mg_tcpip_driver_pico_w_data driver_data = {
-    .ssid = WIFI_SSID,
-    .pass = WIFI_PASS,
-    .apssid = "mongoose",
-    .appass = "eightchars",
-    .security = 0,
-    .apsecurity = 0,
-    .apchannel = 10,
-    .apmode = true
+    .wifi.ssid = WIFI_SSID,
+    .wifi.pass = WIFI_PASS,
+    .wifi.apssid = "mongoose",
+    .wifi.appass = "eightchars",
+    .wifi.apip = MG_IPV4(192, 168, 169, 1),
+    .wifi.apmask = MG_IPV4(255, 255, 255, 0),
+    .wifi.security = 0,
+    .wifi.apsecurity = 0,
+    .wifi.apchannel = 10,
+    .wifi.apmode = true
   };
 
-  state = driver_data.apmode ? AP : CONNECTING;
+  state = driver_data.wifi.apmode ? AP : CONNECTING;
 
   // Initialise Mongoose network stack
   // Either set use_dhcp or enter a static config.
diff --git a/tutorials/stm32/portenta-h7-make-baremetal-builtin/main.c b/tutorials/stm32/portenta-h7-make-baremetal-builtin/main.c
index 025fc6d5dc..2190b49c1c 100644
--- a/tutorials/stm32/portenta-h7-make-baremetal-builtin/main.c
+++ b/tutorials/stm32/portenta-h7-make-baremetal-builtin/main.c
@@ -50,23 +50,15 @@ static const struct mg_tcpip_driver_cyw_firmware fw = {
 // mif user states
 enum {AP, SCANNING, STOPPING_AP, CONNECTING, READY};
 static unsigned int state;
-static uint32_t s_ip, s_mask;
 
 
 static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
-  // TODO(): should we include this inside ifp ? add an fn_data ?
   if (ev == MG_TCPIP_EV_ST_CHG) {
     MG_INFO(("State change: %u", *(uint8_t *) ev_data));
   }
   switch(state) {
     case AP: // we are in AP mode, wait for a user connection to trigger a scan or a connection to a network
-      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
-        MG_INFO(("Access Point started"));
-        s_ip = ifp->ip, ifp->ip = MG_IPV4(192, 168, 169, 1);
-        s_mask = ifp->mask, ifp->mask = MG_IPV4(255, 255, 255, 0);
-        ifp->enable_dhcp_client = false;
-        ifp->enable_dhcp_server = true;
-      } else if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
         MG_INFO(("Access Point READY !"));
 
         // simulate user request to scan for networks
@@ -80,7 +72,6 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
         struct mg_wifi_scan_bss_data *bss = (struct mg_wifi_scan_bss_data *) ev_data;
         MG_INFO(("BSS: %.*s (%u) (%M) %d dBm %u", bss->SSID.len, bss->SSID.buf, bss->channel, mg_print_mac, bss->BSSID, (int) bss->RSSI, bss->security));
       } else if (ev == MG_TCPIP_EV_WIFI_SCAN_END) {
-        // struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
         MG_INFO(("Wi-Fi scan finished"));
 
         // simulate user selection of a network (1/2: stop AP)
@@ -92,18 +83,14 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
       break;
     case STOPPING_AP:
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-        d->apmode = false;
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+        wifi->apmode = false;
 
         // simulate user selection of a network (2/2: actual connect)
-        bool res = mg_wifi_connect(d->ssid, d->pass);
+        bool res = mg_wifi_connect(wifi);
         MG_INFO(("Manually connecting: %s", res ? "OK":"FAIL"));
         if (res) {
           state = CONNECTING;
-          ifp->ip = s_ip;
-          ifp->mask = s_mask;
-          if (ifp->ip == 0) ifp->enable_dhcp_client = true;
-          ifp->enable_dhcp_server = false;
         } // else manually start AP as below
       }
       break;
@@ -123,13 +110,13 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
     case READY:
       // go back to AP mode after a disconnection (simulation 2/2), you could retry
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-        bool res = mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+        bool res = mg_wifi_ap_start(wifi);
         MG_INFO(("Disconnected"));
         MG_INFO(("Manually starting AP: %s", res ? "OK":"FAIL"));
         if (res) {
           state = AP;
-          d->apmode = true;
+          wifi->apmode = true;
         }
       }
       break;
@@ -138,14 +125,16 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
 
 
 static struct mg_tcpip_driver_cyw_data d = {
-  (void *)&sdio, (struct mg_tcpip_driver_cyw_firmware *)&fw, WIFI_SSID, WIFI_PASS, "mongoose", "mongoose", 0, 0, 10, true, false};
+  {WIFI_SSID, WIFI_PASS, "mongoose", "mongoose", 0, 0, 0, 0, 10, true}, (void *)&sdio, (struct mg_tcpip_driver_cyw_firmware *)&fw, false};
 
 int main(void) {
   hal_init();
 
   hwspecific_sdio_init();
 
-  state = d.apmode ? AP : CONNECTING;
+  d.wifi.apip = MG_IPV4(192, 168, 169, 1),
+  d.wifi.apmask = MG_IPV4(255, 255, 255, 0),
+  state = d.wifi.apmode ? AP : CONNECTING;
 
   struct mg_mgr mgr;        // Initialise Mongoose event manager
   mg_mgr_init(&mgr);        // and attach it to the interface
diff --git a/tutorials/stm32/rm2-nucleo-f429zi-make-baremetal-builtin/main.c b/tutorials/stm32/rm2-nucleo-f429zi-make-baremetal-builtin/main.c
index 4570a6a3aa..f722bcf50e 100644
--- a/tutorials/stm32/rm2-nucleo-f429zi-make-baremetal-builtin/main.c
+++ b/tutorials/stm32/rm2-nucleo-f429zi-make-baremetal-builtin/main.c
@@ -81,7 +81,6 @@ static const struct mg_tcpip_driver_cyw_firmware fw = {
 // mif user states
 enum {AP, SCANNING, STOPPING_AP, CONNECTING, READY};
 static unsigned int state;
-static uint32_t s_ip, s_mask;
 
 
 static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
@@ -95,13 +94,7 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
   }
   switch(state) {
     case AP: // we are in AP mode, wait for a user connection to trigger a scan or a connection to a network
-      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
-        MG_INFO(("Access Point started"));
-        s_ip = ifp->ip, ifp->ip = MG_IPV4(192, 168, 169, 1);
-        s_mask = ifp->mask, ifp->mask = MG_IPV4(255, 255, 255, 0);
-        ifp->enable_dhcp_client = false;
-        ifp->enable_dhcp_server = true;
-      } else if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
         MG_INFO(("Access Point READY !"));
 
         // simulate user request to scan for networks
@@ -115,7 +108,7 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
         struct mg_wifi_scan_bss_data *bss = (struct mg_wifi_scan_bss_data *) ev_data;
         MG_INFO(("BSS: %.*s (%u) (%M) %d dBm %u", bss->SSID.len, bss->SSID.buf, bss->channel, mg_print_mac, bss->BSSID, (int) bss->RSSI, bss->security));
       } else if (ev == MG_TCPIP_EV_WIFI_SCAN_END) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
+        //struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
         MG_INFO(("Wi-Fi scan finished"));
 
         // simulate user selection of a network (1/2: stop AP)
@@ -127,18 +120,14 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
       break;
     case STOPPING_AP:
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-        d->apmode = false;
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+        wifi->apmode = false;
 
         // simulate user selection of a network (2/2: actual connect)
-        bool res = mg_wifi_connect(d->ssid, d->pass);
+        bool res = mg_wifi_connect(wifi);
         MG_INFO(("Manually connecting: %s", res ? "OK":"FAIL"));
         if (res) {
           state = CONNECTING;
-          ifp->ip = s_ip;
-          ifp->mask = s_mask;
-          if (ifp->ip == 0) ifp->enable_dhcp_client = true;
-          ifp->enable_dhcp_server = false;
         } // else manually start AP as below
       }
       break;
@@ -158,13 +147,13 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
     case READY:
       // go back to AP mode after a disconnection (simulation 2/2), you could retry
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-        bool res = mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+        bool res = mg_wifi_ap_start(wifi);
         MG_INFO(("Disconnected"));
         MG_INFO(("Manually starting AP: %s", res ? "OK":"FAIL"));
         if (res) {
           state = AP;
-          d->apmode = true;
+          wifi->apmode = true;
         }
       }
       break;
@@ -173,14 +162,16 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
 
 
 static struct mg_tcpip_driver_cyw_data d = {
-  (struct mg_tcpip_spi_ *)&spi, (struct mg_tcpip_driver_cyw_firmware *)&fw, WIFI_SSID, WIFI_PASS, "mongoose", "mongoose", 0, 0, 10, true, false};
+  {WIFI_SSID, WIFI_PASS, "mongoose", "mongoose", 0, 0, 0, 0, 10, true}, (struct mg_tcpip_spi_ *)&spi, (struct mg_tcpip_driver_cyw_firmware *)&fw, false};
 
 int main(void) {
   uart_init(UART_DEBUG, 115200);  // Initialise debug printf
 
   hwspecific_spi_init();
 
-  state = d.apmode ? AP : CONNECTING;
+  d.wifi.apip = MG_IPV4(192, 168, 169, 1),
+  d.wifi.apmask = MG_IPV4(255, 255, 255, 0),
+  state = d.wifi.apmode ? AP : CONNECTING;
 
   struct mg_mgr mgr;        // Initialise Mongoose event manager
   mg_mgr_init(&mgr);        // and attach it to the interface
diff --git a/tutorials/stm32/rm2-nucleo-f746zg-make-baremetal-builtin/main.c b/tutorials/stm32/rm2-nucleo-f746zg-make-baremetal-builtin/main.c
index ffa38ad265..d92cca260d 100644
--- a/tutorials/stm32/rm2-nucleo-f746zg-make-baremetal-builtin/main.c
+++ b/tutorials/stm32/rm2-nucleo-f746zg-make-baremetal-builtin/main.c
@@ -81,7 +81,6 @@ static const struct mg_tcpip_driver_cyw_firmware fw = {
 // mif user states
 enum {AP, SCANNING, STOPPING_AP, CONNECTING, READY};
 static unsigned int state;
-static uint32_t s_ip, s_mask;
 
 
 static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
@@ -95,13 +94,7 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
   }
   switch(state) {
     case AP: // we are in AP mode, wait for a user connection to trigger a scan or a connection to a network
-      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
-        MG_INFO(("Access Point started"));
-        s_ip = ifp->ip, ifp->ip = MG_IPV4(192, 168, 169, 1);
-        s_mask = ifp->mask, ifp->mask = MG_IPV4(255, 255, 255, 0);
-        ifp->enable_dhcp_client = false;
-        ifp->enable_dhcp_server = true;
-      } else if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
+      if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
         MG_INFO(("Access Point READY !"));
 
         // simulate user request to scan for networks
@@ -115,7 +108,7 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
         struct mg_wifi_scan_bss_data *bss = (struct mg_wifi_scan_bss_data *) ev_data;
         MG_INFO(("BSS: %.*s (%u) (%M) %d dBm %u", bss->SSID.len, bss->SSID.buf, bss->channel, mg_print_mac, bss->BSSID, (int) bss->RSSI, bss->security));
       } else if (ev == MG_TCPIP_EV_WIFI_SCAN_END) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
+        //struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
         MG_INFO(("Wi-Fi scan finished"));
 
         // simulate user selection of a network (1/2: stop AP)
@@ -127,18 +120,14 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
       break;
     case STOPPING_AP:
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-        d->apmode = false;
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+        wifi->apmode = false;
 
         // simulate user selection of a network (2/2: actual connect)
-        bool res = mg_wifi_connect(d->ssid, d->pass);
+        bool res = mg_wifi_connect(wifi);
         MG_INFO(("Manually connecting: %s", res ? "OK":"FAIL"));
         if (res) {
           state = CONNECTING;
-          ifp->ip = s_ip;
-          ifp->mask = s_mask;
-          if (ifp->ip == 0) ifp->enable_dhcp_client = true;
-          ifp->enable_dhcp_server = false;
         } // else manually start AP as below
       }
       break;
@@ -158,13 +147,13 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
     case READY:
       // go back to AP mode after a disconnection (simulation 2/2), you could retry
       if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
-        struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-        bool res = mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
+        struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+        bool res = mg_wifi_ap_start(wifi);
         MG_INFO(("Disconnected"));
         MG_INFO(("Manually starting AP: %s", res ? "OK":"FAIL"));
         if (res) {
           state = AP;
-          d->apmode = true;
+          wifi->apmode = true;
         }
       }
       break;
@@ -173,14 +162,16 @@ static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
 
 
 static struct mg_tcpip_driver_cyw_data d = {
-  (struct mg_tcpip_spi_ *)&spi, (struct mg_tcpip_driver_cyw_firmware *)&fw, WIFI_SSID, WIFI_PASS, "mongoose", "mongoose", 0, 0, 10, true, false};
+  {WIFI_SSID, WIFI_PASS, "mongoose", "mongoose", 0, 0, 0, 0, 10, true}, (struct mg_tcpip_spi_ *)&spi, (struct mg_tcpip_driver_cyw_firmware *)&fw, false};
 
 int main(void) {
   uart_init(UART_DEBUG, 115200);  // Initialise debug printf
 
   hwspecific_spi_init();
 
-  state = d.apmode ? AP : CONNECTING;
+  d.wifi.apip = MG_IPV4(192, 168, 169, 1),
+  d.wifi.apmask = MG_IPV4(255, 255, 255, 0),
+  state = d.wifi.apmode ? AP : CONNECTING;
 
   struct mg_mgr mgr;        // Initialise Mongoose event manager
   mg_mgr_init(&mgr);        // and attach it to the interface